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SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/channel_v1_00_a/hdl/vhdl/channel.vhd | 1 | 17,272 | ------------------------------------------------------------------------------
-- channel.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: channel.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 29 16:59:20 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library channel_v1_00_a;
use channel_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity channel is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
Channel_Left_in : in std_logic_vector(23 downto 0);
Channel_Right_in : in std_logic_vector(23 downto 0);
Channel_Left_out : out std_logic_vector(23 downto 0);
Channel_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity channel;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of channel is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity channel_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
Channel_Left_in => Channel_Left_in,
Channel_Right_in => Channel_Right_in,
Channel_Left_out => Channel_Left_out,
Channel_Right_out => Channel_Right_out,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | d6f11305efe85b65383f951614fab397 | 0.459588 | 4.14296 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 4,182 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Thu Mar 10 15:45:23 2016
--Host : minmi running 64-bit elementary OS Freya
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
sw0 : in STD_LOGIC;
sw1 : in STD_LOGIC;
sw2 : in STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_out_en : out STD_LOGIC;
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
sw0 : in STD_LOGIC;
sw1 : in STD_LOGIC;
sw2 : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en,
sw0 => sw0,
sw1 => sw1,
sw2 => sw2,
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0)
);
end STRUCTURE;
| mit | 6ad3c266fada5df2c6bb938e22c762bd | 0.582736 | 3.068232 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/synth/system_vga_gaussian_blur_0_0.vhd | 1 | 5,235 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_0_0 IS
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_0_0;
ARCHITECTURE system_vga_gaussian_blur_0_0_arch OF system_vga_gaussian_blur_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "vga_gaussian_blur,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_gaussian_blur_0_0_arch : ARCHITECTURE IS "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_gaussian_blur,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_DELAY=160,KERNEL=3}";
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
en => en,
clk_25 => clk_25,
active_in => active_in,
hsync_in => hsync_in,
vsync_in => vsync_in,
xaddr_in => xaddr_in,
yaddr_in => yaddr_in,
rgb_in => rgb_in,
active_out => active_out,
hsync_out => hsync_out,
vsync_out => vsync_out,
xaddr_out => xaddr_out,
yaddr_out => yaddr_out,
rgb_out => rgb_out
);
END system_vga_gaussian_blur_0_0_arch;
| mit | 714d9fab4411c00f880976598a2f1d61 | 0.698185 | 3.487675 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 17,433 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Thu Jun 01 11:34:27 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
clk_100 : in STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync_0 : in STD_LOGIC;
hsync_1 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
ready_0 : out STD_LOGIC;
ready_1 : out STD_LOGIC;
reset : in STD_LOGIC;
sioc_0 : out STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
siod_1 : inout STD_LOGIC;
vsync_0 : in STD_LOGIC;
vsync_1 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=19,numReposBlks=19,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_0_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_reset_0_0;
component system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_0_0;
component system_vga_sync_ref_1_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_1_0;
component system_vga_buffer_1_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_1_0;
component system_rgb565_to_rgb888_1_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_1_0;
component system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_1_0;
component system_util_vector_logic_0_0 is
port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_util_vector_logic_0_0;
component system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_0_0;
component system_clock_splitter_1_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_1_0;
component system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_ov7670_vga_1_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_1_0;
component system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_overlay_0_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal Net2 : STD_LOGIC;
signal clk_100_1 : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clock_splitter_0_clk_out : STD_LOGIC;
signal clock_splitter_1_clk_out : STD_LOGIC;
signal \^data_1\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal data_1_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^hsync_1\ : STD_LOGIC;
signal hsync_1_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_controller_1_config_finished : STD_LOGIC;
signal ov7670_controller_1_sioc : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal ov7670_vga_1_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^pclk_1\ : STD_LOGIC;
signal pclk_1_1 : STD_LOGIC;
signal resend_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb565_to_rgb888_1_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_buffer_0_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_buffer_1_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_overlay_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_pll_0_clk_12_6 : STD_LOGIC;
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_sync_ref_0_active : STD_LOGIC;
signal vga_sync_ref_0_start : STD_LOGIC;
signal vga_sync_ref_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_1_active : STD_LOGIC;
signal vga_sync_ref_1_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_1_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_active : STD_LOGIC;
signal vga_sync_reset_0_hsync : STD_LOGIC;
signal vga_sync_reset_0_vsync : STD_LOGIC;
signal vga_sync_reset_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^vsync_1\ : STD_LOGIC;
signal vsync_1_1 : STD_LOGIC;
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_1_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_1_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_1_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_50_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
signal NLW_vga_sync_ref_1_start_UNCONNECTED : STD_LOGIC;
begin
\^data_1\(7 downto 0) <= data_0(7 downto 0);
\^hsync_1\ <= hsync_0;
\^pclk_1\ <= pclk_0;
\^vsync_1\ <= vsync_0;
clk_100_1 <= clk_100;
data_1_1(7 downto 0) <= data_1(7 downto 0);
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
hsync_1_1 <= hsync_1;
pclk_1_1 <= pclk_1;
ready_0 <= ov7670_controller_0_config_finished;
ready_1 <= ov7670_controller_1_config_finished;
resend_1 <= reset;
sioc_0 <= ov7670_controller_0_sioc;
sioc_1 <= ov7670_controller_1_sioc;
vsync_1_1 <= vsync_1;
xclk_0 <= clk_wiz_0_clk_out1;
xclk_1 <= clk_wiz_0_clk_out1;
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED
);
clock_splitter_0: component system_clock_splitter_0_0
port map (
clk_in => \^pclk_1\,
clk_out => clock_splitter_0_clk_out,
latch_edge => \^vsync_1\
);
clock_splitter_1: component system_clock_splitter_1_0
port map (
clk_in => pclk_1_1,
clk_out => clock_splitter_1_clk_out,
latch_edge => vsync_1_1
);
inverter_0: component system_inverter_0_0
port map (
x => vga_sync_ref_0_start,
x_not => inverter_0_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => vga_pll_0_clk_25,
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => resend_1,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => siod_0,
xclk => NLW_ov7670_controller_0_xclk_UNCONNECTED
);
ov7670_controller_1: component system_ov7670_controller_1_0
port map (
clk => vga_pll_0_clk_25,
config_finished => ov7670_controller_1_config_finished,
pwdn => NLW_ov7670_controller_1_pwdn_UNCONNECTED,
resend => resend_1,
reset => NLW_ov7670_controller_1_reset_UNCONNECTED,
sioc => ov7670_controller_1_sioc,
siod => siod_1,
xclk => NLW_ov7670_controller_1_xclk_UNCONNECTED
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
active => vga_sync_ref_0_active,
clk_x2 => \^pclk_1\,
data(7 downto 0) => \^data_1\(7 downto 0),
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
ov7670_vga_1: component system_ov7670_vga_1_0
port map (
active => vga_sync_ref_1_active,
clk_x2 => pclk_1_1,
data(7 downto 0) => data_1_1(7 downto 0),
rgb(15 downto 0) => ov7670_vga_1_rgb(15 downto 0)
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
clk => clock_splitter_0_clk_out,
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb565_to_rgb888_1: component system_rgb565_to_rgb888_1_0
port map (
clk => clock_splitter_1_clk_out,
rgb_565(15 downto 0) => ov7670_vga_1_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_1_rgb_888(23 downto 0)
);
util_vector_logic_0: component system_util_vector_logic_0_0
port map (
Op1(0) => ov7670_controller_1_config_finished,
Op2(0) => ov7670_controller_0_config_finished,
Res(0) => util_vector_logic_0_Res(0)
);
vga_buffer_0: component system_vga_buffer_0_0
port map (
clk_r => vga_pll_0_clk_12_6,
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_buffer_1: component system_vga_buffer_1_0
port map (
clk_r => vga_pll_0_clk_12_6,
clk_w => clock_splitter_1_clk_out,
data_r(23 downto 0) => vga_buffer_1_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_1_rgb_888(23 downto 0),
wen => vga_sync_ref_1_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_1_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_1_yaddr(9 downto 0)
);
vga_overlay_0: component system_vga_overlay_0_0
port map (
clk => vga_pll_0_clk_25,
rgb(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
rgb_0(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
rgb_1(23 downto 0) => vga_buffer_1_data_r(23 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => vga_pll_0_clk_12_6,
clk_25 => vga_pll_0_clk_25,
clk_50 => NLW_vga_pll_0_clk_50_UNCONNECTED,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_ref_0: component system_vga_sync_ref_0_0
port map (
active => vga_sync_ref_0_active,
clk => clock_splitter_0_clk_out,
hsync => \^hsync_1\,
rst => util_vector_logic_0_Res(0),
start => vga_sync_ref_0_start,
vsync => \^vsync_1\,
xaddr(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_sync_ref_1: component system_vga_sync_ref_1_0
port map (
active => vga_sync_ref_1_active,
clk => clock_splitter_1_clk_out,
hsync => hsync_1_1,
rst => util_vector_logic_0_Res(0),
start => NLW_vga_sync_ref_1_start_UNCONNECTED,
vsync => vsync_1_1,
xaddr(9 downto 0) => vga_sync_ref_1_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_1_yaddr(9 downto 0)
);
vga_sync_reset_0: component system_vga_sync_reset_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
hsync => vga_sync_reset_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_reset_0_vsync,
xaddr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
clk_100 => clk_100_1,
clk_x2 => vga_pll_0_clk_25,
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_reset_0_hsync,
rgb888(23 downto 0) => vga_overlay_0_rgb(23 downto 0),
vsync => vga_sync_reset_0_vsync
);
end STRUCTURE;
| mit | 50c876e69290b47e42a4841ead418ed6 | 0.627201 | 2.915705 | false | false | false | false |
olofk/libstorage | rtl/vhdl/suv/fifo_fwft_generic.vhd | 1 | 2,607 | --
-- First Word Fall Through FIFO. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.std_logic_1164.all;
library libstorage_1;
entity fifo_fwft_generic is
generic (
DEPTH : positive;
FWFT : boolean := false);
port (
clk : in std_ulogic;
rst : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out std_ulogic_vector;
full_o : out std_ulogic;
wr_en_i : in std_ulogic;
wr_data_i : in std_ulogic_vector;
empty_o : out std_ulogic);
end entity fifo_fwft_generic;
architecture str of fifo_fwft_generic is
--FWFT signals
signal fifo_rd_data : std_ulogic_vector(wr_data_i'range);
signal fifo_rd_en : std_ulogic;
signal fifo_empty : std_ulogic;
signal fwft_rd_data : std_ulogic_vector(wr_data_i'range);
signal fwft_rd_en : std_ulogic;
signal fwft_empty : std_ulogic;
begin
fifo_rd_en <= fwft_rd_en when FWFT else rd_en_i;
rd_data_o <= fwft_rd_data when FWFT else fifo_rd_data;
empty_o <= fwft_empty when FWFT else fifo_empty;
fifo : entity libstorage_1.fifo_generic
generic map (
DEPTH => DEPTH)
port map (
clk => clk,
rst => rst,
rd_en_i => fifo_rd_en,
rd_data_o => fifo_rd_data,
empty_o => fifo_empty,
wr_en_i => wr_en_i,
wr_data_i => wr_data_i,
full_o => full_o);
gen_fwft: if FWFT generate
fifo_fwft_adapter: entity libstorage_1.fifo_fwft_adapter
port map (
clk => clk,
rst => rst,
fifo_rd_en_o => fwft_rd_en,
fifo_rd_data_i => fifo_rd_data,
fifo_empty_i => fifo_empty,
rd_en_i => rd_en_i,
rd_data_o => fwft_rd_data,
empty_o => fwft_empty);
end generate gen_fwft;
end architecture str;
| isc | a7a2b4954bf7b2318169b2d19ad42a6c | 0.631377 | 3.3509 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/sim/system_vga_sync_reset_0_0.vhd | 3 | 4,160 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_reset:1.0
-- IP Revision: 25
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_reset_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_reset_0_0;
ARCHITECTURE system_vga_sync_reset_0_0_arch OF system_vga_sync_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_reset IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_reset
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_reset_0_0_arch;
| mit | 93179d62ee9427cb541500f7f9257f8f | 0.694712 | 3.851852 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_transform_0_0/system_vga_transform_0_0_sim_netlist.vhdl | 1 | 143,637 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:45:59 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_transform_0_0/system_vga_transform_0_0_sim_netlist.vhdl
-- Design : system_vga_transform_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_transform_0_0_vga_transform is
port (
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
enable : in STD_LOGIC;
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_transform_0_0_vga_transform : entity is "vga_transform";
end system_vga_transform_0_0_vga_transform;
architecture STRUCTURE of system_vga_transform_0_0_vga_transform is
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 23 downto 14 );
signal x_addr_out0 : STD_LOGIC_VECTOR ( 23 downto 14 );
signal \x_addr_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_1\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_2\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_3\ : STD_LOGIC;
signal \x_addr_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__1_n_3\ : STD_LOGIC;
signal x_addr_out0_carry_i_1_n_0 : STD_LOGIC;
signal x_addr_out0_carry_i_2_n_0 : STD_LOGIC;
signal x_addr_out0_carry_i_3_n_0 : STD_LOGIC;
signal x_addr_out0_carry_n_0 : STD_LOGIC;
signal x_addr_out0_carry_n_1 : STD_LOGIC;
signal x_addr_out0_carry_n_2 : STD_LOGIC;
signal x_addr_out0_carry_n_3 : STD_LOGIC;
signal \x_addr_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__8_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__8_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__8_n_3\ : STD_LOGIC;
signal x_addr_out2_carry_i_1_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_2_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_3_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_4_n_0 : STD_LOGIC;
signal x_addr_out2_carry_n_0 : STD_LOGIC;
signal x_addr_out2_carry_n_1 : STD_LOGIC;
signal x_addr_out2_carry_n_2 : STD_LOGIC;
signal x_addr_out2_carry_n_3 : STD_LOGIC;
signal \x_addr_out3__0_n_100\ : STD_LOGIC;
signal \x_addr_out3__0_n_101\ : STD_LOGIC;
signal \x_addr_out3__0_n_102\ : STD_LOGIC;
signal \x_addr_out3__0_n_103\ : STD_LOGIC;
signal \x_addr_out3__0_n_104\ : STD_LOGIC;
signal \x_addr_out3__0_n_105\ : STD_LOGIC;
signal \x_addr_out3__0_n_58\ : STD_LOGIC;
signal \x_addr_out3__0_n_59\ : STD_LOGIC;
signal \x_addr_out3__0_n_60\ : STD_LOGIC;
signal \x_addr_out3__0_n_61\ : STD_LOGIC;
signal \x_addr_out3__0_n_62\ : STD_LOGIC;
signal \x_addr_out3__0_n_63\ : STD_LOGIC;
signal \x_addr_out3__0_n_64\ : STD_LOGIC;
signal \x_addr_out3__0_n_65\ : STD_LOGIC;
signal \x_addr_out3__0_n_66\ : STD_LOGIC;
signal \x_addr_out3__0_n_67\ : STD_LOGIC;
signal \x_addr_out3__0_n_68\ : STD_LOGIC;
signal \x_addr_out3__0_n_69\ : STD_LOGIC;
signal \x_addr_out3__0_n_70\ : STD_LOGIC;
signal \x_addr_out3__0_n_71\ : STD_LOGIC;
signal \x_addr_out3__0_n_72\ : STD_LOGIC;
signal \x_addr_out3__0_n_73\ : STD_LOGIC;
signal \x_addr_out3__0_n_74\ : STD_LOGIC;
signal \x_addr_out3__0_n_75\ : STD_LOGIC;
signal \x_addr_out3__0_n_76\ : STD_LOGIC;
signal \x_addr_out3__0_n_77\ : STD_LOGIC;
signal \x_addr_out3__0_n_78\ : STD_LOGIC;
signal \x_addr_out3__0_n_79\ : STD_LOGIC;
signal \x_addr_out3__0_n_80\ : STD_LOGIC;
signal \x_addr_out3__0_n_81\ : STD_LOGIC;
signal \x_addr_out3__0_n_82\ : STD_LOGIC;
signal \x_addr_out3__0_n_83\ : STD_LOGIC;
signal \x_addr_out3__0_n_84\ : STD_LOGIC;
signal \x_addr_out3__0_n_85\ : STD_LOGIC;
signal \x_addr_out3__0_n_86\ : STD_LOGIC;
signal \x_addr_out3__0_n_87\ : STD_LOGIC;
signal \x_addr_out3__0_n_88\ : STD_LOGIC;
signal \x_addr_out3__0_n_89\ : STD_LOGIC;
signal \x_addr_out3__0_n_90\ : STD_LOGIC;
signal \x_addr_out3__0_n_91\ : STD_LOGIC;
signal \x_addr_out3__0_n_92\ : STD_LOGIC;
signal \x_addr_out3__0_n_93\ : STD_LOGIC;
signal \x_addr_out3__0_n_94\ : STD_LOGIC;
signal \x_addr_out3__0_n_95\ : STD_LOGIC;
signal \x_addr_out3__0_n_96\ : STD_LOGIC;
signal \x_addr_out3__0_n_97\ : STD_LOGIC;
signal \x_addr_out3__0_n_98\ : STD_LOGIC;
signal \x_addr_out3__0_n_99\ : STD_LOGIC;
signal \x_addr_out3__1_n_100\ : STD_LOGIC;
signal \x_addr_out3__1_n_101\ : STD_LOGIC;
signal \x_addr_out3__1_n_102\ : STD_LOGIC;
signal \x_addr_out3__1_n_103\ : STD_LOGIC;
signal \x_addr_out3__1_n_104\ : STD_LOGIC;
signal \x_addr_out3__1_n_105\ : STD_LOGIC;
signal \x_addr_out3__1_n_106\ : STD_LOGIC;
signal \x_addr_out3__1_n_107\ : STD_LOGIC;
signal \x_addr_out3__1_n_108\ : STD_LOGIC;
signal \x_addr_out3__1_n_109\ : STD_LOGIC;
signal \x_addr_out3__1_n_110\ : STD_LOGIC;
signal \x_addr_out3__1_n_111\ : STD_LOGIC;
signal \x_addr_out3__1_n_112\ : STD_LOGIC;
signal \x_addr_out3__1_n_113\ : STD_LOGIC;
signal \x_addr_out3__1_n_114\ : STD_LOGIC;
signal \x_addr_out3__1_n_115\ : STD_LOGIC;
signal \x_addr_out3__1_n_116\ : STD_LOGIC;
signal \x_addr_out3__1_n_117\ : STD_LOGIC;
signal \x_addr_out3__1_n_118\ : STD_LOGIC;
signal \x_addr_out3__1_n_119\ : STD_LOGIC;
signal \x_addr_out3__1_n_120\ : STD_LOGIC;
signal \x_addr_out3__1_n_121\ : STD_LOGIC;
signal \x_addr_out3__1_n_122\ : STD_LOGIC;
signal \x_addr_out3__1_n_123\ : STD_LOGIC;
signal \x_addr_out3__1_n_124\ : STD_LOGIC;
signal \x_addr_out3__1_n_125\ : STD_LOGIC;
signal \x_addr_out3__1_n_126\ : STD_LOGIC;
signal \x_addr_out3__1_n_127\ : STD_LOGIC;
signal \x_addr_out3__1_n_128\ : STD_LOGIC;
signal \x_addr_out3__1_n_129\ : STD_LOGIC;
signal \x_addr_out3__1_n_130\ : STD_LOGIC;
signal \x_addr_out3__1_n_131\ : STD_LOGIC;
signal \x_addr_out3__1_n_132\ : STD_LOGIC;
signal \x_addr_out3__1_n_133\ : STD_LOGIC;
signal \x_addr_out3__1_n_134\ : STD_LOGIC;
signal \x_addr_out3__1_n_135\ : STD_LOGIC;
signal \x_addr_out3__1_n_136\ : STD_LOGIC;
signal \x_addr_out3__1_n_137\ : STD_LOGIC;
signal \x_addr_out3__1_n_138\ : STD_LOGIC;
signal \x_addr_out3__1_n_139\ : STD_LOGIC;
signal \x_addr_out3__1_n_140\ : STD_LOGIC;
signal \x_addr_out3__1_n_141\ : STD_LOGIC;
signal \x_addr_out3__1_n_142\ : STD_LOGIC;
signal \x_addr_out3__1_n_143\ : STD_LOGIC;
signal \x_addr_out3__1_n_144\ : STD_LOGIC;
signal \x_addr_out3__1_n_145\ : STD_LOGIC;
signal \x_addr_out3__1_n_146\ : STD_LOGIC;
signal \x_addr_out3__1_n_147\ : STD_LOGIC;
signal \x_addr_out3__1_n_148\ : STD_LOGIC;
signal \x_addr_out3__1_n_149\ : STD_LOGIC;
signal \x_addr_out3__1_n_150\ : STD_LOGIC;
signal \x_addr_out3__1_n_151\ : STD_LOGIC;
signal \x_addr_out3__1_n_152\ : STD_LOGIC;
signal \x_addr_out3__1_n_153\ : STD_LOGIC;
signal \x_addr_out3__1_n_58\ : STD_LOGIC;
signal \x_addr_out3__1_n_59\ : STD_LOGIC;
signal \x_addr_out3__1_n_60\ : STD_LOGIC;
signal \x_addr_out3__1_n_61\ : STD_LOGIC;
signal \x_addr_out3__1_n_62\ : STD_LOGIC;
signal \x_addr_out3__1_n_63\ : STD_LOGIC;
signal \x_addr_out3__1_n_64\ : STD_LOGIC;
signal \x_addr_out3__1_n_65\ : STD_LOGIC;
signal \x_addr_out3__1_n_66\ : STD_LOGIC;
signal \x_addr_out3__1_n_67\ : STD_LOGIC;
signal \x_addr_out3__1_n_68\ : STD_LOGIC;
signal \x_addr_out3__1_n_69\ : STD_LOGIC;
signal \x_addr_out3__1_n_70\ : STD_LOGIC;
signal \x_addr_out3__1_n_71\ : STD_LOGIC;
signal \x_addr_out3__1_n_72\ : STD_LOGIC;
signal \x_addr_out3__1_n_73\ : STD_LOGIC;
signal \x_addr_out3__1_n_74\ : STD_LOGIC;
signal \x_addr_out3__1_n_75\ : STD_LOGIC;
signal \x_addr_out3__1_n_76\ : STD_LOGIC;
signal \x_addr_out3__1_n_77\ : STD_LOGIC;
signal \x_addr_out3__1_n_78\ : STD_LOGIC;
signal \x_addr_out3__1_n_79\ : STD_LOGIC;
signal \x_addr_out3__1_n_80\ : STD_LOGIC;
signal \x_addr_out3__1_n_81\ : STD_LOGIC;
signal \x_addr_out3__1_n_82\ : STD_LOGIC;
signal \x_addr_out3__1_n_83\ : STD_LOGIC;
signal \x_addr_out3__1_n_84\ : STD_LOGIC;
signal \x_addr_out3__1_n_85\ : STD_LOGIC;
signal \x_addr_out3__1_n_86\ : STD_LOGIC;
signal \x_addr_out3__1_n_87\ : STD_LOGIC;
signal \x_addr_out3__1_n_88\ : STD_LOGIC;
signal \x_addr_out3__1_n_89\ : STD_LOGIC;
signal \x_addr_out3__1_n_90\ : STD_LOGIC;
signal \x_addr_out3__1_n_91\ : STD_LOGIC;
signal \x_addr_out3__1_n_92\ : STD_LOGIC;
signal \x_addr_out3__1_n_93\ : STD_LOGIC;
signal \x_addr_out3__1_n_94\ : STD_LOGIC;
signal \x_addr_out3__1_n_95\ : STD_LOGIC;
signal \x_addr_out3__1_n_96\ : STD_LOGIC;
signal \x_addr_out3__1_n_97\ : STD_LOGIC;
signal \x_addr_out3__1_n_98\ : STD_LOGIC;
signal \x_addr_out3__1_n_99\ : STD_LOGIC;
signal \x_addr_out3__2_n_100\ : STD_LOGIC;
signal \x_addr_out3__2_n_101\ : STD_LOGIC;
signal \x_addr_out3__2_n_102\ : STD_LOGIC;
signal \x_addr_out3__2_n_103\ : STD_LOGIC;
signal \x_addr_out3__2_n_104\ : STD_LOGIC;
signal \x_addr_out3__2_n_105\ : STD_LOGIC;
signal \x_addr_out3__2_n_58\ : STD_LOGIC;
signal \x_addr_out3__2_n_59\ : STD_LOGIC;
signal \x_addr_out3__2_n_60\ : STD_LOGIC;
signal \x_addr_out3__2_n_61\ : STD_LOGIC;
signal \x_addr_out3__2_n_62\ : STD_LOGIC;
signal \x_addr_out3__2_n_63\ : STD_LOGIC;
signal \x_addr_out3__2_n_64\ : STD_LOGIC;
signal \x_addr_out3__2_n_65\ : STD_LOGIC;
signal \x_addr_out3__2_n_66\ : STD_LOGIC;
signal \x_addr_out3__2_n_67\ : STD_LOGIC;
signal \x_addr_out3__2_n_68\ : STD_LOGIC;
signal \x_addr_out3__2_n_69\ : STD_LOGIC;
signal \x_addr_out3__2_n_70\ : STD_LOGIC;
signal \x_addr_out3__2_n_71\ : STD_LOGIC;
signal \x_addr_out3__2_n_72\ : STD_LOGIC;
signal \x_addr_out3__2_n_73\ : STD_LOGIC;
signal \x_addr_out3__2_n_74\ : STD_LOGIC;
signal \x_addr_out3__2_n_75\ : STD_LOGIC;
signal \x_addr_out3__2_n_76\ : STD_LOGIC;
signal \x_addr_out3__2_n_77\ : STD_LOGIC;
signal \x_addr_out3__2_n_78\ : STD_LOGIC;
signal \x_addr_out3__2_n_79\ : STD_LOGIC;
signal \x_addr_out3__2_n_80\ : STD_LOGIC;
signal \x_addr_out3__2_n_81\ : STD_LOGIC;
signal \x_addr_out3__2_n_82\ : STD_LOGIC;
signal \x_addr_out3__2_n_83\ : STD_LOGIC;
signal \x_addr_out3__2_n_84\ : STD_LOGIC;
signal \x_addr_out3__2_n_85\ : STD_LOGIC;
signal \x_addr_out3__2_n_86\ : STD_LOGIC;
signal \x_addr_out3__2_n_87\ : STD_LOGIC;
signal \x_addr_out3__2_n_88\ : STD_LOGIC;
signal \x_addr_out3__2_n_89\ : STD_LOGIC;
signal \x_addr_out3__2_n_90\ : STD_LOGIC;
signal \x_addr_out3__2_n_91\ : STD_LOGIC;
signal \x_addr_out3__2_n_92\ : STD_LOGIC;
signal \x_addr_out3__2_n_93\ : STD_LOGIC;
signal \x_addr_out3__2_n_94\ : STD_LOGIC;
signal \x_addr_out3__2_n_95\ : STD_LOGIC;
signal \x_addr_out3__2_n_96\ : STD_LOGIC;
signal \x_addr_out3__2_n_97\ : STD_LOGIC;
signal \x_addr_out3__2_n_98\ : STD_LOGIC;
signal \x_addr_out3__2_n_99\ : STD_LOGIC;
signal x_addr_out3_n_100 : STD_LOGIC;
signal x_addr_out3_n_101 : STD_LOGIC;
signal x_addr_out3_n_102 : STD_LOGIC;
signal x_addr_out3_n_103 : STD_LOGIC;
signal x_addr_out3_n_104 : STD_LOGIC;
signal x_addr_out3_n_105 : STD_LOGIC;
signal x_addr_out3_n_106 : STD_LOGIC;
signal x_addr_out3_n_107 : STD_LOGIC;
signal x_addr_out3_n_108 : STD_LOGIC;
signal x_addr_out3_n_109 : STD_LOGIC;
signal x_addr_out3_n_110 : STD_LOGIC;
signal x_addr_out3_n_111 : STD_LOGIC;
signal x_addr_out3_n_112 : STD_LOGIC;
signal x_addr_out3_n_113 : STD_LOGIC;
signal x_addr_out3_n_114 : STD_LOGIC;
signal x_addr_out3_n_115 : STD_LOGIC;
signal x_addr_out3_n_116 : STD_LOGIC;
signal x_addr_out3_n_117 : STD_LOGIC;
signal x_addr_out3_n_118 : STD_LOGIC;
signal x_addr_out3_n_119 : STD_LOGIC;
signal x_addr_out3_n_120 : STD_LOGIC;
signal x_addr_out3_n_121 : STD_LOGIC;
signal x_addr_out3_n_122 : STD_LOGIC;
signal x_addr_out3_n_123 : STD_LOGIC;
signal x_addr_out3_n_124 : STD_LOGIC;
signal x_addr_out3_n_125 : STD_LOGIC;
signal x_addr_out3_n_126 : STD_LOGIC;
signal x_addr_out3_n_127 : STD_LOGIC;
signal x_addr_out3_n_128 : STD_LOGIC;
signal x_addr_out3_n_129 : STD_LOGIC;
signal x_addr_out3_n_130 : STD_LOGIC;
signal x_addr_out3_n_131 : STD_LOGIC;
signal x_addr_out3_n_132 : STD_LOGIC;
signal x_addr_out3_n_133 : STD_LOGIC;
signal x_addr_out3_n_134 : STD_LOGIC;
signal x_addr_out3_n_135 : STD_LOGIC;
signal x_addr_out3_n_136 : STD_LOGIC;
signal x_addr_out3_n_137 : STD_LOGIC;
signal x_addr_out3_n_138 : STD_LOGIC;
signal x_addr_out3_n_139 : STD_LOGIC;
signal x_addr_out3_n_140 : STD_LOGIC;
signal x_addr_out3_n_141 : STD_LOGIC;
signal x_addr_out3_n_142 : STD_LOGIC;
signal x_addr_out3_n_143 : STD_LOGIC;
signal x_addr_out3_n_144 : STD_LOGIC;
signal x_addr_out3_n_145 : STD_LOGIC;
signal x_addr_out3_n_146 : STD_LOGIC;
signal x_addr_out3_n_147 : STD_LOGIC;
signal x_addr_out3_n_148 : STD_LOGIC;
signal x_addr_out3_n_149 : STD_LOGIC;
signal x_addr_out3_n_150 : STD_LOGIC;
signal x_addr_out3_n_151 : STD_LOGIC;
signal x_addr_out3_n_152 : STD_LOGIC;
signal x_addr_out3_n_153 : STD_LOGIC;
signal x_addr_out3_n_58 : STD_LOGIC;
signal x_addr_out3_n_59 : STD_LOGIC;
signal x_addr_out3_n_60 : STD_LOGIC;
signal x_addr_out3_n_61 : STD_LOGIC;
signal x_addr_out3_n_62 : STD_LOGIC;
signal x_addr_out3_n_63 : STD_LOGIC;
signal x_addr_out3_n_64 : STD_LOGIC;
signal x_addr_out3_n_65 : STD_LOGIC;
signal x_addr_out3_n_66 : STD_LOGIC;
signal x_addr_out3_n_67 : STD_LOGIC;
signal x_addr_out3_n_68 : STD_LOGIC;
signal x_addr_out3_n_69 : STD_LOGIC;
signal x_addr_out3_n_70 : STD_LOGIC;
signal x_addr_out3_n_71 : STD_LOGIC;
signal x_addr_out3_n_72 : STD_LOGIC;
signal x_addr_out3_n_73 : STD_LOGIC;
signal x_addr_out3_n_74 : STD_LOGIC;
signal x_addr_out3_n_75 : STD_LOGIC;
signal x_addr_out3_n_76 : STD_LOGIC;
signal x_addr_out3_n_77 : STD_LOGIC;
signal x_addr_out3_n_78 : STD_LOGIC;
signal x_addr_out3_n_79 : STD_LOGIC;
signal x_addr_out3_n_80 : STD_LOGIC;
signal x_addr_out3_n_81 : STD_LOGIC;
signal x_addr_out3_n_82 : STD_LOGIC;
signal x_addr_out3_n_83 : STD_LOGIC;
signal x_addr_out3_n_84 : STD_LOGIC;
signal x_addr_out3_n_85 : STD_LOGIC;
signal x_addr_out3_n_86 : STD_LOGIC;
signal x_addr_out3_n_87 : STD_LOGIC;
signal x_addr_out3_n_88 : STD_LOGIC;
signal x_addr_out3_n_89 : STD_LOGIC;
signal x_addr_out3_n_90 : STD_LOGIC;
signal x_addr_out3_n_91 : STD_LOGIC;
signal x_addr_out3_n_92 : STD_LOGIC;
signal x_addr_out3_n_93 : STD_LOGIC;
signal x_addr_out3_n_94 : STD_LOGIC;
signal x_addr_out3_n_95 : STD_LOGIC;
signal x_addr_out3_n_96 : STD_LOGIC;
signal x_addr_out3_n_97 : STD_LOGIC;
signal x_addr_out3_n_98 : STD_LOGIC;
signal x_addr_out3_n_99 : STD_LOGIC;
signal \x_addr_out[0]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_1\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_2\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_3\ : STD_LOGIC;
signal \y_addr_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__1_n_3\ : STD_LOGIC;
signal y_addr_out0_carry_i_1_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_2_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_3_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_4_n_0 : STD_LOGIC;
signal y_addr_out0_carry_n_0 : STD_LOGIC;
signal y_addr_out0_carry_n_1 : STD_LOGIC;
signal y_addr_out0_carry_n_2 : STD_LOGIC;
signal y_addr_out0_carry_n_3 : STD_LOGIC;
signal y_addr_out2 : STD_LOGIC_VECTOR ( 37 downto 28 );
signal \y_addr_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__8_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__8_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__8_n_3\ : STD_LOGIC;
signal y_addr_out2_carry_i_1_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_2_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_3_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_4_n_0 : STD_LOGIC;
signal y_addr_out2_carry_n_0 : STD_LOGIC;
signal y_addr_out2_carry_n_1 : STD_LOGIC;
signal y_addr_out2_carry_n_2 : STD_LOGIC;
signal y_addr_out2_carry_n_3 : STD_LOGIC;
signal \y_addr_out3__0_n_100\ : STD_LOGIC;
signal \y_addr_out3__0_n_101\ : STD_LOGIC;
signal \y_addr_out3__0_n_102\ : STD_LOGIC;
signal \y_addr_out3__0_n_103\ : STD_LOGIC;
signal \y_addr_out3__0_n_104\ : STD_LOGIC;
signal \y_addr_out3__0_n_105\ : STD_LOGIC;
signal \y_addr_out3__0_n_58\ : STD_LOGIC;
signal \y_addr_out3__0_n_59\ : STD_LOGIC;
signal \y_addr_out3__0_n_60\ : STD_LOGIC;
signal \y_addr_out3__0_n_61\ : STD_LOGIC;
signal \y_addr_out3__0_n_62\ : STD_LOGIC;
signal \y_addr_out3__0_n_63\ : STD_LOGIC;
signal \y_addr_out3__0_n_64\ : STD_LOGIC;
signal \y_addr_out3__0_n_65\ : STD_LOGIC;
signal \y_addr_out3__0_n_66\ : STD_LOGIC;
signal \y_addr_out3__0_n_67\ : STD_LOGIC;
signal \y_addr_out3__0_n_68\ : STD_LOGIC;
signal \y_addr_out3__0_n_69\ : STD_LOGIC;
signal \y_addr_out3__0_n_70\ : STD_LOGIC;
signal \y_addr_out3__0_n_71\ : STD_LOGIC;
signal \y_addr_out3__0_n_72\ : STD_LOGIC;
signal \y_addr_out3__0_n_73\ : STD_LOGIC;
signal \y_addr_out3__0_n_74\ : STD_LOGIC;
signal \y_addr_out3__0_n_75\ : STD_LOGIC;
signal \y_addr_out3__0_n_76\ : STD_LOGIC;
signal \y_addr_out3__0_n_77\ : STD_LOGIC;
signal \y_addr_out3__0_n_78\ : STD_LOGIC;
signal \y_addr_out3__0_n_79\ : STD_LOGIC;
signal \y_addr_out3__0_n_80\ : STD_LOGIC;
signal \y_addr_out3__0_n_81\ : STD_LOGIC;
signal \y_addr_out3__0_n_82\ : STD_LOGIC;
signal \y_addr_out3__0_n_83\ : STD_LOGIC;
signal \y_addr_out3__0_n_84\ : STD_LOGIC;
signal \y_addr_out3__0_n_85\ : STD_LOGIC;
signal \y_addr_out3__0_n_86\ : STD_LOGIC;
signal \y_addr_out3__0_n_87\ : STD_LOGIC;
signal \y_addr_out3__0_n_88\ : STD_LOGIC;
signal \y_addr_out3__0_n_89\ : STD_LOGIC;
signal \y_addr_out3__0_n_90\ : STD_LOGIC;
signal \y_addr_out3__0_n_91\ : STD_LOGIC;
signal \y_addr_out3__0_n_92\ : STD_LOGIC;
signal \y_addr_out3__0_n_93\ : STD_LOGIC;
signal \y_addr_out3__0_n_94\ : STD_LOGIC;
signal \y_addr_out3__0_n_95\ : STD_LOGIC;
signal \y_addr_out3__0_n_96\ : STD_LOGIC;
signal \y_addr_out3__0_n_97\ : STD_LOGIC;
signal \y_addr_out3__0_n_98\ : STD_LOGIC;
signal \y_addr_out3__0_n_99\ : STD_LOGIC;
signal \y_addr_out3__1_n_100\ : STD_LOGIC;
signal \y_addr_out3__1_n_101\ : STD_LOGIC;
signal \y_addr_out3__1_n_102\ : STD_LOGIC;
signal \y_addr_out3__1_n_103\ : STD_LOGIC;
signal \y_addr_out3__1_n_104\ : STD_LOGIC;
signal \y_addr_out3__1_n_105\ : STD_LOGIC;
signal \y_addr_out3__1_n_106\ : STD_LOGIC;
signal \y_addr_out3__1_n_107\ : STD_LOGIC;
signal \y_addr_out3__1_n_108\ : STD_LOGIC;
signal \y_addr_out3__1_n_109\ : STD_LOGIC;
signal \y_addr_out3__1_n_110\ : STD_LOGIC;
signal \y_addr_out3__1_n_111\ : STD_LOGIC;
signal \y_addr_out3__1_n_112\ : STD_LOGIC;
signal \y_addr_out3__1_n_113\ : STD_LOGIC;
signal \y_addr_out3__1_n_114\ : STD_LOGIC;
signal \y_addr_out3__1_n_115\ : STD_LOGIC;
signal \y_addr_out3__1_n_116\ : STD_LOGIC;
signal \y_addr_out3__1_n_117\ : STD_LOGIC;
signal \y_addr_out3__1_n_118\ : STD_LOGIC;
signal \y_addr_out3__1_n_119\ : STD_LOGIC;
signal \y_addr_out3__1_n_120\ : STD_LOGIC;
signal \y_addr_out3__1_n_121\ : STD_LOGIC;
signal \y_addr_out3__1_n_122\ : STD_LOGIC;
signal \y_addr_out3__1_n_123\ : STD_LOGIC;
signal \y_addr_out3__1_n_124\ : STD_LOGIC;
signal \y_addr_out3__1_n_125\ : STD_LOGIC;
signal \y_addr_out3__1_n_126\ : STD_LOGIC;
signal \y_addr_out3__1_n_127\ : STD_LOGIC;
signal \y_addr_out3__1_n_128\ : STD_LOGIC;
signal \y_addr_out3__1_n_129\ : STD_LOGIC;
signal \y_addr_out3__1_n_130\ : STD_LOGIC;
signal \y_addr_out3__1_n_131\ : STD_LOGIC;
signal \y_addr_out3__1_n_132\ : STD_LOGIC;
signal \y_addr_out3__1_n_133\ : STD_LOGIC;
signal \y_addr_out3__1_n_134\ : STD_LOGIC;
signal \y_addr_out3__1_n_135\ : STD_LOGIC;
signal \y_addr_out3__1_n_136\ : STD_LOGIC;
signal \y_addr_out3__1_n_137\ : STD_LOGIC;
signal \y_addr_out3__1_n_138\ : STD_LOGIC;
signal \y_addr_out3__1_n_139\ : STD_LOGIC;
signal \y_addr_out3__1_n_140\ : STD_LOGIC;
signal \y_addr_out3__1_n_141\ : STD_LOGIC;
signal \y_addr_out3__1_n_142\ : STD_LOGIC;
signal \y_addr_out3__1_n_143\ : STD_LOGIC;
signal \y_addr_out3__1_n_144\ : STD_LOGIC;
signal \y_addr_out3__1_n_145\ : STD_LOGIC;
signal \y_addr_out3__1_n_146\ : STD_LOGIC;
signal \y_addr_out3__1_n_147\ : STD_LOGIC;
signal \y_addr_out3__1_n_148\ : STD_LOGIC;
signal \y_addr_out3__1_n_149\ : STD_LOGIC;
signal \y_addr_out3__1_n_150\ : STD_LOGIC;
signal \y_addr_out3__1_n_151\ : STD_LOGIC;
signal \y_addr_out3__1_n_152\ : STD_LOGIC;
signal \y_addr_out3__1_n_153\ : STD_LOGIC;
signal \y_addr_out3__1_n_58\ : STD_LOGIC;
signal \y_addr_out3__1_n_59\ : STD_LOGIC;
signal \y_addr_out3__1_n_60\ : STD_LOGIC;
signal \y_addr_out3__1_n_61\ : STD_LOGIC;
signal \y_addr_out3__1_n_62\ : STD_LOGIC;
signal \y_addr_out3__1_n_63\ : STD_LOGIC;
signal \y_addr_out3__1_n_64\ : STD_LOGIC;
signal \y_addr_out3__1_n_65\ : STD_LOGIC;
signal \y_addr_out3__1_n_66\ : STD_LOGIC;
signal \y_addr_out3__1_n_67\ : STD_LOGIC;
signal \y_addr_out3__1_n_68\ : STD_LOGIC;
signal \y_addr_out3__1_n_69\ : STD_LOGIC;
signal \y_addr_out3__1_n_70\ : STD_LOGIC;
signal \y_addr_out3__1_n_71\ : STD_LOGIC;
signal \y_addr_out3__1_n_72\ : STD_LOGIC;
signal \y_addr_out3__1_n_73\ : STD_LOGIC;
signal \y_addr_out3__1_n_74\ : STD_LOGIC;
signal \y_addr_out3__1_n_75\ : STD_LOGIC;
signal \y_addr_out3__1_n_76\ : STD_LOGIC;
signal \y_addr_out3__1_n_77\ : STD_LOGIC;
signal \y_addr_out3__1_n_78\ : STD_LOGIC;
signal \y_addr_out3__1_n_79\ : STD_LOGIC;
signal \y_addr_out3__1_n_80\ : STD_LOGIC;
signal \y_addr_out3__1_n_81\ : STD_LOGIC;
signal \y_addr_out3__1_n_82\ : STD_LOGIC;
signal \y_addr_out3__1_n_83\ : STD_LOGIC;
signal \y_addr_out3__1_n_84\ : STD_LOGIC;
signal \y_addr_out3__1_n_85\ : STD_LOGIC;
signal \y_addr_out3__1_n_86\ : STD_LOGIC;
signal \y_addr_out3__1_n_87\ : STD_LOGIC;
signal \y_addr_out3__1_n_88\ : STD_LOGIC;
signal \y_addr_out3__1_n_89\ : STD_LOGIC;
signal \y_addr_out3__1_n_90\ : STD_LOGIC;
signal \y_addr_out3__1_n_91\ : STD_LOGIC;
signal \y_addr_out3__1_n_92\ : STD_LOGIC;
signal \y_addr_out3__1_n_93\ : STD_LOGIC;
signal \y_addr_out3__1_n_94\ : STD_LOGIC;
signal \y_addr_out3__1_n_95\ : STD_LOGIC;
signal \y_addr_out3__1_n_96\ : STD_LOGIC;
signal \y_addr_out3__1_n_97\ : STD_LOGIC;
signal \y_addr_out3__1_n_98\ : STD_LOGIC;
signal \y_addr_out3__1_n_99\ : STD_LOGIC;
signal \y_addr_out3__2_n_100\ : STD_LOGIC;
signal \y_addr_out3__2_n_101\ : STD_LOGIC;
signal \y_addr_out3__2_n_102\ : STD_LOGIC;
signal \y_addr_out3__2_n_103\ : STD_LOGIC;
signal \y_addr_out3__2_n_104\ : STD_LOGIC;
signal \y_addr_out3__2_n_105\ : STD_LOGIC;
signal \y_addr_out3__2_n_58\ : STD_LOGIC;
signal \y_addr_out3__2_n_59\ : STD_LOGIC;
signal \y_addr_out3__2_n_60\ : STD_LOGIC;
signal \y_addr_out3__2_n_61\ : STD_LOGIC;
signal \y_addr_out3__2_n_62\ : STD_LOGIC;
signal \y_addr_out3__2_n_63\ : STD_LOGIC;
signal \y_addr_out3__2_n_64\ : STD_LOGIC;
signal \y_addr_out3__2_n_65\ : STD_LOGIC;
signal \y_addr_out3__2_n_66\ : STD_LOGIC;
signal \y_addr_out3__2_n_67\ : STD_LOGIC;
signal \y_addr_out3__2_n_68\ : STD_LOGIC;
signal \y_addr_out3__2_n_69\ : STD_LOGIC;
signal \y_addr_out3__2_n_70\ : STD_LOGIC;
signal \y_addr_out3__2_n_71\ : STD_LOGIC;
signal \y_addr_out3__2_n_72\ : STD_LOGIC;
signal \y_addr_out3__2_n_73\ : STD_LOGIC;
signal \y_addr_out3__2_n_74\ : STD_LOGIC;
signal \y_addr_out3__2_n_75\ : STD_LOGIC;
signal \y_addr_out3__2_n_76\ : STD_LOGIC;
signal \y_addr_out3__2_n_77\ : STD_LOGIC;
signal \y_addr_out3__2_n_78\ : STD_LOGIC;
signal \y_addr_out3__2_n_79\ : STD_LOGIC;
signal \y_addr_out3__2_n_80\ : STD_LOGIC;
signal \y_addr_out3__2_n_81\ : STD_LOGIC;
signal \y_addr_out3__2_n_82\ : STD_LOGIC;
signal \y_addr_out3__2_n_83\ : STD_LOGIC;
signal \y_addr_out3__2_n_84\ : STD_LOGIC;
signal \y_addr_out3__2_n_85\ : STD_LOGIC;
signal \y_addr_out3__2_n_86\ : STD_LOGIC;
signal \y_addr_out3__2_n_87\ : STD_LOGIC;
signal \y_addr_out3__2_n_88\ : STD_LOGIC;
signal \y_addr_out3__2_n_89\ : STD_LOGIC;
signal \y_addr_out3__2_n_90\ : STD_LOGIC;
signal \y_addr_out3__2_n_91\ : STD_LOGIC;
signal \y_addr_out3__2_n_92\ : STD_LOGIC;
signal \y_addr_out3__2_n_93\ : STD_LOGIC;
signal \y_addr_out3__2_n_94\ : STD_LOGIC;
signal \y_addr_out3__2_n_95\ : STD_LOGIC;
signal \y_addr_out3__2_n_96\ : STD_LOGIC;
signal \y_addr_out3__2_n_97\ : STD_LOGIC;
signal \y_addr_out3__2_n_98\ : STD_LOGIC;
signal \y_addr_out3__2_n_99\ : STD_LOGIC;
signal y_addr_out3_n_100 : STD_LOGIC;
signal y_addr_out3_n_101 : STD_LOGIC;
signal y_addr_out3_n_102 : STD_LOGIC;
signal y_addr_out3_n_103 : STD_LOGIC;
signal y_addr_out3_n_104 : STD_LOGIC;
signal y_addr_out3_n_105 : STD_LOGIC;
signal y_addr_out3_n_106 : STD_LOGIC;
signal y_addr_out3_n_107 : STD_LOGIC;
signal y_addr_out3_n_108 : STD_LOGIC;
signal y_addr_out3_n_109 : STD_LOGIC;
signal y_addr_out3_n_110 : STD_LOGIC;
signal y_addr_out3_n_111 : STD_LOGIC;
signal y_addr_out3_n_112 : STD_LOGIC;
signal y_addr_out3_n_113 : STD_LOGIC;
signal y_addr_out3_n_114 : STD_LOGIC;
signal y_addr_out3_n_115 : STD_LOGIC;
signal y_addr_out3_n_116 : STD_LOGIC;
signal y_addr_out3_n_117 : STD_LOGIC;
signal y_addr_out3_n_118 : STD_LOGIC;
signal y_addr_out3_n_119 : STD_LOGIC;
signal y_addr_out3_n_120 : STD_LOGIC;
signal y_addr_out3_n_121 : STD_LOGIC;
signal y_addr_out3_n_122 : STD_LOGIC;
signal y_addr_out3_n_123 : STD_LOGIC;
signal y_addr_out3_n_124 : STD_LOGIC;
signal y_addr_out3_n_125 : STD_LOGIC;
signal y_addr_out3_n_126 : STD_LOGIC;
signal y_addr_out3_n_127 : STD_LOGIC;
signal y_addr_out3_n_128 : STD_LOGIC;
signal y_addr_out3_n_129 : STD_LOGIC;
signal y_addr_out3_n_130 : STD_LOGIC;
signal y_addr_out3_n_131 : STD_LOGIC;
signal y_addr_out3_n_132 : STD_LOGIC;
signal y_addr_out3_n_133 : STD_LOGIC;
signal y_addr_out3_n_134 : STD_LOGIC;
signal y_addr_out3_n_135 : STD_LOGIC;
signal y_addr_out3_n_136 : STD_LOGIC;
signal y_addr_out3_n_137 : STD_LOGIC;
signal y_addr_out3_n_138 : STD_LOGIC;
signal y_addr_out3_n_139 : STD_LOGIC;
signal y_addr_out3_n_140 : STD_LOGIC;
signal y_addr_out3_n_141 : STD_LOGIC;
signal y_addr_out3_n_142 : STD_LOGIC;
signal y_addr_out3_n_143 : STD_LOGIC;
signal y_addr_out3_n_144 : STD_LOGIC;
signal y_addr_out3_n_145 : STD_LOGIC;
signal y_addr_out3_n_146 : STD_LOGIC;
signal y_addr_out3_n_147 : STD_LOGIC;
signal y_addr_out3_n_148 : STD_LOGIC;
signal y_addr_out3_n_149 : STD_LOGIC;
signal y_addr_out3_n_150 : STD_LOGIC;
signal y_addr_out3_n_151 : STD_LOGIC;
signal y_addr_out3_n_152 : STD_LOGIC;
signal y_addr_out3_n_153 : STD_LOGIC;
signal y_addr_out3_n_58 : STD_LOGIC;
signal y_addr_out3_n_59 : STD_LOGIC;
signal y_addr_out3_n_60 : STD_LOGIC;
signal y_addr_out3_n_61 : STD_LOGIC;
signal y_addr_out3_n_62 : STD_LOGIC;
signal y_addr_out3_n_63 : STD_LOGIC;
signal y_addr_out3_n_64 : STD_LOGIC;
signal y_addr_out3_n_65 : STD_LOGIC;
signal y_addr_out3_n_66 : STD_LOGIC;
signal y_addr_out3_n_67 : STD_LOGIC;
signal y_addr_out3_n_68 : STD_LOGIC;
signal y_addr_out3_n_69 : STD_LOGIC;
signal y_addr_out3_n_70 : STD_LOGIC;
signal y_addr_out3_n_71 : STD_LOGIC;
signal y_addr_out3_n_72 : STD_LOGIC;
signal y_addr_out3_n_73 : STD_LOGIC;
signal y_addr_out3_n_74 : STD_LOGIC;
signal y_addr_out3_n_75 : STD_LOGIC;
signal y_addr_out3_n_76 : STD_LOGIC;
signal y_addr_out3_n_77 : STD_LOGIC;
signal y_addr_out3_n_78 : STD_LOGIC;
signal y_addr_out3_n_79 : STD_LOGIC;
signal y_addr_out3_n_80 : STD_LOGIC;
signal y_addr_out3_n_81 : STD_LOGIC;
signal y_addr_out3_n_82 : STD_LOGIC;
signal y_addr_out3_n_83 : STD_LOGIC;
signal y_addr_out3_n_84 : STD_LOGIC;
signal y_addr_out3_n_85 : STD_LOGIC;
signal y_addr_out3_n_86 : STD_LOGIC;
signal y_addr_out3_n_87 : STD_LOGIC;
signal y_addr_out3_n_88 : STD_LOGIC;
signal y_addr_out3_n_89 : STD_LOGIC;
signal y_addr_out3_n_90 : STD_LOGIC;
signal y_addr_out3_n_91 : STD_LOGIC;
signal y_addr_out3_n_92 : STD_LOGIC;
signal y_addr_out3_n_93 : STD_LOGIC;
signal y_addr_out3_n_94 : STD_LOGIC;
signal y_addr_out3_n_95 : STD_LOGIC;
signal y_addr_out3_n_96 : STD_LOGIC;
signal y_addr_out3_n_97 : STD_LOGIC;
signal y_addr_out3_n_98 : STD_LOGIC;
signal y_addr_out3_n_99 : STD_LOGIC;
signal NLW_x_addr_out0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_x_addr_out0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_x_addr_out0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_x_addr_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_x_addr_out2_carry__8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_x_addr_out3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_x_addr_out3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_y_addr_out0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_addr_out0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_addr_out0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_y_addr_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_addr_out2_carry__8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_y_addr_out3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_y_addr_out3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of x_addr_out3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__2\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \x_addr_out[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x_addr_out[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x_addr_out[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \x_addr_out[8]_i_1\ : label is "soft_lutpair3";
attribute METHODOLOGY_DRC_VIOS of y_addr_out3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__2\ : label is "{SYNTH-13 {cell *THIS*}}";
begin
x_addr_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => x_addr_out0_carry_n_0,
CO(2) => x_addr_out0_carry_n_1,
CO(1) => x_addr_out0_carry_n_2,
CO(0) => x_addr_out0_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => p_1_in(17 downto 14),
O(3 downto 1) => x_addr_out0(17 downto 15),
O(0) => NLW_x_addr_out0_carry_O_UNCONNECTED(0),
S(3) => x_addr_out0_carry_i_1_n_0,
S(2) => x_addr_out0_carry_i_2_n_0,
S(1) => x_addr_out0_carry_i_3_n_0,
S(0) => x_addr_out0(14)
);
\x_addr_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => x_addr_out0_carry_n_0,
CO(3) => \x_addr_out0_carry__0_n_0\,
CO(2) => \x_addr_out0_carry__0_n_1\,
CO(1) => \x_addr_out0_carry__0_n_2\,
CO(0) => \x_addr_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_1_in(21 downto 18),
O(3 downto 0) => x_addr_out0(21 downto 18),
S(3) => \x_addr_out0_carry__0_i_1_n_0\,
S(2) => \x_addr_out0_carry__0_i_2_n_0\,
S(1) => \x_addr_out0_carry__0_i_3_n_0\,
S(0) => \x_addr_out0_carry__0_i_4_n_0\
);
\x_addr_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(21),
I1 => t_x(7),
O => \x_addr_out0_carry__0_i_1_n_0\
);
\x_addr_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(20),
I1 => t_x(6),
O => \x_addr_out0_carry__0_i_2_n_0\
);
\x_addr_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(19),
I1 => t_x(5),
O => \x_addr_out0_carry__0_i_3_n_0\
);
\x_addr_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(18),
I1 => t_x(4),
O => \x_addr_out0_carry__0_i_4_n_0\
);
\x_addr_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out0_carry__0_n_0\,
CO(3 downto 1) => \NLW_x_addr_out0_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \x_addr_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_1_in(22),
O(3 downto 2) => \NLW_x_addr_out0_carry__1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => x_addr_out0(23 downto 22),
S(3 downto 2) => B"00",
S(1) => \x_addr_out0_carry__1_i_1_n_0\,
S(0) => \x_addr_out0_carry__1_i_2_n_0\
);
\x_addr_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(23),
I1 => t_x(9),
O => \x_addr_out0_carry__1_i_1_n_0\
);
\x_addr_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(22),
I1 => t_x(8),
O => \x_addr_out0_carry__1_i_2_n_0\
);
x_addr_out0_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(17),
I1 => t_x(3),
O => x_addr_out0_carry_i_1_n_0
);
x_addr_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(16),
I1 => t_x(2),
O => x_addr_out0_carry_i_2_n_0
);
x_addr_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(15),
I1 => t_x(1),
O => x_addr_out0_carry_i_3_n_0
);
x_addr_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(14),
I1 => t_x(0),
O => x_addr_out0(14)
);
x_addr_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => x_addr_out2_carry_n_0,
CO(2) => x_addr_out2_carry_n_1,
CO(1) => x_addr_out2_carry_n_2,
CO(0) => x_addr_out2_carry_n_3,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_102\,
DI(2) => \x_addr_out3__1_n_103\,
DI(1) => \x_addr_out3__1_n_104\,
DI(0) => \x_addr_out3__1_n_105\,
O(3 downto 0) => NLW_x_addr_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => x_addr_out2_carry_i_1_n_0,
S(2) => x_addr_out2_carry_i_2_n_0,
S(1) => x_addr_out2_carry_i_3_n_0,
S(0) => x_addr_out2_carry_i_4_n_0
);
\x_addr_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => x_addr_out2_carry_n_0,
CO(3) => \x_addr_out2_carry__0_n_0\,
CO(2) => \x_addr_out2_carry__0_n_1\,
CO(1) => \x_addr_out2_carry__0_n_2\,
CO(0) => \x_addr_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_98\,
DI(2) => \x_addr_out3__1_n_99\,
DI(1) => \x_addr_out3__1_n_100\,
DI(0) => \x_addr_out3__1_n_101\,
O(3 downto 0) => \NLW_x_addr_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__0_i_1_n_0\,
S(2) => \x_addr_out2_carry__0_i_2_n_0\,
S(1) => \x_addr_out2_carry__0_i_3_n_0\,
S(0) => \x_addr_out2_carry__0_i_4_n_0\
);
\x_addr_out2_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_98\,
I1 => x_addr_out3_n_98,
O => \x_addr_out2_carry__0_i_1_n_0\
);
\x_addr_out2_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_99\,
I1 => x_addr_out3_n_99,
O => \x_addr_out2_carry__0_i_2_n_0\
);
\x_addr_out2_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_100\,
I1 => x_addr_out3_n_100,
O => \x_addr_out2_carry__0_i_3_n_0\
);
\x_addr_out2_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_101\,
I1 => x_addr_out3_n_101,
O => \x_addr_out2_carry__0_i_4_n_0\
);
\x_addr_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__0_n_0\,
CO(3) => \x_addr_out2_carry__1_n_0\,
CO(2) => \x_addr_out2_carry__1_n_1\,
CO(1) => \x_addr_out2_carry__1_n_2\,
CO(0) => \x_addr_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_94\,
DI(2) => \x_addr_out3__1_n_95\,
DI(1) => \x_addr_out3__1_n_96\,
DI(0) => \x_addr_out3__1_n_97\,
O(3 downto 0) => \NLW_x_addr_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__1_i_1_n_0\,
S(2) => \x_addr_out2_carry__1_i_2_n_0\,
S(1) => \x_addr_out2_carry__1_i_3_n_0\,
S(0) => \x_addr_out2_carry__1_i_4_n_0\
);
\x_addr_out2_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_94\,
I1 => x_addr_out3_n_94,
O => \x_addr_out2_carry__1_i_1_n_0\
);
\x_addr_out2_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_95\,
I1 => x_addr_out3_n_95,
O => \x_addr_out2_carry__1_i_2_n_0\
);
\x_addr_out2_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_96\,
I1 => x_addr_out3_n_96,
O => \x_addr_out2_carry__1_i_3_n_0\
);
\x_addr_out2_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_97\,
I1 => x_addr_out3_n_97,
O => \x_addr_out2_carry__1_i_4_n_0\
);
\x_addr_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__1_n_0\,
CO(3) => \x_addr_out2_carry__2_n_0\,
CO(2) => \x_addr_out2_carry__2_n_1\,
CO(1) => \x_addr_out2_carry__2_n_2\,
CO(0) => \x_addr_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_90\,
DI(2) => \x_addr_out3__1_n_91\,
DI(1) => \x_addr_out3__1_n_92\,
DI(0) => \x_addr_out3__1_n_93\,
O(3 downto 0) => \NLW_x_addr_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__2_i_1_n_0\,
S(2) => \x_addr_out2_carry__2_i_2_n_0\,
S(1) => \x_addr_out2_carry__2_i_3_n_0\,
S(0) => \x_addr_out2_carry__2_i_4_n_0\
);
\x_addr_out2_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_90\,
I1 => x_addr_out3_n_90,
O => \x_addr_out2_carry__2_i_1_n_0\
);
\x_addr_out2_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_91\,
I1 => x_addr_out3_n_91,
O => \x_addr_out2_carry__2_i_2_n_0\
);
\x_addr_out2_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_92\,
I1 => x_addr_out3_n_92,
O => \x_addr_out2_carry__2_i_3_n_0\
);
\x_addr_out2_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_93\,
I1 => x_addr_out3_n_93,
O => \x_addr_out2_carry__2_i_4_n_0\
);
\x_addr_out2_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__2_n_0\,
CO(3) => \x_addr_out2_carry__3_n_0\,
CO(2) => \x_addr_out2_carry__3_n_1\,
CO(1) => \x_addr_out2_carry__3_n_2\,
CO(0) => \x_addr_out2_carry__3_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_103\,
DI(2) => \x_addr_out3__2_n_104\,
DI(1) => \x_addr_out3__2_n_105\,
DI(0) => \x_addr_out3__1_n_89\,
O(3 downto 0) => \NLW_x_addr_out2_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__3_i_1_n_0\,
S(2) => \x_addr_out2_carry__3_i_2_n_0\,
S(1) => \x_addr_out2_carry__3_i_3_n_0\,
S(0) => \x_addr_out2_carry__3_i_4_n_0\
);
\x_addr_out2_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_103\,
I1 => \x_addr_out3__0_n_103\,
O => \x_addr_out2_carry__3_i_1_n_0\
);
\x_addr_out2_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_104\,
I1 => \x_addr_out3__0_n_104\,
O => \x_addr_out2_carry__3_i_2_n_0\
);
\x_addr_out2_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_105\,
I1 => \x_addr_out3__0_n_105\,
O => \x_addr_out2_carry__3_i_3_n_0\
);
\x_addr_out2_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_89\,
I1 => x_addr_out3_n_89,
O => \x_addr_out2_carry__3_i_4_n_0\
);
\x_addr_out2_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__3_n_0\,
CO(3) => \x_addr_out2_carry__4_n_0\,
CO(2) => \x_addr_out2_carry__4_n_1\,
CO(1) => \x_addr_out2_carry__4_n_2\,
CO(0) => \x_addr_out2_carry__4_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_99\,
DI(2) => \x_addr_out3__2_n_100\,
DI(1) => \x_addr_out3__2_n_101\,
DI(0) => \x_addr_out3__2_n_102\,
O(3 downto 0) => \NLW_x_addr_out2_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__4_i_1_n_0\,
S(2) => \x_addr_out2_carry__4_i_2_n_0\,
S(1) => \x_addr_out2_carry__4_i_3_n_0\,
S(0) => \x_addr_out2_carry__4_i_4_n_0\
);
\x_addr_out2_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_99\,
I1 => \x_addr_out3__0_n_99\,
O => \x_addr_out2_carry__4_i_1_n_0\
);
\x_addr_out2_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_100\,
I1 => \x_addr_out3__0_n_100\,
O => \x_addr_out2_carry__4_i_2_n_0\
);
\x_addr_out2_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_101\,
I1 => \x_addr_out3__0_n_101\,
O => \x_addr_out2_carry__4_i_3_n_0\
);
\x_addr_out2_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_102\,
I1 => \x_addr_out3__0_n_102\,
O => \x_addr_out2_carry__4_i_4_n_0\
);
\x_addr_out2_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__4_n_0\,
CO(3) => \x_addr_out2_carry__5_n_0\,
CO(2) => \x_addr_out2_carry__5_n_1\,
CO(1) => \x_addr_out2_carry__5_n_2\,
CO(0) => \x_addr_out2_carry__5_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_95\,
DI(2) => \x_addr_out3__2_n_96\,
DI(1) => \x_addr_out3__2_n_97\,
DI(0) => \x_addr_out3__2_n_98\,
O(3 downto 0) => \NLW_x_addr_out2_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__5_i_1_n_0\,
S(2) => \x_addr_out2_carry__5_i_2_n_0\,
S(1) => \x_addr_out2_carry__5_i_3_n_0\,
S(0) => \x_addr_out2_carry__5_i_4_n_0\
);
\x_addr_out2_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_95\,
I1 => \x_addr_out3__0_n_95\,
O => \x_addr_out2_carry__5_i_1_n_0\
);
\x_addr_out2_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_96\,
I1 => \x_addr_out3__0_n_96\,
O => \x_addr_out2_carry__5_i_2_n_0\
);
\x_addr_out2_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_97\,
I1 => \x_addr_out3__0_n_97\,
O => \x_addr_out2_carry__5_i_3_n_0\
);
\x_addr_out2_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_98\,
I1 => \x_addr_out3__0_n_98\,
O => \x_addr_out2_carry__5_i_4_n_0\
);
\x_addr_out2_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__5_n_0\,
CO(3) => \x_addr_out2_carry__6_n_0\,
CO(2) => \x_addr_out2_carry__6_n_1\,
CO(1) => \x_addr_out2_carry__6_n_2\,
CO(0) => \x_addr_out2_carry__6_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_91\,
DI(2) => \x_addr_out3__2_n_92\,
DI(1) => \x_addr_out3__2_n_93\,
DI(0) => \x_addr_out3__2_n_94\,
O(3 downto 0) => p_1_in(17 downto 14),
S(3) => \x_addr_out2_carry__6_i_1_n_0\,
S(2) => \x_addr_out2_carry__6_i_2_n_0\,
S(1) => \x_addr_out2_carry__6_i_3_n_0\,
S(0) => \x_addr_out2_carry__6_i_4_n_0\
);
\x_addr_out2_carry__6_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_91\,
I1 => \x_addr_out3__0_n_91\,
O => \x_addr_out2_carry__6_i_1_n_0\
);
\x_addr_out2_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_92\,
I1 => \x_addr_out3__0_n_92\,
O => \x_addr_out2_carry__6_i_2_n_0\
);
\x_addr_out2_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_93\,
I1 => \x_addr_out3__0_n_93\,
O => \x_addr_out2_carry__6_i_3_n_0\
);
\x_addr_out2_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_94\,
I1 => \x_addr_out3__0_n_94\,
O => \x_addr_out2_carry__6_i_4_n_0\
);
\x_addr_out2_carry__7\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__6_n_0\,
CO(3) => \x_addr_out2_carry__7_n_0\,
CO(2) => \x_addr_out2_carry__7_n_1\,
CO(1) => \x_addr_out2_carry__7_n_2\,
CO(0) => \x_addr_out2_carry__7_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_87\,
DI(2) => \x_addr_out3__2_n_88\,
DI(1) => \x_addr_out3__2_n_89\,
DI(0) => \x_addr_out3__2_n_90\,
O(3 downto 0) => p_1_in(21 downto 18),
S(3) => \x_addr_out2_carry__7_i_1_n_0\,
S(2) => \x_addr_out2_carry__7_i_2_n_0\,
S(1) => \x_addr_out2_carry__7_i_3_n_0\,
S(0) => \x_addr_out2_carry__7_i_4_n_0\
);
\x_addr_out2_carry__7_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_87\,
I1 => \x_addr_out3__0_n_87\,
O => \x_addr_out2_carry__7_i_1_n_0\
);
\x_addr_out2_carry__7_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_88\,
I1 => \x_addr_out3__0_n_88\,
O => \x_addr_out2_carry__7_i_2_n_0\
);
\x_addr_out2_carry__7_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_89\,
I1 => \x_addr_out3__0_n_89\,
O => \x_addr_out2_carry__7_i_3_n_0\
);
\x_addr_out2_carry__7_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_90\,
I1 => \x_addr_out3__0_n_90\,
O => \x_addr_out2_carry__7_i_4_n_0\
);
\x_addr_out2_carry__8\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__7_n_0\,
CO(3 downto 1) => \NLW_x_addr_out2_carry__8_CO_UNCONNECTED\(3 downto 1),
CO(0) => \x_addr_out2_carry__8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \x_addr_out3__2_n_86\,
O(3 downto 2) => \NLW_x_addr_out2_carry__8_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => p_1_in(23 downto 22),
S(3 downto 2) => B"00",
S(1) => \x_addr_out2_carry__8_i_1_n_0\,
S(0) => \x_addr_out2_carry__8_i_2_n_0\
);
\x_addr_out2_carry__8_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_85\,
I1 => \x_addr_out3__0_n_85\,
O => \x_addr_out2_carry__8_i_1_n_0\
);
\x_addr_out2_carry__8_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_86\,
I1 => \x_addr_out3__0_n_86\,
O => \x_addr_out2_carry__8_i_2_n_0\
);
x_addr_out2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_102\,
I1 => x_addr_out3_n_102,
O => x_addr_out2_carry_i_1_n_0
);
x_addr_out2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_103\,
I1 => x_addr_out3_n_103,
O => x_addr_out2_carry_i_2_n_0
);
x_addr_out2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_104\,
I1 => x_addr_out3_n_104,
O => x_addr_out2_carry_i_3_n_0
);
x_addr_out2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_105\,
I1 => x_addr_out3_n_105,
O => x_addr_out2_carry_i_4_n_0
);
x_addr_out3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => y_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_x_addr_out3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m01(15),
B(16) => rot_m01(15),
B(15 downto 0) => rot_m01(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_x_addr_out3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_x_addr_out3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_x_addr_out3_OVERFLOW_UNCONNECTED,
P(47) => x_addr_out3_n_58,
P(46) => x_addr_out3_n_59,
P(45) => x_addr_out3_n_60,
P(44) => x_addr_out3_n_61,
P(43) => x_addr_out3_n_62,
P(42) => x_addr_out3_n_63,
P(41) => x_addr_out3_n_64,
P(40) => x_addr_out3_n_65,
P(39) => x_addr_out3_n_66,
P(38) => x_addr_out3_n_67,
P(37) => x_addr_out3_n_68,
P(36) => x_addr_out3_n_69,
P(35) => x_addr_out3_n_70,
P(34) => x_addr_out3_n_71,
P(33) => x_addr_out3_n_72,
P(32) => x_addr_out3_n_73,
P(31) => x_addr_out3_n_74,
P(30) => x_addr_out3_n_75,
P(29) => x_addr_out3_n_76,
P(28) => x_addr_out3_n_77,
P(27) => x_addr_out3_n_78,
P(26) => x_addr_out3_n_79,
P(25) => x_addr_out3_n_80,
P(24) => x_addr_out3_n_81,
P(23) => x_addr_out3_n_82,
P(22) => x_addr_out3_n_83,
P(21) => x_addr_out3_n_84,
P(20) => x_addr_out3_n_85,
P(19) => x_addr_out3_n_86,
P(18) => x_addr_out3_n_87,
P(17) => x_addr_out3_n_88,
P(16) => x_addr_out3_n_89,
P(15) => x_addr_out3_n_90,
P(14) => x_addr_out3_n_91,
P(13) => x_addr_out3_n_92,
P(12) => x_addr_out3_n_93,
P(11) => x_addr_out3_n_94,
P(10) => x_addr_out3_n_95,
P(9) => x_addr_out3_n_96,
P(8) => x_addr_out3_n_97,
P(7) => x_addr_out3_n_98,
P(6) => x_addr_out3_n_99,
P(5) => x_addr_out3_n_100,
P(4) => x_addr_out3_n_101,
P(3) => x_addr_out3_n_102,
P(2) => x_addr_out3_n_103,
P(1) => x_addr_out3_n_104,
P(0) => x_addr_out3_n_105,
PATTERNBDETECT => NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => x_addr_out3_n_106,
PCOUT(46) => x_addr_out3_n_107,
PCOUT(45) => x_addr_out3_n_108,
PCOUT(44) => x_addr_out3_n_109,
PCOUT(43) => x_addr_out3_n_110,
PCOUT(42) => x_addr_out3_n_111,
PCOUT(41) => x_addr_out3_n_112,
PCOUT(40) => x_addr_out3_n_113,
PCOUT(39) => x_addr_out3_n_114,
PCOUT(38) => x_addr_out3_n_115,
PCOUT(37) => x_addr_out3_n_116,
PCOUT(36) => x_addr_out3_n_117,
PCOUT(35) => x_addr_out3_n_118,
PCOUT(34) => x_addr_out3_n_119,
PCOUT(33) => x_addr_out3_n_120,
PCOUT(32) => x_addr_out3_n_121,
PCOUT(31) => x_addr_out3_n_122,
PCOUT(30) => x_addr_out3_n_123,
PCOUT(29) => x_addr_out3_n_124,
PCOUT(28) => x_addr_out3_n_125,
PCOUT(27) => x_addr_out3_n_126,
PCOUT(26) => x_addr_out3_n_127,
PCOUT(25) => x_addr_out3_n_128,
PCOUT(24) => x_addr_out3_n_129,
PCOUT(23) => x_addr_out3_n_130,
PCOUT(22) => x_addr_out3_n_131,
PCOUT(21) => x_addr_out3_n_132,
PCOUT(20) => x_addr_out3_n_133,
PCOUT(19) => x_addr_out3_n_134,
PCOUT(18) => x_addr_out3_n_135,
PCOUT(17) => x_addr_out3_n_136,
PCOUT(16) => x_addr_out3_n_137,
PCOUT(15) => x_addr_out3_n_138,
PCOUT(14) => x_addr_out3_n_139,
PCOUT(13) => x_addr_out3_n_140,
PCOUT(12) => x_addr_out3_n_141,
PCOUT(11) => x_addr_out3_n_142,
PCOUT(10) => x_addr_out3_n_143,
PCOUT(9) => x_addr_out3_n_144,
PCOUT(8) => x_addr_out3_n_145,
PCOUT(7) => x_addr_out3_n_146,
PCOUT(6) => x_addr_out3_n_147,
PCOUT(5) => x_addr_out3_n_148,
PCOUT(4) => x_addr_out3_n_149,
PCOUT(3) => x_addr_out3_n_150,
PCOUT(2) => x_addr_out3_n_151,
PCOUT(1) => x_addr_out3_n_152,
PCOUT(0) => x_addr_out3_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_x_addr_out3_UNDERFLOW_UNCONNECTED
);
\x_addr_out3__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m01(15),
A(28) => rot_m01(15),
A(27) => rot_m01(15),
A(26) => rot_m01(15),
A(25) => rot_m01(15),
A(24) => rot_m01(15),
A(23) => rot_m01(15),
A(22) => rot_m01(15),
A(21) => rot_m01(15),
A(20) => rot_m01(15),
A(19) => rot_m01(15),
A(18) => rot_m01(15),
A(17) => rot_m01(15),
A(16) => rot_m01(15),
A(15 downto 0) => rot_m01(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => y_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__0_n_58\,
P(46) => \x_addr_out3__0_n_59\,
P(45) => \x_addr_out3__0_n_60\,
P(44) => \x_addr_out3__0_n_61\,
P(43) => \x_addr_out3__0_n_62\,
P(42) => \x_addr_out3__0_n_63\,
P(41) => \x_addr_out3__0_n_64\,
P(40) => \x_addr_out3__0_n_65\,
P(39) => \x_addr_out3__0_n_66\,
P(38) => \x_addr_out3__0_n_67\,
P(37) => \x_addr_out3__0_n_68\,
P(36) => \x_addr_out3__0_n_69\,
P(35) => \x_addr_out3__0_n_70\,
P(34) => \x_addr_out3__0_n_71\,
P(33) => \x_addr_out3__0_n_72\,
P(32) => \x_addr_out3__0_n_73\,
P(31) => \x_addr_out3__0_n_74\,
P(30) => \x_addr_out3__0_n_75\,
P(29) => \x_addr_out3__0_n_76\,
P(28) => \x_addr_out3__0_n_77\,
P(27) => \x_addr_out3__0_n_78\,
P(26) => \x_addr_out3__0_n_79\,
P(25) => \x_addr_out3__0_n_80\,
P(24) => \x_addr_out3__0_n_81\,
P(23) => \x_addr_out3__0_n_82\,
P(22) => \x_addr_out3__0_n_83\,
P(21) => \x_addr_out3__0_n_84\,
P(20) => \x_addr_out3__0_n_85\,
P(19) => \x_addr_out3__0_n_86\,
P(18) => \x_addr_out3__0_n_87\,
P(17) => \x_addr_out3__0_n_88\,
P(16) => \x_addr_out3__0_n_89\,
P(15) => \x_addr_out3__0_n_90\,
P(14) => \x_addr_out3__0_n_91\,
P(13) => \x_addr_out3__0_n_92\,
P(12) => \x_addr_out3__0_n_93\,
P(11) => \x_addr_out3__0_n_94\,
P(10) => \x_addr_out3__0_n_95\,
P(9) => \x_addr_out3__0_n_96\,
P(8) => \x_addr_out3__0_n_97\,
P(7) => \x_addr_out3__0_n_98\,
P(6) => \x_addr_out3__0_n_99\,
P(5) => \x_addr_out3__0_n_100\,
P(4) => \x_addr_out3__0_n_101\,
P(3) => \x_addr_out3__0_n_102\,
P(2) => \x_addr_out3__0_n_103\,
P(1) => \x_addr_out3__0_n_104\,
P(0) => \x_addr_out3__0_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => x_addr_out3_n_106,
PCIN(46) => x_addr_out3_n_107,
PCIN(45) => x_addr_out3_n_108,
PCIN(44) => x_addr_out3_n_109,
PCIN(43) => x_addr_out3_n_110,
PCIN(42) => x_addr_out3_n_111,
PCIN(41) => x_addr_out3_n_112,
PCIN(40) => x_addr_out3_n_113,
PCIN(39) => x_addr_out3_n_114,
PCIN(38) => x_addr_out3_n_115,
PCIN(37) => x_addr_out3_n_116,
PCIN(36) => x_addr_out3_n_117,
PCIN(35) => x_addr_out3_n_118,
PCIN(34) => x_addr_out3_n_119,
PCIN(33) => x_addr_out3_n_120,
PCIN(32) => x_addr_out3_n_121,
PCIN(31) => x_addr_out3_n_122,
PCIN(30) => x_addr_out3_n_123,
PCIN(29) => x_addr_out3_n_124,
PCIN(28) => x_addr_out3_n_125,
PCIN(27) => x_addr_out3_n_126,
PCIN(26) => x_addr_out3_n_127,
PCIN(25) => x_addr_out3_n_128,
PCIN(24) => x_addr_out3_n_129,
PCIN(23) => x_addr_out3_n_130,
PCIN(22) => x_addr_out3_n_131,
PCIN(21) => x_addr_out3_n_132,
PCIN(20) => x_addr_out3_n_133,
PCIN(19) => x_addr_out3_n_134,
PCIN(18) => x_addr_out3_n_135,
PCIN(17) => x_addr_out3_n_136,
PCIN(16) => x_addr_out3_n_137,
PCIN(15) => x_addr_out3_n_138,
PCIN(14) => x_addr_out3_n_139,
PCIN(13) => x_addr_out3_n_140,
PCIN(12) => x_addr_out3_n_141,
PCIN(11) => x_addr_out3_n_142,
PCIN(10) => x_addr_out3_n_143,
PCIN(9) => x_addr_out3_n_144,
PCIN(8) => x_addr_out3_n_145,
PCIN(7) => x_addr_out3_n_146,
PCIN(6) => x_addr_out3_n_147,
PCIN(5) => x_addr_out3_n_148,
PCIN(4) => x_addr_out3_n_149,
PCIN(3) => x_addr_out3_n_150,
PCIN(2) => x_addr_out3_n_151,
PCIN(1) => x_addr_out3_n_152,
PCIN(0) => x_addr_out3_n_153,
PCOUT(47 downto 0) => \NLW_x_addr_out3__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED\
);
\x_addr_out3__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => x_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m00(15),
B(16) => rot_m00(15),
B(15 downto 0) => rot_m00(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => \NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__1_n_58\,
P(46) => \x_addr_out3__1_n_59\,
P(45) => \x_addr_out3__1_n_60\,
P(44) => \x_addr_out3__1_n_61\,
P(43) => \x_addr_out3__1_n_62\,
P(42) => \x_addr_out3__1_n_63\,
P(41) => \x_addr_out3__1_n_64\,
P(40) => \x_addr_out3__1_n_65\,
P(39) => \x_addr_out3__1_n_66\,
P(38) => \x_addr_out3__1_n_67\,
P(37) => \x_addr_out3__1_n_68\,
P(36) => \x_addr_out3__1_n_69\,
P(35) => \x_addr_out3__1_n_70\,
P(34) => \x_addr_out3__1_n_71\,
P(33) => \x_addr_out3__1_n_72\,
P(32) => \x_addr_out3__1_n_73\,
P(31) => \x_addr_out3__1_n_74\,
P(30) => \x_addr_out3__1_n_75\,
P(29) => \x_addr_out3__1_n_76\,
P(28) => \x_addr_out3__1_n_77\,
P(27) => \x_addr_out3__1_n_78\,
P(26) => \x_addr_out3__1_n_79\,
P(25) => \x_addr_out3__1_n_80\,
P(24) => \x_addr_out3__1_n_81\,
P(23) => \x_addr_out3__1_n_82\,
P(22) => \x_addr_out3__1_n_83\,
P(21) => \x_addr_out3__1_n_84\,
P(20) => \x_addr_out3__1_n_85\,
P(19) => \x_addr_out3__1_n_86\,
P(18) => \x_addr_out3__1_n_87\,
P(17) => \x_addr_out3__1_n_88\,
P(16) => \x_addr_out3__1_n_89\,
P(15) => \x_addr_out3__1_n_90\,
P(14) => \x_addr_out3__1_n_91\,
P(13) => \x_addr_out3__1_n_92\,
P(12) => \x_addr_out3__1_n_93\,
P(11) => \x_addr_out3__1_n_94\,
P(10) => \x_addr_out3__1_n_95\,
P(9) => \x_addr_out3__1_n_96\,
P(8) => \x_addr_out3__1_n_97\,
P(7) => \x_addr_out3__1_n_98\,
P(6) => \x_addr_out3__1_n_99\,
P(5) => \x_addr_out3__1_n_100\,
P(4) => \x_addr_out3__1_n_101\,
P(3) => \x_addr_out3__1_n_102\,
P(2) => \x_addr_out3__1_n_103\,
P(1) => \x_addr_out3__1_n_104\,
P(0) => \x_addr_out3__1_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => \x_addr_out3__1_n_106\,
PCOUT(46) => \x_addr_out3__1_n_107\,
PCOUT(45) => \x_addr_out3__1_n_108\,
PCOUT(44) => \x_addr_out3__1_n_109\,
PCOUT(43) => \x_addr_out3__1_n_110\,
PCOUT(42) => \x_addr_out3__1_n_111\,
PCOUT(41) => \x_addr_out3__1_n_112\,
PCOUT(40) => \x_addr_out3__1_n_113\,
PCOUT(39) => \x_addr_out3__1_n_114\,
PCOUT(38) => \x_addr_out3__1_n_115\,
PCOUT(37) => \x_addr_out3__1_n_116\,
PCOUT(36) => \x_addr_out3__1_n_117\,
PCOUT(35) => \x_addr_out3__1_n_118\,
PCOUT(34) => \x_addr_out3__1_n_119\,
PCOUT(33) => \x_addr_out3__1_n_120\,
PCOUT(32) => \x_addr_out3__1_n_121\,
PCOUT(31) => \x_addr_out3__1_n_122\,
PCOUT(30) => \x_addr_out3__1_n_123\,
PCOUT(29) => \x_addr_out3__1_n_124\,
PCOUT(28) => \x_addr_out3__1_n_125\,
PCOUT(27) => \x_addr_out3__1_n_126\,
PCOUT(26) => \x_addr_out3__1_n_127\,
PCOUT(25) => \x_addr_out3__1_n_128\,
PCOUT(24) => \x_addr_out3__1_n_129\,
PCOUT(23) => \x_addr_out3__1_n_130\,
PCOUT(22) => \x_addr_out3__1_n_131\,
PCOUT(21) => \x_addr_out3__1_n_132\,
PCOUT(20) => \x_addr_out3__1_n_133\,
PCOUT(19) => \x_addr_out3__1_n_134\,
PCOUT(18) => \x_addr_out3__1_n_135\,
PCOUT(17) => \x_addr_out3__1_n_136\,
PCOUT(16) => \x_addr_out3__1_n_137\,
PCOUT(15) => \x_addr_out3__1_n_138\,
PCOUT(14) => \x_addr_out3__1_n_139\,
PCOUT(13) => \x_addr_out3__1_n_140\,
PCOUT(12) => \x_addr_out3__1_n_141\,
PCOUT(11) => \x_addr_out3__1_n_142\,
PCOUT(10) => \x_addr_out3__1_n_143\,
PCOUT(9) => \x_addr_out3__1_n_144\,
PCOUT(8) => \x_addr_out3__1_n_145\,
PCOUT(7) => \x_addr_out3__1_n_146\,
PCOUT(6) => \x_addr_out3__1_n_147\,
PCOUT(5) => \x_addr_out3__1_n_148\,
PCOUT(4) => \x_addr_out3__1_n_149\,
PCOUT(3) => \x_addr_out3__1_n_150\,
PCOUT(2) => \x_addr_out3__1_n_151\,
PCOUT(1) => \x_addr_out3__1_n_152\,
PCOUT(0) => \x_addr_out3__1_n_153\,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED\
);
\x_addr_out3__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m00(15),
A(28) => rot_m00(15),
A(27) => rot_m00(15),
A(26) => rot_m00(15),
A(25) => rot_m00(15),
A(24) => rot_m00(15),
A(23) => rot_m00(15),
A(22) => rot_m00(15),
A(21) => rot_m00(15),
A(20) => rot_m00(15),
A(19) => rot_m00(15),
A(18) => rot_m00(15),
A(17) => rot_m00(15),
A(16) => rot_m00(15),
A(15 downto 0) => rot_m00(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => x_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__2_n_58\,
P(46) => \x_addr_out3__2_n_59\,
P(45) => \x_addr_out3__2_n_60\,
P(44) => \x_addr_out3__2_n_61\,
P(43) => \x_addr_out3__2_n_62\,
P(42) => \x_addr_out3__2_n_63\,
P(41) => \x_addr_out3__2_n_64\,
P(40) => \x_addr_out3__2_n_65\,
P(39) => \x_addr_out3__2_n_66\,
P(38) => \x_addr_out3__2_n_67\,
P(37) => \x_addr_out3__2_n_68\,
P(36) => \x_addr_out3__2_n_69\,
P(35) => \x_addr_out3__2_n_70\,
P(34) => \x_addr_out3__2_n_71\,
P(33) => \x_addr_out3__2_n_72\,
P(32) => \x_addr_out3__2_n_73\,
P(31) => \x_addr_out3__2_n_74\,
P(30) => \x_addr_out3__2_n_75\,
P(29) => \x_addr_out3__2_n_76\,
P(28) => \x_addr_out3__2_n_77\,
P(27) => \x_addr_out3__2_n_78\,
P(26) => \x_addr_out3__2_n_79\,
P(25) => \x_addr_out3__2_n_80\,
P(24) => \x_addr_out3__2_n_81\,
P(23) => \x_addr_out3__2_n_82\,
P(22) => \x_addr_out3__2_n_83\,
P(21) => \x_addr_out3__2_n_84\,
P(20) => \x_addr_out3__2_n_85\,
P(19) => \x_addr_out3__2_n_86\,
P(18) => \x_addr_out3__2_n_87\,
P(17) => \x_addr_out3__2_n_88\,
P(16) => \x_addr_out3__2_n_89\,
P(15) => \x_addr_out3__2_n_90\,
P(14) => \x_addr_out3__2_n_91\,
P(13) => \x_addr_out3__2_n_92\,
P(12) => \x_addr_out3__2_n_93\,
P(11) => \x_addr_out3__2_n_94\,
P(10) => \x_addr_out3__2_n_95\,
P(9) => \x_addr_out3__2_n_96\,
P(8) => \x_addr_out3__2_n_97\,
P(7) => \x_addr_out3__2_n_98\,
P(6) => \x_addr_out3__2_n_99\,
P(5) => \x_addr_out3__2_n_100\,
P(4) => \x_addr_out3__2_n_101\,
P(3) => \x_addr_out3__2_n_102\,
P(2) => \x_addr_out3__2_n_103\,
P(1) => \x_addr_out3__2_n_104\,
P(0) => \x_addr_out3__2_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => \x_addr_out3__1_n_106\,
PCIN(46) => \x_addr_out3__1_n_107\,
PCIN(45) => \x_addr_out3__1_n_108\,
PCIN(44) => \x_addr_out3__1_n_109\,
PCIN(43) => \x_addr_out3__1_n_110\,
PCIN(42) => \x_addr_out3__1_n_111\,
PCIN(41) => \x_addr_out3__1_n_112\,
PCIN(40) => \x_addr_out3__1_n_113\,
PCIN(39) => \x_addr_out3__1_n_114\,
PCIN(38) => \x_addr_out3__1_n_115\,
PCIN(37) => \x_addr_out3__1_n_116\,
PCIN(36) => \x_addr_out3__1_n_117\,
PCIN(35) => \x_addr_out3__1_n_118\,
PCIN(34) => \x_addr_out3__1_n_119\,
PCIN(33) => \x_addr_out3__1_n_120\,
PCIN(32) => \x_addr_out3__1_n_121\,
PCIN(31) => \x_addr_out3__1_n_122\,
PCIN(30) => \x_addr_out3__1_n_123\,
PCIN(29) => \x_addr_out3__1_n_124\,
PCIN(28) => \x_addr_out3__1_n_125\,
PCIN(27) => \x_addr_out3__1_n_126\,
PCIN(26) => \x_addr_out3__1_n_127\,
PCIN(25) => \x_addr_out3__1_n_128\,
PCIN(24) => \x_addr_out3__1_n_129\,
PCIN(23) => \x_addr_out3__1_n_130\,
PCIN(22) => \x_addr_out3__1_n_131\,
PCIN(21) => \x_addr_out3__1_n_132\,
PCIN(20) => \x_addr_out3__1_n_133\,
PCIN(19) => \x_addr_out3__1_n_134\,
PCIN(18) => \x_addr_out3__1_n_135\,
PCIN(17) => \x_addr_out3__1_n_136\,
PCIN(16) => \x_addr_out3__1_n_137\,
PCIN(15) => \x_addr_out3__1_n_138\,
PCIN(14) => \x_addr_out3__1_n_139\,
PCIN(13) => \x_addr_out3__1_n_140\,
PCIN(12) => \x_addr_out3__1_n_141\,
PCIN(11) => \x_addr_out3__1_n_142\,
PCIN(10) => \x_addr_out3__1_n_143\,
PCIN(9) => \x_addr_out3__1_n_144\,
PCIN(8) => \x_addr_out3__1_n_145\,
PCIN(7) => \x_addr_out3__1_n_146\,
PCIN(6) => \x_addr_out3__1_n_147\,
PCIN(5) => \x_addr_out3__1_n_148\,
PCIN(4) => \x_addr_out3__1_n_149\,
PCIN(3) => \x_addr_out3__1_n_150\,
PCIN(2) => \x_addr_out3__1_n_151\,
PCIN(1) => \x_addr_out3__1_n_152\,
PCIN(0) => \x_addr_out3__1_n_153\,
PCOUT(47 downto 0) => \NLW_x_addr_out3__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED\
);
\x_addr_out[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"66F0"
)
port map (
I0 => p_1_in(14),
I1 => t_x(0),
I2 => x_addr_in(0),
I3 => enable,
O => \x_addr_out[0]_i_1_n_0\
);
\x_addr_out[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(15),
I1 => x_addr_in(1),
I2 => enable,
O => \x_addr_out[1]_i_1_n_0\
);
\x_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(16),
I1 => x_addr_in(2),
I2 => enable,
O => \x_addr_out[2]_i_1_n_0\
);
\x_addr_out[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(17),
I1 => x_addr_in(3),
I2 => enable,
O => \x_addr_out[3]_i_1_n_0\
);
\x_addr_out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(18),
I1 => x_addr_in(4),
I2 => enable,
O => \x_addr_out[4]_i_1_n_0\
);
\x_addr_out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(19),
I1 => x_addr_in(5),
I2 => enable,
O => \x_addr_out[5]_i_1_n_0\
);
\x_addr_out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(20),
I1 => x_addr_in(6),
I2 => enable,
O => \x_addr_out[6]_i_1_n_0\
);
\x_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(21),
I1 => x_addr_in(7),
I2 => enable,
O => \x_addr_out[7]_i_1_n_0\
);
\x_addr_out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(22),
I1 => x_addr_in(8),
I2 => enable,
O => \x_addr_out[8]_i_1_n_0\
);
\x_addr_out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(23),
I1 => x_addr_in(9),
I2 => enable,
O => \x_addr_out[9]_i_1_n_0\
);
\x_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[0]_i_1_n_0\,
Q => x_addr_out(0),
R => '0'
);
\x_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[1]_i_1_n_0\,
Q => x_addr_out(1),
R => '0'
);
\x_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[2]_i_1_n_0\,
Q => x_addr_out(2),
R => '0'
);
\x_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[3]_i_1_n_0\,
Q => x_addr_out(3),
R => '0'
);
\x_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[4]_i_1_n_0\,
Q => x_addr_out(4),
R => '0'
);
\x_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[5]_i_1_n_0\,
Q => x_addr_out(5),
R => '0'
);
\x_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[6]_i_1_n_0\,
Q => x_addr_out(6),
R => '0'
);
\x_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[7]_i_1_n_0\,
Q => x_addr_out(7),
R => '0'
);
\x_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[8]_i_1_n_0\,
Q => x_addr_out(8),
R => '0'
);
\x_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[9]_i_1_n_0\,
Q => x_addr_out(9),
R => '0'
);
y_addr_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y_addr_out0_carry_n_0,
CO(2) => y_addr_out0_carry_n_1,
CO(1) => y_addr_out0_carry_n_2,
CO(0) => y_addr_out0_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => y_addr_out2(31 downto 28),
O(3 downto 1) => p_0_in(3 downto 1),
O(0) => NLW_y_addr_out0_carry_O_UNCONNECTED(0),
S(3) => y_addr_out0_carry_i_1_n_0,
S(2) => y_addr_out0_carry_i_2_n_0,
S(1) => y_addr_out0_carry_i_3_n_0,
S(0) => y_addr_out0_carry_i_4_n_0
);
\y_addr_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y_addr_out0_carry_n_0,
CO(3) => \y_addr_out0_carry__0_n_0\,
CO(2) => \y_addr_out0_carry__0_n_1\,
CO(1) => \y_addr_out0_carry__0_n_2\,
CO(0) => \y_addr_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => y_addr_out2(35 downto 32),
O(3 downto 0) => p_0_in(7 downto 4),
S(3) => \y_addr_out0_carry__0_i_1_n_0\,
S(2) => \y_addr_out0_carry__0_i_2_n_0\,
S(1) => \y_addr_out0_carry__0_i_3_n_0\,
S(0) => \y_addr_out0_carry__0_i_4_n_0\
);
\y_addr_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(35),
I1 => t_y(7),
O => \y_addr_out0_carry__0_i_1_n_0\
);
\y_addr_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(34),
I1 => t_y(6),
O => \y_addr_out0_carry__0_i_2_n_0\
);
\y_addr_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(33),
I1 => t_y(5),
O => \y_addr_out0_carry__0_i_3_n_0\
);
\y_addr_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(32),
I1 => t_y(4),
O => \y_addr_out0_carry__0_i_4_n_0\
);
\y_addr_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out0_carry__0_n_0\,
CO(3 downto 1) => \NLW_y_addr_out0_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_addr_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => y_addr_out2(36),
O(3 downto 2) => \NLW_y_addr_out0_carry__1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => p_0_in(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \y_addr_out0_carry__1_i_1_n_0\,
S(0) => \y_addr_out0_carry__1_i_2_n_0\
);
\y_addr_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(37),
I1 => t_y(9),
O => \y_addr_out0_carry__1_i_1_n_0\
);
\y_addr_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(36),
I1 => t_y(8),
O => \y_addr_out0_carry__1_i_2_n_0\
);
y_addr_out0_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(31),
I1 => t_y(3),
O => y_addr_out0_carry_i_1_n_0
);
y_addr_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(30),
I1 => t_y(2),
O => y_addr_out0_carry_i_2_n_0
);
y_addr_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(29),
I1 => t_y(1),
O => y_addr_out0_carry_i_3_n_0
);
y_addr_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(28),
I1 => t_y(0),
O => y_addr_out0_carry_i_4_n_0
);
y_addr_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y_addr_out2_carry_n_0,
CO(2) => y_addr_out2_carry_n_1,
CO(1) => y_addr_out2_carry_n_2,
CO(0) => y_addr_out2_carry_n_3,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_102\,
DI(2) => \y_addr_out3__1_n_103\,
DI(1) => \y_addr_out3__1_n_104\,
DI(0) => \y_addr_out3__1_n_105\,
O(3 downto 0) => NLW_y_addr_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => y_addr_out2_carry_i_1_n_0,
S(2) => y_addr_out2_carry_i_2_n_0,
S(1) => y_addr_out2_carry_i_3_n_0,
S(0) => y_addr_out2_carry_i_4_n_0
);
\y_addr_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y_addr_out2_carry_n_0,
CO(3) => \y_addr_out2_carry__0_n_0\,
CO(2) => \y_addr_out2_carry__0_n_1\,
CO(1) => \y_addr_out2_carry__0_n_2\,
CO(0) => \y_addr_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_98\,
DI(2) => \y_addr_out3__1_n_99\,
DI(1) => \y_addr_out3__1_n_100\,
DI(0) => \y_addr_out3__1_n_101\,
O(3 downto 0) => \NLW_y_addr_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__0_i_1_n_0\,
S(2) => \y_addr_out2_carry__0_i_2_n_0\,
S(1) => \y_addr_out2_carry__0_i_3_n_0\,
S(0) => \y_addr_out2_carry__0_i_4_n_0\
);
\y_addr_out2_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_98\,
I1 => y_addr_out3_n_98,
O => \y_addr_out2_carry__0_i_1_n_0\
);
\y_addr_out2_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_99\,
I1 => y_addr_out3_n_99,
O => \y_addr_out2_carry__0_i_2_n_0\
);
\y_addr_out2_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_100\,
I1 => y_addr_out3_n_100,
O => \y_addr_out2_carry__0_i_3_n_0\
);
\y_addr_out2_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_101\,
I1 => y_addr_out3_n_101,
O => \y_addr_out2_carry__0_i_4_n_0\
);
\y_addr_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__0_n_0\,
CO(3) => \y_addr_out2_carry__1_n_0\,
CO(2) => \y_addr_out2_carry__1_n_1\,
CO(1) => \y_addr_out2_carry__1_n_2\,
CO(0) => \y_addr_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_94\,
DI(2) => \y_addr_out3__1_n_95\,
DI(1) => \y_addr_out3__1_n_96\,
DI(0) => \y_addr_out3__1_n_97\,
O(3 downto 0) => \NLW_y_addr_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__1_i_1_n_0\,
S(2) => \y_addr_out2_carry__1_i_2_n_0\,
S(1) => \y_addr_out2_carry__1_i_3_n_0\,
S(0) => \y_addr_out2_carry__1_i_4_n_0\
);
\y_addr_out2_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_94\,
I1 => y_addr_out3_n_94,
O => \y_addr_out2_carry__1_i_1_n_0\
);
\y_addr_out2_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_95\,
I1 => y_addr_out3_n_95,
O => \y_addr_out2_carry__1_i_2_n_0\
);
\y_addr_out2_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_96\,
I1 => y_addr_out3_n_96,
O => \y_addr_out2_carry__1_i_3_n_0\
);
\y_addr_out2_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_97\,
I1 => y_addr_out3_n_97,
O => \y_addr_out2_carry__1_i_4_n_0\
);
\y_addr_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__1_n_0\,
CO(3) => \y_addr_out2_carry__2_n_0\,
CO(2) => \y_addr_out2_carry__2_n_1\,
CO(1) => \y_addr_out2_carry__2_n_2\,
CO(0) => \y_addr_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_90\,
DI(2) => \y_addr_out3__1_n_91\,
DI(1) => \y_addr_out3__1_n_92\,
DI(0) => \y_addr_out3__1_n_93\,
O(3 downto 0) => \NLW_y_addr_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__2_i_1_n_0\,
S(2) => \y_addr_out2_carry__2_i_2_n_0\,
S(1) => \y_addr_out2_carry__2_i_3_n_0\,
S(0) => \y_addr_out2_carry__2_i_4_n_0\
);
\y_addr_out2_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_90\,
I1 => y_addr_out3_n_90,
O => \y_addr_out2_carry__2_i_1_n_0\
);
\y_addr_out2_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_91\,
I1 => y_addr_out3_n_91,
O => \y_addr_out2_carry__2_i_2_n_0\
);
\y_addr_out2_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_92\,
I1 => y_addr_out3_n_92,
O => \y_addr_out2_carry__2_i_3_n_0\
);
\y_addr_out2_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_93\,
I1 => y_addr_out3_n_93,
O => \y_addr_out2_carry__2_i_4_n_0\
);
\y_addr_out2_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__2_n_0\,
CO(3) => \y_addr_out2_carry__3_n_0\,
CO(2) => \y_addr_out2_carry__3_n_1\,
CO(1) => \y_addr_out2_carry__3_n_2\,
CO(0) => \y_addr_out2_carry__3_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_103\,
DI(2) => \y_addr_out3__2_n_104\,
DI(1) => \y_addr_out3__2_n_105\,
DI(0) => \y_addr_out3__1_n_89\,
O(3 downto 0) => \NLW_y_addr_out2_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__3_i_1_n_0\,
S(2) => \y_addr_out2_carry__3_i_2_n_0\,
S(1) => \y_addr_out2_carry__3_i_3_n_0\,
S(0) => \y_addr_out2_carry__3_i_4_n_0\
);
\y_addr_out2_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_103\,
I1 => \y_addr_out3__0_n_103\,
O => \y_addr_out2_carry__3_i_1_n_0\
);
\y_addr_out2_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_104\,
I1 => \y_addr_out3__0_n_104\,
O => \y_addr_out2_carry__3_i_2_n_0\
);
\y_addr_out2_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_105\,
I1 => \y_addr_out3__0_n_105\,
O => \y_addr_out2_carry__3_i_3_n_0\
);
\y_addr_out2_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_89\,
I1 => y_addr_out3_n_89,
O => \y_addr_out2_carry__3_i_4_n_0\
);
\y_addr_out2_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__3_n_0\,
CO(3) => \y_addr_out2_carry__4_n_0\,
CO(2) => \y_addr_out2_carry__4_n_1\,
CO(1) => \y_addr_out2_carry__4_n_2\,
CO(0) => \y_addr_out2_carry__4_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_99\,
DI(2) => \y_addr_out3__2_n_100\,
DI(1) => \y_addr_out3__2_n_101\,
DI(0) => \y_addr_out3__2_n_102\,
O(3 downto 0) => \NLW_y_addr_out2_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__4_i_1_n_0\,
S(2) => \y_addr_out2_carry__4_i_2_n_0\,
S(1) => \y_addr_out2_carry__4_i_3_n_0\,
S(0) => \y_addr_out2_carry__4_i_4_n_0\
);
\y_addr_out2_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_99\,
I1 => \y_addr_out3__0_n_99\,
O => \y_addr_out2_carry__4_i_1_n_0\
);
\y_addr_out2_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_100\,
I1 => \y_addr_out3__0_n_100\,
O => \y_addr_out2_carry__4_i_2_n_0\
);
\y_addr_out2_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_101\,
I1 => \y_addr_out3__0_n_101\,
O => \y_addr_out2_carry__4_i_3_n_0\
);
\y_addr_out2_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_102\,
I1 => \y_addr_out3__0_n_102\,
O => \y_addr_out2_carry__4_i_4_n_0\
);
\y_addr_out2_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__4_n_0\,
CO(3) => \y_addr_out2_carry__5_n_0\,
CO(2) => \y_addr_out2_carry__5_n_1\,
CO(1) => \y_addr_out2_carry__5_n_2\,
CO(0) => \y_addr_out2_carry__5_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_95\,
DI(2) => \y_addr_out3__2_n_96\,
DI(1) => \y_addr_out3__2_n_97\,
DI(0) => \y_addr_out3__2_n_98\,
O(3 downto 0) => \NLW_y_addr_out2_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__5_i_1_n_0\,
S(2) => \y_addr_out2_carry__5_i_2_n_0\,
S(1) => \y_addr_out2_carry__5_i_3_n_0\,
S(0) => \y_addr_out2_carry__5_i_4_n_0\
);
\y_addr_out2_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_95\,
I1 => \y_addr_out3__0_n_95\,
O => \y_addr_out2_carry__5_i_1_n_0\
);
\y_addr_out2_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_96\,
I1 => \y_addr_out3__0_n_96\,
O => \y_addr_out2_carry__5_i_2_n_0\
);
\y_addr_out2_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_97\,
I1 => \y_addr_out3__0_n_97\,
O => \y_addr_out2_carry__5_i_3_n_0\
);
\y_addr_out2_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_98\,
I1 => \y_addr_out3__0_n_98\,
O => \y_addr_out2_carry__5_i_4_n_0\
);
\y_addr_out2_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__5_n_0\,
CO(3) => \y_addr_out2_carry__6_n_0\,
CO(2) => \y_addr_out2_carry__6_n_1\,
CO(1) => \y_addr_out2_carry__6_n_2\,
CO(0) => \y_addr_out2_carry__6_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_91\,
DI(2) => \y_addr_out3__2_n_92\,
DI(1) => \y_addr_out3__2_n_93\,
DI(0) => \y_addr_out3__2_n_94\,
O(3 downto 0) => y_addr_out2(31 downto 28),
S(3) => \y_addr_out2_carry__6_i_1_n_0\,
S(2) => \y_addr_out2_carry__6_i_2_n_0\,
S(1) => \y_addr_out2_carry__6_i_3_n_0\,
S(0) => \y_addr_out2_carry__6_i_4_n_0\
);
\y_addr_out2_carry__6_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_91\,
I1 => \y_addr_out3__0_n_91\,
O => \y_addr_out2_carry__6_i_1_n_0\
);
\y_addr_out2_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_92\,
I1 => \y_addr_out3__0_n_92\,
O => \y_addr_out2_carry__6_i_2_n_0\
);
\y_addr_out2_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_93\,
I1 => \y_addr_out3__0_n_93\,
O => \y_addr_out2_carry__6_i_3_n_0\
);
\y_addr_out2_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_94\,
I1 => \y_addr_out3__0_n_94\,
O => \y_addr_out2_carry__6_i_4_n_0\
);
\y_addr_out2_carry__7\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__6_n_0\,
CO(3) => \y_addr_out2_carry__7_n_0\,
CO(2) => \y_addr_out2_carry__7_n_1\,
CO(1) => \y_addr_out2_carry__7_n_2\,
CO(0) => \y_addr_out2_carry__7_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_87\,
DI(2) => \y_addr_out3__2_n_88\,
DI(1) => \y_addr_out3__2_n_89\,
DI(0) => \y_addr_out3__2_n_90\,
O(3 downto 0) => y_addr_out2(35 downto 32),
S(3) => \y_addr_out2_carry__7_i_1_n_0\,
S(2) => \y_addr_out2_carry__7_i_2_n_0\,
S(1) => \y_addr_out2_carry__7_i_3_n_0\,
S(0) => \y_addr_out2_carry__7_i_4_n_0\
);
\y_addr_out2_carry__7_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_87\,
I1 => \y_addr_out3__0_n_87\,
O => \y_addr_out2_carry__7_i_1_n_0\
);
\y_addr_out2_carry__7_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_88\,
I1 => \y_addr_out3__0_n_88\,
O => \y_addr_out2_carry__7_i_2_n_0\
);
\y_addr_out2_carry__7_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_89\,
I1 => \y_addr_out3__0_n_89\,
O => \y_addr_out2_carry__7_i_3_n_0\
);
\y_addr_out2_carry__7_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_90\,
I1 => \y_addr_out3__0_n_90\,
O => \y_addr_out2_carry__7_i_4_n_0\
);
\y_addr_out2_carry__8\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__7_n_0\,
CO(3 downto 1) => \NLW_y_addr_out2_carry__8_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_addr_out2_carry__8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_addr_out3__2_n_86\,
O(3 downto 2) => \NLW_y_addr_out2_carry__8_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_addr_out2(37 downto 36),
S(3 downto 2) => B"00",
S(1) => \y_addr_out2_carry__8_i_1_n_0\,
S(0) => \y_addr_out2_carry__8_i_2_n_0\
);
\y_addr_out2_carry__8_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_85\,
I1 => \y_addr_out3__0_n_85\,
O => \y_addr_out2_carry__8_i_1_n_0\
);
\y_addr_out2_carry__8_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_86\,
I1 => \y_addr_out3__0_n_86\,
O => \y_addr_out2_carry__8_i_2_n_0\
);
y_addr_out2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_102\,
I1 => y_addr_out3_n_102,
O => y_addr_out2_carry_i_1_n_0
);
y_addr_out2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_103\,
I1 => y_addr_out3_n_103,
O => y_addr_out2_carry_i_2_n_0
);
y_addr_out2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_104\,
I1 => y_addr_out3_n_104,
O => y_addr_out2_carry_i_3_n_0
);
y_addr_out2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_105\,
I1 => y_addr_out3_n_105,
O => y_addr_out2_carry_i_4_n_0
);
y_addr_out3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => y_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_y_addr_out3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m11(15),
B(16) => rot_m11(15),
B(15 downto 0) => rot_m11(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_y_addr_out3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_y_addr_out3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_y_addr_out3_OVERFLOW_UNCONNECTED,
P(47) => y_addr_out3_n_58,
P(46) => y_addr_out3_n_59,
P(45) => y_addr_out3_n_60,
P(44) => y_addr_out3_n_61,
P(43) => y_addr_out3_n_62,
P(42) => y_addr_out3_n_63,
P(41) => y_addr_out3_n_64,
P(40) => y_addr_out3_n_65,
P(39) => y_addr_out3_n_66,
P(38) => y_addr_out3_n_67,
P(37) => y_addr_out3_n_68,
P(36) => y_addr_out3_n_69,
P(35) => y_addr_out3_n_70,
P(34) => y_addr_out3_n_71,
P(33) => y_addr_out3_n_72,
P(32) => y_addr_out3_n_73,
P(31) => y_addr_out3_n_74,
P(30) => y_addr_out3_n_75,
P(29) => y_addr_out3_n_76,
P(28) => y_addr_out3_n_77,
P(27) => y_addr_out3_n_78,
P(26) => y_addr_out3_n_79,
P(25) => y_addr_out3_n_80,
P(24) => y_addr_out3_n_81,
P(23) => y_addr_out3_n_82,
P(22) => y_addr_out3_n_83,
P(21) => y_addr_out3_n_84,
P(20) => y_addr_out3_n_85,
P(19) => y_addr_out3_n_86,
P(18) => y_addr_out3_n_87,
P(17) => y_addr_out3_n_88,
P(16) => y_addr_out3_n_89,
P(15) => y_addr_out3_n_90,
P(14) => y_addr_out3_n_91,
P(13) => y_addr_out3_n_92,
P(12) => y_addr_out3_n_93,
P(11) => y_addr_out3_n_94,
P(10) => y_addr_out3_n_95,
P(9) => y_addr_out3_n_96,
P(8) => y_addr_out3_n_97,
P(7) => y_addr_out3_n_98,
P(6) => y_addr_out3_n_99,
P(5) => y_addr_out3_n_100,
P(4) => y_addr_out3_n_101,
P(3) => y_addr_out3_n_102,
P(2) => y_addr_out3_n_103,
P(1) => y_addr_out3_n_104,
P(0) => y_addr_out3_n_105,
PATTERNBDETECT => NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => y_addr_out3_n_106,
PCOUT(46) => y_addr_out3_n_107,
PCOUT(45) => y_addr_out3_n_108,
PCOUT(44) => y_addr_out3_n_109,
PCOUT(43) => y_addr_out3_n_110,
PCOUT(42) => y_addr_out3_n_111,
PCOUT(41) => y_addr_out3_n_112,
PCOUT(40) => y_addr_out3_n_113,
PCOUT(39) => y_addr_out3_n_114,
PCOUT(38) => y_addr_out3_n_115,
PCOUT(37) => y_addr_out3_n_116,
PCOUT(36) => y_addr_out3_n_117,
PCOUT(35) => y_addr_out3_n_118,
PCOUT(34) => y_addr_out3_n_119,
PCOUT(33) => y_addr_out3_n_120,
PCOUT(32) => y_addr_out3_n_121,
PCOUT(31) => y_addr_out3_n_122,
PCOUT(30) => y_addr_out3_n_123,
PCOUT(29) => y_addr_out3_n_124,
PCOUT(28) => y_addr_out3_n_125,
PCOUT(27) => y_addr_out3_n_126,
PCOUT(26) => y_addr_out3_n_127,
PCOUT(25) => y_addr_out3_n_128,
PCOUT(24) => y_addr_out3_n_129,
PCOUT(23) => y_addr_out3_n_130,
PCOUT(22) => y_addr_out3_n_131,
PCOUT(21) => y_addr_out3_n_132,
PCOUT(20) => y_addr_out3_n_133,
PCOUT(19) => y_addr_out3_n_134,
PCOUT(18) => y_addr_out3_n_135,
PCOUT(17) => y_addr_out3_n_136,
PCOUT(16) => y_addr_out3_n_137,
PCOUT(15) => y_addr_out3_n_138,
PCOUT(14) => y_addr_out3_n_139,
PCOUT(13) => y_addr_out3_n_140,
PCOUT(12) => y_addr_out3_n_141,
PCOUT(11) => y_addr_out3_n_142,
PCOUT(10) => y_addr_out3_n_143,
PCOUT(9) => y_addr_out3_n_144,
PCOUT(8) => y_addr_out3_n_145,
PCOUT(7) => y_addr_out3_n_146,
PCOUT(6) => y_addr_out3_n_147,
PCOUT(5) => y_addr_out3_n_148,
PCOUT(4) => y_addr_out3_n_149,
PCOUT(3) => y_addr_out3_n_150,
PCOUT(2) => y_addr_out3_n_151,
PCOUT(1) => y_addr_out3_n_152,
PCOUT(0) => y_addr_out3_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_y_addr_out3_UNDERFLOW_UNCONNECTED
);
\y_addr_out3__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m11(15),
A(28) => rot_m11(15),
A(27) => rot_m11(15),
A(26) => rot_m11(15),
A(25) => rot_m11(15),
A(24) => rot_m11(15),
A(23) => rot_m11(15),
A(22) => rot_m11(15),
A(21) => rot_m11(15),
A(20) => rot_m11(15),
A(19) => rot_m11(15),
A(18) => rot_m11(15),
A(17) => rot_m11(15),
A(16) => rot_m11(15),
A(15 downto 0) => rot_m11(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => y_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__0_n_58\,
P(46) => \y_addr_out3__0_n_59\,
P(45) => \y_addr_out3__0_n_60\,
P(44) => \y_addr_out3__0_n_61\,
P(43) => \y_addr_out3__0_n_62\,
P(42) => \y_addr_out3__0_n_63\,
P(41) => \y_addr_out3__0_n_64\,
P(40) => \y_addr_out3__0_n_65\,
P(39) => \y_addr_out3__0_n_66\,
P(38) => \y_addr_out3__0_n_67\,
P(37) => \y_addr_out3__0_n_68\,
P(36) => \y_addr_out3__0_n_69\,
P(35) => \y_addr_out3__0_n_70\,
P(34) => \y_addr_out3__0_n_71\,
P(33) => \y_addr_out3__0_n_72\,
P(32) => \y_addr_out3__0_n_73\,
P(31) => \y_addr_out3__0_n_74\,
P(30) => \y_addr_out3__0_n_75\,
P(29) => \y_addr_out3__0_n_76\,
P(28) => \y_addr_out3__0_n_77\,
P(27) => \y_addr_out3__0_n_78\,
P(26) => \y_addr_out3__0_n_79\,
P(25) => \y_addr_out3__0_n_80\,
P(24) => \y_addr_out3__0_n_81\,
P(23) => \y_addr_out3__0_n_82\,
P(22) => \y_addr_out3__0_n_83\,
P(21) => \y_addr_out3__0_n_84\,
P(20) => \y_addr_out3__0_n_85\,
P(19) => \y_addr_out3__0_n_86\,
P(18) => \y_addr_out3__0_n_87\,
P(17) => \y_addr_out3__0_n_88\,
P(16) => \y_addr_out3__0_n_89\,
P(15) => \y_addr_out3__0_n_90\,
P(14) => \y_addr_out3__0_n_91\,
P(13) => \y_addr_out3__0_n_92\,
P(12) => \y_addr_out3__0_n_93\,
P(11) => \y_addr_out3__0_n_94\,
P(10) => \y_addr_out3__0_n_95\,
P(9) => \y_addr_out3__0_n_96\,
P(8) => \y_addr_out3__0_n_97\,
P(7) => \y_addr_out3__0_n_98\,
P(6) => \y_addr_out3__0_n_99\,
P(5) => \y_addr_out3__0_n_100\,
P(4) => \y_addr_out3__0_n_101\,
P(3) => \y_addr_out3__0_n_102\,
P(2) => \y_addr_out3__0_n_103\,
P(1) => \y_addr_out3__0_n_104\,
P(0) => \y_addr_out3__0_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => y_addr_out3_n_106,
PCIN(46) => y_addr_out3_n_107,
PCIN(45) => y_addr_out3_n_108,
PCIN(44) => y_addr_out3_n_109,
PCIN(43) => y_addr_out3_n_110,
PCIN(42) => y_addr_out3_n_111,
PCIN(41) => y_addr_out3_n_112,
PCIN(40) => y_addr_out3_n_113,
PCIN(39) => y_addr_out3_n_114,
PCIN(38) => y_addr_out3_n_115,
PCIN(37) => y_addr_out3_n_116,
PCIN(36) => y_addr_out3_n_117,
PCIN(35) => y_addr_out3_n_118,
PCIN(34) => y_addr_out3_n_119,
PCIN(33) => y_addr_out3_n_120,
PCIN(32) => y_addr_out3_n_121,
PCIN(31) => y_addr_out3_n_122,
PCIN(30) => y_addr_out3_n_123,
PCIN(29) => y_addr_out3_n_124,
PCIN(28) => y_addr_out3_n_125,
PCIN(27) => y_addr_out3_n_126,
PCIN(26) => y_addr_out3_n_127,
PCIN(25) => y_addr_out3_n_128,
PCIN(24) => y_addr_out3_n_129,
PCIN(23) => y_addr_out3_n_130,
PCIN(22) => y_addr_out3_n_131,
PCIN(21) => y_addr_out3_n_132,
PCIN(20) => y_addr_out3_n_133,
PCIN(19) => y_addr_out3_n_134,
PCIN(18) => y_addr_out3_n_135,
PCIN(17) => y_addr_out3_n_136,
PCIN(16) => y_addr_out3_n_137,
PCIN(15) => y_addr_out3_n_138,
PCIN(14) => y_addr_out3_n_139,
PCIN(13) => y_addr_out3_n_140,
PCIN(12) => y_addr_out3_n_141,
PCIN(11) => y_addr_out3_n_142,
PCIN(10) => y_addr_out3_n_143,
PCIN(9) => y_addr_out3_n_144,
PCIN(8) => y_addr_out3_n_145,
PCIN(7) => y_addr_out3_n_146,
PCIN(6) => y_addr_out3_n_147,
PCIN(5) => y_addr_out3_n_148,
PCIN(4) => y_addr_out3_n_149,
PCIN(3) => y_addr_out3_n_150,
PCIN(2) => y_addr_out3_n_151,
PCIN(1) => y_addr_out3_n_152,
PCIN(0) => y_addr_out3_n_153,
PCOUT(47 downto 0) => \NLW_y_addr_out3__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED\
);
\y_addr_out3__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => x_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m10(15),
B(16) => rot_m10(15),
B(15 downto 0) => rot_m10(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => \NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__1_n_58\,
P(46) => \y_addr_out3__1_n_59\,
P(45) => \y_addr_out3__1_n_60\,
P(44) => \y_addr_out3__1_n_61\,
P(43) => \y_addr_out3__1_n_62\,
P(42) => \y_addr_out3__1_n_63\,
P(41) => \y_addr_out3__1_n_64\,
P(40) => \y_addr_out3__1_n_65\,
P(39) => \y_addr_out3__1_n_66\,
P(38) => \y_addr_out3__1_n_67\,
P(37) => \y_addr_out3__1_n_68\,
P(36) => \y_addr_out3__1_n_69\,
P(35) => \y_addr_out3__1_n_70\,
P(34) => \y_addr_out3__1_n_71\,
P(33) => \y_addr_out3__1_n_72\,
P(32) => \y_addr_out3__1_n_73\,
P(31) => \y_addr_out3__1_n_74\,
P(30) => \y_addr_out3__1_n_75\,
P(29) => \y_addr_out3__1_n_76\,
P(28) => \y_addr_out3__1_n_77\,
P(27) => \y_addr_out3__1_n_78\,
P(26) => \y_addr_out3__1_n_79\,
P(25) => \y_addr_out3__1_n_80\,
P(24) => \y_addr_out3__1_n_81\,
P(23) => \y_addr_out3__1_n_82\,
P(22) => \y_addr_out3__1_n_83\,
P(21) => \y_addr_out3__1_n_84\,
P(20) => \y_addr_out3__1_n_85\,
P(19) => \y_addr_out3__1_n_86\,
P(18) => \y_addr_out3__1_n_87\,
P(17) => \y_addr_out3__1_n_88\,
P(16) => \y_addr_out3__1_n_89\,
P(15) => \y_addr_out3__1_n_90\,
P(14) => \y_addr_out3__1_n_91\,
P(13) => \y_addr_out3__1_n_92\,
P(12) => \y_addr_out3__1_n_93\,
P(11) => \y_addr_out3__1_n_94\,
P(10) => \y_addr_out3__1_n_95\,
P(9) => \y_addr_out3__1_n_96\,
P(8) => \y_addr_out3__1_n_97\,
P(7) => \y_addr_out3__1_n_98\,
P(6) => \y_addr_out3__1_n_99\,
P(5) => \y_addr_out3__1_n_100\,
P(4) => \y_addr_out3__1_n_101\,
P(3) => \y_addr_out3__1_n_102\,
P(2) => \y_addr_out3__1_n_103\,
P(1) => \y_addr_out3__1_n_104\,
P(0) => \y_addr_out3__1_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => \y_addr_out3__1_n_106\,
PCOUT(46) => \y_addr_out3__1_n_107\,
PCOUT(45) => \y_addr_out3__1_n_108\,
PCOUT(44) => \y_addr_out3__1_n_109\,
PCOUT(43) => \y_addr_out3__1_n_110\,
PCOUT(42) => \y_addr_out3__1_n_111\,
PCOUT(41) => \y_addr_out3__1_n_112\,
PCOUT(40) => \y_addr_out3__1_n_113\,
PCOUT(39) => \y_addr_out3__1_n_114\,
PCOUT(38) => \y_addr_out3__1_n_115\,
PCOUT(37) => \y_addr_out3__1_n_116\,
PCOUT(36) => \y_addr_out3__1_n_117\,
PCOUT(35) => \y_addr_out3__1_n_118\,
PCOUT(34) => \y_addr_out3__1_n_119\,
PCOUT(33) => \y_addr_out3__1_n_120\,
PCOUT(32) => \y_addr_out3__1_n_121\,
PCOUT(31) => \y_addr_out3__1_n_122\,
PCOUT(30) => \y_addr_out3__1_n_123\,
PCOUT(29) => \y_addr_out3__1_n_124\,
PCOUT(28) => \y_addr_out3__1_n_125\,
PCOUT(27) => \y_addr_out3__1_n_126\,
PCOUT(26) => \y_addr_out3__1_n_127\,
PCOUT(25) => \y_addr_out3__1_n_128\,
PCOUT(24) => \y_addr_out3__1_n_129\,
PCOUT(23) => \y_addr_out3__1_n_130\,
PCOUT(22) => \y_addr_out3__1_n_131\,
PCOUT(21) => \y_addr_out3__1_n_132\,
PCOUT(20) => \y_addr_out3__1_n_133\,
PCOUT(19) => \y_addr_out3__1_n_134\,
PCOUT(18) => \y_addr_out3__1_n_135\,
PCOUT(17) => \y_addr_out3__1_n_136\,
PCOUT(16) => \y_addr_out3__1_n_137\,
PCOUT(15) => \y_addr_out3__1_n_138\,
PCOUT(14) => \y_addr_out3__1_n_139\,
PCOUT(13) => \y_addr_out3__1_n_140\,
PCOUT(12) => \y_addr_out3__1_n_141\,
PCOUT(11) => \y_addr_out3__1_n_142\,
PCOUT(10) => \y_addr_out3__1_n_143\,
PCOUT(9) => \y_addr_out3__1_n_144\,
PCOUT(8) => \y_addr_out3__1_n_145\,
PCOUT(7) => \y_addr_out3__1_n_146\,
PCOUT(6) => \y_addr_out3__1_n_147\,
PCOUT(5) => \y_addr_out3__1_n_148\,
PCOUT(4) => \y_addr_out3__1_n_149\,
PCOUT(3) => \y_addr_out3__1_n_150\,
PCOUT(2) => \y_addr_out3__1_n_151\,
PCOUT(1) => \y_addr_out3__1_n_152\,
PCOUT(0) => \y_addr_out3__1_n_153\,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED\
);
\y_addr_out3__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m10(15),
A(28) => rot_m10(15),
A(27) => rot_m10(15),
A(26) => rot_m10(15),
A(25) => rot_m10(15),
A(24) => rot_m10(15),
A(23) => rot_m10(15),
A(22) => rot_m10(15),
A(21) => rot_m10(15),
A(20) => rot_m10(15),
A(19) => rot_m10(15),
A(18) => rot_m10(15),
A(17) => rot_m10(15),
A(16) => rot_m10(15),
A(15 downto 0) => rot_m10(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => x_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__2_n_58\,
P(46) => \y_addr_out3__2_n_59\,
P(45) => \y_addr_out3__2_n_60\,
P(44) => \y_addr_out3__2_n_61\,
P(43) => \y_addr_out3__2_n_62\,
P(42) => \y_addr_out3__2_n_63\,
P(41) => \y_addr_out3__2_n_64\,
P(40) => \y_addr_out3__2_n_65\,
P(39) => \y_addr_out3__2_n_66\,
P(38) => \y_addr_out3__2_n_67\,
P(37) => \y_addr_out3__2_n_68\,
P(36) => \y_addr_out3__2_n_69\,
P(35) => \y_addr_out3__2_n_70\,
P(34) => \y_addr_out3__2_n_71\,
P(33) => \y_addr_out3__2_n_72\,
P(32) => \y_addr_out3__2_n_73\,
P(31) => \y_addr_out3__2_n_74\,
P(30) => \y_addr_out3__2_n_75\,
P(29) => \y_addr_out3__2_n_76\,
P(28) => \y_addr_out3__2_n_77\,
P(27) => \y_addr_out3__2_n_78\,
P(26) => \y_addr_out3__2_n_79\,
P(25) => \y_addr_out3__2_n_80\,
P(24) => \y_addr_out3__2_n_81\,
P(23) => \y_addr_out3__2_n_82\,
P(22) => \y_addr_out3__2_n_83\,
P(21) => \y_addr_out3__2_n_84\,
P(20) => \y_addr_out3__2_n_85\,
P(19) => \y_addr_out3__2_n_86\,
P(18) => \y_addr_out3__2_n_87\,
P(17) => \y_addr_out3__2_n_88\,
P(16) => \y_addr_out3__2_n_89\,
P(15) => \y_addr_out3__2_n_90\,
P(14) => \y_addr_out3__2_n_91\,
P(13) => \y_addr_out3__2_n_92\,
P(12) => \y_addr_out3__2_n_93\,
P(11) => \y_addr_out3__2_n_94\,
P(10) => \y_addr_out3__2_n_95\,
P(9) => \y_addr_out3__2_n_96\,
P(8) => \y_addr_out3__2_n_97\,
P(7) => \y_addr_out3__2_n_98\,
P(6) => \y_addr_out3__2_n_99\,
P(5) => \y_addr_out3__2_n_100\,
P(4) => \y_addr_out3__2_n_101\,
P(3) => \y_addr_out3__2_n_102\,
P(2) => \y_addr_out3__2_n_103\,
P(1) => \y_addr_out3__2_n_104\,
P(0) => \y_addr_out3__2_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => \y_addr_out3__1_n_106\,
PCIN(46) => \y_addr_out3__1_n_107\,
PCIN(45) => \y_addr_out3__1_n_108\,
PCIN(44) => \y_addr_out3__1_n_109\,
PCIN(43) => \y_addr_out3__1_n_110\,
PCIN(42) => \y_addr_out3__1_n_111\,
PCIN(41) => \y_addr_out3__1_n_112\,
PCIN(40) => \y_addr_out3__1_n_113\,
PCIN(39) => \y_addr_out3__1_n_114\,
PCIN(38) => \y_addr_out3__1_n_115\,
PCIN(37) => \y_addr_out3__1_n_116\,
PCIN(36) => \y_addr_out3__1_n_117\,
PCIN(35) => \y_addr_out3__1_n_118\,
PCIN(34) => \y_addr_out3__1_n_119\,
PCIN(33) => \y_addr_out3__1_n_120\,
PCIN(32) => \y_addr_out3__1_n_121\,
PCIN(31) => \y_addr_out3__1_n_122\,
PCIN(30) => \y_addr_out3__1_n_123\,
PCIN(29) => \y_addr_out3__1_n_124\,
PCIN(28) => \y_addr_out3__1_n_125\,
PCIN(27) => \y_addr_out3__1_n_126\,
PCIN(26) => \y_addr_out3__1_n_127\,
PCIN(25) => \y_addr_out3__1_n_128\,
PCIN(24) => \y_addr_out3__1_n_129\,
PCIN(23) => \y_addr_out3__1_n_130\,
PCIN(22) => \y_addr_out3__1_n_131\,
PCIN(21) => \y_addr_out3__1_n_132\,
PCIN(20) => \y_addr_out3__1_n_133\,
PCIN(19) => \y_addr_out3__1_n_134\,
PCIN(18) => \y_addr_out3__1_n_135\,
PCIN(17) => \y_addr_out3__1_n_136\,
PCIN(16) => \y_addr_out3__1_n_137\,
PCIN(15) => \y_addr_out3__1_n_138\,
PCIN(14) => \y_addr_out3__1_n_139\,
PCIN(13) => \y_addr_out3__1_n_140\,
PCIN(12) => \y_addr_out3__1_n_141\,
PCIN(11) => \y_addr_out3__1_n_142\,
PCIN(10) => \y_addr_out3__1_n_143\,
PCIN(9) => \y_addr_out3__1_n_144\,
PCIN(8) => \y_addr_out3__1_n_145\,
PCIN(7) => \y_addr_out3__1_n_146\,
PCIN(6) => \y_addr_out3__1_n_147\,
PCIN(5) => \y_addr_out3__1_n_148\,
PCIN(4) => \y_addr_out3__1_n_149\,
PCIN(3) => \y_addr_out3__1_n_150\,
PCIN(2) => \y_addr_out3__1_n_151\,
PCIN(1) => \y_addr_out3__1_n_152\,
PCIN(0) => \y_addr_out3__1_n_153\,
PCOUT(47 downto 0) => \NLW_y_addr_out3__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED\
);
\y_addr_out[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(28),
I1 => t_y(0),
O => p_0_in(0)
);
\y_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(0),
Q => y_addr_out(0),
R => '0'
);
\y_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(1),
Q => y_addr_out(1),
R => '0'
);
\y_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(2),
Q => y_addr_out(2),
R => '0'
);
\y_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(3),
Q => y_addr_out(3),
R => '0'
);
\y_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(4),
Q => y_addr_out(4),
R => '0'
);
\y_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(5),
Q => y_addr_out(5),
R => '0'
);
\y_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(6),
Q => y_addr_out(6),
R => '0'
);
\y_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(7),
Q => y_addr_out(7),
R => '0'
);
\y_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(8),
Q => y_addr_out(8),
R => '0'
);
\y_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(9),
Q => y_addr_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_transform_0_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_transform_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_transform_0_0 : entity is "system_vga_transform_0_0,vga_transform,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_transform_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_transform_0_0 : entity is "vga_transform,Vivado 2016.4";
end system_vga_transform_0_0;
architecture STRUCTURE of system_vga_transform_0_0 is
begin
U0: entity work.system_vga_transform_0_0_vga_transform
port map (
clk => clk,
enable => enable,
rot_m00(15 downto 0) => rot_m00(15 downto 0),
rot_m01(15 downto 0) => rot_m01(15 downto 0),
rot_m10(15 downto 0) => rot_m10(15 downto 0),
rot_m11(15 downto 0) => rot_m11(15 downto 0),
t_x(9 downto 0) => t_x(9 downto 0),
t_y(9 downto 0) => t_y(9 downto 0),
x_addr_in(9 downto 0) => x_addr_in(9 downto 0),
x_addr_out(9 downto 0) => x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => y_addr_in(9 downto 0),
y_addr_out(9 downto 0) => y_addr_out(9 downto 0)
);
end STRUCTURE;
| mit | ae14c8c740d8071080ba17905ca244c7 | 0.537591 | 2.341119 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_1_0/sim/system_vga_nmsuppression_1_0.vhd | 1 | 4,143 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_nmsuppression:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_nmsuppression_1_0 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_nmsuppression_1_0;
ARCHITECTURE system_vga_nmsuppression_1_0_arch OF system_vga_nmsuppression_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_nmsuppression_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_nmsuppression IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_nmsuppression;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_nmsuppression
GENERIC MAP (
ROW_WIDTH => 5
)
PORT MAP (
clk => clk,
enable => enable,
active => active,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
hessian_in => hessian_in,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out,
hessian_out => hessian_out
);
END system_vga_nmsuppression_1_0_arch;
| mit | d3d3edca9024f1553339ad170550f7fa | 0.709631 | 3.702413 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_feature_transform_0_0/synth/system_vga_feature_transform_0_0.vhd | 1 | 5,944 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_feature_transform:1.0
-- IP Revision: 74
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_feature_transform_0_0 IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : IN STD_LOGIC;
vsync : IN STD_LOGIC;
x_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rot_m00 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END system_vga_feature_transform_0_0;
ARCHITECTURE system_vga_feature_transform_0_0_arch OF system_vga_feature_transform_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_feature_transform IS
GENERIC (
NUM_FEATURES : INTEGER
);
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : IN STD_LOGIC;
vsync : IN STD_LOGIC;
x_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rot_m00 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT vga_feature_transform;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "vga_feature_transform,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_feature_transform_0_0_arch : ARCHITECTURE IS "system_vga_feature_transform_0_0,vga_feature_transform,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "system_vga_feature_transform_0_0,vga_feature_transform,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_feature_transform,x_ipVersion=1.0,x_ipCoreRevision=74,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,NUM_FEATURES=40}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_feature_transform
GENERIC MAP (
NUM_FEATURES => 40
)
PORT MAP (
clk => clk,
clk_x2 => clk_x2,
rst => rst,
active => active,
vsync => vsync,
x_addr_0 => x_addr_0,
y_addr_0 => y_addr_0,
hessian_0 => hessian_0,
x_addr_1 => x_addr_1,
y_addr_1 => y_addr_1,
hessian_1 => hessian_1,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
state => state
);
END system_vga_feature_transform_0_0_arch;
| mit | 8421852a639b5ad5be7bd1c87990a4f8 | 0.695491 | 3.453806 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/madd_seq-rtl.vhdl | 1 | 1,673 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of madd_seq is
begin
madd : entity work.madd_seq_inferred(rtl)
generic map (
latency => latency,
src1_bits => src1_bits,
src2_bits => src2_bits
)
port map (
clk => clk,
rstn => rstn,
en => en,
unsgnd => unsgnd,
sub => sub,
acc => acc,
src1 => src1,
src2 => src2,
valid => valid,
result => result,
overflow => overflow
);
end;
| apache-2.0 | 34f6cbf1f0195a13fda69dba8c847731 | 0.472803 | 5.085106 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/hdl/system.vhd | 1 | 17,214 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Jun 05 08:32:55 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
enable_nm : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=22,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_0_0;
component system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_reset_0_0;
component system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_0_0;
component system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end component system_debounce_0_0;
component system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_0_0;
component system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_0_0;
component system_rgb888_mux_2_0_0 is
port (
clk : in STD_LOGIC;
sel : in STD_LOGIC;
rgb888_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb888_mux_2_0_0;
component system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_xlconstant_0_0;
component system_comparator_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC
);
end component system_comparator_0_0;
component system_xlconstant_0_1 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_xlconstant_0_1;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_clk_wiz_1_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_1_0;
component system_xlconstant_0_2 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xlconstant_0_2;
component system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_vga_hessian_0_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_0_0;
component system_vga_nmsuppression_0_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_nmsuppression_0_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal buffer_register_0_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal clk_100_1 : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_1_clk_out1 : STD_LOGIC;
signal clock_splitter_0_clk_out : STD_LOGIC;
signal comparator_0_z : STD_LOGIC;
signal data_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal debounce_0_o : STD_LOGIC;
signal enable_1 : STD_LOGIC;
signal hsync_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pclk_1 : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_mux_2_0_rgb888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_to_g8_0_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal threshold_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vdd_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_buffer_0_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_hessian_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_nmsuppression_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_pll_0_clk_12_6 : STD_LOGIC;
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_sync_ref_0_active : STD_LOGIC;
signal vga_sync_ref_0_start : STD_LOGIC;
signal vga_sync_ref_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_active : STD_LOGIC;
signal vga_sync_reset_0_hsync : STD_LOGIC;
signal vga_sync_reset_0_vsync : STD_LOGIC;
signal vga_sync_reset_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vsync_1 : STD_LOGIC;
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 23 downto 0 );
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_clk_wiz_1_locked_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_vga_nmsuppression_0_x_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_vga_nmsuppression_0_y_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_vga_pll_0_clk_50_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
begin
clk_100_1 <= clk_100;
data_1(7 downto 0) <= data(7 downto 0);
enable_1 <= enable_nm;
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
hsync_1 <= hsync;
pclk_1 <= pclk;
ready <= ov7670_controller_0_config_finished;
reset_1 <= reset;
sioc <= ov7670_controller_0_sioc;
vsync_1 <= vsync;
xclk <= clk_wiz_0_clk_out1;
buffer_register_0: component system_buffer_register_0_0
port map (
clk => vga_pll_0_clk_12_6,
val_in(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_0_val_out(31 downto 0)
);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED
);
clk_wiz_1: component system_clk_wiz_1_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_1_clk_out1,
locked => NLW_clk_wiz_1_locked_UNCONNECTED
);
clock_splitter_0: component system_clock_splitter_0_0
port map (
clk_in => pclk_1,
clk_out => clock_splitter_0_clk_out,
latch_edge => vsync_1
);
comparator_0: component system_comparator_0_0
port map (
x(31 downto 0) => vga_nmsuppression_0_hessian_out(31 downto 0),
y(31 downto 0) => threshold_dout(31 downto 0),
z => comparator_0_z
);
debounce_0: component system_debounce_0_0
port map (
clk => vga_pll_0_clk_25,
signal_in => reset_1,
signal_out => debounce_0_o
);
inverter_0: component system_inverter_0_0
port map (
x => vga_sync_ref_0_start,
x_not => inverter_0_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => vga_pll_0_clk_25,
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => debounce_0_o,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => siod,
xclk => NLW_ov7670_controller_0_xclk_UNCONNECTED
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
active => vga_sync_ref_0_active,
clk_x2 => pclk_1,
data(7 downto 0) => data_1(7 downto 0),
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
clk => clock_splitter_0_clk_out,
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb888_mux_2_0: component system_rgb888_mux_2_0_0
port map (
clk => vga_pll_0_clk_12_6,
rgb888(23 downto 0) => rgb888_mux_2_0_rgb888(23 downto 0),
rgb888_0(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
rgb888_1(23 downto 0) => xlconstant_0_dout(23 downto 0),
sel => comparator_0_z
);
rgb888_to_g8_0: component system_rgb888_to_g8_0_0
port map (
clk => vga_pll_0_clk_12_6,
g8(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_0_data_r(23 downto 0)
);
threshold: component system_xlconstant_0_1
port map (
dout(31 downto 0) => threshold_dout(31 downto 0)
);
vdd: component system_xlconstant_0_2
port map (
dout(0) => vdd_dout(0)
);
vga_buffer_0: component system_vga_buffer_0_0
port map (
clk_r => vga_pll_0_clk_12_6,
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_hessian_0: component system_vga_hessian_0_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
rst => vdd_dout(0),
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_nmsuppression_0: component system_vga_nmsuppression_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
enable => enable_1,
hessian_in(31 downto 0) => buffer_register_0_val_out(31 downto 0),
hessian_out(31 downto 0) => vga_nmsuppression_0_hessian_out(31 downto 0),
x_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_out(9 downto 0) => NLW_vga_nmsuppression_0_x_addr_out_UNCONNECTED(9 downto 0),
y_addr_in(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_out(9 downto 0) => NLW_vga_nmsuppression_0_y_addr_out_UNCONNECTED(9 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => vga_pll_0_clk_12_6,
clk_25 => vga_pll_0_clk_25,
clk_50 => NLW_vga_pll_0_clk_50_UNCONNECTED,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_ref_0: component system_vga_sync_ref_0_0
port map (
active => vga_sync_ref_0_active,
clk => clock_splitter_0_clk_out,
hsync => hsync_1,
rst => ov7670_controller_0_config_finished,
start => vga_sync_ref_0_start,
vsync => vsync_1,
xaddr(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_sync_reset_0: component system_vga_sync_reset_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
hsync => vga_sync_reset_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_reset_0_vsync,
xaddr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
white: component system_xlconstant_0_0
port map (
dout(23 downto 0) => xlconstant_0_dout(23 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
clk_100 => clk_100_1,
clk_x2 => vga_pll_0_clk_25,
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_reset_0_hsync,
rgb888(23 downto 0) => rgb888_mux_2_0_rgb888(23 downto 0),
vsync => vga_sync_reset_0_vsync
);
end STRUCTURE;
| mit | e95eb25f8a77e9a1c70ec63aa036856c | 0.631288 | 2.946089 | false | false | false | false |
freecores/tcp_socket | source/gigabit_ethernet.vhd | 1 | 22,521 | --------------------------------------------------------------------------------
---
--- Gigabit Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A gigabit ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 1Gbit/s ethernet only via a gmii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component used two clocks, the local clock used to transfer data
---between components, and a 125MHz clock source for sending data to the
---Ethernet physical interface. This clock is also forwarded along with the
---data to the ethernet phy.
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity gigabit_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
CLK_125_MHZ : in std_logic;
--GMII IF
GTXCLK : out std_logic;
TXCLK : in std_logic;
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(7 downto 0);
PHY_RESET : out std_logic;
RXCLK : in std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(7 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity gigabit_ethernet;
architecture RTL of gigabit_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 511) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE_0, PREAMBLE_1,
PREAMBLE_2, PREAMBLE_3, PREAMBLE_4, PREAMBLE_5, PREAMBLE_6, SFD,
SEND_DATA_HI, SEND_DATA_LO, SEND_CRC_3, SEND_CRC_2, SEND_CRC_1,
SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE, DATA_HIGH, DATA_LOW,
END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET,
SEND_DATA, PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1513;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1513;
signal TX_READ_ADDRESS : integer range 0 to 1513;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1513;
signal TX_OUT_COUNT : integer range 0 to 1513;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(7 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK_125_MHZ);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the local clock domain
LOCAL_TO_CLK_125 : process
begin
wait until rising_edge(CLK_125_MHZ);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
CLK_125_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
begin
wait until rising_edge(CLK_125_MHZ);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE_0;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
end if;
when PREAMBLE_0 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_1;
TXEN <= '1';
when PREAMBLE_1 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_2;
when PREAMBLE_2 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_3;
when PREAMBLE_3 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_4;
when PREAMBLE_4 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_5;
when PREAMBLE_5 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_6;
when PREAMBLE_6 =>
TXD <= X"55";
TX_PHY_STATE <= SFD;
when SFD =>
TXD <= X"D5";
TX_PHY_STATE <= SEND_DATA_HI;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_HI =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 8);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_3;
else
TX_PHY_STATE <= SEND_DATA_LO;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_LO =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 0);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_3;
else
TX_PHY_STATE <= SEND_DATA_HI;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_3 =>
TXD <= not REVERSED(TX_CRC(31 downto 24));
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
TXD <= not REVERSED(TX_CRC(23 downto 16));
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
TXD <= not REVERSED(TX_CRC(15 downto 8));
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
TXD <= not REVERSED(TX_CRC(7 downto 0));
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
GTXCLK <= CLK_125_MHZ;
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(RXCLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = X"55" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = X"d5" then
RX_PHY_STATE <= DATA_HIGH;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= X"55" or RXDV_D = '0' then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_HIGH =>
RX_WRITE_DATA(15 downto 8) <= RXD_D;
if RXDV_D = '1' then
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_LOW;
RX_CRC <= nextCRC32_D8(RXD_D, RX_CRC);
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_LOW =>
RX_WRITE_DATA(7 downto 0) <= RXD_D;
RX_WRITE_ENABLE <= '1';
if RXDV_D = '1' then
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_HIGH;
RX_CRC <= nextCRC32_D8(RXD_D, RX_CRC);
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(RXCLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(RXCLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
| mit | 84716ef77a9394124150f3858b55afb8 | 0.545757 | 3.294952 | false | false | false | false |
loa-org/loa-hdl | modules/imotor/tb/imotor_receiver_tb.vhd | 2 | 3,248 | -------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_receiver"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_receiver_tb is
end entity imotor_receiver_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_receiver_tb is
-- component generics
constant DATA_WORDS : positive := 2;
constant DATA_WIDTH : positive := 16;
-- Component ports
-- clock
signal clk : std_logic := '1';
signal clock_s : imotor_timer_type;
signal data_rx_in_s : std_logic_vector(7 downto 0) := (others => '0');
signal imotor_output_s : imotor_output_type(1 downto 0);
signal ready_rx_s : std_logic := '0';
begin -- architecture behavourial
-- component instantiation
imotor_receiver_1 : entity work.imotor_receiver
generic map (
DATA_WORDS => DATA_WORDS,
DATA_WIDTH => DATA_WIDTH)
port map (
data_out_p => imotor_output_s,
data_in_p => data_rx_in_s,
parity_error_in_p => '0', -- parity_error_in_p,
ready_in_p => ready_rx_s,
clk => clk);
imotor_timer_1 : imotor_timer
generic map (
CLOCK => 50E6,
BAUD => 1E6,
SEND_FREQUENCY => 1E5)
port map (
clock_out_p => clock_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
variable test_vector : unsigned(7 downto 0) := x"01";
begin
while true loop
-- Start byte of slave
wait until clock_s.rx = '1';
data_rx_in_s <= x"51";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
-- Four data bytes
for ii in 0 to 3 loop
wait until clock_s.rx = '1';
data_rx_in_s <= std_logic_vector(test_vector);
test_vector := test_vector + x"22";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
end loop; -- ii
-- End Byte
wait until clock_s.rx = '1';
data_rx_in_s <= x"A1";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
-- Next Message, after a small pause
wait until clock_s.rx = '1';
wait until clock_s.rx = '0';
wait until clock_s.rx = '1';
wait until clock_s.rx = '0';
end loop;
wait until false;
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause | 54572ff622d1a575e3448f2293fcf06b | 0.442118 | 4.234681 | false | false | false | false |
ashikpoojari/Hardware-Security | PUF Lab/Students_PUFS/puf_lab_mos283_ad3572/benes8.vhd | 2 | 3,296 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:34:19 04/24/2017
-- Design Name:
-- Module Name: benes8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity benes8 is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (19 downto 0);
b : out STD_LOGIC_VECTOR (7 downto 0));
end benes8;
architecture Behavioral of benes8 is
signal a2, a1, ab, b1, b2 : STD_LOGIC_VECTOR (7 downto 0);
component sw2x2
port (
in0: in std_logic;
in1: in std_logic;
out0: out std_logic;
out1: out std_logic;
sel: in std_logic);
end component;
begin
st2a1 : sw2x2 port map(in0 => a(7), in1 => a(3), out0 => a2(7), out1 => a2(3), sel => sel(19) );
st2a2 : sw2x2 port map(in0 => a(6), in1 => a(2), out0 => a2(6), out1 => a2(2), sel => sel(18) );
st2a3 : sw2x2 port map(in0 => a(5), in1 => a(1), out0 => a2(5), out1 => a2(1), sel => sel(17) );
st2a4 : sw2x2 port map(in0 => a(4), in1 => a(0), out0 => a2(4), out1 => a2(0), sel => sel(16) );
st1a1 : sw2x2 port map(in0 => a2(7), in1 => a2(5), out0 => a1(7), out1 => a1(5), sel => sel(15) );
st1a2 : sw2x2 port map(in0 => a2(6), in1 => a2(4), out0 => a1(6), out1 => a1(4), sel => sel(14) );
st1a3 : sw2x2 port map(in0 => a2(3), in1 => a2(1), out0 => a1(3), out1 => a1(1), sel => sel(13) );
st1a4 : sw2x2 port map(in0 => a2(2), in1 => a2(0), out0 => a1(2), out1 => a1(0), sel => sel(12) );
st01 : sw2x2 port map(in0 => a1(7), in1 => a1(6), out0 => ab(7), out1 => ab(6), sel => sel(11) );
st02 : sw2x2 port map(in0 => a1(5), in1 => a1(4), out0 => ab(5), out1 => ab(4), sel => sel(10) );
st03 : sw2x2 port map(in0 => a1(3), in1 => a1(2), out0 => ab(3), out1 => ab(2), sel => sel(9) );
st04 : sw2x2 port map(in0 => a1(1), in1 => a1(0), out0 => ab(1), out1 => ab(0), sel => sel(8) );
st2b1 : sw2x2 port map(in0 => ab(7), in1 => ab(5), out0 => b1(7), out1 => b1(5), sel => sel(7) );
st2b2 : sw2x2 port map(in0 => ab(6), in1 => ab(4), out0 => b1(6), out1 => b1(4), sel => sel(6) );
st2b3 : sw2x2 port map(in0 => ab(3), in1 => ab(1), out0 => b1(3), out1 => b1(1), sel => sel(5) );
st2b4 : sw2x2 port map(in0 => ab(2), in1 => ab(0), out0 => b1(2), out1 => b1(0), sel => sel(4) );
st1b1 : sw2x2 port map(in0 => b1(7), in1 => b1(3), out0 => b(7), out1 => b(3), sel => sel(3) );
st1b2 : sw2x2 port map(in0 => b1(6), in1 => b1(2), out0 => b(6), out1 => b(2), sel => sel(2) );
st1b3 : sw2x2 port map(in0 => b1(5), in1 => b1(1), out0 => b(5), out1 => b(1), sel => sel(1) );
st1b4 : sw2x2 port map(in0 => b1(4), in1 => b1(0), out0 => b(4), out1 => b(0), sel => sel(0) );
end Behavioral;
| mit | 976436b0e14e0f5ac664eb18612ac4d7 | 0.524272 | 2.386676 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_feature_transform_0_0/sim/system_vga_feature_transform_0_0.vhd | 1 | 5,215 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_feature_transform:1.0
-- IP Revision: 74
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_feature_transform_0_0 IS
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : IN STD_LOGIC;
vsync : IN STD_LOGIC;
x_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rot_m00 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END system_vga_feature_transform_0_0;
ARCHITECTURE system_vga_feature_transform_0_0_arch OF system_vga_feature_transform_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_feature_transform_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_feature_transform IS
GENERIC (
NUM_FEATURES : INTEGER
);
PORT (
clk : IN STD_LOGIC;
clk_x2 : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : IN STD_LOGIC;
vsync : IN STD_LOGIC;
x_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_0 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_1 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rot_m00 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m01 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rot_m11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
t_x : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
t_y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT vga_feature_transform;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_feature_transform
GENERIC MAP (
NUM_FEATURES => 64
)
PORT MAP (
clk => clk,
clk_x2 => clk_x2,
rst => rst,
active => active,
vsync => vsync,
x_addr_0 => x_addr_0,
y_addr_0 => y_addr_0,
hessian_0 => hessian_0,
x_addr_1 => x_addr_1,
y_addr_1 => y_addr_1,
hessian_1 => hessian_1,
rot_m00 => rot_m00,
rot_m01 => rot_m01,
rot_m10 => rot_m10,
rot_m11 => rot_m11,
t_x => t_x,
t_y => t_y,
state => state
);
END system_vga_feature_transform_0_0_arch;
| mit | 54ba29c9ffd6beced9eedf03dcdd6bc4 | 0.682263 | 3.488294 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/synth/affine_block_uint_to_ieee754_fp_0_1.vhd | 2 | 3,943 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:uint_to_ieee754_fp:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_uint_to_ieee754_fp_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_uint_to_ieee754_fp_0_1;
ARCHITECTURE affine_block_uint_to_ieee754_fp_0_1_arch OF affine_block_uint_to_ieee754_fp_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT uint_to_ieee754_fp IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT uint_to_ieee754_fp;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "uint_to_ieee754_fp,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_uint_to_ieee754_fp_0_1_arch : ARCHITECTURE IS "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=uint_to_ieee754_fp,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=10}";
BEGIN
U0 : uint_to_ieee754_fp
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_uint_to_ieee754_fp_0_1_arch;
| mit | 358c5d12b7f3f4380841346470a9bbb7 | 0.739031 | 3.644177 | false | false | false | false |
Kolchuzhin/piezoresistance_of_SWCNT_in_VHDL-AMS_part_I | testbench_pr_swcnt.vhd | 1 | 3,101 | -------------------------------------------------------------------------------
-- Model: testbench for piezoresistance of SWCNT in hAMSter
--
-- Author: Vladimir Kolchuzhin, LMGT, TU Chemnitz
-- <[email protected]>
-- Date: 06.01.2012
--
-- Library:
-- pr_swcnt.vhd
-- v_dc.vhd
-- f_pulse.vhd
--
--
-- Euler solver, Tend=2.0m, dt=1u
-- Output: u_ext1; cnt: i.cnt1, strain.cnt1, rcnt.cnt1;
-- The CNT is driven by a force source Fs1
-------------------------------------------------------------------------------
-- ID: testbench_pr_swcnt.vhd
--
-- Modification History:
-- Revision 1.0 12.04.2012 official release for ForGr1713, www.zfm.tu-chemnitz.de/for1713
-- Revision 07.10.2014 github
-------------------------------------------------------------------------------
library ieee;
use work.electromagnetic_system.all;
use work.all;
use ieee.math_real.all;
entity testbench_pr_swcnt is
end;
architecture behav of testbench_pr_swcnt is
terminal struc1_ext,struc2_ext: translational; -- structural nodes
terminal elec1_ext,elec2_ext: electrical; -- electrical ports
--
quantity u_ext1 across f_ext1 through struc1_ext; -- node 1
quantity u_ext2 across f_ext2 through struc2_ext; -- node 2
--
quantity v_ext1 across i_ext1 through elec1_ext; -- electrode 1
quantity v_ext2 across i_ext2 through elec2_ext; -- electrode 2
-- CNT parameters
constant Rc:real:=100.0e3;
constant T:real:=300.0;
constant n:real:=13.0;
constant m:real:= 1.0;
constant stiff:real:= 0.54;
constant L0:real:= 2.0e-6;
constant s0:real:=0.0;
constant smax:real:=0.05;
constant g:real:=0.0;
-- Voltage source: dc
constant dc_value:real:=1.0;
-- Force source: triangular pulse
constant ac_value:real:=smax*L0*stiff; -- N
constant period:real:=2.0e-3; -- s
begin
-------------------------------------------------------------------------------
-- BC for ports:
i_ext1==0.0; -- input
v_ext2==0.0; -- ground
f_ext1==0.0; -- external nodal force
u_ext2==0.0; -- external nodal displacement (ground)
-------------------------------------------------------------------------------
--
-- nodal ports electrical ports
--
-- f_ext1=0 ->>- o---- ----o -<<- i_ext1=0
-- | | | |
-- | < - |
-- ^ < | | |
-- Fs1 ^ < | | ^ Vs1
-- | < - |
-- | | | |
-- u_ext2=0 o---- ----o v_ext2=0
--
-- electrical_ground
--
-- ASCII-Schematic of the circuit
-------------------------------------------------------------------------------
CNT1:
entity pr_swcnt(analytic)
generic map(Rc,T,n,m,s0,g,stiff,L0)
port map(struc1_ext,struc2_ext,elec1_ext,elec2_ext);
Vs1:
entity v_dc(basic)
generic map(dc_value)
port map(elec1_ext,elec2_ext);
Fs1:
entity f_pulse(basic)
generic map(0.0,ac_value,period)
port map(struc1_ext,struc2_ext);
end;
| mit | b4b886b2e32c6bf5e33350c231f3c21d | 0.490487 | 3.313034 | false | false | false | false |
olofk/libstorage | rtl/vhdl/generic/fifo_fwft_adapter.vhd | 1 | 2,813 | --
-- FIFO First word fall through adapter. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.std_logic_1164.all;
entity fifo_fwft_adapter is
generic (
type data_type);
port (
clk : in std_ulogic;
rst : in std_ulogic;
fifo_rd_en_o : out std_ulogic;
fifo_rd_data_i : in data_type;
fifo_empty_i : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out data_type;
empty_o : out std_ulogic);
end entity;
architecture rtl of fifo_fwft_adapter is
signal fifo_valid : std_ulogic;
signal middle_valid : std_ulogic;
signal dout_valid : std_ulogic;
signal will_update_middle : std_ulogic;
signal will_update_dout : std_ulogic;
signal middle_dout : data_type;
begin
will_update_middle <= fifo_valid and (middle_valid ?= will_update_dout);
will_update_dout <= (middle_valid or fifo_valid) and
(rd_en_i or not dout_valid);
fifo_rd_en_o <= (not fifo_empty_i) and
not (middle_valid and dout_valid and fifo_valid);
empty_o <= not dout_valid;
p_main : process(clk)
begin
if rising_edge(clk) then
if will_update_middle then
middle_dout <= fifo_rd_data_i;
end if;
if will_update_dout then
if middle_valid = '1' then
rd_data_o <= middle_dout;
else
rd_data_o <= fifo_rd_data_i;
end if;
end if;
if fifo_rd_en_o then
fifo_valid <= '1';
elsif will_update_middle or will_update_dout then
fifo_valid <= '0';
end if;
if will_update_middle then
middle_valid <= '1';
elsif will_update_dout then
middle_valid <= '0';
end if;
if will_update_dout then
dout_valid <= '1';
elsif rd_en_i then
dout_valid <= '0';
end if;
if rst then
fifo_valid <= '0';
middle_valid <= '0';
dout_valid <= '0';
end if;
end if;
end process;
end architecture rtl;
| isc | c5ad7c6642ea37c169fc95c691653c26 | 0.621401 | 3.61104 | false | false | false | false |
sbourdeauducq/dspunit | rtl/dsp_cmdpipe.vhd | 2 | 3,197 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dsp_cmdpipe is
port (
reset : in std_logic;
clk : in std_logic;
-- data in port
cmd_out : out t_dsp_cmdregs;
read : in std_logic;
empty : out std_logic;
-- data out port
cmd_in : in t_dsp_cmdregs;
write : in std_logic;
full : out std_logic
);
end dsp_cmdpipe;
--=----------------------------------------------------------------------------
architecture archi_dsp_cmdpipe of dsp_cmdpipe is
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type t_dsp_cmdpipe is array(0 to (c_dsp_pipe_length - 1)) of t_dsp_cmdregs;
signal s_loaded : std_logic_vector((c_dsp_pipe_length - 1) downto 0);
signal s_unload : std_logic_vector((c_dsp_pipe_length - 1) downto 0);
signal s_pipe : t_dsp_cmdpipe;
begin -- archs_dsp_cmdpipe
p_pipe : process (clk, reset)
begin -- process p_pipe
if reset = '0' then -- asynchronous reset
s_loaded <= (others => '0');
elsif rising_edge(clk) then -- rising clock edge
-- loading first tap
if write = '1' then
s_loaded(0) <= '1';
s_pipe(0) <= cmd_in;
elsif s_unload(0) = '1' then
s_loaded(0) <= '0';
end if;
-- pipe
for i in 1 to c_dsp_pipe_length - 1 loop
if s_loaded(i) = '0' or s_unload(i) = '1' then
s_pipe(i) <= s_pipe(i - 1);
s_loaded(i) <= s_loaded(i - 1);
s_unload(i - 1) <= '1';
else
s_unload(i - 1) <= '0';
end if;
end loop;
-- unloading last tap
s_unload(c_dsp_pipe_length - 1) <= read;
end if;
end process p_pipe;
full <= s_loaded(0);
empty <= not s_loaded(c_dsp_pipe_length - 1);
cmd_out <= s_pipe(c_dsp_pipe_length - 1);
end archi_dsp_cmdpipe;
-------------------------------------------------------------------------------
| gpl-3.0 | d64bcbd50f41f33c121df4e66e6ed87d | 0.502033 | 3.770047 | false | false | false | false |
pgavin/carpe | hdl/mem/cache/core/cache_core_banked_1rw.vhdl | 1 | 2,346 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Cache Core (SRAMs), banked, 1 read/write port
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity cache_core_banked_1rw is
generic (
log2_assoc : integer := 0;
word_bits : integer := 1;
index_bits : integer := 1;
offset_bits : integer := 0;
tag_bits : integer := 1;
log2_banks : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
en : in std_ulogic;
we : in std_ulogic;
way : in std_ulogic_vector(2**log2_assoc-1 downto 0);
tagen : in std_ulogic;
dataen : in std_ulogic;
banken : in std_ulogic_vector(2**log2_banks-1 downto 0);
index : in std_ulogic_vector(index_bits-1 downto 0);
offset : in std_ulogic_vector(offset_bits-1 downto 0);
wtag : in std_ulogic_vector(tag_bits-1 downto 0);
wdata : in std_ulogic_vector2(2**log2_banks-1 downto 0, word_bits-1 downto 0);
rtag : out std_ulogic_vector2(2**log2_assoc-1 downto 0, tag_bits-1 downto 0);
rdata : out std_ulogic_vector3(2**log2_assoc-1 downto 0, 2**log2_banks-1 downto 0, word_bits-1 downto 0)
);
end;
| apache-2.0 | e56f10beee06a62390e3a56c8e674d8e | 0.543052 | 4.017123 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl | 1 | 18,869 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:35 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_sync_reset_0_0 -prefix
-- system_vga_sync_reset_0_0_ system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 586331814a3b355ede41e486095054b3 | 0.48895 | 2.733053 | false | false | false | false |
loa-org/loa-hdl | modules/servo/hdl/servo_channel.vhd | 2 | 2,905 | -------------------------------------------------------------------------------
-- Title : Servo Channel
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-------------------------------------------------------------------------------
-- Description: Generates a single servo signal in combination with the
-- servo_sequencer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package servo_channel_pkg is
component servo_channel is
port (
servo_p : out std_logic;
compare_value_p : in std_logic_vector(15 downto 0);
load_p : in std_logic;
counter_p : in std_logic_vector(15 downto 0);
enable_p : in std_logic;
clk : in std_logic);
end component servo_channel;
end package servo_channel_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity servo_channel is
port (
servo_p : out std_logic; -- Servo signal
compare_value_p : in std_logic_vector(15 downto 0);
load_p : in std_logic; -- Load a new compare value
-- Counter for the variable part of the signal (stays 0 for the
-- static part => first 0.8ms)
counter_p : in std_logic_vector(15 downto 0);
enable_p : in std_logic;
clk : in std_logic
);
end servo_channel;
-------------------------------------------------------------------------------
architecture behavioral of servo_channel is
type servo_channel_type is record
servo_signal : std_logic;
compare_value : std_logic_vector(15 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : servo_channel_type := (
servo_signal => '0',
compare_value => (others => '0'));
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(compare_value_p, counter_p, enable_p, load_p, r,
r.compare_value, r.servo_signal)
variable v : servo_channel_type;
begin
v := r;
-- default values
v.servo_signal := '0';
if load_p = '1' then
v.compare_value := compare_value_p;
end if;
if counter_p < r.compare_value then
v.servo_signal := enable_p;
end if;
-- register outputs
servo_p <= r.servo_signal;
rin <= v;
end process comb_proc;
end behavioral;
| bsd-3-clause | 44a75ec5cda27a6dcbf8d7df36d82e54 | 0.455766 | 4.489954 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/tb/goertzel_pipelined_v2_tb.vhd | 2 | 3,455 | -------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_pipelined_v2"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipelined_v2_tb is
end entity goertzel_pipelined_v2_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_pipelined_v2_tb is
-- component generics
constant FREQUENCIES : positive := 5;
constant CHANNELS : positive := 12;
constant SAMPLES : positive := 250;
-- component ports
signal start_p : std_logic := '0';
signal bram_addr_p : std_logic_vector(7 downto 0);
signal bram_data_i : std_logic_vector(35 downto 0);
signal bram_data_o : std_logic_vector(35 downto 0);
signal bram_we_p : std_logic;
signal ready_p : std_logic;
signal enable_p : std_logic;
signal coefs_p : goertzel_coefs_type(FREQUENCIES-1 downto 0);
signal inputs_p : goertzel_inputs_type(CHANNELS-1 downto 0);
-- clock
signal Clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.goertzel_pipelined_v2
generic map (
FREQUENCIES => FREQUENCIES,
CHANNELS => CHANNELS,
SAMPLES => SAMPLES)
port map (
start_p => start_p,
bram_addr_p => bram_addr_p,
bram_data_i => bram_data_i,
bram_data_o => bram_data_o,
bram_we_p => bram_we_p,
ready_p => ready_p,
enable_p => enable_p,
coefs_p => coefs_p,
inputs_p => inputs_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- dummy data
bram_data_i <= "110111000000000000" & "010101010101010101";
coefs_p(0) <= "000000000000000001";
coefs_p(1) <= "000000000000000010";
coefs_p(2) <= "000000000000000100";
coefs_p(3) <= "000000000000001000";
coefs_p(4) <= "000000000000010000";
inputs_p(0) <= "00000000011010";
inputs_p(1) <= "00000000101010";
inputs_p(2) <= "00000000111010";
inputs_p(3) <= "00000001001010";
inputs_p(4) <= "00000011011010";
inputs_p(5) <= "00000111011010";
inputs_p(6) <= "00001111011010";
inputs_p(7) <= "00011111011010";
inputs_p(8) <= "00100111011010";
inputs_p(9) <= "00110011011010";
inputs_p(10) <= "01010001011010";
inputs_p(11) <= "01100001011010";
wait until clk = '0';
wait until clk = '1';
wait until clk = '0';
-- start the magic!
start_p <= '1';
wait until clk = '1';
wait until clk = '0';
start_p <= '0';
wait until clk = '1';
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end architecture tb;
| bsd-3-clause | e05215149923a5919862312d1dc97e88 | 0.486831 | 3.944064 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/system_vga_gaussian_blur_0_0_sim_netlist.vhdl | 1 | 942,600 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:55:15 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/system_vga_gaussian_blur_0_0_sim_netlist.vhdl
-- Design : system_vga_gaussian_blur_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_gaussian_blur_0_0_vga_gaussian_blur is
port (
active : out STD_LOGIC;
\C[0]__0\ : out STD_LOGIC;
\C[1]__0\ : out STD_LOGIC;
\C[2]__0\ : out STD_LOGIC;
\C[3]__0\ : out STD_LOGIC;
\C[4]__0\ : out STD_LOGIC;
\C[5]__0\ : out STD_LOGIC;
\C[6]__0\ : out STD_LOGIC;
\C[7]__0\ : out STD_LOGIC;
\C[0]__2\ : out STD_LOGIC;
\C[1]__2\ : out STD_LOGIC;
\C[2]__2\ : out STD_LOGIC;
\C[3]__2\ : out STD_LOGIC;
\C[4]__2\ : out STD_LOGIC;
\C[5]__2\ : out STD_LOGIC;
\C[6]__2\ : out STD_LOGIC;
\C[7]__2\ : out STD_LOGIC;
\C[0]__4\ : out STD_LOGIC;
\C[1]__4\ : out STD_LOGIC;
\C[2]__4\ : out STD_LOGIC;
\C[3]__4\ : out STD_LOGIC;
\C[4]__4\ : out STD_LOGIC;
\C[5]__4\ : out STD_LOGIC;
\C[6]__4\ : out STD_LOGIC;
\C[7]__4\ : out STD_LOGIC;
\A[0]__6\ : out STD_LOGIC;
\A[1]__6\ : out STD_LOGIC;
\A[2]__6\ : out STD_LOGIC;
\A[3]__6\ : out STD_LOGIC;
\A[4]__6\ : out STD_LOGIC;
\A[5]__6\ : out STD_LOGIC;
\A[6]__6\ : out STD_LOGIC;
\A[7]__6\ : out STD_LOGIC;
\A[0]__16\ : out STD_LOGIC;
\A[1]__16\ : out STD_LOGIC;
\A[2]__16\ : out STD_LOGIC;
\A[3]__16\ : out STD_LOGIC;
\A[4]__16\ : out STD_LOGIC;
\A[5]__16\ : out STD_LOGIC;
\A[6]__16\ : out STD_LOGIC;
\A[7]__16\ : out STD_LOGIC;
\A[0]__26\ : out STD_LOGIC;
\A[1]__26\ : out STD_LOGIC;
\A[2]__26\ : out STD_LOGIC;
\A[3]__26\ : out STD_LOGIC;
\A[4]__26\ : out STD_LOGIC;
\A[5]__26\ : out STD_LOGIC;
\A[6]__26\ : out STD_LOGIC;
\A[7]__26\ : out STD_LOGIC;
rgb_blur : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass : out STD_LOGIC_VECTOR ( 23 downto 0 );
D : in STD_LOGIC_VECTOR ( 23 downto 0 );
clk_25 : in STD_LOGIC;
\B[0]\ : in STD_LOGIC;
\B[1]__0\ : in STD_LOGIC;
\B[2]__0\ : in STD_LOGIC;
\B[3]__0\ : in STD_LOGIC;
\B[4]__0\ : in STD_LOGIC;
\B[5]__0\ : in STD_LOGIC;
\B[6]__0\ : in STD_LOGIC;
\B[7]__0\ : in STD_LOGIC;
\B[0]__3\ : in STD_LOGIC;
\B[1]__4\ : in STD_LOGIC;
\B[2]__4\ : in STD_LOGIC;
\B[3]__4\ : in STD_LOGIC;
\B[4]__4\ : in STD_LOGIC;
\B[5]__4\ : in STD_LOGIC;
\B[6]__4\ : in STD_LOGIC;
\B[7]__4\ : in STD_LOGIC;
\B[0]__7\ : in STD_LOGIC;
\B[1]__8\ : in STD_LOGIC;
\B[2]__8\ : in STD_LOGIC;
\B[3]__8\ : in STD_LOGIC;
\B[4]__8\ : in STD_LOGIC;
\B[5]__8\ : in STD_LOGIC;
\B[6]__8\ : in STD_LOGIC;
\B[7]__8\ : in STD_LOGIC;
vsync_in : in STD_LOGIC;
hsync_in : in STD_LOGIC;
rgb_blur9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb_blur11 : in STD_LOGIC_VECTOR ( 7 downto 0 );
I6 : in STD_LOGIC_VECTOR ( 7 downto 0 );
I7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
I12 : in STD_LOGIC_VECTOR ( 7 downto 0 );
I13 : in STD_LOGIC_VECTOR ( 7 downto 0 );
\B[7]__1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\C[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\C[7]__0_0\ : in STD_LOGIC;
\B[7]__5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\B[7]__6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\C[7]__1\ : in STD_LOGIC;
\C[7]__2_0\ : in STD_LOGIC;
\B[7]__9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\B[7]__10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\C[7]__3\ : in STD_LOGIC;
\C[7]__4_0\ : in STD_LOGIC;
\C[0]__0_0\ : in STD_LOGIC;
\C[1]__0_0\ : in STD_LOGIC;
\C[2]__0_0\ : in STD_LOGIC;
\C[3]__0_0\ : in STD_LOGIC;
\C[4]__0_0\ : in STD_LOGIC;
\C[5]__0_0\ : in STD_LOGIC;
\C[6]__0_0\ : in STD_LOGIC;
\C[0]__1\ : in STD_LOGIC;
\C[1]__1\ : in STD_LOGIC;
\C[2]__1\ : in STD_LOGIC;
\C[3]__1\ : in STD_LOGIC;
\C[4]__1\ : in STD_LOGIC;
\C[5]__1\ : in STD_LOGIC;
\C[6]__1\ : in STD_LOGIC;
\C[0]__2_0\ : in STD_LOGIC;
\C[1]__2_0\ : in STD_LOGIC;
\C[2]__2_0\ : in STD_LOGIC;
\C[3]__2_0\ : in STD_LOGIC;
\C[4]__2_0\ : in STD_LOGIC;
\C[5]__2_0\ : in STD_LOGIC;
\C[6]__2_0\ : in STD_LOGIC;
\C[0]__3\ : in STD_LOGIC;
\C[1]__3\ : in STD_LOGIC;
\C[2]__3\ : in STD_LOGIC;
\C[3]__3\ : in STD_LOGIC;
\C[4]__3\ : in STD_LOGIC;
\C[5]__3\ : in STD_LOGIC;
\C[6]__3\ : in STD_LOGIC;
\C[0]__4_0\ : in STD_LOGIC;
\C[1]__4_0\ : in STD_LOGIC;
\C[2]__4_0\ : in STD_LOGIC;
\C[3]__4_0\ : in STD_LOGIC;
\C[4]__4_0\ : in STD_LOGIC;
\C[5]__4_0\ : in STD_LOGIC;
\C[6]__4_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_gaussian_blur_0_0_vga_gaussian_blur : entity is "vga_gaussian_blur";
end system_vga_gaussian_blur_0_0_vga_gaussian_blur;
architecture STRUCTURE of system_vga_gaussian_blur_0_0_vga_gaussian_blur is
signal C : STD_LOGIC_VECTOR ( 11 downto 1 );
signal \C__0\ : STD_LOGIC_VECTOR ( 11 downto 1 );
signal \C__1\ : STD_LOGIC_VECTOR ( 11 downto 1 );
signal PCIN : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^active\ : STD_LOGIC;
signal \i___0_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_1__1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_1__2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_1__3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_1__4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_2__1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_2__2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_2__3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_2__4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_3__1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_3__2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_3__3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_3__4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_4__1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_4__2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_4__3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_4__4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_5__0_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_5__1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_5__2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_5__3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_5__4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_6__0_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_6__1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_6__2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_6__3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_6__4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_7__0_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_7__1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_7__2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_7__3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_7__4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_8__0_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_8__1_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_8__2_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_8__3_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_8__4_n_0\ : STD_LOGIC;
signal \i___0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_1__1_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_1__2_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_1__3_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_1__4_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_2__1_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_2__2_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_2__3_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_2__4_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_3__1_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_3__2_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_3__3_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_3__4_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_4__1_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_4__2_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_4__3_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_4__4_n_0\ : STD_LOGIC;
signal \i___0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_1__0_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_1__1_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_1__2_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_1__3_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_1__4_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_2__0_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_2__1_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_2__2_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_2__3_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_2__4_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_3__0_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_3__1_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_4__0_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_4__1_n_0\ : STD_LOGIC;
signal \i___0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_1__0_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_1__1_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_1_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_2__0_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_2__1_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_2_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_3__0_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_3__1_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_3_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_4__0_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_4__1_n_0\ : STD_LOGIC;
signal \i___0_carry__3_i_4_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_1__0_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_1__1_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_1_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_2__0_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_2__1_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_2_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_3__0_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_3__1_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_3_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_4__0_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_4__1_n_0\ : STD_LOGIC;
signal \i___0_carry__4_i_4_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_1__0_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_1__1_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_1_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_2__0_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_2__1_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_2_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_3__0_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_3__1_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_3_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_4__0_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_4__1_n_0\ : STD_LOGIC;
signal \i___0_carry__5_i_4_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_1__0_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_1__1_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_1_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_2__0_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_2__1_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_2_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_3__0_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_3__1_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_3_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_4__0_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_4__1_n_0\ : STD_LOGIC;
signal \i___0_carry__6_i_4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_1__0_n_0\ : STD_LOGIC;
signal \i___0_carry_i_1__1_n_0\ : STD_LOGIC;
signal \i___0_carry_i_1__2_n_0\ : STD_LOGIC;
signal \i___0_carry_i_1__3_n_0\ : STD_LOGIC;
signal \i___0_carry_i_1__4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_1_n_0\ : STD_LOGIC;
signal \i___0_carry_i_2__0_n_0\ : STD_LOGIC;
signal \i___0_carry_i_2__1_n_0\ : STD_LOGIC;
signal \i___0_carry_i_2__2_n_0\ : STD_LOGIC;
signal \i___0_carry_i_2__3_n_0\ : STD_LOGIC;
signal \i___0_carry_i_2__4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_2_n_0\ : STD_LOGIC;
signal \i___0_carry_i_3__0_n_0\ : STD_LOGIC;
signal \i___0_carry_i_3__1_n_0\ : STD_LOGIC;
signal \i___0_carry_i_3__2_n_0\ : STD_LOGIC;
signal \i___0_carry_i_3__3_n_0\ : STD_LOGIC;
signal \i___0_carry_i_3__4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_3_n_0\ : STD_LOGIC;
signal \i___0_carry_i_4__0_n_0\ : STD_LOGIC;
signal \i___0_carry_i_4__1_n_0\ : STD_LOGIC;
signal \i___0_carry_i_4__2_n_0\ : STD_LOGIC;
signal \i___0_carry_i_4__3_n_0\ : STD_LOGIC;
signal \i___0_carry_i_4__4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_5__0_n_0\ : STD_LOGIC;
signal \i___0_carry_i_5__1_n_0\ : STD_LOGIC;
signal \i___0_carry_i_5__2_n_0\ : STD_LOGIC;
signal \i___0_carry_i_5__3_n_0\ : STD_LOGIC;
signal \i___0_carry_i_5__4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_5_n_0\ : STD_LOGIC;
signal \i___0_carry_i_6__0_n_0\ : STD_LOGIC;
signal \i___0_carry_i_6__1_n_0\ : STD_LOGIC;
signal \i___0_carry_i_6__2_n_0\ : STD_LOGIC;
signal \i___0_carry_i_6__3_n_0\ : STD_LOGIC;
signal \i___0_carry_i_6__4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_6_n_0\ : STD_LOGIC;
signal \i___0_carry_i_7__0_n_0\ : STD_LOGIC;
signal \i___0_carry_i_7__1_n_0\ : STD_LOGIC;
signal \i___0_carry_i_7__2_n_0\ : STD_LOGIC;
signal \i___0_carry_i_7__3_n_0\ : STD_LOGIC;
signal \i___0_carry_i_7__4_n_0\ : STD_LOGIC;
signal \i___0_carry_i_7_n_0\ : STD_LOGIC;
signal \i___24_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \i___24_carry__0_i_1_n_0\ : STD_LOGIC;
signal \i___24_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \i___24_carry__0_i_2_n_0\ : STD_LOGIC;
signal \i___24_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \i___24_carry__0_i_3_n_0\ : STD_LOGIC;
signal \i___24_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \i___24_carry__0_i_4_n_0\ : STD_LOGIC;
signal \i___24_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \i___24_carry__1_i_1_n_0\ : STD_LOGIC;
signal \i___24_carry_i_1__0_n_0\ : STD_LOGIC;
signal \i___24_carry_i_1_n_0\ : STD_LOGIC;
signal \i___24_carry_i_2__0_n_0\ : STD_LOGIC;
signal \i___24_carry_i_2_n_0\ : STD_LOGIC;
signal \i___24_carry_i_3__0_n_0\ : STD_LOGIC;
signal \i___24_carry_i_3_n_0\ : STD_LOGIC;
signal \i___24_carry_i_4__0_n_0\ : STD_LOGIC;
signal \i___24_carry_i_4_n_0\ : STD_LOGIC;
signal \i___50_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \i___50_carry__0_i_1_n_0\ : STD_LOGIC;
signal \i___50_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \i___50_carry__0_i_2_n_0\ : STD_LOGIC;
signal \i___50_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \i___50_carry__0_i_3_n_0\ : STD_LOGIC;
signal \i___50_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \i___50_carry__0_i_4_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_1_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_2_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_3_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_4_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_5__0_n_0\ : STD_LOGIC;
signal \i___50_carry__1_i_5_n_0\ : STD_LOGIC;
signal \i___50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \i___50_carry_i_1_n_0\ : STD_LOGIC;
signal \i___50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \i___50_carry_i_2_n_0\ : STD_LOGIC;
signal \i___50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \i___50_carry_i_3_n_0\ : STD_LOGIC;
signal \i___82_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \i___82_carry__0_i_1_n_0\ : STD_LOGIC;
signal \i___82_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \i___82_carry__0_i_2_n_0\ : STD_LOGIC;
signal \i___82_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \i___82_carry__0_i_3_n_0\ : STD_LOGIC;
signal \i___82_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \i___82_carry__0_i_4_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_1_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_2_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_3_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_4_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_5__0_n_0\ : STD_LOGIC;
signal \i___82_carry__1_i_5_n_0\ : STD_LOGIC;
signal \i___82_carry__2_i_1__0_n_0\ : STD_LOGIC;
signal \i___82_carry__2_i_1_n_0\ : STD_LOGIC;
signal \i___82_carry__2_i_2__0_n_3\ : STD_LOGIC;
signal \i___82_carry__2_i_2_n_3\ : STD_LOGIC;
signal \i___82_carry_i_1__0_n_0\ : STD_LOGIC;
signal \i___82_carry_i_1_n_0\ : STD_LOGIC;
signal \i___82_carry_i_2__0_n_0\ : STD_LOGIC;
signal \i___82_carry_i_2_n_0\ : STD_LOGIC;
signal \i___82_carry_i_3__0_n_0\ : STD_LOGIC;
signal \i___82_carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1__1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1__2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2__1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2__2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3__1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3__2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4__1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4__2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__0_i_5__0_n_0\ : STD_LOGIC;
signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
signal \i__carry__0_i_6__0_n_0\ : STD_LOGIC;
signal \i__carry__0_i_6_n_0\ : STD_LOGIC;
signal \i__carry__0_i_7__0_n_0\ : STD_LOGIC;
signal \i__carry__0_i_7_n_0\ : STD_LOGIC;
signal \i__carry__0_i_8__0_n_0\ : STD_LOGIC;
signal \i__carry__0_i_8_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1__1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1__2_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \i__carry__1_i_3_n_0\ : STD_LOGIC;
signal \i__carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \i__carry__1_i_4_n_0\ : STD_LOGIC;
signal \i__carry__1_i_5__0_n_0\ : STD_LOGIC;
signal \i__carry__1_i_5_n_0\ : STD_LOGIC;
signal \i__carry__1_i_6__0_n_0\ : STD_LOGIC;
signal \i__carry__1_i_6_n_0\ : STD_LOGIC;
signal \i__carry__1_i_7__0_n_0\ : STD_LOGIC;
signal \i__carry__1_i_7_n_0\ : STD_LOGIC;
signal \i__carry__1_i_8__0_n_0\ : STD_LOGIC;
signal \i__carry__1_i_8_n_0\ : STD_LOGIC;
signal \i__carry__2_i_1__0_n_0\ : STD_LOGIC;
signal \i__carry__2_i_1_n_0\ : STD_LOGIC;
signal \i__carry__2_i_2__0_n_0\ : STD_LOGIC;
signal \i__carry__2_i_2_n_0\ : STD_LOGIC;
signal \i__carry__2_i_3__0_n_0\ : STD_LOGIC;
signal \i__carry__2_i_3_n_0\ : STD_LOGIC;
signal \i__carry__2_i_4__0_n_0\ : STD_LOGIC;
signal \i__carry__2_i_4_n_0\ : STD_LOGIC;
signal \i__carry__2_i_5__0_n_0\ : STD_LOGIC;
signal \i__carry__2_i_5_n_0\ : STD_LOGIC;
signal \i__carry__2_i_6__0_n_0\ : STD_LOGIC;
signal \i__carry__2_i_6_n_0\ : STD_LOGIC;
signal \i__carry__2_i_7__0_n_0\ : STD_LOGIC;
signal \i__carry__2_i_7_n_0\ : STD_LOGIC;
signal \i__carry__2_i_8__0_n_0\ : STD_LOGIC;
signal \i__carry__2_i_8_n_0\ : STD_LOGIC;
signal \i__carry_i_1__0_n_0\ : STD_LOGIC;
signal \i__carry_i_1__1_n_0\ : STD_LOGIC;
signal \i__carry_i_1__2_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_2__0_n_0\ : STD_LOGIC;
signal \i__carry_i_2__1_n_0\ : STD_LOGIC;
signal \i__carry_i_2__2_n_0\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3__0_n_0\ : STD_LOGIC;
signal \i__carry_i_3__1_n_0\ : STD_LOGIC;
signal \i__carry_i_3__2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4__0_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal \i__carry_i_5__0_n_0\ : STD_LOGIC;
signal \i__carry_i_5_n_0\ : STD_LOGIC;
signal \i__carry_i_6__0_n_0\ : STD_LOGIC;
signal \i__carry_i_6_n_0\ : STD_LOGIC;
signal \i__carry_i_7__0_n_0\ : STD_LOGIC;
signal \i__carry_i_7_n_0\ : STD_LOGIC;
signal \i__carry_i_8__0_n_0\ : STD_LOGIC;
signal \i__carry_i_8_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_7_out : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb_blur3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \rgb_blur3__24_carry__0_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3__24_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3__24_carry__1_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3__24_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3__24_carry_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3__24_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3__24_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3__24_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3__24_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3__24_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3__24_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3__24_carry_n_7\ : STD_LOGIC;
signal \rgb_blur3__50_carry__0_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__0_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__0_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__0_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3__50_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3__50_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3__50_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3__50_carry_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3__50_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3__50_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3__50_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3__82_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_n_4\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_n_5\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_n_6\ : STD_LOGIC;
signal \rgb_blur3__82_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3__82_carry__2_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry__2_i_2_n_3\ : STD_LOGIC;
signal \rgb_blur3__82_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3__82_carry__2_n_7\ : STD_LOGIC;
signal \rgb_blur3__82_carry_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3__82_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3__82_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3__82_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3__82_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3__82_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3__82_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_carry__0_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3_carry__0_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur3_carry__0_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur3_carry__0_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur3_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_carry__1_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur3_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_carry__1_n_7\ : STD_LOGIC;
signal rgb_blur3_carry_i_1_n_0 : STD_LOGIC;
signal rgb_blur3_carry_i_2_n_0 : STD_LOGIC;
signal rgb_blur3_carry_i_3_n_0 : STD_LOGIC;
signal rgb_blur3_carry_n_0 : STD_LOGIC;
signal rgb_blur3_carry_n_1 : STD_LOGIC;
signal rgb_blur3_carry_n_2 : STD_LOGIC;
signal rgb_blur3_carry_n_3 : STD_LOGIC;
signal rgb_blur3_carry_n_4 : STD_LOGIC;
signal rgb_blur3_carry_n_5 : STD_LOGIC;
signal rgb_blur3_carry_n_6 : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__1_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__1_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__1_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__2_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__2_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__2_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry__2_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__0/i___0_carry_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__1_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__1_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__1_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__2_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__2_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__2_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__2_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__2_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__2_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__2_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__3_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__3_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__3_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__3_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__3_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__3_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__3_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__3_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__4_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__4_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__4_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__4_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__4_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__4_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__4_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__4_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__5_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__5_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__5_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__5_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__5_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__5_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__5_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__5_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__6_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__6_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__6_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__6_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__6_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__6_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry__6_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__1/i___0_carry_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___24_carry_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___50_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__1_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__1_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__1_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry__2_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i___82_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__2/i__carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__1_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__1_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__1_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__2_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__2_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__2_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry__2_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__3/i___0_carry_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__1_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__1_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__1_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__2_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__2_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__2_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__2_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__2_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__2_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__2_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__3_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__3_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__3_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__3_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__3_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__3_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__3_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__3_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__4_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__4_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__4_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__4_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__4_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__4_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__4_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__4_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__5_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__5_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__5_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__5_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__5_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__5_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__5_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__5_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__6_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__6_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__6_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__6_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__6_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__6_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry__6_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__4/i___0_carry_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___24_carry_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___50_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__1_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__1_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__1_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry__2_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i___82_carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__0_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__0_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__0_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__0_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry__1_n_7\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry_n_4\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry_n_5\ : STD_LOGIC;
signal \rgb_blur3_inferred__5/i__carry_n_6\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry__2_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__6/i___0_carry_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__2_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__2_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__2_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__3_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__3_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__3_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__3_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__4_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__4_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__4_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__4_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__5_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__5_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__5_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__5_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__6_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__6_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry__6_n_3\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry_n_0\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry_n_1\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry_n_2\ : STD_LOGIC;
signal \rgb_blur3_inferred__7/i___0_carry_n_3\ : STD_LOGIC;
signal rgb_blur4 : STD_LOGIC;
signal \rgb_blur4_carry__0_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_i_8_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur4_carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur4_carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur4_carry__1_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_i_8_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur4_carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur4_carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur4_carry__2_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_i_8_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_n_0\ : STD_LOGIC;
signal \rgb_blur4_carry__2_n_1\ : STD_LOGIC;
signal \rgb_blur4_carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur4_carry__2_n_3\ : STD_LOGIC;
signal rgb_blur4_carry_i_1_n_0 : STD_LOGIC;
signal rgb_blur4_carry_i_2_n_0 : STD_LOGIC;
signal rgb_blur4_carry_i_3_n_0 : STD_LOGIC;
signal rgb_blur4_carry_i_4_n_0 : STD_LOGIC;
signal rgb_blur4_carry_i_5_n_0 : STD_LOGIC;
signal rgb_blur4_carry_i_6_n_0 : STD_LOGIC;
signal rgb_blur4_carry_i_7_n_0 : STD_LOGIC;
signal rgb_blur4_carry_i_8_n_0 : STD_LOGIC;
signal rgb_blur4_carry_n_0 : STD_LOGIC;
signal rgb_blur4_carry_n_1 : STD_LOGIC;
signal rgb_blur4_carry_n_2 : STD_LOGIC;
signal rgb_blur4_carry_n_3 : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__2_n_0\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__2_n_1\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry__2_n_3\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \rgb_blur4_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__0_n_0\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__0_n_1\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__0_n_2\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__0_n_3\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__1_n_0\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__1_n_1\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__1_n_2\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__1_n_3\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__2_n_1\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__2_n_2\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry__2_n_3\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry_n_0\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry_n_1\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry_n_2\ : STD_LOGIC;
signal \rgb_blur4_inferred__1/i__carry_n_3\ : STD_LOGIC;
signal \rgb_blur[10]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[10]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[11]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[12]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[12]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[12]_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur[12]_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur[12]_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur[12]_i_8_n_0\ : STD_LOGIC;
signal \rgb_blur[13]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[14]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur[15]_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur[15]_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur[15]_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur[18]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[18]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[19]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[1]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[1]_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur[1]_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur[1]_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur[1]_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur[20]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[20]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[21]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[22]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[23]_i_1_n_0\ : STD_LOGIC;
signal \rgb_blur[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[23]_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur[2]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[2]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[3]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[4]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[4]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[4]_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur[4]_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur[4]_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur[4]_i_8_n_0\ : STD_LOGIC;
signal \rgb_blur[5]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[6]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur[7]_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur[7]_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur[7]_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur[9]_i_3_n_0\ : STD_LOGIC;
signal \rgb_blur[9]_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur[9]_i_5_n_0\ : STD_LOGIC;
signal \rgb_blur[9]_i_6_n_0\ : STD_LOGIC;
signal \rgb_blur[9]_i_7_n_0\ : STD_LOGIC;
signal \rgb_blur_reg[12]_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur_reg[12]_i_4_n_1\ : STD_LOGIC;
signal \rgb_blur_reg[12]_i_4_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[12]_i_4_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[12]_i_4_n_4\ : STD_LOGIC;
signal \rgb_blur_reg[12]_i_4_n_5\ : STD_LOGIC;
signal \rgb_blur_reg[12]_i_4_n_6\ : STD_LOGIC;
signal \rgb_blur_reg[12]_i_4_n_7\ : STD_LOGIC;
signal \rgb_blur_reg[15]_i_3_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[15]_i_3_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[15]_i_3_n_5\ : STD_LOGIC;
signal \rgb_blur_reg[15]_i_3_n_6\ : STD_LOGIC;
signal \rgb_blur_reg[15]_i_3_n_7\ : STD_LOGIC;
signal \rgb_blur_reg[17]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur_reg[17]_i_2_n_1\ : STD_LOGIC;
signal \rgb_blur_reg[17]_i_2_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[17]_i_2_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[17]_i_2_n_4\ : STD_LOGIC;
signal \rgb_blur_reg[1]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur_reg[1]_i_2_n_1\ : STD_LOGIC;
signal \rgb_blur_reg[1]_i_2_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[1]_i_2_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[1]_i_2_n_4\ : STD_LOGIC;
signal \rgb_blur_reg[20]_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur_reg[20]_i_4_n_1\ : STD_LOGIC;
signal \rgb_blur_reg[20]_i_4_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[20]_i_4_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[20]_i_4_n_4\ : STD_LOGIC;
signal \rgb_blur_reg[20]_i_4_n_5\ : STD_LOGIC;
signal \rgb_blur_reg[20]_i_4_n_6\ : STD_LOGIC;
signal \rgb_blur_reg[20]_i_4_n_7\ : STD_LOGIC;
signal \rgb_blur_reg[23]_i_4_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[23]_i_4_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[23]_i_4_n_5\ : STD_LOGIC;
signal \rgb_blur_reg[23]_i_4_n_6\ : STD_LOGIC;
signal \rgb_blur_reg[23]_i_4_n_7\ : STD_LOGIC;
signal \rgb_blur_reg[4]_i_4_n_0\ : STD_LOGIC;
signal \rgb_blur_reg[4]_i_4_n_1\ : STD_LOGIC;
signal \rgb_blur_reg[4]_i_4_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[4]_i_4_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[4]_i_4_n_4\ : STD_LOGIC;
signal \rgb_blur_reg[4]_i_4_n_5\ : STD_LOGIC;
signal \rgb_blur_reg[4]_i_4_n_6\ : STD_LOGIC;
signal \rgb_blur_reg[4]_i_4_n_7\ : STD_LOGIC;
signal \rgb_blur_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[7]_i_3_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[7]_i_3_n_5\ : STD_LOGIC;
signal \rgb_blur_reg[7]_i_3_n_6\ : STD_LOGIC;
signal \rgb_blur_reg[7]_i_3_n_7\ : STD_LOGIC;
signal \rgb_blur_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \rgb_blur_reg[9]_i_2_n_1\ : STD_LOGIC;
signal \rgb_blur_reg[9]_i_2_n_2\ : STD_LOGIC;
signal \rgb_blur_reg[9]_i_2_n_3\ : STD_LOGIC;
signal \rgb_blur_reg[9]_i_2_n_4\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][0]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][10]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][11]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][12]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][13]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][14]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][15]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][16]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][17]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][18]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][19]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][1]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][20]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][21]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][22]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][23]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][2]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][3]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][4]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][5]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][6]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][7]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][8]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1026][9]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1058][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1090][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1122][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][0]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][10]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][11]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][12]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][13]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][14]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][15]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][16]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][17]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][18]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][19]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][1]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][20]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][21]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][22]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][23]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][2]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][3]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][4]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][5]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][6]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][7]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][8]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1154][9]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1186][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1218][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[1250][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[130][0]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][10]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][11]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][12]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][13]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][14]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][15]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][16]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][17]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][18]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][19]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][1]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][20]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][21]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][22]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][23]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][2]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][3]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][4]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][5]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][6]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][7]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][8]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[130][9]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[162][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[162][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[194][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[226][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[258][0]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][10]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][11]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][12]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][13]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][14]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][15]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][16]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][17]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][18]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][19]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][1]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][20]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][21]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][22]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][23]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][2]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][3]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][4]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][5]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][6]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][7]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][8]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[258][9]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[290][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[290][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[322][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[34][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[354][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[386][0]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][10]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][11]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][12]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][13]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][14]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][15]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][16]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][17]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][18]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][19]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][1]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][20]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][21]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][22]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][23]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][2]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][3]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][4]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][5]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][6]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][7]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][8]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[386][9]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[418][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[418][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[450][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[482][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[514][0]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][10]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][11]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][12]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][13]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][14]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][15]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][16]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][17]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][18]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][19]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][1]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][20]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][21]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][22]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][23]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][2]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][3]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][4]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][5]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][6]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][7]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][8]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[514][9]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[546][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[546][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[578][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[642]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \rgb_buffer_reg[66][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[66][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[674][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[706][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[738][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[770][0]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][10]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][11]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][12]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][13]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][14]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][15]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][16]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][17]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][18]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][19]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][1]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][20]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][21]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][22]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][23]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][2]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][3]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][4]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][5]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][6]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][7]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][8]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[770][9]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[802][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[802][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[834][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[866][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[898][0]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][10]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][11]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][12]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][13]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][14]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][15]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][16]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][17]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][18]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][19]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][1]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][20]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][21]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][22]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][23]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][2]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][3]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][4]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][5]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][6]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][7]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][8]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[898][9]_srl32_n_0\ : STD_LOGIC;
signal \rgb_buffer_reg[930][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[930][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[962][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[98][9]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][0]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][10]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][11]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][12]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][13]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][14]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][15]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][16]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][17]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][18]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][19]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][1]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][20]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][21]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][22]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][23]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][2]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][3]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][4]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][5]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][6]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][7]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][8]_srl32_n_1\ : STD_LOGIC;
signal \rgb_buffer_reg[994][9]_srl32_n_1\ : STD_LOGIC;
signal \NLW_i___82_carry__2_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_i___82_carry__2_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_i___82_carry__2_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_i___82_carry__2_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3__24_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3__24_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3__50_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3__82_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3__82_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3__82_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3__82_carry__2_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3__82_carry__2_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_rgb_blur3_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3_inferred__0/i___0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rgb_blur3_inferred__0/i___0_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_blur3_inferred__1/i___0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_blur3_inferred__2/i___24_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3_inferred__2/i___24_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3_inferred__2/i___50_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3_inferred__2/i___82_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3_inferred__2/i___82_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3_inferred__2/i___82_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3_inferred__2/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3_inferred__2/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3_inferred__2/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3_inferred__3/i___0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rgb_blur3_inferred__3/i___0_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_blur3_inferred__4/i___0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_blur3_inferred__5/i___24_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3_inferred__5/i___24_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3_inferred__5/i___50_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3_inferred__5/i___82_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3_inferred__5/i___82_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3_inferred__5/i___82_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3_inferred__5/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_rgb_blur3_inferred__5/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur3_inferred__5/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rgb_blur3_inferred__6/i___0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rgb_blur3_inferred__6/i___0_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_blur3_inferred__7/i___0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_rgb_blur4_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_inferred__0/i__carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_inferred__1/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_inferred__1/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur4_inferred__1/i__carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_rgb_blur_reg[15]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rgb_blur_reg[15]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_blur_reg[17]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_rgb_blur_reg[1]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_rgb_blur_reg[23]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rgb_blur_reg[23]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_blur_reg[7]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rgb_blur_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_blur_reg[9]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_rgb_buffer_reg[1026][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1026][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1058][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1090][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1122][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1154][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1186][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1218][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1250][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][0]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][10]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][11]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][12]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][13]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][14]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][15]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][16]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][17]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][18]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][19]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][1]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][20]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][21]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][22]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][23]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][2]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][3]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][4]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][5]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][6]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][7]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][8]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[1279][9]_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[130][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[162][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[194][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[226][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[258][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[290][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[322][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[34][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[354][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[386][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[418][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[450][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[482][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[514][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[546][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[578][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[610][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[66][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[674][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[706][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[738][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[770][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[802][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[834][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[866][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[898][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[930][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[962][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[98][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][0]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][10]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][11]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][12]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][13]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][14]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][15]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][16]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][17]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][18]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][19]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][1]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][20]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][21]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][22]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][23]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][2]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][3]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][4]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][5]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][6]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][7]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][8]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
signal \NLW_rgb_buffer_reg[994][9]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
attribute HLUTNM : string;
attribute HLUTNM of \i___0_carry__0_i_1__0\ : label is "lutpair12";
attribute HLUTNM of \i___0_carry__0_i_1__2\ : label is "lutpair25";
attribute HLUTNM of \i___0_carry__0_i_1__4\ : label is "lutpair38";
attribute HLUTNM of \i___0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \i___0_carry__0_i_2__0\ : label is "lutpair11";
attribute HLUTNM of \i___0_carry__0_i_2__1\ : label is "lutpair18";
attribute HLUTNM of \i___0_carry__0_i_2__2\ : label is "lutpair24";
attribute HLUTNM of \i___0_carry__0_i_2__3\ : label is "lutpair31";
attribute HLUTNM of \i___0_carry__0_i_2__4\ : label is "lutpair37";
attribute HLUTNM of \i___0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \i___0_carry__0_i_3__0\ : label is "lutpair10";
attribute HLUTNM of \i___0_carry__0_i_3__1\ : label is "lutpair17";
attribute HLUTNM of \i___0_carry__0_i_3__2\ : label is "lutpair23";
attribute HLUTNM of \i___0_carry__0_i_3__3\ : label is "lutpair30";
attribute HLUTNM of \i___0_carry__0_i_3__4\ : label is "lutpair36";
attribute HLUTNM of \i___0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \i___0_carry__0_i_4__0\ : label is "lutpair9";
attribute HLUTNM of \i___0_carry__0_i_4__1\ : label is "lutpair16";
attribute HLUTNM of \i___0_carry__0_i_4__2\ : label is "lutpair22";
attribute HLUTNM of \i___0_carry__0_i_4__3\ : label is "lutpair29";
attribute HLUTNM of \i___0_carry__0_i_4__4\ : label is "lutpair35";
attribute HLUTNM of \i___0_carry__0_i_6__0\ : label is "lutpair12";
attribute HLUTNM of \i___0_carry__0_i_6__2\ : label is "lutpair25";
attribute HLUTNM of \i___0_carry__0_i_6__4\ : label is "lutpair38";
attribute HLUTNM of \i___0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \i___0_carry__0_i_7__0\ : label is "lutpair11";
attribute HLUTNM of \i___0_carry__0_i_7__1\ : label is "lutpair18";
attribute HLUTNM of \i___0_carry__0_i_7__2\ : label is "lutpair24";
attribute HLUTNM of \i___0_carry__0_i_7__3\ : label is "lutpair31";
attribute HLUTNM of \i___0_carry__0_i_7__4\ : label is "lutpair37";
attribute HLUTNM of \i___0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \i___0_carry__0_i_8__0\ : label is "lutpair10";
attribute HLUTNM of \i___0_carry__0_i_8__1\ : label is "lutpair17";
attribute HLUTNM of \i___0_carry__0_i_8__2\ : label is "lutpair23";
attribute HLUTNM of \i___0_carry__0_i_8__3\ : label is "lutpair30";
attribute HLUTNM of \i___0_carry__0_i_8__4\ : label is "lutpair36";
attribute HLUTNM of \i___0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \i___0_carry_i_1__0\ : label is "lutpair8";
attribute HLUTNM of \i___0_carry_i_1__1\ : label is "lutpair15";
attribute HLUTNM of \i___0_carry_i_1__2\ : label is "lutpair21";
attribute HLUTNM of \i___0_carry_i_1__3\ : label is "lutpair28";
attribute HLUTNM of \i___0_carry_i_1__4\ : label is "lutpair34";
attribute HLUTNM of \i___0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \i___0_carry_i_2__0\ : label is "lutpair7";
attribute HLUTNM of \i___0_carry_i_2__1\ : label is "lutpair14";
attribute HLUTNM of \i___0_carry_i_2__2\ : label is "lutpair20";
attribute HLUTNM of \i___0_carry_i_2__3\ : label is "lutpair27";
attribute HLUTNM of \i___0_carry_i_2__4\ : label is "lutpair33";
attribute HLUTNM of \i___0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \i___0_carry_i_3__0\ : label is "lutpair6";
attribute HLUTNM of \i___0_carry_i_3__1\ : label is "lutpair13";
attribute HLUTNM of \i___0_carry_i_3__2\ : label is "lutpair19";
attribute HLUTNM of \i___0_carry_i_3__3\ : label is "lutpair26";
attribute HLUTNM of \i___0_carry_i_3__4\ : label is "lutpair32";
attribute HLUTNM of \i___0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \i___0_carry_i_4__0\ : label is "lutpair9";
attribute HLUTNM of \i___0_carry_i_4__1\ : label is "lutpair16";
attribute HLUTNM of \i___0_carry_i_4__2\ : label is "lutpair22";
attribute HLUTNM of \i___0_carry_i_4__3\ : label is "lutpair29";
attribute HLUTNM of \i___0_carry_i_4__4\ : label is "lutpair35";
attribute HLUTNM of \i___0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \i___0_carry_i_5__0\ : label is "lutpair8";
attribute HLUTNM of \i___0_carry_i_5__1\ : label is "lutpair15";
attribute HLUTNM of \i___0_carry_i_5__2\ : label is "lutpair21";
attribute HLUTNM of \i___0_carry_i_5__3\ : label is "lutpair28";
attribute HLUTNM of \i___0_carry_i_5__4\ : label is "lutpair34";
attribute HLUTNM of \i___0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \i___0_carry_i_6__0\ : label is "lutpair7";
attribute HLUTNM of \i___0_carry_i_6__1\ : label is "lutpair14";
attribute HLUTNM of \i___0_carry_i_6__2\ : label is "lutpair20";
attribute HLUTNM of \i___0_carry_i_6__3\ : label is "lutpair27";
attribute HLUTNM of \i___0_carry_i_6__4\ : label is "lutpair33";
attribute HLUTNM of \i___0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \i___0_carry_i_7__0\ : label is "lutpair6";
attribute HLUTNM of \i___0_carry_i_7__1\ : label is "lutpair13";
attribute HLUTNM of \i___0_carry_i_7__2\ : label is "lutpair19";
attribute HLUTNM of \i___0_carry_i_7__3\ : label is "lutpair26";
attribute HLUTNM of \i___0_carry_i_7__4\ : label is "lutpair32";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb_blur[10]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb_blur[10]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb_blur[12]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb_blur[12]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb_blur[18]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb_blur[18]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb_blur[20]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb_blur[20]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb_blur[2]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb_blur[2]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb_blur[4]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb_blur[4]_i_3\ : label is "soft_lutpair3";
attribute srl_bus_name : string;
attribute srl_bus_name of \rgb_buffer_reg[1026][0]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name : string;
attribute srl_name of \rgb_buffer_reg[1026][0]_srl32\ : label is "\U0/rgb_buffer_reg[1026][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][10]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][10]_srl32\ : label is "\U0/rgb_buffer_reg[1026][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][11]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][11]_srl32\ : label is "\U0/rgb_buffer_reg[1026][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][12]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][12]_srl32\ : label is "\U0/rgb_buffer_reg[1026][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][13]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][13]_srl32\ : label is "\U0/rgb_buffer_reg[1026][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][14]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][14]_srl32\ : label is "\U0/rgb_buffer_reg[1026][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][15]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][15]_srl32\ : label is "\U0/rgb_buffer_reg[1026][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][16]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][16]_srl32\ : label is "\U0/rgb_buffer_reg[1026][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][17]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][17]_srl32\ : label is "\U0/rgb_buffer_reg[1026][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][18]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][18]_srl32\ : label is "\U0/rgb_buffer_reg[1026][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][19]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][19]_srl32\ : label is "\U0/rgb_buffer_reg[1026][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][1]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][1]_srl32\ : label is "\U0/rgb_buffer_reg[1026][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][20]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][20]_srl32\ : label is "\U0/rgb_buffer_reg[1026][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][21]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][21]_srl32\ : label is "\U0/rgb_buffer_reg[1026][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][22]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][22]_srl32\ : label is "\U0/rgb_buffer_reg[1026][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][23]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][23]_srl32\ : label is "\U0/rgb_buffer_reg[1026][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][2]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][2]_srl32\ : label is "\U0/rgb_buffer_reg[1026][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][3]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][3]_srl32\ : label is "\U0/rgb_buffer_reg[1026][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][4]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][4]_srl32\ : label is "\U0/rgb_buffer_reg[1026][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][5]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][5]_srl32\ : label is "\U0/rgb_buffer_reg[1026][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][6]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][6]_srl32\ : label is "\U0/rgb_buffer_reg[1026][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][7]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][7]_srl32\ : label is "\U0/rgb_buffer_reg[1026][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][8]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][8]_srl32\ : label is "\U0/rgb_buffer_reg[1026][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1026][9]_srl32\ : label is "\U0/rgb_buffer_reg[1026] ";
attribute srl_name of \rgb_buffer_reg[1026][9]_srl32\ : label is "\U0/rgb_buffer_reg[1026][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][0]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][0]_srl32\ : label is "\U0/rgb_buffer_reg[1058][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][10]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][10]_srl32\ : label is "\U0/rgb_buffer_reg[1058][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][11]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][11]_srl32\ : label is "\U0/rgb_buffer_reg[1058][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][12]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][12]_srl32\ : label is "\U0/rgb_buffer_reg[1058][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][13]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][13]_srl32\ : label is "\U0/rgb_buffer_reg[1058][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][14]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][14]_srl32\ : label is "\U0/rgb_buffer_reg[1058][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][15]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][15]_srl32\ : label is "\U0/rgb_buffer_reg[1058][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][16]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][16]_srl32\ : label is "\U0/rgb_buffer_reg[1058][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][17]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][17]_srl32\ : label is "\U0/rgb_buffer_reg[1058][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][18]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][18]_srl32\ : label is "\U0/rgb_buffer_reg[1058][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][19]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][19]_srl32\ : label is "\U0/rgb_buffer_reg[1058][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][1]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][1]_srl32\ : label is "\U0/rgb_buffer_reg[1058][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][20]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][20]_srl32\ : label is "\U0/rgb_buffer_reg[1058][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][21]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][21]_srl32\ : label is "\U0/rgb_buffer_reg[1058][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][22]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][22]_srl32\ : label is "\U0/rgb_buffer_reg[1058][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][23]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][23]_srl32\ : label is "\U0/rgb_buffer_reg[1058][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][2]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][2]_srl32\ : label is "\U0/rgb_buffer_reg[1058][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][3]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][3]_srl32\ : label is "\U0/rgb_buffer_reg[1058][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][4]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][4]_srl32\ : label is "\U0/rgb_buffer_reg[1058][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][5]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][5]_srl32\ : label is "\U0/rgb_buffer_reg[1058][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][6]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][6]_srl32\ : label is "\U0/rgb_buffer_reg[1058][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][7]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][7]_srl32\ : label is "\U0/rgb_buffer_reg[1058][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][8]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][8]_srl32\ : label is "\U0/rgb_buffer_reg[1058][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1058][9]_srl32\ : label is "\U0/rgb_buffer_reg[1058] ";
attribute srl_name of \rgb_buffer_reg[1058][9]_srl32\ : label is "\U0/rgb_buffer_reg[1058][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][0]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][0]_srl32\ : label is "\U0/rgb_buffer_reg[1090][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][10]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][10]_srl32\ : label is "\U0/rgb_buffer_reg[1090][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][11]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][11]_srl32\ : label is "\U0/rgb_buffer_reg[1090][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][12]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][12]_srl32\ : label is "\U0/rgb_buffer_reg[1090][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][13]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][13]_srl32\ : label is "\U0/rgb_buffer_reg[1090][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][14]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][14]_srl32\ : label is "\U0/rgb_buffer_reg[1090][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][15]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][15]_srl32\ : label is "\U0/rgb_buffer_reg[1090][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][16]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][16]_srl32\ : label is "\U0/rgb_buffer_reg[1090][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][17]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][17]_srl32\ : label is "\U0/rgb_buffer_reg[1090][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][18]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][18]_srl32\ : label is "\U0/rgb_buffer_reg[1090][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][19]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][19]_srl32\ : label is "\U0/rgb_buffer_reg[1090][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][1]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][1]_srl32\ : label is "\U0/rgb_buffer_reg[1090][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][20]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][20]_srl32\ : label is "\U0/rgb_buffer_reg[1090][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][21]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][21]_srl32\ : label is "\U0/rgb_buffer_reg[1090][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][22]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][22]_srl32\ : label is "\U0/rgb_buffer_reg[1090][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][23]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][23]_srl32\ : label is "\U0/rgb_buffer_reg[1090][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][2]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][2]_srl32\ : label is "\U0/rgb_buffer_reg[1090][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][3]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][3]_srl32\ : label is "\U0/rgb_buffer_reg[1090][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][4]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][4]_srl32\ : label is "\U0/rgb_buffer_reg[1090][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][5]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][5]_srl32\ : label is "\U0/rgb_buffer_reg[1090][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][6]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][6]_srl32\ : label is "\U0/rgb_buffer_reg[1090][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][7]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][7]_srl32\ : label is "\U0/rgb_buffer_reg[1090][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][8]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][8]_srl32\ : label is "\U0/rgb_buffer_reg[1090][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1090][9]_srl32\ : label is "\U0/rgb_buffer_reg[1090] ";
attribute srl_name of \rgb_buffer_reg[1090][9]_srl32\ : label is "\U0/rgb_buffer_reg[1090][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][0]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][0]_srl32\ : label is "\U0/rgb_buffer_reg[1122][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][10]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][10]_srl32\ : label is "\U0/rgb_buffer_reg[1122][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][11]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][11]_srl32\ : label is "\U0/rgb_buffer_reg[1122][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][12]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][12]_srl32\ : label is "\U0/rgb_buffer_reg[1122][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][13]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][13]_srl32\ : label is "\U0/rgb_buffer_reg[1122][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][14]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][14]_srl32\ : label is "\U0/rgb_buffer_reg[1122][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][15]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][15]_srl32\ : label is "\U0/rgb_buffer_reg[1122][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][16]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][16]_srl32\ : label is "\U0/rgb_buffer_reg[1122][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][17]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][17]_srl32\ : label is "\U0/rgb_buffer_reg[1122][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][18]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][18]_srl32\ : label is "\U0/rgb_buffer_reg[1122][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][19]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][19]_srl32\ : label is "\U0/rgb_buffer_reg[1122][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][1]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][1]_srl32\ : label is "\U0/rgb_buffer_reg[1122][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][20]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][20]_srl32\ : label is "\U0/rgb_buffer_reg[1122][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][21]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][21]_srl32\ : label is "\U0/rgb_buffer_reg[1122][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][22]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][22]_srl32\ : label is "\U0/rgb_buffer_reg[1122][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][23]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][23]_srl32\ : label is "\U0/rgb_buffer_reg[1122][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][2]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][2]_srl32\ : label is "\U0/rgb_buffer_reg[1122][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][3]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][3]_srl32\ : label is "\U0/rgb_buffer_reg[1122][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][4]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][4]_srl32\ : label is "\U0/rgb_buffer_reg[1122][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][5]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][5]_srl32\ : label is "\U0/rgb_buffer_reg[1122][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][6]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][6]_srl32\ : label is "\U0/rgb_buffer_reg[1122][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][7]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][7]_srl32\ : label is "\U0/rgb_buffer_reg[1122][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][8]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][8]_srl32\ : label is "\U0/rgb_buffer_reg[1122][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1122][9]_srl32\ : label is "\U0/rgb_buffer_reg[1122] ";
attribute srl_name of \rgb_buffer_reg[1122][9]_srl32\ : label is "\U0/rgb_buffer_reg[1122][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][0]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][0]_srl32\ : label is "\U0/rgb_buffer_reg[1154][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][10]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][10]_srl32\ : label is "\U0/rgb_buffer_reg[1154][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][11]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][11]_srl32\ : label is "\U0/rgb_buffer_reg[1154][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][12]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][12]_srl32\ : label is "\U0/rgb_buffer_reg[1154][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][13]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][13]_srl32\ : label is "\U0/rgb_buffer_reg[1154][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][14]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][14]_srl32\ : label is "\U0/rgb_buffer_reg[1154][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][15]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][15]_srl32\ : label is "\U0/rgb_buffer_reg[1154][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][16]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][16]_srl32\ : label is "\U0/rgb_buffer_reg[1154][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][17]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][17]_srl32\ : label is "\U0/rgb_buffer_reg[1154][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][18]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][18]_srl32\ : label is "\U0/rgb_buffer_reg[1154][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][19]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][19]_srl32\ : label is "\U0/rgb_buffer_reg[1154][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][1]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][1]_srl32\ : label is "\U0/rgb_buffer_reg[1154][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][20]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][20]_srl32\ : label is "\U0/rgb_buffer_reg[1154][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][21]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][21]_srl32\ : label is "\U0/rgb_buffer_reg[1154][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][22]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][22]_srl32\ : label is "\U0/rgb_buffer_reg[1154][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][23]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][23]_srl32\ : label is "\U0/rgb_buffer_reg[1154][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][2]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][2]_srl32\ : label is "\U0/rgb_buffer_reg[1154][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][3]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][3]_srl32\ : label is "\U0/rgb_buffer_reg[1154][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][4]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][4]_srl32\ : label is "\U0/rgb_buffer_reg[1154][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][5]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][5]_srl32\ : label is "\U0/rgb_buffer_reg[1154][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][6]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][6]_srl32\ : label is "\U0/rgb_buffer_reg[1154][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][7]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][7]_srl32\ : label is "\U0/rgb_buffer_reg[1154][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][8]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][8]_srl32\ : label is "\U0/rgb_buffer_reg[1154][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1154][9]_srl32\ : label is "\U0/rgb_buffer_reg[1154] ";
attribute srl_name of \rgb_buffer_reg[1154][9]_srl32\ : label is "\U0/rgb_buffer_reg[1154][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][0]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][0]_srl32\ : label is "\U0/rgb_buffer_reg[1186][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][10]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][10]_srl32\ : label is "\U0/rgb_buffer_reg[1186][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][11]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][11]_srl32\ : label is "\U0/rgb_buffer_reg[1186][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][12]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][12]_srl32\ : label is "\U0/rgb_buffer_reg[1186][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][13]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][13]_srl32\ : label is "\U0/rgb_buffer_reg[1186][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][14]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][14]_srl32\ : label is "\U0/rgb_buffer_reg[1186][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][15]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][15]_srl32\ : label is "\U0/rgb_buffer_reg[1186][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][16]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][16]_srl32\ : label is "\U0/rgb_buffer_reg[1186][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][17]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][17]_srl32\ : label is "\U0/rgb_buffer_reg[1186][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][18]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][18]_srl32\ : label is "\U0/rgb_buffer_reg[1186][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][19]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][19]_srl32\ : label is "\U0/rgb_buffer_reg[1186][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][1]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][1]_srl32\ : label is "\U0/rgb_buffer_reg[1186][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][20]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][20]_srl32\ : label is "\U0/rgb_buffer_reg[1186][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][21]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][21]_srl32\ : label is "\U0/rgb_buffer_reg[1186][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][22]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][22]_srl32\ : label is "\U0/rgb_buffer_reg[1186][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][23]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][23]_srl32\ : label is "\U0/rgb_buffer_reg[1186][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][2]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][2]_srl32\ : label is "\U0/rgb_buffer_reg[1186][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][3]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][3]_srl32\ : label is "\U0/rgb_buffer_reg[1186][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][4]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][4]_srl32\ : label is "\U0/rgb_buffer_reg[1186][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][5]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][5]_srl32\ : label is "\U0/rgb_buffer_reg[1186][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][6]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][6]_srl32\ : label is "\U0/rgb_buffer_reg[1186][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][7]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][7]_srl32\ : label is "\U0/rgb_buffer_reg[1186][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][8]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][8]_srl32\ : label is "\U0/rgb_buffer_reg[1186][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1186][9]_srl32\ : label is "\U0/rgb_buffer_reg[1186] ";
attribute srl_name of \rgb_buffer_reg[1186][9]_srl32\ : label is "\U0/rgb_buffer_reg[1186][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][0]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][0]_srl32\ : label is "\U0/rgb_buffer_reg[1218][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][10]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][10]_srl32\ : label is "\U0/rgb_buffer_reg[1218][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][11]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][11]_srl32\ : label is "\U0/rgb_buffer_reg[1218][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][12]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][12]_srl32\ : label is "\U0/rgb_buffer_reg[1218][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][13]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][13]_srl32\ : label is "\U0/rgb_buffer_reg[1218][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][14]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][14]_srl32\ : label is "\U0/rgb_buffer_reg[1218][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][15]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][15]_srl32\ : label is "\U0/rgb_buffer_reg[1218][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][16]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][16]_srl32\ : label is "\U0/rgb_buffer_reg[1218][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][17]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][17]_srl32\ : label is "\U0/rgb_buffer_reg[1218][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][18]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][18]_srl32\ : label is "\U0/rgb_buffer_reg[1218][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][19]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][19]_srl32\ : label is "\U0/rgb_buffer_reg[1218][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][1]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][1]_srl32\ : label is "\U0/rgb_buffer_reg[1218][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][20]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][20]_srl32\ : label is "\U0/rgb_buffer_reg[1218][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][21]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][21]_srl32\ : label is "\U0/rgb_buffer_reg[1218][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][22]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][22]_srl32\ : label is "\U0/rgb_buffer_reg[1218][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][23]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][23]_srl32\ : label is "\U0/rgb_buffer_reg[1218][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][2]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][2]_srl32\ : label is "\U0/rgb_buffer_reg[1218][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][3]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][3]_srl32\ : label is "\U0/rgb_buffer_reg[1218][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][4]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][4]_srl32\ : label is "\U0/rgb_buffer_reg[1218][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][5]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][5]_srl32\ : label is "\U0/rgb_buffer_reg[1218][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][6]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][6]_srl32\ : label is "\U0/rgb_buffer_reg[1218][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][7]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][7]_srl32\ : label is "\U0/rgb_buffer_reg[1218][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][8]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][8]_srl32\ : label is "\U0/rgb_buffer_reg[1218][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1218][9]_srl32\ : label is "\U0/rgb_buffer_reg[1218] ";
attribute srl_name of \rgb_buffer_reg[1218][9]_srl32\ : label is "\U0/rgb_buffer_reg[1218][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][0]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][0]_srl32\ : label is "\U0/rgb_buffer_reg[1250][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][10]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][10]_srl32\ : label is "\U0/rgb_buffer_reg[1250][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][11]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][11]_srl32\ : label is "\U0/rgb_buffer_reg[1250][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][12]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][12]_srl32\ : label is "\U0/rgb_buffer_reg[1250][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][13]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][13]_srl32\ : label is "\U0/rgb_buffer_reg[1250][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][14]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][14]_srl32\ : label is "\U0/rgb_buffer_reg[1250][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][15]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][15]_srl32\ : label is "\U0/rgb_buffer_reg[1250][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][16]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][16]_srl32\ : label is "\U0/rgb_buffer_reg[1250][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][17]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][17]_srl32\ : label is "\U0/rgb_buffer_reg[1250][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][18]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][18]_srl32\ : label is "\U0/rgb_buffer_reg[1250][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][19]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][19]_srl32\ : label is "\U0/rgb_buffer_reg[1250][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][1]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][1]_srl32\ : label is "\U0/rgb_buffer_reg[1250][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][20]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][20]_srl32\ : label is "\U0/rgb_buffer_reg[1250][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][21]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][21]_srl32\ : label is "\U0/rgb_buffer_reg[1250][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][22]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][22]_srl32\ : label is "\U0/rgb_buffer_reg[1250][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][23]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][23]_srl32\ : label is "\U0/rgb_buffer_reg[1250][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][2]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][2]_srl32\ : label is "\U0/rgb_buffer_reg[1250][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][3]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][3]_srl32\ : label is "\U0/rgb_buffer_reg[1250][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][4]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][4]_srl32\ : label is "\U0/rgb_buffer_reg[1250][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][5]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][5]_srl32\ : label is "\U0/rgb_buffer_reg[1250][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][6]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][6]_srl32\ : label is "\U0/rgb_buffer_reg[1250][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][7]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][7]_srl32\ : label is "\U0/rgb_buffer_reg[1250][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][8]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][8]_srl32\ : label is "\U0/rgb_buffer_reg[1250][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1250][9]_srl32\ : label is "\U0/rgb_buffer_reg[1250] ";
attribute srl_name of \rgb_buffer_reg[1250][9]_srl32\ : label is "\U0/rgb_buffer_reg[1250][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][0]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][0]_srl29\ : label is "\U0/rgb_buffer_reg[1279][0]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][10]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][10]_srl29\ : label is "\U0/rgb_buffer_reg[1279][10]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][11]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][11]_srl29\ : label is "\U0/rgb_buffer_reg[1279][11]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][12]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][12]_srl29\ : label is "\U0/rgb_buffer_reg[1279][12]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][13]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][13]_srl29\ : label is "\U0/rgb_buffer_reg[1279][13]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][14]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][14]_srl29\ : label is "\U0/rgb_buffer_reg[1279][14]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][15]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][15]_srl29\ : label is "\U0/rgb_buffer_reg[1279][15]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][16]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][16]_srl29\ : label is "\U0/rgb_buffer_reg[1279][16]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][17]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][17]_srl29\ : label is "\U0/rgb_buffer_reg[1279][17]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][18]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][18]_srl29\ : label is "\U0/rgb_buffer_reg[1279][18]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][19]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][19]_srl29\ : label is "\U0/rgb_buffer_reg[1279][19]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][1]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][1]_srl29\ : label is "\U0/rgb_buffer_reg[1279][1]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][20]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][20]_srl29\ : label is "\U0/rgb_buffer_reg[1279][20]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][21]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][21]_srl29\ : label is "\U0/rgb_buffer_reg[1279][21]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][22]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][22]_srl29\ : label is "\U0/rgb_buffer_reg[1279][22]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][23]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][23]_srl29\ : label is "\U0/rgb_buffer_reg[1279][23]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][2]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][2]_srl29\ : label is "\U0/rgb_buffer_reg[1279][2]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][3]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][3]_srl29\ : label is "\U0/rgb_buffer_reg[1279][3]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][4]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][4]_srl29\ : label is "\U0/rgb_buffer_reg[1279][4]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][5]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][5]_srl29\ : label is "\U0/rgb_buffer_reg[1279][5]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][6]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][6]_srl29\ : label is "\U0/rgb_buffer_reg[1279][6]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][7]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][7]_srl29\ : label is "\U0/rgb_buffer_reg[1279][7]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][8]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][8]_srl29\ : label is "\U0/rgb_buffer_reg[1279][8]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[1279][9]_srl29\ : label is "\U0/rgb_buffer_reg[1279] ";
attribute srl_name of \rgb_buffer_reg[1279][9]_srl29\ : label is "\U0/rgb_buffer_reg[1279][9]_srl29 ";
attribute srl_bus_name of \rgb_buffer_reg[130][0]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][0]_srl32\ : label is "\U0/rgb_buffer_reg[130][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][10]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][10]_srl32\ : label is "\U0/rgb_buffer_reg[130][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][11]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][11]_srl32\ : label is "\U0/rgb_buffer_reg[130][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][12]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][12]_srl32\ : label is "\U0/rgb_buffer_reg[130][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][13]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][13]_srl32\ : label is "\U0/rgb_buffer_reg[130][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][14]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][14]_srl32\ : label is "\U0/rgb_buffer_reg[130][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][15]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][15]_srl32\ : label is "\U0/rgb_buffer_reg[130][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][16]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][16]_srl32\ : label is "\U0/rgb_buffer_reg[130][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][17]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][17]_srl32\ : label is "\U0/rgb_buffer_reg[130][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][18]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][18]_srl32\ : label is "\U0/rgb_buffer_reg[130][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][19]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][19]_srl32\ : label is "\U0/rgb_buffer_reg[130][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][1]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][1]_srl32\ : label is "\U0/rgb_buffer_reg[130][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][20]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][20]_srl32\ : label is "\U0/rgb_buffer_reg[130][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][21]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][21]_srl32\ : label is "\U0/rgb_buffer_reg[130][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][22]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][22]_srl32\ : label is "\U0/rgb_buffer_reg[130][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][23]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][23]_srl32\ : label is "\U0/rgb_buffer_reg[130][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][2]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][2]_srl32\ : label is "\U0/rgb_buffer_reg[130][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][3]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][3]_srl32\ : label is "\U0/rgb_buffer_reg[130][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][4]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][4]_srl32\ : label is "\U0/rgb_buffer_reg[130][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][5]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][5]_srl32\ : label is "\U0/rgb_buffer_reg[130][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][6]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][6]_srl32\ : label is "\U0/rgb_buffer_reg[130][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][7]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][7]_srl32\ : label is "\U0/rgb_buffer_reg[130][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][8]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][8]_srl32\ : label is "\U0/rgb_buffer_reg[130][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[130][9]_srl32\ : label is "\U0/rgb_buffer_reg[130] ";
attribute srl_name of \rgb_buffer_reg[130][9]_srl32\ : label is "\U0/rgb_buffer_reg[130][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][0]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][0]_srl32\ : label is "\U0/rgb_buffer_reg[162][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][10]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][10]_srl32\ : label is "\U0/rgb_buffer_reg[162][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][11]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][11]_srl32\ : label is "\U0/rgb_buffer_reg[162][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][12]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][12]_srl32\ : label is "\U0/rgb_buffer_reg[162][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][13]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][13]_srl32\ : label is "\U0/rgb_buffer_reg[162][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][14]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][14]_srl32\ : label is "\U0/rgb_buffer_reg[162][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][15]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][15]_srl32\ : label is "\U0/rgb_buffer_reg[162][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][16]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][16]_srl32\ : label is "\U0/rgb_buffer_reg[162][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][17]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][17]_srl32\ : label is "\U0/rgb_buffer_reg[162][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][18]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][18]_srl32\ : label is "\U0/rgb_buffer_reg[162][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][19]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][19]_srl32\ : label is "\U0/rgb_buffer_reg[162][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][1]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][1]_srl32\ : label is "\U0/rgb_buffer_reg[162][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][20]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][20]_srl32\ : label is "\U0/rgb_buffer_reg[162][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][21]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][21]_srl32\ : label is "\U0/rgb_buffer_reg[162][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][22]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][22]_srl32\ : label is "\U0/rgb_buffer_reg[162][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][23]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][23]_srl32\ : label is "\U0/rgb_buffer_reg[162][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][2]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][2]_srl32\ : label is "\U0/rgb_buffer_reg[162][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][3]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][3]_srl32\ : label is "\U0/rgb_buffer_reg[162][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][4]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][4]_srl32\ : label is "\U0/rgb_buffer_reg[162][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][5]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][5]_srl32\ : label is "\U0/rgb_buffer_reg[162][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][6]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][6]_srl32\ : label is "\U0/rgb_buffer_reg[162][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][7]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][7]_srl32\ : label is "\U0/rgb_buffer_reg[162][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][8]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][8]_srl32\ : label is "\U0/rgb_buffer_reg[162][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[162][9]_srl32\ : label is "\U0/rgb_buffer_reg[162] ";
attribute srl_name of \rgb_buffer_reg[162][9]_srl32\ : label is "\U0/rgb_buffer_reg[162][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][0]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][0]_srl32\ : label is "\U0/rgb_buffer_reg[194][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][10]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][10]_srl32\ : label is "\U0/rgb_buffer_reg[194][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][11]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][11]_srl32\ : label is "\U0/rgb_buffer_reg[194][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][12]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][12]_srl32\ : label is "\U0/rgb_buffer_reg[194][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][13]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][13]_srl32\ : label is "\U0/rgb_buffer_reg[194][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][14]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][14]_srl32\ : label is "\U0/rgb_buffer_reg[194][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][15]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][15]_srl32\ : label is "\U0/rgb_buffer_reg[194][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][16]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][16]_srl32\ : label is "\U0/rgb_buffer_reg[194][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][17]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][17]_srl32\ : label is "\U0/rgb_buffer_reg[194][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][18]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][18]_srl32\ : label is "\U0/rgb_buffer_reg[194][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][19]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][19]_srl32\ : label is "\U0/rgb_buffer_reg[194][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][1]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][1]_srl32\ : label is "\U0/rgb_buffer_reg[194][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][20]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][20]_srl32\ : label is "\U0/rgb_buffer_reg[194][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][21]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][21]_srl32\ : label is "\U0/rgb_buffer_reg[194][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][22]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][22]_srl32\ : label is "\U0/rgb_buffer_reg[194][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][23]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][23]_srl32\ : label is "\U0/rgb_buffer_reg[194][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][2]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][2]_srl32\ : label is "\U0/rgb_buffer_reg[194][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][3]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][3]_srl32\ : label is "\U0/rgb_buffer_reg[194][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][4]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][4]_srl32\ : label is "\U0/rgb_buffer_reg[194][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][5]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][5]_srl32\ : label is "\U0/rgb_buffer_reg[194][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][6]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][6]_srl32\ : label is "\U0/rgb_buffer_reg[194][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][7]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][7]_srl32\ : label is "\U0/rgb_buffer_reg[194][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][8]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][8]_srl32\ : label is "\U0/rgb_buffer_reg[194][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[194][9]_srl32\ : label is "\U0/rgb_buffer_reg[194] ";
attribute srl_name of \rgb_buffer_reg[194][9]_srl32\ : label is "\U0/rgb_buffer_reg[194][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][0]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][0]_srl32\ : label is "\U0/rgb_buffer_reg[226][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][10]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][10]_srl32\ : label is "\U0/rgb_buffer_reg[226][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][11]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][11]_srl32\ : label is "\U0/rgb_buffer_reg[226][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][12]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][12]_srl32\ : label is "\U0/rgb_buffer_reg[226][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][13]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][13]_srl32\ : label is "\U0/rgb_buffer_reg[226][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][14]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][14]_srl32\ : label is "\U0/rgb_buffer_reg[226][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][15]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][15]_srl32\ : label is "\U0/rgb_buffer_reg[226][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][16]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][16]_srl32\ : label is "\U0/rgb_buffer_reg[226][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][17]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][17]_srl32\ : label is "\U0/rgb_buffer_reg[226][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][18]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][18]_srl32\ : label is "\U0/rgb_buffer_reg[226][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][19]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][19]_srl32\ : label is "\U0/rgb_buffer_reg[226][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][1]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][1]_srl32\ : label is "\U0/rgb_buffer_reg[226][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][20]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][20]_srl32\ : label is "\U0/rgb_buffer_reg[226][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][21]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][21]_srl32\ : label is "\U0/rgb_buffer_reg[226][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][22]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][22]_srl32\ : label is "\U0/rgb_buffer_reg[226][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][23]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][23]_srl32\ : label is "\U0/rgb_buffer_reg[226][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][2]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][2]_srl32\ : label is "\U0/rgb_buffer_reg[226][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][3]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][3]_srl32\ : label is "\U0/rgb_buffer_reg[226][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][4]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][4]_srl32\ : label is "\U0/rgb_buffer_reg[226][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][5]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][5]_srl32\ : label is "\U0/rgb_buffer_reg[226][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][6]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][6]_srl32\ : label is "\U0/rgb_buffer_reg[226][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][7]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][7]_srl32\ : label is "\U0/rgb_buffer_reg[226][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][8]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][8]_srl32\ : label is "\U0/rgb_buffer_reg[226][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[226][9]_srl32\ : label is "\U0/rgb_buffer_reg[226] ";
attribute srl_name of \rgb_buffer_reg[226][9]_srl32\ : label is "\U0/rgb_buffer_reg[226][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][0]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][0]_srl32\ : label is "\U0/rgb_buffer_reg[258][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][10]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][10]_srl32\ : label is "\U0/rgb_buffer_reg[258][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][11]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][11]_srl32\ : label is "\U0/rgb_buffer_reg[258][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][12]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][12]_srl32\ : label is "\U0/rgb_buffer_reg[258][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][13]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][13]_srl32\ : label is "\U0/rgb_buffer_reg[258][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][14]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][14]_srl32\ : label is "\U0/rgb_buffer_reg[258][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][15]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][15]_srl32\ : label is "\U0/rgb_buffer_reg[258][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][16]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][16]_srl32\ : label is "\U0/rgb_buffer_reg[258][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][17]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][17]_srl32\ : label is "\U0/rgb_buffer_reg[258][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][18]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][18]_srl32\ : label is "\U0/rgb_buffer_reg[258][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][19]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][19]_srl32\ : label is "\U0/rgb_buffer_reg[258][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][1]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][1]_srl32\ : label is "\U0/rgb_buffer_reg[258][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][20]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][20]_srl32\ : label is "\U0/rgb_buffer_reg[258][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][21]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][21]_srl32\ : label is "\U0/rgb_buffer_reg[258][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][22]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][22]_srl32\ : label is "\U0/rgb_buffer_reg[258][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][23]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][23]_srl32\ : label is "\U0/rgb_buffer_reg[258][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][2]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][2]_srl32\ : label is "\U0/rgb_buffer_reg[258][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][3]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][3]_srl32\ : label is "\U0/rgb_buffer_reg[258][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][4]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][4]_srl32\ : label is "\U0/rgb_buffer_reg[258][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][5]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][5]_srl32\ : label is "\U0/rgb_buffer_reg[258][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][6]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][6]_srl32\ : label is "\U0/rgb_buffer_reg[258][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][7]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][7]_srl32\ : label is "\U0/rgb_buffer_reg[258][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][8]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][8]_srl32\ : label is "\U0/rgb_buffer_reg[258][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[258][9]_srl32\ : label is "\U0/rgb_buffer_reg[258] ";
attribute srl_name of \rgb_buffer_reg[258][9]_srl32\ : label is "\U0/rgb_buffer_reg[258][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][0]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][0]_srl32\ : label is "\U0/rgb_buffer_reg[290][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][10]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][10]_srl32\ : label is "\U0/rgb_buffer_reg[290][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][11]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][11]_srl32\ : label is "\U0/rgb_buffer_reg[290][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][12]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][12]_srl32\ : label is "\U0/rgb_buffer_reg[290][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][13]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][13]_srl32\ : label is "\U0/rgb_buffer_reg[290][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][14]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][14]_srl32\ : label is "\U0/rgb_buffer_reg[290][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][15]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][15]_srl32\ : label is "\U0/rgb_buffer_reg[290][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][16]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][16]_srl32\ : label is "\U0/rgb_buffer_reg[290][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][17]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][17]_srl32\ : label is "\U0/rgb_buffer_reg[290][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][18]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][18]_srl32\ : label is "\U0/rgb_buffer_reg[290][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][19]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][19]_srl32\ : label is "\U0/rgb_buffer_reg[290][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][1]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][1]_srl32\ : label is "\U0/rgb_buffer_reg[290][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][20]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][20]_srl32\ : label is "\U0/rgb_buffer_reg[290][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][21]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][21]_srl32\ : label is "\U0/rgb_buffer_reg[290][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][22]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][22]_srl32\ : label is "\U0/rgb_buffer_reg[290][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][23]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][23]_srl32\ : label is "\U0/rgb_buffer_reg[290][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][2]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][2]_srl32\ : label is "\U0/rgb_buffer_reg[290][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][3]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][3]_srl32\ : label is "\U0/rgb_buffer_reg[290][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][4]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][4]_srl32\ : label is "\U0/rgb_buffer_reg[290][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][5]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][5]_srl32\ : label is "\U0/rgb_buffer_reg[290][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][6]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][6]_srl32\ : label is "\U0/rgb_buffer_reg[290][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][7]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][7]_srl32\ : label is "\U0/rgb_buffer_reg[290][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][8]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][8]_srl32\ : label is "\U0/rgb_buffer_reg[290][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[290][9]_srl32\ : label is "\U0/rgb_buffer_reg[290] ";
attribute srl_name of \rgb_buffer_reg[290][9]_srl32\ : label is "\U0/rgb_buffer_reg[290][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][0]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][0]_srl32\ : label is "\U0/rgb_buffer_reg[322][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][10]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][10]_srl32\ : label is "\U0/rgb_buffer_reg[322][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][11]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][11]_srl32\ : label is "\U0/rgb_buffer_reg[322][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][12]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][12]_srl32\ : label is "\U0/rgb_buffer_reg[322][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][13]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][13]_srl32\ : label is "\U0/rgb_buffer_reg[322][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][14]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][14]_srl32\ : label is "\U0/rgb_buffer_reg[322][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][15]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][15]_srl32\ : label is "\U0/rgb_buffer_reg[322][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][16]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][16]_srl32\ : label is "\U0/rgb_buffer_reg[322][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][17]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][17]_srl32\ : label is "\U0/rgb_buffer_reg[322][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][18]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][18]_srl32\ : label is "\U0/rgb_buffer_reg[322][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][19]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][19]_srl32\ : label is "\U0/rgb_buffer_reg[322][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][1]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][1]_srl32\ : label is "\U0/rgb_buffer_reg[322][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][20]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][20]_srl32\ : label is "\U0/rgb_buffer_reg[322][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][21]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][21]_srl32\ : label is "\U0/rgb_buffer_reg[322][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][22]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][22]_srl32\ : label is "\U0/rgb_buffer_reg[322][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][23]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][23]_srl32\ : label is "\U0/rgb_buffer_reg[322][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][2]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][2]_srl32\ : label is "\U0/rgb_buffer_reg[322][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][3]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][3]_srl32\ : label is "\U0/rgb_buffer_reg[322][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][4]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][4]_srl32\ : label is "\U0/rgb_buffer_reg[322][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][5]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][5]_srl32\ : label is "\U0/rgb_buffer_reg[322][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][6]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][6]_srl32\ : label is "\U0/rgb_buffer_reg[322][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][7]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][7]_srl32\ : label is "\U0/rgb_buffer_reg[322][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][8]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][8]_srl32\ : label is "\U0/rgb_buffer_reg[322][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[322][9]_srl32\ : label is "\U0/rgb_buffer_reg[322] ";
attribute srl_name of \rgb_buffer_reg[322][9]_srl32\ : label is "\U0/rgb_buffer_reg[322][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][0]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][0]_srl32\ : label is "\U0/rgb_buffer_reg[34][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][10]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][10]_srl32\ : label is "\U0/rgb_buffer_reg[34][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][11]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][11]_srl32\ : label is "\U0/rgb_buffer_reg[34][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][12]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][12]_srl32\ : label is "\U0/rgb_buffer_reg[34][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][13]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][13]_srl32\ : label is "\U0/rgb_buffer_reg[34][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][14]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][14]_srl32\ : label is "\U0/rgb_buffer_reg[34][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][15]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][15]_srl32\ : label is "\U0/rgb_buffer_reg[34][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][16]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][16]_srl32\ : label is "\U0/rgb_buffer_reg[34][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][17]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][17]_srl32\ : label is "\U0/rgb_buffer_reg[34][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][18]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][18]_srl32\ : label is "\U0/rgb_buffer_reg[34][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][19]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][19]_srl32\ : label is "\U0/rgb_buffer_reg[34][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][1]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][1]_srl32\ : label is "\U0/rgb_buffer_reg[34][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][20]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][20]_srl32\ : label is "\U0/rgb_buffer_reg[34][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][21]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][21]_srl32\ : label is "\U0/rgb_buffer_reg[34][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][22]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][22]_srl32\ : label is "\U0/rgb_buffer_reg[34][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][23]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][23]_srl32\ : label is "\U0/rgb_buffer_reg[34][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][2]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][2]_srl32\ : label is "\U0/rgb_buffer_reg[34][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][3]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][3]_srl32\ : label is "\U0/rgb_buffer_reg[34][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][4]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][4]_srl32\ : label is "\U0/rgb_buffer_reg[34][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][5]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][5]_srl32\ : label is "\U0/rgb_buffer_reg[34][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][6]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][6]_srl32\ : label is "\U0/rgb_buffer_reg[34][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][7]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][7]_srl32\ : label is "\U0/rgb_buffer_reg[34][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][8]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][8]_srl32\ : label is "\U0/rgb_buffer_reg[34][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[34][9]_srl32\ : label is "\U0/rgb_buffer_reg[34] ";
attribute srl_name of \rgb_buffer_reg[34][9]_srl32\ : label is "\U0/rgb_buffer_reg[34][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][0]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][0]_srl32\ : label is "\U0/rgb_buffer_reg[354][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][10]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][10]_srl32\ : label is "\U0/rgb_buffer_reg[354][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][11]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][11]_srl32\ : label is "\U0/rgb_buffer_reg[354][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][12]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][12]_srl32\ : label is "\U0/rgb_buffer_reg[354][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][13]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][13]_srl32\ : label is "\U0/rgb_buffer_reg[354][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][14]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][14]_srl32\ : label is "\U0/rgb_buffer_reg[354][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][15]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][15]_srl32\ : label is "\U0/rgb_buffer_reg[354][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][16]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][16]_srl32\ : label is "\U0/rgb_buffer_reg[354][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][17]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][17]_srl32\ : label is "\U0/rgb_buffer_reg[354][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][18]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][18]_srl32\ : label is "\U0/rgb_buffer_reg[354][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][19]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][19]_srl32\ : label is "\U0/rgb_buffer_reg[354][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][1]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][1]_srl32\ : label is "\U0/rgb_buffer_reg[354][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][20]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][20]_srl32\ : label is "\U0/rgb_buffer_reg[354][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][21]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][21]_srl32\ : label is "\U0/rgb_buffer_reg[354][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][22]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][22]_srl32\ : label is "\U0/rgb_buffer_reg[354][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][23]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][23]_srl32\ : label is "\U0/rgb_buffer_reg[354][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][2]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][2]_srl32\ : label is "\U0/rgb_buffer_reg[354][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][3]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][3]_srl32\ : label is "\U0/rgb_buffer_reg[354][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][4]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][4]_srl32\ : label is "\U0/rgb_buffer_reg[354][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][5]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][5]_srl32\ : label is "\U0/rgb_buffer_reg[354][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][6]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][6]_srl32\ : label is "\U0/rgb_buffer_reg[354][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][7]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][7]_srl32\ : label is "\U0/rgb_buffer_reg[354][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][8]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][8]_srl32\ : label is "\U0/rgb_buffer_reg[354][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[354][9]_srl32\ : label is "\U0/rgb_buffer_reg[354] ";
attribute srl_name of \rgb_buffer_reg[354][9]_srl32\ : label is "\U0/rgb_buffer_reg[354][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][0]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][0]_srl32\ : label is "\U0/rgb_buffer_reg[386][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][10]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][10]_srl32\ : label is "\U0/rgb_buffer_reg[386][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][11]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][11]_srl32\ : label is "\U0/rgb_buffer_reg[386][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][12]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][12]_srl32\ : label is "\U0/rgb_buffer_reg[386][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][13]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][13]_srl32\ : label is "\U0/rgb_buffer_reg[386][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][14]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][14]_srl32\ : label is "\U0/rgb_buffer_reg[386][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][15]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][15]_srl32\ : label is "\U0/rgb_buffer_reg[386][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][16]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][16]_srl32\ : label is "\U0/rgb_buffer_reg[386][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][17]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][17]_srl32\ : label is "\U0/rgb_buffer_reg[386][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][18]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][18]_srl32\ : label is "\U0/rgb_buffer_reg[386][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][19]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][19]_srl32\ : label is "\U0/rgb_buffer_reg[386][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][1]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][1]_srl32\ : label is "\U0/rgb_buffer_reg[386][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][20]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][20]_srl32\ : label is "\U0/rgb_buffer_reg[386][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][21]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][21]_srl32\ : label is "\U0/rgb_buffer_reg[386][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][22]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][22]_srl32\ : label is "\U0/rgb_buffer_reg[386][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][23]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][23]_srl32\ : label is "\U0/rgb_buffer_reg[386][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][2]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][2]_srl32\ : label is "\U0/rgb_buffer_reg[386][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][3]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][3]_srl32\ : label is "\U0/rgb_buffer_reg[386][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][4]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][4]_srl32\ : label is "\U0/rgb_buffer_reg[386][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][5]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][5]_srl32\ : label is "\U0/rgb_buffer_reg[386][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][6]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][6]_srl32\ : label is "\U0/rgb_buffer_reg[386][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][7]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][7]_srl32\ : label is "\U0/rgb_buffer_reg[386][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][8]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][8]_srl32\ : label is "\U0/rgb_buffer_reg[386][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[386][9]_srl32\ : label is "\U0/rgb_buffer_reg[386] ";
attribute srl_name of \rgb_buffer_reg[386][9]_srl32\ : label is "\U0/rgb_buffer_reg[386][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][0]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][0]_srl32\ : label is "\U0/rgb_buffer_reg[418][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][10]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][10]_srl32\ : label is "\U0/rgb_buffer_reg[418][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][11]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][11]_srl32\ : label is "\U0/rgb_buffer_reg[418][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][12]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][12]_srl32\ : label is "\U0/rgb_buffer_reg[418][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][13]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][13]_srl32\ : label is "\U0/rgb_buffer_reg[418][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][14]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][14]_srl32\ : label is "\U0/rgb_buffer_reg[418][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][15]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][15]_srl32\ : label is "\U0/rgb_buffer_reg[418][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][16]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][16]_srl32\ : label is "\U0/rgb_buffer_reg[418][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][17]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][17]_srl32\ : label is "\U0/rgb_buffer_reg[418][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][18]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][18]_srl32\ : label is "\U0/rgb_buffer_reg[418][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][19]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][19]_srl32\ : label is "\U0/rgb_buffer_reg[418][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][1]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][1]_srl32\ : label is "\U0/rgb_buffer_reg[418][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][20]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][20]_srl32\ : label is "\U0/rgb_buffer_reg[418][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][21]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][21]_srl32\ : label is "\U0/rgb_buffer_reg[418][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][22]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][22]_srl32\ : label is "\U0/rgb_buffer_reg[418][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][23]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][23]_srl32\ : label is "\U0/rgb_buffer_reg[418][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][2]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][2]_srl32\ : label is "\U0/rgb_buffer_reg[418][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][3]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][3]_srl32\ : label is "\U0/rgb_buffer_reg[418][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][4]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][4]_srl32\ : label is "\U0/rgb_buffer_reg[418][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][5]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][5]_srl32\ : label is "\U0/rgb_buffer_reg[418][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][6]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][6]_srl32\ : label is "\U0/rgb_buffer_reg[418][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][7]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][7]_srl32\ : label is "\U0/rgb_buffer_reg[418][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][8]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][8]_srl32\ : label is "\U0/rgb_buffer_reg[418][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[418][9]_srl32\ : label is "\U0/rgb_buffer_reg[418] ";
attribute srl_name of \rgb_buffer_reg[418][9]_srl32\ : label is "\U0/rgb_buffer_reg[418][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][0]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][0]_srl32\ : label is "\U0/rgb_buffer_reg[450][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][10]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][10]_srl32\ : label is "\U0/rgb_buffer_reg[450][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][11]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][11]_srl32\ : label is "\U0/rgb_buffer_reg[450][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][12]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][12]_srl32\ : label is "\U0/rgb_buffer_reg[450][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][13]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][13]_srl32\ : label is "\U0/rgb_buffer_reg[450][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][14]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][14]_srl32\ : label is "\U0/rgb_buffer_reg[450][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][15]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][15]_srl32\ : label is "\U0/rgb_buffer_reg[450][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][16]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][16]_srl32\ : label is "\U0/rgb_buffer_reg[450][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][17]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][17]_srl32\ : label is "\U0/rgb_buffer_reg[450][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][18]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][18]_srl32\ : label is "\U0/rgb_buffer_reg[450][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][19]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][19]_srl32\ : label is "\U0/rgb_buffer_reg[450][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][1]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][1]_srl32\ : label is "\U0/rgb_buffer_reg[450][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][20]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][20]_srl32\ : label is "\U0/rgb_buffer_reg[450][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][21]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][21]_srl32\ : label is "\U0/rgb_buffer_reg[450][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][22]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][22]_srl32\ : label is "\U0/rgb_buffer_reg[450][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][23]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][23]_srl32\ : label is "\U0/rgb_buffer_reg[450][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][2]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][2]_srl32\ : label is "\U0/rgb_buffer_reg[450][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][3]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][3]_srl32\ : label is "\U0/rgb_buffer_reg[450][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][4]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][4]_srl32\ : label is "\U0/rgb_buffer_reg[450][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][5]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][5]_srl32\ : label is "\U0/rgb_buffer_reg[450][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][6]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][6]_srl32\ : label is "\U0/rgb_buffer_reg[450][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][7]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][7]_srl32\ : label is "\U0/rgb_buffer_reg[450][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][8]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][8]_srl32\ : label is "\U0/rgb_buffer_reg[450][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[450][9]_srl32\ : label is "\U0/rgb_buffer_reg[450] ";
attribute srl_name of \rgb_buffer_reg[450][9]_srl32\ : label is "\U0/rgb_buffer_reg[450][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][0]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][0]_srl32\ : label is "\U0/rgb_buffer_reg[482][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][10]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][10]_srl32\ : label is "\U0/rgb_buffer_reg[482][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][11]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][11]_srl32\ : label is "\U0/rgb_buffer_reg[482][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][12]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][12]_srl32\ : label is "\U0/rgb_buffer_reg[482][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][13]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][13]_srl32\ : label is "\U0/rgb_buffer_reg[482][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][14]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][14]_srl32\ : label is "\U0/rgb_buffer_reg[482][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][15]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][15]_srl32\ : label is "\U0/rgb_buffer_reg[482][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][16]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][16]_srl32\ : label is "\U0/rgb_buffer_reg[482][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][17]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][17]_srl32\ : label is "\U0/rgb_buffer_reg[482][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][18]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][18]_srl32\ : label is "\U0/rgb_buffer_reg[482][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][19]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][19]_srl32\ : label is "\U0/rgb_buffer_reg[482][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][1]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][1]_srl32\ : label is "\U0/rgb_buffer_reg[482][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][20]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][20]_srl32\ : label is "\U0/rgb_buffer_reg[482][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][21]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][21]_srl32\ : label is "\U0/rgb_buffer_reg[482][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][22]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][22]_srl32\ : label is "\U0/rgb_buffer_reg[482][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][23]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][23]_srl32\ : label is "\U0/rgb_buffer_reg[482][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][2]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][2]_srl32\ : label is "\U0/rgb_buffer_reg[482][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][3]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][3]_srl32\ : label is "\U0/rgb_buffer_reg[482][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][4]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][4]_srl32\ : label is "\U0/rgb_buffer_reg[482][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][5]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][5]_srl32\ : label is "\U0/rgb_buffer_reg[482][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][6]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][6]_srl32\ : label is "\U0/rgb_buffer_reg[482][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][7]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][7]_srl32\ : label is "\U0/rgb_buffer_reg[482][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][8]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][8]_srl32\ : label is "\U0/rgb_buffer_reg[482][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[482][9]_srl32\ : label is "\U0/rgb_buffer_reg[482] ";
attribute srl_name of \rgb_buffer_reg[482][9]_srl32\ : label is "\U0/rgb_buffer_reg[482][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][0]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][0]_srl32\ : label is "\U0/rgb_buffer_reg[514][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][10]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][10]_srl32\ : label is "\U0/rgb_buffer_reg[514][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][11]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][11]_srl32\ : label is "\U0/rgb_buffer_reg[514][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][12]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][12]_srl32\ : label is "\U0/rgb_buffer_reg[514][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][13]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][13]_srl32\ : label is "\U0/rgb_buffer_reg[514][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][14]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][14]_srl32\ : label is "\U0/rgb_buffer_reg[514][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][15]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][15]_srl32\ : label is "\U0/rgb_buffer_reg[514][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][16]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][16]_srl32\ : label is "\U0/rgb_buffer_reg[514][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][17]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][17]_srl32\ : label is "\U0/rgb_buffer_reg[514][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][18]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][18]_srl32\ : label is "\U0/rgb_buffer_reg[514][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][19]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][19]_srl32\ : label is "\U0/rgb_buffer_reg[514][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][1]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][1]_srl32\ : label is "\U0/rgb_buffer_reg[514][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][20]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][20]_srl32\ : label is "\U0/rgb_buffer_reg[514][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][21]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][21]_srl32\ : label is "\U0/rgb_buffer_reg[514][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][22]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][22]_srl32\ : label is "\U0/rgb_buffer_reg[514][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][23]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][23]_srl32\ : label is "\U0/rgb_buffer_reg[514][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][2]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][2]_srl32\ : label is "\U0/rgb_buffer_reg[514][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][3]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][3]_srl32\ : label is "\U0/rgb_buffer_reg[514][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][4]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][4]_srl32\ : label is "\U0/rgb_buffer_reg[514][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][5]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][5]_srl32\ : label is "\U0/rgb_buffer_reg[514][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][6]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][6]_srl32\ : label is "\U0/rgb_buffer_reg[514][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][7]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][7]_srl32\ : label is "\U0/rgb_buffer_reg[514][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][8]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][8]_srl32\ : label is "\U0/rgb_buffer_reg[514][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[514][9]_srl32\ : label is "\U0/rgb_buffer_reg[514] ";
attribute srl_name of \rgb_buffer_reg[514][9]_srl32\ : label is "\U0/rgb_buffer_reg[514][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][0]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][0]_srl32\ : label is "\U0/rgb_buffer_reg[546][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][10]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][10]_srl32\ : label is "\U0/rgb_buffer_reg[546][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][11]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][11]_srl32\ : label is "\U0/rgb_buffer_reg[546][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][12]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][12]_srl32\ : label is "\U0/rgb_buffer_reg[546][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][13]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][13]_srl32\ : label is "\U0/rgb_buffer_reg[546][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][14]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][14]_srl32\ : label is "\U0/rgb_buffer_reg[546][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][15]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][15]_srl32\ : label is "\U0/rgb_buffer_reg[546][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][16]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][16]_srl32\ : label is "\U0/rgb_buffer_reg[546][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][17]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][17]_srl32\ : label is "\U0/rgb_buffer_reg[546][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][18]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][18]_srl32\ : label is "\U0/rgb_buffer_reg[546][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][19]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][19]_srl32\ : label is "\U0/rgb_buffer_reg[546][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][1]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][1]_srl32\ : label is "\U0/rgb_buffer_reg[546][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][20]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][20]_srl32\ : label is "\U0/rgb_buffer_reg[546][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][21]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][21]_srl32\ : label is "\U0/rgb_buffer_reg[546][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][22]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][22]_srl32\ : label is "\U0/rgb_buffer_reg[546][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][23]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][23]_srl32\ : label is "\U0/rgb_buffer_reg[546][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][2]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][2]_srl32\ : label is "\U0/rgb_buffer_reg[546][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][3]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][3]_srl32\ : label is "\U0/rgb_buffer_reg[546][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][4]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][4]_srl32\ : label is "\U0/rgb_buffer_reg[546][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][5]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][5]_srl32\ : label is "\U0/rgb_buffer_reg[546][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][6]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][6]_srl32\ : label is "\U0/rgb_buffer_reg[546][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][7]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][7]_srl32\ : label is "\U0/rgb_buffer_reg[546][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][8]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][8]_srl32\ : label is "\U0/rgb_buffer_reg[546][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[546][9]_srl32\ : label is "\U0/rgb_buffer_reg[546] ";
attribute srl_name of \rgb_buffer_reg[546][9]_srl32\ : label is "\U0/rgb_buffer_reg[546][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][0]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][0]_srl32\ : label is "\U0/rgb_buffer_reg[578][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][10]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][10]_srl32\ : label is "\U0/rgb_buffer_reg[578][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][11]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][11]_srl32\ : label is "\U0/rgb_buffer_reg[578][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][12]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][12]_srl32\ : label is "\U0/rgb_buffer_reg[578][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][13]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][13]_srl32\ : label is "\U0/rgb_buffer_reg[578][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][14]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][14]_srl32\ : label is "\U0/rgb_buffer_reg[578][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][15]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][15]_srl32\ : label is "\U0/rgb_buffer_reg[578][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][16]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][16]_srl32\ : label is "\U0/rgb_buffer_reg[578][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][17]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][17]_srl32\ : label is "\U0/rgb_buffer_reg[578][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][18]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][18]_srl32\ : label is "\U0/rgb_buffer_reg[578][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][19]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][19]_srl32\ : label is "\U0/rgb_buffer_reg[578][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][1]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][1]_srl32\ : label is "\U0/rgb_buffer_reg[578][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][20]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][20]_srl32\ : label is "\U0/rgb_buffer_reg[578][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][21]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][21]_srl32\ : label is "\U0/rgb_buffer_reg[578][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][22]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][22]_srl32\ : label is "\U0/rgb_buffer_reg[578][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][23]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][23]_srl32\ : label is "\U0/rgb_buffer_reg[578][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][2]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][2]_srl32\ : label is "\U0/rgb_buffer_reg[578][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][3]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][3]_srl32\ : label is "\U0/rgb_buffer_reg[578][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][4]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][4]_srl32\ : label is "\U0/rgb_buffer_reg[578][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][5]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][5]_srl32\ : label is "\U0/rgb_buffer_reg[578][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][6]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][6]_srl32\ : label is "\U0/rgb_buffer_reg[578][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][7]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][7]_srl32\ : label is "\U0/rgb_buffer_reg[578][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][8]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][8]_srl32\ : label is "\U0/rgb_buffer_reg[578][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[578][9]_srl32\ : label is "\U0/rgb_buffer_reg[578] ";
attribute srl_name of \rgb_buffer_reg[578][9]_srl32\ : label is "\U0/rgb_buffer_reg[578][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][0]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][0]_srl32\ : label is "\U0/rgb_buffer_reg[610][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][10]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][10]_srl32\ : label is "\U0/rgb_buffer_reg[610][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][11]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][11]_srl32\ : label is "\U0/rgb_buffer_reg[610][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][12]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][12]_srl32\ : label is "\U0/rgb_buffer_reg[610][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][13]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][13]_srl32\ : label is "\U0/rgb_buffer_reg[610][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][14]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][14]_srl32\ : label is "\U0/rgb_buffer_reg[610][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][15]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][15]_srl32\ : label is "\U0/rgb_buffer_reg[610][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][16]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][16]_srl32\ : label is "\U0/rgb_buffer_reg[610][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][17]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][17]_srl32\ : label is "\U0/rgb_buffer_reg[610][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][18]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][18]_srl32\ : label is "\U0/rgb_buffer_reg[610][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][19]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][19]_srl32\ : label is "\U0/rgb_buffer_reg[610][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][1]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][1]_srl32\ : label is "\U0/rgb_buffer_reg[610][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][20]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][20]_srl32\ : label is "\U0/rgb_buffer_reg[610][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][21]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][21]_srl32\ : label is "\U0/rgb_buffer_reg[610][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][22]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][22]_srl32\ : label is "\U0/rgb_buffer_reg[610][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][23]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][23]_srl32\ : label is "\U0/rgb_buffer_reg[610][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][2]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][2]_srl32\ : label is "\U0/rgb_buffer_reg[610][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][3]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][3]_srl32\ : label is "\U0/rgb_buffer_reg[610][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][4]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][4]_srl32\ : label is "\U0/rgb_buffer_reg[610][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][5]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][5]_srl32\ : label is "\U0/rgb_buffer_reg[610][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][6]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][6]_srl32\ : label is "\U0/rgb_buffer_reg[610][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][7]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][7]_srl32\ : label is "\U0/rgb_buffer_reg[610][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][8]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][8]_srl32\ : label is "\U0/rgb_buffer_reg[610][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[610][9]_srl32\ : label is "\U0/rgb_buffer_reg[610] ";
attribute srl_name of \rgb_buffer_reg[610][9]_srl32\ : label is "\U0/rgb_buffer_reg[610][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][0]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][0]_srl32\ : label is "\U0/rgb_buffer_reg[66][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][10]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][10]_srl32\ : label is "\U0/rgb_buffer_reg[66][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][11]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][11]_srl32\ : label is "\U0/rgb_buffer_reg[66][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][12]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][12]_srl32\ : label is "\U0/rgb_buffer_reg[66][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][13]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][13]_srl32\ : label is "\U0/rgb_buffer_reg[66][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][14]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][14]_srl32\ : label is "\U0/rgb_buffer_reg[66][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][15]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][15]_srl32\ : label is "\U0/rgb_buffer_reg[66][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][16]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][16]_srl32\ : label is "\U0/rgb_buffer_reg[66][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][17]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][17]_srl32\ : label is "\U0/rgb_buffer_reg[66][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][18]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][18]_srl32\ : label is "\U0/rgb_buffer_reg[66][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][19]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][19]_srl32\ : label is "\U0/rgb_buffer_reg[66][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][1]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][1]_srl32\ : label is "\U0/rgb_buffer_reg[66][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][20]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][20]_srl32\ : label is "\U0/rgb_buffer_reg[66][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][21]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][21]_srl32\ : label is "\U0/rgb_buffer_reg[66][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][22]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][22]_srl32\ : label is "\U0/rgb_buffer_reg[66][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][23]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][23]_srl32\ : label is "\U0/rgb_buffer_reg[66][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][2]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][2]_srl32\ : label is "\U0/rgb_buffer_reg[66][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][3]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][3]_srl32\ : label is "\U0/rgb_buffer_reg[66][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][4]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][4]_srl32\ : label is "\U0/rgb_buffer_reg[66][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][5]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][5]_srl32\ : label is "\U0/rgb_buffer_reg[66][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][6]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][6]_srl32\ : label is "\U0/rgb_buffer_reg[66][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][7]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][7]_srl32\ : label is "\U0/rgb_buffer_reg[66][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][8]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][8]_srl32\ : label is "\U0/rgb_buffer_reg[66][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[66][9]_srl32\ : label is "\U0/rgb_buffer_reg[66] ";
attribute srl_name of \rgb_buffer_reg[66][9]_srl32\ : label is "\U0/rgb_buffer_reg[66][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][0]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][0]_srl32\ : label is "\U0/rgb_buffer_reg[674][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][10]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][10]_srl32\ : label is "\U0/rgb_buffer_reg[674][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][11]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][11]_srl32\ : label is "\U0/rgb_buffer_reg[674][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][12]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][12]_srl32\ : label is "\U0/rgb_buffer_reg[674][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][13]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][13]_srl32\ : label is "\U0/rgb_buffer_reg[674][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][14]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][14]_srl32\ : label is "\U0/rgb_buffer_reg[674][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][15]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][15]_srl32\ : label is "\U0/rgb_buffer_reg[674][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][16]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][16]_srl32\ : label is "\U0/rgb_buffer_reg[674][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][17]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][17]_srl32\ : label is "\U0/rgb_buffer_reg[674][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][18]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][18]_srl32\ : label is "\U0/rgb_buffer_reg[674][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][19]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][19]_srl32\ : label is "\U0/rgb_buffer_reg[674][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][1]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][1]_srl32\ : label is "\U0/rgb_buffer_reg[674][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][20]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][20]_srl32\ : label is "\U0/rgb_buffer_reg[674][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][21]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][21]_srl32\ : label is "\U0/rgb_buffer_reg[674][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][22]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][22]_srl32\ : label is "\U0/rgb_buffer_reg[674][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][23]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][23]_srl32\ : label is "\U0/rgb_buffer_reg[674][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][2]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][2]_srl32\ : label is "\U0/rgb_buffer_reg[674][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][3]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][3]_srl32\ : label is "\U0/rgb_buffer_reg[674][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][4]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][4]_srl32\ : label is "\U0/rgb_buffer_reg[674][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][5]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][5]_srl32\ : label is "\U0/rgb_buffer_reg[674][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][6]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][6]_srl32\ : label is "\U0/rgb_buffer_reg[674][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][7]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][7]_srl32\ : label is "\U0/rgb_buffer_reg[674][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][8]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][8]_srl32\ : label is "\U0/rgb_buffer_reg[674][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[674][9]_srl32\ : label is "\U0/rgb_buffer_reg[674] ";
attribute srl_name of \rgb_buffer_reg[674][9]_srl32\ : label is "\U0/rgb_buffer_reg[674][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][0]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][0]_srl32\ : label is "\U0/rgb_buffer_reg[706][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][10]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][10]_srl32\ : label is "\U0/rgb_buffer_reg[706][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][11]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][11]_srl32\ : label is "\U0/rgb_buffer_reg[706][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][12]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][12]_srl32\ : label is "\U0/rgb_buffer_reg[706][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][13]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][13]_srl32\ : label is "\U0/rgb_buffer_reg[706][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][14]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][14]_srl32\ : label is "\U0/rgb_buffer_reg[706][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][15]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][15]_srl32\ : label is "\U0/rgb_buffer_reg[706][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][16]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][16]_srl32\ : label is "\U0/rgb_buffer_reg[706][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][17]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][17]_srl32\ : label is "\U0/rgb_buffer_reg[706][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][18]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][18]_srl32\ : label is "\U0/rgb_buffer_reg[706][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][19]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][19]_srl32\ : label is "\U0/rgb_buffer_reg[706][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][1]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][1]_srl32\ : label is "\U0/rgb_buffer_reg[706][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][20]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][20]_srl32\ : label is "\U0/rgb_buffer_reg[706][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][21]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][21]_srl32\ : label is "\U0/rgb_buffer_reg[706][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][22]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][22]_srl32\ : label is "\U0/rgb_buffer_reg[706][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][23]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][23]_srl32\ : label is "\U0/rgb_buffer_reg[706][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][2]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][2]_srl32\ : label is "\U0/rgb_buffer_reg[706][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][3]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][3]_srl32\ : label is "\U0/rgb_buffer_reg[706][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][4]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][4]_srl32\ : label is "\U0/rgb_buffer_reg[706][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][5]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][5]_srl32\ : label is "\U0/rgb_buffer_reg[706][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][6]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][6]_srl32\ : label is "\U0/rgb_buffer_reg[706][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][7]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][7]_srl32\ : label is "\U0/rgb_buffer_reg[706][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][8]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][8]_srl32\ : label is "\U0/rgb_buffer_reg[706][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[706][9]_srl32\ : label is "\U0/rgb_buffer_reg[706] ";
attribute srl_name of \rgb_buffer_reg[706][9]_srl32\ : label is "\U0/rgb_buffer_reg[706][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][0]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][0]_srl32\ : label is "\U0/rgb_buffer_reg[738][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][10]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][10]_srl32\ : label is "\U0/rgb_buffer_reg[738][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][11]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][11]_srl32\ : label is "\U0/rgb_buffer_reg[738][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][12]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][12]_srl32\ : label is "\U0/rgb_buffer_reg[738][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][13]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][13]_srl32\ : label is "\U0/rgb_buffer_reg[738][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][14]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][14]_srl32\ : label is "\U0/rgb_buffer_reg[738][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][15]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][15]_srl32\ : label is "\U0/rgb_buffer_reg[738][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][16]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][16]_srl32\ : label is "\U0/rgb_buffer_reg[738][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][17]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][17]_srl32\ : label is "\U0/rgb_buffer_reg[738][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][18]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][18]_srl32\ : label is "\U0/rgb_buffer_reg[738][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][19]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][19]_srl32\ : label is "\U0/rgb_buffer_reg[738][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][1]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][1]_srl32\ : label is "\U0/rgb_buffer_reg[738][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][20]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][20]_srl32\ : label is "\U0/rgb_buffer_reg[738][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][21]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][21]_srl32\ : label is "\U0/rgb_buffer_reg[738][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][22]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][22]_srl32\ : label is "\U0/rgb_buffer_reg[738][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][23]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][23]_srl32\ : label is "\U0/rgb_buffer_reg[738][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][2]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][2]_srl32\ : label is "\U0/rgb_buffer_reg[738][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][3]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][3]_srl32\ : label is "\U0/rgb_buffer_reg[738][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][4]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][4]_srl32\ : label is "\U0/rgb_buffer_reg[738][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][5]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][5]_srl32\ : label is "\U0/rgb_buffer_reg[738][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][6]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][6]_srl32\ : label is "\U0/rgb_buffer_reg[738][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][7]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][7]_srl32\ : label is "\U0/rgb_buffer_reg[738][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][8]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][8]_srl32\ : label is "\U0/rgb_buffer_reg[738][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[738][9]_srl32\ : label is "\U0/rgb_buffer_reg[738] ";
attribute srl_name of \rgb_buffer_reg[738][9]_srl32\ : label is "\U0/rgb_buffer_reg[738][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][0]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][0]_srl32\ : label is "\U0/rgb_buffer_reg[770][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][10]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][10]_srl32\ : label is "\U0/rgb_buffer_reg[770][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][11]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][11]_srl32\ : label is "\U0/rgb_buffer_reg[770][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][12]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][12]_srl32\ : label is "\U0/rgb_buffer_reg[770][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][13]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][13]_srl32\ : label is "\U0/rgb_buffer_reg[770][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][14]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][14]_srl32\ : label is "\U0/rgb_buffer_reg[770][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][15]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][15]_srl32\ : label is "\U0/rgb_buffer_reg[770][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][16]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][16]_srl32\ : label is "\U0/rgb_buffer_reg[770][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][17]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][17]_srl32\ : label is "\U0/rgb_buffer_reg[770][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][18]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][18]_srl32\ : label is "\U0/rgb_buffer_reg[770][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][19]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][19]_srl32\ : label is "\U0/rgb_buffer_reg[770][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][1]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][1]_srl32\ : label is "\U0/rgb_buffer_reg[770][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][20]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][20]_srl32\ : label is "\U0/rgb_buffer_reg[770][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][21]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][21]_srl32\ : label is "\U0/rgb_buffer_reg[770][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][22]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][22]_srl32\ : label is "\U0/rgb_buffer_reg[770][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][23]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][23]_srl32\ : label is "\U0/rgb_buffer_reg[770][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][2]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][2]_srl32\ : label is "\U0/rgb_buffer_reg[770][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][3]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][3]_srl32\ : label is "\U0/rgb_buffer_reg[770][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][4]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][4]_srl32\ : label is "\U0/rgb_buffer_reg[770][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][5]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][5]_srl32\ : label is "\U0/rgb_buffer_reg[770][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][6]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][6]_srl32\ : label is "\U0/rgb_buffer_reg[770][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][7]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][7]_srl32\ : label is "\U0/rgb_buffer_reg[770][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][8]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][8]_srl32\ : label is "\U0/rgb_buffer_reg[770][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[770][9]_srl32\ : label is "\U0/rgb_buffer_reg[770] ";
attribute srl_name of \rgb_buffer_reg[770][9]_srl32\ : label is "\U0/rgb_buffer_reg[770][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][0]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][0]_srl32\ : label is "\U0/rgb_buffer_reg[802][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][10]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][10]_srl32\ : label is "\U0/rgb_buffer_reg[802][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][11]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][11]_srl32\ : label is "\U0/rgb_buffer_reg[802][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][12]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][12]_srl32\ : label is "\U0/rgb_buffer_reg[802][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][13]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][13]_srl32\ : label is "\U0/rgb_buffer_reg[802][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][14]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][14]_srl32\ : label is "\U0/rgb_buffer_reg[802][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][15]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][15]_srl32\ : label is "\U0/rgb_buffer_reg[802][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][16]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][16]_srl32\ : label is "\U0/rgb_buffer_reg[802][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][17]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][17]_srl32\ : label is "\U0/rgb_buffer_reg[802][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][18]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][18]_srl32\ : label is "\U0/rgb_buffer_reg[802][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][19]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][19]_srl32\ : label is "\U0/rgb_buffer_reg[802][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][1]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][1]_srl32\ : label is "\U0/rgb_buffer_reg[802][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][20]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][20]_srl32\ : label is "\U0/rgb_buffer_reg[802][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][21]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][21]_srl32\ : label is "\U0/rgb_buffer_reg[802][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][22]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][22]_srl32\ : label is "\U0/rgb_buffer_reg[802][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][23]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][23]_srl32\ : label is "\U0/rgb_buffer_reg[802][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][2]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][2]_srl32\ : label is "\U0/rgb_buffer_reg[802][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][3]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][3]_srl32\ : label is "\U0/rgb_buffer_reg[802][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][4]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][4]_srl32\ : label is "\U0/rgb_buffer_reg[802][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][5]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][5]_srl32\ : label is "\U0/rgb_buffer_reg[802][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][6]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][6]_srl32\ : label is "\U0/rgb_buffer_reg[802][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][7]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][7]_srl32\ : label is "\U0/rgb_buffer_reg[802][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][8]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][8]_srl32\ : label is "\U0/rgb_buffer_reg[802][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[802][9]_srl32\ : label is "\U0/rgb_buffer_reg[802] ";
attribute srl_name of \rgb_buffer_reg[802][9]_srl32\ : label is "\U0/rgb_buffer_reg[802][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][0]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][0]_srl32\ : label is "\U0/rgb_buffer_reg[834][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][10]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][10]_srl32\ : label is "\U0/rgb_buffer_reg[834][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][11]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][11]_srl32\ : label is "\U0/rgb_buffer_reg[834][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][12]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][12]_srl32\ : label is "\U0/rgb_buffer_reg[834][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][13]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][13]_srl32\ : label is "\U0/rgb_buffer_reg[834][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][14]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][14]_srl32\ : label is "\U0/rgb_buffer_reg[834][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][15]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][15]_srl32\ : label is "\U0/rgb_buffer_reg[834][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][16]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][16]_srl32\ : label is "\U0/rgb_buffer_reg[834][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][17]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][17]_srl32\ : label is "\U0/rgb_buffer_reg[834][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][18]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][18]_srl32\ : label is "\U0/rgb_buffer_reg[834][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][19]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][19]_srl32\ : label is "\U0/rgb_buffer_reg[834][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][1]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][1]_srl32\ : label is "\U0/rgb_buffer_reg[834][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][20]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][20]_srl32\ : label is "\U0/rgb_buffer_reg[834][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][21]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][21]_srl32\ : label is "\U0/rgb_buffer_reg[834][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][22]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][22]_srl32\ : label is "\U0/rgb_buffer_reg[834][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][23]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][23]_srl32\ : label is "\U0/rgb_buffer_reg[834][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][2]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][2]_srl32\ : label is "\U0/rgb_buffer_reg[834][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][3]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][3]_srl32\ : label is "\U0/rgb_buffer_reg[834][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][4]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][4]_srl32\ : label is "\U0/rgb_buffer_reg[834][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][5]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][5]_srl32\ : label is "\U0/rgb_buffer_reg[834][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][6]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][6]_srl32\ : label is "\U0/rgb_buffer_reg[834][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][7]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][7]_srl32\ : label is "\U0/rgb_buffer_reg[834][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][8]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][8]_srl32\ : label is "\U0/rgb_buffer_reg[834][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[834][9]_srl32\ : label is "\U0/rgb_buffer_reg[834] ";
attribute srl_name of \rgb_buffer_reg[834][9]_srl32\ : label is "\U0/rgb_buffer_reg[834][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][0]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][0]_srl32\ : label is "\U0/rgb_buffer_reg[866][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][10]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][10]_srl32\ : label is "\U0/rgb_buffer_reg[866][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][11]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][11]_srl32\ : label is "\U0/rgb_buffer_reg[866][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][12]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][12]_srl32\ : label is "\U0/rgb_buffer_reg[866][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][13]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][13]_srl32\ : label is "\U0/rgb_buffer_reg[866][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][14]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][14]_srl32\ : label is "\U0/rgb_buffer_reg[866][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][15]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][15]_srl32\ : label is "\U0/rgb_buffer_reg[866][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][16]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][16]_srl32\ : label is "\U0/rgb_buffer_reg[866][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][17]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][17]_srl32\ : label is "\U0/rgb_buffer_reg[866][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][18]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][18]_srl32\ : label is "\U0/rgb_buffer_reg[866][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][19]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][19]_srl32\ : label is "\U0/rgb_buffer_reg[866][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][1]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][1]_srl32\ : label is "\U0/rgb_buffer_reg[866][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][20]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][20]_srl32\ : label is "\U0/rgb_buffer_reg[866][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][21]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][21]_srl32\ : label is "\U0/rgb_buffer_reg[866][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][22]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][22]_srl32\ : label is "\U0/rgb_buffer_reg[866][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][23]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][23]_srl32\ : label is "\U0/rgb_buffer_reg[866][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][2]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][2]_srl32\ : label is "\U0/rgb_buffer_reg[866][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][3]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][3]_srl32\ : label is "\U0/rgb_buffer_reg[866][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][4]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][4]_srl32\ : label is "\U0/rgb_buffer_reg[866][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][5]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][5]_srl32\ : label is "\U0/rgb_buffer_reg[866][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][6]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][6]_srl32\ : label is "\U0/rgb_buffer_reg[866][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][7]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][7]_srl32\ : label is "\U0/rgb_buffer_reg[866][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][8]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][8]_srl32\ : label is "\U0/rgb_buffer_reg[866][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[866][9]_srl32\ : label is "\U0/rgb_buffer_reg[866] ";
attribute srl_name of \rgb_buffer_reg[866][9]_srl32\ : label is "\U0/rgb_buffer_reg[866][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][0]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][0]_srl32\ : label is "\U0/rgb_buffer_reg[898][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][10]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][10]_srl32\ : label is "\U0/rgb_buffer_reg[898][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][11]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][11]_srl32\ : label is "\U0/rgb_buffer_reg[898][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][12]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][12]_srl32\ : label is "\U0/rgb_buffer_reg[898][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][13]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][13]_srl32\ : label is "\U0/rgb_buffer_reg[898][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][14]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][14]_srl32\ : label is "\U0/rgb_buffer_reg[898][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][15]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][15]_srl32\ : label is "\U0/rgb_buffer_reg[898][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][16]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][16]_srl32\ : label is "\U0/rgb_buffer_reg[898][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][17]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][17]_srl32\ : label is "\U0/rgb_buffer_reg[898][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][18]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][18]_srl32\ : label is "\U0/rgb_buffer_reg[898][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][19]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][19]_srl32\ : label is "\U0/rgb_buffer_reg[898][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][1]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][1]_srl32\ : label is "\U0/rgb_buffer_reg[898][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][20]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][20]_srl32\ : label is "\U0/rgb_buffer_reg[898][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][21]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][21]_srl32\ : label is "\U0/rgb_buffer_reg[898][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][22]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][22]_srl32\ : label is "\U0/rgb_buffer_reg[898][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][23]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][23]_srl32\ : label is "\U0/rgb_buffer_reg[898][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][2]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][2]_srl32\ : label is "\U0/rgb_buffer_reg[898][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][3]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][3]_srl32\ : label is "\U0/rgb_buffer_reg[898][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][4]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][4]_srl32\ : label is "\U0/rgb_buffer_reg[898][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][5]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][5]_srl32\ : label is "\U0/rgb_buffer_reg[898][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][6]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][6]_srl32\ : label is "\U0/rgb_buffer_reg[898][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][7]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][7]_srl32\ : label is "\U0/rgb_buffer_reg[898][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][8]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][8]_srl32\ : label is "\U0/rgb_buffer_reg[898][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[898][9]_srl32\ : label is "\U0/rgb_buffer_reg[898] ";
attribute srl_name of \rgb_buffer_reg[898][9]_srl32\ : label is "\U0/rgb_buffer_reg[898][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][0]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][0]_srl32\ : label is "\U0/rgb_buffer_reg[930][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][10]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][10]_srl32\ : label is "\U0/rgb_buffer_reg[930][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][11]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][11]_srl32\ : label is "\U0/rgb_buffer_reg[930][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][12]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][12]_srl32\ : label is "\U0/rgb_buffer_reg[930][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][13]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][13]_srl32\ : label is "\U0/rgb_buffer_reg[930][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][14]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][14]_srl32\ : label is "\U0/rgb_buffer_reg[930][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][15]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][15]_srl32\ : label is "\U0/rgb_buffer_reg[930][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][16]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][16]_srl32\ : label is "\U0/rgb_buffer_reg[930][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][17]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][17]_srl32\ : label is "\U0/rgb_buffer_reg[930][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][18]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][18]_srl32\ : label is "\U0/rgb_buffer_reg[930][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][19]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][19]_srl32\ : label is "\U0/rgb_buffer_reg[930][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][1]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][1]_srl32\ : label is "\U0/rgb_buffer_reg[930][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][20]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][20]_srl32\ : label is "\U0/rgb_buffer_reg[930][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][21]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][21]_srl32\ : label is "\U0/rgb_buffer_reg[930][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][22]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][22]_srl32\ : label is "\U0/rgb_buffer_reg[930][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][23]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][23]_srl32\ : label is "\U0/rgb_buffer_reg[930][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][2]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][2]_srl32\ : label is "\U0/rgb_buffer_reg[930][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][3]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][3]_srl32\ : label is "\U0/rgb_buffer_reg[930][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][4]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][4]_srl32\ : label is "\U0/rgb_buffer_reg[930][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][5]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][5]_srl32\ : label is "\U0/rgb_buffer_reg[930][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][6]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][6]_srl32\ : label is "\U0/rgb_buffer_reg[930][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][7]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][7]_srl32\ : label is "\U0/rgb_buffer_reg[930][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][8]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][8]_srl32\ : label is "\U0/rgb_buffer_reg[930][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[930][9]_srl32\ : label is "\U0/rgb_buffer_reg[930] ";
attribute srl_name of \rgb_buffer_reg[930][9]_srl32\ : label is "\U0/rgb_buffer_reg[930][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][0]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][0]_srl32\ : label is "\U0/rgb_buffer_reg[962][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][10]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][10]_srl32\ : label is "\U0/rgb_buffer_reg[962][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][11]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][11]_srl32\ : label is "\U0/rgb_buffer_reg[962][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][12]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][12]_srl32\ : label is "\U0/rgb_buffer_reg[962][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][13]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][13]_srl32\ : label is "\U0/rgb_buffer_reg[962][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][14]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][14]_srl32\ : label is "\U0/rgb_buffer_reg[962][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][15]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][15]_srl32\ : label is "\U0/rgb_buffer_reg[962][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][16]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][16]_srl32\ : label is "\U0/rgb_buffer_reg[962][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][17]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][17]_srl32\ : label is "\U0/rgb_buffer_reg[962][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][18]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][18]_srl32\ : label is "\U0/rgb_buffer_reg[962][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][19]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][19]_srl32\ : label is "\U0/rgb_buffer_reg[962][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][1]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][1]_srl32\ : label is "\U0/rgb_buffer_reg[962][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][20]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][20]_srl32\ : label is "\U0/rgb_buffer_reg[962][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][21]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][21]_srl32\ : label is "\U0/rgb_buffer_reg[962][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][22]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][22]_srl32\ : label is "\U0/rgb_buffer_reg[962][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][23]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][23]_srl32\ : label is "\U0/rgb_buffer_reg[962][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][2]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][2]_srl32\ : label is "\U0/rgb_buffer_reg[962][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][3]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][3]_srl32\ : label is "\U0/rgb_buffer_reg[962][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][4]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][4]_srl32\ : label is "\U0/rgb_buffer_reg[962][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][5]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][5]_srl32\ : label is "\U0/rgb_buffer_reg[962][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][6]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][6]_srl32\ : label is "\U0/rgb_buffer_reg[962][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][7]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][7]_srl32\ : label is "\U0/rgb_buffer_reg[962][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][8]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][8]_srl32\ : label is "\U0/rgb_buffer_reg[962][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[962][9]_srl32\ : label is "\U0/rgb_buffer_reg[962] ";
attribute srl_name of \rgb_buffer_reg[962][9]_srl32\ : label is "\U0/rgb_buffer_reg[962][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][0]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][0]_srl32\ : label is "\U0/rgb_buffer_reg[98][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][10]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][10]_srl32\ : label is "\U0/rgb_buffer_reg[98][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][11]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][11]_srl32\ : label is "\U0/rgb_buffer_reg[98][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][12]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][12]_srl32\ : label is "\U0/rgb_buffer_reg[98][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][13]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][13]_srl32\ : label is "\U0/rgb_buffer_reg[98][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][14]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][14]_srl32\ : label is "\U0/rgb_buffer_reg[98][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][15]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][15]_srl32\ : label is "\U0/rgb_buffer_reg[98][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][16]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][16]_srl32\ : label is "\U0/rgb_buffer_reg[98][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][17]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][17]_srl32\ : label is "\U0/rgb_buffer_reg[98][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][18]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][18]_srl32\ : label is "\U0/rgb_buffer_reg[98][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][19]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][19]_srl32\ : label is "\U0/rgb_buffer_reg[98][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][1]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][1]_srl32\ : label is "\U0/rgb_buffer_reg[98][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][20]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][20]_srl32\ : label is "\U0/rgb_buffer_reg[98][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][21]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][21]_srl32\ : label is "\U0/rgb_buffer_reg[98][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][22]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][22]_srl32\ : label is "\U0/rgb_buffer_reg[98][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][23]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][23]_srl32\ : label is "\U0/rgb_buffer_reg[98][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][2]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][2]_srl32\ : label is "\U0/rgb_buffer_reg[98][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][3]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][3]_srl32\ : label is "\U0/rgb_buffer_reg[98][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][4]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][4]_srl32\ : label is "\U0/rgb_buffer_reg[98][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][5]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][5]_srl32\ : label is "\U0/rgb_buffer_reg[98][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][6]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][6]_srl32\ : label is "\U0/rgb_buffer_reg[98][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][7]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][7]_srl32\ : label is "\U0/rgb_buffer_reg[98][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][8]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][8]_srl32\ : label is "\U0/rgb_buffer_reg[98][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[98][9]_srl32\ : label is "\U0/rgb_buffer_reg[98] ";
attribute srl_name of \rgb_buffer_reg[98][9]_srl32\ : label is "\U0/rgb_buffer_reg[98][9]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][0]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][0]_srl32\ : label is "\U0/rgb_buffer_reg[994][0]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][10]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][10]_srl32\ : label is "\U0/rgb_buffer_reg[994][10]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][11]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][11]_srl32\ : label is "\U0/rgb_buffer_reg[994][11]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][12]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][12]_srl32\ : label is "\U0/rgb_buffer_reg[994][12]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][13]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][13]_srl32\ : label is "\U0/rgb_buffer_reg[994][13]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][14]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][14]_srl32\ : label is "\U0/rgb_buffer_reg[994][14]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][15]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][15]_srl32\ : label is "\U0/rgb_buffer_reg[994][15]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][16]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][16]_srl32\ : label is "\U0/rgb_buffer_reg[994][16]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][17]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][17]_srl32\ : label is "\U0/rgb_buffer_reg[994][17]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][18]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][18]_srl32\ : label is "\U0/rgb_buffer_reg[994][18]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][19]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][19]_srl32\ : label is "\U0/rgb_buffer_reg[994][19]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][1]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][1]_srl32\ : label is "\U0/rgb_buffer_reg[994][1]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][20]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][20]_srl32\ : label is "\U0/rgb_buffer_reg[994][20]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][21]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][21]_srl32\ : label is "\U0/rgb_buffer_reg[994][21]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][22]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][22]_srl32\ : label is "\U0/rgb_buffer_reg[994][22]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][23]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][23]_srl32\ : label is "\U0/rgb_buffer_reg[994][23]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][2]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][2]_srl32\ : label is "\U0/rgb_buffer_reg[994][2]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][3]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][3]_srl32\ : label is "\U0/rgb_buffer_reg[994][3]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][4]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][4]_srl32\ : label is "\U0/rgb_buffer_reg[994][4]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][5]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][5]_srl32\ : label is "\U0/rgb_buffer_reg[994][5]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][6]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][6]_srl32\ : label is "\U0/rgb_buffer_reg[994][6]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][7]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][7]_srl32\ : label is "\U0/rgb_buffer_reg[994][7]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][8]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][8]_srl32\ : label is "\U0/rgb_buffer_reg[994][8]_srl32 ";
attribute srl_bus_name of \rgb_buffer_reg[994][9]_srl32\ : label is "\U0/rgb_buffer_reg[994] ";
attribute srl_name of \rgb_buffer_reg[994][9]_srl32\ : label is "\U0/rgb_buffer_reg[994][9]_srl32 ";
begin
active <= \^active\;
\B[7]__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => hsync_in,
I1 => vsync_in,
O => \^active\
);
\i___0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \C[7]\(6),
I1 => \rgb_blur3__82_carry__0_n_5\,
I2 => Q(6),
O => \i___0_carry__0_i_1_n_0\
);
\i___0_carry__0_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__0_n_5\,
I1 => \B[6]__0\,
I2 => \C[6]__0_0\,
O => \i___0_carry__0_i_1__0_n_0\
);
\i___0_carry__0_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__6\(6),
I1 => \C[6]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry__0_n_5\,
O => \i___0_carry__0_i_1__1_n_0\
);
\i___0_carry__0_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__0_n_5\,
I1 => \B[6]__4\,
I2 => \C[6]__2_0\,
O => \i___0_carry__0_i_1__2_n_0\
);
\i___0_carry__0_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__10\(6),
I1 => \C[6]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry__0_n_5\,
O => \i___0_carry__0_i_1__3_n_0\
);
\i___0_carry__0_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \C[6]__4_0\,
I1 => PCIN(6),
I2 => \B[6]__8\,
O => \i___0_carry__0_i_1__4_n_0\
);
\i___0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => Q(5),
I1 => \C[7]\(5),
I2 => \rgb_blur3__82_carry__0_n_6\,
O => \i___0_carry__0_i_2_n_0\
);
\i___0_carry__0_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__0_n_6\,
I1 => \B[5]__0\,
I2 => \C[5]__0_0\,
O => \i___0_carry__0_i_2__0_n_0\
);
\i___0_carry__0_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__6\(5),
I1 => \C[5]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry__0_n_6\,
O => \i___0_carry__0_i_2__1_n_0\
);
\i___0_carry__0_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__0_n_6\,
I1 => \B[5]__4\,
I2 => \C[5]__2_0\,
O => \i___0_carry__0_i_2__2_n_0\
);
\i___0_carry__0_i_2__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__10\(5),
I1 => \C[5]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry__0_n_6\,
O => \i___0_carry__0_i_2__3_n_0\
);
\i___0_carry__0_i_2__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \C[5]__4_0\,
I1 => PCIN(5),
I2 => \B[5]__8\,
O => \i___0_carry__0_i_2__4_n_0\
);
\i___0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => Q(4),
I1 => \C[7]\(4),
I2 => \rgb_blur3__82_carry__0_n_7\,
O => \i___0_carry__0_i_3_n_0\
);
\i___0_carry__0_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__0_n_7\,
I1 => \B[4]__0\,
I2 => \C[4]__0_0\,
O => \i___0_carry__0_i_3__0_n_0\
);
\i___0_carry__0_i_3__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__6\(4),
I1 => \C[4]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry__0_n_7\,
O => \i___0_carry__0_i_3__1_n_0\
);
\i___0_carry__0_i_3__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__0_n_7\,
I1 => \B[4]__4\,
I2 => \C[4]__2_0\,
O => \i___0_carry__0_i_3__2_n_0\
);
\i___0_carry__0_i_3__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__10\(4),
I1 => \C[4]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry__0_n_7\,
O => \i___0_carry__0_i_3__3_n_0\
);
\i___0_carry__0_i_3__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \C[4]__4_0\,
I1 => PCIN(4),
I2 => \B[4]__8\,
O => \i___0_carry__0_i_3__4_n_0\
);
\i___0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => Q(3),
I1 => \C[7]\(3),
I2 => \rgb_blur3__82_carry_n_4\,
O => \i___0_carry__0_i_4_n_0\
);
\i___0_carry__0_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry_n_4\,
I1 => \B[3]__0\,
I2 => \C[3]__0_0\,
O => \i___0_carry__0_i_4__0_n_0\
);
\i___0_carry__0_i_4__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__6\(3),
I1 => \C[3]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry_n_4\,
O => \i___0_carry__0_i_4__1_n_0\
);
\i___0_carry__0_i_4__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry_n_4\,
I1 => \B[3]__4\,
I2 => \C[3]__2_0\,
O => \i___0_carry__0_i_4__2_n_0\
);
\i___0_carry__0_i_4__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__10\(3),
I1 => \C[3]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry_n_4\,
O => \i___0_carry__0_i_4__3_n_0\
);
\i___0_carry__0_i_4__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \C[3]__4_0\,
I1 => PCIN(3),
I2 => \B[3]__8\,
O => \i___0_carry__0_i_4__4_n_0\
);
\i___0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \i___0_carry__0_i_1_n_0\,
I1 => \rgb_blur3__82_carry__0_n_4\,
I2 => Q(7),
I3 => \C[7]\(7),
O => \i___0_carry__0_i_5_n_0\
);
\i___0_carry__0_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \i___0_carry__0_i_1__0_n_0\,
I1 => \rgb_blur3_inferred__0/i___0_carry__0_n_4\,
I2 => \B[7]__0\,
I3 => \C[7]__0_0\,
O => \i___0_carry__0_i_5__0_n_0\
);
\i___0_carry__0_i_5__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \i___0_carry__0_i_1__1_n_0\,
I1 => \rgb_blur3_inferred__2/i___82_carry__0_n_4\,
I2 => \B[7]__6\(7),
I3 => \C[7]__1\,
O => \i___0_carry__0_i_5__1_n_0\
);
\i___0_carry__0_i_5__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \i___0_carry__0_i_1__2_n_0\,
I1 => \rgb_blur3_inferred__3/i___0_carry__0_n_4\,
I2 => \B[7]__4\,
I3 => \C[7]__2_0\,
O => \i___0_carry__0_i_5__2_n_0\
);
\i___0_carry__0_i_5__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \i___0_carry__0_i_1__3_n_0\,
I1 => \rgb_blur3_inferred__5/i___82_carry__0_n_4\,
I2 => \B[7]__10\(7),
I3 => \C[7]__3\,
O => \i___0_carry__0_i_5__3_n_0\
);
\i___0_carry__0_i_5__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \i___0_carry__0_i_1__4_n_0\,
I1 => PCIN(7),
I2 => \B[7]__8\,
I3 => \C[7]__4_0\,
O => \i___0_carry__0_i_5__4_n_0\
);
\i___0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \C[7]\(6),
I1 => \rgb_blur3__82_carry__0_n_5\,
I2 => Q(6),
I3 => \i___0_carry__0_i_2_n_0\,
O => \i___0_carry__0_i_6_n_0\
);
\i___0_carry__0_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__0_n_5\,
I1 => \B[6]__0\,
I2 => \C[6]__0_0\,
I3 => \i___0_carry__0_i_2__0_n_0\,
O => \i___0_carry__0_i_6__0_n_0\
);
\i___0_carry__0_i_6__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__6\(6),
I1 => \C[6]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry__0_n_5\,
I3 => \i___0_carry__0_i_2__1_n_0\,
O => \i___0_carry__0_i_6__1_n_0\
);
\i___0_carry__0_i_6__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__0_n_5\,
I1 => \B[6]__4\,
I2 => \C[6]__2_0\,
I3 => \i___0_carry__0_i_2__2_n_0\,
O => \i___0_carry__0_i_6__2_n_0\
);
\i___0_carry__0_i_6__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__10\(6),
I1 => \C[6]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry__0_n_5\,
I3 => \i___0_carry__0_i_2__3_n_0\,
O => \i___0_carry__0_i_6__3_n_0\
);
\i___0_carry__0_i_6__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \C[6]__4_0\,
I1 => PCIN(6),
I2 => \B[6]__8\,
I3 => \i___0_carry__0_i_2__4_n_0\,
O => \i___0_carry__0_i_6__4_n_0\
);
\i___0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q(5),
I1 => \C[7]\(5),
I2 => \rgb_blur3__82_carry__0_n_6\,
I3 => \i___0_carry__0_i_3_n_0\,
O => \i___0_carry__0_i_7_n_0\
);
\i___0_carry__0_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__0_n_6\,
I1 => \B[5]__0\,
I2 => \C[5]__0_0\,
I3 => \i___0_carry__0_i_3__0_n_0\,
O => \i___0_carry__0_i_7__0_n_0\
);
\i___0_carry__0_i_7__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__6\(5),
I1 => \C[5]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry__0_n_6\,
I3 => \i___0_carry__0_i_3__1_n_0\,
O => \i___0_carry__0_i_7__1_n_0\
);
\i___0_carry__0_i_7__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__0_n_6\,
I1 => \B[5]__4\,
I2 => \C[5]__2_0\,
I3 => \i___0_carry__0_i_3__2_n_0\,
O => \i___0_carry__0_i_7__2_n_0\
);
\i___0_carry__0_i_7__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__10\(5),
I1 => \C[5]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry__0_n_6\,
I3 => \i___0_carry__0_i_3__3_n_0\,
O => \i___0_carry__0_i_7__3_n_0\
);
\i___0_carry__0_i_7__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \C[5]__4_0\,
I1 => PCIN(5),
I2 => \B[5]__8\,
I3 => \i___0_carry__0_i_3__4_n_0\,
O => \i___0_carry__0_i_7__4_n_0\
);
\i___0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q(4),
I1 => \C[7]\(4),
I2 => \rgb_blur3__82_carry__0_n_7\,
I3 => \i___0_carry__0_i_4_n_0\,
O => \i___0_carry__0_i_8_n_0\
);
\i___0_carry__0_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__0_n_7\,
I1 => \B[4]__0\,
I2 => \C[4]__0_0\,
I3 => \i___0_carry__0_i_4__0_n_0\,
O => \i___0_carry__0_i_8__0_n_0\
);
\i___0_carry__0_i_8__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__6\(4),
I1 => \C[4]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry__0_n_7\,
I3 => \i___0_carry__0_i_4__1_n_0\,
O => \i___0_carry__0_i_8__1_n_0\
);
\i___0_carry__0_i_8__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__0_n_7\,
I1 => \B[4]__4\,
I2 => \C[4]__2_0\,
I3 => \i___0_carry__0_i_4__2_n_0\,
O => \i___0_carry__0_i_8__2_n_0\
);
\i___0_carry__0_i_8__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__10\(4),
I1 => \C[4]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry__0_n_7\,
I3 => \i___0_carry__0_i_4__3_n_0\,
O => \i___0_carry__0_i_8__3_n_0\
);
\i___0_carry__0_i_8__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \C[4]__4_0\,
I1 => PCIN(4),
I2 => \B[4]__8\,
I3 => \i___0_carry__0_i_4__4_n_0\,
O => \i___0_carry__0_i_8__4_n_0\
);
\i___0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3__82_carry__1_n_5\,
I1 => \rgb_blur3__82_carry__1_n_4\,
O => \i___0_carry__1_i_1_n_0\
);
\i___0_carry__1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3_inferred__2/i___82_carry__1_n_5\,
I1 => \rgb_blur3_inferred__2/i___82_carry__1_n_4\,
O => \i___0_carry__1_i_1__0_n_0\
);
\i___0_carry__1_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3_inferred__5/i___82_carry__1_n_5\,
I1 => \rgb_blur3_inferred__5/i___82_carry__1_n_4\,
O => \i___0_carry__1_i_1__1_n_0\
);
\i___0_carry__1_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__1_n_4\,
O => \i___0_carry__1_i_1__2_n_0\
);
\i___0_carry__1_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__1_n_4\,
O => \i___0_carry__1_i_1__3_n_0\
);
\i___0_carry__1_i_1__4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(11),
O => \i___0_carry__1_i_1__4_n_0\
);
\i___0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3__82_carry__1_n_6\,
I1 => \rgb_blur3__82_carry__1_n_5\,
O => \i___0_carry__1_i_2_n_0\
);
\i___0_carry__1_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3_inferred__2/i___82_carry__1_n_6\,
I1 => \rgb_blur3_inferred__2/i___82_carry__1_n_5\,
O => \i___0_carry__1_i_2__0_n_0\
);
\i___0_carry__1_i_2__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3_inferred__5/i___82_carry__1_n_6\,
I1 => \rgb_blur3_inferred__5/i___82_carry__1_n_5\,
O => \i___0_carry__1_i_2__1_n_0\
);
\i___0_carry__1_i_2__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__1_n_5\,
O => \i___0_carry__1_i_2__2_n_0\
);
\i___0_carry__1_i_2__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__1_n_5\,
O => \i___0_carry__1_i_2__3_n_0\
);
\i___0_carry__1_i_2__4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(10),
O => \i___0_carry__1_i_2__4_n_0\
);
\i___0_carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3__82_carry__1_n_6\,
O => \i___0_carry__1_i_3_n_0\
);
\i___0_carry__1_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__1_n_6\,
O => \i___0_carry__1_i_3__0_n_0\
);
\i___0_carry__1_i_3__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__2/i___82_carry__1_n_6\,
O => \i___0_carry__1_i_3__1_n_0\
);
\i___0_carry__1_i_3__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__1_n_6\,
O => \i___0_carry__1_i_3__2_n_0\
);
\i___0_carry__1_i_3__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__5/i___82_carry__1_n_6\,
O => \i___0_carry__1_i_3__3_n_0\
);
\i___0_carry__1_i_3__4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(9),
O => \i___0_carry__1_i_3__4_n_0\
);
\i___0_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"17E8"
)
port map (
I0 => Q(7),
I1 => \rgb_blur3__82_carry__0_n_4\,
I2 => \C[7]\(7),
I3 => \rgb_blur3__82_carry__1_n_7\,
O => \i___0_carry__1_i_4_n_0\
);
\i___0_carry__1_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"17E8"
)
port map (
I0 => \C[7]__0_0\,
I1 => \B[7]__0\,
I2 => \rgb_blur3_inferred__0/i___0_carry__0_n_4\,
I3 => \rgb_blur3_inferred__0/i___0_carry__1_n_7\,
O => \i___0_carry__1_i_4__0_n_0\
);
\i___0_carry__1_i_4__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"17E8"
)
port map (
I0 => \rgb_blur3_inferred__2/i___82_carry__0_n_4\,
I1 => \C[7]__1\,
I2 => \B[7]__6\(7),
I3 => \rgb_blur3_inferred__2/i___82_carry__1_n_7\,
O => \i___0_carry__1_i_4__1_n_0\
);
\i___0_carry__1_i_4__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"17E8"
)
port map (
I0 => \C[7]__2_0\,
I1 => \B[7]__4\,
I2 => \rgb_blur3_inferred__3/i___0_carry__0_n_4\,
I3 => \rgb_blur3_inferred__3/i___0_carry__1_n_7\,
O => \i___0_carry__1_i_4__2_n_0\
);
\i___0_carry__1_i_4__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"17E8"
)
port map (
I0 => \rgb_blur3_inferred__5/i___82_carry__0_n_4\,
I1 => \C[7]__3\,
I2 => \B[7]__10\(7),
I3 => \rgb_blur3_inferred__5/i___82_carry__1_n_7\,
O => \i___0_carry__1_i_4__3_n_0\
);
\i___0_carry__1_i_4__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"17E8"
)
port map (
I0 => \B[7]__8\,
I1 => PCIN(7),
I2 => \C[7]__4_0\,
I3 => PCIN(8),
O => \i___0_carry__1_i_4__4_n_0\
);
\i___0_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_blur3__82_carry__2_n_7\,
I1 => \rgb_blur3__82_carry__2_n_2\,
O => \i___0_carry__2_i_1_n_0\
);
\i___0_carry__2_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_blur3_inferred__2/i___82_carry__2_n_7\,
I1 => \rgb_blur3_inferred__2/i___82_carry__2_n_2\,
O => \i___0_carry__2_i_1__0_n_0\
);
\i___0_carry__2_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_blur3_inferred__5/i___82_carry__2_n_7\,
I1 => \rgb_blur3_inferred__5/i___82_carry__2_n_2\,
O => \i___0_carry__2_i_1__1_n_0\
);
\i___0_carry__2_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__2_i_1__2_n_0\
);
\i___0_carry__2_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__2_i_1__3_n_0\
);
\i___0_carry__2_i_1__4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__2_i_1__4_n_0\
);
\i___0_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3__82_carry__1_n_4\,
I1 => \rgb_blur3__82_carry__2_n_7\,
O => \i___0_carry__2_i_2_n_0\
);
\i___0_carry__2_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3_inferred__2/i___82_carry__1_n_4\,
I1 => \rgb_blur3_inferred__2/i___82_carry__2_n_7\,
O => \i___0_carry__2_i_2__0_n_0\
);
\i___0_carry__2_i_2__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3_inferred__5/i___82_carry__1_n_4\,
I1 => \rgb_blur3_inferred__5/i___82_carry__2_n_7\,
O => \i___0_carry__2_i_2__1_n_0\
);
\i___0_carry__2_i_2__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__2_i_2__2_n_0\
);
\i___0_carry__2_i_2__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__2_i_2__3_n_0\
);
\i___0_carry__2_i_2__4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__2_i_2__4_n_0\
);
\i___0_carry__2_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_6\,
O => \i___0_carry__2_i_3_n_0\
);
\i___0_carry__2_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_6\,
O => \i___0_carry__2_i_3__0_n_0\
);
\i___0_carry__2_i_3__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(13),
O => \i___0_carry__2_i_3__1_n_0\
);
\i___0_carry__2_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_7\,
O => \i___0_carry__2_i_4_n_0\
);
\i___0_carry__2_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_7\,
O => \i___0_carry__2_i_4__0_n_0\
);
\i___0_carry__2_i_4__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(12),
O => \i___0_carry__2_i_4__1_n_0\
);
\i___0_carry__3_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__3_i_1_n_0\
);
\i___0_carry__3_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__3_i_1__0_n_0\
);
\i___0_carry__3_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__3_i_1__1_n_0\
);
\i___0_carry__3_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__3_i_2_n_0\
);
\i___0_carry__3_i_2__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__3_i_2__0_n_0\
);
\i___0_carry__3_i_2__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__3_i_2__1_n_0\
);
\i___0_carry__3_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__3_i_3_n_0\
);
\i___0_carry__3_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__3_i_3__0_n_0\
);
\i___0_carry__3_i_3__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__3_i_3__1_n_0\
);
\i___0_carry__3_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__3_i_4_n_0\
);
\i___0_carry__3_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__3_i_4__0_n_0\
);
\i___0_carry__3_i_4__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__3_i_4__1_n_0\
);
\i___0_carry__4_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__4_i_1_n_0\
);
\i___0_carry__4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__4_i_1__0_n_0\
);
\i___0_carry__4_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__4_i_1__1_n_0\
);
\i___0_carry__4_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__4_i_2_n_0\
);
\i___0_carry__4_i_2__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__4_i_2__0_n_0\
);
\i___0_carry__4_i_2__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__4_i_2__1_n_0\
);
\i___0_carry__4_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__4_i_3_n_0\
);
\i___0_carry__4_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__4_i_3__0_n_0\
);
\i___0_carry__4_i_3__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__4_i_3__1_n_0\
);
\i___0_carry__4_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__4_i_4_n_0\
);
\i___0_carry__4_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__4_i_4__0_n_0\
);
\i___0_carry__4_i_4__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__4_i_4__1_n_0\
);
\i___0_carry__5_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__5_i_1_n_0\
);
\i___0_carry__5_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__5_i_1__0_n_0\
);
\i___0_carry__5_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__5_i_1__1_n_0\
);
\i___0_carry__5_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__5_i_2_n_0\
);
\i___0_carry__5_i_2__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__5_i_2__0_n_0\
);
\i___0_carry__5_i_2__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__5_i_2__1_n_0\
);
\i___0_carry__5_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__5_i_3_n_0\
);
\i___0_carry__5_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__5_i_3__0_n_0\
);
\i___0_carry__5_i_3__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__5_i_3__1_n_0\
);
\i___0_carry__5_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__5_i_4_n_0\
);
\i___0_carry__5_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__5_i_4__0_n_0\
);
\i___0_carry__5_i_4__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__5_i_4__1_n_0\
);
\i___0_carry__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__6_i_1_n_0\
);
\i___0_carry__6_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__6_i_1__0_n_0\
);
\i___0_carry__6_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__6_i_1__1_n_0\
);
\i___0_carry__6_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__6_i_2_n_0\
);
\i___0_carry__6_i_2__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__6_i_2__0_n_0\
);
\i___0_carry__6_i_2__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__6_i_2__1_n_0\
);
\i___0_carry__6_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__6_i_3_n_0\
);
\i___0_carry__6_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__6_i_3__0_n_0\
);
\i___0_carry__6_i_3__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__6_i_3__1_n_0\
);
\i___0_carry__6_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O => \i___0_carry__6_i_4_n_0\
);
\i___0_carry__6_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O => \i___0_carry__6_i_4__0_n_0\
);
\i___0_carry__6_i_4__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => PCIN(31),
O => \i___0_carry__6_i_4__1_n_0\
);
\i___0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => Q(2),
I1 => \C[7]\(2),
I2 => \rgb_blur3__82_carry_n_5\,
O => \i___0_carry_i_1_n_0\
);
\i___0_carry_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry_n_5\,
I1 => \B[2]__0\,
I2 => \C[2]__0_0\,
O => \i___0_carry_i_1__0_n_0\
);
\i___0_carry_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__6\(2),
I1 => \C[2]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry_n_5\,
O => \i___0_carry_i_1__1_n_0\
);
\i___0_carry_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry_n_5\,
I1 => \B[2]__4\,
I2 => \C[2]__2_0\,
O => \i___0_carry_i_1__2_n_0\
);
\i___0_carry_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__10\(2),
I1 => \C[2]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry_n_5\,
O => \i___0_carry_i_1__3_n_0\
);
\i___0_carry_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \C[2]__4_0\,
I1 => PCIN(2),
I2 => \B[2]__8\,
O => \i___0_carry_i_1__4_n_0\
);
\i___0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => Q(1),
I1 => \C[7]\(1),
I2 => \rgb_blur3__82_carry_n_6\,
O => \i___0_carry_i_2_n_0\
);
\i___0_carry_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[1]__0\,
I1 => \C[1]__0_0\,
I2 => \rgb_blur3_inferred__0/i___0_carry_n_6\,
O => \i___0_carry_i_2__0_n_0\
);
\i___0_carry_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__6\(1),
I1 => \C[1]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry_n_6\,
O => \i___0_carry_i_2__1_n_0\
);
\i___0_carry_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry_n_6\,
I1 => \B[1]__4\,
I2 => \C[1]__2_0\,
O => \i___0_carry_i_2__2_n_0\
);
\i___0_carry_i_2__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \B[7]__10\(1),
I1 => \C[1]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry_n_6\,
O => \i___0_carry_i_2__3_n_0\
);
\i___0_carry_i_2__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \C[1]__4_0\,
I1 => PCIN(1),
I2 => \B[1]__8\,
O => \i___0_carry_i_2__4_n_0\
);
\i___0_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \C[7]\(0),
I1 => Q(0),
O => \i___0_carry_i_3_n_0\
);
\i___0_carry_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \C[0]__0_0\,
I1 => \B[0]\,
I2 => \rgb_blur3_inferred__0/i___0_carry_n_7\,
O => \i___0_carry_i_3__0_n_0\
);
\i___0_carry_i_3__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \B[7]__6\(0),
I1 => \C[0]__1\,
O => \i___0_carry_i_3__1_n_0\
);
\i___0_carry_i_3__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry_n_7\,
I1 => \B[0]__3\,
I2 => \C[0]__2_0\,
O => \i___0_carry_i_3__2_n_0\
);
\i___0_carry_i_3__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \B[7]__10\(0),
I1 => \C[0]__3\,
O => \i___0_carry_i_3__3_n_0\
);
\i___0_carry_i_3__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => PCIN(0),
I1 => \B[0]__7\,
I2 => \C[0]__4_0\,
O => \i___0_carry_i_3__4_n_0\
);
\i___0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q(3),
I1 => \C[7]\(3),
I2 => \rgb_blur3__82_carry_n_4\,
I3 => \i___0_carry_i_1_n_0\,
O => \i___0_carry_i_4_n_0\
);
\i___0_carry_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry_n_4\,
I1 => \B[3]__0\,
I2 => \C[3]__0_0\,
I3 => \i___0_carry_i_1__0_n_0\,
O => \i___0_carry_i_4__0_n_0\
);
\i___0_carry_i_4__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__6\(3),
I1 => \C[3]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry_n_4\,
I3 => \i___0_carry_i_1__1_n_0\,
O => \i___0_carry_i_4__1_n_0\
);
\i___0_carry_i_4__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry_n_4\,
I1 => \B[3]__4\,
I2 => \C[3]__2_0\,
I3 => \i___0_carry_i_1__2_n_0\,
O => \i___0_carry_i_4__2_n_0\
);
\i___0_carry_i_4__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__10\(3),
I1 => \C[3]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry_n_4\,
I3 => \i___0_carry_i_1__3_n_0\,
O => \i___0_carry_i_4__3_n_0\
);
\i___0_carry_i_4__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \C[3]__4_0\,
I1 => PCIN(3),
I2 => \B[3]__8\,
I3 => \i___0_carry_i_1__4_n_0\,
O => \i___0_carry_i_4__4_n_0\
);
\i___0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q(2),
I1 => \C[7]\(2),
I2 => \rgb_blur3__82_carry_n_5\,
I3 => \i___0_carry_i_2_n_0\,
O => \i___0_carry_i_5_n_0\
);
\i___0_carry_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__0/i___0_carry_n_5\,
I1 => \B[2]__0\,
I2 => \C[2]__0_0\,
I3 => \i___0_carry_i_2__0_n_0\,
O => \i___0_carry_i_5__0_n_0\
);
\i___0_carry_i_5__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__6\(2),
I1 => \C[2]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry_n_5\,
I3 => \i___0_carry_i_2__1_n_0\,
O => \i___0_carry_i_5__1_n_0\
);
\i___0_carry_i_5__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry_n_5\,
I1 => \B[2]__4\,
I2 => \C[2]__2_0\,
I3 => \i___0_carry_i_2__2_n_0\,
O => \i___0_carry_i_5__2_n_0\
);
\i___0_carry_i_5__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__10\(2),
I1 => \C[2]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry_n_5\,
I3 => \i___0_carry_i_2__3_n_0\,
O => \i___0_carry_i_5__3_n_0\
);
\i___0_carry_i_5__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \C[2]__4_0\,
I1 => PCIN(2),
I2 => \B[2]__8\,
I3 => \i___0_carry_i_2__4_n_0\,
O => \i___0_carry_i_5__4_n_0\
);
\i___0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q(1),
I1 => \C[7]\(1),
I2 => \rgb_blur3__82_carry_n_6\,
I3 => \i___0_carry_i_3_n_0\,
O => \i___0_carry_i_6_n_0\
);
\i___0_carry_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[1]__0\,
I1 => \C[1]__0_0\,
I2 => \rgb_blur3_inferred__0/i___0_carry_n_6\,
I3 => \i___0_carry_i_3__0_n_0\,
O => \i___0_carry_i_6__0_n_0\
);
\i___0_carry_i_6__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__6\(1),
I1 => \C[1]__1\,
I2 => \rgb_blur3_inferred__2/i___82_carry_n_6\,
I3 => \i___0_carry_i_3__1_n_0\,
O => \i___0_carry_i_6__1_n_0\
);
\i___0_carry_i_6__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry_n_6\,
I1 => \B[1]__4\,
I2 => \C[1]__2_0\,
I3 => \i___0_carry_i_3__2_n_0\,
O => \i___0_carry_i_6__2_n_0\
);
\i___0_carry_i_6__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \B[7]__10\(1),
I1 => \C[1]__3\,
I2 => \rgb_blur3_inferred__5/i___82_carry_n_6\,
I3 => \i___0_carry_i_3__3_n_0\,
O => \i___0_carry_i_6__3_n_0\
);
\i___0_carry_i_6__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \C[1]__4_0\,
I1 => PCIN(1),
I2 => \B[1]__8\,
I3 => \i___0_carry_i_3__4_n_0\,
O => \i___0_carry_i_6__4_n_0\
);
\i___0_carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \C[7]\(0),
I1 => Q(0),
O => \i___0_carry_i_7_n_0\
);
\i___0_carry_i_7__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \C[0]__0_0\,
I1 => \B[0]\,
I2 => \rgb_blur3_inferred__0/i___0_carry_n_7\,
O => \i___0_carry_i_7__0_n_0\
);
\i___0_carry_i_7__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \B[7]__6\(0),
I1 => \C[0]__1\,
O => \i___0_carry_i_7__1_n_0\
);
\i___0_carry_i_7__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \rgb_blur3_inferred__3/i___0_carry_n_7\,
I1 => \B[0]__3\,
I2 => \C[0]__2_0\,
O => \i___0_carry_i_7__2_n_0\
);
\i___0_carry_i_7__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \B[7]__10\(0),
I1 => \C[0]__3\,
O => \i___0_carry_i_7__3_n_0\
);
\i___0_carry_i_7__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => PCIN(0),
I1 => \B[0]__7\,
I2 => \C[0]__4_0\,
O => \i___0_carry_i_7__4_n_0\
);
\i___24_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(14),
I1 => \rgb_blur3_inferred__2/i__carry__1_n_7\,
O => \i___24_carry__0_i_1_n_0\
);
\i___24_carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(22),
I1 => \rgb_blur3_inferred__5/i__carry__1_n_7\,
O => \i___24_carry__0_i_1__0_n_0\
);
\i___24_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(13),
I1 => \rgb_blur3_inferred__2/i__carry__0_n_4\,
O => \i___24_carry__0_i_2_n_0\
);
\i___24_carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(21),
I1 => \rgb_blur3_inferred__5/i__carry__0_n_4\,
O => \i___24_carry__0_i_2__0_n_0\
);
\i___24_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(12),
I1 => \rgb_blur3_inferred__2/i__carry__0_n_5\,
O => \i___24_carry__0_i_3_n_0\
);
\i___24_carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(20),
I1 => \rgb_blur3_inferred__5/i__carry__0_n_5\,
O => \i___24_carry__0_i_3__0_n_0\
);
\i___24_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(11),
I1 => \rgb_blur3_inferred__2/i__carry__0_n_6\,
O => \i___24_carry__0_i_4_n_0\
);
\i___24_carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(19),
I1 => \rgb_blur3_inferred__5/i__carry__0_n_6\,
O => \i___24_carry__0_i_4__0_n_0\
);
\i___24_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(15),
I1 => \rgb_blur3_inferred__2/i__carry__1_n_2\,
O => \i___24_carry__1_i_1_n_0\
);
\i___24_carry__1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(23),
I1 => \rgb_blur3_inferred__5/i__carry__1_n_2\,
O => \i___24_carry__1_i_1__0_n_0\
);
\i___24_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(10),
I1 => \rgb_blur3_inferred__2/i__carry__0_n_7\,
O => \i___24_carry_i_1_n_0\
);
\i___24_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(18),
I1 => \rgb_blur3_inferred__5/i__carry__0_n_7\,
O => \i___24_carry_i_1__0_n_0\
);
\i___24_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(9),
I1 => \rgb_blur3_inferred__2/i__carry_n_4\,
O => \i___24_carry_i_2_n_0\
);
\i___24_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(17),
I1 => \rgb_blur3_inferred__5/i__carry_n_4\,
O => \i___24_carry_i_2__0_n_0\
);
\i___24_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(8),
I1 => \rgb_blur3_inferred__2/i__carry_n_5\,
O => \i___24_carry_i_3_n_0\
);
\i___24_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(16),
I1 => \rgb_blur3_inferred__5/i__carry_n_5\,
O => \i___24_carry_i_3__0_n_0\
);
\i___24_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__2/i__carry_n_6\,
O => \i___24_carry_i_4_n_0\
);
\i___24_carry_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__5/i__carry_n_6\,
O => \i___24_carry_i_4__0_n_0\
);
\i___50_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I6(6),
I1 => \rgb_blur3_inferred__2/i___24_carry__0_n_5\,
O => \i___50_carry__0_i_1_n_0\
);
\i___50_carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I12(6),
I1 => \rgb_blur3_inferred__5/i___24_carry__0_n_5\,
O => \i___50_carry__0_i_1__0_n_0\
);
\i___50_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I6(5),
I1 => \rgb_blur3_inferred__2/i___24_carry__0_n_6\,
O => \i___50_carry__0_i_2_n_0\
);
\i___50_carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I12(5),
I1 => \rgb_blur3_inferred__5/i___24_carry__0_n_6\,
O => \i___50_carry__0_i_2__0_n_0\
);
\i___50_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I6(4),
I1 => \rgb_blur3_inferred__2/i___24_carry__0_n_7\,
O => \i___50_carry__0_i_3_n_0\
);
\i___50_carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I12(4),
I1 => \rgb_blur3_inferred__5/i___24_carry__0_n_7\,
O => \i___50_carry__0_i_3__0_n_0\
);
\i___50_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I6(3),
I1 => \rgb_blur3_inferred__2/i___24_carry_n_4\,
O => \i___50_carry__0_i_4_n_0\
);
\i___50_carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I12(3),
I1 => \rgb_blur3_inferred__5/i___24_carry_n_4\,
O => \i___50_carry__0_i_4__0_n_0\
);
\i___50_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__2/i___24_carry__1_n_7\,
O => \i___50_carry__1_i_1_n_0\
);
\i___50_carry__1_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__5/i___24_carry__1_n_7\,
O => \i___50_carry__1_i_1__0_n_0\
);
\i___50_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__2/i___24_carry__1_n_2\,
O => \i___50_carry__1_i_2_n_0\
);
\i___50_carry__1_i_2__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__5/i___24_carry__1_n_2\,
O => \i___50_carry__1_i_2__0_n_0\
);
\i___50_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3_inferred__2/i___24_carry__1_n_7\,
I1 => \rgb_blur3_inferred__2/i___24_carry__1_n_2\,
O => \i___50_carry__1_i_3_n_0\
);
\i___50_carry__1_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3_inferred__5/i___24_carry__1_n_7\,
I1 => \rgb_blur3_inferred__5/i___24_carry__1_n_2\,
O => \i___50_carry__1_i_3__0_n_0\
);
\i___50_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__2/i___24_carry__1_n_7\,
O => \i___50_carry__1_i_4_n_0\
);
\i___50_carry__1_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__5/i___24_carry__1_n_7\,
O => \i___50_carry__1_i_4__0_n_0\
);
\i___50_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I6(7),
I1 => \rgb_blur3_inferred__2/i___24_carry__0_n_4\,
O => \i___50_carry__1_i_5_n_0\
);
\i___50_carry__1_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I12(7),
I1 => \rgb_blur3_inferred__5/i___24_carry__0_n_4\,
O => \i___50_carry__1_i_5__0_n_0\
);
\i___50_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I6(2),
I1 => \rgb_blur3_inferred__2/i___24_carry_n_5\,
O => \i___50_carry_i_1_n_0\
);
\i___50_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I12(2),
I1 => \rgb_blur3_inferred__5/i___24_carry_n_5\,
O => \i___50_carry_i_1__0_n_0\
);
\i___50_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I6(1),
I1 => \rgb_blur3_inferred__2/i___24_carry_n_6\,
O => \i___50_carry_i_2_n_0\
);
\i___50_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I12(1),
I1 => \rgb_blur3_inferred__5/i___24_carry_n_6\,
O => \i___50_carry_i_2__0_n_0\
);
\i___50_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I6(0),
I1 => \rgb_blur3_inferred__2/i___24_carry_n_7\,
O => \i___50_carry_i_3_n_0\
);
\i___50_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I12(0),
I1 => \rgb_blur3_inferred__5/i___24_carry_n_7\,
O => \i___50_carry_i_3__0_n_0\
);
\i___82_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I7(6),
I1 => \C__0\(7),
O => \i___82_carry__0_i_1_n_0\
);
\i___82_carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I13(6),
I1 => \C__1\(7),
O => \i___82_carry__0_i_1__0_n_0\
);
\i___82_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I7(5),
I1 => \C__0\(6),
O => \i___82_carry__0_i_2_n_0\
);
\i___82_carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I13(5),
I1 => \C__1\(6),
O => \i___82_carry__0_i_2__0_n_0\
);
\i___82_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I7(4),
I1 => \C__0\(5),
O => \i___82_carry__0_i_3_n_0\
);
\i___82_carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I13(4),
I1 => \C__1\(5),
O => \i___82_carry__0_i_3__0_n_0\
);
\i___82_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I7(3),
I1 => \C__0\(4),
O => \i___82_carry__0_i_4_n_0\
);
\i___82_carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I13(3),
I1 => \C__1\(4),
O => \i___82_carry__0_i_4__0_n_0\
);
\i___82_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \C__0\(9),
O => \i___82_carry__1_i_1_n_0\
);
\i___82_carry__1_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \C__1\(9),
O => \i___82_carry__1_i_1__0_n_0\
);
\i___82_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \C__0\(10),
I1 => \C__0\(11),
O => \i___82_carry__1_i_2_n_0\
);
\i___82_carry__1_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \C__1\(10),
I1 => \C__1\(11),
O => \i___82_carry__1_i_2__0_n_0\
);
\i___82_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \C__0\(9),
I1 => \C__0\(10),
O => \i___82_carry__1_i_3_n_0\
);
\i___82_carry__1_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \C__1\(9),
I1 => \C__1\(10),
O => \i___82_carry__1_i_3__0_n_0\
);
\i___82_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \C__0\(9),
O => \i___82_carry__1_i_4_n_0\
);
\i___82_carry__1_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \C__1\(9),
O => \i___82_carry__1_i_4__0_n_0\
);
\i___82_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I7(7),
I1 => \C__0\(8),
O => \i___82_carry__1_i_5_n_0\
);
\i___82_carry__1_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I13(7),
I1 => \C__1\(8),
O => \i___82_carry__1_i_5__0_n_0\
);
\i___82_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \C__0\(11),
I1 => \i___82_carry__2_i_2_n_3\,
O => \i___82_carry__2_i_1_n_0\
);
\i___82_carry__2_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \C__1\(11),
I1 => \i___82_carry__2_i_2__0_n_3\,
O => \i___82_carry__2_i_1__0_n_0\
);
\i___82_carry__2_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i___50_carry__1_n_0\,
CO(3 downto 1) => \NLW_i___82_carry__2_i_2_CO_UNCONNECTED\(3 downto 1),
CO(0) => \i___82_carry__2_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_i___82_carry__2_i_2_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => B"0001"
);
\i___82_carry__2_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i___50_carry__1_n_0\,
CO(3 downto 1) => \NLW_i___82_carry__2_i_2__0_CO_UNCONNECTED\(3 downto 1),
CO(0) => \i___82_carry__2_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_i___82_carry__2_i_2__0_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => B"0001"
);
\i___82_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I7(2),
I1 => \C__0\(3),
O => \i___82_carry_i_1_n_0\
);
\i___82_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I13(2),
I1 => \C__1\(3),
O => \i___82_carry_i_1__0_n_0\
);
\i___82_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I7(1),
I1 => \C__0\(2),
O => \i___82_carry_i_2_n_0\
);
\i___82_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I13(1),
I1 => \C__1\(2),
O => \i___82_carry_i_2__0_n_0\
);
\i___82_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I7(0),
I1 => \C__0\(1),
O => \i___82_carry_i_3_n_0\
);
\i___82_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I13(0),
I1 => \C__1\(1),
O => \i___82_carry_i_3__0_n_0\
);
\i__carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__2_n_4\,
I1 => \rgb_blur3_inferred__4/i___0_carry__2_n_5\,
O => \i__carry__0_i_1_n_0\
);
\i__carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(14),
I1 => rgb_blur3(15),
O => \i__carry__0_i_1__0_n_0\
);
\i__carry__0_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(14),
I1 => \B[7]__5\(6),
O => \i__carry__0_i_1__1_n_0\
);
\i__carry__0_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(22),
I1 => \B[7]__9\(6),
O => \i__carry__0_i_1__2_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__2_n_6\,
I1 => \rgb_blur3_inferred__4/i___0_carry__2_n_7\,
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(12),
I1 => rgb_blur3(13),
O => \i__carry__0_i_2__0_n_0\
);
\i__carry__0_i_2__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(13),
I1 => \B[7]__5\(5),
O => \i__carry__0_i_2__1_n_0\
);
\i__carry__0_i_2__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(21),
I1 => \B[7]__9\(5),
O => \i__carry__0_i_2__2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__1_n_4\,
I1 => \rgb_blur3_inferred__4/i___0_carry__1_n_5\,
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(11),
I1 => rgb_blur3(10),
O => \i__carry__0_i_3__0_n_0\
);
\i__carry__0_i_3__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(12),
I1 => \B[7]__5\(4),
O => \i__carry__0_i_3__1_n_0\
);
\i__carry__0_i_3__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(20),
I1 => \B[7]__9\(4),
O => \i__carry__0_i_3__2_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__1_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry__1_n_6\,
O => \i__carry__0_i_4_n_0\
);
\i__carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(8),
I1 => rgb_blur3(9),
O => \i__carry__0_i_4__0_n_0\
);
\i__carry__0_i_4__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(11),
I1 => \B[7]__5\(3),
O => \i__carry__0_i_4__1_n_0\
);
\i__carry__0_i_4__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(19),
I1 => \B[7]__9\(3),
O => \i__carry__0_i_4__2_n_0\
);
\i__carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__2_n_5\,
I1 => \rgb_blur3_inferred__4/i___0_carry__2_n_4\,
O => \i__carry__0_i_5_n_0\
);
\i__carry__0_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(15),
I1 => rgb_blur3(14),
O => \i__carry__0_i_5__0_n_0\
);
\i__carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__2_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry__2_n_6\,
O => \i__carry__0_i_6_n_0\
);
\i__carry__0_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(13),
I1 => rgb_blur3(12),
O => \i__carry__0_i_6__0_n_0\
);
\i__carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__1_n_5\,
I1 => \rgb_blur3_inferred__4/i___0_carry__1_n_4\,
O => \i__carry__0_i_7_n_0\
);
\i__carry__0_i_7__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(10),
I1 => rgb_blur3(11),
O => \i__carry__0_i_7__0_n_0\
);
\i__carry__0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__1_n_6\,
I1 => \rgb_blur3_inferred__4/i___0_carry__1_n_7\,
O => \i__carry__0_i_8_n_0\
);
\i__carry__0_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(9),
I1 => rgb_blur3(8),
O => \i__carry__0_i_8__0_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__4_n_4\,
I1 => \rgb_blur3_inferred__4/i___0_carry__4_n_5\,
O => \i__carry__1_i_1_n_0\
);
\i__carry__1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(22),
I1 => rgb_blur3(23),
O => \i__carry__1_i_1__0_n_0\
);
\i__carry__1_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(15),
I1 => \B[7]__5\(7),
O => \i__carry__1_i_1__1_n_0\
);
\i__carry__1_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(23),
I1 => \B[7]__9\(7),
O => \i__carry__1_i_1__2_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__4_n_6\,
I1 => \rgb_blur3_inferred__4/i___0_carry__4_n_7\,
O => \i__carry__1_i_2_n_0\
);
\i__carry__1_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(20),
I1 => rgb_blur3(21),
O => \i__carry__1_i_2__0_n_0\
);
\i__carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__3_n_4\,
I1 => \rgb_blur3_inferred__4/i___0_carry__3_n_5\,
O => \i__carry__1_i_3_n_0\
);
\i__carry__1_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(18),
I1 => rgb_blur3(19),
O => \i__carry__1_i_3__0_n_0\
);
\i__carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__3_n_6\,
I1 => \rgb_blur3_inferred__4/i___0_carry__3_n_7\,
O => \i__carry__1_i_4_n_0\
);
\i__carry__1_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(16),
I1 => rgb_blur3(17),
O => \i__carry__1_i_4__0_n_0\
);
\i__carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__4_n_5\,
I1 => \rgb_blur3_inferred__4/i___0_carry__4_n_4\,
O => \i__carry__1_i_5_n_0\
);
\i__carry__1_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(23),
I1 => rgb_blur3(22),
O => \i__carry__1_i_5__0_n_0\
);
\i__carry__1_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__4_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry__4_n_6\,
O => \i__carry__1_i_6_n_0\
);
\i__carry__1_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(21),
I1 => rgb_blur3(20),
O => \i__carry__1_i_6__0_n_0\
);
\i__carry__1_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__3_n_5\,
I1 => \rgb_blur3_inferred__4/i___0_carry__3_n_4\,
O => \i__carry__1_i_7_n_0\
);
\i__carry__1_i_7__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(19),
I1 => rgb_blur3(18),
O => \i__carry__1_i_7__0_n_0\
);
\i__carry__1_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__3_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry__3_n_6\,
O => \i__carry__1_i_8_n_0\
);
\i__carry__1_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(17),
I1 => rgb_blur3(16),
O => \i__carry__1_i_8__0_n_0\
);
\i__carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rgb_blur3(30),
I1 => rgb_blur3(31),
O => \i__carry__2_i_1_n_0\
);
\i__carry__2_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_5\,
I1 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
O => \i__carry__2_i_1__0_n_0\
);
\i__carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_6\,
I1 => \rgb_blur3_inferred__4/i___0_carry__6_n_7\,
O => \i__carry__2_i_2_n_0\
);
\i__carry__2_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(28),
I1 => rgb_blur3(29),
O => \i__carry__2_i_2__0_n_0\
);
\i__carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__5_n_5\,
I1 => \rgb_blur3_inferred__4/i___0_carry__5_n_4\,
O => \i__carry__2_i_3_n_0\
);
\i__carry__2_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(26),
I1 => rgb_blur3(27),
O => \i__carry__2_i_3__0_n_0\
);
\i__carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__5_n_6\,
I1 => \rgb_blur3_inferred__4/i___0_carry__5_n_7\,
O => \i__carry__2_i_4_n_0\
);
\i__carry__2_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(24),
I1 => rgb_blur3(25),
O => \i__carry__2_i_4__0_n_0\
);
\i__carry__2_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
I1 => \rgb_blur3_inferred__4/i___0_carry__6_n_5\,
O => \i__carry__2_i_5_n_0\
);
\i__carry__2_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(30),
I1 => rgb_blur3(31),
O => \i__carry__2_i_5__0_n_0\
);
\i__carry__2_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry__6_n_6\,
O => \i__carry__2_i_6_n_0\
);
\i__carry__2_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(29),
I1 => rgb_blur3(28),
O => \i__carry__2_i_6__0_n_0\
);
\i__carry__2_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__5_n_4\,
I1 => \rgb_blur3_inferred__4/i___0_carry__5_n_5\,
O => \i__carry__2_i_7_n_0\
);
\i__carry__2_i_7__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(27),
I1 => rgb_blur3(26),
O => \i__carry__2_i_7__0_n_0\
);
\i__carry__2_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__5_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry__5_n_6\,
O => \i__carry__2_i_8_n_0\
);
\i__carry__2_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(25),
I1 => rgb_blur3(24),
O => \i__carry__2_i_8__0_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_5\,
I1 => \rgb_blur3_inferred__4/i___0_carry__0_n_4\,
O => \i__carry_i_1_n_0\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(6),
I1 => rgb_blur3(7),
O => \i__carry_i_1__0_n_0\
);
\i__carry_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(10),
I1 => \B[7]__5\(2),
O => \i__carry_i_1__1_n_0\
);
\i__carry_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(18),
I1 => \B[7]__9\(2),
O => \i__carry_i_1__2_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry__0_n_6\,
O => \i__carry_i_2_n_0\
);
\i__carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(4),
I1 => rgb_blur3(5),
O => \i__carry_i_2__0_n_0\
);
\i__carry_i_2__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(9),
I1 => \B[7]__5\(1),
O => \i__carry_i_2__1_n_0\
);
\i__carry_i_2__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(17),
I1 => \B[7]__9\(1),
O => \i__carry_i_2__2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry_n_5\,
I1 => \rgb_blur3_inferred__4/i___0_carry_n_4\,
O => \i__carry_i_3_n_0\
);
\i__carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(2),
I1 => rgb_blur3(3),
O => \i__carry_i_3__0_n_0\
);
\i__carry_i_3__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(8),
I1 => \B[7]__5\(0),
O => \i__carry_i_3__1_n_0\
);
\i__carry_i_3__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(16),
I1 => \B[7]__9\(0),
O => \i__carry_i_3__2_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry_n_6\,
I1 => \rgb_blur3_inferred__4/i___0_carry_n_7\,
O => \i__carry_i_4_n_0\
);
\i__carry_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb_blur3(0),
I1 => rgb_blur3(1),
O => \i__carry_i_4__0_n_0\
);
\i__carry_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_4\,
I1 => \rgb_blur3_inferred__4/i___0_carry__0_n_5\,
O => \i__carry_i_5_n_0\
);
\i__carry_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(7),
I1 => rgb_blur3(6),
O => \i__carry_i_5__0_n_0\
);
\i__carry_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_6\,
I1 => \rgb_blur3_inferred__4/i___0_carry__0_n_7\,
O => \i__carry_i_6_n_0\
);
\i__carry_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(5),
I1 => rgb_blur3(4),
O => \i__carry_i_6__0_n_0\
);
\i__carry_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry_n_4\,
I1 => \rgb_blur3_inferred__4/i___0_carry_n_5\,
O => \i__carry_i_7_n_0\
);
\i__carry_i_7__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(3),
I1 => rgb_blur3(2),
O => \i__carry_i_7__0_n_0\
);
\i__carry_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry_n_6\,
O => \i__carry_i_8_n_0\
);
\i__carry_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(1),
I1 => rgb_blur3(0),
O => \i__carry_i_8__0_n_0\
);
\rgb_blur3__24_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3__24_carry_n_0\,
CO(2) => \rgb_blur3__24_carry_n_1\,
CO(1) => \rgb_blur3__24_carry_n_2\,
CO(0) => \rgb_blur3__24_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => D(2 downto 0),
DI(0) => '0',
O(3) => \rgb_blur3__24_carry_n_4\,
O(2) => \rgb_blur3__24_carry_n_5\,
O(1) => \rgb_blur3__24_carry_n_6\,
O(0) => \rgb_blur3__24_carry_n_7\,
S(3) => \rgb_blur3__24_carry_i_1_n_0\,
S(2) => \rgb_blur3__24_carry_i_2_n_0\,
S(1) => \rgb_blur3__24_carry_i_3_n_0\,
S(0) => \rgb_blur3__24_carry_i_4_n_0\
);
\rgb_blur3__24_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3__24_carry_n_0\,
CO(3) => \rgb_blur3__24_carry__0_n_0\,
CO(2) => \rgb_blur3__24_carry__0_n_1\,
CO(1) => \rgb_blur3__24_carry__0_n_2\,
CO(0) => \rgb_blur3__24_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => D(6 downto 3),
O(3) => \rgb_blur3__24_carry__0_n_4\,
O(2) => \rgb_blur3__24_carry__0_n_5\,
O(1) => \rgb_blur3__24_carry__0_n_6\,
O(0) => \rgb_blur3__24_carry__0_n_7\,
S(3) => \rgb_blur3__24_carry__0_i_1_n_0\,
S(2) => \rgb_blur3__24_carry__0_i_2_n_0\,
S(1) => \rgb_blur3__24_carry__0_i_3_n_0\,
S(0) => \rgb_blur3__24_carry__0_i_4_n_0\
);
\rgb_blur3__24_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(6),
I1 => \rgb_blur3_carry__1_n_7\,
O => \rgb_blur3__24_carry__0_i_1_n_0\
);
\rgb_blur3__24_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(5),
I1 => \rgb_blur3_carry__0_n_4\,
O => \rgb_blur3__24_carry__0_i_2_n_0\
);
\rgb_blur3__24_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(4),
I1 => \rgb_blur3_carry__0_n_5\,
O => \rgb_blur3__24_carry__0_i_3_n_0\
);
\rgb_blur3__24_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(3),
I1 => \rgb_blur3_carry__0_n_6\,
O => \rgb_blur3__24_carry__0_i_4_n_0\
);
\rgb_blur3__24_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3__24_carry__0_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3__24_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3__24_carry__1_n_2\,
CO(0) => \NLW_rgb_blur3__24_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => D(7),
O(3 downto 1) => \NLW_rgb_blur3__24_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3__24_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \rgb_blur3__24_carry__1_i_1_n_0\
);
\rgb_blur3__24_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(7),
I1 => \rgb_blur3_carry__1_n_2\,
O => \rgb_blur3__24_carry__1_i_1_n_0\
);
\rgb_blur3__24_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(2),
I1 => \rgb_blur3_carry__0_n_7\,
O => \rgb_blur3__24_carry_i_1_n_0\
);
\rgb_blur3__24_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(1),
I1 => rgb_blur3_carry_n_4,
O => \rgb_blur3__24_carry_i_2_n_0\
);
\rgb_blur3__24_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => D(0),
I1 => rgb_blur3_carry_n_5,
O => \rgb_blur3__24_carry_i_3_n_0\
);
\rgb_blur3__24_carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb_blur3_carry_n_6,
O => \rgb_blur3__24_carry_i_4_n_0\
);
\rgb_blur3__50_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3__50_carry_n_0\,
CO(2) => \rgb_blur3__50_carry_n_1\,
CO(1) => \rgb_blur3__50_carry_n_2\,
CO(0) => \rgb_blur3__50_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb_blur9(2 downto 0),
DI(0) => '0',
O(3 downto 1) => C(3 downto 1),
O(0) => \NLW_rgb_blur3__50_carry_O_UNCONNECTED\(0),
S(3) => \rgb_blur3__50_carry_i_1_n_0\,
S(2) => \rgb_blur3__50_carry_i_2_n_0\,
S(1) => \rgb_blur3__50_carry_i_3_n_0\,
S(0) => '0'
);
\rgb_blur3__50_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3__50_carry_n_0\,
CO(3) => \rgb_blur3__50_carry__0_n_0\,
CO(2) => \rgb_blur3__50_carry__0_n_1\,
CO(1) => \rgb_blur3__50_carry__0_n_2\,
CO(0) => \rgb_blur3__50_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb_blur9(6 downto 3),
O(3 downto 0) => C(7 downto 4),
S(3) => \rgb_blur3__50_carry__0_i_1_n_0\,
S(2) => \rgb_blur3__50_carry__0_i_2_n_0\,
S(1) => \rgb_blur3__50_carry__0_i_3_n_0\,
S(0) => \rgb_blur3__50_carry__0_i_4_n_0\
);
\rgb_blur3__50_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur9(6),
I1 => \rgb_blur3__24_carry__0_n_5\,
O => \rgb_blur3__50_carry__0_i_1_n_0\
);
\rgb_blur3__50_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur9(5),
I1 => \rgb_blur3__24_carry__0_n_6\,
O => \rgb_blur3__50_carry__0_i_2_n_0\
);
\rgb_blur3__50_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur9(4),
I1 => \rgb_blur3__24_carry__0_n_7\,
O => \rgb_blur3__50_carry__0_i_3_n_0\
);
\rgb_blur3__50_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur9(3),
I1 => \rgb_blur3__24_carry_n_4\,
O => \rgb_blur3__50_carry__0_i_4_n_0\
);
\rgb_blur3__50_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3__50_carry__0_n_0\,
CO(3) => \rgb_blur3__50_carry__1_n_0\,
CO(2) => \rgb_blur3__50_carry__1_n_1\,
CO(1) => \rgb_blur3__50_carry__1_n_2\,
CO(0) => \rgb_blur3__50_carry__1_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur3__24_carry__1_n_2\,
DI(2) => \rgb_blur3__24_carry__1_n_7\,
DI(1) => \rgb_blur3__50_carry__1_i_1_n_0\,
DI(0) => rgb_blur9(7),
O(3 downto 0) => C(11 downto 8),
S(3) => \rgb_blur3__50_carry__1_i_2_n_0\,
S(2) => \rgb_blur3__50_carry__1_i_3_n_0\,
S(1) => \rgb_blur3__50_carry__1_i_4_n_0\,
S(0) => \rgb_blur3__50_carry__1_i_5_n_0\
);
\rgb_blur3__50_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3__24_carry__1_n_7\,
O => \rgb_blur3__50_carry__1_i_1_n_0\
);
\rgb_blur3__50_carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3__24_carry__1_n_2\,
O => \rgb_blur3__50_carry__1_i_2_n_0\
);
\rgb_blur3__50_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb_blur3__24_carry__1_n_7\,
I1 => \rgb_blur3__24_carry__1_n_2\,
O => \rgb_blur3__50_carry__1_i_3_n_0\
);
\rgb_blur3__50_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3__24_carry__1_n_7\,
O => \rgb_blur3__50_carry__1_i_4_n_0\
);
\rgb_blur3__50_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur9(7),
I1 => \rgb_blur3__24_carry__0_n_4\,
O => \rgb_blur3__50_carry__1_i_5_n_0\
);
\rgb_blur3__50_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur9(2),
I1 => \rgb_blur3__24_carry_n_5\,
O => \rgb_blur3__50_carry_i_1_n_0\
);
\rgb_blur3__50_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur9(1),
I1 => \rgb_blur3__24_carry_n_6\,
O => \rgb_blur3__50_carry_i_2_n_0\
);
\rgb_blur3__50_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur9(0),
I1 => \rgb_blur3__24_carry_n_7\,
O => \rgb_blur3__50_carry_i_3_n_0\
);
\rgb_blur3__82_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3__82_carry_n_0\,
CO(2) => \rgb_blur3__82_carry_n_1\,
CO(1) => \rgb_blur3__82_carry_n_2\,
CO(0) => \rgb_blur3__82_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb_blur11(2 downto 0),
DI(0) => '0',
O(3) => \rgb_blur3__82_carry_n_4\,
O(2) => \rgb_blur3__82_carry_n_5\,
O(1) => \rgb_blur3__82_carry_n_6\,
O(0) => \NLW_rgb_blur3__82_carry_O_UNCONNECTED\(0),
S(3) => \rgb_blur3__82_carry_i_1_n_0\,
S(2) => \rgb_blur3__82_carry_i_2_n_0\,
S(1) => \rgb_blur3__82_carry_i_3_n_0\,
S(0) => '0'
);
\rgb_blur3__82_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3__82_carry_n_0\,
CO(3) => \rgb_blur3__82_carry__0_n_0\,
CO(2) => \rgb_blur3__82_carry__0_n_1\,
CO(1) => \rgb_blur3__82_carry__0_n_2\,
CO(0) => \rgb_blur3__82_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb_blur11(6 downto 3),
O(3) => \rgb_blur3__82_carry__0_n_4\,
O(2) => \rgb_blur3__82_carry__0_n_5\,
O(1) => \rgb_blur3__82_carry__0_n_6\,
O(0) => \rgb_blur3__82_carry__0_n_7\,
S(3) => \rgb_blur3__82_carry__0_i_1_n_0\,
S(2) => \rgb_blur3__82_carry__0_i_2_n_0\,
S(1) => \rgb_blur3__82_carry__0_i_3_n_0\,
S(0) => \rgb_blur3__82_carry__0_i_4_n_0\
);
\rgb_blur3__82_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur11(6),
I1 => C(7),
O => \rgb_blur3__82_carry__0_i_1_n_0\
);
\rgb_blur3__82_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur11(5),
I1 => C(6),
O => \rgb_blur3__82_carry__0_i_2_n_0\
);
\rgb_blur3__82_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur11(4),
I1 => C(5),
O => \rgb_blur3__82_carry__0_i_3_n_0\
);
\rgb_blur3__82_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur11(3),
I1 => C(4),
O => \rgb_blur3__82_carry__0_i_4_n_0\
);
\rgb_blur3__82_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3__82_carry__0_n_0\,
CO(3) => \rgb_blur3__82_carry__1_n_0\,
CO(2) => \rgb_blur3__82_carry__1_n_1\,
CO(1) => \rgb_blur3__82_carry__1_n_2\,
CO(0) => \rgb_blur3__82_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 2) => C(10 downto 9),
DI(1) => \rgb_blur3__82_carry__1_i_1_n_0\,
DI(0) => rgb_blur11(7),
O(3) => \rgb_blur3__82_carry__1_n_4\,
O(2) => \rgb_blur3__82_carry__1_n_5\,
O(1) => \rgb_blur3__82_carry__1_n_6\,
O(0) => \rgb_blur3__82_carry__1_n_7\,
S(3) => \rgb_blur3__82_carry__1_i_2_n_0\,
S(2) => \rgb_blur3__82_carry__1_i_3_n_0\,
S(1) => \rgb_blur3__82_carry__1_i_4_n_0\,
S(0) => \rgb_blur3__82_carry__1_i_5_n_0\
);
\rgb_blur3__82_carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => C(9),
O => \rgb_blur3__82_carry__1_i_1_n_0\
);
\rgb_blur3__82_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => C(10),
I1 => C(11),
O => \rgb_blur3__82_carry__1_i_2_n_0\
);
\rgb_blur3__82_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => C(9),
I1 => C(10),
O => \rgb_blur3__82_carry__1_i_3_n_0\
);
\rgb_blur3__82_carry__1_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => C(9),
O => \rgb_blur3__82_carry__1_i_4_n_0\
);
\rgb_blur3__82_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur11(7),
I1 => C(8),
O => \rgb_blur3__82_carry__1_i_5_n_0\
);
\rgb_blur3__82_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3__82_carry__1_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3__82_carry__2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3__82_carry__2_n_2\,
CO(0) => \NLW_rgb_blur3__82_carry__2_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => C(11),
O(3 downto 1) => \NLW_rgb_blur3__82_carry__2_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3__82_carry__2_n_7\,
S(3 downto 1) => B"001",
S(0) => \rgb_blur3__82_carry__2_i_1_n_0\
);
\rgb_blur3__82_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => C(11),
I1 => \rgb_blur3__82_carry__2_i_2_n_3\,
O => \rgb_blur3__82_carry__2_i_1_n_0\
);
\rgb_blur3__82_carry__2_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3__50_carry__1_n_0\,
CO(3 downto 1) => \NLW_rgb_blur3__82_carry__2_i_2_CO_UNCONNECTED\(3 downto 1),
CO(0) => \rgb_blur3__82_carry__2_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_rgb_blur3__82_carry__2_i_2_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => B"0001"
);
\rgb_blur3__82_carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur11(2),
I1 => C(3),
O => \rgb_blur3__82_carry_i_1_n_0\
);
\rgb_blur3__82_carry_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur11(1),
I1 => C(2),
O => \rgb_blur3__82_carry_i_2_n_0\
);
\rgb_blur3__82_carry_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb_blur11(0),
I1 => C(1),
O => \rgb_blur3__82_carry_i_3_n_0\
);
rgb_blur3_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => rgb_blur3_carry_n_0,
CO(2) => rgb_blur3_carry_n_1,
CO(1) => rgb_blur3_carry_n_2,
CO(0) => rgb_blur3_carry_n_3,
CYINIT => '0',
DI(3 downto 1) => \rgb_buffer_reg[642]\(2 downto 0),
DI(0) => '0',
O(3) => rgb_blur3_carry_n_4,
O(2) => rgb_blur3_carry_n_5,
O(1) => rgb_blur3_carry_n_6,
O(0) => NLW_rgb_blur3_carry_O_UNCONNECTED(0),
S(3) => rgb_blur3_carry_i_1_n_0,
S(2) => rgb_blur3_carry_i_2_n_0,
S(1) => rgb_blur3_carry_i_3_n_0,
S(0) => '0'
);
\rgb_blur3_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => rgb_blur3_carry_n_0,
CO(3) => \rgb_blur3_carry__0_n_0\,
CO(2) => \rgb_blur3_carry__0_n_1\,
CO(1) => \rgb_blur3_carry__0_n_2\,
CO(0) => \rgb_blur3_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \rgb_buffer_reg[642]\(6 downto 3),
O(3) => \rgb_blur3_carry__0_n_4\,
O(2) => \rgb_blur3_carry__0_n_5\,
O(1) => \rgb_blur3_carry__0_n_6\,
O(0) => \rgb_blur3_carry__0_n_7\,
S(3) => \rgb_blur3_carry__0_i_1_n_0\,
S(2) => \rgb_blur3_carry__0_i_2_n_0\,
S(1) => \rgb_blur3_carry__0_i_3_n_0\,
S(0) => \rgb_blur3_carry__0_i_4_n_0\
);
\rgb_blur3_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(6),
I1 => \B[7]__1\(6),
O => \rgb_blur3_carry__0_i_1_n_0\
);
\rgb_blur3_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(5),
I1 => \B[7]__1\(5),
O => \rgb_blur3_carry__0_i_2_n_0\
);
\rgb_blur3_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(4),
I1 => \B[7]__1\(4),
O => \rgb_blur3_carry__0_i_3_n_0\
);
\rgb_blur3_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(3),
I1 => \B[7]__1\(3),
O => \rgb_blur3_carry__0_i_4_n_0\
);
\rgb_blur3_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_carry__0_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_carry__1_n_2\,
CO(0) => \NLW_rgb_blur3_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \rgb_buffer_reg[642]\(7),
O(3 downto 1) => \NLW_rgb_blur3_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \rgb_blur3_carry__1_i_1_n_0\
);
\rgb_blur3_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(7),
I1 => \B[7]__1\(7),
O => \rgb_blur3_carry__1_i_1_n_0\
);
rgb_blur3_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(2),
I1 => \B[7]__1\(2),
O => rgb_blur3_carry_i_1_n_0
);
rgb_blur3_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(1),
I1 => \B[7]__1\(1),
O => rgb_blur3_carry_i_2_n_0
);
rgb_blur3_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb_buffer_reg[642]\(0),
I1 => \B[7]__1\(0),
O => rgb_blur3_carry_i_3_n_0
);
\rgb_blur3_inferred__0/i___0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__0/i___0_carry_n_0\,
CO(2) => \rgb_blur3_inferred__0/i___0_carry_n_1\,
CO(1) => \rgb_blur3_inferred__0/i___0_carry_n_2\,
CO(0) => \rgb_blur3_inferred__0/i___0_carry_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry_i_1_n_0\,
DI(2) => \i___0_carry_i_2_n_0\,
DI(1) => \i___0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \rgb_blur3_inferred__0/i___0_carry_n_4\,
O(2) => \rgb_blur3_inferred__0/i___0_carry_n_5\,
O(1) => \rgb_blur3_inferred__0/i___0_carry_n_6\,
O(0) => \rgb_blur3_inferred__0/i___0_carry_n_7\,
S(3) => \i___0_carry_i_4_n_0\,
S(2) => \i___0_carry_i_5_n_0\,
S(1) => \i___0_carry_i_6_n_0\,
S(0) => \i___0_carry_i_7_n_0\
);
\rgb_blur3_inferred__0/i___0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__0/i___0_carry_n_0\,
CO(3) => \rgb_blur3_inferred__0/i___0_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__0/i___0_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__0/i___0_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__0/i___0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry__0_i_1_n_0\,
DI(2) => \i___0_carry__0_i_2_n_0\,
DI(1) => \i___0_carry__0_i_3_n_0\,
DI(0) => \i___0_carry__0_i_4_n_0\,
O(3) => \rgb_blur3_inferred__0/i___0_carry__0_n_4\,
O(2) => \rgb_blur3_inferred__0/i___0_carry__0_n_5\,
O(1) => \rgb_blur3_inferred__0/i___0_carry__0_n_6\,
O(0) => \rgb_blur3_inferred__0/i___0_carry__0_n_7\,
S(3) => \i___0_carry__0_i_5_n_0\,
S(2) => \i___0_carry__0_i_6_n_0\,
S(1) => \i___0_carry__0_i_7_n_0\,
S(0) => \i___0_carry__0_i_8_n_0\
);
\rgb_blur3_inferred__0/i___0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__0/i___0_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__0/i___0_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__0/i___0_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__0/i___0_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__0/i___0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur3__82_carry__1_n_5\,
DI(2) => \rgb_blur3__82_carry__1_n_6\,
DI(1) => '1',
DI(0) => \rgb_blur3__82_carry__1_n_7\,
O(3) => \rgb_blur3_inferred__0/i___0_carry__1_n_4\,
O(2) => \rgb_blur3_inferred__0/i___0_carry__1_n_5\,
O(1) => \rgb_blur3_inferred__0/i___0_carry__1_n_6\,
O(0) => \rgb_blur3_inferred__0/i___0_carry__1_n_7\,
S(3) => \i___0_carry__1_i_1_n_0\,
S(2) => \i___0_carry__1_i_2_n_0\,
S(1) => \i___0_carry__1_i_3_n_0\,
S(0) => \i___0_carry__1_i_4_n_0\
);
\rgb_blur3_inferred__0/i___0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__0/i___0_carry__1_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__0/i___0_carry__2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__0/i___0_carry__2_n_2\,
CO(0) => \rgb_blur3_inferred__0/i___0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb_blur3__82_carry__2_n_7\,
DI(0) => \rgb_blur3__82_carry__1_n_4\,
O(3) => \NLW_rgb_blur3_inferred__0/i___0_carry__2_O_UNCONNECTED\(3),
O(2) => \rgb_blur3_inferred__0/i___0_carry__2_n_5\,
O(1) => \rgb_blur3_inferred__0/i___0_carry__2_n_6\,
O(0) => \rgb_blur3_inferred__0/i___0_carry__2_n_7\,
S(3 downto 2) => B"01",
S(1) => \i___0_carry__2_i_1_n_0\,
S(0) => \i___0_carry__2_i_2_n_0\
);
\rgb_blur3_inferred__1/i___0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__1/i___0_carry_n_0\,
CO(2) => \rgb_blur3_inferred__1/i___0_carry_n_1\,
CO(1) => \rgb_blur3_inferred__1/i___0_carry_n_2\,
CO(0) => \rgb_blur3_inferred__1/i___0_carry_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry_i_1__0_n_0\,
DI(2) => \i___0_carry_i_2__0_n_0\,
DI(1) => \i___0_carry_i_3__0_n_0\,
DI(0) => '0',
O(3) => \rgb_blur3_inferred__1/i___0_carry_n_4\,
O(2) => \rgb_blur3_inferred__1/i___0_carry_n_5\,
O(1) => \rgb_blur3_inferred__1/i___0_carry_n_6\,
O(0) => \rgb_blur3_inferred__1/i___0_carry_n_7\,
S(3) => \i___0_carry_i_4__0_n_0\,
S(2) => \i___0_carry_i_5__0_n_0\,
S(1) => \i___0_carry_i_6__0_n_0\,
S(0) => \i___0_carry_i_7__0_n_0\
);
\rgb_blur3_inferred__1/i___0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__1/i___0_carry_n_0\,
CO(3) => \rgb_blur3_inferred__1/i___0_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__1/i___0_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__1/i___0_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__1/i___0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry__0_i_1__0_n_0\,
DI(2) => \i___0_carry__0_i_2__0_n_0\,
DI(1) => \i___0_carry__0_i_3__0_n_0\,
DI(0) => \i___0_carry__0_i_4__0_n_0\,
O(3) => \rgb_blur3_inferred__1/i___0_carry__0_n_4\,
O(2) => \rgb_blur3_inferred__1/i___0_carry__0_n_5\,
O(1) => \rgb_blur3_inferred__1/i___0_carry__0_n_6\,
O(0) => \rgb_blur3_inferred__1/i___0_carry__0_n_7\,
S(3) => \i___0_carry__0_i_5__0_n_0\,
S(2) => \i___0_carry__0_i_6__0_n_0\,
S(1) => \i___0_carry__0_i_7__0_n_0\,
S(0) => \i___0_carry__0_i_8__0_n_0\
);
\rgb_blur3_inferred__1/i___0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__1/i___0_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__1/i___0_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__1/i___0_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__1/i___0_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__1/i___0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \rgb_blur3_inferred__0/i___0_carry__1_n_7\,
O(3) => \rgb_blur3_inferred__1/i___0_carry__1_n_4\,
O(2) => \rgb_blur3_inferred__1/i___0_carry__1_n_5\,
O(1) => \rgb_blur3_inferred__1/i___0_carry__1_n_6\,
O(0) => \rgb_blur3_inferred__1/i___0_carry__1_n_7\,
S(3) => \i___0_carry__1_i_1__2_n_0\,
S(2) => \i___0_carry__1_i_2__2_n_0\,
S(1) => \i___0_carry__1_i_3__0_n_0\,
S(0) => \i___0_carry__1_i_4__0_n_0\
);
\rgb_blur3_inferred__1/i___0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__1/i___0_carry__1_n_0\,
CO(3) => \rgb_blur3_inferred__1/i___0_carry__2_n_0\,
CO(2) => \rgb_blur3_inferred__1/i___0_carry__2_n_1\,
CO(1) => \rgb_blur3_inferred__1/i___0_carry__2_n_2\,
CO(0) => \rgb_blur3_inferred__1/i___0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__1/i___0_carry__2_n_4\,
O(2) => \rgb_blur3_inferred__1/i___0_carry__2_n_5\,
O(1) => \rgb_blur3_inferred__1/i___0_carry__2_n_6\,
O(0) => \rgb_blur3_inferred__1/i___0_carry__2_n_7\,
S(3) => \i___0_carry__2_i_1__2_n_0\,
S(2) => \i___0_carry__2_i_2__2_n_0\,
S(1) => \i___0_carry__2_i_3_n_0\,
S(0) => \i___0_carry__2_i_4_n_0\
);
\rgb_blur3_inferred__1/i___0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__1/i___0_carry__2_n_0\,
CO(3) => \rgb_blur3_inferred__1/i___0_carry__3_n_0\,
CO(2) => \rgb_blur3_inferred__1/i___0_carry__3_n_1\,
CO(1) => \rgb_blur3_inferred__1/i___0_carry__3_n_2\,
CO(0) => \rgb_blur3_inferred__1/i___0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__1/i___0_carry__3_n_4\,
O(2) => \rgb_blur3_inferred__1/i___0_carry__3_n_5\,
O(1) => \rgb_blur3_inferred__1/i___0_carry__3_n_6\,
O(0) => \rgb_blur3_inferred__1/i___0_carry__3_n_7\,
S(3) => \i___0_carry__3_i_1_n_0\,
S(2) => \i___0_carry__3_i_2_n_0\,
S(1) => \i___0_carry__3_i_3_n_0\,
S(0) => \i___0_carry__3_i_4_n_0\
);
\rgb_blur3_inferred__1/i___0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__1/i___0_carry__3_n_0\,
CO(3) => \rgb_blur3_inferred__1/i___0_carry__4_n_0\,
CO(2) => \rgb_blur3_inferred__1/i___0_carry__4_n_1\,
CO(1) => \rgb_blur3_inferred__1/i___0_carry__4_n_2\,
CO(0) => \rgb_blur3_inferred__1/i___0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__1/i___0_carry__4_n_4\,
O(2) => \rgb_blur3_inferred__1/i___0_carry__4_n_5\,
O(1) => \rgb_blur3_inferred__1/i___0_carry__4_n_6\,
O(0) => \rgb_blur3_inferred__1/i___0_carry__4_n_7\,
S(3) => \i___0_carry__4_i_1_n_0\,
S(2) => \i___0_carry__4_i_2_n_0\,
S(1) => \i___0_carry__4_i_3_n_0\,
S(0) => \i___0_carry__4_i_4_n_0\
);
\rgb_blur3_inferred__1/i___0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__1/i___0_carry__4_n_0\,
CO(3) => \rgb_blur3_inferred__1/i___0_carry__5_n_0\,
CO(2) => \rgb_blur3_inferred__1/i___0_carry__5_n_1\,
CO(1) => \rgb_blur3_inferred__1/i___0_carry__5_n_2\,
CO(0) => \rgb_blur3_inferred__1/i___0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__1/i___0_carry__5_n_4\,
O(2) => \rgb_blur3_inferred__1/i___0_carry__5_n_5\,
O(1) => \rgb_blur3_inferred__1/i___0_carry__5_n_6\,
O(0) => \rgb_blur3_inferred__1/i___0_carry__5_n_7\,
S(3) => \i___0_carry__5_i_1_n_0\,
S(2) => \i___0_carry__5_i_2_n_0\,
S(1) => \i___0_carry__5_i_3_n_0\,
S(0) => \i___0_carry__5_i_4_n_0\
);
\rgb_blur3_inferred__1/i___0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__1/i___0_carry__5_n_0\,
CO(3) => \NLW_rgb_blur3_inferred__1/i___0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \rgb_blur3_inferred__1/i___0_carry__6_n_1\,
CO(1) => \rgb_blur3_inferred__1/i___0_carry__6_n_2\,
CO(0) => \rgb_blur3_inferred__1/i___0_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
O(2) => \rgb_blur3_inferred__1/i___0_carry__6_n_5\,
O(1) => \rgb_blur3_inferred__1/i___0_carry__6_n_6\,
O(0) => \rgb_blur3_inferred__1/i___0_carry__6_n_7\,
S(3) => \i___0_carry__6_i_1_n_0\,
S(2) => \i___0_carry__6_i_2_n_0\,
S(1) => \i___0_carry__6_i_3_n_0\,
S(0) => \i___0_carry__6_i_4_n_0\
);
\rgb_blur3_inferred__2/i___24_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__2/i___24_carry_n_0\,
CO(2) => \rgb_blur3_inferred__2/i___24_carry_n_1\,
CO(1) => \rgb_blur3_inferred__2/i___24_carry_n_2\,
CO(0) => \rgb_blur3_inferred__2/i___24_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => D(10 downto 8),
DI(0) => '0',
O(3) => \rgb_blur3_inferred__2/i___24_carry_n_4\,
O(2) => \rgb_blur3_inferred__2/i___24_carry_n_5\,
O(1) => \rgb_blur3_inferred__2/i___24_carry_n_6\,
O(0) => \rgb_blur3_inferred__2/i___24_carry_n_7\,
S(3) => \i___24_carry_i_1_n_0\,
S(2) => \i___24_carry_i_2_n_0\,
S(1) => \i___24_carry_i_3_n_0\,
S(0) => \i___24_carry_i_4_n_0\
);
\rgb_blur3_inferred__2/i___24_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i___24_carry_n_0\,
CO(3) => \rgb_blur3_inferred__2/i___24_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__2/i___24_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__2/i___24_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__2/i___24_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => D(14 downto 11),
O(3) => \rgb_blur3_inferred__2/i___24_carry__0_n_4\,
O(2) => \rgb_blur3_inferred__2/i___24_carry__0_n_5\,
O(1) => \rgb_blur3_inferred__2/i___24_carry__0_n_6\,
O(0) => \rgb_blur3_inferred__2/i___24_carry__0_n_7\,
S(3) => \i___24_carry__0_i_1_n_0\,
S(2) => \i___24_carry__0_i_2_n_0\,
S(1) => \i___24_carry__0_i_3_n_0\,
S(0) => \i___24_carry__0_i_4_n_0\
);
\rgb_blur3_inferred__2/i___24_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i___24_carry__0_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__2/i___24_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__2/i___24_carry__1_n_2\,
CO(0) => \NLW_rgb_blur3_inferred__2/i___24_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => D(15),
O(3 downto 1) => \NLW_rgb_blur3_inferred__2/i___24_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3_inferred__2/i___24_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \i___24_carry__1_i_1_n_0\
);
\rgb_blur3_inferred__2/i___50_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__2/i___50_carry_n_0\,
CO(2) => \rgb_blur3_inferred__2/i___50_carry_n_1\,
CO(1) => \rgb_blur3_inferred__2/i___50_carry_n_2\,
CO(0) => \rgb_blur3_inferred__2/i___50_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => I6(2 downto 0),
DI(0) => '0',
O(3 downto 1) => \C__0\(3 downto 1),
O(0) => \NLW_rgb_blur3_inferred__2/i___50_carry_O_UNCONNECTED\(0),
S(3) => \i___50_carry_i_1_n_0\,
S(2) => \i___50_carry_i_2_n_0\,
S(1) => \i___50_carry_i_3_n_0\,
S(0) => '0'
);
\rgb_blur3_inferred__2/i___50_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i___50_carry_n_0\,
CO(3) => \rgb_blur3_inferred__2/i___50_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__2/i___50_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__2/i___50_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__2/i___50_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => I6(6 downto 3),
O(3 downto 0) => \C__0\(7 downto 4),
S(3) => \i___50_carry__0_i_1_n_0\,
S(2) => \i___50_carry__0_i_2_n_0\,
S(1) => \i___50_carry__0_i_3_n_0\,
S(0) => \i___50_carry__0_i_4_n_0\
);
\rgb_blur3_inferred__2/i___50_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i___50_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__2/i___50_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__2/i___50_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__2/i___50_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__2/i___50_carry__1_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur3_inferred__2/i___24_carry__1_n_2\,
DI(2) => \rgb_blur3_inferred__2/i___24_carry__1_n_7\,
DI(1) => \i___50_carry__1_i_1_n_0\,
DI(0) => I6(7),
O(3 downto 0) => \C__0\(11 downto 8),
S(3) => \i___50_carry__1_i_2_n_0\,
S(2) => \i___50_carry__1_i_3_n_0\,
S(1) => \i___50_carry__1_i_4_n_0\,
S(0) => \i___50_carry__1_i_5_n_0\
);
\rgb_blur3_inferred__2/i___82_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__2/i___82_carry_n_0\,
CO(2) => \rgb_blur3_inferred__2/i___82_carry_n_1\,
CO(1) => \rgb_blur3_inferred__2/i___82_carry_n_2\,
CO(0) => \rgb_blur3_inferred__2/i___82_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => I7(2 downto 0),
DI(0) => '0',
O(3) => \rgb_blur3_inferred__2/i___82_carry_n_4\,
O(2) => \rgb_blur3_inferred__2/i___82_carry_n_5\,
O(1) => \rgb_blur3_inferred__2/i___82_carry_n_6\,
O(0) => \NLW_rgb_blur3_inferred__2/i___82_carry_O_UNCONNECTED\(0),
S(3) => \i___82_carry_i_1_n_0\,
S(2) => \i___82_carry_i_2_n_0\,
S(1) => \i___82_carry_i_3_n_0\,
S(0) => '0'
);
\rgb_blur3_inferred__2/i___82_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i___82_carry_n_0\,
CO(3) => \rgb_blur3_inferred__2/i___82_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__2/i___82_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__2/i___82_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__2/i___82_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => I7(6 downto 3),
O(3) => \rgb_blur3_inferred__2/i___82_carry__0_n_4\,
O(2) => \rgb_blur3_inferred__2/i___82_carry__0_n_5\,
O(1) => \rgb_blur3_inferred__2/i___82_carry__0_n_6\,
O(0) => \rgb_blur3_inferred__2/i___82_carry__0_n_7\,
S(3) => \i___82_carry__0_i_1_n_0\,
S(2) => \i___82_carry__0_i_2_n_0\,
S(1) => \i___82_carry__0_i_3_n_0\,
S(0) => \i___82_carry__0_i_4_n_0\
);
\rgb_blur3_inferred__2/i___82_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i___82_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__2/i___82_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__2/i___82_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__2/i___82_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__2/i___82_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 2) => \C__0\(10 downto 9),
DI(1) => \i___82_carry__1_i_1_n_0\,
DI(0) => I7(7),
O(3) => \rgb_blur3_inferred__2/i___82_carry__1_n_4\,
O(2) => \rgb_blur3_inferred__2/i___82_carry__1_n_5\,
O(1) => \rgb_blur3_inferred__2/i___82_carry__1_n_6\,
O(0) => \rgb_blur3_inferred__2/i___82_carry__1_n_7\,
S(3) => \i___82_carry__1_i_2_n_0\,
S(2) => \i___82_carry__1_i_3_n_0\,
S(1) => \i___82_carry__1_i_4_n_0\,
S(0) => \i___82_carry__1_i_5_n_0\
);
\rgb_blur3_inferred__2/i___82_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i___82_carry__1_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__2/i___82_carry__2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__2/i___82_carry__2_n_2\,
CO(0) => \NLW_rgb_blur3_inferred__2/i___82_carry__2_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \C__0\(11),
O(3 downto 1) => \NLW_rgb_blur3_inferred__2/i___82_carry__2_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3_inferred__2/i___82_carry__2_n_7\,
S(3 downto 1) => B"001",
S(0) => \i___82_carry__2_i_1_n_0\
);
\rgb_blur3_inferred__2/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__2/i__carry_n_0\,
CO(2) => \rgb_blur3_inferred__2/i__carry_n_1\,
CO(1) => \rgb_blur3_inferred__2/i__carry_n_2\,
CO(0) => \rgb_blur3_inferred__2/i__carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb_buffer_reg[642]\(10 downto 8),
DI(0) => '0',
O(3) => \rgb_blur3_inferred__2/i__carry_n_4\,
O(2) => \rgb_blur3_inferred__2/i__carry_n_5\,
O(1) => \rgb_blur3_inferred__2/i__carry_n_6\,
O(0) => \NLW_rgb_blur3_inferred__2/i__carry_O_UNCONNECTED\(0),
S(3) => \i__carry_i_1__1_n_0\,
S(2) => \i__carry_i_2__1_n_0\,
S(1) => \i__carry_i_3__1_n_0\,
S(0) => '0'
);
\rgb_blur3_inferred__2/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i__carry_n_0\,
CO(3) => \rgb_blur3_inferred__2/i__carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__2/i__carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__2/i__carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__2/i__carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \rgb_buffer_reg[642]\(14 downto 11),
O(3) => \rgb_blur3_inferred__2/i__carry__0_n_4\,
O(2) => \rgb_blur3_inferred__2/i__carry__0_n_5\,
O(1) => \rgb_blur3_inferred__2/i__carry__0_n_6\,
O(0) => \rgb_blur3_inferred__2/i__carry__0_n_7\,
S(3) => \i__carry__0_i_1__1_n_0\,
S(2) => \i__carry__0_i_2__1_n_0\,
S(1) => \i__carry__0_i_3__1_n_0\,
S(0) => \i__carry__0_i_4__1_n_0\
);
\rgb_blur3_inferred__2/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__2/i__carry__0_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__2/i__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__2/i__carry__1_n_2\,
CO(0) => \NLW_rgb_blur3_inferred__2/i__carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \rgb_buffer_reg[642]\(15),
O(3 downto 1) => \NLW_rgb_blur3_inferred__2/i__carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3_inferred__2/i__carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \i__carry__1_i_1__1_n_0\
);
\rgb_blur3_inferred__3/i___0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__3/i___0_carry_n_0\,
CO(2) => \rgb_blur3_inferred__3/i___0_carry_n_1\,
CO(1) => \rgb_blur3_inferred__3/i___0_carry_n_2\,
CO(0) => \rgb_blur3_inferred__3/i___0_carry_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry_i_1__1_n_0\,
DI(2) => \i___0_carry_i_2__1_n_0\,
DI(1) => \i___0_carry_i_3__1_n_0\,
DI(0) => '0',
O(3) => \rgb_blur3_inferred__3/i___0_carry_n_4\,
O(2) => \rgb_blur3_inferred__3/i___0_carry_n_5\,
O(1) => \rgb_blur3_inferred__3/i___0_carry_n_6\,
O(0) => \rgb_blur3_inferred__3/i___0_carry_n_7\,
S(3) => \i___0_carry_i_4__1_n_0\,
S(2) => \i___0_carry_i_5__1_n_0\,
S(1) => \i___0_carry_i_6__1_n_0\,
S(0) => \i___0_carry_i_7__1_n_0\
);
\rgb_blur3_inferred__3/i___0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__3/i___0_carry_n_0\,
CO(3) => \rgb_blur3_inferred__3/i___0_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__3/i___0_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__3/i___0_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__3/i___0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry__0_i_1__1_n_0\,
DI(2) => \i___0_carry__0_i_2__1_n_0\,
DI(1) => \i___0_carry__0_i_3__1_n_0\,
DI(0) => \i___0_carry__0_i_4__1_n_0\,
O(3) => \rgb_blur3_inferred__3/i___0_carry__0_n_4\,
O(2) => \rgb_blur3_inferred__3/i___0_carry__0_n_5\,
O(1) => \rgb_blur3_inferred__3/i___0_carry__0_n_6\,
O(0) => \rgb_blur3_inferred__3/i___0_carry__0_n_7\,
S(3) => \i___0_carry__0_i_5__1_n_0\,
S(2) => \i___0_carry__0_i_6__1_n_0\,
S(1) => \i___0_carry__0_i_7__1_n_0\,
S(0) => \i___0_carry__0_i_8__1_n_0\
);
\rgb_blur3_inferred__3/i___0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__3/i___0_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__3/i___0_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__3/i___0_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__3/i___0_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__3/i___0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur3_inferred__2/i___82_carry__1_n_5\,
DI(2) => \rgb_blur3_inferred__2/i___82_carry__1_n_6\,
DI(1) => '1',
DI(0) => \rgb_blur3_inferred__2/i___82_carry__1_n_7\,
O(3) => \rgb_blur3_inferred__3/i___0_carry__1_n_4\,
O(2) => \rgb_blur3_inferred__3/i___0_carry__1_n_5\,
O(1) => \rgb_blur3_inferred__3/i___0_carry__1_n_6\,
O(0) => \rgb_blur3_inferred__3/i___0_carry__1_n_7\,
S(3) => \i___0_carry__1_i_1__0_n_0\,
S(2) => \i___0_carry__1_i_2__0_n_0\,
S(1) => \i___0_carry__1_i_3__1_n_0\,
S(0) => \i___0_carry__1_i_4__1_n_0\
);
\rgb_blur3_inferred__3/i___0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__3/i___0_carry__1_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__3/i___0_carry__2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__3/i___0_carry__2_n_2\,
CO(0) => \rgb_blur3_inferred__3/i___0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb_blur3_inferred__2/i___82_carry__2_n_7\,
DI(0) => \rgb_blur3_inferred__2/i___82_carry__1_n_4\,
O(3) => \NLW_rgb_blur3_inferred__3/i___0_carry__2_O_UNCONNECTED\(3),
O(2) => \rgb_blur3_inferred__3/i___0_carry__2_n_5\,
O(1) => \rgb_blur3_inferred__3/i___0_carry__2_n_6\,
O(0) => \rgb_blur3_inferred__3/i___0_carry__2_n_7\,
S(3 downto 2) => B"01",
S(1) => \i___0_carry__2_i_1__0_n_0\,
S(0) => \i___0_carry__2_i_2__0_n_0\
);
\rgb_blur3_inferred__4/i___0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__4/i___0_carry_n_0\,
CO(2) => \rgb_blur3_inferred__4/i___0_carry_n_1\,
CO(1) => \rgb_blur3_inferred__4/i___0_carry_n_2\,
CO(0) => \rgb_blur3_inferred__4/i___0_carry_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry_i_1__2_n_0\,
DI(2) => \i___0_carry_i_2__2_n_0\,
DI(1) => \i___0_carry_i_3__2_n_0\,
DI(0) => '0',
O(3) => \rgb_blur3_inferred__4/i___0_carry_n_4\,
O(2) => \rgb_blur3_inferred__4/i___0_carry_n_5\,
O(1) => \rgb_blur3_inferred__4/i___0_carry_n_6\,
O(0) => \rgb_blur3_inferred__4/i___0_carry_n_7\,
S(3) => \i___0_carry_i_4__2_n_0\,
S(2) => \i___0_carry_i_5__2_n_0\,
S(1) => \i___0_carry_i_6__2_n_0\,
S(0) => \i___0_carry_i_7__2_n_0\
);
\rgb_blur3_inferred__4/i___0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__4/i___0_carry_n_0\,
CO(3) => \rgb_blur3_inferred__4/i___0_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__4/i___0_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__4/i___0_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__4/i___0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry__0_i_1__2_n_0\,
DI(2) => \i___0_carry__0_i_2__2_n_0\,
DI(1) => \i___0_carry__0_i_3__2_n_0\,
DI(0) => \i___0_carry__0_i_4__2_n_0\,
O(3) => \rgb_blur3_inferred__4/i___0_carry__0_n_4\,
O(2) => \rgb_blur3_inferred__4/i___0_carry__0_n_5\,
O(1) => \rgb_blur3_inferred__4/i___0_carry__0_n_6\,
O(0) => \rgb_blur3_inferred__4/i___0_carry__0_n_7\,
S(3) => \i___0_carry__0_i_5__2_n_0\,
S(2) => \i___0_carry__0_i_6__2_n_0\,
S(1) => \i___0_carry__0_i_7__2_n_0\,
S(0) => \i___0_carry__0_i_8__2_n_0\
);
\rgb_blur3_inferred__4/i___0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__4/i___0_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__4/i___0_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__4/i___0_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__4/i___0_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__4/i___0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \rgb_blur3_inferred__3/i___0_carry__1_n_7\,
O(3) => \rgb_blur3_inferred__4/i___0_carry__1_n_4\,
O(2) => \rgb_blur3_inferred__4/i___0_carry__1_n_5\,
O(1) => \rgb_blur3_inferred__4/i___0_carry__1_n_6\,
O(0) => \rgb_blur3_inferred__4/i___0_carry__1_n_7\,
S(3) => \i___0_carry__1_i_1__3_n_0\,
S(2) => \i___0_carry__1_i_2__3_n_0\,
S(1) => \i___0_carry__1_i_3__2_n_0\,
S(0) => \i___0_carry__1_i_4__2_n_0\
);
\rgb_blur3_inferred__4/i___0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__4/i___0_carry__1_n_0\,
CO(3) => \rgb_blur3_inferred__4/i___0_carry__2_n_0\,
CO(2) => \rgb_blur3_inferred__4/i___0_carry__2_n_1\,
CO(1) => \rgb_blur3_inferred__4/i___0_carry__2_n_2\,
CO(0) => \rgb_blur3_inferred__4/i___0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__4/i___0_carry__2_n_4\,
O(2) => \rgb_blur3_inferred__4/i___0_carry__2_n_5\,
O(1) => \rgb_blur3_inferred__4/i___0_carry__2_n_6\,
O(0) => \rgb_blur3_inferred__4/i___0_carry__2_n_7\,
S(3) => \i___0_carry__2_i_1__3_n_0\,
S(2) => \i___0_carry__2_i_2__3_n_0\,
S(1) => \i___0_carry__2_i_3__0_n_0\,
S(0) => \i___0_carry__2_i_4__0_n_0\
);
\rgb_blur3_inferred__4/i___0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__4/i___0_carry__2_n_0\,
CO(3) => \rgb_blur3_inferred__4/i___0_carry__3_n_0\,
CO(2) => \rgb_blur3_inferred__4/i___0_carry__3_n_1\,
CO(1) => \rgb_blur3_inferred__4/i___0_carry__3_n_2\,
CO(0) => \rgb_blur3_inferred__4/i___0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__4/i___0_carry__3_n_4\,
O(2) => \rgb_blur3_inferred__4/i___0_carry__3_n_5\,
O(1) => \rgb_blur3_inferred__4/i___0_carry__3_n_6\,
O(0) => \rgb_blur3_inferred__4/i___0_carry__3_n_7\,
S(3) => \i___0_carry__3_i_1__0_n_0\,
S(2) => \i___0_carry__3_i_2__0_n_0\,
S(1) => \i___0_carry__3_i_3__0_n_0\,
S(0) => \i___0_carry__3_i_4__0_n_0\
);
\rgb_blur3_inferred__4/i___0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__4/i___0_carry__3_n_0\,
CO(3) => \rgb_blur3_inferred__4/i___0_carry__4_n_0\,
CO(2) => \rgb_blur3_inferred__4/i___0_carry__4_n_1\,
CO(1) => \rgb_blur3_inferred__4/i___0_carry__4_n_2\,
CO(0) => \rgb_blur3_inferred__4/i___0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__4/i___0_carry__4_n_4\,
O(2) => \rgb_blur3_inferred__4/i___0_carry__4_n_5\,
O(1) => \rgb_blur3_inferred__4/i___0_carry__4_n_6\,
O(0) => \rgb_blur3_inferred__4/i___0_carry__4_n_7\,
S(3) => \i___0_carry__4_i_1__0_n_0\,
S(2) => \i___0_carry__4_i_2__0_n_0\,
S(1) => \i___0_carry__4_i_3__0_n_0\,
S(0) => \i___0_carry__4_i_4__0_n_0\
);
\rgb_blur3_inferred__4/i___0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__4/i___0_carry__4_n_0\,
CO(3) => \rgb_blur3_inferred__4/i___0_carry__5_n_0\,
CO(2) => \rgb_blur3_inferred__4/i___0_carry__5_n_1\,
CO(1) => \rgb_blur3_inferred__4/i___0_carry__5_n_2\,
CO(0) => \rgb_blur3_inferred__4/i___0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__4/i___0_carry__5_n_4\,
O(2) => \rgb_blur3_inferred__4/i___0_carry__5_n_5\,
O(1) => \rgb_blur3_inferred__4/i___0_carry__5_n_6\,
O(0) => \rgb_blur3_inferred__4/i___0_carry__5_n_7\,
S(3) => \i___0_carry__5_i_1__0_n_0\,
S(2) => \i___0_carry__5_i_2__0_n_0\,
S(1) => \i___0_carry__5_i_3__0_n_0\,
S(0) => \i___0_carry__5_i_4__0_n_0\
);
\rgb_blur3_inferred__4/i___0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__4/i___0_carry__5_n_0\,
CO(3) => \NLW_rgb_blur3_inferred__4/i___0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \rgb_blur3_inferred__4/i___0_carry__6_n_1\,
CO(1) => \rgb_blur3_inferred__4/i___0_carry__6_n_2\,
CO(0) => \rgb_blur3_inferred__4/i___0_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
O(2) => \rgb_blur3_inferred__4/i___0_carry__6_n_5\,
O(1) => \rgb_blur3_inferred__4/i___0_carry__6_n_6\,
O(0) => \rgb_blur3_inferred__4/i___0_carry__6_n_7\,
S(3) => \i___0_carry__6_i_1__0_n_0\,
S(2) => \i___0_carry__6_i_2__0_n_0\,
S(1) => \i___0_carry__6_i_3__0_n_0\,
S(0) => \i___0_carry__6_i_4__0_n_0\
);
\rgb_blur3_inferred__5/i___24_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__5/i___24_carry_n_0\,
CO(2) => \rgb_blur3_inferred__5/i___24_carry_n_1\,
CO(1) => \rgb_blur3_inferred__5/i___24_carry_n_2\,
CO(0) => \rgb_blur3_inferred__5/i___24_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => D(18 downto 16),
DI(0) => '0',
O(3) => \rgb_blur3_inferred__5/i___24_carry_n_4\,
O(2) => \rgb_blur3_inferred__5/i___24_carry_n_5\,
O(1) => \rgb_blur3_inferred__5/i___24_carry_n_6\,
O(0) => \rgb_blur3_inferred__5/i___24_carry_n_7\,
S(3) => \i___24_carry_i_1__0_n_0\,
S(2) => \i___24_carry_i_2__0_n_0\,
S(1) => \i___24_carry_i_3__0_n_0\,
S(0) => \i___24_carry_i_4__0_n_0\
);
\rgb_blur3_inferred__5/i___24_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i___24_carry_n_0\,
CO(3) => \rgb_blur3_inferred__5/i___24_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__5/i___24_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__5/i___24_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__5/i___24_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => D(22 downto 19),
O(3) => \rgb_blur3_inferred__5/i___24_carry__0_n_4\,
O(2) => \rgb_blur3_inferred__5/i___24_carry__0_n_5\,
O(1) => \rgb_blur3_inferred__5/i___24_carry__0_n_6\,
O(0) => \rgb_blur3_inferred__5/i___24_carry__0_n_7\,
S(3) => \i___24_carry__0_i_1__0_n_0\,
S(2) => \i___24_carry__0_i_2__0_n_0\,
S(1) => \i___24_carry__0_i_3__0_n_0\,
S(0) => \i___24_carry__0_i_4__0_n_0\
);
\rgb_blur3_inferred__5/i___24_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i___24_carry__0_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__5/i___24_carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__5/i___24_carry__1_n_2\,
CO(0) => \NLW_rgb_blur3_inferred__5/i___24_carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => D(23),
O(3 downto 1) => \NLW_rgb_blur3_inferred__5/i___24_carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3_inferred__5/i___24_carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \i___24_carry__1_i_1__0_n_0\
);
\rgb_blur3_inferred__5/i___50_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__5/i___50_carry_n_0\,
CO(2) => \rgb_blur3_inferred__5/i___50_carry_n_1\,
CO(1) => \rgb_blur3_inferred__5/i___50_carry_n_2\,
CO(0) => \rgb_blur3_inferred__5/i___50_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => I12(2 downto 0),
DI(0) => '0',
O(3 downto 1) => \C__1\(3 downto 1),
O(0) => \NLW_rgb_blur3_inferred__5/i___50_carry_O_UNCONNECTED\(0),
S(3) => \i___50_carry_i_1__0_n_0\,
S(2) => \i___50_carry_i_2__0_n_0\,
S(1) => \i___50_carry_i_3__0_n_0\,
S(0) => '0'
);
\rgb_blur3_inferred__5/i___50_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i___50_carry_n_0\,
CO(3) => \rgb_blur3_inferred__5/i___50_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__5/i___50_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__5/i___50_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__5/i___50_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => I12(6 downto 3),
O(3 downto 0) => \C__1\(7 downto 4),
S(3) => \i___50_carry__0_i_1__0_n_0\,
S(2) => \i___50_carry__0_i_2__0_n_0\,
S(1) => \i___50_carry__0_i_3__0_n_0\,
S(0) => \i___50_carry__0_i_4__0_n_0\
);
\rgb_blur3_inferred__5/i___50_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i___50_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__5/i___50_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__5/i___50_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__5/i___50_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__5/i___50_carry__1_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur3_inferred__5/i___24_carry__1_n_2\,
DI(2) => \rgb_blur3_inferred__5/i___24_carry__1_n_7\,
DI(1) => \i___50_carry__1_i_1__0_n_0\,
DI(0) => I12(7),
O(3 downto 0) => \C__1\(11 downto 8),
S(3) => \i___50_carry__1_i_2__0_n_0\,
S(2) => \i___50_carry__1_i_3__0_n_0\,
S(1) => \i___50_carry__1_i_4__0_n_0\,
S(0) => \i___50_carry__1_i_5__0_n_0\
);
\rgb_blur3_inferred__5/i___82_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__5/i___82_carry_n_0\,
CO(2) => \rgb_blur3_inferred__5/i___82_carry_n_1\,
CO(1) => \rgb_blur3_inferred__5/i___82_carry_n_2\,
CO(0) => \rgb_blur3_inferred__5/i___82_carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => I13(2 downto 0),
DI(0) => '0',
O(3) => \rgb_blur3_inferred__5/i___82_carry_n_4\,
O(2) => \rgb_blur3_inferred__5/i___82_carry_n_5\,
O(1) => \rgb_blur3_inferred__5/i___82_carry_n_6\,
O(0) => \NLW_rgb_blur3_inferred__5/i___82_carry_O_UNCONNECTED\(0),
S(3) => \i___82_carry_i_1__0_n_0\,
S(2) => \i___82_carry_i_2__0_n_0\,
S(1) => \i___82_carry_i_3__0_n_0\,
S(0) => '0'
);
\rgb_blur3_inferred__5/i___82_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i___82_carry_n_0\,
CO(3) => \rgb_blur3_inferred__5/i___82_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__5/i___82_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__5/i___82_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__5/i___82_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => I13(6 downto 3),
O(3) => \rgb_blur3_inferred__5/i___82_carry__0_n_4\,
O(2) => \rgb_blur3_inferred__5/i___82_carry__0_n_5\,
O(1) => \rgb_blur3_inferred__5/i___82_carry__0_n_6\,
O(0) => \rgb_blur3_inferred__5/i___82_carry__0_n_7\,
S(3) => \i___82_carry__0_i_1__0_n_0\,
S(2) => \i___82_carry__0_i_2__0_n_0\,
S(1) => \i___82_carry__0_i_3__0_n_0\,
S(0) => \i___82_carry__0_i_4__0_n_0\
);
\rgb_blur3_inferred__5/i___82_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i___82_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__5/i___82_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__5/i___82_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__5/i___82_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__5/i___82_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 2) => \C__1\(10 downto 9),
DI(1) => \i___82_carry__1_i_1__0_n_0\,
DI(0) => I13(7),
O(3) => \rgb_blur3_inferred__5/i___82_carry__1_n_4\,
O(2) => \rgb_blur3_inferred__5/i___82_carry__1_n_5\,
O(1) => \rgb_blur3_inferred__5/i___82_carry__1_n_6\,
O(0) => \rgb_blur3_inferred__5/i___82_carry__1_n_7\,
S(3) => \i___82_carry__1_i_2__0_n_0\,
S(2) => \i___82_carry__1_i_3__0_n_0\,
S(1) => \i___82_carry__1_i_4__0_n_0\,
S(0) => \i___82_carry__1_i_5__0_n_0\
);
\rgb_blur3_inferred__5/i___82_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i___82_carry__1_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__5/i___82_carry__2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__5/i___82_carry__2_n_2\,
CO(0) => \NLW_rgb_blur3_inferred__5/i___82_carry__2_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \C__1\(11),
O(3 downto 1) => \NLW_rgb_blur3_inferred__5/i___82_carry__2_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3_inferred__5/i___82_carry__2_n_7\,
S(3 downto 1) => B"001",
S(0) => \i___82_carry__2_i_1__0_n_0\
);
\rgb_blur3_inferred__5/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__5/i__carry_n_0\,
CO(2) => \rgb_blur3_inferred__5/i__carry_n_1\,
CO(1) => \rgb_blur3_inferred__5/i__carry_n_2\,
CO(0) => \rgb_blur3_inferred__5/i__carry_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb_buffer_reg[642]\(18 downto 16),
DI(0) => '0',
O(3) => \rgb_blur3_inferred__5/i__carry_n_4\,
O(2) => \rgb_blur3_inferred__5/i__carry_n_5\,
O(1) => \rgb_blur3_inferred__5/i__carry_n_6\,
O(0) => \NLW_rgb_blur3_inferred__5/i__carry_O_UNCONNECTED\(0),
S(3) => \i__carry_i_1__2_n_0\,
S(2) => \i__carry_i_2__2_n_0\,
S(1) => \i__carry_i_3__2_n_0\,
S(0) => '0'
);
\rgb_blur3_inferred__5/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i__carry_n_0\,
CO(3) => \rgb_blur3_inferred__5/i__carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__5/i__carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__5/i__carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__5/i__carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \rgb_buffer_reg[642]\(22 downto 19),
O(3) => \rgb_blur3_inferred__5/i__carry__0_n_4\,
O(2) => \rgb_blur3_inferred__5/i__carry__0_n_5\,
O(1) => \rgb_blur3_inferred__5/i__carry__0_n_6\,
O(0) => \rgb_blur3_inferred__5/i__carry__0_n_7\,
S(3) => \i__carry__0_i_1__2_n_0\,
S(2) => \i__carry__0_i_2__2_n_0\,
S(1) => \i__carry__0_i_3__2_n_0\,
S(0) => \i__carry__0_i_4__2_n_0\
);
\rgb_blur3_inferred__5/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__5/i__carry__0_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__5/i__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__5/i__carry__1_n_2\,
CO(0) => \NLW_rgb_blur3_inferred__5/i__carry__1_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \rgb_buffer_reg[642]\(23),
O(3 downto 1) => \NLW_rgb_blur3_inferred__5/i__carry__1_O_UNCONNECTED\(3 downto 1),
O(0) => \rgb_blur3_inferred__5/i__carry__1_n_7\,
S(3 downto 1) => B"001",
S(0) => \i__carry__1_i_1__2_n_0\
);
\rgb_blur3_inferred__6/i___0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__6/i___0_carry_n_0\,
CO(2) => \rgb_blur3_inferred__6/i___0_carry_n_1\,
CO(1) => \rgb_blur3_inferred__6/i___0_carry_n_2\,
CO(0) => \rgb_blur3_inferred__6/i___0_carry_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry_i_1__3_n_0\,
DI(2) => \i___0_carry_i_2__3_n_0\,
DI(1) => \i___0_carry_i_3__3_n_0\,
DI(0) => '0',
O(3 downto 0) => PCIN(3 downto 0),
S(3) => \i___0_carry_i_4__3_n_0\,
S(2) => \i___0_carry_i_5__3_n_0\,
S(1) => \i___0_carry_i_6__3_n_0\,
S(0) => \i___0_carry_i_7__3_n_0\
);
\rgb_blur3_inferred__6/i___0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__6/i___0_carry_n_0\,
CO(3) => \rgb_blur3_inferred__6/i___0_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__6/i___0_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__6/i___0_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__6/i___0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry__0_i_1__3_n_0\,
DI(2) => \i___0_carry__0_i_2__3_n_0\,
DI(1) => \i___0_carry__0_i_3__3_n_0\,
DI(0) => \i___0_carry__0_i_4__3_n_0\,
O(3 downto 0) => PCIN(7 downto 4),
S(3) => \i___0_carry__0_i_5__3_n_0\,
S(2) => \i___0_carry__0_i_6__3_n_0\,
S(1) => \i___0_carry__0_i_7__3_n_0\,
S(0) => \i___0_carry__0_i_8__3_n_0\
);
\rgb_blur3_inferred__6/i___0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__6/i___0_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__6/i___0_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__6/i___0_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__6/i___0_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__6/i___0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur3_inferred__5/i___82_carry__1_n_5\,
DI(2) => \rgb_blur3_inferred__5/i___82_carry__1_n_6\,
DI(1) => '1',
DI(0) => \rgb_blur3_inferred__5/i___82_carry__1_n_7\,
O(3 downto 0) => PCIN(11 downto 8),
S(3) => \i___0_carry__1_i_1__1_n_0\,
S(2) => \i___0_carry__1_i_2__1_n_0\,
S(1) => \i___0_carry__1_i_3__3_n_0\,
S(0) => \i___0_carry__1_i_4__3_n_0\
);
\rgb_blur3_inferred__6/i___0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__6/i___0_carry__1_n_0\,
CO(3 downto 2) => \NLW_rgb_blur3_inferred__6/i___0_carry__2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur3_inferred__6/i___0_carry__2_n_2\,
CO(0) => \rgb_blur3_inferred__6/i___0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb_blur3_inferred__5/i___82_carry__2_n_7\,
DI(0) => \rgb_blur3_inferred__5/i___82_carry__1_n_4\,
O(3) => \NLW_rgb_blur3_inferred__6/i___0_carry__2_O_UNCONNECTED\(3),
O(2) => PCIN(31),
O(1 downto 0) => PCIN(13 downto 12),
S(3 downto 2) => B"01",
S(1) => \i___0_carry__2_i_1__1_n_0\,
S(0) => \i___0_carry__2_i_2__1_n_0\
);
\rgb_blur3_inferred__7/i___0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur3_inferred__7/i___0_carry_n_0\,
CO(2) => \rgb_blur3_inferred__7/i___0_carry_n_1\,
CO(1) => \rgb_blur3_inferred__7/i___0_carry_n_2\,
CO(0) => \rgb_blur3_inferred__7/i___0_carry_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry_i_1__4_n_0\,
DI(2) => \i___0_carry_i_2__4_n_0\,
DI(1) => \i___0_carry_i_3__4_n_0\,
DI(0) => '0',
O(3 downto 0) => rgb_blur3(3 downto 0),
S(3) => \i___0_carry_i_4__4_n_0\,
S(2) => \i___0_carry_i_5__4_n_0\,
S(1) => \i___0_carry_i_6__4_n_0\,
S(0) => \i___0_carry_i_7__4_n_0\
);
\rgb_blur3_inferred__7/i___0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__7/i___0_carry_n_0\,
CO(3) => \rgb_blur3_inferred__7/i___0_carry__0_n_0\,
CO(2) => \rgb_blur3_inferred__7/i___0_carry__0_n_1\,
CO(1) => \rgb_blur3_inferred__7/i___0_carry__0_n_2\,
CO(0) => \rgb_blur3_inferred__7/i___0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \i___0_carry__0_i_1__4_n_0\,
DI(2) => \i___0_carry__0_i_2__4_n_0\,
DI(1) => \i___0_carry__0_i_3__4_n_0\,
DI(0) => \i___0_carry__0_i_4__4_n_0\,
O(3 downto 0) => rgb_blur3(7 downto 4),
S(3) => \i___0_carry__0_i_5__4_n_0\,
S(2) => \i___0_carry__0_i_6__4_n_0\,
S(1) => \i___0_carry__0_i_7__4_n_0\,
S(0) => \i___0_carry__0_i_8__4_n_0\
);
\rgb_blur3_inferred__7/i___0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__7/i___0_carry__0_n_0\,
CO(3) => \rgb_blur3_inferred__7/i___0_carry__1_n_0\,
CO(2) => \rgb_blur3_inferred__7/i___0_carry__1_n_1\,
CO(1) => \rgb_blur3_inferred__7/i___0_carry__1_n_2\,
CO(0) => \rgb_blur3_inferred__7/i___0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => PCIN(8),
O(3 downto 0) => rgb_blur3(11 downto 8),
S(3) => \i___0_carry__1_i_1__4_n_0\,
S(2) => \i___0_carry__1_i_2__4_n_0\,
S(1) => \i___0_carry__1_i_3__4_n_0\,
S(0) => \i___0_carry__1_i_4__4_n_0\
);
\rgb_blur3_inferred__7/i___0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__7/i___0_carry__1_n_0\,
CO(3) => \rgb_blur3_inferred__7/i___0_carry__2_n_0\,
CO(2) => \rgb_blur3_inferred__7/i___0_carry__2_n_1\,
CO(1) => \rgb_blur3_inferred__7/i___0_carry__2_n_2\,
CO(0) => \rgb_blur3_inferred__7/i___0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => rgb_blur3(15 downto 12),
S(3) => \i___0_carry__2_i_1__4_n_0\,
S(2) => \i___0_carry__2_i_2__4_n_0\,
S(1) => \i___0_carry__2_i_3__1_n_0\,
S(0) => \i___0_carry__2_i_4__1_n_0\
);
\rgb_blur3_inferred__7/i___0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__7/i___0_carry__2_n_0\,
CO(3) => \rgb_blur3_inferred__7/i___0_carry__3_n_0\,
CO(2) => \rgb_blur3_inferred__7/i___0_carry__3_n_1\,
CO(1) => \rgb_blur3_inferred__7/i___0_carry__3_n_2\,
CO(0) => \rgb_blur3_inferred__7/i___0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => rgb_blur3(19 downto 16),
S(3) => \i___0_carry__3_i_1__1_n_0\,
S(2) => \i___0_carry__3_i_2__1_n_0\,
S(1) => \i___0_carry__3_i_3__1_n_0\,
S(0) => \i___0_carry__3_i_4__1_n_0\
);
\rgb_blur3_inferred__7/i___0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__7/i___0_carry__3_n_0\,
CO(3) => \rgb_blur3_inferred__7/i___0_carry__4_n_0\,
CO(2) => \rgb_blur3_inferred__7/i___0_carry__4_n_1\,
CO(1) => \rgb_blur3_inferred__7/i___0_carry__4_n_2\,
CO(0) => \rgb_blur3_inferred__7/i___0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => rgb_blur3(23 downto 20),
S(3) => \i___0_carry__4_i_1__1_n_0\,
S(2) => \i___0_carry__4_i_2__1_n_0\,
S(1) => \i___0_carry__4_i_3__1_n_0\,
S(0) => \i___0_carry__4_i_4__1_n_0\
);
\rgb_blur3_inferred__7/i___0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__7/i___0_carry__4_n_0\,
CO(3) => \rgb_blur3_inferred__7/i___0_carry__5_n_0\,
CO(2) => \rgb_blur3_inferred__7/i___0_carry__5_n_1\,
CO(1) => \rgb_blur3_inferred__7/i___0_carry__5_n_2\,
CO(0) => \rgb_blur3_inferred__7/i___0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => rgb_blur3(27 downto 24),
S(3) => \i___0_carry__5_i_1__1_n_0\,
S(2) => \i___0_carry__5_i_2__1_n_0\,
S(1) => \i___0_carry__5_i_3__1_n_0\,
S(0) => \i___0_carry__5_i_4__1_n_0\
);
\rgb_blur3_inferred__7/i___0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur3_inferred__7/i___0_carry__5_n_0\,
CO(3) => \NLW_rgb_blur3_inferred__7/i___0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \rgb_blur3_inferred__7/i___0_carry__6_n_1\,
CO(1) => \rgb_blur3_inferred__7/i___0_carry__6_n_2\,
CO(0) => \rgb_blur3_inferred__7/i___0_carry__6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => rgb_blur3(31 downto 28),
S(3) => \i___0_carry__6_i_1__1_n_0\,
S(2) => \i___0_carry__6_i_2__1_n_0\,
S(1) => \i___0_carry__6_i_3__1_n_0\,
S(0) => \i___0_carry__6_i_4__1_n_0\
);
rgb_blur4_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => rgb_blur4_carry_n_0,
CO(2) => rgb_blur4_carry_n_1,
CO(1) => rgb_blur4_carry_n_2,
CO(0) => rgb_blur4_carry_n_3,
CYINIT => '1',
DI(3) => rgb_blur4_carry_i_1_n_0,
DI(2) => rgb_blur4_carry_i_2_n_0,
DI(1) => rgb_blur4_carry_i_3_n_0,
DI(0) => rgb_blur4_carry_i_4_n_0,
O(3 downto 0) => NLW_rgb_blur4_carry_O_UNCONNECTED(3 downto 0),
S(3) => rgb_blur4_carry_i_5_n_0,
S(2) => rgb_blur4_carry_i_6_n_0,
S(1) => rgb_blur4_carry_i_7_n_0,
S(0) => rgb_blur4_carry_i_8_n_0
);
\rgb_blur4_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => rgb_blur4_carry_n_0,
CO(3) => \rgb_blur4_carry__0_n_0\,
CO(2) => \rgb_blur4_carry__0_n_1\,
CO(1) => \rgb_blur4_carry__0_n_2\,
CO(0) => \rgb_blur4_carry__0_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur4_carry__0_i_1_n_0\,
DI(2) => \rgb_blur4_carry__0_i_2_n_0\,
DI(1) => \rgb_blur4_carry__0_i_3_n_0\,
DI(0) => \rgb_blur4_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \rgb_blur4_carry__0_i_5_n_0\,
S(2) => \rgb_blur4_carry__0_i_6_n_0\,
S(1) => \rgb_blur4_carry__0_i_7_n_0\,
S(0) => \rgb_blur4_carry__0_i_8_n_0\
);
\rgb_blur4_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__2_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry__2_n_4\,
O => \rgb_blur4_carry__0_i_1_n_0\
);
\rgb_blur4_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__2_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry__2_n_6\,
O => \rgb_blur4_carry__0_i_2_n_0\
);
\rgb_blur4_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__1_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry__1_n_4\,
O => \rgb_blur4_carry__0_i_3_n_0\
);
\rgb_blur4_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__1_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry__1_n_6\,
O => \rgb_blur4_carry__0_i_4_n_0\
);
\rgb_blur4_carry__0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__2_n_4\,
I1 => \rgb_blur3_inferred__1/i___0_carry__2_n_5\,
O => \rgb_blur4_carry__0_i_5_n_0\
);
\rgb_blur4_carry__0_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__2_n_6\,
I1 => \rgb_blur3_inferred__1/i___0_carry__2_n_7\,
O => \rgb_blur4_carry__0_i_6_n_0\
);
\rgb_blur4_carry__0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__1_n_4\,
I1 => \rgb_blur3_inferred__1/i___0_carry__1_n_5\,
O => \rgb_blur4_carry__0_i_7_n_0\
);
\rgb_blur4_carry__0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__1_n_6\,
I1 => \rgb_blur3_inferred__1/i___0_carry__1_n_7\,
O => \rgb_blur4_carry__0_i_8_n_0\
);
\rgb_blur4_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur4_carry__0_n_0\,
CO(3) => \rgb_blur4_carry__1_n_0\,
CO(2) => \rgb_blur4_carry__1_n_1\,
CO(1) => \rgb_blur4_carry__1_n_2\,
CO(0) => \rgb_blur4_carry__1_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur4_carry__1_i_1_n_0\,
DI(2) => \rgb_blur4_carry__1_i_2_n_0\,
DI(1) => \rgb_blur4_carry__1_i_3_n_0\,
DI(0) => \rgb_blur4_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \rgb_blur4_carry__1_i_5_n_0\,
S(2) => \rgb_blur4_carry__1_i_6_n_0\,
S(1) => \rgb_blur4_carry__1_i_7_n_0\,
S(0) => \rgb_blur4_carry__1_i_8_n_0\
);
\rgb_blur4_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__4_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry__4_n_4\,
O => \rgb_blur4_carry__1_i_1_n_0\
);
\rgb_blur4_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__4_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry__4_n_6\,
O => \rgb_blur4_carry__1_i_2_n_0\
);
\rgb_blur4_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__3_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry__3_n_4\,
O => \rgb_blur4_carry__1_i_3_n_0\
);
\rgb_blur4_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__3_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry__3_n_6\,
O => \rgb_blur4_carry__1_i_4_n_0\
);
\rgb_blur4_carry__1_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__4_n_4\,
I1 => \rgb_blur3_inferred__1/i___0_carry__4_n_5\,
O => \rgb_blur4_carry__1_i_5_n_0\
);
\rgb_blur4_carry__1_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__4_n_6\,
I1 => \rgb_blur3_inferred__1/i___0_carry__4_n_7\,
O => \rgb_blur4_carry__1_i_6_n_0\
);
\rgb_blur4_carry__1_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__3_n_4\,
I1 => \rgb_blur3_inferred__1/i___0_carry__3_n_5\,
O => \rgb_blur4_carry__1_i_7_n_0\
);
\rgb_blur4_carry__1_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__3_n_6\,
I1 => \rgb_blur3_inferred__1/i___0_carry__3_n_7\,
O => \rgb_blur4_carry__1_i_8_n_0\
);
\rgb_blur4_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur4_carry__1_n_0\,
CO(3) => \rgb_blur4_carry__2_n_0\,
CO(2) => \rgb_blur4_carry__2_n_1\,
CO(1) => \rgb_blur4_carry__2_n_2\,
CO(0) => \rgb_blur4_carry__2_n_3\,
CYINIT => '0',
DI(3) => \rgb_blur4_carry__2_i_1_n_0\,
DI(2) => \rgb_blur4_carry__2_i_2_n_0\,
DI(1) => \rgb_blur4_carry__2_i_3_n_0\,
DI(0) => \rgb_blur4_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \rgb_blur4_carry__2_i_5_n_0\,
S(2) => \rgb_blur4_carry__2_i_6_n_0\,
S(1) => \rgb_blur4_carry__2_i_7_n_0\,
S(0) => \rgb_blur4_carry__2_i_8_n_0\
);
\rgb_blur4_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
O => \rgb_blur4_carry__2_i_1_n_0\
);
\rgb_blur4_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry__6_n_6\,
O => \rgb_blur4_carry__2_i_2_n_0\
);
\rgb_blur4_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__5_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry__5_n_4\,
O => \rgb_blur4_carry__2_i_3_n_0\
);
\rgb_blur4_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__5_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry__5_n_6\,
O => \rgb_blur4_carry__2_i_4_n_0\
);
\rgb_blur4_carry__2_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
O => \rgb_blur4_carry__2_i_5_n_0\
);
\rgb_blur4_carry__2_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_6\,
I1 => \rgb_blur3_inferred__1/i___0_carry__6_n_7\,
O => \rgb_blur4_carry__2_i_6_n_0\
);
\rgb_blur4_carry__2_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__5_n_4\,
I1 => \rgb_blur3_inferred__1/i___0_carry__5_n_5\,
O => \rgb_blur4_carry__2_i_7_n_0\
);
\rgb_blur4_carry__2_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__5_n_6\,
I1 => \rgb_blur3_inferred__1/i___0_carry__5_n_7\,
O => \rgb_blur4_carry__2_i_8_n_0\
);
rgb_blur4_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry__0_n_4\,
O => rgb_blur4_carry_i_1_n_0
);
rgb_blur4_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry__0_n_6\,
O => rgb_blur4_carry_i_2_n_0
);
rgb_blur4_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry_n_5\,
I1 => \rgb_blur3_inferred__1/i___0_carry_n_4\,
O => rgb_blur4_carry_i_3_n_0
);
rgb_blur4_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry_n_6\,
O => rgb_blur4_carry_i_4_n_0
);
rgb_blur4_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_4\,
I1 => \rgb_blur3_inferred__1/i___0_carry__0_n_5\,
O => rgb_blur4_carry_i_5_n_0
);
rgb_blur4_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_6\,
I1 => \rgb_blur3_inferred__1/i___0_carry__0_n_7\,
O => rgb_blur4_carry_i_6_n_0
);
rgb_blur4_carry_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry_n_4\,
I1 => \rgb_blur3_inferred__1/i___0_carry_n_5\,
O => rgb_blur4_carry_i_7_n_0
);
rgb_blur4_carry_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry_n_6\,
I1 => \rgb_blur3_inferred__1/i___0_carry_n_7\,
O => rgb_blur4_carry_i_8_n_0
);
\rgb_blur4_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur4_inferred__0/i__carry_n_0\,
CO(2) => \rgb_blur4_inferred__0/i__carry_n_1\,
CO(1) => \rgb_blur4_inferred__0/i__carry_n_2\,
CO(0) => \rgb_blur4_inferred__0/i__carry_n_3\,
CYINIT => '1',
DI(3) => \i__carry_i_1_n_0\,
DI(2) => \i__carry_i_2_n_0\,
DI(1) => \i__carry_i_3_n_0\,
DI(0) => \i__carry_i_4_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry_i_5_n_0\,
S(2) => \i__carry_i_6_n_0\,
S(1) => \i__carry_i_7_n_0\,
S(0) => \i__carry_i_8_n_0\
);
\rgb_blur4_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur4_inferred__0/i__carry_n_0\,
CO(3) => \rgb_blur4_inferred__0/i__carry__0_n_0\,
CO(2) => \rgb_blur4_inferred__0/i__carry__0_n_1\,
CO(1) => \rgb_blur4_inferred__0/i__carry__0_n_2\,
CO(0) => \rgb_blur4_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => \i__carry__0_i_1_n_0\,
DI(2) => \i__carry__0_i_2_n_0\,
DI(1) => \i__carry__0_i_3_n_0\,
DI(0) => \i__carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__0_i_5_n_0\,
S(2) => \i__carry__0_i_6_n_0\,
S(1) => \i__carry__0_i_7_n_0\,
S(0) => \i__carry__0_i_8_n_0\
);
\rgb_blur4_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur4_inferred__0/i__carry__0_n_0\,
CO(3) => \rgb_blur4_inferred__0/i__carry__1_n_0\,
CO(2) => \rgb_blur4_inferred__0/i__carry__1_n_1\,
CO(1) => \rgb_blur4_inferred__0/i__carry__1_n_2\,
CO(0) => \rgb_blur4_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3) => \i__carry__1_i_1_n_0\,
DI(2) => \i__carry__1_i_2_n_0\,
DI(1) => \i__carry__1_i_3_n_0\,
DI(0) => \i__carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__1_i_5_n_0\,
S(2) => \i__carry__1_i_6_n_0\,
S(1) => \i__carry__1_i_7_n_0\,
S(0) => \i__carry__1_i_8_n_0\
);
\rgb_blur4_inferred__0/i__carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur4_inferred__0/i__carry__1_n_0\,
CO(3) => \rgb_blur4_inferred__0/i__carry__2_n_0\,
CO(2) => \rgb_blur4_inferred__0/i__carry__2_n_1\,
CO(1) => \rgb_blur4_inferred__0/i__carry__2_n_2\,
CO(0) => \rgb_blur4_inferred__0/i__carry__2_n_3\,
CYINIT => '0',
DI(3) => \i__carry__2_i_1__0_n_0\,
DI(2) => \i__carry__2_i_2_n_0\,
DI(1) => \i__carry__2_i_3_n_0\,
DI(0) => \i__carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_inferred__0/i__carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__2_i_5_n_0\,
S(2) => \i__carry__2_i_6_n_0\,
S(1) => \i__carry__2_i_7_n_0\,
S(0) => \i__carry__2_i_8_n_0\
);
\rgb_blur4_inferred__1/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur4_inferred__1/i__carry_n_0\,
CO(2) => \rgb_blur4_inferred__1/i__carry_n_1\,
CO(1) => \rgb_blur4_inferred__1/i__carry_n_2\,
CO(0) => \rgb_blur4_inferred__1/i__carry_n_3\,
CYINIT => '1',
DI(3) => \i__carry_i_1__0_n_0\,
DI(2) => \i__carry_i_2__0_n_0\,
DI(1) => \i__carry_i_3__0_n_0\,
DI(0) => \i__carry_i_4__0_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry_i_5__0_n_0\,
S(2) => \i__carry_i_6__0_n_0\,
S(1) => \i__carry_i_7__0_n_0\,
S(0) => \i__carry_i_8__0_n_0\
);
\rgb_blur4_inferred__1/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur4_inferred__1/i__carry_n_0\,
CO(3) => \rgb_blur4_inferred__1/i__carry__0_n_0\,
CO(2) => \rgb_blur4_inferred__1/i__carry__0_n_1\,
CO(1) => \rgb_blur4_inferred__1/i__carry__0_n_2\,
CO(0) => \rgb_blur4_inferred__1/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => \i__carry__0_i_1__0_n_0\,
DI(2) => \i__carry__0_i_2__0_n_0\,
DI(1) => \i__carry__0_i_3__0_n_0\,
DI(0) => \i__carry__0_i_4__0_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_inferred__1/i__carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__0_i_5__0_n_0\,
S(2) => \i__carry__0_i_6__0_n_0\,
S(1) => \i__carry__0_i_7__0_n_0\,
S(0) => \i__carry__0_i_8__0_n_0\
);
\rgb_blur4_inferred__1/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur4_inferred__1/i__carry__0_n_0\,
CO(3) => \rgb_blur4_inferred__1/i__carry__1_n_0\,
CO(2) => \rgb_blur4_inferred__1/i__carry__1_n_1\,
CO(1) => \rgb_blur4_inferred__1/i__carry__1_n_2\,
CO(0) => \rgb_blur4_inferred__1/i__carry__1_n_3\,
CYINIT => '0',
DI(3) => \i__carry__1_i_1__0_n_0\,
DI(2) => \i__carry__1_i_2__0_n_0\,
DI(1) => \i__carry__1_i_3__0_n_0\,
DI(0) => \i__carry__1_i_4__0_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_inferred__1/i__carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__1_i_5__0_n_0\,
S(2) => \i__carry__1_i_6__0_n_0\,
S(1) => \i__carry__1_i_7__0_n_0\,
S(0) => \i__carry__1_i_8__0_n_0\
);
\rgb_blur4_inferred__1/i__carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur4_inferred__1/i__carry__1_n_0\,
CO(3) => rgb_blur4,
CO(2) => \rgb_blur4_inferred__1/i__carry__2_n_1\,
CO(1) => \rgb_blur4_inferred__1/i__carry__2_n_2\,
CO(0) => \rgb_blur4_inferred__1/i__carry__2_n_3\,
CYINIT => '0',
DI(3) => \i__carry__2_i_1_n_0\,
DI(2) => \i__carry__2_i_2__0_n_0\,
DI(1) => \i__carry__2_i_3__0_n_0\,
DI(0) => \i__carry__2_i_4__0_n_0\,
O(3 downto 0) => \NLW_rgb_blur4_inferred__1/i__carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \i__carry__2_i_5__0_n_0\,
S(2) => \i__carry__2_i_6__0_n_0\,
S(1) => \i__carry__2_i_7__0_n_0\,
S(0) => \i__carry__2_i_8__0_n_0\
);
\rgb_blur[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_7\,
I1 => \rgb_blur4_carry__2_n_0\,
I2 => \rgb_blur_reg[1]_i_2_n_4\,
O => p_7_out(0)
);
\rgb_blur[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFDFD020202FD02"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
I1 => \rgb_blur[10]_i_2_n_0\,
I2 => \rgb_blur[10]_i_3_n_0\,
I3 => \rgb_blur_reg[12]_i_4_n_6\,
I4 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I5 => \rgb_blur3_inferred__4/i___0_carry__0_n_5\,
O => p_7_out(10)
);
\rgb_blur[10]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \rgb_blur_reg[9]_i_2_n_4\,
I1 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I2 => \rgb_blur_reg[12]_i_4_n_7\,
O => \rgb_blur[10]_i_2_n_0\
);
\rgb_blur[10]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I1 => \rgb_blur3_inferred__4/i___0_carry__0_n_6\,
I2 => \rgb_blur3_inferred__4/i___0_carry__0_n_7\,
O => \rgb_blur[10]_i_3_n_0\
);
\rgb_blur[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
I1 => \rgb_blur[11]_i_2_n_0\,
I2 => \rgb_blur_reg[12]_i_4_n_5\,
I3 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I4 => \rgb_blur3_inferred__4/i___0_carry__0_n_4\,
O => p_7_out(11)
);
\rgb_blur[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444444444444F"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_5\,
I1 => \rgb_blur[10]_i_3_n_0\,
I2 => \rgb_blur_reg[12]_i_4_n_6\,
I3 => \rgb_blur_reg[9]_i_2_n_4\,
I4 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I5 => \rgb_blur_reg[12]_i_4_n_7\,
O => \rgb_blur[11]_i_2_n_0\
);
\rgb_blur[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFDFD020202FD02"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
I1 => \rgb_blur[12]_i_2_n_0\,
I2 => \rgb_blur[12]_i_3_n_0\,
I3 => \rgb_blur_reg[12]_i_4_n_4\,
I4 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I5 => \rgb_blur3_inferred__4/i___0_carry__1_n_7\,
O => p_7_out(12)
);
\rgb_blur[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_7\,
I1 => \rgb_blur3_inferred__4/i___0_carry__0_n_6\,
I2 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I3 => \rgb_blur3_inferred__4/i___0_carry__0_n_4\,
I4 => \rgb_blur3_inferred__4/i___0_carry__0_n_5\,
O => \rgb_blur[12]_i_2_n_0\
);
\rgb_blur[12]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \rgb_blur_reg[12]_i_4_n_6\,
I1 => \rgb_blur_reg[9]_i_2_n_4\,
I2 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I3 => \rgb_blur_reg[12]_i_4_n_7\,
I4 => \rgb_blur_reg[12]_i_4_n_5\,
O => \rgb_blur[12]_i_3_n_0\
);
\rgb_blur[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__1_n_7\,
O => \rgb_blur[12]_i_5_n_0\
);
\rgb_blur[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_4\,
O => \rgb_blur[12]_i_6_n_0\
);
\rgb_blur[12]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_5\,
O => \rgb_blur[12]_i_7_n_0\
);
\rgb_blur[12]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_6\,
O => \rgb_blur[12]_i_8_n_0\
);
\rgb_blur[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
I1 => \rgb_blur[13]_i_2_n_0\,
I2 => \rgb_blur_reg[15]_i_3_n_7\,
I3 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I4 => \rgb_blur3_inferred__4/i___0_carry__1_n_6\,
O => p_7_out(13)
);
\rgb_blur[13]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \rgb_blur_reg[12]_i_4_n_4\,
I1 => \rgb_blur[12]_i_3_n_0\,
I2 => \rgb_blur3_inferred__4/i___0_carry__1_n_7\,
I3 => \rgb_blur[12]_i_2_n_0\,
O => \rgb_blur[13]_i_2_n_0\
);
\rgb_blur[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
I1 => \rgb_blur[14]_i_2_n_0\,
I2 => \rgb_blur_reg[15]_i_3_n_6\,
I3 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I4 => \rgb_blur3_inferred__4/i___0_carry__1_n_5\,
O => p_7_out(14)
);
\rgb_blur[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202FF02020202"
)
port map (
I0 => \rgb_blur[12]_i_3_n_0\,
I1 => \rgb_blur_reg[12]_i_4_n_4\,
I2 => \rgb_blur_reg[15]_i_3_n_7\,
I3 => \rgb_blur3_inferred__4/i___0_carry__1_n_7\,
I4 => \rgb_blur3_inferred__4/i___0_carry__1_n_6\,
I5 => \rgb_blur[12]_i_2_n_0\,
O => \rgb_blur[14]_i_2_n_0\
);
\rgb_blur[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
I1 => \rgb_blur[15]_i_2_n_0\,
I2 => \rgb_blur_reg[15]_i_3_n_5\,
I3 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I4 => \rgb_blur3_inferred__4/i___0_carry__1_n_4\,
O => p_7_out(15)
);
\rgb_blur[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000200020002"
)
port map (
I0 => \rgb_blur[12]_i_2_n_0\,
I1 => \rgb_blur3_inferred__4/i___0_carry__1_n_6\,
I2 => \rgb_blur3_inferred__4/i___0_carry__1_n_7\,
I3 => \rgb_blur3_inferred__4/i___0_carry__1_n_5\,
I4 => \rgb_blur[12]_i_3_n_0\,
I5 => \rgb_blur[15]_i_4_n_0\,
O => \rgb_blur[15]_i_2_n_0\
);
\rgb_blur[15]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \rgb_blur_reg[15]_i_3_n_6\,
I1 => \rgb_blur_reg[15]_i_3_n_7\,
I2 => \rgb_blur_reg[12]_i_4_n_4\,
O => \rgb_blur[15]_i_4_n_0\
);
\rgb_blur[15]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__1_n_4\,
O => \rgb_blur[15]_i_5_n_0\
);
\rgb_blur[15]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__1_n_5\,
O => \rgb_blur[15]_i_6_n_0\
);
\rgb_blur[15]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__1_n_6\,
O => \rgb_blur[15]_i_7_n_0\
);
\rgb_blur[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rgb_blur3(4),
I1 => rgb_blur4,
I2 => \rgb_blur_reg[17]_i_2_n_4\,
O => p_7_out(16)
);
\rgb_blur[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5F5F7788A0A07788"
)
port map (
I0 => rgb_blur3(31),
I1 => \rgb_blur_reg[17]_i_2_n_4\,
I2 => rgb_blur3(4),
I3 => \rgb_blur_reg[20]_i_4_n_7\,
I4 => rgb_blur4,
I5 => rgb_blur3(5),
O => p_7_out(17)
);
\rgb_blur[17]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(0),
O => p_0_in(0)
);
\rgb_blur[17]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(4),
O => p_0_in(4)
);
\rgb_blur[17]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(3),
O => p_0_in(3)
);
\rgb_blur[17]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(2),
O => p_0_in(2)
);
\rgb_blur[17]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(1),
O => p_0_in(1)
);
\rgb_blur[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFDFD020202FD02"
)
port map (
I0 => rgb_blur3(31),
I1 => \rgb_blur[18]_i_2_n_0\,
I2 => \rgb_blur[18]_i_3_n_0\,
I3 => \rgb_blur_reg[20]_i_4_n_6\,
I4 => rgb_blur4,
I5 => rgb_blur3(6),
O => p_7_out(18)
);
\rgb_blur[18]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \rgb_blur_reg[17]_i_2_n_4\,
I1 => rgb_blur4,
I2 => \rgb_blur_reg[20]_i_4_n_7\,
O => \rgb_blur[18]_i_2_n_0\
);
\rgb_blur[18]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => rgb_blur4,
I1 => rgb_blur3(5),
I2 => rgb_blur3(4),
O => \rgb_blur[18]_i_3_n_0\
);
\rgb_blur[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => rgb_blur3(31),
I1 => \rgb_blur[19]_i_2_n_0\,
I2 => \rgb_blur_reg[20]_i_4_n_5\,
I3 => rgb_blur4,
I4 => rgb_blur3(7),
O => p_7_out(19)
);
\rgb_blur[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444444444444F"
)
port map (
I0 => rgb_blur3(6),
I1 => \rgb_blur[18]_i_3_n_0\,
I2 => \rgb_blur_reg[20]_i_4_n_6\,
I3 => \rgb_blur_reg[17]_i_2_n_4\,
I4 => rgb_blur4,
I5 => \rgb_blur_reg[20]_i_4_n_7\,
O => \rgb_blur[19]_i_2_n_0\
);
\rgb_blur[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5F5F7788A0A07788"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
I1 => \rgb_blur_reg[1]_i_2_n_4\,
I2 => \rgb_blur3_inferred__1/i___0_carry__0_n_7\,
I3 => \rgb_blur_reg[4]_i_4_n_7\,
I4 => \rgb_blur4_carry__2_n_0\,
I5 => \rgb_blur3_inferred__1/i___0_carry__0_n_6\,
O => p_7_out(1)
);
\rgb_blur[1]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry_n_7\,
O => \rgb_blur[1]_i_3_n_0\
);
\rgb_blur[1]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_7\,
O => \rgb_blur[1]_i_4_n_0\
);
\rgb_blur[1]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry_n_4\,
O => \rgb_blur[1]_i_5_n_0\
);
\rgb_blur[1]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry_n_5\,
O => \rgb_blur[1]_i_6_n_0\
);
\rgb_blur[1]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry_n_6\,
O => \rgb_blur[1]_i_7_n_0\
);
\rgb_blur[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFDFD020202FD02"
)
port map (
I0 => rgb_blur3(31),
I1 => \rgb_blur[20]_i_2_n_0\,
I2 => \rgb_blur[20]_i_3_n_0\,
I3 => \rgb_blur_reg[20]_i_4_n_4\,
I4 => rgb_blur4,
I5 => rgb_blur3(8),
O => p_7_out(20)
);
\rgb_blur[20]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => rgb_blur3(4),
I1 => rgb_blur3(5),
I2 => rgb_blur4,
I3 => rgb_blur3(7),
I4 => rgb_blur3(6),
O => \rgb_blur[20]_i_2_n_0\
);
\rgb_blur[20]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \rgb_blur_reg[20]_i_4_n_6\,
I1 => \rgb_blur_reg[17]_i_2_n_4\,
I2 => rgb_blur4,
I3 => \rgb_blur_reg[20]_i_4_n_7\,
I4 => \rgb_blur_reg[20]_i_4_n_5\,
O => \rgb_blur[20]_i_3_n_0\
);
\rgb_blur[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(8),
O => p_0_in(8)
);
\rgb_blur[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(7),
O => p_0_in(7)
);
\rgb_blur[20]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(6),
O => p_0_in(6)
);
\rgb_blur[20]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(5),
O => p_0_in(5)
);
\rgb_blur[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => rgb_blur3(31),
I1 => \rgb_blur[21]_i_2_n_0\,
I2 => \rgb_blur_reg[23]_i_4_n_7\,
I3 => rgb_blur4,
I4 => rgb_blur3(9),
O => p_7_out(21)
);
\rgb_blur[21]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \rgb_blur_reg[20]_i_4_n_4\,
I1 => \rgb_blur[20]_i_3_n_0\,
I2 => rgb_blur3(8),
I3 => \rgb_blur[20]_i_2_n_0\,
O => \rgb_blur[21]_i_2_n_0\
);
\rgb_blur[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => rgb_blur3(31),
I1 => \rgb_blur[22]_i_2_n_0\,
I2 => \rgb_blur_reg[23]_i_4_n_6\,
I3 => rgb_blur4,
I4 => rgb_blur3(10),
O => p_7_out(22)
);
\rgb_blur[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202FF02020202"
)
port map (
I0 => \rgb_blur[20]_i_3_n_0\,
I1 => \rgb_blur_reg[20]_i_4_n_4\,
I2 => \rgb_blur_reg[23]_i_4_n_7\,
I3 => rgb_blur3(8),
I4 => rgb_blur3(9),
I5 => \rgb_blur[20]_i_2_n_0\,
O => \rgb_blur[22]_i_2_n_0\
);
\rgb_blur[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => vsync_in,
I1 => hsync_in,
O => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => rgb_blur3(31),
I1 => \rgb_blur[23]_i_3_n_0\,
I2 => \rgb_blur_reg[23]_i_4_n_5\,
I3 => rgb_blur4,
I4 => rgb_blur3(11),
O => p_7_out(23)
);
\rgb_blur[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000200020002"
)
port map (
I0 => \rgb_blur[20]_i_2_n_0\,
I1 => rgb_blur3(9),
I2 => rgb_blur3(8),
I3 => rgb_blur3(10),
I4 => \rgb_blur[20]_i_3_n_0\,
I5 => \rgb_blur[23]_i_5_n_0\,
O => \rgb_blur[23]_i_3_n_0\
);
\rgb_blur[23]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \rgb_blur_reg[23]_i_4_n_6\,
I1 => \rgb_blur_reg[23]_i_4_n_7\,
I2 => \rgb_blur_reg[20]_i_4_n_4\,
O => \rgb_blur[23]_i_5_n_0\
);
\rgb_blur[23]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(11),
O => p_0_in(11)
);
\rgb_blur[23]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(10),
O => p_0_in(10)
);
\rgb_blur[23]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb_blur3(9),
O => p_0_in(9)
);
\rgb_blur[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFDFD020202FD02"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
I1 => \rgb_blur[2]_i_2_n_0\,
I2 => \rgb_blur[2]_i_3_n_0\,
I3 => \rgb_blur_reg[4]_i_4_n_6\,
I4 => \rgb_blur4_carry__2_n_0\,
I5 => \rgb_blur3_inferred__1/i___0_carry__0_n_5\,
O => p_7_out(2)
);
\rgb_blur[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \rgb_blur_reg[1]_i_2_n_4\,
I1 => \rgb_blur4_carry__2_n_0\,
I2 => \rgb_blur_reg[4]_i_4_n_7\,
O => \rgb_blur[2]_i_2_n_0\
);
\rgb_blur[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \rgb_blur4_carry__2_n_0\,
I1 => \rgb_blur3_inferred__1/i___0_carry__0_n_6\,
I2 => \rgb_blur3_inferred__1/i___0_carry__0_n_7\,
O => \rgb_blur[2]_i_3_n_0\
);
\rgb_blur[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
I1 => \rgb_blur[3]_i_2_n_0\,
I2 => \rgb_blur_reg[4]_i_4_n_5\,
I3 => \rgb_blur4_carry__2_n_0\,
I4 => \rgb_blur3_inferred__1/i___0_carry__0_n_4\,
O => p_7_out(3)
);
\rgb_blur[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"444444444444444F"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_5\,
I1 => \rgb_blur[2]_i_3_n_0\,
I2 => \rgb_blur_reg[4]_i_4_n_6\,
I3 => \rgb_blur_reg[1]_i_2_n_4\,
I4 => \rgb_blur4_carry__2_n_0\,
I5 => \rgb_blur_reg[4]_i_4_n_7\,
O => \rgb_blur[3]_i_2_n_0\
);
\rgb_blur[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFDFD020202FD02"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
I1 => \rgb_blur[4]_i_2_n_0\,
I2 => \rgb_blur[4]_i_3_n_0\,
I3 => \rgb_blur_reg[4]_i_4_n_4\,
I4 => \rgb_blur4_carry__2_n_0\,
I5 => \rgb_blur3_inferred__1/i___0_carry__1_n_7\,
O => p_7_out(4)
);
\rgb_blur[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_7\,
I1 => \rgb_blur3_inferred__1/i___0_carry__0_n_6\,
I2 => \rgb_blur4_carry__2_n_0\,
I3 => \rgb_blur3_inferred__1/i___0_carry__0_n_4\,
I4 => \rgb_blur3_inferred__1/i___0_carry__0_n_5\,
O => \rgb_blur[4]_i_2_n_0\
);
\rgb_blur[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \rgb_blur_reg[4]_i_4_n_6\,
I1 => \rgb_blur_reg[1]_i_2_n_4\,
I2 => \rgb_blur4_carry__2_n_0\,
I3 => \rgb_blur_reg[4]_i_4_n_7\,
I4 => \rgb_blur_reg[4]_i_4_n_5\,
O => \rgb_blur[4]_i_3_n_0\
);
\rgb_blur[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__1_n_7\,
O => \rgb_blur[4]_i_5_n_0\
);
\rgb_blur[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_4\,
O => \rgb_blur[4]_i_6_n_0\
);
\rgb_blur[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_5\,
O => \rgb_blur[4]_i_7_n_0\
);
\rgb_blur[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__0_n_6\,
O => \rgb_blur[4]_i_8_n_0\
);
\rgb_blur[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
I1 => \rgb_blur[5]_i_2_n_0\,
I2 => \rgb_blur_reg[7]_i_3_n_7\,
I3 => \rgb_blur4_carry__2_n_0\,
I4 => \rgb_blur3_inferred__1/i___0_carry__1_n_6\,
O => p_7_out(5)
);
\rgb_blur[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \rgb_blur_reg[4]_i_4_n_4\,
I1 => \rgb_blur[4]_i_3_n_0\,
I2 => \rgb_blur3_inferred__1/i___0_carry__1_n_7\,
I3 => \rgb_blur[4]_i_2_n_0\,
O => \rgb_blur[5]_i_2_n_0\
);
\rgb_blur[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
I1 => \rgb_blur[6]_i_2_n_0\,
I2 => \rgb_blur_reg[7]_i_3_n_6\,
I3 => \rgb_blur4_carry__2_n_0\,
I4 => \rgb_blur3_inferred__1/i___0_carry__1_n_5\,
O => p_7_out(6)
);
\rgb_blur[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202FF02020202"
)
port map (
I0 => \rgb_blur[4]_i_3_n_0\,
I1 => \rgb_blur_reg[4]_i_4_n_4\,
I2 => \rgb_blur_reg[7]_i_3_n_7\,
I3 => \rgb_blur3_inferred__1/i___0_carry__1_n_7\,
I4 => \rgb_blur3_inferred__1/i___0_carry__1_n_6\,
I5 => \rgb_blur[4]_i_2_n_0\,
O => \rgb_blur[6]_i_2_n_0\
);
\rgb_blur[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDD222D2"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__6_n_4\,
I1 => \rgb_blur[7]_i_2_n_0\,
I2 => \rgb_blur_reg[7]_i_3_n_5\,
I3 => \rgb_blur4_carry__2_n_0\,
I4 => \rgb_blur3_inferred__1/i___0_carry__1_n_4\,
O => p_7_out(7)
);
\rgb_blur[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000200020002"
)
port map (
I0 => \rgb_blur[4]_i_2_n_0\,
I1 => \rgb_blur3_inferred__1/i___0_carry__1_n_6\,
I2 => \rgb_blur3_inferred__1/i___0_carry__1_n_7\,
I3 => \rgb_blur3_inferred__1/i___0_carry__1_n_5\,
I4 => \rgb_blur[4]_i_3_n_0\,
I5 => \rgb_blur[7]_i_4_n_0\,
O => \rgb_blur[7]_i_2_n_0\
);
\rgb_blur[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \rgb_blur_reg[7]_i_3_n_6\,
I1 => \rgb_blur_reg[7]_i_3_n_7\,
I2 => \rgb_blur_reg[4]_i_4_n_4\,
O => \rgb_blur[7]_i_4_n_0\
);
\rgb_blur[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__1_n_4\,
O => \rgb_blur[7]_i_5_n_0\
);
\rgb_blur[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__1_n_5\,
O => \rgb_blur[7]_i_6_n_0\
);
\rgb_blur[7]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__1/i___0_carry__1_n_6\,
O => \rgb_blur[7]_i_7_n_0\
);
\rgb_blur[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_7\,
I1 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I2 => \rgb_blur_reg[9]_i_2_n_4\,
O => p_7_out(8)
);
\rgb_blur[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5F5F7788A0A07788"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__6_n_4\,
I1 => \rgb_blur_reg[9]_i_2_n_4\,
I2 => \rgb_blur3_inferred__4/i___0_carry__0_n_7\,
I3 => \rgb_blur_reg[12]_i_4_n_7\,
I4 => \rgb_blur4_inferred__0/i__carry__2_n_0\,
I5 => \rgb_blur3_inferred__4/i___0_carry__0_n_6\,
O => p_7_out(9)
);
\rgb_blur[9]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry_n_7\,
O => \rgb_blur[9]_i_3_n_0\
);
\rgb_blur[9]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry__0_n_7\,
O => \rgb_blur[9]_i_4_n_0\
);
\rgb_blur[9]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry_n_4\,
O => \rgb_blur[9]_i_5_n_0\
);
\rgb_blur[9]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry_n_5\,
O => \rgb_blur[9]_i_6_n_0\
);
\rgb_blur[9]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb_blur3_inferred__4/i___0_carry_n_6\,
O => \rgb_blur[9]_i_7_n_0\
);
\rgb_blur_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(0),
Q => rgb_blur(0),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(10),
Q => rgb_blur(10),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(11),
Q => rgb_blur(11),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(12),
Q => rgb_blur(12),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[12]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur_reg[9]_i_2_n_0\,
CO(3) => \rgb_blur_reg[12]_i_4_n_0\,
CO(2) => \rgb_blur_reg[12]_i_4_n_1\,
CO(1) => \rgb_blur_reg[12]_i_4_n_2\,
CO(0) => \rgb_blur_reg[12]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur_reg[12]_i_4_n_4\,
O(2) => \rgb_blur_reg[12]_i_4_n_5\,
O(1) => \rgb_blur_reg[12]_i_4_n_6\,
O(0) => \rgb_blur_reg[12]_i_4_n_7\,
S(3) => \rgb_blur[12]_i_5_n_0\,
S(2) => \rgb_blur[12]_i_6_n_0\,
S(1) => \rgb_blur[12]_i_7_n_0\,
S(0) => \rgb_blur[12]_i_8_n_0\
);
\rgb_blur_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(13),
Q => rgb_blur(13),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(14),
Q => rgb_blur(14),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(15),
Q => rgb_blur(15),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[15]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur_reg[12]_i_4_n_0\,
CO(3 downto 2) => \NLW_rgb_blur_reg[15]_i_3_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur_reg[15]_i_3_n_2\,
CO(0) => \rgb_blur_reg[15]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_rgb_blur_reg[15]_i_3_O_UNCONNECTED\(3),
O(2) => \rgb_blur_reg[15]_i_3_n_5\,
O(1) => \rgb_blur_reg[15]_i_3_n_6\,
O(0) => \rgb_blur_reg[15]_i_3_n_7\,
S(3) => '0',
S(2) => \rgb_blur[15]_i_5_n_0\,
S(1) => \rgb_blur[15]_i_6_n_0\,
S(0) => \rgb_blur[15]_i_7_n_0\
);
\rgb_blur_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(16),
Q => rgb_blur(16),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(17),
Q => rgb_blur(17),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[17]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur_reg[17]_i_2_n_0\,
CO(2) => \rgb_blur_reg[17]_i_2_n_1\,
CO(1) => \rgb_blur_reg[17]_i_2_n_2\,
CO(0) => \rgb_blur_reg[17]_i_2_n_3\,
CYINIT => p_0_in(0),
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur_reg[17]_i_2_n_4\,
O(2 downto 0) => \NLW_rgb_blur_reg[17]_i_2_O_UNCONNECTED\(2 downto 0),
S(3 downto 0) => p_0_in(4 downto 1)
);
\rgb_blur_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(18),
Q => rgb_blur(18),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(19),
Q => rgb_blur(19),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(1),
Q => rgb_blur(1),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[1]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur_reg[1]_i_2_n_0\,
CO(2) => \rgb_blur_reg[1]_i_2_n_1\,
CO(1) => \rgb_blur_reg[1]_i_2_n_2\,
CO(0) => \rgb_blur_reg[1]_i_2_n_3\,
CYINIT => \rgb_blur[1]_i_3_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur_reg[1]_i_2_n_4\,
O(2 downto 0) => \NLW_rgb_blur_reg[1]_i_2_O_UNCONNECTED\(2 downto 0),
S(3) => \rgb_blur[1]_i_4_n_0\,
S(2) => \rgb_blur[1]_i_5_n_0\,
S(1) => \rgb_blur[1]_i_6_n_0\,
S(0) => \rgb_blur[1]_i_7_n_0\
);
\rgb_blur_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(20),
Q => rgb_blur(20),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[20]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur_reg[17]_i_2_n_0\,
CO(3) => \rgb_blur_reg[20]_i_4_n_0\,
CO(2) => \rgb_blur_reg[20]_i_4_n_1\,
CO(1) => \rgb_blur_reg[20]_i_4_n_2\,
CO(0) => \rgb_blur_reg[20]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur_reg[20]_i_4_n_4\,
O(2) => \rgb_blur_reg[20]_i_4_n_5\,
O(1) => \rgb_blur_reg[20]_i_4_n_6\,
O(0) => \rgb_blur_reg[20]_i_4_n_7\,
S(3 downto 0) => p_0_in(8 downto 5)
);
\rgb_blur_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(21),
Q => rgb_blur(21),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(22),
Q => rgb_blur(22),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(23),
Q => rgb_blur(23),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[23]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur_reg[20]_i_4_n_0\,
CO(3 downto 2) => \NLW_rgb_blur_reg[23]_i_4_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur_reg[23]_i_4_n_2\,
CO(0) => \rgb_blur_reg[23]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_rgb_blur_reg[23]_i_4_O_UNCONNECTED\(3),
O(2) => \rgb_blur_reg[23]_i_4_n_5\,
O(1) => \rgb_blur_reg[23]_i_4_n_6\,
O(0) => \rgb_blur_reg[23]_i_4_n_7\,
S(3) => '0',
S(2 downto 0) => p_0_in(11 downto 9)
);
\rgb_blur_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(2),
Q => rgb_blur(2),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(3),
Q => rgb_blur(3),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(4),
Q => rgb_blur(4),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[4]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur_reg[1]_i_2_n_0\,
CO(3) => \rgb_blur_reg[4]_i_4_n_0\,
CO(2) => \rgb_blur_reg[4]_i_4_n_1\,
CO(1) => \rgb_blur_reg[4]_i_4_n_2\,
CO(0) => \rgb_blur_reg[4]_i_4_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur_reg[4]_i_4_n_4\,
O(2) => \rgb_blur_reg[4]_i_4_n_5\,
O(1) => \rgb_blur_reg[4]_i_4_n_6\,
O(0) => \rgb_blur_reg[4]_i_4_n_7\,
S(3) => \rgb_blur[4]_i_5_n_0\,
S(2) => \rgb_blur[4]_i_6_n_0\,
S(1) => \rgb_blur[4]_i_7_n_0\,
S(0) => \rgb_blur[4]_i_8_n_0\
);
\rgb_blur_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(5),
Q => rgb_blur(5),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(6),
Q => rgb_blur(6),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(7),
Q => rgb_blur(7),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_blur_reg[4]_i_4_n_0\,
CO(3 downto 2) => \NLW_rgb_blur_reg[7]_i_3_CO_UNCONNECTED\(3 downto 2),
CO(1) => \rgb_blur_reg[7]_i_3_n_2\,
CO(0) => \rgb_blur_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_rgb_blur_reg[7]_i_3_O_UNCONNECTED\(3),
O(2) => \rgb_blur_reg[7]_i_3_n_5\,
O(1) => \rgb_blur_reg[7]_i_3_n_6\,
O(0) => \rgb_blur_reg[7]_i_3_n_7\,
S(3) => '0',
S(2) => \rgb_blur[7]_i_5_n_0\,
S(1) => \rgb_blur[7]_i_6_n_0\,
S(0) => \rgb_blur[7]_i_7_n_0\
);
\rgb_blur_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(8),
Q => rgb_blur(8),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => p_7_out(9),
Q => rgb_blur(9),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_blur_reg[9]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_blur_reg[9]_i_2_n_0\,
CO(2) => \rgb_blur_reg[9]_i_2_n_1\,
CO(1) => \rgb_blur_reg[9]_i_2_n_2\,
CO(0) => \rgb_blur_reg[9]_i_2_n_3\,
CYINIT => \rgb_blur[9]_i_3_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \rgb_blur_reg[9]_i_2_n_4\,
O(2 downto 0) => \NLW_rgb_blur_reg[9]_i_2_O_UNCONNECTED\(2 downto 0),
S(3) => \rgb_blur[9]_i_4_n_0\,
S(2) => \rgb_blur[9]_i_5_n_0\,
S(1) => \rgb_blur[9]_i_6_n_0\,
S(0) => \rgb_blur[9]_i_7_n_0\
);
\rgb_buffer_reg[1026][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][0]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][0]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][0]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][10]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][10]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][10]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][11]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][11]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][11]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][12]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][12]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][12]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][13]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][13]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][13]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][14]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][14]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][14]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][15]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][15]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][15]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][16]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][16]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][16]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][17]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][17]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][17]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][18]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][18]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][18]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][19]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][19]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][19]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][1]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][1]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][1]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][20]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][20]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][20]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][21]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][21]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][21]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][22]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][22]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][22]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][23]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][23]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][23]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][2]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][2]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][2]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][3]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][3]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][3]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][4]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][4]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][4]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][5]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][5]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][5]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][6]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][6]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][6]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][7]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][7]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][7]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][8]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][8]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][8]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1026][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[994][9]_srl32_n_1\,
Q => \rgb_buffer_reg[1026][9]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1026][9]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1058][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][0]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][0]_srl32_n_1\
);
\rgb_buffer_reg[1058][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][10]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][10]_srl32_n_1\
);
\rgb_buffer_reg[1058][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][11]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][11]_srl32_n_1\
);
\rgb_buffer_reg[1058][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][12]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][12]_srl32_n_1\
);
\rgb_buffer_reg[1058][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][13]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][13]_srl32_n_1\
);
\rgb_buffer_reg[1058][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][14]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][14]_srl32_n_1\
);
\rgb_buffer_reg[1058][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][15]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][15]_srl32_n_1\
);
\rgb_buffer_reg[1058][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][16]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][16]_srl32_n_1\
);
\rgb_buffer_reg[1058][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][17]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][17]_srl32_n_1\
);
\rgb_buffer_reg[1058][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][18]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][18]_srl32_n_1\
);
\rgb_buffer_reg[1058][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][19]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][19]_srl32_n_1\
);
\rgb_buffer_reg[1058][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][1]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][1]_srl32_n_1\
);
\rgb_buffer_reg[1058][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][20]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][20]_srl32_n_1\
);
\rgb_buffer_reg[1058][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][21]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][21]_srl32_n_1\
);
\rgb_buffer_reg[1058][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][22]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][22]_srl32_n_1\
);
\rgb_buffer_reg[1058][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][23]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][23]_srl32_n_1\
);
\rgb_buffer_reg[1058][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][2]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][2]_srl32_n_1\
);
\rgb_buffer_reg[1058][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][3]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][3]_srl32_n_1\
);
\rgb_buffer_reg[1058][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][4]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][4]_srl32_n_1\
);
\rgb_buffer_reg[1058][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][5]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][5]_srl32_n_1\
);
\rgb_buffer_reg[1058][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][6]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][6]_srl32_n_1\
);
\rgb_buffer_reg[1058][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][7]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][7]_srl32_n_1\
);
\rgb_buffer_reg[1058][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][8]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][8]_srl32_n_1\
);
\rgb_buffer_reg[1058][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1026][9]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1058][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1058][9]_srl32_n_1\
);
\rgb_buffer_reg[1090][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][0]_srl32_n_1\
);
\rgb_buffer_reg[1090][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][10]_srl32_n_1\
);
\rgb_buffer_reg[1090][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][11]_srl32_n_1\
);
\rgb_buffer_reg[1090][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][12]_srl32_n_1\
);
\rgb_buffer_reg[1090][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][13]_srl32_n_1\
);
\rgb_buffer_reg[1090][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][14]_srl32_n_1\
);
\rgb_buffer_reg[1090][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][15]_srl32_n_1\
);
\rgb_buffer_reg[1090][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][16]_srl32_n_1\
);
\rgb_buffer_reg[1090][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][17]_srl32_n_1\
);
\rgb_buffer_reg[1090][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][18]_srl32_n_1\
);
\rgb_buffer_reg[1090][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][19]_srl32_n_1\
);
\rgb_buffer_reg[1090][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][1]_srl32_n_1\
);
\rgb_buffer_reg[1090][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][20]_srl32_n_1\
);
\rgb_buffer_reg[1090][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][21]_srl32_n_1\
);
\rgb_buffer_reg[1090][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][22]_srl32_n_1\
);
\rgb_buffer_reg[1090][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][23]_srl32_n_1\
);
\rgb_buffer_reg[1090][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][2]_srl32_n_1\
);
\rgb_buffer_reg[1090][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][3]_srl32_n_1\
);
\rgb_buffer_reg[1090][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][4]_srl32_n_1\
);
\rgb_buffer_reg[1090][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][5]_srl32_n_1\
);
\rgb_buffer_reg[1090][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][6]_srl32_n_1\
);
\rgb_buffer_reg[1090][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][7]_srl32_n_1\
);
\rgb_buffer_reg[1090][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][8]_srl32_n_1\
);
\rgb_buffer_reg[1090][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1058][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1090][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1090][9]_srl32_n_1\
);
\rgb_buffer_reg[1122][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][0]_srl32_n_1\
);
\rgb_buffer_reg[1122][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][10]_srl32_n_1\
);
\rgb_buffer_reg[1122][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][11]_srl32_n_1\
);
\rgb_buffer_reg[1122][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][12]_srl32_n_1\
);
\rgb_buffer_reg[1122][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][13]_srl32_n_1\
);
\rgb_buffer_reg[1122][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][14]_srl32_n_1\
);
\rgb_buffer_reg[1122][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][15]_srl32_n_1\
);
\rgb_buffer_reg[1122][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][16]_srl32_n_1\
);
\rgb_buffer_reg[1122][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][17]_srl32_n_1\
);
\rgb_buffer_reg[1122][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][18]_srl32_n_1\
);
\rgb_buffer_reg[1122][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][19]_srl32_n_1\
);
\rgb_buffer_reg[1122][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][1]_srl32_n_1\
);
\rgb_buffer_reg[1122][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][20]_srl32_n_1\
);
\rgb_buffer_reg[1122][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][21]_srl32_n_1\
);
\rgb_buffer_reg[1122][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][22]_srl32_n_1\
);
\rgb_buffer_reg[1122][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][23]_srl32_n_1\
);
\rgb_buffer_reg[1122][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][2]_srl32_n_1\
);
\rgb_buffer_reg[1122][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][3]_srl32_n_1\
);
\rgb_buffer_reg[1122][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][4]_srl32_n_1\
);
\rgb_buffer_reg[1122][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][5]_srl32_n_1\
);
\rgb_buffer_reg[1122][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][6]_srl32_n_1\
);
\rgb_buffer_reg[1122][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][7]_srl32_n_1\
);
\rgb_buffer_reg[1122][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][8]_srl32_n_1\
);
\rgb_buffer_reg[1122][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1090][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1122][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1122][9]_srl32_n_1\
);
\rgb_buffer_reg[1154][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][0]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][0]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][0]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][10]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][10]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][10]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][11]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][11]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][11]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][12]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][12]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][12]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][13]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][13]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][13]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][14]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][14]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][14]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][15]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][15]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][15]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][16]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][16]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][16]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][17]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][17]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][17]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][18]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][18]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][18]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][19]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][19]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][19]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][1]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][1]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][1]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][20]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][20]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][20]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][21]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][21]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][21]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][22]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][22]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][22]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][23]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][23]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][23]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][2]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][2]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][2]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][3]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][3]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][3]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][4]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][4]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][4]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][5]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][5]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][5]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][6]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][6]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][6]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][7]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][7]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][7]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][8]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][8]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][8]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1154][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1122][9]_srl32_n_1\,
Q => \rgb_buffer_reg[1154][9]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[1154][9]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1186][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][0]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][0]_srl32_n_1\
);
\rgb_buffer_reg[1186][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][10]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][10]_srl32_n_1\
);
\rgb_buffer_reg[1186][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][11]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][11]_srl32_n_1\
);
\rgb_buffer_reg[1186][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][12]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][12]_srl32_n_1\
);
\rgb_buffer_reg[1186][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][13]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][13]_srl32_n_1\
);
\rgb_buffer_reg[1186][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][14]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][14]_srl32_n_1\
);
\rgb_buffer_reg[1186][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][15]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][15]_srl32_n_1\
);
\rgb_buffer_reg[1186][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][16]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][16]_srl32_n_1\
);
\rgb_buffer_reg[1186][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][17]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][17]_srl32_n_1\
);
\rgb_buffer_reg[1186][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][18]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][18]_srl32_n_1\
);
\rgb_buffer_reg[1186][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][19]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][19]_srl32_n_1\
);
\rgb_buffer_reg[1186][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][1]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][1]_srl32_n_1\
);
\rgb_buffer_reg[1186][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][20]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][20]_srl32_n_1\
);
\rgb_buffer_reg[1186][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][21]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][21]_srl32_n_1\
);
\rgb_buffer_reg[1186][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][22]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][22]_srl32_n_1\
);
\rgb_buffer_reg[1186][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][23]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][23]_srl32_n_1\
);
\rgb_buffer_reg[1186][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][2]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][2]_srl32_n_1\
);
\rgb_buffer_reg[1186][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][3]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][3]_srl32_n_1\
);
\rgb_buffer_reg[1186][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][4]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][4]_srl32_n_1\
);
\rgb_buffer_reg[1186][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][5]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][5]_srl32_n_1\
);
\rgb_buffer_reg[1186][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][6]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][6]_srl32_n_1\
);
\rgb_buffer_reg[1186][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][7]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][7]_srl32_n_1\
);
\rgb_buffer_reg[1186][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][8]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][8]_srl32_n_1\
);
\rgb_buffer_reg[1186][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1154][9]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[1186][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1186][9]_srl32_n_1\
);
\rgb_buffer_reg[1218][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][0]_srl32_n_1\
);
\rgb_buffer_reg[1218][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][10]_srl32_n_1\
);
\rgb_buffer_reg[1218][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][11]_srl32_n_1\
);
\rgb_buffer_reg[1218][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][12]_srl32_n_1\
);
\rgb_buffer_reg[1218][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][13]_srl32_n_1\
);
\rgb_buffer_reg[1218][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][14]_srl32_n_1\
);
\rgb_buffer_reg[1218][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][15]_srl32_n_1\
);
\rgb_buffer_reg[1218][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][16]_srl32_n_1\
);
\rgb_buffer_reg[1218][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][17]_srl32_n_1\
);
\rgb_buffer_reg[1218][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][18]_srl32_n_1\
);
\rgb_buffer_reg[1218][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][19]_srl32_n_1\
);
\rgb_buffer_reg[1218][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][1]_srl32_n_1\
);
\rgb_buffer_reg[1218][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][20]_srl32_n_1\
);
\rgb_buffer_reg[1218][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][21]_srl32_n_1\
);
\rgb_buffer_reg[1218][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][22]_srl32_n_1\
);
\rgb_buffer_reg[1218][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][23]_srl32_n_1\
);
\rgb_buffer_reg[1218][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][2]_srl32_n_1\
);
\rgb_buffer_reg[1218][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][3]_srl32_n_1\
);
\rgb_buffer_reg[1218][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][4]_srl32_n_1\
);
\rgb_buffer_reg[1218][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][5]_srl32_n_1\
);
\rgb_buffer_reg[1218][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][6]_srl32_n_1\
);
\rgb_buffer_reg[1218][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][7]_srl32_n_1\
);
\rgb_buffer_reg[1218][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][8]_srl32_n_1\
);
\rgb_buffer_reg[1218][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1186][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1218][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1218][9]_srl32_n_1\
);
\rgb_buffer_reg[1250][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][0]_srl32_n_1\
);
\rgb_buffer_reg[1250][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][10]_srl32_n_1\
);
\rgb_buffer_reg[1250][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][11]_srl32_n_1\
);
\rgb_buffer_reg[1250][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][12]_srl32_n_1\
);
\rgb_buffer_reg[1250][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][13]_srl32_n_1\
);
\rgb_buffer_reg[1250][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][14]_srl32_n_1\
);
\rgb_buffer_reg[1250][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][15]_srl32_n_1\
);
\rgb_buffer_reg[1250][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][16]_srl32_n_1\
);
\rgb_buffer_reg[1250][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][17]_srl32_n_1\
);
\rgb_buffer_reg[1250][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][18]_srl32_n_1\
);
\rgb_buffer_reg[1250][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][19]_srl32_n_1\
);
\rgb_buffer_reg[1250][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][1]_srl32_n_1\
);
\rgb_buffer_reg[1250][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][20]_srl32_n_1\
);
\rgb_buffer_reg[1250][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][21]_srl32_n_1\
);
\rgb_buffer_reg[1250][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][22]_srl32_n_1\
);
\rgb_buffer_reg[1250][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][23]_srl32_n_1\
);
\rgb_buffer_reg[1250][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][2]_srl32_n_1\
);
\rgb_buffer_reg[1250][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][3]_srl32_n_1\
);
\rgb_buffer_reg[1250][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][4]_srl32_n_1\
);
\rgb_buffer_reg[1250][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][5]_srl32_n_1\
);
\rgb_buffer_reg[1250][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][6]_srl32_n_1\
);
\rgb_buffer_reg[1250][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][7]_srl32_n_1\
);
\rgb_buffer_reg[1250][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][8]_srl32_n_1\
);
\rgb_buffer_reg[1250][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1218][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[1250][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[1250][9]_srl32_n_1\
);
\rgb_buffer_reg[1279][0]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][0]_srl32_n_1\,
Q => \C[0]__0\,
Q31 => \NLW_rgb_buffer_reg[1279][0]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][10]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][10]_srl32_n_1\,
Q => \C[2]__2\,
Q31 => \NLW_rgb_buffer_reg[1279][10]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][11]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][11]_srl32_n_1\,
Q => \C[3]__2\,
Q31 => \NLW_rgb_buffer_reg[1279][11]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][12]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][12]_srl32_n_1\,
Q => \C[4]__2\,
Q31 => \NLW_rgb_buffer_reg[1279][12]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][13]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][13]_srl32_n_1\,
Q => \C[5]__2\,
Q31 => \NLW_rgb_buffer_reg[1279][13]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][14]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][14]_srl32_n_1\,
Q => \C[6]__2\,
Q31 => \NLW_rgb_buffer_reg[1279][14]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][15]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][15]_srl32_n_1\,
Q => \C[7]__2\,
Q31 => \NLW_rgb_buffer_reg[1279][15]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][16]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][16]_srl32_n_1\,
Q => \C[0]__4\,
Q31 => \NLW_rgb_buffer_reg[1279][16]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][17]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][17]_srl32_n_1\,
Q => \C[1]__4\,
Q31 => \NLW_rgb_buffer_reg[1279][17]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][18]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][18]_srl32_n_1\,
Q => \C[2]__4\,
Q31 => \NLW_rgb_buffer_reg[1279][18]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][19]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][19]_srl32_n_1\,
Q => \C[3]__4\,
Q31 => \NLW_rgb_buffer_reg[1279][19]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][1]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][1]_srl32_n_1\,
Q => \C[1]__0\,
Q31 => \NLW_rgb_buffer_reg[1279][1]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][20]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][20]_srl32_n_1\,
Q => \C[4]__4\,
Q31 => \NLW_rgb_buffer_reg[1279][20]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][21]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][21]_srl32_n_1\,
Q => \C[5]__4\,
Q31 => \NLW_rgb_buffer_reg[1279][21]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][22]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][22]_srl32_n_1\,
Q => \C[6]__4\,
Q31 => \NLW_rgb_buffer_reg[1279][22]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][23]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][23]_srl32_n_1\,
Q => \C[7]__4\,
Q31 => \NLW_rgb_buffer_reg[1279][23]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][2]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][2]_srl32_n_1\,
Q => \C[2]__0\,
Q31 => \NLW_rgb_buffer_reg[1279][2]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][3]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][3]_srl32_n_1\,
Q => \C[3]__0\,
Q31 => \NLW_rgb_buffer_reg[1279][3]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][4]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][4]_srl32_n_1\,
Q => \C[4]__0\,
Q31 => \NLW_rgb_buffer_reg[1279][4]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][5]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][5]_srl32_n_1\,
Q => \C[5]__0\,
Q31 => \NLW_rgb_buffer_reg[1279][5]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][6]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][6]_srl32_n_1\,
Q => \C[6]__0\,
Q31 => \NLW_rgb_buffer_reg[1279][6]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][7]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][7]_srl32_n_1\,
Q => \C[7]__0\,
Q31 => \NLW_rgb_buffer_reg[1279][7]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][8]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][8]_srl32_n_1\,
Q => \C[0]__2\,
Q31 => \NLW_rgb_buffer_reg[1279][8]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[1279][9]_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[1250][9]_srl32_n_1\,
Q => \C[1]__2\,
Q31 => \NLW_rgb_buffer_reg[1279][9]_srl29_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][0]_srl32_n_1\,
Q => \rgb_buffer_reg[130][0]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][0]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][10]_srl32_n_1\,
Q => \rgb_buffer_reg[130][10]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][10]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][11]_srl32_n_1\,
Q => \rgb_buffer_reg[130][11]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][11]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][12]_srl32_n_1\,
Q => \rgb_buffer_reg[130][12]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][12]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][13]_srl32_n_1\,
Q => \rgb_buffer_reg[130][13]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][13]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][14]_srl32_n_1\,
Q => \rgb_buffer_reg[130][14]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][14]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][15]_srl32_n_1\,
Q => \rgb_buffer_reg[130][15]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][15]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][16]_srl32_n_1\,
Q => \rgb_buffer_reg[130][16]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][16]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][17]_srl32_n_1\,
Q => \rgb_buffer_reg[130][17]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][17]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][18]_srl32_n_1\,
Q => \rgb_buffer_reg[130][18]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][18]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][19]_srl32_n_1\,
Q => \rgb_buffer_reg[130][19]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][19]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][1]_srl32_n_1\,
Q => \rgb_buffer_reg[130][1]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][1]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][20]_srl32_n_1\,
Q => \rgb_buffer_reg[130][20]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][20]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][21]_srl32_n_1\,
Q => \rgb_buffer_reg[130][21]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][21]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][22]_srl32_n_1\,
Q => \rgb_buffer_reg[130][22]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][22]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][23]_srl32_n_1\,
Q => \rgb_buffer_reg[130][23]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][23]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][2]_srl32_n_1\,
Q => \rgb_buffer_reg[130][2]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][2]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][3]_srl32_n_1\,
Q => \rgb_buffer_reg[130][3]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][3]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][4]_srl32_n_1\,
Q => \rgb_buffer_reg[130][4]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][4]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][5]_srl32_n_1\,
Q => \rgb_buffer_reg[130][5]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][5]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][6]_srl32_n_1\,
Q => \rgb_buffer_reg[130][6]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][6]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][7]_srl32_n_1\,
Q => \rgb_buffer_reg[130][7]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][7]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][8]_srl32_n_1\,
Q => \rgb_buffer_reg[130][8]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][8]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[130][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[98][9]_srl32_n_1\,
Q => \rgb_buffer_reg[130][9]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[130][9]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[162][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][0]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][0]_srl32_n_1\
);
\rgb_buffer_reg[162][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][10]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][10]_srl32_n_1\
);
\rgb_buffer_reg[162][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][11]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][11]_srl32_n_1\
);
\rgb_buffer_reg[162][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][12]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][12]_srl32_n_1\
);
\rgb_buffer_reg[162][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][13]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][13]_srl32_n_1\
);
\rgb_buffer_reg[162][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][14]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][14]_srl32_n_1\
);
\rgb_buffer_reg[162][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][15]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][15]_srl32_n_1\
);
\rgb_buffer_reg[162][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][16]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][16]_srl32_n_1\
);
\rgb_buffer_reg[162][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][17]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][17]_srl32_n_1\
);
\rgb_buffer_reg[162][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][18]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][18]_srl32_n_1\
);
\rgb_buffer_reg[162][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][19]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][19]_srl32_n_1\
);
\rgb_buffer_reg[162][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][1]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][1]_srl32_n_1\
);
\rgb_buffer_reg[162][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][20]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][20]_srl32_n_1\
);
\rgb_buffer_reg[162][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][21]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][21]_srl32_n_1\
);
\rgb_buffer_reg[162][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][22]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][22]_srl32_n_1\
);
\rgb_buffer_reg[162][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][23]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][23]_srl32_n_1\
);
\rgb_buffer_reg[162][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][2]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][2]_srl32_n_1\
);
\rgb_buffer_reg[162][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][3]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][3]_srl32_n_1\
);
\rgb_buffer_reg[162][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][4]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][4]_srl32_n_1\
);
\rgb_buffer_reg[162][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][5]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][5]_srl32_n_1\
);
\rgb_buffer_reg[162][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][6]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][6]_srl32_n_1\
);
\rgb_buffer_reg[162][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][7]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][7]_srl32_n_1\
);
\rgb_buffer_reg[162][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][8]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][8]_srl32_n_1\
);
\rgb_buffer_reg[162][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[130][9]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[162][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[162][9]_srl32_n_1\
);
\rgb_buffer_reg[194][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][0]_srl32_n_1\
);
\rgb_buffer_reg[194][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][10]_srl32_n_1\
);
\rgb_buffer_reg[194][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][11]_srl32_n_1\
);
\rgb_buffer_reg[194][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][12]_srl32_n_1\
);
\rgb_buffer_reg[194][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][13]_srl32_n_1\
);
\rgb_buffer_reg[194][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][14]_srl32_n_1\
);
\rgb_buffer_reg[194][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][15]_srl32_n_1\
);
\rgb_buffer_reg[194][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][16]_srl32_n_1\
);
\rgb_buffer_reg[194][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][17]_srl32_n_1\
);
\rgb_buffer_reg[194][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][18]_srl32_n_1\
);
\rgb_buffer_reg[194][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][19]_srl32_n_1\
);
\rgb_buffer_reg[194][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][1]_srl32_n_1\
);
\rgb_buffer_reg[194][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][20]_srl32_n_1\
);
\rgb_buffer_reg[194][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][21]_srl32_n_1\
);
\rgb_buffer_reg[194][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][22]_srl32_n_1\
);
\rgb_buffer_reg[194][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][23]_srl32_n_1\
);
\rgb_buffer_reg[194][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][2]_srl32_n_1\
);
\rgb_buffer_reg[194][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][3]_srl32_n_1\
);
\rgb_buffer_reg[194][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][4]_srl32_n_1\
);
\rgb_buffer_reg[194][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][5]_srl32_n_1\
);
\rgb_buffer_reg[194][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][6]_srl32_n_1\
);
\rgb_buffer_reg[194][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][7]_srl32_n_1\
);
\rgb_buffer_reg[194][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][8]_srl32_n_1\
);
\rgb_buffer_reg[194][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[162][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[194][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[194][9]_srl32_n_1\
);
\rgb_buffer_reg[226][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][0]_srl32_n_1\
);
\rgb_buffer_reg[226][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][10]_srl32_n_1\
);
\rgb_buffer_reg[226][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][11]_srl32_n_1\
);
\rgb_buffer_reg[226][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][12]_srl32_n_1\
);
\rgb_buffer_reg[226][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][13]_srl32_n_1\
);
\rgb_buffer_reg[226][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][14]_srl32_n_1\
);
\rgb_buffer_reg[226][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][15]_srl32_n_1\
);
\rgb_buffer_reg[226][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][16]_srl32_n_1\
);
\rgb_buffer_reg[226][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][17]_srl32_n_1\
);
\rgb_buffer_reg[226][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][18]_srl32_n_1\
);
\rgb_buffer_reg[226][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][19]_srl32_n_1\
);
\rgb_buffer_reg[226][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][1]_srl32_n_1\
);
\rgb_buffer_reg[226][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][20]_srl32_n_1\
);
\rgb_buffer_reg[226][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][21]_srl32_n_1\
);
\rgb_buffer_reg[226][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][22]_srl32_n_1\
);
\rgb_buffer_reg[226][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][23]_srl32_n_1\
);
\rgb_buffer_reg[226][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][2]_srl32_n_1\
);
\rgb_buffer_reg[226][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][3]_srl32_n_1\
);
\rgb_buffer_reg[226][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][4]_srl32_n_1\
);
\rgb_buffer_reg[226][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][5]_srl32_n_1\
);
\rgb_buffer_reg[226][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][6]_srl32_n_1\
);
\rgb_buffer_reg[226][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][7]_srl32_n_1\
);
\rgb_buffer_reg[226][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][8]_srl32_n_1\
);
\rgb_buffer_reg[226][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[194][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[226][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[226][9]_srl32_n_1\
);
\rgb_buffer_reg[258][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][0]_srl32_n_1\,
Q => \rgb_buffer_reg[258][0]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][0]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][10]_srl32_n_1\,
Q => \rgb_buffer_reg[258][10]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][10]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][11]_srl32_n_1\,
Q => \rgb_buffer_reg[258][11]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][11]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][12]_srl32_n_1\,
Q => \rgb_buffer_reg[258][12]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][12]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][13]_srl32_n_1\,
Q => \rgb_buffer_reg[258][13]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][13]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][14]_srl32_n_1\,
Q => \rgb_buffer_reg[258][14]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][14]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][15]_srl32_n_1\,
Q => \rgb_buffer_reg[258][15]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][15]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][16]_srl32_n_1\,
Q => \rgb_buffer_reg[258][16]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][16]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][17]_srl32_n_1\,
Q => \rgb_buffer_reg[258][17]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][17]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][18]_srl32_n_1\,
Q => \rgb_buffer_reg[258][18]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][18]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][19]_srl32_n_1\,
Q => \rgb_buffer_reg[258][19]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][19]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][1]_srl32_n_1\,
Q => \rgb_buffer_reg[258][1]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][1]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][20]_srl32_n_1\,
Q => \rgb_buffer_reg[258][20]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][20]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][21]_srl32_n_1\,
Q => \rgb_buffer_reg[258][21]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][21]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][22]_srl32_n_1\,
Q => \rgb_buffer_reg[258][22]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][22]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][23]_srl32_n_1\,
Q => \rgb_buffer_reg[258][23]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][23]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][2]_srl32_n_1\,
Q => \rgb_buffer_reg[258][2]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][2]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][3]_srl32_n_1\,
Q => \rgb_buffer_reg[258][3]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][3]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][4]_srl32_n_1\,
Q => \rgb_buffer_reg[258][4]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][4]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][5]_srl32_n_1\,
Q => \rgb_buffer_reg[258][5]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][5]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][6]_srl32_n_1\,
Q => \rgb_buffer_reg[258][6]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][6]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][7]_srl32_n_1\,
Q => \rgb_buffer_reg[258][7]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][7]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][8]_srl32_n_1\,
Q => \rgb_buffer_reg[258][8]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][8]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[258][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[226][9]_srl32_n_1\,
Q => \rgb_buffer_reg[258][9]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[258][9]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[290][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][0]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][0]_srl32_n_1\
);
\rgb_buffer_reg[290][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][10]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][10]_srl32_n_1\
);
\rgb_buffer_reg[290][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][11]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][11]_srl32_n_1\
);
\rgb_buffer_reg[290][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][12]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][12]_srl32_n_1\
);
\rgb_buffer_reg[290][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][13]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][13]_srl32_n_1\
);
\rgb_buffer_reg[290][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][14]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][14]_srl32_n_1\
);
\rgb_buffer_reg[290][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][15]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][15]_srl32_n_1\
);
\rgb_buffer_reg[290][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][16]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][16]_srl32_n_1\
);
\rgb_buffer_reg[290][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][17]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][17]_srl32_n_1\
);
\rgb_buffer_reg[290][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][18]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][18]_srl32_n_1\
);
\rgb_buffer_reg[290][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][19]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][19]_srl32_n_1\
);
\rgb_buffer_reg[290][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][1]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][1]_srl32_n_1\
);
\rgb_buffer_reg[290][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][20]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][20]_srl32_n_1\
);
\rgb_buffer_reg[290][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][21]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][21]_srl32_n_1\
);
\rgb_buffer_reg[290][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][22]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][22]_srl32_n_1\
);
\rgb_buffer_reg[290][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][23]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][23]_srl32_n_1\
);
\rgb_buffer_reg[290][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][2]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][2]_srl32_n_1\
);
\rgb_buffer_reg[290][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][3]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][3]_srl32_n_1\
);
\rgb_buffer_reg[290][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][4]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][4]_srl32_n_1\
);
\rgb_buffer_reg[290][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][5]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][5]_srl32_n_1\
);
\rgb_buffer_reg[290][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][6]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][6]_srl32_n_1\
);
\rgb_buffer_reg[290][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][7]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][7]_srl32_n_1\
);
\rgb_buffer_reg[290][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][8]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][8]_srl32_n_1\
);
\rgb_buffer_reg[290][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[258][9]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[290][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[290][9]_srl32_n_1\
);
\rgb_buffer_reg[322][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][0]_srl32_n_1\
);
\rgb_buffer_reg[322][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][10]_srl32_n_1\
);
\rgb_buffer_reg[322][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][11]_srl32_n_1\
);
\rgb_buffer_reg[322][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][12]_srl32_n_1\
);
\rgb_buffer_reg[322][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][13]_srl32_n_1\
);
\rgb_buffer_reg[322][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][14]_srl32_n_1\
);
\rgb_buffer_reg[322][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][15]_srl32_n_1\
);
\rgb_buffer_reg[322][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][16]_srl32_n_1\
);
\rgb_buffer_reg[322][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][17]_srl32_n_1\
);
\rgb_buffer_reg[322][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][18]_srl32_n_1\
);
\rgb_buffer_reg[322][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][19]_srl32_n_1\
);
\rgb_buffer_reg[322][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][1]_srl32_n_1\
);
\rgb_buffer_reg[322][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][20]_srl32_n_1\
);
\rgb_buffer_reg[322][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][21]_srl32_n_1\
);
\rgb_buffer_reg[322][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][22]_srl32_n_1\
);
\rgb_buffer_reg[322][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][23]_srl32_n_1\
);
\rgb_buffer_reg[322][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][2]_srl32_n_1\
);
\rgb_buffer_reg[322][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][3]_srl32_n_1\
);
\rgb_buffer_reg[322][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][4]_srl32_n_1\
);
\rgb_buffer_reg[322][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][5]_srl32_n_1\
);
\rgb_buffer_reg[322][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][6]_srl32_n_1\
);
\rgb_buffer_reg[322][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][7]_srl32_n_1\
);
\rgb_buffer_reg[322][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][8]_srl32_n_1\
);
\rgb_buffer_reg[322][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[290][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[322][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[322][9]_srl32_n_1\
);
\rgb_buffer_reg[34][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[0]\,
Q => \NLW_rgb_buffer_reg[34][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][0]_srl32_n_1\
);
\rgb_buffer_reg[34][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[2]__4\,
Q => \NLW_rgb_buffer_reg[34][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][10]_srl32_n_1\
);
\rgb_buffer_reg[34][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[3]__4\,
Q => \NLW_rgb_buffer_reg[34][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][11]_srl32_n_1\
);
\rgb_buffer_reg[34][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[4]__4\,
Q => \NLW_rgb_buffer_reg[34][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][12]_srl32_n_1\
);
\rgb_buffer_reg[34][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[5]__4\,
Q => \NLW_rgb_buffer_reg[34][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][13]_srl32_n_1\
);
\rgb_buffer_reg[34][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[6]__4\,
Q => \NLW_rgb_buffer_reg[34][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][14]_srl32_n_1\
);
\rgb_buffer_reg[34][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[7]__4\,
Q => \NLW_rgb_buffer_reg[34][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][15]_srl32_n_1\
);
\rgb_buffer_reg[34][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[0]__7\,
Q => \NLW_rgb_buffer_reg[34][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][16]_srl32_n_1\
);
\rgb_buffer_reg[34][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[1]__8\,
Q => \NLW_rgb_buffer_reg[34][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][17]_srl32_n_1\
);
\rgb_buffer_reg[34][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[2]__8\,
Q => \NLW_rgb_buffer_reg[34][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][18]_srl32_n_1\
);
\rgb_buffer_reg[34][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[3]__8\,
Q => \NLW_rgb_buffer_reg[34][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][19]_srl32_n_1\
);
\rgb_buffer_reg[34][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[1]__0\,
Q => \NLW_rgb_buffer_reg[34][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][1]_srl32_n_1\
);
\rgb_buffer_reg[34][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[4]__8\,
Q => \NLW_rgb_buffer_reg[34][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][20]_srl32_n_1\
);
\rgb_buffer_reg[34][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[5]__8\,
Q => \NLW_rgb_buffer_reg[34][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][21]_srl32_n_1\
);
\rgb_buffer_reg[34][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[6]__8\,
Q => \NLW_rgb_buffer_reg[34][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][22]_srl32_n_1\
);
\rgb_buffer_reg[34][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[7]__8\,
Q => \NLW_rgb_buffer_reg[34][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][23]_srl32_n_1\
);
\rgb_buffer_reg[34][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[2]__0\,
Q => \NLW_rgb_buffer_reg[34][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][2]_srl32_n_1\
);
\rgb_buffer_reg[34][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[3]__0\,
Q => \NLW_rgb_buffer_reg[34][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][3]_srl32_n_1\
);
\rgb_buffer_reg[34][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[4]__0\,
Q => \NLW_rgb_buffer_reg[34][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][4]_srl32_n_1\
);
\rgb_buffer_reg[34][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[5]__0\,
Q => \NLW_rgb_buffer_reg[34][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][5]_srl32_n_1\
);
\rgb_buffer_reg[34][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[6]__0\,
Q => \NLW_rgb_buffer_reg[34][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][6]_srl32_n_1\
);
\rgb_buffer_reg[34][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[7]__0\,
Q => \NLW_rgb_buffer_reg[34][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][7]_srl32_n_1\
);
\rgb_buffer_reg[34][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[0]__3\,
Q => \NLW_rgb_buffer_reg[34][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][8]_srl32_n_1\
);
\rgb_buffer_reg[34][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \B[1]__4\,
Q => \NLW_rgb_buffer_reg[34][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[34][9]_srl32_n_1\
);
\rgb_buffer_reg[354][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][0]_srl32_n_1\
);
\rgb_buffer_reg[354][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][10]_srl32_n_1\
);
\rgb_buffer_reg[354][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][11]_srl32_n_1\
);
\rgb_buffer_reg[354][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][12]_srl32_n_1\
);
\rgb_buffer_reg[354][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][13]_srl32_n_1\
);
\rgb_buffer_reg[354][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][14]_srl32_n_1\
);
\rgb_buffer_reg[354][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][15]_srl32_n_1\
);
\rgb_buffer_reg[354][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][16]_srl32_n_1\
);
\rgb_buffer_reg[354][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][17]_srl32_n_1\
);
\rgb_buffer_reg[354][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][18]_srl32_n_1\
);
\rgb_buffer_reg[354][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][19]_srl32_n_1\
);
\rgb_buffer_reg[354][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][1]_srl32_n_1\
);
\rgb_buffer_reg[354][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][20]_srl32_n_1\
);
\rgb_buffer_reg[354][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][21]_srl32_n_1\
);
\rgb_buffer_reg[354][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][22]_srl32_n_1\
);
\rgb_buffer_reg[354][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][23]_srl32_n_1\
);
\rgb_buffer_reg[354][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][2]_srl32_n_1\
);
\rgb_buffer_reg[354][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][3]_srl32_n_1\
);
\rgb_buffer_reg[354][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][4]_srl32_n_1\
);
\rgb_buffer_reg[354][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][5]_srl32_n_1\
);
\rgb_buffer_reg[354][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][6]_srl32_n_1\
);
\rgb_buffer_reg[354][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][7]_srl32_n_1\
);
\rgb_buffer_reg[354][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][8]_srl32_n_1\
);
\rgb_buffer_reg[354][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[322][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[354][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[354][9]_srl32_n_1\
);
\rgb_buffer_reg[386][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][0]_srl32_n_1\,
Q => \rgb_buffer_reg[386][0]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][0]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][10]_srl32_n_1\,
Q => \rgb_buffer_reg[386][10]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][10]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][11]_srl32_n_1\,
Q => \rgb_buffer_reg[386][11]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][11]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][12]_srl32_n_1\,
Q => \rgb_buffer_reg[386][12]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][12]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][13]_srl32_n_1\,
Q => \rgb_buffer_reg[386][13]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][13]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][14]_srl32_n_1\,
Q => \rgb_buffer_reg[386][14]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][14]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][15]_srl32_n_1\,
Q => \rgb_buffer_reg[386][15]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][15]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][16]_srl32_n_1\,
Q => \rgb_buffer_reg[386][16]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][16]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][17]_srl32_n_1\,
Q => \rgb_buffer_reg[386][17]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][17]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][18]_srl32_n_1\,
Q => \rgb_buffer_reg[386][18]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][18]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][19]_srl32_n_1\,
Q => \rgb_buffer_reg[386][19]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][19]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][1]_srl32_n_1\,
Q => \rgb_buffer_reg[386][1]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][1]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][20]_srl32_n_1\,
Q => \rgb_buffer_reg[386][20]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][20]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][21]_srl32_n_1\,
Q => \rgb_buffer_reg[386][21]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][21]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][22]_srl32_n_1\,
Q => \rgb_buffer_reg[386][22]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][22]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][23]_srl32_n_1\,
Q => \rgb_buffer_reg[386][23]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][23]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][2]_srl32_n_1\,
Q => \rgb_buffer_reg[386][2]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][2]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][3]_srl32_n_1\,
Q => \rgb_buffer_reg[386][3]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][3]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][4]_srl32_n_1\,
Q => \rgb_buffer_reg[386][4]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][4]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][5]_srl32_n_1\,
Q => \rgb_buffer_reg[386][5]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][5]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][6]_srl32_n_1\,
Q => \rgb_buffer_reg[386][6]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][6]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][7]_srl32_n_1\,
Q => \rgb_buffer_reg[386][7]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][7]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][8]_srl32_n_1\,
Q => \rgb_buffer_reg[386][8]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][8]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[386][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[354][9]_srl32_n_1\,
Q => \rgb_buffer_reg[386][9]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[386][9]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[418][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][0]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][0]_srl32_n_1\
);
\rgb_buffer_reg[418][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][10]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][10]_srl32_n_1\
);
\rgb_buffer_reg[418][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][11]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][11]_srl32_n_1\
);
\rgb_buffer_reg[418][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][12]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][12]_srl32_n_1\
);
\rgb_buffer_reg[418][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][13]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][13]_srl32_n_1\
);
\rgb_buffer_reg[418][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][14]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][14]_srl32_n_1\
);
\rgb_buffer_reg[418][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][15]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][15]_srl32_n_1\
);
\rgb_buffer_reg[418][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][16]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][16]_srl32_n_1\
);
\rgb_buffer_reg[418][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][17]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][17]_srl32_n_1\
);
\rgb_buffer_reg[418][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][18]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][18]_srl32_n_1\
);
\rgb_buffer_reg[418][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][19]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][19]_srl32_n_1\
);
\rgb_buffer_reg[418][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][1]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][1]_srl32_n_1\
);
\rgb_buffer_reg[418][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][20]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][20]_srl32_n_1\
);
\rgb_buffer_reg[418][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][21]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][21]_srl32_n_1\
);
\rgb_buffer_reg[418][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][22]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][22]_srl32_n_1\
);
\rgb_buffer_reg[418][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][23]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][23]_srl32_n_1\
);
\rgb_buffer_reg[418][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][2]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][2]_srl32_n_1\
);
\rgb_buffer_reg[418][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][3]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][3]_srl32_n_1\
);
\rgb_buffer_reg[418][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][4]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][4]_srl32_n_1\
);
\rgb_buffer_reg[418][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][5]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][5]_srl32_n_1\
);
\rgb_buffer_reg[418][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][6]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][6]_srl32_n_1\
);
\rgb_buffer_reg[418][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][7]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][7]_srl32_n_1\
);
\rgb_buffer_reg[418][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][8]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][8]_srl32_n_1\
);
\rgb_buffer_reg[418][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[386][9]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[418][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[418][9]_srl32_n_1\
);
\rgb_buffer_reg[450][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][0]_srl32_n_1\
);
\rgb_buffer_reg[450][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][10]_srl32_n_1\
);
\rgb_buffer_reg[450][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][11]_srl32_n_1\
);
\rgb_buffer_reg[450][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][12]_srl32_n_1\
);
\rgb_buffer_reg[450][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][13]_srl32_n_1\
);
\rgb_buffer_reg[450][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][14]_srl32_n_1\
);
\rgb_buffer_reg[450][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][15]_srl32_n_1\
);
\rgb_buffer_reg[450][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][16]_srl32_n_1\
);
\rgb_buffer_reg[450][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][17]_srl32_n_1\
);
\rgb_buffer_reg[450][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][18]_srl32_n_1\
);
\rgb_buffer_reg[450][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][19]_srl32_n_1\
);
\rgb_buffer_reg[450][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][1]_srl32_n_1\
);
\rgb_buffer_reg[450][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][20]_srl32_n_1\
);
\rgb_buffer_reg[450][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][21]_srl32_n_1\
);
\rgb_buffer_reg[450][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][22]_srl32_n_1\
);
\rgb_buffer_reg[450][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][23]_srl32_n_1\
);
\rgb_buffer_reg[450][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][2]_srl32_n_1\
);
\rgb_buffer_reg[450][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][3]_srl32_n_1\
);
\rgb_buffer_reg[450][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][4]_srl32_n_1\
);
\rgb_buffer_reg[450][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][5]_srl32_n_1\
);
\rgb_buffer_reg[450][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][6]_srl32_n_1\
);
\rgb_buffer_reg[450][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][7]_srl32_n_1\
);
\rgb_buffer_reg[450][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][8]_srl32_n_1\
);
\rgb_buffer_reg[450][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[418][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[450][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[450][9]_srl32_n_1\
);
\rgb_buffer_reg[482][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][0]_srl32_n_1\
);
\rgb_buffer_reg[482][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][10]_srl32_n_1\
);
\rgb_buffer_reg[482][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][11]_srl32_n_1\
);
\rgb_buffer_reg[482][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][12]_srl32_n_1\
);
\rgb_buffer_reg[482][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][13]_srl32_n_1\
);
\rgb_buffer_reg[482][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][14]_srl32_n_1\
);
\rgb_buffer_reg[482][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][15]_srl32_n_1\
);
\rgb_buffer_reg[482][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][16]_srl32_n_1\
);
\rgb_buffer_reg[482][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][17]_srl32_n_1\
);
\rgb_buffer_reg[482][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][18]_srl32_n_1\
);
\rgb_buffer_reg[482][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][19]_srl32_n_1\
);
\rgb_buffer_reg[482][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][1]_srl32_n_1\
);
\rgb_buffer_reg[482][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][20]_srl32_n_1\
);
\rgb_buffer_reg[482][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][21]_srl32_n_1\
);
\rgb_buffer_reg[482][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][22]_srl32_n_1\
);
\rgb_buffer_reg[482][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][23]_srl32_n_1\
);
\rgb_buffer_reg[482][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][2]_srl32_n_1\
);
\rgb_buffer_reg[482][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][3]_srl32_n_1\
);
\rgb_buffer_reg[482][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][4]_srl32_n_1\
);
\rgb_buffer_reg[482][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][5]_srl32_n_1\
);
\rgb_buffer_reg[482][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][6]_srl32_n_1\
);
\rgb_buffer_reg[482][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][7]_srl32_n_1\
);
\rgb_buffer_reg[482][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][8]_srl32_n_1\
);
\rgb_buffer_reg[482][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[450][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[482][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[482][9]_srl32_n_1\
);
\rgb_buffer_reg[514][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][0]_srl32_n_1\,
Q => \rgb_buffer_reg[514][0]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][0]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][10]_srl32_n_1\,
Q => \rgb_buffer_reg[514][10]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][10]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][11]_srl32_n_1\,
Q => \rgb_buffer_reg[514][11]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][11]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][12]_srl32_n_1\,
Q => \rgb_buffer_reg[514][12]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][12]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][13]_srl32_n_1\,
Q => \rgb_buffer_reg[514][13]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][13]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][14]_srl32_n_1\,
Q => \rgb_buffer_reg[514][14]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][14]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][15]_srl32_n_1\,
Q => \rgb_buffer_reg[514][15]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][15]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][16]_srl32_n_1\,
Q => \rgb_buffer_reg[514][16]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][16]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][17]_srl32_n_1\,
Q => \rgb_buffer_reg[514][17]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][17]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][18]_srl32_n_1\,
Q => \rgb_buffer_reg[514][18]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][18]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][19]_srl32_n_1\,
Q => \rgb_buffer_reg[514][19]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][19]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][1]_srl32_n_1\,
Q => \rgb_buffer_reg[514][1]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][1]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][20]_srl32_n_1\,
Q => \rgb_buffer_reg[514][20]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][20]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][21]_srl32_n_1\,
Q => \rgb_buffer_reg[514][21]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][21]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][22]_srl32_n_1\,
Q => \rgb_buffer_reg[514][22]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][22]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][23]_srl32_n_1\,
Q => \rgb_buffer_reg[514][23]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][23]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][2]_srl32_n_1\,
Q => \rgb_buffer_reg[514][2]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][2]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][3]_srl32_n_1\,
Q => \rgb_buffer_reg[514][3]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][3]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][4]_srl32_n_1\,
Q => \rgb_buffer_reg[514][4]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][4]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][5]_srl32_n_1\,
Q => \rgb_buffer_reg[514][5]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][5]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][6]_srl32_n_1\,
Q => \rgb_buffer_reg[514][6]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][6]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][7]_srl32_n_1\,
Q => \rgb_buffer_reg[514][7]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][7]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][8]_srl32_n_1\,
Q => \rgb_buffer_reg[514][8]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][8]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[514][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[482][9]_srl32_n_1\,
Q => \rgb_buffer_reg[514][9]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[514][9]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[546][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][0]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][0]_srl32_n_1\
);
\rgb_buffer_reg[546][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][10]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][10]_srl32_n_1\
);
\rgb_buffer_reg[546][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][11]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][11]_srl32_n_1\
);
\rgb_buffer_reg[546][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][12]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][12]_srl32_n_1\
);
\rgb_buffer_reg[546][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][13]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][13]_srl32_n_1\
);
\rgb_buffer_reg[546][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][14]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][14]_srl32_n_1\
);
\rgb_buffer_reg[546][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][15]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][15]_srl32_n_1\
);
\rgb_buffer_reg[546][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][16]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][16]_srl32_n_1\
);
\rgb_buffer_reg[546][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][17]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][17]_srl32_n_1\
);
\rgb_buffer_reg[546][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][18]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][18]_srl32_n_1\
);
\rgb_buffer_reg[546][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][19]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][19]_srl32_n_1\
);
\rgb_buffer_reg[546][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][1]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][1]_srl32_n_1\
);
\rgb_buffer_reg[546][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][20]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][20]_srl32_n_1\
);
\rgb_buffer_reg[546][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][21]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][21]_srl32_n_1\
);
\rgb_buffer_reg[546][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][22]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][22]_srl32_n_1\
);
\rgb_buffer_reg[546][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][23]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][23]_srl32_n_1\
);
\rgb_buffer_reg[546][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][2]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][2]_srl32_n_1\
);
\rgb_buffer_reg[546][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][3]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][3]_srl32_n_1\
);
\rgb_buffer_reg[546][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][4]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][4]_srl32_n_1\
);
\rgb_buffer_reg[546][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][5]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][5]_srl32_n_1\
);
\rgb_buffer_reg[546][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][6]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][6]_srl32_n_1\
);
\rgb_buffer_reg[546][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][7]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][7]_srl32_n_1\
);
\rgb_buffer_reg[546][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][8]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][8]_srl32_n_1\
);
\rgb_buffer_reg[546][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[514][9]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[546][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[546][9]_srl32_n_1\
);
\rgb_buffer_reg[578][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][0]_srl32_n_1\
);
\rgb_buffer_reg[578][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][10]_srl32_n_1\
);
\rgb_buffer_reg[578][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][11]_srl32_n_1\
);
\rgb_buffer_reg[578][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][12]_srl32_n_1\
);
\rgb_buffer_reg[578][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][13]_srl32_n_1\
);
\rgb_buffer_reg[578][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][14]_srl32_n_1\
);
\rgb_buffer_reg[578][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][15]_srl32_n_1\
);
\rgb_buffer_reg[578][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][16]_srl32_n_1\
);
\rgb_buffer_reg[578][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][17]_srl32_n_1\
);
\rgb_buffer_reg[578][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][18]_srl32_n_1\
);
\rgb_buffer_reg[578][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][19]_srl32_n_1\
);
\rgb_buffer_reg[578][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][1]_srl32_n_1\
);
\rgb_buffer_reg[578][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][20]_srl32_n_1\
);
\rgb_buffer_reg[578][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][21]_srl32_n_1\
);
\rgb_buffer_reg[578][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][22]_srl32_n_1\
);
\rgb_buffer_reg[578][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][23]_srl32_n_1\
);
\rgb_buffer_reg[578][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][2]_srl32_n_1\
);
\rgb_buffer_reg[578][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][3]_srl32_n_1\
);
\rgb_buffer_reg[578][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][4]_srl32_n_1\
);
\rgb_buffer_reg[578][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][5]_srl32_n_1\
);
\rgb_buffer_reg[578][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][6]_srl32_n_1\
);
\rgb_buffer_reg[578][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][7]_srl32_n_1\
);
\rgb_buffer_reg[578][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][8]_srl32_n_1\
);
\rgb_buffer_reg[578][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[546][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[578][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[578][9]_srl32_n_1\
);
\rgb_buffer_reg[610][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][0]_srl32_Q_UNCONNECTED\,
Q31 => \A[0]__6\
);
\rgb_buffer_reg[610][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][10]_srl32_Q_UNCONNECTED\,
Q31 => \A[2]__16\
);
\rgb_buffer_reg[610][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][11]_srl32_Q_UNCONNECTED\,
Q31 => \A[3]__16\
);
\rgb_buffer_reg[610][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][12]_srl32_Q_UNCONNECTED\,
Q31 => \A[4]__16\
);
\rgb_buffer_reg[610][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][13]_srl32_Q_UNCONNECTED\,
Q31 => \A[5]__16\
);
\rgb_buffer_reg[610][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][14]_srl32_Q_UNCONNECTED\,
Q31 => \A[6]__16\
);
\rgb_buffer_reg[610][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][15]_srl32_Q_UNCONNECTED\,
Q31 => \A[7]__16\
);
\rgb_buffer_reg[610][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][16]_srl32_Q_UNCONNECTED\,
Q31 => \A[0]__26\
);
\rgb_buffer_reg[610][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][17]_srl32_Q_UNCONNECTED\,
Q31 => \A[1]__26\
);
\rgb_buffer_reg[610][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][18]_srl32_Q_UNCONNECTED\,
Q31 => \A[2]__26\
);
\rgb_buffer_reg[610][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][19]_srl32_Q_UNCONNECTED\,
Q31 => \A[3]__26\
);
\rgb_buffer_reg[610][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][1]_srl32_Q_UNCONNECTED\,
Q31 => \A[1]__6\
);
\rgb_buffer_reg[610][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][20]_srl32_Q_UNCONNECTED\,
Q31 => \A[4]__26\
);
\rgb_buffer_reg[610][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][21]_srl32_Q_UNCONNECTED\,
Q31 => \A[5]__26\
);
\rgb_buffer_reg[610][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][22]_srl32_Q_UNCONNECTED\,
Q31 => \A[6]__26\
);
\rgb_buffer_reg[610][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][23]_srl32_Q_UNCONNECTED\,
Q31 => \A[7]__26\
);
\rgb_buffer_reg[610][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][2]_srl32_Q_UNCONNECTED\,
Q31 => \A[2]__6\
);
\rgb_buffer_reg[610][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][3]_srl32_Q_UNCONNECTED\,
Q31 => \A[3]__6\
);
\rgb_buffer_reg[610][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][4]_srl32_Q_UNCONNECTED\,
Q31 => \A[4]__6\
);
\rgb_buffer_reg[610][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][5]_srl32_Q_UNCONNECTED\,
Q31 => \A[5]__6\
);
\rgb_buffer_reg[610][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][6]_srl32_Q_UNCONNECTED\,
Q31 => \A[6]__6\
);
\rgb_buffer_reg[610][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][7]_srl32_Q_UNCONNECTED\,
Q31 => \A[7]__6\
);
\rgb_buffer_reg[610][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][8]_srl32_Q_UNCONNECTED\,
Q31 => \A[0]__16\
);
\rgb_buffer_reg[610][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[578][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[610][9]_srl32_Q_UNCONNECTED\,
Q31 => \A[1]__16\
);
\rgb_buffer_reg[642][0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(0),
Q => \rgb_buffer_reg[642]\(0),
R => '0'
);
\rgb_buffer_reg[642][10]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(10),
Q => \rgb_buffer_reg[642]\(10),
R => '0'
);
\rgb_buffer_reg[642][11]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(11),
Q => \rgb_buffer_reg[642]\(11),
R => '0'
);
\rgb_buffer_reg[642][12]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(12),
Q => \rgb_buffer_reg[642]\(12),
R => '0'
);
\rgb_buffer_reg[642][13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(13),
Q => \rgb_buffer_reg[642]\(13),
R => '0'
);
\rgb_buffer_reg[642][14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(14),
Q => \rgb_buffer_reg[642]\(14),
R => '0'
);
\rgb_buffer_reg[642][15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(15),
Q => \rgb_buffer_reg[642]\(15),
R => '0'
);
\rgb_buffer_reg[642][16]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(16),
Q => \rgb_buffer_reg[642]\(16),
R => '0'
);
\rgb_buffer_reg[642][17]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(17),
Q => \rgb_buffer_reg[642]\(17),
R => '0'
);
\rgb_buffer_reg[642][18]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(18),
Q => \rgb_buffer_reg[642]\(18),
R => '0'
);
\rgb_buffer_reg[642][19]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(19),
Q => \rgb_buffer_reg[642]\(19),
R => '0'
);
\rgb_buffer_reg[642][1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(1),
Q => \rgb_buffer_reg[642]\(1),
R => '0'
);
\rgb_buffer_reg[642][20]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(20),
Q => \rgb_buffer_reg[642]\(20),
R => '0'
);
\rgb_buffer_reg[642][21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(21),
Q => \rgb_buffer_reg[642]\(21),
R => '0'
);
\rgb_buffer_reg[642][22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(22),
Q => \rgb_buffer_reg[642]\(22),
R => '0'
);
\rgb_buffer_reg[642][23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(23),
Q => \rgb_buffer_reg[642]\(23),
R => '0'
);
\rgb_buffer_reg[642][2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(2),
Q => \rgb_buffer_reg[642]\(2),
R => '0'
);
\rgb_buffer_reg[642][3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(3),
Q => \rgb_buffer_reg[642]\(3),
R => '0'
);
\rgb_buffer_reg[642][4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(4),
Q => \rgb_buffer_reg[642]\(4),
R => '0'
);
\rgb_buffer_reg[642][5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(5),
Q => \rgb_buffer_reg[642]\(5),
R => '0'
);
\rgb_buffer_reg[642][6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(6),
Q => \rgb_buffer_reg[642]\(6),
R => '0'
);
\rgb_buffer_reg[642][7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(7),
Q => \rgb_buffer_reg[642]\(7),
R => '0'
);
\rgb_buffer_reg[642][8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(8),
Q => \rgb_buffer_reg[642]\(8),
R => '0'
);
\rgb_buffer_reg[642][9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => \^active\,
D => D(9),
Q => \rgb_buffer_reg[642]\(9),
R => '0'
);
\rgb_buffer_reg[66][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][0]_srl32_n_1\
);
\rgb_buffer_reg[66][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][10]_srl32_n_1\
);
\rgb_buffer_reg[66][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][11]_srl32_n_1\
);
\rgb_buffer_reg[66][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][12]_srl32_n_1\
);
\rgb_buffer_reg[66][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][13]_srl32_n_1\
);
\rgb_buffer_reg[66][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][14]_srl32_n_1\
);
\rgb_buffer_reg[66][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][15]_srl32_n_1\
);
\rgb_buffer_reg[66][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][16]_srl32_n_1\
);
\rgb_buffer_reg[66][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][17]_srl32_n_1\
);
\rgb_buffer_reg[66][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][18]_srl32_n_1\
);
\rgb_buffer_reg[66][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][19]_srl32_n_1\
);
\rgb_buffer_reg[66][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][1]_srl32_n_1\
);
\rgb_buffer_reg[66][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][20]_srl32_n_1\
);
\rgb_buffer_reg[66][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][21]_srl32_n_1\
);
\rgb_buffer_reg[66][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][22]_srl32_n_1\
);
\rgb_buffer_reg[66][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][23]_srl32_n_1\
);
\rgb_buffer_reg[66][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][2]_srl32_n_1\
);
\rgb_buffer_reg[66][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][3]_srl32_n_1\
);
\rgb_buffer_reg[66][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][4]_srl32_n_1\
);
\rgb_buffer_reg[66][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][5]_srl32_n_1\
);
\rgb_buffer_reg[66][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][6]_srl32_n_1\
);
\rgb_buffer_reg[66][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][7]_srl32_n_1\
);
\rgb_buffer_reg[66][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][8]_srl32_n_1\
);
\rgb_buffer_reg[66][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[34][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[66][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[66][9]_srl32_n_1\
);
\rgb_buffer_reg[674][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(0),
Q => \NLW_rgb_buffer_reg[674][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][0]_srl32_n_1\
);
\rgb_buffer_reg[674][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(10),
Q => \NLW_rgb_buffer_reg[674][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][10]_srl32_n_1\
);
\rgb_buffer_reg[674][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(11),
Q => \NLW_rgb_buffer_reg[674][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][11]_srl32_n_1\
);
\rgb_buffer_reg[674][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(12),
Q => \NLW_rgb_buffer_reg[674][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][12]_srl32_n_1\
);
\rgb_buffer_reg[674][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(13),
Q => \NLW_rgb_buffer_reg[674][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][13]_srl32_n_1\
);
\rgb_buffer_reg[674][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(14),
Q => \NLW_rgb_buffer_reg[674][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][14]_srl32_n_1\
);
\rgb_buffer_reg[674][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(15),
Q => \NLW_rgb_buffer_reg[674][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][15]_srl32_n_1\
);
\rgb_buffer_reg[674][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(16),
Q => \NLW_rgb_buffer_reg[674][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][16]_srl32_n_1\
);
\rgb_buffer_reg[674][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(17),
Q => \NLW_rgb_buffer_reg[674][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][17]_srl32_n_1\
);
\rgb_buffer_reg[674][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(18),
Q => \NLW_rgb_buffer_reg[674][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][18]_srl32_n_1\
);
\rgb_buffer_reg[674][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(19),
Q => \NLW_rgb_buffer_reg[674][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][19]_srl32_n_1\
);
\rgb_buffer_reg[674][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(1),
Q => \NLW_rgb_buffer_reg[674][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][1]_srl32_n_1\
);
\rgb_buffer_reg[674][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(20),
Q => \NLW_rgb_buffer_reg[674][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][20]_srl32_n_1\
);
\rgb_buffer_reg[674][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(21),
Q => \NLW_rgb_buffer_reg[674][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][21]_srl32_n_1\
);
\rgb_buffer_reg[674][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(22),
Q => \NLW_rgb_buffer_reg[674][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][22]_srl32_n_1\
);
\rgb_buffer_reg[674][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(23),
Q => \NLW_rgb_buffer_reg[674][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][23]_srl32_n_1\
);
\rgb_buffer_reg[674][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(2),
Q => \NLW_rgb_buffer_reg[674][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][2]_srl32_n_1\
);
\rgb_buffer_reg[674][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(3),
Q => \NLW_rgb_buffer_reg[674][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][3]_srl32_n_1\
);
\rgb_buffer_reg[674][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(4),
Q => \NLW_rgb_buffer_reg[674][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][4]_srl32_n_1\
);
\rgb_buffer_reg[674][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(5),
Q => \NLW_rgb_buffer_reg[674][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][5]_srl32_n_1\
);
\rgb_buffer_reg[674][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(6),
Q => \NLW_rgb_buffer_reg[674][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][6]_srl32_n_1\
);
\rgb_buffer_reg[674][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(7),
Q => \NLW_rgb_buffer_reg[674][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][7]_srl32_n_1\
);
\rgb_buffer_reg[674][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(8),
Q => \NLW_rgb_buffer_reg[674][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][8]_srl32_n_1\
);
\rgb_buffer_reg[674][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[642]\(9),
Q => \NLW_rgb_buffer_reg[674][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[674][9]_srl32_n_1\
);
\rgb_buffer_reg[706][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][0]_srl32_n_1\
);
\rgb_buffer_reg[706][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][10]_srl32_n_1\
);
\rgb_buffer_reg[706][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][11]_srl32_n_1\
);
\rgb_buffer_reg[706][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][12]_srl32_n_1\
);
\rgb_buffer_reg[706][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][13]_srl32_n_1\
);
\rgb_buffer_reg[706][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][14]_srl32_n_1\
);
\rgb_buffer_reg[706][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][15]_srl32_n_1\
);
\rgb_buffer_reg[706][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][16]_srl32_n_1\
);
\rgb_buffer_reg[706][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][17]_srl32_n_1\
);
\rgb_buffer_reg[706][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][18]_srl32_n_1\
);
\rgb_buffer_reg[706][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][19]_srl32_n_1\
);
\rgb_buffer_reg[706][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][1]_srl32_n_1\
);
\rgb_buffer_reg[706][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][20]_srl32_n_1\
);
\rgb_buffer_reg[706][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][21]_srl32_n_1\
);
\rgb_buffer_reg[706][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][22]_srl32_n_1\
);
\rgb_buffer_reg[706][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][23]_srl32_n_1\
);
\rgb_buffer_reg[706][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][2]_srl32_n_1\
);
\rgb_buffer_reg[706][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][3]_srl32_n_1\
);
\rgb_buffer_reg[706][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][4]_srl32_n_1\
);
\rgb_buffer_reg[706][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][5]_srl32_n_1\
);
\rgb_buffer_reg[706][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][6]_srl32_n_1\
);
\rgb_buffer_reg[706][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][7]_srl32_n_1\
);
\rgb_buffer_reg[706][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][8]_srl32_n_1\
);
\rgb_buffer_reg[706][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[674][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[706][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[706][9]_srl32_n_1\
);
\rgb_buffer_reg[738][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][0]_srl32_n_1\
);
\rgb_buffer_reg[738][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][10]_srl32_n_1\
);
\rgb_buffer_reg[738][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][11]_srl32_n_1\
);
\rgb_buffer_reg[738][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][12]_srl32_n_1\
);
\rgb_buffer_reg[738][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][13]_srl32_n_1\
);
\rgb_buffer_reg[738][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][14]_srl32_n_1\
);
\rgb_buffer_reg[738][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][15]_srl32_n_1\
);
\rgb_buffer_reg[738][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][16]_srl32_n_1\
);
\rgb_buffer_reg[738][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][17]_srl32_n_1\
);
\rgb_buffer_reg[738][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][18]_srl32_n_1\
);
\rgb_buffer_reg[738][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][19]_srl32_n_1\
);
\rgb_buffer_reg[738][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][1]_srl32_n_1\
);
\rgb_buffer_reg[738][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][20]_srl32_n_1\
);
\rgb_buffer_reg[738][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][21]_srl32_n_1\
);
\rgb_buffer_reg[738][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][22]_srl32_n_1\
);
\rgb_buffer_reg[738][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][23]_srl32_n_1\
);
\rgb_buffer_reg[738][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][2]_srl32_n_1\
);
\rgb_buffer_reg[738][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][3]_srl32_n_1\
);
\rgb_buffer_reg[738][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][4]_srl32_n_1\
);
\rgb_buffer_reg[738][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][5]_srl32_n_1\
);
\rgb_buffer_reg[738][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][6]_srl32_n_1\
);
\rgb_buffer_reg[738][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][7]_srl32_n_1\
);
\rgb_buffer_reg[738][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][8]_srl32_n_1\
);
\rgb_buffer_reg[738][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[706][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[738][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[738][9]_srl32_n_1\
);
\rgb_buffer_reg[770][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][0]_srl32_n_1\,
Q => \rgb_buffer_reg[770][0]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][0]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][10]_srl32_n_1\,
Q => \rgb_buffer_reg[770][10]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][10]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][11]_srl32_n_1\,
Q => \rgb_buffer_reg[770][11]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][11]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][12]_srl32_n_1\,
Q => \rgb_buffer_reg[770][12]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][12]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][13]_srl32_n_1\,
Q => \rgb_buffer_reg[770][13]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][13]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][14]_srl32_n_1\,
Q => \rgb_buffer_reg[770][14]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][14]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][15]_srl32_n_1\,
Q => \rgb_buffer_reg[770][15]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][15]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][16]_srl32_n_1\,
Q => \rgb_buffer_reg[770][16]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][16]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][17]_srl32_n_1\,
Q => \rgb_buffer_reg[770][17]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][17]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][18]_srl32_n_1\,
Q => \rgb_buffer_reg[770][18]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][18]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][19]_srl32_n_1\,
Q => \rgb_buffer_reg[770][19]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][19]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][1]_srl32_n_1\,
Q => \rgb_buffer_reg[770][1]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][1]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][20]_srl32_n_1\,
Q => \rgb_buffer_reg[770][20]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][20]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][21]_srl32_n_1\,
Q => \rgb_buffer_reg[770][21]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][21]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][22]_srl32_n_1\,
Q => \rgb_buffer_reg[770][22]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][22]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][23]_srl32_n_1\,
Q => \rgb_buffer_reg[770][23]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][23]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][2]_srl32_n_1\,
Q => \rgb_buffer_reg[770][2]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][2]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][3]_srl32_n_1\,
Q => \rgb_buffer_reg[770][3]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][3]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][4]_srl32_n_1\,
Q => \rgb_buffer_reg[770][4]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][4]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][5]_srl32_n_1\,
Q => \rgb_buffer_reg[770][5]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][5]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][6]_srl32_n_1\,
Q => \rgb_buffer_reg[770][6]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][6]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][7]_srl32_n_1\,
Q => \rgb_buffer_reg[770][7]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][7]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][8]_srl32_n_1\,
Q => \rgb_buffer_reg[770][8]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][8]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[770][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[738][9]_srl32_n_1\,
Q => \rgb_buffer_reg[770][9]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[770][9]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[802][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][0]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][0]_srl32_n_1\
);
\rgb_buffer_reg[802][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][10]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][10]_srl32_n_1\
);
\rgb_buffer_reg[802][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][11]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][11]_srl32_n_1\
);
\rgb_buffer_reg[802][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][12]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][12]_srl32_n_1\
);
\rgb_buffer_reg[802][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][13]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][13]_srl32_n_1\
);
\rgb_buffer_reg[802][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][14]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][14]_srl32_n_1\
);
\rgb_buffer_reg[802][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][15]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][15]_srl32_n_1\
);
\rgb_buffer_reg[802][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][16]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][16]_srl32_n_1\
);
\rgb_buffer_reg[802][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][17]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][17]_srl32_n_1\
);
\rgb_buffer_reg[802][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][18]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][18]_srl32_n_1\
);
\rgb_buffer_reg[802][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][19]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][19]_srl32_n_1\
);
\rgb_buffer_reg[802][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][1]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][1]_srl32_n_1\
);
\rgb_buffer_reg[802][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][20]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][20]_srl32_n_1\
);
\rgb_buffer_reg[802][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][21]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][21]_srl32_n_1\
);
\rgb_buffer_reg[802][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][22]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][22]_srl32_n_1\
);
\rgb_buffer_reg[802][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][23]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][23]_srl32_n_1\
);
\rgb_buffer_reg[802][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][2]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][2]_srl32_n_1\
);
\rgb_buffer_reg[802][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][3]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][3]_srl32_n_1\
);
\rgb_buffer_reg[802][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][4]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][4]_srl32_n_1\
);
\rgb_buffer_reg[802][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][5]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][5]_srl32_n_1\
);
\rgb_buffer_reg[802][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][6]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][6]_srl32_n_1\
);
\rgb_buffer_reg[802][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][7]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][7]_srl32_n_1\
);
\rgb_buffer_reg[802][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][8]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][8]_srl32_n_1\
);
\rgb_buffer_reg[802][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[770][9]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[802][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[802][9]_srl32_n_1\
);
\rgb_buffer_reg[834][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][0]_srl32_n_1\
);
\rgb_buffer_reg[834][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][10]_srl32_n_1\
);
\rgb_buffer_reg[834][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][11]_srl32_n_1\
);
\rgb_buffer_reg[834][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][12]_srl32_n_1\
);
\rgb_buffer_reg[834][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][13]_srl32_n_1\
);
\rgb_buffer_reg[834][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][14]_srl32_n_1\
);
\rgb_buffer_reg[834][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][15]_srl32_n_1\
);
\rgb_buffer_reg[834][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][16]_srl32_n_1\
);
\rgb_buffer_reg[834][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][17]_srl32_n_1\
);
\rgb_buffer_reg[834][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][18]_srl32_n_1\
);
\rgb_buffer_reg[834][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][19]_srl32_n_1\
);
\rgb_buffer_reg[834][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][1]_srl32_n_1\
);
\rgb_buffer_reg[834][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][20]_srl32_n_1\
);
\rgb_buffer_reg[834][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][21]_srl32_n_1\
);
\rgb_buffer_reg[834][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][22]_srl32_n_1\
);
\rgb_buffer_reg[834][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][23]_srl32_n_1\
);
\rgb_buffer_reg[834][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][2]_srl32_n_1\
);
\rgb_buffer_reg[834][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][3]_srl32_n_1\
);
\rgb_buffer_reg[834][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][4]_srl32_n_1\
);
\rgb_buffer_reg[834][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][5]_srl32_n_1\
);
\rgb_buffer_reg[834][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][6]_srl32_n_1\
);
\rgb_buffer_reg[834][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][7]_srl32_n_1\
);
\rgb_buffer_reg[834][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][8]_srl32_n_1\
);
\rgb_buffer_reg[834][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[802][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[834][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[834][9]_srl32_n_1\
);
\rgb_buffer_reg[866][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][0]_srl32_n_1\
);
\rgb_buffer_reg[866][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][10]_srl32_n_1\
);
\rgb_buffer_reg[866][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][11]_srl32_n_1\
);
\rgb_buffer_reg[866][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][12]_srl32_n_1\
);
\rgb_buffer_reg[866][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][13]_srl32_n_1\
);
\rgb_buffer_reg[866][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][14]_srl32_n_1\
);
\rgb_buffer_reg[866][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][15]_srl32_n_1\
);
\rgb_buffer_reg[866][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][16]_srl32_n_1\
);
\rgb_buffer_reg[866][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][17]_srl32_n_1\
);
\rgb_buffer_reg[866][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][18]_srl32_n_1\
);
\rgb_buffer_reg[866][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][19]_srl32_n_1\
);
\rgb_buffer_reg[866][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][1]_srl32_n_1\
);
\rgb_buffer_reg[866][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][20]_srl32_n_1\
);
\rgb_buffer_reg[866][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][21]_srl32_n_1\
);
\rgb_buffer_reg[866][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][22]_srl32_n_1\
);
\rgb_buffer_reg[866][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][23]_srl32_n_1\
);
\rgb_buffer_reg[866][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][2]_srl32_n_1\
);
\rgb_buffer_reg[866][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][3]_srl32_n_1\
);
\rgb_buffer_reg[866][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][4]_srl32_n_1\
);
\rgb_buffer_reg[866][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][5]_srl32_n_1\
);
\rgb_buffer_reg[866][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][6]_srl32_n_1\
);
\rgb_buffer_reg[866][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][7]_srl32_n_1\
);
\rgb_buffer_reg[866][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][8]_srl32_n_1\
);
\rgb_buffer_reg[866][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[834][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[866][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[866][9]_srl32_n_1\
);
\rgb_buffer_reg[898][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][0]_srl32_n_1\,
Q => \rgb_buffer_reg[898][0]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][0]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][10]_srl32_n_1\,
Q => \rgb_buffer_reg[898][10]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][10]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][11]_srl32_n_1\,
Q => \rgb_buffer_reg[898][11]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][11]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][12]_srl32_n_1\,
Q => \rgb_buffer_reg[898][12]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][12]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][13]_srl32_n_1\,
Q => \rgb_buffer_reg[898][13]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][13]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][14]_srl32_n_1\,
Q => \rgb_buffer_reg[898][14]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][14]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][15]_srl32_n_1\,
Q => \rgb_buffer_reg[898][15]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][15]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][16]_srl32_n_1\,
Q => \rgb_buffer_reg[898][16]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][16]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][17]_srl32_n_1\,
Q => \rgb_buffer_reg[898][17]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][17]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][18]_srl32_n_1\,
Q => \rgb_buffer_reg[898][18]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][18]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][19]_srl32_n_1\,
Q => \rgb_buffer_reg[898][19]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][19]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][1]_srl32_n_1\,
Q => \rgb_buffer_reg[898][1]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][1]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][20]_srl32_n_1\,
Q => \rgb_buffer_reg[898][20]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][20]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][21]_srl32_n_1\,
Q => \rgb_buffer_reg[898][21]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][21]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][22]_srl32_n_1\,
Q => \rgb_buffer_reg[898][22]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][22]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][23]_srl32_n_1\,
Q => \rgb_buffer_reg[898][23]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][23]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][2]_srl32_n_1\,
Q => \rgb_buffer_reg[898][2]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][2]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][3]_srl32_n_1\,
Q => \rgb_buffer_reg[898][3]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][3]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][4]_srl32_n_1\,
Q => \rgb_buffer_reg[898][4]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][4]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][5]_srl32_n_1\,
Q => \rgb_buffer_reg[898][5]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][5]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][6]_srl32_n_1\,
Q => \rgb_buffer_reg[898][6]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][6]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][7]_srl32_n_1\,
Q => \rgb_buffer_reg[898][7]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][7]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][8]_srl32_n_1\,
Q => \rgb_buffer_reg[898][8]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][8]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[898][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[866][9]_srl32_n_1\,
Q => \rgb_buffer_reg[898][9]_srl32_n_0\,
Q31 => \NLW_rgb_buffer_reg[898][9]_srl32_Q31_UNCONNECTED\
);
\rgb_buffer_reg[930][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][0]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][0]_srl32_n_1\
);
\rgb_buffer_reg[930][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][10]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][10]_srl32_n_1\
);
\rgb_buffer_reg[930][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][11]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][11]_srl32_n_1\
);
\rgb_buffer_reg[930][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][12]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][12]_srl32_n_1\
);
\rgb_buffer_reg[930][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][13]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][13]_srl32_n_1\
);
\rgb_buffer_reg[930][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][14]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][14]_srl32_n_1\
);
\rgb_buffer_reg[930][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][15]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][15]_srl32_n_1\
);
\rgb_buffer_reg[930][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][16]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][16]_srl32_n_1\
);
\rgb_buffer_reg[930][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][17]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][17]_srl32_n_1\
);
\rgb_buffer_reg[930][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][18]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][18]_srl32_n_1\
);
\rgb_buffer_reg[930][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][19]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][19]_srl32_n_1\
);
\rgb_buffer_reg[930][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][1]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][1]_srl32_n_1\
);
\rgb_buffer_reg[930][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][20]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][20]_srl32_n_1\
);
\rgb_buffer_reg[930][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][21]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][21]_srl32_n_1\
);
\rgb_buffer_reg[930][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][22]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][22]_srl32_n_1\
);
\rgb_buffer_reg[930][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][23]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][23]_srl32_n_1\
);
\rgb_buffer_reg[930][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][2]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][2]_srl32_n_1\
);
\rgb_buffer_reg[930][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][3]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][3]_srl32_n_1\
);
\rgb_buffer_reg[930][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][4]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][4]_srl32_n_1\
);
\rgb_buffer_reg[930][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][5]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][5]_srl32_n_1\
);
\rgb_buffer_reg[930][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][6]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][6]_srl32_n_1\
);
\rgb_buffer_reg[930][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][7]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][7]_srl32_n_1\
);
\rgb_buffer_reg[930][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][8]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][8]_srl32_n_1\
);
\rgb_buffer_reg[930][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[898][9]_srl32_n_0\,
Q => \NLW_rgb_buffer_reg[930][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[930][9]_srl32_n_1\
);
\rgb_buffer_reg[962][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][0]_srl32_n_1\
);
\rgb_buffer_reg[962][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][10]_srl32_n_1\
);
\rgb_buffer_reg[962][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][11]_srl32_n_1\
);
\rgb_buffer_reg[962][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][12]_srl32_n_1\
);
\rgb_buffer_reg[962][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][13]_srl32_n_1\
);
\rgb_buffer_reg[962][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][14]_srl32_n_1\
);
\rgb_buffer_reg[962][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][15]_srl32_n_1\
);
\rgb_buffer_reg[962][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][16]_srl32_n_1\
);
\rgb_buffer_reg[962][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][17]_srl32_n_1\
);
\rgb_buffer_reg[962][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][18]_srl32_n_1\
);
\rgb_buffer_reg[962][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][19]_srl32_n_1\
);
\rgb_buffer_reg[962][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][1]_srl32_n_1\
);
\rgb_buffer_reg[962][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][20]_srl32_n_1\
);
\rgb_buffer_reg[962][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][21]_srl32_n_1\
);
\rgb_buffer_reg[962][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][22]_srl32_n_1\
);
\rgb_buffer_reg[962][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][23]_srl32_n_1\
);
\rgb_buffer_reg[962][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][2]_srl32_n_1\
);
\rgb_buffer_reg[962][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][3]_srl32_n_1\
);
\rgb_buffer_reg[962][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][4]_srl32_n_1\
);
\rgb_buffer_reg[962][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][5]_srl32_n_1\
);
\rgb_buffer_reg[962][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][6]_srl32_n_1\
);
\rgb_buffer_reg[962][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][7]_srl32_n_1\
);
\rgb_buffer_reg[962][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][8]_srl32_n_1\
);
\rgb_buffer_reg[962][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[930][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[962][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[962][9]_srl32_n_1\
);
\rgb_buffer_reg[98][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][0]_srl32_n_1\
);
\rgb_buffer_reg[98][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][10]_srl32_n_1\
);
\rgb_buffer_reg[98][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][11]_srl32_n_1\
);
\rgb_buffer_reg[98][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][12]_srl32_n_1\
);
\rgb_buffer_reg[98][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][13]_srl32_n_1\
);
\rgb_buffer_reg[98][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][14]_srl32_n_1\
);
\rgb_buffer_reg[98][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][15]_srl32_n_1\
);
\rgb_buffer_reg[98][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][16]_srl32_n_1\
);
\rgb_buffer_reg[98][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][17]_srl32_n_1\
);
\rgb_buffer_reg[98][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][18]_srl32_n_1\
);
\rgb_buffer_reg[98][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][19]_srl32_n_1\
);
\rgb_buffer_reg[98][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][1]_srl32_n_1\
);
\rgb_buffer_reg[98][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][20]_srl32_n_1\
);
\rgb_buffer_reg[98][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][21]_srl32_n_1\
);
\rgb_buffer_reg[98][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][22]_srl32_n_1\
);
\rgb_buffer_reg[98][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][23]_srl32_n_1\
);
\rgb_buffer_reg[98][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][2]_srl32_n_1\
);
\rgb_buffer_reg[98][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][3]_srl32_n_1\
);
\rgb_buffer_reg[98][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][4]_srl32_n_1\
);
\rgb_buffer_reg[98][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][5]_srl32_n_1\
);
\rgb_buffer_reg[98][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][6]_srl32_n_1\
);
\rgb_buffer_reg[98][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][7]_srl32_n_1\
);
\rgb_buffer_reg[98][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][8]_srl32_n_1\
);
\rgb_buffer_reg[98][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[66][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[98][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[98][9]_srl32_n_1\
);
\rgb_buffer_reg[994][0]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][0]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][0]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][0]_srl32_n_1\
);
\rgb_buffer_reg[994][10]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][10]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][10]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][10]_srl32_n_1\
);
\rgb_buffer_reg[994][11]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][11]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][11]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][11]_srl32_n_1\
);
\rgb_buffer_reg[994][12]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][12]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][12]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][12]_srl32_n_1\
);
\rgb_buffer_reg[994][13]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][13]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][13]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][13]_srl32_n_1\
);
\rgb_buffer_reg[994][14]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][14]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][14]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][14]_srl32_n_1\
);
\rgb_buffer_reg[994][15]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][15]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][15]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][15]_srl32_n_1\
);
\rgb_buffer_reg[994][16]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][16]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][16]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][16]_srl32_n_1\
);
\rgb_buffer_reg[994][17]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][17]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][17]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][17]_srl32_n_1\
);
\rgb_buffer_reg[994][18]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][18]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][18]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][18]_srl32_n_1\
);
\rgb_buffer_reg[994][19]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][19]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][19]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][19]_srl32_n_1\
);
\rgb_buffer_reg[994][1]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][1]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][1]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][1]_srl32_n_1\
);
\rgb_buffer_reg[994][20]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][20]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][20]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][20]_srl32_n_1\
);
\rgb_buffer_reg[994][21]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][21]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][21]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][21]_srl32_n_1\
);
\rgb_buffer_reg[994][22]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][22]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][22]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][22]_srl32_n_1\
);
\rgb_buffer_reg[994][23]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][23]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][23]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][23]_srl32_n_1\
);
\rgb_buffer_reg[994][2]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][2]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][2]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][2]_srl32_n_1\
);
\rgb_buffer_reg[994][3]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][3]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][3]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][3]_srl32_n_1\
);
\rgb_buffer_reg[994][4]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][4]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][4]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][4]_srl32_n_1\
);
\rgb_buffer_reg[994][5]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][5]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][5]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][5]_srl32_n_1\
);
\rgb_buffer_reg[994][6]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][6]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][6]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][6]_srl32_n_1\
);
\rgb_buffer_reg[994][7]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][7]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][7]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][7]_srl32_n_1\
);
\rgb_buffer_reg[994][8]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][8]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][8]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][8]_srl32_n_1\
);
\rgb_buffer_reg[994][9]_srl32\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11111",
CE => \^active\,
CLK => clk_25,
D => \rgb_buffer_reg[962][9]_srl32_n_1\,
Q => \NLW_rgb_buffer_reg[994][9]_srl32_Q_UNCONNECTED\,
Q31 => \rgb_buffer_reg[994][9]_srl32_n_1\
);
\rgb_pass_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(0),
Q => rgb_pass(0),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(10),
Q => rgb_pass(10),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(11),
Q => rgb_pass(11),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(12),
Q => rgb_pass(12),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(13),
Q => rgb_pass(13),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(14),
Q => rgb_pass(14),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(15),
Q => rgb_pass(15),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(16),
Q => rgb_pass(16),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(17),
Q => rgb_pass(17),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(18),
Q => rgb_pass(18),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(19),
Q => rgb_pass(19),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(1),
Q => rgb_pass(1),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(20),
Q => rgb_pass(20),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(21),
Q => rgb_pass(21),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(22),
Q => rgb_pass(22),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(23),
Q => rgb_pass(23),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(2),
Q => rgb_pass(2),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(3),
Q => rgb_pass(3),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(4),
Q => rgb_pass(4),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(5),
Q => rgb_pass(5),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(6),
Q => rgb_pass(6),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(7),
Q => rgb_pass(7),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(8),
Q => rgb_pass(8),
R => \rgb_blur[23]_i_1_n_0\
);
\rgb_pass_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => D(9),
Q => rgb_pass(9),
R => \rgb_blur[23]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_gaussian_blur_0_0 is
port (
clk_25 : in STD_LOGIC;
hsync_in : in STD_LOGIC;
vsync_in : in STD_LOGIC;
rgb_in : in STD_LOGIC_VECTOR ( 23 downto 0 );
hsync_out : out STD_LOGIC;
vsync_out : out STD_LOGIC;
rgb_blur : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_pass : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_gaussian_blur_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_gaussian_blur_0_0 : entity is "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_gaussian_blur_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_gaussian_blur_0_0 : entity is "vga_gaussian_blur,Vivado 2016.4";
end system_vga_gaussian_blur_0_0;
architecture STRUCTURE of system_vga_gaussian_blur_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \A[0]__14_n_0\ : STD_LOGIC;
signal \A[0]__15_srl29_n_0\ : STD_LOGIC;
signal \A[0]__16_n_0\ : STD_LOGIC;
signal \A[0]__18_n_0\ : STD_LOGIC;
signal \A[0]__24_n_0\ : STD_LOGIC;
signal \A[0]__25_srl29_n_0\ : STD_LOGIC;
signal \A[0]__26_n_0\ : STD_LOGIC;
signal \A[0]__28_n_0\ : STD_LOGIC;
signal \A[0]__4_n_0\ : STD_LOGIC;
signal \A[0]__5_srl29_n_0\ : STD_LOGIC;
signal \A[0]__6_n_0\ : STD_LOGIC;
signal \A[0]__8_n_0\ : STD_LOGIC;
signal \A[1]__14_n_0\ : STD_LOGIC;
signal \A[1]__15_srl29_n_0\ : STD_LOGIC;
signal \A[1]__16_n_0\ : STD_LOGIC;
signal \A[1]__18_n_0\ : STD_LOGIC;
signal \A[1]__24_n_0\ : STD_LOGIC;
signal \A[1]__25_srl29_n_0\ : STD_LOGIC;
signal \A[1]__26_n_0\ : STD_LOGIC;
signal \A[1]__28_n_0\ : STD_LOGIC;
signal \A[1]__4_n_0\ : STD_LOGIC;
signal \A[1]__5_srl29_n_0\ : STD_LOGIC;
signal \A[1]__6_n_0\ : STD_LOGIC;
signal \A[1]__8_n_0\ : STD_LOGIC;
signal \A[2]__14_n_0\ : STD_LOGIC;
signal \A[2]__15_srl29_n_0\ : STD_LOGIC;
signal \A[2]__16_n_0\ : STD_LOGIC;
signal \A[2]__18_n_0\ : STD_LOGIC;
signal \A[2]__24_n_0\ : STD_LOGIC;
signal \A[2]__25_srl29_n_0\ : STD_LOGIC;
signal \A[2]__26_n_0\ : STD_LOGIC;
signal \A[2]__28_n_0\ : STD_LOGIC;
signal \A[2]__4_n_0\ : STD_LOGIC;
signal \A[2]__5_srl29_n_0\ : STD_LOGIC;
signal \A[2]__6_n_0\ : STD_LOGIC;
signal \A[2]__8_n_0\ : STD_LOGIC;
signal \A[3]__14_n_0\ : STD_LOGIC;
signal \A[3]__15_srl29_n_0\ : STD_LOGIC;
signal \A[3]__16_n_0\ : STD_LOGIC;
signal \A[3]__18_n_0\ : STD_LOGIC;
signal \A[3]__24_n_0\ : STD_LOGIC;
signal \A[3]__25_srl29_n_0\ : STD_LOGIC;
signal \A[3]__26_n_0\ : STD_LOGIC;
signal \A[3]__28_n_0\ : STD_LOGIC;
signal \A[3]__4_n_0\ : STD_LOGIC;
signal \A[3]__5_srl29_n_0\ : STD_LOGIC;
signal \A[3]__6_n_0\ : STD_LOGIC;
signal \A[3]__8_n_0\ : STD_LOGIC;
signal \A[4]__14_n_0\ : STD_LOGIC;
signal \A[4]__15_srl29_n_0\ : STD_LOGIC;
signal \A[4]__16_n_0\ : STD_LOGIC;
signal \A[4]__18_n_0\ : STD_LOGIC;
signal \A[4]__24_n_0\ : STD_LOGIC;
signal \A[4]__25_srl29_n_0\ : STD_LOGIC;
signal \A[4]__26_n_0\ : STD_LOGIC;
signal \A[4]__28_n_0\ : STD_LOGIC;
signal \A[4]__4_n_0\ : STD_LOGIC;
signal \A[4]__5_srl29_n_0\ : STD_LOGIC;
signal \A[4]__6_n_0\ : STD_LOGIC;
signal \A[4]__8_n_0\ : STD_LOGIC;
signal \A[5]__14_n_0\ : STD_LOGIC;
signal \A[5]__15_srl29_n_0\ : STD_LOGIC;
signal \A[5]__16_n_0\ : STD_LOGIC;
signal \A[5]__18_n_0\ : STD_LOGIC;
signal \A[5]__24_n_0\ : STD_LOGIC;
signal \A[5]__25_srl29_n_0\ : STD_LOGIC;
signal \A[5]__26_n_0\ : STD_LOGIC;
signal \A[5]__28_n_0\ : STD_LOGIC;
signal \A[5]__4_n_0\ : STD_LOGIC;
signal \A[5]__5_srl29_n_0\ : STD_LOGIC;
signal \A[5]__6_n_0\ : STD_LOGIC;
signal \A[5]__8_n_0\ : STD_LOGIC;
signal \A[6]__14_n_0\ : STD_LOGIC;
signal \A[6]__15_srl29_n_0\ : STD_LOGIC;
signal \A[6]__16_n_0\ : STD_LOGIC;
signal \A[6]__18_n_0\ : STD_LOGIC;
signal \A[6]__24_n_0\ : STD_LOGIC;
signal \A[6]__25_srl29_n_0\ : STD_LOGIC;
signal \A[6]__26_n_0\ : STD_LOGIC;
signal \A[6]__28_n_0\ : STD_LOGIC;
signal \A[6]__4_n_0\ : STD_LOGIC;
signal \A[6]__5_srl29_n_0\ : STD_LOGIC;
signal \A[6]__6_n_0\ : STD_LOGIC;
signal \A[6]__8_n_0\ : STD_LOGIC;
signal \A[7]__14_n_0\ : STD_LOGIC;
signal \A[7]__15_srl29_n_0\ : STD_LOGIC;
signal \A[7]__16_n_0\ : STD_LOGIC;
signal \A[7]__18_n_0\ : STD_LOGIC;
signal \A[7]__24_n_0\ : STD_LOGIC;
signal \A[7]__25_srl29_n_0\ : STD_LOGIC;
signal \A[7]__26_n_0\ : STD_LOGIC;
signal \A[7]__28_n_0\ : STD_LOGIC;
signal \A[7]__4_n_0\ : STD_LOGIC;
signal \A[7]__5_srl29_n_0\ : STD_LOGIC;
signal \A[7]__6_n_0\ : STD_LOGIC;
signal \A[7]__8_n_0\ : STD_LOGIC;
signal B : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \B[0]__1_n_0\ : STD_LOGIC;
signal \B[0]__3_n_0\ : STD_LOGIC;
signal \B[0]__4_n_0\ : STD_LOGIC;
signal \B[0]__5_n_0\ : STD_LOGIC;
signal \B[0]__7_n_0\ : STD_LOGIC;
signal \B[0]__8_n_0\ : STD_LOGIC;
signal \B[0]__9_n_0\ : STD_LOGIC;
signal \B[1]__0_n_0\ : STD_LOGIC;
signal \B[1]__10_n_0\ : STD_LOGIC;
signal \B[1]__2_n_0\ : STD_LOGIC;
signal \B[1]__4_n_0\ : STD_LOGIC;
signal \B[1]__5_n_0\ : STD_LOGIC;
signal \B[1]__6_n_0\ : STD_LOGIC;
signal \B[1]__8_n_0\ : STD_LOGIC;
signal \B[1]__9_n_0\ : STD_LOGIC;
signal \B[2]__0_n_0\ : STD_LOGIC;
signal \B[2]__10_n_0\ : STD_LOGIC;
signal \B[2]__2_n_0\ : STD_LOGIC;
signal \B[2]__4_n_0\ : STD_LOGIC;
signal \B[2]__5_n_0\ : STD_LOGIC;
signal \B[2]__6_n_0\ : STD_LOGIC;
signal \B[2]__8_n_0\ : STD_LOGIC;
signal \B[2]__9_n_0\ : STD_LOGIC;
signal \B[3]__0_n_0\ : STD_LOGIC;
signal \B[3]__10_n_0\ : STD_LOGIC;
signal \B[3]__2_n_0\ : STD_LOGIC;
signal \B[3]__4_n_0\ : STD_LOGIC;
signal \B[3]__5_n_0\ : STD_LOGIC;
signal \B[3]__6_n_0\ : STD_LOGIC;
signal \B[3]__8_n_0\ : STD_LOGIC;
signal \B[3]__9_n_0\ : STD_LOGIC;
signal \B[4]__0_n_0\ : STD_LOGIC;
signal \B[4]__10_n_0\ : STD_LOGIC;
signal \B[4]__2_n_0\ : STD_LOGIC;
signal \B[4]__4_n_0\ : STD_LOGIC;
signal \B[4]__5_n_0\ : STD_LOGIC;
signal \B[4]__6_n_0\ : STD_LOGIC;
signal \B[4]__8_n_0\ : STD_LOGIC;
signal \B[4]__9_n_0\ : STD_LOGIC;
signal \B[5]__0_n_0\ : STD_LOGIC;
signal \B[5]__10_n_0\ : STD_LOGIC;
signal \B[5]__2_n_0\ : STD_LOGIC;
signal \B[5]__4_n_0\ : STD_LOGIC;
signal \B[5]__5_n_0\ : STD_LOGIC;
signal \B[5]__6_n_0\ : STD_LOGIC;
signal \B[5]__8_n_0\ : STD_LOGIC;
signal \B[5]__9_n_0\ : STD_LOGIC;
signal \B[6]__0_n_0\ : STD_LOGIC;
signal \B[6]__10_n_0\ : STD_LOGIC;
signal \B[6]__2_n_0\ : STD_LOGIC;
signal \B[6]__4_n_0\ : STD_LOGIC;
signal \B[6]__5_n_0\ : STD_LOGIC;
signal \B[6]__6_n_0\ : STD_LOGIC;
signal \B[6]__8_n_0\ : STD_LOGIC;
signal \B[6]__9_n_0\ : STD_LOGIC;
signal \B[7]__0_n_0\ : STD_LOGIC;
signal \B[7]__10_n_0\ : STD_LOGIC;
signal \B[7]__2_n_0\ : STD_LOGIC;
signal \B[7]__4_n_0\ : STD_LOGIC;
signal \B[7]__5_n_0\ : STD_LOGIC;
signal \B[7]__6_n_0\ : STD_LOGIC;
signal \B[7]__8_n_0\ : STD_LOGIC;
signal \B[7]__9_n_0\ : STD_LOGIC;
signal \B_n_0_[0]\ : STD_LOGIC;
signal C : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \C[0]__0_n_0\ : STD_LOGIC;
signal \C[0]__1_n_0\ : STD_LOGIC;
signal \C[0]__2_n_0\ : STD_LOGIC;
signal \C[0]__3_n_0\ : STD_LOGIC;
signal \C[0]__4_n_0\ : STD_LOGIC;
signal \C[1]__0_n_0\ : STD_LOGIC;
signal \C[1]__1_n_0\ : STD_LOGIC;
signal \C[1]__2_n_0\ : STD_LOGIC;
signal \C[1]__3_n_0\ : STD_LOGIC;
signal \C[1]__4_n_0\ : STD_LOGIC;
signal \C[2]__0_n_0\ : STD_LOGIC;
signal \C[2]__1_n_0\ : STD_LOGIC;
signal \C[2]__2_n_0\ : STD_LOGIC;
signal \C[2]__3_n_0\ : STD_LOGIC;
signal \C[2]__4_n_0\ : STD_LOGIC;
signal \C[3]__0_n_0\ : STD_LOGIC;
signal \C[3]__1_n_0\ : STD_LOGIC;
signal \C[3]__2_n_0\ : STD_LOGIC;
signal \C[3]__3_n_0\ : STD_LOGIC;
signal \C[3]__4_n_0\ : STD_LOGIC;
signal \C[4]__0_n_0\ : STD_LOGIC;
signal \C[4]__1_n_0\ : STD_LOGIC;
signal \C[4]__2_n_0\ : STD_LOGIC;
signal \C[4]__3_n_0\ : STD_LOGIC;
signal \C[4]__4_n_0\ : STD_LOGIC;
signal \C[5]__0_n_0\ : STD_LOGIC;
signal \C[5]__1_n_0\ : STD_LOGIC;
signal \C[5]__2_n_0\ : STD_LOGIC;
signal \C[5]__3_n_0\ : STD_LOGIC;
signal \C[5]__4_n_0\ : STD_LOGIC;
signal \C[6]__0_n_0\ : STD_LOGIC;
signal \C[6]__1_n_0\ : STD_LOGIC;
signal \C[6]__2_n_0\ : STD_LOGIC;
signal \C[6]__3_n_0\ : STD_LOGIC;
signal \C[6]__4_n_0\ : STD_LOGIC;
signal \C[7]__0_n_0\ : STD_LOGIC;
signal \C[7]__1_n_0\ : STD_LOGIC;
signal \C[7]__2_n_0\ : STD_LOGIC;
signal \C[7]__3_n_0\ : STD_LOGIC;
signal \C[7]__4_n_0\ : STD_LOGIC;
signal U0_n_1 : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal U0_n_11 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal U0_n_19 : STD_LOGIC;
signal U0_n_2 : STD_LOGIC;
signal U0_n_20 : STD_LOGIC;
signal U0_n_21 : STD_LOGIC;
signal U0_n_22 : STD_LOGIC;
signal U0_n_23 : STD_LOGIC;
signal U0_n_24 : STD_LOGIC;
signal U0_n_25 : STD_LOGIC;
signal U0_n_26 : STD_LOGIC;
signal U0_n_27 : STD_LOGIC;
signal U0_n_28 : STD_LOGIC;
signal U0_n_29 : STD_LOGIC;
signal U0_n_3 : STD_LOGIC;
signal U0_n_30 : STD_LOGIC;
signal U0_n_31 : STD_LOGIC;
signal U0_n_32 : STD_LOGIC;
signal U0_n_33 : STD_LOGIC;
signal U0_n_34 : STD_LOGIC;
signal U0_n_35 : STD_LOGIC;
signal U0_n_36 : STD_LOGIC;
signal U0_n_37 : STD_LOGIC;
signal U0_n_38 : STD_LOGIC;
signal U0_n_39 : STD_LOGIC;
signal U0_n_4 : STD_LOGIC;
signal U0_n_40 : STD_LOGIC;
signal U0_n_41 : STD_LOGIC;
signal U0_n_42 : STD_LOGIC;
signal U0_n_43 : STD_LOGIC;
signal U0_n_44 : STD_LOGIC;
signal U0_n_45 : STD_LOGIC;
signal U0_n_46 : STD_LOGIC;
signal U0_n_47 : STD_LOGIC;
signal U0_n_48 : STD_LOGIC;
signal U0_n_5 : STD_LOGIC;
signal U0_n_6 : STD_LOGIC;
signal U0_n_7 : STD_LOGIC;
signal U0_n_8 : STD_LOGIC;
signal U0_n_9 : STD_LOGIC;
signal active : STD_LOGIC;
signal \NLW_A[0]__15_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[0]__25_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[0]__5_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[1]__15_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[1]__25_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[1]__5_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[2]__15_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[2]__25_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[2]__5_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[3]__15_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[3]__25_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[3]__5_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[4]__15_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[4]__25_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[4]__5_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[5]__15_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[5]__25_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[5]__5_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[6]__15_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[6]__25_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[6]__5_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[7]__15_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[7]__25_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_A[7]__5_srl29_Q31_UNCONNECTED\ : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \A[0]__15_srl29\ : label is "\A ";
attribute srl_name : string;
attribute srl_name of \A[0]__15_srl29\ : label is "\A[0]__15_srl29 ";
attribute srl_bus_name of \A[0]__25_srl29\ : label is "\A ";
attribute srl_name of \A[0]__25_srl29\ : label is "\A[0]__25_srl29 ";
attribute srl_bus_name of \A[0]__5_srl29\ : label is "\A ";
attribute srl_name of \A[0]__5_srl29\ : label is "\A[0]__5_srl29 ";
attribute srl_bus_name of \A[1]__15_srl29\ : label is "\A ";
attribute srl_name of \A[1]__15_srl29\ : label is "\A[1]__15_srl29 ";
attribute srl_bus_name of \A[1]__25_srl29\ : label is "\A ";
attribute srl_name of \A[1]__25_srl29\ : label is "\A[1]__25_srl29 ";
attribute srl_bus_name of \A[1]__5_srl29\ : label is "\A ";
attribute srl_name of \A[1]__5_srl29\ : label is "\A[1]__5_srl29 ";
attribute srl_bus_name of \A[2]__15_srl29\ : label is "\A ";
attribute srl_name of \A[2]__15_srl29\ : label is "\A[2]__15_srl29 ";
attribute srl_bus_name of \A[2]__25_srl29\ : label is "\A ";
attribute srl_name of \A[2]__25_srl29\ : label is "\A[2]__25_srl29 ";
attribute srl_bus_name of \A[2]__5_srl29\ : label is "\A ";
attribute srl_name of \A[2]__5_srl29\ : label is "\A[2]__5_srl29 ";
attribute srl_bus_name of \A[3]__15_srl29\ : label is "\A ";
attribute srl_name of \A[3]__15_srl29\ : label is "\A[3]__15_srl29 ";
attribute srl_bus_name of \A[3]__25_srl29\ : label is "\A ";
attribute srl_name of \A[3]__25_srl29\ : label is "\A[3]__25_srl29 ";
attribute srl_bus_name of \A[3]__5_srl29\ : label is "\A ";
attribute srl_name of \A[3]__5_srl29\ : label is "\A[3]__5_srl29 ";
attribute srl_bus_name of \A[4]__15_srl29\ : label is "\A ";
attribute srl_name of \A[4]__15_srl29\ : label is "\A[4]__15_srl29 ";
attribute srl_bus_name of \A[4]__25_srl29\ : label is "\A ";
attribute srl_name of \A[4]__25_srl29\ : label is "\A[4]__25_srl29 ";
attribute srl_bus_name of \A[4]__5_srl29\ : label is "\A ";
attribute srl_name of \A[4]__5_srl29\ : label is "\A[4]__5_srl29 ";
attribute srl_bus_name of \A[5]__15_srl29\ : label is "\A ";
attribute srl_name of \A[5]__15_srl29\ : label is "\A[5]__15_srl29 ";
attribute srl_bus_name of \A[5]__25_srl29\ : label is "\A ";
attribute srl_name of \A[5]__25_srl29\ : label is "\A[5]__25_srl29 ";
attribute srl_bus_name of \A[5]__5_srl29\ : label is "\A ";
attribute srl_name of \A[5]__5_srl29\ : label is "\A[5]__5_srl29 ";
attribute srl_bus_name of \A[6]__15_srl29\ : label is "\A ";
attribute srl_name of \A[6]__15_srl29\ : label is "\A[6]__15_srl29 ";
attribute srl_bus_name of \A[6]__25_srl29\ : label is "\A ";
attribute srl_name of \A[6]__25_srl29\ : label is "\A[6]__25_srl29 ";
attribute srl_bus_name of \A[6]__5_srl29\ : label is "\A ";
attribute srl_name of \A[6]__5_srl29\ : label is "\A[6]__5_srl29 ";
attribute srl_bus_name of \A[7]__15_srl29\ : label is "\A ";
attribute srl_name of \A[7]__15_srl29\ : label is "\A[7]__15_srl29 ";
attribute srl_bus_name of \A[7]__25_srl29\ : label is "\A ";
attribute srl_name of \A[7]__25_srl29\ : label is "\A[7]__25_srl29 ";
attribute srl_bus_name of \A[7]__5_srl29\ : label is "\A ";
attribute srl_name of \A[7]__5_srl29\ : label is "\A[7]__5_srl29 ";
begin
hsync_out <= \<const0>\;
vsync_out <= \<const0>\;
\A[0]__14\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__16_n_0\,
Q => \A[0]__14_n_0\,
R => '0'
);
\A[0]__15_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_33,
Q => \A[0]__15_srl29_n_0\,
Q31 => \NLW_A[0]__15_srl29_Q31_UNCONNECTED\
);
\A[0]__16\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__15_srl29_n_0\,
Q => \A[0]__16_n_0\,
R => '0'
);
\A[0]__18\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[0]__1_n_0\,
Q => \A[0]__18_n_0\,
R => '0'
);
\A[0]__24\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__26_n_0\,
Q => \A[0]__24_n_0\,
R => '0'
);
\A[0]__25_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_41,
Q => \A[0]__25_srl29_n_0\,
Q31 => \NLW_A[0]__25_srl29_Q31_UNCONNECTED\
);
\A[0]__26\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__25_srl29_n_0\,
Q => \A[0]__26_n_0\,
R => '0'
);
\A[0]__28\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[0]__3_n_0\,
Q => \A[0]__28_n_0\,
R => '0'
);
\A[0]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__6_n_0\,
Q => \A[0]__4_n_0\,
R => '0'
);
\A[0]__5_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_25,
Q => \A[0]__5_srl29_n_0\,
Q31 => \NLW_A[0]__5_srl29_Q31_UNCONNECTED\
);
\A[0]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__5_srl29_n_0\,
Q => \A[0]__6_n_0\,
R => '0'
);
\A[0]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => C(0),
Q => \A[0]__8_n_0\,
R => '0'
);
\A[1]__14\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__16_n_0\,
Q => \A[1]__14_n_0\,
R => '0'
);
\A[1]__15_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_34,
Q => \A[1]__15_srl29_n_0\,
Q31 => \NLW_A[1]__15_srl29_Q31_UNCONNECTED\
);
\A[1]__16\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__15_srl29_n_0\,
Q => \A[1]__16_n_0\,
R => '0'
);
\A[1]__18\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[1]__1_n_0\,
Q => \A[1]__18_n_0\,
R => '0'
);
\A[1]__24\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__26_n_0\,
Q => \A[1]__24_n_0\,
R => '0'
);
\A[1]__25_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_42,
Q => \A[1]__25_srl29_n_0\,
Q31 => \NLW_A[1]__25_srl29_Q31_UNCONNECTED\
);
\A[1]__26\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__25_srl29_n_0\,
Q => \A[1]__26_n_0\,
R => '0'
);
\A[1]__28\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[1]__3_n_0\,
Q => \A[1]__28_n_0\,
R => '0'
);
\A[1]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__6_n_0\,
Q => \A[1]__4_n_0\,
R => '0'
);
\A[1]__5_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_26,
Q => \A[1]__5_srl29_n_0\,
Q31 => \NLW_A[1]__5_srl29_Q31_UNCONNECTED\
);
\A[1]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__5_srl29_n_0\,
Q => \A[1]__6_n_0\,
R => '0'
);
\A[1]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => C(1),
Q => \A[1]__8_n_0\,
R => '0'
);
\A[2]__14\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__16_n_0\,
Q => \A[2]__14_n_0\,
R => '0'
);
\A[2]__15_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_35,
Q => \A[2]__15_srl29_n_0\,
Q31 => \NLW_A[2]__15_srl29_Q31_UNCONNECTED\
);
\A[2]__16\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__15_srl29_n_0\,
Q => \A[2]__16_n_0\,
R => '0'
);
\A[2]__18\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[2]__1_n_0\,
Q => \A[2]__18_n_0\,
R => '0'
);
\A[2]__24\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__26_n_0\,
Q => \A[2]__24_n_0\,
R => '0'
);
\A[2]__25_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_43,
Q => \A[2]__25_srl29_n_0\,
Q31 => \NLW_A[2]__25_srl29_Q31_UNCONNECTED\
);
\A[2]__26\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__25_srl29_n_0\,
Q => \A[2]__26_n_0\,
R => '0'
);
\A[2]__28\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[2]__3_n_0\,
Q => \A[2]__28_n_0\,
R => '0'
);
\A[2]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__6_n_0\,
Q => \A[2]__4_n_0\,
R => '0'
);
\A[2]__5_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_27,
Q => \A[2]__5_srl29_n_0\,
Q31 => \NLW_A[2]__5_srl29_Q31_UNCONNECTED\
);
\A[2]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__5_srl29_n_0\,
Q => \A[2]__6_n_0\,
R => '0'
);
\A[2]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => C(2),
Q => \A[2]__8_n_0\,
R => '0'
);
\A[3]__14\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__16_n_0\,
Q => \A[3]__14_n_0\,
R => '0'
);
\A[3]__15_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_36,
Q => \A[3]__15_srl29_n_0\,
Q31 => \NLW_A[3]__15_srl29_Q31_UNCONNECTED\
);
\A[3]__16\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__15_srl29_n_0\,
Q => \A[3]__16_n_0\,
R => '0'
);
\A[3]__18\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[3]__1_n_0\,
Q => \A[3]__18_n_0\,
R => '0'
);
\A[3]__24\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__26_n_0\,
Q => \A[3]__24_n_0\,
R => '0'
);
\A[3]__25_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_44,
Q => \A[3]__25_srl29_n_0\,
Q31 => \NLW_A[3]__25_srl29_Q31_UNCONNECTED\
);
\A[3]__26\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__25_srl29_n_0\,
Q => \A[3]__26_n_0\,
R => '0'
);
\A[3]__28\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[3]__3_n_0\,
Q => \A[3]__28_n_0\,
R => '0'
);
\A[3]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__6_n_0\,
Q => \A[3]__4_n_0\,
R => '0'
);
\A[3]__5_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_28,
Q => \A[3]__5_srl29_n_0\,
Q31 => \NLW_A[3]__5_srl29_Q31_UNCONNECTED\
);
\A[3]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__5_srl29_n_0\,
Q => \A[3]__6_n_0\,
R => '0'
);
\A[3]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => C(3),
Q => \A[3]__8_n_0\,
R => '0'
);
\A[4]__14\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__16_n_0\,
Q => \A[4]__14_n_0\,
R => '0'
);
\A[4]__15_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_37,
Q => \A[4]__15_srl29_n_0\,
Q31 => \NLW_A[4]__15_srl29_Q31_UNCONNECTED\
);
\A[4]__16\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__15_srl29_n_0\,
Q => \A[4]__16_n_0\,
R => '0'
);
\A[4]__18\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[4]__1_n_0\,
Q => \A[4]__18_n_0\,
R => '0'
);
\A[4]__24\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__26_n_0\,
Q => \A[4]__24_n_0\,
R => '0'
);
\A[4]__25_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_45,
Q => \A[4]__25_srl29_n_0\,
Q31 => \NLW_A[4]__25_srl29_Q31_UNCONNECTED\
);
\A[4]__26\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__25_srl29_n_0\,
Q => \A[4]__26_n_0\,
R => '0'
);
\A[4]__28\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[4]__3_n_0\,
Q => \A[4]__28_n_0\,
R => '0'
);
\A[4]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__6_n_0\,
Q => \A[4]__4_n_0\,
R => '0'
);
\A[4]__5_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_29,
Q => \A[4]__5_srl29_n_0\,
Q31 => \NLW_A[4]__5_srl29_Q31_UNCONNECTED\
);
\A[4]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__5_srl29_n_0\,
Q => \A[4]__6_n_0\,
R => '0'
);
\A[4]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => C(4),
Q => \A[4]__8_n_0\,
R => '0'
);
\A[5]__14\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__16_n_0\,
Q => \A[5]__14_n_0\,
R => '0'
);
\A[5]__15_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_38,
Q => \A[5]__15_srl29_n_0\,
Q31 => \NLW_A[5]__15_srl29_Q31_UNCONNECTED\
);
\A[5]__16\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__15_srl29_n_0\,
Q => \A[5]__16_n_0\,
R => '0'
);
\A[5]__18\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[5]__1_n_0\,
Q => \A[5]__18_n_0\,
R => '0'
);
\A[5]__24\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__26_n_0\,
Q => \A[5]__24_n_0\,
R => '0'
);
\A[5]__25_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_46,
Q => \A[5]__25_srl29_n_0\,
Q31 => \NLW_A[5]__25_srl29_Q31_UNCONNECTED\
);
\A[5]__26\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__25_srl29_n_0\,
Q => \A[5]__26_n_0\,
R => '0'
);
\A[5]__28\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[5]__3_n_0\,
Q => \A[5]__28_n_0\,
R => '0'
);
\A[5]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__6_n_0\,
Q => \A[5]__4_n_0\,
R => '0'
);
\A[5]__5_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_30,
Q => \A[5]__5_srl29_n_0\,
Q31 => \NLW_A[5]__5_srl29_Q31_UNCONNECTED\
);
\A[5]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__5_srl29_n_0\,
Q => \A[5]__6_n_0\,
R => '0'
);
\A[5]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => C(5),
Q => \A[5]__8_n_0\,
R => '0'
);
\A[6]__14\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__16_n_0\,
Q => \A[6]__14_n_0\,
R => '0'
);
\A[6]__15_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_39,
Q => \A[6]__15_srl29_n_0\,
Q31 => \NLW_A[6]__15_srl29_Q31_UNCONNECTED\
);
\A[6]__16\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__15_srl29_n_0\,
Q => \A[6]__16_n_0\,
R => '0'
);
\A[6]__18\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[6]__1_n_0\,
Q => \A[6]__18_n_0\,
R => '0'
);
\A[6]__24\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__26_n_0\,
Q => \A[6]__24_n_0\,
R => '0'
);
\A[6]__25_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_47,
Q => \A[6]__25_srl29_n_0\,
Q31 => \NLW_A[6]__25_srl29_Q31_UNCONNECTED\
);
\A[6]__26\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__25_srl29_n_0\,
Q => \A[6]__26_n_0\,
R => '0'
);
\A[6]__28\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[6]__3_n_0\,
Q => \A[6]__28_n_0\,
R => '0'
);
\A[6]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__6_n_0\,
Q => \A[6]__4_n_0\,
R => '0'
);
\A[6]__5_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_31,
Q => \A[6]__5_srl29_n_0\,
Q31 => \NLW_A[6]__5_srl29_Q31_UNCONNECTED\
);
\A[6]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__5_srl29_n_0\,
Q => \A[6]__6_n_0\,
R => '0'
);
\A[6]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => C(6),
Q => \A[6]__8_n_0\,
R => '0'
);
\A[7]__14\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__16_n_0\,
Q => \A[7]__14_n_0\,
R => '0'
);
\A[7]__15_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_40,
Q => \A[7]__15_srl29_n_0\,
Q31 => \NLW_A[7]__15_srl29_Q31_UNCONNECTED\
);
\A[7]__16\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__15_srl29_n_0\,
Q => \A[7]__16_n_0\,
R => '0'
);
\A[7]__18\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[7]__1_n_0\,
Q => \A[7]__18_n_0\,
R => '0'
);
\A[7]__24\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__26_n_0\,
Q => \A[7]__24_n_0\,
R => '0'
);
\A[7]__25_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_48,
Q => \A[7]__25_srl29_n_0\,
Q31 => \NLW_A[7]__25_srl29_Q31_UNCONNECTED\
);
\A[7]__26\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__25_srl29_n_0\,
Q => \A[7]__26_n_0\,
R => '0'
);
\A[7]__28\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[7]__3_n_0\,
Q => \A[7]__28_n_0\,
R => '0'
);
\A[7]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__6_n_0\,
Q => \A[7]__4_n_0\,
R => '0'
);
\A[7]__5_srl29\: unisim.vcomponents.SRLC32E
port map (
A(4 downto 0) => B"11100",
CE => active,
CLK => clk_25,
D => U0_n_32,
Q => \A[7]__5_srl29_n_0\,
Q31 => \NLW_A[7]__5_srl29_Q31_UNCONNECTED\
);
\A[7]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__5_srl29_n_0\,
Q => \A[7]__6_n_0\,
R => '0'
);
\A[7]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => C(7),
Q => \A[7]__8_n_0\,
R => '0'
);
\B[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__8_n_0\,
Q => \B_n_0_[0]\,
R => '0'
);
\B[0]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[0]__0_n_0\,
Q => B(0),
R => '0'
);
\B[0]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => B(0),
Q => \B[0]__1_n_0\,
R => '0'
);
\B[0]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__18_n_0\,
Q => \B[0]__3_n_0\,
R => '0'
);
\B[0]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[0]__2_n_0\,
Q => \B[0]__4_n_0\,
R => '0'
);
\B[0]__5\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[0]__4_n_0\,
Q => \B[0]__5_n_0\,
R => '0'
);
\B[0]__7\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[0]__28_n_0\,
Q => \B[0]__7_n_0\,
R => '0'
);
\B[0]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[0]__4_n_0\,
Q => \B[0]__8_n_0\,
R => '0'
);
\B[0]__9\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[0]__8_n_0\,
Q => \B[0]__9_n_0\,
R => '0'
);
\B[1]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__8_n_0\,
Q => \B[1]__0_n_0\,
R => '0'
);
\B[1]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[1]__0_n_0\,
Q => B(1),
R => '0'
);
\B[1]__10\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[1]__9_n_0\,
Q => \B[1]__10_n_0\,
R => '0'
);
\B[1]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => B(1),
Q => \B[1]__2_n_0\,
R => '0'
);
\B[1]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__18_n_0\,
Q => \B[1]__4_n_0\,
R => '0'
);
\B[1]__5\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[1]__2_n_0\,
Q => \B[1]__5_n_0\,
R => '0'
);
\B[1]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[1]__5_n_0\,
Q => \B[1]__6_n_0\,
R => '0'
);
\B[1]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[1]__28_n_0\,
Q => \B[1]__8_n_0\,
R => '0'
);
\B[1]__9\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[1]__4_n_0\,
Q => \B[1]__9_n_0\,
R => '0'
);
\B[2]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__8_n_0\,
Q => \B[2]__0_n_0\,
R => '0'
);
\B[2]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[2]__0_n_0\,
Q => B(2),
R => '0'
);
\B[2]__10\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[2]__9_n_0\,
Q => \B[2]__10_n_0\,
R => '0'
);
\B[2]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => B(2),
Q => \B[2]__2_n_0\,
R => '0'
);
\B[2]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__18_n_0\,
Q => \B[2]__4_n_0\,
R => '0'
);
\B[2]__5\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[2]__2_n_0\,
Q => \B[2]__5_n_0\,
R => '0'
);
\B[2]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[2]__5_n_0\,
Q => \B[2]__6_n_0\,
R => '0'
);
\B[2]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[2]__28_n_0\,
Q => \B[2]__8_n_0\,
R => '0'
);
\B[2]__9\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[2]__4_n_0\,
Q => \B[2]__9_n_0\,
R => '0'
);
\B[3]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__8_n_0\,
Q => \B[3]__0_n_0\,
R => '0'
);
\B[3]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[3]__0_n_0\,
Q => B(3),
R => '0'
);
\B[3]__10\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[3]__9_n_0\,
Q => \B[3]__10_n_0\,
R => '0'
);
\B[3]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => B(3),
Q => \B[3]__2_n_0\,
R => '0'
);
\B[3]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__18_n_0\,
Q => \B[3]__4_n_0\,
R => '0'
);
\B[3]__5\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[3]__2_n_0\,
Q => \B[3]__5_n_0\,
R => '0'
);
\B[3]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[3]__5_n_0\,
Q => \B[3]__6_n_0\,
R => '0'
);
\B[3]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[3]__28_n_0\,
Q => \B[3]__8_n_0\,
R => '0'
);
\B[3]__9\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[3]__4_n_0\,
Q => \B[3]__9_n_0\,
R => '0'
);
\B[4]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__8_n_0\,
Q => \B[4]__0_n_0\,
R => '0'
);
\B[4]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[4]__0_n_0\,
Q => B(4),
R => '0'
);
\B[4]__10\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[4]__9_n_0\,
Q => \B[4]__10_n_0\,
R => '0'
);
\B[4]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => B(4),
Q => \B[4]__2_n_0\,
R => '0'
);
\B[4]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__18_n_0\,
Q => \B[4]__4_n_0\,
R => '0'
);
\B[4]__5\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[4]__2_n_0\,
Q => \B[4]__5_n_0\,
R => '0'
);
\B[4]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[4]__5_n_0\,
Q => \B[4]__6_n_0\,
R => '0'
);
\B[4]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[4]__28_n_0\,
Q => \B[4]__8_n_0\,
R => '0'
);
\B[4]__9\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[4]__4_n_0\,
Q => \B[4]__9_n_0\,
R => '0'
);
\B[5]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__8_n_0\,
Q => \B[5]__0_n_0\,
R => '0'
);
\B[5]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[5]__0_n_0\,
Q => B(5),
R => '0'
);
\B[5]__10\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[5]__9_n_0\,
Q => \B[5]__10_n_0\,
R => '0'
);
\B[5]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => B(5),
Q => \B[5]__2_n_0\,
R => '0'
);
\B[5]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__18_n_0\,
Q => \B[5]__4_n_0\,
R => '0'
);
\B[5]__5\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[5]__2_n_0\,
Q => \B[5]__5_n_0\,
R => '0'
);
\B[5]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[5]__5_n_0\,
Q => \B[5]__6_n_0\,
R => '0'
);
\B[5]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[5]__28_n_0\,
Q => \B[5]__8_n_0\,
R => '0'
);
\B[5]__9\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[5]__4_n_0\,
Q => \B[5]__9_n_0\,
R => '0'
);
\B[6]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__8_n_0\,
Q => \B[6]__0_n_0\,
R => '0'
);
\B[6]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[6]__0_n_0\,
Q => B(6),
R => '0'
);
\B[6]__10\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[6]__9_n_0\,
Q => \B[6]__10_n_0\,
R => '0'
);
\B[6]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => B(6),
Q => \B[6]__2_n_0\,
R => '0'
);
\B[6]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__18_n_0\,
Q => \B[6]__4_n_0\,
R => '0'
);
\B[6]__5\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[6]__2_n_0\,
Q => \B[6]__5_n_0\,
R => '0'
);
\B[6]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[6]__5_n_0\,
Q => \B[6]__6_n_0\,
R => '0'
);
\B[6]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[6]__28_n_0\,
Q => \B[6]__8_n_0\,
R => '0'
);
\B[6]__9\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[6]__4_n_0\,
Q => \B[6]__9_n_0\,
R => '0'
);
\B[7]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__8_n_0\,
Q => \B[7]__0_n_0\,
R => '0'
);
\B[7]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[7]__0_n_0\,
Q => B(7),
R => '0'
);
\B[7]__10\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[7]__9_n_0\,
Q => \B[7]__10_n_0\,
R => '0'
);
\B[7]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => B(7),
Q => \B[7]__2_n_0\,
R => '0'
);
\B[7]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__18_n_0\,
Q => \B[7]__4_n_0\,
R => '0'
);
\B[7]__5\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[7]__2_n_0\,
Q => \B[7]__5_n_0\,
R => '0'
);
\B[7]__6\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \B[7]__5_n_0\,
Q => \B[7]__6_n_0\,
R => '0'
);
\B[7]__8\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \A[7]__28_n_0\,
Q => \B[7]__8_n_0\,
R => '0'
);
\B[7]__9\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => \C[7]__4_n_0\,
Q => \B[7]__9_n_0\,
R => '0'
);
\C[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(0),
Q => C(0),
R => '0'
);
\C[0]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_1,
Q => \C[0]__0_n_0\,
R => '0'
);
\C[0]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(8),
Q => \C[0]__1_n_0\,
R => '0'
);
\C[0]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_9,
Q => \C[0]__2_n_0\,
R => '0'
);
\C[0]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(16),
Q => \C[0]__3_n_0\,
R => '0'
);
\C[0]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_17,
Q => \C[0]__4_n_0\,
R => '0'
);
\C[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(1),
Q => C(1),
R => '0'
);
\C[1]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_2,
Q => \C[1]__0_n_0\,
R => '0'
);
\C[1]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(9),
Q => \C[1]__1_n_0\,
R => '0'
);
\C[1]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_10,
Q => \C[1]__2_n_0\,
R => '0'
);
\C[1]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(17),
Q => \C[1]__3_n_0\,
R => '0'
);
\C[1]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_18,
Q => \C[1]__4_n_0\,
R => '0'
);
\C[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(2),
Q => C(2),
R => '0'
);
\C[2]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_3,
Q => \C[2]__0_n_0\,
R => '0'
);
\C[2]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(10),
Q => \C[2]__1_n_0\,
R => '0'
);
\C[2]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_11,
Q => \C[2]__2_n_0\,
R => '0'
);
\C[2]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(18),
Q => \C[2]__3_n_0\,
R => '0'
);
\C[2]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_19,
Q => \C[2]__4_n_0\,
R => '0'
);
\C[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(3),
Q => C(3),
R => '0'
);
\C[3]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_4,
Q => \C[3]__0_n_0\,
R => '0'
);
\C[3]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(11),
Q => \C[3]__1_n_0\,
R => '0'
);
\C[3]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_12,
Q => \C[3]__2_n_0\,
R => '0'
);
\C[3]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(19),
Q => \C[3]__3_n_0\,
R => '0'
);
\C[3]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_20,
Q => \C[3]__4_n_0\,
R => '0'
);
\C[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(4),
Q => C(4),
R => '0'
);
\C[4]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_5,
Q => \C[4]__0_n_0\,
R => '0'
);
\C[4]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(12),
Q => \C[4]__1_n_0\,
R => '0'
);
\C[4]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_13,
Q => \C[4]__2_n_0\,
R => '0'
);
\C[4]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(20),
Q => \C[4]__3_n_0\,
R => '0'
);
\C[4]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_21,
Q => \C[4]__4_n_0\,
R => '0'
);
\C[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(5),
Q => C(5),
R => '0'
);
\C[5]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_6,
Q => \C[5]__0_n_0\,
R => '0'
);
\C[5]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(13),
Q => \C[5]__1_n_0\,
R => '0'
);
\C[5]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_14,
Q => \C[5]__2_n_0\,
R => '0'
);
\C[5]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(21),
Q => \C[5]__3_n_0\,
R => '0'
);
\C[5]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_22,
Q => \C[5]__4_n_0\,
R => '0'
);
\C[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(6),
Q => C(6),
R => '0'
);
\C[6]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_7,
Q => \C[6]__0_n_0\,
R => '0'
);
\C[6]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(14),
Q => \C[6]__1_n_0\,
R => '0'
);
\C[6]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_15,
Q => \C[6]__2_n_0\,
R => '0'
);
\C[6]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(22),
Q => \C[6]__3_n_0\,
R => '0'
);
\C[6]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_23,
Q => \C[6]__4_n_0\,
R => '0'
);
\C[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(7),
Q => C(7),
R => '0'
);
\C[7]__0\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_8,
Q => \C[7]__0_n_0\,
R => '0'
);
\C[7]__1\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(15),
Q => \C[7]__1_n_0\,
R => '0'
);
\C[7]__2\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_16,
Q => \C[7]__2_n_0\,
R => '0'
);
\C[7]__3\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => rgb_in(23),
Q => \C[7]__3_n_0\,
R => '0'
);
\C[7]__4\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => active,
D => U0_n_24,
Q => \C[7]__4_n_0\,
R => '0'
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_vga_gaussian_blur_0_0_vga_gaussian_blur
port map (
\A[0]__16\ => U0_n_33,
\A[0]__26\ => U0_n_41,
\A[0]__6\ => U0_n_25,
\A[1]__16\ => U0_n_34,
\A[1]__26\ => U0_n_42,
\A[1]__6\ => U0_n_26,
\A[2]__16\ => U0_n_35,
\A[2]__26\ => U0_n_43,
\A[2]__6\ => U0_n_27,
\A[3]__16\ => U0_n_36,
\A[3]__26\ => U0_n_44,
\A[3]__6\ => U0_n_28,
\A[4]__16\ => U0_n_37,
\A[4]__26\ => U0_n_45,
\A[4]__6\ => U0_n_29,
\A[5]__16\ => U0_n_38,
\A[5]__26\ => U0_n_46,
\A[5]__6\ => U0_n_30,
\A[6]__16\ => U0_n_39,
\A[6]__26\ => U0_n_47,
\A[6]__6\ => U0_n_31,
\A[7]__16\ => U0_n_40,
\A[7]__26\ => U0_n_48,
\A[7]__6\ => U0_n_32,
\B[0]\ => \B_n_0_[0]\,
\B[0]__3\ => \B[0]__3_n_0\,
\B[0]__7\ => \B[0]__7_n_0\,
\B[1]__0\ => \B[1]__0_n_0\,
\B[1]__4\ => \B[1]__4_n_0\,
\B[1]__8\ => \B[1]__8_n_0\,
\B[2]__0\ => \B[2]__0_n_0\,
\B[2]__4\ => \B[2]__4_n_0\,
\B[2]__8\ => \B[2]__8_n_0\,
\B[3]__0\ => \B[3]__0_n_0\,
\B[3]__4\ => \B[3]__4_n_0\,
\B[3]__8\ => \B[3]__8_n_0\,
\B[4]__0\ => \B[4]__0_n_0\,
\B[4]__4\ => \B[4]__4_n_0\,
\B[4]__8\ => \B[4]__8_n_0\,
\B[5]__0\ => \B[5]__0_n_0\,
\B[5]__4\ => \B[5]__4_n_0\,
\B[5]__8\ => \B[5]__8_n_0\,
\B[6]__0\ => \B[6]__0_n_0\,
\B[6]__4\ => \B[6]__4_n_0\,
\B[6]__8\ => \B[6]__8_n_0\,
\B[7]__0\ => \B[7]__0_n_0\,
\B[7]__1\(7 downto 0) => B(7 downto 0),
\B[7]__10\(7) => \B[7]__10_n_0\,
\B[7]__10\(6) => \B[6]__10_n_0\,
\B[7]__10\(5) => \B[5]__10_n_0\,
\B[7]__10\(4) => \B[4]__10_n_0\,
\B[7]__10\(3) => \B[3]__10_n_0\,
\B[7]__10\(2) => \B[2]__10_n_0\,
\B[7]__10\(1) => \B[1]__10_n_0\,
\B[7]__10\(0) => \B[0]__9_n_0\,
\B[7]__4\ => \B[7]__4_n_0\,
\B[7]__5\(7) => \B[7]__5_n_0\,
\B[7]__5\(6) => \B[6]__5_n_0\,
\B[7]__5\(5) => \B[5]__5_n_0\,
\B[7]__5\(4) => \B[4]__5_n_0\,
\B[7]__5\(3) => \B[3]__5_n_0\,
\B[7]__5\(2) => \B[2]__5_n_0\,
\B[7]__5\(1) => \B[1]__5_n_0\,
\B[7]__5\(0) => \B[0]__4_n_0\,
\B[7]__6\(7) => \B[7]__6_n_0\,
\B[7]__6\(6) => \B[6]__6_n_0\,
\B[7]__6\(5) => \B[5]__6_n_0\,
\B[7]__6\(4) => \B[4]__6_n_0\,
\B[7]__6\(3) => \B[3]__6_n_0\,
\B[7]__6\(2) => \B[2]__6_n_0\,
\B[7]__6\(1) => \B[1]__6_n_0\,
\B[7]__6\(0) => \B[0]__5_n_0\,
\B[7]__8\ => \B[7]__8_n_0\,
\B[7]__9\(7) => \B[7]__9_n_0\,
\B[7]__9\(6) => \B[6]__9_n_0\,
\B[7]__9\(5) => \B[5]__9_n_0\,
\B[7]__9\(4) => \B[4]__9_n_0\,
\B[7]__9\(3) => \B[3]__9_n_0\,
\B[7]__9\(2) => \B[2]__9_n_0\,
\B[7]__9\(1) => \B[1]__9_n_0\,
\B[7]__9\(0) => \B[0]__8_n_0\,
\C[0]__0\ => U0_n_1,
\C[0]__0_0\ => \C[0]__0_n_0\,
\C[0]__1\ => \C[0]__1_n_0\,
\C[0]__2\ => U0_n_9,
\C[0]__2_0\ => \C[0]__2_n_0\,
\C[0]__3\ => \C[0]__3_n_0\,
\C[0]__4\ => U0_n_17,
\C[0]__4_0\ => \C[0]__4_n_0\,
\C[1]__0\ => U0_n_2,
\C[1]__0_0\ => \C[1]__0_n_0\,
\C[1]__1\ => \C[1]__1_n_0\,
\C[1]__2\ => U0_n_10,
\C[1]__2_0\ => \C[1]__2_n_0\,
\C[1]__3\ => \C[1]__3_n_0\,
\C[1]__4\ => U0_n_18,
\C[1]__4_0\ => \C[1]__4_n_0\,
\C[2]__0\ => U0_n_3,
\C[2]__0_0\ => \C[2]__0_n_0\,
\C[2]__1\ => \C[2]__1_n_0\,
\C[2]__2\ => U0_n_11,
\C[2]__2_0\ => \C[2]__2_n_0\,
\C[2]__3\ => \C[2]__3_n_0\,
\C[2]__4\ => U0_n_19,
\C[2]__4_0\ => \C[2]__4_n_0\,
\C[3]__0\ => U0_n_4,
\C[3]__0_0\ => \C[3]__0_n_0\,
\C[3]__1\ => \C[3]__1_n_0\,
\C[3]__2\ => U0_n_12,
\C[3]__2_0\ => \C[3]__2_n_0\,
\C[3]__3\ => \C[3]__3_n_0\,
\C[3]__4\ => U0_n_20,
\C[3]__4_0\ => \C[3]__4_n_0\,
\C[4]__0\ => U0_n_5,
\C[4]__0_0\ => \C[4]__0_n_0\,
\C[4]__1\ => \C[4]__1_n_0\,
\C[4]__2\ => U0_n_13,
\C[4]__2_0\ => \C[4]__2_n_0\,
\C[4]__3\ => \C[4]__3_n_0\,
\C[4]__4\ => U0_n_21,
\C[4]__4_0\ => \C[4]__4_n_0\,
\C[5]__0\ => U0_n_6,
\C[5]__0_0\ => \C[5]__0_n_0\,
\C[5]__1\ => \C[5]__1_n_0\,
\C[5]__2\ => U0_n_14,
\C[5]__2_0\ => \C[5]__2_n_0\,
\C[5]__3\ => \C[5]__3_n_0\,
\C[5]__4\ => U0_n_22,
\C[5]__4_0\ => \C[5]__4_n_0\,
\C[6]__0\ => U0_n_7,
\C[6]__0_0\ => \C[6]__0_n_0\,
\C[6]__1\ => \C[6]__1_n_0\,
\C[6]__2\ => U0_n_15,
\C[6]__2_0\ => \C[6]__2_n_0\,
\C[6]__3\ => \C[6]__3_n_0\,
\C[6]__4\ => U0_n_23,
\C[6]__4_0\ => \C[6]__4_n_0\,
\C[7]\(7 downto 0) => C(7 downto 0),
\C[7]__0\ => U0_n_8,
\C[7]__0_0\ => \C[7]__0_n_0\,
\C[7]__1\ => \C[7]__1_n_0\,
\C[7]__2\ => U0_n_16,
\C[7]__2_0\ => \C[7]__2_n_0\,
\C[7]__3\ => \C[7]__3_n_0\,
\C[7]__4\ => U0_n_24,
\C[7]__4_0\ => \C[7]__4_n_0\,
D(23) => \A[7]__24_n_0\,
D(22) => \A[6]__24_n_0\,
D(21) => \A[5]__24_n_0\,
D(20) => \A[4]__24_n_0\,
D(19) => \A[3]__24_n_0\,
D(18) => \A[2]__24_n_0\,
D(17) => \A[1]__24_n_0\,
D(16) => \A[0]__24_n_0\,
D(15) => \A[7]__14_n_0\,
D(14) => \A[6]__14_n_0\,
D(13) => \A[5]__14_n_0\,
D(12) => \A[4]__14_n_0\,
D(11) => \A[3]__14_n_0\,
D(10) => \A[2]__14_n_0\,
D(9) => \A[1]__14_n_0\,
D(8) => \A[0]__14_n_0\,
D(7) => \A[7]__4_n_0\,
D(6) => \A[6]__4_n_0\,
D(5) => \A[5]__4_n_0\,
D(4) => \A[4]__4_n_0\,
D(3) => \A[3]__4_n_0\,
D(2) => \A[2]__4_n_0\,
D(1) => \A[1]__4_n_0\,
D(0) => \A[0]__4_n_0\,
I12(7) => \A[7]__26_n_0\,
I12(6) => \A[6]__26_n_0\,
I12(5) => \A[5]__26_n_0\,
I12(4) => \A[4]__26_n_0\,
I12(3) => \A[3]__26_n_0\,
I12(2) => \A[2]__26_n_0\,
I12(1) => \A[1]__26_n_0\,
I12(0) => \A[0]__26_n_0\,
I13(7) => \A[7]__28_n_0\,
I13(6) => \A[6]__28_n_0\,
I13(5) => \A[5]__28_n_0\,
I13(4) => \A[4]__28_n_0\,
I13(3) => \A[3]__28_n_0\,
I13(2) => \A[2]__28_n_0\,
I13(1) => \A[1]__28_n_0\,
I13(0) => \A[0]__28_n_0\,
I6(7) => \A[7]__16_n_0\,
I6(6) => \A[6]__16_n_0\,
I6(5) => \A[5]__16_n_0\,
I6(4) => \A[4]__16_n_0\,
I6(3) => \A[3]__16_n_0\,
I6(2) => \A[2]__16_n_0\,
I6(1) => \A[1]__16_n_0\,
I6(0) => \A[0]__16_n_0\,
I7(7) => \A[7]__18_n_0\,
I7(6) => \A[6]__18_n_0\,
I7(5) => \A[5]__18_n_0\,
I7(4) => \A[4]__18_n_0\,
I7(3) => \A[3]__18_n_0\,
I7(2) => \A[2]__18_n_0\,
I7(1) => \A[1]__18_n_0\,
I7(0) => \A[0]__18_n_0\,
Q(7) => \B[7]__2_n_0\,
Q(6) => \B[6]__2_n_0\,
Q(5) => \B[5]__2_n_0\,
Q(4) => \B[4]__2_n_0\,
Q(3) => \B[3]__2_n_0\,
Q(2) => \B[2]__2_n_0\,
Q(1) => \B[1]__2_n_0\,
Q(0) => \B[0]__1_n_0\,
active => active,
clk_25 => clk_25,
hsync_in => hsync_in,
rgb_blur(23 downto 0) => rgb_blur(23 downto 0),
rgb_blur11(7) => \A[7]__8_n_0\,
rgb_blur11(6) => \A[6]__8_n_0\,
rgb_blur11(5) => \A[5]__8_n_0\,
rgb_blur11(4) => \A[4]__8_n_0\,
rgb_blur11(3) => \A[3]__8_n_0\,
rgb_blur11(2) => \A[2]__8_n_0\,
rgb_blur11(1) => \A[1]__8_n_0\,
rgb_blur11(0) => \A[0]__8_n_0\,
rgb_blur9(7) => \A[7]__6_n_0\,
rgb_blur9(6) => \A[6]__6_n_0\,
rgb_blur9(5) => \A[5]__6_n_0\,
rgb_blur9(4) => \A[4]__6_n_0\,
rgb_blur9(3) => \A[3]__6_n_0\,
rgb_blur9(2) => \A[2]__6_n_0\,
rgb_blur9(1) => \A[1]__6_n_0\,
rgb_blur9(0) => \A[0]__6_n_0\,
rgb_pass(23 downto 0) => rgb_pass(23 downto 0),
vsync_in => vsync_in
);
end STRUCTURE;
| mit | 905104856bfc50ff37c0a73d6dbed6d9 | 0.568259 | 2.478224 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/hdl/driver_stages.vhd | 2 | 4,009 | -------------------------------------------------------------------------------
-- Title : Driver Stage Converters
-- Project :
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Convert the interface for DC and BLDC motors to driver stages
-- with halfbridges from ST.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
entity bldc_driver_stage_converter is
port (
bldc_driver_stage : in bldc_driver_stage_type;
bldc_driver_stage_st : out bldc_driver_stage_st_type
);
end bldc_driver_stage_converter;
architecture structural of bldc_driver_stage_converter is
signal shoot_through_a : std_logic := '0'; -- The bridge is requested to do
-- a shoot through. This should never happen.
signal shoot_through_b : std_logic := '0';
signal shoot_through_c : std_logic := '0';
signal shoot_through : std_logic;
begin
shoot_through_a <= '1' when ((bldc_driver_stage.a.high = '1') and (bldc_driver_stage.a.low = '1')) else '0';
shoot_through_b <= '1' when ((bldc_driver_stage.b.high = '1') and (bldc_driver_stage.b.low = '1')) else '0';
shoot_through_c <= '1' when ((bldc_driver_stage.c.high = '1') and (bldc_driver_stage.c.low = '1')) else '0';
shoot_through <= shoot_through_a or shoot_through_b or shoot_through_c;
bldc_driver_stage_st.a.high <= '1' when ((bldc_driver_stage.a.high = '1') and (shoot_through = '0')) else '0';
bldc_driver_stage_st.a.low_n <= '0' when ((bldc_driver_stage.a.low = '1') and (shoot_through = '0')) else '1';
bldc_driver_stage_st.b.high <= '1' when ((bldc_driver_stage.b.high = '1') and (shoot_through = '0')) else '0';
bldc_driver_stage_st.b.low_n <= '0' when ((bldc_driver_stage.b.low = '1') and (shoot_through = '0')) else '1';
bldc_driver_stage_st.c.high <= '1' when ((bldc_driver_stage.c.high = '1') and (shoot_through = '0')) else '0';
bldc_driver_stage_st.c.low_n <= '0' when ((bldc_driver_stage.c.low = '1') and (shoot_through = '0')) else '1';
end structural;
---------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.motor_control_pkg.all;
-- Convert from PWM1/2 + shutdown interface to ST halfbridge
entity dc_driver_stage_converter is
port (
pwm1_in_p : in std_logic;
pwm2_in_p : in std_logic;
sd_in_p : in std_logic;
dc_driver_stage_st_out_p : out dc_driver_stage_st_type
);
end dc_driver_stage_converter;
architecture structural of dc_driver_stage_converter is
begin
process (pwm1_in_p, pwm2_in_p, sd_in_p)
begin
if sd_in_p = '1' then
-- disable both
dc_driver_stage_st_out_p.a.high <= '0';
dc_driver_stage_st_out_p.a.low_n <= '1';
dc_driver_stage_st_out_p.b.high <= '0';
dc_driver_stage_st_out_p.b.low_n <= '1';
else
if pwm1_in_p = '0' then
dc_driver_stage_st_out_p.a.high <= '0';
dc_driver_stage_st_out_p.a.low_n <= '0';
else
dc_driver_stage_st_out_p.a.high <= '1';
dc_driver_stage_st_out_p.a.low_n <= '1';
end if;
if pwm2_in_p = '0' then
dc_driver_stage_st_out_p.b.high <= '0';
dc_driver_stage_st_out_p.b.low_n <= '0';
else
dc_driver_stage_st_out_p.b.high <= '1';
dc_driver_stage_st_out_p.b.low_n <= '1';
end if;
end if;
end process;
end structural;
| bsd-3-clause | 3c1f10cd6b4ecd5d0cdc8c917758c1ba | 0.520828 | 3.22008 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_1_0/synth/system_vga_nmsuppression_1_0.vhd | 1 | 4,831 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_nmsuppression:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_nmsuppression_1_0 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_nmsuppression_1_0;
ARCHITECTURE system_vga_nmsuppression_1_0_arch OF system_vga_nmsuppression_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_nmsuppression_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_nmsuppression IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_nmsuppression;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_nmsuppression_1_0_arch: ARCHITECTURE IS "vga_nmsuppression,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_nmsuppression_1_0_arch : ARCHITECTURE IS "system_vga_nmsuppression_1_0,vga_nmsuppression,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_nmsuppression_1_0_arch: ARCHITECTURE IS "system_vga_nmsuppression_1_0,vga_nmsuppression,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_nmsuppression,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_nmsuppression
GENERIC MAP (
ROW_WIDTH => 5
)
PORT MAP (
clk => clk,
enable => enable,
active => active,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
hessian_in => hessian_in,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out,
hessian_out => hessian_out
);
END system_vga_nmsuppression_1_0_arch;
| mit | 6d3f8eeb29c49ed3f315647d40128821 | 0.721176 | 3.591822 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_jtag_uart_0_avalon_jtag_slave_translator.vhd | 1 | 14,737 | -- niosii_system_jtag_uart_0_avalon_jtag_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W : integer := 1;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(0 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(0 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_jtag_uart_0_avalon_jtag_slave_translator;
architecture rtl of niosii_system_jtag_uart_0_avalon_jtag_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
jtag_uart_0_avalon_jtag_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_waitrequest => av_waitrequest, -- .waitrequest
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_jtag_uart_0_avalon_jtag_slave_translator
| apache-2.0 | 3b02c729e427be117ee912361e857a5d | 0.431024 | 4.344634 | false | false | false | false |
loa-org/loa-hdl | modules/servo/tb/servo_sequencer_tb.vhd | 2 | 1,519 | -------------------------------------------------------------------------------
-- Title : Testbench for design "servo_sequencer"
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.servo_sequencer_pkg.all;
-------------------------------------------------------------------------------
entity servo_sequencer_tb is
end servo_sequencer_tb;
-------------------------------------------------------------------------------
architecture tb of servo_sequencer_tb is
-- component ports
signal load : std_logic_vector(7 downto 0);
signal enable : std_logic_vector(7 downto 0);
signal counter : std_logic_vector(15 downto 0);
signal clk : std_logic := '0';
signal reset : std_logic := '1';
begin
-- component instantiation
DUT : servo_sequencer
port map (
load_p => load,
enable_p => enable,
counter_p => counter,
reset => reset,
clk => clk);
-- clock generation
clk <= not clk after 10 NS;
reset <= '1', '0' after 30 NS;
-- waveform : process
-- begin
-- wait until falling_edge(reset);
--
-- end process waveform;
end tb;
| bsd-3-clause | 926b6c8d40a992e31401bc73f7ea3e7c | 0.420671 | 4.9 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/inst/cpu_l1mem_inst_types_pkg.vhdl | 1 | 3,733 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package cpu_l1mem_inst_types_pkg is
type cpu_l1mem_inst_request_code_index_type is (
cpu_l1mem_inst_request_code_index_none,
cpu_l1mem_inst_request_code_index_fetch,
cpu_l1mem_inst_request_code_index_invalidate,
cpu_l1mem_inst_request_code_index_sync
);
type cpu_l1mem_inst_request_code_type is
array (cpu_l1mem_inst_request_code_index_type range
cpu_l1mem_inst_request_code_index_type'high downto
cpu_l1mem_inst_request_code_index_type'low) of std_ulogic;
constant cpu_l1mem_inst_request_code_none : cpu_l1mem_inst_request_code_type := "0001";
constant cpu_l1mem_inst_request_code_fetch : cpu_l1mem_inst_request_code_type := "0010";
constant cpu_l1mem_inst_request_code_invalidate : cpu_l1mem_inst_request_code_type := "0100";
constant cpu_l1mem_inst_request_code_sync : cpu_l1mem_inst_request_code_type := "1000";
type cpu_l1mem_inst_fetch_direction_index_type is (
cpu_l1mem_inst_fetch_direction_index_seq,
cpu_l1mem_inst_fetch_direction_index_dir,
cpu_l1mem_inst_fetch_direction_index_indir
);
type cpu_l1mem_inst_fetch_direction_type is
array (cpu_l1mem_inst_fetch_direction_index_type range
cpu_l1mem_inst_fetch_direction_index_type'high downto
cpu_l1mem_inst_fetch_direction_index_type'low) of std_ulogic;
constant cpu_l1mem_inst_fetch_direction_seq : cpu_l1mem_inst_fetch_direction_type := "001";
constant cpu_l1mem_inst_fetch_direction_dir : cpu_l1mem_inst_fetch_direction_type := "010";
constant cpu_l1mem_inst_fetch_direction_indir : cpu_l1mem_inst_fetch_direction_type := "100";
type cpu_l1mem_inst_result_code_index_type is (
cpu_l1mem_inst_result_code_index_valid,
cpu_l1mem_inst_result_code_index_error,
cpu_l1mem_inst_result_code_index_tlbmiss,
cpu_l1mem_inst_result_code_index_pf
);
type cpu_l1mem_inst_result_code_type is
array (cpu_l1mem_inst_result_code_index_type range
cpu_l1mem_inst_result_code_index_type'high downto
cpu_l1mem_inst_result_code_index_type'low) of std_ulogic;
constant cpu_l1mem_inst_result_code_valid : cpu_l1mem_inst_result_code_type := "0001";
constant cpu_l1mem_inst_result_code_error : cpu_l1mem_inst_result_code_type := "0010";
constant cpu_l1mem_inst_result_code_tlbmiss : cpu_l1mem_inst_result_code_type := "0100";
constant cpu_l1mem_inst_result_code_pf : cpu_l1mem_inst_result_code_type := "1000";
end package;
| apache-2.0 | ba844aa810f9a720a23fdbebb0eb402f | 0.631931 | 3.406022 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.vhdl | 1 | 129,298 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:46:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zybo_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
shift_blue : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \dc_bias[0]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_12__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_13__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_14__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_15__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_1__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_28__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_29__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_30__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_31__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_32__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_33__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9__1_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded[0]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[1]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[1]_i_2_n_0\ : STD_LOGIC;
signal \encoded[2]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[2]_i_2_n_0\ : STD_LOGIC;
signal \encoded[3]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[3]_i_2_n_0\ : STD_LOGIC;
signal \encoded[4]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[4]_i_2_n_0\ : STD_LOGIC;
signal \encoded[5]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[5]_i_2_n_0\ : STD_LOGIC;
signal \encoded[6]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[6]_i_2__1_n_0\ : STD_LOGIC;
signal \encoded[7]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2__1_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1__1_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_3__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \dc_bias[1]_i_3__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \dc_bias[1]_i_4__1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \dc_bias[1]_i_6__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \dc_bias[1]_i_7__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \dc_bias[1]_i_9__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \dc_bias[2]_i_11__1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \dc_bias[2]_i_14__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \dc_bias[2]_i_15__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \dc_bias[2]_i_7__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \dc_bias[2]_i_9__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \dc_bias[3]_i_11__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \dc_bias[3]_i_19__1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \dc_bias[3]_i_26__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \dc_bias[3]_i_29__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \encoded[1]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \encoded[2]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \encoded[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \encoded[4]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \encoded[6]_i_2__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \encoded[7]_i_2__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \encoded[8]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \shift_blue[0]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \shift_blue[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \shift_blue[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \shift_blue[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \shift_blue[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \shift_blue[5]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \shift_blue[6]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \shift_blue[7]_i_1\ : label is "soft_lutpair11";
begin
SR(0) <= \^sr\(0);
\dc_bias[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9F90909F909F9F90"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[2]_i_2__0_n_0\,
I4 => \dc_bias[0]_i_3__1_n_0\,
I5 => \dc_bias[0]_i_4__1_n_0\,
O => \dc_bias[0]_i_1__1_n_0\
);
\dc_bias[0]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => \dc_bias[0]_i_5__0_n_0\,
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[0]_i_2__1_n_0\
);
\dc_bias[0]_i_3__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3__1_n_0\
);
\dc_bias[0]_i_4__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[0]_i_4__1_n_0\
);
\dc_bias[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6696969999696966"
)
port map (
I0 => rgb(6),
I1 => rgb(4),
I2 => \dc_bias[2]_i_13__0_n_0\,
I3 => \dc_bias[3]_i_13__0_n_0\,
I4 => \dc_bias[2]_i_12__0_n_0\,
I5 => \encoded[3]_i_2_n_0\,
O => \dc_bias[0]_i_5__0_n_0\
);
\dc_bias[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5C0CFCACFCAC5C0"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[1]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[1]_i_3__1_n_0\,
I4 => \dc_bias[1]_i_4__1_n_0\,
I5 => \dc_bias[1]_i_5__1_n_0\,
O => \dc_bias[1]_i_1__0_n_0\
);
\dc_bias[1]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias[1]_i_6__0_n_0\,
I1 => \dc_bias[1]_i_7__1_n_0\,
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \dc_bias[1]_i_8_n_0\,
I4 => \dc_bias[1]_i_9__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[1]_i_2__1_n_0\
);
\dc_bias[1]_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5695"
)
port map (
I0 => \dc_bias[1]_i_7__1_n_0\,
I1 => \dc_bias[0]_i_2__1_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[1]_i_3__1_n_0\
);
\dc_bias[1]_i_4__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D7BE2841"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => \dc_bias[2]_i_10_n_0\,
O => \dc_bias[1]_i_4__1_n_0\
);
\dc_bias[1]_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EB7D7DEB7D14147D"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[3]_i_2_n_0\,
I5 => \dc_bias[0]_i_4__1_n_0\,
O => \dc_bias[1]_i_5__1_n_0\
);
\dc_bias[1]_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__1_n_0\,
O => \dc_bias[1]_i_6__0_n_0\
);
\dc_bias[1]_i_7__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_25__1_n_0\,
O => \dc_bias[1]_i_7__1_n_0\
);
\dc_bias[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"14D782BE82BE14D7"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => \dc_bias[3]_i_31__0_n_0\,
I3 => \dc_bias[0]_i_5__0_n_0\,
I4 => rgb(3),
I5 => rgb(1),
O => \dc_bias[1]_i_8_n_0\
);
\dc_bias[1]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6A56566A"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => \encoded[7]_i_2__1_n_0\,
O => \dc_bias[1]_i_9__0_n_0\
);
\dc_bias[2]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"9A5965A665A69A59"
)
port map (
I0 => \dc_bias[2]_i_8__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(7),
I3 => \encoded[6]_i_2__1_n_0\,
I4 => \dc_bias_reg_n_0_[1]\,
I5 => \dc_bias[2]_i_14__0_n_0\,
O => \dc_bias[2]_i_10_n_0\
);
\dc_bias[2]_i_11__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82EBEB82"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[3]_i_2_n_0\,
O => \dc_bias[2]_i_11__1_n_0\
);
\dc_bias[2]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"022BBFFF"
)
port map (
I0 => \dc_bias[2]_i_15__0_n_0\,
I1 => rgb(0),
I2 => rgb(7),
I3 => \dc_bias[3]_i_29__0_n_0\,
I4 => \dc_bias[3]_i_12__1_n_0\,
O => \dc_bias[2]_i_12__0_n_0\
);
\dc_bias[2]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"79E9EF7FFFFFFFFF"
)
port map (
I0 => rgb(7),
I1 => \dc_bias[3]_i_29__0_n_0\,
I2 => \encoded[3]_i_2_n_0\,
I3 => \dc_bias[2]_i_15__0_n_0\,
I4 => \dc_bias[3]_i_12__1_n_0\,
I5 => rgb(0),
O => \dc_bias[2]_i_13__0_n_0\
);
\dc_bias[2]_i_14__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_14__0_n_0\
);
\dc_bias[2]_i_15__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[2]_i_15__0_n_0\
);
\dc_bias[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5C0CFCACFCAC5C0"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[2]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => \dc_bias[2]_i_4__1_n_0\,
I4 => \dc_bias[2]_i_5__1_n_0\,
I5 => \dc_bias[2]_i_6__1_n_0\,
O => \dc_bias[2]_i_1__1_n_0\
);
\dc_bias[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"999999A999A9AAAA"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_21_n_0\,
I2 => \dc_bias[3]_i_20__0_n_0\,
I3 => \dc_bias[3]_i_19__1_n_0\,
I4 => \dc_bias[3]_i_18__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[2]_i_2__0_n_0\
);
\dc_bias[2]_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6699A5A566995A5A"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_14__0_n_0\,
I2 => \dc_bias[3]_i_9__1_n_0\,
I3 => \dc_bias[3]_i_15__1_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[3]_i_8__1_n_0\,
O => \dc_bias[2]_i_3__1_n_0\
);
\dc_bias[2]_i_4__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4BB4B44B"
)
port map (
I0 => \dc_bias[3]_i_25__1_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias[3]_i_14__0_n_0\,
I4 => \dc_bias[3]_i_26__1_n_0\,
O => \dc_bias[2]_i_4__1_n_0\
);
\dc_bias[2]_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"75F710518A08EFAE"
)
port map (
I0 => \dc_bias[2]_i_7__0_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(7),
I3 => \encoded[6]_i_2__1_n_0\,
I4 => \dc_bias[2]_i_8__1_n_0\,
I5 => \dc_bias[2]_i_9__0_n_0\,
O => \dc_bias[2]_i_5__1_n_0\
);
\dc_bias[2]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"177E777777777E17"
)
port map (
I0 => \dc_bias[2]_i_10_n_0\,
I1 => \dc_bias[2]_i_11__1_n_0\,
I2 => \dc_bias[0]_i_3__1_n_0\,
I3 => \encoded[1]_i_2_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => rgb(2),
O => \dc_bias[2]_i_6__1_n_0\
);
\dc_bias[2]_i_7__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
O => \dc_bias[2]_i_7__0_n_0\
);
\dc_bias[2]_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2DB4B4B42D2D2DB4"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => \encoded[3]_i_2_n_0\,
I3 => \dc_bias[2]_i_12__0_n_0\,
I4 => \dc_bias[3]_i_13__0_n_0\,
I5 => \dc_bias[2]_i_13__0_n_0\,
O => \dc_bias[2]_i_8__1_n_0\
);
\dc_bias[2]_i_9__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA95"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[2]_i_9__0_n_0\
);
\dc_bias[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \^sr\(0)
);
\dc_bias[3]_i_10__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"69FFFF69FF6969FF"
)
port map (
I0 => rgb(1),
I1 => rgb(2),
I2 => rgb(3),
I3 => rgb(0),
I4 => rgb(7),
I5 => \dc_bias[3]_i_29__0_n_0\,
O => \dc_bias[3]_i_10__1_n_0\
);
\dc_bias[3]_i_11__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"17717117"
)
port map (
I0 => rgb(0),
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \dc_bias[3]_i_11__1_n_0\
);
\dc_bias[3]_i_12__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717E817E8E8E8"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(5),
I4 => rgb(4),
I5 => rgb(6),
O => \dc_bias[3]_i_12__1_n_0\
);
\dc_bias[3]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717FF17FFFFFF"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(5),
I4 => rgb(4),
I5 => rgb(6),
O => \dc_bias[3]_i_13__0_n_0\
);
\dc_bias[3]_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4DDD444D444D2444"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => \dc_bias[3]_i_30__0_n_0\,
I2 => \dc_bias[0]_i_5__0_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_31__0_n_0\,
I5 => \dc_bias[3]_i_19__1_n_0\,
O => \dc_bias[3]_i_14__0_n_0\
);
\dc_bias[3]_i_15__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECFE8FC88FC8ECFE"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[3]_i_19__1_n_0\,
I3 => \dc_bias[3]_i_20__0_n_0\,
I4 => \dc_bias[3]_i_18__0_n_0\,
I5 => \dc_bias[3]_i_17__0_n_0\,
O => \dc_bias[3]_i_15__1_n_0\
);
\dc_bias[3]_i_16__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => p_1_in,
O => \dc_bias[3]_i_16__0_n_0\
);
\dc_bias[3]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D22D4BB42DD2B44B"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_17__0_n_0\
);
\dc_bias[3]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1D8B8B1D8B1D1D8B"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => rgb(0),
I3 => rgb(6),
I4 => rgb(4),
I5 => \encoded[3]_i_2_n_0\,
O => \dc_bias[3]_i_18__0_n_0\
);
\dc_bias[3]_i_19__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_19__1_n_0\
);
\dc_bias[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1DFF1D001DFF1DFF"
)
port map (
I0 => \dc_bias[3]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_4__1_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \dc_bias[3]_i_6__1_n_0\,
I5 => \dc_bias[3]_i_7__1_n_0\,
O => \dc_bias[3]_i_1__1_n_0\
);
\dc_bias[3]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(6),
I3 => \encoded[7]_i_2__1_n_0\,
I4 => rgb(0),
O => \dc_bias[3]_i_20__0_n_0\
);
\dc_bias[3]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"A20808A2208A8A20"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(1),
I4 => rgb(0),
I5 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_21_n_0\
);
\dc_bias[3]_i_22__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBABA22BA22BA22"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_32__0_n_0\,
I2 => \dc_bias[3]_i_33__0_n_0\,
I3 => \dc_bias_reg_n_0_[1]\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(0),
O => \dc_bias[3]_i_22__1_n_0\
);
\dc_bias[3]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFFFFEF"
)
port map (
I0 => \dc_bias[2]_i_10_n_0\,
I1 => \dc_bias[0]_i_3__1_n_0\,
I2 => \encoded[1]_i_2_n_0\,
I3 => \dc_bias[3]_i_3__1_n_0\,
I4 => rgb(2),
I5 => \dc_bias[2]_i_11__1_n_0\,
O => \dc_bias[3]_i_23__0_n_0\
);
\dc_bias[3]_i_24__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE7810081000000"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \encoded[1]_i_2_n_0\,
I3 => \dc_bias[0]_i_3__1_n_0\,
I4 => \dc_bias[2]_i_11__1_n_0\,
I5 => \dc_bias[2]_i_10_n_0\,
O => \dc_bias[3]_i_24__1_n_0\
);
\dc_bias[3]_i_25__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"188EE771E771188E"
)
port map (
I0 => \dc_bias[3]_i_19__1_n_0\,
I1 => \dc_bias[3]_i_31__0_n_0\,
I2 => rgb(0),
I3 => \dc_bias[0]_i_5__0_n_0\,
I4 => \dc_bias[3]_i_30__0_n_0\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_25__1_n_0\
);
\dc_bias[3]_i_26__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9990F999"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_25__1_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__1_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_26__1_n_0\
);
\dc_bias[3]_i_27__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA696955559696AA"
)
port map (
I0 => \dc_bias[3]_i_28__0_n_0\,
I1 => \encoded[7]_i_2__1_n_0\,
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_27__1_n_0\
);
\dc_bias[3]_i_28__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"28882228BEEEBBBE"
)
port map (
I0 => \encoded[4]_i_2_n_0\,
I1 => \encoded[5]_i_2_n_0\,
I2 => \dc_bias[2]_i_12__0_n_0\,
I3 => \dc_bias[3]_i_13__0_n_0\,
I4 => \dc_bias[2]_i_13__0_n_0\,
I5 => \encoded[6]_i_2__1_n_0\,
O => \dc_bias[3]_i_28__0_n_0\
);
\dc_bias[3]_i_29__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \dc_bias[3]_i_29__0_n_0\
);
\dc_bias[3]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"24DB"
)
port map (
I0 => \dc_bias[3]_i_8__1_n_0\,
I1 => \dc_bias[3]_i_9__1_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => p_1_in,
O => \dc_bias[3]_i_2__1_n_0\
);
\dc_bias[3]_i_30__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BD400FFFF002BD4"
)
port map (
I0 => \dc_bias[2]_i_13__0_n_0\,
I1 => \dc_bias[3]_i_13__0_n_0\,
I2 => \dc_bias[2]_i_12__0_n_0\,
I3 => \encoded[1]_i_2_n_0\,
I4 => rgb(2),
I5 => rgb(3),
O => \dc_bias[3]_i_30__0_n_0\
);
\dc_bias[3]_i_31__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55F5F5FFAE8A8A08"
)
port map (
I0 => \dc_bias[3]_i_13__0_n_0\,
I1 => rgb(0),
I2 => \dc_bias[3]_i_12__1_n_0\,
I3 => \dc_bias[3]_i_11__1_n_0\,
I4 => \dc_bias[3]_i_10__1_n_0\,
I5 => \encoded[7]_i_2__1_n_0\,
O => \dc_bias[3]_i_31__0_n_0\
);
\dc_bias[3]_i_32__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01B00071B20001B0"
)
port map (
I0 => rgb(6),
I1 => rgb(7),
I2 => \dc_bias[3]_i_3__1_n_0\,
I3 => \encoded[3]_i_2_n_0\,
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_32__0_n_0\
);
\dc_bias[3]_i_33__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9208000059591049"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
I4 => rgb(7),
I5 => \dc_bias[3]_i_3__1_n_0\,
O => \dc_bias[3]_i_33__0_n_0\
);
\dc_bias[3]_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2B023F03FFBFFFFF"
)
port map (
I0 => \encoded[7]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_10__1_n_0\,
I2 => \dc_bias[3]_i_11__1_n_0\,
I3 => \dc_bias[3]_i_12__1_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_13__0_n_0\,
O => \dc_bias[3]_i_3__1_n_0\
);
\dc_bias[3]_i_4__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"65A6"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => \dc_bias[3]_i_14__0_n_0\,
I3 => \dc_bias[3]_i_15__1_n_0\,
O => \dc_bias[3]_i_4__1_n_0\
);
\dc_bias[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEAAAAABEABAA"
)
port map (
I0 => \dc_bias[3]_i_16__0_n_0\,
I1 => \dc_bias[3]_i_17__0_n_0\,
I2 => \dc_bias[3]_i_18__0_n_0\,
I3 => \dc_bias[3]_i_19__1_n_0\,
I4 => \dc_bias[3]_i_20__0_n_0\,
I5 => \dc_bias[3]_i_21_n_0\,
O => \dc_bias[3]_i_5_n_0\
);
\dc_bias[3]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228822828288228"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => p_1_in,
I2 => \dc_bias[3]_i_22__1_n_0\,
I3 => \dc_bias[3]_i_23__0_n_0\,
I4 => \dc_bias[2]_i_5__1_n_0\,
I5 => \dc_bias[3]_i_24__1_n_0\,
O => \dc_bias[3]_i_6__1_n_0\
);
\dc_bias[3]_i_7__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF4F4F0FBFFFFF4"
)
port map (
I0 => \dc_bias[3]_i_25__1_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_26__1_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_14__0_n_0\,
O => \dc_bias[3]_i_7__1_n_0\
);
\dc_bias[3]_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08A28A20AEFBEFBA"
)
port map (
I0 => \dc_bias[3]_i_27__1_n_0\,
I1 => rgb(3),
I2 => rgb(2),
I3 => \encoded[1]_i_2_n_0\,
I4 => \dc_bias[3]_i_3__1_n_0\,
I5 => \dc_bias[1]_i_8_n_0\,
O => \dc_bias[3]_i_8__1_n_0\
);
\dc_bias[3]_i_9__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000099F099FFFFF"
)
port map (
I0 => \encoded[7]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => \dc_bias_reg_n_0_[1]\,
I5 => \dc_bias[3]_i_28__0_n_0\,
O => \dc_bias[3]_i_9__1_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1__1_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => \^sr\(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[1]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => \^sr\(0)
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1__1_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => \^sr\(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_1__1_n_0\,
Q => p_1_in,
R => \^sr\(0)
);
\encoded[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F6FAF5F6060A050"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => active,
I3 => \dc_bias[2]_i_2__0_n_0\,
I4 => \dc_bias[3]_i_5_n_0\,
I5 => hsync,
O => \encoded[0]_i_1__1_n_0\
);
\encoded[1]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7B33B7CC480084"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[1]_i_2_n_0\,
I5 => hsync,
O => \encoded[1]_i_1__1_n_0\
);
\encoded[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => rgb(1),
O => \encoded[1]_i_2_n_0\
);
\encoded[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"880C44C0BB3F77F3"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[2]_i_2_n_0\,
I5 => hsync,
O => \encoded[2]_i_1__1_n_0\
);
\encoded[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \encoded[2]_i_2_n_0\
);
\encoded[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33B7FF7B0084CC48"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[3]_i_2_n_0\,
I5 => hsync,
O => \encoded[3]_i_1__1_n_0\
);
\encoded[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[3]_i_2_n_0\
);
\encoded[4]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44C0880C77F3BB3F"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[4]_i_2_n_0\,
I5 => hsync,
O => \encoded[4]_i_1__1_n_0\
);
\encoded[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \encoded[4]_i_2_n_0\
);
\encoded[5]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33B7FF7B0084CC48"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[5]_i_2_n_0\,
I5 => hsync,
O => \encoded[5]_i_1__1_n_0\
);
\encoded[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
I3 => rgb(3),
I4 => rgb(5),
I5 => rgb(4),
O => \encoded[5]_i_2_n_0\
);
\encoded[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"880C44C0BB3F77F3"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5_n_0\,
I4 => \encoded[6]_i_2__1_n_0\,
I5 => hsync,
O => \encoded[6]_i_1__1_n_0\
);
\encoded[6]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \encoded[3]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
O => \encoded[6]_i_2__1_n_0\
);
\encoded[7]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF337BB7CC004884"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => \dc_bias[2]_i_2__0_n_0\,
I3 => \encoded[7]_i_2__1_n_0\,
I4 => \dc_bias[3]_i_5_n_0\,
I5 => hsync,
O => \encoded[7]_i_1__1_n_0\
);
\encoded[7]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => rgb(7),
I1 => rgb(6),
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[3]_i_2_n_0\,
O => \encoded[7]_i_2__1_n_0\
);
\encoded[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \dc_bias[3]_i_3__1_n_0\,
I1 => active,
I2 => hsync,
O => \encoded[8]_i_1__1_n_0\
);
\encoded[9]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C5FFC500C500C5FF"
)
port map (
I0 => \dc_bias[2]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_3__1_n_0\,
I2 => \dc_bias[3]_i_5_n_0\,
I3 => active,
I4 => hsync,
I5 => vsync,
O => \encoded[9]_i_1__1_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[0]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[1]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[2]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[3]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[4]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[5]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[6]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[7]_i_1__1_n_0\,
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1__1_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1__1_n_0\,
Q => Q(1),
R => '0'
);
\shift_blue[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_blue[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_blue[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_blue[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_blue[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_blue[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_blue[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_blue[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_blue(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder_0 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
shift_green : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder_0 : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder_0;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder_0 is
signal \dc_bias[0]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6__1_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_1__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_28_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_29_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_30_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_31_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_32_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_33_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_34_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9__0_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded[0]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[1]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[2]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[3]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[4]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[5]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[6]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[6]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2_n_0\ : STD_LOGIC;
signal \encoded[7]_i_3__0_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[8]_i_2_n_0\ : STD_LOGIC;
signal \encoded[8]_i_3_n_0\ : STD_LOGIC;
signal \encoded[8]_i_4_n_0\ : STD_LOGIC;
signal \encoded[8]_i_5_n_0\ : STD_LOGIC;
signal \encoded[8]_i_6_n_0\ : STD_LOGIC;
signal \encoded[8]_i_7_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_2__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \dc_bias[0]_i_3__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \dc_bias[0]_i_5__1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \dc_bias[0]_i_6\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \dc_bias[0]_i_7\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \dc_bias[1]_i_3__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \dc_bias[1]_i_8__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \dc_bias[2]_i_10__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \dc_bias[2]_i_11__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \dc_bias[2]_i_8__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \dc_bias[2]_i_9\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \dc_bias[3]_i_11__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \dc_bias[3]_i_12__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \dc_bias[3]_i_13__1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \dc_bias[3]_i_14__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \dc_bias[3]_i_15__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \dc_bias[3]_i_18__1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \dc_bias[3]_i_22__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \dc_bias[3]_i_23__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \dc_bias[3]_i_24__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \dc_bias[3]_i_2__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \dc_bias[3]_i_33\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \dc_bias[3]_i_7__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \dc_bias[3]_i_8__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \encoded[0]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \encoded[1]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \encoded[2]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \encoded[4]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \encoded[5]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \encoded[6]_i_2__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \encoded[7]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \encoded[7]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \encoded[7]_i_3__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \encoded[8]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \encoded[8]_i_4\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \encoded[8]_i_7\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \shift_green[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \shift_green[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \shift_green[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \shift_green[3]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \shift_green[4]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \shift_green[5]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \shift_green[6]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \shift_green[7]_i_1\ : label is "soft_lutpair34";
begin
\dc_bias[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \dc_bias[3]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[0]_i_3__0_n_0\,
I5 => \dc_bias[0]_i_4__0_n_0\,
O => \dc_bias[0]_i_1__0_n_0\
);
\dc_bias[0]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_6_n_0\,
I3 => \dc_bias[0]_i_7_n_0\,
I4 => rgb(6),
O => \dc_bias[0]_i_2__0_n_0\
);
\dc_bias[0]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[6]_i_2__0_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3__0_n_0\
);
\dc_bias[0]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \encoded[8]_i_2_n_0\,
O => \dc_bias[0]_i_4__0_n_0\
);
\dc_bias[0]_i_5__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[0]_i_5__1_n_0\
);
\dc_bias[0]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => rgb(7),
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \dc_bias[0]_i_6_n_0\
);
\dc_bias[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[0]_i_7_n_0\
);
\dc_bias[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \dc_bias[1]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[1]_i_3__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[1]_i_4__0_n_0\,
O => \dc_bias[1]_i_1_n_0\
);
\dc_bias[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"960096FF96FF9600"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \dc_bias[1]_i_6__1_n_0\,
I2 => \dc_bias[1]_i_7__0_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[1]_i_8__0_n_0\,
I5 => \dc_bias[2]_i_10__1_n_0\,
O => \dc_bias[1]_i_2__0_n_0\
);
\dc_bias[1]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5965"
)
port map (
I0 => \dc_bias[2]_i_10__1_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => \dc_bias[0]_i_2__0_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[1]_i_3__0_n_0\
);
\dc_bias[1]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"56955965A96AA69A"
)
port map (
I0 => \dc_bias[3]_i_11__0_n_0\,
I1 => \dc_bias[0]_i_3__0_n_0\,
I2 => rgb(2),
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[2]_i_11__0_n_0\,
I5 => \dc_bias[3]_i_12__0_n_0\,
O => \dc_bias[1]_i_4__0_n_0\
);
\dc_bias[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"066090096FF6F99F"
)
port map (
I0 => rgb(6),
I1 => \dc_bias[0]_i_7_n_0\,
I2 => \dc_bias[1]_i_9_n_0\,
I3 => \dc_bias[0]_i_6_n_0\,
I4 => \encoded[8]_i_2_n_0\,
I5 => \dc_bias[0]_i_5__1_n_0\,
O => \dc_bias[1]_i_5_n_0\
);
\dc_bias[1]_i_6__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"556969AAAA969655"
)
port map (
I0 => \dc_bias[3]_i_27__0_n_0\,
I1 => \dc_bias[0]_i_6_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[1]_i_6__1_n_0\
);
\dc_bias[1]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9C3939399C9C9C39"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[2]_i_11__0_n_0\,
I2 => rgb(3),
I3 => \dc_bias[3]_i_30_n_0\,
I4 => \encoded[8]_i_6_n_0\,
I5 => \dc_bias[3]_i_31_n_0\,
O => \dc_bias[1]_i_7__0_n_0\
);
\dc_bias[1]_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[1]_i_8__0_n_0\
);
\dc_bias[1]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[1]_i_9_n_0\
);
\dc_bias[2]_i_10__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_10__0_n_0\,
O => \dc_bias[2]_i_10__1_n_0\
);
\dc_bias[2]_i_11__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => rgb(1),
O => \dc_bias[2]_i_11__0_n_0\
);
\dc_bias[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"B888B8BBB8BBB888"
)
port map (
I0 => \dc_bias[2]_i_2__1_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[2]_i_3__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[2]_i_4_n_0\,
I5 => \dc_bias[2]_i_5__0_n_0\,
O => \dc_bias[2]_i_1__0_n_0\
);
\dc_bias[2]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96FF9600960096FF"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_6__0_n_0\,
I2 => \dc_bias[2]_i_7_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => \dc_bias[2]_i_8__0_n_0\,
I5 => \dc_bias[2]_i_9_n_0\,
O => \dc_bias[2]_i_2__1_n_0\
);
\dc_bias[2]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"04DFFB20FB2004DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias[2]_i_10__1_n_0\,
I4 => \dc_bias[3]_i_23__1_n_0\,
I5 => \dc_bias[2]_i_8__0_n_0\,
O => \dc_bias[2]_i_3__0_n_0\
);
\dc_bias[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"711818188EE7E7E7"
)
port map (
I0 => \dc_bias[3]_i_16_n_0\,
I1 => \dc_bias[3]_i_17_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[2]_i_4_n_0\
);
\dc_bias[2]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB2BB2BBBBBDDBBB"
)
port map (
I0 => \dc_bias[3]_i_11__0_n_0\,
I1 => \dc_bias[3]_i_12__0_n_0\,
I2 => \dc_bias[2]_i_11__0_n_0\,
I3 => \encoded[8]_i_2_n_0\,
I4 => rgb(2),
I5 => \dc_bias[0]_i_3__0_n_0\,
O => \dc_bias[2]_i_5__0_n_0\
);
\dc_bias[2]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"01151501577F7F57"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_6_n_0\,
I4 => \encoded[8]_i_2_n_0\,
I5 => \dc_bias[3]_i_27__0_n_0\,
O => \dc_bias[2]_i_6__0_n_0\
);
\dc_bias[2]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"802AA802EABFFEAB"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => rgb(3),
I3 => \dc_bias[2]_i_11__0_n_0\,
I4 => rgb(2),
I5 => \dc_bias[1]_i_6__1_n_0\,
O => \dc_bias[2]_i_7_n_0\
);
\dc_bias[2]_i_8__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_9__0_n_0\,
O => \dc_bias[2]_i_8__0_n_0\
);
\dc_bias[2]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"2B22"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[2]_i_9_n_0\
);
\dc_bias[3]_i_10__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"188EE771E771188E"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => \dc_bias[3]_i_29_n_0\,
I2 => rgb(0),
I3 => \dc_bias[3]_i_28_n_0\,
I4 => \dc_bias[3]_i_27__0_n_0\,
I5 => \dc_bias[1]_i_7__0_n_0\,
O => \dc_bias[3]_i_10__0_n_0\
);
\dc_bias[3]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => \dc_bias[3]_i_16_n_0\,
I1 => \dc_bias[3]_i_17_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
O => \dc_bias[3]_i_11__0_n_0\
);
\dc_bias[3]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"82EBEB82"
)
port map (
I0 => rgb(7),
I1 => \dc_bias_reg_n_0_[0]\,
I2 => rgb(0),
I3 => rgb(5),
I4 => \encoded[6]_i_2__0_n_0\,
O => \dc_bias[3]_i_12__0_n_0\
);
\dc_bias[3]_i_13__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96669996"
)
port map (
I0 => rgb(1),
I1 => rgb(0),
I2 => \dc_bias[3]_i_30_n_0\,
I3 => \encoded[8]_i_6_n_0\,
I4 => \dc_bias[3]_i_31_n_0\,
O => \dc_bias[3]_i_13__1_n_0\
);
\dc_bias[3]_i_14__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_14__1_n_0\
);
\dc_bias[3]_i_15__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[3]_i_15__0_n_0\
);
\dc_bias[3]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"B42D"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2__0_n_0\,
I3 => rgb(5),
O => \dc_bias[3]_i_16_n_0\
);
\dc_bias[3]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"1771711771171771"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(7),
I2 => \encoded[6]_i_2__0_n_0\,
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_17_n_0\
);
\dc_bias[3]_i_18__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"14414114"
)
port map (
I0 => \dc_bias[0]_i_5__1_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_6_n_0\,
I3 => \dc_bias[0]_i_7_n_0\,
I4 => rgb(6),
O => \dc_bias[3]_i_18__1_n_0\
);
\dc_bias[3]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"82BE14D714D782BE"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => rgb(7),
I2 => \encoded[7]_i_2_n_0\,
I3 => rgb(0),
I4 => \dc_bias[0]_i_7_n_0\,
I5 => rgb(6),
O => \dc_bias[3]_i_19__0_n_0\
);
\dc_bias[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFAAEB"
)
port map (
I0 => \dc_bias[3]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_3__0_n_0\,
I2 => \dc_bias[3]_i_4__0_n_0\,
I3 => \dc_bias[3]_i_5__1_n_0\,
I4 => \dc_bias[3]_i_6__0_n_0\,
I5 => \dc_bias[3]_i_7__0_n_0\,
O => \dc_bias[3]_i_1__0_n_0\
);
\dc_bias[3]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"42BDBD42BD4242BD"
)
port map (
I0 => rgb(6),
I1 => \encoded[8]_i_2_n_0\,
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[6]_i_2__0_n_0\,
I5 => \dc_bias[1]_i_7__0_n_0\,
O => \dc_bias[3]_i_20_n_0\
);
\dc_bias[3]_i_21__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAEEFFBEFFBBAAE"
)
port map (
I0 => \dc_bias[1]_i_7__0_n_0\,
I1 => rgb(6),
I2 => \encoded[8]_i_2_n_0\,
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[6]_i_2__0_n_0\,
O => \dc_bias[3]_i_21__1_n_0\
);
\dc_bias[3]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"99F99099"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_10__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
I3 => \dc_bias[0]_i_2__0_n_0\,
I4 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[3]_i_22__0_n_0\
);
\dc_bias[3]_i_23__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_23__1_n_0\
);
\dc_bias[3]_i_24__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2__0_n_0\,
I2 => \encoded[8]_i_2_n_0\,
O => \dc_bias[3]_i_24__0_n_0\
);
\dc_bias[3]_i_25__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002BD400FFD42BFF"
)
port map (
I0 => \dc_bias[1]_i_5_n_0\,
I1 => \dc_bias[1]_i_7__0_n_0\,
I2 => \dc_bias[1]_i_6__1_n_0\,
I3 => \dc_bias[2]_i_6__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => p_1_in,
O => \dc_bias[3]_i_25__0_n_0\
);
\dc_bias[3]_i_26__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFD4DDD4DD0000"
)
port map (
I0 => \dc_bias[3]_i_10__0_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_2__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_9__0_n_0\,
O => \dc_bias[3]_i_26__0_n_0\
);
\dc_bias[3]_i_27__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EBBBEEEB82228882"
)
port map (
I0 => \dc_bias[0]_i_7_n_0\,
I1 => \dc_bias[3]_i_32_n_0\,
I2 => \dc_bias[3]_i_30_n_0\,
I3 => \encoded[8]_i_6_n_0\,
I4 => \dc_bias[3]_i_31_n_0\,
I5 => \encoded[7]_i_2_n_0\,
O => \dc_bias[3]_i_27__0_n_0\
);
\dc_bias[3]_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"8E71718E718E8E71"
)
port map (
I0 => \dc_bias[3]_i_30_n_0\,
I1 => \encoded[8]_i_6_n_0\,
I2 => \dc_bias[3]_i_31_n_0\,
I3 => rgb(4),
I4 => \encoded[6]_i_2__0_n_0\,
I5 => rgb(6),
O => \dc_bias[3]_i_28_n_0\
);
\dc_bias[3]_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAFB5D45BAFB4504"
)
port map (
I0 => \encoded[8]_i_6_n_0\,
I1 => \encoded[8]_i_5_n_0\,
I2 => \encoded[8]_i_4_n_0\,
I3 => \encoded[8]_i_3_n_0\,
I4 => \dc_bias[0]_i_6_n_0\,
I5 => rgb(0),
O => \dc_bias[3]_i_29_n_0\
);
\dc_bias[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAAE"
)
port map (
I0 => \dc_bias[3]_i_8__0_n_0\,
I1 => \dc_bias[3]_i_9__0_n_0\,
I2 => \dc_bias[3]_i_10__0_n_0\,
I3 => \dc_bias[0]_i_2__0_n_0\,
O => \dc_bias[3]_i_2__0_n_0\
);
\dc_bias[3]_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F6606000FFF6"
)
port map (
I0 => \dc_bias[3]_i_33_n_0\,
I1 => rgb(6),
I2 => rgb(7),
I3 => rgb(0),
I4 => \encoded[8]_i_5_n_0\,
I5 => \dc_bias[3]_i_34_n_0\,
O => \dc_bias[3]_i_30_n_0\
);
\dc_bias[3]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"4008000029610000"
)
port map (
I0 => rgb(7),
I1 => \encoded[6]_i_2__0_n_0\,
I2 => \encoded[8]_i_7_n_0\,
I3 => \dc_bias[3]_i_34_n_0\,
I4 => rgb(0),
I5 => \encoded[8]_i_5_n_0\,
O => \dc_bias[3]_i_31_n_0\
);
\dc_bias[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => rgb(5),
I1 => rgb(4),
I2 => rgb(2),
I3 => rgb(1),
I4 => rgb(0),
I5 => rgb(3),
O => \dc_bias[3]_i_32_n_0\
);
\dc_bias[3]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
O => \dc_bias[3]_i_33_n_0\
);
\dc_bias[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[3]_i_34_n_0\
);
\dc_bias[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A088A8A8A8AAE8A"
)
port map (
I0 => \dc_bias[2]_i_4_n_0\,
I1 => \dc_bias[3]_i_11__0_n_0\,
I2 => \dc_bias[3]_i_12__0_n_0\,
I3 => \dc_bias[3]_i_13__1_n_0\,
I4 => \dc_bias[3]_i_14__1_n_0\,
I5 => \dc_bias[0]_i_3__0_n_0\,
O => \dc_bias[3]_i_3__0_n_0\
);
\dc_bias[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"56555555AA6A6A56"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_15__0_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias[3]_i_16_n_0\,
I4 => \dc_bias[3]_i_17_n_0\,
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[3]_i_4__0_n_0\
);
\dc_bias[3]_i_5__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6655555"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_18__1_n_0\,
I2 => \dc_bias[3]_i_19__0_n_0\,
I3 => \dc_bias[3]_i_20_n_0\,
I4 => \dc_bias[3]_i_21__1_n_0\,
O => \dc_bias[3]_i_5__1_n_0\
);
\dc_bias[3]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C40404040CCC0"
)
port map (
I0 => \dc_bias[3]_i_22__0_n_0\,
I1 => \dc_bias[3]_i_5__1_n_0\,
I2 => \dc_bias[3]_i_23__1_n_0\,
I3 => \dc_bias[3]_i_24__0_n_0\,
I4 => \dc_bias[3]_i_9__0_n_0\,
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[3]_i_6__0_n_0\
);
\dc_bias[3]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B08080B0"
)
port map (
I0 => \dc_bias[3]_i_25__0_n_0\,
I1 => \encoded[8]_i_2_n_0\,
I2 => \dc_bias[3]_i_2__0_n_0\,
I3 => \dc_bias[3]_i_26__0_n_0\,
I4 => \dc_bias[3]_i_5__1_n_0\,
O => \dc_bias[3]_i_7__0_n_0\
);
\dc_bias[3]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias_reg_n_0_[2]\,
I2 => p_1_in,
I3 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_8__0_n_0\
);
\dc_bias[3]_i_9__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D444DDD4DDD4BDDD"
)
port map (
I0 => \dc_bias[1]_i_7__0_n_0\,
I1 => \dc_bias[3]_i_27__0_n_0\,
I2 => \dc_bias[3]_i_28_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_29_n_0\,
I5 => \dc_bias[0]_i_5__1_n_0\,
O => \dc_bias[3]_i_9__0_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => SR(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[1]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => SR(0)
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1__0_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => SR(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_1__0_n_0\,
Q => p_1_in,
R => SR(0)
);
\encoded[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => \encoded[9]_i_2__0_n_0\,
O => \encoded[0]_i_1__0_n_0\
);
\encoded[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2882"
)
port map (
I0 => active,
I1 => rgb(1),
I2 => rgb(0),
I3 => \encoded[7]_i_3__0_n_0\,
O => \encoded[1]_i_1__0_n_0\
);
\encoded[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"D77D7DD7"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
I4 => \encoded[9]_i_2__0_n_0\,
O => \encoded[2]_i_1__0_n_0\
);
\encoded[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2882822882282882"
)
port map (
I0 => active,
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
I5 => \encoded[7]_i_3__0_n_0\,
O => \encoded[3]_i_1__0_n_0\
);
\encoded[4]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"D77D"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(4),
I3 => \encoded[9]_i_2__0_n_0\,
O => \encoded[4]_i_1__0_n_0\
);
\encoded[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"28828228"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(4),
I3 => rgb(5),
I4 => \encoded[7]_i_3__0_n_0\,
O => \encoded[5]_i_1__0_n_0\
);
\encoded[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D77D7DD77DD7D77D"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2__0_n_0\,
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[9]_i_2__0_n_0\,
O => \encoded[6]_i_1__0_n_0\
);
\encoded[6]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[6]_i_2__0_n_0\
);
\encoded[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2882"
)
port map (
I0 => active,
I1 => \encoded[7]_i_2_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_3__0_n_0\,
O => \encoded[7]_i_1__0_n_0\
);
\encoded[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => rgb(6),
I3 => \encoded[6]_i_2__0_n_0\,
O => \encoded[7]_i_2_n_0\
);
\encoded[7]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \dc_bias[3]_i_2__0_n_0\,
I1 => \dc_bias[3]_i_5__1_n_0\,
I2 => \encoded[8]_i_2_n_0\,
O => \encoded[7]_i_3__0_n_0\
);
\encoded[8]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => active,
O => \encoded[8]_i_1__0_n_0\
);
\encoded[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00200000F2FF20F2"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[0]_i_6_n_0\,
I2 => \encoded[8]_i_3_n_0\,
I3 => \encoded[8]_i_4_n_0\,
I4 => \encoded[8]_i_5_n_0\,
I5 => \encoded[8]_i_6_n_0\,
O => \encoded[8]_i_2_n_0\
);
\encoded[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF6969FF69FFFF69"
)
port map (
I0 => rgb(1),
I1 => rgb(2),
I2 => rgb(3),
I3 => rgb(0),
I4 => rgb(7),
I5 => \encoded[8]_i_7_n_0\,
O => \encoded[8]_i_3_n_0\
);
\encoded[8]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"E88E8EE8"
)
port map (
I0 => rgb(0),
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
O => \encoded[8]_i_4_n_0\
);
\encoded[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E8E8E817E8171717"
)
port map (
I0 => rgb(2),
I1 => rgb(3),
I2 => rgb(1),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \encoded[8]_i_5_n_0\
);
\encoded[8]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"E8E8E800E8000000"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
I3 => rgb(2),
I4 => rgb(3),
I5 => rgb(1),
O => \encoded[8]_i_6_n_0\
);
\encoded[8]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \encoded[8]_i_7_n_0\
);
\encoded[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => active,
I1 => \encoded[9]_i_2__0_n_0\,
O => \encoded[9]_i_1_n_0\
);
\encoded[9]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \encoded[8]_i_2_n_0\,
I1 => \dc_bias[3]_i_2__0_n_0\,
I2 => \dc_bias[3]_i_5__1_n_0\,
O => \encoded[9]_i_2__0_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[0]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[1]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[2]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[3]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[4]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[5]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[6]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[7]_i_1__0_n_0\,
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1__0_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1_n_0\,
Q => Q(1),
R => '0'
);
\shift_green[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_green[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_green[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_green[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_green[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_green[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_green[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_green[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => shift_green(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_TMDS_encoder_1 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 7 downto 0 );
active : in STD_LOGIC;
data1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
\shift_clock_reg[5]\ : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_TMDS_encoder_1 : entity is "TMDS_encoder";
end system_zybo_hdmi_0_0_TMDS_encoder_1;
architecture STRUCTURE of system_zybo_hdmi_0_0_TMDS_encoder_1 is
signal \dc_bias[0]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[0]_i_6__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[1]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_10__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_11_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_12_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_13_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_14_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_15_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_16_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_17_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_18_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_19_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_20_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_21_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_22_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_4__0_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_5_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_7__1_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[2]_i_9__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_10_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_11_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_12_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_13_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_14_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_15_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_16__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_17__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_18_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_19_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_20__1_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_21__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_22_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_23_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_24_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_25_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_26_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_27_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_2_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_3_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_4_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_5__0_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_6_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_7_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_8_n_0\ : STD_LOGIC;
signal \dc_bias[3]_i_9_n_0\ : STD_LOGIC;
signal \dc_bias_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[0]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[1]\ : STD_LOGIC;
signal \dc_bias_reg_n_0_[2]\ : STD_LOGIC;
signal encoded : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \encoded[6]_i_2_n_0\ : STD_LOGIC;
signal \encoded[7]_i_2__0_n_0\ : STD_LOGIC;
signal \encoded[7]_i_3_n_0\ : STD_LOGIC;
signal \encoded[8]_i_1_n_0\ : STD_LOGIC;
signal \encoded[9]_i_1__0_n_0\ : STD_LOGIC;
signal \encoded[9]_i_2_n_0\ : STD_LOGIC;
signal \encoded_reg_n_0_[0]\ : STD_LOGIC;
signal \encoded_reg_n_0_[1]\ : STD_LOGIC;
signal \encoded_reg_n_0_[2]\ : STD_LOGIC;
signal \encoded_reg_n_0_[3]\ : STD_LOGIC;
signal \encoded_reg_n_0_[4]\ : STD_LOGIC;
signal \encoded_reg_n_0_[5]\ : STD_LOGIC;
signal \encoded_reg_n_0_[6]\ : STD_LOGIC;
signal \encoded_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \dc_bias[0]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \dc_bias[0]_i_4\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \dc_bias[0]_i_6__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \dc_bias[1]_i_7\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \dc_bias[2]_i_10__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \dc_bias[2]_i_12\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \dc_bias[2]_i_13\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \dc_bias[2]_i_15\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \dc_bias[2]_i_16\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \dc_bias[2]_i_17\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \dc_bias[2]_i_18\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \dc_bias[2]_i_19\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \dc_bias[2]_i_20\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \dc_bias[2]_i_22\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \dc_bias[2]_i_8\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \dc_bias[3]_i_10\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \dc_bias[3]_i_14\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \dc_bias[3]_i_16__1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \dc_bias[3]_i_20__1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \dc_bias[3]_i_25\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \dc_bias[3]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \encoded[0]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \encoded[1]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \encoded[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \encoded[4]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \encoded[6]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \encoded[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \encoded[7]_i_2__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \encoded[7]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \encoded[8]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \encoded[9]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \encoded[9]_i_2\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \shift_red[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \shift_red[1]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \shift_red[2]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \shift_red[3]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \shift_red[4]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \shift_red[5]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \shift_red[6]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \shift_red[7]_i_1\ : label is "soft_lutpair55";
begin
\dc_bias[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6F60606F606F6F60"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2_n_0\,
I2 => \dc_bias[3]_i_6_n_0\,
I3 => \dc_bias[2]_i_4__0_n_0\,
I4 => \dc_bias[0]_i_3_n_0\,
I5 => \dc_bias[0]_i_4_n_0\,
O => \dc_bias[0]_i_1_n_0\
);
\dc_bias[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias[0]_i_6__0_n_0\,
O => \dc_bias[0]_i_2_n_0\
);
\dc_bias[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(5),
I2 => rgb(0),
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(7),
O => \dc_bias[0]_i_3_n_0\
);
\dc_bias[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[0]_i_4_n_0\
);
\dc_bias[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699669969669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
I4 => rgb(7),
I5 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[0]_i_5_n_0\
);
\dc_bias[0]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2_n_0\,
I3 => rgb(6),
O => \dc_bias[0]_i_6__0_n_0\
);
\dc_bias[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC3CC3CC55555555"
)
port map (
I0 => \dc_bias[1]_i_4_n_0\,
I1 => \dc_bias[1]_i_5__0_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
I3 => \dc_bias[0]_i_2_n_0\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => \dc_bias[2]_i_4__0_n_0\,
O => \dc_bias[1]_i_2_n_0\
);
\dc_bias[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00F0FF099999999"
)
port map (
I0 => \dc_bias[3]_i_16__1_n_0\,
I1 => \dc_bias[1]_i_5__0_n_0\,
I2 => \dc_bias[1]_i_6_n_0\,
I3 => \dc_bias[1]_i_7_n_0\,
I4 => \dc_bias[2]_i_12_n_0\,
I5 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[1]_i_3_n_0\
);
\dc_bias[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"95A9A96A569595A9"
)
port map (
I0 => \dc_bias[2]_i_18_n_0\,
I1 => \dc_bias[2]_i_16_n_0\,
I2 => \dc_bias[2]_i_17_n_0\,
I3 => \dc_bias[2]_i_19_n_0\,
I4 => \dc_bias[2]_i_20_n_0\,
I5 => rgb(7),
O => \dc_bias[1]_i_4_n_0\
);
\dc_bias[1]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9996699969996669"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_26_n_0\,
I2 => \dc_bias[0]_i_6__0_n_0\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_25_n_0\,
O => \dc_bias[1]_i_5__0_n_0\
);
\dc_bias[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"5CC5355335535CC5"
)
port map (
I0 => \dc_bias[0]_i_6__0_n_0\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(3),
I5 => rgb(1),
O => \dc_bias[1]_i_6_n_0\
);
\dc_bias[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"A665599A"
)
port map (
I0 => \dc_bias[2]_i_13_n_0\,
I1 => \dc_bias[0]_i_5_n_0\,
I2 => \dc_bias_reg_n_0_[0]\,
I3 => rgb(0),
I4 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[1]_i_7_n_0\
);
\dc_bias[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B888B8BBB8BBB888"
)
port map (
I0 => \dc_bias[2]_i_2_n_0\,
I1 => \dc_bias[3]_i_6_n_0\,
I2 => \dc_bias[2]_i_3_n_0\,
I3 => \dc_bias[2]_i_4__0_n_0\,
I4 => \dc_bias[2]_i_5_n_0\,
I5 => \dc_bias[2]_i_6_n_0\,
O => \dc_bias[2]_i_1_n_0\
);
\dc_bias[2]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"90060690"
)
port map (
I0 => \dc_bias[0]_i_5_n_0\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[2]_i_10__0_n_0\
);
\dc_bias[2]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"3AA3ACCAACCA3AA3"
)
port map (
I0 => rgb(0),
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_2__0_n_0\,
I4 => \dc_bias[2]_i_22_n_0\,
I5 => rgb(6),
O => \dc_bias[2]_i_11_n_0\
);
\dc_bias[2]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"2DD2B44B"
)
port map (
I0 => rgb(2),
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(3),
O => \dc_bias[2]_i_12_n_0\
);
\dc_bias[2]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"A59669A5"
)
port map (
I0 => rgb(4),
I1 => rgb(5),
I2 => \encoded[6]_i_2_n_0\,
I3 => \dc_bias[3]_i_4_n_0\,
I4 => rgb(6),
O => \dc_bias[2]_i_13_n_0\
);
\dc_bias[2]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"1771711771171771"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(7),
I2 => rgb(6),
I3 => rgb(5),
I4 => rgb(4),
I5 => \encoded[6]_i_2_n_0\,
O => \dc_bias[2]_i_14_n_0\
);
\dc_bias[2]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"4BD2"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => rgb(4),
I2 => \encoded[6]_i_2_n_0\,
I3 => rgb(5),
O => \dc_bias[2]_i_15_n_0\
);
\dc_bias[2]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb(2),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[2]_i_16_n_0\
);
\dc_bias[2]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(1),
I1 => rgb(0),
I2 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[2]_i_17_n_0\
);
\dc_bias[2]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \dc_bias[2]_i_15_n_0\,
I1 => \dc_bias[2]_i_14_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
O => \dc_bias[2]_i_18_n_0\
);
\dc_bias[2]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(5),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[2]_i_19_n_0\
);
\dc_bias[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F60606F"
)
port map (
I0 => \dc_bias[2]_i_7__1_n_0\,
I1 => \dc_bias[3]_i_9_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
I3 => \dc_bias[2]_i_8_n_0\,
I4 => \dc_bias[2]_i_9__1_n_0\,
O => \dc_bias[2]_i_2_n_0\
);
\dc_bias[2]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb(0),
I1 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_20_n_0\
);
\dc_bias[2]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(6),
I1 => \dc_bias[2]_i_22_n_0\,
I2 => \encoded[7]_i_2__0_n_0\,
I3 => rgb(7),
I4 => rgb(0),
O => \dc_bias[2]_i_21_n_0\
);
\dc_bias[2]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => rgb(4),
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
O => \dc_bias[2]_i_22_n_0\
);
\dc_bias[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"56569556566A5656"
)
port map (
I0 => \dc_bias[2]_i_8_n_0\,
I1 => \dc_bias_reg_n_0_[1]\,
I2 => \dc_bias[3]_i_17__1_n_0\,
I3 => \dc_bias[3]_i_4_n_0\,
I4 => \dc_bias[0]_i_2_n_0\,
I5 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_3_n_0\
);
\dc_bias[2]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5556566A"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[2]_i_10__0_n_0\,
I2 => \dc_bias[2]_i_11_n_0\,
I3 => \dc_bias[2]_i_12_n_0\,
I4 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[2]_i_4__0_n_0\
);
\dc_bias[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"D44242422BBDBDBD"
)
port map (
I0 => \dc_bias[2]_i_14_n_0\,
I1 => \dc_bias[2]_i_15_n_0\,
I2 => \dc_bias_reg_n_0_[1]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[2]\,
O => \dc_bias[2]_i_5_n_0\
);
\dc_bias[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F1F170EFF7F7F1"
)
port map (
I0 => \dc_bias[2]_i_16_n_0\,
I1 => \dc_bias[2]_i_17_n_0\,
I2 => \dc_bias[2]_i_18_n_0\,
I3 => \dc_bias[2]_i_19_n_0\,
I4 => \dc_bias[2]_i_20_n_0\,
I5 => rgb(7),
O => \dc_bias[2]_i_6_n_0\
);
\dc_bias[2]_i_7__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5565656666A6A6AA"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_13_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => rgb(0),
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[2]_i_7__1_n_0\
);
\dc_bias[2]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[3]_i_15_n_0\,
O => \dc_bias[2]_i_8_n_0\
);
\dc_bias[2]_i_9__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"41141414417D7D14"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => \dc_bias[3]_i_26_n_0\,
I2 => \dc_bias[2]_i_11_n_0\,
I3 => \dc_bias[2]_i_21_n_0\,
I4 => \dc_bias[3]_i_25_n_0\,
I5 => \dc_bias_reg_n_0_[0]\,
O => \dc_bias[2]_i_9__1_n_0\
);
\dc_bias[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"15017F57"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => rgb(0),
I2 => \dc_bias_reg_n_0_[0]\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_10_n_0\
);
\dc_bias[3]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717FF17FFFFFF"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_11_n_0\
);
\dc_bias[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(6),
I1 => rgb(5),
I2 => rgb(4),
O => \dc_bias[3]_i_12_n_0\
);
\dc_bias[3]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"171717E817E8E8E8"
)
port map (
I0 => rgb(1),
I1 => rgb(3),
I2 => rgb(2),
I3 => rgb(6),
I4 => rgb(5),
I5 => rgb(4),
O => \dc_bias[3]_i_13_n_0\
);
\dc_bias[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(3),
I1 => rgb(2),
I2 => rgb(1),
O => \dc_bias[3]_i_14_n_0\
);
\dc_bias[3]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEE78EEE8EEE888E"
)
port map (
I0 => \dc_bias[2]_i_13_n_0\,
I1 => \dc_bias[2]_i_12_n_0\,
I2 => \dc_bias[0]_i_6__0_n_0\,
I3 => \dc_bias[0]_i_5_n_0\,
I4 => rgb(0),
I5 => \dc_bias[3]_i_25_n_0\,
O => \dc_bias[3]_i_15_n_0\
);
\dc_bias[3]_i_16__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EBBEBEEB"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => rgb(3),
I4 => rgb(1),
O => \dc_bias[3]_i_16__1_n_0\
);
\dc_bias[3]_i_17__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"90F6F66F6F090990"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[0]_i_5_n_0\,
I4 => \dc_bias[0]_i_6__0_n_0\,
I5 => \dc_bias[3]_i_26_n_0\,
O => \dc_bias[3]_i_17__1_n_0\
);
\dc_bias[3]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFF799E799EFFF7"
)
port map (
I0 => \dc_bias[3]_i_25_n_0\,
I1 => rgb(0),
I2 => \dc_bias[0]_i_5_n_0\,
I3 => \dc_bias[0]_i_6__0_n_0\,
I4 => \dc_bias[2]_i_12_n_0\,
I5 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_18_n_0\
);
\dc_bias[3]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"E00E0EE00EE0E00E"
)
port map (
I0 => \dc_bias[3]_i_16__1_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => \dc_bias[2]_i_10__0_n_0\,
I3 => \dc_bias[2]_i_11_n_0\,
I4 => \dc_bias[3]_i_26_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_19_n_0\
);
\dc_bias[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8FFB8FFB800"
)
port map (
I0 => \dc_bias[3]_i_3_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => \dc_bias[3]_i_5__0_n_0\,
I3 => \dc_bias[3]_i_6_n_0\,
I4 => \dc_bias[3]_i_7_n_0\,
I5 => \dc_bias[3]_i_8_n_0\,
O => \dc_bias[3]_i_2_n_0\
);
\dc_bias[3]_i_20__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \dc_bias_reg_n_0_[0]\,
I1 => \dc_bias[0]_i_2_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
O => \dc_bias[3]_i_20__1_n_0\
);
\dc_bias[3]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A96A6A5600000000"
)
port map (
I0 => \dc_bias[3]_i_26_n_0\,
I1 => \dc_bias[0]_i_6__0_n_0\,
I2 => \dc_bias[0]_i_5_n_0\,
I3 => rgb(0),
I4 => \dc_bias[3]_i_25_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_21__0_n_0\
);
\dc_bias[3]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAEAE8AAE8AAE8A"
)
port map (
I0 => \dc_bias_reg_n_0_[2]\,
I1 => \dc_bias[2]_i_15_n_0\,
I2 => \dc_bias[2]_i_14_n_0\,
I3 => \dc_bias_reg_n_0_[1]\,
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(0),
O => \dc_bias[3]_i_22_n_0\
);
\dc_bias[3]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"02BF002B002B0002"
)
port map (
I0 => rgb(7),
I1 => \dc_bias[2]_i_20_n_0\,
I2 => \dc_bias[2]_i_19_n_0\,
I3 => \dc_bias[2]_i_18_n_0\,
I4 => \dc_bias[2]_i_17_n_0\,
I5 => \dc_bias[2]_i_16_n_0\,
O => \dc_bias[3]_i_23_n_0\
);
\dc_bias[3]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF5775D55D"
)
port map (
I0 => \dc_bias[2]_i_18_n_0\,
I1 => \dc_bias[3]_i_4_n_0\,
I2 => rgb(0),
I3 => rgb(1),
I4 => rgb(2),
I5 => \dc_bias[3]_i_27_n_0\,
O => \dc_bias[3]_i_24_n_0\
);
\dc_bias[3]_i_25\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
O => \dc_bias[3]_i_25_n_0\
);
\dc_bias[3]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"963CC39669C33C69"
)
port map (
I0 => rgb(3),
I1 => rgb(1),
I2 => rgb(0),
I3 => \dc_bias[3]_i_4_n_0\,
I4 => rgb(2),
I5 => \dc_bias[2]_i_13_n_0\,
O => \dc_bias[3]_i_26_n_0\
);
\dc_bias[3]_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBEBEFF"
)
port map (
I0 => \dc_bias[0]_i_4_n_0\,
I1 => \encoded[6]_i_2_n_0\,
I2 => rgb(5),
I3 => rgb(0),
I4 => \dc_bias_reg_n_0_[0]\,
I5 => rgb(7),
O => \dc_bias[3]_i_27_n_0\
);
\dc_bias[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \dc_bias[3]_i_9_n_0\,
I1 => \dc_bias[3]_i_10_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => p_1_in,
O => \dc_bias[3]_i_3_n_0\
);
\dc_bias[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0022AAAA32EAAAAA"
)
port map (
I0 => \dc_bias[3]_i_11_n_0\,
I1 => \dc_bias[3]_i_12_n_0\,
I2 => rgb(0),
I3 => rgb(7),
I4 => \dc_bias[3]_i_13_n_0\,
I5 => \dc_bias[3]_i_14_n_0\,
O => \dc_bias[3]_i_4_n_0\
);
\dc_bias[3]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5656566A566A6A6A"
)
port map (
I0 => \dc_bias[2]_i_4__0_n_0\,
I1 => \dc_bias[3]_i_15_n_0\,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias[3]_i_16__1_n_0\,
I4 => \dc_bias[3]_i_17__1_n_0\,
I5 => \dc_bias_reg_n_0_[1]\,
O => \dc_bias[3]_i_5__0_n_0\
);
\dc_bias[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \dc_bias_reg_n_0_[1]\,
I1 => p_1_in,
I2 => \dc_bias_reg_n_0_[2]\,
I3 => \dc_bias_reg_n_0_[0]\,
I4 => \dc_bias[3]_i_18_n_0\,
O => \dc_bias[3]_i_6_n_0\
);
\dc_bias[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0000400040C0CC"
)
port map (
I0 => \dc_bias[3]_i_19_n_0\,
I1 => \dc_bias[2]_i_4__0_n_0\,
I2 => \dc_bias[3]_i_20__1_n_0\,
I3 => \dc_bias[3]_i_21__0_n_0\,
I4 => \dc_bias_reg_n_0_[2]\,
I5 => \dc_bias[3]_i_15_n_0\,
O => \dc_bias[3]_i_7_n_0\
);
\dc_bias[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000096969996"
)
port map (
I0 => p_1_in,
I1 => \dc_bias[3]_i_22_n_0\,
I2 => \dc_bias[3]_i_23_n_0\,
I3 => \dc_bias[3]_i_24_n_0\,
I4 => \dc_bias[2]_i_5_n_0\,
I5 => \dc_bias[2]_i_4__0_n_0\,
O => \dc_bias[3]_i_8_n_0\
);
\dc_bias[3]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \dc_bias[1]_i_6_n_0\,
I1 => \dc_bias[2]_i_12_n_0\,
I2 => \dc_bias[1]_i_7_n_0\,
O => \dc_bias[3]_i_9_n_0\
);
\dc_bias_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[0]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[0]\,
R => SR(0)
);
\dc_bias_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias_reg[1]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[1]\,
R => SR(0)
);
\dc_bias_reg[1]_i_1\: unisim.vcomponents.MUXF7
port map (
I0 => \dc_bias[1]_i_2_n_0\,
I1 => \dc_bias[1]_i_3_n_0\,
O => \dc_bias_reg[1]_i_1_n_0\,
S => \dc_bias[3]_i_6_n_0\
);
\dc_bias_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[2]_i_1_n_0\,
Q => \dc_bias_reg_n_0_[2]\,
R => SR(0)
);
\dc_bias_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => \dc_bias[3]_i_2_n_0\,
Q => p_1_in,
R => SR(0)
);
\encoded[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"28"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => \encoded[9]_i_2_n_0\,
O => encoded(0)
);
\encoded[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => active,
I1 => \encoded[7]_i_3_n_0\,
I2 => rgb(1),
I3 => rgb(0),
O => encoded(1)
);
\encoded[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7DD7D77D"
)
port map (
I0 => active,
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
I4 => \encoded[9]_i_2_n_0\,
O => encoded(2)
);
\encoded[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8228288228828228"
)
port map (
I0 => active,
I1 => rgb(2),
I2 => rgb(1),
I3 => rgb(0),
I4 => rgb(3),
I5 => \encoded[7]_i_3_n_0\,
O => encoded(3)
);
\encoded[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7DD7"
)
port map (
I0 => active,
I1 => \encoded[6]_i_2_n_0\,
I2 => rgb(4),
I3 => \encoded[9]_i_2_n_0\,
O => encoded(4)
);
\encoded[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82282882"
)
port map (
I0 => active,
I1 => rgb(4),
I2 => rgb(5),
I3 => \encoded[6]_i_2_n_0\,
I4 => \encoded[7]_i_3_n_0\,
O => encoded(5)
);
\encoded[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7DD7D77DD77D7DD7"
)
port map (
I0 => active,
I1 => rgb(6),
I2 => rgb(5),
I3 => rgb(4),
I4 => \encoded[6]_i_2_n_0\,
I5 => \encoded[9]_i_2_n_0\,
O => encoded(6)
);
\encoded[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => rgb(3),
I1 => rgb(0),
I2 => rgb(1),
I3 => rgb(2),
O => \encoded[6]_i_2_n_0\
);
\encoded[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => active,
I1 => \encoded[7]_i_2__0_n_0\,
I2 => rgb(7),
I3 => \encoded[7]_i_3_n_0\,
O => encoded(7)
);
\encoded[7]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \encoded[6]_i_2_n_0\,
I1 => rgb(4),
I2 => rgb(5),
I3 => rgb(6),
O => \encoded[7]_i_2__0_n_0\
);
\encoded[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \dc_bias[3]_i_6_n_0\,
I1 => \dc_bias[2]_i_4__0_n_0\,
I2 => \dc_bias[3]_i_4_n_0\,
O => \encoded[7]_i_3_n_0\
);
\encoded[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => active,
O => \encoded[8]_i_1_n_0\
);
\encoded[9]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \encoded[9]_i_2_n_0\,
I1 => active,
O => \encoded[9]_i_1__0_n_0\
);
\encoded[9]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \dc_bias[3]_i_4_n_0\,
I1 => \dc_bias[3]_i_6_n_0\,
I2 => \dc_bias[2]_i_4__0_n_0\,
O => \encoded[9]_i_2_n_0\
);
\encoded_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(0),
Q => \encoded_reg_n_0_[0]\,
R => '0'
);
\encoded_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(1),
Q => \encoded_reg_n_0_[1]\,
R => '0'
);
\encoded_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(2),
Q => \encoded_reg_n_0_[2]\,
R => '0'
);
\encoded_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(3),
Q => \encoded_reg_n_0_[3]\,
R => '0'
);
\encoded_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(4),
Q => \encoded_reg_n_0_[4]\,
R => '0'
);
\encoded_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(5),
Q => \encoded_reg_n_0_[5]\,
R => '0'
);
\encoded_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(6),
Q => \encoded_reg_n_0_[6]\,
R => '0'
);
\encoded_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => encoded(7),
Q => \encoded_reg_n_0_[7]\,
R => '0'
);
\encoded_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[8]_i_1_n_0\,
Q => Q(0),
R => '0'
);
\encoded_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \encoded[9]_i_1__0_n_0\,
Q => Q(1),
R => '0'
);
\shift_red[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(0),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[0]\,
O => D(0)
);
\shift_red[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(1),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[1]\,
O => D(1)
);
\shift_red[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(2),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[2]\,
O => D(2)
);
\shift_red[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(3),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[3]\,
O => D(3)
);
\shift_red[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(4),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[4]\,
O => D(4)
);
\shift_red[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(5),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[5]\,
O => D(5)
);
\shift_red[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(6),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[6]\,
O => D(6)
);
\shift_red[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data1(7),
I1 => \shift_clock_reg[5]\,
I2 => \encoded_reg_n_0_[7]\,
O => D(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_dvid is
port (
red_s : out STD_LOGIC;
green_s : out STD_LOGIC;
blue_s : out STD_LOGIC;
clock_s : out STD_LOGIC;
clk_125 : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_dvid : entity is "dvid";
end system_zybo_hdmi_0_0_dvid;
architecture STRUCTURE of system_zybo_hdmi_0_0_dvid is
signal D0 : STD_LOGIC;
signal D1 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_0 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_10 : STD_LOGIC;
signal TMDS_encoder_BLUE_n_9 : STD_LOGIC;
signal TMDS_encoder_GREEN_n_8 : STD_LOGIC;
signal TMDS_encoder_GREEN_n_9 : STD_LOGIC;
signal TMDS_encoder_RED_n_8 : STD_LOGIC;
signal TMDS_encoder_RED_n_9 : STD_LOGIC;
signal clk_dvin : STD_LOGIC;
signal data1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal shift_blue : STD_LOGIC_VECTOR ( 9 downto 2 );
signal shift_blue_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_blue_reg_n_0_[0]\ : STD_LOGIC;
signal \shift_blue_reg_n_0_[1]\ : STD_LOGIC;
signal shift_clock : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \shift_clock_reg_n_0_[2]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[3]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[4]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[5]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[6]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[7]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[8]\ : STD_LOGIC;
signal \shift_clock_reg_n_0_[9]\ : STD_LOGIC;
signal shift_green : STD_LOGIC_VECTOR ( 9 downto 2 );
signal shift_green_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_green_reg_n_0_[0]\ : STD_LOGIC;
signal \shift_green_reg_n_0_[1]\ : STD_LOGIC;
signal shift_red : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \shift_red[9]_i_1_n_0\ : STD_LOGIC;
signal \shift_red[9]_i_2_n_0\ : STD_LOGIC;
signal NLW_ODDR2_BLUE_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_BLUE_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_CLK_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_CLK_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_GREEN_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_GREEN_S_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_RED_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR2_RED_S_UNCONNECTED : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ODDR2_BLUE : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of ODDR2_BLUE : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR2_BLUE : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR2_BLUE : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_CLK : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_CLK : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_CLK : label is "TRUE";
attribute box_type of ODDR2_CLK : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_GREEN : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_GREEN : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_GREEN : label is "TRUE";
attribute box_type of ODDR2_GREEN : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ODDR2_RED : label is "ODDR2";
attribute XILINX_TRANSFORM_PINMAP of ODDR2_RED : label is "D0:D1 D1:D2 C0:C";
attribute \__SRVAL\ of ODDR2_RED : label is "TRUE";
attribute box_type of ODDR2_RED : label is "PRIMITIVE";
begin
ODDR2_BLUE: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => \shift_blue_reg_n_0_[0]\,
D2 => \shift_blue_reg_n_0_[1]\,
Q => blue_s,
R => NLW_ODDR2_BLUE_R_UNCONNECTED,
S => NLW_ODDR2_BLUE_S_UNCONNECTED
);
ODDR2_CLK: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => shift_clock(0),
D2 => shift_clock(1),
Q => clock_s,
R => NLW_ODDR2_CLK_R_UNCONNECTED,
S => NLW_ODDR2_CLK_S_UNCONNECTED
);
ODDR2_GREEN: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => \shift_green_reg_n_0_[0]\,
D2 => \shift_green_reg_n_0_[1]\,
Q => green_s,
R => NLW_ODDR2_GREEN_R_UNCONNECTED,
S => NLW_ODDR2_GREEN_S_UNCONNECTED
);
ODDR2_RED: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C => clk_125,
CE => '1',
D1 => D0,
D2 => D1,
Q => red_s,
R => NLW_ODDR2_RED_R_UNCONNECTED,
S => NLW_ODDR2_RED_S_UNCONNECTED
);
ODDR2_RED_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_125,
O => clk_dvin
);
TMDS_encoder_BLUE: entity work.system_zybo_hdmi_0_0_TMDS_encoder
port map (
D(7 downto 0) => shift_blue_0(7 downto 0),
Q(1) => TMDS_encoder_BLUE_n_9,
Q(0) => TMDS_encoder_BLUE_n_10,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
hsync => hsync,
rgb(7 downto 0) => rgb(7 downto 0),
shift_blue(7 downto 0) => shift_blue(9 downto 2),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\,
vsync => vsync
);
TMDS_encoder_GREEN: entity work.system_zybo_hdmi_0_0_TMDS_encoder_0
port map (
D(7 downto 0) => shift_green_1(7 downto 0),
Q(1) => TMDS_encoder_GREEN_n_8,
Q(0) => TMDS_encoder_GREEN_n_9,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
rgb(7 downto 0) => rgb(15 downto 8),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\,
shift_green(7 downto 0) => shift_green(9 downto 2)
);
TMDS_encoder_RED: entity work.system_zybo_hdmi_0_0_TMDS_encoder_1
port map (
D(7 downto 0) => shift_red(7 downto 0),
Q(1) => TMDS_encoder_RED_n_8,
Q(0) => TMDS_encoder_RED_n_9,
SR(0) => TMDS_encoder_BLUE_n_0,
active => active,
clk_25 => clk_25,
data1(7 downto 0) => data1(7 downto 0),
rgb(7 downto 0) => rgb(23 downto 16),
\shift_clock_reg[5]\ => \shift_red[9]_i_1_n_0\
);
\shift_blue_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(0),
Q => \shift_blue_reg_n_0_[0]\,
R => '0'
);
\shift_blue_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(1),
Q => \shift_blue_reg_n_0_[1]\,
R => '0'
);
\shift_blue_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(2),
Q => shift_blue(2),
R => '0'
);
\shift_blue_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(3),
Q => shift_blue(3),
R => '0'
);
\shift_blue_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(4),
Q => shift_blue(4),
R => '0'
);
\shift_blue_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(5),
Q => shift_blue(5),
R => '0'
);
\shift_blue_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(6),
Q => shift_blue(6),
R => '0'
);
\shift_blue_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_blue_0(7),
Q => shift_blue(7),
R => '0'
);
\shift_blue_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_BLUE_n_10,
Q => shift_blue(8),
R => \shift_red[9]_i_1_n_0\
);
\shift_blue_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_BLUE_n_9,
Q => shift_blue(9),
R => \shift_red[9]_i_1_n_0\
);
\shift_clock_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[2]\,
Q => shift_clock(0),
R => '0'
);
\shift_clock_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[3]\,
Q => shift_clock(1),
R => '0'
);
\shift_clock_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[4]\,
Q => \shift_clock_reg_n_0_[2]\,
R => '0'
);
\shift_clock_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[5]\,
Q => \shift_clock_reg_n_0_[3]\,
R => '0'
);
\shift_clock_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[6]\,
Q => \shift_clock_reg_n_0_[4]\,
R => '0'
);
\shift_clock_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[7]\,
Q => \shift_clock_reg_n_0_[5]\,
R => '0'
);
\shift_clock_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[8]\,
Q => \shift_clock_reg_n_0_[6]\,
R => '0'
);
\shift_clock_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => \shift_clock_reg_n_0_[9]\,
Q => \shift_clock_reg_n_0_[7]\,
R => '0'
);
\shift_clock_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_clock(0),
Q => \shift_clock_reg_n_0_[8]\,
R => '0'
);
\shift_clock_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_clock(1),
Q => \shift_clock_reg_n_0_[9]\,
R => '0'
);
\shift_green_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(0),
Q => \shift_green_reg_n_0_[0]\,
R => '0'
);
\shift_green_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(1),
Q => \shift_green_reg_n_0_[1]\,
R => '0'
);
\shift_green_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(2),
Q => shift_green(2),
R => '0'
);
\shift_green_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(3),
Q => shift_green(3),
R => '0'
);
\shift_green_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(4),
Q => shift_green(4),
R => '0'
);
\shift_green_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(5),
Q => shift_green(5),
R => '0'
);
\shift_green_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(6),
Q => shift_green(6),
R => '0'
);
\shift_green_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_green_1(7),
Q => shift_green(7),
R => '0'
);
\shift_green_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_GREEN_n_9,
Q => shift_green(8),
R => \shift_red[9]_i_1_n_0\
);
\shift_green_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_GREEN_n_8,
Q => shift_green(9),
R => \shift_red[9]_i_1_n_0\
);
\shift_red[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFFFFF"
)
port map (
I0 => \shift_red[9]_i_2_n_0\,
I1 => \shift_clock_reg_n_0_[5]\,
I2 => \shift_clock_reg_n_0_[4]\,
I3 => \shift_clock_reg_n_0_[2]\,
I4 => \shift_clock_reg_n_0_[3]\,
O => \shift_red[9]_i_1_n_0\
);
\shift_red[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFF"
)
port map (
I0 => \shift_clock_reg_n_0_[8]\,
I1 => \shift_clock_reg_n_0_[9]\,
I2 => \shift_clock_reg_n_0_[6]\,
I3 => \shift_clock_reg_n_0_[7]\,
I4 => shift_clock(1),
I5 => shift_clock(0),
O => \shift_red[9]_i_2_n_0\
);
\shift_red_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(0),
Q => D0,
R => '0'
);
\shift_red_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(1),
Q => D1,
R => '0'
);
\shift_red_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(2),
Q => data1(0),
R => '0'
);
\shift_red_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(3),
Q => data1(1),
R => '0'
);
\shift_red_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(4),
Q => data1(2),
R => '0'
);
\shift_red_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(5),
Q => data1(3),
R => '0'
);
\shift_red_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(6),
Q => data1(4),
R => '0'
);
\shift_red_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => shift_red(7),
Q => data1(5),
R => '0'
);
\shift_red_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_RED_n_9,
Q => data1(6),
R => \shift_red[9]_i_1_n_0\
);
\shift_red_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_125,
CE => '1',
D => TMDS_encoder_RED_n_8,
Q => data1(7),
R => \shift_red[9]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0_zybo_hdmi is
port (
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zybo_hdmi_0_0_zybo_hdmi : entity is "zybo_hdmi";
end system_zybo_hdmi_0_0_zybo_hdmi;
architecture STRUCTURE of system_zybo_hdmi_0_0_zybo_hdmi is
signal blue_s : STD_LOGIC;
signal clock_s : STD_LOGIC;
signal green_s : STD_LOGIC;
signal red_s : STD_LOGIC;
attribute CAPACITANCE : string;
attribute CAPACITANCE of OBUFDS_blue : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of OBUFDS_blue : label is "OBUFDS";
attribute box_type : string;
attribute box_type of OBUFDS_blue : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_clock : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_clock : label is "OBUFDS";
attribute box_type of OBUFDS_clock : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_green : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_green : label is "OBUFDS";
attribute box_type of OBUFDS_green : label is "PRIMITIVE";
attribute CAPACITANCE of OBUFDS_red : label is "DONT_CARE";
attribute XILINX_LEGACY_PRIM of OBUFDS_red : label is "OBUFDS";
attribute box_type of OBUFDS_red : label is "PRIMITIVE";
begin
DVID: entity work.system_zybo_hdmi_0_0_dvid
port map (
active => active,
blue_s => blue_s,
clk_125 => clk_125,
clk_25 => clk_25,
clock_s => clock_s,
green_s => green_s,
hsync => hsync,
red_s => red_s,
rgb(23 downto 0) => rgb(23 downto 0),
vsync => vsync
);
OBUFDS_blue: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => blue_s,
O => tmds(0),
OB => tmdsb(0)
);
OBUFDS_clock: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clock_s,
O => tmds(3),
OB => tmdsb(3)
);
OBUFDS_green: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => red_s,
O => tmds(2),
OB => tmdsb(2)
);
OBUFDS_red: unisim.vcomponents.OBUFDS
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => green_s,
O => tmds(1),
OB => tmdsb(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zybo_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zybo_hdmi_0_0 : entity is "system_zybo_hdmi_0_0,zybo_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zybo_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zybo_hdmi_0_0 : entity is "zybo_hdmi,Vivado 2016.4";
end system_zybo_hdmi_0_0;
architecture STRUCTURE of system_zybo_hdmi_0_0 is
signal \<const1>\ : STD_LOGIC;
begin
hdmi_out_en <= \<const1>\;
U0: entity work.system_zybo_hdmi_0_0_zybo_hdmi
port map (
active => active,
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
rgb(23 downto 0) => rgb(23 downto 0),
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0),
vsync => vsync
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
| mit | 2c0010277bb95cac39778f6b38dc8b10 | 0.48488 | 2.42458 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/hdl/reg_file_pkg.vhd | 1 | 5,846 | -------------------------------------------------------------------------------
-- Title : Components package (generated by Emacs VHDL Mode 3.33.6)
-- Project :
-------------------------------------------------------------------------------
-- File : components.vhd
-- Author : Calle <calle@Alukiste>
-- Created : 2012-03-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reset_pkg.all;
-------------------------------------------------------------------------------
package reg_file_pkg is
type reg_file_type is array (natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- A single 16-bit register.
component peripheral_register is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
RESET_IMPL : reset_type := none);
port (
dout_p : out std_logic_vector(15 downto 0);
din_p : in std_logic_vector(15 downto 0);
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reset : in std_logic;
clk : in std_logic);
end component peripheral_register;
-- Several (2**(REG_ADDR_BIT)) 16-bit registers.
component reg_file
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
REG_ADDR_BIT : natural;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reg_o : out reg_file_type(2**REG_ADDR_BIT-1 downto 0);
reg_i : in reg_file_type(2**REG_ADDR_BIT-1 downto 0);
reset : in std_logic;
clk : in std_logic);
end component;
component reg_file_bram is
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
bram_data_i : in std_logic_vector(15 downto 0);
bram_data_o : out std_logic_vector(15 downto 0);
bram_addr_i : in std_logic_vector(9 downto 0);
bram_we_p : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component reg_file_bram;
component reg_file_bram_double_buffered
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_addr_i : in std_logic_vector(7 downto 0);
bram_we_p : in std_logic;
irq_o : out std_logic;
ack_i : in std_logic;
ready_i : in std_logic;
enable_o : out std_logic;
bank_x_o : out std_logic;
bank_y_o : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component double_buffering is
port (
ready_p : in std_logic;
enable_p : out std_logic;
irq_p : out std_logic;
ack_p : in std_logic;
bank_p : out std_logic;
clk : in std_logic);
end component double_buffering;
procedure readWord(
constant addr : natural range 0 to 2**15-1;
signal bus_i : out busdevice_in_type;
signal clk : in std_logic);
procedure writeWord (
constant addr : in natural range 0 to 2**15-1;
constant data : in natural range 0 to 2**16-1;
signal bus_i : out busdevice_in_type;
signal clk : in std_logic);
end reg_file_pkg;
-------------------------------------------------------------------------------
package body reg_file_pkg is
----------------------------------------------------------------------------
-- Debug functions to simulate bus activity
----------------------------------------------------------------------------
-- Read a word from the internal bus
-- Example usage: readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
procedure readWord(
constant addr : natural range 0 to 2**15-1;
signal bus_i : out busdevice_in_type;
signal clk : in std_logic
) is
begin -- procedure readWord
if (clk = '1') then
wait until falling_edge(clk);
end if;
bus_i.addr <= std_logic_vector(to_unsigned(addr, bus_i.addr'length));
bus_i.data <= x"1234"; -- dummy data in read cycle
bus_i.re <= '1';
wait until rising_edge(clk);
-- ret := bus_o.data;
wait until falling_edge(clk);
bus_i.re <= '0';
end procedure readWord;
-- Write a word to the internal bus
-- Example usage: writeWord(addr => 16#0010#, data => 16#0055#, bus_i => bus_i, clk => clk);
procedure writeWord (
constant addr : in natural range 0 to 2**15-1;
constant data : in natural range 0 to 2**16-1;
signal bus_i : out busdevice_in_type;
signal clk : in std_logic) is
begin -- procedure writeWord
if (clk = '1') then
wait until falling_edge(clk);
end if;
bus_i.addr <= std_logic_vector(to_unsigned(addr, bus_i.addr'length));
bus_i.data <= std_logic_vector(to_unsigned(data, bus_i.data'length));
bus_i.we <= '1';
wait until rising_edge(clk);
wait until falling_edge(clk);
bus_i.we <= '0';
end procedure writeWord;
end package body reg_file_pkg;
| bsd-3-clause | a10063ee569bc03cd9c12ec379b12190 | 0.503934 | 3.723567 | false | false | false | false |
pgavin/carpe | hdl/cpu/btb/cache/replace/lfsr/cpu_btb_cache_replace_lfsr-rtl.vhdl | 1 | 2,214 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library mem;
library tech;
use work.cpu_btb_cache_config_pkg.all;
use work.cpu_btb_cache_replace_lfsr_config_pkg.all;
architecture rtl of cpu_btb_cache_replace_lfsr is
type comb_type is record
rway_enc : std_ulogic_vector(cpu_btb_cache_log2_assoc-1 downto 0);
end record;
signal c : comb_type;
begin
lfsr_assoc_loop : for n in cpu_btb_cache_log2_assoc-1 downto 0 generate
-- use different sizes for LFSRs for each bit so each sequence is different
lfsr : entity tech.lfsr(rtl)
generic map (
state_bits => cpu_btb_cache_replace_lfsr_state_bits + n
)
port map (
clk => clk,
rstn => rstn,
en => cpu_btb_cache_replace_lfsr_ctrl_in.re,
output => c.rway_enc(n)
);
end generate;
rway_dec : entity tech.decoder(rtl)
generic map (
output_bits => 2**cpu_btb_cache_log2_assoc
)
port map (
datain => c.rway_enc,
dataout => cpu_btb_cache_replace_lfsr_dp_out.rway
);
end;
| apache-2.0 | 8002a2762645ed782b3c8ac8d9dbf2c2 | 0.539295 | 4.290698 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl | 1 | 195,649 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 27 15:47:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={125} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
pullup_MIO_0inst: unisim.vcomponents.PULLUP
port map (
O => MIO(0)
);
pullup_MIO_9inst: unisim.vcomponents.PULLUP
port map (
O => MIO(9)
);
pullup_MIO_10inst: unisim.vcomponents.PULLUP
port map (
O => MIO(10)
);
pullup_MIO_11inst: unisim.vcomponents.PULLUP
port map (
O => MIO(11)
);
pullup_MIO_12inst: unisim.vcomponents.PULLUP
port map (
O => MIO(12)
);
pullup_MIO_13inst: unisim.vcomponents.PULLUP
port map (
O => MIO(13)
);
pullup_MIO_14inst: unisim.vcomponents.PULLUP
port map (
O => MIO(14)
);
pullup_MIO_15inst: unisim.vcomponents.PULLUP
port map (
O => MIO(15)
);
pullup_MIO_46inst: unisim.vcomponents.PULLUP
port map (
O => MIO(46)
);
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 57db58a3043fbdbdf1de88b67787b537 | 0.633901 | 2.761922 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough_vga/video_passthrough_vga.srcs/sources_1/bd/system/ip/system_zybo_vga_0_0/sim/system_zybo_vga_0_0.vhd | 1 | 3,527 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_vga:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_vga_0_0 IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END system_zybo_vga_0_0;
ARCHITECTURE system_zybo_vga_0_0_arch OF system_zybo_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_vga IS
PORT (
clk : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT zybo_vga;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : zybo_vga
PORT MAP (
clk => clk,
active => active,
rgb => rgb,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zybo_vga_0_0_arch;
| mit | 8917e860d09246ca6cae476c88d9784a | 0.717607 | 3.858862 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/system_ov7670_vga_1_0_sim_netlist.vhdl | 1 | 5,155 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:54:25 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_ov7670_vga_1_0 -prefix
-- system_ov7670_vga_1_0_ system_ov7670_vga_0_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end system_ov7670_vga_1_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_1_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal p_0_in0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => pclk,
CE => '1',
D => p_0_in0,
Q => cycle,
R => '0'
);
\rgb[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle,
O => p_0_in0
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_1_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_1_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_1_0;
architecture STRUCTURE of system_ov7670_vga_1_0 is
begin
U0: entity work.system_ov7670_vga_1_0_ov7670_vga
port map (
data(7 downto 0) => data(7 downto 0),
pclk => pclk,
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
| mit | 3f145319d0f6ad38301125ccd8f0f847 | 0.51581 | 3.197891 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_1rw-rtl.vhdl | 1 | 1,544 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of syncram_1rw is
begin
syncram : entity work.syncram_1rw_inferred(rtl)
generic map (
addr_bits => addr_bits,
data_bits => data_bits
)
port map (
clk => clk,
en => en,
we => we,
addr => addr,
wdata => wdata,
rdata => rdata
);
end;
| apache-2.0 | 5273b90758697d06223ea90b5436bc50 | 0.474093 | 5.251701 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_burst_adapter.vhd | 1 | 8,652 | -- niosii_system_burst_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_burst_adapter is
generic (
PKT_ADDR_H : integer := 42;
PKT_ADDR_L : integer := 18;
PKT_BEGIN_BURST : integer := 62;
PKT_BYTE_CNT_H : integer := 51;
PKT_BYTE_CNT_L : integer := 49;
PKT_BYTEEN_H : integer := 17;
PKT_BYTEEN_L : integer := 16;
PKT_BURST_SIZE_H : integer := 57;
PKT_BURST_SIZE_L : integer := 55;
PKT_BURST_TYPE_H : integer := 59;
PKT_BURST_TYPE_L : integer := 58;
PKT_BURSTWRAP_H : integer := 54;
PKT_BURSTWRAP_L : integer := 52;
PKT_TRANS_COMPRESSED_READ : integer := 43;
PKT_TRANS_WRITE : integer := 45;
PKT_TRANS_READ : integer := 46;
OUT_NARROW_SIZE : integer := 0;
IN_NARROW_SIZE : integer := 0;
OUT_FIXED : integer := 0;
OUT_COMPLETE_WRAP : integer := 0;
ST_DATA_W : integer := 82;
ST_CHANNEL_W : integer := 13;
OUT_BYTE_CNT_H : integer := 50;
OUT_BURSTWRAP_H : integer := 54;
COMPRESSED_READ_SUPPORT : integer := 0;
BYTEENABLE_SYNTHESIS : integer := 1;
PIPE_INPUTS : integer := 0;
NO_WRAP_SUPPORT : integer := 0;
BURSTWRAP_CONST_MASK : integer := 3;
BURSTWRAP_CONST_VALUE : integer := 3
);
port (
clk : in std_logic := '0'; -- cr0.clk
reset : in std_logic := '0'; -- cr0_reset.reset
sink0_valid : in std_logic := '0'; -- sink0.valid
sink0_data : in std_logic_vector(81 downto 0) := (others => '0'); -- .data
sink0_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
sink0_startofpacket : in std_logic := '0'; -- .startofpacket
sink0_endofpacket : in std_logic := '0'; -- .endofpacket
sink0_ready : out std_logic; -- .ready
source0_valid : out std_logic; -- source0.valid
source0_data : out std_logic_vector(81 downto 0); -- .data
source0_channel : out std_logic_vector(12 downto 0); -- .channel
source0_startofpacket : out std_logic; -- .startofpacket
source0_endofpacket : out std_logic; -- .endofpacket
source0_ready : in std_logic := '0' -- .ready
);
end entity niosii_system_burst_adapter;
architecture rtl of niosii_system_burst_adapter is
component altera_merlin_burst_adapter is
generic (
PKT_ADDR_H : integer := 79;
PKT_ADDR_L : integer := 48;
PKT_BEGIN_BURST : integer := 81;
PKT_BYTE_CNT_H : integer := 5;
PKT_BYTE_CNT_L : integer := 0;
PKT_BYTEEN_H : integer := 83;
PKT_BYTEEN_L : integer := 80;
PKT_BURST_SIZE_H : integer := 86;
PKT_BURST_SIZE_L : integer := 84;
PKT_BURST_TYPE_H : integer := 88;
PKT_BURST_TYPE_L : integer := 87;
PKT_BURSTWRAP_H : integer := 11;
PKT_BURSTWRAP_L : integer := 6;
PKT_TRANS_COMPRESSED_READ : integer := 14;
PKT_TRANS_WRITE : integer := 13;
PKT_TRANS_READ : integer := 12;
OUT_NARROW_SIZE : integer := 0;
IN_NARROW_SIZE : integer := 0;
OUT_FIXED : integer := 0;
OUT_COMPLETE_WRAP : integer := 0;
ST_DATA_W : integer := 89;
ST_CHANNEL_W : integer := 8;
OUT_BYTE_CNT_H : integer := 5;
OUT_BURSTWRAP_H : integer := 11;
COMPRESSED_READ_SUPPORT : integer := 1;
BYTEENABLE_SYNTHESIS : integer := 0;
PIPE_INPUTS : integer := 0;
NO_WRAP_SUPPORT : integer := 0;
BURSTWRAP_CONST_MASK : integer := 0;
BURSTWRAP_CONST_VALUE : integer := -1
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(81 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component altera_merlin_burst_adapter;
begin
pkt_trans_compressed_read_check : if PKT_TRANS_COMPRESSED_READ /= 43 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
burst_adapter : component altera_merlin_burst_adapter
generic map (
PKT_ADDR_H => PKT_ADDR_H,
PKT_ADDR_L => PKT_ADDR_L,
PKT_BEGIN_BURST => PKT_BEGIN_BURST,
PKT_BYTE_CNT_H => PKT_BYTE_CNT_H,
PKT_BYTE_CNT_L => PKT_BYTE_CNT_L,
PKT_BYTEEN_H => PKT_BYTEEN_H,
PKT_BYTEEN_L => PKT_BYTEEN_L,
PKT_BURST_SIZE_H => PKT_BURST_SIZE_H,
PKT_BURST_SIZE_L => PKT_BURST_SIZE_L,
PKT_BURST_TYPE_H => PKT_BURST_TYPE_H,
PKT_BURST_TYPE_L => PKT_BURST_TYPE_L,
PKT_BURSTWRAP_H => PKT_BURSTWRAP_H,
PKT_BURSTWRAP_L => PKT_BURSTWRAP_L,
PKT_TRANS_COMPRESSED_READ => 43,
PKT_TRANS_WRITE => PKT_TRANS_WRITE,
PKT_TRANS_READ => PKT_TRANS_READ,
OUT_NARROW_SIZE => OUT_NARROW_SIZE,
IN_NARROW_SIZE => IN_NARROW_SIZE,
OUT_FIXED => OUT_FIXED,
OUT_COMPLETE_WRAP => OUT_COMPLETE_WRAP,
ST_DATA_W => ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OUT_BYTE_CNT_H => OUT_BYTE_CNT_H,
OUT_BURSTWRAP_H => OUT_BURSTWRAP_H,
COMPRESSED_READ_SUPPORT => COMPRESSED_READ_SUPPORT,
BYTEENABLE_SYNTHESIS => BYTEENABLE_SYNTHESIS,
PIPE_INPUTS => PIPE_INPUTS,
NO_WRAP_SUPPORT => NO_WRAP_SUPPORT,
BURSTWRAP_CONST_MASK => BURSTWRAP_CONST_MASK,
BURSTWRAP_CONST_VALUE => BURSTWRAP_CONST_VALUE
)
port map (
clk => clk, -- cr0.clk
reset => reset, -- cr0_reset.reset
sink0_valid => sink0_valid, -- sink0.valid
sink0_data => sink0_data, -- .data
sink0_channel => sink0_channel, -- .channel
sink0_startofpacket => sink0_startofpacket, -- .startofpacket
sink0_endofpacket => sink0_endofpacket, -- .endofpacket
sink0_ready => sink0_ready, -- .ready
source0_valid => source0_valid, -- source0.valid
source0_data => source0_data, -- .data
source0_channel => source0_channel, -- .channel
source0_startofpacket => source0_startofpacket, -- .startofpacket
source0_endofpacket => source0_endofpacket, -- .endofpacket
source0_ready => source0_ready -- .ready
);
end architecture rtl; -- of niosii_system_burst_adapter
| apache-2.0 | e6e9099ce06b27008b92bf8e034cfe2d | 0.473301 | 3.658351 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/madd_seq_inferred-rtl.vhdl | 1 | 4,778 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
architecture rtl of madd_seq_inferred is
type comb_type is record
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
prod_tmp1 : std_ulogic_vector(src1_bits+src2_bits+1 downto 0);
prod_tmp2 : std_ulogic_vector(src1_bits+src2_bits downto 0);
acc_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_tmp : std_ulogic_vector(src1_bits+src2_bits downto 0);
result_msb_carryin : std_ulogic;
result_msb : std_ulogic;
carryout : std_ulogic;
result : std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
overflow : std_ulogic;
end record;
signal c : comb_type;
type stage_type is record
overflow : std_ulogic;
result : std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
end record;
constant stage_x : stage_type := (
overflow => 'X',
result => (others => 'X')
);
type pipe_type is array(latency-1 downto 0) of stage_type;
type reg_type is record
status : std_ulogic_vector(latency-1 downto 0);
pipe : pipe_type;
end record;
constant reg_x : reg_type := (
status => (others => 'X'),
pipe => (others => stage_x)
);
signal r, r_next : reg_type;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src2(src2_bits-1) and not unsgnd) & src2;
c.prod_tmp1 <= std_ulogic_vector(signed(c.src1_tmp) * signed(c.src2_tmp));
c.prod_tmp2 <= (('0' & c.prod_tmp1(src1_bits+src2_bits-2 downto 0) & '0') xor
(src1_bits+src2_bits downto 0 => sub));
c.acc_tmp <= '0' & acc(src1_bits+src2_bits-2 downto 0) & '1';
c.result_tmp <= std_ulogic_vector(signed(c.acc_tmp) +
signed(c.prod_tmp2));
c.result_msb_carryin <= c.result_tmp(src1_bits+src2_bits);
c.result_msb <= (acc(src1_bits+src2_bits-1) xor
c.prod_tmp1(src1_bits+src2_bits-1) xor
c.result_msb_carryin
);
c.carryout <= (((sub xor acc(src1_bits+src2_bits-1)) and (c.prod_tmp1(src1_bits+src2_bits-1) or c.result_msb_carryin)) or
(c.prod_tmp1(src1_bits+src2_bits-1) and c.result_msb_carryin));
c.overflow <= c.carryout xor (not unsgnd and c.result_msb_carryin);
c.result <= c.result_msb & c.result_tmp(src1_bits+src2_bits-1 downto 1);
status_latency_gt_1 : if latency > 1 generate
r_next.status(latency-1) <= (r.status(latency-1) or r.status(latency-2)) and not en;
status_latency_gt_2 : if latency > 2 generate
status_loop : for n in latency-2 downto 1 generate
r_next.status(n) <= r.status(n-1) and not en;
end generate;
end generate;
r_next.status(0) <= en;
end generate;
status_latency_eq_1 : if latency = 1 generate
r_next.status(0) <= r.status(0) or en;
end generate;
with en select
r_next.pipe(0) <= r.pipe(0) when '0',
(overflow => c.overflow,
result => c.result
) when '1',
stage_x when others;
pipe_loop : for n in latency-1 downto 1 generate
with en select
r_next.pipe(n) <= r.pipe(n-1) when '0',
stage_x when others;
end generate;
valid <= r.status(latency-1);
result <= r.pipe(latency-1).result;
overflow <= r.pipe(latency-1).overflow;
seq : process(clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
| apache-2.0 | 52abc3707a5260f455b9ce64bb05ca83 | 0.566764 | 3.434939 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_buffer_register_0_0/system_buffer_register_0_0_sim_netlist.vhdl | 1 | 7,575 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 20:15:21 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_buffer_register_0_0 -prefix
-- system_buffer_register_0_0_ system_buffer_register_0_0_sim_netlist.vhdl
-- Design : system_buffer_register_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_0_0_buffer_register is
port (
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
clk : in STD_LOGIC
);
end system_buffer_register_0_0_buffer_register;
architecture STRUCTURE of system_buffer_register_0_0_buffer_register is
begin
\val_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(0),
Q => val_out(0),
R => '0'
);
\val_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(10),
Q => val_out(10),
R => '0'
);
\val_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(11),
Q => val_out(11),
R => '0'
);
\val_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(12),
Q => val_out(12),
R => '0'
);
\val_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(13),
Q => val_out(13),
R => '0'
);
\val_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(14),
Q => val_out(14),
R => '0'
);
\val_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(15),
Q => val_out(15),
R => '0'
);
\val_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(16),
Q => val_out(16),
R => '0'
);
\val_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(17),
Q => val_out(17),
R => '0'
);
\val_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(18),
Q => val_out(18),
R => '0'
);
\val_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(19),
Q => val_out(19),
R => '0'
);
\val_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(1),
Q => val_out(1),
R => '0'
);
\val_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(20),
Q => val_out(20),
R => '0'
);
\val_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(21),
Q => val_out(21),
R => '0'
);
\val_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(22),
Q => val_out(22),
R => '0'
);
\val_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(23),
Q => val_out(23),
R => '0'
);
\val_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(24),
Q => val_out(24),
R => '0'
);
\val_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(25),
Q => val_out(25),
R => '0'
);
\val_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(26),
Q => val_out(26),
R => '0'
);
\val_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(27),
Q => val_out(27),
R => '0'
);
\val_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(28),
Q => val_out(28),
R => '0'
);
\val_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(29),
Q => val_out(29),
R => '0'
);
\val_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(2),
Q => val_out(2),
R => '0'
);
\val_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(30),
Q => val_out(30),
R => '0'
);
\val_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(31),
Q => val_out(31),
R => '0'
);
\val_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(3),
Q => val_out(3),
R => '0'
);
\val_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(4),
Q => val_out(4),
R => '0'
);
\val_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(5),
Q => val_out(5),
R => '0'
);
\val_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(6),
Q => val_out(6),
R => '0'
);
\val_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(7),
Q => val_out(7),
R => '0'
);
\val_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(8),
Q => val_out(8),
R => '0'
);
\val_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(9),
Q => val_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_buffer_register_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_buffer_register_0_0 : entity is "system_buffer_register_0_0,buffer_register,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_buffer_register_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_buffer_register_0_0 : entity is "buffer_register,Vivado 2016.4";
end system_buffer_register_0_0;
architecture STRUCTURE of system_buffer_register_0_0 is
begin
U0: entity work.system_buffer_register_0_0_buffer_register
port map (
clk => clk,
val_in(31 downto 0) => val_in(31 downto 0),
val_out(31 downto 0) => val_out(31 downto 0)
);
end STRUCTURE;
| mit | eda0dcdebd9534da6f1ce52501821c00 | 0.486865 | 3.101966 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 3,984 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Thu Mar 10 14:13:03 2016
--Host : minmi running 64-bit elementary OS Freya
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_out_en : out STD_LOGIC;
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en,
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0)
);
end STRUCTURE;
| mit | c97898f55a6469c316c148b04028d30b | 0.5876 | 3.093168 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/hdl/goertzel_pipeline.vhd | 2 | 3,706 | -------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fixed point implementation of Goertzel's Algorithm to detect a
-- fixed frequency in an analog signal.
--
-- This is just the pipeline. The control unit in in entity
-- goertzel_control_unit and the muxes are in goertzel_muxes.
--
-- This does not implement the calculation
-- of the magnitude of the signal at the end of one block.
-- Mind overflows!
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipeline is
generic (
-- Width of ADC input
-- Due to overflow prevention: Not as wide as the internal width of
-- calculations. Set in the signalprocessing_pkg.vhd
-- INPUT_WIDTH : natural := 14;
-- Width of internal calculations
-- Remember that internal multiplier are at most 18 bits wide (in Xilinx Spartan)
-- CALC_WIDTH : natural := 18;
-- Fixed point data format
Q : natural := 13
);
port (
-- Goertzel Coefficient calculated by
coef_p : in goertzel_coef_type;
-- One values from ADC
input_p : in goertzel_input_type;
-- The old result
delay_p : in goertzel_result_type;
-- Result
result_p : out goertzel_result_type;
clk : in std_logic
);
end goertzel_pipeline;
architecture rtl of goertzel_pipeline is
signal delay_1_reg : goertzel_data_type := (others => '0');
signal delay_1_reg2 : goertzel_data_type := (others => '0');
signal delay_2_reg : goertzel_data_type := (others => '0');
signal delay_2_reg2 : goertzel_data_type := (others => '0');
signal coef_reg : goertzel_coef_type := (others => '0');
signal input_reg : goertzel_input_type := (others => '0');
signal input_reg2 : goertzel_input_type := (others => '0');
signal prod_scaled_reg : goertzel_data_type := (others => '0');
signal overflow : std_logic := '0';
begin -- architecture rtl
-- data path B
B : process (clk) is
variable prod_v : signed(35 downto 0) := (others => '0');
begin -- process B
if rising_edge(clk) then -- rising clock edge
-- 1st RTL
-- inputs from BRAM is already registered
--delay_1_reg2 <= delay_p(0);
--delay_2_reg2 <= delay_p(1);
coef_reg <= coef_p;
input_reg <= input_p;
-- 2nd RTL
delay_1_reg2 <= delay_p(0);
delay_2_reg2 <= delay_p(1);
prod_v := delay_p(0) * coef_reg;
prod_scaled_reg <= prod_v((Q + CALC_WIDTH - 1) downto Q);
if (prod_v(35 downto Q + CALC_WIDTH) = (35 downto (Q + CALC_WIDTH) => '0')) or
(prod_v(35 downto Q + CALC_WIDTH) = (35 downto (Q + CALC_WIDTH) => '1')) then
overflow <= '0';
else
overflow <= '1';
end if;
input_reg2 <= input_reg;
-- 3rd RTL
result_p(0) <= -delay_2_reg2 + prod_scaled_reg + input_reg2;
result_p(1) <= delay_1_reg2;
end if;
end process B;
end architecture rtl;
| bsd-3-clause | 523685ed304062f65e3a5ffbedbdd591 | 0.513761 | 3.913411 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl | 1 | 19,037 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:21 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0_vga_sync_reset is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_reset_0_0_vga_sync_reset : entity is "vga_sync_reset";
end system_vga_sync_reset_0_0_vga_sync_reset;
architecture STRUCTURE of system_vga_sync_reset_0_0_vga_sync_reset is
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal \h_count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_2 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of hsync_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of vsync_i_2 : label is "soft_lutpair3";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000222A00000000"
)
port map (
I0 => active_i_2_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^xaddr\(8),
I4 => \^yaddr\(9),
I5 => rst,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => active,
R => '0'
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => \h_count_reg[0]_i_1_n_0\
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => plusOp(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => plusOp(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(3),
O => plusOp(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => plusOp(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
I5 => \^xaddr\(5),
O => plusOp(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^xaddr\(5),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(6),
O => plusOp(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => \^xaddr\(7),
O => plusOp(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7F0080"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => plusOp(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10000000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \h_count_reg[9]_i_4_n_0\,
I5 => rst,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFFF20000000"
)
port map (
I0 => \^xaddr\(8),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
I4 => \^xaddr\(7),
I5 => \^xaddr\(9),
O => plusOp(9)
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
I4 => \^xaddr\(4),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg[0]_i_1_n_0\,
Q => \^xaddr\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(1),
Q => \^xaddr\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(2),
Q => \^xaddr\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(3),
Q => \^xaddr\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(4),
Q => \^xaddr\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(5),
Q => \^xaddr\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(6),
Q => \^xaddr\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(7),
Q => \^xaddr\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(8),
Q => \^xaddr\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => plusOp(9),
Q => \^xaddr\(9),
R => \h_count_reg[9]_i_1_n_0\
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABEAFFFF"
)
port map (
I0 => hsync_i_2_n_0,
I1 => \^xaddr\(5),
I2 => \^xaddr\(6),
I3 => hsync_i_3_n_0,
I4 => rst,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^xaddr\(9),
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(3),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(4),
O => hsync_i_3_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^yaddr\(0),
O => \plusOp__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \plusOp__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
O => \plusOp__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^yaddr\(2),
I1 => \^yaddr\(0),
I2 => \^yaddr\(1),
I3 => \^yaddr\(3),
O => \plusOp__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \plusOp__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(0),
I3 => \^yaddr\(1),
I4 => \^yaddr\(3),
I5 => \^yaddr\(5),
O => \plusOp__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \^yaddr\(5),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(6),
O => \plusOp__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F708"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(7),
O => \plusOp__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF4000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(8),
O => \plusOp__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00400000FFFFFFFF"
)
port map (
I0 => \h_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \^yaddr\(0),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => rst,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(5),
I1 => \^xaddr\(6),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_3_n_0\,
O => \v_count_reg[9]_i_2_n_0\
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF40000000"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => \^yaddr\(7),
I2 => \^yaddr\(5),
I3 => \^yaddr\(6),
I4 => \^yaddr\(8),
I5 => \^yaddr\(9),
O => \plusOp__0\(9)
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^xaddr\(7),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
I4 => \^xaddr\(9),
I5 => \^xaddr\(8),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(4),
I2 => \^yaddr\(2),
I3 => \^yaddr\(1),
I4 => \^yaddr\(6),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(3),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(2),
I4 => \^yaddr\(4),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \^yaddr\(0),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \^yaddr\(1),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \^yaddr\(2),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \^yaddr\(3),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \^yaddr\(4),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \^yaddr\(5),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \^yaddr\(6),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \^yaddr\(7),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \^yaddr\(8),
R => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \^yaddr\(9),
R => \v_count_reg[9]_i_1_n_0\
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFFFFFF"
)
port map (
I0 => vsync_i_2_n_0,
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \^yaddr\(9),
I4 => \^yaddr\(4),
I5 => rst,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_reset_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_reset_0_0 : entity is "system_vga_sync_reset_0_0,vga_sync_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_reset_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_reset_0_0 : entity is "vga_sync_reset,Vivado 2016.4";
end system_vga_sync_reset_0_0;
architecture STRUCTURE of system_vga_sync_reset_0_0 is
begin
U0: entity work.system_vga_sync_reset_0_0_vga_sync_reset
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 707adce99150c57cba64e42025d16b9f | 0.491359 | 2.73363 | false | false | false | false |
pgavin/carpe | hdl/sys/sys_master_arb-rtl.vhdl | 1 | 14,383 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library tech;
use work.sys_pkg.all;
use work.sys_config_pkg.all;
architecture rtl of sys_master_arb is
subtype arb_sel_type is std_ulogic_vector(masters-1 downto 0);
type request_type is record
be : std_ulogic;
write : std_ulogic;
cacheable : std_ulogic;
priv : std_ulogic;
inst : std_ulogic;
burst : std_ulogic;
bwrap : std_ulogic;
bcycles : sys_burst_cycles_type;
size : sys_transfer_size_type;
paddr : sys_paddr_type;
data : sys_bus_type;
end record;
constant request_x : request_type := (
be => 'X',
write => 'X',
cacheable => 'X',
priv => 'X',
inst => 'X',
burst => 'X',
bwrap => 'X',
bcycles => (others => 'X'),
size => (others => 'X'),
paddr => (others => 'X'),
data => (others => 'X')
);
type comb_type is record
new_valid : arb_sel_type;
new_burst : arb_sel_type;
pending : arb_sel_type;
not_ready : arb_sel_type;
any_not_ready : std_ulogic;
any_burst_lock : std_ulogic;
request_sel_default_unpri : arb_sel_type;
request_sel_default : arb_sel_type;
request_sel : arb_sel_type;
request_array_be : arb_sel_type;
request_array_write : arb_sel_type;
request_array_cacheable : arb_sel_type;
request_array_priv : arb_sel_type;
request_array_inst : arb_sel_type;
request_array_burst : arb_sel_type;
request_array_bwrap : arb_sel_type;
request_array_bcycles : std_ulogic_vector2(masters-1 downto 0, sys_burst_cycles_bits-1 downto 0);
request_array_size : std_ulogic_vector2(masters-1 downto 0, sys_transfer_size_bits-1 downto 0);
request_array_paddr : std_ulogic_vector2(masters-1 downto 0, sys_paddr_bits-1 downto 0);
request_array_data : std_ulogic_vector2(masters-1 downto 0, sys_bus_bits-1 downto 0);
use_new_request : arb_sel_type;
request_be : std_ulogic;
request_write : std_ulogic;
request_cacheable : std_ulogic;
request_priv : std_ulogic;
request_inst : std_ulogic;
request_burst : std_ulogic;
request_bwrap : std_ulogic;
request_bcycles : sys_burst_cycles_type;
request_size : sys_transfer_size_type;
request_paddr : sys_paddr_type;
request_data : sys_bus_type;
end record;
type reg_type is record
valid : arb_sel_type;
requested : arb_sel_type;
burst_lock : arb_sel_type;
request_array_be : arb_sel_type;
request_array_write : arb_sel_type;
request_array_cacheable : arb_sel_type;
request_array_priv : arb_sel_type;
request_array_inst : arb_sel_type;
request_array_burst : arb_sel_type;
request_array_bwrap : arb_sel_type;
request_array_bcycles : std_ulogic_vector2(masters-1 downto 0, sys_burst_cycles_bits-1 downto 0);
request_array_size : std_ulogic_vector2(masters-1 downto 0, sys_transfer_size_bits-1 downto 0);
request_array_paddr : std_ulogic_vector2(masters-1 downto 0, sys_paddr_bits-1 downto 0);
request_array_data : std_ulogic_vector2(masters-1 downto 0, sys_bus_bits-1 downto 0);
end record;
constant reg_x : reg_type := (
valid => (others => 'X'),
requested => (others => 'X'),
burst_lock => (others => 'X'),
request_array_be => (others => 'X'),
request_array_write => (others => 'X'),
request_array_cacheable => (others => 'X'),
request_array_priv => (others => 'X'),
request_array_inst => (others => 'X'),
request_array_burst => (others => 'X'),
request_array_bwrap => (others => 'X'),
request_array_bcycles => (others => (others => 'X')),
request_array_size => (others => (others => 'X')),
request_array_paddr => (others => (others => 'X')),
request_array_data => (others => (others => 'X'))
);
constant reg_init : reg_type := (
valid => (others => '0'),
requested => (others => '0'),
burst_lock => (others => '0'),
request_array_be => (others => 'X'),
request_array_write => (others => 'X'),
request_array_cacheable => (others => 'X'),
request_array_priv => (others => 'X'),
request_array_inst => (others => 'X'),
request_array_burst => (others => 'X'),
request_array_bwrap => (others => 'X'),
request_array_bcycles => (others => (others => 'X')),
request_array_size => (others => (others => 'X')),
request_array_paddr => (others => (others => 'X')),
request_array_data => (others => (others => 'X'))
);
signal c : comb_type;
signal r, r_next : reg_type;
begin
master_loop : for n in masters-1 downto 0 generate
c.new_valid(n) <= sys_master_ctrl_out_master(n).request;
c.new_burst(n) <= sys_master_ctrl_out_master(n).burst;
c.pending(n) <= r.valid(n) and not (r.requested(n) and sys_slave_ctrl_out_sys.ready);
c.not_ready(n) <= r.requested(n) and not sys_slave_ctrl_out_sys.ready;
c.use_new_request(n) <= c.new_valid(n) and not c.pending(n);
with c.use_new_request(n) select
c.request_array_be(n) <= sys_master_ctrl_out_master(n).be when '1',
r.request_array_be(n) when '0',
'X' when others;
with c.use_new_request(n) select
c.request_array_write(n) <= sys_master_ctrl_out_master(n).write when '1',
r.request_array_write(n) when '0',
'X' when others;
with c.use_new_request(n) select
c.request_array_cacheable(n) <= sys_master_ctrl_out_master(n).cacheable when '1',
r.request_array_cacheable(n) when '0',
'X' when others;
with c.use_new_request(n) select
c.request_array_priv(n) <= sys_master_ctrl_out_master(n).priv when '1',
r.request_array_priv(n) when '0',
'X' when others;
with c.use_new_request(n) select
c.request_array_inst(n) <= sys_master_ctrl_out_master(n).inst when '1',
r.request_array_inst(n) when '0',
'X' when others;
with c.use_new_request(n) select
c.request_array_burst(n) <= sys_master_ctrl_out_master(n).burst when '1',
r.request_array_burst(n) when '0',
'X' when others;
with c.use_new_request(n) select
c.request_array_bwrap(n) <= sys_master_ctrl_out_master(n).bwrap when '1',
r.request_array_bwrap(n) when '0',
'X' when others;
blk : block
signal bcycles, new_bcycles, old_bcycles : sys_burst_cycles_type;
signal paddr, new_paddr, old_paddr : sys_paddr_type;
signal size, new_size, old_size : sys_transfer_size_type;
signal data, new_data, old_data : sys_bus_type;
begin
bcycles_in_loop : for m in sys_burst_cycles_bits-1 downto 0 generate
new_bcycles(m) <= sys_master_ctrl_out_master(n).bcycles(m);
old_bcycles(m) <= r.request_array_bcycles(n, m);
end generate;
size_in_loop : for m in sys_transfer_size_bits-1 downto 0 generate
new_size(m) <= sys_master_dp_out_master(n).size(m);
old_size(m) <= r.request_array_size(n, m);
end generate;
paddr_in_loop : for m in sys_paddr_bits-1 downto 0 generate
new_paddr(m) <= sys_master_dp_out_master(n).paddr(m);
old_paddr(m) <= r.request_array_paddr(n, m);
end generate;
data_in_loop : for m in sys_bus_bits-1 downto 0 generate
new_data(m) <= sys_master_dp_out_master(n).data(m);
old_data(m) <= r.request_array_data(n, m);
end generate;
with c.use_new_request(n) select
bcycles <= new_bcycles when '1',
old_bcycles when '0',
(others => 'X') when others;
with c.use_new_request(n) select
size <= new_size when '1',
old_size when '0',
(others => 'X') when others;
with c.use_new_request(n) select
paddr <= new_paddr when '1',
old_paddr when '0',
(others => 'X') when others;
with c.use_new_request(n) select
data <= new_data when '1',
old_data when '0',
(others => 'X') when others;
bcycles_out_loop : for m in sys_burst_cycles_bits-1 downto 0 generate
c.request_array_bcycles(n, m) <= bcycles(m);
end generate;
size_out_loop : for m in sys_transfer_size_bits-1 downto 0 generate
c.request_array_size(n, m) <= size(m);
end generate;
paddr_out_loop : for m in sys_paddr_bits-1 downto 0 generate
c.request_array_paddr(n, m) <= paddr(m);
end generate;
data_out_loop : for m in sys_bus_bits-1 downto 0 generate
c.request_array_data(n, m) <= data(m);
end generate;
end block;
end generate;
c.any_not_ready <= any_ones(c.not_ready);
c.any_burst_lock <= any_ones(r.burst_lock);
c.request_sel_default_unpri <= c.pending or c.new_valid;
c.request_sel_default <= prioritize_none(c.request_sel_default_unpri);
c.request_sel <= logic_if(c.any_not_ready,
r.requested,
logic_if(c.any_burst_lock,
r.burst_lock,
c.request_sel_default
)
);
r_next.valid <= c.new_valid or c.pending;
r_next.requested <= logic_if(c.any_not_ready, r.requested, c.request_sel);
r_next.burst_lock <= logic_if(c.any_not_ready, r.burst_lock, c.request_sel and c.request_array_burst);
r_next.request_array_be <= c.request_array_be;
r_next.request_array_write <= c.request_array_write;
r_next.request_array_cacheable <= c.request_array_cacheable;
r_next.request_array_priv <= c.request_array_priv;
r_next.request_array_inst <= c.request_array_inst;
r_next.request_array_burst <= c.request_array_burst;
r_next.request_array_bwrap <= c.request_array_bwrap;
r_next.request_array_bcycles <= c.request_array_bcycles;
r_next.request_array_size <= c.request_array_size;
r_next.request_array_paddr <= c.request_array_paddr;
r_next.request_array_data <= c.request_array_data;
c.request_be <= any_ones(c.request_sel and c.request_array_be);
c.request_write <= any_ones(c.request_sel and c.request_array_write);
c.request_cacheable <= any_ones(c.request_sel and c.request_array_cacheable);
c.request_priv <= any_ones(c.request_sel and c.request_array_priv);
c.request_inst <= any_ones(c.request_sel and c.request_array_inst);
c.request_burst <= any_ones(c.request_sel and c.request_array_burst);
c.request_bwrap <= any_ones(c.request_sel and c.request_array_bwrap);
request_size_mux : entity tech.mux_1hot(rtl)
generic map (
sel_bits => masters,
data_bits => sys_transfer_size_bits
)
port map (
din => c.request_array_size,
sel => c.request_sel,
dout => c.request_size
);
request_paddr_mux : entity tech.mux_1hot(rtl)
generic map (
sel_bits => masters,
data_bits => sys_paddr_bits
)
port map (
din => c.request_array_paddr,
sel => c.request_sel,
dout => c.request_paddr
);
request_data_mux : entity tech.mux_1hot(rtl)
generic map (
sel_bits => masters,
data_bits => sys_bus_bits
)
port map (
din => c.request_array_data,
sel => c.request_sel,
dout => c.request_data
);
request_bcycles_mux : entity tech.mux_1hot(rtl)
generic map (
sel_bits => masters,
data_bits => sys_burst_cycles_bits
)
port map (
din => c.request_array_bcycles,
sel => c.request_sel,
dout => c.request_bcycles
);
sys_master_ctrl_out_sys <= (
request => any_ones(c.request_sel),
be => c.request_be,
write => c.request_write,
cacheable => c.request_cacheable,
priv => c.request_priv,
inst => c.request_inst,
burst => c.request_burst,
bwrap => c.request_bwrap,
bcycles => c.request_bcycles
);
sys_master_dp_out_sys <= (
size => c.request_size,
paddr => c.request_paddr,
data => c.request_data
);
sys_slave_ctrl_out_master_loop : for n in masters-1 downto 0 generate
sys_slave_ctrl_out_master(n) <= (
ready => not c.pending(n),
error => sys_slave_ctrl_out_sys.error
);
end generate;
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r <= reg_init;
when others =>
r <= reg_x;
end case;
end if;
end process;
end;
| apache-2.0 | 6366237afdf9d0e63f539c298102c8fa | 0.55649 | 3.399433 | false | false | false | false |
loa-org/loa-hdl | modules/signalprocessing/hdl/goertzel_pipelined.vhd | 2 | 31,499 | -------------------------------------------------------------------------------
-- Title : Fixed point implementation of Goertzel's Algorithm
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Fixed point implementation of Goertzel's Algorithm to detect a
-- fixed frequency in an analog signal. Multiple channels and frequencies are
-- calculated pipelined to save resources (especially hardware multiplier).
--
-- This does not implement the calculation
-- of the magnitude of the signal at the end of one block.
-- Mind overflows!
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipelined is
generic (
-- Width of ADC input
-- Due to overflow prevention: Not as wide as the internal width of
-- calculations. Set in the signalprocessing_pkg.vhd
-- INPUT_WIDTH : natural := 14;
-- Width of internal calculations
-- Remember that internal multiplier are at most 18 bits wide (in Xilinx Spartan)
-- CALC_WIDTH : natural := 18;
-- Fixed point data format
Q : natural := 13;
-- Number of samples used to detect a frequency.
-- After SAMPLES samples new samples are available.
SAMPLES : natural := 250;
-- Number of Channels
CHANNELS : natural := 12;
-- Number of Frequencies
FREQUENCIES : natural := 2
);
port (
-- Goertzel Coefficient calculated by
-- c = 2 cos(2 pi f_signal / f_sample)
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
-- Values from ADC
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
-- clock enable input, is high when new value from ADC is available.
start_p : in std_logic;
results_p : out goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
-- clock enable outut, is high when new results are available
done_p : out std_logic;
clk : in std_logic
);
end goertzel_pipelined;
architecture behavioural of goertzel_pipelined is
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type goertzel_state_type is (
IDLE,
CALC
);
type goertzel_type is record
state : goertzel_state_type;
channel : natural range 0 to CHANNELS-1;
frequency : natural range 0 to FREQUENCIES-1;
sample_count : natural range 0 to SAMPLES-1;
done : std_logic;
delay_ch0_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f0_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f0_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch0_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch1_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch2_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch3_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch4_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch5_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch6_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch7_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch8_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch9_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch10_f1_1 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f1_0 : signed(CALC_WIDTH-1 downto 0);
delay_ch11_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f0_0 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f0_1 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch0_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch1_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch2_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch3_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch4_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch5_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch6_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch7_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch8_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch9_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch10_f1_1 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f1_0 : signed(CALC_WIDTH-1 downto 0);
result_ch11_f1_1 : signed(CALC_WIDTH-1 downto 0);
-- results : goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
-- delays : goertzel_results_type(CHANNELS-1 downto 0, FREQUENCIES-1 downto 0);
end record;
----------------------------------------------------------------------------
-- Internal signals
----------------------------------------------------------------------------
signal r, rin : goertzel_type := (
state => IDLE,
channel => 0,
frequency => 0,
sample_count => 0,
done => '0',
delay_ch0_f0_0 => (others => '0'),
delay_ch0_f0_1 => (others => '0'),
delay_ch1_f0_0 => (others => '0'),
delay_ch1_f0_1 => (others => '0'),
delay_ch2_f0_0 => (others => '0'),
delay_ch2_f0_1 => (others => '0'),
delay_ch3_f0_0 => (others => '0'),
delay_ch3_f0_1 => (others => '0'),
delay_ch4_f0_0 => (others => '0'),
delay_ch4_f0_1 => (others => '0'),
delay_ch5_f0_0 => (others => '0'),
delay_ch5_f0_1 => (others => '0'),
delay_ch6_f0_0 => (others => '0'),
delay_ch6_f0_1 => (others => '0'),
delay_ch7_f0_0 => (others => '0'),
delay_ch7_f0_1 => (others => '0'),
delay_ch8_f0_0 => (others => '0'),
delay_ch8_f0_1 => (others => '0'),
delay_ch9_f0_0 => (others => '0'),
delay_ch9_f0_1 => (others => '0'),
delay_ch10_f0_0 => (others => '0'),
delay_ch10_f0_1 => (others => '0'),
delay_ch11_f0_0 => (others => '0'),
delay_ch11_f0_1 => (others => '0'),
delay_ch0_f1_0 => (others => '0'),
delay_ch0_f1_1 => (others => '0'),
delay_ch1_f1_0 => (others => '0'),
delay_ch1_f1_1 => (others => '0'),
delay_ch2_f1_0 => (others => '0'),
delay_ch2_f1_1 => (others => '0'),
delay_ch3_f1_0 => (others => '0'),
delay_ch3_f1_1 => (others => '0'),
delay_ch4_f1_0 => (others => '0'),
delay_ch4_f1_1 => (others => '0'),
delay_ch5_f1_0 => (others => '0'),
delay_ch5_f1_1 => (others => '0'),
delay_ch6_f1_0 => (others => '0'),
delay_ch6_f1_1 => (others => '0'),
delay_ch7_f1_0 => (others => '0'),
delay_ch7_f1_1 => (others => '0'),
delay_ch8_f1_0 => (others => '0'),
delay_ch8_f1_1 => (others => '0'),
delay_ch9_f1_0 => (others => '0'),
delay_ch9_f1_1 => (others => '0'),
delay_ch10_f1_0 => (others => '0'),
delay_ch10_f1_1 => (others => '0'),
delay_ch11_f1_0 => (others => '0'),
delay_ch11_f1_1 => (others => '0'),
result_ch0_f0_0 => (others => '0'),
result_ch0_f0_1 => (others => '0'),
result_ch1_f0_0 => (others => '0'),
result_ch1_f0_1 => (others => '0'),
result_ch2_f0_0 => (others => '0'),
result_ch2_f0_1 => (others => '0'),
result_ch3_f0_0 => (others => '0'),
result_ch3_f0_1 => (others => '0'),
result_ch4_f0_0 => (others => '0'),
result_ch4_f0_1 => (others => '0'),
result_ch5_f0_0 => (others => '0'),
result_ch5_f0_1 => (others => '0'),
result_ch6_f0_0 => (others => '0'),
result_ch6_f0_1 => (others => '0'),
result_ch7_f0_0 => (others => '0'),
result_ch7_f0_1 => (others => '0'),
result_ch8_f0_0 => (others => '0'),
result_ch8_f0_1 => (others => '0'),
result_ch9_f0_0 => (others => '0'),
result_ch9_f0_1 => (others => '0'),
result_ch10_f0_0 => (others => '0'),
result_ch10_f0_1 => (others => '0'),
result_ch11_f0_0 => (others => '0'),
result_ch11_f0_1 => (others => '0'),
result_ch0_f1_0 => (others => '0'),
result_ch0_f1_1 => (others => '0'),
result_ch1_f1_0 => (others => '0'),
result_ch1_f1_1 => (others => '0'),
result_ch2_f1_0 => (others => '0'),
result_ch2_f1_1 => (others => '0'),
result_ch3_f1_0 => (others => '0'),
result_ch3_f1_1 => (others => '0'),
result_ch4_f1_0 => (others => '0'),
result_ch4_f1_1 => (others => '0'),
result_ch5_f1_0 => (others => '0'),
result_ch5_f1_1 => (others => '0'),
result_ch6_f1_0 => (others => '0'),
result_ch6_f1_1 => (others => '0'),
result_ch7_f1_0 => (others => '0'),
result_ch7_f1_1 => (others => '0'),
result_ch8_f1_0 => (others => '0'),
result_ch8_f1_1 => (others => '0'),
result_ch9_f1_0 => (others => '0'),
result_ch9_f1_1 => (others => '0'),
result_ch10_f1_0 => (others => '0'),
result_ch10_f1_1 => (others => '0'),
result_ch11_f1_0 => (others => '0'),
result_ch11_f1_1 => (others => '0')
-- results => (others => (others => (others => (others => '0')))),
-- delays => (others => (others => (others => (others => '0'))))
);
----------------------------------------------------------------------------
-- Debugging signals (variables can't be plotted in GTKwave)
----------------------------------------------------------------------------
signal dbg_coef_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
signal dbg_input_s : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
signal dbg_delay1_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
signal dbg_delay2_s : signed(CALC_WIDTH-1 downto 0) := (others => '0');
begin -- behavioural
----------------------------------------------------------------------------
-- Mapping of signals
----------------------------------------------------------------------------
done_p <= r.done;
-- results_p <= r.results;
results_p(0, 0)(0) <= r.result_ch0_f0_0;
results_p(0, 0)(1) <= r.result_ch0_f0_1;
results_p(1, 0)(0) <= r.result_ch1_f0_0;
results_p(1, 0)(1) <= r.result_ch1_f0_1;
results_p(2, 0)(0) <= r.result_ch2_f0_0;
results_p(2, 0)(1) <= r.result_ch2_f0_1;
results_p(3, 0)(0) <= r.result_ch3_f0_0;
results_p(3, 0)(1) <= r.result_ch3_f0_1;
results_p(4, 0)(0) <= r.result_ch4_f0_0;
results_p(4, 0)(1) <= r.result_ch4_f0_1;
results_p(5, 0)(0) <= r.result_ch5_f0_0;
results_p(5, 0)(1) <= r.result_ch5_f0_1;
results_p(6, 0)(0) <= r.result_ch6_f0_0;
results_p(6, 0)(1) <= r.result_ch6_f0_1;
results_p(7, 0)(0) <= r.result_ch7_f0_0;
results_p(7, 0)(1) <= r.result_ch7_f0_1;
results_p(8, 0)(0) <= r.result_ch8_f0_0;
results_p(8, 0)(1) <= r.result_ch8_f0_1;
results_p(9, 0)(0) <= r.result_ch9_f0_0;
results_p(9, 0)(1) <= r.result_ch9_f0_1;
results_p(10, 0)(0) <= r.result_ch10_f0_0;
results_p(10, 0)(1) <= r.result_ch10_f0_1;
results_p(11, 0)(0) <= r.result_ch11_f0_0;
results_p(11, 0)(1) <= r.result_ch11_f0_1;
results_p(0, 1)(0) <= r.result_ch0_f1_0;
results_p(0, 1)(1) <= r.result_ch0_f1_1;
results_p(1, 1)(0) <= r.result_ch1_f1_0;
results_p(1, 1)(1) <= r.result_ch1_f1_1;
results_p(2, 1)(0) <= r.result_ch2_f1_0;
results_p(2, 1)(1) <= r.result_ch2_f1_1;
results_p(3, 1)(0) <= r.result_ch3_f1_0;
results_p(3, 1)(1) <= r.result_ch3_f1_1;
results_p(4, 1)(0) <= r.result_ch4_f1_0;
results_p(4, 1)(1) <= r.result_ch4_f1_1;
results_p(5, 1)(0) <= r.result_ch5_f1_0;
results_p(5, 1)(1) <= r.result_ch5_f1_1;
results_p(6, 1)(0) <= r.result_ch6_f1_0;
results_p(6, 1)(1) <= r.result_ch6_f1_1;
results_p(7, 1)(0) <= r.result_ch7_f1_0;
results_p(7, 1)(1) <= r.result_ch7_f1_1;
results_p(8, 1)(0) <= r.result_ch8_f1_0;
results_p(8, 1)(1) <= r.result_ch8_f1_1;
results_p(9, 1)(0) <= r.result_ch9_f1_0;
results_p(9, 1)(1) <= r.result_ch9_f1_1;
results_p(10, 1)(0) <= r.result_ch10_f1_0;
results_p(10, 1)(1) <= r.result_ch10_f1_1;
results_p(11, 1)(0) <= r.result_ch11_f1_0;
results_p(11, 1)(1) <= r.result_ch11_f1_1;
----------------------------------------------------------------------------
-- Sequential part of FSM
----------------------------------------------------------------------------
seq_proc : process (clk)
begin -- process seq_proc
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Transitions and actions of FSM
----------------------------------------------------------------------------
comb_proc : process (coefs_p, inputs_p, r, start_p)
variable v : goertzel_type;
variable prod1 : signed(2*CALC_WIDTH-1 downto 0) := (others => '0');
variable prod1_sc : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable sum1 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable coef : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable delay1 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable delay2 : signed(CALC_WIDTH-1 downto 0) := (others => '0');
variable input : signed(INPUT_WIDTH-1 downto 0) := (others => '0');
variable channel : natural range CHANNELS-1 downto 0 := 0;
variable frequency : natural range FREQUENCIES-1 downto 0 := 0;
begin -- process comb_proc
v := r;
channel := r.channel;
frequency := r.frequency;
v.done := '0'; -- done is a clock enable and is only
-- high for one period
-- multiplex inputs
coef := signed(coefs_p(r.frequency));
input := inputs_p(r.channel);
-- This does not work with ISE
-- delay1 := r.delays(r.channel, r.frequency)(0);
-- delay2 := r.delays(r.channel, r.frequency)(1);
-- Do it manually instaed:
case frequency is
when 0 =>
case channel is
when 0 =>
delay1 := r.delay_ch0_f0_0;
delay2 := r.delay_ch0_f0_1;
when 1 =>
delay1 := r.delay_ch1_f0_0;
delay2 := r.delay_ch1_f0_1;
when 2 =>
delay1 := r.delay_ch2_f0_0;
delay2 := r.delay_ch2_f0_1;
when 3 =>
delay1 := r.delay_ch3_f0_0;
delay2 := r.delay_ch3_f0_1;
when 4 =>
delay1 := r.delay_ch4_f0_0;
delay2 := r.delay_ch4_f0_1;
when 5 =>
delay1 := r.delay_ch5_f0_0;
delay2 := r.delay_ch5_f0_1;
when 6 =>
delay1 := r.delay_ch6_f0_0;
delay2 := r.delay_ch6_f0_1;
when 7 =>
delay1 := r.delay_ch7_f0_0;
delay2 := r.delay_ch7_f0_1;
when 8 =>
delay1 := r.delay_ch8_f0_0;
delay2 := r.delay_ch8_f0_1;
when 9 =>
delay1 := r.delay_ch9_f0_0;
delay2 := r.delay_ch9_f0_1;
when 10 =>
delay1 := r.delay_ch10_f0_0;
delay2 := r.delay_ch10_f0_1;
when 11 =>
delay1 := r.delay_ch11_f0_0;
delay2 := r.delay_ch11_f0_1;
when others => null;
end case;
when 1 =>
case channel is
when 0 =>
delay1 := r.delay_ch0_f1_0;
delay2 := r.delay_ch0_f1_1;
when 1 =>
delay1 := r.delay_ch1_f1_0;
delay2 := r.delay_ch1_f1_1;
when 2 =>
delay1 := r.delay_ch2_f1_0;
delay2 := r.delay_ch2_f1_1;
when 3 =>
delay1 := r.delay_ch3_f1_0;
delay2 := r.delay_ch3_f1_1;
when 4 =>
delay1 := r.delay_ch4_f1_0;
delay2 := r.delay_ch4_f1_1;
when 5 =>
delay1 := r.delay_ch5_f1_0;
delay2 := r.delay_ch5_f1_1;
when 6 =>
delay1 := r.delay_ch6_f1_0;
delay2 := r.delay_ch6_f1_1;
when 7 =>
delay1 := r.delay_ch7_f1_0;
delay2 := r.delay_ch7_f1_1;
when 8 =>
delay1 := r.delay_ch8_f1_0;
delay2 := r.delay_ch8_f1_1;
when 9 =>
delay1 := r.delay_ch9_f1_0;
delay2 := r.delay_ch9_f1_1;
when 10 =>
delay1 := r.delay_ch10_f1_0;
delay2 := r.delay_ch10_f1_1;
when 11 =>
delay1 := r.delay_ch11_f1_0;
delay2 := r.delay_ch11_f1_1;
when others => null;
end case;
when others => null;
end case;
-- debug signals
dbg_coef_s <= coef;
dbg_input_s <= input;
dbg_delay1_s <= delay1;
dbg_delay2_s <= delay2;
-- iterate channels and frquencies
case r.state is
when IDLE =>
if start_p = '1' then
v.state := CALC;
if r.sample_count = SAMPLES-1 then
v.sample_count := 0;
-- one packet of SAMPLES samples done, store results of current packet
-- v.results := v.delays;
v.result_ch0_f0_0 := v.delay_ch0_f0_0;
v.result_ch0_f0_1 := v.delay_ch0_f0_1;
v.result_ch1_f0_0 := v.delay_ch1_f0_0;
v.result_ch1_f0_1 := v.delay_ch1_f0_1;
v.result_ch2_f0_0 := v.delay_ch2_f0_0;
v.result_ch2_f0_1 := v.delay_ch2_f0_1;
v.result_ch3_f0_0 := v.delay_ch3_f0_0;
v.result_ch3_f0_1 := v.delay_ch3_f0_1;
v.result_ch4_f0_0 := v.delay_ch4_f0_0;
v.result_ch4_f0_1 := v.delay_ch4_f0_1;
v.result_ch5_f0_0 := v.delay_ch5_f0_0;
v.result_ch5_f0_1 := v.delay_ch5_f0_1;
v.result_ch6_f0_0 := v.delay_ch6_f0_0;
v.result_ch6_f0_1 := v.delay_ch6_f0_1;
v.result_ch7_f0_0 := v.delay_ch7_f0_0;
v.result_ch7_f0_1 := v.delay_ch7_f0_1;
v.result_ch8_f0_0 := v.delay_ch8_f0_0;
v.result_ch8_f0_1 := v.delay_ch8_f0_1;
v.result_ch9_f0_0 := v.delay_ch9_f0_0;
v.result_ch9_f0_1 := v.delay_ch9_f0_1;
v.result_ch10_f0_0 := v.delay_ch10_f0_0;
v.result_ch10_f0_1 := v.delay_ch10_f0_1;
v.result_ch11_f0_0 := v.delay_ch11_f0_0;
v.result_ch11_f0_1 := v.delay_ch11_f0_1;
v.result_ch0_f1_0 := v.delay_ch0_f1_0;
v.result_ch0_f1_1 := v.delay_ch0_f1_1;
v.result_ch1_f1_0 := v.delay_ch1_f1_0;
v.result_ch1_f1_1 := v.delay_ch1_f1_1;
v.result_ch2_f1_0 := v.delay_ch2_f1_0;
v.result_ch2_f1_1 := v.delay_ch2_f1_1;
v.result_ch3_f1_0 := v.delay_ch3_f1_0;
v.result_ch3_f1_1 := v.delay_ch3_f1_1;
v.result_ch4_f1_0 := v.delay_ch4_f1_0;
v.result_ch4_f1_1 := v.delay_ch4_f1_1;
v.result_ch5_f1_0 := v.delay_ch5_f1_0;
v.result_ch5_f1_1 := v.delay_ch5_f1_1;
v.result_ch6_f1_0 := v.delay_ch6_f1_0;
v.result_ch6_f1_1 := v.delay_ch6_f1_1;
v.result_ch7_f1_0 := v.delay_ch7_f1_0;
v.result_ch7_f1_1 := v.delay_ch7_f1_1;
v.result_ch8_f1_0 := v.delay_ch8_f1_0;
v.result_ch8_f1_1 := v.delay_ch8_f1_1;
v.result_ch9_f1_0 := v.delay_ch9_f1_0;
v.result_ch9_f1_1 := v.delay_ch9_f1_1;
v.result_ch10_f1_0 := v.delay_ch10_f1_0;
v.result_ch10_f1_1 := v.delay_ch10_f1_1;
v.result_ch11_f1_0 := v.delay_ch11_f1_0;
v.result_ch11_f1_1 := v.delay_ch11_f1_1;
v.done := '1';
-- reset all delay registers
-- v.delays := (others => (others => (others => (others => '0'))));
v.delay_ch0_f0_0 := (others => '0');
v.delay_ch0_f0_1 := (others => '0');
v.delay_ch1_f0_0 := (others => '0');
v.delay_ch1_f0_1 := (others => '0');
v.delay_ch2_f0_0 := (others => '0');
v.delay_ch2_f0_1 := (others => '0');
v.delay_ch3_f0_0 := (others => '0');
v.delay_ch3_f0_1 := (others => '0');
v.delay_ch4_f0_0 := (others => '0');
v.delay_ch4_f0_1 := (others => '0');
v.delay_ch5_f0_0 := (others => '0');
v.delay_ch5_f0_1 := (others => '0');
v.delay_ch6_f0_0 := (others => '0');
v.delay_ch6_f0_1 := (others => '0');
v.delay_ch7_f0_0 := (others => '0');
v.delay_ch7_f0_1 := (others => '0');
v.delay_ch8_f0_0 := (others => '0');
v.delay_ch8_f0_1 := (others => '0');
v.delay_ch9_f0_0 := (others => '0');
v.delay_ch9_f0_1 := (others => '0');
v.delay_ch10_f0_0 := (others => '0');
v.delay_ch10_f0_1 := (others => '0');
v.delay_ch11_f0_0 := (others => '0');
v.delay_ch11_f0_1 := (others => '0');
v.delay_ch0_f1_0 := (others => '0');
v.delay_ch0_f1_1 := (others => '0');
v.delay_ch1_f1_0 := (others => '0');
v.delay_ch1_f1_1 := (others => '0');
v.delay_ch2_f1_0 := (others => '0');
v.delay_ch2_f1_1 := (others => '0');
v.delay_ch3_f1_0 := (others => '0');
v.delay_ch3_f1_1 := (others => '0');
v.delay_ch4_f1_0 := (others => '0');
v.delay_ch4_f1_1 := (others => '0');
v.delay_ch5_f1_0 := (others => '0');
v.delay_ch5_f1_1 := (others => '0');
v.delay_ch6_f1_0 := (others => '0');
v.delay_ch6_f1_1 := (others => '0');
v.delay_ch7_f1_0 := (others => '0');
v.delay_ch7_f1_1 := (others => '0');
v.delay_ch8_f1_0 := (others => '0');
v.delay_ch8_f1_1 := (others => '0');
v.delay_ch9_f1_0 := (others => '0');
v.delay_ch9_f1_1 := (others => '0');
v.delay_ch10_f1_0 := (others => '0');
v.delay_ch10_f1_1 := (others => '0');
v.delay_ch11_f1_0 := (others => '0');
v.delay_ch11_f1_1 := (others => '0');
else
v.sample_count := r.sample_count + 1;
end if;
end if;
when CALC =>
-- calculating, only use the multiplexed signals
prod1 := delay1 * coef;
prod1_sc := prod1((Q + CALC_WIDTH - 1) downto Q);
-- TODO detect overflow
sum1 := input + prod1_sc - delay2;
delay2 := delay1;
delay1 := sum1;
-- advance frequency and channel
if r.channel = CHANNELS-1 then
v.channel := 0;
if r.frequency = FREQUENCIES-1 then
v.frequency := 0;
v.state := IDLE;
else
v.frequency := r.frequency + 1;
end if;
else
v.channel := r.channel + 1;
end if;
end case;
-- multiplex output
-- This crashes lame ISE
-- v.delays(r.channel, r.frequency)(0) := delay1;
-- v.delays(r.channel, r.frequency)(1) := delay2;
case frequency is
when 0 =>
case channel is
when 0 =>
v.delay_ch0_f0_0 := delay1;
v.delay_ch0_f0_1 := delay2;
when 1 =>
v.delay_ch1_f0_0 := delay1;
v.delay_ch1_f0_1 := delay2;
when 2 =>
v.delay_ch2_f0_0 := delay1;
v.delay_ch2_f0_1 := delay2;
when 3 =>
v.delay_ch3_f0_0 := delay1;
v.delay_ch3_f0_1 := delay2;
when 4 =>
v.delay_ch4_f0_0 := delay1;
v.delay_ch4_f0_1 := delay2;
when 5 =>
v.delay_ch5_f0_0 := delay1;
v.delay_ch5_f0_1 := delay2;
when 6 =>
v.delay_ch6_f0_0 := delay1;
v.delay_ch6_f0_1 := delay2;
when 7 =>
v.delay_ch7_f0_0 := delay1;
v.delay_ch7_f0_1 := delay2;
when 8 =>
v.delay_ch8_f0_0 := delay1;
v.delay_ch8_f0_1 := delay2;
when 9 =>
v.delay_ch9_f0_0 := delay1;
v.delay_ch9_f0_1 := delay2;
when 10 =>
v.delay_ch10_f0_0 := delay1;
v.delay_ch10_f0_1 := delay2;
when 11 =>
v.delay_ch11_f0_0 := delay1;
v.delay_ch11_f0_1 := delay2;
when others => null;
end case;
when 1 =>
case channel is
when 0 =>
v.delay_ch0_f1_0 := delay1;
v.delay_ch0_f1_1 := delay2;
when 1 =>
v.delay_ch1_f1_0 := delay1;
v.delay_ch1_f1_1 := delay2;
when 2 =>
v.delay_ch2_f1_0 := delay1;
v.delay_ch2_f1_1 := delay2;
when 3 =>
v.delay_ch3_f1_0 := delay1;
v.delay_ch3_f1_1 := delay2;
when 4 =>
v.delay_ch4_f1_0 := delay1;
v.delay_ch4_f1_1 := delay2;
when 5 =>
v.delay_ch5_f1_0 := delay1;
v.delay_ch5_f1_1 := delay2;
when 6 =>
v.delay_ch6_f1_0 := delay1;
v.delay_ch6_f1_1 := delay2;
when 7 =>
v.delay_ch7_f1_0 := delay1;
v.delay_ch7_f1_1 := delay2;
when 8 =>
v.delay_ch8_f1_0 := delay1;
v.delay_ch8_f1_1 := delay2;
when 9 =>
v.delay_ch9_f1_0 := delay1;
v.delay_ch9_f1_1 := delay2;
when 10 =>
v.delay_ch10_f1_0 := delay1;
v.delay_ch10_f1_1 := delay2;
when 11 =>
v.delay_ch11_f1_0 := delay1;
v.delay_ch11_f1_1 := delay2;
when others => null;
end case;
when others => null;
end case;
rin <= v;
end process comb_proc;
end behavioural;
| bsd-3-clause | d8947285ef45b94d6e5bf56dbf2f0247 | 0.458427 | 2.914415 | false | false | false | false |
loa-org/loa-hdl | modules/hdlc/tb/hdlc_busmaster_tb.vhd | 1 | 9,111 | -------------------------------------------------------------------------------
-- Title : Testbench for design HDLC Busmaster
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Some Testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.hdlc_pkg.all;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use std.textio.all;
-------------------------------------------------------------------------------
entity hdlc_busmaster_tb is
end entity hdlc_busmaster_tb;
-------------------------------------------------------------------------------
architecture behavourial of hdlc_busmaster_tb is
-- component ports
signal tb_to_enc : hdlc_enc_in_type := (data => (others => '1'), enable => '0');
signal enc_to_dec : hdlc_enc_out_type := (data => (others => '0'), enable => '0');
signal dec_to_busmaster : hdlc_dec_out_type := (data => (others => '0'), enable => '0');
signal bus_to_master : busmaster_in_type := (data => (others => '0'));
signal master_to_bus : busmaster_out_type := (addr => (others => '0'), data => (others => '0'), re => '0', we => '0');
signal busmaster_to_enc2 : hdlc_enc_in_type := (data => (others => '0'), enable => '0');
signal enc_busy : std_logic := '0';
-- clock
signal Clk : std_logic := '1';
signal reset : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
DUT_enc : work.hdlc_pkg.hdlc_enc
port map(
din_p => tb_to_enc,
dout_p => enc_to_dec,
busy_p => enc_busy,
clk => clk);
DUT_dec : work.hdlc_pkg.hdlc_dec
port map(
din_p => enc_to_dec,
dout_p => dec_to_busmaster,
clk => clk);
DUT_bus_mst : work.hdlc_pkg.hdlc_busmaster
port map(
din_p => dec_to_busmaster,
dout_p => busmaster_to_enc2,
bus_o => master_to_bus,
bus_i => bus_to_master,
clk => clk);
DUT_reg : work.reg_file_pkg.peripheral_register
generic map(
BASE_ADDRESS => 16#0080#)
port map(
dout_p => open,
din_p => x"127d",
bus_o => bus_to_master,
bus_i => master_to_bus,
reset => reset,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
reset <= '0' after 20 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until rising_edge(Clk);
wait until rising_edge(Clk);
wait until rising_edge(Clk);
wait until rising_edge(Clk);
-- read with good crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"10";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"7e";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"2B"; -- crc correct
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read with bad crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"10";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"2c"; -- crc incorrect
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- write with good crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"20";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"0f";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"0f";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"81"; -- good crc
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- write with bad crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"20";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"0f";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"0f";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80"; -- good crc
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
-- read with good crc
tb_to_enc.data <= "1" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"10";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"00";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"80";
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
tb_to_enc.data <= "0" & x"2B"; -- crc correct
tb_to_enc.enable <= '1';
wait until Clk = '1';
tb_to_enc.enable <= '0';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait until Clk = '1';
wait for 10 ms;
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause | 935a02bbdcda6dadca563fd6d638a74f | 0.47942 | 3.043086 | false | false | false | false |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_3/Uart_working/Circuit17.vhd | 2 | 2,966 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Circuit17 is
Port ( TE,ROSEL: in STD_LOGIC;
G1 : in STD_LOGIC;
G2 : in STD_LOGIC;
G3 : in STD_LOGIC;
G6 : in STD_LOGIC;
G7 : in STD_LOGIC;
G22 : out STD_LOGIC;
G23 : out STD_LOGIC;
GEX: out STD_LOGIC);
end Circuit17;
architecture Behavioral of Circuit17 is
signal delay1,delay2 : std_logic;
signal G10,G11,G16,G19,G6t: STD_LOGIC;
signal sel1,G23t: std_logic;
attribute KEEP : string;
attribute KEEP of G10 : signal is "true";
attribute KEEP of G11 : signal is "true";
attribute KEEP of G16 : signal is "true";
attribute KEEP of G19 : signal is "true";
attribute KEEP of G6t : signal is "true";
--attribute KEEP of delay1 : signal is "true";
--attribute KEEP of delay2 : signal is "true";
attribute KEEP of G23t : signal is "true";
attribute INIT : string;
attribute INIT of G10_lut : label is "7";
attribute INIT of G11_lut : label is "7";
attribute INIT of G16_lut : label is "7";
attribute INIT of G19_lut : label is "7";
attribute INIT of G22_lut : label is "7";
attribute INIT of G23_lut : label is "7";
--attribute INIT of tr1_lut : label is "3";
--attribute INIT of tr2_lut : label is "3";
attribute LOC : string;
attribute LOC of G10_lut : label is "SLICE_X18Y14";
attribute LOC of G11_lut : label is "SLICE_X19Y14";
attribute LOC of G16_lut : label is "SLICE_X20Y14";
attribute LOC of G19_lut : label is "SLICE_X21Y14";
attribute LOC of G22_lut : label is "SLICE_X22Y14";
attribute LOC of G23_lut : label is "SLICE_X23Y14";
--attribute LOC of tr2_lut : label is "SLICE_X23Y14";
--attribute LOC of tr1_lut : label is "SLICE_X22Y14";
begin
sel1<= TE;
------- MUX BEFORE G10 (INPUT TO G10gat)---
process(sel1)
Begin
Case sel1 is
when '0' => G6t<= G6;
when '1' => G6t<= G23t;
When others=> G6t <= G6;
end case;
end process;
--------------------------
G10_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G1,I1 => G3,O => G10 );
G11_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G3,I1 => G6t,O => G11 );
G16_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G2,I1 => G11,O => G16 );
G19_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G11,I1 => G7,O => G19 );
G22_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G16,I1 => G10,O => G22 );
G23_lut: LUT2
generic map (INIT => X"7")
port map( I0 => G19,I1 => G16,O => G23t );
---- TROJAN (INVERTER GATE) ----
--Tr1_lut: LUT2
-- generic map (INIT => X"3")
-- port map( I0 => TE,I1 => G23t,O => delay1);
--Tr2_lut: LUT2
-- generic map (INIT => X"3")
-- port map( I0 => TE,I1 => delay1,O => delay2 );
-----------------------------------
G23<= G23t;
GEX<= G23t;
end Behavioral;
| mit | dff392cc573311d6b98a0681e34b4d2a | 0.577546 | 2.846449 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/synth/system_vga_sync_reset_0_0.vhd | 3 | 4,935 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_reset:1.0
-- IP Revision: 25
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_reset_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_reset_0_0;
ARCHITECTURE system_vga_sync_reset_0_0_arch OF system_vga_sync_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_reset IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "vga_sync_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_reset_0_0_arch : ARCHITECTURE IS "system_vga_sync_reset_0_0,vga_sync_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "system_vga_sync_reset_0_0,vga_sync_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync_reset,x_ipVersion=1.0,x_ipCoreRevision=25,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_reset
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_reset_0_0_arch;
| mit | 90a9a70ffe4120f20cf7fe6e9a5286eb | 0.70618 | 3.64745 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/sim/system_vga_buffer_0_0.vhd | 1 | 4,004 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 12
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
| mit | d7485b17606c8e93354140c43199a4c5 | 0.697303 | 3.663312 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0_1/system_rgb888_to_rgb565_0_0_sim_netlist.vhdl | 1 | 2,187 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb888_to_rgb565_0_0 -prefix
-- system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_rgb565_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_rgb565_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_rgb565_0_0 : entity is "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_rgb565_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_rgb565_0_0 : entity is "rgb888_to_rgb565,Vivado 2016.4";
end system_rgb888_to_rgb565_0_0;
architecture STRUCTURE of system_rgb888_to_rgb565_0_0 is
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 23 downto 0 );
begin
\^rgb_888\(23 downto 19) <= rgb_888(23 downto 19);
\^rgb_888\(15 downto 10) <= rgb_888(15 downto 10);
\^rgb_888\(7 downto 3) <= rgb_888(7 downto 3);
rgb_565(15 downto 11) <= \^rgb_888\(23 downto 19);
rgb_565(10 downto 5) <= \^rgb_888\(15 downto 10);
rgb_565(4 downto 0) <= \^rgb_888\(7 downto 3);
end STRUCTURE;
| mit | ebdb6ee4434f94f82590dc406c15afd5 | 0.647462 | 3.449527 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd | 1 | 8,144 | -- niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 34;
FIFO_DEPTH : integer := 2;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 0;
USE_MEMORY_BLOCKS : integer := 0;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(33 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_data : out std_logic_vector(33 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_endofpacket : in std_logic := '0';
in_error : in std_logic := '0';
in_startofpacket : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_endofpacket : out std_logic;
out_error : out std_logic;
out_startofpacket : out std_logic
);
end entity niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo;
architecture rtl of niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(33 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo
| apache-2.0 | 838f550b95d77b257199c18e0ecd38af | 0.431483 | 3.904123 | false | false | false | false |
olofk/libstorage | rtl/vhdl/generic/dpram_generic.vhd | 1 | 2,065 | --
-- Dual port RAM. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library libstorage_1;
use libstorage_1.libstorage_pkg.all;
entity dpram_generic is
generic (
type data_type;
DEPTH : positive);
port (
clk : in std_ulogic;
rd_en_i : in std_ulogic;
rd_addr_i : in unsigned(clog2(DEPTH)-1 downto 0);
rd_data_o : out data_type;
wr_en_i : in std_ulogic;
wr_addr_i : in unsigned(clog2(DEPTH)-1 downto 0);
wr_data_i : in data_type);
end entity dpram_generic;
architecture rtl of dpram_generic is
type t_mem is array (natural range <>) of data_type;
signal mem : t_mem(0 to DEPTH-1);
signal wr_data_i_r : data_type;
begin
assert is_pow2(DEPTH) report "DEPTH must be 2^n" severity failure;
p_main : process(clk)
begin
if rising_edge(clk) then
if wr_en_i then
mem(to_integer(wr_addr_i)) <= wr_data_i;
end if;
if rd_en_i then
wr_data_i_r <= wr_data_i;
rd_data_o <= mem(to_integer(rd_addr_i));
end if;
if (rd_addr_i = wr_addr_i) and (rd_en_i and wr_en_i) = '1' then
rd_data_o <= wr_data_i_r;
end if;
end if;
end process;
end architecture rtl;
| isc | 39e26f7ca14f5ab986a74e3659a05814 | 0.670218 | 3.267405 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ipshared/1d19/hdl/util_vector_logic.vhd | 7 | 6,359 | -------------------------------------------------------------------------------
-- $Id: util_vector_logic.vhd,v 2.0 2014/10/03 04:52:57 abq_ip Exp $
-------------------------------------------------------------------------------
-- util_vector_logic.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: util_vector_logic.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- util_vector_logic.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/10/03 04:52:57 $
--
-- History:
-- goran 2003-06-06 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity util_vector_logic is
generic (
C_OPERATION : string := "and";
C_SIZE : integer := 8
);
port (
Op1 : in std_logic_vector(C_SIZE-1 downto 0);
Op2 : in std_logic_vector(C_SIZE-1 downto 0);
Res : out std_logic_vector(C_SIZE-1 downto 0)
);
end util_vector_logic;
architecture IMP of util_vector_logic is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
function LowerCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := LowerCase_Char(s(I));
end loop; -- I
return res;
end function LowerCase_String;
constant C_Oper : string := LowerCase_String(C_OPERATION);
begin
Use_AND: if (C_Oper = "and") generate
res <= Op1 and Op2;
end generate Use_AND;
Use_OR: if (C_Oper = "or") generate
res <= Op1 or Op2;
end generate Use_OR;
Use_XOR: if (C_Oper = "xor") generate
res <= Op1 xor Op2;
end generate Use_XOR;
Use_NOT: if (C_Oper = "not") generate
res <= NOT Op1;
end generate Use_NOT;
end IMP;
| mit | 1fe53be2c752cb07bbcc1c319f2ff48b | 0.434345 | 4.355479 | false | false | false | false |
pgavin/carpe | hdl/cpu/or1knd/i5/cpu_or1knd_i5_pipe-rtl.vhdl | 1 | 14,805 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
library tech;
-- pragma translate_off
library sim;
-- pragma translate_on
use work.cpu_bpb_pkg.all;
use work.cpu_btb_pkg.all;
use work.cpu_or1knd_i5_config_pkg.all;
use work.cpu_or1knd_i5_pipe_pkg.all;
architecture rtl of cpu_or1knd_i5_pipe is
signal cpu_or1knd_i5_pipe_ctrl_in_misc : cpu_or1knd_i5_pipe_ctrl_in_misc_type;
signal cpu_or1knd_i5_pipe_ctrl_out_misc : cpu_or1knd_i5_pipe_ctrl_out_misc_type;
signal cpu_or1knd_i5_pipe_dp_in_ctrl : cpu_or1knd_i5_pipe_dp_in_ctrl_type;
signal cpu_or1knd_i5_pipe_dp_out_ctrl : cpu_or1knd_i5_pipe_dp_out_ctrl_type;
signal cpu_or1knd_i5_pipe_dp_in_misc : cpu_or1knd_i5_pipe_dp_in_misc_type;
signal cpu_or1knd_i5_pipe_dp_out_misc : cpu_or1knd_i5_pipe_dp_out_misc_type;
signal cpu_bpb_ctrl_in : cpu_bpb_ctrl_in_type;
signal cpu_bpb_dp_in : cpu_bpb_dp_in_type;
signal cpu_bpb_ctrl_out : cpu_bpb_ctrl_out_type;
signal cpu_bpb_dp_out : cpu_bpb_dp_out_type;
signal cpu_btb_ctrl_in : cpu_btb_ctrl_in_type;
signal cpu_btb_dp_in : cpu_btb_dp_in_type;
signal cpu_btb_ctrl_out : cpu_btb_ctrl_out_type;
signal cpu_btb_dp_out : cpu_btb_dp_out_type;
type comb_type is record
shifter_shift : std_ulogic_vector(or1k_shift_bits downto 0);
m_madd_result : std_ulogic_vector(2*or1k_word_bits-1 downto 0);
end record;
signal c : comb_type;
begin
c.shifter_shift <= '0' & cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src2(or1k_shift_bits-1 downto 0);
bpb : entity work.cpu_bpb(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_bpb_ctrl_in => cpu_bpb_ctrl_in,
cpu_bpb_dp_in => cpu_bpb_dp_in,
cpu_bpb_ctrl_out => cpu_bpb_ctrl_out,
cpu_bpb_dp_out => cpu_bpb_dp_out
);
btb : entity work.cpu_btb(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_btb_ctrl_in => cpu_btb_ctrl_in,
cpu_btb_dp_in => cpu_btb_dp_in,
cpu_btb_ctrl_out => cpu_btb_ctrl_out,
cpu_btb_dp_out => cpu_btb_dp_out
);
ctrl : entity work.cpu_or1knd_i5_pipe_ctrl(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_or1knd_i5_pipe_ctrl_in_misc => cpu_or1knd_i5_pipe_ctrl_in_misc,
cpu_or1knd_i5_pipe_ctrl_out_misc => cpu_or1knd_i5_pipe_ctrl_out_misc,
cpu_or1knd_i5_pipe_dp_in_ctrl => cpu_or1knd_i5_pipe_dp_in_ctrl,
cpu_or1knd_i5_pipe_dp_out_ctrl => cpu_or1knd_i5_pipe_dp_out_ctrl,
cpu_l1mem_inst_ctrl_out => cpu_l1mem_inst_ctrl_out,
cpu_l1mem_inst_ctrl_in => cpu_l1mem_inst_ctrl_in,
cpu_l1mem_data_ctrl_out => cpu_l1mem_data_ctrl_out,
cpu_l1mem_data_ctrl_in => cpu_l1mem_data_ctrl_in,
cpu_or1knd_i5_mmu_inst_ctrl_out_pipe => cpu_or1knd_i5_mmu_inst_ctrl_out_pipe,
cpu_or1knd_i5_mmu_inst_ctrl_in_pipe => cpu_or1knd_i5_mmu_inst_ctrl_in_pipe,
cpu_or1knd_i5_mmu_data_ctrl_out_pipe => cpu_or1knd_i5_mmu_data_ctrl_out_pipe,
cpu_or1knd_i5_mmu_data_ctrl_in_pipe => cpu_or1knd_i5_mmu_data_ctrl_in_pipe,
cpu_bpb_ctrl_in => cpu_bpb_ctrl_in,
cpu_bpb_ctrl_out => cpu_bpb_ctrl_out,
cpu_btb_ctrl_in => cpu_btb_ctrl_in,
cpu_btb_ctrl_out => cpu_btb_ctrl_out
);
dp : entity work.cpu_or1knd_i5_pipe_dp(rtl)
port map (
clk => clk,
cpu_or1knd_i5_pipe_dp_in_ctrl => cpu_or1knd_i5_pipe_dp_in_ctrl,
cpu_or1knd_i5_pipe_dp_out_ctrl => cpu_or1knd_i5_pipe_dp_out_ctrl,
cpu_or1knd_i5_pipe_dp_in_misc => cpu_or1knd_i5_pipe_dp_in_misc,
cpu_or1knd_i5_pipe_dp_out_misc => cpu_or1knd_i5_pipe_dp_out_misc,
cpu_l1mem_inst_dp_out => cpu_l1mem_inst_dp_out,
cpu_l1mem_inst_dp_in => cpu_l1mem_inst_dp_in,
cpu_l1mem_data_dp_out => cpu_l1mem_data_dp_out,
cpu_l1mem_data_dp_in => cpu_l1mem_data_dp_in,
cpu_or1knd_i5_mmu_inst_dp_out_pipe => cpu_or1knd_i5_mmu_inst_dp_out_pipe,
cpu_or1knd_i5_mmu_inst_dp_in_pipe => cpu_or1knd_i5_mmu_inst_dp_in_pipe,
cpu_or1knd_i5_mmu_data_dp_out_pipe => cpu_or1knd_i5_mmu_data_dp_out_pipe,
cpu_or1knd_i5_mmu_data_dp_in_pipe => cpu_or1knd_i5_mmu_data_dp_in_pipe,
cpu_bpb_dp_in => cpu_bpb_dp_in,
cpu_bpb_dp_out => cpu_bpb_dp_out,
cpu_btb_dp_in => cpu_btb_dp_in,
cpu_btb_dp_out => cpu_btb_dp_out
);
addsub : entity tech.addsub(rtl)
generic map (
src_bits => or1k_word_bits
)
port map (
sub => cpu_or1knd_i5_pipe_ctrl_out_misc.e_addsub_sub,
carryin => cpu_or1knd_i5_pipe_ctrl_out_misc.e_addsub_carryin,
src1 => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src1,
src2 => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src2,
result => cpu_or1knd_i5_pipe_dp_in_misc.e_addsub_result,
carryout => cpu_or1knd_i5_pipe_ctrl_in_misc.e_addsub_carryout,
overflow => cpu_or1knd_i5_pipe_ctrl_in_misc.e_addsub_overflow
);
shifter : entity tech.shifter(rtl)
generic map (
src_bits => or1k_word_bits,
shift_bits => or1k_shift_bits
)
port map (
right => cpu_or1knd_i5_pipe_ctrl_out_misc.e_shifter_right,
rot => cpu_or1knd_i5_pipe_ctrl_out_misc.e_shifter_rot,
unsgnd => cpu_or1knd_i5_pipe_ctrl_out_misc.e_shifter_unsgnd,
src => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src1,
shift => c.shifter_shift,
shift_unsgnd => '1',
result => cpu_or1knd_i5_pipe_dp_in_misc.e_shifter_result
);
madd_enable_gen : if cpu_or1knd_i5_madd_enable generate
madd : entity tech.madd_seq(rtl)
generic map (
latency => cpu_or1knd_i5_madd_latency,
src1_bits => or1k_word_bits,
src2_bits => or1k_word_bits
)
port map (
clk => clk,
rstn => rstn,
en => cpu_or1knd_i5_pipe_ctrl_out_misc.e_mul_en,
unsgnd => cpu_or1knd_i5_pipe_ctrl_out_misc.e_mul_unsgnd,
sub => cpu_or1knd_i5_pipe_ctrl_out_misc.e_madd_sub,
acc => cpu_or1knd_i5_pipe_dp_out_misc.e_madd_acc,
src1 => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src1,
src2 => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src2,
valid => cpu_or1knd_i5_pipe_ctrl_in_misc.m_mul_valid,
result => c.m_madd_result,
overflow => cpu_or1knd_i5_pipe_ctrl_in_misc.m_madd_overflow
);
cpu_or1knd_i5_pipe_dp_in_misc.m_mul_result <= c.m_madd_result(or1k_word_bits-1 downto 0);
cpu_or1knd_i5_pipe_dp_in_misc.m_madd_result_hi <= c.m_madd_result(2*or1k_word_bits-1 downto or1k_word_bits);
end generate;
mul_enable_gen : if cpu_or1knd_i5_mul_enable generate
mul : entity tech.mul_trunc_seq(rtl)
generic map (
latency => cpu_or1knd_i5_mul_latency,
src_bits => or1k_word_bits
)
port map (
clk => clk,
rstn => rstn,
en => cpu_or1knd_i5_pipe_ctrl_out_misc.e_mul_en,
unsgnd => cpu_or1knd_i5_pipe_ctrl_out_misc.e_mul_unsgnd,
src1 => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src1,
src2 => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src2,
valid => cpu_or1knd_i5_pipe_ctrl_in_misc.m_mul_valid,
overflow => cpu_or1knd_i5_pipe_ctrl_in_misc.m_mul_overflow,
result => cpu_or1knd_i5_pipe_dp_in_misc.m_mul_result
);
end generate;
div : entity tech.div_seq(rtl)
generic map (
latency => cpu_or1knd_i5_div_latency,
src1_bits => or1k_word_bits,
src2_bits => or1k_word_bits
)
port map (
clk => clk,
rstn => rstn,
en => cpu_or1knd_i5_pipe_ctrl_out_misc.e_div_en,
unsgnd => cpu_or1knd_i5_pipe_ctrl_out_misc.e_div_unsgnd,
src1 => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src1,
src2 => cpu_or1knd_i5_pipe_dp_out_misc.e_alu_src2,
valid => cpu_or1knd_i5_pipe_ctrl_in_misc.m_div_valid,
dbz => cpu_or1knd_i5_pipe_ctrl_in_misc.m_div_dbz,
overflow => cpu_or1knd_i5_pipe_ctrl_in_misc.m_div_overflow,
result => cpu_or1knd_i5_pipe_dp_in_misc.m_div_result
);
regfile : entity tech.syncram_2r1w(rtl)
generic map (
addr_bits => or1k_rfaddr_bits,
data_bits => or1k_word_bits,
write_first => true
)
port map (
clk => clk,
we => cpu_or1knd_i5_pipe_ctrl_out_misc.regfile_we,
waddr => cpu_or1knd_i5_pipe_dp_out_misc.regfile_waddr,
wdata => cpu_or1knd_i5_pipe_dp_out_misc.regfile_wdata,
re1 => cpu_or1knd_i5_pipe_ctrl_out_misc.regfile_re1,
raddr1 => cpu_or1knd_i5_pipe_dp_out_misc.regfile_raddr1,
rdata1 => cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata1,
re2 => cpu_or1knd_i5_pipe_ctrl_out_misc.regfile_re2,
raddr2 => cpu_or1knd_i5_pipe_dp_out_misc.regfile_raddr2,
rdata2 => cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata2
);
-- pragma translate_off
regfile_we_watch : block
signal watch_data : std_ulogic_vector(0 downto 0);
begin
watch_data <= (0 => cpu_or1knd_i5_pipe_ctrl_out_misc.regfile_we);
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_we",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
regfile_waddr_watch : block
signal watch_data : std_ulogic_vector(cpu_or1knd_i5_pipe_dp_out_misc.regfile_waddr'length-1 downto 0);
begin
watch_data <= cpu_or1knd_i5_pipe_dp_out_misc.regfile_waddr;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_waddr",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
regfile_wdata_watch : block
signal watch_data : std_ulogic_vector(cpu_or1knd_i5_pipe_dp_out_misc.regfile_wdata'length-1 downto 0);
begin
watch_data <= cpu_or1knd_i5_pipe_dp_out_misc.regfile_wdata;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_wdata",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
regfile_re1_watch : block
signal watch_data : std_ulogic_vector(0 downto 0);
begin
watch_data <= (0 => cpu_or1knd_i5_pipe_ctrl_out_misc.regfile_re1);
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_re1",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
regfile_raddr1_watch : block
signal watch_data : std_ulogic_vector(cpu_or1knd_i5_pipe_dp_out_misc.regfile_raddr1'length-1 downto 0);
begin
watch_data <= cpu_or1knd_i5_pipe_dp_out_misc.regfile_raddr1;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_raddr1",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
regfile_rdata1_watch : block
signal watch_data : std_ulogic_vector(cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata1'length-1 downto 0);
begin
watch_data <= cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata1;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_rdata1",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
regfile_re2_watch : block
signal watch_data : std_ulogic_vector(0 downto 0);
begin
watch_data <= (0 => cpu_or1knd_i5_pipe_ctrl_out_misc.regfile_re2);
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_re2",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
regfile_raddr2_watch : block
signal watch_data : std_ulogic_vector(cpu_or1knd_i5_pipe_dp_out_misc.regfile_raddr2'length-1 downto 0);
begin
watch_data <= cpu_or1knd_i5_pipe_dp_out_misc.regfile_raddr2;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_raddr2",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
regfile_rdata2_watch : block
signal watch_data : std_ulogic_vector(cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata2'length-1 downto 0);
begin
watch_data <= cpu_or1knd_i5_pipe_dp_in_misc.regfile_rdata2;
inst : entity sim.monitor_sync_watch(behav)
generic map (
instance => cpu_or1knd_i5_pipe'path_name,
name => "regfile_rdata2",
data_bits => watch_data'length
)
port map (
clk => clk,
data => watch_data
);
end block;
-- pragma translate_on
end;
| apache-2.0 | 7a9de729001342e422f22a74840b8fed | 0.57663 | 2.89556 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_sync_ref/vga_sync_ref.srcs/sources_1/new/vga_sync.vhd | 6 | 3,090 | ----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync_ref - Behavioral
-- Description: Create a sync signal for displaying pixel data sync with a reference timing signal
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync_ref is
generic(
DELAY : integer := 2;
H_SIZE : integer := 640;
H_SYNC_SIZE : integer := 144;
V_SIZE : integer := 480
);
port(
clk : in std_logic;
rst : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
start : out std_logic;
active : out std_logic;
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync_ref;
architecture Structural of vga_sync_ref is
-- sync counter
signal state : std_logic_vector(1 downto 0) := "00";
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
signal counter : integer := 0;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '0' or vsync = '1' then
active <= '0';
v_count_reg <= (others => '0');
h_count_reg <= (others => '0');
state <= "00";
counter <= 0;
start <= '0';
else
if state = "00" then
if counter = (17 * (H_SIZE + H_SYNC_SIZE)) + H_SYNC_SIZE + DELAY - 1 then
state <= "01";
counter <= 0;
active <= '1';
start <= '1';
else
counter <= counter + 1;
end if;
elsif state = "01" then
start <= '0';
h_count_reg <= h_count_reg + 1;
if counter = H_SIZE - 1 then
state <= "10";
counter <= 0;
active <= '0';
else
counter <= counter + 1;
end if;
elsif state = "10" then
if counter = H_SYNC_SIZE - 1 then
h_count_reg <= (others => '0');
counter <= 0;
if v_count_reg = V_SIZE - 1 then
state <= "11";
else
v_count_reg <= v_count_reg + 1;
state <= "01";
active <= '1';
end if;
else
counter <= counter + 1;
end if;
end if;
end if;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end if;
end process;
end Structural;
| mit | 3efa0360963de50657db0330d80b8a2a | 0.388026 | 4.63964 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/sim/system_vga_buffer_0_0.vhd | 4 | 4,004 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
| mit | 41425c84a21fc210602b9813ba7c2cfe | 0.697303 | 3.663312 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 3,134 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Thu Jun 01 11:34:27 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
clk_100 : in STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync_0 : in STD_LOGIC;
hsync_1 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
ready_0 : out STD_LOGIC;
ready_1 : out STD_LOGIC;
reset : in STD_LOGIC;
sioc_0 : out STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
siod_1 : inout STD_LOGIC;
vsync_0 : in STD_LOGIC;
vsync_1 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
clk_100 : in STD_LOGIC;
sioc_0 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reset : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
hsync_0 : in STD_LOGIC;
vsync_0 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC;
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync_1 : in STD_LOGIC;
vsync_1 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_1 : inout STD_LOGIC;
ready_1 : out STD_LOGIC;
ready_0 : out STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
clk_100 => clk_100,
data_0(7 downto 0) => data_0(7 downto 0),
data_1(7 downto 0) => data_1(7 downto 0),
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync_0 => hsync_0,
hsync_1 => hsync_1,
pclk_0 => pclk_0,
pclk_1 => pclk_1,
ready_0 => ready_0,
ready_1 => ready_1,
reset => reset,
sioc_0 => sioc_0,
sioc_1 => sioc_1,
siod_0 => siod_0,
siod_1 => siod_1,
vsync_0 => vsync_0,
vsync_1 => vsync_1,
xclk_0 => xclk_0,
xclk_1 => xclk_1
);
end STRUCTURE;
| mit | 79481831fdd2e1dd5eb939ba28b83653 | 0.558073 | 3.194699 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/system_vga_overlay_0_0_sim_netlist.vhdl | 1 | 21,910 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:39:44 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_overlay_0_0 -prefix
-- system_vga_overlay_0_0_ system_vga_overlay_0_0_sim_netlist.vhdl
-- Design : system_vga_overlay_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_overlay_0_0_vga_overlay is
port (
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 20 downto 0 );
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 20 downto 0 )
);
end system_vga_overlay_0_0_vga_overlay;
architecture STRUCTURE of system_vga_overlay_0_0_vga_overlay is
signal b_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal b_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal g_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal g_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal r_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal r_1 : STD_LOGIC_VECTOR ( 6 downto 0 );
signal rgb0 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb00_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rgb01_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rgb[11]_i_2_n_0\ : STD_LOGIC;
signal \rgb[11]_i_3_n_0\ : STD_LOGIC;
signal \rgb[11]_i_4_n_0\ : STD_LOGIC;
signal \rgb[11]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[19]_i_2_n_0\ : STD_LOGIC;
signal \rgb[19]_i_3_n_0\ : STD_LOGIC;
signal \rgb[19]_i_4_n_0\ : STD_LOGIC;
signal \rgb[19]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[3]_i_2_n_0\ : STD_LOGIC;
signal \rgb[3]_i_3_n_0\ : STD_LOGIC;
signal \rgb[3]_i_4_n_0\ : STD_LOGIC;
signal \rgb[3]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rgb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rgb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_rgb_reg[15]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[15]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_reg[23]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[23]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_rgb_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_rgb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\b_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(0),
Q => b_0(0),
R => '0'
);
\b_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(1),
Q => b_0(1),
R => '0'
);
\b_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(2),
Q => b_0(2),
R => '0'
);
\b_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(3),
Q => b_0(3),
R => '0'
);
\b_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(4),
Q => b_0(4),
R => '0'
);
\b_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(5),
Q => b_0(5),
R => '0'
);
\b_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(6),
Q => b_0(6),
R => '0'
);
\b_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(0),
Q => b_1(0),
R => '0'
);
\b_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(1),
Q => b_1(1),
R => '0'
);
\b_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(2),
Q => b_1(2),
R => '0'
);
\b_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(3),
Q => b_1(3),
R => '0'
);
\b_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(4),
Q => b_1(4),
R => '0'
);
\b_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(5),
Q => b_1(5),
R => '0'
);
\b_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(6),
Q => b_1(6),
R => '0'
);
\g_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(7),
Q => g_0(0),
R => '0'
);
\g_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(8),
Q => g_0(1),
R => '0'
);
\g_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(9),
Q => g_0(2),
R => '0'
);
\g_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(10),
Q => g_0(3),
R => '0'
);
\g_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(11),
Q => g_0(4),
R => '0'
);
\g_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(12),
Q => g_0(5),
R => '0'
);
\g_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(13),
Q => g_0(6),
R => '0'
);
\g_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(7),
Q => g_1(0),
R => '0'
);
\g_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(8),
Q => g_1(1),
R => '0'
);
\g_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(9),
Q => g_1(2),
R => '0'
);
\g_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(10),
Q => g_1(3),
R => '0'
);
\g_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(11),
Q => g_1(4),
R => '0'
);
\g_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(12),
Q => g_1(5),
R => '0'
);
\g_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(13),
Q => g_1(6),
R => '0'
);
\r_0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(14),
Q => r_0(0),
R => '0'
);
\r_0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(15),
Q => r_0(1),
R => '0'
);
\r_0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(16),
Q => r_0(2),
R => '0'
);
\r_0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(17),
Q => r_0(3),
R => '0'
);
\r_0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(18),
Q => r_0(4),
R => '0'
);
\r_0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(19),
Q => r_0(5),
R => '0'
);
\r_0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_0(20),
Q => r_0(6),
R => '0'
);
\r_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(14),
Q => r_1(0),
R => '0'
);
\r_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(15),
Q => r_1(1),
R => '0'
);
\r_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(16),
Q => r_1(2),
R => '0'
);
\r_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(17),
Q => r_1(3),
R => '0'
);
\r_1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(18),
Q => r_1(4),
R => '0'
);
\r_1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(19),
Q => r_1(5),
R => '0'
);
\r_1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_1(20),
Q => r_1(6),
R => '0'
);
\rgb[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(3),
I1 => g_1(3),
O => \rgb[11]_i_2_n_0\
);
\rgb[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(2),
I1 => g_1(2),
O => \rgb[11]_i_3_n_0\
);
\rgb[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(1),
I1 => g_1(1),
O => \rgb[11]_i_4_n_0\
);
\rgb[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(0),
I1 => g_1(0),
O => \rgb[11]_i_5_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(6),
I1 => g_1(6),
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(5),
I1 => g_1(5),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => g_0(4),
I1 => g_1(4),
O => \rgb[15]_i_4_n_0\
);
\rgb[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(3),
I1 => r_1(3),
O => \rgb[19]_i_2_n_0\
);
\rgb[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(2),
I1 => r_1(2),
O => \rgb[19]_i_3_n_0\
);
\rgb[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(1),
I1 => r_1(1),
O => \rgb[19]_i_4_n_0\
);
\rgb[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(0),
I1 => r_1(0),
O => \rgb[19]_i_5_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(6),
I1 => r_1(6),
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(5),
I1 => r_1(5),
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => r_0(4),
I1 => r_1(4),
O => \rgb[23]_i_4_n_0\
);
\rgb[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(3),
I1 => b_1(3),
O => \rgb[3]_i_2_n_0\
);
\rgb[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(2),
I1 => b_1(2),
O => \rgb[3]_i_3_n_0\
);
\rgb[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(1),
I1 => b_1(1),
O => \rgb[3]_i_4_n_0\
);
\rgb[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(0),
I1 => b_1(0),
O => \rgb[3]_i_5_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(6),
I1 => b_1(6),
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(5),
I1 => b_1(5),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => b_0(4),
I1 => b_1(4),
O => \rgb[7]_i_4_n_0\
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[11]_i_1_n_0\,
CO(2) => \rgb_reg[11]_i_1_n_1\,
CO(1) => \rgb_reg[11]_i_1_n_2\,
CO(0) => \rgb_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => g_0(3 downto 0),
O(3 downto 0) => rgb00_out(3 downto 0),
S(3) => \rgb[11]_i_2_n_0\,
S(2) => \rgb[11]_i_3_n_0\,
S(1) => \rgb[11]_i_4_n_0\,
S(0) => \rgb[11]_i_5_n_0\
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[11]_i_1_n_0\,
CO(3) => rgb00_out(7),
CO(2) => \NLW_rgb_reg[15]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[15]_i_1_n_2\,
CO(0) => \rgb_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => g_0(6 downto 4),
O(3) => \NLW_rgb_reg[15]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb00_out(6 downto 4),
S(3) => '1',
S(2) => \rgb[15]_i_2_n_0\,
S(1) => \rgb[15]_i_3_n_0\,
S(0) => \rgb[15]_i_4_n_0\
);
\rgb_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(0),
Q => rgb(16),
R => '0'
);
\rgb_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(1),
Q => rgb(17),
R => '0'
);
\rgb_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(2),
Q => rgb(18),
R => '0'
);
\rgb_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(3),
Q => rgb(19),
R => '0'
);
\rgb_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[19]_i_1_n_0\,
CO(2) => \rgb_reg[19]_i_1_n_1\,
CO(1) => \rgb_reg[19]_i_1_n_2\,
CO(0) => \rgb_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => r_0(3 downto 0),
O(3 downto 0) => rgb01_out(3 downto 0),
S(3) => \rgb[19]_i_2_n_0\,
S(2) => \rgb[19]_i_3_n_0\,
S(1) => \rgb[19]_i_4_n_0\,
S(0) => \rgb[19]_i_5_n_0\
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(4),
Q => rgb(20),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(5),
Q => rgb(21),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(6),
Q => rgb(22),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb01_out(7),
Q => rgb(23),
R => '0'
);
\rgb_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[19]_i_1_n_0\,
CO(3) => rgb01_out(7),
CO(2) => \NLW_rgb_reg[23]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[23]_i_1_n_2\,
CO(0) => \rgb_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => r_0(6 downto 4),
O(3) => \NLW_rgb_reg[23]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb01_out(6 downto 4),
S(3) => '1',
S(2) => \rgb[23]_i_2_n_0\,
S(1) => \rgb[23]_i_3_n_0\,
S(0) => \rgb[23]_i_4_n_0\
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rgb_reg[3]_i_1_n_0\,
CO(2) => \rgb_reg[3]_i_1_n_1\,
CO(1) => \rgb_reg[3]_i_1_n_2\,
CO(0) => \rgb_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => b_0(3 downto 0),
O(3 downto 0) => rgb0(3 downto 0),
S(3) => \rgb[3]_i_2_n_0\,
S(2) => \rgb[3]_i_3_n_0\,
S(1) => \rgb[3]_i_4_n_0\,
S(0) => \rgb[3]_i_5_n_0\
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb0(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rgb_reg[3]_i_1_n_0\,
CO(3) => rgb0(7),
CO(2) => \NLW_rgb_reg[7]_i_1_CO_UNCONNECTED\(2),
CO(1) => \rgb_reg[7]_i_1_n_2\,
CO(0) => \rgb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => b_0(6 downto 4),
O(3) => \NLW_rgb_reg[7]_i_1_O_UNCONNECTED\(3),
O(2 downto 0) => rgb0(6 downto 4),
S(3) => '1',
S(2) => \rgb[7]_i_2_n_0\,
S(1) => \rgb[7]_i_3_n_0\,
S(0) => \rgb[7]_i_4_n_0\
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb00_out(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_overlay_0_0 is
port (
clk : in STD_LOGIC;
rgb_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_overlay_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_overlay_0_0 : entity is "system_vga_overlay_0_0,vga_overlay,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_overlay_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_overlay_0_0 : entity is "vga_overlay,Vivado 2016.4";
end system_vga_overlay_0_0;
architecture STRUCTURE of system_vga_overlay_0_0 is
begin
U0: entity work.system_vga_overlay_0_0_vga_overlay
port map (
clk => clk,
rgb(23 downto 0) => rgb(23 downto 0),
rgb_0(20 downto 14) => rgb_0(23 downto 17),
rgb_0(13 downto 7) => rgb_0(15 downto 9),
rgb_0(6 downto 0) => rgb_0(7 downto 1),
rgb_1(20 downto 14) => rgb_1(23 downto 17),
rgb_1(13 downto 7) => rgb_1(15 downto 9),
rgb_1(6 downto 0) => rgb_1(7 downto 1)
);
end STRUCTURE;
| mit | fd5145044a13ad8fcefd6caae61abc82 | 0.441853 | 2.580379 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/system_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 32,472 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:13:47 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/system_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : system_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_cdc_sync : entity is "cdc_sync";
end system_rst_ps7_0_100M_0_cdc_sync;
architecture STRUCTURE of system_rst_ps7_0_100M_0_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_cdc_sync_0 : entity is "cdc_sync";
end system_rst_ps7_0_100M_0_cdc_sync_0;
architecture STRUCTURE of system_rst_ps7_0_100M_0_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_upcnt_n : entity is "upcnt_n";
end system_rst_ps7_0_100M_0_upcnt_n;
architecture STRUCTURE of system_rst_ps7_0_100M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_lpf : entity is "lpf";
end system_rst_ps7_0_100M_0_lpf;
architecture STRUCTURE of system_rst_ps7_0_100M_0_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.system_rst_ps7_0_100M_0_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.system_rst_ps7_0_100M_0_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_sequence_psr : entity is "sequence_psr";
end system_rst_ps7_0_100M_0_sequence_psr;
architecture STRUCTURE of system_rst_ps7_0_100M_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.system_rst_ps7_0_100M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of system_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of system_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of system_rst_ps7_0_100M_0_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of system_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_ps7_0_100M_0_proc_sys_reset : entity is "proc_sys_reset";
end system_rst_ps7_0_100M_0_proc_sys_reset;
architecture STRUCTURE of system_rst_ps7_0_100M_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.system_rst_ps7_0_100M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.system_rst_ps7_0_100M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rst_ps7_0_100M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rst_ps7_0_100M_0 : entity is "system_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rst_ps7_0_100M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rst_ps7_0_100M_0 : entity is "proc_sys_reset,Vivado 2016.4";
end system_rst_ps7_0_100M_0;
architecture STRUCTURE of system_rst_ps7_0_100M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.system_rst_ps7_0_100M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | db521e9fc2cd0dee795c1eaf5a104fd8 | 0.572986 | 2.832519 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/video-misc/video_timing_ctrl.vhd | 1 | 4,350 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--Flexible Video Timing Controller
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
entity video_timing_ctrl is
generic(
video_hlength : natural := 2200; --total visible and blanking pixels per line
video_vlength : natural := 1125; --total visible and blanking lines per frame
video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync (does not affect framebuffer outputs)
video_hsync_len : natural := 44; --horizontal sync length in pixels
video_hbp_len : natural := 88; --horizontal back porch length (excluding sync)
video_h_visible : natural := 1920; --number of visible pixels per line
video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync
video_vsync_len : natural := 5; --vertical sync length in lines
video_vbp_len : natural := 4; --vertical back porch length (excluding sync)
video_v_visible : natural := 1080; --number of visible lines per frame
--H and V timing coordinates at rising edge of external sync input
sync_v_pos : natural := 132;
sync_h_pos : natural := 1079
);
port(
pixel_clock : in std_logic;
reset : in std_logic; --active high async reset
--External sync input
ext_sync : in std_logic;
--Timing and pixel coordinate outputs
timing_h_pos : out natural range 0 to video_hlength - 1;
timing_v_pos : out natural range 0 to video_vlength - 1;
pixel_x : out natural range 0 to video_h_visible - 1;
pixel_y : out natural range 0 to video_v_visible - 1;
--Traditional timing signals
--line_start is like hsync but always active high and only asserted for visible lines and for 1 clock cycle
video_vsync : out std_logic;
video_hsync : out std_logic;
video_den : out std_logic;
video_line_start : out std_logic
);
end video_timing_ctrl;
architecture Behavioral of video_timing_ctrl is
constant t_hsync_end : natural := video_hsync_len - 1;
constant t_hvis_begin : natural := video_hsync_len + video_hbp_len;
constant t_hvis_end : natural := t_hvis_begin + video_h_visible - 1;
constant t_vsync_end : natural := video_vsync_len - 1;
constant t_vvis_begin : natural := video_vsync_len + video_vbp_len;
constant t_vvis_end : natural := t_vvis_begin + video_v_visible - 1;
signal h_pos : natural range 0 to video_hlength - 1;
signal v_pos : natural range 0 to video_vlength - 1;
signal x_int : natural range 0 to video_h_visible - 1;
signal y_int : natural range 0 to video_h_visible - 1;
signal h_visible, v_visible : std_logic;
signal hsync_pos, vsync_pos : std_logic;
signal ext_sync_last : std_logic;
signal ext_sync_curr : std_logic;
begin
--Basic counters
process(pixel_clock, reset)
begin
if reset = '1' then
h_pos <= 0;
v_pos <= 0;
elsif rising_edge(pixel_clock) then
if ext_sync_curr = '1' and ext_sync_last = '0' then
h_pos <= sync_h_pos;
v_pos <= sync_v_pos;
else
if h_pos = video_hlength - 1 then
h_pos <= 0;
if v_pos = video_vlength - 1 then
v_pos <= 0;
else
v_pos <= v_pos + 1;
end if;
else
h_pos <= h_pos + 1;
end if;
end if;
ext_sync_curr <= ext_sync;
ext_sync_last <= ext_sync_curr;
end if;
end process;
--Visible signals
v_visible <= '1' when (v_pos >= t_vvis_begin) and (v_pos <= t_vvis_end) else '0';
h_visible <= '1' when (h_pos >= t_hvis_begin) and (h_pos <= t_hvis_end) else '0';
--Pixel coordinates
x_int <= (h_pos - t_hvis_begin) when (h_visible = '1') and (v_visible = '1') else 0;
y_int <= (v_pos - t_vvis_begin) when v_visible = '1' else 0;
--den and line_start signals
video_den <= h_visible and v_visible;
video_line_start <= '1' when (v_visible = '1') and (h_pos = 0) else '0';
--Sync signals
vsync_pos <= '1' when v_pos <= t_vsync_end else '0';
hsync_pos <= '1' when h_pos <= t_hsync_end else '0';
video_vsync <= vsync_pos when video_vsync_pol else not vsync_pos;
video_hsync <= hsync_pos when video_hsync_pol else not hsync_pos;
--External outputs
timing_h_pos <= h_pos;
timing_v_pos <= v_pos;
pixel_x <= x_int;
pixel_y <= y_int;
end Behavioral;
| mit | d65f185a3e055d567651ea6d39883200 | 0.641379 | 3.302961 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/syncram_2r1w_inferred-rtl.vhdl | 1 | 2,881 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of syncram_2r1w_inferred is
constant memory_size : natural := 2**addr_bits;
type memory_type is array(0 to memory_size-1) of std_ulogic_vector((data_bits-1) downto 0);
signal memory : memory_type
-- pragma translate_off
:= (others => (others => '0'));
-- pragma translate_on
;
type reg_type is record
raddr1, raddr2 : std_ulogic_vector(addr_bits-1 downto 0);
end record;
signal r : reg_type;
pure function conv_addr (addr : std_ulogic_vector(addr_bits-1 downto 0)) return natural is
begin
if addr_bits > 0 then
return to_integer(unsigned(addr));
else
return 0;
end if;
end function;
begin
write_first_true_gen: if write_first generate
rdata1 <= memory(conv_addr(r.raddr1));
rdata2 <= memory(conv_addr(r.raddr2));
main : process(clk)
begin
if rising_edge(clk) then
if re1 = '1' then
r.raddr1 <= raddr1;
end if;
if re2 = '1' then
r.raddr2 <= raddr2;
end if;
if we = '1' then
memory(conv_addr(waddr)) <= wdata;
end if;
end if;
end process;
end generate;
write_first_false_gen: if not write_first generate
main : process(clk)
begin
if rising_edge(clk) then
if re1 = '1' then
r.rdata1 <= memory(conv_addr(raddr1));
end if;
if re2 = '2' then
r.rdata2 <= memory(conv_addr(raddr2));
end if;
if we = '1' then
memory(conv_addr(waddr)) <= wdata;
end if;
end if;
end generate;
end;
| apache-2.0 | e472ce9e8337f631207274e8fa3e3ef2 | 0.53176 | 4.157287 | false | false | false | false |
sbourdeauducq/dspunit | rtl/cpflip.vhd | 2 | 5,960 | -- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
use work.dspalu_pac.all;
-------------------------------------------------------------------------------
entity cpflip is
port (
--@inputs
clk : in std_logic;
op_en : in std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
length_reg : in std_logic_vector((cmdreg_data_width -1) downto 0);
--@outputs;
dsp_bus : out t_dsp_bus
);
end cpflip;
--=----------------------------------------------------------------------------
architecture archi_cpflip of cpflip is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_bus : t_dsp_bus;
type t_cpflip_state is (st_init, st_startpipe, st_copy);
signal s_state : t_cpflip_state;
signal s_length : unsigned((cmdreg_width - 1) downto 0);
begin -- archs_cpflip
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_cpflip : process (clk)
begin -- process p_cpflip
if rising_edge(clk) then -- rising clock edge
if op_en = '0' then
s_state <= st_init;
--s_dsp_bus <= c_dsp_bus_init;
s_dsp_bus.op_done <= '0';
-- memory 0
-- s_dsp_bus.data_out_m0 <= (others => '0');
s_dsp_bus.addr_r_m0 <= (others => '0');
s_dsp_bus.addr_w_m0 <= (others => '0');
s_dsp_bus.wr_en_m0 <= '0';
--s_dsp_bus.c_en_m0 <= '0';
-- memory 1
-- s_dsp_bus.data_out_m1 <= (others => '0');
s_dsp_bus.addr_m1 <= (others => '0');
s_dsp_bus.wr_en_m1 <= '0';
--s_dsp_bus.c_en_m1 <= '0';
-- memory 2
-- s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.wr_en_m2 <= '0';
--s_dsp_bus.c_en_m2 <= '0';
-- alu
--s_dsp_bus.mul_in_a1 <= (others <= '0');
--s_dsp_bus.mul_in_b1 <= (others <= '0');
--s_dsp_bus.mul_in_a2 <= (others <= '0');
--s_dsp_bus.mul_in_b2 <= (others <= '0');
s_dsp_bus.acc_mode1 <= acc_store;
s_dsp_bus.acc_mode2 <= acc_store;
s_dsp_bus.alu_select <= alu_mul;
-- global counter
--s_dsp_bus.gcounter_reset <= '0';
-------------------------------------------------------------------------------
-- operation management
-------------------------------------------------------------------------------
else
case s_state is
when st_init =>
s_dsp_bus.addr_m1 <= s_length;
s_dsp_bus.addr_m2 <= (others => '0');
s_dsp_bus.wr_en_m1 <= '0';
if s_dsp_bus.op_done = '0' then
s_state <= st_startpipe;
end if;
when st_startpipe =>
if s_dsp_bus.addr_m2 = 1 then
s_dsp_bus.wr_en_m1 <= '1';
s_state <= st_copy;
end if;
-- index increment
s_dsp_bus.addr_m2 <= s_dsp_bus.addr_m2 + 1;
when st_copy =>
s_dsp_bus.wr_en_m1 <= '1';
if(s_dsp_bus.addr_m1 = 0) then
s_state <= st_init;
s_dsp_bus.op_done <= '1';
else
s_dsp_bus.addr_m2 <= s_dsp_bus.addr_m2 + 1;
s_dsp_bus.addr_m1 <= (s_dsp_bus.addr_m1 - 1) and s_length;
end if;
when others => null;
end case;
end if;
end if;
end process p_cpflip;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
dsp_bus <= s_dsp_bus;
s_dsp_bus.data_out_m2 <= (others => '0');
s_dsp_bus.data_out_m0 <= (others => '0');
s_dsp_bus.data_out_m1 <= data_in_m2;
s_dsp_bus.c_en_m0 <= '0';
s_dsp_bus.c_en_m1 <= '1';
s_dsp_bus.c_en_m2 <= '1';
s_dsp_bus.gcounter_reset <= '1';
s_length <= unsigned(length_reg);
end archi_cpflip;
| gpl-3.0 | 1f8bc5fe2a4079e2f43be537ce6ba187 | 0.394799 | 3.832797 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/superip.vhd | 1 | 17,322 | ------------------------------------------------------------------------------
-- superip.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: superip.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 5 20:44:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library superip_v1_00_a;
use superip_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity superip is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Left_out : out std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity superip;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of superip is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity superip_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
Mux2_FilterORMux1_Left_out => Mux2_FilterORMux1_Left_out,
Mux2_FilterORMux1_Right_out => Mux2_FilterORMux1_Right_out,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 49c506895c670987d2b0ec0b85cdc562 | 0.460628 | 4.143028 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_video_output.vhd | 1 | 7,721 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--MIPI CSI-2 Rx Video Output Controller
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This receives unpacked 10bit pixel data from the unpacker and framing signals from the packet handler,
--and writes it into a dual-port line buffer to cross it from the byte clock into the pixel clock domain
--It also generates all the necessary video output signals
entity csi_rx_video_output is
generic(
video_hlength : natural := 4046; --total visible and blanking pixels per line
video_vlength : natural := 2190; --total visible and blanking lines per frame
video_hsync_pol : boolean := true; --hsync polarity: true for positive sync, false for negative sync
video_hsync_len : natural := 48; --horizontal sync length in pixels
video_hbp_len : natural := 122; --horizontal back porch length (excluding sync)
video_h_visible : natural := 3840; --number of visible pixels per line
video_vsync_pol : boolean := true; --vsync polarity: true for positive sync, false for negative sync
video_vsync_len : natural := 3; --vertical sync length in lines
video_vbp_len : natural := 23; --vertical back porch length (excluding sync)
video_v_visible : natural := 2160; --number of visible lines per frame
pixels_per_clock : natural := 2 --Number of pixels per clock to output; 1, 2 or 4
);
port(
output_clock : in std_logic; --Output pixel clock
csi_byte_clock : in std_logic; --CSI byte clock
enable : in std_logic; --system enable input
reset : in std_logic; --synchronous active high reset input
pixel_data_in : in std_logic_vector(39 downto 0); --Unpacked 10 bit data
pixel_data_valid : in std_logic;
csi_in_frame : in std_logic;
csi_in_line : in std_logic;
csi_vsync : in std_logic;
video_valid : out std_logic; --goes high when valid frames are being received
--Pixel data output
video_hsync : out std_logic;
video_vsync : out std_logic;
video_den : out std_logic;
video_line_start : out std_logic; --like hsync but asserted for one clock period only and only for visible lines
video_odd_line : out std_logic; --LSB of y-coordinate for a downstream debayering block
video_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0); --LSW is leftmost pixel
video_prev_line_data : out std_logic_vector(((10 * pixels_per_clock) - 1) downto 0) --last line's data at this point, for a debayering block to use
);
end csi_rx_video_output;
architecture Behavioral of csi_rx_video_output is
signal csi_in_line_last, csi_in_frame_last, csi_odd_line, csi_frame_started : std_logic := '0';
signal video_fsync_pre, video_fsync : std_logic := '0';
signal csi_x_pos : natural range 0 to video_h_visible - 1;
constant output_width : natural := video_h_visible / pixels_per_clock;
constant output_tmg_hlength : natural := video_hlength / pixels_per_clock;
constant output_hvis_begin : natural := (video_hsync_len + video_hbp_len) / pixels_per_clock;
signal output_timing_h : natural range 0 to output_tmg_hlength - 1;
signal output_pixel_y : natural range 0 to video_v_visible - 1;
signal linebuf_write_address : natural range 0 to video_h_visible / 4 - 1;
signal linebuf_read_address : natural range 0 to output_width - 1;
signal even_linebuf_wren, odd_linebuf_wren : std_logic := '0';
signal even_linebuf_q, odd_linebuf_q : std_logic_vector(((10 * pixels_per_clock) - 1) downto 0);
signal output_hsync, output_vsync, output_den, output_line_start, output_odd_line : std_logic;
signal output_data, output_prev_line_data : std_logic_vector(((10 * pixels_per_clock) - 1) downto 0);
begin
process(csi_byte_clock)
begin
if rising_edge(csi_byte_clock) then
if reset = '1' then
csi_in_line_last <= '0';
csi_in_frame_last <= '0';
csi_frame_started <= '0';
csi_odd_line <= '1';
elsif enable = '1' then
csi_in_frame_last <= csi_in_frame;
csi_in_line_last <= csi_in_line;
if csi_in_frame_last = '0' and csi_in_frame = '1' then --Start of frame
csi_x_pos <= 0;
csi_odd_line <= '1';
csi_frame_started <= '0';
elsif csi_in_line_last = '0' and csi_in_line = '1' then --Start of line
csi_x_pos <= 0;
csi_odd_line <= not csi_odd_line;
csi_frame_started <= '1';
elsif pixel_data_valid = '1' then
csi_x_pos <= csi_x_pos + 4;
end if;
end if;
end if;
end process;
linebuf_write_address <= csi_x_pos / 4;
even_linebuf_wren <= pixel_data_valid when csi_odd_line = '0' else '0';
odd_linebuf_wren <= pixel_data_valid when csi_odd_line = '1' else '0';
process(output_clock)
begin
if rising_edge(output_clock) then
if reset = '1' then
video_fsync_pre <= '0';
video_fsync <= '0';
elsif enable = '1' then
video_fsync_pre <= csi_frame_started;
video_fsync <= video_fsync_pre;
--Register video output
video_hsync <= output_hsync;
video_vsync <= output_vsync;
video_den <= output_den;
video_line_start <= output_line_start;
video_odd_line <= output_odd_line;
video_data <= output_data;
video_prev_line_data <= output_prev_line_data;
end if;
end if;
end process;
output_odd_line <= '1' when output_pixel_y mod 2 = 1 else '0';
output_data <= odd_linebuf_q when output_odd_line = '1' else even_linebuf_q;
output_prev_line_data <= even_linebuf_q when output_odd_line = '1' else odd_linebuf_q;
linebuf_read_address <= (output_timing_h - (output_hvis_begin - 1)); -- the -1 accounts for the RAM read latency
output_timing : entity work.video_timing_ctrl
generic map(
video_hlength => output_tmg_hlength,
video_vlength => video_vlength,
video_hsync_pol => video_hsync_pol,
video_hsync_len => video_hsync_len / pixels_per_clock,
video_hbp_len => video_hbp_len / pixels_per_clock,
video_h_visible => video_h_visible / pixels_per_clock,
video_vsync_pol => video_vsync_pol,
video_vsync_len => video_vsync_len,
video_vbp_len => video_vbp_len,
video_v_visible => video_v_visible,
sync_v_pos => (video_vbp_len + video_vsync_len - 1), --keep output 1 line behind input
sync_h_pos => (output_tmg_hlength - 5)
)
port map(
pixel_clock => output_clock,
reset => reset,
ext_sync => video_fsync,
timing_h_pos => output_timing_h,
timing_v_pos => open,
pixel_x => open,
pixel_y => output_pixel_y,
video_vsync => output_vsync,
video_hsync => output_hsync,
video_den => output_den,
video_line_start => output_line_start
);
even_linebuf : entity work.csi_rx_line_buffer
generic map(
line_width => video_h_visible,
pixels_per_clock => pixels_per_clock
)
port map(
write_clock => csi_byte_clock,
write_addr => linebuf_write_address,
write_data => pixel_data_in,
write_en => even_linebuf_wren,
read_clock => output_clock,
read_addr => linebuf_read_address,
read_q => even_linebuf_q
);
odd_linebuf : entity work.csi_rx_line_buffer
generic map(
line_width => video_h_visible,
pixels_per_clock => pixels_per_clock
)
port map(
write_clock => csi_byte_clock,
write_addr => linebuf_write_address,
write_data => pixel_data_in,
write_en => odd_linebuf_wren,
read_clock => output_clock,
read_addr => linebuf_read_address,
read_q => odd_linebuf_q
);
video_valid <= '1'; --not yet implemented
end Behavioral;
| mit | 3b6a87495561f01fdb25a476f18760d3 | 0.642015 | 3.428508 | false | false | false | false |
pgavin/carpe | hdl/cpu/mmu/data/pass/cpu_mmu_data_pass-rtl.vhdl | 1 | 2,879 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use work.cpu_types_pkg.all;
use work.cpu_mmu_data_types_pkg.all;
architecture rtl of cpu_mmu_data_pass is
type reg_type is record
mmuen : std_ulogic;
vpn : cpu_vpn_type;
end record;
signal r, r_next : reg_type;
type comb_type is record
ppn : cpu_ppn_type;
end record;
signal c : comb_type;
begin
ppn_large_vpn_gen : if cpu_ppn_bits > 0 and cpu_ppn_bits <= cpu_vpn_bits generate
bit_loop : for n in cpu_ppn_bits-1 downto 0 generate
c.ppn(n) <= r.vpn(n);
end generate;
end generate;
ppn_small_vpn_gen : if cpu_ppn_bits > 0 and cpu_ppn_bits > cpu_vpn_bits generate
c.ppn(cpu_ppn_bits-1 downto cpu_vpn_bits) <= (others => '0');
c.ppn(cpu_vpn_bits-1 downto 0) <= r.vpn;
end generate;
r_next <= (
mmuen => cpu_mmu_data_pass_ctrl_in.mmuen,
vpn => cpu_mmu_data_pass_dp_in.vpn
);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '0' =>
r <= (
mmuen => '0',
vpn => (others => 'X')
);
when '1' =>
r <= r_next;
when others =>
r <= (
mmuen => 'X',
vpn => (others => 'X')
);
end case;
end if;
end process;
--cpu_mmu_data_pass_ctrl_out <= (
-- );
cpu_mmu_data_pass_ctrl_out <= (
ready => '1',
result => (
cpu_mmu_data_result_code_index_valid => not r.mmuen,
cpu_mmu_data_result_code_index_error => '0',
cpu_mmu_data_result_code_index_tlbmiss => r.mmuen,
cpu_mmu_data_result_code_index_pf => '0'
)
);
cpu_mmu_data_pass_dp_out <= (
ppn => c.ppn
);
end;
| apache-2.0 | 915e1e9385c1d759fbab2e9f60d3b2c5 | 0.505384 | 3.748698 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl | 1 | 804,707 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:47:19 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_i2c_sender is
port (
hdmi_sda : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_hdmi_0_0_i2c_sender : entity is "i2c_sender";
end system_zed_hdmi_0_0_i2c_sender;
architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is
signal address : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \address[0]_i_1_n_0\ : STD_LOGIC;
signal \address[1]_i_1_n_0\ : STD_LOGIC;
signal \address[2]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_1_n_0\ : STD_LOGIC;
signal \address[3]_i_2_n_0\ : STD_LOGIC;
signal \address[4]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_1_n_0\ : STD_LOGIC;
signal \address[5]_i_2_n_0\ : STD_LOGIC;
signal \address[5]_i_3_n_0\ : STD_LOGIC;
signal \address[5]_i_4_n_0\ : STD_LOGIC;
signal \address[5]_i_5_n_0\ : STD_LOGIC;
signal \address[5]_i_6_n_0\ : STD_LOGIC;
signal \address[5]_i_7_n_0\ : STD_LOGIC;
signal busy_sr : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 );
signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC;
signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 );
signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[0]_i_2_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal divider : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \divider[0]_i_1_n_0\ : STD_LOGIC;
signal \divider[1]_i_1_n_0\ : STD_LOGIC;
signal \divider[2]_i_1_n_0\ : STD_LOGIC;
signal \divider[3]_i_1_n_0\ : STD_LOGIC;
signal \divider[4]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_1_n_0\ : STD_LOGIC;
signal \divider[5]_i_2_n_0\ : STD_LOGIC;
signal \divider[6]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_1_n_0\ : STD_LOGIC;
signal \divider[7]_i_2_n_0\ : STD_LOGIC;
signal \divider[7]_i_3_n_0\ : STD_LOGIC;
signal finished_i_1_n_0 : STD_LOGIC;
signal finished_reg_n_0 : STD_LOGIC;
signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC;
signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC;
signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in : STD_LOGIC;
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 );
signal reg_value_reg_n_10 : STD_LOGIC;
signal reg_value_reg_n_11 : STD_LOGIC;
signal reg_value_reg_n_12 : STD_LOGIC;
signal reg_value_reg_n_13 : STD_LOGIC;
signal reg_value_reg_n_14 : STD_LOGIC;
signal reg_value_reg_n_15 : STD_LOGIC;
signal reg_value_reg_n_8 : STD_LOGIC;
signal reg_value_reg_n_9 : STD_LOGIC;
signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC;
signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC;
signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC;
signal tristate_sr_reg_gate_n_0 : STD_LOGIC;
signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC;
signal tristate_sr_reg_r_0_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_1_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_2_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_3_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_4_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_5_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_6_n_0 : STD_LOGIC;
signal tristate_sr_reg_r_n_0 : STD_LOGIC;
signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of reg_value_reg : label is 1024;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of reg_value_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of reg_value_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of reg_value_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of reg_value_reg : label is 15;
attribute srl_bus_name : string;
attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name : string;
attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 ";
attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg ";
attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 ";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16";
begin
\address[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => p_0_in,
I1 => \address[5]_i_5_n_0\,
I2 => \address[5]_i_3_n_0\,
I3 => address(0),
O => \address[0]_i_1_n_0\
);
\address[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(0),
I4 => address(1),
O => \address[1]_i_1_n_0\
);
\address[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008080808000000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(1),
I4 => address(0),
I5 => address(2),
O => \address[2]_i_1_n_0\
);
\address[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[3]_i_2_n_0\,
I4 => address(3),
O => \address[3]_i_1_n_0\
);
\address[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => address(1),
I1 => address(0),
I2 => address(2),
O => \address[3]_i_2_n_0\
);
\address[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000008"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => \address[5]_i_6_n_0\,
I4 => address(4),
O => \address[4]_i_1_n_0\
);
\address[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => \address[5]_i_4_n_0\,
I4 => divider(7),
I5 => p_0_in,
O => \address[5]_i_1_n_0\
);
\address[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808000800000800"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => \address[5]_i_5_n_0\,
I2 => p_0_in,
I3 => address(4),
I4 => \address[5]_i_6_n_0\,
I5 => address(5),
O => \address[5]_i_2_n_0\
);
\address[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF7FFF"
)
port map (
I0 => \p_0_in__0\(2),
I1 => \p_0_in__0\(3),
I2 => \p_0_in__0\(0),
I3 => \p_0_in__0\(1),
I4 => \address[5]_i_7_n_0\,
O => \address[5]_i_3_n_0\
);
\address[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
O => \address[5]_i_4_n_0\
);
\address[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => divider(6),
I3 => \divider[7]_i_3_n_0\,
I4 => divider(7),
O => \address[5]_i_5_n_0\
);
\address[5]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => address(2),
I1 => address(0),
I2 => address(1),
I3 => address(3),
O => \address[5]_i_6_n_0\
);
\address[5]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \p_0_in__0\(5),
I1 => \p_0_in__0\(4),
I2 => \p_0_in__0\(7),
I3 => \p_0_in__0\(6),
O => \address[5]_i_7_n_0\
);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[0]_i_1_n_0\,
Q => address(0),
R => '0'
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[1]_i_1_n_0\,
Q => address(1),
R => '0'
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[2]_i_1_n_0\,
Q => address(2),
R => '0'
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[3]_i_1_n_0\,
Q => address(3),
R => '0'
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[4]_i_1_n_0\,
Q => address(4),
R => '0'
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \address[5]_i_1_n_0\,
D => \address[5]_i_2_n_0\,
Q => address(5),
R => '0'
);
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF200000"
)
port map (
I0 => \address[5]_i_3_n_0\,
I1 => finished_reg_n_0,
I2 => p_1_in,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => busy_sr
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[9]\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[10]\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[11]\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[12]\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[13]\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[14]\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[15]\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[16]\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[17]\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[18]\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[0]\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[19]\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[20]\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[21]\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[22]\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[23]\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[24]\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[25]\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[26]\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \address[5]_i_4_n_0\,
I1 => divider(7),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[28]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[27]\,
O => \busy_sr[28]_i_2_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[1]\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[2]\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[3]\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[4]\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[5]\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[6]\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[7]\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => \busy_sr_reg_n_0_[8]\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \address[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[19]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[19]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[20]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[20]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[28]_i_2_n_0\,
Q => p_0_in,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[28]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[28]_i_1_n_0\
);
\clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
I4 => clk_last_quarter(28),
O => \clk_first_quarter[28]_i_1_n_0\
);
\clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \clk_first_quarter[28]_i_1_n_0\,
Q => clk_first_quarter(28),
S => \busy_sr[28]_i_1_n_0\
);
\clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => p_1_in,
I1 => finished_reg_n_0,
I2 => \address[5]_i_3_n_0\,
I3 => p_0_in,
I4 => divider(7),
I5 => \address[5]_i_4_n_0\,
O => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(9),
Q => clk_last_quarter(10),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(10),
Q => clk_last_quarter(11),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(11),
Q => clk_last_quarter(12),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(12),
Q => clk_last_quarter(13),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(13),
Q => clk_last_quarter(14),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(14),
Q => clk_last_quarter(15),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(15),
Q => clk_last_quarter(16),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(16),
Q => clk_last_quarter(17),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(17),
Q => clk_last_quarter(18),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(18),
Q => clk_last_quarter(19),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \tristate_sr[19]_i_1_n_0\,
Q => clk_last_quarter(1),
R => '0'
);
\clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(19),
Q => clk_last_quarter(20),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(20),
Q => clk_last_quarter(21),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(21),
Q => clk_last_quarter(22),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(22),
Q => clk_last_quarter(23),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(23),
Q => clk_last_quarter(24),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(24),
Q => clk_last_quarter(25),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(25),
Q => clk_last_quarter(26),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(26),
Q => clk_last_quarter(27),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(27),
Q => clk_last_quarter(28),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(1),
Q => clk_last_quarter(2),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(2),
Q => clk_last_quarter(3),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(3),
Q => clk_last_quarter(4),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(4),
Q => clk_last_quarter(5),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(5),
Q => clk_last_quarter(6),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(6),
Q => clk_last_quarter(7),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(7),
Q => clk_last_quarter(8),
R => \clk_last_quarter[2]_i_1_n_0\
);
\clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => clk_last_quarter(8),
Q => clk_last_quarter(9),
R => \clk_last_quarter[2]_i_1_n_0\
);
\data_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEACAEAEAEAEAEA"
)
port map (
I0 => \data_sr_reg_n_0_[0]\,
I1 => p_0_in,
I2 => \data_sr[0]_i_2_n_0\,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => \address[5]_i_3_n_0\,
O => \data_sr[0]_i_1_n_0\
);
\data_sr[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => divider(7),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(6),
O => \data_sr[0]_i_2_n_0\
);
\data_sr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[10]\,
I1 => p_0_in,
I2 => \p_0_in__0\(0),
O => p_2_in(11)
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => p_0_in,
I2 => \p_0_in__0\(1),
O => p_2_in(12)
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => p_0_in,
I2 => \p_0_in__0\(2),
O => p_2_in(13)
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => p_0_in,
I2 => \p_0_in__0\(3),
O => p_2_in(14)
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => p_0_in,
I2 => \p_0_in__0\(4),
O => p_2_in(15)
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => p_0_in,
I2 => \p_0_in__0\(5),
O => p_2_in(16)
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => p_0_in,
I2 => \p_0_in__0\(6),
O => p_2_in(17)
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => p_0_in,
I2 => \p_0_in__0\(7),
O => p_2_in(18)
);
\data_sr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[1]\,
I1 => p_0_in,
I2 => reg_value_reg_n_15,
O => p_2_in(2)
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => p_0_in,
I2 => reg_value_reg_n_14,
O => p_2_in(3)
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => p_0_in,
I2 => reg_value_reg_n_13,
O => p_2_in(4)
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => p_0_in,
I2 => reg_value_reg_n_12,
O => p_2_in(5)
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => p_0_in,
I2 => reg_value_reg_n_11,
O => p_2_in(6)
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => p_0_in,
I2 => reg_value_reg_n_10,
O => p_2_in(7)
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => p_0_in,
I2 => reg_value_reg_n_9,
O => p_2_in(8)
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => p_0_in,
I2 => reg_value_reg_n_8,
O => p_2_in(9)
);
\data_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => '1',
D => \data_sr[0]_i_1_n_0\,
Q => \data_sr_reg_n_0_[0]\,
R => '0'
);
\data_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[9]\,
Q => \data_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(11),
Q => \data_sr_reg_n_0_[11]\,
R => '0'
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(12),
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(13),
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(14),
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(15),
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(16),
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(17),
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(18),
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[18]\,
Q => \data_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[0]\,
Q => \data_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[21]\,
Q => \data_sr_reg_n_0_[22]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
S => \address[5]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[26]\,
Q => \data_sr_reg_n_0_[27]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \address[5]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(2),
Q => \data_sr_reg_n_0_[2]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(3),
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(4),
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(5),
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(6),
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(7),
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(8),
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_100,
CE => busy_sr,
D => p_2_in(9),
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => finished_reg_n_0,
I3 => divider(0),
O => \divider[0]_i_1_n_0\
);
\divider[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F4F400"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(0),
I4 => divider(1),
O => \divider[1]_i_1_n_0\
);
\divider[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F4F4F4F4000000"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
I3 => divider(1),
I4 => divider(0),
I5 => divider(2),
O => \divider[2]_i_1_n_0\
);
\divider[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA8000"
)
port map (
I0 => \divider[7]_i_1_n_0\,
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
O => \divider[3]_i_1_n_0\
);
\divider[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => divider(2),
I1 => divider(0),
I2 => divider(1),
I3 => divider(3),
I4 => \divider[7]_i_1_n_0\,
I5 => divider(4),
O => \divider[4]_i_1_n_0\
);
\divider[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[5]_i_2_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(5),
O => \divider[5]_i_1_n_0\
);
\divider[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => divider(3),
I1 => divider(1),
I2 => divider(0),
I3 => divider(2),
I4 => divider(4),
O => \divider[5]_i_2_n_0\
);
\divider[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A84454"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => p_0_in,
I2 => p_1_in,
I3 => finished_reg_n_0,
I4 => divider(6),
O => \divider[6]_i_1_n_0\
);
\divider[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => finished_reg_n_0,
I1 => p_1_in,
I2 => p_0_in,
O => \divider[7]_i_1_n_0\
);
\divider[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0B0BBB040404440"
)
port map (
I0 => \divider[7]_i_3_n_0\,
I1 => divider(6),
I2 => p_0_in,
I3 => p_1_in,
I4 => finished_reg_n_0,
I5 => divider(7),
O => \divider[7]_i_2_n_0\
);
\divider[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => divider(4),
I1 => divider(2),
I2 => divider(0),
I3 => divider(1),
I4 => divider(3),
I5 => divider(5),
O => \divider[7]_i_3_n_0\
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[0]_i_1_n_0\,
Q => divider(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[1]_i_1_n_0\,
Q => divider(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[2]_i_1_n_0\,
Q => divider(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[3]_i_1_n_0\,
Q => divider(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[4]_i_1_n_0\,
Q => divider(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[5]_i_1_n_0\,
Q => divider(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[6]_i_1_n_0\,
Q => divider(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \divider[7]_i_1_n_0\,
D => \divider[7]_i_2_n_0\,
Q => divider(7),
R => '0'
);
finished_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000020"
)
port map (
I0 => p_1_in,
I1 => \address[5]_i_4_n_0\,
I2 => divider(7),
I3 => \address[5]_i_3_n_0\,
I4 => p_0_in,
I5 => finished_reg_n_0,
O => finished_i_1_n_0
);
finished_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => finished_i_1_n_0,
Q => finished_reg_n_0,
R => '0'
);
hdmi_scl_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => clk_first_quarter(28),
I1 => divider(7),
O => hdmi_scl
);
hdmi_sda_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[28]\,
I1 => \tristate_sr_reg[28]_inv_n_0\,
O => hdmi_sda
);
\initial_pause[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => p_1_in,
I1 => p_0_in,
I2 => \initial_pause_reg_n_0_[0]\,
O => \p_1_in__0\(0)
);
\initial_pause[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0110"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
O => \p_1_in__0\(1)
);
\initial_pause[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00070008"
)
port map (
I0 => \initial_pause_reg_n_0_[0]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => p_1_in,
I3 => p_0_in,
I4 => \initial_pause_reg_n_0_[2]\,
O => \p_1_in__0\(2)
);
\initial_pause[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000007F00000080"
)
port map (
I0 => \initial_pause_reg_n_0_[1]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[2]\,
I3 => p_1_in,
I4 => p_0_in,
I5 => \initial_pause_reg_n_0_[3]\,
O => \p_1_in__0\(3)
);
\initial_pause[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \initial_pause_reg_n_0_[2]\,
I1 => \initial_pause_reg_n_0_[0]\,
I2 => \initial_pause_reg_n_0_[1]\,
I3 => \initial_pause_reg_n_0_[3]\,
I4 => \initial_pause[7]_i_1_n_0\,
I5 => \initial_pause_reg_n_0_[4]\,
O => \p_1_in__0\(4)
);
\initial_pause[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[5]_i_2_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[5]\,
O => \p_1_in__0\(5)
);
\initial_pause[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[3]\,
I1 => \initial_pause_reg_n_0_[1]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[2]\,
I4 => \initial_pause_reg_n_0_[4]\,
O => \initial_pause[5]_i_2_n_0\
);
\initial_pause[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0201"
)
port map (
I0 => \initial_pause[7]_i_3_n_0\,
I1 => p_1_in,
I2 => p_0_in,
I3 => \initial_pause_reg_n_0_[6]\,
O => \p_1_in__0\(6)
);
\initial_pause[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
O => \initial_pause[7]_i_1_n_0\
);
\initial_pause[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \initial_pause_reg_n_0_[6]\,
I1 => p_0_in,
I2 => p_1_in,
I3 => \initial_pause[7]_i_3_n_0\,
O => \p_1_in__0\(7)
);
\initial_pause[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \initial_pause_reg_n_0_[4]\,
I1 => \initial_pause_reg_n_0_[2]\,
I2 => \initial_pause_reg_n_0_[0]\,
I3 => \initial_pause_reg_n_0_[1]\,
I4 => \initial_pause_reg_n_0_[3]\,
I5 => \initial_pause_reg_n_0_[5]\,
O => \initial_pause[7]_i_3_n_0\
);
\initial_pause_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(0),
Q => \initial_pause_reg_n_0_[0]\,
R => '0'
);
\initial_pause_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(1),
Q => \initial_pause_reg_n_0_[1]\,
R => '0'
);
\initial_pause_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(2),
Q => \initial_pause_reg_n_0_[2]\,
R => '0'
);
\initial_pause_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(3),
Q => \initial_pause_reg_n_0_[3]\,
R => '0'
);
\initial_pause_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(4),
Q => \initial_pause_reg_n_0_[4]\,
R => '0'
);
\initial_pause_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(5),
Q => \initial_pause_reg_n_0_[5]\,
R => '0'
);
\initial_pause_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(6),
Q => \initial_pause_reg_n_0_[6]\,
R => '0'
);
\initial_pause_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \initial_pause[7]_i_1_n_0\,
D => \p_1_in__0\(7),
Q => p_1_in,
R => '0'
);
reg_value_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110",
INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 10) => B"0000",
ADDRARDADDR(9 downto 4) => address(5 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk_100,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 8) => \p_0_in__0\(7 downto 0),
DOADO(7) => reg_value_reg_n_8,
DOADO(6) => reg_value_reg_n_9,
DOADO(5) => reg_value_reg_n_10,
DOADO(4) => reg_value_reg_n_11,
DOADO(3) => reg_value_reg_n_12,
DOADO(2) => reg_value_reg_n_13,
DOADO(1) => reg_value_reg_n_14,
DOADO(0) => reg_value_reg_n_15,
DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
\tristate_sr[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => divider(6),
I1 => \divider[7]_i_3_n_0\,
I2 => divider(7),
I3 => p_0_in,
O => \tristate_sr[19]_i_1_n_0\
);
\tristate_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[9]\,
Q => \tristate_sr_reg_n_0_[10]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[10]\,
Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__0_n_0\,
Q => \tristate_sr_reg_n_0_[18]\,
R => \address[5]_i_1_n_0\
);
\tristate_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_n_0_[18]\,
Q => \tristate_sr_reg_n_0_[19]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '0',
Q => \tristate_sr_reg_n_0_[1]\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[19]\,
Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\
);
\tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
R => '0'
);
\tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_gate_n_0,
Q => \tristate_sr_reg[28]_inv_n_0\,
S => \address[5]_i_1_n_0\
);
\tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
CE => \tristate_sr[19]_i_1_n_0\,
CLK => clk_100,
D => \tristate_sr_reg_n_0_[1]\,
Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\
);
\tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\,
Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
R => '0'
);
\tristate_sr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => \tristate_sr_reg_gate__1_n_0\,
Q => \tristate_sr_reg_n_0_[9]\,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_gate: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\,
I1 => tristate_sr_reg_r_6_n_0,
O => tristate_sr_reg_gate_n_0
);
\tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__0_n_0\
);
\tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\,
I1 => tristate_sr_reg_r_5_n_0,
O => \tristate_sr_reg_gate__1_n_0\
);
tristate_sr_reg_r: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => '1',
Q => tristate_sr_reg_r_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_0: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_n_0,
Q => tristate_sr_reg_r_0_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_1: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_0_n_0,
Q => tristate_sr_reg_r_1_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_2: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_1_n_0,
Q => tristate_sr_reg_r_2_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_3: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_2_n_0,
Q => tristate_sr_reg_r_3_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_4: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_3_n_0,
Q => tristate_sr_reg_r_4_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_5: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_4_n_0,
Q => tristate_sr_reg_r_5_n_0,
R => \address[5]_i_1_n_0\
);
tristate_sr_reg_r_6: unisim.vcomponents.FDRE
port map (
C => clk_100,
CE => \tristate_sr[19]_i_1_n_0\,
D => tristate_sr_reg_r_5_n_0,
Q => tristate_sr_reg_r_6_n_0,
R => \address[5]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0_zed_hdmi is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_de : out STD_LOGIC;
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_0\ : out STD_LOGIC;
\cr_int_reg[31]_1\ : out STD_LOGIC;
O : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[27]_0\ : out STD_LOGIC;
\cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
hdmi_sda : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_scl : out STD_LOGIC;
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
clk_100 : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
\rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_zed_hdmi_0_0_zed_hdmi : entity is "zed_hdmi";
end system_zed_hdmi_0_0_zed_hdmi;
architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal D1 : STD_LOGIC;
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal cb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb[0]_i_1_n_0\ : STD_LOGIC;
signal \cb[1]_i_1_n_0\ : STD_LOGIC;
signal \cb[2]_i_1_n_0\ : STD_LOGIC;
signal \cb[3]_i_1_n_0\ : STD_LOGIC;
signal \cb[4]_i_1_n_0\ : STD_LOGIC;
signal \cb[5]_i_1_n_0\ : STD_LOGIC;
signal \cb[6]_i_1_n_0\ : STD_LOGIC;
signal \cb[7]_i_10_n_0\ : STD_LOGIC;
signal \cb[7]_i_11_n_0\ : STD_LOGIC;
signal \cb[7]_i_13_n_0\ : STD_LOGIC;
signal \cb[7]_i_14_n_0\ : STD_LOGIC;
signal \cb[7]_i_15_n_0\ : STD_LOGIC;
signal \cb[7]_i_16_n_0\ : STD_LOGIC;
signal \cb[7]_i_17_n_0\ : STD_LOGIC;
signal \cb[7]_i_18_n_0\ : STD_LOGIC;
signal \cb[7]_i_19_n_0\ : STD_LOGIC;
signal \cb[7]_i_20_n_0\ : STD_LOGIC;
signal \cb[7]_i_21_n_0\ : STD_LOGIC;
signal \cb[7]_i_22_n_0\ : STD_LOGIC;
signal \cb[7]_i_23_n_0\ : STD_LOGIC;
signal \cb[7]_i_24_n_0\ : STD_LOGIC;
signal \cb[7]_i_25_n_0\ : STD_LOGIC;
signal \cb[7]_i_26_n_0\ : STD_LOGIC;
signal \cb[7]_i_27_n_0\ : STD_LOGIC;
signal \cb[7]_i_28_n_0\ : STD_LOGIC;
signal \cb[7]_i_2_n_0\ : STD_LOGIC;
signal \cb[7]_i_4_n_0\ : STD_LOGIC;
signal \cb[7]_i_5_n_0\ : STD_LOGIC;
signal \cb[7]_i_6_n_0\ : STD_LOGIC;
signal \cb[7]_i_7_n_0\ : STD_LOGIC;
signal \cb[7]_i_8_n_0\ : STD_LOGIC;
signal \cb[7]_i_9_n_0\ : STD_LOGIC;
signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_108_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_102_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_103_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_104_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_105_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_106_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_12_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_27_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_9_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_10_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_13_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_16_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_67_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_68_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_69_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_70_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_71_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_72_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_75_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_76_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_77_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_78_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_79_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_80_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_81_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_82_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_9_n_0\ : STD_LOGIC;
signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cb_int_reg8 : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC;
signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC;
signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cb_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cb_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC;
signal cb_regn_0_0 : STD_LOGIC;
signal cr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \cr[0]_i_1_n_0\ : STD_LOGIC;
signal \cr[1]_i_1_n_0\ : STD_LOGIC;
signal \cr[2]_i_1_n_0\ : STD_LOGIC;
signal \cr[3]_i_1_n_0\ : STD_LOGIC;
signal \cr[4]_i_1_n_0\ : STD_LOGIC;
signal \cr[5]_i_1_n_0\ : STD_LOGIC;
signal \cr[6]_i_1_n_0\ : STD_LOGIC;
signal \cr[7]_i_10_n_0\ : STD_LOGIC;
signal \cr[7]_i_11_n_0\ : STD_LOGIC;
signal \cr[7]_i_13_n_0\ : STD_LOGIC;
signal \cr[7]_i_14_n_0\ : STD_LOGIC;
signal \cr[7]_i_15_n_0\ : STD_LOGIC;
signal \cr[7]_i_16_n_0\ : STD_LOGIC;
signal \cr[7]_i_17_n_0\ : STD_LOGIC;
signal \cr[7]_i_18_n_0\ : STD_LOGIC;
signal \cr[7]_i_19_n_0\ : STD_LOGIC;
signal \cr[7]_i_20_n_0\ : STD_LOGIC;
signal \cr[7]_i_21_n_0\ : STD_LOGIC;
signal \cr[7]_i_22_n_0\ : STD_LOGIC;
signal \cr[7]_i_23_n_0\ : STD_LOGIC;
signal \cr[7]_i_24_n_0\ : STD_LOGIC;
signal \cr[7]_i_25_n_0\ : STD_LOGIC;
signal \cr[7]_i_26_n_0\ : STD_LOGIC;
signal \cr[7]_i_27_n_0\ : STD_LOGIC;
signal \cr[7]_i_28_n_0\ : STD_LOGIC;
signal \cr[7]_i_2_n_0\ : STD_LOGIC;
signal \cr[7]_i_4_n_0\ : STD_LOGIC;
signal \cr[7]_i_5_n_0\ : STD_LOGIC;
signal \cr[7]_i_6_n_0\ : STD_LOGIC;
signal \cr[7]_i_7_n_0\ : STD_LOGIC;
signal \cr[7]_i_8_n_0\ : STD_LOGIC;
signal \cr[7]_i_9_n_0\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_int[11]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_101_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_102_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_127_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_128_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_129_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_130_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_131_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_132_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_133_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_134_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_135_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_136_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_137_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_138_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_139_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_140_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_141_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_142_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_143_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_144_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_145_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_146_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_147_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_148_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_149_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_150_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_151_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_152_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_153_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_154_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_155_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_156_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_70_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_9_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[27]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_103_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_108_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_109_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_110_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_111_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_112_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_113_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_114_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_115_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_116_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_117_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_118_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_119_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_120_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_121_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_122_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_123_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_124_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_125_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_126_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_16_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_97_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_10_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_13_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_22_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_23_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_24_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_48_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_49_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_50_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_51_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_56_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_57_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_58_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_69_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_71_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_72_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_75_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_76_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_77_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_78_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_79_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_80_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_81_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_82_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_83_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_89_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_90_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_91_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_92_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_93_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_94_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cr_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_11_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_14_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_15_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_17_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_18_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_20_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_21_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_25_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_26_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_27_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_2_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_4_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_5_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_6_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_7_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_8_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_9_n_0\ : STD_LOGIC;
signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 );
signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 );
signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal cr_int_reg7 : STD_LOGIC;
signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC;
signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC;
signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC;
signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC;
signal \^cr_int_reg[27]_0\ : STD_LOGIC;
signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[31]_0\ : STD_LOGIC;
signal \^cr_int_reg[31]_1\ : STD_LOGIC;
signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC;
signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \cr_int_reg_n_0_[0]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[1]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[2]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[3]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[4]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[5]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[6]\ : STD_LOGIC;
signal \cr_int_reg_n_0_[7]\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC;
signal edge : STD_LOGIC;
signal edge_i_1_n_0 : STD_LOGIC;
signal edge_rb : STD_LOGIC;
signal edge_rb_i_1_n_0 : STD_LOGIC;
signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC;
signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC;
signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC;
signal hdmi_vsync_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal y : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y[0]_i_1_n_0\ : STD_LOGIC;
signal \y[1]_i_1_n_0\ : STD_LOGIC;
signal \y[2]_i_1_n_0\ : STD_LOGIC;
signal \y[3]_i_1_n_0\ : STD_LOGIC;
signal \y[4]_i_1_n_0\ : STD_LOGIC;
signal \y[5]_i_1_n_0\ : STD_LOGIC;
signal \y[6]_i_1_n_0\ : STD_LOGIC;
signal \y[7]_i_10_n_0\ : STD_LOGIC;
signal \y[7]_i_11_n_0\ : STD_LOGIC;
signal \y[7]_i_13_n_0\ : STD_LOGIC;
signal \y[7]_i_14_n_0\ : STD_LOGIC;
signal \y[7]_i_15_n_0\ : STD_LOGIC;
signal \y[7]_i_16_n_0\ : STD_LOGIC;
signal \y[7]_i_17_n_0\ : STD_LOGIC;
signal \y[7]_i_18_n_0\ : STD_LOGIC;
signal \y[7]_i_19_n_0\ : STD_LOGIC;
signal \y[7]_i_20_n_0\ : STD_LOGIC;
signal \y[7]_i_21_n_0\ : STD_LOGIC;
signal \y[7]_i_22_n_0\ : STD_LOGIC;
signal \y[7]_i_23_n_0\ : STD_LOGIC;
signal \y[7]_i_24_n_0\ : STD_LOGIC;
signal \y[7]_i_25_n_0\ : STD_LOGIC;
signal \y[7]_i_26_n_0\ : STD_LOGIC;
signal \y[7]_i_27_n_0\ : STD_LOGIC;
signal \y[7]_i_28_n_0\ : STD_LOGIC;
signal \y[7]_i_2_n_0\ : STD_LOGIC;
signal \y[7]_i_4_n_0\ : STD_LOGIC;
signal \y[7]_i_5_n_0\ : STD_LOGIC;
signal \y[7]_i_6_n_0\ : STD_LOGIC;
signal \y[7]_i_7_n_0\ : STD_LOGIC;
signal \y[7]_i_8_n_0\ : STD_LOGIC;
signal \y[7]_i_9_n_0\ : STD_LOGIC;
signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \y_int[11]_i_100_n_0\ : STD_LOGIC;
signal \y_int[11]_i_10_n_0\ : STD_LOGIC;
signal \y_int[11]_i_12_n_0\ : STD_LOGIC;
signal \y_int[11]_i_16_n_0\ : STD_LOGIC;
signal \y_int[11]_i_19_n_0\ : STD_LOGIC;
signal \y_int[11]_i_29_n_0\ : STD_LOGIC;
signal \y_int[11]_i_2_n_0\ : STD_LOGIC;
signal \y_int[11]_i_30_n_0\ : STD_LOGIC;
signal \y_int[11]_i_31_n_0\ : STD_LOGIC;
signal \y_int[11]_i_32_n_0\ : STD_LOGIC;
signal \y_int[11]_i_34_n_0\ : STD_LOGIC;
signal \y_int[11]_i_35_n_0\ : STD_LOGIC;
signal \y_int[11]_i_36_n_0\ : STD_LOGIC;
signal \y_int[11]_i_37_n_0\ : STD_LOGIC;
signal \y_int[11]_i_3_n_0\ : STD_LOGIC;
signal \y_int[11]_i_40_n_0\ : STD_LOGIC;
signal \y_int[11]_i_41_n_0\ : STD_LOGIC;
signal \y_int[11]_i_42_n_0\ : STD_LOGIC;
signal \y_int[11]_i_43_n_0\ : STD_LOGIC;
signal \y_int[11]_i_45_n_0\ : STD_LOGIC;
signal \y_int[11]_i_46_n_0\ : STD_LOGIC;
signal \y_int[11]_i_47_n_0\ : STD_LOGIC;
signal \y_int[11]_i_48_n_0\ : STD_LOGIC;
signal \y_int[11]_i_4_n_0\ : STD_LOGIC;
signal \y_int[11]_i_50_n_0\ : STD_LOGIC;
signal \y_int[11]_i_51_n_0\ : STD_LOGIC;
signal \y_int[11]_i_52_n_0\ : STD_LOGIC;
signal \y_int[11]_i_53_n_0\ : STD_LOGIC;
signal \y_int[11]_i_58_n_0\ : STD_LOGIC;
signal \y_int[11]_i_59_n_0\ : STD_LOGIC;
signal \y_int[11]_i_5_n_0\ : STD_LOGIC;
signal \y_int[11]_i_60_n_0\ : STD_LOGIC;
signal \y_int[11]_i_61_n_0\ : STD_LOGIC;
signal \y_int[11]_i_62_n_0\ : STD_LOGIC;
signal \y_int[11]_i_63_n_0\ : STD_LOGIC;
signal \y_int[11]_i_64_n_0\ : STD_LOGIC;
signal \y_int[11]_i_65_n_0\ : STD_LOGIC;
signal \y_int[11]_i_66_n_0\ : STD_LOGIC;
signal \y_int[11]_i_67_n_0\ : STD_LOGIC;
signal \y_int[11]_i_68_n_0\ : STD_LOGIC;
signal \y_int[11]_i_69_n_0\ : STD_LOGIC;
signal \y_int[11]_i_6_n_0\ : STD_LOGIC;
signal \y_int[11]_i_70_n_0\ : STD_LOGIC;
signal \y_int[11]_i_71_n_0\ : STD_LOGIC;
signal \y_int[11]_i_72_n_0\ : STD_LOGIC;
signal \y_int[11]_i_73_n_0\ : STD_LOGIC;
signal \y_int[11]_i_74_n_0\ : STD_LOGIC;
signal \y_int[11]_i_75_n_0\ : STD_LOGIC;
signal \y_int[11]_i_76_n_0\ : STD_LOGIC;
signal \y_int[11]_i_77_n_0\ : STD_LOGIC;
signal \y_int[11]_i_78_n_0\ : STD_LOGIC;
signal \y_int[11]_i_79_n_0\ : STD_LOGIC;
signal \y_int[11]_i_7_n_0\ : STD_LOGIC;
signal \y_int[11]_i_81_n_0\ : STD_LOGIC;
signal \y_int[11]_i_82_n_0\ : STD_LOGIC;
signal \y_int[11]_i_83_n_0\ : STD_LOGIC;
signal \y_int[11]_i_84_n_0\ : STD_LOGIC;
signal \y_int[11]_i_86_n_0\ : STD_LOGIC;
signal \y_int[11]_i_87_n_0\ : STD_LOGIC;
signal \y_int[11]_i_88_n_0\ : STD_LOGIC;
signal \y_int[11]_i_89_n_0\ : STD_LOGIC;
signal \y_int[11]_i_8_n_0\ : STD_LOGIC;
signal \y_int[11]_i_90_n_0\ : STD_LOGIC;
signal \y_int[11]_i_91_n_0\ : STD_LOGIC;
signal \y_int[11]_i_92_n_0\ : STD_LOGIC;
signal \y_int[11]_i_93_n_0\ : STD_LOGIC;
signal \y_int[11]_i_94_n_0\ : STD_LOGIC;
signal \y_int[11]_i_95_n_0\ : STD_LOGIC;
signal \y_int[11]_i_96_n_0\ : STD_LOGIC;
signal \y_int[11]_i_97_n_0\ : STD_LOGIC;
signal \y_int[11]_i_98_n_0\ : STD_LOGIC;
signal \y_int[11]_i_99_n_0\ : STD_LOGIC;
signal \y_int[11]_i_9_n_0\ : STD_LOGIC;
signal \y_int[15]_i_10_n_0\ : STD_LOGIC;
signal \y_int[15]_i_12_n_0\ : STD_LOGIC;
signal \y_int[15]_i_16_n_0\ : STD_LOGIC;
signal \y_int[15]_i_18_n_0\ : STD_LOGIC;
signal \y_int[15]_i_25_n_0\ : STD_LOGIC;
signal \y_int[15]_i_26_n_0\ : STD_LOGIC;
signal \y_int[15]_i_27_n_0\ : STD_LOGIC;
signal \y_int[15]_i_28_n_0\ : STD_LOGIC;
signal \y_int[15]_i_29_n_0\ : STD_LOGIC;
signal \y_int[15]_i_2_n_0\ : STD_LOGIC;
signal \y_int[15]_i_30_n_0\ : STD_LOGIC;
signal \y_int[15]_i_31_n_0\ : STD_LOGIC;
signal \y_int[15]_i_32_n_0\ : STD_LOGIC;
signal \y_int[15]_i_3_n_0\ : STD_LOGIC;
signal \y_int[15]_i_40_n_0\ : STD_LOGIC;
signal \y_int[15]_i_41_n_0\ : STD_LOGIC;
signal \y_int[15]_i_42_n_0\ : STD_LOGIC;
signal \y_int[15]_i_43_n_0\ : STD_LOGIC;
signal \y_int[15]_i_48_n_0\ : STD_LOGIC;
signal \y_int[15]_i_49_n_0\ : STD_LOGIC;
signal \y_int[15]_i_4_n_0\ : STD_LOGIC;
signal \y_int[15]_i_50_n_0\ : STD_LOGIC;
signal \y_int[15]_i_51_n_0\ : STD_LOGIC;
signal \y_int[15]_i_5_n_0\ : STD_LOGIC;
signal \y_int[15]_i_6_n_0\ : STD_LOGIC;
signal \y_int[15]_i_7_n_0\ : STD_LOGIC;
signal \y_int[15]_i_8_n_0\ : STD_LOGIC;
signal \y_int[15]_i_9_n_0\ : STD_LOGIC;
signal \y_int[19]_i_10_n_0\ : STD_LOGIC;
signal \y_int[19]_i_12_n_0\ : STD_LOGIC;
signal \y_int[19]_i_16_n_0\ : STD_LOGIC;
signal \y_int[19]_i_18_n_0\ : STD_LOGIC;
signal \y_int[19]_i_25_n_0\ : STD_LOGIC;
signal \y_int[19]_i_26_n_0\ : STD_LOGIC;
signal \y_int[19]_i_27_n_0\ : STD_LOGIC;
signal \y_int[19]_i_28_n_0\ : STD_LOGIC;
signal \y_int[19]_i_29_n_0\ : STD_LOGIC;
signal \y_int[19]_i_2_n_0\ : STD_LOGIC;
signal \y_int[19]_i_30_n_0\ : STD_LOGIC;
signal \y_int[19]_i_31_n_0\ : STD_LOGIC;
signal \y_int[19]_i_32_n_0\ : STD_LOGIC;
signal \y_int[19]_i_3_n_0\ : STD_LOGIC;
signal \y_int[19]_i_48_n_0\ : STD_LOGIC;
signal \y_int[19]_i_49_n_0\ : STD_LOGIC;
signal \y_int[19]_i_4_n_0\ : STD_LOGIC;
signal \y_int[19]_i_50_n_0\ : STD_LOGIC;
signal \y_int[19]_i_51_n_0\ : STD_LOGIC;
signal \y_int[19]_i_5_n_0\ : STD_LOGIC;
signal \y_int[19]_i_6_n_0\ : STD_LOGIC;
signal \y_int[19]_i_7_n_0\ : STD_LOGIC;
signal \y_int[19]_i_8_n_0\ : STD_LOGIC;
signal \y_int[19]_i_9_n_0\ : STD_LOGIC;
signal \y_int[23]_i_100_n_0\ : STD_LOGIC;
signal \y_int[23]_i_101_n_0\ : STD_LOGIC;
signal \y_int[23]_i_102_n_0\ : STD_LOGIC;
signal \y_int[23]_i_103_n_0\ : STD_LOGIC;
signal \y_int[23]_i_104_n_0\ : STD_LOGIC;
signal \y_int[23]_i_12_n_0\ : STD_LOGIC;
signal \y_int[23]_i_14_n_0\ : STD_LOGIC;
signal \y_int[23]_i_18_n_0\ : STD_LOGIC;
signal \y_int[23]_i_20_n_0\ : STD_LOGIC;
signal \y_int[23]_i_26_n_0\ : STD_LOGIC;
signal \y_int[23]_i_27_n_0\ : STD_LOGIC;
signal \y_int[23]_i_28_n_0\ : STD_LOGIC;
signal \y_int[23]_i_29_n_0\ : STD_LOGIC;
signal \y_int[23]_i_2_n_0\ : STD_LOGIC;
signal \y_int[23]_i_30_n_0\ : STD_LOGIC;
signal \y_int[23]_i_31_n_0\ : STD_LOGIC;
signal \y_int[23]_i_36_n_0\ : STD_LOGIC;
signal \y_int[23]_i_37_n_0\ : STD_LOGIC;
signal \y_int[23]_i_38_n_0\ : STD_LOGIC;
signal \y_int[23]_i_39_n_0\ : STD_LOGIC;
signal \y_int[23]_i_3_n_0\ : STD_LOGIC;
signal \y_int[23]_i_40_n_0\ : STD_LOGIC;
signal \y_int[23]_i_41_n_0\ : STD_LOGIC;
signal \y_int[23]_i_42_n_0\ : STD_LOGIC;
signal \y_int[23]_i_43_n_0\ : STD_LOGIC;
signal \y_int[23]_i_46_n_0\ : STD_LOGIC;
signal \y_int[23]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_48_n_0\ : STD_LOGIC;
signal \y_int[23]_i_49_n_0\ : STD_LOGIC;
signal \y_int[23]_i_4_n_0\ : STD_LOGIC;
signal \y_int[23]_i_52_n_0\ : STD_LOGIC;
signal \y_int[23]_i_53_n_0\ : STD_LOGIC;
signal \y_int[23]_i_54_n_0\ : STD_LOGIC;
signal \y_int[23]_i_55_n_0\ : STD_LOGIC;
signal \y_int[23]_i_56_n_0\ : STD_LOGIC;
signal \y_int[23]_i_57_n_0\ : STD_LOGIC;
signal \y_int[23]_i_5_n_0\ : STD_LOGIC;
signal \y_int[23]_i_62_n_0\ : STD_LOGIC;
signal \y_int[23]_i_63_n_0\ : STD_LOGIC;
signal \y_int[23]_i_64_n_0\ : STD_LOGIC;
signal \y_int[23]_i_65_n_0\ : STD_LOGIC;
signal \y_int[23]_i_67_n_0\ : STD_LOGIC;
signal \y_int[23]_i_68_n_0\ : STD_LOGIC;
signal \y_int[23]_i_69_n_0\ : STD_LOGIC;
signal \y_int[23]_i_6_n_0\ : STD_LOGIC;
signal \y_int[23]_i_70_n_0\ : STD_LOGIC;
signal \y_int[23]_i_71_n_0\ : STD_LOGIC;
signal \y_int[23]_i_72_n_0\ : STD_LOGIC;
signal \y_int[23]_i_73_n_0\ : STD_LOGIC;
signal \y_int[23]_i_74_n_0\ : STD_LOGIC;
signal \y_int[23]_i_76_n_0\ : STD_LOGIC;
signal \y_int[23]_i_77_n_0\ : STD_LOGIC;
signal \y_int[23]_i_78_n_0\ : STD_LOGIC;
signal \y_int[23]_i_79_n_0\ : STD_LOGIC;
signal \y_int[23]_i_7_n_0\ : STD_LOGIC;
signal \y_int[23]_i_80_n_0\ : STD_LOGIC;
signal \y_int[23]_i_81_n_0\ : STD_LOGIC;
signal \y_int[23]_i_82_n_0\ : STD_LOGIC;
signal \y_int[23]_i_83_n_0\ : STD_LOGIC;
signal \y_int[23]_i_84_n_0\ : STD_LOGIC;
signal \y_int[23]_i_85_n_0\ : STD_LOGIC;
signal \y_int[23]_i_86_n_0\ : STD_LOGIC;
signal \y_int[23]_i_87_n_0\ : STD_LOGIC;
signal \y_int[23]_i_88_n_0\ : STD_LOGIC;
signal \y_int[23]_i_8_n_0\ : STD_LOGIC;
signal \y_int[23]_i_90_n_0\ : STD_LOGIC;
signal \y_int[23]_i_91_n_0\ : STD_LOGIC;
signal \y_int[23]_i_92_n_0\ : STD_LOGIC;
signal \y_int[23]_i_93_n_0\ : STD_LOGIC;
signal \y_int[23]_i_94_n_0\ : STD_LOGIC;
signal \y_int[23]_i_95_n_0\ : STD_LOGIC;
signal \y_int[23]_i_96_n_0\ : STD_LOGIC;
signal \y_int[23]_i_97_n_0\ : STD_LOGIC;
signal \y_int[23]_i_98_n_0\ : STD_LOGIC;
signal \y_int[23]_i_99_n_0\ : STD_LOGIC;
signal \y_int[23]_i_9_n_0\ : STD_LOGIC;
signal \y_int[27]_i_2_n_0\ : STD_LOGIC;
signal \y_int[27]_i_3_n_0\ : STD_LOGIC;
signal \y_int[27]_i_4_n_0\ : STD_LOGIC;
signal \y_int[27]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_101_n_0\ : STD_LOGIC;
signal \y_int[31]_i_104_n_0\ : STD_LOGIC;
signal \y_int[31]_i_105_n_0\ : STD_LOGIC;
signal \y_int[31]_i_106_n_0\ : STD_LOGIC;
signal \y_int[31]_i_107_n_0\ : STD_LOGIC;
signal \y_int[31]_i_108_n_0\ : STD_LOGIC;
signal \y_int[31]_i_109_n_0\ : STD_LOGIC;
signal \y_int[31]_i_110_n_0\ : STD_LOGIC;
signal \y_int[31]_i_111_n_0\ : STD_LOGIC;
signal \y_int[31]_i_112_n_0\ : STD_LOGIC;
signal \y_int[31]_i_113_n_0\ : STD_LOGIC;
signal \y_int[31]_i_114_n_0\ : STD_LOGIC;
signal \y_int[31]_i_115_n_0\ : STD_LOGIC;
signal \y_int[31]_i_116_n_0\ : STD_LOGIC;
signal \y_int[31]_i_13_n_0\ : STD_LOGIC;
signal \y_int[31]_i_14_n_0\ : STD_LOGIC;
signal \y_int[31]_i_15_n_0\ : STD_LOGIC;
signal \y_int[31]_i_17_n_0\ : STD_LOGIC;
signal \y_int[31]_i_18_n_0\ : STD_LOGIC;
signal \y_int[31]_i_19_n_0\ : STD_LOGIC;
signal \y_int[31]_i_20_n_0\ : STD_LOGIC;
signal \y_int[31]_i_2_n_0\ : STD_LOGIC;
signal \y_int[31]_i_32_n_0\ : STD_LOGIC;
signal \y_int[31]_i_33_n_0\ : STD_LOGIC;
signal \y_int[31]_i_34_n_0\ : STD_LOGIC;
signal \y_int[31]_i_35_n_0\ : STD_LOGIC;
signal \y_int[31]_i_36_n_0\ : STD_LOGIC;
signal \y_int[31]_i_3_n_0\ : STD_LOGIC;
signal \y_int[31]_i_40_n_0\ : STD_LOGIC;
signal \y_int[31]_i_41_n_0\ : STD_LOGIC;
signal \y_int[31]_i_42_n_0\ : STD_LOGIC;
signal \y_int[31]_i_43_n_0\ : STD_LOGIC;
signal \y_int[31]_i_44_n_0\ : STD_LOGIC;
signal \y_int[31]_i_45_n_0\ : STD_LOGIC;
signal \y_int[31]_i_46_n_0\ : STD_LOGIC;
signal \y_int[31]_i_47_n_0\ : STD_LOGIC;
signal \y_int[31]_i_4_n_0\ : STD_LOGIC;
signal \y_int[31]_i_5_n_0\ : STD_LOGIC;
signal \y_int[31]_i_63_n_0\ : STD_LOGIC;
signal \y_int[31]_i_64_n_0\ : STD_LOGIC;
signal \y_int[31]_i_65_n_0\ : STD_LOGIC;
signal \y_int[31]_i_66_n_0\ : STD_LOGIC;
signal \y_int[31]_i_67_n_0\ : STD_LOGIC;
signal \y_int[31]_i_68_n_0\ : STD_LOGIC;
signal \y_int[31]_i_69_n_0\ : STD_LOGIC;
signal \y_int[31]_i_6_n_0\ : STD_LOGIC;
signal \y_int[31]_i_70_n_0\ : STD_LOGIC;
signal \y_int[31]_i_89_n_0\ : STD_LOGIC;
signal \y_int[31]_i_90_n_0\ : STD_LOGIC;
signal \y_int[31]_i_91_n_0\ : STD_LOGIC;
signal \y_int[31]_i_92_n_0\ : STD_LOGIC;
signal \y_int[3]_i_10_n_0\ : STD_LOGIC;
signal \y_int[3]_i_13_n_0\ : STD_LOGIC;
signal \y_int[3]_i_17_n_0\ : STD_LOGIC;
signal \y_int[3]_i_18_n_0\ : STD_LOGIC;
signal \y_int[3]_i_22_n_0\ : STD_LOGIC;
signal \y_int[3]_i_23_n_0\ : STD_LOGIC;
signal \y_int[3]_i_24_n_0\ : STD_LOGIC;
signal \y_int[3]_i_25_n_0\ : STD_LOGIC;
signal \y_int[3]_i_27_n_0\ : STD_LOGIC;
signal \y_int[3]_i_28_n_0\ : STD_LOGIC;
signal \y_int[3]_i_29_n_0\ : STD_LOGIC;
signal \y_int[3]_i_2_n_0\ : STD_LOGIC;
signal \y_int[3]_i_31_n_0\ : STD_LOGIC;
signal \y_int[3]_i_32_n_0\ : STD_LOGIC;
signal \y_int[3]_i_33_n_0\ : STD_LOGIC;
signal \y_int[3]_i_34_n_0\ : STD_LOGIC;
signal \y_int[3]_i_3_n_0\ : STD_LOGIC;
signal \y_int[3]_i_4_n_0\ : STD_LOGIC;
signal \y_int[3]_i_50_n_0\ : STD_LOGIC;
signal \y_int[3]_i_51_n_0\ : STD_LOGIC;
signal \y_int[3]_i_52_n_0\ : STD_LOGIC;
signal \y_int[3]_i_53_n_0\ : STD_LOGIC;
signal \y_int[3]_i_54_n_0\ : STD_LOGIC;
signal \y_int[3]_i_56_n_0\ : STD_LOGIC;
signal \y_int[3]_i_57_n_0\ : STD_LOGIC;
signal \y_int[3]_i_58_n_0\ : STD_LOGIC;
signal \y_int[3]_i_59_n_0\ : STD_LOGIC;
signal \y_int[3]_i_5_n_0\ : STD_LOGIC;
signal \y_int[3]_i_60_n_0\ : STD_LOGIC;
signal \y_int[3]_i_61_n_0\ : STD_LOGIC;
signal \y_int[3]_i_62_n_0\ : STD_LOGIC;
signal \y_int[3]_i_63_n_0\ : STD_LOGIC;
signal \y_int[3]_i_66_n_0\ : STD_LOGIC;
signal \y_int[3]_i_67_n_0\ : STD_LOGIC;
signal \y_int[3]_i_68_n_0\ : STD_LOGIC;
signal \y_int[3]_i_69_n_0\ : STD_LOGIC;
signal \y_int[3]_i_6_n_0\ : STD_LOGIC;
signal \y_int[3]_i_71_n_0\ : STD_LOGIC;
signal \y_int[3]_i_72_n_0\ : STD_LOGIC;
signal \y_int[3]_i_73_n_0\ : STD_LOGIC;
signal \y_int[3]_i_74_n_0\ : STD_LOGIC;
signal \y_int[3]_i_7_n_0\ : STD_LOGIC;
signal \y_int[3]_i_84_n_0\ : STD_LOGIC;
signal \y_int[3]_i_85_n_0\ : STD_LOGIC;
signal \y_int[3]_i_86_n_0\ : STD_LOGIC;
signal \y_int[3]_i_87_n_0\ : STD_LOGIC;
signal \y_int[3]_i_88_n_0\ : STD_LOGIC;
signal \y_int[3]_i_89_n_0\ : STD_LOGIC;
signal \y_int[3]_i_8_n_0\ : STD_LOGIC;
signal \y_int[3]_i_90_n_0\ : STD_LOGIC;
signal \y_int[3]_i_91_n_0\ : STD_LOGIC;
signal \y_int[3]_i_92_n_0\ : STD_LOGIC;
signal \y_int[7]_i_11_n_0\ : STD_LOGIC;
signal \y_int[7]_i_13_n_0\ : STD_LOGIC;
signal \y_int[7]_i_16_n_0\ : STD_LOGIC;
signal \y_int[7]_i_19_n_0\ : STD_LOGIC;
signal \y_int[7]_i_29_n_0\ : STD_LOGIC;
signal \y_int[7]_i_2_n_0\ : STD_LOGIC;
signal \y_int[7]_i_30_n_0\ : STD_LOGIC;
signal \y_int[7]_i_31_n_0\ : STD_LOGIC;
signal \y_int[7]_i_32_n_0\ : STD_LOGIC;
signal \y_int[7]_i_33_n_0\ : STD_LOGIC;
signal \y_int[7]_i_3_n_0\ : STD_LOGIC;
signal \y_int[7]_i_4_n_0\ : STD_LOGIC;
signal \y_int[7]_i_5_n_0\ : STD_LOGIC;
signal \y_int[7]_i_6_n_0\ : STD_LOGIC;
signal \y_int[7]_i_7_n_0\ : STD_LOGIC;
signal \y_int[7]_i_8_n_0\ : STD_LOGIC;
signal \y_int[7]_i_9_n_0\ : STD_LOGIC;
signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 );
signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 );
signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 );
signal y_int_reg6 : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC;
signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC;
signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC;
signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \y_int_reg_n_0_[0]\ : STD_LOGIC;
signal \y_int_reg_n_0_[1]\ : STD_LOGIC;
signal \y_int_reg_n_0_[2]\ : STD_LOGIC;
signal \y_int_reg_n_0_[3]\ : STD_LOGIC;
signal \y_int_reg_n_0_[4]\ : STD_LOGIC;
signal \y_int_reg_n_0_[5]\ : STD_LOGIC;
signal \y_int_reg_n_0_[6]\ : STD_LOGIC;
signal \y_int_reg_n_0_[7]\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_12_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_0\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_1\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_2\ : STD_LOGIC;
signal \y_reg[7]_i_3_n_3\ : STD_LOGIC;
signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC;
signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC;
signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute \__SRVAL\ : string;
attribute \__SRVAL\ of ODDR_inst : label is "TRUE";
attribute box_type : string;
attribute box_type of ODDR_inst : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34";
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6";
attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9";
attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8";
attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7";
attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6";
attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10";
attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9";
attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13";
attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12";
attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11";
attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10";
attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14";
attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13";
attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17";
attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16";
attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15";
attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14";
attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20";
attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19";
attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18";
attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17";
attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21";
attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20";
attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19";
attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18";
attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21";
attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18";
attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair39";
attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2";
attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1";
attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair39";
attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4";
attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3";
attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5";
attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4";
attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair26";
attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29";
attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29";
attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair30";
attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair30";
attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair31";
attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair31";
attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair32";
attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair32";
attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20";
attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23";
attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23";
attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22";
attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair40";
attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25";
attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24";
attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair40";
attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27";
attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26";
attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28";
attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27";
attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21";
attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair33";
attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair35";
attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair34";
attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair33";
attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair37";
attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair36";
attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair38";
attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair37";
begin
CO(0) <= \^co\(0);
DI(0) <= \^di\(0);
O(1 downto 0) <= \^o\(1 downto 0);
\cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0);
\cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0);
\cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0);
\cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0);
\cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0);
\cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0);
\cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\;
\cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0);
\cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0);
\cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\;
\cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\;
\cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0);
\cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0);
\cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0);
\cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0);
\cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0);
\cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0);
\y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0);
\y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0);
\y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0);
\y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0);
\y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0);
\y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0);
\y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0);
\y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0);
Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender
port map (
clk_100 => clk_100,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
ODDR_inst: unisim.vcomponents.ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
IS_C_INVERTED => '0',
IS_D1_INVERTED => '0',
IS_D2_INVERTED => '0',
SRTYPE => "SYNC"
)
port map (
C => clk_x2,
CE => '1',
D1 => D1,
D2 => D1,
Q => hdmi_clk,
R => NLW_ODDR_inst_R_UNCONNECTED,
S => NLW_ODDR_inst_S_UNCONNECTED
);
\cb[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[0]\,
I1 => \cb_int_reg__0\(31),
O => \cb[0]_i_1_n_0\
);
\cb[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[1]\,
I1 => \cb_int_reg__0\(31),
O => \cb[1]_i_1_n_0\
);
\cb[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[2]\,
I1 => \cb_int_reg__0\(31),
O => \cb[2]_i_1_n_0\
);
\cb[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[3]\,
I1 => \cb_int_reg__0\(31),
O => \cb[3]_i_1_n_0\
);
\cb[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[4]\,
I1 => \cb_int_reg__0\(31),
O => \cb[4]_i_1_n_0\
);
\cb[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[5]\,
I1 => \cb_int_reg__0\(31),
O => \cb[5]_i_1_n_0\
);
\cb[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[6]\,
I1 => \cb_int_reg__0\(31),
O => \cb[6]_i_1_n_0\
);
\cb[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_10_n_0\
);
\cb[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_11_n_0\
);
\cb[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_13_n_0\
);
\cb[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_14_n_0\
);
\cb[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_15_n_0\
);
\cb[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_16_n_0\
);
\cb[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(22),
I1 => \cb_int_reg__0\(23),
O => \cb[7]_i_17_n_0\
);
\cb[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(20),
I1 => \cb_int_reg__0\(21),
O => \cb[7]_i_18_n_0\
);
\cb[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(18),
I1 => \cb_int_reg__0\(19),
O => \cb[7]_i_19_n_0\
);
\cb[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg_n_0_[7]\,
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_2_n_0\
);
\cb[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(16),
I1 => \cb_int_reg__0\(17),
O => \cb[7]_i_20_n_0\
);
\cb[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_21_n_0\
);
\cb[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_22_n_0\
);
\cb[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_23_n_0\
);
\cb[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_24_n_0\
);
\cb[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(14),
I1 => \cb_int_reg__0\(15),
O => \cb[7]_i_25_n_0\
);
\cb[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(12),
I1 => \cb_int_reg__0\(13),
O => \cb[7]_i_26_n_0\
);
\cb[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(10),
I1 => \cb_int_reg__0\(11),
O => \cb[7]_i_27_n_0\
);
\cb[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(8),
I1 => \cb_int_reg__0\(9),
O => \cb[7]_i_28_n_0\
);
\cb[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_4_n_0\
);
\cb[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_5_n_0\
);
\cb[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(26),
I1 => \cb_int_reg__0\(27),
O => \cb[7]_i_6_n_0\
);
\cb[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg__0\(24),
I1 => \cb_int_reg__0\(25),
O => \cb[7]_i_7_n_0\
);
\cb[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(30),
I1 => \cb_int_reg__0\(31),
O => \cb[7]_i_8_n_0\
);
\cb[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg__0\(28),
I1 => \cb_int_reg__0\(29),
O => \cb[7]_i_9_n_0\
);
\cb_hold[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => edge,
I1 => edge_rb,
O => \cb_hold[7]_i_1_n_0\
);
\cb_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(0),
Q => cb_hold(0),
R => '0'
);
\cb_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(1),
Q => cb_hold(1),
R => '0'
);
\cb_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(2),
Q => cb_hold(2),
R => '0'
);
\cb_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(3),
Q => cb_hold(3),
R => '0'
);
\cb_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(4),
Q => cb_hold(4),
R => '0'
);
\cb_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(5),
Q => cb_hold(5),
R => '0'
);
\cb_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(6),
Q => cb_hold(6),
R => '0'
);
\cb_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cb(7),
Q => cb_hold(7),
R => '0'
);
\cb_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[11]_i_10_n_0\
);
\cb_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
I1 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[11]_i_100_n_0\
);
\cb_int[11]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
I1 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[11]_i_101_n_0\
);
\cb_int[11]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
I1 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[11]_i_102_n_0\
);
\cb_int[11]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
I1 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_103_n_0\
);
\cb_int[11]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
I1 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[11]_i_104_n_0\
);
\cb_int[11]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
I1 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[11]_i_105_n_0\
);
\cb_int[11]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
I1 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[11]_i_106_n_0\
);
\cb_int[11]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
I1 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[11]_i_107_n_0\
);
\cb_int[11]_i_108\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
I1 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[11]_i_108_n_0\
);
\cb_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
I1 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[11]_i_109_n_0\
);
\cb_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_11_n_0\
);
\cb_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
I1 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[11]_i_110_n_0\
);
\cb_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
I1 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[11]_i_111_n_0\
);
\cb_int[11]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
I1 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[11]_i_112_n_0\
);
\cb_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
I1 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[11]_i_113_n_0\
);
\cb_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
I1 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[11]_i_114_n_0\
);
\cb_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(9),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(17),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_20_n_0\,
I5 => cb_int_reg2(9),
O => \cb_int[11]_i_12_n_0\
);
\cb_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_13_n_0\
);
\cb_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(8),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(16),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_22_n_0\,
I5 => cb_int_reg2(8),
O => \cb_int[11]_i_14_n_0\
);
\cb_int[11]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFE200E2"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_15_n_0\
);
\cb_int[11]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E2001DFF1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
I3 => \rgb888[0]\(3),
I4 => cb_int_reg3(7),
I5 => \cb_int[11]_i_27_n_0\,
O => \cb_int[11]_i_19_n_0\
);
\cb_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
O => \cb_int[11]_i_2_n_0\
);
\cb_int[11]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(0),
O => \cb_int[11]_i_20_n_0\
);
\cb_int[11]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(9),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(9)
);
\cb_int[11]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_3\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]\(3),
O => \cb_int[11]_i_22_n_0\
);
\cb_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(8),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_4\,
O => cb_int_reg2(8)
);
\cb_int[11]_i_27\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_1\(0),
O => \cb_int[11]_i_27_n_0\
);
\cb_int[11]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(16),
O => \cb_int[11]_i_29_n_0\
);
\cb_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
O => \cb_int[11]_i_3_n_0\
);
\cb_int[11]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(15),
O => \cb_int[11]_i_30_n_0\
);
\cb_int[11]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_31_n_0\
);
\cb_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_32_n_0\
);
\cb_int[11]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_34_n_0\
);
\cb_int[11]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_35_n_0\
);
\cb_int[11]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_36_n_0\
);
\cb_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_37_n_0\
);
\cb_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_39_n_0\
);
\cb_int[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
O => \cb_int[11]_i_4_n_0\
);
\cb_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_40_n_0\
);
\cb_int[11]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_41_n_0\
);
\cb_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_42_n_0\
);
\cb_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_43_n_0\
);
\cb_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(2),
O => \cb_int[11]_i_44_n_0\
);
\cb_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
O => \cb_int[11]_i_45_n_0\
);
\cb_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(0),
O => \cb_int[11]_i_46_n_0\
);
\cb_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_47_n_0\
);
\cb_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_49_n_0\
);
\cb_int[11]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DD1D0000"
)
port map (
I0 => cb_int_reg5(7),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(15),
I3 => cb_int_reg8,
I4 => \cb_int[11]_i_19_n_0\,
O => \cb_int[11]_i_5_n_0\
);
\cb_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_50_n_0\
);
\cb_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_51_n_0\
);
\cb_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_52_n_0\
);
\cb_int[11]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(2),
O => \cb_int[11]_i_53_n_0\
);
\cb_int[11]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(1),
O => \cb_int[11]_i_54_n_0\
);
\cb_int[11]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]\(0),
O => \cb_int[11]_i_55_n_0\
);
\cb_int[11]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[11]_i_24_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_56_n_0\
);
\cb_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[11]_i_57_n_0\
);
\cb_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_58_n_0\
);
\cb_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_59_n_0\
);
\cb_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
I2 => \cb_int[11]_i_2_n_0\,
O => \cb_int[11]_i_6_n_0\
);
\cb_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_60_n_0\
);
\cb_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_61_n_0\
);
\cb_int[11]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_62_n_0\
);
\cb_int[11]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_63_n_0\
);
\cb_int[11]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_64_n_0\
);
\cb_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_65_n_0\
);
\cb_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_67_n_0\
);
\cb_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_68_n_0\
);
\cb_int[11]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_69_n_0\
);
\cb_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_10_n_0\,
I1 => \cb_int[11]_i_11_n_0\,
I2 => \cb_int[11]_i_3_n_0\,
O => \cb_int[11]_i_7_n_0\
);
\cb_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_70_n_0\
);
\cb_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_71_n_0\
);
\cb_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_72_n_0\
);
\cb_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_73_n_0\
);
\cb_int[11]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_74_n_0\
);
\cb_int[11]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(2),
I1 => \rgb888[0]\(3),
O => \cb_int[11]_i_76_n_0\
);
\cb_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_77_n_0\
);
\cb_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_78_n_0\
);
\cb_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
O => \cb_int[11]_i_79_n_0\
);
\cb_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_12_n_0\,
I1 => \cb_int[11]_i_13_n_0\,
I2 => \cb_int[11]_i_4_n_0\,
O => \cb_int[11]_i_8_n_0\
);
\cb_int[11]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \rgb888[0]\(2),
O => \cb_int[11]_i_80_n_0\
);
\cb_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_82_n_0\
);
\cb_int[11]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_6\,
I1 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_83_n_0\
);
\cb_int[11]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_4\,
I1 => \cb_int_reg[31]_i_12_n_7\,
O => \cb_int[11]_i_84_n_0\
);
\cb_int[11]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
I1 => \cb_int_reg[31]_i_33_n_5\,
O => \cb_int[11]_i_85_n_0\
);
\cb_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[11]_i_86_n_0\
);
\cb_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_12_n_6\,
O => \cb_int[11]_i_87_n_0\
);
\cb_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_7\,
I1 => \cb_int_reg[31]_i_33_n_4\,
O => \cb_int[11]_i_88_n_0\
);
\cb_int[11]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_5\,
I1 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[11]_i_89_n_0\
);
\cb_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[11]_i_14_n_0\,
I1 => \cb_int[11]_i_15_n_0\,
I2 => \cb_int[11]_i_5_n_0\,
O => \cb_int[11]_i_9_n_0\
);
\cb_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]\(0),
I1 => \rgb888[0]\(1),
O => \cb_int[11]_i_91_n_0\
);
\cb_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(2),
I1 => \rgb888[0]_0\(3),
O => \cb_int[11]_i_92_n_0\
);
\cb_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[0]_0\(0),
I1 => \rgb888[0]_0\(1),
O => \cb_int[11]_i_93_n_0\
);
\cb_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[11]_i_94_n_0\
);
\cb_int[11]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]\(1),
I1 => \rgb888[0]\(0),
O => \cb_int[11]_i_95_n_0\
);
\cb_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(3),
I1 => \rgb888[0]_0\(2),
O => \cb_int[11]_i_96_n_0\
);
\cb_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
I1 => \rgb888[0]_0\(0),
O => \cb_int[11]_i_97_n_0\
);
\cb_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
I1 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[11]_i_98_n_0\
);
\cb_int[11]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
I1 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[11]_i_99_n_0\
);
\cb_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[15]_i_10_n_0\
);
\cb_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_11_n_0\
);
\cb_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(13),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(21),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_18_n_0\,
I5 => cb_int_reg2(13),
O => \cb_int[15]_i_12_n_0\
);
\cb_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_13_n_0\
);
\cb_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(12),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(20),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_21_n_0\,
I5 => cb_int_reg2(12),
O => \cb_int[15]_i_14_n_0\
);
\cb_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_15_n_0\
);
\cb_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(11),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(19),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_23_n_0\,
I5 => cb_int_reg2(11),
O => \cb_int[15]_i_16_n_0\
);
\cb_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(10),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(18),
I3 => cb_int_reg8,
I4 => \cb_int[15]_i_25_n_0\,
I5 => cb_int_reg2(10),
O => \cb_int[15]_i_17_n_0\
);
\cb_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(0),
O => \cb_int[15]_i_18_n_0\
);
\cb_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(13),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(13)
);
\cb_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
O => \cb_int[15]_i_2_n_0\
);
\cb_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(3),
O => \cb_int[15]_i_21_n_0\
);
\cb_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(12),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(12)
);
\cb_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(2),
O => \cb_int[15]_i_23_n_0\
);
\cb_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(11),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(11)
);
\cb_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_4\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[12]_0\(1),
O => \cb_int[15]_i_25_n_0\
);
\cb_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(10),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_4\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(10)
);
\cb_int[15]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(20),
O => \cb_int[15]_i_27_n_0\
);
\cb_int[15]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(19),
O => \cb_int[15]_i_28_n_0\
);
\cb_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(18),
O => \cb_int[15]_i_29_n_0\
);
\cb_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
O => \cb_int[15]_i_3_n_0\
);
\cb_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(17),
O => \cb_int[15]_i_30_n_0\
);
\cb_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
O => \cb_int[15]_i_4_n_0\
);
\cb_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(3),
O => \cb_int[15]_i_43_n_0\
);
\cb_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(2),
O => \cb_int[15]_i_44_n_0\
);
\cb_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(1),
O => \cb_int[15]_i_45_n_0\
);
\cb_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_4\(0),
O => \cb_int[15]_i_46_n_0\
);
\cb_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[15]_i_16_n_0\,
I1 => \cb_int[15]_i_17_n_0\,
O => \cb_int[15]_i_5_n_0\
);
\cb_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
I2 => \cb_int[15]_i_2_n_0\,
O => \cb_int[15]_i_6_n_0\
);
\cb_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_10_n_0\,
I1 => \cb_int[15]_i_11_n_0\,
I2 => \cb_int[15]_i_3_n_0\,
O => \cb_int[15]_i_7_n_0\
);
\cb_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_12_n_0\,
I1 => \cb_int[15]_i_13_n_0\,
I2 => \cb_int[15]_i_4_n_0\,
O => \cb_int[15]_i_8_n_0\
);
\cb_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[15]_i_14_n_0\,
I1 => \cb_int[15]_i_15_n_0\,
I2 => \cb_int[15]_i_5_n_0\,
O => \cb_int[15]_i_9_n_0\
);
\cb_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[19]_i_10_n_0\
);
\cb_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_11_n_0\
);
\cb_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(17),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(25),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_18_n_0\,
I5 => cb_int_reg2(17),
O => \cb_int[19]_i_12_n_0\
);
\cb_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_13_n_0\
);
\cb_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(16),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(24),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_21_n_0\,
I5 => cb_int_reg2(16),
O => \cb_int[19]_i_14_n_0\
);
\cb_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_15_n_0\
);
\cb_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(15),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(23),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_23_n_0\,
I5 => cb_int_reg2(15),
O => \cb_int[19]_i_16_n_0\
);
\cb_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(14),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(22),
I3 => cb_int_reg8,
I4 => \cb_int[19]_i_26_n_0\,
I5 => cb_int_reg2(14),
O => \cb_int[19]_i_17_n_0\
);
\cb_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(0),
O => \cb_int[19]_i_18_n_0\
);
\cb_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(17),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(17)
);
\cb_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
O => \cb_int[19]_i_2_n_0\
);
\cb_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(3),
O => \cb_int[19]_i_21_n_0\
);
\cb_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(16),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(16)
);
\cb_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(2),
O => \cb_int[19]_i_23_n_0\
);
\cb_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(15),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(15)
);
\cb_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_5\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_6\(1),
O => \cb_int[19]_i_26_n_0\
);
\cb_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(14),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_3\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(14)
);
\cb_int[19]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(24),
O => \cb_int[19]_i_28_n_0\
);
\cb_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(23),
O => \cb_int[19]_i_29_n_0\
);
\cb_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
O => \cb_int[19]_i_3_n_0\
);
\cb_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(22),
O => \cb_int[19]_i_30_n_0\
);
\cb_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(21),
O => \cb_int[19]_i_31_n_0\
);
\cb_int[19]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_34_n_0\
);
\cb_int[19]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_35_n_0\
);
\cb_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_36_n_0\
);
\cb_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[19]_i_37_n_0\
);
\cb_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
O => \cb_int[19]_i_4_n_0\
);
\cb_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[19]_i_16_n_0\,
I1 => \cb_int[19]_i_17_n_0\,
O => \cb_int[19]_i_5_n_0\
);
\cb_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
I2 => \cb_int[19]_i_2_n_0\,
O => \cb_int[19]_i_6_n_0\
);
\cb_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_10_n_0\,
I1 => \cb_int[19]_i_11_n_0\,
I2 => \cb_int[19]_i_3_n_0\,
O => \cb_int[19]_i_7_n_0\
);
\cb_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_12_n_0\,
I1 => \cb_int[19]_i_13_n_0\,
I2 => \cb_int[19]_i_4_n_0\,
O => \cb_int[19]_i_8_n_0\
);
\cb_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[19]_i_14_n_0\,
I1 => \cb_int[19]_i_15_n_0\,
I2 => \cb_int[19]_i_5_n_0\,
O => \cb_int[19]_i_9_n_0\
);
\cb_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[23]_i_10_n_0\
);
\cb_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_11_n_0\
);
\cb_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(21),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(29),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_18_n_0\,
I5 => cb_int_reg2(21),
O => \cb_int[23]_i_12_n_0\
);
\cb_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_13_n_0\
);
\cb_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(20),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(28),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_20_n_0\,
I5 => cb_int_reg2(20),
O => \cb_int[23]_i_14_n_0\
);
\cb_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_15_n_0\
);
\cb_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD1D22E222E2DD1D"
)
port map (
I0 => cb_int_reg5(19),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(27),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_22_n_0\,
I5 => cb_int_reg2(19),
O => \cb_int[23]_i_16_n_0\
);
\cb_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(18),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(26),
I3 => cb_int_reg8,
I4 => \cb_int[23]_i_25_n_0\,
I5 => cb_int_reg2(18),
O => \cb_int[23]_i_17_n_0\
);
\cb_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(0),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(0),
O => \cb_int[23]_i_18_n_0\
);
\cb_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(21),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(21)
);
\cb_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
O => \cb_int[23]_i_2_n_0\
);
\cb_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(3),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(3),
O => \cb_int[23]_i_20_n_0\
);
\cb_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(20),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(20)
);
\cb_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(2),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(2),
O => \cb_int[23]_i_22_n_0\
);
\cb_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(19),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(19)
);
\cb_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_7\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_8\(1),
O => \cb_int[23]_i_25_n_0\
);
\cb_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(18),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_2\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(18)
);
\cb_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_29_n_0\
);
\cb_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
O => \cb_int[23]_i_3_n_0\
);
\cb_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_30_n_0\
);
\cb_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_31_n_0\
);
\cb_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[23]_i_32_n_0\
);
\cb_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
O => \cb_int[23]_i_4_n_0\
);
\cb_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[23]_i_16_n_0\,
I1 => \cb_int[23]_i_17_n_0\,
O => \cb_int[23]_i_5_n_0\
);
\cb_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
I2 => \cb_int[23]_i_2_n_0\,
O => \cb_int[23]_i_6_n_0\
);
\cb_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_10_n_0\,
I1 => \cb_int[23]_i_11_n_0\,
I2 => \cb_int[23]_i_3_n_0\,
O => \cb_int[23]_i_7_n_0\
);
\cb_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_12_n_0\,
I1 => \cb_int[23]_i_13_n_0\,
I2 => \cb_int[23]_i_4_n_0\,
O => \cb_int[23]_i_8_n_0\
);
\cb_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int[23]_i_14_n_0\,
I1 => \cb_int[23]_i_15_n_0\,
I2 => \cb_int[23]_i_5_n_0\,
O => \cb_int[23]_i_9_n_0\
);
\cb_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_9\(1),
I1 => \rgb888[8]_1\(1),
I2 => \^co\(0),
I3 => \rgb888[8]_10\(1),
O => \cb_int[27]_i_10_n_0\
);
\cb_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => cb_int_reg3(22),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_1\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
O => cb_int_reg2(22)
);
\cb_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_12_n_0\
);
\cb_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_13_n_0\
);
\cb_int[27]_i_14\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_14_n_0\
);
\cb_int[27]_i_15\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[27]_i_15_n_0\
);
\cb_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cb_int[27]_i_7_n_0\,
I1 => \cb_int[27]_i_8_n_0\,
O => \cb_int[27]_i_2_n_0\
);
\cb_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_3_n_0\
);
\cb_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_4_n_0\
);
\cb_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_5_n_0\
);
\cb_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[27]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_6_n_0\
);
\cb_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1E111E11E1EE1E11"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => \cb_int_reg[31]_i_11_n_1\,
I2 => \rgb888[8]_11\(0),
I3 => \rgb888[8]_1\(1),
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[27]_i_7_n_0\
);
\cb_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD1DDD1D0000"
)
port map (
I0 => cb_int_reg5(22),
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => cb_int_reg7(30),
I3 => cb_int_reg8,
I4 => \cb_int[27]_i_10_n_0\,
I5 => cb_int_reg2(22),
O => \cb_int[27]_i_8_n_0\
);
\cb_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_11\(0),
I1 => \rgb888[8]_1\(1),
O => \cb_int[31]_i_13_n_0\
);
\cb_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(1),
O => \cb_int[31]_i_15_n_0\
);
\cb_int[31]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_1\(0),
O => \cb_int[31]_i_16_n_0\
);
\cb_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4404440444040000"
)
port map (
I0 => \cb_int_reg[31]_i_7_n_1\,
I1 => \rgb888[0]\(3),
I2 => \rgb888[8]_1\(1),
I3 => \rgb888[8]_11\(0),
I4 => \cb_int_reg[31]_i_11_n_1\,
I5 => \cb_int_reg[31]_i_12_n_1\,
O => \cb_int[31]_i_2_n_0\
);
\cb_int[31]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \^di\(0)
);
\cb_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_3_n_0\
);
\cb_int[31]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(30),
O => \cb_int[31]_i_31_n_0\
);
\cb_int[31]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(29),
O => \cb_int[31]_i_32_n_0\
);
\cb_int[31]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_35_n_0\
);
\cb_int[31]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_34_n_2\,
O => \cb_int[31]_i_36_n_0\
);
\cb_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(3),
O => \cb_int[31]_i_38_n_0\
);
\cb_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(2),
O => \cb_int[31]_i_39_n_0\
);
\cb_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_4_n_0\
);
\cb_int[31]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(1),
O => \cb_int[31]_i_40_n_0\
);
\cb_int[31]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_2\(0),
O => \cb_int[31]_i_41_n_0\
);
\cb_int[31]_i_43\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_1\(1)
);
\cb_int[31]_i_44\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \^cr_int_reg[27]_1\(0)
);
\cb_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_5_n_0\
);
\cb_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(1),
I3 => rgb888(2),
I4 => rgb888(4),
I5 => rgb888(6),
O => \^cr_int_reg[27]_0\
);
\cb_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55565556A9555556"
)
port map (
I0 => \cb_int[31]_i_2_n_0\,
I1 => \cb_int_reg[31]_i_12_n_1\,
I2 => \cb_int_reg[31]_i_11_n_1\,
I3 => \cb_int[31]_i_13_n_0\,
I4 => \rgb888[0]\(3),
I5 => \cb_int_reg[31]_i_7_n_1\,
O => \cb_int[31]_i_6_n_0\
);
\cb_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(28),
O => \cb_int[31]_i_67_n_0\
);
\cb_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(27),
O => \cb_int[31]_i_68_n_0\
);
\cb_int[31]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(26),
O => \cb_int[31]_i_69_n_0\
);
\cb_int[31]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \cb_int_reg[31]_i_12_n_1\,
I1 => cb_int_reg8,
I2 => cb_int_reg7(25),
O => \cb_int[31]_i_70_n_0\
);
\cb_int[31]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_71_n_0\
);
\cb_int[31]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(23),
I2 => rgb888(22),
O => \cb_int[31]_i_72_n_0\
);
\cb_int[31]_i_74\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FE0"
)
port map (
I0 => rgb888(22),
I1 => rgb888(23),
I2 => \cb_int_reg[31]_i_73_n_4\,
I3 => \cb_int_reg[31]_i_34_n_7\,
O => \cb_int[31]_i_74_n_0\
);
\cb_int[31]_i_75\: unisim.vcomponents.LUT4
generic map(
INIT => X"3336"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_5\,
I1 => \cb_int_reg[31]_i_73_n_4\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_75_n_0\
);
\cb_int[31]_i_76\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_6\,
I1 => rgb888(22),
I2 => rgb888(23),
I3 => \cb_int_reg[31]_i_73_n_5\,
O => \cb_int[31]_i_76_n_0\
);
\cb_int[31]_i_77\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => \cb_int_reg[31]_i_73_n_6\,
I2 => rgb888(22),
I3 => rgb888(23),
O => \cb_int[31]_i_77_n_0\
);
\cb_int[31]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cb_int[31]_i_78_n_0\
);
\cb_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(3),
O => \cb_int[31]_i_79_n_0\
);
\cb_int[31]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(2),
O => \cb_int[31]_i_80_n_0\
);
\cb_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(1),
O => \cb_int[31]_i_81_n_0\
);
\cb_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[0]\(3),
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_3\(0),
O => \cb_int[31]_i_82_n_0\
);
\cb_int[31]_i_86\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rgb888(11),
I1 => rgb888(10),
I2 => rgb888(12),
I3 => rgb888(13),
O => \^cr_int_reg[31]_1\
);
\cb_int[31]_i_87\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => rgb888(14),
O => \^cr_int_reg[31]_0\
);
\cb_int[31]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \cb_int[31]_i_95_n_0\
);
\cb_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \cb_int[31]_i_96_n_0\
);
\cb_int[31]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \cb_int[31]_i_97_n_0\
);
\cb_int[31]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \cb_int[31]_i_98_n_0\
);
\cb_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(1),
I3 => \^co\(0),
I4 => \rgb888[8]\(3),
O => \cb_int[3]_i_10_n_0\
);
\cb_int[3]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => rgb888(2),
O => \cb_int[3]_i_100_n_0\
);
\cb_int[3]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cb_int[3]_i_101_n_0\
);
\cb_int[3]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \cb_int[3]_i_102_n_0\
);
\cb_int[3]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
O => \cb_int[3]_i_103_n_0\
);
\cb_int[3]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(10),
O => \cb_int[3]_i_104_n_0\
);
\cb_int[3]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cb_int[3]_i_105_n_0\
);
\cb_int[3]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_106_n_0\
);
\cb_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(2),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_6\,
O => cb_int_reg2(2)
);
\cb_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(9),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(1),
O => \cb_int[3]_i_12_n_0\
);
\cb_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(0),
I3 => \^co\(0),
I4 => \rgb888[8]\(2),
O => \cb_int[3]_i_13_n_0\
);
\cb_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(1),
I1 => \rgb888[0]\(3),
I2 => \cb_int_reg[3]_i_20_n_4\,
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_7\,
O => cb_int_reg2(1)
);
\cb_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \^co\(0),
I2 => \rgb888[13]\(0),
O => \cb_int[3]_i_17_n_0\
);
\cb_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_33_n_4\,
O => \cb_int[3]_i_18_n_0\
);
\cb_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
O => \cb_int[3]_i_2_n_0\
);
\cb_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_6\,
O => \cb_int[3]_i_22_n_0\
);
\cb_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_33_n_7\,
O => \cb_int[3]_i_23_n_0\
);
\cb_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_4\,
O => \cb_int[3]_i_24_n_0\
);
\cb_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_5\,
O => \cb_int[3]_i_25_n_0\
);
\cb_int[3]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
O => \cb_int[3]_i_27_n_0\
);
\cb_int[3]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[31]_i_73_n_7\,
I1 => rgb888(22),
O => \cb_int[3]_i_28_n_0\
);
\cb_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => \cb_int_reg[3]_i_57_n_4\,
O => \cb_int[3]_i_29_n_0\
);
\cb_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
O => \cb_int[3]_i_3_n_0\
);
\cb_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => \cb_int_reg[3]_i_57_n_5\,
O => \cb_int[3]_i_30_n_0\
);
\cb_int[3]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => \cb_int_reg[3]_i_57_n_6\,
O => \cb_int[3]_i_31_n_0\
);
\cb_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DFF001D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_4_n_0\
);
\cb_int[3]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
I2 => \rgb888[0]_8\(1),
O => \cb_int[3]_i_45_n_0\
);
\cb_int[3]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \rgb888[0]_8\(0),
I1 => rgb888(1),
O => \cb_int[3]_i_46_n_0\
);
\cb_int[3]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_4\,
I1 => rgb888(0),
O => \cb_int[3]_i_47_n_0\
);
\cb_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_5\,
O => \cb_int[3]_i_48_n_0\
);
\cb_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_6\,
O => \cb_int[3]_i_49_n_0\
);
\cb_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
I3 => \cb_int[3]_i_2_n_0\,
O => \cb_int[3]_i_5_n_0\
);
\cb_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_6\,
O => \cb_int[3]_i_50_n_0\
);
\cb_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_16_n_7\,
O => \cb_int[3]_i_51_n_0\
);
\cb_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_4\,
O => \cb_int[3]_i_52_n_0\
);
\cb_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_26_n_5\,
O => \cb_int[3]_i_53_n_0\
);
\cb_int[3]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => \cb_int_reg[3]_i_57_n_7\,
O => \cb_int[3]_i_54_n_0\
);
\cb_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \cb_int[3]_i_55_n_0\
);
\cb_int[3]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cb_int[3]_i_56_n_0\
);
\cb_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_9_n_0\,
I1 => \cb_int[3]_i_10_n_0\,
I2 => cb_int_reg2(2),
I3 => \cb_int[3]_i_3_n_0\,
O => \cb_int[3]_i_6_n_0\
);
\cb_int[3]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[3]_i_64_n_0\
);
\cb_int[3]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_6\,
O => \cb_int[3]_i_65_n_0\
);
\cb_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_7\,
O => \cb_int[3]_i_66_n_0\
);
\cb_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_6\,
O => \cb_int[3]_i_67_n_0\
);
\cb_int[3]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
I2 => \rgb888[8]_31\(2),
O => \cb_int[3]_i_69_n_0\
);
\cb_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[3]_i_12_n_0\,
I1 => \cb_int[3]_i_13_n_0\,
I2 => cb_int_reg2(1),
I3 => \cb_int[3]_i_4_n_0\,
O => \cb_int[3]_i_7_n_0\
);
\cb_int[3]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(1),
I1 => rgb888(9),
O => \cb_int[3]_i_70_n_0\
);
\cb_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_31\(0),
I1 => rgb888(8),
O => \cb_int[3]_i_71_n_0\
);
\cb_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_4\,
O => \cb_int[3]_i_72_n_0\
);
\cb_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cb_int[3]_i_76_n_0\
);
\cb_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cb_int[3]_i_77_n_0\
);
\cb_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cb_int[3]_i_78_n_0\
);
\cb_int[3]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cb_int[3]_i_79_n_0\
);
\cb_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cb_int_reg7(8),
I1 => cb_int_reg8,
I2 => \cb_int_reg[3]_i_16_n_4\,
I3 => \cb_int[3]_i_17_n_0\,
I4 => \cb_int[3]_i_18_n_0\,
O => \cb_int[3]_i_8_n_0\
);
\cb_int[3]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \cb_int[3]_i_80_n_0\
);
\cb_int[3]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \cb_int[3]_i_81_n_0\
);
\cb_int[3]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \cb_int[3]_i_82_n_0\
);
\cb_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \cb_int[3]_i_83_n_0\
);
\cb_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_7\,
O => \cb_int[3]_i_89_n_0\
);
\cb_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(10),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(2),
O => \cb_int[3]_i_9_n_0\
);
\cb_int[3]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_44_n_7\,
O => \cb_int[3]_i_90_n_0\
);
\cb_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_4\,
O => \cb_int[3]_i_91_n_0\
);
\cb_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_5\,
O => \cb_int[3]_i_92_n_0\
);
\cb_int[3]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_75_n_6\,
O => \cb_int[3]_i_93_n_0\
);
\cb_int[3]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cb_int[3]_i_99_n_0\
);
\cb_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(13),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_7\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(5),
O => \cb_int[7]_i_10_n_0\
);
\cb_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(0),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(0),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_11_n_0\
);
\cb_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(5),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(3),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_7\,
O => cb_int_reg2(5)
);
\cb_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(12),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_4\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(4),
O => \cb_int[7]_i_13_n_0\
);
\cb_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(3),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(3),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_14_n_0\
);
\cb_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(4),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(2),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_4\,
O => cb_int_reg2(4)
);
\cb_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(11),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_33_n_5\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(3),
O => \cb_int[7]_i_16_n_0\
);
\cb_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_2\(2),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[13]_0\(2),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_17_n_0\
);
\cb_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(3),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]_0\(1),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[7]_i_29_n_5\,
O => cb_int_reg2(3)
);
\cb_int[7]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"B0BF"
)
port map (
I0 => cb_int_reg8,
I1 => cb_int_reg7(15),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg5(7),
O => \cb_int[7]_i_19_n_0\
);
\cb_int[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5959A959"
)
port map (
I0 => \cb_int[11]_i_19_n_0\,
I1 => cb_int_reg5(7),
I2 => \cb_int_reg[31]_i_12_n_1\,
I3 => cb_int_reg7(15),
I4 => cb_int_reg8,
O => \cb_int[7]_i_2_n_0\
);
\cb_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cb_int_reg3(6),
I1 => \rgb888[0]\(3),
I2 => \rgb888[0]\(0),
I3 => \cb_int_reg[11]_i_25_n_0\,
I4 => \cb_int_reg[11]_i_24_n_6\,
O => cb_int_reg2(6)
);
\cb_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_3\(1),
I1 => \rgb888[8]_1\(1),
I2 => \rgb888[12]\(1),
I3 => \^co\(0),
I4 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_21_n_0\
);
\cb_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"1D001DFF"
)
port map (
I0 => cb_int_reg7(14),
I1 => cb_int_reg8,
I2 => \cb_int_reg[31]_i_12_n_6\,
I3 => \cb_int_reg[31]_i_12_n_1\,
I4 => cb_int_reg5(6),
O => \cb_int[7]_i_22_n_0\
);
\cb_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
O => \cb_int[7]_i_3_n_0\
);
\cb_int[7]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_39_n_0\
);
\cb_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
O => \cb_int[7]_i_4_n_0\
);
\cb_int[7]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_40_n_0\
);
\cb_int[7]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_41_n_0\
);
\cb_int[7]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_42_n_0\
);
\cb_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int[7]_i_16_n_0\,
I1 => \cb_int[7]_i_17_n_0\,
I2 => cb_int_reg2(3),
O => \cb_int[7]_i_5_n_0\
);
\cb_int[7]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_33_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_5\,
O => \cb_int[7]_i_52_n_0\
);
\cb_int[7]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_4\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_53_n_0\
);
\cb_int[7]_i_54\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_5\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_54_n_0\
);
\cb_int[7]_i_55\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_6\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_55_n_0\
);
\cb_int[7]_i_56\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_29_n_7\,
I1 => \cb_int_reg[11]_i_25_n_0\,
I2 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_56_n_0\
);
\cb_int[7]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(2),
O => \cb_int[7]_i_57_n_0\
);
\cb_int[7]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(1),
O => \cb_int[7]_i_58_n_0\
);
\cb_int[7]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[0]_0\(0),
O => \cb_int[7]_i_59_n_0\
);
\cb_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \cb_int[7]_i_19_n_0\,
I1 => \cb_int[11]_i_19_n_0\,
I2 => cb_int_reg2(6),
I3 => \cb_int[7]_i_21_n_0\,
I4 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_6_n_0\
);
\cb_int[7]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_20_n_4\,
O => \cb_int[7]_i_60_n_0\
);
\cb_int[7]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_62_n_0\
);
\cb_int[7]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_63_n_0\
);
\cb_int[7]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_64_n_0\
);
\cb_int[7]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(1),
O => \cb_int[7]_i_65_n_0\
);
\cb_int[7]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(3),
I1 => \rgb888[8]_1\(0),
O => \cb_int[7]_i_67_n_0\
);
\cb_int[7]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_0\(1),
I1 => \rgb888[8]_0\(2),
O => \cb_int[7]_i_68_n_0\
);
\cb_int[7]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(3),
I1 => \rgb888[8]_0\(0),
O => \cb_int[7]_i_69_n_0\
);
\cb_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_3_n_0\,
I1 => cb_int_reg2(6),
I2 => \cb_int[7]_i_21_n_0\,
I3 => \cb_int[7]_i_22_n_0\,
O => \cb_int[7]_i_7_n_0\
);
\cb_int[7]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]\(1),
I1 => \rgb888[8]\(2),
O => \cb_int[7]_i_70_n_0\
);
\cb_int[7]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_1\(0),
I1 => \rgb888[8]_0\(3),
O => \cb_int[7]_i_71_n_0\
);
\cb_int[7]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(2),
I1 => \rgb888[8]_0\(1),
O => \cb_int[7]_i_72_n_0\
);
\cb_int[7]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_0\(0),
I1 => \rgb888[8]\(3),
O => \cb_int[7]_i_73_n_0\
);
\cb_int[7]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(2),
I1 => \rgb888[8]\(1),
O => \cb_int[7]_i_74_n_0\
);
\cb_int[7]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(3),
I1 => \rgb888[8]\(0),
O => \cb_int[7]_i_75_n_0\
);
\cb_int[7]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cb_int_reg[3]_0\(1),
I1 => \^cb_int_reg[3]_0\(2),
O => \cb_int[7]_i_76_n_0\
);
\cb_int[7]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^o\(1),
I1 => \^cb_int_reg[3]_0\(0),
O => \cb_int[7]_i_77_n_0\
);
\cb_int[7]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(8),
I1 => \^o\(0),
O => \cb_int[7]_i_78_n_0\
);
\cb_int[7]_i_79\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]\(0),
I1 => \^cb_int_reg[3]_0\(3),
O => \cb_int[7]_i_79_n_0\
);
\cb_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_10_n_0\,
I1 => \cb_int[7]_i_11_n_0\,
I2 => cb_int_reg2(5),
I3 => \cb_int[7]_i_4_n_0\,
O => \cb_int[7]_i_8_n_0\
);
\cb_int[7]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(2),
I1 => \^cb_int_reg[3]_0\(1),
O => \cb_int[7]_i_80_n_0\
);
\cb_int[7]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cb_int_reg[3]_0\(0),
I1 => \^o\(1),
O => \cb_int[7]_i_81_n_0\
);
\cb_int[7]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^o\(0),
I1 => rgb888(8),
O => \cb_int[7]_i_82_n_0\
);
\cb_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cb_int[7]_i_13_n_0\,
I1 => \cb_int[7]_i_14_n_0\,
I2 => cb_int_reg2(4),
I3 => \cb_int[7]_i_5_n_0\,
O => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_7\,
Q => \cb_int_reg_n_0_[0]\,
R => '0'
);
\cb_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_5\,
Q => \cb_int_reg__0\(10),
R => '0'
);
\cb_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_4\,
Q => \cb_int_reg__0\(11),
R => '0'
);
\cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_1_n_0\,
CO(3) => \cb_int_reg[11]_i_1_n_0\,
CO(2) => \cb_int_reg[11]_i_1_n_1\,
CO(1) => \cb_int_reg[11]_i_1_n_2\,
CO(0) => \cb_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_2_n_0\,
DI(2) => \cb_int[11]_i_3_n_0\,
DI(1) => \cb_int[11]_i_4_n_0\,
DI(0) => \cb_int[11]_i_5_n_0\,
O(3) => \cb_int_reg[11]_i_1_n_4\,
O(2) => \cb_int_reg[11]_i_1_n_5\,
O(1) => \cb_int_reg[11]_i_1_n_6\,
O(0) => \cb_int_reg[11]_i_1_n_7\,
S(3) => \cb_int[11]_i_6_n_0\,
S(2) => \cb_int[11]_i_7_n_0\,
S(1) => \cb_int[11]_i_8_n_0\,
S(0) => \cb_int[11]_i_9_n_0\
);
\cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_16_n_0\,
CO(2) => \cb_int_reg[11]_i_16_n_1\,
CO(1) => \cb_int_reg[11]_i_16_n_2\,
CO(0) => \cb_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(8 downto 5),
S(3) => \cb_int[11]_i_29_n_0\,
S(2) => \cb_int[11]_i_30_n_0\,
S(1) => \cb_int[11]_i_31_n_0\,
S(0) => \cb_int[11]_i_32_n_0\
);
\cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_33_n_0\,
CO(3) => \cb_int_reg[11]_i_17_n_0\,
CO(2) => \cb_int_reg[11]_i_17_n_1\,
CO(1) => \cb_int_reg[11]_i_17_n_2\,
CO(0) => \cb_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(18 downto 15),
S(3) => \cb_int[11]_i_34_n_0\,
S(2) => \cb_int[11]_i_35_n_0\,
S(1) => \cb_int[11]_i_36_n_0\,
S(0) => \cb_int[11]_i_37_n_0\
);
\cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_38_n_0\,
CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3),
CO(2) => cb_int_reg8,
CO(1) => \cb_int_reg[11]_i_18_n_2\,
CO(0) => \cb_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int[11]_i_39_n_0\,
DI(0) => \cb_int[11]_i_40_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \cb_int[11]_i_41_n_0\,
S(1) => \cb_int[11]_i_42_n_0\,
S(0) => \cb_int[11]_i_43_n_0\
);
\cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_29_n_0\,
CO(3) => \cb_int_reg[15]_0\(0),
CO(2) => \cb_int_reg[11]_i_24_n_1\,
CO(1) => \cb_int_reg[11]_i_24_n_2\,
CO(0) => \cb_int_reg[11]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[11]_i_24_n_4\,
O(2) => \cb_int_reg[11]_i_24_n_5\,
O(1) => \cb_int_reg[11]_i_24_n_6\,
O(0) => \cb_int_reg[11]_i_24_n_7\,
S(3) => \cb_int[11]_i_44_n_0\,
S(2) => \cb_int[11]_i_45_n_0\,
S(1) => \cb_int[11]_i_46_n_0\,
S(0) => \cb_int[11]_i_47_n_0\
);
\cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_48_n_0\,
CO(3) => \cb_int_reg[11]_i_25_n_0\,
CO(2) => \cb_int_reg[11]_i_25_n_1\,
CO(1) => \cb_int_reg[11]_i_25_n_2\,
CO(0) => \cb_int_reg[11]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \rgb888[0]\(3),
O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_49_n_0\,
S(2) => \cb_int[11]_i_50_n_0\,
S(1) => \cb_int[11]_i_51_n_0\,
S(0) => \cb_int[11]_i_52_n_0\
);
\cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_28_n_0\,
CO(3) => \cb_int_reg[11]_i_26_n_0\,
CO(2) => \cb_int_reg[11]_i_26_n_1\,
CO(1) => \cb_int_reg[11]_i_26_n_2\,
CO(0) => \cb_int_reg[11]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(8 downto 5),
S(3) => \cb_int[11]_i_53_n_0\,
S(2) => \cb_int[11]_i_54_n_0\,
S(1) => \cb_int[11]_i_55_n_0\,
S(0) => \cb_int[11]_i_56_n_0\
);
\cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_28_n_0\,
CO(2) => \cb_int_reg[11]_i_28_n_1\,
CO(1) => \cb_int_reg[11]_i_28_n_2\,
CO(0) => \cb_int_reg[11]_i_28_n_3\,
CYINIT => \cb_int[11]_i_57_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(4 downto 1),
S(3) => \cb_int[11]_i_58_n_0\,
S(2) => \cb_int[11]_i_59_n_0\,
S(1) => \cb_int[11]_i_60_n_0\,
S(0) => \cb_int[11]_i_61_n_0\
);
\cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_15_n_0\,
CO(3) => \cb_int_reg[11]_i_33_n_0\,
CO(2) => \cb_int_reg[11]_i_33_n_1\,
CO(1) => \cb_int_reg[11]_i_33_n_2\,
CO(0) => \cb_int_reg[11]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(14 downto 11),
S(3) => \cb_int[11]_i_62_n_0\,
S(2) => \cb_int[11]_i_63_n_0\,
S(1) => \cb_int[11]_i_64_n_0\,
S(0) => \cb_int[11]_i_65_n_0\
);
\cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_66_n_0\,
CO(3) => \cb_int_reg[11]_i_38_n_0\,
CO(2) => \cb_int_reg[11]_i_38_n_1\,
CO(1) => \cb_int_reg[11]_i_38_n_2\,
CO(0) => \cb_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_67_n_0\,
DI(2) => \cb_int[11]_i_68_n_0\,
DI(1) => \cb_int[11]_i_69_n_0\,
DI(0) => \cb_int[11]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_71_n_0\,
S(2) => \cb_int[11]_i_72_n_0\,
S(1) => \cb_int[11]_i_73_n_0\,
S(0) => \cb_int[11]_i_74_n_0\
);
\cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_75_n_0\,
CO(3) => \cb_int_reg[11]_i_48_n_0\,
CO(2) => \cb_int_reg[11]_i_48_n_1\,
CO(1) => \cb_int_reg[11]_i_48_n_2\,
CO(0) => \cb_int_reg[11]_i_48_n_3\,
CYINIT => '0',
DI(3) => \rgb888[0]\(3),
DI(2) => \rgb888[0]\(3),
DI(1) => \rgb888[0]\(3),
DI(0) => \cb_int[11]_i_76_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_77_n_0\,
S(2) => \cb_int[11]_i_78_n_0\,
S(1) => \cb_int[11]_i_79_n_0\,
S(0) => \cb_int[11]_i_80_n_0\
);
\cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_81_n_0\,
CO(3) => \cb_int_reg[11]_i_66_n_0\,
CO(2) => \cb_int_reg[11]_i_66_n_1\,
CO(1) => \cb_int_reg[11]_i_66_n_2\,
CO(0) => \cb_int_reg[11]_i_66_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_82_n_0\,
DI(2) => \cb_int[11]_i_83_n_0\,
DI(1) => \cb_int[11]_i_84_n_0\,
DI(0) => \cb_int[11]_i_85_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_86_n_0\,
S(2) => \cb_int[11]_i_87_n_0\,
S(1) => \cb_int[11]_i_88_n_0\,
S(0) => \cb_int[11]_i_89_n_0\
);
\cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_90_n_0\,
CO(3) => \cb_int_reg[11]_i_75_n_0\,
CO(2) => \cb_int_reg[11]_i_75_n_1\,
CO(1) => \cb_int_reg[11]_i_75_n_2\,
CO(0) => \cb_int_reg[11]_i_75_n_3\,
CYINIT => '0',
DI(3) => \cb_int[11]_i_91_n_0\,
DI(2) => \cb_int[11]_i_92_n_0\,
DI(1) => \cb_int[11]_i_93_n_0\,
DI(0) => \cb_int[11]_i_94_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_95_n_0\,
S(2) => \cb_int[11]_i_96_n_0\,
S(1) => \cb_int[11]_i_97_n_0\,
S(0) => \cb_int[11]_i_98_n_0\
);
\cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_81_n_0\,
CO(2) => \cb_int_reg[11]_i_81_n_1\,
CO(1) => \cb_int_reg[11]_i_81_n_2\,
CO(0) => \cb_int_reg[11]_i_81_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_99_n_0\,
DI(2) => \cb_int[11]_i_100_n_0\,
DI(1) => \cb_int[11]_i_101_n_0\,
DI(0) => \cb_int[11]_i_102_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_103_n_0\,
S(2) => \cb_int[11]_i_104_n_0\,
S(1) => \cb_int[11]_i_105_n_0\,
S(0) => \cb_int[11]_i_106_n_0\
);
\cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[11]_i_90_n_0\,
CO(2) => \cb_int_reg[11]_i_90_n_1\,
CO(1) => \cb_int_reg[11]_i_90_n_2\,
CO(0) => \cb_int_reg[11]_i_90_n_3\,
CYINIT => '1',
DI(3) => \cb_int[11]_i_107_n_0\,
DI(2) => \cb_int[11]_i_108_n_0\,
DI(1) => \cb_int[11]_i_109_n_0\,
DI(0) => \cb_int[11]_i_110_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[11]_i_111_n_0\,
S(2) => \cb_int[11]_i_112_n_0\,
S(1) => \cb_int[11]_i_113_n_0\,
S(0) => \cb_int[11]_i_114_n_0\
);
\cb_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_7\,
Q => \cb_int_reg__0\(12),
R => '0'
);
\cb_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_6\,
Q => \cb_int_reg__0\(13),
R => '0'
);
\cb_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_5\,
Q => \cb_int_reg__0\(14),
R => '0'
);
\cb_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[15]_i_1_n_4\,
Q => \cb_int_reg__0\(15),
R => '0'
);
\cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_1_n_0\,
CO(3) => \cb_int_reg[15]_i_1_n_0\,
CO(2) => \cb_int_reg[15]_i_1_n_1\,
CO(1) => \cb_int_reg[15]_i_1_n_2\,
CO(0) => \cb_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[15]_i_2_n_0\,
DI(2) => \cb_int[15]_i_3_n_0\,
DI(1) => \cb_int[15]_i_4_n_0\,
DI(0) => \cb_int[15]_i_5_n_0\,
O(3) => \cb_int_reg[15]_i_1_n_4\,
O(2) => \cb_int_reg[15]_i_1_n_5\,
O(1) => \cb_int_reg[15]_i_1_n_6\,
O(0) => \cb_int_reg[15]_i_1_n_7\,
S(3) => \cb_int[15]_i_6_n_0\,
S(2) => \cb_int[15]_i_7_n_0\,
S(1) => \cb_int[15]_i_8_n_0\,
S(0) => \cb_int[15]_i_9_n_0\
);
\cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_16_n_0\,
CO(3) => \cb_int_reg[15]_i_20_n_0\,
CO(2) => \cb_int_reg[15]_i_20_n_1\,
CO(1) => \cb_int_reg[15]_i_20_n_2\,
CO(0) => \cb_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(12 downto 9),
S(3) => \cb_int[15]_i_27_n_0\,
S(2) => \cb_int[15]_i_28_n_0\,
S(1) => \cb_int[15]_i_29_n_0\,
S(0) => \cb_int[15]_i_30_n_0\
);
\cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_26_n_0\,
CO(3) => \cb_int_reg[15]_i_33_n_0\,
CO(2) => \cb_int_reg[15]_i_33_n_1\,
CO(1) => \cb_int_reg[15]_i_33_n_2\,
CO(0) => \cb_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(12 downto 9),
S(3) => \cb_int[15]_i_43_n_0\,
S(2) => \cb_int[15]_i_44_n_0\,
S(1) => \cb_int[15]_i_45_n_0\,
S(0) => \cb_int[15]_i_46_n_0\
);
\cb_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_7\,
Q => \cb_int_reg__0\(16),
R => '0'
);
\cb_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_6\,
Q => \cb_int_reg__0\(17),
R => '0'
);
\cb_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_5\,
Q => \cb_int_reg__0\(18),
R => '0'
);
\cb_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[19]_i_1_n_4\,
Q => \cb_int_reg__0\(19),
R => '0'
);
\cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_1_n_0\,
CO(3) => \cb_int_reg[19]_i_1_n_0\,
CO(2) => \cb_int_reg[19]_i_1_n_1\,
CO(1) => \cb_int_reg[19]_i_1_n_2\,
CO(0) => \cb_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[19]_i_2_n_0\,
DI(2) => \cb_int[19]_i_3_n_0\,
DI(1) => \cb_int[19]_i_4_n_0\,
DI(0) => \cb_int[19]_i_5_n_0\,
O(3) => \cb_int_reg[19]_i_1_n_4\,
O(2) => \cb_int_reg[19]_i_1_n_5\,
O(1) => \cb_int_reg[19]_i_1_n_6\,
O(0) => \cb_int_reg[19]_i_1_n_7\,
S(3) => \cb_int[19]_i_6_n_0\,
S(2) => \cb_int[19]_i_7_n_0\,
S(1) => \cb_int[19]_i_8_n_0\,
S(0) => \cb_int[19]_i_9_n_0\
);
\cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_20_n_0\,
CO(3) => \cb_int_reg[19]_i_20_n_0\,
CO(2) => \cb_int_reg[19]_i_20_n_1\,
CO(1) => \cb_int_reg[19]_i_20_n_2\,
CO(0) => \cb_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(16 downto 13),
S(3) => \cb_int[19]_i_28_n_0\,
S(2) => \cb_int[19]_i_29_n_0\,
S(1) => \cb_int[19]_i_30_n_0\,
S(0) => \cb_int[19]_i_31_n_0\
);
\cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[11]_i_17_n_0\,
CO(3) => \cb_int_reg[19]_i_25_n_0\,
CO(2) => \cb_int_reg[19]_i_25_n_1\,
CO(1) => \cb_int_reg[19]_i_25_n_2\,
CO(0) => \cb_int_reg[19]_i_25_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(22 downto 19),
S(3) => \cb_int[19]_i_34_n_0\,
S(2) => \cb_int[19]_i_35_n_0\,
S(1) => \cb_int[19]_i_36_n_0\,
S(0) => \cb_int[19]_i_37_n_0\
);
\cb_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_6\,
Q => \cb_int_reg_n_0_[1]\,
R => '0'
);
\cb_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_7\,
Q => \cb_int_reg__0\(20),
R => '0'
);
\cb_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_6\,
Q => \cb_int_reg__0\(21),
R => '0'
);
\cb_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_5\,
Q => \cb_int_reg__0\(22),
R => '0'
);
\cb_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[23]_i_1_n_4\,
Q => \cb_int_reg__0\(23),
R => '0'
);
\cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_1_n_0\,
CO(3) => \cb_int_reg[23]_i_1_n_0\,
CO(2) => \cb_int_reg[23]_i_1_n_1\,
CO(1) => \cb_int_reg[23]_i_1_n_2\,
CO(0) => \cb_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[23]_i_2_n_0\,
DI(2) => \cb_int[23]_i_3_n_0\,
DI(1) => \cb_int[23]_i_4_n_0\,
DI(0) => \cb_int[23]_i_5_n_0\,
O(3) => \cb_int_reg[23]_i_1_n_4\,
O(2) => \cb_int_reg[23]_i_1_n_5\,
O(1) => \cb_int_reg[23]_i_1_n_6\,
O(0) => \cb_int_reg[23]_i_1_n_7\,
S(3) => \cb_int[23]_i_6_n_0\,
S(2) => \cb_int[23]_i_7_n_0\,
S(1) => \cb_int[23]_i_8_n_0\,
S(0) => \cb_int[23]_i_9_n_0\
);
\cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_25_n_0\,
CO(3) => \cb_int_reg[23]_i_24_n_0\,
CO(2) => \cb_int_reg[23]_i_24_n_1\,
CO(1) => \cb_int_reg[23]_i_24_n_2\,
CO(0) => \cb_int_reg[23]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(26 downto 23),
S(3) => \cb_int[23]_i_29_n_0\,
S(2) => \cb_int[23]_i_30_n_0\,
S(1) => \cb_int[23]_i_31_n_0\,
S(0) => \cb_int[23]_i_32_n_0\
);
\cb_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_7\,
Q => \cb_int_reg__0\(24),
R => '0'
);
\cb_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_6\,
Q => \cb_int_reg__0\(25),
R => '0'
);
\cb_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_5\,
Q => \cb_int_reg__0\(26),
R => '0'
);
\cb_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[27]_i_1_n_4\,
Q => \cb_int_reg__0\(27),
R => '0'
);
\cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_1_n_0\,
CO(3) => \cb_int_reg[27]_i_1_n_0\,
CO(2) => \cb_int_reg[27]_i_1_n_1\,
CO(1) => \cb_int_reg[27]_i_1_n_2\,
CO(0) => \cb_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_2_n_0\,
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[27]_i_2_n_0\,
O(3) => \cb_int_reg[27]_i_1_n_4\,
O(2) => \cb_int_reg[27]_i_1_n_5\,
O(1) => \cb_int_reg[27]_i_1_n_6\,
O(0) => \cb_int_reg[27]_i_1_n_7\,
S(3) => \cb_int[27]_i_3_n_0\,
S(2) => \cb_int[27]_i_4_n_0\,
S(1) => \cb_int[27]_i_5_n_0\,
S(0) => \cb_int[27]_i_6_n_0\
);
\cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_24_n_0\,
CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[27]_i_9_n_1\,
CO(1) => \cb_int_reg[27]_i_9_n_2\,
CO(0) => \cb_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg7(30 downto 27),
S(3) => \cb_int[27]_i_12_n_0\,
S(2) => \cb_int[27]_i_13_n_0\,
S(1) => \cb_int[27]_i_14_n_0\,
S(0) => \cb_int[27]_i_15_n_0\
);
\cb_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_7\,
Q => \cb_int_reg__0\(28),
R => '0'
);
\cb_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_6\,
Q => \cb_int_reg__0\(29),
R => '0'
);
\cb_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_5\,
Q => \cb_int_reg_n_0_[2]\,
R => '0'
);
\cb_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_5\,
Q => \cb_int_reg__0\(30),
R => '0'
);
\cb_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[31]_i_1_n_4\,
Q => \cb_int_reg__0\(31),
R => '0'
);
\cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_1_n_1\,
CO(1) => \cb_int_reg[31]_i_1_n_2\,
CO(0) => \cb_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cb_int[31]_i_2_n_0\,
DI(1) => \cb_int[31]_i_2_n_0\,
DI(0) => \cb_int[31]_i_2_n_0\,
O(3) => \cb_int_reg[31]_i_1_n_4\,
O(2) => \cb_int_reg[31]_i_1_n_5\,
O(1) => \cb_int_reg[31]_i_1_n_6\,
O(0) => \cb_int_reg[31]_i_1_n_7\,
S(3) => \cb_int[31]_i_3_n_0\,
S(2) => \cb_int[31]_i_4_n_0\,
S(1) => \cb_int[31]_i_5_n_0\,
S(0) => \cb_int[31]_i_6_n_0\
);
\cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_11_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg5(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_31_n_0\,
S(0) => \cb_int[31]_i_32_n_0\
);
\cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_33_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cb_int_reg[31]_i_34_n_2\,
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_12_n_6\,
O(0) => \cb_int_reg[31]_i_12_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_35_n_0\,
S(0) => \cb_int[31]_i_36_n_0\
);
\cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_37_n_0\,
CO(3) => \cb_int_reg[31]_i_14_n_0\,
CO(2) => \cb_int_reg[31]_i_14_n_1\,
CO(1) => \cb_int_reg[31]_i_14_n_2\,
CO(0) => \cb_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(20 downto 17),
S(3) => \cb_int[31]_i_38_n_0\,
S(2) => \cb_int[31]_i_39_n_0\,
S(1) => \cb_int[31]_i_40_n_0\,
S(0) => \cb_int[31]_i_41_n_0\
);
\cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_20_n_0\,
CO(3) => \cb_int_reg[31]_i_30_n_0\,
CO(2) => \cb_int_reg[31]_i_30_n_1\,
CO(1) => \cb_int_reg[31]_i_30_n_2\,
CO(0) => \cb_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg5(20 downto 17),
S(3) => \cb_int[31]_i_67_n_0\,
S(2) => \cb_int[31]_i_68_n_0\,
S(1) => \cb_int[31]_i_69_n_0\,
S(0) => \cb_int[31]_i_70_n_0\
);
\cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_16_n_0\,
CO(3) => \cb_int_reg[31]_i_33_n_0\,
CO(2) => \cb_int_reg[31]_i_33_n_1\,
CO(1) => \cb_int_reg[31]_i_33_n_2\,
CO(0) => \cb_int_reg[31]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cb_int_reg[31]_i_34_n_7\,
DI(2) => \cb_int[31]_i_71_n_0\,
DI(1) => \cb_int[31]_i_72_n_0\,
DI(0) => \cb_int_reg[31]_i_73_n_7\,
O(3) => \cb_int_reg[31]_i_33_n_4\,
O(2) => \cb_int_reg[31]_i_33_n_5\,
O(1) => \cb_int_reg[31]_i_33_n_6\,
O(0) => \cb_int_reg[31]_i_33_n_7\,
S(3) => \cb_int[31]_i_74_n_0\,
S(2) => \cb_int[31]_i_75_n_0\,
S(1) => \cb_int[31]_i_76_n_0\,
S(0) => \cb_int[31]_i_77_n_0\
);
\cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_73_n_0\,
CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cb_int_reg[31]_i_34_n_2\,
CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1),
O(0) => \cb_int_reg[31]_i_34_n_7\,
S(3 downto 1) => B"001",
S(0) => \cb_int[31]_i_78_n_0\
);
\cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_33_n_0\,
CO(3) => \cb_int_reg[31]_i_37_n_0\,
CO(2) => \cb_int_reg[31]_i_37_n_1\,
CO(1) => \cb_int_reg[31]_i_37_n_2\,
CO(0) => \cb_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(16 downto 13),
S(3) => \cb_int[31]_i_79_n_0\,
S(2) => \cb_int[31]_i_80_n_0\,
S(1) => \cb_int[31]_i_81_n_0\,
S(0) => \cb_int[31]_i_82_n_0\
);
\cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cb_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_15_n_0\,
S(0) => \cb_int[31]_i_16_n_0\
);
\cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_57_n_0\,
CO(3) => \cb_int_reg[31]_i_73_n_0\,
CO(2) => \cb_int_reg[31]_i_73_n_1\,
CO(1) => \cb_int_reg[31]_i_73_n_2\,
CO(0) => \cb_int_reg[31]_i_73_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \cb_int_reg[31]_i_73_n_4\,
O(2) => \cb_int_reg[31]_i_73_n_5\,
O(1) => \cb_int_reg[31]_i_73_n_6\,
O(0) => \cb_int_reg[31]_i_73_n_7\,
S(3) => \cb_int[31]_i_95_n_0\,
S(2) => \cb_int[31]_i_96_n_0\,
S(1) => \cb_int[31]_i_97_n_0\,
S(0) => \cb_int[31]_i_98_n_0\
);
\cb_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[3]_i_1_n_4\,
Q => \cb_int_reg_n_0_[3]\,
R => '0'
);
\cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_1_n_0\,
CO(2) => \cb_int_reg[3]_i_1_n_1\,
CO(1) => \cb_int_reg[3]_i_1_n_2\,
CO(0) => \cb_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cb_int[3]_i_2_n_0\,
DI(2) => \cb_int[3]_i_3_n_0\,
DI(1) => \cb_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cb_int_reg[3]_i_1_n_4\,
O(2) => \cb_int_reg[3]_i_1_n_5\,
O(1) => \cb_int_reg[3]_i_1_n_6\,
O(0) => \cb_int_reg[3]_i_1_n_7\,
S(3) => \cb_int[3]_i_5_n_0\,
S(2) => \cb_int[3]_i_6_n_0\,
S(1) => \cb_int[3]_i_7_n_0\,
S(0) => \cb_int[3]_i_8_n_0\
);
\cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_21_n_0\,
CO(3) => \cb_int_reg[3]_i_15_n_0\,
CO(2) => \cb_int_reg[3]_i_15_n_1\,
CO(1) => \cb_int_reg[3]_i_15_n_2\,
CO(0) => \cb_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => cb_int_reg7(10 downto 8),
O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_22_n_0\,
S(2) => \cb_int[3]_i_23_n_0\,
S(1) => \cb_int[3]_i_24_n_0\,
S(0) => \cb_int[3]_i_25_n_0\
);
\cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_26_n_0\,
CO(3) => \cb_int_reg[3]_i_16_n_0\,
CO(2) => \cb_int_reg[3]_i_16_n_1\,
CO(1) => \cb_int_reg[3]_i_16_n_2\,
CO(0) => \cb_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_27_n_0\,
DI(2 downto 0) => rgb888(21 downto 19),
O(3) => \cb_int_reg[3]_i_16_n_4\,
O(2) => \cb_int_reg[3]_i_16_n_5\,
O(1) => \cb_int_reg[3]_i_16_n_6\,
O(0) => \cb_int_reg[3]_i_16_n_7\,
S(3) => \cb_int[3]_i_28_n_0\,
S(2) => \cb_int[3]_i_29_n_0\,
S(1) => \cb_int[3]_i_30_n_0\,
S(0) => \cb_int[3]_i_31_n_0\
);
\cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[27]_0\(0),
CO(2) => \cb_int_reg[3]_i_20_n_1\,
CO(1) => \cb_int_reg[3]_i_20_n_2\,
CO(0) => \cb_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[0]_8\(1 downto 0),
DI(1) => \cb_int_reg[3]_i_44_n_4\,
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_20_n_4\,
O(2) => \cb_int_reg[3]_i_20_n_5\,
O(1) => \cb_int_reg[3]_i_20_n_6\,
O(0) => \cb_int_reg[3]_i_20_n_7\,
S(3) => \cb_int[3]_i_45_n_0\,
S(2) => \cb_int[3]_i_46_n_0\,
S(1) => \cb_int[3]_i_47_n_0\,
S(0) => \cb_int[3]_i_48_n_0\
);
\cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_21_n_0\,
CO(2) => \cb_int_reg[3]_i_21_n_1\,
CO(1) => \cb_int_reg[3]_i_21_n_2\,
CO(0) => \cb_int_reg[3]_i_21_n_3\,
CYINIT => \cb_int[3]_i_49_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_50_n_0\,
S(2) => \cb_int[3]_i_51_n_0\,
S(1) => \cb_int[3]_i_52_n_0\,
S(0) => \cb_int[3]_i_53_n_0\
);
\cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_26_n_0\,
CO(2) => \cb_int_reg[3]_i_26_n_1\,
CO(1) => \cb_int_reg[3]_i_26_n_2\,
CO(0) => \cb_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(18 downto 16),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_26_n_4\,
O(2) => \cb_int_reg[3]_i_26_n_5\,
O(1) => \cb_int_reg[3]_i_26_n_6\,
O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0),
S(3) => \cb_int[3]_i_54_n_0\,
S(2) => \cb_int[3]_i_55_n_0\,
S(1) => \cb_int[3]_i_56_n_0\,
S(0) => '0'
);
\cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_63_n_0\,
CO(3) => \cb_int_reg[3]_i_33_n_0\,
CO(2) => \cb_int_reg[3]_i_33_n_1\,
CO(1) => \cb_int_reg[3]_i_33_n_2\,
CO(0) => \cb_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_33_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_64_n_0\,
S(2) => \cb_int[3]_i_65_n_0\,
S(1) => \cb_int[3]_i_66_n_0\,
S(0) => \cb_int[3]_i_67_n_0\
);
\cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_2\(0),
CO(2) => \cb_int_reg[3]_i_34_n_1\,
CO(1) => \cb_int_reg[3]_i_34_n_2\,
CO(0) => \cb_int_reg[3]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 1) => \rgb888[8]_31\(2 downto 0),
DI(0) => '0',
O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0),
S(3) => \cb_int[3]_i_69_n_0\,
S(2) => \cb_int[3]_i_70_n_0\,
S(1) => \cb_int[3]_i_71_n_0\,
S(0) => \cb_int[3]_i_72_n_0\
);
\cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_75_n_0\,
CO(3) => \cb_int_reg[3]_3\(0),
CO(2) => \cb_int_reg[3]_i_44_n_1\,
CO(1) => \cb_int_reg[3]_i_44_n_2\,
CO(0) => \cb_int_reg[3]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(5 downto 2),
O(3) => \cb_int_reg[3]_i_44_n_4\,
O(2) => \cb_int_reg[3]_i_44_n_5\,
O(1) => \cb_int_reg[3]_i_44_n_6\,
O(0) => \cb_int_reg[3]_i_44_n_7\,
S(3) => \cb_int[3]_i_76_n_0\,
S(2) => \cb_int[3]_i_77_n_0\,
S(1) => \cb_int[3]_i_78_n_0\,
S(0) => \cb_int[3]_i_79_n_0\
);
\cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_57_n_0\,
CO(2) => \cb_int_reg[3]_i_57_n_1\,
CO(1) => \cb_int_reg[3]_i_57_n_2\,
CO(0) => \cb_int_reg[3]_i_57_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \cb_int_reg[3]_i_57_n_4\,
O(2) => \cb_int_reg[3]_i_57_n_5\,
O(1) => \cb_int_reg[3]_i_57_n_6\,
O(0) => \cb_int_reg[3]_i_57_n_7\,
S(3) => \cb_int[3]_i_80_n_0\,
S(2) => \cb_int[3]_i_81_n_0\,
S(1) => \cb_int[3]_i_82_n_0\,
S(0) => \cb_int[3]_i_83_n_0\
);
\cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_63_n_0\,
CO(2) => \cb_int_reg[3]_i_63_n_1\,
CO(1) => \cb_int_reg[3]_i_63_n_2\,
CO(0) => \cb_int_reg[3]_i_63_n_3\,
CYINIT => \cb_int[3]_i_89_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_90_n_0\,
S(2) => \cb_int[3]_i_91_n_0\,
S(1) => \cb_int[3]_i_92_n_0\,
S(0) => \cb_int[3]_i_93_n_0\
);
\cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_75_n_0\,
CO(2) => \cb_int_reg[3]_i_75_n_1\,
CO(1) => \cb_int_reg[3]_i_75_n_2\,
CO(0) => \cb_int_reg[3]_i_75_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(1 downto 0),
DI(1 downto 0) => B"01",
O(3) => \cb_int_reg[3]_i_75_n_4\,
O(2) => \cb_int_reg[3]_i_75_n_5\,
O(1) => \cb_int_reg[3]_i_75_n_6\,
O(0) => \cb_int_reg[3]_i_75_n_7\,
S(3) => \cb_int[3]_i_99_n_0\,
S(2) => \cb_int[3]_i_100_n_0\,
S(1) => \cb_int[3]_i_101_n_0\,
S(0) => \cb_int[3]_i_102_n_0\
);
\cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_1\(0),
CO(2) => \cb_int_reg[3]_i_94_n_1\,
CO(1) => \cb_int_reg[3]_i_94_n_2\,
CO(0) => \cb_int_reg[3]_i_94_n_3\,
CYINIT => '0',
DI(3) => rgb888(8),
DI(2 downto 0) => B"001",
O(3) => \cb_int_reg[3]_i_94_n_4\,
O(2 downto 1) => \^o\(1 downto 0),
O(0) => \cb_int_reg[3]_i_94_n_7\,
S(3) => \cb_int[3]_i_103_n_0\,
S(2) => \cb_int[3]_i_104_n_0\,
S(1) => \cb_int[3]_i_105_n_0\,
S(0) => \cb_int[3]_i_106_n_0\
);
\cb_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_7\,
Q => \cb_int_reg_n_0_[4]\,
R => '0'
);
\cb_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_6\,
Q => \cb_int_reg_n_0_[5]\,
R => '0'
);
\cb_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_5\,
Q => \cb_int_reg_n_0_[6]\,
R => '0'
);
\cb_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[7]_i_1_n_4\,
Q => \cb_int_reg_n_0_[7]\,
R => '0'
);
\cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_1_n_0\,
CO(3) => \cb_int_reg[7]_i_1_n_0\,
CO(2) => \cb_int_reg[7]_i_1_n_1\,
CO(1) => \cb_int_reg[7]_i_1_n_2\,
CO(0) => \cb_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_2_n_0\,
DI(2) => \cb_int[7]_i_3_n_0\,
DI(1) => \cb_int[7]_i_4_n_0\,
DI(0) => \cb_int[7]_i_5_n_0\,
O(3) => \cb_int_reg[7]_i_1_n_4\,
O(2) => \cb_int_reg[7]_i_1_n_5\,
O(1) => \cb_int_reg[7]_i_1_n_6\,
O(0) => \cb_int_reg[7]_i_1_n_7\,
S(3) => \cb_int[7]_i_6_n_0\,
S(2) => \cb_int[7]_i_7_n_0\,
S(1) => \cb_int[7]_i_8_n_0\,
S(0) => \cb_int[7]_i_9_n_0\
);
\cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_38_n_0\,
CO(3) => \^co\(0),
CO(2) => \cb_int_reg[7]_i_25_n_1\,
CO(1) => \cb_int_reg[7]_i_25_n_2\,
CO(0) => \cb_int_reg[7]_i_25_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_39_n_0\,
S(2) => \cb_int[7]_i_40_n_0\,
S(1) => \cb_int[7]_i_41_n_0\,
S(0) => \cb_int[7]_i_42_n_0\
);
\cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_28_n_0\,
CO(2) => \cb_int_reg[7]_i_28_n_1\,
CO(1) => \cb_int_reg[7]_i_28_n_2\,
CO(0) => \cb_int_reg[7]_i_28_n_3\,
CYINIT => \cb_int[7]_i_52_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cb_int_reg3(4 downto 1),
S(3) => \cb_int[7]_i_53_n_0\,
S(2) => \cb_int[7]_i_54_n_0\,
S(1) => \cb_int[7]_i_55_n_0\,
S(0) => \cb_int[7]_i_56_n_0\
);
\cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_33_n_0\,
CO(3) => \cb_int_reg[7]_i_29_n_0\,
CO(2) => \cb_int_reg[7]_i_29_n_1\,
CO(1) => \cb_int_reg[7]_i_29_n_2\,
CO(0) => \cb_int_reg[7]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_29_n_4\,
O(2) => \cb_int_reg[7]_i_29_n_5\,
O(1) => \cb_int_reg[7]_i_29_n_6\,
O(0) => \cb_int_reg[7]_i_29_n_7\,
S(3) => \cb_int[7]_i_57_n_0\,
S(2) => \cb_int[7]_i_58_n_0\,
S(1) => \cb_int[7]_i_59_n_0\,
S(0) => \cb_int[7]_i_60_n_0\
);
\cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_61_n_0\,
CO(3) => \cb_int_reg[7]_i_38_n_0\,
CO(2) => \cb_int_reg[7]_i_38_n_1\,
CO(1) => \cb_int_reg[7]_i_38_n_2\,
CO(0) => \cb_int_reg[7]_i_38_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_1\(1),
DI(2) => \rgb888[8]_1\(1),
DI(1) => \rgb888[8]_1\(1),
DI(0) => \rgb888[8]_1\(1),
O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_62_n_0\,
S(2) => \cb_int[7]_i_63_n_0\,
S(1) => \cb_int[7]_i_64_n_0\,
S(0) => \cb_int[7]_i_65_n_0\
);
\cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_66_n_0\,
CO(3) => \cb_int_reg[7]_i_61_n_0\,
CO(2) => \cb_int_reg[7]_i_61_n_1\,
CO(1) => \cb_int_reg[7]_i_61_n_2\,
CO(0) => \cb_int_reg[7]_i_61_n_3\,
CYINIT => '0',
DI(3) => \cb_int[7]_i_67_n_0\,
DI(2) => \cb_int[7]_i_68_n_0\,
DI(1) => \cb_int[7]_i_69_n_0\,
DI(0) => \cb_int[7]_i_70_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_71_n_0\,
S(2) => \cb_int[7]_i_72_n_0\,
S(1) => \cb_int[7]_i_73_n_0\,
S(0) => \cb_int[7]_i_74_n_0\
);
\cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_66_n_0\,
CO(2) => \cb_int_reg[7]_i_66_n_1\,
CO(1) => \cb_int_reg[7]_i_66_n_2\,
CO(0) => \cb_int_reg[7]_i_66_n_3\,
CYINIT => '1',
DI(3) => \cb_int[7]_i_75_n_0\,
DI(2) => \cb_int[7]_i_76_n_0\,
DI(1) => \cb_int[7]_i_77_n_0\,
DI(0) => \cb_int[7]_i_78_n_0\,
O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[7]_i_79_n_0\,
S(2) => \cb_int[7]_i_80_n_0\,
S(1) => \cb_int[7]_i_81_n_0\,
S(0) => \cb_int[7]_i_82_n_0\
);
\cb_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_7\,
Q => \cb_int_reg__0\(8),
R => '0'
);
\cb_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cb_int_reg[11]_i_1_n_6\,
Q => \cb_int_reg__0\(9),
R => '0'
);
\cb_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[0]_i_1_n_0\,
Q => cb(0),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[1]_i_1_n_0\,
Q => cb(1),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[2]_i_1_n_0\,
Q => cb(2),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[3]_i_1_n_0\,
Q => cb(3),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[4]_i_1_n_0\,
Q => cb(4),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[5]_i_1_n_0\,
Q => cb(5),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[6]_i_1_n_0\,
Q => cb(6),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cb[7]_i_2_n_0\,
Q => cb(7),
S => \cb_reg[7]_i_1_n_0\
);
\cb_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_3_n_0\,
CO(3) => \cb_reg[7]_i_1_n_0\,
CO(2) => \cb_reg[7]_i_1_n_1\,
CO(1) => \cb_reg[7]_i_1_n_2\,
CO(0) => \cb_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_4_n_0\,
DI(2) => \cb[7]_i_5_n_0\,
DI(1) => \cb[7]_i_6_n_0\,
DI(0) => \cb[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_8_n_0\,
S(2) => \cb[7]_i_9_n_0\,
S(1) => \cb[7]_i_10_n_0\,
S(0) => \cb[7]_i_11_n_0\
);
\cb_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_reg[7]_i_12_n_0\,
CO(2) => \cb_reg[7]_i_12_n_1\,
CO(1) => \cb_reg[7]_i_12_n_2\,
CO(0) => \cb_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_21_n_0\,
DI(2) => \cb[7]_i_22_n_0\,
DI(1) => \cb[7]_i_23_n_0\,
DI(0) => \cb[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_25_n_0\,
S(2) => \cb[7]_i_26_n_0\,
S(1) => \cb[7]_i_27_n_0\,
S(0) => \cb[7]_i_28_n_0\
);
\cb_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cb_reg[7]_i_12_n_0\,
CO(3) => \cb_reg[7]_i_3_n_0\,
CO(2) => \cb_reg[7]_i_3_n_1\,
CO(1) => \cb_reg[7]_i_3_n_2\,
CO(0) => \cb_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cb[7]_i_13_n_0\,
DI(2) => \cb[7]_i_14_n_0\,
DI(1) => \cb[7]_i_15_n_0\,
DI(0) => \cb[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cb[7]_i_17_n_0\,
S(2) => \cb[7]_i_18_n_0\,
S(1) => \cb[7]_i_19_n_0\,
S(0) => \cb[7]_i_20_n_0\
);
cb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk,
O => cb_regn_0_0
);
\cr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[0]\,
I1 => \cr_int_reg__0\(31),
O => \cr[0]_i_1_n_0\
);
\cr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[1]\,
I1 => \cr_int_reg__0\(31),
O => \cr[1]_i_1_n_0\
);
\cr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[2]\,
I1 => \cr_int_reg__0\(31),
O => \cr[2]_i_1_n_0\
);
\cr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[3]\,
I1 => \cr_int_reg__0\(31),
O => \cr[3]_i_1_n_0\
);
\cr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[4]\,
I1 => \cr_int_reg__0\(31),
O => \cr[4]_i_1_n_0\
);
\cr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[5]\,
I1 => \cr_int_reg__0\(31),
O => \cr[5]_i_1_n_0\
);
\cr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[6]\,
I1 => \cr_int_reg__0\(31),
O => \cr[6]_i_1_n_0\
);
\cr[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_10_n_0\
);
\cr[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_11_n_0\
);
\cr[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_13_n_0\
);
\cr[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_14_n_0\
);
\cr[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_15_n_0\
);
\cr[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_16_n_0\
);
\cr[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(22),
I1 => \cr_int_reg__0\(23),
O => \cr[7]_i_17_n_0\
);
\cr[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(20),
I1 => \cr_int_reg__0\(21),
O => \cr[7]_i_18_n_0\
);
\cr[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(18),
I1 => \cr_int_reg__0\(19),
O => \cr[7]_i_19_n_0\
);
\cr[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg_n_0_[7]\,
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_2_n_0\
);
\cr[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(16),
I1 => \cr_int_reg__0\(17),
O => \cr[7]_i_20_n_0\
);
\cr[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_21_n_0\
);
\cr[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_22_n_0\
);
\cr[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_23_n_0\
);
\cr[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_24_n_0\
);
\cr[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(14),
I1 => \cr_int_reg__0\(15),
O => \cr[7]_i_25_n_0\
);
\cr[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(12),
I1 => \cr_int_reg__0\(13),
O => \cr[7]_i_26_n_0\
);
\cr[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(10),
I1 => \cr_int_reg__0\(11),
O => \cr[7]_i_27_n_0\
);
\cr[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(8),
I1 => \cr_int_reg__0\(9),
O => \cr[7]_i_28_n_0\
);
\cr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_4_n_0\
);
\cr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_5_n_0\
);
\cr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(26),
I1 => \cr_int_reg__0\(27),
O => \cr[7]_i_6_n_0\
);
\cr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg__0\(24),
I1 => \cr_int_reg__0\(25),
O => \cr[7]_i_7_n_0\
);
\cr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(30),
I1 => \cr_int_reg__0\(31),
O => \cr[7]_i_8_n_0\
);
\cr[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg__0\(28),
I1 => \cr_int_reg__0\(29),
O => \cr[7]_i_9_n_0\
);
\cr_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(0),
Q => \cr_hold_reg_n_0_[0]\,
R => '0'
);
\cr_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(1),
Q => \cr_hold_reg_n_0_[1]\,
R => '0'
);
\cr_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(2),
Q => \cr_hold_reg_n_0_[2]\,
R => '0'
);
\cr_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(3),
Q => \cr_hold_reg_n_0_[3]\,
R => '0'
);
\cr_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(4),
Q => \cr_hold_reg_n_0_[4]\,
R => '0'
);
\cr_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(5),
Q => \cr_hold_reg_n_0_[5]\,
R => '0'
);
\cr_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(6),
Q => \cr_hold_reg_n_0_[6]\,
R => '0'
);
\cr_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \cb_hold[7]_i_1_n_0\,
D => cr(7),
Q => \cr_hold_reg_n_0_[7]\,
R => '0'
);
\cr_int[11]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[11]_i_10_n_0\
);
\cr_int[11]_i_100\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(11),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_100_n_0\
);
\cr_int[11]_i_101\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(10),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_101_n_0\
);
\cr_int[11]_i_102\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(9),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_102_n_0\
);
\cr_int[11]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_104_n_0\
);
\cr_int[11]_i_105\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_105_n_0\
);
\cr_int[11]_i_106\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_106_n_0\
);
\cr_int[11]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_107_n_0\
);
\cr_int[11]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
I1 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_109_n_0\
);
\cr_int[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_11_n_0\
);
\cr_int[11]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
I1 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_110_n_0\
);
\cr_int[11]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_111_n_0\
);
\cr_int[11]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_112_n_0\
);
\cr_int[11]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
I1 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_113_n_0\
);
\cr_int[11]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
I1 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_114_n_0\
);
\cr_int[11]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
I1 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_115_n_0\
);
\cr_int[11]_i_117\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
I1 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_117_n_0\
);
\cr_int[11]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
I1 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_118_n_0\
);
\cr_int[11]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
I1 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_119_n_0\
);
\cr_int[11]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(17),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(9),
I4 => \cr_int[11]_i_24_n_0\,
I5 => \cr_int[11]_i_25_n_0\,
O => \cr_int[11]_i_12_n_0\
);
\cr_int[11]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
I1 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_120_n_0\
);
\cr_int[11]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
I1 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_121_n_0\
);
\cr_int[11]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
I1 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_122_n_0\
);
\cr_int[11]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
I1 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_123_n_0\
);
\cr_int[11]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
I1 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_124_n_0\
);
\cr_int[11]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
I1 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_126_n_0\
);
\cr_int[11]_i_127\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
I1 => \^cr_int_reg[7]_0\(2),
O => \cr_int[11]_i_127_n_0\
);
\cr_int[11]_i_128\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
I1 => \^cr_int_reg[7]_0\(0),
O => \cr_int[11]_i_128_n_0\
);
\cr_int[11]_i_129\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_0\(1),
O => \cr_int[11]_i_129_n_0\
);
\cr_int[11]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"8EEE8E888EEE8EEE"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_13_n_0\
);
\cr_int[11]_i_130\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
I1 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_130_n_0\
);
\cr_int[11]_i_131\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
I1 => \^cr_int_reg[7]_0\(1),
O => \cr_int[11]_i_131_n_0\
);
\cr_int[11]_i_132\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
I1 => \^cr_int_reg[3]_0\(2),
O => \cr_int[11]_i_132_n_0\
);
\cr_int[11]_i_133\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
I1 => \^cr_int_reg[3]_0\(0),
O => \cr_int[11]_i_133_n_0\
);
\cr_int[11]_i_134\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
I1 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[11]_i_134_n_0\
);
\cr_int[11]_i_135\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
I1 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[11]_i_135_n_0\
);
\cr_int[11]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
I1 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[11]_i_136_n_0\
);
\cr_int[11]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[11]_i_137_n_0\
);
\cr_int[11]_i_138\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
I1 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[11]_i_138_n_0\
);
\cr_int[11]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
I1 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[11]_i_139_n_0\
);
\cr_int[11]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999696669996999"
)
port map (
I0 => \cr_int_reg3__0\(8),
I1 => \cr_int[11]_i_27_n_0\,
I2 => \cr_int_reg[11]_i_16_n_4\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_14_n_0\
);
\cr_int[11]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
I1 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[11]_i_140_n_0\
);
\cr_int[11]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
I1 => rgb888(0),
O => \cr_int[11]_i_141_n_0\
);
\cr_int[11]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
I1 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[11]_i_142_n_0\
);
\cr_int[11]_i_143\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
I1 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[11]_i_143_n_0\
);
\cr_int[11]_i_144\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
I1 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[11]_i_144_n_0\
);
\cr_int[11]_i_145\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
I1 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[11]_i_145_n_0\
);
\cr_int[11]_i_146\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
I1 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[11]_i_146_n_0\
);
\cr_int[11]_i_147\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
I1 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[11]_i_147_n_0\
);
\cr_int[11]_i_148\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
I1 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[11]_i_148_n_0\
);
\cr_int[11]_i_149\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
I1 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[11]_i_149_n_0\
);
\cr_int[11]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_15_n_0\
);
\cr_int[11]_i_150\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
I1 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[11]_i_150_n_0\
);
\cr_int[11]_i_151\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
I1 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[11]_i_151_n_0\
);
\cr_int[11]_i_152\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => rgb888(8),
O => \cr_int[11]_i_152_n_0\
);
\cr_int[11]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
I1 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[11]_i_153_n_0\
);
\cr_int[11]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
I1 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[11]_i_154_n_0\
);
\cr_int[11]_i_155\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
I2 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[11]_i_155_n_0\
);
\cr_int[11]_i_156\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[11]_i_156_n_0\
);
\cr_int[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
O => \cr_int[11]_i_2_n_0\
);
\cr_int[11]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFDF202"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_22_n_0\
);
\cr_int[11]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0DFD"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \^cr_int_reg[27]_2\(0),
I3 => \cr_int_reg[11]_i_16_n_5\,
I4 => \cr_int[11]_i_15_n_0\,
O => \cr_int[11]_i_23_n_0\
);
\cr_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(3),
O => \cr_int[11]_i_24_n_0\
);
\cr_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(0),
O => \cr_int[11]_i_25_n_0\
);
\cr_int[11]_i_26\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(8),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(16),
O => \cr_int_reg3__0\(8)
);
\cr_int[11]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_13\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[11]_0\(2),
O => \cr_int[11]_i_27_n_0\
);
\cr_int[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
O => \cr_int[11]_i_3_n_0\
);
\cr_int[11]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_4\,
O => \cr_int[11]_i_32_n_0\
);
\cr_int[11]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_33_n_0\
);
\cr_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[11]_i_34_n_0\
);
\cr_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_18_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_35_n_0\
);
\cr_int[11]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_37_n_0\
);
\cr_int[11]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_38_n_0\
);
\cr_int[11]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_39_n_0\
);
\cr_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8A888AAA8AAA"
)
port map (
I0 => \cr_int[11]_i_14_n_0\,
I1 => \cr_int[11]_i_15_n_0\,
I2 => \cr_int_reg[11]_i_16_n_5\,
I3 => \^cr_int_reg[27]_2\(0),
I4 => \cr_int_reg[11]_i_17_n_0\,
I5 => \cr_int_reg[11]_i_18_n_5\,
O => \cr_int[11]_i_4_n_0\
);
\cr_int[11]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_40_n_0\
);
\cr_int[11]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_42_n_0\
);
\cr_int[11]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_43_n_0\
);
\cr_int[11]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_44_n_0\
);
\cr_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[11]_i_45_n_0\
);
\cr_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_47_n_0\
);
\cr_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_48_n_0\
);
\cr_int[11]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_49_n_0\
);
\cr_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE200E200000000"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => \cr_int_reg[31]_i_11_n_4\,
I4 => cr_int_reg4(7),
I5 => \cr_int[11]_i_22_n_0\,
O => \cr_int[11]_i_5_n_0\
);
\cr_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_50_n_0\
);
\cr_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_52_n_0\
);
\cr_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_53_n_0\
);
\cr_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_54_n_0\
);
\cr_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_55_n_0\
);
\cr_int[11]_i_57\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(16),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_57_n_0\
);
\cr_int[11]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(15),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_6\,
O => \cr_int[11]_i_58_n_0\
);
\cr_int[11]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(14),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_11_n_7\,
O => \cr_int[11]_i_59_n_0\
);
\cr_int[11]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
I2 => \cr_int[11]_i_2_n_0\,
O => \cr_int[11]_i_6_n_0\
);
\cr_int[11]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(13),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_4\,
O => \cr_int[11]_i_60_n_0\
);
\cr_int[11]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_65_n_0\
);
\cr_int[11]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_66_n_0\
);
\cr_int[11]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(0),
O => \cr_int[11]_i_67_n_0\
);
\cr_int[11]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(3),
O => \cr_int[11]_i_68_n_0\
);
\cr_int[11]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_10_n_0\,
I1 => \cr_int[11]_i_11_n_0\,
I2 => \cr_int[11]_i_3_n_0\,
O => \cr_int[11]_i_7_n_0\
);
\cr_int[11]_i_70\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_70_n_0\
);
\cr_int[11]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_71_n_0\
);
\cr_int[11]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_72_n_0\
);
\cr_int[11]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[11]_i_73_n_0\
);
\cr_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[3]_i_32_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[11]_i_74_n_0\
);
\cr_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_4\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_75_n_0\
);
\cr_int[11]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_5\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_76_n_0\
);
\cr_int[11]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_77_n_0\
);
\cr_int[11]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cr_int_reg[11]_i_41_n_7\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_78_n_0\
);
\cr_int[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_12_n_0\,
I1 => \cr_int[11]_i_13_n_0\,
I2 => \cr_int[11]_i_4_n_0\,
O => \cr_int[11]_i_8_n_0\
);
\cr_int[11]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_80_n_0\
);
\cr_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_81_n_0\
);
\cr_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_82_n_0\
);
\cr_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
O => \cr_int[11]_i_83_n_0\
);
\cr_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[11]_i_84_n_0\
);
\cr_int[11]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[11]_i_85_n_0\
);
\cr_int[11]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[11]_i_86_n_0\
);
\cr_int[11]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[11]_i_87_n_0\
);
\cr_int[11]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_88_n_0\
);
\cr_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_6\,
O => \cr_int[11]_i_89_n_0\
);
\cr_int[11]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[11]_i_5_n_0\,
I1 => \cr_int[11]_i_14_n_0\,
I2 => \cr_int[11]_i_23_n_0\,
O => \cr_int[11]_i_9_n_0\
);
\cr_int[11]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_30_n_7\,
O => \cr_int[11]_i_90_n_0\
);
\cr_int[11]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_4\,
O => \cr_int[11]_i_91_n_0\
);
\cr_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_5\,
I1 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_93_n_0\
);
\cr_int[11]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_94_n_0\
);
\cr_int[11]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_95_n_0\
);
\cr_int[11]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[11]_i_96_n_0\
);
\cr_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => \cr_int_reg[31]_i_11_n_5\,
O => \cr_int[11]_i_97_n_0\
);
\cr_int[11]_i_98\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[11]_i_98_n_0\
);
\cr_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => cr_int_reg6(12),
I1 => cr_int_reg7,
I2 => \cr_int_reg[31]_i_30_n_5\,
O => \cr_int[11]_i_99_n_0\
);
\cr_int[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[15]_i_10_n_0\
);
\cr_int[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_11_n_0\
);
\cr_int[15]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(21),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(13),
I4 => \cr_int[15]_i_18_n_0\,
I5 => \cr_int[15]_i_19_n_0\,
O => \cr_int[15]_i_12_n_0\
);
\cr_int[15]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_13_n_0\
);
\cr_int[15]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(20),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(12),
I4 => \cr_int[15]_i_22_n_0\,
I5 => \cr_int[15]_i_23_n_0\,
O => \cr_int[15]_i_14_n_0\
);
\cr_int[15]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_15_n_0\
);
\cr_int[15]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(19),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(11),
I4 => \cr_int[15]_i_24_n_0\,
I5 => \cr_int[15]_i_25_n_0\,
O => \cr_int[15]_i_16_n_0\
);
\cr_int[15]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(18),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(10),
I4 => \cr_int[15]_i_26_n_0\,
I5 => \cr_int[15]_i_27_n_0\,
O => \cr_int[15]_i_17_n_0\
);
\cr_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(3),
O => \cr_int[15]_i_18_n_0\
);
\cr_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(0),
O => \cr_int[15]_i_19_n_0\
);
\cr_int[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
O => \cr_int[15]_i_2_n_0\
);
\cr_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(2),
O => \cr_int[15]_i_22_n_0\
);
\cr_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(3),
O => \cr_int[15]_i_23_n_0\
);
\cr_int[15]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(1),
O => \cr_int[15]_i_24_n_0\
);
\cr_int[15]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(2),
O => \cr_int[15]_i_25_n_0\
);
\cr_int[15]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_14\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[15]_0\(0),
O => \cr_int[15]_i_26_n_0\
);
\cr_int[15]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[15]_i_38_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]\(1),
O => \cr_int[15]_i_27_n_0\
);
\cr_int[15]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_29_n_0\
);
\cr_int[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
O => \cr_int[15]_i_3_n_0\
);
\cr_int[15]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_30_n_0\
);
\cr_int[15]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_31_n_0\
);
\cr_int[15]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[15]_i_32_n_0\
);
\cr_int[15]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(20),
O => \cr_int[15]_i_33_n_0\
);
\cr_int[15]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(19),
O => \cr_int[15]_i_34_n_0\
);
\cr_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(18),
O => \cr_int[15]_i_35_n_0\
);
\cr_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(17),
O => \cr_int[15]_i_36_n_0\
);
\cr_int[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
O => \cr_int[15]_i_4_n_0\
);
\cr_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_40_n_0\
);
\cr_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_41_n_0\
);
\cr_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_42_n_0\
);
\cr_int[15]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[15]_i_43_n_0\
);
\cr_int[15]_i_48\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(3),
O => \cr_int[15]_i_48_n_0\
);
\cr_int[15]_i_49\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(2),
O => \cr_int[15]_i_49_n_0\
);
\cr_int[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[15]_i_16_n_0\,
I1 => \cr_int[15]_i_17_n_0\,
O => \cr_int[15]_i_5_n_0\
);
\cr_int[15]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(1),
O => \cr_int[15]_i_50_n_0\
);
\cr_int[15]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]\(0),
O => \cr_int[15]_i_51_n_0\
);
\cr_int[15]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
I2 => \cr_int[15]_i_2_n_0\,
O => \cr_int[15]_i_6_n_0\
);
\cr_int[15]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_10_n_0\,
I1 => \cr_int[15]_i_11_n_0\,
I2 => \cr_int[15]_i_3_n_0\,
O => \cr_int[15]_i_7_n_0\
);
\cr_int[15]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_12_n_0\,
I1 => \cr_int[15]_i_13_n_0\,
I2 => \cr_int[15]_i_4_n_0\,
O => \cr_int[15]_i_8_n_0\
);
\cr_int[15]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[15]_i_14_n_0\,
I1 => \cr_int[15]_i_15_n_0\,
I2 => \cr_int[15]_i_5_n_0\,
O => \cr_int[15]_i_9_n_0\
);
\cr_int[19]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[19]_i_10_n_0\
);
\cr_int[19]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_11_n_0\
);
\cr_int[19]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(25),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(17),
I4 => \cr_int[19]_i_18_n_0\,
I5 => \cr_int[19]_i_19_n_0\,
O => \cr_int[19]_i_12_n_0\
);
\cr_int[19]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_13_n_0\
);
\cr_int[19]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(24),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(16),
I4 => \cr_int[19]_i_22_n_0\,
I5 => \cr_int[19]_i_23_n_0\,
O => \cr_int[19]_i_14_n_0\
);
\cr_int[19]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_15_n_0\
);
\cr_int[19]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(23),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(15),
I4 => \cr_int[19]_i_24_n_0\,
I5 => \cr_int[19]_i_25_n_0\,
O => \cr_int[19]_i_16_n_0\
);
\cr_int[19]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(22),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(14),
I4 => \cr_int[19]_i_26_n_0\,
I5 => \cr_int[19]_i_27_n_0\,
O => \cr_int[19]_i_17_n_0\
);
\cr_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(3),
O => \cr_int[19]_i_18_n_0\
);
\cr_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(0),
O => \cr_int[19]_i_19_n_0\
);
\cr_int[19]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
O => \cr_int[19]_i_2_n_0\
);
\cr_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(2),
O => \cr_int[19]_i_22_n_0\
);
\cr_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(3),
O => \cr_int[19]_i_23_n_0\
);
\cr_int[19]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(1),
O => \cr_int[19]_i_24_n_0\
);
\cr_int[19]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(2),
O => \cr_int[19]_i_25_n_0\
);
\cr_int[19]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_15\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[19]_0\(0),
O => \cr_int[19]_i_26_n_0\
);
\cr_int[19]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_49_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[3]_0\(1),
O => \cr_int[19]_i_27_n_0\
);
\cr_int[19]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_29_n_0\
);
\cr_int[19]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
O => \cr_int[19]_i_3_n_0\
);
\cr_int[19]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_30_n_0\
);
\cr_int[19]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_31_n_0\
);
\cr_int[19]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[19]_i_32_n_0\
);
\cr_int[19]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(24),
O => \cr_int[19]_i_33_n_0\
);
\cr_int[19]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(23),
O => \cr_int[19]_i_34_n_0\
);
\cr_int[19]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(22),
O => \cr_int[19]_i_35_n_0\
);
\cr_int[19]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(21),
O => \cr_int[19]_i_36_n_0\
);
\cr_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_38_n_0\
);
\cr_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_39_n_0\
);
\cr_int[19]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
O => \cr_int[19]_i_4_n_0\
);
\cr_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_40_n_0\
);
\cr_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[19]_i_41_n_0\
);
\cr_int[19]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[19]_i_16_n_0\,
I1 => \cr_int[19]_i_17_n_0\,
O => \cr_int[19]_i_5_n_0\
);
\cr_int[19]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
I2 => \cr_int[19]_i_2_n_0\,
O => \cr_int[19]_i_6_n_0\
);
\cr_int[19]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_10_n_0\,
I1 => \cr_int[19]_i_11_n_0\,
I2 => \cr_int[19]_i_3_n_0\,
O => \cr_int[19]_i_7_n_0\
);
\cr_int[19]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_12_n_0\,
I1 => \cr_int[19]_i_13_n_0\,
I2 => \cr_int[19]_i_4_n_0\,
O => \cr_int[19]_i_8_n_0\
);
\cr_int[19]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[19]_i_14_n_0\,
I1 => \cr_int[19]_i_15_n_0\,
I2 => \cr_int[19]_i_5_n_0\,
O => \cr_int[19]_i_9_n_0\
);
\cr_int[23]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[23]_i_10_n_0\
);
\cr_int[23]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_11_n_0\
);
\cr_int[23]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(29),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(21),
I4 => \cr_int[23]_i_18_n_0\,
I5 => \cr_int[23]_i_19_n_0\,
O => \cr_int[23]_i_12_n_0\
);
\cr_int[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_13_n_0\
);
\cr_int[23]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(28),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(20),
I4 => \cr_int[23]_i_21_n_0\,
I5 => \cr_int[23]_i_22_n_0\,
O => \cr_int[23]_i_14_n_0\
);
\cr_int[23]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_15_n_0\
);
\cr_int[23]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4040BFB0BFBF404"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(27),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(19),
I4 => \cr_int[23]_i_23_n_0\,
I5 => \cr_int[23]_i_24_n_0\,
O => \cr_int[23]_i_16_n_0\
);
\cr_int[23]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(26),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(18),
I4 => \cr_int[23]_i_25_n_0\,
I5 => \cr_int[23]_i_26_n_0\,
O => \cr_int[23]_i_17_n_0\
);
\cr_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(3),
O => \cr_int[23]_i_18_n_0\
);
\cr_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(0),
O => \cr_int[23]_i_19_n_0\
);
\cr_int[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
O => \cr_int[23]_i_2_n_0\
);
\cr_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(2),
O => \cr_int[23]_i_21_n_0\
);
\cr_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(3),
O => \cr_int[23]_i_22_n_0\
);
\cr_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(1),
O => \cr_int[23]_i_23_n_0\
);
\cr_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(2),
O => \cr_int[23]_i_24_n_0\
);
\cr_int[23]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_16\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_0\(0),
O => \cr_int[23]_i_25_n_0\
);
\cr_int[23]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_21_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_5\(1),
O => \cr_int[23]_i_26_n_0\
);
\cr_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_27_n_0\
);
\cr_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_28_n_0\
);
\cr_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_29_n_0\
);
\cr_int[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
O => \cr_int[23]_i_3_n_0\
);
\cr_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[23]_i_30_n_0\
);
\cr_int[23]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
O => \cr_int[23]_i_4_n_0\
);
\cr_int[23]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[23]_i_16_n_0\,
I1 => \cr_int[23]_i_17_n_0\,
O => \cr_int[23]_i_5_n_0\
);
\cr_int[23]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
I2 => \cr_int[23]_i_2_n_0\,
O => \cr_int[23]_i_6_n_0\
);
\cr_int[23]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_10_n_0\,
I1 => \cr_int[23]_i_11_n_0\,
I2 => \cr_int[23]_i_3_n_0\,
O => \cr_int[23]_i_7_n_0\
);
\cr_int[23]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_12_n_0\,
I1 => \cr_int[23]_i_13_n_0\,
I2 => \cr_int[23]_i_4_n_0\,
O => \cr_int[23]_i_8_n_0\
);
\cr_int[23]_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[23]_i_14_n_0\,
I1 => \cr_int[23]_i_15_n_0\,
I2 => \cr_int[23]_i_5_n_0\,
O => \cr_int[23]_i_9_n_0\
);
\cr_int[27]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \rgb888[8]_17\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_1\(0),
I3 => \^cr_int_reg[23]_1\(0),
O => \cr_int[27]_i_10_n_0\
);
\cr_int[27]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[31]_i_8_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \rgb888[0]_6\(1),
O => \cr_int[27]_i_11_n_0\
);
\cr_int[27]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_12_n_0\
);
\cr_int[27]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
O => \cr_int[27]_i_13_n_0\
);
\cr_int[27]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \cr_int[27]_i_7_n_0\,
I1 => \cr_int[27]_i_8_n_0\,
O => \cr_int[27]_i_2_n_0\
);
\cr_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_3_n_0\
);
\cr_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_4_n_0\
);
\cr_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_5_n_0\
);
\cr_int[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[27]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_6_n_0\
);
\cr_int[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"4B44B4BB4B444B44"
)
port map (
I0 => \cr_int_reg[31]_i_12_n_1\,
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \rgb888[8]_18\(0),
I3 => \^cr_int_reg[31]_2\(1),
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[27]_i_7_n_0\
);
\cr_int[27]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => cr_int_reg7,
I1 => cr_int_reg6(30),
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => cr_int_reg4(22),
I4 => \cr_int[27]_i_10_n_0\,
I5 => \cr_int[27]_i_11_n_0\,
O => \cr_int[27]_i_8_n_0\
);
\cr_int[31]_i_100\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(14),
I5 => rgb888(15),
O => \cr_int[31]_i_100_n_0\
);
\cr_int[31]_i_103\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_103_n_0\
);
\cr_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_108_n_0\
);
\cr_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_109_n_0\
);
\cr_int[31]_i_110\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_110_n_0\
);
\cr_int[31]_i_111\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_111_n_0\
);
\cr_int[31]_i_112\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_112_n_0\
);
\cr_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \cr_int[31]_i_113_n_0\
);
\cr_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \cr_int[31]_i_114_n_0\
);
\cr_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \cr_int[31]_i_115_n_0\
);
\cr_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_116_n_0\
);
\cr_int[31]_i_117\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \cr_int[31]_i_117_n_0\
);
\cr_int[31]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \cr_int[31]_i_118_n_0\
);
\cr_int[31]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \cr_int[31]_i_119_n_0\
);
\cr_int[31]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \cr_int[31]_i_120_n_0\
);
\cr_int[31]_i_121\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cr_int[31]_i_121_n_0\
);
\cr_int[31]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \cr_int[31]_i_122_n_0\
);
\cr_int[31]_i_123\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cr_int[31]_i_123_n_0\
);
\cr_int[31]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[31]_i_124_n_0\
);
\cr_int[31]_i_125\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
O => \cr_int[31]_i_125_n_0\
);
\cr_int[31]_i_126\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
O => \cr_int[31]_i_126_n_0\
);
\cr_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rgb888[8]_18\(0),
I1 => \^cr_int_reg[31]_2\(1),
O => \cr_int[31]_i_13_n_0\
);
\cr_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_15_n_0\
);
\cr_int[31]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_16_n_0\
);
\cr_int[31]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_17_n_0\
);
\cr_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => \^cr_int_reg[27]_0\,
O => \cr_int[31]_i_18_n_0\
);
\cr_int[31]_i_19\: unisim.vcomponents.LUT3
generic map(
INIT => X"17"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_2\,
I1 => \^cr_int_reg[27]_0\,
I2 => rgb888(7),
O => \cr_int[31]_i_19_n_0\
);
\cr_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DD0D0000"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[31]_i_8_n_1\,
I2 => \^cr_int_reg[31]_2\(1),
I3 => \rgb888[8]_18\(0),
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => \cr_int_reg[31]_i_12_n_1\,
O => \cr_int[31]_i_2_n_0\
);
\cr_int[31]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^cr_int_reg[27]_0\,
I1 => rgb888(7),
I2 => \cr_int[31]_i_16_n_0\,
I3 => \cr_int_reg[31]_i_48_n_2\,
O => \cr_int[31]_i_20_n_0\
);
\cr_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(1),
O => \cr_int[31]_i_22_n_0\
);
\cr_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_6\(0),
O => \cr_int[31]_i_23_n_0\
);
\cr_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cr_int[31]_i_25_n_0\
);
\cr_int[31]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_2\,
I1 => \^di\(0),
O => \cr_int[31]_i_26_n_0\
);
\cr_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_3_n_0\
);
\cr_int[31]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_31_n_0\
);
\cr_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_32_n_0\
);
\cr_int[31]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_33_n_0\
);
\cr_int[31]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_79_n_0\,
O => \cr_int[31]_i_34_n_0\
);
\cr_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(23),
I1 => \cr_int[31]_i_80_n_0\,
I2 => rgb888(22),
O => \cr_int[31]_i_35_n_0\
);
\cr_int[31]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(30),
O => \cr_int[31]_i_37_n_0\
);
\cr_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(29),
O => \cr_int[31]_i_38_n_0\
);
\cr_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_4_n_0\
);
\cr_int[31]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888888882"
)
port map (
I0 => \cr_int_reg[31]_i_48_n_7\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cr_int[31]_i_40_n_0\
);
\cr_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEEEEB"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_41_n_0\
);
\cr_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_4\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cr_int[31]_i_42_n_0\
);
\cr_int[31]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"82"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
O => \cr_int[31]_i_43_n_0\
);
\cr_int[31]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cr_int_reg[27]_1\(1),
I1 => \cr_int_reg[31]_i_48_n_2\,
I2 => \cr_int[31]_i_40_n_0\,
O => \cr_int[31]_i_44_n_0\
);
\cr_int[31]_i_45\: unisim.vcomponents.LUT4
generic map(
INIT => X"1EE1"
)
port map (
I0 => \cr_int[31]_i_92_n_0\,
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \^cr_int_reg[27]_1\(0),
I3 => \cr_int_reg[31]_i_48_n_7\,
O => \cr_int[31]_i_45_n_0\
);
\cr_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699999999996"
)
port map (
I0 => rgb888(4),
I1 => \cr_int_reg[31]_i_91_n_4\,
I2 => \cr_int_reg[31]_i_91_n_5\,
I3 => rgb888(2),
I4 => rgb888(1),
I5 => rgb888(3),
O => \cr_int[31]_i_46_n_0\
);
\cr_int[31]_i_47\: unisim.vcomponents.LUT5
generic map(
INIT => X"817E7E81"
)
port map (
I0 => \cr_int_reg[31]_i_91_n_6\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => \cr_int_reg[31]_i_91_n_5\,
O => \cr_int[31]_i_47_n_0\
);
\cr_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_5_n_0\
);
\cr_int[31]_i_50\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(3),
O => \cr_int[31]_i_50_n_0\
);
\cr_int[31]_i_51\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(2),
O => \cr_int[31]_i_51_n_0\
);
\cr_int[31]_i_52\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(1),
O => \cr_int[31]_i_52_n_0\
);
\cr_int[31]_i_53\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[0]_5\(0),
O => \cr_int[31]_i_53_n_0\
);
\cr_int[31]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_55_n_0\
);
\cr_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAA00000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_56_n_0\
);
\cr_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFEAAA2AAA8000"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_1\,
I1 => rgb888(11),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => rgb888(13),
I5 => \cr_int_reg[31]_i_102_n_4\,
O => \cr_int[31]_i_57_n_0\
);
\cr_int[31]_i_58\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => \cr_int_reg[31]_i_102_n_5\,
O => \cr_int[31]_i_58_n_0\
);
\cr_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \cr_int[31]_i_100_n_0\,
I1 => \^di\(0),
I2 => \cr_int_reg[31]_i_63_n_2\,
O => \cr_int[31]_i_59_n_0\
);
\cr_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6555559A65556555"
)
port map (
I0 => \cr_int[31]_i_2_n_0\,
I1 => \cr_int_reg[31]_i_12_n_1\,
I2 => \cr_int_reg[31]_i_11_n_4\,
I3 => \cr_int[31]_i_13_n_0\,
I4 => \cr_int_reg[31]_i_8_n_1\,
I5 => \^cr_int_reg[27]_2\(0),
O => \cr_int[31]_i_6_n_0\
);
\cr_int[31]_i_60\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \cr_int_reg[31]_i_63_n_7\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_2\,
I3 => \cr_int[31]_i_100_n_0\,
O => \cr_int[31]_i_60_n_0\
);
\cr_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int[31]_i_57_n_0\,
I1 => \^cr_int_reg[31]_0\,
I2 => \cr_int_reg[31]_i_63_n_7\,
O => \cr_int[31]_i_61_n_0\
);
\cr_int[31]_i_62\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[31]_i_58_n_0\,
I1 => \cr_int_reg[31]_i_102_n_4\,
I2 => \^cr_int_reg[31]_1\,
I3 => \cr_int_reg[31]_i_101_n_1\,
O => \cr_int[31]_i_62_n_0\
);
\cr_int[31]_i_71\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000001FFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_71_n_0\
);
\cr_int[31]_i_72\: unisim.vcomponents.LUT5
generic map(
INIT => X"0001FFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_72_n_0\
);
\cr_int[31]_i_73\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_73_n_0\
);
\cr_int[31]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
O => \cr_int[31]_i_74_n_0\
);
\cr_int[31]_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
I5 => rgb888(21),
O => \cr_int[31]_i_75_n_0\
);
\cr_int[31]_i_76\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(17),
I4 => rgb888(18),
I5 => rgb888(20),
O => \cr_int[31]_i_76_n_0\
);
\cr_int[31]_i_77\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(20),
I1 => \cr_int_reg[3]_i_26_n_1\,
I2 => rgb888(18),
I3 => rgb888(17),
I4 => rgb888(19),
O => \cr_int[31]_i_77_n_0\
);
\cr_int[31]_i_78\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_1\,
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
O => \cr_int[31]_i_78_n_0\
);
\cr_int[31]_i_79\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
I2 => rgb888(17),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(22),
O => \cr_int[31]_i_79_n_0\
);
\cr_int[31]_i_80\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(17),
I3 => rgb888(19),
I4 => rgb888(21),
O => \cr_int[31]_i_80_n_0\
);
\cr_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(28),
O => \cr_int[31]_i_81_n_0\
);
\cr_int[31]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(27),
O => \cr_int[31]_i_82_n_0\
);
\cr_int[31]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(26),
O => \cr_int[31]_i_83_n_0\
);
\cr_int[31]_i_84\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cr_int_reg[31]_i_11_n_4\,
I1 => cr_int_reg7,
I2 => cr_int_reg6(25),
O => \cr_int[31]_i_84_n_0\
);
\cr_int[31]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \cr_int[31]_i_85_n_0\
);
\cr_int[31]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => \cr_int_reg[31]_i_91_n_6\,
O => \cr_int[31]_i_87_n_0\
);
\cr_int[31]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => \cr_int_reg[31]_i_91_n_7\,
O => \cr_int[31]_i_88_n_0\
);
\cr_int[31]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_4\,
I1 => rgb888(0),
O => \cr_int[31]_i_89_n_0\
);
\cr_int[31]_i_90\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_5\,
O => \cr_int[31]_i_90_n_0\
);
\cr_int[31]_i_92\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
I3 => rgb888(4),
O => \cr_int[31]_i_92_n_0\
);
\cr_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cr_int[31]_i_93_n_0\
);
\cr_int[31]_i_94\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(3),
O => \cr_int[31]_i_94_n_0\
);
\cr_int[31]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(2),
O => \cr_int[31]_i_95_n_0\
);
\cr_int[31]_i_96\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(1),
O => \cr_int[31]_i_96_n_0\
);
\cr_int[31]_i_97\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^cr_int_reg[27]_2\(0),
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \rgb888[3]_0\(0),
O => \cr_int[31]_i_97_n_0\
);
\cr_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(2),
O => \cr_int[3]_i_10_n_0\
);
\cr_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_6\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_4\,
O => \cr_int[3]_i_11_n_0\
);
\cr_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(1),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[3]_i_16_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(9),
O => \cr_int_reg3__0\(1)
);
\cr_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[3]_2\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_13_n_0\
);
\cr_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_14_n_5\,
O => \cr_int[3]_i_14_n_0\
);
\cr_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
I1 => \^cr_int_reg[3]_1\(0),
I2 => \^cr_int_reg[3]_2\(0),
O => \cr_int[3]_i_17_n_0\
);
\cr_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
I1 => \cr_int_reg[11]_i_17_n_0\,
I2 => \cr_int_reg[3]_i_32_n_4\,
O => \cr_int[3]_i_18_n_0\
);
\cr_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
O => \cr_int[3]_i_2_n_0\
);
\cr_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_5\,
O => \cr_int[3]_i_22_n_0\
);
\cr_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_6\,
O => \cr_int[3]_i_23_n_0\
);
\cr_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_16_n_7\,
O => \cr_int[3]_i_24_n_0\
);
\cr_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_6\,
O => \cr_int[3]_i_25_n_0\
);
\cr_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(18),
I1 => rgb888(17),
I2 => \cr_int_reg[3]_i_26_n_6\,
O => \cr_int[3]_i_28_n_0\
);
\cr_int[3]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \cr_int_reg[3]_i_26_n_7\,
I1 => rgb888(17),
O => \cr_int[3]_i_29_n_0\
);
\cr_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
O => \cr_int[3]_i_3_n_0\
);
\cr_int[3]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_4\,
I1 => rgb888(16),
O => \cr_int[3]_i_30_n_0\
);
\cr_int[3]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_5\,
O => \cr_int[3]_i_31_n_0\
);
\cr_int[3]_i_34\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
O => \cr_int[3]_i_34_n_0\
);
\cr_int[3]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cr_int_reg[3]_i_64_n_4\,
I2 => \cr_int_reg[31]_i_102_n_7\,
O => \cr_int[3]_i_35_n_0\
);
\cr_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_36_n_0\
);
\cr_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_5\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_70_n_4\,
O => \cr_int[3]_i_37_n_0\
);
\cr_int[3]_i_38\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cr_int[3]_i_34_n_0\,
I1 => \cr_int_reg[31]_i_102_n_5\,
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cr_int_reg[31]_i_101_n_6\,
O => \cr_int[3]_i_38_n_0\
);
\cr_int[3]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cr_int_reg[31]_i_101_n_7\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => \cr_int_reg[31]_i_102_n_6\,
I4 => \cr_int[3]_i_35_n_0\,
O => \cr_int[3]_i_39_n_0\
);
\cr_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2FF"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_4_n_0\
);
\cr_int[3]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[31]_i_102_n_7\,
I4 => rgb888(10),
I5 => \cr_int_reg[3]_i_64_n_4\,
O => \cr_int[3]_i_40_n_0\
);
\cr_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => \cr_int_reg[3]_i_70_n_4\,
I1 => rgb888(9),
I2 => \cr_int_reg[3]_i_64_n_5\,
I3 => \cr_int_reg[3]_i_70_n_5\,
I4 => rgb888(8),
O => \cr_int[3]_i_41_n_0\
);
\cr_int[3]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(1),
O => \cr_int[3]_i_43_n_0\
);
\cr_int[3]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(0),
O => \cr_int[3]_i_44_n_0\
);
\cr_int[3]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_19_n_7\,
O => \cr_int[3]_i_45_n_0\
);
\cr_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_4\,
O => \cr_int[3]_i_46_n_0\
);
\cr_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_7\,
O => \cr_int[3]_i_47_n_0\
);
\cr_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_27_n_7\,
O => \cr_int[3]_i_48_n_0\
);
\cr_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_4\,
O => \cr_int[3]_i_49_n_0\
);
\cr_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
I3 => \cr_int[3]_i_2_n_0\,
O => \cr_int[3]_i_5_n_0\
);
\cr_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_5\,
O => \cr_int[3]_i_50_n_0\
);
\cr_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_54_n_6\,
O => \cr_int[3]_i_51_n_0\
);
\cr_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \cr_int[3]_i_52_n_0\
);
\cr_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(22),
O => \cr_int[3]_i_53_n_0\
);
\cr_int[3]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(21),
I1 => rgb888(23),
O => \cr_int[3]_i_55_n_0\
);
\cr_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(20),
I1 => rgb888(22),
O => \cr_int[3]_i_56_n_0\
);
\cr_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(19),
I1 => rgb888(21),
O => \cr_int[3]_i_57_n_0\
);
\cr_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(18),
I1 => rgb888(20),
O => \cr_int[3]_i_58_n_0\
);
\cr_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(2),
I1 => \cr_int[3]_i_10_n_0\,
I2 => \cr_int[3]_i_11_n_0\,
I3 => \cr_int[3]_i_3_n_0\,
O => \cr_int[3]_i_6_n_0\
);
\cr_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_6\,
O => \cr_int[3]_i_60_n_0\
);
\cr_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_14_n_7\,
O => \cr_int[3]_i_61_n_0\
);
\cr_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_4\,
O => \cr_int[3]_i_62_n_0\
);
\cr_int[3]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_5\,
O => \cr_int[3]_i_63_n_0\
);
\cr_int[3]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_70_n_5\,
I2 => \cr_int_reg[3]_i_64_n_6\,
O => \cr_int[3]_i_66_n_0\
);
\cr_int[3]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_64_n_7\,
I1 => \cr_int_reg[3]_i_70_n_6\,
O => \cr_int[3]_i_67_n_0\
);
\cr_int[3]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_4\,
I1 => \cr_int_reg[3]_i_70_n_7\,
O => \cr_int[3]_i_68_n_0\
);
\cr_int[3]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_5\,
I1 => rgb888(8),
O => \cr_int[3]_i_69_n_0\
);
\cr_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(1),
I1 => \cr_int[3]_i_13_n_0\,
I2 => \cr_int[3]_i_14_n_0\,
I3 => \cr_int[3]_i_4_n_0\,
O => \cr_int[3]_i_7_n_0\
);
\cr_int[3]_i_71\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_94_n_7\,
O => \cr_int[3]_i_71_n_0\
);
\cr_int[3]_i_72\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_5\,
O => \cr_int[3]_i_72_n_0\
);
\cr_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_33_n_6\,
O => \cr_int[3]_i_73_n_0\
);
\cr_int[3]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => \cr_int_reg[3]_i_65_n_5\,
O => \cr_int[3]_i_74_n_0\
);
\cr_int[3]_i_75\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[3]_i_65_n_6\,
O => \cr_int[3]_i_75_n_0\
);
\cr_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(17),
I1 => rgb888(19),
O => \cr_int[3]_i_76_n_0\
);
\cr_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(16),
I1 => rgb888(18),
O => \cr_int[3]_i_77_n_0\
);
\cr_int[3]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \cr_int[3]_i_78_n_0\
);
\cr_int[3]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(16),
O => \cr_int[3]_i_79_n_0\
);
\cr_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"1DE2E21D"
)
port map (
I0 => cr_int_reg6(8),
I1 => cr_int_reg7,
I2 => \cr_int_reg[3]_i_16_n_5\,
I3 => \cr_int[3]_i_17_n_0\,
I4 => \cr_int[3]_i_18_n_0\,
O => \cr_int[3]_i_8_n_0\
);
\cr_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(0),
O => \cr_int[3]_i_80_n_0\
);
\cr_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_6\,
O => \cr_int[3]_i_81_n_0\
);
\cr_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_39_n_7\,
O => \cr_int[3]_i_82_n_0\
);
\cr_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_6\,
O => \cr_int[3]_i_83_n_0\
);
\cr_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cr_int_reg[31]_i_86_n_7\,
O => \cr_int[3]_i_84_n_0\
);
\cr_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \cr_int[3]_i_85_n_0\
);
\cr_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \cr_int[3]_i_86_n_0\
);
\cr_int[3]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \cr_int[3]_i_87_n_0\
);
\cr_int[3]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \cr_int[3]_i_88_n_0\
);
\cr_int[3]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \cr_int[3]_i_89_n_0\
);
\cr_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(2),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(10),
O => \cr_int_reg3__0\(2)
);
\cr_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \cr_int[3]_i_90_n_0\
);
\cr_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_91_n_0\
);
\cr_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \cr_int[3]_i_92_n_0\
);
\cr_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
O => \cr_int[3]_i_93_n_0\
);
\cr_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
O => \cr_int[3]_i_94_n_0\
);
\cr_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(10),
I1 => rgb888(8),
O => \cr_int[3]_i_95_n_0\
);
\cr_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(9),
O => \cr_int[3]_i_96_n_0\
);
\cr_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(5),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_4\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(13),
O => \cr_int_reg3__0\(5)
);
\cr_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(0),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(3),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_11_n_0\
);
\cr_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_7\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_18_n_7\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_5\,
O => \cr_int[7]_i_12_n_0\
);
\cr_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(4),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_5\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(12),
O => \cr_int_reg3__0\(4)
);
\cr_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(3),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(2),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_14_n_0\
);
\cr_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_4\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_4\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_6\,
O => \cr_int[7]_i_15_n_0\
);
\cr_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(3),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_30_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(11),
O => \cr_int_reg3__0\(3)
);
\cr_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_12\(2),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[7]_1\(1),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_17_n_0\
);
\cr_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \cr_int_reg[11]_i_31_n_5\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_41_n_5\,
I3 => \cr_int_reg[11]_i_17_n_0\,
I4 => \cr_int_reg[31]_i_7_n_7\,
O => \cr_int[7]_i_18_n_0\
);
\cr_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(7),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_6\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(15),
O => cr_int_reg3(7)
);
\cr_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"555556A6AAAA56A6"
)
port map (
I0 => \cr_int[11]_i_22_n_0\,
I1 => cr_int_reg6(15),
I2 => cr_int_reg7,
I3 => \cr_int_reg[31]_i_11_n_6\,
I4 => \cr_int_reg[31]_i_11_n_4\,
I5 => cr_int_reg4(7),
O => \cr_int[7]_i_2_n_0\
);
\cr_int[7]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"7477"
)
port map (
I0 => \cr_int_reg[11]_i_16_n_6\,
I1 => \^cr_int_reg[27]_2\(0),
I2 => \cr_int_reg[11]_i_17_n_0\,
I3 => \cr_int_reg[11]_i_18_n_6\,
O => \cr_int[7]_i_20_n_0\
);
\cr_int[7]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"44477747"
)
port map (
I0 => \rgb888[8]_13\(1),
I1 => \^cr_int_reg[31]_2\(1),
I2 => \^cr_int_reg[11]_0\(0),
I3 => \^cr_int_reg[3]_1\(0),
I4 => \^cr_int_reg[7]_0\(3),
O => \cr_int[7]_i_21_n_0\
);
\cr_int[7]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => cr_int_reg4(6),
I1 => \cr_int_reg[31]_i_11_n_4\,
I2 => \cr_int_reg[31]_i_11_n_7\,
I3 => cr_int_reg7,
I4 => cr_int_reg6(14),
O => \cr_int_reg3__0\(6)
);
\cr_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(2),
O => \cr_int[7]_i_25_n_0\
);
\cr_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(1),
O => \cr_int[7]_i_26_n_0\
);
\cr_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[7]_0\(0),
O => \cr_int[7]_i_27_n_0\
);
\cr_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cr_int_reg[3]_0\(2),
O => \cr_int[7]_i_28_n_0\
);
\cr_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
O => \cr_int[7]_i_3_n_0\
);
\cr_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
O => \cr_int[7]_i_4_n_0\
);
\cr_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cr_int_reg3__0\(3),
I1 => \cr_int[7]_i_17_n_0\,
I2 => \cr_int[7]_i_18_n_0\,
O => \cr_int[7]_i_5_n_0\
);
\cr_int[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => cr_int_reg3(7),
I1 => \cr_int[11]_i_22_n_0\,
I2 => \cr_int[7]_i_20_n_0\,
I3 => \cr_int[7]_i_21_n_0\,
I4 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_6_n_0\
);
\cr_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int[7]_i_3_n_0\,
I1 => \cr_int[7]_i_20_n_0\,
I2 => \cr_int[7]_i_21_n_0\,
I3 => \cr_int_reg3__0\(6),
O => \cr_int[7]_i_7_n_0\
);
\cr_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(5),
I1 => \cr_int[7]_i_11_n_0\,
I2 => \cr_int[7]_i_12_n_0\,
I3 => \cr_int[7]_i_4_n_0\,
O => \cr_int[7]_i_8_n_0\
);
\cr_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \cr_int_reg3__0\(4),
I1 => \cr_int[7]_i_14_n_0\,
I2 => \cr_int[7]_i_15_n_0\,
I3 => \cr_int[7]_i_5_n_0\,
O => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_7\,
Q => \cr_int_reg_n_0_[0]\,
R => '0'
);
\cr_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_5\,
Q => \cr_int_reg__0\(10),
R => '0'
);
\cr_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_4\,
Q => \cr_int_reg__0\(11),
R => '0'
);
\cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_1_n_0\,
CO(3) => \cr_int_reg[11]_i_1_n_0\,
CO(2) => \cr_int_reg[11]_i_1_n_1\,
CO(1) => \cr_int_reg[11]_i_1_n_2\,
CO(0) => \cr_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_2_n_0\,
DI(2) => \cr_int[11]_i_3_n_0\,
DI(1) => \cr_int[11]_i_4_n_0\,
DI(0) => \cr_int[11]_i_5_n_0\,
O(3) => \cr_int_reg[11]_i_1_n_4\,
O(2) => \cr_int_reg[11]_i_1_n_5\,
O(1) => \cr_int_reg[11]_i_1_n_6\,
O(0) => \cr_int_reg[11]_i_1_n_7\,
S(3) => \cr_int[11]_i_6_n_0\,
S(2) => \cr_int[11]_i_7_n_0\,
S(1) => \cr_int[11]_i_8_n_0\,
S(0) => \cr_int[11]_i_9_n_0\
);
\cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_125_n_0\,
CO(3) => \cr_int_reg[11]_i_103_n_0\,
CO(2) => \cr_int_reg[11]_i_103_n_1\,
CO(1) => \cr_int_reg[11]_i_103_n_2\,
CO(0) => \cr_int_reg[11]_i_103_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_126_n_0\,
DI(2) => \cr_int[11]_i_127_n_0\,
DI(1) => \cr_int[11]_i_128_n_0\,
DI(0) => \cr_int[11]_i_129_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_130_n_0\,
S(2) => \cr_int[11]_i_131_n_0\,
S(1) => \cr_int[11]_i_132_n_0\,
S(0) => \cr_int[11]_i_133_n_0\
);
\cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_108_n_0\,
CO(2) => \cr_int_reg[11]_i_108_n_1\,
CO(1) => \cr_int_reg[11]_i_108_n_2\,
CO(0) => \cr_int_reg[11]_i_108_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_134_n_0\,
DI(2) => \cr_int[11]_i_135_n_0\,
DI(1) => \cr_int[11]_i_136_n_0\,
DI(0) => \cr_int[11]_i_137_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_138_n_0\,
S(2) => \cr_int[11]_i_139_n_0\,
S(1) => \cr_int[11]_i_140_n_0\,
S(0) => \cr_int[11]_i_141_n_0\
);
\cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_116_n_0\,
CO(2) => \cr_int_reg[11]_i_116_n_1\,
CO(1) => \cr_int_reg[11]_i_116_n_2\,
CO(0) => \cr_int_reg[11]_i_116_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_142_n_0\,
DI(2) => \cr_int[11]_i_143_n_0\,
DI(1) => \cr_int[11]_i_144_n_0\,
DI(0) => \cr_int[11]_i_145_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_146_n_0\,
S(2) => \cr_int[11]_i_147_n_0\,
S(1) => \cr_int[11]_i_148_n_0\,
S(0) => \cr_int[11]_i_149_n_0\
);
\cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_125_n_0\,
CO(2) => \cr_int_reg[11]_i_125_n_1\,
CO(1) => \cr_int_reg[11]_i_125_n_2\,
CO(0) => \cr_int_reg[11]_i_125_n_3\,
CYINIT => '1',
DI(3) => \cr_int[11]_i_150_n_0\,
DI(2) => \cr_int[11]_i_151_n_0\,
DI(1) => \cr_int[11]_i_152_n_0\,
DI(0) => \cb_int_reg[3]_i_94_n_7\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_153_n_0\,
S(2) => \cr_int[11]_i_154_n_0\,
S(1) => \cr_int[11]_i_155_n_0\,
S(0) => \cr_int[11]_i_156_n_0\
);
\cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_31_n_0\,
CO(3) => \cr_int_reg[11]_i_16_n_0\,
CO(2) => \cr_int_reg[11]_i_16_n_1\,
CO(1) => \cr_int_reg[11]_i_16_n_2\,
CO(0) => \cr_int_reg[11]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_16_n_4\,
O(2) => \cr_int_reg[11]_i_16_n_5\,
O(1) => \cr_int_reg[11]_i_16_n_6\,
O(0) => \cr_int_reg[11]_i_16_n_7\,
S(3) => \cr_int[11]_i_32_n_0\,
S(2) => \cr_int[11]_i_33_n_0\,
S(1) => \cr_int[11]_i_34_n_0\,
S(0) => \cr_int[11]_i_35_n_0\
);
\cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_36_n_0\,
CO(3) => \cr_int_reg[11]_i_17_n_0\,
CO(2) => \cr_int_reg[11]_i_17_n_1\,
CO(1) => \cr_int_reg[11]_i_17_n_2\,
CO(0) => \cr_int_reg[11]_i_17_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_37_n_0\,
S(2) => \cr_int[11]_i_38_n_0\,
S(1) => \cr_int[11]_i_39_n_0\,
S(0) => \cr_int[11]_i_40_n_0\
);
\cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_41_n_0\,
CO(3) => \cr_int_reg[15]_1\(0),
CO(2) => \cr_int_reg[11]_i_18_n_1\,
CO(1) => \cr_int_reg[11]_i_18_n_2\,
CO(0) => \cr_int_reg[11]_i_18_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_18_n_4\,
O(2) => \cr_int_reg[11]_i_18_n_5\,
O(1) => \cr_int_reg[11]_i_18_n_6\,
O(0) => \cr_int_reg[11]_i_18_n_7\,
S(3) => \cr_int[11]_i_42_n_0\,
S(2) => \cr_int[11]_i_43_n_0\,
S(1) => \cr_int[11]_i_44_n_0\,
S(0) => \cr_int[11]_i_45_n_0\
);
\cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_46_n_0\,
CO(3) => \cr_int_reg[11]_i_19_n_0\,
CO(2) => \cr_int_reg[11]_i_19_n_1\,
CO(1) => \cr_int_reg[11]_i_19_n_2\,
CO(0) => \cr_int_reg[11]_i_19_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(16 downto 13),
S(3) => \cr_int[11]_i_47_n_0\,
S(2) => \cr_int[11]_i_48_n_0\,
S(1) => \cr_int[11]_i_49_n_0\,
S(0) => \cr_int[11]_i_50_n_0\
);
\cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_51_n_0\,
CO(3) => cr_int_reg7,
CO(2) => \cr_int_reg[11]_i_20_n_1\,
CO(1) => \cr_int_reg[11]_i_20_n_2\,
CO(0) => \cr_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int_reg[31]_i_11_n_4\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_52_n_0\,
S(2) => \cr_int[11]_i_53_n_0\,
S(1) => \cr_int[11]_i_54_n_0\,
S(0) => \cr_int[11]_i_55_n_0\
);
\cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_56_n_0\,
CO(3) => \cr_int_reg[11]_i_21_n_0\,
CO(2) => \cr_int_reg[11]_i_21_n_1\,
CO(1) => \cr_int_reg[11]_i_21_n_2\,
CO(0) => \cr_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(8 downto 5),
S(3) => \cr_int[11]_i_57_n_0\,
S(2) => \cr_int[11]_i_58_n_0\,
S(1) => \cr_int[11]_i_59_n_0\,
S(0) => \cr_int[11]_i_60_n_0\
);
\cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_23_n_0\,
CO(3) => \cr_int_reg[11]_i_29_n_0\,
CO(2) => \cr_int_reg[11]_i_29_n_1\,
CO(1) => \cr_int_reg[11]_i_29_n_2\,
CO(0) => \cr_int_reg[11]_i_29_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0),
S(3) => \cr_int[11]_i_65_n_0\,
S(2) => \cr_int[11]_i_66_n_0\,
S(1) => \cr_int[11]_i_67_n_0\,
S(0) => \cr_int[11]_i_68_n_0\
);
\cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_69_n_0\,
CO(3) => \^cr_int_reg[3]_1\(0),
CO(2) => \cr_int_reg[11]_i_30_n_1\,
CO(1) => \cr_int_reg[11]_i_30_n_2\,
CO(0) => \cr_int_reg[11]_i_30_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_70_n_0\,
S(2) => \cr_int[11]_i_71_n_0\,
S(1) => \cr_int[11]_i_72_n_0\,
S(0) => \cr_int[11]_i_73_n_0\
);
\cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_31_n_0\,
CO(2) => \cr_int_reg[11]_i_31_n_1\,
CO(1) => \cr_int_reg[11]_i_31_n_2\,
CO(0) => \cr_int_reg[11]_i_31_n_3\,
CYINIT => \cr_int[11]_i_74_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_31_n_4\,
O(2) => \cr_int_reg[11]_i_31_n_5\,
O(1) => \cr_int_reg[11]_i_31_n_6\,
O(0) => \cr_int_reg[11]_i_31_n_7\,
S(3) => \cr_int[11]_i_75_n_0\,
S(2) => \cr_int[11]_i_76_n_0\,
S(1) => \cr_int[11]_i_77_n_0\,
S(0) => \cr_int[11]_i_78_n_0\
);
\cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_79_n_0\,
CO(3) => \cr_int_reg[11]_i_36_n_0\,
CO(2) => \cr_int_reg[11]_i_36_n_1\,
CO(1) => \cr_int_reg[11]_i_36_n_2\,
CO(0) => \cr_int_reg[11]_i_36_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \^cr_int_reg[27]_2\(0),
DI(1) => \^cr_int_reg[27]_2\(0),
DI(0) => \^cr_int_reg[27]_2\(0),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_80_n_0\,
S(2) => \cr_int[11]_i_81_n_0\,
S(1) => \cr_int[11]_i_82_n_0\,
S(0) => \cr_int[11]_i_83_n_0\
);
\cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_32_n_0\,
CO(3) => \cr_int_reg[11]_i_41_n_0\,
CO(2) => \cr_int_reg[11]_i_41_n_1\,
CO(1) => \cr_int_reg[11]_i_41_n_2\,
CO(0) => \cr_int_reg[11]_i_41_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_41_n_4\,
O(2) => \cr_int_reg[11]_i_41_n_5\,
O(1) => \cr_int_reg[11]_i_41_n_6\,
O(0) => \cr_int_reg[11]_i_41_n_7\,
S(3) => \cr_int[11]_i_84_n_0\,
S(2) => \cr_int[11]_i_85_n_0\,
S(1) => \cr_int[11]_i_86_n_0\,
S(0) => \cr_int[11]_i_87_n_0\
);
\cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_15_n_0\,
CO(3) => \cr_int_reg[11]_i_46_n_0\,
CO(2) => \cr_int_reg[11]_i_46_n_1\,
CO(1) => \cr_int_reg[11]_i_46_n_2\,
CO(0) => \cr_int_reg[11]_i_46_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(12 downto 9),
S(3) => \cr_int[11]_i_88_n_0\,
S(2) => \cr_int[11]_i_89_n_0\,
S(1) => \cr_int[11]_i_90_n_0\,
S(0) => \cr_int[11]_i_91_n_0\
);
\cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_92_n_0\,
CO(3) => \cr_int_reg[11]_i_51_n_0\,
CO(2) => \cr_int_reg[11]_i_51_n_1\,
CO(1) => \cr_int_reg[11]_i_51_n_2\,
CO(0) => \cr_int_reg[11]_i_51_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[31]_i_11_n_4\,
DI(2) => \cr_int_reg[31]_i_11_n_4\,
DI(1) => \cr_int_reg[31]_i_11_n_4\,
DI(0) => \cr_int[11]_i_93_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_94_n_0\,
S(2) => \cr_int[11]_i_95_n_0\,
S(1) => \cr_int[11]_i_96_n_0\,
S(0) => \cr_int[11]_i_97_n_0\
);
\cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[11]_i_56_n_0\,
CO(2) => \cr_int_reg[11]_i_56_n_1\,
CO(1) => \cr_int_reg[11]_i_56_n_2\,
CO(0) => \cr_int_reg[11]_i_56_n_3\,
CYINIT => \cr_int[11]_i_98_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(4 downto 1),
S(3) => \cr_int[11]_i_99_n_0\,
S(2) => \cr_int[11]_i_100_n_0\,
S(1) => \cr_int[11]_i_101_n_0\,
S(0) => \cr_int[11]_i_102_n_0\
);
\cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_103_n_0\,
CO(3) => \cr_int_reg[11]_i_69_n_0\,
CO(2) => \cr_int_reg[11]_i_69_n_1\,
CO(1) => \cr_int_reg[11]_i_69_n_2\,
CO(0) => \cr_int_reg[11]_i_69_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[31]_2\(1),
DI(2) => \^cr_int_reg[31]_2\(1),
DI(1) => \^cr_int_reg[31]_2\(1),
DI(0) => \^cr_int_reg[31]_2\(1),
O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_104_n_0\,
S(2) => \cr_int[11]_i_105_n_0\,
S(1) => \cr_int[11]_i_106_n_0\,
S(0) => \cr_int[11]_i_107_n_0\
);
\cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_108_n_0\,
CO(3) => \cr_int_reg[11]_i_79_n_0\,
CO(2) => \cr_int_reg[11]_i_79_n_1\,
CO(1) => \cr_int_reg[11]_i_79_n_2\,
CO(0) => \cr_int_reg[11]_i_79_n_3\,
CYINIT => '0',
DI(3) => \^cr_int_reg[27]_2\(0),
DI(2) => \cr_int[11]_i_109_n_0\,
DI(1) => \cr_int[11]_i_110_n_0\,
DI(0) => \cr_int[11]_i_111_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_112_n_0\,
S(2) => \cr_int[11]_i_113_n_0\,
S(1) => \cr_int[11]_i_114_n_0\,
S(0) => \cr_int[11]_i_115_n_0\
);
\cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_116_n_0\,
CO(3) => \cr_int_reg[11]_i_92_n_0\,
CO(2) => \cr_int_reg[11]_i_92_n_1\,
CO(1) => \cr_int_reg[11]_i_92_n_2\,
CO(0) => \cr_int_reg[11]_i_92_n_3\,
CYINIT => '0',
DI(3) => \cr_int[11]_i_117_n_0\,
DI(2) => \cr_int[11]_i_118_n_0\,
DI(1) => \cr_int[11]_i_119_n_0\,
DI(0) => \cr_int[11]_i_120_n_0\,
O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[11]_i_121_n_0\,
S(2) => \cr_int[11]_i_122_n_0\,
S(1) => \cr_int[11]_i_123_n_0\,
S(0) => \cr_int[11]_i_124_n_0\
);
\cr_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_7\,
Q => \cr_int_reg__0\(12),
R => '0'
);
\cr_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_6\,
Q => \cr_int_reg__0\(13),
R => '0'
);
\cr_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_5\,
Q => \cr_int_reg__0\(14),
R => '0'
);
\cr_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[15]_i_1_n_4\,
Q => \cr_int_reg__0\(15),
R => '0'
);
\cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_1_n_0\,
CO(3) => \cr_int_reg[15]_i_1_n_0\,
CO(2) => \cr_int_reg[15]_i_1_n_1\,
CO(1) => \cr_int_reg[15]_i_1_n_2\,
CO(0) => \cr_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[15]_i_2_n_0\,
DI(2) => \cr_int[15]_i_3_n_0\,
DI(1) => \cr_int[15]_i_4_n_0\,
DI(0) => \cr_int[15]_i_5_n_0\,
O(3) => \cr_int_reg[15]_i_1_n_4\,
O(2) => \cr_int_reg[15]_i_1_n_5\,
O(1) => \cr_int_reg[15]_i_1_n_6\,
O(0) => \cr_int_reg[15]_i_1_n_7\,
S(3) => \cr_int[15]_i_6_n_0\,
S(2) => \cr_int[15]_i_7_n_0\,
S(1) => \cr_int[15]_i_8_n_0\,
S(0) => \cr_int[15]_i_9_n_0\
);
\cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_19_n_0\,
CO(3) => \cr_int_reg[15]_i_20_n_0\,
CO(2) => \cr_int_reg[15]_i_20_n_1\,
CO(1) => \cr_int_reg[15]_i_20_n_2\,
CO(0) => \cr_int_reg[15]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(20 downto 17),
S(3) => \cr_int[15]_i_29_n_0\,
S(2) => \cr_int[15]_i_30_n_0\,
S(1) => \cr_int[15]_i_31_n_0\,
S(0) => \cr_int[15]_i_32_n_0\
);
\cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_21_n_0\,
CO(3) => \cr_int_reg[15]_i_21_n_0\,
CO(2) => \cr_int_reg[15]_i_21_n_1\,
CO(1) => \cr_int_reg[15]_i_21_n_2\,
CO(0) => \cr_int_reg[15]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(12 downto 9),
S(3) => \cr_int[15]_i_33_n_0\,
S(2) => \cr_int[15]_i_34_n_0\,
S(1) => \cr_int[15]_i_35_n_0\,
S(0) => \cr_int[15]_i_36_n_0\
);
\cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_29_n_0\,
CO(3) => \cr_int_reg[15]_i_28_n_0\,
CO(2) => \cr_int_reg[15]_i_28_n_1\,
CO(1) => \cr_int_reg[15]_i_28_n_2\,
CO(0) => \cr_int_reg[15]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0),
S(3) => \cr_int[15]_i_40_n_0\,
S(2) => \cr_int[15]_i_41_n_0\,
S(1) => \cr_int[15]_i_42_n_0\,
S(0) => \cr_int[15]_i_43_n_0\
);
\cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_16_n_0\,
CO(3) => \cr_int_reg[15]_i_38_n_0\,
CO(2) => \cr_int_reg[15]_i_38_n_1\,
CO(1) => \cr_int_reg[15]_i_38_n_2\,
CO(0) => \cr_int_reg[15]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_38_n_4\,
O(2) => \cr_int_reg[15]_i_38_n_5\,
O(1) => \cr_int_reg[15]_i_38_n_6\,
O(0) => \cr_int_reg[15]_i_38_n_7\,
S(3) => \cr_int[15]_i_48_n_0\,
S(2) => \cr_int[15]_i_49_n_0\,
S(1) => \cr_int[15]_i_50_n_0\,
S(0) => \cr_int[15]_i_51_n_0\
);
\cr_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_7\,
Q => \cr_int_reg__0\(16),
R => '0'
);
\cr_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_6\,
Q => \cr_int_reg__0\(17),
R => '0'
);
\cr_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_5\,
Q => \cr_int_reg__0\(18),
R => '0'
);
\cr_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[19]_i_1_n_4\,
Q => \cr_int_reg__0\(19),
R => '0'
);
\cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_1_n_0\,
CO(3) => \cr_int_reg[19]_i_1_n_0\,
CO(2) => \cr_int_reg[19]_i_1_n_1\,
CO(1) => \cr_int_reg[19]_i_1_n_2\,
CO(0) => \cr_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[19]_i_2_n_0\,
DI(2) => \cr_int[19]_i_3_n_0\,
DI(1) => \cr_int[19]_i_4_n_0\,
DI(0) => \cr_int[19]_i_5_n_0\,
O(3) => \cr_int_reg[19]_i_1_n_4\,
O(2) => \cr_int_reg[19]_i_1_n_5\,
O(1) => \cr_int_reg[19]_i_1_n_6\,
O(0) => \cr_int_reg[19]_i_1_n_7\,
S(3) => \cr_int[19]_i_6_n_0\,
S(2) => \cr_int[19]_i_7_n_0\,
S(1) => \cr_int[19]_i_8_n_0\,
S(0) => \cr_int[19]_i_9_n_0\
);
\cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_20_n_0\,
CO(3) => \cr_int_reg[19]_i_20_n_0\,
CO(2) => \cr_int_reg[19]_i_20_n_1\,
CO(1) => \cr_int_reg[19]_i_20_n_2\,
CO(0) => \cr_int_reg[19]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(24 downto 21),
S(3) => \cr_int[19]_i_29_n_0\,
S(2) => \cr_int[19]_i_30_n_0\,
S(1) => \cr_int[19]_i_31_n_0\,
S(0) => \cr_int[19]_i_32_n_0\
);
\cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_21_n_0\,
CO(3) => \cr_int_reg[19]_i_21_n_0\,
CO(2) => \cr_int_reg[19]_i_21_n_1\,
CO(1) => \cr_int_reg[19]_i_21_n_2\,
CO(0) => \cr_int_reg[19]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(16 downto 13),
S(3) => \cr_int[19]_i_33_n_0\,
S(2) => \cr_int[19]_i_34_n_0\,
S(1) => \cr_int[19]_i_35_n_0\,
S(0) => \cr_int[19]_i_36_n_0\
);
\cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_28_n_0\,
CO(3) => \cr_int_reg[19]_i_28_n_0\,
CO(2) => \cr_int_reg[19]_i_28_n_1\,
CO(1) => \cr_int_reg[19]_i_28_n_2\,
CO(0) => \cr_int_reg[19]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0),
S(3) => \cr_int[19]_i_38_n_0\,
S(2) => \cr_int[19]_i_39_n_0\,
S(1) => \cr_int[19]_i_40_n_0\,
S(0) => \cr_int[19]_i_41_n_0\
);
\cr_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_6\,
Q => \cr_int_reg_n_0_[1]\,
R => '0'
);
\cr_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_7\,
Q => \cr_int_reg__0\(20),
R => '0'
);
\cr_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_6\,
Q => \cr_int_reg__0\(21),
R => '0'
);
\cr_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_5\,
Q => \cr_int_reg__0\(22),
R => '0'
);
\cr_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[23]_i_1_n_4\,
Q => \cr_int_reg__0\(23),
R => '0'
);
\cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_1_n_0\,
CO(3) => \cr_int_reg[23]_i_1_n_0\,
CO(2) => \cr_int_reg[23]_i_1_n_1\,
CO(1) => \cr_int_reg[23]_i_1_n_2\,
CO(0) => \cr_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[23]_i_2_n_0\,
DI(2) => \cr_int[23]_i_3_n_0\,
DI(1) => \cr_int[23]_i_4_n_0\,
DI(0) => \cr_int[23]_i_5_n_0\,
O(3) => \cr_int_reg[23]_i_1_n_4\,
O(2) => \cr_int_reg[23]_i_1_n_5\,
O(1) => \cr_int_reg[23]_i_1_n_6\,
O(0) => \cr_int_reg[23]_i_1_n_7\,
S(3) => \cr_int[23]_i_6_n_0\,
S(2) => \cr_int[23]_i_7_n_0\,
S(1) => \cr_int[23]_i_8_n_0\,
S(0) => \cr_int[23]_i_9_n_0\
);
\cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_20_n_0\,
CO(3) => \cr_int_reg[23]_i_20_n_0\,
CO(2) => \cr_int_reg[23]_i_20_n_1\,
CO(1) => \cr_int_reg[23]_i_20_n_2\,
CO(0) => \cr_int_reg[23]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg6(28 downto 25),
S(3) => \cr_int[23]_i_27_n_0\,
S(2) => \cr_int[23]_i_28_n_0\,
S(1) => \cr_int[23]_i_29_n_0\,
S(0) => \cr_int[23]_i_30_n_0\
);
\cr_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_7\,
Q => \cr_int_reg__0\(24),
R => '0'
);
\cr_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_6\,
Q => \cr_int_reg__0\(25),
R => '0'
);
\cr_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_5\,
Q => \cr_int_reg__0\(26),
R => '0'
);
\cr_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[27]_i_1_n_4\,
Q => \cr_int_reg__0\(27),
R => '0'
);
\cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_1_n_0\,
CO(3) => \cr_int_reg[27]_i_1_n_0\,
CO(2) => \cr_int_reg[27]_i_1_n_1\,
CO(1) => \cr_int_reg[27]_i_1_n_2\,
CO(0) => \cr_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_2_n_0\,
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[27]_i_2_n_0\,
O(3) => \cr_int_reg[27]_i_1_n_4\,
O(2) => \cr_int_reg[27]_i_1_n_5\,
O(1) => \cr_int_reg[27]_i_1_n_6\,
O(0) => \cr_int_reg[27]_i_1_n_7\,
S(3) => \cr_int[27]_i_3_n_0\,
S(2) => \cr_int[27]_i_4_n_0\,
S(1) => \cr_int[27]_i_5_n_0\,
S(0) => \cr_int[27]_i_6_n_0\
);
\cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_20_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[27]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg6(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \cr_int[27]_i_12_n_0\,
S(0) => \cr_int[27]_i_13_n_0\
);
\cr_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_7\,
Q => \cr_int_reg__0\(28),
R => '0'
);
\cr_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_6\,
Q => \cr_int_reg__0\(29),
R => '0'
);
\cr_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_5\,
Q => \cr_int_reg_n_0_[2]\,
R => '0'
);
\cr_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_5\,
Q => \cr_int_reg__0\(30),
R => '0'
);
\cr_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[31]_i_1_n_4\,
Q => \cr_int_reg__0\(31),
R => '0'
);
\cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_1_n_1\,
CO(1) => \cr_int_reg[31]_i_1_n_2\,
CO(0) => \cr_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \cr_int[31]_i_2_n_0\,
DI(1) => \cr_int[31]_i_2_n_0\,
DI(0) => \cr_int[31]_i_2_n_0\,
O(3) => \cr_int_reg[31]_i_1_n_4\,
O(2) => \cr_int_reg[31]_i_1_n_5\,
O(1) => \cr_int_reg[31]_i_1_n_6\,
O(0) => \cr_int_reg[31]_i_1_n_7\,
S(3) => \cr_int[31]_i_3_n_0\,
S(2) => \cr_int[31]_i_4_n_0\,
S(1) => \cr_int[31]_i_5_n_0\,
S(0) => \cr_int[31]_i_6_n_0\
);
\cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_64_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_101_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_101_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_101_n_6\,
O(0) => \cr_int_reg[31]_i_101_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_121_n_0\,
S(0) => \cr_int[31]_i_122_n_0\
);
\cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_70_n_0\,
CO(3) => \cr_int_reg[31]_i_102_n_0\,
CO(2) => \cr_int_reg[31]_i_102_n_1\,
CO(1) => \cr_int_reg[31]_i_102_n_2\,
CO(0) => \cr_int_reg[31]_i_102_n_3\,
CYINIT => '0',
DI(3) => rgb888(14),
DI(2 downto 0) => rgb888(15 downto 13),
O(3) => \cr_int_reg[31]_i_102_n_4\,
O(2) => \cr_int_reg[31]_i_102_n_5\,
O(1) => \cr_int_reg[31]_i_102_n_6\,
O(0) => \cr_int_reg[31]_i_102_n_7\,
S(3) => \cr_int[31]_i_123_n_0\,
S(2) => \cr_int[31]_i_124_n_0\,
S(1) => \cr_int[31]_i_125_n_0\,
S(0) => \cr_int[31]_i_126_n_0\
);
\cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_11_n_1\,
CO(1) => \cr_int_reg[31]_i_11_n_2\,
CO(0) => \cr_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cr_int[31]_i_31_n_0\,
O(3) => \cr_int_reg[31]_i_11_n_4\,
O(2) => \cr_int_reg[31]_i_11_n_5\,
O(1) => \cr_int_reg[31]_i_11_n_6\,
O(0) => \cr_int_reg[31]_i_11_n_7\,
S(3) => \cr_int[31]_i_32_n_0\,
S(2) => \cr_int[31]_i_33_n_0\,
S(1) => \cr_int[31]_i_34_n_0\,
S(0) => \cr_int[31]_i_35_n_0\
);
\cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_36_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => cr_int_reg4(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_37_n_0\,
S(0) => \cr_int[31]_i_38_n_0\
);
\cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_39_n_0\,
CO(3) => \cr_int_reg[31]_i_14_n_0\,
CO(2) => \cr_int_reg[31]_i_14_n_1\,
CO(1) => \cr_int_reg[31]_i_14_n_2\,
CO(0) => \cr_int_reg[31]_i_14_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_40_n_0\,
DI(2) => \cr_int[31]_i_41_n_0\,
DI(1) => \cr_int[31]_i_42_n_0\,
DI(0) => \cr_int[31]_i_43_n_0\,
O(3) => \cr_int_reg[31]_i_14_n_4\,
O(2) => \cr_int_reg[31]_i_14_n_5\,
O(1) => \cr_int_reg[31]_i_14_n_6\,
O(0) => \cr_int_reg[31]_i_14_n_7\,
S(3) => \cr_int[31]_i_44_n_0\,
S(2) => \cr_int[31]_i_45_n_0\,
S(1) => \cr_int[31]_i_46_n_0\,
S(0) => \cr_int[31]_i_47_n_0\
);
\cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_49_n_0\,
CO(3) => \cr_int_reg[31]_i_21_n_0\,
CO(2) => \cr_int_reg[31]_i_21_n_1\,
CO(1) => \cr_int_reg[31]_i_21_n_2\,
CO(0) => \cr_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_21_n_4\,
O(2) => \cr_int_reg[31]_i_21_n_5\,
O(1) => \cr_int_reg[31]_i_21_n_6\,
O(0) => \cr_int_reg[31]_i_21_n_7\,
S(3) => \cr_int[31]_i_50_n_0\,
S(2) => \cr_int[31]_i_51_n_0\,
S(1) => \cr_int[31]_i_52_n_0\,
S(0) => \cr_int[31]_i_53_n_0\
);
\cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_19_n_0\,
CO(3) => \cr_int_reg[31]_i_24_n_0\,
CO(2) => \cr_int_reg[31]_i_24_n_1\,
CO(1) => \cr_int_reg[31]_i_24_n_2\,
CO(0) => \cr_int_reg[31]_i_24_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_55_n_0\,
DI(2) => \cr_int[31]_i_56_n_0\,
DI(1) => \cr_int[31]_i_57_n_0\,
DI(0) => \cr_int[31]_i_58_n_0\,
O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0),
S(3) => \cr_int[31]_i_59_n_0\,
S(2) => \cr_int[31]_i_60_n_0\,
S(1) => \cr_int[31]_i_61_n_0\,
S(0) => \cr_int[31]_i_62_n_0\
);
\cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_16_n_0\,
CO(3) => \cr_int_reg[31]_i_30_n_0\,
CO(2) => \cr_int_reg[31]_i_30_n_1\,
CO(1) => \cr_int_reg[31]_i_30_n_2\,
CO(0) => \cr_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_71_n_0\,
DI(2) => \cr_int[31]_i_72_n_0\,
DI(1) => \cr_int[31]_i_73_n_0\,
DI(0) => \cr_int[31]_i_74_n_0\,
O(3) => \cr_int_reg[31]_i_30_n_4\,
O(2) => \cr_int_reg[31]_i_30_n_5\,
O(1) => \cr_int_reg[31]_i_30_n_6\,
O(0) => \cr_int_reg[31]_i_30_n_7\,
S(3) => \cr_int[31]_i_75_n_0\,
S(2) => \cr_int[31]_i_76_n_0\,
S(1) => \cr_int[31]_i_77_n_0\,
S(0) => \cr_int[31]_i_78_n_0\
);
\cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_21_n_0\,
CO(3) => \cr_int_reg[31]_i_36_n_0\,
CO(2) => \cr_int_reg[31]_i_36_n_1\,
CO(1) => \cr_int_reg[31]_i_36_n_2\,
CO(0) => \cr_int_reg[31]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => cr_int_reg4(20 downto 17),
S(3) => \cr_int[31]_i_81_n_0\,
S(2) => \cr_int[31]_i_82_n_0\,
S(1) => \cr_int[31]_i_83_n_0\,
S(0) => \cr_int[31]_i_84_n_0\
);
\cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_39_n_0\,
CO(2) => \cr_int_reg[31]_i_39_n_1\,
CO(1) => \cr_int_reg[31]_i_39_n_2\,
CO(0) => \cr_int_reg[31]_i_39_n_3\,
CYINIT => '0',
DI(3) => \cr_int[31]_i_85_n_0\,
DI(2) => rgb888(1),
DI(1) => \cr_int_reg[31]_i_86_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_39_n_4\,
O(2) => \cr_int_reg[31]_i_39_n_5\,
O(1) => \cr_int_reg[31]_i_39_n_6\,
O(0) => \cr_int_reg[31]_i_39_n_7\,
S(3) => \cr_int[31]_i_87_n_0\,
S(2) => \cr_int[31]_i_88_n_0\,
S(1) => \cr_int[31]_i_89_n_0\,
S(0) => \cr_int[31]_i_90_n_0\
);
\cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_91_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_48_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_48_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_93_n_0\
);
\cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_38_n_0\,
CO(3) => \cr_int_reg[31]_i_49_n_0\,
CO(2) => \cr_int_reg[31]_i_49_n_1\,
CO(1) => \cr_int_reg[31]_i_49_n_2\,
CO(0) => \cr_int_reg[31]_i_49_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_49_n_4\,
O(2) => \cr_int_reg[31]_i_49_n_5\,
O(1) => \cr_int_reg[31]_i_49_n_6\,
O(0) => \cr_int_reg[31]_i_49_n_7\,
S(3) => \cr_int[31]_i_94_n_0\,
S(2) => \cr_int[31]_i_95_n_0\,
S(1) => \cr_int[31]_i_96_n_0\,
S(0) => \cr_int[31]_i_97_n_0\
);
\cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_102_n_0\,
CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2),
CO(1) => \cr_int_reg[31]_i_63_n_2\,
CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(15),
O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1),
O(0) => \cr_int_reg[31]_i_63_n_7\,
S(3 downto 1) => B"001",
S(0) => \cr_int[31]_i_103_n_0\
);
\cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_70_n_0\,
CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1),
O(0) => \^cr_int_reg[23]_1\(0),
S(3 downto 1) => B"000",
S(0) => \cr_int[31]_i_108_n_0\
);
\cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_14_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_7_n_1\,
CO(1) => \cr_int_reg[31]_i_7_n_2\,
CO(0) => \cr_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \cr_int[31]_i_15_n_0\,
DI(0) => \cr_int[31]_i_16_n_0\,
O(3) => \^cr_int_reg[27]_2\(0),
O(2) => \cr_int_reg[31]_i_7_n_5\,
O(1) => \cr_int_reg[31]_i_7_n_6\,
O(0) => \cr_int_reg[31]_i_7_n_7\,
S(3) => \cr_int[31]_i_17_n_0\,
S(2) => \cr_int[31]_i_18_n_0\,
S(1) => \cr_int[31]_i_19_n_0\,
S(0) => \cr_int[31]_i_20_n_0\
);
\cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_28_n_0\,
CO(3) => \cr_int_reg[31]_i_70_n_0\,
CO(2) => \cr_int_reg[31]_i_70_n_1\,
CO(1) => \cr_int_reg[31]_i_70_n_2\,
CO(0) => \cr_int_reg[31]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0),
S(3) => \cr_int[31]_i_109_n_0\,
S(2) => \cr_int[31]_i_110_n_0\,
S(1) => \cr_int[31]_i_111_n_0\,
S(0) => \cr_int[31]_i_112_n_0\
);
\cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_21_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_8_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_8_n_6\,
O(0) => \cr_int_reg[31]_i_8_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_22_n_0\,
S(0) => \cr_int[31]_i_23_n_0\
);
\cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[31]_i_86_n_0\,
CO(2) => \cr_int_reg[31]_i_86_n_1\,
CO(1) => \cr_int_reg[31]_i_86_n_2\,
CO(0) => \cr_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \cr_int_reg[31]_i_86_n_4\,
O(2) => \cr_int_reg[31]_i_86_n_5\,
O(1) => \cr_int_reg[31]_i_86_n_6\,
O(0) => \cr_int_reg[31]_i_86_n_7\,
S(3) => \cr_int[31]_i_113_n_0\,
S(2) => \cr_int[31]_i_114_n_0\,
S(1) => \cr_int[31]_i_115_n_0\,
S(0) => \cr_int[31]_i_116_n_0\
);
\cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_24_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^di\(0),
O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_25_n_0\,
S(0) => \cr_int[31]_i_26_n_0\
);
\cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_86_n_0\,
CO(3) => \cr_int_reg[31]_i_91_n_0\,
CO(2) => \cr_int_reg[31]_i_91_n_1\,
CO(1) => \cr_int_reg[31]_i_91_n_2\,
CO(0) => \cr_int_reg[31]_i_91_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \cr_int_reg[31]_i_91_n_4\,
O(2) => \cr_int_reg[31]_i_91_n_5\,
O(1) => \cr_int_reg[31]_i_91_n_6\,
O(0) => \cr_int_reg[31]_i_91_n_7\,
S(3) => \cr_int[31]_i_117_n_0\,
S(2) => \cr_int[31]_i_118_n_0\,
S(1) => \cr_int[31]_i_119_n_0\,
S(0) => \cr_int[31]_i_120_n_0\
);
\cr_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[3]_i_1_n_4\,
Q => \cr_int_reg_n_0_[3]\,
R => '0'
);
\cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_1_n_0\,
CO(2) => \cr_int_reg[3]_i_1_n_1\,
CO(1) => \cr_int_reg[3]_i_1_n_2\,
CO(0) => \cr_int_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3) => \cr_int[3]_i_2_n_0\,
DI(2) => \cr_int[3]_i_3_n_0\,
DI(1) => \cr_int[3]_i_4_n_0\,
DI(0) => '1',
O(3) => \cr_int_reg[3]_i_1_n_4\,
O(2) => \cr_int_reg[3]_i_1_n_5\,
O(1) => \cr_int_reg[3]_i_1_n_6\,
O(0) => \cr_int_reg[3]_i_1_n_7\,
S(3) => \cr_int[3]_i_5_n_0\,
S(2) => \cr_int[3]_i_6_n_0\,
S(1) => \cr_int[3]_i_7_n_0\,
S(0) => \cr_int[3]_i_8_n_0\
);
\cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_21_n_0\,
CO(3) => \cr_int_reg[3]_i_15_n_0\,
CO(2) => \cr_int_reg[3]_i_15_n_1\,
CO(1) => \cr_int_reg[3]_i_15_n_2\,
CO(0) => \cr_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => cr_int_reg6(8),
O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_22_n_0\,
S(2) => \cr_int[3]_i_23_n_0\,
S(1) => \cr_int[3]_i_24_n_0\,
S(0) => \cr_int[3]_i_25_n_0\
);
\cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_16_n_0\,
CO(2) => \cr_int_reg[3]_i_16_n_1\,
CO(1) => \cr_int_reg[3]_i_16_n_2\,
CO(0) => \cr_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_26_n_6\,
DI(2) => \cr_int_reg[3]_i_26_n_7\,
DI(1) => \cr_int_reg[3]_i_27_n_4\,
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_16_n_4\,
O(2) => \cr_int_reg[3]_i_16_n_5\,
O(1) => \cr_int_reg[3]_i_16_n_6\,
O(0) => \cr_int_reg[3]_i_16_n_7\,
S(3) => \cr_int[3]_i_28_n_0\,
S(2) => \cr_int[3]_i_29_n_0\,
S(1) => \cr_int[3]_i_30_n_0\,
S(0) => \cr_int[3]_i_31_n_0\
);
\cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_33_n_0\,
CO(3) => \cr_int_reg[3]_i_19_n_0\,
CO(2) => \cr_int_reg[3]_i_19_n_1\,
CO(1) => \cr_int_reg[3]_i_19_n_2\,
CO(0) => \cr_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cr_int[3]_i_34_n_0\,
DI(2) => \cr_int[3]_i_35_n_0\,
DI(1) => \cr_int[3]_i_36_n_0\,
DI(0) => \cr_int[3]_i_37_n_0\,
O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0),
O(0) => \cr_int_reg[3]_i_19_n_7\,
S(3) => \cr_int[3]_i_38_n_0\,
S(2) => \cr_int[3]_i_39_n_0\,
S(1) => \cr_int[3]_i_40_n_0\,
S(0) => \cr_int[3]_i_41_n_0\
);
\cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_42_n_0\,
CO(3) => \cr_int_reg[3]_i_20_n_0\,
CO(2) => \cr_int_reg[3]_i_20_n_1\,
CO(1) => \cr_int_reg[3]_i_20_n_2\,
CO(0) => \cr_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0),
O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \cr_int[3]_i_43_n_0\,
S(2) => \cr_int[3]_i_44_n_0\,
S(1) => \cr_int[3]_i_45_n_0\,
S(0) => \cr_int[3]_i_46_n_0\
);
\cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_21_n_0\,
CO(2) => \cr_int_reg[3]_i_21_n_1\,
CO(1) => \cr_int_reg[3]_i_21_n_2\,
CO(0) => \cr_int_reg[3]_i_21_n_3\,
CYINIT => \cr_int[3]_i_47_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_48_n_0\,
S(2) => \cr_int[3]_i_49_n_0\,
S(1) => \cr_int[3]_i_50_n_0\,
S(0) => \cr_int[3]_i_51_n_0\
);
\cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[3]_i_26_n_1\,
CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(23),
DI(0) => '0',
O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[3]_i_26_n_6\,
O(0) => \cr_int_reg[3]_i_26_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[3]_i_52_n_0\,
S(0) => \cr_int[3]_i_53_n_0\
);
\cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_54_n_0\,
CO(3) => \cr_int_reg[3]_i_27_n_0\,
CO(2) => \cr_int_reg[3]_i_27_n_1\,
CO(1) => \cr_int_reg[3]_i_27_n_2\,
CO(0) => \cr_int_reg[3]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(21 downto 18),
O(3) => \cr_int_reg[3]_i_27_n_4\,
O(2) => \cr_int_reg[3]_i_27_n_5\,
O(1) => \cr_int_reg[3]_i_27_n_6\,
O(0) => \cr_int_reg[3]_i_27_n_7\,
S(3) => \cr_int[3]_i_55_n_0\,
S(2) => \cr_int[3]_i_56_n_0\,
S(1) => \cr_int[3]_i_57_n_0\,
S(0) => \cr_int[3]_i_58_n_0\
);
\cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_59_n_0\,
CO(3) => \cr_int_reg[3]_i_32_n_0\,
CO(2) => \cr_int_reg[3]_i_32_n_1\,
CO(1) => \cr_int_reg[3]_i_32_n_2\,
CO(0) => \cr_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cr_int[3]_i_60_n_0\,
S(2) => \cr_int[3]_i_61_n_0\,
S(1) => \cr_int[3]_i_62_n_0\,
S(0) => \cr_int[3]_i_63_n_0\
);
\cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_33_n_0\,
CO(2) => \cr_int_reg[3]_i_33_n_1\,
CO(1) => \cr_int_reg[3]_i_33_n_2\,
CO(0) => \cr_int_reg[3]_i_33_n_3\,
CYINIT => '0',
DI(3) => \cr_int_reg[3]_i_64_n_6\,
DI(2) => \cr_int_reg[3]_i_64_n_7\,
DI(1) => \cr_int_reg[3]_i_65_n_4\,
DI(0) => \cr_int_reg[3]_i_65_n_5\,
O(3) => \cr_int_reg[3]_i_33_n_4\,
O(2) => \cr_int_reg[3]_i_33_n_5\,
O(1) => \cr_int_reg[3]_i_33_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_66_n_0\,
S(2) => \cr_int[3]_i_67_n_0\,
S(1) => \cr_int[3]_i_68_n_0\,
S(0) => \cr_int[3]_i_69_n_0\
);
\cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_42_n_0\,
CO(2) => \cr_int_reg[3]_i_42_n_1\,
CO(1) => \cr_int_reg[3]_i_42_n_2\,
CO(0) => \cr_int_reg[3]_i_42_n_3\,
CYINIT => \cr_int[3]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_72_n_0\,
S(2) => \cr_int[3]_i_73_n_0\,
S(1) => \cr_int[3]_i_74_n_0\,
S(0) => \cr_int[3]_i_75_n_0\
);
\cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_54_n_0\,
CO(2) => \cr_int_reg[3]_i_54_n_1\,
CO(1) => \cr_int_reg[3]_i_54_n_2\,
CO(0) => \cr_int_reg[3]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(17 downto 16),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_54_n_4\,
O(2) => \cr_int_reg[3]_i_54_n_5\,
O(1) => \cr_int_reg[3]_i_54_n_6\,
O(0) => \cr_int_reg[3]_i_54_n_7\,
S(3) => \cr_int[3]_i_76_n_0\,
S(2) => \cr_int[3]_i_77_n_0\,
S(1) => \cr_int[3]_i_78_n_0\,
S(0) => \cr_int[3]_i_79_n_0\
);
\cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_59_n_0\,
CO(2) => \cr_int_reg[3]_i_59_n_1\,
CO(1) => \cr_int_reg[3]_i_59_n_2\,
CO(0) => \cr_int_reg[3]_i_59_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0),
S(3) => \cr_int[3]_i_81_n_0\,
S(2) => \cr_int[3]_i_82_n_0\,
S(1) => \cr_int[3]_i_83_n_0\,
S(0) => \cr_int[3]_i_84_n_0\
);
\cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_65_n_0\,
CO(3) => \cr_int_reg[3]_i_64_n_0\,
CO(2) => \cr_int_reg[3]_i_64_n_1\,
CO(1) => \cr_int_reg[3]_i_64_n_2\,
CO(0) => \cr_int_reg[3]_i_64_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \cr_int_reg[3]_i_64_n_4\,
O(2) => \cr_int_reg[3]_i_64_n_5\,
O(1) => \cr_int_reg[3]_i_64_n_6\,
O(0) => \cr_int_reg[3]_i_64_n_7\,
S(3) => \cr_int[3]_i_85_n_0\,
S(2) => \cr_int[3]_i_86_n_0\,
S(1) => \cr_int[3]_i_87_n_0\,
S(0) => \cr_int[3]_i_88_n_0\
);
\cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_65_n_0\,
CO(2) => \cr_int_reg[3]_i_65_n_1\,
CO(1) => \cr_int_reg[3]_i_65_n_2\,
CO(0) => \cr_int_reg[3]_i_65_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \cr_int_reg[3]_i_65_n_4\,
O(2) => \cr_int_reg[3]_i_65_n_5\,
O(1) => \cr_int_reg[3]_i_65_n_6\,
O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0),
S(3) => \cr_int[3]_i_89_n_0\,
S(2) => \cr_int[3]_i_90_n_0\,
S(1) => \cr_int[3]_i_91_n_0\,
S(0) => \cr_int[3]_i_92_n_0\
);
\cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[3]_i_70_n_0\,
CO(2) => \cr_int_reg[3]_i_70_n_1\,
CO(1) => \cr_int_reg[3]_i_70_n_2\,
CO(0) => \cr_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(12 downto 10),
DI(0) => '0',
O(3) => \cr_int_reg[3]_i_70_n_4\,
O(2) => \cr_int_reg[3]_i_70_n_5\,
O(1) => \cr_int_reg[3]_i_70_n_6\,
O(0) => \cr_int_reg[3]_i_70_n_7\,
S(3) => \cr_int[3]_i_93_n_0\,
S(2) => \cr_int[3]_i_94_n_0\,
S(1) => \cr_int[3]_i_95_n_0\,
S(0) => \cr_int[3]_i_96_n_0\
);
\cr_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_7\,
Q => \cr_int_reg_n_0_[4]\,
R => '0'
);
\cr_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_6\,
Q => \cr_int_reg_n_0_[5]\,
R => '0'
);
\cr_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_5\,
Q => \cr_int_reg_n_0_[6]\,
R => '0'
);
\cr_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[7]_i_1_n_4\,
Q => \cr_int_reg_n_0_[7]\,
R => '0'
);
\cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_1_n_0\,
CO(3) => \cr_int_reg[7]_i_1_n_0\,
CO(2) => \cr_int_reg[7]_i_1_n_1\,
CO(1) => \cr_int_reg[7]_i_1_n_2\,
CO(0) => \cr_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr_int[7]_i_2_n_0\,
DI(2) => \cr_int[7]_i_3_n_0\,
DI(1) => \cr_int[7]_i_4_n_0\,
DI(0) => \cr_int[7]_i_5_n_0\,
O(3) => \cr_int_reg[7]_i_1_n_4\,
O(2) => \cr_int_reg[7]_i_1_n_5\,
O(1) => \cr_int_reg[7]_i_1_n_6\,
O(0) => \cr_int_reg[7]_i_1_n_7\,
S(3) => \cr_int[7]_i_6_n_0\,
S(2) => \cr_int[7]_i_7_n_0\,
S(1) => \cr_int[7]_i_8_n_0\,
S(0) => \cr_int[7]_i_9_n_0\
);
\cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[3]_i_20_n_0\,
CO(3) => \cr_int_reg[7]_i_23_n_0\,
CO(2) => \cr_int_reg[7]_i_23_n_1\,
CO(1) => \cr_int_reg[7]_i_23_n_2\,
CO(0) => \cr_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0),
S(3) => \cr_int[7]_i_25_n_0\,
S(2) => \cr_int[7]_i_26_n_0\,
S(1) => \cr_int[7]_i_27_n_0\,
S(0) => \cr_int[7]_i_28_n_0\
);
\cr_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_7\,
Q => \cr_int_reg__0\(8),
R => '0'
);
\cr_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \cr_int_reg[11]_i_1_n_6\,
Q => \cr_int_reg__0\(9),
R => '0'
);
\cr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[0]_i_1_n_0\,
Q => cr(0),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[1]_i_1_n_0\,
Q => cr(1),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[2]_i_1_n_0\,
Q => cr(2),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[3]_i_1_n_0\,
Q => cr(3),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[4]_i_1_n_0\,
Q => cr(4),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[5]_i_1_n_0\,
Q => cr(5),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[6]_i_1_n_0\,
Q => cr(6),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \cr[7]_i_2_n_0\,
Q => cr(7),
S => \cr_reg[7]_i_1_n_0\
);
\cr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_3_n_0\,
CO(3) => \cr_reg[7]_i_1_n_0\,
CO(2) => \cr_reg[7]_i_1_n_1\,
CO(1) => \cr_reg[7]_i_1_n_2\,
CO(0) => \cr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_4_n_0\,
DI(2) => \cr[7]_i_5_n_0\,
DI(1) => \cr[7]_i_6_n_0\,
DI(0) => \cr[7]_i_7_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_8_n_0\,
S(2) => \cr[7]_i_9_n_0\,
S(1) => \cr[7]_i_10_n_0\,
S(0) => \cr[7]_i_11_n_0\
);
\cr_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_reg[7]_i_12_n_0\,
CO(2) => \cr_reg[7]_i_12_n_1\,
CO(1) => \cr_reg[7]_i_12_n_2\,
CO(0) => \cr_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_21_n_0\,
DI(2) => \cr[7]_i_22_n_0\,
DI(1) => \cr[7]_i_23_n_0\,
DI(0) => \cr[7]_i_24_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_25_n_0\,
S(2) => \cr[7]_i_26_n_0\,
S(1) => \cr[7]_i_27_n_0\,
S(0) => \cr[7]_i_28_n_0\
);
\cr_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \cr_reg[7]_i_12_n_0\,
CO(3) => \cr_reg[7]_i_3_n_0\,
CO(2) => \cr_reg[7]_i_3_n_1\,
CO(1) => \cr_reg[7]_i_3_n_2\,
CO(0) => \cr_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \cr[7]_i_13_n_0\,
DI(2) => \cr[7]_i_14_n_0\,
DI(1) => \cr[7]_i_15_n_0\,
DI(0) => \cr[7]_i_16_n_0\,
O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \cr[7]_i_17_n_0\,
S(2) => \cr[7]_i_18_n_0\,
S(1) => \cr[7]_i_19_n_0\,
S(0) => \cr[7]_i_20_n_0\
);
edge_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => edge,
O => edge_i_1_n_0
);
edge_rb_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => edge,
I1 => edge_rb,
O => edge_rb_i_1_n_0
);
edge_rb_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_rb_i_1_n_0,
Q => edge_rb,
R => \hdmi_d[15]_i_1_n_0\
);
edge_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => edge,
R => '0'
);
\hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => edge_i_1_n_0,
Q => D1,
R => '0'
);
\hdmi_d[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(2),
I1 => \cr_hold_reg_n_0_[2]\,
I2 => y_hold(2),
I3 => edge_rb,
I4 => y(2),
I5 => edge,
O => \hdmi_d[10]_i_1_n_0\
);
\hdmi_d[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(3),
I1 => \cr_hold_reg_n_0_[3]\,
I2 => y_hold(3),
I3 => edge_rb,
I4 => y(3),
I5 => edge,
O => \hdmi_d[11]_i_1_n_0\
);
\hdmi_d[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(4),
I1 => \cr_hold_reg_n_0_[4]\,
I2 => y_hold(4),
I3 => edge_rb,
I4 => y(4),
I5 => edge,
O => \hdmi_d[12]_i_1_n_0\
);
\hdmi_d[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(5),
I1 => \cr_hold_reg_n_0_[5]\,
I2 => y_hold(5),
I3 => edge_rb,
I4 => y(5),
I5 => edge,
O => \hdmi_d[13]_i_1_n_0\
);
\hdmi_d[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(6),
I1 => \cr_hold_reg_n_0_[6]\,
I2 => y_hold(6),
I3 => edge_rb,
I4 => y(6),
I5 => edge,
O => \hdmi_d[14]_i_1_n_0\
);
\hdmi_d[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active,
O => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(7),
I1 => \cr_hold_reg_n_0_[7]\,
I2 => y_hold(7),
I3 => edge_rb,
I4 => y(7),
I5 => edge,
O => \hdmi_d[15]_i_2_n_0\
);
\hdmi_d[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(0),
I1 => \cr_hold_reg_n_0_[0]\,
I2 => y_hold(0),
I3 => edge_rb,
I4 => y(0),
I5 => edge,
O => \hdmi_d[8]_i_1_n_0\
);
\hdmi_d[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => cb_hold(1),
I1 => \cr_hold_reg_n_0_[1]\,
I2 => y_hold(1),
I3 => edge_rb,
I4 => y(1),
I5 => edge,
O => \hdmi_d[9]_i_1_n_0\
);
\hdmi_d_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[10]_i_1_n_0\,
Q => hdmi_d(2),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[11]_i_1_n_0\,
Q => hdmi_d(3),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[12]_i_1_n_0\,
Q => hdmi_d(4),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[13]_i_1_n_0\,
Q => hdmi_d(5),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[14]_i_1_n_0\,
Q => hdmi_d(6),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[15]_i_2_n_0\,
Q => hdmi_d(7),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[8]_i_1_n_0\,
Q => hdmi_d(0),
R => \hdmi_d[15]_i_1_n_0\
);
\hdmi_d_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => \hdmi_d[9]_i_1_n_0\,
Q => hdmi_d(1),
R => \hdmi_d[15]_i_1_n_0\
);
hdmi_de_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => active,
Q => hdmi_de,
R => '0'
);
hdmi_hsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hsync,
O => p_0_in
);
hdmi_hsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => p_0_in,
Q => hdmi_hsync,
R => '0'
);
hdmi_vsync_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vsync,
O => hdmi_vsync_i_1_n_0
);
hdmi_vsync_reg: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => '1',
D => hdmi_vsync_i_1_n_0,
Q => hdmi_vsync,
R => '0'
);
\y[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[0]\,
I1 => \y_int_reg__0\(31),
O => \y[0]_i_1_n_0\
);
\y[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[1]\,
I1 => \y_int_reg__0\(31),
O => \y[1]_i_1_n_0\
);
\y[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[2]\,
I1 => \y_int_reg__0\(31),
O => \y[2]_i_1_n_0\
);
\y[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[3]\,
I1 => \y_int_reg__0\(31),
O => \y[3]_i_1_n_0\
);
\y[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[4]\,
I1 => \y_int_reg__0\(31),
O => \y[4]_i_1_n_0\
);
\y[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[5]\,
I1 => \y_int_reg__0\(31),
O => \y[5]_i_1_n_0\
);
\y[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[6]\,
I1 => \y_int_reg__0\(31),
O => \y[6]_i_1_n_0\
);
\y[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_10_n_0\
);
\y[7]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_11_n_0\
);
\y[7]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_13_n_0\
);
\y[7]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_14_n_0\
);
\y[7]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_15_n_0\
);
\y[7]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_16_n_0\
);
\y[7]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(22),
I1 => \y_int_reg__0\(23),
O => \y[7]_i_17_n_0\
);
\y[7]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(20),
I1 => \y_int_reg__0\(21),
O => \y[7]_i_18_n_0\
);
\y[7]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(18),
I1 => \y_int_reg__0\(19),
O => \y[7]_i_19_n_0\
);
\y[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg_n_0_[7]\,
I1 => \y_int_reg__0\(31),
O => \y[7]_i_2_n_0\
);
\y[7]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(16),
I1 => \y_int_reg__0\(17),
O => \y[7]_i_20_n_0\
);
\y[7]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_21_n_0\
);
\y[7]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_22_n_0\
);
\y[7]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_23_n_0\
);
\y[7]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_24_n_0\
);
\y[7]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(14),
I1 => \y_int_reg__0\(15),
O => \y[7]_i_25_n_0\
);
\y[7]_i_26\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(12),
I1 => \y_int_reg__0\(13),
O => \y[7]_i_26_n_0\
);
\y[7]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(10),
I1 => \y_int_reg__0\(11),
O => \y[7]_i_27_n_0\
);
\y[7]_i_28\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(8),
I1 => \y_int_reg__0\(9),
O => \y[7]_i_28_n_0\
);
\y[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_4_n_0\
);
\y[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_5_n_0\
);
\y[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(26),
I1 => \y_int_reg__0\(27),
O => \y[7]_i_6_n_0\
);
\y[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg__0\(24),
I1 => \y_int_reg__0\(25),
O => \y[7]_i_7_n_0\
);
\y[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(30),
I1 => \y_int_reg__0\(31),
O => \y[7]_i_8_n_0\
);
\y[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg__0\(28),
I1 => \y_int_reg__0\(29),
O => \y[7]_i_9_n_0\
);
\y_hold[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(0),
I1 => y(0),
I2 => edge_rb,
O => p_1_in(0)
);
\y_hold[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(1),
I1 => y(1),
I2 => edge_rb,
O => p_1_in(1)
);
\y_hold[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(2),
I1 => y(2),
I2 => edge_rb,
O => p_1_in(2)
);
\y_hold[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(3),
I1 => y(3),
I2 => edge_rb,
O => p_1_in(3)
);
\y_hold[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(4),
I1 => y(4),
I2 => edge_rb,
O => p_1_in(4)
);
\y_hold[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(5),
I1 => y(5),
I2 => edge_rb,
O => p_1_in(5)
);
\y_hold[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(6),
I1 => y(6),
I2 => edge_rb,
O => p_1_in(6)
);
\y_hold[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => y_hold(7),
I1 => y(7),
I2 => edge_rb,
O => p_1_in(7)
);
\y_hold_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(0),
Q => y_hold(0),
R => '0'
);
\y_hold_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(1),
Q => y_hold(1),
R => '0'
);
\y_hold_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(2),
Q => y_hold(2),
R => '0'
);
\y_hold_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(3),
Q => y_hold(3),
R => '0'
);
\y_hold_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(4),
Q => y_hold(4),
R => '0'
);
\y_hold_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(5),
Q => y_hold(5),
R => '0'
);
\y_hold_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(6),
Q => y_hold(6),
R => '0'
);
\y_hold_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => edge_i_1_n_0,
D => p_1_in(7),
Q => y_hold(7),
R => '0'
);
\y_int[11]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_10_n_0\
);
\y_int[11]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
I1 => rgb888(0),
O => \y_int[11]_i_100_n_0\
);
\y_int[11]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(10)
);
\y_int[11]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_22\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[11]_i_12_n_0\
);
\y_int[11]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(0),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(9)
);
\y_int[11]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(2),
O => \y_int[11]_i_16_n_0\
);
\y_int[11]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(8)
);
\y_int[11]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(7),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(15),
O => y_int_reg20_in(7)
);
\y_int[11]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_21\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(1),
O => \y_int[11]_i_19_n_0\
);
\y_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(18),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(10),
I4 => \y_int[11]_i_10_n_0\,
I5 => y_int_reg1(10),
O => \y_int[11]_i_2_n_0\
);
\y_int[11]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(11),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(19),
I3 => y_int_reg6,
O => y_int_reg20_in(11)
);
\y_int[11]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(10),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(18),
I3 => y_int_reg6,
O => y_int_reg20_in(10)
);
\y_int[11]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(9),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(17),
I3 => y_int_reg6,
O => y_int_reg20_in(9)
);
\y_int[11]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(8),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(16),
I3 => y_int_reg6,
O => y_int_reg20_in(8)
);
\y_int[11]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[11]_i_29_n_0\
);
\y_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(17),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(9),
I4 => \y_int[11]_i_12_n_0\,
I5 => y_int_reg1(9),
O => \y_int[11]_i_3_n_0\
);
\y_int[11]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_30_n_0\
);
\y_int[11]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_31_n_0\
);
\y_int[11]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_32_n_0\
);
\y_int[11]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(16),
O => \y_int[11]_i_34_n_0\
);
\y_int[11]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(15),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[11]_i_35_n_0\
);
\y_int[11]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(14),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[11]_i_36_n_0\
);
\y_int[11]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(13),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[11]_i_37_n_0\
);
\y_int[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(16),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(8),
I4 => \y_int[11]_i_16_n_0\,
I5 => y_int_reg1(8),
O => \y_int[11]_i_4_n_0\
);
\y_int[11]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_4\,
O => \y_int[11]_i_40_n_0\
);
\y_int[11]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
O => \y_int[11]_i_41_n_0\
);
\y_int[11]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
O => \y_int[11]_i_42_n_0\
);
\y_int[11]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_21_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_43_n_0\
);
\y_int[11]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_45_n_0\
);
\y_int[11]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_46_n_0\
);
\y_int[11]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_47_n_0\
);
\y_int[11]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_48_n_0\
);
\y_int[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(7),
I1 => \y_int[11]_i_19_n_0\,
I2 => y_int_reg2(7),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_5\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[11]_i_5_n_0\
);
\y_int[11]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_50_n_0\
);
\y_int[11]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_51_n_0\
);
\y_int[11]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_52_n_0\
);
\y_int[11]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_53_n_0\
);
\y_int[11]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_58_n_0\
);
\y_int[11]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_59_n_0\
);
\y_int[11]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_2_n_0\,
I1 => y_int_reg1(11),
I2 => \y_int[15]_i_18_n_0\,
I3 => y_int_reg20_in(11),
O => \y_int[11]_i_6_n_0\
);
\y_int[11]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_60_n_0\
);
\y_int[11]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_61_n_0\
);
\y_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[11]_i_62_n_0\
);
\y_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(12),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[11]_i_63_n_0\
);
\y_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(11),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[11]_i_64_n_0\
);
\y_int[11]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(10),
I1 => y_int_reg6,
I2 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[11]_i_65_n_0\
);
\y_int[11]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => y_int_reg5(9),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[11]_i_66_n_0\
);
\y_int[11]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(1),
O => \y_int[11]_i_67_n_0\
);
\y_int[11]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_21\(0),
O => \y_int[11]_i_68_n_0\
);
\y_int[11]_i_69\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[8]_22\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(3),
O => \y_int[11]_i_69_n_0\
);
\y_int[11]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_3_n_0\,
I1 => y_int_reg1(10),
I2 => \y_int[11]_i_10_n_0\,
I3 => y_int_reg20_in(10),
O => \y_int[11]_i_7_n_0\
);
\y_int[11]_i_70\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(3),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(2),
O => \y_int[11]_i_70_n_0\
);
\y_int[11]_i_71\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[3]_i_35_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_71_n_0\
);
\y_int[11]_i_72\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_4\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_72_n_0\
);
\y_int[11]_i_73\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_5\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_73_n_0\
);
\y_int[11]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_74_n_0\
);
\y_int[11]_i_75\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \y_int_reg[11]_i_44_n_7\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_75_n_0\
);
\y_int[11]_i_76\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_76_n_0\
);
\y_int[11]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_77_n_0\
);
\y_int[11]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_78_n_0\
);
\y_int[11]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_79_n_0\
);
\y_int[11]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_4_n_0\,
I1 => y_int_reg1(9),
I2 => \y_int[11]_i_12_n_0\,
I3 => y_int_reg20_in(9),
O => \y_int[11]_i_8_n_0\
);
\y_int[11]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_81_n_0\
);
\y_int[11]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_82_n_0\
);
\y_int[11]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_83_n_0\
);
\y_int[11]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_84_n_0\
);
\y_int[11]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_11_n_6\,
I1 => \y_int_reg[31]_i_11_n_5\,
O => \y_int[11]_i_86_n_0\
);
\y_int[11]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_4\,
I1 => \y_int_reg[31]_i_11_n_7\,
O => \y_int[11]_i_87_n_0\
);
\y_int[11]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \y_int_reg[31]_i_30_n_5\,
O => \y_int[11]_i_88_n_0\
);
\y_int[11]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[11]_i_89_n_0\
);
\y_int[11]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[11]_i_5_n_0\,
I1 => y_int_reg1(8),
I2 => \y_int[11]_i_16_n_0\,
I3 => y_int_reg20_in(8),
O => \y_int[11]_i_9_n_0\
);
\y_int[11]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_5\,
I1 => \y_int_reg[31]_i_11_n_6\,
O => \y_int[11]_i_90_n_0\
);
\y_int[11]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_11_n_7\,
I1 => \y_int_reg[31]_i_30_n_4\,
O => \y_int[11]_i_91_n_0\
);
\y_int[11]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_5\,
I1 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[11]_i_92_n_0\
);
\y_int[11]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
I1 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[11]_i_93_n_0\
);
\y_int[11]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
I1 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[11]_i_94_n_0\
);
\y_int[11]_i_95\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => rgb888(0),
O => \y_int[11]_i_95_n_0\
);
\y_int[11]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(0),
I1 => rgb888(1),
O => \y_int[11]_i_96_n_0\
);
\y_int[11]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
I1 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[11]_i_97_n_0\
);
\y_int[11]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
I1 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[11]_i_98_n_0\
);
\y_int[11]_i_99\: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
I2 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[11]_i_99_n_0\
);
\y_int[15]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_10_n_0\
);
\y_int[15]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(14)
);
\y_int[15]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_12_n_0\
);
\y_int[15]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(13)
);
\y_int[15]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_16_n_0\
);
\y_int[15]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(12)
);
\y_int[15]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \y_int_reg[15]_i_33_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_29\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[15]_i_18_n_0\
);
\y_int[15]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[15]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(11)
);
\y_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(22),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(14),
I4 => \y_int[15]_i_10_n_0\,
I5 => y_int_reg1(14),
O => \y_int[15]_i_2_n_0\
);
\y_int[15]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(15),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(23),
I3 => y_int_reg6,
O => y_int_reg20_in(15)
);
\y_int[15]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(14),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(22),
I3 => y_int_reg6,
O => y_int_reg20_in(14)
);
\y_int[15]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(13),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(21),
I3 => y_int_reg6,
O => y_int_reg20_in(13)
);
\y_int[15]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(12),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(20),
I3 => y_int_reg6,
O => y_int_reg20_in(12)
);
\y_int[15]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_25_n_0\
);
\y_int[15]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_26_n_0\
);
\y_int[15]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_27_n_0\
);
\y_int[15]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[15]_i_28_n_0\
);
\y_int[15]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(20),
O => \y_int[15]_i_29_n_0\
);
\y_int[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(21),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(13),
I4 => \y_int[15]_i_12_n_0\,
I5 => y_int_reg1(13),
O => \y_int[15]_i_3_n_0\
);
\y_int[15]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(19),
O => \y_int[15]_i_30_n_0\
);
\y_int[15]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(18),
O => \y_int[15]_i_31_n_0\
);
\y_int[15]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(17),
O => \y_int[15]_i_32_n_0\
);
\y_int[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(20),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(12),
I4 => \y_int[15]_i_16_n_0\,
I5 => y_int_reg1(12),
O => \y_int[15]_i_4_n_0\
);
\y_int[15]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(2),
O => \y_int[15]_i_40_n_0\
);
\y_int[15]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(1),
O => \y_int[15]_i_41_n_0\
);
\y_int[15]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_29\(0),
O => \y_int[15]_i_42_n_0\
);
\y_int[15]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_22\(3),
O => \y_int[15]_i_43_n_0\
);
\y_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_48_n_0\
);
\y_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_49_n_0\
);
\y_int[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(19),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(11),
I4 => \y_int[15]_i_18_n_0\,
I5 => y_int_reg1(11),
O => \y_int[15]_i_5_n_0\
);
\y_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_50_n_0\
);
\y_int[15]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[15]_i_51_n_0\
);
\y_int[15]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_2_n_0\,
I1 => y_int_reg1(15),
I2 => \y_int[19]_i_18_n_0\,
I3 => y_int_reg20_in(15),
O => \y_int[15]_i_6_n_0\
);
\y_int[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_3_n_0\,
I1 => y_int_reg1(14),
I2 => \y_int[15]_i_10_n_0\,
I3 => y_int_reg20_in(14),
O => \y_int[15]_i_7_n_0\
);
\y_int[15]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_4_n_0\,
I1 => y_int_reg1(13),
I2 => \y_int[15]_i_12_n_0\,
I3 => y_int_reg20_in(13),
O => \y_int[15]_i_8_n_0\
);
\y_int[15]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[15]_i_5_n_0\,
I1 => y_int_reg1(12),
I2 => \y_int[15]_i_16_n_0\,
I3 => y_int_reg20_in(12),
O => \y_int[15]_i_9_n_0\
);
\y_int[19]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_10_n_0\
);
\y_int[19]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(9),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(18)
);
\y_int[19]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_12_n_0\
);
\y_int[19]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(8),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(17)
);
\y_int[19]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_16_n_0\
);
\y_int[19]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(16)
);
\y_int[19]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_28\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_27\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[19]_i_18_n_0\
);
\y_int[19]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[19]_0\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(15)
);
\y_int[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(26),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(18),
I4 => \y_int[19]_i_10_n_0\,
I5 => y_int_reg1(18),
O => \y_int[19]_i_2_n_0\
);
\y_int[19]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(19),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(27),
I3 => y_int_reg6,
O => y_int_reg20_in(19)
);
\y_int[19]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(18),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(26),
I3 => y_int_reg6,
O => y_int_reg20_in(18)
);
\y_int[19]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(17),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(25),
I3 => y_int_reg6,
O => y_int_reg20_in(17)
);
\y_int[19]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(16),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(24),
I3 => y_int_reg6,
O => y_int_reg20_in(16)
);
\y_int[19]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_25_n_0\
);
\y_int[19]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_26_n_0\
);
\y_int[19]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_27_n_0\
);
\y_int[19]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[19]_i_28_n_0\
);
\y_int[19]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(24),
O => \y_int[19]_i_29_n_0\
);
\y_int[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(25),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(17),
I4 => \y_int[19]_i_12_n_0\,
I5 => y_int_reg1(17),
O => \y_int[19]_i_3_n_0\
);
\y_int[19]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(23),
O => \y_int[19]_i_30_n_0\
);
\y_int[19]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(22),
O => \y_int[19]_i_31_n_0\
);
\y_int[19]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(21),
O => \y_int[19]_i_32_n_0\
);
\y_int[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(24),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(16),
I4 => \y_int[19]_i_16_n_0\,
I5 => y_int_reg1(16),
O => \y_int[19]_i_4_n_0\
);
\y_int[19]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_48_n_0\
);
\y_int[19]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_49_n_0\
);
\y_int[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(23),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(15),
I4 => \y_int[19]_i_18_n_0\,
I5 => y_int_reg1(15),
O => \y_int[19]_i_5_n_0\
);
\y_int[19]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_50_n_0\
);
\y_int[19]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[19]_i_51_n_0\
);
\y_int[19]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_2_n_0\,
I1 => y_int_reg1(19),
I2 => \y_int[23]_i_20_n_0\,
I3 => y_int_reg20_in(19),
O => \y_int[19]_i_6_n_0\
);
\y_int[19]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_3_n_0\,
I1 => y_int_reg1(18),
I2 => \y_int[19]_i_10_n_0\,
I3 => y_int_reg20_in(18),
O => \y_int[19]_i_7_n_0\
);
\y_int[19]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_4_n_0\,
I1 => y_int_reg1(17),
I2 => \y_int[19]_i_12_n_0\,
I3 => y_int_reg20_in(17),
O => \y_int[19]_i_8_n_0\
);
\y_int[19]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[19]_i_5_n_0\,
I1 => y_int_reg1(16),
I2 => \y_int[19]_i_16_n_0\,
I3 => y_int_reg20_in(16),
O => \y_int[19]_i_9_n_0\
);
\y_int[23]_i_100\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_19\(0),
I1 => \^y_int_reg[3]_0\(0),
O => \y_int[23]_i_100_n_0\
);
\y_int[23]_i_101\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(0),
I1 => \^y_int_reg[3]_0\(3),
O => \y_int[23]_i_101_n_0\
);
\y_int[23]_i_102\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(2),
I1 => \^y_int_reg[3]_0\(1),
O => \y_int[23]_i_102_n_0\
);
\y_int[23]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[3]_0\(0),
I1 => \rgb888[8]_19\(0),
O => \y_int[23]_i_103_n_0\
);
\y_int[23]_i_104\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \y_int[23]_i_104_n_0\
);
\y_int[23]_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(1),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_24\(0),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_12_n_0\
);
\y_int[23]_i_13\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(13),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(1),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(22)
);
\y_int[23]_i_14\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_23\(0),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(3),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_14_n_0\
);
\y_int[23]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(12),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_1\(0),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(21)
);
\y_int[23]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(3),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(2),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_18_n_0\
);
\y_int[23]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(11),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(3),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(20)
);
\y_int[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(30),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(22),
I4 => \y_int[23]_i_12_n_0\,
I5 => y_int_reg1(22),
O => \y_int[23]_i_2_n_0\
);
\y_int[23]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[8]_26\(2),
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_25\(1),
I3 => \^y_int_reg[3]_1\(0),
O => \y_int[23]_i_20_n_0\
);
\y_int[23]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \rgb888[1]\(10),
I1 => \^y_int_reg[23]_0\(0),
I2 => \^y_int_reg[23]_2\(2),
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(19)
);
\y_int[23]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(22),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(30),
I3 => y_int_reg6,
O => y_int_reg20_in(22)
);
\y_int[23]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(21),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(29),
I3 => y_int_reg6,
O => y_int_reg20_in(21)
);
\y_int[23]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg3(20),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => y_int_reg5(28),
I3 => y_int_reg6,
O => y_int_reg20_in(20)
);
\y_int[23]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_26_n_0\
);
\y_int[23]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_27_n_0\
);
\y_int[23]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_28_n_0\
);
\y_int[23]_i_29\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_29_n_0\
);
\y_int[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(29),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(21),
I4 => \y_int[23]_i_14_n_0\,
I5 => y_int_reg1(21),
O => \y_int[23]_i_3_n_0\
);
\y_int[23]_i_30\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_30_n_0\
);
\y_int[23]_i_31\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_31_n_0\
);
\y_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_36_n_0\
);
\y_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_37_n_0\
);
\y_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_38_n_0\
);
\y_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_39_n_0\
);
\y_int[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(28),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(20),
I4 => \y_int[23]_i_18_n_0\,
I5 => y_int_reg1(20),
O => \y_int[23]_i_4_n_0\
);
\y_int[23]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(28),
O => \y_int[23]_i_40_n_0\
);
\y_int[23]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(27),
O => \y_int[23]_i_41_n_0\
);
\y_int[23]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(26),
O => \y_int[23]_i_42_n_0\
);
\y_int[23]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(25),
O => \y_int[23]_i_43_n_0\
);
\y_int[23]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_46_n_0\
);
\y_int[23]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_47_n_0\
);
\y_int[23]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_48_n_0\
);
\y_int[23]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
O => \y_int[23]_i_49_n_0\
);
\y_int[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF404F4040000"
)
port map (
I0 => y_int_reg6,
I1 => y_int_reg5(27),
I2 => \y_int_reg[31]_i_8_n_5\,
I3 => y_int_reg3(19),
I4 => \y_int[23]_i_20_n_0\,
I5 => y_int_reg1(19),
O => \y_int[23]_i_5_n_0\
);
\y_int[23]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_52_n_0\
);
\y_int[23]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_53_n_0\
);
\y_int[23]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_54_n_0\
);
\y_int[23]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_55_n_0\
);
\y_int[23]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_56_n_0\
);
\y_int[23]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_57_n_0\
);
\y_int[23]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[23]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[23]_i_6_n_0\
);
\y_int[23]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_62_n_0\
);
\y_int[23]_i_63\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_63_n_0\
);
\y_int[23]_i_64\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_64_n_0\
);
\y_int[23]_i_65\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^y_int_reg[23]_0\(0),
O => \y_int[23]_i_65_n_0\
);
\y_int[23]_i_67\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_8_n_7\,
I1 => \y_int_reg[31]_i_8_n_6\,
O => \y_int[23]_i_67_n_0\
);
\y_int[23]_i_68\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_5\,
I1 => \y_int_reg[31]_i_16_n_4\,
O => \y_int[23]_i_68_n_0\
);
\y_int[23]_i_69\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_16_n_7\,
I1 => \y_int_reg[31]_i_16_n_6\,
O => \y_int[23]_i_69_n_0\
);
\y_int[23]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_3_n_0\,
I1 => y_int_reg1(22),
I2 => \y_int[23]_i_12_n_0\,
I3 => y_int_reg20_in(22),
O => \y_int[23]_i_7_n_0\
);
\y_int[23]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
I1 => \y_int_reg[3]_i_16_n_4\,
O => \y_int[23]_i_70_n_0\
);
\y_int[23]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_8_n_6\,
I1 => \y_int_reg[31]_i_8_n_7\,
O => \y_int[23]_i_71_n_0\
);
\y_int[23]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_4\,
I1 => \y_int_reg[31]_i_16_n_5\,
O => \y_int[23]_i_72_n_0\
);
\y_int[23]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_16_n_6\,
I1 => \y_int_reg[31]_i_16_n_7\,
O => \y_int[23]_i_73_n_0\
);
\y_int[23]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_4\,
I1 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[23]_i_74_n_0\
);
\y_int[23]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_21\(1),
I1 => \rgb888[8]_21\(2),
O => \y_int[23]_i_76_n_0\
);
\y_int[23]_i_77\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_77_n_0\
);
\y_int[23]_i_78\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_78_n_0\
);
\y_int[23]_i_79\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
O => \y_int[23]_i_79_n_0\
);
\y_int[23]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_4_n_0\,
I1 => y_int_reg1(21),
I2 => \y_int[23]_i_14_n_0\,
I3 => y_int_reg20_in(21),
O => \y_int[23]_i_8_n_0\
);
\y_int[23]_i_80\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_21\(1),
O => \y_int[23]_i_80_n_0\
);
\y_int[23]_i_81\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
I1 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[23]_i_81_n_0\
);
\y_int[23]_i_82\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
I1 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[23]_i_82_n_0\
);
\y_int[23]_i_83\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
I1 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[23]_i_83_n_0\
);
\y_int[23]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rgb888(16),
I1 => rgb888(17),
O => \y_int[23]_i_84_n_0\
);
\y_int[23]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
I1 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[23]_i_85_n_0\
);
\y_int[23]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
I1 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[23]_i_86_n_0\
);
\y_int[23]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
I1 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[23]_i_87_n_0\
);
\y_int[23]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
I1 => rgb888(16),
O => \y_int[23]_i_88_n_0\
);
\y_int[23]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[23]_i_5_n_0\,
I1 => y_int_reg1(20),
I2 => \y_int[23]_i_18_n_0\,
I3 => y_int_reg20_in(20),
O => \y_int[23]_i_9_n_0\
);
\y_int[23]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(3),
I1 => \rgb888[8]_21\(0),
O => \y_int[23]_i_90_n_0\
);
\y_int[23]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[8]_20\(1),
I1 => \rgb888[8]_20\(2),
O => \y_int[23]_i_91_n_0\
);
\y_int[23]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(3),
I1 => \rgb888[8]_20\(0),
O => \y_int[23]_i_92_n_0\
);
\y_int[23]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \rgb888[14]\(2),
O => \y_int[23]_i_93_n_0\
);
\y_int[23]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_21\(0),
I1 => \rgb888[8]_20\(3),
O => \y_int[23]_i_94_n_0\
);
\y_int[23]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(2),
I1 => \rgb888[8]_20\(1),
O => \y_int[23]_i_95_n_0\
);
\y_int[23]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[8]_20\(0),
I1 => \rgb888[14]\(3),
O => \y_int[23]_i_96_n_0\
);
\y_int[23]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \rgb888[14]\(2),
I1 => \rgb888[14]\(1),
O => \y_int[23]_i_97_n_0\
);
\y_int[23]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(3),
I1 => \rgb888[14]\(0),
O => \y_int[23]_i_98_n_0\
);
\y_int[23]_i_99\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^y_int_reg[3]_0\(1),
I1 => \^y_int_reg[3]_0\(2),
O => \y_int[23]_i_99_n_0\
);
\y_int[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_2_n_0\
);
\y_int[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_3_n_0\
);
\y_int[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_4_n_0\
);
\y_int[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[27]_i_5_n_0\
);
\y_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \y_int[31]_i_101_n_0\
);
\y_int[31]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_104_n_0\
);
\y_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(2),
O => \y_int[31]_i_105_n_0\
);
\y_int[31]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_106_n_0\
);
\y_int[31]_i_107\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_107_n_0\
);
\y_int[31]_i_108\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(0),
O => \y_int[31]_i_108_n_0\
);
\y_int[31]_i_109\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(6),
O => \y_int[31]_i_109_n_0\
);
\y_int[31]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
O => \y_int[31]_i_110_n_0\
);
\y_int[31]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
O => \y_int[31]_i_111_n_0\
);
\y_int[31]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
O => \y_int[31]_i_112_n_0\
);
\y_int[31]_i_113\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
O => \y_int[31]_i_113_n_0\
);
\y_int[31]_i_114\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
O => \y_int[31]_i_114_n_0\
);
\y_int[31]_i_115\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(2),
I1 => rgb888(0),
O => \y_int[31]_i_115_n_0\
);
\y_int[31]_i_116\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(1),
O => \y_int[31]_i_116_n_0\
);
\y_int[31]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_21\(2),
I1 => \rgb888[8]_30\(0),
O => \y_int[31]_i_13_n_0\
);
\y_int[31]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(30),
O => \y_int[31]_i_14_n_0\
);
\y_int[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_8_n_5\,
I1 => y_int_reg6,
I2 => y_int_reg5(29),
O => \y_int[31]_i_15_n_0\
);
\y_int[31]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
I5 => rgb888(23),
O => \y_int[31]_i_17_n_0\
);
\y_int[31]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_18_n_0\
);
\y_int[31]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(23),
I1 => rgb888(20),
I2 => rgb888(18),
I3 => rgb888(19),
I4 => rgb888(21),
I5 => rgb888(22),
O => \y_int[31]_i_19_n_0\
);
\y_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040004044F40040"
)
port map (
I0 => \y_int_reg[31]_i_7_n_1\,
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \rgb888[8]_21\(2),
I3 => \rgb888[8]_30\(0),
I4 => \^y_int_reg[23]_0\(0),
I5 => \rgb888[1]_0\(0),
O => \y_int[31]_i_2_n_0\
);
\y_int[31]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => rgb888(22),
I1 => rgb888(21),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => rgb888(20),
I5 => rgb888(23),
O => \y_int[31]_i_20_n_0\
);
\y_int[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_3_n_0\
);
\y_int[31]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_32_n_0\
);
\y_int[31]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_33_n_0\
);
\y_int[31]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[0]_9\(2),
O => \y_int[31]_i_34_n_0\
);
\y_int[31]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \y_int_reg[31]_i_75_n_2\,
I1 => \rgb888[0]_9\(0),
I2 => \rgb888[0]_9\(1),
O => \y_int[31]_i_35_n_0\
);
\y_int[31]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"36"
)
port map (
I0 => \rgb888[0]_7\(3),
I1 => \rgb888[0]_9\(0),
I2 => \y_int_reg[31]_i_75_n_2\,
O => \y_int[31]_i_36_n_0\
);
\y_int[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_4_n_0\
);
\y_int[31]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(21),
I4 => rgb888(22),
O => \y_int[31]_i_40_n_0\
);
\y_int[31]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"BEEEEEEE"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(21),
I2 => rgb888(20),
I3 => rgb888(18),
I4 => rgb888(19),
O => \y_int[31]_i_41_n_0\
);
\y_int[31]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FD51540"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(20),
I4 => rgb888(23),
O => \y_int[31]_i_42_n_0\
);
\y_int[31]_i_43\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \y_int_reg[3]_i_64_n_7\,
I1 => rgb888(18),
I2 => rgb888(19),
I3 => rgb888(22),
O => \y_int[31]_i_43_n_0\
);
\y_int[31]_i_44\: unisim.vcomponents.LUT6
generic map(
INIT => X"A999999999999999"
)
port map (
I0 => rgb888(23),
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_44_n_0\
);
\y_int[31]_i_45\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CC9C9C9C9C9C9C9"
)
port map (
I0 => \y_int_reg[3]_i_64_n_2\,
I1 => rgb888(22),
I2 => rgb888(21),
I3 => rgb888(19),
I4 => rgb888(18),
I5 => rgb888(20),
O => \y_int[31]_i_45_n_0\
);
\y_int[31]_i_46\: unisim.vcomponents.LUT6
generic map(
INIT => X"157FEA807FEA8015"
)
port map (
I0 => rgb888(23),
I1 => rgb888(19),
I2 => rgb888(18),
I3 => rgb888(20),
I4 => rgb888(21),
I5 => \y_int_reg[3]_i_64_n_2\,
O => \y_int[31]_i_46_n_0\
);
\y_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996699669"
)
port map (
I0 => \y_int[31]_i_43_n_0\,
I1 => \y_int_reg[3]_i_64_n_2\,
I2 => rgb888(23),
I3 => rgb888(20),
I4 => rgb888(19),
I5 => rgb888(18),
O => \y_int[31]_i_47_n_0\
);
\y_int[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_5_n_0\
);
\y_int[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"659A659A9A65659A"
)
port map (
I0 => \y_int[31]_i_2_n_0\,
I1 => \rgb888[1]_0\(0),
I2 => \^y_int_reg[23]_0\(0),
I3 => \y_int[31]_i_13_n_0\,
I4 => \y_int_reg[31]_i_8_n_5\,
I5 => \y_int_reg[31]_i_7_n_1\,
O => \y_int[31]_i_6_n_0\
);
\y_int[31]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \rgb888[0]_7\(2),
I1 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_63_n_0\
);
\y_int[31]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_64_n_0\
);
\y_int[31]_i_65\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_87_n_4\,
I1 => \rgb888[0]_7\(1),
O => \y_int[31]_i_65_n_0\
);
\y_int[31]_i_66\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \y_int_reg[31]_i_86_n_4\,
I1 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_66_n_0\
);
\y_int[31]_i_67\: unisim.vcomponents.LUT4
generic map(
INIT => X"7887"
)
port map (
I0 => \y_int_reg[31]_i_75_n_7\,
I1 => \rgb888[0]_7\(2),
I2 => \y_int_reg[31]_i_75_n_2\,
I3 => \rgb888[0]_7\(3),
O => \y_int[31]_i_67_n_0\
);
\y_int[31]_i_68\: unisim.vcomponents.LUT4
generic map(
INIT => X"E11E"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \rgb888[0]_7\(2),
I3 => \y_int_reg[31]_i_75_n_7\,
O => \y_int[31]_i_68_n_0\
);
\y_int[31]_i_69\: unisim.vcomponents.LUT4
generic map(
INIT => X"6999"
)
port map (
I0 => \rgb888[0]_7\(1),
I1 => \y_int_reg[31]_i_87_n_4\,
I2 => \y_int_reg[31]_i_87_n_5\,
I3 => \rgb888[0]_7\(0),
O => \y_int[31]_i_69_n_0\
);
\y_int[31]_i_70\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \y_int_reg[31]_i_87_n_6\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \rgb888[0]_7\(0),
I3 => \y_int_reg[31]_i_87_n_5\,
O => \y_int[31]_i_70_n_0\
);
\y_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_86_n_4\,
I2 => \y_int_reg[31]_i_87_n_6\,
O => \y_int[31]_i_89_n_0\
);
\y_int[31]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \y_int_reg[31]_i_86_n_5\,
I1 => \y_int_reg[31]_i_87_n_7\,
O => \y_int[31]_i_90_n_0\
);
\y_int[31]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_4\,
I1 => \y_int_reg[31]_i_86_n_6\,
O => \y_int[31]_i_91_n_0\
);
\y_int[31]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[31]_i_88_n_5\,
I1 => rgb888(0),
O => \y_int[31]_i_92_n_0\
);
\y_int[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(0),
O => \y_int[3]_i_10_n_0\
);
\y_int[3]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(2),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_4\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_6\,
O => y_int_reg1(2)
);
\y_int[3]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(1),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[3]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(9),
O => y_int_reg20_in(1)
);
\y_int[3]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[14]\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_0\(1),
O => \y_int[3]_i_13_n_0\
);
\y_int[3]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(1),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_30_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_7\,
O => y_int_reg1(1)
);
\y_int[3]_i_17\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \rgb888[14]\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]_0\(0),
O => \y_int[3]_i_17_n_0\
);
\y_int[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
I1 => \^y_int_reg[7]_0\(0),
I2 => \y_int_reg[3]_i_35_n_4\,
O => \y_int[3]_i_18_n_0\
);
\y_int[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
O => \y_int[3]_i_2_n_0\
);
\y_int[3]_i_22\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_5\,
O => \y_int[3]_i_22_n_0\
);
\y_int[3]_i_23\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_6\,
O => \y_int[3]_i_23_n_0\
);
\y_int[3]_i_24\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_16_n_7\,
O => \y_int[3]_i_24_n_0\
);
\y_int[3]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_4\,
O => \y_int[3]_i_25_n_0\
);
\y_int[3]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(18),
I1 => \y_int_reg[3]_i_30_n_4\,
I2 => rgb888(21),
O => \y_int[3]_i_27_n_0\
);
\y_int[3]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_28_n_0\
);
\y_int[3]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \y_int_reg[3]_i_30_n_5\,
I1 => rgb888(17),
I2 => rgb888(20),
O => \y_int[3]_i_29_n_0\
);
\y_int[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
O => \y_int[3]_i_3_n_0\
);
\y_int[3]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \y_int[3]_i_27_n_0\,
I1 => rgb888(22),
I2 => rgb888(19),
I3 => rgb888(18),
I4 => \y_int_reg[3]_i_64_n_7\,
O => \y_int[3]_i_31_n_0\
);
\y_int[3]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(21),
I4 => rgb888(18),
I5 => \y_int_reg[3]_i_30_n_4\,
O => \y_int[3]_i_32_n_0\
);
\y_int[3]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(20),
I1 => rgb888(17),
I2 => \y_int_reg[3]_i_30_n_5\,
I3 => rgb888(19),
I4 => rgb888(16),
O => \y_int[3]_i_33_n_0\
);
\y_int[3]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(16),
I1 => rgb888(19),
I2 => \y_int_reg[3]_i_30_n_6\,
O => \y_int[3]_i_34_n_0\
);
\y_int[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE2E200"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_4_n_0\
);
\y_int[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
I3 => \y_int[3]_i_2_n_0\,
O => \y_int[3]_i_5_n_0\
);
\y_int[3]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(16),
O => \y_int[3]_i_50_n_0\
);
\y_int[3]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_5\,
O => \y_int[3]_i_51_n_0\
);
\y_int[3]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_6\,
O => \y_int[3]_i_52_n_0\
);
\y_int[3]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_26_n_7\,
O => \y_int[3]_i_53_n_0\
);
\y_int[3]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_54_n_0\
);
\y_int[3]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_30_n_7\,
I1 => rgb888(18),
O => \y_int[3]_i_56_n_0\
);
\y_int[3]_i_57\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_4\,
I1 => rgb888(17),
O => \y_int[3]_i_57_n_0\
);
\y_int[3]_i_58\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_int_reg[3]_i_55_n_5\,
I1 => rgb888(16),
O => \y_int[3]_i_58_n_0\
);
\y_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \y_int_reg[3]_i_55_n_6\,
O => \y_int[3]_i_59_n_0\
);
\y_int[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(2),
I1 => \y_int[3]_i_10_n_0\,
I2 => y_int_reg1(2),
I3 => \y_int[3]_i_3_n_0\,
O => \y_int[3]_i_6_n_0\
);
\y_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(22),
O => \y_int[3]_i_60_n_0\
);
\y_int[3]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(23),
I1 => rgb888(21),
O => \y_int[3]_i_61_n_0\
);
\y_int[3]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(22),
I1 => rgb888(20),
O => \y_int[3]_i_62_n_0\
);
\y_int[3]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(21),
I1 => rgb888(19),
O => \y_int[3]_i_63_n_0\
);
\y_int[3]_i_66\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_6\,
O => \y_int[3]_i_66_n_0\
);
\y_int[3]_i_67\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_30_n_7\,
O => \y_int[3]_i_67_n_0\
);
\y_int[3]_i_68\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_4\,
O => \y_int[3]_i_68_n_0\
);
\y_int[3]_i_69\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_5\,
O => \y_int[3]_i_69_n_0\
);
\y_int[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(1),
I1 => \y_int[3]_i_13_n_0\,
I2 => y_int_reg1(1),
I3 => \y_int[3]_i_4_n_0\,
O => \y_int[3]_i_7_n_0\
);
\y_int[3]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(1),
I1 => rgb888(10),
O => \y_int[3]_i_71_n_0\
);
\y_int[3]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_32\(0),
I1 => rgb888(9),
O => \y_int[3]_i_72_n_0\
);
\y_int[3]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \rgb888[8]_19\(2),
I1 => rgb888(8),
O => \y_int[3]_i_73_n_0\
);
\y_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \rgb888[8]_19\(1),
O => \y_int[3]_i_74_n_0\
);
\y_int[3]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"E21D1DE2"
)
port map (
I0 => y_int_reg5(8),
I1 => y_int_reg6,
I2 => \y_int_reg[3]_i_16_n_5\,
I3 => \y_int[3]_i_17_n_0\,
I4 => \y_int[3]_i_18_n_0\,
O => \y_int[3]_i_8_n_0\
);
\y_int[3]_i_84\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(20),
I1 => rgb888(18),
O => \y_int[3]_i_84_n_0\
);
\y_int[3]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(19),
I1 => rgb888(17),
O => \y_int[3]_i_85_n_0\
);
\y_int[3]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(18),
I1 => rgb888(16),
O => \y_int[3]_i_86_n_0\
);
\y_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(17),
O => \y_int[3]_i_87_n_0\
);
\y_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(23),
O => \y_int[3]_i_88_n_0\
);
\y_int[3]_i_89\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_62_n_6\,
O => \y_int[3]_i_89_n_0\
);
\y_int[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(2),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(10),
O => y_int_reg20_in(2)
);
\y_int[3]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(0),
I1 => \y_int_reg[31]_i_88_n_5\,
O => \y_int[3]_i_90_n_0\
);
\y_int[3]_i_91\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_88_n_6\,
O => \y_int[3]_i_91_n_0\
);
\y_int[3]_i_92\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(1),
O => \y_int[3]_i_92_n_0\
);
\y_int[7]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(6),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_8_n_7\,
I3 => y_int_reg6,
I4 => y_int_reg5(14),
O => y_int_reg20_in(6)
);
\y_int[7]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_6\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(3),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[8]_22\(0),
O => \y_int[7]_i_11_n_0\
);
\y_int[7]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(5),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_4\,
I3 => y_int_reg6,
I4 => y_int_reg5(13),
O => y_int_reg20_in(5)
);
\y_int[7]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[11]_i_38_n_7\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(2),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(3),
O => \y_int[7]_i_13_n_0\
);
\y_int[7]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(5),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_5\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_21_n_7\,
O => y_int_reg1(5)
);
\y_int[7]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(4),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_5\,
I3 => y_int_reg6,
I4 => y_int_reg5(12),
O => y_int_reg20_in(4)
);
\y_int[7]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_4\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(1),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(2),
O => \y_int[7]_i_16_n_0\
);
\y_int[7]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(4),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_6\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_4\,
O => y_int_reg1(4)
);
\y_int[7]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg3(3),
I1 => \y_int_reg[31]_i_8_n_5\,
I2 => \y_int_reg[31]_i_16_n_6\,
I3 => y_int_reg6,
I4 => y_int_reg5(11),
O => y_int_reg20_in(3)
);
\y_int[7]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \y_int_reg[7]_i_24_n_5\,
I1 => \rgb888[8]_21\(2),
I2 => \rgb888[8]_20\(0),
I3 => \^y_int_reg[3]_1\(0),
I4 => \rgb888[14]_1\(1),
O => \y_int[7]_i_19_n_0\
);
\y_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E888E888E8EEE888"
)
port map (
I0 => y_int_reg20_in(6),
I1 => \y_int[7]_i_11_n_0\,
I2 => y_int_reg2(6),
I3 => \^y_int_reg[23]_0\(0),
I4 => \y_int_reg[11]_i_21_n_6\,
I5 => \^y_int_reg[7]_0\(0),
O => \y_int[7]_i_2_n_0\
);
\y_int[7]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => y_int_reg2(3),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[31]_i_11_n_7\,
I3 => \^y_int_reg[7]_0\(0),
I4 => \y_int_reg[11]_i_44_n_5\,
O => y_int_reg1(3)
);
\y_int[7]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(7),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_5\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(7)
);
\y_int[7]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => y_int_reg2(6),
I1 => \^y_int_reg[23]_0\(0),
I2 => \y_int_reg[11]_i_21_n_6\,
I3 => \^y_int_reg[7]_0\(0),
O => y_int_reg1(6)
);
\y_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(1),
O => \y_int[7]_i_29_n_0\
);
\y_int[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
O => \y_int[7]_i_3_n_0\
);
\y_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(2),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(1),
O => \y_int[7]_i_30_n_0\
);
\y_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[8]_20\(0),
O => \y_int[7]_i_31_n_0\
);
\y_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_1\(0),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(3),
O => \y_int[7]_i_32_n_0\
);
\y_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \rgb888[14]_0\(1),
I1 => \^y_int_reg[3]_1\(0),
I2 => \rgb888[14]\(2),
O => \y_int[7]_i_33_n_0\
);
\y_int[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
O => \y_int[7]_i_4_n_0\
);
\y_int[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => y_int_reg20_in(3),
I1 => \y_int[7]_i_19_n_0\,
I2 => y_int_reg1(3),
O => \y_int[7]_i_5_n_0\
);
\y_int[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_2_n_0\,
I1 => y_int_reg1(7),
I2 => \y_int[11]_i_19_n_0\,
I3 => y_int_reg20_in(7),
O => \y_int[7]_i_6_n_0\
);
\y_int[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \y_int[7]_i_3_n_0\,
I1 => y_int_reg1(6),
I2 => \y_int[7]_i_11_n_0\,
I3 => y_int_reg20_in(6),
O => \y_int[7]_i_7_n_0\
);
\y_int[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(5),
I1 => \y_int[7]_i_13_n_0\,
I2 => y_int_reg1(5),
I3 => \y_int[7]_i_4_n_0\,
O => \y_int[7]_i_8_n_0\
);
\y_int[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => y_int_reg20_in(4),
I1 => \y_int[7]_i_16_n_0\,
I2 => y_int_reg1(4),
I3 => \y_int[7]_i_5_n_0\,
O => \y_int[7]_i_9_n_0\
);
\y_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_7\,
Q => \y_int_reg_n_0_[0]\,
R => '0'
);
\y_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_5\,
Q => \y_int_reg__0\(10),
R => '0'
);
\y_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_4\,
Q => \y_int_reg__0\(11),
R => '0'
);
\y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_1_n_0\,
CO(3) => \y_int_reg[11]_i_1_n_0\,
CO(2) => \y_int_reg[11]_i_1_n_1\,
CO(1) => \y_int_reg[11]_i_1_n_2\,
CO(0) => \y_int_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[11]_i_2_n_0\,
DI(2) => \y_int[11]_i_3_n_0\,
DI(1) => \y_int[11]_i_4_n_0\,
DI(0) => \y_int[11]_i_5_n_0\,
O(3) => \y_int_reg[11]_i_1_n_4\,
O(2) => \y_int_reg[11]_i_1_n_5\,
O(1) => \y_int_reg[11]_i_1_n_6\,
O(0) => \y_int_reg[11]_i_1_n_7\,
S(3) => \y_int[11]_i_6_n_0\,
S(2) => \y_int[11]_i_7_n_0\,
S(1) => \y_int[11]_i_8_n_0\,
S(0) => \y_int[11]_i_9_n_0\
);
\y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_28_n_0\,
CO(3) => \y_int_reg[11]_i_14_n_0\,
CO(2) => \y_int_reg[11]_i_14_n_1\,
CO(1) => \y_int_reg[11]_i_14_n_2\,
CO(0) => \y_int_reg[11]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(16 downto 13),
S(3) => \y_int[11]_i_29_n_0\,
S(2) => \y_int[11]_i_30_n_0\,
S(1) => \y_int[11]_i_31_n_0\,
S(0) => \y_int[11]_i_32_n_0\
);
\y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_33_n_0\,
CO(3) => \y_int_reg[11]_i_15_n_0\,
CO(2) => \y_int_reg[11]_i_15_n_1\,
CO(1) => \y_int_reg[11]_i_15_n_2\,
CO(0) => \y_int_reg[11]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(8 downto 5),
S(3) => \y_int[11]_i_34_n_0\,
S(2) => \y_int[11]_i_35_n_0\,
S(1) => \y_int[11]_i_36_n_0\,
S(0) => \y_int[11]_i_37_n_0\
);
\y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_39_n_0\,
CO(3) => \y_int_reg[15]_1\(0),
CO(2) => \y_int_reg[11]_i_20_n_1\,
CO(1) => \y_int_reg[11]_i_20_n_2\,
CO(0) => \y_int_reg[11]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(8 downto 5),
S(3) => \y_int[11]_i_40_n_0\,
S(2) => \y_int[11]_i_41_n_0\,
S(1) => \y_int[11]_i_42_n_0\,
S(0) => \y_int[11]_i_43_n_0\
);
\y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_44_n_0\,
CO(3) => \y_int_reg[11]_i_21_n_0\,
CO(2) => \y_int_reg[11]_i_21_n_1\,
CO(1) => \y_int_reg[11]_i_21_n_2\,
CO(0) => \y_int_reg[11]_i_21_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_21_n_4\,
O(2) => \y_int_reg[11]_i_21_n_5\,
O(1) => \y_int_reg[11]_i_21_n_6\,
O(0) => \y_int_reg[11]_i_21_n_7\,
S(3) => \y_int[11]_i_45_n_0\,
S(2) => \y_int[11]_i_46_n_0\,
S(1) => \y_int[11]_i_47_n_0\,
S(0) => \y_int[11]_i_48_n_0\
);
\y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_49_n_0\,
CO(3) => \^y_int_reg[7]_0\(0),
CO(2) => \y_int_reg[11]_i_22_n_1\,
CO(1) => \y_int_reg[11]_i_22_n_2\,
CO(0) => \y_int_reg[11]_i_22_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_50_n_0\,
S(2) => \y_int[11]_i_51_n_0\,
S(1) => \y_int[11]_i_52_n_0\,
S(0) => \y_int[11]_i_53_n_0\
);
\y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_15_n_0\,
CO(3) => \y_int_reg[11]_i_28_n_0\,
CO(2) => \y_int_reg[11]_i_28_n_1\,
CO(1) => \y_int_reg[11]_i_28_n_2\,
CO(0) => \y_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(12 downto 9),
S(3) => \y_int[11]_i_58_n_0\,
S(2) => \y_int[11]_i_59_n_0\,
S(1) => \y_int[11]_i_60_n_0\,
S(0) => \y_int[11]_i_61_n_0\
);
\y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_33_n_0\,
CO(2) => \y_int_reg[11]_i_33_n_1\,
CO(1) => \y_int_reg[11]_i_33_n_2\,
CO(0) => \y_int_reg[11]_i_33_n_3\,
CYINIT => \y_int[11]_i_62_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(4 downto 1),
S(3) => \y_int[11]_i_63_n_0\,
S(2) => \y_int[11]_i_64_n_0\,
S(1) => \y_int[11]_i_65_n_0\,
S(0) => \y_int[11]_i_66_n_0\
);
\y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_24_n_0\,
CO(3) => \y_int_reg[11]_i_38_n_0\,
CO(2) => \y_int_reg[11]_i_38_n_1\,
CO(1) => \y_int_reg[11]_i_38_n_2\,
CO(0) => \y_int_reg[11]_i_38_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_38_n_4\,
O(2) => \y_int_reg[11]_i_38_n_5\,
O(1) => \y_int_reg[11]_i_38_n_6\,
O(0) => \y_int_reg[11]_i_38_n_7\,
S(3) => \y_int[11]_i_67_n_0\,
S(2) => \y_int[11]_i_68_n_0\,
S(1) => \y_int[11]_i_69_n_0\,
S(0) => \y_int[11]_i_70_n_0\
);
\y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_39_n_0\,
CO(2) => \y_int_reg[11]_i_39_n_1\,
CO(1) => \y_int_reg[11]_i_39_n_2\,
CO(0) => \y_int_reg[11]_i_39_n_3\,
CYINIT => \y_int[11]_i_71_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(4 downto 1),
S(3) => \y_int[11]_i_72_n_0\,
S(2) => \y_int[11]_i_73_n_0\,
S(1) => \y_int[11]_i_74_n_0\,
S(0) => \y_int[11]_i_75_n_0\
);
\y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_35_n_0\,
CO(3) => \y_int_reg[11]_i_44_n_0\,
CO(2) => \y_int_reg[11]_i_44_n_1\,
CO(1) => \y_int_reg[11]_i_44_n_2\,
CO(0) => \y_int_reg[11]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_44_n_4\,
O(2) => \y_int_reg[11]_i_44_n_5\,
O(1) => \y_int_reg[11]_i_44_n_6\,
O(0) => \y_int_reg[11]_i_44_n_7\,
S(3) => \y_int[11]_i_76_n_0\,
S(2) => \y_int[11]_i_77_n_0\,
S(1) => \y_int[11]_i_78_n_0\,
S(0) => \y_int[11]_i_79_n_0\
);
\y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_80_n_0\,
CO(3) => \y_int_reg[11]_i_49_n_0\,
CO(2) => \y_int_reg[11]_i_49_n_1\,
CO(1) => \y_int_reg[11]_i_49_n_2\,
CO(0) => \y_int_reg[11]_i_49_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \^y_int_reg[23]_0\(0),
DI(1) => \^y_int_reg[23]_0\(0),
DI(0) => \^y_int_reg[23]_0\(0),
O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_81_n_0\,
S(2) => \y_int[11]_i_82_n_0\,
S(1) => \y_int[11]_i_83_n_0\,
S(0) => \y_int[11]_i_84_n_0\
);
\y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_85_n_0\,
CO(3) => \y_int_reg[11]_i_80_n_0\,
CO(2) => \y_int_reg[11]_i_80_n_1\,
CO(1) => \y_int_reg[11]_i_80_n_2\,
CO(0) => \y_int_reg[11]_i_80_n_3\,
CYINIT => '0',
DI(3) => \^y_int_reg[23]_0\(0),
DI(2) => \y_int[11]_i_86_n_0\,
DI(1) => \y_int[11]_i_87_n_0\,
DI(0) => \y_int[11]_i_88_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_89_n_0\,
S(2) => \y_int[11]_i_90_n_0\,
S(1) => \y_int[11]_i_91_n_0\,
S(0) => \y_int[11]_i_92_n_0\
);
\y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[11]_i_85_n_0\,
CO(2) => \y_int_reg[11]_i_85_n_1\,
CO(1) => \y_int_reg[11]_i_85_n_2\,
CO(0) => \y_int_reg[11]_i_85_n_3\,
CYINIT => '1',
DI(3) => \y_int[11]_i_93_n_0\,
DI(2) => \y_int[11]_i_94_n_0\,
DI(1) => \y_int[11]_i_95_n_0\,
DI(0) => \y_int[11]_i_96_n_0\,
O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[11]_i_97_n_0\,
S(2) => \y_int[11]_i_98_n_0\,
S(1) => \y_int[11]_i_99_n_0\,
S(0) => \y_int[11]_i_100_n_0\
);
\y_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_7\,
Q => \y_int_reg__0\(12),
R => '0'
);
\y_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_6\,
Q => \y_int_reg__0\(13),
R => '0'
);
\y_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_5\,
Q => \y_int_reg__0\(14),
R => '0'
);
\y_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[15]_i_1_n_4\,
Q => \y_int_reg__0\(15),
R => '0'
);
\y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_1_n_0\,
CO(3) => \y_int_reg[15]_i_1_n_0\,
CO(2) => \y_int_reg[15]_i_1_n_1\,
CO(1) => \y_int_reg[15]_i_1_n_2\,
CO(0) => \y_int_reg[15]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[15]_i_2_n_0\,
DI(2) => \y_int[15]_i_3_n_0\,
DI(1) => \y_int[15]_i_4_n_0\,
DI(0) => \y_int[15]_i_5_n_0\,
O(3) => \y_int_reg[15]_i_1_n_4\,
O(2) => \y_int_reg[15]_i_1_n_5\,
O(1) => \y_int_reg[15]_i_1_n_6\,
O(0) => \y_int_reg[15]_i_1_n_7\,
S(3) => \y_int[15]_i_6_n_0\,
S(2) => \y_int[15]_i_7_n_0\,
S(1) => \y_int[15]_i_8_n_0\,
S(0) => \y_int[15]_i_9_n_0\
);
\y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_14_n_0\,
CO(3) => \y_int_reg[15]_i_14_n_0\,
CO(2) => \y_int_reg[15]_i_14_n_1\,
CO(1) => \y_int_reg[15]_i_14_n_2\,
CO(0) => \y_int_reg[15]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(20 downto 17),
S(3) => \y_int[15]_i_25_n_0\,
S(2) => \y_int[15]_i_26_n_0\,
S(1) => \y_int[15]_i_27_n_0\,
S(0) => \y_int[15]_i_28_n_0\
);
\y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_15_n_0\,
CO(3) => \y_int_reg[15]_i_15_n_0\,
CO(2) => \y_int_reg[15]_i_15_n_1\,
CO(1) => \y_int_reg[15]_i_15_n_2\,
CO(0) => \y_int_reg[15]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(12 downto 9),
S(3) => \y_int[15]_i_29_n_0\,
S(2) => \y_int[15]_i_30_n_0\,
S(1) => \y_int[15]_i_31_n_0\,
S(0) => \y_int[15]_i_32_n_0\
);
\y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_38_n_0\,
CO(3) => \y_int_reg[19]_1\(0),
CO(2) => \y_int_reg[15]_i_33_n_1\,
CO(1) => \y_int_reg[15]_i_33_n_2\,
CO(0) => \y_int_reg[15]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_33_n_4\,
O(2) => \y_int_reg[15]_i_33_n_5\,
O(1) => \y_int_reg[15]_i_33_n_6\,
O(0) => \y_int_reg[15]_i_33_n_7\,
S(3) => \y_int[15]_i_40_n_0\,
S(2) => \y_int[15]_i_41_n_0\,
S(1) => \y_int[15]_i_42_n_0\,
S(0) => \y_int[15]_i_43_n_0\
);
\y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_21_n_0\,
CO(3) => \y_int_reg[15]_i_35_n_0\,
CO(2) => \y_int_reg[15]_i_35_n_1\,
CO(1) => \y_int_reg[15]_i_35_n_2\,
CO(0) => \y_int_reg[15]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0),
S(3) => \y_int[15]_i_48_n_0\,
S(2) => \y_int[15]_i_49_n_0\,
S(1) => \y_int[15]_i_50_n_0\,
S(0) => \y_int[15]_i_51_n_0\
);
\y_int_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_7\,
Q => \y_int_reg__0\(16),
R => '0'
);
\y_int_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_6\,
Q => \y_int_reg__0\(17),
R => '0'
);
\y_int_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_5\,
Q => \y_int_reg__0\(18),
R => '0'
);
\y_int_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[19]_i_1_n_4\,
Q => \y_int_reg__0\(19),
R => '0'
);
\y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_1_n_0\,
CO(3) => \y_int_reg[19]_i_1_n_0\,
CO(2) => \y_int_reg[19]_i_1_n_1\,
CO(1) => \y_int_reg[19]_i_1_n_2\,
CO(0) => \y_int_reg[19]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[19]_i_2_n_0\,
DI(2) => \y_int[19]_i_3_n_0\,
DI(1) => \y_int[19]_i_4_n_0\,
DI(0) => \y_int[19]_i_5_n_0\,
O(3) => \y_int_reg[19]_i_1_n_4\,
O(2) => \y_int_reg[19]_i_1_n_5\,
O(1) => \y_int_reg[19]_i_1_n_6\,
O(0) => \y_int_reg[19]_i_1_n_7\,
S(3) => \y_int[19]_i_6_n_0\,
S(2) => \y_int[19]_i_7_n_0\,
S(1) => \y_int[19]_i_8_n_0\,
S(0) => \y_int[19]_i_9_n_0\
);
\y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_14_n_0\,
CO(3) => \y_int_reg[19]_i_14_n_0\,
CO(2) => \y_int_reg[19]_i_14_n_1\,
CO(1) => \y_int_reg[19]_i_14_n_2\,
CO(0) => \y_int_reg[19]_i_14_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(24 downto 21),
S(3) => \y_int[19]_i_25_n_0\,
S(2) => \y_int[19]_i_26_n_0\,
S(1) => \y_int[19]_i_27_n_0\,
S(0) => \y_int[19]_i_28_n_0\
);
\y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_15_n_0\,
CO(3) => \y_int_reg[19]_i_15_n_0\,
CO(2) => \y_int_reg[19]_i_15_n_1\,
CO(1) => \y_int_reg[19]_i_15_n_2\,
CO(0) => \y_int_reg[19]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(16 downto 13),
S(3) => \y_int[19]_i_29_n_0\,
S(2) => \y_int[19]_i_30_n_0\,
S(1) => \y_int[19]_i_31_n_0\,
S(0) => \y_int[19]_i_32_n_0\
);
\y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_35_n_0\,
CO(3) => \y_int_reg[19]_i_35_n_0\,
CO(2) => \y_int_reg[19]_i_35_n_1\,
CO(1) => \y_int_reg[19]_i_35_n_2\,
CO(0) => \y_int_reg[19]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0),
S(3) => \y_int[19]_i_48_n_0\,
S(2) => \y_int[19]_i_49_n_0\,
S(1) => \y_int[19]_i_50_n_0\,
S(0) => \y_int[19]_i_51_n_0\
);
\y_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_6\,
Q => \y_int_reg_n_0_[1]\,
R => '0'
);
\y_int_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_7\,
Q => \y_int_reg__0\(20),
R => '0'
);
\y_int_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_6\,
Q => \y_int_reg__0\(21),
R => '0'
);
\y_int_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_5\,
Q => \y_int_reg__0\(22),
R => '0'
);
\y_int_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[23]_i_1_n_4\,
Q => \y_int_reg__0\(23),
R => '0'
);
\y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_1_n_0\,
CO(3) => \y_int_reg[23]_i_1_n_0\,
CO(2) => \y_int_reg[23]_i_1_n_1\,
CO(1) => \y_int_reg[23]_i_1_n_2\,
CO(0) => \y_int_reg[23]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_2_n_0\,
DI(2) => \y_int[23]_i_3_n_0\,
DI(1) => \y_int[23]_i_4_n_0\,
DI(0) => \y_int[23]_i_5_n_0\,
O(3) => \y_int_reg[23]_i_1_n_4\,
O(2) => \y_int_reg[23]_i_1_n_5\,
O(1) => \y_int_reg[23]_i_1_n_6\,
O(0) => \y_int_reg[23]_i_1_n_7\,
S(3) => \y_int[23]_i_6_n_0\,
S(2) => \y_int[23]_i_7_n_0\,
S(1) => \y_int[23]_i_8_n_0\,
S(0) => \y_int[23]_i_9_n_0\
);
\y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_25_n_0\,
CO(3) => y_int_reg6,
CO(2) => \y_int_reg[23]_i_10_n_1\,
CO(1) => \y_int_reg[23]_i_10_n_2\,
CO(0) => \y_int_reg[23]_i_10_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_26_n_0\,
S(2) => \y_int[23]_i_27_n_0\,
S(1) => \y_int[23]_i_28_n_0\,
S(0) => \y_int[23]_i_29_n_0\
);
\y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_16_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg5(30 downto 29),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_30_n_0\,
S(0) => \y_int[23]_i_31_n_0\
);
\y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_14_n_0\,
CO(3) => \y_int_reg[23]_i_16_n_0\,
CO(2) => \y_int_reg[23]_i_16_n_1\,
CO(1) => \y_int_reg[23]_i_16_n_2\,
CO(0) => \y_int_reg[23]_i_16_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg5(28 downto 25),
S(3) => \y_int[23]_i_36_n_0\,
S(2) => \y_int[23]_i_37_n_0\,
S(1) => \y_int[23]_i_38_n_0\,
S(0) => \y_int[23]_i_39_n_0\
);
\y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_15_n_0\,
CO(3) => \y_int_reg[23]_i_17_n_0\,
CO(2) => \y_int_reg[23]_i_17_n_1\,
CO(1) => \y_int_reg[23]_i_17_n_2\,
CO(0) => \y_int_reg[23]_i_17_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg3(20 downto 17),
S(3) => \y_int[23]_i_40_n_0\,
S(2) => \y_int[23]_i_41_n_0\,
S(1) => \y_int[23]_i_42_n_0\,
S(0) => \y_int[23]_i_43_n_0\
);
\y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_45_n_0\,
CO(3) => \y_int_reg[23]_i_25_n_0\,
CO(2) => \y_int_reg[23]_i_25_n_1\,
CO(1) => \y_int_reg[23]_i_25_n_2\,
CO(0) => \y_int_reg[23]_i_25_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_8_n_5\,
DI(2) => \y_int_reg[31]_i_8_n_5\,
DI(1) => \y_int_reg[31]_i_8_n_5\,
DI(0) => \y_int_reg[31]_i_8_n_5\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_46_n_0\,
S(2) => \y_int[23]_i_47_n_0\,
S(1) => \y_int[23]_i_48_n_0\,
S(0) => \y_int[23]_i_49_n_0\
);
\y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_51_n_0\,
CO(3) => \^y_int_reg[3]_1\(0),
CO(2) => \y_int_reg[23]_i_33_n_1\,
CO(1) => \y_int_reg[23]_i_33_n_2\,
CO(0) => \y_int_reg[23]_i_33_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \rgb888[8]_21\(2),
O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_52_n_0\,
S(2) => \y_int[23]_i_53_n_0\,
S(1) => \y_int[23]_i_54_n_0\,
S(0) => \y_int[23]_i_55_n_0\
);
\y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_44_n_0\,
CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_int_reg[23]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0),
S(3 downto 2) => B"00",
S(1) => \y_int[23]_i_56_n_0\,
S(0) => \y_int[23]_i_57_n_0\
);
\y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_35_n_0\,
CO(3) => \y_int_reg[23]_i_44_n_0\,
CO(2) => \y_int_reg[23]_i_44_n_1\,
CO(1) => \y_int_reg[23]_i_44_n_2\,
CO(0) => \y_int_reg[23]_i_44_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0),
S(3) => \y_int[23]_i_62_n_0\,
S(2) => \y_int[23]_i_63_n_0\,
S(1) => \y_int[23]_i_64_n_0\,
S(0) => \y_int[23]_i_65_n_0\
);
\y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_66_n_0\,
CO(3) => \y_int_reg[23]_i_45_n_0\,
CO(2) => \y_int_reg[23]_i_45_n_1\,
CO(1) => \y_int_reg[23]_i_45_n_2\,
CO(0) => \y_int_reg[23]_i_45_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_67_n_0\,
DI(2) => \y_int[23]_i_68_n_0\,
DI(1) => \y_int[23]_i_69_n_0\,
DI(0) => \y_int[23]_i_70_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_71_n_0\,
S(2) => \y_int[23]_i_72_n_0\,
S(1) => \y_int[23]_i_73_n_0\,
S(0) => \y_int[23]_i_74_n_0\
);
\y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_75_n_0\,
CO(3) => \y_int_reg[23]_i_51_n_0\,
CO(2) => \y_int_reg[23]_i_51_n_1\,
CO(1) => \y_int_reg[23]_i_51_n_2\,
CO(0) => \y_int_reg[23]_i_51_n_3\,
CYINIT => '0',
DI(3) => \rgb888[8]_21\(2),
DI(2) => \rgb888[8]_21\(2),
DI(1) => \rgb888[8]_21\(2),
DI(0) => \y_int[23]_i_76_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_77_n_0\,
S(2) => \y_int[23]_i_78_n_0\,
S(1) => \y_int[23]_i_79_n_0\,
S(0) => \y_int[23]_i_80_n_0\
);
\y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_66_n_0\,
CO(2) => \y_int_reg[23]_i_66_n_1\,
CO(1) => \y_int_reg[23]_i_66_n_2\,
CO(0) => \y_int_reg[23]_i_66_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_81_n_0\,
DI(2) => \y_int[23]_i_82_n_0\,
DI(1) => \y_int[23]_i_83_n_0\,
DI(0) => \y_int[23]_i_84_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_85_n_0\,
S(2) => \y_int[23]_i_86_n_0\,
S(1) => \y_int[23]_i_87_n_0\,
S(0) => \y_int[23]_i_88_n_0\
);
\y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_89_n_0\,
CO(3) => \y_int_reg[23]_i_75_n_0\,
CO(2) => \y_int_reg[23]_i_75_n_1\,
CO(1) => \y_int_reg[23]_i_75_n_2\,
CO(0) => \y_int_reg[23]_i_75_n_3\,
CYINIT => '0',
DI(3) => \y_int[23]_i_90_n_0\,
DI(2) => \y_int[23]_i_91_n_0\,
DI(1) => \y_int[23]_i_92_n_0\,
DI(0) => \y_int[23]_i_93_n_0\,
O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_94_n_0\,
S(2) => \y_int[23]_i_95_n_0\,
S(1) => \y_int[23]_i_96_n_0\,
S(0) => \y_int[23]_i_97_n_0\
);
\y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_i_89_n_0\,
CO(2) => \y_int_reg[23]_i_89_n_1\,
CO(1) => \y_int_reg[23]_i_89_n_2\,
CO(0) => \y_int_reg[23]_i_89_n_3\,
CYINIT => '1',
DI(3) => \y_int[23]_i_98_n_0\,
DI(2) => \y_int[23]_i_99_n_0\,
DI(1) => \y_int[23]_i_100_n_0\,
DI(0) => rgb888(8),
O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[23]_i_101_n_0\,
S(2) => \y_int[23]_i_102_n_0\,
S(1) => \y_int[23]_i_103_n_0\,
S(0) => \y_int[23]_i_104_n_0\
);
\y_int_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_7\,
Q => \y_int_reg__0\(24),
R => '0'
);
\y_int_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_6\,
Q => \y_int_reg__0\(25),
R => '0'
);
\y_int_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_5\,
Q => \y_int_reg__0\(26),
R => '0'
);
\y_int_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[27]_i_1_n_4\,
Q => \y_int_reg__0\(27),
R => '0'
);
\y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_1_n_0\,
CO(3) => \y_int_reg[27]_i_1_n_0\,
CO(2) => \y_int_reg[27]_i_1_n_1\,
CO(1) => \y_int_reg[27]_i_1_n_2\,
CO(0) => \y_int_reg[27]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_2_n_0\,
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[27]_i_1_n_4\,
O(2) => \y_int_reg[27]_i_1_n_5\,
O(1) => \y_int_reg[27]_i_1_n_6\,
O(0) => \y_int_reg[27]_i_1_n_7\,
S(3) => \y_int[27]_i_2_n_0\,
S(2) => \y_int[27]_i_3_n_0\,
S(1) => \y_int[27]_i_4_n_0\,
S(0) => \y_int[27]_i_5_n_0\
);
\y_int_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_7\,
Q => \y_int_reg__0\(28),
R => '0'
);
\y_int_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_6\,
Q => \y_int_reg__0\(29),
R => '0'
);
\y_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_5\,
Q => \y_int_reg_n_0_[2]\,
R => '0'
);
\y_int_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_5\,
Q => \y_int_reg__0\(30),
R => '0'
);
\y_int_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[31]_i_1_n_4\,
Q => \y_int_reg__0\(31),
R => '0'
);
\y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[27]_i_1_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_1_n_1\,
CO(1) => \y_int_reg[31]_i_1_n_2\,
CO(0) => \y_int_reg[31]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \y_int[31]_i_2_n_0\,
DI(1) => \y_int[31]_i_2_n_0\,
DI(0) => \y_int[31]_i_2_n_0\,
O(3) => \y_int_reg[31]_i_1_n_4\,
O(2) => \y_int_reg[31]_i_1_n_5\,
O(1) => \y_int_reg[31]_i_1_n_6\,
O(0) => \y_int_reg[31]_i_1_n_7\,
S(3) => \y_int[31]_i_3_n_0\,
S(2) => \y_int[31]_i_4_n_0\,
S(1) => \y_int[31]_i_5_n_0\,
S(0) => \y_int[31]_i_6_n_0\
);
\y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_30_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_11_n_1\,
CO(1) => \y_int_reg[31]_i_11_n_2\,
CO(0) => \y_int_reg[31]_i_11_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \rgb888[0]_9\(1),
DI(0) => \y_int[31]_i_32_n_0\,
O(3) => \^y_int_reg[23]_0\(0),
O(2) => \y_int_reg[31]_i_11_n_5\,
O(1) => \y_int_reg[31]_i_11_n_6\,
O(0) => \y_int_reg[31]_i_11_n_7\,
S(3) => \y_int[31]_i_33_n_0\,
S(2) => \y_int[31]_i_34_n_0\,
S(1) => \y_int[31]_i_35_n_0\,
S(0) => \y_int[31]_i_36_n_0\
);
\y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_16_n_0\,
CO(3) => \y_int_reg[31]_i_16_n_0\,
CO(2) => \y_int_reg[31]_i_16_n_1\,
CO(1) => \y_int_reg[31]_i_16_n_2\,
CO(0) => \y_int_reg[31]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_40_n_0\,
DI(2) => \y_int[31]_i_41_n_0\,
DI(1) => \y_int[31]_i_42_n_0\,
DI(0) => \y_int[31]_i_43_n_0\,
O(3) => \y_int_reg[31]_i_16_n_4\,
O(2) => \y_int_reg[31]_i_16_n_5\,
O(1) => \y_int_reg[31]_i_16_n_6\,
O(0) => \y_int_reg[31]_i_16_n_7\,
S(3) => \y_int[31]_i_44_n_0\,
S(2) => \y_int[31]_i_45_n_0\,
S(1) => \y_int[31]_i_46_n_0\,
S(0) => \y_int[31]_i_47_n_0\
);
\y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_62_n_0\,
CO(3) => \y_int_reg[31]_i_30_n_0\,
CO(2) => \y_int_reg[31]_i_30_n_1\,
CO(1) => \y_int_reg[31]_i_30_n_2\,
CO(0) => \y_int_reg[31]_i_30_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_63_n_0\,
DI(2) => \y_int[31]_i_64_n_0\,
DI(1) => \y_int[31]_i_65_n_0\,
DI(0) => \y_int[31]_i_66_n_0\,
O(3) => \y_int_reg[31]_i_30_n_4\,
O(2) => \y_int_reg[31]_i_30_n_5\,
O(1) => \y_int_reg[31]_i_30_n_6\,
O(0) => \y_int_reg[31]_i_30_n_7\,
S(3) => \y_int[31]_i_67_n_0\,
S(2) => \y_int[31]_i_68_n_0\,
S(1) => \y_int[31]_i_69_n_0\,
S(0) => \y_int[31]_i_70_n_0\
);
\y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_62_n_0\,
CO(2) => \y_int_reg[31]_i_62_n_1\,
CO(1) => \y_int_reg[31]_i_62_n_2\,
CO(0) => \y_int_reg[31]_i_62_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[31]_i_86_n_5\,
DI(2) => \y_int_reg[31]_i_87_n_7\,
DI(1) => \y_int_reg[31]_i_88_n_4\,
DI(0) => \y_int_reg[31]_i_88_n_5\,
O(3) => \y_int_reg[31]_i_62_n_4\,
O(2) => \y_int_reg[31]_i_62_n_5\,
O(1) => \y_int_reg[31]_i_62_n_6\,
O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_89_n_0\,
S(2) => \y_int[31]_i_90_n_0\,
S(1) => \y_int[31]_i_91_n_0\,
S(0) => \y_int[31]_i_92_n_0\
);
\y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_17_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_7_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_7_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg3(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_14_n_0\,
S(0) => \y_int[31]_i_15_n_0\
);
\y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_87_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_75_n_2\,
CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(7),
O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[31]_i_75_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[31]_i_101_n_0\
);
\y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_16_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_8_n_2\,
CO(0) => \y_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_int[31]_i_17_n_0\,
O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_8_n_5\,
O(1) => \y_int_reg[31]_i_8_n_6\,
O(0) => \y_int_reg[31]_i_8_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_18_n_0\,
S(1) => \y_int[31]_i_19_n_0\,
S(0) => \y_int[31]_i_20_n_0\
);
\y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[23]_3\(0),
CO(2) => \y_int_reg[31]_i_86_n_1\,
CO(1) => \y_int_reg[31]_i_86_n_2\,
CO(0) => \y_int_reg[31]_i_86_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_104_n_0\,
DI(2) => rgb888(2),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[31]_i_86_n_4\,
O(2) => \y_int_reg[31]_i_86_n_5\,
O(1) => \y_int_reg[31]_i_86_n_6\,
O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_105_n_0\,
S(2) => \y_int[31]_i_106_n_0\,
S(1) => \y_int[31]_i_107_n_0\,
S(0) => \y_int[31]_i_108_n_0\
);
\y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_88_n_0\,
CO(3) => \y_int_reg[31]_i_87_n_0\,
CO(2) => \y_int_reg[31]_i_87_n_1\,
CO(1) => \y_int_reg[31]_i_87_n_2\,
CO(0) => \y_int_reg[31]_i_87_n_3\,
CYINIT => '0',
DI(3) => rgb888(6),
DI(2 downto 0) => rgb888(7 downto 5),
O(3) => \y_int_reg[31]_i_87_n_4\,
O(2) => \y_int_reg[31]_i_87_n_5\,
O(1) => \y_int_reg[31]_i_87_n_6\,
O(0) => \y_int_reg[31]_i_87_n_7\,
S(3) => \y_int[31]_i_109_n_0\,
S(2) => \y_int[31]_i_110_n_0\,
S(1) => \y_int[31]_i_111_n_0\,
S(0) => \y_int[31]_i_112_n_0\
);
\y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[31]_i_88_n_0\,
CO(2) => \y_int_reg[31]_i_88_n_1\,
CO(1) => \y_int_reg[31]_i_88_n_2\,
CO(0) => \y_int_reg[31]_i_88_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(4 downto 2),
DI(0) => '0',
O(3) => \y_int_reg[31]_i_88_n_4\,
O(2) => \y_int_reg[31]_i_88_n_5\,
O(1) => \y_int_reg[31]_i_88_n_6\,
O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0),
S(3) => \y_int[31]_i_113_n_0\,
S(2) => \y_int[31]_i_114_n_0\,
S(1) => \y_int[31]_i_115_n_0\,
S(0) => \y_int[31]_i_116_n_0\
);
\y_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[3]_i_1_n_4\,
Q => \y_int_reg_n_0_[3]\,
R => '0'
);
\y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_1_n_0\,
CO(2) => \y_int_reg[3]_i_1_n_1\,
CO(1) => \y_int_reg[3]_i_1_n_2\,
CO(0) => \y_int_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_2_n_0\,
DI(2) => \y_int[3]_i_3_n_0\,
DI(1) => \y_int[3]_i_4_n_0\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_1_n_4\,
O(2) => \y_int_reg[3]_i_1_n_5\,
O(1) => \y_int_reg[3]_i_1_n_6\,
O(0) => \y_int_reg[3]_i_1_n_7\,
S(3) => \y_int[3]_i_5_n_0\,
S(2) => \y_int[3]_i_6_n_0\,
S(1) => \y_int[3]_i_7_n_0\,
S(0) => \y_int[3]_i_8_n_0\
);
\y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_21_n_0\,
CO(3) => \y_int_reg[3]_i_15_n_0\,
CO(2) => \y_int_reg[3]_i_15_n_1\,
CO(1) => \y_int_reg[3]_i_15_n_2\,
CO(0) => \y_int_reg[3]_i_15_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => y_int_reg5(8),
O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_22_n_0\,
S(2) => \y_int[3]_i_23_n_0\,
S(1) => \y_int[3]_i_24_n_0\,
S(0) => \y_int[3]_i_25_n_0\
);
\y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_26_n_0\,
CO(3) => \y_int_reg[3]_i_16_n_0\,
CO(2) => \y_int_reg[3]_i_16_n_1\,
CO(1) => \y_int_reg[3]_i_16_n_2\,
CO(0) => \y_int_reg[3]_i_16_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_27_n_0\,
DI(2) => \y_int[3]_i_28_n_0\,
DI(1) => \y_int[3]_i_29_n_0\,
DI(0) => \y_int_reg[3]_i_30_n_6\,
O(3) => \y_int_reg[3]_i_16_n_4\,
O(2) => \y_int_reg[3]_i_16_n_5\,
O(1) => \y_int_reg[3]_i_16_n_6\,
O(0) => \y_int_reg[3]_i_16_n_7\,
S(3) => \y_int[3]_i_31_n_0\,
S(2) => \y_int[3]_i_32_n_0\,
S(1) => \y_int[3]_i_33_n_0\,
S(0) => \y_int[3]_i_34_n_0\
);
\y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_21_n_0\,
CO(2) => \y_int_reg[3]_i_21_n_1\,
CO(1) => \y_int_reg[3]_i_21_n_2\,
CO(0) => \y_int_reg[3]_i_21_n_3\,
CYINIT => \y_int[3]_i_50_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_51_n_0\,
S(2) => \y_int[3]_i_52_n_0\,
S(1) => \y_int[3]_i_53_n_0\,
S(0) => \y_int[3]_i_54_n_0\
);
\y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_26_n_0\,
CO(2) => \y_int_reg[3]_i_26_n_1\,
CO(1) => \y_int_reg[3]_i_26_n_2\,
CO(0) => \y_int_reg[3]_i_26_n_3\,
CYINIT => '0',
DI(3) => \y_int_reg[3]_i_30_n_7\,
DI(2) => \y_int_reg[3]_i_55_n_4\,
DI(1) => \y_int_reg[3]_i_55_n_5\,
DI(0) => '0',
O(3) => \y_int_reg[3]_i_26_n_4\,
O(2) => \y_int_reg[3]_i_26_n_5\,
O(1) => \y_int_reg[3]_i_26_n_6\,
O(0) => \y_int_reg[3]_i_26_n_7\,
S(3) => \y_int[3]_i_56_n_0\,
S(2) => \y_int[3]_i_57_n_0\,
S(1) => \y_int[3]_i_58_n_0\,
S(0) => \y_int[3]_i_59_n_0\
);
\y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_55_n_0\,
CO(3) => \y_int_reg[3]_i_30_n_0\,
CO(2) => \y_int_reg[3]_i_30_n_1\,
CO(1) => \y_int_reg[3]_i_30_n_2\,
CO(0) => \y_int_reg[3]_i_30_n_3\,
CYINIT => '0',
DI(3) => rgb888(22),
DI(2 downto 0) => rgb888(23 downto 21),
O(3) => \y_int_reg[3]_i_30_n_4\,
O(2) => \y_int_reg[3]_i_30_n_5\,
O(1) => \y_int_reg[3]_i_30_n_6\,
O(0) => \y_int_reg[3]_i_30_n_7\,
S(3) => \y_int[3]_i_60_n_0\,
S(2) => \y_int[3]_i_61_n_0\,
S(1) => \y_int[3]_i_62_n_0\,
S(0) => \y_int[3]_i_63_n_0\
);
\y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_65_n_0\,
CO(3) => \y_int_reg[3]_i_35_n_0\,
CO(2) => \y_int_reg[3]_i_35_n_1\,
CO(1) => \y_int_reg[3]_i_35_n_2\,
CO(0) => \y_int_reg[3]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_35_n_4\,
O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0),
S(3) => \y_int[3]_i_66_n_0\,
S(2) => \y_int[3]_i_67_n_0\,
S(1) => \y_int[3]_i_68_n_0\,
S(0) => \y_int[3]_i_69_n_0\
);
\y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_2\(0),
CO(2) => \y_int_reg[3]_i_36_n_1\,
CO(1) => \y_int_reg[3]_i_36_n_2\,
CO(0) => \y_int_reg[3]_i_36_n_3\,
CYINIT => '0',
DI(3 downto 2) => \rgb888[8]_32\(1 downto 0),
DI(1) => \rgb888[8]_19\(2),
DI(0) => '0',
O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0),
S(3) => \y_int[3]_i_71_n_0\,
S(2) => \y_int[3]_i_72_n_0\,
S(1) => \y_int[3]_i_73_n_0\,
S(0) => \y_int[3]_i_74_n_0\
);
\y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_55_n_0\,
CO(2) => \y_int_reg[3]_i_55_n_1\,
CO(1) => \y_int_reg[3]_i_55_n_2\,
CO(0) => \y_int_reg[3]_i_55_n_3\,
CYINIT => '0',
DI(3 downto 1) => rgb888(20 downto 18),
DI(0) => '0',
O(3) => \y_int_reg[3]_i_55_n_4\,
O(2) => \y_int_reg[3]_i_55_n_5\,
O(1) => \y_int_reg[3]_i_55_n_6\,
O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_84_n_0\,
S(2) => \y_int[3]_i_85_n_0\,
S(1) => \y_int[3]_i_86_n_0\,
S(0) => \y_int[3]_i_87_n_0\
);
\y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_30_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[3]_i_64_n_2\,
CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => rgb888(23),
O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[3]_i_64_n_7\,
S(3 downto 1) => B"001",
S(0) => \y_int[3]_i_88_n_0\
);
\y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_65_n_0\,
CO(2) => \y_int_reg[3]_i_65_n_1\,
CO(1) => \y_int_reg[3]_i_65_n_2\,
CO(0) => \y_int_reg[3]_i_65_n_3\,
CYINIT => \cr_int[3]_i_80_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_89_n_0\,
S(2) => \y_int[3]_i_90_n_0\,
S(1) => \y_int[3]_i_91_n_0\,
S(0) => \y_int[3]_i_92_n_0\
);
\y_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_7\,
Q => \y_int_reg_n_0_[4]\,
R => '0'
);
\y_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_6\,
Q => \y_int_reg_n_0_[5]\,
R => '0'
);
\y_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_5\,
Q => \y_int_reg_n_0_[6]\,
R => '0'
);
\y_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[7]_i_1_n_4\,
Q => \y_int_reg_n_0_[7]\,
R => '0'
);
\y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_1_n_0\,
CO(3) => \y_int_reg[7]_i_1_n_0\,
CO(2) => \y_int_reg[7]_i_1_n_1\,
CO(1) => \y_int_reg[7]_i_1_n_2\,
CO(0) => \y_int_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y_int[7]_i_2_n_0\,
DI(2) => \y_int[7]_i_3_n_0\,
DI(1) => \y_int[7]_i_4_n_0\,
DI(0) => \y_int[7]_i_5_n_0\,
O(3) => \y_int_reg[7]_i_1_n_4\,
O(2) => \y_int_reg[7]_i_1_n_5\,
O(1) => \y_int_reg[7]_i_1_n_6\,
O(0) => \y_int_reg[7]_i_1_n_7\,
S(3) => \y_int[7]_i_6_n_0\,
S(2) => \y_int[7]_i_7_n_0\,
S(1) => \y_int[7]_i_8_n_0\,
S(0) => \y_int[7]_i_9_n_0\
);
\y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[7]_i_24_n_0\,
CO(2) => \y_int_reg[7]_i_24_n_1\,
CO(1) => \y_int_reg[7]_i_24_n_2\,
CO(0) => \y_int_reg[7]_i_24_n_3\,
CYINIT => \y_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_24_n_4\,
O(2) => \y_int_reg[7]_i_24_n_5\,
O(1) => \y_int_reg[7]_i_24_n_6\,
O(0) => \y_int_reg[7]_i_24_n_7\,
S(3) => \y_int[7]_i_30_n_0\,
S(2) => \y_int[7]_i_31_n_0\,
S(1) => \y_int[7]_i_32_n_0\,
S(0) => \y_int[7]_i_33_n_0\
);
\y_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_7\,
Q => \y_int_reg__0\(8),
R => '0'
);
\y_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \y_int_reg[11]_i_1_n_6\,
Q => \y_int_reg__0\(9),
R => '0'
);
\y_reg[0]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[0]_i_1_n_0\,
Q => y(0),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[1]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[1]_i_1_n_0\,
Q => y(1),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[2]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[2]_i_1_n_0\,
Q => y(2),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[3]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[3]_i_1_n_0\,
Q => y(3),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[4]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[4]_i_1_n_0\,
Q => y(4),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[5]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[5]_i_1_n_0\,
Q => y(5),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[6]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[6]_i_1_n_0\,
Q => y(6),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]\: unisim.vcomponents.FDSE
port map (
C => cb_regn_0_0,
CE => '1',
D => \y[7]_i_2_n_0\,
Q => y(7),
S => \y_reg[7]_i_1_n_0\
);
\y_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_3_n_0\,
CO(3) => \y_reg[7]_i_1_n_0\,
CO(2) => \y_reg[7]_i_1_n_1\,
CO(1) => \y_reg[7]_i_1_n_2\,
CO(0) => \y_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_4_n_0\,
DI(2) => \y[7]_i_5_n_0\,
DI(1) => \y[7]_i_6_n_0\,
DI(0) => \y[7]_i_7_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_8_n_0\,
S(2) => \y[7]_i_9_n_0\,
S(1) => \y[7]_i_10_n_0\,
S(0) => \y[7]_i_11_n_0\
);
\y_reg[7]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_reg[7]_i_12_n_0\,
CO(2) => \y_reg[7]_i_12_n_1\,
CO(1) => \y_reg[7]_i_12_n_2\,
CO(0) => \y_reg[7]_i_12_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_21_n_0\,
DI(2) => \y[7]_i_22_n_0\,
DI(1) => \y[7]_i_23_n_0\,
DI(0) => \y[7]_i_24_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_25_n_0\,
S(2) => \y[7]_i_26_n_0\,
S(1) => \y[7]_i_27_n_0\,
S(0) => \y[7]_i_28_n_0\
);
\y_reg[7]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \y_reg[7]_i_12_n_0\,
CO(3) => \y_reg[7]_i_3_n_0\,
CO(2) => \y_reg[7]_i_3_n_1\,
CO(1) => \y_reg[7]_i_3_n_2\,
CO(0) => \y_reg[7]_i_3_n_3\,
CYINIT => '0',
DI(3) => \y[7]_i_13_n_0\,
DI(2) => \y[7]_i_14_n_0\,
DI(1) => \y[7]_i_15_n_0\,
DI(0) => \y[7]_i_16_n_0\,
O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \y[7]_i_17_n_0\,
S(2) => \y[7]_i_18_n_0\,
S(1) => \y[7]_i_19_n_0\,
S(0) => \y[7]_i_20_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4";
end system_zed_hdmi_0_0;
architecture STRUCTURE of system_zed_hdmi_0_0 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_10 : STD_LOGIC;
signal U0_n_11 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal U0_n_19 : STD_LOGIC;
signal U0_n_20 : STD_LOGIC;
signal U0_n_21 : STD_LOGIC;
signal U0_n_22 : STD_LOGIC;
signal U0_n_23 : STD_LOGIC;
signal U0_n_24 : STD_LOGIC;
signal U0_n_25 : STD_LOGIC;
signal U0_n_26 : STD_LOGIC;
signal U0_n_27 : STD_LOGIC;
signal U0_n_28 : STD_LOGIC;
signal U0_n_29 : STD_LOGIC;
signal U0_n_30 : STD_LOGIC;
signal U0_n_31 : STD_LOGIC;
signal U0_n_32 : STD_LOGIC;
signal U0_n_33 : STD_LOGIC;
signal U0_n_34 : STD_LOGIC;
signal U0_n_35 : STD_LOGIC;
signal U0_n_36 : STD_LOGIC;
signal U0_n_37 : STD_LOGIC;
signal U0_n_38 : STD_LOGIC;
signal U0_n_39 : STD_LOGIC;
signal U0_n_4 : STD_LOGIC;
signal U0_n_40 : STD_LOGIC;
signal U0_n_41 : STD_LOGIC;
signal U0_n_42 : STD_LOGIC;
signal U0_n_43 : STD_LOGIC;
signal U0_n_44 : STD_LOGIC;
signal U0_n_45 : STD_LOGIC;
signal U0_n_46 : STD_LOGIC;
signal U0_n_47 : STD_LOGIC;
signal U0_n_48 : STD_LOGIC;
signal U0_n_49 : STD_LOGIC;
signal U0_n_5 : STD_LOGIC;
signal U0_n_50 : STD_LOGIC;
signal U0_n_51 : STD_LOGIC;
signal U0_n_52 : STD_LOGIC;
signal U0_n_53 : STD_LOGIC;
signal U0_n_54 : STD_LOGIC;
signal U0_n_55 : STD_LOGIC;
signal U0_n_56 : STD_LOGIC;
signal U0_n_57 : STD_LOGIC;
signal U0_n_58 : STD_LOGIC;
signal U0_n_59 : STD_LOGIC;
signal U0_n_6 : STD_LOGIC;
signal U0_n_60 : STD_LOGIC;
signal U0_n_61 : STD_LOGIC;
signal U0_n_62 : STD_LOGIC;
signal U0_n_63 : STD_LOGIC;
signal U0_n_64 : STD_LOGIC;
signal U0_n_65 : STD_LOGIC;
signal U0_n_66 : STD_LOGIC;
signal U0_n_67 : STD_LOGIC;
signal U0_n_68 : STD_LOGIC;
signal U0_n_69 : STD_LOGIC;
signal U0_n_7 : STD_LOGIC;
signal U0_n_70 : STD_LOGIC;
signal U0_n_71 : STD_LOGIC;
signal U0_n_72 : STD_LOGIC;
signal U0_n_73 : STD_LOGIC;
signal U0_n_74 : STD_LOGIC;
signal U0_n_75 : STD_LOGIC;
signal U0_n_76 : STD_LOGIC;
signal U0_n_77 : STD_LOGIC;
signal U0_n_78 : STD_LOGIC;
signal U0_n_79 : STD_LOGIC;
signal U0_n_8 : STD_LOGIC;
signal U0_n_80 : STD_LOGIC;
signal U0_n_81 : STD_LOGIC;
signal U0_n_9 : STD_LOGIC;
signal \cb_int[15]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[15]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[23]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_100_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_101_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_18_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_19_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_20_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_21_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_22_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_25_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_26_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_52_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_53_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_54_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_55_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_56_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_57_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_58_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_63_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_64_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_83_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_89_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_90_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_91_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_92_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_93_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_94_n_0\ : STD_LOGIC;
signal \cb_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_38_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_39_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_40_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_41_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_42_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_59_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_60_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_61_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_62_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_73_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_74_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_84_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_85_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_86_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_87_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_88_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_95_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_96_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_97_n_0\ : STD_LOGIC;
signal \cb_int[3]_i_98_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_34_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_35_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_36_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_37_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_43_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_44_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_45_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_46_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_47_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_48_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_49_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_50_n_0\ : STD_LOGIC;
signal \cb_int[7]_i_51_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC;
signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC;
signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC;
signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC;
signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC;
signal \cr_int[11]_i_61_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_62_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_63_n_0\ : STD_LOGIC;
signal \cr_int[11]_i_64_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_46_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_47_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_52_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_53_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_54_n_0\ : STD_LOGIC;
signal \cr_int[15]_i_55_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_42_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_43_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_44_n_0\ : STD_LOGIC;
signal \cr_int[19]_i_45_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_33_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_34_n_0\ : STD_LOGIC;
signal \cr_int[23]_i_35_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_104_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_105_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_106_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_107_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_28_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_65_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_66_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_67_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_68_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_98_n_0\ : STD_LOGIC;
signal \cr_int[31]_i_99_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_29_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_30_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_31_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_32_n_0\ : STD_LOGIC;
signal \cr_int[7]_i_33_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC;
signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC;
signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC;
signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC;
signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC;
signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC;
signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC;
signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \y_int[11]_i_54_n_0\ : STD_LOGIC;
signal \y_int[11]_i_55_n_0\ : STD_LOGIC;
signal \y_int[11]_i_56_n_0\ : STD_LOGIC;
signal \y_int[11]_i_57_n_0\ : STD_LOGIC;
signal \y_int[15]_i_36_n_0\ : STD_LOGIC;
signal \y_int[15]_i_37_n_0\ : STD_LOGIC;
signal \y_int[15]_i_38_n_0\ : STD_LOGIC;
signal \y_int[15]_i_39_n_0\ : STD_LOGIC;
signal \y_int[15]_i_44_n_0\ : STD_LOGIC;
signal \y_int[15]_i_45_n_0\ : STD_LOGIC;
signal \y_int[15]_i_46_n_0\ : STD_LOGIC;
signal \y_int[15]_i_47_n_0\ : STD_LOGIC;
signal \y_int[19]_i_36_n_0\ : STD_LOGIC;
signal \y_int[19]_i_37_n_0\ : STD_LOGIC;
signal \y_int[19]_i_38_n_0\ : STD_LOGIC;
signal \y_int[19]_i_39_n_0\ : STD_LOGIC;
signal \y_int[19]_i_40_n_0\ : STD_LOGIC;
signal \y_int[19]_i_41_n_0\ : STD_LOGIC;
signal \y_int[19]_i_42_n_0\ : STD_LOGIC;
signal \y_int[19]_i_43_n_0\ : STD_LOGIC;
signal \y_int[19]_i_44_n_0\ : STD_LOGIC;
signal \y_int[19]_i_45_n_0\ : STD_LOGIC;
signal \y_int[19]_i_46_n_0\ : STD_LOGIC;
signal \y_int[19]_i_47_n_0\ : STD_LOGIC;
signal \y_int[23]_i_50_n_0\ : STD_LOGIC;
signal \y_int[23]_i_58_n_0\ : STD_LOGIC;
signal \y_int[23]_i_59_n_0\ : STD_LOGIC;
signal \y_int[23]_i_60_n_0\ : STD_LOGIC;
signal \y_int[23]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_100_n_0\ : STD_LOGIC;
signal \y_int[31]_i_102_n_0\ : STD_LOGIC;
signal \y_int[31]_i_103_n_0\ : STD_LOGIC;
signal \y_int[31]_i_22_n_0\ : STD_LOGIC;
signal \y_int[31]_i_23_n_0\ : STD_LOGIC;
signal \y_int[31]_i_24_n_0\ : STD_LOGIC;
signal \y_int[31]_i_25_n_0\ : STD_LOGIC;
signal \y_int[31]_i_26_n_0\ : STD_LOGIC;
signal \y_int[31]_i_28_n_0\ : STD_LOGIC;
signal \y_int[31]_i_29_n_0\ : STD_LOGIC;
signal \y_int[31]_i_38_n_0\ : STD_LOGIC;
signal \y_int[31]_i_39_n_0\ : STD_LOGIC;
signal \y_int[31]_i_48_n_0\ : STD_LOGIC;
signal \y_int[31]_i_49_n_0\ : STD_LOGIC;
signal \y_int[31]_i_50_n_0\ : STD_LOGIC;
signal \y_int[31]_i_51_n_0\ : STD_LOGIC;
signal \y_int[31]_i_52_n_0\ : STD_LOGIC;
signal \y_int[31]_i_53_n_0\ : STD_LOGIC;
signal \y_int[31]_i_54_n_0\ : STD_LOGIC;
signal \y_int[31]_i_55_n_0\ : STD_LOGIC;
signal \y_int[31]_i_56_n_0\ : STD_LOGIC;
signal \y_int[31]_i_57_n_0\ : STD_LOGIC;
signal \y_int[31]_i_58_n_0\ : STD_LOGIC;
signal \y_int[31]_i_59_n_0\ : STD_LOGIC;
signal \y_int[31]_i_60_n_0\ : STD_LOGIC;
signal \y_int[31]_i_61_n_0\ : STD_LOGIC;
signal \y_int[31]_i_72_n_0\ : STD_LOGIC;
signal \y_int[31]_i_73_n_0\ : STD_LOGIC;
signal \y_int[31]_i_74_n_0\ : STD_LOGIC;
signal \y_int[31]_i_76_n_0\ : STD_LOGIC;
signal \y_int[31]_i_77_n_0\ : STD_LOGIC;
signal \y_int[31]_i_78_n_0\ : STD_LOGIC;
signal \y_int[31]_i_79_n_0\ : STD_LOGIC;
signal \y_int[31]_i_80_n_0\ : STD_LOGIC;
signal \y_int[31]_i_81_n_0\ : STD_LOGIC;
signal \y_int[31]_i_83_n_0\ : STD_LOGIC;
signal \y_int[31]_i_84_n_0\ : STD_LOGIC;
signal \y_int[31]_i_85_n_0\ : STD_LOGIC;
signal \y_int[31]_i_93_n_0\ : STD_LOGIC;
signal \y_int[31]_i_94_n_0\ : STD_LOGIC;
signal \y_int[31]_i_95_n_0\ : STD_LOGIC;
signal \y_int[31]_i_96_n_0\ : STD_LOGIC;
signal \y_int[31]_i_97_n_0\ : STD_LOGIC;
signal \y_int[31]_i_98_n_0\ : STD_LOGIC;
signal \y_int[31]_i_99_n_0\ : STD_LOGIC;
signal \y_int[3]_i_37_n_0\ : STD_LOGIC;
signal \y_int[3]_i_38_n_0\ : STD_LOGIC;
signal \y_int[3]_i_39_n_0\ : STD_LOGIC;
signal \y_int[3]_i_41_n_0\ : STD_LOGIC;
signal \y_int[3]_i_42_n_0\ : STD_LOGIC;
signal \y_int[3]_i_43_n_0\ : STD_LOGIC;
signal \y_int[3]_i_44_n_0\ : STD_LOGIC;
signal \y_int[3]_i_46_n_0\ : STD_LOGIC;
signal \y_int[3]_i_47_n_0\ : STD_LOGIC;
signal \y_int[3]_i_48_n_0\ : STD_LOGIC;
signal \y_int[3]_i_49_n_0\ : STD_LOGIC;
signal \y_int[3]_i_75_n_0\ : STD_LOGIC;
signal \y_int[3]_i_76_n_0\ : STD_LOGIC;
signal \y_int[3]_i_77_n_0\ : STD_LOGIC;
signal \y_int[3]_i_78_n_0\ : STD_LOGIC;
signal \y_int[3]_i_79_n_0\ : STD_LOGIC;
signal \y_int[3]_i_80_n_0\ : STD_LOGIC;
signal \y_int[3]_i_81_n_0\ : STD_LOGIC;
signal \y_int[3]_i_82_n_0\ : STD_LOGIC;
signal \y_int[3]_i_83_n_0\ : STD_LOGIC;
signal \y_int[3]_i_93_n_0\ : STD_LOGIC;
signal \y_int[3]_i_94_n_0\ : STD_LOGIC;
signal \y_int[3]_i_95_n_0\ : STD_LOGIC;
signal \y_int[3]_i_96_n_0\ : STD_LOGIC;
signal \y_int[7]_i_25_n_0\ : STD_LOGIC;
signal \y_int[7]_i_26_n_0\ : STD_LOGIC;
signal \y_int[7]_i_27_n_0\ : STD_LOGIC;
signal \y_int[7]_i_28_n_0\ : STD_LOGIC;
signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 );
signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC;
signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC;
signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC;
signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC;
signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC;
signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC;
signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC;
signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC;
signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute HLUTNM : string;
attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0";
attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38";
begin
hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8);
hdmi_d(7) <= \<const0>\;
hdmi_d(6) <= \<const0>\;
hdmi_d(5) <= \<const0>\;
hdmi_d(4) <= \<const0>\;
hdmi_d(3) <= \<const0>\;
hdmi_d(2) <= \<const0>\;
hdmi_d(1) <= \<const0>\;
hdmi_d(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_zed_hdmi_0_0_zed_hdmi
port map (
CO(0) => U0_n_16,
DI(0) => U0_n_4,
O(1) => U0_n_7,
O(0) => U0_n_8,
active => active,
\cb_int_reg[15]_0\(0) => U0_n_76,
\cb_int_reg[27]_0\(0) => U0_n_75,
\cb_int_reg[3]_0\(3) => U0_n_9,
\cb_int_reg[3]_0\(2) => U0_n_10,
\cb_int_reg[3]_0\(1) => U0_n_11,
\cb_int_reg[3]_0\(0) => U0_n_12,
\cb_int_reg[3]_1\(0) => U0_n_72,
\cb_int_reg[3]_2\(0) => U0_n_73,
\cb_int_reg[3]_3\(0) => U0_n_74,
clk => clk,
clk_100 => clk_100,
clk_x2 => clk_x2,
\cr_int_reg[11]_0\(3) => U0_n_34,
\cr_int_reg[11]_0\(2) => U0_n_35,
\cr_int_reg[11]_0\(1) => U0_n_36,
\cr_int_reg[11]_0\(0) => U0_n_37,
\cr_int_reg[15]_0\(3) => U0_n_38,
\cr_int_reg[15]_0\(2) => U0_n_39,
\cr_int_reg[15]_0\(1) => U0_n_40,
\cr_int_reg[15]_0\(0) => U0_n_41,
\cr_int_reg[15]_1\(0) => U0_n_77,
\cr_int_reg[19]_0\(3) => U0_n_42,
\cr_int_reg[19]_0\(2) => U0_n_43,
\cr_int_reg[19]_0\(1) => U0_n_44,
\cr_int_reg[19]_0\(0) => U0_n_45,
\cr_int_reg[23]_0\(3) => U0_n_46,
\cr_int_reg[23]_0\(2) => U0_n_47,
\cr_int_reg[23]_0\(1) => U0_n_48,
\cr_int_reg[23]_0\(0) => U0_n_49,
\cr_int_reg[23]_1\(0) => U0_n_50,
\cr_int_reg[27]_0\ => U0_n_13,
\cr_int_reg[27]_1\(1) => U0_n_14,
\cr_int_reg[27]_1\(0) => U0_n_15,
\cr_int_reg[27]_2\(0) => U0_n_29,
\cr_int_reg[31]_0\ => U0_n_5,
\cr_int_reg[31]_1\ => U0_n_6,
\cr_int_reg[31]_2\(1) => U0_n_17,
\cr_int_reg[31]_2\(0) => U0_n_18,
\cr_int_reg[3]_0\(2) => U0_n_23,
\cr_int_reg[3]_0\(1) => U0_n_24,
\cr_int_reg[3]_0\(0) => U0_n_25,
\cr_int_reg[3]_1\(0) => U0_n_26,
\cr_int_reg[3]_2\(1) => U0_n_27,
\cr_int_reg[3]_2\(0) => U0_n_28,
\cr_int_reg[7]_0\(3) => U0_n_19,
\cr_int_reg[7]_0\(2) => U0_n_20,
\cr_int_reg[7]_0\(1) => U0_n_21,
\cr_int_reg[7]_0\(0) => U0_n_22,
\cr_int_reg[7]_1\(3) => U0_n_30,
\cr_int_reg[7]_1\(2) => U0_n_31,
\cr_int_reg[7]_1\(1) => U0_n_32,
\cr_int_reg[7]_1\(0) => U0_n_33,
hdmi_clk => hdmi_clk,
hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
rgb888(23 downto 0) => rgb888(23 downto 0),
\rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\,
\rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\,
\rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\,
\rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\,
\rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\,
\rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\,
\rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\,
\rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\,
\rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\,
\rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\,
\rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\,
\rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\,
\rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\,
\rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\,
\rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\,
\rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\,
\rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\,
\rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\,
\rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\,
\rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\,
\rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\,
\rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\,
\rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\,
\rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\,
\rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\,
\rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\,
\rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\,
\rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\,
\rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\,
\rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\,
\rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\,
\rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\,
\rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\,
\rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\,
\rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\,
\rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\,
\rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\,
\rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\,
\rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\,
\rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\,
\rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\,
\rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\,
\rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\,
\rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\,
\rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\,
\rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\,
\rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\,
\rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\,
\rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\,
\rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\,
\rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\,
\rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\,
\rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\,
\rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\,
\rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\,
\rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\,
\rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\,
\rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\,
\rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\,
\rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\,
\rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9),
\rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\,
\rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\,
\rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\,
\rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\,
\rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\,
\rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\,
\rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\,
\rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\,
\rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\,
\rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\,
\rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\,
\rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\,
\rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\,
\rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\,
\rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\,
\rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\,
\rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\,
\rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\,
\rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\,
\rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\,
\rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\,
\rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\,
\rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\,
\rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\,
\rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\,
\rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\,
\rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\,
\rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\,
\rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\,
\rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\,
\rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\,
\rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\,
\rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\,
\rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\,
\rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\,
\rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\,
\rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\,
\rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\,
\rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\,
\rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\,
\rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\,
\rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\,
\rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\,
\rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\,
\rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\,
\rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\,
\rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\,
\rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\,
\rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\,
\rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\,
\rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\,
\rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\,
\rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\,
\rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\,
\rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\,
\rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\,
\rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\,
\rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\,
\rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\,
\rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\,
\rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\,
\rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\,
\rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\,
\rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\,
\rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\,
\rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\,
\rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\,
\rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\,
\rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\,
\rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\,
\rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\,
\rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\,
\rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\,
\rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\,
\rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\,
\rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\,
\rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\,
\rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\,
\rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\,
\rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\,
\rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\,
\rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\,
\rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\,
\rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\,
\rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\,
\rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\,
\rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\,
\rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\,
\rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\,
\rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\,
\rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\,
\rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\,
\rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\,
\rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\,
\rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\,
\rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\,
\rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\,
\rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\,
\rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\,
\rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\,
\rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\,
\rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\,
\rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\,
\rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\,
\rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\,
\rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\,
\rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\,
\rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\,
\rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\,
\rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\,
\rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\,
\rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\,
\rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\,
\rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\,
\rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\,
\rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\,
\rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\,
\rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\,
vsync => vsync,
\y_int_reg[15]_0\(3) => U0_n_68,
\y_int_reg[15]_0\(2) => U0_n_69,
\y_int_reg[15]_0\(1) => U0_n_70,
\y_int_reg[15]_0\(0) => U0_n_71,
\y_int_reg[15]_1\(0) => U0_n_81,
\y_int_reg[19]_0\(3) => U0_n_64,
\y_int_reg[19]_0\(2) => U0_n_65,
\y_int_reg[19]_0\(1) => U0_n_66,
\y_int_reg[19]_0\(0) => U0_n_67,
\y_int_reg[19]_1\(0) => U0_n_79,
\y_int_reg[23]_0\(0) => U0_n_55,
\y_int_reg[23]_1\(1) => U0_n_58,
\y_int_reg[23]_1\(0) => U0_n_59,
\y_int_reg[23]_2\(3) => U0_n_60,
\y_int_reg[23]_2\(2) => U0_n_61,
\y_int_reg[23]_2\(1) => U0_n_62,
\y_int_reg[23]_2\(0) => U0_n_63,
\y_int_reg[23]_3\(0) => U0_n_80,
\y_int_reg[3]_0\(3) => U0_n_51,
\y_int_reg[3]_0\(2) => U0_n_52,
\y_int_reg[3]_0\(1) => U0_n_53,
\y_int_reg[3]_0\(0) => U0_n_54,
\y_int_reg[3]_1\(0) => U0_n_57,
\y_int_reg[3]_2\(0) => U0_n_78,
\y_int_reg[7]_0\(0) => U0_n_56
);
\cb_int[15]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_4\,
O => \cb_int[15]_i_35_n_0\
);
\cb_int[15]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_5\,
O => \cb_int[15]_i_36_n_0\
);
\cb_int[15]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_6\,
O => \cb_int[15]_i_37_n_0\
);
\cb_int[15]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[15]_i_32_n_7\,
O => \cb_int[15]_i_38_n_0\
);
\cb_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_39_n_0\
);
\cb_int[15]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_40_n_0\
);
\cb_int[15]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_41_n_0\
);
\cb_int[15]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[15]_i_42_n_0\
);
\cb_int[15]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_47_n_0\
);
\cb_int[15]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_48_n_0\
);
\cb_int[15]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_49_n_0\
);
\cb_int[15]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[15]_i_50_n_0\
);
\cb_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_38_n_0\
);
\cb_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_39_n_0\
);
\cb_int[19]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_40_n_0\
);
\cb_int[19]_i_41\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[19]_i_41_n_0\
);
\cb_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_42_n_0\
);
\cb_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_43_n_0\
);
\cb_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_44_n_0\
);
\cb_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[19]_i_45_n_0\
);
\cb_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_33_n_0\
);
\cb_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_34_n_0\
);
\cb_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_35_n_0\
);
\cb_int[23]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[23]_i_36_n_0\
);
\cb_int[23]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_37_n_0\
);
\cb_int[23]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_38_n_0\
);
\cb_int[23]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_39_n_0\
);
\cb_int[23]_i_40\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[23]_i_40_n_0\
);
\cb_int[31]_i_100\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(14),
O => \cb_int[31]_i_100_n_0\
);
\cb_int[31]_i_101\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(13),
O => \cb_int[31]_i_101_n_0\
);
\cb_int[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => U0_n_13,
I1 => rgb888(7),
O => \cb_int[31]_i_18_n_0\
);
\cb_int[31]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_19_n_0\
);
\cb_int[31]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_20_n_0\
);
\cb_int[31]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(7),
I1 => U0_n_13,
O => \cb_int[31]_i_21_n_0\
);
\cb_int[31]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => rgb888(7),
I1 => \cb_int[31]_i_52_n_0\,
I2 => rgb888(6),
O => \cb_int[31]_i_22_n_0\
);
\cb_int[31]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_25_n_0\
);
\cb_int[31]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_26_n_0\
);
\cb_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_6\,
O => \cb_int[31]_i_28_n_0\
);
\cb_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_66_n_7\,
O => \cb_int[31]_i_29_n_0\
);
\cb_int[31]_i_45\: unisim.vcomponents.LUT5
generic map(
INIT => X"99999996"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_45_n_0\
);
\cb_int[31]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(2),
I1 => rgb888(1),
O => \cb_int[31]_i_46_n_0\
);
\cb_int[31]_i_47\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA955555555"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
I5 => rgb888(5),
O => \cb_int[31]_i_47_n_0\
);
\cb_int[31]_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCC999999993"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(5),
I2 => rgb888(3),
I3 => rgb888(1),
I4 => rgb888(2),
I5 => rgb888(4),
O => \cb_int[31]_i_48_n_0\
);
\cb_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA99995"
)
port map (
I0 => rgb888(4),
I1 => \cb_int_reg[3]_i_43_n_1\,
I2 => rgb888(2),
I3 => rgb888(1),
I4 => rgb888(3),
O => \cb_int[31]_i_49_n_0\
);
\cb_int[31]_i_50\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A95"
)
port map (
I0 => \cb_int_reg[3]_i_43_n_1\,
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
O => \cb_int[31]_i_50_n_0\
);
\cb_int[31]_i_52\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(1),
I3 => rgb888(3),
I4 => rgb888(5),
O => \cb_int[31]_i_52_n_0\
);
\cb_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => rgb888(14),
I1 => rgb888(12),
I2 => rgb888(10),
I3 => rgb888(11),
I4 => rgb888(13),
I5 => rgb888(15),
O => \cb_int[31]_i_53_n_0\
);
\cb_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000006AAAAAAA"
)
port map (
I0 => rgb888(14),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(15),
O => \cb_int[31]_i_54_n_0\
);
\cb_int[31]_i_55\: unisim.vcomponents.LUT6
generic map(
INIT => X"2BBBBBBBB2222222"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_0\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(13),
O => \cb_int[31]_i_55_n_0\
);
\cb_int[31]_i_56\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFEA2A80"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_5\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(12),
I4 => rgb888(14),
O => \cb_int[31]_i_56_n_0\
);
\cb_int[31]_i_57\: unisim.vcomponents.LUT6
generic map(
INIT => X"9555555555555555"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_57_n_0\
);
\cb_int[31]_i_58\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAABFFFFFFF"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
I2 => rgb888(11),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \cb_int[31]_i_58_n_0\
);
\cb_int[31]_i_59\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => U0_n_6,
I1 => \cb_int_reg[31]_i_85_n_0\,
I2 => rgb888(15),
I3 => U0_n_5,
O => \cb_int[31]_i_59_n_0\
);
\cb_int[31]_i_60\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(14),
I1 => \cb_int[31]_i_88_n_0\,
I2 => \cb_int_reg[31]_i_85_n_5\,
I3 => U0_n_6,
I4 => rgb888(15),
I5 => \cb_int_reg[31]_i_85_n_0\,
O => \cb_int[31]_i_60_n_0\
);
\cb_int[31]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_4\,
O => \cb_int[31]_i_62_n_0\
);
\cb_int[31]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_5\,
O => \cb_int[31]_i_63_n_0\
);
\cb_int[31]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_6\,
O => \cb_int[31]_i_64_n_0\
);
\cb_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[23]_i_27_n_7\,
O => \cb_int[31]_i_65_n_0\
);
\cb_int[31]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_83_n_0\
);
\cb_int[31]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_8_n_4\,
O => \cb_int[31]_i_84_n_0\
);
\cb_int[31]_i_88\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rgb888(10),
I1 => rgb888(11),
I2 => rgb888(12),
O => \cb_int[31]_i_88_n_0\
);
\cb_int[31]_i_89\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_4\,
O => \cb_int[31]_i_89_n_0\
);
\cb_int[31]_i_90\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_5\,
O => \cb_int[31]_i_90_n_0\
);
\cb_int[31]_i_91\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_6\,
O => \cb_int[31]_i_91_n_0\
);
\cb_int[31]_i_92\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[19]_i_32_n_7\,
O => \cb_int[31]_i_92_n_0\
);
\cb_int[31]_i_93\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_93_n_0\
);
\cb_int[31]_i_94\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[31]_i_94_n_0\
);
\cb_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \cb_int[31]_i_99_n_0\
);
\cb_int[3]_i_35\: unisim.vcomponents.LUT4
generic map(
INIT => X"BE28"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
O => \cb_int[3]_i_35_n_0\
);
\cb_int[3]_i_36\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => rgb888(10),
I1 => \cb_int_reg[31]_i_85_n_7\,
I2 => rgb888(12),
O => \cb_int[3]_i_36_n_0\
);
\cb_int[3]_i_37\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_37_n_0\
);
\cb_int[3]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cb_int_reg[3]_i_68_n_4\,
I1 => rgb888(9),
I2 => rgb888(11),
O => \cb_int[3]_i_38_n_0\
);
\cb_int[3]_i_39\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969969696"
)
port map (
I0 => \cb_int[3]_i_35_n_0\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => rgb888(11),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_5\,
O => \cb_int[3]_i_39_n_0\
);
\cb_int[3]_i_40\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \cb_int_reg[31]_i_85_n_6\,
I1 => rgb888(10),
I2 => rgb888(11),
I3 => rgb888(13),
I4 => \cb_int[3]_i_36_n_0\,
O => \cb_int[3]_i_40_n_0\
);
\cb_int[3]_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"E81717E817E8E817"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(12),
I4 => rgb888(10),
I5 => \cb_int_reg[31]_i_85_n_7\,
O => \cb_int[3]_i_41_n_0\
);
\cb_int[3]_i_42\: unisim.vcomponents.LUT5
generic map(
INIT => X"69969696"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => \cb_int_reg[3]_i_68_n_4\,
I3 => rgb888(10),
I4 => rgb888(8),
O => \cb_int[3]_i_42_n_0\
);
\cb_int[3]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[3]_i_59_n_0\
);
\cb_int[3]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_7\,
O => \cb_int[3]_i_60_n_0\
);
\cb_int[3]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_9,
O => \cb_int[3]_i_61_n_0\
);
\cb_int[3]_i_62\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_10,
O => \cb_int[3]_i_62_n_0\
);
\cb_int[3]_i_73\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(7),
O => \cb_int[3]_i_73_n_0\
);
\cb_int[3]_i_74\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(6),
O => \cb_int[3]_i_74_n_0\
);
\cb_int[3]_i_84\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(8),
O => \cb_int[3]_i_84_n_0\
);
\cb_int[3]_i_85\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_11,
O => \cb_int[3]_i_85_n_0\
);
\cb_int[3]_i_86\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \cb_int[3]_i_86_n_0\
);
\cb_int[3]_i_87\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_7,
O => \cb_int[3]_i_87_n_0\
);
\cb_int[3]_i_88\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_8,
O => \cb_int[3]_i_88_n_0\
);
\cb_int[3]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(15),
O => \cb_int[3]_i_95_n_0\
);
\cb_int[3]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(14),
O => \cb_int[3]_i_96_n_0\
);
\cb_int[3]_i_97\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(13),
O => \cb_int[3]_i_97_n_0\
);
\cb_int[3]_i_98\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(12),
O => \cb_int[3]_i_98_n_0\
);
\cb_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[7]_i_24_n_4\,
O => \cb_int[7]_i_30_n_0\
);
\cb_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_31_n_0\
);
\cb_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_32_n_0\
);
\cb_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_24_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_33_n_0\
);
\cb_int[7]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_6\,
O => \cb_int[7]_i_34_n_0\
);
\cb_int[7]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_9_n_7\,
O => \cb_int[7]_i_35_n_0\
);
\cb_int[7]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_4\,
O => \cb_int[7]_i_36_n_0\
);
\cb_int[7]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_5\,
O => \cb_int[7]_i_37_n_0\
);
\cb_int[7]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[3]_i_32_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_6\,
O => \cb_int[7]_i_43_n_0\
);
\cb_int[7]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_4\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_44_n_0\
);
\cb_int[7]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_5\,
I1 => U0_n_16,
I2 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_45_n_0\
);
\cb_int[7]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_6\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_46_n_0\
);
\cb_int[7]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \cb_int_reg[7]_i_27_n_7\,
I1 => U0_n_16,
I2 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_47_n_0\
);
\cb_int[7]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_6\,
O => \cb_int[7]_i_48_n_0\
);
\cb_int[7]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[31]_i_23_n_7\,
O => \cb_int[7]_i_49_n_0\
);
\cb_int[7]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_4\,
O => \cb_int[7]_i_50_n_0\
);
\cb_int[7]_i_51\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \cb_int_reg[3]_i_19_n_5\,
O => \cb_int[7]_i_51_n_0\
);
\cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_23_n_0\,
CO(3) => \cb_int_reg[15]_i_31_n_0\,
CO(2) => \cb_int_reg[15]_i_31_n_1\,
CO(1) => \cb_int_reg[15]_i_31_n_2\,
CO(0) => \cb_int_reg[15]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_31_n_4\,
O(2) => \cb_int_reg[15]_i_31_n_5\,
O(1) => \cb_int_reg[15]_i_31_n_6\,
O(0) => \cb_int_reg[15]_i_31_n_7\,
S(3) => \cb_int[15]_i_35_n_0\,
S(2) => \cb_int[15]_i_36_n_0\,
S(1) => \cb_int[15]_i_37_n_0\,
S(0) => \cb_int[15]_i_38_n_0\
);
\cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_24_n_0\,
CO(3) => \cb_int_reg[15]_i_32_n_0\,
CO(2) => \cb_int_reg[15]_i_32_n_1\,
CO(1) => \cb_int_reg[15]_i_32_n_2\,
CO(0) => \cb_int_reg[15]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_32_n_4\,
O(2) => \cb_int_reg[15]_i_32_n_5\,
O(1) => \cb_int_reg[15]_i_32_n_6\,
O(0) => \cb_int_reg[15]_i_32_n_7\,
S(3) => \cb_int[15]_i_39_n_0\,
S(2) => \cb_int[15]_i_40_n_0\,
S(1) => \cb_int[15]_i_41_n_0\,
S(0) => \cb_int[15]_i_42_n_0\
);
\cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_76,
CO(3) => \cb_int_reg[15]_i_34_n_0\,
CO(2) => \cb_int_reg[15]_i_34_n_1\,
CO(1) => \cb_int_reg[15]_i_34_n_2\,
CO(0) => \cb_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[15]_i_34_n_4\,
O(2) => \cb_int_reg[15]_i_34_n_5\,
O(1) => \cb_int_reg[15]_i_34_n_6\,
O(0) => \cb_int_reg[15]_i_34_n_7\,
S(3) => \cb_int[15]_i_47_n_0\,
S(2) => \cb_int[15]_i_48_n_0\,
S(1) => \cb_int[15]_i_49_n_0\,
S(0) => \cb_int[15]_i_50_n_0\
);
\cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_32_n_0\,
CO(3) => \cb_int_reg[19]_i_32_n_0\,
CO(2) => \cb_int_reg[19]_i_32_n_1\,
CO(1) => \cb_int_reg[19]_i_32_n_2\,
CO(0) => \cb_int_reg[19]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_32_n_4\,
O(2) => \cb_int_reg[19]_i_32_n_5\,
O(1) => \cb_int_reg[19]_i_32_n_6\,
O(0) => \cb_int_reg[19]_i_32_n_7\,
S(3) => \cb_int[19]_i_38_n_0\,
S(2) => \cb_int[19]_i_39_n_0\,
S(1) => \cb_int[19]_i_40_n_0\,
S(0) => \cb_int[19]_i_41_n_0\
);
\cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_34_n_0\,
CO(3) => \cb_int_reg[19]_i_33_n_0\,
CO(2) => \cb_int_reg[19]_i_33_n_1\,
CO(1) => \cb_int_reg[19]_i_33_n_2\,
CO(0) => \cb_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[19]_i_33_n_4\,
O(2) => \cb_int_reg[19]_i_33_n_5\,
O(1) => \cb_int_reg[19]_i_33_n_6\,
O(0) => \cb_int_reg[19]_i_33_n_7\,
S(3) => \cb_int[19]_i_42_n_0\,
S(2) => \cb_int[19]_i_43_n_0\,
S(1) => \cb_int[19]_i_44_n_0\,
S(0) => \cb_int[19]_i_45_n_0\
);
\cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_32_n_0\,
CO(3) => \cb_int_reg[23]_i_27_n_0\,
CO(2) => \cb_int_reg[23]_i_27_n_1\,
CO(1) => \cb_int_reg[23]_i_27_n_2\,
CO(0) => \cb_int_reg[23]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_27_n_4\,
O(2) => \cb_int_reg[23]_i_27_n_5\,
O(1) => \cb_int_reg[23]_i_27_n_6\,
O(0) => \cb_int_reg[23]_i_27_n_7\,
S(3) => \cb_int[23]_i_33_n_0\,
S(2) => \cb_int[23]_i_34_n_0\,
S(1) => \cb_int[23]_i_35_n_0\,
S(0) => \cb_int[23]_i_36_n_0\
);
\cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[19]_i_33_n_0\,
CO(3) => \cb_int_reg[23]_i_28_n_0\,
CO(2) => \cb_int_reg[23]_i_28_n_1\,
CO(1) => \cb_int_reg[23]_i_28_n_2\,
CO(0) => \cb_int_reg[23]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[23]_i_28_n_4\,
O(2) => \cb_int_reg[23]_i_28_n_5\,
O(1) => \cb_int_reg[23]_i_28_n_6\,
O(0) => \cb_int_reg[23]_i_28_n_7\,
S(3) => \cb_int[23]_i_37_n_0\,
S(2) => \cb_int[23]_i_38_n_0\,
S(1) => \cb_int[23]_i_39_n_0\,
S(0) => \cb_int[23]_i_40_n_0\
);
\cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_10_n_6\,
O(0) => \cb_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[31]_i_28_n_0\,
S(0) => \cb_int[31]_i_29_n_0\
);
\cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_75,
CO(3) => \cb_int_reg[31]_i_17_n_0\,
CO(2) => \cb_int_reg[31]_i_17_n_1\,
CO(1) => \cb_int_reg[31]_i_17_n_2\,
CO(0) => \cb_int_reg[31]_i_17_n_3\,
CYINIT => '0',
DI(3) => U0_n_14,
DI(2) => U0_n_15,
DI(1) => \cb_int[31]_i_45_n_0\,
DI(0) => \cb_int[31]_i_46_n_0\,
O(3) => \cb_int_reg[31]_i_17_n_4\,
O(2) => \cb_int_reg[31]_i_17_n_5\,
O(1) => \cb_int_reg[31]_i_17_n_6\,
O(0) => \cb_int_reg[31]_i_17_n_7\,
S(3) => \cb_int[31]_i_47_n_0\,
S(2) => \cb_int[31]_i_48_n_0\,
S(1) => \cb_int[31]_i_49_n_0\,
S(0) => \cb_int[31]_i_50_n_0\
);
\cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_19_n_0\,
CO(3) => \cb_int_reg[31]_i_23_n_0\,
CO(2) => \cb_int_reg[31]_i_23_n_1\,
CO(1) => \cb_int_reg[31]_i_23_n_2\,
CO(0) => \cb_int_reg[31]_i_23_n_3\,
CYINIT => '0',
DI(3) => \cb_int[31]_i_53_n_0\,
DI(2) => \cb_int[31]_i_54_n_0\,
DI(1) => \cb_int[31]_i_55_n_0\,
DI(0) => \cb_int[31]_i_56_n_0\,
O(3) => \cb_int_reg[31]_i_23_n_4\,
O(2) => \cb_int_reg[31]_i_23_n_5\,
O(1) => \cb_int_reg[31]_i_23_n_6\,
O(0) => \cb_int_reg[31]_i_23_n_7\,
S(3) => \cb_int[31]_i_57_n_0\,
S(2) => \cb_int[31]_i_58_n_0\,
S(1) => \cb_int[31]_i_59_n_0\,
S(0) => \cb_int[31]_i_60_n_0\
);
\cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_61_n_0\,
CO(3) => \cb_int_reg[31]_i_27_n_0\,
CO(2) => \cb_int_reg[31]_i_27_n_1\,
CO(1) => \cb_int_reg[31]_i_27_n_2\,
CO(0) => \cb_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_27_n_4\,
O(2) => \cb_int_reg[31]_i_27_n_5\,
O(1) => \cb_int_reg[31]_i_27_n_6\,
O(0) => \cb_int_reg[31]_i_27_n_7\,
S(3) => \cb_int[31]_i_62_n_0\,
S(2) => \cb_int[31]_i_63_n_0\,
S(1) => \cb_int[31]_i_64_n_0\,
S(0) => \cb_int[31]_i_65_n_0\
);
\cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_28_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_42_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_42_n_6\,
O(0) => \cb_int_reg[31]_i_42_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_83_n_0\,
S(0) => \cb_int[31]_i_84_n_0\
);
\cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[15]_i_31_n_0\,
CO(3) => \cb_int_reg[31]_i_61_n_0\,
CO(2) => \cb_int_reg[31]_i_61_n_1\,
CO(1) => \cb_int_reg[31]_i_61_n_2\,
CO(0) => \cb_int_reg[31]_i_61_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[31]_i_61_n_4\,
O(2) => \cb_int_reg[31]_i_61_n_5\,
O(1) => \cb_int_reg[31]_i_61_n_6\,
O(0) => \cb_int_reg[31]_i_61_n_7\,
S(3) => \cb_int[31]_i_89_n_0\,
S(2) => \cb_int[31]_i_90_n_0\,
S(1) => \cb_int[31]_i_91_n_0\,
S(0) => \cb_int[31]_i_92_n_0\
);
\cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[23]_i_27_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_66_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_66_n_6\,
O(0) => \cb_int_reg[31]_i_66_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_93_n_0\,
S(0) => \cb_int[31]_i_94_n_0\
);
\cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_17_n_0\,
CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[31]_i_8_n_1\,
CO(1) => \cb_int_reg[31]_i_8_n_2\,
CO(0) => \cb_int_reg[31]_i_8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \cb_int[31]_i_18_n_0\,
O(3) => \cb_int_reg[31]_i_8_n_4\,
O(2) => \cb_int_reg[31]_i_8_n_5\,
O(1) => \cb_int_reg[31]_i_8_n_6\,
O(0) => \cb_int_reg[31]_i_8_n_7\,
S(3) => \cb_int[31]_i_19_n_0\,
S(2) => \cb_int[31]_i_20_n_0\,
S(1) => \cb_int[31]_i_21_n_0\,
S(0) => \cb_int[31]_i_22_n_0\
);
\cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_68_n_0\,
CO(3) => \cb_int_reg[31]_i_85_n_0\,
CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2),
CO(1) => \cb_int_reg[31]_i_85_n_2\,
CO(0) => \cb_int_reg[31]_i_85_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => rgb888(15 downto 14),
DI(0) => '0',
O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3),
O(2) => \cb_int_reg[31]_i_85_n_5\,
O(1) => \cb_int_reg[31]_i_85_n_6\,
O(0) => \cb_int_reg[31]_i_85_n_7\,
S(3) => '1',
S(2) => \cb_int[31]_i_99_n_0\,
S(1) => \cb_int[31]_i_100_n_0\,
S(0) => \cb_int[31]_i_101_n_0\
);
\cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[31]_i_23_n_0\,
CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cb_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => U0_n_4,
O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[31]_i_9_n_6\,
O(0) => \cb_int_reg[31]_i_9_n_7\,
S(3 downto 2) => B"00",
S(1) => \cb_int[31]_i_25_n_0\,
S(0) => \cb_int[31]_i_26_n_0\
);
\cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_73,
CO(3) => \cb_int_reg[3]_i_19_n_0\,
CO(2) => \cb_int_reg[3]_i_19_n_1\,
CO(1) => \cb_int_reg[3]_i_19_n_2\,
CO(0) => \cb_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \cb_int[3]_i_35_n_0\,
DI(2) => \cb_int[3]_i_36_n_0\,
DI(1) => \cb_int[3]_i_37_n_0\,
DI(0) => \cb_int[3]_i_38_n_0\,
O(3) => \cb_int_reg[3]_i_19_n_4\,
O(2) => \cb_int_reg[3]_i_19_n_5\,
O(1) => \cb_int_reg[3]_i_19_n_6\,
O(0) => \cb_int_reg[3]_i_19_n_7\,
S(3) => \cb_int[3]_i_39_n_0\,
S(2) => \cb_int[3]_i_40_n_0\,
S(1) => \cb_int[3]_i_41_n_0\,
S(0) => \cb_int[3]_i_42_n_0\
);
\cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_58_n_0\,
CO(3) => \cb_int_reg[3]_i_32_n_0\,
CO(2) => \cb_int_reg[3]_i_32_n_1\,
CO(1) => \cb_int_reg[3]_i_32_n_2\,
CO(0) => \cb_int_reg[3]_i_32_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[3]_i_32_n_4\,
O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0),
S(3) => \cb_int[3]_i_59_n_0\,
S(2) => \cb_int[3]_i_60_n_0\,
S(1) => \cb_int[3]_i_61_n_0\,
S(0) => \cb_int[3]_i_62_n_0\
);
\cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_74,
CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3),
CO(2) => \cb_int_reg[3]_i_43_n_1\,
CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1),
CO(0) => \cb_int_reg[3]_i_43_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(7),
DI(0) => '0',
O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2),
O(1) => \cb_int_reg[3]_i_43_n_6\,
O(0) => \cb_int_reg[3]_i_43_n_7\,
S(3 downto 2) => B"01",
S(1) => \cb_int[3]_i_73_n_0\,
S(0) => \cb_int[3]_i_74_n_0\
);
\cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[3]_i_58_n_0\,
CO(2) => \cb_int_reg[3]_i_58_n_1\,
CO(1) => \cb_int_reg[3]_i_58_n_2\,
CO(0) => \cb_int_reg[3]_i_58_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0),
S(3) => \cb_int[3]_i_85_n_0\,
S(2) => \cb_int[3]_i_86_n_0\,
S(1) => \cb_int[3]_i_87_n_0\,
S(0) => \cb_int[3]_i_88_n_0\
);
\cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_72,
CO(3) => \cb_int_reg[3]_i_68_n_0\,
CO(2) => \cb_int_reg[3]_i_68_n_1\,
CO(1) => \cb_int_reg[3]_i_68_n_2\,
CO(0) => \cb_int_reg[3]_i_68_n_3\,
CYINIT => '0',
DI(3 downto 0) => rgb888(12 downto 9),
O(3) => \cb_int_reg[3]_i_68_n_4\,
O(2) => \cb_int_reg[3]_i_68_n_5\,
O(1) => \cb_int_reg[3]_i_68_n_6\,
O(0) => \cb_int_reg[3]_i_68_n_7\,
S(3) => \cb_int[3]_i_95_n_0\,
S(2) => \cb_int[3]_i_96_n_0\,
S(1) => \cb_int[3]_i_97_n_0\,
S(0) => \cb_int[3]_i_98_n_0\
);
\cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_26_n_0\,
CO(3) => \cb_int_reg[7]_i_23_n_0\,
CO(2) => \cb_int_reg[7]_i_23_n_1\,
CO(1) => \cb_int_reg[7]_i_23_n_2\,
CO(0) => \cb_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_23_n_4\,
O(2) => \cb_int_reg[7]_i_23_n_5\,
O(1) => \cb_int_reg[7]_i_23_n_6\,
O(0) => \cb_int_reg[7]_i_23_n_7\,
S(3) => \cb_int[7]_i_30_n_0\,
S(2) => \cb_int[7]_i_31_n_0\,
S(1) => \cb_int[7]_i_32_n_0\,
S(0) => \cb_int[7]_i_33_n_0\
);
\cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[7]_i_27_n_0\,
CO(3) => \cb_int_reg[7]_i_24_n_0\,
CO(2) => \cb_int_reg[7]_i_24_n_1\,
CO(1) => \cb_int_reg[7]_i_24_n_2\,
CO(0) => \cb_int_reg[7]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_24_n_4\,
O(2) => \cb_int_reg[7]_i_24_n_5\,
O(1) => \cb_int_reg[7]_i_24_n_6\,
O(0) => \cb_int_reg[7]_i_24_n_7\,
S(3) => \cb_int[7]_i_34_n_0\,
S(2) => \cb_int[7]_i_35_n_0\,
S(1) => \cb_int[7]_i_36_n_0\,
S(0) => \cb_int[7]_i_37_n_0\
);
\cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cb_int_reg[7]_i_26_n_0\,
CO(2) => \cb_int_reg[7]_i_26_n_1\,
CO(1) => \cb_int_reg[7]_i_26_n_2\,
CO(0) => \cb_int_reg[7]_i_26_n_3\,
CYINIT => \cb_int[7]_i_43_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_26_n_4\,
O(2) => \cb_int_reg[7]_i_26_n_5\,
O(1) => \cb_int_reg[7]_i_26_n_6\,
O(0) => \cb_int_reg[7]_i_26_n_7\,
S(3) => \cb_int[7]_i_44_n_0\,
S(2) => \cb_int[7]_i_45_n_0\,
S(1) => \cb_int[7]_i_46_n_0\,
S(0) => \cb_int[7]_i_47_n_0\
);
\cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cb_int_reg[3]_i_32_n_0\,
CO(3) => \cb_int_reg[7]_i_27_n_0\,
CO(2) => \cb_int_reg[7]_i_27_n_1\,
CO(1) => \cb_int_reg[7]_i_27_n_2\,
CO(0) => \cb_int_reg[7]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cb_int_reg[7]_i_27_n_4\,
O(2) => \cb_int_reg[7]_i_27_n_5\,
O(1) => \cb_int_reg[7]_i_27_n_6\,
O(0) => \cb_int_reg[7]_i_27_n_7\,
S(3) => \cb_int[7]_i_48_n_0\,
S(2) => \cb_int[7]_i_49_n_0\,
S(1) => \cb_int[7]_i_50_n_0\,
S(0) => \cb_int[7]_i_51_n_0\
);
\cr_int[11]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_35,
O => \cr_int[11]_i_61_n_0\
);
\cr_int[11]_i_62\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_36,
I1 => U0_n_26,
I2 => U0_n_18,
O => \cr_int[11]_i_62_n_0\
);
\cr_int[11]_i_63\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_37,
I1 => U0_n_26,
I2 => U0_n_19,
O => \cr_int[11]_i_63_n_0\
);
\cr_int[11]_i_64\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_30,
I1 => U0_n_26,
I2 => U0_n_20,
O => \cr_int[11]_i_64_n_0\
);
\cr_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_39,
O => \cr_int[15]_i_44_n_0\
);
\cr_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_40,
O => \cr_int[15]_i_45_n_0\
);
\cr_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_41,
O => \cr_int[15]_i_46_n_0\
);
\cr_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_34,
O => \cr_int[15]_i_47_n_0\
);
\cr_int[15]_i_52\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_52_n_0\
);
\cr_int[15]_i_53\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_53_n_0\
);
\cr_int[15]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_54_n_0\
);
\cr_int[15]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[15]_i_55_n_0\
);
\cr_int[19]_i_42\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_42_n_0\
);
\cr_int[19]_i_43\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_43_n_0\
);
\cr_int[19]_i_44\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_44_n_0\
);
\cr_int[19]_i_45\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[19]_i_45_n_0\
);
\cr_int[23]_i_32\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_32_n_0\
);
\cr_int[23]_i_33\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_33_n_0\
);
\cr_int[23]_i_34\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_34_n_0\
);
\cr_int[23]_i_35\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[23]_i_35_n_0\
);
\cr_int[31]_i_104\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_43,
O => \cr_int[31]_i_104_n_0\
);
\cr_int[31]_i_105\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_44,
O => \cr_int[31]_i_105_n_0\
);
\cr_int[31]_i_106\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_45,
O => \cr_int[31]_i_106_n_0\
);
\cr_int[31]_i_107\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_38,
O => \cr_int[31]_i_107_n_0\
);
\cr_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_50,
O => \cr_int[31]_i_28_n_0\
);
\cr_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_46,
O => \cr_int[31]_i_29_n_0\
);
\cr_int[31]_i_65\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_47,
O => \cr_int[31]_i_65_n_0\
);
\cr_int[31]_i_66\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_48,
O => \cr_int[31]_i_66_n_0\
);
\cr_int[31]_i_67\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_49,
O => \cr_int[31]_i_67_n_0\
);
\cr_int[31]_i_68\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_17,
I1 => U0_n_26,
I2 => U0_n_42,
O => \cr_int[31]_i_68_n_0\
);
\cr_int[31]_i_98\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_98_n_0\
);
\cr_int[31]_i_99\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_29,
O => \cr_int[31]_i_99_n_0\
);
\cr_int[7]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_28,
I1 => U0_n_26,
I2 => U0_n_25,
O => \cr_int[7]_i_29_n_0\
);
\cr_int[7]_i_30\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_31,
I1 => U0_n_26,
I2 => U0_n_21,
O => \cr_int[7]_i_30_n_0\
);
\cr_int[7]_i_31\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_32,
I1 => U0_n_26,
I2 => U0_n_22,
O => \cr_int[7]_i_31_n_0\
);
\cr_int[7]_i_32\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_33,
I1 => U0_n_26,
I2 => U0_n_23,
O => \cr_int[7]_i_32_n_0\
);
\cr_int[7]_i_33\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => U0_n_27,
I1 => U0_n_26,
I2 => U0_n_24,
O => \cr_int[7]_i_33_n_0\
);
\cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[7]_i_24_n_0\,
CO(3) => \cr_int_reg[11]_i_28_n_0\,
CO(2) => \cr_int_reg[11]_i_28_n_1\,
CO(1) => \cr_int_reg[11]_i_28_n_2\,
CO(0) => \cr_int_reg[11]_i_28_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[11]_i_28_n_4\,
O(2) => \cr_int_reg[11]_i_28_n_5\,
O(1) => \cr_int_reg[11]_i_28_n_6\,
O(0) => \cr_int_reg[11]_i_28_n_7\,
S(3) => \cr_int[11]_i_61_n_0\,
S(2) => \cr_int[11]_i_62_n_0\,
S(1) => \cr_int[11]_i_63_n_0\,
S(0) => \cr_int[11]_i_64_n_0\
);
\cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[11]_i_28_n_0\,
CO(3) => \cr_int_reg[15]_i_37_n_0\,
CO(2) => \cr_int_reg[15]_i_37_n_1\,
CO(1) => \cr_int_reg[15]_i_37_n_2\,
CO(0) => \cr_int_reg[15]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_37_n_4\,
O(2) => \cr_int_reg[15]_i_37_n_5\,
O(1) => \cr_int_reg[15]_i_37_n_6\,
O(0) => \cr_int_reg[15]_i_37_n_7\,
S(3) => \cr_int[15]_i_44_n_0\,
S(2) => \cr_int[15]_i_45_n_0\,
S(1) => \cr_int[15]_i_46_n_0\,
S(0) => \cr_int[15]_i_47_n_0\
);
\cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_77,
CO(3) => \cr_int_reg[15]_i_39_n_0\,
CO(2) => \cr_int_reg[15]_i_39_n_1\,
CO(1) => \cr_int_reg[15]_i_39_n_2\,
CO(0) => \cr_int_reg[15]_i_39_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[15]_i_39_n_4\,
O(2) => \cr_int_reg[15]_i_39_n_5\,
O(1) => \cr_int_reg[15]_i_39_n_6\,
O(0) => \cr_int_reg[15]_i_39_n_7\,
S(3) => \cr_int[15]_i_52_n_0\,
S(2) => \cr_int[15]_i_53_n_0\,
S(1) => \cr_int[15]_i_54_n_0\,
S(0) => \cr_int[15]_i_55_n_0\
);
\cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_39_n_0\,
CO(3) => \cr_int_reg[19]_i_37_n_0\,
CO(2) => \cr_int_reg[19]_i_37_n_1\,
CO(1) => \cr_int_reg[19]_i_37_n_2\,
CO(0) => \cr_int_reg[19]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[19]_i_37_n_4\,
O(2) => \cr_int_reg[19]_i_37_n_5\,
O(1) => \cr_int_reg[19]_i_37_n_6\,
O(0) => \cr_int_reg[19]_i_37_n_7\,
S(3) => \cr_int[19]_i_42_n_0\,
S(2) => \cr_int[19]_i_43_n_0\,
S(1) => \cr_int[19]_i_44_n_0\,
S(0) => \cr_int[19]_i_45_n_0\
);
\cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[19]_i_37_n_0\,
CO(3) => \cr_int_reg[23]_i_31_n_0\,
CO(2) => \cr_int_reg[23]_i_31_n_1\,
CO(1) => \cr_int_reg[23]_i_31_n_2\,
CO(0) => \cr_int_reg[23]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[23]_i_31_n_4\,
O(2) => \cr_int_reg[23]_i_31_n_5\,
O(1) => \cr_int_reg[23]_i_31_n_6\,
O(0) => \cr_int_reg[23]_i_31_n_7\,
S(3) => \cr_int[23]_i_32_n_0\,
S(2) => \cr_int[23]_i_33_n_0\,
S(1) => \cr_int[23]_i_34_n_0\,
S(0) => \cr_int[23]_i_35_n_0\
);
\cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \cr_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \cr_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_10_n_6\,
O(0) => \cr_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \cr_int[31]_i_28_n_0\,
S(0) => \cr_int[31]_i_29_n_0\
);
\cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[31]_i_64_n_0\,
CO(3) => \cr_int_reg[31]_i_27_n_0\,
CO(2) => \cr_int_reg[31]_i_27_n_1\,
CO(1) => \cr_int_reg[31]_i_27_n_2\,
CO(0) => \cr_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_27_n_4\,
O(2) => \cr_int_reg[31]_i_27_n_5\,
O(1) => \cr_int_reg[31]_i_27_n_6\,
O(0) => \cr_int_reg[31]_i_27_n_7\,
S(3) => \cr_int[31]_i_65_n_0\,
S(2) => \cr_int[31]_i_66_n_0\,
S(1) => \cr_int[31]_i_67_n_0\,
S(0) => \cr_int[31]_i_68_n_0\
);
\cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[23]_i_31_n_0\,
CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1),
CO(0) => \cr_int_reg[31]_i_54_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2),
O(1) => \cr_int_reg[31]_i_54_n_6\,
O(0) => \cr_int_reg[31]_i_54_n_7\,
S(3 downto 2) => B"00",
S(1) => \cr_int[31]_i_98_n_0\,
S(0) => \cr_int[31]_i_99_n_0\
);
\cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4
port map (
CI => \cr_int_reg[15]_i_37_n_0\,
CO(3) => \cr_int_reg[31]_i_64_n_0\,
CO(2) => \cr_int_reg[31]_i_64_n_1\,
CO(1) => \cr_int_reg[31]_i_64_n_2\,
CO(0) => \cr_int_reg[31]_i_64_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[31]_i_64_n_4\,
O(2) => \cr_int_reg[31]_i_64_n_5\,
O(1) => \cr_int_reg[31]_i_64_n_6\,
O(0) => \cr_int_reg[31]_i_64_n_7\,
S(3) => \cr_int[31]_i_104_n_0\,
S(2) => \cr_int[31]_i_105_n_0\,
S(1) => \cr_int[31]_i_106_n_0\,
S(0) => \cr_int[31]_i_107_n_0\
);
\cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \cr_int_reg[7]_i_24_n_0\,
CO(2) => \cr_int_reg[7]_i_24_n_1\,
CO(1) => \cr_int_reg[7]_i_24_n_2\,
CO(0) => \cr_int_reg[7]_i_24_n_3\,
CYINIT => \cr_int[7]_i_29_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \cr_int_reg[7]_i_24_n_4\,
O(2) => \cr_int_reg[7]_i_24_n_5\,
O(1) => \cr_int_reg[7]_i_24_n_6\,
O(0) => \cr_int_reg[7]_i_24_n_7\,
S(3) => \cr_int[7]_i_30_n_0\,
S(2) => \cr_int[7]_i_31_n_0\,
S(1) => \cr_int[7]_i_32_n_0\,
S(0) => \cr_int[7]_i_33_n_0\
);
\y_int[11]_i_54\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[11]_i_54_n_0\
);
\y_int[11]_i_55\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_6\,
O => \y_int[11]_i_55_n_0\
);
\y_int[11]_i_56\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_7\,
O => \y_int[11]_i_56_n_0\
);
\y_int[11]_i_57\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_4\,
O => \y_int[11]_i_57_n_0\
);
\y_int[15]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_36_n_0\
);
\y_int[15]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_37_n_0\
);
\y_int[15]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_38_n_0\
);
\y_int[15]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[15]_i_39_n_0\
);
\y_int[15]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_68,
O => \y_int[15]_i_44_n_0\
);
\y_int[15]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_69,
O => \y_int[15]_i_45_n_0\
);
\y_int[15]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_70,
O => \y_int[15]_i_46_n_0\
);
\y_int[15]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_71,
O => \y_int[15]_i_47_n_0\
);
\y_int[19]_i_36\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_36_n_0\
);
\y_int[19]_i_37\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_37_n_0\
);
\y_int[19]_i_38\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_38_n_0\
);
\y_int[19]_i_39\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[19]_i_39_n_0\
);
\y_int[19]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_5\,
O => \y_int[19]_i_40_n_0\
);
\y_int[19]_i_41\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_6\,
O => \y_int[19]_i_41_n_0\
);
\y_int[19]_i_42\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_7\,
O => \y_int[19]_i_42_n_0\
);
\y_int[19]_i_43\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[15]_i_24_n_4\,
O => \y_int[19]_i_43_n_0\
);
\y_int[19]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_64,
O => \y_int[19]_i_44_n_0\
);
\y_int[19]_i_45\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_65,
O => \y_int[19]_i_45_n_0\
);
\y_int[19]_i_46\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_66,
O => \y_int[19]_i_46_n_0\
);
\y_int[19]_i_47\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_67,
O => \y_int[19]_i_47_n_0\
);
\y_int[23]_i_50\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_50_n_0\
);
\y_int[23]_i_58\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_58_n_0\
);
\y_int[23]_i_59\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_59_n_0\
);
\y_int[23]_i_60\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_60_n_0\
);
\y_int[23]_i_61\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
O => \y_int[23]_i_61_n_0\
);
\y_int[31]_i_100\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(3),
I1 => rgb888(1),
I2 => rgb888(4),
I3 => rgb888(2),
O => \y_int[31]_i_100_n_0\
);
\y_int[31]_i_102\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_102_n_0\
);
\y_int[31]_i_103\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
O => \y_int[31]_i_103_n_0\
);
\y_int[31]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_22_n_0\
);
\y_int[31]_i_23\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_57_n_0\,
I2 => rgb888(14),
O => \y_int[31]_i_23_n_0\
);
\y_int[31]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => rgb888(15),
I1 => \y_int[31]_i_56_n_0\,
O => \y_int[31]_i_24_n_0\
);
\y_int[31]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(15),
O => \y_int[31]_i_25_n_0\
);
\y_int[31]_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => rgb888(15),
I1 => rgb888(14),
I2 => \y_int[31]_i_57_n_0\,
O => \y_int[31]_i_26_n_0\
);
\y_int[31]_i_28\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_32_n_7\,
O => \y_int[31]_i_28_n_0\
);
\y_int[31]_i_29\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_4\,
O => \y_int[31]_i_29_n_0\
);
\y_int[31]_i_38\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_58,
O => \y_int[31]_i_38_n_0\
);
\y_int[31]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_59,
O => \y_int[31]_i_39_n_0\
);
\y_int[31]_i_48\: unisim.vcomponents.LUT4
generic map(
INIT => X"1002"
)
port map (
I0 => rgb888(14),
I1 => rgb888(15),
I2 => \y_int[31]_i_80_n_0\,
I3 => rgb888(13),
O => \y_int[31]_i_48_n_0\
);
\y_int[31]_i_49\: unisim.vcomponents.LUT5
generic map(
INIT => X"81560042"
)
port map (
I0 => rgb888(13),
I1 => rgb888(12),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(15),
I4 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_49_n_0\
);
\y_int[31]_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A88A80808008"
)
port map (
I0 => \y_int[31]_i_83_n_0\,
I1 => rgb888(14),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => \y_int_reg[31]_i_82_n_6\,
O => \y_int[31]_i_50_n_0\
);
\y_int[31]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"9696966996000069"
)
port map (
I0 => rgb888(14),
I1 => rgb888(11),
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(13),
O => \y_int[31]_i_51_n_0\
);
\y_int[31]_i_52\: unisim.vcomponents.LUT4
generic map(
INIT => X"6559"
)
port map (
I0 => \y_int[31]_i_48_n_0\,
I1 => rgb888(15),
I2 => \y_int[31]_i_57_n_0\,
I3 => rgb888(14),
O => \y_int[31]_i_52_n_0\
);
\y_int[31]_i_53\: unisim.vcomponents.LUT6
generic map(
INIT => X"6CCCCCC9CCCCC993"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(14),
I2 => rgb888(12),
I3 => \y_int[31]_i_81_n_0\,
I4 => rgb888(13),
I5 => rgb888(15),
O => \y_int[31]_i_53_n_0\
);
\y_int[31]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"366C6CC96CC9C993"
)
port map (
I0 => \y_int[31]_i_84_n_0\,
I1 => rgb888(13),
I2 => \y_int[31]_i_81_n_0\,
I3 => rgb888(12),
I4 => rgb888(15),
I5 => \y_int_reg[31]_i_82_n_1\,
O => \y_int[31]_i_54_n_0\
);
\y_int[31]_i_55\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969666"
)
port map (
I0 => \y_int[31]_i_51_n_0\,
I1 => \y_int[31]_i_83_n_0\,
I2 => \y_int_reg[31]_i_82_n_6\,
I3 => \y_int[31]_i_85_n_0\,
I4 => rgb888(14),
O => \y_int[31]_i_55_n_0\
);
\y_int[31]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => rgb888(13),
I1 => rgb888(11),
I2 => rgb888(9),
I3 => rgb888(10),
I4 => rgb888(12),
I5 => rgb888(14),
O => \y_int[31]_i_56_n_0\
);
\y_int[31]_i_57\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => rgb888(12),
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(13),
O => \y_int[31]_i_57_n_0\
);
\y_int[31]_i_58\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_5\,
O => \y_int[31]_i_58_n_0\
);
\y_int[31]_i_59\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_6\,
O => \y_int[31]_i_59_n_0\
);
\y_int[31]_i_60\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[23]_i_35_n_7\,
O => \y_int[31]_i_60_n_0\
);
\y_int[31]_i_61\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => \y_int_reg[31]_i_9_n_5\,
I1 => U0_n_57,
I2 => \y_int_reg[19]_i_24_n_4\,
O => \y_int[31]_i_61_n_0\
);
\y_int[31]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(5),
I1 => rgb888(7),
O => \y_int[31]_i_72_n_0\
);
\y_int[31]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(6),
I1 => rgb888(7),
O => \y_int[31]_i_73_n_0\
);
\y_int[31]_i_74\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => rgb888(7),
I1 => rgb888(5),
I2 => rgb888(6),
O => \y_int[31]_i_74_n_0\
);
\y_int[31]_i_76\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_60,
O => \y_int[31]_i_76_n_0\
);
\y_int[31]_i_77\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_61,
O => \y_int[31]_i_77_n_0\
);
\y_int[31]_i_78\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_62,
O => \y_int[31]_i_78_n_0\
);
\y_int[31]_i_79\: unisim.vcomponents.LUT3
generic map(
INIT => X"47"
)
port map (
I0 => U0_n_55,
I1 => U0_n_56,
I2 => U0_n_63,
O => \y_int[31]_i_79_n_0\
);
\y_int[31]_i_80\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => rgb888(11),
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(12),
O => \y_int[31]_i_80_n_0\
);
\y_int[31]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_81_n_0\
);
\y_int[31]_i_83\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666999999996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_1\,
I1 => rgb888(15),
I2 => rgb888(11),
I3 => rgb888(9),
I4 => rgb888(10),
I5 => rgb888(12),
O => \y_int[31]_i_83_n_0\
);
\y_int[31]_i_84\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEABA802"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[31]_i_84_n_0\
);
\y_int[31]_i_85\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => rgb888(10),
I1 => rgb888(9),
I2 => rgb888(11),
O => \y_int[31]_i_85_n_0\
);
\y_int[31]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(4),
I1 => rgb888(6),
O => \y_int[31]_i_93_n_0\
);
\y_int[31]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(3),
I1 => rgb888(5),
O => \y_int[31]_i_94_n_0\
);
\y_int[31]_i_95\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(2),
I1 => rgb888(4),
O => \y_int[31]_i_95_n_0\
);
\y_int[31]_i_96\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => rgb888(1),
I1 => rgb888(3),
O => \y_int[31]_i_96_n_0\
);
\y_int[31]_i_97\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(6),
I1 => rgb888(4),
I2 => rgb888(7),
I3 => rgb888(5),
O => \y_int[31]_i_97_n_0\
);
\y_int[31]_i_98\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(5),
I1 => rgb888(3),
I2 => rgb888(6),
I3 => rgb888(4),
O => \y_int[31]_i_98_n_0\
);
\y_int[31]_i_99\: unisim.vcomponents.LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => rgb888(4),
I1 => rgb888(2),
I2 => rgb888(5),
I3 => rgb888(3),
O => \y_int[31]_i_99_n_0\
);
\y_int[3]_i_37\: unisim.vcomponents.LUT4
generic map(
INIT => X"8228"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(9),
I2 => rgb888(10),
I3 => rgb888(13),
O => \y_int[3]_i_37_n_0\
);
\y_int[3]_i_38\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => rgb888(9),
I1 => rgb888(10),
I2 => rgb888(13),
I3 => \y_int_reg[31]_i_82_n_7\,
O => \y_int[3]_i_38_n_0\
);
\y_int[3]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \y_int_reg[3]_i_40_n_4\,
I1 => rgb888(9),
I2 => rgb888(12),
O => \y_int[3]_i_39_n_0\
);
\y_int[3]_i_41\: unisim.vcomponents.LUT5
generic map(
INIT => X"99969699"
)
port map (
I0 => \y_int[3]_i_37_n_0\,
I1 => \y_int[3]_i_79_n_0\,
I2 => rgb888(13),
I3 => rgb888(10),
I4 => rgb888(9),
O => \y_int[3]_i_41_n_0\
);
\y_int[3]_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669696969696996"
)
port map (
I0 => \y_int_reg[31]_i_82_n_7\,
I1 => rgb888(13),
I2 => rgb888(10),
I3 => rgb888(12),
I4 => \y_int_reg[3]_i_40_n_4\,
I5 => rgb888(9),
O => \y_int[3]_i_42_n_0\
);
\y_int[3]_i_43\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696969"
)
port map (
I0 => rgb888(12),
I1 => rgb888(9),
I2 => \y_int_reg[3]_i_40_n_4\,
I3 => rgb888(11),
I4 => rgb888(8),
O => \y_int[3]_i_43_n_0\
);
\y_int[3]_i_44\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => rgb888(8),
I1 => rgb888(11),
I2 => \y_int_reg[3]_i_40_n_5\,
O => \y_int[3]_i_44_n_0\
);
\y_int[3]_i_46\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_5\,
O => \y_int[3]_i_46_n_0\
);
\y_int[3]_i_47\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_6\,
O => \y_int[3]_i_47_n_0\
);
\y_int[3]_i_48\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_7\,
O => \y_int[3]_i_48_n_0\
);
\y_int[3]_i_49\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_51,
O => \y_int[3]_i_49_n_0\
);
\y_int[3]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rgb888(15),
I1 => rgb888(13),
O => \y_int[3]_i_75_n_0\
);
\y_int[3]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(12),
I1 => rgb888(14),
O => \y_int[3]_i_76_n_0\
);
\y_int[3]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(11),
I1 => rgb888(13),
O => \y_int[3]_i_77_n_0\
);
\y_int[3]_i_78\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(10),
I1 => rgb888(12),
O => \y_int[3]_i_78_n_0\
);
\y_int[3]_i_79\: unisim.vcomponents.LUT5
generic map(
INIT => X"A95656A9"
)
port map (
I0 => \y_int_reg[31]_i_82_n_6\,
I1 => rgb888(10),
I2 => rgb888(9),
I3 => rgb888(11),
I4 => rgb888(14),
O => \y_int[3]_i_79_n_0\
);
\y_int[3]_i_80\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_52,
O => \y_int[3]_i_80_n_0\
);
\y_int[3]_i_81\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_53,
O => \y_int[3]_i_81_n_0\
);
\y_int[3]_i_82\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_54,
O => \y_int[3]_i_82_n_0\
);
\y_int[3]_i_83\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_70_n_6\,
O => \y_int[3]_i_83_n_0\
);
\y_int[3]_i_93\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(9),
I1 => rgb888(11),
O => \y_int[3]_i_93_n_0\
);
\y_int[3]_i_94\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => rgb888(8),
I1 => rgb888(10),
O => \y_int[3]_i_94_n_0\
);
\y_int[3]_i_95\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rgb888(9),
O => \y_int[3]_i_95_n_0\
);
\y_int[3]_i_96\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => rgb888(8),
O => \y_int[3]_i_96_n_0\
);
\y_int[7]_i_25\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_5\,
O => \y_int[7]_i_25_n_0\
);
\y_int[7]_i_26\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_6\,
O => \y_int[7]_i_26_n_0\
);
\y_int[7]_i_27\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[31]_i_21_n_7\,
O => \y_int[7]_i_27_n_0\
);
\y_int[7]_i_28\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \y_int_reg[3]_i_19_n_4\,
O => \y_int[7]_i_28_n_0\
);
\y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[7]_i_23_n_0\,
CO(3) => \y_int_reg[11]_i_27_n_0\,
CO(2) => \y_int_reg[11]_i_27_n_1\,
CO(1) => \y_int_reg[11]_i_27_n_2\,
CO(0) => \y_int_reg[11]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[11]_i_27_n_4\,
O(2) => \y_int_reg[11]_i_27_n_5\,
O(1) => \y_int_reg[11]_i_27_n_6\,
O(0) => \y_int_reg[11]_i_27_n_7\,
S(3) => \y_int[11]_i_54_n_0\,
S(2) => \y_int[11]_i_55_n_0\,
S(1) => \y_int[11]_i_56_n_0\,
S(0) => \y_int[11]_i_57_n_0\
);
\y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[11]_i_27_n_0\,
CO(3) => \y_int_reg[15]_i_24_n_0\,
CO(2) => \y_int_reg[15]_i_24_n_1\,
CO(1) => \y_int_reg[15]_i_24_n_2\,
CO(0) => \y_int_reg[15]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[15]_i_24_n_4\,
O(2) => \y_int_reg[15]_i_24_n_5\,
O(1) => \y_int_reg[15]_i_24_n_6\,
O(0) => \y_int_reg[15]_i_24_n_7\,
S(3) => \y_int[15]_i_36_n_0\,
S(2) => \y_int[15]_i_37_n_0\,
S(1) => \y_int[15]_i_38_n_0\,
S(0) => \y_int[15]_i_39_n_0\
);
\y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_81,
CO(3) => \y_int_reg[15]_i_34_n_0\,
CO(2) => \y_int_reg[15]_i_34_n_1\,
CO(1) => \y_int_reg[15]_i_34_n_2\,
CO(0) => \y_int_reg[15]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(12 downto 9),
S(3) => \y_int[15]_i_44_n_0\,
S(2) => \y_int[15]_i_45_n_0\,
S(1) => \y_int[15]_i_46_n_0\,
S(0) => \y_int[15]_i_47_n_0\
);
\y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_24_n_0\,
CO(3) => \y_int_reg[19]_i_24_n_0\,
CO(2) => \y_int_reg[19]_i_24_n_1\,
CO(1) => \y_int_reg[19]_i_24_n_2\,
CO(0) => \y_int_reg[19]_i_24_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_24_n_4\,
O(2) => \y_int_reg[19]_i_24_n_5\,
O(1) => \y_int_reg[19]_i_24_n_6\,
O(0) => \y_int_reg[19]_i_24_n_7\,
S(3) => \y_int[19]_i_36_n_0\,
S(2) => \y_int[19]_i_37_n_0\,
S(1) => \y_int[19]_i_38_n_0\,
S(0) => \y_int[19]_i_39_n_0\
);
\y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_79,
CO(3) => \y_int_reg[19]_i_33_n_0\,
CO(2) => \y_int_reg[19]_i_33_n_1\,
CO(1) => \y_int_reg[19]_i_33_n_2\,
CO(0) => \y_int_reg[19]_i_33_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[19]_i_33_n_4\,
O(2) => \y_int_reg[19]_i_33_n_5\,
O(1) => \y_int_reg[19]_i_33_n_6\,
O(0) => \y_int_reg[19]_i_33_n_7\,
S(3) => \y_int[19]_i_40_n_0\,
S(2) => \y_int[19]_i_41_n_0\,
S(1) => \y_int[19]_i_42_n_0\,
S(0) => \y_int[19]_i_43_n_0\
);
\y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[15]_i_34_n_0\,
CO(3) => \y_int_reg[19]_i_34_n_0\,
CO(2) => \y_int_reg[19]_i_34_n_1\,
CO(1) => \y_int_reg[19]_i_34_n_2\,
CO(0) => \y_int_reg[19]_i_34_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(16 downto 13),
S(3) => \y_int[19]_i_44_n_0\,
S(2) => \y_int[19]_i_45_n_0\,
S(1) => \y_int[19]_i_46_n_0\,
S(0) => \y_int[19]_i_47_n_0\
);
\y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[23]_i_35_n_0\,
CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1),
O(0) => \y_int_reg[23]_i_32_n_7\,
S(3 downto 1) => B"000",
S(0) => \y_int[23]_i_50_n_0\
);
\y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_24_n_0\,
CO(3) => \y_int_reg[23]_i_35_n_0\,
CO(2) => \y_int_reg[23]_i_35_n_1\,
CO(1) => \y_int_reg[23]_i_35_n_2\,
CO(0) => \y_int_reg[23]_i_35_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[23]_i_35_n_4\,
O(2) => \y_int_reg[23]_i_35_n_5\,
O(1) => \y_int_reg[23]_i_35_n_6\,
O(0) => \y_int_reg[23]_i_35_n_7\,
S(3) => \y_int[23]_i_58_n_0\,
S(2) => \y_int[23]_i_59_n_0\,
S(1) => \y_int[23]_i_60_n_0\,
S(0) => \y_int[23]_i_61_n_0\
);
\y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_27_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_10_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_10_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_10_n_6\,
O(0) => \y_int_reg[31]_i_10_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_28_n_0\,
S(0) => \y_int[31]_i_29_n_0\
);
\y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_37_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_12_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_12_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_int_reg2(22 downto 21),
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_38_n_0\,
S(0) => \y_int[31]_i_39_n_0\
);
\y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_19_n_0\,
CO(3) => \y_int_reg[31]_i_21_n_0\,
CO(2) => \y_int_reg[31]_i_21_n_1\,
CO(1) => \y_int_reg[31]_i_21_n_2\,
CO(0) => \y_int_reg[31]_i_21_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_48_n_0\,
DI(2) => \y_int[31]_i_49_n_0\,
DI(1) => \y_int[31]_i_50_n_0\,
DI(0) => \y_int[31]_i_51_n_0\,
O(3) => \y_int_reg[31]_i_21_n_4\,
O(2) => \y_int_reg[31]_i_21_n_5\,
O(1) => \y_int_reg[31]_i_21_n_6\,
O(0) => \y_int_reg[31]_i_21_n_7\,
S(3) => \y_int[31]_i_52_n_0\,
S(2) => \y_int[31]_i_53_n_0\,
S(1) => \y_int[31]_i_54_n_0\,
S(0) => \y_int[31]_i_55_n_0\
);
\y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_33_n_0\,
CO(3) => \y_int_reg[31]_i_27_n_0\,
CO(2) => \y_int_reg[31]_i_27_n_1\,
CO(1) => \y_int_reg[31]_i_27_n_2\,
CO(0) => \y_int_reg[31]_i_27_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[31]_i_27_n_4\,
O(2) => \y_int_reg[31]_i_27_n_5\,
O(1) => \y_int_reg[31]_i_27_n_6\,
O(0) => \y_int_reg[31]_i_27_n_7\,
S(3) => \y_int[31]_i_58_n_0\,
S(2) => \y_int[31]_i_59_n_0\,
S(1) => \y_int[31]_i_60_n_0\,
S(0) => \y_int[31]_i_61_n_0\
);
\y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_71_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_31_n_2\,
CO(0) => \y_int_reg[31]_i_31_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => rgb888(6),
DI(0) => \y_int[31]_i_72_n_0\,
O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_31_n_5\,
O(1) => \y_int_reg[31]_i_31_n_6\,
O(0) => \y_int_reg[31]_i_31_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_73_n_0\,
S(0) => \y_int[31]_i_74_n_0\
);
\y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[19]_i_34_n_0\,
CO(3) => \y_int_reg[31]_i_37_n_0\,
CO(2) => \y_int_reg[31]_i_37_n_1\,
CO(1) => \y_int_reg[31]_i_37_n_2\,
CO(0) => \y_int_reg[31]_i_37_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => y_int_reg2(20 downto 17),
S(3) => \y_int[31]_i_76_n_0\,
S(2) => \y_int[31]_i_77_n_0\,
S(1) => \y_int[31]_i_78_n_0\,
S(0) => \y_int[31]_i_79_n_0\
);
\y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_80,
CO(3) => \y_int_reg[31]_i_71_n_0\,
CO(2) => \y_int_reg[31]_i_71_n_1\,
CO(1) => \y_int_reg[31]_i_71_n_2\,
CO(0) => \y_int_reg[31]_i_71_n_3\,
CYINIT => '0',
DI(3) => \y_int[31]_i_93_n_0\,
DI(2) => \y_int[31]_i_94_n_0\,
DI(1) => \y_int[31]_i_95_n_0\,
DI(0) => \y_int[31]_i_96_n_0\,
O(3) => \y_int_reg[31]_i_71_n_4\,
O(2) => \y_int_reg[31]_i_71_n_5\,
O(1) => \y_int_reg[31]_i_71_n_6\,
O(0) => \y_int_reg[31]_i_71_n_7\,
S(3) => \y_int[31]_i_97_n_0\,
S(2) => \y_int[31]_i_98_n_0\,
S(1) => \y_int[31]_i_99_n_0\,
S(0) => \y_int[31]_i_100_n_0\
);
\y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_40_n_0\,
CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3),
CO(2) => \y_int_reg[31]_i_82_n_1\,
CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1),
CO(0) => \y_int_reg[31]_i_82_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1 downto 0) => rgb888(15 downto 14),
O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2),
O(1) => \y_int_reg[31]_i_82_n_6\,
O(0) => \y_int_reg[31]_i_82_n_7\,
S(3 downto 2) => B"01",
S(1) => \y_int[31]_i_102_n_0\,
S(0) => \y_int[31]_i_103_n_0\
);
\y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[31]_i_21_n_0\,
CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2),
CO(1) => \y_int_reg[31]_i_9_n_2\,
CO(0) => \y_int_reg[31]_i_9_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \y_int[31]_i_22_n_0\,
DI(0) => \y_int[31]_i_23_n_0\,
O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3),
O(2) => \y_int_reg[31]_i_9_n_5\,
O(1) => \y_int_reg[31]_i_9_n_6\,
O(0) => \y_int_reg[31]_i_9_n_7\,
S(3) => '0',
S(2) => \y_int[31]_i_24_n_0\,
S(1) => \y_int[31]_i_25_n_0\,
S(0) => \y_int[31]_i_26_n_0\
);
\y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4
port map (
CI => U0_n_78,
CO(3) => \y_int_reg[3]_i_19_n_0\,
CO(2) => \y_int_reg[3]_i_19_n_1\,
CO(1) => \y_int_reg[3]_i_19_n_2\,
CO(0) => \y_int_reg[3]_i_19_n_3\,
CYINIT => '0',
DI(3) => \y_int[3]_i_37_n_0\,
DI(2) => \y_int[3]_i_38_n_0\,
DI(1) => \y_int[3]_i_39_n_0\,
DI(0) => \y_int_reg[3]_i_40_n_5\,
O(3) => \y_int_reg[3]_i_19_n_4\,
O(2) => \y_int_reg[3]_i_19_n_5\,
O(1) => \y_int_reg[3]_i_19_n_6\,
O(0) => \y_int_reg[3]_i_19_n_7\,
S(3) => \y_int[3]_i_41_n_0\,
S(2) => \y_int[3]_i_42_n_0\,
S(1) => \y_int[3]_i_43_n_0\,
S(0) => \y_int[3]_i_44_n_0\
);
\y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_45_n_0\,
CO(3) => \y_int_reg[3]_i_20_n_0\,
CO(2) => \y_int_reg[3]_i_20_n_1\,
CO(1) => \y_int_reg[3]_i_20_n_2\,
CO(0) => \y_int_reg[3]_i_20_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[3]_i_20_n_4\,
O(2) => \y_int_reg[3]_i_20_n_5\,
O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0),
S(3) => \y_int[3]_i_46_n_0\,
S(2) => \y_int[3]_i_47_n_0\,
S(1) => \y_int[3]_i_48_n_0\,
S(0) => \y_int[3]_i_49_n_0\
);
\y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_70_n_0\,
CO(3) => \y_int_reg[3]_i_40_n_0\,
CO(2) => \y_int_reg[3]_i_40_n_1\,
CO(1) => \y_int_reg[3]_i_40_n_2\,
CO(0) => \y_int_reg[3]_i_40_n_3\,
CYINIT => '0',
DI(3) => rgb888(15),
DI(2 downto 0) => rgb888(12 downto 10),
O(3) => \y_int_reg[3]_i_40_n_4\,
O(2) => \y_int_reg[3]_i_40_n_5\,
O(1) => \y_int_reg[3]_i_40_n_6\,
O(0) => \y_int_reg[3]_i_40_n_7\,
S(3) => \y_int[3]_i_75_n_0\,
S(2) => \y_int[3]_i_76_n_0\,
S(1) => \y_int[3]_i_77_n_0\,
S(0) => \y_int[3]_i_78_n_0\
);
\y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_45_n_0\,
CO(2) => \y_int_reg[3]_i_45_n_1\,
CO(1) => \y_int_reg[3]_i_45_n_2\,
CO(0) => \y_int_reg[3]_i_45_n_3\,
CYINIT => \cb_int[3]_i_84_n_0\,
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0),
S(3) => \y_int[3]_i_80_n_0\,
S(2) => \y_int[3]_i_81_n_0\,
S(1) => \y_int[3]_i_82_n_0\,
S(0) => \y_int[3]_i_83_n_0\
);
\y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y_int_reg[3]_i_70_n_0\,
CO(2) => \y_int_reg[3]_i_70_n_1\,
CO(1) => \y_int_reg[3]_i_70_n_2\,
CO(0) => \y_int_reg[3]_i_70_n_3\,
CYINIT => '0',
DI(3 downto 2) => rgb888(9 downto 8),
DI(1 downto 0) => B"01",
O(3) => \y_int_reg[3]_i_70_n_4\,
O(2) => \y_int_reg[3]_i_70_n_5\,
O(1) => \y_int_reg[3]_i_70_n_6\,
O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0),
S(3) => \y_int[3]_i_93_n_0\,
S(2) => \y_int[3]_i_94_n_0\,
S(1) => \y_int[3]_i_95_n_0\,
S(0) => \y_int[3]_i_96_n_0\
);
\y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4
port map (
CI => \y_int_reg[3]_i_20_n_0\,
CO(3) => \y_int_reg[7]_i_23_n_0\,
CO(2) => \y_int_reg[7]_i_23_n_1\,
CO(1) => \y_int_reg[7]_i_23_n_2\,
CO(0) => \y_int_reg[7]_i_23_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \y_int_reg[7]_i_23_n_4\,
O(2) => \y_int_reg[7]_i_23_n_5\,
O(1) => \y_int_reg[7]_i_23_n_6\,
O(0) => \y_int_reg[7]_i_23_n_7\,
S(3) => \y_int[7]_i_25_n_0\,
S(2) => \y_int[7]_i_26_n_0\,
S(1) => \y_int[7]_i_27_n_0\,
S(0) => \y_int[7]_i_28_n_0\
);
end STRUCTURE;
| mit | 61b04781da1ab36478be2969aa72a051 | 0.480125 | 2.231807 | false | false | false | false |
loa-org/loa-hdl | modules/io/hdl/shiftout.vhd | 2 | 5,679 | -------------------------------------------------------------------------------
-- Title : Shift Out Register (74HC(T)595 and similar types)
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian@kleinvieh>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- Maximum frequency 74HC595 : 100 MHz
-- 74HCT595 : 57 MHz
--
-- At 50 MHz it takes about 360ns (+ 25ns propgation delay from the 74HCT595)
-- until the output is visible at the outputs. The maximum latency of 380ns
-- appears it a transaction is has started directly before the transaction.
--
-- ## Pins
--
-- Master Reset (Pin 10) should be connected to high-level,
-- Output Enable (Pin 13) should be at low-level.
--
-- ## Waveform
--
-- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
-- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-- clke __| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |
-- ___ ___ ___ ___ ___ ___ ___ ___
-- sck ______| |___| |___| |___| |___| |___| |___| |___| |_________
-- _______ _______ _______ _______ _______ _______ _______ _______
-- dout __X_______X_______X_______X_______X_______X_______X_______X_______X_________
-- bit 0 1 2 3 4 5 6 7 8 9
-- ___
-- load ______________________________________________________________________| |__
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package shiftout_pkg is
type shiftout_out_type is record
sck : std_logic; -- or SH_CP (Pin 11)
dout : std_logic; -- or DS (Pin 14)
load : std_logic; -- or ST_CP (Pin 12)
end record;
component shiftout is
port (
register_p : out shiftout_out_type;
value_p : in std_logic_vector(7 downto 0);
clk : in std_logic);
end component shiftout;
end package shiftout_pkg;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.shiftout_pkg.all;
entity shiftout is
port (
register_p : out shiftout_out_type;
value_p : in std_logic_vector(7 downto 0);
clk : in std_logic
);
end entity shiftout;
architecture behavioral of shiftout is
signal clk_enable : std_logic := '1'; -- clock enable for the SCK speed
type shiftout_state_type is (
STATE_IDLE, STATE_WRITE, STATE_WRITE_NEXT, STATE_LOAD, STATE_LOAD_WAIT);
type shiftout_type is record
state : shiftout_state_type;
value : std_logic_vector(7 downto 0); -- copy of the input value
-- value currently loaded into the shift register
value_buffer : std_logic_vector(7 downto 0);
bitcount : integer range 0 to 9; -- Number of bits loaded
o : shiftout_out_type;
end record shiftout_type;
signal r, rin : shiftout_type := (
state => STATE_IDLE,
value => (others => '0'),
value_buffer => (others => '0'),
bitcount => 0,
o => (
sck => '0',
dout => '0',
load => '0'));
begin
seq_proc : process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process (clk_enable, r, r.bitcount, r.o, r.state, r.value,
r.value_buffer(6 downto 0), r.value_buffer(7), value_p) is
variable v : shiftout_type;
begin
v := r;
case r.state is
when STATE_IDLE =>
-- Wait until the input changes
if r.value /= value_p then
v.value := value_p;
v.value_buffer := value_p;
v.bitcount := 0;
v.state := STATE_WRITE_NEXT;
end if;
-- Clock high
when STATE_WRITE =>
if clk_enable = '1' then
v.o.sck := '1';
v.state := STATE_WRITE_NEXT;
end if;
-- Clock low and switch to the next bit
when STATE_WRITE_NEXT =>
if clk_enable = '1' then
v.o.sck := '0';
-- MSB first
v.o.dout := r.value_buffer(7);
v.value_buffer := r.value_buffer(6 downto 0) & '0';
v.bitcount := r.bitcount + 1;
if r.bitcount = 8 then
v.state := STATE_LOAD;
else
v.state := STATE_WRITE;
end if;
end if;
-- Load high
when STATE_LOAD =>
if clk_enable = '1' then
v.o.dout := '0';
v.o.load := '1';
v.state := STATE_LOAD_WAIT;
end if;
-- Load low
when STATE_LOAD_WAIT =>
if clk_enable = '1' then
v.o.load := '0';
v.state := STATE_IDLE;
end if;
end case;
-- register outputs
register_p <= r.o;
rin <= v;
end process comb_proc;
-- TODO clk_enable generation
-- to adapt to higher clk frequencies
end architecture behavioral;
| bsd-3-clause | 52eaae57ffcb0056012cb9b2ad79c23a | 0.420497 | 4.056429 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl | 1 | 17,470 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 02:51:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0_vga_sync is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_0_0_vga_sync : entity is "vga_sync";
end system_vga_sync_0_0_vga_sync;
architecture STRUCTURE of system_vga_sync_0_0_vga_sync is
signal active0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal active_i_3_n_0 : STD_LOGIC;
signal \h_count_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sel : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of hsync_i_2 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair1";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000A2A"
)
port map (
I0 => active_i_3_n_0,
I1 => \^xaddr\(8),
I2 => \^xaddr\(9),
I3 => \^xaddr\(7),
I4 => \^yaddr\(9),
O => active0
);
active_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst,
O => active_i_2_n_0
);
active_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
O => active_i_3_n_0
);
active_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => active0,
Q => active
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => p_0_in(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
O => p_0_in(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => p_0_in(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
O => p_0_in(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
O => p_0_in(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33332333CCCCCCCC"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(7),
I1 => \h_count_reg[9]_i_2_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
O => p_0_in(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFFFFF7C0000000"
)
port map (
I0 => \^xaddr\(9),
I1 => \h_count_reg[9]_i_2_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(7),
I4 => \^xaddr\(6),
I5 => \^xaddr\(8),
O => \h_count_reg[8]_i_1_n_0\
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F80EF00FF00FF00"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(9)
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
I3 => \^xaddr\(4),
I4 => \^xaddr\(3),
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(0),
Q => \^xaddr\(0)
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(1),
Q => \^xaddr\(1)
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(2),
Q => \^xaddr\(2)
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(3),
Q => \^xaddr\(3)
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(4),
Q => \^xaddr\(4)
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(5),
Q => \^xaddr\(5)
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(6),
Q => \^xaddr\(6)
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(7),
Q => \^xaddr\(7)
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => \h_count_reg[8]_i_1_n_0\,
Q => \^xaddr\(8)
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => p_0_in(9),
Q => \^xaddr\(9)
);
hsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFBFBFBFBFFF"
)
port map (
I0 => \^xaddr\(8),
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => hsync_i_2_n_0,
I4 => \^xaddr\(5),
I5 => \^xaddr\(6),
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(3),
I3 => \^xaddr\(1),
I4 => \^xaddr\(0),
O => hsync_i_2_n_0
);
hsync_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => hsync_i_1_n_0,
Q => hsync
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555554"
)
port map (
I0 => \^yaddr\(0),
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(7),
I3 => \^yaddr\(4),
I4 => \^yaddr\(8),
I5 => \^yaddr\(6),
O => \p_0_in__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \p_0_in__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"78007878"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
I2 => \^yaddr\(2),
I3 => \v_count_reg[9]_i_4_n_0\,
I4 => \v_count_reg[9]_i_3_n_0\,
O => \p_0_in__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F8000007F807F80"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(2),
I3 => \^yaddr\(3),
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \v_count_reg[9]_i_3_n_0\,
O => \p_0_in__0\(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \p_0_in__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(3),
I4 => \^yaddr\(2),
I5 => \^yaddr\(4),
O => \p_0_in__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^yaddr\(6),
I1 => \v_count_reg[9]_i_6_n_0\,
I2 => \^yaddr\(5),
O => \p_0_in__0\(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \v_count_reg[9]_i_6_n_0\,
I3 => \^yaddr\(6),
O => \p_0_in__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \^yaddr\(5),
I3 => \^yaddr\(7),
I4 => \v_count_reg[9]_i_6_n_0\,
O => \p_0_in__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000002000"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(5),
I5 => \^xaddr\(6),
O => sel
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"D00DD0D0D0D0D0D0"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => \^yaddr\(8),
I5 => \v_count_reg[9]_i_6_n_0\,
O => \p_0_in__0\(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(4),
I2 => \^yaddr\(8),
I3 => \^yaddr\(6),
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFFFFFFFFFF"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(5),
I3 => \^yaddr\(9),
I4 => \^yaddr\(2),
I5 => \^yaddr\(3),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^yaddr\(6),
I1 => \^yaddr\(5),
I2 => \^yaddr\(7),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(0),
Q => \^yaddr\(0)
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(1),
Q => \^yaddr\(1)
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(2),
Q => \^yaddr\(2)
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(3),
Q => \^yaddr\(3)
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(4),
Q => \^yaddr\(4)
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(5),
Q => \^yaddr\(5)
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(6),
Q => \^yaddr\(6)
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(7),
Q => \^yaddr\(7)
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(8),
Q => \^yaddr\(8)
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => active_i_2_n_0,
D => \p_0_in__0\(9),
Q => \^yaddr\(9)
);
vsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFFFFFFFF"
)
port map (
I0 => active_i_3_n_0,
I1 => \^yaddr\(9),
I2 => \^yaddr\(3),
I3 => \^yaddr\(4),
I4 => \^yaddr\(2),
I5 => \^yaddr\(1),
O => vsync_i_1_n_0
);
vsync_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => active_i_2_n_0,
D => vsync_i_1_n_0,
Q => vsync
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_0_0 : entity is "system_vga_sync_0_0,vga_sync,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_0_0 : entity is "vga_sync,Vivado 2016.4";
end system_vga_sync_0_0;
architecture STRUCTURE of system_vga_sync_0_0 is
begin
U0: entity work.system_vga_sync_0_0_vga_sync
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 4b9e5952431fd0ea96535e0ba92f028e | 0.484888 | 2.727557 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/system_rgb565_to_rgb888_1_0_sim_netlist.vhdl | 1 | 5,724 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:56 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb565_to_rgb888_1_0 -prefix
-- system_rgb565_to_rgb888_1_0_ system_rgb565_to_rgb888_0_0_sim_netlist.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_1_0_rgb565_to_rgb888 is
port (
rgb_888 : out STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC
);
end system_rgb565_to_rgb888_1_0_rgb565_to_rgb888;
architecture STRUCTURE of system_rgb565_to_rgb888_1_0_rgb565_to_rgb888 is
begin
\rgb_888_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(5),
Q => rgb_888(5),
R => '0'
);
\rgb_888_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(6),
Q => rgb_888(6),
R => '0'
);
\rgb_888_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(7),
Q => rgb_888(7),
R => '0'
);
\rgb_888_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(8),
Q => rgb_888(8),
R => '0'
);
\rgb_888_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(9),
Q => rgb_888(9),
R => '0'
);
\rgb_888_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(10),
Q => rgb_888(10),
R => '0'
);
\rgb_888_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(11),
Q => rgb_888(11),
R => '0'
);
\rgb_888_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(12),
Q => rgb_888(12),
R => '0'
);
\rgb_888_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(13),
Q => rgb_888(13),
R => '0'
);
\rgb_888_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(14),
Q => rgb_888(14),
R => '0'
);
\rgb_888_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(15),
Q => rgb_888(15),
R => '0'
);
\rgb_888_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(0),
Q => rgb_888(0),
R => '0'
);
\rgb_888_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(1),
Q => rgb_888(1),
R => '0'
);
\rgb_888_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(2),
Q => rgb_888(2),
R => '0'
);
\rgb_888_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(3),
Q => rgb_888(3),
R => '0'
);
\rgb_888_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => rgb_565(4),
Q => rgb_888(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb565_to_rgb888_1_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb565_to_rgb888_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb565_to_rgb888_1_0 : entity is "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb565_to_rgb888_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb565_to_rgb888_1_0 : entity is "rgb565_to_rgb888,Vivado 2016.4";
end system_rgb565_to_rgb888_1_0;
architecture STRUCTURE of system_rgb565_to_rgb888_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 20 downto 3 );
begin
rgb_888(23 downto 21) <= \^rgb_888\(18 downto 16);
rgb_888(20 downto 16) <= \^rgb_888\(20 downto 16);
rgb_888(15 downto 14) <= \^rgb_888\(9 downto 8);
rgb_888(13 downto 3) <= \^rgb_888\(13 downto 3);
rgb_888(2) <= \<const0>\;
rgb_888(1) <= \<const0>\;
rgb_888(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_rgb565_to_rgb888_1_0_rgb565_to_rgb888
port map (
clk => clk,
rgb_565(15 downto 0) => rgb_565(15 downto 0),
rgb_888(15 downto 13) => \^rgb_888\(18 downto 16),
rgb_888(12 downto 11) => \^rgb_888\(20 downto 19),
rgb_888(10 downto 9) => \^rgb_888\(9 downto 8),
rgb_888(8 downto 5) => \^rgb_888\(13 downto 10),
rgb_888(4 downto 0) => \^rgb_888\(7 downto 3)
);
end STRUCTURE;
| mit | 20e8f8b37a9cd24b3ffadf626271e983 | 0.532669 | 3.05606 | false | false | false | false |
loa-org/loa-hdl | modules/fifo_sync/hdl/fifo_sync.vhd | 1 | 3,523 | -------------------------------------------------------------------------------
-- Title : Synchronous FIFO
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A very plain FIFO, synchronous interfaces.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fifo_sync_pkg.all;
-------------------------------------------------------------------------------
entity fifo_sync is
generic (
DATA_WIDTH : positive;
ADDRESS_WIDTH : positive
);
port (
-- write side
di : in std_logic_vector(data_width -1 downto 0);
wr : in std_logic;
full : out std_logic;
-- read side
do : out std_logic_vector(data_width -1 downto 0);
rd : in std_logic;
empty : out std_logic;
valid : out std_logic; -- strobed once per word read
clk : in std_logic
);
end fifo_sync;
-------------------------------------------------------------------------------
architecture behavioural of fifo_sync is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
constant ADD_TOP : positive := (2**address_width)-1;
type mem_type is array(0 to ADD_TOP) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal mem : mem_type;
signal head : unsigned (address_width-1 downto 0) := (others => '0');
signal tail : unsigned (address_width-1 downto 0) := (others => '0');
signal full_s : std_logic := '0';
signal empty_s : std_logic := '0';
signal valid_s : std_logic := '0';
signal do_s : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
-- assign to ports
full <= full_s;
empty <= empty_s;
valid <= valid_s;
do <= do_s;
-- determine flags
full_s <= '1' when tail = head+1 else '0';
empty_s <= '1' when tail = head else '0';
-----------------------------------------------------------------------------
-- one process FSM
-----------------------------------------------------------------------------
process (CLK, di, wr, rd, full_s, empty_s)
begin
if rising_edge(CLK) then
if (wr = '1' and full_s = '0') then
mem(to_integer(head)) <= di;
head <= head + 1;
end if;
if (rd = '1' and empty_s = '0') then
do_s <= std_logic_vector(mem(to_integer(tail)));
valid_s <= '1';
tail <= tail + 1;
else
valid_s <= '0';
end if;
end if;
end process;
end behavioural;
| bsd-3-clause | f6842fdbd3c8aefb66a4913ebdb52b27 | 0.399659 | 4.68484 | false | false | false | false |
pgavin/carpe | hdl/cpu/btb/miss/cpu_btb_miss-rtl.vhdl | 1 | 1,447 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
architecture rtl of cpu_btb_miss is
begin
cpu_btb_miss_ctrl_out <= (
rvalid => '0'
);
cpu_btb_miss_dp_out <= (
rstate => void,
rtarget => (others => 'X')
);
end;
| apache-2.0 | 6805edaf192f84a1fd89ec232efccc92 | 0.480304 | 5.077193 | false | false | false | false |
loa-org/loa-hdl | modules/ds18b20/hdl/ds18b20.vhd | 1 | 6,993 | -------------------------------------------------------------------------------
-- Title : DS18b20 Reader
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Description: Trigger by the "refresh" signal this ip-core requests a
-- temperature reading from the connected DS18b20 sensor.
--
-- Uses the skip rom command to avoid handling ROM-IDs of sensors.
-- Only a single sensor can be used.
--
-- DS18b20 Sequence is:
-- reset bus
-- skip rom (0xcc)
-- convert emperature (0x44)
-- read bytes - sensor active while 0 are read
-- reset bus
-- skip rom (0xcc)
-- "read scratchpad" (0xbe)
-- Rx Temperature LSB
-- Rx Temperature MSB
-- (drop the rest and idle)
--
-------------------------------------------------------------------------------
-- Created : 2014-12-14
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.onewire_pkg.all;
use work.ds18b20_pkg.all;
entity ds18b20 is
port (
ow_out : in onewire_out_type;
ow_in : out onewire_in_type;
ds18b20_in : in ds18b20_in_type;
ds18b20_out : out ds18b20_out_type;
clk : in std_logic);
end ds18b20;
architecture behavioural of ds18b20 is
type ds18b20_state_type is (idle,
reset1, reset2,
skip_rom1, skip_rom2,
conv_temp1, conv_temp2,
wait_for_conversion1, wait_for_conversion2, wait_for_conversion3,
reset3, reset4,
skip_rom3, skip_rom4,
read_sp1, read_sp2, read_sp3, read_sp4, read_sp5, read_sp6);
type ds18b20_type is record
state : ds18b20_state_type;
ow_in : onewire_in_type;
ds18b20_out : ds18b20_out_type;
byte_cnt : integer range 0 to 3;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : ds18b20_type := (state => IDLE,
ow_in => (d => (others => '0'), re => '0', we => '0', reset_bus => '0'),
ds18b20_out => (value => (others => '0'), update => '0', err => '0'),
byte_cnt => 0);
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
ds18b20_out <= r.ds18b20_out;
ow_in <= r.ow_in;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(ds18b20_in, ow_out, r)
variable v : ds18b20_type;
begin
v := r;
case r.state is
when idle =>
if ds18b20_in.refresh = '1' then
v.state := reset1;
v.ow_in.reset_bus := '1';
end if;
when reset1 =>
v.ow_in.reset_bus := '0';
v.state := reset2;
when reset2 =>
if ow_out.busy = '0' then
v.state := skip_rom1;
v.ow_in.d := x"CC";
v.ow_in.we := '1';
end if;
when skip_rom1 =>
v.ow_in.we := '0';
v.state := skip_rom2;
when skip_rom2 =>
if ow_out.busy = '0' then
v.state := conv_temp1;
v.ow_in.d := x"44";
v.ow_in.we := '1';
end if;
when conv_temp1 =>
v.ow_in.we := '0';
v.state := conv_temp2;
when conv_temp2 =>
if ow_out.busy = '0' then
v.state := wait_for_conversion1;
end if;
when wait_for_conversion1 =>
v.ow_in.re := '1';
v.state := wait_for_conversion2;
when wait_for_conversion2 =>
v.ow_in.re := '0';
v.state := wait_for_conversion3;
when wait_for_conversion3 =>
if ow_out.busy = '0' then
if ow_out.d = x"ff" then
v.state := reset3;
v.ow_in.reset_bus := '1';
else
v.state := wait_for_conversion1;
end if;
end if;
when reset3 =>
v.ow_in.reset_bus := '0';
v.state := reset4;
when reset4 =>
if ow_out.busy = '0' then
v.state := skip_rom3;
v.ow_in.d := x"CC";
v.ow_in.we := '1';
end if;
when skip_rom3 =>
v.ow_in.we := '0';
v.state := skip_rom4;
when skip_rom4 =>
if ow_out.busy = '0' then
v.state := read_sp1;
end if;
when read_sp1 =>
v.ow_in.d := x"be";
v.ow_in.we := '1';
v.byte_cnt := 0;
v.state := read_sp2;
when read_sp2 =>
v.ow_in.we := '0';
v.state := read_sp3;
when read_sp3 =>
if ow_out.busy = '0' then
v.state := read_sp4;
end if;
when read_sp4 =>
v.ow_in.re := '1';
v.state := read_sp5;
when read_sp5 =>
v.ow_in.re := '0';
v.state := read_sp6;
when read_sp6 =>
if ow_out.busy = '0' then
if v.byte_cnt = 0 then
v.ds18b20_out.value(7 downto 0) := ow_out.d;
v.byte_cnt := v.byte_cnt + 1;
v.state := read_sp4;
elsif v.byte_cnt = 1 then
v.ds18b20_out.value(15 downto 8) := ow_out.d;
v.state := idle;
end if;
end if;
when others =>
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | 752c204db634482cd6fc0f2e90a5a58f | 0.394966 | 3.946388 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd | 1 | 8,234 | -- niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 10;
FIFO_DEPTH : integer := 4;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 0;
USE_MEMORY_BLOCKS : integer := 0;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(9 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_data : out std_logic_vector(9 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_endofpacket : in std_logic := '0';
in_error : in std_logic := '0';
in_startofpacket : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_endofpacket : out std_logic;
out_error : out std_logic;
out_startofpacket : out std_logic
);
end entity niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo;
architecture rtl of niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(9 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(9 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo
| apache-2.0 | b0948d1965ac5c96d902492621fe564d | 0.436483 | 3.920952 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/DE2_CONSTANTS.vhd | 1 | 2,089 | library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_SEVEN_SEGMENT is array (6 downto 0) of std_logic;
constant sev_seg_0 : std_logic_vector( 6 downto 0) := not b"0111111"; -- ~0x3f
constant sev_seg_1 : std_logic_vector( 6 downto 0) := not b"0000110"; -- ~0x06
constant sev_seg_2 : std_logic_vector( 6 downto 0) := not b"1011011"; -- ~0x5b
constant sev_seg_3 : std_logic_vector( 6 downto 0) := not b"1001111"; -- ~0x4f
constant sev_seg_4 : std_logic_vector( 6 downto 0) := not b"1100110"; -- ~0x66
constant sev_seg_5 : std_logic_vector( 6 downto 0) := not b"1101101"; -- ~0x6d
constant sev_seg_6 : std_logic_vector( 6 downto 0) := not b"1111101"; -- ~0x7D
constant sev_seg_7 : std_logic_vector( 6 downto 0) := not b"0000111"; -- ~0x07
constant sev_seg_8 : std_logic_vector( 6 downto 0) := not b"1111111"; -- ~0x7f
constant sev_seg_9 : std_logic_vector( 6 downto 0) := not b"1101111"; -- ~0x6f
constant sev_seg_a : std_logic_vector( 6 downto 0) := not b"1110111"; -- ~0x77
constant sev_seg_b : std_logic_vector( 6 downto 0) := not b"1111100"; -- ~0x7c
constant sev_seg_c : std_logic_vector( 6 downto 0) := not b"0111001"; -- ~0x39
constant sev_seg_d : std_logic_vector( 6 downto 0) := not b"1011110"; -- ~0x5e
constant sev_seg_e : std_logic_vector( 6 downto 0) := not b"1111001"; -- ~0x79
constant sev_seg_f : std_logic_vector( 6 downto 0) := not b"1110001"; -- ~0x71
end DE2_CONSTANTS; | apache-2.0 | f5c5c2d27665c81814a42765222218e2 | 0.6764 | 2.522947 | false | false | false | false |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 12,865 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue May 20 11:28:03 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 2;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
--AUDIO ports to top layer
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 downto 0);
--AC_SDA : INOUT std_logic;
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : OUT std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
COMPONENT adau1761 is
PORT(
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
AUDIO_OUT_L :OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R :OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L :IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R :IN STD_LOGIC_VECTOR(23 downto 0);
--AC_SDA : INOUT std_logic;
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : OUT std_logic;
sw : in STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(1 downto 0);
signal slv_reg_read_sel : std_logic_vector(1 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal AUDIO_OUT_L_s : std_logic_vector(23 downto 0);
signal AUDIO_OUT_R_s : std_logic_vector(23 downto 0);
signal AUDIO_IN_L_s : std_logic_vector(23 downto 0);
signal AUDIO_IN_R_s : std_logic_vector(23 downto 0);
signal clk_48_s : std_logic;
begin
--USER logic implementation added here
AUDIO_IN_L_s <= AUDIO_IN_L;
AUDIO_IN_R_s <= AUDIO_IN_R;
clk_48_o <= clk_48_s;
AUDIO_OUT_L <= AUDIO_OUT_L_s; -- AUDIO_OUT data to the next buffer
AUDIO_OUT_R <= AUDIO_OUT_R_s;
--
adau1761_internal: adau1761 PORT MAP (
clk_100 => clk_100,
clk_48_o => clk_48_s,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
new_sample => new_sample,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
AUDIO_OUT_L => AUDIO_OUT_L_s,
AUDIO_OUT_R => AUDIO_OUT_R_s,
AUDIO_IN_L => AUDIO_IN_L_s,
AUDIO_IN_R => AUDIO_IN_R_s,
sw=> "00000001"
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(1 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(1 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
--clk_48_o <= clk_48_s;
-- slv_reg0(23 downto 0) <= AUDIO_OUT_R_s; -- AUDIO_OUT data to AXI bus
-- slv_reg1(23 downto 0) <= AUDIO_OUT_L_s;
-- AUDIO_OUT_L <= AUDIO_OUT_R_s; -- AUDIO_OUT data to the next buffer
-- AUDIO_OUT_R <= AUDIO_OUT_L_s;
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_sel is
when "10" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_reg0;
when "01" => slv_ip2bus_data <= slv_reg1;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | e4ea1996a3bfaa57f93410ecb34be979 | 0.493043 | 3.835719 | false | false | false | false |
loa-org/loa-hdl | modules/utils/hdl/clock_divider.vhd | 2 | 1,185 | --!
--! Generic clock divider
--!
--! Generates an clock enable signal.
--!
--! Example:
--! @code
--! process (clk)
--! begin
--! if rising_edge(clk) then
--! if enable = '1' then
--! ... do something with the period of the divided frequency ...
--! end if;
--! end if;
--! end process;
--! @endcode
--!
--! @author Fabian Greif
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_divider is
generic (
DIV : positive := 2);
port (
clk_out_p : out std_logic := '0'; -- Enable output ('1' for one clock cycle)
clk : in std_logic -- System clock
);
end clock_divider;
-- ----------------------------------------------------------------------------
architecture behavior of clock_divider is
begin
process
variable counter : integer range 0 to DIV := 0;
begin
wait until rising_edge(clk);
counter := counter + 1;
if counter = DIV then
counter := 0;
clk_out_p <= '1';
else
clk_out_p <= '0';
end if;
end process;
end behavior;
| bsd-3-clause | 5f75278a9c55ed1925ef0a1e97f44bf3 | 0.481857 | 3.761905 | false | false | false | false |
pgavin/carpe | hdl/util/logic_pkg.vhdl | 1 | 9,461 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.numeric_pkg.all;
package logic_pkg is
pure function reduce_or(v : std_ulogic_vector) return std_ulogic;
pure function reduce_and(v : std_ulogic_vector) return std_ulogic;
pure function reduce_xor(v : std_ulogic_vector) return std_ulogic;
pure function all_ones(v : std_ulogic_vector) return std_ulogic;
pure function all_zeros(v : std_ulogic_vector) return std_ulogic;
pure function any_ones(v : std_ulogic_vector) return std_ulogic;
pure function any_zeros(v : std_ulogic_vector) return std_ulogic;
pure function logic_eq(v1 : std_ulogic_vector; v2 : std_ulogic_vector) return std_ulogic;
pure function logic_ne(v1 : std_ulogic_vector; v2 : std_ulogic_vector) return std_ulogic;
pure function logic_if(p : std_ulogic; c : std_ulogic; a : std_ulogic) return std_ulogic;
pure function logic_if(p : std_ulogic; c : std_ulogic_vector; a : std_ulogic_vector) return std_ulogic_vector;
pure function reverse(v : std_ulogic_vector) return std_ulogic_vector;
pure function prioritize(v : std_ulogic_vector) return std_ulogic_vector;
pure function prioritize_least(v : std_ulogic_vector) return std_ulogic_vector;
pure function prioritize_none(v : std_ulogic_vector) return std_ulogic_vector;
pure function is_1hot(v : std_ulogic_vector) return std_ulogic;
pure function lfsr_taps(n : natural) return std_ulogic_vector;
end package;
package body logic_pkg is
pure function reduce_or(v : std_ulogic_vector) return std_ulogic is
begin
for i in v'range loop
case v(i) is
when '1' =>
return '1';
when '0' =>
null;
when others =>
return 'X';
end case;
end loop;
return '0';
end function;
pure function reduce_and(v : std_ulogic_vector) return std_ulogic is
variable ret : std_ulogic;
begin
for i in v'range loop
case v(i) is
when '0' =>
return '0';
when '1' =>
null;
when others =>
return 'X';
end case;
end loop;
return '1';
end function;
pure function reduce_xor(v : std_ulogic_vector) return std_ulogic is
variable ret : std_ulogic;
begin
ret := '0';
for i in v'range loop
ret := ret xor v(i);
end loop;
end function;
pure function all_ones(v : std_ulogic_vector) return std_ulogic is
begin
return reduce_and(v);
end function;
pure function all_zeros(v : std_ulogic_vector) return std_ulogic is
begin
return not reduce_or(v);
end function;
pure function any_ones(v : std_ulogic_vector) return std_ulogic is
begin
return reduce_or(v);
end function;
pure function any_zeros(v : std_ulogic_vector) return std_ulogic is
begin
return not reduce_and(v);
end function;
pure function logic_eq(v1 : std_ulogic_vector; v2 : std_ulogic_vector) return std_ulogic is
begin
-- pragma translate_off
if is_x(v1) or is_x(v2) then
return 'X';
else
-- pragma translate_on
if v1 = v2 then
return '1';
else
return '0';
end if;
-- pragma translate_off
end if;
-- pragma translate_on
end function;
pure function logic_ne(v1 : std_ulogic_vector; v2 : std_ulogic_vector) return std_ulogic is
begin
-- pragma translate_off
if is_x(v1) or is_x(v2) then
return 'X';
else
-- pragma translate_on
if v1 /= v2 then
return '1';
else
return '0';
end if;
-- pragma translate_off
end if;
-- pragma translate_on
end function;
pure function logic_if(p : std_ulogic; c : std_ulogic; a : std_ulogic) return std_ulogic is
variable ret : std_ulogic;
begin
case p is
when '1' => ret := c;
when '0' => ret := a;
when others => ret := 'X';
end case;
return ret;
end function;
pure function logic_if(p : std_ulogic; c : std_ulogic_vector; a : std_ulogic_vector) return std_ulogic_vector is
variable ret : std_ulogic_vector(c'range);
begin
case p is
when '1' => ret := c;
when '0' => ret := a;
when others => ret := (others => 'X');
end case;
return ret;
end function;
pure function reverse(v : std_ulogic_vector) return std_ulogic_vector is
variable ret : std_ulogic_vector(v'range);
begin
for n in v'range loop
ret(v'high - n + v'low) := ret(n);
end loop;
return ret;
end function;
-- prioritize (from highest index to lowest index) a bit vector.
-- the result is a 1-hot vector
-- clears all bits except the highest '1' on the input vector
-- e.g. "0110010" => "0100000"
-- "101" => "100"
-- "000" => "XXX"
pure function prioritize(v : std_ulogic_vector) return std_ulogic_vector is
variable ret : std_ulogic_vector(v'range);
begin
ret := (others => '0');
for i in v'high downto v'low loop
case v(i) is
when '1' =>
ret(i) := '1';
return ret;
when '0' =>
null;
when others =>
return (v'range => 'X');
end case;
end loop;
return (v'range => 'X');
end function;
-- like prioritize, but chooses least significant set bit
pure function prioritize_least(v : std_ulogic_vector) return std_ulogic_vector is
variable ret : std_ulogic_vector(v'range);
begin
ret := (others => '0');
for i in v'low to v'high loop
case v(i) is
when '1' =>
ret(i) := '1';
return ret;
when '0' =>
null;
when others =>
return (v'range => 'X');
end case;
end loop;
return (v'range => 'X');
end function;
-- like prioritize, but allows no bits set
pure function prioritize_none(v : std_ulogic_vector) return std_ulogic_vector is
variable ret : std_ulogic_vector(v'range);
begin
ret := (others => '0');
for i in v'low to v'high loop
case v(i) is
when '1' =>
ret(i) := '1';
exit;
when '0' =>
null;
when others =>
return (v'range => 'X');
end case;
end loop;
return ret;
end function;
pure function is_1hot(v : std_ulogic_vector) return std_ulogic is
variable ret : std_ulogic;
begin
ret := '1';
if v'length > 1 then
for n in v'low to v'high-1 loop
for m in n+1 to v'high loop
ret := ret and not (v(n) and v(m));
end loop;
end loop;
end if;
return ret;
end;
-- return a set of taps for an LFSR that generates the maximal length sequence on the given number of bits
pure function lfsr_taps(n : natural) return std_ulogic_vector is
begin
case n is
when 1 => return "1";
when 2 => return "11";
when 3 => return "110";
when 4 => return "1100";
when 5 => return "10100";
when 6 => return "110000";
when 7 => return "1100000";
when 8 => return "11100001";
when 9 => return "100010000";
when 10 => return "1001000000";
when 11 => return "10100000000";
when 12 => return "111000001000";
when 13 => return "1110010000000";
when 14 => return "11100000000010";
when 15 => return "110000000000000";
when 16 => return "1101000000001000";
when 17 => return "10010000000000000";
when 18 => return "100000010000000000";
when 19 => return "1110010000000000000";
when 20 => return "10010000000000000000";
when 21 => return "101000000000000000000";
when 22 => return "1100000000000000000000";
when 23 => return "10000100000000000000000";
when 24 => return "111000010000000000000000";
when 25 => return "1001000000000000000000000";
when 26 => return "11100010000000000000000000";
when 27 => return "111001000000000000000000000";
when 28 => return "1001000000000000000000000000";
when 29 => return "10100000000000000000000000000";
when 30 => return "111000000000000000000001000000";
when 31 => return "1001000000000000000000000000000";
when 32 => return "11100000000000000000001000000000";
when others => return (n-1 downto 0 => 'X');
end case;
end function;
end package body;
| apache-2.0 | fffebeadc68b19e6c7e7c226f687917b | 0.592961 | 3.836577 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_feature_transform/vga_feature_transform.srcs/sources_1/new/feature_buffer_block.vhd | 3 | 2,475 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity feature_buffer_block is
generic (
PARITY : std_logic := '0'
);
port (
clk_x2 : in std_logic;
enable : in std_logic;
clear : in std_logic;
x_in_left : in std_logic_vector(9 downto 0);
y_in_left : in std_logic_vector(9 downto 0);
hessian_in_left : in std_logic_vector(31 downto 0);
x_in_right : in std_logic_vector(9 downto 0);
y_in_right : in std_logic_vector(9 downto 0);
hessian_in_right : in std_logic_vector(31 downto 0);
x_out_left : out std_logic_vector(9 downto 0);
y_out_left : out std_logic_vector(9 downto 0);
hessian_out_left : out std_logic_vector(31 downto 0);
x_out_right : out std_logic_vector(9 downto 0);
y_out_right : out std_logic_vector(9 downto 0);
hessian_out_right : out std_logic_vector(31 downto 0)
);
end feature_buffer_block;
architecture Behavioral of feature_buffer_block is
signal hessian : unsigned(31 downto 0) := x"00000000";
signal x : std_logic_vector(9 downto 0) := "0000000000";
signal y : std_logic_vector(9 downto 0) := "0000000000";
signal cycle : std_logic := '0';
begin
hessian_out_left <= std_logic_vector(hessian);
x_out_left <= x;
y_out_left <= y;
hessian_out_right <= std_logic_vector(hessian);
x_out_right <= x;
y_out_right <= y;
process(clk_x2)
begin
if rising_edge(clk_x2) then
if clear = '1' then
hessian <= x"00000000";
x <= "0000000000";
y <= "0000000000";
cycle <= '0';
else
if enable = '1' then
if PARITY = cycle then
if hessian > unsigned(hessian_in_right) then
hessian <= unsigned(hessian_in_right);
x <= x_in_right;
y <= y_in_right;
end if;
else
if hessian < unsigned(hessian_in_left) then
hessian <= unsigned(hessian_in_left);
x <= x_in_left;
y <= y_in_left;
end if;
end if;
cycle <= not cycle;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 4c942adf1b72517dd409734da9030a30 | 0.502222 | 3.688525 | false | false | false | false |
pgavin/carpe | hdl/tech/inferred/div_seq_inferred-rtl.vhdl | 1 | 4,465 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
architecture rtl of div_seq_inferred is
type comb_type is record
dbz : std_ulogic;
overflow : std_ulogic;
src1_tmp : std_ulogic_vector(src1_bits downto 0);
src2_tmp : std_ulogic_vector(src2_bits downto 0);
end record;
signal c : comb_type;
type pipe_type is array(latency-1 downto 0) of std_ulogic_vector(src1_bits downto 0);
type reg_type is record
status : std_ulogic_vector(latency-1 downto 0);
pipe : pipe_type;
dbz : std_ulogic;
overflow : std_ulogic;
end record;
constant reg_x : reg_type := (
status => (others => 'X'),
pipe => (others => (others => 'X')),
dbz => 'X',
overflow => 'X'
);
signal r, r_next : reg_type;
pure function div(src1, src2 : std_ulogic_vector(src1_bits downto 0)) return std_ulogic_vector is
variable ret : std_ulogic_vector(src1_bits downto 0);
begin
-- pragma translate_off
if is_x(src1) or is_x(src2) or src2 = (src1_bits downto 0 => '0') then
ret := (others => 'X');
else
-- pragma translate_on
ret := std_ulogic_vector(signed(src1) / signed(src2));
-- pragma translate_off
end if;
-- pragma translate_on
return ret;
end function;
begin
c.src1_tmp <= (src1(src1_bits-1) and not unsgnd) & src1;
c.src2_tmp <= (src2(src2_bits-1) and not unsgnd) & src2;
c.dbz <= all_zeros(src2);
c.overflow <= (not unsgnd and
-- e.g. (signed) 0x80000000 / 0xffffffff = 0x80000000
-- so result is not representable
src1(src1_bits-1) and all_zeros(src1(src1_bits-2 downto 0)) and
all_ones(src2)
);
with en select
r_next.dbz <= c.dbz when '1',
r.dbz when '0',
'X' when others;
with en select
r_next.overflow <= c.overflow when '1',
r.overflow when '0',
'X' when others;
with en select
r_next.pipe(0) <= r.pipe(0) when '0',
div(c.src1_tmp, c.src2_tmp) when '1',
(others => 'X') when others;
status_latency_gt_1 : if latency > 1 generate
r_next.status(latency-1) <= (r.status(latency-1) or r.status(latency-2)) and not en;
status_latency_gt_2 : if latency > 2 generate
status_loop : for n in latency-2 downto 1 generate
r_next.status(n) <= r.status(n-1) and not en;
end generate;
end generate;
r_next.status(0) <= en and not c.dbz and not c.overflow;
end generate;
status_latency_eq_1 : if latency = 1 generate
r_next.status(0) <= (r.status(0) or en) and not c.dbz and not c.overflow;
end generate;
pipe_loop : for n in latency-1 downto 1 generate
with en select
r_next.pipe(n) <= r.pipe(n-1) when '0',
(others => 'X') when others;
end generate;
valid <= r.status(latency-1) or r.dbz or r.overflow;
result <= r.pipe(latency-1)(src1_bits-1 downto 0);
dbz <= r.dbz;
overflow <= r.overflow;
seq : process(clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
| apache-2.0 | 3dd0a259b6387773ca53ae87fed0e6a4 | 0.545801 | 3.687036 | false | false | false | false |
ashikpoojari/Hardware-Security | RC5 CryptoCore/Rc5 Codes/RoundKeyGenerator.vhd | 2 | 5,694 | Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use Work.RC5_Pkg.all;
Entity rc5_rnd_key Is
Port
(
clr : in std_logic;
clk : in std_logic;
key_vld : in std_logic;
key_in : in Std_logic_vector (127 downto 0);
skey : out rom;
key_rdy : out std_logic
);
End rc5_rnd_key;
Architecture rtl of rc5_rnd_key Is
signal a : Std_logic_vector (31 downto 0);
signal a_circ : Std_logic_vector (31 downto 0);
signal a_reg : Std_logic_vector (31 downto 0);
signal b : Std_logic_vector (31 downto 0);
signal b_reg : Std_logic_vector (31 downto 0);
signal temp : Std_logic_vector (31 downto 0);
signal b_circ : Std_logic_vector (31 downto 0);
signal s : rom;
signal L : L_rom;
signal i_cnt : Std_logic_vector (26 downto 0);
signal j_cnt : Std_logic_vector (3 downto 0);
signal r_cnt : Std_logic_vector (77 downto 0);
Type StateType is ( --Type for state machine
ST_idle,
ST_key_in,
ST_key_exp,
ST_ready
);
Signal state : StateType; --Signal type of state machine
Begin
a <= s(conv_integer(i_cnt)) + a_reg + b_reg;
a_circ <= a (28 downto 0) & a (31 downto 29);
b <= L(conv_integer(j_cnt)) + a_circ + b_reg;
temp <= a_circ + b_reg;
with temp (4 downto 0) select
b_circ <= b(30 downto 0) & b(31) when "00001",
b(29 downto 0) & b(31 downto 30) when "00010",
b(28 downto 0) & b(31 downto 29) when "00011",
b(27 downto 0) & b(31 downto 28) when "00100",
b(26 downto 0) & b(31 downto 27) when "00101",
b(25 downto 0) & b(31 downto 26) when "00110",
b(24 downto 0) & b(31 downto 25) when "00111",
b(23 downto 0) & b(31 downto 24) when "01000",
b(22 downto 0) & b(31 downto 23) when "01001",
b(21 downto 0) & b(31 downto 22) when "01010",
b(20 downto 0) & b(31 downto 21) when "01011",
b(19 downto 0) & b(31 downto 20) when "01100",
b(18 downto 0) & b(31 downto 19) when "01101",
b(17 downto 0) & b(31 downto 18) when "01110",
b(16 downto 0) & b(31 downto 17) when "01111",
b(15 downto 0) & b(31 downto 16) when "10000",
b(14 downto 0) & b(31 downto 15) when "10001",
b(13 downto 0) & b(31 downto 14) when "10010",
b(12 downto 0) & b(31 downto 13) when "10011",
b(11 downto 0) & b(31 downto 12) when "10100",
b(10 downto 0) & b(31 downto 11) when "10101",
b(9 downto 0) & b(31 downto 10) when "10110",
b(8 downto 0) & b(31 downto 9) when "10111",
b(7 downto 0) & b(31 downto 8) when "11000",
b(6 downto 0) & b(31 downto 7) when "11001",
b(5 downto 0) & b(31 downto 6) when "11010",
b(4 downto 0) & b(31 downto 5) when "11011",
b(3 downto 0) & b(31 downto 4) when "11100",
b(2 downto 0) & b(31 downto 3) when "11101",
b(1 downto 0) & b(31 downto 2) when "11110",
b(0) & b(31 downto 1) when "11111",
b when others;
Process (clr, clk) Begin
If (clr = '0') then
state <= ST_idle;
Elsif (clk'event and clk = '1') then
Case state is
When ST_idle => If (key_vld = '1') then state <= ST_key_in; end if;
When ST_key_in => state <= ST_key_exp;
When ST_key_exp => If (r_cnt = "1001101") then state <= ST_ready; end if;
When ST_ready => state <= ST_idle;
End Case;
End if;
End Process;
Process (clr, clk) Begin
If (clr = '0') then
a_reg <= (others => '0');
Elsif (clk'event and clk = '1') then
If (state = ST_key_exp) then
a_reg <= a_circ;
End if;
End if;
End Process;
Process (clr, clk) Begin
If (clr = '0') then
b_reg <= (others => '0');
Elsif (clk'event and clk = '1') then
If (state = ST_key_exp) then
b_reg <= b_circ;
End if;
End if;
End Process;
Process (clr, clk) Begin
If (clr = '0') then
i_cnt <= (others => '0');
Elsif (clk'event and clk = '1') then
If (state = ST_key_exp) then
If (i_cnt = "11001") then
i_cnt <= (others => '0');
Else
i_cnt <= i_cnt+1;
End if;
End If;
End if;
End Process;
Process (clr, clk) Begin
If (clr = '0') then
j_cnt <= (others => '0');
Elsif (clk'event and clk = '1') then
If (state = ST_key_exp) then
If (j_cnt = "00011") then
j_cnt <= (others => '0');
Else
j_cnt <= j_cnt+1;
End If;
End if;
End if;
End Process;
Process (clr, clk) Begin
If (clr = '0') then
r_cnt <= (others => '0');
Elsif (clk'event and clk = '1') then
If (state = ST_key_exp) then r_cnt <= r_cnt + '1'; End If;
End if;
End Process;
Process (clr, clk) Begin
If (clr = '0') then
s(0) <= X"b7e15163"; s(1) <= X"5618cb1c";s(2) <= X"f45044d5";s(3) <= X"9287be8e";s(4) <= X"30bf3847";s(5) <= X"cef6b200";s(6) <= X"6d2e2bb9";s(7) <= X"0b65a572";s(8) <= X"a99d1f2b";s(9) <= X"47d498e4";s(10) <= X"e60c129d";s(11) <= X"84438c56";s(12) <= X"227b060f";s(13) <= X"c0b27fc8";s(14) <= X"5ee9f981";s(15) <= X"fd21733a";s(16) <= X"9b58ecf3";s(17) <= X"399066ac";s(18) <= X"d7c7e065";s(19) <= X"75ff5a1e";s(20) <= X"1436d3d7";s(21) <= X"b26e4d90";s(22) <= X"50a5c749";s(23) <= X"eedd4102";s(24) <= X"8d14babb";s(25) <= X"2b4c3474";
Elsif (clk'event and clk = '1') then
If (state = ST_key_exp) then
s(conv_integer(i_cnt)) <= a_circ;
End if;
End if;
End Process;
Process (clr, clk) Begin
If (clr = '0') then
L(0) <= (Others => '0');
L(1) <= (Others => '0');
L(2) <= (Others => '0');
L(3) <= (Others => '0');
Elsif (clk'event and clk = '1') then
If (state = ST_key_in) then
L(0) <= key_in(31 downto 0);
L(1) <= key_in(63 downto 32);
L(2) <= key_in(95 downto 64);
L(3) <= key_in(127 downto 96);
Elsif (state = ST_key_exp) then
L(conv_integer(j_cnt)) <= b_circ;
End if;
End if;
End Process;
skey <= s;
With state Select
key_rdy <= '1' when ST_ready,
'0' when others;
End rtl;
| mit | 16e9e87d50c5d1bdf2b0e67b443841a0 | 0.575342 | 2.367568 | false | false | false | false |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/niosii_system_nios2_qsys_0_jtag_debug_module_translator.vhd | 1 | 14,814 | -- niosii_system_nios2_qsys_0_jtag_debug_module_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_nios2_qsys_0_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 9;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(8 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_debugaccess : out std_logic; -- .debugaccess
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_nios2_qsys_0_jtag_debug_module_translator;
architecture rtl of niosii_system_nios2_qsys_0_jtag_debug_module_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_debugaccess : out std_logic; -- debugaccess
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
nios2_qsys_0_jtag_debug_module_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_debugaccess => av_debugaccess, -- .debugaccess
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_nios2_qsys_0_jtag_debug_module_translator
| apache-2.0 | 88dc4ef01f61aa601bdad4f7c29985fd | 0.430606 | 4.351939 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/synth/system_ov7670_controller_0_0.vhd | 3 | 4,423 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_0_0_arch : ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
| mit | 78333c0a882dd523fc772fbf00176917 | 0.732534 | 3.914159 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/inst/cache/cpu_l1mem_inst_cache_pkg.vhdl | 1 | 9,294 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
use work.cpu_l1mem_inst_cache_config_pkg.all;
use work.cpu_l1mem_inst_types_pkg.all;
use work.cpu_types_pkg.all;
package cpu_l1mem_inst_cache_pkg is
constant cpu_l1mem_inst_cache_assoc : natural := 2**cpu_l1mem_inst_cache_log2_assoc;
type cpu_l1mem_inst_cache_ctrl_in_type is record
-- when '1' indicates a new request, must be '0' while
-- waiting for a miss return, otherwise '1' will cancel
-- a pending request
request : cpu_l1mem_inst_request_code_type;
cacheen : std_ulogic;
mmuen : std_ulogic;
alloc : std_ulogic;
priv : std_ulogic;
direction : cpu_l1mem_inst_fetch_direction_type;
end record;
type cpu_l1mem_inst_cache_dp_in_type is record
vaddr : cpu_ivaddr_type;
end record;
type cpu_l1mem_inst_cache_ctrl_out_type is record
ready : std_ulogic;
result : cpu_l1mem_inst_result_code_type;
end record;
type cpu_l1mem_inst_cache_dp_out_type is record
paddr : cpu_ipaddr_type;
data : cpu_inst_type;
end record;
constant cpu_l1mem_inst_cache_block_insts : natural := 2**cpu_l1mem_inst_cache_offset_bits;
constant cpu_l1mem_inst_cache_tag_bits : natural := cpu_ipaddr_bits - cpu_l1mem_inst_cache_index_bits - cpu_l1mem_inst_cache_offset_bits;
type cpu_l1mem_inst_cache_owner_index_type is (
cpu_l1mem_inst_cache_owner_index_none,
cpu_l1mem_inst_cache_owner_index_request,
cpu_l1mem_inst_cache_owner_index_bus_op
);
type cpu_l1mem_inst_cache_owner_type is
array (cpu_l1mem_inst_cache_owner_index_type range
cpu_l1mem_inst_cache_owner_index_type'high downto
cpu_l1mem_inst_cache_owner_index_type'low) of std_ulogic;
constant cpu_l1mem_inst_cache_owner_none : cpu_l1mem_inst_cache_owner_type := "001";
constant cpu_l1mem_inst_cache_owner_request : cpu_l1mem_inst_cache_owner_type := "010";
constant cpu_l1mem_inst_cache_owner_bus_op : cpu_l1mem_inst_cache_owner_type := "100";
type cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_index_type is (
cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_index_old,
cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_index_request
);
type cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_type is
array (cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_index_type range
cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_index_type'high downto
cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_old : cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_type := "01";
constant cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_request : cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_type := "10";
type cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_index_type is (
cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_index_old,
cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_index_request
);
type cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_type is
array (cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_index_type range
cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_index_type'high downto
cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_old : cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_type := "01";
constant cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_request : cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_type := "10";
type cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_type is (
cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_old,
cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_next,
cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_request
);
type cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_type is
array (cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_type range
cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_type'high downto
cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_old : cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_type := "001";
constant cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_next : cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_type := "010";
constant cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_request : cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_type := "100";
type cpu_l1mem_inst_cache_b_result_inst_sel_index_type is (
cpu_l1mem_inst_cache_b_result_inst_sel_index_b_cache,
cpu_l1mem_inst_cache_b_result_inst_sel_index_b_bus
);
type cpu_l1mem_inst_cache_b_result_inst_sel_type is
array (cpu_l1mem_inst_cache_b_result_inst_sel_index_type range
cpu_l1mem_inst_cache_b_result_inst_sel_index_type'high downto
cpu_l1mem_inst_cache_b_result_inst_sel_index_type'low) of std_ulogic;
constant cpu_l1mem_inst_cache_b_result_inst_sel_b_cache : cpu_l1mem_inst_cache_b_result_inst_sel_type := "01";
constant cpu_l1mem_inst_cache_b_result_inst_sel_b_bus : cpu_l1mem_inst_cache_b_result_inst_sel_type := "10";
type cpu_l1mem_inst_cache_dp_in_ctrl_type is record
a_bus_op_paddr_tag_sel : cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_type;
a_bus_op_paddr_index_sel : cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_type;
a_bus_op_paddr_offset_sel : cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_type;
a_bus_op_cache_paddr_sel_old : std_ulogic;
a_cache_owner : cpu_l1mem_inst_cache_owner_type;
b_request_complete : std_ulogic;
b_cache_owner : cpu_l1mem_inst_cache_owner_type;
b_cache_read_data_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_replace_way : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_result_inst_sel : cpu_l1mem_inst_cache_b_result_inst_sel_type;
end record;
type cpu_l1mem_inst_cache_dp_out_ctrl_type is record
b_request_last_in_block : std_ulogic;
b_request_cache_tag_match : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
end record;
type cpu_l1mem_inst_cache_ctrl_out_vram_type is record
re : std_ulogic;
we : std_ulogic;
wdata : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
end record;
type cpu_l1mem_inst_cache_ctrl_in_vram_type is record
rdata : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
end record;
type cpu_l1mem_inst_cache_dp_out_vram_type is record
raddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
waddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
end record;
type cpu_l1mem_inst_cache_ctrl_out_tram_type is record
en : std_ulogic;
we : std_ulogic;
banken : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
end record;
type cpu_l1mem_inst_cache_dp_in_tram_type is record
rdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_l1mem_inst_cache_tag_bits-1 downto 0);
end record;
type cpu_l1mem_inst_cache_dp_out_tram_type is record
addr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
wdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_l1mem_inst_cache_tag_bits-1 downto 0);
end record;
type cpu_l1mem_inst_cache_ctrl_out_dram_type is record
en : std_ulogic;
we : std_ulogic;
banken : std_ulogic_vector(2**cpu_l1mem_inst_cache_log2_assoc-1 downto 0);
end record;
type cpu_l1mem_inst_cache_dp_in_dram_type is record
rdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
end record;
type cpu_l1mem_inst_cache_dp_out_dram_type is record
addr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto 0);
wdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
end record;
end package;
| apache-2.0 | 4e03cb836be58f97aabb53dc9e2abb25 | 0.664407 | 2.858813 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/vga_hessian/vga_hessian.srcs/sources_1/ip/blk_mem_gen_0/synth/blk_mem_gen_0.vhd | 4 | 15,236 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_" &
"loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C" &
"_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=" &
"0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 22.1485 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 16,
C_READ_WIDTH_A => 16,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 16,
C_READ_WIDTH_B => 16,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 22.1485 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;
| mit | 51eb293749b8874b22c35a4961c85ef4 | 0.630218 | 3.018225 | false | false | false | false |
loa-org/loa-hdl | modules/hdlc/hdl/hdlc_busmaster.vhd | 1 | 11,329 | -------------------------------------------------------------------------------
-- Title : Busmaster with HDLC Interface
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Decode 8-Bit HDLC Async framing int 8-Bit Data + Frame Delimiter
--
-- Read access:
-- frame delimiter
-- cmd - 0x10
-- addr - ...
-- crc
--
-- frame delimiter
-- 0x11
-- data msb
-- data lsb
--
--
--
-- Write access:
-- frame delimiter
-- cmd - 0x20
-- addr - ...
-- data
-- crc
--
-- Write reply:
-- frame delimiter
-- 0x21
--
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
use work.hdlc_crc_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_busmaster is
port(
din_p : in hdlc_dec_out_type;
dout_p : out hdlc_enc_in_type;
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
clk : in std_logic);
end hdlc_busmaster;
-------------------------------------------------------------------------------
architecture behavioural of hdlc_busmaster is
type hdlc_busmaster_state_type is (IDLE, -- idling, waiting for a frame delimiter to arrive
RX_FRAME_CMD, -- CMD Byte
RX_FRAME_ADDR_MSB, -- ADDR MSB
RX_FRAME_ADDR_LSB, -- ADDR LSB
RX_FRAME_DATA_MSB, -- data
RX_FRAME_DATA_LSB, -- data
RX_FRAME_CRC,
BAD_CRC_REPLY_1,
BAD_CRC_REPLY_2,
BAD_CRC_REPLY_3,
BAD_CRC_REPLY_4,
RD_CYCLE_1, -- these are the states for the read
RD_CYCLE_2, -- access to the bus.
RD_CYCLE_3, -- access to the bus.
RD_REPLY_1, -- reply 1
RD_REPLY_2, -- reply 2
RD_REPLY_3, -- reply 3
RD_REPLY_3_WS, -- reply 3, waitstate
RD_REPLY_4, -- reply 4
RD_REPLY_4_WS, -- reply 4, waitstate
RD_REPLY_5, -- reply 5
RD_REPLY_6, -- reply 6
WR_CYCLE_1, --write access to bus
WR_CYCLE_2, -- 2nd write cycle
WR_REPLY_1, -- reply cycle of write
WR_REPLY_2, -- reply 2
WR_REPLY_3, -- reply 3
WR_REPLY_4 -- reply 3
);
type hdlc_busmaster_type is record
state : hdlc_busmaster_state_type;
bus_o : busmaster_out_type;
cmd : std_logic_vector(7 downto 0);
addr : std_logic_vector(15 downto 0);
data : std_logic_vector(15 downto 0);
dout : hdlc_enc_in_type;
crc_inc : std_logic_vector(7 downto 0);
crc_out : std_logic_vector(7 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : hdlc_busmaster_type := (
state => IDLE,
bus_o => (addr => (others => '0'), data => (others => '0'), re => '0', we => '0'),
cmd => (others => '0'),
addr => (others => '0'),
data => x"5678",
dout => (data => (others => '0'), enable => '0'),
crc_inc => (others => '0'),
crc_out => (others => '0'));
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
bus_o <= r.bus_o;
dout_p <= r.dout;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(din_p, bus_i, r)
variable v : hdlc_busmaster_type;
begin
v := r;
v.bus_o.we := '0';
v.bus_o.re := '0';
case r.state is
when IDLE => -- idling, waiting for a frame delimiter to arrive
if din_p.enable = '1' then
if din_p.data(8) = '1' then
v.state := RX_FRAME_CMD;
end if;
end if;
when RX_FRAME_CMD =>
if din_p.enable = '1' then
v.cmd := din_p.data(7 downto 0);
v.state := RX_FRAME_ADDR_MSB;
end if;
when RX_FRAME_ADDR_MSB =>
if din_p.enable = '1' then
v.addr(15 downto 8) := din_p.data(7 downto 0);
v.state := RX_FRAME_ADDR_LSB;
end if;
when RX_FRAME_ADDR_LSB =>
if din_p.enable = '1' then
v.addr(7 downto 0) := din_p.data(7 downto 0);
if r.cmd = x"20" then
v.state := RX_FRAME_DATA_MSB;
elsif r.cmd = x"10" then
v.state := RX_FRAME_CRC;
else
v.state := IDLE;
end if;
end if;
when RX_FRAME_DATA_MSB =>
if din_p.enable = '1' then
v.data(15 downto 8) := din_p.data(7 downto 0);
v.state := RX_FRAME_DATA_LSB;
end if;
when RX_FRAME_DATA_LSB =>
if din_p.enable = '1' then
v.data(7 downto 0) := din_p.data(7 downto 0);
v.state := RX_FRAME_CRC;
end if;
when RX_FRAME_CRC =>
if din_p.enable = '1' then
if r.crc_inc = din_p.data(7 downto 0) then
if r.cmd = x"20" then
v.state := WR_CYCLE_1;
elsif r.cmd = x"10" then
v.state := RD_CYCLE_1;
else
v.state := IDLE; -- illegal command
end if;
else
v.state := BAD_CRC_REPLY_1; -- illegal crc
end if;
end if;
-----------------------------------------------------------------
-- Send Bad CRC Reply
-----------------------------------------------------------------
when BAD_CRC_REPLY_1 =>
v.dout.enable := '1';
v.dout.data := "1" & x"00";
v.crc_out := (others => '0');
v.state := BAD_CRC_REPLY_2;
when BAD_CRC_REPLY_2 =>
v.dout.data := "0" & x"03";
v.crc_out := calc_crc_8210(v.dout.data(7 downto 0), r.crc_out);
v.state := BAD_CRC_REPLY_3;
when BAD_CRC_REPLY_3 =>
v.dout.data := "0" & r.crc_out;
v.state := BAD_CRC_REPLY_4;
when BAD_CRC_REPLY_4 =>
v.dout.enable := '0';
v.state := IDLE;
-----------------------------------------------------------------
-- Execute Read
-----------------------------------------------------------------
when RD_CYCLE_1 =>
v.bus_o.re := '1';
v.bus_o.addr := r.addr(14 downto 0);
v.state := RD_CYCLE_2;
when RD_CYCLE_2 =>
v.bus_o.re := '0';
v.state := RD_CYCLE_3;
when RD_CYCLE_3 =>
v.data := bus_i.data;
v.state := RD_REPLY_1;
when RD_REPLY_1 =>
v.crc_out := (others => '0');
v.dout.data := "1" & x"00";
v.dout.enable := '1';
v.state := RD_REPLY_2;
when RD_REPLY_2 =>
v.dout.data := "0" & x"11";
v.crc_out := calc_crc_8210(v.dout.data(7 downto 0), r.crc_out);
v.state := RD_REPLY_3;
when RD_REPLY_3 =>
v.dout.data := "0" & r.data(15 downto 8);
v.crc_out := calc_crc_8210(v.dout.data(7 downto 0), r.crc_out);
v.state := RD_REPLY_3_WS;
when RD_REPLY_3_WS =>
v.dout.enable := '0';
v.state := RD_REPLY_4;
when RD_REPLY_4 =>
v.dout.data := "0" & r.data(7 downto 0);
v.dout.enable := '1';
v.crc_out := calc_crc_8210(v.dout.data(7 downto 0), r.crc_out);
v.state := RD_REPLY_4_WS;
when RD_REPLY_4_WS =>
v.dout.enable := '0';
v.state := RD_REPLY_5;
when RD_REPLY_5 =>
v.dout.enable := '1';
v.dout.data := "0" & r.crc_out;
v.state := RD_REPLY_6;
when RD_REPLY_6 =>
v.dout.enable := '0';
v.state := IDLE;
-----------------------------------------------------------------
-- Execute Write
-----------------------------------------------------------------
when WR_CYCLE_1 =>
v.bus_o.addr := r.addr(14 downto 0);
v.bus_o.data := r.data;
v.bus_o.we := '1';
v.state := WR_CYCLE_2;
when WR_CYCLE_2 =>
v.bus_o.we := '0';
v.state := WR_REPLY_1;
when WR_REPLY_1 =>
v.dout.enable := '1';
v.dout.data := "1" & x"00";
v.crc_out := (others => '0');
v.state := WR_REPLY_2;
when WR_REPLY_2 =>
v.dout.data := "0" & x"21";
v.crc_out := calc_crc_8210(v.dout.data(7 downto 0), r.crc_out);
v.state := WR_REPLY_3;
when WR_REPLY_3 =>
v.dout.data := "0" & r.crc_out;
v.state := WR_REPLY_4;
when WR_REPLY_4 =>
v.dout.enable := '0';
v.state := IDLE;
end case;
-- running CRC, reset on frame seperators
if din_p.enable = '1' then
if din_p.data(8) = '1' then
v.crc_inc := (others => '0');
else
v.crc_inc := calc_crc_8210(din_p.data(7 downto 0), r.crc_inc);
end if;
end if;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause | 19ac81d7a15dbb6dc5d39f7de1f4d00a | 0.379204 | 3.976483 | false | false | false | false |
olofk/libstorage | rtl/vhdl/generic/fifo_fwft_generic.vhd | 1 | 2,643 | --
-- First Word Fall Through FIFO. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.std_logic_1164.all;
library libstorage_1;
entity fifo_fwft_generic is
generic (
type data_type;
DEPTH : positive;
FWFT : boolean := false);
port (
clk : in std_ulogic;
rst : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out data_type;
full_o : out std_ulogic;
wr_en_i : in std_ulogic;
wr_data_i : in data_type;
empty_o : out std_ulogic);
end entity fifo_fwft_generic;
architecture str of fifo_fwft_generic is
--FWFT signals
signal fifo_rd_data : data_type;
signal fifo_rd_en : std_ulogic;
signal fifo_empty : std_ulogic;
signal fwft_rd_data : data_type;
signal fwft_rd_en : std_ulogic;
signal fwft_empty : std_ulogic;
begin
fifo_rd_en <= fwft_rd_en when FWFT else rd_en_i;
rd_data_o <= fwft_rd_data when FWFT else fifo_rd_data;
empty_o <= fwft_empty when FWFT else fifo_empty;
fifo : entity libstorage_1.fifo_generic
generic map (
data_type => data_type,
DEPTH => DEPTH)
port map (
clk => clk,
rst => rst,
rd_en_i => fifo_rd_en,
rd_data_o => fifo_rd_data,
empty_o => fifo_empty,
wr_en_i => wr_en_i,
wr_data_i => wr_data_i,
full_o => full_o);
gen_fwft: if FWFT generate
fifo_fwft_adapter: entity libstorage_1.fifo_fwft_adapter
generic map (
data_type => data_type)
port map (
clk => clk,
rst => rst,
fifo_rd_en_o => fwft_rd_en,
fifo_rd_data_i => fifo_rd_data,
fifo_empty_i => fifo_empty,
rd_en_i => rd_en_i,
rd_data_o => fwft_rd_data,
empty_o => fwft_empty);
end generate gen_fwft;
end architecture str;
| isc | e1d50eced7d512ea6853d8d8f214c8fa | 0.623534 | 3.379795 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0_1/synth/system_ov7670_vga_0_0.vhd | 2 | 3,723 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_0_0 IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_0_0;
ARCHITECTURE system_ov7670_vga_0_0_arch OF system_ov7670_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "ov7670_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_vga_0_0_arch : ARCHITECTURE IS "system_ov7670_vga_0_0,ov7670_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_vga_0_0_arch: ARCHITECTURE IS "system_ov7670_vga_0_0,ov7670_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_vga,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ov7670_vga
PORT MAP (
pclk => pclk,
data => data,
rgb => rgb
);
END system_ov7670_vga_0_0_arch;
| mit | 9bb06b50273493793ea0f9fbe608680c | 0.7408 | 3.834192 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0_1/system_ov7670_vga_1_0_sim_netlist.vhdl | 1 | 5,327 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:02:41 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0_1/system_ov7670_vga_1_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_1_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_1_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_1_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal p_0_in0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => pclk,
CE => '1',
D => p_0_in0,
Q => cycle,
R => '0'
);
\rgb[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle,
O => p_0_in0
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_1_0 : entity is "system_ov7670_vga_1_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_1_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_1_0;
architecture STRUCTURE of system_ov7670_vga_1_0 is
begin
U0: entity work.system_ov7670_vga_1_0_ov7670_vga
port map (
data(7 downto 0) => data(7 downto 0),
pclk => pclk,
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
| mit | 858c1365eef3c486309aaac882d9c3fa | 0.524122 | 3.178401 | false | false | false | false |
pgavin/carpe | hdl/util/types_pkg.vhdl | 1 | 9,204 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package types_pkg is
type endianness_type is (
little_endian,
big_endian
);
subtype void_type is std_ulogic_vector(-1 downto 0);
constant void : void_type := "";
constant log2_byte_bits : natural := 3;
constant byte_bits : natural := 2**log2_byte_bits;
subtype byte_type is std_ulogic_vector(byte_bits-1 downto 0);
type std_ulogic_vector2 is array(natural range <>, natural range <>) of std_ulogic;
type std_logic_vector2 is array(natural range <>, natural range <>) of std_logic;
type std_ulogic_vector3 is array(natural range <>, natural range <>, natural range <>) of std_ulogic;
type std_logic_vector3 is array(natural range <>, natural range <>, natural range <>) of std_logic;
pure function std_ulogic_vector2_slice1(v : std_ulogic_vector2; n : natural) return std_ulogic_vector;
pure function std_ulogic_vector2_slice2(v : std_ulogic_vector2; n : natural) return std_ulogic_vector;
pure function std_ulogic_to_character(value : in std_ulogic) return character;
pure function std_logic_to_character(value : in std_logic) return character;
pure function character_to_std_ulogic(value : in character) return std_ulogic;
pure function character_to_std_logic(value : in character) return std_logic;
pure function std_ulogic_vector_to_string(value : in std_ulogic_vector) return string;
pure function std_logic_vector_to_string(value : in std_logic_vector) return string;
pure function string_to_std_ulogic_vector(value : in string) return std_ulogic_vector;
pure function string_to_std_logic_vector(value : in string) return std_ulogic_vector;
pure function boolean_to_string(value : in boolean) return string;
pure function string_to_boolean(value : in string) return boolean;
pure function integer_to_string(value : in integer) return string;
pure function string_to_integer(value : in string) return integer;
end package;
package body types_pkg is
pure function std_ulogic_vector2_slice1(v : std_ulogic_vector2; n : natural) return std_ulogic_vector is
variable ret : std_ulogic_vector(v'range(1));
begin
for m in v'range(1) loop
ret(m) := v(m, n);
end loop;
return ret;
end function;
pure function std_ulogic_vector2_slice2(v : std_ulogic_vector2; n : natural) return std_ulogic_vector is
variable ret : std_ulogic_vector(v'range(2));
begin
for m in v'range(2) loop
ret(m) := v(n, m);
end loop;
return ret;
end function;
pure function std_ulogic_to_character(value : in std_ulogic) return character is
begin
case value is
when 'U' =>
return 'U';
when 'X' =>
return 'X';
when '0' =>
return '0';
when '1' =>
return '1';
when 'Z' =>
return 'Z';
when 'W' =>
return 'W';
when 'L' =>
return 'L';
when 'H' =>
return 'H';
when '-' =>
return '-';
end case;
end function;
pure function std_logic_to_character(value : in std_logic) return character is
begin
case value is
when 'U' =>
return 'U';
when 'X' =>
return 'X';
when '0' =>
return '0';
when '1' =>
return '1';
when 'Z' =>
return 'Z';
when 'W' =>
return 'W';
when 'L' =>
return 'L';
when 'H' =>
return 'H';
when '-' =>
return '-';
end case;
end function;
pure function character_to_std_ulogic(value : in character) return std_ulogic is
begin
case value is
when 'U' =>
return 'U';
when 'X' =>
return 'X';
when '0' =>
return '0';
when '1' =>
return '1';
when 'Z' =>
return 'Z';
when 'W' =>
return 'W';
when 'L' =>
return 'L';
when 'H' =>
return 'H';
when '-' =>
return '-';
when others =>
assert false
report "invalid std_ulogic character: " & value
severity failure;
end case;
end function;
pure function character_to_std_logic(value : in character) return std_logic is
begin
case value is
when 'U' =>
return 'U';
when 'X' =>
return 'X';
when '0' =>
return '0';
when '1' =>
return '1';
when 'Z' =>
return 'Z';
when 'W' =>
return 'W';
when 'L' =>
return 'L';
when 'H' =>
return 'H';
when '-' =>
return '-';
when others =>
assert false
report "invalid std_logic character: " & value
severity failure;
end case;
end function;
pure function std_ulogic_vector_to_string(value : in std_ulogic_vector) return string is
variable ret : string(1 to value'length);
begin
if value'ascending then
for n in value'range loop
ret(n-value'left+ret'left) := std_ulogic_to_character(value(n));
end loop;
else
for n in value'range loop
ret(value'left-n+ret'left) := std_ulogic_to_character(value(n));
end loop;
end if;
return ret;
end function;
pure function std_logic_vector_to_string(value : in std_logic_vector) return string is
variable ret : string(1 to value'length);
begin
if value'ascending then
for n in value'range loop
ret(n-value'left+ret'left) := std_logic_to_character(value(n));
end loop;
else
for n in value'range loop
ret(value'left-n+ret'left) := std_logic_to_character(value(n));
end loop;
end if;
return ret;
end function;
pure function string_to_std_ulogic_vector(value : in string) return std_ulogic_vector is
variable ret : std_ulogic_vector(value'length-1 downto 0);
begin
if not value'ascending then
for n in value'range loop
ret(n-value'right+ret'right) := character_to_std_ulogic(value(n));
end loop;
else
for n in value'range loop
ret(value'right-n+ret'right) := character_to_std_ulogic(value(n));
end loop;
end if;
return ret;
end function;
pure function string_to_std_logic_vector(value : in string) return std_ulogic_vector is
variable ret : std_ulogic_vector(value'length-1 downto 0);
begin
if not value'ascending then
for n in value'range loop
ret(n-value'right+ret'right) := character_to_std_logic(value(n));
end loop;
else
for n in value'range loop
ret(value'right-n+ret'right) := character_to_std_logic(value(n));
end loop;
end if;
return ret;
end function;
pure function boolean_to_string(value : in boolean) return string is
begin
if value then
return "true";
else
return "false";
end if;
end function;
pure function string_to_boolean(value : in string) return boolean is
begin
if value = "true" then
return true;
elsif value = "false" then
return false;
else
assert false
report "invalid boolean string: " & value
severity failure;
end if;
end function;
pure function integer_to_string(value : in integer) return string is
begin
return integer'image(value);
end function;
pure function string_to_integer(value : in string) return integer is
variable ret : integer;
begin
ret := 0;
for n in value'left to value'right loop
ret := ret * 10;
case value(n) is
when '0' => ret := ret + 0;
when '1' => ret := ret + 1;
when '2' => ret := ret + 2;
when '3' => ret := ret + 3;
when '4' => ret := ret + 4;
when '5' => ret := ret + 5;
when '6' => ret := ret + 6;
when '7' => ret := ret + 7;
when '8' => ret := ret + 8;
when '9' => ret := ret + 9;
when others =>
report "invalid integer string: " & value
severity failure;
end case;
end loop;
return ret;
end function;
end package body;
| apache-2.0 | 45a60dea2197f31cfa0659c5aea89747 | 0.57801 | 3.838198 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_sim_netlist.vhdl | 2 | 7,148 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 19:58:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 44.625000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 75.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked
);
end STRUCTURE;
| mit | 0d54c7d965b26490fdbfd73b5d7730ca | 0.637661 | 3.297048 | false | false | false | false |
pgavin/carpe | hdl/isa/or1k_pkg.vhdl | 1 | 31,078 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.types_pkg.all;
use util.numeric_pkg.all;
package or1k_pkg is
constant or1k_vaddr_bits : natural := 32;
constant or1k_paddr_bits : natural := 35;
constant or1k_log2_word_bytes : natural := 2;
constant or1k_word_bytes : natural := 2**or1k_log2_word_bytes;
constant or1k_log2_inst_bytes : natural := 2;
constant or1k_inst_bytes : natural := 2**or1k_log2_inst_bytes;
constant or1k_rfaddr_bits : natural := 5;
constant or1k_wmask_bits : natural := 4; -- word mask, one bit per byte in word
constant or1k_poffset_bits : natural := 13;
constant or1k_vpn_bits : natural := or1k_vaddr_bits - or1k_poffset_bits;
constant or1k_ppn_bits : natural := or1k_paddr_bits - or1k_poffset_bits;
constant or1k_word_bits : natural := or1k_word_bytes * byte_bits;
constant or1k_inst_bits : natural := or1k_inst_bytes * byte_bits;
constant or1k_shift_bits : natural := log2ceil(or1k_word_bits);
-- the number of bits required to encode the size of a data request.
-- for example, is word_bytes is 4 or 8, then we need 2 bits.
-- 00 -> 1 byte request,
-- 01 -> 2 byte request,
-- 10 -> 4 byte request,
-- 11 -> 8 byte request.
constant or1k_log2_data_size_bits : natural := bitsize(or1k_log2_word_bytes);
constant or1k_wvaddr_bits : natural := or1k_vaddr_bits - or1k_log2_word_bytes;
constant or1k_ivaddr_bits : natural := or1k_vaddr_bits - or1k_log2_inst_bytes;
constant or1k_wpaddr_bits : natural := or1k_paddr_bits - or1k_log2_word_bytes;
constant or1k_ipaddr_bits : natural := or1k_paddr_bits - or1k_log2_inst_bytes;
constant or1k_wpoffset_bits : natural := or1k_poffset_bits - or1k_log2_word_bytes;
constant or1k_ipoffset_bits : natural := or1k_poffset_bits - or1k_log2_inst_bytes;
constant or1k_inst_endianness : endianness_type := big_endian;
subtype or1k_vaddr_type is std_ulogic_vector(or1k_vaddr_bits-1 downto 0);
subtype or1k_paddr_type is std_ulogic_vector(or1k_paddr_bits-1 downto 0);
subtype or1k_wvaddr_type is std_ulogic_vector(or1k_wvaddr_bits-1 downto 0);
subtype or1k_ivaddr_type is std_ulogic_vector(or1k_ivaddr_bits-1 downto 0);
subtype or1k_wpaddr_type is std_ulogic_vector(or1k_wpaddr_bits-1 downto 0);
subtype or1k_ipaddr_type is std_ulogic_vector(or1k_ipaddr_bits-1 downto 0);
subtype or1k_poffset_type is std_ulogic_vector(or1k_poffset_bits-1 downto 0);
subtype or1k_ipoffset_type is std_ulogic_vector(or1k_ipoffset_bits-1 downto 0);
subtype or1k_wpoffset_type is std_ulogic_vector(or1k_wpoffset_bits-1 downto 0);
subtype or1k_vpn_type is std_ulogic_vector(or1k_vpn_bits-1 downto 0);
subtype or1k_ppn_type is std_ulogic_vector(or1k_ppn_bits-1 downto 0);
subtype or1k_word_bytes_type is std_ulogic_vector2(or1k_word_bytes-1 downto 0, byte_bits-1 downto 0);
subtype or1k_word_type is std_ulogic_vector(or1k_word_bits-1 downto 0);
subtype or1k_dword_type is std_ulogic_vector(2*or1k_word_bits-1 downto 0);
subtype or1k_inst_bytes_type is std_ulogic_vector2(or1k_inst_bytes-1 downto 0, byte_bits-1 downto 0);
subtype or1k_inst_type is std_ulogic_vector(or1k_inst_bits-1 downto 0);
subtype or1k_rfaddr_type is std_ulogic_vector(or1k_rfaddr_bits-1 downto 0);
subtype or1k_shift_type is std_ulogic_vector(or1k_shift_bits-1 downto 0);
subtype or1k_wmask_type is std_ulogic_vector(or1k_wmask_bits-1 downto 0);
subtype or1k_log2_data_size_type is std_ulogic_vector(or1k_log2_data_size_bits-1 downto 0);
constant or1k_cid_bits : natural := 4;
subtype or1k_cid_type is std_ulogic_vector(or1k_cid_bits-1 downto 0);
constant or1k_atb_index_bits : natural := 2;
subtype or1k_atb_index_type is std_ulogic_vector(or1k_atb_index_bits-1 downto 0);
constant or1k_tlb_index_bits : natural := 7;
subtype or1k_tlb_index_type is std_ulogic_vector(or1k_tlb_index_bits-1 downto 0);
constant or1k_tlb_way_bits : natural := 2;
constant or1k_atb_entries : natural := 2**or1k_atb_index_bits;
constant or1k_tlb_sets : natural := 2**or1k_tlb_index_bits;
constant or1k_tlb_ways : natural := 2**or1k_tlb_way_bits;
subtype or1k_tlb_way_type is std_ulogic_vector(or1k_tlb_way_bits-1 downto 0);
constant or1k_cache_way_mask_bits : natural := 8;
subtype or1k_cache_way_mask_type is std_ulogic_vector(or1k_cache_way_mask_bits-1 downto 0);
constant or1k_contexts : natural := 2**or1k_cid_bits;
constant or1k_exception_bits : natural := 4;
subtype or1k_exception_type is std_ulogic_vector(or1k_exception_bits-1 downto 0);
constant or1k_exception_none : or1k_exception_type := "0000";
constant or1k_exception_reset : or1k_exception_type := "0001";
constant or1k_exception_bus : or1k_exception_type := "0010";
constant or1k_exception_dpf : or1k_exception_type := "0011";
constant or1k_exception_ipf : or1k_exception_type := "0100";
constant or1k_exception_tti : or1k_exception_type := "0101";
constant or1k_exception_align : or1k_exception_type := "0110";
constant or1k_exception_ill : or1k_exception_type := "0111";
constant or1k_exception_ext : or1k_exception_type := "1000";
constant or1k_exception_dtlbmiss : or1k_exception_type := "1001";
constant or1k_exception_itlbmiss : or1k_exception_type := "1010";
constant or1k_exception_range : or1k_exception_type := "1011";
constant or1k_exception_syscall : or1k_exception_type := "1100";
constant or1k_exception_fp : or1k_exception_type := "1110";
constant or1k_exception_trap : or1k_exception_type := "1110";
constant or1k_spr_data_bits : natural := 32;
subtype or1k_spr_data_type is std_ulogic_vector(or1k_spr_data_bits-1 downto 0);
pure function or1k_spr_mask(lsb, msb : natural) return or1k_spr_data_type;
constant or1k_spr_group_bits : natural := 6;
subtype or1k_spr_group_type is std_ulogic_vector(or1k_spr_group_bits-1 downto 0);
constant or1k_spr_index_bits : natural := 11;
subtype or1k_spr_index_type is std_ulogic_vector(or1k_spr_index_bits-1 downto 0);
constant or1k_spr_addr_bits : natural := or1k_spr_group_bits + or1k_spr_index_bits;
subtype or1k_spr_addr_type is std_ulogic_vector(or1k_spr_addr_bits-1 downto 0);
constant or1k_spr_group_sys : or1k_spr_group_type := "000000";
constant or1k_spr_group_dmmu : or1k_spr_group_type := "000001";
constant or1k_spr_group_immu : or1k_spr_group_type := "000010";
constant or1k_spr_group_dcache : or1k_spr_group_type := "000011";
constant or1k_spr_group_icache : or1k_spr_group_type := "000100";
constant or1k_spr_group_mac : or1k_spr_group_type := "000101";
constant or1k_spr_group_debug : or1k_spr_group_type := "000110";
constant or1k_spr_group_perf : or1k_spr_group_type := "000111";
constant or1k_spr_group_power : or1k_spr_group_type := "001000";
constant or1k_spr_group_pic : or1k_spr_group_type := "001001";
constant or1k_spr_group_tick : or1k_spr_group_type := "001010";
constant or1k_spr_group_fpu : or1k_spr_group_type := "001011";
constant or1k_spr_index_sys_vr : or1k_spr_index_type := "00000000000";
constant or1k_spr_index_sys_upr : or1k_spr_index_type := "00000000001";
constant or1k_spr_index_sys_cpucfgr : or1k_spr_index_type := "00000000010";
constant or1k_spr_index_sys_dmmucfgr : or1k_spr_index_type := "00000000011";
constant or1k_spr_index_sys_immucfgr : or1k_spr_index_type := "00000000100";
constant or1k_spr_index_sys_dccfgr : or1k_spr_index_type := "00000000101";
constant or1k_spr_index_sys_iccfgr : or1k_spr_index_type := "00000000110";
constant or1k_spr_index_sys_dcfgr : or1k_spr_index_type := "00000000111";
constant or1k_spr_index_sys_pccfgr : or1k_spr_index_type := "00000001000";
constant or1k_spr_index_sys_vr2 : or1k_spr_index_type := "00000001001";
constant or1k_spr_index_sys_avr : or1k_spr_index_type := "00000001010";
constant or1k_spr_index_sys_evbar : or1k_spr_index_type := "00000001011";
constant or1k_spr_index_sys_aecr : or1k_spr_index_type := "00000001100";
constant or1k_spr_index_sys_aesr : or1k_spr_index_type := "00000001101";
constant or1k_spr_index_sys_npc : or1k_spr_index_type := "00000010000";
constant or1k_spr_index_sys_sr : or1k_spr_index_type := "00000010001";
constant or1k_spr_index_sys_ppc : or1k_spr_index_type := "00000010010";
constant or1k_spr_index_sys_fpcsr : or1k_spr_index_type := "00000010100";
constant or1k_spr_index_sys_epcr_base : or1k_spr_index_type := "00000100000";
constant or1k_spr_index_sys_epcr_index_bits : natural := or1k_cid_bits;
pure function or1k_spr_index_sys_epcr (n : natural range 0 to or1k_contexts-1) return or1k_spr_index_type;
constant or1k_spr_index_sys_eear_base : or1k_spr_index_type := "00000110000";
constant or1k_spr_index_sys_eear_index_bits : natural := or1k_cid_bits;
pure function or1k_spr_index_sys_eear (n : natural range 0 to or1k_contexts-1) return or1k_spr_index_type;
constant or1k_spr_index_sys_esr_base : or1k_spr_index_type := "00001000000";
constant or1k_spr_index_sys_esr_index_bits : natural := or1k_cid_bits;
pure function or1k_spr_index_sys_esr (n : natural range 0 to or1k_contexts-1) return or1k_spr_index_type;
constant or1k_spr_index_sys_gpr_base : or1k_spr_index_type := "10000000000";
constant or1k_spr_index_sys_gpr_index_bits : natural := 9;
pure function or1k_spr_index_sys_gpr (n : natural range 0 to 2**or1k_spr_index_sys_gpr_index_bits-1) return or1k_spr_index_type;
constant or1k_spr_index_dmmu_dmmucr : or1k_spr_index_type := "00000000000";
constant or1k_spr_index_dmmu_dmmupr : or1k_spr_index_type := "00000000001";
constant or1k_spr_index_dmmu_dtlbeir : or1k_spr_index_type := "00000000010";
constant or1k_spr_index_dmmu_datbmr_base : or1k_spr_index_type := "00000000100";
constant or1k_spr_index_dmmu_datbmr_index_bits : natural := or1k_atb_index_bits;
pure function or1k_spr_index_dmmu_datbmr (n : natural range 0 to or1k_atb_entries-1) return or1k_spr_index_type;
constant or1k_spr_index_dmmu_datbtr_base : or1k_spr_index_type := "00000001000";
constant or1k_spr_index_dmmu_datbtr_index_bits : natural := or1k_atb_index_bits;
pure function or1k_spr_index_dmmu_datbtr (n : natural range 0 to or1k_atb_entries-1) return or1k_spr_index_type;
constant or1k_spr_index_dmmu_dtlbwmr_base : or1k_spr_index_type := "01000000000";
constant or1k_spr_index_dmmu_dtlbwmr_way_bits : natural := or1k_tlb_way_bits;
constant or1k_spr_index_dmmu_dtlbwmr_index_bits : natural := or1k_tlb_index_bits;
pure function or1k_spr_index_dmmu_dtlbwmr (w : natural range 0 to or1k_tlb_ways-1;
n : natural range 0 to or1k_tlb_sets-1) return or1k_spr_index_type;
constant or1k_spr_index_dmmu_dtlbwtr_base : or1k_spr_index_type := "01010000000";
constant or1k_spr_index_dmmu_dtlbwtr_way_bits : natural := or1k_tlb_way_bits;
constant or1k_spr_index_dmmu_dtlbwtr_index_bits : natural := or1k_tlb_index_bits;
pure function or1k_spr_index_dmmu_dtlbwtr (w : natural range 0 to or1k_tlb_ways-1;
n : natural range 0 to or1k_tlb_sets-1) return or1k_spr_index_type;
constant or1k_spr_index_immu_immucr : or1k_spr_index_type := "00000000000";
constant or1k_spr_index_immu_immupr : or1k_spr_index_type := "00000000001";
constant or1k_spr_index_immu_itlbeir : or1k_spr_index_type := "00000000010";
constant or1k_spr_index_immu_iatbmr_base : or1k_spr_index_type := "00000000100";
constant or1k_spr_index_immu_iatbmr_index_bits : natural := or1k_atb_index_bits;
pure function or1k_spr_index_immu_iatbmr (n : natural range 0 to or1k_atb_entries-1) return or1k_spr_index_type;
constant or1k_spr_index_immu_iatbtr_base : or1k_spr_index_type := "00000001000";
constant or1k_spr_index_immu_iatbtr_index_bits : natural := or1k_atb_index_bits;
pure function or1k_spr_index_immu_iatbtr (n : natural range 0 to or1k_atb_entries-1) return or1k_spr_index_type;
constant or1k_spr_index_immu_itlbwmr_base : or1k_spr_index_type := "01000000000";
constant or1k_spr_index_immu_itlbwmr_way_bits : natural := or1k_tlb_way_bits;
constant or1k_spr_index_immu_itlbwmr_index_bits : natural := or1k_tlb_index_bits;
pure function or1k_spr_index_immu_itlbwmr (w : natural range 0 to or1k_tlb_ways-1;
n : natural range 0 to or1k_tlb_sets-1) return or1k_spr_index_type;
constant or1k_spr_index_immu_itlbwtr_base : or1k_spr_index_type := "01010000000";
constant or1k_spr_index_immu_itlbwtr_way_bits : natural := or1k_tlb_way_bits;
constant or1k_spr_index_immu_itlbwtr_index_bits : natural := or1k_tlb_index_bits;
pure function or1k_spr_index_immu_itlbwtr (w : natural range 0 to or1k_tlb_ways-1;
n : natural range 0 to or1k_tlb_sets-1) return or1k_spr_index_type;
constant or1k_spr_index_mac_maclo : or1k_spr_index_type := "00000000001";
constant or1k_spr_index_mac_machi : or1k_spr_index_type := "00000000010";
constant or1k_spr_index_dcache_dccr : or1k_spr_index_type := "00000000000";
constant or1k_spr_index_dcache_dcbpr : or1k_spr_index_type := "00000000001";
constant or1k_spr_index_dcache_dcbfr : or1k_spr_index_type := "00000000010";
constant or1k_spr_index_dcache_dcbir : or1k_spr_index_type := "00000000011";
constant or1k_spr_index_dcache_dcbwr : or1k_spr_index_type := "00000000100";
constant or1k_spr_index_dcache_dcblr : or1k_spr_index_type := "00000000101";
constant or1k_spr_index_icache_iccr : or1k_spr_index_type := "00000000000";
constant or1k_spr_index_icache_icbpr : or1k_spr_index_type := "00000000001";
constant or1k_spr_index_icache_icbir : or1k_spr_index_type := "00000000010";
constant or1k_spr_index_icache_icblr : or1k_spr_index_type := "00000000011";
constant or1k_spr_field_sys_vr_rev_lsb : natural := 0;
constant or1k_spr_field_sys_vr_rev_msb : natural := 5;
constant or1k_spr_field_sys_vr_cfg_lsb : natural := 16;
constant or1k_spr_field_sys_vr_cfg_msb : natural := 23;
constant or1k_spr_field_sys_vr_ver_lsb : natural := 24;
constant or1k_spr_field_sys_vr_ver_msb : natural := 31;
constant or1k_spr_field_sys_upr_up : natural := 0;
constant or1k_spr_field_sys_upr_dcp : natural := 1;
constant or1k_spr_field_sys_upr_icp : natural := 2;
constant or1k_spr_field_sys_upr_dmp : natural := 3;
constant or1k_spr_field_sys_upr_imp : natural := 4;
constant or1k_spr_field_sys_upr_mp : natural := 5;
constant or1k_spr_field_sys_upr_dup : natural := 6;
constant or1k_spr_field_sys_upr_pcup : natural := 7;
constant or1k_spr_field_sys_upr_picp : natural := 8;
constant or1k_spr_field_sys_upr_pmp : natural := 9;
constant or1k_spr_field_sys_upr_ttp : natural := 10;
constant or1k_spr_field_sys_upr_cup_lsb : natural := 24;
constant or1k_spr_field_sys_upr_cup_msb : natural := 31;
constant or1k_spr_field_sys_cpucfgr_nsgr_lsb : natural := 0;
constant or1k_spr_field_sys_cpucfgr_nsgr_msb : natural := 3;
constant or1k_spr_field_sys_cpucfgr_cgf : natural := 4;
constant or1k_spr_field_sys_cpucfgr_ob32s : natural := 5;
constant or1k_spr_field_sys_cpucfgr_ob64s : natural := 6;
constant or1k_spr_field_sys_cpucfgr_of32s : natural := 7;
constant or1k_spr_field_sys_cpucfgr_of64s : natural := 8;
constant or1k_spr_field_sys_cpucfgr_ov64s : natural := 9;
constant or1k_spr_field_sys_cpucfgr_nd : natural := 10;
constant or1k_spr_field_sys_cpucfgr_avrp : natural := 11;
constant or1k_spr_field_sys_cpucfgr_evbarp : natural := 12;
constant or1k_spr_field_sys_cpucfgr_isrp : natural := 13;
constant or1k_spr_field_sys_cpucfgr_aecsrp : natural := 14;
constant or1k_spr_field_sys_dmmucfgr_ntw_lsb : natural := 0;
constant or1k_spr_field_sys_dmmucfgr_ntw_msb : natural := 1;
constant or1k_spr_field_sys_dmmucfgr_nts_lsb : natural := 2;
constant or1k_spr_field_sys_dmmucfgr_nts_msb : natural := 4;
constant or1k_spr_field_sys_dmmucfgr_nae_lsb : natural := 5;
constant or1k_spr_field_sys_dmmucfgr_nae_msb : natural := 7;
constant or1k_spr_field_sys_dmmucfgr_cri : natural := 8;
constant or1k_spr_field_sys_dmmucfgr_pri : natural := 9;
constant or1k_spr_field_sys_dmmucfgr_teiri : natural := 10;
constant or1k_spr_field_sys_dmmucfgr_htr : natural := 11;
constant or1k_spr_field_sys_immucfgr_ntw_lsb : natural := 0;
constant or1k_spr_field_sys_immucfgr_ntw_msb : natural := 1;
constant or1k_spr_field_sys_immucfgr_nts_lsb : natural := 2;
constant or1k_spr_field_sys_immucfgr_nts_msb : natural := 4;
constant or1k_spr_field_sys_immucfgr_nae_lsb : natural := 5;
constant or1k_spr_field_sys_immucfgr_nae_msb : natural := 7;
constant or1k_spr_field_sys_immucfgr_cri : natural := 8;
constant or1k_spr_field_sys_immucfgr_pri : natural := 9;
constant or1k_spr_field_sys_immucfgr_teiri : natural := 10;
constant or1k_spr_field_sys_immucfgr_htr : natural := 11;
constant or1k_spr_field_sys_dccfgr_ncw_lsb : natural := 0;
constant or1k_spr_field_sys_dccfgr_ncw_msb : natural := 2;
constant or1k_spr_field_sys_dccfgr_ncs_lsb : natural := 3;
constant or1k_spr_field_sys_dccfgr_ncs_msb : natural := 6;
constant or1k_spr_field_sys_dccfgr_cbs : natural := 7;
constant or1k_spr_field_sys_dccfgr_cws : natural := 8;
constant or1k_spr_field_sys_dccfgr_ccri : natural := 9;
constant or1k_spr_field_sys_dccfgr_cbiri : natural := 10;
constant or1k_spr_field_sys_dccfgr_cbpri : natural := 11;
constant or1k_spr_field_sys_dccfgr_cblri : natural := 12;
constant or1k_spr_field_sys_dccfgr_cbfri : natural := 13;
constant or1k_spr_field_sys_dccfgr_cbwbri : natural := 14;
constant or1k_spr_field_sys_iccfgr_ncw_lsb : natural := 0;
constant or1k_spr_field_sys_iccfgr_ncw_msb : natural := 2;
constant or1k_spr_field_sys_iccfgr_ncs_lsb : natural := 3;
constant or1k_spr_field_sys_iccfgr_ncs_msb : natural := 6;
constant or1k_spr_field_sys_iccfgr_cbs : natural := 7;
constant or1k_spr_field_sys_iccfgr_ccri : natural := 9;
constant or1k_spr_field_sys_iccfgr_cbiri : natural := 10;
constant or1k_spr_field_sys_iccfgr_cbpri : natural := 11;
constant or1k_spr_field_sys_iccfgr_cblri : natural := 12;
constant or1k_spr_field_dcfgr_ndp_lsb : natural := 0;
constant or1k_spr_field_dcfgr_ndp_msb : natural := 2;
constant or1k_spr_field_dcfgr_wpci : natural := 3;
constant or1k_spr_field_pccfgr_npc_lsb : natural := 0;
constant or1k_spr_field_pccfgr_npc_msb : natural := 2;
constant or1k_spr_field_sys_vr2_ver_lsb : natural := 0;
constant or1k_spr_field_sys_vr2_ver_msb : natural := 23;
constant or1k_spr_field_sys_vr2_cpuid_lsb : natural := 24;
constant or1k_spr_field_sys_vr2_cpuid_msb : natural := 31;
constant or1k_spr_field_sys_avr_rev_lsb : natural := 8;
constant or1k_spr_field_sys_avr_rev_msb : natural := 15;
constant or1k_spr_field_sys_avr_min_lsb : natural := 16;
constant or1k_spr_field_sys_avr_min_msb : natural := 23;
constant or1k_spr_field_sys_avr_maj_lsb : natural := 24;
constant or1k_spr_field_sys_avr_maj_msb : natural := 31;
constant or1k_spr_field_sys_evbar_evba_lsb : natural := 13;
constant or1k_spr_field_sys_evbar_evba_msb : natural := 31;
constant or1k_spr_field_sys_aecsr_cyadde : natural := 0;
constant or1k_spr_field_sys_aecsr_ovadde : natural := 1;
constant or1k_spr_field_sys_aecsr_cymule : natural := 2;
constant or1k_spr_field_sys_aecsr_ovmule : natural := 3;
constant or1k_spr_field_sys_aecsr_dbze : natural := 4;
constant or1k_spr_field_sys_aecsr_cymacadde : natural := 5;
constant or1k_spr_field_sys_aecsr_ovmacadde : natural := 6;
constant or1k_spr_field_sys_sr_sm : natural := 0;
constant or1k_spr_field_sys_sr_tee : natural := 1;
constant or1k_spr_field_sys_sr_iee : natural := 2;
constant or1k_spr_field_sys_sr_dce : natural := 3;
constant or1k_spr_field_sys_sr_ice : natural := 4;
constant or1k_spr_field_sys_sr_dme : natural := 5;
constant or1k_spr_field_sys_sr_ime : natural := 6;
constant or1k_spr_field_sys_sr_lee : natural := 7;
constant or1k_spr_field_sys_sr_ce : natural := 8;
constant or1k_spr_field_sys_sr_f : natural := 9;
constant or1k_spr_field_sys_sr_cy : natural := 10;
constant or1k_spr_field_sys_sr_ov : natural := 11;
constant or1k_spr_field_sys_sr_ove : natural := 12;
constant or1k_spr_field_sys_sr_dsx : natural := 13;
constant or1k_spr_field_sys_sr_eph : natural := 14;
constant or1k_spr_field_sys_sr_fo : natural := 15;
constant or1k_spr_field_sys_sr_sumra : natural := 16;
constant or1k_spr_field_sys_sr_cid_lsb : natural := 28;
constant or1k_spr_field_sys_sr_cid_msb : natural := 31;
constant or1k_spr_field_dcache_dccr_ew_lsb : natural := 0;
constant or1k_spr_field_dcache_dccr_ew_msb : natural := 7;
constant or1k_spr_field_dcache_iccr_ew_lsb : natural := 0;
constant or1k_spr_field_dcache_iccr_ew_msb : natural := 7;
constant or1k_imm_bits : natural := 16;
subtype or1k_imm_type is std_ulogic_vector(or1k_imm_bits-1 downto 0);
constant or1k_toc_offset_bits : natural := 26;
subtype or1k_toc_offset_type is std_ulogic_vector(or1k_toc_offset_bits-1 downto 0);
pure function or1k_inst_rd(inst : in or1k_inst_type) return or1k_rfaddr_type;
pure function or1k_inst_ra(inst : in or1k_inst_type) return or1k_rfaddr_type;
pure function or1k_inst_rb(inst : in or1k_inst_type) return or1k_rfaddr_type;
pure function or1k_inst_imm_contig(inst : in or1k_inst_type) return or1k_imm_type;
pure function or1k_inst_imm_split(inst : in or1k_inst_type) return or1k_imm_type;
pure function or1k_inst_toc_offset(inst : in or1k_inst_type) return or1k_toc_offset_type;
pure function or1k_inst_shift(inst : in or1k_inst_type) return or1k_shift_type;
end package;
package body or1k_pkg is
pure function or1k_spr_mask(lsb, msb : natural) return or1k_spr_data_type is
variable ret : or1k_spr_data_type;
begin
ret := (others => '0');
ret(msb downto lsb) := (msb downto lsb => '1');
return ret;
end;
pure function or1k_spr_index_sys_epcr (n : natural range 0 to or1k_contexts-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_sys_epcr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_sys_epcr_index_bits => '0') &
to_unsigned(n, or1k_spr_index_sys_epcr_index_bits)));
end;
pure function or1k_spr_index_sys_eear (n : natural range 0 to or1k_contexts-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_sys_eear_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_sys_eear_index_bits => '0') &
to_unsigned(n, or1k_spr_index_sys_eear_index_bits)));
end;
pure function or1k_spr_index_sys_esr (n : natural range 0 to or1k_contexts-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_sys_esr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_sys_esr_index_bits => '0') &
to_unsigned(n, or1k_spr_index_sys_esr_index_bits)));
end;
pure function or1k_spr_index_sys_gpr (n : natural range 0 to 2**or1k_spr_index_sys_gpr_index_bits-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_sys_gpr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_sys_gpr_index_bits => '0') &
to_unsigned(n, or1k_spr_index_sys_gpr_index_bits)));
end;
pure function or1k_spr_index_dmmu_datbmr (n : natural range 0 to or1k_atb_entries-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_dmmu_datbmr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_datbmr_index_bits => '0') &
to_unsigned(n, or1k_spr_index_dmmu_datbmr_index_bits)));
end;
pure function or1k_spr_index_dmmu_datbtr (n : natural range 0 to or1k_atb_entries-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_dmmu_datbtr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_datbtr_index_bits => '0') &
to_unsigned(n, or1k_spr_index_dmmu_datbtr_index_bits)));
end;
pure function or1k_spr_index_dmmu_dtlbwmr (w : natural range 0 to or1k_tlb_ways-1;
n : natural range 0 to or1k_tlb_sets-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_dmmu_dtlbwmr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_dtlbwmr_way_bits+or1k_spr_index_dmmu_dtlbwmr_index_bits => '0') &
to_unsigned(w, or1k_spr_index_dmmu_dtlbwmr_way_bits) &
to_unsigned(n, or1k_spr_index_dmmu_dtlbwmr_index_bits)));
end;
pure function or1k_spr_index_dmmu_dtlbwtr (w : natural range 0 to or1k_tlb_ways-1;
n : natural range 0 to or1k_tlb_sets-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_dmmu_dtlbwtr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_dmmu_dtlbwtr_way_bits+or1k_spr_index_dmmu_dtlbwtr_index_bits => '0') &
to_unsigned(w, or1k_spr_index_dmmu_dtlbwtr_way_bits) &
to_unsigned(n, or1k_spr_index_dmmu_dtlbwtr_index_bits)));
end;
pure function or1k_spr_index_immu_iatbmr (n : natural range 0 to or1k_atb_entries-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_immu_iatbmr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_immu_iatbmr_index_bits => '0') &
to_unsigned(n, or1k_spr_index_immu_iatbmr_index_bits)));
end;
pure function or1k_spr_index_immu_iatbtr (n : natural range 0 to or1k_atb_entries-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_immu_iatbtr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_immu_iatbtr_index_bits => '0') &
to_unsigned(n, or1k_spr_index_immu_iatbtr_index_bits)));
end;
pure function or1k_spr_index_immu_itlbwmr (w : natural range 0 to or1k_tlb_ways-1;
n : natural range 0 to or1k_tlb_sets-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_immu_itlbwmr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_immu_itlbwmr_way_bits+or1k_spr_index_immu_itlbwmr_index_bits => '0') &
to_unsigned(w, or1k_spr_index_immu_itlbwmr_way_bits) &
to_unsigned(n, or1k_spr_index_immu_itlbwmr_index_bits)));
end;
pure function or1k_spr_index_immu_itlbwtr (w : natural range 0 to or1k_tlb_ways-1;
n : natural range 0 to or1k_tlb_sets-1) return or1k_spr_index_type is
begin
return std_ulogic_vector(unsigned(or1k_spr_index_immu_itlbwtr_base) +
unsigned((or1k_spr_index_bits-1 downto or1k_spr_index_immu_itlbwtr_way_bits+or1k_spr_index_immu_itlbwtr_index_bits => '0') &
to_unsigned(w, or1k_spr_index_immu_itlbwtr_way_bits) &
to_unsigned(n, or1k_spr_index_immu_itlbwtr_index_bits)));
end;
pure function or1k_inst_rd(inst : in or1k_inst_type) return or1k_rfaddr_type is
variable ret : or1k_rfaddr_type := inst(25 downto 21);
begin
return ret;
end function;
pure function or1k_inst_ra(inst : in or1k_inst_type) return or1k_rfaddr_type is
variable ret : or1k_rfaddr_type := inst(20 downto 16);
begin
return ret;
end function;
pure function or1k_inst_rb(inst : in or1k_inst_type) return or1k_rfaddr_type is
variable ret : or1k_rfaddr_type := inst(15 downto 11);
begin
return ret;
end function;
pure function or1k_inst_imm_contig(inst : in or1k_inst_type) return or1k_imm_type is
variable ret : or1k_imm_type := inst(15 downto 0);
begin
return ret;
end function;
pure function or1k_inst_imm_split(inst : in or1k_inst_type) return or1k_imm_type is
variable ret : or1k_imm_type := inst(25 downto 21) & inst(10 downto 0);
begin
return ret;
end function;
pure function or1k_inst_toc_offset(inst : in or1k_inst_type) return or1k_toc_offset_type is
variable ret : or1k_toc_offset_type := inst(25 downto 0);
begin
return ret;
end function;
pure function or1k_inst_shift(inst : in or1k_inst_type) return or1k_shift_type is
variable ret : or1k_shift_type := inst(4 downto 0);
begin
return ret;
end function;
end package body;
| apache-2.0 | 85ae2c6a890dd224f9e6160699e6eb5e | 0.658665 | 2.873601 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 1,706 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon May 22 02:50:48 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
clk_100 : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
resend : in STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
clk_100 : in STD_LOGIC;
resend : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
clk_100 => clk_100,
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
resend => resend
);
end STRUCTURE;
| mit | 86a5154b1869f9f12602e9fb0fc11923 | 0.572685 | 3.653105 | false | false | false | false |
pgavin/carpe | hdl/sim/mem_1rw-behav.vhdl | 1 | 13,165 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library util;
use util.names_pkg.all;
use util.numeric_pkg.all;
use util.io_pkg.all;
use work.options_pkg.all;
architecture behav of mem_1rw is
constant addr_lo_bits : integer := addr_bits / 2;
constant addr_hi_bits : integer := addr_bits - addr_lo_bits;
subtype addr_type is std_ulogic_vector(addr_bits-1 downto 0);
subtype addr_hi_type is std_ulogic_vector(addr_hi_bits-1 downto 0);
subtype addr_lo_type is std_ulogic_vector(addr_lo_bits-1 downto 0);
constant byte_bits : integer := 2**log2_byte_bits;
constant bus_bytes : integer := 2**log2_bus_bytes;
constant bus_bits : integer := 2**(log2_byte_bits+log2_bus_bytes);
constant size_bits : integer := bitsize(log2_bus_bytes);
subtype byte_type is std_ulogic_vector(byte_bits-1 downto 0);
subtype bus_type is std_ulogic_vector(bus_bits-1 downto 0);
subtype size_type is std_ulogic_vector(size_bits-1 downto 0);
constant entry_size : integer := 2**addr_lo_bits;
constant num_entries : integer := 2**addr_hi_bits;
type entry_type is array (0 to entry_size-1) of std_ulogic_vector(byte_bits-1 downto 0);
type entry_ptr is access entry_type;
type entry_array_type is array (0 to num_entries-1) of entry_ptr;
subtype mask_type is std_ulogic_vector(2**log2_bus_bytes-1 downto 0);
procedure check_addr(v_addr : in addr_type) is
variable templine : line;
begin
if is_x(v_addr) then
write(templine, string'("invalid address: "));
write(templine, v_addr);
assert not is_x(v_addr) report templine.all severity warning;
deallocate(templine);
end if;
end procedure check_addr;
procedure check_size(v_size : in size_type) is
variable templine : line;
begin
if is_x(v_size) or to_integer(unsigned(v_size)) > log2_bus_bytes then
write(templine, string'("invalid size: "));
write(templine, v_size);
assert not is_x(v_size) report templine.all severity warning;
deallocate(templine);
end if;
end procedure check_size;
procedure check_be(v_be : in std_ulogic) is
variable templine : line;
begin
if is_x(v_be) then
write(templine, string'("invalid endianness flag: "));
write(templine, v_be);
assert not is_x(v_be) report templine.all severity warning;
deallocate(templine);
end if;
end procedure check_be;
procedure check_align(v_addr : in addr_type; v_size : in size_type) is
variable templine : line;
variable v_mask : addr_type;
variable v_size_n : integer;
begin
v_mask := (others => '0');
v_size_n := to_integer(unsigned(v_size));
if v_size_n > 0 then
for n in v_size_n-1 downto 0 loop
v_mask(n) := '1';
end loop;
end if;
if (v_addr and v_mask) /= (addr_bits-1 downto 0 => '0') then
write(templine, string'("invalid alignment: addr "));
write(templine, v_addr);
write(templine, string'(", size "));
write(templine, v_size);
assert (v_addr and v_mask) /= (addr_bits-1 downto 0 => '0') report templine.all severity warning;
deallocate(templine);
end if;
end procedure check_align;
procedure split_addr(v_addr : in addr_type;
v_addr_hi : out addr_hi_type;
v_addr_lo : out addr_lo_type) is
begin
v_addr_hi := v_addr(addr_bits-1 downto addr_lo_bits);
v_addr_lo := v_addr(addr_lo_bits-1 downto 0);
end procedure split_addr;
type memory_type is protected
procedure clear;
procedure init_addr(v_addr : in addr_type);
procedure read_byte(v_addr : in addr_type;
v_byte : out byte_type);
procedure write_byte(v_addr : in addr_type;
v_byte : in byte_type);
end protected;
type memory_type is protected body
variable entries : entry_array_type;
procedure clear is
begin
for n in 0 to num_entries-1 loop
if entries(n) /= null then
deallocate(entries(n));
entries(n) := null;
end if;
end loop;
end procedure clear;
procedure init_addr(v_addr : in addr_type) is
variable v_addr_hi : addr_hi_type;
variable v_addr_lo : addr_lo_type;
begin
split_addr(v_addr, v_addr_hi, v_addr_lo);
if entries(to_integer(unsigned(v_addr_hi))) = null then
entries(to_integer(unsigned(v_addr_hi))) := new entry_type'(others => (others => '0'));
end if;
end procedure init_addr;
procedure read_byte(v_addr : in addr_type;
v_byte : out byte_type) is
variable v_addr_hi : addr_hi_type;
variable v_addr_lo : addr_lo_type;
begin
check_addr(v_addr);
init_addr(v_addr);
if not is_x(v_addr) then
split_addr(v_addr, v_addr_hi, v_addr_lo);
v_byte := entries(to_integer(unsigned(v_addr_hi)))(to_integer(unsigned(v_addr_lo)));
else
v_byte := (others => 'X');
end if;
end procedure read_byte;
procedure write_byte(v_addr : in addr_type;
v_byte : in byte_type) is
variable v_addr_hi : addr_hi_type;
variable v_addr_lo : addr_lo_type;
variable v_templine : line;
begin
check_addr(v_addr);
init_addr(v_addr);
if not is_x(v_addr) then
--if is_x(v_byte) then
-- write(v_templine, string'("warning: writing uninitialized data to address "));
-- write(v_templine, v_addr);
-- write(v_templine, string'(" (data: "));
-- write(v_templine, v_byte);
-- write(v_templine, string'(")"));
-- report v_templine.all severity warning;
-- deallocate(v_templine);
--end if;
split_addr(v_addr, v_addr_hi, v_addr_lo);
entries(to_integer(unsigned(v_addr_hi)))(to_integer(unsigned(v_addr_lo))) := v_byte;
end if;
end procedure write_byte;
end protected body;
shared variable memory : memory_type;
procedure read_bus(v_addr : in addr_type;
v_size : in size_type;
v_be : in std_ulogic;
v_bus : out bus_type) is
variable v_byte_addr : addr_type;
variable v_byte : std_ulogic_vector(byte_bits-1 downto 0);
variable v_bus_tmp : bus_type;
variable v_size_n : integer;
variable v_bus_off : integer;
begin
check_addr(v_addr);
check_size(v_size);
check_be(v_be);
check_align(v_addr, v_size);
v_bus_tmp := (others => 'X');
v_size_n := 2**to_integer(unsigned(v_size));
v_bus_off := 0;
while v_bus_off <= v_size_n-1 loop
v_byte_addr := std_ulogic_vector(unsigned(v_addr) + to_unsigned(v_bus_off, addr_bits));
memory.read_byte(v_byte_addr, v_byte);
if v_be = '1' then
v_bus_tmp(v_size_n*byte_bits-byte_bits*v_bus_off-1 downto v_size_n*byte_bits-byte_bits*(v_bus_off+1)) := v_byte;
else
v_bus_tmp(byte_bits*(v_bus_off+1)-1 downto byte_bits*v_bus_off) := v_byte;
end if;
v_bus_off := v_bus_off + 1;
end loop;
v_bus := v_bus_tmp;
end procedure read_bus;
procedure write_bus(v_addr : in addr_type;
v_size : in size_type;
v_be : std_ulogic;
v_bus : in bus_type) is
variable v_byte_addr : addr_type;
variable v_byte : std_ulogic_vector(byte_bits-1 downto 0);
variable v_size_n : integer;
variable v_bus_off : integer;
begin
check_addr(v_addr);
check_size(v_size);
check_be(v_be);
check_align(v_addr, v_size);
v_size_n := 2**to_integer(unsigned(v_size));
v_bus_off := 0;
while v_bus_off <= v_size_n-1 loop
v_byte_addr := std_ulogic_vector(unsigned(v_addr) + to_unsigned(v_bus_off, addr_bits));
if v_be = '1' then
v_byte := v_bus(v_size_n*byte_bits-byte_bits*v_bus_off-1 downto v_size_n*byte_bits-byte_bits*(v_bus_off+1));
else
v_byte := v_bus(byte_bits*(v_bus_off+1)-1 downto byte_bits*v_bus_off);
end if;
memory.write_byte(v_byte_addr, v_byte);
v_bus_off := v_bus_off + 1;
end loop;
end procedure write_bus;
procedure read_srec is
variable filename : line;
file srecfile : text;
variable c : character;
variable srecline : line;
variable srectype : character;
variable srecdatalenv : std_ulogic_vector(byte_bits-1 downto 0);
variable srecdatalen : integer;
variable srecaddrtmp : std_ulogic_vector(31 downto 0);
variable srecaddr : addr_type;
variable srecbyte : byte_type;
variable templine : line;
begin
filename := new string'(option(entity_path_name(mem_1rw'path_name) & ":srec_file"));
assert filename.all /= ""
report "option " & entity_path_name(mem_1rw'path_name) & ":srec_file not set"
severity failure;
file_open(srecfile, filename.all, read_mode);
deallocate(filename);
while not endfile(srecfile) loop
readline(srecfile, srecline);
--report "read line: " & srecline.all;
read(srecline, c);
if c /= 'S' and c /= 's' then
next;
end if;
read(srecline, srectype);
case srectype is
when '1'|'2'|'3' =>
null;
when others =>
next;
end case;
hread(srecline, srecdatalenv);
srecdatalen := to_integer(unsigned(srecdatalenv));
srecaddrtmp := (others => '0');
case srectype is
when '1' =>
hread(srecline, srecaddrtmp(15 downto 0));
srecdatalen := srecdatalen - 2;
when '2' =>
hread(srecline, srecaddrtmp(23 downto 0));
srecdatalen := srecdatalen - 3;
when '3' =>
hread(srecline, srecaddrtmp(31 downto 0));
srecdatalen := srecdatalen - 4;
when others =>
next;
end case;
if addr_bits = 32 then
srecaddr := srecaddrtmp;
elsif addr_bits > 32 then
srecaddr(addr_bits-1 downto 32) := (others => '0');
srecaddr(31 downto 0) := srecaddrtmp;
else
srecaddr(addr_bits-1 downto 0) := srecaddrtmp(addr_bits-1 downto 0);
end if;
-- ignore checksum byte
srecdatalen := srecdatalen - 1;
for n in 0 to srecdatalen-1 loop
hread(srecline, srecbyte);
memory.write_byte(srecaddr, srecbyte);
srecaddr := std_ulogic_vector(unsigned(srecaddr) + to_unsigned(1, 32));
end loop;
end loop;
--report "done.";
file_close(srecfile);
end procedure read_srec;
begin
seq : process(clk)
variable v_dout : bus_type;
variable templine : line;
begin
if rising_edge(clk) then
case rstn is
when '0' =>
memory.clear;
read_srec;
when '1' =>
case en is
when '1' =>
case we is
when '1' =>
write_bus(addr, size, be, din);
when '0' =>
read_bus(addr, size, be, v_dout);
dout <= v_dout;
when others =>
assert not is_x(we)
report "we is metavalue"
severity warning;
end case;
when '0' =>
when others =>
assert not is_x(en)
report "en is metavalue"
severity warning;
end case;
when others =>
assert not is_x(rstn)
report "rstn is metavalue"
severity warning;
end case;
end if;
end process;
end;
| apache-2.0 | de0adbaad0ab60932d7656f8034dbe4a | 0.555488 | 3.575502 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_idelayctrl_gen.vhd | 1 | 718 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--Core-specific IDELAYCTRL wrapper
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
entity csi_rx_idelayctrl_gen is
generic(
fpga_series : string := "7SERIES"
);
port(
ref_clock : in std_logic; --IDELAYCTRL reference clock
reset : in std_logic --IDELAYCTRL reset
);
end csi_rx_idelayctrl_gen;
architecture Behavioral of csi_rx_idelayctrl_gen is
begin
gen_v6_7s: if fpga_series = "VIRTEX6" or fpga_series = "7SERIES" generate
delayctrl : IDELAYCTRL
port map (
RDY => open,
REFCLK => ref_clock,
RST => reset
);
end generate;
end architecture;
| mit | 94b23ea76756fdea4253050577e55b41 | 0.672702 | 3.60804 | false | false | false | false |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_3/Uart_working/ascii_hex.vhd | 2 | 1,957 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/07/2016 04:05:30 PM
-- Design Name:
-- Module Name: ascii_hex - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ascii_hex is
Port ( clk : in std_logic; ascii : in std_logic_vector(7 downto 0); hex : out std_logic_vector(3 downto 0)
);
end ascii_hex;
architecture Behavioral of ascii_hex is
begin
process(CLK)
begin
-- if (clk'event and clk = '1') then
case ascii is
when x"30" => hex <= "0000";
when x"31" => hex <= "0001";
when x"32" => hex <= "0010";
when x"33" => hex <= "0011";
when x"34" => hex <= "0100";
when x"35" => hex <= "0101";
when x"36" => hex <= "0110";
when x"37" => hex <= "0111";
when x"38" => hex <= "1000";
when x"39" => hex <= "1001";
when x"61" => hex <= "1010";
when x"62" => hex <= "1011";
when x"63" => hex <= "1100";
when x"64" => hex <= "1101";
when x"65" => hex <= "1110";
when x"66" => hex <= "1111";
when others => hex <= "0000";
end case;
--end if;
end process;
end Behavioral;
| mit | 9fd2950bfd0a128a67b275ae85b3517b | 0.465508 | 3.969574 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/hdl/system_wrapper.vhd | 1 | 4,756 | --Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 27 19:47:32 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
config_finished : out STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
href : in STD_LOGIC;
pclk : in STD_LOGIC;
resend : in STD_LOGIC;
scl : out STD_LOGIC;
sda : inout STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_out_en : out STD_LOGIC;
href : in STD_LOGIC;
vsync : in STD_LOGIC;
scl : out STD_LOGIC;
sda : inout STD_LOGIC;
xclk : out STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
config_finished => config_finished,
data(7 downto 0) => data(7 downto 0),
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en,
href => href,
pclk => pclk,
resend => resend,
scl => scl,
sda => sda,
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0),
vsync => vsync,
xclk => xclk
);
end STRUCTURE;
| mit | ae0833b5c49ab4811692b0921b735932 | 0.583474 | 3.141347 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl | 1 | 17,729 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 09:37:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0_vga_sync is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
active : out STD_LOGIC;
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_0_0_vga_sync : entity is "vga_sync";
end system_vga_sync_0_0_vga_sync;
architecture STRUCTURE of system_vga_sync_0_0_vga_sync is
signal active_INST_0_i_1_n_0 : STD_LOGIC;
signal h_count_next : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \h_count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[5]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal h_sync_next : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sel : STD_LOGIC;
signal \v_count_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal v_sync_next : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \h_count_reg[5]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \h_count_reg[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair0";
begin
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"000002AA"
)
port map (
I0 => active_INST_0_i_1_n_0,
I1 => \^xaddr\(8),
I2 => \^xaddr\(7),
I3 => \^xaddr\(9),
I4 => \^yaddr\(9),
O => active
);
active_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(6),
I1 => \^yaddr\(5),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
O => active_INST_0_i_1_n_0
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => h_count_next(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
O => h_count_next(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(0),
I1 => \^xaddr\(1),
I2 => \^xaddr\(2),
O => h_count_next(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(2),
O => h_count_next(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(1),
I3 => \^xaddr\(0),
I4 => \^xaddr\(3),
O => \h_count_reg[4]_i_1_n_0\
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00000000FFBF"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(8),
I2 => \^xaddr\(9),
I3 => \^xaddr\(7),
I4 => \h_count_reg[5]_i_2_n_0\,
I5 => \^xaddr\(5),
O => h_count_next(5)
);
\h_count_reg[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^xaddr\(2),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(3),
I4 => \^xaddr\(4),
O => \h_count_reg[5]_i_2_n_0\
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(4),
I2 => \^xaddr\(5),
I3 => \h_count_reg[9]_i_3_n_0\,
O => h_count_next(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAAA"
)
port map (
I0 => \^xaddr\(7),
I1 => \h_count_reg[9]_i_3_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
I4 => \^xaddr\(6),
O => h_count_next(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF0B00B0"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(4),
I2 => \h_count_reg[9]_i_4_n_0\,
I3 => \h_count_reg[9]_i_3_n_0\,
I4 => \^xaddr\(8),
O => h_count_next(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FBFBFB0B000000"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(4),
I2 => \h_count_reg[9]_i_3_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \^xaddr\(8),
I5 => \^xaddr\(9),
O => h_count_next(9)
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFEFFF"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(0),
I2 => \^xaddr\(1),
I3 => \^xaddr\(2),
O => \h_count_reg[9]_i_3_n_0\
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(0),
Q => \^xaddr\(0)
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(1),
Q => \^xaddr\(1)
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(2),
Q => \^xaddr\(2)
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(3),
Q => \^xaddr\(3)
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => \h_count_reg[4]_i_1_n_0\,
Q => \^xaddr\(4)
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(5),
Q => \^xaddr\(5)
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(6),
Q => \^xaddr\(6)
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(7),
Q => \^xaddr\(7)
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(8),
Q => \^xaddr\(8)
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => '1',
CLR => rst,
D => h_count_next(9),
Q => \^xaddr\(9)
);
h_sync_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00002AA800000000"
)
port map (
I0 => \^xaddr\(7),
I1 => \^xaddr\(6),
I2 => \^xaddr\(5),
I3 => \^xaddr\(4),
I4 => \^xaddr\(8),
I5 => \^xaddr\(9),
O => h_sync_next
);
h_sync_reg_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => h_sync_next,
PRE => rst,
Q => hsync
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \^yaddr\(0),
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => p_0_in(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55AA55AA45AA55AA"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FFAA0045FFAA00"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => p_0_in(3)
);
\v_count_reg[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \v_count_reg[3]_i_2_n_0\
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => p_0_in(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(3),
I4 => \^yaddr\(2),
I5 => \^yaddr\(4),
O => p_0_in(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^yaddr\(6),
I1 => \v_count_reg[9]_i_5_n_0\,
I2 => \^yaddr\(5),
O => \v_count_reg[6]_i_1_n_0\
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(6),
O => p_0_in(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(5),
I4 => \^yaddr\(7),
O => p_0_in(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000001000"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[5]_i_2_n_0\,
O => sel
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"D0D00DD0"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => active_INST_0_i_1_n_0,
O => p_0_in(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^yaddr\(9),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(7),
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
I4 => \^yaddr\(4),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(0),
Q => \^yaddr\(0)
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(1),
Q => \^yaddr\(1)
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(2),
Q => \^yaddr\(2)
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(3),
Q => \^yaddr\(3)
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(4),
Q => \^yaddr\(4)
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(5),
Q => \^yaddr\(5)
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => \v_count_reg[6]_i_1_n_0\,
Q => \^yaddr\(6)
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(7),
Q => \^yaddr\(7)
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(8),
Q => \^yaddr\(8)
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk_25,
CE => sel,
CLR => rst,
D => p_0_in(9),
Q => \^yaddr\(9)
);
v_sync_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000040000"
)
port map (
I0 => \^yaddr\(9),
I1 => \^yaddr\(3),
I2 => \^yaddr\(4),
I3 => \^yaddr\(2),
I4 => \^yaddr\(1),
I5 => active_INST_0_i_1_n_0,
O => v_sync_next
);
v_sync_reg_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk_25,
CE => '1',
D => v_sync_next,
PRE => rst,
Q => vsync
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0 is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_0_0 : entity is "system_vga_sync_0_0,vga_sync,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_0_0 : entity is "vga_sync,Vivado 2016.4";
end system_vga_sync_0_0;
architecture STRUCTURE of system_vga_sync_0_0 is
begin
U0: entity work.system_vga_sync_0_0_vga_sync
port map (
active => active,
clk_25 => clk_25,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
| mit | 228ef99bc38d85fd0f846f51ddfc143a | 0.48965 | 2.753806 | false | false | false | false |
mrehkopf/sd2snes | verilog/sd2snes_sdd1/FIFO_B2B.vhd | 2 | 3,648 | ----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 18.03.2018 20:49:09
-- Design Name:
-- Module Name: FIFO_Input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FIFO_B2B is
Generic( FIFO_DEPTH : integer := 32;
PROG_FULL_TH : integer := 16);
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC );
end FIFO_B2B;
architecture Behavioral of FIFO_B2B is
type FIFO_Array_t is array(FIFO_DEPTH-1 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal FIFO_Array : FIFO_Array_t := (others => (others => '0'));
signal wr_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal rd_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal data_cnt : integer range 0 to FIFO_DEPTH := 0;
signal din_tready_i : STD_LOGIC := '0';
signal dout_tvalid_i : STD_LOGIC := '0';
begin
Process( clk )
Begin
if rising_edge( clk ) then
if( srst = '1' ) then
FIFO_Array <= (others => (others => '0'));
wr_ptr <= 0;
rd_ptr <= 0;
data_cnt <= 0;
else
-- write command
if( din_tready_i = '1' AND din_tvalid = '1' ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata;
-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
-- read command
if( dout_tready = '1' AND dout_tvalid_i = '1' ) then
-- check read pointer limits
if( rd_ptr = (FIFO_DEPTH-1) ) then
rd_ptr <= 0;
else
rd_ptr <= rd_ptr + 1;
end if;
end if;
-- occupancy control
-- write only
if((din_tready_i = '1' AND din_tvalid = '1') AND
(dout_tready = '0' OR dout_tvalid_i = '0')) then
data_cnt <= data_cnt + 1;
-- read only
elsif((din_tready_i = '0' OR din_tvalid = '0') AND
(dout_tready = '1' AND dout_tvalid_i = '1')) then
data_cnt <= data_cnt - 1;
end if;
end if;
end if;
End Process;
-- first word fall-through
dout_tdata <= FIFO_Array(rd_ptr);
dout_tvalid_i <= '0' when (data_cnt = 0 OR srst = '1') else '1';
dout_tvalid <= dout_tvalid_i;
-- flow control signals
empty <= '1' when data_cnt = 0 else '0';
full <= NOT din_tready_i;
prog_full <= '1' when (data_cnt >= PROG_FULL_TH OR srst = '1') else '0';
din_tready_i <= '0' when (data_cnt > (FIFO_DEPTH-1) OR srst = '1') else '1';
din_tready <= din_tready_i;
end Behavioral;
| gpl-2.0 | b741e7fcfc73d7f164724a99d5e990de | 0.537555 | 3.00742 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | video_ip/zed_hdmi/zed_hdmi.srcs/sources_1/new/src/convert_444_422.vhd | 1 | 2,593 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
-- Module Name: convert_444_422 - Behavioral
--
-- Description: Convert the input pixels into two RGB values - that for the Y calc
-- and that for the CbCr calculation
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity convert_444_422 is
Port ( clk : in STD_LOGIC;
-- pixels and control signals in
r_in : in STD_LOGIC_VECTOR (7 downto 0);
g_in : in STD_LOGIC_VECTOR (7 downto 0);
b_in : in STD_LOGIC_VECTOR (7 downto 0);
de_in : in std_logic;
-- two channels of output RGB + control signals
r1_out : out STD_LOGIC_VECTOR (8 downto 0);
g1_out : out STD_LOGIC_VECTOR (8 downto 0);
b1_out : out STD_LOGIC_VECTOR (8 downto 0);
r2_out : out STD_LOGIC_VECTOR (8 downto 0);
g2_out : out STD_LOGIC_VECTOR (8 downto 0);
b2_out : out STD_LOGIC_VECTOR (8 downto 0);
pair_start_out : out STD_LOGIC
);
end convert_444_422;
architecture Behavioral of convert_444_422 is
signal r_a : STD_LOGIC_VECTOR (7 downto 0);
signal g_a : STD_LOGIC_VECTOR (7 downto 0);
signal b_a : STD_LOGIC_VECTOR (7 downto 0);
signal d_a : STD_LOGIC;
signal d_a_last : STD_LOGIC;
-- flag is used to work out which pairs of pixels to sum.
signal flag : STD_LOGIC;
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
-- sync pairs to the de_in going high (if a scan line has odd pixel count)
if (d_a = '1' and d_a_last = '0') or flag = '1' then
r2_out <= std_logic_vector(unsigned('0' & r_a) + unsigned('0' & r_in));
g2_out <= std_logic_vector(unsigned('0' & g_a) + unsigned('0' & g_in));
b2_out <= std_logic_vector(unsigned('0' & b_a) + unsigned('0' & b_in));
flag <= '0';
pair_start_out <= '1';
else
flag <= '1';
pair_start_out <= '0';
end if;
r1_out <= r_a & "0";
b1_out <= b_a & "0";
g1_out <= g_a & "0";
d_a_last <= d_a;
r_a <= r_in;
g_a <= g_in;
b_a <= b_in;
d_a <= de_in;
end if;
end process;
end Behavioral; | mit | d6dfbb761fcba14d181cd84e6ba26533 | 0.49248 | 3.429894 | false | false | false | false |
pgavin/carpe | hdl/cpu/l1mem/inst/cache/cpu_l1mem_inst_cache_dp-rtl.vhdl | 1 | 16,870 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library tech;
library sys;
use sys.sys_config_pkg.all;
use sys.sys_pkg.all;
use work.cpu_l1mem_inst_cache_pkg.all;
use work.cpu_l1mem_inst_cache_config_pkg.all;
use work.cpu_types_pkg.all;
architecture rtl of cpu_l1mem_inst_cache_dp is
type reg_type is record
b_request_vpn : cpu_vpn_type;
b_request_poffset : cpu_ipoffset_type;
b_bus_op_paddr : cpu_ipaddr_type;
end record;
type comb_type is record
b_replace_rstate : cpu_l1mem_inst_cache_replace_state_type;
b_tram_rdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_dram_rdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
b_bus_op_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_bus_op_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_bus_op_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_ppn : cpu_ppn_type;
b_request_paddr : cpu_ipaddr_type;
b_request_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
b_request_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_request_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_cache_tag_match : std_ulogic_vector(cpu_l1mem_inst_cache_assoc-1 downto 0);
b_request_last_in_block : std_ulogic;
b_cache_way_read_data : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
b_cache_read_data : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_inst_bus : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_inst_cache : std_ulogic_vector(cpu_inst_bits-1 downto 0);
b_result_paddr : cpu_ipaddr_type;
b_result_inst : cpu_inst_type;
b_replace_windex : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_replace_wstate : cpu_l1mem_inst_cache_replace_state_type;
b_vram_waddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
b_mram_waddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_new_request_poffset : cpu_ipoffset_type;
a_new_request_vpn : cpu_vpn_type;
a_request_poffset : cpu_ipoffset_type;
a_request_vpn : cpu_vpn_type;
a_request_ppn : cpu_ppn_type;
a_request_bus_op_data : cpu_inst_type;
a_request_vaddr : cpu_vaddr_type;
a_request_paddr : cpu_ipaddr_type;
a_request_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_request_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_request_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_paddr_block_inst_offset_next : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_paddr : cpu_ipaddr_type;
a_bus_op_size : cpu_data_size_type;
a_bus_op_data : cpu_inst_type;
a_bus_op_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_bus_op_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_cache_wtag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_bus_op_cache_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_bus_op_cache_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_bus_op_tram_wdata_tag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_bus_op_sys_paddr : cpu_ipaddr_type;
a_bus_op_sys_data : cpu_inst_type;
a_bus_op_dram_wdata : std_ulogic_vector(cpu_inst_bits-1 downto 0);
a_sys_size : sys_transfer_size_type;
a_sys_paddr : sys_paddr_type;
a_sys_data : sys_bus_type;
a_cache_index : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_cache_offset : std_ulogic_vector(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_vram_raddr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_tram_addr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
a_tram_wtag : std_ulogic_vector(cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_tram_wdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_l1mem_inst_cache_tag_bits-1 downto 0);
a_dram_addr : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto 0);
a_dram_wdata_inst : std_ulogic_vector(cpu_inst_bits-1 downto 0);
a_dram_wdata : std_ulogic_vector2(cpu_l1mem_inst_cache_assoc-1 downto 0,
cpu_inst_bits-1 downto 0);
a_replace_rindex : std_ulogic_vector(cpu_l1mem_inst_cache_index_bits-1 downto 0);
end record;
signal c : comb_type;
signal r, r_next : reg_type;
begin
c.b_replace_rstate <= cpu_l1mem_inst_cache_replace_dp_out.rstate;
c.b_tram_rdata <= cpu_l1mem_inst_cache_dp_in_tram.rdata;
c.b_dram_rdata <= cpu_l1mem_inst_cache_dp_in_dram.rdata;
----------------------------------
c.b_request_ppn <= cpu_mmu_inst_dp_out.ppn;
c.b_request_paddr <= c.b_request_ppn & r.b_request_poffset;
c.b_request_tag <= c.b_request_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.b_request_index <= c.b_request_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1
downto cpu_l1mem_inst_cache_offset_bits);
c.b_request_offset <= c.b_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
b_request_tag_match_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
c.b_request_cache_tag_match(n) <=
logic_eq(c.b_request_tag,
std_ulogic_vector2_slice2(c.b_tram_rdata, n));
end generate;
c.b_request_last_in_block <= all_ones(c.b_request_offset);
----------------------------------
b_cache_read_data_way_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_loop : for b in cpu_inst_bits-1 downto 0 generate
c.b_cache_way_read_data(n, b) <= c.b_dram_rdata(n, b);
end generate;
end generate;
b_cache_read_data_mux : entity tech.mux_1hot(rtl)
generic map (
data_bits => cpu_inst_bits,
sel_bits => cpu_l1mem_inst_cache_assoc
)
port map (
din => c.b_cache_way_read_data,
sel => cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_read_data_way,
dout => c.b_cache_read_data
);
----------------------------------
c.b_bus_op_tag <= r.b_bus_op_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.b_bus_op_index <= r.b_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.b_bus_op_offset <= r.b_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
----------------------------------
c.b_result_inst_bus <= sys_slave_dp_out.data(cpu_inst_bits-1 downto 0);
c.b_result_inst_cache <= c.b_cache_read_data;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_result_inst_sel select
c.b_result_inst <= c.b_result_inst_cache when cpu_l1mem_inst_cache_b_result_inst_sel_b_cache,
c.b_result_inst_bus when cpu_l1mem_inst_cache_b_result_inst_sel_b_bus,
(others => 'X') when others;
----------------------------------
with cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_owner select
c.b_replace_windex <= c.b_request_index when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
c.b_replace_wstate <= c.b_replace_rstate;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_cache_owner select
c.b_vram_waddr <= c.b_request_index when cpu_l1mem_inst_cache_owner_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
--------------------------
c.a_new_request_poffset <= cpu_l1mem_inst_cache_dp_in.vaddr(cpu_ipoffset_bits-1 downto 0);
c.a_new_request_vpn <= cpu_l1mem_inst_cache_dp_in.vaddr(cpu_ivaddr_bits-1 downto cpu_ipoffset_bits);
with cpu_l1mem_inst_cache_dp_in_ctrl.b_request_complete select
c.a_request_poffset <= c.a_new_request_poffset when '1',
r.b_request_poffset when '0',
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.b_request_complete select
c.a_request_vpn <= c.a_new_request_vpn when '1',
r.b_request_vpn when '0',
(others => 'X') when others;
c.a_request_ppn <= c.b_request_ppn;
c.a_request_paddr <= c.a_request_ppn & c.a_request_poffset;
c.a_request_tag <= c.a_request_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
c.a_request_index <= c.a_request_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.a_request_offset <= c.a_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
--------------------------------
c.a_bus_op_dram_wdata <= sys_slave_dp_out.data;
a_bus_op_paddr_block_inst_offset_next_gen : if cpu_l1mem_inst_cache_offset_bits > 0 generate
c.a_bus_op_paddr_block_inst_offset_next <=
std_ulogic_vector(unsigned(r.b_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0)) +
to_unsigned(1, cpu_l1mem_inst_cache_offset_bits));
end generate;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_tag_sel select
c.a_bus_op_paddr(cpu_ipaddr_bits-1 downto cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits) <=
c.a_request_tag when cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_request,
c.b_bus_op_tag when cpu_l1mem_inst_cache_a_bus_op_paddr_tag_sel_old,
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_index_sel select
c.a_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto cpu_l1mem_inst_cache_offset_bits) <=
c.a_request_index when cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_request,
c.b_bus_op_index when cpu_l1mem_inst_cache_a_bus_op_paddr_index_sel_old,
(others => 'X') when others;
a_bus_op_paddr_block_inst_offset_gen : if cpu_l1mem_inst_cache_offset_bits > 0 generate
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_paddr_offset_sel select
c.a_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0) <=
c.b_bus_op_offset(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_old,
c.a_bus_op_paddr_block_inst_offset_next when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_next,
c.a_request_offset(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_a_bus_op_paddr_offset_sel_request,
(others => 'X') when others;
end generate;
c.a_bus_op_index <= c.a_bus_op_paddr(cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits-1 downto
cpu_l1mem_inst_cache_offset_bits);
c.a_bus_op_offset <= c.a_bus_op_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0);
c.a_bus_op_cache_wtag <= r.b_bus_op_paddr(cpu_ipaddr_bits-1 downto
cpu_l1mem_inst_cache_index_bits+cpu_l1mem_inst_cache_offset_bits);
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_index <=
c.a_bus_op_index when '0',
c.b_bus_op_index when '1',
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_bus_op_cache_paddr_sel_old select
c.a_bus_op_cache_offset <=
c.a_bus_op_offset when '0',
c.b_bus_op_offset when '1',
(others => 'X') when others;
c.a_bus_op_sys_paddr <= c.a_bus_op_paddr;
--------------------------------
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_cache_index <= c.a_request_index when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_cache_index when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_cache_offset <= c.a_request_paddr(cpu_l1mem_inst_cache_offset_bits-1 downto 0)
when cpu_l1mem_inst_cache_owner_request,
c.a_bus_op_cache_offset
when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
c.a_vram_raddr <= c.a_cache_index;
c.a_tram_addr <= c.a_cache_index;
c.a_tram_wtag <= c.a_bus_op_cache_wtag;
a_tram_wdata_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_gen : for b in cpu_l1mem_inst_cache_tag_bits-1 downto 0 generate
c.a_tram_wdata(n, b) <= c.a_tram_wtag(b);
end generate;
end generate;
c.a_replace_rindex <= c.a_cache_index;
c.a_dram_addr <= c.a_cache_index & c.a_cache_offset;
with cpu_l1mem_inst_cache_dp_in_ctrl.a_cache_owner select
c.a_dram_wdata_inst <= c.a_bus_op_dram_wdata when cpu_l1mem_inst_cache_owner_bus_op,
(others => 'X') when others;
a_dram_wdata_gen : for n in cpu_l1mem_inst_cache_assoc-1 downto 0 generate
bit_loop : for b in cpu_inst_bits-1 downto 0 generate
c.a_dram_wdata(n, b) <= c.a_dram_wdata_inst(b);
end generate;
end generate;
c.a_sys_size <= std_ulogic_vector(to_unsigned(cpu_log2_inst_bytes, sys_transfer_size_bits));
c.a_sys_paddr <= (sys_paddr_bits-1 downto cpu_paddr_bits => '0') & c.a_bus_op_sys_paddr & (cpu_log2_inst_bytes-1 downto 0 => '0');
c.b_result_paddr <= r.b_bus_op_paddr;
r_next <= (
b_request_poffset => c.a_request_poffset,
b_request_vpn => c.a_request_vpn,
b_bus_op_paddr => c.a_bus_op_paddr
);
cpu_l1mem_inst_cache_dp_out_ctrl <= (
b_request_last_in_block => c.b_request_last_in_block,
b_request_cache_tag_match => c.b_request_cache_tag_match
);
cpu_l1mem_inst_cache_dp_out_vram <= (
raddr => c.a_vram_raddr,
waddr => c.b_vram_waddr
);
cpu_l1mem_inst_cache_dp_out_tram <= (
addr => c.a_tram_addr,
wdata => c.a_tram_wdata
);
cpu_l1mem_inst_cache_dp_out_dram <= (
addr => c.a_dram_addr,
wdata => c.a_dram_wdata
);
cpu_l1mem_inst_cache_replace_dp_in <= (
rindex => c.a_replace_rindex,
windex => c.b_replace_windex,
wstate => c.b_replace_wstate
);
cpu_l1mem_inst_cache_dp_out <= (
paddr => c.b_result_paddr,
data => c.b_result_inst
);
cpu_mmu_inst_dp_in <= (
vpn => c.a_request_vpn
);
sys_master_dp_out <= (
size => c.a_sys_size,
paddr => c.a_sys_paddr,
data => (others => 'X')
);
process (clk) is
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process;
end;
| apache-2.0 | afddaa60dda29ab1d0d3f6b04a335d3f | 0.60409 | 2.890679 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/hdl/reg_file_bram.vhd | 1 | 6,465 | -------------------------------------------------------------------------------
-- Title : A Register File Made of Dual Port Block RAM
-------------------------------------------------------------------------------
-- Platform : Xilinx Spartan 3A
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: A Larger Register File Using Block RAM.
--
-- A dual port block RAM is interfaced to the internal parallel
-- bus.
--
-- Each SelectRAM in Spartan-3(A/E/AN) has 18432 data bits and can
-- be configured as 1024 address x 16 data bits.
--
-- Port A of Block RAM: connected to the internal parallel bus:
-- 1024 addresses of 16 bits
-- 1024 address = 10 bits (9 downto 0)
--
-- Port B: used by the internal processes of the design.
-- Same configuration
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.reset_pkg.all;
use work.xilinx_block_ram_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_bram is
generic (
-- The module uses 10 bits for 1024 addresses and the base address must be aligned.
-- Valid BASE_ADDRESSes are 0x0000, 0x0400, 0x0800, ...
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
-- Interface to the internal parallel bus.
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- Read and write interface to the block RAM for the application.
bram_data_i : in std_logic_vector(15 downto 0) := (others => '0');
bram_data_o : out std_logic_vector(15 downto 0) := (others => '0');
bram_addr_i : in std_logic_vector(9 downto 0) := (others => '0');
bram_we_p : in std_logic := '0';
-- Dummy reset, all signals are initialised.
reset : in std_logic;
clk : in std_logic);
end reg_file_bram;
-------------------------------------------------------------------------------
architecture str of reg_file_bram is
constant BASE_ADDRESS_VECTOR : std_logic_vector(14 downto 0) :=
std_logic_vector(to_unsigned(BASE_ADDRESS, 15));
-- Port A to bus
constant ADDR_A_WIDTH : positive := 10;
constant DATA_A_WIDTH : positive := 16;
-- Port B to application
constant ADDR_B_WIDTH : positive := 10;
constant DATA_B_WIDTH : positive := 16;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal ram_a_addr : std_logic_vector(ADDR_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_out : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_in : std_logic_vector(DATA_A_WIDTH-1 downto 0) := (others => '0');
signal ram_a_we : std_logic := '0';
signal ram_a_en : std_logic := '0';
signal ram_a_ssr : std_logic := '0';
signal ram_b_addr : std_logic_vector(ADDR_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_out : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_in : std_logic_vector(DATA_B_WIDTH-1 downto 0) := (others => '0');
signal ram_b_we : std_logic := '0';
signal ram_b_en : std_logic := '0';
signal ram_b_ssr : std_logic := '0';
--
signal addr_match_a : std_logic;
signal bus_o_enable_d : std_logic := '0';
signal bus_o_enable_d2 : std_logic := '0';
begin -- str
----------------------------------------------------------------------------
-- Connections
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Block RAM as dual port RAM with asymmetrical port widths.
----------------------------------------------------------------------------
dp_1 : xilinx_block_ram_dual_port
generic map (
ADDR_A_WIDTH => ADDR_A_WIDTH,
ADDR_B_WIDTH => ADDR_B_WIDTH,
DATA_A_WIDTH => DATA_A_WIDTH,
DATA_B_WIDTH => DATA_B_WIDTH)
port map (
addr_a => ram_a_addr,
addr_b => ram_b_addr,
din_a => ram_a_in,
din_b => ram_b_in,
dout_a => ram_a_out,
dout_b => ram_b_out,
we_a => ram_a_we,
we_b => ram_b_we,
en_a => ram_a_en,
en_b => ram_b_en,
ssr_a => ram_a_ssr,
ssr_b => ram_b_ssr,
clk_a => clk,
clk_b => clk);
----------------------------------------------------------------------------
-- Port A: parallel bus
----------------------------------------------------------------------------
-- Always present the address from the parallel bus to the block RAM.
-- When the bus address matches the address range of the block RAM
-- route the result of the Block RAM to the parallel bus.
ram_a_addr <= bus_i.addr(ADDR_A_WIDTH-1 downto 0);
ram_a_in <= bus_i.data;
-- ADDR_A_WIDTH = 10
-- 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- |<---- match ---->|
addr_match_a <= '1' when (bus_i.addr(14 downto ADDR_A_WIDTH) = BASE_ADDRESS_VECTOR(14 downto ADDR_A_WIDTH)) else '0';
-- Always enable RAM
ram_a_en <= '1';
-- The block RAM keeps its output latches when EN is '0'. This behaviour is
-- not compatible with the parallel bus where the bus output must be 0 when
-- the device is not selected.
-- Solution: Use Synchronous Reset of the output latches:
ram_a_ssr <= '0' when (addr_match_a = '1') and (bus_i.re = '1') else '1';
-- Write enable
ram_a_we <= '1' when (addr_match_a = '1') and (bus_i.we = '1') else '0';
bus_o.data <= ram_a_out;
----------------------------------------------------------------------------
-- Port B: internal device
----------------------------------------------------------------------------
-- always enable the RAM
ram_b_en <= '1';
-- write to the RAM
ram_b_we <= bram_we_p;
ram_b_addr <= bram_addr_i;
ram_b_in <= bram_data_i;
bram_data_o <= ram_b_out;
end str;
-------------------------------------------------------------------------------
| bsd-3-clause | b084d3f180d78ed7de0f8fc17374c55b | 0.464346 | 3.868941 | false | false | false | false |
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