AWfaw/ai-hdlcoder-dataset-clean · Datasets at Hugging Face

repo_name stringlengths 6 79	path stringlengths 6 236	copies int64 1 472	size int64 137 1.04M	content stringlengths 137 1.04M	license stringclasses 15 values	hash stringlengths 32 32	alpha_frac float64 0.25 0.96	ratio float64 1.51 17.5	autogenerated bool 1 class	config_or_test bool 2 classes	has_no_keywords bool 1 class	has_few_assignments bool 1 class
siavooshpayandehazad/TTU_CPU_Project	pico_CPU_pipelined_MIPS32/PicoCPU.vhd	1	6,316	--Copyright (C) 2017 Siavoosh Payandeh Azad library IEEE; use IEEE.std_logic_1164.all; USE ieee.std_logic_unsigned.ALL; use work.pico_cpu.all; entity PicoCPU is generic (Mem_preload_file: string :="code.txt"); port( rst: in std_logic; clk: in std_logic; IO: inout std_logic_vector (CPU_Bitwidth-1 downto 0) ); end PicoCPU; architecture RTL of PicoCPU is --------------------------------------------- -- Signals --------------------------------------------- signal Instr_In : std_logic_vector (CPU_Bitwidth-1 downto 0); signal Instr_Add, Instr_Add_mem : std_logic_vector (CPU_Bitwidth-1 downto 0); ---------------------------------------- signal MemRdAddress : std_logic_vector (CPU_Bitwidth-1 downto 0); signal MemWrtAddress : std_logic_vector (CPU_Bitwidth-1 downto 0); signal Mem_RW : std_logic_vector (3 downto 0); ---------------------------------------- signal IO_DIR : std_logic; signal IO_RD : std_logic_vector (CPU_Bitwidth-1 downto 0); signal IO_WR : std_logic_vector (CPU_Bitwidth-1 downto 0); ---------------------------------------- signal DPU_OV : std_logic; signal DataToDPU_2 : std_logic_vector (CPU_Bitwidth-1 downto 0); ---------------------------------------- signal DPU_ALUCommand : ALU_COMMAND; signal DPU_Mux_Cont_2 : DPU_IN_MUX; ---------------------------------------- signal RFILE_data_sel : RFILE_IN_MUX; signal Data_to_RFILE : std_logic_vector (CPU_Bitwidth-1 downto 0); signal RFILE_in_address: std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); signal WB_enable : std_logic_vector (3 downto 0); signal RFILE_out_sel_1, RFILE_out_sel_1_in : std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); signal RFILE_out_sel_2, RFILE_out_sel_2_in : std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); signal DPU_RESULT, DPU_RESULT_out : std_logic_vector (2CPU_Bitwidth-1 downto 0); signal Result_ACC : std_logic_vector (2CPU_Bitwidth-1 downto 0); -- Register file outputs signal R1, R2, R2_FF : std_logic_vector (CPU_Bitwidth-1 downto 0); signal MEMDATA_OUT, MEMDATA_IN: std_logic_vector (CPU_Bitwidth-1 downto 0) := (others=>'0'); signal Mem_Rd_Address_in : std_logic_vector (CPU_Bitwidth-1 downto 0) := (others=>'0'); signal MEM_IN_SEL : MEM_IN_MUX; begin --------------------------------------------- -- component instantiation --------------------------------------------- CLOCK_PROCESS:process (clk, rst)begin if rst = '1' then RFILE_out_sel_1<= (others => '0'); RFILE_out_sel_2<= (others => '0'); R2_FF <= (others => '0'); DPU_RESULT_out <= (others => '0'); elsif clk'event and clk='1' then RFILE_out_sel_1<= RFILE_out_sel_1_in; RFILE_out_sel_2<= RFILE_out_sel_2_in; R2_FF <= R2; DPU_RESULT_out <= DPU_RESULT; end if; end process; gpio_comp: GPIO generic map (BitWidth => CPU_Bitwidth) port map (IO_DIR, IO, IO_WR, IO_RD); ControlUnit_comp: ControlUnit generic map (BitWidth => CPU_Bitwidth, InstructionWidth => CPU_Instwidth) port map ( rst => rst , clk => clk , ------------------------------------------- Instr_In => Instr_In , Instr_Add => Instr_Add , ------------------------------------------- MemRdAddress => MemRdAddress , MemWrtAddress => MemWrtAddress , Mem_RW => Mem_RW , MEM_IN_SEL => MEM_IN_SEL , ------------------------------------------- IO_DIR => IO_DIR , IO_RD => IO_RD , IO_WR => IO_WR , ------------------------------------------- DPU_OV => DPU_OV , DataToDPU_2 => DataToDPU_2 , DPU_ALUCommand => DPU_ALUCommand , DPU_Mux_Cont_2 => DPU_Mux_Cont_2 , ------------------------------------------- RFILE_data_sel => RFILE_data_sel , RFILE_in_address=> RFILE_in_address , RFILE_WB_enable => WB_enable, RFILE_out_sel_1 => RFILE_out_sel_1_in, RFILE_out_sel_2 => RFILE_out_sel_2_in, Data_to_RFILE => Data_to_RFILE , DPU_RESULT => DPU_RESULT , Result_ACC => Result_ACC ); --register file RegFile_comp: RegisterFile generic map (BitWidth => CPU_Bitwidth) port map ( clk => clk, rst => rst, Data_in_mem => MEMDATA_OUT, Data_in_CU => Data_to_RFILE, Data_in_DPU_LOW => DPU_RESULT_out(CPU_Bitwidth-1 downto 0), Data_in_ACC_HI => Result_ACC(2*CPU_Bitwidth-1 downto CPU_Bitwidth), Data_in_ACC_LOW => Result_ACC(CPU_Bitwidth-1 downto 0), Data_in_R2 => R2_FF, Data_in_sel => RFILE_data_sel, RFILE_in_address => RFILE_in_address, WB_enable => WB_enable, Register_out_sel_1 => RFILE_out_sel_1, Register_out_sel_2 => RFILE_out_sel_2, Data_out_1 => R1, Data_out_2 => R2); --datapath unit DPU_comp: DPU generic map (BitWidth => CPU_Bitwidth) port map ( rst => rst, clk => clk, Data_in_mem => MEMDATA_OUT, Data_in_RegFile_1=> R1, Data_in_RegFile_2=> R2, Data_in_control_2=> DataToDPU_2, ALUCommand => DPU_ALUCommand, Mux_Cont_2 => DPU_Mux_Cont_2, DPU_OV => DPU_OV, Result => DPU_RESULT, Result_ACC => Result_ACC); -- MEMORY Input select MUX MEM_DATA_IN_SELECT: process(MEM_IN_SEL, RFILE_out_sel_1, RFILE_out_sel_2, DPU_Result)begin case( MEM_IN_SEL ) is when RFILE_DATA_1 => MEMDATA_IN <= R1; when RFILE_DATA_2 => MEMDATA_IN <= R2; when DPU_DATA => MEMDATA_IN <= DPU_Result(CPU_Bitwidth-1 downto 0); when others => MEMDATA_IN <= (others => '0'); end case; end process; --memory Instr_Add_mem <= "00" & Instr_Add(CPU_Bitwidth-1 downto 2); Mem_comp: RAM generic map (BitWidth => CPU_Bitwidth, preload_file => Mem_preload_file) port map (MemRdAddress, Instr_Add_mem, MEMDATA_IN, MemWrtAddress, clk, Mem_RW , rst , MEMDATA_OUT, Instr_In); end RTL;	gpl-2.0	b251491bebedda393dd89aef551c259a	0.514566	3.361362	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/instantiation/rule_033_test_input.fixed_remove.vhd	1	559	architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_ENTITY_INST : entity FIFO(rtl); -- Violations below U_INST1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1:INST port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;	gpl-3.0	0b05bc9512f825c9a1dd5e820cdf7375	0.483005	2.753695	false	false	false	false
rjarzmik/mips_processor	Caches/Simulated_Memory_tb.vhd	1	6,735	------------------------------------------------------------------------------- -- Title : Testbench for design "Simulated_Memory" -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : Simulated_Memory_tb.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-21 -- Last update: 2016-12-29 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-21 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity Simulated_Memory_tb is end entity Simulated_Memory_tb; ------------------------------------------------------------------------------- architecture rtl of Simulated_Memory_tb is -- component generics constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; constant MEMORY_LATENCY : natural := 1; constant addr_zero : std_logic_vector(ADDR_WIDTH -1 downto 0) := std_logic_vector(to_unsigned(0, ADDR_WIDTH)); -- component ports signal clk : std_logic := '1'; signal rst : std_logic := '1'; signal i_memory_req : std_logic := '1'; signal i_memory_we : std_logic := '0'; signal i_memory_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := addr_zero; signal i_memory_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_memory_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_memory_valid : std_logic; signal addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := addr_zero; signal next_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := addr_zero; signal output_next_addr : boolean; signal first_clk : boolean := true; -- clock signal cycle : natural := 0; -- test signal test_block_i_memory_req : boolean := false; signal test_force_clear_i_memory_req : boolean := false; signal in_read_continuous : boolean := false; signal in_read_always_memory_req_on : boolean := false; signal read_continuous_incr_addr : boolean := false; signal read_always_memory_req_on_incr_addr : boolean := false; signal read_continuous_first_clk : boolean := true; signal read_always_memory_req_on_first_clk : boolean := true; begin -- architecture rtl -- component instantiation DUT : entity work.Simulated_Memory generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, MEMORY_LATENCY => MEMORY_LATENCY) port map ( clk => clk, rst => rst, i_memory_req => i_memory_req, i_memory_we => i_memory_we, i_memory_addr => i_memory_addr, i_memory_write_data => i_memory_write_data, o_memory_read_data => o_memory_read_data, o_memory_valid => o_memory_valid); -- reset rst <= '0' after 12 ps; -- clock generation clk <= not clk after 5 ps; -- waveform generation clk_cycles : process(clk) begin if rst = '0' and rising_edge(clk) then cycle <= cycle + 1; if cycle > 1 then first_clk <= false; end if; end if; end process clk_cycles; process_incr_addr : process(clk, read_continuous_incr_addr, read_always_memory_req_on_incr_addr) begin if rst = '0' and rising_edge(clk) then if in_read_continuous or in_read_always_memory_req_on then if read_continuous_incr_addr or read_always_memory_req_on_incr_addr then addr <= std_logic_vector(to_unsigned( (to_integer(unsigned(addr)) + 4) mod 16, ADDR_WIDTH)); end if; else addr <= (others => '0'); end if; end if; end process process_incr_addr; read_continuous : process(clk, o_memory_valid) begin if rst = '0' and rising_edge(clk) and cycle > 0 and cycle <= (MEMORY_LATENCY + 1) * 7 and rising_edge(clk) then in_read_continuous <= true; read_continuous_first_clk <= false; if MEMORY_LATENCY > 0 then if o_memory_valid = '1' then read_continuous_incr_addr <= true; else read_continuous_incr_addr <= false; end if; else read_continuous_incr_addr <= true; end if; elsif rst = '0' and rising_edge(clk) then in_read_continuous <= false; read_continuous_incr_addr <= false; end if; end process read_continuous; read_always_memory_req_on : process(clk, o_memory_valid) begin if rst = '0' and rising_edge(clk) and cycle > (MEMORY_LATENCY + 1) * 10 and cycle <= (MEMORY_LATENCY + 1) * 20 then in_read_always_memory_req_on <= true; test_block_i_memory_req <= true; read_always_memory_req_on_first_clk <= false; elsif rst = '0' and rising_edge(clk) then in_read_always_memory_req_on <= false; end if; end process read_always_memory_req_on; read_always_memory_req_on_incr_addr <= in_read_always_memory_req_on and (MEMORY_LATENCY = 0 or o_memory_valid = '1'); output_next_addr <= (MEMORY_LATENCY = 0 or o_memory_valid = '1'); i_memory_addr <= next_addr when output_next_addr else addr; next_addr <= std_logic_vector(to_unsigned( (to_integer(unsigned(addr)) + 4) mod 16, ADDR_WIDTH)); i_memory_req <= '1' when (in_read_continuous or in_read_always_memory_req_on) and (MEMORY_LATENCY = 0 or test_block_i_memory_req or (output_next_addr or first_clk)) else '0'; end architecture rtl; ------------------------------------------------------------------------------- configuration Simulated_Memory_tb_rtl_cfg of Simulated_Memory_tb is for rtl end for; end Simulated_Memory_tb_rtl_cfg; -------------------------------------------------------------------------------	gpl-3.0	f41776ba64f993650ff9e9bdd9327293	0.507498	4.013707	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_dc_as.vhd	2	10,777	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block oN5tQGv58ad0TQklq+ppWUJeb7KNziI+enTXsg5uou7kjLrVMoZMjxkV6jourW354ejkuKrT/kAD Na4sJwnObQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FJ6okuHClgRqD6ZirYpockIZO9fK2XpcheuWxJbU6nlx70KpsxYoCyupKKngvK5C2jf1ONvlvroj BkiNOfoH3PNzIoPKcYti4SH2ogIAmxCCm/FSG2Y+ze45k0DndsmjFuu1l1fF63sy3XNvzijc2ZjQ pxn+5OMxmWiB1rBCGCg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block T8yqDgkeqDZWBEiLh685sm7+Ou5Sn93bKceOpzQP1xPHtpWXmwAbpAwbWPwTYU44J/AXx130r72u vhrhqArSpaXtmy5Go3PHf7nvTpoLzNXP7O0lRtTI6I1HZC9ACIWoES4AxMDXxebKjK0GzhFqYjYB 5F1Ipq6tgGdUxmyXtc2/A18c785S1dklUXS1f5Ii3HRlZemsU+/9t7cySD5EHWSiTIF9sx+7GmKL UjCU9MgHaGcioSCpXxB6Ur+ju47QOfVzKXHHHox64+sOal2Mhhur6ma//2TshO0Rzg3jy14sKsT9 QU6Fcdy2kBNwCBj8O2tAgFfM5ozHMQ7ilI2qLg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mu2sas6InMk1EV2ILj0n93KttbGY4SP/9/xti0Nu96OPFobz+j0qvQ6FkFC1cEiHwG+ol8xFWMVh //IZYmpuAsyQNdeuZjnqSZm7EMWS/cMo+6IncixBL+zZEYkY2+0Es1UOK+ljAgYWHiwEp2FHfgRJ 6es7lBB5FypyplCcOMw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block d4P9EjiQtTxgNXURxrnK8qSPqHjHt8xA1GOptATncCNOFJwu0ktb9wrtWChHh72FQ2cIFKub8WP9 ealyFk2ZW0OH1E1pU2UkIaNVZraKmxdq9gaJK3s5sSYqSHM/Xm/7MzH5b/bIt8eH3nAgEgSdtJKL hV/8eAjjDO+wYpUT3mDNCT8aC5OyCe8TipvETFHFBCBo/CMAt9LU7Hb/Ku7IKaBtIZr2s9IsHrI6 X34+j14snZ/alsLlhNyaXTIcgA4izC+bsl219s9XrniHDjZHKUW2KOx0QX0C4lGCVSrvUNku7y3F 91XqLYJYmDOevgbfe9SAYLPmR7hFuiYeD5riCw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240) `protect data_block UuzWrNt0cjl7oHFjPBZDlq+weV1NskmPnuVZdUKfLHKm/l7uODLgPYKYsMgaRtWdeKtfTg6NSgN3 LVUnsRrQEOrIpqrhK5fiPF2MLt6Y0H87O0EWeDhjM1A737tmqZKlBJg5DDi67drLL1R7G0gximV/ la+kQo4CE8zdij6jYtCpdkNwP1CXNjZFVQG/RYBZ2HBV2o6Xjy1gq7bBSdQaCnCWYc3qntJZnBs9 ZalbB+/CSagRcC9EvIn24gDC4Se68RUDS19red9k7h5sS+e9bN9EJ1mfaYsq/cIbw/8P5nllg4FW Fa5zN+HORUnMNvQWDOvw5z6S3+wAURhhev6prvSmWatiMrjb4qn4xii0hrVFNU0azvFKnL55HyTU CkYSAStmxM3ir2pvBWAmMPl18uEQw4BLHIt4LS+K672hr9LSlF2XdFG6MQS2xsCqUeO2wTomakEw yMQDbsGMjm5ipF7WQpEDosHJUxJczJWH4i2K3ly3GD+UaG+F6D0v2j4cu9ejDNN2r08Hvw8zLmAU 5lzzGB6RVhLtYrFh5kturZt6molXpNDnu1yV/FQ21Uya2YVSAvB/MOBWugUKjHqv/LA/PNGD6tzn fB9j9n2grPeYqeCvQa4kId+VOq0e9229/gnYXrrSFgezsoOHP8Etu3Q/AYe9nIjBhqsKWa1k68uG TkxHV6SzoTCQZ99tr9HemlHTabKLfmKsFy7pa3KUr6Q/cMfT5ARoGY49cvtE4EktDlpJorIrToac j/e2+PZuowDN4TrkjE7WIFMFQcqEWo60OR+K+I5nXNZdYSjfeiWc06UDBaCB2GOgGmAP3VXJTBS1 GmR3gkS/oqjBClhVbvjxpVhpdDBrMxP7/eObiJTuTBXvA/KcaXguZmZaV7J4N0f69n28Ozh562R1 XTluT07glbnYvp8W758pXZW4sFewKmv1QbA4XRFTIXfyZPu9LB/6nlmg17KS1WESEUEZwMP9Kfec V3UoDTniOmv5yGY4DOO8I3By0h02M7XAImEmTuikoizwUIDIquwYzXsMrhtKBSZxtowHW0djTxY9 kXlRsC1yz7kMimHhSpcQWodlc1DONvgPsvLdz2MV1FJFBGcnvr2N+F7bmUkA2jVAWECf+n2B4Pil /biV4/3EG6jydVVuiZEMTRcsu5UIl/MCu2Lnuau7XGnexjxUkxI4tS/k7RhwaVbuaqE+g9q+PTTh /lFj0X7avInSqF0nqp2Yq820ahGEehenHlz54Rn4tvVigiJa4nrBwtpLEEBP4NpyDkb2PKvZmBHf gN23mVT3QqaBl5poN//JueoLkoSMhl/KgiBgY6oGiViits2LXCx0QTI1G8zNE14/14hmz5LfZtQ4 r48HU/y3yKzNDuSSxwKAf5N5RVeTJcDrVv+4iPzgUE9dhIpzG7uiICRcYutIE+qi0O6N8+PCeDrw 0JYvjKfIanLDn4hNSzMsVqsDtqTZ7OL2xscNGRGmJirnqdgyg0YWrl9lIFOYJRSYp8bUHaDb9D20 P6oVdchHzr/7c/81siMBmvVLj1hfh8TWqKiIgWmOmOEO2ur26KwC3DoEolurQYtde3TV0vyJJOKC OtdZV8nKDQBuZ0gxpa0taEl2GfLcO72NTWTgFQ0ot+k6q+evp1pSmPPvp7tCyaUNCgzXb47KY0mk pYNUlTvGNhlTrzxjkHLfqSIfoyH0dqiPxcseI0UsnB1e/nrS2Y2sLrJ7HkwXiIPT/YYYuC/YFE1e 03tSS/0MY5yaCEGCbIhvouAS8zdtWaSWmkCm5CBOZGwd6SWnkj6GChus0t0Ae1xJ5FyStY09/d2J pq8jhAlF98jIarFSSi93LQv9wsK78z5qayES0q7xXODV3+f76TFB1G0wAhhqIKVntKxM8Cfq2cF1 VT8t1uMqzKYHFf6AcA4WmU+CtiWS7U6e5YhSs7kGK6ImBmG1nXewSh+o5146KNOBnjfBsQK/hVer Euzk93jwlYr91CEc6HIH2XoUxC9/ENeAQAhw+ZuBpLi6B/zXO2A7d3QAx4Qg8abKrYkDyviGqe9X u7InXUpyeVziAvMug+ztFyGeliKbvZW4jYR2SNoF/cl4rsbeADov6mYW07JgKCGDKBfkq3PdJu1c MEJTCbu7i68iU7g8YDtb8yKy0053ds88c+6Wc+C97hk8u1S53Qm75zlxhtPmzFThOC0+mp9QIiPx pTDrcFZNLj0ahueWiRd+nPACguYKc4SMoc1TU+azBD3j0Q/kgCVNQ5IG2nqLm+Ya3/STp4YOidNG FqeiNyUKeBovPgat7C6CCDvpHsb3Rohgxk57BDu5gShh2WJBGFgerFDLKyp3vq8j2+2JEyT+i/0d fK77pxQLxYrA7zJCngYhbLbHNmyl2IBH0WIa4m5E1qGYS4H+ci+PNIjDlr4ZSJuISsFC2UC9gnuc bJjgh5wCl5yvMeffbndG1spcLXCEeerKNCEOJI4WsBjbqFXla8Xdarj4/d+9q15UeJv3kdpVVJmn LwaTo6tVRb85eaZ7o+sS0EE/7pS3WTOhGJk/RRxNERpMe6D4oYppqYpylR18cM0oDp45rW1ecqq1 GXdh2FP8dlLIaZwgQTiFNmSeCQbfNhvntjoPgx3UIZDzmV39QBrzzzEy5kmOY51GeHziTwehWuoW m4eyJwp1Qb3dr2ZWQtqwWCQorcXQIkSSQbCU+3IfzwUvk1+VjVPt6ZA5qpphwDx9sJ7oRLR1PUr2 XuC30kiY9eAguwj09lzxqCUONQpzh33X1lbsjljSoSKkvqVvrFSDWa3xJpUR7/InJ+7v25UPotPL 1AQizxnojVWc2smBF3L7mVP/N0rqIpjiivIJsgDo7LFbeKlXjTu6ZRPXbOdqXWnKwfyxsK6a3Epf wqD5vp8U7Foq5JXfVSNDYo/Ykuya5fooodPtcT3RkoaTQRV82L9u7TcL8DdSdekxw6Hra4i2AoJy 9j6WB0dk+RAGdR8+TLhHq88Ttr/55BoS4hf4joeuPtOCizeTJuDg8CEtvfIiKbL9b5gqG0cSIMCj XciIyDV1X4pG0DYSAlEe9WUER/QBVMydY+5i3FyF4pN5On9YFNcEMgoBVKy/roi+LxYZbGqhxLpH aDiFuPJTTd3yN8Q6+v1z8CxX1TY9qsqIF9+g0RiV5vcKFi/H/kYYwT7V3ILVV0l2BtitjjgHMBdz g0XGMeZHk1laKtQeRMj59C0WSiOLIxNTZOR8AgRitvuYBeioFhPm6q30IEWpG25JFfbNAHvUA/u0 pSsikK1qlYmjVllRJ/BoAhEK0OTfL6EYUdh7RXT2CINNARMZM/iA0DGL097s26Kbs3LGum9Wm6CU Ka/HPmVfNw8uFLx3nOZlAuZFFDkXjtcFwCS5Ce6y/1Gsla4IM5XajVORH4+5vORJF8tN5vrLxD+0 nmP+gWb7XM+uFQb73kJR1V9A1b2TaQqGI2JrLTUXb8MYGSDSzTtc7TvrO+cbTjKjgjbL+qGYoE2E ttWqarSK2QSj7SBth8tjbulLI+bLxRvCCo5/iWyTRneTPVbFzWkEk4UIm7GHhk+uj0m6dUxX8X6/ LLUcwHwJZerqdE8vute13BWp2Va0CndYT5OmTh0XGI2gkdgoKPlnSp6Fh2QsgtWPa+PiUr/2sajS eSfHdCLoiLtVs1cKMIE1qB7XSeSUuhCmEO8ChLrkmgzbUqaB6prVchCeSjiiBMXD7E8CIR60+cNr RVpQBjin77C+1jXn7qEp6dMDefITVHkxJElfivikwXtXVoRNLFAujbI8JZ5IWvY6G20gRs0hqSF9 09Zfct3AjdX1+bg3L6aOb+9NK2Va987AGKz97uT+2WL9W4SFegKO2rhVYSLT+gfftrr1eiiEH84E zcfIGdnrjeIGPxpyxxOUlYAyl6XuZ0tH8liEkIUsFqOUU0SO306YJ8Dr/DO5meSnzvzaU9GNx4XU atVSfq6z70QB8F92TkzEMXsdbyO8p3FMs7eUdMfV2Potgwnop5M9fiG6G/JMF2iqcCaeIJVFCDBV btoHC+6a8s9c7iF1igryazZgSTPiy5ERN1eI1W8Im18uyrkxLaL8hI10oD4RcBxJLXYy/9mdaURV V5RcRuOJATMEB/YkRqTRi8xfmx/nQ0jSSFkErkzuEhFI7SsfM+HC19GheL2KO6FRn6BCS5CTGQ0S H8no7O7Y477a0E3dO4+l9YJjpUUw+zur34MklNww166JrZTdoS2ErZ3oFgbvj7DvrF4xwew0Inpc pOIytQvxRbMx/42nnF2lDMEC1Jn1Qg0xg/MW3iEdNVDRygMBZ0mfPefoLBl/tg9Eg95DWXBpFvzK bAEdwQSPwQaeqYOJnR/o3IGpYre6Qa/4Jyt8//Zf7PDqkdE95DdtlsgkmLZVh+jh63JfnhHqiEb5 4k41h62siAtxs1QEA8u1EmBf5YMesNUHTE4JTCh+FyczBjCEPXQNEnqLDnEY39a+M/zalnc/OKlW gQ+T84cPFOHcQLqcmww8CPQuvpLl3/taMCCasONXpaA8R7c7WzGj6uJVkVPYMgTAfl3bKwV3jco5 Qsj0UByfQbFfBo7kyG0MtqlycL8UKiEmQ3XJBbD1IoTYXcap53q+Wn+EObFAARMGSENqsI2Ibw04 pzQm7Ho6LrS3MTonsKh40HVqoE0jYZm/xpP3ARhcMlS7XQB6yIn7v0yXUzdrK2D/kWgWwoU5mNYP 0q79WxMAYwGfzCRlsf8dn74WSEhL4l6e1lkiWf7lxqnK+R5l/OfJHfIt4F/ZlDSxejLeiloTLZRR ZTFsuZs1TftLKjXhiTRJw2ctFS/8WUas7FBYjLBhTg97Zdr2H4IxNHi1rjfBZCiN8V13yeD9ofEH kBRi19oXD0KkynYPm71RIlXy5lvXW+dWy1qKJtjnGrc6M3bCK8+3L/9CPXGklGkJCxhFQqagJByO aLwprCcr1Mm+RJRhZD5N0hlKlWR5TtXlFA3T5S/LOLNcbtJNNMm79vqPi7FPuU40i3ykxUVWhTSt Wv4sSGDBU7TT5he+x5TTn7LL39pr4RgT3HAPfkz+HlSe1UVjMb2WhhLu7az73yPrJfQ2ludFLJkT orf/Qo7Gygmof2+dP+ZEeeQg6jeGjg3kQA/Wre+rVlWVIjEfEgQ2z3g4adz46DhK2lk84jPpqvAo 2YlosgsNlEfopf7E7iAxyQPyfHJoe/+3erkzKvY/ssq6/vvTPjDuM8kKjRhrSbea4I5XY64RZKhm i5XOMIGXE6DaxibYOXwBL5FntBaI/Zs2qdz1kNFut0TEViYeqDc5Ovq78n6v5iawEdUFqmN5Q1cW eV/Oat5ho0RxBBk4FxRFwhJZNfbAGyCOrM/TibL72YYbzp6hMBFHV4zHO0/KvRoToBHs1R9/+AXI gJcXCCJf19ayuy4UrLmYtA3LNcUvU49jvk8EKxtG8igtiA4ZNLzcdvlzZPVLePworlrs7AudUHUJ qo5VpcmnMeQD3t0AgccH76qfdneuWld1Dgnv/IaOwuKtQLfcH75B20cZBf2iblfzit7WmOEgoMi1 2zTNacrLkPdeff621IBOz4CVPlvnQEqsZN4WOx14Px13/bOXkmnaRqQhje4U7GSDdHmmeU4F7RT2 nM2/4nVw4d3P7xwcPYbwvGA1b6dxZHOVW6X+W3SQbAGz55nJ64bM40fXxOD9hr8elVBqgY6prvvX ok+r/hpRBO07W+Z2JOK4w2K+rekN4xe5K0W2jrSmDt3qD99/7HX7t0wDgG1RREktM3Lcz2R95ycO CF2cdtzHB2Bq/M98xrtCvrBuRz8a4ZDxdbIgRm+JzoWrTXXB6IluO5v9CZkB6vLTXiDB2Y+/1qaD aKzc3TP5SfzkH7uLvRjg8DyOpTfuu5adYwyObmx8vgWOpS6IATP/3w0pa/uNnXbOVuSQ/iS0AbHd AIc58lF5CNPdBDVPh8Yo1xf7httfcZGO7iGySHtEKGxWtDiXyFbqUA2rxYMHIVHY5C3O0CQj7VGg VUX5DCD9FbJKjPRmuS8lVTZ1e+MBUwFtLvX2YZnE/KbD9ZtkD2N/6GhUPeXuiRir9UfdWOGcHxgx MmXmr53JYAq8syrQc6p3FhKgdrKocO3F2aXCZbJ0XRuDNvvfNG96l0JfvpFrMQ5Uto/uJBFpAB2c ezC3OV2zpweFCdHLC6OewXwcTOt17E+w9S7PNvwnlOm5snkt7SbntYKgmZmDdshkJmJdMyXI40Pi dWpOnYs0sw95aEKes6qdZitjVMMFwsfVwV42Z0YbQFk6n5hJMsWRWbLmuJbJX8Nf6CTsncEbMbSn x1AwoUVId/WWyVx6PrwmhiuKZSSvQ2eCCwsSoYZRsGjUXqAuhWssqcF2hkQF6fTjri/h4fbJR002 Hl45l0xeYG71+fh5ja5KDXpfk425s8rTWCAPFXNndqiQB0VTOy8iPR5eIPA97D61vZk+oBjeaeoB rcr/aAkHsmXoelOyJyHfrrCHoZEfMOsyv1V/H4FTnFOH7dRrHpXXwQ72Xaq6uDCDfAR4PUmFPB4O WL03JI+qFQh1C7ZABGG38IkGPuISi3EuhREl9VPL/0u6HIWRakeneB3i5o9ZmoWjAUCNq+7rHDNu MVewa4zJV36H6uKnr8WipgU+4y2Q0uj7woC3ICgGuMSG4coAscotMz3WbF+7bqMmc98BYyTtdK8G WdcxZdlujxo/ryx1lsP4zM1/6G59RlUnoatPawGYJciDcbPOaintg5yno1FKrqGo1bDzN1IPgvyJ QdoVLoainGWZfE4f/0UwnIT31QlsGOjbMuY+agZ3Pd17vP6OnI067ma90uIhnY5Yo1fChmRfdPHG puViEoVIs963S9FeNs3MpM7aNKi0OFcwVhtOoCUCM7qySNv8Lf4/wEvD4upb6x2Ti4v00CaQbqcm Pb0eomO6BO04b0rA4Igl1Bz+dkPQR3gsR7BUcAc9Ckxl9z46W3GHioHdXuaYx9eZfIaJk96cKtti FVkujXrA21Lf0lOW5K5byJuWdIMLDazNW6LsWqydrMb4iKK2hGe56XOHpNA7OXBOadARHR9Qh16N DwgYsxxiLqSEasV+w8KwronPVN4hBqd1sRpp72M+klbweZlYoXKzOijQvH63bdQ/+dNhC30SD+qB yqRN2PPSZXqOIX/DBZxIsfTXl4waxWMU3EUQer/dGh4EUOEvSfh1CpoVNn3XlVu+TcN0/gLu/nqH YuqgsP8GckBSYS1n6JUbEq6sIvm2Qd4LyorhpLYIVHvvOFn+lRrRuH1ozizOlqSWo8QUjwJQiARZ ktW88EV4I3CWVC6+CAOfG7DL418Mtr8eP2tEox9su0f6a6C56vdBCirBDGtc9ZyVxgNuxJUSrMDw CvM4htehadZ0YgwLAtS498RQwb5+NDnt0x0XhQy/k7CXLRRE7s3+YYlveaH1KVfVAxHIlHJwbHFd mc714NpAFKYuqKst9GHiNRn+siu987ZfY8MHv2mlogYIwwctNq8P/Z91NDleK0ViCUVUUo2Jn4XT qtMd2bpB8JdcyCf/qzL08jGJYomUPR3CukNxnGo7TNqgl1PcI2SG9m+N/UMjhyvGHcotDsw1Sm+J 1aEfMXOP8HewBUt+MumHQsS64WLcNkjs/mqtGJzhGGBOjocbnX7ZdfxO2f3Kjfp1jCbmNCIUSsXS PcIUpqSutw7gwkWjZI2dpaVHckyrEy/m6MjrdyTYO5UnSR+dxZhnJpG9VhV1Mm3vhytxyAqvZY6C WwBwzlOMRNPgnRU6bAF3VNxrSeSqLzDHtGk6uGwEYTCS+o02zarErWvvfxJ+Jsm30CDcmd2B8VEo FrfSbiAEG3EWvXK6dBwuYpWCcqXpEeVnV2cxGFS0X09mkbToB1esqu9tO/QYrhKGB9fFLlPLKKn3 CeIlitFtZPb2WmDxonVIHouLYthuAQLWh7T/hPx0+KUT/CQmBr+IpIomkUHRR85HtvhlszErTMZ3 dEB0fzsVoY2T7HCnIHAdS5Sa2oLhpdDeGDtl4KS5Pw/W745okMKaMWsPt4gmMkJBlT2bm8xq6Fnm bI5otqEUv0AkHjYQ+mpRAwMglk5l2kvDkSGYgug+nKza0iNl0XGAIinkaHBYEQrVFuzANnj6zA2P ozE1aAxWkVXkHXsANMTRh6tivseOE9bJa0UkF4xXY/LGb3NfszyyejiKHwQyVX9PFLLpghVYG9xO /sByX+Fru/6hvOj4nEYSpjSXPUUV4mY+YB9hFbQwOy+9or396/x7yv9t5j03o/jhpYTGu2rjgQQT FVfOXetxp9hSnlJDNqVNIme9obAucuclKNgP `protect end_protected	bsd-2-clause	7e41f6fb813e7fece779f90556f09ffa	0.926974	1.892029	false	false	false	false
Yarr/Yarr-fw	rtl/common/wb_addr_decoder.vhd	2	8,328	-------------------------------------------------------------------------------- -- -- -- CERN BE-CO-HT GN4124 core for PCIe FMC carrier -- -- http://www.ohwr.org/projects/gn4124-core -- -------------------------------------------------------------------------------- -- -- unit name: wishbone address decoder -- -- author: Matthieu Cattin ([email protected]) -- -- date: 02-08-2011 -- -- version: 0.1 -- -- description: Provides a simple wishbone address decoder. -- Splits the memory windows into equal parts. -- -- dependencies: -- -------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE -------------------------------------------------------------------------------- -- This source file is free software; you can redistribute it and/or modify it -- under the terms of the GNU Lesser General Public License as published by the -- Free Software Foundation; either version 2.1 of the License, or (at your -- option) any later version. This source is distributed in the hope that it -- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty -- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -- See the GNU Lesser General Public License for more details. You should have -- received a copy of the GNU Lesser General Public License along with this -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html -------------------------------------------------------------------------------- -- last changes: -------------------------------------------------------------------------------- -- TODO: -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.gn4124_core_pkg.all; entity wb_addr_decoder is generic ( g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address) g_WB_SLAVES_NB : integer := 2 ); port ( --------------------------------------------------------- -- GN4124 core clock and reset clk_i : in std_logic; rst_n_i : in std_logic; --------------------------------------------------------- -- wishbone master interface wbm_adr_i : in std_logic_vector(31 downto 0); -- Address wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select wbm_stb_i : in std_logic; -- Strobe wbm_we_i : in std_logic; -- Write wbm_cyc_i : in std_logic; -- Cycle wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in wbm_ack_o : out std_logic; -- Acknowledge wbm_stall_o : out std_logic; -- Stall --------------------------------------------------------- -- wishbone slaves interface wb_adr_o : out std_logic_vector(31 downto 0); -- Address wb_dat_o : out std_logic_vector(31 downto 0); -- Data out wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select wb_stb_o : out std_logic; -- Strobe wb_we_o : out std_logic; -- Write wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle wb_dat_i : in std_logic_vector((32g_WB_SLAVES_NB)-1 downto 0); -- Data in wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall ); end wb_addr_decoder; architecture behaviour of wb_addr_decoder is ----------------------------------------------------------------------------- -- Constants declaration ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Signals declaration ----------------------------------------------------------------------------- -- Wishbone signal s_wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0); signal wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0); signal s_wb_periph_select : std_logic_vector((2s_wb_periph_addr'length)-1 downto 0); signal s_wb_ack_muxed : std_logic; signal wb_ack_t : std_logic; signal s_wb_dat_i_muxed : std_logic_vector(31 downto 0); signal s_wb_cyc_demuxed : std_logic_vector(g_WB_SLAVES_NB-1 downto 0); signal wb_adr_t : std_logic_vector(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); begin ------------------------------------------------------------------------------ -- Wishbone master address decoding ------------------------------------------------------------------------------ -- Take the first N bits of the address to select the active wb peripheral -- g_WINDOW_SIZE represents 32-bit word address window s_wb_periph_addr <= wbm_adr_i(g_WINDOW_SIZE-1 downto g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)); ----------------------------------------------------------------------------- -- One-hot decode function, s_wb_periph_select <= onehot_decode(s_wb_periph_addr); ----------------------------------------------------------------------------- onehot_decode : process(s_wb_periph_addr) variable v_onehot : std_logic_vector((2s_wb_periph_addr'length)-1 downto 0); variable v_index : integer range 0 to (2s_wb_periph_addr'length)-1; begin v_onehot := (others => '0'); v_index := 0; for i in s_wb_periph_addr'range loop if (s_wb_periph_addr(i) = '1') then v_index := 2v_index+1; else v_index := 2v_index; end if; end loop; v_onehot(v_index) := '1'; s_wb_periph_select <= v_onehot; end process onehot_decode; -- Register multiplexed ack and data + periph address p_wb_in_regs : process (clk_i, rst_n_i) begin if (rst_n_i = c_RST_ACTIVE) then wb_periph_addr <= (others => '0'); wbm_dat_o <= (others => '0'); wb_ack_t <= '0'; elsif rising_edge(clk_i) then wb_periph_addr <= s_wb_periph_addr; wbm_dat_o <= s_wb_dat_i_muxed; wb_ack_t <= s_wb_ack_muxed; end if; end process p_wb_in_regs; wbm_ack_o <= wb_ack_t; -- Select ack line of the active peripheral p_ack_mux : process (wb_ack_i, wb_periph_addr) begin if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then s_wb_ack_muxed <= wb_ack_i(to_integer(unsigned(wb_periph_addr))); else s_wb_ack_muxed <= '0'; end if; end process p_ack_mux; -- Select stall line of the active peripheral p_stall_mux : process (wb_stall_i, s_wb_periph_addr) begin if (to_integer(unsigned(s_wb_periph_addr)) < g_WB_SLAVES_NB) then wbm_stall_o <= wb_stall_i(to_integer(unsigned(s_wb_periph_addr))); else wbm_stall_o <= '0'; end if; end process p_stall_mux; -- Select input data of the active peripheral p_din_mux : process (wb_dat_i, wb_periph_addr) begin if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then s_wb_dat_i_muxed <= wb_dat_i(31+(32to_integer(unsigned(wb_periph_addr))) downto 32*to_integer(unsigned(wb_periph_addr))); else s_wb_dat_i_muxed <= (others => 'X'); end if; end process p_din_mux; -- Assert the cyc line of the selected peripheral gen_cyc_demux : for i in 0 to g_WB_SLAVES_NB-1 generate s_wb_cyc_demuxed(i) <= wbm_cyc_i and s_wb_periph_select(i) and not(wb_ack_t); end generate gen_cyc_demux; -- Slaves wishbone bus outputs wb_dat_o <= wbm_dat_i; wb_stb_o <= wbm_stb_i; wb_we_o <= wbm_we_i; wb_sel_o <= wbm_sel_i; wb_cyc_o <= s_wb_cyc_demuxed; -- extend address bus to 32-bit wb_adr_t <= wbm_adr_i(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); wb_adr_o(wb_adr_t'left downto 0) <= wb_adr_t; wb_adr_o(31 downto wb_adr_t'left+1) <= (others => '0'); end behaviour;	gpl-3.0	6d8cc41d9ab7d8e18ecbe510ee9fa16b	0.496398	3.753042	false	false	false	false
cwilkens/ecen4024-microphone-array	microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/addsub.vhd	1	16,419	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block iyLMoRkq8KweSXb/OmiUfaqOAj6jbJITEqxvBgE/jUzhW0RCfnvOo36gHBUdDtFnAKoyFuUHiy69 fx82Km1Tzg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block J1bTW+xuCgfsRF1zdVwqPHCrDAty0YhqrEZfeGbg/VwnvDcdoMSVUaz8upv0EKwQF+L4EwMcjEv9 dhR5feonU3gMHZnaO3/Ro1symRiTC37GwMaOrLUp4EjxiFUlfzIBqxxPRh0gu62P8KuR9kHOh0Yp t7+rGXHegImBEcBcdqE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hPPna73xF0f7y6Na91ioJYvNx3mAq+WSNuaYsFgnW8gpumRZGNJbyCNkhOilWBBRjSOvhVoxOZy3 GYqqGJ/5965xWrDLg0WfVKbk/TfzPJ8gr/e7J9zZEzNg54RgcobugAO+DGibLEFEfhfLAOFXpv/2 6c5sDKIp/+jacJmmZveCaP1X1oglH8Af+A7YOqAIom2hm0aTFIqF0czwBOaJ8/LolISU4jSIxTYL vwJJcY7WMjapXoQ04wmL93IIT8mR6z+UiQ1I5grNaZdUJyN6eAY0L6iW9wQhVe4H+sAt9BF/Wb9d ELxi9DpxjOvggchMMjYBnGpeIyztdOxRv61DTA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 0OVcAsV3fB9hQUJQXo9MT0XNI5xANhjWjnB/R9VKfA3sxb1BrWn7m9vnlpo9NVYiFuAdjbPa0+M0 3um9dLE2RiiQ2Mvvd0AMA7vBaVGeiKGMpxF/ks68FaEesusfTiAicS+9j9+GzzUD9FUoDyKNJFZx MIkpqTAsNhZKcdM/xTI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Gr2odoPMguGX+M0fLWWZNn5Tbb+TxZGInwpa2GGPXnVUaV9L9zuahuvXmZugRjm+XCrwWfyNLOj0 HDggLbt7bmF8+cORvJcmwsRrrNJfkuDr2k5H0xw7n2hKiZ/ZSXnTGEuDvmHbE2Cqr0JAsSoIqNqa hvVgEvtjD+lL6Avz38NkdwSx/k1d5AKfc6lF1hpTDR6NBDW+Fpvmqql9bVAWQbBKF2+7bCgcCCuM wHpENYW8SzPvg6pH5W1nyKp0k+bPOpr5ntSc9zGlrTgVS10MQb9UUjHZy7hZBiDAj2zdfjO7YlaT t+Qg2f24z1V8gkJwAN/4dAzQQXS8k+YGnxFD9w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10416) `protect data_block flaJS0+sE2jUtvWfB86YlOMP5tXkpL9xuV+/3VGgNg+WiS/EZCPmSwF8GnsWcdKJpnNXmXEbJC8w CSkrr/F9ZyCU1DcdiZfFRTQxC79JRlH6b9KtICE5r0h7nOVN2XthikB3CQ9nMluWGzVXvw2O/+FS bwtuvBfWtZJepYeypkUUY0lQyDJYwAmcoVQx+pIaodfCjtfpYdgUccfW7R7zh/XdfBpJbtV36pyy cOAGohsEb2NwMGK8u9lt7ELIfJ9gDWEMgXyoH1jQ2DM2xVWGgSFh6WoQO9aQB9zxAwfXCf2QKs6t d9uUQEefCLdNWPBuxER5DWwItjFPOr23yjbY00jJQ+tKxK4MAEawaxRasxNVDOB8BO8+c5nU7psh mHmu/B+2COg+2sGeiNdSsoqxrllNOhUda7pnaTvF1ZhAzOhAwFv9WiVd1u8khA2Ea2agPyezqoEj /wigvm5qbld8gvifz+8RIIDvx0z46Zs8W/uBvFMciO9+X88sSzi7KEzNgSD6SyrAJGZ1gqaolloD 3be9GODQFNNDofu1zBfAQJaGV3tfkiOPe/oWHjwzyCBcNMcKrwCQ+IAbVrhapMLwvz3Z9dEr4Zqo 8G3z9k/b75vRqjY902k3/HInbMlRT7pZzkY1RQ4WPPJDcwaRTJcKBq3e+9xuJUH6uJbo9F8wmSy6 dvWJhTKGB6RBThkeg7v3hZNS8KSzwx1CoCChP/4sBLwnSagGa4ThDY7N2f7+AfqPQcgWObLEP3GA c1vpVSaFmcNcLJPfOXaf1dQyeL8G5EO6kuhCCoBGHG59kyV0VssGrXJKBwSxbvQKJVK1kpCJyGy5 zHS/UqIIwyu1h3CeVxz7Ql1qp4kOR572KroiRg0FRTtvpjKSRrh10PJvKsZyjE1zzOdlZVVJ+1+x OsHgdcQKIVn7nSORF/NgCqMr4T/hvdxTXbSBE11ztfLVvA5kfcNmpotVRKCEJqINhagGSHL5s6u3 ebE6GFPtypqE8t7HWaeBH1I01fokfD2FEetYQy9EqKYMNEkZNJGw4sj8F0kh0hPTM/BmXjk8vVs7 CWX7/f6mhw2thb1K3l2s+LNrUj7BeZ95cyP3l4tARXlFkjhRkryz58236PDNRAAHYC+dgbSTBRyf Bu2X9GAirTxiU8k+6Cz73u89/C2iyPRy9uTQURk2jWQXGucsrZLjMqiWXlA02Rexh9qDfbxCmCpo vDV76y3s6WrdDzZIAxjHXdqtHWLGAw/nXyH9ls50m0nO8bVn57glHszA+JFzJc9m2ZCjUnikzVFJ en1S3BIGOyIwvhVg0OvfvlC/T4W6lbys6RcNzZZCJZBIKL0F8X89uYjfV0Kdw4N1RLhafpAN/tuq s2oNhfUTiyDz7sX4CZlMKp8dz/ycCBJU3ZVhnv7Zp4x4LZFPvSbaCvMsoEt5FlBLghPS7asEj/bV FEM5Ky1A9/iqrGbdCfYm53TX4pk/yf7EtGQiOBnqxhLIm3yhrzW2R+VExkLt3zxw4ScnGidfaciG 1LV7T+xBEwIbt3Ie4vgeOgjUQkLofj51HjMuexIvhDPn3mzbs2cUuS8ZmDo2CrAkij4pjLHpXCL2 kCIyhDiqAyxqyIHquVN9PWPGUZ6q3C7v0nY4mHXGpOT/hnl82ZXE6YU78acfWe/FVLsEmFLBIXaQ KF7LiLzEWqhsOBkP6qUF/yXxUZnQtV7dDkfcEh45alARusBRroQN6mxruUTe/OVdB+qMMjZSc0yL VTbLEPiWkya5tdDKXUSdGv6jWIrZyjZxnNq07cLxVEqZ5fSq5dYm+sEb+psC0zWFiDkg6s+KXPvi Eu6T7iNB8FWF2kIw1dLRUobZIr7uB04+QeUECT5eqV7dV4Dk/bIahAwrvauqXk7On3T5P+Z3qKQW 2uwLtIIvpk8JRoQSF8JbQ8xLeN/7lhkzxNcyi5rGaVwYcnSZ1B/GZzaGqCoKRUBRZDQSRAhHLQUA /4NUSPxtm/WrN7RZlWYG1vGVErtTJOYXPSkrg2kCHiKehpflzNTIRaSQe5pcqY1mBmZQRIhAy3Mn fkNVKB/JWQYD7MKHJLmIKqGtjbLzNBVWA0hwghRLLOIfYPJv9iPkejdLAq2zlVbz2RE9lhguJmHp sYUiD6esDWGwQz1/PfMjoQBJOk9osn49rm2fTfmA6lgYYf4a4NS99XB1vc5PF6kxRkOqvJ4PnsW1 uivACoGxbQewzR02+p2MelxLJ1Ddd7Z/olZ8+Fsoy60Q2vkvO3zTpgh0sk4AG/HCwiFaP5dcXE+G 5P8lXWx2jxilY652YEXbmIrSbBEwTLK3LDq+ELmzKAu218V0c+ZFYckls2NW13blMx27gQJpmQaJ SMDr/rOIAO9MJXt9v9itgWHfNp7WV1uvXbFYnhTY3UUxRQe4SL9kLC3UmcB71VPz8VcCbTWg2eC7 HCokG1qY24PfyZbx+LHaJ8GZzLqlOyTBSh3kE9g/ObJk85pyrk3nywKrh92LoI8lTtJZDhUl0Yvb yGT15yEr9saCvQYVb1duqglFnxCuJ0dM8JxJHhnAzHW+8i0Mw/zgMg1i0A+xokiImwfXXuf/V1VU KqPizrK2+GlLU7HutoIVFt2LaWttjZnx6vO2IU5bFUaGn8/bzH8VJZp3L9ySmeppWe5eQTJo3mSP IVQ8nsLbQbylqXJrezYnEkTzzFefjOzaKDhwXHkKh0SxLnn1JvGKu81thLatJR1BskJm9GSUco6s ZX8/RNC7N+TimvnC5Cuh86kqT6gh8BJBxbvxHfKPPMmBfCT9hS818ydLQLKuJWJ9hlmnpUOnRjYJ 4UbqB81qs/UJxkhZ41vdweHC+VUsUqEgn26J2NNp+D3m6pUfqes4l8FMtuqJm0tMMimMhOBbrr46 anKW9KjxqHHi+insjWSJVLPRrmOeZ4hxSYVCoMO0lqQneJzhVYkW+1T+mHBtvU5ZQdyjpiiXPgwD tzdz1+7m2DVtRT4ru4k28t05oPxawdPsCRSWAvahABCA7kRK/+Yf9wNEhg79CchJQYsDZwCLOAJh 8b8odvnAPATf4DXioRLOQIYUI7qtdcForKIXHcOaUYMq+ZqTmKRzxKKGRrI87rVZBGO7xGc9juZX v5RpritIjWkXiVXY2lBMIEAvG27h4yI2xKvF72QPaI5j+D1Ilfc7u0YUp0LUj1yFixRsDY97CxLA ah5hHWiMOjE1wrh7qbmb6A24OhF4PXSvN9UlZ/FYADZL6SjqS99VOcgTU0cX8E++CwZ3vmKVWjRK i+vqGItcYjvDGJmafoEswmITu5u1ZfNUwM822WmFMyPS+e3hRNi4E02HCR6nhmc7qESewBkcy7cw /D1WaT5Dp3Ug2knxcvqJxdSZFhCZ1yUX9R4yAHMRHaA+Mx1vBwb7cTCz+YQ/SQkYO9PQ1axE6wIx /Dank2kjRLioalbsnfoWYBe31paRPW3EHu6ShrxwPXUVP8vFuUcvAoMuhfs6ZiDo7q5PQEjbP0zS 1tLaNS/XEcDpV//hFRXiRfr6e6L5P8RxYRlZ0rgxFu3MkHOjcF2OYgvMe9W+UVW2ESt3M7LVD4MU HX+U/vPp77fmJe2xNWoAmgEI0Sfw/e1lSd31z6Rip7AIo6tN7SMO9zrVnWzQ1pIMw5UxnTwNDJMP JKhiMobu9NEWARnEDMThCH62gm2qM4mSuCvcOGrsUc/k5N5FA7Xo9qgcc85EC3CQgz8QLOilqSAn /Foz+DsLl8DX2avRXIMoWE0YXig+/45cXHeHGdArwxskzW8gE/0qs4dcrZkK0njAJ5CSdMlfrzjA R4yV4vxkcG19BFo/VjHAQqi5wAnN18sbv4hOMfnM01le7s0FGIG+b2pU+h4WnOXjidT5GeV8F6IP fLFwm9r4D6xI5Hz5TcfMr/Lu4z2swXgMZMHvgPjId0Intjje2LJ8GsNiR3j2whsN50gfyvm50gWR PZ7MWP6ZxeDxeHYM91u43m5mQl6QK7qca4BzJR6VgFl05m5l+BNxYVetM4zvahDYv+q4gGkbCUte NJCUws3VdEMaSlbBDqixmdTDYXNFYSqR4Ud85k8HholBITXwZm5dEE6gkq7HevPyD8xLQk8j7V8H Xi6pFD4++jVzqNVmMFGdVCTcD5Z3pXin7/uVOnFYNkgNn1BeFhKf/1Fa9OIWactdUrz1AqB9jpx1 WtwTeedVjGPKUDLpW87X1opZ/ldlQVSMN9AJM7X4qFKCBib1tUeTC9oyu3w9rDYZJ6wdMc13RUFU bbjh2TnPeFZRRYtCH/bQt+UQ59mBYluYx/GdcX+Dr3nWP0gT+nYD2PCyIukMIe4ms4Lr1QRTqn9W Qy3oT04ANEcdA+X2+PmFn6xvzIOE2MeoiGB9EFyuu9Yu9w4Zf4dU0p9hb3+kPzKllkv/YjrP/Uc8 PHH2bnvpfC2OLNPfOsDg7ZjGingXYbwj6eu8S3okqFsCs9vsy1n6HEZj/rmiaCHIJLD7U6Jj4NZP EQzmXk1raeaMYUp9GcDuogB6Wbz07vIm1Vd1pCwdxHSwH8p7PC7fywvVQm4xvge/5Hx9uYChsTRA wZtM9ZluoXnVCfhdUoYXlp5tjP+0AXvZrypmy8XDYkOzIWGH9md+IXEX1p4HloVdrpFXXbRfuNbO xd/3d7yTzXKlRbay7VVAG0M39KyuBlvDL5whn2jQlGJnmKEgXV6tevCNhA1T1D4cZ8kIG47hHhZw GxcGiKT0eMa8r0oiiZGQ0gGFQeW0+lEkvDPYc5aYnKBin8DQtgbgmY5Cq9IFcroFFXS2CKUioi/N QTZK3OWkiiim06d8Ll20hBlATge4m8CsDB/hvhbvEv6NBdIXZdSqhXvDT2pJ8S8eXwTsIW3j8Nry ya2NYEX8uSiR2OoEw2ZfuKtvWB7lQAnC+oKZ58ppjQhWne/bVqtjyLULqN2pBrVHAVoJFvKaQP/A we7wOxqlzi+ZaxSmgpSCAFMju+8+Tcp28dXpiK/GnA4EvbK+SgXhc5779lkH+WFdjAeVQhOj7H04 SGBDZMsG+T8naeeErJ0/88Jg4Krhg0qsXvxk8YFy4j9ePx/sF//d9rr4HjkbZdrsERUVII+XTylp PctvyN5FCQjNWnWgkdjIbLBJzu0Aag8ybI/jrLGYR3qJNwKuPYid+v947pepGv741StOa+e8YcNS OheUrAiRtc5OES61wFTWmnwIdCjxWfObpIYDND2SIiWiqwUM6TlhUpmlPndr1q4ZXxZOS1n3qXnq ftjvs5k1bSvM3iOdquq9M27ORqAoQyY6NKlayxX3cDisYaB/0Qq+H2W1mNPPVY5hFCQFzlW5fLVZ Voz0yGJBHSFIcb8YqRXuMTYul5S0XZ+3NE/nmwR/sc5gFiMKxRhNioHTpgod0k7XQk/Mtw5Tzu/0 41/93Oz//YsIf00hy1g6F+67RLa5f52TxAHTzq9F3rvfFq8i9i2a1QU1k7i2DpQMltfGM6OnytFA I9y9yL4rPUSIc3WC7hQ6XanZmnyoj8j7gnNrMnaZfq1LtNy7Ybxu3P8m2gck9/SD/trxdeOphrWu S1li/Yx684p1DiJcZO5ep/scrlgVb6lc2BDfxGWP+OPmipF9fjKBYD4XrvwERV95K8FDhdiWrICf DGQBN0STRgE/4s3KNNoXd1LZWaKZoUVcMDLbs9m51BYExEy+w1uvZcS9itVkEkJVPXNP7SvVTX4J AgSJa7JJk+3C5IPpDvlIIW0j+18JI0mNI3UrZ4FWs2sxEjbUifXxAniCci+tbMTQeovB+BLan2NF Dm2aFQNPe1c6lRvHNON2xUYW+K4ZEokTKZJhXCGxRxXUWRkRYTNw1NCEPbph/7D4uyeFS24lxcaW YTseniBRJXDUEOt/C6MJUBkSLWxrXJHpvAkx6o8Ls6RPuxQIzKDjkcn2iLgpktGEplam7qPT6xlr DwGEG2uGVnwWTJCEgjp1Vr3JHUXQ6eUNu6++P53W3iG42b4u9s/6sNOdQrWLY0rBjFfY6XNrSFFs /RE8p55lg9nXbfN2IzjV1N8BtPz7yo77SQ24JQ2EETLWGvHxlPM+3N0g87XqcLNVhL/jpkc4Wiqk GNbkC7MmCU7pgncGj3SCcDe3BOAZDwpwkRRTVEjrYFpNwyxm5C4QE/Amjqji5GHlAqu86Wu7PafR RFMREU5eoV7OH5xy9trowAZ3L2mS+J3N+YLFvHq5umzhil1kF+NJGecNM8pNrYAwz0SE9JWgSPhV rAHAJ22mDOrOpDqSGWR5tfRXxdz5CTl7dcxRssvBmx/ppX9SWQKh4D/uFxrpQJIL14SUAB2K1wti f2jORQdxconFo2SD0N40KvThKZfb13u/yb0yPViGPVguWBc/FsXCV0UNoyJ9YDvhhDyWgQdMzny3 fP6HfEaaLogCW0cMvz/PT3SP5VjNHY72k0ZEbZFDNJqm98H95koZwLy6AoawnK0lQCWtgjcEDZUu Bfo2+GpRN0wQSNC1jfxXMeP3lMKJjg46Hrq9jX6TVH14iaLfq95/n9Mx7SdV5nByUQtVURBZJ410 Fb5DPK+KxvHwhVpl8qJege6tCaR3hkvpvPiOPjks4a5TegsUEa7umYto+GxiI2wTptkmI8aKFDIj nk5u9YzMrVsZGSBrXg2qqxlc1VbBor7WrPvQpM/8e3LxwYp6sB8JPXcLhVHBJTQkLdD4adWxIl4D COs+tKE6SNf2CNRXELO5yiwm1JGNR7cGGlFzCqAHfHnvPpc998QMKtz/jwkebHk3qtG9wvVSKOPg V3ZxPBYTpyX0lYulNTwLduU7bLzwi5sO55927mFigJ7tT1PgO6585Jq0xlVCMGy4KuRoOeXOhNDK 6KS7jTLsC00F6/lY8TAqCv9GhB9YSSuOuN9q6YmSHylTksJMePnOtKNIsq/Ut7USb2mWErkzgsOA JNjq++XOWjPu4jHhBAko2FogmFRxmvYQPDITykw3Gp2ZVWGuJAcYkYczzIfIAzP9WPO2sDoG9S/r w079I2WBuIWUuCn5LAqD0X80qEA7vlzPr4OPqEyPGdzUsKDWku1a9iiy1/mHdfWP+Qp/E53/zkYG xh1GG/KdoHXHoH9/UP/9CeOpsw4b6cj59XhUQFrD1MUkXiXzC2NhhIuvm8R9OiXmlCf+CoF1hCGP VZ9BvgYLqv+zz2yaUkXL9pXOx74RJ65ED0c2OiojGhMZbBP1vsRoNPQ+TH4leAu+uqLVZi9JyCc3 86jzH6iRCC9cnR0WByl8P79JlpgEJkMLfjPIUM3DTWVvNCzuIzlLqSjsEk1juMViWSAQR/gWiSQd 8SJWj3tH7DZLCodvIKdVgIqhuk9XIoDkMBRTk7nkWoi8nbnFRNZrs5q6fMdtnRGO552oVtwrO0LA FFbb6kmZMHdNoIFq5abdLfPmLTGWpaTJk2dl7oKIILZo/DNnYvUZX05V1vC1soAc5I1k6Pz9b8ES /m9wmRI+1ZLhFSCFhbVrMge4ZsITcQf2SlwCnZWWlzb7esuJT6Wem5mtnN6ZLz2vFIMwk0Kfp7yi 7PdYF7068yxo3H2fFhqIOYU8ujuxBIey0ErZofOxEYVhjGBOY9laR0cRtj9dkNKZ3oSgABM96ihW BBwdRg/0V1GKNfgvhlcfyzOYnpwolhgyFFxV8I/QjzaqT7xYKMor+kXACRl2ioRObSlvLi73JdK5 f3N/VAeXIFzO80BbYROeyEcp4TANCk8B05dDxv9aZOs7qwENT041uf2Ijb/cEojgNL846YjRx1RZ DIEJCAJdmvaietCGuOzGEjom8mQpUvs40pWfj/rJ3aLjuV9Anvu8CO6gDi8jbnbGVeTguJLF4w6x aUR/rezRxpUuB7tNDKYrR+bufhDvrxt7kgEs2M1oLTLY22w+1lb+vQKMNsqhSRfvL/vloH+ExjLN dVsQaIFBu4aiYZjZPAnuy3wXC/WksHbe/vYxDERYWVYIflE7aAFQw1N5rTxSJm7jSo1vnhTn1VZH +zq7jNpkxn+otIEwfSw5OHl8J8SqgnPs2AtlI/qJGdVXVyhD/WJkKC9qNIuM6qHq8daJ25tlU1dK ufEGjkQ3cxi3yHsV+DdhmWbdy01ewlZ9D4O3bKGdl6M5Jb2iIcTQ7oX8rERiLVZff2dvA692JfM/ DSrA8ihQF7iHhIM3gIiiR6zl8WREjbdODB7AJu+ZbkdayxbZs8f3tFC1lcNMm0xsueh+GqVd3Q/d 8ZToBX8epz/LkLh90sdhzTjhdrf4KKhkVjGar0ZlDY+k0O+EliIN+JCrd54DKVOnF89vjWs++d0n +qCQQJBYxviTbus7MyEi2QzSNrqcTPs/82aGe1Dhis3FDzbBuKDm7u9rZ+JWHzwAiSVxFuzbm3Br RFDvV7iXjUSNsI/1+gAPaiG5NNp2UJbhLny8cxpJdhrPMO57pKZSnPTeoDC7Euhjiag8yVw322UM MVVJaSZGSY0n2XOr6DMiIMR43DlovTmG8iFNFNqrYg+JUPpUVkt9E89CAoyPKngjS5wlhp4NY2Vc in8dvvcnN9vD1I7KSjxglHrSK88FDYQB5c/xIBf6XuE2ApykEkKroLgmnqTIyUjXm4wn8dmZiaX0 2ggiPDj7WTUweFgY64M7+dS+vAdQip014z+R2gi7HrHbx0F28iFrvZbEhdjjmT3+kdOj0aswYnse dm3O1FHmat4m6cry6er4mWGA95qbPAz9KDE/FmWd9ES1q4JbxjCRfvvOf1SmcTWrTdkeA7xm4uUD rZMVtRyTanQ6/NjnNz8Hahaiz1lbIZm8nWKwAWuQciQ6DqdrAIOVtgwmhLLrhAurLogxhgFN/rYC fk833QxLbDelETBOgdelIGSeVpeNvoBBrQbdDn0K7SHsEyBWYpx2+Kq7qg/X2KcBNGCyBfqe6R8s m4Ik0QP5f++hfIJLhDpq4u1k4dyrBTXVRz/dPbE8k/ZLkz+MM0xkbLIGzva5Ckys5beivV9tDatu lH9BAZPfX7Z8EuhrMfmfXIRiV0MTV0HPtBViVPwHKyJAxWZvLDFfRRBwgpV19saWCDs7NEVZglcp kBP3za6R+YYanMNrIDi19h2Af+Xp0OsvqEDG9IdQuZQRoS7Ot608i97MnOrlkR6ATiJLNvmaUgks 42Imjbe2QNaP4VsnwWHtXAZ/x2WfB8L5r/R5jqdZw5JNPoRvnsiFUiC+pPg7YQ3HQPJOgFlQYbfn aynFd7VCq8mJwHDD2qipQfZLybwz8VzDD/n+lKWctiVXzdnYnxwKZelH7MCkOWDfY5A9xQecBkXA xHn7vczfRA/TIswBnK4R8r2pcChFcvrJkhD9rSryQo/wOPwWrxmGuHnfAzKDBj7mnQh6KzKfYY6x 2425fSFKJJ7dgDmBFWvbIiwEOP1fR/LxwTmr099opAguAJCzxfs8a6PUxCp0rURnfdQEeFnwkkKM NYPjqUitW5Blu+bKzQiow762sBEoEL/U6wuos/v9vjpptyMQdKM/LfEepc1YSrdysEHjxClMwAjm 85gaT+NgILoKLGwj/stCjzVupc0PsKfiJqMKYTCnoWXzaIpy9eeeUFSlLOO9gOWlECEEAqClXwaP iyvBMmXMoqMUFIEw9u1s9xUhLghaHZwWPaOEzyv3/ontub/uAqJvp3//EHJ/Cnmrh0JaVLRVUz95 9/YkyMdggrwuS8f7ySthgMiUbWVdbKy2FtxsJl8a28Dmlg0U7e4qi5v9/0UiC7vclZ6d0zyMGMjU UviRV7Ut6A3CF431Ur8rjQCh45li+j2Z9cubWQ7jC43zVkQBZG2clFR4kjkdlozEGNGAH8mNLFQs xMx45QU5BHZ1ehkuHK3ao2mvQCay8btC6GjtyJQqONGNBkkWsBNQazL5zJhm2rX6aR8AJB73vs2y 7C12PaMgnJyIpH/4PgRcgYihKz7LdFmpXusuh9rS2Ee7htJwMZd0xSmJ9gvbvtx2fD+iIm+xtq+S BCvFpOu+L4hqvb/ye0SIamsUjf4ZFsGU0ZUCIbbbEuJe2kBW7exp7MbQyNdQ20GBs0QcfMtN893y 4fracR/0CmShi/lBRKlbOiVN0VQVdORab1WTg6Z8RMg35upjutiuWemTGn5JQ8pQt74TOPlub8uN mTWgr4fk84iiq3XFaG8Qzv1jH/Yo8wUQGhXHKTWMCW7sPwhrzgnvU1bgQ0ojeP1/eCLZnWUwKb3+ 2k46fjg2pRZRRict7hVdIL+pfwBdlBfB9TiwKeeT2rXUcoEYAFIjYzhGmeWZGg37mc6IS+3DEaDw 8JBP0YJiR9dMCw1e2LFA9GsJJBYw4xW7qIWIXtTlzxmkL2fBXZpmMVrZV1cAGv+r6khZwM6e1BAQ UtvlR94tbWG3TYTlIhgrsUZtN3F6mj+x2GRR/zKGY4sGFJCQQJQjP5CoORbZdk7zKDYuyHRkSiu5 v9MU6FVaGsGywLq9accuQjP3LjG53GbZfWlvV3f/8hVMhQcFUj8WmOpymzZfDyQU2VoDfOw8ju71 qFjdAgpyslDc+8iaE/oDV4zd55ceCsymJEAtDZUWx42MKY5STuG1mt6eS40MnpBIbe/4tkj9JNLO qBU4nKN2Pm5oPYAPvjqKwSSjpT66FS4IXsZKTIE9/vM+y2NfIu90VBD6cWmHMH20ZRRaGpHaEmFB 1xNEk2ihOONvGK0sieOZmDVLd4Jir9x3085ksA86bGVF1W2jOgsBbfRYdvO8btctdqx24qsOS3fi S665KslAY+rdl9nACLoWSpz5cBvu0mQzvH++CUkajQYG01lmkuxNcMhI4z6OY1bI5FeDXAUtGY31 8UCeojQ90ekV4Hxd3ggic1pXo90upI/Kg3NY/Jssg6rCcQTMThJ55Lfo/x4NShgASH9jDiNTbG32 2U5P9X6/dTcvdsOT1rBeKchbMgxHpYa+xqLk4ZYTqN0oPT7XCc9yEocVhB6Sw16cMA0JGTzwFAxu 43AnE/tuW/j2IvnIk0ZLlWXWJT6F062q9u5gTgO18itZIQGdofF8/k/MbiD9uRH46tBc8EjgW3Nl W93smxHZO288VUCn4wZ8Hs+4CdVyZ9P5v94kr7pO4+rUPLSbhL+D2yj6FEfXZOgaP7Vxh8a7VtJl dAk5Sxbm9D9eGTLqM1Tgga/dmGXBpDEjK214QP7uyXqM/jSA2sepaXRMdIRSru5Kjm3VDE6zHugD 7Bk6LdPLjarzHscmi0YIpghyrzgsaEVXd9nBgUp+Qb/2Ht/9HOSCoI116nPp4PenHIHOcBN/C47W xJioMj4yyI0FzTAXmj8UhZxVNmevBEc7aqgR0aUwcKRQN0TYNRpgdEaMThB2Dw0Z7yo2RcZ5Bh3n OUw7ch8PraMuzcPSLcInusmjCJTLXYAL8g1OklfiCs1XGPpQ2BlXGFifm1hfW5NDrtzpMb8fmkqw TtOCapIcbwLvtcpPCFrTWB8UmK/7ccRrrf0ftypCMzHrnA7OvzKGRI0s5G6TRwPm3P/LbG7VXz5n hlW9sAyIXuVw+ratBmycv0J8aR5AaasqG1OH6U+4oDUYQupkWYItzjo1fF5kzfogOyZfJMpYL37D oXBdoJqTkQWGf6EIdvucz7Oxfrf3KhxGdR1vJtlLGsN8FiA3GpSDM5KBfpmmje1PrBiJPHI9lweO GmjydKHW9Xy0Djib6lJlWldwz5q3ag0XPM1VkdcA4EkogLkPjpZjvDr8A5bvqwNIfG8KJ19pMk/F rgeFSdArd5+Mj6Id2rAXmRKaT2m3N9gTGJmBtB5dpT4/umLb1snQQBXX2fbxx0JR9iU55B1b+90z 7atOUugPjKHTwL4UmNFxAVtD08WLNaWbzRqCw0idgd1yrdHi+43JsnXTBDDIHKoJEv3kSXz0OyVh jnygGBkALY7nOrVlEMoGDNZN13h7dLsYrW8ZYtxRcoEMC/fgWMHFn7hFabuUNs1fNbstqbHIXxZQ 5EoF4AOWd+C63Qjyx6UHrf/cZM7DUjQsLMgexJTW6QkpoqzufvvIG15RYsVf4RCbg0DDiHlPpF66 rpR95hILYMv7avePDtUKuhmW7MhjX4ADX/ekOIeReiNb6YoA0dvqU+m4p6alRAwnlyT99scYhMXM h7nyPkSyJ0wsGDBwCfd6z1Hna/wjryr8sHMIcIUvSTWr3GQ9Mhi5jNPKjdibzvGnPwY1KmlxZ5Ce spILSUti6Il7nc8466tG29f5cbTl704OnNtFDWc7NJSe8oQ5NEZ+xo0GwksM7h1hChrp/o0IKgKh GSN4RIfTBGUL0IXd4/7gFMeT13MG7gzyA72iPq3G1P8w1LdSWRHQw/RX7TA6FK3IJrF0Yd5ttj5p oI0/D3cLoep8TfAtvGPun7gb/n2qVlGdSGw8UsZ6p63jds7vKa6VzrtI3Zn+nG78HMRPdFK4mFHv Du5dV+9FAdIutFMsAFAKNnhHf0aLAw1fjroNqUw1CWcizZb1ZT3Fm6/3hdtF3sEMfhwGa9k7byWh BxFysym2O5TStwTTV4SFuuKrUGUstUIaj+/AtPkS2IsL484EftN9DQsgQM9NOdGdfBjFquUegJ+P HE9BGrmIIOdw8Pi4+t1xzzZr+DVkjkWIzw0p813L1Y0X5yJ+o9LEw+rqSMcDexTzRF7i0MjO7Cyw aLSdJmn8x5HujU6j9QfI5DMrBl3NLqeB7uPBkVLZd0FujjzBWf1g3FZSFu26Qg3B1/tJSEr6crG7 BqxYR4enA/FayWoECNsbPtCEgi7xoBZuCE7HbqWKYEsh91mmvLrEjNfg5o/4k3bLp19YC3Rs4c4b WR062yi/ovUhQLfV2YYuuz/SdzyvdARn3aS4oKtxLj4Y/o/38vzK5wDm1fbM+82c9kd2SatIV8Pn PmKZwJgWwWvniMCrrPOk4d3xKF03fxtrHyNeoxTmZckneFdNt3gpodRcLu0pziq3BNwB5Pq9DCnd JxV1KHPfKQOV53MI+Jabz/Ppy/CWo3vIn6zwApnBmCjuCYtSftabb0CuxAEcuYsAf6gCxXGvN6OL JsliLRLVweHEt0nCgGuVCFPyiYMbBVNE+MwKMzedijmOSIzZPlspBtvpb+l3MdV8nSyVkh01AJiT X+6fvW41zpkWwQkFbMEnyEK0eAxlfOLby1ALO2IQwZQ5+KEFtevnjc+xp9+7z+EeEoVFLCe3Ch5P ZNP8fJWxR3y9lIVpdczoADfxuc4jiqTMxnN7xfF9KvIJwXfJj0n3m6/1G1ufUeGdgsFQQ50OKXNh 3q3lrjbuQFR3SHXeHQFyfUrqoZ9Nyq6ofBvM7dRlLJhAVnDYz6kOvpny061gbB3Bj/LUxmVX4bVu GMlF6C1TcbSHR9ko1Y00/7OTxO+cEkaUrCDF1wm4t9oc2SyA9DvaWONrf+JC7Tuq+EViJmDV5vnj w5Sgay0Js1Q0CKoYd/1NtT7WUHEvaZe3EOWkaUuJ4gOUCtU1hjkvvIWjJh+WnHwu0yDb7nyOrtd8 A50R4gJHsipCAxfinIE7eqL5RnjVTSTb7PzxcKpVIQdoCQ3oCQnTqpKqSnvLx5fqxBqYCyzPvAzp cxP/K+qcCA/CDp0+jD7hH9VBi6cDdLjwFgFocg7NkQeCkFpvLWV/t9tJ6q2k1HhYjThnGh8yy/9B syiluPTm50G5Q/1tdo/bS3Pjrbkp5ADJRtyzVaEr2oTwN6VACFlz3oG8j641KGRaAJEou2OUBdWr 8nC0sYvkPhsnmS27SH95z+kJq2tUhUnVLgVMyLUJ5jkGQeHShXUeYCe/Q6ZudLeKQ+Xi08ci9IQI A8XxdCueCtMNsk9Qu0IsZeRoSxAz4K+L6bYD2jDEEMGdyObURGf66SlglDhgbRl8cRKSJ6lPbKC1 bXtGXxbCFqb7quGNtjiyayclOiuARMBj3w5h79DZCttlTOB9XObRGJlp `protect end_protected	mit	5d9ea72c88e7387d6479ce895fdce603	0.937877	1.86516	false	false	false	false
Yarr/Yarr-fw	rtl/common/common_pkg.vhd	1	2,695	library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.gn4124_core_pkg.all; package common_pkg is component generic_async_fifo is generic ( g_data_width : natural; g_size : natural; g_show_ahead : boolean := false; -- Read-side flag selection g_with_rd_empty : boolean := true; -- with empty flag g_with_rd_full : boolean := false; -- with full flag g_with_rd_almost_empty : boolean := false; g_with_rd_almost_full : boolean := false; g_with_rd_count : boolean := false; -- with words counter g_with_wr_empty : boolean := false; g_with_wr_full : boolean := true; g_with_wr_almost_empty : boolean := false; g_with_wr_almost_full : boolean := false; g_with_wr_count : boolean := false; g_almost_empty_threshold : integer; -- threshold for almost empty flag g_almost_full_threshold : integer -- threshold for almost full flag ); port ( rst_n_i : in std_logic := '1'; -- write port clk_wr_i : in std_logic; d_i : in std_logic_vector(g_data_width-1 downto 0); we_i : in std_logic; wr_empty_o : out std_logic; wr_full_o : out std_logic; wr_almost_empty_o : out std_logic; wr_almost_full_o : out std_logic; wr_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0); -- read port clk_rd_i : in std_logic; q_o : out std_logic_vector(g_data_width-1 downto 0); rd_i : in std_logic; rd_empty_o : out std_logic; rd_full_o : out std_logic; rd_almost_empty_o : out std_logic; rd_almost_full_o : out std_logic; rd_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0) ); end component generic_async_fifo; component wb_spi generic ( g_CLK_DIVIDER : positive := 20 ); port ( -- Sys Connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0) := (others => '0'); wb_dat_i : in std_logic_vector(31 downto 0) := (others => '0'); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic := '0'; wb_stb_i : in std_logic := '0'; wb_we_i : in std_logic := '0'; wb_ack_o : out std_logic; -- SPI out scl_o : out std_logic; sda_o : out std_logic; sdi_i : in std_logic; latch_o : out std_logic ); end component; end common_pkg; package body common_pkg is end common_pkg;	gpl-3.0	b164dcea417e0d5dc667da2c2b3a2ce0	0.547681	3.159437	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/instantiation/rule_019_test_input.fixed.vhd	1	713	architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : INST1 generic map( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); a <= b; U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); a <= b; end architecture ARCH;	gpl-3.0	18f557418c975828b296ce7915330318	0.430575	2.670412	false	false	false	false
rjarzmik/mips_processor	instruction_tag.vhd	1	4,598	------------------------------------------------------------------------------- -- Title : Instruction tagging -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : instruction_tag.vhd.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-12-07 -- Last update: 2017-01-04 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-07 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- package instruction_defs is -- Smallest 2 power with at least : None, Fetch, Decode/Issue, Execute, Memory, Writeback constant NB_PIPELINE_STAGES : natural := 16; type instr_tag_t is record valid : boolean; tag : natural range 0 to NB_PIPELINE_STAGES - 1; is_branch : boolean; is_ja : boolean; is_jr : boolean; is_branch_taken : boolean; end record; constant INSTR_TAG_NONE : instr_tag_t := ( tag => 0, valid => false, is_branch => false, is_ja => false, is_jr => false, is_branch_taken => false); constant INSTR_TAG_FIRST_VALID : instr_tag_t := ( tag => 0, valid => true, is_branch => false, is_ja => false, is_jr => false, is_branch_taken => false); function get_instr_change_is_branch(itag : instr_tag_t; new_is_branch : boolean) return instr_tag_t; function get_instr_change_is_ja(itag : instr_tag_t; new_is_ja : boolean) return instr_tag_t; function get_instr_change_is_jr(itag : instr_tag_t; new_is_jr : boolean) return instr_tag_t; function get_instr_change_tag(itag : instr_tag_t; new_tag : natural) return instr_tag_t; function get_next_instr_tag(itag : in instr_tag_t; step : positive) return instr_tag_t; function get_instr_change_is_branch_taken(itag : instr_tag_t; new_is_branch_taken : boolean) return instr_tag_t; end package instruction_defs; package body instruction_defs is function get_instr_change_is_branch(itag : instr_tag_t; new_is_branch : boolean) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.is_branch := new_is_branch; return o; end function get_instr_change_is_branch; function get_instr_change_is_ja(itag : instr_tag_t; new_is_ja : boolean) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.is_ja := new_is_ja; return o; end function get_instr_change_is_ja; function get_instr_change_is_jr(itag : instr_tag_t; new_is_jr : boolean) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.is_jr := new_is_jr; return o; end function get_instr_change_is_jr; function get_instr_change_is_branch_taken(itag : instr_tag_t; new_is_branch_taken : boolean) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.is_branch_taken := new_is_branch_taken; return o; end function get_instr_change_is_branch_taken; function get_instr_change_tag(itag : instr_tag_t; new_tag : natural) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.tag := new_tag; return o; end function get_instr_change_tag; function get_next_instr_tag(itag : in instr_tag_t; step : positive) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.tag := (o.tag + step) mod NB_PIPELINE_STAGES; return o; end function get_next_instr_tag; end package body instruction_defs;	gpl-3.0	48b8bf9dffe6a6e136ea320eb1a64495	0.484341	3.943396	false	false	false	false
Logistic1994/CPU	module_ROM.vhd	1	2,054	---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:39:06 05/11/2015 -- Design Name: -- Module Name: module_rom - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; use STD.TEXTIO.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity module_ROM is port ( clk_ROM: in std_logic; M_ROM: in std_logic; nROM_EN: in std_logic; addr: in std_logic_vector(11 downto 0); datao: out std_logic_vector(7 downto 0); do: out std_logic); end module_rom; architecture Behavioral of module_ROM is type matrix is array (integer range<>) of std_logic_vector(7 downto 0); signal rom:matrix (0 to 2**12-1); procedure load_rom(signal data_word:out matrix) is file romfile: text open read_mode is "romfile2.dat"; variable lbuf: line; variable i: integer := 0; variable fdata: std_logic_vector(7 downto 0); begin for m in 0 to 15 loop for n in 0 to 15 loop for o in 0 to 15 loop if not endfile(romfile) then readline(romfile, lbuf); read(lbuf, fdata); data_word(i) <= fdata; i := i + 1; end if; end loop; end loop; end loop; end procedure; begin load_rom(rom); process(clk_ROM, M_ROM, nROM_EN) begin if rising_edge(clk_ROM) then if M_ROM = '1' and nROM_EN = '0' then datao <= rom(conv_integer(addr)); do <= '1'; else datao <= (others => 'Z'); do <= '0'; end if; end if; end process; end Behavioral;	gpl-2.0	1565b7a4c309c0c94d36a3f80d09c871	0.607108	3.164869	false	false	false	false
rjarzmik/mips_processor	Caches/SinglePort_Associative_Cache.vhd	1	28,239	------------------------------------------------------------------------------- -- Title : Single input port associative cache -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : SinglePort_Associative_Cache.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-30 -- Last update: 2017-01-01 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Cache suited for an L1 cache ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-30 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.cache_defs.all; ------------------------------------------------------------------------------- entity SinglePort_Associative_Cache is generic ( WRITE_BACK : boolean := true; DEBUG : boolean := false ); port ( clk : in std_logic; rst : in std_logic; i_porta_req : in std_logic; i_porta_we : in std_logic; i_porta_addr : in addr_t; i_porta_write_data : in data_t; i_porta_do_write_through : in std_logic; o_porta_read_data : out data_t; o_porta_valid : out std_logic; o_porta_rdy : out std_logic; o_creq : out cache_request_t; i_cresp : in cache_response_t; o_dbg_state : out cache_state; o_dbg_cstats : out cache_stats_t ); end entity SinglePort_Associative_Cache; ------------------------------------------------------------------------------- architecture rtl of SinglePort_Associative_Cache is signal allocated_way : natural range 0 to NB_WAYS - 1; signal update_alloc : boolean; --- Searcher type search_t is record way : natural range 0 to NB_WAYS - 1; way_found : boolean; way_alloc : natural range 0 to NB_WAYS - 1; valid : std_logic; dirty : std_logic; all_dirty : std_logic; data : data_t; tag_entry : tag_entry_t; evict_dirty : boolean; evict_tag_entry : tag_entry_t; end record; signal search : search_t; signal state : cache_state := s_idle; type flusher_control is record addr : addr_t; way : natural range 0 to NB_WAYS - 1; sel : cache_line_selector_t; end record; type tdm_control is record re : std_logic; raddr : addr_t; waddr : addr_t; we : std_logic; update_way : natural range 0 to NB_WAYS - 1; wtag_entry : tag_entry_t; evict_compute : std_logic; end record tdm_control; constant TDM_CONTROL_IDLE : tdm_control := (re => '1', we => '0', evict_compute => '0', raddr => (others => '0'), waddr => (others => '0'), update_way => 0, wtag_entry => (others => (others => '0'))); type cdm_control is record re : std_logic; raddr : addr_t; rway : natural range 0 to NB_WAYS - 1; waddr : addr_t; wway : way_selector_t; -- write way by way wdata : data_t; end record cdm_control; constant CDM_CONTROL_IDLE : cdm_control := (re => '1', wway => (others => '0'), raddr => (others => '0'), rway => 0, waddr => (others => '0'), wdata => (others => '0')); type porta_control is record porta_rdata : data_t; porta_valid : std_logic; porta_rdy : std_logic; end record porta_control; constant PA_CONTROL_IDLE : porta_control := (porta_valid => '0', porta_rdy => '1', porta_rdata => (others => 'X')); constant PA_CONTROL_BUSY : porta_control := (porta_valid => '0', porta_rdy => '0', porta_rdata => (others => 'X')); type flush_prepare_t is record flush_mask : cache_line_selector_t; base_addr : addr_t; way : natural range 0 to NB_WAYS - 1; sclr : std_logic; sdata : cache_line_selector_t; bclr : natural range 0 to DATAS_PER_LINE - 1; bclrena : std_logic; cline : cache_line_t; allclear : std_logic; fbitset : natural range 0 to DATAS_PER_LINE - 1; idx_rdata : natural range 0 to DATAS_PER_LINE - 1; tag_entry : tag_entry_t; next_victim : std_logic; end record flush_prepare_t; type refill_prepare_t is record refill_mask : cache_line_selector_t; base_addr : addr_t; way : natural range 0 to NB_WAYS - 1; sclr : std_logic; sdata : cache_line_selector_t; bclr : natural range 0 to DATAS_PER_LINE - 1; bclrena : std_logic; allclear : std_logic; fbitset : natural range 0 to DATAS_PER_LINE - 1; cline : cache_line_t; tag_entry : tag_entry_t; next_victim : std_logic; end record refill_prepare_t; --- Tags data signal tdata_addr : addr_t := (others => '0'); signal tdata_re : std_logic := '0'; signal tdata_waddr : addr_t := (others => '0'); signal tdata_we : std_logic := '0'; signal tdata_way : natural range 0 to NB_WAYS - 1; signal tdata_way_alloc : std_logic; signal tdata_wtag : tag_entry_t; --- Cache data memory signal cmem_addr : addr_t := (others => '0'); signal cmem_re : std_logic := '0'; signal cmem_rway : natural range 0 to NB_WAYS - 1; signal cmem_waddr : addr_t := (others => '0'); signal cmem_wway : way_selector_t := (others => '0'); signal cmem_wdata : data_t; --- Fetcher signals signal porta_rdy : std_logic; -- deasserted when porta request ongoing signal porta_requested_addr : addr_t; signal porta_requested_we : std_logic; signal porta_requested_writethrough : std_logic; signal porta_requested_wdata : data_t; -- Cache line flusher prepaartor mask feeder signal ffeed_sclr : std_logic; signal ffeed_sdata : cache_line_selector_t; signal ffeed_data : cache_line_selector_t; signal ffeed_bclrena : std_logic; signal ffeed_bclr : natural range 0 to DATAS_PER_LINE - 1; signal ffeed_fbitset : natural range 0 to DATAS_PER_LINE - 1; signal ffeed_allclear : std_logic; -- Cache line refiller preparator mask feeder signal rfeed_sclr : std_logic; signal rfeed_sdata : cache_line_selector_t; signal rfeed_bclrena : std_logic; signal rfeed_bclr : natural range 0 to DATAS_PER_LINE - 1; signal rfeed_fbitset : natural range 0 to DATAS_PER_LINE - 1; signal rfeed_allclear : std_logic; -- Outer interface signal cls_req : cls_op; signal cls_creq : cache_request_t; signal cls_cresp : cache_response_t; -- Debug and statistics signal cstats : cache_stats_t := (others => 0); ----------------------------------------------------------------------------- -- Internal functions declarations ----------------------------------------------------------------------------- function reverse_any_vector (a : in std_logic_vector) return std_logic_vector is variable result : std_logic_vector(a'range); alias aa : std_logic_vector(a'reverse_range) is a; begin for i in aa'range loop result(i) := aa(i); end loop; return result; end function reverse_any_vector; function get_acquire_new_search(req : std_ulogic; state : cache_state; rfeed_allclear : std_ulogic; force_write_through : boolean) return boolean is variable o : boolean; begin o := (state = s_idle or state = s_searching or (state = s_refill_cache and rfeed_allclear = '1') or (state = s_write_allocate and not force_write_through) or state = s_writethrough) and req = '1'; return o; end function get_acquire_new_search; begin gtdm : entity work.tags_data_mem generic map (DEBUG => DEBUG) port map ( clk => clk, i_raddr => tdata_addr, i_re => tdata_re, o_tag_found => search.way_found, o_way_found => search.way, o_tag_entry => search.tag_entry, o_data_valid => search.valid, o_way_evict => search.way_alloc, o_evict_dirty => search.evict_dirty, o_evict_tag_entry => search.evict_tag_entry, i_waddr => tdata_waddr, i_we => tdata_we, i_update_way => tdata_way, i_wtag_entry => tdata_wtag, i_evict_compute => tdata_way_alloc); gcdmem : entity work.cache_data_mem generic map (DEBUG => DEBUG) port map ( clk => clk, i_raddr => cmem_addr, i_re => cmem_re, i_rway => cmem_rway, o_rdata => search.data, i_waddr => cmem_waddr, i_wway => cmem_wway, i_wdata => cmem_wdata); flush_feeder : entity work.mask_feeder generic map ( WIDTH => DATAS_PER_LINE) port map ( clk => clk, sclr => ffeed_sclr, sdata => ffeed_sdata, bclrena => ffeed_bclrena, bclr => ffeed_bclr, fbitset => ffeed_fbitset, allclear => ffeed_allclear); refill_feeder : entity work.mask_feeder generic map ( WIDTH => DATAS_PER_LINE) port map ( clk => clk, sclr => rfeed_sclr, sdata => rfeed_sdata, bclrena => rfeed_bclrena, bclr => rfeed_bclr, fbitset => rfeed_fbitset, allclear => rfeed_allclear); controller : process(rst, clk, i_porta_addr, i_porta_req, i_cresp, search, porta_requested_we, porta_requested_addr, porta_requested_wdata, state, ffeed_allclear, ffeed_fbitset, rfeed_allclear, rfeed_fbitset, cstats) variable wt_cline : cache_line_t; variable creq : cache_request_t; variable cresp : cache_response_t; -- Tags Data Memory control variable tdm : tdm_control; variable cdm : cdm_control; variable pa : porta_control; variable fprep : flush_prepare_t; variable rprep : refill_prepare_t; variable acquire_new_search : boolean := false; variable force_write_through : boolean := false; begin -- Input variables following signals update fprep.allclear := ffeed_allclear; fprep.fbitset := ffeed_fbitset; rprep.allclear := rfeed_allclear; rprep.fbitset := rfeed_fbitset; cresp := i_cresp; acquire_new_search := get_acquire_new_search(i_porta_req, state, rfeed_allclear, force_write_through); if rst = '1' then state <= s_idle; cdm := CDM_CONTROL_IDLE; tdm := TDM_CONTROL_IDLE; pa := PA_CONTROL_IDLE; acquire_new_search := false; porta_requested_addr <= (others => '0'); porta_requested_we <= '0'; porta_requested_wdata <= (others => 'X'); elsif rising_edge(clk) then if acquire_new_search then porta_requested_addr <= i_porta_addr; porta_requested_we <= i_porta_we; porta_requested_writethrough <= i_porta_do_write_through; porta_requested_wdata <= i_porta_write_data; end if; case state is when s_idle => if i_porta_req = '1' then state <= s_searching; else state <= s_idle; end if; when s_searching => fprep.base_addr := get_address(search.evict_tag_entry.tag, get_address_index(porta_requested_addr), 0); if search.way_found and ((search.valid = '1' and porta_requested_we = '0') or porta_requested_we = '1') then if porta_requested_we = '0' then -- Read cache hit cstats.read_hits <= cstats.read_hits + 1; if i_porta_req = '0' then state <= s_idle; else state <= s_searching; end if; else -- Write cache hit cstats.write_hits <= cstats.write_hits + 1; state <= s_write_allocate; fprep.way := search.way; fprep.tag_entry := search.tag_entry; fprep.next_victim := '0'; force_write_through := not WRITE_BACK or porta_requested_writethrough = '1'; if force_write_through then cstats.write_throughs <= cstats.write_throughs + 1; else cstats.write_backs <= cstats.write_backs + 1; end if; end if; elsif porta_requested_we = '0' then -- Read miss cstats.read_misses <= cstats.read_misses + 1; if search.way_found then --- Way is found, but data in the cache line is not valid state <= s_refill_memory; rprep.way := search.way; rprep.tag_entry := search.tag_entry; rprep.next_victim := '0'; cstats.refills <= cstats.refills + 1; elsif search.evict_dirty then state <= s_prepare_flushing; fprep.way := search.way_alloc; fprep.cline := (others => (others => 'X')); rprep.way := search.way_alloc; rprep.tag_entry := TAG_ENTRY_EMPTY; rprep.next_victim := '1'; fprep.flush_mask := reverse_any_vector(search.evict_tag_entry.dirtys); cstats.flushes <= cstats.flushes + 1; else state <= s_refill_memory; rprep.way := search.way_alloc; rprep.tag_entry := TAG_ENTRY_EMPTY; rprep.next_victim := '1'; cstats.refills <= cstats.refills + 1; end if; else -- Write miss cstats.write_misses <= cstats.write_misses + 1; force_write_through := not WRITE_BACK or porta_requested_writethrough = '1'; if search.evict_dirty then state <= s_prepare_flushing; fprep.way := search.way_alloc; fprep.tag_entry := TAG_ENTRY_EMPTY; fprep.next_victim := '1'; fprep.cline := (others => (others => 'X')); fprep.flush_mask := reverse_any_vector(search.evict_tag_entry.dirtys); cstats.flushes <= cstats.flushes + 1; else state <= s_write_allocate; fprep.way := search.way_alloc; fprep.tag_entry := TAG_ENTRY_EMPTY; fprep.cline := (others => (others => 'X')); fprep.next_victim := '1'; end if; if force_write_through then cstats.write_throughs <= cstats.write_throughs + 1; else cstats.write_backs <= cstats.write_backs + 1; end if; end if; when s_prepare_flushing => fprep.cline(fprep.idx_rdata) := search.data; if fprep.allclear = '1' then state <= s_flush_outer; else state <= s_prepare_flushing; end if; fprep.idx_rdata := fprep.fbitset; when s_flush_outer => state <= s_flushing; -- pragma translate_off if DEBUG then report "Cache: flush @" & to_hstring(fprep.base_addr) & " mask=" & to_bstring(fprep.flush_mask) & " at way " & integer'image(fprep.way); end if; -- pragma translate_on when s_writethrough => if cresp.done = '0' then state <= s_writethrough; else if i_porta_req = '0' then state <= s_idle; else state <= s_searching; end if; end if; when s_flushing => fprep.idx_rdata := fprep.fbitset; if cresp.done = '1' then if porta_requested_we = '0' then state <= s_refill_memory; cstats.refills <= cstats.refills + 1; else state <= s_write_allocate; end if; else state <= s_flushing; end if; when s_write_allocate => if force_write_through then state <= s_writethrough; else if i_porta_req = '0' then state <= s_idle; else state <= s_searching; end if; end if; when s_refill_memory => if cresp.done = '1' then state <= s_refill_cache; else state <= s_refill_memory; end if; when s_refill_cache => if rprep.allclear = '1' then if i_porta_req = '1' then state <= s_searching; else state <= s_idle; end if; -- pragma translate_off if DEBUG then report "Cache: refill @" & to_hstring(rprep.base_addr) & " mask=" & to_bstring(rprep.sdata) & " at way " & integer'image(rprep.way); end if; -- pragma translate_on else state <= s_refill_cache; end if; end case; if acquire_new_search then -- Cowardly, we're only refilling one data of the dataline rprep.refill_mask := reverse_any_vector(std_logic_vector(to_unsigned( 2*get_data_set_index(i_porta_addr), rprep.refill_mask'length))); rprep.base_addr := get_address(get_address_tag(i_porta_addr), get_address_index(i_porta_addr), 0); end if; end if; -- Default values fprep := ( flush_mask => fprep.flush_mask, base_addr => fprep.base_addr, sclr => '0', sdata => reverse_any_vector(search.evict_tag_entry.dirtys), -- s_prepare_flushing bclr => fprep.idx_rdata, bclrena => '0', allclear => ffeed_allclear, fbitset => ffeed_fbitset, cline => fprep.cline, way => fprep.way, -- registered idx_rdata => fprep.idx_rdata, -- registered next_victim => fprep.next_victim, -- registered tag_entry => fprep.tag_entry ); rprep := ( refill_mask => rprep.refill_mask, -- refill_mask => (others => '0'), base_addr => rprep.base_addr, way => rprep.way, tag_entry => rprep.tag_entry, -- registered next_victim => rprep.next_victim, -- registered sclr => '0', sdata => reverse_any_vector(rprep.refill_mask), -- s_refill_memory bclr => 0, -- don't care, value is overwritten anyway bclrena => '0', allclear => rfeed_allclear, fbitset => rfeed_fbitset, cline => (others => (others => ('X')))); cdm := CDM_CONTROL_IDLE; cdm.rway := search.way; tdm := TDM_CONTROL_IDLE; pa := PA_CONTROL_BUSY; -- default creq := (req => cls_none, addr => (others => 'X'), sel => (others => '0'), cline => fprep.cline); cresp := i_cresp; for i in wt_cline'range loop wt_cline(i) := porta_requested_wdata; end loop; -- Combinational s_refill_memory if rst = '1' then else case state is when s_idle => pa := PA_CONTROL_IDLE; when s_searching => if search.way_found and ((search.valid = '1' and porta_requested_we = '0') or porta_requested_we = '1') then if porta_requested_we = '0' then -- Read cache hit --RJK dbg_incr_read_cache_hits(dbg_stats); pa := (porta_rdata => search.data, porta_valid => '1', porta_rdy => '1'); else -- Write cache hit --RJK dbg_incr_write_cache_hits(dbg_stats); tdm.update_way := search.way; tdm.wtag_entry := search.tag_entry; tdm.evict_compute := '0'; pa := PA_CONTROL_BUSY; end if; else -- Read of Write miss if porta_requested_we = '0' then -- Read miss if search.way_found then --- Way is found, but data in the cache line is not valid creq := (req => cls_refill, addr => rprep.base_addr, sel => rprep.refill_mask, cline => rprep.cline); elsif search.evict_dirty then fprep.sclr := '1'; fprep.bclrena := '0'; else creq := (req => cls_refill, addr => rprep.base_addr, sel => rprep.refill_mask, cline => rprep.cline); end if; else -- Write miss if search.evict_dirty then fprep.sclr := '1'; fprep.bclrena := '0'; else end if; end if; end if; when s_prepare_flushing => fprep.sclr := '0'; fprep.bclr := fprep.fbitset; fprep.bclrena := '1'; cdm.rway := fprep.way; if fprep.allclear = '1' then -- Cannot launch creq yet as the last transfer to frep.cline shoud -- be done first else cdm.raddr := std_logic_vector( unsigned(fprep.base_addr) + fprep.fbitset DATA_WIDTH / 8); cdm.re := '1'; end if; when s_flush_outer => creq := (req => cls_flush, addr => fprep.base_addr, sel => reverse_any_vector(fprep.flush_mask), cline => fprep.cline); when s_flushing => creq.req := cls_none; if cresp.done = '1' then if porta_requested_we = '0' then creq := (req => cls_refill, addr => rprep.base_addr, sel => rprep.refill_mask, cline => rprep.cline); end if; end if; when s_refill_memory => if cresp.done = '1' then rprep.sclr := '1'; rprep.bclrena := '0'; tdm.waddr := porta_requested_addr; tdm.we := '1'; tdm.update_way := rprep.way; tdm.wtag_entry := rprep.tag_entry; tdm.wtag_entry.tag := get_address_tag(rprep.base_addr); tdm.wtag_entry.valids := tdm.wtag_entry.valids or rprep.refill_mask; tdm.wtag_entry.dirtys := tdm.wtag_entry.dirtys and (not rprep.refill_mask); tdm.evict_compute := rprep.next_victim; end if; when s_refill_cache => rprep.sclr := '0'; rprep.bclrena := '1'; rprep.bclr := rprep.fbitset; if rprep.allclear = '1' then cdm := CDM_CONTROL_IDLE; cdm.raddr := i_porta_addr; cdm.re := i_porta_req; cdm.rway := rprep.way; tdm := TDM_CONTROL_IDLE; tdm.raddr := i_porta_addr; tdm.re := i_porta_req; pa := (porta_rdata => search.data, porta_valid => '1', porta_rdy => '1'); else cdm.raddr := porta_requested_addr; cdm.re := '1'; cdm.rway := rprep.way; tdm.raddr := porta_requested_addr; tdm.re := '1'; tdm.we := '0'; cdm.waddr := std_logic_vector( unsigned(rprep.base_addr) + rprep.fbitset * DATA_WIDTH / 8); cdm.wway := to_way_selector(rprep.way); cdm.wdata := cresp.cline(rprep.fbitset); end if; when s_write_allocate => cdm := CDM_CONTROL_IDLE; cdm.raddr := i_porta_addr; cdm.re := i_porta_req; cdm.rway := rprep.way; cdm.waddr := porta_requested_addr; cdm.wdata := porta_requested_wdata; cdm.wway := to_way_selector(fprep.way); tdm := TDM_CONTROL_IDLE; tdm.raddr := i_porta_addr; tdm.re := i_porta_req; tdm.waddr := porta_requested_addr; tdm.we := '1'; tdm.update_way := fprep.way; tdm.wtag_entry := fprep.tag_entry; tdm.wtag_entry.tag := get_address_tag(porta_requested_addr); tdm.wtag_entry.valids := tdm.wtag_entry.valids or to_cacheline_selector(porta_requested_addr); if force_write_through then tdm.wtag_entry.dirtys := tdm.wtag_entry.dirtys and not to_cacheline_selector(porta_requested_addr); else tdm.wtag_entry.dirtys := tdm.wtag_entry.dirtys or to_cacheline_selector(porta_requested_addr); end if; tdm.evict_compute := fprep.next_victim; if not force_write_through then pa := (porta_rdata => (others => 'X'), porta_valid => '1', porta_rdy => '1'); else -- Prepare the writethrough creq := (req => cls_flush, addr => get_address(get_address_tag(porta_requested_addr), get_address_index(porta_requested_addr), 0), sel => reverse_any_vector(std_logic_vector(to_unsigned( 2**get_data_set_index(porta_requested_addr), creq.sel'length))), cline => wt_cline); end if; when s_writethrough => tdm := TDM_CONTROL_IDLE; tdm.raddr := i_porta_addr; tdm.re := i_porta_req; cdm := CDM_CONTROL_IDLE; cdm.raddr := i_porta_addr; cdm.re := i_porta_req; if cresp.done = '1' then pa := (porta_rdata => (others => 'X'), porta_valid => '1', porta_rdy => '1'); end if; end case; end if; -- Control signal --- Tags data memory if rst = '0' and (state = s_idle or state = s_searching) then tdata_addr <= i_porta_addr; tdata_re <= i_porta_req; else tdata_addr <= tdm.raddr; tdata_re <= tdm.re; end if; tdata_waddr <= tdm.waddr; tdata_we <= tdm.we; tdata_way <= tdm.update_way; tdata_wtag <= tdm.wtag_entry; tdata_way_alloc <= tdm.evict_compute; --- Cache data memory if rst = '0' and (state = s_idle or state = s_searching) then cmem_addr <= i_porta_addr; cmem_re <= i_porta_req; else cmem_addr <= cdm.raddr; cmem_re <= cdm.re; end if; cmem_rway <= cdm.rway; cmem_waddr <= cdm.waddr; cmem_wway <= cdm.wway; cmem_wdata <= cdm.wdata; --- Flush : cache line mask feeder ffeed_sclr <= fprep.sclr; ffeed_sdata <= fprep.sdata; ffeed_bclrena <= fprep.bclrena; ffeed_bclr <= fprep.bclr; --- Refiller : cache line mask feeder rfeed_sclr <= rprep.sclr; rfeed_sdata <= rprep.sdata; rfeed_bclrena <= rprep.bclrena; rfeed_bclr <= rprep.bclr; -- Outer interface o_porta_read_data <= pa.porta_rdata; o_porta_valid <= pa.porta_valid; o_porta_rdy <= pa.porta_rdy; o_creq <= creq; -- Debug signals o_dbg_state <= state; o_dbg_cstats <= cstats; end process controller; end architecture rtl;	gpl-3.0	683307fe74a3cc433b583d4a343ebaa4	0.498495	3.656954	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sts_mngr.vhd	1	11,936	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_mm2s_sts_mngr.vhd -- Description: This entity mangages 'halt' and 'idle' status for the MM2S -- channel -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library proc_common_v4_0; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_mm2s_sts_mngr is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Any one of the 4 clock inputs is not -- synchronous to the other ); port ( -- system signals m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- dma control and sg engine status signals -- mm2s_run_stop : in std_logic ; -- -- mm2s_ftch_idle : in std_logic ; -- mm2s_updt_idle : in std_logic ; -- mm2s_cmnd_idle : in std_logic ; -- mm2s_sts_idle : in std_logic ; -- -- -- stop and halt control/status -- mm2s_stop : in std_logic ; -- mm2s_halt_cmplt : in std_logic ; -- -- -- system state and control -- mm2s_all_idle : out std_logic ; -- mm2s_halted_clr : out std_logic ; -- mm2s_halted_set : out std_logic ; -- mm2s_idle_set : out std_logic ; -- mm2s_idle_clr : out std_logic -- ); end axi_dma_mm2s_sts_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_mm2s_sts_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ATTRIBUTE async_reg : STRING; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal all_is_idle : std_logic := '0'; signal all_is_idle_d1 : std_logic := '0'; signal all_is_idle_re : std_logic := '0'; signal all_is_idle_fe : std_logic := '0'; signal mm2s_datamover_idle : std_logic := '0'; signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0'; signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0'; --ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true"; signal mm2s_halt_cmpt_d2 : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Everything is idle when everything is idle all_is_idle <= mm2s_ftch_idle and mm2s_updt_idle and mm2s_cmnd_idle and mm2s_sts_idle; -- Pass out for soft reset use mm2s_all_idle <= all_is_idle; ------------------------------------------------------------------------------- -- For data mover halting look at halt complete to determine when halt -- is done and datamover has completly halted. If datamover not being -- halted then can ignore flag thus simply flag as idle. ------------------------------------------------------------------------------- GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate begin -- Double register to secondary clock domain. This is sufficient -- because halt_cmplt will remain asserted until detected in -- reset module in secondary clock domain. AWVLD_CDC_TO : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => mm2s_halt_cmplt, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => mm2s_halt_cmpt_cdc_d2, scndry_vect_out => open ); -- REG_TO_SECONDARY : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- -- if(m_axi_sg_aresetn = '0')then -- -- mm2s_halt_cmpt_d1_cdc_tig <= '0'; -- -- mm2s_halt_cmpt_d2 <= '0'; -- -- else -- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt; -- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig; -- -- end if; -- end if; -- end process REG_TO_SECONDARY; mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2; end generate GEN_FOR_ASYNC; GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate begin -- No clock crossing required therefore simple pass through mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt; end generate GEN_FOR_SYNC; mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1') or (mm2s_stop = '0') else '0'; ------------------------------------------------------------------------------- -- Set halt bit if run/stop cleared and all processes are idle ------------------------------------------------------------------------------- HALT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_halted_set <= '0'; -- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then mm2s_halted_set <= '1'; else mm2s_halted_set <= '0'; end if; end if; end process HALT_PROCESS; ------------------------------------------------------------------------------- -- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors ------------------------------------------------------------------------------- NOT_HALTED_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_halted_clr <= '0'; elsif(mm2s_run_stop = '1')then mm2s_halted_clr <= '1'; else mm2s_halted_clr <= '0'; end if; end if; end process NOT_HALTED_PROCESS; ------------------------------------------------------------------------------- -- Register ALL is Idle to create rising and falling edges on idle flag ------------------------------------------------------------------------------- IDLE_REG_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then all_is_idle_d1 <= '0'; else all_is_idle_d1 <= all_is_idle; end if; end if; end process IDLE_REG_PROCESS; all_is_idle_re <= all_is_idle and not all_is_idle_d1; all_is_idle_fe <= not all_is_idle and all_is_idle_d1; -- Set or Clear IDLE bit in DMASR mm2s_idle_set <= all_is_idle_re and mm2s_run_stop; mm2s_idle_clr <= all_is_idle_fe; end implementation;	bsd-2-clause	edafe709987cf66ec75d55d31f6ac66e	0.45501	4.433878	false	false	false	false
cwilkens/ecen4024-microphone-array	microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/single_rate.vhd	2	370,178	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block qvnP+TCG9SuXRvv7a3rmuAv2C6rsYM8jAKFPno/STh9idqR5n0FK43o3aY0omE0ZwrzY2ttHqnIj 3dqICvMRlw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block GBOodxVyVUrkAi59/KekQELXvq690plpxovv4wFnUwDONHz0YOQk6eJs/2bJDQJGejj9wuVDqsbg 95gtN/U6GB9hHLJIX9sliuWeFQwGDPNn3O236v9ZTpQMiWuuja0hofL/S999Mqgr3u0cbTNoYkdE fs3C94VadzwBdg2guhU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Cp8sEszpVFNPLJPbdP65Nzx/o8LDk5SPLkg5C3O8IHenLI6lEcUl5CEFNcD+mQzHJLbB3ViDw5OZ sgSNOhpwRRTqjSPTxsdLlccEWzLDsox0Z/Suhw56InB+FChiRoMvwza4YKAkrc0mjoslVnYYOLvY 03Q0eCkX+SSnInS439o1sjZOOOua09vETcssSw3+gamMWM8ikrd3CoLzo8+E3VpZu4xFZVyl2Ow6 cacHGQmFeanhwzkrMvbsmRFeT9LmjLq+lBUxpwJGJr2w9sAJ0MZFqUwo8xyUHzB8x4oZRQo2e/w7 cJ+zASBCZsksLQQ4k9p1S5COjfq4YudL0nH/bA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pa8yyOZJFNW+wentPuYPmJYKYoikN5fKHznWMzdv7L8didyyoHPytL8YzqL4fwRIBlRmogb/E98u fBDEldyIabwfxetVJOoLC96J75pfn6s08GUEu50qfO6ne5nrYpXBm6rLgqcAlL7ZOYpNkrNXXTrv zjq9I8LcvtMOD8N17Jk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HagCWHSO/Xsb1R5I+VaMowWwTeTXVdAudCC77O1kf7f5N8TsxigBkB7r1lAKxGgbrhJmGbCbdPPv sc4tSQGz+l2hTPDz/7E/onmC8PZo3jnStfGPUiuN5D+kgfYW/Z9/1IyYWsoof3wsdjy+1CzG+vd0 uyMOeu+yCf2pLJxP1VcmeUT/ya+wVBaDRcPou33SroIYIPNIJRhTtxPOGkokQTIkDXStEKfhU2Wt ZdVXorAtCb5O5KE16dibeZasxjhJkW1WqFfpcx0FM7z3ntCextcpI7pbpW0yrzGqITyOHwmCJiGe Rs9RdBls7mIEhyC6sBY8Mdt/h0nfNqgp7VYi7w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 272288) `protect data_block PpNZ/e3KODH8af1haqCiAcrXGybbF7Uym0XDpYm/sBhNIq3hbnvm0dlevSxu6Xhq9JTv/ja+e617 J8kWSUTddKptqXsvpZbLkLFwNay+N0AWqyuFWUP1u+9H5ZwkG3uWgUrAVn92bHddKsn+Wt6vqZmL uMZxCXLNBRLmSWCM6U9PhflDO7PQVKq2xyVDBotkFc9x1M42AuIGdPqILXugUZgdzq6j18KlgGyk 6l0nGQdEjASksHLZEzk5IjmftdH5/gWPx7TPxj1WGCBnsOoey9MOe/BQFd+eACHjaMZZn/dvy0X3 lwqwEs+RZikTmNHGVWPl2fXoOPW8cTocvHiFVHdqGuRHyBc0E5NwrWnQe3mK81gjIjg9tylrr3yT qVTEtOC87rTfNip5aQOE7NyC+Qptc2pdODWCCGEVkGPOG5Dq6CiiMLAvaQuQU7klcnIvABK/1Eb1 M6i5btMBG3Sk1LdyNJNssBTiORO1bQStALo6fqVcZKbjDx5DVdfxsNlJbfXBJrjUvzHyjFIyxhVl wbVMmWdk46rlDyGBoVIuSZEUDTJJohbSzlIauLs7YQnDAmvk73cclza2vJYbSh5VoQtH01pjZ0QX UWg+rCGLKhgJYPduxLkFTQ24aMcZRc/1usRcgut7cfbcy1Eo5wCSSvN3/h2KEALpnnFwH19p9yPa e8A5/I/5+dNsMcDWaRMN4u4H8jG9wOAEayfo2t70iq70+OOa3OUBVUS+HLclNtkEUC1hw1FOGmam gk+I4iKbVHn3fcdV2ys2YXDetX812IZs24Hm8iqbFYzTMdSfJnVquq4ZmhZcjnWQDcUqHRX5IYVa d0yEaCIvqFYJsLxGcdCqELXm2ZvvhAzA1Xh9si7mi1nbrb04wEK1HlHXw+s11Jm4E9wIHZdauRRf o4Xs77Pzgv3TOPUcpSbht7ZN4h9tlLMiE9zFRJnONNMYADgLu88BkkKyYwln4iUc6syZYP6UlW1L sdbzreCCz1jpTKF/502NkQ5HdAlAls5x4Jk+0w36bohlGvI8XxaK3KSkaYl5oSSZbrzb03EDNZWM nQIv7Lj+EojGq52bAHHa9UQqYF2CklQUKu96sFT21NaFt6hOBMY/QON2uoBAKwcKLyf3jAOHiN/e JmT768qjlZEpR3/paTbviNi77YEvyt4mxnHwGgotsqgdcjoFRXxEj92CZ/7AvhmWitSWDp2/rsx2 qKKwZSODMBtSthpJdYZuMad6gJXShRMyleQeRg4OTxuZvrRfXvehx+RpvCkW/uoVWv01/CWMOuJA 4zUZPPkrLOtW90ERQui5Zz5pGuycLzuLn/mjUH2JtegKipesLXQp5WIXNBolqpWT/t5PxjgAOiPY /miAazNAPHjzdVJtGb0JbcTzm879GrcFrLZRiP1TzmqFQOwmjonYul7hY7x3JFM4XHn7cr8SwF3A B5I72A1fluHdc2fw/Qj8X49PVC+oX83JAuW8BhRW6WJCF5YGglBHpMpXgRxAASp5NlsOhKFhrnhq yyjIYFw7FB/7czMp6xNjii9KB+vhr/IvpDPnyS/uGo/Ty/lIbLur9f7mx+oRmHOhjgvour9EGWsi 3liu4P8fcD5sSPQiXWjCUqIdpA3czuvZUUG2WoFNp3494nId/qqZWsOXMgUqIB/Xkb0cXBTYl9nM W2UTKY/IeOEPh/ccAwG8Urj3uPFWszuTa5mxYxOb/bRzIZBsE1BpMDmF0NT7PJQ3QSBUlOjU/D/h c57mN995yxjgm/74vPIF/Dapwwy/wEBUMQmbWJ2Xujkgk9M/UlFgKTvLcRdV37GFl7WODuz7Utdw iwi7yaAceHQ49oHeWH2g9yia+Q9/s7NLBvF+hJ9Trx3LFC/ZTJT6YouROGq/ZM+MtQe7tfS8Gm6e EbrBBbGhKHJ+20dEslZDp22jAQ1sezg01MxeD6FoPIme6nh7woavT0DYfKDSn4V/waRWKU6uoNUn hUcsP8k1jHukT3B8F8yjeH28AUH4JvqEgBRtWAq00lPmfPvDS9q1KuTmD+uxnnMc062ukeVpCGE1 WBz2VTmRrdvkjWAsWTnpYH3lxcMAw861AkO28Jpb2C0mM+n+/sEsMsmSzoJ930WxXWcU+muIi6t4 KYOVLvdejLFaU6uz3sLbh43HAPGbiOp8rfcQqeHSuJKV2TBb/wWDrBm+Px1OGhI+ZOn8YUhN6O/j 2O4bpM8Z2R6/R8kpxJBbCQWvMw5EYTBcBROOVuEBjB0vh7y1GGHFek5WBNiki+vsNoVyo5MZUvyT dymmWI8yxCy/coGsTZLnGB6UwHD2uuS6P7PanKMSNTFcy1Mg1lNc9bOV0RMir17++2ouQBqoeyZ6 c5M6ITuz6+xBVWEZIc6h8SVYhbznB4EDGolHl7PJNEt7rgQbubNa+9iXCG/p4EPCGg7bkcwX/KRV pyJgxAlyL7awtTygx2C1qHrl5C/qo5TPxq/uvU0fW3pbkMLDDvzXY8Kt+ZeGxg7J14WDCTPDyWVd qzQGE1i48qK0TJOb+T3kkWZcTWJ4+5Au5Tl3YnGdr5lBzSawl4bIFKXYxxCBTuANkLeFnLt9HWsM khmOIcilClWDvnTO4G6ZysEfcmg2MCFHZKmzSjKnQdNqtGtusO+ItFGIJEGDuQU1xbY9hy2d4dkk 0nFDZmfiPJ/PMZHQWMhIa+FFOWic9RJBGNS2gHdoVFcVv7kNM6QwAEX8mpcU0YWKkOLcKmCp/y1k 7m5bu1+2wbauGKHlygh0WdjiLz2IqxP2rNXdvFAN/BXp6mSZy7oLNuRLLllxOgpEwPmkNHjYvW3z BQ3m2T5jjZOXA4vzwW6Lv5rmrabDfx+KxTreHBiIfra9mt6AQ1DF6LIUqVSKkNS8HWEivFgUCqne CqHRGCrwJs/lkxT+4YkxLgHlgALtv1zeDZxlBQbXxw5Vh0t9MPL/YS1qjvZs9qOwne40pxjOs2I9 N//h6Q1HGC5MegAvqGpWMOMez/COBBn0+0xAxcFg9fjHjnDDMBACeL3T33Ez0Ec75SLoN2kOWlrC HgvYEXW1/oPHKHvcukGlPsRrKmcLs/f1Tz5zdpU3pOMdQ5x6fCxfsdecSwEslhaStsE5E0v/B9qv nvGvZhvh1WK0ca6ox39NpzAsm7NF/FtJfjYf9PbTUQg3e+Dqf1uCPrhzjGWtaVLWlTZYmsqZJU9h AgWMDEGYZ6w1qaMBzytBs2AUjsRhFXPvqJQqDnLk9bEOEemcGdXVfdZKLE1cR7C3/ESyxh8N3GNq tMDdHf0pQpk1o+vZGV0pJ2isABJT/+k4oZ5/M+9L6vsS4TlaVpjIvoz9vlVeagJSRNQ/eLF+vX8+ bYyu2dBGV0PjkG5ySdEV0+0/3jPHuKHwzyJiG6EHwsg8cRpAjt8w8BVu3GEql3dqMwuGwgcfdoU3 w9D1c2VZpOga8ID5j9PmeSVLEoNHajG6wilyu1pSINMAj7HnEbHku2xQ1BRyuG0taFRKS29mw1zF yKaN75UW2vUEm7KCe56Gs6tu1fhKtUtVFCWVgxIcuZfJWh44iQEXupEaTPD/jqlO8g2AifoDdpP2 3vhgnqcwLDjOt8uZzZsMA4/JgzV6haCzJYZDwxZ/hCEKA+hxi+EqUXz+6FIeRgiMB9sq6rcNEFqE wTpro+Us9hckcHm0nPAHT3aZRVBpixaejNfLjgFisDNTF9Q/PkRdUghRhtKfZGXmUTEyAzUIYCTH BizFVvuqz0SCwtKfYChRhwtjm53XIVZk0lbcChahNwcaWrnFisZZ1nBRVmhql6peeHKWlYwgIeV5 2YmzHoEvpidTay0XUnioAZkC2VPmHpIrmnE/bwSmfDG5bJ76+4/9BmY17d1Tp50YVRSL2vVKBo/Y Gkw4+4l9ke+rjWFpaIbvvcqj1taezl+dU9syKzTktZX7KYybHr4KahAfKEUbmGWUi9AlrDdf2VS5 5EtHT4vAen4S/4Jcr0ykckmNsr0sBOkFJempCep7SRgGSO29G8d5XhCm7X/bYrimsVayUCkgF3En pKsE9mw8SHjcVjn1A30QM/LTjzwetJzbmaEUy2z6jd+lY43yPLxlU9g+TW/sx1kBpfuyR0LMEiWT pnMS/xZrCl3q2Yql1tc0K6JjNtQAYLlBzW2r5tftIQdKvyLTrAnyPiXw21TxBTo2HFOQGq0CKfUY fCFt0J4GfJ8Km/ghL2L1W8IhjJ0hq7NtrU3aGcc1FfovqVOmZkWNKjEjHciYZZHd2yhgfCcl0oCZ UgDmpBOWVklm3XJd+QMySvADHWq9NyyAfwBjsN906tnHKmiFcbnsCS11mkM7FQRhoGrn/mjpl3EE OJGPRMZobTgBmAcNdxdtGo3EAhN3e2WhZQxzkPe4/1CIlz2oM0neQ4UYJ48zTrOoBZ0Y/jSXzLJj k+xf/4EnVLTwoUyZFi+xieeOZO6KykpWYZYtrqdACwEhVtB/2sVsVdiFl1iS2jiTvOwA2heRT98Z Y7gfNt6N24BCRGvDjsJCuWAfWFniOYrFKLQ0RBBE56lzsH2Fn81D8sQz5wm4C1UJpVxKcPVg1Dnp F97DPilV2NL2j6RoZ/VLisps+FbRFwkCZlEBdubjUYaT4N3s+ozCZCkISpCZY4nVwfn5Krjz2A7l GK1ikxkxhZWXfzB5IDWcjr8PoekwL9cG94gl/6ria7AK8ZTr39mRTlMjYzFP2MlwIvfN/1A6YaYI KhK7k+Ue/PzTx0/9p+iznJHTYV5X2Qk3V2nlqYG8q2jFlZ75xUF/qZZEBSxjt5NbV6zrHwB2+sJo DGeedrA/RWnjBlEGc8H9UYf4Iut2dbcisZrdY0evbjl6tN+HiZORbSVcwKmDZP6pbg/877kW7fe/ Fo+hiLDOHMPkGPPuqmWyaEs6rccror/iN/zST0INrmRazpGXYDD8Jr8FtLNFC7Z+Bya1PU5xJsWe HU86+vk++lVBgMA9DVGNjWGnD30xrAzvv2pbe526ZltnVMU6EyGtDV3C0nDi1uVxWnIPuoIr81J2 a0bfV7ZAY742nk9Jg9/KnzYTThsYmDXmAwWUKdOTDzbLxvBRn35H8ouIgoGIkKU1ZXez66PaXGqx LpVYMfh7cpbrKKfs+6D2JxFYlGiS3rqQJCBZc3uZdMlAKJz1TJX9I0suGFqI/r+Jyi1GZ48Tcwhk IDHFP/xJdNVZzvBpSdEDo2Ges1euUhWKyYX1pujez/AIfabHzzzl423E/aOc1WKtLa3a2f+XRROG dJ7liSBYNENWIZD2DYFNtbWvslY9ZQWVIGhr6d+MMMwWTpEE2OrJ6StURVch2XFrYmACEPxsCBct LpeAhf1OuhVi1jL0QHJ8tqND/80QdRBNGPcH2rJXl70c1zoouuz2IzvkV/VrFR3+CFq/01lC5xvO XxOIqsvJQOwYIogOsldfQfYS4z35Ntrm/ABAe2Vkx5Sv8KVz/nkMtOlmHzt92VlUq9xGNdjVjfWs qWRe7gcCEqyskenmCDviZkvaSB4niEn7ueM5mzmUuwRNaFMl7ndiIRF9lbyZANBzG141JycjUF76 NDoda1EEdYTbeFDQnV51FQaaA6MYqOWkuCP/3T9o4RNkNwYOmpyQYV4EuLw8taDPtRxdlPx3qFTt /aHyTmi3RNP3aW58y9oeAZLO/QEEryh/bRowkVC5NsrxadPXnvOtb/WIY+zW04gFdJsvE1v1Av+L Jaj3tP319DW8vqUoBi+4X4XHNwAjxJtQgl8vs72HR2ET0HPoTUdPWJOVDFSRRTi0aHHm4ulHEu4Z rJz0MMkYJMKymDrXIEEbYmIWWAjrUvWlDguYoP3B3eYCknvJBASMUvXbWrnBY4A3fUYe2PqhUxRp T18120nvLlVZR4efL0/fCDADdd1TsPwWCSY0AtzwjGPJ5qhY3b77p7WUr9wJaTv2CR/E9parBznJ R08d6nJTWPbT1kkP3E4Tcj0VmpGoVkV8X9xJx4cpSHewoWPrRa++bE5AMPHwW4wRU/G9zk0Js8BD EW3TfQdEWNU8fWzVlYb8BUcRflKRRvll8RsKmuSn1wOvaAMtP7Id7nMjBwPDZQKavJIq1pVqKgdk G4tt+ir4U7TBN5EXbWfv7WnIuYQT42ns8YYk8HXkWt/JGfu/R8vsNl7GS7zruU6TX6S04clMyPkl eFmsZj8VBVdNxrXiQI+5IBiveXPB/DVy1wNwx23Spx/qDSlmxBKWlOqOauLi1eIXrC55BbvHJqVN RLWB43Rv9/NFqg3cJgKzMb/TU0WxA6pODO0xN9DUKUimykk4BCuORwEcmRyvc3eXEbMFwNvKj9BO m1L0rFBon1YQHeQbyuI4qwBkQkM9kOJJjGfoFLShjWjjfXsgY/rXpHXEB1kgfdYR59h/nh7yJoNO VhtILmnd54joXwctXj+cFyX3T5UublD1znCOX0Q1GUucar82RgwuBxKSZKnvXK+BlHCZt2G8ofD7 dKlQSkclI8U8mJt09KjyyQ3gGu4oQeGV9TWb9JbF38J1PQ8JmljzFFwtUX9mb1VSIWik2DqGwY8U x8LknSge1dsFMp68KKnKQgHQjEvisJAKozw6OIhfAQXpG+5ybYi+GLcZxdciUwcn27G3+F2gsqf0 pXONR9/AYGjvetRI6K32fQ4xv85rxaWIC34zsw+ToWZ28b04+97g+OuNH/Tdn2RzFHiULSoCkEKH OcEQmQ+7X+uAkGo4f35Lkf5oYKf7x9mUk5y/u/ayP+PCPL/fONAHwN8Tmip1+iiYG19jCzTk1T32 d6GNmoQ3EY3A8lysWutopjsyF6YpG0pumY1GikiO5eN8oRROREX9tZVZVaS8FaYnpc4Is8XkD87u rMaGqHSeR+LsEcuXeZsLeJoYsHNMoVI6vaThA/lhW5jRapVgQibxRRZMJmy6VLqUbnFwNvpFNm3B 65BQjAxl9eRXI0+BJJ1GyhML/8Nvt1peIygwf/ns1pGtoEpKEbGj0+A7TnGfA5t25X4Fs8+OJwLn PxXwNywHR2f349eEjYJuCQvEYsmBJbg+/wVTh2lMBWatywTBcHh3dL9dAw1dc4ODICJDc4GOKLy5 0quGTfOWinmRb9yi7V/sZSN+dmRk8KRlOTkfXgdOFrMXsl+ROTIoH4xDsw7wYO/dspCJG0bQx0d5 /KEX+pI/NUJdBoM0E8Jfaqqn3Ie9KD947msnvOuCGWbel1TN+u6eQSWnMES2urpoKRwfvSvpBzg2 sGV4atKYVt0932MesQ6hll+QGk7oCr1dq5RSXSibNFDmrPA7w+GTc7MswTnxmNvDaOOqI0nOYuXK LPogBs4NQ/Ny07uHsbFXtfNt6OYwijo6HseHNl9307y7jN2gEHx4fBwuV0r99rNbGBvR8kPNCStJ wHSu6hwIlEwhvGZpjVRoeFzomN7bQRF0cPdzfTHQQtLkwESfeJaUg2wVzpLZQCghAXDv9dQ0VxiX fqYi49OcZCakT6hizABQ2hWxWcQAar+bYf3pbm8IYl2hOTxOh4TlmSPexQd1h2wJiOrmTCaADbVH DhCCgWxx025LM5rmQ4EvzYDQGuq6jGiAY6SM3NBC+Sy1THkn6hd5lmxQGa7xc5SfWW1jb++YDLQg jqpnfdAsMh336Nf0g+cBB0TL7QWkEQeUwQl8/dqm2iEV9ZaSKLvzs1P+ZsHqp+lEJftDtK+3AEZL +dEqxTbIa5C1DmjEmS3mQmwrS7K91z/d6JwYRSbfSveHUEQ8cYmsv3Mrd/HaeFPprjvaqiz3FMWa nh+aS1zXbw1j67fLuUnPNCSoITcngYebT5dYjnS/vD0D7Wc6pGEfrUX3Ug+PPgAEtVYOaJVfo2Wc JPmU/vX8BNvM0jPQQGQsFzmNtwcNRP/omZ6NMFlNx0fOxZazuO8dRZZ/Z/VPtJdoqrUPgPYx2ZEA Y5U2QDdX8ryyoTLBRYMqnjte9ptKp1nM58LK/znLjn1YVmeukb09MRV6PWi9Z1JWcYEQ7xM06T+S 5T5bFYcv92tsphGClPYNlJlTC/CW7QM/mAP/Ck2+kUcZvxkobkNUZmrhPb+0fP8+cujaOwbtt9r8 dWYwNI1WrpwvTwQGseZucM38BAwNZ+7nUy4uROB9zP3dsvdEenLcl3mf2wCSrYrsrVvmE2M8yWNw 3796Pfo9QUom8fwxIaXnT53S1tb+miN6xqUyPbnoHehc6O0ivOmc8eUGZA69ppoD3LJoGDT8dqMt NdAoMfkayMozBj30vMIwxdZdw6a3bpDCaDdtVAGiVXcSOD8q/grzJ4wCqZP+JY/d54QZou34orzw EFlbHzV6QkPR8YZ1swXJqdN3nDJpPN2fp193qDB+wB9+vJk+dBiz1HRke+prwJ8G548uxFZPaGdM H6kGaEKfD4+5SnGS2dn4yMma3GBFOdLVlTM6f6zRI2bFwohSPljL2XaotZOQDQdwVCxUrXPdj3R2 9Osy5gnhhWM4ABz1Hkuu7NLD5ZP3Gf8f60zZJqraVK21C0Q56UqiXngaSl26iOv5W9JGM5CD/KB4 2AYL6zaRkXjaLeFVy7M/X5q8GBvN1QSqlTbO86KYnJyRyEP7HtECJCXuTH2+DiITh5upUGS5459Y JbPnqnYcGYyuagrheUbbN7iCpGDeGPZUleMVIntNl+ZCUEW0v1CbftRtdpNfonGWU4ZRWs/D5kV7 criVMFzgt+8Xs3XVXmiHjdxs7+iaJsZZ5wCO2GDTmGwTBxg8lWO0E7K3t9BWAZ0XaVqf0HKKhwTI TQZCoUkLsGLGr2LKMTnSkQHyIIMOxFa1nq+kcAg6EJNf8TBw03FU9etQURwJFd+K5kmWD+Xa8jTL eJl1L4CEIe3tAKhITV13LIrQeiB72w8+bWkBKH8h07YmChNP9YfcUmOMYFedqNKttrNDqH1N/F9f bnvpXRp91Ip1LpOJoHf8OLZDnczUqlXKrUDVK1lUqfBkrfY5+BqPM4ACNQ+LYwZU1WY+cJcIy+bF kW92d5jwcjuviSCyyGHKj3IdPgjf4OEm3OkYRwB4tZhtp288ub1wiDAkJ8zRiTYG5tQf+itdEfNB 6Xt++9OmF2x53U82hSMOBmTjA0AgyeYuhdmSPON2eG7ZgzqJZTInRjDiK52zS1f8ZMp56UhKwzwX zppdxwNUApyunkLqlhYRzwcf1W6079tC8+9IAbMJS6dEP+hnLbJbw/ul7GGWVw1jEazkZvMWefsv 0JuzfAITYm4Xy3NA75I656fgeIv4tDBAShitsFMpSn63uFBuv3gcizQpALHB8vk6qRhI94CQ0nS7 YuiAKAgBu09+lKo4b76c1pxB54SzR7ZiUO8p4qAo0/zLzsiyCQHF4fHrBNnXVtvE6dKuo1SZbS+X wBl+gFRCMAE511+hdLFh4ypY+ddnAQH4bo5QIzfeRnRM3L3ofpu+td5dNlen63faHB0eojXw5cyk tldcIgtjoXlE9mGLb6LqSiPXzrLq7it9FBipqGMzgHck89Uu1VoVPptPKUrJBiBj6DtKq+CKrytQ ufB+LkBTn3o+SrfHDIQjy04pejcr6nTyKVEgMsIryGyT6sjlS//9UmF5uANsipmU7DfH/MYa43jq kUbiDRy3tYEhP85NvtEVwZh7PtJOiNKX+ndOom72MXBjyPzmAV0d7HQCEu4yq5uSdX1a/FNb/Lvi HHc3EZGA5MkNS1o7ty3i5bi9TtxeyExW/uGzReG0aZ8iqhJnzunYdGfJrO8zXUNw9VeZwBqJIMU9 c7ZZkbjCBVGrCmz+FVgbVRJgxyn2zooNkJxeCClAR6q2f+4yL8WbDHAjYGdqpSkPrpYEBIpmIXLa PTv1Hb6BOFXTo2A7kWcYos0xPK80NKirfBfxuyTf1VlCaoAeqoY7z0YcATmkwGiQlwlgafqgsF+Y TMCcbZM1Dkf7kwXnMDa4Wha2balizrAldc6GsPiAAbj1+mFluWMaPcDd/7j8NWqS6JDDk+RFYgkK NgbT3Iv6ve74b3Y8ePzOcJWoh7jm3wSk0+TqZSQAv+uDu3oxvMamJP4UvGLtZydWmiTTlAMj0NXR YWp9VhZL459fM4OrvZBZoNjc0uNILCQQUEl5OE4hPb7IC/NJ+Scu+cS56IrjH6bmh7c/VK9kXo2w zM+C0KCzxSsnr/IBvJCQ8xgs6U/OGQD4LG86HUHwU92iVq1ZUJiYqKbQgFhiKAxeVlv+D8BW5IED mifLmLpP/sb4R8vZBk8oWz5tseFmtIZAFlXT6sld8zhASkKPiz7lWX/EEOaeZfQIXu2Sc5R8JBqv zyBQ/lAA7iGbANGTM+baP9gSJRuEZ+uzB1dsKSwyx0US+yoq9jVIwHn9O5tD2zSj5NjV862SCY83 uJyFZpQTFhpokwrgCPLop/8aEmlmxZCoZzxUnqGodjFjKi+WVR1/1+8bcAZFgSuMEJTdy77trn0r N/q1EOTPm3nCgFBhWuyhxpgdEVm4l3KD4uiJ9yr+ERzqWlc3dnMt574vgvC7nLyAfoyr/6s7J8VX apluf7vydKJpG0VJUC5/8BtnxrwjnPwBidSUcMD44w1IDsL46bFUBlYgyCD2iicw6++TIBGQfflx PUE8Ra7KZyfVjwZLSjJbu7crXyn3+neCudaNkEAJHxm3iIQWhiyuTEGgonUta73v7If26haAWi8U v1rrfBYMmKJAdaWm+iE1N+A/qsg45MQsPk8xyk6EIxWh/sQD79LLyi59vzw9x4SAHgHbHEWgycGp ZnR6zl1vj4o25EeJde+X0P/OqF5E4Uw091OuEOmQuAndUL04yUu+w5gbL3btDo79zA2Eo57hcC6b 8xPf7AjLce0RPF9ppQ19PhiPeLfCZzfB8u8pFTzo4YuXotz4G9O6ky6zRZsB3QPVtaEBNeDxHPRc Zu0SuzCoAk/wfkn3HNXjdb9p9OEdAprq5rrin0/ek6VfdkZbEiXfOFy+9I5QdzfRW/SK7f5Yl+Bd Oup/+sivVDkcx08j9mLSBmKVXSS0ciYnZiUTvYotzuBqVlaXalRmMTmNKJ8cq522cEwWq1zQXRer SUmmf9q5dRunPTR46HSDSRBQeD0tDC/+GSDL1DcR76JjgcXMeWrk2402mimC5vBe1tPcGSwzJ/3L s38ttQkSgculGVsi3kLK9+TbJbIEnaMM3B9pt2IHpDZiOerUiJ0+NT+QGintVCecT9SZIRHzv20w diXkEKKHGA4XJLOO87Btv+K0kvaX/+VeLZwj7ba10b9Dq+FFzQiRx3SOxlCu+0MAWnzjekImaHVY xQgWJLk+bDDmwr8Hboec8AQ6fOV2FonQC49G5tD8oLNGv9qOYHCNQ1t1LNY9EzaTwlQqbi/YImQh FRq7VFNgAGLw4pMlgGwYiSCam8sVbOracj/MoDmYuafAF5JDNx9UBvP2Ushs8HCmZU0+ppF8RAZA 0DRkHodKEbFwaLeiC4PdMAXwFLDwFe9PUpml6qihAmYcU5Hdsy4iTuGJizzMz5bokqVJZpXla8wq DAbQdJ0WlDwb58d1XQPWIV0nIUTK90K46argPOmEjAR9uzlIMk9BkDEEZIz+zX62u89R+mUXBKuR fEeYjY4X/7YMK9mU7/DiFgixYPBAHIdULif9bq+vECAGQXrOwXxA7UyiV9iXEyCd91O8pRPoYWby DGU0AP51Y65WYjrnIkS01VLPcIXs6tcTJNS6TK5yRu5xB+l2m/+SGQGApcbaWNrVKLX3g6lyysk8 seR6hxrFWvteCr/EhpRrea2L5KLfIS11NEeg+cmuTm22oqG0dps6DqlmVicax191VFOVFX2ZEi8l cpUthkcWrX9POR6qp+FeG67DA52E7aq7qhoE/NHaw8oP3U3kkuRLGWcHYkxW7PKKECCg1mjCwLXY wRhjHXfRx3xV9aMsGWuuC1USTz4/l0x9cwTCm6dwDTSpThh8oU8VY+MDucVoLMf5sUd80qIlkTzX I4Z6bVg1FT9eiEP3kDaVeJXRmrBXEM3Rp4UbbU/MOX4qiuuUkRcuwXs8ZgUCPaV5P1Gp0W3kZcqI DytrlUoDAyWomus/e4qWZ4O9xDulA4SBH8TzxAWry7SBnt4cDhYUfwMfBm4hWILD6j/Jc6RgVgUY YcvzVMyiD8UV3GkMo+83xF3JM98yuwu3XjdcBszcRuvoyzqWkhHZf062ahAtDM8eIB+16+FLgXvt U8sXpP7iQsBOgwlDe44AQNl6ajd7qPcQqJSvLJ0GGpc+Lyn5HrqQpgg5HL1PqqXn0COpllPJcCKu s3fAvBe7WaJswO4qxa6yjdqnxwyz5gYVEH39AP5RMDeeRhL3VMwAVD62Dj2oWlIMQcGe7zvH0CJ5 1yEJGmUJJ3BRvY2NPUv1wAZLNgNsgtj74o8CyotWXFO/VUGrnuqNgbfFkS5cEP6MA+/Pgklq/JGP N02tKhad+uz6FVOaYWcqfnCXXKEqWZttgdYzfjSqCdXbLbT1ExMbhoIxZtJ9Q35MLMUlHCRLIJJN 3IoZeP/suR1wBnVaOQFcp6hSEQ4dn7RbHKyDAvNRa0dOBBP7TbUclRxJtvMOkP38b87ZD/E1oqfM rQsKCJLaDpsK2c0VwJ2gr72WaQTJEL75Ws2OqLwHVrzJD6O/fmMtxwgX0zq55Mawqh533t/ml8bX C+gKcGjlDOXsUoLjFPa8tfqLinNQjwAgRBsVGwC4d3TjCQ0PpxFoplqyc+akqn6UEOUP2e1l22+k HhubU9xlp6TjIkFdzZwmuXSzYJ9+EjLsMnCoxeJprraFNhlx6ovkZfC9dLezfsv0Bkp1TleGVhD0 k14XrSGQPxbW0bGKG6Ndadk2fs6w+Kr3pNc0t5+FjjgSdQcLVLCFWfVMYa/iAGqBtZW1YBZeALuF goff3YA8OQ52pdFwHthJyAHo6IhenabTFC51LAv0zyuI+W8oPfl/WTmRPW3vywtOft771oHKcygX DuRmblMELYCjj6dgsKBhBcejhfvwvzUdmhfiYYr7EtO1D/esAmfWMSftiX7sx+BK9byc7eOhxfCV opyE1LsiN6Z9FwUCxEAiKHui+LkEvBgcTOIFOQs04Dh+LVkYoJyK1wwUozb0TR0W54oMdz7qed57 g3423A1K03JRZUiJWMndzA5tcki/Xnk+ZmEk5oimBswLMVkvLBfP2zUp6QPrQ6Si2vLTyHGmOavH hD0cIIMo0mARzyqyxWz06QIdgz7TsxELmsHS1FeJ6V/tZTFKD3/zXV1zX7WqvXCretJB/WAqJnFC Ppz7it0QxbTeI5bUa9/wmWyB24EXDri++MxV01O2GhZEN0t5YvpLDN0FT7Q6JLq1wQJHxjZKnnZb RnmjpHuXUYJggxobZ8qT1iVcHzsR0l6aUtwAqPgJgXhMno7OaNldiW8LdnbSw5fB2TjXnY+JClzw 55bKHkCG11cve27sUC/SOXtNtMXPThdVAZxJE1zupxtOmscldsTIBUtpYdUbRr3gjQuj3jvgVnBX cZuio3I5XiRMNjK1crZDmnuo5lCUTQvdQWsywGW2GwWh68Ay6rkXrJraQB+agkpbf3KUm2KbGS38 u/UcEyztuie5GIAc2fW8c3Ia/8uuS4D3Fi20zNe32HgC8+DIPtZocMfEtn/d379yPy8xFoxcYej7 Eficq1tG8oi8pGuMhK2vrgPw7a2DTBy3o0mLEFxT5Wc0ubC+nmXgHWEzljFcTc1wX+kL8iRjITlJ x03R/KyeF09FUIRySMgIBni67A/RPiNoDxYPOE+pLHYdRe9QyGP005dJqdnP99d7iKriwwVa8FA7 VLMoVJHG7XhfKaDZ1mms7dXgwVlXOP5Z78P8AsBAZE39XyQCsjSFHOWBR3Sx9931c2Pjxh2FLfjf sOrG++SSUkq2TsaQgS0onbT9IC4fXwTZqVbQBILjl0WTMvC2UFoW0JP+ppi1eeUcEKHuLWY2kAUg tnE2poa7xZiPJ4NEq/1i0WOFeoWxRgidr5ddBwkIrS1nWDJjnhnUfbmAGHkWlXoJBcXqdyTlh1rk MEBHfYj4Y4wOabd8hPfGTgIU+v1/IOCT2O7KHhpBGsh70ySW/uxuUYpmDs+L7mQ/72ZvpnPSLRpV /s7btX7aeQQKhBzjb+g56J7b2twLJt5O+/5iM6RK7X5ylHPvACLEFUlyHuiAaRjQpVra6amL74uf VCME6mQliXOb2/GWlTjKJtIQ6BLS/paPrSqjM3vTqDsVerCiRHlbwwSiiMZOUPtt4kd3SmorQrT2 3K5QrJKD12WAtDYvhnQOnyteHqixrcl6RTqRfuW9CNAUWe0FwnzwHX/WDHcO+0rFQH0n4cx4Q7q4 1JNsBA0r6nSoDBULqfKt9Uqw31bD3ZMZK7dLrB0QkjR5ny2QEGiR5vhe/1i5yBxU5ZTsZwBpaH1I 57KXD707Nw5elV5MeXr/8RFkbfj+aaTEJxDiYV7ZLCHCnkoBnmYMpgOYESAiRF7xLmGzQY08oXgu Ot+0rMwcFKvBt2ToJ2ssrJ0G5swdKHindx3ZPb1LU0BnrZAPCfAgsVAqHDec0K8KpKhFPfs6MpaY NK5KVZdEeKw7ykNJKVMiXzTH7ygtZL9HHVOD3KFE8FAE4dj36O4WLJDdPiQZ/To5dvumP4vFfAw/ wc20lJc0jUdTj6fHWgoiN/rhXzsn+iVRlf9NG/dfEb8ZEL/rJZwaeo7GnN92ATWuU9w86OHqBb7x XMbPLxofN8jtocm1lTlYf6+YO0yApztV51mbTJ27F9SYeWFpo6MRy3K6xv3pQ+da9G7gibFBiguW XcOn32Q/6MAKK8hyZqryYDCxgtfJc+WzbhWopXTv02l3OjWOffZSt/4T34n5KwyKTzdjzyykp+4e cuy2jSH9WL5L8BZQuS3eI6o0SqHYi+2J7xOKUkZpANO5kKFZZT53nunDWRDFPmKIjhoqRocTO14A C4EKT+ebErX1dWeEQv5/GR5wWC14PMTSSTE0g01ow3aWz6YEfNPDfTtrHTk265oD52TA9xDOQxrk uHwYdjS2rwn/1tS/BDhiOoHzd+Rc3DbVTfOwgEUAhA87H8hnKJdVgvzM4lwqO89uLXDWGM5JcUoI M+f2ZRMuZu8dE1vNhC6BCZ9QI+L66s8WzDaV8mokJUmyPwZWOPXNkELzziBNY0pnXJtYuWDQmFFj eI5tU3uNv1GzU1g7m7j/mtTY4hevdV7eaSdXzZXPAXlv76CVY64G9ZnmE75wq2CWnWjNXqTmA3h9 gzWu0loru2Dbc6UPHadV1WGJ2ig6MfvJP2OrpxrHhA2T7de9PHUCu1Hw7C8aYEF2WGzQn/gKRVg4 6HiJDTfujmiZWCLy36I8G3rk5M+PpkcB6h3DQMD+yxk9bOQyLMjuJaWh1I3z00SdKp60oTYe377r 7obzWft7jDbcgwgghOLUqkf404BN7UUhy5O8xtsIw4XVv6CknF2gZev1XieeP1cdm3t+m0i/PHLr N9v558jfQOvZk7OlKHWCdNXKPDyUu+GLKKOVMyb7Ku9UWL3kqvwFeQnFgh1yrXyGHq+/51iG+c5U +Cqx9HMlDN/owsckcZwyx4vXsVnC3fYDAyb0PaHtTKlTvAeaV2o3K0/aIy8+Gzg1HEo5QalFOPqA VX9GOMspLpATF9bWsZppJfT4fB+LbG3uMSQdQWt8fgaKH/x/LSGWIgLFQpanRT29B0FTE/siMDJQ bVInDTzr9R5cis82ryi+Dm6EFSL+x5b921hX5x46a6pCfdV1xfw9s9uoQxZHZYhbGcVyC3qjwCfI qH3gGoiX2tN5Td8AYhOXbpQbyAvEzP4pFIvOP1lwxzcVgt4m9spsFsc3kNDhKcRcTu918Aqvs9FX 3bgWMJDX2lpwaEyKb8jX6h88TzIkg57C2uMFGLXJ9uOh4tMGFJuWhD74qdzqtyIwIciLTjpogzxB JwCXm6Q3LI27Okw8t/87lk4hDhZJn4/xqMRzbu8K1T+/EkMiwlGnPypntMnYk5C2cVR0sEP6r68b RTrr+nmUOVIl48nHA8Xy9fCjfzW/L+BSPsCEBImQIVKrpn04af8yvI+/cpak0ETgmnHDwsLke8gD iCZPRIkoZHFnhkerr883jN4flS9mPM06JxMZ+O0M3/THWg3O5GaKTPBCcvh86KJuVpae0N5fyGyf w/Z55o2+ta+77FRLGXLMDPhcHkMxOvwkiFrbBcPTlYHoHd68AkRGRo8283SfFtpKdwUs4ltbimNo YLvUWzLSTgf23krIotq1Y9wc22Pn36p06KVut8oCs9V52NvcFBp4xVKvxILIpNUlJxIJYgi8BjL4 vhfbv34gG16VdYCpWQpTW7VI+40ACAanfMObAeQ/6jQPS0Y/+hBTaZQD5J1xt/eovGHRPOHh5quh WEzH33Nhs/jykg09ukLROqpi0WMVYNCx/NStcB+a8NxeDEMW4GieeHw7KH0tHJH/kojQTPFRHs/f 6oJtFcvYB/q0w9Sr4/hzqehy4RBc0kxkz9NJe9galkyzVJvMfo48gFq6ltKfSqRpUh6Tnb24ZKef +IxCAZDfZG7BnoiLYU9eP+maXKsMqZJlJOIx1jNKAxwxDGKeFSlCuQTv0at3dOJpJTp7q4sYHiVw 3CkIwIH4Ata9BQYizXN8mMzesI+ct7Vvsg1dthqpLGLk5SNomVYCZCNXgsc4UqOmg5nENAGgMLPk 8HSFFb9GASSFgUdFzy1FyFZjE1B8QRZJhPaySoIO8IeK8G/ABlN/k0/9+mGYUJVkxJXoERRfIQ4y X1ldtdxurqr15PSzcrqwUAWx0py6UpzZRDNu7U64JeoXWmMhISfniL9TLgWGUEs36ShA1SY1+d9f EjFBl/fzKt7+opMVfEGFOFt1YM/grz3peEE7XKUYgQN81hJZvK9DLqiZKiJexEMVzyzNpbDw2J2/ Q67O9ksQN/sncT6NTj8Gu0CZzKwfjzKeZYAt2MFiNdqUzAhw+hnfHpdtpPgfkzbBrisfLfbzwjGT mtTCCysV3MpXQSx+7J+dvC/eqYR0rMJJAqtfS8UiHZwp9K0ZnGe6wXG8INNcuIJVhs1t7YwtL7/E qgTXYskuHC7wMm4zLzc5d6GFWGfWr8/ufRMyY1iFVE0IMUJ2NtQIQtB7RKL37YihZeEQ4BJPdQ7y 410sxX8Dg8dLGWbkzNd/2rfdhAzjiSnxahlc9vR9WcVp/uBbzprys/AF762xTRNHgbGJ+kY2/Uox PWlcEuyrPeHXKHiKPxSIBGyOalZ/WONSgJVemCf5tS43CZmiNiwPiL3X1Jk99NagV3YIWtUOxLYC nOhGkD5vcyPikuJLA5sCnKVjFA/jtUh8PZizB3dRYXa4KEgSH5Jx4KT9oLo/Ixtr9FfTVLrEgYJQ uZj1BnpALzYlqun81Pk9pD7UD/HIAbqB5hza4nch5RdMF46UOYfoNG5OhQLkd+tAgtJ7hHEUyB2+ KRn14cgUoRH/ZNJ+b55RhjhHTcZztSVQmzciAt8px61GZt99bYYMn6EVlVuoI9AUOAqsJ8YwSWe2 kGYHzGlxhBudcdtlrUqzWSvj6wfRK7LfSlyF9wApFp3CLMNZzEedF9GHXjS0Gxe75r02tHqmzi4V O8bJYZEC/wVh2wexVruPeFdtEChcCPeZS3IrHzlvPyMh4+gqEfrArCdE8hC39Lc59S8JdeNM+uaG 200p1ME2NVndGLPrpARH5GTZW4qJivqrNO20ppv+n63Rizt9OaT6dd4zWud1a0BujyQWGOnFLmHH 9xsfXEmv2LBNkFRBMH2iRloYq5i4yeKrV8JXG8bTyoocH/CHGx7+JvRS3+022jf9nJjYOYkwLNsF laWpgWbgvf19g4uWZxZXPAYPok+k9G/qUWL1F5AExQeZh/5neaPENF85xAjJbzEYm5MzxmjT9DhY 73nRaisyml7QFVge94tOJChmnlT8cUOkxvJgZTUrXJ144NR/gTufnt7AS/8EZBICgQdTOEeC46Zl bpkwRWD2PhabTr/J+t+hP5j4jn0atBbKtQTR6KZyLBrdMtOb+iZCvy2d16PaAU6TEW+MsfdjGw6s TRM6MQuiQ7kW/wv1U5BAlmk9bKBBhkwO4EtF4rfKHp2bIQTP8Ke6LrBgv7M84mbiIkV5Zg62dAg8 3NpZnBp0Xf+jBzT+m5CnY1v06Ma3EdCbNdpgpVeKgDVu3tR7rFHzaaPxbaRLqZdbgT+YaJbpFtJJ cTwM6N/JS35EJ8tVw6+yMJzTYanO+PYiktossmywcC5z0dRX6DSvFBzDWK9z612SxzVfL2ErwpxE wlU111T+YS6YRObstgKvlqYeSCacN7/PCmLJHDBBW3dvr3R9wDzYUOqN+2yvdNctGlSCJ39KchVV ezg4Zia+OeiBgQpWIblXN7Zdb3IMiDLIH94SpomxYYkFZ9MqCvs3j9Io/SsU51QYl407zur13/D+ 6g7gz9gT8//OA7cJW+1KfU+gt2ln6mJ+i6IE6alvjUS5c9r4kHvKSN2Jjv/9Sq+80mmg+Kd1fcrh 2tyCbWb3I+r7EPUZXaL1As8gMwEOMblrqg8m7edkKi6f6ARF9Rtr0sKG9ii428RkjsMnxIXUDDh/ DiEPcseJIlsjdngMrJk+4xxrfE9dTFu7PN28X5PV1WuP2VQLmXq8AAYQyQwbsIrKMgGdo00B7cup ERXsO61/sSPfwo1X5GqUMs1vEfsasLbK3tpGW06u2XsUTNBdZKtO+8xIKQHjsljmsNvt7IKDReZT MrGcdr9wHiU/CaDDBy/uWaHo3SZkp+/z/4hmtVNuDYInLpdTxMW5pubPuBDHcxNyaKCmQ26WurLv GP/IZ78nxTIw3mEDygf7xikcVK4VdGJCVrHcaK5vR6J0gcdKzgeJWt2i1bbyEf9kMu6km3OMXEPK KsKvCMl8mapW9wxmcmcDocZpKPgjntXMZQhtbnR4hfCsw7vmJ5R9Nh7zbMOv6MNRD5EF57JbMBSQ Wt+dF5PtusF1VYCnnryd5KWuM5RQ/aV3jHqqB4YJ78yDq5LktN3PiNoDEIJA96nROPQ0Pc+xksDS JcK9+ZH7ckmb8VOpN1dx3C04dd2Wq0Eq7LLIltpfPS67/fm8iknUuL5OqE8SCKRy6J9gVkWQvlpr QmIXxV7bdyMraueTES6C4KzEz5HywTXsG8BOOqiv3ec6eEigE+PQ3tal4ZobnQIwM72dngcnyLzp ZVTFqFXUUid7r8QK8VnIZqQYWZu0UB5zcexsm27+GYmnustlt5kJNBpKBCkA3u90ZWx9EjQ6uZEF Eo9F5MGmD5G7cJ8rWgtA75Js1Y0aIwFR7FGkJUuDwpQA4MtSI+32f+fhroqFVER1IBiyJVBxyyzJ Sic2EGsuJuUOR/hKvSiNQAoUGOUY4wrwozhkT9enGbLVqa+0uBRKWbE6AfMMNqamzyDzRmwEwhqt EGhvyxMQq41eDReMeZ3bX/k/gxz1JL67AbtdpKoj26eOb3cFOsUQdLCZuSZ+tZVGZ5923n174YGC q72EYwX6NJ6jiHLvZToMLHKQBZD4rOGCciCG5etf9SLKYf/LunsPnwo7epaGgOJjeWyUH5OGrRyx zH5rB+cAHO7x1/KCpIgsN4TFG76hrk4BRPW679t0maUZ2bBhlDlAIJWiY8w36PFIz+c1JPmODsic mq5UYu3e/t7Vw/Z2Xhq1h8Vju44lmvXxfWafzrL1a2Mxgvrx9REH7sVQDMEK0afW5kcUWxL22SHz Z4hDbB20p5q31Y1psL62w5heBZKMuK34FSKGH5SdjBhl5WlSoqx22R+UhINDSuJ38mr7C6HZFJki ZK5mx0fRL1+HHPENOpoyq8KNH3O43jDoGqKwYHdoguQKyNdtbbKXQdhVXa202mV4HIBEag+NWcJ4 hwqdMxsR23ZK9HifCSKVEWLsgtIZES2y6UJGFAXlfSQW5Dlg/5xrufGgB3bRlp59rtr3LHvngq67 oNtNZU/ZhnlZXh9QR8Si8khmxXD/L+L2lDrG5WsSSHSed9yFVZ1y2Ak2Vm60g77DziGs4U8BCluv zi/C//kNl/sULL0Z1U+EQiUtDUNJfbT4vV3O1mYmHj0CySjBvqo030I3rGvi2rkD82OwJ034vvoI aP+MHpdcXUIXj+RejRZp1AR0ZLaaomfyw8QtaY2QvCEvWNFPCbmt7pE3rb2Fs4/B/jMjGDfVSks4 +LakuIg9Fb0inMnC9C3jylmnHY3HoinwZXWTMMEuDsqF0YnBm/zumQ/DgDOyiCb9KJXckZ7sV/Vu BiA7O2Zq8I92MxgChOWaYKtUmxJyXhHqg9yj8ds/BvX4Yx5Z57xAUlYv1fR4ntXkmaUFRjmh8thF aCVR3QNWhzN7HOdWnZpSstMVtNhJNBjmkIepn2/mQVcnfnWL3juD9jkkCJQTKCtP9IPxWnwT1AfP P1QvMViTVyyaBWiGb56PCMhTov5uRtrdfCWMZVVqEbiH9r8CPsQntOvRqbZUQGYZfYIXlbzMyEOx VAxu+n9bakI5TjealChM1gUm41vGAWlCPgQLibtVhomTsUPHl+d9XM7wqtDyVKZWfxZPcQ5d2izL r7xcxqe4BvSy13v7myPkNLf5aDmIB6fIE3j6HaUCxvDidO61CnlLLajNWmISUHNaownx6Y0zGAR2 BwFWhlv3V1i9crCq+jvD6r81FXKbnozB29NwvzqTZ1jg+FHQQu2cWR3XyNul9yeJova0KxbZ87ry KJ9uLHGfewbCPQ1w0gjBa8KuD0nNsmBKW5vcWlG3NG7NdJag4ZojIiliVVnVMvDD+ERfavr8YokT MhyOesWIT200vSj+AEP3WYtkKJlgejRu1S0t/XRi0ILJ1TzRYNjPn4Qf65xgqDGeGf4yDT+VB+g+ HOunfQyRTE8okPV4trFkIa9oq9YtricT52RPHHJ+FFszh5Fibpf+al7xfWSppj1BUHXkt2HaCA3i Y/++q4msu6R4kQK2X6t1mRZtTK5MjyXmghCBFmH9cbiRuHfQF9+ZLnRjQ+6ccY42cRpnXpm25ndQ rF2UQuTHy5VF6J9cWzxeQ4Vq7JCZ25B7j4AQTKhk28SWVMmRVWFMEKWJ0Gql9lcX52Qp8j+n/x/c sBJq9giIpGLEMMjEeGuFX2qNPYV2hNyPiRzBATmDhEYryMsMFXK4jruNTSvenZLTxPwpDkCfSToR Vt7l78rxDcjOMP57Zx4RDBl8BZzhAJ7A4hzk6I6upRj19r7Dh2rP4IxQiEv8lidVCtm48nU59hmy A+twVT/D4odECjDa8BGEYxScQHi61w5kByt0pRlQCMa9uViZQ+l4044k9fISYesFmpmSyVZITDQf bKcxAgOk0OpTnAx2iSwpVRdQwartLqzMztsmPsLtCd2uRlAMz3E/YlFI9o/b5opXm6wpc4i/6ZkI 2unvT0o6bqGZ8QfxXHT/7/cAkIFCtZKSTf3FfTx/IbePZoxyvgAIZd+XLQ7YZpxi5PIKk1V5re56 dzZbiOHSJQMEQSvOKBjKv48sGi16YfGdWH/HWVEMyy9yNKknza0dgGhXb5WI7ilJd2u7bIZoJ42r ONttFQjlz/snqlu0+9JzkmICWj+2jCb8aThK4uNbJApggD4ZlMEIucR64wBKwOCLfW5sQ8FBsBXR eYXSjVOTcnc/BqfRJIdyNE/HnZslDalovXS2pE0hAn01vL4uBmZXbqILb6p0hpO8TQIxiyUkzgyD ShsbykSeHYUY2DnmIi055jzWy4rVLI+mHjuZ+0DGgt/tLUtdhDu7AjkfA5gK/U+xUv1hBfpM4w0d lGc9pXSqaiLtBLd8pRVYEUhrEv5sg6IvDYXhyeh2hAqNyDKs6CXsn228Q2Jo8+4Oz8cS7hEOPoZ5 awyVq4XO/mEKcmgKUVEeEkpmPHsIOJcsG1FfWhTAGrNdEQOYALih0ycVW/yDprprA5yoF9EK2/J2 c/MD0Dh1rE7k2BCAJd/d53p397ibiHUxVk8X7w3LFA0q2ySbmYmQBl7CT9Yc7mfLhy80PgxbsYYO JCy23xi4shUO+fsNe2pjDLFwKBlLa9fIfFLV9I8aQFZANEGMNtxnHt0wMCfKvlBXbDlRaufNjJHf gVRFWoadziIszumYXGPAZiDG7ZfsAwP87uCQ3AhXV+my2mgGazCSKyeUASLH3gjDhQqpcabtGvEn p4sMEEpLB01yHamLBDZCXwByDXhKQ5jwzXkGpP7XAwVwNR6UOmGMMXJPOdjUXxczqr2hUgqlkO7r 5a1Mo7EXiSneRAFP1UPIad3ILV9GszsKmMOopfF+dBfLFWJ7cHvxIt71moG+LVmhQ676v0/+Vtfy kMPz2bsZv9EBwfZkezgcVt2fzXYfIAgsO13VYcVX1XenEPMU3A5p1poJUECzVhNdJUDF6q+FBaHV OFgopWOzM2SThNp7BnbkgTCXw9s0Um/9B1MoKLuHv5IWuejjMcNMnpxJlCKZwqDfvVvYdiGyckW5 ldQueiDmB9Z7rb4jrqFOondbDeyHON+tsW/QqXhjJK0G61ggyd/6rx2Gpt3twHAHd4vg0ZQnNjbV n58sY4F3Evrpjzm3ANfDrjLxWPbseP0N0UqISTRrWfhw6iLEDIbLifcIqYAM745sN1GXl7nGvi3U Wul91EYt2zVzm1lpTJ/le+JCggCQOhrp+buo8Edd94fS1LPy+cmVNTb/eY8OjyAcjd93m55zRyzR ofsni/n7VFKiyhaoqo5tgmIfzv8bDzPJYEpyOpfB0VjaX53X3KVrQP5Y3UUkkX3LUPpOaBGPWwjV NEq7u3uSueAUzC6rCzUwzIMpfpu7/vkUV7NBhYq2T/Q0612GDj4qz1k0o1F4WWZN7gKH/iwA5vmX Kv4P7tp5YHMbfcRud9KrB9rzO2iQeE+55EosSc3DO0R3YpfjFRPejkThovSmaeqFtNCGAHYRbIzi DbwBEqQg2dXh7b1YL2SPlNvEhtG78f8f1ezm2cPhUa2m71CqpsQxeQ+FqiBnKe/ASdHOZN4lNCY0 Linh+clHCFii9vcFV1rc6Yzf9bRCev3CWLdaP9MgTtRQJMkBKpRY7SPx1bj75bhSObLQ0keWoUcK wrfBuJaKLJq4YdRustBxWd38xdh6DjtaaU+MDamr+IJXlXq1i3bvVfMCt+YurFbbGq1INi1/v9SW mYeGmV6z9bhSISNbvUevygjl/x+7V4gBzS4cxDZwx7or5qQLbFWwZeGuvR4vgSceGoGe0fjRe2Zl zsDLlm4qxKocf2dqNm65A4R27yPqIQBr73YNhotPLTfDMgzdgvn+ulkKbZ3W/VIdyVRuVBXeBCYV pxqtpsv3pHXapRZqhFA1Qsm4oHIQsWSD8HSdKiPWg5t6Vv60Q/ou3pvcvmkxEr6uV4BmPkeqflba 63CkCGCFdtJA13l3s4lv9OrCqyQsRBQMp1nLc0VAMLn8zCo3AqXlSnHLX/gyQqSZr4cZCd9IziHT itpIJdo6VV8rJB2lDgGe3rta0SzIWWf4Ye92UYx1S7NkXhQ1OF3H9PFi0jOm8Jz3SFiP4vod55/z QjZKE45epwnCbuB6NpYfyJEPiaxz0o4hrPBkwEoyX792CUEYzvTDxD7cCimadusgeBG2iDpi7T8w 3yYMFrOC3lpVH1VFXRYf7SFlJRr8HDv/WSMd10xS6YZ2LEvvDGnAfvW+fNptJBCML+qoZ3Qgm3MJ /5h5tYXNub9IxOzJIT9rR2GV8J56kA/RhGOlE+2r0eli3Ud2C5Kt2i6cyDBriIZs1QQ0PeKftrsx AS3qhwHg1Oz0Vhl1R20NmMjrWgIcnmgLJ2qLopADbuSVpQnGLQ/E1FStiGv4BT2Ad88OTmCqRJkB jWgvlfK1xspx+obYcrNR32I6tRm/jZH7tHn5Zz3c45z5QNIBBCZrJ2J3aKXBPT94kqiInwdBN42c sVi9RhPO6dlFl3CkI6RcZLvM6zWLmtonYD3mthDXtuHbm+kWoci6acbQdAlREhble3N0MPqjNUNF a6iRy/AStHI1ysLU5DRhuqphOKWs1K58Tiv6Uw7v4sjU7RywV/o85of9K9oATRKt6OXqhow+HRrx ctD9DonSYnQI1F2dDkgPR0mHtFs9RcOvxe+IN/Ue12fA+l4+z9GaC35VojZqHGLhQ7oPr56ifTIo aImi4HZqo8WEK+aXw+h/X252m1ocW2c+93snsH2b1gOSecU6TZkbMuYt1WNwiw398wXTngI2a85j LjZ2ez6TtfTifpKoGcYsqNFq9je64PXep2lY2+eVKi5Mn1vKCo1jeYaGP1haXczhOAV9XhjG3aIF wEa9in8eQJKo/FJRjBSue4Rrh+pHL+dpwJ15ZtXEgUUKQkzkzOVZxJ5NmlIJNuQN/lA5MjqmxREJ 0SR5TgdZ5rV8jp9Vb/5/ar2HWYxQeVXvFJ0r4I5Te+V8tISGnWcLtX35JSB7wn2b9akFxylb8m0S 33vHtTK6H7qKB06PR/yw80VfTIGXmDe2AQIHLzITgv/hS9Sc6DI9ugTpuAKvjCJBFa+HkKf9+48L zNpPU4RK/gGfKBUzRuqWVaCARBTLn/PmqS4F4YdmZK35W9A7brPRurtjfOCaoy6F7HlZGjxd0glz 41xDVgdq8uZ7PwOV4DMPuzIYqYi4fE+65VhIJAT0oeIorHrUzw8ZmoK5J3XlaokCzg0RsoFY5AfD LhWH0BkYYtuXehcuG6mv/7CTiafQ0+09DA3d5h3wy69VivmvsTYDf6ZQv3VZ6w4dokPOg5IM0ovH zmX1ZwOpwRGRgXMymoiHHFRg4r2gf7LZPsydUcPk046yx5ZTzGpqbm3AUeSke0HeZHRvqei1bQc6 0vm6F14GFM6+opJiAhua7IPQ2aMYWG0NxzKIT/oXQaqrWWfPnwFgOFfXqc2spP1fJk+wLcgKpku8 yliRnAzPymYseIrrkeum1YOJ2lklwOUAFieGMe/KpVqt6Zqm3flNi7uWe8uNlHMQSXjq3NGH2w2Z 5o/CWXu3WfitF7tsy1kOEQZZw0eGl6h1bwGKh465I5WPU2ndDHe7SUOYqIi6Cyyre8NucUviWX8y f3Bn6XamCmqBnJFb7r12l5qm0hdyIAj5qUQCuw/9SxvvQdO3xFTo2JYj7sHG3GiKTrbFBDQGR9P3 uAc7ryhCEUaA3blozlZ8PyDEGV+9inIXgJiVvdQzvOKXPYmGIGFM/KCiRC8NYPcaLF3tKVt710Px 6JAGDUFNKuyy7i3blI72qEXuc+EsPhWu90CbSe9NC3K7pPYgZ/u9BJYYWAFgIdZ73gtwXRTJpZq4 3vwpe6CQPC9hx70yF7jkW3Mv7eL93zaHOMqdk3p26yEGDZUK7PWmuOzQEgliPEj7CPtWsC9rVZpy U2wp43apDKSGTl7V0qhIAtBt3dkNRDiGKfQdzZ+siVODDMRrF9HUKKsjOMeAhf3NoKPk+Oa1LF2Y 41DbCAh36WfhP5MRLOMEuYsfo2lI/f6PG29OSLmdV4FTFD1+P9pruRPbaJ3Q8FGoCRva6F8YxwmB jgikT/WBw8h3tnxsE4n24Rayx7rVLINAOzMpsGy1+EuX2s6KYz8J2AR9902P7P4sEbe1d3/+rxXk aALLBv3vtMwwd3IefXgaU3lcnRDITQIHjjOJM+0RFZrkxEA2uJeyuBzidRpahjhO4LLjnx53fR/K fhJvFzWhIlyPpW5aHKqE3eUeX+teBpYR1AO5nOiZjHXPZ85zXCKkNDSeAx4h7ZbDXNvxj70S3cPU fl7cpPj1wSxZoXJPwIz+hyUiyGTAx9Z4bvuRJmg+5KuocAuP659hY+gOjZvL1aUkkribaR2gke0q Zm34ho0duD+J+yl/L1webJvxfhGYjvnR8Nlr2chElxpt34U+uEbq2BagyNd56zHPMDVhVzTR+N5g ZLA/6za/Hh1xxfq+ASR/dcWshawHff7DzMnYlpe/KfITRHZ1Me4L6Br30hXd7td2dz3KgtWp2nYk 407/QXpJKpKnzcDZEg7Ep8MUFrOhb6pn/R41rDNr1yprNRxiZNgd2RPh6RQHPyLm48gT1rHXUiPs w023i/kCuZ6I+UndP/no9Fjc1JnNiU1ywBYw1CmHPMDiVk/fGSborfZH8MMEzd/pjGuBNynqa1sV MKgil72hBgH4UR4cwLkewNw28GCuzipj7F7LkA1JuaA/CwAhVoYjEuyOxV3luLiKcEnIIde2OK+D L9ddzvVQ1tBXY11NhTkRG3IzGI6iB0Ji6imY6SBgv8/temSD8AuVwpfZ8CGzXk/VrN/EIoUHR1o0 lpYMcML8GRUsYbQMc8tvbAEVKFO3G4sVluJuI//GrCWZuT5JIN9rg3beS0U/6Uh/FnpnIALCiCpT /qtPUL1+lxsBVHgBwqCQrEW5TpZl/RAA9CoGHSPvwjhqM1Ce0prn6negFWOoSWLYAvHIcjupBi4R dKAsNQJqf6Um+lsvWazlVcXVpqWx8SP9UB6yyS2vAFsoOPMnNQIK9JGg/CrTlgaLUl6Aylk+jLW5 50tTauciOMnl+158pNY/9I7Z/Jx+R3b2qWwdfZ2pserQPwzV9JaRhzn7qMuDoZdfATq8Rl1mpxYB YhsYviTMdXQyOPHekzssc7Zf7JIerBFAnH7271+LV3GpSDM6oIO6ifH69o+v0c3GSdXsCnzrqE+h XR45Q2xEkHlf6ycCv04IlbVnWW0vP3hC2x7UsReLsJmN9bqGFWg195PDK2PA3kFGUNmcgnaZWCdY aVLVI/O/Fdt64E2liDpJk7+WOOJKen2ZyQrRWBnqcN8ooWlTGVCYATE1rUDqZ0wuTVvvqQ+Lavdp pwh6V3FkJhpgTRTKImHSl4iQJCjgdJ+OYlSG/CgEOpkTcgcL2yipgr4HUeqmsgBn8zX6Xf4rjF5P S2v+dBTTjRHoXAnFFntbqbInOy36RwfKjnI9rRI4Q5e1dh2bH2j+4ZuM9E3kN+fg6yRPTWTZa/jq miBc/5RkqnyL6qPAAHLsNcPVZ2gJlJd54gLj1D1h7jhCdJqCPHl2ZIi0Fy7M1252P/DB+8v3LCRp BRCe8g97fqTfPcSqlTmJ6drwvdqI07igOC7LZQhAOm6C4Gan/GQQ5SQldvlpRGUrEJN679gYLpQ7 V9McIkP0vklWiCPoB+RzuJKjjbVVp7Fl46Nn7GAQ+TnXGBH2IT1aRQ1PK6IRVDCRUfK6wd+5ax5K Ba7Ga9eXi9+ewBIKJjn1u9kEfPKEmze49fNEvLNZSLg2tiT11XzA8emnGlGCS0erjp5ojcDDLDLV bGKI3lxd1QjvvTMa3gaapoA/dRfTvi/8pd53wSTDIDoudENAx+UmIxoD6szU61SZfn5P6fl2nc/h rdAzb68RLwhgtZB5SK+8JfVTxsupPUq/+trHiwYia1JtxIr3GBXm4dlJ6Au5qXpH/BgCUZbdNktH T5tDNnsfh/9ym3/hu3F2b8miEGTZ237iRTIr1/z8UKwD7RTnlX4EGJFBILxmDqDFQSIBBG5VonpO PbN/VtcrJTeJ5UwMT48DlcXEH9BVndQnnyUSAkKaHSvl7Q5AVVEjQMAQQsyy6gYvVRMq6YW4q5gi IeoDSdkJzaFlBJ8qWTkPXFNASDCBvMV0W/ilqxj9n+gS9YRO/skXO/9dtrItGKJbXPFZOISD5V3h Rpfsm/av6HE4rXxZXLrSz4HxPXOWajsoYAPEMYyJPNIZr69URNemVCXpLxunyx3BN0RATWfcJYDs hdHuMOSoRHIleFgaaCRnRu59dB1C9jN+XHyLRw/a8g6I8XGC4HNoAIwTjMXyCWeFsUqpETvyL7eX P0YBuGcRF9uTx6Err7mOGsqjdW+3Jvj3TZfEuLFQliZflTFF/Syj7lDvDpP1APHYlP3APZpoQD0a PRGA7ltGHcnjychxG0dKrlkzlwTAeVM2aJ0Ym3To9QP8qzVJPagHDgR0PnQ7z3QcP7uTRldEpwgF IzjDgfRS66NwiVOvs9QjgW6CjN0qhEr2jy6aOH370Nsr9gogO8lj6DSTgkuSgWdg2tLFrkOJzGR4 +okpCAqSaNA99zZjrelQtCG+HvZ5wMnCncZpmFb/VdZ3cEOzM+Er86hK8lh7Wjsvwj3Q5KELDp0/ ctoWBQD2KpfIgNtL7J/efQbzGO7AgIAXxDRU6fCb/LZk4fXYUKeMUM9i1YgVTN0kHv9R6BZeJ9I/ zu6MI9fsY/NJn223q4ZPLOUG4BRCP4ojDdKWO7kdhSTK9rXj2G/N44CIU3xzBSkD463UeR9Cwang TPvqR2rVbTeYqIRrkvKNxrfkjDwrLwnP0wLjBXmMNo/ydF+gTHzkoaIYuWBv6Vqr+YCopRw3WJBi mJFc/39aanxNefkolWCTZBzCj6sVrVUPr3EbnqLvFxg5vMSHZj6yjWO5p94njCpTF8pAc56lUnd7 WLRfWRUHwqgf20bpoxQJ1vqX8Knre+xIrNtrrz4EmrgXfFpkpw3fZoJa6bK8Xp1w0SaQY3sxJtUY s0pB3sRkAkHQIR9n3CWu0Nb+Nkbp+3jTFriutoLOYRcbHRX6wvAm1kmO5XtsbGM1jckeRFgIKWed CpKkYeoaAbFbBaDlzlYLUViE6cdwXknErPqwm0QjKvV8vwOJYYgrP1j/AlFtJdObS/Q7lgv0je/m g9FXl5uO15f/K2+fkzg674nlkafpe5AcdS2PnVNr+6/DdT7hY2waoQmHp/Y+9U8RrL8bLeCZLzVM f7ELSoVTilDmmkmG8JWPsEo/nge0M/dIRsQcil5BrKKPZJLpGcD9RFTTM2TXIcMib+DfGQKRRZA/ oulAtH3YBAMl9WFE00fLpKqlryrjxvSgTg1GZzXNleakXJuYwpEoE0mCM8j+0uR6vLYmBsDRwTQl kRhy/nQ0qtlI+/btLaXBLpI6SR+HUO/SNZ6/U9kTO/EA7GcyhBNb4uyNnvHCL/7VKxcQHAmapKSR dA8u8bjYr3AA/2Ir8rcltfMlOtibqfY0ph1RA1X3fGTUBsT52Y+VtnmLTz7JQ7wI71Y96FBEbR0L Mbvm1AI2voAO00mHHlL1ZEJ11AIa9VBIhXoiJuLGB7MOHIgwup6NIjIMQXDVTkUCgC1FyWgrIBmB xAQr5crwF+E0kFueOxyQs+NyiucBqyubp6OVyvALktVVMFJ4UD01/rkq37e6M800ZVrimbp62hB3 ixoN5RxhbDa1pfVxkkoMtPoHU/IYS5vEf6iU5+xQ36BB5vqxXfSeJmCJ2GJ23MUc/Ej8K9ymZSK4 h67O9U3Qo8kY/XDNMIKpKU+wWsSsSDs20T/cthAJWRTHye325zxR14ZmPRU4hpBMcy13xRPSDqUz J3K4R4akMinKdJU7QJfuLZli1uMGjvsRFMMgfelPlm5dA9keqdZ5M50eRDqXqrUriAoeJ1DoAgsN CBGCygcZ3Hjnjn2Oix1wLnv4OVilAstmMZL+/I0Eho5Cd5p1vYA3RpMy8ELLE4q0Gxhmn8LHZB5V wcchrEi2wYxbYBot3uZBTEAU/AIwt+tq5X4IeBdE8UgMkXJpEYr8Neeqs7kUoO0JmmFs9GOjhMZp IYvxsqTaN+ns/lx5Ifz/2Y1oawUQ4Avu6MQ1JwP44IMouoHrLUd9iSMKNemqPlDwyscrCC9e9YCr xiHWipXJmAwPSl6x2EVi6q+B3dk4pRmTUnApOIchhQTmhLpUxC1Zp4JOY4v8E62nzWSWNpw+gZj/ c3vSJbuU8qYd+OmBEmCwTqtV3+VhXV9OtNbaEw7B5y+PbHMr8xVxPXwqJ/WoT35Vhn1iuYCsEjRz KFBLuRigFAJLSCy9dhHklNDEH8NtMYdKLCe2BPEls0Z6nUjrwYMFQlsnDV89H0Uq6vhfx6+lpNjW AXyymOf4HUtQHHTeaOG8ifK84iGNmspRX6BbaMlGM02JGiZQeqNayP3cNZSqVgbTmBMYHnje8dK3 O32MJLPEWtWjh4Rsp561xG6ooa/+nTQBKI8Y2ilkmPbA+REWhO3Z02ScKB4ROpcTJsEhSwDs5o1K kbwMumEApXTGQ8vJPeadQUglJ4SzYUPoeefewD2dk3eB0sZdQ/dA49MHjyxj79QkKOt/a4Fe7X1B AM8ABKYUXOw1MFxRzPnsE3JVyRy13V/t6io/f+TR7Fiw/d6Jqz6v+ImtzlofRmkJBaqTQRJAblPO Rejk09AjmoWDnbvEWARtOjsAEEW6fz0l+bK/DeLqqErsP/2Zu9v837vAPUsGMdhaoHgsKOv9c7Fm KT78fKdMd2J5QxoBF3lfU/QFpk8BlLiCMvgknrl9Dp6gapVnp8sRQhiL/p0/ORTLe69QfTJobUPE h28Punw6rb8FSwe9JWXrFs521CmDz/0XdIr/VnLKTAjgDqtH5sqZfaTCJlG/XnpP+Eqf08NFlvqt vkj6cWJ3U+FPvjpQ6rUqNN0axxDpnAcsEKSANjB4I7hy+aq3Ap58goMK8sVv7lLkZGdZ2ckBs6+2 CUNwkQ82ckN55MaaLALKeslnVd5XqBhjeEHe90mfn8qRoT0ITNxlsgJ6np0Z05vsMsedlW3yONBz j1VUhNQFZMR96vXREWBajDkzIYNY4gge6PrFPxXpnDI1pUAYQEWBnQXG9OWDLDEsfmSmYj2ksaQi UPvCHUhyVWb59vjxz7yHBr47sNUM5reNw+/6xdv4CwA/p/rhsrwTg2T7TZkPp1rqEgLbPibmNOc7 wovThXDmrtlVKT4T4Iv34Y0KZl4Mv+bMoZDTkDSDbbVrEjjfo6vs1fPxCU4mHHPaql9cql9h0xEn 0hHzj/LXW0GZHsb6rzoTyi9RcxeMviheRV5uptI/gXMcEma4dkvNFARbEVOqq+S9SvlQcwFejHS1 TBdtAVTLVX1HcSy03Ev3RGsKc27y10ePkXMXyIp6c4RfF3Hbc2oLzYg4OHfNCra5huEuhrnDFMpn BjTSPTGmpfFXyQ8a3dfxI9ViL0fQkfJxp9iLa9Vmo53ad3WbSPbuDBZ0oiXyoPamqY1gfay4NZ3A SnSIXP+uMNM/rjf436NZVi1DneEe0Y+0Jy3p1rSyBOfHNXPY9B9xwdJ88oy45DJq85OqN3j5y2Cn Up9lo9NT+HduQyE7z5DQcEjzkXInKw69oL/XHipQOgNzBp/ZKX90Jlix7ODtkSK0Uco5L8LYMhaO QpyxTFU06VAuOU0vx8qUgJ8XTfnemQkdVFPPtFb1kp2Hxdaqzc52QCeH8Be+tUtVYhgd4k9/sClh zrGHqmKKrQBde/JQDWZrUUzxiu0RBneudbRYyko+9Izi0BE9aUErSOUpCTMab0lrAWGjXU9ClS1X mQOQLDkzPK3+QzCXrlnW4bWLqaKKwZINdcAddncp7O8o8UatCMVNYXzq7ktdVuqN4HT/UmNk9jOX JNTCIgmpprg3kxIt90FLV9+6fWlSNaEDoV934vsVhLtAiiRlMXVrfpLLwpECr6Eq0x0UM6HmI7R+ cPvlFz1MTuUgg5C3/ePBesWlKaAqo5tU/aAYlwJlR1Vl73JgDL/Rb/byIG5IkXzOnJTLmJLPKzph JURsYohV+ZZ6RBQ0e6bNOjooEWe+0o1i8VZCGtJX2v3xpeZE189lS0UnMjkHagrKUM/PP/R6UbVz Of0w6t8l0+yVl+9x01fVsjmhQsCyE5s830C8YrS1oGAR2ZB9KzaJv7sSCnW5+C75a2MzLdnVA/Zi 9Fqda1IPZSPPeMLtMO19hZyMTwu/4zeyWd4MR5agMzGseb6/8drlIzKwUbjViY0xg05+tDeewUAw LylsffWMrh++RUfz56UU/8GyoOog6ad/mqeQL+7qL4SgxHuwQqployM5CBcAImnmSic+AyCXL2y5 rDOX8tYrWbzp6H0VTbWt/4rrKSyDzQdnIqVniIFyzbSo0Vd2GWeo9ywFFhRQnsWiddZzhyYZqJIy wMpyRdLo9fJH9eRHES0qeQHbb4FhiRgWZJSDh+Imjair5cBdXHrK0CjoVHCZk4AiAGAaoxt40OD1 LcEZpOe+HO0zbbEk63RChJp0Wu69Xmw8YMC0XfPSEoHmdrFRHGYOPGB/5SV5ch4eOe+LXjULw2Vi rzhDMAY7YM85u1RFXzcRGD5TdMolGxBbTo2SBZsS5oNbWZYm1dFvWeitoXyTPFfHsB6NzylEXMo/ Ac+trQ5ZboN1HdVXtiGjNrafNMAa0Hbe6ApoO1CirlHufsiNxBEfYQRuMubiwfuSBvPVlnFygl/J jrEpT0DFLA1iHPjgdYkqYB09OmyGTLkmra+0orBxr0LkhG95Snv0g8mHfzcuzjCAoJd34XpjrYz8 BlzaMUGzc8XmlR3yoyqA65L5Rq45pn1OXny3AySFOROuDOzAJ9FiXFrwxDUI7lJSWIeUaYuAmHwj EiVcCB2mv2gkNaiEg6cILehlhi9hc33uoGd99OHP73xP9OFFSZ2HAk9UtBhC62uz+EwAKYfe7S3Q 7cDcsJUEZMluko87X3HIWZP0uK7lQhyRl/zliaw7crNS9KUf2mAMFQgI7dOSGPr9NLXoYBqz7hMP 7mH+/ZyrrvwUTeH9MArYC0A1xFlMjJxhEf+JT1oI5A/Vo2I2nFUHB7yzRTHYvueWxbm7CC16rSyk 9xy08gm7Pk7TTwZyQTL/7l+Utx0yBf0YucI5fj4GQ6RvCaxR8fKCpvLNJJryZUA+cXaDFp+ao6IC SVoxtaqExa5vXC9HCUVoDILTp8pkThaW+FVhM9AEBuxpYjXsJtgXz+xn7j6Z/bl3XjCH0/ldvENM mqiWOBtBXagIAcVP//sdwOHVr3+EDbPEawD3ACP/Xim7kuz+2cc7/O8Ib/mxe1C4Tid8i0dHe+sq e81M6PC5UlhFI7/nlTj7CEoGrqTEQxBqiZoMrIKVDJwvtQXB6JipY+trfz5oZ3l5XePmvzcJij+9 mH8aJmHLdh3hyqCpwgCq4HwTk914FIoSN+DUJlb+Nd8uB+V6BwDKmSNusFv9QLYKahyaVooPd76R xxxG4woz5ZZjhPXLNtHlTKxV4VMaFJlrCinnvMGLd2h3Jk0X1lw9857mxAZlee451x4wed3Ebsh7 we0M1qkdoJJK6n6mjDnnXgPLs8wXpkv04gY7ShIza8QDT2YUgqJ1YhPe8ZSTTViREz3zoSVSz+2r cHYKuktahrb29myYXBx1jVlndSMchTYUVDlQFqKn3HX4LFtjLFodT+88XaEiZCf1vLBPIufqIL/0 iIYu8aq0Mh6acLCnlsCq/Oe5K4VwqTeeAa81nNbN6cv83XPLR69xajisSqYL3SlzaRb0RZORygd8 IfybcnTPjI2cK/ub8cfp7Pq4soc8iZTDsSis2TOOKeOnr7hguwQ1c2Zrn3GLLjJI9N/+tYqdnjAH oTJdMGLrmpmIDPTQvy19jryZ4HhU3rbzYhAPRlDwYL2W05PXGaE7Nnxd6IWPdac17MEUUCqsMloN A0AHIXjm1paYNFha5mQYUyxcF61SINlzrsWDS3pqeO351u/PHAz7oZd1eWnA7dIjkhLTRu4XC442 siCkxtG4AC4jNzKp7gxyiMcV5yw+Tw9cBxGGMq/Jl5pzzYFbveLdhpp08GStSkRPsoYZCEj8xl3a GKXFwVCxTIMIsEJ9x5Y36R9UrREtap4pMkkpx4DB+ND7DRUQdBWpmCSMcAbHykErDLGqKSjy/J2I oS66j60Briud4cxwYfR/EMeRNap4mlrGiJcJvubc3/sYzkkE3eRnMVzNSW/scSrOIDwI35k554va /2NuQDUYlVBXICh9vJ4JyMcGGsx0E5fP2MY6RxLwLk5F0xLOAXNQLo6vyEYVQUFvAlQx3nKjlb7c diprgue80ZaMBn8ZABYtUiMCruHadl2K3pwa0Nk5dA7h3fzCVMQ598c2z3i3EzCCZOO6k2df+yDR 3dgs8mjcdD0z4qeVMLcJCYNrNSkoWBLMxjvZCmnSi/BiY2bPWhJMBb7FKbTRN19yX9JK9MMIZbTt Z79PRl9eTAeqYP45FRmaCf3KW02y9J4Api9yb8BXqXlQ3LlymsKk9Pgphce65t+bVeliD6yMOU8z rFSxaEjjUTtmteZOQXKUtCmmfadYQVFCuOskPpyanbjU1fsXh4JTmg+RZmxeC4HDkqnpAgtEu0xV 5TpLcJnggHDJeCanEk1NPEC18rYJZQtCVRRoJUs5DwqWQwtyfDjK8YQ4GaiF/eJAiuf9VBy/SELn iaIvnTg5h42H2TE/ZJil1SuweMr5LmRxfLQLioJQ+hR78t/+i03XfTAKQOQhZnQyMWapJ3uQLZIH PLGB2ug2cjyGaOehDvwt+k2id0I+NcJdaMAHaEaEjOiwEni7pMAMZPlK3GcYxYhGm73zcBa8kk5U hKrS6mH5OhGEuhjoMfqubvqB3cND3nxGwYS27Y6sSP3Hnpk6Q7BNhlIFUbjtcn9RfG8IjsaNIcmM EzP9o1gfGr6uxG8zRAt82uh8D+IjWZ1+l3beVzMOsqCB6t/n3fVar04we/8hVruwySXREPbm2Itd U7ERgdpigRjz0mcgIhOElYyxoP5oZCzYDFPxVQivCvkriIiQ3JzFNIGPm8vqYGs9wpbOjJpwF131 jubIMhRwqyFGY/QK9zdW9fazV5+sY/1TRB4sLo4ZkVAUCSo8eJd49YQMePaWvSJMDuWo8io/y8tm wDHitj+/LtEHTTP5Y+K/oHfRhY6FYN15GasUmFxfk/jczzx5+8jPDraMQti6GPADWfYx0YmdJqm5 +k944wVZIrX8TOBs+bSI9cwljhum6yDkUjW9wnFvIeUY6wGPVjZ0GlvuhzjS0DX41HbgJOQGw++h 8FZecT4/3LcjRdPe4xehB7x8N9/z1Wt/CYJHViFYmTP4gXp6ha8oEFFdrvs2srIKlIWpQALTKHM0 qC6znULxQWIchllRqgfpA7tXJvNWUALL5UNOWzbZdgv8TEpZxZtIEtFLaZoDAYGBPpO+xMRy0BWd kkjzWRlABFbJi2gxtYO1ss6C9hCJ5z65n6o17vKKMpQv4/X3UJKge4hBObHzzPnc8rrqGm2ZyJoN eNwfRpO6EEZ7iO25hNW6b0Wns/2Rj/BmQIEGXZKrbRaYEvIPgV8Ckm1yulk9YsFa8wBLQEWmnmlg VIfJtCseZV2r1UHxx5LZ0YpvYFQOKNFJRHqEQaGjT465cWz+z1Wjgv0zPZF91j49MY8lhYzP2SyI KvLTIKnNjd6TqlSaqqkDvtDOMPwaR2sKAyp5tUGmPHPrKiwqMPNH+/n9iftRQ6HAORjGCMjYSUoO dys0sGwCzvxNRi5lXhu3aT8+hEr0Tyzkxr/r43D/ZKWXPEREpDTiSbdcC7jM7bBoxH9JFCRTJwqa a2hYDAJG2disOoNNWiRn5h7xGFddj/ybtvckLyVDgZNIGG4AHKN0d5HUV1zoLEhkRSkeJy/WIXE4 Pm8MQL2Z/CjNfn2tUGaNxQmiKlL9qE/J4142l0WB0IXgniA08u1G2dZ8RLrBXFihh0b2gAEkwl/2 t83HMw/4wqWSdmJfRoKC+kldZezlGCLZBHlCwKMkmvlOu1fWEcqu/WHDNUWdwPqaYQ8wDfid1wbm eQ39aBVCNRUny1exZigJO5JpFuBKGLJTMXszFw9ZuJle+F5P+WoPqaZQpcqzfShUjsAzHBE8mSQO FuZA8trEYNGd7ZR3kisB8TVudT4Qp1h3VmYw8vwKoYVETy9tDVw/52h7yvIfLSOtvwiIJrOXF2jU o+Xh1hrb2XFmubRrN8lQOLptT0J7EmwUuWZYrHthY/XX8T/kqj3WbzqZ+PbhrQHa+44b20+lNxlF +Ux6TRFG5JwpkVmpNPxjQhGrXYtAyL3ZtPCh9srx5oGYEBMKlmjQ11C4ahb9fKhfSlO6H2E71JTx 1v/deL3Odc1jPz8iluB04DuGnggtC7i1pDqJKiCUnzY0QK7Me+xatW1zWpx7mboB0uPKYAIJVX8H 2NJ0pKiM8gd+NckhvPDyMWxOYTXA5/JVh7lTYuMGv/nJnMKuoFeJOlLIKjobZULefjah+OLoyi+E d/Y4WNBOz4oELDDq80SEN89pBgdlrQbOUkDs8uuy4AWFk3tAIzK7Pf1LaEx+Tw4oo0+ITur5YXEG uMgwgNem6rQuJrLD5BXTyuxGsf2/uaebgHUiiZcpSDH0qjcc61ZYwuqaSOFKDxGFyJgF/OkFLIUw ceSrddEV5k3uaCCAjwR17f/ZAQrK9+K8G8PPiIZl5v9H6N+4HNYG+tWTERLq5x1VPh6SRh2KnHH8 qwyYvTVIdPesjTQNf5vetRv8cNkoxStQAqNfk8gJXDk8eqI1c0pHD/wmLZkPC4L1FxJvO6WW2CvL DtTffIgAnLbb++Ydwh1VUUhV44Wz8fTQ9AhTC6MZ/M+LHYbOYXk6srHb+MUs+539wqxT5Yi0sI5q uDvZE/ChOu66ZAB1N9Oa+b1+RQrXxOMgkqh3j1Cgb20MMUijTgcz+rsVgOjbMBw+XH+C2jaT0AQV yrkfT3pDIX4pZnrB5JEzjkqPmwXGt8fm1OL61w/LfIb4UyuBpKS5jQcgNbL8K15huIxFbdSel+rT 769JL0lFn4yGDFPOLNyk6GOOItiQxeZCv8VNMDVyMfO7cR57vpKSu/v3k8OZvg91ZCcjumkZVqsH /kC+W1kOOxxPHC2IgRgZgKZbf3AnLDr5L/Eahc+YbbuRAKq74jSFzmsjsG9TVAIULE9mgv4ELeSB 41Go5E+gCgd9aLZXSqna3YScUaRXJGf/sEPkNBQYDdtceqXuJue0jBqI0B8hhSI9En/E5IbsRV/S 3oB2uZX0piFhiGNSel7bPVVG0s26LAv1v3mG66UlmYnVwe6usY5eK6HbKYTlKvRkPVttiUxFC/vP 8Qi4lNFtFYIXBRBGwu+fg9iSy1LgFbyDr5c+O6hBD7aRt+nQfBCwewA9a7HnAhGyUYW9gOm8Wtq+ G1h24EyDVTypGytD50NbfaoeYyRAH/hzECC1Pwv2eXiszG+Q9iiE8SUaXo4ByEO7MP2aBExuBh3G iW+4WkIFVRe1pPbyP6clQUr0W3npEIzi+lKMSmi8+BWuAi71otCUADcJ8/1fBKJJXKAR6DayR/5t ixmGAFIezTUBzYaXY/szLU5ZCWi5Zx8QvCtePnvPlXe9P8cm7lOxJFHW9ZmEik8Hca6wtknUSXKa +jxtjZgB7ROAY54qIgVm66wOHR2jDgdxv7Ge7zD//02JgUtVqXrcXyARXHXxWr748WQ4qvxpl9r8 p0wyoA3D8o9RngDYJ/7ZEgXJC4dZHooifptKJDxfGRj2UeOy+n5t++A396MCtjGisen+7AklpyRh AQl82W5LUvFFehuF7a+z9hHcWM0lvK6DwRLEle0hXUUn0xFNAYYyCxYH+mUM/Ytqp4YMlxViC0z1 3ST0Y5Y4LXrUWvOPbyYjXbyncgGfzT5bv1qKV/mz5Dy0HVE2HSeS7VVqQnLq0+AlJhg+aLAi4Mp8 uVs1hQNJDxFHNPcW3LpBZlH537FjlPo98JxppJICJZ3cU4rpKPud+AD+27GEUFsz6h+GOyUePE9H K1f9ylVDnLJA8UUvb9bRvroDYzb9ICzbp0fTOWzN2kdlBCovOWZVS25mTpkM7z8uBMkz51J2JJk1 6poo8aa5tqTXCsUKM7tpbAFdLwm4nmiPlPwqqMBMs1dmuPYz0WDT8HjqF4Alye0cjokiVfn+gwgw X5ygYImST+H5RFYXWc1GsUH64rNhtdpyIVe8z2kmo0avfjBIqZMllFCZ3ZxGqFmzwXHgJh9+wcEY FB2PLeQW7AFRbPVx1CuQgmcVUOp6vhvaaXMzS5O9Q7pmvJjaZ1OqThfkY0VQSik6kgyoc+UZOJT/ 6d8bhLjQw/C5nPiQ13sbUDtjW8Z0ZDU7DLoXBY6TIwV4Pom6mctYpcM1oA//tjntiwRQnSkyAVq4 IrAXVNsHh+2ple4ryP7GMyjHB/s+3OLLTmSx4nwWrAwaiCAfb/l9LEQCQJegDT7r2iIEjWjORdZR C+3vFYx3ExpetQe8eW4wWAJKKywVbdP3PSX6JEVASmGuBVCeg7Qxnfw6i8oLkG6acXv6oACaBTNN a2YcpvK4AtLAabyzERQDvLLfOTjPI07iqM1L/rePHzIXViY4mKNH5wGmvTWAQNKOvxoYO6FRZF73 MIFtPMTKRSQ0DM5L4S36cLIFlZopP5C6YQzzZt8wFzZM4rlLbA0DenCo+3TIs+/FyjXSQvkL2Bxc daK3XUrHAnXQ2k5YNA4O3Qc+NKR0qnNVJ7O1WGuccSfuiURKQyCMUHCHP/6+gzHZ5wRmsMlQdvqL eijfUGmZlCU/2zYdBbvh+o5YYUs9+cYjDu89sKeVHP/p0jaUQPHYKeWmg1HDGsFSSNne6vmEBC85 Almj4vX1loF+a52lzthnDWSnfTH9lzq+KlK9NI29yx0FXTeH03XKGm/umwb0jDZLg+hLWsdWMh0b 8/5sIA079lvrFwmqE92tTThhX0FKXdVNmpAJXRJQ29fRlOhOQAzjzrX9s+YJUKp4dLqXq0SkqUVf Hta4mwQhB6Mte8v4a65DqgW/qddAUcPZiYFSRGAFtMKsoOKjtGYhUiLFj2tLoE40bmI5qBa26GNS BbHSOyZuRaLIM0G7ZYR47xyKcxOOLxtqB2yMQc3D03pvc8KNS2VssYZGWwN+Q5NGX93HMMruNTT+ aI1zfhM+s37QCmt3m92n/FPTqD3or1/e4EQPU8F0HfEWoLPWkYBG/p5whNv7nV2XSYJAp0Uk2oZe pudplHX0VejykyFgXmfJKM5baYebylcidH5JCu43e7TD27WSMOqiJyz/mjdwU3gwOUoojua0KH4T Z+hoqZPKOfNNypZFzrAMCsPx52zzXLsrQqlGpXehaoERGHSOOiizkZXSDTtyjKf6OiJOhoM6vOxo gwlWKNrpVpAK6877VFVvVkauj8IETxzNDvbN0FfrGxKKFHay4OtY3vZcdBlCdSa+fw6OLwBIvJyn rSPhLV+irTgli5sZmcKE3JXBhGiyDWX5JjDm0pds2LnZYf71jRynAV6ZlEv3cg3T2kQGMQlMmROT LvGOUIRkFk6bq9uOxWzAuUTOIsvWEtjxAHivUzK4ruGNo3cr6H5WjxRtf9aOemkr5IXOTBuRZXEY NWoVbQt/xqaN+w51MAa2X3nbNwTPlK5D81Cks3bxQIYSV8hqAMjGDKXBih+DVJVz3HEX8g2kH3sy m+7/kV9G/dqqDKT2lSqcj0kBFUJ2YhqJrFGTmuIWSC4Ueqg9K8dIuwNI8vvqGZvD2+YSZPcuiteU iCctdodpGU2dLrwP2oUQSdA2bQsdLZWW6LEJlSDmaAF7BSwdDQJgaSoHKGTsUl2k5ghrJayx+aiu q9vbYATmwWCH66kQoIEybRidXBaN6BowJZetb4sIQRWeA2wXuwqqX5z/6XxczOvCtjVjj8BuZWHO 7A/dkFFC+x7SmFghJVcTw99u6QffVwOzFEh9VjWHYULz/+vwnjFmbQyLJm+vuYFU2uyz4saNoaYA tCw2ti18dzhjy87QU6EZPHE6f7fZu16iDcffSYh9wk308HZUDpNWPNJlJ0U/12X7BTG52FXMhXLC rIvbMsIh0V2P5JST2SqgyK9lvGhzX4Q1gbXTGk1WK4vwn8vsfni8dH7hu9lTeP8ccA1LbBuW/Psc Ib/VKhmAiqSQcMg8r24cdEDF5IIHeekohCOK5SQJD9LcQvyuEZzUc8ugzFDJtiElMqFon61OnDJL MfzjuxoXAloTm2gjEHJmZY64tW6NTxyuudlUAzCY4xlg9NKYdIHog0IZeklb0CEGNG4pnBewHNBg IreAfbZNyXtDehHjqb36BrGdNvge9huxO+vg+Es/vEPq5BWWT4mY98dIdfJs9P53Ag/Eybn+Obe6 Rbdr5oKRSlvTSVlbdBuVcRjLT7EUuIWVTB8B7Ec9oBcOE08emwcfNtpXlnhpiaQovPKY20HI+qmo ukFWJrEByuqw372sXOIKIE7sswEH4h/vy52adUO4CIKvQcJLtNlL2EBcu8rN+zfHtRhy8+tP7gai 11MsRnJ9wttM4b0nIyrOS7b5fXi2+Wowz+nBiVA7T1MVlRVZ2cwVBbWP1+5JUXzww6LYyIuMzvcT AGy91aorFvgBPRXxaWB1Ed1R31Ekt6f4Y2r0tNn4Gd/8B5g8JxpchnVjhmmK6mwEIBDiD0Vq9bPH GQTjT3vev4MP0axMobNSo8fF598fxc98so98cMzFjiZv1VeKt0m8KYdM73187CqP+QFW1rQL1w4U k0AVQofR1GBDtSFcCWQfEzRQUMmIPGeC5NmmDGjOsEojdATnNQ2MML2k//KQRbCOyQejhDvILXy9 OxU2OxBS/oNyqMM+61OO7mZLrLZYmKjSui5iu7k1hV8ym/59ZFGsjDA4XAHz3pXDvrOcZxYnmrZd DJVHwsv3c25lL7Ah4/dd/3yhSWUkMfCEDCCKaH/iYvnhAVN3J4KqkBARDQWi95NOQ/EwpIgo0vyb Jupqw8X6AXOyhpyIAlJiRUeKZ+6qWvPZ3klNgVJkwtWZQWP1y389mvxwqjbLtmoblcEMObnlaDOB qG6ptq0PeIy8IOpXi/+X6fon407r7WVpd1REvqatuo3DY3Zd081qWQQgKVXyAbP1uO4CnMnKeNb6 CRWmo/mrYW0tHhDxbApJufs02/VGS4PNNR0qYlGd3xFFS9ddfFwpVRwBeXAk4xXFhvpQ3Xk5Z8sD MoSBO2RRKN/321sk31gThbrAEskYPdSytJRzgEnia+yO/wOmGG4iFVkwovRXGiZQMPbFPUVSK2sv gT4RGDQDMGxc+zU5z/LBrj1aDmeRPfN/2XM/HeltZXTNzQr5LCNYV/e3uR7stk0LxQE9kfVeqXD7 TYpKEIZRXckgiL/65i8HKt19gifQHMMFT018pk682hmMZ4bFgla+5rd/SmOy+8SvBegDTh6guiAP cJOFf4ZIlJuPmNQCnUJ/90FC8R+Bki2BgNE4A94IuQ+4QXg2sRR+pjaez14K4BiyjtCE9MwjbPm5 uYVfoizlZXEzQe51Fk9ZWPYLbMxL9I2pWDewiSzN5C+hU14q0W1HJnkfw9fDKhH1ovHbUFGiGhZI oGvMgSa8mRju6isWfyudHQR8ht8LyleBwdFMfvKF3YSZrmAAZ5xI/9mvG9ay7G7yG4a1H8j8Cm3e p5Jmdt9d7KrMeZaj+OeIM3PBczbbHZZGwR9sv1oZep9L2In00XcrR3D7rh5lGd3RZU4lNM4XjqJU hUSvHP6fISYrEGBCRh/hYGx2uCILaUomrbTeBDjP02jMZclQjphczIPsj9O7+DpufJ4eDFO1pRcj dyaqGthpNN+6/KJMtb93Cg4DFJV3IhGYLKpKadUVePk0Hb0LyhwpsVD4f3e5ddJPYUE8DH05/7IL aTXumVuExc7EZhL0eg38BvMNoVC1sSGDGvlhv22TsuubmrthIZVR1nO0ZglO/3LrSwAIjlRqQOCM 2nAh7rb6iTkBPLNcpS6BE3inVB67Q/adaDbzRxEhPZUOezADEvJ2auUJWBfb1e/FRlgZw854CZd3 VcZHL3ggU1hx4Zb6jCs1p5Et2bOXekrENsxMOeCINV7WPbcFrKoeDMXHgHoJqg+i1ZX/SBC5Vhov bT7LOTLIGFkz+UUaNK67HOusx7o3y9TlNFqZNGHPCQvoK+GutNvEA6Km0PVlmbuBRakkUORaV5Jm Dv7QMPjMeM8e54f4yPluid7mIK2Hxf8d40dbu3fZgWToReWtucj/859ynQ1EC8MnIFARNqaCVpRl hA+bUMHAwVWVbiRBNlIO2VQhlzoDD/PN+ShJjX78Wljt/lTyXovXWdwyNRaYh21H9MlTU7QMgyiD 3B5GMQbJSYTZWleDrzwOZmQ9xqNayOcV9dW+ylGGW78OpDMjjjAK5C3oKB27EU05MtoaSLVcUwEY QEqg4ry0C2opAlBeFsxo7n0MHYAfzqElSkZ+ZIZ3RoreOqf/vaQD6VIDaW++pcr5Yeb9Bae9IZae uN/zBIMD4j+w9ikQneKPibZfz/n82crIDc18RXarv5FswB8zYATzN8JWbwMsBjwB8PPVLE5fyaR8 AvW1ACALWj5O7IIJkX4WgkB4N/CLcL6WD19052HAMfAXjKaBXAP6S51DEp0xbZHRPMd9WDAltDdA ETJS1pKM2+aDf5A9EJC41QRdhrKkn0Q8mphKBosGl3N09FLkRpNRc0qreMfl0fDlIr0KU5i8LZ3D VWH52x7agqEb9ViRhHpi1WkYyXlgpJlDOaU1rnp/JYurj4lTSrIY54ANT0qgqBRfNOHEtgGCeYKY rzglWDMbMNSXtFmFuw9pRvJaSCm+Tfl850KqprleKMriqhpAHdFxbBiYm3XfiLksuCQ1SpLf7fRc owy6iOjH5YY5JJz+nmUQN2xvyyQIC0ZRTER5QS0Er6oMg69GqWnmdM/t+d+vTgnP60Q/HKsVvUeC tMbiJ0PS87dmtTQLFdFjhlWv+MHn3wfEs6LXmBXqhNvwyV5jHJk+gZfamzUsjRfhkqXCbVfHWvCr Zb7s3sNJ6VUYa738n1hwsk0L2Rkcj7AHfU9ouERoHlp+luKcYyBA34mhgSpnxKghM5Uj2osch2eo 33i93Tyy5HYYaByPTlr6WqAOmNIpPhRCXL70YIapi5gfyrjtqGx+Yl6ph9XFeiZTWId02BB57Ps0 CulKTSjyX+gJniSwPqjLTuzMGKnPngVcAxytFAdJ8YILO17FAOu/NCP6nJiz7rcc7E9uTVmhoVDN e/eECaXFzQNCNwlYsWNVtf3ccAS5BDNeo+ZJ7Jdi8/TwB/7zdRfzzLV6HBaqfDdgNOvjappLT8f5 ljNK+ONMNI6BixMcLIFfcqHcl+0X9oKjOOansdenQ9/NtBGHyCdeEZ6aN/k/aUnu9Y++YzpH4voY j3Q/moTaQMzTAMn6m5htJO4M1exfTzLTwlyyKS6tQUiUdBq9Da9+a80YsCDLz5OAuvUpFwzEqwhR fQnXPLk5+pTunkqq3zDOx+yld6LOGaouO4cwgo6/4LWd27y5kfRL7G+O0cwIrtJr2bPphL8ctTcr magYaIcRaBw6R69CotNOdfh44xNA3B+Pm4YLQE13Ysu4dBTnfiI0qYk+PgiYG97V+6/EZro+PKS1 jErExPchCh3RAiqaVSNZuv72SrVkfB4BMIvI98kuNTGPVAVQqxx4TRMyrWyq1vNDagubrhoG8auc a3n1dtvpKg3hX3OMz7KakIkLeDAdDSPrqEyl6HslGhyLNnMR3YnwaU57uLf5RzxwhCPwMd/4ng7s 9/8MxZI49GpVMkMsE44dvTsvI0ooxZNMNGl6Rh5F4sBHfCqRyrk7bGPCXhM30Edxa01JoRkiHupk OdWIAtXwWzBmucm8JuKPpr+ce4pBHH8YWyV+dnMAub4d+D+6fBbtiPnyHgmXvt6CnSrfp8D9qSpP NqocnIzTFI8zaiCYuil27BcdztfYsr2FLVdrpzD+1Zme0WGT0J/qcmSd1c1csKP9zC/nIvUfJ+6g PPPY2/CUkPItYmRTII6+JBy8oEcMhTfI41kOTUbqU/jpdVypBovBrWOxTPPU6NUGckDqSrE55NxD jgi1gGDq9fWUCOEUMAo/71pRDvGsHMMgoqFm9jH531dcm9Qf2KPDGybWqfyFFbFbMyjmLWQRnqxE R+sMYQw5ZHGebkkKyt+uBV01O/LzqwhFRG8ax9aWTpAXFfPa/qMV7ifz46PR3fGfC9g3Y+jref9f RVAwZ4G90rcNWfGoFKSGXt0+rctnxO51kJH6dBZSXqCBiYblb4Qa7h+i1tm7kHFczvIbK6M+IAZJ sOEkIIT+bvuvKVPlrtSxO1ejHGQz/eTr3y78COzU7xcKUwTkxQKFiCEJ0DjiP6t+etJJiFkhR3sL UNKVuTQudSBfO7C8eHaRFoQpvXnf78wkMKxuHJx20J6y0QuggKZLgCLDS9Klg+mscsNAYDYtyUSF 7gBYH/IJxlx8WMsckrexOEe2wAonSmJBAdtnxs+7fZQUMfjxAWSFkK25BbRin1obWANObQcxEbUu QTkhqzwKpw3coKuKOwsrQ2qHmxDjFtg57Snt0hDp11FmNr1WIy580DUfouZ9u4r/p/KkUbEXVPEI P5rKzpys2p3zbW/YRIVTYD8ZF8sdSasEDTPU0pl71v84t9wJRDmgEBq9e/hUAYnkD0v4d+BD6psK WpsG3X1rhe5IhQjS8d4XCuNBDXdhziJCtmrPBzasP4yC0utZlJGGqfy6NNI/H2uGmgaVO+d1xgzo NY1riZaovj/qAGILkTADWo3kywaUAzGhkPfKo6nbvrlQwX1putOyzksSGFUYMjwQnHBA0xMVB824 zFbJch3j6qFjLxs09NgUsLJIuf3c09ZAwXKfwhnVBzxzi7lctj6xraaNhCSQsp4CLu7BVDRSSQc9 3XviI474itl/2YcqoAcgon5UbP+FBDTsGuYKR5vpyC3gvfE3d1XmemfI2O9/8+eiq128XSMPDzpY Aa/mnBLU5ghqCO9RCuJlID1etvs76glG9kHNeWGgme+i9cNNRDFS/5HLb9yjNBDvX68SjV+9yQrF YJOTv+ISheN6xOgovMY6orwkBml3kwxgGTmKqzT6qt8D4nErhMrh+cpaykTC/aHXOQjUxdSYHNzB efGsB+sFKY6IBF8bNMI7EbluXW0y0yLcPeb2LYPw4zDoz9ewLV0z0J632lAjdwz6VHQzAiPIQtPT LkmV/mWwX39nmhJYD16wNYL/S4ewgc9h9GHSoJIaJjvZq9DrmsybU1gsDJUwltDf/Vbsbo5TElQo Agzm0nX9ngvVrtnYcM4aMvF+J1Om0IPdxyO6ourVjs8D1GK+YEgMB1g7/8RhZpfYooKU0PFFZ8Zy yaJ3BLZHzMB3NVZoeaFC3jYjo4ER9n1/WqgkwEQiTwVV9uD8tkjp++YQfrzaK7M2SouPaprXxKif 7Qx3ERT3ucRbXLlLt6GtK8yP/+s/bEn2sMWdThL9Okj7wH9BaE6OzKKm0uHlRlOfvwUmD2Iq50sc L/4lRrsqD8FB7BiL6v4Bd59WmTPl4VS/Km6sKxwQBe76YbLn/fFaOGo7coVV/bCa4QWCUNdYtPZg 6EopGWl73H5yM2GiREoGzAO4u2xgbk8gufazKqEGARohLvetMwIm4/X0AfW5XWNtAYC+dbgJMaPS MHKs+4Rb6BRP87yl4GKBoeWGzaHWTyS3PUVrsvo53L6PazLCDksNajFR5NtduHZhi16dZllhmvmt Ra+gfJIq755L1nSIxOCxiDBbqhqJWCU0gQ5vCwW4Gc1Xo0aB5mtSALaAkrOch6OilRqO5T4/hpSF NjyGAV4AbxNJN0dMp6mpcsFBi44uWnCjOUYFmZd/drTYG8hUxc2EynIaXFoT07ooazD0Z9HYrrYx WRB4lFqzEBxiuf9QqeNFtk01ipOm8jNePcdychpwAA6tobsRiKkf/2XpX0F9QaHtjJuYHvidbzZM 57e/w8o8jwTlhvsr9vg6QWSZ8IR0X/2FYdRy8Q3eesHpFzS06r6FAIYvDi7XNnsJCcQmPEXomABG 6MhoPqMye4hXhOqUnrGmEZglUlyh09gy2ouWuT9SoS8mnjqZVR8uno0D8uL+SY51Kv+BqUNBAPcM EhG5Z7UhwCeR1cWtn7IH65iLc1pzdv9kA4Eeb9nqjz5cUV0+OOfy+GP8Yu3IPjd7IQbODqNbN1Nu tyjuCKTC9ZFBCmc5OGR60oTjwtGIzgc60MyaXK0JsTfr1eN7dNrUD6c0P5I/u6jqbhCozIt6Qmxe e7qggwdkFGGqJuv0i1CfrNy4RiR00mDqPWCqpGFuiT5CIBI0v6mVe9saZf0GKlNPXf03FaDYdJWj jJ/AfCJbHONR7hTYC7Vv/l3AgYp6JVZsaXqXMK7OSOXk5gJZtoMhV9S2JD6gouWy2CWBOGB3P60g fmUzKsV7HAs0RfzlPeQ+J/zxpSEt1YCWc8vftsLpB4OQtKm/6i82578R6gWdbKWXspaZTcjnyvRd 7cXS2gdcaLaVEBEppZHwDLPIhR9IAM4/zHCpO0TQ1fbipGYPS9/1kDd8mXyEb69MbNNRdlseEO0h SVoHP3iNyLsjshlNV9C7x0q0sNwc1yT+AtjG36Xp0XRZDuQEyVvCHVlTgI5HAjFvvp3wCq03MvF7 8wH93YQQv83s8Bj2sXwPvaF0aQu1iagWJYJClRob70P2lxb4jhB4/hEixsVFe6DSDw9kj9r/cjoI kLEw+khHp5wZn6sUjTI+6EmXA9hHEHOs5vzJ7uTBOPzu0Zncb7MKb9EPYyuhkeBDvW8uZXsa7ewy Zkus8t39c1H8RakjyrrWDx97LQs2XlxPL02c8bXPArIQnrKjbi5LO0078YVHdWmVsJoYOphApPje RaldD6n8/G2LDWrOfn4sXLqoJ0KmPW9w3K8/XmUVkN5DngyrlSaFVx9+MOZBw+aq0vB83I2ZS26T xqMOTvPs5CB1DnuYj7AynK7XVOA10mv2hqJ/KKL2oFOw1mHM9r8Bh1gTgUwE2ouHCCJGJbTxYN57 N3zWgyzoe+xo9FiremA/8lY8wCqLob4Ea/y79S0RKKwtUqsJWRcpT4qIGe3DZ/DB6z8ZRYvjT0xQ 7jvG+n3Xf4Gy9sqEv3VprLh7Il1FgVk4qQVGDZyySXhbGKlfv0MmtT0N9HWm0v3fffir6k26WJee MJEFWPdxjLH8QLGG4NT12ZG962Nkc3MVGus1kNpS6w3FfSk6us+07QafDoc0lQjiE8iLyhG7USUW 6vI0vbUfKT/x4nzmxQ+cM36a1RRZxXOVfEB9kpw/+gqlSO5P1YhRh1yK+yr1bUagvw64CWD4IExp yL/NZVzOVeMEWpI34Ktmvot1mYxzzZ2DFZPh2596PMupfVqCGL5MfiAR4hDn9WvomUnF3D7Xhtjj pmA6du2Qdex5jIvkp7mXPOSX1KF8CaSThfNEVZnsHyI7QAQmjnkYaLT4AFSzhXPphdBPALn9/13E Rcb2+RtDLvfywiwHOg8iyOZ+vc3i6aZQ7UH/Pf96k6Ryu8C0toEfehm+OoVSn1ReS9m6euQXUwel pBFalGQFj6F/B/vSzENk8wXitsPH9T+5fn+1JHSfvepiM8UQjPeEjDlXbntbxim07polVVcROJcE uobVGjHvAVZbvC9pYqms4RAImSXCR2uKqDWz3I5GePCciP5AefOslpuP6DZQ9b5owxeqhGJn8AfV j6zL2wM1PSBKsPovwGFQnqKR3BMafHh6jNfPxH97hri3AI//h7Ht6a32SoRA23/+s684kFGo6sQt Xlp7ypuLLO4owjsYQu+FS415LPAlqMPejczhJ23XH8mH3EX/1VuNnRvyGcxgAQYXA1AdZKGLEhtM uBuZBO2djQ6f1o497qo6r8ZO64+VSF/1VJHWTZBXmxJTtsW5f9HqxwM//xk9xs5SAE7B1ncAPs6p ZGWkaXi/46AwA5jOdAJRFquyAeGpaLnkMH/nxbRBi9ZRFpfD9tU3v4Q8VblK1X1ecp6m0Q3xx4PK 1wrQNccBmlKpdub8mFF5gXIjqEFCVtD2NOe80AWb7gtkuChLL08Wr4R8grkeEHhg8iXXlRiZxQqP rkHpKYwCApD4372LaTYPDlmoYqeqWCqD1btcpswge/1ZQTbrTIo8dVfq1MidipoetYm2ZAnaA4fP 8+GkNds7xDuL1lHLhz+rj/tUDay6dA1bg3Uo7ntb8EAAEDQE1c6CruRiMAIcfcdPxBMgghfnU78h 93KQvX0YZGleLi+TL8bqk4E4km28IUbuoAtmRH5BV6w/9eXsupY08bI3IDGtOAMKAIlvy/gXqAif qOZX4a85FcCBXl4CDpBFL78OKVQsELcP3AajD4NuSx5vUyR8wE0hk8W2mtzAyyL4zhEL8lhvnJA+ 2W1ozEr8dqSzXWrMpffW6LFmiZ+EEXo3ub0bRatGd7PkVGsasrfUM6/ybE6UBu5U4AwfaUEa8am9 EKXBNhQTfg797uhCyLK5/de69HeKq+nH6pOGQNxUzFDn0lSXS6FeqzdeoqMdxgV7eNN4SRVD5N2n aBVr+I9o/RcJPQys1w+I2JKgLMN/xSgW1a6bSlIQUJkCL3fGWoGAuE26MBJ9ugQ7j480GBCb/dmH r+YtQhXeEivxuoBpF634KFGNwkUabzQhQQVps/U9Zk/dlKBRBtXkjgUlihK7C/VRnvTNAz0X9xse 2XDsSu78VFnomNhBieTqCZD8XrpWKzTqyMgJO80thc/ygcrlQDItWHKLh7YvHBdZB1HsuiELHe0o 92eKDcqHf642hig69B0iBM326uKecGz0kHI+cMelaPlKX1plud4AUl24PjTXWderiFsbjElHtK9X zxt2oaa0o1F2v0MUI2yV58wvF/aKOVg6GVZBFA6WtqFlIAJoD7Q04vNpGIsQ2IYeRMVEnnxg8OSA h/+DS6eCDWCIuk3v4g8OjuKHrjAVNE6wmIaPiGtCFtPYDigCSrAn+PiwiUHLEJT9aSLZPhB1mjC8 UEFAdA6KQiSzVbQOLYn93hT+oLoQCe7QPvlGVS2tmHSg62t4sAJa6HsXCN7wmS08Hi1VPOAtboRY KuVUEN3b9wZJBzlLid+HXk9t9L2zZkIQxGUm2fG1+quHnbtNTobBY4NkUTMSoLEbB50Kpk2M4VzY kfeNUFDNnpnuYBFud2oyCxQKPKSPm3PecyqaQBCub8kzJOVlRpas5M3wEPxrF8xt1mXJtTSd9lc+ 2l5BxLVQ5RjN8yQtwLsZgMJ99hyRyMELt1pwNN/YvDlyxYDqIWK0aWNOoZMiEd0er+rxN4ChEO8e cUQXVm4FB4xVif1hRqCXKgUaIQJWkm+5G4UTlu4tMs/1yGy4TEmvm/czy3pfZoCgNeQUHYHP+Ar6 2POJUDXdnnYSyi1oX1qO1HZ42s8CVn1iDQdkmn2sTY1evaP6lfWNG9Aoe8mXbm5ErX8HuZ9TGdKb ZcYg0NGPc3SwMCqK/Br5EAZwCKF0uwQyFrARU2sOMUUOSe+VlQtB5BtWjv/nbs075plVPxXHROI7 bICuGbTSCYeM1Grod4jcUTxCodTHV2B6jP3ZLOMWwf/Nm+x9335qFpPyiKvgCnmSmpqkYzifH5+1 D9c9kVg2WhEo/pvvKjp0Z338t4uLJRwVuXM+7jBo2CQsNBlpnuyVRPS4xbMJPR3ISK0+eXKZIKd1 r/d1GQdfXp83QdNglqnAJbFcESEXsrLvinLI8JntCtUNORCYDPLGAs6tJNNY0GPlFndsBXANx2/t T+BWUuI3Yf31kHp0J9E3pkjUHkNoW8IRgwTApffLh0tZhQfydGUUggHdOwFBCf5qEuCJCnQDkET6 SI9w+C6u/Y7aHzbNBoeb1J4a/+tMVV+twEr///9jdC86otB9qRkaiRyiRy3wHv9ux78AHLDpa+fl Bq7CkXUBwj21aRzt/znPOu/bzqHf69LrY11aGVMcIs/QS3bovDrzFGH01B8YD+h1DUoH/Xavc5JN er95RJO0yLFs8n2hqG6O7ZzLufZiOb2aZ9tEJw5NDID6dLMrves364s41d1DCugaCPqC4KwC9oob Sq8v6drbTZ1uWnq88NpHlJZ0515scAafDSv/HnKS6OSwjW9Z0ux0mQuuhpPYRpQBHUE9oRkkWsv/ 5LRYJDUHMAGdDCkUcvsKiW303Nb3ueKhvgl4saRWOZZoG8lVHpsAM2+0Styfl3Ok1Us2A3R18II8 Ky7p04vjug/UvMM0x2J1CbPNeUKXhaHEkf/3IQtSLEbc8dDu9CSMwODJ3S49S33AX5JaCNjM5mis HKkx6zIMsWeCWIFmV6cXWAChWt2veT03QJnLeahJF9NFppvBrzDv0dmtNZ4TInd+S5uTk29Wzeia iyRluQjHsP2ARbuvW5hAZv5B+arjlhvDoxZy3fqkbJ1VRfDfhY32It94lpZguZEio6WmCcC9F98M eglg1eSJgXV2PGPhgMC0xoOeUcIpqkH1CwfqBva9yOy8QBHbsghm0J2rE8H0dTml0YcsTuXAcGl9 aejKvA46ERzeiL4rkTQXbm0U+RAJOmbAbeiWct1Or+wl3mFHA2Y2unnIhUqnxKB8xa/VXaAbIJtI Q+6W3xpetVXGLFQfKsOzjkyDJT76weL7hJv765384MBFE+/VnqNoQub4d2E3J4g4LQFtwMTnFIUt ZoyL2ijJgpZ2J/eQxWbKKrM7iTeIiGRCXB6yDKIs/elxENZbMj6WQQmcrg1awmUfodrkTP0eSLBg 9lMPC9P61CDwrGwZpNfkGbc0Gr8SN4sMgnQfvEipNWkiP25tV4ajZEtA43e6qm3w/EzC79Z7BnJw RjPfzuS/qlmt/SPuI7M3nZ7YY5cnxJfnGFhK1khuR35uHlr1r1CQlrUdcFajk9xy8VbJUgwkN9tl rdlvOC7nHZn4gGWIEAnbrRUHD2tUK4MhOWnmbXSk8A3kROwgC8qanxDoK3vr8RjUn7RppASFlplM 0y3BGMGlhKiOB8adX6AD/uGJsKMO9hh0brTwXpO5Nz0AjPSz3zdxpQWuvx9MC0t6CRksJofdyYnN hreaqR9IP1uQbnHc701Mjj1X1mwhj86+UthoqhAq2TTsIF945ig55GK/y+F01KzFp0pw7Wv3Fhf3 hs9sY1JLXguCq3ej2J6p4PtusUbcu82lomh02/xWVVozb+l8KU02Y0GAmaNMTbrv+Vo62nDZx47l wgdjgTt5yupZXs1TguSn7qGebZiY2gdXYc8ljRoiSCDV4ePRw3FltyDVwffB/E0Tgx6RUbdRrI9q dk+KIDzGMW/VWBtI1yZHCGPOGLZD4g21YG1L66mUjRZDznXOdvvCVCwrh5nAndqzMpx3407PeX69 GVEP59kGE43RX2+bLdPu+89WakP/c4PF3vmtFnfxEvFFwLYJ9vW0XySYHPxmUIHuR9tHUjriREPp /4Scf+OkOv2+5c+X6UsAHIi+uJyYRO8KYyaSeqT3A0kogxUEckGIvYzHFjDZ/kXajBq04f5o0VdX sWz2FQTkeEBf84d1dYyOnkaAeEAqnQz6ZfCCxuJSajgjmIjcQxc8vRgnn1nSD/JraUITxn6IGCRG y/P13croUpFyGmnimX0V3caSqVtt98HSxWfp8asChEZafCkeH9SOT9y1qbpQFOY4XQGeyhGQB90g SyhFPk/BPU3HrsKaapDrhSlGEY5mXfQ6H1UBQvommtK3Hsx0aWiu40KiE+O8zmR0xLJvbQ15jD1s bBAYljCzzJZRoGlKXTrlr+aORkF9FFQXth/iQibziSHT2MdMUW40VGCZskBsEi5G3Xh7WwCtOdqn 8rEDrwv6veLOEQIGbuinXDQjRArZSerZr8urPC6xpW9nm45ZN1+JFHHNUYAC1LGfkfPW3qDbp70w Q0ahUPcYxgtedpjtgm9nlTU4/A00EqUswvhgEJyzpgrgVycWTObRjO1E7NOohFivWMlma1cN+seY S03TkhlswCfZe5Cn0TX3u4OiiYm4SsH7AVh2j1yiN1mfoLmYzz2/6VjYY6pVoJT+BqAIltY0GjSN sFcq2L0opw93hFnQFFUNGXW3nMdRfdli7qai9OvZgUY7O1xFYYHUKCbpfrzhVJsqLl92Y3huKJE0 2T7RsN9JnXCFcayY3lDTd9KIk+CQRiHCexWnjFUB7dMcB7U3N9kvfeaXyWqlqtj6OvHoP/qZBKRr DMCsEC54SGC9Mkls6BKbadLh/R68N5uyBehk+/MLv+2pOllbptJP6KDOc3lq8an4jbqJ1VQf4aT/ oOXCqbaRdy+JndkTfuLm4Gk74XhbnuA+cbshUNednvFI/BxiAJPterQkoq63gMJ+KzYVcOgZ5NWf ZPV+n1u1lByrz4feZyTkhhzWdlVyf0F1ke1zwojkIlYhm6hA6x4YIDuGPD4hkmLStlxXgnPULE9G yYFuzPz4F3V/+97DVP73Y6PaIvzPS0TL1fFhotEczoFL5Q9un+iail2EDQqWqBMay2kIhzoqvBF5 F8p1uiOEYmYpPwRrQcLJLhVkieSCsPkK0fMQEstig7k81DKr2fv6V0XtA4FgohOQOy262xk5Q6Uq w0AiMWEyjUQdAEDluJB4G5IBSs+aSf4DmFd5VCpymNlBW54T1yi70bVuxWpQpKbBGdepskY87CKe 8ZXh3fkfX3HvpZj6F4rfCVfbdFNNMPfQMs91YXhCg1c3JcVhi0twEhJA7n6R/pJ5N02xhU7QHRL3 tLxblv2t+yJI9ZXaKS649PpJqhOwxdHPRJHbU65k9/8Et6jva+QhGNniRdGIVJVsJdxs8r3G0rr+ nuRgvKq9SrbziFwNEqG9cZ2s+nBK2Fa/GSlp9RB42ovPwGrygLTnZ9a88FA0qfU5XeP2WO0HZkR+ l3sDteFz5h5oOfitPc64oHzj+xUwHn9Gx9y+qJzbX5u0VgpE+A8C6TCrJ6amEksxMTy4e0qQDaTQ 2unuCSM2vOrTNm7MqYdZKKZB5h0RW/czZ6eX4qURyUUQPsMpP8+skWfJ+V7GQpWchYpQLasASvoy 6epfJ9ejXOECea5SAMTpbV6bI/jv+cI5LEnoPLJ+hoHWMlKCzCvreT+seyq0kIehHt2TSPAveRRf I/LnFkONohDRtTFA0wiyPBpvQEftKbtuIK3lUqocVcu5FnlUGne91hCzQnFX97lcDrJ4ivxRnWfC vpovPCf/3QeOh64QLWTSVHx5VdUwoiwxbMqT+ixQsx9vuzvd4ub0LImC2hXE5dtrj2cFlPZeEA2u jhe2+Ba/KVKlhMr8LSVwyrKWfvWytQFEwMtALkedDiPrugdHMlefoaYMzFHdJ/fRTuSmr0v+P9q0 mzmKkc+koOh7X7p24FwnvFkspjNsBGvfwZKKR+e5qBl2O3vT1a5b50fMyNOtraNwMabB03XK5LLo +HRpMXdYZ9EvUt3yHLaBvOofiamNvjqPhroYF6n2wyUBsWGw2giRv+BIJINHjAEFh8p1NVAk+krc 0MaqJMVYxhBxg028xFX1k7yQvNVva7TKjOwg1neQ/X2nEqEmw61jo6D4frnh2mEm/7nCxPTCgMcu mzOirgokh2bqeA30ZM8gq/pBVj+UPQcBdirzwYtvJv3uiCzFtw5N9NIwaelNTd+RGtWu76noBmDE +WqCmrRDxVWr/vRz/HjdJm9yRXwuPrczhdoH73kR4+Mt0+/ZaMZPgIigK+75vFcuZeQlcbNcytJx Q4FJuwlGqYHOP9jg0c+k/4gpk5wJlbKIr9zndcW8BbrMZZ378q4JzdrPqz9CukBYhx+DOl3AyHg8 aX8VoIlb9MEcEN+XcPTm1d9nVErCHd4gsK+stw7hiYTRTAcIm+PmrpjV2ng7Usl3FYP47AZcusuL nHWFvd62D1boNiLq9Ogg2FpT0Dux2DvmO/JvaEcXHy/+iRntXfvttnlBxuFr1M0QKygngQjhUOzH S/KvzLCCkkc24SOmFmfMlI4fFzAjDZ9m+1J3qBww64TF8zeqn3pQfCQ8k5lP4O0FoXfvq6fJQXk8 t+CIuVX1nmeZXg7PC56iU62Esr3LWLqI+WWNHWgXZi7/Sx61rT6UOo2vK4DwmVKlsOm/ZNAILo5r Y5FCuWxcrCCyOE2tH9OviHZH44oBtdRijFrploECqYep0upqYjva5sGjhR86m0EUfz7YFICxDJI7 f1FOI/6qQApozQRWrL8U2Daomu06onIKpRXE+HKVm0JxlDUILIqLJ5DJ4S5M59dx4rly2KaZ0pfn TIvWpMvnmUrGQk1mjFnr5obTyYsed+4MPGVsJ8MoM4YCRUy3Pn8xcJPiW00ub0u1jMVnHTmUyM0U SEqKybquhG3z2GZJw/NvCl24Ih9qi8Moc/6lWJGjvPIzDhVHCpiYxjMpopAIbEPSGkk3bxDDRZg+ VZu3KjAUDHAJ0LJXd9yzLO7je1JnkKx9OyczlIqWzKICRkVHwuPT/1198pFwCQBPD2FgAZvnl0Q5 BJFDfEhIu25tPj6GZnoB9KssGGU4/wh1xEYotOYv9N+GR/8eAr9ZFBlRPIRbZDQ+gC8n2H1timna JwjGYwtzCBI1f0B4IAjH8EtnFl8O77/PUBnx/u0k6N1FeBuJkNqs9I33TjpeOv0x7pklTgUmWVwN F27IYsUzplR+zQoMyOvTlHdCQaZixODXUiquwYpbCccfAtJhif+GyW+wnxUjPG046ACFbubXqOFK tkHMXqxSh2zawoNr+3u3OJ8e4EDrsOjRJilSAWLLUfpGhFvQkIQ2E3s0lv1BdyQFB+DKsnW6jeIO tmSq7nGyGB0Ew6W/EKwNIG52Z6Y+DmTiLaLsyKbr2NbG7AmZuoGDid0TwkW/SfSNT546h3ZlqlN4 U5oyox3GZ6rggSiPEoC63I6c6AsieGwV3T1B7t9JeU6yAwvzP6ehNuOaWobQsPhVqr6jvD1NE1Zb Vt3oMtjhQ3879mWCPnx3aDm40Lpr1jGjJZ+zdklhIfFjVs3GsPbfLfMF6yY19Fk54m+5/BlzHnrf RkXXOs4gqDYu8pKOl9+FeoYZgji+yvwagJdp63xHKZs9zG1vRiL7CyMV2YdOWvTI/Y1zePtpiLOL AnC5bvTQ+cT3kCBb6Nhr+pOMktOGwTCndpmuaEdXrScykyAq8EcaXPDkdBOmIo7eqno6W5UFZAQr nuEKZsSTT6wkKVXxR3UD8bP4Whb71eYOUnRgH95QLMfmm5HHYo+AJJ4MglHG5kgSob3uITIEA8ZD qAh7JZQCFVFXl4PuQnnNuNveKFy4X3WE7EwtO7l5RQrHZptu08NCh/tWSFP/pYAwpG8+4R2/qZRu 3KULxOswCH5VZCE5VA1Q7okkeNSPmkccESQ/D1h3cX8X5IWX8s5WuHeBOkFRzEAA2cQM0NKciA5G s3eOmEwRO809t6N0aym2/xucsbepBLb1jarK26fGIUVWbkg1+/NJ0MLTDz7lhTX8pvvNU9KQnFIg p0LRn/b/CASUnSwCDPE7EOsHpyE7vROgHJDlL/5fpvYM/AJJcUk8O7/WOVzs/dj90L8d4jR+MMev oCD1S1iu5N9U319oUKm3/IyFBlfI/3PlSeyv2C2mB8gDUK374WurXVTuFL5XLVap1sm7ocyNjFmI rTB4yZIasgQMNzJreta95qYp70B7nVD/EZrnm7vSdzxPslmCdy7pOMFz4iJWX0+YUYPlZqC5t66M uTxyBErssjdFDDEmSNXqB3bZneVrWtB2nk4H0CTuxcMnxrtddr0BahZ1EBH1my36aAim45r4rPTh jUy2NAjaWoxyUBW0H7vCiQwcPb67KLQ2pdwyDKPLOlcu2SYLCy6sy8zI+Ar9UbIpSGHki57PI73h 24SW5Dn+67HYFThmOAMARVIS0gaO2VBW9eeKrYJCdQd6KTRR+/VDHSx7wwoaCU6PlDVWO6udVIWB +pnAhS2FeSv5+ECVGqgtJdLr1LqihAoeCzdH8SrHtkIwksjcbGEyKTUImKX6ij8Mrk6z+7LK4FNY Cm/396NOUW7vnevtYwnmp9ER0vB69+CbCI41PnS22ZrZcF0Kuk34btaXaumly2YYgzYNKUdmZGx6 MaMi5N3WO1CirJfItERjv8ykbJ5jyWlBVY/ITE5ZzKzTYggQwDIeBtOVscMjznQoeUCooqEmlNmn 5yNMy6PUqGeOjQYO6iFL/DsThpWQ5j6GMfedpOyYtS95vtSTN/4OE4kZMApO8XEWKkMv597o0gUR gyC3sSbtb9kNDiqySgoXPHjjEnRp+lcJaWsdw74Jc1Bcf+QzCmusvLKfXogK7rjA3cXzrDUy6S2K +aH9gVB5/4oVV8tuS8ruP1vVAeGFdVzurGxsXNUlrxYHFwH77JPZonqq4J625LiYpfoLCOhlMOXS fcDKSY8NcCb30SCgh6ekcurBNiSI4g+b4HcP+bbiMjSBZ2A3BppyDlS7jGG1WWQyFfIc3ZKT1jAV 03aEpMIxcTs4GLNYp4bI7U1rVei7eTlwXsUaHVkABcanAs4P1xP63Sk17CF1zzEBi2ZyXNXM4D04 M5nBJEnZLh0d5iranudVUzKB+5z0VVUj1a5JupS2ITrWWv2RGLqoS3nvJA38xdp3oS2DAFkyQybx gCOGWGqcFJ1Q/DYhVc/A4HbfjZiGHJ2B9ynIOYHK5LRajxNkom3iaP8rXqpSlhGMdxf6bvnYt7Sv pUHCfX2q1qOHm0GtgOSNp9Jt1FZi/LHX7FoqF4fy50vbLpvzKFXAvx97K2t46z28U0x6bLBDl5mZ IKq2TGqKyDKf/x1+1iq5ISGtkWgdqEd5718Gi6TxqwG0J2lgI7MHm6SceyfQ/5mqBzZGOqxwo+8n F9LNL87KSF0zNDEShQL8yLI2k8i19spPYGWw4nQx++YwZZhoOFMlOs30Hzb/hkGg9TRowFD+PzyS JEMUEL9Hjy2pMd9KRRzwTs2+DwKbjvRRALSbHJvQDJqZf6TpDgSnJhZuGf98hTo5oimdABKjyUaf hDvTUpFp13xKII/it3ywM72tI3cwJBCl4hkKmVOcJegPlfPNk1xYayCFM2HxzWiZdv5wQzNVh1/Z C5M4PA56CsQ5wLYuiEanMb5b35zzHF+IlvuZAnP7CjNuapjc3aScFM5y8bSogGrRa5DpnbWLStKN QzMnF8R9d3c9bA/Z0KjJhlIldxSOged4MSH1aFXEffKYpDcUKws5ck+BZziQZsCFRoakvWb1QMd4 QjGu42kN22CuJ0WKvSsv8yn+LFCfflGqrf2SsresFH33ZfWsWg7iIYBcMbmQULmVJKCqUtxPgc4h JpGKhVrk2DcqWdnoF9Sk6Zy/n5xldyKwZBCsrUylOeHxvV6xHPdyJ6kSLANq3Q8j/5ulRSljAKrt HBlK9vosz2ptcNtYO5XunsPVQCz7kdG6WWqdI7z3zqX1zDDctY/kToKGyTSO6kEjr+dV7jqp66UE XDzDzi5RwaJnf2P9m3Y+5Ic/OHWmLNDpX45j9lr1NlApC4IudcLQRnO7Jausn2PrIgKKfu/vV52y eJ4eSw+6fpXfddInRs/ZhM8xjaEFxUUbPI1zG2tlhiyhwlG1X1w3LROfIzJz/R5TPZAFHbRVE+m5 MuSdovr/I9KKbCoCnstkcJFNgjwF/VxCLN3TP/HzvrR64BKc94LrwLcHhKyNcIUR76yqUZltg3+e f29XW69K8ANGwCJsm1dnECSOaGrbAocqRVRs+fn+1hzqYcwKg1/m7u4tEkj0xskllC/oIVznuX6m 2EM4s71bHZmYD1CClo0XD0cgVmPzUYJLaXLUxyWk5CPfHTAk/dUa+k8iviJWgdrPdGWJTpji0gP0 W9IAsYtQZQoAK8ZTGcR1gfJKrgKyzweWrWPmzTDH6OwL9U02Ua+8cULu3WPJ2qiCZQ/JZJJyQ7Xj /sas5qEA1r7o8+3QHGbGXSmdhy9XfvxpDrmjSvzhr6pwQ7bAWp5f+Yp/x/5jVklJ6ss89AxHJQV0 mhf2+z5baHg8MZw4OB6wjr6fStXgvY3ZIFa9arTOAF38V33xT1T7QrWy54k10oNwcnp2wHg15I41 WRD8Y4nY06+AgYe7mwobaFA3klGpC291HcL2S8o/jhPt9QE9hJY5vOLz71zwfI84IgM2IsREQkE0 9eR8SONTSqOihBtj8RAQckgoapywLhIcqotC0UdRXL7ensvjBISMsCGhxUQ1m4W0XSHe5ggazVQ8 TS2AK//8HUcRIDHpzgki5dohu1AQGo/AmlxxWW+XjX3Pu/aStNs5dGifMRj5gfiw+ozHeGZ99fbU eaGPFulCxvLBh7MRc8fyyX+y+q09yR/kAwuYYVb7dg/dhZe+0A/+b4uins0UH0/xGu9Gt6eNnh3G eAXlMevpeC80YpLDLrU3e8KZMRMu7wmM9FrYSK8/rDVbHk4ftYmYV4GvP0erjB9ze+nwc7FhcCVk voLdZdgt49UHdvDpRhaS4QuBec6QbJ/2i6hY2uCjV1XRu0vd1mGFUU1QaBRyHMy2GgSz5vWtoy2M TGyhz01LvTLZK53HUdV8NkDxt1dkK/hglZqjnWlCKYB/yqPkBD/vBS3wEtLoeYqhOkUgIReRJXJv Q0Ad4KLQNJNlBdxDZ+AEnZfpxgpw25pDXg6S0J6weogLKqVFp5Y6ZNCr+TVOnhH4xw8EvbNbCTgy U3Q6+5+3uLRXav+otperHvhcVZxgJWVQQTsgE4Ih/loGiZoFKoOXFfvSRu66mfnUkHOix2q0u/ft ueIfExMVRkX2wIn6Kj0Jvc3Mjd1x6yD4klBSnDQW9Nc0AO4BcE+dL1AYePXiM19Sp+2mENJx5T69 dpGEcWk+uoqFVCu2/8ZJx1JUzevi7yeIJySfqCR+jyrvGxOi/8S5zPzOYIhD8I8epjfuFt2+C69Q atXzpKfCPAvgTGxjdAQvktPOaFGD5yk3tJDOOoMIKmNgL+qSMmJHIDAuBWXz51LbVzRT1e5OZ38c 2g+yGgTY42+LVk+Rno7rzepHltiMOo2NP5QazChlQCFy3QqlpXPrK6LaNJUYibVrKanTmWUKGnrl L7J/i1UgJt9/wsvYNtkivD5bePvAjOKkW255iO6g1sbkMxRb++ddNaA0RSHJxtZk+OIF8L2/1A+p rtXLu9d6aLiHys6yo0+QQfiNMlx7l1hcVXamTTM0vC1OJ0M0m7UcDL4xqmnACgwh67cCJiQpW6UD /PxVne7JtJjwqDayhQIb36eTkhl4TiekpN94vml1pAorOgxafhIh1Mmrjyl9Og65j05hwIkibVlb DtVjpnwFE9oS1tzUaf+sTtLI+p7PEPdiFcOqeDwgJScDMkJbtQD496dMGr/U5irIYG3YkGaKt4lp 13zMeUWBBHoLGnvqH/bMLqCEmreM0U64E3pKxClgXGlFVXnkZjTFBRKxClX018c3yURJ8fzn3Kgn qaghaEt/llNm8G1k9vfiVULg3IxScRGU9VEr1NwT0h9HAktFYxCIxmSsdouioBTzM/QMsHQEzXAA MSAUfzvF8YssPaFpa4U5jejNCP8p6iY2ebbKWYMjSwt4puE3NucUqWyKWp/+E10YTyWmwapihk6S mH7U+zXZ01kF8hedpdKDxDacj5mdoN251BBwCS2XDy5M7iI4V5QG7AO55m569ItzfMJAY8ZXCJr8 oq4CsIFGu2PvRVIuzTa7QoBxHUfcvZVtHmVqfe4qrdUQiyYS/Xnb7bVRNSfr5h9Chrr2oLnk38HJ viBNb4GQpvvY18UxQbCaH/XAj+v8hDTCCAj37mJ+Znk7OCT+6gpSGqv55510SclssMuRw+ZssF9w k6U6xdfNODvrdWYDDrvZ7B1uDjeif9EFwWEABPh++HzEcKYTmLOiaZQmPN10GwCcDBohpyKnmH8T QB8T5gbiz+cR3rFiZS44t6vmQ8QxXw96UuIT8HClWFy1cYu7rU3M4J7okns+4f4XzuN7NTnmMzVa xksd+pdN2267f79/bGa818uXdjWqKmAJmZOLs9D8KJZfEMCvL4YdSzG87Tnr6xZR3ab3BpD9kmeY kYlNg//waoTy7E6i9FbdOoLrgJWarAMnf4f2uxPwkORKOA5hJucyqJku8qfD2BCYhIpy3t+f+3V/ wMorT+JjhqO6rgqpNp56zlBLl73Tz4NJldJ4nE3yqi0UimrwhApfc04vpf5lKrF5vKOPQV8czla5 ZpqXWDTkUKp0NsGeTHZlNPwx2Sp7d1+ZXH7sLjuTh3vFpTCXs6GsTAAQfzJ92PvSCak2nXhP2OEZ /OJ/AZZ78Lix45Or5awmWdgO0jyh2BJvOHk4E4FoQ+IiLsLIgDM+Pa68xNwk4IpWWwDVHs9nxnih LYgEJ+pBwkNl6l+60Y9WM5lFLjkFu7zlRdxfUOZrwteyK20Q9fVi8DNC/3py+YTUs5VWpuR6HlSt Rk4YQXCj1YJVKvwtJ7FljtVKcBfx6JMigFv3JjlQteDWQFmaNbD1RK2mfk78R00SerMag7DJpzDA 4DLrsz0+N9IlH2Wm2188nvV9wnWgAchTAK5JLTWJ/7GLqGGaglq4xhYi4DFN7TVWOZ+BHZ/DFy7n z1BheLim5RVszkPVuxeqcOIut2wrfoa7+bfUzuaS+nEkqSv9bc+Y4Z26qG0kfnXpcHrC+trr8GLp rYqzZbTn21radvEamg9G6XdGRP7GFFNOXddKtusT9xrlvv1Pbnuf5u8MYkdcBYlh5IOZ+BRw5mZN 9eb3Vtkdf00B7fAFeX0V2EcM/c00appUkBJLpzvwO/8be/XysyasYjHdu1NBVglJ0imNZZeY6juV PbG9IX4Iy1lIhtuFsLC+g8bck5Efg3mzMiMclZrNAJ0d5Z0xgEaJlcPzUV9ppo+Y+ISPPSCTOn3L hBUDDi3locvVkCOLMc0/fVxDjGd/DG0AmkicQT6uVoQnh0sZWY4zIlG89DzjW7WpMNkcbp6Ajd2L Vm0zEtWPFMmsGiz8svS9BRmBSAI4x4j90KdOUTCNCmhJWDIIBBsPsEyl8eeKjzNrcZBQrwgLSgwm TeJguS13f+ri0STko+iRarlXSXDSh2RGtKV/tvcqOOBkIgSnUmkaxduidXNA6KDIt6eIQlAuwZc9 aBNSoqDbTQY7urwPFlbrde3iRzw5v2YDdb4re8xA6JN5NnX8TTmGKNFEK3gCEp6JJYe/PXx804aU KDuscsUC/82P5Qaf3m1KDhNPh7LBamodMZ6o6ONd1xWqAEyrVKNdW693d+5FJq7xl6gIeR8AHynY TyOy0Z8p5JG1zBw35yw4Tk18BBEuiVqCxHWY4b8E6rQb2A22Als7q8J/chxSCEvaxtvD2Louamoi eJlsl0aHRqdI7+LIU4NxEW1BsvyFjCGwk+Efq1Gk1fSIqnoSS5JKBx18401qCQdYM39O884uQ0jW Mkwu5LtrD+sFE6deNMZS8ht6AkHcSfOxGu6iDGCyydDjN70Dn+IdVJn89/L1U7/zPEbPgG52xLIq Ef3Mlegv8mzg/BiNShdAdu9j8fGwxKVNQtovpLhbIJxMdPAMvZDKgLsohCqvtfw5SMH9FQ4kR1Er +yu4E2qI1Ft4F986FtCZirp3Bz4VuAIlcfWvBrBS9j2L3MBdJ6OCzVhSiOEuqk3nJ399aRfv+isR 1c13CSXqWzIT428Mj3tpj5tVtwnv3O3ax9YhHm80SUgtDl9CnAmk1FFPDjRZN6rkhDrNaI0LqdCp Lv3Iv5FIelKEKLt2xxm5fZLmqAmrkKvIEBCeL6TpTcuysvJ483oT/VE34U5j7UUC/aK7/iA0MnPD ZzbO1WykDeddTn7qiG0xDe7bu1mlxv6ZNVxp4Q7dLXyuXoHFTECHdrYozk/vWOXF381+G0VJqI8Y PIGPzaNRaFvEv0TMZLIzSRnf8fiT3zLOj9GOjzUkomI552qSMD6BiMTnncfj9UOlJqljftSsrOGm vi+P9qw/xI/DnqZ+QjZzQmDBw2Oqs4+ldjn+zTk2n6BXSj/Xg3YEQ9YnZRsJOWKi8uZ7nKQ+RkHj npev/3zcCpjdXQfcmQLJkP0cZjGilxUjgg8ZeND6TmttVDawkkrdlolLIOc+NU3wDF1VWvWZANCu BgsrWmbEaVGqi3MZWSOe9zwC7eGlt1Ybltyd1NmJ5ybiI30kfGRwYENuDHM5guerTOWg4//ornbS MvLx8frjJjJPwJJxDDShlTSGJOtYI59GvrciuIE5KeDPpD+wLEgW9DlLs6qRIMMDxjgm6ugDf3p1 dVMJDINusUaSEl+aCDggZFIomt5RbYclPmhtxDBpcGPKAFID3l60/LDmzgemlWSqnUg6r2vtZxut hq31EksgJTaoFfdBaH7htpOMCuEZyXyxT+ktvIVy9lYDoS5xxDbL2NIIvtVXneCS4bs3X3sCFcQM pdnjm+Y7+gxkuT96uc9FeAmXpMGzPZuWAPfySDxSxaY967U/VFXEJNJwj0LwxWX7erjnE1VQsccC rUC4nUZNZmYq5SlkQVMvROOJ7OPJL4HknNUdLs4KYUqsDShGu2IpyodpLMg7/7wRc1LyimSnxXoh jo+36ASss93bhOj02UofTI/YjOg+nCpMfq/cZbQeuH/IISsPza94ys5Xue9NyxQgLD5fur9grbRw sxQJhP8QPrSbkAx79HlHYX73cWdLxwqyN/GaJhWTIZxNl1Y/wqt8+GcNR4UEKBjst3CV1XSrOqTp DF7yfiFs5GXjudosqFraARLbPPiEY9YdUpeEJ1FYByvR+PV8IxLEhS0J87FkgLp+4kv3B1P8DT9y 1m0IK0b6EVRGMpxZrKUd+5nwc5uT9vY6O6wFfK5Iz6jMkKn3FKpEcHZu7CWwTD99ejdy3fDNlz+u w8PwgIzA7gfGiwgvqnXG1jrwNoW5F2/23B6CafkUsmOaWY5j2vY3XofJOXfYQ8tv5KFO4waSrKhD 10G7w2+Mwl6hqfz1+lOghfsQgYuWPXjcQysiPTT6XZa9OS609kDDy/M9F4FM3dgySkmceDUE9uTh DJXZy32NVOLKbCBEo5pkC3qDY8n79jLmiNAjcl5OsLKlMQvnyVgiMHDUAwJmwwWl60ZqLPNYkyAN NU7yLKGMkJP/RRvlJeoI8MqzhZR+7IZsZD8XfIu+zS5u5rcrOzUHR5zZduNHNpDHy3AWDJHWBR++ Pa2d4RzdT8LNannK8xYlMIKUYgItJ7slJEXpg+md3tzDaK0aRXu6fg2K8krwiwZfR7xr48t2dAnr I4TFMvD4pWN5s73PIsOmNCei3Ve8WQDr9n1KdMsyMs8aezwcH09wh39RUw3ubX5krzDRiXtm7cRQ cGuY6r9m4vKFj3xsX2OuMBjtJiFo4J4LxHq9zzziZ0THKBE99PXYPlb4O/hdznaUp0BF16/jG81Q dO58uI6W/vkd3h4hIBd0fQXRT1KO+a6dRlwRMzAlAAhh9H06iXdGiRsrmAvs4yaphrD5lfzL6GZH Usd5oSWiRd6xZABdc2YABnhd//Mv51AOYkkl83yt1ziDTmJtbOKtq5KKEoS248oNQx5RiglRzRFO cJa8y0++m09axz2o038WVOKhRwRRtDoSe0nTSee2GbrjipVqIjL3T6EOHyx8l0xEnWwSd/9p/Y2b GgeY3bfdo89uzzv39S5FDhffFAiN9NMjIkWXLXzyvB7kRu3vGRYNrnVjvVzVRGmXEec+b1zLOJ0F 5Ahxgc9z9TfqBgN/ZtHj1dPPwrjUFa7h0phgHnnJSFsDCc3MpqqKwD0Phw73lWUfPSECo2MTRRCb reO+g1cboCigyMqAqHl73rOMfz2NakKMo7xXtCv0VmVYcG5r9ExPWb+5Iyt39QI0F87hPKi/esFR 37+NDXWpgM1/E2qFqhsk/PM1d7y5O9KvDrEgQjFq77oJf5BZYbJc2dFEDz/PEPweOebNRpG9ovii tT+BbH5EIc098wWedpAt1Go5X/MdK8USXifZsIUMwOe+Oj5gpSF0BhKbeGgKl6ocml6P1oMv1bEa 5OCOQC17nZLPc0ruXSqOui5//WJxV8SqkLdUdD5hyRnuZpGk5Wp7eU+qV1UWQxRJznKICMFFiGiJ 5jSdQloMCsurbasaHHuRMH+kIAvFDNMoEMRI4XGd0zpaeOgQdBOBVY2Irw5aynJQHj8PzW+iO2T5 T6aY8DBN3lvpBmdGSNUsHv3ZPkbOXhq/myDfo7Zr2NmgZawYdYAPvUsNHRcvmpAw5J6mkzbpAthf HLs14XVToKEpEixNQ5if+YxOzaTYkirf5mrnCeP9FUT9f6AKQjnAVrJnkSETX8gAvXU8PEp2lcaz 1/3CzRhKrEz9eYYgin0TaaFEPkoffYV4fK37WCXW+HyS+Sh2vAyjqq+IrOyUj4w9IeSyiECQwP2W DC6U5Xl8VX+fIWoavSJ/ALb/SZe+JOPFUpk382ar0hzpDkF5dp62GKOnq29ZDUYvwacnMVgxEC+3 jRqcjrCwFn/4RdYGQhCSFRSoe6b6nAm29/VTo+aOTr9U/4m5pB87pEnCQAG24LE7uoLXlXeWorIz h87DSgqK2/7pU42QG1gxpaE4u1NfvpGh66gAb1/pzYT/RTA2RkdwjopxovYvdipTXUQIH6dqt/90 ZCdLSfljXH8XvKPmpO/j/GYVm3+CMRAfYeTAlklyRpsfL1crYFA4p1eBM29e4pBBBIbdH28LQyxX t0Qmc/FiPsMtpbORhC84KwRw9sE0gj/As/UGIuDCkhdWPbO5SVhsNwRq8cwAvtlKEPY9wecVf8O2 o2tgTNagkLMvTbZRF91uZ9XD//3CozlKpg9iKYdGxM8/3u+k9Hh91neWgzRHMkJ48QQF/aka+yd5 ULnpg6q0S7pS0zhphZEjeEozk4T9h9rVju5Z0YlkNFgLNznY0zkjGSxFumTSgsMmYxZ0IJ/t2GTC 0yX9cMb4whMADHHQou0Z8hLzA7XOX5Bok+/fdhqtcwU+HiAnWd0MuWZm4uI8Nj4SrHFpj7kCu7t0 1HAHmm0I5f7q9wSXyusg2jNEjPpDKWn5RVAtyBZHk+2i18QgoZGyVhBQ6EJoDdQaUmz86YaiqMQB f6qTeVPrQghjsw9xMutMbW3qEeHph0wxJ+T30gNll4xislR7N2dVkzFMhQf3OShMnH7G6CzqSuVW yNRLNkr+CUnTS4XbjGgMKvuCttmAj1PvumlaNmu/T4y1AgvkLw6bRQX8Iw8nSSIynAVRUi4vyDKr Xo0hWsEWZuvOKQr5+jtidU9r+IbFgldvbsV37hGcVTVU9J9pcX8cp6l7XCuH6ik6f5/faq4mWAdF T8563asgElFJ7agsY8XfyAe0Xe7X31MzWqGlo+PtfiYYvqRFkKJ9zO7KU+NKePH6Gk6fCyUtRJQs JnEH0L4KSigNBgwTfvS2y8xMTyjABrhAewwaL/jbWUX5lB/K2YhYAE39chLUVrK2vJMhCpYVjdzR k5F63HERfI/NnWxHtith0+IefIH2WBApjVVA8L3GUSxtsruoH17q4kEnMlm5E3161y/8qifKW77c QZDHL4oeT7PXIVrotLwJj2PqHACQCORBpH51+OVc1fV0uo9MgE1SUzb/YtilJKQ7XUHyCuIdLTR2 sBB2n+X7+IAfO+3Fti7rs19KY3GIs3bpkBiipL1Oav7kHL6kDSpgWEVyUCZoFmtrKCTTi6q4uKKj 1dqQduoYsTJIOa2GCeBmUZYldANKwJdx4YNIwB8UnIqorK5H4MAs4hFraD4UIOIjOAepqkQNr3fs nOQfkjUcRXmaMFQTSTGyKgq1PFY5MZUn1Wk79qbpZnZFaRDdp6zkAHchMh1pXFkmaHAKeg2YddNx eMa/jpj+SNiPhPrO7vE3V98XT40wFhkTSt6SeitI5vDcjXYR7KwRpwnOxsRTLdoTiCSvAkEDVyRt 1K8lB3aeQmvi4C8DaqyWwNy+KysGW+esPe052qerq/ZN4TCEyPkhSclgvFSlLchLVBcocogodT7O EO7dwdFnQv6vd6uN+E1gmXMy6y469osJ0slQKI3eSy6ff5y4oJ2sOvW+CVl9lE1nCukL01uMnmbY glzGearHGOajoIJQ26hGcrQgjdk4Qij4uxmDaklb9ORiB/u6CzyVlUNHiJeu+TkBpj7431tcyS9Z 59XD6PX5uqGnIL+PZ07cv5iDT5Pe92KaqbpbxlYmBOsOjWGvStsInk7djvBROMvnz2G6zHoSuzlm 0sbKHjJIAF/ptJT4Egay4MRSa9jqhHGClYjk80+ITadnQzQWyYWcBfWAK3M5m2S1egsB3ekCCimg U4eMYyhl2ji1g1OdOsqh3dtQNLgO2uhszJaMttnQrjqGAcs43TIZIFSo+OY7bKw4o3bpwn4favPP RNies/4GHuAkU3jpR2h5BueHSYLZMta7zqa0MhBjd6NNDDn0WmiuVdZc363G881Hjrf3qwcLx4+r ZixAlz3rL2Eilec8wRlKtSO4vMZ2/biPJEu8Fc/ePAjjHCzcdVDIyXLeuTfSJs4cR0yjqfI9juCV P8vMA00oYOoCocwhqrBAdq/lVXr59fsus3oVkX4Ga97ilapdguXvzR7uhayHxBaaaht74NILRAbT WQ2r6z/DH4cFkpbX8UU5TU/9sHfPprueZmr7K2vLu5TeSc9NcOqSEvh7SpfP6MEa6Yl/j/mnDYzT kaEvzt+4ZhWrWRCMGqqd9cj/mgsXgPAZKPETk48lvf+Qkgm8v2nN1PLc3+WbeIhuzXOBHdeSydSd YCLooWJGMRLZOpKgsKFlNOL/0p+cgFk5DmTp9v3ZcqfCHf5QunrVauh+E+SHDzhHtPSPya4Di1N/ pD62/e5JoFg3ugdzyxv13UcrahL1S5qP3zN+Oz+CPEMdj1+2G4Vibk+tegcPoM4BXPAyNPx6RVO0 hLdsqku4bNQbG1QiEqH2BuMnuHtm9IjsePZFX+njPgJupqN+mTQwLOP/cTzx+B/d3BxaWPEunrNr QESwQ3n7nd8E/P2uGN0eONm832lAOwq162JUtkACngBfufn/irPaVZVg2Uu7Kt6PB4yutPLhXb2K 4jwX3sPmxMdRbzTctKz51M2+COw/FyyGQKbzKbpw+8oDSafImn8Oq2R0BHnXLziWQkjIvrOQS0H3 fJFbrTognX4c2+2B/yPXcTgcw9Nqty+jZApbJaG/Sf9DNTydqESizsehfSt5shoSB8gxWLQZYPOe caLWIr9Blq1EMypokfgALk+6xeGlLhSbmFUVMC2oS3iRzvBR0BaFzPg0wL4y/srF6E4GvnzfF8tM 3w8A6Hcji06ufeF7duWek2NAhCcmI/LWzNnLUOd1b+pq/QoEwdViDa3Tq0wWQR59fyOUg0IZncFg d0NuqXT02Ur0lGETR9o1B7jn6Nq+Hb+SeHePyykIOkRLUFIgsaVXVjmyDPgHcpoA3UCb0MV5rIuq mFkqftirT9uhYRIGkpHG4htZW8t8LIbBlqHcLCc8NjpvO9WfzPxrw5I3ikkb5+w3EG9OwFyXAxq7 ddGDrUNTuPTSVdLoqivWqffu9Grs1sr9aJKHuvqcLkfUsO0meREBBxJCjivlXFFDtohpdVBpjuv6 vc8QiwrLYr8CGIxL4NnbnPWFfv6g6N0le0/qSu75fWyIVQcNKoh9RsAb0b8DqqGoVQaPxKCK7VKV s/9PV6JMvX0YTKoif4oPidriqfPLGq0WInMYf6utOSI8SlCFUX1zuuK2LX6+bmzQFDbuuZWYlVeb xgLx32dIRaxAGPn7Qa/PzrsNH8b50L8AUxt8tUW4g5OXw70TafYVVxCurq1AR2MmsnbrU/ItdEc/ wiEhffLQtWXqoYY0apU7qiMQvlKVr3gUNcoMNXH+ZIWZRpp/h6z+nTbrggj3R+qMk7nyO9a+UcB/ tm5PtK9GLXYE9sfG/98C8dmYucZKT50hf6o2Pp9IoflzSr/AhFLVD0KDronK3ZuW/ge75YP9xyFY LUMkSLldFmsaJEkY/IRmB7fYLedJnWbZyZ39ZNmh4RCnDMuqMKTHYgjW3EYGC36iV+OGGFzh4QLJ krKOjP8llOw5e8qM4+dILoVbCDG5yvENqomAS737JRZcE6AGvcsiydyDD+RHC30bx3XVSi1vBDGg Eyw0xZ4sC08QGqM/zc0R7qwxAsbR/E2y8nSFftIyo1EW7ieBNivALcuBCzAjKXt2cUg6MT2Ny7/Z D1Gl1iPBoV5Z7pwCKF6m9HgK7Z0VaDkvedlSqgswvBUDNpW4Gv00ivGNkp2pm80MYiwDtKpa5yma 7OKluiszd5msMS3iBIM4KARHKwBM6kumngWP1cCNCYNCtmiTWWFQDQyODuPu2ezmfXp8BPCIW9ZO QEnZZzgNZwGs3A7JQSCRJr5gR2A9v+DS5fEDMhGSL0rMPbSbVu7rGs/Uo3o4SPTyWnxc2o0XWPgG plaNccrWPr+OeCbv0tKW+Tn8ijRUAS7heTt644a9P4CtmuWZOflCPMKm/a5umwFoUXBtmuqkX5Z+ 86Fk1UckOIw5gD4QqjBbvvMLYHkNaOGeJoj87QXVsJUvWJjKK26L4K8fu5tfoTs8/0NbMOl5u35v UYS5D+UdhbS16x9SWeJhxWDT29nZAMBdemmcXslK5ZiqhHx5voICwZrG1cVpBx0fvqG6nLV/is4n iyTbNUD4G2MvUW0xTij+Sz25smofsmLQBSpfqDFscCsd+vN34ZAZBmAOFXGORa0UQCAZXFVdfY+k O/POOqYav+tWi0V7hlLETd59kBNW/N1XqYl7HxagX/zKbGaVmGaseNnj9AGlmN8dN9RHQAG3PB// MRbW1w8VSlw6NhQmDiqLhbpeAcoS/hj6QK8uBe27U9Hmi20jNXpQ6348rWOOr4guMtKR8L4xhlIL PvHWaC1uyKtEyE3v+AW7K6KIyb1Ljum9GP/OBbu4d8Za6zOFrKeJLG2Br/MubC/HZjyDWVuiPfnE FTr7NvtCJRLlz+DqtyOpWzkeIhQq6jVwmxVkpQBS6+SBxm7qePB84uRpQX2UNpx4Bi/w+OYhZLGR App7sx+KTzCEJ3wH4tScyNDwIjgYVFmXIaAUQf2itxS6rSj6K7SWnphoerdXjTns4oVYvXznuwQY 6CMlDR5JWZie2cgmEVWzhq3t/mEfjbw0PsFTv2uAd9ESujlmzBPVCPN2IqijfJKIJv/IjbXOWh4p nSICS6uTMz1rLg9D6bnxkabQl4mBxRk5vUk6XFw66uToSZFIIki8nG/NnlRFG4NOyBm6f0l+6YNX g9FdpddT6TqTxHICW+7GS71anW6rz2Oz3Iw3nI1oXHV5ZWXygPlIGRsY4IVEy4kvDdf3syimeaqr 80qPmgfoZIfQvBPcM+eQj6p8Rng4i076HmE84SpNkExYlTZAgGKO6MWigtfIjI9xR8S/un912b4D iliVkfQSgT/lnLOzHMkOaOiKIIttj+BDD0eDf7hNJ+fpcT8VK2ucGafqTdv730kwIBqCJl3iGM2J e7eBNvxNuvSiy92gPj4bm5xg7rOnzoYVILZqV3ksEtxTcfa8vpzCNXgCuTYU5mDTf5Iyooc4Q48d aJ31aixzJZYGe4M764lGdat/xjIIZKhqkonqhCRIQo74hh0svBnVGhyeIlOKgE63WvWZUB52MzCT n12kxzq65lCBdXiUM/RRoOUJpWmKu0DweXY0YuqmggFTMMtJf1vbBSgytSiWsh73r83BMh2EMQ04 uaIuxeVAsH0pPhFAWpyynoUeHUYAf6v6QV9jveoGuYaTk2N5TAxz52ymzWyna+eV83yXKf5Omt6Y 46gI5ImOYhfi+UIOlaEFYrYMrTCMv5a2YbMLk7Kt8Hg1FQXKUZr/8qAbj7RNznzcnTC+xttpJ83j hyd6npYLBJrrTcjnmType7BOwVPQUI6+Y3lHOQ5hSX0w5atzImS3VOEQmNviLlfa9LZRCVuRiYXQ Z7ZWbOXignlLo0JxZtqHtyMUGYdf9vXvKK7cbGPQzPMM2l8QLh7nwBPiGj/5lus6o2S1CDTZQq+r hCXvOnAp/9y/uEMuNlVfdX3HhTjhFRvswx/KdFdjBCVvJ+PLaqkRzPTjKJzyJ++TPeimlCg3Yj9j k5ayvSM4I1dxuw4FkwS5LFEEZQY5f6H14oxlEUPwJAQHNDSN1GQ32mabc4gl2R2+wU4WKwVDTs3m zLM7NDCPa8ozDjmtRc2JO5MpZXZd3BZJXXyHkuOc8IRjwrVi/1aBs30WA8ePNOxw1obhXq9ZGRIu 4vNo4UzxhVKzOJwwj7UN4NLLBn+U4uPpS94KSV0S/HmzA+lpQwVRg546hKEwPSVtSCpNGrdqw2N+ ZgWL4LZCeLb1JJVyFu1BfRFPwyWdMtiLEr0zC8IPi2WYvNbw9+XRplEB610T4xycgOv9tsCqfUKb 0gZcounqL33aDez3JMDMajKud1TbO+XnIPePLxKOCueX2sX7qUIOnxdVq+0SrhCdYCXmgcEcAKBx m+1vQIudqCXvLfHoLZsJoHsG1MOMgnbs2l6J9qQj9M/5wzjiXslnSxYKaCIDFRVmw65MjtfPs2tq DQyZUR8oNh1xRhTEFf1oG/9PNNsR5JgMpIvVyx9VeVLcCWm7H2CTi2onoaGzQ40W4381d5FdvEnm Y/PhlVaOj4uYyZt0AqIiUNC7NEL445Jh7sKLyWEWOmzT87Kke1kmG5aWsmNKq8pRocNVfnzfGJ1Q VgPBlceWuL6Iili/MDWRcHrRXGRDiUURaMJjXhoR5/aUaYrkfUOQqHKqA5EjmqfGwpIICZS4Vhsj 5Oj2HvG5YPAR6Qgbrd+d9cMa5ml4jLgY1j1PCHPHT3VEzIH50Z1fHLmN0kFfdO+5HoZnaeXme1kM EYPTI3WaViNsYur6Mjc6uOxLockOvicWsjORdv7h8t27AqUEETmkeZvOnmhxt+F4RkDkMI+XxuLX sbCIqYGkhq2/OtQyhtpFygztdvzj6wcickO3wu5fuVNfzdKiM+XysEr9k2qT+zu8574Y1M4t6UvT VzftBA3wxmbi92Opzw9BfhMiqsflr07jV5C0b/G4Y5a2Yza9M4O4OjXk3R6iAujvrQpoj/iwp3vS hG9749NwEltGw8Hs2cZ72k6qB9sHJ8UQT4AKryeN3akv3yp+wf6vl1NlUUet6KnFXnW4c+mdVgH9 34fpdDCcITKvpgjOyhKCHZLkJWvQNNYuAKC1X57LK/SLezkzZGp3/iDi6IQw6Y4IDdKneiAleTCK LMleK9eicbt41IgfnHlnDQTXomksKJrzubmYSiS4l5lGXvqP2aNn/hp+j7wa71z3XhoIgkHxn2Uq G8Sw08p6wyM2RDn/sLOuz7D5uDkKtTrDeKBULFRHreuXztc8j4K/c/L22qmL5wXUfOO777XRZFBB I95ZDmJy1ArmUqzx9vopmd496uhoIRTMgT9zIVC0R6zqry+2QPbxbikk5SvjYhuHLdslo06VxIcV +sjj6m2SJkY5Y1pSgicaCHhEambTJ1Qbb3hqWWMN1amAx4mvKzjn7uR1wK/jXpmWITpMh+cxzPu7 DgQf4/XmfrlMTnmlguaqsW3GmLK47Lq9bectls8Vgkdzxf4CadpK1gm41aalxEa7+aSiAzJ5Lfpo UvwwQGKt5n+GJvxlpmIVTsCIUWLNL44NEYF/iQElsGoTfHzcgTuVRyC14A1YZf8XJuTTMOY5oPz5 rNiMefv3evBw1I/QFZmLC9fJQDXRiOvHIFpjxoqWW1dSYx78ezwOy+P/97QA97YDLWh+Ia/fTsLv /2UT9vF1YIvw9TJNKlyv736R5HnnYV4she+5AiURVpL1CAfoKGL+/XLPgooxLiWiSC16eVA1F8Vm pywad4iwW0laPjVijBLWEplnPQspVGvl69Q7/7V/tld+94NYsNJseKrab9Uyw0IQf1Hpp7sPaWBJ iHqW7c+2VU1P8l5M2XdmY7FC9+8iZxllY8TafXFY9Oq37haso9BSoPNl4jpJElZGNoUFzrJo7gR7 IDJXysrs45hVtiF8rw2yaE/0XMUaeQiwaIskrE7DqLQBjKz4p8cVm5D+dFbNvWbabEGqbtDFeVIV HGhRTVcvLOcyXbzGVCZpFCf2bhDQjsDqI6XUOdIX4aSP1OXYCCOCX3CB3EiEjumYyb0lkeGd2F8f kwAzbPp/NbFz+9YgfkgStdTaRPGS6vXxqWfiarQomg5W0lOLplXyVStAUCrnnn/1ogEyQHMFefRc lizcZLSH18ZimUSO48d4kKaKlsU2RtRZGZc8/oeVzTNMeODCWIrLhlQSJ+m2zF4RyrbePX5R9FVN I02XQ2v3lAuVuncE3BSF6eqAajkeqXiOVRcL8vBOjDSfS65hVuURSGhpL6etV9tjgQUnkqxxyYdW CoCXSip8v/QwJiyKuGIdomAS4PDOY0Z9LSufwcUn4bicIcImH2Ai/lLHEgxZXZ/DxxbbepdfUVH7 s/wnlROgCD/6qyhMY3cqbOx35g++gNfQjdO8mzlYOjhjWgoiHuHTAuqbUYK/htruJ87zXAo1f9wF mx7rIdje2vrDgcrSyAGwFm9dtJa+qXgEh19Y8d2KjI9DOasdrGWeExLupNL807UkDeTx57lhngiQ h4q1zvlv/Kp1A6ivNiJI8OZq622sd9NP674IofcOZ0jpYJ3cnTQzESFEoOS7ODPI1MaNTRkqLJqA 4WUpBHyXpILjwbYchEY6zpxFyY5ms8OQ2OWtwabIZzpWCFViGDnfMLwQcegWYlZ2jz/z9hIddjnQ b859QGdor5451GMhqNVDtvaJGRYOG30OQOGB/oLJtU3KNmk/fnK2ln+gUVAuXg8FPYNwFoYdW89y 2TzKfkBivtmdDL3gV6R+rxtjk2F27RPmSCQcU/QZnA9BV5kinIV8nnZNw038ZYmQa2yrahiifmpO AeLqterowo/pT57rE0A6Ce4Glx58tiJEZIWZUmRXuyCM7qdjWsPdIn75KpmJjMZxKno1Mnf9sRpO iZ2UszxcGRj1/QLjYfYUlRbIo5DWVtEiEWqZQyhrXTGNDmkR7lD4Q7qzWr274Rr4Uwj2oHDuwnHi 32K9Tw6JLBZ9jq28gLgAu/QbDpmwoUXm/hmlu/jCl+o7UP/KWM7r4bZ5Jhi3/h/Gow44Kn88w4qq Zoc1rQyLIH/+FtZDLohyRH75Hnansnba+j3AtnQtYqOfQA5pKO7LrsAejxLFGU7DkibwUEvQqYVa eM+2anBXZpotHCI+2Xyw4iRwRUuaRY+xCUHNEK/KapM7HfAjk7ftQZrKynj5mqgtJBsrTfkFP8Um CWCAcuFMY6Ke5xkV5Re0Zp7MV2WO3vnn+AX+iOYeNXInP2HawWAo2AGKMMci+87BYFJ66rciWD5W eizpXyw/eHVdOxj0bwHsWmMP28dx3eG4Qn+S/hgfufF2YF7bERg1G5cj37pr05SePvzAWw40Unu2 w+6NEOGJThVThiABF5I7f7NzFwNXo0VWK8vvRyOND4yxewuZ9RoO1mjCkeZrXjpA2EMc6fOfMSAK mdf8bX/fITrcuDoAl1CzDw3sE46+Tc1I1hke/w6bc52DmfnQLwOuCQrG0+jWhqnX9b9T91s2EL0N 0r8pAVvWAHPaxdQIL8fTLoxdZA5cf12dvaUfLwf0DsNMczuCbSUjMA0PChzcxy/klLnZwRSaaPs/ FlvZMTh7Zc+TQs6Cj/HMh01xj5+D8zXZhhV3Ob/mSdl8I+5hfQznyN3MbmPGubVYP95YtAZe1TxD I65q1ha1sw+igaTHvDX0pjV+lWmOsG70qYTMv2xyS/XILTG+JvktboBvz0LcfKpzfJICLnkDa9a1 1w+JLJq5sIH9VQGhREBNYGEXqumG5GvxhaFZSSD9xcD09t7r+8r3V6VeyCzEBVhKVmBW3uRmIlAT cNXdcowMVV9aFh+8110XGjFlo42dKdairvmMy7lk2Pfc5YWEY2i276N7gc/emPwk6G7FJ7Kqbwk9 9LUouWZoCRx/KjfL6JHJYzC4y73pAkzWsL+Tur/iHozQt3QvnP50D4enhGOjVUkqbQr9UJ5vOSj/ UjPZhY3cTrv73/s16ACWULt0elQdSW3mUbeSO8VygE5vwN27l6rUw/8UZ9dpDLZVIi1uhC6dAt6k uSzR4BJ5WTATax6gDpKJ8hKa/C/81WE/lqGwTvrdb2dmBoD2QHWZRefqMGktBpHi25xO6VU3UG2b cfwLH5WdUH7yJ2BA8GASb6Vk7JM9m2C/cXZx540Rubv42XKwrBifP5Zw+D3dixxaenuWFycLKy22 hQx8Vtiho70Rx8c8ldEzvBd4vfVu51jIQcqfFdMvMv/bDUwRwaiHv7pmEWvqvbpCfV9p0ug6vd3d KnG+qmA7CQWzcaq/1VufWPfaSwfBH542O9D6ZBI1h7FlJYgrQ683AR7J0Q/7KOlAgOy5C5USaJB7 V7TqvE0mYBMQ90pQ6dOOdzJ3rTXMRTYGbhxCNq4ZNU96oKsjHwtVNxp+9rRuSLHfNchQCO/BMaWF 6mb0bTzyf+kBPqC7gGkqeUegGzPiTVgsPBEE8FDly1nPwodVlFF7VwKbM9wXMQ9+l3Av2vBOrT1J 6KJEiw9Rl6g6NN1GYQr2/3/nLIsWJL39bpXNUeUAu18ieMAMePlHlNSk/ZhD/IeNF4v4N52v23on pR5mYcnlT7F3T+Ib7MtvXyZqw7viofQbnP1a4IvSRwlardJ2R5tPzwzypd7+ATcYNxrv7tHdy2oW TZzZvtQqGfJNCuzYi+jIp8Qenn6uV/JpEE/0OGz0ZBock/fl6BRIFKfhQmzFTo6+RdHJcfIf2HVA 2dYkAVdcBQngT/MbZmpXKWEx6pcVSXskh249Q8WIv07szDh5uciFD4zMgG9+DtBPczQcyV6gSvp/ 1Okugu6LEQ0v1tgTSUQRFV4xs8nEa34jY5OECGtfieWV4WKabQ5gecQrh3Kl/k2O9VmLVCy4k/Nr KMzHlg8JPE/QSNjgUl+IcYzzYSiuV3kV0CiTm+WdfMl7kpHyYX8t63kiU2p2Gici2FOZAZDmfnzr 3sUFma98lOca5vKVOKWHTlcoWMea4hfUlhjeP7cSFr6GJ/Ey3KRNv9PymqH10VhqxXFNTWKiRk4o yRim7ujUxDn4w+luKz5fmWFKCHu5Z90INh5WpNGr+vDB2GpjT+8obbbQvwk4qFcXC32vwIwcTcYy R/r/+/o/trK2y6v1ZXDHsa/PZFnnhM3c1bf+JwX/nWFJlbLx6+pri87ICuCPAFVj3piReO4h4mwp qoNW7UkexyeCJXLSf+HH7LbJeG0gPX9rgsaqdG2qq0DRYnUfKC4ZU9BQjVsTr/dx2Z8Kv6b5ELTL T+Ax7a7A63nSaB3JdEWot7SIdBSfN03Gxsy5A6V61RpPNtvEd/cyxLS3sV09gYDPv2MywvKySErU 8QMyN+9JcBWj4qM02xXehzf7jHOGoY9xrhhCWI3s42cq14D1ViRPKx3RTk7GfuTl9ZAlk9YgC119 5xRcV08E8zBOeJqcbj7bhq9hhoOPKi8LrGI77ONhdrHzTMRSuM7f3s4zhZMTW6U9QJU4qyYhsqxs AZlvNn5BOAhdG39cYBkePp7uqqsw+ZCFy2/8IrkeXShPlvcsE5tHqMGQnaUGgvaPqpDIsIlqCrmQ yg3N4BUGKECuluVPq+4C2INcRXp6kyYHwOYFx9oZjXkg+Z2UBMTVNyvEBIgNlDdDawXKYykMUxGh KofXuOg1AEPowzsXVkv/DiMZaBQkRBGNq7r0pIShKd05k0AsE6uvLe3HPUtDFwQPMH92LnSdRvaT N5bO0IG9FRLAPg6nOkh4Ux1RWUS+e/1DOTFlKgMxmKXrzGKsWQt0iaFx8t+gbbRF3wl7gI37aSI0 a6conuYbOP46zWiClp+0rgjsTuZNYvIRIX4naQa+EM8TdQIS+iqhDvbfeYVVt+DAvWvIQaF12YhE bHPgKhaxhdQEPH9DwO4BBJzjYm0FyTMQ1zfYiqG9GK3Am/rpDXJOf7S0xLHmH8f8aom23bm6JRBD pjeYnHNwLRRwGbqINhtlMD8GSODfmn/MwJgjmMsTtN2vNuLqvpzl1sT0VZDL6EP2x4x+yjIfSqb6 ESTWM6XHooyQGquXTuWQ60KljQqsPie6BhgjZlSEhNXZmkCudSrP/dbeM5+0gVNJ19B7aMPjTlWM cuFU6meImhx/cdFVUTauBhvy6sF2x1d8Emwx2nVbOjqJ2oWeuc977Ef/LwKBKmCoJpxdGOe88crS DnLwjCLCbi6S5v14QWjhQ6n2Vs835cDDpT2ehLnC7rQtDRyMOuEfZOyRZDu1ZHSAKrCc5y1rZd7B Ey8dqAMdixvjlVbZKttVITGN3OB1stqdaMywUNZ82liy+lmiPnlm3QqmCUmHy6s1ouslLOpBDrHG KIzdNfPBVVWT7C7laNQJPKwhIzBxMVSXPctFIClPSTS/8Dz5NAkTYFf9Eaux+GblvQhlOeC+WG/z L4z0/GJ2GfRYTbUnDft4UdOm9K5KQEL7w8q4K0wVknUp+vepqtoTunIy/rWZBySQnvso4ymRPurL jEO2lM5IcFA4hSvhW80cJKt/p6yiE2Fr8vGVxGvvjk3Hr4gOv92PFxHj17Jguvs1hcgdb9r09KCy J2ZaAmhYBylUZxRb2otgEyEimXm4Gs4szZBICmgxKFdrKHTfOXOcKyq5fez7dlv5d95cpd6eIwk4 Ooxx2OqsdPcuNerZkV7qWJATq/TpIAfQEedCKNaNWJuNFzm8IgsI0H6Rah5bR9+VfDGPF8KtwFOU /F0r5D5v7UuYrSP650hyT2P9vXSEygNxIr03mhKmgvpjIOKDxwgwcocvCh5AWUgiBxKS/qDFsJjH xVvxFSdN3hppDO3mad9pAWMJaegCOL6fF7utVKTZZuExWC/SH+d7eaXdGAXxE2guNlC8oF3+M1gi A9rQZHBz/WS03GfafDf0lFuOH3oylaoWbq9oNgJC7qzo5jXLD7Sx/g5G3FEwFIcJP725RfKlBiJZ BO0Wu0WU9KNsZgIb2HayMer/I75fbpP927qRzbnEzsBMy4a0qqslGGteavWCZ60IjX16o5rXXQ+c 3PNz/WVPnYJD3Si2R02IWSj1bTKrQu0Y6s1DGrGjVEP737V3xPUzIEmakWXMziH/jTI1m3ZBPPmk 6J4P7ZNyefezYcV/hy+/D3BNONrkMgu2gC+UOvfLvsPnA5etfijDj3hQ6YzWYE4RzdCV4gXXkhyo AOeYsstiJc6yfdGjSfxqEPkYrk1TgitvivQQ1Hot5ovK++h3bICIFaVV5QzHk7WrTenW1KAZeOF+ F1t6aY6I48o6psiDldfT97QZD2GvjpV8bFhXLjMOxQoTm04ZpClbPjTNKFuF/qsVb32lAQiQ5asO 4NyXHCYBXWZpoaNo8SiQ63QPNDvmv5xpnpm0ruHwuPEk1jA17cXP0tl7jD/iVSQslaQD1Ccgd3d/ 9yTL2em5R5Tijd3Rhj1piQOLNRXS97xcFx7Da4vN8RwKJ7ujbsOW9LoeA18BRWxMqMewi5tlqXJx qUAgMj6q5ERkStDpMblI4KMict8JIaXyUDF+zI2dhyrjOj1wS50hrHVZ3Ns3j08ClncK/xCFLfOe faFlaSpg8XqaymQdonLVQmp/ucPg1BKbdU2ruN0uy2qyU2hHWl7B3IfPqTALwPDa4CK9BY4OEZOh cEZD/ZVdCDGls0tmqYwg7RpmkA2PGLixABWZnjMZsGC5PH4UhLvkJR8FqU/8fSkl3ZFArJbN3mbU jcAsjg4sbbkDBLJlRft0Wuj1fJSa8b/BQ+5xYiEsQHWZeZpLsgfQdwfHH7YUnFduRQAfqbPmiGBw oUok2KtQRA1PlV+f3m4Pkizh5kXNW7rQGHjtal5gu3POzogG9eToi42w0oa4dOgqwQckPBO+dazS x1HwrjZJsL0tHFfk5NRIcVFbhGDDbLoANa7RQgXK3cC6Kz0AwAAvLJvH0i5ln9P3WFuTemPKjUIi Mk+0r+9ffDfA/M7MamdncYtNdNxjX2fgscrJkFwaBu4HqgR4zrjgrj27aONO/bDHkHrykonJQV1M EqyQwvQf0wCliEryLie3O714DKkKYhXsVj0dmfxDDrQ2L200KXMW21/ccDsDUJntGQVGxS3dG05S 4x682lP5NpJdEr79sWRzmx3rpiSclmHS8/qO/IjEkBsN6P9B2fl8h/IWjaKhQ2zjSGVpFoJUceal 1QwT8uFxC4c7g2Ioe3d6273aQQi7Kphe9GThKC29cNtmdJnBXVPrse3eeFV06dO7yxNjcU0sdJ0F Rh3KtXyJ+Iu3lHOEsQF7vyVnx4Pkg7PHA20taXcM3jEKnzANZK3Ujf0JhQzAFM4N9VHq0GqqCS/f oI1AyxJjEqcd5jdBq2pjqx18S71/VOwQ1nHZ/xACqcPme+XoafgRGVqZkbeMmvJKs8HoDTf8vjiH 4XL/MZlvGyw4F30cv8VJDlpBaBCRcIqkrCmUSeyft5TiLMeZwkpeg9AvorYcmC3koXJCUf7W3kFB 8Hwak7ZDv71v3H+E0LeLedHH+9Shg3SpgPDyJA3HgxKMTUcZBe2gp/pO8pmQlvnBwsY4wi6RdfgZ Y7x+9uykqxvKUrH1jQUIG5gl3C56VFKSgJKX/SxpmeAJZFSViMXWyS2f+1v+tqYypnmQDrs6K+KB ky9Q+0Y3U+t3a91W1hjJZS5bd6FYG+CdS6m4JfmhyG5sVCMHV4tSM/CLUC8sHK9V69ImzqjBVd1c Qlrob5leoPXYvS9WFHqNYYn51Ijy1J3H4xAJ1xAu3m3zi0h6ITnI8ZU1jMeqsDKaYTA0RzOe4S0q aup8MfGlWMJCUnH0JBex0Xyqw1t3MMV9/Nm9Y5GGFNlE3yXDAA+6UvX4ujB+Oj1eD9A8aJ+tqYxi +LYlLDLREJPGmaoCoYpUhEqPFgtjGsDoJ+U/7fxB5iIBvUlihnV2Kh0+YJ2zMmlS2tWMrKLh2A7Q IUNMAZA0t1FzrV2RPFv1hpBLbFbJXd+Jus2rmwCBjGLmuTiRzzxlHxmoq9Y5UKZ8R61EBHmtg9hs h+RaagjjNXaRzSi1vVu+nzlLmqfpWYhnJ61EzxVeg6JZYLC5WByHPK+2zUwRtMc8KLMml50u1kB+ k+fw2f4AzwHPSS9UhoW8+93PV6Zg0ayIGA1qCt+M4VJwhCtH7aLVRFm9K3/uHCOyFxHQeLzrSilP r8/H8/7J1Iqu2cE0rfF8BtTGMoZLvhLf3ePrxanHjFWb3BXVkAGbymsuinODRC2xoyn/2ajSyVlR tLkQxnlRl2Kwenwkh9+XPguRmj1P6u4kEKrSPTJSsN+Yqonfpi9/aulgJWasisZWwOPNZ3BfTEsI gM5cyer/YiEzf88PSw2/5ZgIZQKJtOHuVTIPHMqhBGNAS9eTgvPf9O2rnH+Gypo7AMKb8sjUERON Srs/44YAlix3ZdBh7cfSfVkxxM9uBL02lL9C5QI8OBBQ3ahcpUnZsKIx1nBp/wIkGVbPIpv61owG bmePdvuwr+zMlDD6apxGdBvKNxe5xdt251UzRY2peu94OwfqZTFHdGzP4sJRiOsGaLPHkffa7cqH zqnrd0mQ9O4PcmAmAdz+kGVz5X4tBOwOAZ8j/5wQS0f6NQsIk7sqC4d7fyJGxz9FEHmUFq9N9Nw6 9rgtZrDUS8nDludolyu61FicjtVdyW8ur/f8EXXcZK0Kh1JE9Uh/+NnsqLeaALgSIhaW8db3uMbt QsFOwud/D7PFTiM+juA4y+2bpR+gsk5Am0dZ+zsayNeqBllHeNc0zyvQB49ig4djk5uiSdhKvwHH K1+zVrIM3w4N/bYtvBLOmqi6vuvLaCT8yF3yeu5r4GrjhURxGGj7AkT7uXF1kL5QqUCTvWIP8Yz5 OYsJaU1NNuFU1gK8kaIlsrOmYJijWvcgCxinuxSwfg1Zw3U3VI5HzBCgEK+Iey1T58BrPvTs9lbj hSVF9Ts5CYSTgpvT5M75OmKyrPTwFMZx15qevr60w5evWzYBCZCUfuxhf2lFkSowLvm2j20fcBYI 1mhgDEvXvwRryVca4LAVSlG2TblPbJ+Y9QxKpFMoUfRFW5Zz8sb8YkSWjNDaT9Bc300rQMPGOXMS d4t2lklBXawwm2ryh0FlDJFU6WdgWLJTE57PwFHqgIK2EySUHLdFYkwPvf4VIa2KH0ODdVIb/geN foQd7tVYqenyfpL8g13bGtN3J9d+4mffl6tMWzAWoIc6Z+w+wChGpzg9NYEAF+PVHuvoQ8RtH8le meIVxTWs4jYl5A4ueiRe/oD3tu9BOLeRrFgfwUpcboIrFeMZvy1QSHruItHHfeJK2/0aWfpIzVrB Q/dat0aaXYlW9RTE9nm23tPdYPzb4U3ji9B+6shzTcoXN7/RbSdFat27sqJyC1g++vNVBzd9acQx nqeHMOPvSBNE7nLzDelSpvxXjArjBqGp3f9Q4OvlJ/s9kU/WnmpVT+Xjntmv/EYJo4AJcjhtQNmX w0jj30ErTG15CYA96ZMP7zmowlOEFIvVQpu3OT60yShmqd9cTokNHVZ1vKDYhBLnBrKGgCd7H8RO 70UwoP8I/zcPRUWkBr2yCWyxtyFD68cT0rYe6Fxwkm67e/aAcN6IamtuYjq4DPORjiqfD1JPFGUP EwccP0ruiwDSKEFaj/SlZtP0iV5dFPnk5ANT9U2EZ4raaIydK37ywFgr/X7n9juLaLixM27PFwNO pEOsh3h0MmgFXW35hwaLv4gmB3pTxypnuxJT2xOU6mZBZ6ep6UebTCqZsl5IokNMCgQUnk1iXsLn mhlzmOGycaOBhiGc7LzAXjfF1Nwlxrwy7hxzykKhzGaqgk3jGTWYW+bargcEKz9QUTI+W4mSKi2a S0ymFEetlhe0cq4dpCON7bjGVFhgbpvxZw2J4Dx8u1OEd+7dp3BoYBJhrH5d480dHuotPP6sJ43p ENZ8ilnw7HQnqbvFDe/EJe7gZ9NLyLSwmenvGCn3gZudokCApvB91Kqk+wXaRDzFCx2/z6Fae/Q/ AbUs4heic0rUpPOF4tlPZrWvN/tA4g3EntNUUDQqFLpUnw8nFhkH+0mSim1ZG+baPjqLXd/Rxn1B hYc/bj2j77j31G9QDvPkyP90FPQ3iND92JIUJ1CA6Jou29Fxa+r0mO3fet1RE44e+yRZuA2cMtxT i8IorWoa3e9/4KTxbcTazQWHsFwuUT3CHuEGEfKj6wRx34C5CzbeUUuIwGPNFQCpCriRmRSPp7Au T0N/qVOJoC2dzqRrs1Y/mZsWjgQG2AI0AkZgj+OP2fpf3mvo+5TYs9toM/SXfwqql7JqxLVP4UF+ 4IYap5a55qxNyHiR/VjnGDNEKfVWlddyKvu15lpJvtppKu6ZCzqIL8owyvjIVB0jdX2xP6bRl7Wl gOSc7/9CxW/uDStvNn62AWWmU7qNqmCp3qvgCj27wDaFv+SXmNJKHT9xFBKau0F0m6jcCr0SK2np TM/laMShTWzzT/Eca/xpjkCWHky6HYwGP/PYHGDX9MQ4r39bbM2f8y1NgkL3kPBAwavlBJ9xLLec lEtmE2LXbR0qlXm4B2lh4rhSYk6EnVpBNLrgE0TsL0Awzlesm0X3Kahe0R3qvakMPCpwu0l+kuJ+ C0wciPvgVdTFvm7duLdcISObGHdybIP+uI0QEoBo374GF6ZRsdWgfRCq0CeW2NN1BGqzRdVOy+TB 8wn8egqc5JXInOAOsSXmp4wN7VZgcr+Q4cZId/XzE3pOqQqvYOWY/vUKBvcrvrdq9rTlGoYeHeAj 4wsDmUIpbHVIJ2lW3zbiUXnIqyM9O1MmFcTeRsPeRy4CSVOfamkj9mW1Tsz8IiA3tWQvlPcYCkvu b5OD1HyQ/KesfVDnp9JIE2c4zbjbN8hISeZ4V5DSf0yPxPn/TWTgSVPPIumud2BMonrI82m7Sob4 IfnFjbsfb9UK0xrlPqpHTgKh/g5Zh5a32TAHc4QxxzwJBbXXI9GJ1StNVKauRlSIGHSqBlhmLax3 3hCQ6PyLagEnOXo//EXs8ULMDILtzxeCSUpP0WwxgnIhJrRISlEj7p2gRBR9jFX9VWXUrmmZbVPy vedkUgcBEiUrA/Ulylik2ISUET5xZnjT2vflmoJBQHnfEUm/gEgJbt39AYnQXiykAxCvm2YVSdmg b3KFaElA9O/pe1gL+lqoGVtbQ8uqWoYiFtRs2JJNHvjAId+/4JOlCjyQcYTHV+I95GuMvTSSrGEf ygzNMU3SrLNIJruE83brmmXHMPRMmUVtqh8wUlSdJbjW29vyZTX6Ew7ZdYyRasLgn/55RMySu6eK yRlrZzwV6LrL/sVCvfh0ARDtBK6y8+SsWUGPDB4Ko8cgwtH2Bt0AS//BqgaTVpAJn2xnsw2+UZbn +bnW42cT5FsZ3ds5RdWrzhsakP7DIWB5fbYQRsd0Ze+xLA11zlOHrxd7phxDITquggqoSYQ9vpaz 7bTeAV6wfl+czDlFCJXShezCu6WTC0jcuLWkRL1cPb3Sb8N3cQ681SirW51ZsA/eYpeJQk0X7tuL zDMROeT50a2lWhqSHKzGWHff0SSqCG5Hh20jGTuW0bNHgm6/IAUmtAhcsPkiEEP3mLuhSOFLUSDs A+IZHeu/JY4KRn61I7dO2+Doj2m8GF0Pob9X4+3qsaWOJ3+ulQyI5j06/OOB7TObgbV6nMc5V7b7 r/GBce1snANZ9w1OsI62/LaaX+nhgA1/ADBF4kxIB2SV2MfLGF9F4UgrY7KAFZi9htNr/VlhIC5l WTr72BQDeuEY3XEBCRdGlI+h1DgGkLhvwZVvKzeh9BYz81ySmIrz0PpOaj7i0ApXdo7Oa85B1LUE gLPsNvGBnL96s89NlDand+KnNnE6EgpHQ5GZA4yNt+azBKkcinkbd3vAYAYANw5K528pG5/yijom HkUynXHxl86mb9iLwjKmux3IKYmuigJ6hSq3lQJz8/a14DHxsREwe/bOt+DWmpXAnCTDY2f9IlCb 5zvsnIEamQPfZeA6z10fjx+hTtpuWeY8OsOpBjBj5SS7+KMY3Mp/NIZv/WzCP80h+lthnzzVzDkK UdrHRQ994OpBgRLj35wTbbXrCOLkpP6DvYqdjd7m8WzdRX/OXHRA5mVVTKIlQ849eCihYYg+4VpM 2nIFN0qbjobkhFaS7bwaLXt3IqF08VC0TTSgBocbGVg8+Sef3Gy/9XSw6uWODHeNx0E/LW2Tx6B5 Tu9kEq7BRr+ACGNFbZsDIzCmAH6Oaou53k4Fqz5CoO0JfnxaXoE1BQXwnwwS135H6XgNA9bB9rCg 9fZFjoDtQr2fgk8T/x+RflnfqsaXgN40TZmFDqs3/3f0W2cqoHTy8WlXBA4o6U5k+1RkFrUGUev0 dc6dSmvL45Wx9tVVZYok/9QWCv+vpSOVSIDUlEaFwYVezax+andkVn9WqNM8nIbHfcYorMKQbVrd O7RBkGNHdd6lFEzTw2KZuMoDQrvAWgLaXKzCUggo4SvX+0ZhyQYfk7P3khXFzSP0mUkPe1PLxlzJ XRoueeOcIyNO+TYhXwbXDxB+/6x5qOBaMnS8cHb8Ik5iDHoP9LBRcDYMXv00o3wA27+Xm+iYMB0s VHf0G9vcWjnvEB/lNwQhTluUJKFfK360hBHgPaV7/BsGQ2hOdRlJtNzES0B/V6JjlWVo/ojIyjMM pcAuZqJasqZRAbyf5rDWY+JAPadpKbMaEQEF9ynFKXpKQkGo/N7UCfcYmLtl4LdMx+fRDVPL17RO +lbmIFyA5hGAAHWj3sq8am+nGBFOanJsyJ8KUxxo2eNTY0C4RUpS4vNplOZs60MkYp9gyeyiIX7K A/b/YiuQiLScZnVZ+IREj5KNNZanRW3ZbtNH0I3dFf9C1Bs6ZeQXhzc6aTV73YsEctj+FRc/VwOp a5F0yyplNVwQr4URICJ4VXhiy9uaS8VY4xj3sgG9IjJUsFIkYB4cPKuX6yxto24TIvVIxPitB5oL B3z3PJvcXal19QrR4tUPgMEW9b53L5LJoJVc+3YU3wSnmv/8sA7EUyW/AxOYXuY5O/dZbC12614N UdbktQPW5plc9qtXjrWJqTl1HusbQowVOg+hEDMGECH7XlxB8ZZHkqe+CVIVo1Yqgwr6CQyPVogs /+pWwTlglLnw0jCNoScraKSVIWt/KC5cXJbJs+9zxUrQ8qKnQqaQqjPJHE5H6nBIRjRzvSy3L9F4 T+bSk8M7CNPTlHW/ysI5euSQg6gtmjWHz9e6xfqIFtDmYVs2kytXAe7Loku6fKIrEYxeCSZYYR/N sxyOeie7JCI0FaO4+ONuVQetNEHkZYIMtc8IFPj/tjyGaS99oTlY15BOhh578/a849NkMHnZ1Q5i 48Um4i6EoDm+EjwwzUGjLV7sIKnnGPjwRsSqo54u9voT2dGeb5+i1h4Ft8xwDma3XkFeBEpD4L5o mYuI28R4KW0gltSyIvBBSOpaEnFyrHf0AqwkhIcjOQ2fwkOChFfNdyU5LL96D2jBgIwoaNwJjXCf m7XCnSJNz2WxTdvaLUpTjvA8Q24WjBO6mVtjM3jCkIRPeMlrI/ey6mhG+irKTdfPROaXt+8zUEkQ 0SIZgWBU/nDh6zfKu7HaAhFu+ZAN2ssTiJpt3dWtFvkvauFhEEU74J36UvSIq+60ghOXBqqvjgze gdari5bZYX+cHmMR5u9avgVCelpAWGbNvoXeDXXwgXzLXEZjxn2MH0t7ZOqz6iLahzRXihZRzXKs 2RmBLGZ5MhOZjqEeZ38EzpzBHrpWIZQzdQvbdnLpSybCi4V0c50ZA5U9cjK+QSf0DKSsEpwepg7g ZbOzuVc1S7VqI1RonGhCzDO5od9BvV7XX03m5pOAR1ZbfVwinYJtLh+DxgXFl+1ep590zNdFdXFp s3fd/M9kyBeuPOP1Xs3wU27LhS63n3pekl+YbsiIDwPwb5oEyJU6XCotNKpTUkC4y/W2CP4qF3S3 QFNhKyS7EyQVU2m79Y2FW8IioNH12b3LTVQrflO7f74VByn+HdyCES4/pIJEB8Kb26MKZ0qZ96dV 0rNOa1FeG2ov2FzdzSjJNpfD5tlbLzd1vX2SNcUcpnWYgmtAQdK/m/izhjb4lf6JCXD4a0kymVZF Sn5xrYitLUSlR/9dLUpMq/ngHMMJMm1OYbHNoh9SwALMfir2wqrBpG9OwpOKCAIo+XSASayhMtRs 0MZMQTXVPEKWx3fYwpqAw3AeCGn1YZRuLzbcANwWymG4V5qThlEWg05iCW0aSawXiHbR+SGanIve wfcEkrgqQCGFdM4C5JfqB3gtm7hR2K8gFqZNpBbA5ya/QfEZeAdZgwVEVcQ2UO3EbEXIThKljrb4 L82y1m3zs0o3o/rTDV4LZPaRUCz4RixJmq/uRj79MP6w0gWYd5IXQbSa1XYL4mOSa4gNsRwapa6X BFNBCVbMAgPSdaprofbTh6U0kuXZ8yBod+4CRzNrRYbnPIqYH8I2+n5JHOaKhUq3t3CUjQ62TrkT E5tBzYg7JK09wsihjicjQcrh13wBa+JcH6XPPUzb9nHJvOdGCe0BLPcZcXaeVMdHeXAyH2g8MUQC NkKYEav1uckYOs3zAKiQxxGdFNFFX4DUR5xFLEFH6QoPosA9D8p68YWrn/rlDLQXzBu9zSIw4Z2C sqIyJ+ayR6hOLQFZDBFmFxP5BGXQR1GkN2chOcpIVf4b2jXyzzuKFEITKiQAUvlA3IU+nkSblmIg YhEcOv0RHBHl6is2paU9QkgYJABwbCzlMO8wilYMC7fLu4CwseJjcviRY/1IXi+6LodojFK4qU21 PpJzQPPukJye3KXyeHyhnENbtK7j0fdXSNdYJfB7ZWIfNhT3MpFvx6qa8d8sIPsO5QzjvGcsQyeF iBw9iMOLC3gfhTyOk1g1cBile98AfU6PSRsnh9HPWBGEaSZ/ryaJOSB+ODUaE9jbJAcFHVMw8kXt nQ6S6WcpNibk/UU9q7Colny3dOnqulKmwNcy2LND/flZAtZfx0FymBOw/gizdd9YgtnPYbjr3qRR eU988TZbvsWtuto+0ERVrgBvGqVVTb3cnmYbXmfxhUQFAmR1ut5jv4HJlhbWeRl5R2yEzU1iktj6 ItBAWdG5JYRgsU7FJsh+L+hiAC31u13H+uAOunkAifyuhdYKQ/SZNJsCrpOCGJL3ikk+z6EriqGi cRxUFIyZqmHtfzD63gQXuykGhYprHp4CM1MUQ0V+dAisFOnQcqFt0Ny7mmLfQYRsPX9f+bzfqfmx jn6MBs/3RAHGiKEagIn2vF6/c2rzfny5pVVTdPYPL0Ybsjsfmdn/BuzT+//uz3cAICbJwf1aQddh MRpVoS1eCGW83siMlqu7PmrSyyT68BeIPlHHl7NGPN8gAi2g0STiZ95IAVzkAsNQrGZy5VGDbyTs wsunyNHqMacv1EDr+8+ioVs4yE+aMvJSmNc/VKY+GCr7O0VSAMblTUPycBWqodCagfb83GQ2P7yy s4WXMtK6vf0v9NXv6yQHn8cWydAlCEzUAFVAZ8F2X+8N5vdw4AOHZ9NyvBbe6LZ+8wNnGifEDf5J /Zrc7uH21Zd7tGHQhnWNaHl/wb7HVyZjrwadfZoP0PC2OL6E+5HQJXSm2R/4tErRUrjwsaMbdowq R4StaV2e+yq7P2ZSb0BeFP8i0j0RmtGX33z1fIvMdXxeZ5zdQZ3CkIASj1n2kSh/FKaIwvXH7hU7 J/mQm2KJvVPV+sErhwNcBN6Np8X2prEZaPgKDFNr7EgppH6Q1h1fu8km0JIFJTnttZbjyTAIvYAw mchBfCvGbuX3JixCu9IiSdvXew5EdpgshFoT1P+KWSDZo3Uqhw8Lv0D7CZyV0e5Gyc+QlT9lh+jL 4eA6dF/RTLuZJ5NuYH2c4h5UR4Y/s2poONJjmtQFcYcYAlC1t0p9LF4gvH0XwQpEvD6dIHHQkz8+ u2qw+TCNHObvGv+JN8mIItsjuExFCud2IgQVgT6Bi5OKUUhCg4UqYvMWj9Q+MFOa37wmAo6727hq 8OotC1s1f2yqbqi9hhWtPI1LXd/N/gag8fJb34GI7uziRo+KGz1iPnYRjW0nnuee1PL+LTWxwFP9 apja5rxyt7xmeDdUBMq8oT52uJyHntRbTQsD/JQiYiPu4rdfBjjDtFKFO0kv40ZUM0cJg83ckrqi Aj9WeT6cNPPJbqA/+vVO+T0lg25mv6uXEHNWUtuE8/7H2Gb5ZxtnDwqgFeNvCCBPNXTJ3mo1zs4T uubZaczv9Nn73MCrQeVl7klHvNGYYuIaQIks1m0na5pHw32/QEk12A/uaiggn2RVGZy4YvsvQ281 ZEL2zKHi557pgbcbv0Tehx9VOO/4B0l2VdVjzZbnAKNrupRBnm8OhBlor3wQhRA9wFBqZmRIHcxp dIJ92wxHl4af63cqqYuGhNJ2Yj9dQg7yVZTh2e8fS1lyIzgAlPDk4Qxwq7h0RVjY/zLkVVHN0h/U +x3qFX0c4c5GznHw1MRBUKzlLB9GZdXtrl+4p4E5zf1nWXafTNR5Em8nxzAPO7djCdHV1fgnqY+o WuFDl2ZjOyJ80b+se0QJ01XmUGX29KRzs6vIROOhL0iXPNgB5Fpsv/LSTX36k+bq7rlK5JqVku1x mpSb69YJKO1wZLA6KdIQ5G9VQkhHiAmJvOSJWyo7gTgtYYzNHF+6uRcO0uU6FL91Tr4dR+1kWcLY +z45I4Faoj/2oxy42alCNeONHAdP4vkObqJbpZhQa320DYXq72IeKeqduutR2CkabciK4lgBzQay SAJHL1aSDX3dIz6GD4DbGYiD3Sr03nfMeEtB1kU5ALHTvv52A0hJvcuXcPIhIMMrduzCwlEro1+L 5FeUpyUBt8l/jeSq60sWysXfdBQgtEixozC/RWWHM2eOu7C1DoXGwf1T8a1iDAXzhbMxvS3HJW2t 24CzyURMjNY8rt8bA0hT0uIP+Fz4bHlC3gBlQl+wKKWmXFfrR9dzS+uN6g92CQjI+0I1X4LH3KPO wp11ERtIyby54U1lN9A/W3UkMIOMNfgRTosxQKfZy/jPDTDkl/gax2tcFh0TblgFej/yohgWwWGV ZBBrbYJ9bd0PshLjV9qC1dIaGZDR5YbDr6IedgZVs5slIm5Q9ZnniMEo9sYRlcSC/V1LkoZw+38o /zI/CReNrSr4iTjqI6mJehvArLxidjG7ypkaDVDU9WvyB9uFxYnmYcq8RtyHFBBJ/aI4AUrQFBmk fkt+D2PUtPb/57w4pLTs108pJaPXR7t7v0jOiJB94A3T+e3IjPeOq9t3qdkBm4VkByXfkj1ieyy+ x1kZwO+KSAf4kzB4aX5z8wPl+I8EnJGzW+iLa3+J9cIMA9/NvVzsLSwZQ2DWC+6IuKRf2/RI3wzx sZvSHucatflInVeUvh23z2cKc5jUn9tj3fdzmVxOPE8JkUi4dTPgA0o6njgrfDpcbG5FB3U3lgFI YlsMCf4b/7uvwIw6fLqHpLhMR5i+8RUpA6cwXPifus3H5q8jLyjU8Ubq3jJQO/L0k32Rm8uMt9js 4dZTxGWk//0I4pSeArm9UxQzvW8KD6sWUmYAz6hJGCRsVyKdhJSTdw9doVI0sWYWtidyY+uvRt8N LtXZ/Kof3LXpCK1o8kC6/F6TpW5xhNqX3kwGGddlY8ONQRfwv0XUF4qvB8chPc/spIqVAKLwqsU4 CqahAJyi1hUmyhk7tTH5jfvAd0h7l54HeR5OgdUtpwbXmHI5HfZKeDTK5xXCImjT59/4bp7sHZD3 ZdntyBit2a/oGQzvpvEgc6koNS/hzaVE7MFH3UabhU24WE1/FwyTYW4nSx5tPkS9nzhpmimfWBqe MO/mF0/AkQq76oqsTX/zR9ibMvXKDc8Yy8OkMHhrWohQbYhmechkjpv5UZ2eJL0LAC6Y+rN94fpK vhnCKvJb122Zs3euJ37nQwJNXrDPEOoHTn92xyc2p+L+v+hmCAwMePhIJgcUMxCpo10F54sKwQt5 10fqSOI8+xg/1a0QZ4rvF3HVpcGAspON8AabBfoQqAU3djmgdRT0ysxMW73q41ROilRgJSZpESxY CIbBfEw1zS7fP+VbnnyUicEm6EeTqFBGQq0fnz8AtBf+XiDY70Tk+lSCb60zg3lF0L6GA61hn1AS Mo9fE051rmfKPjOoakD8GgDQqLxGep0aovKLRabvd068HOgecYkRaZU17mKMRKLc1pJYciFeZ3zj qH40gnUr6WKY3AX1Jn+Kh0QLHmV+A/ONh+yPBUbxgiUW720X/xwFpCkjaxJCbxidLeB97zpmiVeZ GqFRzo3o8bdyU9pK+SOMVoKPJ9eVEjTiQ1Tmwlm1ryB0QdEX9RgmGwZMx1j+UC483l2F+fWosJkP i9G5Aed1NMKLH2top/dMwOmsBBA0Lkz4NQ/dk4R6SCDpCNFYFQ3lNs4ahSJ1lx7QOyIzjacGgfHx nkp9oq276R978GcHmNuXVzkSR7tJJbE/RdRhr+4V4ZEzAgNMorsLJfwMykFqlrfrlzLPlFRChR5i wpK6tNFXrp/twR7/HYv2qmTNruFVXdGjB6qsoMe2naptmj2nyRTteMJMvI5lkNwLiZnSoFT515MN sbYDFM2tf0RiQLyEW2XMrmEiVs8zrn7SZRTVuhxMnKD20X11o5c0/PSpzh2qLSoyUNmfzC5PZRPN 6aNzgLcIJwScO0nrv0OLjNxwV+wazZRsyxFISyRERg8bWAwWozQ0z1Pr3vvJStmt9SglzfTFvsIR HQxDE9LX4NvIGeMrxxO8/3xKGXcBMhlXPyGJaihqdkNdjs6YJDWwXUUlSqgxtPAzqelyQOQkbN9a /Uh2/PXERnp9EHqyVmwFpCse4zWH7PjJ0w8+915QAxxPSCh2hLmBWbP7D97fFpyRtl81oAWgnEfV jjmvEARSuFn5Z/Y5340cdEejQqfsTrRk5StIJC8zFTbW9XnLZVbWzAItUS4ZfW5AN89pjQ5YhWVC l4fJ33dajhalhTgtvYgOd5SngAg0OMw3RfhjvyjyEvPUWq8VJluWiQNWyqG0iNcqmDp8/4kH2QVc n2EtYmAaiLwmCwHX4p2q7A+XowYkAUM2vEI2XKobNNSiWskg35C5aolSMyPKOe5oWtHJTYjjJGAf q3UxN9Jxx+YkzvTlTgRDaJTkv1EXDxivpiDVjwCLc1bNoPv7nk3TCKCXDKWuv8uaFlqGUIzbrQVv IOz7BWQs3zaIkICSYGHHBueyLXgNCt4zVtlVh/aaX3yQDrlL/91sPK/SdqEI96sbjTKy5Rys7x7M opMAU4snpttVxoWSUraYzWTnx0y5AqykzUf+UrlCsM0vfPPUX75zH47hch97pTMdtHK7qq819/sO slrlKp6NXZ6XTNanxqW7Qpn/OgL4q/lN8H/T3D2N4bUBLN2rN+wSj2k2DKTSK8MX0H7lcXJtlOQe kMnZljYI74h4tcViAXRhDuDZHPtH/eE2PkjsvvOxgAyhc17SNX5aCnPCb60dqvxnSmySMkCE2hSz y32BjvOTNumPcq1C/B/38BvlxMTWM41PeYiqjqEQKfL8LTlG8bo8ge/NXHK8Y3HJfbXhzOX3QPBh 2eMd5tWCHqg+vCC75TTmD8+k4mPaBYnqzD9loN20Pc7jmu4moFN0yJAU1FNoiiqAGRapwmjBnUwt j/nM6xCw9/Vgj4d/jgIqn+VCkvgkGpFI0RAIOnL4/gDNTCNEMpazQ5pwAE73+Cn1n+6NYamVme7a PXJrXS2Ls3a4gLHU4l1wp5ujR0aYNaKDMGcusBOOwjZGaKNK4HY39vEzwY/3HY2aUDG7qC0lR9T9 HYsohT2crgKtsFrDUxM1Mqaps1JX6Ac2uv/bb+LHn08xL6XmfdTL8NBZ6q+67A3nbb1yoAO385Oi VKnEtlwQ8F8g5/YXCAS/+7uHFWA1EmYpl0R0xsykaHxOpVoPhoW0WIBlqGEHs4WFvOD5hxR0X8Zv dQYXz/w0YFAjweo3vw4j94ZeUYrD1TVUxplm9Tvmy4YgL1Fhe5cB0RPF7SuxQnOisMgCZ1Iik4GM TsI9zfO62JxBveYlNELXQm8xWbIoG2tTDij2M4ir7K4nKhr97ulD24zjVVaAzGHcPOn715kjCviq q30Be8LTEzJaOiNq+xMU8F/SMylXX/sNJasKTwtutjZ8M1ggYCPA5q5AeNi8jOeG40D5/G9TFrfD YIrldlQoeBpCu6gZUXWRAgRiqcp1K32fSmghfuJBOGXKSYSHh7iR+AHHgYjcBZtdi58TigijnYvR l0R53qaw4FM1mdQMGdhMSA/tiMdq7FmtqgkGzA9VC5um44Ilv2hPTnxbXQHeMVb39QPdlvsSuc4U NILY8Hh4v2WXMJQQKwXmSwIu7HmfHQ5LFVjCwu6UIW3+7wc1Pcd95h6fI9ARvP4JcHFXteY0nTVn Utjw20wRFCX8+6l8PJ5ex63Z3aAIxlJzOEoUh4ygXaRVVLwTTGSJeWAcxGQdlahZNLapckHqRVY9 YYjoBcA3X1rogEBzT2rIO5QjO3PUZVInENfhClT3VyBVKmYrxOm+E2F9q++dZIoPgviX5Qaw7s+Z S52gFq79wt9r7e+sZHtHMNXQnl3dE3h87DsptKGFaXCE2PqQM3Po3vnOZkujCSUxwP+EaQ4vAN2g p7uY7Ear4E0pm3TZaeBhDxwBlVsN5wkE1EXcBjnKUQ4HsVUI+kZ1uIQYIm0OC7eHKStMUeSw8LPn 5NDTxi//BJ/tCR8SowrLkqsapdR1eaEMG82Uw9QskBm5msNbEnoqd8iPiaDpcuFz1lHNLiFFcyK3 JnbUyq5oNwr1He0EV0rO/hyXFb4u4cU6EWXGHtx1FQpaSbkaiEbqJPiMZlTGv/8Y1/eBOJnqM6jI vGkoQkN9vqTlGB3WXUy6VcN42S0TnpDXJxRpf55ZZ0ow4OQbwOp4vgctHV22s78qzGwAqnYJvkSa xsP68ScHwyENOApWb7R5DPbeTt4JY0cFm3Z8RJ2uywfqMOH++8FGO5G21Rq+tFA9pYgICQJDUhN1 cFIrgV4c6CKHXQrTbsCyLhNhVlSPdffgHuqD1q6hxnPO4g9spiWxYz9qQajKLoeCGy2Gr4VQfnfE twuL4QdtPIHYuSlp8Fo+E2UFkKlsOttLntN4UTzfv9zlojnpDBwUKUIM3phFd23dxKrQzbP4rLeg 6m/Kpt0eJSKN0XTi5Nk7LofJf6+poxUrY0zlIB2NT/bkWap9R87ki26OqQPvo469/ElzkBIwFJZC /7dir871ei5YHGPKeyxmEWUg2p9FaqqzQO61pOmPGQWMf4gLv4ridkAXgJeEfzUxVrnqUClGw+Fo 1dGUOajTq3S/hQ3J9eFIlwqGBKM8PjjQuVy80CV1YEq8sEaIRAR9XXhWIFj2MXvaxnAh8u8Rdk0n 7i7/Br5X7k17tgRdjKuPYAs+tquesH8QmYaAkvAHYvYNKomDDpmm08FGW6CcOacxssvtXUm6bBoi ABo8wvE815yz0KqBRsZm42AJWadX04n9ubKyuC0EKMueclwMe/le7VzjejmG5/YukFQ9rfQeocNK KfePSU1xBM9UxbO3LsqRUfID6q6UWbv+oghZr3lndusX2njpFe3zRJgdwCvj/0bkBJvyXUinEiJ0 4amCfSxjTkd6qC6nKHOcpYphe8z//76AbGsMP24e0y03Y97UKbr9avNw1GP2N2zXSVdrD2RKL+i+ WU+skBC8dTo8eGi/mmMQBldPDmcXONtYSOAATzf9OMvvADwnJrR8ufDm6xm3VcXWdv7Tuggkn2cb ys9DFanSLInJIzoL1zPnk7SwSoz49tdVW5DkaJF7WpTVE2+4XY/LryBzOThVnVPelnzeTCxlbQb8 JkMvSqpKseHvp2VBVTf7K+EM3qMM33HnvHvgDz7wemJSrcUX5CMHmi7+bcW8yk3Uj7uoU+VU582K f5GxRlMNlBEX3hcGjU0S9XoISu1VyUXuqp+2XK4W81TEC6Kv3GtIuSb/KewdBHq2scofsYlGA/sc yfdw4hzQeFJ90pOV1/BeOAaoCNGO1r2o8QINqlioOBoNB16BVxO8iY0gLYWL85kHkU4AgInlPD+S JNz/5ER7vyqPRuUNFQKjXh69xg8R9kI7Mcx8fCtKlcfSXrucgn+EF52C6Q1+MMnvjQxp1dUb4Uoz yHTdHsfs+QdptDpLrMtdrRhZerLjJ74pGv8Zc3OoXMhb7h6Exm6haUK4XaTl4inagE/6EqJ9W69p 37NVB9JnRYWmbnXBX3Qp8sQBcV1CafsLys1XPnUz3y9EutAC0Un9m2w34pRb/N9QBa7Qv7dJOTjE yne44yOe+mmW/vPWV0ECR6oyHFl9sn23NrBpSYse2S9mTX2Z+9avB988Ar2Lr5HMRC/23K97RGyZ NsVAG3lTE5gq4HHPB4c5iveHjcjux5CcXk5WeXC7FyLhaJHDtm93119MRyjIyDcsYTRohP4+fz07 03RCEmzfmsrTEFbJ2e4yqt96f8cK8cuDQbRa2gHXCJS9vHzSVDb0eRokvzoZJpFA48snjY11O3Oe lFF0jRXW96nkvLzsXIwX3ITYyLOzJjGqQJVrZvY9vBZrykeGpGZJ10d+cH68wkLIdeM0XQ6XjEmz ODmUe9gjtq1SHdPNAongtmDWYwrnM2APiGji9mikhYWuJIhJmGaUwmUq7dmuqjD0gPegVw59ehQq /AXZS130idMX/zqsCT5w4ZNvPogyAkeaBcsNVzq1ae8w95gy3Yragi6rWjbsv1cubAXcSPELjMAA eCyXE/FxOxS+WSL968AtEAecmG4STgqvpWGmgJJtgY63JELg/DvvCZeTKegOfs7Bl67L/zi2a8z+ r47tHIaylKXK7E4RjhMRJxFc8meWJzGdD+Luahonu6HaNaxiHeQT0V5Qlq3Tv4AM2TioV/+eQ6WF DbQTDGLAKsZJjeTnbxn2JDJfU1pgJ56WD8qsUILM2WHjgjGwwUfohVYpMZVNTP+eiTqtaaybI9AG PA/5nct3kkk5uzot/34IelUjL/3qKf1H4iNnKYu5uWsxjI3A8ZwMuw9Z3vwk0H2ZMP6DIITDQvIq HR3LGEGubbsZTF3bZf4UPxnUy6JqrujrJVooAmEALtPnq0SsZE2YzTI97JH7NCfkqZFerZhBizEZ W+F09eBCwa3wsekyy0wMqVZFrRrvKDghopmj/TYEZ/t3qHbho6VIt0aAyOd5QxgGTPmzhHcDKBQh 2TUc10iwJwMRNcHibWvidHbNOUogOHNquvCtItH8rN4/QfOb6hHbJtXeqVEbM9564jS1i9k5j+CE wLh85WUN9IhT6vj+eqKedPFl6TDmTx2OfM9VXBzrQhWOG2twC7LPG8mRFIT/8SoRTG2vG4XDvVm3 0ypHei+XUWNbwLfEqIpvJfMLWpyVEqixopD7W1v4Lg8zXRwDPqFZME2JjvnzQkZc01iLkEK6R8TT kRWXlNjOjAujWLvHmu5RTdrrCsyseP/XOAAVJAXQA+9vWxWQjGU1aCAMdAflhF0FK6JCAtB66As8 jcYGz9qKbYTGqmr8h/CPWkmTgfG83+Mb0jsB/Srs5PT0SUc1VW8vTYBw7JbUNaNOnRo5IYDqADCg ddnG8s4QDaWXvc6Ch+Pt1TUwC2ahQ2JXYqxD6X55F0i2Qz3L9yXFLXSgrCI/XDqsRRt2TahrEAHU rQJV7fs9gzV5r6V/szaC6K5RVqnzVFGVqXySYdge62oYzJBjrn6hEilx6SnyMwqiZNQX3BO/iGkj XY91+b6Xoy3nAbjAh6WKOKEjzfp8ORBA2NmV/rCX34EXtKTSzHR81eptM9u9afqK7foBSLXutZQK QyNbxIqlqSP3wEFCwrZmqB84dGGLzcoAWNAbTg253jA2KNQ+9AkE8ZnGHlWa6uOFeP7xyx5b9TbF tt+SnnihjvG9CbFhzKzuq8NEjsdaVvlub6YZGBf0W77X8vo43tF5eXhZxHgDGsTgO5LyNMQuyBSZ RnJ3cOGO+LiLBZ5iJHshQZApFNJzU3Wp/16OG1Xpkga9ZKgsW5qFT8U8pxPuovQaOFZulJce0+UU LBcinBsAP5hBCy5EQz85HFI0V1kRiXPTYBsGAT/Kg/dGBC/Z8U0+D25DvzCO5Zz5KVevc/VQ8wX3 VkpEyPcRaZ8FCxTL4yUrEifLOP1fSt6N0fZq7nVA6eXfAErs5qS9cj+09IsZZV4Rkp2M9Gw/l55f L0X2ZGcBoJYC9LPLNWnVgcFJIRquxuDWnXvMzGcXJpeeOO2qTl8K3LmpJE2xgUQgEgiLA1Kdj5LJ WKgUXr8qAGcZzpmnyYxzjL5/GtEC4R1UZWwpxJtfbuYpqkvESBgGpo2v0nihp41LPBF4ESSi5sYz FIr/jXWSk7MzEalNNxe/qTTovM3o6DFpIgY/SaBAmaaZMLLfA5WlR057gDAeWf2qnp9uu+Y4LO12 yRPDya3ujnkRzRBLYe7IwA5f1ALR9bg0JngPqjQ37X2QSQTf/k11O7Ph/RncbgIvVsJXQjMJCq/u jKsnwK7dVSSbByIYUV1Mg+IqBL2asOyvKf+IaXf0NxPrfdCcgw7uuMnyocvs1v20HMUM+f6OWsd0 o3F02JqRclQeGmwGCP7gFXwaGcH0MNCCGF0biGbooVH+WGlsQLJ7o3NFFBVeZNluCfOqCbv9vEzZ PutUDtfrgOEqo/qYdNroJd848mLDRPN9FkYg8DVRi+j64DlSJZB/6MCg64yuKAO6GDLfaqUSBvmc /9C1vMf4tbUdr1R9j/p9JqzQCNEYT1xEmR6ipQfuXZ0dy4paIk4OUvX2ikOljwrI5HpvunAGyryS CP/3xcxJUEsooCHhcwOCD80U57T/u4dgrl/NTq3P//hP/GdPKkTjK2Ue7K68HMzMSORnjgG2zLFV QsX13vqMm+VSr0xadnN8UkWSxfpH9apq9Kc72z7x5eNrPWZFygAWNGmP/0DbPikdfczPofzU0Vif SaEH6VEgKBKuAcsfKwWLVWlZXM4d75OjRvGbu9aJ6WnJMa/O3xVZEYW+Ms91n67QBuIXgmZGE36r aKvpeJEuGq4DXw+Z2fexLNiKLbeEy2nbR8O7OWFBvkhrzb850dYEBgC8RaqtsiddC4h6/8fP1I2K Vwp8GXbTEA8JzdOVtFn3TP4SC0H424V0qmaHl5eR1M8GZeteALYrS1VtV9h0M+1KKAW4sB4Y68ZK 1gfqKN4ifx3K/C6AoOP/nMkb8PKO13HTDtoF9U131MrzgH+brUgk3UR8vP3IQmJ9gTIbeR+B3Dlu 4dVMXtWBi9gv1+p9bcF568YQRGpIaezXoTn/oNHc+lrLczMQHOp1OINPUGyP93qVLwh4PHtIcAKG 5gwRnL6+/sPjjXevf2p9RPdEmX0mESx6N2Bn98tVo0QromMwRLhz8KlK968cGLfDNBdG4cdLbPWK s+/Dug/yVwAf1Ofueh5rS6/5NxpATiMwMZrKiJF/O01EyD45bKuqByrWjLwrXiL6qjnf5E9gJLje sLSuz5JhcpaawmqJDzFqymB/LVrD2yCUsRNMnOYTlkaTcwYes2iLuxsalQvXbpgVTyQ0OOE5eeWD Syq2cMuWwx8XPfUmxf45JSbFs+Nqefh37g6T7qOC91KOekCEP+9p3ONNpm50XgL6eNy27h4cm64y CwKux9mD6o9LM/OYdioQgJU4Q9SvciwssJKzSMCvlmrzMmnH4Zpa5gz+IT7LAV2Rgfvw8t7Qos2i P0NF0HGYsbGKycaG4E0NR2VlcRcar4ZAxpRdXehlu3tjnMpRgj8rjy/xBBCSq0Ms/WOH7mcxHiNu JStt1hvQzXzat2E/mMTaYi/MJ37lacasMNptrKm+GUM+KJhBJFzt0GW6iJhrPpMwMNvbfgX7ZnQo ojAb6JeoPmfKQfAzARO/YWxNt6b1V8eGwFx5cHe9Hv++9EzupmrI7bQtXIQf2JmZ9OqQS78/ro94 o/NKzCJjkJyzt6ILm0ChlXoLpP2VYGWNdkPuXhiRUa5cNqbc/3BzCCSvCvfqY2qSbWbqC+qSmT9l DNm0My03l5D4HPjOu6+fLPpCWhWpk2W+zFTV2sjwc/dNpxr134e/Ycub5DI4pAJzZ3rQ/mN6bseA D5z8js3ElBeOur0/nHg4T6YQAf7NgYUMJCsEiMZjOC1z7odQP6vUKEEvYyQ+hVuqpFCq2jJT4igg W6fvNeZXWjUyLqUDgd4oHWbofrmyRpwtlqi7T3Y2q4up3tgKjhPA+tkri3IppM/pY/Fuv9CpK9cX vCmPW17pNmkgNR52acYkLMSd2g8oOQdJfh2YYS/5gKpCyYqe1oVwgDejuyxNlqcNFhX23Lad32EE hLgMDB3+OuYyYkp0UvT06nao123fTaAByQgqweU69QDXxpliOT0vqUVyZZziSJct66/jVZOYucbp EMt3P5gGv2HoO/yTcoEfz6D5kkR+qseki0cxsnRAnf2OdcfrLtqGIsOX3jy/cwv2dyLDcT2dECtl Ztn183awWJUyhOz7P89MqzLKpQI4Ucb9XPfTOWDg1AydlUXcXDVmHm0Uvn0Y03d42AAmBJsQvw3p Zt28PgJlo3LmDIsm/Pe+nCfhBt6tSNOBlC5xZi4PbpmF6cVVnDm+7oZ3yj/3qNCXQg5iFxe8j1T8 Ep7jRBqMQHwfuxCIJbdEZ3FI3sDU/3JXAe/g7i0DgIhrL+8utbH5rDINgRPWUySI5Xl5hzwwsjNY PA9jz32dMQ/k434KSuTz5PylWz80r7v3Oacwsnt2DeD5ossrJF+WarDiB+mtPZUL7K9NUuoZ8Kzp 98BgxtXu6bYvlDcvqgUcuUH/RW7qwwaxWYFH7VdZB0TkJ9eyXK7lBDFa/O2duU6CkIcNUeO7MTDm S3yNvys2QmVMVbInEB9HdYxzJzsn/YbkkXbB4W/IoSO6U2iHpzjA8wkbllwNPCu5Gmq87D+jTb2P e9zasY1dYEWPFnFweCS5lnGBZqSOXmIgmY2UC36CI8tjM+fM1NENXxbqy0qbhQtMewPUmcbIDZ10 kS8ws+/Wnsd7CDdjcyDhmZ9GiPTLwXE3Pp37F2x4fU+5yQNsyEQ3/aQgg3CBXOwHcpe5cR+LaPnx obujmIFYEHykBcFAeBU40AKWUlXHFpiEk3eBrwi0cTKYK15U8kkCbdrNklW0nvvmlHHCFTeqbF6J EoQxlTbu2b4PUuDWsBqouHEfIOOR8g+rmxoRmWcuvZ10r5OI2WVmFHLbbYFbfux0xTn9koFA1Fnl mqUuL9xHR3nF27MGRJ/ucBr/lxsaVtcS+uPbDYk+bgzbDIU8eqUsNE1RwMBbyf5+5My3Gp4S0Fpz KC2CEwp3dhRvCQNBMx8LPqmOTB03Oq+vMx0EnbZAM2nfh9jBFkz9PIQYuR0yS7OZtiBN/2VMsbgq AEOUtM5kvBPqK0I3evMjJdy93lXtkqpbo2RUXL+Km+fATXA/F7ekQuzjyNiybb7EhnhvyxxrazJw kRA8z4fFeEfpgwgCeEzEr8TQkkjxK7X58ia5lMcqw5CGDhW9f57v7uMiQ9YHXbyulHnwJ9NAbFPC 0eWMh/VmY1Q69ru7EGWAmwYMEvy7mJEUkRhw32aC9m1MyShOJX44k6kR1bEQZkkAFVxvPPzRQznU RRepBK3yShVM4Sntw4DoEHuesZHxUcnEjC1O7VVRdpQza24RN9WatGLPq7u5QDnHA0BCKe595NDS ARRKsa0UBUPwsjzNuq4OPWQANG5ZfqPPaouOK4Zh/nJbo8qxGQ8nPNTR2E7D8nTcZlcp1aVOnDDG 6QP39u0IbC1Vi6qT7zwZRcfssUJjBa4D0WdzhfXIxi8RVNwjYWZvDRXbER6KnAmkRqOZboLRawTU Se3g29M76YDxFucGrElHD4v7At1znamGvC+QWPfGkQjF2od1yh07ZZrrR9Kghdp9MtMW2c6CiKSj 18eLQgvhO2MaUhMCkeQjDR5xJA/h5FAyGSHqfOeuZcFXG9p2jFvKcotSy63Qv244AKfHzrdA1hLy TeQTjQc9vHGpYKEIvlXaB5CcQXsZXO5vN0Snv5KUpOr3KGsivpp4nraGnXEuXT87QnGE3x5tLB13 cVG77ssCVshMY/zznCU6kXX1YQOxJfk9xGJLSviXEZ36xOD6wCMp6uO7TFxjOJm4iDOlmEWUxeNE d9UpuSiO7lnOGLYoM+RioZfYsIzwHnA8IppHOmGlqDKE1XU6Xvvk2HPLuWqNl3tCXTTJuSb4xNW3 rYVL0K4vWmQA0nyoDfVQsI3ryhbh9IkdxnyxEj4GCndVgaZAklhavCmGtJ7czeV1agIZGnJccDpa EYNsO04QPg4BFXcelfXk0MGxoiyrx76Qv5daYQ3PtQqi9l7jKGNGfi09wpQ4vXb8iDek6yf6AT9v HXvO2sJVna4USdD1BCpn3QMpxonr/SV1bfvdLF1MRoExa9EcwptAFsK0ThJcCiTQKVSVCR+Ff/+j tXwaqCH9dH49XdPt2S84l+DAcfINspHuUxyugYHV2elK6XjvVUmOOl8upP31xQQV4n3cs8utiOBv zaPzOhHPCm6zlGPeNXhUmKfc7N/7HAljl7ViWcwB/jJAKBYOgtwlugen0vPg7fpnznqNVSIiXYVR 0CguHj5i2Bp0lm9oOzldO+WXwxoNExkWga0lXOwbHmSRE+rFX5BtN7+CnanNNu7ThpTaLZ22OnP7 iacgKgZsU3SV9s4EwwHtflems7hgaO932jp2RsVRkAo5W5HF3fmraicED6X0T/cjEAXoHibbB+2e P2J2SUw7hXbZydLL9X133E6PfE3AJs1kRAgd83+LkrsKwwM4Qgn2GnqANsGd8kh1LgK+4qZEDbTD y6TCGhQKwM/6bqtF7HM40i567L7kKsJ94TySiY2zjBEAe/ODm9H4U3TIyxyGZA8YpLElrc4UmGcY 0gAye8nD3XxwxcAWNNvRSpEk4+6fODW7PBQhqClVeJrS47hBq8cMPMlAaRk9PH+gMqe7kj+OMkUM Lo6zKbqqr40GOtExXxuDBrYoB/gs3DqI0eKX9uUS6Yfb1dgFCThIgChgBr3NCloY15NfiMX7woTb vSLF78KiXrUQ52lSW/p122jIYHYOK2XtQC0O/qx+vQIxvqwITSpLVX7t37O9GhIKG2syL/B8jOUW sHDdLJCxlK5JjLnPREFawEgNEkhE+NVjBCZ0VtdJLTJQaCrPLy0CsbnevAZ7xciWuMzYBITpT93o o2WMK9EkFNc2u3JEKKk9TI9zocOn0G24VFD+NiEQly34AYdZnGsVMW/9ngBZJpnekyX/EUNSS2+e PfxM48odL9Rq3KZ5NJBsiJN0axDvXOqOZTw4kPDjdHSvhNSHc7kaVh2zCytbCanrBnCCiD5E1bHZ EUbjFVFqxSvd1ZSIRGIYMlnodZBWVgymU8aP0dR0cn/WAzyIOp4/pcSF+qbqebsXrn+LSvzTR210 3MjVKNiiUOgL8GEYVwq/9hNcex6MIjXaqol6XuDq10ym1Ly4zsJBpdnrthXR4fBPqnGFklMJWSt5 9sq7AyfT3OqbIsoO9AfTVlgiZdtcu667mB37fPFRNVlvS6ayfvts89YMAfIvoRyYektbM0jqv3Gc CUlEwLW9rSaseEXq8kEnf9c+EXXMQ0cDC/zaSK9jWdETLjJLsdhaRpdF+9WeV3Th3mpY6IGzhcOb 7GbzgQNh5GYuKX+K1xS3HHksnFa2oKVEIgsOutW3AiEAhzS1+XPFD/6aS8t6ZLXc7/evVqtONPoj 6aeD91dH8chxbDu6UOMFYSCKfY2mDQEeH76jReTfuSGEXxqOzl+uprxflOUSpEV/nPF/HMvp/d9z jeF/ytnR0jJ/Zw9C1xQ1KG4MYp+0Tn8EihK5JLXh4kQTItNafyY/zUlirrroEYVvZAt17jfx2h/0 xrHVkIEAF91SmunIorwDySD//4STBsMtc86J7Xxbrb6zHUAtbqnJdDDBZ0WAQZzMoHkUHg/lod2y rSCV8CVMbDTY5vUO2Kd3rW8ZR3eH7i+Qjnu/e+H+Biio4ET+tFzU09eFnNPi+HmiJ9J9319bkc8S 8uO/VWQeb0sQm5wDZ1RgxIejLedYeTej7UMsiXmr7/YQac1Y7U458dXPfXwD1f22doj0ly0aAHlX WpGyVxQIyjHMOQs6gnxy5hc9es2ODtI4erOULoRpN9ID/IbQR1XoYJ25eCZ0BPwt7CDpTgsI3/Xu 5StdI6iBqa/UvZXGUH5SwscNV7rGE4v1TX8watxrNBYpPblF/JpQ9maGQLSHUO6H1tgyD0KCOPxQ /qmHBqdnAwwrm6z4OHfHvG3zsgrnhul7ivvFmNSQ7we9X1kw0ZYmMJAZzGP9KFXj/T1SoEv3e5Ei wrw8bRPGbWEz8uSeswvPsKD9UmhV023VGkPI2m+mrdWC3s69z7l7rpebwlb/VFt3pu9R6/62y7tl wrkud1H8gMvxkBO99LS1mYzLUjYbIqU14E548jaoka8W88eT0QamDnaDqF5lVdUmhs7C9VREgYzI F2DITqoG+CU9e1hDvRMU1srxUvaoFioYzr9ymuxyGlKr1pR85gI+MhTYTcm8nqAQr7H61QZ7ZsC/ WgU79E0SD27TdGerRoSPCfgwuE9NFqCUaBsRv4WXAeQymtaAkd8j2qYIepzGSw38aFTfnEouy472 R6iH17/0oaUvfv3X3dvIfxuVAs+kC5eSL5TQPNI9LHi2oXOw9BJ6tj2Tu9bHr8Hv+iNKUEH0f3+v tK8vS7W0ttqe1545HLt81o5WDzATA6zxSnvW2gGqCOAVQ3wh3qKptGTOfZOY3VTsoYGDO1cESCYS 5LOR5SaXS21i1GMp08+EcDs7GL9cTWb57v0QowQBnZHha8isOUqCLPDcpl/5mvL5MbV+MeopDkQA lXJQVY+NQQpdT4PKWrpmW8KrxaaYtbH92IiUFWUMwcxXAhKQKfIfum9gyGLp4bR9JDxY8Fi5gbos liTt3cQWjgwAV5jFKxe8ZnDnOIMnBjc63Z/H9jXcZh+9v/OGc1pQMIV3pmbKRY4s1NBWKsxaYq3W 0eC8m85g/3Ay1c895mI9tzoJvucYJq3/F33BtCgrSRUxFAAA/6Z6SSsQDNcJN9eO8KaEEc1OMdd8 1EPs6biRvAgaQnhkeGwYMNvu6K1qLq2I1pPmUNHiTI9hhiSsd/luDyrcb15GMR5bSlRxWTkoqvig N3L/erSzybGI8eE8m7B1s4Y3E1TO9qd04lST2DpFXWWbIlpGSrgGyjipR28SfHFOfDjgu2giYJWz iKIaiMhClPfwShxh/2tFfKwQcEpsTW+o3jGXHbxEkBFbejYTalibGPNOIvf1l8eRPI7Nrl0NqD90 R555XjSjmtlu7cd9PY0uEctkZj83XGcsWbLQ7mg7eOKmxo9VHX/glt2Zag4A7HLEyRkEYcCge8V6 MJMDIpuYod/6alN9AyzFg4SO6+FAGjwZGEnErr9FFmNvuSmRMYocD119N3EkXqXbD5TeGim7iKnl VSiTHB/6B1KwLLeDrx++F/MHXylE6recKrg0IlDV9T20EvlzNr6ilhGwMEfQIJMrJIz2Q6ir5xuR J6GfNbnBQaRX8sgJbaiZcAh375Ifun3sBoFAHs5tM5d3IFKq2SSDLrljSGkQrSJd+uM8JIZaR2F8 T54/Y3SCLdbsmVnkKeybL9rfzh2tOwjRZslKtRWDM2WvLVfXVoOxhs0lJjTpg8qZY9/RPAesyfOx 13DIzJ0nnLcskX3OoUnnWGZ4vbp/t+nrl6WNYEqn1leC+iL4X1bP5qQePyEkE9r8f2ntetuCE3NO doWY25vFKqpmeHHkJUFYR9dQjiYzjt7EapaZ30Ae+6pMAi0gSdP0m7ZXOJpN939P+hq5OFetJxpy TvMteHrJyjVyhFJW79i3mkB+hwn+bpZiNsi6E6TcvNnVz7xI2S57xGllglHgFuJAjZA98nJ8hp72 HK3GbG6RMcoXXWBqPKJhJMlk6p3X3/i8QvH33cvxJI25tu8XTOikV0urijjXSD9CMM4+hL2xzF+0 +wGmuLqdGVtpIPJRT4D1s98nbgUYdc2ZkvrNJ21JXK+it9IP4SdHxgA3yC/mKXWLKwZTt3vsHUeE BcFpn88KV8OTTMR6O4rKFEny3OFp3Mv8qC7xE05bRV1Wb57O3URcDB+tzvwQGJ2sC0sq1da+9beU F97egAwaD0ymEc3ohvAFjF/WkeGr2xiVU9IhPctZCLFwtpkW5Bn7xXrXbjwsTxLNjBSoxLqHGtaM tfmG9bz4mCxY3mfJ7DuXk29HiD1DFohVYinj1lpxSXo0KL/A3vqf9m3q/VKyxG9QpOGqhJTkSIER NqFOgeY3RuWhxBUce3bh/4F8Td+3Wf6rgPGjTdAorW66zKNEQdSckgPCeLvjeF2tJHwWAeczIcUS CWlxXevEP1TdsFrWmw6mc1Pii5hKtDHrkZKaRw0N/+yi/o4if3vxP422b4kuQAilbcVDKZfuYRO+ uaEAU+z4HMGqONwMjqQM31whVG4XYPz56KeoId5URs2oTNu3OpXqxUh/kxQj4lPZX7P0FgrIuEmW FTBx5a0aspR8StOskW3kN7AI8+fd3BeXEJN0femHr65YdFayF8AnbHcEr1Bt5YeKmXJxyDtptfkx P/yUduO9lzQlf4WSRyIxdrzp+uGBywx2SwUzlj9jHMZXBQvDXCKT5J8R6jOXIr43P+CZsgjuNeco HV3ieaz/6M02ImPU7hsh05fOOF2m9t67PpF8jdzxbmaTxKxP6UGwCXZB65fcerJtpi7JhP0o4oCD Nph3vXWtNniurCKfXMrAvM5i12b3ZL9xy5LbhhiAziJecD36Uk53/Krpin+yJ9oLidDteNk8BTrw 6nJbQyMP5kVUtX/gulGIAw40pLk64GX9KaNm3fiu2X2F3ZnKa2NUIBu6xpBwSY3u1oQ7bCjgzw9K 1SprKJm6ooA/PyYlkSX8jIeISZe1LITquja5/GJSoLREXi+g+fu8pUkIwATtOWRQPVxVAB5JNPiU X09+qOaQNvuBpHZuFFW7jBK/j5jQ2CVQZ621oqJTh8TM/5VhTJfZ1hAEXIPvkX+kerv+WjZbgLj2 PqcnWIlso4bySORaeHoxMI53E1hoiSa9Q0LtlAOcUI9JTklgBu/dXVc+XdbHGc52MuZtYw4z3eqE 5018f7bMN2b/abGT5vDfs2lNx15Ja+WSY7D0Fk4X2FVI6Zh5IjW+f5u5XUCWNmpkiNGlGEMRlXZw bXyS0QqX1B2OiwcZkp+YstJZJ9ifzLrc6RTL5mO0NP4VaqX0jJWVNi8RozIY72+gmG4vnQ/EB9q5 IR4ygyfJiMhmVpzJ/y7/PbCKDeVG3NvM5P9xcVy82WDj8FrdTgqT0wUG2Cv+llk9nzB7Xwa6yoTa wVFL8BLP1KzVNXuvgsmDdvwuzZVRK2xBxMJGemiQcuLWfRp8npbe5pYvOoY6C4DtYQ3FKrjFDlfr 1gCtie1JYIL6KLhA1Z9uya0rc5/O0BKqgfx5hmKvBbZLNYGWWE7YmTpfuARRz67NNedbCQBHdzHT y80I2D1K7UC5/hy8DiryUk0zHC2nvTPVx2nHwa5W3L8QFBe6M2ti/QC771PcqAiHrWaTgjp2vIJ3 Fj0Rf0/3CmfhQhPl/JD16YjAML7dbebxjeT25KE/5kwfLVsU5DEMNtECLp0GTJ+F+tz9vT0Mel1f mV7WKZALi4Dj7B5rmcf2onHGmAOz2dlq39VjOGFJckzuJg9GG19rbdyktp1fYlfwleRj5ZoeoJNq rBBxSCzAUkWrDKJmClxXe5QQRVDVIJUdkZTfyQnzSX0ai2drscaYHyzvYLj2rISslKiChkt9gHxj NlvFV6lhmZYLSCvasxQCTHXSFVSaJPvykRUyiq9Tvp7TNtAHO8JN+fxywbqxj7aA245i1Wb6gC9z jWCx3s1af0IWNRtLDducfMIjyZygjYDLMU/lGz78QBM6Qyji75SfkaNdZ5IBSEhBo1EMqZIM5Kh8 fyS1XtYPnFSMYs8tNGOoeN5uJQGsR8meSf5GlYdjZArvbgOa+G+gfHu9NQ40nfCq+AOMOjyFzIOq Ip7Fk4Yw24zz/65wSrfNSqw0TGliSiGBuvejapxse0WAx+pck+HqlD+dxAdd1xkl108gmBOmGFct vwIQNqTWho2sYRKZg8OIUvc5jqaR8Uh0nXGn+WaQwNwPmpMQTlUtEy4j/cXqMWKzk1Vfl7xXQt1U FhxGFqrxPc1tB27viTSIJCkgZVrlCXUrBaBD1h37l6v0NroiqvJErk1glzJ77V256y7E+QO7A03L rmmxSWulwZ+1QVg9pOSao6gZTvJkG+k24Mqt3Ce0fsxG+U7QblLuOZgEoyvu/kah//cxJSvHFGXn AL9RS7e2r4f1l9GDWzsry6hmBKbzZkByMaI7iHMsKDRnNe5bMrStWJXW2yWfFgyi67gbfLwYHyTS cbZZJJRJIr5Yt8bKuIEjRA1pULMrkBpNJl/Dy1pLcnbvwmfjdcM46nuQwJQuV5sKp2YnuuYq8tve HaUJcnQKuhRnMZYJ4uRvSHnVINfxhjoFxydooG5yhhT/usw/u3r+CGkmb8d3IcBj79xPbXdWXpbV xGDinZxL6FDd/vmRfScXrdASkLc6eXbX8pm6uNg5Yxgwx4ocmgKoeQuTLFZ4ahSY1/D3Jp4BegGc kTAoleccNwxtpmmDplhYdRj1zem3WynI4AecB43NsKt1+oy7aBdmHk7Zbw1yuYzX4zkx4CWmjH3l W5wwhvPPhoic0GnoSFhik768ngXguj4DshptpJN7hPXDgeI7LcUAnIBnMlYIbbaPlX41CwO2PrTO 7q2oSqCipH3Rehugk0Tb2ccL6+2N/iv8D8CAwWVjSRIdmLMb3iy8IWr4PtvgqztsSfl29tnGziQp SCP4jCJ19V7j0uGn7dm+MBvWsXoYoDQMhl3Y3IuWg4uE0H2HNxVC8mcKgLg0IXavJlrS8aafDFbY Zo9WQvJD+AVeBHI62ogpB+98TuGfFH0vO9gnZtiQYTJlAaD1aSg9p1MVruvbmDAnoHOfxEIoJmRT gPIa41kzHbGMx4Sacnk6BVrt4HxRBga5oy8JOrhrhNQvUp3/pYSb4pD+CgzqED+roPSIqQHLxIW+ b4D7FhNZxYxoG6NFl0t63U/0u5G+TYv+6bJJ3SSI5RyAJ/FQh5wFQufFjSfos3QXur6ia/fEJxtS xXfeqcCzZUziQPk6LDH2yxJKnG9AAqPnEHn2UPhoXCYUGprCBirEga06VvpXREYcvM1xt65r07Em iBPzZaa39AcugHB6FMG2DS904mYj9IFRJOFtSyp4b77UwVs7x+VwOa5SiyqOvLz9aZ8mCOT1knw6 MmCyE3rk7A2ORaQQX9gXkwC8EFVlLeUZ440perEArIFiS5V2KrNDXDBAFgt1vpgsPQCbuqY7vukN WyeRX+Vh8bbnEH6+cFaLL+gQ6TIFaZqojLX0FbiIaPHBT1z54mhSbQc2w2tez4s+eeNOJiow84i3 sUgtyBPYwJ74gsB9TNBRQVtrqgUN0GAqR/4pk2Zy1IPqjnQQAzgHIZwxnqjOI0ABuxvlVbAgZc9u efnVQxaFsKQpBUbY10shmUrIKgKmG42y5YpxVo/O4b8aRHOhiR/sMot84QgOpnPuBuiTx81ptJ3H w3hUHYyPvMDkkvkG8Lc11qDZRvo3UU68TZJ3ImcTZUF5RARSJuXTn2pQl5qtw0wobhLTzxf8UfRt WivX1+u2mKQ9zoAmsH/hb8Lp4C9oQlH/XpJiLEufcoE3sS3uuCQPkWwBFxLT0C32VcFCLRAmPyu9 vzD4lCVZRXJ2lNsigPh0cegM/GqA1wjjtYd+PIjmHrhs/ehTz0Z5d6HeM4qWfOo0QQBwaL3hh5+f r8dyFnyIxMBnVjI61/3T6c+hn+gCBpvrbArF8dKlZXvHJEvL1pmDvF3DRN/nF6xD/Uf5/2WumZSh LsjslTllXZWxbzqUWQUYpve+xFD8a+SSueoYtszaaeMGdoSZpMwqmy1r3AqjtdYa5Kk2kIl9+IsH PdZzYqKV5IbjoqH/GLd85T6P1kuNWtrUfVU/WHaEPM7o6XmEyPfUWH/KyGE171lRGHPavUPNMSvg CF2DIwi1IFfWCWtJW9wYUrcQms3NA/7OlrZ6/Jk61H4zxAMhP3uXBU4cWAy7XdDeKmvkmyQ0VhKq sDNwnlPw2Tw1fWxu5b0GL0xlW6t5JoUDTWXWWHzLVWHhppgFKbDVizihFs5k3thGukvo/nGsIpss nSTaFfe7SPYiqUBacEwUou+tcYZCVFK0VUSvPk3+Hw+Ep95eMi0aTt9XAT8ER4xxDOIOdbytse8j /rVsUpyFlGCrtFV9gJyrgGgvfQCEwnMSgIhAtGzMi5rtUmrtVAGT3TxRLOvuwu0HS9x61GtsBHPK AhY+9wk/zJMSsCNKidfWVNbNwKwVgHmGPXm2lJtSicb9GWfW1TIK6qxtcGUQOLuNVKf8MyeO3iTx 7o7ojGb216TRqebMVDm+uGcEUgpBmZFarYr/Wlp7Obe3Jhad4higcH8xAq62xU8PjZQBHSVpmHKJ fBwjWdyMfe6s2Yjol50gu5U7j+evt4g+6pjqC7OU/pdMK1HV8jxbdAv6sRHnV7zyqlVs4LGVbYK8 wDKSDi3VksrjY8F8lFJWZlJ1hDsrCT1rVsgkUL8UY/OhWHBo/2WyAz2BrswJNDMfYSQ98aLunnxo 7kOaX3hmyxoTNmnLS1VZ4SpLYrfYMLyEcHYw2bQQn8igo05vowKmDOjjlNCIcekHcgvSaaCgGW5k b6c2nudo6GN7nyXlV95SbxliLARo97gzlvjLf7rwUAj/Ph8yd2GuJk6Nxe+qpS1TO3sWzrwrKTtS O+1A/M9pMJoAbiNGesS071uNTM3sjzHGPPm40/7iTjt1AUO3WD5SKkPPVQZRtossMRCNJIoRlQeR UJU/n1+BS5nykM+t3V3O69bhx8WOnaK7fm4PExUGU2+EbEFUjgxInOpMx5owdtjFFS4KJZSqQVgn ABQII/DC98r6b/Y+N9+ONZi68AHt9VTTASp5y69H8k3AoyMBchd0hzVCtzud1khe5UUQYQIbyzhQ pzLi40gqywZ9qtJajQOPVie2r6VBclYpUZV/Wt+JK6ZcBlpk4syI9z3YMWsfiZSGlwJ3/Y2JBvLo liya8jdees4FdQP7MFACCO/DBh1jD9cdFhg8/RXKVmoJWJRQcOn2SVrjSbQJBn2gEiMjrrl3PAA+ owfsQAT3RlC5Bu09VmIQ1bQlaEh7lvfp2hPC7cPzCmPovNLSts5kJjHhAJsotaRWBxTWGHeoQS9H dgVhwqYLcKw8FK3gdA2RRk+FqjmOuXxFEPk5GoQXPTLSS5PGGAFrflv8mTm06/tridCiZ3PguOSE 3fPaPCiIXoM0OLJKZ1RTzScRv3Ws0dJbcdniDavJa0JunBytOLoALsrtOCeslkcmU6x5ArzOLRTj 0RB8aSVQhY2pHFBKuBxZTwG/XVL7L8c56i/EwejIL8h7ElDHYUL3MeDr9y35uQmXiE25dBqYYlmt NtIh94D3ejo76bWvTMs7nP6+78KEKJ7FHAfJKmc7nGXVk9rjr9Vp41k2npgAJWkDpnAtHy/ZPB0l IrRBd+thduUjVyvm55dL9TNFSc6ErPtyYQTIsD7c8NeNxc834B2BCjg+WNqcwlOXOTBwhyg5wmXM 1vcw4L6x/6N9xtraJeaH/0uMjV3AvDdB6/X+slPb+9UiCaChfoU6Y+5I23wy9YQVIFRJoDwh/Jmg 00wERVrz7WQffkihdNbQBHGKIEYxeLf8RRfU2ynbAGh4zlEkCvN0rPs36yBDnGEwDvnirXoycGJ1 gUvO4xr2tt8uoQcpB7USmnUaEwgI9bR/ph0uOvw7EtkMrx7t44DG5cCFEFmWy5OGG7trFPsW6SeY Ag2C2eNAkDX3qYrWPQPy8CfjQZM6gyyPJfnWBuiKvd0Coe9rTltEcniu1pH8zNwq3PBdaW4YDRAg kV8Kd7XQp3NQ2f7Q14/Ud3GNk2WtazjsPOLIb15G2L3D8bvNCOvEOZnQGRQFVn3vMzmmQSMvQmZk vGJ6PJzH7kw5FmNsJcreIpEM5H6HKQpjhy6PdCAUNzL9NBmgL8NMQIzy/BeIrmyMbMrvpWBh0CFj 3yh3yKUXvdr0DIduDeaQ88V4Ep0HmCivjWPxAENQtxHVSKWFdN/qEDlQgWykHuMhrpIufbnoY5i5 KRbDmYXqkTJmIlkarCfgSVnRffq5iucD9jC2Ph6bp1COKctZX1YiabAjt0NaoDVOCuOioWqgagJi q0nSxtCMykrLyhgkZy/QnaJB6FRXnoXGy5Uxu/Bvu6Xp1pJaZNm22dnyFfdDbeBu6f+SbImW1Gbb /0iGo5vakwzd7GsCt+p3Pv+kfybG27Jhee4jzCw9PJMouSrnW3uJMQ4WZ7SM0EBu7APX8it2PLVh hxtCZniIw6PRny6DV/ppfV1flirUn31gMT/Q6prZIxRszBnMWZP+/f2ORFZT+4zx4Bk/D81baIp9 IzFpEnEDlElpLytLcy5f1wEKZwiHxv4k47flf+BM2tli72HcZvQOSZAPz1TCzjoXVgfKIq6JVK9b KbTsdffCFmHwW7kyH2qtLXHUn3LLNVU/BpdJLy4+SNOBxzZcZYkk68bfhGX6ButsnzoQj+5IAO2G yvE2ql8bZT0s3Vi6t6/PJa24HYf/4M/AaiHQY0XK9maDmEVR4544NZwxMVKFwQqWQ17QtloyWZ5z 2F2XQTvFhQ/6VmXjhLyMmh7SjFprE6hwcMCKgmeYYST9YA0AHntXg8RUIdFUBlbWfHOCu+X3ogIp 92dd+d7aA5mecAXR1p3AltdR2JQ1NGzIncbTWBMjQ1dhfMiZTVkznMWlfZ4EcLvlAJJPfD7S6vLM g9ek6tDWe+KQ9SQdfcf1mC5FsbEDF8a5S5ZYf0DjNt7TGKjueYYsQE3xEYE9/zhlTtK0w1ZCWBLW 1+sFwe0Q2rdez0ZLfGRvmDDBqOqB+S4oALxaQf/a++NQYOGYIxF0hVYiXwSOO11yEflZCszZc1Gk BdhFngFYWokFPEHgvPFja+kANPwqm2edImwJbNzg4FQRfnRtjYIi9oxFvIC4mfeKYqjStSBuWAHY 6HqYRtA9GB+BEI+MeYrjfh3GFv+m60WFoCwX+mymq8Dj47Z+nX8dB0z3+rPIDCfDYOmKr81desTk aRN51p+OHC8T7B+AXKDv+tgeUZvPKAlV0v8qOEzHUGaadW6tMwTfQ+KeL7Z7IF4g6BusOqUMnvMF tRWQHFhrIyiozOenE1wBGW13xf2tFRM2LyTiE3xczhKOuBFGw7Mx8/tZ2gYdp/4V9o99TSEHAJVV FB0uGOKDI16yCHbSSInWiutDeIFXSQtFcoE2j+AK/dD/G0dndfXMaGREq6ZXGVyzsUWqjnv/BM4G KslPjKAYR60j1wvSI40ClVb3GpeOnKQ2Vtq6srdAfuG7eCrVLhb47hbPiv1cgwSrduRFCrgMR/Aq EitBkB3hmBMun4QTOZe+ObUKFwqJHC+uvYSKS3EHNzXLLe94NvHG5XJEEke/bPIpmNADJQtE/Z// g9s3rgNw+9Im2dRz+v/6AZu+xlCWEaI+VytbuLEb4i/ZnlHVhnETmJZjIIkraV67Rff7nKpOI3xv a6xL8fWdTMzxxK8eO3IM3BdHfD3lmjy3sJGYgYudsi+DT5tIlcUw2siWNKWtUl4do9QEEYjyiPVm WauMRdZRXJvSYQZBXPeF/xM1Fkrw/E/svQ+fmRyh5TmW/56yHyNo5W+03hHNizSWtXnKRoqlJWQu E1yXQmDGcQhGc5lj5+OkJNUqsaMaI/RkkE0mQYETea10GeX/Yt9yI+05oy6VcaSnzTNR+juMlWbe z4RaKJhrkDbGmpgFobwwgC5JLa8lNb12OVJApvr6WrCEiGwXfqmX5BPFKA1A36ObvKFbKiDlqTQv sETCDXF6dohNHCGh+zYIr/0pObu5g9v3Viub/G3Q8ARM4I62gF4PM0ccTH+t0RuTDhZPkxmMaxcJ UJ5yjnOCKkNOEW50McX5zQsESiLDs6Mp3HJ8tzzw6EN68yi0A3cxl2bSNJkDRMc9tsptES8f7gND AUOaJSqsP94tfoJ8cbwAHIx3UsMH5L7NkUKU8sY9X+KtuYUIwEtevOeFdAoMQb9+ui110/let5Zt mTq36oDMvlu0VwEWgmuxw1nmzV7Z4btjFjprbyPgxm7eXnH+wwSaHX+mBcytOm/rukyv3zXqbwYb pPhij/EqBt8KVdY9z2T9gj0eDVa4W71pM+y5hgjmbwED1p4g1+uN4S95OgDKckaZ3DkjyUoQqkBS /UPirH0K2YurhzGde/YfIhUkCr59HEcXA2JkRZTmGSWwDURlosBe0lMPY3RG2dBoRhBvzXmHWCOi fdSFGxH/f+flV9BtSGVvK5hyCxhU+of42s+LKDGScLvX9zfxt44nFSNhcBFiTwvFhVLoUhhDGB/B puTGO88i52CPk50SyAInWaHy0sQaGN3qMhb1doKBRD1lH1EOUotrmzr7C+qyfpKsvxb7GWHW+QmD wLN9kEf3LPUs+CLEZdbgGSUYab83FU66VrxgrOVVWvQeAAlLXmh+AjxGsO/uNnk4MysqI7zO2H+i ghgSzN4KlqzNYhEVF8fef+dfVz6CE2f6m4Q4MoHuSH662hzelvSgWaJqyAFr0H8nO9JN1WuqamRc C1jZq8JocPzFzYJJj3dXkBo82eq+1YY1cRWIdhkUSQZFp/hik2eti8RRNQuRWSB9drH2tlVSUs4u 7coAJTrAgc8nI9wLWXFyNrtUcXSQyTLuzB5CWWWPvkhyTdhJ1cL6w63WxZVciqNWMxqKp+fiUiOk TBOlnOrOj+OKC1WfQcdojUbF9sLirejohiEnrBxc5XcQWomqnBQwR89FfDfXf6UZGUr8Kg6RHMaE zRzUCYjjkzWRKbKzzG82iObC/9YJ0F34Esk4yzFiFWcqIja/OmIvMN+tbxifjm/Ao53xLAgQSQDg Y9R8uEZqr+lnS1G9ACBH0zFEBlEl1DxAVDkmYlvMccVjnTXQNlO76OOpkrDeBXAQKoIL/cPumEBq x7ZxaB+J4rI2mxNa2CDaVEmHBFWlzMZIdPzGHLi3LCCjiJ9JMr4eq7qfjdUSLiEr2g1+geihlDwI LdD+wXwoXLrvNp0NdDeUKBFMLuIYwMmuAb6bg/mtTyFcWJPZCA7q+UKWMND1REhlsgLMAiKSflbF ctrVrhMdRQvOoVRjPuVPtEIvyxjOl4u5rJ9rpjd9dvWVclHJGRz44Ke6iKqMAcJi4a73fmYNcj+F LZpvzNoI7wwKErA+dANadp17SY6RegNmu1/5l0CNVHLJl0gMjgFXk3hZmYl95xj2Dg4kdji0V6F8 Vbq+a0R2DLsS4KLtI6b0szbSLpuX0FsjTZWUFLWoAtYXahTt7anQ0/hD9qk8o47ih8Ka8SDlPCGX dvHWU7QSUpH+MXmS0CJIigwnSqB9hgya3KQNA0SS8+7fTPZoI5h3D8xZSsVZJ251TmDC0ubO2t7w P5guGQQ0I94jQFbVIV6E+cWnvRZcTNH6zjh6J6iaS9CS0ks9TSzDDNHKq6yC11/ho/5G6XCFBkfH QUDMFDCzqqE/GeCz/RggJIYPb8exjrXgRcuZJmoI60RHKkv9PhxOGS4UN2C2dOmG7BWuGQ/2j4kI M0TV8+oFr0Ym3nIUG/s0/3vNcTMpcgsBcgVk8/6vjlbmr7Ucnd1mCUE3xiOVWCMvrUzeVpo6PUpD bn3igo6sKZPBQ4a1eJFeEtuWpm3qBYvBIrCU5eqJteQSPTEdCLXPpE6tl34fihJiwHyTGk6LteZ6 gsp8PgR/fBTqeEkGgmkevZ1pzyFIj5z9OdtuT5FWbTYQA5Bn91SF9IwKgh6cEhFLPfkVVw7iq5x0 M1U9nvWKlr/xXlkl89oIp+gOkYptqiMm/D9dL+Tt/QYIcaDgNaCSjiYWwWOLQiGeQn9WHPbnbgk6 tyrq114j6OWBSKKMXLiCVOymwFnxBul4RGrJqqIUPiG7Mlzyjgi8FpgoVKMFKt1ufhjxs/3RRCIq 59EQLWZEVr1bzyEBq62V47d1IoRNo11NjZZZqrLQjmEsH8Li0fnF3MwjYQ7oP+uSGq+0jYI3eseD cr4OBxSzGPOfkVHOXnPcHpHX8ncoM9Zq3nlq+chJ3Y9fiw+6OW7oRugb9RhCMj6r097P3YUAh64v bZ74DaRJ4TWuZ/eoRueV+Ge/UIk676yCKBJN0f/Wpl/WlRMgv7orPL413dbkqG/FKflm3oOFKuo6 lEgc/ZWDn1ELSrQgSAID7Sa8nIg7bhNqffFa615/+o3uG4RYgH6NEkY/yUHJROL8qwVyxfLZVSK3 VZWWNmhGjfhApuRCMxt/jHWQqI+EC+IhiVBYUlxQwZ7HnLeFwm3ZROj2R12bsjvlc/XYVFwKspkR dZwS6wFPdywAUQqOidLhcxHsj60FUF8BEV8ZqAOy6/T2sY4zXamAleaNWBQQugeKxQVdeABcq5P1 fD7Ae1h25Ha/DzOyIGTAyuboU6/I1psWvGiKTyJYEpsaH0r3I7vP1uLY/4q3X+L5QOEJIKwGGt1B MdVBUOQew1AmwP0wIFvM+/O6zNGqLNpiPEz6jemOwfFHJ7pSacYduCmjqJrcXFZVntDaEbBZVC9p Z1fOxj+Wyk6wFdzS8tyD3lyz5s3rd/ohM8S/P7TPYieb5yQTYwMcOsRudCbi97+T5OhsIU6IEHH+ 3r3EOdkRNnGlhEacmAYU31Juzd6b5AxIbxuvJlZMNYd1Lw5rTLoU29ZAaKztv9ZqJsOjP+OSnULP VwcORiGBIyJt0tlxAg3Ty1tAK1rf3BM0uYjcDrBcdaQW0wlC9ZbQJYXs6rj4MEDciIcOzqC7Kv4n ZSlMObDloj7g5xI+ucZZkguQu2heU5Bk1EsO6iqFfMHVyLnRYHJPxd1p+wDZrhKxVfoppN66ib4Y cmJn4gyms+EJh7aRJv3VTmrfK+QpejCL0/TJAdgUw587zzDD1T1Zd7xV0Ozklxhe/RwtFjPaZAfV crUmSzVfBKcQSKs6FUDZ0V0wLt10qeCcwsC7i9mPaGC056RTQyVlLtTCUlsAttH+tEhZA68ZLaCS lVhedxv+N1ywxyg2zE9BFMRT92/8fW3XlLVtCERK59LPTuKH7bn8P0t/uVPMOWX0fqZqpduKE5Db bWURRejIu+xAjPiiuHW+wj84IfL6yPCC0E7CblB+EprpVIj49ZlCdsOxVXOGhcahV0gH8qyGab1j g+fqEnXTheeBPY+Z71qPqCedX/IC42GgNnojM8oO9gtDU7rhRbMjffU5LHjrMF3JvSz+Hqop/xcz he7obVjv6h7cazi4HbXOxEswZVzv/b5lolRGCcWs2cZSeOJNVVq92DKT5OcdIwydC/9K9Zg6z4Ty T38GjJbbwE2OZkOB/5Vr1AvIkMtjavJEGSUtiQ3kKCdYFv4pePJtQdand2A6aOEJ4//bMwN4AoXH f50jAFsvTBw3ZN4ikJyYnCGDTJ9Sca/iq9aXutPLTzeuUQN897b6rSVlf43PydlsSVs6pVq6Lwds hSRAABERPH71cBfFvfW+Qffs7J+J4ATZ6XIBTeu65jRx2GP1sThPAMQLiGk4K65p68Bj1YvdCzsG hXHNF3+RS3IeT/juQHPCo2Oxe7MDDAmGT5yC9/AnKmm/SynMEexXDWtiwN77lKu8Fp7w5/fuQfFC Un/YbCNCAphOthF4xYWZNua2jFZxJgtcg1YbLTOObi+R7Jtu9CJQLD23i7wYsS2gqq2SeVa8EZdA EGYAOChK3zEtUtfKlBa9ud87Py4tJrsGxKLGriD2IwWxcJjwgnNU8wRScK1xqZ6fY8pkILopx50/ F8E2SmwZ03EAv1UIZXchfaWzMIgMg2pguf7Wll/TCCtpbG6VDkxHpWfxIupXTsHL378jHiSCE6e1 ldvTF0t1gcOnb3ixuYn0RWLbNwWfvl/Lz86K062Dzusqzf/aDEEZ/rjzSlxp78bEppVj/2FO9z5M XSxmI2phdqsye/KEcNK2cbC5g1sZKnGyZDUBdJdEPhvWiSc5RrhIIBZCkNwReGwHwKgEBQqfI8+e bfnlhAEFzDwDU4WH2HA9JSjoPJu3VOh01zPAXl7vwTkpTyBzfwjRq8QhiXNMXzxLtK/JFf1jFkCe KJtf3dJUQ5fWEHXCaF1WVtpDaOXcbf/PA0nr4YErg2r98zC3aJEzZ2MJk4Wg4iPy1/Zd+48seDba dRpWv3QcKh5slisEgvDArY98VQ1C7+h5F/5cVeFxe5OfR1RVJkUNrL6py1V7gypHXaPMOHiv24kh 6/FyJOs+ftX0RBYaVarlxPZVR45C1YJSGDJOi13cxrCb775G1Hs5DRRixH+MDDnXzt0af7bNBChc sgCcdgnbsIqbuWS+uqEc7rdfBoqX6furnjpny7h5o4VwK0myrH8Eg8Xew4DVJLObKtUmUv73RTWk O/WJ5ndK9yGSnoDezf1LN50knP6mtja33grQKVCUxFHWWQNjDwZ3zosNj0+5A/V8aYFSjKbvc1Cq 4XfroMGBYWosZBr+yGMz6TfZLQNlQlo5scLB1uQ9uuuVuNuug3dN1NcfIV5fIeEwFOS5SWK+Zsp/ Xg7X0NM/Cc2tCzLWCgFRL1DfzB8UqevAcB0mM2DhZL8tbWex8WM6XuosRvbvSVYKYRlHRMgsrCq5 GlS+K2yDa51Uzn3sqFepaj4Ks+lTXE71YRq8nXVXC6cjhMOnPsa/ZqSEG9rwnNtbyxFhCN2ILcQe KqQKWwTeNRipFL75wPcwKnpKWujRycBx1MtRg9fuGfnO5ks8BLizSQYsuzK1PFLpfRZBwuzampDm jcY3/46cc+gl4fe5FLHmxDw0Wkpo8tF/B4z5l1cyKf1pa5f0rQ46M6AVgYD6uoMlWWISL67aG/t5 0bfPlQpraXe9V/4751lu7s0kg6663r+n2BvE52jFupcTiOF6N8xxhGB+5EeahGfGenot/FvEtZxc wrYkkRD858vIPQoNDSXEziH41uJVkB3f22JBeNPdIe/PK90Pnxe5dRCeklcW6EAr9r3jC/LFVSHS qauqmwTXn5rCg3/kZ/Ocf31/xSqwhZ05SFdOP3oKCclr1SxT8hXd80fb/LYYPJZnfFSmkUZqG1DJ 3NPpUBkxnAib2Eqw9XizG04gTNqqdAZ/30oyXlolIwgjf+fiU+KrdDaxWuyekpByOPwDV38oIarf BIgh8SGdV7/NA4PTF8qNWdcEaKiM7YjOifpZ/coVp7+OHZo2Hgrz84Tetoo+6PjLP+/0pgHI3Niz aYeD9uMolJBnmXFc7yqqCaiJ2zxGRxZ1KQHb+sbPfjMidlL2zbg3cr2i8BvzfUhU57qppv0FPjrM E9O9p4XE+rneH5Hd2UPJQeQsbRXT9b5kEoP7K6pRv6h8cwkPpN4rKSyqU0b5QRb9rQ7QjBGaCCZE ZdkLDKb8ekprkMcDQejdinwF3kxP20G3FYjUxx0zXE1/WARvE8ARlmtzBvvuFsTFpVEA+EA7NRmr fCVSZTHXerwwctqomeTb2JS47G7vxmY/xxb8ckm+KkTXYTZ8UJ1W1OTiDyrzbHfhpWts9v5KFe7k 97uYpGBsC2kPljiUpC2xBm5NqWTUkDdHWgwsS04de0NnqijMJ9p9G3HdoXnSdghLG7jiQiVQrU9T Zdw5+Mz5NfFA+5tDRsCGWrJ0+PSA3JDoNkFBVxcJlbzDTcOAWtRhi8huhaaNp7waHeVjPEdE9b1Y lNtQ6XVVAUq7N1JiCrEraJQ3nymN+93YXSGvRO7LYtiU91gsAacoVv4bJQ5dcFELvx1zMozckGvd jM0qR8n3GE2foT8n0o5jUCAs+wWCo89k+H5ENvvVX1WCSezClHZ+7tJsiYEqedbBLBTNrdAeqFb/ jW6dYzf5Sr1BKBJimyqWqmO61FPHPabCWR+iDvSwFrJXz98JDfWeBYxmCT1hqpssli71uBy+y3qh BqQwW7WPKOCWijOtGhS3bBq+xxuk3i0j2PfszwzVx4WGVJZJ4S2Luo9Ml4AF1bgNpjP2hcH3dH0s VXtEykovyIhhMqSVjV3dclD+oNQvowg307mCxciECr4xRzku/TYgTDhhQovXkjP5VzyaYSfyWjXz hGSxx/CDHfQnQKARMCCEYou1PuY/xdqrTCT15zO9d4DvmqCXgTQUKnmdMtYFmMEEYJG4s8mxCl+R h2RxPB0t1gmK3l0XfMAPs6eRoI8tIerHwm4mWxqP2kZwkkyuXT/ruiSwgxnt4ulc1fEYCdGWBpDP OFINiQseFeiV4hVLlb+iLPNlS5VurfK06vGVZfjTu7LDPA0gPtO2V+M6q8AlGTLjqm/9WqUhLCaa cpajYREUapg3oMph3+L7CtrYWWy36eabsbWcuq1JQNlHWovA7BbvvjZ0CwHg393LZdRnb/Pr/vcA Xs0qy5mcSmQgm6sQQuYlnFjxK5Y6ykAYCz6Y5c4TF4oKwC4bCOpOkWJlH1LnzQ6FNsf/3BBFkNOl EBadKN5tdprYFEAWl83zOViZr1c+RYv9nWYyQ9zninyCfkcRZM7OaVB+mvFMZ78z13OPA+nhntfU 4t2sPUpsQ4ODaQQ99SDdYO1xYfwsCYLAxaT6PPEc37by3M26EI2B/sYRV9USaU+Ipjwyu5/Ht1l6 /crh95WUSHNew+5plvWKuwEmH/x6ZSOj5vbVqZ3fouQYgbgy2eSgDCUb6jG0ljaave9ia30BhEb6 8UDUrDJq2mQ8xMBRuWWwfZSII+3RGdaDtFPZYSZwmGT9acUQmqLmnW5F6aO3pwG8mCvzWcvCxFbq jHuFGWkQSVLm9NGSZhRi1qPZrBAX2rGt8SdlGw/1oQU6Xbtqw7MIUwDUcnrrW2QLF6JBRSJOFt99 2DgxdM6Y7BM35EWfRGfDM75tiE4X0jNGGOvVmrPfunp7jylCCFIPs5KXEchTKhoLJz3VY/C0Zdy5 7zkdjtmaFBqlUAq7NWwxWdYCIuFRurFa/upw7Ju4+PUPR0FLRvpMmsznnjCUzNNPGSZLGjwya8QO mIoBfsV46Eez4xfrP6ox9eBDNNq/5eEZC/LVfv2K3ILQt0XXMDN1VmlVNv3dtQYbf43zxJgSqYXE UtSi7a3I5eOGgaAhF3GzxrQbU9xb11hC3VZjXeJvYZxI+CVIJOfId796f4mF05tzGQ1dx6nZCDUk eKflUUkmEWr3lCnCl/H0M0rVi2cS94B7ObU3iOVPvegCZDLjAHe+vTxRRumgOtx2IXyrDAu6SDGK W1TY7ivcU/iAOtfhcXzuaxCT7sfaw+rfScNmLTr6foxR6gmr2USJApAXAh/xCw3YLm4Ig7mehWhZ O5OF2CARmvT31ALbVkacP9zQ62/0FTHO/cWnTHw9CrQABzRMb6l7csOwFkR9Z49djZvzRRhqvqL9 1jU6uwf2/LIU18+O7j7KkYwoFQRkmRrKcBlGHkuI7s6f1qWlgC5PQXyjXhU43uecj1PLG9n1PrJz chg7K0D3GHeGFKx/FhlHqcZL0zzBsYVVuyk0JU/JQv/ffpUQtVbRteHNXjXEqdIIwanFTcMZSN0f fF1LXJRzJSkCAHekuMt3FXU8r5pqPBM33z8SoPMIKrjHEhfzLxBxKVvh7uuc5pVZLrpL+7SOACSL hkly1NXdFU1qaRbzdtKXuQqA49oGkR2i6yyChySWWHF1t+Mwf/dQr8Ei+R1xFm56klhckYMAhdY9 I4KTTNZNenxbhSUWyvuUrgGsGAYGLvbmQZjuDXRUVy1K6RnCrUVGawpooTnb3rBphp1Yo/aLIuCQ 0VqnlN1aHjLMiXOJHN26ZFMwSELm+Eb7hktX6bsobgIHLZ8fiUhEj2zz3eXVQs5CquNYbn0zD7n/ lI0I7u8+iVBWEH6O8Ef4DdEsXFoRjGscb7GvuzaA2ZyLPw0ndCvfGO9s7UN1Ue1ZBQWWa5BYzeGz CBPTyuA7tzmyYDhehJtp1/HyAIOJ5Yd3DJ/dtU22GIz1uPkPANIYGNiVjOWlxOQAQ1pzXjsscl9U x4O36XTvEU7IqLwwWrXuoLpYEOrEb2HMjaNbnWin0jxnm2Z14Ah+jJ4O0RSjUQm2F0FA+YHvBr/R Rza+9ZXa8x0J/O2+upwLQc3g9s9cZ2oIg/EwTxnwvBdEpw18mNXmTqbzZ6ZQ0/jnm2HqQmml0vgT nVlZaB0co70pIkTlWIb5LWZI0RtjqSsxnoOv68kCp3KgcWMrZkczONmvypVogFcOVsCl/R7bSMhL b5TpiMurQXUGQIql6d1kf931plvhJ8vSB1b+oFPgG9tcj4aMdrN/HbvN9Sa/Nu9RcOr/pVb9PHwG D0xNHu93AT8/dadlzGJk241xwqbysxYMaJKwEh8r2+7j9svv0c7bcziibp21irfjXKRE4n3QNuSp prP/YPUJ8CpEGYmK2XmCu1wd8H+stbg2gG8xiaso9F4l2jNtetGJsMtWECv9MaiVZbawbsL1lnQH RTn5ym0bBjtbp4D5iQmgHX+foznFyNm6/6p62BbUe0yaTP0W3GSoAm1ZB3/Pyb9j+zLduKk8Efbv uA/FVuqYO/a7QO1vWu91z8QnLb5vb5HlXnqLF3UG3G4wsmOnL22NrqIgauevIf2UF/jKEmEHqtQO cfIOq7pV1/SFf3W8gA/ii0azq8jNUyOeFpo+fPOHPj9Kq+vQ3Vtecp/7bcf0pRwuFOdbtlapFwi/ hsQ3zyWkgaEhUq8KLF6ugsKNYs7FNtcpZCNcJj+D9voG5/wOgBxc+cWROTndyyY3+Lm3RwQRh2hk ci8qvhEYwKr6fyfHh175McYh4Xy3vXwivnpKPo56/sYTVvY1oi3ZC8Oupd9Uwh7u2IaJspLvxXDA nTsSSi4OJtGpP96XmayQIMFa33RJEjSWnX14vn3NXHZcOMUXSIyj/kUF1n/ByyADCUT5NjlFeDIb m7AhISgpXQXKH89MHZD7FrgPDfRZuQ4a1A+l9ImRu6wOyUnAVnK+VpqfZAQTvoQw3ZgQ50iyvNFa vjQYvvohuaMuwoTXuye1N+pfALSKRSFFF5dabvNFq4ZvGw6WlGgJZG4jCSBhRMsViyn5eYHn0yQX PEfw8hEcCOLSTYqH7+nJcRNY9DirLKIV240PaUi1RWXWSz1FCQ4roYoTv3mRd4eIcmshZ+l/U6ad rB4Ln5Gl2Gc0homto2OGtKVVrvjofMZuqQLs4hccYQghE+TXTsUgs7bJnokRTWTJU7bjqbVRWimI i4ZXoEbuuNCpv+Dqum9Qq5gIGUk+OZ2qLtSaTJ3npcLvnzZBZL1yEPgODWMqpRu5Xiuaxh80O4ah RrKraZlTii80BZvkNOw77wLUuaUq3GhhsitnrTN0lpOeTEIWlAtkz1ARSflRjjhjfVu+4qfCX78a bi8iAxp7u0NcacXx66Bmer3CC+slVoi8nCayE603tpebfSVMNGLTwtMGmUMHX6g4om8iObx07T56 Nx+HZnOm3JU0Hx/sUGEQymv6wh/PYJRDwbMxRpeDIojDpaZs74J4Io4PA5MBxfYVtioqSMGZZR8j VUhTUw3CWlz/CRJmxnPHhVFvqe+YcCWdR+tF4/ayqtFwmhzV7BGXft0DfkL9IkkEKOpccLIXSzsM tFAISxCvPgg6+7E3LVJmQ2w4FlG52y68Mz2mH+YPu4jrOuy2WaLYw19CcTcDvIdPUGMGB3SaOqT9 nyz0PlgwGTKiZtWQxNFqN43c06FMTETSKynSDuTGQDQZo2YyqoQo/Fvn8UEqupwnqA16zFu1hFmX 8mXKbJINquy2o2OTI+kPfbdFlw0O9hZ4rpQ6uB7kFyvL+JUN42Cmo8uwiFdvw/RJUV2ES4nH3/rE uMBT+c8XzWqWEi64/603FQwirrm44sKitNwnEvpx1mnng2xZDkimdOdbsS2NVBw7ZEgfy/Sq8uw7 4WBPcmWswHGbkN4txVYuRXTXaOq5i9aO5PKLunfYGBXMB01ZSjZ/5Q6EHFmKNEGk6N8nwMTLLkKq YYxuuYfxOP+PHhF2DQWD5JyzENqmSE//6jRSWl16E4GFsSK0gDcH8DSETCKo+OAv9usaNRZXNGNg lswGzOWSBqwNzxvUjck5swc4lnFd42dWjiYKDhReDcDnKht6mvkWITDLRQrsCoPgH9bhGQ3eQCj6 EifRmsyFL86opOgx2kfRqPW6Ge/3EGR7pNK6xtoHAgmC2Pv6Me4i/pGvUGI1J2kiZZ+4ePaUsped NcQTgha0nERH+trPTHJDhWUhqmmhSHMg5eV9/zbrJlRWFy8Gb3enBe8VQv2VN5SCI46nZLRgdVQb QqaaovFUtu8A6zZEOUjRtIb+EYYHccr+d42D+QcokiZzqLbY8q6hp5CzWR4F1jOROeINFbQtf2sz CxmC4QMXGnHclzZ6SWZxre0t/3YlgIAseaApDIqDECEEcpPGeuKgklHiWACFcrnTVAL9MuFkx9Fy x3Tu/ym3EUubWiGgMKyLAdHL+2X+bu9/aTN6afAdKDOZFUEI0QRVwbKy925Ym1EkrAl18Bg939Xm 3aKmk/nvpJLD1+frwKkrN4J9/PGHxKCEA1IQpuWTpyNN+iXQiWNJRNGZ6hc7VoCzL3+CkxkOALSL EboIL+YO9iVJ2e8S7KVkZgvVnJelcS/TYbypJR8lADmNK1VnIL0yOZ+/4dtWtcf3Iyrb6C7FPD09 z2eCO5ffRkVLzgAf7D1ym0Y5w1i9wrF2g4PabxB6X6buc1/x9WLvl+9ynnjujOgyr9aoA2oxn9VY mGpZf7bhH/zSuY27AjDGPi9GATVQ4wJRz9BqpltLBshmNr2Fj+rBphhFgf1OuTw6x7F87hfv3H/m 9cZjQ2+LcXnesoSchEKdDG+zaImtvuRfs2f5oXvIy4CZCB0lODIiL7k66YzlPUCOXgAKvQzo2X/0 Jz4xCg1wj08hUlccNvh5aEFaHPdyHcxih42PGjFZaCWfAOVo7ykPFUZMJcCPaLQXbh53Wi9kSdMC Tyi459YOvlwOHOP+Xe/OnABi94/Ky5YCmzFrBwwr2LIjWL5e63UiW9EtMx0Yqvm5TWYE3PgbZ2Xv OPEnsE7BjggndLCQKGhn8IX/qA7QNKwFm6nBDYTYVnBlPceZa6KEMRa/FQjYmetGY5w2ZDhTAd1G kVWLwgPWbFxsPBx+RlmWCzEdK4urEMxAa9jMWqhYlqvFqTayUviFVrIg7dLdSQBHVzmirxaxiCcu CIMJxYrHgRiZDym5Kw+qLITi0HzKfbJfauAX6yyvdn+3JNzspzhqY4dq4zV1skxljYhFoMWeB/5p i7h6HFoP2Dok0/ce9xasT80M4hMYr+7ajIiMXUdJ3pg14rm+ScdpIVlATZ/bVDYOu0uwLEKBxkAS eez/6zvnw/S+yMC/btpDWT53HflFt1iWTcwko3r0qRS4Yl53OdlH0z59aIDn/QWt2rs1KMbq6rqJ FfoUpSzekclpTnOLCwKTBOAtQGKEZdhLDe6umb3ImGHNCBt3yZP3htTZLsx/6Q8znKgtqw0jSWGD bCcvQNt7CW3C9ZZhOTFKWAE7TlXChfCAckjrfTE4ouON44RVkF5ErrBxB/tNGteMFFx9VyufcRcb TA2/AB2zdwe0owxr1IUBX38VdfV9U6SkjN1siwKsDkGmZia8CyI/HTKL3jTjJl1psn92bxFohs0e 32VEsDhu4dcrne2eUd6J8xqd1D7VuI4f4MklcXqtsiX1fukRGCFXmoWYWsFcPgB9CGJ7VKpxh/83 OvPnmYMWqYW6sR3z7fxsJPkXMfJws3KnwwodeiDHVoplUZOwaKelpd9Ty7VhphzfiHyRH/K+JH/g /gcpv6ZnyrwP+GSgPIaLTe1TptrUh14BcDBxtuZmvVUfW3cZnfrWC7I6pGjsdfQS/i8wUqEqp8dc arwGhvGREtxHx4E+d5dL2ZbzJDFUhyZW+5KtTx9hqnNChzNed0VOBP44xbrMt8RhPg+wJtm0EzJR t0tTAQle9SjMU+hN/qhLC0VjF5JyYQosf/+wujsQt6gGqJDezK9B4ac8vXKW9lp6lU3whLI4vcgZ 9E2n2sslAd2BglVM95Z5aij4k7H+XuPH1LWHXrAl6RjTp9cKhOH+GDoIlszjEStAuH3DrPVhXqHk He1jJL9wabrXoJgiYGnNpqmknexl9ByRQlXXvQ4d4K0nyMQ55VcHMQWg6vSojxwpoI5rssgDsoq5 eV/Xj0lR4W7h6FRk8zIwVSn3gUg0lN8W7ZZvGj/269DDDZh/QLXJUwhK+HNWd1kxyV7XAqM7eUNu ORIxPh9gpBQFfoiOp8JvrWRtsGZvU/lBaWgN7HdxJCd7OLXuuOwPT23FCgyTEEtHv2sUMQ8+AofE 54Go4mncJ+FTMN7RBwvWPhztOwDRA77TSfUhydLUQuRMBG8lKtiTT5Pk90F/2iOdxuyTUQkylSH+ 6sRAhn1WSrAIiJVXuMxgJtGLlqT85CYsWKONIx34pRSMOo/RtoJNA0MlVl0V42hGVeJJSmxW15LT PRYPGO3nzaxAHJ1PqHB0anvm4vUcV3WX42q5ec2kWPDRvwiPCGmD1Yap656QVLoh1ilZVha1lA/g 1jnqWuloB2fbZQmFWitlmYpXyWt9jRdyoJ/a4otd4+keDog8gVn63guV/GPXj4BxnhUY7sqt5QvK ADV8SrBuIPOrL1jrAIg3qXNppcEU6rIe1KPi4Wc9Dm9CJ/6gUmPIVDo5TayWQRtMMCL838zFH1Xi wi/jLGA+6ag4wi+aN65ZQ+h3LH4x4t3Vy/82IXOldASq0XpE3y7I/MXajwkBpD1os+1zooryZg86 9zq/aveLXP1VIqRON20agsM3j010fZki9zJH883CYSc91LYxGl9hspIBvm6u0WpCiNn25DA8hNZI 1ZRXQnkdbpnLH4c6Vaj1c68alG3Y8rqcknK3BjNHm8DK5/dS9eHco8qr4YnAk/mhnaOXedhu4zgA 7g2qStHNhwhvP4uqsnsxzBJXhqkv8TdtLSQVJ5ac8p7CX81SgV383nlLpCyglRTK3YZC0ux6Xjeu US8JpcMAjJa+JPe8eSZL8+6vgy92kWCRRCjZtL5iY1HTXmB9KwaWKbDY68HbAs+6pYjs7ry8InBS nFQk8oLiFEPxIz4jqgRqlBMr48aNttcTo0MbJpJMt4zzD+qHygcHrU9aRJDrrYo9moapDsiF98zu oUSfdlDNrsKfex6WjAJdIk1Kvggj0ARRMZo5zBDKImoz7AxHHAu3ku1ggAfYaSI8u3QtvkwNj44A Wt2eN0OzYYx5833tqy0Z24ynuojgSE1OGf3CkxXZWOoamIyY9Uft7iJw92yWwq140Lhrzy4jYTLC EfDypYJSDDqBuRR1SC8leNZiI2l0Lgf0NcU6A96W63pq2Gq++hgUUaMoyvucuf3Ccd7ItOzL+VMN ecNf7ZphAby9aW0gsV73xZ1FGWZG4VyVDM2K2W+Vpv+BlcJIyDM9L0P6Hv6Wkxjqse/nTcBtLN54 aAXXKmvcPUV73jQ0ZrlZb/CNJMvMONl6CuM86a2Lhi7vbNrJ+DKEvgNAtvL5YJtIdU0z5aEayy6F a/4yHnnb4zWVh68M75FU3Ve9cyFssYZYOT2wpePafA6tzrXAgL4Ic2fhMgPxhzMnDH3LkeEdjPAK ozdcc3Ou0jNUE5mZJWJ63YVxd1Sfo0FyrqN2ejjfi1E+UBjnWf5Qu+CsW6dsXbFpFdjBqLPD3yfw 3P2WoYjJLD3KgrcLqG8DFor2SnfF5EM+J1sGPJXHt3VGPcweCnWjZuhEMOtFD+po8dFBZ4qBHkDq uczyB3rV0n/Dkc2CqRGieGknJEukkDe4X4fak+cfOaJMtdeTf8/5OadAC48O0jbeaHeYEidgOnEu KlZDvAPQm0gh3Zt7rGMraXk3wfoaG/zhfvUWiJSJPjo/SaedNCGUN8Nz/tjeKWLpvChRctv6TgO9 fj9bGhhq36mYZD0CWBCOSJoMXqXuzChQ1cnf+lXJD9MudiyUn2DYDXNj4a3GQ6s3wKABdb/9th1M Sx3yLImAvqZWiYWXn7FfiqnxWUEcxKfZEQ5Xzs6H4f+GI/W9r98i2BLe7oDzEXpW5kL16b8az9Mn 0vTUnl7cLFWWI+tzMOY6N2XDpQ4aOoGhNnS2fcmIVxAB4kNl7pzsvkkq/EMDY00Ilr4HDeMWoh2b MF6ZpVgIDzADQVK0Y1cZPVtNpXZ7OlD6xwPiWtaACPS6Mj2mgBo1tEPyyK8rxMNjDwKSR5xAgJXh +P0KEIkwFPxL/IA5VyAMc92KW33eWTwSk6/o69R7hTpfRxiYY32bEQx4mG/jMmnnsH+HGFFE4qBX 3t1fRGS7xUhxYBu9REE7lCnJE0YJgGsRARvTIzit9TCqz5XLBS3QIcX7he/swfwuFX6gkBRf4W3i YpXooFPqSi6nQ1zl+0uhGgVDwKn1+cXCV8vA3dTaPT9VpgrgO17ZdLMCZ9c5XGdaZvK7gUXBCbIN tU5EkheE4hHvvtYdxXMN/8E9jY+ovaxfQVA/HQyKFoZzIn6XGp3/B1s0NiVN8mMGrQ+NUA9YrhEC ZyNJ2obizLoqzSpPL7Xonm2PzQW/ECzTEn+ZxXcqs2ZzXwhDD2d8IT9r/Ng6FI6p49cVphkifogC +ZdDaeNEGsHGeH8tRmVgV2AOWxKsoxAJfjT9K0y3tpKS8K+WCHdDrYeJnFyVBf5GoYvyvl+TGaZi xA8tg/83yPkq4DFe6RA6HrBYDjCJAfHqGysMOET8bPeNYV4NxkfQxMG0vaqWeJP9Bahh0ZdxOJfz VOo7EW07vGIqOdz15HhKdH1AGe81Wi4ZXk+oSHM5+px84spX4TpZteDqCrhMuOTM1pK3cIr6t0hF rwuhCoWnXX0DVtLedzJdWutDKZ6CuyEJ7R+Opk1RjT7Q+19xOu7TZUsVR59scGqhxIQGvcz5eH/4 9OUrOc/ljrk6K/Taghb6dlFGA0On44Tuxey3buRSeShsP6/M3qGe6C+4len1FnKbedHh35aaruOc GI7IrK5Gr0sk3QBt8j3IWke7cw7SsyVdBVOCEU04nZnE7YFfflcqYqmMDW4fUr6AaiyX0rbBle5x ieMt/5r1NzHPrW8T7HR/FemBPjddHHOu8PYn88yCicFCY54NEgc6zQd++TmQ5utm2iNdB13+IxE9 BQwXspj4/kkcHIFanFX7VVmmTqMzjQNWYfvipyIlc+N+FGY7iDZD+IP8FNS+ytuc3wWOSbkziT0X iWzkAyrPnf0WY5Eqx/vqCtRcobwqnrfrhlQe1hWh/TLCdt6/q5gfYl2OP553kXVFjGu9gVuVyGEa My1c7LEz31Df708jmMwNX3ePcB3Dbdhd+f+DARkhjGSkGOSFmBQSV2V3LpzAkprb7dwoekmoQGgG H1eJeqEUP2vLnM4ZinMetLn5pZ742tHO/S+zsnbDktlwhlza/eBljvFfk2NtMNrariQ1Zs7hb858 i45uo1QeCMX5sAbmNU86cdY5o4vgQaoEEtWSSFS+kWcoOSGBuF1FXopyrA5lLcVLZ7sIoA5bx+gg QKzsbO3+yLIGwLTdDrNJr+ymhH9mOXQ0dkTJNBt+jqtdQOyqJInU49o27f54fi1kFgi16WhPAMka gcu6o8/rajuV8VmYvEUHfC6CHN4FBhgr6dmGdwZBTpiJCGfj29v6sSl6+BzREnpMnRurvTTcFG/c BEKUBuiyYOl8sGtbI1mzp8hMVXvRrotLForjV95GgXszOPjkVVygObrDQ2hGXj799XwErcusODio SvaUYvP0XJgsf3Hx/osZP91IAbuyCCbVbOHe9GXrn8dL8NWxk/qtlm6hPRs3PaJoP0J1BrZy6hMy tOl2i+zl4ZtQQ56GgRMTLquKp+oc5QUKrUVb468JTBmyFdOCfEJ7FDAj97VvyD+nYUipEHfrJCiI axgagVeyVdcM80gdNNV5KODMVlgLTwNm+WAKn7ndxqmD1vrKIFx6FbrUvR8+iVxYjg0MhDY4BTua +k/JCm0MW+m7WAErMtAb+Sn3af461LdILLTfnVH6n1NjakcbQj6aNncF7LknUR6PvscGPHEuFsth ckJTOQn06OXAjHiFxVO59fQDFAQzKsGmH/7J2dt/bfUwVPJg9HZoOlULMs1VqnWzT0cQBUc90mLk s0KPV+5Z/giw/0pWMjxkht9X4o1Yz2qOjAABqcOGEuqgB+haCLfP9QHWnqZvgNVjbfjGIE2pk7by Nr7kIs2USylQWn5erUuIA1jcMVAhqopS7e2Anm1RmPwZQCxNKr/GTD08JEO7dsNoKbW2WsYk3d/n f9tZcv+3UvSQdUv7d120Nl0iaFHrtx7bsUYJasLPr0Lwh5yt1grSh0yGM7WmPyi+3O70EPNx72wA /wJE9Qd08ITZAI8F5cR4FyHVDXNMLpIc1b6rJURFZLZD5ITsNf4pkiPCbhHxYJaJ1wzYAgV5ybb6 wgNY6DoT2El2+AUHAJf85ftdY5+7983qOnKHKy++4r1f/H2/DpXoJwy6GfSJY0tJns5K9yq+Bec8 /eZNAsvpiY/tFFrepLCoAU06GcZE07lTAnO0leAblpkIUOr4Wp2g1FvewHFhDQboHAQLs1mAfH3z mjqfpyuE2MDAW2DG5wnpfv87toF3SlvwA34hy4mIAei/uJJLbQIsPBHEe5HmKtVwG7xKpdWlTqoN fxixFib6YrQm1RucDzUxzdO271uxNBDdobD7aG7sUGg/mGcdXdsPL5W5iAgqoAvX7MdOLCQu3qVq BKfI2WQTAOXajzvOfjKxm/1Z4Wxzv0P1Lpr2cF6XEeaUPp1e/xQQ7fjLX2Bl9/+Udp7yuNtKVjNN iWQNgMgG79R4OgfFQbQgMArbXFYBV5sb/UE5kxGhuFiy79FudO6gGhAGHBiFrpvv/qPGLy8YnVUa 1GVVm9Wlv5u8IayumGndKX4P99adPdHuZtLtZBunrmezq/zzca4/uB8azO5tJL0hrYaUzW015D9S YRPBMMHULJMcbKc21xRskeZ8uRzw1guBnt2956vDJJMrmHcC1KgJ6Zcckzfsn338PdO5IQabFoaU uAlHx0u4O2Sp5coff1FM7hm2L1sG/T5ctTLy5lvFA6oa/8UmRobjTDP0ikJX4yCjJYa3rnYZOPbV HoM7iuRjyZSa/v7yOdvokE/LPLryKG0x0UtjnnGCmf5vOjPMgoKEEOkNLTjO5kzBQmvtPdqy+0B+ wh1H3bCp2F906Yf3XxlRj4JbNl77mrCY3apwmRF+7Brz0XArQU6Eu7kC96QBqDAUQb+rltYiVx9n nEICz5gfwOKfxei+pkYLWsDM8LxPr7q4xXhCAPeDYdw15WQqC0Ogrey6dZLBNwdxgi7vNjmzUPLh xT+rEAmF6k606kJQKHRFu/TzHBdC38NwfTyDaccq5U1UzRxXwYn+AtGaDR/NG8mcXOiWPOlA1ggj 286tiv+vbGCvHjFWqrzRc7aApViM8dhTW43YhBMwYhse1ku3odECc3o9jIkhznkuNNdExIYFDP/R 4PlfQXPHwcowz5SwILiIQe0EBXesHUujWa+OMPAnL3RJ9xt7/CbG65W5vNVF6yPOBQsbUxHbh0da HjjBEvfs+acgJIFREkSy7OU68gIjKIsDhjU0wAeV89uC50gaBI7NK/Y2JBSJ5HY5a01a0V5F5uuc mtnOjoQPWMQPkYnonO08VTmIgmExRV0TSF9Uk75QUfW4OIahrh/1+fHULGRZJM4KuxL3/jRcfVlb eTv8AmN9Jb1j1DWkSrOQ5yQLZ2cSsIlNBT2IQiSzjXXFa/VodW8ubBIhe84NnhuUxKipSyl2v5EL 3MO/E/iINyGEi9xayOuHEqrtUIUnu/QK4TMkxcFEP9mehZvx2LuMnpcTcxmo9R6GHk38BmHgv15w yfWdQXCdKkmWs+Q0L5AsK4SwG3CGCneDupD/2aJjXuWZthr3LxYL5SB9UoX2H1w5IN5nKlXToNPF Zvl5JyLAQU2IusUVAGcPIaUCZYk4GXRv7Cugd785ykBAhijDwmE0+pHOZ9DtfTQ220Fq/ioXf7Gt mNbRmkuJPI1WLvU/gHINYOJV7sD9aS6wnWneNM/pzQ1YkgDunsWnrIKeVoouzhvYbk0jirEISjX2 44SlIGPauN/nqr523TBN0drJq+clRsZ3t5Ej7OsfsoAwKX3akaNXu07PqiSNG8UtV60mn0ASI66S /HyWngiksXqUpKE0uK3g9yx55xgTES2EX2eWW5OmWJDPWh4GR42sjRw1IqxT3+wQLyLLT4ep1Uz7 NvO8Ix9DDnYjV9bQak8DpU+STIyGqE+jt3PZ9uWzFUZuMxgy98gnU0Sv38iRg5Ahb6RAOg8Z81eC eyu2w4qn+dNQBXjPZ+uAAAFFSYF4KQBtl2L6PJO/j4KCdT3e9Fc5++Y6a0Wwxz4CkaqgmKAwtV11 ksL6NmiSOrSwab5A5lPoCkEAoh1yb9kxmI5olanKPx0aVp4yQ3QYa1qlLZ44y6x1FLnQc1D9Jykb N3vg9AV6JMyCQJd/01nw8mtx55XmHFUjQUXGaPtNKyR3eOrqxuhZBgprYoKqcf8Ft9y28KTIo9KN 4vY8GIklFtnn3bOCcHaPUnnwH7EsTftOa1dHTy6x54FxWSOhBHzqe2RkMw6VKFcuqJIT8RQ+1PCd 6fBkQd8f5i+m2icsQf4nV4EEWr4yCrujL3U4aKmRyPnJp3zdwKJbR9rcwPP4kTSOnL5PZyywBoAV fYNMEyLrjwtVPwbXJ4czG5DiLwiKw02hSwUa7o73CO9hMJw4RLyoi8AOTqVEcLgpEU1cHfcgpvzl ObJyQI8f5IAI6BZX4DKXLfkvRDi0DTOCBOXKd0csPzhS1zaJLnUymhi936KKygWVT+Ox6mXJjVNZ wqiB2CtOXEW7qKm0JGhNtM+ThpGp0ilPkieZqmgs5m1JMlqozntL0c16lCVyyHLvKC28rZxrCn00 u8NysJkYClBqvjk3l2NEgYM5AclwGho0ZM9121jIVYNUeD9RHlmlXIWlsA4cqvLff+egTqKmFui2 qfZc75k1pcECp1HAlUUNhIOOE0GGSKaFgtObPjx8jquRdNrRuSFK7lefxm5MwpzwLXsT7zuqoZzQ J3Kl5JdLpOcg7VpVyPjKWmGw3BPvnbMOUVOfzTPE9kjhZhgrIzFQMcdZDGaIQUXSyYKpvWtqcZPB ypF05voY+oUEfdw5sttNLk5maxvWTDAweFt+AfIcZ4Dje16M7DMfJKHWAmGK+md0Kg1Z4jk/A+ZG 7wu91zVAP8ZJj52XwdY7R5wza517KmvCvfUCbkMqMp8WoKkauw4KztvRvlcN4xhGcY0qyzDQM3lm teBYBkVfE78sXB2g38kmgdyEQFxP//CmmHpmGNHOpu+qfuFqoj3T1Gw/SGg8PJ+bjAYHS8Wa8ilC M3bSbWjdVx61jeNShfYWpkQ8x0JPJ1hLwue6kwpjC0Gv37K17HN3o604TNhJo8xEPi27m1ugfO4J PSJXlvB8xN1a0UPBFTmbc5+3VJ8FhjjsUR93cY2fdIzSmO+oJTENIodzg1OCjAsM8OlqbN+90iD3 ippzyNG3cAnxEWu7rNyRbzeaeWwQA7jWIWL6BQqP2eq9dHDqO9tpGWHfhAWwXvddZZrIBdgh5mtO /lNAdZWrC69H/SYgWtwn/D8fap3V7PFqdj/TdOgK5vE8xYM8VpPa0EmuZNcDDMoeG1xMc/8Q0Oq2 /Ql7+BxTBxyG02qhO07DkQAow5VGrd6vf7GWbOBAQHYckN31lBhb8CpHqBuhGi5y3A/YayrvUZ7m MYwxhN4iw31IXAkzDZArrsoy/+fnEQXGoul55hYPQvHQfSC3x6hwrJ6I2GGIQGq35d+NLjzO34U6 d1hBNUM/HGlMapEbmKTsKptRHYYlkyoO5Bef6aWmzTKfHZJfcFlzC6W8xAZh4HqusmqWX2k69vG7 EuH3gbyTs8VOGjutskaRTuUNWTE0NkfIxLJWD2303T+hNqk1l/w6rdM8KlJA8x7uVMFxSCQhgGAE qatPpuz9GsYlxeijqgP1RqJl2Q4MU3sg5UG7W6Pb57BJlTObruFShE8RYL0MdCuEN6sKKwAx8lUq Emjn2CvZB5nckclBh4nazyFYhNkiVGJKjRNWtHsRhsWE4X5Y1b2kAO8ezatoBLXMit+8akp/9b9p ZOpx6pdm1Q1snRaCwBYtPlKGZFk7f3ZhHlP7dOGk2sFqTpGccGzPQIKQtHSxlZaBA5iYG5yYI0Qt T3Gc6PoNXg5NebzLzEkADOizQQi+W35SkQSmNbfMAE5jKmF5/3hDDNaCZTuzb4uZ1uu7prxptdht UczsA4zD9RSWQpvBq8mK19RcENYZKLv0+oHEHimsvJGQ1IIjC+BV9PIrdn72I0kS2UJpPjI6yhXo 5fCkI+kS9pRyGFWPUuWjr098xxW1wMPug5JUrFjf0hDhrlrjcMnAeVy8wtdKgBlGme6aQiG2psmN ARuhaibakRqWBfQRBNvNR+tz5gHPk63C5D3sXFecUrsngGs3G2byF1tRdAnhFjbxDN7f6ebZ5Cfd WoneW28WPQVXdqndyGC/HzppwexPnHzIij89Zku/4e9q8SFZuajKaA0tOwkE7+Z5uz1EIzW6o9Ou 4teGM1sEgPNKDJ8cRcWXBgyH6Et+duYXpZcq1y1oakkWEX3bFrxosE/UxihAUKKV+ZeYORrf4c1d brhQxouA8fqMwGEqzdJHMNLUcFxorj1C8NqqHTzHkufrMdKpt6YhepXnEIPGFZ/bPQhKgUXW0iiv p6cx6Dag81VuVAm0pOskW6Vzbiyxkij7d1GPO7vZw1rUkoSsFXNnTxsY3IMVpvepyv9cDClww4C+ WT42oDC+U3vsGCZlB+jOe+nho1cEZDkhYidOIGiaEWQK1e6ofOTT8ntNBi2egnVSL0nr29QdkDKv 4IHVR6u/ALKqdNzEHjB6p/X5XZbNn8E9siQdBkJXNApVQPvNLRIL29his7OH5XuaGHHE9fLG8mBX w9pMHZq2E3n6m+Ha6yDWf0W+i0sURmSOaszANfVj8nuoSBirYCp+cIuzNL0gkDYfVjdJMTpdm15V 6EfeRYGE9XGT8eZ7lHHqun5hM/jsmA+eQGpP5FOGU9LModsm28rfs979HDw5zN6oahd3kr8lAjnE J0Mu9pZ2Z2mlj9xZE4ixg5a772Wi60mX8IGjdwUDJIPPNZPbLpsSVKWPH0m3Qo9ybTvSWaZwha+g cB30HVTpIgzJAQkjQZJUYWZuIg16PebU3dl6IzXgqM+cv1k7WXD673ELOi0bdRAcgtHO8nbZnvVv CgW25VorhmeTZO1C9vdXxdQTZ4gzrpSDoWf224XK/2ITCzWpZQmPIhXutNni6rvcuHuYfttBOTfz wVniSEw8HEhxjuP8OYqxt+UeTwIkB9nB6Vzcp68v4a4NDLBDct9bsFSqh8a2aNWcsVWVmeBfYAwD 8ivqfaTz6S9fI2lcPuDS1ito2xh0EGKvvOCcOlrn/uK4Pvfg17wO1BX3e8TQjg90U6KLpSM526GV +GWUcV4rA40t5P7XvHPOF606V76etbvrUa4mBOMGFMgo/cQKoKulhQbweFPmfSuulghR5DxHZey7 QUSBFrg5dm01eBRz07+qhyDbWqnG4PbWTUxE/LHWJzZFwGtuIETcup/5WqnN+22qiqU4clbAsscp 5UAQOBJ9ConvTh1lUYLMPwDWey1lYSrWL7faoHDl1VKr/63woNnBkL7lhdPTZ8l48NMWCpc3QuZ5 eD1S9pluO+aAQCdpdinDYiYLa3mm96dXo5qWotKPsqQ9k3bu7Kciw/UTGQ8DuyafdrRdYD9oCR2Y 4OO3G9fA4j40V2u6mxYpLD9yewTvL7GzqohPaGIzpioXwrUuryNKxd5AXUvcLIV2Kr9CewWORdTI 53Lz0EnUfXQzMV6QarexTiQ/GRIHuAyNy5LzOkMrBnWnPeXtEZ1/qiu1z+QHulwDjrUFggbWwt9T ynhXcwsJnT6FamRtgFXTAeP9lv3Rhz+DMmj+HWYmAgcKLrUZ8zO96nX32GKEpb6OziC2vm2TCGXt j0yiNl8PsMk193pQfoj5wAbeI8fAV9PIPOQudbymu1N54Urz94+ZS62HaOYbVpuNwR72D7XPMza+ PGnB/yZIciwmeKe1Hcjk7CB2a1d3SygGQSmuPveZKo+6SfukhMQDZ5VBpv9XwR8kdWjgrrK/VMN7 voNTM6PpqQddj31RCXJzVLeSYMqfzNZKML1/Is+eii3IrnWTLJeXrhtXV/tO4BjUvY8aDKfMsTD3 uKYfOX/66ptErwRP+IUIo9hi3WEXY2sPA9fZ+dvoPjanF1kXVA6Dx1eaYqFsXB7RoqjIptEaL+5e 4547wZXr/TrIPhu2xBw0aiUyYlugoiP4yqu4HpuYmvre82HcVm0076iqJXWp5bNOCR3HhmjAsmWd MNNYIqhX3/3l4plCl2OWKcN+VgNRD3O25HLO87GXGpSh3bw6rdpSmA8X4IsAyE7vjvV+cmv4IYFM 997s9uT0rnjtjT5DkiM+RbXKQVJz8w4yY44L37dR9sLP1yp+c62HoGAp1XvQywgrUS1d2Y/2y4Nn y8VYDjFZwQqcV6v+iOzmoKNBnx1yxnUVkrMgsGLjky/iGtkAoV73kWx6IaJWyxkK1Ud4U8+D6Wle JGjtMQP3ME3qMK+xnPqnPbYETcnu7xSBQkobeEg5G3pcguNgh8GqQN/o4+u3bFdo3ywO2fJRw2r0 wKnhjwQQSpJbjJnglz14D3iEmLs6pTQNCXBPZFbiuqkzpdRFBzK3yIrlXe2Y0sUb4ckFmLcYj8xK KurD53NZA+oaoISKrRYGt8NSJoZw9WPkx4T6JFVX5Y2ekTExzg4oxWL1FhiG7U4gmvdviiisQsjj U/igSBSgtGIcZzRSw8C39FMZJXj/YKrIIKJDvD8JyugJHexCZc0+sVCWQuN3vHmWl8qewQ3w0EuW HJCgjCc07OE+yNXf6ZgsZENvYxFuhto35w1cFg0/RGNF8dP+DQCeWqcKb2WjnjmqK/XchOpUp350 WhqXMJS6PK872ehLLmoJvDQYRoLHqrm5kKAx8NR2InxiOn8q57lXLHt5r60qys9rMNwI7y9uJU7u TtQDSqHTTYe4m1JeEUbpKBw2xraB/r5zZ2XbVMTxLfPt+tHyGiq9JwOf/5j3uHDZJYYtmc2xnV3Y o9/eUvG18neDou41FAAeu5VIRBWQqvs7KGXnW5viJl6h16AJT0iKf+cfXULy9W/YYqFPZLEn1z7y G/BStt89NjizegfagW6pRRdb1rAC5EtPfT7+W9XYtk/muS65fCW+IT4yXkS2Q1olGISsJ+Zf+s2Y 64bWqB9NOQZKbYooImwVOt6/K6iaa/aPS4dWi3rSkybff+bFKUHay6PJfM52/JDJlCdnjekszQUM zKiiaSGBgJeMt2ZkmUsS5JNU8O0cPOxA+QUGrQJxLffsAmsRv9Kmdzcqr3+gKpsgxRCnUsaCcBXd mDwKAVGBeUcv7ol60T6ye1z+5oGNB6ZfVanJgPTJ27mkkH3osowHjg0q0Y7z3TwOM6QExsGB/y9O Pi0R8+Fx9ZQfDLKzAdMasTK/UUp1Lrx/fJ3dMdhdK1Cq+H70s6PgiEyrMCmGVYFy82sgPCp88eR2 sPdcb+n/O4FFQlPAzwA77dwv6xvq0UR32CQ3sABM8CZEzSPqXJaHbW69C7dZGhXQRbucXhqSYCB1 OZ3u2d6TVHNvmRKeDYS3YlWApG1Ji/O5D1fv3GvnUUzi5f7gtNMcD+sUQXPM6ThxUt+ahViudTcE n9Fv0paUG9I1uPstcNv16muV+24LVUS9WwW3be6kCXL2nQnLIVk3lFmdbIWy8DpxDZkB9DwKqPCm KMwxayFVPAl5MQ5S35sVcuXDOCL1W3lU1vz+hMVNSbWXD+ZfTIMP7S7h5Rv9yAIzzeorX95QbzR3 iJzRqibLqKsGOtL1zZWS0oS1Lls+k3agCOQyVa9bwuMhPy5yW5oZP82WXapCdJtoxMdFjVDdU/tS cuvYUlYl6Xziub+B23NyyRkLWw+cPfPErHDeVXFCzrg1EwpX0oeTbX6ec1xJdVCXEi0KJJGcjBQD 2shVbuMBwlzxk13CY3c8/1k5XN6z2nq3SHOrVMDIHzAvyFUrawXep7/JOWgLqgUkV8wmZF0oi+YM XaNjFez5QvkQWqm0Lf7J0Fc0bmDk3mjn4qNka9eLtjZjn721IRkR5cdHsqCwBt2psYbq0Shm2vWw QGWBxHWPzOZ6KLNmLHXseGstqtDIqiPfaPtDTzGHyqb7HgWPQ95Z/L8WJAemhxQiBc0r0NUNtvmU OdQKHmUHc3PGwyhFkBpc5wN0sb5MVy9y20e7w/3qwQGHAbfbzLi9jY6Z7uLuI7ph/6Gp7iBSQdtd fDRzFEqL4zN4xcoY79SW9IxfAKh3d07ovLAEZeaLmjfZZbBd6xGQheiRTcp6sbpaZhbbxfjdZPPv Jy/VeljmP9UdYsLFvm+33OlIT+3jEdoCiKsAzUM/8kF+ywTfFiKvUWmtPcTzz1XdpSmLp3ChCZOR aaXsM1AUyl9nOdnWklW9IoXjS8lccQBaqOhiC/VJlJrOJJauI+wyJFwkLB1xxYZlREq/sIdnRKIA yYSoCd36uxkG1R+P70vzC5tUmV0RbJqVI3OyVuOoP/1qjwBhnyhIpfuq/OvNQbTwkk2iZ2nQEzf5 IbXoaLj1ZsUYCRMtazu+8NUumSaVwdDU8AFBi1uuMDUF1Wa0oUXqQYOoZneRpfDtjISgB/i/GK4L MtVzZO+5IMVe3DV+PbOg+n2djfa9muTB9Q0wkOxhv0WP9MCcv2ZQtJ17vBGbuBh6GfdBGuIfL5RO WnTSHLSMsbLT2ERYeRnycdKxM6LLdtHq/FPzZSK3C8SEjBAMFJmeQoFGSlu6fAaMJ5O2OtNOFx1g RFu2ZGTYE2MjbowLM5Y66KWd8FowIGyqrcTP2dNt2MRezZRBibRREBQIWRsDDbgGGJBFI//YnIfG X/oJjmTbKIL0XRsH43uvWGQFFM9yBZtLnw1satApSBzRSTWVEdAkBlAXAp/E2ls8oI8xpkhA1Jty xsuNVpFxDHzOQdhwYv+amoGqRS5fW6ORJuWQYdl78VLrqcusnYSEY7d6pImexRWjiOj3Q4mlsDGW T9RbAbARqVawzYtb6wfbO0r6Z3kaif6NR/2B9GAvoYh8nu/YCsnlgPJh462bUlJFnkrUwWxMKv4I yhmx8mYAeCZwqzs1CV3xx+k7/Vq/a45OuaJECgmD8hwAXKfytsBFK9xgsQO9wkp9qh9Jbs54zQZX xwpxKJfQ9TyXn8tfdd+AWS3mfv89HOZFA+BL2JTNd/eWld3yzWvQqSB0beAX5VMKZe+37P/24zZh UjxXOD7LNS3lmNRIGA0hgEzHOnI8em37LuNTweOMot8fx839ANnpVPZfcaPICDyvjP0kClFD4pny 6pKLrnBr7vvzZ5bLrvA9i3vML3aEQdgHtskGwShgsEfolMWfG465rulJAoCYtet+Slk1ffZ2GVwj gFfWBDeJ5htX3DpRZrU7D2PGHXE+BjboObwuSxNj56TbcxwvBZ/lLpXfTQgAZr7p4k9DXRnnYmTr p3glEPsjRzJBSJ1KulmMjldbzVeHv22cC5zQJHg9ip3u31Usp/tW64Mz6IfhpYvo3Bm0L33m5uBy ub0BN1jrDneVqsel4mfX7TLQXZXCxlddH8c091xizdnIsqkfFLGcA1lH63OtMg5WAQddWG3Vlmc+ fKh2DruCDc+1KGC7R2xXrY466O0EQQ65M1Nr2B+mXe23fd3edomPDMimiv0MAxdeRPVwSu/Z0dKD BTuGmQvoDVt+iZttUVQG6YtMjgjyjxEyiIyrcra/qQZ9+4GgP6CQ//fmdmeaQdcDRdTl1idzRKpU DXMOqe7xxzCV1uRs8GKx+bsBLMi4oMrOsjHfUHvI8h467/IkNF3ntci9opV2rRkWG8F8cm6nAD4C UvYLo6awJHZixK9N5P22OUiX/lp6KNC1+Y3ylWuPsPKh01cSLymie02fxL+rumEEcuZbYA5OSuL3 Na0XbIdk1rEb2YRZQaxWWoC2HJOwyjFmL6qAL+3okQL+LOob047nTy+xyfMsZgyAB8IfBYEWwB2n VtgqMPUA+1B/GXUvSEKdiWwLHzFFV5EPtNVeA/hslDQ8pRuc2XnSqTxy/EgRWzn9k/4/GO4/O7BP DidLeuEQt+nUFLOhlB+JiFGu7w37VUlWEeCAZOUo5gO2uhB3upSvDd8/lVBAvNpZIayFyMPAUbMj Gv64O9dIwX6mZLgmWFroewAPSk7emw8PcxlcQAZbfn7xR395NxbbNJUvxGYKeLhvKfc5X8IS0PLU 04Y87HPmigIJstHEcNxy9Sud41gA+mo+LUw/+bwu1Y55cRAHN/SJxdtd/Z1uY208cy9UaXvZWiuV p+TdFW7fKaojiATDdk1xJFRLE1OCwgONa9zqsJaDeZVCl1+WZb6nYaWu1+/2fsrXtvDTnpahm4d+ 4hcOc7zxzPJusti8uux8ApUO37O501z+VYNH+fKNKJPOduBuBKWF5Y7HHpxhkC7JkFecOItzGBEe Ay1rPDYqiYnPI6kH0VlD3cv1nUhXoXLCywG1P/61l1TP8eWmldRfJkOfwRGcHR1+k3TtO/O6s9JB pM1kjCinLqJ2Uquv0FlDgglQVPNxxfNrNOalCVvnpiXi6Xolau7PCiSXXNqcACfmHgFhbGg12u2o Wf/ofCDdZCoXycd9rt7L4N7QqStBj/mixhSysmuiapjsYPTRvNjBHHDoSXuszAVE4PBbfsZLCK1e U/BfFHw6gktCBHsazhY+K+4v+4r9Gpga2PNCWjq6rK6DH/OpgbtUssYazybOyG195amtBfFC6zDJ 8IhL7EniaXU+4c1W1AW9zWotZK5CuhJuP6hWNw5EJC0TFMOkSsb/Hxcvwlu58/7gDovyUCv4zDvS syc7dKoHh3SsgzNI3EZg7JIzd0E4trLlO4Ucxho/6w/lY9bIwzH7jMm/EKOszwUpfOgTxWH9mT5c tvGywMWmhY6j+Yl9UZYIPqmycv6nBPpCNEJbDmVaf7WZpoQqdr6COYUa/DO6W4cJC4WcIuuo6NJW lQ3MjYd2tnVFhKc9v+9fwJqMSdLk3uTtVhF2+W/aUC9tiXth/MwSR5fF4zvZ5wIoDm5sck05E0YD SaA508Mt/awxbmUOEfu8XOyFB4ZUR8thJZcXwsXeb6i5xkRYufTNK8qgZnsLEOekzED59TzvANhd qAfd9xYq64DwZS1FVWAYvXHST+rmfgo2judeYWiKb3YEKi6vvv6URc2IxZjj3uyZHCgxZ3E8BzrL wnrDN2rDsG7I9xSNy2VYCXI7AyLsGHiBI5DsotM5Fs92E2mDtiypJThiRyVRwStyziv6mcqC/UKc FeH6XyFwMMfSLwmagCsj7aTUtjljuloJkjWa/4NC1elnmIlNpfb9xWUVWckTZpQQwrzjkPdUtMrx b3mNQHrKWWG+sUwsg8r3sCdDxAUkoIzxUL0jqwSEuAa4FNZwzx1p2p4VPZUGGTQY9Bo2UasSONCT 8CSEdTQwFETGKppJoGz+a/KqzTgNm6T7Sp3oEWuo6pLQJoRAE7qlMvd28SpplCYoafBza8s22zFA w50HXiGCFqI4GJve2axa2PzenLmC3ZqZiHeHEMIcXmued93jeuJQVOOArde/2ugfxP1mbDadoT36 Q+uAw6RSJyYYsLnoqaw6D3RDOcpIOj/XXj7Wl7RlUjYN/nHXuG7vQUnBjX3TFQcWUN1PVImbTPeB /neyo/4N1hpLmBVsGjTpFKcWhQjrN0PqevxuJSvk0kdo/3oCKAwJBHScKBXX8qjQjji7+Zo4p3Yf 5OM7ni3ego2H4XLCJuP7Lp1kxNJLb2gi9e6w8naKFs0m4b0KNBExxl+3A144Q68t4ZlTvmWpGXVR +vEgEcqBnV+c8M42MIvoGuRKMj+oUst2yIbr2ijVbaB7siMYQi/1BfmCXOgKK+8lORXeUplTeacc MG8lsGV7wyT/gyqEEB1v73ywGgrgZ6RKiCTNT4QEdPsgDYvs/pooun7axF8/hfq0CtEz0A8EiE+5 wigRT1P7v47+NaZDf2rKQMNrPMbg+B3DP5Z5oLg8Ym66ybLVkhcEFYDK4iepNTm8ojyrb35CMa/E AWo1PVxp347fnifjIBnEzE5O6kLqr1RGZkLaKUYrP6g55pFudV7RlJx6nwqdp8M/ruq7o45/0Lhv 0hZghwEVSUcD3T2z3JMk3AidWyMrEV0YuVsObNs+wR4uoyxEQBSHXc5jNCyfFfDSCfpWdgcd9C3v bBewxgtpj3MFxn1g8KafmNUD83FP5LVH087KEn2gJ6cE1vObHcwu0isZtCOGunPE2w1cruGFEPks Ed1hf9Sv5+87+alZ4MdiFJXeoqeNFm3hZMDtP3I74ADMNKHExtPf3O7sh1V9WCpTry38RdOPZW7C Es1isjD7q8HoeJ0aJhBP3nIq0eBF74Sb9CKMGSt8N6x+cvRAtc0yFDmFvSe3p1kPw4mwDuUoDCDC y1AfkssJeq6z+pqCyoUALtETANdtmBBEhAw6qZKDEr0v21kL02nU7x2gyFjlE3rz8WVB/7E1NBVX 2x4aBP/T4dXSi2sgilsr04PmD1PCuYvtIm7G+sZJ7MPf1zpoRYwuv6zToBJaYqrjmMRhbQAGCht+ UFNzwCQeMEqwbo9OlD/gSzs/lVCfYYwYdgRZ17b+xB7HPFhdVKoUA64CJbzON0wpWyHjA73jmu7C Px/ATMiWdPufBIewjtp5oPd30YIg7v4xymr7C2IEjDqXqCOPOr3tiB8PB8orYqA57fx/8Y6OBJI3 JaxHevzkzQnhaE/fBQsmteXv4BoJPu+/OJGshK04nqHP88zMWvzSLDxPIla6REOxtwsn0H8ErIRt WfXiWpTm5GwVvZ9SoL6mouL1fafqDnqW5m4eN3GbVxD4yauu3GTTCb8LtnO5qSXW5TiQ5jhq1+la JbLj7xQ5eClp204uFapqN6VLVgkk8dU2Beo8ZNjTsfqXaQActGhXIzg1wST3ubkW9OcsbzI7WJ0c CdCmPkIzGtegx+5ITLPsKUOxBPWkGrECKslswfYix4e77Qttk10CrLpKipeth1ahxPcHKJzl4HbA yfR+2pij4pFmirxCjcD9Z472WZ5pz5Z3MUyXKsLZvl8miGVN7DBJeejd+9tgL1Dxd+KDcm91XoMC xzii6OLy+rdRTmOw0bRevz6RW5v/m2mgEh7Xxm/+8gRfRNgpHsHIaKu5mB+2NEMTVes4FezI0fjm 4NnjFXU6uEVE07tIGc7XFxKTRWdKcIj79cic55pw4tO0lKQDkP7A9+OUCRuCzw4IYwcZkDon98n9 XvW3ik+C+Tri9WtBlboANPPJ+1NVV5H8xdQeDnx9oh8cwQXHIvXy1bBFLYbAII5BmZZSj/pxX2Kg 2JcJy8csiffpAbUziRcJrnp730YGMFBVr5rNoMoixnNBWrr5Ucp80N35BKT3oP3DpeNe9O7r5AKy Gb0vxrWNl/N6p0dzzoyQfNIwSf5alKF8h/ypT+d/V+puls6H8Nubd6miohTPwDGVhTgEx/2JU0a6 gQwM8OoGFEU/YvNUimuIVJ8OOBnvED/2PuPnByRPTpSqUV8EODOAJKWVKYbtDWsJef7PbHhSS8yF KsXoSkCuxDf0hy9JwBDo3k5flhx9nKqE+TJCnKa/3TgBzsLqeCJ2NiudC5kksEz1gKrViUOUMsg6 9BRqjz2gSQZ8MEo59R1+MJYROs9zqEyxZocsNsmArByDLh5qTafvcJOfxnhaxsPlq4UiuetcMBd2 YnytAuWo1Uf/eNOIB29FxNkem7HIigthP3orVAtM6chTf42UpLRxTcwyO4ORMJKZ2dJSP4xct9GL HiOSmyy3Wt+K0PWGUBoYQ/A7LJheI49jUtFjMpApGsMAPEFhbFXCcNsaWWBGAlNh6PjfsmUlx2Nd OmSxDHKZweZxo/KWFG6Hxl8bGmWM5xtkrn+S3VmRIiP+nD6AtN4DuiFT8VPjIy7meCo5pO8a6tty cbjvi2l7Ke9tYYPOSKzmxeq+Pz85k7/eKmAUsYx6zEdhTk6vMJBjEnsD2OlTGXdVXbDcLTpiPqoU v5FLnF1NH43NCKCh63jlxxRv5D4TUHiFEKWSn6iFUnFt7VaUZOlPcgSA/mOrsxHj6tUImmYpRPZF R+tfKfLyN2GFav1vgITkj4im8HGXCSbRb77zs1SKMjzrR3naloXUDJTYKRQj3ut85ivh53b5Fbwy PgIssiDS4xg1O7TgGdoAjCon969aArrVrQP33ntvEGKi5ZbzBi4s+YWtHut2+RLlOFS8PzK+LA8z QYWT8xYHoTUR+c5hZ/rwg9wLeWfN7XDeoFbVkRiaDKf+Ktl6pTVOMH8ha0nDlqWRm/8TEyFJKrOW bMMCnR3ngZUJ0a7nLMLQg9m4IOZgyB7Jl7iuF2VNwrO9AU1fHiXVCbEJrNDgBgUb/GjzDIxMbetK RWoExjh/UTlZd6jtEOH1dA8JhxQ/uwoGEhcqZVsElEibRCNdFdJ/88wUKbuDdEy3awo61No3Y+G8 Wtpb12KHpZv+TUFQTy63YFPYLrUPSbM+DIvP+jhoSIS96/fHpO4yuerCPN6dozvlXuMFa4QlIWS2 uXvaWCU3kgzR9pt28F6gFUs7/XA35vZ1JBOCXT5KllC0DeiReuKyi0XFOGbdKxEgUK0FLG8NYVbd 4IgmKUYN1VsyRguOBU1WBWN6Velon1ms1AEnHn8EtFcdGs+/Z59mM/2cSDO96WQKbB2LN0XM+Egb /voMopDMRgqPtJzWeqIUDIwv8vmzUC233ZJLq5FdQ8kzHKtL1CpwaYE43nc9A9Y0gU0Bti/Hhhj0 Wy3o74JiXxZdE9HbQZJ8DefvfLVn2wxv9d01JwzNLlJ9NNOgJOx0PNThm4fVJUJ/1JsEU1BwKSYT dPPUAUpvA78avZl9h713NlAuo+3aj1hfomu5S8ZoprRs1aaxteCHXlCeDb03T0C7mU7vOiVyOLeB QxX//g0V9mkcfQTzFEgU1iG0Xn3Wyv2UwWroBX1po22ihBDDG4d+S7ylHPPnpbFMEpTDMo5IgIjZ KLlX01qIV9K839qX5LQkUirH3dYx4M1Qe5Gd0d9s9vS9XvaK9Aumlsy8Ow0rsKgxV9S+ZhJxwenc kDIb3+Q+0nUDRzCMCvsI5tUmhY/VY3LJpZ1RTsifOPUsK0lbPY72W73YGP2yl1sMwW7zwZ/t8YJz nVrc7EMtwT0ukvYct+oK9WJ3lIffJwOd4e35PIViVk72JsdqAxx97Ow9e6XrETKhh+mYNB2u5sKV Bgfj4Ojr0r8z4xVyOLLMi2TV+3CC5cHQmlQfleCEXMHSMiPap4/IS0Z0MWKa0K6lvyJbE2DzS2Mm YM1u8xRx8yFSuNms79CARqyqFGw7dXAQiRASy57OlsTAKyv2PsJrH2CsqpSgl8PSIzCgK/wqRcL3 CZUfN4Z1CO8ZKmjCegWhG192+dtelZbMzP+MwehOwhmkQviltbm2jMaInI1u9zcHgDtENS1r9K/5 xR0itt5YjMRFrKib1PYxUajO4CSoTzBBZQ8CjuNKmmeiyBlROkreP4RBmhFim7qI/k9NMfBiS+4m WPD0tBjpzFs38FXHy4ibvYgBwTIvOs9Xe10MxWNYmTJJwAg+dhD7ZI0G3pjYMWPy7U4JVXlR7xHk cGMlHkMive5hxGDKblsAm7+I+wdtllHx/LEALc+gnLyfhvK0yQlQyN2Ut2JWNYOWmI7bnboMp+dS 0EngbSi8yfiVVSzt7krCTyL6VInJcCV2RS2T5dI4BgiHLAlxvPEvX5oPmWE72QrzgVTUfmiiyrFr 1DgvhMMSzC+R7J6LRj/G2qVWieCvqxB+6S4MNloCtIMN5OCUy743U0LT/0YB4Zjqsi2lpvgeIolg zroDLqP1U3gtiA8GRB4eZNk12cFOLW9CT4be19GbTFjKrpMw5qb0DYbGl/0y1g9dbonAfDg8bbz2 bEqz8sBbKdKuVJ8XJZpFJ/Ix29UIJh8QhBWi0EQJVWJRYXj6v1Z6UWUafYlL9C/e6Ox3zWxzSNVy V/4SWBHg+KE51EcJ1rmXWlJslGIu8UetN5+6E+uoqVfi74m8hQU9RX4Dw2vHYIr9hu0aJ1I6x/5C nlfLiJ5mcsiHMOiVn2SPSVe3XWwgk8VCGuzBiSHl0Cku6+PcrEluBlT7aunjC/M7VjMmZlhVH/NC Ios5Pfc3N274f5nRhjJHJYAuzAPn/1SEzl0a4n8dmSJrRYJZaGeGxX/lfQHUgTxfbJINfHWbpWRT jO4IpP1rsqKXN7s/Z2IfL+zbCZlN2Pc4B4k6eRfOdqNmAJJF4UXMIaazRHz6XxATQaDMwAxtvlvP Mj6tot5O0FNnQ5GDtYANqGIVUq+cY9iB4TIYl6hTWiJZ3iy47Oa4HqnZY+5zVeOoJwTZJe+/ZYzI Wr4n/5ZoE3KyI9tR9tGmZi9ujeaMTv8++h3JhfBLgeFJqP6UkPdPLUnKw+R3gTxMoaXB43EMJIVN XvL5bzbS+k5x/JqgoViBtZEBbuJ/sI5/wJeRj6k2D+IFjhx9e1MXG8MZYw7NVljXfSL/AxJz3hlU hW8N33hmlnQsSr5uDTuqgZCvn2vJ4K8MPj0CJn3yBi0/mypZVxImjaD+NrS83LMsZEonxaAZk2ep EQkTEGLMlGv5KBoIkm9Ko3rNDF3SAdLgpgjJmMU/55IRVg4kMAk2AB66h15c12v57Ztq91E9GEBO 8/enqrxPKoRSS8RKLWnutiUazzDqA8t2BGOnUyNMhIR9SSOb4+vySQCFsiO3y5iTSb6cjysSqx6X 7Ig0U9CdLyphRsl6/2xNziHp7On61QCTSPv3/cK/+3X2XR4QEkEp9WyQXzoJj8Sxs+vm+JIbdwZ/ 6jfUqmou2pul2h1MDxdGgwmRuZsfv4yioDCWNgwMFlwO88bVJIuM83o1/5StCkBin/u0xlRV3vBA rlS2eog4fWQHr3YbTiZ6RYjHaoFtjL2JEMcbk/0VGv4yTAlwhwPUCc96jMJz/l9yroCjnWfmfscn zVj9chT9zeeglClnB3SL3RdhxEJKj/HFhEnizuRwV11XlGX6XGXH6ejpKw0h/vy3Ni9NJqziRIka O+u+5FO0iaFRLm/g7yyBJH73LrUUIt/xKkM7v4hPbXCbusPMgmtQo0Vaboe/THXmMeMllTuU6blX mHQjV8iyiQjZbtHBqQMCakRrBcmSuLBPpepaIrKDtV1WHj/I7WfSxKU4U8EqprkHf5171rSsajj4 ZbsOjUSbekVpCgBrCZoUcT/Xf9DvQcDc4amiVFDedOuUnloORnxIili+nguxC+t9op6iz2tQZO9Y LrmXUEKvgBoNJP8fcK2+NeHbuQEW8FBUJXZMIJqlFg4vxhiurtlLDhwoagy+G1TAgr5Nm4002n6z jOvIcL8V1ZGINeDhFtGj+qi8y7L39o6i9kl6A/Qx8AkhU7ftvoXyAxsbs33yV3DsTzEuu24/mpXV lo50NTXWTLGswflNtZXuXsJMgR/A41r8j6ilCclWLmxTWWeHvqbyGzMd7H1V8XKZxOzMnnI5XKVj Vfna5FrJsaiEDaqi9Ej9a8nM8LoX20D4vfyLX8A5m/KbRhj9SMXnPoE1+VzGihSK2E4YLrw7Nv36 ox5DZ/kgFdJ7jgFuAcXHxYT21NW3BVTlJkLw8ONLb1MM6hYCO2Lz/mjHecnlcZPe6cSG+nFyu7kh Emecn4TjGuGONL+HumXAQREoiCXn7k1N4j918y14ZrQiM7XIgrHCwPvZJLUknbB19CfatKzd/Km4 JQ5GpyGnFbfNSR155lg/rRFA1JMF/J1hZZkORSfhnCPwCGzYP7iYRWv+j4TYsyofa1Jl5lfQEeWn wnqjmhNC7ZLdCcuaaHeEBu3BSkzkuxEoDG6amJOdkjlyU0IQ/NI6az2xqBVEp9jRz3bksvu4EtW1 VLyZsd6MBAUj46VayyBa3MpoeTwYXuP78X4Z+/2bw1kUmKWn9bXKz0IhcFG3wg6ndeX676A/5UkZ G6rs8tZOdiGjzyE2bJTEnlykpUUvP+HUz6x+Jcom5P4o0gtjjKaWoBWjAqx2jO3HhrptFDt4GXcZ cIw8e0uH1LswQaAfFgRRYtEn50gJANF1MvGTZolDEQqNFYjmKVw9YfcgsMzqMCCtCsIywHK4Hfh0 XhMMVlTEg+eKz6yw0Ce5NDRYhjEAjazj4F48TIc+gOX7RhXySDSPpe+1K+dWU5C7HFSHvhcBoOMw Z9bM+QrX9z6YVtH3MIqGA3AVVfXftXaKojBr1oInV1wTWHL+Xz8xXokGNc7MtcBFrUi6vcmDtPM0 8Q6FL28lr0XWud5hIPYHBFTBNCA9zbLqDjXjRAKLk2nQrV6IAxcF4CC7Xj7NbwXuRqHMNUGcl3+V 08reDcRgHAFKuv+OdIoesbhmLaHefgsTy1fjRFXXCTCy6uh7+EW3Ypf1JxOPZ37NJR4veRxqLEg9 YnpEdWhhuADB79O/5HxSp9fRF0X7SsvfYv/jDxjQypOaFkr9yibmWrgsaW8nczpYuyYrClQdl+4P 1oDPEyS2N8kcW99YWo/Z34OZrQ/f6PT6M5OrOVmobo8RixgxZ/Ebw3Uo15DPi+dfc+2TcGk6CPgD iihvYHr4AhDYTtvLE/BDt9EzBATt5nWxXH7ArM4DA3GekDHIN4zFItAk6dI7x/mKq0xZvYjwO4fV H3yzcu7n7GOaI8o2JG709345woOpXqut6VWoETkU+yGvZlLaM/JyBiy+dykOyLHw1fRq+WFDt3Rs BclVcZA051/wUXx7JpMbrovDQiT79ZSsRiNk86UBuuwo9iRUrP4xq60X6fMPAsqTv1Qeq/l84XRH SnE5dk7PqfAB/icVIMwSnqpWkpGy4bOcPVjo8J0txu3XsfcXwDu9U4XKxmn70NyQftw1Jd1CZeQV ISV/vqYMlqKCL7jnIXfJD6ezEW6MNN4zZTMRkb0BoAmOqvL1uQupsb3s+hlhrLQQodRctuTkWRiW RkY4fE+qCKH1ZOuJCObpXZdjL6pHMLmajSzcxTK/Pz0TEn9qlJLOPqYgTb8j3xmjLknW9C0TpGyj 8QiszMpWit2grKlKAPOEbjaGQOsn/A7YovhchxQxJhe1+maeI9M8ZnP8k026D5tw5j3gy5AT41aC XLgIiPjBzKERihlGwqUW0OXcmaxIVXL9Bha/0PBEZHoewQcSIiCquepM/lwb0avy5cboyiv14pT5 xsQ96m+o7/G2ib5U1r2OZFd4+c/8IFJmyknJi7HHtGyRniwVtaREse84LNLqjVpIFaMv+pbcDGLy X+3wwDaA4ViCkuMOTyNqjKzfdsEtjdHiaKYEfRKFbs8oMVkWp2dBB9DV+KQLhLse2pwf9xMWQAom LYTqkrAgHp/EcszDjyI166srp9TXY7gKOe6YJI62kdD70Rn2ZOFu8w/n+D6VbeiGqoVUDzQB4xgM Iyrnzx3FOJsAyPoZPDkc+siAOhrZIPEfNnhVWNTYWpVFgMaLU42YCzmEhJJKERJnGh2LB0OQcFaM T5Kjvl+EfjmZ2aj2PzlycKcJCg81Ib+ax3ugE+TyY7qUh+dH2sOi3J2kRg100PtU+YmaQvkz3VcT 1aytk4ibL1k15DUomh8rSHw5IxH35W1MExHrfkzP1FkNgMpe1X/OTs4BQM76okb2Z3Ul2KKN+DFv InVopRP5+0Iqc+kZ0Bp9Jk+XwyOyuEpw1vGwcK4uawdL5eLd+dQszmfJBsypAz32XZxaAZxqlnID sHWkclEwx6IbOruJt90BwLaI7sfClWwQnKbOCjSh0Wde6nCmRFY7COuCYpKhAm3UCdJ6UdhAnyxS PYmfl+4b95WxxJpFa9N53IX+WBUXCkqGyW/NmoGK/mymiAEVawzRp7URD7ozeCem59/nFtTlifrD PoHjJFy9fdABsdf/IkReJvjTIH6tcSRE7PXZ6qayEq4iJjQGzAl0/UEBmOlxv1QGjhJWekHI1+VV 9tPryz+A1+2NRjWVkaI6kbajbkUtPzU32fGl9FRiSHlfuDIdlKJ6srxqAgOLXc508ZAT2pdMn34D DVfyRsPTg+RXXxe1uuCB7q9V3wdMbLKmaKvq77kjyLpw1uSkSrAjLEcVDFsOyw/LtsUTCHp6zhQD vBz3+X7xEBetp834/JUKo9pWfdExjp+kCSMw2sztyVV8duh5MQqDPE0iurcw9pWPrFJV/l8KyEgS OUBXv8HhquAmvWZ/jd3Q8/moH4S6XSbDKAiyXKNsFPLq8EeM7zD8n3hWUJnL6kTtc03Vug7UF0hr 8grMDrTgBCH8jX/F3ihpWIObNm9DTPjIqIV0YrUvWQH7yV4r01hjBMpR+EiqS5MN67TyKJB42JV+ 54F6FbIwCFsz4792BDV1Tz5WFMMuSIvV5Z66ZICyyqRYKJ+6dL18ussagH3NxfGJBhQhq2p2ZK75 pbzgwJQK0itaZRw6XvlZNPH4psII1LMLXtMDXQWpJIavJgW/6vzVGUrtNJIefysm4UK5p6THFhH8 c+rkPHueMv+68gs/l9vy+4Hn4n5LHPehVcQsbvgSK0yYaCwHaZY0mmwXr2LdelrTfBtZXiIFZGUM vGygPkp0uPFjwM/iHSUymONtuHqRLaNMJ+8rGDYTfaL5pBqnONDBvNqxayeXRbIAyBkHyIuxaW2X o1JzVh/SFBBwFdPnE3vOO1bpFsmGDpM6OspcvXoXjTizmGVrSOYOE7z/70JK9uteX7vc30UMRIzd uVwGi5KoaV+k2Hn1U8N71TT3O++Sxjm7EriQr9NyKfPa1e/y1Nv7bwy5LWQtD9wZ5ZqQuTVPWGx5 d7alpmQLulKECVe7yjB7LkypCCEu8n5UisX1sgigk4z+Dl9mAH2TpY4SFhDdrLLaT1Cvbnh5ljCM PQDgmBnk/j7HuvP4U9UVnDhUwAr/hpfzAGGcmsPAhgnC9UAuN8An0gmzoj3VoSpPwc4gzjARhdPc WZBuyMOnxw7VX9GQu293hGbt8TCJaPTOKVpEBz+06Wy/UfCDrpOZgrvcddzinQTtQgl5yMJRPtvF VfqECqtsEcDUIOFDroOD28csqcjPf236M178doyBeVJ2Y/ccRYvcZhGT1nTrtEyjP1chKhD4c4gp zHD59N7LbVy8sPqfUzd4C1WSL44Uhm4deEUe6BYESlS6iOyiS3eDFLn+azOiL/x3GeIJWgiwT3fF ylKQmusoI2wSysIlQoutmU8jLgWbvkFAvSlBc8ef/7R2J20ED8y1kmwRKDyufwchLYZZH4yexHpp He3/G8JuQx4atz1dPab9tuh/cQVHHwrr6kxHnLNgVZPPrcUOnm0klH3TLUgi0FTEF+g5XbA9jH2K zZlfDvUUhE9Tvrm5zNs5kIIfrqBpRURmmrGx2jUwTQlccEWloDIJwH7bnVVS6pBz4lhWuY79sXKx V4T8zjUBmv53T5DNkLJqSMFxRROV4dY9xxMc29xgydnym9yQOJyt64xS/o4xTMOid50YRyTLG0hI QwY6kITat4soN/VEekhcqzXFBy8ELnaMbO0JONl3BEiLaeGx1mXx0WEGdKMcUcIz3w1Eff6hFTde fcgol9gEb/dvtd9HpaC1H+rneP/+CFCPwXeLxvb14x5uRzLQwMee9oF/vnroUVl8dtRHw2QwQeWU Bp/wydAUy6B+qGT8oVO1c5M7w2yuYP54izsUE6RrDL4jAjHWyon/YSNHoaTEZf7RLYHvCI8E1SNX yZF7noL+8RZMjceLOk+Gh06fHXlN9ztDhavUyy03lLQkJK7QXKfeKBYBu0Nv6gbjg6MiQtjOeinN GCVpWSyR68DRuGzfwQeXZeg8p30f3yOYoRcV4ol+N90WCmXWRuchtaWhwbB5gEyT4yPRIJGwivM8 dQ/UiOrwuwca0wsuWtvkrWulEQeAMwdr9L/N66OIoeoQ6k6TYgDsbJsa2BKL5ikc+JUdmFuGk0Sj zOFS0V7gdsdD1JFQJqT+gkdEDz1b7l1OUu0u6ppQWIYbS+PrWRW0JRxj9qRbB4SMp76oU357GRSB if2moOGuXan9Ij9H9NGjrrCr3ul+jAdnMPQ+N59GZ2VQbH9+MFxZZCuq/BcLqvlzmQT8FexO64YL EimlOqy57G5lYoKtZnAfN5t2uiMuiIfD3wBQ3FMMwZDrBrLITuaty6GVeGvY4JigUtZ9um3fdOWQ k0xMhlGGzCbjRfzXsQyux2au4tGesqnT77mqBcJAA4aTjGR7maNmlmYeGQOCsoipF2QI/vmIEjQZ KLn3uGiedj7mVTRADY1zFQ5ruipyu+4LH0be1SO4593vI68oCFLnKKWQ9+JHPowuzGoHJUjGI6dY JhOxpiUrHQBIeYhzsakMq+pSYZ/AgfUW7EYTWBBZbeo9eE3W7vik0lHDhJ8Oo/ZbcQmWJ248V7oz ROfnvFa9OPOVd0YC+w8Dxt3YFgzxXaIrZGXk7W8CbGRaFWNYgFwR2ylOjMDmGdjbamnso0Vb8h+U 8UbSCqovZ+yFXKJQMnf/6Cm/v/Cwv4bW7DiUfE50prBtdmIIzf/vSev/6cW7qSAuIm2gl+zcjCn/ oUFWIyqjWyKUfOrB1lOYVn1zYVCzDknXU5S1CKXpcMhjPorKfsX/e+cYDlhVN65/wx6peYN4/HYJ kbEbLmY8PaOYQr67sPqWB53hWokQ8kKqB3N7Qr/B7Zd592ZvIh62Bc78un8jL+EbPfp/+7t7MzCl tgNIDQFMc57dfFsSlt9cpZYoeoeGJ7iprEYwCfeaQ64JMATR1YZPg7cGTp6sIGVypSgKV0NZTjrM r3/cyBfoXt9mpNuziTH5U/Dx5o6Ay/0Otc50Kc5TR4BEN7vhPYTaG8hmAllHzvnOsRPnz9h+TDNz hlhmvhKtkNk3cgvJc0dQ8KGJe9qlatkQQaWyNLdbVjV3O7+jFIiJOLDjkEgK7eGnHYEhSuGxrRfC yw5zEVhPfq4tFGBqa1ZYTxM0cUoFsxA1Ck/+duDKLD4HAcYJZ0vD3wIQsSRk+I7LvPDJ5Rr4pKnK Ud0zHk+Vkv/5XYPwrKes63C4OIyRPPqc/GyoomFxtk2d6X1SJ6rlGWWqVlqHaY89WsQzR1HfFqev VMDKRYBSrnM0nWywt05goVjK0OTflSnxzmWkLhj9wQCQVNyTBL0AMHXd+yQBWl+dhGYT2JEcGnxY LeB/rpuGK4LEjhy4aPvzWPx0Mj0RNJ33CPV+YgALiQcT87Qgspl2s0GFWB+F6OwErGu3SAbv94s1 nOgWAgxwizKBQhL2gynuxTaRA1CwTYZBvejWSymxkO95Rhco/Afm9RPF7FEMNJ83LdiKC6eOwcdD n5Q+TIjYPCBkYw0EenWjQbhlXfwybZo/GHfjTgyqd6wRlGRv0iDtffqTQyJZYDy6YrFjOrI8jwzT N2QNQxNn17uIKNlmEboYQkWu6xQulp0d9SydE1nTW8dkBFM4zZZNHPaKaV04OHHhdV8lN32idKoD M/VzE84c5PZsrUrD31F72Mn9lJ3Uq4OCC33e61b0IITLcVzJZ/onc//nggyxpbYxfmax50rsNCj7 4vKhh2BgfAJ5yW9dpOl8WbogLlDeT2Rwq4xMtR8bI9gyUt74nnrXuO9nISI0lgKbM9H/0z5D+Y4M WoeQGvTnCL8mCj5OYYVoIHQtzNA5C+a6Q7x9RrLIFtLcjW+gh3jtY1yVZ1SzZhlbEjhAzGg3A5IS 3JetrCjPoSFTR4apKMqh79dsaB1ME2POt7FQeX1Wun00gHN9yh25WwGGaYRYVnJDxqly62TLEnod x+hkkI1V1utYDOlOBM/gbLjzCF411RIGwZJPApxTKheSnl3SApuzWgAytpSE2Lrm3F6u7ZgPvX4R T7U+riabgbv64FxDBzHVNybKvV+B5+WA46ZGxM8xk1mvYRYaGMHIEjTN2hYC8YdMwZkPlQRJtvBj vIiynm6LEFbE7GKN3cH1m2S9q1u0zNWDIKIal+NupG3bdvVjUsPEZPTrN1/jX90NGTdrvfIOm7BG MG1uh46YPr+VFCc4WOW7AR6Wi7bL4vTeNnLr+Vt4n1wEiMk1d58Tg0KvUt0xNEIWFM3C7Ldh5wfK YUGlefk0rVcJClcbBw79qrlI4GkASd/OpKj5xp3x/fNlbBDFO5VzUVlGQuuHTT/IM3bT1H4cdbjP REljmEnludPGJIm8ThzS9OpknWJOy8Ul5SELhieCkRh8rNkPb8NSYwR1FaPSQ2rjclRw6MvG/Nao E319tFsckPiytKTg/bqTGLWNF9ahOv/dZ30i1OlqDljLwYT64PazKFpjrf4KFswRuofeeENEaQpZ EUMEnZyMjSmTmmmchAZify5CymE4pg/5on8jvFcjqOjgB2EmT5jenaO6ueXIX/LiJgLB41cPbLFf c/sD0muH1t7+IsT36jdQkwLGqtudGB8pvnYKo96hgr4HYZYUfYOAxSVD6gSBYOwrfoQKKw9vdahn raC8pc2MMyAVDwy/T26C/H3hOXw5GCcgszTz7L1JnWhdp773S6aKBe3tVqF2Aw+RCVXILW5Fil83 YwbDpXCOJ2x18kfyQHJqYTZLw6ECYzTA6haqIh6GHLLScEXP/AqU5Tbg80GlpGGwkU+937sSqs48 kuJw7/iyFkIiT8jXbgqyVV/E7qDGg71+GwiA20TFZ1fdk1jmyd0g/9Pk/WuZpIUG3gK7c91yIfWQ MP/6iCo9JYVHfY0GnDj+ArzGARvvttYVpJ4rDZPthjB1R+wuIly+Dhd3RGZMzbhnsqFu62IoG3gj /l9aC433p3mdT65SESj4PnbnFKnKMR1PVgoQyI+YoUxvR6XAY6XiWeJ4X3rS+A06JGPkSIGnviNX +rkac4iP7LDJWBBEwSEqsc2zoiHJjwp2h4B25mDD2geawhAWwLqVZztKYnD1sVTFMfgNBkN9UoqL NtXw4hdHB5mxrkBSQp43gxYiZqWTHH9Rbyd0OAVygunjwbt+wOKLAI7ydR3HSujiisiYBfgiwgGW pb16GxJtf+4syb6A8HRT6M3W1re4mvuKVmiFFcpX6KAzZcAnK1bHN6vrc/uqmhMPASRYd70S4OqX SmbqB3BwRQCd8rPhIkcc3bDpCSjWq0BYqIp3fwmDZVqPCoDr0m/Zxox6LIaqF1Y6NPc9CpzX+9Ya 7GgNrria7IkqTJy0xrRHjIx+GgZ3w5Bu07Yiuowm0dC1B5BdhsoSVxtFhfN/DQeCaqAcpw+JE/GA yUwhAxplXgboz9+ksUntdnUW1bUT45Aiwn5n5GwxlLMPxg9t06/75l84Fhb2Iv0JVyPTyGHCok+b wUek0kckHKZ8IyMckY8zxfXPOnQZMOCmT6X6BKEaOBcUEscqmKOIFSglkG1sDi3XwwP7rES1sCkr lkL5AcvP19M2RbW2Axk5tTObE2cIvz+rdN6YDiKBZc29FTm+PpOHBRW5fVQRI/Ydko4LUCqki4x8 iVFFxCtnRaJyokrOEABe8Av2LyduWQFU3fIPCww6nR5TTL1iWh3Byp/CKXDGcX7RUPecmo7u0x4G JwVdKG6dIYZyOuNwVlB/8FI9uj40J/MWO1GVTQUUGZlFQABFhOxOdOmuKSP5uMoDKTLZfQGNDkyG kcUyKGd+B4ujLHJWEBfoHg6P2Rx6jKVq4yCHd3mku+P1fVGdzXV2t2Gpp7+BESVuScHLqFSaBygD SvRIo/wIBVYLYn8RidZMDvKmfzMAe95m82HlUMzBJKR+/fEzyg9Tws+nyy4do0cv4RZyUUxjuofZ kBn8+axZ2bH+kBVILpnpZu1Ix1imYnmObvROgAVb3dNRIQqsjvFGsdGMaHFW8oJIeGeng+iKLhL2 eM1XYXE/vVYRWokWx5OOh5snF3qpgXUXNfy3k5feXDOnHBt7hxqN0spJRPew+Cc43ThGuSmq6BAR FRtNIEkFejPW8T6+GIEsttWjrzrAPkze67Oa2Sra/h+ltOBUGjjv527Bd2pWZIPbhnysEs0DqKfd ybI0yvrSopgH5fMnXDfrqOVrk6lr9gJKMLFdZC7MeM2V7AGCzd/U6nXDWX+I0i1xag4+hSnw+0Og LAswPBzpGQdFn0bLsCucxvF10EvwqoeVLBn1q4w1KcQwIC7WArkmGYBpwS8ONF0ieGyjzc+CMrUX LU/NCqjNFkSvjnOt2pSGnRJg0Q7x6ItUn5RwanDUa9Wrbnyn74U1Q3pZ/2sxQe/VrCkgxcbDv5Hl 8M0j8QtteAUnn2uJyRv49kfkS/jEoUB1AoA/yzELXaV3Ewp698wkGM0cIWll2ihRkmY674UMqBn2 xC/L0WpdS2bw221z+P056WZfSnVV/6b6tTXViRErxHN+RGFNG5RxChVL1MP5NtfMiRtbCWHp6B7n ueP7G32gUaP1WtqoGAwr7F/zZl1x/DH4SeeItYfYH2Pu5kFsYJ/FfOFvWAqxT0iqp4cTnYe69+AF JUs7VdBTAZiEKvgWqDPj2W5Vy7fayHA9plNja3rg5XlZn59O8+ymQYnPzszIlz8zPx2tpnEZSOyy hEhSc2RANTwc+r5d2r9LCSaHEJ1HSe6V2jpH3qIF/BhvPceZd2mgpOlmT4vh1AIxnMtzKOVFhjyJ 0L1wFsK/Vya5DUH1UPyKjNvi2QZ7VZea8EssZvZ8Fy9kl5FMjCCTvR9jfcMQdrDww/sNmvUnbErK CfmpeuXCGDtdU/wSrvUkYGY8XcesqNgdnhOCQjLTDguQ/wC+V4uNpNd6bYoItL4+u4wzU8gdoIyF x6v476UMqHeAogKLoTimcnVxMlb/dUSZxWP4gJIweL/sEBfLOb/+EwwxYMvXpDV1tbf/SeFLX2T8 jiEHTvJ+NMG7e7ScdYBHhQHz9bRrEMunttzofewe1idpNOVj7GbYsj06aZGiCQQtB6bDH4Eh7rC6 4n6dGuuNSqnPlJV+lqtzL5kibbpgiRsEhKiLThRNMbFWm3IBM4XNv0+tqLvUohMxDzwEMsEJBRBz hGZazvB4dOpEXlfF3vaURutLatdY+A5nIa0ud7gG/l5Ohn/tz5oCmCMC7u+P+0wHBbS5j6RiaIcs hvnD7iTJ+hPHLUR+isZJV8iplI6H838reKLS64fm3me7sIH8/GFLpy1HbaIyGtdGEG5uNTZcni3/ ae3iC5rv/X3J4qtlYMe3wPUb1Ruzqp4saoif8GPy+/v4/NPKUbleHfZdoO0omFBZJPjJglutjcUN dbnoqgY3sjS/K79OMzFQQ3mV61fxe7nDKsmjx4SS2zEsd7jfEIFV7zGsd3dPOGYX+TpmkP0G+N87 XKwhJfDCTbXg9Oz+doxAV+24uh0N/EQX59e5vsExY3Vv7jVtDaZi31vHj08oVq5Ja2MQ0LvlipIp OwmeT6vJAP6aV+mas3V7GRnmKpTKS9wjrfGTmQuU8Onle2a4f2y8WCtEVlAHKCo9EQt0yF5UaVFQ rVpB039X6cVN8c/crmAEs5R1ERjIpLVk3AuQNKHZdZ4/vwdxU3onub4E87R/ZC+aWjtq8U8wSp5X CJBWX2u85ZurAVd04K58YT8V8iCyLhKs8FaeR1JeFp8ZTqzoQUSwvJvrsWqxkNbNv98TZGjy7B8T HDshJh2NsTyzRwYcxq4tv7Oysll4ciE0CEYCvOC2TIHzobQsGhd5I8WL9z+HxQb8KscfqkTvnf+g 7AA1KnG3FTqiOXtgJSjFTqvrfuKmimhDCR56sbgqTgi6XGE8r3xdMapAC3aOAxHrR4dkcMFNFy5p EvibjjgdEf+SyT9zCxBhzUsYsiIIOqmNIVmIONGgElWbB4a60D1HkAYXHZtIYNDa0Pnp4NQbQoHk KM6+Way5JSAXucCNZBzc+UJqzlyiiC6W3uexGyh0C5+UGFfRGXbaBa5vZwBMOsEg6pjosiKgeBMw FMHcPIBjnf3x5IcN+ZYqICFM1PveElq09Vr+Q45WK7IvHfnqdvXA6dt6cl33p2Hx4z4na6YKdZs4 JzqKZFmp6eZgAobW4MlRNlIPNwk0WsmGExJRqqE6BlUVT/qTDoDm1mWQj82fSHI+r1ugaHUSuo95 f2kybtsRYL4ZaqMdHAwndblIEhAX7qXxmKDFcW7/lz5HuIKC5p56luCQwPfsbWX6XqbpM9RktZ4+ hzVt7/iyJC8Nn1Q7fQiII9AyAy0nOBWsVgL6MdrIkLXnonoqTh14NmShfxiQ+mSPOPu2bx18kGov V9kH9IIb+yyESFP3ODloHlJTto/YM9RCOdlRM3y9gxMom6vM+Rnt/SvvaKG6IijZ/1kmd1it5eQZ pzObwV1u9WhgEZEjlYDO/no6o1fN0Ot9v9QjOrSaqY9uxtEgYDqgApFLOR42VWjSVDQ/ulH2p5Ze WCuZlmDMmiZmk/tCirrIzm1IxuQ2/oV+KlVIva2JkWfFywIHYHd1FiVcZQbhl27s8LytQrgWKiHS CxoIcfaeOvq+++GGgqHA3t99g/EHsLRcMRZ64VD9rxa5ARQG7Gx/6aqj4grGZU6Yxszht0aNVXfB 5ul8Pkr0GRaXyC4GhTnvxwibhtISboLVky01wiMZAN7UYqbirpXlDMiM83QZWI9HeFMUV9DnaJ/S 7y5m4h05Y4/yTefGWw62aF5dWEwd+WUr2HfT/g0aurj8RRM53qG5il2uKUmtDx9L9utULsTkucKU cuFqpb04fB1UKcX0CBZFdaYA46qRczb6Jh4Lsl5qlcipNpgIdflE2HvI7Wmmj88UvamENWs89Jga LOUsbXpuUyurbDHuz9qmhXraUl6OZOWUTBL8D2909640po7AAIxLWI00F7P/0rbmfipl0phwrE0o o9x60qqj1oAakI0jDlPSPPkPMMpqVYjoohvQli9Fl6+5Vc8GB/940IKU5Gs8NzLcaiTo6CZ5/d3e r1S4k5KQriAJWGKsAcGGIntHpC56RwnsmjIKgs1YNImqOZyYFkDvRhw1mpxjLlKIk6O/3syI2cOX M6nNJod3IxslZ55oPybLnR6tgIDlWHF0diLJWA7H6XU5qpT4nTWrghiXCKXjwvc+Mljadq6DYIl7 FLzffBDeKnc/ZjWdEcSX18lbbL1ii2R6r5wCFL43ZaBheCx4QBgLzwqYfj+vdsUGoeFnv3OHUJne UioM3e9zNbp/A7oEdpq38ZdCuaWEyb4SZrTbBX/vn14MnW8ln43Mn9+AF8b+o0/3Yuon1xpkNA4N 8m/c5Y6bzRIxM0xUVhET6A0Y18OxhZblCxPXHqoGp2bjCOOgaYOYbGF/mBmCDmxNKy1KTauCF++0 uxs3zNBHqHxXk+Von8zK1cNQDBny1WD9Sb0A0rA1quoVQAo06GXOmseqUQE51oJ6XI/QjgN7fY0h wkObfmREmiWr3LIlP+5x5YHojyZcGruhzCZPcuMhsr4RETjUcxPBPbbQEiyQYZfKc64GXQJg3hXc +xFj7u/JOb/ReQZZMzO1HvS+sERkCPKUQ3bR0J/0pi9jC0UPexbXjLaPvrmbf0T37k0lFPqnTnC/ PMVAGiYwXTiU4A5a2z/2QUXOt+JulfR0OFCmVkU1oQIaKr7mvp3Nz1ivk0YLzw9iKp1qNRYHrypg nh8eXXqoBTFdqtfspX2244Gtyl/2RG8vdhlRM+foUtMl/clo0S9swA5Ou4jR5xeInUldW9stsSpJ kc+6IvMQ/ggk4vibTmx2TjeYaW/mNJS03pHqxA8lE5owPLuhBD/uIE+O24RBfi4QFWMKzymoeg8U seCJRiqbkJ/wVxOEUguJOCIYII56GabX4tARv0FOef90Y1rJTW7l1O8lzVT8woEvApg94W0eHRsS atdtheFwt+m7Bqqia5cr4A3Zy3JOJwyRzx/Tjd2pWe1pDiblZstu6QajlK7z+p9m5oBz2EXHtCJk sTZTKNuzv8Dz8i3uEBeDd0EaXOb4tdqt5DMumB9sFXRiXbImq78NkfSb4fRzfNDg9m0+KOm8slI1 AGPJrQ7TETesxk5yR/w04CHGf6PIe9a1P8C6umIK0ZgNrmpE8Q1apxLrQBzP2K4xfkFwKxw/HLQQ Xe84LduoD3efCRRrhJdTb2uQDg3S+HbdxINeKNHmAp80m7rQ87feqhzDRj5xYGfpuvDwMYiR6acS QGCxbWDX6Rem/RafSSE5jFjrK1DBOzD1EtEGov9cNUFl3qyOuUnJ7QC0HOzBzj5ugNrmWePsQgxs Whf13gUotkrlYXTZx3oUdP1ACa0odnQW8Ta3Oh2RmArGand9EiR03dgW4B7Eg0IWq+MNMYcBMRfS /i/rYOZUoyMg6pP/pZG95NTbMwS3HGf6J+7sun8BKhSiLpoCK0E5Q8H7XAG7FMOKQwZsmEhv6ORs 8M1wlCHDWdFLDb1BeLhHXEukYJJPofzaY2Cpy7q+sim5s+Xs1OC1AHk42aU1IURh7YLUdjtzY8el qq6Nyuv3BD1UfAuo7sGMmT/YggyZXFhRNXD3L/A4ysSRjIzBt6kd0NZugTwv8OX2DiuKaixWCoiQ 1EfcEG8FC1YIx8P1tBBGx8ld3LW7ad14w46N4bhXV8f04lbSLJ3OGZp47KhweXg81oyFIzL72GlX jCPlG1HYdlN4AchEBg8JKNjcw31w3xRHAklrewsvKrBXvjov5SAFxcaR1KvAxAVLNm9/7HOoroff HzvwqdDCz1Flg+PSWX4u8Y8g6l0XCP+Ph5zseNZuEyKQ2mK3UM6AHEHdpo4jy7pPxN+js5+0oh2b 1xPzh+V/DHg9AjfFV0Ig0Ew2/6aYREHJpqaG1+QxWM4z+1sS+kSdXVzxdDzSWp91+QuY1O5eoEl9 vrL5a+7NvUox/kNl1X1PJZz78/SUuKhZiSigui+HULpJMJ2FQ6+HHv7J4LXmjUd0HxnSC7hu+Kmh oIfVW/Ill01T0Lol54lFSzlZ0Kulpywpg7CbHv60dXst7XD1CYrtoTMc9Ho9G1ABAMcV3zzbMvkG /uXXZcTGfGeiS5+yVLbwJr/yFdM2wfQVaFNuZZHv1vTeFIDTe0CaqC01QjKrhKBE6Kg135d8tPsA TZq13brrGZlS1Cx75xW5hzCfKJojz0q7Lv6ExEDEKMc6lfUWbJ6goNK9hJRR3G0kVY6l5p5e6Utj oXctAHmcPabHNTBkwwLOjol0lmx9kpr6IgiejYh3DQZqrvy8v3hu7H5I4yO/xxQGQWuM6DZODNGO 6u+qBoVeVpjLL7lS7bjf83pKD8djGFjEXeD1L6+6LpRWESvtZmGdpJKTFweLvKfMp6Z2vNNpGh7g 6Lv1SQLzPYwE4fa7sMPMymZQXKlvQGlL6YVcnX80S+BuGiIq4E75qkW0w0PTqgCRv3BSceBOSowJ OmJ6/DZBrcmhwil2thIV+Ep9RcC0ilWYr5p1E64DRZcPsbtZIxSWz0fJHdmcp6p338MdJlGtwI9/ ZTYdfzfmivWsQ/rbPegzM92kBk8PeYTWKMM8fyYONIQYLTVeAwt7lPFX5CgzfR9luiQYAYFw0MNo zbXqnsS5Syb9xhv1RxE1X8F/3gsmBZPaKTzn1P7jTJgfe5OCj3KAFwAuCc14iS/tBbZJTI45ls4v cVEnmCdM+gXodGgIqb3lwiT5T5YAbDd+pgOXHl4trTZvkJbPdmMW7/MZPJ4jEQ4ARdBpA+mEQnTg RzbQW1PN1IgBYFqKS+G78fbd8KUNJpv+uuchrguCnHLUFQ2MGDfGUe4yJzXFwFabDoHnEKXKrdPd JfyKcXqN/3QUQa8Ma/Ie4FmUfocQxURN81A+HxAhZ7f1wD+grLPhb+g4Vro/JUOLRwyj+uUFaJDz xzzZ/oOpSZgppnMA9/cZ0AhYIalE3QaJDwEO7DCKCInrvdKuwmO49CsRgkFkBX8Gwwahm26mxlJK 7CBha91K/WXphxXP6BHLVxSZi6EfjTNRPKpfbvYWiQKYmMOFG2kHihNVsmk6DWJEFHsDw+f5r1aA XbSvXvBbULFk6pvl1Vm7S5EnV78t+0u08ilCLooOKJ3agKvF+jQmkMIODQG2DRrD0u3fXD7LNeOm DbH0qEaQiPgZ/PPVOkXqs/Yq27om32mE7grftC5l2knZJuku0ZF65BCVEZq8geOzpR9CCVdOq3Tr BxXV3RBmdAqO7c/ifhFrcxs7Gqp+p1Lvj7mhCGLuftyMmEe2wzw36ZEqrUu7CBhE3LAZzuLUF/1+ QS3qlTSFbko4AJOvzwtoi6oB/TrI7xzNsbkMZvMMkxAuBBabbr3ug3lMaxyNuWyi/92/vesoEmZH bHjCqqysExRpe5NCHWrSMst6VHmh3ZMXm2FsFrx+H3fFJ31rhvKyyeaGSv0HPZmhIMAXL3tTs8o1 fT8zsiQP9iKtIbUSvvosomnOqW+XOzDhThSrU/VN47Ku/0uxenpPFOuPi4yB8jpQ1AdMT30WE4hZ IoLMtV9IxO9gotjp4MUfLbvuXej7XclW6ys9M7wmI18+ZXo4ofHeebCf4ZgAd6SB7zeKOrD3A9Ty g+vqN5p3yAJ/HUZEHgippE69stzf5H0QdCNRPl2iyTklrtXVBbIXlQ/PDh+mSq06py5VIRtUeKKG OgULZOHfO4FFxROng2S1l8vAiqPLUtZtN5dVl/B3iMFbSrbwJ2WJaF/1/58GXJc3j7Uk7a4mZtna qDXyexASSJce3u7b/v7SaZhJtDsJkQ/C/VdqARNgFX1CC1ov10/vmedfSMTeAOSqD+XOBVlcjwMA GT5FpHXOzNRZQFbpHCJTCYDRoKGstdriGHqV1QJ9gLA2XkD83lcoaVk6a1hMk1t1Sd6svL6IN/M4 gsdVRUI52+WOk4j+6twTIPgHe75c3jfnT/ZOxr+R9xuRumJgN+/9d5B4dwaCpoCXU8XsR0hJc5Hh dfR/OpOyR7von2qfqf5bKeQyGcThIOowLtC1lW4mnpQC8XvFrpHHr0sKs2wuX+5Z/XD656gsfofW GUNJREaJMgdbUZ9RntrinfCWy28DRuesPadQhwXyUxyyPe2gjaODaTufUjATUKcmGRqyhfULP4vp p8DLABzRcwO6QKI0FgfdqMaeMh2g1VrH9dm/LmlovwVva87kqp85rhRbR23+kgqmYGnjcfXACaRi 0L71E8h7qb/ckUHP0jVomARsl1Py80mQlfleakbqWy7fC1xZasLyGwoStbEAMOs1Y8kcA2AlMLXK 1BckuLVedxiIMnfBWsNu4KlxV5ZCEu2GNhtLXuemv6P/82ks85PKnPOIZPzKKEic++gkPEGhC6lA W/gFpS4zM1ItKibuWnJCcJ6IXTjJXP0tEtiMEFw1D/2k1AAq47Jr5IgDTBTNUXTnl1N1j7KEy0SO W5+PXny/RzlFJOzg9nnCF98dX5v+ueuQyT6B6GIOaLljBpxO9+JiLmMO2k2y5bIYU03NBqYNqh5X gSjPUVOEKVPEvUu/WJVevS8YcjKs/1QdIqkDLthb1ugoUI+fi54fbmmBkCd3vyGitEdn+n5BF1q2 WJ/I/Cbl9id/YlsA/LqmwzVQfWDwRbEPL8kYqdeh6/5Fc0YGfBkCpXIM2w/iIgcj1aljIEn2ni6x tfJ/fElRXq7+t0Oux4CzwMMn3zbbCQM0VQkGr5HTIxYNFZJhdoF7jiab64UvdXm14Fg4/tLqEcrn B4OC1vMLfMB72PnB1UmcZ1rGgPiqsmozOUuJYdHLbjPu8Xhk7xxnNi8142cwlRbypeEurYloI/6H gPMXTTRWRkURkp/8QRzwFHLMBQ8zoJQFVI59s/AEBz1kuvL68XZd9ClUw0NHqlzJp5itf0baxVI/ dBAekyCqpbVeR66iz+DBbLeIKMaJjDcUDxc0mURLtnUgvh/iWSJERp0eaiRETbrzH0gq/SBp7lOJ 3m7b9wJtAI4LcjOdmwponi86J/to95CjftO05bPPeSIYdPjdVy/55FfupjREEsulTsCcWr1b3P5G ZnkDH1UU9HDWWmClIyNxT7ttD9JYFflfHPPDxpUCzYfnijrskLMeprp847OoBOuz3ugfZxfGYkDG tF/TZwqKrIvuGT43kdghgK1905W5lJqYVHaBkn/FIvXjTIiuBSQ9n0EH3bKR9kpJT9d90c3hJ+SY M88yvkFYPUr5BJWDIARZFXp4fVkryVaNMd9t41kEqV1C3cB/od45za/vJllpSMf6ktkKIfUjcl7r ACLwdSZw1A2tyk7lguLOmvfeglvx6W9PP27skl6iG8vAto2VTF+7A+kjUyPnHvhM2JBp0HhYg3p6 j0QIVofozKs8plAjGyUeRor41UzhO017+iYbN2OdyO2OQ3C6a4L3kIWZ7NR0FwE2fMmreKj9vv/W Uhs4q9buTNvUzNY+QxMm/zo3f7ksJbN0VckFbsliy1RvSbh3aT2ZAtMDYbXgf4Wpf+FCWXIuRtvX JlrR9y5HBFA3Uqm/3RuQuMAP7Wzv5lXeXH+XwIkeqbzrtLgWuhrK1IRf+tjEXp/PL6Eu7nw92Uiz sgZiDNaRVVAc62FdH0HcbRzTgJYZ5uowl1ZvIGprWFPE0VYhSfow/nRWHK51odg2MvS+1yCnousP Fw5hmimeA+RzDACokQj3aZy1iIajl9RqC/2TvBmKG/G4Bp3n+D0eBhwGfCpx8e6J95ApVm3cz3KX woomLApgfj6KFvztv1HOoRl2jVuO0x0iGvytdzzMYIpoGvmSMKIf/iwSTdkQ3PmF09krT7CJyL8i cpn4r7sFCXCKegu7fZ6Z+frY+kGdxTCAQqwydZ/IPOr33+sBC7Ym1c+2pC4rU+U969yoG1yEmHF8 E3qZfhPtkXn4KIw7GfxDJA4uQHcOE5b53ITZUnF1y8QStCRMxNKgztc+E9DVahQFKheY2T8rgzxC mr/RN8Rv4Csi9VpTcrEyEyTkn49DcW4MlEUc8R0D5nnx30P5s7zgWvck3GFvkbaR8aAbSYDSGU8M XOli3Ik69dclrcoob6jaMYWy7hZgqhMUkn1pE8xv74FZIF1l07mU8zZbQu9xYRhKiPAmfeAazpyu 41Rk5gQPEpIpZKNNN2FYHbkrTsrTPtIQIqKw70yT4xUDiOX4S8Y503GOfp8DYDxuokww/Q8C3i1o hLBrlmCkngs+HWebLofkWKZZANDYJBFDiZV/pZnvCW/9o0DBz38WXygtmISw7loeDUSC0TjROnlf PdqdqYDJj3HCzAGJfUEbJowizl/EwF6eyKJVDrhnii7oG1ohtR4GSlmDPj3/7LPmvbhkWClZRmDc KuWxyaGskvRL/dXwhXwx2chU1arudTieV2//KIaJtaVHFgj/S/DEn/UCGbr04Vrg2pQ7jrT/x2I2 dmxR8TLPIRcGMXAP3MZJ30RK8PQV5QMrNljuPdqj0ewPj+q+sYQjr3Vzy8fWDtSdbRtjjmse0Ix9 TRafyCbY2sFdnk/NXHEcYxrpIh5ajrt2v1PAr6DUtTHmx+mbVU+vW4uIyO1LH/SQ2OjQBEeWeCi+ zC7LBJ4Dm/oNrek0Cta+r1Xa1uECrIlPa4KlM1x9mqOsJWjU000YT6qf6Q8kJMA+Pb/SYpNQHvJV VSv7yMhEACH125TQ1sQ1lEOe+lfPDuPMDnnoOOMdAgV36B+lDD+SZmR0n1VqQSj0Z7vYybNvPqYb Lenm13mX4IOVNgB/P2QzEgHgWSY5kqzHjJy6AGusXo/prvkWg5GNbtj+g4TyJ2V1aYcSBfdB49uZ nBQLsqxzaIM7fwytN6agp4LbyCOUjI6XJhcXhR7NU1hj2Xed5oTdI2nVu4SD+BgFUZmZ4w8rIsgp 0EbdEExB/gl1IdK72gl+vLfCAobw8zVX4Rup84qPjqnhlhEGCorEUmFEuwFjhRFHZZ4DzqF6bcX5 RPQY/fewR/Z4Y6ho+M2ZrNcdjVCnAkjcn5ygMuU1UaseOt0YF5BMtPgx+f5ospVYm+IQMoayRvL4 KArbhOejqdU/o6gaRBBVxhCBYrOsPPpn10tDJJmffp3Gm4KYO6XQ4VyEOzxl54pVRfA3vpiyskL8 iBmYQnC10hM83SXeP8e/wGzy/rny8/G6bErma6DZ22YJ3OINpvBha6Vqul0JP7hlFQH9OK4/CQvo 50q0vCW3upDHnVd29vTHlrdLfewjNWyyh0wSLIa2Q252sQ6WqSiZeuykzlXHbAUjCCWcIiZnRFQS RSODWAKPs6TGbBr0sNRDQsw/ce/6jkDUJsfOxYwNgWPrK9xV4/WZ/rU54WWo9+4vCJ2D5vnuCUD2 0O0sTq19YJAnOsMKW0+pV1otlPaVm2vLeqtYEKD9i1FMEDrphoQSv8hZODNKaiJiIvz+gf3Ycv2p ddCbKSxhQsjalN84SbGoBT8jdVMeuIHkVxZBlRIlelfkjLTY04wCIJkWGQs3EfG9jIzbXmvzKMSd /9P6S7aWi1hiY+igcNY9LwqG3ynN0xghotI1ubgSmC3ckoqcFifAqaTXoX7K+i0YhzGGL9baZR1x /fY5ONCisvM4CpeOa5QI81uPpa4AdVzKVL6wC/mcRkPpgvCkWj/11zQNfceAezXMKvi3T83eNmQL s/iqoL+zaYZTdopnYTb1ysFQXXb5ZDpACmHdA85l8UrYBWXZVyNXGcx4rQW8G3gif2RIB7fLqs7l x7/K1WGbLHVLIoA7ABlIzpWBv7jQHB3e1NTxKYd+cSpr1kJrv6Aj8QzdjLUI/IT6fHzx/4eWtNdI hOhJoYMwpUkFKpYPtgXy+5xBoBDgCeHW5s2kEFZIJWNW+VrkaL30H2aYRiMX1peULR2XbxCg/t88 OFtPd5NPcDjBsVW5QQjhHGOzNjw7dDRv0iorJGIc3w5Breb+zWOGnyfAdroapypdQRBI6ZQDzIZj ge6c9C8klBo4md6wiI0pUufb8QSjoMgg/OmsyD8dW1jptLs0FO3zkZapuplSokszgJVPwIwHGUWH Nh69p0r5iBmh8NG3AV+CsTXF3HkypFav4/9Mth6SrEoPFMS2hM2Klp/m3IP6dovfjLVzNx/uRZrL 9ZTADpRzKXuQnGhWiktkSH1vKW+oHuL5968O3KUO0fedqsjMKkChrfcTywSBPBKEmxQiphYd9joT kxz7YgUmfo9BKKnPcLG0/X2oYhH55i8jj9EmayaAVtblu9YNYYgQ7Ovpnvjn4wVy8Tr+p34ph4SY 3MzuNVoNEIN0ll49E1UQp982YxqJ/AtPI3cn5sLEpEo0X0k75XwCgeWN4/ONctyIGY+dbhkVoz3+ cywNA8en8oIb25FvMCUyGlDl/5/X8CyRYYYytbu/W1eNuDUfzTAxjE509+xZWMM2Vm0x8nxyyziy 20SA7MA8caUHTuB/Ny55dqdGokU7pDkFFBjepud3gyyw3Q4jjpVhtDRYLhKXgfcdvZ8UgbK1/y4h HC5daq2KXaDdsFuiJQlVzDEOLpws5Q6zwWkFDaPh02ENTTP0HpS84L1QSTTqpc5XRn9pyeGy/c17 arMUbXNPUK9M4T3ou+GwdT/0iqUGvR2FnMJxyM/lxMrgo2n9dmiIaZWA5KdEZ3K7InFsCBMtJ7mU r15pJSh926eI7g/AVVPJwS99G1sNkd8FlOej9N1wBS0I4hxLQ9r+ozPTn4SiNkmpCNCXpSoeyvUs pGb9DEw9WKdNGX5f4oDARjdL/c6dFm2bAGkwgJqAzicCirVw6uSpZ7kevx2gaNREXI0AhVFvqiLj qZFglM7mhEaUFGX2L2x2MNJBFoqMqhB0Yxk010Al6OfRFtDIuIGP3/NKDl2Xcq1vJ2UGTzTYb5Sz +aIlqtxKRHcUIwCjmP7aNgH0iTy7THTPxC2CGT4AW5NQ7kB0813QjLZm503UWg5KmV2fGBjeameO aW7TaO9QVowKs2XEoLxUYYZ5EMFZzqJJpoAWgfDh3c6KIz/XcENVTdKJBsBNalTXlqeFdcoq+iO9 yIc5AJptw2acx61R3fdEcgFumXSU4ujUA5ck9dNnnpqg/wwpCTI8K/HV8Kw86qfUcCZ2RMtb9sla YeiCqo5KXlUA29Jk4L8kbSsOI24Wc9Ap9ifK+NdOebZxFtoUkUCtzXSvyI66/rHE3HJxMhkrihE7 zARrhO0Z11oaRO2sx8KzrRq9AwozhNcEPoNI7hnoBxFZAZDzFMuB3o0hGX9M8DGHd6n8jCyV2E5k hL+vdK2ZYNWHjWW0wWLUToO1iVmbFMTHshmqKWiKo/QJH13MSGddoKwVgJuuISDDgNaxBjE74cYe PzZaExxPvdPRHim0X/hFCXKTdVewRFehV+4z0yNttmAkrelNhGQMyCbm2iakEo857fnKyzeReI/2 jC4Fz5ISvX8qOAZKASfFO2V3RteKbJn1l8Xy3O7O/pFKllycXCCrdrfYDgFG9V4+DLVNtFQvGfhk iEVGXZHv4nHifl4rsm1S9tc7kthWqCBQBYVsOlRjeCXrGVWmSUx1Afv2F06V6MzOvyWtSjbgCUs6 m5HtBgqxr9HbueDwho5bT0jQC0OUj/wzaxvxJkMOLlxx4JqnRHs6EgesM+V/CGMJ8LVufivQg7Bx ycCmM6jO9YoT8kAiVcyICTBHj3qzUdPqStORwfacru3iego/I8yRyh8gp1LJJiAqmTtVQfAePylI slWw8HCKz4Ropf2tcT8x9tIWikVsBSJmhqIl/CNO5dc68Q3BD2eBuI6JMgTiX18trlCEVPWcTuDt OtvFxnQoPzz2njMzJ6ZBLdxhb4i7aL7bnXdPF3XvJJz0FWHyyNsbPLawMiXdI7tu5Zxsetl928Us vh9z0pc/1RQASuQWcWiFlTC7nJIfiyCMVPZ8XV8MrHQbho7LtbL9MGdWoXO2LbNw3r3xmNc75PHj 2z05TvgDU9LFTCNfyFfufrRZaTFiURPi6Um29F+E3RXPWzMGa5TUqIDIDSfN8Deij2n3orI6+n7x 2jOgwPVlS/CT9TaOGASq5zNlOaAn/8zM3i8jKRCv7Og/MziVPlbnuwoZvnCOutXDCGpsug1/Jla5 VgafyYW75plQdFyhTlGL0Ot1Qxt4MucA0X0Kva/JksKOuNx97bnbU94VjWAhqg54f/gTllVhuGHp SsdBoveosrq+NIGGGJSXK2wYUXv/SdeuSZNRprMQZsYWksg8Iz+bpgVABELXDvTNuZCVJp0h1g3A 2afY9z6hknwDPkwqgyLRUO9Spbz4+HMmonicsGM7coDZxOcl5TV0CNYAFC1uAI3gOS0WNzcVSnLp wlgCSX1J+CUDiM92drgXfiNjjpMShoaj51U074taeHRywCLX75n+CBexoXoP2rSxXQ3USLUIhMAE NYBTH43kmq7VlN1gfMdZRinrEs+wCQ040POFgk4Ql7ZySGZ14iG1tc5Yln4eAZj9n0YbHrG3zfFI JYm6EqobDptRWq+DThsMWT5K+CB8uVn+HtJR8oMDP+t0uNwT+3QvWKr8yVkgPQ4dfMzSEV9kUfAK cAs2Xl/zrAKwEdmBYzImHGjvXUhaYPuaT3b8M0C4R2uuYKkHEcMR+qUeqEx7SD50SBtUQQa38yJs Rmd625m2ZoWi+LJkt80XI4oAX7K7KJAwEjiNo0+zTWYEWt9ZrICV7EN1ja20d10YECUA6CLTGYP3 94M1Xx2RjqPKQpQlvT0fg/b3Br/Ckh2c4lLpmQG93kdzGbuSOpEeHMVSQ9XlvKkCb2/7s0X1VpsK pIbKoVmq5GwwadzlQ5t5L8M7WktvP4OCHdK1zxPDqK7I304QxIFWuyPD9rgx0WFX0tUT6J4gmzDq ftdti8/jwIIdQJa5wZ0J1ecgIWHXSZnqRLawXcyilpn0ueCjCUDu81XYqqkG9NxRedj6lN2tgRxm Cfh3DSlaqCDC16FAFyQN+e372HwYbR+koVGkC4qrhsa+AumJUOX39LzZBMkUR9AhAvvrF2IEzw9y WD7twK/HMF7CM7iQRB56iOYAq4hBGQs+zJZgh5azhqodP7lXwvOgijRDJ+2brXOes6ZFYTTqSsa6 /BIVYe9FAsdxha+M6Wwfo1CLpqatzbIF1pr8lgxJKpsWIR5oiPzuF5G6gcr9YiIMQXKNWyY2eXxa jIYdhUIRsoGSo5rIcLIWmI2dZBzNZDtgsuZBqf1Eqs9tXRAhJnJFcj9rCpq25RmNjUvbQYrO1Coc WqPN1ehUJLyT90vp9IKHDVPvJwlM5H6uWB1fQySOcy0dqE0/grYMlmM8h/BVexLPOzwhlZVqcBfr QUVDE1RGe+aSbeLyhAOem9Rfq3RvUHAzxIxayNqvXa9tvlpYajyUXbaWbxsGaoXxIjIyfw4oWqWn eJDOYI1otyBfmrOHOluRX+vRkXkgXgflU8Pvg7JwfdHTa66gyE3MMdHNv+eu+idcOnN4De6Vfzfh mzI5NYvpOo+YinMhl+OMw/04pZoPF6g0ku2QPTtW+nADJIaRVCBZhegvKDLUcoWLjc5rR2vvsyna zG2/tJBQ7xkewVRUICPwBU6AI1v05lnzyaRyQ3g9ChlcTxZpGWRwzzwSMtv2LFTY4wPKbWfX8/Ir Er/lsNxxqaeRGqgYT3+MiKK860/Q6PMVXAjWAXJZ46rSLM/Szlna6PBSLG9yLVsGamMtyz87kgnb aplg3VKAk8obVCP8kHSBa1hb3FIcPpit1Jik8iSQ1Sn+s/o6CRQriQwnCwi0+kOgDzfaxP5Zs1br 4CHbRMXnnPk0s6YNTVhnzwEJEURsw2gkfhqui575vGnVk9yKtOPSTQMIV+OH2lniVGT6E5s9UWe3 ZXAFcnZlcwQJjdlsu1VSwADFtoz8JQ5iGLUZdJjwXIcqYXoB564FsWo1oN9DH2cAd7i7K9u2Ewbz cpo6UAf50Ekk0ZePSE76RT7nyff7vE2FXoMxZPvVub+l2Z5xzmbNdtwy5uLUQIkhZ15/iUU3Ixr9 bnHxLkJnJUvZNbuvN2Qp7iPlPe3zuj6lGsTPsOICmk8pYLj0P9glrF7HmMjfp6EcHlrH2zOEXXFQ VqLW9G33lqrYCjIXPH3620ZR+cl025QD1okzZsBzlyv0z5hzvO9kpMBHfbcV8u0ytXb2LLDDVla2 2NSEQRWkcPFU9TIcjKNymGxIXRault9S4Gh2uACE0BIoX+ukQZrutiy3MRMhgHm/XDEu47u8J7gj MuBFmVj1p7eeDjWyiCFFnVfaqbQAhAaPHJCV8EZKRh5F3kRnIRdVZvsYPp/kMDxx81Nb0KhyfuQQ pHOVYV/Zx64Z8zEJEVxwqGjQC8ihys8jb23wUzkOBii7c6KyJlaxSQ3mNbRHc0k6x2Dj1w/Xm5Jf 3crnNLLA0GEG2q1CKiWiVRcJl9+zAsOpM3KVyTaB35pVz4GR0FA5dy2LS/4QEKMXWsAXZlVfI7aX BL+J3fJr3fBS5xGWpuRwGJq+jfA28wz14Cmhyzvju4PUDG4KRBpBGq4/nIj+C+waqmop0LVm32M2 zVfrYindnagSfp9vM6OwSnxhepsbaorKX+Ys2w8vT1SYINjkpxb6xBDlHKs5qCaP1NMUB0BinYzd QVEIG2Io74CQxbRZC8ZjHBuSRBy0lS9od9W5U6SIsHJJfM+lRNKkt34mCDV8Yi/4yZCd/ujtWQWy v+OPDIcbifj8AZUjZbr1oQcz6810i5zfoZ2IHZGPIVHPu2hFhNXvD+lKiw+a7VRCYUOVnpaDdkij c0EfoeSzHmfFvWobXhzQkINfX3jheIIxUyxiaodhBdJE7JLRBKj1kt0aZKf8GYZfgvz+gdwpvEHZ D5rTmPS0chrhOd0fXfM/JNhCsPcSA8Eimp5aLoJKXDDHZIedLGgv5goWAZ3zhfoEVkNgL63t8B/L U6PEI2NEQTw9Ig1E0La/CtmnaOLx45rMtrzdUmM3A97cP+UZWLUnwcSwABt3RadP6vOy3+aYDEyv +TYFS+ZTt2WVn4s3TAE0lMWhlPR21b/nn2KXTF1WM7BCRMDqAmt0zfroU1tgp1QSPIqm2kfdHJOQ AjKjnv2eqXKlVh9ZZz7mLCTojpEIFiye3M+UJalADdT3zlTV4ZUrogCVI2Eu09RGxd5F+IqBXYFg GmQ5zEsqUnx/OjsvhFlPy0uQkT+WuKyF0lxOIJ5Qws2vnm4bIJQv1hShyI2XNfMpLrE2HdxluzjO OaV4lpd4VdQXrwghpjTrImdj/BUGYnL7Gon26Ulv83HsZQRZadSrOuLrNAt/ezKsfF/m95RN1WNa jEw9HhBcGcscH1f5+2zC6COVumuSeL3udUaEyqd27zUWhHb1u2fcXcv+RSDTFZA7RLpUOUV4EV9v 9VWqw1K1IGsNndZExATbQg0HS7IVuFJOYzUkN7ux8sjnIEgCf7cvB2QW350x3Ywuiw1acI4KUJmG b480i2kptmbFzSDRG34vxxQR9sl4isUyToCeuO5EH2XYxesRg+7YL2NCUR5M2e4PnZ1tdNslExR4 6VaaSsDXNJ6IV1vnRdwrx1OrWoiKjACetD363PobJ2ErPp9wDdzA8jPCS9utzr4Vcq8BUsS3/0LL DsXsRSnOPI0NDtl4opcknMTUDYp2bP8nYDSHUE8V8THG1z6gOvN9Qqt8CpWYqEVMX6ASrCPUb70m XH3pHg9mEtAJRVUfm3Ud1ZyNnSZTDd0HTz/tT3EzV9TYO46ea4ZJLwwQdvoMaLwSdrBD0U0kziXU JDSE7gZ9X5d/XWd+4wNBnW/ou6UfIdps4m+SYjNmXmhlXxovcFu6cxuiMeWOh7Vncq2jLQOGGjvL 1bPR44oiWVBxUqPmN5dUwBsvSDgOA+mk/AcrbZaEdQ9hVMUUViwaA7v6MYeb5otyABSMWNEErvzo xOOUPHT4tM2+81Jzsf4Zl7eFEIAE007MFmZ8l10GBOgi3ahyZzCySISe95FARCiSG56/OmJBgwyg A1YC6i8yNDyzLIff7LNh8ItCS0nqq6xvDBr9+Sp0PWpIo2U14+fWesb/2Lo67TixwtI/4L4QOIT2 Y5/DiO7KxjHPK6lF/H3h1rja+H8/AoPVqgQ+95RDtNNr1l1ZAhyI4s5pzlgkRT5LR+Eph5tYfIcI 0NwC+Iz9gRsZ8INRiImR/lfwvUJuPJAQl8XGB8wyu0tptcGqF40Y88U0JZKKv6hnUeX74ZuX5IGd qLEACoRWlRVEz9Ic6g7F9KNtO1FDHEWwj5Xt1BLDvbvKaLA/Q7Tp0Vs/4sY0CPm0P8ho++qM7ljg 0A+RS+tCckUs59mlXAWmZpm1ZS2X0gTWyCOQ2cz/u895eBWxWOfbihc8B84LbmLoKN00mwsFzTIa UJEsyV4AW0l1Wm1UAb447rHBdxAY1p6lpj/kUoMi3rGpasZQuM6wAYuFuSqg27yJ/WxAUhY8dJYs BmV8KPa4aAIr415F1IsU/MCCbPPuQ278/Pv4NXzN2mCwyIrlOQGhkIUEjyLyKrlVaJyP5fQtssLX JKs3cewR1ey0hMJ/UCG3iQ9h68y+P0emgq6qdML0VuaFoUIWIzun7Wt+X3KaIYfWM89q2K5iaYWJ /PqPX5hZVrHunb6gqSoLcY0niG8RWO+xZbImsMUqePc1tvjsYNoOwRmEBaTHmTn71NLH/rH2h+pz 1/1EGAFG2bWymuLErNgsE29qDgQmV6hf/px/SugI0v1Hov7Ly+wUA7X+zu7zPwlQN/yPSQhctN0A vaRLOckdrUX6ZgfQ1MDTyYa9jwkNLuceIWXw1yOAqqjw8Ivf+qq8QKGo1NNvyggQ1bMBuC6rSRLr T+LuuQ0cBifBN6ea4cza0iP/nixiujUulNChM0q+0waLVEQpt1wK3wGEiXCms6GBzyojh2XWkDzK xz4XwR3kw7aCR0Ui/haX4hv78DMf8syRPGTPgX2w/DFXLEp27O8cxLa/kYxiW2zubH1+bgZtVG7c irg65wtvmDlN54Vxfe6mbUjwOsOW1eHasgkf0mXDgJNRYixjQ5/74dTlWx9F+ILiI7Xe4DBRIgWg MAF7Wn8QUZnZScWCGoJos+sQiePLwG9vQi5x1EmXO1IIh5JsdseubjSgMCryCTBUta8CeNXZ3g9D y83mpH6gwamE2NLGzwEDRnqf+O9ZdhGa5j1IY/W15KaqWAOYWWsdSAtaoZvlq8wSn/pXIpAjwJJT gG4UHzikjVXiZ8vdQNfLmp7MJiB2ceFUQP0D2BHZUM2LSBS1emjet19hjZjiMkgnq5Elvcuoy0Xs YQaTNE1mxVylJeAd98IcImeMTFC5FkrqebWAhusiO8GG0ZnZpCHAUvMBdd8ZcgqhsPsG+HsNZZa4 ReA7RS3YC1LA0GYPDXZ/TpVFkQA6SYGZXo+RS9X300LVqIGWJK7nj28y3s669vO2KnjTskGK4y/V mAy58Ma3QnfyJ5SOU7LX6v+GdoUTV2FYbp25FNmZtNSww3MG2PmVbkrCvsGdmaxJNKjF8Euw2Wbv mL1zqbShJ1aKOh55KfFafqiLRkQOpeXFmzu6Wtq+OS/ZqSeniLhMvVQCYQwcGkeayvpKYZ0NqQ3u fOBpoVf/kq0Z8PRe2F7A8Af8grKm+mmExluufbejBAAWWr16sGlWjKhkTjb1AdpL3hvkEhzuo4iq jjGRrffsHTtOMtHvksNUquea0UOIcz6Z6OsdAMIq2IW7Oiu2T/42+VIvQ2kCCJKTq48GzKqPpofr A4jR+FQ4BzJD2qHkej6fV2VgT3KMTKyqj+lCgHiG7AnfS72lmXxwfsoszPAfnk6SHpkMyxty8PxA FtVouwdBoxnJD6lzPn92nE3NPbceQLV+8lC5yYNNRCDCVZYy6fgk3gMdNRdU0vhR9FcZV1lyOh+J /6xQtxh0U+uLmgECvOHc7OMQyHG4T+Mc5oLLo+xpkpzO27Jd4EDuWRbXipDkB74K/xj0DbE67hJT UC8Nbj6/BDGfMmB4cfEmYYUMf9k7/o6hfIXyWbF/gR2lUzNVpEGImsZBu1QGZjrKNo/ycaPGYGd5 KklQM3/RO6K5qXTTaInDcSasNQEDpVMg9FBDetOPixV2u+7p88ETZhX2MinUlb7vZwaUpR5ZtQa8 rg+Z7meth9eZCI8tUgyHxKJqSF9xUTQdrrp2vj8kcWoYse0wwc9mfEH7CsqMwMP3jn9HHPK02vCr TtSoEEyoP0pbrdc+wuCe51ily6Fsy4KEsvUCfA9RQlefSIjHVMiOHGugyP55I6pkEYEpY2fCmIiY nPkfSaQqPQTgdU9SqHpyoXfNfaw87TPMQcgf0tLXiSxfyGyW2kNJfkj9LCxTj7wGnHu6bTRZ3wlV vOgVAq09xBzlpxP9mXRHBAh5udljGpVelBpmA8AdRTe07ygT2bs6oll5lyhxmz88pOCpbvb1IEqQ 5VkI1dCko5qOH91R7YZ4ZN/hCalO4E5HJ+yhSOUmyYP6zOxlrdNHoQh4caVEWlO13o1EdVNQTqd7 +vFIWGklLVzYMfk8O0fG1923OZHHzbuh/bfOvrKeKqOv/s+6GxdonPf+RPJn6LDXZWo8IPxmGZky ku1Ly85DVAbhC5HDt0XYai+V5STL+3Q/mj7i0kky9ls7smwuu2vaxef3LO1+OXXZj6OEawyMed8i Aboyx4DaR8Qlcolrfvwh8sG8JC96wtXYKO0KUvVHnldnGdTS8+epd05nRwhWrCIq4ZoC7HTup3Fc uD1ty1vHzyJaCf7RMJp/zOtHrnV9fZ6mDr1N2ihKxRUQmMiKzkYGmxPq9wRYLHeODfaMDLYX1Ig9 becxn3NiH3fIp1m8rtbsgjex7Jb3uM6dQufmPk7gQ1ejqqoWWVz9he24f+SstDCQHTKlUGDZb5JD FBDtDFHIod6817BRnMqTrtZq0qxp4njFzi5iCiVkdBMSlwx0AWeeYnJ25AyebIQlNvzo1HGuBeRl CSffuIUD3zXex4JrqWRA9aLeftNwYqB5FApPpmIQetNe8XubM2pGZHcc/FAyoSVPf60atl2+vwm3 6YwHys6VjfcmcWr16OvJAlIbDi3Gzbje0xhzJKkUCHRnla/r/vXCI+xVi4w9GspD6ZN4hiii12Ei gJSsMxMWgUcW28GvoT8jRC8GbN3LQ9gVkOYyfpaEYkHt3TAn6I+qtF8cTqHd4iOA/kEGNtw9yGxY UJUYgl/sBqwdOZ43h8961Eo1g3NF5/IF/Ca6HdLklisNvYRoCM8zOzDyGGoqONm/CpWOBBjExi+x DeOLpc6cIawsNPzMUaGVGEnaX7ovaCTaTuU6HZRu5sAJPgE/iPwm7ZKSXXufdaPpWgdbl/ume7j+ HFnWjrW6AsAnydfXixxLDK8u94nVbxWFY6E+825sQdhsYtFZG+bhUxZbnewXziPfPDwbc+Zrwxlm yM8MPiWWjEQQw/1tdmG1VGy7rlzDE0uQV19W6Ue7WN1bYCbnSUFASpop8qBWs5qI0t3VDgjYj1e/ txs4rpNDEL5hKNpfbLy+gWtcpJ/qT0h9XIzNrIp+Vabgh7AeZtJA75iBpT+xnXhElZRbT8D6EyTj 1Re3IOFdGM6lNZjARGFyZ9y8mT7bMrAXzh01sOjp/uBvu/8nJY8gK/mMDi5bNGA/lzc1WiqnQpw7 duZ+wAo3quur4P7smYnWr9NbIyYAdtUt/4ao9vIt7EioYk+CQrYe9ea/jFaZ5fz3+S95Z6WXvZ5N dfWK+347rkBo7eBGRbxA8D0Z4S8ezzEbYf8IvTLujo0R8rlWqPtxFxt7om1Ah+r5xUKwf/LEs4fX IEXvUVa3zd3oq9rCP3E/OTTjPZ60I0vwIFOfs4nu9BbeXfmzmlG7LpOT62p9qXqR4pnMnfN8x7ln BQBAWaydbK2hd6nWfyGZVOUp4pQ70Ec0ohlPL7d7Oh3BPXKRYm8T6Z0KdbZhyrSGHsIxkxXjembg bLstQaju8avtPFwQnpA5kRShei5PAiKRTAysrQ7fcdzTZZOp/f4vUkDvRnPBV39qvmn20z51IxQh zk0jqgGlhUKZoLXhUnuLZl+VJOw9tOGrCCC57q3gWUph6r2vzL/poUdN3ncPug8D5OgNy7CqswY3 XjbB/j6+YDTp2v9u/tk/7JfbF8C+x7R6w52EbEJZ9ty2Zkpm9iZo4/V0lSfV4SJMjk7wQb9Y/wy7 jP2Gr/bsbAuKvGn/qG7qehCdwHTZeFO/d7LIIGuMn/3gytlHzf2tpxp4HmonM2/oL7Igiu6YoiH2 tdarlsgF2BSqLYGRDvIiIJWOSVG49S/46vlRRySrqpbrOD7Z3YZDBIsVMeBVzv+VQZfaNCNvb8lO E/5gud//9KoYq2vaXCaBKEjzwhzhj4fqnDvim64rPwATYi8jU4oibv2oUIcUSKS3tfszXnzRl1z/ sQO7/PfnYgmTQ9zAWVw2+X3bgK1aD621O4J7N+hfH8BX50h9yW6LTj1TANjudpuAtut8pM/dx7Mz cYIJa2tRDSPY9uM5UUeg1g+wSaJoNeJVQGndQwTf0MGNl/Y9JgPPNdQtSzYK0XMXrhO4jBQCrRIF 3KxGCX7gdwHiA2JWCHeh3qgpMsF9ozsI836TU45Ap9Z0aeFSN7Tgm3IhdtaBECJAcFlMT63ACHFV fiUTLz5AnxPGXQA/c43FAPEGYOkkEL//RDsGpOtLG78oL6gMFcXhiCjiuWYhb7yEah1u8L+dvneJ i4y/wBWoyF/tFantIjEK5owybo20/x9paXyv4804BSB1DwVGTiD2bbmQAFCX+Q/zPppeocFdWAN7 QAcEk3uDibfHRNDjv6nT9ZjVSjtJy96vStp9monejoQVT5t4ltejwlnQQr7HNzk39gvctSseKphB TlRsSrKJsp+XyDcsYlxn5IQO+SLv+1n7YVUv6cejqWkf+MLxFhvJ8JdDdOLrG3xu6KKVXeWvylUP tRK/FF6SmjeOLqPl01ITU2mdbORi7HrdIU6hxcko6pmVFxELwkDTAMiNXhHdPRdMFIVCR8ZTEK6E 7RAX+R2OEWaJ6fGr4aDG9KcZiGsKLtrA4rc5Dz0UiICzxcEK2sznDAU066jDhaXWQwx+HpejQp71 Ln125jtZRI5B2SissQwgO/Cyady2QJKyPM24rtcc1kDl1U1KS1JtSdzlzCrirWu64g5gIZHdo+MM vs6L20YYSVyQizHri/Vo0IKPtuPqzgItUjkbGEpXfYdVPS3qSIAdpK2V+dlnsP/BAaJf+fajvoOc 2VquaNoPOKf7OKmei0HwKc9d0yUfv45fUzOaNcD+hL/gfAmMfiRCxniO6jQXI4flVf2ZHQo3F7y+ D7dHEiIrBcg3x9jICDCnPjhXeFtfMLLqzvjKkuI0mc50BQI/Yt2GOy4t9YBE3cYJDh2m5R+JVt5e 4I71LPHWW6+I0xSndlyc+0aXxc+jOOJHNYfj/KEVSHig9z8OjtLneBfy+PUV2iR61QGE/mVNW6xI AtdSEfYqfbavQsBK1aBipTUf32B5eRJEG456QArc5VAN89M0iCKmmacXY1oymYfxmdLuslnva5dG 3X6YKwcqEjzyahdWPQLyWLCXbD3dja/20B2NM7vcBymrl6Y+5eB3Pocz+EfkJ/WQNEOPMOBb2e6p NUUfYsMWXWqQVGE/20T6gqHZZFTiR1jgyQBV1DoOCw1RvMmMHlp448J3Zdbg5p1Aa0aIfWtksHiP E636Zy/IJBo5VHeBEHQHoCQYZ3CU/pdtZvTY5An2836bxSfGeBMlpSWkTXpW48TO1hVxUPquYYGE JAUVOpVlL/mUWSfTerkPWcrTlOIBroI9BWyr5RrexgSS1cHf6/mdJi6DLwuajVd7Qnma1vyxlZMI zw/wA+cyHDeak87P0LVyhSceWSgx2YxHujUeuicKM0bno18RimlyuLWgLc/Wi2h3Q5nldlAQQnya IE+nXzDmvSNuMmmhlsbiS+zreLCufu9sA6wcfSYWwdKICHf7pk4Yh7OytietwTz52nfKX3h1x5I3 o7oQLOD7vccXpg1EXmsYYc67YyxJbT8U4rwxAGrv2t3qanINT7WKJEUP+Z9VXnZzqxtk10bkIgqA LsUV02OEKeaWNVtO4lc/WjjHVMtBsa6Fe9WZn0yCHwehl+76mnQ0Arrdx0kw39SOhrkIpRXZYTQq R7NO4BKanDrQqc9r6thyegCXKojDdhOv//FsLv85Bt6hD+ucgxM0QCHBdOAfDKZBgXoFTbmzQZ79 lDx8OdL4mN1rAYCuEzDS0YX0r3fGTFEKRB/4Svw4qQHtL5MQirLAuAOm3qG8n5mVaAaOlrmQ3dRI ZPrag5577syMyW0djwW0q0NEK3snFeYLT/cCv12vXTrW4c6ZW2MD79oDn1XL2KFQbGLkLg4CkIXN yR0aBJSBL44eNznbcCSnZ/SnFqnzfiH1rS1F/vu6oKXF5TjEYrhnXXI+TCybOrzMB2F/7eeiLndL nezkVoegDTJVUHyoxzMLBpTRtO678LIeSLC3fmtrhMH8uWM0dvoThzRFqqNKdwmT03zjXEhGfww/ Ax03cD/tTqX6VcSLJf3mLn40/2leOIBdq8aDJX2E8Dj2RxVnR9w//A4LM83OiBwoB+R7gGCPfGEB OEdY0csWXn2W5YPML/rX7VOSJN04m2Luf/ZpZR9OZLC+MPi2WTwd8i0vMZV8mqzyCNmS/7INwdHO NEXB/D96aGJIrTlrW/6IQxKxGygsQDW+Ak4/YY2i/MhV6+vVyxdfrx04hor59zHOFl1j6mgoycIY YkKVJ09h+gV9yupoek+SOTAwgGrTd5rBM2H4n02BIn9SP419qa7cXOQBc8R85VY2M4yTTL6haWNW LQNBywOAb963IZ/EPY6lnN0UOABIqtp57MSkTZNr8hnNJSodipo5Di+W+2mh6B3BJVdpMOnVrC39 fRxMxu8XEnPkLGqADb8aRahRnY9NUQvbxlBOvRcyGFB06wNRW0XZXx/0ILWT1pjuiiuc9QkqDbDs tkjA5k2A/Q4EigWzJNftXN9vQ/eQCTLQ6BGWmc2wMFk9EqEU5xwyRxivJW1uWoyGpum6ZFWMQCOf fYKd8zraDF06h1JJWJ2enQh1JyOm+M/+6p1u4H9XKzuakIAMFeh6MFhWCXCkX1HY6a5PKTKbXt2o Wc7QddDzRS16JKK+Pwy+gZuF0PIX78Me62Heof0CmrL66eb/2i9PWABiU0qOcqN8PmPBNKvGAP0S zyIdtuvBGPDHn+Iw4sJbXpeR7FtQ00k3z2SPNvvhP+FxhXCbGWWa9d4OTLShLeIqmmlV4TmwsLSt yxwUKmICP/fq4Ob1KqThpQ3CeDsQrjmBB4bnkiDQU+FhVhp9/EvP3RFAGu0PxCnE4Xz/0wQBv8b9 VsENAgDqzClOF4cO/qLc+TMGlL+UQkIuPi15T0exFXb/RQEvcWFJwutqJ45ZQwUva58i0fkSbUZq 8R+aQpwfSbfkS+eZtwTh5PNngGC8amyWsYZPbIDetZyoaxjgE34UlRE02RqLJqLRkCZUMGKUO2CO PDJ5QOUab9PogYdhYC+NEn2DHGor/bHKnQ5m1P4+0cHRcf4TEQefLkT8AEUcgZRLQTuHgaloljA4 2DymPasRsQDE/t+r5IVG1b9cqG3zROuSrok1VdrSJf5Gox9AcQh7iTSeBQIWrbACCgyPz3sniELg xwTcV2mPoGyUwTNQ8CivnJJpgjf2dg6Rs3zEJhKkkqae4ZWOFCt9lfSK+5+k1gYpWa12usvnvZRV M09hv+gf/Y/KBxdCAv3UVQSpwOGjhho4CnvC6dXPr9Q81y74zZiqXGzhHRiV5N0+u8OIhPTc5SWb mM4/lFGSGLO2SgBquTk5QFIc1YmYCKc+MgLAXgW7Nofymeq/5F9O7LrSU1xzVutOzOIqP9dVqX6p XNrvyeHscIfnqg9AiRiIlRcqpMXDCPJFxJiWWfW/1XPkA9UeThGwWCdp8i/w5Y649OmSo8w6u1hX Yu3qldIeNhQfSxYh1IyZIOGgwGd1RIx0UL7YtrbJ0KddrZM5VMbrPMv96/NU4Adkmixxp5d8d1y0 Hy6/Bz06qspDZR0SJvqZ61VrYqKpSlRIYLD1kHzKayPGXms0Ge1+r9ipD2cL+bCwr5PAeIFGDx3U 9WLHKnCDzT9vljTnT6JXGMpx7dLZzsp/DAE9EhYqFMO3hDZ5LjQ0PZM0bzssQmR5riDUPNu9VnsF Uu/zBamKtehztk1Sp8FO058Wmj8zCKn/yFNIKxU0pUnXB9KZDP3z9zHk04yyzYUWntCQytm0feIT EM3cIV3saaUYys2MFbXobuRpPlZSCnX3ldbAvWSwNksMlPpGTsnHQZebJvbLPLiwcDhPe9jxtYZ1 wy+BgbALpyKNeUvPRmQaUk1OY9Rl2FNx/8CENGV7Ytc34kDg9C/FCaC82Ytw72c3o55OxgIputby 0pMf7FDXSjurI8PELuvCvdOHtMKz8EOdiWk5G9w+1aByu96QfFqcBEfpLjX1G/o9AYNP3V9oA2vl 7GHCETORp4FisRn4USsftifva5kqE6a7h/66Jqll+yBQG4Qb5eYKhb4E2dBPrXOfQ4YmkHrtlYb8 e10zYPIOcRSeZLnRlA0xG4v7L+bF73e0ujEqQtCrMVmMOIqKsAb6n/dPpBr++3vqJ4vxaP6LxS++ b/6I8llNgX2Uzrt7CWmtsstGt8prvmlMYnTUEfkIt7qE5V4pO17DC6Cyje1DFhOdNvZ44RGiL1HM Vj4fEjsf+GDlSjf9kCnxc4tVKUp4mPd0cKcE8cd3hEoebgdEckTK/sPA0IavrKOXsnP2Pzqv4R8h m/LbEIH0r5jySxBsZpH4e7jPOfSxVdxkM/kZqJ8OGmIAjE87kFrM5cV6Oo85x77R7iXa+knvuZ7A v+/cYMSOCnSdA4OPqYgStk1+pjkXztgLG+9Q4UhU/kSRbU3KgZbm6eFlVex0hU6O5QmMvZwGDFTC junCdKPlvkVQZYo2k3DVcf5zOX7pQ2LBsdJuCRj/qOd0HWeZ5Qn2eBCPtBIxNqxhUynZmET+wPc+ I40p8bvV4q65MLouF2x/eulA7C21QR50zaMdgsWq/qSNehQsiMWHoisQqq9i196IaxuI3t4XR7vt xcfibBwCCS7H/FhRcdCLHo1cj7DNZt24iZqKtxK6V/YYLpjojwGnT8zc6/pdyrUaQI6zo6da+Swj t105ih/ZtN6J4+P2iT2aZzn05GjPLQeCDmWkgV6+4xknt4zBH3VTt2ChXJ1GXMnINsbe0eVsaiJ+ 9heD8L7zXsMzvD69tCOh0qOcHFVyJP2OUJRWtWUskiCt7kNX6jCPD/YknKtaEDyAb+DOEHZx9SSO X8fou8wKJ3HXy6+wlpcCIdq+OGoAqxYJ3Gx02fy3CqO0WoaRwahnA3HIniqURq5DpNZriXw0unFD tXJl8Xqq+0UriWO6vWd5ZdVnDfRdjL2+A4qdaKSg6D+X+2o8UMyBdMSc01v1ypRhpAkFASgthZnc vaaJsYa9B4OHk+cjww1UX80zQFrC9qNaymEtJHgURgzsUUBz54dTjlrUcJlfJpq4flJf0yx2/d3O eq4cB0RNx1p6PO1hZ+EQXqfXXmSGyvH8bm9hYXxHGLCN6J65nNTrgELXFsuKqnpXFLiFcZM9Lu8f tN+kdozrjF7DEtg7MhqbILZ9UL/yferxHlI4mRrkXLhK5RwyDgh1JhIPqoS2EgK/iF7q+CO+uwyd 1NEAlHMhQelD4+SDp73cxgQ0fp86KrTknZYRNWg/BFcErztm6nxW8awFUirlUAh+8Cm0f5NTQvOF 2/SOCJNbpu0vbXQsWWVF6GtfilOQH2RTSaixWY0KYGGgSLISEvCyD9zsSEIl6yaXB98Xo78DTOvm asFOrrVqR15yuwDw9agV7HpL+TP9nrmpdlwFRq0eXNhYz+A7CyBzhdKCKrz+3vQfBBa7uGGzSrgB uo16PPLdHg1ZAoucsoIrSAZoP+o943HU9BG5CIJ1/0A4H5h4BmiFH6aYjHUdjIsxbY/ttFnUDj7i 0GumnGwEmP+GP+Nuk2m9+ZG1rYoOdXU9T+uN6ydUF7PocgY/kjO3KpC0u7vdKEyw710lIprRNmBL 27rFkTm8eHgODvXektfbpu2xe8nCIys7mLhGBxJonKnimNDUzSiAPnnTasqoYFZ82E8/av4hToU8 XhfwWLcxXqnt3K6DRr1tSJiyfLgxyYKHNvvMYNNK2REDvKLUNtSEUs39TvJf4b9arFkJhnItdjWS 5Q8itwBdZxLxLmsh2ovC693aDDvQdS1bJAgS32A6MBstj39eEpet1BVYAnPpu0Rbj5Ik2lZJhGE0 KCosHk8JUqS8bKr5ULTFyXogoQnxKdmQZbcBaaBts8qnaZAmjiYKgsAZkT/w2Wli7AImiPuj4/4R jZNOPcSw4wq4N62wTcoU1K9YA4oBFl80YtwLT4sLUvIDXt1/gpg+zNSCfvBCbfOhYBWrGE9zc26d nG/JqVxtxFhfa3jOAEMydkrNSm1XMji4VO/uceHJzWdGtWA8I8oE9McaqxPpTVrMjytYxHfH60Qt kuMTgklOMMw7wVJpvGp2TfBiidoZxRuyjB4TyJkQcw6iHNt2x/JOJyEMrakrigwdIENc0YV/8jkW O6tFsZYXgIa3Hj6S1eQSzzkgegZKUfV0lPhuFXsyAaPzv1lDAwWw4aj4+fAKdbo8SuZTtvB7kgr5 JRV+CQLf5p2fh7DzB2LFiW5nAeMgOidAr9FS/hbrkKRT/JAJiJX4EtNfqcBb3vPyedbY783Z1a0h OotFY8u2FyXlrW9U7lvb1T+ye1NOe+YivAqkY6DfOM3PGNOgIMxGxVuMzHPmzt9NojEuqwdI6OIA RHbkPGsCGnvgTo/OTj3O3sUZUFGUcqqn6SZj7XzWY1CDdUIYICy9aTOMTJnRjuNZT7o03e77MY6r /ZXSLlJkAs+hs4SEAeH9yBDwVVWBNxxtDkZaWlAMwmvVHi/WTLsdqGZHM2NGlByoDTbln5L3kNG6 Q3+A8479R+7ypVkPrl2VaQJ6d1K0Vjl+j++8b++Mmet7iYxotKzWXQruBLtprM4VjoeCsRDGDl4c s9eeT+4yJAaETtJxlhHKKxgmj1C5EvHDrAmNku3z4hQNFWS1xsdMDamzzPvktqdOpQ6FRolIGMJO DyUOrdyVYVKUEhUXaIpDo1k9vZWoQsi4vWGkHiZNq22O0qdC4xsv4l0Wzr969+OkzTMocACAIaKg WRh9l+w7WYrGl6iRLqq0ZsB7deDOpLl4oNo86ExmxUlZlojAETdr+S2Ry2HThB7l9zHRajTLUP1E zLDUPvYLBAabEBT+XCzw7mGJ9i7hn6hiHerOyttTEQpsMFSMUhiW4wRRiRctax3IajaNlv5yq9nJ 9nOGjrhzP+7WnSFAVk0GfWDMmAlK8jDLYqAMvFQHzdJSygJaLqvIv1a5MaNoUgFPVkvQhTu2jby8 qKtGXsd0Pa6kXEq5gBXr0a2cRszc2ptk1A6CF4Uh/jbwob3PokiZghtpaZwOqH+GQpW772RDy5Nt mOerSez1lRFYnOA+sUUswgnydy49jimyCN3Uq9FfovqCfq5bWKapuFaQz4/d7VibDuE+zgqoLFZO uZz6QuyieQONgh8Kr+Q7BVjOvmdHWyi+fGdb7BCKQ4rQ2smaKf+vPN+3AG/BVV14rSAatRmnr2nI o+rD0dZl1MeQnmMnIRv6ul/UtpYgD2xGzqOdfGlWx1e22me5LNZ/gU9dk0iaSxHG7MWphgmH7WGl zuBNxY5AyoAN0Ppx03jpAwdVFoWffaUZ7sBMRICfTqh6WcYPfln510Bhfda2OMziK714A50iRmX1 pyBW0jUICyy6uSNXvWJxMrR0pV1bGLD1slTguyz68o9ob3ObKnWeMDoMV/YCPr3071gYGpvrzHcw JA4BntFhc9roIB1pVpPF5+rz5RtDLZNpohk2ZEbd3yWqzZQOnnHofxDpWkP+9nWUbZPCZGwQ+7dh 1SL3iVYLgUivZL4IQMOHQEDTskR973YYldrfq6CMNfIGvd1xolwgko+WhvtEYZVRyRmOmov6qzAG CSAN+GJPEEVtiYJ7d8NDmy8fpEzePqpqGpa0i0hbGxYwxuzklBZ1yTFxt7Ml69AwGbOOMSElXDjv 2RdJBcK0XfoJHV6GrlU7Q+rG6e6000DyHtKJP40KwlZhwnY/xLb/HD4s8aFYEZJ0F+gjAKy9wcSa VhoHvboLnWa/t/JufLbhPMwslMNFClIKEy0K7LJwaDAzb7Ty4ISGMAbCF9tybI+433dC4N04Ylbr xSCF7g39IijW0lWn35N6uRm/bEw6DPc0LOOpILL6JeICtzDN7AOncgbbSEXjjnW5b3ubYgu27Q7x t01ZJBl3QbjAQRHGTvGanU3DzvtF+5WB0pmEYSTzuTjghSm3hHfm4touH0dU+lgCITzDdtUAqLAk PaKdQ85HbmHZYQ9CiC1OaOEgMrookRvr/vVwiBRL2vRI7EDU3z1eJCqIwuu5GUtz6N9aR6+qT5ny 8TFBcGhO/xr0kJJr7e3Teh2Ahd6dOgdZZFvunDuLyNQ7d069492U+4lgCRAEsTZ8YTXJCqoPR66O nSdXcYLMCJ4jWUNoFQKLCq+1mrn46kXs8KS6bm4RvADMesXSFqifQ/uyob4kTgqbvGPuopD/Hpk4 e8LO/+NB4p9a8f3/miN/GRd7FL11j8jo2RmSJOC/D325ApBbUPDulVpoM+NtUzEthBljh6/A9XjS SiTWAZdVjffj+rVnPmTZ5JUGDuuDHz0lBaNLJi2jcCH5wNvvT4Reo7/07jKzzhL0fsuAxpF++WE3 fDI5R204iBqZZOcaUpf5IJlGTB2i/6oVmQ2uSI9ENXuZ2LNwVHFQ2kkQ0q+vhMUgjWcmxYu8/jOJ ds/dgPLtfVquzZSohJoHgSjiGvRSQLz9Nyfaj0uj3jlPoG6N+KsRUmuYuUrM9SCQ1kjR0INHn4hE iRTFWRuf9aKzbskMIh6WepCVK9bwSDyiAeXGRmVT2BwG0Lp5GwOfOOpjIn5RfPXGcmnEJCGhzO6X mmrMnAtTX5WldizqC9Y7NE8BbfmIBHGIKklv6Ax3uoEeDJ4ofYlCJa5TjGvFDR1fXnLP/0OAYEw2 pDUJ2UwGY+nWdQW5lZyV4tfmYugUR/VeNaKv3waFoN5s6qwyoorSBkKTHh2P5/npFYEN83XcT+tE /j6ot6RBn1Vgtwceraxi5Rff+ueVlwFU+04K2FZa7QuaufE9qyeF70F2+MVD5tEsYrRh240GGBPf y4py5vc6xiqE/6N7osYPv7MhS/FADAboFHpPv0u5BuFCeGESG8A32PfoJ8JTUQCELWew3fUN7xWi 7R+axAjzE3Z6BlO3scbB1zZdV6jSp8KPYsKvNXjQMbYR3C8dj5GTryO1FItpOFf1id+CarKtoTq6 S5eFG9qBxtA2FKaeXfVszIDFPkqgwCRZxc8W5exUy1opLq+SeQyTTaSgFo+e0HHFEDcvFLXhBinm Oa81I4NSL3eB+JJQ6KOfA9bx/jeYEZZ7C8Jg9zDJngmxpz7gJzul0P2JBv/xn7SVuCQLTO1mXlAj UqtgZxgXKzslYCPpj0SUlYZYiXA7a7UqDxckw5vGYGOCUQeyzNAfOObZcjgY+qQVtCyO3kwm9nLb EwxIQx8bq6oO2HlFBnUr0pbY7uGG0VSntnLB4FMEsCtzlaF0NkqZk+rZ99s9Ezm844HhwQ/aC84e T5WhHJpmcXPDQiGJHJWuUspQRVu9FcCJfvUgLmnZJIz89/rESHd0lEomgwAKFtcEtMNaPckiXjwI NFOxHGdBr5DlqPOhjK1KRbQJh8ObzqYsSMPdTZm16ulm8cYe+HF/8XorpnlPwsaWcoHVRycWR1Rf 24zEnbAOXTzlA6og8/kAYPp3Yyny3D98/Bhwhm3hM3LAKsIEcLiK5zlmAF503ouH1BlgrCVrHCMS ZW95Uu1t2CtcHGMVDvOvEWQS84SnVjzlaq9UyNgbe0RvzqU1CHWn4m2zX0qIkRuNIMf3zL9eM2Ze zXCWMguI+7+6oU/aYNZmRX5ojuhDCUKrNz4FmdqSw9THaa3KBN7duiljnrSQbzHQEulcScQU69wQ RWZC7jhNNwmzhJOaJSi1nUm4cT3/MRMAaGLDG6aGD419cu+7gm+OXhdxzDH7SaN+qrBd2HVdRHyr tOFEUTXxCADQG+joVR7Xl+jHoaoNQMX/i0joF86KBKRmNVqQUSNnDKX9govYdQcIXE0eQLJI+CMs Ms9qK2Qn17n2Ray53n1IsCGvPX9ZqL87TYxqSQrIVljUfhRQ0z7qeEJbcx1aaXqUL/TFKHBr8i7b q4BID05LQUNjrIpcUkN5G/66nNb+EDOwZuyY+VJ1+xr3od9xcjR+y3A627AgPZBjAOWT6GVCyqpX nbGYOyFcAfiNJu6NuH3fRMbnkvWguzIvWsgJ8bFdDiZ+toLvSRuFhvQuO95P7NDBVffXK6gIQCIV 3aOGRjxJiWEeAzrey4Ktojp/cGqG7JR8UyXxYEFHoMa3ANb4KjTUAoJW+IPydvds2E1pxaAft2kg 5ypuLJMqLD/8OvSgdL3EM4Tu7xtQBY/oFYSmUCbFQ7E5PX2DHQtDIKPMVH2shMT7pR4j/jgMsuoO WydB+9REle45FpHzSiNApaPoE08rsUulNI3toJRVnoxkM/Cqwc1Pp9k0W58pRWdu1feuZNS+LsYf 0Z2ZWbEzDEQ6A3VE88JzQyffkE56zUeHL83q/9YTJZcqdSHxxUUGU6i9E0w7fYM+yREGYsW73G3O Y8KooLQspTpYnk7vqXjuzGxKCSvY+uSuGKS+BhnDGqvNP/vaeJMsLX6Vn39aVv4+T4JV7CMiLCre To77QFuJGbxx+d2yExnkk1vk12qsMiMrGX/BpYlRvWMvtRUdKuN8R/C/Ze+z7qDt7bovJlAsMXLw AG3D5wZYD1dSfVKV3CjOIGIa3e3rY1TXGBJ/GkugJCtjStTE+UKYUAa8qeK8o/AAYakQpSycaRbK 6unTacDhihgF1ixwqvHl+XtxwGfaJPcz+5b/z0w4HDl/gUe3JlidQaSwRC2EGaBCtnMfeEHleRfz ImGBBYqgsTkyqckexh7vYsvqcgP2s+pM1ZybEDc9X/iOGIcyi1RG/QrXFcrmQsmwQqFK5eCO+OjB h9y9Ys6+1aC+6y8wjpN2tpbAkAhHIWKlthYGPaDY8mfjNhwvJMQFxAn7VRZi3BHzHpm4XITmTtXv JQCamEYxN31vZSjd318PQyt6BVc1HvMEiWLwZ/s0gb7fycE/aHyu1GYKJAKVbpQMk8210t2oZHuy 8BWBJSpCar+adxskUOoPi5RbpPhsppPU/eo++ffKpF4r1M5bPOy29KEysnSGU6Q6V0jQg85rtyU0 ZypYRF4T+ZLdgPDLcLvOPlCiTnLZKX9m7IPAE7eHolOng+RMD/JtnmA5T9GHikG4mRzte/Hi4nWR TS1Ctyr+6ASY2BELJSmfy2SynBuKB8Ig6EGO1g/dklam9HJu8XfEHOtWZQDvoQ2JVAQZUhCesf1A u/CDJ4wTZLKr7Wqxw/7ANBXuG9LplBu2GrVpC/7AfsW8clTtlGUEAEX0ECri8Yc01FxfUPbi5HJu UHz1no8E0+TNsyVZjKU95tAYOVowDbMnVlebirl+/wX4hfOivOGFtSOIBxrcQJd+9UTZm1hkwyA3 iRxvW3WAAQmgcOjcVGBHDyBLP3kN2v1v/ZxYYQ9jjwbVNolyHqbOVrlprB/CfOipZIVY2bW9UYqX mOt07MwlFbDwZZtQOmnX8f0KyBvkAjmuBorkGQ/5jC7Sxw8MosO//pS/2Fz9BG/gbanY9nKeNRDJ vBb6Au5IkXtX4Qc1J2hrMXO3HfaNYyXEZqRc5nKFpG+QhuTUgHWJkfnowDcR9m62R9qGy+yp4+o3 hJsK7p5S3AySq2/UIrrQTR7sqdYEpTXwE/zqJzKsRAOIHS/Btbgzc5+3+HRZ0Jb5TzWYIHsQj4N2 fS7rPsx4QpuE4UBV25gsaUovhYZVb4L4Pnypt7IV0hfTJAXD5Q0/sr6QFV9BGXxvS32X3LRKukHS oIxPqlATQI7PRIhD51n80BnpsD2avj/id7F4J0Uw8NYMlg5Lz5jFZOIHrQD+W7t9yBHR4MgD+3AX geXOxQz1BPRfxy2pKPlk4yIsWTZxzuD7PdEh3soY8B3wi6r2xuq95zn3konGuwZrUSMO+T3WGPx/ /Sgak2DcKfks26/YXVjlTJdiL3rF1xuZZ4zsr9ajzsztKPdy9UlZe2CcacsUtUTpujaDQIBNlcVP oQxS5yFx7FymdL7VBgICyRNZkMIGC/V+RRndT+GMgWHYaLGdbTmeJV4/xL76H1j63ISQhff3JS3/ vQe7EPud/58cQoWxkD1jck5NqCBU0+svQXsUqE6+pX42T6Frw/bBBuaLRScgI5XM3oZG1vPSPjhr 9uIPjMxkq6NIYJBKJnKshyjDaB6qzlSc7AerL+zAh0iDPKHUd/LOg4kBZeX6pV4t6emCy66NXT0W Ci0NK7nXqnOp8dlkVf/pKoDA90ANOZzD4s2OHiCFzj9u5DTJT/u+UrvHDkz6bN9t/UAeZXfa/MSf F9rUK8dcQqnS+oF7ZL8IesDWVDK5loW7JZM+VFAQkUmdg5h0nRuPR+My067dAd+/M/9pPfzrPI1z 3hcPM5PewLZvbFh3J6Dt3Sc9FtwVlz0aIhIKcQIeqGHRyd29UYcE7trw0duUBpyoBMeHG2MEbrEI DUIiuaXXjlHr5507R4EU0nz5OSYbVRQ8cqt9yWNLYI6BbYT1cXUGII32yfghmVbLL1fP1BlyD48k /tRlANJArQk9Qbv6ZS1P15AYvtelxrYCbqh6K0YwsxINOEtZarfP0kvuHP5bljrv+YOrEq3TI1SW cBjldudCOzc8KReA9TwxT/2bNpu6mqKxThBdzOvqI72DntYB8ixXTv49AKLV6c6sPLE0bu9BipAE 7pwWkzprwI3sNNTYr+7FxhNyN3vX6NbQT0P5TdERacFYPHzphjs77fdT4s3wTg4UwsaZk3+L5hmP al9jzimNv4IThUuW40xLKI2B2/lHa9Z3BfQ4v3dEDhlS+L7Z6xPquIPjXJOE2YpmAuC+56l9GRYc /w7Z+gVPAPB8C5poeGoN8JwSv0buMpoeNjepJb3OmxRPgys7LNII3WthN66A21vp4eVAoUVCv1jI JwoTu5Y5dNxHLjf+iCQa3F+du2l/kwVgAsV6bmvtuJKiyAjVSJhH2e3CDk81VOm57TIpYsYqSZhz BCmnqpcKEfrz7YXUSjYRSUGnSY1MUK6eR2t3PJll2vS60CbeELBkInh+iKSttkIbJEVi2sYOqkTZ /PsbbgCvJ/z9B2o/bCOV3p/ifK5nS2/gdO6mSEkj+gsqBVUlneNWhlZyeSpxvWOh2ov2IlHCDljh 77UXGinHa7RdP81HhqevXKojE3kZOIcOfa9Fe6zSkAXJ4/uF8WN+dIvgUxumdQWGOmbDa0vi/oFh kNOFa57Qz8qzglxVoE1gJftS/z1hvI5dnVqPKKAcZrNjSIoVeDWKNab9hxBFfr+slKjO9L9qHRM6 I8WYpPEQYJAOkEucMZ3zqZb4UeFFkzRFowb3bb5toIVPOA5x4sonBLGCyFqKTbOOwB2F75j6pRy+ UJm2K8nzQJ6GWSbskkkAoUGN3ZC4jNveogX88fmGFGpk9yneghG4Kvmjp5kjtQymS/GqpQ8XIDI8 FTuG5HViT1S1b+EQKP3ubFb2yhSFUHN3Lzw2Rzj69IbfMMjk4GLdztqq7LaDJpO9HPDgnVmXJWwi MvTi4RHIS+KiuLmQZedF48rNnZ3mk8MhZ/QFZzDQGMUjXxlg4TO00nh/j25TnZER3aW5zYTN25D+ MFlF+PR8880M7MHkRq5HAhNxQl51SgTVypSDg2b5YwRfc6JPC2WajtmstVv+21SC7EL2Ysd8jnWt H9T3jg09Oh9XW9ajr31DGhdiOh/dHgi1i/1mrI4yTJPBYvwvPH7iWKAzYbhihCLDBkutltRTrZfl esEbn01ZcbdKfwwDiW7mnfqa1gr2+HVmQMR7TSfTM/iUh+jc8Pp6e+nN+tcCwBbVc8EfQOwMIAKx iE+czsFBAYTjjG2gbB+nwxXm+HxuONbsZfNvgxsvtBLAX3Y9LASqZmHCYidg/nezQmjC0V+B3DSD GRF0D5h3BtqgCuDdlW+nuopjcE2hHpYV+j7+k9KPPE8UbpXfUQ8UFKqpCPOXLEUXJgYY6es8L6+k 2VkW6+qwkGMeO0uelcHZHw7phIzJvoWCWY8x1A6c+lV3DUH0sDdpfq6oPIkD5QPLymRbnrj7awg3 8KAffJyvdXuQ5AoqYP2fvei5sJbPwM4MM9pa5VQDANl0WpN4N+neOJSS+jg5W0eet1FEO49Ho3vz 7+agb91oz8T+i9ODeEjgJKNxIsE5jggNHbQB95d3rujhCKA65/pUX8VlhnDSHb67BbfGwHnw7pvH 6vlhEJvL6vSv5yrTGDNO8EjxcRwkKX8Q+D9sUEMUGqSzpkU8hLkTyEGJvTKnPFUDNQxIdzcxet+F Hc5TpDvPQOyJ9Wmilf8AmiA8UctGDVFFWQoLFylRv5roJnAWk6gLzJE6ONWB4LHrj00p3i4xnDD8 HpP/RI95iO34D5KXnlrzSKMD8WBRhS13jAUHeXkqlGOj2Cvy3Vjx+YdUS8t6gOG78DX88oQUNoGi 3yfEoApQk/Qtpuy8xvxdWzkZCqYDLxtv4khlWvg086xM2ihGfGgerX2kQuGcuyEg4LEBocBdRv2m cqLPRaGpYIZlQVUnRS/M0K+zSMRTaN/Qz8tcsYB8OFAa7ezYCBabMGrHgWT07ng7/UBhH1jYkA6n U8j7oO8CYv9kzcT3xM5zET4wG/35nSSneZjKcG8mAMRT0Dz6ryXkJSL3BaMARVl9bstPRlFCfIgK ddOA2HBBe24ioM31b+RYRfCDWosfYpVxxqFQ59w4Bq+Ecg1l44B0JXMU3GZDaUhJ1skIl89l1JZe SlwExO1hmOJ3u2wos5LbwavRGCBPEeWe5Aaw2de9ZOW7UKRB0ig5/bZWErrRmHK8uBJi+jH1YJ6j vRqtMIH/9KfHlzSOJJfH3na/G15HwZTFjpA+5AkQKLJPbtjB+EG3fwEu2oZLROobpZg95+NjA5uX 2WV1QgofOU0Zq9/RcPgtEavKUbS2dQLYwFEXEUtfMckHp1zv7utrVtsuTNF4x+Whs+jLDpKBGTV0 sIkmtt+KSBw3/Gg40Ie+8ifWmnKmg9Atfz4fEYGbIaOZerKYen71G7kIg1277SLMacW0zXUtXCe+ o5SZvwLiKkKxwBpAQ+bPlp9+IRNwH9rHmYkAIdT3PTV0PVldwe8/WPN2ZMD+rt5L1PEVXOLPTRLN WfG1PJN9is78aFZFBikGKvBEiSz5j8fpDEO0t3xRb4IiweTWpZFACYNh8CLw/lo8nbFmpNad3B/C swZcLBx7nu20qm1K84uoOAUaEV+JClBd2R4fcI5iITpycFg5BKK3jbS27bOf5vfMgA4fsMwyGJnG 5ttyxf6L5ficVzJfIx3mEtXgDCRUl96MRgDAsMXrGpI8zbCEcc5twldjshd2hImS2Ch4uivh9iYO ejXW7SDfVQTSuJzqECHLYZaMgOUV5B2uaHptP4yPo1i4+vaWrgakJqS1F9VxJTW91Okd8yXt3RP3 E3jirqbz5/yF8DvZV/b2+x9iPDGeTDS7pOSsHM7txrY2ftiD9kxU0Dkg/k4r2lw8uzqjiZWy1bDM cxmOzqHXXVBDmJK+kgz7KeHRWi/RW4lcSRol20mPkDLSKL9SAuyocdzDGWbxfCtiPq4K50efAu6x 2cWAwhFtnDF3xpzZ8PECc3OfvY8qdeDcspxAqhrHeQUxDJ+n0rQ0cS6gc9pDwhUWau2Rh682WYQs 3UAJIbW0ilV17FVs3ssuWaZP9way2qpdwofaM/f/e+HkdJytFANT1Q9i3Z8vTxcWksMccFzwpufl N1zJSCfa4Sx46syiFY8xeI3Wqr2i59VEMk9NjbOQQooqHO9aONBsczf+/bFmtFHslDMj2Tugfy8I OenqHMgLatuNImIZPUV57x3kiNXa2E7B7OQRQ5861QEg/YjdNArZJYKBTpO44lMMyeUbA4J4+DiE 2n1pgHLJNJt1v81hKAmHOJUe6slKx3fDoSMnAIjsyBemMjuTDmjPVSNNzKH7uQr29Wm/CKxjOb11 TtTZ9YyhXlv3hmyKjw+/lFi3iQKE9BD0mdAxWZVxDpwjuKuA2VGQncl7eBrlgXmmt6FM0k3rRysA jUx0fNz5/Gwz9tGg99E5mxuztm7xg6ZxXbjHPAiEwOVF0PX0uTqYTs7TiKUkj5832Necnt7fAkWq yb9jNACEAXZVHkgYhSYqxLGaFPSseL/SxKtHW+Ov6wKFbDSKs/RzqHXwIie+HmKwIRkzR99V9G1M nvXRQ2VrfSQCatUhu2tROvDWBPqV2pISzkEcD5KiSPUpVjSzW2RKx+Z5snN9iPF4a/z6SQBHUBHX VHo5mZs5+6+z38M8xxDwQY6zaIhMNlwahGte3mvzRhzx6XvkoirZb/o16ck8IM9wMLFg7WC2zqHN dmB0UgY3arRyavUt+aflb/aCzUpz/mOzXCbq9eacur8MZl12ZABEb9tGUQqJlVctMXEw3JkN3Op1 3Rinfh164UYaR9zFCBU9SL7wa6JCR58Exc26mP7X3m/yoNa3nJLkAcoDwFK1TBJvA1pc37hG+pVB 7g1nj60aTfxX2Ghe8sQn11NP1FHFGKoC/lUDKnRGKm3xPcHz1MXqtJNT+cHc+19AoPTtf3SKoidx 6ojkpn4FlSo1rsh6RAAfPYqukNp8tuk2Taf09FiG9Nqjhxlt1S+0qgFy9rPYV3FwmesP4/vqrHLZ 6UJg6r4MWtVvQ7pJI4x5OjeZ0ccDLJPg470V1yTM7Xw1KHqWjN5xwCnapY8COk4ibweLo5Wgy+O1 SBG30ufiSC7gnxCkXx9mKt7CT3Mvr1NdLhqGKoRFx7R8LE+nBGtX6Z+0gSDxLH7IKfclZMAox9Ux CYVM03z/4rREFnSupl8h3lSW6rambjjayjIExvgGz44dX512/hVHlw6pWkArSWj1pNmMqj9fwtaM xM0569G+JK+/W6qEiLKyvJKcNKPfpgu1wqTLGtFZp5aVTJziZEEOVg7okrgP+FlSuByVooBRkB9m ISHW6KylTsiUh4S8d9jbxXMybNeCsBsXiMsybi/lGHHfGpCPh5CoQfD1bcrrdBppK+bwKGqNrEPr Fj9t82yA+fOA4Ens4U8e33gG/oo76ljHxZC+E55Jpr/036CuRAuLK5j5A5wkBKHTW9qExvoLxKVp 7420I05zDMK4d4SfEhovBRM1A+3p5iDQDQ1+0j9rvuaNwISQ6ohuwyOczyKXB+0bQqhMnZEWz2RP /TUbaAmMy3LUSeEpSWQKTpCtaJ/eCgl81gDGX0mgxVNxWpG9AQfVkY+S0ZUtVeB+6yw+KSZXuY7n Epy9ZkIHitb5STeCfoyWfipQR8pPsr+3SYXjQ7mZJ2tLI5iz71XlI5ZP3rKCz3fQlmBGzJ+nlIxm RBMjZKVMCU7oeIIKS6pOgxMHeHZ+fh2tgM0PlTNI6uH/ds1BGLRghcFMH9NslT/2DSBZ9SPfsIgt KBoNqWj2BBqs5HzbHaU7svS8lXlhkfofNFScS8beVfw9X5brNkwbUkMY+LddQSEmwGeAK6P4bTGd I3dwphX02E/MXbSMl69QPsSb0L0y/URlc9f68GYogTjm+f2SDZj25seyIkTvdxuRufoweWBR0e26 MZYi7nLGQlH8gZHhzf6/dOqhrD+KYuAcDIRlYmlEX44dWrVKYj2xAWYPIo8FFVDW+/QvXxoRMNvE f2gv/uQ84ljtYreG571wfiwQZGswgC41Qx88YK9iErbOXFU2tJu5g5cKR/TI+Vkod4g8ES6RqAcY XTirmTYMsMszIQPXRJlJ6eb6FbYZO3IkCgLZVx0X0eELBPwcpLlZRfEx3BGQGgx2V9SMfH5FrPlF Jqh+c8fTFXa9VSug7L/VUGavgMIJSFGozCZWdlgci5/npkVh/oFebQfAGHapROq5XEVYyT4u/tyN 9LE8dNCxLnYblLDke/Ox2OyiLWq90fJ7AeqLto//6B36YMuRV0Sz8TAil+3fzzcFxBnbJ6a1zKHz tMIQRNW+vHEsnsSdGwk9/g5MRDEvN4VBuw+Uevg5vUzFj8q4X+APg5i39JnOfFRvKnID5/ikRvh3 83/KgaoIL0AA4ICVgH3lJqXnZAMsnsVIOpVbY10XagfiPEme59J4xszA/DZi/VAubmm2R2xLaDQK P2RDHSTY7JNxB7IktUFHD0AqxbTkgRIh07iyvzxMnvsr6w17nAg2Qd6NwAudpPLj1nSIVSWAiDZ1 eO2TUbZBjBiA1eR9GXC0Dp27rTI7bgM5puSdfKyTRrNnYgX3/B6o0ere1svHLbAEDqCvppw0GQdr ibHOHMrYQJl1tbu1dGLAldDnF2iOmVRRr4A4fTxaoLTQaVXM61nWURDYPWansEwY8/xnFu1Q2Jfz SoWfe5Rd9WIPPgNbikV1MfkDP5nRcufpndPGohpjbc2PF0ZlIWxQmiJt7PoIr9vee+0l1/fEDIiW coZfGhWsVFt61VHmzR5DkSHh6BcYqFrAWcMae5plGhrokxYLqfsdslt4WBBjbKZmp5iIeq5oTkcj UqSQ/1qWSigsl+zBsMV440dximXZ/eRZzjflrr416dvTPHE06bwh6xM162CNkn7oRrcAjcMEKbti JcA6+hizPEgeRYuVZ6k5jB9IayZkUT4bpUTYi76kC0cCk/az2ExiE5P4BybugrLtz3ub1Kr405WD mTXfkkcZ4dmS4GRv2I9M0j9A+eCnwEBNrY270I492axEtw6UfGbqStEDL/OcSZvwtZocYjXTUaKT bYjP2MbCr/RX4j9GteKMQS8oZFOWOZsKVMiHxtYZwVtLxDSEpRD84bveAAyevErS1ZeLtLKPYO1H jz53nIS0RMg5hQln7ZUqEQwPvNbMBuFWvoae2dL0BiMuATjjpAeKDXB5ibonPIWK3+9zrJLCmlew qGbYcZeRqIGkzdpL7dZfmF5nG1R9FI6chn9bTJNuhQpQ/fr+Zv29WWiF6LxaMv0Xjncj0SWqUju/ YKjVIVHzVJFqZmEUtn4YfVskqFn/S02vodM/JoF8Wsp/xdHIHBBujgJCskLEPmR70Ht22IsDigjY HgISIMYs+eaJE9c5UXuquxtVvV3DaP5w78qg8A4/hS4tbcEoHZeYxBvxCSLtPSpFBYJ5jieuvG1Z XrZ8nGanwdiOJuU6doLuipEcbg+5hM2O23di3zeC4ce9DBboMQhiOmfWStAD9lWLQY8C1oGVA8Eg IAvldYTpAYp36LSkSZBirlYbkD2MlKeqmeWghR2gw54eR/OSGTOv/iHCbe9DGxVXkw7KCZ4QPoPM S/Jo54sz8gdZ9bPEkI2uZrI66fIPrhwDvioiJWT6GjiZVFWsK/O1uYdpErChZ/0Eisadu8GNArmN QBOTfcUrBkVneY+51HX0N2tvBYIM83/rtv1Vlu0BwjQZ8MoyoN3jabyDg0MEA3JNXekXYnJ/WkFb wuGUXvIEY9Pbt0Z7pHi9juqkSc7wzPcPgTzKmMaWoOkA4YIgtzXPvKKk96Q8cezYMXjR2x6Rweqo i0kY+EwNOFMtChTIBs2codVTFS6YGslbjyfxjYyAOoX8cxWaVY7iUxe1ThQ2FcLK733okM5vk4IC pq1JuAXXlZh4AP/MSV4nnWIUoqsy1BAi7KRg6sgKMqSdk/YOSUJzqqufmFLs1JU2KjF00Le1AHKB k7CqkTwYXIfzjz/oD2ICedB7bRkpbnibv48Tb3SbTw7ViyFdlgTVifhU+kyo5kL5/P0YkukEcaEp EKoiVx5Gnf6rBNJZZkhJvcrVK7fZaGTNy5GCzVuj9rWMaTpQjle97ivOm09JYleUvGfa5+MH4Y/z wcUy6RVR7jGppGFJwPZSoJoY40VLuwhCxDzLAM36KHjo1374ZaifCj3oUxdBV8duD0oewRc3ve2k +au0A+07ADK6OL63XgoXD+2UZq6Zx6OQWPJhINw/IJIw0akuGgHnmDUoCsYdAoGvW8NvXzEovQ2I c+Lb7oaCgY9UnUnQYiZpVHh0qMGdYxd1UbmFCQUYSU65w9EGu+1/iCCK+8jGZPOS1F8paTcm2BDM AVOgrciGyA7EuIi0qh/WA5jyQelBEgVKL8bifkD3kt4Cf9fgWfnG4VzAn+qBC5H1KqSAbRf5qYFW wSOq+Or4OE0q+j0l/4bXxoRCX0AGOnBicqLWEBbUtPNFMZ84XZvqY+LChYDge9K+q11nEyiohi/L QxFOG5hHJivLJOHxY1XDakoVVG3O9R7rSy1Fjxw3V1AvCANmsn+7stSxQOW3Riu2Hn9E0m2f4XkB IklZLtxyJHn7b3EQOU2H4//Vu+r40VdGhuLyY4hTESquvR4sX5W3/UYcvStw1qxXkl3L7s+aINuM rSpWRRbcGuyBSBWbIf4kAtklE4e+GfhtZSFFsfQGPSFZT/oOW2zLQH46vGwGMmcm96Bn5euxw/OP 9cC4d/mPU6rO49o9L44RZGbZQfDU9tZRHEY50R15uAh71upKT3l/biBgWcrxXiOfPxMQ1jVoSitb 3eHK0+XBhns7zBkH8VieAJ/pXr4PMn0Bkjrr8namPaHdHjowqALkNJTxUTdDJHOrZTjeeCh8n+5P LyWJAQ1M9AQo+1whKJYZxSM5a2v7eHQKtRcji7ylzMxucu+l0DcyZPYHRYAD6Y4MNOuqRs6ThIlO d7oOyNr7pk6c282sU5ZqEXZa8bjPGmfCySqbPUs0PHgipX+b7Q+XCPtzFDgP9zC6MkUS8+F6VOK5 bcCymaN3mQ1+GN1FCV/Vh7vZgb/OAfnAB29Zci6pF+HtdamCzwJUjz6HtARjrNjb22UcrdLWn3Bi BdswLLWBCYwXAUWOXB8B8Y93lHuNOlEtU/wjpEKw/B5Qy12Jn/WkEe4R4xWvBvWwO1XzG5jmeRb2 KlsxbOGPg6mygnxGDv347kDbJxMlhmCsJRfsafxHGe8yARiLAQJ/od7XGIhC5AJFFrRJb1LbgJ14 +0Fyp/D5Jkag6xv68c1j4KLm5Rx8Vto5NK9bJR4J3WQR2+Z7E4fR/Su3jYawbPYj8xmgphefD0e1 ZNTXE6xAlhOaCGDmYoUc7bfnCeIGg2rybyvgihroks79+rg6+uCGU/sqORKxmK3FHPkx9Pvmv2ft OAGChnHozQ1VDtjP3fpw1lY1r+7pM3bQZs33/xc3+dEFtZXizE5wbKvGxpdLvdu1nyDi4Wv1VdFb X1vOVRVtoJr+HMriABTCtJqPYLCoox8lT5mqwC7nvyRPlI+9HKpi7JGc3teBQh17DmpASGt//FR+ KxPovYUd62cRH2Pt4Qvm7TxNLPB9L9ARotFnC9MLxxnjHisx8lTLWyxDMjpU3OEpMNXsmEvfBE2l 5vbE8ndgnA7iqk0CjGYcdKGppLma4fS1UODv7ew6RzuQAR2V9J10uEIFpiGFWHK3zyL8+Mi49q3d +5qiva8mJtcOvcZnSc1NJHpOT+RfOJWQdqDA5t4JKUwaVKVKpHtDYeLYCL8fPplmqwTM/zVmD4iX +FXEsVFC7j+5Qng3GVWe7LLpx1pZ9uhyfnf3SvtbTj7L/Vp7L2j+aHGT/cwzdEmT3uhL03CtaN+s H+0TQ8EgxeAW+wciKmUrqoH0Ee5gntsrNF9bUVRp6aZ3kpGoEk4SqYHaY9/0Iy47X0GIQ0ol/faZ JN5A8NS/SY62ExlDzYtqv+TXoYFxZvjBIL+wQnM+VzVPZXDHsFZ9+FsQnKwGg0mtx/oFIfryVDly FTUZbBhrIhJswZLj67kx8A09IC6/lvyHLwjMPpDSZHn9ap81yw2YnFHKMIaEvN2sGMm+VYycyBcV uGGsznuSjH0GGdvz/+y3Fu0DSya4eXItlWYoiMBJq8wNzQGlDVjWwmsbekRlZFYNtB0G4qyjT1Wo QBMCYV8ua/HkHFsk9E7huolJPF6wy7D5ciaw9XnNDdTF9IMOvkd+OPAztvHlHfhITPSg6c9zcRwT qWzKF5sj7f21gLRJlpCXpK1TbtHgI3jE93OXChatbSHZRslkRaxWD7h39qMdEfHhKIF33jPH6G+7 WSDTfP+xwdmf9x/VqiZe6gaiZHOknf3TQjb9BatgGxCWOO/UsTDAz3VvCduCbPsR+9p+US8Kigd7 uetpwFxTSkfLoV3DKtShjpsMJyOJkgNs8pkgZvif6vgw4vnvH7BlL9kWnszfnnRjPGosz81WWdjV UR3v4efr6PC79UjS+ek1ZgEvn6lBHz+vmDQTZueWJXHF70Wul1MZu54cXB4dPzp7srncN44u23g9 KXd/lfNfD3lzvpCKWFL+P6Pe+hwPrXwbMP2hgnntyFHBJLkWwAidT9rikyivdt9Xsq/u2kRM4Qtp aUxmvmxInnVbI/AkVSKEYD9xhYzxFge8Wn06+YWtQhstVFkUVdHgSYhtIIxnVeky4oA7V6BnK6dn trf0Uon6F/xHPVDnluDIJQgsWOKoDx+59wgFBOzz6cjjZiSj4Jr/+L1A/aEloD3ezhtGwtnoMu5n kx/Bnsgv+Glc71EHie3dqMzh+HLdf+yis6RONHJR0TR373g8jC4VVLbFbpS7ArZ/3xnta4E8gr70 ZxlcNWYK4aKR+hFYE+wpgUvjpJPx82X+mH2hBfPHTJ8BYihoIjq2L9g2dwAfzd0Ajc7rfFK3E/LS nIUaCnUGX3rO4neDEiwBP2BKeL/GFiLd4aOtvXtsnBGvjpxXg5Riul6hFTXy7HnNeKYguSwGcAzr wn/1CWYrR7fzkxPwDHGRsfHOHK0FcjE7v+us4K28nzfkKvXjiCHeVuJrtUc8YAJQoUR8jyC6zDa8 e0E8eL8c+dgRalAZNq6BajE4gsLp5sBVGVzMfin9uhksNKVEIpUHObkJoukObjByf0dTlpo80utE 54PSrCv0pJhMls9YLblQVvVEe1igQojH1CE1C7m2CP2JlG+r51PfWiU2xsQhYMFKs4ezSmwvqOjG kKtPxQfBhxxShVdxDBOzOAowljfj//23iN3yue4WTcQYts1gZvc805j2nn3wGBzv6+OOP1vr3GdZ IvYB/Z/s3J0/BlDaMK0EA66Kf04cytHH6gHlw5uaqkx8Fo+yh/czrv12x1I3MAPmMgnbx91oUTIm +VJiNUji0xhUw7CLs4f48rfr/rPaB7rvA3vzkhVKLU4PYYvyAUkANuW8PZAJb6oKtOxamOfFCqJV nDbAXmncxsoIIDd/ORV2TvglcHW1MHGDYhqpQXHzP9zAR5YxlYY+HjyxJmrD3mb8ph5/bKAA5RhX wKTeZexDK2aXFOw/JH59G7RroVcOPgEPgwvv/7wZOnRo9Cthv2cQERA2o9rDs8nCRElOq8ZThX6A ly3vwQtGMkduYNbgcec5mjQfS77TJrUVAZjUFPQmhjRfmlQy/cbMUzwkp9g60fDdrecHPkZkTXFd J5KGnVJENL5MPHX9YFV97vP3yl8Z25WFoWVOgXoFmE10a+ImQWINIBwpdt+z44Owu6Ivkub5hxr/ rFqqQ+o+LS2H0fvsLgBRwz2S4/N+ma+9MMvs3oNLYxxAtJUG2k6iw53HsUUFp3sTSCF71hOrkTfN xLdOR7/uXxp2i+S6yfdHFokNk30jy4dDwJywHbigokk4WbpTeKoiGHv/PvEruX79tSAzk33HwrAU gl0UvnFAcVQOxdGJmqaTDeiuau+PEbSjtLUoWcwm0/YVBUABJEjBPN3cW1JuPd0nh/iCU9ynySBq JAc1OlFxgMUKc4PKDpM5qY7NyjJg7bubhHt6r4spmsp4i0ZR/zKgT641o1uzeoIbnTS7D1u7WYAU qMPQFZEGh35qts+wxAiOfaBNPJz65rApl3TFdmsWX0GnXnZSSWY0JCCcOQ9pQuT1JfdENukTG2s9 S4NG3r14ZQJlLtbpf9PrhyIXboKWwqeYCCmJfC+/CcfIhBvq+xUQsSysL2OIVPkRQkFBDQ+1XFs5 OmvaUmcYsC9GrBoIAnS5eeZcYPx4RDM6o2uESRtaRdxbvP4J9hNLXe/yxpoLjOfSHmj+JbbJ3w7K DPXgXpKEoYFxWGqw5y7KBBliFF6t6C6Cs6xICrixvjyE/SiehHpZSkl+EmUIwSD9D1ezkwPJQjzb CCot/01jCPKQJkNHfq29pwdBgsnLsk9J2+LyozbP08pjN2ILCIHOKcddJYJEBwUqw/HzTIA8n1eZ eH1NzlkYrtA++KZG+d+k1k69HMmVvALT4hDtlVmcXfBbbXRj5NngSCH9/37DQjecNFYD4IhM5B7c QCfyoC3y7PN5n/Mef7BY+9et//5V/F8cJ/liYAszYniFewwb9guDuoWNJFpiVBArAADUo4f/NIA1 1xPJMT1b/LHzfFSiT40lQykNM3yJX0GaLzM+PRk0fNarxpgE2hTkhLvHsJK1kvByG0knsu1XNkzi 0D6JLySWv2WREdHZ+epWNrBjyP28z8cIT7ZRgac1Kyj9PpOiU9h6uaFt8liKjRGPFnHzwnR9vGc9 Skpk7NE+zOq4RNRTtlGRj47Ahd55Gclf7sMdSMD3/IEbLS+N4xiJn5nJTnNFSEO7hkzJAVxr3oah 8uSnmawlYKnyiBOlducP9A95bJmOmJ5Dz93HX9DT8sTOVndzs5lZ6yxvnvzKDypy7FyQm0GhD1/0 zGI8+nJPOMZlmesfXkkTlfvIJfRzC7ZLcjyboHpeq1sIqCtAe4yLawL+2hkJSHYeaGOF0YHZyHRR TO+vFUmgkM8WxD+wvmq/FvqIuR+TKiQlyt//583JsF1IdiiEcwC7p9rp+D6/HFQHN6VtVDedIKcG kws1kpkmMuBDxjaZ+Yp6zbmTRfDkgnnLiNa9u2T9/dokevp36rmQU0NSCHaM1Zr2L7lOe7eF6sLA ui66S4l0kXMC+dk4ycUsIkcMjWcTZ2DPw0gt7pwCOmrI/XR8XCKUE+sKW4GCMei9Qsa3IBwHOJzQ jgJ2EzvVzrKOy2oo/FA5D/SEHGLT+Kjwot40ORncaMhCoY4Clmj2CXjOi8DRsBacW3MKKupJJH5u vCvE74WsebOc302iANxZBAGHCp6JobPfH1h5GLIGNTElQsyPgkcv8i4n5bLnWh4p+nKiNWH8jOy4 2KgssCtkCGF6iq7UsOFcr4OZwe/i/A16IUl3EUthFulNVr/94co9AVde1JCAdLoaJqJaHA74Gy7/ 1B8+UpFx+QzXZrS6E15UeyKKblznSnhSfNWJvBrcACdiqvOjuqAxFt+puDBaXeWheALTBn4reRHe ElmtXj/SbvC4gtekXsIsLgfWhhPgHfQk8ET+ovjSUQcOszt692fKqe5fsTphOXwfF9o+cyj48BFB bQs4/hFP34aNtodVPvBkb6eCdf8zLndnWOKbYjoNzpC8Ladn9DToufBrkIF/iO/8PNuv9OwKhLPm kdtfkqJuyEfw1kSNDKlLyInTNLW2ePY0gMUjmLbJ4PPrg4X/Oayr51qvmIR9OSh15lnrfs2MoS5J UbAl2gKPxeUQn5sPZhaYF9FJ9OfaBu7tvNI3AoDlY2YIR2RwjV/PEP6zpEEP72OP7PMQPBHR2CL/ 7tura21xc41DVx1kahbztrDduUeIId336X16Dt4c7PTVXfm45PhzHMn49Qv0F8q8sFi/jo9A0rOS YJOdUB0Is/rpFuXVhqfnzIaJMON4OB4No+94jLMzygsJBJXEZ97DVVnEhDQdzmIivMyfyd+TywKu EWOhZYjbD8NQgcBEw6Y/iAyba+DPfjjxIVfArFeCeW9czumcM4VIVuAHNH8aY46Guq5ybuaP4Y2L Fts/toXFIDfgQ3JyjiXKuiXgQG3T1JXx9Dm32q4kj2b67Tuzx8xUocm3EaAI8UK88QEZN/qez6Ed 3nuy5WMm7JcOzFudt6Dfa7qHi1X4dZUFePQIuquLpGsinyLxitz4hIkduBWjh7RRqJ2K+6XDv6LX GP55uh2Qz/RZYdxdlXfCnX4uIytpRtunhfr1b1vnB4VMqxo/J8NWUBOjRHr52eE4LmAybuzB3NLe 3Ec3j+6dT92ar3AxgpnFf/XAH736L3y1hf5YM2jPMuI3wVKpMRMeJpliFfNEFH/e5d6y8mF9kNRC BXhpStYzOe/QG4QDJIzCd+x/cbVSoj0YItH1dIHbq1Vz76t5peSQzyw2C6FxD8QvMeMtMsgpX5BY /Ah75Ch+Mb1kz7gGxd9fPc063qgs6329fD2roo4KfOLduJLB58MOCdOoWHQYkHUm3fFDc+CsZDmy a3Rhana9RgpUQ0ZKNzvggSHIddw4uHScfYW7GOUa6eT6HRpce1a+4nBJQMUfz4FtmdnFqBjpSjRp wHYbuahXA3xL6dEoUTqOT8nOpqWB2vM/77gEp58MoHAolf2Sfj70ct6zKClxVITpgefYIE5wS11X viULTAqC+qkAAxBWAMvx7ESJ06TPkK0yOFKdqhLhC3/A/Qm3vU61ZwfFvnVog4g3/Oz2XsmTmLvC 1WewYLWlO7YNg+r7WOjcTLK4Gh+bcg+y7vAr3YatXfh4zbTYrGs9opnDQtR3xJYgq5iUdbi+ApTy 90MH8NZuh34chWjs4nHtpcbrACR+xJjBf8G2wdxwlhTwJ/5RoRcZc8pVsw1PQEyPZ4des9BeLSKp dVuyyc5Vh3XLxbE6xldEYlvMHgvyFOSb5W0fxPJbs+ZaDg7oSmJk2NGPIv3KbQfDs6Cej119dLPN OynQdxJbHnMMuZQOAKJ9wtJb9IG3hPPfMRscQ/mF3rGq0Q5ZXL+gRQEg+WVrCNE+UsSGDcbWqlD1 FxzIZn6VfrjDuFsX/Oy6ux3oV0NKp16C7Kee7pztE2/5hWxStriiG3xXpqtUy8k4L0NJubM/fIre LdKnJKT8cSAI//XBSYxhFjFcmkfmxWfFTX4z7Ii/AMuOqTpaYBOkDfha2e+Jpuca1rKeb0LvlbAZ fncyyAV27iHbAtF2xH1E7vDjhDLVxTVgRQ1gzMUnpOECoQ7/vIqRyQEuauLMu7J6gHg6uHFQkVkw zbCoJZfvGW0ydrAYvPIqrhpcwGA39b/d/lgtzb5LWnDDLdjvOyczuRxFmpUjAskE98RxLX+qdceI ntD8U8joPX+hdoo4OzFHR5RDvwIsxn7GxkNS2gzO1GW4PvkNvju7wn6otWXAcCzINriVB1LqT5CZ 3jo6nHpv+3TgXjSGinEOyQXujGhlhcFpVVqfRbuO9EKGcCtST3ZwOWUyAOPkVcREjSBSDPqMDPui QkLnwRRhsgyjTwGnWOIrrEBc2fgQ4BBnhyfNat7V/XL0nXPnwyLE56C/QwQCMMp6AuPqkOw4Ur2P erpGCJS29alCAcMr46auqioaSocgRWKBZYeKCik3PYl6Qnz9slcKMnrrjQV2Zg7P3tyYs7kEJ2Xq TbRcHam3FzbRs11AAsY/PP3O0GxPtvT7Wv2wrFZsPZ4syLZudRXezTrNuMgKfvc4OmZYQ1/WGdFx 62pEElt9Gp1mnAeoOfcC3r++D1VffICB1hNads3oQgU8IjIquA1k5qsBZMtQapCBcDOw0Tg4T/fQ vmjfhqA+JTt6Nh/8MlPsZMO6bAlquaFCkSljMgM4FW1n9Pz97SmYc4SZYQPdGMvHmW9SEFNl4RnN StZR/WaF2KqNqq57H/cLz+KQEc2vFjrEzj0BRbQvH8IeOIihInIhFRVEc0bDjv4mlA9B8aigqpVw VeK2UHO6+8OfIPpQRozHpK+PfA/IFjOV5n3BKcvaAz6gRw2jtUaAmNWankNYonaPu7gBoorgKQFs xCfbvBGoC12wN0waXiFT1LOxudnSJCAp9wO9fSs6ZrKHlAo/iQwpaQ54rqsY8TpU5qQGeUXwxKgS i8cTvWyD47XAFG9EvHGjuUqQu2a+40HiSUm+C5r1QfiarUDJlMdRw1jIDun5tfdePMZvzVBU2zD+ IyIAcn96N8EQhmL8FIKHbyZ9hMPAi+QfNTTgXnWr6yCU2WxDKKk2h29O97ez1bZvJ4AjGFh09lke EkJ4si69oAAx3xTr/oQcBUDR8puefN3bvBapCIAo97mQ7eS8pVYCVy9brB24lAb/Jux2SKk1FkJl LroMEKFOBfBc50ZkViesGcSb6KiOJH4RFtQbqOAOkctdiidzb9XCBeSpIcQdguTcMgsm6X66PJcJ 9dDjHEbf41IL6GM5wDvdIZ6GGH+iDOESFJ247Di4lA2FQOUl/3VuT6E6K2dJ5BjxOiE/oY/qPcDv ZiqdLnqnfHy4EJHtKWFmxROqBc4RQW8jzJMLftdcuMPvnF9hKSgY/z5TVLNPrGFXOhF8dR/UV52T TYvHEQLH0mZwvNFFDi9QHUovYDK09THErXqjLDNpEbW7AKEdS4W3E4hIWlZtdgH3K8LmIGfoAADQ IZtSL3J3mVIYYWDBk+7nzJD5m7vTOukHo6fMfadN9y0AqIj+MG5DrBCxiqLgiEo1fx9FLHzw6Jvz WhH4vzdLlZfxX0vDCD5mf5SY2/xXAfoRInrK41lXsRGRlZM1+qAu2SESGNT61YzotJCguZ26rvTP Ex/k26BUCtkK5s+E0ufc77/TovQxXWGdjUWvkVuA2ETARg9XnVjHdgc9jATT50MfegZuvOrTZxcJ nV1HSLGokMCEAEQaMiDjeIApWcq5vec/wwyodB1zl4EzhXIuf5Xn7MhOjyJJqXDjLJAeGQ7ZWD6W kYp+GIZAf/vYHXVof1jrxqK+pBrVITD82ead3r7SX1DPSJVQhZ3tHAxaYnipCa+w2JFbkN2Fm225 hacgTNqDCMbw1r1UGwWjHW1OGEb0rt2oMxcPQ9hyYMN8kIMsSsdDbQsMxW5BlRJiu6Lj4EtMhFcK CKHHHMS1PFXxzwQKqlsAR9KyvFnyJGGZztwHgqDznXXEOlsLICy9XVhhiXVoBNRwrCFSQXkLpTlE /51AzqdhKVIE6cz+DI/fzn2h/phA0se5TCg02XGTUEZXFbhi2Y6qNTYwX3Hq8CS7Dp6krGFAH9+R 9Sg11HNlxW78yKTZS46B7MhhyVRoDe9zIy9jnKsaCe/SMvFLtR+qDnRneaWCsLcPmC/qWbIRYiP7 5lpuAKe0uk4RFL1ytCwAGyQRNpIOtLqL8sfMtfU+9tjDmt2FDYDT8e8hke249Lz4Sq+I2W6I8+fo KdxNlOsUoA8pq+Na1p8G/dVzKabG96xvLyZA+qJCsT13C7fyke8Xh8miUlbk5H7HhGwq/iTgBOlx dSr04tOJYk1DVgj2A/9Ca/6WZ9WDF9nhSmIXaIgovef2neakL/0ZnurshDOcmhG97JlF+MtbvLTT 2QcLqOOHNtXihBonqcj5QTc/hCjsSXqZtD1jY5dq++Omb25N+b4pTXo6/Rqa05uHiJvaq5T4kv/0 rA24nbdftKDoUHK3YtviH1EdwLqMRiauBwqku2dwMi/OBNhdHprrtBiwsMiDNtHBbFfR6A5ebZca 81YFSR4vr3VUHzU3VtLjQhKMcRvU43w4yKRjB/pR5vDiLkHFAnaXcCiCg4aEtAuI0LUopXQWbXC8 //xcEORsPWqJKDuEuN0TAn72JtncUZa05nzQdQ4vm0kGN3YVjRn3e7iVdEHQ3f4jf+sL3W3unScL CcFUgcLso1uLJ6kglJt4F/k1f2KzZvHziJ7gFw0qo0EzD5th5guvMf/RfCZ4Yhfbe0MFoMkEwpKU Ohm2dFYnsvDbHYcwykTlPMDTRr4JBSsGPXoLVMyUXbLoreBcZmALoS/PY0S0VCjuM9vyo4kqEIxM Gl779sUO6LokXbjZZskIqMUgn35fOOxneX7CGfMrKG9MuQI0LE1+a3AeN8tmZBKKezPb/eOLaPoC LDwqJDjRHydCBOyMT3STAcht7QeOIbC2wKr4qkXoSL+z/wUVfcHW9iCax2wVPZxgTyVI8QIX9YPr FMy6rt3yN1ChTVv7q0lNRVMoLY/25OqximDJKlWKX7s1P4FtPhrR8KX+SaGY+D8yEuFJ5SYWae8D fqi6SY3IwUoGNzkshamhK1qNeG5viq7+JkJWuxi2K0mAIRk7Vo6qwuzZQMrSmBceOcuUKqMDnptl n9kRfEbICmbMc9JBxVm73E2yiOzy3STejYst877I5AxmToCBrDzYArl1X1jmY5k44BDNKkq3F8x0 AtGweQAn9MbiWZbQDZ1EwCX4cKr/rqL6Jy8SGIvMUgIgO7YAG569sJmO9M8SbSm3B99zWM7agRxb Z/YUixqswV/N0vyJfNVAbpmi7A0wD/4PQCm0VcpYlGHDGlxfXi/TXzBgHuAvFx3GZZ1oR8u+PiqY PoBKELGMWqMuQ2/+Ta0ukAUOpOiXrZ4w1RFxytqQfS8Dwu3ZnIBmrSZbwbMjZ4irEFsVCnJ4jsou AuyTJVNurqLCj1h9pz0MHVADxqqXB4724VAc4jutoUuehN/kww3W9h4G31O93BNef9FwpeRC3zGc qRVJv/ps0PveFoJuAdqJVLjRSTIAUSOv09TNeFaLlE9uQh5HBDjsouKNYk1p0s7ZQKPHjmntYRR7 1RDIgo5kqZ116vMZruiLc/h81Lf8AdZoanRc2EVrQkS+QFSo2nnaXsTs3BfAK4zRtNOu3EuQbj2M i+cjW9rdlZamzA9Rn4Z+wj4SbGydlRgQBPLR+YvCxEaov7SjHsG+w30TBgwpvIC9a2ZkublKe781 GtOMMmk+5NLjeMK66fZGyjqw9R/4L5PlzSydujCfjBnQB/n5WHEsY2Y/9KPyUbgqlt6a18yIfSZw 7HSW3bLYJpZ3uOhUGLlF1NQX0eIvHyoI/Wxf2fRxOzA/PsvX2uFe/zQjPH4KYZaYDRLnP7zgMGmm 5jFDcMwjDCipTTYdMO1wix7mVTeonbF0ZLYnCc21begWazhU+aQyu//cipL3RlWz3L1Pmo8H9E3+ ckqWdjUhMUmRrdcW+9/pa9f9uRq+CNcoq0iXU6RkzcebJVeqj1n6IqZt9CMpRA4XT+6CF7Z7ENT2 F7cumzO6m17RZIAfqsuBfj22bYsR5si4jfxYSONje0MUCnzwMpgBOjnsaDeeHUzZMKX7kdVdJzor UbcVprSHYkkEiP+ZF445sKoGt3W91ipfdoXIhKEHkrIeyhNWHuKhnCpZ2qXmEnNwhFDd9LzIVPCy oagn6JR9avvNjkO6E5rQ3H+Bd+c9gzug53OK2MiNMhnjXa5GMAPQsvPu3eTN23DxXaDUco0K9mAq OlwMYxr6TRzv4c29IasGFjFb1SjiR1A/HmjQBCWjdC5cxjaCUeW4+AO51fU32iYw4+fs56UStadG OTTg60ZAZQFNNrGJBLhQ3zHOwNAWRiIAeeTxyvPZ9dyZZYoq64TV2r5mwfhExJzIqi1L+Fp0LFx+ mFYxx6rfx1M75QFNnkC5xCA/oAGQFisyv4pbh/Fm5ci5vsz1AFGsK7TCzZ0CpuAAiIxHAgyFhLqa JnoZtZWEwWZdVaH1fK2o83x3TZ9qRJOIRplaSg6nsK8rOxAIyhbWOxnCPmJf9N9EuefR+c9ZJ7HY 5v/GL13HKPbq3hIvMFYd5DfnmLsYKBCBEMYsEKTtLXRHlGIvOlcm4hmTyzPWFwoDkQhw/p9BdS4u J3CKvc/dtIbeniojo/0jgoxfa/YJcQARXMpEgnJDitrUoCfUUN9rW/tzc5i0z597UNiYqnSQo6M+ VkS4OP3w12V85YvOncEZL4yl33YRdVMYDLiQFG1xsPCJIIa7Qpi2/UbRpp41K0aqLIPlGDkWpwn6 4rM+qKm/g+3PEf6pt1fIf3KKcZHdt811FDQNPccdI+rRtaJLYUiMrK8NUL1KClKYOZo7Utmnq+9N rF5pfgq2nelvmd6+KATc+iJw/ICT2TMD0ZrbthlqvTW0PxzuhglLO2Uc6bgwPmu5kashkmuMZvGh mO9eRuE4o0gFZznqn0uGmo3RkXdINjNZXz4KFPf6r0OXNs+iB9w0xJq2cUDUZfhBQmOVfDKwrKBl Zy3wNak8RSTMKzc1v0+9g6nfa1M7NZZ7f7DSx5DkJUWPwu2B/6ho/Cd9by3S3owAYQCKXD8isCMu OtJZxoWktD3qJOtX16/sIt1WhcCF+V6fWQeOjKHtC9v2VpH831at58bWWD7CtZp67IaWz5f1ys0g sw2JZ7ZzRXu8tyKww44KHG3+ZpzOwnNJfE+buwJnfHplCEgHQF6iE+s6kgcJFfv5Bugbg+vHU7OG bvtiVEUI2wBg0tCYVwTL39eEP7f4Jh+eSMsNTuVqASwAh+3oE8ENo4NoOUYauRqNydu/J7YqUkVg i/r48twYkXpJlzH7kZXq9L0J/0V4TFuYPwTUC2qL3ZQxvJDHZ2eW9DOVE71lzkxy02ryDwsZ3u61 0K2gP/OE6zBVPStp9RRx2vHZLFL9drIqXGmfWIKUldi7v38SU0a4BoMauGdUB8x0NoxuaX371tTb r7fysAFHstkJoBQREHxvPvcM6arr89ym4emLvlBlFunh43YmeSlMvZO+iVZ1r1XBZ8bJkDC/hqgx 69xe64kH0b+Fk5Um2/EyFBL3LtFuApg79PAKy5NxV6EdBzuule2E23m12h8BQKscgjQtdmdlxBDg fQn/WvL8pI8PFCs1YPzd6lOKkDfqhZ8PFWGAwpgybFYvs2poXjIfWZMqe3BnZ6u/OE8vU63Nhd5B drVJJIYHxciSLIXbEWXhquUbKKcE2iDlSjkaOLienf1xOPwAPuhVNykI1f+GPkZ73OBuI6Xd2J8Q kp98BX2XjJG6nXBkR+qynCqNJsqui01tbqaGinhJgFCj6QTwF7/myOVinz5jOFkt72BLGMRN9w/N gDyen/K5Hx8F418rv5AH6xGYruWjQSH1031Lh4g2k5moomSUvnaE+B9Ll4ARGU/oWm2VnSCYzPda cC0qZONQB9fiELEYr80Bn+lM0Nk5xrPKb847tACDWa7QTrxZvwG3tjNqRWsJsXE4CX84NsyFMtwK 8m8i9b226dmFogdYB85oz6lDwAPd55MWsPAS/JmLwLm7O0a0eOzY7qwwU3s3P3Gb0LtXuvjt6Cku EbT/0HIzfMeucINg9m2BOBGc33tT+t/aVtqJA2nOl8oNzTGjOfoVaqxzOufLaIY2aha3qMjjlsep z9ZdygtF5JHZGM9T8bXpEDc9OljphqcPcXZUc1Af6K0REDbin6IqitTviOE9T6sbl18ZSyGnRjeQ DGzYC5X52w8VG0VUN51ZsqWSP0v9wKNtRnI/CJepVw8ILE4DsF6BLYpaB29XzwxGTZzka35nJqyd +K/sAfMgOUVEwvXqjIyChgVLYo4qsMo21BSXVPOj8GztzdshtVyIjNLNYLQHVcbDw+H2KLat0lKL gjZJiAbFW6+IeDYmK+/u4fSOGLbvV1r6GVpd5yOXo3cMI8tbl9AFaLtYBzIRKhApTtvC77/ED7na J66/56XZQhqLHIefD1wDCswkcvUWUYsvgY1juCEtMFdN5lyZ0qMgo6Peaj8xGxFRZC9hEaXjBjUD EXkXsGvooZkS16fCuwGlKYLjd28+ByadyBf2BUKqB5N69X3UjNsDOlJFqb8gdnOdFrWVS2fIZk87 7vDb96P8HKEf/jqBwe/UeAL+7ID11wwxpdvF3pwj5oBHUuQdQxziHV7lr/7DmSVwI2QCZ+n1c0Qm M/vgzOcFxtKirET+YRfLgE7338jP7Z/3f5KC8i7KoxbwtRxV8Q/djeuWZKY49fnqSTvkmPOJ6H2+ 0irWdqRU7s1w1IlEPcW3HOiRpy4gTgixAk0xvnrHh2z++WvSzMHp6gFdJJIfONavrHUx3VifLkQl GYwp8icRgFZoIdF3vroRzZug7p7hqpYiLKHnAD2ukQltNj1sZc2r5OwQ/QXxibFsFuZXcIBew+4J pMQu2IZ4T0eT1iCUucUtMezskHlVpR/Xj8HA2qyzU7oiyxNjVd6ETT8HvAbNZJOsq91xPM/OzLRg HrzoRSowixE++fQo2bjulVJOGJqRf/5k9xayygKjLlZVQIUung9+tzprk2ewgLWUwCxmhVBjuEm0 PuaDOpt9/CQQvqCtqy3tt/Km4zg7fYg0k/t+1mSSCjNYHXHhbLpH7w+ijvu1sMtsJ+an77At4Ys5 QEj/0EXoilHu/mkRavOqP8ZXJyKCmEN03izP0WEC/NEXCsAcP55601wB2vkIAYnYvhZ6ytbPvQmj b7wIRiw535iX8mCo5Zw5TSs2XAFq6PecOImzBdJKv4Ti5T2ssQNfaelMFFk8vT84HxagkE4ZOh/V 0sxKSai4AwlamRPEkAH2JKDkkhFgOqfTsrvqY/mdeyTjWBA1Zulz5Ktq9uSdLbu25ZnKkBFgDWyX rfxXAgECuJ4L1k2M85hTOYHDffvJXaD2xNF4iEaKYFMNteX6uqCNHejdLf4pHuzB7FcorCrL17TK PlC4IX/TAd/spRfXPC/tz29oLeY91o9jm9NJ2S44GsRgS5ktNXoDZ6S2Bp4MW93UR8iAdia0E43/ wtDqrhZGM03ows1DzX2DuJjdPwvgzmF+fmSO3KO8YXaT1zbGG/94wuEYY2BH8KVtkcaczXxIpKur tNU3znhSaacNA6Kky6r7u79VJdCFPyW9RMaRl7DaSsXbqPnUJiP1MCfNWHHQy0CcofWYIp7r6k1V UTVjwnS9E7/zHfGRNGj7mJPH8Wky/gw/zjeUOVwmT2W7B3GlqKe1Is6gmxJ1Cw1PintJoOXs6/Mo 2SJ5HtV1g8QAFy4ErNKmBRepVQmUPRONl3aKnz+jHWrFktjziEFP9nsUaqaknGhxR5/H9rA8hzS7 8fRDkMLVqOl9xvJ4Hhw7UThF610VpERi3mptwrUnAcIFMVTXvMMRe9wuS/XHhyMOs/Z7fpfxEcfa 5Cu/Iit9JNTZKhFl5LCiUttdrGFSpUGzVXqCU7yn5Xw2wOwemV8vXbu14bB4T2Ekj5L1rmj3lxpF jqrCni2BuKuz2MYCnUlz17/eLZlYadVs9KG3g/Uz48fcx2batRz7dSZV6QKh6ix3eFtjld8I1WqA a7FNp0bfA0Yz50EM74RXePJiAtuyhag0A55yxaCYJR/JSoGjGfD3f5csFcOePwUyYpTQVFVxCI8x gAIV0jf+PX6lR4iSAAh/7EDH5f+mbeHmE3E0zndSEb00Fd+0UzD48VW5eKk1dJ2VEtpIT1bjWbEW esxTldkdwgwLBJi5RWqpzA3w6FhTdoSHXmM6t5ov3hvX5F+T59kt653dDIEOJ9ix4BXRIlOlF39R UgTpVsYNlsz1rDAI4UauTewSw3/HyBtu+ov0DOrLFf7LYuZ+mmBHfLvv4eoVH4XT+zncA4vFprhI TnD5CnVg3+yeJzVSHoHnyuD8GwVKdheyXPv6hVcSmC4L3DAesgDsRmwMCdvMfwwtPO48h5v1qL7s 6tKlYwNmU2xQndywW83EPDrpPjTXmGX5WXPSVq8UHRwGk1rLR8fRenBZ8Ai4tkQmgE7lNZDJB09c bq6Hw/WFsIQ7E3Uw/oRJmOCTL3VhdeVc6oCjlSp0jQIFCfYYR8G89ZkwafCD4Kb2W2DDPegvDMCj 88ZL3HlA5ac+B5q7PrsadljFWyPDqQZtVw3A9gKVvaAVDvR6khcgj9sRV8IEd+Wi4R8+dGniOTSX w25oWAd9GdfcG4+eprAFJ2e3/SvGRZM5EQlRNZXNzNotgOLoFKAsSNg7HqGJRwABzIsIggGOrjaU mVfZ3auSSw2WAwmqoUV9+kLAEP3fHOHqGeJc3aOAINdsOU0jbE+b3P1f4aEVGDeJGllQ3ePmzXLd FDLqVMe4yvW6DjUYCAxEgxuVI8yQiJS4Y42a9I63QYbYuV6M5uNaC48+GS50hFbmsOk2UXCLl2iF fbIjSSffq+DhsdnfcWMRb0oV5Zmx9M/ViW+vwgRKbHIkGKjjoIoH0YCh2qosPD3S+ncNb0PpcNWA O4GCDxPD0CJNaI/eLLrsoHxXX3IjZ1FghwxStDvalxrXU13JoOqWo4SHjRC/3U8FlzltYsXIjB5U D8GTK8+XTtmBcx8kT3nRANzQ6aY+bLK4IPTgVOQf+SC4jUWbyRFTFi0ic88aec2cExPv7FCdKmp/ 6shx5MLnUKe28zgLuA6BT3OrUOt7DP5WrEWtJflzg7rI+TXuzk8uVCu/acNvBhCsK/pWHH1tWkxp QAyGL1glS8OOPakFk4yTwK50tgrMzIcnkOoFJoeCS7JjX83lQF1FeVZo2V4HdPzNgUDwn++nOuhv ASjPmskCy8P/msFxttp2QreUs19THlnP4FVl6KwlRkl8GgMOnSWb7POHutOuYtMqSY6IIevjFpke 7cjz3GkhDJVRt+OfyGb/Vuklc1HKmMTWDVVVcZzm1PAxzUHrucl4RJoZaxq0F0xSUTJ9c4P2DpCI jDvlnfBngodba2L6Z36CfiHG774aKaL0BVi001kmLfWjNcVKREQBPNH8OXawmWhIjEht4Bowbp// lCkomco2Qx4G3Z7gOAuo7BRZnlLKoSfEJLii3C+/s93FOr5xqaYqX/0EEPyCdDodvVY1QKU1f3qy qbeimfNhMvC7AO5KxFTjpOohSJKAjn0JzW/xkhma4dKtB4/bP22GX7GAifags/c/5FAIipV0SIrS +0J5it2hOTvvyxKb3SAJtlCe7kdL1eMOAIpxiRXu0zxtp48DiAS46DJwAGqUOCc7D6MjU75C9Exm +jfSRbVA3u7LHl2CUIlsbJA0Gn3JaFs3e8HNyBfFbkB4iy7rh/GoiMoTve6IZ2U8Gkabe/qblYGP t+6DCD7Jz+6Nrv7HTnefRyZZwj3Ts8lzV2g5LvuM6UGTwOUEH0S/CAKzqFXomLax8hPssGCHYPBF GMhi1wxMBsLd/rESbH2wB7uIqjVOEauaLP0zP1n8r9A//7pxYHFkgkO99PzG6OloQLjd2PWpCYbz qfCNMeRgMoi0+7rYc6ZtMEK0vdpOhCCifWKCwSMvoHM2lFexeS3gD/+4MSodq5jkM9QkCyfiglwL JB2A8J14jq+IQAXtPeGBYTv//COvUcuwm+OprTh5qpW6PXWBRIGDSnlNUe6U0hR5nbybQT/Hs+sZ QnEIbWKdSVsGBUf0d5GgPzKclCACOxENpPetuNEGKp+uoEHqtB809bNuUkQyryDcNFeX/Rz1HJbP XcJRVtm/zmlIUZ37OsH3d0NBfbPvCyshIDHsl+1FOGDIiTueVEJlh+jQ534Ub+XiRWKFX6RebA0a Zy8+U4pJEub3XJovSPA9mKz9ChBAZG9VCA6U5dWwN/QKxBcG3krfD42s9vkPrJaEv3CjVTqNdwIw FEnkUaJt5um9trudpK66R50rEgKFgAumbj9E2ox+QHqw9rqsTtWDEGGnvSKcgeQ2/aoDQCR5GlVo Yq/TJBTCN9w/F2s0foKQPw/L5mQYRUNGzBZVrpakOWlubkmgNoGup4mpwXf+ixhmARjK7sNY0MO0 gwOsTOBsyCA/4R35U+kjuQMwOljWTVZJyBlHWyWVWLv6noELtr1UY63hhD6j6fAo6lNQXR6DVr81 VKc8e5ZASgdAAb6YtZwsFruIV1Si9BWZgRJlkyy6JzoriGC/EQC6RJ2f9o/BjsMK3CS1+/svsADM ilcwngraVZ6nsOK6nxcB9Ongasbdh5hzC3JBVW2F4W+SmZm4mVMcsl6y0k3ngSBrpyn1+YoY/8vC PFawfp/NE9qp6era8CnFNTIiE2HOzcuo+aNlIHPTrA02J7AHqCuPs47K27WTnG2up/ZdCIX/Sc62 vIMwJ5gVQJO+VOE7NJeFOSngDv2IFSZhxXCW5s+eTOV9tgcLYYHNUOFKLjSDTLRuOWl9NbcXeHKm MvUlMXeFJZd+a0zCZgRYAawU2UbWj0tGVm/dt1C6zbB3QfFLUyAzpVRmzV3o9voA7Yzx1bMIBymy J1dP3Nh1yV2FeD+33OpPR2pm4cLG16RN+m/mzPICry5I7sEvDNcsMNjzeQ6IvkX/UJuQTSIFMfNt weKRvSAYmOhnWQMQ8iM43B//JzF3No9a0zXMkx3NBLXB/0mBM9Y+udeTwrTlW7tOhVS/N/6FLiXe ivRxAMmkjOuZwO6bKdgw0oopI2/CSzXXVt4rOFctHvHgCAgCe+f/nvO9jrirSzLQI6pbqtOS/SlW NbRmbxGmIrdhgsBIsTopL1aFLzLPiUxINPLEZQd/Q14sbnkFbywfC+Kcw+tbLNQCrLYrZUKERXQX /gF9ySCsiNN9Bw/dKod5NIYPGwNveomZJuyCIHg9uKwW+zrZ2SSQ6jhtyBE2paqLRazwwQtG5Opx 2v82i9ln0jgeskYZJHIkvcCkR/rqNUZ1guv4DGO9eEpm0JsZ+yTPXHbEzgTGPnDZnmFLdCxoWTEA +4x8rd7rAiwJ0AbTbUxZmoezV1qhmhXzuaZfe1KYPDQUxGS8tbCH8jvjVxP3GLF0ZYdcJpIm9R7H NU3AqeUNIpBAGM6Xgy/nogfKs4S3f05hea9xA2QhBvxjDvMKDXQ8V5T75DTfZNpetJrzXIWr735c 4y8v+e4rZU6z3K/ks9V9kikyZzThktSEKrqfSEAShK8njRvFLOv9G9MCPCT9atr88AZ23uQti/+O OgNaEVpWMdgzzjxM5m/wB53j/rH5Q8fG5AmMYn3LMraAOa/kwNx4f2a70wH3hJPqkecKT5i3vPNW B8JmV4UZ/k7daskK/mBPPoY0GRYht6FWREurfSY5abRh0L1dKYVOGdm6OU963dJK+t+ZWiK9nmMw 05YaS7rrkUbbnqLnAt0SltJmQe6HjBDT/H/bkm/y8ea7Ba9/lX8NS5R8U16sD3g02UHCkdjXf018 guxHLzQ2l0e69AHkisJyiTL5OlzKth1G+gzdtuYKY+fFPXeoLd8DGEYXPK5x9904C0NA0O5jUT+z 4V7/w4moMhfBC7omLZzkOIw0IqFHqumVkUK7zlgIhaLtYkxsKyKdsWBiOKomMACZrWFE5xjLDSuH uXIqi69Zo+NQ3cYINRDYBDWOjeQbVZ29y9w6GnZTdsXjXKOwbx0uEywG5gqZvBlPqAc3oqkFbfvW J7hKrJbeePIuUKGhTHHVb7nO9FhMCGh/DzwTbG/9gMn33/hItQaFQB7aqi576QbHto/wHGEP3HVV MlLXrxi2gITPKXf9M6L9HYHzJvpKJR4KAO+G3Eu+F3lq52ArHO2qYZNSbh6FKckPA0JgUKxWeZbo Q/3j+B83m2tyDGj10EIM51IfFjRV7ovhNwkJ/DgG7sO3DLB62y3NC9ZFsz7KcO9ZfNNiiJ8zqWTE zxx3vP6fcuUQt/dVdlr+kS69qdTtNhObgYTvCPj1Nlt9LcE7QcrwFrUIv2cmUCxaZLRy9uYBzFxG mCZqFIAtvxtauAkOBL5KzoxXO8fiv9UcZbxuDZ4E/nrKh9fdt+J3Xag/DAC0GJRiQRAZU0TcJDvL DveriN1/E9Ta7GArIYyeIurY7AmyQ6GyY4gEXWcOr0+EKhFtSYQTF6KczGDDZrB2VAVisIMnj+N4 zs7YMQglFcEErZJLngkjksspsRSxBSKgu9UJ8zBu0kvUE6zSG1t6OtdA9MKsRxWxyG8g+uMAcP0r DYLUNpt864p95mGJL9agkD5YBMaP9uPVavqQzbXm+UROI9VQTNk+KOve/VN9WXCw5bEKLLnZzN+O hj5AF/TI4sgT1EHhefQaN4rL8f7NZieuC9Nh+U/NSL+f5kwRPXI2+TdPWcMDyyH3+xvIdhAyV1lD LEsjF6fsTQ4qAdleweF9vxuOHb2NcAQqXhTYm5YZ2V+d3Zp1RLLdKV4yxPMBkRhx6mTufLnWE9H2 VMdjL3ELC4wD8ZVvOY8n0dULQvLToIF7cUOy/EqyIrlYUMAl8BLIOjS1Trfamrx4oALQVOFIpXA4 /BqDZISfuYuZMlBUkFjIs8lGzTS2AVX77oIJ4+SVoyURRCzuZco06GKAjeo2Jk/UtAQmYqLtmMuB n+cIcVXfiKxYkC/726cGUJ91hdP/rC5MwGALDdnnFq0bK+lMEZ2q/SVCO6h/z1Q1i1h97QKet3KV Zq7uKprpB+lxlYhN0JhkrQCP9qBsEaVYeSylaXzYQZ3aMtt9Ci3RAy3NxxIR0gLANM+cU/pgHFp/ UQa93H6ik+hTRO6AtBIk90kjTyjC/v+x03t49BtQrga4mMPCbpSunyIpqYtGchQ1Kd9XHNeOrJMe lLm4Y8IfIZXhpzLceWm6AGkpxrnILPJcdDfLqqr/nn65MJ8QUdKqO54qgNU7sEiQV0NKDSVj6/gc 8vZG/uD79bJYP0mE6S83Fy8HO09gquO2evXZ8d5NZd84kP/GM4JnV2Ua1+95GZ0IIitWUbI4TwOZ b/7HqdcMMZo2X854RM8MlX7cQ8Hyowcvqq6YhNUwvpDdTUYi2/rOQqnWaHdqNZ3WN8691DjY+IeW qrDfnY1SPjLnvvbseTQnb+38r+Zg2rFB7QbfS0B1/Nf5YHcvty5tATlDHFcX9aFjeJHSa3g9ABMN wzzYF4p9EabsDlR5I+HJ7UK6ItIrzNu3q0hEPKmWeo6G4KHmHmx+uRqV+siVJnXXL1uzP18qMOKc lXRczQklXcuUxpr5nYv1f73MFPZe8gW1/eJfO3BDZN33C0CeQSteDxUHXUJCozo0DZCtbEfAPR55 icfMA2mEMAw2mdtbXy6Qss7rm2xF1DKffUvtbkiChoLneJ0jxEt40GIl3MPTiHvhbjBwIoWkBwWN tV7g6wYDUzpqmig3jORbEKwqMbFX0A21yqoXzhdOQQiP08COwbRg3eLaaBgqEFVnaaT5DbM3Ybkg 08NWBHqnLZUTQEXG5V5/yNq3XwRGsi+oATL8Sr8skc7sz95NSJ5hp06ZiEfhPAE8rdsrzUCYJZUn UZmoK2/uQhkHrqI6M0dJnZzC4eYKePJNoMWbcuIMmGSJqVB9W18DM5aoYohsUWM4rq8sSUHu8scJ 8ENNYsIBPGVWyk/KsCnttcq68Pn29lx3S6U7m6ZjYij09Qzr2jakKDfk8E4nghbhLD8ibiNa2hUe yNacndOVGV4/EkZUXieuCr7afiNHg/5KqJAuySzCRsOTFHS4b7w/h6YxowYOxZE+mCzEHUIJVE64 yb7eF79UV6W5Be9UlrCZnO8FbmAJFy6XcOkJuyY6rX8ujUOzN8kLYte8gahjnqVoEQE5yqX7Rhex cXMYBMveXjRqprFoiovszIEM8YYITW68KDyzJ72A0gZuAaIi5dKBaOh+H7H/3Q8PAWzJCc1zrYh3 WeyYVOUSIKkrGVWHe4CknsyZDuX5oWXON8YxPpu4dxf3DOu9//kCUISYpw6RdCgG8AjRdOtpbIuA OaszBMUV51zF3COQYGMYVO89q28icNv9DdTjG9FZROyIhXcjn9qG5Y13TxPDGKCcPGwtKv4gGiLJ bz5GahU8D/tHAx+/JAtkUYeg9Z5tf7j1YSFZiXKF/0ziAafAIxv+kX8r+5VPok3tGnDO8OO+gjVp kaMuEtB+TP5B1t8NyIlUXrE9NDvmvajFQMQpbvrtZqCQZ9MxsT8/EyDmniekDmWLk02diSzX09/s MQFCA9MxD8wEIj8hF8qVpDXTGAwIrk2sDC1WdrjiMYgtPkikzY0pROwM2RcNbHwslac6rDMgYp+y kZr37hPLFFMwcPC2IJ04ne5x0WhNXIGl6i14pZiRUAVYiMcAP0UKVZzBmw7LKpNuRWI2rNDNT3dd 1XuiOOqXRJVb0k0R6LzgUhIFPEkEo+XoBAUZDLRxmx0d/eFhxsbVMjpNrmh4Ge3Mx+ZhnB1zpVA8 BqJwsfT/byda83uhQF7PQArSmHe/CGfi5EAcYss2T7Ka0o3308Z0TfmiTSOJIsuK1cvfr0u1N0yE RszSX3s+5FQlKWYN4N5Fl+zWwi1ZFyeQdLabH7aH8NtJ+Rf2OKAM0ABC8jWJXqREHEVWo1Rrcap8 FzNciqX/T9q0QA3xKQh8u3sjha5QdTcMDXx1aXpEDfQEiqxFT4tzzB1utVnQxZa5pHv9a3nQEl95 1+wZ9u5j3Kz/Wq//Ej6KUkZ3pV+LptFTR13smkd6xvIsNaF2dNgNfZ+s39iKmScnl1d+8gbH+QDl 8xhz+HcfcjwfmDgEjGvl/GJ1TSEejy5qT+7NuRBTxZvQfy+M4hLkWhrinzh1FoTJIG1uRZlqGa5X cN7ncx0zt5a7jLR4F2bjb7MKyJE889mcoSIC+aHiAlEpjLjrUgQkA6zYQ5UMuWiL6A70PPhIu0Iq 72fVwNsHiRETncqDS85AYSjQ9WKOUp01qTxQaQyil+z7VRtGxDZW6Tp4AzjUYL4wGC5DPbcWdtwD cIEFPKJ6XDkDutqC4TOQnC6nJal8w0Dh8413Hy1szOggpbaU68J/ts26J3dGfTH7YGsRnWy598yV E5KJOklbXbVn2waqxZHq3FIJcF2RRbDvzLyunqVfGVI48eIg2SjBTzV8lBuFCv7pViB63itAWCs2 VP/KrQc6V11rDrhLJ2nJGUGYzVBnh60iJq3uMNMhsSZKB6oDLjyXtPRVY9kiS/KTou9QMMUlw3Tk VXZdp2QT/ocJizbDRE7KqbJtIXsbYx9kHb+ONkvlmohdcgl5tgjPU0qDAa0eZejFfe4yBDTGGj/a DZdMzl4Avm/ARNYi1skTMDMJzjgR20Vtio+Z/foweCcqMVfy2QZoYP2/kSGFtmDQel6iCexD1y7p xNAS9bejeiVKTFMAlEYPkL0uF4KOdh1i5IxImVuBTz5fHSfieWXglgeys+VK6tb1YV/MnZd8Nrs/ Rs47ZUfQ6Q/tFhsc5ZRsbJKUOX9p/0HxW6ZJY8VKZscjPANpxChP30b4u891AEuCDCu4vjNu8swu q9COe8iAdEzl3zngFFHOpDRvFBd1/QeBjU3FdA6YZStWQWN7GwwtshIo2Qs1NZU/VK6e5JLBFpY4 KbGSqD0DKvwoDq1/c4Bozn49/+U5eljMeBvF8+UsYrn6pboTwcvvDJTCCO11iSlWDuudzYPUuGFp MYyRm283uRG97QizmZcEiLXGyqObcJfceE1YfpWkCZZkoZGjwvhFXRBd0RBbjFiQzHm9L9AIG4rm ko/lzg8BRWnt9wf+c0ltU7/SyMCxpUhiTBymwNndSCfQ4eJr07OrL+Ay8Q+7UaCx+2EnXXGk7Ls2 xrPV+b0x5woI5m2/9QVEQB1QShUwVarCDIqXS4gBhR6X8SeiHRLKnx253swtYKypIFMCWyfMFBb0 RvBkGLZKXGYhukIrEe7bd6l+VIUBRPpNx0oGl+EPz8D4VmjXIzbO0vrVnHAztKm5SvkiAxa1aFDv 9bCX/6Gxq9Ln8JI9G8DHnJFKtWmW2521GI7vW3lB92OGIXpyr+Os4u7j8WZcPPHS12FrTGAZmZAY +wFgScCXBSakKTKFWD7SHqdt7yE2cIqBoUEnyzWeECw7ozipD8HHXHWo5soN+KcgoGoSxQajFGu1 Fzat5qiMyZe05FmosyATHhUsKJztVtcx5YnnTknSr9fnfLHBJLM5RCMjng62Gh+p+b2IEAI3CJ0Q uNQNgIkuJ0Hu2ICa5KJH4IJ09GRp6kMe361gDtw88PzR6ukZDqmZSsuJG1FNClt+EIX8/QbtigbQ mrwFEu5Rzz0nLx9kC/ufaaTPQ8/RSJsaX3bFj0OhFzIVxIWBtQYSPuM/ty/DFele8fX7ajeww3NZ 3fGeFFSBegTfHWGHD+z9DI3UWPcCB3WYrBWC5T13dkxY2UoYSPzF8S9Rs7Yfrwsl/52f4MA44RO7 Tuw7uD+kh8Z6cr+SZfdPGSIJ9zZch9uUp6fpJ3oU9s2tTUzGKQz0rrjSUHfeQjyemNmbnSBnPvI9 MaLlbffnlDk5heJYLMAbfLiZZR7vtdFgdAaFMtw//NKFdZVQrl9glbTwvsZ6li4Z5xromkYetNyx 1tkyuJNvQTaSqyfLbC9940mVAqkKdx3AlnG2yQm/DdWQBTChK4fB4zotJRoyfqCcWskVTE1lbHrg HXNdYVChxjzgiOXhWQ0/PtMBRHPvMvNWz7FobFGu+9BfbVqqg/5ORKr5IcNbhzztA99sVxXzDziV VSH4pI3Kg3zODZCMaWDY1cfqVpVSuf9kKnuFnLsWOaZn4Ludd662D8nL+rqZDRuoRWw4n3qwOfMK 2S4jTdlhuMmZPajp8KYhT+QiyQ+7Ha//r4jUZ3h9bfSLhVVshW4yKzLLLhp3DBuGiEYwaOXrrZVK Sd72H7oGV3DUSh1WNkll+Tz7FEBcoPNE38zXO3emZgKLOUA0cpi6O9HPbNChiAmnTQ36kLVW1+zy titWkSLjpLxuOCunxCiLBgGiXCdHuCPkB4DfT/T0IXLwdFMrn9nWK8aZDQ910Gmrh7kUnw5Sr0jk Cn41R5M8olLSUDmkbXVXSVpOMQn3XW/Fu/HKU0oFNIs1lCccibKMVt7IVD+tUrggRm8CGBew3lgV NQqM5FlUlx2VBkpaBNZyxWmb/Qshf+5Szh/0wdYzsbLK0LXm3LH/WaJOp9RndpGjkLpIK3WC8LPt jc7U3G12CMvdZ0Yp6yF1X2nMO4O5ISVBRLNEbwfY4tatsFO4V/IOWbwmUj1EceJdaodrV3586+ee tOwfqdX42y/amULMdNFTb6uHqSAAGpplg6K5UHfeNYvdRpUHwyhz3Unrfb0lV5KqRMf6zvDfGbQl q3aPkFNG0t9yiEwJBk2mn3nQrghnlcPM2hcfc5rB85B8/hleMZW6tZFJ+FOMLuJbhz6MXzUvv9rc YbGUkn2KPKW5AOGk7m8Lp6FqNrfQ4yqexq+ywkqqBFKLnJM3V4dvn58GKK1PjF6fePS0sYt+gQgh f8MEbIQnS18TjqF5CFXCm6a2lGvGTL1nrrM8Un2XJeMq6AiV42N8ozHT7uBFd9OpE7+/dVg4NgpE eliLOKOelE87uYPqLAjdch4p2d3koV+fnBwJ8jVY7tihBHTOoGUDE1jk5Lz2kXTrLz1h7hcXzDk0 2ZA+Tjxqfmt2Z8effoIJ3nzIxhtCiWnyACgX710AcZP7DTAvsMmgLah+Ac2yeaolQVvhRrkhLLZL jHfGhPQYIK6c7sFwoYXVVLUBq1xUitg9objkeWVynGNZmyMh50z2T4MeapIS8jcMFdOxxXylgHob 01AiBWzh99DcMaZpo3sMmQZ0oZ1xnJ0HhtDlc8Q5yIXfmKUtrl74szX2wAC6fcu6MVdgkrm76ZI0 S50UKgJ84grGYpJc/abAWt25o8uZtWdWW0DZj3rcpc/rouPWGHMC9+mPqAUu219GjptpypwMtKlF K8U92G0usl7dgIs+NfJjh1kEqF2/0/VZVTkJh5bnXqfylqwqgJ90dGXopQxJmu7GBrNgRAX5bVCF ST9zHiwvf7fhIuTVtuzxNSo0wAy1Ybfn2KrXt8wQ6EbhD2YccnoO20X62xi7cr8LQvk7bO8hwPrk u9M7xlGoEs8mBmCdV3EI9CMENl2hNuUxp24mp4mtPcMCnV546O1FZQ46OuocNzQ8klBqS+OVOvo7 QkTzIhN+0hz20HjsPFaHVtKYitOjKbMoar/oqE0pHXPzp552kV+PrxN4cmoj5CtMYssa8OuFyEVd GtMbnZfktvNDzvYknTjsAy0Cu+HFa/sGhQTQmTEboAdrTbmdaWQJUkUbEi5ZVuev+Jvp2WfJCBV7 JBrpH3/OLWocUqdQR9DmmCHL5cV3bsxSu0wJgm079NOPmOWF7brmtTwvYnZlVrvxKeI9WK2yXqcn CVjdyo+esmuYqybFkdgPkAcvsaBQN+j3o7q2nTERBmVGSA1V8Gpqqgf4Yfp8vD/VmXZR4B3hts7z OfDMOhp79hTGe+5y0elExY8iPy7l0UXGx9elkW72JQVVIp9Dcitu1HtT3tP+9RuEgwhbDQeW5GwJ hK0/e97vndrJOXfn9o8nW+0aUSTRE/5/m41SMX/t0RWJL3qXWni2Cc6D1aRcNlFlhk1Hw1Tj+nub adRY3MdgPn6BeiTKddBK3he1NuKuZkByxDIezT4RmIxGPRPQWrLAhzgFpWpv2VV0iLOtsYEHQilT 2wuBqLwn2lurNO8hrJTWJ9pB+2/K1yQouDE0h4Ik8nCM7eHHLORL73mpxqmSsYH/hdkQW6Nvs2io R9oFC978BQZ9kgQZfhsdBsQ5tyfNbnx0lHHILgEOXa/EbBWPJ36c3gCCAXbYezrruImx9gmN6gm6 u+diSIYoRQ5HeqkMX/MUAMTUvRc+lcWVqGdbM+t/eZRvw9ro7e2AdMF4PHFzMCOCFVsEAemadVk1 4Sl8u+bKoXcGrIqkzp7iXftI0hNmz9fshmTZeSeZxy7AxYcR2zS0ltnLn5MM40g5bzextI7szYQx bsCLE22WBQA7DQ6kkeGs+pP5RxI+/1WbGh/UmmnPxmirU2CMnbUtfsHViVr9VHrLAyPg/tsZDAxt blgv9YGPb+8mW6B9azOZoQ5+2zNFwlqjwiPpWW3EzPqrUVHXIf41iRRy+xGTvUogaYYaQxFknjGs i8S2cL3RBXbqa+Wv6ucrj/EoV6FlcgpWonwUnLYKnBy0jqP5xFb6B9eHXvCe8YY7y/728Q/8amTc 7D+b62wmCCB7jXAiIbmtWnWPZzs0c+XjYsyCZ4VsxGZyDHO3E7nLvx8KEyOQx9LerrTukwfrkG/f cWOpKv6KxYUyMoH1vecl/DfxQNvxU+4MQxXsAoYQMW1DR00gFXhhkiaDgPocLY9ipdGS+MrX2cCk FrM5Jo9hmExQGmLNBDa5FMW+rKVfiUMoYcKZ3hOciCyXlOxW89gmif0oFB0DVrAoPGlmBDSHoaXb xDUG4ysvYot4nv6nE4bEaFEMsrtMgKEp/T6FLgN4mVOpnkAcHy5EIj8/42DIIIGhk/8vo/I2vN42 +268U3hHMW8qyIQCvcTHAHnSLZxbRGuiUtJ+UEx3AJhU+ifejohcoc0w+Ul/bxEUbzww7JUSlFZH h4yYYfWWLgrKS91EdscTJREjpx0BxvbZExMufTyD8Sc/8qDA6pUiC3ydX6PW+MdwpXzOmq1SxbK2 VooD50foh96PwVRN1V9Bu6x9aLqI+f4Dn+ylvAc9+uPYR7dPlN9z/nhu36YQeg+L6hMk9H7dXMZ+ kyVf9JzRLBmm6rHZwFOkGmQQ6hF8G+b1M4ChWzHSwYc89CttiFOjo+lzqu/NLqSadA+xhh9+zj9q vv1LCCon5QORzJ6+EIc3TMeXvCwEvjsjjetp8E/CLaKIF37j/rxs9639Rf7eW8W8cwYeWQ8Ohy8z BtT2UMRKz0YxVArQ78QExhmNc8WdHmXmM0JNWezGS/sob7xU3PMZ6WlfJKLg7VGC41o07eHQ9bwN 3xEqwB16AG2AWMISinfUSgp4HJjsgs+3UHFefzUSsbp1sczqYEeW1NQ9fZCviE85z2Ejr+DBqabU G5Nv6zFhBM1sJlX57pVyJsUQv4mOpQpP1CaDlD9KN78/qp0iUDsbo5ItKtf1BbJzzN1gYXKLXCUs 6SNX0Y3PO2jIj+B6SaVVyn4wIwWU26m+yLebAl5O1sakWe0khxT7/S+HrIUPfgFxUatS6/Wo59bq zWrrB9DSZsjLc/iS2n7UARcKDkS+aisQ7yRe4q7JBBQaZ/9iPYh9uw+F4r6QMJD/bjnbcZ6V3rFA btejv+dVp/5HwliZAu2b6gG7FF/5/RkezfUiQFBNZKu45ytLnavj4GvMnLfspmYhJxle/4ycOQXs y1DaWJlRAYV2zPdvX/asqexIjz/t/bHyjl6BX7nIhxWq4roGNyRqMj6yxFwo7RPhBm50caKB2i/s DwNCI2R6cIzdO/+/qrx+GLux1QxQgKDj9713aLS3v7XAFklZ+zk3JBy2D3dICUmDLb+4ZqcBxTFL UHZB+OJBPCRBbz0rvkNejEL7ldJCcxuxQv7EoKyo9811bNIRUVV6nbqgYEAcPs5q/4xAZ3haXgI9 FqtNVleCnQmjDH2OV+CPcL5Mgaj4JqugH2H+UvsubXYf1MOvhKmeecZ/s3YyjQQtN939xx3Qlhhm LIDSfGNAAtqkCmkjA9HvRJH8xiHtgnakCQPX1FDCdtI8wO4DX3ppcffsQg4XCJqNh4EJZ34AlWPb VhhTZgaL0KV5eqcm9Y4kY8uwbfqzPyq/2N+QrXUpCjeve8a83hQgQRzMRhelNO3mrLr/zUE/NqVE PlOA85jyrwOphGLxIic3iVl9QqJH910xyev7RBfxsUtYITH2z/fUP6ZrhWU7Qsno2Cu6oDj1bSdE ZsUsPFT6+/YxqbeZ0gSyyK9x8wsRKGPXxGZvKyqf8IVMJL2JExB9n2x6I6ALV3Wc4mUBTfmbSrN7 TzLfzmZOBtTPlZ/t57v6VTuU4JkkNUMgORCcsup0EOVbUk+h8Mhobp5+KYBiQ9lsdGCIA9oxT9eF r3k3a2Bb2/2NgV5xM2Kxh7l0YY75xRgLM+Uc9KHWI5ECdGyOmKKpqWkgc0wLiP3Pg0Kb+w9z28ro drRfk+VaSlQ5jc2Pd6cpu5qlSfB/XVHt9LsOyGYLHKdB9jnrjLnRU9975RdfPTMjC05KNXG7p29A NsDFy5nmNj9KtuLLcvPa80XSjigcigW7iMFgQ86/psIaqfK4vk+SolBZCXcXgUdS7pnacsbYA9EX IdUOI+uXhIL4pK0mxLPzl1DAw7D5Gfr14Ryo0s27VevsKcSgAcbayCba/0KIPRX2wQ3T5mfla39a XhCLw1rOHtRCr+y/Ei8tBEzNTC3az4whDu1myjYoHZ9UG2MCL8y2FTlZ+5iYfuYjcRPMzXBeBkoR vOXypozvkUGN28aa+0fr9d4P6LPj2UY8cF0A4L9hjrN68C8WNWX6Ju8MJPthpBsgJrZiOnZyDxDE gc8QOLRc33DfJIcOkvcNwV2TxtEtyyC5fPVpmHfs595pgtKKR8GZawEPVi4sBJ3yzTYsXYJqIyal 9AZBYXSY1YvADQLPiukthc5haQcyzvpfzXnq1baPvm6Zx7X2JAZovA/UCrafqxYg5csAcnoknWQL cYMbMxRPYDBiW+oUyrdnmHDF3XFFIjZKZnFaRaJlHhyBMeZqmXxnnazk3HO7XUY8ABbtOUTcTYMU pcpJ2Qh/C1dPHysKh2lVfzoQnSCm3iQXk03VU9uLqeiFayqGJa2uH/BwFEkJLgl/h23HFA1959CH JH8/YRgJ7alcgjKaPVIpo+kipdVijP4QbUs70iOYv4SXdBjP8uZFVJM47HghWurqmHbRlF+h2id5 7bGcZUxt5sLXDSkD8iZgu52//waWE1H2SdjTjPviqFaCt5SPoKftiTlJSw4gH/rr2hVaWLtH53DE kFjWv1HdlmbMdW7Jn8BqNkE9TboIqjcx4nxcweeRo3+Op6rCvXn/Twruv4fCtqJEolvwuE305jEn 2C8EdwYzKxtvr5ccev3QedKxbniPkhnZELBu4Sc8KXwU/Xq2dJG10OgSRgJI3gFg0ZZBF2DKaSFx yaEG6zZ/PZJzfWAibUXhGP2oh9ORAn2s7pRxHKBECEVFCOtnrNPbLpY7iMubIoj0yJMQifGVOiou fZT7SxOFwJpp6Ewoh5Wf/s8jcYHOwTbjBMLeH87XCGuUNefWDAVA7AYjtZpbdy6rj5O0abt6CN1b bfADpTSqeLdZhbAyLUACUXBBzn7SB1JHOHi5bxQc1ySDl3irkwbJ0A1XXw+X4Xr7tLXt3LCJA33q 6ig+mTBsQrqnhmJuzFLuRuPG+hChjMH8ZLwlIicEdhuNANHn41azjQFWC/BtY7yAZOvIW3H+sIJ3 k0gM21fp/1nF8bPYwAB18DuJ68On8Nw3aIOkMfR+ofsAs2xWjfrR1pB+YJ3KTq6SmWayuDUb8irG qpb3NXNpD+jKzlW6TiJwwt249+2fjqUoVH36UfhjZRFOdxIzZlgxRwiF9YUux623K1m/ShR26SKl UA8ly8ckpoBG4JwBrkCD9dQmY8bBy57FvXTfB/mA/jh1HK8xFFhWlnsEOTYxkefrbbAflUUaGXUd TOLxgO94d/AbD7sgudxBSfwduhbkKPqJVWtdzT3z0OEjmao4fHjZIwrizQidxlbWpV8uODEidLrV i3JkGi8s44/7glNMUtXatEn5VkNlRWI5ZC/PbIi1j4AEwkCnfE0YBGp5DpKT3kneAS78I03wzWgo TWp4X/IQzfVdzLBYZo7yi0T3Z0UsCEz+rfpVQvzJs01QzwjDTHN1Yp0Ow6fmiWimzXGdDLW8H0Uz ehbTTur9xfnBEto/ewwqax5v0ZPEtOTZ1oLbpmXmYqMx+r8Tw3F90W3RIlkIPs/a8wrRcfPkrGrA 5+ml2NLY7LukN6NTf/HzJtC8nUF3UzhMprj+BvMvQ+Sr7oTxx3J/y+nNRy90aUwcvp8IIJYNxJqK tGnMAJglTVv2sRubLZ3iFaCB4Qmd+bZq2WQpkEN6bwdN+KVxwQdCaIyQVjXXcIGBR/2Mu3Z8eHSc Al0KaDj3WTmC5ViVNVKk5XgS7MTR8nwk96ielFHf14IetqYVMw8UmEqQ9fj5KI3nCtZn5VWiuHCy U86fh3ywspQ5lvyUcy6HcuWiR0by9NB8hpZDbDN55cQPeb2W+LD+AgKOKePrXf6RmhulAyNakUDc jqSWaeSH0o2JqZLU06ox3WQD8dolPiynN67AuHTwUaSV+w46oo5vb/BeWiSWwzVxk2UPg0qvH7zg miI5j3xcU5t4PT9nz5upF8KDUccOsdJyN6HHsFNODms6WdRANIx9EMlVGBFGqXsZXJ09w78xtQ7O akHgHjuPH9FIS28V/as+Pt7r+nYVz8+uU5aDjDJ3fpRlLb3yhAZOH6o4r1zwGP5QlasbvshSH/ja hq9xGmsiZy1ris26txAB5FKQvZvA/iV11FfudDmM9G2z6NKEVxypZ4HbZg58LLu9VU6N/+sEeCO3 WqtdtWVaLDtrVH1q4gdLN+waZla3MlquqF7lNvgS2eJ5PrbyYCLtXPfVNpo2h/R0zAu6G9r8/Has 7pgxiu8dvlI7kbXIwqsS/n01XGyEfoTv6CRhtGwoL35lH59n9J5G4FTa0HM1hreywA1SCJwAdfi6 9ZvZpxOKD8Bc/U2432RSRdvJ1GStlzqRyiSzYJ6wXcNitxCs5jJYzoTjElOuTY9Sm6mYmepnI3O0 9lM+ZSvqh0EkjRAW6gf8M80VHa8xvlGA0DfH7NC3FmAlV/iRUGSR0PMJ84IF04aTihM7fT9tCVtW LUn+niQqzda8RMIwcuWrwW8uzuzBZnPDjgVjyQhCotMFQLNIEC8lsJzmAbAYpI2cezDRhZPJByN5 xFbms4jDmdXVo7QEztiinVJrVgJaYunLAmTKP1t4C2L5yzzmdQ7dphBlCUdtKf0tlK+uQgKfOgYA HCX+U71INrTZXoBCvGOT3bQL2lgDjH5xXPcn4bKRVA2z4/SKp6ZCXgDcvZQB+FiRZHIFLzmgi12G qCGXoYcsK4/NWVrvOWGuLwIXpwkjiLj17BE/SZXK6YO9P1CKBYN8u/Bnb3+1FNoyiLDKK/CKQl/8 wlr8jUIcH9YoIO79CSREkhqZvVmVk3QvGdkA27ox1Nq+U3A0i1u/FJuJlyhaiPLeHWZSEquTs/rI bMdoLaJ2hpIyMPEi/cuYKmYgVNwR7miS0J7TPqlhZnK0j017ZeWJ2z8FSq9zPPW2VjT9Lq8xMW2M as4mPgf0aI+d1Hc5/8l2hjMNNIN89uTCuzFyOFKpfUrMIBDT+Hwzs30ooJ7+/ypQwVgzlNMFJSoK gSXpBqagRhaQxpPU71zLMAu12zBNEfa9hZSyeNBk2TJsI+iU8fD1CKVU1+4j1l4YXiKyGXikRTqd URqZUYuDMakUnb5w+4QnKyX5TP+GX1bLedFamvwAcICWw3OASwq7rxXBD0a77RSmV64zRK/Fqc44 0C+Tpu1ouvC0Abag7ijMxtmUUQYbjJkmw1gg75445yVgDLn1mOY8AocKYXGP6yQQF5K+V6aHYoy3 kcfCDHoM3rhHZUs6nUSzx6Ijr/1yBydcXqu2N5o7k7llEO6e1AZ6V0hMnYMGRV4OuCP89ZxH7Fob 9WQu+rPTDhs9Zu67PCOI6FpTh1WIqc9n0xIheHsSIj2qjDS16WEDObDgrPIfjqrkIgiFIg8ds1X9 fcth2ElvjslZBQNn16Sjr2yVR8M0nq2uaDigjDflJXYUXpsE2jiEJemHPb21fj8P5CfImlRJjroy 3OYY75VzsxeJ8dStRgqZdXNflaY9UAGk2OAK9OpmXhfajPfwkShBKBT2naFaBobooVVH9Nafk9RW g3ouT8VCNMxcHcSfwXNz20IMz5vXZ+sDVN/fwZreKnm45PG5P8+azLJNJIjhFnAqTHIRgE5p4ZsJ Sno65Eb1jOrqdLj6VGwM4/hOc7XhwG7XGBdOx0WKIcgpGbiRBfdZMaVN+fl6KN3PusX1mcC/RR8i B5KQUHaDwQ5gPdY2e0uyLoU2w5CyLjvks2LpH2vdGGuhk5XgR3WRyaSefLSa++ljxWxuxCz1yceG aKqGlh4/bB8Suwk+n97Z2TP/Rp/I3DcxYdkv89DUeE+69Gwl1AxbAZDHWkS41hJw6fhBXoj2KMor pEdvZy4ixZYSld63pTqmmuKIv7sLzod6uleirBPuX/xF4nEpRrV6Q3fYdTDWnBeJszj97HafbGXs xl9gRvTtjJt09H73eBqeQD5UoCg2bEYaGcAXfGM0y3PwugubmwXMxFUKPkfU35axdR+Li+UQCa70 E8N2AFrDDV92tRFO5Y6ere8wgc0bEEY2VQ1xnzWomQ03wZ+0VG8DQIh3TawKLFfD+41j5MXiIj5z GKY9O23uCKu7k6G4fZiabvG3GcSRFJSu9sdFSKZ27cVr/fj/YrYcJhhKkA2iX5cLaQCDkcDxjxpH iwkwkGLX+d9Cqx77ATPkidDSSXxkbZmJgd27Yz8/oIHhrVOooMiDcxvTzUpbIM9fRcws4NUreYP+ WihPb70ukL0eN9GrYUvvKi51iju/4zqKkgvMoIAWLhzwbhdNQlea/O+M/aRgvW7kkJpRSi3z+lNa mCq62ftVZPwh3CD0xMelwmplOmc6TlrbR6QlQQcMr2K8usaoRlvOG7/SsQGlR1WeA0FpXMuw4Qmw dazvThv0n9JOQaJ71G5FknZ21ix+YRtjujhPZejmF40QBuA+uGLS/2TFXVgTXEtQ1cWUCqfI2xWr caXnY8VncgmbM/loZhB1EbZwAajGuVLW1zXvCb6T2fcA0vXhZl/YnfMDRMpYxBlj/s+fXb3IWAQg 3So8TNdYWK95r9BNuuG2DNji/ZGPK2mCgFIh/hPcfHJOIuyCnXjEDI/ym7Y+7YJ2dK50IwUvS9m7 lOcLwRP8dMQN4XLldPWTCA4gkR0ZtRBEj30YozKFJuvJ9pNQcGYex8b+rTcNP8Mu/XxYPRIwKJo2 WXDHiX5pFgqjmdtwg9xblQu8HuOC/1ooVqles0c15uAuNd0V0XcoRg7Mz1SNZ6YB1QjE01tyyiQn ka9GRzs5EwopVgRBSTYlU5G8HpkmatuETCTAUPhhOlEPlCavisDQkDu9j3oIvYuvKwax8e0ThIrk N1z8WkkI5CM3r6hDux6wPpH5A23ONP8RXMiQT4NG3l1yOLsCCHC6oi9NZNjUvv3LHuLBoLPlMbBD k3b58WXzFhIiDtbMIdyTdGG9rmCAOWNpVV/hkraEngtZeGjHKV7uXJyih9B8GOrKFobu65sqd9dc 5upqNDxxJRXxynTG4xQjBzL9OGemhnj8VufEn5hoSvBGMBOw5GHQCFGb2xww2JnmRV+2Jz6u0Din mpMxLRznzrVzvKvAlUPXrthikrf6g8/yHGiXVllDynZ7udjSU1/gdD6wklzfY6Pi+c3HCXjnWbbh eraupDwrFT9syWGiEGrDz5PHpR4WiebJhYS76v9omIuNOe3Z7ukC3csun++ERx7MaVq4we3ayGLg GsVSUzMU/uajDCkR013SNuy71nLtqxz1vkUriu4u5G5VgxcSZJ5v9ps9leGQtXql1vETcyCyXYyQ Pan4g3zNC2CrxizzgxgY31JLf6Y2VNV7QxUDK3+m/DbiXJBy2haaIzxOn4DtezaKBfTyiZ8uCR4d BvTIPY2hJJqCMWur/t4gIy3pd24hIKpTrccU8zauCe3nCafIbbCUJpI97Qwhl4NvQaEIqgzZ12aI nY3yYHWzoKG6ueT9ck9EdblnAupaEbxw8a/19IaX7W7aSbiNvRT0SIjeiaFvWafTxuP8L5bSnI3V 6IavolfbKWZS6/8G57PYhilKxYK/3kWG+e3eFn10F163ZgUsDSHHxkrY4vNin+5ChCy+aW1+EkP6 krDQhqwXjzzDdO19oVpaO7HSOa3EPm2OSaZcjGG0txVM6KZ3uGxSWBSHcByPgBKIM8CpXhJwQle2 Qaxuavpv4QqOKXjGlux3moiIA/1T9rFt98nvfd2oiHAh2ASczDs6+CztO5L6McSwG6/6fOpIIRO/ JeRS1bpLSdYb8+XjR6uXpmfrkPNzdTuNxMbR26Wu0K63Tvrnl1s1oHRSq6DLRAuIlAyc6Sv2f/Nu 8DG+00CruHUiZjKGtukxEFnCsB4qZUy4NhpuEFqFczRRmwn21Ci4q9X66SkC7bWds6h6XFDk13tf eObuqMNeDitxUw9EsG7Fw33pzW0xLcp8q7t4ppDtTm+jxRirAc2VTfZA3d999zICHp12Bwdw9XtD 8G30mavXGsUu+nSbJ27WU4HxFUGBf3MLLkFRM0v8rnq/OnNOPkweaRVeNgSluDqLhvtyBoeg24H4 V9rClDVG1saBBB27xvRJAUJ2E+z/n8hwRXylVOMp76D6JAQkaPd1x5jFyv486MF4iZlZxkTpvsXe +3LoA4t/5VRpRC3+6dUmEk7Esg9W76PzWUcn7QG68FBU5uZB7P92Zux4Zo0BMtDH21yjUnd80fSg oxsY7CE8na2Ww7AIuGoatW6//i7fm+yNjcH06dWhjACWk95/8++gQNyRp88k+lhb6hvFYOUF+Cp/ sdJN9JRVZfgVsqvAQzjUN1+QJUb0f1E5LGGVl2sbVnGd1zEhR1Oo16LCdGu3dcP8rJvmeOP0F0Lk K9a0vY+FKsTqTTtJSoTq0AjP6D/iBtV2xM9+s28foi47CBxT+AwMGMZ3TjRZ+ThZbJsZ9OHtYEr+ 8M4Ku5OQCTSPCTV3tLtvqjRawvBI2mvYkmt9Q04KlO22DDw/QCvGcxatpdyNE9r/Yi1AptW8HyFn u50Pvinl+SycFudBqhgxro3BsNCRO63hEUgCr0ApGc7yUIVqI4zUj+55plNM5x6buvI/2T7GsAC8 wA0UFExX9bWLPEikRZnrYcj/kZqWHfWwWHBerVedQlR1NXPIlCQecEmVkDNDX90O6+dVN5G1hVC1 7Nr1YewnQlhjbec5xq9gQIbKaRjWFWUJBqmlL3vikPzV2U+e7vZ3ThnhZKrutiT/yRbe425Dkn7Z n34RFdafqXyzO/apn5khI8vIsK6V7Ri5u9daK2pntJ+FVhL0yGwFPeLfKqloXaolIzXe4sUlNaoT Qe3Kwyht4/TY+bnjXl//ldWYsIid6rLY0CNJK7Sq8PKJy93qlNGaSy/Weqdgx5eAopT/xrAKCw1j i5otD7ZkBPvubQOt+l+DO2HJQDY0nHYiC48+Iy7pNW+gyAiKQI2QlCzXrFzYAJLsnm9KuojzSWBw uAZ3qUC+fmSn2ryUATl+D9t88g0tV2aPBzURwX0gY1qZh2geybjEwvgCU9HwQrSUaGPFfvw8mTNP hEvJshYpf9+KETruMee9+Q+2JyQ4Fogc+xr0S3J7korF5jN0BSAnVO3svrYcAI04yS4rC0jGflf5 ab1nYmVLtPSlNEq6TKALLLI1NxcTxObKjTma2Ob6IB+9Z5mTFmWmCnb3V2fcq+4YNlzXVYzGmI+Y L9iGirPMym4eVzvlNRfCl7fuvxJqrWG/wk75oPc6ldNNCI49spxw6bkqdm4aLB/ophd5bkrX3ykY YISl/LEtstwI9dFrCM3+Q6JQSfb8ynCS5C+0e//9KM7KgC7h6EOffVRfh0tFvgmZyimT+VH13FWk nQ8abs5owXyHASPfsG63WVHvMlfpy6YBRTXiwLpqJLg3tFv1QLnA4t1uxs3cS18NdhwTYnjlD0Mv YjLpOGDI9EevBkGkwHjt8s/xg/0LpvNN0CHExp6WpACEn+TYbyKluEVk3QrQ/WnyZkAM8VswErGG JXiGU0bDgmSUgH2zZHTBHO/54L4AIKAuq5IklKDLmQqwGF0X2cUr9AORcGTw1nKhIi/c6lYUXPiD TxC2Mxk/NWoXIsiaFYBhIjiclaozsNWPtG1F6FQMTO1UwUBb+JjbS5KGkvHoxpq7jAT3ZlpMwR6Y U7Uho17pmdC6WQzToWAhB3qTo039quJ11rsQjPf3VFY0VGYXZ/fRul/Do7t/9yf/ssBL8kYhh76N DXtI6+ECnFeIJ92Aj3Me7Gw6dFNfpXFmU9LmnRHdTpqA80hsRaUQzhPMfGzRbtQ3JOKzrcjPKBNC 0mklAHIPOzNOBevVTKWTvty8o4OG5P1KmZqGIe9C3IpseHnFNR+l6X2GPOoGiFxJOF0tXCX5kRiO Hq2rjyoQs+ywK5CefSbsIV5bzP+/PnshIKbKk3+dUa1xOgEO9++BJTSuWvA4qvZSN4IaQaCrlvrK HJU13VYW8Exj7IrlTNHYeNcZvDkBY+uER/EQjT0aq010RjqyjDmc7eHFJ6addJjl1SMXmKpZBIuP wrL1LlWJmB+A+qJ/qDK0Jx9uQ2uUAxrvkNRJ27rLm0U9eWN+u+kSCqbh+I8xrlmB+cZ4y2SWf07I W8MbbTWC+3QxAeHYCb8Hd3fwPdB+4NJ/0sitAPVjbdWjOp7nzcAfYdGeEJ+5T51cYVVDewX+mHHM VvaVO/cE8+Kr1kZuLJmwsRKpThGfrrrFCwK4CuPh80T23wBWXxR256VA4MDpiNRMKSkVOAyQMCu7 8lFxKi7/PnZH0OQ0XxM6tlao58fgx8BB1l5gfYkZQuS08OhZWYnWYOY/t6HQXmZkeJbf8XioszIT f+6FFfLIJryoxiBM5EJIm90cXZDIuBQUISfopW0ea4gfjXzEIP9NNZFRAWAGX8HFzj5LhC1g9RRs Epp3fTVFYBcIGmbVuksUsqiHOkfRjA/ov7B8ntUCtpGtxjc3upLsedcQHeKBn7+9a5ZRU8LEB5yZ MrCOLExP4r2qar+N9UFcfnBKkn1fnlE2xYUUlSxi2Kg31Ar4M8WRdokAYtoqos1tjemXa3ZXJ+Zy DZIvQ75uXOyYEnb2HSIcb7ihwFG/K6fVG9em4igjk46ugbduuhRidirEBHDNxYvT3mcEH/Vr+JDu w00i3Z9iYO7LFXZ7Qtl+Mgu2LzPWf6I+wn1jFIBvA5eJn9TV8n9feHoZXpKe0ZcGXAxaOAUKvmsO BwQsiQ9lLA0lCA+FuOXi1JLCFkPUZyWwwdaSI7smmbGoQwxX/YdFfMOZFwM6FvXeHpq0Jb7NanBN 346Uly4p7w9HLYaj4iQZf+WysPcBU1o+dkUTZsXsqFknMwdY+oO8VlPBnB/8v1Qrs8buPmaGSCT1 kyBwewVXa9bOz5lmOsAiC209vsnlXwF0zu2nLA07KbBdoUfpMLZ/iJ+30ZPjbUVSTdoS6wCQaY4l cowBgfkOWWh0HOtjDHLsZSSXrrJsMtfJWXzHDxBIuM6NLUqM9JuLfkeLKySx4FuXwF7TcmF3NGCM fnp2liXU/OKCoz9NfHAy+tXIR79l32peCa/7PJWui6T2ZMlsinC8UwXxzv8q2rCMOJl98tjywRKE 95o2Ibb9eSKULJ3kz0Q6DJIl6vrDjK9LtwGNj/aQD4wCAl2oAYjIM1uR5PT9vm2hcvwGiXT1Wr/T +8N1E5Ufz1NZt0/k8alBRYx+7XW4OrNG4ro9+W2gHAAs/iKf9a3GKl7NcNCYTQgM5UIU0SoBt2E2 Taz19rCdYrjpAYSccW/rSHMPwA02fUd4Oewn4LnJYQ4+sZj7VSmvSQIVF5FA5TxDStxMbQ7D0Npw NNCZ6H56QFLm8KeGeeMSAurKozrTfgljMdUP+3Ci7FNzzSI7fVjKwVKugQnBPTwiHWf77OXlBgFF 8mv6k7iFcIG4yUBvlcVC29258HR8NcAEmVUaYkQYBhck/yiwGWhcZaDdw71v7vTTBE4ekhkE5wnq YcmkBkwpHTpp/HOgQGQm8oFqq3w7qf5mIXoRK/OAFycApFwtx9pZqWtbDX2CR6LHvhLWE1TJfqqB x6x6yWIahzN5hp48rhds1iHZ+n7+SrK/Gf1TbiWxjJqZ7yvuzzZdn/Dsrih2NMa+yV5tLJGY2xOn /Po/GdFHFfaClAIWXpOwNHo3ManCZl+EYJHoe0hYXMB8GoPQ7NmSAr4iZl17YoDyaWkLxPp1m0WE YMQoqvh37ljWrUrMposavEkJtIe5K/1Ql+F+DlhFnnWLCDToVlWzB1IuDE0pKJkd9wAYo2FSlTvo UeEG82GKz2OM/iy+p8PmXlw9uvab3x+ArdOJue+O1dtSvZDYpOsCw9vYyZJ9FwMn85Yx9gSOOHzX unEOxhpKW7UAWGvPTyaJl9M5FjRNcHBkI4Azw2CIuEC0lRtUf2o2yD0fsScHKzW4Rx4g5PAKX6Gp EhJegB+b3GfxcSVsZtm+GO3H4iioeik/Edr1W+cYNuXtLHL32T6wY55kdb0y5qYnA6Slvy5XMZJ/ g7bWcV9oWCj3VumKOcfNrWvWg3CPHjeA4SwuRnhJH+dhQg5Xq894+2Abu+0nGWTKf3pO+UR5TFET t+WTvXF/qBAAA9pRkPbRzSaXjS+xnIkuwH/EqsWDtkr/jrlxHdFZvSPMGskRANEPOawb1bqsj6d4 8IaU7zvqv2POLjzrWDFN0GSOAK2NurYVClK7IXBjftsDilsaeodlqnCLsgKEUu6P6QZMURvjbvda YXNSanC48/eAP96zYDwhWehY5p+m0utBVarQ9ME1S+W0mDxgvckVBNg5MZCz2fPdZiEjk3bNTIKI OYt8nJpTIDwGje7rwyQF3gkGSK8guPJzzl7LsJns8/yM5RqQa8rVYyQ9SBgUEQfzujNm0i53EaNU WWCoKc/WgcfxVD4eU6hO8l6S0oTh7r6YZNObykboZwYOaxJPVKIb0g6uQCHx3e3TWmwIBMFb1qNE BZKo9U9AhECz2C1qx2ZG1QniSRn2+uvY1KLToilmI5EuMYhEPWNgYSSqlfwbBNxBMki9RnWkLVCC nqMitTa1rhWvqkmN1vQuYavwF9hFoGrdEqyYZgoqgnye4tSbO2+CrieONVD+ePXkTUhue6DBAR07 Vd87iX9+iRkeje7nKQm68ekp5jpoiw2tHxZ1tWPCKTfOHRYO3Bd1LQsj4UJWKljK/L0Bhnd3YQnH PUOUKT8Kg1p+orIuGtycm8nv3GWeFqh+OmSmLdN+/+QyrLKG055B8UdNHVS4acaBq644mSe0Nxe+ ekfPzyglWlS3RQk5O1P8KjaSrIpGKzobuLzxc88tz82n9CAXQB0Hw478nwD5UXOl/ZsTSnL7Grah xPncsfPGyXiqIQ4ifFUVfEaoGTxWOeJcK0TbkTDMNHZqNfku6DfDMjsyb29Oy/+IxU7fBq7GMG7z /eOmLaY9axKZ/BXhZMRUydsw+prdRaxQ9SHVpgIoBuEhzX64A+oDlFoZs/at4x/2eOMA0Q3RmxIc B0GKDCe5G37ZvaNdopK2nFg11LonKB8n0CogP3a6ElW+AclW3c+3emw/NSs4KZj+Rq8QRY/fOc1t FDcLVMteL9mc9J9l3So/swCYvnIeTWcbLh9IBBq7X1YrhmHiu0dSjqaVTnrrPdodcBgbDUmjWQVe MYbko2c9d66YvHdp5nzQK6COPa996DZbc94x3gaWuzx8MTAewpj67adUzNyKEJeTFbNSK+uGveuH WUASPDJdC1EqRNL9hJpgvCBiKxHIulOiGSIg3QAL3yug/c8noRkudsqRPDtGLAIqE4Ga3/ylyXb6 qel68+GaQHn1Qqy7VzVNAOapRQ7SnuYGPwYdp/Ns2vhnd1MPgJJgZCtrppRWn1qCIQo5rG3Pazoe FinhQHMxaUUwdIHM3FPyHDudOALhLYm3QuvZRS5y/EGr1GdYVAy1GsBJ2+RtISPD3YBQPXbHSjNp uD5OSmbjdBM3gLI4FQaTIPKza++1dxH/e5qTeieibqMPsT+0DRwHcv7sURIZ22BHLfoc0D5+e9VF MedI4aEURX/7OhENXi/hGlWfsqEYgt4CiYsJtSuZKLuL60vyeC4SVovPGLyIJKpb6UJGFdV9Tk2J gdGFUnvamd3+daQe13Po/dZFjAEVEDeJJeErgcjpbqXExbY9DmODkmLh4Ct4BfmRpwEINvMGUo/m cCxrNbyZso1P2ODn1VS6+sCC9DCybjcZcdELQCVFp2sAaJAAugMObuqeP9IGqMKHYNopH8QPULQJ v/b0EDAjYDG/9z/Tg4pQqyeLAKcI55Gdm3H73f+/ke1pjd7BQnynAhx+2+igMw37CTkcxhTSCkDD Gm2l/9SdwDgRHzuMEQ57PgpHLEYaGHBnrKdeKrNhp4UPvyLyRbkRHHWiV0A5RJj2bbXxwT1vTgyY T9+bzmGIL7wsXbK3fNStoL/EgrlKUqXii+BSmRm/pcvjQS68s+/vR10e9ujs2pZEBAUcdgFp1Np6 3jqF9TfD/xyuG3W7pHcvVE7mVmmqBw+aJvFTHwzM3BchWTfiyyHLKWF0quMXVo0AHG5IZr8sIEYY Uch++YW7b/NXnGBYt6+f8ckA1cLdC9McqffjRQeIapEgZpbUsqYB6QBhubWqD+hB7dtFHdo+1HFu O3LXa2AtHuExIsAAVV6wckl2bfvm6wrNgFiTF4tgWgAbnVqYOiGgGUNp23wuouYO4hvsC6ip7/9a 7lRzrKHuqgSDhibzyWD57fsQnFZwb43XFcdTY0NDF3PaBAEsrHvOkIIlqVUwz5tThIc4AeW0BNmZ UsijESxfis8PPC/onpIbUVTy/knA03HC8At0RgMSEdVWVSPbLxyLH7xndmiaMb6Pr09xSaLctHeU oqbZB6kmiUV2Mo4E5ILz836Y4PoePhUI54qg4m8M2YO96Q9up/M9zRnFY8BwA0yRiW5i+xRejUOF xKq+tHaM5jum8kWfbQqOCKPBRT9rZZx6f7lHAmMWKg2yplxLqnreNh8OSqBWoEjTSGXIiU1XiyAT y394MLg9J+WtAH9ibJJYyzdmcwtfu10VhIULrjM1ZrwMpn729+nDloDry7TxWQolzrpTmyKkjU6q TGfClA+I6Q2c1780ZMgXIvsS/bFIqesZcmNho9DQb7T3n/+048xN8LSVhpndfEf6Ie8YMx0doXyi EPvo6am19Xk3HBIPZSQUpLJhJRkA2sStsvEbB2LARxjTvCQ+EcWBDX2AhugwQUtV9CGPNHO1EoCu YL1IeJt3YScy22chVgYI/lotOeObandYg8GLmdsmLJ/fLkC7rQ4/dsGKUSLIiJeAEicIwWuiEbuV zy6IvPiSAftZAIoUmDQZ1UWpRvIiACw9XqV0sCZF2pNr1usOAfavwy9YxnNQEAMGxQQoRsz4F4fY +MyFLO9ty+kcUGZFVKbNnh9RUrPzv5hl4haq3byq6xaIShf8sHFL3YLXRIO/X4lQF2CCLpBQ7PkX u3kSUNOG6OKFKsSkvtm9hHBfRUX37WxHpip7x1nhc8JzT3f4+6w8NL/osW9wjC7yGbULucbfqvIH O/z6f1t9vQsRf/77WVCe9qIhwWgkr5vIHToxG64aQAm3uFsKewMrPDKYe7oHHzLAtf9vHXZkTkuW hu5th4aDZXxWh/98qkwHjnWoyqJpffX8xqE9aW3Qq3VR9KjGtUdCe/kkQ2q2XQu1133Hwhboqx+q 8pEJ0++CwKrgcBP+lG4QfstSJ11GvAvItccXpf1X212TBa309vRmX2hWbxEk8MvSCr4UeeJL3DPQ iGZg+HZ91TdqcBu6526ik+piEZHS71WHHU04LSeA37YWm3ZlrKnZHvphCrYwpIw9MAdm+JyhuqNr yJDjaGEpPTVZJrqL+OulodH9lvMSpV/H0duwCykBRvZtO0g7w9Km6PrEBrY/K27NuzCe7mXnB1kn 1OfIUj/vKMERiK4S7eyjHfdVOPLEQsNL6lzYQYK++NZF53TbsKNe5RYZKTbyh24xlvgjyWdXtMP4 3c0/Yljx+qNRzHgI4BZ/vYfe2OISV+Q6e3rFOOyGolGTOeKBIudfSPqbM/z1nTyosnR7cHbmliYv pcGXNaiau2VPKz6/K5AeWHu358OZ6hDiFY7LCiHn+HU31axIB+LGESuBwz14oTPAkr5w8ZR4KjFi Gi+AzpdZrx79+Si1jVANgaRG+nmXXTw/e0nU7dO3uOULwLFcjJX/jZs9APXpl7M6qIqADdfX8owX +1hNdlT01rEGE317iLwBbSvy63n8biyJiDwnnR4ykjGIIrZmW+8ouG2GV+7kHRc+0PFrfoW59QO2 xmtSyEuBKw+fTIXP4SNLTmtwMf+rOoVa4N/vPCBQPjRGk3F3CyAO6FDS2ThrSYE/+8h0JzIZANyz VEGTT9sy9QJOPclF3djR0obm+urZXYpMeoq1XMQaWAJnj5L771OgJWjNVv8nQJGfZywUgViUlASs +wnUWJ4KHbBE0XvWQ9gei6UwG/OCdwVJSpfjuVUEF5SeIfFVHxwu/LgyjprpJ9X3W25Ykp+v5YNZ SvESRDK1X7Ji4j/XdRqG8jZYNQxFc4roN4j2vbbH3mjIpko3MfPpfeamiEBatN0+VPNbDkPcwhKV SXqd+izcXA05bZd4rj8iYSIqGXZtMQf12QN7k9hAYiWexIzTPEqTICs/4XJZTIm76hlbYEZ3JjO4 0i3Iotk+S169hqwvRkaVgwyBpH2xDw5PW85M6f5stdrQXK7ROhGtucel1eGLy8aL0Y1iLeKpF8C4 kL9pnDpI4dnRccKOSjBxr4MkMdqRwzHBvLo59zLr5F3ggRLYWbbdfUnP4J2/qSw1WXp9YHdVPI/I hWuL/bFAdjhVpM0b8LrpCyXozk+mgE3w6dgZWBI5KZJOGjFx7ZpSTuxs6/l0i2j7Gz4V6gFD/DOZ NBdWk20juaUA+RHzLVpJk/F0akCKnBSAnC0KXUq47EbnUKpbtB60CBY8ja51poLbVUnPkqoF8tk/ VCjv2zm3P8/MThuaoky7wko9/ESteXmk34Mh0cfiStefZ25S9CLnh520rGsM8YBwGOjByLYMTH+C MbsUWOD2XLLuqJNzu5TWSScUqUg/PYkHXCYFJllSf2v7vC41WPcw+1jre1okP4wwMeILzCJ4UCsz RxRftplJVlzqk4sUnttjaWvK8VuFu7/QwAeFPM6H26ky87FMnSF39Kvwy2ZS7RVDuiU1/RR2IKCl c3ld2RmbKl40aZLz/EREXYfD7xrJChAMAHDDa8uL5ujIkOwBkn4Ijg6loWfwFYtqHgNyslkLlo1N TOEDlXrOXxGZzoGfZ2hd8t2znmX1QXWu1VEkNTwXq2ow69LfjTTnai0a7ddjG1+oOacjO1Mgji1F DHTP1iMnYsdrvzKguww25R+YcX27/gK+ejmZon3lfD22UCsNfAfnRtIWeFfQds/AFFFUGuBTGQyu zgKgjFuFXcbSbe/bg/fLeZGvc3IHP2vk05SQLBc4UI7M8sSU+nMm8mFQPJHQdlE/YTKr5CZJ/jFg OQ/TXhNNkbJ4oT3sPXwXoFndVKLnI8WCP/y9DPR82JUgXna6PjUO7H9SZoKKpSUFoY/hTilOKNei apQitBuYrkoXw4kjsZcKseZUG3m0SZK7wo97ExLe1a+INyoZiDyVGK6Oz5BGNyqoi4CIHAViYUoF 4SztQi3/P9jO5NwNXaiKjVyL9y+OdFitTF5H8qwkdWpUNN2CvelgIDbDx/sUOCfFnGfk/N4lbnJB s7eSpkS/kdMOANWzqcyRPgfQUiIhO0AOprHQLnMcZNN8fvmPEKQQNifEp304r+BXtXGjfF6aqwWR j31imJds1Z0ZZtoXlQZSC7D7Clukr8Ps0beXpru5LcNyM21y61aEKcSOcoYl+OcPEnDatuFxJmXy ztwkI0XiSB2b1qqijAhbwz0Tx076cI2NU/2sJESToAEAI7TkPgokJtzHSyNo53pqSjuROFaL0eYL Pqxb2OOPdMfcif8cFC1y2xI2WYklLdbeNlI9F+yoNXHM32TgRgtHp8I0tMvX86tTzA05Zo+i9UzA kHH5ScG1yUK+gseoudZScVDGi6pD3YyC9WWvpcOl5bwJebosLbXna0C201ROUUxQcnyvWgXpyV6Q 2MFge0R67zWAAfCQ+p621K/idRa4LCc+hhpUGxSri75pYxccJtshdl17ThgvIQxbsdfj8imSb0U5 Iq3qTs5GnPAqEClYsEh4eicVQoXTliEOFIRSJKShHGMYcbeNe5Fvv9RwA+anUWChCKWmFZSjcpsR 2OofhkYmIcLFCc5r/2hh88RbhNrxP6uz4j7yaTIGSGQGu6huf4TDOipZPs8PvEKLiyetkOw3vsPD 6FuC6MoWzFnn4hhWa/Rg8+hLLfv14QQyptO2mU6YAQSh4nDIwcvUQg/CL3vU0AVlc+fxDHWtwXaA 0R1g0MFA64DdOdCcvgbiRZjJgkS92nrdAURf8HwRr1gbyXhVYWlGaattodL1deVn2onC71dVIirn W6I/Uyy+t2Ui3dF80nB4+UVrKOjcW4KShQtqmCZow1tJxJaCS0EmbCeiXv5mQ5yaAP0CxrauKmDs z5Sf3yZo9y6JTt6JXTvcEl0UD69cosagUJxza64jvho8M/Jm3/5vdDaNFIy82IiEqMTfjbKLUCBC BB906ikydCU9NQVGc98Vr1nYsalBKCqQdZi//Fpgy66uAeYqINSGVMPhfCN/cDBUd0x+VzZmwXqa l6cYe/Bc+jjxmF9kvnEfOdqQw/GFAgjUkK6azYe2UWsM2pjSpVYuf2w1g1vjh+OhjcvCDsnNnXpe UGg/n406vSimZ5pOQ8UcfYiJUe5MQSTFVmMuaCS3CShYNZWWHyeIqew0J64brwwlRVAx8yk0L4Ni ZH2DX7x+2gTx2R8VidO3zD12On1lhGoVAznIiuJmFjXAYLNPw/cRRrSJl+Z/09ZbDsumd684Ujs+ mxEI1DMEFLpRbCAGP17JMD9h0ZP47UceugDxnmS7gjcZizDWobEKam6Xb2wFq2yp9pca9ofVKbe/ dldRu7DnbGlCQPIK4LlXHIQg9t2WJ7NgUadqn4Q+Ud+FZGlYE2bAbvxGDYYDv1De9gLlOnYrYk8U Q2r7dlFeIDr7ZWys8YaxZqQ/PNg4SNn8Fl5GwY+k9gqi+yKwGo8xdvKL8VpBbCTGAcKHYO2ci85J UAB99sxeKMpLla5labUsDrhXJe6BW8Ute21MZBZHzDyPlEtg9PDyCHyIDnR+wsEHHd0j3e+NvvTK XN2F2YdsusKSSDHxVYIppGpYl1FkrjT10oju0SPR7Am+le2zUxvtVeHK3ChgcP+r6K6pRiuyhTWK uk3kUlDjfE+xP5Ns3PMZtKL5gj3N0z+0O3aZtX+fzkSPLU/3jHcv53CQJCMSiFNGSFmr/slHG6Tm cfJVyJ16ttDO+xnMxmaaJP14aJNoVZUUwjyOYYnP9IQg47xsM0ThH8Bf5MvQbif6xlrjbnCGm0Da 4MPy71XLoDha2hC9s7tU5Otv+7mDv6aS1FDQp8y6IU9prJoUZ5G3PpzBfNytPWPdI3Ix7Zp/uChu B5TTF6DTmMD4qY3hd0B5RLA0s1JZuDLpjEtoqeYt+D+/r2Q4y45R1IHmHhuvNHNJMB8vmIJgB9GG 54ml387tof6vqtvm3U/L04qpz7GyBCdncibySpPSRc0SU0dlMYLKg7v1mEYg2CHWX6Ap3Hc4HjCH Tigb2rafp/g6ChkRuujOGcXtD4hOdsiDZ9IOivF7KLrXL1PAyRAicfBAw49wVWRlfcBFsLrGxS+s 7Xubld1dp8EFn7YIzQ6uPIvkVZu3L/oPetxi22v2NJ3giED0uv/M/AOT+8lTDw+2KAcUnVUTaq/7 GER4qLSulG2oQzpvLrRfBoqE+CDELEl2W2TxOOm8Y81Fy0faFOMMFSoQ8qBYDBkKSnuEKWkqoNm7 ALKwCXKjJfWN8EBmlVsVC0DUPNsRdtMeUCWfvXU0hsVZ70FoKkgItp2vCeJnE3JZEkWG8iFUynrg Q8upmsGoVn8XewvPA6ndsGeLYExZjtAeGmKbQFiCq8dbBis3KzynUHIAL6Rd6jT05QSe1MdBzkel GXDgKPbserfaxmhBWONPdfbHQ7csmKBW7Qz2Yg2pM9Cc+IX/t9DdYlAeNbkzmPt5HvO+w2vyoyuU L/jK1nkpqhWCbNmd4pYlPW4k5gVYdZvfMce5e/U8Jf/bPevsWEnis519xSIN302NgC/H5CLGx4uy 9skYC2U+DjctCYLcv3Vyfcnh2vyKK5QMlyHhLss3fYa/pflADGd2zjFkS/N8Cd1V+6biwndOGdH+ BHapnz8K+XJdCp7Tqv8e/2DVWLfG6dv4RoWyVOxEkrim004rTc06q6R6/Rg2qxAiAO52+FGUfGm7 fJ/YV1zfimULjTp8Iy7JGbrwvOqDzoqSWksvkPKVA1Mgpp5s2zOsFLyrRdaeadkNyRlen64xbLo1 yYoOWXRusjviifOshUWLKdon93kwc7UxY6BL/yS0/Pm2yUCJsb4C+KT8e3sN01ocUVNJ/7GxW1NI Z9AC+Pn590lOCxqNxGXBvDNSnVPnybf92oRVasP0L8C+bmZ7X9MdUk+tHRu5W4ZgNxu4LoIq70tn eH4dzk01996LNYd8eZCg0MIf4zK+BHmsTl0KJHCwnPGImd1WNlyZueba505RI+BM0tPhhlASppKF gJvnYUBwXpX1mEb2wTTizU+KlA2bvVkSNDlS+/UqqVLiV+I9gAD+eLMuj8yiAhCNLi7Pqp0VXJG5 p9ZvI16TsQTXQHMJzqwlxVNNfXwFo7Gum1bs+8lo1px3eSIq6NIxGzOiMXuAQDv8nBNxRFnY8bCA QY4ZJ5hp+GI8ibgZsSgOk/h9sprlhHG1JvlXzkVqVCklkOfCvOV1OXbwytvLH71m3qKe2dyD884A GBMXX7sFK4DIB18jBG0rq+uJI6L8gsqB5xT+Jh06Og2x9bk6LR3TaUhZYVTZPElTysqtO3DBpHXX 2RRB0aqhVvp5p/Ap07PAZQO50D3L1zxQB/TJCYBbRX6pal9qXJL9aNxnY0Qq+JL5EDJ9sJT5CU1x cAJFDsL6edmGybQnb8YoRRQyjFVe6ZdUxdThCkDuf6LG9KAWVaXgTnyq9tMH5zj2HnybxXvUV+rC C3HR88Dyz7ZRQAh5XNbvfxxkzGJPnipxY/EkSLWM5mTagt0QYqOZn2yeTNOPe0B/Fqd4/Mp0OWde c2FkrLPIGKsYHPgv5tClW+qr/Ta2xLemSq/v+5TardPqaGD+l/o4rNXPxnC+d/oawvTfazDbD0lQ pz2fVYF6YgpseZbfrawabN31NIBr5GvOpGbzzF+4wJMbkOad56onJuEh/h4lKZBE8dMwuLXEUOnc JB18SOfZWF9hMpIH1885+GO2Q5PRg9ShxaD2hSF2Q3TCpQosUKrK7C0rgvHHR4+jDpKJPLTMnY11 tkH7ODXoExhn5d9V+chTuUlBf8rYMTJuxr39Akh3Lrv14wlL5UIaOG4I/ePD0cI3jO1fSsx7bVEx DRfmodIl37FWXK+x1RUp3do0XsfHHPzY4fKVI3F4SII3f6HC6MwWl2n0R3l0uL0s490a3rO/WjmN Du1zHbgEly6QvSMKVJPefPi3KszUV6OiCvyslfYHQIGP8815VXBfun6kGvBsZ9JCxavzSiKQU1MY xHwNOh/HC5kYsU5Z4BqCEUc1ylGmtAvNzZF5ZvsgTMMUOfXnSDo3bzJ/yq00Fnnzg6Ff48WG2zVz PT3lmkc059KvlQjpZbmrwe/a1KlYDhypySQBL7uYE6oD6RpdET7D7KQvlgdG5FgOFJUDHG1s24w/ UD6X+4XqZoVID9c0YVJJnPOalVXC2H7pvQM91jBgXG8l67Xx3Eqf3xv2tT+8E8ITm1Pyd7OksRjR ugUBGltGTXVpSfryVgU9WYKdojg1xhAIpIkmXy3gwackwIuK/oT8BdcgHGjxLIIwVTAKkesdRuTO JCyvg/5P4q+iDBBQ+BM2nUAZpuECPaLx2Z8d/66uXCSfwtp/W3igBfBWCiPoLToteLdzEbiMg9KC l3CLqo4JfTSDPv+/9yAaBlOERs4UST9lU707wW8e2+SsBLOOLVRmByAr+IkirxBFXXy6Le9JvTMT Qz9ek5SOmg3J/ixZGqD2feNfVvxuQfcn5DrISx1bk3hJL+pYxXUlRteggmvaR4dY/I2PMdd75maG VkZFMFGUvAY/fGYcCmEPbW8I/hlUCceyKtxAZdj91tvCP8ED2yTmdlwCAXDu9y2aofVn/O6gON2K 883bZBg9ZHOxPXHILkg48fQp9NSCjxNJCc7+r8Ho1BlM5KLDohm6RIbNDdgr34s4aJryOFuwF/IU xaeJ6iPzsiVZlWp7ps9RPJOL1P5T2fXE3il4cfp0vzzYUKhR3NLUWMaRzuw49ulSIprnY2YtzrJA lFJVCQjDPTqjmtZdD+INdX4btU+zs3V1tIvND64G/HXwPkoOYjX6dTUuJOdFqR1iNHaGXIwIyjtJ 8L/2wxya8NH2J+awJY8MiprLSnJMXos0KQElultVRP7pJAkp1iGIIYsw4wo6/pC1z9bdaZfS1yCt JlVsMT8cbM8JX2PNHvY0w1RNJkzT01Z2n+rxxAKMWvSbWf6uT5W0AKmDNem26SGsjToGDj/8mza6 U3fCNlQspGMDFBJFF4SOFuaSexb0uy/Gf9BwXOdOCCE1w2b+0oFQPfqxJ+7MrtLlY6w4gDQJllA7 VAGBPpjN/33rVfmRkfB8Nzza+vbCEC/llabc1b0H/eudjtPTBD8rz1iQ4UAtyE3SZEH5zJVF31J2 zIsTcwbtWSRFQK9znC93M4CZNaYGLz3VzP1faen4jqfm35nwRsPl5bO7hrv8mBLeTNBwiVco+8DG w9a2oS6RpVOF+7I4WO1vUYJHenaVqH1sPfPa6yJq6VyvOMDsHUFzBBy+tj237thOUfSxKSnNA/tt 0Q1t5UWvb+fz/UzuvGoeFDCz7Q9xTsNWlpK+IduuIMrVQmZptH5AvscswuQLtH5qyJMMXko32UsA HKshdzTeZHpBkXkHkppiiromqpH0UZKUK79yHrX+AQXIdNpwZKs+q80iV+eg9isQUEUDUa6f5kXO PkdrT7fef7mBVy1IPZhdQ5zS+AbZ3s8g8nmlou5YrQF7xU7LJs1eqCd2jmoAeUTYUWDKP+696SOX CqK6ZeLQC4nWRM3QZiQBVnzooZsPD4H+KUHaICyYqHfw6bP89SgKEak9sFeNNJQNoyjRcLKwOgaK iZZY9nedGenAxUmHffUIlqF+l7naSO8mlHQ4ik8QaeSHhoJlThR0oky2R4BwS5SW0ECjBVKJMBAC aljivXLanvwQQ/ySIs6JvnHAge/Y4qvRcylcG+cb+QnNJRXZXFvUMZCni76dH5uKfVMciJApwxBw Pee2ObEhVpK8c4L7S0W79Uf4GbrqzxeomBbbyYAKVg10j/Q81rNHtA0f23rPZ8/5C57dLHM1+7i7 BcMkirvtI5DxRt08KJ8/o6vaIb8UIghDq8fgFHgRCH3fGKLEIIhdpt1hDTU97VOAvA21frDT3xec kMxId+mNy5WiDm9lpXncEyBhvg0G6ZVhe35t82ImsnHwkV+ZYHWZjd0YWLCwcmxoGJloVDd76m3X 2nHcH+uAT8SMeeTVhbzrP5FWpMbBOq0sR3kr5twtkyz/JKIxw0FaGwA3bFHTWQy7iwcyckXi/c1u Vw+KXpozjYvJI+17BZav5IZ0GmxCSdyoD2LvssEN0ioFUJfWmesFhLiJ1/yoPB8UfFp5Mbbux2JM xzs96Ywi/EzwvSqQ2nRtCSd3J3KxYufHA09ddK/gETw958kGWOe6xylk2nkJ34o4CT1HEGyVCzm3 BT/VJ41CDl9Mf8LShQu9lY7gIT9DIbv3504IOmZQbtu6nkg0sEw62c4RS36BtjW0LaOKqfXLC2NB AK+iBZUk5vW7QmEbahYU2NvXiywsGdPqyhpT0Ukg11oTxKDDfU2NvFLHrocImpuOOhoOfGIBz8rE gwUVM7sX1BkZH/rj+1GCrqxHvS04NirZ4swhqvM3oByBI68SsF0TypiNQ+kx5E7+3nvRfIJ3ler1 1gBaRHWWWS3E8fYdhUEl/DHlXRj4g3CqG1zQvOpHPgD5GcoftpPHSxYS+nt2z2fCRYGhbZuXZREH HjT58RsJR0xZa8/Az2I4L2SmNroENxmCLenAS5n5tkxT41zoouqNNzmk1NMxF/2bDmjrWMBXebMk u5wzPcRB1FUiIWd4k6gwDBZfQd9GrXaPCkBccnJPJFpxSMyc/YO1J/GfYwi1dsxQtutQMcbg5Ffw oN6A0PfGXtzAeNo2MDGr4xKQPm09OqLWnGY3AJ79IU9WvkCn9hSKaEk9sAZoBTeSHJzj7s1BWl9B q08d7FvSLlGQ/l+yPKL2VoXvq6lx6rZfw7kBTQAlESAsCtHF/srnD/hF+4szfh15UIltsBI8t9+i tA7ha5z81wi+LocvHEECczMwbaUMnYQ6Y4DpMdB9QL8sft1MLXYVdElSL+EWV5zXwbAw04Cw200v J3216wmO46Z/RNzxMwxRwnvMUcOWAIlDKDnSjMaJOOPPxirDKeoKoWX8rMD8N26QFqJnjMRwku5D HfoYE7HQ4nryO6+HMKafdBHY3R2PZV0lh5UpFkwUu2JRyve7KRCyiJj1EWmSPKkc6llogG0Q0JFh cpsFAZ/Xieha1+dodInYmgjM8/aRV/J/0Avj/ZpzY3MIg/79kSugyA77sxbjugMW8VI6GzDHIL4B YhyMeWnIE9OLB8O0h90Auq1YE1kLJ5ZgF15hn1HdKMTxKaFd0r99qYx7rOq70h+HRHXPW/SBQ7/k 196cnV5lAzbw49V3sna1T0RbRh/yD9UWtgAmc7X/9Yd8TGHCzZ1N81q4/eFcSN8KsTVLNtuEsdj4 ejBJdYvFTsMtmh5T5do6rPi1mjk0K22t2gHA+ZXwEq/pTjC6POVyPpXyWqlWJQl6otD6KLq7eari 7n31C7es6rMrBrqL8xLknK50lH+3iJeSFUm84MWJsGeX29lah+wGK/dgCiQILQTOZf/QwFeLF60s 7ytMWnqOgQr9xSMewfpzGqK3Nvk8qo+QdOLIGtpf1usxvnbDMdj7ETjYIPPVdmR56h3Bd9HBqZO2 +F6XSN3VicEbQ059l/SvbbVRgafRrG05D3PI5XpX4tTNs7Ga2GEErCXhQauwO0u6caZk7r06mu2L IH4Qf912qXUQtyKi3G0NYPtiEAuKR2Leex8EyVmz4pDNa49oJ90NmfGgdB/TTgCUgau9vebRt5G8 S8EIFDolHc70hCNM0bCI0MMHdnyPbLJcpw7aEajxcqi6I0LZT/ldmwgtkbJGmJQY00B9duApM22a fXR/KuUKORKXEdYwlPN3lOw1rkPckiwZBg4VBZzVR6P0JAfMvCvcbpAFSBMZmLsA4Xo2mIHFeDZc N01J6tnsc58FqbH53Ly9VB669Atmj+LSO6W2uVWSioaC9+fIsiVfFWPK2xOvLdBJzCxE4KBEcnlI cCImzfol9tajjWjDnBXiZIdWA2xLl/mytjFTdnU4lQ2uUzrk5jRjYYW6fZT1Q19BSrOHDHaf47wd T+UpWSCwUFUZGXr+ZjWC0TLam6UK9iB0JNbpRdgbB7k9GEF6fyRa7VBggEzAh/V7OwONSg1ZbIdx LCEStD7lZbPAYPVio4wfnSZph2C0G+/Hgcc0hauRAirZoLWJ8+4o/txvKxSJ7c0HFtcC+iDezbIE wg3uP1Fy1GtscQmqr0TR/W05U23g5jJAdUqtLslUNopN+dkATn0WML+M1g3fgXyAgUMB/OQGsLGf R7h+JZWNrWlqBJnqevcyqGyIh+8aOEXdVbEgKRrv62p+mjUGRfxXp/HVP6/T3hqDrhRmhx4jXAll U+elovJfeADzUT3C1Ve53L6caPcIHtPemtv46iCNzKmV0i/AnwS797tlsUEyUt6TJSnJ1FklYXPW X8ULxQKlozZfPriWZmfNy/kIH18QDSw3yRiil/+vIhkwAeCzFgUSMnwdDBNA8uWVaNsGHsC9DC/i kzZodzbv3oJcwKN9BUbPDjEXcZzB5JEsMBQqHeXrsmBsuryBfVcXTXVu5UTXleC1mTWDX5wZ7BGX 807puPYqCs+XK9OGpC+vAa85/EFV4+/NnqcTO6iEl0M/jTyv8UlRMfAGYgCp/tiU3q0JN8QIv/YQ DvXroRD78IGTuyiZsvUgR7IkVCRC1Uvyfqu5ZHw4iRJaYGPEjBAKnmou6xyunxRe1ysklMk7xsZU 3AtGgv/99Yb4/yk/gQBcchjbXDyDXgyQ7zCMHBbeCj6ZhFQUUsrsY4HgJEOHerIANl523mezHX91 DiI25BZjJfLsiEldOmMrIxGOCRQBNzKKnoL537fO2QSxBz6WVZ1lN3tdeUzFkembrODYuyVkoc+o 0qME5o67GOFOPSxkVdtfV4NdLU2QtH5DLWPdxlKIQhMNGoCWy5bbqyr6/RzV/qAGLfK9xVtS4wKL ng5lqs1mcrtghVTnE8Am7qF8XLMkaqSBNleSEVPStOF4zlW1UDHHE7FZiWMHB4acLHsi8cVRaPkM EZM31Q89ii1bqRUNZdh8gcun2vyiLUHIucwnkYXu+l8DTJnQjEz2CK/pV6kwWF/ZzFU2/4ebKsq/ rNcKpHL/HZmCtFlPTO46ppVK0uOuzmg/GrW8O558+ShVNq8IbLFpK6/kM5blQbo/Balv+Jb+I3nv GBm7FxZoP31thbojXQWH2ICP+WU9XD60gEjrqFCaNPemXYJUtHayUtAcDPdITulxMG+1l+lMVDgb OSCcHSlIhlY752SU/W6D7AR6oE9a1yl69uaXwOX9Z+C90YeGpEOd1owsHLMpkr0Pik8QPVC2w4Jf 1iajLdN2uo2Hc1UIAfT900PePGpjtlKCqB6vAqkNCN8komBwQ3eaio8cd9jdhUmf+Ah/8nvy1T/g Y7qfv5vyZ73JT9R0+n5iNDedmYEupAyKOTMe4WNRzoI+HtVDOVVI9P5ZkIx/HNdXH9V2yvd6mov7 s4dNS12vIgv8yEyaiJf4h3Xu5yePWXacO3sOz1oAfd94rRxQpzefbhEdOHgzeBxA7273MSboGuib RqdmTr6MMEoVWxC4mG+BwuD2OuN7so+DOyJnOC6QBLKyHA5jqMgZYhhYk6DMi0VwV2OqDBE0hNme 9dCduQ1tFjboriSxI1qmQ88dy7rTq/uwvwZHotOKsyYZcnzkNCDm4xDSiHzic6q8UTKEfWeRTRcp YM0s/xRZXNvXXGG7ebrIbsPSD0KusQlNFPRXoPL23tGViytXCu/oGI6QT5/rcp2jZRZTk5uHsWMw HwbEhOAervFvmJLnU1dkpx5uJO5kIFppg/8FmNGawdKH3/M1MllPiSjRWXk5HK7Rcwn2uaXNwWx9 EeRw/55Zb9BBhCUeF+bA98kN6f75yN7On1hD6bSLwZ1sIlMeqFsDqb/B5dkRojmKrN6KFPQHq8Za vD6BhTmKWaJvb19JRQAaNPVh0PkvzwVwfPYOdaEGGukpnuU9OgRT2jwLCN4zb6prqDYP7Y0axhj6 2P91W6pnfAetHsI2LTaDNW/xDEce9CKGOuXfpnOnbuaGrgic5tUuANNq5YzoAWmggyBL6OXhWow0 WQhOaKH2asr4ytQXqvje0emxlVwRSyT92HuhRuVa7OFd7p1/EY0kV0zQENDSpQ4SUcS5rP/Olzc4 ioFY0Sawz74GlJ/Gfaj2D9B6t9NgwVYvHLxiSrsDeZv0gOGCAprSTPD9k2NE7dkd/eX5rIO0gWAJ sOdORGuv/9NP2l1PelwMtasW+6WbtCswOOZPXig+8pxV48EjmGMlYt9VkGDycv9+ryzLrhMo/MUv tHorAKL+pbVey/kFGhgcOFZz3gVsabVVaE+HPOgDlfSk83h/7lpZgfSdgY9Ge0uV+FhFtfLP6Y68 kFDZ2D1RGJ5C4mWig0ksrAz0v2zTY92o61L9zj7XfwkPbviLkuFmJ0Lbq7nvRCyQqDSUpXQCzFgf h4hTk7eFpT/DaSL9C7RA0IZMdGEMD3mlxiiDRRrKdy+UZbIXLhOqItur42iRzWA6RSrAj9uMPTpN qkQ/APd8JeBRFJCc6ruFGdhkUZ4LnJmvdytqWVwsMhlsVom6noNUB9Rh3HsFyTAWlPDl1PRusHSs 16YREABHEfEsZLiHixEaMdYUa6bAi0zd1TVIFV1a2/EFPUat4ou5ZEppEHZm2m/rvFD+NFdi79Zb hpxY1MIjh1p55D80lPPGDPvs5a9icv/XllI9UhAwyA3SLriz6+RkjFaFOSU12QWNHnfbwkbrsj75 wFOoYWFiYu/Krn55QX9maNMZRXM5Mys7X22BfmAAg9mNEQlbECmjVEQjGIPR3gaaHT8ZontKws7H p3eXI3pJB/xWYPIgxoUnQFP1Mb9oGIIU2nWCpKBgEiceymR5NKFNh+dEFdXsX8rYLDM4t/4qXFzd 7foECoCk3lqbOp9XSDen19uJiDX0u0P0FhMkisQWHLZmtbjuWxeFyaWhJISpsxNGCJaSoo2yyd/8 pa5cBUnnCZa3uoVQY1QTzLedOQMeAwfNFeYg18cqzxO1GbhMM1O0xBxksK4lKL8xMcUCssanhHfD jxQHSoKdxnARdUNBaa4dYMTw3feaF94UuyChuSv2lWyD61gpz100efrbjVyseSHaCZfGRZvJRfnU uKX+UDtfpWjsTvqKIb27VRzeo75FUTesw0DmMk3ZWIPNW0sk0EmVdvchy7LDaDmoCMBfha6VhvD+ VGbVBGGUw2oIK7m3uYq8OYSYhqhT+RRYSRwq7uPb/9AcAeifH4q+FD/wzVRDVsdSLU87BFtKN+AJ X6pHdx4aONIkHXdYmx4cP2+Bzm8XUDgEc5mjlGzvzZle88LpwX5NDtjzTF7jgHiQwFVm9xDoaIy5 h14BsfCHYNm/tdpVfNjMZfGIfhrjpY6zkpX7n8TzqBDWc6lf22Nrk/AMTJ10RFZbYJ92FoSdkGxW r9yM0MG4VYduLnPIPm8Om2IAnHmpqG043DLAnAuXzowvPqcNqt2R/jq6hWPqh+VsZTfEAdc+aGYm WeOsrglQLouJNRlXKz37pG2MKn5JBDWVh63ALrNPmten9/kx9x22O/TAdbZCZVzC94a+A9Kf5DgN 0ql0dPVXHRkNyKu/X7xuQN6xsA01rqz+pr1IIXuawg/JyZhsbn1LFWPxu9mSL7pBWMJBwKorooAy MIglzsUd1qGhZt43b+xgrAcLGSMED1WG1vGTdwN5mXE1gcInAaGK0GvhNzRRcfkQJMcCm9RopVOF VihLFeHBBl9c06SueKKJMcxtruMi5T2yJazLY8X7mjVd4rVmr+5T1Pe3FSkxFM5f0Ch6iAniO4Wd hnkyyy0Pt++4LWFrn+8FaGkQu3EHFdqRFKHwbo3W6UcxBUFsn7JAsRi9FYIYKR6knhKd8TmA/ISW raUlXmRcXjMkfFf6z+UyaVN+5XbLqfPiimlUe2m1msuCDoE+IPtNvxm6okpYYOqzXLpxMDPnyCZB WlIh3chyIWuupQ5zhptymsmqb5pZyVicKtC376wcaJRrJXtwNvCbTVpVGZne29E0mEsGHaKtIxjV 9dsMXc/NVbzmy9dTidgsFRL/wObGCGH6/cEjBEwAlwZXeMQcGXMYLVI1y5bhiEbix6BFnYoIw4xf v5CRCb3E+CTTF3r2K3v6/CwAUkXhZ+dPds6lz+ZFby5PSqsr5YzOB3GcoFXJcWlMt3dgBCKeZ0rf I2ShJ3xvXGyTB0++GLeKMXhBEXthFNP/VQXZb9uT/HKFozHZSl8jPApjFjNXlVkacGoh+yteGg04 bTzGd67FgSIaST7DqmrB0jYPWXswChw+mS87lRxH6e+CF4dHiwA1zZot1XVRKy/MO0PhBZ/j4+k8 NHcVrWzAgO4YNLCW15/Bh8sI/oV+8NxaPTt0Sri78MuVxYQCxC0dMr6atzs6jLe7BUZDhWyouDdc 3fKcFe83P8R0LOFJGOB7fnZUr/tpW+3Q+Ezcb9CHjVdqsUdjEt8inXeBGC8NQ0Y7Y2tuMxZ1CZRv cv3/yZV6i4/S1YpTAkPmohjbVoSft7dkA88soA68Lv/RMD7ktqsyyAAxgLaHJWskglMCGoiQK8D0 4Sd9/qEHclbOaABbz1eb6crPOs5zUkoVTONjuffJuGGmQ2esxAgKgWjBWUWU4+zEe6/U61tzzuqv +s9PZDgFvxSKPEUSaCJeHRweEA9m6cvgzAPZy8Hvl+9fLcn6emrnM0xdC4QIvO0Y+ULermlsyWRr FXFpUvsmaRCYVXgs1khniY8Knl3F3l5dtuW3d+ZHzyEGMQ9Z7GovEijlnWNfuM9Nk2k6u1Mp/qFg qhHtBw6YTDFied1Uz2tffvVPX8Pv0rHx2DtHwFjhOTfM4V1WLwK8LLnniA6Xg75m1kRdhT9lM+Oh HO8BLQeNcJ+TbnhSrhoIbAC8A9UEFUd+AB3j3bPXlMtYJGPg8bh1DsBHaK+jHvnV2eO9ke/Hg7F0 XWp7TafXZy0i2gYphkYL7ffpOQf3xhJrQOQebWLyFrQ3jzarW9wZDYnPhP1YLE1+7b3jC9JyCPft YCO+R+QM5ClXYYIVJkcZfv+hbod8j+sl13aMNRNtac56kzkVMaE1Q6ImOLrn8wKbUHQvk9fHYvSF W5mAA79FVwOzjeewTUYkNLy4Tsqw60B79ZXwZIgsDSfFj+MeE/bUhDHdYJljGzV0XgA1ncgNzAAL DulNEtQuQPxx+8A2qR8dj0FkKl0fL0Lm3VqqYlyIVasj9JRyvVRxumsthsQecfd71VtlLHDIHUBE I8IsMpff+jUAVxPfLkxP9sE+j6ptce6aOVKa/z7AcCtG/13yD7kIEHWRFg57VtLL3jya5hj8dfbW nU0LY97V3o/XXmtdseD51svYDNaNRQGK6Ruuls/F7OJdhYrYDxYvAz21bupOQQ0YsbdTLhNLwVnZ 5fn3mh+Pefh2SzZvo+ZkALGqCnamOLXlVFNGBC9leSRfqZoc1rRU4T5nsvVacM8Hsu3QvHpqnaIO Wfhns3cIzRP8eKG6wpqvNNs6FvPE/FXWwZrBsrv3CbGtYjcg7+pNc0BJIfF8P8O445GpU7WbuG/A PoSlAFQnx5l/kWd+6jsrp2eP1FaDM/9QcHx0FlsN4CsxdJ8yHkrP855/i2FmchyUZ4VKZv0Ylmmw uV6THH9Rs6TN59QP5H1FQpA9S3486/SCoyq+csKIVSqAWbRvNggMDzr+a4QNs4UvTLFouoZNaOar Bk6cW4u1mSGQ55f3WeA6Pb7Sy88eh0FAmCdfovVUTHimHQl9IshBZhTgiPFdyvM+sKL/dK/w/RK3 WkH1yfQJ6lLNlIwstbVjCfn5415/mP1okp+5wrjCGfLceXBUajPq3AMRjCgWKPusBkmS3t2fCAk3 LKXTAKk3XVVitXev+aKv7s7iuoe4Y9jPbPXSZC2BmSDwc/VwmsDS4DBkxXlekHQF35PmlFxa8Jfy 3GXz+D7yaekl+uzYkWlWd17q9ebEbDOimCT0YejXLcG+oHyD7O08XcbBd/VFaSeXJOrd8PWpDYpQ 37hyTfUio4DXQLuN1oB1DtqJ2h3yOpqHNQJaC761flXrmU/dVORcQ4xz9qXununyuIqHiTFtfFg8 7pD2s/mupKwnX4jVvOGoZZJ0eNLCgWtjP4oBW1Gt8E+oSFPK2nBuChb7R6ibuLnGUZy68lotx9vB mgY+w4UwF1AlNTdu7GFe+hQtZSWaQpMlBSrojPbvZWU1ZxjntpdtnVYRomQwpyn6fnaJgIxT3Q3e egP/xcoSOlcZ+6WHSgdPHv1T3D1DNCvzU4EOvGGII8kwl+vJcMKo4ltOsefW5AqBCwnNGZDl3zev 2G9ITPJ9R4O3EvLa+ntbpLrYQjPZTwV8g0AyraVaj43TZQgn4LxH36yS4JcGLkzi0yA3Czr2bbMJ 0DcexXJVw6L8DrimctPcuwmnN+JkaBx5WRYIXsj20YXfqkL5BjS9wQ+tdHsDrCneJvYL8gmXJPwU VlN6hsg5ip7jxtO2kaac4dx25BjrowWcltQFbarni6sZ5Xrc16LUgNnnqRTVxAd31CWj2YFxYWmN 6baI9vOv1K3qBErHKSqngZgH55DxWUOSjzLHqwkCCYezBqm2S/Zjo/2no4qU1xd6nvY3o1lH38z4 +AUvqKAeKX3RAzxtjJT9IuzcioM70p9oGk3eSH9zE2MK6eFrs5yJ1ixfHV50Xbgmbqe9ghpyqLDf PIFn9m96tL3bRH4/oH9Hao7oE95gwh1laQcXr5vJ616ZQAuO6sGH95gL8xDqByWdbJjFHnjSVfiQ dV6dBg1CddQ8VhEgChPI4WwnkU082C2RscrvcmdHV9v+CXMLCsp8JAnGiy1mbmcu0sgBUF6sZ2nW 1kuaIlzkV5xE+EpwWIyGAbAXCR6lJAKapsV3ejJbyNfZvhiFUn1E9eoOSk35iuhSxighkY2yY7IF p+FQKYNctYc+qKOjVHhEBSnSUyCTBKMk2GF0YsDEXjaU2B9zMrZVNnp8/jEtX9W5rhaPVumC4zLX 7rX7PnuIgKsXjL1E1QT9OclLqOacAqUPYWujBnSGwRXhlm6b7qX77jh5TwG4e/aDOgEjSe96EOmJ QE3sIDYKoENcAo78VGnNzlb7Gd0nOi/eIK7MSn4peRIinpRB2qug5KPXd9dePTFz3cHEeAAVMF3A Yl+/6Yi6ji2MBG3QRYtAYXCsOxTuOtNQu3yHJpC2gS3N0qk+wcsd+hWs5jDYIWu2oYT7Zr6J47bc ROnOt6Kg5XVeu26s1S9KKDZR2KNUMyvhWwaiWumLaq+6B12Xg0Y7PQIfAELwOp9d3lU246PO8bcc iyot1llWAOPHTs54RmtGjgK6J44Gs5ExvfQ4gWVMjwwKp+SmeCtRkIe8eVZTGmFCgzeutCnU/ZG3 aH30xMSRELl8owu2YWAVAhIB1jF0VgR7AcakErq9ICVFeIcbPtcYEeAdAZ0vt+kvw9s2V/HGtJ6v D5t/dsHAzbUy98I7UEHlUFqUVWTmJMc1zG00dmf6i3a8aNo+4yi864gewvwVd4MV6aAsbjANxwqV V6Jc+Rll5v90BwefZWRtodUWL31wc0pFWjAzmhrQcxylt8SaETVyvhFsq7+5WUzZuoThEezAT6EA tWtdLIguPpJzbX0/2HTBCZqrnQY8MVz1U5+qHRvcMMTKJXu6pkC2AaKieyxRJdmH9mTbewj7LMQc 9PErS7YhT2GprzP0CF39imS+RKa+GaCyjacVxBGzM9XGVN1YsCtwoY/Np1AIrrSHu5oY1K2cPZ4r /8l5C3Tqpgam/bu9/Eru4L0UxAJlNG9nXuaIvTG01fcc4mqcgDJpphXI+l0pPYn70WJyTFemG7Gm kjx559jIc72fj5J5FMNQ1sZIjl1urmVhG+W7E7odTQPZWZXi0b6nL1IUPsYo5p3nFADGkl/oudER wH6opGFjKhoIcvw1Vk+7rzmeXlRugym8G1OaWiY1v/QfArWjixS64IDIrtr8M0SP1b63VlsrNoGl Tx1lODXaSB8TsqE2onip0crslvUKsfxiIGXhD4KviXhpe+AZ4ZDymEmP2d2yUvIpP2DSIMWaRabs 6L4L4ODUz+RZOUEJqgfofd+ILovzTxRozC+sLEkV9nMFMPsX7g6GzFPR1nNZwv3M8f3FMw3DQ6tv WBue2Xz/WYzG7X9rEUrcu52FxpffwlPuKLqOHQPScVqv+wRdKmGB5vGDojcDf4myxAyHZNh070A4 PaTYG+oZC/4cLAYqqnRwSHlaKPsuFYwr50u+tKP1BuME6Z0PdbCBTU2mmU4v46TjW21Y6/w60wq5 h9QQTbYpsrbGnb6XO9POezS1qKk7EoUj77qqmmLtzsxGLpOD9BKvh8lWwUir2LtijxlgQMDuLwYB S5Fsz0/vrUg4i4sVEkfgDmjxIlHYk3wC20FGVBlBiseVZ/b3/byaNNcPTOMAl5EJvFUgf8gsD2Kw ty1Uc1F6SGw9KWZXwAnN6TXmvBftLrHB98Fk/khHGVn9GxY6Z1mKpyWBgAuARpDRLQLMsKg28y4s Hzb6Yqh+ZGxEvlI7BT4FiA0a6lQWNSshMFG7yb6bhrI/w6jXsx9G0gEvjBRExQUuIXIn2fiQ6e0W e0XbBkHqRMCTjXKC5lC5wccxuR98CGdb3puZ33FygkDdI6By7Xew8Z8zfjMM0aAZdXtASNz0eC5h v5J2T1RqfrQU9It+Yoq3qUIgqk7u1dywqtfRxJjuQme1NHqLosDaLLWHZBJXMkNUrCWLhoOw5twj BYVC5K7JECROjx/WBMjl9giCuEuycJwIKx/CsXu0lXCt2BB50qNwmo/1HQwwB4dizjJPyxmVmUbF wS97VApM5g2EZ8u6zh2BrYvKPBN5m/KaPexN8903k2NQm2WRLcLQq2hthP7xTDjtCPYrYFsj/Nvw 5eGUgJLQE09MGNm7X/VV7TcIFmN/KbdsKAyl5EikYe4fMSWGZ/DBJ2E3gFfSD8DuBUDhnrdGCt05 w3B04H+OUg/cvvY2zk1Rpvf0buN2YwYbTfCSk+mV/D4gWcVgyJ7ZWbAUSBZdcXrkQuuiwgNmbcMw flPngn/A1DlAOd5DCftJfNduk8R2EezaOBBHFR+j4BgDYuSQvLxjAB7iAJu77DfY/3y49dr03PxA St7lRaFwx8l3qY/SN4Be3VEZIUtUXjUGTgc2xRQvV7/lGid8j0oI9e/8pNHtMHIsBLRe3AdT9U47 ZvUA7ACguxzqoz6LGt5p/Sek4UVrYJP7d5IRVe7Q29L5/6t324WWciEB7Ww47KQb4s6y73F1o5lH cj+FYOXxVfPvqPDugMiBLWbbtQEvuo3Q9S8nZg7VwTi7eDGLvFLps5O75ImyCPvj363+oahVnQOX YKoxPmyefoIZW6jRN//SSIzYHra75F8cKik+aHIRAhCu2EsIANr45uG2DFeTy/L0Vxa2V2VewCix fS6uDKjyoV0yMExRYfBUpSKLjv7y2YPqkckt6427Ffb/aVjjsSqjTA89gLn55NjJoK9JfdtpAu0f O61gT4PTIT43QYT8/4Nzx3ezmuOmXBx+ouT4eeXJLSQ1jxScyzzuNvb6wIEpz/igtArdqps0GSV9 34waOMmwzTJmC7u7pYxaRB/F9AKTlkuJl4+k+K0nVMkdpZx/18TEsqcE36CreTNGfn+RmGMufvcv +VQi4WOLBbfMn/dFotgJTja8qGPXY8v0i8wgto2Lh9Z2qv1ugSxosT2FQSezF9f21EYZ6IEE5aJZ 9koXaO1WiMF8kQkoXLQBJ8F03gvsfA2GYoRx7T4sfKIzICDRD8cUeCpSAZwkBak4yqXDyUn3JEnA xO4KmTpaWpxabMLnyCeSRD0hg26qntC0qsvjKoQfcehkd+8wdf1nieVilTcvHTWx9giG1h4GSFMu ONx4Eb3epaISgHtxlXQOvgPSnLrGhfwiIWYuIwWYAwWVxSCgPpjcB0xF8l3wZGGnQ9nVWcaQLpfp 7tD8VStcYohAqG4J7jGohvv/Vbday9201L2mV7ss6ExhfTorlKcPhRiVvOo9wk9s5CxGID7aBIcf s1wvKWmzRpnhk5/8iurMdSwOvqotQHXCTxH/zPi9z87W3fI/xswVKOXUSNvaXMn+eUJtITuNNpOj +zIt3yNwmcDqgzW7U5/rqu/phiZ6bVLVmCd6bEPym/4HMzJNK7XLVBrnP1i3wQbE/Qk4wt128bX2 8fvFBKX8OEyvUdl6oB7KL21B4EnJ+MygZa1BzwjQW6so3xB7nGBABMwJya+frhkzq8jbKxHKbehY BH4e8LOTk92Qr9hNnfg8r9WdGMYlofKIPyOIbR4wPrvLxI0/F+6v64L5HbcqHj+HcTdUCbxpzm8E XKAIk2KEzTIAwGYFzVJ/FQ5sHOcfc6WENHRd5xG8C0FgLXzbWg9QVJ1zgPwpx3Nd+pTGHoqbcUdI DfB0ZH1YYbNE9WmvHRPpQfk/tPK65AsekGa5YaGat6T+IQ2GO4ZWSVUXbHJZ3njcked8PEnY3Ru2 OuL0jeYovN2Cg+/TwixGEV7Yy+p8RE8hua7rD4QtUiMMrBYw7GBQVWOpml1w1bPm+GLc0IMpLUs4 0XCue3QJIxcTc3gfNfq/YwB/avrb31mRPzZR2w4eXGXzdOanok7uuXePa0CF1tryo8cvBCePudEZ 01mHBRH18c3kkl+69vl3rQldiyJJos9YLHcu6h8ElDl+/4tIOrKAsD+rIye3NvzlVV7Ze9TJhX8e 9H9HXu64uzClhHVa/8bKlBx052XPgesINJPs6Te8sFJaa9hpTpUmm4oc0ECh665uk6V8UGYWS1W9 SKSGqhN392ygTXYJHRwQZlPaE8ljS2dzY/qSuPKJyteWDdepTu4CI7srMuXGOZdpRB8ENpk3KP04 mMa0rPvYVzkQYynPNAlhEBHGZrKQ19naOaRpC/nMEUZQ8hglpj7i1r95dXvajYjGztlGX37zJnCO Qk9rgqK/CKDQNngjB0V4RVWnQ8k2JXau4utIzwd2UPQNlWsDh7D2ItFMVxdPwYfnxBuho8sLZlDK VENd13mdb+7mpH+bstyz+g0Fj5CsQ/5V6vXp9CZDY71QcceHtD6MUNThDQZ+JSVtBGhdBCtX4HTM HTDNCiF4wI91NUtCZb7ewVzLCIiqUf2ukUSt61K4AKu7n39hugupIqQhCY5UG2QkYe2XTCRaroFv yZ5vG8PAJ7yX/s4hpIOHaV4NAlk74MEs81dxrgBKlhA8gnYIOrRtqUjFVnHqjO8WXUq2CgwiUlVK WFFnyLZlg0KHh5ckggKHjVIpmdqNyeJOPyf31iQh4miRQ67Ynhca0wzZ/b1ILoU1TNI9S8pAHus8 SPXe00QpHu+t+42BGjSNB3qheSbzJNtoV3WcLvxLw0hu7GUtnvBdEXv/7mFWKWdCMhBT1MgUV2OM tVp8R993UM10iNdPJHHdONXkh8JGmcOZjx800CtAnW1Ya7Ut4WaLskwf2QLFKPS2NLpoBh6L7F45 bE5beublFGtUse/YlWur5WsUBqJ/FQ7Nd/UcSd+IrJGUgFogE/RFGdiGipnGjl72KBm6WfW5xvLO +9QQ6T1HNJljwwVo4miVhNmmAC/Hm/ASiI3ZQ+SKjHUk/uBRjIRNo+1DL8HWGj1Zryk03KZoJLU+ x8mT5Iq9nKGK/yda/e2TolgFPiBS0NgdvtYroFEm7YM94HFNhN/W19pqT1Fu2ieJH5lH7m/+/4MT GSHkeMR5uyopLmCSKcif6AEHjD2Zi6p4xAm9cRhoElKtJ2Ug4MYvR39IVW4FD0kyBYj999peKmK9 1jAX75F+SgwGRArxmuiT4Jsq49qhcD6bP5mFvOS3Ues/GH0lKwUVKy3D0L1xdyvs6BXaDJrNVkyd lf3QXgSCwOBJ2SmS5ZXY7APoUpB9xNqwKAiJwt97iFV4UkSK+8pNFu6uGI+3vHiEYDSLhmXIfvgK ofyuD8glylTS8Moe1ygvhrSJNA1Mqam23AHRxSCG1zlYV0XYQe/3GtShGybctTKy0Jz5CZ80QhYi eHBGXnf6bE55v+vs+8mEO7R5jLV194XhalplK/Jtg1/ohaZ+URsinP1mHCHwos+ZfCz0CGw6VV6D s3fUv3IT4rAq9q+8QfcoHDShXv4WgEJwLYm62SCzkcbjYhPAP/fbl9nfgvoz4qUTzRkbifRnOAw8 FPES8re2FPdvzlqtR1QcnV6GhkiSirH4dizf34PHjGFPtB4wyhrs97nZvfmLqbwg3DVKIPZkoZhx 4VqjqOTGbp3N21l7rTQUeWaycO3TvE6jh4HTUV1U41vLEPz9ebJ/UTA6ml51NhB1190XjaqKdRnm 8G2k97e3a6V2GDmK+d/mZrTtwQKzOMFy9gp42Y0z/Q38pnQHVKDOny2TR3YxhbjKLEv3bxFG+gyC rcOmr3fSkpyyVm9sGnYrePaBFVndB/6EaVR9NU6jBd1nsnWJVCOoVRCnRFH8Ww+b4FLV//BH1cE5 dHndss4xYRyuXc+IvlDBEOZGTEJqgGYxH8eGTfY2Js54uoEOrhE+NNULsYbp3eUJb9mdB1VNtQt3 5YxTL0yE59xfXTVS84XFo5WTHCSYtd76ylwmNtPLhSuyslqXGt1VyOvnOZi9MfwA0i795v5rCWfp Jt/Sf3vUKx5c5T469E7tmGt7hvORNbc2fntDdISSR7vYJG7xN6ATSukOoVAQfSk61VaNii2etdTF CgI59tBs5f323ilqHxqYVOdiqRx4tVbuWbFkwfHJw+wmJ20N007Own/5ptPyt0NJ1/QJg6/WR1ft WF4u2WJ1z7S5pqPCkRnw0ikh3opTMHdmT9EaqFjwnc3MDt2j5pK74+H5dr6F/YBdjatjSEJUcgIr PVIwLbZn5teqoLI60b2tWmdvwKBmW+Q2URUXHzdXnoVQJP8SFS2+/n9TJJJBaW7o6uD4wVDk7IuX /S7tCFI+qvfOvgAvKbxthVCtzaD+3G9h1UaTJKlCbLUfqYqPnujsnqaK2wBFJxcO74fv+RtxiauN 2t1529XCIDBKn8ghsFeejUiNFtsYTG87xEwavkKAervYqBGnPGweZoSZqITLzv3YJO+MY/UK58/N mllnYwM0xd9jyyttKSfuOTgcEd7DBPIC7iVfVisuQqfBU8Xt3KWPe8u1yIwbdPo/068SXbfuPv31 N8wzRF//EUpP8n7HMooSNvVWJr61gS6JUW7mEOwzoajr7VNMRKcwRHVijSxEk9ItDksyuWc7iOs4 dOfbF1FOoWtY17zHFFbrocVLkSp+XrAZO1++QN+03Kqi8ZBgCSvio/BQpMLCCgD+tJMKdcBM7YMi fe8WXm8lxP6AAXPll/RY9JGDJCn2XN51UmX1mF+F0mfBJHo2kzw2GS230emW8l31dOa1zN8qvO3S Tb+lCJTCnpg3fenjkRPdZ4tGGEuCnfxMLWVUu4Zph3N+Kl0GEkKR72kH40XL7Ix7+u1QILU8mAYG WGma6/Wd6x8mQYqY9vz46n1KjCit+3DRmtHFd1HByX9DoBOVp4i9DvdFvaOHXZa8MhA6YBCfH1Z+ YiQN/0xl7HqW502WIuy0AnDLNvKgEaypHSkcZQBCk1J57JgCdlqajtLsEGa9Nqzj/IDtTDu4N3pb bXi+/j6TOCaGJy6wZ43uZnD/x5dorDr59t7s88dXrX3jUp2Pn3mLphQVCII7BL7fUFILBS7fB6/g uVBZ3sj08rSqzeL4/ncdxsBqyN/v2ztyRkQO10BFywr6vLWI3M4Q5OF3qhyQlipSkwvIcQ7Y7bH0 U0SD0ACcsBzq5kVXjPUZ3pKlSaTNupYTCKzvP1n6bl0v1DORFhjqCEIk2LcOOfs0iQy7aUC7Hb4F 73XhD85QmdvqYzPV4AudpbidYfzddDkJmTP7qJAwk+G2Q4KfaeWZXFL3TxMQxL2dcy+a0yiF/QvU k+Nv03aLztAxVokiFDoJAWnIEpnAFdoJ56BKKcX9XbB+60CdgF8qOpHoNsWlaciWTXpVej+iZssH D/tWLPpaT9ex/npnXCrYQzTxbXeoUbV8dX0/qpIS0DV8R/fHUAkgCk+MqYFL0aXg3Ty1NlMZ5Urp 4PWNNEJMTWvzgUdWtixjmSvl+vtXhrtL0iKA8oQvKOEBljp0wnirqvxzPQ0a26f4UrYvN15PRBNC xq4bmj40LVq8ozGfAg7IeB4k2VxqXDLB02ss4wGWJd3Pj5K8GSQ+z6rOuXS5ce6QaWxv039JqEf1 T+I/DHyXKetdMvzP6qFV0iI9qB8X2S92jrtHERWHqHsG0OVxsdq+AjOgMAXDpX7fPLmW3eG7XAIG NHUIimQLiowE+Ne40uc55JjS3A0lhLxtp76KHfJfAtlB+dMrBHX12s4QiYkC4gXyJZmgR2xlovFm +J0l5MGxiFcZMxbyjQX3KSPiTZxpid0ABzJ9byb2S43Qias6UmZLX48UvHGkP/rXNt3KQUYmdwKd t5LkJYeWiBnv1CW0qPU84WAxjuDkoGgTAQX8/ULp6toudrcdnGiAyteVFvB0mcGKjQtJsadbbqGl RU8CE4IevWi1Ji/j2nebBZxu2q6FZoSQ6frV8Y+dq3skfFYcyvKtN9WS7bWRJ1uUp9bgF5ZZs1ux wFFvTvknghgLD+Dtgl0KkvaNbUY3bZ9q0mBddJSSIMiJWFoyQQwPB74b6GUFzyi8+LTzETLWRjeF VeBxo+nXJUNpaUGKYviIt3MvIlhrfzml8J8DySmWMLj2fEhofodAazGN/QkSZkh56v1VvN3km01v N51VtTZkVUWBe8CKC8qCumDiNAowbRwlnx5TOuBSDcSL6F8H9FOLnfPNv4x3mhnitH6gmlfgWMYC FO23enMJ9otn1sd2Nebw//mB0riPoexjOXVLFm+cJWuSDD70hyBOLGc21cNRh1wPtbv8FKUeW9LO +bPqL3CEBqBPgXGNM79asfG+sV8HzVgofz5foeDVvW2hzb0viDfwIiPoPXBjgDSl8J343iOF5CWr EnwShqWAWp6h6WGbzp0TFqyQNgTKjcbh4HI0B3Wk5XxlHd8Vik+MFGKRqXCTgrwlK0CIBge0prWk k/qarMQXRUiX520nazHJW+y559U8xwa4qog8eN4Tg3XyycXb3XaTz4YohWbxfr410gVNOw1VMy5j //KN8lFKDSKLJs0mUol1DAjlv8BIcyZIdNWM4qnXxMBxmGPVoeD7J3iYV1arQ2Tc9ydZpFD6Yo5i ZQpOtFX9jLE0FRxiSAn7h+/1mhIN+O6pPqzaMBKnr/huBTZUcBLaZ28Kfa1/nAz0Dr8MrmINWKpG ely5a46QqTVtAwYY2eB7T0yE8y4Ojye/rTeVlFyV6dcm1P4YlPCpASQGtrGfIitigYDZDRsNx8Wg 6eUce3hRuoAZczgyowysdxLJEvi+u/GMjyMDfvDh+8MwvbRKQKVepAvRQW4FBg4aSGLkHYw6bGCR ihQZWNy6Vrsj5/zpP82dEnGUTrdpL9beZj0Dyx3CZPGM7Hf+oEkMBsAbaNJ3JFupTm2Doal447cZ XJt3iWq4HpcBVdSRicxcl5VYtkNs1rCX7uKhuqof6EEF+62EPzpYj5JidL6wcDrMmQ5cfuQ84+pC t+i85gBE3s+JqzJK7+SfhnPL5aw/W/qWgSLpzojEfAxsTvzVJWadPzoitE+IMh3a4M6nFy0ZNGg3 E9vQoN5dzZv9HzHe4evSkDFqucl1YhZUYzUSrAxEvJtYpQvH+wl1jP/xdpF2irc+n9tOxhjtBTi1 VkNnfe37KOBQwGnHgPcBxYfmhJViYaQcCetRMSrKrpB87L9UkapiMNVYUZ9y3aP0cd/I0JtcQkW9 UVB77FvuBT41qlelazfBX3CBDeiFP/aLfyukgSmZ6CBFzfK6LPmRDp0lWtyAEKEtlh9FplS66dYB yjYv+BWfI3NB+aIeJFYmtqNJ2ZVjPbfsLtM81qplQZHLd9nnLyPkMbrPp9yOVXR9IiICCuqIT9rb ImrSRtO4l7V+CF1MIhmH9VG4FNBH/FK98NiWh7RUQxLlnohMelt3s8jSq3HNeawRXCyW5LTVhrVe vUxLerKTDUwAcEVe+YgTINKmSiU31fvh1MZKI/4bdOdcs2wpEIR7V/I37cowhmAQOicqt7Iv4PbF Aq2+1YRxNcS4mK45fDCg0jfrNyObdI8xUh36kbMehQ14jZ8W8vXOTJLTyCNt3NeGO8q1WSXUQRvZ 5kw6n0OoTkZICDDn8xYc6OS8YNvTN15jV7E5Ngcpb+grAAqk87mUH1Lplpt7jxz8sjnvQQuiqQD/ aHlV2V0LnefjFpLgdp8Z5KBgG/U6cHhFj2S9zmoPLfk+6aga0aKzjz+JNcqABtDi44KT0vRJ122e ZgJT1pC7oBCUtic/WwCnHf1CqzwIbBt6bZjjzPDK2q7Ed5lcaj3yvA2KGCXnR+abxGFT7PmgNH+F U6DJ3S6ySajaRwMxG+l4WpHj3V2LKgTMN47NFk+6fcUz+6uQT36YQVjTFyDCX0kDmT5J74yTIF5i MnXoUgYw86YfgNSMzLPo6Foru0d5ZOtUKdhZyxpWfxmG47eWbhjXrLchRXEf3x2bIDOeurgENL5U 33qWE0VGYxoQAWkQhDncqt3ZLrwuPHPNhOpZS6huzTtJIr8GwhMCULofLo+RmebdgNRPTQXMLSU9 GEELihMAwrXX1ptUGB/63oJHhDQ6Qa6RtJFrFEftTFqxGSCuXI36ff/7rKaY7lBC++6Vw8GhT447 +IKu6QG8cSsDNlXT0/dyFHIncBXlByLfl0Cn+MGwDNRORpaU+Imi5TYq7Kas+gzJPx96siMX7nP5 yiaaCGJMP9Z0GJhrVrMxwrKTn7ghYL/5mYjZK498brKina6kCjVdk4zCeb9g46DT25JBfh7fMKcx RpNkgnb0nA1IHxIqXLwxmlrb1zhoWG/CR2/liwNSbbOF28KT5qSRSHi+pHr/ND6J7PpphEf1JVxF qVTbIzLCQC+E5Im4nMF2+eGTwATa/hIuOEU0pcHOadxb0CH4N6ltI/Xz3NdnK+vVGP3TYb6WrTSy +w6V5FSRlEvWddLM7UpSZyhGkfv3dMjWto2+Gtf3YF5ylHyyblqLyNab12pFqtiOEnThM1NP3dGo +FkRWgQTfrXzOA9FtlUby4BCnPfsSQZ54KvkGa8rt3LGdVUxjCM+l0R+767VmKc1MW8Te0e8jJ9A pLfP14XqdfcgBIGoGfQEYBqzbYW5cAyp/PHjqnyfjYwCx0YIwKGra33M8X/7++mAD2YhYPQO3RIt JNXZvZgit1k7VRfkLC8nXkal3IDe55EXf6rz8tNeR9xOK/scKlZ2usFC38C66hcuS8spSasAt2Fz WWytPr3DGRYjOr5rACTM/FXyGs2S/zlMN/O74GrhQ0kIp6CI3RjWQu0kVeotvezdmzNZPy2jHe5/ QMQDjN5y/cVZYrdkKtQhceZoC3j89D1NEpx9M/POAkk8dLBLlxxtbeTDyLM2Ol7X4KUIOB6tNX4w kZ2WjOiv9IkwDqliAWgXY4GE/zihvu6rRTHnPoVmrsKriWASzZ7S5k7KWaA9nQj5wtgZ6RFQGLPH 21BI70R9IvxkC+ArDaABvH1H7mcXc66xDMkhcLWw5nzuImZ75fElRR4vknU68rbjpC7hF+xrZIZP khp3SVxAvYZLcXXtS81nq5jTG/O3xeDLMOgusNCdtpR4v/6MP0Kc5WyrDTvG/6ijEeTuIliZVWZM +kggSewWIvNK7f0C4Zjl/A2pIQSu8IVvfP2pgQp4zRY6Xd8Xj1dtR82226aMWZIIGPfs3hCPrOnd sw5GhK25AJqkS/ussmDAoBV0/TSgFVL83/xXYdi0yn9GnFCB2uc9prVO9yFFtfbjl8InNRRXba7O OqawImSdL6gcApzs/XAVrEy7wdO1nT0d0fqTgYOrNOuxaj228HFg5jlCN2SG3O2hxXr5TRDRGinO kn9H+5anoTzDT+mB48ZWXnt5Mu+3/19QqeIL2uF45KwB42r7xMLVlAxIwPPJGMi69tdrscPk3GEj PjOjhcvGgvMO/Z5AnVjKpfJAN3S4456WdZJECfFSZopagMxDtTJwwjsNCprhm9IDfY+HJyOU9S8v 9H3ymZ5h0u5VuIuyUxpfeah27mFsZWgES2i4976axvQTDyD4a+QUgVkEK1CN9XkAWWDsyIFv7LEQ pWKS1HzYlWiyajFv6ZjiPLPPDhGtWS/24NHOAdmJVbiqWw1fr3/f2iBziIU9+U0xq06j/UIHg4ut KkPjrdhrMS/cDkO2zCtxAEkV/LfXGeQJC6sDevEYYZJ+mzTmqn88xPfBgoTOp+2+lIzEvIGWG7YO YPNzOxWZt8NuPp/J9AHY7h//VVXxFjl09VaOTXj2NP1qX8Fpews/jzufAvVczJiYSts18M3ZdkBS lFXss51t7wtCbjNDA8ckHErfspZX0nR1Unea4z4GNhl28ULIQETLjP+VTr2bF7w98pIu5t2ScOt0 g4Kfxq9crJWUUZHIxUP4iqUOgsh5ycK8w67+uuumsjPqtqKvI2W6z+vkW3Dqsy/cMUUygUTWfHmq YJJ9fPwtMte0tZKPdIQvOryNPSD8xDBPkD33c8+M8J+QMGXEbM1oTTu8U+coEyEPf/7/vPX1tPfa iTpJjbppD9OBCFBz7wOa5n100BQxqVU8LGjXslKqzGp37VZ8C3FYBDM+E0IpBjHVUs+bSIdYhu93 +VnfaiknFNJizimymtjrOjePDbxusRDMds5zW4TmIcr0cwd8B/5iLhfP5MgCnhZWSV37U7rqLuqC dS9PAm2fUO8FTXNdDtmgHm7kCeAjh7qpPSnydbXEXJUWcHBS5SpV//5Zu0THJmhvCL0yD8AAbDFd rwMgMbtznerxfrmcmyb3Bj2VnLRd3ztMNMkSaoGtEAK1KxGicwr5VhayXwyipg+pCZ2J1Kp6eFVI NJeV+5Gw2piV8FSAjY719QdVLTymZyd/0TvoOMRo9BQq4aSUd/61pFGQb20EOhBtz9GfXWbG7uf2 GZjJLRbJ+85IouxRX2ZllR/QL3R8FXQJdAR95llOYnRusJF72EDM88bZ9Tthd5K0o1JZlDOwsIG1 YaRA6AsSX4ZmuyieE4mxN7AmuJ5J1vMpwY+FgN315upXWql7zO3wNlVtpzPO0ExGZ5MhLVSVfZZX iCCn4ChiCmCJzwWw7YagJiJXk/ekzbKtU3p8N6lqOYdrwdGhBRTZonJMquzXGPIyfpqsIpm5DWDy QzhVFuKt1WgpfK05ZjwVell2+hTLr4P0KC+im1zpKi5G3d4IfptMUPf0PQHjE00C2HFLsjaJdBp7 IYdKx68QOGbu9gL4T79163U7LCAmNPXzdMguNfk4hLf6c2BnASjDu1Coj4OXaPUXvzkgdw3kHvxZ EYz0YtctNNMCO13a46z13Nf3qFhhpEuJnxigKPW389bFHU0QE/J6Aze9jf1MFsNBh2K7uhc5WnO/ FjvEsKxzEM+qfSk76gmzBl2WQiHgIsJMGWs3a1mg8nWbjs15oH+U/pPH+zr65s+QFeB3cCHPRcpL g/GjfLpf3Gbq0lDaGbb/PWz6HK3RTU9GGBc2pEO6QWFazAIDwS0JLbY7f7Ye6fM8fZ5WkPW+7V7k +/1j++ZVHMtySoGkQjJVggnAEx/Ndmhu1UDLswOOKLegrUJLHki1I84dZAS02izX29xQUGWyhVQH tS8iE8XotjJnkLencnFCQnutoeCvrBbkPUjniEbniNRHXYPmM3XHoatNKWTHMWCNBQkw3gAVHndf EaimueDwTOLtCqwLvvaH6EIkKn+1c4cQO5yH2WJ4BQITzysy1Cv5JjYq/eNWgN2gb96fviSOBnAY 7jok70CH0n3hTRrpsnTqC7UpTFXcfDdWE1Wr9Q7/AWGic4t1FgWHKbbNR1pdVxjuLDdadDtW9VRp MhJox/m224DxoJdtW9V/xXNajC3ZQAu3MP8pzAtos62t/ybjg08XfQBt6i2Jx1WGamMh3rJw73P9 wNOD56WGDxYh2kmlNNtusE1OpBdvUJkWKLCHN/ksg3ynpbULpwJPCv+SdN9s9lO0wljKHZzUAY3L BDOu1rjM0kci6os4ImS9m3ALuj5AS3q/IAIYoaPsUd2/jawxolIRfJvtdvuLFrabwpBhUlSjcrt+ YqKPA9jHOhX2vGME6e6+rzmqK+MU+X663XwFPnwIPr7hKNbuYEEtfe8UOeduNIUEcHSUI2iUeikG MMKEVYE9mBDzHSiPcq9fCx6ECYed2+7Y7cymOgYYb3LeaFXfFM+n0SumiYpkukopxbB/gSGr16L9 K+6FRvqsnujr2SnaPKs1Qohd8kS+MWKMrrGHEW/Bn0xhS8GWgf43NhoxicEI+fnyQvYMO0oUiaI9 cXX+oal06gsAzlEmq4/uMB0s96wDNrntopJe/Fi3R4BU9155sED4Jq8Cey3g3sNdHTawU4D+D/GU VSoaZLrs3hBylNWmzvcCvCP8yvn3PVWz6goeS8+ciPqEYZEJfJ8ldbijwun/HTBjvW0Fg5t204SS 9OWlmUk+mvIDzRp1c3ZFYuM33DMxQZmzj4dO4I6cZIub+gb4jj0L7hANPJsqKJ8Q7I5Elhm7jJR5 W6Xm4CHomIlmqjAkPmdV99Mdefm9NKOugMfOVzUwZkARGohUyD2b3dpMajzgtd5dkRGg3YbxdjjR nu/Uj9jSPtqf5MXBVCGqOX2sf5PLBNE5leKyu3opcVaMPIFqUh9MaYVxFNSVXUv6/tdWbV2P5Q0S Cw31PL+Dz3hxIQEwLw5w36HFLTmDEjrrvBUPdiyttoHRvO2GLu5mCS1bpjdGOedhvKoG5wwpIlLe s/u9dIiVp3yEJhkWr9Sy/+kDZkKFYo9xdvOlKojgHIO5ebDd5K4Xjm0+xbrdU74dPDXIm8993BVV 2XISPLCZMf/uu9Ei5EnMrrN9+UuTgbChKcahyulgz4XZxgD2+7MGOakLGI2ZPP7JCoy07Mmbf89m v2qBF0nQ3j32VrzqUo3lsfDBDwKQnCzYkhmyc5RWZ0aVCbkMj5XmzzXDl23GuMOXFYVIUXk+qPje 4gSoqt08f1rLeNgaouEukCYYJEJwb5zzAPDszMxiIuyZrsvyzz355+D1x4Qk8VJfyETU1faH3HpN Zo+369y+lvwbC60/97N0QcwsO1IW76oFPIY1eBQZ+nFsZTe1RfHxBqiKj9ZhPyLFkfKWhhVTYM/5 od1tNEkX39HyRfqImvgrK27jHBseVFKPCiNHFpySRyySgnu8VRIX8KRlauCgEtLT86RYUgAUZl5Z EH6ZXSLUGVXmoPyc5ANSVl3L16T/LABHMpx5R8kExwQQ8zCW5Oxu310VhNR9yejGOF+EDeQz4Irv d4wGXZ+LsjDk/EIRTPjNx7V7yS4TT+AMAuHlTvziu31Qs10ybBM+GgUxZw6/aY8oHB/MJqPAA6oV ZE5SdApzIS2aBsTBjT2qtZZuiCUmSatacAWS9Fb5OGf1cLu/a7WtsGKhA9FcWxQT1PkfAlX8kR1M SMqpk0EEzVg7EHpZoIGjbM3fCXebSI8ReltZgn9akHRd0TgPiKitO6YVR0aFuh/HyAN+d7+2OrZq M4qq3XoCWAifAnF7nc4oaxhpVx+05EnXQD23BoyiYTEe7bpMowdXzthERxSyJ2T6+HeaWnFh3ScJ cSJNfzdVMtpn1m9gnr+HoBXA4G/dywPSYW7K374nvXX8rdlP+LqEGt/HA2jiTIoMRA9QeAjsM9r5 ZnnU3xlPyy7zutzTV/w0pBOPWAoqdZdkDFx+6iDDWFWBrkawGWGo8M9shUoObPMbrfQFHxZ/jTHm n8M9y5VnkcBc9sLcotmAMJDfP3hyOFPyeQLBXAdp8w0xhU57trXxpOqdiOI3vXMe3yorO7EG1sTA zxnobr2T1PZnyJstTA1ZItLd5lMDRKKRuVpZQILAIkNAop8DBTWNCTtxTbamOQCh42hesMxUaYXL hAFlznYkPxzmAJPKM3m7TkfAE5hb20FPqzuiPiGtHMxQZaQIxvb7T/Mo8ClZ+H+gxO80XP17YNJc P8HZ09m8uMwYi+OiUvYOKPXXR2HRo0PlgCMNE21vwbIgrHcjH9ZNFsnFXLVEuqL5eY6W0Rk5+Zyf 4FEGB4agl/yeSGT7l86ctLcQo7fywDeTxluD3fCvTWWbAooAVa+xOYWqL1rCU6hDHaNG967RDJSb j+Eyg9vqbEo9ObViANJS8GibkCRG8MlfT4faVh9VjpQE4uKMYOzEJBwsNk2wkvGV6riyRcgqTy2A IZAMLQsBmqtBpd9VBHn5y8VAul4deFHjjqebFcujX5bGOQsViLDPPYrhB/ceB2zlM9akj3IVhfHB N6BYDCTaMZNz7j6/BptPJZArhHk5OltqakFOiM+ohiparXvBCrlIEvr91wTPOXFeOxxgvEpJ1rJD FH008LMd7X3+GvJpNN9D2qaoco98NSsijJxWwhAheF0NiWTPGWwCwHNQdJRVU44X35JpgFSn8f6Q Sn8WM9lr+YZh2p/dLV3QvGJfTr3Wg21rb/1OI5iOJgP8Ys1iTRg1x7/zbXOY9w/wSL66itzEGCkt w/Swvzxm9WdjDZrjC/QSJU5AyW/PWbJ6mSCE2bMEgV7Zs5buAtMDS4U1Bfe3cgfxdS/a3G260YBS mm8G17gaBNz40pzOAt1TWneSTiLUeqB3P4Kpy9q3hwprPjChOw7Nj6YcAIV91pZ2m0xTToMHrW7Y jFHh2uKX5/V08LsyHRJiaU/m342tAgKw1mELJNvxZvUBYylh1jg28GSP5KpF29otrkkntMnU9w8F Ibjl15QZ9Yg083IWphj1Ib9SMU5Hutgok5yWSUMphtFX1/Dl1Vg/CZcwZrXl5tKFK9JFQqn3cXh4 0kqI4ls8I6ibV5C0m4QkeCZmlTifw2+lbeCZPi4Y4ZEL4SursqqdUaF7aDBDc5nIdl3z4xXuI13X qRq4u25mW+zFRIDeaEsr7pwsCZyP7oKzjSmsMh9nZw3iri2np6X+LKX9MXx81+8QIWvqC3PV97un UlxJFrOhIIff+JsDakOVQmAVQBlQ0HKlY1Ye/DPAW7pWU5KkzU91zOMzyXXJxDvNmrPTWMSk0wrj rjENxGCPYtIalZZdXjgmn/iSKzJtts4tVYLZ1QUS2OzI0VtpBsgBzGqPQiHKipyBzMoksQ+Wuxjx aQMXZMM3bRqgCm80gc81kMnszlMgTJJ17cgJu7krVKJdP7nviN971iIY48ugaIuwdgc4uczohs0m N2cuzTrgaHE9nGg5ZtczAAX6x9xJeqwnkBAR1x+J7kyWIqWWlQiez5YY5M1NwpfkY/7YsUBCM4L+ 6+FhRNrtdxW8j6fkpopUhO53Jxvlaf07aYQnJjRzZADaqYmyQMN2xxSV3GSl168Z8ZkmlUY7PvWZ Ysy3JMf2r7v99DICWMdMqqLcyYhTOIGlBknGrmQU3hRADK8q8gxhdz+q3BS7rx+vspc8R/EaQnUc yzGW8oUauWjdqAYn3cY6R1oMHIEbQS9ZNNnh/02KCvo4UWXHJ54NUKt5AxnHJ7Tj8mUZkAYWHkGk P9elurTzb3+4nHrCAwtpzsCIH4nZbiMqpKrxfQraw2rbo5qiqRvJ4pLNLz3zyVSJJsLInQY1z1o4 c3b+uTTlmEfDOJvCqamEuQ746TagRv50/SHsmG0vgvf5Fu6cDabs/rSSf89oJnYkp8PtjZpm6qk3 mnUZONtq0dC9n5e/4qxs1oyLWyY0VDiq9G6LQJwhWnbwwSN2jEgdm3utuEyO0zacCoeG9OFtVR77 qxIhzmimUcYv8AZg02fM/yFMZSNOY6bUTvjq6/B8QZ+Dkk6ppX0PGqes94KRvFs+tlJZ+W3+SFVD 25U1H4WxdNb+RWUTwAJjISP1Cjnxh+rCGUMSTyN3gNp/cmBf8g0RWyVi0y1soBd87FF/NmNInarK 4G7vbGMkeA9kXan/PHChabkj8Wr6FtOyFld2W7ollVExlm1Z9OowGxCC7/uA5422ah3sHFrc0Whi WdFNquTw+VlVPl8Bh60Tqx/Nuxyoa4Zz+rZt3CKe94R7bTGycPDSS2DgyTbbEqmm9lKAK3oIwpr8 Aj4buEiP2C0VTKEM/7lrUBEZdi3EdNA/wFwl4r/q0ucpD/P2OaFZ5Sf6gtTMJB8j/tNtlnfUevU+ 8DM8AX+ACwU54g7Zs8M1/DiE0qbgosOHlj8m2nPUTKl+m3Oxlg6pDbJAYNrCTkgeMp4HXsm3ezNE lwV+unXgHHkntHzgBPSXkSot6yGw8+JAU1hrnnqSUDtJGFYzeYgI52BvLVAwcmq5F9uJ6OmpQHYQ 2oHi23W7aTNmXIRaSj8FQ3mqsegsXCNH5cSriVOx7x1+EskrfIDRwBtWD2h6w4R5kMdTfraLj8cZ PrEmT/Z6mh9T0e6VSFzSHxe6ugmN3qSfykAIdupmlweAv9ucqwb24sdZuW+sZz6iBye9anCAUVq5 /hpewY8iy4BfzhNhPL5vNLhalIvvlvwnqLVKnpbcMXtrV3Q7cz0heUlwsBzhF8dUd475tboiusvp t9dZ9dSo7RK+fCp/ZFrcjxa2T/e4k12JfUO6k297vlBjibbRN/l0X4JSuqjNO8hgI97LZwVLlfmm SZ0AWEAwqhVsb+qL470RqfBstZwmoRkrY1LGTh85WFdTxt9wKiunG9CuIfF/I2cgAwsU9NnTXryu ZjE7gxl1QmCG1ov9SqxeQNh/DpUwSd9eUoNu0pz9UL5Ubd3Zo3G2SVrIw2a/KSLYUyQynNRRuugK 19wFDm5XNz33NKueYlJe17j8vu8/iJ2eKU3QDNV0cn90a0gQ+eKVf3/IPDehlxUe5jgojdgqNC/2 mjRj+MEq6k+Ypfv+065jHwfRNFOdULGeDCQWxgiCdgHDMDMkf2p8wzDtt6D3zPAhALXtsC/BqRx1 kqak8oPd1I476cOkYpYUyLxupcx7gWpujBqhsoFoLNdXC9i4D4oSAD5ErMb/JfTLWxpUcIuo9eaw IpnHDI2wMlXGoautKT6UPFpQW3CZFjTiOAnVsXHmQITd+HRQ77MTkIxx+m69oVo/P60g7FgHjb7b twqgU6IX7hrd/eBPQoyOn23SMQ8Jai/T4pzMe853rXGrcSgC69z9bA4yj1QsQfPDBvlHdlcBZpCC q/Xi2EezpQabdKyarZMidLa6SmKbZXlOYauvjyMkJSd4eUrcqS7rQe7H8Qgy150ogf4kqk1CLqBB iib09PuY9G7u+sxCJ1UVlji2DnIceBtEIByEBystd6xUEbUYXuzVAM0axz9Ra9usOVVgiXhznD/T +rc6E11z/Li6ciUbcqvQVAYFMKQ7gvSrAQ81rYRiHyqxhrzBaMmRgUmM38TSs/emIa3Edg+HEKSD r2aCNylgbRynxHclRNiEXxU/3z16tWcukYcJScoz7SuffTdQZnwEw3MHOZfz2+1D4Rt1cszvgYW2 jDt9iaPBniA7y0h9v1+AjQC8mT4aPxI4XMmHsOQeM8ky2WBwzBUgTonTslnBDlkJ0+9lJRfFsRKu j7A/o2HlgNCvBZ9KiFIS6eTIJopeXmKqS8VBN0k/U4XgAVCXhVdsVpaMEd/xYGoBuW/6VWzq6TMO qoxDtrNqUmUv2fubvJ4HOnYtq2hLPIzAeenil7VGi8umSPvvkytUOeGCtr+SL9/GATN5SDJQaTV3 7wSCZki68UAjwQsIrmivmMXvH1X5X/MgVWs2Owec/L+56gEcCyKC8up8PbZAs2UOX10IlaV6rDoa YXGhbRkM08Rp7m9Eb0uHXlVa6A1efAvudMzv1NM9NOwvtKxjHqcmu+YylbiY68XXLc8T1VeCmslv mTsve6eVlC29kNK63eBMNderRSxkTHO22OFG540zfiRCNMPBpU52IhraQolU8/NlgOb0ZGorvu7B YeYbwR7/yE0z1JzjNbut5z3QCh/VU6pxJT4+H9a7VVqz5QqzrAOMj1advUCtxKLg8XDKTL4bgr96 rSKgufaxVrUa96ND9gLagI3YelkiklAU2C751cM1s3Q6sthKmsoaPtv+oiUrJFOGBKO9iAWoP2/+ ibuP7nkw0VsRaKLEv5RVRS/1p1wKSHeZ/5ZLlNvwKVkre8gKv5zlCxGBOcyAIw7SJfeyuuSxSIo7 OTI0PJwLuZkU0mZWIOxHulZ459HtVB39TUOGbpPhToFqgqGthTxBq6yn0KcVdJyk5fX3pSE84AAL UYCVl0QsGyH2W/1ooG4KuEak3BYJ/KPVqzwakiI7TSNDeE+nyQy+35zFbvRgyroKsKRuh0ulTaL6 XHyPZ7nE51JldNqquD1M4BWsbWHqWAdFqvq4z3NoPrZBpXbcbjLPCPkPu1HsSSsDuLs/tDWS0sg6 Ltv75GqaGl5HyPQ8SzV+HQv4IwjO28j5xRImzjkGi8tkptuGvVbWWp479smcKMtjADh9B/85xxwy bHozt5anK3euICWP76fVnUV06f02HF1ILTQSgnjOfsyfrpc+zlMGl+M2cZecsuPeGQVttMIomYhW z2SljhBuJXOGGVfFu0qlx2zscdlFxLoGRHc0GRR6jh02C2VJR4rz8vFC570pN5O23D/UcMAu0V1Z rXghg3vFF6JlA7YWHaofb8vRH70yuztDTya1Y2tIAkshaVZxgzXnqdsZ5YH+2DJ+XDVD+0xQ4UA9 ysOSAjfUhxk4Edy+DRO9rCQaCqGebJKiz16i2cwSvkqflKB1Ke2QVlBDOFUldXY49LPN+nz+wB5l A4XQCF8P81NANakg3Obuk1+XlHBNEpqPLfJZaFy0qYv0N2NQ75hiPvzxPCLN+doAFwp4qSDaKBQs VHZvFzYDg1QCymZZdR/2Xcf+Fi5tbc4/XdC9qVmYDoIypTPSlFCFOQrlW/v6m98/Yz6NUDRtkZrP ry/+qT9mg6KxIRB/oGvFQzmUe6SqOrSVV4l2jO8fz4ohS1AdssW2q/EM2e5fO7/yK8sr23CNoELb N/sqcfl+hKbmpS1DLC1u/u54aY/8zn5y0a1Y0tIyfpXKWGgHBL/6cvXwbI3chq2IFYm5aYz17FDj QjP9uA7aGxU6cQlqEEZjcsctbBzP8Nhpcqe6yHHo6E3eZES3M24feHNM9QMDVDNHpCBar3ZUFJjL Hfszj6Bc1GbIwA6o6HZh5V3egiK3690Vfml6SaySkj9ZXZ+9Ja028ToCO5nWiPds7u+nb7fDrQXD WMHPMVCm1LKm8t/GE4hgO+/vJ3Ox152WdmLa02Cwu6Nh5Y8C6feTHbKCf+TO/Thu8FTP7CANHjJX r+tyI4xxX0l6kuhBrCDCDwyHg1/asJEOGgczEuAxMtL59oejQPnRQMOKAIYcgiDG6FPEdunxTUMO LIquQCmZC5WsrnprUarjqIVI9neyCydB4cKXFiYd5JBh5cONPCBwZoUrzWEq/qGahCoBuRmRekhh g/sDt3b88VA+rup3Lzya8QGkupfXSo8tChmSPOT+dSqbtAJxiqhbf53ZlyZXPXlWWKdHVriDIe1w BHIVuuOksMPCaSGozLx2I/VhxDUFvtIe2PJd22gN+GVHGmSHuwOX82KrPy7gyirqRO1fzhvdGk10 aJJCFUDLm377+0BjhIDR8CO52tWZdbLPDrLWL+tW9FN0MTG1gcx2rxjy4hIe83s4CqIgjpsehUeC LkAqdHKU+BtqLE4nW1a3MhSi/0bpzIHm28l4KBONpZOHZ+K2Rl17mebY9XL7KecixyzO3nETY2Ae d6YxjzlzqZ28zVebO7X+Usr5rbL8NC1eEwuaUMTAgivnnPNW/TaGOxsRBos5bDijZKXZK1nFlOTH J3EuDdzo0KOPsQrJ/kS1rUOoq5/frehhdU4pwHIlS7QBDtV7NEOH+6smv41c4avLbMiolt4XJq5Q Ues2S/VvNudftfVTId+sWcpHuUm71fD6QMavPKfPK7MqxA8H/oZzjmmeu/cJbUGDT9VEsguuIsya DMSqIxGm/nRqcITkyoZvyeF9x6QFEnKnYq8L9yWv6RlizLWGUOmZyWwK2++3crNAsBW1l1Ar++MH NbhG3OtipOCymON4Yx673hNzbTieV5WwSPyJU7WF/KR9fe/axkjwMjKapPbS76N9qQFYdKfs3yAd oYOdHwQSQWlIvTrAAAQaeQyELn+Me3/q62b/z1CuvQhGs6ws43RFGvTWhDzuED0AAqIwW4LtNOQh laGuR0wpv+xNNxfCWbD6HZw1/I4poNPzEFkOd1jOixuxfNIx8CET4MeQvYVTA24Do3v7oZ+VDnXM 9SPPJg/9mqbT1D8LfwjxJXNo62Z+ctdVwfRLlwKVZIMkYHJplR6Z0MzvlneAN3XrhhFNsaXmX91E y6Ja4CdVKWGUWgXCB+Gd3tPnJD4BZSheZJ4wEVMPay+JDk7K1e3Wng4C0WCFe2wTKESSEb/rQr06 dnXohx+vEAnFcNGi1YDESVtmCLvMMk2Epl7nQ0j4px+QTknDnudeZAjFuNrVm5YRC5tWYhUBKSCW c+enbcaizCRP4X/LuBtAemTku6ZX9iFYUpZK5e5ClkfSxs/7ATNb0pJqc/qPTzK6znAgzxqSO58b YvSNJPwlWZ+upCkWyxZimwV6EhUcqiBpNEG01QtDUdM0UbP4YWVgmftf7g/1ClyKmvA7dWsckyQF LCr+4kfPhJFOWGzNxyFD5AuHk/5z3RZM0fnPPk8uunLCorfZcJZ5AEKxXqlwBnIipIJBrxxLpIp1 ULQS1MIeawVictUewgtd4nEHIAhi1IErjZ1/adC2Xavxe3qNe7YIFOfHjdUWdX2bMZ+PTGjBuf4B ARWN6pZU/UA3hN99U+Rv3UmF/bDLFz+5OVtAo39qfOwemS5HtykMlXt/YAQbrfIFoDhaDLegFHfQ nVQGbwMOA01XN5Dy3tLDwXZA3088+/2z/GHdj0SikZCISyq+cbIbiPNS4ZE1nt3QkZIL8eHpkGWJ I4Jzh642X6weVvO6ijcTXAkzqY9il4hT/Hfj47ZBNmlBhXKfeurGdD/DzxZCME+fAABAuFYgSS0i hkGWy+sWZ8DBtS9imr1TBG5xxz9QVLIMh/QTmKAmDrmW/hqV30dBufwNWr6YHLr9XrmFkCGtCs+R 5PYXU5LZewDv84/BAL3yAaXtA19Lx9y8BVZ2r4+uuV6J2niIYaPZ8nj46/He3WPyayu2VCrVIg5m GGw3E0DSqAOWDFg5tf/VYdRpVpQcrIq6winRKdZi7RKY3YFbXhK6JYsr2uURZimRTel79y0OhCRC KUjQYxdy9hAaHX08pMUqMoTYaaHVuQNpou1jQsp+q7hKwxSWncfePTDqcoAEk5h7qinAgJqnkl60 djc4v0mAgf0hhxDtokeySbBORtdl8CSLd7CRA6hp83KmSIgyvCvPDeA1Y4+PLthIoev+fT9p7MC7 pud6c//qk6kYQPTKdxiozbxy9QyrohXGTar5gjp7Ao1Qf6IbLEwPUA+pCwKy1i4F3vaCAXjzFLFb gGEUCIP5mK2HWOygQhHm/AJa6zDigUgvpK+1CiSjZoqnKGIqawCthuVLqf6i64f5SQ0LUoV3HIp0 fwvwWoBHXSsgz4Xg7xXV6XU/7usuQwqPgb2U5ca4thM5wgOHmxbT9AySXFTccZyEzquUgmpVOqIZ zkrtgKaR8+fstM+jAEi3Q3yd3JBhrWS13U62GT7CRmsTQVCgmqd6IkzW1XycCNbwM650Q28TGcH/ jjj/n9aC5OVnLtWuz35UWdKiDN/MECQmxcZ+CrYsU6uHk1wqindf4swYOMBLrbmM/ctgWFC1TORn OGgkiEvXRXV1KMVF4rjijh2x0+BvaRsI5Lwad92BVP8Id9M/pkNX7csvSDx8OSA03kaPIw1/hjrV 3De/5busR1mCoyBGIVCnMR9owlxeAoMoLtjTBdeW29Sbf65UmmNaCFTFkQyCcOHG4Sp7zvRJeZQw rAsWX6at/gfR+ZJFAGptdthCJPLiE6ojxuPtuVnoRcB5Ptd5Mlncbei6osOOhY8cDsGRa1jnH1tM +FlkTPfwBJQ8x9Cr5iIrMlX6qLfbDHSfyCd+OcNUnNMAXry97uAAIrYiYqJJXylhh062d2qeLvkL /5YsVDWozDi0WA4d7ORqBan2cItFzlYrTUVDYlZGOKuZ66lbrwbSdCntArjeO70YLaSs6JbOPazv 9bf+GQwjz+V3cGe9NO/Lzk/250np8F1knV3TMjfuqSamdC/8A3dAV6x7wx63+udbRdidl/GI4XQg +VADVKXf6XcWQRO/zebKizh1XJMEBD/rzdXMj0LPDI+oZHZz4ucY+QATdjYfr3c35qX6OktJ2Y5H lZ7RUzCgo2AQFtPhXGFpIuJm+p7bmMvA+aJufYmBoYjhC3onUn7jlmxuzlzzEaoODjVl6X2QvykM c6D2qk/9DKKXuyMQ+XMVx/OTlzZqZqAmMHHohQldgqV1EFKvlATx07oJjqDt/x/phBxVEe/ZH1DY bhEwQxZgOlfljfPXtAFxfeXqdyy1Ksm/afz69nnBuictB2JJQBm+m42bdHs/DcixvIGeuPFKhEwn mRwJitcuOXjbpM6AVqXPKPuY5ZTGHC6cpgDe0v4LosFLbXwQIGhCLZth4JIkkPw9Dnm9R9INFQeX E6ZwORG90l3lGX/+LZuI2BISGdny2Xaq3RbttWHxA7lxDrRrjQILYWgLCI6tuNo4XDnx5R47nB0C y2bta+ct7whiZ41q0jji4qWa7BmcFeq5ekfA7pEy+KtZ6OI3clemb1qTg2QDY+5gQxJVPPwNXk2Z 0twz9ZQZusHC/wJeJCnAVGt9oMyM8oGKehizYJcGcKQF6pX9vg7ovhpzpnNd6TD5HgZyKHyGwj6T 4/NVIPd1zkFgioxdVr0NLLQOJRVIwP3r4hCwu8Bk6TINcVE+sVSqafJ7cvegHemd8HxmBi24jC22 fwEMbixMaM+2J3B3qkwWnGxfJIL8KsSiUNQkj9OjHyoOq49wnsSJ6+d+7KPNRmkIfZAB0KQW7lBb 5IwO80azsnv4tIp41dK07p3ZEaRRy4eiGNjrqa6jL20JqfyFLkI8jsdl+e39nRK/hpIVmUUPNfRZ fTSTKjajJ5++avcnwd0empo7b92KJIToKrgU5wEtkfEzLwRuXMm2ce3Of8fbYmJh/AW3JuxUhlzn e2wcVX3UpSA2Nq8VNZq6UGo2YkpznVq7wpKC05AQdjLyfimj4cCAdx+rfjn8j5ECNMmEvIXhBB03 v5F7nKeRvfx0vcwivWcP0XzFlTEeMdKCPs+dP35SOx0Zs2Hz8gay7KhcFHVkHNJUblzDGb1tzqPS TQ+1T/HwRRNnW6Ja2s+Ztj/+7m8xCoyjQB3WsXowwT228CAz8ksOU54Zev7gB+yOIq63XteInEVH JJ6wow7MOj4OpesNkCmc0rqfzvQHPL3Jc+EpmOab/3EcoKdlErKoDEXPqzpUD1kg0u8/pqkRgBFz NUuK9WPAvaSQxVXG8RcZGBxS3N3BYELs0Q17aoQpbxt1WcpYuq4LIcTImJcrcVDhoCjbvUEQLCDh kISkXg+jxqq9VB0RRAkaYVKjj3YiZqfYV07SBIy24SaZg64TsI08Zd9AA7ebpRXENiOnSFdyf/6Y oSMffsoPRDe5K0XBepBm+n2xtLq3QKqHkcgepZkkw2WpR4iBv6g+TE6CQxQOEZw4sDx5YS+epFJr BMr9D5ODXEQYwWgvrx8Kye0ViWTmk8F5udMonuLxIwaxatqIzzDnSQAIKD503LnbeOdsxPTbJHbM QDdH+i1k5X1/C8kZvu1kQeASi7HcN65pcaqXSM2aiOZ4AJAVJyZclz4OKbZ93WkHyjvur+pkg4Ie ae9fMqGSmavO6pllwwO1Dl1hG5bYn1pJfpUq2Xm2q9enV/+KPgqiKwFS3AcYHpFiF1o2bAIsFuRn XDjm2q4Y/G/jZdX7XjrBDW0dWMi/2i+aMwHRLRKG4+fskruakTOIxmRCFnz59F/Fa4kZGnvqToGY 2NSz3bxq1dhyTNr9trV95FnhKiMrfUJt9ow3RE8RupDWMGn0aUqZ4gKMmnFPmIJ3/25s5XQL3iFJ bBc/GXACu2cLpt84FC3TKbXLr1M5nFu2RiBFKVW1YAZY70WF7ulqhHizCrP3MBmy4ItABaT+DOcn WjEQNQC1cPvs2TzoGR4eHrT+RioBBJS1soRuOkkV7P6f0MLNAdXJuikPvCWfB8PprZ9iUoi7rLbN Z++DNDz5k7eM+Wn8UcPnwozREGAZmjg7gATBoX5XBM50BZJ+VC+NqL0wEtdLMOFgUpwOpAX3UL8C fYokjKKE1mmlNDw+v4QyZ+cjMDB0alcEPkFVvCzRiRXxvzrhAlPec/N3+6n+Ep4yYZoIlLB9dAMh qO6VXk6hgt8y6QtzB+86Oqo/y7zW152wj8vcU309MHuYpZE774aeTycoIfkOF48Ir6zDEly6tOJ5 zq+OWlMdrp18QW5L4TgzmhyDRlrra8snAKQtYQhbTJOz+9d9EkxxVVOc0ogBK0Ou8c/pWT64SNNq 36Z1aBIZgRqxxTss+P0/dG5BqE/DfTdlh0HRkNX87BfYEKdSu4T4v2FxSnM/qA42ExCtM+QVRFuO 8l4OclxNZUz0g+HZguW9TvXqn/EVVp3X0JVbRWgQeJVmbaFeCKocnBjNtEWnDW2E/gnMsZogkDD3 Va4tEw6voFyY+07MbEqNAyx3WkSfBfU8u0XTQJOb2qZPYGjYZzEqFHPeOZ1TvtlqxWWTK2SIZ3fb vUbc2jGZkHuLOVBSUKtO/bnb+v4l9dESYFh5TC1vgwRE2zITafyJHr9njUsMeEMpuB9RJusjAEGM HYDRjpIO/SgIFZZiRf6QDQeQBmanY333by5MT3G7AlgcB4w/P6gW3YMQgZTtfnaZIEsZPTh7aqql jPrl5b1o4KiO5+UgqMeYPm7/Xf4OtMPhgh1uFtHQrEHZ23jBqETsgoFrTZWS7XT7CpsmAGIMkjS8 13WeDJGgLskkLPQr45OY+1+q1r6MsZ0x7ReZz7+FKQkQ/atbLnefJWS5az/bYYBrDhU3ya+D8Z9Y aploJskPlN5EREMoOoRu8YHHOfZUgzar712XexzDI/hmYB04BnUyohaPamqnsFYk0mVKQFi5IWpm 9G9kdcWoLxrFdzfF/utKJ3oKdSGbfYJjFOUh9oRvPFrqO2sv46p7Knq7qxx7caSm9kkpblmzCau8 1osGrRy3zBhwsZqvfTZcmMmOa33+RBYyZKDmblqdsyy0GY1HNcCicI/nTMQiHsVh4LOSRGIvkivi /WSzAppiQr+WAqts1xVLpGlF2yLMMGAt2Ap3ICfSM11wOEeAvEHvGVD9mRKRDH52QNNm178XMFMp o2oqsoi7iNOVaoVimuEI/mP/7LkCsGrgEfWOjvsZjLLrk48RR81CjFousPIPa7i8YC4jlms/6i2l UjukhvqdwK7XjBvShi3JEMu8kORRaO/7NxmrH/GRFxYGPliuDyBLN24/EDTU4VbJjyGIk3gcVawN w28kkLxyprv8Ee+yZ4iCVdvjH2SxpZZdEg8v7XrNrrYiyjWppwJwQT5Z0+DIQNRg6ufYLqceHMG3 8FtIKJSmrqQpICEYTpotfpv1D3xD21K9pVZe2WG8gEHenLGtyaASJXP4ay4AfuKpK92JaYA2ht7n oWuViA0SrDpbA7fFzqoE/DLLvS5X9T0VnFP3Tz+UksfdwJimdU7hQpPagSMxuWsyK4ulA+3z8ldg ouTfQvRrrkuDnnDuK1vv6qnzlvMqjWd0F028XWUO/cLxNtbrsFjcriaifxmVWNob6K6ckvOGujr9 wK5F1M5syvw1mVtOrqKoAFfnd2kGAgynj81pdG3Cu5/dDe8HneetZOoS+NV7lJiJNryA468kWM4S 0pdhyM2qt26k8FlIWS97hqlqtiaWcmJASo7ZO1eIK57kE4oCyoPiBxfVxURVOYY+dACjM5Yg5j1K YlqFAq6FnbfWrk3qLyqE+wmlj9GUXeO3YKohHYu5CO0qvMGT4cnaezYp+6pCYFEnLPFIinc/qwvm Sdeo7Im1PMobk5IAjvodTKVdr+34VBCCg8yna5Uo7ddPCS9pKV3smsW1fTYPH3ihiUqjN4iclKRt B0Em1Lh6R0j6MWogjxMI6gC5LzchRrA38qpp3xw+t6YD7lZ7gqf971snC3e7VOHMQkP+8vqeKQ5+ oTi2ScU6CGqy4ciFQou3547jj6E7343GXYeN6XmAnRC0paA+BDoz+yqe1uTjuwxTrZ2NxCkaox0X B86S7Ob4CvzIUKOGJru+CgZXBs7E3p4dCQycgbqdvaKalS36hPti+ZIzpf6L3GkVqHhHcQpHlNL2 0sfl3WgK0xfCdcYMLNpNAa677uTs3ygctJmk0OD17nhcD9AXp13XKlkB6DNARi/kOaZTM8q5i6s7 6L/ByiHIzNa6YUBMkw2pNrm+LNRkuOasU65Jny2UErtvXDQVdN5feJA1UvOSJC9aW69w3FSpCzJ+ R+01lJGBEvfF2gRAlSWrb4oODaijxqK3K5Ryd0q5wkkHsr7YOAz2ERlUtZrd5/RvzmGKKLPpSNhN 13GPq9khsXpbBIdi288oaLHMYtTRPD4Ah5C19syINngoDFeiWURfmFRgPL0CVD1S7DWlwtNxxEFw MnawqdJnWWNOlfRdQaQ/ZSYohjeW6uNZ4ZsSnCTrlTNfAUEfuQpy3d00seOXygleTM5SjYH0g/Bm qJ7JQhdtOhz5K2ElPDybzEbTWWsPtP0kQ/e6gGKTSQuC54o7frMKRhtYgE1e17DR9VODBRsJ/4em RKdNkANyS/HIqp/h5hVDhaq48J5tIgNnBFVLd7hrnV/+xwOlCs7/uaMkWHMs9jthtGQKaMBCfsG1 nayzdhRjjz7oDe4wJcioKdqu7/2SmhXn3HkCd0qyFOQlGsMxRy1RYCzbT5tK1JTMhim+RGJimO7i ib/Ibwkq40O4q+hr6/poCoIXIlnEFBQKsKvkrjFmDlMAc9408L08fPWImcZpqe61j8v4HOiCzQ8j ZmB+upT2XBVeY9YDxGGlEfLD3hHaU4UT+McOZZ5+u34/8JwafhLJmZtsxEwpRsI0lsKg4cUCv/NN 4QOyJc9bBEDJLvlnJwEupHsKCl1F2KYD63qnlhcVJwjV7jTzB1XGB+9jLyfFJ/hhp508Jha09+0j 3ZDyYC55P+p4bldNdpbVbrFbtsBSjgmHlWXFDyX2Jw/922iHGrz21i1BwLCE1ig9Heg6f8sVvovA t/aeznEys/NLAGQQj2KCBHYx+96b6i62SahZ3o7QrHtz/a+H80sFDtu8sc9h6LVQdKn7NGrPjPsG 19D7NfgfubucaSa1jyELUFtDdSD7NruQuMwGtfzlQlQ0n3I7QRlzsGfzA3fyZ2tvMVctzSrA9nBh WfK8Xvb0eUoUyE0Ij5i55ZVTcMNnN/eonADpxaEy6Pj1E1hgGW9R5j+qWyTVJcfxB4x4G6SLaD6K BE4hhpnsgpY7Jl2dZ6L4TR9bkwzaUR1Eii687HitZU08AseerQOb8JYwsCSpveKgiZwJkW7pn8/C 1/cSwo4tpzYPT8UG8cc/8YiZWApbu+O9aHJ/bXQq1lJ/aptytpZndov4jay1i/aCaIXZAeozpV8T BLA4VD7hFBZmuVMHxsLl14bklMltJ/RuUQ6kKcXOV/EE+MCLW3Ol6TVo5C+TDZ/dYslD32y4Lm4Y YwaPlzWltMyJXOfSrFJmwc5PYR7th/RypTmZbw8G6twUYQ5QiioDxAh6El/mhGiOWafyy5WSZ3f9 H6FwClGnOdPrgi1O+CMYxBLm4muTNHqGsifUT83KjX6aS5p3PcHIzFSULKgNMXxJrvlUnbOde5BF qqYeQWh4CzCwkEqqqeb+VZdCvZj1NiPfkmhUuF690rpeuRauSL71yzU37csaN6SJwZYzLdFKrpkS e0J40M9ruCdqmW8OMQ0TpArM3avGOTI3lkpAX+wvLyDbF4NIsUS1isN8lG0ennDuDHgTTb6dayZi 2/GSK1PhI+l7Rbd97niY+tUNhTZf3rg0J9TZeRWehxqaOFmYkKq8X0D9jhR6aOy13uYy3OWeQtN9 dde+H+C8MNVlKwVUQFqUOFb1X1nWJmjmGX7+flHYGzoGCQLQTAxkdMTeFwdSsjq0IBs7sj5h/G41 U0Zl1tv9qU4Ht+57OJCXI0i/e5xocTfPc9VRaXzyz7jo8mfyjCjTv96cnK+1gzeS7/kCQ9L/Mwin i+j5c2ku4esyjCfCbSkv1c+jm+ajeOdDdn44Uery3K4aIjQEIaG1bER7/alsw6z9kMcMeAB1oofo eBApVO1E6g9AuhCHOPlHwEG9IfZDAACUJVpU6k8Ti401l8+6qpHSGMmsF4uyVKhFLpIXOXYgl/B4 lIL5Wd+7EjEtAAkESzmM0y6lofAKxalSGsu0mIpcLeDvc3h1LPoMfi1/2pqF0SPtQkbeNyY/z/0I wopbCC68YQVq7IoEk6zbPM7f8psQ85JqfcZY/VspYJ3U9/SYROA4nQ1wd/agb1O+MkCr0Z1buE6i kS48oap5GesIRUJPjJmY+KhZ5hLnlPhp8BlsfowzSn0firdt82ug8z5INPqq6OyLGGYHYnN0H5sD bkHmCpzm7nPUd/TP0mqd4d5jBA2kMiwtMh7/qh0KqKDa7w2WGpX+MayDMXuHFQB2HlPpG2Q6c1/G MxDdSb2NmK3hlPZO5xBvpSA7Ueyycogh4Rgp5lG5tRLnrCMMqoVYSGZOqyaJKvJsgTKD7RME0/hJ KrqAZWhTH1E3cP/1phfQykINMHUUME61K4TNexv9A0IzqBQuKNRXRG05oLr4zyCYbYR7YQUAjaUj 2RK3ybNz4YvJ2viImn1tpDOrf4YnVIBRa2oxp7QHtpt0cljxYTopYcxckDgeOwUi6OyNvzRFivIL M3xZqeeM9EywSrKX244+quHJ7s7SwDJzmNzLFVOZp8JGPJls6vJ32aiwZensuwo/QwLFJp9F8TtU QOq9Ww2HCnmFVoXASgkWIT2S5YGRV7z63YjcrjRQYks3ZrL1ldFo0PEieM6CzJxivDH/s4qL2vaL e4oqNP3X8cQrnLVEyx3dmiiDD0Z9UT2dSDF9GjFgEMHccIL9bSEQluPzi1j44KswrtwOBsRoumdg 4TLv2Hd3JdWwJSUpuvA82zBTuhkXfazJ+7BWhvQTVnFFD/gpNPtLlj8pH+rOS6DRQOYbnSb9axyz RQdFe65q8YKGzVmHnXEa84fHWr9rBnSzjgMI06zRLe+74zebO06bYaXm10NGT3J6phBRNGftrwoR suOitsaboS34OaWX3I1uzdpejjufA7O9djOoQ1nYzHssHUECOQs2YB4KK2NrGW8Oh0Vsm9DaNSw+ BgqaDERRuXt2GUiSaR6m0dVaEeZb/hIAHIlHINDrl2L3A1/kXhctPurbvounwp5bzT1VUOcBWqiD EyYFYs8N6pzxVHVsOf2110pdG818rlQPAKjVfz/ZiVGhfPdbEGRplYqqsL8jms7h9rVwxGAMKysa z3gNqgzJ38dfQyBKAoML0PcdbJ7HyZd56H5uhQi5dncA9LFntWe0KiQis7RNBAgsyR4bC+Xspoay 796V15lJCa/XkiYXjgG/nO7nTL/26srVdwc4xJPb8+NDCSY/xcand0cP6EYsbbsh+i6hkSvOaQa0 E5yn8xV+Liseszwogcg9iNnkvdlCKn58rPR2ZXP0QMpUeMjmOi0FK6IzN0WxFMRMmo3USvxhWVEZ 7Xx55d+AQDYY3M53lXCjoDvlgBhEY+E+fcF4Muo4FeffAGybUlMNYkLFb66OxiQvjLn4zB6DUn0R wmhrSb2bFvfzHZo6w4E3UQEOGAC0AOd6P3ZdOK5U16y231PDiMuFX8Evd14LlT0mCGticJCA/VZE ntUidPKGh8rmx3RSO2L34rCL1cy9W5INHkB26G9X5h9BlOw7dHB4IaqjcXeF2HX41fCgR/kG7Jk8 KA4T4T2q2hRdu4pl8j5H5KD3hJs2UNbH0/EdYyYKtbatWnWD1Sj3r2Uwd2J4RaBxZOAsxs9enfLc C3KtScPwLjnN1B1neM8xwjR50YXbG/ZDx1AnZ3x6k+YN71jV4xFCIYd3NOo1EMELasKqZ0hZJp7O la3f04MdiGrba6vEtzhx2XEMZS5xOZDesw9EEwaz6X84mwD+PiGd/BSryG0M+BO+hmPAoKDVec5K TejYy/LdeFFVbNCMzQitNOY+LHROPwDRASRpIEVekpsNxQY6ZStJYgwkUpdmZYkWAg4dbQM1xIkZ 3sJmtrAl/oHqxIi1KBw175YCLWkpWW9JRl3QPL/p15+4N64APJurI/nsV3Z6qY5kI9djqOe45i/I NICcLs5FlkPkyTJRJs0SOyOGJCeX7XPCu2lMmn2cd0fGCENKlN5UkyC0TBUV5OftxDPjDfmdNEUn wAfcvbEcxkfKd2XbhRhpsX0AcZnUAozgrdU2RaGECnQ2RK4IIUdc+S+h9tajminkjaEmy4nL2Fhs 4XJ07G1bemqQ/pzmU3bcqGXaioIaOR+Wnu2LZLzxGKtkMtjIVzZMAjV4q+hWVVe8PllWR1cSIZSP H/UYrfH9k2ceHDMJYQmSE0rpw7R2zxJ9yJh1gNfim0sKQ4HLTZSe51UUW7MHMCafW3mqPDSNSD2c REjLvvVAFQzknUsBm5ayE20fu++87mUc54b55IMcxpusnTveixOyc2LHnnb+zjQX7Z+ekbpzElR9 8zgtQVbuz8pTNotNAbrkO6am+x9IvvJMwPr7UuhGgs3F/VJIinkH1XdwTX8eBDTA2nMYxtJ8u/Y6 yKBIACVBEb8BzAcdj9ZB59S7IrKl3vjZbR2VP7nkDLQP/0/pT+3Uui964vjQP5RXlpqlSkBXCGpw 6eptzSfPdhBJdLnBoq3Gd1nwop6Ab5wHRSH8Gx6d82qRHycHGB5nQYczmSVlK5LX5f6lFhSCXGqn oUpussndX+dHParjjQAY4/eLHzVEqkWfB+2m/eKK6qNsRfl1/85S/y9aBvBiA5Lhw5WHYiRuo0pv 8ES5G4cJiuMDeRzAbo5sJR+j0GioK4WqYB7KpMWJ3kfCjanB1pBDztV+HhjCe99ovjl7ZlL0yeWz 98+h4MthHcCCpUWnhqiVVAL0SmxXmkaYYeFuH5CcjgjiLDmrPJvzZKVsHLzDnxJ0YgxKsTChnQEu q9q4u/Kc71DyHE1aUo/W8zKlunDYqTQQ2EDunHI+cV9i3re2/6mIcojY5TrMLZkWQRTC05yV07o8 fcuokF50j8q4Uur62MgVBn9D1XbL4fb7UM4gp2an+ttk19H9Alie1TT9uJnmfpOECNv+pGX9DZed qBwY7tcyZG79uY2ehIGa8MSdRzDdIlUKcd5+GyquoiO8z1N+P81IQ+wM+0Avxtz72GDFgBAsnnff RRgr3t8ffUBybvlWBgr+s99jHpuL4rRmffPeQmp17UX0u8fQNtJbVImRFjB4mUf7CxPofLZ1cfr7 5fdqw0nMGRMQd23w1YLPO7pixlAztQdN5pKvXJa6OZ8b+MsBS5wNG6UQsiaoHkh4p57BnRJE3JMp guTijzcsvRH/uGzLscS1GRVx36cuBxIpZgwgwKOKtYX04Ql+cEwdCuilwC3Y4gpGkc63wXRF1oAd Y/GFh1hypG27uP8/24Bo4sm3u41yL681tcyBkEmb0ptwr9DGgWx1wdkjeIzO6phO+WL3eXDs37cP br92ocIgV9voaZuV2tV8630WqRPwuGPXg5kNdFvqFnxz3ai052YRTjz1awCgokntddJI0KSXvV0w Ow+UdetNjM4XqrR3jyQ2HikQ/UpdTm+zBF/P895vMJd6iqkk1716AuuMu+kgxSEGsIr/4p/dd339 3uQZ++c2jHtp5qwFYA/uCrl5W8nd8Fv7B8444JZvyEVULsPFZ3PjkJXN0Q/1VhwdEwLjuGJoyqzy udjHZhqihVjc7hSfmy1Q0r8KzXR3kHTg7ku5vMa53NENNRccTcWtMVf11O2+N0ZKDYo9g2jVz/DB CGXlysAZP33V+0o7KD53mW/QIqkfPiZCCPmdtdxgwoMQzerD8wp5TZtgUJ7LJKEVWM5tWVFsO7Jx q7bXMR3ckHg9A4I9qlD/kWUIkLoetbSQfooEx20XcYtIo6jGOv+QGsAPxnW7bT0xd2u1d/ubbSIk eWVA/HAA7RxG/7pu485DQD/CUI6sMlR4Nd1nqxo7FRhV518fs8FWQapzslpjCrrrGnyYlfbaFC31 EDu+N9VnlNzeZ//Zf4di1Jo5bdu/P4XHMK4KzQZxFI8g6Dk1fSqznpJHJMnhzS9hVdyWqIg2H0hW yDbd8lw8SckLl1RjcX9mqdcqz7O3dK5Tttk3hHN46haLAokhsEOzINpEhZ2s18OpqgJ3XvVYpmpt RnQtyhsFYuaRX73fc5RcSD+twFqlrB42yG6gabpre2/WfYOgUzMDkX7UlE+LnqCqMIark+1+pXmM ohcLvw7WaAWVLBiRAx6fD7FOzwRlwUgnHcF7jQz4thtF38vZgcXzOwy9wcrqMC3/5AUUjVvQpfQ5 aRCjDPrx8XBbWXjHEgl79x4Vmp/FT19SYXRewflU3+dnNgJcFIIEmyyNmiWA31OeXTJH6mfpoceY gUgS8YCj0XqeWg2p1R9n/XVTaDg4QlOfVAAX3XkfM1MZyDC0U6/bZ0lewJmle1Ktoqfn3dc3d97X jnDny/Ad2skAK+9NQrWzVj0Z/HEyIkMbcpRpwgptZp1IQGDmU6/lYuG1PZwXZ28OlTIF5pbKq+IQ 2XQgc7uloiGtL4LpgPrWf3AoXe2f9nBhQS+hQNb3ANvW8fcob8MasQ1KnPEaKDbIGT8RfeCUHF/p L4KHuJlJegddIOMViWNVMbTVuVSFDPCAAtejmM8Ei1PAftna8Og0UYFB4oQby5rF/oYKFna9sTbU jmgpQ0O7Xok9MqHvTVjLGJyfThtmk0q9MWv44QeJ4h8AK1R9k9BRtJ6BnxYI3LRxau0sRQwaFdRW 7DpeA48hskI/n9vUwWxOi7clqkmosJykghmfpxyYsc/qQRjJY4xOgn4e75dTyr5A8j6jJeizbhoY gw096J2czo4xdKydeqpF1B0Df2xfV12pRNvYvwAKor07pMjo5tSEDgWBogpVNFloy1mle7deJpkT ZDYSPYX6WiZBIkYDuCmljBZ7HDWPp8IIJFjY67idQfFLjhUyVZenYv9hypEj/pogW1qOpk7eu4A7 thpE1SC9uB8S7hzgqvrCIeq2bzAxId1Y5TwDQoPXd/n3CLWEte5ZyR5pK1LCmGm01RowmupZXyDf BTxR/is2zRLE/GPWOk1ycbk5uohYi2rUfJkmpdQEdw8wRr+rnOdAGXx5ZHtENcZbZkS3HWsbQSP1 9Pcox7zgekYy674AyySj1aFxmE0/HgleyWQlH5MeCCm7E0FL1Dc1IzmuOU0G4UW3daBoa1Fab8R+ E3oPJ7Xc2AQ1O469FHeoLqBuAwUDMojmUASWZNm0yQDsa/F+YwvyHfHQztqxTPwxUujYakdwYQJd n1zMXCxV1ywUwMyG0Xhjc91LybtYa8Oulj2Wul39EAdK0sPPTAHRQvkFHlUHDhWzLiWKcVH99U/J Mtvw3LquqvNkuQa46f8RjUneTvtHmwADC41Mz7bgbI12yFdfF4OyTMfJoYmuHMnKMyozsmDoy6V8 JjCDy5XcE/3Uw6yhobC74s3bYVORh/72sSfthfCsZOHh+dNRUi6HqhJcQPtULPXOD0QyWmuZr8F8 FTY5/hWlZE0WMTyZ/ig+jZjmZ/KeTXVdGdNkWflEyndz0aF8FwpqyTM1pfipC4Uhvs4fMpb5vZjm g+9M0zQb8pik6mYbOEtcwrSEk9ZWQFGj0hB5cGzZILGGNGS4zADfAd3cC9piL/DmSUmB9lP59oW6 MRcHaYwo6VzXJbh0vCq199KVCEqrLHXHutjhWza23soRs2MraIKuSiziChQePG1476ZUx3oygCjI S7vFPO58N84e3BraFN6s8jF31u/vGzdnZiydtBZrO2jKtdr3bj3KdCdu4uWo3rQFx2e6nxeU9jmS qT3MhUPsh70Yc3KXyWr9eWYMg/Iqh3UEhjoSJWkkNHLuHKvd8ktlXTj6/BzH4v4Ucd4nU41heWn6 XnHUYjpsWx9cKhZMPgN2cVBn7Z6xfBvCZy3aOptf2mUGHbmPJEHaSmJ1AHEEiQhmBi4ahIErJDWd AJYSguxxWHtkWXo8AjISljIfB55EuwycLdZO1tbJlmPVttVQGFE/q3TZp1tRbuu5ctwDoTDTi69c KkE4uxTXFnEfXnsyVVwxPdXqmbTi3GrqVBitAqXIyWsxe2yjf8XpyGLnaNM/UhxpkRmMzmS9DoOw a6Z79oVhNaHogBvZdVGE4iQ1EKIrSyAgtUtm++rks23NFvBpbpkLI6ZPCEzU6lswVp+7bSotxXG4 uuz3G+PwlfXCCPHuYfatQtMRGLoIRj1dXGZ91o8sj6psqaMRgZPkOrX+pwbCxLQyV7lkUhG1wZvz AkcN1VwUwNArIHsSP/VZbHVQU5fgm0PbcUZrfOdJa32cn08HTRscU2i/IUC4ddYZwlLb/jpI6cjU tGKCFBO3j876881FUgwekrM4cFQIqo84VprlHT+NKqsP1FTl+zC+bmdtqccwF+uZpdVnA+lHpUBm Mo9xGTBHFcCKthW3ArLB1JihUIy1ZXLGF63kETzOssXbqde/JchwF1Y/V9R0TdHAzuezSrQ5qCj0 KprDFdQ1hQryUB+hyf7bTFpd324ED0Olgd6Lkw/D2jdNG1AAVR92GSnqg/gbAGQ2v2af/r6OOsit poYyyvkuCP9PM03t1UuAdp4Z6BoHSpKI4lqDj1EF2D40GSIKP1Q0nFMKa/mWhxxlBSjXbYgcvP4U JENkAp95C3bGQj8trIK77MKFsq2uQcb1SoNVN9jgNfyIP8kc9tafaRumZ14npbAxCeCLkMvlkLON Lll2+2t7Nae8Ds1yPXc9trzWEwgdetobLYyNl980huoH26EORs4wk2lT/l2MXaxmY3rwdL3JLBq5 dTDDKVq/XANnBx9+BQiuuF0iBeebXCOYE9b5EtW061GERR0aNZfdVvQGh9ZKxrTkdBjszee0dkUc XPSdUplCppgCsQFCX1oDgiQ7HUZ6oE0W6C95/W7Pu5N8kLr4KwvWUNffVQNmY3ShF9cSBBGfszXZ Gluzj6MeSOTctRndVnC54El2kLLHYWl00Hq4Lely/q+jIbsJGAAbWFTlmO7js3nOFK98TiLJgpBg ZQ3FuvkGI+y8t6SF2YWzMWSZImlRkb0Luz6rccQO9lAsJaernFf/tciHE85bAu+S9BTWgXPJCBvc 04ZaSk6r5XZaAi3nCQRTBEbEquBVOUK794Ar0CaaD076PfeDD1oCCvwapt0NMeJ+zVAAP+ZP0iQ6 9J/0zkKVzAxg3MlywgW0lVDYwsDb1C6F9zgdeRtZ+DAo12x4JMxWc1v2aQg2VQA8P5gUiIMPMepw EIiVX4suDcl4nfIUZ3STtPdzypxg+5WcSg6/J3rpPgcuhKqqjd7+q7Hac9ZOp+rkPhy5BDnYPVHd 3BqVMccib/kO3EPMdEWq5SxErzYP4hY28fQdFYmfV0Sq7F5IgtcPnsd7qTamL7JwL12sl9XVsCHY o9p1QYotHB75OjZzhcFBzS1xo4s6iwmwBwUjK25A77w8kRnN4P1dcaTk9hlQ3oamV/x+TzmDM+S8 0R27nbdywnwddJSPhJApZ82tkJ2zXhO87L5icEND179oGZ7hEJha+Ty1uOLOBx+USEzPL7767J4O B9j7V2ot5iCT2z6/qYL04e+UcfFZTIdTRrdbWwF7CnwFg7IfN0X4dv5woY0gNWSw0Nmkm+KrJIF9 Idf4wlWDU2hDfO78CItpJ5LhX0TSYWriixtr5IZR+oFH9lm+6178xNeSa3hlp050r5u84mMH8HNn qvECTJD72rYR/wLS2DN7cvNS3eFjMcibGNDrxeqy/dfKRAarMsPexcCFW2IHiQiHbcEezpGQ86FB DQ8H2E8bJ8pRPXi4PBZY4xwDtiwxbv/j62p8TEzjtFFb9/qAAegY7ETVRfpibcw0LLPM9NETG+r1 dPOwwVo7aqiUMNK4rHI3ijxFAQaEDi30FBg2y5/iEXz+wxuPZKhhwbnG1ibOf5AtkvMs1LUQYxD2 gA4omUGmwLTIpsK9HXJlHYwTy8ruuJUBVbEZP+XxK9o59pcFAC49uK0kSTO4e03IP/Sb6Y3qLdoV zANyzQWquEXWk3/wVFM/mhdmrdqhc+RBI7xA+44GVPLHrDyjW1y6uU9k2bp+dI4yRJqfo5j2lZG8 gMNkbv7BIIYdhF+YVFhpaA3Zyxw6s5kkc6ZpTLN4wZV0fGjI/wY73fw4tV7F+Dk6uwXAOfmZkiw9 gD0rCw6X6hAJ8Lei4fHdRrXuT+cKw5Jy4pApXilIKtpr7vkwKWyQREehb3J2D0iovjBc1bN+fU2A tuO6KJ8HX/0xYDAzYAB5vVS40SuQ+aIOOO5KDMttpO4LjoHysJ4ibXLFIUPJPIfPTL53la1Dzxoi KNDuHOttx3Nm0MUL6HwZ1D/SEg+jRaUc3CvIFkrh+b/KDlTkZNMHFOViIMGl0tZ6zgiokY029Urp 6C+seeAaBmLwZAL+pmR88NRkkwqDqy1hOy1t666A8VugpoUkRc/DT8BEvFr+wax/KLJPZ8Uczo1j Q+EQ9dbXFfSV3+h11k6fCryweLyZnqRYafMKVX9yrJvdA+IFQG9CZVWT43ceKPZ2lEBuj34pU6l+ ZKkrCwIuwtbrdf8jLER3uYesXpFh5Awglk+AMA0trY2CVyK50MLio99jsQrzRj+S3Hy4x+I4YFtj YrXToOvKF1vRVr06pzp+J4f2UXzLmteVELGXjOF7kmLD/aK9vWSNHgOL1iysfq7t3RtnGmtliaYu DAZXL5fCLbdyuUv96OivEMrAOCmSTRCIs15zpNs6QVLgfJGlqSyyuOpkbC/wyM5FeGrZFGMRnnhF 3oDYsJRMiLQlXenGoC3dsXoeAkjAgbNpH+q1xnkuh7NgVe0UxFlqh6ZofjxfrMei1l0JDve6HLKF 3J/a2CZ6zCH8vG+DbnCLcHapwkAH6fHxt7MfMOe0jFsEhfz8ZXyF6ceiyVpd4nQEiVwJaM9107g6 02iqh/zqV3a9KmYW7L1L8P/yarCByuyj0VKt3DuhYdWfykcfLGwuB804SgGq6gJPgpUm4XsrgLQK BmT18ks3BksQYZFn3+aImz+UYmg6KOp4wJ/CMW7lE+iCynqhH+LlMYF2j2IGsabH7b8ioLJN/97Q lPZTLvNFnMO3tZSsTZV9WB59N7K9rgjLrkB3nnpNAZojRiyEI9dr5jjLO6jJNEAiGp4Vg7C9BuX5 tv/6p2m7PGnim772LBdzRgm73cxXA+8MqKr3goOOu0xCyI1D9TB0pVzVBEXOfL37WDjYjB8/y/6J X9UeM33aJrsXikDHw80HGDpGFlJoLFJEp3FFRR/Efn5lZxxrpR/J9blp+UvDgNpjWerpsljilHV9 xhPu9HDZq9kwESpgt9be6qhuQ8q7JCHMb9CkByTUAPBtC9HmtmJ4rtS+EZlGVaUzhWChCR9OSjYP k7oZpy8uqcpdIftmfwBZ43d2VoaLhftiinnxciyGYOEzZhiD2Uvos0JyOyDcVQlCG8VCyO/InZYE DqzycTwg/BqZCoi0AP7H7Xitva3RtCbe88XvRb56p0g9ZP54ketqYpThqHBxxY4mlVAJR0K8dYZs ikgK2tW27panqTYh8ix+d9lvFzhfYanuL4fnCdraj/9cKFETxYWtEwlV6EoNf26rq9XdS1ByXBEe JTH778WWxuzSBUeWocBZOtm9iR7VGXKoLrHAPLt9WK9G/h0I6osuNXR1/ctuXf5V1CSsK+EjTwcQ fN17YTuLNeI1JYL0CuZ932YrWqmKgAPUN0FK8mZRepVncM3kHKTPnKsvf0qOIt7VeZV2pWNzDYba pyOBePefDEcI0sXY2j+C+8mjb7UN4hQcZTktMhzodR+zCQXBzSSrvqRCz2haSi5Y2QiE5PnGgzf0 Au28H7A0wLh0OXQk1heS36bwuTAxe1NqFEKk0afBmZE1j1i1Ojg/nhBPOCf8xMzlvT8gtWvty5xH y0jxHoVjAeHIVW6+4OS8AWGlyeGxYgWsQeFti2ZGJz8gMTqN0QOsk2R2AZiXF420lOjqblHQcTHL kESAYfA4zsWlGC/6s5RB8LCDywSgIfsfI5yW+RDFX6UAsMWZL+A0wOh+5kVGQ9D/LlzFNf9dS2fC M4NjWl4uYzobWLCWO4qmew+7h4owrKzKClRT6/8kP1TPlXt/oA8S+4WMby5vR/qrW5Dg+ustIyzb INRUq6bo51u2qjSBvHfYKvg+dOfimhBppQ1EvTjvTISZ2C6ZJ+a44ff1VcQo/Jf8+/yOqy9B4nOC UCwEDx3Ym3Ct4OuWBqvQzldTsKjgs+tmwrM3IYXSWTVPLCVrjyB1r9iqvZCvu/0UeAWKNJEKFMJr KNZCzEyre60SnfC6fIXZGtZNVFkRjuCSJvL4qHop1xjYniHcxPBz5dPWkDNAa/6L7XDhikVnXLb7 heET+E5HYgTNsn2Mz9qnXu25oM+UFbz4hKDRy6MqRz5L4NLOCLllFNsmlzlmTLruhoADovSKbrCm +2LIyRCMT+fT0Jj+2e+3cqnEEjZ4zbW4UL3BuKep0KwsIW7i9XmmPgYJpSWs5GI2G4LfRKJ2UY0S B5uR2Y4Kye9YM0xOyTIVrwR+a7Qg11x63tdiuiK3llZbCmTIyatY6Lz1HM8W1N9nbklavetl7iH/ vduRtZ4bkCQ6jywZRhyEJBUFOpb1SCUCK0gDcnVvPUL0cAwrEpD7ZTXHI6Yix6kXg5yd+ztplVaq 28nqrc5uGJpZzccvrBYc8qOZ54bKb4wtpFXCocO4k7FFShIJs7AfSEVC7vq8koAN21ol5d52uxa8 Jh1ixW7m8GKun+cS8NL9090dRn9FIslH9gvXJ74m0tQTVC4xB8+HyyI2rOXU2nGl1FjuuLivhZk1 H50JOAxwYk0LFJEkxz5rBMSWSMBAacOGWt50cXVSf8iLf+XFXoafuJgJLYO6mixpa2fFtrbEBl/R F3uUqfsgjWP/O5tRtvSAIgpXQY99ga1SbbtfOPl+0/17GVknJW3TjstvMiLdsaUQAgqAPlMG5JMc qBv+/kdm2AoNrnqZVZX2upxEspFMBItEFkZEiC4pfXAMHQZJRYKpV/Ez3SORTzWW/QqziMBtf5kN gvFrN53jUnvXs2R3Mq15xWi3rlNmEpRSbbLYQDZRwceKZSi/LwPVl6mkup9O2P7DePHaVxi+lSlO enXdjuftsGEwCCcgS0Y/tYAphto6hq6YlZBiZ7iMOUD7OWe/9hkmqqo9nc6tV+lByDWyuxkMi8as L1S2cRVnStV7LAhl0B283y3t3Rluz5mFALtJJ0rsnmC4aCDdCiHr9fLrm8+WvoJXv6ULNlVHtszD 1VX8+w2hzwoMQJsJK3ZGJnL30A2o+DXGDt0pOqXA7akPGMgKna5JMEMkXtoE8/jPwHYxH187sRo5 5P5eKUMlR3JK23dDDR7AydQSRqmf05QezFKPgnLsx0oICvLwrheubA9GtyMvyvYO2EEupEDdtLIB RdHrT2i377Fz3mcJBgODMzX9HKHDYsYXdKTuVZM7B4EnP7CIutfIeD6zjRfY8Hm04kuWcmxA4MHV nDAYwiEWgwQdk8LyQjBxmrCUp5xvBvrFxhqjpEKMQg4LjlaQUzPn5v/Bst0AOVlRf51k/xisnHxM Oya0NDkgoLcPlkJ7MRnwcpTA2730qXvgdxXQHLgxc0DYSPFx8oIuGLwc2Q08746hYRl0S9YInFX4 FXz7SmdE06bFPuQ7bhYoDi4I0eU4SrRFcb7wu9pHqON8OC8myYPLJ2qou+76O5ExQet9Cp7p65y+ X40x5lGUDwla1J/aFivLSYabXVHBPs39CLiuPuQo84WWItK0GVwBz+KJy6OTSxEsanm96v9YwqY4 3JucfTZI28buGyHyPh6JA/PCHDZ8Kxfnof89WGmqE2kTRkixvjb9CUL6GeD5f4MCvXWjbZuzYJeM hBtlVkPH+cRDYpmGY5quj9OSAjdH3JDepxxRAWIClNXnCEWCJzCCTFa3+TEmK6gq6LyfMLCx875m akkXNyO4NQzMAy4UEme4+JyDvo9Y0Rce3AaAvp5KkE7Y/GAOWChH8O6gCef4U0pjx75c9CHwFfQp q0pUiIK1Cth+WcQWP/4mU1cZa0WzkD8NZ+hI/j5k7OBqr2G6yc7vjs3LzR7XUdIt0E6H5KDOiwTG pVMu9goT+uldtXf2VGIjeziGZpDi7VT2k/JG0cWRlRpoPntjOVSYUmKGfE2wN/Ceg3pxSiqvs/hy Zhdw510WyTQ6WcpDTzxTE17GfjpOFCtobIZ1NTh9XbbTiBuw3WBEHhj0AifHXumRPvGux4Lm/zj3 0WJqNj2fUDac0wCr+h2ar23Htz5SpJjEUYgRVaOIWY9Bf7/kROuBdn0QF8qvijPjinS0Vn4eTkOn AOhGTvesEtyYBy3K4FJL+YpjcqIhWTd6Ogo/uK0HA0daPw3x1Znp3JJM5tzazNrvVABKEkvCIebf 2VGeDV0gv7mI/rhTQLPCbfgxg/2F+Ch1Zw5H24SDAlTR0S99hVIsl19eMoop6Y/4CsIl/Km+MVPe hLbsGtQ+V5OUqUGmFFTJxMR6jeVkUIkM+/PSC2TkeUDQXZfnm6W9jCrNHHR2/gbVW3POMrbezyps QFa44NdKWaEjSKWrhgHcGATfJaQNBHtn591T8f5Ivju6RlK+K/3gyVJ3YLRFQXc73BLWWc5vXo2Z jktsRQSBRR6WgDvsXl617WhCL3nfyPQwY/+Lz8LD5UR7Ap/dclGT4zdDYIsdPnmiX5kxfO0eFAd0 ssP8w1t/ef0bqiUNqb1tavEzO10pogIbfdIaTiszorre/cBLTSWtVmWdPhGy4GX253rYPKnVTvNu IOnDMMEUZV78GexlYQ9U5jK5do3eTARnRM3l2vPL4o4NO5oiond6E5iTNkV+jdsXM2Nry1z6Hb/X 9CtpP8LMwc8Y0a/3HGDE7P8lOVqZRdKOvvLyRCshh5E2VVDUxmpUU6vBtAilKvq6Mwj0ZTv73mga 4lJZKZfHcWmWIgKqDzF/dJfziof3mYViNVVsKLy7frbCOvhol6qtllVPM4gMQMOsatcbbL1xD+4f WOzW9V3sMeLnio8fKk980CDTIAP/ETsWZh845cHTKUDBIEBxmQ7ECrloqQ/29JLNDOiuhdAADQro CyVJcAT7BF9hscPTr7QF5xBQxkp7cDAwaWVDuWyTohqnjFr6tc0u+qYcDOdw8Ixx9m81Qc/7m/4x iYR75iFcLZzjQYtMZr0r3JXgyQJ+aFfV6Ul5JxsD0Auf/feJR6vg5BgiyfhTTSEA+qN7ggwUNJ2J bxEDVkPSmYCziEogjRedAaIngj7W4lvKTFpC5FyAdYNe3NfeHY+zkeKxxcjWO2wtya0WgtkshSVb UCjf3/VJfahNsqR6dbepgHSVvAei5F02otS/LtyU9ZAIe3VJpjpvlQQxo9sMFybe9ZgsjT4nb3DQ tY+a3oo8WXvisAz5ENbqkOxfvrL45G0eW1wn62Wqs/FiIyetROzu6SMPIyGyG0iCPfLqxOvDJuRB vpX4yMdaqO/qgfERD3PlflLPg3mO3XTgtg3DEHXSjT9ErY5GFrwyju/2d8s0gC7zjqPYRMXX0i5O TiIRd6pQSP+T9JOapYl+mC0KnxZs4V4Ow/0/bcHhWoza8aKZguCuippIcOT2gBLucPQaomSvc/Tf fcA6fOlEmCKyl1AQwwdqMKm+vSGfhILISmxx1fZwMOg5xj0MQ9y0FfiKzQHeBwRvRbSogUXD4td0 ck+1Eg1g6Y5pnjMG+ICL480eDk6vwygEqXSEmwKiju4BhN5DnjWwy70l9QotyQk4GDYJ2LZ0iX4M JE9QhW3Uv+iN0hocc74dTNOhY8E8GRLlsb+GcvqoSx6qdaKZ9tsiVwppZabYXW5gpDHJieQyA3tM Zxd8Cc0Zl/0t6mvjT4h9aQe0xmR7DWpGCd7OkYZIheVbZ/gfzDLalDvPsjCV+E2r3T//tm0rMGDB PHZ/11Bq5zG4sZ2SejaB7zgbUWcoottPRJyLlvhNLtGYfwxmVJRnUr7Y8kVZ/KqK1nCHxD1h6Qx6 s+3XeOzUVdRmycBn2LMV+kYS48SLgbRny/npteNqcCMBolwTw6MSaXXvT4BKUZm9jHmTC5MApBT/ U6QSfjhzKxC1eSqCC9LT9puJHz8xnO6YT5r+uxXarJmr1I/el6TVkhp62rspw5UQ7KKVBiSt56zg DmR5NFqASy1+ZSrVp0MIGqfjG0CC6GMw38/cByXCzdbCo2353JJhIyn9SLt1vEeQwJ7g2t6KsMeb fEkbvcdFy6vemX50FC31bBGnoVUzflXuorftADin5BEGARMz4h72IDP7D157141vTTyrGsC7zNFQ LYA2roQA3WjiLOHPsEmoWuor9RoNmNi2xsRI85ugHQCApth6c4s+AWMeG8A1Jm0kdgzgZEop1Yqx TBgE+Pi5W0msUp1OV8ZAKpddG2O7H01D82ft0ag3/IfYMQuWCk0PYPa85X0MhKc+xewshsTRrjV/ 1wyXGgklB+gotVqmV8CZlrGFx/RzGOQMGJ9wQIKE6gcBFSA5DovYeBMrkkGDtSiGdFGTtYZg4RYo 1197AbB0QWWvbY24YigCfqjK7Fy4FjnghNINI6aP9BQtpFBYhEwycCCZqMWbesuFmAV/tTSB322T 2A3t6zsvU0mOBtkvIfXLOgoz1ltbl03lggAGqGuZiQjdmEzIkivZvwQvzVYY7QjSehuFrC11cJoj 9rjzXHLbDI2LBOd67+FlWaxyornIFH4V3Ef3AOvY8p0QOi3L/c1U8jhbpmmPJzfqlkWJoX62NVzP tS5Ic8tVS+dfok5cLHUHrlS2+5/hEKtbt9MKp2fvfH4YCIOaEgiG8ktHFxJkDuyybFCz1Dgr3fXR NEtIxvgsvlF1uH9LIXxPulMlJ6/N/fUqfcM5tkU4J3tWkNKjhoo+UdZO1H8quLNkSzTZWaduJq68 FAa3sidg6+KauGOS79KVRzdiwexsvDFDtotR3bne1uYQNJu22I0N3WmFy53X4f50y4RTCxb/f5Ky xiP6NApHu0FCKgi1rpJqLH4iTsfQwSao8bUUclfVb8HLJ5ZD5Uh/lEnRdcKfSZTe8ERikqE5lbPf tsNV750Lmxpd2GyNzKXaKh96aWld/qA1pnrExWxqrs6lSn7R7izBMZkFPiEAMc80yC+XicPsxVLb HMeDpVJt7d26/qmCCy5A8WfkvCyR1a/WkXxW/1f2/JEJQteKmiOZnfZ4GTKb0CjwiP1Iucnas3zI 8gvQj5oEiexnkUtfKntmIYdHrcbyZjxox+Ee3GslX7Zgd5h8/QYxoh2NAP0h8xooKPzlBwN1JdSl N0bZ30rSRwW/TblVPtdYdKDnlDTurbL97Qpx72H3cuiKBNr+4JmsvcO3VVEewEOLHp72vPEpAuYu QiKjBqvgFFSk8jONr1E1wQ4i0uRWHGluwtx0jW4Ha/EPjDOFv2VGdS559TTeLvM2/Kbu/VbWbYYJ CO6pExCPfQ61Qwj8DhNy+x+iXaQLxt4aORR7cGhh9ovZ+zwpL/QtRpy13tl7OWgHogtf0wg0nG1K e/ii98tbyzSlAwqyIg1rQJB+mxnNGTOIZh7U0fnw57PMYK6H+LWR9mpcOnnia4oHkM8UTdpHGyDP 1TQKVGaPPx8z1kp/7mneFdQemb2n7Z7j8NqNBWwEwwCcIFLnOJ34e5keCblxhe5AV9eZwhVaYDil +d7Vf/CLlBJmJ/vlXp9WpGwg1TSuBxz6hECKIhy3oePnme1s132c/gZqtLuw29fePR1JNVbHNzd+ G1gqockttXVZ14nNh1M8R9W/E/T4sWGtnuhCsLrQWI0JiCMJBW7piQ+zLKigOHvE8jVr9Ad1l5aj 05H/+MaVMoIw3eQUr7N3ee9E8kblBonwDKfzNrSH2S21MZTZci70ie+aSngVZ04tXgqt51YIB/Lt 8w0gQvIBXqRC+1xZjqtqYsxx6jMEZOQMsKNIoyM4RCJOWA6E+a/Ms4O4AWV7LnZKyji4fnOmlMc1 Edb3tEJffY89VeCw697+MW0szyjP0DBXVLB7Mxqc6ll8V2EFFfpsgxeScDTKEsbmtOr3ul+jdsi3 krLrY0XZ19u3dQ2/8UUOs4FhszBTH2Zk5ALAQHjfPR7U6D3+w7YtOLG3PcxE5nnKK/tr+uLpZgjt 7Yctm1gS2/oLTP81gRloUM5vC17iDu7lhJsiTlgTc6VxISxHnBAWcVJsw4RFtaN3kpRrXowLRXms Y98+dp/1cqo21qlQOTkwSlyv0dQPxCh5nHSU0bUGYcXTk/YrR6vg1/HN60Vhdk89SpN5UvJzm87H 5MtHnO1rJV2ZYOigWHAShpQwik4BYQNe7LN+8zD9U7xzXyPmshkcLYu3uyqLQx/+Qc3jms8wjUag AddU1Bwtc3gGPzPqVUA6J14eT06jvHpP/DHIR+o62CRiJZQoJFWp7CrYT3wniPBTn2JxwSOiVcjH 2beCZAx4aMAgcb9BEyze4YNrY580G24pUmXBWgd2lTqURyWAdsJMEThQetLXrhfC4Is9UIWRdFF1 rnhW9YlGurwGXGd5VyrOrXDbhRxQHlSXk4hpusaCKkLs4KZik9TcXNh8/456xlpdxGEHtxBrw7e9 lQggOMFbhHtA91+20szmeDz28SGnTzRdurKc9jgWbPCGoUQMFVs2o7wRTRUMfStrOQ9o0k/ACQ5Z gIUVLaJP0+cMFDODwUll77Ze9wwijqSEsOQzBDOx16kh1w0Km/2CVC+r0tNqKZk1o/1MTseXj7a6 oahXO3tKTPcgoa8kpdwLec9pyUUx6TBDyAjTcSUgLqGXcddFqkAL+d6SHs0ZCbb54eqU0liQCU/9 cDu9gPuX+ia32zOjW4C0xCkJaQi//qsV5H3gzpeNrdfUOliu0eguoFRrIdpbrj/GGqkl3myvwIyQ OyTB1BXcV3M1tVqiaERFshY0jXDIyn5HNg8GEmMmg4yLfJ/Us0/Z8h/jb3hcyhUt9lotVhN8LQst T2+P4EnNPRgfUWIAhqm0kCGm3t9FxffS3GFZo83/uMuQimBAQPjRrHyVUlne60xHNekAPf9Jnboo b59aGHMfleT23APqUDdrKvQkFqdVelahczekgBnxz6c6XchMyfDSpJLCVkzvwc25CV2Uqh0DJCy7 PKSqdW5+rMmu/mW9IP+kbraBOKkVmo7M1u9ln8gQCw7MJbECnEbYXcMdXUbIkDKqxAC2MZC9NapU byKfeeJ72Gh/bwL2HLrgIQqaNPOCUqRSh8c2BGqB/Yyn/DJz4gsYvi/2Rmm9m4ODcaYNRmtYq/IS IcNHCxAfcscZDqcnr3ZSO7+AI71bX2fWIHkjnn8bYA63dWKlyDk3/euRv9//IP5atn15qSNy7zOw 6rlEbCKdnSHC3HgNGVRFzMceLc5VbR9c0PPnk5c+7/cTLTHrwzA9YjKfO+03iCUy2aaejUNtjFz2 k6cCNrKKBPkyCPsTWUY4HCdZMMVrCrdRl1ziiYE4mmuIkmPYCHagNX8UV48RSbHiRXl+Hr2BFAiQ LEOtLN19bZVejpJYrtVMlSkvRrj0f0Ay8sUt5VyN5lhxlP6xkTTfDbMhcrg6gF86aDzpiuRcCTNt 723azBsYt6tCS9sbydwpvMi1aW7z+VYAZ3suMoP13DzNg2GNHpDxlK/qqU9+ucTltH29EONXA/tN a46YhN4pg6+RN00aGPdnDmoF05zwAKP97Gf+2laJeutd3aZcS4/mrED+iZztriDqbG+f/azpVmoX wvGnVoi0g/+d2ZzzY2utxlx7cAgGwn292X6VIZPxQeRvkidIRzzm1QPuP1Eb09UA2t2/0Mh2nLDl ps5dA4x7W2xpBI8kXguiIk5FMQPC5fhO79sl4F4+wPxG9BeLBMHHWy+2cP5cPlkAwRRLdxNLLfTh gaKDD51u2E7GACbjceT/A7d0GOc9sSCu4feuJHH7DRTmE4n4o8IOZqJlJ6Zln5JmRDcn+6FmPEWX ikNTkpYC6FqDbOJVqNikPQqn8IR1gTDmdSbyM9JWL2CKdIMFmOuY2Ai0uM3KFd2UlK0ZRiRqCv/R 2n7HXNbdFXYfzE+eGQfPARv9woAkf7PgoXwjcFzDiaI5qYJoRWmr3WW2oTk+fylhShSwP49xuXDD bQZ9DoHzxDwNYtfNvd/jtCGvAdZV+rkIbImBvJAKRED6Huqs8dgOTs5mMCS7cWphKSoj1qEd3yYJ HknruBLMRvugeOlTHuNM/z2BIB+cb3rQTppU+f8zgf3j6qLlu1XNvIcLvF/b19Bymy4N4rh1y6mO LFoYqHNhKlroO+Cq/xPyKTRopBnUlm+32EN1EbeFjTDiSz6wQ8FV1S/xRphjpBfzhnFqEYw1GOpU FWMO4nnBotSgHInwI+UPA213Bf7y/WgbpnCcVQBrpqDJuv9Ph2tpEsjfiNI3cLQJof1TW5HQPjtm p8Z5S16ea9hd4c966Obr54kn9Nu55Gi9jFDgRFv8VeGWCPF8Jkz0A6/aMu1cTZmdOYqMfqtmSFUN yw3SHUCHwJGQaFts5AA9hpOzSJumQoSwoQZ0rmDrn+6mj0Lqd8KLf5KdOuZhGfDpNahrHmZaO5uu E6ZM2ubtEgMjc143FIghXlIQ8e7TDQXGq+354PEReJB4/f/3U4BXyRatggVLu42Q7/4jc/MUufYE gNM0pGjqviUuZNJwha7zJT4OscFqOmA2420uVyyiJxLEd0ZNoZz2vtYZw6o196Yy3JHgrhFi+saq mMFPb8QN9BdaTRYxuG+1o5yzASuzZpsucRI6E5na7YgcYihPfjVTvz+8CDVXweTnMbOTh0DYfn93 cmECnd4Wd6BgVzUIhH1EedNbVua5qlLPvnayH8G9uHhjMEhhZ6VPcQEIzAjOUPdlM5EfSFd61Ezs J+38Cy5bblA6oL3pHybD4gLive5a7voZorPNc9Fi217BmkAXEy39hL8hTiV73jS57QAuoC+hALsu 5hemWjFpJQKGmwlSVnA5IduU51GIFmdf1VYuFuLWBJsp2WkX4Iw+vAP3L2MPPFbm4qibn6kWfAHn Y9JxG6r16vmzCtIpuD7+RiHm2t6Y7fp/sjEYezCEIy+QzmGCpBxy3LUe8evVYM+kgDDhonTTNDtQ oIRYjbCf6Jep65QC9SjOk4YSB+1B17ua3Wyen/SWk4dFLdveVQ2Vte6CenGE+fsnzUzAaySCCdLI JmGmCFF0C9uCXTMwkvjGIKxbQhNygRBdTZhUqXAYAdH+/t8qWG/CQkvV5MPNGSjwGCnZT2nHlbNq yLUcfu4EsqjaPY3S1JqQKHtzao2st66a9zJM28arm+/s5IGO37rXVOR0+jt8eQx+qobm/HGjYstv xcKFcH41b+JiPLNTakhabv1QtfBUHpa9nhv0dO6Qn4mPZLz7M9nfQ6oLVi7dtmfvcaCRgrC9rPAm 37RnmOne6en+sNElJnOahWUHxzxqGkLUIfOW9f/PkK0r9IKeSVQ6moMtoSAU7tHZKNqLXSU/rtoI nkLWhQXdlGjrQX0qIyNltlq2ksdehFHZVc6uABam5ggl1z7HZRysSrLen1IEM6T3uUJZebFN9foU hppWx8Ti7YOgj1eQm102D+F6F9AQyHwKq/8F4PXJVuPVT8WjHkgYDQqNTfqQiWz5mv9COcHxrcZb 7s1RiGoBI6bLTuyHZCUcDi9NEDOrun6kNhFMhO/GRKp2vI/2wtX4g7lDMgJmbeZ7ahn6e6vmToWr Lug8Z5R16Azv92XBfsSGGtuRMmncSmOWnAw8ioe7NsrrMQcA5zljVVkVD6b4nrsG/KpFa5qsMy1P DvCB25kgzVcZ/eHNEZ2LTDvaWbosN8mDZ/sFcSLrMHdiZ5U5jj9byKdskBkYUNc/CdPSWXvHzK1C vJZ4Jz0MTo2M5wDx3bxDotbpmrst4rOd6D1qOZtz+UNF97eSJBhKxDwu6p62Qqj1NV2/bAUrFajQ +42buVtPOySemfPI4bB/BuYWuu6BrW5cxCYOim75SUlmi3vYtnwYN1+ZVV4AolSIbfi3QlzfJph3 8btNrkVTrSuEX0ugSyF/ZV0INhp8KBwZgMbWuvkQlAYaDNBpD47k5t6hkEmYGDGbgic0GH9fzxu5 SzgHMXpPReGgiU0KRkU4KUeH4eu9hEF5JrXepjNQhkdNofMRvC/wp0Vo1HbhZIDNRhszpIn2VRtT HOOOaBIO1DgDsObcekUfTUoqCjjtDgSdZTLYGtgN9eABRXuwktgPnRtd+rNU4IwDihCpPErx6LwM ZTtePOhSt/Sk+aL6x9GvV8G4IgDgjEsvCuGyIfrKhHUMXpcmFuz0HsPxxUXQzWG/4FzwvtI9/d7y ZFKsSdLabHMoN4Q7LeMeXig+N7Q7iD+cJVEvXpn1Y2pK0x24NQ8uCzabBhiPywoYtX44WcJ3EvjC 8aZ/P4J+JOtPd4hpPUBO2dGscE8OqQktFmu8QVwXM8KZr8Duy4htkOkpjUACamtnUg8wphN1sHpe uqWF4aeQ15T0CFfVtSO+enrN4Xt9gePdDMjzAFTJoX2cgQryWD5J6XcLbzOPzpVosnHooYj/PAok PYvq4p3dDcWwFlAMOKO+H8bgVV0jkQNzBP1sVBi+JqAT586tZPNoc4czoFjKKkGnz0jIY5OQ0k0Y m9QMefKIkdg0GGmXzjnXyhKkSf+30nqkoWAjA/wqtT0ctFkZQdvrpeSVM2vOqPSue57WX3UizmEj s+f0hSFnZp59DjFCjxs34t1qQuz5dkPjD8lv3gCi+sywBDWGFeiZX+kCoBi/oDUwASQrVrXR3snO KH0kRyKmUXQPn98qPw4U/aakLwkP0NS5jnfOl8dTvnhh0EszlHyEOV1fRVPPXtiGlX91GNw1L1AU Ex7PnpBRClTsKml1lZ34zvJHnE6DYafp6/s9uejymexkGch1kiGiRvn6d2rKEJRoD2ABWWkgWUsl 2enWNjG4FwvGcc1Ss3qXqD+VlRrBnLG+1hjLxecCFm/xUFFIbQmmQ5X5hZvA3/IBrUdaJen6fXxV BpEobVYHCQHe7qCbUPir9zrwHyr9NPv9BrRBUYbUuowBoB4T2cp6j2o+WKex0dZzNrh86a+GUvdn MbUUVzgq/oQTmRdF4on2AEJBhNIM0Y554IMFP1Z4eHR3Rs0xUj9Xr6kRNV2jmlPtN/6WXFbw2YHk SjrfcR9JUAOCX7/UhMASFXg82USCCS8kAIu9cUNAwNzdTfx6XdjuYh7AglI2Ye81ayhoz5b87sNK Ju5rbcvHRHxRBecoUf0rbukldaRIMw0O21j5OYg6fyUHEzltD9Am8XNPeQe/sqy06VdiRHC1DAC6 YzYYknVky6c8WzwsmzVPCqJDbQqq0p5mh16umGH+4vsjc4fzSpakyO3ZyIWDWT6ELJYEPH1Jweo4 lOOOJ/6liZnAgLUM4Auv5Kg0xhTSFNESFPZ8HFGMNb7+xjT2mX7yKdOspyhJO40OjiyAQuRgm9ND T6idki/cRSiw5iV8G4SbC0UwQosu6wcnPDQlS1L5DeqX+eVnFTAaIhJGMQh3t2BGPKbMdAnWJ57l 5D99MWpluvUDrGT4y7MlHu5B3GbEnwP2X663/5sDlyZsFHOJLOj7l1mSg3aRsiIcUlUP19H4QTW1 02gbVfV2Xvv32G8HJEoYTEaCgOfwBQVZqRdMnaDMNAjYELmOtZyIilLG1HqnpSNaWarcqI5J6ryp sBdjetgvw+kj/7LX0zw0z1T8MJUeiaiXOWNyg09FzMtz1pynRvBZIDTcSNbINwB91/dsBvMGiqSA 8mk5Lgz6/TlwJ2//ELw7FgQHH8vL/M3w8HqP2mNBPYm66edNeGijimZsD+V8kUkz5OfxFrr+1i10 DzSrEPvFoiLfNPQGkkcUAU7Y4L42HqSyKrxNVGfte4yekvieWdWG/hWuudJRbj6Q/SEZVBKs4htu LnNiKPo9SolN7XYdmOj5eiCBn7rK8EGZMsvzy6ESm6rO75r2o6/e3cFTFgJXzg1QMAuLm/xst+s6 HZBQwDR+6vF5zhoXy8qcsSuBEDdh1dpzyIfTV29/FuCGokXxiC5PMZMO0upOyTfT747jT2zPu0ME YJMXQlx2Bw8n2rxGgREx+uw+jxZkuG0ehXzUggX8RSmYksX1xYShpHxdGB91VRC2zf03fXfArHb1 R4TLOQQnrJ+wEHan9+vKrIs40FN+TFAODnPuwBSeBHctW7JJ2JAz56oyvRGQmVYp9o7stzgh7FCs LvR+tiIeFkqkgnkRIIP2un9figmrwVWlLgxuoSdm3DKIYf830lN0lm/lE2m1umahHa/GnxVBPsBp Qo9K6Ff7yMeOovjJekOXNKEEV/T2gQMwqlDBVl5umUx5mp4rN367/A5hbkFXqCokQUawkp5HFD/t gViwGFEUZ0pYUL3NiepJuyY77ds2wT3QYqC+2iQtYuNbDbvJsHQ58gp1UDa7z09q+aYux/dm5ajf fnaoWHoa7IiOKHj8tzFfRjSl8CBWomY2RjMkjY8k2jCXNV79RW+yrlBf5zwGE36giUophbilUH9J WPW3XXO1/f45sIE3rF1Nm+HHweaqqng+CLPUEp55vfr3/OZ0tv3NLHZ5TtLIEZQAXmglliyqskBN 7Ibzwn9sPPeaHtr4KkDRV5FCKenx6RJasNjE1ODg/dFbHzqABhyQxEnA9H953Cfn4RYskLnP+Cs8 +V73f3TbgjB2732+TW0epRbVdVsWk+Py8tU5QK2kMcCQDfiGnjbDjRrcwNIZnL3O1uu+quZ12ntd sFk3cNHrRWmGJ8UZEFE+c0NemvuNiK/bTcrrpV9xgFqRtirVJopBM3pWONkpEY+uUp3dadPK3PLH eYMwC5eDpGLGJTB+YdNMuuHoQ5oHcvrNPFk9LhvSCHjD8YojbFzpuwxKXku27YwWnKu+rEsT8EBP 6F1nTm5cz8rsMnbzO3faqbQbD/DBq1Chj/8/ABwlsUc9MNrsmSDzdoyvrK5DxJhNyhfkigcrUb/n oJb0YCt0pY3wonl60+cg0G45NHc3G2GbkdZUQsJvnOeSesOHNhx7UzQNrBruF0gcs26FcG+VFYl+ x08eQ4yjwGJZr6jIR12V2y4F0w47/rr7Dt5DvIzrDX/6AqSVnorh1S84VxSwGmEWo9BB7GkMLIba UrOtK3cvKDq2SSKQKliNtSlkE1n+0e9vxYUo15NCYmG9/q9Nk62xB6vz68HhSWB6KjHoKrDDoI/p BTzbBC/ZB4Pbh321/uYcqiIJCzp5DAx8iSaMAEWXUeBLjvxVNSTHkya7Gt9/P5L2GXLNwcn2cqVS dk/SK0SRtuSdy3Gd5UVqn0ANdv/w3PGZKu8EbuiZCcw3XnM0/BjEMRyA70lj4HqPYL8S+FjFzn9t 0fPEQnyzi3tr2qOOrX7H2owWA0dtoe+p/yPY+wahQ9vX+CRRNq+oAAfJjag0o2OajG2ZnWuFxLiL anGQ7MQ28PHll+mjlJKURMeuRNfhhEtdaiiAikJR7sg7dkG+Bpx7U8XL5gAWmQQFLq1PMqCttqyd MAQdHq9NJkrUJvLAmfDAxij9ZfVtM0GIqG2+v0wtd1W8ny6V8HDsNH7albPkue45ZqlrVr93US26 1ike6ItXCmbm62NRKougqkdLcuHTgbGm7gZUh0+W3FEeKfU1JB8tb9RXtihaKb+dkxF79YzGwicc vOUF+BDoFFr+428xgpg0lmiOrYe5V1iBMqEdMS9c3hQCFmGCYxuplKTHSTqfrjwJu4+FDrrncCk1 N0pnErcS9MDMrqLaesDEcIxNeVDUl6FGllpcG8+LlQjnVTuzAqx4XyfoY6+PugkAwuNtQ3pkP73l UnqnjHm+M2Jwda3luamW7iXLOGXMmdCUC8Dw6eWS9pCpkgc2lmI+2LrSfAw8Lz21z5T5pt2BYc7i ZQbGK7Tw+QeNNBJv8SwveOll1taJzx0WptykXLeOluLbHk1zq+t7lACaeW4vwsIPoRUbbHBqdDeZ /72bwwl8YzS3w5Eg+ftxGO3Tq4XM+ZyRAzQP5MfKh3gQvv9211eh8gED/HIfjSGn0Cfxx0sbLudd CWhxZIjqm4W2QLT4svR6ZvBSz+3NKSD01Ki9bzv6t33Abu+wu6YZr/A/Hx1kT9H/YeSksUWrCa4G MJ3LFa2qgwwe9+azKuRgNivYY0wK9s61NAoLDUzKlND9v+UkqZVroYEtk29rn0nK6Bz1hnDRn1nW 0ht0wvNimmCadG/JtsMBpsSJHtjHADBWccixPr9lrD6+RQ24lsY3XubqzNEgR6q1ivfDb9wuiUNo mEBsTCHVXXviOkYGzxMWeFwC+M3XpN8EHmHR8x5wdJ/bQyCIpslB/2Dt1tZQqgHTUNCsJHKrlHmj p1NSw7uMD/TOVKxmfY0CwRb4rdQe5ITDHowzovfXJTvcydMhV4ss0Q+jkAmsQJ5LGxdwVqljPgqt FwjGyXN15NNgf9utiGW9CvCvxggGSV1Tby2wF7y9wWhY64B1u7UcQTn1dvSfw2TQ7Sr6xt6oVmGJ fN3+dQPBjY5FwFeY/PTl4z/IYLqFCljZ0hvkMTm2wx1NuEnO8N50v96Hb3G3ucBYK247s3/QJwj4 GeM4GPW+7amf0Wqxv4FDGuxue61ka4xGqPSfV+4iBQPzKO97DJe52qkZgvf+TjebizKznGV8XSCh 85WAM672FgPJAS6VISpj51albNramKmaT6NmG1bR6AnpuUSRiUbb8zie0Vzg608vRVA58mHpGqH5 uqOkWg0DIqZBfMp6d3SBr7G6IUFOrLspcBMroFxyDYgaEla5wcYZ2pqFMQvJ/s0inVtzE6i+qHko xErrJY0UHyVBeMLtrP4KUHDwZFXq8prNHEaANVMwN8hb9Z9A1R7kSyokpmRoUMOkAGCh3KXzpZhw +AUDagGhsITj97pyP1ouBGlFkAPPBOWeMSAlJ8lZlDgeva06H7yWs0Idx/dvYHvzE4Aes6f3cC8V q+/Y3Lj8To0apuuH78eF/XXJhmiY7sgDxfziNKn5Rqx2uq+a4G58O9H5Jb83hB4BPEf1EojeoH+k gCA+TikTMz0T3GyaCgxibk9iqHt+uWaasr8WY+Psw9+M0yx/uW8YMXJcuBhMDyjuTgn2zBs6ES4I BWsD94NI40YmkBsqhZPQgEH4MntfwKEpgKW7hmkvuvbBK1/R4/Q7nIasLHyxzKqC0srIr/Oxv5SE yNRNLr168qDqwvaBkTi9udraVY8yhVvNjI3EgSbLCWn0oD/RG0z3Lm0XmADqwoC4Eon3cfuAwFd0 5cfQiiVvctWo/jv43IxG+fuY+sPo+OEmm/mDH20AicV/RqQpGSEhuy91+C3+A1Kqg4EWNiR9cspj db17ck2TydAjGc/cGp0O1UM6pgpit+Q7QnkeEyGduXX4DLXQjhEBBr8ndHWWdsS5MsDlPvcNwaYK LJbD7ew5g25arzEoESoeUsHddwVXp70wdtqPfS9u2Ur+6kIf1kzw6GyB3DvZSX4awY5gOiYy2gYA hEcpuVn3wfbR7BOYPv8KfyCx1h4+DXbEV9AbBzs+AP6N0kiT8g5E8ZOLJktJrTXt+hKfY81T8zGB Hido+eLEpk3TDMbs3da+HtfK/uKSmX8PRnWeDob/0YOirpGTuXOG9wW/HVF9nTjGF99Ck721Kif9 VHdX1+BguNBM+DDWmcLXIElZ5ZzfXqrPSbI1C/j6vED3j9/E9NpJ3KDjHr+w5J5nPqemXMl09278 FnQrEe+9SVGt96xTZajS4xP7yc0uY0O423YARUkpGe+1TQIJgncEZ4k7a6x3arjmnsVSV57nv0Qb 3TlCGR8ewkdULZDE96FpZRxcJrW9XpEGH9+HFtWhU+3yvB9vPG43gqc/0quymIFHETQ7dF7o7Fn4 yn3AZBK+pi5Oc/G873HfpNQRuRHPR7GSz2L/aprLQyz2lfyQJPUsMJHGINzrxajurAtv3bL11JVR FzVotHau47e50bWtoCx4ewKT4TpxEOT7B2Qk6/C+XyUIM1xl+hAEMs9oMsnhNJ+TKeaVZLg7MRwM RrYcmw8JnE/giqCCJga2WGou891DH1i6csAZGHIo2ityHFK4RgoVsnvo65LjQZIvJDYu/msbAbTN V8gd9bgLxeLocDke619EKaSdv9xiCrhX1SDbJ2sRGnjnOLyiTHAvGA60aPxkK9w2eSSvS0oS9+B5 Loeoui6be8FbYdiJtqVq6r6S8qntDK0vFuGTUFc0ovPXMrc0VD/bY295tudfylTkSV97CVjemndi tBmZxwqbMgsSYjn8uYJOLEnaViy/GM1IaAC+E7XvENBUe5mq8NpejkjVV6SKlM//rI8RXm7ltcYA LhRhJpB/XDv83zOcpzFPGm7KSKJR6uyKvrWrc2W4FyRs6y8725FGp5kKFQdTjmtuoFiXo9QhtBYc pT6cH1eOiGyETCiSN+GyRE6VsDzIPJdPZv8SfTB3eVLZLtcyYBG4pIR52Z0oJbA3KDj+cHlHMnF3 iVGDqxkmihXE3zawMSx/EwtsUPnyrSU920Zp/h1GfwXzzzaW03KRX0cIRE4hW8DW1FamKDNfW89c cQ/eRiuWqiXYlaSIJ3lvIdLup0pVza8CkMLc3uQvUdo0S01ikqkKUvPaidwPIyHsvZkcM1l1v2j5 CwHzSj6DB1WK2oTakQKxksbSHwKIZS5ee1AxPweH2uMEHGK0J+8s8p46AxqAGsokEI73evKuHj3l 3iTcz7INulxLfJ2VDWV0mbkoIfou5Db+xq22L4iwkjBqP265q/VxaHSCRvIC5Bk9HkQ4+mT9Saha qfzSBy8Whm9SqZ/fwim1+k4YUt/YoCBi3bGdgC1BpZPRRUHNfsxQbTki8woUvNfSUOXHtcQFefw3 w6NO6s6dEurCqhMnED3kAVICXlYlPqehTayGgbxbj21QVjJATqi+OyTQCApX7aS4m9ZdWnhowENg WtftWeBqvj8zLsNcLUeFiqlFJolpekrK25ZYZvuABYAiXjAXhlc/aVJV2G2+s18aTDoYHZLM4Nny o228dHcN2/4cWoscd523vvNpq2/bGr+2Abao9Lh46s2fxiSX+/Rex2hublvUx1pPI4b3kYyc3R+G PgRWLh/NiauWGt8+FSGoBWRs4sPkLcygRPv0JDIBHYO0NbvHCvRlWrnrApjnjHUiOc+aDADcuYpf ijBD5h5Gig0VU7qLeOn9YSPk+RTBw0mDmGWwmX8/l3uhMnAScn0oWcCSOT6BQVhQRL6IQEuuRVR2 HOG3rKckD6DgqX9yO6bIzeMeib/LS9yIDh/LJm1E30CZsxIQ3EKF5hMQ/+zvltd9VnCY5gRSKskl sCa8CdKe6dqpIFWIIXfzN5merCduEEXYSZIS01H22kCoXeoqNo+8cTkH8aJk8vAHVE5+jjDm3mEc GsQ5nW2ZYnDuREhsHcz3sfbL7GdSJh7/zfv1lI8spXpdebDCHx4VuHm2OK41DV2bv3ovry96M2ZS XBHuKwTFwhUQ0ZJBB8/NgC8Y/PjA/yRhgUpBDeiUc+cMUT0FJF8d6dpeTLd3+vhLw/3Cb3+r0sxU sNKBF3+hRI//D6ueIHGqfftwEBNWzm5dreraygpVBvJZzzvqvfCRJBmA3e643RslrVLX1+3R4DsF 59QhUezMc8a1N9iic6lIkQ8U27vmU0rEdftb0urdWkKdPv8xJ5xWyLBcEA3PTRFu9lM9u0I4ZIBC re0fvHR1rye8UOl5RU5VmZ91vYEs5GgnlMoUJP2OG3IE+h6y71CO5CGxGjAO6Rtk/EqW55oCIzos dac2CgfiU/E7LrYBWn2lwqE9UYhaquncE+rYwNLJoF1r1IVhlU2nvJAC/uv72NQHhxgUUPkShUVT SBz3kte0lJ2wJKgdHqaf9KiuUUl91uH1HCjVbFrQwB1P7NmiDtQU3a3Umws20Wv09csyrLh0cvwa e0eMOICpJugHdBirkos0x8xghHV7xouVBQDB4islChQGY6ee1yhM9ccDaspPUTQuLRcDGGFKgmo4 zIRhvFngFdorlYWL/TzOGTam3X1YczU5hkq4SpFQEKmCmJ+2DnvggZd12/NQDZQuSVl8QExtIPvw ettfUzIHkv6x2YaQrWuz0au7pGrM5RdMqacqDnlPbYTAeP9zELuMyte52TISgO8NdnXYUk3LlFB+ RqHsRT8nbYRRmGTttRdFylL+p7U4IFV/5uT7QfjJpzvJVqJ0tHKytvnb90/HyN7LX0w2/sy9gE93 A0z6hoBSAYDafYH001/bNnSSTuAUK2DZO1iHY8gL1GJGCUF3yRoCkwicp0+R6VAKhNEb2UdVyB4r RWndUYJnFVnoCdWdTO05W1/mN1KheyBtw3wh8mfnaser8Bv+Xsn3gGVHbRTWxLZhS7+ZRb2sqS2H CCSwY+xZVY/CChWOwWN9eMOKdqAjC/UKM4dO4uZBlwnRjjoMDaa6Ie2eTFS2C3mTWigFAg4V8PYH 8c2WwKp26XHA3S7mxNgzZKXpCb0yndinTiXE83o3QyA3ZPVXS6EnVKuN+ZskAlS7OfEwWqpylaef lfAYOLJJn0Vb/qOsuqmHI1MLI1x8LIYlAY3EFaQJImY4MpbdZFibkFugr87wgJEMyz5cvK9btSpI RSQCp1uD7LNMK27nrnbfeZ8T7pO7D+HY2ttR6iT+5HXL2VEEqyrB6nUFtxk3nq5cC+Aumst3e6J7 mW/GDEYoj6g3CrW2h2ahe4bjVTzzkqwHUh6kwI7xmOoiOW9WXHJbBDWriaH5+1AMYRQPjT3ad0kH n99HkztvGdSR9cI5imYYYuZoBmN1F8xz4N4Xz9O7oEQ+p371Y9QYr43e5UF1DOCgigLg90RnIWPC 62tFMaOJlts0XujTXRMPD51KshfDbO7MFK1L0Gd7zQYYas8I2rorKn3SbEyV4Qg5Xzk962XhEGSw W+MDCVwknUSY3D74VwcNaUpzVU3RsYbuJ+iXOGR2n2wcomlretsG1wyMU9K4pIRBLerfJ5PyTfHI PW4G6popMGx6skXC5pug+5llVUI7q/ywCFHvss3csuEiRZeQw5eERkZHru1BP3qBFZ3jEWnxcLVp erize7IgXYlygIZFjtm0T7HsUeasqrTxPfNE2BHgn+t2t7OVKbSFmAgrYldMWKgx1nOSoicL8gIS 5SmUPmJ9LzSg43u7C4pRPgt1H/jgYNrza/Irv6acVG/Mn8WJIo3Fimg0/QDFOtZqnrsq0lobHYHn 7+9ET0jw1J2TE5DJhthBcw1+3hu6wHwsWoeGL7uLbHai9pm8b86em6UXgPheCXUPNoUcyll9pu3P ewShgrBy7BAo4bCrkQqVt+j8ukUwqsFUu5vjX9xhSa8KNzIhsiz7BFs/v2WknFloVxFX7FFMeXZm C6bOy7i0KVt6BmIY00QYQ5tnW72fkGXWBDWq14YDRjrgL9EJVrefCCEqSHRbycm1eD0qAOQrGIQq 1l7PdiTj4tCuftTLF47fpX4SKg3u72/7iDHA6nVQKQzMgwBqieVeBbMFwC+oErh/lbqniJ4FbmH0 BEiylqd6VhmB+9KR72V420eyaRR4MkxpbjPhkKmOyczgTOWBvbXX4MMNNrYz96IwkachccgQZD2q hbcseiSK4ARlzg7cwiqjPrk7jz85WA3dDqd4gb9jhJxDAVc2IlETCbuxFtLRSSxOK9HCh2EXJOoy nzyNJBY8PkImT65XaRSNqtDk/p5aDjkw8s6Upbz7BVWf/l5mzQdRegB4aLMY8un+7+REkJuAxNG4 GXAEpvFJhVA0Hr2C8b4f3kFWeCuQ7La08PBSbcAaiHVBYWOF5P/rOfXPEgHQ82DNifRBL5vFk3IN pzPm2lMXylzS3su1sV3YsPkVBB70MQXOskw7pNTsQKKBlkECZZ6cbJaEX7YbLUiufiTydxVQ14Dt Bqy7OQzSLyVxHeGFU4bMeW+DhdYm2sfJeKxWBYHu+fE0SJ8JwDH77oir/8KJ2sIzeCoMoIbFp6Iz zBGAGBL2IUfwsXT9cgUzSvuUQLhouvRW8SEOqTyTV8+0GDQkI7mHaDgdE67N62H5nhET8FO4gLWH +vhm0cXitJn9HfzVrsD22+rlZYN/cu7yPumSxeVB3ucr/cpW25JHgQDD7PD1iLppHJT9ph8YtUT1 sCVq+NbZ8ceN1fRo3nwvO3kJoCuNpzO4iqoW3605kUVYkRRPp589g6hgTGN/rbPjm5HV/m0LrMss vOsGmPMCc7ug0WW8kifJOsn/svr6NkYu1exDXcOWQfZkhgtFPiEqUjz2KwhWe6bZZvWUYSHQwZzl +Xt6f0yM8keKVLX2t1f9P02rL0CIgLJtzkdnskJ6Yk6wQccRX3gLSweYw77R0+nmu42y92YQ4/y/ CHC74ceOQL8Jy65hX5vuGbVDrNZnIWUHQylDlX55XPU41+5iaysrgbsMld2CZFch3/JgXwzNvhTk XPlwdFd8suNDciaM2IOpmMYeLsUb2NjPkFRj3fhqxehVIok2T3zMntwGDHrSzMkW/zY/ybgbgdrr ZNkqsoYpifAZqdv0a27busO2Epo94LOitULjY8HIsu+tc/dj6anaOI43GdISr5i2JK98+z0eLbad IaucpldJ1QXWPiuwl3hIGKd5+oy1xTgpOinqbYqZ34YUirTKLY1mwveX8EQnW/ZfUGSRWW376Tjf Y97WpI60t8rlXE0ckwtktzP8RE9MWnrPf4Ixz5Ov8xlMEL9LUoDU5n/MoiQuRYJHLzn972s/S3fu 1dHeb8Q3dLxn5yWovnx4psE2l5vxqWeAByMDKJiBF+2IDCkarkajfR4ioukPM5zPEj71bzkn6Sg1 WIMSHhCnZSV3fCFY73rz1PBpVIFhWqOAc/ht9GWYNtP0PyY98+ScEke2XWkCt9GcCyXUaltLaac7 1jrLPmVl6s5ydOY1XF99+T4Kyh7+GvZdn3el3ARflKNzX/YWxFedSuQeh4zZQd5JDeJOe70OgnJW vZ0b2nBZT4PTE02ppTiYerq8f2+CmnCB5lcjj/WSALJDjLzblVGPtGSfZaX4LDi19GS7A6g+R3M/ ly6vfjGeXFINUPRcZe0XdGRuOiG+4cpWGdDS8YgtM/Xsik/61Cp8H76qhToIJ8pXVFrgoGyEloU3 N9E0Q9ZQex3hwxA7T2SLPFJNugPij6YynKsqGZJp/mD6SbXH8/UTr7DlWYmxVejd1fcgvH3un2Er Ytsq6sHzDE6watRSITFwgzeNKrjH0qgHZxpXXWNvdrpxlCr1BTL/voNebZiYxOPb8Esd0xYI2cJo BkzxVVnO1A1p8zBna1+ZFEqJMCqQgngWPtMNpw2/4/hZiTtUos6Ogmk1IS3wtI6eswLN5TOh4rHn W0Afcljg/SCzqPaCVae4GPTsQ73r+AcrSUSexZq3Y1RRHaKVBU35mH/2JA/lHEyKND23LVYoBCU1 A+Mwq/KTH0ZUuzaahHH5FuqwkNhNpEoGk3o5K8k+IDpWitR8NeSi13zmK4lzTLT2GayURDv6xBnf 2g/bOVo+GvhauwpxpU1gEd+TssNBDEqrxS+jNNFUCX6q4uD87k9xb5Ct8UMo3jVZFgII0Pu8jBkg ZKzW8CMfVU1C5F7EzUzDh6FkCMUkPeMAGEz/o69FHuNahoGhL0AUF/xOF9z9iPu3UNOQ0qK8qE+u 8haJgu0knb6oBsz0OMVDtxgTYbyZ2LhAkSgLWtQvY8lSeUjqmz4IDtbx37bn8Oc9ZdImoNphBOmm VvUm/1b6Fg9YyuyWYzwUIY0yMzXsYBKysi5GDOLjKRIQrpRa/bmiANQQ8g37e6INyARa6qCBowdq vTgzT1TeKV7AXx49SGvQv83PXqP3a1GXG7lVLASqtwWVeTB9AdG2SUp1SbY0C4WonhX+WttWhl6g Ok1rdP7cI5aAX8SX/Af5kXDIT2jWWWO8cId29zYsva8oLbnnG0ftjujMDLxsW+1fHZTeWNsPFITR 1hfrTeHpqFMQzcQ3cJ3MhtMN4dx/k9MAT1jM4Wp/RBbrrq1OiCBo4HWrNpJ8uuu1tT++tvdQuinS UVnNNokm+fIeE1D9QDgJO86oYBjlbSbxyejpaKN2wd6NImAW2rhS+pb8ikH9iB356RBCGtJU1cFk ojzzxwPatrdB+QR97zVLVCgLKYavcQOJqmm2cIpAVbM9EYxe6t3hUZfNZLDZD05T+pEBwZ5wTew8 HpCDYO7SNUuiIwQddjxMzzhGPk4P8NHIiEbshTkUriilN/EyEhskOW24yYOPeY/o6gn0ijnjYJI4 CrGJIS76MiBfp7W+M431ZJIKYK5b0HpGj4MrJF25UFuAuc65vxv804Kxv0aRaQFsM/g3P4DXnpxd WcckqxIeAVu/foOQYbgXf8j24eBpvLGsso0elgLAhS56ccHKkKbDlPnGS6qA3R9B9WIqkxtghKU5 Z44K5jA7DjZLENF/qdc4jmzBqHZbUvc12VWqFusU0Z/3WWQxjmEaYcC0sjvWlrsPGErMSRFFTujr cf1iV0hAM3rkVlnobC4bU3Iw+tcu7MN2H6mmO27rFItkDYiYIr3bIsBTEmc2CS3Qgvsj8TtUgS4l aVhkWwCL4Cq+z11oQY0y1hIIKqXDmuz5BtGEqXHCb/Q2b7tQr7PNBkVxQDFaYRw0ngOlmXHdVzCu r7bBOo0O0p9PkOIhpBeCCrtLPqJctgYe3S4D8WNxPs+/aPrAPSMYhnwD/KB4lH4rd3biER31emm9 kxQtSQ/LhxDvR3Ba/CCZKyLcA1baTowRAXsMqt0WmegZoeRKFeSTyuk5VUwvYhhVzEEGdAzzDMqr Ifag03Amfx92jJ1SqV4FCKz6KijKu38y5yMcxs6/ULSHpUxs6pYRXBDNrKDofpVqduzGBxt7RFsM Tw7FT3MjZPlpCDntm+x4HyJB9LR2ToFJbbMHnclWpG8dFG5rfR3WuDYGaRb7yMCQejHDjaZeWu9J seeM8mw+stFVbUl0C1SCXPZnuJLh7TFUkWdEQpyuj6GCLL/xcSUfEXatdQ6/4Xj/Twbts0lMKeXK dvZO9e5oKDhrhkw3Oqas4tOyS9VrVK0/qSH2wpTPAcdGtzLPLiR68Rvvn1F2T7BnKS7gHYWN5BtG py9PJcm9K04z0kkovS5kbrBb1o6CaeEhzrKQA9HB9TCNlJnhj2vjQ3pRy05KHFumSu2UiPq63iIZ wChGO3eGnPUnnT6Cm8w+IFSJIjKABVXFxlHocHYcT76dNOHGVbknrV+bn/uM6opERVnFzfio5776 gk6RDl5F9YCzb3L5db2y7x+6jHiKK+YxTRLBm/RKjz9RYDhq1R6VONwkhUxZAnCkFTIMppXkoAnI TUxiqBRYz//MDQQbbE/j2rzlYUPNG/y9nFDM4Pkk3qVtpk160522jvgOrDk79IOS1LXCBg1bZtn3 Dvos1JmDYSFhve0qz3WTec2uSkItSY3nnhEHfpOrzqKtZhfNw2nGKrUSHsWEEGYl9LygIi4ZA+fz 8fgs17oJBrS1cN6MGucbOI0APDPiDTWjY6eGbj44jWWbpF8EJWv2A50XkyN3hBMX2egCn+ZC2mfc hem2Lx/+pEi6eMZJx4fuSLa8mmTrqhkGBlWq4WGbco7thLSBeLLf9VV5/lk5P/Uc29y1FnIViQyE 64YXQVOaHpFBkYou5UNrPXtAfRgRfXm4JLcNzYonvFD1XNVtKvjpI7MQecimhw7A6wER33IFR3i1 wf5J3S5IHLN2TvTwKh2TUEghSobZLYlzquQNWah+dPFXSdY5t/8KubqvpWEStAbP1bh6E9JDIm3e QzNkZtfnzYFcJK5GXceYQwVOmKkvxglM54wNEp/xBow28dxCnRD357OS15NMw4snutREC/OkvX4D 7R8COIKPKXc7JU47GrlE3Ex48UwJ+fS0QafX/kueaTeqrGN3YeIkvcgi/w8JIadUwaZCy4X76a5u Fej3SYnXSVjbjqsZIr2ZREZzLR8wT+ETEo6qc55luqjQM/HO/X7bbEBLNmb0iUX+hodcNuvdjgfw qMiX5/XSQKtZNOnNpSztPQz/3gprqfLQN6NVIP9cIgzAbpitjyi2WRVLr+VJobG0SBQTLpBlvZS/ CJ+lJbRDHakKxP39VdSNwvh1YtkEvyBPNsWJtP1RQmy23CLX01WFc5znuXDvJbCwWwiwUJANk90c E4DeiDz8hECTdXeoypQ4+mH2f+FVnFYwHR2O9QFj4Kr4TnbTCregQSUsq1lG7oRLrRfd5iz8RLjD Syai+n0ePzHEwwMXRz1yFNuq+kgdhov5Ty0r9WsQarX7KtriVFRngLunuAv1e1RAcWSlMXoJj8Dw RTJ/LVCZ8kqoYdwI6XljMpSA9c9GOqtI37t0i4D9pt9DSzibz6IYdC3mQTDpPCS1NiQO7bYz8gTl HU4e1IODZn2DswTmifBrqO395fKqstjzjjw/1GUqQDc2Vr6WRUkbmU1bXXXxI8CoLpfbTYVzQGy7 nAN8IlC16sTapIPE8f7dZXxZnpDgR0Ef871pyffFiyVIEi9EnmBWCH5/oEC5YHL/hViebwhJVqJG l1RyAqjAOlz0zGv5ww7rO2ar6VCnKETYHpVBgF2w/doOgBPZhZZah41CNbyDsguwgs/JIEplF0Re Ciy9zU8q7kxULbHYT1+VykKR+H9UoP5Yw3wmFtGifOk3uyXtAq0flT/cKEJ6oSVq8kWaspbxX2RF imaXp3kJJcOrWQ9b/RX/zMq6eN+QwJluTTqQP2Eu61/o+8lyc3AxAHwSwW8YYDrP4jakiUWpzeQ4 EbK/Vz1iaOp0t9p8tlN4dd5+bhhCLGrmhcl9vQbx+oRUlm9FCZIAPCRtYObC5Gj8E5tLGC+zuoWa W9jNdYiTDVv6pRdcmijx1yD8fuxHGBsoDguIQ5SVR3OLaqOg3YI6vPpJ6zXNjEpN+NRMWOe2zKZd M7rwd9mC2mOUUkEoOlw3y8VUUhYhHkHwa9uCx7b0MWzVE7/9sdJlKDvWr9/Xlso93P3RKuUfZG+0 tnsLifdmjgpZlz2RQO4x2aeX8+oac947hAYaFFBFWhGT4qGkr/wy+ixtc9SQAT3Gl30lonbXA7yW k87gXdNAx2NTYou2NR87MFzPWVpFVdG5OuwsSHOievVj7l3fcIpHkvbcmv9dup3bdHch4nbuvohE xQi7/b/NkKIUuFw4iS/boVmvykr2lSZSw3ODowB5IDkHoed/AhdDb2PnXhn+NzuiciNTmc9cj5FK XU4t7c0DD6pNZTP57n+q2LnTOuemWdJg6tJy0OPxAsXaFd29mkkaTzrlNBkNhKPW1UTLt/J14uzF peRmdQFPB9UETEuDAhQDFuJ48VzEcoLMmCx5VlYxLivrkENu9Usa1gfx3WYHDA67H2DkRos84mGt xsoqk21xm8WvfEkjgvJ0fLT80QXSFa/zJMDv3h7lbMlZIXb+oEAc5cAE63wCBRDTDMyA0WbcFz64 QTQ61THD1Cg3SMVNc+PgQzslcumo46oMHvhH+mtU8eOEimtRHZa6K8fAOmpU+jV1m2SAqnLpKx8F aKK3iPeQ2FHSYiodubinij7qtqPsMsg+r3IiDSgwL2kdewi5EfMSzviVl9tZGGwjVEIhLVJaaTFT jzfUkbjxKzpicra/i6jlo1sfSEnDnWVh0H9Ny/rgZlZtK1vXfXzLTQNSpH1FWIYyzDHbAlbGSMLh qmJG/cPoEIHHRTw0IBH0PyjCmXTjxSemQBO9q9h/o2iqqEeBu9a7vDBj+RzbaZ74VHqpW1jDKOlt JpWSGu6hkbGuL2J2C03F8d8GJi4sLQjIInWfjxmlIxxDm8O0VeWIVhW0v6xmOBjw+Pr9uIDiCWR/ 1IWMWJdbu9mtssvON0nD50KLj/anXaWAENpM+k6YVJXOCW5tm1tSDs5GCVH2czRV7dW33HhVaMVh LCSi3/BalKvlmQe+HyV1qsX4U1KnOoe6FAW/WhS3XT421yiGXJwUaI5uNYH8fSrw+1Nb+vYm5Dtd BhopprGibLTqmyThR67DOpUhG/za54bFMvL2rtHrv8MmiEx0LwDcKDzgV1rWwMtOtbJUWZLIP1N+ fkFLVBBbBawLc6NzELYVbwvD454REUTfacld0tY/BgeWUlzN3AV9r5KbbmPzE4SvgFUhz20rwIwr YqQ1FFKOhq46gdZFRl9qt4C/vhLvlL95bwfyday9FnPqSH7EDFdEPE24TiIxr3U/jPlF1JVR4s5c DszAiW9nrqIpEvZQ3dFCIL6QKoDhi2tP7Bzls9p1jgNw/LoLifV2+/cFmOeOJzjoHNsLHuXpG/uR Zke88IRzpoYHb/KwcUvUXd2XhMoBlsbbjWvdFeW9TzdZy4e6VitUGoylV2w0BCjxbHSH/6lqZcp7 dvXhegS2ILEYj885cWrD22b6XYowLRNIFxJantCzR3IXB1M5QgmNAnVkLqKiRI2m6TfO+4NNBN7y n8B3FemSrK4E8rm8cLDVJagwBLJRgBwZ9RcKZ8NCooIrmm+rJ0RX+54pFQJwKrr4aRQ4ej8hYE8o oOYZB36tQfunIsAS4vFeq8TzCu8AEG8VyvVxuzSOft+CVST6j9suulo1bPqkU4WH4NKyt34L/4up m46LRI9ICjff2HaiAirDJB4EPd0MygR3tdF/p81LFaaHKclPLwqF2B1JGEchnBDDf0sGFYMJ2ap+ h82trZne+XPWrV9JW7yT0JH0ueGlIys18jyVrQUbKfB9pENKmFD3t0OJshATBoBnDUNgpaXSrSWK g9zImmPnPZpfCJWGbatwQLbA0Yxm1yJGyq2LVfjU5HDY1uM5wdU9pglUc6x/mo/T+ZuIDMkc4YtK 9NYyo6R9CI3/CZoHLpOjNUloWe20Z9IT2z8zJZBc0aJxhX+SIjt+6X8Jjr7XxAiqXLD2e6GBazjR /0ffFLeLEpR8ghnrdhMWpI16dmcCaKkDKNCohWFbfMIoj9FGPbdJmD4z2GEUnWRw2kne+9fHWha3 H6+JmuAZ98nt7eTGcUvYg0V3ErEK4cpe95AcEfi4Ps+vnEYq4yWN0mFzC4d4wbnYORDSaeA5t7ud UNBjn+60SP0XQIllRhI2j1ELvXv/ILVYUb+EAOrZH3eTBqAr8IxUtBrc+IITVFzrFaV/0DG9yN4K ioMXt93r7WuSLAM2ckCaVX5JXgfhgSpL7Um9T1TyGRAMk8CouB8QuLbGjRTTE6okWVtVTKwN7sZV tJA+RoosjeRZ7ci1U9dMk+2CDx3YPY19Itqk1hrjGLqoxjmt3yMm6S0r5bGkQax7jGYFksustKtn nRV8xMk2wjXNhvntw3jR2sO33KJ92mBFQT6I+hG2SqxaecpK1xdH6LjDeBZoniJJR+E8Pf24OjWa moDLFQBeMC2efbC3ANuWmuakGE/G/mWibRV9WgN/OoO2n5xHMkBuxLpaRhJaNvmFZGdSrGLXwkin TgUBQJZ4p33zGqfHmhnE6cwyTynR4PtmOATPg76YjQ9du7jwyp3APGUVh770akXKFpobhA6uPWHl 7nRyKIm96aX70nER+CZHVRpR3MK+rM+IczK63nGhURJJqT5WI9whaSER7GywtesUV/uzyWZo9LLe Hc3nFIrZBBJQG4rtqy1IZeL5AX45HaFOmZkThOuBf8XD0m+7xFDU/djYv0jtGWA4LsgpP/R/23Ko FB0ZY+LberVBLcmBf7kf3vc81UCV1K1kKo1U1faSYP6CIzsHjzT0Dh1vUE+EXZsxyZqYMXMpCq+2 oE2vNT6bj6ZpZuznqc5v+d8UDKtalSSVIRIV0SNKxeLLH0x8uT+4CRQEmanA6/U8vmjce5957htv CAYgT1AS7KwPtY1epAIfK8+s7lM9EmPB7zBuD44MsRfc44p3kA1U6Pt2N6VlQKQnghjHiYA3LqRZ x8zTlEOENqhlJRPgu7sRavLBdGZJYheHcyOFsl0rEaeffJzj5KU+Ekpjqglq/WG8Sp9TcOicywWb K+tEpE4c4zTt+50fqM9N+m4e0kkmuPMxdOYkXc/A8WRCw2dd8qGC9GIVDkO/32HnRb0LplQyeIaI BQEpbZ+fpAS8o3s1nmL2yyvj1wncHxbVWBCo873p06XvDbk9vD9C36sHM+MpPPoC1FayyvUEP1So 2GQS14wLOHv9vAE2KtBjKm3qP7vPR31zZJT6ubXKtr0XmMEH4hkISghApiCvLWv5HED10VqXjbYP J58D3peSr2iU6uDlyz0MQu20pDXL01zoXsl+pxR+D6ly49FIpT1NRlxeF+YUptL2nWFObE26fwz6 wbmm8crRV6ZD96gvGJfUMqXr3tAwkYqlfUEwZBwyPP6sL7ewxE3a5DLelUhMeRYnJ/uEQ5hgPs8I JSt2dyDaXBWkEVdXj276FyOQCOw/MmexXwBgxdQ64YPzH+5OP8GOJeE+lFvZ+MDJywtXmVSR089A hJ6nvxGHZn0sFd4eTq+RCOaBA/B/xUKuCESGUv02CHT3G8FzB4jZctFWNVGOHLlRhIQo3k7uwLoN 404yedjMC0F3lZeLH7Tf0DiL/bjoHZNJjP5r3UyhQQdSbv4j23GKEyrHKpSM3ILuv824YTsMIhAE 2OndMpEDFVnyAaTTdUYcmRNhEDREcR/qij6mztxKfhQjai0u7eHQppfEv7t1IAvqSKYPc2cK0Efb ctuGQDIIEmh7zfHCyBDgceHyc3UI8nB1EhL75xcZy2ot1E4HfM/+RO+hJj8qnue7gB6UjhR7c6Ps w/2EFPZH8L8QAx/CevSv7hAI3Kv2r/av46OkcWELz7oz65ie6I3NSOCrQUoTiPSuWgOwLcJ5VsuR iwGT1S/4CN9LeJrTF4YjM42g190Dk6fElShM2tU5tLns52Eqes+7grn3M6WtlSotBfZuNyFfsnaM GFY/+1dfiL8bxpaBTkZa8zKVTGB770Of2HR5q9S9VR7n4ZDoBsFomew4qW+CnNYyC1Ka/sG+sLPj /cGL869uNcJc7QjV5pJYkwwU2ParVVDeWRAwYxlUYY0Ax3bKl+7I6DAPSzM2ZPmSz74JIQ2enw70 gv9uavYcB1tc6sWd0WKegWTfTZ5GmZXlR2Td9FVdyMhYwn7qg6CpztOkjyoJUcGxaYXvB7CoNqMC rylsHgGMTlgb/oAPpr30B/FJJS7eNX3M3hrrQfPxjw+DSP/MzpVc035TBXNY66/B+MlrRDUaBb0C 0D9Ar8ZqpmHtFx2mRNQusdyyGKPyMFUgbArikhB8cTZ1hVACJEzRC1xI1rldtgz4VK8HqZ5AdW51 VS9QIJ2HTRby7QZ5eCf4SBRqjGteC5XXRS9vioLKAbmqZyMifstB3GIxjJ+ILYDaKipSR9AtpHnV 7rWHqUkDw6DTCJnOWktespy2ZiAA8xzh53V1W3H6X4NQtMKtoJzaylI2kn0TWriO4RtdIs2W5qEd xVXL5mo3yd+n5a1cqwsNZumkOYjyIBG6qbuYRzu61KwHwWd78F1eBMr1Z15wJUiY1dhx0HgvH1x8 kOyIQeNUkFBmzsST/+Vu9+cMGigtaoshPUP5xXgr57naAONWN0EfQ3yjjJCoc81YGL/f7VL+cZ3W Cr3S9lcx7k1KYI+XfDSmYiepm5L8JjnOu08/3VjiktkLA9l47NREg48BksyXBRb/ZxkoQ27QYkc+ jlBq4dNW+oqdHgWyPnw9aFI+gU39Fxlbr83wmtaLWgnquYtALIYwAxoX9jf1Yz0hrbXB9alJNhfs drdQjlN8ombMJBeOLuc6bO03yVOAuoIcee1YwjPr8IvwIrhkohOJ74MzT2eStbAI/PRRcY5mTLxI P1Coc709SsfFkninwaM+Xl98UbOWT41bZ2/v8dG540fVj8Zy4uKeY2b0Qx9xMo+Yea0iK0vye2Iw 7bjfIICJh16Vt+vBbmaGdusjoIx9y4VUxaAP79yRR4b2brfximPFL6LrNF8Rwqs6IthAIL2uVS0Z +sI+pZi/Y4ifsgdVj4RNZPkauqE8jrLJokND/cei7sf4gMD504uDqVu21oat4xGSatZMjECdUCxE 9brRCfJMrvfYIuGEuTuu0Wlk1W6dYo9p4aa94nXCthcxr5GJp2F8taMSc+mCELPoIKy2GdA91oxl z7rVGVmlSSbFqX9PMAMNmmuQALAIJrnLHpPYVbVpZiuht0ZZcExevj/gC/v0TOrS56lfIgggzfBt WCUiwxedmmhdKS5Ct3jwNWDCZxaWv6Zs4LI7ewod/PMLy/F/mVIWw/YZoVANilghrGXbh7gfcBF8 B7C1Xq6pDevv8zSzQytiGubBxelcghqINFMZXDvn9Lx9Hmk3AL5aP1PKxAVeVUX/aQxulgJvTLih b4G2x29NxGXAonwdCDp4g/3gxUwDJmWGct35oveW27Q6wECxuIGAKK61iJoU9m4uZXUnUlcANi7y wU/wbaJd12Mmi2l5tZ1inuJAiecxNgYG34CNd37D4cCddMWE8c+JzsOYmWDFqJXI4q1zZKhD0bVP VgHlUeHq/k2WCK4CjkdxEq+S90YENJhGRXHOFP5V7FyNaovyrb4iuWO8XXq1zsi8gIt/T7VyY4VE OBCuwWpLY8k5WuNB7xVFwdvhQqFVNjHaF2nLYy72Txjo7gx1WGMeqmDJHQ5VJZqhgB7fEt/bn8dp zYSH+iOIdujO4kgMqy5uI6vmbT6Et4CM59HvQK2J6J0QZQ8yoN+7U9wvAF37fh3BrRh81wq74jc5 SrHUt3tG2HTT8ieVqxbPCXB5alwuJYvyA09kZ40G06Thcylc0clyPN9Yte0I5TQQC0xwPQqV0PxS ZYnO81UMPY7VgCdPKoQ7rcZDbGuBTgB7l24BlpX/6nGfVlSibS5Z4hK0ca/t7Dp0XXMttN8zp+hl i6mbdrKJgcNDy0923GvkRxV6wzTenHhTuNfrHqFqqZS3JHEA35+zruI2t9CQj2Fk1z8Yl3l6rnXB U+Y42fm7Wxq9ZMaaCeMADUyiUFfJ/D5UY6aDtcwVJmpnP5ppS9VLv0drg9I/hP09aeWuIcRN9wdI imIqghiOPzm3mvJDMA5uJIivlrv/6ACh7lzr13K1NQeo6+9Hf4DDb/5xQ0LsxQuc95iFriHEVPDc cFuOEhiOQ9EXQsTM09CwhidXdyluTwfP1AXuRTVk/d+OEdmz6O7Vfw7cxDs3iz86nQe3xIFf7fkl 4MqKU74S2asjvTDPnyMbMC9sL42pf7myY1LlWPNHWQvBKwlOiuRPuI0UUQy0pnwHotopHlB6VJk1 DnahF1Wt9jZ8T8Rh/uq4kvC61DSxolJdLnFbBywtslxok5Dp49xeOfoj32X1sL6na7gzv9HWgtkn oHwPti/pe3q3UPTNryKLO1v9b3alALpub+pi2iqOywhrOk51tYqSyLjEj72jyhaocx5rIrkGIbmU GtsGPpY/Jmjs9AdYt81JOtPQNTEJYs1UcinXWHg7tersZnJGFpqT13J1tyb8MU2XRQ8TIdxtrvG9 Zd71zjkZOfnfWwUfwb41elUvymTcn9+S67eGRjHhE4jTtQzqbeZB0bRMhb3WwCzkAsqihBRktMxv ruCxIQE0EpMm9R2nKeV/xLAS1hdrwWAEuB3vzGy4stNhhezZWa+C5y1CaCTk0aP2F3xBtV/O/nA/ 0FznVuGI/3GT4pkPVhMtothIDbCIEmZTpJoyK5huK6YuZ1X9/kVQm6KuVFk1kErwiU7sIkH0JJW7 37AgDhKEGhyc1e7gtB7mErOEBnQh9k/16o/Q6N5ZQdJY7h6KOzA8HvfWrMyY/+Txd1w7To1cqEfU yZ+uHNsaTOiBFQpwaZQwtLBf5dyYXZT5LqMaYos0pO6xvAtVk2UM5ROouzOwnK4yr2izKN8L8jUi ID3F3IUCwpR+tjxmAAkeL8OEQDKQj2XFFw38ehSqGWNhOMEYNsNtsUAiAhEBQ79NKie1qERYqXQu 1bbxFk/zAUoU7qsSNDvhKK0mWlqPi2I4EF+bbwQXlFYy9zi8b6OOC2K6zmv2N4Vxt2p21RjGPEGi 3eUiR788krYCqrAIjWhtTbKVXmeYmI58UaAVwoIzHXpXHkPpxNw41IJ+0Tz2W33YUBH8BlGrhM/M JWysJwoDpS2cO3cImg65eWfHo6z7Ew+hy+ZJKAc15eA8ijICEEqOeTc8nodxNZH1yxqazXs7Fpg4 HTAowTwsZBJ8Q52QYqzL9WL/89d9idgNFxVF7tfKSgdh74oZpP412CsHrKrbteNnIxSi1+PxHADs jqesUU4Qz7SlLvAuw+xyev5/m2Tnpod8fEOw24MwkHrQHYd8Xy1YIP77QVfLlB2q7ypMeEhR2jc7 CuD1Gq6656/WYVVXv6vl9maoJFhw4EkHlZhxzCJwIreZBwJ1YEnFORhXkP8n9x73aOCNVDEuaNf7 Rg8mXJM99ZUAyCSDe1Yf3OWAQzDxe+6npUfo/+4Tl5NVJCXLJH6XeqfOuGuCtUuwwXk4CtZp6fv9 lRgZhXuQkD52k9ulVOIm5dhVLIYXigycyu28fVgaY9hHav4TaWG5MxNLKE4McPIGk7L8L771HedA ZObLGBKXl4jSZz4QgdVp2kgqhuCUvJziU3HS5/QPIynvMVGcGDEPumOyjuUzXZt50gbpIqjX+Gr2 zXrigF9xRsLZT1hEmz2ITTRoJwl5tkqFMxJZyWbfaOFUS6XkRNtOYiKrwp+NZi8Te0nbEuqvJ7Te IYVcxPF+6SbBZaH9u6TWG8+9W29T3JBrLKD6umqaIvZH+CYZIHt5rR5BDh8G38IR/2pC0S1HUrrx 3NOyEhAL/cZWHqYoCgk9oTAf8XAczr7hXRWDrrQ0wGBh8cJQCitzoxzeihIWSLkliMqnK6j/nQdM d9aM1Tc5kc51JW7zRZ1ETGrc9jMCcSWPgFxo1e86ZVPfLU6c88dJecefHsERi2RWWnTIJbQLVEtF L1kwWxn2RqeTvDnm4XXDDP9rf3xfJVqvVuUFbCFufGWFJ3pycryGDQ0WoUfxSk7jakuhirS77Awg /ka140K2ZNFVTnMHhNheEpojJ0lMWJg2TJwpeiqmKhjXaX4YzqV1P1ax0uG6O1HDPA3tntpVqT1H qpz5y+yIAfnuxgVt1hoBw5KmHBR3K1lzsAQY/K1quCt5SAbe8CHU6DQCMncL8vhnTMWA+koHIPMn Kkbx0Yj9pQVo4Sjc+e0/Kn82KGUrw+A8NLAMjakGYIKguZdG7nLAxTt6HgO+YyKu8lo0tTB8qGqz jPHFZpn+6ma/+97VkjWd+QgwnEZuDXl7ercXXufMsnQkuwtU/mniZRYPVpuN6qenUCg5069lPqJI xc++D987JrLr1JezRMWH5kTsG2wU0heDM//EF/9z8f0mrHMRGyMa9tXci6g4xP5mHsjLKonEG74A FKdGgP/SwShlmxixLC4yrSkMK+zw2zWWn+wu9mS1vVv9JOq0KGH/c8dqjfr6++VHxwz9CXoYxXmE oUYBPmlBsc6FBLIW9byuDo/hQm6+Iywa47WrNH+SkXHRuEPBNKVtsGB4VH+PhFYsitl2UfwtBp95 3v383d4xg1bXW1p8X67cVCHzFYwSZH9+4rRBsaXPoLXGKJFyn5cxv1PqBtZ1pCuU5sleWCrg4F4G w7Im0RV7C0Py8MFpTC/y8U20zCDGf3jl3rIF+EOFetxI5EUMpdyyUaK9vq6ylzs5FvN1d618EDjA jve9ZNGna2WYR6T3A99zMZFqZUDX9fIMY9aS81k63q2PLT5mvpwpSFNNDFLMBxeYqTQhtesHmNfv 0sNkdftk4XG9qcWSTFUzcQWUvcz55GijLS7yyqTfda27vlk6O62+DLMFWs2kSyqiWeealLwY18Ts 98gvEzSv842EZGZuT1bjQVQ0TJgcC44jsEQLtWDR/XMkYu5ZyZuTc0pCxm7t32irAXIJFuXtofWV Ver0qGBWIDj+WdZRZQLeBMYYfAMIHrTnCPZ5EqvvcdC8pBJUFCtcU4T5LhQh/cSLTjmvMcsI1zXR PGFSH1OG00gr3aiLwzVKSj518vw8xiFEntfTsr6SwZvZZXkWE3phAwbxCw3mqVsdR5iEPRYbua3e eZ8BESFb/p+KEFBRqiAaivBnv7Op8a1R09AWakJLGC9XqARsIJ71ZNbaa+tqSYCx24Ok1mytYaQg gdL6rwGRmImFQQ9QiEzQ5RlEoM/ogBQtlYIPjdPiy5+J3c19V0Ny+iAZnuVEzWXrj4Cb8t6xoFma 3cZ9GWiOKw1TyDuSHWojeIGvhH8AJVwWKfyt7hmNy2waVFYJ62ENMsqwce7apSuUCmZVsr7PZu/9 4Vcl+AawI/cXOL9q9l8WAeD9SXhw6Reqsvd44+wtF366ZgIXPO1kaOgzQEK9sePfEY9nVtHTdzmo asbbaVgVCI5aXjUbeP2y6Y5KEaXcKkcZFk4V2m1HA+6bw098Rs1uNkqen4G7uzb6GwrGIgA6jZp+ GUzvG29Gp+gbIs5UGlx9CKjH1Q79VX0qaSS1aRIbgyiAR8vK7B2uFihzfh3HpRp4FadmwqIfxzpE wnRC3ycOb5yZgw47YfeZtydUMVzkGwtcLBmn8n09AlfTmeTGyYa5WltYfV34RlC8tBucN4Vfe1P0 zmcf87g4oEqvVnOdRCJubJOoEBwa/KAmy6nZLwuFfKfOM0OVlsrfGU2llP8ORn2mcjLt2vDUJlio MN7zB2ApXIohfsJHjvOkeOqyAp+dBg0+jy8EaMdF89EIylBw2YYk1g1b0ZgsKOTJ0YssbbBCgQq8 gxhewPk/eo9ReibUKfjed2GlItZTxCRLBEA+ghjSU8lUh4IZJLK+NYAVWgiUjbbi533poBL6rpws PBeMFfdXJndSiKLvndUZJZInTbos/xBB1KGBXRs3xCpuUyFgsRg0GBvfBf3dMWOUyqXwnrIhSlJY WMWaS3+QUvngZ/vuk4xHPWJD7rVWmF/S34+r8bzhfbDJmfbUQFDgMSZRn9f58mxbZwEndUhslOTl G2CqxSTGmLMaPTeQg/V0m2FTbosyP+vVtdVw0iAL44y+D8bv9AwSzlUu2V7PBu9Dh7Gw3a45ZZ24 tjmY3k2oV+ZxSkYJvu/BVFQNuX5MrkVCWo7GHx7go/8Ff2scA8qHzLugPruh0oVBGTzJNl6bQbgf mvmPQ40jUPsdW3tqPPeQjzQNrs6bHF+s2zy5vpCTg8GhJansJZQqs7nz+AdRQHrqmHoNydw9iWhs Q+c61DuDFUG/VAgOaOq1qbd6Pwj7TgSD9ymeKOZgtDJU+5eJ7EBhYDF/7IVuldFxcLLbjktXorcg iWtgqcvhoG6kc2dByGLJDT/9yzFYwy2ItocksLno+52Zjyd2aK295Csf034FFVVPhsVsk/5Tkn9I WafPKJE9+Ebj96tV4hF16QQsWkMKlJA0XiCsDt0EXY1jwWk4FQXFBJuvbis3jy7eYIyrtsv9eq0L 7fIAlOfPhTrjuJqr1zTM9TluKXBYctoseSbJva7tSHWPtFOYZXZbwyv7PGuJdQ/hr2rmbQNqjTRp C54C+eC6ccavmj56KhxKXDXacE/Ky/w/f62sFgTPQg6xNMzgzTEXVVMK+4EaEV1yqVSBIUxFt5F1 8E36pPGX5Rmy5yGpswjiVpDkZ/iyuM1Mmp9912wrBe1hKTIsOQDnbiKEGsUMCUhhUzT5fOJmou4u HkqvyhTYH3Gdo0H+jYh6w5qKjgj+ZPUCRpcUsk/6Jas64KWLHjh78H9iS434FF0dNRK2V6G2JCy6 qY9eNu03zbul3fo4Zmy9xNm/9rlaNKgQyiT+wuwz7L/CHgWJNY6rwyr+SkeQodFlSSeC++4qrNDx Luk8tNXHbKT0RtPocpRHF+7iRQWZc07NvP4lJRsuO5d8zwxV5biUoBrJ5Cb41eqBZ3XH5hlkIHv/ kp1GAjQt2CC7CdMTjYF5NWYFSwH6M9q8cnfDOFFOlAFUz2ndn7i2DmKrSwrZtRl8UL39iHbYBiZW RNYUt75qRdhv1DKqRs0/5+MFL6XFa/eRWZA6u3Ec/emlJ2RTC1AQZksrC8VcHsLs1tdZbNqo/dTr r14En5qMmMgJovGgzK3PWRmP7HGxoMddSHbuxzODH1IaAsjEKIW6nCaPpethmrfGNNF15eJVINpF dw+BiD/GYyxkMznk+OHnCgp+9LBueT4jQuEbluTvXIO7k234KMXJot3Oaoe38b6Ne4wQEA/elE8f kFZnlafZQXMbml7svZCi2JcAchertri9FkxPxChz9n50fO0rDZZy8rPw7ci0UubQxwr6hyiC18se TqaZ2CiCXE4oVhHS5S537xHqMPFQGpterKM8/bmOZ/vFXVvV9gyncIsdSxm5jrchH0DtzQMy8wOH Ttq6K72ZbnOGbXJd2O7Iq/axihNTa2t9R4QYMA0ouwMjjq9W0Ds0qoKlFng1VSX5n3sdJrLJRNe7 H75piPkgg4NxtsOa+/aACST/LOeqffPD10H3u66U/h7mvbcrOwNWReR1eKWQ6XjS2JO98p5zaab9 ZlQYNXS6iS85LGAOFqvnUpO2JUuGDWeoEiR0HIf+ufeoN4Hmd5uTreatdU/wQ44mj1eYmyBI96U/ rA0UyzRTjBeZ+v8I2Nnf+9xNeM4itoeEYijligrp+mnyYPG9jjf/dKzTJxDi4CJ0SmYTNS3Cl6jc Sr4gPPjG8mFgRiWrO8eN8ZJAaRYKVrp2W8DGppx3/jTVHN/rhmzKHvBnwoevSlNozvg77YjgIxdr GxBKQg7kCvxBOj8ha1HpcEYjc6hUr/ROn69vTR9eB2eeLon/A7iZMlQiB3myG1K0Dtx+RG1iWA0Q hHh+djHcVhLRaCtw9tMx1jaMc9j5uadCw6V8KiDAliF0NXj9dpfTMI6kujZEtfSkcki870zNyQGS ej//W+UCmxzjL3BySRkRgqvGihZGI+J3bfBeRZJEt3zKW5t+WFDTN9RaYlUjc7QjkMtszxQySaWj BBCFnqVeOtC5oRMM8HWhoRqgytBx141xiktVvQ9H8ToTVQvgXgF+1MI2fggwZpY3rsoQlwZz8R6z thF0PAjZ0t0pCse0eN40LVN8Sjd7HjiPFRiAKwqqTUSX+nKuy1YHhHwotRJz9pc9loofeQESF0M2 0XTHqDIl3Sbz8zEhNLpZiM5T8ig1T1LCycMnQOjOFaTipCq6z5UoRjSBmAql/loJUCokS6YrqTUO 8kVOerEcfuScVe72ZrnJTpLCWamDif18vCRqkPqSvua1IjgYg+fDGPH0TJMaHro6zA6KjQWXBlKm iHg7mRB4KTG9gBWaqx2JhTTZY0r/XYqfa7bYcYCE1KFWJEJ7TaGNmXOrwql7habCyJ2Gugln0F0d iiXeSDZcLJu2L1hZaZWU+rOIvgs/7gSM5blzqGo2RHs6r2pgN3InRDBsGIyFGuwoihkz8Cztq3n3 d/UDs/mMsnzhdtVj5C8dWYPsXnspScwD9RecNn25RUbXuv6KyIi0/Ayp3uYv8m/B5ssvDKd1y4js iSpdLlhFo6D8xGLPc4qA6DVTgGa0x3ig9eXvHAFXpgRmHOMLCCrGE5520NS4Nk+taKkD8Lq54FIl oRoIhb8aLqKFzWu3DXqZ5rBsDX+UWovxZRxZmesPtHcg8O2obQMNuIc8H01yDAYdLPzAK1olfnv0 MbzTG94c1ZVLio+tQTikheX6kFacb7ZTf6BzHWrx8oFp/fR7AGK4vpc4+AfGQFnZfC88W+1QmS0F wzGhZOlQ+shiyVfqrq0RY/4XWuJ0B8ySep1zwlM94WcOjFQWadGUWpkSOwQojjnrj/NWOlZ/v2cj Q+zvV2PC/OjB6UfkE5yolre6aVinbYD6K4slTYsdt/ZSLhZaJ5R/tmNFNMfRa7A2AgxRH8fqNLAu 9guqczG3n13FQCI8KTDQHwDdBkE5cjQf54ilmipOMA+3SPioBToKObWjAXFpQl92tXVpfTtT0v1l dYZmG6+QVNIqdcnw28XKYlGB5OTqV0TO63MCcj/xrA+gLzlDJOemnIQeT0MhN8aoqSRfb4ZWB+T6 ekyQoOLJ8OaDkP+qpnYcvrkHB+APZnOstTh2IkQULAF9iCFMoTqvLGjO+R1iUyHpakSBXsLzGtiR rytQJkNr54o0mBEA6PIW5TjLWw/t2iFavJFnEQwjMcMNg+oxHOVLx4bquPa55Q2qkVri29m+eNWo 0QgM0EeHB1URQlycQrdzoJRmObD6SOgHM598gtwGYTRrcoQPeeaOKeDChhk4w36N5RyePiLb/2sq ji4MQpbm709WH6K9cf4TEcvyTQwFDZKYWYvgmDXieZVR9MN7X8qq5rzaulmMY+R0GMdHEG0WOAKu b8yohzdA7XjExGqxAjsTqs+x19QQjkxZQsdK60MfS5kkF9ulL0zrJIr2oLuP/rjUvjVqr5OThHUa VH667EieI4G9oazd8odCeLgI6cPSApwzj/4/HNgb5KHHFIixKktjN2X7edjM+0HyEahJFAvxGEZA PlmbVt77RbqF9uqkrZrMeeko/LM5MlG0jvxdG8ukVghDk1UoEPsaNPSp7l52+TA7XLWy0JPWkB8k q3T2cuWde0qH1GX3NjAiT4gYHI0SgVH2p4yZmfYb+Xutalr/PXm/stA9x3z/ZfDbGcFhKU5COCu6 CwtSArnILRUvqq0VY47v1+WZWZPOnGn5hlowh8g99L1+tskq+v8r+RVs02an9nQNd3Cn1k0o0JM8 r1VTJ8idQEjE2FxBjNuT12YezS2oza/3ZhTTep3KBrrPI5WXfBmMjMRMP40o57mGph1hzhb7sorS 7VW9lGHElw/tAMp6iJ5ZCgMnXhSW37NjvmvqJVoWuQ/S764NIi7XP3jCnItNbylI9Uw2JPJ5GbQT e0ZLlM+yc8HcNtA25oeZpu6ASh0aVGr1TYRJf1raQsmqRSpc1lecTvRFf/gBxkX3sxlSFDg+09NH CwN9VSHnORCR1S2NCesi221lMS+znOJB03jYe5KH05Up9Ezs7Th3J/z5jTs7WIDNnfnugfOa5a8U vGllf8AfUAsdjz5A2h7bewVjPva2jjPy8bvvTLbSzF+oiEDMBLP2eeAmt4TrfAXfuc6Veu/9PhLE 3KR+mR632DKQO9atqNAsiZUHXDY1aJyNdep7ooQQUpWWmKg/f3oGmJLYGucNC1R71H5cRn91ItyP P8O1gKjja6vYaNx6KH6WFN2gCgvIHi0tVsL5UR4ua4utbIk3BpIzrNKQBsEInoF67ncHYCLVhH7L 2ohfKJ45jo329Lew3u/mKCMfIeIjSeXBddZ9P1yjR1j0DN4YJ1Q+OXoMj9aWISRst0dl990csdEm TCJrLeIaW098JUZctgueo+bhYbHLPk4/WXZ34tb5zKaAkNM37+uZVrJCpVpqmG0A6HGlQxzyNi7J CUUbl7BH1N/rer7e1zt3CaXzDV4VltPs4jhMx+cwL8duh6lPafqzzfgc+zGBSiiEZOdoOunkm6Pb YNPMG/VdkvyKKm5x8e6EDmKPLUGmMou+pPmT7yoFR+Swmt394ZswjnWTfSF+EcRkBIFJ1Io4G6vI wGlLyLLqYZiz/cUa0fiqkE38B4J3rMFhBm4AIyU7ee1WyPvNzJ72CTP9lc7NAWoHKnaMgNMcya6N jVU82U0H+2CktSstRh/41hpJUaYS4YalnOovMY6gy9VgsTsCRAIX/34LmbMxgfAMq2qSdXx7USnV zRHlcbmPH/1/31J6j/O3fvt0t8IA7wqd3OACi+HHGAnvdpRc8HNDx9sBc/AIgepZzX0BD5i2OTN+ tXfr47yrXvNPqjYeg/3JUZOrLV8lbFUpVbvQSLk2mUOJOKSFGHwSoIDbkv5ue8a5rrVOeLQqlp/1 +flM4515MctQ19OYdtNWtBa4pW0mGtF9R2pqyGHVss5Crcl+KF46tK9SAkvKX/o0QyXJ62spbuQS p3HJgHUEyVX+g6upVq6SAD+Nqw2o6kMvjHZjdz6OiaBPM76T/PqVFdsySthBhzYGaLRqEig1asAz M4C/dVLW7ko5E091x6Rt/5dtX1hgUp+c6Kzi7y1Dvtk9e2+tC11Acr+OSNR0omdcFF5h7nzwC9qp t8Tnxzxy9tuX/JJJBn1HOpN+ASJOOxltdwYBHIEbJQ5MARqbT2nctEHurnOVGI8shVw8e8RkLn0M vacAq2LCWADnmZY4cz2+HPmvc6mkkOpkyyKDdcwpdDkCzdfk2InD8no+1VgFZZlZjPZm+D39paIj jhKn8dIEQblhaIsUdJFmpAWRNzL6T/NHU5X5t7VHRo0Xy0Z9/582Z0jKOAgBr0WxirW3YUmJbPy6 nLWocPn6ZC+6qmGbJ1FKX2h3xvjS6wPmr997Q17RTHdktbsV/r9vb8LzWqS2oqaF1Y+dfvCnbStt eUbypFotq32vqRbEiXYorgSDT1gT2L3HgUyJc3xEek+O/SVyY+VJK1BcxNbGhMHuWIq411kQV0UA DpA4vSpNFO8DbDvhkjMbgX/tuZnwVOd5I5a5+kjnygkA/pwBCnKzOu2/+wsWw0iF3yMHZ3yVy+XC 5IyvmVk6ff68eIFEEvf7M5UC4WQbXDFq7ME/MGUSmPoDCkdsYmjFGo0nldDfob61dMXHgm922y6R SWuxvRImz2N0ahEtwWtqqBqYI7C4SBejHRUC7HkIiJHyOtfr/noi9aV0yu/Z8zc9/zTk9MpYAfQv 7gvqGPbmrV0VEegLQvrhagppvWEO3qeL6jUIeFRKW26TEpI5Xp9irg++NxMxuVzOK9i+J2ZuhRK+ XvQftURbjU4ZrIdcHJ7/TDU7uj6xqjbSCV6Ysn1a9fRfn7y517hwP6ocryOXdP+o8OtJWvgZLmrs b0Cv+qwWVqPIN3+IAGvxpZ1VlbiP4uwUVOXOv9pt/kJr5DURkssimLeu1aHzWTRsTZzCVj6M9c+y 5ktTKj9XB8z5fEeK2b9Yv2K/91MGAG39ymTpOIA836gbh0rNdcYanIYnf7E+Hy7sbRvsD6lZMtaF vzT2GTBvM+anqloXRABak6M/xwiS6B/Oq5R161J2EtBBWGOsufaULhoyyNWIZTQbg2LXv1r/hGTL u5c8A41LO/WTsXuEdCOxrKgvmdHo8yl4JhkjTkUgRfdaA0VGfwvP3uuKGPW2zePCivWOBbrCuXhb hPolh/IHpU9j/65YoVLZLfQ2raIFAdxeYuI/iCOhOxhpgsGEvP8xdPOtlQykgiNqhWbMcETQ8TCQ SnJOhlGJ+OVhjJdKjKg2E1TJtOMbRKWfUcse7x/tXdsfkw30nTZPGeH2lVflc87DX+xMqKH8RXVF rMn8IH3ZiIII6Sq6SnRIH8nUebuKqW4BOsIuY9ZZTF1zLQowIqAHGa/AELlZVjQfsQOSG5ZDOOZs n2+mVwtQ0UAFsKks0xivbIpTMDTdIVXCl55cAjYVVYwx3MKm5ozOqxKkD/X+mvqwMyJ8inQiQFww BdUBqY1/ooMiTB3uT1l3cVKfybxR3fVoHKbmsNDU8WlPrW/T2lqLro9C8szg44mV1E202rhIYLLA kJ6Y22qM64aoLj1ICmlq4KiDZYSaACC3s/iABt4Rz7+J0wfL0J3riBuE86zJXJ8xl9jRcKEJljF4 9Bxt90Jk6yNCFV1C6zPDHr6ADt2YpQBh/pGmtr04/tzXjr+IPrt8HnpE7I+xaya4PPZBt4MQ3NBt aHDt40Og07Z2NObKvVrZ7R3J0sbssA6SSB3PgSluKf673tX2gs5IDfkqF9NHU0p/TO0Ydaeo2eEA iJbt1oLYU/PyMMouomhSerjrPoHZP2TU5bsET9s31ZN2Uq38SlERy7woREpI9K5BDZC0iKpaOXXV K/Tyx50mblyWt+aqM0CJGs+Z7e1l2Vkay03OaoguYQ4Nv9amkgu7cNro5mFGY0z9Na8fMwZoWclZ R6bIeo9umB6v9ddMQ6G0Sk5W2CKcbzw07YPCQdkN26I0hbwGdtbrjuZi5cCrvsXQ+Qv9ljfmDxsz NEIdeRa4FGH2bsEYTl/HclQhZxi2dzVB8omxAv6CTBSor3gc7WotVgCP7lz7I/YSWCCEPn3/p6tR 5bwA3WZDG5AEvDw/0FF3zEax2EzNLUCSqTkp5BIH4Jd9CM7dVUEpD7F5Hdxev/+k3dHvCK67ZUJx 8ukaN2QPxY/P7s7JSqNV4xa195+4ELYhMcDvyqgHp4H6A+MpP3YRQ8N8/NhJh2JdPnLE8Oh9rv9b /ghCDOstM0wvMTXUCpaMj6LcWz3g2DFA+bFs/WHnjGtkte3+4qWwzOc473B2oo8gj9j2DiiVB3RL UTrM/kBGYW3SVGaVn4CfBkHDiTj9vTMDrh1Muu3UZ5XXFt5oL7++a+9bVrqk6lkItvvBr7vHbhDk AADayid9EvUM7/DeXQ4jPD6O+CwNuMkJYs95Jg1VU4JrR3ej857g8jCTo+CeWWaNLI/2YfRvQycz 9ZjZO1AnPoU/TlTnlrz3UdK6Z+UOotPe8zaA1WZYT1OW4WjcbmaWXudI5ADbZqNCQLgdbvYNWHsY xPeTdOi116KvUvPIYPqhtn9X74SwbjlKJyAbooy6hikYiEcj6Mizt2vClkJBcI6WKPQ9UVyCUdCf eRCT1YVLq6ziWqxlSoWSzaWTLY7ZWbGSf9Sl1ms1BpG6XXnySQBtcFvfbynsCS0nZOsnNqsknd1a twaGLbIevQDwQ+6idKNW16FbQ/XOX4NIFusMBUN3HdE5GrCQJIYqE7F9dAwfITo8fKCIfOIE76YC IVbCrutjEGeERxbPJdgQrs5yKWKyOKs7mOPwatAT9LuvKe0qag9oMlhzZe3gp/RsddSq2zBJwwOk /iGCRe0yC7IG7ZWLt1/7MsfCL5TWzaLZdwRyw6jpMIZ/5zhSfRxTPYvktgkq2T7LjLwuFtQr+oLh CwWw+bBJCett+aSSfZiH/ERGuAKzCCKLIkaoUbMYv89LSv8Yj69Vxn6kQRfd8EGTOujnhRJ+/JKS IlxaSAjudmO/ywXy+jEQQ4PMP///Vyrgol8MOE3TARsTfM7/Mn7OkVbfpOQYhFZjdhGIVs9jhbsr fzW/jnFua9ghq49QsqLnXx8seCXa2+Z6hDK2l8pgpFkkvHp5mV/EdBAFgnZ6rdHamCfXt7GJBZTA zJbBlwLAyDe7jtZqOvilEGsmiCtnJc3pQLQaaI3XNFP9AK+5rqE9t7kJysP2d87tAITF+qMJ6wDi 3Yxp7j/C6PE4ZWEQpvZknb49adQGrYYoEqA1b6fs7osoykrCWB/KjjHXQGf6p9kXq7JMFjJ/doyG sXG9ltB4+YPHQabvehSAWrSzv16kvQyS0pGVwqA63lhaSt9weABi4L0LbtY3Br5yquaD5nh0qjT9 5ufxvAPcEktmHtNUUjTJkKeeRtCF7kYj/2pwiyVTpQm+rSVm4D2RewmBZYxUvPH5EuGu3ltqwbfU bwkh/gMdweLwq0UXjxew2r9NIHZPfTGgR/+LLkcBQg86QR7GCAzMbPLyQz4co/wuiOCQgdftetrs DW8pw0DoRsofsleLzbjdzHkTplI+QSSjNjboT51MkTHIy2qDwQi5tawTcbSyOuj+hlJ+KiGkBM3+ 4110eEL9wS18YfvAFx9DKUGfZWiWzV/XoLtNLIW/OGmOhg0Ldw7mX5Ge9kOcVAwJdzBmXE51MCIT knZYKUauJNMoU0ZhnRuvB+Kr2WuExjy415bSMAFIah8sqajGyMjk/3BXORo4a218vKk/kUfRiADw IjO9cj3eCVveaZzLc+njvprPPOLcB5O7Pf0Vgh3Q5H/1v8AIE8u+BF9dJ1Whr+TLuFa5cFHMov86 vZhXQAtC1FmyH8BLopaD747cHd80FcrWR2hwTvrcpIHjdQtIFfuGacPneJfLDadHEksHNm4IAIkS Paky6EWhYu77U/sgSvPYjIes6TSaxy6foQi6/7W8oAu+bPZ02e5eoNv+GrUZepOKDeCpkwnjukyX dDYmv0amiEe6YLWYnEOr+h0rQzJV0wMfLbXz8q/6RSoHO9Cu4Se6pAQkIg5IstOJDCCPKQI2Aflz M7okeCe5E0FoDA/rfGjuzCuukxp2PrDewp5TbOj7fuLltxGDdEwtUgFlUELUQz78nyUDsNqzWp5C AmscB4nUYosxQtEqEnmLFXjP++ac1AxY1nJg3moUsBFEz3c9olgWv95Hv8s0i0iKCM78nNm60G2R fFB6umACFz4zbrU6LupJYI5GBEeGPvEHNpr590zwLvyKvqUJJLWsRu8sz81ZUJb3T7iQ6HO9W1gK g/py5mR9JUmV5zhTgfdBTji7WTzHW197LABGPbJsJsG2bvTxvhOkQlv0A+yZxgOni3Si8XkuLar6 4YBpDkEjShfLUfINzYpLjnj2BGBwakMcaflqn9IxqgXqgMs06mBW56tVctOWbjxwgTFUcKRF7qZ2 ew1Dd6hKJFAaCs8j/opFemXLOQHOBOe5jpOTiYiBDQU1+iwAjfHcTz3I7Av+g5h0SWBVH+c4ad3B oIHWQzmiIVWQUfy42/fgBKQkbNbejuX/ic3PTw/Nux3I2kjPZ49tKdoBSjesrdrmr/WUlZo4wwVS ooeCsOn7/joSjN6Yae2SCGk29TqjjpwUwMgS4oh7fD+skG3SFzikOMwSj2EqYagU6KNFKsIewHUn 1VWQ9MLcsJtFCJe7dPbV3yz0+600OrzQtmDQlHq25IEFjG5BfoV6Fq8/WcgucfSf3fzZvkNEOlw9 /9/Oyhd0v1pbMwN6aqAmIOAdR8GSW/b3T4y9v4GDTL5Fs4UlfD/QqLkHVs0Jkw38HMkvwkg2WLci 2KddyjxozJ/DJqay1he2hxkSCDDaxgSGFTRjL0MkCl34e/3PiOvrW63vYspXrRdEFlmhyF4BTI+s SaE8OriWhJDoF+F5+5StPtuP0I6XfxuDPfaU7DyWo610fF6WkHivQQN0muQGTLqrXz2s03e3M3kI OF77IfBT5jzZzUmB0X456TVEQ++RQ4OM9390yPUkWFsH6+4f72Tbn7RPeB2wWlS/9vAOH5NRIV9I ej1bi4QWvNdZHYcdh4APbfgkDdTdsGsJV4k60Omm3vfhBYhOzbPM0/DejdAgQkL5S2C+fvwJ7iIm 1bmiC1PNHPQu+eIYXLQQdXF18eZIfE5ZM5DQognA7QA/ughso+y8bOy9iODPx1t2oofwxv+U/ciZ iy5BAiTDkUqoeL0Kyc28jcchiiDV9GMoYo+nqtkbgsIBdGSnxL/3as3S6SpcsMi+8qKKBMhm/KPY 2OAR4R1Vi/Q4n1KzSAQgnEXAsQ5dr/QIstRSq4WFA0TKnLUwHnlxuXHQvvXk0zwNFt6xmQEja2Pb SVVyNNqLPmtOOGkCcwExh2TGNia5aYFlN5UB/Al6tRwQLEMy2hiMIpgXCQDWjoV/cFMTDL4x595a hVCm2wGyQJHpQ63Y83febTDu146qqkbSAS5GKTt8ngtPc9N5P2YVLSVw3I/Ugod/ZwYpHIEGrJPH DGCCiIxq0RFPnxRxywgvMCPwHFR0RPECMIWTJ5WpUQGzLkdWV9d0c/cmln+3oAMktrCAVg1btdzs H/2MDyAFazYLQ9a91R9qBVQnfStBUSmrqM/vcl7QkoZyupfoO/jmL0r/dNKjgaUeEDgHHxPx98sr nE4wVg5Hf0dV83kNdh/JwgR9AOzN/FbHizZoRjMyOCMjPcJw0vBUDXxoEQZTCp4e2YBAxe/jCakD NOf+3ozQ2czYZBBpVJK31HP5FjXxxMi2gU125KU+I6cLJ8TrE9k2czmrvQLyqxblakFgvrg4A9K4 9tgpnww2JgvavNnn5U274DDW9aQmBlQqMblgeaOxSuY37JCjvWPRwmdqoPf5zZDcpVNoCh4dazYU YzZmdv30MrBEOOtegLvxInkREGgbuPAAsnJ6o5QCyTRpndYHLLTo4SC/eFHK4pDlbFVFMj5Nz/i6 7gZdb2s62fPjd2XLhAmINhwarstAWTfDdwfMjQNHiOpJHW7k8e1riuwoE4zUi1zvHno6y6lAfp42 CoUtnUmFU/A4BFxAMeP4ne6FybG3ahYl4Wj7G5xfF0i+YAqJX5uQL/GRKknXIsPactwrFRqr9azI jZXsuasTLOgen99iDnSUZYLqSMJboy2zpJaKwJjrlXlrNJxFk7MTZM4afVNJWyiEKzSq4oxsTxaQ K/KNXqM3koMdRkujYqxKdr4OD7IrGkRjtMf0thwZBt2736suXN2IZfxjPBWOkm6I3zMvJCp9kSF0 tngSAuBgTYD2I4ddjWMF1x8VPVCVNK7NjFn81xIPq2UCL3Oavs9urFvu34wjPKag2/WXdxIlssTv qeH4V7+wGDmEWZLPjtPhxepTiJ0XQNu1Te4VwQSkKV+99P3MDpan48dAKsCCF3ZexQSH6suepDUS pniVfMXxrqQ3vrmVSHLHW/ae+yAGw2qJjucBs7cbEV9tWSTxS6xigS+6+9BJEacN3Ww1JAqJ7bPB kmxsbkNGTdXGAMKLUxx5lCKgM0pXYaI/PxozNYhjU2zaLuilRjHOT69tGnkELrrJKUizN2dHN3sB QgWscXIukOAwiKBFUk3P1wTm96S1NadMNgk0a/6EjCLWDG8Q5TPW1N/u9q2S5emdyyP0DdXO8EBy iNYlkgc07/V+Svs7K2Zyl8Bk/rsoHsD52VX9eCRuy5nX7ArQn91FbqunZgofIrtkCTgfaxSbtuOE Td3Mgslt62FHgpuTJK0Mt4ZRMz0MN/QRqeYDMzGBhvO18ZROzK6ibeGN/oKdXn50MCy+jQPP0bwY 9pRDAxBn7eJJZhN6onnzaj/TDCiETKnsEJBHIp2vnN4jk6415i2kxufFSL7r3rsn4lwWXzGPeHdF lEb73hzSxb+slQAGAypw438V/cyaG0PUGSccmCri7Z8KDxtVACPckfGQfzBv0IjyocH8eT/JGFLD YbbelWVjth8OxAVfB0yYHFJ72JWTy+7laIQeT0QQn5K9M3ZtYzioUbxxt/g05o6GKS+V0dET3lbK 3pQCd46B5bCRr6ACbY+zy9e0wxFybFWZF9zFl5uvnZ+m+PkgahvUODzqQQHuIkmQP3SvKygRw4xQ uhnriNguM2Rr7DMm1xlXqlS+zFCCSccUBqQ38GqR6IJJYGR8A6qMEiw+IMV3dgfjawkOwESMFtqp krTJXXN0beIYi7MjAobaD13vHL3nDjDNK74m0vnG2HkgZBjKteS+r1frJGDNtk3xlGnr8w2be2Rr qIc4hb6zZWOuqu784urMsWfTpH+/OXvN87K9RfIADsh9/rfI2qineYiCRdLQbARc7lenC6wdgPuW PEv9UD/IKlzjpJ5UbBkTucPLQOvKlBWW9CvNmVv6cWs+xw1qctkrx0DhNlZu1qUl3tQqMDHIOL8e s7Z+D0eH4oXUMw9wiJ9nCf5kwaMUeoLkDUDHCYu3NoVxjl/AvGoHELwWsD95yl3Ma7TsrrLAzerp 9atKvZyJTrapGYRf6tPRlKMGSfKm4b9tZ/0+EyuDQkf/6mTJCY2xOLRfb/6tR5u7TfJLjsTpluNV 4ye8Jpr8GnTfIo3rr9B/2Buh5c9x6xRanDBAKebDRpPhf0dYa2C2AfwPJdYYi7OoyBN9bCHlZb+3 G0PPFg0+Xbg7hOuiaADTfvbBUeJUQJSgVJC/riTeIZ+pT+K8oeLtbM1a5GMtDejFQo9rt/2dK6XE 1bes1/X2bVg9IlRwrHDYlt6eY/MPtsDIg5gMDL0moHkq+58rbsSDsRj7w4+HUiKi0XEWx5D/yzIB 3W+sgOyDUAnxUSpcdMlbdfyG15QZS/qd66jKEhTHnDKKYIN4xqhhW0HuNqCGJswj3YveoTZ/Xi61 bfTEhK5jWJvzXzyjk3gPH/3TimkYmy7J1O8AwSzFzE/i7YDeN9YVKD6mR5tCO5WzOdHILc/IjV8m obL3sa+FoBMfz6q38EiBJspxd1jKu1tvYPKteLEBSkcXU9NdT0JBePZ213ytdka0H5N41hD9Lz5K UlmaHdP2sbg46d7LVlyJnnip1qRsXCJwXPrazXz5oNyycMzysE7oXrv6z8CAALULGYcr7zxUXsAq OYOzcCl2Q+RhJPWeFjMcA+ikOHomLcKjYWt4oJyGe8NgVIQwdvI93uc7rgSook4JioHnvXfauPWT 8zhcaeUHuj7RW40S7T4fmBLhweeUMEj5NvwuMiWrdMQXNmYXwNwWeISp9QFh/FgG3PlMhE2yMlnl PkgFC206931o/WfWAc8riiIxu/6KSo0VE0Z4VjQwwRIrIsiTHNT3Rr671I1nqXNpj+gCNOvKGZDk iu84kjE9PPZyMUpx7Vgt/buU/wP+g4+FksEPiNrDDvmVPhrZw1XVaCcdiB3xKlVV9ZiessIcxsWZ 1yGs5ZyTOwkLwIxVNTjehmsHYjXnULczI9MVvknPvVa9mKBe60efjLOHa/mTc5xKDzkuRI0P/l9i n6lrm+5AsOoo78bSzJX2qjArbzgIWdIaq7zjIyegH/eSw1/wj5PHeug/ueVqYctUHAL1HoGwmyFZ 2YlvK66lKLepy8aW620lrq29M8u6FFfU6tfVkaz68e334zoTsSigHCzZjAV4/zM1ZajWE4KKh/sU Y+Pid5OaIYna1e/4GxJHfrOHxIUYWhrz08Pa4McehJWJb7625iwZO7JixiT7wAXZgUHLj595DXJr PLT+eqH8sCxjp6i5qhTiwRjJqvjOZMxwXzWsEz33FH8oyNDzIiXfxzRb7mtwZVHBP55YQMJFtHZW 92e8hCyvjktbbXsY76fcA1J7beBzJ87w7uBt2dmbXnIpu3WzrZGXDDmZBg3E15at4aR5s5lA/exc 2AzIm5mSnz/gornVFDIHYvdEuYPfOD/VjrlMEfLEv/Sl5IwjUX2uhpjcyvaPPTbD+6DSXLPceEEb MHY0dlsyIFUaSTDn4hLjFiFZPNQJJWCXmClOpuHJhMoHtrC9ttQ1p8uYDmzNwcep2vXkRtTglrtS 65zQBa/eqyPVtGUlPxTrSXDPu5G9jTYLIg2C83fz6/iNJMQzQ5QHF75Rt/Vb59tIFQaEMh+sgkTx UhR6EG3EJzH5WA06K/z2uUCX2q57ERxmjdBKS++z1xIVfuCSjuyXO5PeUIF1wtc7lkYNIZfsnjsL jy9nlpfNUycgTC1l+Z+alOY4UfyNFcmjdc8SIaHYzA9veAmBuZSeEkNLuqwMvPnH/Nj0pRKk5u/d TDgneibXEiitdayqUFjbHMSRDMD/DL9N8iGlnv0M09fzORmlE+r0SR58sQMdlO6un/yRMYtOLx7H ZRMnZoj/jMgzHuhHAUFTctlROJDe15NpE5UjTYjxcGSSaNf/0868aX/UJnvdawKP2iCl7TI70Kxw NNXichBw7Y4k1LlFZOhffLH6HKkW7CmBGucpK7g7+QQ8GFRmApwPamcGscfltoQehuNfl4IE2WiM yEKgX7Rfw4PIxGecR4SQH7Wgd+sE3BPy6HIsb0P9EVLZ4oLuVX4fapFCOvwzS7zKvdVX8CtMCFHi gSoWWQE8kZ+GxY62axwKIGt0jmI9ReMVX1T7ygMJmpNG8iP1FRMBzq8BEA8gLANlrPw9y8WIYi99 frEdk/rtMHAW64KDVr6izuBB3me9ZeampztuVnQKZOAOxyWqu5s32FzjxFlCzfYj5KxJ3JD3bWkn 6AzhvuuIpgSgqkz9Xpf2wAOQl1eLIyJa9uhFpojaDlBuflLIWgSmHEv28eMrXoKfIiiAyuK3yUyd 11aKNBlghihSHvHpbKeVOGpJIe2navtqWABa/Du8B/4lcIxgVlmbdFZlo0NtuTFBn7VenFC7YR6P dFjMpXPSx7lTAp6YF7jWPePWMY4wC+ixdln0rxzKeRSJ4CVTkFsMZKN8RzDY7W76NVpqqPsaY8MF YQccygz9tAMN3yrr3wcP1CGA+ljtArtqsM1iJmkHuZP3obKr6NDTTB4v1DC8Qdfp2yNjYrfxr0d1 jmFYzR1eLweDygH/Dh8/eIsbDsY8AhA4+DzSTEKSypTQMzfc/a2v6efINCDDU2aVCPqDpyBVWXwX iNiWbnMy9uo5oy8x1bZfqhHZXMUShTgQx5fB30S5Qb884967SwR8WUeAdO+3I0o9ylHuxIu5b+bp FEx4QAqPQg3X6pGWv8hePKzFl0C6BRFBZsb7ordMRfJeKp4NzRoe82I6ISTexQJmp+3V8/RUTC2p qec3gOuxhQe1KC198Tbczq4RZto2tm9KDEswdRmXHpDl2op4VBoQt7Uu7kIBfi3JPjZF7Lo1Rsul Yc1HI3SLFzE+JaB0GXntsUCO8KQ4qfDakJJPZy311X0E4gyoZKpO2YMFNWgsxqj28rRJgKlI3JwW SNf4jkcr77x7sSln2ZMG6av+jfrnr4Bc/JPNFFUgIJFX/sZv5IcUez2T//NDSssykmLyeBT1/VcB Ks8hcd8kppB0J5rotn6O+ZLjRA4Y6mXUwiEgBkIuWiwAOSqH1/AvFuWCgnofPX6cGiEZKg7+5VWK Zxk+0r5fORUJiWjxucwgwM9tXZlqQeGKXhG4LWLqwyntSoemVc77j3fNjwdGYzKh5pOwvERicxMx 1rKOPW5XJAHbI4CAJJaDU5FR7tmd0zEFd9hUjVduA9C3QW2cXRIZ1G6xKNqW7TMXTzgoEE8PYUJl oP8zJHmEYqIn2URMmdOOBgq6qovwAvbvLtkBCNbDxblImy4Tn0PSsOXC9LV29kd7KRNqkGnXK4jU 6xlJRJ5EpqNQbMxKd5AOGzAELeOyu+xUndmu2sBMxawWyMkHkwtYniZghAXmrXsya4pQ+Ne3BiT1 jxlW+t0Loiqp4uYSscJ5bCtvOe8xcrlb21GJitfYvhfG/16CUE0ANGRImwOrwkSsrob0k1hFwkz4 iEhTtaLjcDj0ByuXk1rqZkxQk6+tD299ungNQT/dZZSo1pk9AQONPlaUw5/e81vUJOjoMUBOdv2d P4CogjlkzpEv6OFMONGMH7Itu4/k1CuvsRQ4SUrFWq0ID5oEkhDqNqeX/H8FEABmKyiKxUR5pcQf ARBCxSPPezblV9/vZaklJBtitoIc8KessZ1GPYxDptSbCVFw3kbfAl0/qj4sLAWUMbifWuCWBPtS gZODqsadMYSRDKCKMJgCjS0LdI7nRYiK5A2URcQ/o5f7qu+WLjr6miVx6FrIrKxJeVBH9chXDCTA cXGviH8gu2V+5UNLnqnx4CFVAYaiNepRfLVRsWgsgWBgJvBCmWnOeeLlQJP43B/JZc8xcUArE1XV ks525ued9P3icgC3JoJ4qGKaUMYfVRBOof31ySm/grGQzNMlO1XYolUkZk8OIMZBh5HMbgeqdULE vyLnDXOq9c0kJf0VBsjzKo6IoH2KWFRx5NkKtvHMrl7RAPcUsxOSKUoqdKgwbWuOe9bzYNP6hiVD DIT8V8RNX+lNzNjOunaxGh+h8x2j33v07mj4Iyt8X4kXb1JnBU6tE+xoMiY8AsgAYbW8vKCKGxr1 JP3wsjcYTude0UwozQpIWfetqKJzYM3tZhZQJsS1NTK6TQsnfuTfvmbhuyCPTP3IyulKHFAZbjcS IkFwD9KYkXRkKtmTkTxXm0IPhoh5/7xZ6Zla4l+jmTKX1vpPAPjTMRggwFxJad/Pe5dQ80Lre1ju Ndc4Z17eAmx1GsAiHVtYNfrh0CULI0WX1okawfWvqstPVPkWEcQdWv43YwfGevcrNn1d8CexQVhk Wv9DEb+4ToXYW2iYh96CCcokXKhCJ5UYEZ3kvDj35zz1UEiQ2BpX0/mpt8xoPctE1TxkrOzAXffV NvMCuw1zBIA772y0eMUlP9pLlWyyQA5JFQg05GO1cF77tPBYh96NUKA/jQqyKB/eIbZ8vsQNf+sj c96fnVCaPZXpc9mHVzD1sjxzdx4CgY4i4v2hjv/GPHI69vLWaUA7C8G5K5ht1jzkzksqE2I0FAMv OlzyGAPk2Ba7wmcHaImLCzU3yQGImL9aVVAhHs+VNU6UfvcmcuI26BCJ34T/Q7U6/63BUjxfNHuS NrgOY3uuMC/I67DeT61nEB7hm7Z8nVoIP/FYlqZsZHuHSpLy2PS/fdGuPEoOlS6EEdMCSFgYPQio DOuhtUlg48+r5msGVQgSX6xPcPUQ+kZRh2s5WGIfuTFGQRUbQ2WnzlV+Rz6+QHCDCnHMmiwndUmP xG22ECEJYC2tP9V/owFplqnJx8Ga2Kg7H+doniIwcFsLJVyhqp9Mjt70Stz+ImT3WHLusU4BaAJx rfLCGzult+peEQ89B4iQxvqebSMny+NcvhnU4BZJnb3Qf42nmOw4kNvYEFeoASpAGzpi5cFf5mVO MNXfCfsuwZDge5bPpNZ0x0ph4fDUdbwlGsThqqaTizTPEpVgRnEipw5BImNv9iLQ1i9Ea2gVpMv/ flteBvVFmPX/jBstc3CZWYw6FleiOw+gZ6/UARQlO6sgBfTvd0yazIahM100reidfOXk8mF9yt0R qDevJY0dvAn+tsoslWFY1x8/dGxc/ty+Q+o1cCsclBX32uIL+kl0UBTWCUgcBqh9ObwvDyGJWja7 Pe0cJVbaGz0rLPeQqcAaQELtKCzCTfsI8sFSm51UiwXiRZKW2Xq1B5Wjof/aF2qAgOqa0IsT4xBJ G96JnDhB1nmM/Z8QRstUD4WBIUwwmmDTR+nRzlzbcUHgXqum3k4wWXrRKj0lofL8970oFnQXlisp Sf3vDqrMFQNYHw6++ulHiBspih05pdRaI8EVJZU8ZXtNsI1w11NIG8uFg4iruzsUWMOLqZvb7XD3 D8t3xH21IFlmnR1esUdwjPCpIfga+IpArc5n1PVlqedYeg9tix+G4C6++uISKlnkMFtzPZfMbdyG ghZsNWm0QhjsfXDt9bNJVuz1h9KUVoj8/XP3lkiceIorLc9OM6uRX+TeXu1QabSzeW7RAmfFJiJt Zpdo94D483GeIluu6WWtohHb6Pifz5QluahvGhjTkIMgu9c415Amfv6fgpny4lL7wb4dDJT1s1qU wX+1ZovAP/VXnkWGW5I4ZI0ftQSOqu/JwJ4gmYbiDb9lSf2uKlNtwTVbXzi6S7iQlq9OpNNQLa5i d7cHQ+fnXWY3lkIgAtB3i2ytXgIQGGLbRKZBd5cYzwDHEoxnMZrk6VNUGGUOmWlBmvYdHLSZ68aB 3E/Ny23iUBR8DjjZpiVaBU94EJJWpLJaLHfiFrEIkmlsJfNqso0weAgV+1da1vG7CAGAkhfgOPnv kztr9S2SggZ5IyGlzkgrba+2CiES3NIk9Q+j9oio5QMOuinZIxQ5G0Z5zom2AbbCzm1HKSALStXL 3S5Xbf/lnvbsQ3zmgHYCiXjw/D7RPekgCPhM/SjMFcwUB2mzGK7e23TJTr7eQNxBVvMM0aF8QUP7 mUtdlATHrp08y3cFoFZ1QT96C/zMhNE9WTX5uIA9hYqy4ZdjIjpnbWVLQ5dIrl6+rnDLWgZrKlNX /QpHo282MU3B5q3+NoGLmjyRv1SnvIcTGnBQZ3OAXVPLSaIwZgUCQJeCvQBiRExHw5HAsLwXRP9e Jug/v2dIyXjG7z7r1mWfRNPtyCNxGXZpfazur6pwfdfRvsYni7Q07N3PQuRFo7A4dC29S0KCrOta HyLF9UZMbS4RQUGEFHymw3L+TO7DmWYxe7QsbewgjgV5KHnaxdXkYFw761IAkCHURiuOnQduxXrf JYu5ooCKbE7B3RZ0CU09Gj+jlfnZvIEZlC9O+5SBUCQ8wYSMQz9ev9WY7Y2jaz7pl3AnHUfnKGU1 pWvq786itvJob3xP/WdHLgBfPyYvm4W8M9lu97O6woifa8TChHx/RfHd3Vac/mAlY07A7CfZlQBV PnppoDmonVwnQu5m/qyT/XjLRH7q0+95N9Fdq+QZQOqziFlO3wsBw5gTbWq/hPOeLzb6tMYiTNG6 pCi/+ei+3iHr865BI8J/PlfUUAD3mQhd4rvgtLFkBphBHoF4oHN7JRfXmLhHiFdu0gs46E87Ax/9 nSq8eeMnrnLR+leKJMAZh8s/e9VlMbWBdbU6ss5Goy0a+crlDlsF0tunJbPdsqSQ3/+m9qiEfkQ8 +Zln/HeZaxucXoH6A4TBurQGRqtzonIMF0Y1PRyu/GDVKIcg+falsSj5uHU1SxwHBsBGUtZiN3bs Q/YRlZiopbbflWoHyNegdFGbP5Q4rELvER0jgK6V1WIud/P+O3v794aSudyHg8FtRne/Bw3JHisB Ra8ugmXwruE7v0z3pg0JtCkZj7DR9MlHq6rx6OCp9aWKd9A39KePe2q6sTIbwQShnwhbrs6IXHBn hP5K2DFXqfBi+mwbPSmNsCZmyi/b/u+KrcUK9j0fua97VYZGWQ5tXy1QkZWI6iGmGdDUdDor5mph 5U88LjOHCPSjxIZLbDXUK8vBXzK3jWds2fscvnPdedpzbxwbB5eELxUcWURcXssJmm9mO8H4t1us jtkRKPkIdz6BKJGKGVGQWRLz3L6DzqGoo5eKrQq4IPcB1vJf7wGvaZneUaDA7nCvt4KUDVXmdgF9 +mljvNJ63u1sG4WAfdxwINGsNDVRo2lGa3VB01a/xA1JqB5v/Rvb3J3SarYNWdSUttsJm05UXgrc LMLqC39RuE30UI0UDARqgx2q1calv2o5NIbA7eiYwRl1L1RvY91OONaqfAidZRL3Rck5+n8ChL5X q2zAl1nnbZAyYoNoNWc9TycYYNfPKOyQjobdt9JGWdg+aitiGWAYk5sDmJ7a/fqNIx0p8hAaSZTC 5Iehx8eC+3cohwb/ibmgsJkpNAiqW6b+e8Nmydu4aWEE3SbD7TF+o2kAuWwsNUuRzg72EU3NY6hw CV8M3Ytwd1TscqVpJNV82liDirATeGWg23dYfkZ9f6odp87+5wErD9ODy8enZ25198Y6WINSW3Pa TCR1Ggn9OueodOcy5h8vOlspggFFQAqRTjHhU06jYTdE3alLaUJoBJzcHCcd5n7sK6WZnozr1RWx 0WCnbqQHU7KN3eH6oBTL0abTpyYb6Xw9w+XUbsMQXcgxJiuLWw7pk3HzugUIhc58AZV6T1DbQZZ7 Nh1Yu2DyyumcIEM0a1XHOvd1+qTy8trn8KOh53SaUcW+MGQ7/ah5GpA/huE5Y5YXkhYuMw+72e1b IVl/MNdlD9J2+XVwq3vvF1Z9Oc7iPFmzYp0vZ5H+ijXlou2cgtE1KJ77wV5pF/27y9El/9alPPZE /UbdPF+NCoIzzPOr42hJy5cDjxrE6ySiQLnPUGwpFlBy30J7QVlcgMYC1Li/ACHBc71omfIeySoF 4PGJtCtw7uyWaJLd/Aa/SPXo9iTDQUbVTmS4ipF+7EYuuNozLZBEsP3wSpqVhcWzO0g9y6Q06QHq TPwj0tHmEVu9T0GpDGTChUe6JokI48TnaSaif4xzv0sb3O3noRD4sabRO9KjocNxCGFDYpS7aC7u DFzuz6/Kwf1ad1qQpGrWXVfbUZW/8wdt+s4wohbV+3CBEA8LLrRTYFaMmxyNgsHy8VUn1x1wpC08 gKG9Zwdjq2NLh9Wuvu+AeEgIYTtF4X0dqdPFsvjtlNuwnQhrjb6oJ+bK9VXQyPkdp7Yrtwkk2aqb GClJKulAUirOAD52vPVVoeSXxiK018WouM2MPRJJYgvGuq8jVT4sGO0Zelmg7M5S/o3kdCMNpkB8 SNAisH91XKiH/1zA3A7ay0fYKvNwPZr9pw2w9tEy9DOI2FdTy+t8/UJklWjqehU/YelIAoWLOjcm lj65dldOQw3SZHBQIEc5JkNNFSb+4UJ3f0pMzAr2aN/PqSZ1qCFia2g20z0cAUS6snnI4/7Kk6wX S8tqXhsXB351IDEMF27FhmgtTdn+utFEC1ZJ+Qf2g/JAf+0ZTz7bQAmnblsRi8LE3AEnUxuNiJW5 uHzIdtX87WSTQpsE/4D3TMkmdUY77+IcH4KXbFHVlwpGzw9pNeUaFkgrY3ULPSqTJNumYIFwEIKI tDEMj5/SXnLaVJI1+WlzEQMV3YuMfpMC04m6/SK/NsoHA+hKZz0XPW5m49ikQVMCC6eZhgXrWprx SCZe2VOKjvGcnNfYxmiuhlgrvOBJZMinai3DFkl/NKQgVoNJjP/cmq+Aji3qEzLTRnzxCBNx5s3F hBtnwAdseZifglWuWj4RSAa1x+thq9HNCtSc4cJB8XL1x1FBTGuKPtMVmJc1xeWdlmMrOyF5uYEt jAmxqy57u3H9Xv+ztH5WyhldY8ylc7mlJntaJt6LqLfO1KBYXVKYvBj45K8rrpBbozJwc+gfY/kV R14k/6/FGO2PC6TxlMz7MIHFR+8N98Cc9995NH9u0DxNzy5GwZYYyZtryeLK447Y/OoTIz+okMV/ YQ+a1F0zLvzd/EWCQeszG5uCOHztVN05cs519dD5c2hPz7nQoxk6YL/XTlL6aCUM+hEDHbTLlB14 MlPOBM+KOuA55YYua1MddHdr6MO0DghlYnHSZOh9AeaRK0rYghgvUgcepZ6RTh1Zbn9FlhCgI8pD 3Gv2jMZSlj6O6ACUkG2MLRNuDuDiTQDrS/Xv/0qlFuwwdChYEmEIw9oECgylcKd/qqsaz3LnUs6Z ocqHddPwpvb5pk6o3lJ6fjG0buHCvy/mjALqQJZei47f4OVPXs9KyrtAqKZ2MHNW8b+Eun6i321A hWMX7FDHD2ufvwNHVxMjrOSRw+iUPs2otSKbeXUrvbIPq5JgmX2p/CvknordLmlO2bjCIdIblFyU a2BEqTvvl7XF2gr6cswhLS8TnW4ezLPiLUHB1WyXYgFT3C8oISrINXfiQTbeicevPw68y8fRpgL1 6ONEbeWtt9J6qKVA+TPLYV0aU7CWVV/DUavmlPoBS2Nj+fSZxbHz91OJzDR26Qt/SS1ZytfEgEAD BxFO9l2oi518/KOmSorgydq/tApnZyTiKgd0AjuRIQvCQAstpNH+FmSO7Wm6bomPlmhvS0+ezvlH /4RQwFmeMObF71P0QdFa0Pl7nuFSveoXC2umDdlEvw5F1J8i0JYNRrApYYLwUB/Xbg0PR6S2Hu3/ gwleu81nviAKhUaOWb70lghdCY/EX/Ks+ZFhWkTVAHhGc1uJ8gYTtAoEXeHmBlu82YUO7xJMNGFR 28mTXl/WXKHdoBoWwKFxclLuL3G96sQ7uQaThb8loXwxa95lhcG7dVS6fe+1DdxnNm3tqjYd+rAG cvOy6bVaF9y2KhCfvMf7pqN8j9AFBQw1rcM1k1czx7JYUXpyzKbnPx4nrNbPzlTHpmXwetvfHpO1 WPcNfW0veow24ho+VigAMydYiv8nTlnjdb1q+xJg55YLTc6n3D/FEG1Omb6kXi6DkImGCYqA+gfw 32zTetdQ4ClAZY2xVH9pxXfbZ0Md9fjoGkKeVHBFBxCsK3iZCJwtRtRo/6Te2GPepivkRC+N6fIk wynCLicEkKBzvIgKcJzc+dYThnMc8YKLkcyyfq9p7TXOSY1vUMAyGDXtqzHry6zS/JyIaNFuvUus WSqSefFG+QaioDjBbp1+gJfBX7zYSGA/RYdNnYnY0oWrLBynYBWeqjlIgfeQOGhvXxG2nj5j4MGC Ls7849gvD1q6Z09/8/SjkwCzCEc1LnKrXvY2GbluaoLxoKXIt0ORrHm58CUwfknxuXYzctQkrbWt b+g5ibM14Y7Qo7hGwQeV/FuuZjET4X51iWrexX9QhB0UHlwP4MlzAZS+cuggFIuls/wqOz7qrud7 hM/NZhas/FsgCgWZ2djyLiVkw0PX+EfGlrXeSPDgQW9GaoGR/E4I3Nxb39xIlUQP/nqEArOQ2SFP YqOURlZyen3Ug2smdQHnzhVmSODk6G6k92c8krsZI86M4bnyYVksuKLRK03XJ7XbXE/eYl+ovXmz IPDiEqnCC7lV0lmC3DaUJK1Ms3ZwXNLpzXWtZxyO3OjGW0/QiNM7q4Wi0ucL49RvRFeNspb6Jg4M L9ZfHgT1TOgp6QyGXQN+lQDUyzkavU5eVsybqCgB2xnODLjMU4WMmCBXmvDpozycffXKf7I5WaZh VYKTTpTqXgd6cUAOi8tD/vKCK73yOyavk76Es1hAe0j0CC60J2OmAk8xoRn2xO4xiuBWkrS6lND2 2Dko6e73cBBqdRQ/svIc4y6NyIP6kfE+kI0+1Tp5pkdDj6nsyA+Y/uPxB7wihWhHWwI4wiHiOWS7 JcQztTS1K+ulQ7d4grvVJ3IPxr+y3mEd6paLjD3VRcEf6+sCkGt/3tGkLwL5q7YQUS6Dc/joi31v e2MuzIGkgTd+7DuLJ3WIvudimMMzLKRcQ4u7aeZPMZdBtBaBn4gTt4MOujZJMvt60Qp3q0qBAWFW epsg/njniZ4aWl+veZevMa6HT4cG+cG6g2dGl/YzKRf0B4DmNmnnfBBVyWykq9qM9oUW/0iq8ddW Cy2PjVpD7L2b1oooC+jgcsk02kUN7UuyQ/n1I9NWL3jqfYp/5eJKJx4LAHJAmQ8PNIULc74xGOYq IsSYFErXcsxPey69sgWB+qptEbF/6r7ZE/d7fCQXkNDvo8KbvD2+dVuUz/rCzoQNgE9D0gfcvoD0 C8b+8H0qB7WNDRreU/g5NtzgYjr20i64f4Q7FJUgMg/Q32j2YzKhg8eD0lzfexJ1T7McGpYWnt7+ j/hTRjlBgGrYvHEsWyA85/9/STWCz/T5utni8wucizRImOyKcmawVMFV+R0P5MOlgS11hIjkdAMP zvl7IPjsAnBhSAnMyreJzcvB9lIzevGG10Lad4C8WEEoZFw8FlB7EyK5H4IGplNmwnbsjjZkPehH 4zgMEHS1C/eU17bLNcTsDlLZC16IjJTWe9ZbUo/7xUuqBQQ9NW1q15EVf5SOt6BtOuOD0u2rtA9P bOhdxdqjwAUFxbuUvz3FiabSYLAlzSpZZ2eloVky13XytCNG5d5R8IQVlXLgSZ2W+GDS4Xh363TQ Uh+NR+Sn/a0yvCC/TzmdmZimJVcFtg1AdNulKFNG4/bbNrCSbWWqGhI6JZYaAvhVfsteNdM4ZZgZ b89yHKhC0LcmNpq53TAIjJYD+MMJ/MYEad1VmEq83JhxzqzO8Bg28U8fCmatoQJrUDFxlMsa+Ev2 eqiyvvJR1lyKSAuX7iWgdnHSj9bUxziGoqqFsoiepVynTr+6cBWrM6+MNbsNRW1SQfer2tvOwW26 aowze5yRsfwnOZmTI7zzswa/C2ndqCdQECAhmFpXn11DoK/xjF6+UyYuMbTK926Rxra9INN9bFR5 fT0k/PQV9C9CyfhF/HBS6IH3qpNhW2WFIBNwGOZ2DUpa6OEf1vPziRkZU39++XHvdnGiu9ySqqSD /a5MOzXGUYwKPmprGgHuRTLZ3giKNgAaFzwIlpYtspEXszd43cySkQFH92cHdAdtbkyzbyc4Qm57 RXof2gvWw+gP+WQIwiwODNIOkX0AcMXF9UjgGJLOrAwi1HJyn9q28dyrjU4ugpMLK95jNve4zsIv TB50d/QtPh16BXjupVh/bGmmva8Yi3I2RAa8kWyg4UQAWeAQ+a3Oe9lSdq3l3MC+ltSUoUhc5MLV 0uf7KsS53IUI3pceWE9KVTA1rUVg8nAOb5UwSmDBfXBaYm0Pg/v532hVvcZJKtt9WF7nxLVU98hS q0FJrXrdEffw57ejcvI9SmIJBE39BUG7UHJGchnoBDByQoNh6pVGxa9+1s3v4H4o551hmj+0Po5u TmwvUJuOUoIbazJ8keuuvq17cMQsIX5CbV+ARBmvhAOgQbSOkidNNq9TuyOoLgC5NmtzU8w4YbcG KYjNhzU2JqHbK7pMrkVHeajmZXmQ49mTd2PaGNijqvske+jjHMCjW9oL8v3Snett+ccHk8kDzWud Cwwn+JWB/AraTYDGxjaH55A4e9t0neiUQGwaNv/oXFA6DrsyUudgAJZpxtrImUKA1k0r8rajBMkQ d24ljZbxXGLCz1wjVJ1/e4jctwoiX/AVrvbbkphjwVeoPjp00eYszKebu6RDjDhStRqtuk8LkbYV ex5HfNi+HD2SJexaJuaztaryGwikzeFKqn2LjgQPz5pXcBBnB0Qg2lnRGhiqeDff6D0UdUPI6X7D QDOSRNQyg0NrZEezfhKGActzY/0YVHm1B7eriIyocJgVHHPWGl+8i7ylsJ0EnWxVuv7AE2RAfoc3 wJIV47KvB5wL3MqFi7+0lMu6ZIg5AfO18ku4yePJ9KchCs5TNh32d91BxTzjxEWdFZSza3IjN1se 1yu9uMO/Fq+XCHjX+zOaXlzg2/ixyQvaUf5jUYLfk+zXIv9mE0desGOT7OTpsxSQGVQfSPBOkoT4 1k5pdnTNrsqe2yFjzJ75mnO4pHOpsvb4S7ehxGa/nYrKagvi9tFhT7RGTQZ/hGrL6E7bw/GrlIUG L1ykca1lvm/jwtygtc/kQ1RcgcNLlrd8okv4+gT3GO6JJtAOenizX/DQHgOd8W/EDQ60jAWHzpnl z5yPkXU3ZsQotVpnjDE+68BqWPypbTyqcprw3b7hdfiNF1Fl5o1oxkmXAHxKwFblj32rASpEJ23N nGs8C9fL6Pa00GqwP1p0sygRzBKjBVEDxbuLyTWxUh/VL4iWetEMkGm0FhlgsIvvbg89xFJE53Fh oeW9Tk0VrEtSqaO5G8Qi0X8A9u+GIx5aV6MBxhRjphj8Z1YOkQIpgdkinMvDf51siZtuEaLNDaa8 t70SrhYF7VaMVg8g7tZuKvzKHSsEMSqStiJh4XHOEe2zlsnQLfiTGQcNO28RurpqKcUduYDQWYGz iP4PWn0RXyQfl2oo3A+56v+apDYqEuepw3R8PHnOvxHKK2ko9KHYorCocf+DllM8EjLyGm28V9Mk S9tnEva6IHiMufTQccTnSg/1nUnujJ6oLE0dnK3PNVy2WrF73abQzS9hVQhH6Wn0vJQj6PHnFL0v IoOzNa1sO/VmX3LxNGS17i1A5xg6CXj8Bggh+oWx89FiwtbLxxzWWTcZbUKgqWtkKl3BOOtT7aKY 9SrHJYWNUxLqDmQmXiCDa34lWZj60TKA5HduugN3ET6+hWFMefm4OjZzLSWZMZWFXJWbdJPG3tk1 xw3fQnBbHAbyl8OowkrRvyUXmB5vH6W1gQORa2uM8JkW92SQkoGAxZrubweY+SyWxJH4wfMiRhhH ZjQzZLNqMytNk2n5OF1OMhSkUyKFQee12FIh4y9uyxS5XfvV/OX0IKPSOzyFKBBFVaZjYG0xAeN3 Az5tVQccZQRAMscf91YNuVSzbxsd6e8wMupSTJobjueeiamZHgf7JFAwbiGmLYhfgcaGSn/cOaJx 9Q4EErdMcxCgyw84iYW2ky5WDwFGwllZBSFMzsGtmnZNTidQL1SZOBpUgkUo5DpbKEYOEXvWivdp 7LMNdnekwl35jyOM2winDHtg8/h//yhelyFVM4DYjevBWfE3EChpYHjyn0GeynmUEcWMG6jY0ySu 2eogFyKiQ+lNS5o4HPOjTnDyzLjKqEFZEQWLkfSQLilf2YIkZt6jukMpJ0JAGuZUBzHWHhkhkdEY 5dhS1apbsKuDLTEv9Ej3mH9rhYf7YOkiIux/a8qafE/NMKUKum93Xd/qJzFB6VHqDe1bsctsj+kX MwvTjq1KmgV3Ik74KxHtO9cCs0DxVRLgV1sAcsdquRdFUfUz5NdKQIOeWKb1mDDtW/nKZ5aBF16A jc0g47Y8cDrKgDIKJpUFUd7G57nz/Re/yqSbKiROYM0fBbN54z7u2W1KEdoVoqru4u39rnSAz3Uq lYqlqH7V7queuObRZhwwiA8DAOTAevvykw7h/p5PxGiJGFp0udWb3ZkZb12eS6sgF4QOn4OIouS3 rSQjpocZqSj/uswVV3b2tFiz+79DfE58mh/B2abSDWEEgmkxt3y2PSgiZ2zw8tt/hEAZF+RH0BSj /M2wkJC7lLJgleNwqphxTVEbAoKPGxfXULOZ6BRECW0FKXjf8zsVZ4QvXo8YxB0F0VQdPNeXWqyq 0Vb665P2y+i46+dT7UHj2dT3+Oa/AgTckvTo03jUQAOK6dYRcE/3AruYJEW1HzW7DoFKz6/1YNCS fw9X8+kG2hiagEhJXpG8i5GWFcgmJ1ml9TqauCaw0ZAQ1pY+thHPAcvUHlF0A3gDJQYeJwdJ1B6Z OKobNNM2z7Uuft8VZajVBhOp/7NSuG91Qnhtsord53fWruNhIBiI+vknptYOynsOhn5XYkOfKvCO aTa0JOfLVj9SkdFyI32kcvExZ1mqWkEgj3ApTERofL+eiGhGoOFyjvQ3zTHCeCdHaMTYWMGBgcvZ VBMW+PFQSROw0Skhjls92vV3Dg1CK8IKOOHpPvA8sGM07f/g9/STXjhiE96Ns4VM9Gy3BvwB7tZf xpWXQIgiSRxq6gXCEHT9po0f8QK6vUYVI7Mqy+5O5n4+QGJrZtLm4K/I7ZG+CMK0ztFrQVPvGmN+ M04ENJm9grigc7GCb43mNorvbmaHcX5AN+gFTsZobPBhlDQ1RrYij43uZ+HsmQAHUSWbdt+X7bU6 go6SHkFo5QRm8W27EQrE74ZBimkb8ZRVHHsstlUTmVR4Y5fakakEHMhO53QOz2PPSMdWv2lKYK+V vSjoXTSwMNV0vZvJ3Mpi3qyBAgMgs+9OqL4VEM1q0UhCs+uLlrTZ82X9Mff1K9zMfxY1ZgieTCIP WRGPCxop5y3qbELY7a4dfP7L6ngYwJFlckBcZqNaELaisN8uJo4i4XHzdA69oj+VIuZWMJ8Y2MgB 3vZB4EiYZl2jV31BBtpN4OjJLcKxZITXPAgx84X2iecJ2/ovAylJP/RbJr92zCgMzaSDPsiaagsX B47nSYFHmhuRGkQ1xjzyictKGgiwIapxK1AU6tlas82pb0U1xH63rlkxVAivFV4NB7i4BWNnvMAM wlQBr2Z0ka/xzkUogBNDGqcoack3+cx+Er34M/TdqeAdMSiF/d+DZF5ttWs1nhETaBeRfpRfzUUK KTa2g/gmabSevy4AVQ32TWzhIYaHnJ3BV2OfsFBygO9niw/kgPtH/gqeqHCtgm/CG63aM2aABh40 +YTIW9yZoXwnLOWfglbwnfKeqZEEO5kvtpc0KlKbGjboWhW+BK47F8VovDmp4dCFnngEnhOYhMcG eiaxeNRiVPN5M3GjNT907Rs7oLA/G/2BViqu6v3KgRndEFCs00/lKi3/m8L4jJHUlxjzlPQLDMFU C+dCMSviqav2RXAPuxPiPMg8x8Tqk2RwtUbiAsd781lW13BLSgQnwAujgC732Ra0Dk+0gpZgJ8BH C172pnxa3aSgwxrrSOeyenqbIXZssuVoWBpSo8vGINc3MdlCBaw4KnlE0ApY96QnClncg7x3qZA4 gkOUqRtZNGI2a/xCMqtpPPzvVLOLK2tOMGFyyaqPyy0IqiHNZ8PE2G3o72pbiH5d+if6qtUPACoW ++RMf19btg2YkSpq5YpsO5tK8Wa9m0yGAeinauRxI1DuvJJAUnZfXzKIz4nxDtSd6KnFJL6UdPBA KFnZoHkpvoQ3lS0yLFz2MrFOJdsQNf0ZsnRWaw+/yCBkR8jyxld/WIiaTDv1SH1/I+hDQ2sJbEy6 f7iQAisUc/lVnFfZNxAewNzRBp2qz0B/qqETB2CvzVoTkG5VRGutgY+y6D0MYgjr0BrcIQoTXf5O iS7rBf9XbVnM/+JIjypOp2GnUDdZeXLS1c1+koqOME/7bjhkfdg+twdqJeqGKYbDqq8LemOM131f 8d+CX203bmUHj1dvocz3ufLYnUYx4FDcPdRWfIHqB1qZUQSOwUQ2lIz35hTYs7m0c5WgpW4G+f0T 0rR9KkIp4YJduJmJ5VS2mIqAZbW8Xhm5DcQidFqrjiwJFM3msTP8XuPwaquZed9wXC0Vho2So4R1 sZECNStyl/dVBcqng7xfOmjFu98VRkxxPTAibVDmrDiweRWb/woPPMrQigHv25wxOPfuZx0PDNM4 m9/XCPNsk5ih61+EHOz2SGTkHSmAzBJCRRU2O9jSBOznrcSjrh1nOxOlMScmIsb0gY5cb2dBDjr2 yai73z9UEukbYDhyycDEiDHY+qm/EZtOPjh05/QHOiYsNM98nef4Xg5lwuQNerzdd4CHS6bhz1DK ExZGdIfqKmk1I4/emUMEl4yIP+3o2qON+Ved6I6ZLZPm2noS/hXsopRYpwPVhuWfJ3AztweJD7Uq 3sywijOGFwNVzOxsT8KUleueWc62pha3z9F2DQVikc2hpw3qc04IeHcZY55RZJCBP7pbC01jFKC5 2hNzoas5t9bKJOieSu/coI8sBX2qBUN9U8FTZJVLIE4P1BunFkooNEtVz20nl5WmZfnFa7MYmIUx F9hBJEF31Oayq0CNY4yufdS3HyxvWcewCSwyDH4jmXwtA/6+E/SzcQPmSe6xQHjUBkhPOc5CTReu dL47EhfSEPjzpZKFdvuAGqm+XchTWEzUTRQgfxYN46I8s2mZic+MG//IsJXydm9CQH2GjdOjC3ag Ol+FbpOmfj2sBwih1cEYD44gQLBItQBXPgfNBW9dmlb270gVq1De+KuB6VGOY25UL2Cda28KYXyM 16SH4P/viKwnyAdzByamAfQC12gN3etj0/tsavXhN0PR6ZxMuuaA/BUaMBjkcgp/2l75XoiXRFSL oFUi9OHEMDDKKMRgEmxlD2pSy6Z/I7yJk/EaW9PKSo47U2mb7AhIAZV8CNI5+XdEjwYSVk/bpzwB caD1b7LphWGpsF3dC7pOul3QEmnlK9ExmsoeYXWKTDnqAjOvBF0RKl7qzxCD5cmF6QRi235H6yrY nAZFCABBQARqAcw8vCbtJPupkl4MPgzMoyEvgKCAxKORcNgM2w6NEcUase+6j7XkeyMNHtFRwh8d dWTG3i4tw/w4C/RfDgIGAXN/rCCUZsgFxvvUcCYQ1P+6H2m+L5cVrW5SWns8GOC5ER6Fifh6I+JV +51rPM7t5d5GWDF23IKMDYyMjQTLhIGDHlFhQM/OCdC86VEIFKMNpQtB/WrTn1dSJlGSSN7Qiz9u ltY/Ern8UKcBYZFb/BQOVPsOvi4DzjKb6QMd+Vwh1CdID1yaTmMWmFE90DRAyYVzDWvo/tcqbE+z lnkPUsQsasoBBAs7Mk9tYZd7qcI0DILGvd3UHvpxCJU1RxkN8aK0mZUg3BDR3YRWCABHPVppRusP eR5ekUPtIygptSLpVw0xdLPvndJAHxc18hlipsHzOFpx0eu2RmXOlGIpasI12AlYtrPcphheBDHz FbhsTyOK2gFu2daU4L2mKEWEHcOlJ72N/VaxnRl3jUWACd2KIp1a+wFBd7Mf8VFHUGt5dLMteLU2 eI6zk6S8X1vCS9PnCXwdgVzoRXR/xmnnvT6BxouricNCuT7wQI4xMR8r5qT07/pW1p9s0i8T/fTp VzzH4zBU5meJFvz+ERaNDZzFshSvrjo+8PkSvGnHpZ5SfojKO+mXshb52pgxhuSZp0O/fq+rspMO L+7APZMg7C9m28OgN+qDnINFGzDEGmmKcsbvbb7RAZxIh9k+W+W6WFqcyKBViMhUcsj3jb5cVJbv WUzRytw9LGctwa3mu2f1HVtxjN0/kifLjtIasxnySMCNAfVfe7JqxdRbrKQ1fZuh+OcfmjwIiHgm qTSxguN43E3Pj2gprSg4d7hNXJ4C5avIiopOs6QVbzOo6zTXpCa+fLyklLvHvlEEQyUdHg1f95He wnQCX3ADd3mwe1/PUSgrDhCLtanoX/u6o55PSUpedGAVODaJB4i89k70M7rHPj3iqSJTb2pqkins qtN4ujmhIlCT2zHl7tRuaDpjNGrfmj1+1LrI2G/zvjvLEMwq7jEEuNUmFGBErDOX6jLbspgz9pq/ tfK5egFddHmo0E6W4UK4CXXPPPll5Djs1joAoLwlI1h4rlD0oHc4zzgmwCKTMHgahhYj/FI7bU2L BnpE7AjW+uybe2V9nXW0akx1YbPvKMbvdBPLvDYTb+9prjeCgIGaluzdPpBIxP+OjIxwRF5PAulR 1OdEmJhx3Q8vAb0dsiU/NaipIrCK1/pyISMLKzIRr3Q8RNS5+7yYax7xL0757aJnxaVmgbr/a0vA 3uCnde4ULBGVNXERcrDllqzYaLYSE9bjVxFTRgP2uzIuYTAgDI1LmXmyxyFMhtUx2OUFMmIYuru9 Whq/TL3o6h7i8sDajQGQRkZDOqsRJsuWbNqM3fWLnrmip2uymXbhgs0Wetiu7u3ldfZ7PvFnm3JZ FqJAWGVQCml6u9VWgMHGXPdgnjeyXUiGptgQtDZaF8eD75zJTWRCiFgnNjGgC/T29hmOB3vJbvw4 q3b7tbD/pcLJw5sTWagcriFKAILKwfk6ugCX8P8mjjrshJ/1SWc23axnvCdAKw2A6+Pmu0cUDUft rRNk8izFMSAvuRQAxX3n9TXqIx8gwDFV1HDLetNGj+bpVQqScb6LMwEUHwYSBGlUjohKM8AxdXil kGN1T/JOuFqgLSuoB7wKA7gnlXQ6f8mQLfoGxgZJ7vsQy0MZI5gOJ/e/oC5TOkniZ5+Vm17Fe6XD 6Q6lVHY53Xz4wVfBV1n/vKJhGXEKg1jTz14S7ls61T1pzmHEenQoFbtK7l7FEWAQSCRAi1pLjKlj iNaSgzz/TKl+/55XFUHuh6UKHs12QuNpIhlgw7mFaUOe9i/PSVfueX80H9617su3J5xfKlbh2NFb jZevy/zOWquB7ijOyTOD/MYqPAAmdsUv33UZCdBDDkP1unjnigG+kgYDXFjWgYqWgkf8jRv1nb+8 l7MMMdgBVonarB3VdxKt+fr9odRw1qag2gMmeTJQ2mJM20V4xZkyyj6U26i+FEbi/S03yE8GE2oL 7D30rbfFcyiHNrZdAyTUuxJ+6TvL5/xcvBImtiSZ8fhLwCXPf3hBnO3MzuMoVynkT+X0tuT69KXg BYtNXG6pXmX/M+AM0AB6EhqvizTY/L9ZB8F8UXMfsTh/9sbFzHFrWvyt5ViuIWTMCVNitlliqFQD sYtotuFK/Y43t8QC0rEKphh2qbIeSaOnn++Eh8oN9Rrl3Q4bBVTAJpunWNYrQj8s3RJbrK4JqmDx 56G8x0SfaA+SnJRDkNL+dLSWR5bjp8NIw7JcDTHzUQSYK2NNOvOV3GWRVziq4URqne7BXVzbl/fE hpNDLGQUffgSWRfhlLQzhaUV//MtaB0KjZbx2EvEkxLubwH7g5LcAzWMqfI8eMPpJKEHOF4URBE+ AEhJ10G9QUNkAa4NJ1wP2LUHhp3HKi49QkOptlQ+SZzOANgMymlkccJmF5l1n05OibhQbkEYKOiX fVanvKSyElYVukz3Q5uedf/hr0cQX4UqMOeELYqzoPRbTdck4UfRUKuIpzcApy/XcwBH5N/Amdvi 7CGCa6PBtuGccasGPWlwwPoy8JIufjEYJJ5Z9l0u5UIwFsNSO4V7aCWv07yQMKmIy0PRQvsM3kA7 FaARrMcSqD1laFE5H0tPO3qHadPYW6f7gGjBnjVoRZjqTEnxaDn5IEjHvF9oYlN2XgBsdCSMkL3I NVYrMWMyi+KccruGG82HIn8/31sPn5bsirDm6PQI8fNdKXv5Y26kv0KTZcgF5MgW8Z/kPFGL1IGi 309OqN4LFuvZJzZymg8/YrCQwzzQeiSu6oe4uwob8dInQpr5jaAw5dIgp+J8EkS+UZRxA4/rcCbn M9STLlK8/OFk/o3g/Dh8sOlUMMXVrDNZAPcPN7XRvdjs9SPds9u6sTDGxs4kD684G/C66HdVxKBc 34d81WPWKy0UeJOnNqsn4XZKKzIZYQrId4Ch/L1GD7bi9hi+Oi20cIcex0cvuT56qn61Uf1WZ78s n7MLSGlcO4W23jwGFWtcUsMt3o3AqX3qWAdt+OWPk3EnxwzD89f6VX3KxsfYf5U8twgAcy2Po5h/ JwaB330i7E/rMAlIXhO1bkPLya/BiwxL9db1Ebjl2Eh+mjaMJlpZ6RAIyp4GQh6cQ8h0njEPTOpm drW6drVSGucuBVhimG+cuU15fJ1uGN4m8/vlQP2L9sd9b5AaliSHHURw/+vest0282jHRWgr52EO BpTwqa60gXroqQIEMsRQpaOZcvM0y8DaH7vM9Afxd4r+atl7uFYBmxpbgyL6uyixZOTR6L2QujZM 8ch/PSqwybIQQftFgscmE1R3kYb4cLF+LswyZZk14ae5K7A3VxAX+Za0/tXyRIUYb7XEIvJGEWK5 +7M88BAF3QktmHzY09C+Jj9DPfPWVDqW/UQEiZyZrRG/7Ptg055MBveE/DcTQJrFPN0JFymiSXCr nNbfHdOJh030Js82CKOBcFn1YOn2L09sSZrPHMTpm90XB7QY4RPRPSm/gUFXviAeAP2O0ZcQGswo u7hZTIsv9ncK5ILiSEAYXSzT89rU7AvcjMNyj1cbr7bGxyhXH7VPn1IA+UDtXffhI+leCMtOK/4S +74U46OhMFKn08+T3QnTeWAEzpRsKZZeIvBnxaCYkNVvSozOmLV5/2rar86EQMdrveW8GohpgnHY tnnXBZsG/j9Rkjts59iOPmpT6t+5R71xQEqwJHswYW1lTaFQWl8ytDdsj2hmCoMvi2OgiXOuaank VjjrNNG2ExWWG7EtGHgeMvlgwQ+zAQNvGmkpZGE/O3DmZkxY3nIm7YbvMHtTES0H9oOC8gu6/ONB 6Oy8Iic4cmBaEQK2hKRAzeoOCphAif1VMqlfBw4DIyQE46xDmtzgbobm4KVzUOZRJ03u86I0GxTy q8WpOjy2/5Nbb/clFISzS6au9ytJyTUz5fNaVuKA6MRAJeemnLsfHsy3NiB3U98TcLq76VLOsbLT fMh5nlcT0NXVH8nY1rC3AOpnSY2Wb7BodSDiXZUfdkbs7Y9gDr98XBc5jp+4zoj7TNF0R9cJi458 ywr+XndehtrFXJ/VfeYNSjm3TSHUqsGbtlPeqqugEWq3nVUX4oE3pTf0Cjj7bI+A3KyZg3CNaVaD MPbKyHXrFQODBS0Z4cueqTJdWbi365iIq088axJQLl+bz2CsM+vWqEKqt7jq0QsIDzhFTlMT1wbo Fu68o/Cj1dKhtES/xO7894DJxnl1kkjMpIm7W+ytltKgL1zlUtDVhkz4nUI/NHjxIZhwFM06WeBY KvZxUMjs/5pbtHFnQUHq+Q1YZDnMuUctjyrS+egGmOJwgzbKA+NddremHjaN4bKTbJYj6iBBHjGF 2rX81wy3u+C8r4Av1PORhYQtuHZgEEpRTUnk6VbUI4aSBN1rYB/OuNSe5SwzDcLYOgu6eoZwkAOA 6fJCW9ij3ZS/GsShY2eaB4LV2xdcDqMNR/yPVr+Wh5+rYp1xYPYZNyUFC5zyfFrKUqSC9IcCG9Sd OQpMcz63YShl7MfEQE2R5uX9UOo1ckt7jJSM8F2SYwEqh7OVBn3fl+uDTimWDBMnHO8Pkj970rSf qcNMUwsx5iY9McsIAJ6Sj2R4wogQFU9v8JynbwJGmNKUX1GgJgQOPBUDP2m9cC5LqJY5v56oZ75c YreV4KnSCpG/ze7b8/Cud3kddBraxe++T2+AHoD7uOlyfsFp0e2GPJustCzfVH2GBz0EG9W1SJ8O uxyet4uOUKBIScDtV3oMwme4l+p7FHOOFbKL2bC9ZoFFGPDccWEgQO8bCWPhMn+B2KVDGmMdMDH2 2fDWThRYYxmQkpsPKpM9CEVzO4lDfqpPd2fcDXTsNCIF39pJNhH2s0G33qWUCxtOGpQ8xO4Mlm3R TA0Zz2XrRVBqDuB+SRgz11LshR1TQULWhZlLj/+ptP0i43xR1Y9qml/T1NZadhUErDuAi7dI9oN+ AtC3Z3jVacq7j6An9k9IAnd0ciowiEQr+6M8l0fMR2G+cCK/XK0XvBOsbr7SRxf+TLgP4jau2rjI QLXQGzi5gO6vj/VjFzuTtT4/tNgzI3jqrV4q0rMAnaOyGLeerhrC+eW7HAJqLGyweEAFJhiWY+Bp BOb9o2pUwgdvZeAgqNQU4z/X6x9O9Kgx/z8c2zoadvF8nUWys3tIc1KGjVN8bsyU2AxDCJKTJXAo yj+5KeGNJDlZcZRQ/m2sxFSwpHok9XkvXATPRJEuu2ANMZpvmr1lTfZOWzDSVatw2KdWqd8lt5VW xuhpCzWCKtSYZIlNqjuobldOqc+pAwOY89W0sAye0NBcDjvl1eD6QgDmXnAGFQ0LOMWCKojxPy/Z hanrQGw7Butr6ZH7zWvR8jqJ20xO289HB7uZJRWzYeYQEPsPIOhbRv+L2VA1iX0O4RPro/qr96xP y82gBFRFRANaA0iHpUMzMgln6/3pntB8o8sHCP6NlD96I51COHrrqgYgoXPKebwi5ekZAEom6oXS d2aD2VK/euG8idXqJ7cyvBCJJdlscFvh6EPkze0xZ9I6UIqdOMFxAYsijvJCtrsUEjF0sw/PpmsU Q7AFaFV8zLluS/6leXp1hRVP6boCDgFAI5MrrFha60citT4xT2yxl834A5o3SayJm1UhAD7Kl6dc V/iF00cDxkRdK7D3392d7qanpz9B4KlQGe5J1rrJwWSU4+SVUTuqI/B7ujrSDN290aOqQ9T1ocVS i6nmSbvgo9RfQBxXwyLt8MarwIETOJ7typVngmOxNKq50lx3vdCzF/O6zkJ6mrWzskrjr27lqkDi z/7cDYRDOZitSBoDHGTlCW+YAqo1Q+ab2AKhmBFwUPBy1HE1InK3tUUabSM4x0JSYSidLPlwnb/q tPa6Z7KZ/CVMLnDgAgCZtROHfFw3o5q1yfJi5PXj2Wau6YyJlhtQ6BVohd1owvEwMBl+ukEbo/HC EaC9XqWM5lm7lbyWT5HvHy/DYb2V23/YHo4Z2A8aSy12c9NliYk+ESa8DYEbFgjigwhwiqkzk9ep 9hjMjsbujF0j87hmYuEHs4MZzSLGDvHfqD7oGosnxRhKICgNMR/ykufQ8iyqkh9Rbp7urXodgEd5 fZf3ri2JeM73YhMzorCxY+hbrXCfljoF3WocSATe+GQWpHdxY2KT5259phPJ96LsYXv50xrpjQD2 BHgwN/GioU4/rL16AQ7bD+m2oau7uAauDf+HkvPWK7s4kSuU+R91M7wc2uXAUMCtsrXw3pUFWpU3 5m+7qD49Z+KBo0eq6TgUg6ITf32F7z1zSRiVPwyyt8yZrl9hwZEZiCfdPtWw1KX6via/unpEL5k= `protect end_protected	mit	925754b4d7806b0da5374954af1bb996	0.955203	1.808808	false	false	false	false
Yarr/Yarr-fw	rtl/spartan6/gn4124-core/spartan6/serdes_n_to_1_s2_diff.vhd	2	11,029	------------------------------------------------------------------------------ -- Copyright (c) 2009 Xilinx, Inc. -- This design is confidential and proprietary of Xilinx, All Rights Reserved. ------------------------------------------------------------------------------ -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: 1.0 -- \ \ Filename: serdes_n_to_1_s2_diff.vhd -- / / Date Last Modified: November 5 2009 -- /___/ /\ Date Created: August 1 2008 -- \ \ / \ -- \___\/\___\ -- --Device: Spartan 6 --Purpose: D-bit generic n:1 transmitter module -- Takes in n bits of data and serialises this to 1 bit -- data is transmitted LSB first -- Parallel input word -- DS, DS-1 ..... 1, 0 -- Serial output words -- Line0 : 0, ...... DS-(S+1) -- Line1 : 1, ...... DS-(S+2) -- Line(D-1) : . . -- Line0(D) : D-1, ...... DS -- Data inversion can be accomplished via the TX_SWAP_MASK -- parameter if required -- --Reference: -- --Revision History: -- Rev 1.0 - First created (nicks) ------------------------------------------------------------------------------ -- -- Disclaimer: -- -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to you -- by Xilinx, and to the maximum extent permitted by applicable law: -- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, -- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR -- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract -- or tort, including negligence, or under any other theory of liability) for any loss or damage -- of any kind or nature related to, arising under or in connection with these materials, -- including for any direct, or any indirect, special, incidental, or consequential loss -- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered -- as a result of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- Critical Applications: -- -- Xilinx products are not designed or intended to be fail-safe, or for use in any application -- requiring fail-safe performance, such as life-support or safety devices or systems, -- Class III medical devices, nuclear facilities, applications related to the deployment of airbags, -- or any other applications that could lead to death, personal injury, or severe property or -- environmental damage (individually and collectively, "Critical Applications"). Customer assumes -- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only -- to applicable laws and regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity serdes_n_to_1_s2_diff is generic ( S : integer := 2; -- Parameter to set the serdes factor 1..8 D : integer := 16) ; -- Set the number of inputs and outputs port ( txioclk : in std_logic; -- IO Clock network txserdesstrobe : in std_logic; -- Parallel data capture strobe reset : in std_logic; -- Reset gclk : in std_logic; -- Global clock datain : in std_logic_vector((DS)-1 downto 0); -- Data for output dataout_p : out std_logic_vector(D-1 downto 0); -- output dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output end serdes_n_to_1_s2_diff; architecture arch_serdes_n_to_1_s2_diff of serdes_n_to_1_s2_diff is signal cascade_di : std_logic_vector(D-1 downto 0); signal cascade_do : std_logic_vector(D-1 downto 0); signal cascade_ti : std_logic_vector(D-1 downto 0); signal cascade_to : std_logic_vector(D-1 downto 0); signal mdataina : std_logic_vector(D8 downto 0); signal mdatainb : std_logic_vector(D4 downto 0); signal tx_data_out : std_logic_vector(D-1 downto 0); constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0'); -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing. begin loop0 : for i in 0 to (D - 1) generate io_clk_out : obufds port map ( O => dataout_p(i), OB => dataout_n(i), I => tx_data_out(i)); loop1 : if (S > 4) generate -- Two oserdes are needed loop2 : for j in 0 to (S - 1) generate -- re-arrange data bits for transmission and invert lines as given by the mask -- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2 -- This can be avoided by doing the inversion (if necessary) in the user logic mdataina((8i)+j) <= datain((i)+(Dj)) xor TX_SWAP_MASK(i); end generate; oserdes_m : OSERDES2 generic map ( DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL DATA_RATE_OQ => "SDR", -- <SDR>, DDR DATA_RATE_OT => "SDR", -- <SDR>, DDR SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE OUTPUT_MODE => "DIFFERENTIAL") port map ( OQ => tx_data_out(i), OCE => '1', CLK0 => txioclk, CLK1 => '0', IOCE => txserdesstrobe, RST => reset, CLKDIV => gclk, D4 => mdataina((8i)+7), D3 => mdataina((8i)+6), D2 => mdataina((8i)+5), D1 => mdataina((8i)+4), TQ => open, T1 => '0', T2 => '0', T3 => '0', T4 => '0', TRAIN => '0', TCE => '1', SHIFTIN1 => '1', -- Dummy input in Master SHIFTIN2 => '1', -- Dummy input in Master SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave SHIFTOUT3 => open, -- Dummy output in Master SHIFTOUT4 => open) ; -- Dummy output in Master oserdes_s : OSERDES2 generic map( DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL DATA_RATE_OQ => "SDR", -- <SDR>, DDR DATA_RATE_OT => "SDR", -- <SDR>, DDR SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE OUTPUT_MODE => "DIFFERENTIAL") port map ( OQ => open, OCE => '1', CLK0 => txioclk, CLK1 => '0', IOCE => txserdesstrobe, RST => reset, CLKDIV => gclk, D4 => mdataina((8i)+3), D3 => mdataina((8i)+2), D2 => mdataina((8i)+1), D1 => mdataina((8i)+0), TQ => open, T1 => '0', T2 => '0', T3 => '0', T4 => '0', TRAIN => '0', TCE => '1', SHIFTIN1 => cascade_di(i), -- Cascade input D from Master SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master SHIFTIN3 => '1', -- Dummy input in Slave SHIFTIN4 => '1', -- Dummy input in Slave SHIFTOUT1 => open, -- Dummy output in Slave SHIFTOUT2 => open, -- Dummy output in Slave SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master end generate; loop3 : if (S < 5) generate -- Only one oserdes needed loop4 : for j in 0 to (S - 1) generate -- re-arrange data bits for transmission and invert lines as given by the mask -- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2 -- This can be avoided by doing the inversion (if necessary) in the user logic mdatainb((4i)+j) <= datain((i)+(Dj)) xor TX_SWAP_MASK(i); end generate; oserdes_m : OSERDES2 generic map ( DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL DATA_RATE_OQ => "SDR", -- <SDR>, DDR DATA_RATE_OT => "SDR") -- <SDR>, DDR -- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE -- OUTPUT_MODE => "DIFFERENTIAL") port map ( OQ => tx_data_out(i), OCE => '1', CLK0 => txioclk, CLK1 => '0', IOCE => txserdesstrobe, RST => reset, CLKDIV => gclk, D4 => mdatainb((4i)+3), D3 => mdatainb((4i)+2), D2 => mdatainb((4i)+1), D1 => mdatainb((4*i)+0), TQ => open, T1 => '0', T2 => '0', T3 => '0', T4 => '0', TRAIN => '0', TCE => '1', SHIFTIN1 => '1', -- No cascades needed SHIFTIN2 => '1', -- No cascades needed SHIFTIN3 => '1', -- No cascades needed SHIFTIN4 => '1', -- No cascades needed SHIFTOUT1 => open, -- No cascades needed SHIFTOUT2 => open, -- No cascades needed SHIFTOUT3 => open, -- No cascades needed SHIFTOUT4 => open) ; -- No cascades needed end generate; end generate; end arch_serdes_n_to_1_s2_diff;	gpl-3.0	997e2b73fec334613bedbf469f5ccdcb	0.501677	4.129165	false	false	false	false
cwilkens/ecen4024-microphone-array	microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/buff.vhd	2	15,490	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RAdCEmtmW3yuIMLzvz5lbCamyqg5eINaQFbMjHs+ixucClDNKHKZzetFoWPXqsSyg1jlYZEAc1yh WPQsgz5p2Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eMzZL9YvBSQiI/IJUlxzCjmET3lsc5Qww5knUMp8yVXv+14AYBTJ8VbvxEupk6a7amfSSl5osBgI oMIKR+nnRX4x7MaI99LPUTJ1acCkJJ58tVzvFXPc2BTfBYmbIOFrwB8ARMQGFHsbN/BfeGGOqVYq daxMyeEYTXuqp8UqwRM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block NyxVJqhB1xiGWHp8z67hmvLSGB7TG0isuFrjbH3Dt6g9lUWGR50FJRltA+X5J8MN+heFHzCrbe9o jWMAYY7JNTj15N7aCrOuAX2FRdOC67pxVjAwaNlAAmt1mKyaLVKXb2O9d7H292PbKLmrgh6OjA3n LZPZJfAYljNm1Uzd/NTEHg5j95pauHX+yML++twIW7hK37YpmyTr0CTfferVJ3B/NADkGho3jFEy 2CU6lRVVwHFusDsMrUFRFdQL5thVgOdn3bdwSpXCweBiZPOS/yMVscInL0mNEaGkGRuDvbxxvk46 ggPPV2ptT+x6zmcq3Ga34TKQSQF4sm6iPCBAPg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block sOBRhV6YD4wF2l9Bs97TjXCjdwn/NsNgrNcMi+HMOuk3u1dGY3s9G1VjbZiPbgO52yAfxofelLJy 9vU8n1w/Bb47yIl01KyFtMK7AWE7nicbcZceNkaT+EUd+QzDHe2ScDgBXwHFNa7mTyepSfLDZ/HU Y/XUQl9PxiqXQp47W70= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block fkD9+1OUmvbMGamswqYcf2bvNrIxKAtKBH0Nd9npDGvA0JiUOo3roa/1TAi9aumWgCzYFpe2nnAV beK9UvAnLu+wpXeNZ6POTh8zH4+lAZwhMV3O83Q94TFkF+RgM7pUcaQ8KaacbkfQzMZsktX/jKRm N57bRawyg2QKWXbIhhvIQ/drXMo6w4uKxq/QqmWRIcNAVw1vYTtYKp2U2bxhtEmbihowbI3jp/qD h4/Xza6Y+9/m9S8ZNhx7lvgr0+Dq25cVIvc8qWOShak70IUujuAe9yJtnpyXaJ5A7FIgB1Q0k6dX x13rabSRDtMIwXXbr+RJ6N1T4GHt7X7U+BdkVw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9728) `protect data_block EpRbq4oeZ+2IEePxifxZHobCEYasYGHTUDoSGiFUqhyab0NE+9k6zj7pV+NeBFhIYuz1LDNPwgcd k8g/LvyeireePCX70Xl1Q7wCGRmUcQ6TvvDimvFi1jjiKRTcKiUBF2rD9adYPh/n+j5Acu7xFhNo LqVWDfjyICbmmfMr9EmMkHizVoARyik+Dm3lzLe3BFFd3v7LWYUWF6IXCbIYhPaNAwiH48ihZAGz X9bwjRSIL5PV14EO1UVsGf9fViDg+tmsPXj50w02vdn8LAx0l0Qm2JaWqIR/Oz1W7RhX95tmgKij lLuw3pDZ/EMqcj/4oId+NpwDs0E+Xosh/O9H6t585RC3u/72Z3ZdC9AOnmI6P+PqYIe2BgRXahl1 xN27wDoa5uZSx5tFoSs+ZkDJ1TsW+GvKRsd1YM6+7HZMbvPY1sqNUGAEuhabo1f8IOR+ky8vGBKr rah216j9Ug/aSP5uo9EGCuRuC2faprpPHPidAgtp+zjVmqvf2nYoXrVYfhJ/6xcApFQF9cKr2V7J n+K0VRN3MT9vuSXBFXed7tQKE8HyFXu2v7x+RXmYBBv0swmgksT/C5A5UmjtzFkwRURYU3QUaYSh A/lzmiFCR89J5UpAbZzkONY0CDd2phefxWLK92uCPQF1ZMF9M5fQl40uBlPkHBtkjetXdpwqvJzs DowwDJ2hdH4xQgm/G5VnLS46wol1sz6ACKnKhuwJqDMVi/etZnEKAfqWXFLA877FgZfcGt/3nliS PYQR5/hUuAAZgSPszH64L+sp/7yPEneJHUKl09coEmMCjz0vf0ErfK/fKwhWkfyTafFqW/PKsZ0k /yNo4mQwY2EpfbgN+JSBXimLI31nVKY3HrqVkGVXY5YMnxUClPs5UWi4bHrmes1O0YDkxIgIR8+k YJoLPgsm9D5gNLuYFBkQghLYjTbpdw9lrfUWtUZtz4SF/wh2Y2w24H59rvBHv78vL0BiM1QVbZ6Y ffkMRcMpHojizVSYX4qEfZYRGae1n5Wz9opklZ5lB7vzpQiADHZN3sBL8iplyJWCEeFi6Zu84f3u rHUZ7AxVI80JjqiF0y8zszEwGnC1J1Cc7qFXxGqeQ+7fGO5gBRx0nutaFqTiXao3KdRHyc9rBsf+ fKsWqYdVkGuzdMW1JvPtprAEk7Ykij9pIApoptP8nE5cNQ+kUJziZNGkUG3Z2pPmrJhDGLkxBPAv N8OlIZoVCtKvrXYcXiKiD0Uz279+qH9dM4eQTBzDK0QFoCR+1/ah9EQKi/V1V1QECLzwvTareMmR l+KDtwNt3Zaq85RaS5DxILrHW0hmCHmnJD56WAHGJwoZecPr2RD8NI4l/QT0+kedRIA7RmCUOz/z ousCUxtgaMf494G4vQdfk0vF+HylQdF5TasgEEck5uZ9MbGiGvKBXS6vabjYrT7lLTNimap70KXy KJr8F4heNadVrhKQ7K9x3vlDtQ627JD+rFgmcuw3QmXz9yFztFpdbPuEgvboXhRBOc9YH09D2C1O ocfk7KBSnT2TSGKVjQbO5WCaTSCeHzmVDj0xfZNQ2XXTlq00hXWi1kkjjYZ0YzeXVwH/STFUoGKm scOl9klIx3qUdbAChp2TPOA+KAQfRebI34t5RYetlUZl3023tAbx9DssImy/L3uAztZoLb21syns +JOG4g3IsVnvU1IowesxDUF5WMvGAdYTJ4ljN3jnpiiiPrhS80/h8WgZ6tlEB7u7d3OEOvf3CfxQ +xV4WDakcECN6ZC0ZwhC/b1b/TSF41Mh5HseSdMhTY5Iw2wmbPf8SY0xFsNnSdYoWaqmkzHzQt4D L3kS6EFQBBPWpvPRtoSX+PVxrYdkJytPutxE3HV0w8nDiF8KsJgeX3Dvjb/ow4Ler6oK8zDil7Xa +DSgRqUFTinNlSl6GvRDbK+RnsFchoUWf0WP2j/Qg2iV60FH/RDus+SgsW5kXX0lDnDIHw37TZxq F7UEvcBAUeZ6ZhgUITM/GPRc/heLMoYp5Jae2D1VUXgSzauYgpLk/5tzshq716+3KnDK/bD4JtF5 AYciAAPZoQyiujRt3Y7nIZHes/AcnxCXxj9tFhQy6YhKJsq6SqvkoHGNG6qNsUy9J+UbW6p+Ykwl mBv0Lzp8IetURboLAWWu5oP4SiR/kpeQuHNbRY9LOEfQNuiL49owxaJMet48lBkwVQ23zwQ95u7x 5TNgAq6PCDRvUi8EkPLLZtaUJuICm2woiVheq2biL2b0bR/eUbHmLi6oJDQcSSpkAWh9wGxQGkqK ECOI0XA8C64QwOHgMrziAh9LOxA7O0H7sQ7WMQAoi93eus0GdWn6KojqzwKFG+QT2sBZBcE/Tpop 259dwp/BLqb9N0QGOVRMnHiL+amtd1+dmSsA0nEAYHG+YOOfvhHf0vprBl1TuHdkWu8Tuu1R7S9p DlGVWLEZeTOAz4AJ2PiI/YQ8zudRRiig5n9Dkls2FLXfCajYd5KswNTqIOFQHgCO9wkj7NTTf1XE 79u/DXCdX9NGjbI4A1zkhMFBfV9G4FB/S/QGLcWhut88gACYm9xU1B4+FavbZmiLERud6r+kpwdF 5lMkyc8wBgNFd/M53IuUXo/ilero73vDrTJHHPGpVfYtEY9xUmnIKD+W85R2BLbBSK0hDGMBsw0b l+kLb0uTXXAB4t9jAZjE7fIksDvIB5MWKHNNdeaQriEHo5dX2NyOPqJA3vvdplxNxWwwM5RH++tk ioztz2fJrjrZoe5/p4y6pvRbsFR9k5tf3UCC6y1qAkp/4FUPB5h5ZcvcmwWugdECbyqn1PtNhGVr p/pXm7DVilWwptNjx6Fu5L/RpfZUM6jK7RkAfUhhIHkoTpcgGSSCNGE25uUAbeeJzV+Adf5R+6K6 mtqdUHY/pyV5XNQHXTKq/TX4KtNG9LAZLNPeePgz6L5xv2JURbBZN2CR3C6DJXnncbZ4KgPKs74a LIiU8yFTYRjTz7hq6OlmeXrirKOuF9LIbNEBQP8YeOrYlBwiV6etXz6UrgaYgkaaNumc8DXmcSX1 wApCc3doyiJcWpqQtKAL0WkYdscgh/x5BwuW3e7IEMHXqg4reSClYRMBY6inSV1ySDEv2/wqVwqM g/tYVzvv6a+XzxwSK54fFzuf5Z5MyfjOAkDI9wNLkU3gxg+8+4kDH8kg5/B5nZfzi+nl+VcLVv9R mh7Cn3uT9Q4y08g8nO+wPytG2or7OpZBui7pBjAsFpLSe3Tkb+3ezdYfjLf8ABxIGYoXJeMsXZcY 6YOuEMDE4r3UyeDzoIYssc3SVO633LV6LxeVSDtsbtgFDQ6tkw2bvZH3igyKuzB/XqFKUmGxIxOk hShm1Xqw8I9BYpKvEZWqg2kXtDtNYQ4rTehJeg2AaH62lKNfXZZUeCPfcZnH//KBnXKZAcIUHWNH IWvzHzMoUnDAc1fpITLYS/voSyzqALGnCScAAlD2OGwx/XxlarSd/RDHMbEHEU4J6lZLpt0xIvLT YiPrSoyK1Xe5rCoMpZRNltjGKstuXFSLWUluymyhlcVJY547AmRD86kI0B6NDVMnHKFLouGA/qKa KJlQGw1CqM75xAbqQe1+5t6KH5lu3ZSCN0mo470VL0MtNCpdhm1gwH1uHEuQLv1qZwSMIwFTXgr+ /orj4BthWosucMe2oo7g3hoDdrJ6fWbQ8XW2ATtgzofUG/nhlRWObSWiQh3GTccO3MYlJheY6IsP 4O0NjHwzEfetp7OCn5S0e8Pwrf6vVNH5E2dfMi2cNy3iqN6faGicWYlZnayghWKk8fwUDnnXpNH+ FHTCW8zuSq6spQ6e5sFlV9W7lkGP0SRPHOub7SHvDJDy+ousS3mywtbhxynINMXTN9BoKA0if6DX hdtkmFaUQofRqQHhy0uPhcoG1iPMM8sA+WwppJRJX4gWx0UwXHZwwaR5GGRNBB8NDtqNojQSTnuK u5d30b/CykPRhO/eTncCns6qYjRSpAxVhDsTCEEAxWOtHEpTdOprP8XE3Nt0OtLrZeyoDgtkQmV2 Rr0gDDG5FS8qYJ81Z+FfayAufMMjJvYGmKmI/Qbvn7ID4PcEIHlvP9w9M2kzzlsJkuiSEnq2TIBr 32DU4L13wTai1b9ZBDAFk/zLwgx11q00lfbcNHd0aQbqTSF1YdbZjiQNzF2Yu3TmIrksi4WyqnV7 vtP8rAIZzomjS9wsLxX3/6BWD0ntfJFt3PzHdzUDaY0yRlZJ0zo7GHVf27wFizm9FioLHmC4Gj8R AVAqi6bci9hpi1ovSytNgUvqnvxQBFs6VWa3UaAApoxHP0H5RyK0FNaoBo9hH1Aaqips9MTCaW4s OE8aJA/bmeUdua0ertIGFmcwZJPoBjiVCXntnvU5nHnwfp4gaDN+pT6U76bVXplPcDicS7VdnZaw iujva29NYAHk21ShCHuX2mDVTcIE8FJxfjDMIvrea9a2ic9GYLsWzLo+kH8XEPAkBn4Ufhjlnfx6 mKIsdW1qazhHu/hPlF+XOL/KEHRHTBciQDrdYhDl8aKFSopxr+JollziZUcooSGam7WtdAnCLTjx WT20y0nepZD2OLeE8Nqnq/NaGwVWqH1yPXXirVxGhON1sSkpGsz2QCnl0IkTe2c7THpH6N/5vFxr oggJFmqYzwB/RFfPXPni0fjPBnodV6J0XnR5lUItOd0ez2pRVGc1y80YocvbpNGhKLhiYKJdcOOJ Rk620MFdZHynWcsGitg7TNMSrCMNyzFIZ8SP2CdTESk6VpsPnKaE2p4RWfBWwATn/1gQLGc8KAmZ oD7MFNc1S2C+/PZw3ZQ3V7soDSb1v4DhTGqBMihkamDqFRaaG/p414nVgLdagLpT2fUkfFvZs5rP 6e9IRjBbRgQxJGrKgvYZAZIzEfnBIRJ4cpSTdCdq6MXcCe0j4Qc7yJW40IEjOGuAatdbk5nDSz32 8PBZen2YIRiH/s89xkibpcK5bftO2WWK0l5fBaqMcsKqDVIOG4DtINHx+cuJuxfShKqETVBgQm2V uhe6l9lAt1NcnW9rtOuU9kuTAe7xdnejdH6FJfcSUa3SiANzmLmqBied7veoQ/xESAjTbK3ckz4K tr623VBDHwxVQXfgrT1bFJMBJ73f6dIuQGE4Se+Vic4qTD1kPbODp57CZQwU0bkbFim37e/M2ji1 /kKoSwEZmjbbJELd3uEGYVA1Xh+UDaiDFSnD3aO8Jw4EMBJWA96KG5et2Lg8pbNoBzjEmet+IgUZ N9PaV8GKVjYMBYh1Dbx/Gjgax/LW1I8mmGdUrKe7/RvVyGBEB5Itk1gdl+4y0yzYCYjp9kYLi0DO Iv/pkd0BsbqYYrUYn4WDG6Jul9I+NgS0xC+ebo2HN8geI/Qi6ZdsD7jHZjTnDZW4Fbwmm2FfHYSt RhBL0VII1O3U3DMU1VDqAaKvQdU9Uo//RQy3nnmxToIxUe4bkK29za3Pl0ytbzxTiYboeG2yZvak MwGhQ3beJf2ppyzv7lh89BWwQmqB8jXE1cfSQO8wUqHFatIMawv7HJZ+P4tsYp/oP6cBeXqrWWb5 f6mMAhbS+gas/Lg0OuKSi+BrsXevQeK4HdT2Zl/iHakQoFUO1BrvKcRzeAXEgm7DPrubM6HKK3tT 2OyHiwcYUFtyS/8mTHMrcXKuM3aJDyfZYmnd29+u3I3w6mi1Ptn8pI0T/SIm1U8u8ImUCTpZyn/4 a/lZDRWU57Wugv+v6i6ExPe8ucQcak/h1IFOepZnwM++DXOZ0jr3NvTf4aLluWxssA5itoM8CuN2 4iDx6sOt2CW79ex/tf+SxS39w8mIozwgaXHJnD7PNL8eiUTXo6t1Lf3hiov6m5YTnlfPJf3/utCI 84wBql+1hoS+0nXtX8xm13KGDXk3Aob+5DwNR6VaXaKhx4Rmtj58vOKJhTsSw8qYzmcr/zpgae6B YVhJOwTW/hlCGA0R3lNChLVUMb8kjseGV7NawlwszwYoR3YcaO7PwgV1LpPK3PQCVsdprjt/JBjN XmFWUsbn/7lWvJ5GB5rJXbFAo9dcQeEPVW0o0CVwTgIRs5j2Nifh7eJcx/rNGzGNRwPQ7dliakI4 QhRGXbuM7Abo37g/S8y1Y/rnsM1hHl6rSKBbhxvm5GPk4+p1+leLqoCs+fCeZlQ6RHnUmYXF8x6D pCGPZb2RFYcQobUPqdcNkAnRcTpgPHb+XUHW6e9PuUOrcBkiJH2vmUj5NB2l6V7xVV8wca4lW7nG 7hEsxUbwSkSwkWhcHar+nZHGdYfgW6gBeRnaky4HukqW+ZWTG1Af2KiML8U09SQadSA9Ho/3cbC1 vFZ6bCQY/MBaubkLFgG/20fqCWArXJzL/VC+vl6UcAtqYO0B0jVKmlthk/C7R58Et3fYb+8XjJW9 MA+kjynG0qQLs1qBFrcAYu3e7nFWJVUzE9bveTvaol6Pqy2alIeZPcetahKchwUa7obnGp8no/L0 EuehbZ/CAmeQgKpOTVJo5e8qhPPuKk4WfQvhy/11ySSpBN6NHQHEbCJxBc6st7tcvtf5paQaH8WI tdPI9d6xsREqUJVs2LVVn3O4vzmVhQWYh6Nr6A2tId2mfqqg/V9hKZpq0qxiBw8ydQuisv7mj6ND BnJ1Or79DwNW2vquTOqePgP56aO0im2XgQeVsIWmSHVYBYo/WwJd2Krp0Y+f9YvYkFpVgiyfN0ml pn82Q78t1c4Kt1HHj22QbtrUKEAjmszTaO5wy5wSpJ+Zo2yp3h6GoOzmAVeyOWl6PrXb5unlBKdM nUFqGcR4Hfd+3DOjwRjAqzDzCjuRObGe+O+7fJAYgaawpL9wHrp9Ql4/jDFLj1vdCF5D7KXtST/7 /KwqfYdVx2TpOaBgSGdSKYXbmhL9vMNanU/7XmcrA1ajhibdm0Oozjva6eVks9yTZagZXKRUJWDP uQIEh+y1wzFbqlbyAuBM/0It8rl1/g93YhZbHY4MXJAb3VnQ6AsnVFDhmYo7pD/wv1OdbQGXOALB ySsO3KQLhe07A0wQDqGIHLlu8WLzyyAOJHBUi1SZBEN0JgYrvmJDhkPpmfkHstOJgmBjHe7nMAM6 jC0ZduWT0PHVOF7j557zN+xkBb1dmU/98k2138a/hjol6KHd2czNZhfSOI9lMmhCMPLFcV/tRiY6 OJLm2euseWf06PcCeprfTDPqYUOqPQG/NrJDZSznaCGUkN6r1p/d+FuFPjml+guoFsvCq0dKpOTS 7IrVD66IOu75tiagyRT1aWUT/fjbFajqyru/s+E1/n+T59NtgaadLgO0TGWKPQ3ck1TVS0Ei2JZ9 naW3fwIXsryNaynnh7vSNlkdzwUqSp1dzA7+UDI8qblxvfUPmLWRS/qTfp8bioxvJR0CKzx+1Jt5 /131yKXP4Cob2/UrqVr66pDel6lGkiKN4wh9A9Z2bTxhuMQZ+K7Qpt3bHa+hbCu1AmA1o8p9vZxw M0kdHUl2chlMZ4Xo1nduvxaFXpTIVPYSrEhxz6n8SdfbnghuHcnuQGhjazOUj2dzFSUXvw66emuy K88p9yh+vhrHoDdus3noHg+9h9onwjMDY/I69EkIuYOG+evFlkpswcIiRYbCob0pTWIekmf4Seww V92cH3xulC3RwgqH6eWFi7hYhBB8R5/lRUPiqhLS1ReqN0iGUrV3pENhwoBK5X1pDYSfL9XVphsH i/9yxcRQZKBx8VHRRltbS1CZoH+2mhiTu0rNO+lQ4eBUlUaGXJVI/L+hmYmAbTg+DnyYJmgSU5l5 lDRbFc8zcrJn9qcGbh9NCZ05mPaD9KTaWlSvqtCveB6LKcpwknGtdjKMqCI6SclqPw0ilKmoF3ww q/+PyuUL5cBpjp/ShKO575bzxOSeFtLXkjFyOlEm+5/MTlb2GhtAkWnxJW/hoD/W2P8YQtlEWfka c/cOZtS8IlkFknh6vhAcWTYwz2a0DslGkI3uQKfqF64h+faLOO8FEakTAGCF49gGNAdKMSpz0Hs5 s5ugCCyjwfgNViWeOcoXT+JwPm5spPEpqBSApZPeFqVWr3av+BYOJ0Zpy2GHCoZtMFYjMc/oAtV5 Y5t1FhR4trv8vqw8kGj/Qzg03HO4X5iJwjbqDVxpj9D3zKt7M5G+f0x3a2dqCgAR5cVwzp9LGXW2 KaIlwOuwrqDRY/FvK5nrFWzvfhtYQ7tXdg542UdAADYotJD2GRshQUJ2xy9Kmh4HIlPq2guksB8g b7jxrbkhcHLKxjXbsRXAnYZ0wTkghRU9QYyECp/nS9wR3z9UcUzqEX3/BDJ5LnOUgVEL+AaFR0DC ig1Kc1E+Ah+NkQoksKwCeQZ9+1o9FFnOEhZ4o0jM1QDlkOUZ9sUHF9ISDg5LO7zyjXM9Cbji6K+F QS5+evOY6Jqpj2nD4ZWM0ex6yP1vbbIekoJLIw7gvKWTUN8cOiF5QRx7gqjekiJ2D1Nln+sAmjKK YIad/hfKZZr2BwjSTciOHxEE/FZFkuS5rEgT1SUihD0cRSJ+mioEuKmc8JNpJUFdOARsdmZqNpR7 qa9F2HcUl0JaPdQmo6VQ6bnl/u95E2t9+NQ2ZamKUTCTH2ksgcbLHx8W6923vZFWdm2dXWokyS8s afcC7hcrXZ732r+pQVBfv+8nu2TeuM6hNr514Nbt8qt7jJpWXBJTAEMxCtwGfqlgAJgnO+a0xIUg qr6z55nzqUSpA1e+beEhkbaYUIf68PTbhRrFpF2t3WkKBDgGn1CB6UkS02EDVKElBbxRTSG/9cLL xVTgFz1zg2sJ0Q4uEThd7hkZNNzZtRLby1WKhAmXz7qT//2B1yztyOPEC8Uk60NutjTX43SwtFoe 3JDQd9ZwNEFSn4KmomOmX6vCVRZ7ZranNQW09LGXLCl4QWD9N6O2tukMUieRBvXCrkdOZ0HJeQs/ WpkHJlh0bKCtzWOKPj8B9oslh98fGiqThSQzZPROcq3EoE9QBmx9y+ISgJ+15gAfTfpKAb+BL7d+ A6mCszpqeB3xOeDguRXikb0aMNg8tJLWgPjmEQnjK+7ojvRwecz2ljK5qRAuVQKnczkUDvaIJs9A wUPzmkuw9pj9jFMNWFCCduJa78fA//hQSZDMOUB58dmNxKSJvDqe6CcRtm5XJIyIzatsXno6IeBP tEwBzVI3j34rie+9LrLcGWJk4Vdr+R8dKXuZAM3KW5C3wI5w/oKeue0cDAxTkrY3ss64LTjKjhvD IDFx0ZoCLippHtD+jeXfgJ9V4GU1ZaguFmXxXvmbAwJDYNtkHn9n2PhMx/hzcDihCmUCrqvirB21 MMQX16aS/qWZkDrqqAm7HXrPtd6FX/X3hEEMiq9CDVyKdqLYIp7rQanMqZg7CpW3+BHTaXbWCQ9Y +nCkOl6rexsO8x2N7rzyWa/pOpHLODxXHSCsuMOf8/6bBtkdTpM7mWDqQqud5wL2pKmt5LjhLvC7 asB+LSipLaYeUFEuZFwICRML8R5MsTUvL0KaWRZPNqXgiNalG/rm/iaLB/arjczkgM7kDbf6yY5j Ewi+jhjDeMJTg69m4c+MypDLpONp83FwWkwChWuiWpxRdnDtadr4IXSvRcfHdVEP5fvCu1/1Q6Nr 84ld1fns1BsQFdvNKXqaFE0fs8sDlHas5O5N+hV/flSb49UvVmcYACFrToA9Wus4YGkHXiz31VHe yyIP6yryswb4eByrdYVa+FzIFP3Nmu18HA9ceORuFPd9M/2VYk3gDYSQmulstG/ud77mPxEEHaLE wYr6g0LB8WS4jG/ZMSTtNGVq2i6+WTfBqE0kFrhQEkbnbKhR2FJRxLtOAxaY3UwNNxU6sC1iF/qv oHfh5fQjJMY9fhLakOlvH1sp90jrWXcBorE05+X3dk78K4FDhGVYMa1J0PCqdUoMcG6WNHidSgTN 1ZRXk3nBUp4AV57bK62g/5JAlsiiIGbYctiwqos2oOUnEOUgzmqIrgEMNXuIWdBFIVJLHNV/qoRR QmduF7O4IoJ4RpxuILIqqjE+uZKc8pvJCIRKtYyLF2EpkjijH8aRRbK19CgEF6qlOQAssG2GLvsy ValOSssOJZ3b0GSFvX9L0l78lplcGpvFAurCJakaTD1q+nljqgATx6kt4q6N2ywaNb8W8ARSxdXE dLBBCyM0LEMqpvdsdICCHULWbAKes8wvu4jRmxzt+oHWi49CQnIzu249AjaH+CbD5OtGnIhD8iyB 4TuHD4NutmmC+AyUo0aliHajozFAN8TW7b6Eq/S3arXMYiDIlqjmsrgmm0/ZE9lNy0vgUzZQCR1h 93M2sHYfjmS/roAz/Xtj064DvfcuN44FA0/KUPxQZBSa69MSh7lmNhUzI9GyMwwik/EfsWH+ThPk XxOpnfHEzYJxwXKbJHVkBq/ek3rLXnRloCXcHGHPr1Ko52+huSMSev/E/H5vdLKiANE4m/pKDG71 GSYt2uXaVfMhpmvQQMA1XkLYtutxzw/Bfl2118IkIeJ8jR4DvtlNnb9SG0aktd6z//4qSzRaMQOS 3YaaboWAi3u3AZBmvWPzEOYujQu2MTi+iH2ghX81/x6ntx1Nvq0kKmoH1T/awiLbV2/FuaumrMEk vrM6j5Yc5y8oV14MG4L+LBUJ5oNP6Rc0Mx4BiHuegAfXBSzJZcoEUNc+EauofJQfcnegbLVn51ov PB4sSTsIvbhD+KDB+cgzsuwlo3pynHCKtG/v6YEveDG9udXFfG5Ox3ZpAekOo2F5IkwN5J9rJOVw tHsSBufXVHkV8ywzihRnMgE8B5y1IkwsCr3faHyuQB0yF/lnVUSK9YKacolqhDJz9iOo6+70dcEn xqSOLNOG1lxJdpRcx2UqgQpS9yvwrGsVbIA2EKljmSCFvCkBihUmL2GcQ/EH3NMc/Jq5HoaUbVhQ BaYNyNFTxQh46dPg7iDpOWxSfB4uT8i53HFYY52GCP6Cae8fPTyxd1Zwe6fApouFxJxhrpe/oOYe K7HNiAm94NGJZVCSrby60ePLxl4dR+IwKQFRYBs6t/rqSEg8Uk/7b/nV7ktJkl6Bm5k6SkxhlLNp wSAI2IQnZsZ9UMEcUMP0hOBlkhxZy7O4WT/ZlLo/a7PFwTXqBNOOiK7ya2AoyWJSgXjjOF0dW6Gc EnCBGMPzubSCc/p3XKnsBmjz8FCF0AZiB7IPRucc9jKRSBgxnqYkbutVH7L1jgW/MALcjnBpRRqe sqQRSv39GdT6xtXFxqy4uY4BrXjVnTlcxSz89uBKcjEx/cNXhn/IlaQKYt0JwVnwj2DObgsdgnqA ZqLBBMlAYj1VHwnbMCP4hZYC5zGpqMgOagRTQTxXwdGVfaUzVF9Ef5eaXUpvIukTJ8G2sZJy+JUL R1/uINLnr067jsr88Vih8ZU981X4iU1ldx8ZiulLDPcbWzZvNjL1w4tOsorA0c/foSeFlxa0aFNY mIW99yk6234dxjhlKmTzaikMjzwQ8vDzxJy+iwFEKv/MjBepXIikZVXs94mfCEZcSKcE+AB3ckw7 qeFUupQPCv4bkj7KW7aqke0HyiZacGusFYhF79AqL61AgLEww86142TJZBlPWecxfVa7J2OTdWag YYZJ/ahLc7NBe538HjJvO5CHYnCDUHs8/ji9XfUTQBX0Qg7LXo3Eb5pJ3eSG9Oho7HB0mO25FCgL jupl1RQm4q5dEjmTN4j+SRXC8BNNTcr6gDzikvSRDVJA67W9xRf/4TwuZxxx0l7Mh6ccY+BbNpe9 gcLIkejcGrD/cXk3CGUg2DyuH3rFIsmQ3mwRLuJFerEhteGOvmKyAu/iabMbMSEOTYqDY82Np8Vg AtmM5tO9LGVqD0WgwEqvlsmSemSSWjNRH1CJMi/iZ3KnXBQk3RUvs12zXvG0Dx2Q70auOMm5afsM F/BBuS7qnWE3IjvihnBt0PG9WHej2lYEFNkJIHs+da7lvWAGjaRU70s4KstywyZgpVuLp6CnjorJ cQ8leqsMoaRi+aKtG0IHJKnmHVMRQwugwrKuSFrWxEBgYcqPpAPfY2sH3QHhlI2D1be4/fr79g6x zmXc3Jvm5lALTcXmj/BPwYk4b510dQYzrexsxgDTeK4Yh/6RYPtWE0G1QASyGmftq3W6cyg3HTfl IgO9bmiGpr64WYQAL7+QVZtAv1WN4sDL42Zukc+l91npRyL3k7ixkNrR5vxcmS2RkxEEr0UfjBNY 5gwsebb2vYBMlctr0MS82+JL48Nhmc7DXYuXyApTF1+81JRLKQ9vpnjESc368hKhBAJy+CR8sif0 gY0rLLAUnFda79PsKX2/zbPJmjLC8q+YL+GQuJ0oAOsvpiotEmbHzLqLe37jQDh5q80pErY3gOkb 0OGSqeU0IK51r7dpNEREheWz2bUanwofC5qn4YOXf8/JU2CKiPIED+omJzppGeyi0KWQVWwG6Lbp zZo8mYiwenAhy1MWmfC1Jku/shWQ1Rh+0viyVNOHhmo/mUYyYbAQqFY9isM7PfoUYkfYo5Opnxsd csjc4hYehHK2eV7G19P/vXAmCdZC++mzDJnmHnasEWmBu2a+DKc7cJDKEspiBIWb3kDzTaxSzHc3 h7X0yvjU6DleI2UVSPArTUYGLNg/v35uwQuUKlW08lZcgIffZYIAxW1njnTgTml4+sy3Ygpd0POx 9XjMHAo1nEMFc3CnyhO8F++xIXD+BuQhvJHNOQ0PVk3+XV/Y5iElUnLZ4xxfGDAikkhIhgOUYekv VKb2iEVdLGQko7gU7kRyl+Ni340laPD0KzVIGBB3/ltegjxNF3QryWAAMZ3fuv/l2EamNUdT+Sxx iCj9EVWun97yIdo4QO9LTWXIUFDwGNP4mbsA48rAkRMPIEwvirBkNgp6cqEn9sd8X372XyOThtJL XkMuW7Hipzv5xRYNCm7l9+2ILGGTjTLskYgMUmsPDM8mmzbK8ZXYRfpkEtMCsDpYrZM9taDDVyPM Y9AZjHVHg49yMmYKvDDNETwaCke41eWNSzRhTk3Hcwo/qPgwoyI= `protect end_protected	mit	3af215ff25fc55be7d520547f3a4fae2	0.934538	1.862003	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_queue.vhd	1	37,514	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; --use axi_sg_v4_1.axi_sg_afifo_autord.all; library proc_common_v4_0; use proc_common_v4_0.sync_fifo_fg; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_queue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Stream Data width C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_INCLUDE_MM2S : integer range 0 to 1 := 0; C_INCLUDE_S2MM : integer range 0 to 1 := 0; C_ENABLE_CDMA : integer range 0 to 1 := 0; C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; C_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_primary_aclk : in std_logic ; m_axi_sg_aresetn : in std_logic ; -- p_reset_n : in std_logic ; ch2_sg_idle : in std_logic ; -- Channel Control -- desc1_flush : in std_logic ; -- ch1_cntrl_strm_stop : in std_logic ; desc2_flush : in std_logic ; -- ftch1_active : in std_logic ; -- ftch2_active : in std_logic ; -- ftch1_queue_empty : out std_logic ; -- ftch2_queue_empty : out std_logic ; -- ftch1_queue_full : out std_logic ; -- ftch2_queue_full : out std_logic ; -- ftch1_pause : out std_logic ; -- ftch2_pause : out std_logic ; -- -- writing_nxtdesc_in : in std_logic ; -- writing1_curdesc_out : out std_logic ; -- writing2_curdesc_out : out std_logic ; -- -- -- DataMover Command -- ftch_cmnd_wr : in std_logic ; -- ftch_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- MM2S Stream In from DataMover -- m_axis_mm2s_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_mm2s_tlast : in std_logic ; -- m_axis_mm2s_tvalid : in std_logic ; -- sof_ftch_desc : in std_logic ; m_axis1_mm2s_tready : out std_logic ; -- m_axis2_mm2s_tready : out std_logic ; -- -- data_concat : in std_logic_vector -- (95 downto 0) ; -- data_concat_mcdma : in std_logic_vector -- (63 downto 0) ; -- data_concat_tlast : in std_logic ; -- next_bd : in std_logic_vector (31 downto 0); data_concat_valid : in std_logic ; -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ftch_aclk : in std_logic ; -- m_axis_ftch1_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ftch1_tvalid : out std_logic ; -- m_axis_ftch1_tready : in std_logic ; -- m_axis_ftch1_tlast : out std_logic ; -- m_axis_ftch1_tdata_new : out std_logic_vector -- (96+31C_ENABLE_CDMA downto 0); -- m_axis_ftch1_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ftch1_tvalid_new : out std_logic ; -- m_axis_ftch1_desc_available : out std_logic ; m_axis_ftch2_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ftch2_tvalid : out std_logic ; -- m_axis_ftch2_tdata_new : out std_logic_vector -- (96+31C_ENABLE_CDMA downto 0); -- m_axis_ftch2_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ftch2_tvalid_new : out std_logic ; -- m_axis_ftch2_desc_available : out std_logic ; m_axis_ftch2_tready : in std_logic ; -- m_axis_ftch2_tlast : out std_logic ; -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (31 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- (3 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic := '0'; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_ftch_queue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_queue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; -- Number of words deep fifo needs to be -- 6 is subtracted as BD address are always 16 word aligned constant FIFO_WIDTH : integer := (128C_ENABLE_CDMA + 97(1-C_ENABLE_CDMA) -6); constant C_SG_WORDS_TO_FETCH1 : integer := C_SG_WORDS_TO_FETCH + 2C_ENABLE_MULTI_CHANNEL; --constant FETCH_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE -- C_SG_WORDS_TO_FETCH1)); constant FETCH_QUEUE_DEPTH : integer := 16; -- Select between BRAM or Logic Memory Type constant MEMORY_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE * C_SG_WORDS_TO_FETCH1 > 16); constant FETCH_QUEUE_CNT_WIDTH : integer := clog2(FETCH_QUEUE_DEPTH+1); constant DCNT_LO_INDEX : integer := max2(1,clog2(C_SG_WORDS_TO_FETCH1)) - 1; constant DCNT_HI_INDEX : integer := FETCH_QUEUE_CNT_WIDTH-1; -- CR616461 constant C_SG2_WORDS_TO_FETCH1 : integer := C_SG2_WORDS_TO_FETCH; constant FETCH2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE * C_SG2_WORDS_TO_FETCH1)); -- Select between BRAM or Logic Memory Type constant MEMORY2_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE * C_SG2_WORDS_TO_FETCH1 > 16); constant FETCH2_QUEUE_CNT_WIDTH : integer := clog2(FETCH2_QUEUE_DEPTH+1); constant DCNT2_LO_INDEX : integer := max2(1,clog2(C_SG2_WORDS_TO_FETCH1)) - 1; constant DCNT2_HI_INDEX : integer := FETCH2_QUEUE_CNT_WIDTH-1; -- CR616461 -- Width of fifo rd and wr counts - only used for proper fifo operation constant DESC2QUEUE_VECT_WIDTH : integer := 4; --constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461 constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461 --constant DCNT_HI_INDEX : integer := (DCNT_LO_INDEX + DESC2QUEUE_VECT_WIDTH) - 1; -- CR616461 constant ZERO_COUNT : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0'); constant ZERO_COUNT1 : std_logic_vector(FETCH2_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Internal signals signal curdesc_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_tvalid : std_logic := '0'; signal ftch_tvalid : std_logic := '0'; signal ftch_tvalid_new : std_logic := '0'; signal ftch_tdata : std_logic_vector (31 downto 0) := (others => '0'); signal ftch_tdata_new, reg1, reg2 : std_logic_vector (FIFO_WIDTH-1 downto 0) := (others => '0'); attribute mark_debug of ftch_tdata_new : signal is "true"; signal ftch_tlast : std_logic := '0'; signal ftch_tlast_new : std_logic := '0'; signal ftch_tready : std_logic := '0'; signal ftch_tready_ch1 : std_logic := '0'; signal ftch_tready_ch2 : std_logic := '0'; -- Misc Signals signal writing_curdesc : std_logic := '0'; signal writing_nxtdesc : std_logic := '0'; signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0'); signal writing_lsb : std_logic := '0'; signal writing_msb : std_logic := '0'; -- FIFO signals signal queue_rden2 : std_logic := '0'; signal queue_rden2_new : std_logic := '0'; signal queue_wren2 : std_logic := '0'; signal queue_wren2_new : std_logic := '0'; signal queue_empty2 : std_logic := '0'; signal queue_empty2_new : std_logic := '0'; signal queue_rden : std_logic := '0'; signal queue_rden_new : std_logic := '0'; signal queue_wren : std_logic := '0'; signal queue_wren_new : std_logic := '0'; signal queue_empty : std_logic := '0'; signal queue_empty_new : std_logic := '0'; signal queue_dout_valid : std_logic := '0'; signal queue_dout2_valid : std_logic := '0'; attribute mark_debug of queue_dout_valid : signal is "true"; attribute mark_debug of queue_dout2_valid : signal is "true"; signal queue_full_new : std_logic := '0'; signal queue_full2_new : std_logic := '0'; signal queue_full, queue_full2 : std_logic := '0'; signal queue_din_new : std_logic_vector (127 downto 0) := (others => '0'); signal queue_dout_new : std_logic_vector (96+31C_ENABLE_CDMA-6 downto 0) := (others => '0'); signal queue_dout_mcdma_new : std_logic_vector (63 downto 0) := (others => '0'); signal queue_dout2_new : std_logic_vector (96+31C_ENABLE_CDMA-6 downto 0) := (others => '0'); attribute mark_debug of queue_dout_new : signal is "true"; attribute mark_debug of queue_dout2_new : signal is "true"; signal queue_dout2_mcdma_new : std_logic_vector (63 downto 0) := (others => '0'); signal queue_din : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0'); signal queue_dout : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0'); signal queue_dout2 : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0'); signal queue_sinit : std_logic := '0'; signal queue_sinit2 : std_logic := '0'; signal queue_dcount_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0'); signal queue_dcount2_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0'); signal ftch_no_room : std_logic; signal ftch_active : std_logic := '0'; attribute mark_debug of ftch_active : signal is "true"; signal ftch_tvalid_mult : std_logic := '0'; signal ftch_tdata_mult : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ftch_tlast_mult : std_logic := '0'; signal counter : std_logic_vector (3 downto 0) := (others => '0'); signal wr_cntl : std_logic := '0'; signal sof_ftch_desc_del : std_logic; signal sof_ftch_desc_del1 : std_logic; signal sof_ftch_desc_pulse : std_logic; signal current_bd : std_logic_vector (31 downto 0) := (others => '0'); signal xfer_in_progress : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin SOF_DEL_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sof_ftch_desc_del <= '0'; else sof_ftch_desc_del <= sof_ftch_desc; end if; end if; end process SOF_DEL_PROCESS; SOF_DEL1_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then sof_ftch_desc_del1 <= '0'; elsif (m_axis_mm2s_tvalid = '1') then sof_ftch_desc_del1 <= sof_ftch_desc; end if; end if; end process SOF_DEL1_PROCESS; sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1); ftch_active <= ftch1_active or ftch2_active; --------------------------------------------------------------------------- -- Write current descriptor to FIFO or out channel port --------------------------------------------------------------------------- CMDDATA_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then current_bd <= (others => '0'); elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then current_bd <= next_bd; elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST + DATAMOVER_CMD_ADDRLSB_BIT downto DATAMOVER_CMD_ADDRLSB_BIT); end if; end if; end process CMDDATA_PROCESS; GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate begin ftch_tvalid_mult <= m_axis_mm2s_tvalid; ftch_tdata_mult <= m_axis_mm2s_tdata; ftch_tlast_mult <= m_axis_mm2s_tlast; wr_cntl <= m_axis_mm2s_tvalid; end generate GEN_MULT_CHANNEL; GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate begin ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid; ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata; ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast; m_axis_ftch1_tdata_mcdma_new <= (others => '0'); m_axis_ftch2_tdata_mcdma_new <= (others => '0'); COUNTER_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then counter <= (others => '0'); elsif (m_axis_mm2s_tvalid = '1') then counter <= std_logic_vector(unsigned(counter) + 1); end if; end if; end process COUNTER_PROCESS; end generate GEN_NOMULT_CHANNEL; --------------------------------------------------------------------------- -- TVALID MUX -- MUX tvalid out channel port --------------------------------------------------------------------------- CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate begin ftch_tdata_new (95 downto 0) <= data_concat;-- when (ftch_active = '1') else (others =>'0'); -- BD is always 16 word aligned ftch_tdata_new (121 downto 96) <= current_bd (31 downto 6); end generate CDMA_FIELDS; DMA_FIELDS : if C_ENABLE_CDMA = 0 generate begin ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0'); -- BD is always 16 word aligned ftch_tdata_new (90 downto 65) <= current_bd (31 downto 6); end generate DMA_FIELDS; ftch_tvalid_new <= data_concat_valid and ftch_active; ftch_tlast_new <= data_concat_tlast and ftch_active; GEN_MM2S : if C_INCLUDE_MM2S = 1 generate begin process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit = '1' or queue_rden_new = '1') then queue_empty_new <= '1'; queue_full_new <= '0'; elsif (queue_wren_new = '1') then queue_empty_new <= '0'; queue_full_new <= '1'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit = '1') then reg1 <= (others => '0'); elsif (queue_wren_new = '1') then reg1 <= ftch_tdata_new; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit = '1') then queue_dout_new <= (others => '0'); elsif (queue_rden_new = '1') then queue_dout_new <= reg1; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit = '1' or queue_dout_valid = '1') then queue_dout_valid <= '0'; elsif (queue_rden_new = '1') then queue_dout_valid <= '1'; end if; end if; end process; MCDMA_MM2S : if C_ENABLE_MULTI_CHANNEL = 1 generate begin -- Generate Synchronous FIFO I_CH1_FTCH_MCDMA_FIFO_NEW : entity proc_common_v4_0.sync_fifo_fg generic map ( C_FAMILY => C_FAMILY , C_MEMORY_TYPE => 0, --MEMORY_TYPE , C_WRITE_DATA_WIDTH => 64, C_WRITE_DEPTH => FETCH_QUEUE_DEPTH , C_READ_DATA_WIDTH => 64, C_READ_DEPTH => FETCH_QUEUE_DEPTH , C_PORTS_DIFFER => 0, C_HAS_DCOUNT => 0, C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH, C_HAS_ALMOST_FULL => 0, C_HAS_RD_ACK => 0, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_PRELOAD_REGS => 0,-- 1 = first word fall through C_PRELOAD_LATENCY => 1 -- 0 = first word fall through ) port map ( Clk => m_axi_sg_aclk , Sinit => queue_sinit , Din => data_concat_mcdma, --ftch_tdata_new, --queue_din , Wr_en => queue_wren_new , Rd_en => queue_rden_new , Dout => queue_dout_mcdma_new , Full => open, --queue_full_new , Empty => open, --queue_empty_new , Almost_full => open , Data_count => open, --queue_dcount_new , Rd_ack => open, --queue_dout_valid, --open , Rd_err => open , Wr_ack => open , Wr_err => open ); m_axis_ftch1_tdata_mcdma_new <= queue_dout_mcdma_new; end generate MCDMA_MM2S; CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 generate begin I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1.axi_sg_cntrl_strm generic map( C_PRMRY_IS_ACLK_ASYNC => C_ASYNC , C_PRMY_CMDFIFO_DEPTH => FETCH_QUEUE_DEPTH , C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_FAMILY => C_FAMILY ) port map( -- Secondary clock / reset m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Primary clock / reset axi_prmry_aclk => m_axi_primary_aclk , p_reset_n => p_reset_n , -- MM2S Error mm2s_stop => ch1_cntrl_strm_stop , -- Control Stream input cntrlstrm_fifo_wren => queue_wren , cntrlstrm_fifo_full => queue_full , cntrlstrm_fifo_din => queue_din , -- Memory Map to Stream Control Stream Interface m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); end generate CONTROL_STREAM; end generate GEN_MM2S; GEN_S2MM : if C_INCLUDE_S2MM = 1 generate begin process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit2 = '1' or queue_rden2_new = '1') then queue_empty2_new <= '1'; queue_full2_new <= '0'; elsif (queue_wren2_new = '1') then queue_empty2_new <= '0'; queue_full2_new <= '1'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit2 = '1') then reg2 <= (others => '0'); elsif (queue_wren2_new = '1') then reg2 <= ftch_tdata_new; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit2 = '1') then queue_dout2_new <= (others => '0'); elsif (queue_rden2_new = '1') then queue_dout2_new <= reg2; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit2 = '1' or queue_dout2_valid = '1') then queue_dout2_valid <= '0'; elsif (queue_rden2_new = '1') then queue_dout2_valid <= '1'; end if; end if; end process; MCDMA_S2MM : if C_ENABLE_MULTI_CHANNEL = 1 generate begin -- Generate Synchronous FIFO I_CH2_FTCH_MCDMA_FIFO_NEW : entity proc_common_v4_0.sync_fifo_fg generic map ( C_FAMILY => C_FAMILY , C_MEMORY_TYPE => 0, --MEMORY_TYPE , C_WRITE_DATA_WIDTH => 64, C_WRITE_DEPTH => FETCH_QUEUE_DEPTH , C_READ_DATA_WIDTH => 64, C_READ_DEPTH => FETCH_QUEUE_DEPTH , C_PORTS_DIFFER => 0, C_HAS_DCOUNT => 0, C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH, C_HAS_ALMOST_FULL => 0, C_HAS_RD_ACK => 0, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_PRELOAD_REGS => 0,-- 1 = first word fall through C_PRELOAD_LATENCY => 1 -- 0 = first word fall through ) port map ( Clk => m_axi_sg_aclk , Sinit => queue_sinit2 , Din => data_concat_mcdma, --ftch_tdata_new, --queue_din , Wr_en => queue_wren2_new , Rd_en => queue_rden2_new , Dout => queue_dout2_new , Full => open, --queue_full2_new , Empty => open, --queue_empty2_new , Almost_full => open , Data_count => queue_dcount2_new , Rd_ack => open, --queue_dout2_valid , Rd_err => open , Wr_ack => open , Wr_err => open ); m_axis_ftch2_tdata_mcdma_new <= queue_dcount2_new; end generate MCDMA_S2MM; end generate GEN_S2MM; ----------------------------------------------------------------------- -- Internal Side ----------------------------------------------------------------------- -- Drive tready with fifo not full ftch_tready <= ftch_tready_ch1 or ftch_tready_ch2; -- Following is the APP data that goes into APP FIFO queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast; queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata; GEN_CH1_CTRL : if C_INCLUDE_MM2S =1 generate begin --queue_full_new <= '1' when (queue_dcount_new = "00100") else '0'; queue_sinit <= desc1_flush or not m_axi_sg_aresetn; ftch_tready_ch1 <= (not queue_full and ftch1_active); m_axis1_mm2s_tready <= ftch_tready_ch1; -- Wr_en to APP FIFO. Data is written only when BD with SOF is fetched. queue_wren <= not queue_full and sof_ftch_desc and m_axis_mm2s_tvalid and ftch1_active; -- Wr_en of BD FIFO queue_wren_new <= not queue_full_new and ftch_tvalid_new and ftch1_active; ftch1_queue_empty <= queue_empty_new; ftch1_queue_full <= queue_full_new; ftch1_pause <= queue_full_new; -- RD_en of APP FIFO based on empty and tready -- RD_EN of BD FIFO based on empty and tready queue_rden_new <= not queue_empty_new and m_axis_ftch1_tready; -- drive valid if fifo is not empty m_axis_ftch1_tvalid <= '0'; m_axis_ftch1_tvalid_new <= queue_dout_valid; --not queue_empty_new and (not ch2_sg_idle); -- below signal triggers the fetch of BD in MM2S Mngr m_axis_ftch1_desc_available <= not queue_empty_new and (not ch2_sg_idle); -- Pass data out to port channel with MSB driving tlast m_axis_ftch1_tlast <= '0'; m_axis_ftch1_tdata <= (others => '0'); m_axis_ftch1_tdata_new <= queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0); writing1_curdesc_out <= writing_curdesc and ftch1_active; NOCONTROL_STREAM_ASST : if C_SG_WORDS_TO_FETCH = 8 generate begin m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= (others => '0'); m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; end generate NOCONTROL_STREAM_ASST; end generate GEN_CH1_CTRL; GEN_NO_CH1_CTRL : if C_INCLUDE_MM2S =0 generate begin m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= "0000"; m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; ftch_tready_ch1 <= '0'; m_axis1_mm2s_tready <= '0'; -- Write to fifo if it is not full and data is valid queue_wren <= '0'; ftch1_queue_empty <= '0'; ftch1_queue_full <= '0'; ftch1_pause <= '0'; queue_rden <= '0'; -- drive valid if fifo is not empty m_axis_ftch1_tvalid <= '0'; -- Pass data out to port channel with MSB driving tlast m_axis_ftch1_tlast <= '0'; m_axis_ftch1_tdata <= (others => '0'); writing1_curdesc_out <= '0'; m_axis_ftch1_tdata_new <= (others => '0'); m_axis_ftch1_tvalid_new <= '0'; m_axis_ftch1_desc_available <= '0'; end generate GEN_NO_CH1_CTRL; GEN_CH2_CTRL : if C_INCLUDE_S2MM =1 generate begin queue_sinit2 <= desc2_flush or not m_axi_sg_aresetn; ftch_tready_ch2 <= (not queue_full2_new and ftch2_active); m_axis2_mm2s_tready <= ftch_tready_ch2; queue_wren2 <= '0'; -- Wr_en for S2MM BD FIFO queue_wren2_new <= not queue_full2_new and ftch_tvalid_new and ftch2_active; --queue_full2_new <= '1' when (queue_dcount2_new = "00100") else '0'; -- Pass fifo status back to fetch sm for channel IDLE determination ftch2_queue_empty <= queue_empty2_new; ftch2_queue_full <= queue_full2_new; ftch2_pause <= queue_full2_new; queue_rden2 <= '0'; -- Rd_en for S2MM BD FIFO queue_rden2_new <= not queue_empty2_new and m_axis_ftch2_tready; m_axis_ftch2_tvalid <= '0'; m_axis_ftch2_tvalid_new <= queue_dout2_valid; -- not queue_empty2_new and (not ch2_sg_idle); m_axis_ftch2_desc_available <= not queue_empty2_new and (not ch2_sg_idle); -- Pass data out to port channel with MSB driving tlast m_axis_ftch2_tlast <= '0'; m_axis_ftch2_tdata <= (others => '0'); m_axis_ftch2_tdata_new <= queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0); writing2_curdesc_out <= writing_curdesc and ftch2_active; end generate GEN_CH2_CTRL; GEN_NO_CH2_CTRL : if C_INCLUDE_S2MM =0 generate begin ftch_tready_ch2 <= '0'; m_axis2_mm2s_tready <= '0'; queue_wren2 <= '0'; -- Pass fifo status back to fetch sm for channel IDLE determination --ftch_queue_empty <= queue_empty; CR 621600 ftch2_queue_empty <= '0'; ftch2_queue_full <= '0'; ftch2_pause <= '0'; queue_rden2 <= '0'; m_axis_ftch2_tvalid <= '0'; -- Pass data out to port channel with MSB driving tlast m_axis_ftch2_tlast <= '0'; m_axis_ftch2_tdata <= (others => '0'); m_axis_ftch2_tdata_new <= (others => '0'); m_axis_ftch2_tvalid_new <= '0'; writing2_curdesc_out <= '0'; m_axis_ftch2_desc_available <= '0'; end generate GEN_NO_CH2_CTRL; -- If writing curdesc out then flag for proper mux selection writing_curdesc <= curdesc_tvalid; -- Map intnal signal to port -- Map port to internal signal writing_nxtdesc <= writing_nxtdesc_in; end implementation;	bsd-2-clause	ac50c123bd76e09bcb82bee493ad84eb	0.470731	3.78738	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_addr_cntl.vhd	1	42,473	---------------------------------------------------------------------------- -- axi_datamover_addr_cntl.vhd ---------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_addr_cntl.vhd -- -- Description: -- This file implements the axi_datamover Master Address Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_addr_cntl.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- -- DET 9/1/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Fixed Lint reported excesive line length for line 196. -- ^^^^^^ -- -- DET 9/1/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Fixed a Lint reported issue with the vector widths of the addr2axi_aprot -- assignment to the constant APROT_VALUE. The code was ok but Spyglass -- was not interpreting the vector MS Index correctly, I changed the HDL -- anyway. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; Use axi_datamover_v5_1.axi_datamover_fifo; ------------------------------------------------------------------------------- entity axi_datamover_addr_cntl is generic ( C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4; -- sets the depth of the Command Queue FIFO C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the address bus width C_ADDR_ID : Integer range 0 to 255 := 0; -- Sets the value to be on the AxID output C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the AxID output C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Command Tag field width C_FAMILY : String := "virtex7" -- Specifies the target FPGA family ); port ( -- Clock input --------------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------ -- AXI Address Channel I/O -------------------------------------------- addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- addr2axi_alen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- addr2axi_asize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- addr2axi_aburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_acache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_auser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_aprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- addr2axi_avalid : out std_logic; -- -- AXI Address Channel VALID output -- -- axi2addr_aready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------- -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- Command Calculation Interface ----------------------------------------- mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : In std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- Sized to support 256 data beat bursts -- -- mstr2addr_size : In std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : In std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : In std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_user : In std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cmd_cmplt : In std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2addr_cmd_valid : in std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : out std_logic; -- -- Indication to the Command Calculator that the -- -- command is being accepted -- -------------------------------------------------------------------------- -- Halted Indication to Reset Module ------------------------------ addr2rst_stop_cmplt : out std_logic; -- -- Output flag indicating the address controller has stopped -- -- posting commands to the Address Channel due to a stop -- -- request vai the data2addr_stop_req input port -- ------------------------------------------------------------------ -- Address Generation Control --------------------------------------- allow_addr_req : in std_logic; -- -- Input used to enable/stall the posting of address requests. -- -- 0 = stall address request generation. -- -- 1 = Enable Address request geneartion -- -- addr_req_posted : out std_logic; -- -- Indication from the Address Channel Controller to external -- -- User logic that an address has been posted to the -- -- AXI Address Channel. -- --------------------------------------------------------------------- -- Data Channel Interface --------------------------------------------- addr2data_addr_posted : Out std_logic; -- -- Indication from the Address Channel Controller to the -- -- Data Controller that an address has been posted to the -- -- AXI Address Channel. -- -- data2addr_data_rdy : In std_logic; -- -- Indication that the Data Channel is ready to send the first -- -- databeat of the next command on the write data channel. -- -- This is used for the "wait for data" feature which keeps the -- -- address controller from issuing a transfer requset until the -- -- corresponding data is ready. This is expected to be held in -- -- the asserted state until the addr2data_addr_posted signal is -- -- asserted. -- -- data2addr_stop_req : In std_logic; -- -- Indication that the Data Channel has encountered an error -- -- or a soft shutdown request and needs the Address Controller -- -- to stop posting commands to the AXI Address channel -- ----------------------------------------------------------------------- -- Status Module Interface --------------------------------------- addr2stat_calc_error : out std_logic; -- -- Indication to the Status Module that the Addr Cntl FIFO -- -- is loaded with a Calc error -- -- addr2stat_cmd_fifo_empty : out std_logic -- -- Indication to the Status Module that the Addr Cntl FIFO -- -- is empty -- ------------------------------------------------------------------ ); end entity axi_datamover_addr_cntl; architecture implementation of axi_datamover_addr_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant Declarations -------------------------------------------- Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0'); --'0' & -- bit 2, Normal Access --'0' & -- bit 1, Nonsecure Access --'0'; -- bit 0, Data Access Constant LEN_WIDTH : integer := 8; Constant SIZE_WIDTH : integer := 3; Constant BURST_WIDTH : integer := 2; Constant CMD_CMPLT_WIDTH : integer := 1; Constant CALC_ERROR_WIDTH : integer := 1; Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width C_ADDR_WIDTH + -- Cmd Address field width LEN_WIDTH + -- Cmd Len field width SIZE_WIDTH + -- Cmd Size field width BURST_WIDTH + -- Cmd Burst field width CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width CALC_ERROR_WIDTH + -- Cmd Calc Error flag 8; -- Cmd Cache, user fields Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM; -- Signal Declarations -------------------------------------------- signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0'); signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0'); signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0'); signal sig_axi_avalid : std_logic := '0'; signal sig_axi_aready : std_logic := '0'; signal sig_addr_posted : std_logic := '0'; signal sig_calc_error : std_logic := '0'; signal sig_cmd_fifo_empty : std_logic := '0'; Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0'); Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_fifo_next_cmd_cmplt : std_logic := '0'; signal sig_fifo_calc_error : std_logic := '0'; signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_fifo_rd_cmd_ready : std_logic := '0'; signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0'); signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0'); signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0'); signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0'); signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0'); signal sig_next_cmd_cmplt_reg : std_logic := '0'; signal sig_addr_valid_reg : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_pop_addr_reg : std_logic := '0'; signal sig_push_addr_reg : std_logic := '0'; signal sig_addr_reg_empty : std_logic := '0'; signal sig_addr_reg_full : std_logic := '0'; signal sig_posted_to_axi : std_logic := '0'; -- obsoleted signal sig_set_wfd_flop : std_logic := '0'; -- obsoleted signal sig_clr_wfd_flop : std_logic := '0'; -- obsoleted signal sig_wait_for_data : std_logic := '0'; -- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0'; signal sig_allow_addr_req : std_logic := '0'; signal sig_posted_to_axi_2 : std_logic := '0'; signal new_cmd_in : std_logic; signal first_addr_valid : std_logic; signal first_addr_valid_del : std_logic; signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0); signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0); signal addr2axi_cache_int : std_logic_vector (7 downto 0); signal addr2axi_cache_int1 : std_logic_vector (7 downto 0); signal last_one : std_logic; signal latch : std_logic; signal first_one : std_logic; signal latch_n : std_logic; signal latch_n_del : std_logic; signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0); -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no"; begin --(architecture implementation) -- AXI I/O Port assignments addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH)); addr2axi_aaddr <= sig_axi_addr ; addr2axi_alen <= sig_axi_alen ; addr2axi_asize <= sig_axi_asize ; addr2axi_aburst <= sig_axi_aburst; addr2axi_acache <= sig_axi_acache; addr2axi_auser <= sig_axi_auser; addr2axi_aprot <= APROT_VALUE ; addr2axi_avalid <= sig_axi_avalid; sig_axi_aready <= axi2addr_aready; -- Command Calculator Handshake output sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ; addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; -- Data Channel Controller synchro pulse output addr2data_addr_posted <= sig_addr_posted; -- Status Module Interface outputs addr2stat_calc_error <= sig_calc_error ; addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and sig_cmd_fifo_empty; -- Flag Indicating the Address Controller has completed a Stop addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case sig_addr_reg_empty) or (data2addr_stop_req and -- shutdown after error trap sig_calc_error); -- Assign the address posting control and status sig_allow_addr_req <= allow_addr_req ; addr_req_posted <= sig_posted_to_axi_2 ; -- Internal logic ------------------------------ ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_FIFO -- -- If Generate Description: -- Implements the case where the cmd qualifier depth is -- greater than 1. -- ------------------------------------------------------------ GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate begin -- Format the input FIFO data word sig_aq_fifo_data_in <= mstr2addr_cache & mstr2addr_user & mstr2addr_calc_error & mstr2addr_cmd_cmplt & mstr2addr_burst & mstr2addr_size & mstr2addr_len & mstr2addr_addr & mstr2addr_tag ; -- Rip fields from FIFO output data word sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 7) downto (C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 4) ); sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 3) downto (C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH) ); sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH)-1); sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH)-1); sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH) ; sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH) ; sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH) ; sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH)-1 downto C_TAG_WIDTH) ; sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_ADDR_QUAL_FIFO -- -- Description: -- Instance for the Address/Qualifier FIFO -- ------------------------------------------------------------ I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => ADDR_QUAL_WIDTH , C_DEPTH => C_ADDR_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_aq_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_fifo_rd_cmd_ready , fifo_rd_tdata => sig_aq_fifo_data_out , fifo_rd_empty => sig_cmd_fifo_empty ); end generate GEN_ADDR_FIFO; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_ADDR_FIFO -- -- If Generate Description: -- Implements the case where no additional FIFOing is needed -- on the input command address/qualifiers. -- ------------------------------------------------------------ GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate begin -- Bypass FIFO sig_fifo_next_tag <= mstr2addr_tag ; sig_fifo_next_addr <= mstr2addr_addr ; sig_fifo_next_len <= mstr2addr_len ; sig_fifo_next_size <= mstr2addr_size ; sig_fifo_next_burst <= mstr2addr_burst ; sig_fifo_next_cache <= mstr2addr_cache ; sig_fifo_next_user <= mstr2addr_user ; sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ; sig_fifo_calc_error <= mstr2addr_calc_error ; sig_cmd_fifo_empty <= sig_addr_reg_empty ; sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ; sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ; end generate GEN_NO_ADDR_FIFO; -- Output Register Logic ------------------------------------------- sig_axi_addr <= sig_next_addr_reg ; sig_axi_alen <= sig_next_len_reg ; sig_axi_asize <= sig_next_size_reg ; sig_axi_aburst <= sig_next_burst_reg ; sig_axi_acache <= sig_next_cache_reg ; sig_axi_auser <= sig_next_user_reg ; sig_axi_avalid <= sig_addr_valid_reg ; sig_calc_error <= sig_calc_error_reg ; sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and sig_allow_addr_req and -- obsoleted not(sig_wait_for_data) and not(data2addr_stop_req); sig_addr_posted <= sig_posted_to_axi ; -- Internal signals sig_push_addr_reg <= sig_addr_reg_empty and sig_fifo_rd_cmd_valid and sig_allow_addr_req and -- obsoleted not(sig_wait_for_data) and not(data2addr_stop_req); sig_pop_addr_reg <= not(sig_calc_error_reg) and sig_axi_aready and sig_addr_reg_full; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_FIFO_REG -- -- Process Description: -- This process implements a register for the Address -- Control FIFO that operates like a 1 deep Sync FIFO. -- ------------------------------------------------------------- IMP_ADDR_FIFO_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_addr_reg = '1') then sig_next_tag_reg <= (others => '0') ; sig_next_addr_reg <= (others => '0') ; sig_next_len_reg <= (others => '0') ; sig_next_size_reg <= (others => '0') ; sig_next_burst_reg <= (others => '0') ; sig_next_cache_reg <= (others => '0') ; sig_next_user_reg <= (others => '0') ; sig_next_cmd_cmplt_reg <= '0' ; sig_addr_valid_reg <= '0' ; sig_calc_error_reg <= '0' ; sig_addr_reg_empty <= '1' ; sig_addr_reg_full <= '0' ; elsif (sig_push_addr_reg = '1') then sig_next_tag_reg <= sig_fifo_next_tag ; sig_next_addr_reg <= sig_fifo_next_addr ; sig_next_len_reg <= sig_fifo_next_len ; sig_next_size_reg <= sig_fifo_next_size ; sig_next_burst_reg <= sig_fifo_next_burst ; sig_next_cache_reg <= sig_fifo_next_cache ; sig_next_user_reg <= sig_fifo_next_user ; sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ; sig_addr_valid_reg <= not(sig_fifo_calc_error); sig_calc_error_reg <= sig_fifo_calc_error ; sig_addr_reg_empty <= '0' ; sig_addr_reg_full <= '1' ; else null; -- don't change state end if; end if; end process IMP_ADDR_FIFO_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_POSTED_FLAG -- -- Process Description: -- This implements a FLOP that creates a 1 clock wide pulse -- indicating a new address/qualifier set has been posted to -- the AXI Addres Channel outputs. This is used to synchronize -- the Data Channel Controller. -- ------------------------------------------------------------- IMP_POSTED_FLAG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_posted_to_axi <= '0'; sig_posted_to_axi_2 <= '0'; elsif (sig_push_addr_reg = '1') then sig_posted_to_axi <= '1'; sig_posted_to_axi_2 <= '1'; else sig_posted_to_axi <= '0'; sig_posted_to_axi_2 <= '0'; end if; end if; end process IMP_POSTED_FLAG; -- PROC_CMD_DETECT : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- first_addr_valid_del <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- first_addr_valid_del <= first_addr_valid; -- end if; -- end process PROC_CMD_DETECT; -- -- PROC_ADDR_DET : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- first_addr_valid <= '0'; -- first_addr_int <= (others => '0'); -- last_addr_int <= (others => '0'); -- elsif (primary_aclk'event and primary_aclk = '1') then -- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then -- first_addr_valid <= '1'; -- first_addr_int <= mstr2addr_addr; -- last_addr_int <= last_addr_int; -- elsif (mstr2addr_cmd_cmplt = '1') then -- first_addr_valid <= '0'; -- first_addr_int <= first_addr_int; -- last_addr_int <= mstr2addr_addr; -- end if; -- end if; -- end process PROC_ADDR_DET; -- -- latch <= first_addr_valid and (not first_addr_valid_del); -- latch_n <= (not first_addr_valid) and first_addr_valid_del; -- -- PROC_CACHE1 : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- mstr2addr_cache_info_int <= (others => '0'); -- latch_n_del <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- if (latch_n = '1') then -- mstr2addr_cache_info_int <= mstr2addr_cache_info; -- end if; -- latch_n_del <= latch_n; -- end if; -- end process PROC_CACHE1; -- -- -- PROC_CACHE : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- addr2axi_cache_int1 <= (others => '0'); -- first_one <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- first_one <= '0'; ---- if (latch = '1' and first_one = '0') then -- first one -- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then -- addr2axi_cache_int1 <= mstr2addr_cache_info; ---- first_one <= '1'; ---- elsif (latch_n_del = '1') then ---- addr2axi_cache_int <= mstr2addr_cache_info_int; -- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then -- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4); -- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then -- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4); -- end if; -- end if; -- end process PROC_CACHE; -- -- -- PROC_CACHE2 : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- addr2axi_cache_int <= (others => '0'); -- elsif (primary_aclk'event and primary_aclk = '1') then -- addr2axi_cache_int <= addr2axi_cache_int1; -- end if; -- end process PROC_CACHE2; -- --addr2axi_cache <= addr2axi_cache_int (3 downto 0); --addr2axi_user <= addr2axi_cache_int (7 downto 4); -- end implementation;	bsd-2-clause	b164ccf0bc924253a8da524d5c9cbfa9	0.395216	4.962959	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/architecture/rule_601_test_input.vhd	1	8,216	entity FIFO is generic ( G_WIDTH : natural := 16 ); port ( I_INPUT : in std_logic; O_OUTPUT : out std_logic; IO_INOUT : inout std_logic ); end entity; architecture rtl of fifo is function func1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) return integer is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; procedure proc1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) is variable w_data : std_logic_vector(g_width - 1 downto 0); variable w_read : std_logic_vector(i_input'range); variable w_read : std_logic_vector(o_output'left downto 0); variable w_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; signal w_data : std_logic_vector(G_WIDTH - 1 downto 0); constant w_read : std_logic_vector(I_INPUT'range); shared variable w_read : std_logic_vector(O_OUTPUT'left downto 0); signal w_read : std_logic_vector(31 downto IO_INOUT'right); begin output <= large_data(g_width - 1 downto 0); process (I_INPUT, O_OUTPUT, IO_INOUT) is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end process; a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input => I_INPUT, o_output => O_OUTPUT, io_inout => IO_INOUT ); U_RAM : RAM generic map ( g_width => g_width ) port map ( I_INPUT, O_OUTPUT, IO_INOUT ); end architecture rtl; -- Violations Below architecture rtl of fifo is function func1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) return integer is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; procedure proc1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) is variable w_data : std_logic_vector(g_width - 1 downto 0); variable w_read : std_logic_vector(i_input'range); variable w_read : std_logic_vector(o_output'left downto 0); variable w_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(i_input'range); signal w_read : std_logic_vector(o_output'left downto 0); signal w_read : std_logic_vector(31 downto io_inout'right); begin output <= large_data(g_width - 1 downto 0); process (i_input, o_output, io_inout) is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end process; a <= i_input; b <= o_output; c <= io_inout; U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input => i_input, o_output => o_output, io_inout => io_inout ); U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input, o_output, io_inout ); end architecture rtl; -- Change entities entity NEW_FIFO is generic ( g_width : natural := 16 ); port ( i_input : in std_logic; o_output : out std_logic; io_inout : inout std_logic ); end entity; architecture rtl of new_fifo is function func1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) return integer is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; procedure proc1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) is variable w_data : std_logic_vector(G_WIDTH - 1 downto 0); variable w_read : std_logic_vector(I_INPUT'range); variable w_read : std_logic_vector(O_OUTPUT'left downto 0); variable w_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(i_input'range); signal w_read : std_logic_vector(o_output'left downto 0); signal w_read : std_logic_vector(31 downto io_inout'right); begin output <= large_data(g_width - 1 downto 0); process (i_input, o_output, io_inout) is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end process; a <= i_input; b <= o_output; c <= io_inout; U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT => i_input, O_OUTPUT => o_output, IO_INOUT => io_inout ); U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( i_input, o_output, io_inout ); end architecture rtl; -- Violations architecture rtl of new_fifo is function func1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) return integer is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; procedure proc1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) is variable w_data : std_logic_vector(G_WIDTH - 1 downto 0); variable w_read : std_logic_vector(I_INPUT'range); variable w_read : std_logic_vector(O_OUTPUT'left downto 0); variable w_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(I_INPUT'range); signal w_read : std_logic_vector(O_OUTPUT'left downto 0); signal w_read : std_logic_vector(31 downto IO_INOUT'right); begin output <= large_data(G_WIDTH - 1 downto 0); process (I_INPUT, O_OUTPUT, IO_INOUT) is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end process; a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT => I_INPUT, O_OUTPUT => O_OUTPUT, IO_INOUT => IO_INOUT ); U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT, O_OUTPUT, IO_INOUT ); end architecture rtl;	gpl-3.0	e88599457b2386a01d1af5739d32ba5d	0.607595	3.127522	false	false	false	false
siavooshpayandehazad/TTU_CPU_Project	pico_CPU_pipelined/GPIO.vhd	1	634	library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.all; use work.pico_cpu.all; entity GPIO is generic (BitWidth: integer); port ( IO_sel: in std_logic; IO: inout std_logic_vector (BitWidth-1 downto 0); WrtData: in std_logic_vector (BitWidth-1 downto 0); RdData: out std_logic_vector (BitWidth-1 downto 0) ); end GPIO; architecture behavioral of GPIO is begin process(IO_sel, IO, WrtData)begin if IO_sel = '0' then IO <= (others => 'Z'); RdData <= IO; else IO <= WrtData; end if; end process; end behavioral;	gpl-2.0	ac0e3b83f638f36311b8aa883be40b13	0.59306	3.336842	false	false	false	false
rjarzmik/mips_processor	EX/ALU.vhd	1	8,032	------------------------------------------------------------------------------- -- Title : Arithmetic and Logic Unit -- Project : ------------------------------------------------------------------------------- -- File : ALU.vhd.vhd -- Author : Robert Jarzmik (Intel) <[email protected]> -- Company : -- Created : 2016-11-16 -- Last update: 2016-12-09 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Integer Computing Unit ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-16 1.0 rjarzmik Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cpu_defs.all; use work.instruction_defs.all; ------------------------------------------------------------------------------- entity ALU is generic ( ADDR_WIDTH : integer := 32; DATA_WIDTH : integer := 32; NB_REGISTERS : positive := 32 ); port ( clk : in std_logic; rst : in std_logic; stall_req : in std_logic; -- stall current instruction kill_req : in std_logic; -- kill current instruction alu_op : in alu_op_type; i_reg1 : in register_port_type; i_reg2 : in register_port_type; i_divide_0 : in std_logic; -- if set, a division attempt will be a X/0 -- Carry-over signals i_jump_target : in std_logic_vector(ADDR_WIDTH - 1 downto 0); i_jump_op : in jump_type; i_mem_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); i_mem_op : in memory_op_type; i_instr_tag : in instr_tag_t; o_reg1 : out register_port_type; o_reg2 : out register_port_type; o_jump_target : out std_logic_vector(ADDR_WIDTH - 1 downto 0); o_is_jump : out std_logic; o_mem_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); o_mem_op : out memory_op_type; o_instr_tag : out instr_tag_t; -- Debug signal i_dbg_ex_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0); o_dbg_ex_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0) ); end entity ALU; ------------------------------------------------------------------------------- architecture rtl of ALU is signal ra : unsigned(DATA_WIDTH - 1 downto 0); signal rb : unsigned(DATA_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- signal q : unsigned(DATA_WIDTH * 2 - 1 downto 0) := (others => '0'); signal cond_zero : std_logic; signal cond_carry : std_logic; signal jump_op : jump_type; signal is_jump : std_logic; signal adder_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal substracter_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal multiplier_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal divider_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal log_and_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal log_or_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal log_nor_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal log_xor_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal slt_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); begin -- architecture rtl ----------------------------------------------------------------------------- -- Component instantiations ----------------------------------------------------------------------------- adder : entity work.ALU_Adder generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => adder_q); substracter : entity work.ALU_Substracter generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => substracter_q); multiplier : entity work.ALU_Multiplier generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => multiplier_q); divider : entity work.ALU_Divider generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, i_div_by_0 => i_divide_0, o_q => divider_q); do_log_and : entity work.ALU_Log_And generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => log_and_q); do_log_or : entity work.ALU_Log_or generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => log_or_q); do_log_nor : entity work.ALU_Log_nor generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => log_nor_q); do_log_xor : entity work.ALU_Log_xor generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => log_xor_q); do_slt : entity work.ALU_Set_Lower_Than generic map ( DATA_WIDTH => DATA_WIDTH) port map ( rst => rst, i_ra => ra, i_rb => rb, o_q => slt_q); with alu_op select q <= adder_q when add, substracter_q when substract, multiplier_q when multiply, divider_q when divide, log_and_q when log_and, log_or_q when log_or, log_nor_q when log_nor, log_xor_q when log_xor, slt_q when slt, adder_q when all_zero; process(rst, clk, kill_req, stall_req) begin if rst = '1' and rising_edge(clk) then o_reg1.we <= '0'; o_reg2.we <= '0'; o_is_jump <= '0'; o_mem_op <= none; o_instr_tag <= INSTR_TAG_NONE; elsif kill_req = '1' and rising_edge(clk) then o_reg1.we <= '0'; o_reg2.we <= '0'; o_is_jump <= '0'; o_mem_op <= none; o_instr_tag <= INSTR_TAG_NONE; elsif stall_req = '0' and rising_edge(clk) then o_reg1.we <= i_reg1.we; o_reg1.idx <= i_reg1.idx; o_reg2.we <= i_reg2.we; o_reg2.idx <= i_reg2.idx; o_jump_target <= i_jump_target; o_mem_data <= i_mem_data; o_mem_op <= i_mem_op; o_is_jump <= is_jump; o_reg1.data <= std_logic_vector(q(DATA_WIDTH -1 downto 0)); o_reg2.data <= std_logic_vector(q(DATA_WIDTH * 2 -1 downto DATA_WIDTH)); o_instr_tag <= i_instr_tag; end if; end process; debug : process(rst, clk, stall_req, kill_req) begin if rst = '1' then o_dbg_ex_pc <= (others => 'X'); elsif rising_edge(clk) and kill_req = '1' then o_dbg_ex_pc <= (others => 'X'); elsif rising_edge(clk) and stall_req = '1' then elsif rising_edge(clk) then o_dbg_ex_pc <= i_dbg_ex_pc; end if; end process debug; ra <= (others => '0') when rst = '1' else unsigned(i_reg1.data); rb <= (others => '0') when rst = '1' else unsigned(i_reg2.data); cond_zero <= '0' when rst = '1' else '1' when unsigned(q) = to_unsigned(0, q'length) else '0'; cond_carry <= q(DATA_WIDTH); jump_op <= i_jump_op; is_jump <= '1' when (jump_op = always) or (jump_op = zero and cond_zero = '1') or (jump_op = non_zero and cond_zero = '0') or (jump_op = lesser_or_zero and (cond_carry = '1' or cond_zero = '1')) or (jump_op = lesser and cond_carry = '1') or (jump_op = greater and cond_carry = '0') or (jump_op = greater_or_zero and (cond_carry = '0' or cond_zero = '1')) else '0'; end architecture rtl; -------------------------------------------------------------------------------	gpl-3.0	503b2e44f3fd07181ec33eab1fd4017a	0.47261	3.414966	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/dc_ss_fwft.vhd	2	9,156	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block rHJ+29MZ/51RW+8RxBIyMfaHxYDaaOjBE/eEB1G4Z7n+Y4SNCiLpsD4QV/UHYQVcratvHGJL/Iwh 5tcSX5ro0Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block IjfEfFJ+wSDFntr7e0yFi3zx5F9j8KL+3YLAnStzZfksF7IvXdzwub4fw8+A0UUlBFtDZA0dAWXl 1H0D5rU8tXsQvjlffxb6ttDSltxnckWc9DlXznVYuqaKqt4fkad2vvLjTswpzKhBRGNQogydJlay MVR0AnHjZyiozQlGUqM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Pr9hkyoA4bxBXOYxo81Aj0Cg1VdKc6RcLD5oJK4SjzoAY4EIJwx4DGyAj5fGmZVGGTKasiDv0b03 ktw1A+pr7SIG2+AiG9v2eZvIulAxY4v/HtsPTMVvxB5kGu+4J3xJwkG3IihcHVPsJxESw545tZ3M uQXYyZe4ZI++yNHF7w1V5Bwzaz9e5bPGI08iMS9EkqToVc8OKHXsA/bVpDWJCI3WwgPbInr26//B U20XskKobVxeSRmOdW7CChVZY6yur6EeICkYylCAb49UfiwF8HxZCO82OamUBDapXEXOVP8Ys9Je 6ygeBUm8WWNyXi/5L3i5UNPlWKQIG/cZzv1Bfw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block l2mvE1B53x+qmvvu7ioq8n2bk022Ko8YUnyvuyQWqPcB/lKbsK2BZqB/8oPaIoKnxfcPAfCxwj32 bEpyeiYS6dD58IvtGelNx3jKosWLxCq2UIj8E0r7E6m0iAngMZQ54c34WDCjZ/I7IXSyR6Dl6J7c M1mGM+PBkAetpGJRO4Y= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Gw11EzgCL46WMHUhQRKXx64bVvw4eVlOWxvvByQtkAM74dcurr6NTsYIW/IBvMoJERiE1RyLXWSy 3byDXGIr2+aD+3orWbiqMaNUbmdYQc1v53ls74GUo87b1S/ut+8xQ1K8jKf3yj/zQ97QPhPNQqRX SPmZjGfn5ZHYyzL3QBdeDdj4hNBOH6DSF4Qx1X8dtButL4EXXCizSXYZHXOHiI5K0oS+JLJDrwGm 7YSKzx1zmldF4hgIMDRlE46c/CqrsTWjeh2LfaL6Vpida6m8sSSnHtUGIB7YhCz60WNYKxXgR2gB TqQoSKOBsxwc8N/7NtZzr68DXeo1PNV+vGl7eA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040) `protect data_block g3pFOXw4WP1M7lhfy0lFLTk0YiBQwFW/yjglnWbFB7KBwwX90+LwjAhUk9N/JSUK19A2kCZgMUwO XqwXyS8p4eA9yRlsHWY6r9CfCbO6af6+I1iLx10fwTYJAZZwkswTN80c2ZCM+unOxbspizke0Tc+ GCj9D48fVu9qKqhlQuKE5ppU37Aj1GQ1qiemqPe166r3/94TpiCGhUHh4WNS8/R6qwZK5r/zE0af 5dzyfp5tv8AzseZ9MMcqhZNUaJfK0V8qaYyql+EDay4RX+4S+jAlTcxRLnwV94X/UYHgLlgevzHy D5CHRb8XTTFFfLPXbHyG/8+YOjLA5jRpz4DKUkwLSUhamruvNgBM1zIwTwF1/9DpGGubMRuIKEkr ktZmqntEVHpeqE+OEy6RkWVoNeZbZs52CB6ZIAfZ0xZ8XI05K+pHbMtKGmOkpkf0SmuMB//PI6NW 5X+PkYaCyWjr52dc9GXaYaDGSBpIm7kqBO2QYWCTORLAtouiPpm5i3xsZHRP/Eyl82lbjuKvMiDu bclSwRfCGhEg5AfcFvHk8Li/Yu7DGut6UOZszl9QyGQLSZ/fdkotHsJRy5OgnfKU6UJLOd67PVru 8yCJ6rytD1OP1wLCMVVBo+LDAYURUsnIflpqMCHyzTiTXWymhXbWR6wch0eaTGkKprkyxhjlyIwg NmRGxWwYiuTbgk6HLNLm+PcBGwy9NJiqY+gvXPRaDlsDrliIB68YIZxUm3MMbnm/lQU5WmOBd37W oJI6gHB+NKd4tY6kcGypEWPOsmC/YFcjcdPusnsNTQ79G0RyZH03Disrtov8bT5OTv7G5IJT3a7g HBsw6kP2JZCbtZ0OVG6/Re0783iGXEaeNd2/m9JN1Hp3otjWh1a+k/C0dD4fzE/h4IMELqu4FAcQ Xqks8n4kUoCfsbj+wioakZneX6RcdnxeMnjpxpbnf4SiZUrqtIaJN54UomH47LHqwAe2qozkqQ20 deSsoLQKtXvXV8f1ZZnjrXyN06Dip2ASJ7J8vJ/a0zktUFfQBUvdDUn4Dxg383MKa0l591JaHMN4 DxKJYsv+ZqO2Rhtc/jCRtmiouGtDdr3EkkhkBSHcGHxgQFc2XqtAnr2x4QXr3yRWtvoAdKV0Logk BKucXK9kpfX4WvOa19+5pyeY4Q9XNJEDrYfle00xhlIuSV2nuN4xdAHSIWaFPNE0g0/EAPdd6R/3 gJ5RfL0YzLmbVtt5cRgUPkH8XdSSvIrFJ2MMycMxtdUjxpexRySUh6aUTa4CvW8SCr9Ox2G9L1Hi zudLL7mpQ5/hZfY4+iOGdzo06LCzWn1Gfzh4olNguBgxGZLLmmncovs3jwR0mYtohrPCAEm7WTd4 /JTBVXbBSqsWn4H/7h30gwLoigS2Otznopwn3hHgivWidpere3TSxUiIhBw9u78ulxfpiq5tvjim J+gywzlF2e+xX8X7VQEblCj0BTew7CLxlX07BZLARBqpUA9Ji+4rAEftjcr4hfDi86waGvfha8ZP M3/lPBo7qmyV3sLfy8ajVAsObhar3285Ax8tPYz/GEKpXYM++BORcbrl8hlOKx/xCNJ174vgxHx4 nGeiFV4MbzLCNsbB0dWd8qG1HxE9vExqAmvDT60XenHMeoqJvEhP5DkR6G6AEzIdKP04LznQvXTV uxkOcSiOKH8prgIGhsH+qHvSrgvk3KPih36SMbo4K5s7MIJ0SZzF6HiKJ0pmmfAnBH+GWyLdFYLH BK8OPVOzOMpS0UdA+Cygja16y5c9mnyjIjP+M4AF3plb6szTXgzcYb/LdhLMsTEzd0IXBwGmTS5C B1llOHHYsEArhlrGHk+RQ7OwpbuJkQGGL6//J4Op7zH86raQEwD4/hTs1k2zPotRBl75IM5xDhKk WNtimDjaHX19cf3u3nGviGdqsW5FZDj96kkEuaYKuD2BRTKrQFChZodl65PCvwInAkPemaWn5FX2 9fnau7Y6BwoEERf3hL9Cs2+ZvXacYgZkv6l3sXVALN6SbGHhTUg2AHNXOl7xAGj9VYOE3/BS4bzC irZDYKVYrUzn+EZ3XHJx1t5gAkQlXEkdbwfGk6eoS+yzS87oual1fndexLq78ba406pHKaeWeaVb RCG/TTCKed35swx8W0Av0I7IQ7rPh5TPovW22WP2FKz9PypWWFymWGRBOnjHGYNSUTzkrP8hOpUc oLN6l0z/V9DJ8Gv5DFORVIIyaP14E53QUq40gHWZ69R99uGoEUJlw6B8c7kzgo/tc+E68CSrr/U9 V0IIQeLwon/a5ye9xIxkRPJsTSasLvywZAdjlQd6C3lc3eHkcuuYblZMQhfKreKTOcMQ9Fbj9LXi r798EuKPDiAzOuht3jqpEXuPOzPdG817c2PNxEvyitn7kM/xMgx9rC0wMWzNcVBngQKwHp/iqT3M MrDBiez9u9RCbQmgxN74MYwWJEFUlmxspNV5ElOVLCf/u0ZvHVhl+au2Uj72S+4/tYvexQRktTiQ oC5mxtU1KRTAA4VVBHLmlkMffXxiHqcapPeyeHhKvughSxAWIf4zSJWS60xk8XaPu1AR+42wYLd0 wd3MdiWdE/uFTIdFWlCR5QcBEqULQmzcJ2KEUKKqcTnVJi+HrSaaVxJPOV/iFI9ghjOWQubdfZd0 JUhxHmMRwS6bb8x0HKEJkwdGlwUmmZ7GNOKpoVFrOINB7zOfYdAvR3mxfTfdoYQLASYRUy5cRvaa lRU0QoBqbFEYZDkhJC0o0eEKERSApQRYJMzqbPcp3IFlBzm1FAa9zuC7dDN0BMpd9ZXSEO4NN9SP EaSPGIsZqOIhCew4b04h1zc55Qnq8hQ+sYUZqFGVzBQFkUAaqQVzlvVnLN8WhbDr2Zo1MoC0NsMc OKNp6OLwBQ3NBeo04RiGlaVp5BIrEMVmcWLaDcU6KNKRV9CcSBnwOngFe5+jkyUqKqyhMStKbEOk tuNjL/sfyRv9zZTdW3b1dqSdmPzG/025Hdp7xf33RSy7E0FTQxh7Xu/RQldo1xFKPdQ0U02UUIns UyzpYUbM998v0kEinvGciBFzwQg/vk3V9J4OzD1vKFqS7XFYxfexZxmfhIw7u93817xjal3VBkYC k6C1N/vJXj8FAz0LHO8ClIoijiosNXAQ3sek36HbzS0wSPmDp7Uxo05N29gOW+7ZPWZ3Q0NQ5Q32 412fQrjQ30zYS4VqBeSqjjthXhGaz3WC8SkS5jKpQ/KFzs8HrCTvkgxfFx2XN+OZQ/JTvpHBaus7 Ogzp3p/4VvnnFlpA0PuGMJ0R8s4x/vXf+31fT49JkJLdQ2kJPyDIltE1E1eS9/lERpWkrrjWmRRp EP31ua/CTZbaPhtkn5+1bQrEuMxUyL8EZ4zBGjaiEbYVCbaiL+eAukCuf/i+yQ54yMIyLrOr3Ph8 t8cNwwnCAaRLRlxNcJq/psPwG/Ps3HDkeJozz+re4m039d2bJBmm4a2RYGxpWtvDnb4smguO3UkS nvWA0LmHmZzH8V3yR27uR0ZgP8qbw6iPKF3lfA+SGelIRh75EzY0sz4CeYN7USNx4eJw29ViDry0 +rWHM1l0OVKtqXA2TvN5+c6a4KuSnKKBlocFoUuYEJoL9SN12+LBDpnz/vWQDwcgGCUzMPWGMUr5 7gNq4gwHSaM8rpcLA8BZW8x44U5+CD3l2QYR+vhRP4fTu3hVtCBbxXOzwotN7/CqGS7uBS+tbo2B aY2X9ZEBzfHM4Vftu9RmoUxKVkDZF/tVdgdQMS6Y5KacXj0eDdIdfIJRzXVEZr2EGv9j+NYZsv/C d3Du76UAngOFFI/IDyap7G6XJEWa/V5C18wisGZ4UJ+ic5tH0lakP9zOHzRxfBkAVPWpKvu+H+dS 1P5Yi8F1SY4Rzsnh/QG7k53dsk/pXwc18mNF3CVDb+gAIq66e9Fk8bKmTTe8qoXbwBq6Sdy5dBcI kkvCuYEUerS6m10avfTm3HgUKZV3lgESV7auVKs7UXuys7vze8WvL8zVYvrJm9hCkU3vo3VSy7Po dOQ0lYWIiTU6cYlCLbknvxGA9/mHoFBV5VFNVlL3L3yNr8LdPwHU1QkBy5d6wj61X7tE6Yo8XbGA +HnYvLQtcuqcZEOVRGbOfxtFZXB0AMJqmsDyXtPC2a1pUWt44ZlRhIyObqhXo+lgtO9wfYkJEeqA JjWnpIM+Ca3ItX0sw7pbLL+I1PQBIo67EyojhCkc0cCABbbYGXcwLC7IRDnU2BOdmWTn72UmliO+ vmJ17UnrZU8hUIBidl+1Ex9VqL/+4NX7wIvHO9rd4+bgDhjCwdeTCjVV+Et96+qC/UMOMF+NMf6l qVkPgdYTopKA9zJqN8q3GCJe59Fte4ty/Msm4aw/JjdX2XXqftGqIu/DiPsoErsleHWp4CRfjV6n z4Go4Tf2wz6o1+ZOLD9mp5PBF7o7vM710GIVvRUpLPh8ov8VxNy0nHjTGbNqbQ0cDO5ns2ozyqEQ KjlO+xrLgq3bpQT5BzUleDeU0DKIWkL7jwbdecRrvo4pk7vcx5VLPtTQ8hZCosFs7N9ftrctUDYi wPDUbXMr5uU7Ek130Q5Y8YYfgKi9VrnGn8LuU8L+n3OQ1XG+48OcRfpE4O+Ay2vFTQdir7v2c7/q IDgy0tpKjTCnhrt0PAlYfzX4NMWTp9lE4tH4jL0wHh0gdrHWsjr/puLMm9Oxoa8oTLScUUjU61gg V0tpPYRZnP4q9GqBfJt5Ch+OpQE1fZtptuGGL7o0TYHJs3CnYiqE9m3fZQlUlBH4R9H3d7oNP+5j KB93+d6qO4mpY7/cjhBqkCWaGfL7P7mOg7ao7nqTonEpnleXwnW7JMrrlIsE1xqE03e/SaruAlKP /Y8R9iPgkqHHNEkkPBRfRkPmxBkjWYx491zh/Gp52y5xCLr3xFP2tZBeSOFAbjDbf0ZGkEsaGBhG Ci3M1Qcaz79JL3rceaWiFuHhQ1iBF23nQC6UeH5lI7dK8RYGRAxyzvV6W/4VoZvic97eAuJ1kPDy DECYXS3Hb7Gx99XMeVcJ0y6vXBgMbstx/4kiRQmbybTReCPIEACue9hU26uX3/uw3ReB/rbBW4Fw VB0TaQNc+5XX19kDoQ8DWxWl16UQwY4a/2kz4ZRmeWdY6PS/WP74RPQzqUAg0q97SzVWvvm/Cyp/ VFEhL6MmUNsRfHoig/8lM9XNDndmQ9FlThbO/VdovrfpbQwBTE2JYIAKy89jaoJeMaHMerE8FYr+ zeD4ouwrZWQxTO+DIvRnA3I/yE1Pr0lpMcVDELF65mTRVpHzPPp5ya6E8Xdw6VQOYhY5DgD6uR5z 0eYg1W02mftCb9wlxhncwdEE7t4g5uJqWTF7Gf9Yp/PFYWNC4bGb3H6oJoi491MYLrQY9fKBSIWT kOIPFEGBk6VGb4H1uJ7BnxYiJTXf8HYGfFmTxnDIyflDM83hYMp7mkgiyTJLDsBzoS9tvqNV6YQx RL8WhHrkS5clNgn3fcULm9JLzYhLvN14sC/xUQCICI0cXzbCMgrmEm5bgOkwznEb5QJ2Ua1wRQWl PfRB6gtKGW5HdAak4+5LieE5ST1eJU6+8Cygc8QAbtUSSJEGow7aUSh9ajtQ6dbSYCG1P/KXaRux uzwhh361B5rfDf9EwFTLjI4YZMAEiEBtACmsckcJ808krr2bfQdev+S8HMKUKNXC+XzGjE9jAA1d QHbjkHquQdb5v2BWY9k/E02BpsCoO/juggdIWWC46MUDHhqOBRnP5ri1T0B7ykD/80bAMvaCLDON IxoB066ZjjDMMeRjCdznV7u36RLiIc+pJTz13+hYFx9YOIWpjaQmNac3mDqVpKMiIjbvWwXD4VlB lp8Ia4dLtLOmRwLJYF7osAtv5BuLbZy20/jxYX6EnHQmqgPKiaySOapGl6z/aCO827uWm5oxHAvL 8d2BZ0xL6Eo8C2IOvVChMnseDTvzyyi28YXjVnx1l9DwUT/FtGeItpeuUsDf1HYctrcuvCp0Ehg1 WkBJ4HlsquaYRFAfAHS/KZ86lOpwwgjXIkRRTM81a+eIYC1Gl0agURIxWsbH1RO1LIRgRVWjKUD2 8QkTYiew2iWtCL2qwrCIWL4IeVp/650F5JxD8QhjNqLQy5v447a9Tlgh4qSL4jZwdKaLTYplbKly eeuHtopNIqqm0lNGgLZ+YQQcGgAegfH69U2S/i3hb35A8FiwdiKTjSw13R1KnZ+gLSCMUkuChmhK R7j+J+a++nWWlSMhz4xD01N1+MjW4RrAUKKvSikhsqBKadfK6b4i10glDyrL+Hf3d6BMzbtPjolI kswGkCDEJcYtWPyXbKwHYka+9/Ntuc2al4U78fjjdpUhlXcPHXAM3EtEafgHpxHM8Jvfiglnc3vS 4Hr/DLBjDpvxGiS5WR+Z0YLYn/4dagGorR2IUCziNOTvkkZpNKxyk+LBsp1x4tHMSXdy4UsgpTnW TnSMayh+eCy7NDWdkqtTNAPG/tFAev5Kt4e9PjyuuUpfMMPc7M8LaETrqQLN11pM8sYJnVaX8iiI pD5beLGbJlLrCAsj38A0e/JNcH0PmNsAY/lpQUOWjZgG+zFVoS6VaBVeNsNvjpbuONGzcioW2mt3 bLLI789xDIBwtOFtxdrNSs26/GNhIStnummenp06/kWxezj7XvGQEHJ9Wee3nwBl/iJew6KxkU2b vUIybHyy34lpcNNHf22T731L+emeLwX6 `protect end_protected	bsd-2-clause	0f20eda2c4d6a4fe5ee677da71f6dea9	0.921363	1.902348	false	false	false	false
Yarr/Yarr-fw	rtl/common/ctrl_regs.vhd	1	4,691	-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: Generic control register block -- # Mar 2020 -- #################################### library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.board_pkg.all; use work.version_pkg.all; entity ctrl_regs is port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- Register Outputs R/W ctrl_reg_0_o : out std_logic_vector(31 downto 0); ctrl_reg_1_o : out std_logic_vector(31 downto 0); ctrl_reg_2_o : out std_logic_vector(31 downto 0); ctrl_reg_3_o : out std_logic_vector(31 downto 0); ctrl_reg_4_o : out std_logic_vector(31 downto 0); ctrl_reg_5_o : out std_logic_vector(31 downto 0); -- Static registers RO static_reg_0_o : out std_logic_vector(31 downto 0); static_reg_1_o : out std_logic_vector(31 downto 0); static_reg_2_o : out std_logic_vector(31 downto 0); static_reg_3_o : out std_logic_vector(31 downto 0) ); end ctrl_regs; architecture behavioral of ctrl_regs is signal ctrl_reg_0 : std_logic_vector(31 downto 0); signal ctrl_reg_1 : std_logic_vector(31 downto 0); signal ctrl_reg_2 : std_logic_vector(31 downto 0); signal ctrl_reg_3 : std_logic_vector(31 downto 0); signal ctrl_reg_4 : std_logic_vector(31 downto 0); signal ctrl_reg_5 : std_logic_vector(31 downto 0); constant static_reg_0 : std_logic_vector(31 downto 0) := c_FW_VERSION; constant static_reg_1 : std_logic_vector(31 downto 0) := c_FW_IDENT; constant static_reg_2 : std_logic_vector(31 downto 0) := x"00000000"; constant static_reg_3 : std_logic_vector(31 downto 0) := x"00000000"; begin static_reg_0_o <= static_reg_0; static_reg_1_o <= static_reg_1; static_reg_2_o <= static_reg_2; static_reg_3_o <= static_reg_3; wb_stall_o <= '0'; wb_proc: process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; ctrl_reg_0_o <= (others => '0'); ctrl_reg_1_o <= (others => '0'); ctrl_reg_2_o <= (others => '0'); ctrl_reg_3_o <= (others => '0'); ctrl_reg_4_o <= (others => '0'); ctrl_reg_5_o <= (others => '0'); elsif rising_edge(wb_clk_i) then wb_ack_o <= '0'; ctrl_reg_0_o <= ctrl_reg_0; ctrl_reg_1_o <= ctrl_reg_1; ctrl_reg_2_o <= ctrl_reg_2; ctrl_reg_3_o <= ctrl_reg_3; ctrl_reg_4_o <= ctrl_reg_4; ctrl_reg_5_o <= ctrl_reg_5; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '1') then case (wb_adr_i(3 downto 0)) is when x"0" => ctrl_reg_0 <= wb_dat_i; wb_ack_o <= '1'; when x"1" => ctrl_reg_1 <= wb_dat_i; wb_ack_o <= '1'; when x"2" => ctrl_reg_2 <= wb_dat_i; wb_ack_o <= '1'; when x"3" => ctrl_reg_3 <= wb_dat_i; wb_ack_o <= '1'; when x"4" => ctrl_reg_4 <= wb_dat_i; wb_ack_o <= '1'; when x"5" => ctrl_reg_5 <= wb_dat_i; wb_ack_o <= '1'; when others => wb_ack_o <= '1'; end case; else case (wb_adr_i(3 downto 0)) is when x"0" => wb_dat_o <= ctrl_reg_0; wb_ack_o <= '1'; when x"1" => wb_dat_o <= ctrl_reg_1; wb_ack_o <= '1'; when x"2" => wb_dat_o <= ctrl_reg_2; wb_ack_o <= '1'; when x"3" => wb_dat_o <= ctrl_reg_3; wb_ack_o <= '1'; when x"4" => wb_dat_o <= ctrl_reg_4; wb_ack_o <= '1'; when x"5" => wb_dat_o <= ctrl_reg_5; wb_ack_o <= '1'; when x"6" => wb_dat_o <= static_reg_0; wb_ack_o <= '1'; when x"7" => wb_dat_o <= static_reg_1; wb_ack_o <= '1'; when x"8" => wb_dat_o <= static_reg_2; wb_ack_o <= '1'; when x"9" => wb_dat_o <= static_reg_3; wb_ack_o <= '1'; when others => wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end case; end if; end if; end if; end process wb_proc; end behavioral;	gpl-3.0	089f51d60852cfa2a369ebd2ad92d409	0.495843	2.702189	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_pf_sshft.vhd	2	20,160	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block F9G6dpNubZOdcFjJsPg4yGA/lxMn90z+RAo6UnWnrcihwIxe5JWhi9q8L+/4/oREa75Ngvk7DQVE g6seKWp+JQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Hb6FKCBzWQ4rBnYqb+vORxcIRgAfgPQbSN8Lj4sDZnZBaq8G4IMUME3iyIwZHkyV5R3ZUWNIHIu8 ksP2467Ea/TPnHKYBC/F3fuB9s6dVI0r9GzKDYvaX0DxXKppmjgeyySUYcUVoHxg0gIoMsV1inqP TgEoCyv2Sr4TUsG57mg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block dja7spovDKtAWBakQxz/0HG5ecXk+zKMJA+UKr9YFT19EqOhAPEWiV0tXQWh49QbUjFyCZjkAOeM k34qRJ9x3w/sWyFssAGNHH9WoWerts4MDiFELf8NjsYwP2rALzgiv+0xY2dVCdow0InUA394Sazd oIw9KqGCd76ynjgRALS4j1rp68O9orO9MPT8ykPXge2efg1i653lnA/5B/m7zpbcHB33yT60fuRY 3JY7odS1n0K1GM79/8QACNu4kcVQcWeexjB/ORpZeVAGmOCmERaUKwsPA1Mr77N6im6ErLeCj/Kj OeQYszXN9eQhUYtGG2MNZzU/Z3sAYQK2Y+3Dxw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 092wbQAUa+agI2J3y2F6rmVudzHXyIDhH7KN0gCknwG7HRiIQIwXopzJgIiccVKXNeFivr5Bpj9U HEZ9UA9IfNCPs4KbBUl4qczOUByImW9Fg/k0nvBDORYj0Avxl0N8j9OVZTsBddkdhEOAk/fV3D5i 2DWzzFcBB27esjY+SsQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block m56rCjBT0e8mkwtg+YvzZgfnsjkP7faUa77D0Senvq56+SYRcybQPdbj4QVKjz5fbXy8y0qINc+I Yd1z4Y3/YGMBlgL8uBe1Nb2Yea49J/Q6TB/EKhBTTahZpbrnOcHnA56SUw6H7mremtAYwq7RaY7c 0FqIfo4BnIagEv+zdsrOomp3r2Hl3kLHBCOebFCY2DtxEUrk+oQ/tXhBhUTOUTP4JwcvKI2gkhkL 8hBEWM6wHOjk9vJmHClvvaPKPhZxguxiUad0uEFsxPlYzJqp6DcckvqSQYglJX2oB4OmOJ5mMfRy dOniK41V1CMNVIi43Z/wgYyPJQbdahdxsejGeg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13184) `protect data_block u/GmWeDZqKz5KQvAKaqE9N9QKxvEfj0yIqhMgVXrpfXnTe/NvoYCsNw/hr9FKKZ3ipdB2jBJLy2o fKhOrGog+cqwT8quchYiayixd6pmzpmqo3Wl4tPou/gpfwU+auo5qza5U+1k0HzLRH7vI4WIEe6a kiCygVSQq86ij0YwyYV53aiNqFCodKUxnjAaCjQOwKa30L5oh/OG/q3/md0qLf3BqOLGCIFzSS3D uK/HKYfUgMjd04YAJtBbU7pnf+hNvYQTDZj1zo+2OcDAqaOxEBEmMW7lmIfFodkXx7cG6020t9su fJZSazJx7rD37rNxmsLGLIoCM0WB+siZv8E7+KMtRedfvFhML/RxgC+G5Z79paA84UOQVF5q4zqb 9PB5uNQmOD0w3pfodMP17o0WWZ/ulwI3KTMXipYUll+yAVobBuYY5ekoFQgSeJnVKOAPawdmpr+p K2b+mIZFrR3drXHKR6rJAHU5pNSKjGujx8NYMj2TagfZhKLTtVIBSsZE1FD8QpeNTk2OHznrtOJ1 458O69tUm6+Kz7l4zqOf7B/7jD+7saC15G+bGGowG+l5bOgI8HR+H9eHIrbIHS34dbG4X3O+fXHi 9+NB1Ofgs5/OuJmXHGaxAr6iQ5gA6+Rg4G2L1sYnWy4ZH7jsjS3c8dzTa0ytNG3K2mqr5HaxrANI RzrVt5Yn+T2kLmXmt/ctwlJZic5j2hI0wayHJTXSpi4e8lnXgDfpDqZSIt2f7gSr1BJYYQMPrgPm rx2GFaz0YezHEixsv/PeJK1LFwFF7t3TIKIRcMNNXoWbxDQCEh5fc71WAKmDd0lfzQh7NoxOyAbZ Xpa/gWaCb/VtDXnMnAcFg3odyLi5JZNpvyCV1i6TiSOuACWX9lvR6VLzjiZXXfqXASX8M1lnt2p8 2yGmRjL2aQE+KjOgNRbE/J6P8/yafr7MW2F9XeKVmvZqWNCJDGvrorZRj5/Z+RjHSXP6AQ2srGBr m6rnZfQkWXoVLM1j0D1cPvTTwOsqR6rcuzrZ/foM0guDaCpIDy8nGA+6XX9cRYYxf3Cd2Ftf6/MF b+D8Cragh+rvpsvj4EZoA8/zPsngDu2Zz2b2kTNZiurzwsCkoWI4D43l+LoU/9YsthGgYTIvSnw6 DWN8x4sWLaWLkp72nLIvWn5B+3wvWsV9pLURjF+XN8Bfuz4vG+Q07zOhnOmk6OyZJugvb1dSWSeN SxgbYZS+Q/Awrc82tKbnBoqmSToChfWRvN3zcaHABD5mTxiEYFpg45DrWGJsSIOHn1kAFmkGNPgQ kRLHpDLjn3A5xPrfOovzxJY6NO0b4/e1TXjvw0jfkwWAHCPw8d/YysSuO9EIDPV1y86w8qODBK7H UXkHuNPgT9lUxu+vXZ02Proj9RqamfYQXNFkCAotP163TtOvrBH5JX4MkjnVcWllmfcE3UvyzsqP 2MTFKyKkDj8L230KdKZtuv+bdFsBqNYFZ507bzhRmdtTW1IRl+nry4LmLIbT2mWsVOAZYPWx8qDR hITlz+f8JdqufltR8NBzTtp0y76HNshbUl1vWc3edIRYwkGSBDz2kjJw4lP8u3VcKOv70V6rL8cC TI6XfiP/pVvFAb5a4U7pRCGZ5A0G3F5ojqudJNOHW+PDwZbL27f5PJ0nCndMryE+53yGRP2gfLl6 OlGWl9fajHfHJbbsGzGkXpq3GaXYsVJcoYZr1ZXZ9D5z1SCamXLHAYs3ky6GZLDP3Z2Tn6S2qQgk Mtu/B/X4WAfDgU1bm0Wo4VbDjYY0/QxqUgwi30aYLyfkxlZ6xIc4/4UD+efq5EoWvPiIFD8fHO0z Oiy0XgHgTO9dvaXMh5+jlkjiKL3L/Pbnpfajr1OeaMYSa9jJ4bZaWEs0Ol2rc6Yo469vxGZLhJAG br1crS9xU8hJxwiesQHOhftctW6Yp9hLWu3NMnz3FVvYX/Z6XNGU0rI2N22jApsnGszNeFHZrvB0 a2PAsfOZd6oDn12dvktpvM1B/cHLz9rkmfZJtE312izxmETkUTjen9lw2IPWBLaznUCt7QFy5Xfd FH5RN2OZMPBwXhDsoncnXv3SOx2keHSokxsocQmmbEQInvGOLaiaE7yW+NPJTWVK1esDIixlHxr6 MTVPfnGI7vI7S6Q1iYjloEUw8783n1xC46R1RlBCk2X5M5g7M1SlZepTOWQqkbPOCDulm1MuGJcf dv+M9ef+ReqK20JOYSZfxmgWN/Cc0PjIgj+yjeGx4vnI3edxBixr8qoobEjxfUWvJf3aRfhfKpWQ sySgPjY3w/+24QnD4qEjxChKreGi3jyyLeuoJXShlAA3Jq4BoWLe2JlRepu4m16Ya26rmQ71Hgv0 O3NTssQzTrRFyxTmu28eF5QxJgudwJcLcErbkDuxdiLgR5p/u7cRumpC1+d+Ry4eNZ1mlJK0PTr4 zuH86v2a/ogCNQm5pA7hcNORHNA6p5kJoKYlYb+V1oHMKbOrPvhIKKLversoEp8Zs0y5Ul/e4k9/ f/APwpDvaKSGNNCDqznJMk88BpMzuME/S+UwE21W1AIwY+2N8u6tyuCsE0kaXIuY9Ho4ZUgVdLi3 Sn8s3KybUX4ciou5N4qXEc4SeYFI11yzyqpXAfkjxPCwUkOdONI9fX6lBucI9mFKSr54vFTCwm+B KOJgJPGw09v0hwqlXWPegP1LtfrLY8mvyT38ZkH44HQUxJhSO5vaWLdA+6wthgmRvaVA6KNtMObq cxY4q52whnIeMrxpjf5uZeW87TCgo/11J7yqaUFqg45cFLEDuz3+ZbpeTN0xJmwUF55CHO4Apo/u 7N+a+NCm1YXM+/IicaeoA1q5KVgoALuoeAcCYhmtrm56CeCkSLbzt9X81bkSwJF92nBJD1cacMtA Pt4Co6Ad04eBLpSMCrSLEB939JqhmWzcNZugEXLKAAWNav5aPN8SbyTQ/mwczftNp1nnqzWDMIhh fsL0eB4CRUug+lUmBFup+Lbpjk9VnRJGlqaleGb5qqG+u/rhMBZ1qM2NLxI8+VEkZuSZ+B6AkMPv Ibt+Fg+PXZOT97Rg4+mky9tXxYamSoO/I3rgxA/e5b5sb6mXJzTqF/Nr6N+7AAtXw8es4aIsj0Eg q0u65u+FAcJhCZkZKghooPFS44iwEQxCnBT/gNSBMRHuKSHQhLIBcdxoqS97Ur9lI+MzsORQLkUU hjN7nLxjnMzbnt2VsFClmsR1+Hkk5sFQJ9a3uGONalTqzblVWY5Co+Owp7Du4V0JZd4FYoWoTVxY uf7n7dqogsMLXSNztusG/y+2w7pHL2GDqvJKFTLJYjU5cKD+rn1UJQ4SObxCzE81crma90nBKVi6 aeDduOa/1ggcoYyns9MVXxnGHXCqbbtZKIZ3Qwmu0rCFsTKH2h/kcLaLXE5yJTXIoogV7g5r5Nuu CKnR6kL2ZrzQOBnGfvFIKxTGJaeYsvrAqRUDWxB/HwaOjdmps27t7zoAw8q3k/l3faoCNA9fbTpU yDgBfoC1Ovtym6JK0DCkvJotPORZxR91RZceL5ZW1giyjHImwJzkGcXStXp2w8ViXNgGM+x5Ggpo nS3SvpA2hrv494KlcxjwrPLIDWsc/oog4G+UA/iAx9HpjkfMb3yOlsRrgDdSFEykKJqu/0fpVKRK G8BXMVWbuinThYwwT3FOvkAuM/AaEjSt3E+P1xISXLussy992ezlemR7z1yQeWEwmpOYuODA+wyV HQK6ZrX6V4xrlzOTRBujSci8mpIBmUwbsxXVENHHUXtqV2ZJZy63aftKeSbpMDP/+Om5CNkcyG+N KhF5rAtmgJImJ/6+9FpMTmYkOMlcgxFOTx03Pm7moJSrXgqrgsQy9SBQ6qC56lYKceW+D2BHtoZs kuDA1+ib5jNz3FmGhrakJQrFbUeu9dP4/PocIrjpdsqpu8LCj9W3bmu0l1XC7yriRhO5awSeFZno ijDAh+8yXsd0TiyW+wfnCaGVC4PRgtfuAZuTuldamfp+wD3yqL+M0ci/rwmvbsjai10U12ErlyA6 oJ9lAQ9UBsfIhOYHPhq5mQyRfruxn97/s3abIz/259dl+/4r4z++28FtfreXCKDj8DSfrs6wD6Ak iDXBuHcvDLqYdSzRaIqb052nb1yVScO+2m71LJ2yjm973qysP0Q47hdLG1qBTD5eM2r64MxOLKsq GXuKROO/m5u/FYY2fxqsMxrA3coX+N603N3MLse1p/CXONaboT+Y2bE1ZHPXOt/vXJd0fyrnuYNL pRICV2wWAhPtbfa5h5w+hMZW4ImRw2ZLXQnWB2Thh9kJqkFxYNL5nP7NtesIyLmCOvUXmmuDxE04 viUvwsLdpJKHGYbVBxQVjVzxkegkTA+joIjDK/6jBc93byL0CDmcmE2f+FI3A1jfxcy0bpGqy3v+ PBppXYREYz3Tps9TZL7I2JJbp0Hy+//yPD8K5DRfhXpQuoAH/CMyK9nGeQ/6gzNyZRsccAqlMU2l jmlMt6GyXcbMOiF9BTXpzhuzHo/VTACxfS6u2t0BsPSbtr4a3gpbivJLOroGhS9RtVwpe19KLgYU Q1o6Rx/2zNWa8woUqNJNsAs8DBLLPHRtTJwTH+lBc/f4Rm0GRNziPwJ93R6bB7Qji1WUvtR6uw7+ +wHjE9i4NnIdMM+CZG37V7hTTbRH4uxmaa9zCKi2xFmzRQG/RxSjCsY9bejcBwln5WZW+8gtrXfc pita5wSEyElkdRaARY5OLlBrfSaaA7/V6MpoGbSNHZ9FkfM7BR7c7Drye8Ig6N+ZWUtE4L5OD4mI NK5XvzoKecE8gg/v/PehZLYDDUKXUu0uX0E7Qq886TA0qxOhPJWSK/aWX/RLfDr5XHreko64hLd3 SQiqPLO1AhJ5b/uXQHc8qRIaSAWsjZgdS+juAb9YxGwCETZNe166G8MtaQCGzqWdXcKz8ZPZuy5N 9cEkuo255LuKjdG+9iJA+DYzRq4pwq2HQJ+9vO8qvt7INWr7jgRubagMvOGCH9zWBT7Fqk76HzQC 7QgKdypbNl3xTC2x0pptnWJFiYEGV5JvHyusovIrBknWuD3MNCsmJnepiRlrcdbt2rs6b+4dU2lm E0mHWfhbY7j2QChhTyg0PZkVjsJXz4clTLTgtnufJ7AmEubabyGEsV63kDO6n/Vh1ZF5LBhAAgPP tzkOlGau+3lIVhHWcbet2CKA0lknla48W78EjM8kZCNffCvpPk7T20NzaJ8xp5OVHn662j5r9ErS 3mp4mqTHqHY7k/QJwQBQM9+QKWX4uWBS8cxvDc7wdtQdhrD48FfMrHOoM998YhpG0MvH2341dPT6 LHwmF3ez62JtVl1wsqauX1Ob3PqafFKOf/J+Wg6y98o7w2ZsLaeNXOnHtmq+YZBmq3Db1J49OXMF VF+wIRxpZ9zQncsRsTMsCPJFL9PgR3zYueitWv3jq5eAGqiCA7qPPAB9MxB16NfRy7pf67JrS5K9 TnCSJDYhLe7NKM7RPyq7hm4lxnnefqexp7LbNpVgMKO2XJkxU5hJv8wvPyF5+qefQQYJzYXdRX9t DDcDowpqtSWbruwGcEqcWZ3uFwJpFYGI0OmsSpl9XOWktA5T5Cf5Gjsdbt7iu5B+vE6AoRRsW0ro XnLjvnz9rvRVNlUSp0zbSNZaepxYmnyaovc8ZRfrhxLIsN+SA8uvY6hI7Qyze2asO3wxAYbNls2y +X8TJnLFT31azHexDc8r4n14wZX0jxmZn9RIe6EYKg2TmZODTMspAjrMsXrby4drXLNrSF22sD9W VzNeeywXkHFa3EPA2llcAeJjwxVw3KgyU6ErcSDTZTw8eroa0ErIXZ0emyey+1OQfnntmcqexf8l yzMTMPsxI0GeH25FzNEx4RWx/xZCAZJWfjiCnz5us1egrD/JOzoKsWwQU9kq8ii66OPGQyH5o5lr taH/Q7AUyWICoTMSfy7/7BNSXCzzdnrNJ8UmpQH3RnjNydvinEgdcnR9ctq7rwNg42G+WULJGgNv 9q56Hy+otdJ1sGGIMTE+cDbSBCo9lqTnDPwStk3zhkUaEAbyEuDf3eeP5oG5kqBTl10bsPALfBRA 7czuLGVOEcB0knEgBj/prGYfzyEsxhMmt6FLDACajtw1WReK/OBeE3sIipdIgrSIZFTMczMAD/Qp MjlezmWc65gmWP4Gi/Ofnp0uYIsR5VrhgO+hMhkEg5420Qm5DHIdfw+cxASythoZLJrMpgwnmpPh G3k0F29Kg7XeHK+8Ln/hHS0wN+fVYUEtqOzTMwCWZDo5/4Q9IZ+y0chCC2wWKa1cSUo3GUcz0K2t BDZQe8ZW4WYKKpXoeNT4763wGdGrfikVOVkRKAPlY06Qw0yXVXTB2hbsvzu0SitLLNdcp7gaASAN KGeaD7Fq1QgsoBwVoLeQdIRZX1nFwEKAv9PYnQ1MBHMwslOuhSgh7C/3X5kVWuBQ8D3i+XRIPA5c 4nsU0TlZFI10Ew04dOzE6bdJwERPFtDOt9t72q3/z86gTM2UvcqXO1TPliqVEP3dNlTptCYIjcSF cVcWxpCPVBTfYm4LqsZal+BuRCV8LaBPbYSIbEMzcIBGaFY3hB3yDQMbPfiOY0u6zpQOe05QZBkl IA4psfmjgSchg45Wpb+G/oQpFh0nwdXIykD5oKxbl5TuiADLJ445OLg0k9Cp89vdZefIzBf3Yd09 0CidL743JqsDjSli+7tAwoHZxMnzXzMC7qV/9/lTCYztXwz2sHvJc8pdO7Mms5vcv7rpSg8W73uh 3L73D1UUqjlkRGjX9SgFBz8Q/RGAXgUs5DbonOjM46JZgzrA/V9pxpoQtU7dSJ/gqTTDFxWUzqTz 9O70lUKbWWZ9WW9qkcYV0NrG0rwA4LbedS1TAlHehsj1agzi26ioe6mHcFqXB93EcytRvqmRaJYu shbEIcnc9Qf36CwiHJK0Dyy9Tl3zy8LPmozOR0zwsZFVUI44SWnj+u0JEi7pi7SQa5q4c8j4IRns 70Npu3zBags2y6SEqaJpXgshOuXujaHU+GYZIydKf7qzLaPcPMLM5vy0ShKQRHcRrzl12IuxgeDS MC34mVzQHNNCMJCmF+uJyrnnwqjDzbivvlquCIWjC/Qwyc355SZiveU8syqmz7ccZNeJsV8tgAt4 UiAywgoy6JBJnZ8SRF1cDVHExWrqcpE/5m4aU6lTsWWGK7zUEFYzmqmmkiNCjJEgDT1youaeXhX6 +X7j3zf8GbvoPvNLHRAOLhJf0eLp/QPeJhz66/QJ5rVEOg3N6ssbN6gexK62x1euxEOSiq+Ewhzb myywpgNBDeSspBLQhUahz/EKBG9GHoCWyStkMiEnIN/b4xKfE0Ryszm+tF6Bt09h7DU54yGUXYV8 +AKEU40Db6fnzoaWKpCcmEPI7KkOoDrfq/MzfwHF7jLGVhGC1nGBLyyEAeayztJE/vnRW78kgVFe pHsPVEThLTqdODZ5vgwlBWEoqRA9emwApJYJ5s4v2Zjf5+ggB9aVZEecoSbXlSrGoLh7ef8zqXo8 z9f26uPFJVRIyZtVr1uWWxQA1i53ah8n6orjyn0fZ3JbABmDKKGzMXBcZQqiQJH0hojxed8RwhXG FQ9PrBaJp4o1OBOW1Yafw1FE4xwWrH+vPdd+eJEl2xsuRXVm6hDTQ4wth+P8Bi864KQsDrs6YlrR 3tIKgyQtGyifXqGYH+7mKiorrj25qKixWMvEYVK05rUIjnSOjpkyeiLrrtYgy1U4ACog+qgFXVk/ ZSZ/uLSIL4zwS4bKwfR+KSVJ76h4nAfvCcEVuxeADR373X98io5CjMUrSs45pI6kwlQVZaTj7kZe Bma6xtDQ73cgRMoQ2PgJ9Rw7pqNA9kUa6AmIMkUo01yN94LJw/f2I6fxxl+vjbsX0jv3sdPQwWAD vmEl4DGRpaPs7izAbkSk/453f54A7vmI1pccff/sx+mGirGpeEQyx9XZf2mOJxI9hrg4zsrDgSZ7 UPxziiAvM+5PxuvH7Pag8OsizGAKnMODzQVyUnbiwGRDJ0KeBYZDO0UWvcu9XVd1o7Pstyer0IFs 3b95z1Qr2gLD90mIPDm0174wmz/fLHD7adFkJrzIbShVMlJjgXpCHd6WKUtO/ySkIMJJ7u2SNNR1 JifadZ0UDCIsIjuhL6GWKwmNqQEiHSe+1nU8NGQibPacskYLgS2vf1fwioMCWU6a8aIeAM84oMrj kZlpGC0JFXyTbOx405SX3YLGzELXU1VpRgLLPLTWLfnTwziNgSQAa1fSrh6Li786qYM7iv+B7f0J dQ1HXgeBnlKYjAtQB5MNpnVf0qrig7a1wFKI+aReHPVBHTXnIlzVo3VYzXqtp9FNwKsN/H8k7GWc x4+UfkL92h/2ip4m6jDJWUlcytO+HECr4xqzI0hTBa1ReAyjP/BTWcPgDLXFPIDl0fWW38b9rXOR c4KObHJG/Zj85SLfpO9aZDOCVVdCiCcPvNFkW79O/pdFk7ee0s8ijySdFPWdRycJKUZRmx36HFax NYqOULENvIF8+UW3ESdmUv7CmCieP/VKBgRTX0YOyd+YMClCcLFRhBjqmM5FMeQDPvxql/s8+h40 Dt1uZlD1pQMvNwjSM+P02b3AopoRIX1EQ6tpCEdPqopvxJTSHHqHo26iP6jO064ohbows8y3T3he FarT+kHbitzikAEhiz1zSSsjSUWsY6vlwa3MPMLwPRN64gDVFJLrbI9fLrNy2o2q0sPg52kURns9 AGYOPZevIqCOV3q1x3UbLsoH0S7RsETPJgjMZDvf0W8gmdiuOdBk04AkiW4YwVjdFMfuklVGBriv h0zcaLSBew7wUaDaKdMuDOo6vGnBauGQF4Bpa7KWx4EX+JvDjyALFT+W6Lc6WbAbEPxL+lNIUZC3 U0ADQOG4FeJEUzX7v0UfufomH9skn14NpGRlcYJHyIDzEsyB3qaxPJHTmtPWlBEUftW3zDdz8dBn 7TadTdpDVRnhHVbnz1gL0bO7+VaPLF5hiUTs6lm0NgU+cBkPk/l3taAX35DWiRw9mbjcFLYFCZup 0K3J8BwQgNnLtF0tNaMl6BFtsycLe9G8qMRbqBE0wzrM8JYjA+gNJSgz7PFF2K+rnUdPiQyOgD1m Gp400QXkul+rD9yJ7/6pwJksJEw0xqoKeb/X564yShplrMbFwp6KkPVcYbUwGJMJ6PchSCuFOBO2 cZNWJuE0ZoTBRKgN5pVfsyBYsZOvSnD4LSVyPCDkF0A+ELW/Z/SH6IGCX6EDoV8YYlcbuTM4xk/q FG6WlzKBNvYjexv7JpArDy6qiNk5Unidkl684OzqvGg3JHVA+GU6kAY+V8W5vtx9TdZFn95+N9GZ aI4fmbOfialgrGPuTd22Z7m7v5Zjqy3tnUYPvj08KZS+vKV8xE6b+LPH8KRWvF4TrFCQLU759uXP 6rqime0AoHHYmcfoYFXX2JNcLBae2lKTjurzXiTqIeQIG9TLQsw6tfVwnlC3v+FdYXm+LUVdJL8h 5cC/sueK5ECxFjoQE4WK+VXNSlrTjyPeCZ+/kZ8WBsxO9/yPS8anHnS+QoTl8kj/Q9AMBLZ25Qi2 4zE7pBWQHQIxKEj2jh7yfi/i/5oYhQk6xm/DICSIngmJzJTRV1YJJevrcUQDyjY70bvAaVI7vUtP g8iNBY8+KCzOwDEidNYwA+Fe3E3qSwV56hzOlm/8yQezksArvk2yoO3vBwb0xD2972HW/87vy6YS He6UicsSvg1s90Mk0NN7vpyOQAIQZ3Z8Yz091w6K4Z0R5d95rtXqLqeLExudWJtDng0j2kje4ok6 0c7dGERw2vJJ3tVKtwycuR80erRgjiiAnwXalhO6tzNMs0TZhJOONO5Tx66d6a+aAgSsGLV1/bzm Lmwk4fwiFOImKXizY8hHI9n87YYEbj0OCmL8pKYI51nzN8Tw5A38d4D1CDrw70cuICxX5I3LezW0 j1vtyEysHQcR1DE2SrOqKiOO9IWT26ANYak48AuB56XwpiJU0USW84PSG9KVg8/sEMX2YKejT+tp 1Hs9EqIUKxApmkIezBxYFd9ZarfevpOBNbv4TwiwRaGwAyNSjoZMvIGgUgFpyy+yR3cSX0UMcL4g o6xWKT/vvagMLObWX2iU4gbHtkh0PpXT5rdsNyiTRMXIbfVcLluCwjS2V1ALVOjOudH2QJDe6VL5 NWuC+Mt9Eo6hFIiSkyb7FBbOYzKYVIfAsSCoJqlSrKP7o7rDM+5DO+1f21LEUG2BBMJzajUBNspT 2N5p0vRiD8B2rCc0IpCLEAJhaQekU6MmRp6dTnf8BYowb34Mqw0SY8IuQYn/4o9yaJZHBWH3baQZ w3SeJaay/MvwKxHkNF8bONDk7fGtmgeF7hyq0Abb8U1MH6RUbCiqtCM1UEu0vNWIb1V9IAGoAYQ3 o5o4kgT+Qw2xooxN2z1m/IFrLo6qm8gKo4D5a77Zx1c5mxo9RldYheXnHdOJ8qZbgY3du/FK4HQX h6/aD/9hMmOklQW52AbKPmFmRgPF8c+RPZLsHy8fr65d9kJi4j0sj353IHZMod/x1j9jxBUukxbz V3kmFQjRxlDIlcOqY6wJAfgrUpK54S+0Hubfa6ZXMicjy5WPMVuZAaqyVa8YJaDcjU3d/rn8Y96W JF/MAKx34bdvGy4In/C1iHQOILhNWNw3r2hC8oUmU/c4qzCUgmfRK/W2THkPB2WpSGbKbmAS1luH Yz5cZYyTEmqwGx2e36GyCpmF/6igrTEFM9rxnQzknm2X3y0/WLLamIJFy0ceF4nk0y0BHSDMLMrm 1bOm+9itwPzkgkc+fPZFacpHnMdGecko9O/tiK16M1kezTCJbdSpJLC72CPqhhVLMQROpk0EobDY hSYeSz2k7johAEsAoG8Le4t/aQ6PV4cxUL/MJflDleCuJYx/Wyu9o0UqvJqUG4moOiHsQcYc35qm 0OMWvW0WL4sTNRWfbyFwG5h/84pzANgCwiBEw/lgtzzA8p8P/Wo6gBgC4iPafe2fwa3FKi8W9Bgv w12oIuBvLDFsapyZ0UU9+hqACCkbooJFKgr1C6q+UhTpSRIPMc6eWZ50rO/8Rd4PQzFqTQtKfC7E UiAyaOIok3EGaV6sLt/tXoiqjee0cVP29SPhebloiWtHhPrPgsvJhj+G3hBZLqqjD5ctH0O0Wtx7 09rtRZfGu5LZ08XMh8BxENnD64by1xrak42lCXJtPZaQk4WvKGfpSmwUKABh0jvcyDQcRH/hLAmn R5hCVU2uDmwzuOsnJSK8U89cUUJ2kURpv9u/UCzHtBwcR1wIx3V0sDgxhAJomZX0Y0xkYO6Uzd9k 7gfU4Eci68wXe1QkaxXBFTuD7dXu61FR6Bid+YYHi5qk6BiHpKfosyz3kVzZFMKK5rOdFCikL19N cFLoVBgwg+YaVUf3CWtDSnDpVdZuWh4WqXlsNiJoGmP4CWbhaXwmvF046FABLLv3jRWhTlsfeDf4 9SJ4FeFCSYwQk3KaaDBLAWVGFw/Q0g0LweEw2qn1KXKSiHWYrWNOzOcVl2fNHIU9uDquh34uDJnS 8GYslg1tr98NcpalIPfgpg6zw/69IKOXBrx8HVqkN6lNa0RvYdTquEY3oLEGxs4xZPU6oWM/Egqd VDvZ0Wg9vPCdeXyHeg+WFEw+hZd04w0+wLWKdDOF09IhfMkAYG28/IoaRFFLJ3YPpNwjFMAH0st5 8f4jCfb3cLBqyCoyELAbo/eD5GJ8cZJZwEU7jz6A0BFwugn0k2701xQYz+Rma2HMKE0moUAu4O7m poXyFjqI6x8YtWu22NRt13uI6H5r4SlexMIaveuv04p7/uofdVDcmdXDbdFDISldaK+jxgxvlmpL BZVQJhoMLS5o7DY8M1lPjzVXwGicN9nHJkz/DOrlxzz60s2oNT1CfSWeaFHhct4F1Wtx8E7hdazB Hmg6LaDhTahGIkypeYZHvkQbB8QuwQvj4KHIJxxqxhlui6LJcKYRT0uOlYNrQn7Nc/0vjLicplp0 Buej9Nw5ubfxeO6XZ3eS7BjtdqbpsuGmYeV3cD2DiAvSsMCQhYctAaCF28rYWUpi1wUpICYN6m/Z 8iRWwIROMVk5m8/8Yv7wHsCPnEmEb4IwFdIFa/QFZDpsIS+WSk8eq6aNTsq+cnM30nOiX3ITBgj2 VAZ+GlwNHzUieDbb6GkIlUPnwPjevbbm2cgR+msW4mNXVrSdoMQT5jx/adjc5798Gelxk81laNO1 QF+CVebCEcbe9giWseWidBkrCLK3qqdhrAVJ8lYW6fc/lY+O3IjNRVxbFaBXComBK59rDC6S/3WT direBeqqGJc3ZtvlMvBqzJj5uAOGksnxuJnBGrOpE+IbiUwo0p3fq6hPUgQ17VBAYC1mLwpP+Hce kdaifkuHtJ8St8dgjtAiMvAmZv6RRByKf5mv+Hp0/tz8G5hZ8hCOsyCiDoTZWPcmvTBxz49q+zEb tYpY1LdJSA1w2nkVbUm8/ecf4GQYUYqzpdEp2VtFxwMyaqHZcXiQxxI8JKdOCU3YeuBeQyzwkYXf FQR4l19XOIXQLEv1xpgJPwvba+o6YYJd/Cka38/BL2dQWOIV4vRWZWT8hiiCGw8gStoJz0sICz8t kO5ZUlIrpCecdW5ocufG6ak7ne+BG9jYQ0nfbRpO4eaT9UKCMqQzML2rtrKmWm+/6dh4B5jBB6zV 4mblsKtkq4XP9imaaFxTLdkqXl8v+4Z9O1FpuHrHfbXFn/nrFKnQuqunQLmEgCYB4xdX2VEJPrdw yGQ0Jn1qEZNqhxh7dsJFdm5rWAPB0fX545CCxwDW59lmwoOWYv07CIRmtAqFiO26r+4dMXVoz02L dSrdti06Rn1kvbQaoZNaqWMpzewm6BLHB9L8Wr4pBtO1GG+3xMGT3u0MjfFTfhYWzMkUOEAtgk7s 35CNBquFX3vScharPSUYpzyO8rsv1muQGdjJoPRhup7cG2zJV1BMyf1cmCBNTKE70Y6HTaNPsrLb S9J38gU1d9nqq2tmii3prcBOn6Rvf++9fZVKV9UwUxKSKiU7U1UCLnuNm+gwBzICzjltmlu/kqTg 8T8sTtMZZdAXrSgsd9O2YZGDDtLdacuFs7pzlJ+kUT6QPn6IcC3+xUQagB0XiltdZyXA7wnvfO4u ICRybXJvJKaGSruTxhsSe3DSBQh6WmK3EwmO8RcLRMmQOJLbLR8+LUVgyjg+OlhNXzwwnqwcRCov 4phqnWok0vtXeh8PT4NGUbpceEbWuuJdsZPUUV5RjawNP53lVHOSwG14195ckFWMEC/zsG2fMAEc hLCwPqSPzht18zWLKCaasfoDkmBF67nPQ6HNUmg8I8aXYmcKSNVuwYzBrLA3NTMbo1mz7xOSu7QD wQ1XCD+m12aigD3Zg4zrgxf31mzWgwfuR/LKsYlT/2ukiQm1I2+XV6fC3ypZR2MNBHpPBeLUVSuB OzpkDC2Vv1E+UdQ79ggtAvemyochjwgW+6VdXTelAmrx2vAUaIfNXzaJTJt4JVSMgZ8+I/0Ho2Hz 3TKUH/DU6Hmtbw5GD+COYazRDVu+YcAEHzlmkQJcWh2PDMkMdSTsb7ui96aV1lo54SLWy6hs3E1p a3LJDwSfoSSK0YU8lUk/PBMkDVKoT9QUvbEB1Fav19gMxgCQLOB0p3ArExGBKQb3xQxcRF2k3zKr gECa7Ja6OmTcFwLugVb4KvUv2z4IMeNc/ZtFAjajtVZWLXOI4ELG4SQyfGqWPsWcu6PM8U+Q84NL +nowp+ALrtk7+DXD4A97S3+C2v9xVoJdUNWR84qs6hYYsIygJBShSHTZDypdCrNAY9RfHgC8gDQg dw7WvApC2+ykqlEYI8xvrkHkQ5aRg6zSq/4GmgWZIRWhTkNgJ/CtRDumvfL8tAG66Z7zSGJNqf0S sgT8bzuKHIzjeOnQJ0nDl/lefs0XUcYxr9ZycVFjgLOEngsMtViHMrzZgxXR9AiTqM9yxZ0q9Lc2 IFwvrowCHWPPptqAltmfwi++6j1IiYqUnpGzX/QKnh5L9JGCDZaUHbFwovX8OglYI8iRm2oJIV8+ w53Oj4+xiSyVNVK6+1uK7LFB6s/59AktF1QxxMxddZurI+a+bEpNX9W7sfndst2iyMJzwcbUWT/u Hi6C6oPiRNXm3hYqGWGnWyfARdxeRnE5J9m9m2fwg7QxPvrTnAk0CDGTCmIZTs2GekrQ2WuOlf1/ L1OmvW0TD9Si5Qn/TX6oB905YaCkVJzcTS54pnf3AeqBuVEVBe8FvlJJwEv8hKLX8HJ2xRbEXjRo 4Ng7Upr2bJPG/SXtpwCbHO7iPqr5OwyHZtUgt+Fw/0DUIPjC2DKNkmiUOOzwsF0YHNpOqFwScuKr N2LU6eXWPejgNO4yIF2w8fF2CugjKoDeIGySQXcwK9FsM5hxZ8yVyMNIk98Jhrhlprg39pxh8Lxf QUE4AJ9/3ZUwxBHlMVMHfw+pw2ya0ntIauzyrhEnffD4uEV3vhuONnZEG8XXfe08SVw4aQs4b13h NFHbUJItj3CTFyfMVG/9mym8w590l76Feyz6x8qEWBolZsCqmKaT9T0rvnjdijCUvbqkgsI8tP68 JPwv54+Zjp1OIVKHT5dW0KS29fjoiUMP3n75sWUtWzBcmbEY1ATU2XOB3wvv935saUZeWbUDUI93 7AMd6bHBS74qVP9rSLzGSWOESw6HJb+FEbcx8/0juAgBIPFffozdfkDrydYq6EK9S0+lgrCzu0Vi KuxQ226jIl9bC22pRddn6Y+v8EH2sbjB4ioYkWtwtSaZBSQ5w8wbc7SOZ4fcftSaFVyf9H2/HVq8 YmiRcHo1sBW7KTr9fFMlqOmdpPfBjvB5cBvaNKxcUSR7iXzYmYSyulvSYylthBNITTdmD/O+wREK N2rZt0Mu9cuo0ZE8EQFxdeqm3ghDLj7so7x4xdHSJ0nUn3CuO7h9ebHUeOymm+UHUCIS1Y//+2p6 ylFrt4HP9wCnHHvRUKFiwfTDd3yLsXH9UVoyxBPR/aKFw8RLpFZeLXvzTLlu7NtJJK88AldP8mF6 PUIW85stpJ94cBljEstOglYMwSLHGYveX/GyaHM/7UO/Pcy3sVb08ELqUnyzJVaA3LmmRQCpsYXP HzdVlP5xMHco0gHDdAQbkfch6/MoRk5n3a4m19JfE8uyAcNeD97QLMu4HpFcDaqhvAC/w5A6xl2D Hn2uwNzTz0E/MVBjo+4I5v2QJFzVFSkefKtJiz1NUHEKwEDu6fxUfCpybQUMQivpg9hPPIw/XX/B zxA9Z5hdtdehspw2ovO+6kXJwdJd/6urOKeGpiINz0/QFiTGv5XHoP7QlD4ankSxzChjMeUgNY6p u2UiLgg3f3DYWUX14Sj4ejfOhWsCxbNSVPGZcNI+NIMo4YyRZaUs4hakUm7IkSzhal38/zXpxGrb /jZ8DrSKL0EONe//sZhOut424R5TKSAXLrulMCApE7x3gN8wRT8NhLHGF3i7tUQkalHtPglzFd8y HGys55Bt5bpBBJfP/RAUnvL2ZYKwEzWcpPOdgnDL0ZXDMFaZd5z9LfmiLkPETN1Ql/xfJlpB7wm9 9Z1EqsIBvwhB25jG9T7DFXLhlrJTrD134ExoArwGua5AQiJFyhySH1O1u6ZbpJfgw9p1iv5Qjk6Z RYoqnne9kFhHyP7/Aorx0lHkwvHBFpYY0/cpny3fkZr9U5OCV5k38kx46NNTfgijyfjesJPESVJv dH2dBCNBUoGQSg0ngy0rg2B7+esGfspDQ0LHsSQ+v0i+MNXNrgmYxI1QhYYAOS7aL8+/9LlbgQ29 hsZfhJR2umHysypKqfZyhC8vG39jOwr7Q8vHrgPkieiY5Nja+13vXnmppSM03L1L3rlC1uWSnGN1 vqpiFap5vyFZWnhrLOeBCilR2bjVGXDHaY9pmvTV00hoT2AKg+2jtV/9e15VlZrl+/dmy5EBDtWm 1npbajuwivjsScKngya0FxeLL1XOUtctE9o8LrRhezuplysQJehlVLTTZBZxaY580e1n7Jmduhw9 snIP8ZWgyRUCBsk/76xnDZf0clV10dsQb2r92FK/ldmLx2nhexD0iteekRsVXDDm5hHwzrp4Ksij 8tFwwB36t6luKRwlKmnknSOazLy/c+pN5I6DZFZrv/dmDd1OaWBgB8ZNOdCP2VznxqEoXCCvLGzL FqLcaj7MF9viWIZ9EHDKexGG901D2X0LHYPKA3gwpOKk7oymNdCuUNfrQXUE8Z10Hnvq4urOwyJX 3uX3qdGPSieEtZ0Pbi3WCYh4jbP/4/I9KVRO2ndQlF49c7PEa1XPDbUlPWbIQaDFAsgZB8xY45L7 +agevoIBb6pGanLs7+Sn6uVbCpgv32DsC/wFw7KL76Yyt+nf0IWiCz89GsYlztQlK3tWRGDp5bGX 0Rv+9kfueBk/dGPqSLjnnIGYgmHUscUAusY/OGBkf1vLcFqNjH8bjw+pICbt2At5RiTkXIScU95j cLoSIpdULJ5mNZB+YXEm3AaXsVutJgkmfyBR204ID1xpkiofyP0aux/UMsy2xc0SPHo2EjKVZxof sacGGf8OYmnOdLxPTyijBkHwdDeMRTxzo9gpVEjU8t1lUyscd2OBMdMuIvZnFtvooTzeuyDW9/ya 7JsOxnr9Fw1FfjY1JoNXyl+XFCY3OOAd+n1I/Q5nWIm1oPj2m6B/c9cQhEt4lL096dPwZ5aN9cBw urVfSvUl2ZFiTwi1K69ky0QS82Tjw3kqmMKcDZJ2wLbGVPD8BQkUMqjMV5X6Kx+9n8uh/Yw/BwDj IZV/y9zSWKXlzu+s535bxmjRLpgEG1YWRPb+gpn14/vmQ4Q/t/bM8a600UkZ8kNwtSxIWNwEzRnR lKyoTSi4iO8qkg1k5hLvkJSkR+h992dwUfzblZkcWh/pV2Wvpo9KVEG1gduuzVrGzDIHJmbXUX8R E0qGCYh2BrHgruvxCgbREFuHr9R76ZJAivvUAZBrdigWJxEjewWo4vv0U1FAr8mANRc0t/9s+k1k CArhDoqyifDhtQx43qoCT0lnDxYjti3fg0THMPw/urnuyIhsNuELpu8yejALvAbi+s2J2AW7y+xg BDk4qiheuKdcuk9F2XMbaOaLmv7RNvH5lnSzg4A6xckF/bV/F/OSjvh589/t6gyxYbMno9ovwcT0 cj4CttFGkk3hHTKLsKFG8/mG/I8UatvKWAraOx0FWvjsNXNFoCvwVK7kD+usJu6wXevfdEQOBWlk gbE/pw86mvoMkkLP8sJU2NB5yl2xYQI5V9KVWVm77r9rUfpWrFRlnXm99lbZNmR3J8lG81sf5Rtj ruik0oUQUQXhyS8jP2PUCH7scv0UYOunZAArgRpu5snHZ9Mns3umECqKDuBQdTX/NHW2kpY7i/2d Y2I41ZhP/9as5ojauoFxhR82J5beKS4JxmYaU5uDKQFRWi8ltdQLtg9Ion3Gi4S7sXOkOmMGod2y yfdpM3OqS9ikaAKDMbNXxP2a/VxAo+/UKOr6503oSExYoHFOa5j8nMNJV2aBiuXVbO42YmLelTNv AnYQzN7vAoGMGo6rznuw+Xw= `protect end_protected	bsd-2-clause	248f247d3b878d148bc1e9b03f527a5e	0.940526	1.844634	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_status_flags_as.vhd	2	20,484	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block j3zaIMoArA6XWIHFomLzKtuq+Rb2F+tSmSFNGOdieWSUzjbLz+u6uPRcJXllL3MZUcvj/uKaOaj9 u0SOi73LHg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block g7IZF/95wRkFGSInsPOZyO5sMJ+VrRPeMk1Blgwfu4W37IyfwU0wC36/2/yub4KiFF/mdlx0TSKw EP08DLOpASSW8nblpF3eaw5WYMK2tUbVB83MbVhLDWJels5RU8ZtvQfpnN0wg00PGoyqKcQg7dn/ S7LnJCwhTtwOdibkn5s= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block xmiZu2CEeySwoJ3exH5beHvjFkdMUHC19GZhVMYdsBJyF38vUIt0PBnEtKgKuBh5L+hXPBv2Bcn1 45xYL3IW0hXv958NMBfrydbbKdc2V5H+Ip2BMijbMmj4f0PSSHCW3t0h2wzGdS0vSoSjMFn3SO/c rikEVE2WW4wfYs7cMlqZ/goswvusBIMezls8gbIbmNnpIDHO0aO/G/ocW8F3kp6/KXOfPXb2820V XypCJJs3iOV3sTAND1i1KRya1mele0sf2kv12wl7H1TvodOCeTJifnRqXa/55LwWMyY4NidqG0PF KngAInxyZiv0msQB1uX2uSZkkKVIEXcihXizdQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Oah7MQQWFuso1UfVI6+06ZBzaeEbWnOVzKjCf90BmtDRoim1EcmTxmf6hL8yEVrH9aAwxN9vmIuP F62f8Bpc87xfwvhNIlkJ8s4A3iSTXSE/1VZCnHsWySS6x4MoRD+OzKSLhjeKseLd4u8saYd27BJf pEKEznWpli0c+mVIZHQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Sw7LWGzZeGjtXHY0gWzJ1mNcwX4GVGKCG+T+cIhzI1JlvGataZiKJyIuPKjVEIdeL9nYSKlx5wsJ i2DKKxZbU/fxwcsOz/E3bwzmqQvxJi9hcQKnr8RsUuvalRtHMEAxzbxzTybENpYFBMHSozYUbdKw DlTn8aZGPWxK0551Cgh8ArsXmMslGjui+tBH40wHVxyj5AgeeWlOTKlmTWBsOgrv/NZs4d6sWOqP TTbQdeJfbAc58yTmfXvyOzWwnI4yyRyXzgDKdoIl2Dpm1rxTn5wb/KBu/pGkHNK6uCI2CWEsmPF4 LN0B3nuSzZt7dZQ8UrbH2+hv43qyDw3cqqQsJA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13424) `protect data_block zlDtPbjsW8z3LlFkU6lypKe10hRjpTnxsOYfxmOk8oqaX8MMtzWBLLgZuHe8ICCaPrTFOoiPWaOL vffcQ6GzaS8XqSNfx/AKWlF+JwOkx8ATXtLHIWMY6q46/WRfu7cLIMB0Ew/MSn26K3Hd2pcGsSdj sMRl7zyGG3+oeSwx9uM4OFmvpC0/OvBCqPFER+41dApe87hRk6atBP2b0a4WqojqQvQ54CtoDukZ gJGCIhxJX3PsMuBMX7ilefaNjtFvU2HLHj7xbu8qyHfeic6AJLY5sx3H3mnLU13UvjsvGJkTOiCF GDln/3CGDiWUrYIpqA/S4lz2feWzGmBldSO74Ox0LZMdLzgMVD/7Tu+ggVffLQHmxxX/RhU+RupA vhNK/qemVkG6dZqXqw7GOadvBIlEHx7GDh577LyURs2HOzx6CzGBILmSxaB+IgaUGbHdqMEkCvKb CBuZjSOsWQLa3uoEQajTiieftTeQl/Ciu9j6OciKeX5fnoIfr2ZqFE3J0tLdUzDZkMh/GEewVkib 7z9lwOYjX0sF1HBOjO+j1JZ/NsL1cdP3q8xm3jyyf3wLkCvx523rhozFHiDHsugKf8bCLoFhJa6M ow/QvT2MR+wTIts+4MyfdCNx6hXgFJ4KiY0fDivwQWgsMowGuthmDXj/lfQ20jwY8TkZIoljnCSd 53myxYOqzi+aSYvoiC0wY42VPpwTOF3lKnsgeTSbFZmc8AF8YGl1aVXS5wXkjNVxZ0yQAQBDqi/m hfno0lpDlIwYqn5MYq18wEszXHzZjzsKiNdV7ssKmLM6eydUNgOvY6o1ViTIAuYKDui2Ws8+hNQ5 ebZ27gYyRouu6b/rGUCJPoF5EW+9CPTLkKJPbruXlHY3j/tEtXa40xd2HQpnB+xb5H3Uf7195wtT xrF0Dvv0Jp/P+VqrNR4ELn2V8cJdLNgFaJsHMA+IwbkLYNRlxbga+XqM2h1XrJbk3F84EMRnFOQm LKi0wBPW7Az3msw9w9I7ZYVR7dztlhm5R+JS190gCMPlae/KTOGk/UPVsPwubi+af92SIZgkt0Lm MWy7Kspn6b81PDI4eFAhnv39A42EPcuyGAQCqo1Sgbx3kOFZrnkU6zrqP8hmecYioE+SwGi8yaja 1+87vbFbLjSJI0j/O9Ch2W+QVt03/NnVjG0SB5PnCYiafmbu3DKhtH2w7DTH6zYdfy5O4Tat14St H28KKwNyep3YtMEmSBmkxUAYvUkAQHRytf2ASxR85DkQA+ilL+ps9RHoHgDHfVzW7snXVCj7kj+P 1WziNjJORZWc9SBUVRn3ppdIfGKS3eHxjyCBSpVvdpgRqC7lvgv7G0ocdbwhbiGuBWwgi7ROJwud +VhnNbmxiOmIx8PthXL4ABbpva+xlFgAviq0+ACq8Wb/Smqox7gXJQbHCo/IJWnBLctM5RE7jrn3 2jwtEOc7XhjfhYnbCPlGLNq8PAt6zXWFM91zjnqDvU778O489MU4X1e8/Lk8zJQ84reiIHsW+9pl EQgckHPKvKY+jbxIPreE8oDbvr1vZQ69yxvwwaGkXx3xXt/rrL74n2CfuNv3BFhqHwlfnihre33G eVxLcMIzOiYRyIlXN7WfjF0I0lWZbJUBTCP3IkkM1w6rDyhKWZWQnWZg0syeMbNO2hXeZycjZ4Fx yxasL0RkBRuQutfRPMLcl6nPdFMiIdMMuTAvwzOnFakLK+Jq6n49JIg7I68wX2iBOtO7AmTjZQAO 3sKYoA2mnMZI4fuJM7lQsLMxt+YJQ5YWTe11GkkSUEvaeDtc3jvLLzcnA+5Qy66Dva1pVpGN/Za6 pzfEkI8wXd2TpF4w0edc/R0ExYT8gNAYLa3h6KLwYo/QWODMUbSt60VqedowvhyVfLH1dHGFM31j 5XtNPjcTbFFIuaSIJD+xxBuyWNUFG3lOj8gYak3oPtmziwFbqPsnpsuG8UF1ND8e+7ECcyBunLrT NUM6gqZzj/biwosHT4zGjrynk7lMliey3T38p8QgBGXmD0qfGDv8gymEVk5r/fwmFOCNWLFqlz4Y W0Tu+5JP2Y6N+jVBiHdWuHuXnbeGWLeItdGQFDqnub8SgyNSrVY1IheMexavqGiFXXyWF87NldfB NB4g2MvmQ9KE5gtO2XSbweKXC51HSaAwtnZF0Ieo10eErekGjJ/chsURl3glRkcy6k+VvHTSLLqX IOmrNUJYJ5tGPeVwfc1Tfz45FOR97y5BUrRUgkP9ffoUcKkfOqPhnpZgjQlvD2yxczB4aj+25Un8 b0CbNZhxFLzHwG3nKJwuYs1PlRq+/QEdD7qhNPZ/fwoFuyjUsX4vIURNZF5JKAh9MBK46KfmrnOJ obOX4JK7buhW/GMRRIJQV3wEzKYrFBmEneqeFc+8XTMc88YuIm+on2TpJdqrhT9E6RTu39m0GJtc /zdnbisOSFolzsEf+2Y6K6x4knAGrhQeJGF+aPxgcpM6EmmD+hwif4XipC1Yk1YXzg8joe8OTjYx f4WIoWVGmXHEPVDzordm+zEt2SMpY4y4TUjZqAAVU3WaJDKprvDwJ1l8Nm75HxjLC9PmAv9BoOTG 8y0mOEocMZ1Q1H5w4PRZScOJ4KgtANRJujqieniti91xinmzS95fVMMvZlXJXEeOaXXyTor/wOIY H1cJWg3Tq4YmH7Tma8SxAj8DmzfkcWnzOgLPbhcRM/WcROpaOsixnJ4pZEU4J4I1lVkXlkMpoVdk OtC7sowCXAcj0d2kf3BoQH1yx2Wnr/9Z01J0x+s6iK5kcpiOnwnm93OjW8EsaJBYCEY+tdJulnxt Yt5XJ8HhaY8PgI2gYopTVUYKQHh3RUkl0rYv3zG4rL9GS/ddU4gbXe5c+CGRRXSMxRHjyy7B6Rjj cbgWY4wwtMeL7yAbE06wjuO0W1iGKjWJ2l8Zm+fDeMA9t1C/J/3bTJ9++4qN//Br/+709LSC4r3n ldVexwy3X5NP+n/NskBnue4Vhtn+zdVX4hSnC+ZbR/6Rca9nwt7lCc4JFqWtyqqwojXxkyD7fj/C 1MsrGxtDJQIxGTEP6DYXeKC9g9W6A8aJpigsZhk1R4nMSAV3nlwpXIhVYTea8QUN1TvrIfGPzc6s 2qHmvjGm0rDeIaeMDxPsR9YBQXJLwVwsFRp4QJjQHUNn7zHsDdqLmxQDemz1iJXLqk7CGz9TVPpc b71fQaCyHZmacbHvo8sD2+iL11RfStZO1+/mrZ0N+3bGW/VkhaSfgmVGApBxOVWA28lhe0Jmf4FH 6eLEE64NV1pMbZp20Va5LWpYWFqOOkGJyfJ7Rr+UlYO2zK2isWaDt9iQVP2UrNui5f6jdDpSw9xc 3FYBNL+k4b3TzBf2Dfzb1wJxgGuCZW1pENt9IqNmapLchDbe20vNEpXIf14fUXzTXU29tVKl2jN9 7kQddrMEMgKvkL0YzJg50Bf+aUYpvXEMS2LooSm9fwny4czA4cYWfbOLCZebp3eNSQ41hwNK35qN dCklPO2IVtXXrgT22ayTJhYuKAUg3wGT/5F4rxMdnv/OxOYJiGVJh+fqAjYLx1lywboF9u+yWlHr Pt1MVKVi+b2DIKSui6L91YGLN3GCbHD46a2hZ/rpxNU8D6h71hXMqioLwLregVgyEMEsd/IueQNk NZrkL2+F2OnQWCQKeP1uYhFsQemL8kx843NYLxNoM+aW9W26CFbpud16seYbjAScEgJRM2hAA05e Hwer9oLfgnYfWeApyC0PgC3wJhbg7hkUO+Z8opC/R1juUJowLk8GNeDuW0DIr6ZQvxuK8Bg98buG FuHAIxJbaWQZYB07KMAaKXoqMPBwMcjkjeBw+dPOEeB+Jz2OQ5eCDdp9WHHB3PBb+54QDr6Yn8bA Yc4WqIj7KUCU6c2NLVy7iN6nrFtmOud75EKX4cURvae8ZooGhKGRVRu11FlSZX0+EPn6/dw0P4YN jddj6++MC6oT1dTb5I+kJDkqW/UFIs4O6Y/s/AJ0h+aOle90MK01OgWnZU6pJ820hxcN/Omr4Ffo kqoUGj1y3it2h3vfOoqzQwM8P4W6SyHuKOoZMEgPlVUOkNszJo+xR7lj2Owm26qOv/TZwO2YqwfD esTpKElrnIulsqn7xkGKhuGT9vJXhYxoaP4gLBntBRueE6/yEd7IJtFKEOQS24mA0n412HtKni/1 b8yrnOhPO4+iQqtnvjt4u1Q1zJbnc4kTivftRJE3xeqJE/o9KFj1q48dgQhCGLmSqP6ZuifVEDrU zB3nUzZiBfBW4qvFFe1pE8QZ3lzU5RXQ8N+jH+GZ0+UHV4mAc3o606Jjodw7NgeE63WpaBbrXMuc xUdhWfMcTxGTRifzRY4huQMtKMajEuNPGa50bhfyX30g6Aj8lyza5IGBc67RGyrJWgtrorHQz/z4 VhJCd1ZL76QMK1GcfDUYKgXC1Ab6tdaPkaZC1KPUS7evSKdVJz3PiIh99iP7p1EmShIt3C3DuC46 Ps7JnlAmhHq0JcuvjKmhBHwBn47jxWafG2hnk79Bl5SbGdwoS75S1XSe7nf01m7KuzlbtKPj8ugP GYo9t9wkXGYK4FGt3SdK8tESOErxzb9v0m2HpsbnStMGzlIPG+WODajGEsg0wytRhNfCIBgB1xx3 58/PDeLuwhEXeMWRqLDZfg/TXC29htVqRADADlvsDoIXjQ8eotu2L2DzoOqEGa5CiE7CnwhzTtm0 7dB2lgfBIpQIsmship18PJcM8pW3rKuwKxEt2GyCznNBV9W/HsiqjmokAV2mUOFra1V90rvCeTrU ZRUCubxxEoc/ZlzYRmwP8szm23gPyWrxkpJwIq3PAxMGQxpmEkBV1Buz5l+LxiPuYibviD8LPrKe og2zEoqUgzCglRc9PVbds/DOFnWluRKAlnmV5LTB7riA7ayptZn8e+DNuwAmOzzOZMifiOX/iK81 7eFrZZoFK08O5lmQLXLK9pPf8jLgdmsrDPDnFwTpJGMy+hIbsMhSeW3BxaL3y80RYvNoerNC6Ojw K/5C7+wZzv1/ngd5slJT7vJfQT75TJT1GZtcA0COtZbLOnKFnfOwugkdwcyWOrlDdjzNdbUk4yZa 8myPwiFZiM6sVOlCdtXj9cr6Vk+HtZdgKR8Q3NopybzGffvi9txKXg44QSSjMXY5pqf5CKuvn8lB rvpS6Bvdu0bMn6/ucTWvpnSRpYpO97XuTjlzXWsxk9mpFSb0jdCt8TzS2CB0fMdEX8Dtpnv5HNAZ CuLKnb2S3fny4wL+L9vbFS+863Z04WWZwfE8FdNJNj0vc9LBkmqlSt39GwB3dbBzvc7mRg2/DPcZ KNwhXxEdJXCNcRrP0+ffOhXAiI1/nR2FZCPDEVCX+Iy9CqJr+JsoQvmHfcS0M4goycTJk59t/2US lLcPdDtb9zEveggi9W2x5z73qKVlit5GtZ41ZgJD3/XxFNk6JdncWm6jQv9Ingp2bMbBbqsnjh9z 8zjDrVAOsXzSwxr7el54/CK5+dd3Qhm9HjE0Upca4WhJ3oxH3YOihJro+voHAd8b0rpW3ub3C+sr CZyXKvJfQwWN+3QoOo2FcyMq1G7C1Fxu7Bva/xskU8b5pUnU0Rs28MZ5h+BHPeDgcGh52r5ny0Id k9fy/d1SGCvU/FrlUhGfKh5Ur8TQPqHxnR4HqHPbfFvWHCt5UsH0HpIodzEmSVPApdjjFmBgcn+k OixYXbgFKrHSXFuwcA4X+vz9Y6Z2b9ZxxwSlJTjpkT4hed7/6CgIf4acYi0ubcJsNdq9FAAmfu7H h2mW//uCjX5gK3S9lPOjd8ksJOa+RarpbJDfIo8hBX1DksNmP99W9u8jz4Hkx8+M3bbO0wt4lJVd RKiuszmQhLKi4AOQHV0rP4KCGNJAE9GwJ0WfTincGDD34hmr4KIAF0BrlvFOV60aUCKAU78XXKwt yE9YZdf7gkToU2cXStilQkyAs6LSso0/4Kp7z1/CoVPY3Kh2FvfbgpijfH50nQp2leuhGhe0AAYA oGcuztBaJ3jTqTvNM1St3e1a2W2B3XClT+ipTY2UN4xutwngsaIR4U6YvWCd2o6ANj2jJqxob5Xs /6Tx++S9stq0P6wYqTRxCgd2/fLtKVNDkV0YuJh1Xqn6JNfQZsnOoW3ug4V7VHo+mxO96IFQ8VLf cz+9HjjYr0ySR19C8CVCeAGLojION2dAW7oGOQW4oa8zzMDeBjZcn05oGrSjfl/qNgMAcoCXQv+M Jv/4oAJWKKeCf2pnVh1xL9BDXX8u3XQHL+kzeUS6c5J+lp4oRjE3ypB4+IjjYyTRMh/x47DtJqJr l2nCW5q+GEbFSO5On40hXNpFtxXT4+il3QMfci7UjaI2/VB2kFQ+fx75sOKbM2AhwVnaloR/kfjW 8LK6zIvepMFjjbqX2kblWU7mC3sK8Le8/QPlkaeXoh+mi7FQq5/Og22XxQD4QUX++9sY2Lo2uxr0 dKvdcJDIZAJfThg96O/KP/FcQWlnZNvmvwjfszOKjD+S6Qj29GQCP6yotuF4zUIIc8MogwiuHPVC tWISumhcVQDLNlOVfpfS0XLv3qa+v2oYPM04mxitEZZC7Zgnk5kJro5pG8aa2Z32Hd3olAPBOioz JWDc/rmtu9UJulFj6Q1I+IBDSusDEwCtxqKZkTMMFQDGfiN1QkeQs4lXzCoJnqTcnKFWJ2z5Fmev cs1gcp2vSk3E5vdr/+RvO5Yj7lyiJvgLvBQ9YG4qBvsiOkDXA5xFQMCIfG79wuvoowU4neIKHh7Q BTUg068oSdkenJ0urfyA0x3XwDiyFsJYGtcwtSU5qN2nco4BuwYTlAmHQaZ5z877AUyesvVlds3/ 8HEWzauCjGKKo6bIjg4Roh2pmdK/bHEdcVD3xHhJW9XTmPFuQGGXk2gNr8WJIpSSzGeb6xpzi79w QPEZehbUvA54qHXEFU8A2s+dlMvcPYelDwdcZ/fToWXTPiHAFBYtknym2Zs1dNIpQsNTXTyaTUQM MTqnXCCg/U4bn53Yd/zI8+GkGbWNX12qS2/fzEjNB/QU207pgl8xz66FRoXcR327l2PBKJWQX832 Odlez9Up9BchnquBruYXQ2tdK6abznc3e7YqJSlMnYcwsExuEN3uMQyIvwlnGMf9qyRzLe/5hXH8 q6aiSNrHe4C3VaeSPOk+BOyF+XMBJPedY5LysBeM47RZ93q19FpakNN7Gr6gGnw8zDG18X87zWMp 8rxDSyW2GTiDRQVC+xJaTw1Q12joVoN6Wqn5Hewp5KqeX+Ad3TRxR0b1bSgSF7Aq8H13XJwOaC0e btP2/D61ibfzmbEB49JWLZYWkd/QUNLRuQGQd0CLzH9EWCjdhmGbOTmpDFv4JjUCvoeEgzgVv/nO w/xc7n6wDSQCwfFN8n6TODCWNiMiYoWcAeCfur2P5bvFg03at81RyY65/JlQBCvDElm125toRlnr GAa+sKKssDhmRbMXXUia6GHS4INigS8vZBfRAJODB/7owJWBxpyOs+U+6JjY07c5ZRlEz3O/Om0C 7xcXluYEpfJUuRmf/F5NcoSO4L/Y9hF63uuBpbwLr/MeUocu/IcvdYq6bCEe6Ie+k/kvB/Q6uC3+ 7ATMcJ2de/6djZuwj5zUFshthmFQqGiX3aVSBE0G+SVCJusVHf5uF46TA+XuZnMubVkBfdujeTnk UtY72ckUebLTpVRuuGisYknZr5rNw8HkVNNJHUDw2VIMyueVHVZ5yhtzl2ktfmO9lMK7xQ+nM9Sy W+QuHgT6RRNwP6+6BULSLKCVIoNoTLO4JYK3cq8llFfVSOz8KOrdMm4RlQAEQULZCeaT+xiukOB5 8CSOllx7109BSwN1QLYgTl+vf4KIEhfwzP/z9RqZfQa+g0uSC1tQNkxG5rtXUiZXtxUqarEagC6u vKcj+NCeuBgCfuZ47kvNA4YQpdOkLpTpLhKgjZGIRo3Qx1Z8aJkIjOExxwWMiIep4rZAXtAdbVdH wh8Lr3FABZ9/0OIyDii+WtsjGUu3yDWuWC1G4mvVDJaLd+lb1dy5tcC6R2tNwj2rNztKhPeCQ2Hz /Vbkw+rskDeeqcKsyhSZ+snm3g/scVQn8iU2VnNbvdM86Tn12qhHvMJOepoQg2jPB4cE40JYnjQW wjNCcwJR1QDc37vyIxs3JbQRtHkjW+PfEgzYTVXlEtlWEpprXaXd9PoFJDS4zbfzSwVDZOHGiRjD vlob03ArCf/C1lnTowSiNIm5449yy0eP1ByM4+EDxxf03580KvVKU6ETOrgLpesmLQjq/Ecy0zlL iGs1uOnBGKF2BWrQsIP5EmprOLJFK3AH668BkE8yBsMHaSSGGGYwObH7STpiMsKDlxCWbob3QFAN wNvwiPMQbnrfUl1cWHExq68/nYr48kdz0dXNEkK+SyvMa7cTtlG65T4tBhQ0EXOEEXU2D3G6FfMv QSyDNMs0kyFLOjr8xuRpX8Re/Nm8NMPaLJvf/GObkNnTlKDWgpba/9KUD1650hDWYTH0Aj3ygFoG dPVgafeB6QAtrPvXkv3ympd8x89GBsFg08U7O339My365RJggEKwCIFUBrN4N8jnHBMqk3TV5vjQ QP1lfJn6GFaQpBM7EyAqdj0l5+rsLtcOcC4HrQO6soUYxQ1GBOLI1DChrllxgTDzI+VnAv4TChaU PwuyyZpeUd19gQIrQC2YnP9+b4rWaRzftqq/vCjytAyPF/rjPFDwhIKjpd/cmyp0S8FkkAOYSN1f 7wMucqt/mf4ISWMLwpS8bBVXJmZ5lHnxSiz2QlLgisTF/3nTx2rN9wWvcYNb+l2U81d1HUkLfAEk kqQmt/Yagmq9DSRabpyR1zjoWtQnZoaf1XYX7cbElO+EQtfid7m78FHoE2smIQTWwjhKXwitHtYX tRYX58UkI7DUpI2tEe/rGjlQnSQW+4o3zviqn5Wq9liaHoO/Y9nmAqmD5Dx8O9tWSL5WnxKCO5k6 iLadYB8dO1UMUN9B5GgtW5av0YbVkaEFOH3hqrjh/8gjWcrCHmxRkKJCK+a5pOvkHTtQe2ACkIlJ l7rjAhXXPMZPGgnSjGv5YtWi7W8L7fkX+mtt6evo/Q5ZUXLNcJTbu68gcGf05vgbkiBOXmsC5U3Z zJCyRrkQnv3Q1QByH54miet1kvnEW5m07yguw9h5/t96sp9x8M2e877Q4OuE+AChrxhv3+KfWrYT fUMKnD5nRTErCKXKtfrVq9pdfXtPQkcQPzMNc3VvmsUbuNySZ4gjKdlQEfCANpPirn7S/WcKKUoS 7llsrZ/ePj96oxeR2ShARDzkw1wRHvCllT/5K1Buuk1tdSxOSGQpkfqr6jonluj4rtj4BPHBlbIi cn5jdhF79kutb+XX08mmcVsRtvFKb3RJj17MRliiaUq9/lL5YqIfqEpcn6aSvwAI/6tUb1ZfKgJ3 Rw1UQl4xY9HD/OkQV511kewZnvT+kmJpG42E4cBm19mPjRRvaopaZ7+mMeRZbm4GR96DV2XsOJXF TAH5MI+u4Vcw1xNNwmHMixYXOpexlgo4dS5nfJ75aCjt48RDEIZiCu5+9iS7HZ612QEcVrUoazO5 hD0fERTjraMJMVClka5LxBIT9g6/6RclcRvhr4qwuAXVomkoXsmxEDeVvvVKra/yXL2yWVqSs3N/ wqYmz2x4nWP65ss8Xh/aD+HMv9sNpuqNUmHsUaBTjf826K33GG9Vo3ZsZ+w5UGQxG7360wFc4Jz5 lVco2zanMzl17Ca+jC9yV+AbBQiKSQ8trwDO+7zJDs7jh+ptMtVUutWF2ZswuRboTqTcopcoprLa kJCTP3Tzt42CKYCWMboUCEh93qZrOzRlEHEfEEq1v/0+30p5TW4dmsVk7y6JmhrTjiNiU3tyqWFJ WEIbYnBpWpCETZMfqaH9q9bsTcF30RhICGAiuRHVvpjXTsmekJQYjh6gG79D4raGjVQpCkm9kYq+ ell3P7F8zxY3PSSmxCzijJSDeHauhOJuvP8bTwItG33I3Z3L+KLaSG8r311yKbCDXVbE77qVsegL M9SqjpYVbUeJIMqKmypVaHL1SBED43ziC0gSP6UhfJfxqle0FUkxrYvzf516pdo1HjIQ/4aNeEgz A0asPDI/eg4f/2OJCi6ACg/wCDBSWW2x9nNtOq7PgtXMxCHUjvp5HZ1a4u5Ab8+6lgAKde81BPLm bNV5hvePK/BKfcPVjNhDh5BQhb+6eAJgzkjlxudf5Xa74X+mbdpmTe3OYKtlkxITxEnqgqbTce7b Lk9711BZOHVviU8owJu3oXJdxmjh3wl1J4s/dBHhJsVKZX+DKMEonJ1oZUhtNCywqzGnQa89jRnV QpuMj9CFoGvVpLdc7ztBgtwsP2bnj95aBUlvLLV0KoO3glM1Egt4ZG8r1bKQlgWIRpEUywpXre7f 36NWkp548cFGlO16Sx0fWzy/c4Q1pBafXL4dr12Iaik0uGAef+yYlT/zOzbtXH/YISXre/DuI3Xy Ulb8BVF9lvGQw5e8RQLMNIyk3LcJ2bYiPejTHGOoZA25JTsoxSdfvdHOLnTuHiSjGqQiUkbPzXqt VRbvOl/OkBOF3tDhWFZi25oJTDmsFBKTlYrq9mzF1MlK6XHoDNd0OZ/tRrqSZZ7RfkO3MA5VsyJc MjQtWk05pgJrvkxej8r9Etfl/2+5NR9rhknvQsLDEob8cyXZzEr2rQFIYj3ecnHpKPjoTyRnVAjL wfcVC1jdLFv9AFu015R2ySRLclotU0VQb55ATp/TpCHNqdOFmJTgrpWbRPFNrEfgrqD1qq6U75HD P6xyF71qH+MZsrEVqts5WeM52U2FBdja6xNMprahK3ZwBowbpWTKJBJPqzAv2DZ99PmO4X1BcjVS xympC06Tcu9fVMMO+/3CT9HcoWnWRMjEt1EyOtaDctzjk5Ed8CsY+f3Z/1vbJynEieDX1W50iPIi an6STtinrlaAAWkYLdV8BpzTA/EVV0JcNMN8EE//sFYZxjmdEC3S4S4b71VHzB5BImjb7aECrXCT ZBVZHnifSidIBJwrj2aH4qzt8kFg4bW4FAe42iqkmP1sHaJpfEz/D2dHKrrpPuO+WQtW2CMuNjTn pDRLZ3525Td9L3TPqJiw7M3tpTg50nK7svh64lithh5lG+y4pxKVLf/xcfgsTtpsnUPqvZAHBpmM mJPMlaZ4fycEriWScoSGyoozwrmnm64JdB/99by8qkD9WUGBLc8Sa/BsjbQmUNx6whY4zkkRdmjE a+4yNgAAChsZwmYgMPVg2UoiKmiFGgwCIFLRGofF8f/912ufKFP40scM+eOVwa0PijwRZ+rYIFsA TwH+mmLbIC/PCtZQC8vvbSwIJTDKP0KZ/QKxBrwqXK9tyz+AxJwEI+x6SMeREtq2ah21JyscgtBp iW5II4vn5H04/9MwazMRemERCESORkxNmhcIkuFGTsFIAIUr3ZOfoAwflHPf/YDNt6fBDBUeBDjV 62/0LrA898FrGbMinAw6uNWtNSqCT63gshPEhzZfLhcmbhLzOOd7WQWg3V3kIK6QYnzuY6HtHhnZ 65K3rA2pR3mwJXlt4TAG0mcMKoY38lPuoyTBO710RG+E4QfCHf1XbBEEq9Lr6xT6N7gWPMNRc2OH yZH6iVK1Wa8fXanMBiiqsXt1rvequdWSzZ9C3VGYGIExPayiwzVUYsHYgDPThCI8ja1M6UhCi7xy mbusUFiPPrtFjhyxOuteL3tLb1SVvN0/FGf4zGx0pjKmIuxybgyCKJ2+Kl1IUXQ2G51wiGuPnMcZ hIXu/9xQhltXJ9gsotJPVuIHvNctZbyyqdeK+TeoOXHZwSSLpjwJHmExS/AxzXUvIRkE0WVO7mg5 NSIvlTZZoNlEHCmAYpzcY25GBw6bCE28UzK4187aOTvTmFZVlUnX4AXeIs1CoGJhopKBq7dXRaGj lZEi8TCw5Kcl8lg+GnvE//3Pc18Tu9y0LaIndPjV00UKd2hEuFGbOebO0CHsuF/AwqLGvoBo7xr9 4r9gRtJp7DTIjOJrzdIH3Vu2B01k/Kocf/BOX/Xt7/tF4PspMz5CLK1uJIJuM1zWnBWP4DcRX2OD qXoe9SFT/CKfFILmjlBmhRAa1335GZDGnrs9jYFJaYDdW/MZ7s6ZOrryQaEhY3yA8qMjmUYIqQoW 3b8KCkeVq9viYZGJ6UBP/Yuo0vjGoidg8tw1S5+onAkBY4vfTb7mRB9xstIpg56q9UMtdmLj+eEh VmoXfNL+wpzmaiAX6geQPRCjCcqDWS2OSVMYDOkP5PAIJLtL3ObFGUnj5ejfmkxcguegmXjC93hp C3IGdW1ole9BwMVSfAaJSYgcarExuohfGiAxcH+frFlv51TySrWif9LXb6dW/+uaq1yIZpFT75GF VlSEKvLHl6XVKiuUCCg9/fT+4NTC7nsw8ptzmdj7dZ1hfFFOni0MpVgo+qgK2/dlB5O+P3ByU+gj EZOlngOFLD+z1ojltz8vwTiHJIPhs/TFMAqqyhXYrE6xDeTT++oCcxxHJ2CdTjXmtHMW8fWFK6YZ R8/myw9lH5dtjwQFN/cqFaOTZRzH5kJe6qA6mJnNKslZuyAWVKJD8HTJIdPg9g5ldvEsDaJM+XIl cLLap7C7NGlP4cg0fBC2cB3+cjCAVgA334zZIb/DhhAcq5qVG2vgn7w2GhVF8B/99l6savTNCzAr q5s5SRNfurNynmuu6oar7cNzGsDIIq5yLHQfCboiQRLPpb8AX6cxRCFKPLb23Qr6HHVkbVLEgdD2 F4kzD8ADdKL3hlrr0QcnHEzZ8eq/DRVtT1hGMJ5lJjH2SHgcbJ0NPI+kVjWpU7hPSb+6MFJDrKqm Z+WL/2p5jNIpwSnOFUggvxuO/ZH+oHe5lxtpCYxuIsel/grLGDgQ7LuDcZ5yHMATfxo8gCOA+63w BiO/TFzf9SmUHpKTxoawHo/ARGYUiuaq4grO8DW8CDpgSakv1Kel7ohp5Dg/HmgB81XJXRlPXZ7E lHrCW+PSgaoC9OUuI7EKT6JunJZB3yDXE556vQHm/NVLlHGFBeHFa7Qi0YrcO911QMHjKzQQkjXl xoTCeJA4l3g2rVVgjGBhln6JfNoCYuylqb6iFZpt2UpadKSPBPv9uCTuFt0RrfSE7C4O9vHZltpw OFgXuOv4fpAmjATkL5opmJoxHbDbsf/fK3h9YO/X6ZW26nJdtdcatLr0HlEzxW9A2znR8ihQBVD/ sFaoxXc32DC8gTHC8N3eh7ARyuWYxX2eqUbeQLgtE3vMJeMjreTJSkk1NCMUnAU0JhAiYNBsMnVv XOXqfmBaHhGfLqxTnHeyyb0yPT1GVjvW2GZv2JVD2ghL17237S5kiS7eLiaHyRQZOIDYagWSC/cu udZfDO+FRGEUMSQPWyhJxeuLl3PJRhYK3A+AC9R0699ffjSLGMl0AcOZU8v4/Ry1hh1D88Fms0Dg FXQcONeREa3gDjN+ft3SqkSEwtTm5Mes8kQcOcCr7NfHB7+IsefiUDe3Ls4B6VkpTIQBzXHR6XA8 odudeLkKACd+9LA8Ma3aiSnBTthfNHI+LHKdccQ1U0cxffQmgEfQ7tWxVURfoas+KWHzImvSIBpR KEUu4DsHuGEOsHYkN+7WSANkYqbL4mFIoW80RFJM8LTHjR6wNIHkQzp4bMhP5od9HzXfrIlUlw++ c69q8gsp/Etf0NUpXJUECzkQVy++QWZ2pHyG+ajXhYLDRgA+0wkV9CfVZ8uv0LJ3AqR5vsoVO7ds NJcCjkFdP05Is616Ws5M8V/7okPdGO4oBmrlKJ+4fMZDCC6ZuPneSa2Tf4KB8vejYO24A3iWwvRz iHoQPWAE6Kvwb6tBECnJ4kwT6GwbNNHHlTOCOseXAv2gB3lzT76sEFiKg4fVKcGmOdGlvt/XWxO9 DE3RAhJM7fjqdA1B3ivexhBCjKOQ+paQbE2ExheJ+K/c+Qo3YK20U2BaKf7H096yPz72EdZFdLCS h2w8bBUKmNguHP8jRniAFmm+5GV2EnN1qhbIZ5iYgEGV1cv3JiKvgT9QbU8TLx9RQQynOc2oewIB MOf6FYV0BhYymqC38WlQRv59sxRBT5QOXrx86qDQQLCwJJayeMspZqQdJkr7SG9fPzsonolxubH0 1zCEP7csIiUd7unPdNoRuPmplwqPZxZ60Hmg4aeMQyTrfvZDdcNjW0xaMGtZc1JxtEvJ47p99YOk Wx+RaBC624QRuyRiRmkv19Swc/Duc+Rs09fgw1dKhiboXPIIBSxDRsE23KkZCPRTFJMPViEPLhBM yz15vtNhkLs8V2mAmt8MFAT1r/7PfrQwT0VcouweOtm867s5H5g5F39BNaYOKkgB3uoy/wtDXvNU TBFdWLeleJ2dXKwZu/aNLEQv2ZtWc+r/gL2HdzelOJJzXrjGW0hkWoSlU//x6uYR1LXHvB5QALb1 kBMhZ7FfKaq6wMP/hhCSMzwJfbXR9aSfeO1SczFhfvFcXVZn2wnisVP+CJeRN7qWqxuDAq1oqC+k B861BbfK4v1qSuEaHh4TkVdtQGLfoRjPj/wcqKI2HKFHh8U89ZAcZLpWb4dtWtaauV6IKtEq7IpD yEY5qlctEBf1FZbcRS23F3vQM/Le55cXCry0FZmZF8sQ0tAp7DB+qyZAYBO36j20PWo2icZcDhmI a2w5wVQ6FTvnqWT+C9POFfBhZyYWjrxiLHQHom1lGj8ljr+ANawC6nr0EHwTGBDL4IlRA6ZhXlz0 vCClUphi5CV4iC4UDzhCsd9FaJL+Njwt4CwDU0ginliUenyu6lKj+avH8hrYY0KqrEUVVQUubh0m ccSWA4aXcbWmr4RrSiCv20HCuvkJoJw79Z//oNu8tc9cU4TYarJqvWmYloZS0/zu2vhI9o0UALF5 0J/jxuh8LHiWVDXUb0PEjg+knxuve+TXJ/sT0N4hGtEF/3MvhAMhlZe8ZA7QpapbXWGklrWSgJ7Z 0NXp+QUG6Ijdb0F/W+f/sWgG2NZ9Ur19HU3WvVVn/cT2TozHZlThfgJCqjyENKTxAcc0kfmh1XBr 4KR6xWPp+OWegf7B7CsMsAdknE7vS+mgvMmwDNteaq/2JNLBGeR6O4iOY5WBpm6nivZkLknalJUP fjLcb8fUp7fN+9jmofDrkSPOad4NDq5pnRPheIeAK+VaflM7F3GNKVZzGMWtroJ0EdO8eUaSvVxr ookPBLHAimvUrr0SHRW/WZA1O8Dt6gKLFfBVl6NwLMY09MzF+Y4DsEMX5LGhwOtEnNzv/n4orA1w AxNLzCHAKO4/5rHZOgGpHPZ5LueU8G8dyvx1couoQbxOh9Tv7JNqvFq62rdX1z4O5z/V0PxEugii ef5d4TKUzEoSZHyuvXRuh3FFFQexb4X3H+2zEDdFE2Aofc+7Sx99E2ZEagwEQkL5G9fUEeuXnG6T QNDgyqdBdTmAE+tdrx7FIozTrrkLSv7Vd0/oSo06QgK/N4rs0lJuxqOXm3NWNqONF+74eiLYrn4l dVaZhln2brWfKvz2sU+nCP/jEQCfcpb2nOdl0MDB9ITjS4V+eRVuJzXPu6Q/U9vUxcM9gMXYwjJN /iVLzAJBB951O1ibNx7jxs5Gfm1eQdi28hgiz75yCp61JHjKjBnvUFbc08vsap6sDOqcg/j8zm6Y 7YpIhNmiQBLcn6cLWK99QF+ysMLYwKl/Fp0vcoJCSq3y/yE9lvF4zUByWmtIlMfV51uqG8NvWSFA 3R6wxZYH74GSVWtsBlQJCjt8xY0nXSTHGiBrvwRk8VGwTao8zI3gs32gsVn3/0tgG8kOUNqKuZnY JwW+t4p7u1+zmeJqnWQG2nSf6/CJ87Rq6VeX7SRRHIrLfXjZUxEBiAlt7B4rK/uQTkcMWgzj50/K zO2LV4M2nXPInXzFOx9oSRsUwdLqSCr+lB0U8yiuMPnUgqdkDJkaLNUpYVu+0QeqDJS3AkPMgGkw ggF+NX6fiTKyseHzXpCfqWFloABOg3hRl0Q/F9imK2w4p3ZBb8bm54mmlH0o0lNncTJMletVwV5M wOnLtu5z/qA0Anu9BvlUzu0ZFiPhqGXCg6TbdYRXw2WTxIpbI2dKXLuQvRE/gnvGAoISYTZlhEAF nEmD1KAb8zrzC13zvSSEHkIIelT2Q2KOLgHygkENJuexSPNd9CeqG2iSY8rNxf8kxQQIxKicPrsC 8dG5xN0OR9qYGRyWXKxwaf8Knj51I0T0YQZgHTyukhUzT7e9g5hGYj7mbNUa9Ov3SdbvNlDch9t/ 5usIGVvsYMTTjgpqZYDae+7eTZTQEgibyxgtKJ3p6TwCYi9LFKUm0oh6nSjGpCUcYkWJy2bH2WIp eZ4BdcTfKnc1+bNECExXCFIX30TJiCQ8A/F2kBojI3dw/1cYOWbQOKocwl+TmFahzD/rRzEXrZzb iCXfAO2rjcFvoHjOEZk1CThwMUP9yAg/d9CrAs7WFQe+7uDU36KIIIy4kdYSGfoI4zKqOVMJ+O76 bDz/oDYSZrHEcHPGkSszfnO7V+0ias36+LUaRRPopmt6Afa7q8mir33q35F1ttj3JQivGOjwwku7 h4upkWKOZP+nrjDR11c71bLjpLN4hS8gvOx1+UGk9jWo5NoV+3kaeSS7gjqqJgQtmwRdbpYivDC2 BubTzhnZIjl3A1ccUY8oOMCxr7fvAvt1ScdlXfmiG/9MUaBbwME4aRr95LXxBcRU9xXKhhYGt8xX 8i/An4O5e4RpLsh3gd6P/piAyPFGS22id2uVTiQAKL9WBrZE3ClM6kLmg+uhOOigDEvgL1HG8eEe u9ZcpoOBsolTHectGdDZaAeiZ5K3ATAs7+knvwuA6I78FtVhWbzHqghZZcHW8nSJR5mf0QQ0D7ps jEIpiazYNn8rFdMKmWrw5miA2hhfbWnWmQTYxZLVZWNPE9lbW7GDZ+DlfToNuuX6v8WWVCbkDeY/ LL7w1MFlhOe0FBbAVGFNuupUv8ETOVj4mbnWtNe/QyZ05q/J5+gjsZ9Rf7bgb0DisdVBENfu634R gC3aVnOkPuLWza3Lb+tTxyqci70L5oE2yGjbZ+RXw1K0uj450obAcDF4jjpRVwbRUM1bnfJxII01 zBB70yueSOnLK+Wst+1BgET3A9ZAIkfss15fmnEtadcN/xZOr0FZa2WcCgsyKh4tqJSNDwZxiXtH K+ee784H+VDal9pNMJOR8PcTDYH7QWD/cKlMw6YZpHetyyQLWyDY04ICmmzeIkWZolRCfoOSQlfA WfWWxwZgJxm7QjydmAzj6UzLAM34ChHk+WUtic3fw65wjtGJFdtqrLqr+muXaU6ZCgSLgiPVHSia TKoQqhY0fSbJ/ovEei/+5yq3959wfItKoBlL2Zo2+eRhWKZWkpe7hd83Wb2PysWr1z34HHf8GTU/ gHrOz8lgp8dHTGAfY7oMISzn0ZEnOTqprgdQHzMf0xDoeX15uP2xk5zN128Nn/f3hNqZJlbzsa1B wy7T84qbjxPS1tggItYCgtS3RqIGAo8uo7kfQ7N3BCdB/Fzj8Rybd9sOWCmS58lU7yUNn/L/Dn/w RT45sElD3glwmqKgTfdNYYIviy4aVcXztOlXKStMwGiz0s7sYQvcz34EqbuRvjSrUoY188/cxuo9 ASOrMDu949T7Ni5RLwuF/zor3Z4AolEYqli0q7d8o2nnsa2SF2mz6o/2oTKa36YIA/mlrF8v+fNc iBLOY8P+2P2hlNMddzq0rK5jf1MnGcpm5a1xmgnWWe5qjRIwrXUKCYcCMweCjXcKui4vJ7W4Y7da wnEAXMUpZ6JgJmdSw4SKV6De/xs62U/eSdQUkw69uVIZZWfWxfMjmR31wGBiVryRnqeomm7X2wvj lGB+tbrZQo667aBA6nUvF8ZxNfAwXaHDseHj5Vc= `protect end_protected	bsd-2-clause	eae873e5ca78c767734d43876af5e819	0.940148	1.86049	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/if_statement/rule_029_test_input.fixed_upper.vhd	1	566	architecture RTL of FIFO is begin process begin if a = '1' THEN b <= '0'; elsif c = '1' THEN b <= '1'; else if x = '1' THEN z <= '0'; elsif x = '0' THEN z <= '1'; else z <= 'Z'; end if; end if; -- Violations below if a = '1' THEN b <= '0'; elsif c = '1' THEN b <= '1'; else if x = '1' THEN z <= '0'; elsif x = '0' THEN z <= '1'; else z <= 'Z'; end if; end if; end process; end architecture RTL;	gpl-3.0	0fa4c892245fb80eea3fe4a3f9705490	0.379859	3.19774	false	false	false	false
kjellhar/axi_mmc	src/vhdl/mmc_crc7.vhd	1	1,758	---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/01/2014 10:27:20 AM -- Design Name: -- Module Name: mmc_crc7 - rtl -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mmc_crc7 is Port ( clk : in std_logic; clk_en : in std_logic; reset : in std_logic; enable : in std_logic; serial_in : in std_logic; crc7_out : out std_logic_vector (6 downto 0) ); end mmc_crc7; architecture rtl of mmc_crc7 is signal crc_reg : std_logic_vector (6 downto 0) := (others => '0'); begin crc7_out <= crc_reg; process begin wait until rising_edge(clk); if reset='1' then crc_reg <= (others => '0'); elsif enable='1' and clk_en='1' then crc_reg(0) <= crc_reg(6) xor serial_in; crc_reg(1) <= crc_reg(0); crc_reg(2) <= crc_reg(1); crc_reg(3) <= crc_reg(2) xor crc_reg(6) xor serial_in; crc_reg(4) <= crc_reg(3); crc_reg(5) <= crc_reg(4); crc_reg(6) <= crc_reg(5); end if; end process; end rtl;	mit	c0197e90bda6ba9fd2552d104b2b7d91	0.510808	3.624742	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/architecture/rule_601_test_input.fixed.vhd	1	8,219	entity FIFO is generic ( G_WIDTH : natural := 16 ); port ( I_INPUT : in std_logic; O_OUTPUT : out std_logic; IO_INOUT : inout std_logic ); end entity; architecture rtl of fifo is function func1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) return integer is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; procedure proc1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) is variable w_data : std_logic_vector(g_width - 1 downto 0); variable w_read : std_logic_vector(i_input'range); variable w_read : std_logic_vector(o_output'left downto 0); variable w_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; signal w_data : std_logic_vector(G_WIDTH - 1 downto 0); constant w_read : std_logic_vector(I_INPUT'range); shared variable w_read : std_logic_vector(O_OUTPUT'left downto 0); signal w_read : std_logic_vector(31 downto IO_INOUT'right); begin output <= large_data(g_width - 1 downto 0); process (I_INPUT, O_OUTPUT, IO_INOUT) is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end process; a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input => I_INPUT, o_output => O_OUTPUT, io_inout => IO_INOUT ); U_RAM : RAM generic map ( g_width => g_width ) port map ( I_INPUT, O_OUTPUT, IO_INOUT ); end architecture rtl; -- Violations Below architecture rtl of fifo is function func1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) return integer is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; procedure proc1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) is variable w_data : std_logic_vector(g_width - 1 downto 0); variable w_read : std_logic_vector(i_input'range); variable w_read : std_logic_vector(o_output'left downto 0); variable w_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(I_INPUT'range); signal w_read : std_logic_vector(O_OUTPUT'left downto 0); signal w_read : std_logic_vector(31 downto IO_INOUT'right); begin output <= large_data(g_width - 1 downto 0); process (I_INPUT, O_OUTPUT, IO_INOUT) is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end process; a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input => I_INPUT, o_output => O_OUTPUT, io_inout => IO_INOUT ); U_RAM : RAM generic map ( g_width => g_width ) port map ( I_INPUT, O_OUTPUT, IO_INOUT ); end architecture rtl; -- Change entities entity NEW_FIFO is generic ( g_width : natural := 16 ); port ( i_input : in std_logic; o_output : out std_logic; io_inout : inout std_logic ); end entity; architecture rtl of new_fifo is function func1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) return integer is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; procedure proc1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) is variable w_data : std_logic_vector(G_WIDTH - 1 downto 0); variable w_read : std_logic_vector(I_INPUT'range); variable w_read : std_logic_vector(O_OUTPUT'left downto 0); variable w_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(i_input'range); signal w_read : std_logic_vector(o_output'left downto 0); signal w_read : std_logic_vector(31 downto io_inout'right); begin output <= large_data(g_width - 1 downto 0); process (i_input, o_output, io_inout) is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end process; a <= i_input; b <= o_output; c <= io_inout; U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT => i_input, O_OUTPUT => o_output, IO_INOUT => io_inout ); U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( i_input, o_output, io_inout ); end architecture rtl; -- Violations architecture rtl of new_fifo is function func1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) return integer is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; procedure proc1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) is variable w_data : std_logic_vector(G_WIDTH - 1 downto 0); variable w_read : std_logic_vector(I_INPUT'range); variable w_read : std_logic_vector(O_OUTPUT'left downto 0); variable w_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(i_input'range); signal w_read : std_logic_vector(o_output'left downto 0); signal w_read : std_logic_vector(31 downto io_inout'right); begin output <= large_data(G_WIDTH - 1 downto 0); process (i_input, o_output, io_inout) is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end process; a <= i_input; b <= o_output; c <= io_inout; U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT => i_input, O_OUTPUT => o_output, IO_INOUT => io_inout ); U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( i_input, o_output, io_inout ); end architecture rtl;	gpl-3.0	c697f04a83d4745f18374b388491bf80	0.607373	3.128664	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux4_1_x_n.vhd	1	5,771	------------------------------------------------------------------------------- -- axi_datamover_dre_mux4_1_x_n.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_dre_mux4_1_x_n.vhd -- -- Description: -- -- This VHDL file provides a 4 to 1 by N bits wide mux for the AXI Data Realignment -- Engine (DRE). -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_dre_mux4_1_x_n.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.STD_LOGIC_UNSIGNED.all; use ieee.std_logic_arith.all; ------------------------------------------------------------------------------- -- Start 4 to 1 xN Mux ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- Entity axi_datamover_dre_mux4_1_x_n is generic ( C_WIDTH : Integer := 8 -- Sets the bit width of the 4x Mux slice ); port ( Sel : In std_logic_vector(1 downto 0); -- Mux select control I0 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 0 input I1 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 1 input I2 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 2 input I3 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 3 input Y : Out std_logic_vector(C_WIDTH-1 downto 0) -- Mux output value ); end entity axi_datamover_dre_mux4_1_x_n; -- Architecture implementation of axi_datamover_dre_mux4_1_x_n is begin ------------------------------------------------------------- -- Combinational Process -- -- Label: SELECT4_1 -- -- Process Description: -- This process implements an 4 to 1 mux. -- ------------------------------------------------------------- SELECT4_1 : process (Sel, I0, I1, I2, I3) begin case Sel is when "00" => Y <= I0; when "01" => Y <= I1; when "10" => Y <= I2; when "11" => Y <= I3; when others => Y <= I0; end case; end process SELECT4_1; end implementation; -- axi_datamover_dre_mux4_1_x_n ------------------------------------------------------------------------------- -- End 4 to 1 xN Mux -------------------------------------------------------------------------------	bsd-2-clause	2f25b0ac2d709c4431e0d49e0adc70a5	0.476521	4.853659	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/fifo_generator_v11_0_synth.vhd	2	227,980	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gL0CqO1ypyB9Iajc4H0PZWSiVuR9rN+e/dExZ5CzCiWOIMm1dkeBw4ExExKRzJIKHBnvfMPGx0gY NJfwOBv1Ww== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BmI7qCK4aPeD4rx20+AiTUTtIjC99eXYSOn9Yfn8p33JFaxMkAy5+CgYjbYDX34rK6U5iySkhAtI ccUkx6ZMkz8hNY6EgkjvxtnTtQxMaKQtILNv/DO/0dRPcEzl1G51tso++2d0+SBysiWQ/6GLLEAC minyDmKCKUfWkdQ2IdU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block li1siM5dimL8mdnKqtBlzL9QPSSf5uTaDmhGwdSa7wPFoD99doQI5kl7srjBgKvOZgXSsiucBxMP XAH1KSDdbE8pj79NttwuKGCxe1K75x7NyQDGLBfjbFsAnPc7hvBNoBKC3yfGWu0FlO+BXoQq9+mJ TZKheapqnfam/gV2tLL97UOWHGQlK5k4C8fEeMgXcxiHkUhA8got9xa3R6kRomre8jrbq4zSxdoj g8xZhvm6+wW2aZzizle7kOJU5jZTMTlERAAk6ZIwBk8hCncQKMjBSN4TJZ167CeV08XzJEIRrCKc gNl55Unx1zpzEn2SQBMTsRFZI6jPGJRVsEKhSQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Mp5AzZVFDo6GkMs+iJ6/0sDABOkxTJ+bTm11GYBNdjWmBEqZqprmdJBXI/6KNBP5n+4FV0B1J7JI MFj/cXbaRs2gkdC2Wxm2bp49nV95vZ1+dGRbfgA6lqN6xhHzd5MzNRBsZqn6AhZAPK2w2viFYdFl ytMryyHBmkDLU2obtQ4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mi/KOQkUb+Rz4/CkC0aVvOFVjkUQNWC4X0FbQYlv3nkKpZjsfHrt7+q8iLIdrGwtDs+qUs6QEOqE Bp2ZO9OL6Kv7K7lu6vausGK85Mj+MVhYnV5seqPWUOjjJioEyQWscstRXbtQ5b/uIjm2BWX2PF+v WyLUCDS8pbDb1/uL+PloLxbep9jn7tZ/7wOQ4hIFkFBvDdj4x9HppDm7+Q6LvEp6hA4Ox9S2N2Ko Dczf6s0+iAQfrfVnp+zCnNz/eH2qE/+Ad2W31T4EO+5+Z6chQSqIxer9iEbUt8lcYll0jOpqk5sW 7wL1uOnv6W/oIqpv9CCquOS8RjshPZSYcOuMQw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 167024) `protect data_block 5CAqsBX/bCuAvz/pLA8+ITOTP+PzFNqI00yoi2MBSJsfxHqrooSP3PMAs2elQr+nss6NZ8kXfGPN bhkFbqD3pP7HJz00aaiOMR35UZj69qWdZH2Yl3utu8p5aKfASw384HVf5Sn5Xjkbxgu7IDjNuGaK coAI20plgvxnsD/7djzePO5eZQFCm8+BjyxKmU4ACqXEJaFZh2DKHjsJCfN/js01Z2+/uIKsmdD2 UFcZ7EcSbV8ZBhgxEUIoNwAUow7OcwydJUqHH6/Ah66Rl1Lm3+0ejnr2Kcwub6EVgYDXvWyI1Lsr WMwLLKwVlOVXsYqQWSvBfCH0AtNylXk55Zp/1V8IHXYP/90B3OOGaHiEc9QeDqd1H5+vp6WI9JS0 tgoa+N+OSOvfUBZanc1QT2eKnNy67Lq6Ve2PshxHkJZbVhCaBe+qrdl9ZHYUHNxLGXatyHpyStPg FWGTLJe3HBanuaBQiejGVTB9lko2qee8g6nrlgU7QOUFosELTnEjia4CHusNzSBwii0IZw0jx8eD c48Agl2/oiN2B9ekeVWdI5V3ZdykIl/1Dd60rfmBpxLTyr+BidPj5Mad96QddEfUpJdCXV9CkmQi R9rbNPCF9bnAgoYteRfk+BA2T+ueNZesfA800KHP+fw3zCAgrLmbZen4FRf1usHVtaljRLS1IZbh Hv8B/el+cghQnO/HmOFyvYD7PrSpUnHbSgmk75vdolOgRbnJlDztmx4iu5KD1EZeW5cVYXBMUcwx ehWWBPgg4Yc30fAGP3EQ3dolWu49MKJZngf4FoxGPcZ8KQ/GHceU8NcbWN+e4maflR/RdCWHrwhm BQ1Gyr2+513U5EOkDl5IOJB87LFOXakvKnHAh6uU0UDrjdGjQWLUSjNqhXIgX0UFomK4omhWSkwI cu7wABedz8IEFtDrrnW9M5CKVwRoP6PsjopknWj2J0/5yqgtXxd835RUdNdjHW6IR7Ruid2sYPeZ 0bsmEb4n+G4cWeiANa/MkeGcVlsPaBHv9PfBUbuFFazh1qtzc0ZV4xB5xLs/BHaJrWtuRMpza/0q 2u8Dg9UuaFyrjzj8nJnXXhtYxrNc4u8xyGwLX82cWsQKwUfJdt5p461T4KleQtJiYyuzXmjhBABO NcC+XhBo8Coo4H6hkYPjQtdLl1dXlKUAVvOYK2q6huw0uGJyC/oipDpeJg8TnoM1AInhmxyWvjD8 OHdZyAFrS1S8/mJD1iJ7Mk3Fae227eXOwdz/tYziRNd9FJKnXzPWF6jXCsQq5eerYYl8oy0wPrWj LKeIPWRn0LS3+EdfUMxRWiiaQrpOMfyhz+aP+AuLhxB409iYT7FKLcawJP8FjpeWUxF2wLrZjhLn DpeBhGLUrVHh2xmu82Wxnc7gJ4rkqTxpf2kQ6iFkH3KzYtpvu1iRP/vP+FcngJLQjQpv6k+lCDIr nB7GSUlguo5WjzVX582T8tYeDOd9SHFxo04T5C7NdBn7E96Tnyx0NLcTncnKBRY/PoKqFRP2NA+F B9luWTAFkIiYhLpuEEyaPT1gYQhJMLiOJdAv6bq9+LzEjC67tV41H4al+YqAKR2odcaJOBM/KaZl hrEbni+kxzrflIJZB/W9N3GB51NE2l4WOTbSOSZ/JmEtw0fa4ixnjPD1PC4CqOxYsxfpPZqBSaWq o5kBjgdftoKduMs2fWsH5cJhhm947Q0OHFtrkrCCVY+i2sEG+pLaYg4MSSDZyTtRD827fUgEadbJ iyTHMYeN1sX69znIJ3enlzGj1ebgl2P6mNq8O2vXbbP1HmC0phaEjKlmwKtiaOjbLZAhBVuqKDgH uAGv9hv3OCZgDWbkMfixdIwn0+I7J0LfKTxPQJuCnnRcvu2MpJpB4z/7QaVjJJmqtm0F1vmeeLYh BdvKPf6th396otGuBuUFAubBXfvoUrBUITmzP11ZvJGSAmM4rtUjuvGqpI81jmJccuOcz6SY/gEn Z0IQ+otIquSYNzTJBy4hUQafxWwrrB1/sruSKHJOhrAAzdsl5Wzmb7GBo4qaEodxKatECKK5fq6Y elhrJiC0RktRT69ucpsbIUKQj+FixuSf2iO5IDW81tLQI/55vkc6n/uU4t7Hvurj9uCij12K29YL /MeODom3tkxVYH+GR7PRhLA3WSqupmYdeMhbqFn3CpoF17xgF4Yha9zBple3g42818BjyFbz+arO /LWzbIOBcqcolrGun766JOR3rxYl0jB5O6+SD6V6ZrJP9I0QmGVZuwxviItK9+5R450Q2LUJTXyO Y7QfKh7tgVXk/DLJyVH+7YIbF+lGTEL7dE+kCYGiL9uIp0+fvnjZyGCLxAOQOp7aIhpkCxCduRjU cCe0YOS0ribdob4hE7VnecfFjhnm7rDA9szY/j1espwg5QWpIR2icTHFSK6I+jCU/AZtIfGH69eD pPyyL+4TQ9xNOu6UyIvRNj/tbK9A2gFH8KuY2xJLQgfSoQKll6L9HfoKFPTd+2Irym3ShS1WdJSI ELpOOVXzR9imAoEvJpyPRHTF4S+ePH1PvVexCQPQObmN0NeXdLqOhslO+Uv45NQDzT9zLhfahg+G KUorBL+S1BI8ob1RQ7A4gjH4KoUFMsQeMNF4DIBI9x/lNgZhSeTpWQePaIzW8XiZFHBUnTe4QHqk SAAV+2x+pS4rGsrkn6QrvxhwLBCkgQEaMqmDCOI0klNiYQMt2icYwn45lqVO9nv2S3hXGDuSFcl2 qhH9I4FCdqodadKjlncjeH5oa9hhb+DS7Hul9mkdQbYdabtA6KIUwSLpLh3qBkAvYquUKfUs9RuW li0Dl8xDnZNbSRyf61IALLw62ycg27Lf0txZx/AW252K2VXUnxMnvDIZrhURBurBii3XMmrDYht9 Qrmtxn/6bcRUPdSH4Lg6du9LcmN5S2EPnajNu97A1RiqXtmbjyl9b2STNEixOEVuRvGo4dWdsEIA d/cy55ajrPNZ7Y7waAf9x8+LcGrxR7LQQlZNxqFOmOCE43XJDPIL4FPxxhyQJ2gV9T5N24sILblS 45TlyHS4CnFyNBQ8nIHAchov09uBgYpYfqfRFMw1a8eToFA/LQyfJxHZo2o2zC7pz2JyuwXEMS+T mBtaEKpKIiZvTorRzzJPPLKEp7P+PmS2DUrDfK/eCCOoP9NauYmMwVLHnQe3qeZgR1g0TRw0+qDX zs9/ENQU3r1RvjyNU7llzeNHLi84FIeQ4Ril6VLhA/owdlkYK9EP1DG6WOd6LC8eiftAjVL45sTH FEX+Tjz4MA28PPgVa2SHrFbMHf5YXne/x7d5A+LVkHhaCkknngxUZWDieWTLRxIqwD2U7C2Nm3u3 lQR686QkLbpa1fK6aDSoWHGwzURQV3bTZDxbopyNEfxN8SdNMAduqKonAsK90X60nVvqD379QlhX 3LbPSg44esKrpjc7ObfrmqIrI8nTGNXxQXD/FY5PBsQsQktss4ovRTY2iPbdUmjwDhZvqd/IGkIa xJluBITHt9UiEHHC1VgoyTdJA7LeIqgkXfJtSvguM5jG9L/4wU0Y4fwHZxLqLhXAL6DbZbnKV7e9 oQRW8+ngyDm67A7hf7SA8ps/cnA1XmrmYslrbTHZlDbqOy2Qk4x/uTE9tUlPYgTIEtZK1XO86TJX VJZ3+SWrhtvVdB8i5ggiU7zCLf+O/1stm7Jwvn9aLX/0Eo4DUcT42tpXd8yZPII5kcF6HVPtZhbn 5InPn35pZo1Qndgic9Cw8HTC6n4hjRpPfJYEAsJCItH5gpZK1hCbRSGwSEn686DAzyUah+IK3UdM 4GGZ/1nkSO+ZCajBRURppaw7WBJ27/utMvbzORJIpHe1nIELTESiNrS5YJ2TdGHsoPwWdt8exNbt Ex9PHC5VoQImsh7XhZMWvlYpKq3NZJnuss1Nbim/MFoFswDpiuG9SIefHwWu4sJxeFt087m8szk1 zq/1EBUc2RGM1qd5Pt7rfOM3MRFdpoDsOtR4bmLV0bER8RUANnC04I7FEcLr4MfcxE9UDS4Yr82x MK5MiheMDmLklf9glvRcJrQXshZ05O5svK+vAZoK7grm0f19mvF0LYUjbrk1YEafQi/tE4wzuRTf SSMtoU5lrvng/4Lj9wIy1VA7YM2s8bnKOzAV9SBimynm8jMnqnYu2WOjH2iZGhwnP0oxoMo1MFN1 uVWu+ioDHa8ZaaO/ecd+LToelWqYaDTl1nZsC7V/1r0qd3ktqCCjxrCRULU2SeyKYZTt15cS49MX Fm11Vp3ypSgeGnWs+9MlAjjt8RXnN03Q17CW/EHXDw1ooHv8Xi0hOIOvKDawAYsUHWUj+yjhJiXq eOtkE4bbZCCD0kNIq9eAwFgC5Ojdjo869vbnoGygMVGx1e410VPwNiQFdosdxgkpzalfz+VCpZO8 PiSOtsYVJqWW1wLYlkDCNqsJpsgYskJ+Vxf+Nnhw4gNNCIFSmSMgBkx1xxyB74VyWgfPxWlgLDT+ XlzlfRi+MOrjY+qFNxNasWzw4LPzyST0td5u4vQBUb/ddviA5EMzSBd46nvpp4m5q6qPasxIKYpD cd2rLM/SP/u6GmBdk1qF3SCXybUT06boaaQ/CdqIJPwApd9klNnCpz7zsiMNWms2JKmKQo3fGPB2 3j9fnXRxr4T8GQ3zl1KbktWl9wAivFAaxna8Zk2euHstDep094attKc/ANFeebICwJRIaUATJyxV vZiwgGO52S925FoWIoVjDiCnLgUqWarPrrhrmLDCgfslNIn3v9F48MEeBMIgWT+Ozn+8/RPcZ8us XrF9pCF7jkLQtZL5VqrqajiNOzwoFPUKGho+fCM71NneNbIn9DgaSgvBJHQm2FjvCduJpSYQGTvP WqMItryJXDNBvLkac9Y6i+mIgiOD4lwpM4GMfw4+6XRzOh20+9W4efj8P57LCWa1tdESwzbq+twS pGG9IXfbO2moM7+i53vBn7rRTkxiLgRePNUGOgwFkUHp72A3+QJY9HyNVTFbvOWo8+GVxzDhedYb 7bREXrM4t++GJa07p+kvuX3pfmgs/V98tTgjPWREhcLY94pi8kfO18ys+VUV6p+3mpk7gcWISIIf GGtW0ve6C2mKaKw764VvuRQw73ZAzDiQxnhBGmlrj9a9SUhgX9yJ8x3NCD7NoVbQEqI+ngxr00Ct h2holPjJ3Ow2hpSMi4aLsc7AEBq9BSN3LcGTuWdKZAJibjiufNlzTLW9+VkUFdGWsw0Kbfhic6W9 tT8oFal0cVmSLdg2ia0MFVaC8UEtox3N3Mw2480WDxC5arBBRdiUAtqz11T0uG3FNk5y2a8rQHtB VnyIOlLotF84tfZcbs5mwzO1QXP//WZUvPw//3f+pCvamZsQjxfYtrjWQaau4mI4G5HGJ3nzw72J ciwMOb2WuTowtJavfTFMzi8gklq/2Q/u1X7P+K+Ccx0yOKhzTPDcBJPcsn8zLkWQUknTNJRIGMEy YQ9lps8beV/A7c+KqWYaKpKxzgCcFFvdtvLnoIepFDvkVPZgBoP8VItkvaUHqJviwyPcdoPg3Fws gUiFEFduDuy3AB9YUJfSPMzmtXF+UGDFubsjm7cqqAzT42Px71A6GM9A3FZRKCBsLel2E/UwKcDq UiJEsOCA9NYtNkI9ApEBrADmcWOKrQFU7OxDyl98sN1tbsn/6QlNJTzvpcIpp3X9Nvs9kczIpZfN Fe6dVCONBQNm/OHLWJ1fnqs1myyd0KgntopWojRYK/sgdL1Z4J1LtHlewF2biKBJWQ+K8gIjfIos hGXOHOCR0N99ECi0XFnCKugonGo/M6hJ3rAq0fkCs5Ent6A656w32E9QXfiYZ61ePZ2bDz8j0uhr WKx7Bh2v1YfCW29FaiRz9wvP9k0kqAGzLlWVL8b1Zr4Mdf3AEIn4iCQvIhHdrc6PclFGyE1fsiFA 4cFQ5ssl+jHKZt/yy2Ax8Dh/DnqzrOocBetfuAPALsTLn/4LnadvBrZ6mLGq88gaLpxE7FG9EBnh Azw2GBYyJklMp1ZDZwBTXZ6gDWdHsyax9aLfz126cQh+sk/EaivDSSeEz5Ui1FJ4pGnh0zxqBExW +1zja/nqMD+e8hO/thri2Vp9e+RUAcrQ8XZRSM8EGkG8HV3lmc7L2i/9jqiONHvF/ztLEq0chBOQ 7lXjeqrK3tW3B4VwOINB9M0cbO74wEmpJmvXckR2ahsAAxNdCXRS9oJi1Oqja2XIzVwJkh0I8e+M kOvUyUjiGcRE9lWVkptKj32JobUMO0kdqL7FDu3KWjUZbiPXQ/uCUipJpUdsVV14Y16g/qmUadST c/IDmY/ey3DWH8GpwDMECD2z8hUZxDjkwi2BrPqWuTcew8CGcqAEcOMtWLSxtq83Iou/g+f2JBho jvIkG0z0QGAKrbbwcWCbRZJdEU+r4FjdYwZbGkMC0rkKZT1ChAc/cmC4wfMajSxZPGjR2ybRifOl QNOl3eprUhTzTnYiY8ac52jums87u1SpPIXXQs1WIy4uBGm7RdvWlZNnz7Mz/QFW/GFH2OKLkc1x 1m7Esx2abMURA02YOjA7q4vd7eF9EZrbDzAo0FuMrtsLMZea2kAbkSw+OpP9jkzoAbiGyY3m/wca fEvudpoq1IwczpYu4obwB51dgVHMg8CzBVL+jiAo2764WXNyl8l+1KsKfQtjEd4NF2WyCqxB0i5D bFESVfbiCcckrl1JgbUD2jbZ0gKRRImupLjnEfujnM98FDRn0KudaNo5BK/9GQljXcgybo/qVusb 3GL9uGJ5imslARKSFmTIZfg+gfl/mn69d1px+XDwynKUY/kcck3CJmUK3LtfuC7h9NQ9O/wRjABi K+SQf/XhZghGMKhWp/KaeR6nCnwIhVdilSZdJlCTPorE+7x5IlaLgoHQP3IfoweApvNQ2WKLpiaR RPkbjADlDY6QqO5rZ0cS+yT1OGpCOatowsNaoxo1UQ4s5oN7IeAwsVjtNodmfFyy+OqKpsER2jty GbEQMPUf4upoMF6/7vfG/VfSGGUvKWKQ6zR1xpq44LcFsr1PZ8+Sbt4BM4fHYnLlSr3fvqLHddWR mVp4slWgE12kx25jfRFbHKJj1d/MhPXH9GrpBxEySvZij3vTzsykWXHy6gfEwLnI+Ehm6hrIxAji XfIaGHv84IzxhEuCc1Sjj0bjCxTJVg45vaNk7EWRuf/fiE5T+QsO3iPm2bbbscsc4ynPJHhajqS8 wZw8poLEg2T3/IKCMRMWpNFnf5Gev2OaNO+jMQzdJ795VbS+XwPC1gd3k+22aDrPDvY3UtxgFo47 CgEOU2Hy5eGZzq/aRQfwGHcy2JqbBP5vrBgh+YsZNUhpeCnkgDX7/2MOP1Iz9kDS7O7pP1daJrYO D79EcWU0zElEOVkEFwBJR9Fe/VLRKcVjxVmiDFwh2y0db6jaArMev8b5EifAWoPlsbsXQNByoe/I 3qRcpRvQ63XdMYu4An5ChMADl8HRx5jxTAOdB8KEFe6CV3Slp5JapyFbCR3giH06KRuLr1X+EvqB bMNTKys80DQXJATwvhzwv58aYzj5SgAZZNJLXwwf7H8ZibTiVE31n3Ngxxr4e8s1vO8RWqF9lY8w THmq9k+X50erGwDpfOfVlzbhUprHzLKYmlymJRkUgM/iiCa734IYcmmZLz7AknSZRvTCI4iqSTUR RDodd6FqIAZxgkaZ3FLnrSeJaDqs/Jj37F3eCLKmO2Yk8uxiWGiELZIi6e2H0scB9nlKHSqCF07U 04NgiDxYYPUTWz5OaurI9giGpo6NXEBtPms12kkmlhEgfnFGEDNNqysmtOQUS8fEpsoGwys9mbFB +6DuxSEFqMHhKdSPybq5XBaIjwVxK+4ZmS7ZtHSrL5OImm0Ykkq64J7/O0nl502YJFnX9nEo+Kdt zn51u29V1kH4b9Sg5Ok+XLhkJ2M0W3f83/Jvjw7VhHQ2Gm74t29Kj9xlG17d15UbHjDdDdAn3RKA TRApFEzr3zFvVeBNz3nASp3klnHVZ2/mnR3iIaWRy4bVIwzKqEOj6lfruNCWeGLZvhbU7VDR9ABs ZWx/e3T/eLrORCCWxLgm+zL6yKllN9TSwuZWr2krZ4wjPgfSIWq81mnULRxB7dDnXxIN4Ei4Avvh 5WgVmfwEG0L2kDqfkQy0gRMk4iTeA1BfHrenRkaIUspaxbUCJtxBFPUQgAUURo21AsWFqrQwWmbJ 7hzaiJHn5GB7bnVvWfIeRToI8isXJ+nmEFrmFeInfVXykpOo1tZC04C1ituDnf5mJhp4RX8Vl/k8 nJTXvEIEOW4ThmpfJ/xMZBKBlzDxveS/MCSztv7YNY598uGya5o9GNTA97IAQCBQoK91+/W2s+MV SHlJm9t2OTMNqmFo980/SLXeG/zAk/7sVOwljZsbIBwgvL4ZrsOLoTi9OUu/SR+V4DaDFRMoITbm xi0zfmroSxPDNs9BGsEBmSP5Zcptp49xSD2iWI+oNy+y3F8Sc2z/X3rvuGxvCQBXHc9v3hCcRwFH kB8G9U1h2Bdu+yshBvtIHbxoDBMmxGQvfgeEOPW0nufv3qDQHH9fsYnYCuur4fTNVIYzAR28qzdu eSJGqvZ+MFIVTfYuePSzWTx3rEnvcC7JnNcxoQga7csWyT1yxi14+Hriw3vOqiGmoSufctaFpm6c RfzkI67osKUwonl+PqpbzfLOXaSfJ5AA6yieC0Mz8uKxLcUJrmEZpYhi5WDMX/WPwBg2NeJBeLA3 Qhg0/ccCqpzzWBnAMIgC+VQy+cg3dutRpTIPcQVP0TelzyDV4HbfQT1DzlwGRqkSW+OoGdzyVviw 36ZVDPkNGY94tHQAHsBLoL9PfDJShnBfwPO55KjNraov3sMFswOGtGHzcXxnfIVeUN2QGPr9e9K/ QPebr1KZlvP11l3YJ5pG3pjKXYa9KojGDdoZLLVHKsuwzEBbseT7gfBLQukup56e+XfFwOPjEdMj qBdqazQcVPPW+p9eunmwquXRdHJot+wFy5Afdnfl5E8FGsn9qfXWPHzKnczxyBrEgZj97+CEO8bU 7JB4of3zZ2yO7EqSmigYl0iM2TyetoOR78PUudFmyYcYyAgCfAhO+mhPEWa9F7JZePxuusRFHD+v lDvcvBvCCNKNg7fNogY8FdSPws2pyciF2NZAJniKcN2JAhVHKioVPItZmUy6tfLsDexuhB6QXSn1 xPBYLvU7uZ5qUtejmzlTTR6ZH1hx/D1Uofu13kUhXIHbQgN9gGOrKkq5bQZy4O/mt7oo0jryNyVE aEAn52lAv3IvkI8jbPMUTBJ5zCVEMgmXlRg5A0U1KvaxqXLUS3wIfjLlmKx1xgPf5Qv38hOfGhn/ 9A33Ix2NxAVo+H7bo+JjW52x3StZoHtCmjucPXASeBI2zFMGhUPNA0/hvbBKvpYDnZVCy6M0ooGa Bc2z8hxlPYB94FCiWdwPrkhv1T025MLkIaX7+ESN6/I3AWbnq/KfvI+G/ZSjbliOKpTDLky/nk/K HYrZ93NVexcZ9MFL+DEOO2PnkNfAYCdoLVQdOufWdnuQKGGLFRpnOBnl8JagLN31TZXFA0PltVoS 0EMVZexiMnSvo9VLLThMtXHRlrqEQD9u0HYjTrCPxnMAbKIGvJX4YM74w5NBhiO7kMw/dCaMaE64 Nws4AlySGWuABDju8M4c9Y3R5+r2MNvnDfy2ScQuSvz/TV5tRdQX2nuRVnZsNPGbdIC1cHAgIMmG 3xDea9fYDOHV/LPCmTKmqABc48kCAUpCaER/mDKROX/ZW8lcRaXH/DT1BI+vKim/fbGqetFHBXsv kEJv0lVYTta52ZwWVeWH2/d7yGq9fYSmvHZoYhOz6/K9YUfkY5gnbFImyB6BJiE3FxIPWbq50Dmg 9Igyc5Sex2tf7GEaWnbfWGP2olzKtbGTXLULGBXVY57nGEM0lA7u0cZQxgWBtjGinoJ2QUoydqlm VKP7C5nC7CIkMV2zGz5EKcNNHnoCk0T8B2fFge+xlWiuZS9pZF/OobrxK/zLiI/Aqk8yGqhjVCn9 32InB8ZLBqZzZ3cK2yCxH7cpNwoO/AxeiHhOtp0nYbNNThngUuL8+gnqJ6EfiUw4r9ADj5o6kLlp DT/YFGFo5mtchmzLYGoiB30JrV5zUJOCjNknTOzWEn7UESoXn5tpcrVamgpTEyG34YUuYYao8BM7 ScTKA/p77xMlnVPiMEVhSi2NG8F5mYz9gXbC0kvD3Lv4y8ne9vH48/F1P8UifpCX8GPcehuC9eYH 2bdjSpl+aOSzLGDier6diz/75WpQngmwypKw0JKu1qq/jEjSyh1UvOCdNZuRFs2cl3l5qlCddLPk PK9WTCHynreuksIjIdanjjg7NTbZ29emcv9DSESBB4ZnhuZAZjNLU/gv4O0osFTeI2E1FF7neZaq /kvp/7agheCFtGMTofakoFXmSJRPoIQxdI0tvT4In5xSl2aSekFa5EzXpxH4EKeA44VbrcN7pSp4 8QpsOOqSwbZmTEd0+6hPHta0RUole5pDdv7AlUlXV3Gdl2kjjeSwfURk9GsV+NT07xVSKWZvF/tj E7j+PFci8/HPT7YNOnIGm2UskqjTazBmd5PUTuyRzgDUjoqz2ShgAyYEypSMhtITKiMRusqUndCH yGJBnwEyVO0lng+0HENsUHnS7fGKDBy5cE5fDclcYuYQ9AWEkf7VgO1sUwYmj7MKSeY6XzA+MiSB B2xSAA6ttrfi6VnSzsqJpXyIAiin7ChFbCq51IHDA627l8DARmkQwrnxrx0sCrTz0VvL25rQvWtT 5L2cfZXcJM2dq2RM96PrB3dInCpjVm8I/n9uHFqEq8NLG/zH4rWs2d5Fv3/2Czzi3mqTtjHD/Y2+ M3HpxVhsjGduzby7YngPYxF9U804jLPM513nEAc6iFBA1iaw5bXefqNsb3xu7ORBtCplRo3jllhL CX5fE08qT4Jwaa6PrA1ORtPmusXXKnScwwWHbhoyynCmHp6i3aR+8994iwa6qK4yZxD8ISDHdL1S 9rOdnzjg1pphdjiJzvrxku34ExPYncs98Eju1KkePtRyVZ2hICzb1Of8i12h+H09puQuMKBQ6dp6 it1LBjvphQ+r+AF5yGtx54Tn8fWR4pgNaAmqeuXieiICn0vuSG6Ygq8/2V8gHA0w7VZ+p2ZAtQdc 4Ro5CQzO/6uUm7khRiI2XRpSghgFwxk9OtzY5uIPflaGLFN74cgndMXuVvDnzF7Txf9Ry5iUhU8K xgWCdntg1nfaecMngeEuETMD3//HsaW3w1ohsKKgJDxU8ZM4JAvImj3r/QF1JZU60eJ3cK0bVmKd yRkMSM5rELER4Qfm1J0+VVFa95JD+JY4+YRcwQoctDJJYoZx4IUv6yYdq22k2RHZZ019E/YlWWVa 6DtUNbrzVDKycy4kGWDD1sJXOUWTb5F2JV21+p1xl+syAxxllLdhKcGfB+We+ym8Z3CoXE9pYxsz jZxFuRn30994FGBg89Ie19lBQM+Zyv5WYxEBe4um0eKuumUNy9mQwZaa5IavzW1oH9CVajEhWoPD rle9RmGHtOhi9BbK2P+/JDHOmhlfMD01If5HzRwxhFJqSb74QE0zJoOVb/avCEIcO0/0y4KF4wFr TULKSt4NE7CNGtCYmtv8BeHpOaEg7x6ZGNtRNUVSyHMpQt9BTEVup3ATR/5v/7lk4reqhaYQYXl3 NIUXldPeYrlVSQb6nd4l2rlmJfqwFBgWFD9etgzPhKpl/+fSxmkrbXGFg/L9WGMFWYWiF1gc0Jfc Ta63EhqLAiITWtuOKoYanvTif5bjde0O4Mv0YMOY9T/ghyeEG7WsUUc6dIfThsJIeSH9iKEW+Jun G7XcXs+yJ5/J6Njs5Ocip7kZl/pUTdWRehh5xn9wrKTvni5SWPTujzriYX7dJ/0fz0Ffg/c/G8xH rtk+njnAXhSi7HPQJg7Tnt5Iy1kVip/z3IlRxQRIto/Y/2rwcNyH4TWNSrTxouVZOSVW70n4VjZS lg+1hpw1E5CGz5PHxlKgy2lR1RjhWw/etLC6E59DFeG/AZ9TzpSSGPyKyJoZvlqzOosaQ+ndNIuC LNQy6TtkBcDoVLzv2Ui4BGcQWh5aBxNp2eOKZRIxzmcUTtwXJt2Gt0nZ/VKlzdVP/sxKe4DOd5L3 v/DlmXIKXPc9v9bDH3vd3EnaCYxlYvyW1tuG7E45M6zdSMxnM+ckSAHXhjZxQiYbJs0NCeFlQu8a ju+BvrZIqBpv0eerMBfS2ZaMBVETuHubueC+pTy4OrKTyXVGLJgRXcda9V+58L/P8yo6d99CB1SV f/mtHS9FSHY6NL8X9afbSr9mDnx9u4ZL27/zRJe1wDJU7DGnD8U2jAAJRvAs20mEoHkjdkh838Uk SIGGoWmk+YEv81OYofApWRYL8mGzlgTHzaXfnmHOa3EvPtpm7oLoM5YVj7hO/yb7oQ5JmLyE3nT0 iG8rHMo2xqS3mLirwJAA2GiDqJWEa5SFFV+Fjt1FXn5B/KCJwm1XCysCOBcM1JaOtu8q0xdWWIjd WGui05iODPURxlSIG9/KzUy4W6KTbT/mm3jrd/CDifAkKFfiKN5mjAIHIDWHANelozogYh2eKhsz Yv0y6wihUUgrUqsnwbfWrAONyR/fUX9MlOpiI3/Afsa5pafLv2jYDcjs0MHDlWSGIdamyISBXeoF x+LOcNXIemnbzTLQaH0cWhTaxgxTBJ/GRidIQolumyRF0dibS698zUMfz6lWY1fIOwPW08lXbJ2r YJYQQ/XT1LFbUM4npk1B4eUsjgfDWO0PrAHuHr7ZUfrEU8uRQDz04pDVQi2VCAIk9/g7cqCXPuN5 lvMeXWfGWZ33swe+/Y/Qqwk2+ACE2pbZY+/zvfLm3LdpDHYb13s2JrV1GUcITlRrAy+uPnC1NsQB aIfajVDXmMvJKfwCruGs6zsxq30vDykkHsiht4UEkdBlO99dreLuu93MpZ73omwxoCQlyrlST2NP wMORb+f+fgMPpWtx/dZRbn1hHciGRpgTeRXTrDEYOHmgb0sUGZ1tjv5LfxVEQf4r+6evL5xq/VIf eXBXqQ5RDYiJk2EgfQYawPVcFal9L4i0VfOtpcEdXYXH1fuwMEdL5gEHbQ6X8/G4lBhhEh353Sdn Eh9BUFMWTuOUP/HRUYKxd4IvH+NPbrRS83lsQ7JQDw50uVhiqFjFFk9DwE8vAIFPuMsIvYPB1Dcp o9DE8m5zBF8QjDnwK37xkTPPSrJyfe2pbiQ98bfW6RDI8hG1HNpJSqFOrIATgoh8kcAYTy6jUCd4 GEWlwgSCnf6/LUGj0JlGceQCj7MGIP1OHIxfPPXKjI3qvw88u/Mzzq3uP+j7ZT7Dk79tAiJJ3sKW CTH1BOkmzbYUFLYXS7hyU+ve0NRXB+mF2+1mbOYsXomBuuJj2eFWBfb8ZsDk1ddrvopSKkQBrD6/ QbXtmAQjn5Kqr89Tqlb/L3eKk8N8KNymeGHas9UtaShE5IuJ/kdZSFz+9av0dHyP363stlNju8xw Uvli0VfXFKzMAnx2E0vAFXlZdAP5y+98J94c13ltnhNlqQliGSYrV5OyHR+FmiovKWL42/Im5WQh AI3X/52bMJ5P3IEDxtMYWB6eN6ejsoR3raNkHrQl+itY73edzCizM0myarwvNXDEPHBi3lFCHbvM hSaK28TW+bvcRaNhJuj/3hxJzBWTpukbxfo+jTGRd+BliF8bHDH36y6uWxzCBlAm0iRzdhLcGCN/ CsuC8td5w/91nu9EOspUh5Op9tqZHFYvZ1KQY9wCaD4WnBWR7icd0yyDuTpor3WVqJnNPj35vXIV aOxOpavCF4HnaV5c8UyDwfuKKEuAkf9HbLzgTToYNNqfmez4IpNbnR3QXcL5fvwUnV0exMpXHXxA aS07bNOPvVg0hew0B3d/7mRQEc94vcMMN3LCJ2K2jps4QqtUmgz6ys4y18xXTKt62hlRdAYWxkmg 9eKkeSkNhtz9P3iBdSy06qjexscl94ZZYOvbBWpaHQHtcDYura7HLjv3qLRF68UST4Fh94dg/ZIh CftqII5uhqfHqDw3R0iODqU5/0AceJIQrPfjQcWAI/M8t4nyvuKzhgURU5LOBvRRAAGQ7cnaRp4B XLCBiNX9n971u5ehBCKRd5j7jgXaGczNs5VQA54p/g9OGEzJLO4OApI/oucEyW5VuC5HvCp7IbKq 2y6Fsaaq2BvLd4ROuVxy5bYMTVUrIvczyM1j6g98Gh1EFBrWzGDoosRM8wFy2MVR8/QKVANugCIx XyS9pMG66DDrFC/IhBd3pxAdAaYdR1mgbwFTORPYJRDwrCMNzzi7wyV1cMPoB3fqCVrdJHeHQNG9 D1IQPBgyZfUe2uth0f8k+TCNly2+JEnHbUQh6mN4mNTS/e0044OJk5MUDIii3475FrrimfG4+U1i N6Hx6J1sx1JhMNBoTu9XCTv/tt/onbpl810PIe3BebhwRJdh1CJmQvSFVtaY6lIZ5568p3rYKCCr MhUx7IYmOYftorM3bZC83u9p8H2q2ljb8rqzreJeElU3Bmtbiu2NaYRWTzJ1tNKFEyuta3lnCVW9 awkdjj9XrMCtEggU8Gi465g87l2SSuDMkN/9r8hiN+MUfKu7V1HJDP9gWYDUYz9cHfpUkB1mlNul vUav/Qgi96Rmt1dlWafpSRs3++FRomn0I1+8R3oVayI5cD/QzaPwKnn68bTehp2ijia1eeuSnQEw gHmyjYke//DJD58qBr0O6kPmd3q2htOlnObe25AMnWLTBzEpcTsTYW+gAmM8EBGkmH4FljQhdajL +viQWsS6GQ9K6VrXbZcGXtWVj3NZT7RMPr61V1gZleq20GOYLvuZBmJxnaT0GXEcxBk/xAb54xbZ 30Kt6xsAekD83LPg6dKNZk0HDYgf6UPCh4Ix8t3DTo/22fkQcBwRpeqD9+ML8UhnR89AxzUZO/+i TjFDLMF/gGcFd5ddz6Sw4D4iE9hVFnwApnTJa6BQHSmX5WqhSWBaAUFiDnnmU59yBkGp7Y0tJidO VhhF6FqZeqvm+qgvABrNsEDXjBZkOA6O1/ncjSnhaslRk4V2kxc021uSJVEZQPX/NEAHiG3g2Keh +6SuTTpBhP11lRS1B19fbWf474rAXSr9+eV68t+0uBdPEQ0dbYe9qsW7rYi7srzkOizCKJZmwLpf vrVg+vf5JDgtzxPxFzKHaDuJd1i6itstQlnsw/3wXmBAntUxO/VRH1cttYiN2eLLqDyoTUAjeF87 JMLhkGP3NrwUguQnNEuGfPEieQanmqSLnlzMQe2NNue4aEzEPej4JmSycoQ2BhgJ72hyv+ICf71I Mv4xGRSuOkTsTGo/45hUe26bFpcUEM7AqamWiFo6zhH2/IGPirzIOZgCiSYn/FZLePD3CLv8QwhZ MITeMQkTHkeynqHxpPsQ7ikdQ8L2mVzFcOGsBkaMWJd5GlKk0GafHFKqtt1hA8MSWLhL4vOegDdS fSYiv4Fe5sT4oKla8C0Bp2gh/95WrBP78MbzTAp5yn14BUgrvG+IMtRjcsxQOUVukwCdAULIKjJr jD3GTlZSIZ7ZUxBEyubovxX5tGBJZD+7TO89E70zGQhUZ7yQEUJg5ivOEKgRQGCyh0W0ZHAfsUau 4loe1jcb19texwlF25bZL+ZpRE0mI3boHppRWdDJYdfht/FrLrhyJXPfV+ZFef9vWno3N0us1vEc U0KHwfqkJM24XU+daRY9Wpl7r+Wpd8R6tDwP4aVjFslVbLBBs/E41Ojth6UuFbXtC+mNuEhaiUZB dtVQ+PK6dZyDkzb2bPR0CAo9/0D5CNFTyc9xvwh7rrm3gvD3NHo0ihklddBsdsILdeVfyuZlT2H0 qn9+iyWdZK1OO1MdOhnRg0AXcwdzwwYwUXQgcr3VsY3Jk/c0q53pCEkatUSdfDmrcWhlW7nqSi3f n/YdGCkp65xqy22GaBJlczrleL/YNnCVpQkh9qy/FRO2sD+MFiClKfCA3p2d9nPjaUFwxFqog7bE 7tLQPLh6PkC+jFd+YcUk/XPUObmv684zJKewXySEb1lghgxU80rnx0fPsWNTrN8z6FUEmn0dK9E6 UlMGVdKdFP8NqGuD/FvEXLh9jvXuZazDJb/O0o1rqYJbzQgzochaHdG1HxZGdSS6rl/2NuVwIupu fVwB0jqy8H6Qo8bYILNoiz5XPVxwKO3qogWseizlO/M9AzLfMbnroPp5Eo4aZ+AIvSRzF6FfCpU5 si1j4UFN3NTSQKvbNgq1dmqDnwe3zJz+ALJoYfARgoRH/mooZkZJ47ZabHca1oVySkhFzalnJbmh LecDGNuh/Fz6+ni2EjgRJFeq0cIdXS8aeTK3i/qcK1qW3WxSvypFjIfQijIZj6pKFmT20hl5l2P3 iQSz5+uHOitF4fHZPBARPgIcnvPjSGt6XqQzOxM4c+Sh3foAtGufrGf1JLQMgXOjdQlRF1+CDuOs 6Frpw6LAmVWkxGGUuh0/jjY9uWXriB33swt8j1w/L18ZfQmeqCDPi4+w0W7kQSjWRDvFfP0Tm8p6 WHvKPTP5loeQiaQcysZ8BJBQwcOv5mhhql3XHpkp3JQFJGMoQbKjg/8rxwwXMlBGpylH4Uago/rm J7S6ytRoHbMpcKtaCOy8Ih7pp8zBiYfTmXd4rH0kjpIJot0WVzunvfODZ5OY/svj7xkbDDqcOUgf 8+HsUNCOKWjNHxZJR0Z1/xIQxFQLd1mcRICktR64w70gkae3X8FLzqoPmf4xFySgc387uHDIfHUk F3fMbri6j5W3R6lLILoDbyGFO0HEwOxYVF2kaWJ8OgXAfsBqus2BqDCchw5H4jxh8jTGbN4+h32d 4u1jNFefwAkb9Dy7OW42DYCl8Gq5gqFZ/ytxy2qUK/dUEI0fBQO2GGPYE+NNicHi89tqJsNcLZkE tDYKMYKHdb12kCIU5YMAijkiQjjIKIP3GoAh3w0vU9+SaKHjEicP+e9S28EXpQNxYqMkTTssjOnt g/jd9CBSW3W8/w9PN/yt29+nzU0mwK7k+G5hU1z/tu88jwVJOx7fQh2mP+Hx19OLCKUJgi+eSaqG 5Dlv+ZJ/3YUIvD6MZ97SDy9UceNRgt17WXVAsK5mQheVNENU2SAO5IMCDyUNVV16HV2L9uEInyR6 KunmyoY2iAXUl+qjYiw0fMyFIXfTV5fU6all5WrXp6YWAjxQIcJlkoNEvx7BjuJfr8NYPrR67tLP 2MIhtnMzkh16oDABwAUnAfKrfzrMaTVS0yeXYDlmaaTc+GAF+VlKoCWq4B4ubb5akIA0vHqrYn+P X6qtBkk6HQqY4Vy18aKugFZDkRDrRaeP3RsfO0F2CfWvwpEFNv/aD0zaxqHs4d2nwL8DxTl0/T5V MH8jjQvXHUl/Hv+RU9WEczPAkqhVNWZt3fCCNDIjxmkT3GtXmyR+XcCvz7l8Z3kQYqQb3LwSHDOY 1ub3WM5aFuWi4x9crTRE/2zUdObjLoyDE8XcQOb2TIQZJJzWZtAHRt325UePoeT/KyCv9yobDFVj sRYLIDtIxws6+g2ZumMGC03/n7mOoW/HGx5URvtWw5NYdPOTMmJIS7BYtD7RlXQWTx8c85adEqEa xY8U/lOqtgv1az6Yr4AghBVRkTVQJ/uxzM+xveghtfuzfbrKBNS1OKzYopSvHbQ0ItVbzyL/kIx1 7PsDenIl5bcZqcneSBxdJM2jZNFzJsDVJH2AeHvvUkWKFFM/hSEfTHtwRHwbQfnSG4xwttvq12dL jwdRmVyhlClWa9miTmDhioEauvQaD/silmqhTQsnG+3Aato4huV3i5lYZXVgRlgiKSsf3l9/BhDk iLt8S6eq0bGQ5XkY7P116ztUe4bS7Df1oN5cMWrjbKboTm3bodqf7JSBlmgBB89tTdHQdNb+J7Cb VqyV4cPghhbWe+xZk9/5+bO862RgQw6J6v6raE3nBhVopapG2z+77Vzf5n+ucPMgJ+NxG0R3NhvS KAeby9XI6idMj+l6l8J5IIpyzVP5dUFUd3sjk9XNY5nEaKg6CehvZH/FLzbGBIJgkeRIZCuVLzUc zhGnu6koWj0F/lSQ1k+dWZ4UPZa61DL1GH/pabQ3xejDjsY83kiuzV+pNzc9GqXiwlVnlF70Ifwm nZwu+5aTzPsvM0afKqfERxbndfu/yfJmdRMr6eF6DTnIOXpx73BcIowUzDrL5zt8N0KgBPgp4R2y 5H8cSOM1cZem44k5FMTLPIG+u16uzZ6HmnABCrHevHz+A7seKzcUjI6TBdlwyraRWGMSSR882iUL WqqZAMelSWfsF56f828gM2dhpUhs5YQBnzbeuT8OXNZHLI+8PSOUSLqzHMhoI+mvligBQhIV2Qoh kiFRf8YZSlqX27RWEJtR6RDZhiLgnXM26/FWxdwraXEsD6hBaitk9bgsnIqS17Zw0nC8bK6LXSF5 lzRaZos8erIdH5o9fGmN1NRzoilgBCcXLHwllvkoYruIBGWgOcraXxyjByYfbsCo9LYh5UXNGAMz wl8aGprKqc7JNV8u1y4/Z2VkyJK1/R6mhyOkw4Go3Dp3nDGtD1A37hWDWydBT2kinS7Q5yIIk60M rJ8k7Cv803sQT0HYzoyu9HKtI+okKl3FFPQl5ug3190Z2Y5whDBDFtWRRrfHbp9cW54XuUhW5oPQ 7fLVDhapu32ZNYC+YD0lCWcpSPrqFKYdX4gTEpiVkGU6QX30jHs7QbnmOa78z9lFdVjGot6Ll9zN MfoLlUFdD6xeD1JB9KBdFYvAomKPVQ5gY8zzFgTFywoEVjv/zEkTDFo5zScTZLbFNrZbd2YKcJNe DDp1m15HPt+uW9dwnpsWOOWa1Z2W5OyRz3wOnHL2tHlZm2UdFOAZhgYT7d4xOiOgSDQos1vay7aL 1f+pf17Y8svNSOufDiNcCOc8dYaNQI4vwkykzsoS+Kz59OavhaXoARMQ1hEPnVHRzqVxWKNcxSiO BEkc9IaF5yLmxgCKOpn81Mdmy/Cnh3NNDm9klFoAUXBfw+lW0++XHXEBuQxE1/4W3a1xBsEU2Ns9 xlU6LmMPW0bGLi+QcTlNlOit4qW74KhXI6uCN3VQxBAhvLSl+fkPRQRCjTlhX5tSbQ0LhFwL3ajM 5soO5wqGJ7Hi02IKCb+6x9P2oLyOUmExKmSNFafxNQZ7Y8rjCeP4/1VR4/FqCb9DpVKGQzBZPgPn JjFdExYZhZk2u6V4rF46d+LQd5w3TMZJs24eKsI6EiI7mETdKnGfwNw+YPyQXpkzFxvQEDmJXTH1 lS6vh2J928bsrsd5faCIZ/9DaajgQJD879/4WyH5mkwEiKoG0YjSvcnF4O73/arY3xVVRLhFmV8+ fGyKHmTVQd5zPm+m5bOVWMEBzogUJLjmHrXhGndXzs7TfRHEXEzU7kTFfdFfMgp4OwSnjtlnEzQO AYJuq4RuoKoYMvZImagpjX9JTif7nTXYauymInHe7xqWOBYw0uWALSNr0K1+vZZpPQXPDto7StMo NNYSp+soJFAkMIpZGp9sQHyT+Gq2+9RjE4ohpBeaJ7Bq1dgerqS+ZSGRFQWs4wRU3Vrnx6ESVLTU Ate/rPcMPh7DzRLBUQ9tT/nmGhLxUQNb+mRwbhIxnP2ew0sluJiZfakyd+W1dCmcxwQxwUjRwIoW 2EUq6eCxv9cdESbLXsNFfskflJbUV/QkRufj1eQnJSvZeNdzLEMR3HxihHDoITaB62zGlVa4dQ9O oGlr/Crkn5tmQ0z9OwNGagV2H/EK3wVsgpSsOJhhH0g7Gx47a3eT2j4ZaFnFAp4Q16KDZ8bPCEED qoc4cKWXLxVvat0Yjhldk+USS3jAbEgipNzO2Kidq3eoeI+D++A+lh3HXm8nMmXFWy0wBNvJXRGd GzxZSYxMs7GipYB6UgJcsaB935ImqwJHY4XufNEeoZ14MXYEpY63gO/4njm4AnVWQkb+6WpJ0JBN Nw50rmnudYHqmrswIoN/LXFYkApo6UdqF+IBQPURYP9rROjjmd5Ih8tzURxjYiu8EcI3/+il1HqD 4cbGkD3r/dk1toyMcR0DZ3MhJ5iYd3xxITeVcivcufWq8xvKloSJK5g1Sy74T0xCMSyDk+a+WkoQ jP44zdXCXwIJoE3F+ZyVWA0jkn3OzjtprpYRZ1KD16Pr590pV3Uj5w6S9L/JzCA4RLyrIp1vo2rv 12uFNGSWkHpJImMqVFWgjzl3OZ1CrggyzMwkcjT+oFSy7gTDuJdysfxwpeSBMlHO7SQ1pj4VlpRx wRVng09VcMKSTcF7uPbWOxMJu8/LhFSjkLODJtyWan+1ulvLZigyXT1FiJZTcBCWsngsWYOXZOO0 7E7mIotdkcYuiDYeC2rIqBHyYlfpepRxl39dsgQYXwQVFQAkRgbVUV/eSCawswYSBOBJVx92fS3T b2zxs5DvsqW5suCxnUHlXmpChenUIf7xzXbi1dqfYvqke2SG70NIhIIIWiHBu4UPeNOYUu7t9F9Z i0E+twrZ7XpGvfxZR3wFFWMfJ6c/IMC4hNbtXm/clfYSDx/B48YdID40pA6O3wYPH5pL/uvUDS+/ c1h9sMyo6Ndd/JQ4XkRO2hm3bUYbIOU7TsXL4l0+XTuQeBf0E/jnM//PBNiWjEjNEP+TvtfU/Ml/ Fjkvlvei6gzi2cnItl6UZLZ5mg04v5s7ujAfmqamm7J/yFTHNwd3Kvmt1xPKZuwe0c51uAYnIQ+2 6R9WTzV13tArP8XEmkH6VHhedbF59VYngLe6WWlFTZf87hUulepi5PtgDwfZm+K0gvNpspIXlUYc oSs+4f9sdnkqDwqeGDRaknkZaiiVfjemS7jIIchd36HWFYwaQylv4k1FEh3uOeRSZvxk3wvipLjd AP+VcAibjH/BP+rE01wLfJ+04lgPQiBgFOrdihKFciGMqRPqElmqHvg67ev6A/2VUm6bHw9Hio6T u1V093d2wzyy3nNVMdGHCwUlgiSKxjehCW7+Bn8lRlH6L0uXo7UCz7tio6Zflk6B4OU1EuFPz51F /eRDWl+3v4pfEZkzf86IZcaBDJqZ7Iru2fMLPQ61xY3AXhCG3fE12quGbi6257687OdwnQCpPQx8 vzOSvIrXIzycfb8qyO/izWC8glciyId0Uhz7bIovn7LQFvrUCuTruxXh/S0GvAv5Krc3tpFY2x59 teCXWT2bCQuBf5djsy4FByv2yK+7SyYR+69+XpUuVGTUHBUanqmLEQL6WvhXal7xpuzoR7VD6tB6 Ce85+5xizMGTKU0F/95jgomJjN5JYxDHn9PA6rBD4btXiOcGDLU/DP4wubHhQ+r5PUuLq6wq+Fn1 OdERtLTapl2ic9Fk8HEL8gCHRyD79a/MBKvckd89J1O9aHkAqhqnfxnvxG8+F6P+aS4K6BcWfLOl MMwEbwvZRwwaj8AqETqu9UN/lJXlrnAcyAM5UZd9JKe2fQ6ppT3v9KH1exwqktmwXS3j22xW0+73 8e+MNIqExNBZjE0q1ulnBKIzzi1iYE/MZoYIA8N+sXG2mOgzeFQGeJJDW7sjLZ0+PKxhU59g1Ve4 +CjKrWZGU+mVYB9CcUJnW9DOReyCNyGyEKkaIv6dhcpWduNQUSb0cV6Y8CLcfBynPmgubquZPeZn kk6rt33+No0o0Pceo6BOXJF9UmDneT0ftJRCkXES0P2RGP6oci2YqgdKxY+bb9HTEGixEpubnguv 1Q4G7TbfusW5mVGpeEl8/RVQMLL9mO9wpU9YmYJVUcKXRH9fQ2ynfmT1R/KZF/0UhG2HCZ9g549r ulaKW6s69IoXu/entjilizdjOo2wPx+vTgDCivO/auHZehPig0xTfPbhRNs2O67Mgf+Vn0bhu1VG sF251MxSCFxKoKVZQc+r1wkeOsNHfUD4cvOuVhtPhzXJnHaBJbFeJispPRwJQOD+22Si3YbzyJjZ xT0y8Wv/lX/NXDLmBh5mAcuy+/JC26JCjRO0iLLgk9o6SfR48GIZbJGifLvTs3QmnSpDV+7HAM+v vBwkZvbKSXWvkxQJRh/ghq1zBRwQfK98YNGaU9xnpb1hKp35xVcB6b691YZL3xPlZwsWJHu7JfXB sCr0WUZ4HOXAQ0DjX2PTFDxMve/9r6Nw7Xstx4EaoPdEm5gHeIW+C8RlVsHWXEMGopAGvk6SjI9G Qvp/fYp90wPj0oRFrb+zNDf7NG9kQZXOCIt2BqLv7irKPGo0V9Kurn4v2a/fqw9DGfWVmoNkr1/L HaGDijgPK4ul4QH2/mZF9wjN1UaapasQKMebkpGdlTPrEhjBYKUY7ubNP1Rs1fFCAFESSz8ObscR ezt2v+VmC+RXeHkNnzUxm0bTn3owg2nGmd9kJLyXQZDvn8uE7oRNDA2i/V9KPFdj69nQpR/SZUBI pzNDC/RW9Wfoy4pv52CGyk8ZoerDtTFnhz6PhdF00w7QumWUlj34d3/HpPKxTqc4xZcQBdknDAx+ gFvA3QItKSnuhO3Pd+dR5QjpwxOtCWNRpF6qtByq4g9/MYcgpuZBTuuGsydYW82Ii3Mr3rUepOJt qxsukqa5PoW4ooO+qn39I8cEzJYbK6Ju/wnfeyXOIOmyZQp7b+L3wHwYTRutBYKMhSz6g2uyB65e vBjEjK+znoNclv02VucKmNaY48pZ6tRAjqsk9o8ENTA/1VJOEJVZwq8nztGkt9cuUsE5pjWevPKG 7/lAa92DEXvjRIlUqGNE+YktexCAx4pE6e6AsWE5SwzVDRYpdWWCJu0R5k7RW8tvpL8cC/QIdmB/ ZprCLGZWff9QwIGSsLfb9bg/HG7isn8z4Y0IsbIEdefEunWkCi4KH9Ap7fLNT9EpGG31JJJ5oLVD UGHggmQqxKLq37NbSHxUaURTtPGHkaDh+RRvcDNlijbb369GE8lBymGoyTVIQ1kUJiVZ5AgKaidC 7DXrQ9c+7dUVpKpsQ7cCXJQ0ZU01e9ynzZaWf50a2bqD+oQyw3MomvWdaI2F97lK8CRkoUDUtj/t QcxGeXb7k9bXV2yz08Dr5k+6bzVGrIy0yjWI/GAGqTsAvi92A9EP//gMJlDyjYsi4m3mcYdAH+Jd 3xeLM42TSkrTB06VYH8t396BBHZ18u80mqdVMTanmMjiuJMUVeTAkZU3wvtfQmWth/lx655fkHA0 95w4yLJHDfYmiJM8JTJZLqwYO/hUL2ZTdz4A6WAhiVB9H/k81lJMJ0EtB/iWVJCwUy1rDBgwiVBs tGRxwTICm0rKRO7R/M1lOFPg5gKNMcy59vJqZTo7BK3gDItD3nWybqhNA9TZ0x1DxNJcwaD9eNEY OGFVcu8S3DhQ/dvNTdz584GtfjuHZttdudheLgI5tqKFB2G9Boyv90wXvz+crIyNDRoJeagM4J1I BNYda1zW9lxlqvtEYyf9Fs+45AkCyjjpSG6c+SG+1fpOEJi6keTeu99zdJ26fjtI73h+Rdup7iUQ Csf2PBEdx/i5PruLEsaOQIRxM/roQSJBpLAaOLeP/CfLY+wwuUJz/uGGauYFMWLItFN/jp9WKBgi snaVKQM3hWcdrJ39HvTbLGQOjh/oCWMSKSLRXAdjUQq1xImPPCKFfe5pBTw6sUvB0xVjFYWcACuU uwnw+bjxutai1yQtf+BrFIO9qgCxxOWqQUt7YKQV3EBdqV7HmgR5wkjCgvFEa52vnrJfRYriWU67 HdEhVQBHTs3IHXCx+QEGj9dH6p8NkgY1gU9hgsRBGRDNFnSkUYIE3DAFG9zRM9tTfotevRxF2nKa YpAboyZVzj+erxwtanwaQ4iiwxMoeHeDJwJIej8EqxyBHZxRKBoExf0DAhwkN6ke8yZEVuZ70+jn QNwcA4PW9UTHoOusU3fenUElw/WK5HvOneDwvpTIUlgMk44V/JH50Uw4myOzkzind/TfEJaTMYW3 impcxhQ1x4o2jWFrjvIhxhdai9PuNK+xJMtqb0fD7rxJ0ZHDUz723P52yXleEJna9NUFEblUdkF9 lldOj5qDtRJDU2bHGTT9oXvXF/ChqTuXl+K/CTuYLy+ud9GxEhv5bvLUSaP9NHQfOZ5qa4aqYhb7 XnNZZevcIqVi6Z6g0f2TU88ZFAjWqZGhXtg8BdYN2Z2dA6AjHFgjUXCBvoRrI627X1B6U//Gkogs Zw1LJUlo9PdyFApqkpDfJ54lTKkyUBxWmjufwJSczK+35gyF6iRcggsmWJGwlJ7X9ErI8SkK3UlV IWWyUbp9+j+dBrTKMmtG1lE9bq77yTwD0lUxyslx/sBCpHX5QL7DJJtZj8hu2ul+dWRCQ5xpmec+ 06WDRlSSWoQ+NTsldqP6QF5sojlMgW/X1zg1aInh3rMQ6jaBwRXZkxnsTqyeS2/oD6UPjY/Tb2V5 tGHltIUzpD77PeXBachjiSsIOe0SOtC1k/H7hl8eYajw1V3LIOWbVqoErXhftrgngLnYviiHPYeU 02G8GBqoh1Ae/xmMgH0qDOYBI88zr061vGU12RcF/V82xBHLmsPM74zsi+RH3da4NAehjOC8CJZR 9T2jV4TnkHO2L1kAw95dlKO6Us+GqTAhOFoSthC6DmK8K2ePQDVWywaBQgBb8nKPpYLx+7aed9C/ zHLHwelbAenH1KkjpvzK7aQ3XPCsvW5CjtqEFlWKBmZ7KvRydYMhz8JuX+5GqrzRClir6TEevA7o eg1OQMJGeXE2jw16JWJcpet6QZB2SyGXVCt63LC6zGH6BGYmcCKW8mx82yxtxtrRNGb0m1o1FW4K Ks9T1Kg7ZAk3u7uIjksaHAJeK13nmHz+NK5lfvT5JjmE3SquNt2TGaof1Evz5tLzKgztK8j8+JE3 cia5L1JVayj+Mwpc5MIWGGKjvMW/dzSVQ8RHY4fcMrKnAhdFM1wkIOXOJcqyD6cetoO8EOVrZkFW Wg4hUcSARr+R3WKCNRZrF3ncAQMWhJhPiqqymjtErtr2o7xtSaP/Wdko3lX9pcxVMa6ZwjV0WJVi /+yeu28lTPzkbtSpZuMc5JaIcZ3Wd5JiWjfsSIFaVgEbE3u9sRl2slzanuB6OVWQddNN3LauyqbU KLsKkv6eNTRxKN6n4je+tawF+i62rLK3PcztF8JVDZBdjDJdudIDloBvKCjNTtSrNQbmQLj6OL7m elmL011NOjf3NydnVKZbjYaGQvFm9KvwLQoT2UjPDsoFD4vV0aDIaNDSK0lEU/GIjfi++eCcAawS PTrV0tl6YPJ2oL29UKRnaaB0wpc9B+f+axF3Au/cwzxlqP42sxDLn0l7GfQqnJM1pErRVTcqOCoZ eId0Y7Dn6aE6cult96bIpreenYusQnRH5VVvaAHw+THRAd9+qaK/sd9F8vM6nEySMK40VESp/bF7 aHPgR545e/jXGrXONG1K8TvBu27VxWhY5cJUAfXWfEfKIQy4Um/z+EtTTudW7qNOmun94PiNA4ac A/Ts+FqJaW12eRL+fejxF9kFlby3B6CfSG5LMQzC9tfZja5qWm1uLkMqMzUbYiKvxk+9Hm1zNb+D yW4rlBUULvr66SRWX/1OQwuZs2gUo8PL/OAjoZSD0DzvXq3TB//5AbpAxM8kQ8Z9hl7MXiDtySx3 pJasOOvMeKZzu3SwLGGlYRwUiG4uyJxJ5H+kdpEvDrsUl2p9ZwhvfMDxKrTYrKoylXXp+n7neXMt bFRor/Pr1SnlVroHHa5dYzTlbzx0QgqXi9UxYqZEeadYe2gYM9tL5133N1m5jW3+7a/Yvd+Oad3h P2tHAHRTxVlY+7fCu1Wq7F2dnGIpwaHbrrIJPqPjz/V7ckyHGFA/C8otISzEhfyhuEfYb4g2/grb qvpjuXZCQiRJ2o2wGsl1WjtEe53AaYM4B5oihiRdV/y39WVu3283PNhq8dprlJwGwpGuuzCxyk33 of23fJybjqbSANdrIEtjQi0Z+yHGZhaHLzgrwp+Mq2E8wu4+28QOQ0+fMo+Puhrrnea1AoNKcne9 O0ZSVUKGuRRgDpqyT0KpatS+vGdll2b1WMHIluzI4oyDPkU1Wd0f16W51kgwyA6BfH6j3ru1vo74 2OXm8BfBvjEz0Os0QQdftzKbqtG1/0C5HhIhfcqcpyDh9/wr7Okd0t3LwQBS8iBO/sYG4zqt8V8y SWA4vISDpoD1u6sFiEHyteHkrafkzr3jJ93VUGm8XeBp3tIknllB1KClsolFXjKpWKhzuJXljfbr w2zBFp9LzpwNayEQfHgN1FJbaTm2FJjkvfnmr4hPAhitxizCPgJgH8/UXTADz6H6P2PDXL47jz4O oBua0UDQYjaSQL+2KMPCqSAOw4BRkIE+zdp+qEuzEBaSMwU2Y3mcf6SxEdqPW8kOS3mK8RtM0ASl E48AAAbCZOQVSxPm5erzZOfZ81YnKjGRgPzkGuhTAmgscF68pl2vsKqKN7vg50pkC0MZfqZp/F+c P/glne6OPfvi7LBwvvBMUMDCN/qHQyltYL5BDnB/uuUQ4/0DJlqzWMmQHGJ5C3uUSXyxIf/CWTtG p1BEEbRz0xFuSIWzb/n139nV/MFzIWzIun4n0Qxh+7tRYMhaHVhMe+d1V7QVlXqQ71/c50bPV94A r9tR4Mbl93Ko45CvnjA4BKr5blDzSLmPA36h6MRqvVftElCVXw85dvXNxYatv4hsmEt/0z89niIW MjgWI3EOGPRb/e8t+Uyo6snzFaJQ32ucPL2b6cQqFdnJquWLGwKHfGiNLNSAxuY99NslGfahxvWm w/NgUg0qeaJ1iKf4RHEU5D4Szb0dLYK5y9O1z45QsJ5FxRkvzcc+XQ+c26PuXBcaKC/J0Rqrsxj9 yjBOoiZRdvAqzTWt0BnR+zcC9ksmlIs+5QVIe/3hPCahygoW9XJY9a07tbDi7zbJuVPr7Da5k3wM 1K2ZZ0wmbUHiHeggXTDbPQZ+bAIsMKwLhmz6V2qRj6ra+KGPieyPcwR7/c3QOrQrI2UoESCtZWGP W+7fM3QwG6czef4T1EkKbR0WjJBO0ixreSYb/+3S5J0IkESWops4wOtJt6nJOSSFdyfrfRUGD1dc pQ6Zeg2k+1EDUicNNOQv/75mKbJ5OGetihKJoHuejU9cw75ZiQLtUEHEfRU0vrEHRg9a8TBwM6Gg hOtNqWkEl0D3cm2sc2oYVlweLUTDuJUVu30R1zMut/Lpm/X8s84nkyvMhys7YP/y73YROL71YIy3 qvdWW3OWRtk66iuJ575vFqyOWnzDc5StBwaaz0Nn7IwS5oTQZnxCuDF+oCFiX+qJ0SBfhdpcwvEW tvhZgnFIDPPexKrShe6lsGAQcc0voR1cni8P4dd8hKqhIXKDfwCipDxMCVVlTeDCAB9aW/auTjbK apX/+vx7Ny7dB21fmgOSoV/Syqu1b+5hMrgWZWXJ02ntoxWc1DJZ5QlYldQtvxYPxuQakEdgarFS bsF0sbHy/c26WSqz1+evVBq7JC8/0ECCtW5snXxKWZcKmZOpH+WkLRx426ZbMoy/AHJuNwyFLqtR LrvdA/g7qVwc05BFZ87a7DhZbZ/GHJuH8IBgyYWDbgpyAaqoayZJo/guTNDBpFq4C1doIhYYAdgw aRnZiHWVzHAUOX9OdJCkYBrRRWr34adv51mU7yFnF3VbA6Hk4jFLHxkDpIPjSwW+7cbm0+Itw+eg exn/e/Z9VirSgGWZqgFWmoev/X06rSft/ZE9Dr6e83/7OsuN9j2iv6+JjIyOAKXjtH3ZH8LtSpLa AZqxCjgLhW5QcMvwjciFigFm16FP6J/3am5dlQkKa1NefkwA4qxWWRJa5njSLp3Uum6SvfsLUaJL 0D01bf+qWdb6aN/sx1sLHL6Ui3Z+gxyGeZwLlfecJPoKITtdzXtZnXf7TbCP6v2Ufqui5O2z9Uq2 WqScpD3pyyaTlgQkptwWYQzjn6ZUjHG/JQqWkR06Rxojoh1zSWjboCKdyKRPIYYgMS+iAxFOjuh7 KikZQtYnQjNm+JHT51mB8S4XqRxZQqQlKRev6MUIJYkdR/2n8vXxLZICVyEoVCMZk1A8GXVL4U4K VLRObw0AsIiWVEVIG7GN6QpUtUiBGYKQ2YyJJ5Q9gEC5XLO1wrz7LiLTfRrwuoPCtEqwbfWxMqD6 iY0P8S2+WZaI+uNJYH7RcSpZB+urpzSrbT+/5a3rOaqS2tsBEMLJ1UUMsKgoAlbXM1h2N25cfEXe ufUPSnpoKLNIOcnvMvjmCZ+98gmfeXIxYxBkZd5CTNk9POZmmew9rTk/IITg9rUBuHxyAr3P1bbp iEzlhQNv7NYEJGf7nLNr/ixnSxMwCO6KV2IZHi+fcL6lVIr2pPMJpUaeBz8ohQMv4qj2HC5Nwz+q gK+5HM2vMtRA4/lYUiTWqw4e4zPUPnEVxDmHXqn718WKecoYsMJL0Y3fePMHZ4wpPvx2pmuSdlfx JnOfX8Bx80qtIRfomKq6JN5yiYf11H1fAJVtAHYu4hTcM0p5WVYhkptNOQWX5TwUFcRkAtVA6V5x rlGvL9bauB7iX6Hgw+1hTCuR+yV6fOHCAdoGDMn4OPNHR1c+aQ/ZTeKRLc3kl05wfuGgdHaAEwrR oDQG6DNtekOAHGIKUNPZ7xH3g72iYSNXjmlTwBdA/SXFwAkrhrveRTyWkCP1KhcxVlSodK1ujl5+ TqLFVUugBzLQWa+Z7AMASyU18BC8sGzFPjVTqULBn8gebKqfXyPWnmBInM5ci71SONPloeoszjLS pB00/oQH8WdYPmL1wU+ykMFpv80fIqB4lZfKcPQLpdTZ44SB3ZfOOAaatMZjGYDkDll5g8sZXpC7 2z4k2S00FxQAN7eTrPuLeC+Jp4CWIm12BCb8I8C2iPNa0ouBjAmRnn/GOAuWuoUbzJWOUoLHnhQT VdR10kAwEcpaZeER5flZfsiAxQsTPhIKOdJm/fkKLlJ4fTCaIpMxRJ8ONUeJkGZajErdbQXmWQsh e3aaUpXAEzyrBdJirVZFmEJpbb9mD/qQovHRXAAHl69JpgfqH3UB0zcWavqxXwu1EGMFIuOKbzPW uA38xeLG/HmRf2Vo/TKuaybfPXWkGaqaty0yGNPWcJ1GI5VPIIvjBOtTxwsO3h2ia7hL/IEHDLdx hso3Zx6wAKqIRhFZWr+mpl8pcPpZ5O4Saeye9JERoAODrQqKtW8qGSjDumpP8TTqLz8qUOuz93eR 4YPHQt5/28K99YPKYyQVdMNWotrxzQcAmKLKCWeglO3ZEl0SCa4FVBU3jkzV6DKhK8mOM80S96kC /oDQdJrDG/Fa0qOwP8gkVmiwLJmnDNnu1Jck/QTk4kqcbX7HhIdzh5NV/y9jaTckCgiDzbkJUFic UTVHHW5MsmP859gws0AD2mla58GF/gu8kolpXpIdyUlv9pntiH5UcTUrasopdHgfUrGzOIgyIw83 Mh3CdHgusvnFdHz5N+BuxzNHlX8nVq84xKouao/jlisqW38FopuiWneknj8RU2bBPQaNk+G7PACY SNikRmkIWTLBz8bYwaK4nafZ7rw4oSP52R4+f/Rxo5Xk7bIcNODhr3+lJROO0b9UIWW2MZCNjLNK D2pJnfy9bYJNCEyL4yvPd9XcX0sVzNb7Z7IQo+JNtXkW4Ww4KsUi3UxnjUtWtPtdyfXbk18KnnV6 s7csB07L0RvqbRNqOpTv4Xo0nvX3N4I4XOEF53lxdEGdppv8rowGtmGP4S4q5Q9UK2+rzD/nnAuS Qm+ciqpVFS4EPj/WZzWUGJM+DtwyUX0hd+vZu6VRLUWmaFry9xzKUN01WcYBv84dOBmUEC+IRDYr rS8D/ZUOGnAfkrlKZQtIPacQ0Q+yUoOzCTtDpqlGdGVQtlP1ET8yN1BdDsftW98Con+JGNUNG/DW IcOkT2h74VHAd15WtDk28qogca0e86MEMyeQ+pw3N2WUQbA7h68/gIDAyFuVtfE7wOTMtbyz/QAL jQHMEbYJG2ev8eUCiDpwNk4TmFPbzwpFz8GSTV+f2Q7FbUJl7Xrhq6JumCVGOl1sob7TaBiQPbPt 0duDsnpJ2jlP1yPsoOFkCcVMypmfBAAU9oHPMY52P7Q1BlqhlH65ubcZVFI3C94dDE4BJUjH0W0P mkVuDGWi31sQ9aFdFAf/AZnndQ7E5GHlJNlNTtAv704N6FFX+8c0+5KDNvJZVVfiDYyNDTC5vsST by7SfNpQcL7jIBIgZOZBt/3vNVhq2QyDtVf88TBwRmVyghjWXF90V5m7HBeIwZBdyY+SUEYo8Vah 28wpOysFmEf+O4/kotGHZ6szrev6E70SqcIqtOu40/qt7OttHW81ZC7/Iyo/L2Ne8HvV2Rnixg75 fvV6D0F7fNpTzaWPNdgUcYyBiex7PhDnviw7Da0CRn8v1BM0Tj/OStrjVS4ITShpta8FsZr3EGAO QHLnW2+O+/T0baRe5MOl4gWBVZip1d/+SW7069bebsVIBT3K2j93G7AKB5g4O20mWdQu1X4pTAqQ gkMmc7Desls9Si9BnSqfJevWp3WlD9HHnytqhavvQClgTMtQZaapztMZ+FbMHDGNyb5meVzor7pO 6iK+R4oOuMilt9uTngKbBGlpeWCcHofbLr7PV1nVh7+l6bpXjlAUF8qPN2MddJBdUiZ/tE316T1/ OBjx7+4tjVsWChFsIQRAhdPDzJ4QpCHHll1UPRB2/9G7KYpaNiGBoJJoplQkPbNdFkWSmmnlEv4K PcgC9SP+OhVJIczxmxWlcHud8d/TN4l8LnishMvBrn/rFkDbwRSn9fiqpWJUx2mYUsm8vcYHSnz9 wo42+7DKo4FnuiLW7HMAGzC81WM7vFn3aBj8PHZZm93iFD0X6MFIvFpDj0HwmauC/xXskaX5yK5R 9A8yiG5PhefatHm00BkEz6WlMeCFnUSNUe/AOTd+/AFUFUPlFNpQHMfXCnARuSdDTzyju2UClf+l mDKcG8G3W8lo91kF+2eaEqIn7G3aUZ7ovABCEeak3Rta8DRdH5xQE2ZAzDbIXXo1yv/BliEMoZaA hF/+0RrA4UZxAWYPDlnbRChescFVjj3/utYHk7bbAnE7NjI3vw1QF/iTS6L7RMVb28EVf1Ql62bG 7SEnWDa6v8lDHicmOc+owwrdjc//P6PFnmeINbsy15hLrNLTr6Tni3Gxtn19zJ5Ze/g3CN8dknS6 rLx051j190K1ilptryuTSGSsyZYlMuLxbHFfY6ugGQ0lGOOZK9oChsbi2vQovEwdq1Y4VwX18jsT 7IH5URxqNObH4HLLgWYw+E8WKOzJDCKwQMkC5sSQ6sDz9WLKcrCD7C/6wQJ+U87EOi4y0lQ4QJF+ PYZfKr/zrPNEY3DJN98mUMtBonwbdgAQqTBnErWRlAy8PGfqGcLs21NAbJt7AlZVMrynBs+B4s0H fNoWDfUJVjwzFeLxvKA0i3FO1FhyAp5b9eLI25FOwAhQ2EOzniwPwhMQau5DysLncBKROxqRwgTw 5d108OHbiL0RGspPKHsTaGp+hk6jW8N2iA1gEopQSSiv9pmzCV0uGSD8TQ3GpPLXx/a4ASOFcvi2 nsZ5KK01ZzxRTJoJkYuutu6k2OC/8gYmnUP+wwu+fHYC49LDj9dEh6HG+wBMm7A26a3LO8NSel18 e/egUSYy+PjAzp1b4wWsFWonRoH4DZ/E0ZtFZGArDpuf2kR0J8T3G6YjYV1T1HPC+1kkUUoPsVYg dMoqpHYyZJvGeIGkFLMNx5/lxSjivGMo3mkbApEyOBU3+18cGDtQAOi52aeTSZYmzxklco1DbJZ2 PDOPAXH54gOvfL/DDNx4OWumSSwejtwLMAw8bk73ZuSa+EgkpZIOP0jfLFQHyP3pCCTKroqIPMc2 EUGo/HZrIPGwyNpYZXRy4DWNa7zY89+04DVJET0S2/MqK1maeJtuECa+n/NhO6vZMAT9jls3T+6o 672hIBNDAn8STLCXBRUdiE+j58OG6BSyBXFkaHBzaxug5N3oYQopSqFVRctwz2J5S5JYvAr59mMH 4fiMKHQ+1RKRXClPhI0rUcPi/rY2Fkr7C56cfNXDBWTjOffagd6nGfTYu4foxPAw2391aAkuvFFH g5n6tHuDUzz2vin/43L+7rZx4n6zJrsnXmGBLD/papbI5RPJkS1CwF95L4HRLwruOaM7VhOhtyxJ SuMj82HVuZ7RmcVgLaaKznZ6R+JIrYRXYTI1Jp2f7bACSm7QGw6GrqLpLHk9XMmuqUy4LSw/u2oq 7N8wgTUUlt9AFIAQZFo0GxA17+4H8EAQb7dhbiyBVs9JuHv2eZRBnP3ZykE8e3I1rjpOPUvga9gl TwEHLrPTCa59rcztHc2LhKWontlcXh267Sky5XSJ4Z4gnwmyoAV5H8ttscGGOLiLIPzVf3ar8/C2 buLvMNvC97Bd3OgodeA4Y4EsFIa/wXVc7MfeIt97JdITjQhADwMfL5SF+ygFB5bAX5SneLENUSYS VuwUpdq2+dCtDAYDOntQ7ER3qpWM3BNj+uEDxc4J7YazXSW1O9kOMnbY1otRb9HPf6nHJm9asubL BuEbHm2+MfE8NUmZLrIu0DidIyMBXXD+j4irTEeP7ggpQ02ZKlPbwJw1yywU6uDXmrE48+jO0Whn O+vM4gUn1uOGArv5uuXHze9VYxRqc1TmgfD5YLiK1Q5ii9vmfKyXcvnhakEUGTX1gxL0WuHk6Fmp mAZbVz7ijkkq/Wo9WTfZp61DBAk18AhrgabS3BCHC/WKmTcY4f91spOgF2e9Rxuls18WfZavn6yq 3guX7aDdocVw8UD91mFc7OF1RH/TbIaXFugJtPsxdCgWgra24oZoGTz6R6sHsojmavCBcH4rWMsI OBMr3OOfPtMGg8uZ2KViXgeFpzG14AzQG4lEZu0dDFEN76IWwcuFaUDrAlu59LuaA+Xl7UlviV+O iwlneA7Ic21uOXBNUzLYMJ/VzZ+KrKsqAuFxsaIn/28tNMrUPBcKtvB9I3127/4iW53yjc1UKfc1 ULj5K2sgrIOZ6iLEjF2z4Vjevy0ROc1S0WXaSyeTRBaxzSeA2dwg1RJwleN+pAv3M/FGnD32ciDQ 51wXRxu54V2vRR/DpHQoS38XFcAptLPUvYUtLWZp/GgVVA7Vc3kfG/3LjOl1o19qYrKe/AhOaclu ogdv6j+kJHsT7Rd+YS2XwMzKVxVIAJXy+VS2FjPCCr+cRYQo7/iSI+/Al+pX1+G4eChnnMxBC+Qp JbXs7yHvCw2D2twYd4/7DA97P/JaM+R55IHb1jHm/MFPrfZW5seBiN2xRDV1TpjGxTFo2xMuMNlx L6VsXw+h3U6mLA4liZZJCCPIa1MmqjjrWbtM6e+EyWyDAcl60hBy+qOx+0jKGt9n6H6gVXhFgz2k WANlvU4osNTcKvtTVHO4naeEk0qOFucuBvBMBBICeQIrpfDzh7TPhR/zYtdqk/cO+4Eo4gKliwxT qo9czfCMD138ZZg1qzONcmIubbF6vni61eP2o0BZABRqdLVCWBMItP4D7UCxD6UZGRoB1hV/Px68 HmwVwnHadIl57XU3hxzqJbL8nFTOBXAJssME13hXmRT68mrdeX8XBSsw2AMZpJhZjD1yIacq0bdz peHwBImUm3C1mYszi43nrNA9dSuieWqOx4MToT8zZEqqQ+3RhE8yN2qz+LG9j9gf4Yi32erDU2ai p5nqDxtb3o7q7nf/Cd8qTTolNkSBRWzb0jRaHqCBStQFPPBPfRclbvF8spAYLcHxoQumLkToHvpP C5+Gz7M1y3az+g0/BQ9b5Gh26vIFvmE+/RpVIJqZeAKT8zYPpjKhumrVDopHNvYrX45BZgK/TE19 EnK/9Gdhjl/xlRsuljKdDUfgzp9XqTCK/v5Oalia7AD7iRmZYxyr9VEzmqwIyHDyRrFKucTz8UON wRUoDss5FTJxMxgNtuOtPcOGFIAbfNTqLlKcFV6zpE//ns+MtpryfTF4dv7KyCAsSXMf0LdmPLnZ 2dG6hWceCRT031LTaqGnTVmMYqMoN3rsOD+hlgs5HREyiEuv+067J6cC5JPi0e9stNEhrJVezAIZ 932SPzdB+XHv4axW0YKNmgNj8TDg3zZ+Af9HT707ngdn61W+AYC8S7Zd7m9iIGAiTVw3+fV5PPpA tEb2E+UTr2+wBHEZejYplq7QvIanGlaiEyozKxlmpxnGP/8O7othb/31bWMaihbdMiCd+bw6qczl XjH+ij7RZzIciYyTm7rLrseDchKQOcPv5VKWUqX3s/O48qJGwy+Xt5ntm3fwtZEyXhBLJzD6LG+c EW7VYGquPIUWKu/9dkzp+dlI9704QRYi0oBuffVxFLuywPXyOQrnAN3gSssp1Q/rnaIlUBw5uJYY Id+J64DQ8vNX9nGpkbjQeX7V39krLIsOK8b6YebZBWy5ZJUe1QC+Zj1kiV9q5u5S9ubAaMy+LM/m Acz0BPxojdK6+u6bXA1ClAjwyNHjayNY5aksPa7Czu+DUZZZ16YfxN3a+Dx8QOhf/4m8k+4HHoHO 5Z9N2bUQZv0jZB4c12TqW0pxL/RLJPumlj7KeCuNUTOhPapcw/nSr88XtFmduwXx5ITIh2BA+dTp W7dBLbXKj75/XwcWevLoiVk1FQwZAI6xj0jENIGVqWs/MzVuTkMClGtzcDAaPaUwIg01PI1LLHPE BgPVojHQKNdsMsfYkw5Oniqx6wcteG77KqmRDnFHhFeCXQfqYmEwT04GS7oudc161DTanNOm4ad4 lGPOv7moQhRavRzDoBv9oLWcJbJYTKSqxhOerbGp2LiaRTrsmYLfFSmjfkiFhMLbMYXYygGFo4zB cyCyk7QQkFhHxCocLiBzR7YHZJXYt0atGvvnHfio12nqLyL9fGH4C93HS+Xb65p8SEZLUvmHv1gL FiLQduk7AQnECcFNMUhKbwtED225Q58qvE5Y7ao/wf2fJDD0FVMcsXnCFH1099BQA8hXM4NlviT3 Ye1ZIqQTIQrSOCwHx/+bP2Ln/71wbTqsN7APjo0Kl4NlB5abIhv1pA8pI40Nw2rc3KlCHCpCaoEe lT//nUEfCqKlmMHH0OQ8arA74x7jighvLIR6XwDnwigV7AB2jWU21Thp2MHbiJFUTjyKTiU0hnXW NksYO7EepFXKfpNu3kUSE+TQX5RzDbCOmkRqo2AyUWMink71cLYrwMv0Y6WEWGio6mDOgmZCfGcH xL32/hJOqu8Wom7yFwNZPiSzUFDKfaiHLtcIMkKOxhBHWhXbHezoYQ7ELbxjNcjI15yAqJYWf4SH GWioLT3sLEH+dAeWsmdI0d90wDWv9PnGY354dxFzgDpDX33vtYP2dXdtfKIOMeiFnKg96s6miO4U oZulqZ7eZ40qKkQ9AnxGwwm4YfY1qZAqclPGWow3FxerRpFxcanjCbDY5rA/Ls4NCaEw2eCmGC3s JMtQiBcBVVzTbadEafJv0ZN9uMevtXgSpOJFM1qymTTPfIDXpCmdGjEtUTVtOHu/8/4pNIvWUdOb 76rOByfF/N82sYMltaCpCd0IMSjloPIb3jwjYwtlYaYEzEu0Xoap0cLf3Q195+0a0+FQeKGcw8ER L2/AqUsdRDlX+pDe3EaYguQGOWgYorJPzfooy3IORmxBeR+dN9lrOt+fUzJg0ic3ev+qh/ICPZ8x qcWcrnKSaZU/oYHJRlSj3uQDOn9Oz2IWWk1yqD49/XfNgAHcyPSoxhVVJ3eXnuD+tdcQPzal/5ab Gd0HnHXM6yI6dI3ZkGjdtn1WPs/DQAznVbzEiCRPR9iHOKrK1Rur2AD75gERRW7PZ0z6g4hNRL9q 26wK+UPEBVOgwxaVddZC3cncq8uHNhpdhcn71Tl7OHoT6dK8zFh3dKXd0uqNOaOSGp9hMHFYPBvQ 7AcJXC5zVRMuuHv4KxLev9ViG78DHsHP2HLxKIcJrcMmAVH98IxhBT0R0ccvK9mRtrmU+dzcU2UN VhN9WZ5tLxsTsVMNcMeMGpu+0Q3DsiViR6kaVjC7HX5fNWdOn1k99CX6NMSLDStrct7+QEYBSesi q50XNC3CUDD2zfTWgRcWPywS5uN27Wr2cRxIqGmLLgH7N71t+qDSDRE006hKOp4hWXZvtzmHUC+v MuFtO7FGHMpMHCRrLAmJaliWUSGGVhnr/xsR8spSQ/+5QcFsjewX6HdbcVRaJCubgbTwN4FoKBYO lnpXv7RrQlzhyXdDznBajDzdVl/cAWjaUYHTKJyex+MrqW7O40Jyy2ToxLzph8h9Eo7Ngnf2yZMD eh3NpVCYckh4UpOOpqwU9iSpCJbbqr8E4iadc2MppMtG1t8OlsSsx7BZc/1fv+tsZEY9cktbvxWf o2o6VQou6orrFK4C15r4YelyZAEgQ9OQfHLy4dsATBHaHRHV/44BJ5GGTEsLdure3aKffFgeawl1 /t6WRYMoLdSRrrh0GfmKOaQUE2D5uoPLncwbSzIIJZYnjSksiWyhQDnBE1SSu4JDHhOeNB69m9yZ ywESWsb4F7lugrdQAUd4BzsiF1n12dbDlx+fZ00F819iT6aKRf4JwJiH1wftMFNJrmHjHz1VbTsx dve+0LRYxbfwbVWo1usUmXwd4l9RSRto9K5Qqo/SfBjk34cNNc1t1WpuRrqZ7tW48L4N3WzOFGkI lvsIroyLwyz2y/46kKDO0cLuTodLTpjOVMzxRTR99ypVLpCVc0xieqPToYJI8Ld+i/A65xGGjiX0 8W3lvg28QRxFbNQtzZtRYQriAtO/QBUAYOdkkp+kq5F9c/EcP71zQUG2BOskdMosr7hL0D/Umr2I 9N1sr1bn+/XvfvkMkslVvthEPPgsx4Sgrb5lcH5wWOxJgbYAnlQR3w/eTdnbBls5F/CW35EcCGqW vSQ6LvFPe4hlIs/rfV1LlDQ4+NrOd+nQZ2uTwK3uCM0/OODnHJlWFTgH2Ft/JsQFpUCCS6mQTgvt rcLE+zDEoGeeFLZzesD5VoPZS85YK/OjiKvtj66Uh1h/aVGanLu2mRMEPN6R/9v53oGJ2gcY7HY4 sMbvFz4ZGmB4YLAZ0hod5u29jtBOCXOzMGoYxsP2LQVgfaec+ZmeWlYBmUPFGHmr6rGG+x3kShYz tlih7BJJ7OEy0fpUnhLxxgzO3N7ez4KcIMw1SZ9fTt851uauVIFBMbePraBCF2TYd1aibGqnQZos lTITOsBlD6oyVUDPFeQ17qD2u13+GEXY2dpfhXGsQOayyp9mfz/CHKU8F07W08RXGC+OXoQB2Xh9 HThF3eVtTgzrY+82QvlHLFv/19UCVCMA8M2zSh6VrICXfhpUIhDoL5+0IlxGD8jXRgJ7XA4lNDS1 ofXMHsRuio2QTd3wrbS27K0P3aLptn1dKyBLSWOGH9Liklfv7cystXBKQusOUAIuWeSP13QjHcfU oFvPLgoWfWpKkaFO8eYn4atEd3WYD5h+RSL2POYK2GnGMMXxG6WnqwAR+botVcw+jYyxtik6/d9t AJLjM+jpS5xYovVJJM8QZSrkeP5N1rOkIMiuo7fBbGZ5J7bBfmZr/spNTYFCDIZWOpl6D9BLSg8b s7mwL2ytSPX2N4q4gifSfUuVC99tvd7kFEMZY7ammgD2iSyszp/NneFKewE/npw4dzEi+U2J0KJY 7Bpm9bEMiFZSM7GtmHpUPEuF0eV7blU0QL9EB3HWSxFFE+zotfpdaD2EEBU/lXBYCv71bIyLPfuj pd6kqd67vd6WtWxWahMp/ZroOjnHDDv+vfVa66FUZ3RTUw8bbMX7aBtdsqhIT6RUzJ6+yv3KnLb4 afupsXHwVedUnUB+fL7F9Kv6yPKTVUvKG88bIW1iW6/NQO00aaHwmM7km9YGMGcvBWVa3NjK5plA zs4ihY+8RlkkWgM2Wop8oajAO42IeS1MMU3SRiiDARgKs2AMiks/wpUg/g7MwMEqfJYRBnYB81ft FueHxWjzbi3euEdwZh3aSP6PkQbk5fyLYmimszk6lpc+4+3MW8aO/iZXI2zPhUNnkZFa87mFfbep L1DJQbBhHYpSwqDE3/r2qmh1tCOW4nOEAupALK8bgefDgk5zc+ekzlJb359x9eKC3aqU3AFJtRNq gR4INnUE3Lejv1uvyY2jNg2ro1a60ZugkQ7L5TKMCBNHRq1ddD2ltnVMQDrlR9DZkH1sfzQ8Cnie 2gnqyENhaBca9osJDn7Rex/q8rknW7Ys7NsGE/wpWwJpjf/ZJhGj0+2AtVsElZmzph0cVbYSvhCi 9FP1LVwjFrZHCT4XBl1Yq5Z+Q+5hw3fWhCMciF1v+KCNdMuD0dY11BojfEoHeHyVzLGD42B34UPS 68yneUn1nc3DdxBGu89kFMFdX5WUyhkqTeYVTBzkFZ7Bxf9s+kpRhuHT2oCtEAQQY3Ok/2SmIHfY poouVxv4FtQQbCH7wOvB9BvX6adHtOmD1V9chmHTOM8lKFmbGPq02HIrMF0mp6Aj/3HAm/coNnb3 rF0yxQDfyRlz8YRA0n/81REA9qq6WtqfvDPs2K4PvQvH+5w/V4wIqPkbZfCZe8716tGYUQ3h55ul DSCsqL7Z1fMrsu96H3b2ssB6MV47Vlv0eJW5Ebj0K37gEPFuosffI61+iK4AQTV2oeb68iBliVB6 +j1nsJ+jr2aXRs8/ZTsBw5+6WaDH4K4ygCad/gRNtgXeMVARgisyXmBMlXP7sFbRgeyTIPYzFbmD e07q/x7g0xNtVZXc5T7DcSclLLuST1RaEoYBKLcKidxM56sitaGgbQRcWihpXxo2Dz1TCZsIK7AS I/qubY3hStAhepkFf/sGvtXQ3pLFeqJOSs4Jrx5YioOcLJdhQdojPI/UTzJv9fO9/bL1ndNRueY4 9VLhzwcitCvHphzE9WD9zX2iH6FnHuhLKfskwq4HVUXKpgsQRpGbX4k8GZb2zGGHW/cWwZfcynXH I6gsoowFQPjMOOpPEyZyMiWobj3vqKLTG/krltkPedjIKx5xwpG9Enbv/3iajNGGhYsGUwv/766W 8YuwkbT7R6s9GD5EQhnoJPtxaCQu4H1/SeUsmPJJGPrM/pTZ7nHLYBzBw0I6kYTIWJAnKn6A1mzi k7jK0Pr2Dgor1+RJow6Ekzoawp1D85EM0ua6kZdGw/nnIMGdRMHPxPwmfGkl7dT9Zb+sz9fF4ojV g1tp7S2FS848IlA7WBRk7f0Qwzbw1hwHnYOIUnaKCDXzrL/koNgvL9s2UjGtzTraGJ9dCqQKxC9X qrNIerBuby6uzBd9pSkXQ088dvdnIhzVDYyKx4cu4sEID6yN346JYz9xRSZS5ZdCJzvl7GRkwNA3 khGn7KfL+6TLJ9jzOpBsAF2VJ0BMnir23X5pJcIs47YNoTJhqPNRLX4+viTbLSNvtS6FQEmPMhA+ Hxx0WSnJptHGn8TfKPEjQrAR9IxRTM5sk3VpVC2yh0SrQbir/b5nNRcbwfjDHwWG02XGsOD2bsvZ zeAhksaGMk6hfaDhwKdkeLl7/9kCFxmnH0ru23nqrth0NiIysMQy+GZ7YmwFJdVsfb2ObeGQ6bBg Jwn3gMXPZRlwm+gd10VEmiyHyUk+2XsV9Z37bjnNCaberg9RqvjsD7YV/VA9qJxRjy1z05/fPWPq /MgofdmUEvhAxiryN0WbOh1rEZJzi41yX7K2DIM+Oh1oxXnUV5dSbyzxbeaPdkAUq6+0K3P3PTKA YIUpAPkNCKhuy0iPjPUvnxYos4i/f++2Z5hGfqlS0BsxAxcxriXy4IqMrjFeQ34BEiqTYX8z+t28 /xR44yUWOFA0icmKMNVUwsot8VTNc2y2ZQbvOGc4qYuV4bZDLrshOO0Y4lQdjrR67aI364MdsLMN 1PH16vvYySymOKqnya4oXMPEtyLgNJmhwsoXV09JGoHlFBcDaAxhFV79pPOKn3jo4ljDUzU6PccK f1JDHsf2D+7AeuVIxT/XlhAAXM0aO8kTB7VeQaFeMpCDu9DaustPARgS7hA+BYPeZtIBlfWCres2 T4oIuKzhL6AsyfL8y0KtH2BIsvZqobQC4v3fMhk0CBdcKLjtOidXLh6WIdFwbDgLgpks/eVz8WZU tzyXr1jDwdZGTYphajRhrgF55Qz235NMEJDhyGaXaIjF1gF3oyQXPIsGnhKrMAEM6xrInpPxUb04 0+mqg26Jcl4wt1Nw3L1fm100c0h+u724vFnXJZXRHfNt9xpPHxa1B2oOTEcawdBYvrY23092J1xe oFjjdeUdNNkYTQYIo0UegJ1biyu5/GsRdMROtDH93I7Fam4CIkjGJn5FPDmTAecvkBqVoG1pRIIM Iltf2Vg0yYsKkWjxAfaiBpuM/bFl73o1Agzu8UxPR6XnxeDR4lxHvTPfRIRoOgAyI/mSp5Uwxg1O R0CZDx4BugpbWuyCkN+JARMNAFiMlNomiKHQXGrbX3tYKAHDLw96lBikUaFZ8SAu3R9Hu9uynIJs k4DffBxj1zfRkIYw80Yv2No9V9ET2xP/tuG/ublGYReEeyxUMEAXm1PcE6c6sHcnPSUc61IA35uO XjBzOP7t5oEt7LWyROFk99N3WMoJYhPGXqrfvTxS+Rw+NxBhmfPTCi2uFUyCkl6yy7iU+63QbNE+ vZnrvqICxgOf0tvL1O3/efLxnkyQBitOh30mN2fXXEYI+qajakTLpT135FtOQhHfNnUdMrLNG0dN OYcRLzUc+SzM0Qwx5ONgRs3YyIH0zteReZI4fUjh9SpbHMIz1mhGGG1708JszKE3V2AeNelvRLZf vgPbS+EYNL4se5jMiH+0cJSCuo9uJX1I4T9t5U5R6lJbQelSLYulrFQrNkhiOZPMe7YxTp15D6tc YYUFxmrWc6/5XHoiZhKbwZ+Ut7CkiKuS6HvGWVnQLJKiT1jqDBl8CgNnAg2ez35v/resYwyLZhhA 8vvIqu3ySgLluLdtruIwfqNWZwIlxLey8RfckgYcrcOd7uDHporNdhfyDD0YEUffP3lLHj/3Yxy1 +5UKd825IkezVM6IEhQRxcCbhA8aydxFsOATkB4rzELPHXaqF2939YT8IMDcDcIsgHzC0M8rtMxg W/ixXIALVQ1brS8dJa6YyEARgbbtgJRZXOKy7yKPrGI3MkI8yZorjncb/GMvCyEjQRVuph+kie6v Twrfdj76xg2g/C4UJmM2a9NXNFlZtL4H9fNrKxdGPRz2HSyrATvtRJL0iZJNoz02YQigTHuQEQoj ClAGo2ahnCjZnP/5t3aW2l9V2QMrjLvybvw3SKaPwmFZtVOB7CZHPjgbcLWVLhu+UOEUtoJHd52C 8iJ14NMtk2MtJtq+58Sxi9WXCJesfr1eZ75RWHRpanMDn9DW4OtzKHJNv5fpqwhivOFrrVHwiv8u RLsNoHPzlOXZ27ptpqvuz8u8sTNOxY24ZF7fk73yA0CE4TLq63lEugepfZ75ORVq2Op7K6jAVqQm w3n+hQsXVPgsWJv0fut71qXQmxkSQTv8qreuQda9yFx6gFALM1107PUqFKpEypDY1bsFCbC/GXUK Qeo6tQc9gAYCyqqlsrkbHKTAcqtvfiXi+3A4nkcNYMlRcVP8gLOF0WA2dE2p+x2tPKXtbqN29qb1 QlRE/S0w9AoGI7sj8DfSVaR+W+evT0hSp+KlgfbH+c4b5qC+Y2upGHlp7QUQ0JObp8/H06VmYh8w jesSIYHjj8ePydtVSWprtrgC2DAID5ZHZ+x6HY+kNYr7ZCrqjcImcDb9YFYVzFt40ZfTZ+Z3lwMP jceh6c4041W4bCnR4lqPkVR/K5d7osCXHHeUhTFYwmFH0HtSJHZAIk2a8xqPqTe4o8xvSqMStP60 7EYZNvZlTPN+gZvbxFe3MlFNI/N9JP427qzXCw6JkrbDPTqYW8GnFJaB1P/SrNkAoEbx/U1742Fg pYhWVZr6U5REhwtzpuX7CVJloYKJ/zTNwvNu6PZZb0uMn0vD+iI7VmcUqmxRVnbiKxrRFTS7Q28a cgV9nqNOU21zMTL2T6TC2mVq+XYHUaih2TDWmXTUjLPLLidxGEt/vpQDal8sxFsvAvcm6Ln/jcO2 yIXn8fvnXvn15W/N5XEXets3dhbjkA+bEGCb+i5/lufU2RLPAFpfe9Jnw2teWEuqHW2t8K4UErGT TXv/hIdVF0W7fr1h8THdBpYKjylYj+5pMKtRqCO4NX7CJDe4+gxgAw7xaqNYfdYFLh0nUo9Db2rW fIF6P8NmQpdziHEmD+Og8yNmHqbH5EsXGvnXZvNzbhZa0HxffFD6uMmhmZc69FZIc5dqc3LBx/R9 BTiP0X9f8H5bb16D4xuaSWnoSJnVMSkR/c1TF29xOSKqVc/zMDrzWbek37w5yqaKR47uSqECon2o yHciZM2/L9IYtVBPk3Ws+fRXKFdNBecavHzDl7Q9h1j4rfmpyNIG8Fa+qxT8LZZZIc63J0w7tLzN oSQK76ft9+sdwK5ShJVptgzkhOuOrBEW+t+xf/UW3AZKDmLxZOam2+FCI7sPzmYuxLKkqnlTbsQY od6jbhsQuFqKYopvA8Nv2e1lNFTmgZXhdkKtLo06fwq36AGaoFa3b3aodhIWFEQK1eY0JtLopZRP ztbT83h7DKmVAmvwz4XlA67+4CVLE2W0fuiN62/oKa2eS+R947Kt8u2IkzJ8bbvcxmUi07nSekXn 0xh8TYbTirdOV5qw8LDLd+FK0EbZYLCX3YbU6WwlB4yaiLABipzTqZMgik7bFL/H60yTLDk7c5eG X79233DT+jrO50K3uF9Pk+s30z+aWc5x+AgI6UZfSYJRIrllYEtcvf+UouGf76Aof5UsXoM9KjJ0 vWCD7MbifGSv4DGEqc0GotAgTeDZQ+ZFEVPLzPGagrbs27ejbn95spPBG79BL77ebVVkpzFWNgER QvS7QfFpTSX1SK/hYmwVwyDiEux9Awt1Aq+dWRR9az8tr51vMhu6faZOQnyhNTl8r4YhSz4wSifE mFDUjLzO7DKKozFrO74s1ruduk+D3m90pWlECxl6AV6OBV1MYzV3Rc6m9wB6+N2PZtQrZ6vQgwWw aKrU3lQDkYUpkp8bTe0jlf/DZuwQTNmAtEZ5Vyz7FX76QwBu+jBhiMFfUAacdYIrygBT7lKWPAz0 UZH2uO5vFlBfXfP3CDjd6EYw84HwPUWqqJjeFdf5DQKzV78I8ipHtMsEZ+NNO1KtPOtVjwFHB6go NYheTqOLKx4QY8yP9XKgTXMyoUB8PcX7CRx0A5yo5B0YFMKfn+SjSnvuVptzIAwcTpkgMQmeSP0v XJ6fxloYnNfxwRR2N64MVqJXl35W4wn3HesgDAi2eNOTgzu4fuUj3UijovO4cGCean3QwH9THXZJ ZT+ilacqUeU/cRuO+Rw3BgDOCRXY5FdYoLhkeSKF6DIwYIRVg4Uv/9WPtFt+Hfypp1zQB3turAl7 lmaa+MlchJUESnyjVX1A9jIuaxktoqfVYeuFOwanW+By8VNqrl3Cir4ZWPRPfzcS4ySv9zo62Nf+ 6NNmKpUXL+gmUqPWS2Iqnr4CGuPNDjHCYxhzTAaXKC+C8BEEI8LTyi9xYBVC5xMuzKyeA1/6LNYU orofJuA3IfkTdzDZoK6L0IyUCLrUzKpVJ/Kf+tK1RMvcLWJU16blp3AjnOflwd8qfkWpg7B+zRur E56b6Ua5MxHyCqwDvnq+6MQaDp8dQnescGXcTepQoteCE0b0wDN5ptxe34LFJbdRUuE71b80w3kr C1kRxFCgwq3MfZI9XTd+mqHlknZfch/rdnOsz1cjLy9A1Ow8N1vS7pkRtcmH1QDZnTyTs8Ip1UTd qWxdfT3brcSJdiSXonSsG3sX/3tVCxCxwceOesktK1kWCR5MyRb7hKsi8TjKPAYT1wkfRpB/lC5Y u4iFsFhW6aTOaZROrTEGF7ZTT2SV+52rHcNE4yFJaLPTmye+SfANE4akz3nCBWLvzL/YirgH//MG atqPEwL6TXJRTM/ZFfd+ceV2xIjvWFinrStHaVp/Wt2/bWq+PFvGAgRgCO9gg0tqdd1jlQnCgC4z 64sE9g5NqbERyt9Xe4TXV1VxtsuBDW6rjl94I6zUp7O+J3j1qhPf68PQjWCMUdpN9LKocLCdNWjD FFQyBnSZvNRHb3PtglZNj8ofRejjGXhcKQdFDj66OQ3nolhAG6sTeJ3Urbh0QpbNdBWsToq1+nX1 oXbgBSAUzBeADo1R1mk9QsmCilll7z0c15qK3rl8ekL9aq4rHITPam1jCQvem69vMvPDrcWjZbE8 FDJYX/8VknavhJkYGZ9BqY/a610CFF6fwvMr+VHyyqQQwGFhXatqffskGQcXq5g+slrd5fqeIGpW ZPOhd0CAmXm7GELZIzb3GP/R41cIf5UFNNj9MmySsorHtalCFQNjwqsI27ciE8QzBR8YgrJ9LRjm 7SJZ0socn+397+XiS8EHWvYJz/9iVdDueiGzuRlfv19tUC904NViWxQSM+964ah7YHFF4PbcTf8g ZhVZTj4XEm9vTK6+ZlBxj6AXhXdkPQFyoP4K2Cb/zGl1t2Rh2JUJ+eMEn8TlDPtsEQ/rfARDBd5B P5j/LbD4nstpu5HWE1d+c+EL7MQnsNuJP4PaaTrDQ4TcXZZuSYepH1OCpAG8Jfx/XFvKingFyzPg /vr0qG1grU2+qiAfHlBLfr9q/ob2eHCFXBe5QNsLxxGnAhHnCBl/albsenNhTArehBVdxPpLoQTn 6ZOt895HRD9FOG7x4U9ip/DaocPpdT5RyY6dlvjyY0Owv3hX3dsEOf9IWX8UJjI5yL7+8e2dswAn biszEB7yewLJXISF4RThIyXGQhpdXhTT9GvwPOTTVGaupQoqQEmphPvzwxKilaQV24QJV9lyP30p Ueh97k48gDNjikI6CppzLYTSoCaf+TVAzycrGjFjJI6tzca+MhN1LcMh2WtQNrPdCw/7Rs49SwVi J9XTkLafT82M3vnQJh0+FJeo/41Eozzgq2Mzu7vOeneIpfDK3/nbrIuORiGwuEOZChnsNZ+85rH5 APDskx/0+lDEHZabIyfxrpqqq40gbOeh9oqDwdZul6yI5DRNh1i/AegdrAYQs/YrIBK9pEwctTwP Y2tbppx901i8vEy9klwmnt03vZBO/pa3/YnJhM5/onSlAYMkxCWXl5I0SLjW99Xe7ZgO+elzRfVB w674WQ/LFScdhgCpoDRUqSCL062RrbHGPx33VMR5g+rUXGqvkQLIyHTHSb1Gu+AvDnjZfgtISCiU fq4wHn3fVLIhPYxrCjs9gcLuJrb6aMvAYyatMPj9MeqmjPopAf1+E3O4i0YUG9C3xW025s98mZ0N r/SGNRcG75B396kvGHVsnrsZdWHLhAYpdDS9k0OuugO42jwcHDXYW5VcaYJd3HYxffzSs6PR6ihV x5wsCwjkiPHhSJTSZzFIo8MuC9YnswnQw36ENAHjvZplzO1pzD76szQFimWyL4+RIS8PMlauulBX 58AB0T9kCBPl37kPv44xOPv1TuyDUi0r00Ew/onBEDv9XUeLLYpnCK0lm50Ds49geiNyELTnY8Vn c6gY1Yn0tDoJNNLYhvK1SYJ3aXCUsYCrx6Hl05Acu+N06H1NstickuNCr/hcZIoXU6XC/iC8UwyY RC3VAGKKDuFQD43IrZG2TQ7O4T4Up9LBEJPLk6dDvai6BEI6UMHpYggYpi+XkludjcPYFU7GtNyi EzW+DQHq4P0+oxkG41MVMVChqLBpnolC+2RXwmUwJCgAvpi4xfSIa8650xfN9LbggSVcldCTfomu rspRxrdvSnWFJqQG+nl/lZiY0GOnlXO01YC5+DtrDYlwtqihLncBz2Yem0Lwp/J+QivFws/nsuex BNGKr22ZlN1RZZk4l6vDJQxppz2gybRiPh/3JfTlPwgG0LCDKsUcZk0B7XrtgvuU3Kw74tgLKHpy CWHhUIzqx+zrcuKLo+OBTVpX2UAIMqSgbLJrGoTjsbh+8u4b2X0VFkMxJf4WIMiIGe82kScWeywz e7zbbdWjPQWWDGlxVQPO7UA/kVwXVeb1oG4aYvzhAcx7vppNJUHuKPFRu4FHsYLKy287fqtFLb8c 039JEPrBMojfFTopQgqXUgmA5cqsJO9bX9VODicjnUMtziNdRolaiBrKpA+644KIS8OW1EP7maUT e7Whyn5tKkjcI/uYmaNh/cYOSLUNAkfyRX2YBQVBPiV/voaZdjuJxvnu8bf4wm27cM0IX07++hit gdr7lKNpY0TpVDnIbhaWMaKeoH/TLZEZCx3iJ8Du8XSMI+kgE22+k9bmcnR1/lOVbVUZ4FBPFwri wqIZA+GiERbCq8QvN61Nn5ux1UYRXfR1t+HOr+wmUVT4cDESsIC+9vDoHG/bYl1gXs13AHiSVeFs ikGgnHmttxncxY75R1cJ7lwttg46LCAU+phLs03bd4LwhVAIOiPrdYbEPywKLOxRhM9Wr57+s5dQ 4aaWL0WS9W7v5l52npfPosLyAeDBEpVGYzR0WGOzcFcOOA4odCQGtAL8owUh/uRnxiYiDnNChtel sa68mXkiu8OE9dPdx8Izmrp5pdr2DoV1q73T2qS4qjkSAA1zE9yoaN49lKCoxoREcjPXgy2vjlBP cLxt2ogQTXlbYDgx8Qn/iUDwAtu1sEYFGIGxMnC3fqr3LoVgDifD5V6QWoqB6J9vnMegyGthJ6cL 1y/ryMEzQkhgBwD4bw8fri3b8tZ1wpNoRk9ytdX6XkNURSX3Ix8b3tABWVBNr2aosvH6EnJVxj+q qkzG4ewrXv8L0bIaRV2wpZEdONU1swKqL8tpyK/0yRlPOAVydRIeKwO6zOfeQ8s/TFEeRxJgi5Nf RSQJyjnqHEafskvjFc6424pGATGqlGyht3N1WBZ53z8+K/8noEpTNkbVcIZ2v9FZxTl66e2OK/qf vkb+0piLoHOLOLGKPxK/chJ1KXgQ2TiXJgXRcYwsR1VNYhNocsSz9G+0rSpI8iHWCJNJ7wTEhMoE kr+LTmUgdSS7v5YnMC/zVGHQkD6vsYc1tmt3rH8nkD1Mr9b63cQLCKdNC0peJPu5IdzCGN8xt1pR oqFhSOfBSe4nPwMTkjxKFZ75yfO3dJI6XXM+PIEE1lMw4KIIbijRbDj/Y/l1ZXBrXiz5uL6TBeYl whEuuHOuSq8Pi/5muZA00AXEE/x9XbhYjKNin2rhnSCJyMLtfe/Yq8q8Tad4u1Cr+QiL+HgXTo3X HAlAhKBqDCB4/Miw3061jMjeutNyckZOt37QlaITJVXpL/q77SpvVRz9+qKy+yhCbwS2QZmAlykq q75d2GZPGY/7J3tch1rw6rCLajoIalwym/7OpMl7Q1TGD69T/zs/OqRiu+H+pEgU95EjQXvSzcRb nWGglzY2X8X3lZWLpkoM5nIBlFxh8QoLhuWa8wfYmGO9/eVgXLL3KUU+Dxk0SCmHLu21fEruizGs M81iodMaXW+MpZNVOT4oI2LhcIQqHzaJ4HmOndIwdRghLK49ufqtWFsJ16og2NAweoZSKJGWEYZC +q8sfstdUfbvHq1PiR0h1K9qFN2RxHJDHQ4iMYz3hmSNLvvrwo8ShhyJyxzTGwp3W81TUpADi7iA cxoj57Idgw6CK3LM6VucX7Tme/ifEFeqpEU9bEl2SYHQDJO+a+qC9K/fZd08906wp1tMpbunsexy c1NWAW8tXonuPlus4xHSXyS1gjHWqKoPVqWRNVEA37ot2IFCsrbnLMuF93jnTmxUYTqaCs5ElY1Q IETiVlS/NJVK5xQ/iCNxH5MjRo6uXOoNQRBPBOtcqgvgRjFkaCPjxU+OO1kqrnvSR+EtK/QGspKm UzT1ndFzU/+Rt6t0/x5Nb0TY9tlqICHC35TDxH7mOC8zwgTvvv439Ubba6Dyc99OwPLB53o0BxHo eyoYmh7eXACkBbpMzCtlgwTmoPTvvOaSEXQsAOoLaBU3muqRJwh3p82/wiM5WSgkTv/HwbZX9I8W wlU7TAP4t7Tl/Sfkqgb9NwsggD9Wv4xMuniumIw7ZXxrA6GEHi49gePoMS5q6febzVMW1F/6LZZj ToVHLg4PqpoQWU9h/vZ5PzUhtL8vixrmcdfTkdN7qEXuBQLf6XccUZaBk9dlKr+RaTfhE1SXO6Cq XIR9icKzYXe3NOZEbLxBVENecRzmmNeQzXnR722sADxKbb+P8aRs7+C4Zd5vUpBbheosgXpuon5+ ERUCMX+SqGyt3BezarGcHFt1Fu3KMta0Sf0K/fDeXB3UpnofPzbYYluIIpIBfdj2S+1XOPXqRWPr a9kYZa1Q93G/2zxTeuMDZb+TG7T82Pa36yIGwtq2kd1b3EweqHumxJDr8J74wDEU6kn/aBwfo0kF JFPqUZPOF5uCIwdBiIV4nmBTObxdf6IzBVnY4y0nG4XmI7cIlAGhhAoLb4807+qJvF7+a28rebji Wn4FNK4qL41WYU9WjIOWsVxyXGfxtD4RrLyAL4UkCgv9rGj8RAOLRp692QzSENhVRKNyCcHFDj5e LbBsQGiSIoV90L1HgTzvcg4H/RwFu2VB5/bDxoyGHj0TEZxfuymvvkSm7cQ+MvOa3y17dcZ4g1+A PrekTOBPJq9YIO3kG/MH9MSadpBDvHJYx3z6WyptBM5N6TDC6qdetefywgyw9KJIHlj9eaaT1hZm 0L/V6SN4synLfbG432Q58OMgu+5rfsmsnleSNbYbReDhmOqG3rMv4DAzCFtkAyxMo8Wrkg/4bJoB HrtmnqN4FIlwXjzJ++oXy4G6kvMeCzOZaFRMHnL0EOuI58RRHJp5wn93IzkXWHY1FkIo3ZKn4ULf 474t3goeuaOg2kIzsySgQsjnb2gj/XMDm+EMu3rqRQGwUxYh+phqIBttswnX5kys7s28MMNrOKsc DKrOEXWnNKT4NuhIfTkBNbXGEE2MuWwtOprxWodM8Tdx2IfdMQAyznx10K3uawghZ22QwkiZyURE ScDt8K48Cc8+z5w8KeBCkaItqz/71ZBlBSmvuGyTPzc+ls8COumZ/btiELMN88Tw6rYf9u8IKkhP LHV+I7CZgn2aFto12xrWGWrRqWv2goIHM4pUUldIttkwHJGFeyFxUpDxb4rHakCfhVMHXmAa6NJ/ FqRRAyx+0YIdLZhpbGdU4osD6/fG1sUYzz06oMDfulFK3rVu/EeOfomM5jDgKOg27SPQbzepM1hK f1SMPYywN/nLut/nmPGwqO7gkV7TUyOBifKT3gzGc7JbqaoSmQbEApZPrtYa4vqPwQ1UU3wSy/5u yXIocMrz2SSyyuYE6ErQosNPniXrYCqiWM1LbhTH7y/CJ9rjuP0nw/6FU3q+bCkOluSZUoKm+XXG 5LQjxq9fFjCM1u8P7jvaaThLLh8nrgqtVCndCIgwZI+du/mosV+jccEFVhSDgbHD86gh7qSR6lbg bDOdIdMcxR6/u5BbqovvTZeOh2+Oc2pfFkE6gkA1/s08Avs+uXZylYTJlVlAGAqJdmuIVDzfLwF8 quTZwpqtA6GHoWBOxh1ID5llvKAiFUTzN6NQMwKH+iRgM8HrsgSG7uim+aBilCxGwaXff6HrMoTm doHqb/nGJMh/zUhq1miEX54Kna69cpWdbG9/kUu09mkbCFjnmIZRRUETBK5DrEQwJWWKUncK6CKD JCD0aBPkR+XGcFD1f98PhzDw9na7OOyEqRP96omBPA+XQxXRLjGjxxZzrXX2z3BBT9zhWtGf1C48 JZuZb0J8mmuf3h22B8XbVnLQDCuWyIijopdl4YaRxN5KZnXMBVU/4UITG5SxAOtWRx96zsRHxk8w xvgcfVFSHmqEeGj/TwPLvWJS3Y6L1GycJXCQ9ynVdn7Xu2JpiZUqsFteNT5pvL3jebseRIEElVM6 k4DaN7noH6Rya+7WnrVFOysAAe0L50WMPMJ5Fuja4AzM2NLDGVME+eu6UuJTVppOe+bLQDBQLyrZ Nvml5+r1nKdVrHS0EFG07pLkQW8a/Ca9z3j7pV/I1aErXe69I5oZwcnVXcJ5rIt3X4/ORd0ImlWj +aFvSt4qbIh5lgYIyMCIDbVDUwjc0fxON65GkBCHkwaT2bVMjvXqoW6NYBWg3602U8elIQocnN08 UQjpE4Q7kkKMY9fUgUAY9YB+qEdP9Im9h96IdKMURorSE1NhqhJbkTL267G1IMEsYhC+TlTP+jmG zvYr/B7iGCgfiOA9YCCB7+eMdmyV5NaC2BnT3YjJMAedv6R0Br7Szmh6zvClFV0wT+mZlPJrSuVL +eB2QDOx9hsSH/+JQfmwCVuDDpZy9tMQ87Lcss/rH+mTga6CiTkV/gJJE2paVquOGeD4gkp46Qzq M5g2idp2G5NvFiBo6AZZdXbo33MPN9xmNWMjyYGHeznlaHKmwN8EVMNmDnkZ46KKPuilzRUlb3TX jhpoSO3C+aJodXfGHJ93PTg4y7zN9rj1qa8DqfYfoDMgt1kRw8u2LllRhDXb64fbrKUZ5siGZ6+2 NLqYGcwBGTk2BTa0kNmEN8gHwZZdp3y/RFkIGMgFCm/lizFBGb9RtP+ref8Vuep/O02B0jVkDegh DkIuiKWhv8YbViGUVIIGgjzT4T7UdqOK3nmbKuyZ590RMrp2HqNxLavqCFXeuIGWVl2CbN3FuBfI awRIbEZ8+9GHDVv/3vqJUSdHZQ4/Vve2UorNrVsyPknYQ0J49wh20BZJ3cNC6mDsl4jqZi63ouag 8BGccLOHuNNAxI5Hv+p7bqm5aQfeFYST2sDFDgxZDO0i5FIdg6y8b/1unpZelFqx9R+e0Wj6lecw E2wCySozyESTcs+zIrZgwTFHfIXR5IzzVaQCJPBxPTPW/xygU8DzBMY4NJQNU4NAMVa8PEgfHMsX qOD3bvx2n7EtG2LuqqlZ/URMM7XRcdyktqPsWE+uHjliTQ3d0IFPX/wpbtfohgq7Q4zhHAxuNXhd AG37/uxclbkgBpHZQJuru2NE743t3QI5iGEdsKzXDlUi9wvd60CzR3uTfqpeCevIMxEpkQQuseZX CATAJtwR1Muvszex8HAwiuHD7qsWWVNFByCoIlB+OqvAz747BDK03Tq4Osiwa2bNqDlvbD15D1N/ dj/SJsjc5uylrWMUGuvOILkBEjVEe6g199KG4+oTXJwI58gvH2wquMc61ZDH7zp1s/2XGv0hZGeu LOvVjm5zTNq+ghe+dz4x2IV7KWxgP4rl7VN+lJpmno6UUt9didHmx6l6hJnQZsDiT6Pfqr/Ni8qw YoJLVN638kVWRCeuCTFZ+ptRZyZh8mTYbT+wUd/BjF3dv3wDh2SR+XXaaJmfEuILKFGvVCdtHW9b KIwEXPO07FR4LiE+CR1hIzUYKi9LvQ50ZrN38+9Hm8Wp+ZCu6jgBUs/tYCMkPSqkmkk4TJHlOCC5 1IqwgG6MXwbDbYLS361Xa0WcAbOxbMzyrBs2aHKkWMtSd5n8hvPSPx6dF66g4GxiEfPtT/Pt1y37 KexbzQt8L3f6TtGdtI/KpFosbHvoATBqFQxdQH6QMh3LgeQqWJJCnpAbl2D40ExY1mUMDOuZig5v oeJbmWvYLTRNa3WQQIXT1YxKWM50emFIPnB0VzeBwupN5Ctd/hoWJ9LqyrmvWDplB4mA68kyleW8 TXUhwjP8KmUmghkR//0HPSHpbQnYTqxiOfkqNlhME8hGUkZGfLjyO4O+MAomxkfgz8A0y3HbYBbd 30shATWCAqdTrj2JVPWivpGrFDIAouy/z3LfOzDGMgHZycAzCFZJwR75BVkCvaUTf+uUiPUvMxTc m6Z+DhvKgH4WD1qoEsk0jp8rwcczxsgEiKdBT3UCbqDNeH7jMAQXSAF0aND7GreFN6tLIw/ZeLpo AO9OXJdRmNspojGkHT6JozLG9Ds3lk+IEMJrWpNJRWZdOPkf3+IH7cIrkLrJZRFQippNskblSLTW AM74KJm64PjrQUdVB/8+2wlJo5sIcQwjlxWdC9i8CpGtqPGNFeGIRae90Se0eIb7EwaDsReHB6v0 FxLeO1fcQS1eoteqMU8juYjjsK4j1n61lq2nHrDUKl/6m0jImhv+EOci86RJWq+KxkrqvfngAKXP ulvys/k41oRlE1k7Omkz6U/rl55sYBMm/geIy29Nm5bPixiqActH/wIEb2vP6usT3IJCtcPzJmFp AFOoucyesTz9uFucpeGBid9Y1+YFz2c2GDLzO7I50OofuAIOctDxDodAFQjaj1lfgOH+ChGch+eU ON9SYRGSYM3OjellrUEpGoamayuh6cTaHOWMmWySPfBYF8028RwsQwxpRuuLqgVsrE4Zl+NIj5Jc zQQU7Sq1DedrO+79JM6gvoXZLGgMKPTHp7c54bUXlxAbXildZVU9XpuHKqiT/wYgH90ifRTuR915 NpPiBgKJ/hwAmo3KXkbLhwvVVqRyi8BTUgXiYNlgmxzZc9o0/2F1nmpZt5/+g4RmqpdeT99FXir+ fNX0ShVBwSvp7FVHIrEyTKyL/TXQ7XRspnWakSv2BPX39UfO8kZ2n8x5bgwzIqmQPlGRzI8pUub6 J3ZD+VbZ3zti+zWIwkIPVRc+bRiRXLkc0h9jv0O8D+0am83TuxBvTuVCxC39mTY4vgukLm6u8YrM bzsyzxIXwNtw1cFOWG87e25L2NHfotXImyCi/d1Vt9xLZWi3m87UohXreFpN9McDSnjXpHC2iEnn 18bjDQL/CjmFEJPw/IglQFoKTRCBvyFmiuf+oTld6protBcnFHwz7C3JL33X2x4hWaK2JsBLilB6 zbBES/XI0K1G2sYdSrdc7WXv1CKdKd6xTRg3p33Lur2ZQcW9CUsn40YBDeCHTdCY+zYp3xpRxTlr gj2BUVrjWTsStZrzikrErJxXmVXOs8Hxuj/Yg8iBuSuCTblnglNWv6uHcVeOXd8cksTQWnGvGl9d y8IqaO9JJcJFL3qpOg6TuVJSow4wAHkT7yoUtF/wGB5eOCZf9en4UsqJqOpFhYNpX86sKbjMBKCN r9Www6YfvifzBmIaBcolWKVJrFLxoVSeivEz+aHrqMCVRUa4CCSH+amT/DjFV1QOOrzik5JxwxET bkXmGxY64m+HWJ32+ENWClO+pC+/gW9gMHHP068drHIA1XLoJ4S0QWqgkZj/FWZERm7/b6340LL+ w6tDevehpSHnjzfq8jDAZ0VSF/NhSWwq9qr5UdMXTH1eY6RzpEM5QJOyoKIjb6qmVBR/0V+tkKcv 38sWCJQDPd7LEjelIgz2a8y6XLP/+g5gdd1gUiF/Re2ltumMNyVOBTZjHRlHjyuxopUZ8j2ra9/0 dtCWrBU0e7qSr+zhziCtydCN9FzKBamlWtIHKw5RRq+OmIaVImjT+WpLbMOGnL2FZffDBLr9ykyf 8smWfRTOoQHb6iAsaUHFXPCRm1plUTMdG2pwg/HZdLnM7uWfTOu9Ixa1kHKBOvuvdGMVeX2dnJSF 5GbnZS4cmQYUrYzNSkbf+yTxeXw4KnTEUFm7myicFTi6LYR2DlY5RqXkj3/7ipAuMIAYadWCXL6M 153IjlMSqdZffn9Mrn36JXamUDIKPin9ewDXGwNo6gLj9NbVSt9FXKWBXIcwuxrEl++gkZE+ddds /yCFgGGtZrSBspGKmFQnKjTtPyEOHhs56skyPmki8kFgRv6gO6cFbF0SYKtZxKOVo1002Pth4tZY KGfEJ1Zw9yqmfhwKOvSD6C6rqf9i4TF+0xZNxmja1Z7hoy1UPxDoNoMcsIL4LJJ/8jxjzdJAsrhq pRXUs1YBAHarZFqBAXw7XVyYHBnnRWajn55v0QhUJR8c73n1aPeY8xZReVaGZbXKoUFnDDGCR4Wp 229ePI+C4wYuEtBPQa/4ZsoXHh8QmnXC8eNZYgodWy68+JAQ5XdykzJA4I5Q4nVunLOq9/zNXlQb fbaaeJnG8kLZVvDXkP/tpXrS2/iEG+LWTRtIqq8UOzq1RYCiq9J5VPngDy8Fn7kzt7ILqVlIZGtt K3r9fiwOU7gBUz4DCxHQtc90H+wJciyi4Kib63JhWLV30Y0etLKfMbPqpBiyk9eA/yuO2V9dqCfm ikjDKYrvYBgdaXyJ+XOHpnVfOeh6djxyHVfjyPr43hmdw3yCWRdXZNS5u9hwGs5CdvrSV42u+HpV xSH1q+dxto+ey/v/zRRRZn6WUn/RBQKGyiRYlM8Vj+WR/SbSmVCXWh4n2ALpvSYQv1u7hLUKv3Qs Z4OUcgzGrmq3pgAp8/iGJNrNh8EErRssgE1J3IZxIaS2HkUNsfq19MqKlanPUUnkGkkaOXyqOJMc VKPVa9OfRiyOQcIdBaNuQs/M1uAZeSXAxqlYq/4bQYvBqgRIkx0QCwF49cSb29o+u/iJIycVzq1w /vcEhp8ty51ChOAYzGrvt4NVIMMAF7E9XQF33t57yuZr/cQkGR1rkomUWzcdFimH6Zg7hth4lyX6 KwjDLP4ZEElTfMYFthR9J25X6AJtkVhQn5u7zql4Qt1VvjkmGxPNSbafWa6/XiQI3nrIbt/qx2hW Sto+BXgXYc9faSWmbGd1BIOJ//tFXinYGryMC+wCGTa7LxndwNPOCgtJ1H/MkwhjWbq81tVmEVr0 r30fnrm9ZOR6pNjfxdJYNyfeUl08ckzuHkxys51v0WxewuPfB9Hft/X8Lt9eRPnGxJq+Qsniqlh6 KyL8oTRX6PPOW2c88gGD0L+h1EMsN7EZKyfjWVfbJ0soCDmlYdDSIAdp6lFrP8ZXeTB363Kr1GyJ XQzH7TZTHxG5r5yys27mDdSU+l8jY2wvjUoq8hDyQx8xALdF7FHNmW6xjLMBl1XDlvgU5nymnXpa H5TYcel1JFBjcsgEfx/UjeQcv5w3XXD3CnNtc2A7P/ejC6pMQvdj4xIhuzBuSXzub2b1KKH7xhWU 7gtb/J1+BiRC7n/wnTfYX+Y1nEqHOweHqEorm3Tularroow+jEzKLKShspzOyIinLjMB3WM4nQYc kKITz8MxYV4kuKxMlKBd73mIPmnmTxZGbUQyF/MtbOxq8qf6Sc09ndqKkF24X5qndTp2x4VEZbXc RsCAOUzyd0HthbK4FD1FnBKdEvNI6EAlFm2Eu5/GdoH0buY+9NGq1F+KUVi0hKszntEuU4d9Iayk NrVmKeH0x1esTLdSDF/a9AywffZoNurBvx42zWkt+5V9CCHe++EakO8pNdvahuKd3HqtnWKfN9zn lCZrxmf1/yq9JK1+pAwzsqFDzTkNanUFnnM/b19Hk9qrwINYeqZOGce65efJBWHx1wqsJG8DF5/c +qyO5XQ1nOKGaHuGAE+7hL6rMewhke0ugwGCWibHHjPwyYf3tXBc/cI/7zUHENA6DxEC9+Spn0xh pjiNrjzj14IYhLhakOqW7ak1nBOiYF9CuB4WiaBe+0jSdHKSzqSaXHKlBLEv8JaUcw4Qm0mz017u /TwVtrSFNH+QVWvn7p9/XGO+3NqDI9aCuwqGNiyTUX+M0n2aUKCwBl0Z7GFDVU4UHjrs6I4aOZ8s 9BehaoJ/LdL3YlHgRgc+Nt+F94T+8BBj+cV09n6YG8YLR51oI48UG9QhzeuxdsBJf2fY3OhfWs/V +UR+K89Ho8lEs2n4KQMeCoYVIBMWy9kWY8SkaXYYssnhxrxrNAvlN2n1Lmyj5QEuXUA3FHi+AjIO KD5ASZuTcSRrQ97lbIqED/n19zzSclt9zJ8TiaxfwU0jAvn6jrmvhcbjgj0pKRD8Xl4HEjMAhWvQ V7tD+D9/yx5nP4W4Yj9FTUG4b2S7Ibimm3nAJ5dp038Z/tbb2YTE3/SizqrVDQvqWdDCYGke1EWT FfuqCNPphCJavAV1acxiZi9tZWh5XLbmvkEK586W98cGVA3YHThAFPfE7G1O31LJpak3E6wDJx45 cpQgkkKDydtLzPHDI+5MURuIEgy8kX/MGAIS0DGflqZeSliVFiZMtr6Bbv1HL6jKNmgOxYHye09m miirpYt1TJWy8l96TLmRvFkpgEsGqfQNO2EccSzYqGM0OFxKMt1SuG9UG+ZFJwH2/e32qGH1wtP3 qggMr4pKN4tLg6mKDvb4ThQbwVanjnlJLDmUKgU602MTyqhEchFY97M3iiZ/7Ty3m6eV2+osaV99 EHORKuKKlctvrx9Adt0BXhOMsKHV8m9x5zUHzMFOTQbWmuTQPIyeFy9Glwm175sjGUdE08jJUHf1 78JEQ4rHzhPXPO/ICXfpMX/2rXMHKMoFhHEE0PqDhgSQNqaPwdL59thuH/Q6Q2ufZRneUYHhfZla TDNReqau5Kcyilw3MxpAG6RUgFZIMhb0CuGTkjkprJ2PG13aX9nnr2KO3HcRPsbzviyr/TCFnVqv ZlkWUifPTcDZvfDR8tm3hgk+dMLjEw8b8nEOKdSqR2is6NeIqXgnLg3kUtbDUjP2RJq4JKwPBDYd FG83vXhInyG+jEex2fROk3Hla6f+gUU3ZPZJ1GaKWPsdf8udbTTMDvV+E7UddrYRHmWutC1yC4RX 189lAyH7uHfAY6Tq6FKPgW3RjsTOyYyJe0x7vKx0VevY+ZTJwV0r0o/Y/Zt+qD2c2HUDnx5ISc9F 9RRKlKuNfr0gCDM/MY9aj7WCyNdqDbWaUbndc2Mr5kWK4rDLunzHO3KBLOFcGcom97oPR9Di/gPv i8HqdJtEwXEPNhWgnO2GUXpvNdCOHA/gdjJohudERYoSCKJoQGx8+DdKZ58Sdl4cxw4KYbfQiNOw FxkPjUw3JRkwhN8lzT/Vqi0vvqjO3XN4u//b+9KRNm6qhk8QbpkgkOPM5ZcSSSrAuYQrIMJngpeO WB+UZM9otXpTRlMaM+BSMfmBxkSPCRR5ZRGU/mcJEgr8iB6tUcuMxVEX7VQr/ei4DrormZWvn5/1 Q/uh8nCkP4+pMTNP4aPPP0JAAJpMdA6sn5Krt+2/Hv3QyL8UTHbJsGUW+sNXzQVrVVLrzgIfyOYm LCKQCgIFxMuLb4Pwv6lxd3aK5yNuXvH0guhIbgB+wz39CPhou+3atKRvg1TS3yEG+3wk+IbR/Ivb 4lxfY4Dk4gqoFPuko4mY1l5gUceWIcG+mQftcLarvyTYhHvWqWF6TdK6ey+cRlKyiMP39JU1F7j/ +E6Iw1Sa/fzvzanAvfzztf/1/VzNG54f8TF2pBkQS40CwL+ZFXzGkON6DdWGHB47QjMxc3GLNiS9 j+FPETv6F2SNZe69jh5pg29lBwfK2H+PbWz/dZGv6eVDReEkd+/gMuoamW+uVdVVfQP1zXv0R7eX He/so5vHYpkEnlxkja56Cn5UF8mSENlPRlKc9Hg8tF/nRiWwBRYErTi4cfgS6YH30VkmyfX/yM7Q Wpbdk5964k576eVhWYwGo0FKvJMp6JTlDFSMoVHq2KyRz/aTm9+YQhcabuTw9zuUB6k244qCaiK8 8O1r52XP4NoH/0vW1elwbaCy4Qvk2T2wEvpRO/1xFbyyGsE7LvIdQZI3u3lKnQ5rawNhWTNRr8Ep RSyLXeCpxrKTZjDBb1Rrr0QjaYLPvRRJIFNHkl4vxE232+mYxFJxxdSlTlIviMShQvPhBQ7fQYc4 uS6XORJQJS2ELTdzd68gjNTFlRHHyN+2iyOHCD1HdUgBoVePiAs+DjyFx3JyKBxW6ynTuHCTt9WQ 0OLbMr0ZE9jTU0TLkvBXcIuSzT6eVogRRep5Z/JxTNBrOxK4lYJ8cn158WXwZVBFDsm7hKg6Xj0N ZgBbGuvS6Aj4O52Tpn8Nngg3GQyEnZKDyvkg18SyUVdDfMuv7P2Xzlq9xJHktMk6xZb34rRwU2Fa HTz9FbWE66S6hV8MbuEi5yEg+5xKcWZA85acGspCCeEP1MU8rxPaskMvgkGyr5YrD95SV90an9Xb KSDQr97CytW3AFI6FXxwNJP5TGlRbMg6jtLah3OWXH8jIKuMfSFOcdg+bf+ASmJQYtdKsOJNhQqi N6BlTWfM2ffTqGZuonSrLv5fyLRR8G5AOdcPNdD7HmALHhQDLNUUpfl5E2f0dcxbIOWCkbC7ljQO DLjP9xLyg/jliyz9mu/d5VxLwJIhB/nyLVHYZOT9ROIp6IorINlcJWFLDVn8Hc94fiwvr5erkjEq P+LkpvqbQqBUuheTBdMwLRBRSykGJJkcFsNO/RCok5I5CJYe4PoVWiez82K0EPjdLkc2HFhBmPTq IgEs4pVskCiVzYUV521QNt87ofZjXGCR3+L8JtxGIsai5cRKgDaoXUtvMbCpCO34jSVEOoRUPTaN 7/eHJdrLe7cIsEfTYTV9DU8q6Qv4ospMKkmQaDZ3XFClK2EdwsThut3b0WDHD/H5Zbb4RyDoXGrJ 465SUOIVqajOuoSelcxLa1sfQgPjoSlZ+p039txt9xCWgsjGQopdgWPj4vixKfXDhdOezpO3X1rQ shRNVApO8rsZ3oq4JG/uo0XJ4CEhrguD/nZHNJu6BUTpC5Ki6RhsfnPf8dUzDKBXBeQAAgaY9zMS O6jAS1Spsj5i9KGRNcw2ZX8rKzm45Y0joqN4TwNBBa0fRwtuuHsk3SK+tSoEByXSUlIT/b1d+6Jg llfJh3UpkGezI4KucvEjaxI6k13+RJeB5TiIhr3AOJjtiqZUAGB+19FEvAsRqdRTXfRfLMCnr32/ JdfqrATTuNoCwWlZYB9tYW+EQtaM1jRCiQ8F+jJNk8CryjnqcYExgRtgSKNwYWc4XMpS7zro8KzM AXRrLW6NNgnQdsLjhL54i4eWepLc7rKxxXIQQUzOl0uXuwXm53+cPJbcG4NcFr1nPJLjBcpPDMRP /spo/KuEqFh37RSNSQinoKQVFoLQalFhd4KROTC8Mk3GN2UNXUohaVFBzKh4R7LRHGnvDEbz/pRX EBJ3Zbx9iaYkGuhHoufTTesOZiXqQCk3Zm+BQrDeFfMmkFJ7QbiZnEB+bBRXYE3JIE76UFWP8rKg R2BMIfsymx9LqLgHvbeQD8FrPMePai2av0Mtp8F1VVFQmbd60hREMjleTB+HmDRUHNOFC1MZkrVc NLKURw4wNw62TUWszqZc1dIqG1MHvSVu4u+9QKdZHzRQKT/U1WBRdbgfUc3w+yCmqBFYsRhH85oz KyIZB8dpBp6oRZensc+AoObnhWtZBTxHQF4rA+1WpAQEBV15NJTleGxelaqCNrILEN/hkFbcL7GQ botnW8kMy0ePAfPJOWVzGMbNIjd9fouKWrbIH7cQyU9ior50LWi+Cr/+DfWUukbKZYGbTYtk8sX1 hndCZYrON2JASaY7pEXdzqA3FFE8xkNJM0AEtD/u6/9pm+fDyciNuvZlt+j/sh0HANEdCI+zrp4j whB6Jk+i4IouV6ICoP+TYJd4g9HbIsIFOUy7Z4H2TPy4T8imCjvFdu3yuF3HaYexE5TXkRZehyfE OQfEg9AMhmEu4UoDjtgJJkSBnVpljMEdUbD+FSKs8CeWdjyACqXvNSTzqZshEoO0t4pyseONfHep 60qmFQZwNmIlxBgu3jvgRKkMmm3QiwRipgGiuXDFmOpaubt7BaXSUqV97FHoVbFyMSZzssgkGefp yvnFmmMLFOHrehsVM5jC0ggSHTg//9sEwZnqLTWWvo+FnzdcFFRlGPzKfVDaWzD27LAChX8fujC4 p19hgkJPakti7L2gTnnvPWoQfVwY/lZf83ceDMpOuOSvwU0E/gGOqIIdYHA/HTkKgEqa1fHsxIMI y1832FzvDPGJ4eDHi620XGPh6khE3mXt8TusHfuor5OWy1v4xPZ58dXV+nO3lKgG1GeDW4uYRvsg XVjAQctZ4BdAhwwlkKea2Xr0LcyvBhojkXI4ox5DEyTdxZmiDCSW8zqW1u7JFpuI8jh+ncuvWX9l 2CHr0HHvezZQbfm+K3/bjljk1TL19sS0qyDGvaN4KW6d5BWoRuHAxTjN2q0LsNYbTQi3KmvnRLpa yldJ8Uv+pxMwLRJM0/kYHT8tVzJSOLHYgF3C5SbkNJ142eTdDwxdNrGWGNz3jNpPm8/sgjoDfSo+ 7czB5ujRcIin/STeqPGkyHMT/ZqNB3m1nQs/Ypf+B3vDLqDTujEhW8Sr1beTXCbsxjKOXAnXQ0XR 0NppCu8d00xvNkFBpUDFcnymylNARvqjR9SCO14pF/uPjPa5xlwN+FlY0kNLfcvkRJCzsglKDlwv P4pDnMKCYKuFx7yWdhQwn/8OtpQKiGmuZIE9Os7s8oPEZJ2EbZYCPiFEWDacsJvqGX+stjPyUeyu KyRmEHA/xbC2pkoDdfTdp2O9E0sXPaeHY4FyROAQwcD9pN0NSz84tfY9Hm+Xg+RCr8IMIynPZbs4 kOktpHWguwfz6UTLxD5G6O8jV05IT3uBu3aF5KqtXQ1dddCzXJByK7K+xawEpIl5p4fd7IQ/v0h0 SmpY7IQTTz6+bkVHrOrGrDQn9J/zZkhhW+Kd34Acz3TJ7rZVAZkKmK2wvFglpi9cIzkl6D8mrXvl M6fTfqeoh9zmak1e+g6JkZpzpuRGfKErLUFL6o0WjFjzCOAwAEy/mpUic+raKQbjr2Ww7Nti20AL eeICr2sW+YB3FZKJwRTEuF4u9eIRhp8sffAS1LK3sWmoOAKXtWk23lS9+G5W/4JWtW5hlPAxA8Y8 QhMvb8khXAk+sjM27uSYV+6SUhvOuQGOl9pI1n4wx2ne2UDS9n35zHminelE+EcEZ9tb2zN2hIOG prAwXay0JbYuXkniHWtH/eFuZpC5Skv2duDOF1q/pDgWhxvASRsQ93WGin5iXRSgvaabBO7yzY3S CCiALPZEp+0PVhqNBHPVeazO1wsFWWMplwau1JoZdv1ezJWx9C6+aE/oNn9SmglMiWp5TsNcFMyd g/gADtOdociuocpNBbWMbatk4eepn8CEIBs43hVZoBd20Ukb7/AX4+paLpuM/aJzVcXosA05dxeB pdvCpSDztSXIG5yFfyszk8eGu4zXAIr/A693zoDJMKBKD2vJYbYYIcH2kOSoMW5xlkfCwDqXtY4j e6hfFqxq34f7Ms42tDae3l+sjvntI57tvt+Mi+g1pkKpWydETCLOdmC3E4RMqhM5xRA7tKp5AdBg F/4bOfhkvWqgXbl93siBS7+4XZJAfuJp90v7FJzEFptEXK3jQvuLD2ghQbscT23trnMOUt289WwT BkFpUcd3cNkEJNG6MqZcQ8i2Zf9JibJhnM6L4kLEG5YJv+hojekrVB8OpntEdJ1AaP6lUeg6rr52 HoBMLx9ldllV2o+dzLvF2dzjapbjw5r1ICOtW6+orCc1B9NPuTKigjkBpUiSpmvytJ1WaE76uy0I Z/Z4QMSd3W4p4puMoA1/Fqz2qxKnBEjJom2gaGNY0yzFC+5rO9sPwS3ewKTfKO8Ny/gpujT9LSI4 zJcaXI8b1puSbbQKOVojzzhG9mXcPR21XDGAmpcLRbTk6BLtHX+gq54qUe5yb0jnYauNM948R6aS it+AS4zOVHvqoU0Bpg1Q5BzMYcRDmCYRv/sUxtFcMd2Q9CIM68QCKw+3KYgMN2E4ycPm/gSe2P7b 0kk8aonI2cEQVZ1OVMP6ffN/C1KRv4yqL4X1L4CApjbaIeYhfRH4G5lmfM03I8mAErQTs9ghPshN e6EAnrkYzCk0wsXtivYCnRKmHXh+jhSL8SjJO/p5AHwDWiPLoSAiDUPd34UFaJYTzMesnAEFi8n9 VY/BgYYT/VNvp+nXcqWvQdEFcZHjVjjVGlmdjKNoy/GMlXrYb3sM6BlL/wSvgkzYCLO2ZT7QVH3m bDvUuMIGrLTrYlLKvOLTt3rTPG8f5YLYA1/+xNB4/nycqwm0sAZT80Ww70kZbJQkbhoBVS+RRxLA 7I5hoDu0uB3xTvPJhTwHHhEPYy5+PL0e1thEDrNl76wU4Bxp/Bb6WjMAedZ/UJgQPz0Grc0p0TQ1 LXqzJne5FqmCqNOydH4bSWghAS97vt1C7gpOjKWBkl07YFdaETjlV5JgFzJG04var4OyRHXdmtzi BrjwJv8YuTSDhdjXkPqnLkli/UCkYgPFTfo4xTAD/Qmnfxs8+abO0h6QjNCzZVMIltgQrPwcLkeW 6HIdbPp+RaMm4UpjyNpBcxzx5wjBCvGWEXGiZzuhyKuukl8i8PHokMgGgLuzfHn+Q0nH4zXS/axx U9IU36V4cXoVvZnVlnw/Q7OXfgQoxUIzOggBfRGFIWMxC0JN1lIrjZu3/eTRop16A+/BgTLRPt8l SULZ+HkHn2qOogIhiwPgaMIRzCa84UkuiQ5iNnCrnBQaQfG3CxyG8POiG+DqvaUqvHWtfLupRZrm 8q8ebe99c72M4fsg525t7/KIiMXIQSMPqxiLjBGx7Tz7G0zK+IH2BnGZJCSWKdnXi8hC8mlRldBt 0Dj77S+lc6TXvPJYtLZFv999k4767nlRUgfGXmM7QuXIEW3KZ/CCcdVLJx2GWbC2KR8xal+Z7vOU w0iiVWKvm+sd+lw+WdF5sqVtWgxVrXqiCOE0bCYiaSRiU1fFRXkixs2pYfS8XFiBwxeIFrZARtmE ADEsAkaq0iGEx4cOyVNQ6JN57CurSNN9mNfY++GhTgfwtjG3GG92op2TxUUtqmWzCHzFKaq1nSms ohoqs6sCBjukqnsOg0h+qaEKh+p4z9ptmPY73WdYEfOah2awYWLW5xoN1A5WlYl86Q1Dsclq9xe/ S9D9U0P30WAAY8wpi4iXU4Rrnf2eZpf9iGwOHrrBt8V1d8Qw8b9M+O+mlCb3huuN/wB5a0vUgvwx eDvAtw6UwEt8Ypt8cbp6DhRoc2Ej9m6jxT08DkAtEbKmnUXQwu5MS5J396z9u4t7uCu3hGy2mpq8 TtaH5cxuXkmedPJVEhWuXK7CzK8JcEoevYN0rYRH+MLiXoQaFR6tVTbgeA1gE4qg61EQ9mKUnBlG hzAa7P/RInHmshicLb4jNVo3ytOuu/gulvHO76hTz7xEzCk/kOZnhrAU19rSx9LsnAWZCxw6H+rt 6/SMy3jx3PpnZy6D3wjOfaKedJl8PeT9/oRRkNWElruOxCUkQVrilP1CtjqtX3HafdXUirLhSjrB Uq/5oHNrps1rAh6e3e9RsH6jw5lmj19RQJMJ121IYnA1OUhRR0fcYx25TtJsOrDykp+z5KMJQnPl 6mfuKwM4b3qf3rwyNQRYMmWceJYxeun57SikWUgXmQL3T88zEltD9jePWe09m7Vy0M/G5mf9Ly2o X1UC/Y28O3n/bBFDoCdtEnbxsXDDnbcYAUh9kmFhGEEtzFAIh61Op+tBQj+tATt2S7NzkZghWJLy ak1OnyX273PcmuMp9OyUM/DYtF3VJNznjcQ5WcC+sbFpsk/+LSkyu2Tz2QR5qI7vPXrgMK27u9V3 hVKNGW1f/IlXuEkoCByUSw5+qFlM+HhZHkQJBgYE74hPwK4mRl5YWbZNU3HXhVY6Ww42S/UqE9Qf rjzkOTtzWkzLleRqY2tL+IprFpRoanupsLl1jCmn+5P19wMPadtYirl57/dUZUfwTHiVevkoRrsE TcCl1uH1V0diLSD6nNlFPRUurqGYkmZlMFunDOLQFHLmeFMgYSAoAwoBFQmKz5WWuHOW0uNTFwnk 6e0JxHp4XNkwnFPf8JxZrr2hW9olLhv7zC2fd3vjTu/61nk+fyXIAHNnqaX8Aor8m3CqO4N19q/v ZXuHGh4cO9aOBYh//WSmNuRB4AaaHtt+DPBriLN8SZtd3UftU8N9cer1/+o6ZMF2P/XusNdaTAoL vBhm5Pytbh9+kEYYzud0UWveEgblekdT6ml9UWOySNKg4v/hkj+chnxhPU7jNIWa3GMF5/ey5hdG Pqh5AfQvpX2SkGGsS9Sh/37o/YI+g8WeDmPtBlTXTcfe+zviZfQWMDj4B447jTUh+lfmq31THudp eOIDY4N7W7UdrZ/jGUAE9nrQP1HeO8qxuF1QYsdbXITaOpmbl4xpmP/5er9MD8MNKWEnmqniBren Zyp9M3y4f+9SVjsGw/BwyrIzCVI+v+jir6N1Wu9um6l1RQNg8D7lbNrxnQCTG104ML8RJg5K4gpr U05M3FlQF9iYmdpzUuu1gKbCrQVgwvOu1DBwiBFLSLk0JIP6nv6CAGxaMIh5/hG7u8R5Ai5waJar umHBGQMknDLKMqj3xPkmv6MJWteei1ZkoEiIw0cnBRoxF4CF/oMAG9Vjp7YCexdGpuZS2CwlyI1K 1SCeW5LyEisEgT14xu7UwuScNO5Zykf5+RnY9zUjkjH+V3ggpFQf0LUyVSnaI4FjMYcU3AVZoMeB dTjjnBTCqzR4RBJ1DPjwAmOZZ34lqqOhDcXaAlBj0lquQK6SjkzTipCocufhzKQn7mvhvFv7T5UY xr3bK5SE2zgELIZrUF25sW6SGo2WJ9uZTEuI/XK40BQzRakn9Fyy9RJSy5SMRQqZVuoKWYb83PP5 XvTQpkjOhQF9vnnyDraorJuCpch/+KvrjWqZcgUOLk0AP6YdsP7VmpQ4L58AlvL6Yc4YjFGSteZS r7G7EeQeuop4mP8M7l3V0ngmJbxVUFYncKb+DmNTZ2ml7Oed44eF2M1Qc79D/6qMXiIwsMlIFraF Os8RqRTeHSo+n2iB1cYhhrG+T8gapFlIWNhd3Kn+Diutm8OnCs4nihLNaLCCmhtNbLbFbUofIwDd UJ7SZVa2SbC4CYcZHyVx6ZWklZtLjnpIiTIINmj6jxm86YlMAkdPR7bZqh7w9vNr5nUbjdCzTOe3 qzQTB5AoQoXUWmm6E1GH09oQfodoW3ddxMtBnGNmZ4+xsLrcHk96MyHbPoJl4sPvMzmJxrcFu9r9 RkD4ODQuTbIuAVy014QzruFKtjdlgWXire2d095glx1GbaCY+uHmsk+QqI49Z1FnrQ+Z/O15ucWG eM8oWPSsHgv3HrUQVAZpDh5TAP/EwU44Xu3dh+srtzINcV2z8VZAkxqNzaWCpF3wK7bMHpr7nILR T3ZDsKeiDSvMMPK6RJf+GSTdfZdcKUCBS2PRj0TJ0DabitHMd0OzZTeqvYfYMVzEql8Q+/D0036G nxIbI+DXI4yE5RmugbZ2KUiXjMCRdsP/bSyPXTfE0/M6NGc1WazpdeE7FaI78FHpQEFhi4At9FOi vbzE+AewOHTGVhnXGxNhPzrShK1gN9k3YirUCQb83oyKzk5ZP+iSv6v4COwvth74KEA4BV1rkfAx o/ggqQmsaKF2+TjvKt7SuC+WgiXyJBAsYChwqa4WoJ78Sd10bW94Pc48tklclimbNfoWWfnsKlMH fNyBMry9jY2r77jGEVLaMDJZelcVVw2Klt4xNI5imDX9XQvDtm8HdPME6NrD6sSDLPCM15tAwLrA 3We/k0UbSpN+0Bf7Vzf9Rqo0PxdxyHFY4cAyFlSgRvS2z2wGICtYSIDeHUcb5Krnvz0e0NoWSMjd 4RetQvXKKFinPky7VJC3GP5JRIBpkUnifG6ReZrwZbQc569C4eUvIEcQQU7apW2TX05JfXN+onQB Dwz0+gIe///0wCs9J8r3leFCkk1sw5tLyJ7uJkCRz8KUgjtTIzmKdBS//1dM1be/G3dUk4+64yk9 kWSvvMVDnaoIaZnMb8ndHrIxonw1HCGKa2LyXIUbpXwgZ2fyzgH7HmHRxdWPG5omYAjD+PdF3JJ7 tlSY0PsBALt8pwQjqqVsGw/+QmSgPd3/NcspPgOUaPrhQ9BspEv4odS2QuvuXAuVqJhK/ACMxD2Q gUN08dWMd4QwgFSVa+4VL4qctaltCkk9yrxaz7BLATEbvI9UJc8dnPgbj6gFI/5IkkqzOg6ohdoi shvu6hc+TZnkPagLWcv5EAxJh2MjhrZt7o5/SqfD5Y7+PZR4YG9rwhFOGAwJ1QCZSld0uJA5BShN SxzgYYAJye4CCHMLhcG59UbMYL4RPmAxjt9YKVrzJxVskuWnhT9wEUeIulpdtkYyL043doHQ/+gQ FdIfCZGWyCHjQ4RD4yrMrgyDVlmjpV52ERu99v+jrgwtX3PKoadeD8qHhHpgsstrqrbq6d6QGqud DyJhYoi4TyaVJD+GnCnuolonR2kquKfmxFxLIaQH1u+28SJGcjHB1jnnW1Jf1KRl7wM/tT4oqdUN GRhUiFodO+g7GoT/D8zcC6BmKifAn+7L6nJrhwEaBhRk53cZRFrajpBk+U+riM8N8JGs3c0JkunT ao6lh6ld4dsv471zZQSMUkC+oui/oyAOaVVqxc6YfVDbqZZkT8ymbti4xq5wofqo4miemJ2xJZVf NlFOBDJAY1RsR3ZtP+Na+CON9ck55uKy/l4RhuhZvC7UzMf5oSAieXofQZAHKs6t/xqlRxg6/jgM u2PDAfqrji3btDLXru5kbwlo1+DCF6T6qdoMB6tmKCHmwtrDAK4WEqQWCrnUCyb3dnWN9M/4GSNF UcPzFkJmC8jIm4BiUYT8Ds2wzqRn3mQ/ihyofTE8Ugx4CQRcnDuHr8T0r6U1wiWx3t/nPyIsLne1 tSCsnAAaPBceCLbjYkAAC9MQzE5TYXtXCpvXb+SWfho2c+yk5Gk8kqBxpGR1ACAsvxTLmysl9sbZ pbAJFYnFdkkJEynY6jUBtVE9SJbz9C8KBuDv6xEVIqhYIgxtFu9+4YoLHLfm0aaidLdF9kOUMZdu mGQsZjYfSxBp7xlgJKMo9r6JHNPl1nIhACTTeZ3rNWLsKCMkbvNvoN389OgMKfXkuWQSaQuwME3v +lRQBmckZC6DOFomeskMWe+g8zqc5fhEIi+KmEdJl+o/OpA2XQzmGQb4g47I8osQAycfiTJbmcJz lsI6hs87NgNU7BToPTAD9DJJsl0A7WvKQLgomN0vQhl5wTHL8mcorX2bgWiyQuUyEfI5pfGtCfvh ze+P5ZRgLXHYmwe9FRSO5dohih7QxfZt9wdHe7zxjVlg/+u5fcVB8WbVFt1aEff7QSyVmEgjEuWn 5S8hJVOBLpTO8z0kKgBMzf9eL3W1vsrifU76dBW19kuHessTidvrkXp5VHbSo3iX7K1xQ/t+Z3DJ DrVjrsgreEENcOJ8KM0ybDWrWUmCSZXU7/LRC+myUFfThwc4NMsTfwuCHrVcGW+GwYsHw+UT7qS/ rULiIGfvs903Jufjh8WFx8x7MyAaApl3FKHYgLyV2DYKpVSxPKo6TOZHSPFNstw+XskYDfaVXj8R YDvjzSQA7wNGRQHQ73j4w9dj+0buJlOLh0mlCN1wJmLvGPaM0vAeGMcblj2d3m6V3tE1ExzTesMf XrgWHhTkDkuPcnYvbjiSBZ0iMhH5AxuHupMJ1Wd2n2EccYIZSgawwmrajsg2FNR8dahSH7eSFdkC N/9KHFMaV8R8JbnmgYizZkZd/zNLoEoFkN2dr0y/ktOrKyKh7yzEIV2e0il0lCOBceS9rrfSNfpZ 7BILe9xqOAAy6HGuy0bvwWP+S6201YDIRLO4aYnBmzdZs1RZljqsXthRh1SOzWXlHjNtiTNOLd6A Ut4I2Z+pgHXE51qUa2kr8edXMBcXnnalTruQ9t+pIcLqgaWKQJ/jB4ODSIbuW4NRpfIu7fE/GhYA TUBIwzvaR7IntD7F3hq/w4E44fF6C0dl8/VctCLa/ydh8lzJbTvxSj6Z9A1rX5HiSDRliHD9OgdO zKB6SGFv/v28iOpWFen8MDcWJRR+FJxV3sC1t40NHc48v8XWzSX9y5KfcrfJh9U8+M+37J8Yc7Dd bt/6com2+2qzWFah+TbqDqVMlt6Oq1iJYzk0fYFuOr8Fv01I6FvdtV2rMF41d0MQ0cWD6s78gDxJ TyD3qb7sYZuoQzlnJGZfN+pHln2M9Uyz7QZaHJIYFyBe0NepS7EtIKkWtE+B0MK2b2Dg/6H1jgnS Gf4ECUOnDa5k3ooeH/EJZvpBbbH6HIDgxN6cw/J+on05YEPoqz0rrUnITzUJOhtcU/1vguLhvFCp d34ucFB7dYvMXLfY7vGaKLloViKbiPi5i9fwtQ9PZOzaHPZqHQzeCceo0BHP6ERNCgg2z9DB+xlW orBMXLS1CYNuxkSHT2e1E5eOhDp9AaxR1MEnuEpbmrebXs5piSSNFZf/3FoRP9kX0jplnAASVjbY IRKIsr1PQtpfvKtr+idqTZ043+tE9UqfKErDXJW6C5F1H7tS4zmiBPW7/OeqdhsHPrtlIzhzT8vs d6vQHL6YgqOkvny7zEIskVTrblDdnnW5+f133888cC84KDYXRZ2X5xDclK8IIKM+36yjcFIdv+BL O6IGcu5qDWR7e8MLMUC+a+KczHYzZ22GOEWJHlRVR0q0exoBBFi7AKVAIE9/5eulPrfliuQ6o3zy vHsGCM9dz5KG9xWk3IPGNYPB9WdHdR1PGmeNGWdBa3D7C1qaHAn1L+IxxMF/nkDXO1uG+xsBVcJ4 Sc3z2Dc2Rtsb2j2yivCnSKtFUydurNbIg4EZzVIeZLuj2/hNIDTuccib13mMh+ARoqqYSRAU5As4 QUtXcP7ZusC5+UlFJrabSh2Gu0L3K2LMVOyrP0s/FXaBhwlCVOew80F4hL9aGFcGPFA1I53HipaA xv2Ngk/E0hog5hjo7iyBJTpKlrmHiXMwmuM0J5CK1cSMbTPasFnX2Zhm2hI4Dp99EZBE+MexpaBL EDClgSsFpBspDAFeAPe7XSGhhv1fPKIctorO1Q1qddxpRU/SV4t7vcLrxwKF4dPmpXdMTpVTLBj6 JlgigVfDWo7lObQ8UJb5ogMjXZHBDdZRYk6XcVlpB+fRgObdOxEYhG3VEOiO212AOh/yG77nn8+2 +W5EQw5QQzGK84CC5H3jXe15qdho7sWCxxQVGfiWK3r3RP5RuxsbCESNgTupcLhUEavhRr2bd/KW TtcWLfrgmtVzMhoWkplhhJ8tR3EgbzB61sUAAunUpmG9c9lWOkDlr9bu7xCA+nnwvKtSnkrvHVCi YDK6crmu7cn4S0NAeTcxVcRe9hClb9capAUPCbl6jggQgm2EGR0hr496ke449lkqq7wNghHqAj8e 6ofnz/XGRoHInJjf2UyHV3GHUESSuL3yaI94FuUNYnFX4s0wOdenna2F5q7r1jsU427IyZQ1i5Qq MV7akjAzX8hHQ4IWIBc7C72CgwTYImo/5a7jUsJ6pH8adKTpKy6R/RUYQEc9txXhSNc03hHvtnnI s91WmLvsODakD6hVrV0tpdwwJwcT7bNaAOzyS9OkN6iSPOgYtDd1Tw7jniFtcNlSzibWl4QmwMWn S/TBgTWlcVEJCLwgxN/GRMMzWZD4B5foeEzf9sBYHkG2pHz/F7RSMFkZ874QSgc/MtUSmdcGNdzQ tjiA3sO5uSjom86UqpJ/5Qccu51tUtr6DojKC/ASCrYoB8lZY/jhOskzx9JsJlprToyPIXelNav+ BKtPJMuUl8c5pdO5f/L37LrY5faFcSnSrn7THFh3yCTvAoiVEXUrjyBCGGbUIRP/qEeKpPCvckPY ixgGZWZDy7MivftZH2QMM17HQnaapDel79CWl6GvmX+sFjBjrQR5BALC3lbdDzADHRaBndIAzzzY WUi5/4TY5Ize3ZJUH3QO1fZEAQVGBgYHOyS4y3o2a8OfOS36xwqfnFm3cVBekFmO4h+VCXUVakd6 AxccVa5wrFIC14cZ5fd8SXQ+KCXw9UItHHZYeO7pV8AfKOsBzQ6gF36ciLjFsfCosymXSquG2nIx leEx1cYSANKuuhnRgpU5/4YAfSZvHocnZvCJ2NrthlgRZc+f2EFrXB5dlZR5h7AyApg3cCz39Iz7 QwX3wvC7XD1w68w/fFjL9zf+S+1EsKSVDTNGEzyC7sqlfnKkkNHlRpSwJUhoa5pWziqPtBNRsvKC Y8g5EoMhcPqgkcEmxnyu0zXvkxBYWO9YSIeCN4OH7QGnLo27zkODtEKDWPg95UdCTt67jSozgbvx Dgl5vTDc8xjwZeke8YimQ4bQDSCBlmoVcdfZ7pQ3yO+ycheMEhFUJSMJdLLr0DI7/Ns6brre6ekz KdiYKWUkAdOrkmZR0JwT/AxP5phR+X8mk2c/czLAlmfMX1is+NEwmwPJjyFGEdXgbzaN9A/rBV0i qqzjEQ7ZlphU4P5yqVYZAhT20ZiLVcom1Sf8vYLmrDTMxcHFyzr+NTmn3I5EbRyjUPtYfPWoom5N PKLqv4lEa+oAC9MQ7xRXTEt3Loa9WIS6cHb1X95KjFKYnBR6obzQfDNr6jjQgjxnb3m4gubpRU4K zLTnih8l2v9WQh0ohs66AzVYjILqUSihs8lji+VP1UjIIwZpAMRf3EuutveKebZnK8PN9RVi16Go vCx43nO70waRO280yS9xN6jA1fwO+8q0+Z+Dey4sZyv213aU2jCwYFRy9mjw7svj77xOYuGgWycZ /JB5KVAvzJCOpHHmQ9EvCDEtjBA9rPuCkLrSammIlveavmYXQbNxbYYo7Ykl2yoyBM29zaBq1+D7 DNRrab5TfSqtlM7vHf4d0BCPWpWWkndkBU4D1oK+AFjTzA5pBxzBGU81BvPq3zfd//iwVB8heTXc dgIXHOhGuANUwdd0fXt1k+zIub8sZ1083KparBmFzPLI0MTjod24wg5UNmCzg07piHQjrTNnolOf wvTAeVZTKnjeZgr4BI+guoLipheVHnh95Od1xeWqPjSTjK63A4/X6sdv9ZtwoMMA98Pg57v8H69R Kl3BhIREXI8gsBl9vMc10enXWy2oc+dRYpq/46u+5jIJaQlnqJX3ioCz8rmFSAmJZTaY2eRYv+sI fxRb2UbbtLElzo/7TPPDaSDJiPqjD5ws+V8OfZHaBkburnTO+UdHXAGnGQ9vB54jvV1sSf80cYHT kJFpAWD0EGDyfI66njkhUU197m2mYsMFngj+snYDMK9If+PM8+g+fEaLpcNRGEv+V9cc13IMIRk5 9PFaidKkKcd8y5DICd+AT5OAORLVzH1wCIum+eHnNTCr9zosk8jr27qd79aEByh+bXn22qGiFOuK BJAm/dshxo6/q5DERUICh4GM9iAdzzGjP0owzfo/bZp/q5XU7bkvZYnWIBL/AxaM+MdplEYlarNa tPkuZjQfn2wwOSha/2bY871Yoy5OpoPNyUTUnTG3dq7Aq+KmAWdH5ZLC5mnsn4ynObCjp/6dM/3x 7nllPN+KRcettZ4Ghrs66LbUbqUfH+4AdjMmq6pIIGcmVwseyqxflB8eW7ADktnDg9jCtGGsveuR 5X43O63+FDe8dBlLH46E+qZmwwI6sfZ6dKT00wfnUqYBudScqCa04abJfeO+vua9oC9QREVb45+P JhbvrQCekzQcrJjUtBcal9RJZaPgRZD+6OE36LCrCp+6HbrMK4+LLf77J3oE/BDk5OaAAScqMN+M uADoUbRo2UhYVPJH/ow7DKZA3DJlqCb3TewpGxX87YYDPcYz9b1SZXTcWyHsXNraCWLdZVQxHJG/ PlG5B6DShITvkSFMk+1tfX9TQ+Tgf13dGeVmprpJ74tO3A3+FzvBu+vpibEYFRkf+DKahJP0ZYPs fWRaEPHcxVTasIDVBVjhX8A6Jn7PXsFhY8UMOiWrfFDyNVC3JwsbNE40yUe1NNhuzfxwwuEiH19v 29ZNYBKGDoxE1O4Hpc3IWJe6NZO+7MDgOVaXvCP62zM4dH8dmMQnfymnYljqz4RY1ZQAssMyL70B xpEMAxoROLQQvx0L7N2BioRAesfhdEU99NTFCptuqtFvPZfkyl4HCZP6M5Xh8ZOeXXaxkFkPlUCd fR/2AuH3SSZPNwMTkAyVKNefpdFXuRcxhtg8sOZWy1qkTTOWfBdvdb6Rwf1P266Dbh3FG/QWwW8T yplX8Yl8cj70hULRqHd7tGEZFot74Lwnn/GiX4OU8SgSv8nZ5DGFz4IDv25i7fq10mnaoZnjjKzM u0rNscXs7dTYOsItQmiMgm7kzuwOeDw8AWfCzMCEB/FRtyVOD/TMrH4q2M9hmpk8JQnRGBPAyret P1OOhtDl7kyBY6RNUqKQCNr3DGgc+nvnBLH8E2XgRt2W7utYwtlo4IHtRXtWx6Jv/2OPBhDjuWKg M+oNDMQe3xrkW/i72r9MJrnupq6u0BmbK0Qit2PwAhmWP71FCTkrYnY7FfhjiPZOQxhe/29AplHu qy0EKBRPMf/EfCQ/GslyQaa3g+i9nh86ni9Ka+352ySRIUeYlCoPI6irNANALH4i1dXkH7SRZlJW q7IWcGTV09pVtRtjDQyuYPdFYfIVohjBaVqSynNZh+SJRISXdD8LAzesVsoAN0jpP8bog+DHbzy6 S8SxA76mCEhjj9QghNGMAtx26+atrkrSG3UzNggXILGruxitYtDp9oyOMbFmf6ab1Uc++K6HI4S7 pgqIh3+DXXqu4McEb0g7UNPwinJzCCgU0nNukwwOaIBoRx8uTl+DqASost+G6f+LqimL8/6TMS1V mHdfPtD0dK4WPTqr5nsVJTeJGgLjNP96dHC6SFYzBN9/SJ2Katn5LN+gKigEofb8bOuaz5NiKX9O WaF+vst5xUwxCvrn0abVRLx6r0rncZNzxkEmD6mu6Go0JPP4jJuo4cl9VFobb7fXMvIhENCjDfGX ReGK0fnmFMKc1Gfex5XFQ79sDaYBJ3N8UIEGf0upKqRgTKtIIrbydGZb244uzz3Bop1AJfvOe6vX hyhxkypTzRY+28p0FOZzzI8S3DVj3L4xjQRvngaWo8/dtmrEw84uwwKNbQKejBDf7oWg3hh+mfIo a6maepJw6Auk5dxKgt+2k+M80cQetF6qCbqcZJhKT7ZkmrNATI4S60qIjraaV4tTNRnsu5lOMvjW gnnAIdD/2ZACqK5WL3RSGaeaEIAVXtA4f/Lf+NAxJ7NWBKR86v7lY1E2aJW8kpBkIteH8pLOCSob EXAOqsylDPhMoLkDDPHuZWrc/TvQv18AsKgq8rn3nAtod0o3MflULxoajQzLMKuIsYqd/0ZyL5GX j1MyWAvMcKXVSHlUaEuzMl/HjilKz0CRw1Jy+FwFtPLj0/fiJfSywPvNP9ncbQAuPOgwiZQvmAkF 1K9w1ZjRqQvGB02OIaTP8QHVnSfRRY216yJgTxZKXO9sKSmSynjkZmVhsP/WaCF9/E/kqNUrpoXU pRtCkIF64klXXlOkGZnJcz0ppARtkb3q61qPgbUGSwVMPeETw/F2hK3a3NxqldB97NIzLFnzwnw+ OQzvnfmZ4wsdLU666TXaDIj2dw+lSyaP4t6JSMfajONchex2K8ul9XOWvQIwer8kSXVHDspk67Ek Jcd2zmNveIfGbmV+ZvkUqXjr+doz5Qv2BGm+RiiTEstSSWCOptrkSwhmZiPhxCQPhesvinVqMyJB t8df36q9GkseIm0fHma/QisHO6OraBFm+6S1+4GoCywU1m4LBgUjeEuSvM7zstBU4Pl2l7gfU8w/ 6wb8iyZAiFKQjCKFGYuxxgwOw6Qi71c4qj9YFgxyiWMt7ipRRj2qgq/eLGD/bsTQOcgbTniFgpgd w7pWpckmz5SYolD7UbHHlGB7fpPY9XSQ5G+1dgZYF5fPRbkWF52nHB/wVWaVmDvTcXssB1GfwKjl dMagGiqRf+Nkqg7NS/U8UX1/rFfTDtu3fiSxl3O+POCio1kS+1ZhBftTznjs6JQnh4t5r6mIuZfk D9q6HjyBkMW6+fuY13Fd4JDp7BPulApyHnHX99njifFsGqWY2BDZWsLfWRBqTohv6GqqO7MJZtIt Td8ToLk2eOIWWgqg6k5Z5eViH/Q3ECodchspVd1zRAY5+/8UbB0+zBkqyZv3A90MvXXIZj6v09RM FIUQIGbPAoc9ra4RyWR/rnyHq0rWwUFptn/NQf1V+iZ9tTICF/DFZsuct+/lm6A1kh+e6rHHs2sp fzpCVaa/2gByOWvpcahIy2BDQb6navxA6Aqs9EVHA1o5n2CZvLwg6u1ZyBzM1s/Nhgg2EnUqC102 3Icewu4dBMrf+ivxY7sZGCtZtWww3Rloj3wqTPHCqtbbh1Adv9FW9+HjZPAZh1yCDv9FVda01cDU c3Pycgqmm1hWxeUCimBGSFJRgCc6CSM5V9QTfXs441F6oc5I8qxqE2EwzlLa+zrY12iaxpMDPUbE q7v62VnhMcFy9UHaZ1RBTR8lGMzr7Bccmjogvnmw3IvnY3vWjTqcyy2l88aOmV/6vv35BpJlEC6I cS6+rOO/M18JZU0uDFoS+Sz0pvyubhgAJOUiQ2eFWTkXozMiWKF/SDpJB7cz39HNsWz27CGvWyfi UtUwcO898SGDqKhbpSOuTCth0yd/FILxbwBel+kh2o6ZJCiA5svvi8K4kX+gdorz6yBONZhfUQeP BYx1c9uEPvLHoPBrkejZ/XgP+bJiuo7KKFs+8oi9f8M9ilillKEzoaMWxpp+cnaKrzvQjQvU+Afb h7Hso+vtOoSGhc3OFQdkVScN407xgrcBVuJyuV2pWUL0MUlKqvy8aqnn8puqphUzachKM2gqO+z8 gKUuZmmjXrYYve8rsGhuFZWLPYgitV9Lv2jclitmDaO+IFoEJlDjMiTf6DCAo8/8bGgmKc3sNLLR XXQ+DjH3wg1n/wnorBCvgeTe2aoxYcxUovNjF/frvLQ65QFMPf/p5+kFpLtiMz40yD/URrK/2wI3 RfVxzkkexrPXVR0e/YsjnQrQyjoBHYlUZ5sn0md6IdwK6EtJUZHRQEENt6FwUpY0kMVFdKzHBt8F wn2QxqWPXGbBCaU3G4COTp3rJd6Gtuifw5rxfF8RkbzRF6ASlE06oDbJAtK7G33loirJZxoxdrat ewVLZpl8JdNiV5JWzj4wy8XYb2QPjX5sX8b1gvIh2jSKeIezh3VWVr2FEvAXr2DlVLSC5rg1AEFK lGdo972fnyph61p2noKJS660PreZhrHYqf+ZjkU1YTO/gPGe+NEhdYQUOztin8axu47e8Ke29njO 7jGZ05ndScAYzL9S04xH0f+OFCNKv3UbHWIv6B2usHu9zy5CQbnixIch+D84SAdvJ2SDWBv+QKgh IMIQhcnXVy2mXBw+sMZObR/JV4VBO06D5zjNZNRzbWmIHdHRpRFxgve5M4+aotsHDBrbYLkoXdjf Beg/R6drDosAXxIA5OwRnUTltV9d+XJvTmL6PEKoz+oiLMIzI6MP9ehXM0wSoO0ZYVJ5TQ3FVsU0 6OnlEHZRljqo7KgrqpkUdCtsscqBw0MVLFOg6Iv/ZS+CNDm5YovvY8gaTRILWkoqEWqijouqJoiq haAIqFKGmQlY901vFb0hyUW91hM1cDnVAH3DwwhNsTiQqKyXgqXpt4Y5NLbzSFmFcLm/w8dMt0xO +Wf0FUSC2+x3Lpfz/t9TCbqtNFpYvl/0SPLPBzObPZmp7NM6M6r0scF3Sq9piIvZdtlv3qFpwFK2 fDJGy1WcYs8f0MXkGTOeTB5zDmN7py09xm3urt6TsR8V2XE1awpwLkLTSSaKrwholuJGRRzaHZDG v8Xgjy9uXiN4VXWyxJnDEJu8CgE5UN53zX0fALMMjdz98nFta034VZzhfSItPHkqm76huywO8TFm 31DpGYgCPnhcquFGQx+kRGyUbp+CxEI8rvXenNG0nF0rkY3Wwk3LOU8v+Jwg6YqAoLvVH25UcEft Ky3cQSKdYq14HKY7tlx0ERWZrmht4aY5+urxO2iUNNlzsjT20Ghc4UvDB5BbrmvdDHzIInATtaEr rz6II2ip8PKsU/2hRUdLU39wx46QlG9ILk6O+iF13Qy8whO1UEtcesvtAv4yTpN8fc3Gtrrgm7ek cTws3TV3H7TIW6Dp5Rnrc4Dx2ZzYDfeW/fcJQMHKKn7oCs3oC64YjjX1T511V3mlVsVLkzFR/lVj i5gcHO8QVAyPq1SH+tMDr0/wRbSx6l91ltt0shs+uZrpOSchZ2h213TkiXy4SDm76ZGxc/4uz5se pD7gRT4uLe5nh9+vSOkGMB+y6rGyr4wTGiMXF4eKhX+HDzrBEWyuq3P2zxzmHBLXjK3keEJiN7ZE 9Sl7MFoUrC199TH4IQpA/O5hrx70jVo3ImKoqTILuyjeSIaezZaf5Mey8BryYizjgqTnJOt/kMIl u4YeUpDE32YcWKFnDsNfaBJrnccdjrfFj29a0Y4FqVDGicw7M7w4YtnWjJv0G2bSAlsNCWvtRfaA eyS2anm3tmVnTb/SuMJQuUG61Pmrl2qHhHnV9ZDnyc+QVoxO6GBJ764EQBOPliGMEak8LLKtfS5c WqWh82hToApIBzKEa8gNJBAEztYly2JN8KaOW7DNC+s+bP5YnIgppkBpxxRzgyzvM3N557XW3T/Q cQhjA6lsrzbkcowyIt5RTgGVuyhwMYQ1TpVukTxLhJaXSdJkSoCkH+bR2Pm4ND9AmeQrScCS1swL gpZ6mdn3yLVXruex+asdrWyKB4r48CB11R/+llj94oTdidnNdxNQw518RpXsikNHjTKjfiw6Q+4l mC8eoGtSGc87N5aQwTPiqYUAW1gieK/pb/o9nx5VZPDfPvWCTcGTu26t6O2Jjstku3IXJM16QHUb VXImE2YQPkpzH8gm1XrCaGq1q2I51NTzKr28CPCa/X+tJ31mX7/QE+XPep56KM+gIZgWrTvzxQDj n/gk97bi2b/HmfIRBZzfgdCHKvZwsjXC44DjMUHxREs0CJdUvcyk+cuopFsB8uzkBFO3uhtV7/m0 2FieMAJdkviojiIt6Wf5uLu3iQ4jptj8zSuyg2e0DKTG42wtoJ1YdeRXE/f4sqIm81lDt8bpSMDN 3mP3Osi/vn8KWCTtMHRsUrVpCeEWd1PWi9aHhGQyQuFjRIt9FTEQ8HI4gW6cLhRyqVqavLCpB+pm sNGYTLtm1J5ERf8wh3pGS0/xQaPbMtTUw60AOxvrVF126xyMGhvA7xus6xbVz1It8AldyJCy3zeg hhtrfkQjpPs9t60iQxrXdMIEoR8XKC+5Ll9xWix2IbLdWN5bNustfM5R52/F8di7EbuBtRrIpLC6 slig8tQFlaKOzlF1E8rFOyoBVvCHAPCR5EOCraXTw88fmkLAJG/uA5+IvrWzAvyHFjknXKFqvQ1d p+F8I774vRAYrZrdhXdXuVlwcsBj1ryB79VCgRLag8WNB23voytwIP+ksVr2kj/KFnIyGtqMbJtF 1nuqSfsNVn77VAllJK8LFjewvQZR5CKkkjm38AmiVnBBoGnT5SHJ5lTxCTBT1PwUwU0fAQ7Uz4WX 17vAJaY6RIHQhD5MsQfml+SRTiLrJqU9wU6hlft0DBEUNFw/F1aP1vnIOPmx+P/IRAJQtmhsmqxV kiQ3hM8I8UjNglBDixBu9G2D1QubX6WNn2dsTFONgGvDUk4tCpQgK40CpxF8nLLa1Umc9zM4dQsi AN8A7KPbw1LdXOzJ5OqBAuCHm4d7z4aDOquNEuYMOwC3nQYs9CY4N5cPsCUpkepyvkKRym9fGyhO y9mIfntQxsGP8LQd7wqnA73OGiLNLZtw1zR0+HfsNP9DOWdtcCanHYuGsJPhDdU73M4CGqQfWUhF dKDKrtgPNKKIHJlXamy5gu5ZYg4uLFX3b7pidtnd+d77QOmWedKGQn64fxhowMsc6PiX70FJp9wP jnBRBinFXKLQZAXRW+Q9I+CkOyHAcB5K6acmlAKqtJKpu7VPyFiUp8HhR3zuTIoF1MGQ2nG9A9qK 6i371EIVNzx6R7IgOTm0h/iKRFWZrO29/kc/LgBARQYZVedQHwGF4IxoDLAUA8XQhaEQ/jzJLNOO 08wOdZXbW6m/BtL1BTt4ZeBtgzbwTVsOcZ8rdl4aNv6sHPK7HPCXzE/AI3/m+etWuDhQX4KYhzQy xojWPrxzJnfE1JqzqjFAwVLxFzrjsVkPT+grb+zBucxlv+sWFW04eIA/cG+qBA4947jUiAtX0D9U lzpZQZ+0jL5vUlMeGCjliXWflu8ruAfmnmxjqDME/+wKmCU1Qy3i68FSXVjgwlVqWVejhOMAN4I2 ua+yl95AXtr0LxrOAG0dWdLO0p/25xO56a/KOT3Pv5Jrxyp27WaMpxPjVNy+yRMcC52qCaVQS1G+ 2ofuCLP4tSONSTpUVa7DE3pbne3CCM2pKYwvWZ1djLu7ekUeUL29aamgxOLkGo4cTPLuHa2C+k4m 48pB7uuX5lYIXLMseviz0b8ogpOIKFgajcQIlqvbDHDx2AwEZvBoOa7qacrVhAxEeRU1QFJbeTlS 95+VXAY+y99uplDePFpB2XMoOMfZtf4o47QMwP6jjVDRrUzJ0cj3gLS37WhGT3woGUeBRxflN78H Rp/DKpbY+CiOLSKGfJJMVVgrTFEQUrbtjuF9d/Ut0cSWg2YZK+qOHmfGKN0eNgocoi2UidpBrqu8 KhvNVcGJMotrKLomwGOda/qkgttREF10BoPWcnwcSjfEwmFVDQKcaZYbxqk2YNDx+NXjlLDP6vpN ZOhnrwTQU2PowvBBz9We82L4l3wVdwnyXIFsvIPA2eky+25hCOPuVsZn2lEo3h4nvy8AC/N8a+Sk o0BhclXuo8wrowSmK9sOJwlvWuoYqzISKn77j/vKSer8YO/2sA5g/ZG9MD20WM8uZPG3uPT+Ra7N zJzCx1HBLkyDhCylICJrYVQdN03UAUf1URGd8xJR6Ho6fd9eNA6C8Ri+6JSHElNWa7mhrTYdbsNE 6M9g34P4mdzm1g4hJtk78HV28JinfBUCj6/vQlRDKpj4zpC8LIZu1TXo0H0zMEt/53mB0i4Q3laf PsmaSFACO+BrXKeRe6GMpzPZpbV1Q0t5yjhTj1p76cLiCU0ldmilnQeG9IkmbnOnvBN46HtTiPCu BnhP9B2BYHyP/vsc/OSxsZfDhF2cQQpQ4AaujvfFsyunfFmSw8zdaUrYrIQMEH+qw6t4ScG/7rTh 8lV/RqPVprKxB5OLRNzqaLfuWQXdm7O3MfJrl/PUopZemDiZrCRkQob+4/5rt5lbq/FvEC2H5rJH H8qeqgTp8cbUQv+JR3lNG06c2Fl5S+MgKbk/5uGuvhcjQSVn08QjAVIJ6wrgpvbB4i7N+Ig+gxWs C+FBbpM4zkTpnEOLtQG9NUIV2Vy0YjLiCERDqQFYq2hTxbhcx+Sh6uEtfFawyxjhswIuI60qlX6m xmT3yI/sFkXU9LFH+WWfdNkuWQjRc14oVWpKUqciYx0U6Za0jlS3hULn7Y1vzNPEuiJ2atUfSQnJ ZENtKBLUF4iVWypAo6HYTIDjVZVIZ/rgN+P4NmUQwu0JBdI5Nst7vrsyhxymlT6qguuTEtR5T9J9 FOOnERmyrvVADY8oqppptsqIihsvjnlRBPnpv4cJhs6dy7RRtxE+6uOvISTulP+oSbC4rJvps2fI GEZ48+7andG9gkTFSj3kxJwzXFJyL4tPD1SDAMvs1St3d8fluegVagZFKkpMgwjIjU6O/+wUB7VV gYoCvUey2S7oj1pSP9Ibywm6lC7dKtX/AKI02v7ktoi6YulYNx3jFs2qGoXf72OYGbKoSYjN5iHz 5SJB4IW0WTCpeqODcB5LZBCKwdmaVWjNfBd/SgwMvzth+cJuv91fiNJWvAlIEV5WoVHR/KYUyF2M 4GV+cLI32Pey0hW8EyDYZmCGXP0vbWjvutC7OfDRKZx5oxargZ7CAQTHfQVgHM6jFPb958BnEI4E cmkByNsUXqYHjNyCt9qPfw6mUdQRv1rJhwqKORBvs2xCIx0nyuv/uZCokAjU0vGJm2M2tWamTwRX BCAv//zz8nxnXSwAf9k0yVEjjr0olC+ENkpJWFTfill2BZN51J7Eol1nF7i0Qws3P+TSDBY+TsiZ o1C+qNpxE2FwcGEUTbnNQjM5BzZqIfj31Xo312OSZhUuxIuj6dpo1xGq1q8eAIIca2v1KU4OsdWM pYYsuE/f1GMWBOvhazunSHVRxzuV14JcXFEgAyCfAhdDLDVOrvJ2RzoK3WDruT3ZHfjoKumbiuhG 8hq3u3+TXwCwHaxuTgrIzvVKu44y5rH6hKIxcwEinkx7y0/80hPw9tEqC+eL+SVjnqn53elbDG9L hXBNMJ/FkqWGxt488vpv92eYwQlI8hslNMlwdqKed8twxwRRtQyC891mxs+LdtO0l5ImhG/hWe7p Z7tfbAkzCQdwqd/XAqnX+4TqgwUSf3KSRorzTX8wURKjqL997Kf8N8eufE3IBvjSvVV3P9nQXYuH 8UY3u9nfuBBQDn+lsy5B9AW1rVvy0bzw3t+xXgIZfLTbfl1TsT1rkwYXGeA2qWNj59NaKNoFbuLc vM/Szy0vlluqffKcJkhs8pWN1ywpo+8iVkQgAt8sxIK5GLqkCgtQUpuSVdSXoC/EoVutEsCgyOWJ GZvDo2uWLxrkl7gYoeCAj4KqA1OGeC31zTkPrtyiwgwtLxfaIZIQ/kgqKNQB5P741VkyWJ9p8mty Fh7KXRkrngqDnT7tJgOrpHO9iXpnwCRF45qunapFGQNx3gZuCC5fRkXAqpVbzNkEHZruqqtKuXjA 8vMpUSUET6sd3+VsA4zkKmGpyzWZtIeOGRedpbdobuxsavD+DGfVswt32sBKR9QblBwablV9oiWH aMyasqDBYZ5txh8oiEvAhAwlNBp8lOskEGDvBnFFFkaCAKpfItQ+8eQTdjjV6cxdJmqsF+j+N3kp uBLk5AMPbPecsmaY9LKcoulKpViFf6gE4NHjtDBzCmCGAlkFDlCezYYWJ2WxtLoT2Y/WYf7mnN8B hUA1Sx5IZjT5l+tipcP3jttwte8tNjohfq3eefjq8IlLrxPbSsoI/pl2exU0f/VgxA0FF3hI9IuV JHEHffR7aSycylQA9tvMN2HBxRgOpVV3nJdf8r5/zuOnKvtzVkjh/+TZUMPrSeD69ATPl6kW0jRp 3SPd24ADxXHCawnZgLSGeM4PZo4JHmpB0+Y0ijMZN2J0HxkJfH8+dnh8Lrh/oYpR0PLbNd9+59gu I3BURFTuEjSlDtaw4z///kl516A9of4d6eaViS6pTXjh3xd13yq2xP2j2ML3FQ79efskadLWeqfj wGS6IwvbmIGBwfgsgOLkEwCoWCth3fEEX8S6CmShrBftFq9iwQhUarHEi+2BmprCkdf/nP0V4mam 0XRQSGJC1FIjHOtobf2MQqNvhmFl2Hjc4Qjky7CovBM9N8BkTVMeOd821z98wIer/vr5Wwr8UViS lzuYkLHYOVK5wW6PqoSR+xttvRksKU5UBY39T+21kML+T7MuHDexKQZvyUEVZP5RyMYNElx0HrHH cpc2bqUj8eD8Fl+gtsjZ5qYV8ifFauujgfk/IWilAG8jmSOfCJUA7oHrJApcbYklKE/V5dgz1Yez zf9evCcW+AYTcWVFzOiKfcI3GCcNMB2KqX3G5hDD6il9eHvncdfhcj2We5mFZUx9TqgN5SDmAgFM dbHbjCpNE+RLLlDkMYo85G4WKVda7ea0PIE4Ewa4tCdzbwRf7BGhRefeG30tSTDPrTB6nXZmNYMh C4lDoXSeBWPA9MyprviSBpq+WH/7pbxKreBWopdKF/vCyQ+3t46VvWUN1ZIbEzj8nnrjm6oy0jEx isGxmb3hnBpE4vOHi3nQBr4uPiCVqXcsl7W/ppb+KGMVuCKhpkWwRj98tOAYdU59GvAKnEVo/HaQ 0FMvboPad2Ttb7GS2HZEgqFb4qd6pnR9+M4HLgU3iALeDK2lyVQ94kp64899i8hDI3zUoKxHgwFH iWnaHxXo5cy9snAwfS0krnNTVZSfneukcI3hSunOoHEEjcdKDlQtfSQlyXEiR2A9NJaTsaRFq9Hn HlX8vWOWySNeboCfmjN7hhgs/IXSJkGoRaYloWpxCilU2cfac8w1BZ8RhUsWizbfaL8VA+nR06I2 cTElvKSJgl0hnMnyj1nLExWmGglL31U2IeY82gk/+1YzcHGDMjllDq2zIKuGtw26aOYnMndI4MMt mxzXcjVIDJ+QjL00qrr5J8hQFt6/iaTXL1w1LqteKCQY50cF33I+s4NiHavJlnYQiG1BkicMB+TA GiEUcYqaZa7whCNF01DS2v3gep7AnGJFxODHHiIsMXFdErLUMGe9V24P1N/YvMuTCxtX20xIvfs3 H/ykuLwkFO3SanOJrXTbGT/XO2dtrWeGzjoHbzFI+AhmM9TayQEBNyAnnW6QDelWYje93yqpZHZ9 c6TNawTtO9H1eU2T8pqw3W0j9p6XPWxH6sCy/SiVdSFdIOtEIocUo/UitDTwAbGB+XvvuA1IAsRC R3h3kU2r1/MdE5LVx02d3DgvOCsjWrx4jxyal30fULqS0LkI5UhcWsvhQXtkACgMJJ9BYGtVFGAf TKFNKVBTdXklq1XxjkC4RvnEfglHE9UamQUiSSKJdFUydUzKY7Qb+VNVZdRZVnN5Os2Rmdjcr77W 55pIzBpjgkUvdLcjjIkReSvaneHD3UhfPVDv1Zl96VdVabse+d8JaNAJKzVT91OBC78c83xu/JSC 2AcS1jQphoha6x9U8I9KHa4p6lizg8qXgg8kunc4+VTrkual6jES1WhJceby4SAh1g0FZT2cKfTv L0m+8Uu+5LXwKsPocNqkq/+mRI1INDqnVfwLZFWkIHfa7fBoteK3neZoRcF5E00MyvGwO77aB5lI mKU9pHFQnvglX+lTEgRc4LgL4nd3KDcnfc+xaLiuLq5XsHoQqCpz1I2SPJSawYv75Ov3cUEpmUy5 B+AHLBWy8LxKtj0xQMV9epe/Dc6ROHikiYBL8GJF0G3BUY2aXwbvq9G5deyPP2LuICSb+4et+2PT ycfDEFiRFvUBOSTuk4KDNZhL+pvvjdm3adQ9Y7mYkB01qqEefasQpsHWspO/wdfoRdBjNuPn52ci pka2lSutmvpoobiP5+puurLdbCWIxQHQMJ0rM0tv+AqZH8/FsQoDSYlBcGGrfJz2W0XegTcb0Eda dpyA2sWbUT4T5lzJAbxfzHnivMG+CDx9AW89QOIa8O87MLiPUTBioEQ6PlJwRGVrJPhaVL0Mcj1U YGAj5LOReQxELs+WAQ1W9HIpKzY3OF5tUFQa5B0ICd9W32jhzZLtrXoY4Eg7CAdbZXqxHz4GYCE3 PIy3Rwfuns1fc55B99qSbaJNX9cqWWvf3fj+59bEPY01ORhACnqVvkBLZDj1CcGMG6frumsN4XJU Kii++Cs9xNJAjWYidntSGFhVnJL3yfG+Ot1gBNwjClapkuCVxJqEgGst+Z9piAZ4o/OSG40/m84j Xfoo+Mj/OdyBQ0Qek6FN4yKNGirwhHMpxYBAAPO9bSQvrUPD24B35WJ30jbUf0c0ua48vE+7qIPu 6/wxT39GIJGuYN0Q4FKQiJBuEJrg+Pys957ap0eN4IB6FQuyoQK66sjrozQA7YbTW6L8FMv1kZIB vdBXa7XVw1qYOUIu+8n7PKfAvf8sDSZatq9BqEl/9SogcHSOctwbqHOhIhCzs1oU+59Wvhx8JNcE 4JKkWrxxRZm8RXAzv+99a+HOk57TUVPf1vcrrDO0Lde2u3AZHDNNJTvDAOmCuJnOQN/oCjYikwKN ZzVy3CnIXw9K2CfN5uDsvXzOayMXlre7GlXMvu90jGrG3PyCs08RD3fr+MAUCwHHtWVtEwoJ/NSJ TPn2Xm9IC6aRoqHb26tBd359jteo21Q7Hr/dMj19pxdp4hLArzuFurD0sovTR7k3YwVdswepWr9k c2CPvB7oLhqfTUCjt5fi0yVMKQGLPgbUZYil9O/O48QBSczW4kOlODLaFMwoqarJAmW03ki5ReIj crVKmd7Gv+7PvDY/wej7+sAR7nfEtBsnxY7iLOA2rtQ7kicSLaJ2minhBIdNfTLiEPU2utCF+xip DDqP6wcBnkCO3qzoTYSizRR7/ES7DLis3QydhktF9quh/UNSNU6q5l19QXZssrnb743yx7RBbbef NbNcnoB8/mOkXXDjzQzBXfagX0PpVLK4oG7CwNn5WWsPDnJGhV1/cQsF3bxDp39ZKSxtIMzJv7At +NBktInLB1gAaGfuGy0BCOhrrNx5JNT5/Mvvd6QSMTeyEM6Ev+cfYbKt8ImiItN7aKYLQqaxrtAa yhNUJmRx4OXPO2mOVD8FBngSr7ZeWWTGE2NjEQpdb6Nth5BjC+FSR5X2ze96dEiahSaD5dGHGrPC YsJTg5zC3UDV/eY5xnolJPOdWrm9JC5dwp4n6xEGM5tvSQZA3ewgns1gUa8uM/Dt9FzWrTEx2E7f vJaOmS5QbPh7dlO86kk7Ytm2xYtcliRhGvsY4iE4h9m/ORhmwlud1sI2E1etm1iF/h4nngkm+FRo F5W9CSJ3W2aA0s0RwTEMJdtlEs5KSE4zKpEGKzy6A9bbRXtjScBU1N0PzVpcdzDKTOduVOoN3aYE /I5Yogj2Jo5L9uXYev+N6SekKgdznDgvcwidz1ksvh9PuZ6L+SgFXT5u7chNgo6Rlc7F1loqvaH6 qt1vaC//Bw2rcFli+mZlFealynntcIyexdYPGNJ6FJ5ngr9gQjWn4td6DU9qK2wYWHJ3RsuJjloh BZNUAJu8z+rwxZs8C1APIQ93MwFcFboxJeR2KAQxZOzx02emtFeLzObSA8z+sH0QMwO82N7PeVIk Xs8r2XUK/Nqc/BkLIXEEJh6VVP1yJcJjWf4uWccVNPs4OMPLzm8GEhiX/As1f1DamWUcmkGo6Mqv SsqAwb89Zb4AZpt8hra1425SGpjwTp4KE0troPz4xkS1kdYCFnpxNB/SNe48PZTlgUu/pENs7GYX GgOAlQJUZ+NrOX3E+LczQfY7JfhxhB1lvrk7HskEaQndaedhyTn97xqjp2l/lXoMhvmAiDKWIDNx 7bTSmW/iUvpR74YQGLJqx1CwxEhq9IBbSMMtBw2eQpdimzyfeFYF//MIoFuuXXoiVCazeAtwHaUc 7nl5+wtXOy0GwCI1o0XN4wP7uyxNKn4H62IwMo80EP1XFT3m7Ut7rQkZpwyX9jqEqzbybbBVN9PH 6/V+SFyvllo18uyHXQ6u0zWrBaIWe1LWoMOq/h9qZrdRQO0b5kx3uIYRggmFGfm2m05lbHfTW/3H 1SVWBAya/45uTEju9ly0TSqCX2ywuLPuP9KFhXvidNTGbStE3aUgymf6xsq9W8LQtu0tiC6OKkrH Ei9aei8vYGXWmdY646ImKlijeGc2YDEJuVvdyfxB5//WLzsFRr2LHgY7OlHc4TkCRnT3OlGPUnuM Bjo5MvYZuL84JBdmVwymfHEj7rOWMC0Zfz1s+S0iH4xkXPO04iNS0zkrsv5aVGEPyhgg/90wZCCF /2FkRnp1kWrYBe484WcNTEMM6wDQQA2zMlI2ytfNeR5U7tWx3nO7z99GisViEsoXkDpQY3cyDI7L byUYuTzVMY3zamIbmnSVlMXb9CFC6kDu03Z8wTRafFfBqWg3RzLq0NVkxl+Raf0sZxthQXVjfgdn qKSI+Pb2W0gQSd1uqTT6joBpVYiueX7KrR/ePnmxPD4JLfSXzCpIyPZaBzqIsW31cVVHFe6mpbHI 3t/wBK8de7UagB3XsUlUcqHPp5b1yrs27c4+6SSiDQOctHHTFJLboHhgu4OsRkKcgHo/MuoI3av3 G/xIwEX6pZUo0AftGzE3qRAbK1vqveNG/YCJwet0xatGsKcFBQHu95XhVITTDS0NWa9vjXXcS6Ze ycMAWj2T/jlmmDhF1SfakpuOfcm2NYDYDaH0EAU1eXrh2E0FnxyXoX3vyKoI0msL6GWHHSGOiQK8 hcUgu9xY81wKaws0YvANn896UJLPukSG9E3NbqVQ5Tfcg2QQrVM4iIlE5YJygTuXUGqedA3ZwM+p yo/Ej9pgU4ITBduIQEtY4S2MN3hW4tnZzzgT3/B22UXHhPQQNZ9jLpB+sk5zdCmjWo3Hmg7nGbn7 k58YVQIs0IEeUvWDMwYNUNdtTgXQ3iVRGOHre99eZHEAWqf7GvN7Mj73VRgWcQ17pxbQmBdF2CL1 V2upwef7yCvrT4oqWTSmhMyeMCgRaEQI+wBYxBcGi5rr7Jw5XGsInvm8GqOAYBejnV19kgXPjBWv ++WkIr2PGUr89FC+TRX/0yEJd0STxmlm4VrvRSeuFWJvks1HEpkIksq84dGpfn1E4UZ7F2iMDrBr W639npmzq5smovoc8SOuVIHs1ns+/TDQb/y3aJR2qZz8QA3kIq2Y2zUNoKwmnDuk935e/Zk/4wUY 4IwAO7Tjp3y3G4+kyrYA2Nv7eJ+24IKNp2rHkcwLfwnIwuKMlPgrdzDfY91dCEOTNLU6xBKnsenm d8se29pwXtf2OOrksxYA4jbXHmQaCXaMhjcO7e3ubgAcodyv8jvzVGwPGPn2+VK0UoS+dGUrnTUo 24lzcboXUsTLjpd0Xsrj/H7fQVbLvCs4siFNYoYquPOUGuwoWQaoXqOV0bP4Un8g/Pzkau0tbkCO CMZuyg/jpz86ekdxsMR6zmY0nzrezaaOCn1JxxmYPUH/VLxWCJpGC0h8RDKelxrK/KqtpeRQvmt/ ra5DXpjkzKCl+KlBMqFbA2fZmkhptCvfqb0PvIm50qFBlnhWXh6I9zZH/+mixaiANq4+D3NIGkQL LHnfnP4QslIsHwapoFSEXYWTsI2498Ic//4iwUdV6IaTjjgJ0N1yaGY1AE9gUcxFqZMYNxo05I2n KDq4MS/ASBwD1z9vio3kHUXqbRTbGyhuwupoCsfWKU8fMFIjk79qNeeNmC1PZdLXqixKaZAj1FlH TLfRnwIvyDu3M5hKSxQXWmNVEYkbY1RdibMVottE8ICiR3af6BpGVbqKrFeFF+e6Sg5QY8e2TcIa hB7dSjH9AHfhIXECkOORIdsKR4AmcYLbxKMF9wQ4XuBmsA0RKcfNMJq/h0q/fJMprKGN31QVYKXd yn/pzI4aj8zf2O1xUnMMZh0dZHnoC8u0L2A8juzKw8gIzC5wLWDO1+OVrjR8X4bftQLyqkm04vw6 z9FkK973RT9NyICQIGfnLhT+nscwAxfrdYbfiuTjGY4BwnanIZUpGW5/u3zUYi/ntWMr13OfZhxT /maJKt/EPh+NjoSrxjBNR+4iJ48PSpgAob0DZFiOZyZTMLff+ucvqZBPI77FHTdgF1soqu6606B8 NvTYqzfzls4z2X+f5K/N1nLic+993FIF1Wfv8uQKsXySriJJv7lFfkvwfHl4d6QdJviwjqjdBjF0 XnAjUEnaMYT1EOIBh5JY5K5ZtDK0FAlKMM9VhmjzeqCihcZos0Yfd1i+2ltzrKl06DZ3kr6RdcPm igQMLUEt3mRteXtb+u9r2RGg0kDK/WuOU23C8iMOyRc2bIeUbbR04Av2vVtn3pPs2nRaOe2LFmfi rt77hZfXJkwZrrymSDoMWvid7zgpBtdWcsQmjWnF1YYOXRwQnT5KPAxnR5TT2VEi7/Hb4zbxZEqt FiZzhdjtZs918bIV1b3wQnB2jNLR/0ZyJvQKRuemV1+KnAgoLINKK5m6V/0+vFX8G99vvhvRSUWA wbZ4+veEXM5/crkPp78xgIt4u+IU7qinjr6Jd3Ngaq7RUMr623WG6C4NoQ3uAdhkozTOW7E8dJpe WwU7zPoMQq0nzfBqUXVH407r0JrC++eD8bCorPbmmoZYO6uNT1CX5PEWdxJIzbulRFnwr5pL4Opw vzJCZjmC3aPnkgolWvMy1xVT5t8ewhLP/Hgx93tGYbdsFbsgT+Hln49QoH/HHGz6wTc9xkpkWAUu UQrtxfE8A4tH3YXWfmlmLUiOgn93w16XlhBj2J8AIff3Nw9Ga1UAqX77T3wdr4ZKQ6gvJtQUEfnM 7b9tL32MYBlbrYJzbKYVGtJveAECr6ebKXxVD8IN8mtLafG/I4/hIgOg1V4H1LGmVcbNcZIgtZg7 Pj6jVk85YrQUMO34k2avmLgYLfG+dFAsnbmpYPFvvmNPUwext0DZ1aGuur6Qt4l4VsMuvrbR+SYJ lmAgNAO+a6ZgNLx75g95y3tQKDcoLusHmDwlEReegt4w4LT4kk7s+j0/Ykpn4LASL5hiJsIutUu6 0XNdNLMrI1OQBHcu4UAO/qYmIjTg7JscerqJ15Tmyoj1Co+7IlN/Y6ZtixrGfQNh5lo6ScDOodV9 aUJDYl0ntZ8XVwjCkuIo10qneJbD9Rga/S1Rtcz+iZbaZ7XD6WvWrOa/Kree7BdIhD4LkpjVwFEv CWkBxqzf8F36ABQ6FFg0Blub4lKP51e4FZFok/ztzV76GGVnenJVK9OeznlAcw5b2s9es37ZcyGY 0hiT355dGnSIzShBAylVfgUsVerm5j51fkqBu0Uiw/o0OyK9ETPWNlWw5bEapkw1GNUScrUy9QVn vVggt8+JnOxL5EHQTvc6aD8DQu1+zoJL55LxTRAZ0ksL4Sw3w0m7hftGVOzMYe1bb4csM/+J8Y8G KkgfxKlnbZSoKuymWCIu1Hl0a00DQ+0NZkhMxibQbmlH984xZ9zYbHQsXfdDp2arovygg4J8fbp1 xmZeeChsoE/TGvrVQxIdllRdAUozqW1TDwLiVgVkNaAVx24BNYDduujOBg3A3CRctldTk1uDepar UZRY+6jSWNJwFTZJUI+2LtyLoVjsDdI9ba4tDsykAbBcqRPDQdxadLeHml4TWLMlFiP02KS29Rew hrTMPkwNVggMuOcQ7jzkkBLROioQyqo8w3/vf15hc/nC7qY6QlLQz2dDJrYR1d+2JbpxTHjP6ECC 27h2oj91V2vNs85o0osuuk1YBOPmLSFUGMKzoNVL3SQCpEjiAg4fnuG4Xu1IwgKpNO26mh1BOAQm zFrsQ3rtdaWJPWKmcOIF8vc8CyN5sKguwvmrTsBjwp+acC7gvNIqiL9Ns3S04HCGP5GR+lnLSwLB HQih+vPKDnBy3GcYNCoBJA/fR/9LeyqVejhW6wyB7WFqA+m4PjQiHii9ZgkelkzjXBQ3hzArFZvR ej+VE/cEi1spX/wzPNOKMLhyuEdkR1eoemvdai1vyqqXAtksoxe1tKqMsafrTgVm7SaWHBlUAVRg ZVUCRy2Pq+Hum7IXeGKqvNE31EOU5frrvdRU1vL6xK1TlJ45b/7yLBWhj1AdbZAujWAdzOiMuKsT N0aqkUb9wwx9I9qs8SG/v0z/SwiPBDFQTKUxEd7zaMi2SDLHVQ7ibvA1tKEqwHEhiu0ZFat8xBEd ufsjXH9eD1X9OGeex7SmvzK8uG9jhLR93gpG9zbNyNiEA+AqJOl9A96h831IOVwO24IUUZ3c0PPz KnAw1/Sh/FGP+Nxpm4X4LkwIUrz+D9q+SboMx+unxlRYcGzgu0NMiC6/pKwMRUnZAk+SCP09f5bx K47wXVWwgYAr/Zsa4zNNLdgWgpITiiqBpFu8iFQcrDJXi+KD69zL3kLxEYhDn8Bkd1d0W/PSS+HS NJ7n+5ADdFpM6TLk0uXrd87qnEjFgPLVDb5anbzRzY8zQRR1oCLffNLUipeIBTs9L+e0SFvQ8nqE xHUKA+oVJ/sZVGUv5vX1pjooDRae22GRnGIPmCCus30wKHYsgZ1xNQyg+An2oKPEzuaQwwRkR6a6 xY6bmwZ1QhX6Q0eZSAmKbOW++vNWyfG643+Z3ERJ5xfRNxqH3WoLRBPkgimMc64XkpSoEQNrRzt0 kt3eqZhmDpKGnhrxnecWNGH87aQ6MT+X0ukE6dno2SRzc7EAW+Q6Jjtbdd38ERewsE2WmEQy/GrF 5oD+7BK5b5nmsW83JBvSIDC91qGv5zqcz+hijuXcNPrPoE7/T8wcHRcZwpbPbEdhawySyeY1vUVS e+7oNI5PbID1QtGm61zc5HDJlUy3+JwgZT5yzbw6MoIKqKwDYi2qeNMJLKz4aghck30z2+7+cDhT a5CJOf7F8pejyBtMx7A8oENTbS1eBVQsfUNgodabnymxCzNKX4lgwR+CUEqD0FCeLvAc6Ch9EmdU yNQ5DDkgfg8eXVLMe5+Jz9kZ0QNZgB56O73XQN1dMSlwy5aLVScLRpSdXEZ0QnnQBkXIJ7xNzJIW y5gvKGh3c4oSCzgdi/5dKWrAzHeQYEiZobmEFo4VklCrLog1M4mfHhrQ57WudApm/EL7GGzPemSm HQhCQhSm93aUmSY1vu5u40/k1FCHLtUO5QFwO5SyaO6MoCV2nq1JZvsN+4kxLtfi1tDiS49qweaB /50rD3yAp0NiH8rWGjUe4ktrUrOoKZrr6iXzi4+21S+nLjd0A8DfvVBAuPTMneTUsKois1t+Bgrf nsqKJMbvupDftWAafcBVSGy+b2nsrm/OQJUwfbNudRTwGMsWLp5H+0MJz0OwnTPW7mgf8a7NWxZP AVlIVNjhxk5uQrE1tPmKzNYUvEkuypXnBdD8FZuLytwYxVDuPpvusCrrIYnJjF8r7KaDBq1aOC4r snMqMXOPOTMV5KledrJH7Hjv5X+n9I3qoDcZbGeq/Ar2uqpitaZFoXHGUJHphD+3vTlZllsf9Ic8 rFU/n0FmHwonDUkFl9SrO04HZFB3PYFYhTzNnQcAry52IuL/Q/BjrilD1cXzUDs4D6A/lKLMT9qO +DsVXjGDRx1QuOvD1FHKbpXLfWScbqYUVJNn3FDJqalq+/0M8Y7yp/CdrmnixgjxCFyEuodnOWew /AWTpy90nEZJw44fH0F+m7zIj11xh6t3yxGeRonjDq47VTpMbrSwQtl6XPm62X2aeMe/g+L6nXYo RMnkV2rS7vEcwAGFNbOYa365C6rB1Ng/qfAsC1xbeDNmK6KvFTAnFrenuD+yBpmLBDuRf/4tVRq5 8Qc6RLjLSVsoZZv4INfD8RGy0Rtsq7GVs06LJDp2VhruxqC5Z5yMfbnXNytLHCupczesc5OeqFqP e6XihzRIAXFaU5xAFmWT0Pud0l3DsWchJm9P6znuaKZbrKk+TGKcxBSsICQizIYK+ttj5GJMSXBS pPr1GAnO/hb0R3qBSiWU291KSk+48pd034KQ3LrIfdviwAg27tyjLR5gyDuvYjNZlwAGsh1ySX+y adqWZ/jshBgXrXW7bsuI0BT3n1sGjaHtz6wkxVtYUmCNewvmR483lKHs/C6BSwKu2TSJRbkivT4p nOzrNbtGK2vxdg+zBCNWsnPMO7KWB0IhkkXukNbhWkxsBfVA0l1Hd9aTIFBX0XzExBl+HerW4zws WR5X/AjCr8TJjedqY/7wqiujW+Q1R89vlCv2R4COsC81AZIy4Mq76FGBIWFVgp0YrZLVytWP7JxY b2bGqlSAk/pnX0rI/bHINd5/3uHFbykEJjS0C9aPw5xMO4z+uLig9wiSsBgwBGicX3HVoS3odKZg Y1nRsBDLF/umENjg72Rx/EI28SQM8G81dk+nw07PuRjV/TjPgWnvLwDm1XZfaqwwSYCH2EOuuFTP TvYtJ15H8RFhtxgRQCn2CxZLHT9Smh3He6XAtExAuC+Bg//2Mom5z5mlzcZRqi+qkdXTjiems0LY rqzz2HpfJEdTRL3n3cGcGbXon5DayvB/jWkQQLjfRZtnqVnwhamV2I8d048QVoIokWS603Moq8OZ N+bevmT17h9pBq0dc0ghJOcZVDCfoWiWnSw1vmQKzrODfWVa6LiNIMVrN8r3XyAAqN45pCPwYMfI JylOF6LQXzuoFqaghTbsEGREzsORwUhEasMjl6BKB908RM51JkHUDiekOi5+IBKIfM/1MQILh4ok VPgH9F9uj4wnbJtOg9Ty3jPHDryWDF0qGjzIly7Q77IsTfXEG1Q6zrewE0J5g35A2UGqyjruhwHt DaZeZAp4EhTkLh7FCh01xHjI2xqKRx6UXuGBt1smsgAykxTlXlpujpH1KBt1i5JoNBtVk1jrl4ln hDlAF6g96wRbw7NAUcmF48PzKrnPdy1PyxOrA98sxL61GfYjG2SyM9v4wiYuHgbNCOOAY/Y3IwSl p0EtBGHE3F9MovBoQ2Hxkgud53+frox9S+bx4cgzNJl2KLjZjLwgmy4lEYBROe8WzX0c673e5k5C nNUmQRY7pMljqN5nsNf7Qzjrf9MpRXJaTh+BJBqrqeV6ezTbbvWNL7FfXn5wSgC+XkessUWXA9Or ENpd4G2DIJUvbTmU4cNR5ktmR/0Enj3/VwWjUXbWnhkwTewpg6tvVYtzn6b2Zh+DrnQAP9pWnzj0 v9WI49TlSH6I9+XzQ9cugGzevViox3DjMijF7gUPbL35Bjleh0vBHiAiOalKDXV2+Uf5KurrSoay Vnt4ihw6j15x2OY9TZHR9RCXsNsI+0JjATOIC9QskQcOOloS4eNIFNqkc+e5QA5Ke0/n+/CgaGZy l/aQNnj/v5Jfd9toEOPAo7Co70CVg2U+FASjR3+HMybNv3ILL1t1ci7O3CeOBTfO27mOWLLn1AKu pkIvT9A+XWh99yaQgGM3sI3eRLjfLy5Jspb2MVbLn66/ZaYV5NuBNiraazmfQ2p+7dcp2ixgCBE9 LM3N0HvQc5pogBnugmjhVHwHp17CVxZuwjOPzgDS8Tk6w/7jgkQiHqGN4VMYDJf3GI+iu4z8cAOS 8zHvqEdiXagUitw/4LkMKrrDzE6NAOGpIW8qlJLy6XzYaZtqfrvpU7u0bk7yYHI4z46dCRyOau5B 1ndofI+xQ8ZvT+qnXY7xcgdCIti7mOEYuYdDaCpnQSIQgIB9LmmGzqK4C+pbawod4kvXJ+sNFoQu mYTDuwmeVRUUAS8kJbqa2m0bY9U8TO7K8Ee3P+X+M9Ig0f3QLNU11/g3eCdiDV+EAVj3FPLkAdwB MiNKaivWpIzWytdwP7neKUkXn4xhpUgHmwLyUf2n2t1DQq/wa3rTtqR2SJsxtcJYfhAxwSFimMey g7Ku6CpIq/NdIvG1iKiW8Fbo71pO8YK3okZz+zAKHVpM3D1X4b49eYyd9RfPYqOlxLPvXsuKiWKl yy3RArVlIi1y4SAngp1PGJb0mzLv5cUTJ2iJ77CxDHN4TBexaN7ttdXuJyQ/5O6l2D2UMXCNdHjO qheWeRCNEvrkagw2Y6oPzpdBnJlyWU7cgq6EMbzzMu5WOnWe725YmzKI1xgG3mfVO9JnjbyNr3ay ZmVOuitaL+Zo9LmvvvvT0rSAk8278o3MgDkIsxJrwawfjF9E7Z7ypea95RSiN5ARW6qWALkK4c2Z EC15EXa2ggWyeJC2UcQgkt7jM1dJphVRhuaKa7ZA14DT4vUlyH44IPa+M0vUedlNLeCe3GMumt2U SvkalL6SLLU8l3FVgB9b1Kk2slCuH32fQKcX40N19xpcRx3SnA3IvlVp2autDMUoqDC6/chMiHIq BxkVDGqzDkasf+vjHUdoViWm1xo7Uren/X/TZPPZoMke391cOaYJiye9nFz+0Qo86U54qPdrg7CQ JzEb8JKTpr4QIXQZh2bYkT93xN+nnG8AVfG02JEb77CFynogJAbRlklc9nCt+FrQFhLxa+KsZcdI iPQCWmtWciXyC7CgtkTYyvevmLSzb7y/jZtJGTIryntvnzman7wK4xiqqQ7IEvxQ/ZjuEk5WaR1i /qzo3+zxQfjU5acHPJm5Ce3A7IjBdTgX7pdaNO3yUxQmKXS6NFIazKvIuuBJJkbLEiY8jlCDbOct DyRhhVR9q3koMhAnmIko1t5eacEOKYz1nW65L91v3hxpiqcuEUe51Bj25/6DZuRipQv8uVX3GqWx pdHuYDwEL+p7eKfM6fWfLxVA9bfl3pZL/xu0JrGpjgY6h4lIwBrC8SVl1b4Ei1SSZcFhIFUAclU4 bD+6RqkDy8OBLQYUHdgsKuEsIa0ilenhRBqykOLw0FCPBW8E2xISlxrQ6gWLldIarsc+ale/A3YI 7eK/vntBlbIt4murfyOtIKCkVUaDMubaCUkuZ7PLMiPzRU7JVDe6ZMJNHH+sbx3Ro3fXX0bE9SUl U6B0LfkfPblK9GmhNoO0ouS+cLZyI/2vk1baxKF/vDFx94tIPcoSWFsH1PsWh+F5V1C0U75I+r4b Rey7NoZ+QnZ8b2pPiUhdMMi27dxThBui631aLXBANjCvaJi7/CTaO8iiy90xDR+SpqmNC5EqrM1Y OY11oSV1vtYNXOKmhibce7ve9qRrI1lxIYTepaeJ3w9rH4OzpSHYviHltPT09sw3yQgeUMnZZUZo Jlkq3qPO5OmlHLsGn4pdHMLKCIkWuYv5+r2W7Ye7NUj0YkSMHjsF9GQdR8XHUGyGLUTJREJcU1Vg 15yd/djYs47ZBzO3DDOnkTouY8HVR/I3E9q0TSGABLPRQnL8FLU+dCruiYF8Fovv0sq2qha9UBmu xb2K7+T63kd1BwiT/OwcOeaM53cTFCitTb4R5e6m0aEboUkH7ThV0MZCkqS1TWKuZVXlBIWFcRBL WZnuaoM9JMR4QQyW+vqTrKjFfoB9cil7dFtteFlzM2q37w+TOH/sfmrf0r82Qei6SQl0FBk8szPd nxhhCLrUTumdoRFSXnr7Kdy8N5CntRtoJ+RUZLtgzOiVsnkA34U4HlnHWhQXjqKBljOnPbB9gZvg RVb8y7fdhRHZ99osvJ2E6nouW2nLmSGfV2AU2SHbvvu8jDNtjxZhi/zXoAqNIx5TWwkDtuOiF+2P AY0//S0/+bJSApFjd2L2VARHMfTOBOYB1pRGlP6CEFV260yNNDxxQ+6NVg18/NHmUptxefd6eHB7 ydci+ZefFP/5XkorokULfZlftsyFMyWDjMDtcbRXPVyjk0p9uRz1NE0f6D/VHU3dIPAiCjlGOc4E 04FqhM/QHOZLCXRVUbEaJOKsn+iVD0gFc+lFz5JSRo8rsU26IMHT5PwrYO/9uisdy0mtXHQ60abx fJjjRvn4jz/XB8cmgz4xtt28xA/mi/I/25DemIOn6S1L49wvdFzJepcD4uU5wSAXaMM4fMFMi6Iv mlSklZuPyeMck7fsN4wYPimFhyNXG/9SsypqjiU3/WlTgL3ixnHKaRVx4uI0EFrEYV1/BHbVMRT/ 60jQ9vETTWY3klVkw07VmYrXbomXTMTENWVxQObvLDojA7lpCO5L6inO0dmDIF47QaJClWsTHet4 2+nTbd8PmxMlha2ae2npDdX1fz3fIjd/6mxTv+0cDRRrdQq3AVYuX+GxxxgpVvfBtzA44y69/5ES WAfI12tYaM6EbrSPWGDhEkrGw0SkYmWpSTIGVmlGDIAmAszy1RCjs+PnklhX2+ZTfS220JHRFR1J TIRo/91r27sTnyf8D21U1gX3ftloPo+k0AT9hELCfi1J600eJDEHOsI4D1v2ykXWJ0w4QyMQ0572 LJM+h5gr9Mfwwe7LB6Xg69+Fs0gcVqb98IWdgXcYPsPdO3RRzyN4vDrTM65wMuE3QQ2AyatIQf+C UmF7bxmSY5hRUWJC47xt7n3LRzrZhh8LzpxOWA8wPsDARFMIqIdyqWet1SpJUiJrVBjiOMeCpkA1 9yZhjZo8oMIRoRMaBHzcJhHNPd7uKltqeeNoRGfwZGt0/CDZaKKp2qPGAR72b6drQ6yaremocPkD +9iEoacc2QHMUclu8hxqJhyp1/Dl4hNx4c45b8es7KxXb3kP+WBYwredRq1pmR+R/SKVvtH6+IFz qsYXojy4WTH8mhM0F8sir7al6qgLVXExMEMQXrc3z6OcdXV7GRZSAKf4dyt2FzpYyI5dMHOmuUac BKtbFrJ2fHann2e58u0Cw5Wfxh89kc+nEDm9dBEJLV4k7I2pq0AOAFqNM+C3rmQMSR04PANDwsb/ l2jZvBtwb2lXH++N0ey4Cl1VIlGTBYWdL61G54uA4FFZJ/bbPIbSmbCesph0E6gLycYNIP5DdgX9 QLMeHY6+rbQb89y3mXIh4zK98UFoWqEI0r6Qm0FX5rXj1GdBHgJxWjaTB8pRLp57f07hQTU2Jm/N uQVsfVjp4BUtryjK8dnr00QjWQ8j3DVfukIOHL0c1CdTI1gFZRCA9yEZkjRz8bbQJWRQpvvUETnS UsEwT20mdYASTqPhq4fE7hIpdi/hXCoPB1NRNz+lNC+ioMEpi3lCcXEvvIRcfx3lUL+1uZbJCo5d sDGWqpArWWfK6DBPy9JwAIIUkzu5mHFupUM0F+2c8lgV4HvxVavOJIjBeQNEnTff44FVNkj3BcCK 2V/Li6O+xjFZGLUjXBe36KdT+UMd5i+9pILGpSOB+MqN1TwlapZy6HGxeieJq5l0ZSB2BdbhdmPt VMYLbw+Zo8GR3LByLRdJ7wgb3N3hqY4ibpzPZPZsoBpLWiek+AWsscT/d0fsikB6eYc2JqfBB7a+ /HTm1t4RNZAub6SmW4k7/a3lzTscNU9/5nzEZxMfQB4wSUgibkqBhTBVmzcquYLjlJSqsQXAZ1Hm Hm9ZlRs7r4T/afYTgwDmmi4vQH+q9VXNZ3hZezhBIqoznY0KUGkROLyUNQY1kEZItgP0orGx7gfv x1ZmORJGbyViyndK1f0EGWA5ZT9BpfE2FbY7ibXGGFc0jdgPKkrFOAGXnraC4j8FUjJjq/vaIpGr E8v4WurTQIIQDYxcDcMHsxxNSo1XuvSURzCorXhLgjMTEXyxCdZjBFUItff/x0IQ8fWm2a4Pp1jf MNgkTOVN9pJZfZeozoPZKICSxfaXMsBEA6fgxs+dqtM9QYlN2PqoHgkwQns9RSXH9CzFYC6nPD18 wZ4HTXXrzZHTgR83LHjDVaJo6FHnHwVHQeFXCQGqRsqcLZudpNuLxHUu2tak1aC4LllChR8xCrCk rtRcFLnbqtiFQiaEMBgj9t1fDWtZOiIkzQYLoCY0w4zeIeHuKP0Nr83XScnW7gLeGxBbo3d8QjLH I5m/GPo38n2cNfU9/XVgHjNPhUAdrMJA5AGQCFiqwwF+bX0koHnrHmE3zs1/dOV+57JA1TWss4mX ZY2ZyrIHxxTu9O/IGSJmMRz+SlEbPL1Gi5PZKjRjZtpvjvPQHVvjfYvhpoxzpVS70k9MCB2V37cF R4enQctcC1G0/BHSb3z5/tuozCA8cLzJaPqMC6owu2eeWaNe5QREYGH0u7Yv1ikP4gg3iW1bPJc8 GBZnQjRXAezX0P2kdYXgN0eNuvry6nTno9sLctnuM308ZelyHJu2nMdcR/undnWwJB6GEQJXkm6K b8fGtXnpCB07E5h2VwylMnZhbbCBPszKoE1qONR2trlxOmtjSzLPeGkfaypbo/zs+vcwdCS0TI0+ lUgvjnseu/cgCqvVhLEPAVfBvrDO0HO905OC3eHBN3PcuuCQRmL5I+6RUm4zInQz3i2HABm9ib75 Ep5tCuN5WVqD6Hu1tqbN3XwwlE9Sr9HpwjjraZ4HJaYTInSt8sqFBMGJlROtvvJksLXqyk1Me8uG K6rcmYd3GYW+ORsNSCLzeKfgPkF0xYOgLWA8SmTBZhtcjEB0sBBrvGF5g77GRxkkQLgSXnR0R3Ia McBOglUwtmJv/BJXQJYBf6Z8emO80R8tKJJ3JnjojioGlRmjVF45q7ry7+V6Pwn4Neg2AlwT7M0m Pf4zT7lRBZ45fnxHuAm5aC+p269tY/S/AtzooLxZFyfyT4drh9H/JGLA2qfOy0bZ1tTlzWncz8KC OVkGqNRwvGi8mGgsviUyTV+VHTkylCLRNGI9uThMpmMqvcnccZUSF0urELz4Fu+aZbfzWE1baAYy dbwN+XOW0WOfMzOECTzFu8YqYLbZ11qk3dFphSZPwf4i2YNqPX7myrxtMdW4PjXogOZJNpH7hcW+ +6ahV9i4YzGuZm5QZ5/Y0PlrqLc6f9VV0Y1TzOAGA+CIl5YQHsDCu9iKZdgDggQqHyOs2lRNPb2u GpcoF+olUZ8RBwI04KfsDbXww7+KgE+H0hQm3MTehPkY6cWOjjiPquJ6anWpr1MKcLCcYrxwn43l ctEAW0Du9own2nUC+tvOKUl+1HXBMIujg9LN5WEo6pSJypGMf/FFkUNezRtUqrOlVVv76szvmkw1 kvrP0EOumbxhH0x6zAqHJXgjtfY7BJ02m8IV3M/+hBNGUzX0+XunHe2F/+/Z186EAUWRHg7VE6tb gTv7fhTk/72nCjYv3O+xPyM3SAtAWyNhtJVzTg5DkS2sF5wJ0Ap4ooubOFE5Z9g9ifZk+eYkRjXk a2iuh/fFjAMFmxQ4RFap5Imsd1sCjUhNLH0773/KYwttPorp5AeAc6x8pfXzMAP3+JpT+vUAEPk/ yIG/JD4ylYLc7TU84Yr+GhCZQc6qEuufx+CdO3ig7bmHmBI2Prol/fojoj3+Gp4HNtXfQTa/vQLx IeIJeM9CfWX4y5640Zl6sTdD3dVMhlBupL+OYVU2z/YQcAsStmk1ve5Qm9prqRc/K1G8gdu0b9P7 SHUD0QXmDu4EUuKq/+LcN0QEVEAZpwvcNvzTDySecCf+5UpjB8Rj8FLZsfalYiDZr4/cneZkQkiZ R1VuU7Ra6+TRWFjSG7T45+uxsiokVnBYzvYe8NoMn9cTINC+X0LUyGvflETH0n72pCI1JCRwyPv6 w8iOQzPhNSS44eeBY2GhDnh1AtaW0o+kHH6NS2N9lHhrpsIwLlUh85VZEOmWuHiZPU3jKQDcfcHl So4c4+w0CYSlcOLeTtWWB4yazW7dM3s548TxxruaSYVI8OaAcXaaVbGOfLXmz4uMR+AJkE/lxTLV jnlJkUwyGfjVzGbHDTQ7LfB7VGdzamsCxciyl8igEOmPvU2ZiYyI8rhhLlzixUjqBWPPBFPnBAGI Gbdk2kZ69SliJDrFE/+tgy3vRDldsqRenIsjNBO3L+S16TSvddXJkUiM42EQbgl2aDG600bmCHNm ueC0oQICw0qRnBhIy2zwQqTX33NQP6qzZdZUxBrvSc4JmT01514vYpm2BVXTlF/bUKjfMgvZlh+J VlPWysyBlpn1u5rhK3gPm0uh8qYiAVUUdJQO2wG+xEkEWKnRU7RBMvwk1boQdcvL/pQzv0qBw3Wk h87BkbZyvWoktsx2diY2tA0w3ZuWv4DM08L0qCQkrYr3g9Lhe5kBf9QAv3Sg06RgYt3ZOQWNCiMj LzBKG7+k0bbRZ8QI1no6AzgMj9AkzVbi22z2JGuJiqfeq2BHXjVu9ndd/uafcjyWjoUexPaEsQBW +L/bS822p1Wsbfqvo6Kpf9JkyDM7GTZCvdUDF4CKeSP5usd8PV7Wye3EdFrMPc2bEyaS94PDJ9Nr ir+b0rVvlpHHn2oMuLlm2fkVMvUVa4m4BVKbrqbXhvuAjd/kp6MR84nKeXDNk8sN2wVzw+cZcUiv KY4y++0pPGqV/3lk7wUWramQJr7fQuXrRvtB5HGc6PhzQIwHNbvp/+9thl6wQ8TH1wCRplrSGCqg VUeo++Jf01tldYGWsCnaTGvn0k7GNw76hE2Lx5WC07scRxjKexcdI1w2Xb/tG7WPPT/4Do/n27jI GpTyOOQgq9xUZHAi+BtyeDCl1euIOKVC71yLX+As6qnIk0s1FZTm3xeyoLDibLXJ96Dq+/x+JUKb W6ys6JDDfBZ6LIqaKP0UznNZZY5M2b79J/6W3vNfZghIlKrAbbBJJju2+8JpOICnluaJhAsscTVC YI4SfYGLuQLzU74214GPwfclYPTFZaep1dU3MjcilzNcQZc4kFq8Vjp/uPBAe7m+zW6wDI6uiIHc PqK1pIxjNRdpNSTbZyoSxV+SPTMVk9QBYD6D28Fi5Lc1UTAkVNPqOxn421HXiIPjn6mR/tKVy21m xAhFdU9EHz2CnUchAz411pX8amXHO9iDziRsemgXmg4CwbKPb4XVE92VU8VM0vIdhXkMJMC7Sg+x ST3YsxJjgc04Pqq8F6rbYlTwUazNspfO/zF45Lg6Bx+n1HxcUss2cxZ/Cv2+m90FkZEDqILNV/y0 IJ/5t1uYV8RE1wBdbKY/qvIUO5MZ/oBdV6acBjExXXSjDfAyYby639HYefK5OoOVk9mq5atwBl4q odS4y2AdH84VTHZa9jt6ThWmKELDqIXvkORhP7l1zCt2vC5bCh4Lg565FwxEsu+BAYbz7rGKf0qW C/IdwAIEc8iJsGUtv8YmE6Ddnf4lLOOI12CtJGLknO3/FahCRw+2FqffG40gm6RH3qpcrmnRx++Z zKC7i2T4i0Yf/6uKDtpHN0HgfHIgrwqaPGiJNa60iMpgZRrAeI06jzNLJ+052ZNwYwzaeIfukrJZ Eu/uIhLJYI0cFNGbq6SoietaKQYischNpFXI+9vEiUZ1uUtOVC3x0m3o6Af+KAPZgAzv5Cpg00cq gNq2Ewg/uKsy6OpiRt1pvd5I46OoaAt43cKof05ILzquq2BlfMkERw4YLPqEmRTFnqW+1zt/5wgV OS+HCIB80fVr6blX7dR09TBpu7wpGjN/TEOrRkkyVsnfTy/bBkqQkaQQf/LIvlftOPr6uWjMmyoK 0VaWXSdH8OoBWyaOC4WxvH9lTq9EaWoB9dt8q37VCcUh1z+vDYbboY27niIVa95IwcSh2LAQ+5OW 39U4FQVND9PA3zXbQQL28r03pZ7CSrF7N8O3tkMzgC/D5t+b6tmxr/ay1iU+LQoQBALR1Ybxqc/r ANpMvTz7RhAoolu0Vd9AoBbZpwLNks4ZI96dM1lwctU0c4nAP8dDgKeVBKkopUSIE8bRCJn9yb/0 j0I6Qomm2GrjNXpSNO9/7QLtgIepK3LYWVHFwj7FbRAjxu70V3n6mGI9QkHDHaOOQnAJm5bcdrKD xcpKGSq6Qb/AFmfIpj1uivh3xNJFh5/OxFAUWmiy7+Ru/57DIQ+N6nd8UlfybuT/e8TM7T/O30ie BoovgQJMQyWhjJuDRRcwf3vEHtFf2TG5u2Y0i/s1QBiVB6KQexI4xyDd3PPIwD3PpIgmyyQF3Pxh HalICmef3ax8PvIoS91p2p+J5KaYHxMlIiDsnNxCW+GHimtRceUqxmseY/PGtw0q1unKX9px87x+ EYqHoYkUoGc3VB88dJQ4nvEtQK4x3qiEZ1xQP7kom+z5q9R93GoE778lg25+dtSkXhxgINIFwIVM suXN64UDDoMNWiLdG9UPTUXirdRLTQfYb0E8t79gYvTo4qhiEj+MrW4z2xI4VRBx/m52NH+CbDIR 1oBACyVlXMkvEh9Cy2Yn3T1Co7Vupvu/JvsMaVLDCudvU427f5hrutirkwcLEvp5vRZleFHV9e5j ABQwYq6Exe+PqnmVKFAq+Q1aeU1Wrd6IuSiSXh5vA2G3wl7t3Xusc2kvFDYq/k4P3T+6xolfXfUr PtVMa/WSVPuyeNOxBnU5F6FtuNF4C4zUbZ3bUqqzgwiFGnckf9gE7W4JntBRYGCzQYT4CSRJdi+w 1g8nCmNINEJOxGPApJWkzNvD/QnPyjLON7QLezG46frcrlvJwid5nqM69fMcBrzc9yqPSuU7SAJf 4gRIjPBfmRak28B8o574hcSFUb/6Igb17C20+4v1/5v1OuV5nES5FQmrRf32MrRqPORYe6K8C0ud QXFv6oIv2Niozd2/VrvC1XfBNcbOcWWOVB7rlsiGRZMG/Dl42xmnR4xBce7shXG6xnQviyKGdlCn WSSdcx+owKPEoswBEanrZ9TUvrSS3SQVgLigMA2bzOA3d4lqSzzUtoYg7JwTqR5uGv1X2F9WHoe+ IaCVOEyuiQHtQpP5x7Y2fLFW/2S0U3kcmD+r/5+VpI8LVZM+AcVpBg62aQG608oKWQ4dskEZfg8H 6OnCQOTSHXHjIAZXe9MRpTct0/l8GWa86BLm2Hof5qCR9lI4YE8ynh+Xl+YfJLMmKxYsKjHzpUUC orAhk2GHX7QhY8Yd30mt/Z4CGF3kiG1XQClP5OF15m/V98Pui9rtkOt3/d4YBPE68AGtKxpF4kWZ Ti9DWX71272YZ+SqlHqfofUB08HbDMElHKZG9QriULJeKpNbiAeCOrHD+vDVLXskiQATg8mrlePu b2dY449YZNwSrp6++9LX1/dbYIptuDhUWzmPIjTfVtrmvmsmIczE5oOHEaOfQGzR4U108Yjw8Cpg 1S1RTD3T5/VPPFOZgSXhgaQ4vTGdTrt/pmZkkhlp8mMsTX7JhdjewK5jEakCcv1qJ+x1rFMq+SGz eIczpdy2DODcqow/0KwctP9Oro8S1pc8EPRVYMkHK9ZHCzuVqHXIi+uESEwujmyEJ/LYPFG94Wok K80zi41Ji5GtFyu7oqkN0FiFtKgNk73/hkU7vF1KzcgSTcgODHs1nFW9pe7VG7lZzltYaKahMUHC XgEHWq5qbEcXftuMHcB56JUJP5pq4YOW3Q9iR2/kSWRF7pUaXrGL2B0xuYB96rGBNbjogmo/XKMw 5NSeG4iME0PlOej7vmAYj2ypesaKVgmt2KUVchmeM1TLtBhaupUWLV5BzYGXS8X2FzZslBGEGB+2 ac0vHY94Ruw3TeSqjz9/g90fTMMszjtX8cW/ee02COnhHCp6b2DjXbOGjAJfW/+U2Ci4FnposHe7 VGqgXT6C4YU3L22pc467hWpW6jyXr5/Zac1yT/imoKfGaqTxwp4kfRlMpE4Uga2ECUP2BxMxDiAf 0MWgqIA11MwYiprgPhCBESGibVarCKAA9yJcF+K/KU+Ody9tydiXn0Ys4nHJcZ28P/NNTzEtEpNO vl3c5qoxdR95xS2eYbDLV3XC/gwvHPa6RR2pzA0i5dBd0Fe2g4Mk2QLgWfXuZdhygH4rXY/fKZwy inODaHI40LP6t/bbpLKsM5BfplN4wDC2B1E28PiP2VENMBiAO7s+U/pV67RY6z+RbFhJ4qdm8F5f KgX30q66iSGEKxeyaTPbJ+DJ9W/LeYXqjKTBOrsgG4rQll6eO7ZGWG6Tnv7A4Gnt0sVj9QNpKUM4 ypPvuCJS+N5oMnOimU7yVHxyqwWqNjaaXl+6NtnXXYXJcMrZTzahBIml9NatqNoV96OpPEG+ambO pfq63/5kGVJJq7+3pDv0MQQVesHFG8BnrsExlzItBscGJr90ROOh/j2gVdgj8Lb5RGk3oDriOHJp a+HdtLpftgELBOrpyHLiTyo/mKgrG0S/a1e2pMhadWpgW0LcNxd8yl3WqDpmdNgHxJ9W+KgzC4oR o2PGjmW8Uw637fVikGHknoiuvdn+s68+zfBIztbpb2xr5kbS73zhQV1knHixT5in1t6fnhJ4mwpQ Kjo08L0mvRQu73ha/1RTPSpBbNlf8S38q4KqV+LYcqA+rJnjBgXzPeSKRug04TaHb1BaskoIF/+a hUg0NckWpywEY1uhpmr4HiL1tYek7QPMgz2nQiky7nreEzen/P0ZG8fhCQnAiE7QidFZA4f5Hn7x /e52rLoByEF9mIYiRgy4Qic2fqAbbJ/2oOwygEgf70eg4AKP3zIEb2Dh/dVj5B+rb5Ir8c1vIXsg JDJp7XHtthZXMVuXVgtI7eOA4PsGpqCui/rn5toOMstSPHAv3Sps2/TLfST4VcxPW8YeNqynG1oB /p0oTqZJoSh3Hoj8GdXqwqiWm0Iu2p+JnNHOkCEf6c8jFfRkq8BUyRAFQoU1wjT2yj7mwpOB6ZBE KTPi8aKrQwrI4J9uJhGVzQ4RfK13QyBvSatEF0RP1avcykHnCjJ2+/9ujZ1mAFYjFTLnPf5hUGjS qPginKpEPrSuwTB0djnTZvMRpKf0rbjws13SrDiXFbwL5Teg4fJoL+RkNfdX7IC1UW90oqPcx4ud 4i1PDsyOS7ArHzhel6U/nHFDu6fiLGfa3Sw0/wwGJTp0xRdFKlrjs6LOvcOjCQTc6f4kPd4Zg68h V8C7QJRGDi+t7r7AGGyfTiFIyYwtUoQjEZ6fvqNs6Qzztjb72zko8RuJZnj/w9FctjJjPWObkVA8 WfZ70/nNDr+ic9cFWmvFZ6e6U0TWeVmkVRrk7iZ3pCzSTGmAOtZdDTsyBphiGz1WdkX9Bl5IrZYg 3nw91weCm1UtOTe8y8deDRrRckFDfsqlpenKTPun8mYqgsLb6TK9r/xsksBciAkPkhbXAYfIEytZ cQRZhveYxHR4HcPLwmdOKC61ZgJjYpwFPC1y77dyfwuBBcyYGeZZawL3xbZbagoSoZftBTxXVYOH 2lRIEdoL9r/zfDMXe9pTu/28UUELrPDxmV8gsCg1T4ATg2xo5DNLyE6JMaRemIdzzBIVutgJv0Qh 1OJR2+1lASwMx7YtcAqdINQur9xIvKCr390Bg7KCcJo5KRZeD3Y9hUjNnt5TZAFdVe2FTFUtvaZh 5/wzJ0bFlGA1F4HEBuvmbjrUDKO4IbGryaC2wphzrZ4U00ttG2/kLFexiNfS2fKao4kc842ylvSI 38lhbiwjaB35zvZ6EjafGtC/q7lq/HPJVtacsKoXdSFu+cz3/M9Rhbcr3er0ztDEH9zPpXNU0hRs EkZej2RG5zJIlfWFWb7eOydEHMBQXs5O1febvB8evxDOD2FTSCoKDkOfKAz8+e2hb3O0LABAxzf1 xDOjp465REvmt/TM5n8ZQ07JWfWkYKGuLe1tkuVls5RA1vvgSK0AO4f2pB6ja2z8E3M1EQSzPy6K Rj4JnOU7f+V3Vsxd/YICTDClD1/u5svVtUcZ//nHQTDExLMf3jQ0OyD+B7k6ETg5C6HEkRUfkNp9 B3YjlvjX+RzSmCMc9Oqurw1uJ3e2YBXgNL8BwsRI4uW5Mb8qh3rI3tvWvL8mEr3Vn3iItcxNH4J5 ecCsNvey1YPxIH/FbQ4QasJdgO4HfxnhNW/M1+YHAcJbkDAZvfGlC6BeBV7PFImOJ8d97mU3ASbh OJLnVuIDfWCwsR1qw05Y5GLWAyFPFJVqhvBbc0+xEoYpu41qK93+NWIHCLibNCjuQzHszVfKQthm 0Gbnjm0pO9tE0AkFj2cJzud3/KMU9S3Z6frF4maXYlWhFWDikmvOndH66vSqUsFNbr6djjo3V5X5 5lIJJndOYQMPbRbMbWihl4iq8tSvXM49Dyndm1Xk3Ool5Tvyq8s+ma1f27PJkwEm3g/KYQy8+Xjh JbhVV+I+/Alp20jDswffep829GgKtT7xs7pOiAMBaUkpOfecO+DreqMCRQwSTl6TpU5pV8OaN6mA b+XVHORvN634HmoBEzBe/ugv2QNvpJzehktR3QmVXvZ51eatefRW3mF8kGY06xpzy101Wtz6s/3r yz17HHo+XGlYU0s1Z6ESrIJNicYX+XtQ+KH+Zotl0pWg4Hf0TlDKakRoQ8RuL0DAVQHvXefFqX79 ui9e4sXJ/uZoyHpBAqtjDm3tHExgY4uXluI9xi252ccjIRO7xABzvpTzEOJbSmH0UPB0l+ccQyt4 qkyZvzeSIObaOHhYlEunaE5DNSrXRMOXebE/pyu3RFa5b74/u+SPkgL3Z5Vmgyh9voKz4jD4mVWz +HSqhHQxlXISpEZvFuyIznm+0p849OK5BkA0qWuxkLFhE/ELVQm1bqs+hKpu9ofkOH63y3f/nwbt ajMldAGN9oSatW8LRoLklfCUEP77TK12fw83R9k+iH6sJD3NPIXnEHYaR3mUIo0Faw93vCFcC/UG GjcvXPHAGsxEjhly9TlAxTJgD/MB6YBVeU6zNEnAHmoiRFrRqxeiengiYPC8WO3Gvs+RbE3o+lx6 Ojz7nYaIxWc/+NE2XhbyLw7XkjPHD8iYfSpe2ZFee4++yDfdxI44k5DtfzZ9fTYvV2BJB8h8fDMc VVw51lT86sWCp3rnKhGGetSG3FoGoH+F25vmW9nx0uWCoT6KQZNjNd4kCrCrLdH0237OXdMpSVSM 2hHN7LwOG2f8GkdusPNHpaXBpjN9q4p4j9DnugCXHt9EsiLIpG/YLGwYugA0WNIHHkkX+XDUEpo5 gOZ/Zo5o4utIChqtmHmG0wq4dD8jfVg5sY9p4bXBDe8MwadrPIElnNJuiHcenWoRiCciWqOy2Yr8 NV6DZX4bPPkXQzD30Q7OpXU5etS/UZRFJj69+eZUaJN2PnnPe47vjdj/UcVap935VHu1xM8LX12c uWJvkCiVCXJwtqEBtaWJPx9stj/PXafdbp+ayKyR+va+97funrFbc4fXtwuKl+4j74OU1AReWwuZ cWLEJ9Yk4DjyCfdj3ncrcnCcqlmgZLx91cNsmknXm4yi0P2NV2Yz0oXwGf3yhT1Ga6TJudLJ3mde Fh5FcmilHTyz5j1XsPy2ZrCLS60V/X6zbsAEdfvhQIo5SDlve0VUHP449ZRKkVEtgYwMWFp++igT 2cP4E+tIppnveIDvcpsdgi8K2bNAXe3dNcaCfTc4B7wyDaC6qklzYOodAV0nv1qI0FqeOsiVj/jL keXTKWDl+yHka3ZSzFnssjE1zhEp5aMuVla+0PqUuh06k718LJbArlyWx7/7D+G9trV2Ag3qJ+QR cZ2O9V9vrSxlCLt1MAZMJzOjwCSnqUJqAdnhyEunUyD85bAjkT7sntUYvT3nj63B1o8eGjzG9p9U HfBqwwFmuOfdj44pL1ZlpF5DTfjVM7zqllZTfF+x7U7JLWkoAR8DIczSOHMl09CTcgqZqIb2HnoG bvLUPz4df2c+lVrEVS/yRZMZWY2R1uLuC61qfruKvfPCoT7cMGM9Ig8+3q9eqA+R//c4E1huWO+k cW2X5sGi3c3Ogwwpo1o+16kNYzQ8ixc3pRj84FlMym46avIbxA3FTrPKWl9summJu0ml6Bwv09G2 jnmWeHwGVHTr+ZsVOnbP6TBF7XbHme+kRoOCNfgDPpQz3nulbZugIc3C9flfIe2F+cj1pofw9jTV ot6OF2m3Gu7uFDnBMj5Wo8osKoykyCF11JFCqrGp/0y7iQVl8osd/bqI1fPJd3ug9fd2pWwI540y FITmLBFdQO3DDeTgHKVvecBGtU/yrEzeRUrQECKTJoS5badkPwyfCuxXIjDT8g+pG0wdRyh6c2dJ 68huE7zchKal9gN2xvwk+9LMTaRytzmslBCGjF3XpjI4zdviLGwthkiohk28ngPql8AD2NVYsyYz etNYzhb9gJQuyM6iONtVhFxrsutA1D8R98YS1NASSCtz0SY2xl0Er4Lznr5Pek28akmiMn4SIiuM 2CTPpsWXQfZnvUIy6Xjgpl8gSoBfryUjboD06NRn6uloPHnObMWfWQpBY4yuUvBnjRLVv+20QzBZ 3WC1kVYfgn6PAe8tacJoq6ogB/e4Y+QgXRhV4YyfxdSwBu0Z4pONsPasMem+xXu6nhE7wxLWuAML M/c2up+TR9dMPsqBCtCRNhm1uu2eDSoe9NCwmoXvv4r5JE8/xi1SEdIJCSo3tDUIc+8RGXPgaknj UMn4stRN5LxmHsukDa0TOHwHqr/3HhBEsmiNjv9zWCtVsAiTqsjR5llqn67NxHJHaOia42PLCRMC N6dmton9Xa/ZFhyyXgMZfoQZbgyQ1Fpc3Mgp+nmgQ5/m8dMwKn9dC2TuClgCvH6+7tlczkdFW/eJ HINHmQqXBEaC8FXvKsba6Cri2yOnuVgvLI7dBd6EACQiVMYce7Nf/M00KOdQqE2pQltC+6/5WB35 TQbGVmwXGWYkR8uDPlNa33szZe2uytsgnlvwQ9kLVJTXtKTpPNRTjZs5F9SXFlF3YV1UJtSoSydt LrrJxMaGmmrkeFFe4NboKj7mxf3JiP9wXOl4IieLBN5HZ1j5akHKlFdakUWJJV3NpwcFPV2kC3ng dfRWcPiNxzKVorqGXn4BHizj/dPWQuLLL9twekJQMAlxzQZeTPv6naUvdjSh2x++Ivkb5xww1EIA Y+367qnJ9OGCP2kthdv0dTaaNyttzyTc3jV9F4WjEFqjBANS7ur0NmgxxpeanYsPJc/A/NF8504G eiiEZDeSAmiKfWzZ3lJj07KQXu/k0tRKYAOzJHJVhviutOBYx1nczJotq3EvfPEWspOvIdairjVA YeSfMJ1PWfBMYQ2WvpfuU48no5W2cUnOqrNdAjIq/IY0KwO4hsY/PP++IQK+7NuB3Z7VOT7dhovo uVAB7rpZmftCl43EcenUErDnEp+ALYZV6LfMNEtkqW92Jxq1AuGqjujRmbjdhsOGLZBhZdgJwSbl ilxVwLcEJ98/hqUPwt7iZffiM8qKSoV5CQGXkAQQKE9+OK0/Jq3s4bj53spH+a0MKR/O2TnFLgGO ghm1I9kedlm/KRdwCTAKUfL99w250s2gyDiED76o63bcQjgC/oYX52O/Y6dCDUQA8hclSqVzH6Il slqOPDw7a4k96jmilPKl9SFVKbHCAqGMjR+APEQqXn3dNRcCQ4ti3q6txi6aKZNhVayHL8Ht+0AQ 2BnvsFVWgSNU4UWU9/4Ow+1b50xrQ1g0vuAZchrvBApB2p3b05Ee6B1uHQS0H816aIO1gWTqjjql WV2qLP2Aun1Uyu+MsyaknwOFd/XOuINhdWfOQ27Rhn6t8l9ImO09g+wUDHKEgndcZN+0Y+pKY3Yq o+8hYqi/De8DMXnINLlJAUUs1HYo15yonnhEGG5wsZm4Il2RZpnyDDgwqvon9SHFRS6X6NRU5qkV a6iINN2NNAEegxdFUXiFyYS3TVX9KVyIg2SiqVhHl/x1VMxlQDs8h1jY8BkOdECZGe6BtIh7qOPT HQPrQFegAnuotsyLLw9p5qrq/OIKy8OOYycrig7Apt+jAhhtBEwl1dgPEp4CrWYnInCGwhu8aGLs /nS10lrFb0OIPcExTxwECGTLNC3EPgj7iMe4/8IEcJaZY/djvkmLWpVM7rzq7TWm4mdbzJU5KOnk nCRccF2qUVZNIdiUg0Sy8y6aCMcHzjObpxBRsuQrKmKD522K+ouwArez9wWojAQprt1RipUcOWeY qqwu2GG50I2A9NOUZklXuapjMy6oK2pIaEc2juk4LAxkk8Yk2i0mOVgJZP7NN7xKURdnBzMqAh2r sRs4aG7r7WCPyMAE6HtW518KTNnh41RfsviM/3mKDnpEfzlHSGDHz1EJ3GJjdmNPjLJxVfh7srrL XnDgnp8882b7Qra0ORIY3CotIXn5FgHrFk4fyXbUToKaEYqXj2bFwOdqPWQfKPfvGTr6i8cNzSqy i3LrkGZAPhtI/HqA2Ar4cIs3iB5YAI4PStBXS0xFYdOt/+am26S8jioujmqfQAkiCTULzI91ofXO 6Eeag62cXZE0ckB+NWGWVNKEMwNez5YdNvzJuBNIaQWaNK6VGx+o1pc0QH5VcP7j9uHeXkYDBV7H Ueg02NodAAfYT748GtpRKJvacINnco6FXpgXMlEK7/EfEDGtbNmkBTp0bnzb7jgwDFuFsJwSbFo3 rXHlJ7iXDKNOzYwpAYtk1p1RADHOOhNQBaFwR16v0c3n6Soi1A5x55Dwh04AfezIQF5lvbNIQ8q2 lPAfuRXew8/U/D56UoVrejt9hqmM2RJ9WjY/aD2B0PA2M9JBr9I90zgtxwxYkRPXGqQw7ZVt2PJr mz/VBocfc+SWQrmM0Vtyixh7fT1x2lfKoFVWSMCwAyg0K8hk6MlMtpSc3dicOJ7d2H7UMrvt6xOi B6b/1+PSTfVvzmOYEJTDUARkDsU7IpauX2PGyrl8PGca7JL4mxU6gj0KWUhkOyFxzesMQMZvBkcM 1iV70EctwEEjlnkzD1BgYMv/UEfuLGb3DCvRtWnPbJ4JQfcOJ9jALSGZX6HeJIjan0wvpMRqfm4j gEmTuBBqj43DSSd7D66kXj8JN9fMu6DRAAvrwihyxHvmAos6Ih5B4xrbhB02fHIySyb7qTG+N6B2 Qd5TNLHhPhaw17J6TfZEfZN6+t8doSOHKyX5zZQUlorT14H37pIrEas2m5HE5klPatb82q3q9LFc 5bNbUA83oUNcsgfRRVtuVt/0b6KyAYDLv0Y8OVQLLlneD9IfSgwc61lXetslHmzuvT8vxUIuJEei hl6yMiD7v0UMbgv3tAfg+Df3+SXHMMWAXCmmUni7mML0U65eM16pRf5/0f0WH3GrBRp6cCKVrdFA WG9LWJljXCgx4wU7PFG8K+V8A1su1P30FTiTUoc9irNI+UYYEjczCsl2hkV9rugEmvwjpgTiOYHn 3G5d/cPm3i6kxl7/HGoZ49yEE5VKV3pNCZsaEPZSgU7HBkD9LVgi1wG/0Fl2HacX0uzdy2RalF9N 2YMFV76pF8KzRnBGR21mksSvQFYA1E+CHqyMhbqs4g9L9sGf6dNhT6w5Kry3WK7o9nFIWZkrvFVd Q84JjZappujKp47wZKsvpSEiCVJCKshgGIDnJdJA0rZ9VPVykUmbZcfv0owaufYXZ+i47aCZNVmq E6mO0uk60wwRy+EqfN1bcmGbPBPcUZIqsA1BvzaLaL5HSzHI9nDQzYMmEc+U4PYXjCiezYPvDSUz aFeTMq1YFRf6TyZZoc8Zvg/1baeKZNqUMHPDM2g28aVfeLv0MQnM1Lm/B9kCFrzn4hwzhGnLpx81 5dU84Pa/oPaeYTeP4M1dThB7UxFnpOw2JQXA29iMOrMLze3HOw1MwZGSGNnB0UYZFk5jiYELTTb3 hams1WKS6BZqRdivLfJZkLOkQp3r6spY+2qllRO9QRHVMawsertoBGueSchgp6hPLHs0JKJ92iF8 gd2ogcV6lgyPmigAo3KgKc+hjFocyEn0F9LUJozs1Ob44v9KMAgziCQ0jlyfbpoU13M8DPM0/Nlm vptAi2sVXhYKgYAm36IVl497hS6rK6I1Kwsc3zJq+VLzzNeOInOHLjmj66Du1/5NdHo+sS56GcpM rt2Gtx7hX2J7xWtVOBFIjoEME2E4PpssYeXikdG+DknxoDE/jo52f4iSbtmSJnC+sf0j6fsAa/60 I/U01rpvi/MNPrZ/jzprEW4SzaxIBmVXgmPL1+pru6Yiqu1SKdWw8Q1+53sdMXyHE5cckIoQHqpH 4snldpEOghM6r9kOcyC5NYcF4mpIWKvxxtR3/tYoi5W5EOWbgxy38CdMS6/bHP/TM0NWp00WHqe0 63BVp7ixzuMdxf+UFCksmraJkIW8jiKsx26dfDkiP/SSI6fPKnN6iwbXH6AtV6HNctxdXB5VZv4B 4wD/eUmUBXgE+kYHtrhTkhCnvLSfnlLRrFFY9Am2aCrEFtc4p6AxEgRgvcV25tZi/13A7Em0zT1G G6yQ3vB8eCgLqgdwiEAQ7IC7GTV86IhTDTCd6oIDbqvERo8Hbd5WvvslHlp8tfMBUnd/1/ZQCBB4 YCh8mRRzroK3D2WDY4V3ZbvPIOxzRzlZYANSMvZMhaH+jruHPTw9oGoikJX5+T2fKZ+H1PKb0+Zl wwN02TgtbD+8w1+tBZuROmBbPV4RTr1aLWm0Qr3lTk/61NDKCY0lbrUPfV3J6dVjWin/6DrSBH84 MbjwGtD4ISnhIEoZOIQCxvm4Zo1P/yBPgHm+r6Id7zxBEX4isBxR8rMqv+kbxz4xnDyXsW1/zQmD ECe4LsL5LtSNllf/iIixiR5U8NGpQo2hVH1evfqtDMTZi0yAXwHuD/1rcpslilsY1lraeQeMvyqT SoxgUystryenagV8y7R/T0C0IUArLjDc7ptA6Kwqr77jspBxqju39ATy78QVJl9pt2y/3LjqdFI7 WkrK2cUgjYy35qFxrvaLEiZY5T657Ts2SvAaLGhN2yjQNrwtr7QnHRc3FEDgXGjFQSFZ3NpQHTvU bn+v2KuoTFnXNVaxVntz/7KcxcbrvTSGJGsPr5bQhtbWN8SjJGE+Ta+r5P3IxJ7aPvfyYj9c40x0 41gAFMlLRG60K+xpd3UNb7pTrJec4tzWonWPup+VnX9EZgDZ3N5Z2V2PHVFChivxr9rsPWp8BVeO HWA5a4ayr5V/rDOpKCpX7aUBc/e1iz6ed2rIpuAQwOgC0BPpYDnHXqjnDLtlQdrwqWIe0Y613mYN qpd52ulDdtlt4xZQ1mX/+DASZu4VCq4ZgtFtAoDgpX13n1gnY+Q8x8lcDp506Jo49Z1aerkfNAsg +LEueBPjtlYBjDwgFsMQV0vh6//VK2OVoKAifQpY3Ii0IO/XnNtsKdVBK5nE6H/8xXojvffGp865 VEDygrln6QtejLOza1TjSk9nAq3+0YO9V+kq881MsI/74GtAWZ3X/v7i80XHekyMQ/0FquRdR4Ri 997lLusPsiHrIzxvqqCGjVvuvUUi4faGlo3tWqmqxYxvdidbAKDlkwKpn6liNMXP17/C6V4HyK9l uR5Eq4xMWPu4zlJGKC5DUPw6DbfvOG4gyMqagz3Si4LgMFCmQw92vwLP5unctWkB/Pvj2YavRyUv EGUq53fwjK8YrT25BzPhAKi5j9O3oPrV/Fp8vRQaPYrLIkwTX8259oMMLgDprypZ4WHf6yo8ODgi ivB+qBHQz+R4B3jWyj2tTNVcXWWT43lDvrQGsoaMyueAVY06QWr/qJTsnBCbmCFNqRBz7DbJpUk0 OCEECz92sUfLmwIbY/BCLKUGZiqOu5G8LbpUMIO5JnE9FcA/XeFH0P1v242GIJ9YmPSp3+DWaHF5 8VmT3APPRUVU+5KYsEeLAhnF7Kqlwo7n8Qs1bV2uwfftI1tTDxayLDbMhUhTlH1Wyg5rL2kvj1PZ xktFEY0nmVG5YeQX/RAB5OEVY7Z82A6zLDC5a8Pxi3Ts2FPJhSdJAhYQAjbz37yL0a+EoKKqxUFV r+8CddZzs87oNQv/bo4DX/oELR4gUjk0IdIEQGapEIhDJrXi79F44ZID02eY9+ZPd+fBv+SedQ32 5fYoKBi79c2aHSXbLsnJyN4rz/1FkZNbefl4aelbGHxQxUE/EcOu58u4yzlbZmni5qT20QHt3VfB DvKS94GuGLTwa3DYrhJ00ketJmyD9lN43Aeb1WKpOSWNOF04cYRKhWTVaW5fgyaHd8BmkqfFuUp3 tBnnggb/5fyTldbVeXL3V9litw7HBbN8YSZdI5nUG2xe5xlYiNzAvnsZpClmQ4wdPMe1GbiNP5mQ kZomvAOBcFtkC2ZdOELhvOsJmzDnAM8h5SwHnRnR1Am1SBCSF+IXU2fdN1lIzRjfi8Q8Quf64IG+ uiiE4XVScY3BndjzGLSKiw9s3zkzxpgQk3YShVHfomj7u+dMfd+lMVDH4n9sQmrh4Z5c/r+4BSu8 75UiTwfTN1/h9AgJvEsiiHw0f5Q5v2vvqfUIbna05t/QTMyEAc/AfD4aKB6L++HP0qBCI/bbGmI8 vGQzkVNjPlhq3/WPRgWjgHmEOfSNvVRYOreBvHvFkyYzM6w943EkA64gs8UoX6WnYs4ByIa1KEi1 Nepr6B1zQohiy87g9vjgzec94mEW0gLkLY+mnsXp7Qif8/dwoADKdXkmopDtvkCnOm/2Lwqm2S7H rjt34CctCTIMSq+Jrnq0/a+PMj99PKpNzG8P606oOPuEX8P4ebekOl5SwgWiOpGkv7okWmU2XC78 e0gv+cbnmLSOtYpF9D8UDibtLbfd6g4aawowksIUyTuNrqfFb8LgneJwZMVsnwEFVCNxxIOfP0/O cxzHCgQM7LIupqvxX6msAT4HhXYWLjrUEQDQIIItxTEVBf7IzMRr8/nCOujXAks3+lqjA8mcJOFM E0ZeZ1vjXbCVMZblg+vtM/I4zKfDqVM8/JA7JpfHngtPsHeuO3pITPJiFFJ5IBBmr15bQXswzq4w MjZIMNW40i58xuXDeSpeCUND+mQZ5rhbuvgfHBUONq72bKdDfcAl0uxqqkeFhSp4Na7tw8s/VGmG bBI9SHM5aQPsIQ4IuZuQx1S8SO5Kml6wj6mo3q7ycFpp2WdawDFzYfGm5H8tMDCuhMeHQkBrHS+j pMDJda9ZpcNVMAHGjwONBgYO6C0laQqcpi2MqpTBKL1sCyy1UJ31AKPzmCzxHRJ56dcyTO1/nstx sn6P6dwu6yfy+lt06DneOTc6LyTq1/7PZLLF089fVWOf0WBc+AGliQmGyUsARfENZe41Uzz5v6Zd mhPsCwGqq5xCxSq6DOk8cimvkQjtKl2yh2uD0wmxEIPZKAE/F5EHjU39iqtcxHoAnFAGspln0OOm AISgLOFCAgSq/ABM9JkQI34IV6/PShPzRDn3HZjin6wnclD1eG4V8Hx98/COHdPS+o/NA55gMCH/ boRgg9kueBlZRCL3MI0lpaeh2yxLGZHW5FZ0SbnbIxam8yW0dWaDEX+D57EcYQTueXWUDSt+Tr2e wUS2ah9YsQAFtHTbESb/IdbHimUSQ/AVpB1bx2EiApxL8d7O2tIEXkhKQsGdaKt14jfHawSm/gem Hu0GYyfHnPxHcdMPABxGPEf6dHGBa6dO5FaJqEVbsNpmH4qyGq5Am7P6zqWJ+kmxC6Sku2RJL+9K k7HpbDNyzbeGLNEBPKzHI2Gx2TSQyouIxwmtqAN7i1uQNX5O4ni9hNkMy0r2OEyY2XmJOwOoPuVs jdoYhzGRaizaPi8u2VmY8SBp5NDLGXrLzklLjrEgZ4DlnHwZgaL+VI5t9KHDA7kStld67CqeNFHV /1y0+Fe8DQxeLsum0MlcPl5tc/KS2aXHvc5+G7EEVr5ZElP1EQGTamsDxrBfzSLOWXSP6xxzVdgL 24MO2SrhZTFFZJckHANdpVYuflODy4WpjY1u5DEd82S0NXoOcjY5kt9Y0o9Fmc9KqrH9NjiZTlu4 Tdjdhumhc3x6/rf5RRfY1XHTb5aDX47Rr3C+ai9ALbDGnAzKx1uj8jVf02iuDsiMitu0EpMB0BND CAg2arauuJj2yOAaas+6YC7JL+YueLOKKhmoeh8+CcLalPq2ndRQVFnIrfD7qJP1DEdQqa72Zrdd vbz/D6V4Zc+3lkpnzo6n54CUhbbiWuTPlvK12T2Vuhe2ABN2FygWFEJpdnxh9FJVvG8udzkwNQZ3 yy2wmccq21k90dk6wdKgHvcGge+bS/2LI63zlYrfQKyd5JxnvHsMcgJToPemyE2/dsQsHHEM4YxK W3BlPdiqREzBodPf8rCaJ3JfmT+nAEih7PZ3OGCs2Wvcdq9pnnjaGNfGObdaDk5/RKnkqJ5StH3E z3pao5st5xMVMxv8wCcAOnNlYzayrRZ6NYuWIQ+9ocVwJraF4gXzs92T+DdVh34a/GY2fBw+SX7q wSlCsfQnTMHgA4wZr+OQrmSKrme1rREcKZ0zac8hAb9moSg85YvSpll9U+CiowFxyCah3Vf4tAFR sJeAK/Mp5e2Lxev7pQsyKeQY6I0YMxMGmULn0vuU5BR7j43XNi30Y4jsAQka3V4bH/4udbQGsHCx xourReGisCBYJPIdml+TYWFVbIPoEgcna9r+73wmv/ddu40DGp7pQqCLIbqlnJfpzlCctFKfgBuc hA4HqzFumy8h5Ke/jTHlWSGhzTJJGRp87Uo84xq9vZFLae8JD26FucLdxr4ocSvfZqKHNhKl3M+V iwfS0kYiSfoOool7NtjWwgu1Hko93PRUxyIlOLoLJYt+JD+Fnqr2XT8PDChalI1QlJ8PCdM10kGK 3o/8c9FMvsmeyohBGzVknJSDUUruo+ZPiooZtfwz6liHYIxg2ox5WCpvCi0jkVND7dy4HBr8iohD PbGJBALV1CbHRUsq9z/ZHJFwFaetm81OrGebeqLH7f0XvCUgT4DeVw2GCEHYjVfONPDWWU7tK6cs NsVsCDg2QQanuKwB4PaD8HObosmjOYD+FL3+PMgujAQqAtN2eI9dl24MaQRxu3Ya8dRdzqIrYapN 0KDcY+1Cu+P8VL5UX2d7bTaKPCTL9NkiqLFotxBG/7vX/QAPGA0OnWCbdcS7BpI3QOcKRpYiMBX6 7foE2OBIszqyyk6T0Oy0QIHWC6I3fJuJnBAfwgkypCBSp2vt23YDpJ01R9tkzMbuDjN7KWy7LS/r X6N342GFcF9caUOnJzqdLbBLlLmN9bNSD7GJ2t/DvX92REYEzBG5otLIPEFw81sHeZ4QZxDBj/Fv xg4NZAD3L3bjDYX3Ucr+biXy2IrrxrqhZeI4J19LhcNoEQ4tI+OpUtaG27Tg5DtBpGCZmHlyFjHO unQDLXw2+riWjpVdWWMwTIJIhYk+uY9KryHdLVPA4AD2SahNd8MqBtNoLvHpov9zJytRX2r/3p5n ZhAUHygpcppYG+kcWyPXpq4uzYgBrGaPQ4L3etRbAXd+e+4wxxjHBo1pwPKKbS7ESc+iX1RHWU9F dS53fEzV/fUxaGPMPb8aieeWhJFgWDMOH1eSkaWhGAas97cq3sY1IuQiQLS5/7bdnPl1/Z80xlVA 1zV62YgVUzZuiFgS8sjPwGYF8w/ZONy0/WJLx7vBXne830k2S3poI4lzffdzMXCQ4eeeR48x3/hC LZbak0MKx9Idi3b9gaLKJZAwZs1aW18NloO7xWZHu9d9wetvv/1nfySu2bOr/RyngVXO5gE+Ie5f UtNCBkJGYKkU7WodNYhs83yRkyrmXnXAY9P5QL+e9ljOxZkSuHxloDSB7z/eatSIK48Hm7bStpWY DFIJPaYKO3YNbAjrSYbe1Ucywe5jEFv7d6GqoSl+aodOPZ/OD6Cgpvd6Vg7+VcWMX8ufhKpjHOUa 3oLCczaldX/AP6o+Xz3P9TJGLQgW5X99azu/WnKq2RimCKoz0ax7NRqw1a+M4KBh37cPZ+/RDNFK 8rbLNjy6VFEFBDmPx7GpOHXACl2HVTjlwAYASi+ScLKypNesNrdV9OxeAwsq8lSQL9nKc05MXAS/ HZQq2Zrek4hxQQS2fP1R5RJONslyhGraCaq8y4wKoxI20/+7VVjmgCflwmv5TN+WSsShYRRElEKd BmMZ3cu9LAKzra/KB9U30SmlD9ZjQ5gYKQxqF4tTp4tyHVejgZXF26YfthxipwAZtI4vBOJi2oKp hBPm3BxlhoysccB73BGiX25ql3yfD34QCH6rSgzq9B4Id+ackiPJb/EFRUBbN5dxfxi8TyoIHuLp 4CxeG6aQmptX0lSKgJIbWvLctdtB/bWcSBHAAIxv9Qst3mP3A2RWDqWtDamCfETSGwyWlVNl/bn7 gddxDGdV5o5YalQ6WtBHoktjHfxdAjZSsqfNAujKONzpgh5zbP9NjhU2iHSTEOcJOPt2BndVUc1D TRY1zuNveqrKGxO6xbyg8ZgpzfxHCw+7zGiPSZQN4ZbkX5VMapaAqLTpEW7mUndsa9lXo5+KB9Iy mktbyH5IArRoX85Wgi2VWbOHzV3UpnXtqWlI8rQvjKRJUtdXBJ3tpRyU0YyrRWhoPAY3adeEzuON pBWUkqCduNQ+ZZ4ZG2xrskGPBfELQI3/iOFrmbYRurGJdERlpQH2X8XzwrvbYE4MNin+xmuM8L4n IlXbdJ1cwwFWwAAoHKgEZOfFIdyyN3OSyRMBeY1XeINxgpyhAaex8VAwixkUvOc/oGk/h02u8U0Z gyqrLm9u8X/Cugp+iBi/Y7ZxY/a1+XgNx1HVwVMmkEag8v0S2FLmECD9JkPHhwdgiZiB3kcVAI7X YTt0+2NXdJoddt12ekEfxxvWm2BMRWya0sf1aWok3JA78SVZ8BNzO2f8n2+ssqVlrYQgxF98gkGg Agv51rmTAdykaFgcuyLyzUaXpZHWLJoj0dIKiGHNsGL1CqLIk2fuO/82H4tlvwv1uks3g2JiWnig X7+N1tNPpPrZMQd4JLfDhIoH5I4r3pa5a2odV+t9OLGifdS7Zq7EoX0b714N4WhivCHfS1LW64/6 VAaST7Z6Yat+6D5u25B1c+ro2Rw9O+l00Ls6m1wtOh0xZQHtTsO4FcVMLoJw5kI2nhwCL/jBTgY0 1861wrUmSr2NAgGwl5Gd7gdQFgo8E/zKbOOJiRVkFzNlEORVNPQDuwBU6NjCv1as3U71Un09lFrL 8OBySGvxRnYBrrPeNw5qZWRLIdHDmSI4qLHwY6Pp7Iicze4G6bp0jt1CFzH/fjgTq2bH/YHDlVao z/9cmQBDwKNybAzqK76heZxqENHPSKvk++uLv4AhmOCRoWvI0PLDhgpioOD/OXS5gmfnTpT2Em/n yc0jN2gW/Q20ClUO8KoXPn7ZK9imMV6FoH8RUfczlrysjxKJ7OnDOVx4Z+TKd0ys4f/HIwNUB+g/ Pi1nxvAjAhsguR7V3e1+TbnxeZS0RP4OcLNCSTYkVN//kLmBa82gD5H5ecdtNCKyk49IL+AvKKRc /eGRHWrmDN/sRO9mN2cpdyGfkqTFg4bTDNJbdG6alnJRHvP0zEt2ifdPrSQSkndTYUv6X9n7QIfU lowzHEulzq6kpkZ0yhS1hcS/CMuR4RtkbBdX262tcc9Pv3ijqhmFONM7+S4CCY30dmiSKsyfyjeN GXj1WFV37EZ3csvt0MRHpHIqMRukQFdNixrhmpGQ2mIHPUeRnVqbJh0TM1YFBeZF4+O8wTShfTYU rTUgRJMW0pwvW3u3jndEBum7lXwnOBI8RTJorkpjjELWzKcd6GO0xrYsUKVTOc5WszFvaLyQAWQ/ sKcqZ1fMWRkzdvoMzkEI+WRvDQoi4YnzH1v3gggC/AkhJrRdrqAYlwQ75tnMLiM7VuSHCRiOsTYM AKMB9+0kjkbNBfi3iUsivPTTQuEJxtLxYXmehoTKWo2mKWTMA5Xn7oDrCJnoN90iqePUqx3oclkG Kad4cEOzmvYM43KvAZVT2cZui4gH0URkSRqfVtJrlEsrze8CaCTnGcQiH8fj5rG9PZ9mhvJKMRNu cND2NeoHMOBJl26CxdhgEaHwdZZLu3lsJp59Rt7QAIje8gprUtFYee162yPompWn1up2zdGwu0WB 7dGazjRASfLjjMM3ATB6SK84c2atrV6/3DLEevjMGtCQ431A0AEWjEY029vzPYlQ7UpMBlU49pe3 O9VPyzemUfqJLLn3HVjns3wdIowA2j3TlsH6kRYbh6TVUBZq1+Y1N9AD0bp1fv4LhdA4CQMp9WuC XgrMf+I3EGhxlmUUj4Gg4HSS0+4Eek9WvuZcyOWUVjdt/JaXA3FOGI0Dnffav6oPC/yUZpWvpoW5 kmxy/vWl0yqDcxRR8TUw+xRrtm31zfiK1xEQG9a57ezJ9Ohtx2FDDXnHpfFB+peD2MqpU/NdgJ8Z WDnjSZdlvwrzs68VZsEcpDHhIclqv3SXv12LKqUzuYiN9qJRKZAP5Amm2dYDsaDwQJZxM8ZkB7uK vjxYG31Oh5xg7ZMUrp6KQ3vV59M5PuRcjMGYj0m8YlydEmeb1NmGXwXk5EKynZntQwpVhM1/oeAQ 15TjIqjvbdxS1Ag+CmVnYVZ2p63kZboOQmYyQZazBH/DJDiRstHhwB7Rq2aLpO4dPy12MhRnIJrR qX67Q772ynJFAl6QZFiSp2y7Xsj5uTsXe8KUlDrrnxyzjnv0OV1BRKalLTtRICeBOMQVqQYpt0oo IPJ2rfVStRQBqRd4KZZQwRGUPvay5+9sTP40CK5pNfH2byMglRMVObUbbo02y5azyqx6Ah6ONl0K qtkM7TYyMYpeJ82AhT8qFevoAI+u88lFWumfzEmqRqEEE9L6YAtkPGKprrAI0VNU+HJ7tOV0DWu3 umHKPt6UL6+KvaTw5xLJ9hjgUIt0GLwtoM6YW1IYhtXqkmutxQtf4hGYO/6NLBrjBZgp60Nx0jUB joTnIO8sFs5BZvN9M6RQCzUhka0bViWpAAxeUkJ41I5QEDkfY4y/NA9v1kDcEGdaoNY/VVaX5qC9 kepUpCg/U0lUStJ1rhIThXfBIciTZ7Mt4fJivDJmlnX2Y8f+BM3rS5T6dcf8194Xup/mFQAQZJOw YVYNe+ntvociNySHHgfEaikUYKYj5Adk+rzua1mZENezH5483xqY+NvnNdNRssuxsuCLDR84WLpV UTXZ9uDjr18bfjtSLncKQTvz3uGxC8TTF6gqZ42BHRBuGf2AMb1No6IG55OvYh/dhWNvwZHAcQKn tW8ceY/C9jS1cwCrBhk+wkquSiNME7QpNbOpwH08q0/JljY7fM9CXeHUx3viJI2ytdye/QteSRgL oRc4tT0eX2Uv9CbnIjMf4ZaNFUEn4NVmz8QrVN6KVN9qDIDfNKU0L8js+YZIuZYBoxW05cPNr/1X 1/SJxjPM00J3ywNm5BrofGpji63NUtC4caZ+Xz3ATZUZAM53zmbRG1wZvW7YLaDc3ruTBKmcXUTo 8/IThMn+7bOctt7pkcwYGXSfcNgDVksKlZ2sIXdbVJ60kfvBOHaet4kJ2BbMmT/2bC4IosL1e/qE 6h4uc9/tDLK3+Tm9afYQovj6y/V3zHSAAinXdDijcuHuF9RWpngysdmUrHkVfKMM23f+mHGIfZFO 1pUkvgyulrGNaT51ieSQilDGQ0A08/5mb140unCYmwI3TsqJMK/Mdm209Lk8Nc0aj02tj4OnyOIG 2JQyVCIUFjAVDSOMzhNaDFi2I3D0hE0/Qf4PXvBIyolbV0+cQ24Tcm6V01gYgjnLFAgqKNgmSwgf BbgCtgGMvP+lug6QFD0N452EllVJeyhZc9li0diFlSJ8BW0IKFdb5ks1h9Hu0AFcdRuLVi9MErYS mUQL4+/+Qoo7WwqMMGDEDzTb6q3ZtbjERVjjMZWNUv2RXoc9AuRtrTjLXmLNAD6NCg+pnE2hYTGa RDWMnwU4z8agy1ki9y/LGQhXsfTE1x+SOiv3Ho2y1aYID0a5FOVtjfILh5VLKMXZcNYGq54qiPNm EZNUuMvecZ59nrLqFZGVy5T13VPb18XRMOkao2+y5i29/cMYdC4nNllEIcBTwlbTopSaKhps01SJ jgSKHgVFvlGQ0EJqjyx8hPxj5C0Pb5aLbf3cqevJ0hyYBstrwfozTqAa6UJMlwR8WOh4nxSnFycg 1WGYQTZ7W9Rr2/ZIYxFeGGU46VQs360QlXOdayIiHw1K6HZ04amUJ32G7cQxy4cYHPiClMRPgh4j /VQBPaOvCA9vXDATFom8DIxP8pPG4AwIg/Dg9lVuajWiLSZZtoM+RVJHonncze/nUPZWr1UUpV1H iPX4xc+irRR24lP+EPCuVSBB9ShxbiU6xAVRPY1TvJSXn8QSwje2EnHtb9Q8SWTTEZaWzRYtPJT3 5PGd6aQd7l0xbhpxApi0AMscPm7mNoldOk/wKSVjyeWCWMO6DKQHZJ+A9waTJS/r0uw7IZkwvKkz e0k2uUEg/BK0s7vqkYIZLozg23vkuVepDSGqCdLyG8/1c3dzfhvOmZLErif/lLdD84Jo1KzCjlNS sU9+JLoo/bevHhtKHIJvRG7Rkyn758y7Ozn9/QnS7LEPjziJO1eL7t5Zu/BiFm8gNB9QEExjo0Jk sUyuCMFJwF/DPvqV7BiKBAY0f+0Cr7+01Ee8lglNsZp/sEn7jUc5OETQp47o3/6PgHW6XHJROm7A cbHuGFRtkUwzl72fAv3ejUY+UkztIVu0852nl8UPtv2YCjh99duOxgXUPzlguipE+39euQHT3LkA +NXpD+/8Mw/ot9Fu9ViDxRadt3rrH5ZrnQPnU7/tvGata6E0FosJg1lyfQ3CySVFT+PbdZ2mP+te 2ga+NjG34NSmmUUBHvetu8eK/IEv1z3BtLTWgQOke7m+uuUkVLPgNd4LIEwk4Z3tdQG+OmgqzAZG i1mcHjl4hUefvgTnFr+uRLgPstZojQ7uFFHi9r1m84F/IeozoXkOqPTzVx7NeexeEaNkMcpLcrTl vzA2F7Q3yHMouJSFhulHOVRp4aHy8DlV084sl3jfTp+Wltn2/9HV8E3UgXm3ZA0d6NfDDAa2Ed3m BfzEQjSpaSti28TuhDqWBNAmwsFoIv+A2lvJcFSYVJw1S/UPWixjUp4HRUkyo3BUjVebIQqRai3J fjeL/oZ4qVQf9baF41jB5Jb11xgmubbaBHnbxu6UpVqLYRGN50ixS55r/2EN1NgCp1riQ/eFvJOQ qE7Wh/ySDypjYN4xOgYt/JIKb9e8sGIUKpViHBKr7HWTSNno7P/JR8yX5RpUolI9WLnnFcqrsGb8 MGG43OSwKA2yrFizgYVHlSo+Xhauzx/s1OZG8Cc1pPBHxvpE3k6xDaIkU2LVsZ6Wa7tnbRoOiKKF jakakKZs912/oPk29U+moK9phVCVl9VLgnjF+v2kStiHkjlERxKdNqD/WImhLN2b1rORpwz4czWg EPjCrYvMc9qL5OCJRPCxUoO6lvkdc6cOL+9lPJRQmk4Is/Mni/Wm5Yv8oExoeUbeotL+UNomIZLX pIfWPJcMERxDb6dxGeofCZXq9lkh1P/rLn5HdNaHNQWZVgPNdPxrsHpwz+NV3Wudnzh9xl36oM68 jxAh4ACkiJhHGi3dDCfTXVHQrdB/loJFdH04TmwWSPOioTuulKqTxPzSTZ0fJaPx4pnfpdqhQ3LA W9CJ5priNskYVBf9W0zAvTOB9TDMAceQTmpR3Sku+wIUbW1MKqJTOhQQFlcwpUb1Emb1UhLlEQYU Fouebq+qGSHgKgd2XRVtfNlVApqy/+dTFLNDfpPvk3SlLdgK7HEo10k5yiEFl+1P6WvTpCN9isZX vf93FUAwwgF7+0K4FZg1ydb+23vlLrBeTe35VAVIWh/dXVqnNGHbRu7414GnNs+kptjoFrV7UC9D LevRQ9s2VcAc5CkNJnSFxPVEjDagV0EYL/MkbN0/wVU21uqD+bNXxz9cKSgz2DA/uJExM14LrxWk 4dRJVHpGbnc6ya0NjxtcDPfYsVxy0SgLPOx0cUo3ULOJGomadsNXd0+W1bc/LROF/r9oJiA93y4D HegHCpH0vKHNQ0RpXUrkVA3uDE66Iec6rvGUQS9vBkCZKpzJGwLEI3z7PVyix2Lgy/4dk+mLbUnG CdSsXl+Xjv80VuOlpfcHlykyHRCGTolzDljgNEcAPsKL1G0QgBS1QVAngLQj/I5EFkyfcMlOcKsF knxbpukGH8VEcZOzsctz/Grasl2UzDHMAhtu9RtJdJdX+BsaMH4f5/rBlW1xPdz/FfPc8HQd/0RT 64JGrYZDCy1alsczzglZkAgzo1zMTGUPatj9gKSi6W6tmlDljBFNgZOvCUT8yO9gHR8/9X/NpfD4 8abzQ/Gv0G4G/QlUmXexzLy2TUJq2nmcb9WOp4XqrfsBSGJ0KYV7JQzmyBtieBIm7Y51WNsfRrG7 CCKopcPwdxk7PtN0IEJfv5knL2ktjN6VVeCr+AeL+BU9YCRC70egu/DiCLaianeRdEqv23hDstQH rWuaCbIZjy0RiCE8VI/pjYUXFBQVfkwlJJ5sjWL3d+c/1FUHfnXoL3ON23LLUb2WyfaoOK2CIotk IAskkU/OrHxv4wg7bi7jgCgh8yIJ8x5dxVlDmFtxBmSU14KKTrKrN3I3b1KhkiTO/JjpiieHBMj+ fdEmnA+Hm0MdftjWCN8NYw7RWiae1cGRPmAdEifvTJFS6Ivyygo85sPOMlYOLVpkHXNeVmoUt1tR YO1TonOYzePSfeJ5NHZUe7YAMyN7ZZZ/aASKxmkdHOF7hL4yPCGrQMtjkDwAcLysZ3F21+Wro7cu YuzVGECK/1PmN9QtTuOlDOafZSf0w6NUZkSOz5hlFJoejAfTIYWXQNJMWeka1DrYjn85A2FmN7K6 lbE3OAbCG/Mvgw+IIvkS53Ns1v7J5PjHpwDnP2kJ2Wglc+fPRgdEAy8QNoIa9j1BI0QQa4Irnm1v q5bQQGhwDOZA5A4tSOonEm3w1abppKqMByyydXb9WLvxc03PPfnYHGpwa669sh/BNBp5lrIpziwC n8B0NqXt9EHT54aIsm2Xebt2oOUAaHZhrrptpyuaXZ1b47zuvg96a20YJSoHOA3X+3dMNTjLrXrH FPYK4+l+Z6/USHRc8n5K8l1iCCRZDTmSoweZlWv8tcQfQT1Ll2jUgywBapl+kXavqhNRkjB3+hSQ SUv6FY09xo5ar6A+EVx0TpDYRJelio0DfzDQmpE7eiSbAIW4610HXzikRShKi8uKv8ymb5GVvr8A YpM5QI3EhPgvwW70MbsgnFl5FMrVMXc7iixGg+V4NaBYxBVTu1NKEhNRC4g8ssoA77/ae1NMbmvp 2VnZMhJORF9KrImwNUX2tsVxgt+hJ0sShZvBaipXR6iMmYWp4qRUsV7hG7FeIHFO2MqRdwGpGqzU lsG0/tjHzCIAFSUqJ9ghDfgLGG60jH1rRYNOBD53zYZGdzDgeDrz4EnqQyuTIegKkSPS2nP8CxtU u8Xq6rmOkvs59x/h8EhBlcDKVObYLA+D7Y5y6O2vR53FWmS+kGUWeF0ftuDg7+sx8HNlEBn338p1 CITx+lSozlP/n2VPQt6jxRMISc0sEqA+abk5e1TpjtrsHTIyn7TOFt71TTF6Fpf2mTvPLULKgYmD L5B9Vi50DKhpsahbAs9mm7O4xCG7px2Js9qfX8fdLki3Oahj13wxAoXF0yzMBY46dQc41XUks188 4uPcfME/32UJTu1aguPsfgN4eb5SiboqAowSDcIkL56FUc7J5IfGjFLYENyImD+P/8TJcF5983+6 3BbFz4K1PS5xkrIuWCP3c3FiasNdNeStH1FblRzF/xFM6EAnNB0bIfCj2Z77oSI0y1AkJ/JKoNzS ij3Yid93tyIjFAnLFB23R2h3ZgOWuVtWywAFSIYI7Ku+cigysPz7Zq2GnGOT80/NPdV+OotoBxEO 0WWBqpBl3PJT9wO0OAhNNzjLcXX5UJhH0i2GtaK5NRSNzqk+by+UyPYMrLCQYdHW//NnLcfTfcD/ 7kExeWcI9LI7o5O1K69MS5ErxqGmPRpkmEwSafBfre/Dl9NZ31m/4NQXoLC2ea8QeLbUzWpC2VNj 9ps+o+peosKzJgl+t2GecrG1tHZY3QAQ9hW5RhFLtzA9hMSHc27pMgzW94P5vfwpua+aBZae/p8Z ogIEIGs8GXbHN6+6FxRqTQp+1euGANcaB5xOu2lEnp+nS47My/Y6UaTyFN+tl6VXVikpVlQKd+kW 89ptOq2rv8sbCUvkMnoCeM+YNnwsyg6hgVw+bIWkVzpzqBN1jPGRmE0lGqufEy50F6jEbp36d/TS WFXU0cOOBp0ZLExiAd4sbROP23NVymbqtYWsLB/LhBX8hQ3u8ImOWNuEB1Z6jGpgzVMvvps9V8e2 oTWcm+9/cZt6gqgfQxUUe0E2CS48NwcIM5BO4E9P5AyVkAGcPgRaoium/HqraPYLPFwX0cgRliKM EWIuLMsM0jvZvuv2wvJEyCvHKR6kNKE6wDClhksHx5ZOB8mlWFUwGA0OycQUeIGFfTfzBIt62Eub kodeOukX73fvFYOBrazcgxY5upRoEPOwm5D52HzgoTGUWjXYAn99O3hB5eZkB0O8MuDu0YwFuCFo JSqDP3SkhhZ+VCAXc1Zt7J2e5fXAouG1EVJaNl97ewRw590LoFzg+VpINkTKSpY1BCXGBfSHVo0W wOBa+xfiU/ocjFINA7Du+SoxVISr19bFp8DjNVOVZ3Moxls1gnABlJPw+q/jr9B6IBFFoRN48Dpe 573bW1gKwfT/FRLwR6xsoaC3kkmT50s02vgkbWsPwDjSlo03jVxD20J/T42tRgTbwYybCwNn3XyZ SOl+UYh9fPHJvOW8AAyXSwvplb1kCVdL0KZxZGqPzAQG+ldd5AFlsJAg4Jtj2eOy5qYywSVx5Qdm 0gubTyOKGVBAfzZrSfV9vAiMseombahlnwhZfM9UqZ7fxl9vTWelSbHRT8yNPV7NyYSj/o1sh0XZ tK2d/wQLQioe+B11AfIltoIW0MABuVCdusJuSTIosle4/3241knWyjuyoe3XtxQiSjL6U2SvMGgW 9jeNFnh53js8hNYhM362ipf0FUYSo7FqtYdCbl6sbFV8ahh8j/HA+6jcXhtWD6iZ5CDAp1n9Q25Q ZqP1l8TK7zgHm3aZhFVbvX3OFVFdKxRHJbXKj/65ksCz+eBKHWJDwiH6qVCHUKR4d5GWUCP5PJWm +aRC/a7NInwCxIWzPJeZGEu7SS61y/hxFdHa11+pHu4yMJpOJzabYgE3R9m16V+AKviGPJ5ix76w +QZaPHxk+ZQEysC/iGermgvf2Wmy5pvx1gHx+dl/SciHYl9eqTQM2N900qooyBZQcv58IEFOARFr p6nFgAYFK1fB05Xygc3MqGkbD1pJFZVG1aLZyzIdFe4WMYvX2gnRPh3Q7mRD5UtDOOfKnWzKmKcq ZJY0oavuZrX5FQtZi/eLR8Gg4tDuVPkY9PcN+RZ/gfe6EV5kS9N1boTlKK496RfL2hswqHZcqcMT qxL5AtmtiBMD0IVb2IV8/nTbPIV3N4b8JURnxurbkVeYvjDVPFJgB+Q/VIJCEg6RzfOVHNqdEnus jwRMvfvogdXBlDqMTMnuyWDJigbc4RRJeLhNiNKlCBrmydhsDaDb2SECVb8S+hnY037UOFDesL/O yBuZtYR1WwMIg6lYQpHx0aqGSigFeq25oxbNuOafEe1ElM7bjxLO1vqxThwP1O2Bjwc+eZb0l1yt 3JKWLo9MPjcdhaElJIw7FTSVBVsty4mo+qpYGmUq9Imot+ZdxIy+bdOUq94fKd6WidW7/DikDu5a dqubKHm7YoJRhe1gOx/jIYlE0ByCPzeiK5epzsNmBs6bo1mC0ApZLDgO7b0nn1McgvyOVbH1sc6e uAghBmJqLqBFT0dLipf4k7b9PhO/9DtvTqhoWKkpWzWtKrUQwtWjdDuErdYVrUP5Y1+brMG5T58e 9hiJ364uPFj7nzyl2xjCGQOFk8nUSFR7S9BWg7kwRD19mj5wBqdJtW5R8c9OlhrLipSyJQsPVGxD Vwkzf7Hf0WDY7gbkC6rL80kC4r7p25t95AnAZ8pWvxLXgx5AWAB37jUepdpUX5z1honf2OI3GqY6 fmxJ5nk+3jwRvhBPl/yeUUO8yqfbKIi4DREp60AbFNKQAEFVckH2IWMMCWLKsXylPViSpAyrn+z2 uPu2eYw1zlS/ESzHpHt9Nayv/i/WNZZXRBRyYGXOVjC0kovX7VYWjIbq4sgOjKsoq85Xb/OnhW4d DK4SaiL+PuW35ME5Tt1P1rM/YcElbdPZMne+qsbil5s1TLnHVRwK0V70pfcBjkD7vrkXow/+i2yF HvTnd3iGGpwcuZ3Ca+l8b33M001LMySDsLYMhhAo1oaONKcNtcZpLeKtH8zAJAAEaaU+Rt2j77cf UXTyD+ea1DejSlMhBbBSC4418vcRMj4NVp4dGStzxq4uM7m1Vvy6EC7rcNShoBbFh8QrEMQjkngA o4opAMONXoUshxtueMKu3/CSMMqefTd7fmpBcKb9lykLkrS/1EN/xAQyQkOZMOA45VjpGTxeeBFi 0HWykwF09YZ97mOjmZ6nh2NoN8O8062rkyChacTWOYkdiw3gNRnma42UqO13MJvVi9W3KrMWLzCf 4Q3YgkjGiwqmRA63hClrKYXTSZV0ZEfNZKpUgcG47X5D3uKptH6wKYmdWZdcpeIBX7j3vXNF8s35 AiPBFY3ul5BxmFKSoRyhyNDJVTCF4rUDSdFKqCqBLkcFXShGbOwQzZpCaAWO/HDsSWSU/eglSa+o 0J69MMu4zSPVnWm8l61UTzVhnpNmISDUEO7TF7fkm1dPUN9bxGUla0LcfUptsP56IdRVZz9wBIZq c2uZgixCnNQNtfImbl7osUboOurtP+TobbygexfvI+x4TVL1InH1FHtoW559JRM45Yv1C69FVtul ccMezmawoJw4C0xjr6xO/PMFDSuQJptL5A24DOewFM16exTuoCJ/XCZiLe0KhUbAAhLmNPILseGY g74MrD79tFaxTi8ut0V4oZUfjPh3GfmlEX8Gk25A7hmHE8XQCHbgZEpFUBlFhFARdpH0F6MKEoGs +6CxTgtymu20S3kQbVF5fE00zW5/Pjlr4QouOmv9Dz5tAgICaB+HKUrSVKtxHeuj4MJLujnVt8+b TL4GvrLbL+M5BlJW/wqpcWkPpphN2hQgiGERmR1G0wJlyisJIUS3rsOXJQsCc3ox858nxCT4iFja Q7FI0a1wn04j6NeJlxqBOItsJmUnkYA3xhLooh0DVna93uSRw158XXK5tshLopNkV5q+BB2LkuxX LU4XZzQixdj5n8U3K6syEu715xKC/Z1yQMp9nwscfu4czW/S2Iq+cIMryzLA/2ByiOOMPN0YqGrd e6X0lgLuQSRgk+kICeyxG7xKDmTXNrB7LzcAXZN7NXm7z1d24xomlexR8DPMA/trZncaZkPUHBP6 uGkzZWwmGDxOp9amAgNBHzXLoyUHpxZcTJHVZR+yPnyr1RpJjEkVGTuWbrmRbVD9WRWG5+BX4z3y HK+lRVUm3P5yzvPotwIvp0mRDE63BxHnbEsAauax5or+VUv6WtJN4ZiEsMI+9lx6DZc47QIe5j0t ++kX721K/07pZCskAGdOhqO301wguWJL8q3cDC9caqfISMVHTJMOHQ+GY40buSWO5zTVDP3vF+k+ 8BnrxAkfEhWNldZzFOz6mQFEUxmpCTwWik4FfUS4Z7nMUvcri6gTBNibolaF2SC9MXgaIPBhE2Sb c1JkgE19fSIu0N0v5UFfLa/zigQaA05zGfWLlFBricPQuG1R3BfCvyjD2/675MClkvIj8R0HewuH P3PgxpxBCioLW2Zj0bN4+1HbU3dAyj7XjyTs09188IP2Uf1ocpY6SOnQJfrz/RGbV6OGVwm/Q24E ZnqpTtJXyeS/wJw3esxFFaNbhNzslkmEvSkSfO9obeng0hxw9f2JZKqmczcS5zimN9hd6bB6cyL/ AMQYXZpMue2vXDqA93M+JVBfkuMPC0o98ufHPV0iNZ9hMjVmEZ/+QMaBQ74ys2Li1tT8gLNPVEEg UGGubDbaJT4C4b/14j68jD7UkyjA4yAZBHOeR+D6hpcJUxqVNXsGTUMlHShhinuyTSIhGIUUZ5nz V/cl8zqa+ZeqwYIl4fIKztIgJK1DvryOPseHjofpYEarP6qauq+vCTa/am100dze+18Tnjp5pFA3 J47y+5CTSi5/tdAFkwt/fGE2ThUl49nfp9QCDZ3kqlSuAdA1K0wZIWWY7yhbH1YvL5VqhEU2brCA 4EU1fLSSQDDmkrI/O9qTEi6VLwfo3tsKDS9ZWCDB/IX4yakRTRkoJVuZxShYu5Mb52HifW5AjGjA Rwi/b+5a4FaD9+/blExBuTdGxv+Isc/aUzCZpm30wWrGPUbD5xghs597VsLZ6z3U6MwSMkTFokXB qw8LTjL4ETUQNfXbNU6dmcHA7hvRj0BogG+zGNhzojgt4kay1RkILo5lLLMRaM9J1mLkOekdMHcj 7+ekEzpNwV2MeK65Z0RCN1YkPD6NjmiF60UeHd3NPo9a2kLvf19w+/OxpM3RW0tnRsPlkfDeDObv AcFrwap4G2KFV8UKx5CUybQsyUyXvtygGANUDEkufUBspbE0jZMoIpN9N2yVh+g1xEeUFosV/6kY 1qeqrPQKDenxfb7H2dF9npuW9cWIvBbN4YAOoDRM8ekDILVO6VKdaWlHRqXipfItmEt9j7nweGzf VtweeZYZoOUE2BljkHLJeknNjS7Oh1yMKcETGeIMlgqaFD5wH8nSjtSgNp5oxf6UUfgUTCVbevUh GnWFiOaguvlC2bMOJdj2l1pz0ecDkPosB3FzdnbxGVFp+B5k3qSQ7Chw2eoSm0JD63phiG8TTQ43 fes9/m5ntgZv1f+is8FXqrLLXJe3TQ06WVFXlixV5vIem7/iqQOwfH0hN3bH+hJSTtZYKVDh37EK t46cVnG4PBFZPQR66LFyOIZCnNHtIsbuhtaNnUbn33FUw/r5HIS7p8SiHZ3SmdIEL6V6SMlKXdlh fnoH6wkKItbpWBJGH8CVvJtfvb29sCaHQ0vxr31y+UZKo/AjbwbC/3iqQfqYEdMhdxf1a1eocZmv SHPDvEgeUqeFs90fmWwck6CSEAm06BNb4wA2nS+HKPXL1SPEcWbKyxUpmas2W2h/LBwmBtSYRrb/ Ca2UUGgV+QOJL1aDOEMS7fHHA0oMKGEv80H8y0MZYbw5q5D6o6ssAlx2fAwc7Cxk77oSvevtX2Gp 2pHWQsfq63vnb6Z6KAJ8KkBb9TRDTVd98NiQsOK4mlcpw32B0uRiaSPuet9ROOahxTQG6qYB0r18 1CcvRag3fZqYLbLoKEAHrZtJ9QtRPeIymJR2mDIXCQCXbuECe+C3vPx6OYovyBQBc724E4EetCud HxgUHeuOZOwIHdZoBdn8YLVdzkzWTvqQZN2e1zA52HqsketC8vnX1IQgxlWfnaBHSCcOW5eJ5twn uQtOutBr5fQbWztST6HKtcO8VKeS0v+RV/SZdDSRjEPetID3JWNfNn1boJKOXxIADPxRI0JCgQiP 6v/4jlBsopiKrT62Um0RtJyMhR6cDFUXLw8oBZXteiHhmenHpA50ggll4XL0LumGyu2iztTBDIha b08xGg4M9K7LonP4bIleRBRirVpVY6VmdK561O3Lnmf86THsPS5IW6YRz00nmBw2nMrrrdUOyDLy 2GfklnPOydGtBLu+dGjSqn3XZNVn5ydH5dkk02Y1pkc/aqMCmko6FzHGaJJW1oYN4iOsRKPmoHLH ThlbTiJ493O9NC11rHGdfkvvpTgXBzB/aNz1pcqPPgbt/ajaZvPFgMiaD+/rlG+omec183SZEmWP 46I/K7IxXCMI7Ijn+9TtkWPIZZoH7Uut4wL6GqAi5FDB+AOhJldDwVv6WmkvpONFaUZKSQb6IIJw dUHKUACDo3JEHQPi5CD9HI4XlFKkHblToF+6J8dw+tEF/dPIdL4QZPgGc23LcEun1fvuhEjbbeNQ yQQ1D8SZ4cfmAvmP+X0CHW6B4tKC9NzP1bFz53tQClgcBYajXIVZHzQO8EieazAzfk0Q6Nd20ByB mR6Su9b5EBToEW5uByuw/2H0N11Hn8wHg6x0e/vY7EgEVYAgNNkmnYDeXInjZEuko4JLEKX8pa4r SGgTFXkN3YBupUetiuACy2W79I2hZrWSqJIjqyo2NL4V6DbxR0I8eWrq21D4JG3Hwx8ZYQ/7ZqeG Ddu1Cw/vRXtks7KmwHLZHMV28c25LdJOTEFmOUPiTaSDfWR3PZBwHV/UbnLmnRIqzv+XkjctcZCN Xo5cyqcQ3HQq9X6++CIbo4IWElHTuRoTk/UgLhL96XCs8Qf8deNDme8jVRdADDihmqmvGjSn6Xeb UBbm28RcCMatqoRhKNOpAc+CfaHa/0nKpjJkq2oVs2p8IjqMDubUCqi0OPJcl7ckhXZepth2QPoW Jnm4SKrVV+s4oLHbjtXzgtdxW5ARv6CZ1ZAJ5pNYhv2Q1SCHqaLUNxZITxc2llimdFAeIZpXVsxP Ib7XyMuc/UnBWalBKTvuBGaur0u37QQjcqhyiXhJCaITpmxIqN2NFY7vj9rQLEmx2UCPweSVcDiy MXLiCL3F9sxu5uoO1rBOIv8y5SfDXJJKzxobU3cvIPBEgtatmTR4nxV23HJXBg2crPm6Kz8af0Xb snq1fqJUMXe/fVx6c5CzExLfY2HeK8LiebEprz8XC7gIitEYc29rE7t/mEl7H6NKZB4GPtWfKPNo s9+oKIbstdlbVsKjzf0s16bfrHREQlKWR2Ex1Oj+P2LpmBWLMZZHxenxkuwZd8y7tDLEzv59clXI oroy0WgCGfQjwvgaS61Wht0uZ2JOpkbPmFZ7ROJPkvfDBFmaRwzBtzL3psBqA2TbzLF1agRDVDci MrWYdfYdYC3++uGjKccA8KXEaIxbVe6OuLVFG0kSTOHZj+4ewFpplj30pLQgHoRgW+is1geNY9DZ zm7PuiAJOLnGzaMyyt15ZoQIuMFyjkrG4+4gSwL1bMeTOXgCNqXnqYEpQ0avdxCDl65XMbHiDHDC nJlJ5bYc1A8t3lUcEInfGd2XQvuxIGRIfLEi9ied0WGr+e84Ih9GbsLATpnIf5T0vZhbwtS93iIA 1B5xsrP3bN9TVtWjmuuBJr6GeogxaWYFeiflDTfx5Vg40Tuh0B9f5FYhBBV1VFKPYb9w8c0gWlWW dJJ8qpg2c3lb4YBoDXyKy57iPmjPbGdN2WttR8u0NFNLHdrI86TcAm3gHjc6JjLiW5DiO3rAwR8+ z/ek3s2bUpBQBEbmSwIAoFZo4xxcWeWCOlbOamwPFzQVVJytQXXW5gRcugNIpG43ijKpud4jDEZ0 BIpg+3E6U2DojgKe0UWp/2OPeJDlt+odjb+6DQp9OkhuDBDxkmpxxx+uM1Az0sq6NHaT6P7ANsai /zTpDSOJuvhWlwxvMQH7Se6AcZ21hjQm8EMSL1qt5daWUFu3vCSCqpj1b5uQ/3Yc8vmjYrvGCLlh AuX1XUvWju0sw+WD+42yhTM5V42xP0Zv5cgtBlwO8vjboFwoL4xcA6At3M8abVOuh2cpppaFmoep Q3XoZKKgdMpVYzl9bcpsPsakF48IYreZ38BZqWL0Dj0vB8Bl+5ZDz7yViQdgiz09O1j4IbNSF76h M4+1TfpRLidftm6ZlAGiLjJtOjDZKep36CV865PJ5UNtNO9oBCRTwxteWSf6jBaAswGiUdedJpQN LbP2XEWmxYF+qRgvhFumbHkBM13OoK6x43FbpWnFvfqDIbGyc3d+gBOfrP2bL/gG0jDKv3uQkf90 JJ4T8DbRX8P4cKsF49hW7nNaRhnGcCvg23fFrHxuRDTEP7H1iGqiBYxJYcWtOwMJfJYbqGl0eoaO rx1ZZKIXEWPlyDp2QxTEQFs47hhOOVkpUsMJSVBTWUaAunr19GRbyreGIxlHPHqcy3Nuq0P3PbSx mgS+hQUX3jztLh76cfkKCfI9+YcE4uOOZ76o22DN5hcvyUuV17kfVwsUe6iOCHslkEtLLuNTeec1 ejTc6BKY76pjGA+NwUzdcnhSMr51ZPcAeB91rHZN70JicxwJdiBDkqsX2mDk95kDwGcSsZM6W1l2 A0QgwtsILFYUFEk9DgEcn8LWscMqKOZhQKd4z8Njh20dLJEPB9m5chYO90xIbX2Rc4A+uRpUiG0N dbAFQpjzRfDe0/82I692YbRElwSu8A5Jr0oSIp7Gs/zdK8gsC8WILZhaOWE0DHYfjaoPLSBmuHs/ AHNq9aCQEjkThhDbCdaBJxEjCnSuxp9fihwvDdUKntaWvNFU8PHjiYIxljq1hnTyzG+6uUSvO2cN 7t2W77KcWjk1gwGZ5T2207kLSR/of0CFhD64JB3Wz6XbWl7UQg9neohNQNrYfkmjl3Ki4JOLYu3+ Chwadgb9lWjhCKY47rwAEf+GohwqJFjA5e4ZjyiJiQoDVZplIcz3OC8xpscwnIlEN6HH3aQa8IWQ W9+tKT2uQZbyfNt8tnbl3mVdkB8lvmxTzpLhUlBhS992CAoE1PguRBO7b43l32OtGWcvgWpxY6Zs vUvdqcg8soyRQh3Q6xy0hQvd8T60ANtEentLJLMKnvfu7p/7gTH0r/xZN+YWaJKB1Ua4LkvvL3je EGIyIMRC4eRQfNWig9TYXpi7jp9SFps1+8OZ44BD3H3PaL0dT0dJhy76yt8zRt9BDbQMgCghztwb DxCgM+WmzDB2YxrEbHIxYuhnV2zVrG4rn++0OgFMx/j//+Tggip5hNldfdceLXZuzuJkz1GuERC2 BHMEbAJQtYHYqXQYsD2hnkuX1RSmgUK4/Np9A/vuXj6xSX1lJeFmyU8kjjOMr9GzaYoZgoCF9keo YtnPbZe0NgolMY0ZQGeioNtGuiKC5u48zQedlNRwoc2Kx++EZ04Nbb5zWP61EPbIsRU8cDfv5ZED iykAVVgGeWElKb6SlOV7fdNVUnmXFbABRWsAktKEagYQv85rQXu+wXuNjUmAHMHzIsjhm7/b25JF mRL94XTMBjmBayiMUQjhcAjYde4YUvKkAvmTR3ijmbIkKW7ZxOqT/WhxIo9Fwkn64znk4O07nq+s v8RuKOAhHzThkFLSSHd6c337fQPJUbeK3NfQ0LkHdzLxRzwn+TSV7tWfqNhLP2teUar1oXjcND6m 2IpJWkEfD5VGc6ur/gvyWYkI0iN9Vc/jwskQSuiudomdumDa05vzNaNcnE8PrX9dih1fF4fuvs0M AR5sIdk1pykVY59Uu7kxrAu82YOgPIP0ra3XiWy29JFVfh3/UqGcP1HUNHmn+RxFVhsb0DC1brbJ L7lpvyOe8Vh4PPiNZuj2EyqTqaGMVyeSf3W7DcLXzibIzy+bo/UWBgJHqqLp1OkHIo5N6GLj/J3k JPR8TlHSMoGm0JAJLBs10ry60lA+b6CUrkYjvi++zhJyl8fOfXaIh/DCybpDZ2e6R80PTwAgPvrJ fFGYwP5mwLvldEtCyn6XYs+JNSSNb37gRtD8Yi7/2CWqPzNm6fl6uyK3NmSJtB9qIDc7yc1g7nuL 8YrSPK7zKgZRoKRFD3gY4VDi/Qa8G1wJtjfDJ61r5W2QMHklWW4xavYMf6YNhKir2SL+lxUryQ68 DQG6DKDntI5qImHK2zzaBwycpFXPLYcR1F0/iTtce3Bm7CfrFQEOu0tUsDt1nQpxMK/IzDiC7q7s 73My+GNGeUmmWleVLPjbrv/ILnh2cUsq76xkMWY7rSz6zgnI06HjebX/4w0KLo5tq6aPlxD8hApP KTAX8I/p+QQi+BX/F5twSNKqWAuidX/7ncVnCxHhvNRSCZaOOIqthR3M5/IPskxPJfgLFLeBHbZl GdmVN00/6DHUdkEai0NeclmcskjhQ4OmAUd2mXtxzR2Pb9CtnHqIWFH+GdPnapX9AYRp8bKLnzbn voDgYo/PybwanH1r6bf4ALL3VcqIpIjpzajIG7d6xOr1VdNoFtoUqWzVB4Yu4/1PPoCLnwGJL50c NZM2orcapCB/N1eo96d6K4qQtLgr7jiZZh3W7XLSDqx5eYZz2zmyaqkxfS0wu6Upq74CJLpRs6VV HNFO3Zn9gp2kUfYDlnWNcFp5vYIrUB4w41Nt9gSsN/vOzgRVLLPp2u44kfCZZ1wSJ9sSgcdk09Gj Xoiqgd8vdaq9siX1EcSAbZuPXN+82FjOy2HK5UgRMGI7GtCWK1v4ZXBUtMl5FAE5xvolT2oOW+OO E7weFZdJ805EDJqY4fOg2iBKP3d3P83CqHUEsNE4WMAX+xnZj7kXZPrkwSYLE3u8LORp7vzkH1Jt DuklFsVFk6UmPLTJSk2bLwUUOtzAf9tuHEBVYiJcKiea1wxx0vUQU/vwU2y60y4t31HiJuC4HWPp YyHaJyqwExtxyTs3fjnimeFskllG+tFqoCd1KYdVVF5hNYBtUS63D45ZVOzncuMQBqYS5q8zBDGs /GXnNSKmj5gT8qtzRgR8sE7DYHE7v43Y5+YA7qbhoekPpy0jK9eI/+oQ0WPO0N7NMzdvfztQ/Mou oc7iB0nbFbwDBpkpIcGAEBpbXf1eIG0MfEjtCtZ3CQtAlJbWOEXujWRTzNsLE5FkpsZAz1f7nIBK Vy+zNu6re2+ARKRmsRYcIniaZmzcKEw1AmQo1wy6ZcXzsFB3vRJ1OXBU0FidjlaETxoF6OKRA6aS 0JZACreFEDMNcdJsiT1982jQCzokEGgqzXL0+VTyLoS9kSUWESvPY47IzAdVFYIa3m0RDxefUZJk /7vI7acluDAclEdiulYmUSeZ3PZ3i21a4l/BcvNTs3aCPBQkHEOaVCFITw9AQR6SY2ouB+NhZ5Nl JG89GOt1Upn/lz/67e1l5GUyclMY7h0mNVdf1AKGJjYRpEegI5vefrgW+sQ549xYwWGvbsnlGAXM 0iKIqDTsNFNx0mailfR2znmJnudAgc5maERZfZVLjFPKBZIqodLd60l9qz5cxqqANLS0fcI8diUz dR92ObI1B21NYfigYPNqyDxd4Ik1VXRNpWA2GtcnT19L69XAsBLE9YwCf1UfmZF7Vuikd9Yxj0qe njY3vVIBR3ekgGuKeYC2GpA4j7YYtwN8ZURCw4BkWp9/OfPl59k6UPnq+zitwvEHjSKFArZksbnk PSCJgE+ArgxriPKOBqzcTMIAbsE833O8o1ISUH8BMs8TcIgvxEHtc0MYpq9itiyO6jMj8P9Vhbjf +XM3f2K813oxNbeXbIrGb8PIvyTSrlTUKvmTO9m8qjd2S8KKzGPSeZwUwWxBX8n/hfCvIh0Sfj4m 7T2l9qVN9wZFgXAgH7kIBzaeydKNFTT3A4+n7s8KrBhXpAvXAPAFNUk5jgLrFGGSikvkBKWRWMmg L2+TaM+sWqQJ0cBjPeYViqJ/pOnnHPEGn3P2O+svIfWJZPD7GNmfcFOSZLYzQp1RdVdux6bgdIcc wDdV6ZONlKCG16HTOv8ldzXhDqRAoXD1ZYYwhKF/pVQSU8Oq3fHYPgXJ3uR9r82HqZHGGK1379Uk kFtyD88MSibkkFyAqa7X47vGS/zzc3sJ825DJbDkxNYgFXAsM9kSQf/jD9NEYILW1ZjdNc3s4K12 2ncbo9fiFVfJ6VtYEGpzLdKMSlYa0YEQZipq6bJ9WyugolQpLgeEKkGQQN+xNNidjnj6YDEUgQen lPqJFUy7TiRrpKhGK1NXSImgcPvwlsaWP2hpxq3n0tnf0Cua+SKpfYjZiNOKJHWTfOFoPi6JfCqB 9mJ9BQurcdIx0UnzRAaDBt3KeVrY2OY5JoF2RcQRnvCULfD+cz/p98N2brjkCMho/FFW6uBdJDLt rJsW6qvaKNU5t83ydA+a4uPpuQbUEv2jVjkITaoCFP/nLETu5P6cFZMYjTY8TyN8XvPPCvqveNdJ nYl+Ts88BamEtFsNq1O6qATN5nMvh8ooRRPLUnw3sNLndIiLWH5cYxHZtrWdP01C5U+euyopEUf/ MKwgGqrtfYiZAVWTD20wMrrG+GMwfxtkNeXgH+3j3fSNBKodvzKmimxrB2Jo/PHlGMQrpo5uwb4G DdERhrBSErkrII000Lg2bE+cqDUcSRzADpC7uwqGrtYMB+sGiYGd/qg8NIsZ2e6Z9zIUzn5xSH76 FPwHhCclYpcjQAJVenbBH1UnoOgn4G1fVxldVDKVwRhpW1sDwj/SWUCwYmLO2thK68jv7S2BpLfy XX9p7outTbyqFsKew1hh9TMAsK8uogQEGnOsQli4EGjakYkZFOmEh2gVdGE/UcImfKmQURZzP4Pb C/UFFV9n9L9Qsod8RMK7637orPKDD8i6g2SmvQXmegvnF+TdZOv3iWjtheUVO3Tfxw7OjhYZA+W6 nobsxcOoO9grL1rX7X8Y2wRP48F12UdQZW4rV83FPo94eQNnroIkEholQTSvv0DtYfJbztOXC8ac n3CceQYLYzb4BzY7v5lsh8bTrWmOPN/RjFP8EhMjgr96RvKthR825Apg3vD/HHxE3+nwiyq1YHuV KiUKKI/m1aGMp2LwO6p7E3CXi4tfL2zlTiicD18q04Vg25TobBWHgvpBubiVeISiNK+4GqCBMw7S plwYXLFptjfcO7GsKQr037Mz8Ufaw8lmnPHPO1z0TEhV8U566Um1QSF/Ox7ooxvXQwYZ4+c0W1vk vWcA6Sy2MFvtn+QbJfYmZ0nTu4ywJed4BB5rzYGQVUJFOB0O2g6qvnlbw5VePtxXG4FEoSlTOePz R3W2c3fsTwZLx/ADu5QfKIToM1mLVmokXfnZzY9JewITs6sgoptNuwY+AtvH7qFmimVDCJVn8p+z 5C/Tc5A7S/2cNP+04C9edqNDYD0bI5la/F1BZThem58WnfUuM/9m/FIQu1rIXu/4mpNWwAKRdrnD SGSZC1m8PoxYkUSXogQwaEc3M4MNJR2PcTGyJFETD+vA8b8ScgnV6irXO6NC7cYbeOis79GXt6Jp Lo2DYgfwAhC8BOhgpY96nuUB0xfJeL6yprX3yMxxUEZ6XZ5YJQ4vdClFXXPyhLvyA3/+4iIvqeI/ YNZfXyKp+ZNFBNcxet1pG6ylj5zqCTb0lLWoD3F1hnhopu8XvJ9nQInIpEGA5vc/gXgVbhSMrRTn KZclWu3ZoZ2LcK9HLBLvj8Vjb1+rWXtUlSYwIZiMG3VTL1eXCHJzZKZgxhguErehO9n3yikw5ZpC 9PmR5jmAJStyCfy900dvOBNy1lzjWC5JbQtAIN//VjOzrHSw9t+dmpL7kn8Guime5304iLCdHNWW EkMkuiyielEBpyloLjwqiZn5LGLB7eG3rlFe440A5bpkwCdDjJ6U46+hShMwWqO43Ra5jy2Q6nNf rhTNRaEaPUPZ0WICqurDGzvb9TsZ92YqPM3NLdYabdGo9st6WTwqFXydrDekfArbjreOK19PAp15 gx87WFc6ohoUDkTgxRlbWvGYbVuLtoJBgrrnG34GJwZZ/f4Qd1XbbGoc0rEOeYfaYOZ3E5WEqy9+ naHCW7oekRa9IaoHci9wDSg5pulVxN9YD0qZt218pr6UqgAk6beVJjBCs178SzsSVrFfppJB4kG6 t6zPY0MQ5uQQOWfvUUIICLOFDVNnJ3DrYDwXgDe9piVopPc7RvxBbP65nja9Z2VU56dF2IwG0zLD i0zE+JjwfY6FPXU7sGJQbLklWjoJTMnYjdW8AvXlPGNC/1yNbEdEb+vFnrMrO557FoEqcRhSYNvQ 2UYPwwFJ66Za7kYFQ87225T9At13rf4G8NKhraPOdEIK8cAKl4fXPgWunNGtTDb/3ZhT7bCWKXBp cYR+yQAXmCY6CA339Q132iSQLMIf+/3VtpuEOYWy723iz4Co3aDVf3kN6OWZJ+G1tOirbnXaOV4O 0JItt8yhsXNt8iENFt/6sgJKk/MUUmDqjWHTxW+DsXrEwngualifglWN1dbFthiUg7AZqD+UeUyb r80bz5GVNmGwyww1wccsjPJP5V+o7tWKJJg8xtX5FsHfLx+GT+hDozefpyd5JVWhYis4f46/NNi2 wYixMz62bSKPzukgJ0NU4k6aq+4Y3EBVPwKgHErwGEKUPsvXXWMFwIsCiVLVJM/L1+W7RFhVRi1V aqsyfGN5nCsYmOo29RvY25ZVL49kZ4KcPwnrdDSNNF3G4GCiSX9RVcJdtTxU19On0/TZng3jct+J ZrcX6mkHfUBW2tCelvsGuVr7CBNpOL3hhueiDNaikDFQLT/bcoUl2XbcoZYUQUgATH7BFCqvmKoy at4INHO570q401YUa6UZlM4/VEWhk7U/u5kyeVCLpBJ08btykv/rS/Na6gVJMUnjmpRcZ1CMCbs4 0Iu7wedI3VEvJh6WDeqXbhPVbHjW8eaWbN0MCAa7XPPGYnTkpcFl4Hx+/57QbSDIi+w8G+4yE6qM UVFV2JrFpIGQ7uDbLY+zSxmWmdpWtZYN+pYB2kWQI+xoOJKC5/iyii/KN7I7zD7totGuL0wQMF0i Z9GgvlJ4pnkhc8njw/CZwy6LQoQ/C2bXR2y3hvIcDtWEISGBLPSnXYWvwCPxIabcXzSdC6tXvBo0 L0lJy8ml/ZLjE/Zv1CZyQOUgVUODNh4yuCsp+KvIX4P4Y3wjv+8O36jYl0egn011Zm1AoqL6hIeM 9eRL0QYDe/dMA7DRQBLb9sSEeK6QMSdzs/fbzbBFJ6JepKoUUN3DttFezqC2x668AyCMwSYQTLVB BtFrxh19V/OoF7SAS+6uTx3AeESOSKGdffaWxUazrQCZdDkrmzhVCQoRQUfwAQA9F1Xr+wuQV8jN nLx4PryC/8bboUYzvMFfR4xFCL74xqahzFTbfxDidD0uWIG3xQqikpb71inqO1Ty09Dh+X+UUizZ sEbjx+zAioVptV/Ial13CeDC+xsCGQicnffo6grb3KAJ604p3rBCshyeoC9m0jsawAW4JGtymZSI P/NvyWiAE04xz5fkcZ2v0smU/wwC+gbdRIu4WK5Xf9nGhv2kbAFQcS/Ll9uslSZPKGcOMaFErPBA TMrfqOoivGxpTiHTDiyN9AcxP190QPkajlDiY+A/Cljb4qigzFhMmqs2rQerjRIFVAFlQcJNsigx a+t7FdIPGkcAw5P99q/M5SRYbJuBgZRFqseu1UB4DFfGELjnZ/awUwVUxqHjY2iS4k6pX+2mftXs ZhohZpnc4dwujE1YvxIvwa1tVMl7I4LtkCLQ2fOPjrN0PvOH+pArMHxp/+qnrcJepiK6MJWmqfVZ LP76fQSRZOW8209MYznaw9/zN8vF+76C2kXEpUpBSOHltdk4HIqNrKAealrtIeFSHRwyK47BrWBo pX/2fEy2zMMaU5kSqsxbRBzQ9ATmb/0E0AnT9AOuywprD7Kq8zfY882C6aFpSBpa+eyq93qsdbBE zXiuG6eDgeLj6HNa+tGanLTxzj+4/rcpi1JAiicKOJkF2peQeGH1Yw1V2dDdf9IHAhYPsizzCanV 5kHRB1hT3xbBrQAh4IPKJpqkNQXVqBEhjH3SFPEXFOC5/j1cttnX0DD6/X991MZq1F280CsmdvIM Fh4gKawZMjjA5bC/Zb4zBUmYDVB8zxSt/PCrM+dMvQfXtSgHUIHGi/gLg77CDqQlqPyyaMM1Ha2v /O3Z7ZDa3NvuQggdeZExz9hQg2o+lloXlM3b5Xs4DDqQNULzLR6S+iK2l+aJdD7/2mfoLZIgULHh WjAJS0NnotwrLvgCeJyDcYfqozaS1pd8K85OEBaq1dCWGNQDLuVxLOsQG90CKjlt8zfU/KHUDGL1 VNecZ7isVBJQQ9qkAJFlnqZXva+UJ2FTZaA1P01vAcYqZZb4wlGt/8tNIR8SWSTntEn33aOMHdr/ 3BUqLCQAbE8I/8BX4J27IVw+4ai762zY8XIJuWSrFW7jjyDC0HxIUmELAhtcGY1PRWn6QaK+K8TR YOAPM7wd5phgt89a/zNOp9vacT//hIbWz/aOsfnc3ee0fJF8RXZV2hvPATwQ3xS2zaKSneIgreVn MgCO61VYLZfKxLAE2SHHCp5n1c4FQp1auzm/OnvISPGhUlQljTAl9Nm2ngQoTgoqpibfdePgWoMn LC9Gk+nkxKbNthuD8q6HrqWkevSyYOqOgcl0AXxSyPiMQVlMhHLAwyhhtIlCBLaZU1fYOZhJaQeI v0JAzV4YNisX/DlwBrxvZn5OE8CkYl4BrSyg0lnPmkHlJ8NON9duSmaU2cUd8YJE12qT13nZ31sp wjLcEx55ZSmnhzcPIxPWVddRHYqOXLYkh3mxZ9fOnJtLHSbYJYS3HSLmUOJYUEIIzUY3ZRy86Ra9 S/2/iUM4hylLYYPJ+J63A8KZWIld94wrOJH1mzdBNNkt4gwEJDjbB7PWg0O8DmRyQHYK6iVe0Myh +T87COtti/JhKcWL9d5gBzYk1vH6VXgVD5cul4aYlzkju6saueCkBMGbNFg2F3xxyqYX3Y56PpU+ B+t41cePnvOe8aWMu25Nu3a2aJmftx2IWyUfAVoSKZJ7kc4ObIgfOVZmZ35E+gcnQZfS7y1wRf7f Y/IB41iQoFgGzB3uGMpWDQHZjuVhhoERFcKRP/GE5wf4VC9uUE2DV/lVzbE0Vwkpdcs0ujYA1rbU y5CZqWAwI98wSxwqCoI9Aq3R1pwuq4++IV3ZiLe+jWWVnx6HsAhdwivsM61z0f3bRRhnjOfHWvSV WDAOaKvQj3cDTCuc8+plhm1YVeXMO02f9nzByScMseYBuefbYJIGY+jqnJx5bwSOag9hNYBE3hH1 Tw3iAJpFk+MhZbpSglZ8pPbA0T/NcHZbaD7oawBZ9DpbLbpnG4EKYMU6Ducg4/ATkYhmFay3O4IG q4Rgt1UB6HkdLHBuzf9VYFwpG7NBqZmCzKsxnb7dwIfc8vDQjLfEj0QAkRTsL3PHz9FRDLRV8pe3 C67hFNCtJYKwo2jfvPhMdEAMmdRRgsL0beTFQI8/lE7REz/hSrNH8xy+M2YHM4W283TRntrc5Yk7 vYzaO1U4vFqm1qISu5DA6uWFknWaKro+B+EA8jpNYpZ4cV8sGpsnFePvzrS1m03cDcg0Ym74w27e /twa91wKPh6jcEsm/herTr5qF4a8tBYNAm09VmOh0rkGLL5uS9LbthmBorh11ZDb02YHZBW230Et 3VJ0A7U8RBEYzArzdLIaoyLZa6ZzFDyz8wPKH5+ioNnhYpRLaCuNd+xA7w9dVqUfbqa/od0X0SG4 gwOjkGK99tihnkWfphYZbRdXtzhFTrsHXMZHbSVvRxVTBKn33wOMcomXYKw93sVD13WbwOexXpeb HtXky3gWkUpFOgcmYjsw57C1O64y64LtUQ2rFRKlA+ZqqXLQUphbJG8rJhdvMb3FNW/vn4XDIf1a U2wQvz1qklTz5U5NNR6tnF6olsRWv7zUmxSoBG+gkBxG2Z/zWyP1rqXnM7No5MPpaikAcZX1n25M HNACLBuXtAEuaxgEsjLUzg5O/Mxcu8s/Klm6fsxn1S9oiSYglrw1VFSmwo20JQ6SmHLGTPgzs4IP 2tkEnsoAzi56KLnSdPooe12VqlHfzKdIp8qzDLDQjSUxmGN9Ah9qZQ8rlL0neus1KuGwQj0JGlpA orA7KIxLJHP/iE/FTQ6DhKQaWAuxaSJY445kGqQBfOrotN7oRGuZK5VAiBDtfGqRPQrKBpdZTHjm n4Pn25PC8Z7TAbe/s52HqV8YSh/9lv+25THx2stnzFOMvKjuV7ljMQTvzoThxzGpvMw6oG13Ol7+ vrCQfHHUyhH/vgFm2b8Hja9JGKolQGbGCR1SvFTHW4UYQ1WGe2m94AxcLQi16DNrxP0ZvY2JqZp4 e1bQqSQsLU+/z0Pxr3c8aCLfRCKX6LquXLQHx55yTLctCiosbZwxFImP0WNRqopu1P8cUCDVlkpO LUkupUoEGajaZUC32b3AfUCajwXvfxbTHLBcEVxUC0en97NRB98dtbre9qiMkGdK3ouotpgfO3MP fZZO5UTCTZngMA/9qTNB2fJ+5qY3uN/nBKPlV5Pkz5LWAwgpdDoH7cEhhMCWOKlClG9HNcnBcft3 fPUg54aXhPBjztRAbLH+DoMkonE/9Zs52wUWg9psYjt4OV9VFQLlSdmP474Mt0tmFJ0wcjaYx+pO RVddMmL+rnoe6YmYxyVuJC13FiYyk3VoZT8zOTs92KQVD7ZKuhfvvE47wdnIa/jJ12F20ljCy6Pa TJ4pBIXMq74xTJoOfJ+QNDaG+E30oRSrcykJ9PfpjgLBchuD71nocf7FeFRojngiUIm6U5bbDwde AxJRpcxRDHVwNU9vK7WZV/kK8fRDGrcqsBnskZXqCrvzSgGmEYVBFPnYWRzfAfBhYh5OEjgEkzeU LoTDNNWF3YiRA1+0J/Q7l0WDFFQrR3hQjbHgkn+g2Y8tZeqecUD1SC5YKLSeu6cF9YY3LwwaCmui xcmF+Rg/ERezeP5erubW+xBA0G3MNqionsF/rwqV2ZsIbv5mGypz756PSwnXSLDWxahi5YJQIcQR D9uCioexl9P8JhE5ib0gLx/8/kAPU+yF5UKzv4NKOgUnJaNKwtz05nRLC1OUJjV8cs07bES9NiCQ aa4KoETNCCAI++pv0wBYdcp0kRHDDvhz5AfSa6McvPuz03vWVTBONOBic6Kd2q9i3xTBr7V/9zNY dRiOd417l7sdMcgIz+Ey7423CWWPGUNQ3nEhY2xR+s+tQFZb2oIHjaL+zCbnjtZPfTt1zPWX0YdZ YTAUqQRwLRjvWbVumjLx7pjvkavdU1p+03TLdK/GwbnWfhG3EJi9Hu2mvMfKeZzpKCDurXdJ8vDB XervxiUbGAlnF29oxfsyAcvFnJP4a1PCoXPKFXxPIVZNZmw0AdG8XQX6NCQQ6efdnFYVHoQKQZt0 z8diMrhgZkxsTfaLshAB2CDaolm9KKp2pRWJ69vPsiU108aKxe1Igc/e+VsYsUv9iBLGvHhzW+Du LwsyD1hrYz51qG6ALVDqhS2PWa0CjlTXyjSXf2j4QfiUa9rkay0TYTLybVLIt7/FtbguayGF9CZj fZD3hVKHXdf0cr9XHep2gy2CdaPnATk6bzQPnXlTcyBMbMhX5rjhQujtKJJ8Q+XBwrcYFvPoLkcO B3/k/bORZ2NBwsXj28s7fWH0DCjOnSyyKoz8bB3eVAVoH/kVO7kC+AxQ2DWIVvsbGjH01aZe0Vkl LjNZ23ui7IcGoxXSMqmfd8+1WdczlqSv7XZzdFjRFghYZWJOxoNQfoZor8ucFEWJ3hNujCjajrMX 6tRQHk6ZxQ8hJjumOh3ZiVa4RSewrdSkgLYp6WpAPeuxD3DyNRD5VKxe4P0VtbNz6NlMugPU0oCB f/oFvhPxpC7NNlyfaFh0BuDzcHJS+qf7cjswVn3jMRL/z/pIltLLTb/2SzThS1x0Zli8+azUQCJK 64ijVQuHwS2AWYEGVmXSW2KVVR5t9wIu54dmhOP+q8RqZZg32GqwmjIBDoSHn3z5Z2lDGY3cso9M FkeoehzhBjWBRhFUCsgqdxHdMtHtA5Dfx6JytNOv+0QWd+iWWQQpbUQGo/etkXJZKy+NDZ86BBMH SQlNsOQF+0VjAAqv9fkjWK37ZjGgCNZE8bWsAW983imsRnTKFjYaILiu1qxV5BVNDI8cxo/mlv3J xpIDa6teuct4Iqvbu1gJZhFVCUETtcLorcoskywPB9utKYHLd76MsZsQkrQ09BD94wmWLMgUsEHJ G4XX4s7V5gv3p6H673dABXLW+TzKg/FZmTAGlkAX15+rA4/mlx0UjDxXtlVadRe1mJlFV1ELt0Fh mv4lVL2gdo6xWZy5LASa/thJtha7JhVm5n+FBXTwuU6Gj5oGL5Y1qMjb+qxWqZmnt1TKRUSXsoya swtwHY88jU7iBNg5MoWqxGpUQugNJpL7A28xStkWoVlXR2AO7lW3NlWUWTUG0xf9W9KrYOu2DPdj jFKDMwQ6pp0tHXMfsXYWp3dwxb/zTb3pl2Ha7x34Bkmv+O8+wMxaIw0Sr0RvdKRTjRoX8rcvi1kt P2xQvAcTCN8O1EL9V+O5lpEConnu4J4dzLI2uaVhC1kdOl0TV/9GaQE/KItV1XBi8BplP9z4F5gG eZ9InqWJZmBWj7poA0+2wHIfeP6jygRlSed7Jkoodl5BmqhJNUK8KvYR5F0rWCCB/iKI4dqjzptC j2y3jJHyaNbAhKvBZzrTLEgjSFrwMrCZeWCJMYK0+jCiUnQJcQhcoOBj3U9135BECUU5LLICRn64 DZdu3MAJszO+HIbsElj3C4tUba57/ggM780GP5yWnx0w+je1d4htRWbur7IifR+tsRyyTN2a0KHL soAbDNzz0QKQZ8cWld8cJEZK0zSDkDhcI3FO8LRoHPRnfhCuDtgt4Pcfe+6e7jsyFDQCmM9tYDK9 DiQxtL9oD/Id2MOi+LeDjQ7ifX7NA3+m73Uj1KsWWwP3YRJ0o/cJBh53/OpAB/8+AbBnzuGKD+lL O2FO1xO43Y9t4is64rUzWsileiIHIMKr/k1KrbkquU2Yi8/tRZ82YnFGJnDO2bgeBEkre3qSLhXv /aduExGTp0o05YFuXcx06LeeaMibfPphr/9uXu6u2dPKCvtKo+TkXe+WTrxsCnLrZ1Cuoia3RkWk WTrqJhptsCxONtdTO4uDu+5ioPcUXEzcPt9oDwCYgMXOnDDTW5fIcEwHwEUQvJg2SSo9eLw0nUN6 NjwkAjJgzulejjpDZmjiXv9k5DsAr06p7wpN+WxyBomabqrUOv5AGtl/OetEs6LDolEyvt/QsuaH jXrTmlOUxyxlQfktL17iWbmSif4fXFyq+ne49Nnw0ShUT63UfG2+GTPNTn8OEes1FUwlLWZgk/6P ias59szQkiCssDf/OrQyHc3f1RTw0vRBwOFUA8A/4qIBQq+O/ViXefoNC/8R3cI+JjtiqWWRJDVf UsBH49K8SK50oEpQUMrQW3Bbw/ZLRQHwW4p1KFp/Mdp8fGatnTY6HEkFIFQKuPBG/2Blvne9+/FK fpcdFZB2FT13UZU+O9gLTjDcmPEmyqP+jKN9DNO1siP+JFou1XXp+uKYoX8pWAlBaX0Ij/TLmyVl gJwjogiQu2a1/37bk5ehtMFPWTmsHuTRGWReZ2HpJZe79AS2uTOWwoP1KlPdBrA/u1vrQHWfhkLB u+/hhT5kgIXA8NzS+djK601ETeqXzEVL6LXgv7lLyyv9TfY7G0b9957slJ4ot83uPW3DkimicbkV MBnQMixFXd4t+VsFJgiprE+/YLwsD5I5Mu84Gij13EjzghySu/B+jjQHg8Pe2QJSrJUIHWbTATsA UuQ4byKa7G6UpJsoXFGii7to53NIqaA5I8aN/3+CQh4jWmXXZCLNguaIQAi0FE1pYUp63V9Ewdg3 otiSPAhtnryfI10sUqzDI1xvvo2s6OtIMCnMfkepgg3AALKQiFcmlpTHajLYkF48u7R11kV+x4c2 /GMskZ/xvxeeqiloTkUxZtAc2X/c9kJWN14TPXgbuAPNo7klS4ZpI5wgZydrJygEjqc1CxZrzv2z nGYL0G3GUcJQXUFVh3tkf5AYfP9Pd8IvB7iFonwSj8EIDQdIj2E5y+TQXsKpdMfApm1LqX6AdwUk AUy25YwwbSBFimtSpvM/RF6/Q4fZCyro81wCsaylFMR5X+CeRy64xou8rajf45CYHqpcF/Wwnpdn zX+oBhYDQF9VclND95Un4KmtHDF+QFK4DWGGzpRG1+Z55q6WkpcxmF9/Z1Yh9ryQRxGt1QsJ54CE Sp2qQQu0B1yDb9gJnqEz8SXlQypYqNb8ojWv90vNVwvMgRgN4na3DL06BDEZiV6J1x+8q/4Kniil 0Bmvfn1H+YJ8n+S5dw/MfAKHUtoL4cMMO+YDrtj67+VjtqVT1YRUuGHEGRnFNqBhkp4r2H58y/6l Kpt+t1IifUlrFljHGSgZ+wfHoOPasiGvQ1XxIXWqJcjgr6YCXvjUamS+Py3/TZdG5SUd1RB2DkkV YBmAKYOIftw7M5Le8F7nbPscIVtSK3s/72oq9UgHQzFj5yW2PSaO/d4/tNgaU34wWNq7bdkcq37y 18nQpIVVkwroWfD4q5Yd9gOShmxeewBO3lez5j0UzUfB+v41eFHJPAIr2GrqeMJsEXd13KrUhbGz 2yBReMaM9bP1PXAMPWWBFEvKlpzo4De8belWtZx4/dWXq49dvj9TSJgn+uuIsKoSGgfaj+TiQlyH cA5mQzJBrhMqyMu5fPX/fRpR1wYG9tMO/fNx2ZPNKh9pCNgTPKrPoO2nYt4FOH0RCeaIZstX8fdL KzMC9Y5lX+Qvmor1Iz5uLPpceCA/4R/RnhYtDPCvILWRUlKRnM4eK9CzJctqtAdRw4RRlodBWEyK TcUpOZ/lYh7eTlrIfFH9MMPJ4/hzrh0zSrYaT6+ObuFVi/mgbjs+rAcEbOKHZGxNgfye7olv/EdZ 6JND+Pd6il9e9/diVUnKhUPpxRKiCfslP97HH7uPlHMuv8FLWbNGDSO64F3rtKgNnuIVT3iW2oli UM4ymY9oVbjggRCJAP6B7fjRoQWGo5ZVQx83hJyf5hmyZJODAjyScr9t9G1bVEI8CFG3tQN8shOk +kufrZLjAyc20Hx1sCvXw+SwTthZBDXog7TZ3P+JkNrL7npUzLUYpNFDu8lwkt6PgnCbVrF2OPlv 8Mn0HObOCPoE2USEdV10krQAim8lyxFS5YXE+3PHN39PHpLJOT19YrFeswA/StHttpUDCjZQQkd7 uXmkQHxQurq4kdLskA0OeUrKUYzSX8aloVNp2i8dx+A9E5COjWDaRq7mLQvwzM3uAPoQlOTcOuUv Dg/itiLpELmslH3Y3L5QhW09KaPyJ6iU6CeyCB7s+GqDHuZOb79KnjjMGsmvPzGJWA/MgI3bh7Pj EtcwD3/U5ee8n1qfZiztB+UeohUrCTRW2AqdaTxL0Zjb6nGxYYsDTEj/3LdYnyi9glzPTJtseXg8 R6FasEaj1f0lkBeuK2cw/N90pRpHCP+ue2cC/UzN8CbQ9l5VRfKAeeJ4C+HuL0QDv7M9mx823aGy YlNUddzhYB6IxsyievHvCDdpADys6WgCYDigtDTn9friHMYBjsjcDnDpyzv26JoMfkmUYLz/snJl EF52OYKmNkqgbAnbldbl72dMDRna9vcvcZE1tLhQgTNwnDBstkY/nrLk0ZaJ/mOcY5PJ0wlLG2RW yMnBs+xsal5jvRvie2Qh+Kkmmh6A9eFsHhpnXe/7ETWEr5WT8154BxftkX6UgROrPq4SCf0kbfR0 +DWqM1k4F6EqVFq+PfXDgy/5p21ui9YKHZw/YzgmlORya/OFiAS5x53GvqOhGv6wrBmPXy6rZk59 yG1E3XLt27yf2LY1kWouZlMR1wn7fwga1hjyF0rjpNioGo1Pln4W6lfRwIz7CMx6Raq3fuXAcRqs Toq6wa7oZ9IsBefTEJos59dv9FbRYJ+fOdgtub3XYL5Hr9Tg/dDvffkGKAXGBXQR/krrquWPt5E5 4Q/6L5Xeo2M6eeztPlKgAfvs56fLrtXA6iFlaQhefEKopt9XHS/zYoZe9zpVrlEclQiNY7yoIJv1 53LAEXFwniqYQDm/4rxBVcfvMYCn/bH1UTI3LVcJ7M08QaurlNYq+5nK1SVlX9l+hkbBRcYzXlSA sCRdoPyxUxL7NS5YqL8UGiGp1UtCBvg897b+E8LxTcxf6H0mCTfCboL6uogXrDcSuh69v0lMImLS sv4C8sdfZYgl6XhqqQtgnhnzu3SpzUCcJ9XgGbL0tSJ4ivxv/iE80YdMiXtrzdeGrAil78eHar+A VM3aUT2xgChqpuCxvH6oSf1v0bWuX1Dwo8EXL9sNlT2o6lJFUWkPbkv4Yh66Y6lTpO2BA09p24jr nrD77/nymElbpgJgYSHZ2w3o2CiGt6JX06PSYfSqcwNVxUKNYbC9fQCyZHDmsH4Yf7ZY60QGTFpH uz75x6gMraGQUCz0u49kYIG3K2JtT7lgMRE3KOYewf4j6cBEFUKV06J6wCbpwV0Kx6LvUNScSpj5 roqCCm7FTDAUujOImx2+Jsi+YeAxhpQPl9xQEakemoRh3LSkQ4yJYFlgeu5No/3BEDbF70WVuZGr cYTdadl4CWLVxVUpKoJwYZCJsWOtKF10xp/BnsRIiQiLUrz/nEOqGiMzVrZ165TK/OypYjhXJ5W/ xV7jDQtNHxu10V9qtsj+CJwd148dpabd83S5NZIQ/eSj99HSaktwrkwYUJFBnWWqxzPjUVBcAemY YTSxbL7ZahiQn51WjjiI5hyRrOJdSE8G9+Q+5MNgkWBVCVysql/blcLuiDDgdKoxd48rmsA147DA LYCJd48bo1UYf/IXwsOYQGq0+k3ny8DIPZp36HKyRIaQEJpF8g2yQ4+Vme/ivGEcVdRcL5Qk2JTb wX07UfSrmCnxofioLp7ET3OOfa1R0WS33TaIIPUk9G9LLeCsKorFV3uLaFRFHZqLBJcy7WWZdXfQ 9rM3TNtqsLR77i7vp1cqr+4SDzYWdXkyIX2EM+0IF3aAQT2GhTrNE/Pg5FRfoHapLOdSANIOyZBO h4beKmPIzfh+FA2mCL+N2xJFxVU0XycjCcxrqJ87gGSNU7OMjYXq3ZWFEe3z+4lSu1ffAsVoLIkC cOMM8jzBLbgmkIdxw7rAT5ssbwQLw77L/xzN76VCWU88q1i6HlwuGT903HKDycro9d0n/VmOuJ7E HVIYrF/7k5EI1c5db083jBvCn0ps8r9okjj+155Zq7YM60fZpvEP69siuOSceMR46AbHTdiecjrq vtE1TAydH+4buUu2XDrP+emPGsX65i9lj40ppQMLNFjSe2hRD3nHZmdX1tFClpkjgR8H453HRVKv 4RDre5XYNTDPkazka8lhR1z6HxZsJlI+A0wIw6PozKet4dkKYglTg1LANCJxq8tWZafQeDCvGnVm k/RLCeV4QSKsJxi5Nl+XnBl0C0qB1rKiDne6nrLGGWv8sDAnUkJrJXPYBbK/gQYRPUTeuQtiGr88 2zc5tk+hFlh1sNu5gqXPJt2E9XPrMsuL5k2QZ0L65To9OTMc/mAUQafQEGCC6AT7VRqh1tMuzCG1 bh5JBxDXXlxUCrNyoIzSo6nb31TGaqMxW31QfACYlGuplHHfFpCIVt/taI96IidFRJfSeBtl4qba dwUxerlO6CB2Pz6arwrSOigTUV8JUT2aRh1m60JMTpyWq5mLqrSgPUTc06hu3ILU2ECRbYBSW1YT QHCM+mdcmbmmUc4C0vkyxZN+OvL7/olcBd1sHEjV5Iz20QUpksTEjQu1Tmv/enzRNruQyLo6BPM0 c6iIteDhppalfnlQopbXdgBVd+e557SBA3XKCvYG/HKJDZhbW3bfUp1/DqDYPMRh7Jr+5tyPNmoN AK+jG9wPhNuGhX6qBW8aoJycaoTXjzj2iBlL7uT7THh9l+H5dSu9QcQnZUgLUDjQTz3au9JkyJCq Yspo5vD75P7dH/TKk6PueRh09Aymc+/2JtN0GAw+0H2wGlJij1a8Evz15EvOfmzBZ/0RJw6aD462 JuoW8i3c+RGimtlyrNI72s+dc3+pF/rmmJLI65wzhDG+XcEGTGRHCmDfrtHXTD33okpRORX9LrZf ZMEBqITTvG8WX03idMhG7Zqq3RlEdVmy7POEJ1Cu4lsOePcfOmhpOhDsS1fHN9LxhSiAWr+tjmtO qjByPqxsLMXUYWOxVkpYoLGXG32LIi6kMcLXlg06yGmIk/WwTv9l3ZRiOc1iBw6WyiINPDOdRchc 8/b/9zFfeJ8knR6Eb5qrNSXyjmiTu/AIeiMEfd4fJ8R+xSCapwUEUpozGmwZ5dDka15Vm+0BX379 9EbrgEjMVCxbtfdYcrMA6agnreDs8bYHG3fgg5IyvdHx/tiJ4+sH4Z4bSpDtp6eZ0IT4+fORH/Xj NGLXoPicKMj3S3yKEe0dlvGiMXq7VExMNtq5BXTNI+s2fPRUJo8wCWP/vL/mlgo9SGh/6EYryEuQ o+hhBm6EjrayYyzloBlxxJXLli2zt7HXXpNoSHDLrloqilO0aqCbFJqLs1UHFRUrH8JKpd8Tq4xZ vAl17tedYhn05RzXSIinKgAU0Bwxaq2Tz6wBD5PWg8ehsJW0JNxMcvM6UfeFof4Fh+h0RPZ7Lbzf PijbW67nQC6phOSsZW/Q4Rkp0XULudGOJhlsIgr9L7W3H3qg3vxEuNoPyABBGW/LkK4YLiPfIaKu i5mknih4ZYJvTbKub71kKg3xbF/FFGr/W39Hqua+beS85FAzWGJ7f3QrQfuOB83Sl0f2ealyX6WP 1VBZcuMr6pacUIDWLnLeRoausKbGiGcBO9T4UcXnp82HITPe5yle/hdXsSHi5MI9X3I1ygNhhbm5 VylFJ3V4C0nmm+0b7MowS2FP/c7sSZlfpHFis/PR8N/aoP0hGTbcHppZsmZSJJ3i5YNNHJQyHjMz toBFK7MGC4twOovV4ynhrjl/ICrfGDYeVW6di+1wYX74R+868VayLj4CWyvJ+NWmxfEFb9UUUW4a qBfbdhvF1m4rJ6ExbHmEyjd5nSIdK566ghiVKRvmLjGnRQWxcMekNoj2v70IcXIlYx8RPyYk09Ea 8Mp8Es8Gxq8RMLJE79UVmDXOnO1iqV0yIQ6NZDMzfHI7o5rjLnVLYyIhx7O5i2D5FVTBUS92QpQP zisO0d1n5H3Ap6zic4JxrkXpb32hWkHVCso8zROWarT3NdMzZo7NoWYEF5fvCp3RqVU6/ioCqa0f 0vnfZ8m/07l3mH7zy+b4qU38wU1ec0gBYBrwj2jqnKhv4zlpjUtk2TuuTKm0oHB/Yf+7S/T2tZsx Y63ElBqTrZ4ZiWD1U1MZHSdg6xRfYkL/vozU1qOkOWHeEDw6V1oCZAPvREHINzPiQpJ5QYfr+wyd JxjxkfACwWb6TbymZArR707BzMGK2CblO5iR4xUOGvHoWrOPkX+7o9AJpZDgFTGdTfT4K5eBAhDG 5KFSHDqfysl+QXhooK+o795a0EIrKdxwcUng+tpmKvCkcb0TNigBkomDF+Q2EKn9BR7ZjLKXWGmt fGEsJlwcIu3VUSlj+m41XzX+x2auP3z7iciBBn649fVculF4kshR8GHXA4lBLeZLN4J3okWb5Mb6 80upCur9VxFInmd3YUvRixZzdDsBfBI/EtLfUp2eeNflsRYcscy0BQ9ZtEFDp459BnjiqjVwkPUR 1krlI8XVsf/TrhmfrcOVuB67XVNpABW0f35HUBcTUcBxvYD8aimhyuhmfKV2apDUozPW1uDLf6UF cCUD49F5Ps4I5YULZhbYKFn8hSXRAQ7r3PV8tgMuRgaBIuhXIlrH4va9/7uZ+XWj5HEuWZrxiroh qBa4YKhygh9WqkedOr4ipjZLiStlrqClhp8UnUno6cWjTobL4wpBCpE513tyObcofuv7wEzD/OkJ hJqdwHXTqrv0t7bTn+orAku5DH55FTUDLYw1b2fbxSa/dyT20M/1zFmfNT3bchMfbVqmJaW+kUt6 nGwms2Y2JmA/LZ8mLLXQ9UO0YMX0/qIbUA1WieQDkFi5b8Ot31djO/rhV2MUYtsVRUkxMtfOH+oF p7tpG4LI+2ZXISDGx3h6EvE9o+wmMVdnAfuCyC7bReCv0hhI7GEpdAOzcpdgkXXuN5G/4P9787cS H15EVRU3ssVA1hHKHvAORaLK/gIMrxhFImjZ5EkBOcdgzFJN4ZmKc7p3bYDM4F5wK2r3WoptkzmW EF8uuG88B1Hyj3ESlq3jRcsWj6e/h/+b/Arw11jTidHRsEQenSyAZst4C5ibZJgc0IvWAcCOhifn WEIL3vntkROHXV9ktHlUmuRmHe4riS/DNjaQDGEYCIgN3x2ZsTaY0Rv2PkQ6Sdm+cky40oexrRCf WwP6xnqNtDme2ySrr0dR9YWRe3kQxsC9prtZU502mYPgtxxRLRe+ZRo1ASkHdYR14/8zwWZiM40b rv6hcHu09UizCnFU/0fEZ4FcjYppJWxuPH1uNDtEiUBsqxVoFrQk7AHpXauL+/TxolhvnNJ2R5RQ 2ZnIZKPiG8C7vJA9gS1vt5AQH5xjrD1cJl/YnPdchHoOlUUi6ZHtx/aqGHrYMW9E7pBHZTOXIh1B gmILbgtvjFq4PO5BhdK77l3vqWObwioIZorp+qQzC4I7Zre6Cqpa2sMId4z7n5+G14VA7WdvzUDH CLHcVoBI2mhhMHdXYGEr1DZKhjvQ+WrFp1nhJzOvc7RPpDXt2oaYUjst1/lHjPguX0+BjBLriRHn VVvSGlFx7CJoJB4N4YTUDVzbO60eTMCmj1PRkqpe315nh1ky6l46fD2PJySLC9y8KO+bZ5Cb7VWk VKZlVdZHIjlxC4JGk957sRDZZEPlUzvvfr0o5INoRXPi4uWCLXIzmfa6DICIsO3w8fIJ0uXuYVab 5NFM3sg900c1LgP7GpmQcSzNJvYYWVgmmTC8+KpZ9qKBWEUUlwBvHWe6PgyixHR/HGVfffSbdGZE pNYt8HvVkcSFTVLVBmcKLT3NwyB8Aqk0tXswpZ45302+6CrqD6I/Yr92B+U55b1M6wRNCDjh/ncw qsyOTSSidaEfR+50zXDdIiLkz+0yaSxa0Up2G4MiO6nRONMw+n9/HOw5tHormxJq1AGFycOAm5Df 3/YUXDDFVZ/CUSJJ6IHyTvnkDW3ytCAA0R5uN1gou3jvfV+2nr7LfcwVnQ/UCHoLlKbJeqKlj/rC A0uiG1y4nGS5Uju5Pe2hxKTVqCTYk8OfSk/lKthBq327P0bHWS6hjBuBqRwHoGU6COSwoCuYEsQe 1XFAduPr4zvE2KX7Z5MbLskw9GIHrzQPgJWhS0wWzbYi3LtVBvI46t4c+GKpPb2+DQ+ZOWUvlBtu 4nB52dVmZGo4QHpo6BHdAV+D3meeIpbFwT69Pc6Q0UNCV8rWomWUti3vsgNKhiXOx/gyNkdxwx2Y 6pGcNkfLIoz5h1M1zct+kbAeMehr+Y3SPY0Q+BgRyVlIq5QovJwUd7P2Dz10o7j12J6lslBw0O3v xiK7hL0THXf3LXzdGZ9vpRtdyaNuD/4gC17AO9frfzqMU6wJz/Y9QWi4D1RsAdDOGRalboWprcAo j/R4yhLZcPuxwXC4/6fSefOt7mtOPvLWXQd8bTJzvH87+DbK4JkG2bCLS982E5kcoe327rVaf65d UOtyAyZoSoXHrCEYujEnRZRQ4MSO4P31LpqqOx6VqgPpvdomEldQ2e/Zq00b+3cCoHenDOpxC3ce umxEs9hTZMOj5YbJKVZfjhUK3S8aiyFc1DEqdTTgln67Bs1Vi8TlZD5+zfexYt1Phuds0+9I4whG 5cgeXgLXl7HfkI4N7k2ZftMerR1pjFYOsPyKQcrXcvz5sQjrYBCQmj7J0rFolcgNmBHznADVd9j3 eplZR9Lqmi2gnRMoybHOnEkjO4XoUVO8k/ztIrSE/kN2b1xMOY/EGBwIErujRP39hVxxny5+qZ1j fSHzYsetPyW6XjkRNc03T8pVUYcN917dNXgnGENp/9IbCCSXnsYSAYzSP9mb4d8hEPh83FKvy9r3 biev1iZctk8Lv4D+8kn2MFgC1VVhnh4tMF1qF/MFKyybnSRTMPWYy3te73leJzXRp6D/h1NYXP2O jlO6jz4eU9HdkFqgt/9StKva7PS8hEIuOpArjBCVqx7z4faHpUqemIUhb6icUzHmJ/I6f9A3Nvmy vOQrfWAU1Gh9YoQOU3OsnBgtEtfj7CBdNXHYzntF2VXPewbczXax4lx55t50uahZcZHhNH6JNUM9 cLdPIzrwusLsrhXJ3OKdFGqVzqlPgWdnr4QDOLpqm5jT3dxa4E52dAh8Cw5we9DZrfBF566TND2t qNh20Gs2en2dwnBlYlMh4zpCnnTux3per9E4aJhAE4BRhB+ISPhYXH3gAmPqxQ69dAGwEP59txhE bS1hZneobU68nc7cftVlC2dssrYQ2Z8Xt2AOnU4Xaiqv4lJHvcKk9/5dXqMStYBGu+r+CIzZ4OnA z5CLOuIsFT6W98Ob5QXwwQ9qPRD/7Zz4NwgdxnJamAaIS4gZk9U1n0IorD3s1K1NUmda7v2GGUPs Nvw+qqWAgxMJ0OSdbHNrsoreKrxeTMYs4wca6Dfo81E9N5Y5Q2Mhi2yvq7h/Q4ZCK55qlnLlX64r +6Otl5q4Bi5BauWrc0fails4A63dUfDrvnlMbWGMOkXZa6asnWjfpOpG3BOikMPKeUz0xDOzJ796 19cfZFnDLsI07iS93tjg2chvFPhno/glOdKXtw+9UMUxmYb2hjQK87cC7B6Yxux7DmXJgCiBdNE0 HmmPl6yFxiph0vb3HOCvbtka0XtC5hGmrlk9idvgTjmK8sp4lFmyiMqLGG7jyY091PyRPz0ciBL2 3mJyQhbJhoSSTVsQIK1fqEYbsrcP34BVhLxmtUCT4sApw7PB1D6J4M2yaATJz4e6rkIiHHEHgJSd VQcwmNt1kTRN9BTAuFAIDtws0G+iaJ8As6FNiEI2DKK/Vb6bvi1RiGRuWwbpx+bGvgT2+UurtUNc QSk7KsSM944ytKx2ww6OnfRtg2JsJ9wF4bSReNIN9m/wSk4f72d6YmZzjlkyQFOVtKRo7GH0OLkq MXDU3ncObjGFpBTeeMppIq/z9b29B39bWmnFUYkY2AD63mXii4CY1h8Se8z4h7u2WohAwKIlrI9B b+/yMEETJ/PpuetcSSF849r+vd04tPgyQUWcS5Gmq7hqGBYy3LUMFOdwHSbxlCrSFJE26m/rOmTR KcDigqN+VmSubQR8QtCq0PtaTfCICOeHclsArWmKSsDKBLKvIaazbIZJWzbLWxD6MRsjNlcDrehr GAyNPVSoJB0AeBsi691uwadoNSh/bYOHJeknc4rmx1yDx8KwTtqn9/ENggMiMQXxiRvhdYnUHLo8 ZEaBismdUA8Gf3YqhYqpZWBOmYCQqvehBx4FUFxOJapdXwt5LsDkiYD1oGpgTn5Qv4hLvrY6WGWi ZdqjIFTQNgoLkpKCvubRBOsQc59+ghhqSfgIK05Kull+SRmYMQ39TZXQAWXJBQstx5287GSX77To x0fd8qvgAftbKYE6y/oEbA1OotCB/MaUOUctusQqbgmWZbCviyFL58n3Z+PRRdBeFRsdpKWZwgYw MRpkdNaavF2rQPpYA3LbTIDrM8Ip3OgK0JUJZUxcwi/oDyqfzBbzOnQbajFd/ARen8QM+xUYacEW zR95hKYSiefTaPQtdqmB0dYwbqwLtryynuF96yXsLrJbPlVOAyzYnfwaseMr95opWammqHP7ZUAp rEl1OgUql8PbgBSZk597mHdmLGRm6W85Dw+g11zuIRfGPbsT+186G2qibi0B4zK9D/12zNF5o071 iXRG7OSMNXBOnMkjxe8yPhdCV0NtENRgkxbgTnaiwozK+Ph+i36Lh5pq2r859f/ndeaHvUgJpi+B Vdeww3hDhqaLqGNKTTFPVhyDuvqsuquOJwqh+oCA08DCm+VPM5AbVOsCdN67m4ABhh/Y/xDQOdfj yQ3gPWEg70IJSz3sL+labepVVPTa5In6HShvJ5PsFz+32/QbBW/PL0eCr1UeudFvq/piBs13jzoI o8Yg0awQu0Izw3ovLpZl0po88VswmtQjBbOWaL8PyjkaEmyifZrYXbrsThP/hv59GJAj6wvT58DQ QCzpIMczDQFHMIgdOaxM4KusShodYQPCHIF8O7GqHpDMukVDvOLqrR6zr+wbmWJHU4n5IR7MsaDT WyB5NZcocaMd+yxbttXx4mLLNHqvMEIwX7dRVpLBKJnA1Q09sBE8aXjosto/UYY7GV7NVPD8vWyB DDL8dRGByXvNyE5PdwNQIPA9W15nluTrSc8z5o8AmGayBqInhHUP6M2lDEWgZO3byqa6tx3NH54v lDaKNoFOC2Pl67NsoAt5dpm+LtcsdwtUi4mzrNPcE5VRYOA56zRl1GqSS2nq/nX+AJvmNIMaG+NM ONM2Rwd30HYt9LY1MKONG4hVXaZYW7nZIkRLns+0ry6gwdrvd8CR7DsTnlhNXVaIEcr21fhYg4k6 yFpWWYqZLvDxICas1EB5tRPb4XHPhkW1+5OR3SeqB3H0MPwrB+/H49UQ46LQaJdLo6e8qmF9H9gS o7GI/Z8e9J3fd+3EtXjw7PeL237O5tz8J7rZUeM0CnyY1lY1DF5b6GRQv2YWOPsHQxKIERRowG13 AA9eg8eDajcBZL2KkYSs8M8IdA1QH/rAoOyhUiy6RSGxDmecEk8UOsUu838148GTlNTHE/c11sY8 4MUpJVneOm0u0k29tD3iggR6MnSik8T8LkgcV9l0xYNq4+I/qYBxYV58TNwFCSPqouFftnfzWZ62 taZ3F4Id2DFRB1nhJobzKpV4tv5K96k62rrGchJ05yXX1llY/IQMD2JR1gZOPDww2j9NzuTPW0jB 5CLyrhQNc/J6NIdxQi3n7KTMRPu7dmg8Ool46r73htrVeob/n02pKwmYZf1AQiUvwhieSx8+Ti7D RJqnDOgqo6G/zUQBMchUHJyazDuZ/gKTJXcggGb/jXsbYEw64xVwBGXrI6PyWbjQVxDe9nZULzks 0xa7qmgCLuHTdPBSXQqDQbLef4KVc5+Ic6ZbFexmdUr6sUcajgOCO2dsXn+NZ4P1wyIdvX+gL/Gl b9bt1pHzWhqZIL3sCobilr2a//4o6QIm8PxS5c9FdY3J9+zoT/gu7nZGfvlCw4FEHXTAFbnmsu6c tZBk5/IUCXcaXs07JUuUceUafDBuCcgVUN9ksUt0KZLq1gbxbKAbQXS0Z+SBIoncQpvtqRkrabSs 7pf3UV5FxzXU/rKQbPQuXYDruH/1QrZ0/ij0IDZw78WfEbHJQOg6z6P+XPSUjTOi7cIWQF8gXcyD pKkPqE9/X+YWaaXbdtGY7PDIX5Yfq38PbnmGcc5CviAhV4kQbNPBX/Wq5u4k6vwYR9Djw00/zfl8 9Kb+eLQgpeT4RuUhzo+l4jtdTfJ5h382LtmDfrJ6fGTPjp+HdSk/socAbFlc01wB1SDuXapTLQDu j9ZEF4FNZjkyq2DRoGHtG4dzCUtOvPghYBLQJXMvQ3hPz9ToC95aZBtLuJ9ozSlb9tL6tUEdQzBN BA4IiJJpjMZPmr4WRX2nntcopfEmkSByoUm7St+zt2+dzrZk+z/gRZWLGHZf612KFtBQLY8Dq/y3 Wrp+YsaZc8GRnpOqZWk8d34yS7dWs2bfvJj1kJ7oUVQ/jbkXSsy2NanSYo6rps2NpiU2HeD6+uEX SNYNIB3BxZoh6S7ZIqsKzhFXrIMoUgn0T+/pLR4neY0wV1Xhe2dbQRSLuPnwgbSwYcCEbCyh68Pf g1rHLn7nQFGtw/3fKn+X8+6FxDQNdKbesRjWOMY7JqjzDgF3X7M6HRmjyoTv4qJuXgo5BH7/b4kB CswcGr+EjkhRlBTAlR5GSc5KMewaQhWtLyQ9gmu7oeaeWX4zt6LFLMOOpyC8tU7zzR5ZMeOoGKcx q75lYUu6jTIRY4lY6bMZ9KvewoGM3KKuJsarLcDnCtucuRTGJr8/D32x7xJwiPUjRRGWP1+ubUD+ agnGlc3jQ3iORD5DZ97l2N3y+6gtWvo/LBk9YQieMYzFpy68/Ks833C1PEocQEGADGDM1aIx9snK 9QjWdLe2e55+T8SG/6XaP/n9jbAB1ZJmT8xh4K+7PsXqMiesKFa9LsIq6GCzoylucYoauhEdLey5 0GATHieolNHFWq1PS91c6ihLBJ3b99SQykRSZTtoHVzo6mozJh9QJGt1h0tE/ZS8WLu1sR/n39x1 OBDvo+HVVCjaGpDHCYx9KE2wEmZigY2RxNTLxNsOvb+R9tMyQEfbkX86+Bbe0ZmiIQFytgOO3bBt 4tR+Lay+eVuRYzxuXtc2mKcYRxAc18OZlabTNORTDKBYuE6Ra41/ZjOpBV96RV7vc7qJ0YmIwnl6 NeyTohcuAiyHZ45TUqVQ957hcZORPW2tUChdiVcSTpPCpN5r2T0wmooTO+lVG5apTTjk9J2V4vbm NuEkV+AXd23K+HJ5BiCb+G9VAZUnZv785K4cTibPjXS8RnPIuJoWgpZnHlOGwOkkAxq/sDcRW+YU vRzpNE7nKNaDFov0naYYxSGy92RskIYwRxI03epe27MjxEJX/8uJxU13vKRuNk4Pt4qlbTvU5fB0 eE/X1WP57wjkDPQemBl2eIK0TWlz2dXaz5K7M5gFLzCM9XR1Me7a+JNyFOWSM/I+O1ytdizRhR8I M05Ed0UgudW+L4EULIZgq51HKxzvLITDFysFUEbx0Ku8AqjHqJOoCeWtVzZV9/TDZmKf4Kts1n+A 6gC5L9dHBl1Dmx6tCn6Jx0K2gSntBsE2oACXiygoIFQIRXFgR5qorBqt70Hf5wHCpE4UcxzQdg2G oBV082ELO9lo3Oo097dLdcJ/s+Di8iGRJ/KWkkwx3c8R1/RqQV62t1XYcfbDDxZPC7exw5HfMbjY ffj27zRlRTIxp2ez3ov4T2WpcegJYKv6iSDuKFZFuzpE8c9FI4hwdw4wGaEWHDWHyI2WyT8RLRsp +E6QmQn4ELkEGO0SN+xv1TeAbM/TNuJZo/zZrbDNW/2kcl7gg+VzqTNB5dssUm6AS9psIyxEbhaw hqndZeCHWj1e6+9xUWIvk2ltwiaoqxjKhwDSgBSAVCjSU78jDACWHB/5B3wAE+xdHDDde1ySEEIg Ht+czCb8fLk2LP+qgVzsjOd5VzQMMBrHIjIpxA0XsJ6PQGJa6QGU7AN9DKSIqhB0VBKMrcBU+yCq eQ8ewAL0lZ/dokui5WeG2PtNDlanwwFL8MY3QCTR4Lzg6VcwdV6rSALUjxklbX/7ZI3GaGLYml9O JiEDu9LnKLAVGEcqwomkfC8RWoySEMoP8mRpUtqzkrf4wFVrd8tCoX3rLt8d+xk+TF2c0XaJuQYy VKnvZeBz3NPfU1mo55XbjybG79EtCR58FFln1xo8xP0DxIiIuZKJvPHD8VUbd2I3vQfEAYyqEwdt Dc9pqmDr3VZ5QN1ZgqM/U7RAIZOO7NAUF7AElCWfZvbSFwq+kApzUxZnKJQtlz/kzPDwGBQ0ipnZ /jNscC5Qqgo/GYU4Eru7DkTsD9iabX4NRMtMxKCVE7tUdHBv4K5psXB7ZvbEKuxKK6PB5NN4hzTp g6Mf3TDDCI/RvtWp9fctUCaplao6CO0rruCmhhvNRnpVmRFbg8in9iGXJzJ80GuTs2oVrvB9hqkU MCzHMf7b5LhWbPbP/HEKpA1VeRJ17qSYsFiTBwsL4/WPcPzTTAVJ9D97Oc3YSfMq1/wCMLMCFxmZ JbjslhQUvBJXGAulivit7buuV4qrStvkhqVgrB/3MsSETzjGSxHAsJQlr/76UHxHkwySCqx9NFOC ts2BmJjcxpDOip6I2VNm0kwikkSYKVUiizXyNiWlCq2vCaE0cJyH2VcH9HlDYlPBJHLj0j1iINCf J3y+jd3EMoLxDvG/hmXj+Aossz0zpcn8M+hvpOT8RhunS3JGhncwcHI3WXGHOCBob4Pish8RaMqU xf+p1PEOwrHG719zCusEA/CxcQKM2pSWR2I71MWLuMO6BFLCx5ZmkYoqcI60cbD9ONgcyHox7Mat 6ByNEj13tcYUcTNYSoMHKoaNyxLQqd5oD7CEbWIdZAEj2JuC4qJ5t+5rcIaTJN9NOdGh5LZcwO1c JJzh82EFhpzev0GJ1BD1f8ELZjUJr9yStn2D0bYIUAS7yLQzWs+LWv/PlMVvRcTO1ebvHXL/Xc1k iQ+zsZ9o1S0JFy/133xzucDqbu6WT8s7bbWwm1+Usk8OLsfbidOFSLqiRBCgLxIwBHxOBxgAERtT nwzr67NFsaxdXAjGK82KnLp61tdTaI/AmNeIKO8qBxxMeAZCgLEtn2sb8AftncVDyrfAGTFIL8Hx OnjxqvCxkboFXvDGb6y6m7ofs3uQ9QIJQAVbukTTI1QxY2N2skvjm1u3Xbj3VQdT1xwHRWnZp30O kA6BHqn+7byCmvf9ODp49+fo8ikjfMsodLde+jpAaHnvGJ6JV685pv6igALXtpYnXoue+VJRJ0// 0nj6JpLwYw0RFZFSWn27mRoEtefa59GpADNGUbfNDpmQMUKWpmRpBIKydq6LAG250rrkQ4gi5kTP UUM+YVcc3aex5ELzeXwHwlmOUlS6OfU5ucjC3ivsmPD4P4+PiG+3nnvwCUvFanZm8yFSiuzDNilv 1vpB2kagfl6jYYHTpS+KF7GST5c0mzstt9QwFdHJ5oP3wQEkpA+iiQbIgw/C5AzALkU1LvNXitHU qGxfMmvNge+r3LNGQvrsiyxocvfpE7AoRBaLOTJnyjb9cdcLliYfeLU3OY6w1x18oYTNN+qPns4i zmgAxH8G7nnk4KplQVrejbDPdP7VA5onQ0N9fsBZKzwVBAH6hRYZmtp7NgjrMZDEW36MAn/txV1D Xoqquegd8ZvSffgo4kUjY9Ocg/7TnJYSS+ql7qVnHM7j7rfYvGc28uCBLaBMiaSC6g1glvUmSwuU YHgGGyU0o0pJLnBuw+vDkh3CrjHedZD7gz2OaFXghiO+QF/gZFWS7oMeAdZFYpfpwDCp+p+EylBo P6unYIrjL6XK/68BB3BTWA5ET0ZgFdB6h5ZGh9IUYP5GGtcbsiD7SGBRo20niNx9UmCWvi3ywAxD OWwZB/5jZqpSnFDrQeBhKm9TRFlECJhLqfPOvXnS6Z9TDlCo1yuBmxVp40Dtz8A5B0YLSYXPqyjV QtKtLGWgdwDLV3o5vmcIewrlJ8AcQJ4D82IWRqNvBWJiqeEtLAeLsGExFtqvQkV+TxWyTV5/BS9H Tbfq6Bhqk2gX+MbLJiXTtQDGBUuJ9OHgIke0dhXABhzS32h/jvUVSXfuakB27BtDmUxC7ui99QjU eIcq3c2v+18GQBqTIrd319KQP+L1V1C0I+Kb702x3ypERlUQ/Mka5i4wvNoaeYYUgijAqu2s639e AeENSMucvY/AbUc6E0btajIZflQWmYr78uWqC4/xVJriDC9qpcNxR4LvITzQotUAjjJEl8l5eeiI AP4QSw5i72D7sF2v3VyQBR1NWVC1zPJ+rNfLKD+UitA6JdQ2GWCB4kb5Ru29KgJBN14Rd4pxP2ed t2wto9zYY6AW8Tgc7F9trxXZbsoRct0e36eo0ytgAooBtbmlVrXS8Z7RdH3ejUDn5vTf1c/RAatA +AKjTzOK5S4855EIMeR9CIUoMZ5RGAoB5A2TqdfQYF0ezgVxyvOaWk5il1ql4oyHK2DPyJ2x32IC VmADDowa8n+Csejgfsf1w6EM/+BYfWdWtQslfjwLINfugGmA9ocfr8V4lJMbUiPKmzT1AqZoc0B5 BzHLaLN2GFQRdK8i4qMjp/XMPIkvSAvTfeePOXOMvM/5wardNyfKXIgy8W06L6Qg0z9PqrpRAXjR oqpVY63JEBX+M04i5ArQ5cZgD7uFqULxQwQNsY06vyUE+wI15k3iqscVtZ6LKiRH9RmNorKsEB9l u1ArG9f10bsHKfyzIR53prkqQVpNQmNkSdqR4yKZY+wbL6BAxizbcu2auae5pV3I5vDN0oaxSKfY z33zond6qg/0BHJe6IASO8lBTxeDBycioEIQD+DZlN8qA2YhXFOJTGFBWbbsWV10xH6h7Z7kuxkW bZYDcfDPLETnZHUznAtdfEJ8IEK0AkZ+e2fNaNRrxRjbRIeC3IQ/IUXl2Sf++UBdyPhsUD4Y7umG mPS8AHTisBR8N1bt2mW0IOv3/qHoxxemwVR3Iu8HEvHlZuVpBUoSDdCDIivIcXWB8x1ht1X/s7Bo wofbwLRedfDpFlHh0fd6jx3ealaXfpYPwFS+ZdHY+d1ZG1JUIuuBgWxsGx5gBtOObKtILL4IT5IR HkhSbL/RnfqNeSK1jjQ8cvN32yUY7uuEh9SgCAI0+od0Uz/en9knkU5O41esG1GYbNjkYo3x4lyw CDd+EIY34LzWvrWQaagID5YcP9TVeEmg7GHtgqgrj8SiHkCMqmEqHQjcyaHgi0LZKZ7ukmvh6bvE 6YCcED4MlPS7tDMJUb7+RCLo7p++aJogoioQZJkgAfHqCpypzbVEFWutGs4368kGXzMfgk2wGSYO ncz0es+2l8ERF0iVrUOl2QZhxSlaXKIAsxj8X0CfyoZTQObD1Z+LTcAE26dzan2k4WlosMg3zVqP rHlX4ZbRTwXLcw9f9Z32an8ct+RpMtgCmby1uPFAfiABWjZwG6fqoZisGOaLEHn8JliyUDfDJENb q3q2mztEKzQcXcLIgWZ1w4mD5QjwletuDUZeRfeFpHGGwQybiG/Hoqj8bdSX8+Y9jRWgegv4XqCm cwUMDkRAnR6epQHhmp7Xc+Vlq1fPhTta8dZHPV0QU9Or/uH6WrD/6CvTBF8IZ2648NUV8PO8yfSB 51imoCmGXQpov78iMeupZUsoNQMLNXEc8jysvdtl0/PlWj1zZccAFkrtkZPfFhCez1IL6AYG1uBs Y7gplXI27quwOpIFLJz7fJ+Ym6M9wxScszFLJtxQhStXM9PEGf1xpDdvbDOfHIbXkQ3Zg4MTF9bc Ue67P2r5aqlWdLgyp218Xt/SWQZz9LAQahPig1QHjw8uMiWcia8JQ+tONvOpbxrIpjcw0dDykXtK 2P9gryBFFkMr/iV6HuQLJ2A6X4wtXFL/NWxW2XryjgRnaH60TbT79Nk6A/lypAZrClfcYaA5K6Ts LMIAiEB4MR3J2XfTzPzcil8tPsfMo+kFHE+c4zZIJ5fmqa80JEPC2kmnLhXLwP3J14CKRQbo3FEn r+40xO5+GHkDRjJJ0gGLI0DkpjNaq6xGgUccijnQC3E2NhFA/YBWB621WD4tm551gvQ4tvSOnAEn 4NacLNlWO+UwLa0CxXU/eWdWUQdqzCs7tgN7mNKNQ17C0hafJaSDd6Z8MVkaPQbndtZTjxDsqfvP 5qc5GPoi5hstcLk/zrbNEC/+RqXMsZbsXQDT5XM0dJssypC6nfJmsTcCbPFac0AbCBL6F37oQVgB cHlMUl/r8ICHrDkHy+cEj+/u+Md52NIJu2tXTu5jXiZAdkSg6id7/4L9u8tiC6ah5RAo7EK7i3CY lh9N0xHs+tIoIJK59CjTMA+wNDVLB0a4bLPjnhGQUn73Bs0qN3YZkkiI86yKTfeRW7eQHBIHEvXQ 83lINvWVqFv3XbdEuPfDgzzMkRbNp6FnlumrvdBWptmN/fJUKr4SB2CCZzFjiU2MZetml/fRBCt/ UojEJ169BACKtv3V04t+IjPgEMxCVt/TlD3PRqIHyuksghobE0u6ZPRwVfUYzkfGMPK0+jnayzxF 9w6KGPqfEW7OQBXahaSiMo4QIQD54navsL9tAQ421jxMqsUBoafJc+Irj5S9Db+lEMD8p4jLWQiw PVMnhw7Ve2wjkXhbZTMBDvn8EuFNZ/Rcq+i7xrO6R+QtX/ZNLYLw8HdBJnTIVa6n++f1gbJ47lLV B31tBUpVVGwGnBfKGI6NBoDPvyg18HB4cP7x3AI7EHQfgo0Aha8y2EK6KnuBZY8uKq3cAa5B4bqL Rue8kAZBWLr7fVXM5hpCXrCPSFIDsUzsfjLtXOLKMM6a4W6C8JXR25e75oblfd7YaBGIBwurwu2+ QO5Pim4lZjtaexl5xpNTDzxnHSw1dO1DA/CXGFLZNeupVuuW+Hngpjnosykf2CNmGaxCsQecLf15 cUN0g0gQ3FCUcESHhZT98BOlDhIj9yP79a3tCN6R1l9z2n3lz47nIBBhNTinpj40W+lLDgQLyZvd Hs/xQS5lKO50GaVjwCeAbyW4QwiY7kNYiS+q5Jue4k8cAaAGrKmw/4tAQhl2GMYZLEr7v2f3I1VY d0pkQ1sLVzWvTiOJf3EUjEuwyOTqyCLTlTrUXm2nQDSk4shtirNZUlFvGkTyoFv3Kv6RJCj9ld8A th+45qL9iIy2dB+arD62Hh39xDtc8STbd7F+f7+aQXD5hSZi5rpqimzL2mcm6I44U10E3qv14LwE qGpTltbhLrFBm0QZOLRCoR+RGN8uvqnwbAeTDA6pVgVNlPeWJ/I17EYqicS6/FaTWcy3Y5USpHRN OvLfkVc6IgMBKCSpNh3XWw8UQ2CyLZ80R+sPm+oWXuKOTG0oHpnH4BN8X3zq8nrAZPZQ4y+q08P+ 4a1eT4WRWOXAHBFUnoFTUGhRh5HFo+6VFCtB8W2lK32diuwk7G8kMqzHkT0+HAVBiSQwRJffPuPe 38Fu4e58MWUhr1ubGEc046P+QPm1W1jptbSJ4OrPcObKbFGoypCuCBXVTVP5iGZ3aaxWpv2j3949 zyZ2LPNWr0E8titiPyJP0lvSuf/A4h2BUV2ArQdAT435AZxEivZqRDlRaoU8MG4eKArt/nwPq4Bp 3GrRTZ5zT5nsyxkLma+JJcnKqwAgItI3YIsOaWH2WSYSWukH+hX1G8tOVEmzHP4mSqcBMpwlgeSk tIwz6HOorMaJm5rkB1Au+5q+ZIuX0buOPYGTxWwOguxQT5XaFzeawJ6nbVgOGlk/6ZLZV2m1yB0t hVqAdHgxR98luuFx4BRMJQEpV/i3TldSIeo2eDn1wtbbNkRbyxCrI51NaMEe1nCLrQKE6o3qoDax O4ilJR0CU1UwjZ3i3fytYnl6angN93Mzji/ODLMQV2bl+r/AEg5y/KwdQrUROEg0XIl1Bje7xKJE 1tTChw/h+HU/mu22Xwy3/JVe0it5BotWmBSjtWDgLCL7e+7raUeDW3SijRQvuW88pt1yaUcW9k/X lAMvTEIdaHZpW76Ol3ejiXLjFZbhuHJY8ucG3zGTa9rZmEMEt916vq/kOWzPHSgHKdszi1aLYkW8 eLREA/CFmR5WVephqgK2umsjKl3bJK8StN7xyfmovPNI2af0T2c20/n8FBktDswvhVGKBsyPgNtL 182wKCi20/LkHvdrMtCEGjzvQDGsGyxpgM2ErtObg83+WDqr35hUIRgLFbgM+Ovbngh2nc5pxGk6 rW1FyZ9uhUSpeAQ7nP7UySremBKdip4QwoVBOk9HdIXpF19SByJiAOLPI2j2ppCx/+qLYYSuhNV7 wx/9aCJqZnZ+2aHiyoIAqI5oQ9vEuKx6Pyo4LppavHqaaaXs7YyGvsDQf87rVHOg78qlKBCt2SJb 0Bd0hHz0iheouQ9JgEk71Fu5UYMSi9E9t6HtOOVkku2ZiTffXP5fXiHrJWz5SbKyxGUPU4gbiRM7 QfTuBVt3SxRb8brqotakmLMs7D+JdYIVhpt9SViYP7Dy1i2wbYs80S8Isg8Evb7lVWYNDIzVdk1I xn4eVcbSQo3j+KJ3G5fyM65SZE+huEeKyR8Mz1u1hoX+XLet4uJH215UI2c7SPYNC/vkThC5DZOQ kzoR0jxfEyso8iy0Wn7okJTF0zXdAUEoTGS3ByqaMKxd/39cajvh6+L5sRL3eDZjjyVAaK2bpOj/ AlMlOSs5bxs46rZAjDDpVWFBPuKz0+UmDrk/+9RKSkq5ORur6VtB92LNSBRMiHNnsDtYHBanzZQ+ LpFX2YDSu0VL/fn+CVq81uaYcB9jIChNqmH86s8COKUwnXMfdmRDIKpGf5CeM7/P16ZHZlOf4tCm r4qBnJq4Ugx45DLEn5Z45Gl8/vIwRNGICXV5YnYDzXu1s5iuTpmDbY4DJchCICorwr+zd75kVfUy v96aENsGmgHCe1zgqBo2hsom93LxK5d0QU5lQ2AoxKjVnLeqRt8XUO7HWJO5lJg3u5wvlD6NYn8k mTwQtos8JCRwX2lY9MrbNuOdDeXU/YeFmQNfg1u+tUb7J0h8v7m33ZIknv21haDALOZUcuxQNb0Z VZxo/GFUIsmJ3sQyOAbkiROAS2KhweLgFFTwzurA/pr/9Z0udxVFqD/Yzqbo+CAKcHPdPJB1ihFu IPS76omAFi1OMA1DeDt1MEGyo8zFOJrqx0kvg2tu2OML0bdqu96OT1OSojDZEJQzuqrDyUW3INO1 hhj7mqLH8njjDm7dYePJUihFv77Hj8woq9Arw/OHrIFhh1V1hU9oqqSfWXVJTMPKvYc53Q/T08Js 9dBQ6L/3Pce3AWLurK1Eq57IKtc77zTN9jxtOxKo8Qwy70xQW7GI7lmVt6yzSOIKFSYVAPaxe6Cc 9a/dwNPFmJ5ufvQhpJvZU1nOJTJjhBuc/7stuCZOCuCIqMnI8gSQBPLk8nlnSgbhswuo7XawHceg IwYdXhDHBHcpauksoW2bJIZGGAOqToBNTD/20xop7eaWdFWJZr+g/mBNlOOExF2wXMf8fcbqqebw bnX08gRClWYTARyNntpWI2HPHWyvFZVGpuFV/XH3IJ9kj2ImgKtb/Q0U6qdvUPCmS87UZKElADlO NDPidnYaCef2YF2PsXBWu03xFJSBq8jsFzZfyv/rrOBy54/MZPJzodjHfvrv8Hsfx3BBGoPRWf/x vAxBozXdYhglo1kEQ/K6z085Y0Oo49p/jbvSltv5fIkq76VTQ1eRNu6cAGSm/+4HRwBK/5/zGmoo yNTVzedkq7ycka6p+vw5vQSB5oaQRFxsyDJ4GD+0K8iN6Z9MZ3TjXLdBk3owmM8dluSDF+R7Q3Dp S6+l7UucrnXy0mWkNFGVlfWNHIdzEabwWiSllb07j0xfv+zQxiyfkKcLAh8hW/HQatb9bRsUyKj9 oTEIp+qTz4OehYZePyHyyDaayXam/hAH8HJDkwgce0+ibVQ2TFN1txoccwYHKdluz4FBwIParnMi zSU83mwbFt8FxHsWYOh1KbPeTJjIlHzy2rcCM6Ze3gUiyeeBJwLjZI/YGtvvTgpZtMlmvj/KHdGY RY8nUpDCsskQHkyz4Y5c5io6VJeJTWFHK89STf1UddZUEExbmTmYApOG9p1FZSvL4ldg8lxkUCXq SFsAIvXgyMgIjtMvXE+kmhaPYtpdppWpwbmxDMtOHod4l2iKIc38/Yqcq0/WHdBhewP7g131Tf4e pP15ghLs6Kg4Yrt2hThxzXMBF4e5fSMOl9SwcvYhiMcGUrkWQd5JjPdO+PRonCIG69qdlNGHq+Q2 zVjOgG9pg6BE+hbybiHBMcyGPa4h7/27ZP7f5C9yqGm+uSz+v9KDggcvX7bpyR3f/hgEzq1sJ0dA F4kVx5Xsiout0G40XB96U3vgFKFyxtITGap2/6p2ftQdUxrW4T1ikG0WtZ907TLCfExnGv8LJIUs vSszs/UDeSL9sLvwlqP2eA34KBV0owZlvRoyGDoIVrCySBUO+1/U4E7AxXR+bt3La/gRs6wyoRhC 016nMozRLfTu9viejdDYLQ+OS3XJHqa9RHdZfiE0Rx6gZ6YDE1Anb4MZxyDkb348OE2ooJVoplOM QKl7LCpAnpLVewpUcBIiNopOwTJUeaLKMyl/NGbyYErwsqnBCdGCgAbL83aHoTesGBNwKO2GO0kS Q56p1yw7JzthxAzb3gpOCPVCBNXVPpiMtpYQwjT1F0OCAEIBtxE1Vrk0/Tib0jLDHbSS2TK9jHu+ wskCefuhWvuSi/PTCFSbKcDFdMUZcIPtkbes41U65og05v4dYaRM3Kl+6S2JxQvqsZPGqSdiIjo1 wlHdKQnCFgOtpnBOkPYuSzbMH1zQsw/CkrQAH5waZjWeZml+4WlQXdjasCkKcKsSzX7Rdz5GQ0CS ztXmfDPZq3zK0QVzUxKuQx9MWx3dkg9tjTGKSJN+HcluXnbIffGN08vAQ8P20KfqNhuiQ5brB0OP 0oRYVVFG7ETFr4aDm/LKm+Szm0ZJtcNcmrVpaAQYn2r8kt/q3qetivI+ZDYL1A/PmD9MpcVox9bd ndY77ioWeBiMXPJD97tkAEfTLrHsuwD1DKs/1FzOymI7ibc5I/8qsWMR1/dAgT7fKI8rjBt3yRAa IgW3qcvuwn+gj+KpiZBfupsRMUJFsFM10YZX2yLEF7viEam617eD9puE9KQBDLso1QUm/QGKgGEa giTAYUVdrkiQyqa/MxOLFR9pVA1B7TmPzPkmufLPWUCC5ALSvdurxtVmrhZ9UzXXtVzjyH6Xb/PG bKFK7dNKREv+drr6OuN1tPBxnCw5M/yAjTKI9YFu4yfUtDBG8CollAvMcM0UAvR8zgXbCcTRGERc eycRzS0f5dwGXyrccTJCkPDZpun+X1waPWN8jjznnr6RXiExoq/pVw9h2cCafXhBMg4gKoWp/2QP 21jJhUEtPd9JBKjvBSdciJV5n5bJmwq+zugXqr7pFgKB4l7IKYn8yq1lIOIYKjcBls+ILNIkoTim Qduo/HoRQo1Jl3BtlCA8nzAa9przyyOGJBUAUAC0dY3cCWYwWEra9apygTP7ClhaHrDIqrm2QyPL FFqTuS4xne1u6MRVGlT3hqrZS0y+6J8WOf0360WQJZoyagS59rK2lhBf6lFWfFqJti9MeF882vLy ySVm7M6q0Hd2o/4WA1leUREfzKBMZeLJt5HnJUME5VXKjlKcuHTQ8cZXcR9WspQpyA5Yi/LBQida baiPAQL/lepuP0EgYsJHoyy7wmF246nS4xOpwIbIBg7VntoL02UDdEGhtPzFZBON3b+WImUmLgE4 05wOk10zK4oe+9QugF2jaydUfJz93ruFGiG0K2FKD5nH97F5ctRTIQ+4ndFT6OPX870g7MQtwgvG 4DruL1Ya1iMGA2FqY0PdvmarSGeqGuoEbl/ztYrlta0sNsu6ZSzqXYOb5MWGUbSe1PjQBiYFrY1K h4FAa9ymFbQA+KtyJ82Rbj94jDKDrnw6KwwcYz87apyZhfGEf8zjO6TANn+tGHngQmmXUxqjjbRj T9SSxnZQbFOmxyvbdl8T9wF0MJeLEmhVgUH6akedEUAuuUXggV7/RwalwHQYRj9E/TQR81ti/VLa i6wiiAv4FfO/5BUKytfpsLvsvWdFTBwZ0DO+7nTVDu1o3cpvXjjqRLTambzr3yXQYjPzk12wSacF d0+0Lk71V8j+WU0XMQOMaJNTBD2my3FGggjn/PoRx/IpdDNHyS3bGEZU/4NEMiC+ef3Bw9uXWtK4 iWyb4uuoAO9jh0d+vq5HDSOKCCUH2p2Ce1Uw/xMW714ahXBLwiBFlG/cZKV9iT+aU2Gl7A4f/RA+ qmdRMvXq1HYbEbSNoK/U81ws4Fh2wqGFkUAtzdqbpFT1x9+6lIOQ5GjusTCyfE7+r6xwnvOUcECf 2zOFp/aaCvNjwEqjuks4M5L2lZblsd0SlQcdYx8WZ1o/d0ugfrlJr9zXb3HpKZNhsBGcBcCajyPx DtjbmdRi0IhjHSLFgAf6X71Wwqpy7CKCekND/p98KuJkI/qvrsbgs+zeB/rz45TjPaXFsbqgce0l Y9fDa+40l4OVd7OZK8IBlDlVV+VYf6xeHD0o6f8b8Kdl/CKmWhX/CgvVMlK8j2AUcf9PkGJ4czak fr6NVBNg88BYMHb8XKXjSWuH1qO4TdP3SwMWDRtgecAXROEm/G/6DwcT9wX009fFczUnCjUauyGJ J0BLED/KZL5XFIjsU+I8lS6Bb2lmcZMhD+PevTwmLoDl646fu3rUOxwUlKqpCKnITZsKjDlym8hS 7PMM0KDMqU9RMsKPXa1vK4dTDWprZ2VD4OW8LS4WwzkfwaIokH4/gzX3HIPjsPtpJvI1NO2NRZz4 cNuuW+9sx03Ovd38ddH62Q9ENY7GyqEWTNSAr7vtqiFSMp7UhKRQa0iNKAECEcOEwLxnRdFCEFNO vxDP1hF2JctwvQSYMhJOiti/xLO4OrkoUEG66EvV/nQxgZs9+cj/r32M1STQLyrBG1IOTHnRWNc6 4/tibhQwEgSxuVE/z7VAqWbDqvP3wEYQ2lqPWLuemPU9BdwtzTdSKrZwOtXDRfnNg1jjaiiFxpDo Y7MY7ZBj9namPODM+gDxjVaF6Xk7SPpuV/y/9fcjElzO8miEgzt+z/EdWaHGM7RChYLqWpNSnwQL FGjUS1OAQ7YkzXzeyY0TrOpn4bydYwUHfq/i/zakyEhIqn/TcuTYf+BOMEiDntcitjskLumJqIeq SGOWdbzYMhliUiBMpeingG9JaKyRb3j1ySvFcN4dOTVidmVdxFk9PJhYUuX0g7RJWz8ECIiU9LC3 /TSQdg28KcPUdybK1npRsdYYd2bV6MTTXTz4WqICZF/MuPPXfp/kZS9mAh1PHF12xnyCvguBplag vq2FXVEBJ4ChbhdUwLP5PE/oSF/6dzk2um7WaUBlyeV2Afe9NAVRnYHr2znQnm9Ja++1djOyPO9Z qwFxGdINJGEqA0AxQgrH0ASvNaLEuN2Tu7akyH0A1HOJGscoZtHPKcmbalxdkFjAL07c+ROG08Ci gCp4caUU00axAnvzw9/MugwGqXSrptbLU26l/rwpx2jYVkRSf6fpMgcj0286IX+RBfLz+Si4BrKY 945A82XM4HnkuHmbhxNSIuNHPtrS75u+o8p6RPUwQWX7h7qSFh4VQjcTOSjyvLnF6BTf95R5OYVV o95mtHZhuRppDI0nslXZjVTT0Xoquh3pu112eEHmQ8g8+K4vNprcpKbWk6M8PcjKps4PGFBqNFtr hqsdTjHYqqYKWDtlMlQxxmGpfVEFiPtlsT3rOCgBrGyfY+cT/MkOqtb0vNsREATtt+wl2CCu84fP qAQhx941Tmv5D7avYwXXEXAQa7Ew2Q8T2+pCUAxvyESqxpZOui91/v5q/UQLI3ktf7xgl2zL/Ui8 QwKWXW+WS6M8B1Y8aH08YCP9PAOwzVhv/Bnr+6/0mkSFwlSObtIPlGr3Y+biaMcy/K/Picxggg8O YmUdFjagU9YP4hOapBAV0t/hR12Sh4qPz/RUEFwumRD9vvdXhV2azT9Z2qrfzBZb0g7iaQm+D3Zr gR8B5Pytp6a8p+674oN6RCon3/rFqMHJwPPy0fadUI2icH9X0ai2xjUPL4A02/HTvrmzzZtxLftW wKXWz5c7LtE4TlSkrtfgIYzp/x9cg/kVe1PRfiYqeKC/3WKv0vFNyFhca+QNsGPg7w8WM+NHQMNc YqUmZ/6m+Rb0SWjoUTv29KujbUe7dt7D71UEr/4v9ABRU2UM4me2kUfpPhrM1JGFiNyYeB9Bbl3K JOHfaNCfopazsMf4eNwvJYKOrGnE3F8ckmkUuQD+01gDtzC9G7EziyJn0d0B9iIRj6KKEj4kOJKE K14dAhy+ypbFZ/RxvlvqGwtC1+4F/m+K1HN12mRrzNl8lPJbugdGUGXwlRRd7dXqIKZ6ZUQSa6wq YEgXJvnju52x33CUzQz2bbLUSrpeNrupXHNuDx3UFQIi3NKNTdtuCncEZ7AqD+a01RiONGHT2eON ta4DPsj65Z7vh7qjV2S7169N4mJaEHmhQAcsrBe39FWyGWrC0Tx7h1bs/Of/RhHVk5uPT1Y0/clY wm++oZynpd4sosExxw7c5K1tuvMiM+4B4CA9WBYOGh2gsC8wxY+0VlJ56VZlawoIY+53Npv9EjY0 HQ+4uykWE8YWMOstDExXMZUPjGClwIYxaoRmImVSuPuFFIETMaJ7Sf1O5XlwvFhk6QplxKpSaqYW p1BdWunbqVL/XDM5T4pLcPW/HQHd8/C2noFeqm+OoNoik3/b4x4nKv8o3FijE1FSxZYoDN+fEl6M Kpavq8/0rCXYPDUmAGserNvvysvrPXjcsnZDRbDwssHziWDlkUaLk66NVeuGL5pHoteSVZ4DuL23 YujZAARedarX/38gc8l1SpHMtR6Ajs5lna+nJWpEnhw4PYzoGL4VPPuy5TRdWKPGH34iTyO9gmig CLHUxzb6TIdkhPBm8AwVX7dQ61Nlawptxa4At+5XlgyoMAcgGiPP2jEdLDyZfHNZ70dNJWIl8Au5 QJGY/8OpiVkCmxYBHBAC/Bg+SNEASX2H2n8v5fTRyXfIRoqb6IMkfENNl4PNPj4T/jZdwjJIsjeR WObSagqZ0Z8PUhDvlbEnCTjkR09nS76QmT0/scPN7Q3Ia+R/9x9WUGC2nC0fkf4fDKPVEjgpH4SV cuFk1jWoq1exIyY7QIq5VAy2wvIp1uhGGeKde73782B624lTGhWCUX7G4nTV9DqZ06PIUY1CRCZW WsvzFIhJvdQPrz+NdVpuK/TNsQL4gDqHmeVwrtZAjIdubGXs35tP0tyamteH2MlFLU/m2XGeaHiH UobuIwaOSmXJAK8aNvuC/F4ztYRulpQNbWI1gqisg0iPMZ4nL8db7zmJt8cnI/KP31gEtjBrT4Y6 Gj5Vqg9RtbH9kfQEYOfbEZ4tyFV1YKeqdQR1AL4RiKlqk+fonQiM7PJYtBjp6qBosti1Aq5qsgVB HsEqjUbd01W22TUbU6wVFPid0Iw+OAHao3qpAS6AuDA49QaVhU7Bb16yunp79VEI3JSU+0a0iIAX lo67gTTGvfv/2AEUG8S+qYgW/EBY1UOs4Fh/jwP4aNeeXg9+Of2UBahOGmyA94uAcqxhIvjx2U8j Yve3y2DTqpl+gPIMQm2KfILj+7+oqyM7jgZGxzU02DkOZvrWIaBC0Ml8tsJvQwhVW+O66gEVeA6+ 9OQExcYgbt/IIfvGk84f8vnmMFVv04ynThdtpYWuXgWlfY+QDz31BoixURk2jkTdnHMYaX1RdW2m rH0KjPJCBc9vs5Erqch7UA/Hr67p8lTGjMPFoS3mGGB9PPJqh19hnOWxDqesPBKG+erzwLnDEyN1 JM/Fsl5DCavDNo0gYPDA7f2B/mBCcrStXW0hWM8HQdDI4tMZLe6lqjNtedZzVBCie63hzQV5wK68 M5wt8TNnzvLcAP9pyTAIX3ECy3fDKszwfM50v7Xu2+zOBqiQZingL/KxhKpcWf0BgmBHHhmfGe8H vqsZkw1hnSrw4zKUk0QG7yIyD9ujqO/kJovk3+E3vt70+e7wDv9rxdQCzjmsSIS+ge6PETliV5qy ECgMpqgeV2ph69lyZnBpKGqLP6LBVLlrZpZSFIBmclciNiCPMHJz8q8C9PGbXW7+dYwPewBz6MlJ UDap/5Xb4hXe4EBXDoSCkn0eBZ49Ux+4+R2BrW8epLpruHDe4BQCom3mUcKROi5Pi7lrkmUDClkS I+475DFf8sQgkd7dEuJesyZchaU9l5xG1Ov6m19Yjbb5/TIE1C8MFS4kyB3E+BTsBovbmR1k7b+v TPmkuTY/zXsHs+oHXk07EvLrFkkAlhi2SOkGelP1NXqVIsAPlMwe3kgi4i5DpUcqCmgzuuod8Tmp migNk++5LQ9+pMwNR0lulUl9+TCh8/aUNBCeaggK4h3lI2RPICip2fkcpJ3UkoJ2lJt99Tc1Bn3A ZbyGosf/hCFIQAJiYYvxq9HxknC+HtNFEjfV2Dygz115aYebxvX08dCVcaMDT6372PswOppAyeuZ XfVsUfWiMAjaVE6uC/uHXMw3nlU3zpkxq5qckS+Mz13Udpmnu4R7qX9N5IMUcixrQyyA67zQaP2p fso1+Vyo9vio3naPCseMsUqDeiFhx8DYsWk/Ks4rSu+V79u/j3yJIVtC3pQdGXiR8FvlEaJ4IUSC WJue5OOAkT2TgVNKJkDJEXJNHJhe6nEFZpF1J6nqzhChSNv5kpbj1V5uAzTRtfWEWcU3yIBYqeGP /ss+2lAF0HxFfVPQRJJNtQeRwXjlVx684xpLYlwSUSfjvoY89O1z9xaXW6g0pnXBVP5sgNz90n9O 3DI9By9siJEoKo3ZAlV6wH9UI2m0BgPlvLwvowTDd9uZXcQmwKm763kMRWi6iwA4NcoxQBPrQWGu UHYeMOYkhWoDL1aSUTI4NbIbSrRFBAifbDeFMTa8O0fvq2kQ/3drWCg44dA/B6Y5JRb3H2qUmT49 2lDvyd4vv4YHQnNjaWjQ4aZN+F+fKJaDLJBUaMUHYrtWi1cN4+iZ6PAx+mCDnsptY3pvmwU1c+qM XLjXPTCpbDWz1nvPy0efelwRQxkztPvbY/Mnxlkg0Ls4jmuwpkaxAs6a8C4yX28kRWkIW6R1Dow6 QGSp8ZANMoKscgzeRY9IRlMvTpMKHmHtGwYz8fzk5BQqBV6r+Rj3WQwzoCJj6m9cqdSLzxT+gBfZ yxQ/HcbBgtHKVItLFgmlPIAoLuc/VCxk7BOQMvQRUCbcHkqLXS0bH6I5LrVbYQM6cusNTCivTEA8 1MoVRoVVmsCt7iSdFAA89QXIRQ7qdllzDL3X6DIA1tann/uDlcVioigHF3kyKlKMrS8PCaOkiFM9 THrJFlqS7ipZcXZS5usyAXUv9RPDPjqCprSXQK0bRa7Blogfw/0/rNUEmx95ZQlEuc5xsJi4AsOI 0W3Xz0y42T0bMGwkmilohfRvsboVuCNcR26NXbc/E4iF0zOVlbH+GJgx+ki70Mya/fUvxh7VDUKs VrJeiGoUJx4yPrTeuv0iI7UzY30PZLklPiyFBL1903dwNrRbcPuxJU4s+gp5e21YxVEMrl6bcgdP njqJASYZjIEKNeSoVwBSY4XBu018Sy1KdhwXfYS+Ct0lSBk56FZ1J36mDHfUqowEmAeGX/FNgTrN 8ZfdMhpoIBLDKEZzFN0M8GNFTaVE8fyPMassHmRPyl+HuE/hLHbHuGqK7GKIyDaEesnfdWR2LjGb OGfpA+vndwgl2pPW4vs/DnlcEVEGC2194MdvL8e2N47TVAioJA0u7ODTm3DmokHK7jaZTlWW0ooz WQn9v/TCrtV0YGYWYnXJHEhWfddraQIN2/E8KtflORlbPLOp3n/2qZ76N1S6hZlbqHb5XvxIq4EF 4RcxBqcZKvHdDRch0jhUrx1iH5QByrFYcpgtc8o3PfQgSoDS4kQxh9c6r7EZVFK1gxFc6ma2BqUS 5GRMSNtQk3wjpmJHqucQaoCewvupm5ItvcOcaZNgFIsrQuNUSRVm5gSL/uQEcV8BrQJIONdTRSnS u9hIs8b5lAr0t67a/JDsKMAwer/NM4ALV6jsRyz+Pf4zgUz7bZtYWWlKN8y5Pg8A235Fegw/dM/M VoMATeIqmitl5mby5sSjehMP5vnYuiFQAlrKDl5HPyW7xLSVKY26RIB7G9wvryTPCu19borjgMVe SM3yR+iYHL+bIMUM/2CnqKuS5h5j15E6uLsPE1TMSDnYSvDwCnGIl/HciEimU5GAr8DRJ3D5eJf6 V4n3V/++NAXVfAkERcOhy9/x0+D1qwQMcfo4H3/5o54zrdGqB5JqCO0FIdSM44saCYTwyNDX+E0x rlKLyr5v1wYaZnDIl6b/xX+jUiaLsGoqZrAJOuIP1glBGcRf5r0y9HqiTu3g5FYyV/L8EdP+nPwW 3j0a7zi7ou5uKPrfjg/mLPlJEXnaQQKcq1Z0FoR7SNLyBm5X5NlIfSDd01NC6LKfrXznXspV8/6j AJ62963tA+LRp9jd2CBQei1y8axxRJXck5XrHnGYGl/3cQK5icLZI6aNugedJkWl/QgDMM/9ChKB 7VHUIIAEJNVOFqO6vBSC8JUGQkogI7N7Nfum9VMSvn5GJH0vTFQAJIwHlGPiiY834O9lNx/LAM2Z 5TrUovfxVguCcKIH3Mzp15J4rTLEtKJIKWkRoTvXPtvZ9fQcB7VhTpvSZCH0PNSqe/3ytqG0jEd7 95hXDzngyGzk31A180FK5SG08/oWgODSVEcQ/WGWENuBFdkWVeYVo2HmlkN792jCOvsrGoroq5is GkzXDfR7y18W8hrTdG90FCU0lScY9Kv5YMWiSpWqnJR4TqHPeYZKdxhQbkHiXfxWrKnLmw4nS+5k WFVV1Pz58xSaEq+3b5uHNbN9E803JXlfre43NIKTaLP1dDxNwVgz6r1ewI5IhQXDKvM4wQ7xZrFf doG9D3YPb9jLrpcqR1deQyttzffxT/KyQDBrWdS22QDXQD6BYuo2PJTZx1T/J2vzha7LgTaJMtrP cLpiMeYqHEGvCP2plzF2DJqR5ugcyPUQ9JeUUwq2ma8nme4FqBfO20euwF+EKjt3WhooHPHSQ4+0 CkBHphrFR+rU6DqYzADsGNOPp27IWykWnzWkRoqMu1hEfEYN9Cw/9ezUGCjGNbUE7daIHgVtn+kr ggDfUdpSNUR8GVWYQ6UwII6gG03tnrGAqliu8qsGJHGorXMiyf6Bjqb0U1KDrcYBPUllrHBDSShq bvxeUhMcrPjH09ph6hyUzc6tpajs4KqW8gkqYozXNIct7GSH246bAFc/BxGIm/kmAtsRl3GiMmAo cwZHoV3VuW+SjApOzdZK/A++prwPgf+RcFdAZoaD2gsXfFz8JXzAUyWzl+/ZhHYzzdKozLnukSHQ yJhkt2Z8RnMhEJQ8bQ34gJ9040R0dGAUIA8I4kSh2Cq7xcE9uRdV4md80b70+H0oTWdKjbEijCfp 3VIRljPKhCbI2lO/byalwacLYbQORibPFHh6Gan2WHIxOWHstRPxGKPvGC3X+oVMdN6aJjZpVzZz 8rARvaUf6RkyTkG0OclMq6eTLH1UZ2xYsKHrAK3oUrU9YNLRSNvkpSrdnxK3Al5+EI2mHLrVyWE+ WdVE1v1rvm+cBPunCHuD0/ai/7SSoGDq7iLY+Gy3uL7nvHLHMVwclScng97o7Mb5+5u78J8wjgHz Sorh0NNGMJZDeUmORomx3Q7ZCTb+tja3V3zX7eLHAU8gFjLaaBkQu3le2xEjjo2IQF/tEjKSmz6G TtK0M5o/djAHyScCIQ3Mrn9kQe5KA2lZOjJdWSDElSjpLzYZVM+HWncNukpeJBp+8qNsaG5PHob3 GHmfFfCp/UUh8rVX8cVyURqZLYfSM9LKsVLdTKDkr130qtbUTqxDu1Vt2q4dy+7Q7KyCoEw7BH07 y1SIrdk/ibQrapoJLelhd488WJ+lE9Fvwg0ROh6R6WYTu5/wDQQccrkMsZ3ftEz/+UqnEeklafWb 9lf8vpctUMApOQxTUoaCxzBtQLHEyVs+SbcZQysmAUlktAhOLuL4q4KDdTOJSYYbuVviaxx/U4+v 2ghNEUm7bEuMCykX2Kk+0iCHMNU5GSd19U/ceknbNtvsHFo5xOKDTa16BrLEOmptYkNYg2xTjP4t miPO3x12M5W3/+i/+/kOqgKWJgqUYvzA8HDzopkSXeMIbSIU4E4BPBGZBgzSTGKfx2ElCt4NQwrv 6CDiPsXrg7td5iQ75NhyGc/ojPw/FCg9iHkM2oLm6Q9LMM+e09xtim5WrvgPQEyg61VapkQUPkSZ JEUtQH6FWSlPPKYMPP5/mfRexige7ZhfdHagafCCrz4w/RXCPP6DlxNlZZNaY4K9Et1/hl3NWMpP huElzMFSDn4ShQLgoWK5LHu/DmoFGoY4G0mRUuBhoN8o7s7DNY5/Wjoqpfe3dU7qCdfrhB/oGLYM xwmnDf1+xPRsq3BMk0FtUeR8db4lb36fDO9HV4FkYGQieM5vm8tdY4tvwMVv9uuJfMiEPHJRBBb8 7+lIkt+db6Gu72iBiI14Vj2L+87pDDw9KeG41u4tWggqlZlyyctkQjsdefp5UYUkfAvnCZGS1jq9 jntpv9+WFmxkwLtUIxgjf8e+zEe8Nhc1jOumkSdoFpVv/qcUpvjyX9AToikjrgVYjWUNvV5aoT2j 7v4JgMgD4jFz3m2BLHtaHQOgTie7XqCL7KppftqMLVZsITXg3bK6Z+fbXufKuptWfbXdI7L0kaRR yVWeEgjVX4H1cVNoAukcnWHmLz25O0zSp1ZZUZs1pkFW4p1XOG95lclzq8XxFP991PlEyOXmFqYq oqIk24hKiCEReeA7gPcvBM1/07EtAIct3UgkoMKtf41mTCC9mJPkDI+auS7cDMf8Cz/CUmlzuy1x qB3b5twrzJOnjNW4rDFoNlhoInwP4JZJ4almR9iZy45DGUWOVJXinIM+0ngIId4s2ezlE7gwYGQy HfrmfPnB9yjAuzEKafue6HdkrEqAt3I+9WvLx77hydsDRJxDUc/Z9Y1VFIzP1Z03174Jfyz0+8Hc kB4ziyk+0w0Tiwx/a+L279ERBphXmi0tkJj5bsV670A3670iy9bSht3WSow23E9EHlTEAqDbBJ/t Pd80ZXVzIoRvG4HesAeSZEhg1WgDnHPHBax9sgNs3KW3GjgSrtLeTxpNqjM70JgCYzMtY0Yf+N+O XIns/ZFi5DBJBbvzpPgksoEX3Nxw/BRkhI23yDMp6J4X1EnAOd65eLvIB6sSVX30cNwi/mntt1ie hc5DR1KmX2LAtEa930XKI5rh4q8ajdP9/jG7xxnADfGqVWURaNEOFwe/3FmRZGYGfoJ54jk3CyR4 UsvZ/fGZdDIISLEhyZrmtwNLESJZoaNpx7LFGfBeGMENnZZAVlNvyWqUPuz75Tkcjtw3IbKZPvwt cfXa4j/XMUpQsvpHIof+W7KvTwz6ub3pZ1jkfq579CkoTujSVMI31/DMk8in2ddbDztEXuqOh2OS 7+klSssRiOD0rCaLhP2A6+/Fl5q3ueTOlgkddm1KsBiutjn1dtxVnaAWUUY2c8hhiC++BXP3p0kv x4LKGnlWfZF/i6GUbdfN865vxNxtG+aHhhbzuZ60QyL9Vk+G2+l+RgVw2nkRWlGc3mEfrDrZS2+Y 2cNhqbyuFx7mAHufMdoOdZVAQhMsvLR7Az3zHAjLMPzXYqslffUD+782hOtgF8ihEsX6n2FJJxgf oximGJ1Ljx866lnYAXOUifFPgLgKdkEs/uN8aQe/2nCkQYIfOenmq4ttXHkeX1a73loI/2qPB9aK D2JpN1TPqwfClJUjd2qfjub+YnE3yGdAJiha4sFxXg2eJxTXfH5RbN9JdBozJUWkRkZJiAukl1/S 9YKJWQi8ctRu/XUbt0SfrgmCh9mWl0XiI4l+m6pdJibWagK7l8g9hK4D3A7XJdyTGDeBR8KTMCbk oDOlsAbtIZpI7sySYX5f6I3hhcpqKji7WlczxoS0Z0Z63YuOiqq+c9WfqRqRAu1iGaZ5cRndQMWi YeutHd4GeoA79ij1aJfMUYqRSUYj3PnYORRpRP9k3rU21MSMWYJgVIkzrYozVgKC+Bk0gyvkfc79 Hd0FeC1qmOxz5dlPa8j5GySF9QhcwKdipCoazfE3rts/xM0oII0oUpOC83hEckrLyUaUL0A1Gk0N OKOtKgPFyKNszRS5v+/WfCFJP6ZnX7uJkKD4NcQC2Pho4m6XBvUbcx0KZMh2kE+6kgJmqBno+S7H IIMI/6NCGIgulKG+UJm/S1rXugUoZsB6DtJMJK0TjfI22tFQbBFCRbP9MoKggCSwCxzMNB0cx01d PUuVq5WaF8fxpeiCch+LC6iqaarToCU+o51WJbDEa4E1ndW60YCIgtcFpFZMk4ioNm5K4TjFBk0t fpFM08UFY1FagB0gf8YryXEWKIOHhtVb8NWUd1VjXoVDrE5ayh3uT8wyBtvCErClnsa0taPx+XN6 eCvwM8ly9KS/iMmquYkX+0c9YwzwLqagVqGOYYgI9ljOoKxhvwJ43sAmi4t8v8nanaVV+XbxexEG qsg8c83rxOCRBSLfsgVPiH1DOQJTqjJD5fZCqnzG3J7u0QxpBXgBxmqkzj4YD48AptUn8vtsGiKU E+6RfiPyM5gULK7JA5DsWX8KoUrJJr6aOw1lwEk7tzcBz7utaZgi0od6L9Zp7fiv4cu/qBV4bpnW //F1VjQEP3jZv/wZ1bYyKsV42skzA4jmsGqHDBnDWYRWXv8SvoKd2FmW2UVkROUC/FpdIVP3NNYb MODSBdhf6dVfylsMEQDdh11T7mM5C/9+RbmZ7Vz5a8mhXw80YJevaLSQK4usLT6VlDS7tTqiLcyv FQo1PPtElGk2XNlpXqYeTqF/NLIcXlkx7FqiCF//qcWI6rIIUJLmS+FOaY2ucQ/OaeRZFKqop2G+ okm5XX6UfjnifxFVGCTqwScKEGCymme3qdX2yp2sXDU93UTn0EC6BdEUFs8jJ625kt1tzyYmDfmc dILOpnVEcP73KREVii35oqDL9sBk4JNBjNR7lDD8RTe8HjJM6/32kqOfSuhOHTTjJbeLHOVuTBss ZCvL8hPXR19Shn/uA79nbf1ZF92/Fac+/KeBWg6Buf5nHHaXELzwGwlI1bY9hGp6w4yyD2DgDXyo ebZOBojcsdzpyxxucHUQZNNqhwlWD2ww8rtK6aZ0OL7M9owXOwXvKa+uElqmBlCxe6EsKRaYVp/Y e5baWtg89yct5JpHgwQYK3X5PHNKTkQcGeWDzKGEkCZfsb6R9E7SjltvYgkGXr3B1P8jcdcZbSPw /MGEYfW5jnM5bRV0POVvz9F8HMISne9lOT5aCBz6iFFyGLSFVghgxqGs9j9zsrPBI0RKlhWEdCSh tIWbQi+tWGBZR7e+zjkcpf34Bi0Gq6jFeCVJc2+0+0cwQrMI3fXXIuM7eVavxJtvWwxiWARcx3fE m8Y48QA4jwpJH9ra2MObAvymPcEI441xAUZ7wwwqwabRrauBwzaeuWuInxaX6HMXwMukx88SPFQg ipZwKjv/SaRVjyntPdsjs12dTTlyQ+u+8htcsynTbpD7sfpgqdKhUK1H7dCWeeNKg2jWhNXiF8+4 bFY2EZP54lWlPO/N8zlf+LKczmFkp9uLULAFCC0OkHaLvRLCWKzbkn/ffvfCfhYOgyl45crNTfso UpWzsBpcm8evKEa+dcU0WX026KNkrA/5FmkZWYfn4qmOfsVes2so9taOWjlbQoSTNstsy/t4QelP bnoRTl9tKIggMnZb9/747ibKQaJHAKpYKRiD0d5BOW239zoCt/8/lmp9smp/U8naBvyx1kXfQPhS SZCiWvfbM5stx0t4qpCygt4RYsspyN7ehuEC+LuW8ZzhamJwmtTKuRNn5ahmf6me3ciAytn2GCu/ BJm6Y+1e/70HZez8gWwtyQPOoHoSnoVsuymmlBvKCcEARqnYMMEfr1NsZ5hglfalVdQ9Nhdln1Yc wLlKEFVQGMBr9aBzp5mh9wz9aw/LtASFjfglpYd4gou+UO3/K0AhFyuDZhTafmGLpbRCp18G+9hJ gZFC+2DxKm2zUrmweCPnRwRPm3rrbFLiAlFdg5BlNxFO10GI2WFpWFzTVJG2l2Uc5eI7OW1e4r5f dyYLLeaDQ0NKZqMBJQBZdUyVi48dB5FtsBAOgIv+84bTDidsDcPxZxpIKQQTJvAjbXJmFRm1W7Vn uRD13uR3zLzFf+o9jYonO4QzoB3IJxFqI6l3M5buG//KBrtuisMejCimBkevyvfFiVkVu5DcGyUk d1X1bbHYAkFpe43ac0rlrTSizf6tq7DNCVNH8PU3g/kJvPQdT0ZF0zNztP9NvB1IsdfGsLea0xDr d64IpRC6Zb6lObnvdnhj20xGbey1vawTj551rxiBv4G/y1zLtOzeY134Yv7KhprIVCrfVOAnfr/o zEKzG+MX+vgSmFJPPEdxMKrI0uAiplomhnYrHTKiFozRCCJfO5AQ9B9L0MBKDMWkaKYcQdmFVs48 oVLjtklnSiZH2sxNkyRwEANgiurvTs/S+89/GoqzHQBkGTsxMAF97zLIMO8xtL6L/snYI9OxGeBq BmY/qgmJ3JNip7QlaZ1gieRyb6pYuqhiFJ3viDJsewsfWLxQjX81WNwThJUq4oYty6B0rZHwH07w FDwEB5nOvURresWVpYWOy6nEXETaVtRDk8aSQNS+te2K4leaw9WdG+uhigFRKLNxubsAr03r8+LA aMZvlOjNQrtWb5gXfBV+yRu7sWdbZ+uiAOihMepHzX+8BIPCOzEiu1UMXZbHPUOjwdwfXl9Pvc00 EjsKmS5MqPgko04IW0cMzxgmjKe0qDt7rkCR8cc5o1a4JoGtv4i8qb4dS1ZczZCiHGKg3shCK7af UvulxhYRVFwm9wtrxV+LwWWB06OF0e+ChGXm55gkAMGAb1W5MUYpvy6tcEn0KF/zhUg4Lge0q2HR xGBNJBkOCtKhx2A6WooYFm1L5riHlvRBGAcWXdZDaWOVJXfsInRjRx4+6mqdIfsTH2quR0zTsjBa V7d08d5AwnW+IZevLs4RK29sIcan74Q/wY6CmIdKh63UZwTbmRCz/LvgSZM486RXoe40KFQH2ZqD 0VS5vcs5+Q5O5fE08OC0Jtegelip434uFZH7SlBSGN4sd0OR+BgAGYqJ5vU63VoWvuAMC356ygLD fDRXMO3JAtxTy2YQVWMB2JLvZTWSZcpdksP27RkW4r8GIzH2jZlFBjr8oDgRG6UZGoOvPYT9G46p jAVLrrULxhaylfCorqRkd1lQOI1jAbVjBCp2ZSzIhaW7NdfFyv30hti2RbXUeupTl42OVjL0t5kF rlBFqx9M/lP0xNEX/ajGQ6XmsoMU2gXY+4KIbbw318HXktSE5YOlC/dBOmhEEfskz0iZRuz9szT+ xvT9Ji7u6p85s8UYMTfOKJFbpzshMcLP4CEE0IBT7uj4Ds6b2uSFUt9pxA7lGkGZP7m0D0SEJCwd h6/TZeOyld4YpVa6kq3I9abGM3Y1a/977ulLNRwKKswYuTqAV8ROhDxM8ICaf8aw6o9mDfa93kbp /c6EAhgyD/2RG93IZB5gQjOT3CbvTPlCIznJoKDJqMRDPI40nlaWB7bZ99zzkpxFxMjFKyirdw/I Cc3Xpl32k684UnEMabfzUaQxHF9JoIXU3RcQ/UZqSQVu2cdSetAnGYxA2+/06O9cnIxsigbtqP35 0gwDs3tZbTlpvnxvjVz5BAnsygbIXLyixAWa+ZRHMsSuiY92hYU6oORx9NbTGk4vz5ccZUsBBkBA 8XEB25wK6e7z9TdcmsChzl+yaHE4n7plbrZZGhAtaz2z2sasUlgJEKQk0L3eGtVdsuU3EzTzsI0X u7xroCAA5iMC1x3eVWzIGLSGn7QodyMiaG9tQxhBwpGgxQzreNsmpIj91l1xglIyz1SdI3y1XAQb FieHYMP51hbuooZBRTSFwkeeo0Wjn2SrJIPrqB5OyPr9c75bykD/7n7wkPAcmebh7EJ09I6ND9pY hUNNEkz4nowCAXvZ1dpT3f6Tl2n4UHaGvoaLs/Y0HBsS5gWvKXiW24OwyioFjc2/xlsqhYfP9h08 fBgltqam/j+H6KTzp3RjWlWlv+z2nzoz8Htd8rFvqVxTpS5dYKXhblk+Mu9TAHWGRMvWLdooRKtd 7bhhwiAghsWrP+vClmahi2/hh4du+mSMT5SyOHI1i8xrSNbAS6BL0PCPWiEx6exCV+FWjSbxFGZN GRgrNTnMRAbhV3hNdEOHc7CPn49ghElYBLBtgM+fvY0mxZlFRvokub0HXFHk/jglZ6gmke0PW1HO 1QKwm7ZapYOGlXAnUMih1NUO3DtH/j1sR9IkZF3RbolNtd8IAquhHxleasNQrcY1H1VFHC4lcaes X0YXruvzCjBEF2NkVsiL6tDOvjwu8R8SFaCXBFmabZ8UBCrrHe2J9GkVStyBP7EcPEOJ5YYWp4ps B2ZNhC5G6vDrbTjxiV9BdSd7gs+/P2FWrFsMRitTL6O6VYUgVtn43kOhPTGLcNjlINxo6yVGZmEs CXfjDpi9YQwemp5HyHUnmbcrAchsXvHSwMk7JRoUMmdBQ1p6ZJXK985+qNqrAYwWBnVy/y6HQwXz SDDn4B2dbQ8ANzHl4TUS6iK/NTWIHGuZ6hcmaAjNudtCuT61RyJls8jf3PLFHAQYeE/K3cnMJDO3 j9E4wNnK4zv7YY736kitJ4ogLEmmSB+unVGR0VfZBAsL2TiSoYZX+XV5B98l9A2c0UvslS0xoROK GIGbdrI/A42xBepoIwqa6cN40XpQLOg1auZQqfyCwmFKY6lwWhyDnMlBwH1iepCkfa9L9x+a76ze SM0keyZgM2mmsC5iZ+1atO0NeW18q2mlXoWuTPK2IoJHbIrG0UeE76gdhNNX7/fiH6D2s1hDQtDa GHpVZHt/+l+TQpgI5q3UAGl5FVgrgxWNXemlFSzfJ/0l6tahiQ5270X4KaXAoZ86n8icMTMQ8HtQ 4/wm7M+wtkrwiC4kDtBxltQFWewsOatLBlRhwPx36frJa+6bMjD0ww3OgaGcpNBnPqvRxZMU3v1U RiHjMvPvdxcrq8ZDiMu6ZiNJVJrc8F6y+BslrAJkKR5+80G9h+GhvmsmuC3MWeHXnru2cP/gS1jc kD0jsdL83ha+6zBEnllpRhakyfjSg/vaEZx/hFiDcNSVIueUpb1mql28dgc9D5ODekacMdc5g3EK WOE3//AcdiITmzKsTKpRVsp7vsQ9pc12QqhuJ2pkh0HN40G3qIJm8/cH2BneL1U9tSV5hlXgPYzo RkcQQ67gDct9oiviH0nX7slYKMey7rssz2IFD89IEKnj7jekueLarPiH8N6NzdeIKN7HLJOWTTyk ddp9F4WtzRqtkRRK+7JHOfWIxiG6WooHKwEwBzReE/QtiNF8O+SFQZi/rByeZQ02Cg5+fvfkfEa4 6IR0ArY7XtUDDeX9v7QE8c0ctForzHzeZBeIlqQDLgHBJqXZ9HR+1QEH5qN2yPN6E6SpKuZKIbDq 5FRALDeoPDncYaFp+vk67AqiPBRKiowOUFOK/dgHfLzDH93YGRj42d4hcw++xLEwdVY1b9uwVhLV NYGYeyT4wxCYiFev0TIERE5KD4Ke7NRzIe4j+hpqY7looNYMA+nNCfYHDnFyYb3NOYI/WJsw1/bR /iB1Tx4BNQbwiLSGQmDCsRo3j0e07y+Zq1zzNmujqaNV1rFXYDrFFroljJwNajYH0ziHwMGfrhOq GUCDvXh5VOeebqvAgkX5gHtujO1Sxfk4UMgmHesQflDNUyJYe6dPwpcOE9LVLUyFJEDEO+NPu1D6 SmdB3hr3U7CBD69pIMNJ3Bzvs3Hb/VIbyFwyY0ii+B3BYLY85P+eLk8xiBVHGomG6KA8SX+pxUG+ 0Qfin75HqnpLgpH5srICSjG7PGBpqi4G8QiPP5DrooFxx1QAffXU9EQV8iWHWRBV/HLhpNzAR2Y9 4pP+icYEk0wAL9vttOdSg0VpandYd2JADjYVUWdBDPOh00cgmGdCZI17PukaRKRIL3wPdmrgoo7T AAQ5URARYHR3uZqTKI5TBAs2KszLo5eg3VaSpRlV2e5QXPnriDLlp1bBktwiakv+68NsHH7CfO2J krNMGdFQhbs4eLmr3l9cP6f0TH+Y0mlMIog3dUAx8C613LV6z4XKLpxwMlK6dQl0mzfzf9TI3YMj j7Vri8mUPBybOAjKoIwvg02vJg40o4oj8ZJ7SObjHFGmx4noEaScL6Cqn3VwIc9A3fX/HjC2htSy cBfDopk2O5PP7rXa0VupmP2oIqP+To6KizOcm6Qog6sh6PDA9nhirgZp1GW388ctxzyBao7/+pS5 UMKVVMCja9jX4CPUmAVrm3dCKEbpkTjt9lHOZrPU4zBpcF+1mqGLIw9JBM1e0CR1OJY5DYKuoorO 94R4FldLpkyiMi2jI4cUYW4Y7ruqtRR3GqFrD7yE6FHgFTmd75I9w7fh0XibF7OdgLBVb1dBpkTg CgmLP7QHXhvHwpB6sCQVqHe18rK6OuoK/Pd/ToP5XKJ+mDAYL0GarQonyIVg8LFlZkg1gn1BY6QY 1eHjiWO6Mh1HGjywmf7mf1RoPz239dAGuat7KnXKhc3PVABFlLjkQpvAxAfqzVg2bTtchn4R1vhY 520JgotaNU7oVpF+1mELw1HiWty4NAvrAZsaTm/OOIe6CnemUPmi0KPR+umPzznx1pumV2gBbBJh +SIw3sT8fjCtidF43rtx1sPHhp/D7boXBsYcYaeLNLLBmXIvVwU8A4aZCKNtFlmupK4iJP3NZJZp h7HL6ubqpHmeANKjo4CrfnnS35FeQbOqNeUaMxwWLH16akVzF3DpVqZ2A6z/BA9OOojkSz3kWAfu 8ZJA4P27wB51d84Rbc763YYBlGFflIVw16tmuLo341oGViwfrT6r4c1HsvJkm6SOlryohKh4wJeC Z/6ivmqE6XJS+yT/Zj/w07egQMWJwgPE6NBBzicdGiXQsQtI6oBQhR+EBnuugTKPN20Gue9eKw5Y uUOMqCnx/uwV6IhhTG8O5nhzxhWBvsamsFnZDNdp/YhcOuKJahdS8/Z7OHrKSbafLdRBRvsyEpXM iwgFtW4U96hIKB/x1GY4a/581VIc6grqqTnfRRMxOddNaU8E5ed23I9Oqwxf8HrYT69J2DcuR4UC 8wOqhTL4ZBcGoOYtm7hmsKlSmdvUU94PXWNhDNr0hUMKmVTJ964GUsjA0bqcEaCj8Ckb1kPBmInD JM+6NZ84omcfM7Mtcd93RnhKpNBcHvA0HRQQIhK39WNDqxKZSrmkHHM3jJ/I7n/3EGqOg4+Bjm6Q S2+8CkSE1zZ0size4Dfg6PdVpTvZKIkFaNJ577KaPcz7YR9+fV+P+vyApXXr8BZbzt4D20FIOyku gRpoQVRMfAVkI66FEXxOn8y5+loRtI/Q4ClBSZULGbog1R5pL7ujQaUYLP6Jp9y3SoacQ4lEToXu pooOnj0ve7pbUifUWCgVCd3xPEeJBJUV33TbNJ0g/rnOtQm0nL3Y7Up79jYCSpVIzvxIRFiVsKyw +42/gR3otU4FCQBh2kUFJATj2z//i9x8AaEs/JqfXBDh/rOH1lslX/sNgWbXmLnEsT1L2M/s+qVh WZzJAg2qu/BdmcO/QsvwxGsbLLfaOVlf3TkRMlQfsduX+tvnozFbGxS2w+LfMPQe3FkFk65fRp2r TUCLUYZh/6Y7cqS6BA/E3NATW9CRH4V0spWb8EXQ4s9tPBFQYAkM3eyoeuo2HkkAQkKLqhythdsJ 9yy45QYsUa9vdu/wBZJ7z001bliXbf5k74Fw7MUrVBzh9G/BkwfOPH3FWS4yA7qBX0mj9KX+baq+ zHRV0ZvSAjZ4X4BU4lS77sVkKQKn1HW7AJxuJLcwP8ksLKMDv4u1liJWT8vVqMjU9X6E2rw8JRYx jnyx7wOwe1EJ/rUq1sJDbbpeorgqTmTA3/miNf43w09A0M/MW/gDr6ZS4+DFLwvSGM9Ij9JIkj4s ytPJSrgJJ5geMPOFJix+Z2ySN1mO17IafFQW7iKG7xwn88bsD5w1abEbGe1sIep6ZM9168xa538E Gh2YOYahD74ScpAnaCJbwgRVmODJqeMklv+Aj0JZpyL1SewmvQ8xftQw1xckb/uswkpTIqDnC5+2 tPE2vYumjTxulS6hbxvqpM1DpSRrjAe1P7oz7p+DIDOd9fAdQBfAgi/GwoGZXddnpBG73R/Wm2V1 m302DLdPw+r1C7/R3tY1v0cwGrFPjgkdNqR38CMlExv8tYN6eaOpF/5aMP5f7j7iSjMEkmvRs4zh sW84nEf75xY3oCsqGcj56vSpM2sclIrF0Dfg8CBYZYlS1LCoELXGLf+aIoXbosPgq59aBtwexVQZ p4VWusRlJ3TxrKtiVl40bjINafan3UpBWO0yriT1o3cMyRdxE+3LJT3rXWek6Vd1PcCtwlV8wSzW cq6NNwDcrEuwOyRlT20i55Mr77bWmyoJwe5uQbD8erFTnVj2dwRdRvkKabyh6GUekaz767y1wWr+ RVhS16i1eI44AVUGiBYHu0vDCRiyMGo0UDI8KM1vfyMbDZBXDFXQiFgdOzt8qKBXvsgyj2yhHoN7 A0x/f8YoG6F7cyUzFgyGdRNmofmRvSriOcENRFNcgZYqBqy0v0a29zIDMmb8yqyxub36f/oRir8x eBvnQJWdcU7i66H31ums8/C35Uwc65KOyX/20Gf67u3m38AmKgjUGsoNxnL2UWpShVAUpqKIP1GL njJ/vJDetioPp/9Ci+SSCsNdI7xCWpcYygtoVtqMeeeWVPGlViCUXumFi6sT+tU7gJDWMFE7qPo2 9lAmFyuVbahJagPl2mS4zSDUUspiGe5qfQJQPCoqFoSPkJv2p+Rg4qQTSGnrX3oody8FoA1EyLIc yNAeZ1Z3MtlSgG8QBny1iI10jIdO+L/8Go9lTmP+Njeaxmj51tWTXLsZl9NGxmG9DTJpkP5hzW2k ESjmxMTtIhEo7begBFAQIMZoR3te28iTVZ0/KxLffnM7iRkrAKgfEJy1xhQbCH/Fp3xNSioMrHUs U8x6ZmBVKanbREv42a23Cf9t4NUYcscC1yfO2lazvjGUcbEhG2iMTZ1X/FdFmfsjaLCMok4LdAKT DmSFRhLjuQk+t7pcDNWGPdJRNB7lVcPlILz2vAqUjdmiK2J5JKBYqd+CL67L55tDh3bW/4KZq/io h6Nz1h4KZS3iblogK2r2czMcE/T4OxCY64wEyRF50cOZbAyjXdqjQCeHxJCTmeRkfjeub0et61DG OcdrN666zTYNtpov/Wn/gRgynBSaYEwxhpmlo/VPRqwwFqbZyZvtKHrRWXndQxzKXGA0H25/g+/5 iy5qi/m2F5cZoPPO/ksETgw1Fsp1kf1yDRRTWfw1TM7s7lr/8MLiDaILVfsyfaQR6/mRpmxo9Jjx gelrBClOB2XCcrvt1xpdTcdFotVl7JkQhxUjy85yXyXvOl9j5HQKUveLDXKXNa51goS5AZQZgqdZ 4H+Of2/AcGOWQGqlwi7D1PoTKJLimHho2HvVGdkkeA4s5zG2DjBb9FN3qdOmTlvPSiMdzKlWwkXr Xqh4gRwFJE+9/apKZmNu4AViqenBnnq+zgJ7O8Vja4f2hZILyA1/DWunGL+OIu02qzaZgD6yw7NN Zi7e8/n5bMuVjOhmDffPc6eKsbZsTvzOFJ6l4cYqJnrem0JDZlpVtB9tSqrr88CZfVt1Qo+2hQSa Mza3k4VHjvYRpxRsWbRD3bR7Etet8EeWG18b7aUgP4TMKFuW7a3QqorA3tkIebSzUEt8TO27uBq2 3hyhgLaCP98AgtM30ZBngNf1Ee6MTwgmOlIQtxJFP1iDF7TOKzg3jAbiTYlljBHUEv81vUF7neZF YCp1vTt9QLneRMe8XqaWCLljTKHdlotT++ph08UaneOOmIiuuafXpkInF2JMqBxBUMVuACdNdGfl qIMRIvDouymKqooFqWOFQf1f6dL8OtccNizRfzkTBKy8i9h88dJmjYoV9yt7Bskdk/KW7pdSMjGG vcxOsOaWK45wcGjtiWiF5w0ZuihzitUm0YadeYrIODvP/F6g/GNDmnJPjtPxVGxg37OJx0XiG//G fVtCjxwTWrdN03f/wnbY8OSSjL745WvQ7kJIPT4DGiPTaXXb2DT7h90RT9EJ7MT7smCubUh5BVvb SntCj2pm2ajAsPXAUdYq8eIgORE+dEm/zjKO0hfueEDTPQtAE7WAEScMIu5rL7lTgYCuEkMGcAIT V4sqzFoqoCdl5ybVa+wr+Ms07EwayzmUHZCqQQF9SKKc4N7c8P8nFui/l5rTsxzQBiOSWmptc9tV 3giu6Z33nhUEZ3ts415SiADhrJNg+SY7QZYx+XfJ9hONJLlHkSyqa+SucYJb32n6ftuwpxPHCq+D 3KfVn/amuo+yIITRn0teW5B1eIeTzF+tPvuU5u0vxbMXP21CWATT2OTjrUdbuq21A66cp0hHXZbE b0e4LccefKRmUY25XIVk7azf1gawEFEZuqZuRvF59bayAvSkEY0M6O/6YjEv2zveTytT2mFUEEog BpUxIr9JaEAU5zY5f0FgCfi5QOrr0zedQURqKQvfc+soPHCtoaS4G0uEhOKWdGpo+Mne8WMNWJEd wfprqtnPGmcEINC6wvOs0TgUzsW+FBT7QGtXBaXOV4wvxRmPhQldPvvRNZflLVwOhSZWLO8FpQ52 PwgKz5x92HgOMMYqUrGOyu4UHFH0Lvmv71YXe40u8LN34sRLwG/vYJPsidp4WwY3DgoaGtdx6gUt vgeRQVuxkhKMEJyD8EHYZ0gGgsaoUZTKgaF4iOHJF3meaufv9fAIH1J0xk+Cy3Yn9qwqllbgsioE n16dU7IL5XXMqe+AkuVJe/lrQIzMaURGp1+iBle6SdvbjXgs34HxswO/e6c/2OGS4+QQ9OlFh2JX Lm2J5gavpYASpFMJgirT0aurYHd0dZ7BrLPgeMU+9kMD1eIYAmm5CrxcSwjBQgCP9REyqItoaG2P OGH3SnCq8tobflgzBm8GjpNmhjUPpLHYL722vMR/t+tjixpy1qtTlIM00wIJh/GhWz6QSvy/0oqL CjjhcE4iS7f60Oyy9D8PGTHlmmC81A5fkitU5bhkiLV1WTgNzF9cLy0F9Wv3PguMmClwA/AbmO0m p9WjpkVZqX3piDlrW+ToizToUmia5m7Ft2668A5esPUCGQS51EOEQ3LHQztlt7AXXVpc/wfXLZoL yY0JTsyxAqxiuvlX1au5trCT+wVjz1YLzqGsV00gCnRyhoMvCaXZ+MbyRDcF4B9s/yRRe18tDifC qYPFr8J6m+MzZIZPLSglSIsKM8bpEPfG+WMyhM+XdTIIgjh3wCzCmr73rFiyLpk6ylqGHuwYErsu NdBlYQfPMjayzSbarxDnuYM6gAkPgk1mubuovs8P2YmkOU3U5Goo/NFnDhpIn6B83lw79NRly8lf 5PHypV0yBlNkIdJbrB8hj1pWsNi6yJdETWBzkybWYMwJPMQWhLO8pYAAAAMx/YHDAQzNwjWfec3t a6SrN64jEBZ+PVxIRv36Vmlaw2lcMrMpQWrXSLv15/N2ntrc1b2AbJUWMrNITpzF2UBQeUE/Tlax Msy5A1JBOfkZBeNDKI4eJRZ0BmDwR+SnuBUusLuuwZdScy1/v1IjijcLIBtppMSGlYtchExyHcsa GiQMIWbwJywHiWgnhcPzpCm3YyLiRvchr9TLPvTeRmGXh5uuJD4Yqb6l1CcrPcuTrLZy4VONQ1Kf nXUW8dUBbF4Pq0FERaT7tGintNevUPIuR1FDC+CfjIxWLbDg4wUD0s5tLpMNp8fmWx9JcuKeFdjt 3r+y9q3z2aAowwxnDrPU5LFHeHa0GDrfBfij6bwdUm3hEHyAbVaxPpsvzF/2GxSLuCosWF2qcVEv eMCDVZlL7eMMv3ooicsk+hjuIX7Yp3NnvB+XwXSLaaHpm1mxaXoX8bSVZ6edoLvChrC+M8cQkXEZ Gof2q9qlzoSeJS++N0cwSos5sAm7b46ecSyuFKcZ9kLeIm1xxXiVSwco5hy/B/k5harjKVyjdgXH zq31vBZwCh+OMbgXZMGd4W4Ttyw0d2vbOMZUFQpEgJ/aDIE+x4/u2LVQTX74MLV5Jwdd1yDJ7dWV x5UcUM1aDBji5IqMUjNU+VdoJcSCVanvAea0ZxTAz7ABDKwVROJ1/wY0q1x5Seleuk0Zo8Jygn9E C5rMAmLIRn9hyy16o+Q5l/p+Zu15hjtZIF5SqOC3/5H4ZL6duGvVp2PP4G91X1+JHGlPeoW4sNdF 0UD/3//jX5JLjckvGK5hTZQZ4BcjI6prxufUJBS0SIX9ngzA99fzIknaoJYYN0b3h2WSreW2G97v yzaP7k2gfcCfrLvoNzUx47rMXkeEA2YrCPE8Xm3VjSWHy/KdchHW2nAkhPgW04kVownDzRF0vFMd tZDPAygM7YumZzPDQ8fAyXlwkhe4BHGKJz5Tnunf9y5oIbYBGeM3xc5ZcOg7Z6Y4v7e+8N/Bcj1j YR4ZUp7hjwi60flQW99wCxgDE5yRw8ceQQZtDFH+jqU8Hyaq1+eUxWpOJ4tTAZYal3EW0uBllkV0 Dn9H+POef+KqvDWhyYhZMwN0BvLq9PdKzAxDmzCvr4eGjp5sEKhjByTSMlb0k+Ap9iILNZgwfNIh OWLSFtBPJ4taNGtrH+qEVxrtgXIoaiTLVSoSQwM7AQMVJBHjMph4ETJJt8475Qv/8OBrcglVGHyY 9SKS+LyoCyY0uk1S2r0ppH01S1tZ+r5+QHD+WZE2n88/r62rkze+V1ml74HrrdJoAawARBKUJL8w DDLtAYxQ5+GfuwisHbY8nbQ30QFuh10QFPcAf66BVqsQT411Gb4QR4YOwNo8oBpkigoegSwEgeJE HZw5jYCW8kkjSz7RJgEbHUVywf3UxvnedagM1un2uN+BJzp3yxzn3FdhKX+dqv80DCLlblx++Fk3 c21MWCWLTL5XyYIxjJ+2f0ELCEh9H4bdbrwc8CK6xKQH46EOMWNnRUjixqtObZ2dNmQaywFcyigM 3tBAluV4LXiCFw71c7UPKOr2wTe0YX8bmKn566ujSM3e+frEWHdnHEEQuZi2Y7haUvEHQvJTxAi1 I8BuzrXNUwFLblLGw69SgDZmfZY1DxEVdyNdEzT7pidYJVPsAYpPqDvrG8nXH4ETvB3JvrXbMrjC 1KcU2horlj2XP+o96hRtO0ufo792mmi/mmMZjdrxtbm3RQvnIbM9gvwKBD41l0c7Wh8TsTKoVDBV D1+uaMBp7EuPPtXIyYeA7xTwGgAk2v8BS1va4hrYEMD90mmbTCBH4lgo6aeCsoU1DCiwXihW1nY5 hqPv11jGjmvoaDQGSdq/dIJddpulpnQBKlYUpyOTraOVn5AHQqaS9VLTXInE+DLnYNjPgKh+h0X+ NKhuwIyD7EXaAHaOLUf8XaQqqKr2Y7z6hQ2ijWsHEN2PWaj6W+ANiGQTgBQW9+CGx3gZhjkaF8Wt 3xpPqkltYKi2YhPVVQNFLyoayuuMKpG7UDS2to8eN5Hct6n2hoGZ231FOG9k4iTXYVQ2KYegvwaw jhakZcHhpOSna0JUvaIN9pjWoLinbiTSh8bHiMFKhEQCEDCFJxJg9Yc7R0xEri+FJWpluQNE04Tb vPX4JSg725DCipUZfP+sZOk+DcyKQK/5QXwbkwsPRiv1dve5JxQuOjxHfX6zBX4tsEJI32NAXBbV Z7WgRnVsNoTZv6C+XcZueh53WIkiIM05jVrIJOaDppajZa6lL8J8Ve+YUAMbaRwy2N5eMk4VDIJW XwSOIoFcI9TET3XFePQYEnI6+dkPLLf42HBcNAm60WbMkBcmThOQxrc3oLVvTAneueTOQdh5tqco nYNxW4ig3uJhwHR88kNDcDvpZLEyNRMt3oKCfzCoyY2QYbmJrlBD/9xKkH+LR16M4sca3U1TQVDo 1AXZi4tx65umvXng001Yu7XLvdGeAGMwvNYQb/0DLKrRDkAlqHk7kLhgwKXUw50jUdHsV1EaCUhL XyuthZJJvBMNODz2WKNDmtCZf5cZlB3d1fTql/BZpxXpwqN5YiXRuylaAFVYCRt42xG2nUqAHQrR 4KTi1D9eBibi1YLRFF0AUO1Xr7kftWPqL9OHnFmJ8wI65WlmSUAh6DyANsNu2UzsqA4XNfdtXB1E rsm/z0pO0amOA6bF3tPFdhTgoawFntYrCRU53q8rKd00itox37SaZ1MAyL+PGDwE7B2fL2Kpnk4Y pK21I8nZ5pj3WsIUqcVK5f2Zf1VvwcKBYxXZ4v9WYlvlU5FO6L2JvUTG18/BPZG5SB5sy7iDNKxo 8WA0N9HoB85dOTop/G6Uz229fzB6qyZJi9mYuh4r6MEbcn0pk7/KcLBkXbPYEIizRo5XwcaEfvGv tk/NonEut8qa12dvu/b6HTIOBvKTLmrl/6kSpn8qwCpeY7IlGvAKY0q9Ec/6i4NjMq/S4x31PovP xvUSWx2ACHscnoTQFWMWcH4+eKxR3c1Ut5NApZWhAPgg0/4ixgI5wtvchz7kzTPx9w8A6yDfRfKI 5JFSFNBqMO37G5yrZ4ERt/RDCILg1FaONQrXGGkt0aw5rnBBC3LcBHwJHR+1zMI6HCFKPIQkSLp3 nk3+EF7ViACD0WOxF9ssKbvyBOZBZoOBUmEhtpCFcKFBckMLZBa6ZUDycRqLUXYKqeGPo0CeSXgn hn017cjsC1p7rgjzpx2ln9XtWfyJZ9JBdrbXiywdZi3y1abKW4y/7UJr1DWhHeAL5YWM2iuvZ9/l 8WLUSzxibKq95tVNfD7+4DyFA7vF4EW6At5qfsGisTOy0ddtTOQLhK81o9etIrv/dvKNXv/G4b1j BhCIUmLSy7rM7Mf5Vvg8MGlDBjLH71UXgyzoBqoM7G5lzbE8lNTtjFY535vYh8onn3uz1P8J8cPM xSo9CknHVxzwbnd6an71JTpyzdC+eG3fTHs9UvQImkX36citra/xtrb6UcddyTIj3KcRfHqSVKF8 se5gOYUxBrK4IiYk9UHMs5EsCvOHHI04E3KD7bFcj4i9crjmgze+/zcAdy2FgKzRLx0yt2qGVZET X/0zs3IoAGLU4E4+my21OKRgEwLc6x6C65C3kEOzxKDXXzStCQWbLzTCbVpxH3hxEjNKWtwYDSmZ w4CTeY/u6kJ6hoXkZckB5whJYJVli7QqBPUOAu3iCohrS0a2Jwd81eEXrqf7qED74LRdrf8UUHgd C6ouWKzNlJ/Y7a/HfJQ0f4TZrjWmWcYCs4tluAIm/78g3TEATjvOmLnDSgzr+25zbGHZNV0tlktl BvyGe5EyoPlrahrDVHyVbFoXnXOwv9zGyX7FBRxJONOxKttIx3AiI2SAZ0Ww+P2JQm25mSpx69i6 czZ2z5/gQWwV1xe3z1h+OEsykhg0YZI1bVVQxK7ENkVETuYCF8xIGOERGxw1Dq8YOo1a/XYxqM8z XczJcONJoFH7gsxoW9xziinkzgEJAx99vzLRlH11A4mx0r2OEBtqR+/Y+e8wnKLA/9Y3uYV0dTQU 4pCkOLpA6Qah2MuUvWKHQxPZCsE0dHX8cJQYHy4dGofEwkxq2fwXxrayyjyrNQJl6PP79MpiIsPm 6B4lp44Zzn05S97cCbB0wkvYmPs4OKAF4aRaxcZWoYxjduMb+c/36rIWjDHSDfYsyEtHGjXYkZYW bIKmZ68abjwOcbkoN1133Ujk+Z047nk31gsxr+zC+t34DAbBFfasxSbVfgQwU2wCuqg07rQ3VbT4 FdM+2YN7iTjGcundAjplQkKdHcQayfz3LFXCqkr4lDsqVKd3KCrbqRIBumyJmFC3ckOBTL7jHnYp Iig+6WOXGEBMO+lopkq2utK1y+iCqcwMK6MjEv0VgvAvksINb0VYPUhhdXC0eNxRlXyTjh7Vk5By Ie6Ft4FvTvnw+Le2jUKL1H2Lu4M75HfSZeaQCevRkPlbxZhQ8Sozvf8Eoyxqn+R9WryxsppLYxJv n4qfb3oFe6p6AHwHXtZXjk8q7/7SdPyUvole4l1nK7oj9a8NopUxZqt+hCU6ZqIKvu3tTuRKqK4g BddsdvqH/LTXldhXmCTEjNDE5btnLf83qNp+OROoZG6h+f9UeGXBQaCecLARiDUx1VX7/d5jT5Pi +AO/ZC6aWAjr3zBeXgAZz1fn1p1/gOzGTU994oiFVehkGdRrUACAm/+YLT3CBUqTBlVRg96a0vOt /MAVG8oIPNcBowiIBoXwayI7zcMVc38HCuxblzZqVuoutx15RPnBsGsSLjKfw4GHbE8NO/uw7ikO rV0ITEhq7WnKnmGsfoFGpTFMBEFku6Sw1mvY3x4BBWP80aEwt4l9p+SoP+HGpYABYEWid2n0b1sA QssIHdqOg/CiAKTB1Lb4BxdHzYU804uebC/ZFGQYbegdjTnb/+ay8NnsoKyZ/q5daGrjJs+oeewA eXxccqLAcW/nar9H3dm50OzoqqPEhYFf2DsVdcU2jZn3DdrqEk0+eh0ZxkgT1409GVkA6LESPV7/ DyyP0ORNu2iwiqCYkU3wQ40m5zbav8Lt6/PKjr6iYydP5JWw0aVbfFoPOsou0CvnbZs+SXM2BRJj abxfufouqGZa53AVnSlUe4NkuHNACwQJfB9FsFgcV2vfa4I5cq9SI+VO5V1FVEsemHPBKwqCPg5M 1ZwCrOQEXdavBIs0RJ0jxISiik0Gk9MLA7+idPo4McIr6rtxVpffylMnXpOgYu6Ct7gzRQ0FNXxN 8D6nJK80Uio/pmpYuQpoAsGuXaom04auu4recnvVFjsQpLnI1ZF/ovd6OdfAeJy6SX1Dw/1X5qdt 5CPYOP8o3F+V5mXcHsTnsTh8GbB8jc7h5N4CmvqeMZ3rZokaZ8Ulp8buEk4VIJOta5V2Tmvb1DYX 2Su5KcF4hA9e2LWBhfboFZv4qAtaaltdYpkHVtJFBWlSr52N1J4orGsSFq5HKSZ+FN1Rpsra86M6 QgNBLY+DhzIgk5aLErAeUokTGfibFCBPf7RbOxrvdm8KNWb+J+699L7vq7/dCmnf7zhp46T6qH8B 6NhTHYS9DFxicQSk4Alp+fOI2hLHWWRPs84VUmRQvQ5Yp0mmUwlK9mXr7NYAYlaOvW7a2GdzQeVs IigMbf/UKZ3FYq8fePtVuefMIAW5ldh7DnQl5V8pQkvDJbL7lKDTO2uJ8h2L9VrU7iljj7Ro0zNb u+QXGTTlSVTTWxl+y9JDKFfyeO8gEXxDb/LAxzUSTgSd0UqJoMzojVHKwbPBeBBjQXhY9z0GcMNd 4OkMqmRR65fN7aHxBAU9LdJq7TgnSn9ABgcHbS41FLfLtEFsK/GK68/ivKxeXV8rcytxLv/A2dYJ 616YXALzxeMWqkOo4hz15W37/jCt6FPHbfZxe2AcoC3LCTo1TNrxK3pe7hQ//CaLK8lmmzWSiouW JFIRsN9bvd0v3JeWEM6Zqn3SPkuolwxkNWiNYVD/zKeKUc+B3E5Rc4rDFZDz4P4my0oqH24Plbmt aaEcpnZFXu+iU+JImtnGErx2rWre3qluWYxWGnj34+RdHVG+LZJOP8f7vAvwWS7DSvfJ6UKEl69O 7dKP+j0XOgoP+rLX34nllQgW7+QQO+MlOPYgKHZsyhaXpkoyElJeYa503NaSdsdUjeIjOG80SpBk WB/K52xrOHf76BVN4fCstqXJ6+FnWt74zWXCDWgqT4Xa8Stj/QWLGucEjBXivcM16804kUZ/56z2 V5yIxsPfzDfyMjCCzhfCY0ND/uMKSSvTrtoLrzSP3m0lDbNLIBoK87qDb/khfQq1LfVLVGQ9jMid 8cDBC0q7FqxfW2SZamo9sru3pAL9twPyXFFbDhVVGlC5dfDlr5VC8ypigZG25P0PRU0yuIDk5yBo 9gC5jMhdOD5LPYwc7IYaImBk26qnAA3El2BLLi88AB9c29rCErgSVhvX94x2S4tMEpwFbD2wXFia bk2OmMKDko7peP7yPp/TfxI/2w+UP6PUbIZ+gCbQ4rypqICEk39F3XO9VUE7mZk2l6p1QzAYTpWj XfYtCgVVieuktKZQZha/2feHoxFxIaUalMBKk9LJujtEjUduBeWDtnm9oV4FG6pehF3wxH3paxM5 JwaMM0NogoPsAvaMBYdC5AMiBVkq/fSzVUY4T8csNxIBWQECIXIb6T/0yf+g065aLtGV7QDIms1w rrqoz4ihgFx1yP4qEiV5NrrB/ksREwPrhaZDfB7iRP6hpa9gAHXFIn6/YYcsLs1iWrTDHWiymw2w enogw3ZNWkAbxKa+eOe8qbusbhXIPg/0teRhJHcG+yxGT3Qj2VrJ5XBlr61BGVTO9fiNd5Ezgppp QGvQPQQU5oYtYn7yVIbdryRAAhMrXiaZBZS7xuDw08O/BLoAVCCRt7+8296gK7hSWbkIqlU8TanY hXujgEh3nOxShw9uuxllwenD0DeTFWVkvBSU4iIqh5v9nCQLo547rqVk8DPCdgLmg/01iOD672tR WTf+fP+6Ge/ZMoZqKJCLhjYGhHKY7+8bOQH1O1D9A65cJlUS16t/pdNJoH8wzoEiFqKSFl4x96kn CR0VZ5hporpllWH0y64ruSnB0pOVyNRGS/ivPf7liZsVrlfDp2AS7auCdxsnaFgPQczL8fgqVSsz SK5u3/q/BA18V+xzxwMoJOwL6E68K88L1YRtmckq0hEhzbn/+VIrztpDqC9lVu+s/VTHdapveFpR PMh9K6HpdRonw4Lian3UIKgVMZRqk0eJN9bO/1gBDpNp4pzl11b5LWYQmKOWX66cY0y9JpkDRFrr 8ZpQWTeCKG8puHKylNsCX2mFkMSnQLJHvCwfXU6b2avPEfxoC2dXIxVGgDwP9B4du8jDP8ZjhnyK xQ2txFJvtb8r07YCimGR2GPZUkKFg5L8rYQE9L6xTjP9u7lGIOq7lgyN48SwKYCnRvOc6Eok44cP O3d5NA7iSSI73rJ6vhAkM4wiLvv3O47G6yJuzetGnsvcNwpsFgKxZ7/e5DfhjkzBfBp/3S5pS8ti R9U98TvFofHQhaAGo8MHi2a07sE0/zB1LbOX5Eer1b5MOl4umNwGm+9dKnGkObwFt4sh8Gz0L6kb 6Ojguz+llwbsI5vEk8FGLkmXm1XpxV5kRSY1ezd0wz6TXBB/8NeslQHbxYVJ7A+YdQsmhfpoUgxw 1dlYk/TV9plhhpWguLJW6es34MRCNa3ypHNO9kdOrDL3vMFIVrblQJmtvyNy4DSbwI8qfqVjqxDB 12haETCoHOZ1A3kE894YuTMQuRrhRLsFoJmU3ziuY66sbjHQWiOZZ4Lr6HiRhhDybE7rBb+c66lP 9m7Uiu8nZVXH2G0o50vzfZwgCW5KF7oO50eJMOADdCp0kNwZP9L0bUBnA0irxHGSCtijNlt9QeWj Oc9xhz/+EXjPTantZM5q4jqKUwR/RTw+p2ctZ58wXYpPKubJLKQBfqmsiMHw/5eEqI0nooQAZ3nH UoJ0iTQdIYbxARCxx96hVy9B9N+Nildb3aYmLwKPghtmViwUELkFybig9VyWfKbkS8PF2UITl6eK PS060/BETAvnh5JjEKGDaaPdpCqWIz+iVzTUy1jFPRHLiM2KHD3xWWAsRGq9pQ0k9DLWmAPpNJTS 7ISOfS8WOH74e/IjUdBE7dl+FVo+7gUO7hYJZAXfG0hZwkrs+L0Z9NjSVdqp1UUBpwQXmcOvyENQ kWVJD3nR1Oa+fjS+Vg17HxwhX+3Ve/BsTu6BCi1+9u/y1AYsgBDbL01f6dL8OBv53l5N4Q2AmZ5X CsDcd8ObrZ1bZA/2O746NpUOusWwG+L39aZEm0Rn9jxKKEfLN030fG9h/hESt+dIdciwPXcdsnoS ABh8fyVAQnOIXWWEqNKbRfLRsREcx8IXoAXr/woXOEcIh2jvavEwCzXZXl6d7CQxT3sc5OHzAdTm XJxqavBUseKoxQwx4Jtl+kaBSFtBb2yDKLVs6oSphGgsGt+HkyeePnGccaAz8KippqrS0+ns3bRK ZdTo6KO1hgu5qU2f0wnY/CEJ7rvqQghBZLxA7uz36SV+N+gfmkFRGuE8DS6C6rtU2Zdpgr8zTLjJ K5MBTbn1KnquLzsjc5T5s8JG5OregJ4k0rD8FiVfBMcmKcw2PgUIdFvQIUgNm5PSAI9hIZJX6SCr jH7BbSNE3WpGkzvAU0+hR1ap3phUNTVLB1+lfWmaeeM67r1yMKEcjk6ujzvEznfpnD5XGe1YLZFh X+yXRJBAz6KGdUtgAS1H+ERK54OJtbiJtCF3PTYxyNIML0QKWbZuP8GQYFOBLCzkLQXiWXqop3Qw hI8MtTK1Xwc2ltszePZMiJBac1D2Zqa4laA0PeK4JUuvzVcVksPfE9Q0PGyp4+PHLSvE/2nkwL7q x8IBi+xg/ZsQ4n6MA63mvFHHF/hTHzVvfArnfoS7gaNCYLEZXEOMkXdTWi7ZxGfSmz3ERb03sR87 cjgtw1AbEgLfPXP+bUSp5XE7X9uR6xdaR0eeMOyb/OtEjqCA8/2OEMxHBop/szWZjdyR4ezYuNT9 aTxcoEXjjNE4O8uc4JP77cLyC4OnJ60/ThS5OeCwJHIiiNVkScmMb1b2TuOftiW+AeYOsnYlCRwc OEPvN+RcxAjG1638n/VB13Os0Z5d20r2RSDC4+1Wu8PoeUHthBG2YrTptw78jDKIKo9weRTBN420 GiRxtSJX/wHw9hJS7cD5AXyksjSk1ONzypiqlRuH9Rj5g3P+vbxOmgC/pGS3QLeY2BZfPKH9t0Cp /vjCvKpX/iTClu/il+NyLUwyCztsyw3cn3ZEz8Aer7G9YlNgOgxARZzXLypt62wPnmuHxhihujGt gb3US/c2Ifghuqs8hbUmpGBa8RK6yqIdRyOOwHTSqS64qf4dPo9ySu+PY3lHAwxZFbne4PTXv3V0 WLfT+WURBYE4qj2gX4OYemhk8vJbhCfiEvlXW+yXxClOgmyLWAyq2aZKapmVp7g/WcVeHX6rYps5 1yDv5ZqQEd3H2hEP7xmTcbg/ashtcNX2JkULXl+gebeuZyV9SDtO+e54DwE2wG+MhZ7sHd9YG0bJ tMWrYVvT8SRPzu3b4PmYA5nnNzmvItcvatfZpFTppAWSODdtI26LX+LN4PbBB96CFYEyDCcH5Dmk U5+Uqk7+cAsKXJmNTexv3XxLSxoN8YnhZfxGPrPR6MKvyc8B107LbnMc5uxcg23rAyQ9CIyhZ131 db2JMKFuuns6rNwPvuvqWMH9VjpYBR4o9wnAjcMfJ3DzevTMyPqFiDVQBDuRjI3+Q0z5JQcwpHGw V5S7fyn3k5QKTNwibu0li/CP7E+VuCaJ+vPetenZuMCvH11wEjgSyqnZMnMt1eiMKPxvyGRHnFlK /6mKKGLmsl+kBKpqSOPPSsNdAopmK2txyzSky+J3WYkmXgBEGCJh0GPq1exs9loyHspA+Id9NQOa BA2lKVMt17y7NcH4HId5jou2UFCBYGvH8GUaO5qInatIf89HaiQTqd4dCVye+ckSgYHjN5A1bzz2 Le3r20Y//RtCMBIsMeJChif7p10/FOuohc2USUoO3zZ9eiLIR2+KWsc7Eac35CkVpvQ2vHGaf4SY kPCWH6TO8yWpSd7364QtPHCZ/dwJ9DrpMeTytS9VYWyYTJYXKeMKvbCP1hwHFY4tGlIbPpNjhxCf Ppjuw4SILIf+uWMjxmIAu/vv+EBR9h6z6wA3a/Bb2HmLVhTC7uoRSucWKjG8Tvlc0sxZLZ9GSbMh 4LzD0LM85TMo9TxzUbp3s10jjDC1OihmhZoq93BRxg/dfkKrP1lP6exzFzm+WR1+/eCEaXinlVsW spKgjkI0ej+azZh2FQx0JPFSO05MVOyNxua78AwZTpgUVropf6EgBIPgmUB+hscAU8z2XPxQLP/s jiVRDA3WsueItx+b3IMWrXQXFd8X+Mebq/hIvjD5QtlYshdPkgrNb9WQz/4mEnvnZhXd0gLndpp4 2ocLRo4TWYC0crnyhwyf7n6Z1JhV/wDRinZjlXEZssG/lqLtjZ3yDYFk5a9gMscM8y2yajnWKpZv 0LZxp0MYZ3pqeNUXg5NQ91LdTFd36YLE544UXBpGozG6NT9sx3yvCBOftZUh18jfRSaC0qF69xDn W/GV8Me5ZWz2csjn19ZyOV/a3X9ZoD0lR9Ji4tpQvjk6/8QWyVwAFv5wtPmXQAN3hGrguphVaLc6 j2hqn1QaYb/WQTQ4stMGt4Bnt4/e+RMbANk/FvM11zSqIOsCJDa3mdbY43cVNIe8X6BMZaDu4ht8 pqiMJnBQWko3GFY9ZhMFn+hWRR5IiBhy7/WPL8FoupU+8itmOmbJzJr+XztZ3dKQpjpBqGT9+O8M gQvD7V7zFVd0VvZ9NyD09xqPK4wpYkEZ6fk1PbjMgkUzQ728WI0JUN6h1AwcxUCGWG6Ki/g9k3yw wkGG5hITgbizjnoA/pQ0oAwxLeY7k+JeGlHkBmgsKzuZoFvVhtFAdaYMnKRK7kp1UBSoydlHymLi ZX4QeBf+GCBo2lnrxc9zRVNcj8NskZbnaFRMPI3n7n/IdwymKP744ixOL6pApdQC3yO61/TwNzz8 n+cnXDevqQ37f0yRnkHLxQ3Xu5qgFAYfScXlSkTi0Rmnb+49ztKee7W3ngwB6p1tCFbTpXQxAxXU vnpGVKNeYu6hiTcyqpYKAbBsroEk/5Yl+4/C2EOe5qRCwM+kuPJUzX9VdMitH7+pYKWV3Jb7KfpU E95zRH78I3Zs8I8taWjfvGhpjsb+z8iKH1nn6d3XbrjBThfzpSbcMh0Xm2TH4qBGMot2tlc4hTz7 oMMdsaGd4WBLKhx9wD8NmrcvtGL/lBUeuYc+DxJaUwLLthTGD/85pNTZx+X4um3aQofuJ4COQi+0 DRsEamJV9hvae1TWm6ylH5z7i3xu9dTdG/5Gj7kNuBx/z5ICP8QGxj08WvtLOiKR4gW+4NCybGAU 4FS0uFZ1tZ52qR2/197u//sUFQND+QzoovUTjQV3igLDKD9YnHFVxzr5PUhDxQOb4Dv+cqqU/BMk rWVd3HPapCstyrhwaVpGazpZZDB8beewHx92AVB1qZ3bNb9CXYWqz9H2Fj2OXJqXdERhIPL+SkP5 aux70IXJO+oa06pCw/x7bJprRldp9ZUSxNWRhDeHe/wyE4PpZ39FxSwHB/mkOvXhz+kzTfU1J0x9 wxSvxPtoi8DophG2rrvbsfqmUjED1IddOMAaafspB/4iEPQnGKk19/Mljzp8MxskkMlsTXTCosUy 87QThuapSEbWd4ET90Um3bu/Qv1FdV1cpkD5ZKTGtoc0/MZ9ZB+pK+eP0RH6qQcsydoeYcsRa96R YOVe0Qwzd0snE832CGQJs8skGSuryFxQScdpdgQwYHcQKKgVY+XzB8BL8R4hxo0PPk3wM1kapJTc qMeiBdT18f85bGvWa7bNL48rHp6jO9kkEWP/8SsDofEXWfXVDiXGkyRtCzhabcQ21Bkp1uogMusS y8pkUvZBsTAfjj9qVz1LJBBhaxshB6vejMDoZ+euaXGqsgnSZPdmNFAXJtICpjoJgnTVcpZn9fGP jaMtdouH4blxEb/m5rQxghqD7XJOiIC1h1SRhX1AkbpzxKrzT/VKs/opkiAxnA0+sO9sEWADqnO/ 5tD73HbB4K9m0vL0i2anpeCE+lFklbda7pWjA/ZLqYAM60cbMLVFXolIJoGYH4kPgTb+9Hzf3w1m lpkg5jX1yAB/lJMHl8A+B7ylcRYqGBxsFSLb4Gg51LXB5CqIUFmlUQyfVbbyVVNMTi+tmeovF5HR GeU2RvPoXbsF7T0AVx+7QhoGPGDW+JDeHyhJuwidvvReHqGNSHvp7TX27gUlr/jfVXxveGPqf7zC mDZPaeHyvULsIuz56QzL19yryE3VIbKC0WetQPMwU/Hvi6aHaYTz0GL3/Op1Tv4qe/wOl6Ne1feM Y7Z+qa+pvNSx/UKRBvAy2NHXMvT7r6CJZEOdlBi0xVYa6t3h9ekI0N5hf9DMeNjzle1bJS7JV4qp 7yLZh7L6ElRN2HqJMzp/nTtAlES/x+vokk7LKHe3kMwlpKwbFWMn/gBRiWnpzDHk0IeidS2YYBK3 iPQr0qoj0v2jm3EGBOV/ljCwnqFuhzJg0kH9sBEpjTrRGs5JWl/TuoAHGza5Nv64Y1fyOw9bvbxc wB1KRRXVQ5S9tWv6+broTp8ZSIq2nGtuYnYiimqoQWt3psrduHSxpRHiZe6hogkURYxGkWSK/Wdf DkdV/4OZEcc4nHtp0ZPEEDXrJvUtn0sZkMTELNocWRUp1Rye3QMv71ZuRQ1Gmdgd4DIrh8KVqaPI qcKqcH7d+jtWFGZqfN5I2YlAWTVtzFAFEkJzzkv7GEifIKLPVB/d5L7nIZSjV11g5ZfGnqTi/OY2 1EJ8Fhx+9wZ8LRXfGPHe5AepBGAtWHqlaVDNWt8qxLbQYEL3NIhEMuZp5PtncGUfPhtr6mHtyIcT O8fgGxL7jAglqYzy2uIAYF48u2QiCDhfbvJ37CutmYL2ByNDspiZNpmZECDm4031Bfq/cO66a36C 0kT+oRiV+kmYvF7gsMqOUYxmfyhqYIprnWe/3YdsXUEU8qessYz8iEqVCApfmgkc/vpXBF+pRAQw dFHiq8eVuU2CklGKzaGHogce2Yy3LQHOs5cjADZFLYSNn2vJshzdsGyFGzA8B8MPHoi9Ydhvco7p NamDFyBYsP2S2J55bWl9KjpfDrBRF0xoNrFRmDh7dZJu8qdU5IIsQru6pP4um5lXw0sO5rwYFq9M hUmm+rCenOcNdOnAzMwnFP62ZzGYK+AORBIGerWFEsMYaJ7FW5VscWVjPE24vx8H0+gwvahq4IXk evzlQPlBujF5ShxrjuodHvQPcypdvLTKDuTA9z0mFYgRx3a/MrW1IZqY36JES8zkQwbGPW3ND1ak FelNggBFV7ISQCeiE78kMYmHjTrF9/MoT2BDmAYZyq+ZHzMLis4OE0WVHA/uiGDtyg4e6ZgBo2Ja /grwT5UU++rWXUF9IfT0UT4w2jkGFf/HKcAujgRP3gRVF+ri1ZCUzAd1hr6HyzneerJifkYVSl8k VJ21Vv5y5HYoNjA+p0dlnSVyYOYjc8VHfm8N7rfkJ7zUSRLKxri+msGaBp79vjScRrdAvEvlVCkU 04L9I4I0AK7gHhOsJSYlwBThnKJ2ywXMemTx4ahJBRUtlMTNEdbe8SBac1WLhMXwMRzDZwkNT/k7 0QdYsc5JR5LJGaeQU8JF3MUHwNh0IYxur/qedN6VTkyKOR0yZMo38hf3bXIuuqFtCpUn04gK++sX DGrM6C0t29urYdOKHi7DdbIrhA9nws7a5cMEOlzkC3sV0QuFC6Hq9Dvex6hp0D8AGuw1W0Z/Vsya Ojrlw05viG912+NtRo8Qy9fP4x6J4duslZnNuIxBP9yeMxHi8z9p2GJA6HVTTmUkHEMh0iW2f0KK i8va9Z7qUYDzYDE8jzknlVETws1J204cEZUZKGOkQSrCBhTo87qb70FsZl29GQUjhNBdVS3/OgXs u4QMBAhsNNFECfwY7hD8FNE4C1lgXtv7JNzGIFBYv2JP7iA3DC4bywjWPXcn9JJph+LDmkMI+X59 862q8Qsuv7Zr/eq7DQeJZUbof0K7D5L5/tlffVIf5gnBvZbPy0O06t3nZB7ksl7viyc0pOU5eZ7U WKwk+v3N8iAmaTIF3M+uJc0dFsio5aOGdEFZxP94sENnyllWU8dGZhLcxm++smvgmgh9bfK0i5gP fF8q5kP5Wogyl3/Pd0XJRJtqoPMnGPWH+tii0i7+zZ0biCUNYMgAoIGbw33JZtxYCHJn/hPTMHe0 St2nP+Y5R/7ZiTXF55VKlmjtxk9s/fmxCRRJw8fVE9musgbwDwwsdpEiogY7BrQHwOPTmkSuHBOq lSwAvUtfSGzhnjh/ICLMNNmZK51pNP1H9hXlmG2fEAwPdtFcWpWtfyHpNBThV0D9aIPD11tbmJC8 UCC9f9m/+fxam/IhuCDp6dS6cNHZWShu2JIkaAnaq9CgKTHvUnmAu82wrb/1u1ysPQqpU+D6CY+W WCXV8Peb/EBe0hG5FsuiOnJoQKAQ36GUBJi0XuNeLEfdIh2MbJIZH//eRua12nZS9LPmT2EKBXE8 iz7TuQwvysU3BaA6GMiRlLb4s//gklHPHyVoIzGzJGwTERh2EwVz8uim6PWkFS8gDd5TRhx6q2ur BbxpuHuePXJ3GMVWIHDt4PDBHYo9BUrIsM1dTrKIKLMNpZnZ+vLCMSIRtzuJD2DjzYDf+Kd80Nvy rr12vADGL9ZQ7Vu21FVQ+uGxslo0EAnCCa0f6oaMks/7f9TgjQzm2kOHocb06fVtOFlja8LqCWv7 qNJYQ1sFkYI4IGS6ueZuJxcRKG0VIDnx2vblcmF+fnf9TVASO+qK/y6tCVa4XkwsMyZb52/rKe3K MLGG9Y1IbJ1+f5B4tytVh/TclVuN/vtOQFx/0jUAFf58ozbLhXAafbKKhWPcfEJ2IMjdDKA/EKle IEf6o6FIQmNj+Fhz0Nn2kZDAq6ForyG0mFT6Cd2Iro0CR5iq1wfaln+RHwnK9ymsGFbNxdpsvTYu MSAoHn48ev/dWjwVkEilNBrzYsSH2my1x9+YnLMiDaysvWJYlO563pw7tCR+3b23jcKOFY3SLTkY e9sJiCtXrtbufXYTPqpyUzNcgdwlYxuu3Mlea6KEjXhxcX6KJ+fVxIEpftcg8xDldrL9sA+zdZym wrKcwl5Grtiy1Ah6BR4B3xSl2uOB6pwPGFMR0f+a0/W4ZY1yMsoE6nfzJpRXFV5hf6Uab17aC9qc AUd7xR1DsmMeymX5oN6rqPLUYU/thAZbvAlE+FT/MHY2lANgxffl3xFnpdXgwmfFQ4nwnBaVdqSv G16MqCHfnmnJ11ttklkjTcMAbyjfooMpsPP4YZ8cYfOckGoaGRdq/r1CZrKhMUahjvGRWplZLAPm Z8r5gZemcdMMdEemwHfiAsiEo8+Hn1nXNLmdGv8wjL8XVxksatLRXeamiBq+ftJjZgiiP+BGh47Y tcD9a5qFe1/BYVgh7d7rKCDHpmc3kA3RZ117jgqgAm8dE2w2iaaRKBjKkcV1+Ga2kOC8DvudaEC2 2KsHQQgmWZK9xKvRZwss/uL2ePIgyJc4XYYlPq3uwu2TitqrmOV77CX/Ge+3aACleuuMm61td6pp zr4TV+QOUQWkhWEEhImG48WrQn+41StjC+x9FVcIjt0WSYxw0CMhGAAG86dHGoDb7OivTMIl9XRj /T0cUGjd95JyW08xKpPTZPLiQVfJfAYogxCr90cFWZzRJfJHjuaCGkbEh8J567xvRiML4Fh+Jbm/ SV7R9hl3KbUB0ULXPdGJJKnPsQUjThGXnNgVq+GEncZX5OpDP/o0kg0wlFva7VLipRcaKYNHypYN bWBzLBGz2HXT1ILndG+/S/tjN482mnvpzhUNnJ4dhf9sN9V/d5oj6wXU3U7kqZgeiY2S/rdv88Ui avSHGD6lrb2ROUo1LMASl5VBpJo/COIlTwDFhkdnlfjctpgPIFL/NeprK7rWdMhhOwz9cPjkHZA9 +ZcHJPudSJoZSuNUuSjAEKSHsoj5WGWY/GFpey+drhKiUR64gD6+Z0GYA65+COD3lmxPWpH2lpna DQCQfvjAQTY2n1WyvAFAAlrBs1LMvQQeeOIunadv8a7/6Y/RKzWKPMtVYzaS2JdchIiTpmgdgLUL KVQuog1eqUmAX7hhLfCe05sS9qGROgSi0hUW7pgXzU8UcoSPBvG+m2uXnF92lNdO91Z7e9QcRpBQ JSICNViRbrsjcMI2FjGN5xcvH+cUEHKHvCrZGUS/3DdykkpGPu8FloFJ0vT6d/nJC/3pi9LSB4xc hbFM3bxtiLSlP/veE3TJooEJeKIKepnlH2L7LHnnEn36TxnH58HrTT2VS8rG8yU8wxiTankrTgdd /f7y9I+3p4K5TQ0XrmroqWPCpF/Og8KdQd2WGwZq2R2VJb3jNNhSYXlkUL0/SbqXgAgVBnrOo8nM sVKV5t4y0c++1uLAkw4m97bB7hlArhMyOB3cT/pkxEC8NO66GwasWGrRVxAWhRzRWZ2UrrzR/79k b3N3MnJOdYwNIC/ioeHig5qs+QKL2kZS4mlPUT2064T1CLZq0zE3rIEVjfQZfmIh6evh5S0cx/sm UKkLT5/Qj7eEnKSh1hVd62dRhJSzejVcBexj30mGPdzNwogo/2KUTEEBwFf1XD7eTRUQDJFUA1qX vIF4n8RFPQ057ZLM92zF5lt5cHwJLWOyOgTlMefqXSiBeGIg9OezmfK+qusEA1KzO5UazMijbqlk B21FdQBHPnC1pinO2fupqFbLOchWyrK2OIdonTBLAwYi0WYt1jIQPVfqrwHplj9gjuTMYXO1OMlH MHA7BGR3pLXWKDJcChj2961/emRO81pp0yXDlq5OSrqh1PRRxBIfLZ1lMX7306It4p4qQq954vqP xrmcaK7RFSqQy4YdHuLKk5YEf5i+1cmAM+oyt+NKeVjRTZ0NSIENMXKdq7dM+8gDPuXjBfKLnmDy 1YZMCkt9bp+KNeHllllqJVgxMEnwdLB59jGaTvOKoSUqrl7kRzChvUwiVmLwXn3Vecmb8LjsLRIl MD2sdl0ywAC5lNgkYKdCPsDq2k3VwQMa2TSWzf2zcdsKTUi7oSnuFfA4YTqY+tUq7p7iAE3w5vcT yaLd3auY7iN1BQ4vuFPXVi1aeolEBg8sPBPi4d1IFbyB1HU4bA5iBhP9hK1ZglfvvEh/1GZZGVEg 4V6K66H2Z5a2gkslxG2DePkJGaeQa+RqjZBdBUduQHmoO7nbFiJ7x8o4h7AXbfQEm5O79BZZb8Um 9BowGO4NldiMUYAahqrr+QbV2dybNovZeO5qVowNcUcCGxH7No6A8syyA7nXICAn3ZKy+iGicPdR b02OBoqqJCvrC13PLV3J+VY/5RQR916PXaUzsAYk9NbcQsEhhN2aB4zs2UQBwyILUD2L3StcL1fG 89MK3tqPZptJ1HKhGLSCSFeGMKpToSTg+V0IxzOSpebOeR6D/eHkvPi2q5/KXBnjS1Mn0eNLSLXq Z8eBXl2hg+vQCPaq7VIzWyqqoKanUi0NvRWDSXTAipLdte3DrP2d9cRMlrgDgstnbWEUQP7XlaEc lnxzSWMC+5EUqZN/ETrYuetCJxtvYfooNSf3ju8icqFiHQO42yQesd0AgKNXylw3c1uMgGj8EGZl IrBgG1P5sDk0xZE4K39Dk0QC4KLw4VBk1F/snr5qfy0E4ZmBCELBGSg9CIT/lGWV/HkiZPuITqkR bnlF8vXOlx1QXm0xlEvJQkC5xeNh7RrfC1jn5RnDJNezO8G18C2F0rr9ciHg8OIfLwjztYOnvuth DS24A1vlJlV4ZSrkO0B1PRsgLPs2JFJo3N28yjyWylPesxFHo9mPem8jYWLmxYX4wwRrniaDW3fB aQSI8X0c7V0Hjqs8nVAcvrkpfkacx9S4N9MfsgCzsm3z+2a2XHRU7NmvBiAP4QPQYca0pMxR789R fPhLZfyq0f1gRpivR77WLpDi/WfvDSkRnlVrHnughnZ57j7iF3Ikoo6JE0qD8/lPjt2S6fCM7HMi /y/zweh5v8KgmgNz7q1WUYLWXg7Tf8UjU1vyQU6ZDR8vwpjuAnOehCGH9siOAG8dG8nK07g1uX1o 5D3ENMlYhQF4RwpzGSqLQ8vT3OXQZcuSF3RTyjYjHIk6bYIvWtFQ0I3e6ED4dtD91CmeMzXLubt5 vViOk7QLJIntICUbKTok+NYaguesdd+mddb++tTDHoq6fIVGruZiSyGLwTuTLpqk7aWIhDQN4V5r pIE3GBId7yatJREC4NQlfz94OmeMmx6wxLuOIVtPrgemovGt4QQKHG8yFzWi/wIXOBAWadHceDRM RMmSElcW4Y/20iFej/rZd50ob2ar+RvU6horaC7hej31Ja2IcdbOkc7leReFJ3uAoLnZtt/H01Ep TQk0nsmus6DlMrteCWUKzv9FeTOJ0wEvc8zhoW71KZEEkVZ/FphRCzcgrdwc6XNSIkyOoe4k09A0 Thqc9KvW7ugX2szfwG9FyvuwdcIRT5ZUf7uZqtYAHykjFqANHFBPS5Kd4vt/QoCIO4KHEwa51Fbd IED9DNSXYeP1jH6ZGu0TyxYJuKBB1c93IGAoDopwk9eWRT9Jkx9cfoW/zCDzx+jx6XZBNXcICnxk OW1M0t8GpSR62LPV9YgyckEoEOb70ztIJoSPZGffr9K7698I4rE7h2QQaj6UWI+15yDrk58+bFCq dQZxaJUNNJBFBfD0mXXSbh6QMXWiVidhdS8mq52NUer4kQ9epI+nm1X0bnbnVWQlUIEY9cP90l4h legFwQFpfdEWPAw3LBHmfP0bLtdLaCfl6O8dtHhmFW0HERGN+kAAGWSMypHYLPunOQyGwAStygoY e4/OxVrggCnewT9gnXnWTNKTK/0q9IisoU/UxcRInWOv1KL0HzloNtjhh/USlnKo9fPjQE07ZUsc bD6GDoetyv7et+wlYbJbLcIVsjYEC+YacCZ3GB39JMsdBbF7NM/1SOWJfGSOvQn+Tfq2K/NgpecP bImfehML9EYv7DL7Wpo4ZsN5dkqCI/OjaGydbdlKQH+VtcaokyZ9rVmunUkzIFz6he33bctDrCPV DxW9WdLYt+sSuixTiYn3YzwA8Vpo5JqbEqOw93o3u9eyolcLzOKN4L+6YWMy4Ky1KfLM1ItsQN6K 2Jdy63tsW7zz5lZ6P6iM19E6OgMBpM6RpEJeAlj9f+Bg1Q8ogCl3Ii5FVUmGoQZm0e+oj174wXo0 tcHCzdBgr8GljEpf4gYxlGe4XYX0kbAn9tlm7hI5nreFqJPyYR/PZZEX9NQpZQOXwj6Xj/8Dlt9B 7Eh3Oa0kl4zTqfsDAxeoGKFZKmH19fnYqM3jilennh7op0PSX/wTscI130fmpF6ypH6HCwaFYapo Au65ABDXHHYIbkliVP8wz9QrDSayQKTwKJ3wyKR6ZwBuB16Aau2B6Dv/f5L11luUaOevHYHnMSq1 q/xSuLB19GH8opOVoH2VkF82I6z43+Jhzk12Z1IwqgLtUnMRQTIgYyAVPLeqSgyZHhUi/QwwnQOe alr1eGyvJYq6ghBsGHXG0+Djc9WbMB0wrPc4ZUS21BnU/Sw89hVjBXPBKHpn50Fs5Fd5DQYOKi4/ lchKaw0xlPPJPqVfXzBcBlqwQ4ZFU/sKfI6qXhEBJjCiyBOlcVydsuNneI2T0r7UjN+5CFOcp61Z H7+kLe1Es7ZFbOMiYrqIrpLj9HYiePySZSbvc16UasDXZO/L6Dsw80oxJ5b9ZX+q9xp+HcVMAusi DUo/1PSbt/ZTSUMIiWsVyuksDAq4n1+jE9e44d1QWeAXJaK4G34Kn3qAtJvJ3fpiSdhDAIXICMuD U6pdJUwhg/sFFu5ZLe1xe2fLMoJBZncFE1BGsq3uTakI04Lsbpmg5yA91mnIvfmj1A54HMXZ61K1 QJNHN1c/o3jSGyO/Zdxo3efRaQJNEmX7cRy8N1j/hEdoJu0p+60iFabSG28RPQwNHNtRtNO6YFdF RvZBy+MuMUPdDXXhrgz9kiRB52k3zJQCOG120/caZMRqzhaxMY5XNHTkZByLYFYNcu3bZqbgaSrO 8sf5hJpXd/rzzytAuY3eb4cNocMkrvEt+Ul5wFvzKVmxqrupSukMmBpxc80+QuTH7543g9mIRxfO TSYBMMvfpZgddCYFwlDs8FS9kf0QE0xHg2AS4G5gNzaTCczu0K6o7bNgBBSuLoknsnmAbm4vY9CA bwgstLN4t0dbar4y76HqwbISAjapsS0KG8Z9x7Iy6PMMODN5Rzbsyb3PaCau/2vDj/Rys0YdPQVX QBM0rJIYfMnFw8xPF0JpRs0z220sANa4acQPYwpcnascOokHB/fT1jGKL79JCUwN0wblhuWhHF0f 1Lr561UIVncpMkdHKgBIBu4V9JP5km1yjtcTJsmvtKIMojl8P2ZVjU/lh+mBKQSJ5Ug3kg8gXu6U 0Uju+glYpuvOxcETnyVG5TzGOzc7k0j08fep7pjjYbOaZqI5a/zUT/7Rw3xDrV7gCviYCq2hNTOI Hzu4qAJHzoGOho/aaGVqVTNElcThQDL0ffMHC3KT56TiMRIWsBKRqXu/kqKYBWC8sYCziUn3IeIO 16gxB7BUQDmAkHPrb/vNO1wMdFqYJZtDHvtI4Nz7Ha/On3aWCGFaKE60/qIKqcsBAeJmquKxLljI xFIiu1ZohxalFdpA9dD72UL4oufBIyAqlqEHn2yHlP75DP79urT4lTBiMFskpuCBVjoHYoLv7phl kUblzybTk/2X9SCh1u3Tguw3NaAeTOEpOmz5DjG72b0zmpSgbgmD1qPE8yuGlmgmFO4pch6+0COM PlWjPGj6DxxRhZ+Rr0hvGWoF6ns4ZHPqR+KsXLDIapnfYAphQ9T0+GkscrQTlBNRQJTCWCNQ1Ts0 Ihfa+jCVn+Qc+3k8uI7okqpOVQe3mcs48+8rIZXwaaS/JDfrYLhX9ueNnN+9A8n6UzwjBoIaJhSX VLLuo1MY8Vyo+zqmHsy9CFbZKLx1Fps6tppMvEq0cDkcqYVf+ocIcQKyrvBfHUNFHiHN8hB01+IH HaBEf/IMUo5qaI+AnQApNycB1D/DOdKvagn7/PYtD1Iql0KW8MryNwhhwx5bXFfb7zeew7HZGyiJ Qty4O+U2TqO+VZ+G+LXy4gZ+Ekw/eKC0kaWXndBOHfSUAu3MrBiI0X1Hhhk4xA6y/CBbFj6BrB/q VRCvSfGm3ZIilXTTZystj9RPOmtfzNfKFNl3R1L6TiwQFVl/MSJ4cfrP6LEPatsDuiwTRpelq+bU Pd8+YSZL8wS3DYy+HhoQxFPBCMxzMdxcASfhOyT1/gRKKDTZy0lQ32fK+vr/cVaWsQrz65b20P2v CjhV1W11R31DtJifYDwPVlYGZx24snXZ50jXV20B1MEmsnT9BT4+/CvG+P9/qN5kJ+Ud0y15A/EF rpPUzaOWvmsNxrTxVKHWwJV3zeUDKbivouKHSWTY+kQY3Bd4SlQ9jqhVRB+TknSKJWfmVYmRIRu1 BHIR0NiS+lJu13FdGbR/5SjEMxorvZlftGM4ndMbnRJchcXX9k0s5bQSYpHP/JjOfx2ZGDoGaWmu bNv1FatJayzojyIX9xfxZCUvmPRdPSlurKC0bEi5dIslRN4UCtmLNy54Ri2y9YWCMzqiSRsC/KQo 3rP5xZOx4a2MN5zTAj3vSlhEA0r4ssW9O91o0iRfnSJlurPAKAxoUeCZ0hMrL/aIpCf5yiySimjw DA9PFr889EDzY5XITw5u8MPN4y6K66laqLP7rw6VXiGUPmPhfaY8zXfncs2RfivDtTlPNDqiPGQh kWtsekdYT+KzMJHXci2EOcRMiCIs4V4ThUrmKIQik8fecJF+Vbb2HrCk66VtSh0TQd+zx8rQq9o0 1VyUE5axViNdK5voXhmZupeDYxDbImz7dZlla2qtN4WOgF/jCO/lH9cqWOgSkQ6fzxJMUyHktTIT eaIlf2nVRGKOo/ZWnUdYzWJgjQF7XzFbFAi76+bai+p420om268/S8LC/rLdyGMr1TXyaq9rcbL0 pvcY+maLzC5S0/4PbDIum9TjdBOhkrT3sLnN2/AOhnWq/oQeKM2F/smEVLwwXGkEQ9wo/xgb9sFb Hqo60F70gyk5dQPxVR4FT+pFfK91UoMgN1ij6kI40+fi5TwMHxhVqhccWTq0/QFdoGc0Av3CV4SX dSCvdbS64wqYsXdfAAn3+K7YBzzYYJZ6F2u6s0T1kOXFi5OGyt0i/Y/w4w4dLhpok9Ji6EU2kmXt WcWOIm0YjaqyMLIIE07Oi6ZSFOxVhel6hekNVp+L/rMNlCazfIY99x2iASOEejVPtCes8156I3sE 9UD00ieYm3qPhqdRA5ow0nibSIBTn4CBa3WWBGThnKZJqyX5KpZKVBrvPc/4KWUfix6h9jUHtXD8 Vc+Z/kGvuC1fOv1PI0BS8n2zyw9khQ3o+L0ul3Kz2c2Y9WWKstc16X6KA/KngHZbHfr4bj4/ZH5l z6k4+8SSmMhHXp9k97iITS6zf7CRnm3w9/1TnwYXvhCYXLUwAgk3K1ZswvYP0QTByshVflqdSOKl rKs/4FJRJtsX8eGmTad4XxB+6qx87jhmHfu9ng2PWgKkoKomU4uU6dLVKsYd/Kmp/Pb7ojpd5Gi8 9ArMIG0wn3UTTy5E21iQJb2wi3PlikRK2x0a4QfP5i9eyWSD88ASjmkbKbCoV5sSAXRJOetM1xeF rtfDkW/AKgNEQGaMf05rf5k7jSdSXctxKYSQK81m98WIrssEg/QeeOsIeAG4+N04lqtlE32wHirT xK8Ba24siz6H3ImgYgq7CwXYNBgmt40EQz0V8NR7M29nykeMbv6GTqNBVndVZQFyuYhazu6WLHUe DddOaBlXyiNstOXSjV2xia3Et2yZ4mCQOCShbtRHKQtoObLbTyOX/Xnlbrpb86U3iNXX7mLDwjsB ODlAxCY4Gb7hrHLoYy/qEHyrS/u8VBscZoyvZJR1rwBB6k60V2XkBjUjK91td2ALFZgJtXW/wyVS DTwadtsyo51lvqU72fDOXtmXfa6Z0mAwo0JefZGQ2dTDoO0LAvfmfhunbx8GLZGLBxV/g4axPwyQ VfXnlNOuLHlR8jbCwBYm4204BO2XvyKp0sW+8HWpvO0E7BX10aCK2WS5MtN/4vWO+LOQrNU5ZwKn OCuVWAbqgmIDn61syLE0Bb4p/7Z6B5c1SMwXTDoNW3uqWxDVZD3Tyr9F5xN1vhMA8XMiMME2nD1w tmCY/biYLE841TR+TNnGVykVpDIuhSfJPh9saDYfkARGgASgSKcvgY77gxD4yxodCGKzPrDf5fGr VVruHa+3E8zjge/rLHVGLCXMF4K5CRfumGD9F9DI2wf+mEgC68eBJgbcOnq0cSCaKJZH5pSV2trz N7Uqm4VX+KdfN+rFjag9U4K//7XSgq+jCz5VTRFHxxDAXTC/iIlgcX6keQKyzFPhZ7zkT7vfh6Bn w7tHHqDskU5oh+GmlQ4bU281OrOa68KTY2FMoztmYLY9msHhYZ7tF7XHN/2pU72xs5ezevkgDxAE U/KuaUpfQGNV3bwOWkH/nPyrKOpolG4WeLJ7PIziEpB0nur7XojFD37X7092u2dsKxDgtVQSQWrn CV/o1gUJJLbf2u7GCSqTyex6NgmA5qJiCbo7Q8rScE6lyt4EFBQm/S8t5IgdlUp6yDBeA1u+X3Q5 Q76UXPHfbvurOXfYMc5MBhaFAXmrS+UUXf7EMyhVjSyJ8KoduIC8fZtFPCRU3aoA/Ydo+hP040yr O7VLDx0ZCf9b3MKjjRuIB+eoNAomeH970V4LWGMZDGaBHLjzSXvv1oZvednDWXytNOgGmsJj3nna Vm7Doz/tZILHe30S3oLaQr6G4NzxOPnguocVZyw//j+QSZjl3h7iO3HgU0Mk6SMgZvAb1r0H6stX 143Vha3nuxpOUALSOLGgwyirIFJs+/FzhbMJxAnnBTUHYEwgdm99M9MYHLDWuaP5xxfUSgX0B8fW XaxMtaS4px+laos13Nc7pPjBvPnFF1Z3Tkv2/5iPSlW9lctZQIc8zsg5GJEyomtFdo2IwDJZ62pO VDYfK6n0oi00jHUzKVFpl2kACCsfQWTKEKKsNyFA27bgHQqjPneuBNsZxwxwQGO3angsn8fiESFK OUIE+EGZSOzQkZFAh0ursrB8wRyT0VeqkoKf6XbJvR5ewanxovYn3EvqxaP5B8OBNXd7IamzWAx/ 5J9p+am+5sehYGSn+EFA1NxgwDAajZmYcJ3LUk8fawkwXCSCgrC4oTnsxOm1eIISkJop2+qiHROz OzgniXRKGMSx1ZSKqtCZq3xEhNRJyZ0stuf2acbObeFc1avjlofHGCY15ubVzTEoY5fWzTqUixfg 7bOHXI5buPHehVQvgH8cA/puwnnS1nrEh+inNHOElBHqNQ+ePVvBHpdSTOfIkBR/UqrrjFcuvg36 In28lXcSlpCM4weNB64MljzVFKG4bCHxEIs2Eh1w1YJbMHQJxvrc6okgtoFQRCHfEMh07WFfQuff d0ozSg2QVmVYpq7KjePxuY/4tBbdxW9tddn/xfsJcrr7Si1JpdReOOj/IgHUpH2bEoQhwPqqhs8/ 7keU95k3fVdaUHri7RT8Yq6y3A9h0tCfYM+bLxW6nlGNMmXlnsDUAVvhLPdraX/i0mJpTNu65G/M 8kI7jfcP+z6vFCMahjkGRYcqD7yQG/BxpRfZIkPITvaQsElQ799qDEloofXxOWHnpk0STlbGFxAe g/OZcarXp1j4T/X+xCIUjrgQuICzGIJd+K981j8IaEk/WiQ2tsf48XFLZcRQAXHd88qb5pgbjR9V qfAVFU5NXFWTPBcOM/EtnDWCvwZNTCaJewlhurMSYJwRUKBVY933LdOwPZRHmkLlUGfNTFaiWTJP 2VTymv+aP/Mf40aipa9LVGQICIRO8prC87BcpVbZl8U+Uf7X22TeoNhPFV/+261Tvbotu+aH7PI/ J7cL0tinLzBXj4scBOsIgfmw4mq2Fad/rwqWpSm/j7fR1Q6OWUSimx/jrM4JtYo9BhYfNmlIfGL1 Vuo3vH4AWZ45pLqhkVOsyr58SkAkhQ7VbDEF+DWshluA0JwhuGLWIm4u84HiP8EP6Yc+tXYLXXoN QLp/i9EUUK+je0tImyiATLRSN12PBGvmI73/6Joc86krXTFY8XuTH3kI1FcEqZqm8ddT491dnPG2 fRT8rsJdeqiTt4gRI2Q6uRJWQwCFwzi5vr2uTL+ylTwdbsnkmcosDgA+/pW8ymFdLhEyu0L54wmH twaxDKwZ1oFKoyiuew9pBIo0WWFMx4FGS5rrPOjU10YItFD3iF+qZNFrDeJ9nuh8IfWRc0z41rJR 8rX040Pr+D/rGX7advX347iS6EXwn8OqeXvHwW8gGEenZpYd12Y3ZT+JT716rKAsU0Wc+OJUhLUf 3VS+ZGvBh/emjmXNUZDgpT/7nSOigPDywrzYf78EjIKlepy8RTE/btfOEXLU15/2etIKHkFoserh fLsnyLSmBboBXMA5b/pM1xgIilRYW1mgeVVQC/tCrHr8daXFavMF/R5/KXhbhZ9R5wCPtwAhaRGy 4wzZEAp9c9Z/OYLHC1rajhNzzdcnNSEOScVSoQRO2kYLUca4Rc0yVS/KeHZZumwX3YQj+IpEFHgp m8siyf1eMIKstxkF5RRLUDfO3X+/iXvro1vMDlTY8xi3m4Jw6iK5f2NIPZEyg2tlriSvy14i+8Ew 7SN3UHC59AchpNSDGkqheyntfrWv+TOkr8fAWzjRyMz3xSm4y7sEVCnZvJhXV4+yyi1jMNTPKDVZ 8EpbPp9Hx6e1poRlGzNhRNWCM8X+Mceeol69CRCDJXQqMUBArMPjt2ozn7tixDjiEDIdMRXwHboW mTSA3r1DavTfSEdjd/1j2EqfFyKlaqa0RJuBAF0GTXrQlEcPZgAMynYdXHtG3QCzBQ2Xb4UweqcN gJNArvzyBtwr+Etl/8lSPAqCiYx82ESP66oNfRbuAZVYr4rRKkX6WwrZdKtQraTR+2RSr8fxCHEw kK1Cmt7EJcMtp5PuVW+A/AdxOoTIr/Lu9MU6yOAKP85+aw/SnKLKSMEn80DWs4fqddk8t3fB/F5N Kt2RM/gVu2gtnHPGh6vl8lg7AbDUe27nmwvNXSUlg3VZapKif4VRyxqoHA9YwGUeLlmq+nUGCCaI 5fMkIBOoLBzn2QoE700GVoQe9CRFn70uxlQCxowdWfguAX9TXtf4CkKE/6e8HCLuVU3ypIvcniP1 2bgNHMxTnWqLnLVO6T3yVfVJiQ7RrskZZvTcnUSZQj4WVGQow8eiFMTYdBj/oR2tkyNmumVNpxQ1 gW+QfnAvAK2iDcdJEcKAhIv0jX4p6useZpaRCurBpwMDciiTtB+XRGDMv+lOYlL4kgQGR55aYD4F 5JqD64sZgn7ZjibPY/Gcj81ZNKCtV7/jbXWGf6GlAsYl1rSAEtipOKkfmLStkgCwPMYPDb0L9Qdw 3xxeops10j2xJq3TcNV616YEuXZ3eZVS/26OJOFPTI4gFdnsm1d8GOqXhbLbVC4J1viEugilZ6/w TPaX1L18YCSgBkdGMXaeTJSYWziikDcbhpytsBuH40a/sBlUGfoHeWN4Qap+DdQSiJfE9F2muAQ/ z0YEuIqHKJpG8dwv/Sbw0eBDMniT3YxxtFrK6pFL9SIeiozIW6qp+BmL/uSN60j/saXfIjSoYPdU c9QgQuotO9slJQ7RZNTGzazOlgqXtL36YsnoqMq04ggSvDrD7FTA635PwPGF2t3LYw5NT7+o8fJD Xvg7uV4/IqflMc24giOl1Aky+5pFsZzhFbSAPl5LY7GEsqKnhsdPuBXkMZ799P3EtGCmh9PDN+H7 ry2tusUl45vY15wB3t1g4W8iV2NRgeyWclKGSH/tNeDYZtPQZ0RgZdmWTpUscaaOdOGcB12bxBH4 UVusHliuLfELroWGXXnJieq7ogkbQBEJ7UL6p1r3tpBrevxiIbcRctRG22mYciqBJohbiky/ebKR 4MwA9tzxO0GGjbq8ex4c8hL5OULX4X9zPZl172JjKyaWfd68ZKY8Wh6zuouIOzPtSOdvCzYDOief 6HCQwlGaCZbqfkBUfKW7i7EySSIpYiTaEOpy/3TIQ/dNFHDYc3UWS5EiYgr8uUDOvhnVJxiJ/KFu J7+O+3M8AR9JRhIhuyXCuwfkFfv6q5PEJLNpj0p0W7S0JLvbn47F7B9TOU57bZYzUB1oTcT6hC5Z MkY/BNxiW/wiqRE9bg9yawCRtHekjEzjiCMBF+OWjeO+VESyojFXT/vzBJOOPuLsbJT/0qO+hsuj P0QugT5NlizTNOiarT25Jw9m6s35A5CyGV6h4tjG//AyZ5h9KDzo0mzOsT6Kr3LG1dPpB0jpIAh6 pkxKH0i7TOGoc1tPp4g+NP9KcycN7je44rRTfrCEDS9cxWSkUYKwhTOwAg7bEPPS/z+1lgp/yN9E IiPw6kzcBVUI7ibfG6RbR1r5v7TG9eeKmSLOLI5uI5bpaNtzamrTCOQUkuw3FgAPgU9cI87UdthX wX/D3Lo6Qzuxx17+XD2mEodkeDUnX1VB12AwQiD3FkxGpV40A49TARrVX2QiAiKkkAwJGs6RY/QE xw21Vi7/DzqlLrDaZBRxJDYRUZkf51h09YE/eK6wvF4v8hEdq1uRGbgtbWOuuQfgfUDTIO0kNxPo N/VdbHtCmTA+R9SJUCKJF4hvW/P2LqGrWRlNOUJHGF/4TFwTad2K1M4n9/byadmLui5R7wXBmqNO xEcGMyHxngHOhkTSO5Rm3Q6/06Zwqa/i8B16bP32UG63HG8q7ToboeiMmFt56okJaIaD8sNmNG25 RXRlDq8UD35EbOnqV85V1VeOecCtegZ/5dCm0uqWC8OqG7fChAX8BWOg2kCFyE+u2dUFB1Ff7UUb sNSQpTS0r/kxZGrPAIo6E8mp+gOAoOCa4Qg045m3G8/xb8Hcap8JWtTXnkm3/4E2aB9HpjkO88QD SFO60T/+qLRHF6lQL2YPmuAcEQpNPZz5nT9guJAuKJuISAtsVrj1WYcnZHb4ZSgVZ1sXPBCKELJ+ cttJ8ud97zA42RwhcSmuKIzn8S9jEqfa630X/LkVz9x0CsUO3ATnroLJIXkC555tTKt6T2w907uM 4jUDAkzGHhP0ZJBp56vo0I0C2XxOaTjVYMhUsedaBF6XIkOUWx0/KDt9f8++941XJyxZQyDS6b1I 2tEwmZdDd+KKFLy1w1K8lTg8eCN0HKKlprcxIU9XesJ7QjpmRtwnJoh7Jr0cls+duNzeNZC2lZp6 lprgGxlU8yBsBUMj9gNP7t2nl4PjujA+rnMu4g07yUHgcQcGXI1FCNc/MPISF5Q2in7PCimzwmxO Dn0bIPmcW1tSh0KtzI7cvVVVbCzRKJUxMtOauY5jLuDqNfnsLz1VU7082lTCOLw/ulyQOiEhZWbN bt7/tOtVhjkRKZaKk9VMqWtGrgfDJCVTw/8Ea7ntQNQLTFzzO3HjaQ3TsRmPmFsScq/iS3KnEVpj NzeViqfj1lDqW7oJMJVBDB3626XhMC9NPtZ0qktLLniOK08PX9nxtau2yigGOz5zWWVhs3lpnr5x UtWL6Er49WbdQ9RJQIFw2AaOQgZpPTSq4xUiaDUW+P1JhGr9FR+yMOJisyRzp4sBeoty7LsIccI1 u9mRFrTLu8HLen/5Q4N80FAsAd4sM3A/Cu+4d57kswWZH1yoAlmPwH2n3MW5I1a1WRNDpDsZzdUL h7aAPg4EstxJv370DxJLqGPt3JlJWjAFzq/DVQ6Jyv7u7cABmPJ4Ul9VEJk+DjuEwPFpOIfErjyo 2J1G/EFxQseLwAe0JIwbAU8B2IGl4MJh0hZoc0wp+vZSdS/U1AGelLuHMiUNMcnUH4eqkvteWZbj M0BEIq6AhHPVDbcZsQ78YN0S+UiwM0jYFQcfxmvrZcKlyQ3OJIeTWYuMOZQjL5z1BbnMFb8WOS4u JHdt+MR2QTLb9f3WcqU0quWqlD3ycgZx3evMMjThsLTs2vWb59hf6mIz1eImOkfh+AuGA8u39var Mqoo7OUgoFHL6TKfsiGJWtS6T2XbKYzJt01h861Plo9qyUHcC8BwukgJ3bueckPbBzwRDxaMlJii dQ+jewRw0dI3Vmzf6e8c8StYq7a7d8beb3g2Rhkaq1+vAAQ78SK9VCsS819L0PcLX/QbAzuPoBwZ sM81USz3b7t8yVq7xeCZIrZjyvXK59kkfcG8TSeddQnimS01dqZNY+mdTDD2nr1mo1K8eWA+P+b3 PCKEsfLu6ENGkxlZf0LPU4YR69EML7EotVTsz7bQOv7E+CN6SuULmBkpDxxRbxQc0bZaNwuQcyqL APt1DB0cbg/ksNhE+cKebUrpEjWe79I+6Yv+PuTjLzseVjVV8JdwNd4PiUZ5y1UsuJ8Qs+GkXx45 HXfvzZlmpGHB4Hq9RGkzkRkUF/Yu9aZjPQEnyue5V1QtKMjMYKOZy7yA2XNfDeSVHWcQt7Fd4ooj HidFg+iwZ5VRweoNn3orG2sRVTPhw7caYShJr00on3E/YTyDm9HggVzoEzvMKCIvCvmtYu44HO4W STlMCqGWt3p+Y9GR6dLUiOKNbYqSpJONon+9mE/ooipNxvOR416CE+P+u+Zb89Q8zKhrvZb6+UWS MjTFgfYskMOhlD1yPfWD63zCha4ZyiqQj21j5QKnTyWH+DBvqWGqzdQjOm7FDVGrIlAMTrroiiXU lrJe9aQteKkNgNpH+twd8T75cQXswH/92GhzAS11iTsbOs2flx07zpInSPN63XZ/ut1GFGPJMHFh 4t1gsc3A5mKtLH5bNMkZv7GBoCrd5nJXRdUBUTIo7sv7/FULN46AVnkqtgIwhh03nec5TzpEAHYE oSOsUC1p/w6KYbxCRvbjQeWsYO2vceuawYxtovkiRVeCiNf80MISVcKcjzVU73T3CjVX510WDSI9 +mkKJB34c6yOga2guW9lL+uEO+7qU6boXi8o326wC+vJbld4HehGwvJQJ6RXlz2r7V8hSEa8QuZE Ozslg/INt97O9nmhJmqezdzUT83C2QstH/WOzDOiaxsiBJ0MsR/tdE4v0ykZTjTAXv4cGlXhSAUB 973oKHVQr1RcOC6v3fAF8Yk2nZCA59NIqAH9lwrYddXnnD78r5NKIyKpKi8mFF0kiBxiWyhpCSD2 R/xK5r4o0fc/GfLlRHs/ulAL+Mym1PmG8xd4oct7wPNDd9r9c711m2gRz84FadxGT+VigWBY6oYW YFROMojC8P93GkYZdipVgcDYsGayDePJ3USwMASZFJDBTt0BhF4EKsQiG/Ty9S6YTGk3+SqUMc4F 5oVoldnqmQejPHNSHZ9GZDiA5Gq04PcMJ36D5ZUKZLVou+9jt0+kndpSX/rnOBeJKUFgUEV7LLj7 c2akGV9vKWL27hgiKuo/cser3S/kgtkpO9i+U9LLJXmZ1bFrPGDIIaafsug4L3x/Itis7R3siwge XO4MCVco5hq4zBkAbQrII3wRAve1XePsA57mBI0n6v3CiH0s+rl4uuA2xGyp8EbWziDqhmr1VeI/ 22PoI/yPYLOkPqMGu/aS93QxpOvADUkhxqadJ83Mt5uV4AX5gzGWKIycUhpF6esZaSUByZR2EYrg hNIo6vs7dPUYctWzj5s0HDHz4x4mSnf5BP97trXV3zskgISZGXL8rQV1Ryhe/m3cOsJfPGB0ssdc 0sFYwpru+04WBSdGQMBRsuCAJmDM0B8HxwoINPz75tWfYDVM62OhIhGi/kLHC4qWDTSTYLDjyiYe TO16rqFvVIyF1bW/CHNapo/AHs9+2CCPo/kBrAA2J3kPKqbMtAWnr0dGvegyfV14tm1osL/7FgAf xwmmdJg7vDRHcvu/n3W98hX+gKrTYZm6rORjZSxvLETmOY48YLXgqRx+0gebecn+HRyKkkvzJQqZ hnU3ap5Fr6GysCy+4b2W/I6fAITtIuD+/x3caxLRHf2IFBF3bp9YzX7nmwH0vlP5T3R4Rd+IqjL/ fllaFNeIig0oROZ7GKEOnkYSZ8jnAgMon1n2mxOCbfJE4kmLEgmzjR4CseEAgWC8N+uExLtCty6Q R4Uu1CSg9cvVMwQN4Lw6ACoG6U4pu4+3QOX+HprYE/h4eeYRf5MUfUCxaNqSkZ31bDPLJVNPsNLd GKZsEez24ZHeXV01K/1PZDB+T/4A0X/TX2LOvEelDmxRU1M1pL8Mx4ULa8+cUTsetKzsMXbWJH2Q S0XjQghEjtStnzjnE3RjRRGNlsjyYKUAxWmZdMKr43KGSWA+vEGGerKvV1F6EMQHQCR8zWyhGyWe NCEtZRCbmu5HES1IfhU= `protect end_protected	bsd-2-clause	a5bc65d2ebf2bf31e13db337e1b14f4c	0.954474	1.812371	false	false	false	false
Yarr/Yarr-fw	syn/spec/top_yarr_spec.vhd	1	52,161	-------------------------------------------- -- Project: YARR -- Author: Timon Heim ([email protected]) -- Description: Top module for YARR on SPEC -- Dependencies: - -------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.gn4124_core_pkg.all; use work.board_pkg.all; use work.common_pkg.all; library UNISIM; use UNISIM.vcomponents.all; entity yarr is port ( -- On board 20MHz oscillator clk20_vcxo_i : in std_logic; -- DAC interface (20MHz and 25MHz VCXO) pll25dac_sync_n : out std_logic; -- 25MHz VCXO pll20dac_sync_n : out std_logic; -- 20MHz VCXO plldac_din : out std_logic; plldac_sclk : out std_logic; -- From GN4124 Local bus L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers) L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers) clk_125m_pllref_n_i : in std_logic; clk_125m_pllref_p_i : in std_logic; L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N) -- General Purpose Interface GPIO : out std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8 -- GPIO[1] -> GN4124 GPIO9 -- PCIe to Local [Inbound Data] - RX P2L_RDY : out std_logic; -- Rx Buffer Full Flag P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock- P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+ P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data P2L_DFRAME : in std_logic; -- Receive Frame P2L_VALID : in std_logic; -- Receive Data Valid -- Inbound Buffer Request/Status P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready RX_ERROR : out std_logic; -- Receive Error -- Local to Parallel [Outbound Data] - TX L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data L2P_DFRAME : out std_logic; -- Transmit Data Frame L2P_VALID : out std_logic; -- Transmit Data Valid L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock- L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+ L2P_EDB : out std_logic; -- Packet termination and discard -- Outbound Buffer Status L2P_RDY : in std_logic; -- Tx Buffer Full Flag L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready TX_ERROR : in std_logic; -- Transmit Error VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready -- Font panel LEDs led_red_o : out std_logic; led_green_o : out std_logic; -- Auxiliary pins AUX_LEDS_O : out std_logic_vector(3 downto 0); AUX_BUTTONS_I : in std_logic_vector(1 downto 0); -- PCB version pcb_ver_i : in std_logic_vector(3 downto 0); -- DDR3 DDR3_CAS_N : out std_logic; DDR3_CK_P : out std_logic; DDR3_CK_N : out std_logic; DDR3_CKE : out std_logic; DDR3_LDM : out std_logic; DDR3_LDQS_N : inout std_logic; DDR3_LDQS_P : inout std_logic; DDR3_ODT : out std_logic; DDR3_RAS_N : out std_logic; DDR3_RESET_N : out std_logic; DDR3_UDM : out std_logic; DDR3_UDQS_N : inout std_logic; DDR3_UDQS_P : inout std_logic; DDR3_WE_N : out std_logic; DDR3_RZQ : inout std_logic; DDR3_ZIO : inout std_logic; DDR3_A : out std_logic_vector(13 downto 0); DDR3_BA : out std_logic_vector(2 downto 0); DDR3_DQ : inout std_logic_vector(15 downto 0); --------------------------------------------------------- -- FMC --------------------------------------------------------- -- Trigger input ext_trig_p : in std_logic_vector(3 downto 0); ext_trig_n : in std_logic_vector(3 downto 0); -- LVDS buffer --pwdn_l : out std_logic_vector(2 downto 0); -- GPIO --io : inout std_logic_vector(2 downto 0); -- FE-I4 fe_clk_p : out std_logic_vector(c_TX_CHANNELS-1 downto 0); fe_clk_n : out std_logic_vector(c_TX_CHANNELS-1 downto 0); fe_cmd_p : out std_logic_vector(c_TX_CHANNELS-1 downto 0); fe_cmd_n : out std_logic_vector(c_TX_CHANNELS-1 downto 0); fe_data_p : in std_logic_vector(c_RX_CHANNELS-1 downto 0); fe_data_n : in std_logic_vector(c_RX_CHANNELS-1 downto 0); -- I2c --sda : inout std_logic; --scl : inout std_logic; -- SPI scl_o : out std_logic; sda_o : out std_logic; sdi_i : in std_logic; latch_o : out std_logic ); end yarr; architecture rtl of yarr is ------------------------------------------------------------------------------ -- Components declaration ------------------------------------------------------------------------------ component gn4124_core port ( --------------------------------------------------------- -- Control and status rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124 status_o : out std_logic_vector(31 downto 0); -- Core status output --------------------------------------------------------- -- P2L Direction -- -- Source Sync DDR related signals p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+ p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock- p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data p2l_dframe_i : in std_logic; -- Receive Frame p2l_valid_i : in std_logic; -- Receive Data Valid -- P2L Control p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready rx_error_o : out std_logic; -- Receive Error --------------------------------------------------------- -- L2P Direction -- -- Source Sync DDR related signals l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data l2p_dframe_o : out std_logic; -- Transmit Data Frame l2p_valid_o : out std_logic; -- Transmit Data Valid l2p_edb_o : out std_logic; -- Packet termination and discard -- L2P Control l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready tx_error_i : in std_logic; -- Transmit Error vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready --------------------------------------------------------- -- Interrupt interface dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO --------------------------------------------------------- -- DMA registers wishbone interface (slave classic) dma_reg_clk_i : in std_logic; dma_reg_adr_i : in std_logic_vector(31 downto 0); dma_reg_dat_i : in std_logic_vector(31 downto 0); dma_reg_sel_i : in std_logic_vector(3 downto 0); dma_reg_stb_i : in std_logic; dma_reg_we_i : in std_logic; dma_reg_cyc_i : in std_logic; dma_reg_dat_o : out std_logic_vector(31 downto 0); dma_reg_ack_o : out std_logic; dma_reg_stall_o : out std_logic; --------------------------------------------------------- -- CSR wishbone interface (master pipelined) csr_clk_i : in std_logic; csr_adr_o : out std_logic_vector(31 downto 0); csr_dat_o : out std_logic_vector(31 downto 0); csr_sel_o : out std_logic_vector(3 downto 0); csr_stb_o : out std_logic; csr_we_o : out std_logic; csr_cyc_o : out std_logic; csr_dat_i : in std_logic_vector(31 downto 0); csr_ack_i : in std_logic; csr_stall_i : in std_logic; csr_err_i : in std_logic; csr_rty_i : in std_logic; csr_int_i : in std_logic; --------------------------------------------------------- -- DMA interface (Pipelined wishbone master) dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(31 downto 0); dma_sel_o : out std_logic_vector(3 downto 0); dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_cyc_o : out std_logic; dma_dat_i : in std_logic_vector(31 downto 0); dma_ack_i : in std_logic; dma_stall_i : in std_logic; dma_err_i : in std_logic; dma_rty_i : in std_logic; dma_int_i : in std_logic ); end component; -- gn4124_core component wb_addr_decoder generic ( g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address) g_WB_SLAVES_NB : integer := 2 ); port ( --------------------------------------------------------- -- GN4124 core clock and reset clk_i : in std_logic; rst_n_i : in std_logic; --------------------------------------------------------- -- wishbone master interface wbm_adr_i : in std_logic_vector(31 downto 0); -- Address wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select wbm_stb_i : in std_logic; -- Strobe wbm_we_i : in std_logic; -- Write wbm_cyc_i : in std_logic; -- Cycle wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in wbm_ack_o : out std_logic; -- Acknowledge wbm_stall_o : out std_logic; -- Stall --------------------------------------------------------- -- wishbone slaves interface wb_adr_o : out std_logic_vector(31 downto 0); -- Address wb_dat_o : out std_logic_vector(31 downto 0); -- Data out wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select wb_stb_o : out std_logic; -- Strobe wb_we_o : out std_logic; -- Write wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle wb_dat_i : in std_logic_vector((32g_WB_SLAVES_NB)-1 downto 0); -- Data in wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall ); end component wb_addr_decoder; component wb_tx_core generic ( g_NUM_TX : integer range 1 to 32 := c_TX_CHANNELS ); port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- TX tx_clk_i : in std_logic; tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0); trig_pulse_o : out std_logic; -- TRIGGER ext_trig_i : in std_logic ); end component; component wb_rx_core generic ( g_NUM_RX : integer range 1 to 32 := c_RX_CHANNELS ); port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- RX IN rx_clk_i : in std_logic; rx_serdes_clk_i : in std_logic; rx_clk_locked_i : in std_logic; rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0); trig_tag_i : in std_logic_vector(31 downto 0); -- RX OUT (sync to sys_clk) rx_valid_o : out std_logic; rx_data_o : out std_logic_vector(31 downto 0); busy_o : out std_logic; debug_o : out std_logic_vector(31 downto 0) ); end component; component wb_rx_bridge is port ( -- Sys Connect sys_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- Wishbone DMA Master Interface dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(31 downto 0); dma_dat_i : in std_logic_vector(31 downto 0); dma_cyc_o : out std_logic; dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_ack_i : in std_logic; dma_stall_i : in std_logic; -- Rx Interface rx_data_i : in std_logic_vector(31 downto 0); rx_valid_i : in std_logic; -- Status in trig_pulse_i : in std_logic; -- Status out irq_o : out std_logic; busy_o : out std_logic ); end component; component i2c_master_wb_top port ( wb_clk_i : in std_logic; wb_rst_i : in std_logic; arst_i : in std_logic; wb_adr_i : in std_logic_vector(2 downto 0); wb_dat_i : in std_logic_vector(7 downto 0); wb_dat_o : out std_logic_vector(7 downto 0); wb_we_i : in std_logic; wb_stb_i : in std_logic; wb_cyc_i : in std_logic; wb_ack_o : out std_logic; wb_inta_o: out std_logic; scl : inout std_logic; sda : inout std_logic ); end component; component wb_trigger_logic port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; -- To/From outside world ext_trig_i : in std_logic_vector(3 downto 0); ext_trig_o : out std_logic; ext_busy_i : in std_logic; ext_busy_o : out std_logic; -- Eudet TLU eudet_clk_o : out std_logic; eudet_busy_o : out std_logic; eudet_trig_i : in std_logic; eudet_rst_i : in std_logic; -- To/From inside world clk_i : in std_logic; trig_tag : out std_logic_vector(31 downto 0); debug_o : out std_logic_vector(31 downto 0) ); end component; component ddr3_ctrl generic( --! Bank and port size selection g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B"; --! Core's clock period in ps g_MEMCLK_PERIOD : integer := 3000; --! If TRUE, uses Xilinx calibration core (Input term, DQS centering) g_CALIB_SOFT_IP : string := "TRUE"; --! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN) g_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN"; --! Simulation mode g_SIMULATION : string := "FALSE"; --! DDR3 data port width g_NUM_DQ_PINS : integer := 16; --! DDR3 address port width g_MEM_ADDR_WIDTH : integer := 14; --! DDR3 bank address width g_MEM_BANKADDR_WIDTH : integer := 3; --! Wishbone port 0 data mask size (8-bit granularity) g_P0_MASK_SIZE : integer := 4; --! Wishbone port 0 data width g_P0_DATA_PORT_SIZE : integer := 32; --! Port 0 byte address width g_P0_BYTE_ADDR_WIDTH : integer := 30; --! Wishbone port 1 data mask size (8-bit granularity) g_P1_MASK_SIZE : integer := 4; --! Wishbone port 1 data width g_P1_DATA_PORT_SIZE : integer := 32; --! Port 1 byte address width g_P1_BYTE_ADDR_WIDTH : integer := 30 ); port( ---------------------------------------------------------------------------- -- Clock, control and status ---------------------------------------------------------------------------- --! Clock input clk_i : in std_logic; --! Reset input (active low) rst_n_i : in std_logic; --! Status output status_o : out std_logic_vector(31 downto 0); ---------------------------------------------------------------------------- -- DDR3 interface ---------------------------------------------------------------------------- --! DDR3 data bus ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0); --! DDR3 address bus ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0); --! DDR3 bank address ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0); --! DDR3 row address strobe ddr3_ras_n_o : out std_logic; --! DDR3 column address strobe ddr3_cas_n_o : out std_logic; --! DDR3 write enable ddr3_we_n_o : out std_logic; --! DDR3 on-die termination ddr3_odt_o : out std_logic; --! DDR3 reset ddr3_rst_n_o : out std_logic; --! DDR3 clock enable ddr3_cke_o : out std_logic; --! DDR3 lower byte data mask ddr3_dm_o : out std_logic; --! DDR3 upper byte data mask ddr3_udm_o : out std_logic; --! DDR3 lower byte data strobe (pos) ddr3_dqs_p_b : inout std_logic; --! DDR3 lower byte data strobe (neg) ddr3_dqs_n_b : inout std_logic; --! DDR3 upper byte data strobe (pos) ddr3_udqs_p_b : inout std_logic; --! DDR3 upper byte data strobe (pos) ddr3_udqs_n_b : inout std_logic; --! DDR3 clock (pos) ddr3_clk_p_o : out std_logic; --! DDR3 clock (neg) ddr3_clk_n_o : out std_logic; --! MCB internal termination calibration resistor ddr3_rzq_b : inout std_logic; --! MCB internal termination calibration ddr3_zio_b : inout std_logic; ---------------------------------------------------------------------------- -- Wishbone bus - Port 0 ---------------------------------------------------------------------------- --! Wishbone bus clock wb0_clk_i : in std_logic; --! Wishbone bus byte select wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0); --! Wishbone bus cycle select wb0_cyc_i : in std_logic; --! Wishbone bus cycle strobe wb0_stb_i : in std_logic; --! Wishbone bus write enable wb0_we_i : in std_logic; --! Wishbone bus address wb0_addr_i : in std_logic_vector(31 downto 0); --! Wishbone bus data input wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus data output wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus acknowledge wb0_ack_o : out std_logic; --! Wishbone bus stall (for pipelined mode) wb0_stall_o : out std_logic; ---------------------------------------------------------------------------- -- Status - Port 0 ---------------------------------------------------------------------------- --! Command FIFO empty p0_cmd_empty_o : out std_logic; --! Command FIFO full p0_cmd_full_o : out std_logic; --! Read FIFO full p0_rd_full_o : out std_logic; --! Read FIFO empty p0_rd_empty_o : out std_logic; --! Read FIFO count p0_rd_count_o : out std_logic_vector(6 downto 0); --! Read FIFO overflow p0_rd_overflow_o : out std_logic; --! Read FIFO error (pointers unsynchronized, reset required) p0_rd_error_o : out std_logic; --! Write FIFO full p0_wr_full_o : out std_logic; --! Write FIFO empty p0_wr_empty_o : out std_logic; --! Write FIFO count p0_wr_count_o : out std_logic_vector(6 downto 0); --! Write FIFO underrun p0_wr_underrun_o : out std_logic; --! Write FIFO error (pointers unsynchronized, reset required) p0_wr_error_o : out std_logic; ---------------------------------------------------------------------------- -- Wishbone bus - Port 1 ---------------------------------------------------------------------------- --! Wishbone bus clock wb1_clk_i : in std_logic; --! Wishbone bus byte select wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0); --! Wishbone bus cycle select wb1_cyc_i : in std_logic; --! Wishbone bus cycle strobe wb1_stb_i : in std_logic; --! Wishbone bus write enable wb1_we_i : in std_logic; --! Wishbone bus address wb1_addr_i : in std_logic_vector(31 downto 0); --! Wishbone bus data input wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus data output wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus acknowledge wb1_ack_o : out std_logic; --! Wishbone bus stall (for pipelined mode) wb1_stall_o : out std_logic; ---------------------------------------------------------------------------- -- Status - Port 1 ---------------------------------------------------------------------------- --! Command FIFO empty p1_cmd_empty_o : out std_logic; --! Command FIFO full p1_cmd_full_o : out std_logic; --! Read FIFO full p1_rd_full_o : out std_logic; --! Read FIFO empty p1_rd_empty_o : out std_logic; --! Read FIFO count p1_rd_count_o : out std_logic_vector(6 downto 0); --! Read FIFO overflow p1_rd_overflow_o : out std_logic; --! Read FIFO error (pointers unsynchronized, reset required) p1_rd_error_o : out std_logic; --! Write FIFO full p1_wr_full_o : out std_logic; --! Write FIFO empty p1_wr_empty_o : out std_logic; --! Write FIFO count p1_wr_count_o : out std_logic_vector(6 downto 0); --! Write FIFO underrun p1_wr_underrun_o : out std_logic; --! Write FIFO error (pointers unsynchronized, reset required) p1_wr_error_o : out std_logic ); end component ddr3_ctrl; component clk_gen port (-- Clock in ports CLK_40_IN : in std_logic; CLKFB_IN : in std_logic; -- Clock out ports CLK_640 : out std_logic; CLK_160 : out std_logic; CLK_80 : out std_logic; CLK_40 : out std_logic; CLK_40_90 : out std_logic; CLKFB_OUT : out std_logic; -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end component; component ila PORT ( CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); CLK : IN STD_LOGIC; TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); end component; component ila_icon PORT ( CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)); end component; ------------------------------------------------------------------------------ -- Constants declaration ------------------------------------------------------------------------------ constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address constant c_CSR_WB_SLAVES_NB : integer := 16; -- upper 4 bits used for addressing slave ------------------------------------------------------------------------------ -- Signals declaration ------------------------------------------------------------------------------ -- System clock signal sys_clk : std_logic; -- IO clocks signal CLK_40 : std_logic; signal CLK_40_90 : std_logic; signal CLK_80 : std_logic; signal CLK_125 : std_logic; signal CLK_160 : std_logic; signal CLK_640 : std_logic; signal CLK_40_buf : std_logic; signal CLK_40_90_buf : std_logic; signal CLK_80_buf : std_logic; signal CLK_160_buf : std_logic; signal CLK_640_buf : std_logic; signal ioclk_fb : std_logic; -- System clock generation signal sys_clk_in : std_logic; signal sys_clk_40_buf : std_logic; signal sys_clk_200_buf : std_logic; signal sys_clk_40 : std_logic; signal sys_clk_200 : std_logic; signal sys_clk_fb : std_logic; signal sys_clk_pll_locked : std_logic; -- DDR3 clock signal ddr_clk : std_logic; signal ddr_clk_buf : std_logic; signal locked : std_logic; signal locked_v : std_logic_vector(1 downto 0); signal rst_n : std_logic; -- LCLK from GN4124 used as system clock signal l_clk : std_logic; -- P2L colck PLL status signal p2l_pll_locked : std_logic; -- CSR wishbone bus (master) signal wbm_adr : std_logic_vector(31 downto 0); signal wbm_dat_i : std_logic_vector(31 downto 0); signal wbm_dat_o : std_logic_vector(31 downto 0); signal wbm_sel : std_logic_vector(3 downto 0); signal wbm_cyc : std_logic; signal wbm_stb : std_logic; signal wbm_we : std_logic; signal wbm_ack : std_logic; signal wbm_stall : std_logic; -- CSR wishbone bus (slaves) signal wb_adr : std_logic_vector(31 downto 0); signal wb_dat_i : std_logic_vector((32c_CSR_WB_SLAVES_NB)-1 downto 0) := (others => '0'); signal wb_dat_o : std_logic_vector(31 downto 0); signal wb_sel : std_logic_vector(3 downto 0); signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0'); signal wb_stb : std_logic; signal wb_we : std_logic; signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0'); signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0'); -- DMA wishbone bus signal dma_adr : std_logic_vector(31 downto 0); signal dma_dat_i : std_logic_vector(31 downto 0); signal dma_dat_o : std_logic_vector(31 downto 0); signal dma_sel : std_logic_vector(3 downto 0); signal dma_cyc : std_logic; signal dma_stb : std_logic; signal dma_we : std_logic; signal dma_ack : std_logic; signal dma_stall : std_logic; signal ram_we : std_logic; -- DMAbus RX bridge signal rx_dma_adr : std_logic_vector(31 downto 0); signal rx_dma_dat_o : std_logic_vector(31 downto 0); signal rx_dma_dat_i : std_logic_vector(31 downto 0); signal rx_dma_cyc : std_logic; signal rx_dma_stb : std_logic; signal rx_dma_we : std_logic; signal rx_dma_ack : std_logic; signal rx_dma_stall : std_logic; -- Interrupts stuff signal irq_sources : std_logic_vector(1 downto 0); signal irq_to_gn4124 : std_logic; signal irq_out : std_logic; -- CSR whisbone slaves for test signal dummy_stat_reg_1 : std_logic_vector(31 downto 0); signal dummy_stat_reg_2 : std_logic_vector(31 downto 0); signal dummy_stat_reg_3 : std_logic_vector(31 downto 0); signal dummy_stat_reg_switch : std_logic_vector(31 downto 0); signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0); signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0); signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0); signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0); -- I2C signal scl_t : std_logic; signal sda_t : std_logic; -- SPI signal scl_s : std_logic; signal sda_s : std_logic; signal latch_s : std_logic; signal sdi_s : std_logic; -- FOR TESTS signal debug : std_logic_vector(31 downto 0); signal clk_div_cnt : unsigned(3 downto 0); signal clk_div : std_logic; -- LED signal led_cnt : unsigned(24 downto 0); signal led_en : std_logic; signal led_k2000 : unsigned(2 downto 0); signal led_pps : std_logic; signal leds : std_logic_vector(3 downto 0); -- ILA signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0); signal TRIG0 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG2 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG0_t : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG1_t : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG2_t : STD_LOGIC_VECTOR(31 DOWNTO 0); signal debug_dma : std_logic_vector(31 downto 0); signal debug_trig : std_logic_vector(31 downto 0); signal ddr_status : std_logic_vector(31 downto 0); signal gn4124_core_Status : std_logic_vector(31 downto 0); signal tx_data_o : std_logic_vector(0 downto 0); signal trig_pulse : std_logic; signal int_trig_t : std_logic; signal trig_tag_t : std_logic_vector(31 downto 0); signal fe_cmd_o : std_logic_vector(c_TX_CHANNELS-1 downto 0); signal fe_cmd_enc : std_logic_vector(c_TX_CHANNELS-1 downto 0); signal fe_cmd_del : std_logic_vector(c_TX_CHANNELS-1 downto 0); signal fe_clk_o : std_logic_vector(c_TX_CHANNELS-1 downto 0); signal fe_data_i : std_logic_vector(c_RX_CHANNELS-1 downto 0); signal rx_data : std_logic_vector(31 downto 0); signal rx_valid : std_logic; signal rx_busy : std_logic; signal ext_trig_i : std_logic_vector(3 downto 0); begin -- Activate LVDS buffer --pwdn_l <= (others => '1'); -- Differential buffers tx_loop: for I in 0 to c_TX_CHANNELS-1 generate begin tx_buf : OBUFDS generic map ( IOSTANDARD => "LVDS_25") port map ( O => fe_cmd_p(I), -- Diff_p output (connect directly to top-level port) OB => fe_cmd_n(I), -- Diff_n output (connect directly to top-level port) I => fe_cmd_enc(I) -- Buffer input ); ODDR2_manchester : ODDR2 generic map( DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" INIT => '0', -- Sets initial state of the Q output to '0' or '1' SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset port map ( Q => fe_cmd_enc(I), -- 1-bit output data C0 => clk_40, -- 1-bit clock input C1 => not clk_40, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => fe_cmd_o(I), -- 1-bit data input (associated with C0) D1 => not fe_cmd_o(I), -- 1-bit data input (associated with C1) R => not rst_n, -- 1-bit reset input S => '0' -- 1-bit set input ); clk_buf : OBUFDS generic map ( IOSTANDARD => "LVDS_25") port map ( O => fe_clk_p(I), -- Diff_p output (connect directly to top-level port) OB => fe_clk_n(I), -- Diff_n output (connect directly to top-level port) I => fe_clk_o(I) -- Buffer input ); ODDR2_inst : ODDR2 generic map( DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" INIT => '0', -- Sets initial state of the Q output to '0' or '1' SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset port map ( Q => fe_clk_o(I), -- 1-bit output data C0 => clk_40_90, -- 1-bit clock input C1 => not clk_40_90, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => '1', -- 1-bit data input (associated with C0) D1 => '0', -- 1-bit data input (associated with C1) R => not rst_n, -- 1-bit reset input S => '0' -- 1-bit set input ); end generate; rx_loop: for I in 0 to c_RX_CHANNELS-1 generate begin rx_buf : IBUFDS generic map ( DIFF_TERM => TRUE, -- Differential Termination IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "LVDS_25") port map ( O => fe_data_i(I), -- Buffer output I => fe_data_p(I), -- Diff_p buffer input (connect directly to top-level port) IB => fe_data_n(I) -- Diff_n buffer input (connect directly to top-level port) ); end generate; ------------------------------------------------------------------------------ -- Local clock from gennum LCLK ------------------------------------------------------------------------------ IBUFGDS_gn_clk : IBUFGDS generic map ( DIFF_TERM => TRUE, -- Differential Termination IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DIFF_SSTL18_I" ) port map ( O => l_clk, -- Clock buffer output I => L_CLKp, -- Diff_p clock buffer input (connect directly to top-level port) IB => L_CLKn -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFGDS_pll_clk : IBUFGDS generic map ( DIFF_TERM => TRUE, -- Differential Termination IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "LVDS_25" ) port map ( O => CLK_125, -- Clock buffer output I => clk_125m_pllref_p_i, -- Diff_p clock buffer input (connect directly to top-level port) IB => clk_125m_pllref_n_i -- Diff_n clock buffer input (connect directly to top-level port) ); ------------------------------------------------------------------------------ -- GN4124 interface ------------------------------------------------------------------------------ cmp_gn4124_core : gn4124_core port map ( --------------------------------------------------------- -- Control and status rst_n_a_i => rst_n, status_o => gn4124_core_status, --------------------------------------------------------- -- P2L Direction -- -- Source Sync DDR related signals p2l_clk_p_i => P2L_CLKp, p2l_clk_n_i => P2L_CLKn, p2l_data_i => P2L_DATA, p2l_dframe_i => P2L_DFRAME, p2l_valid_i => P2L_VALID, -- P2L Control p2l_rdy_o => P2L_RDY, p_wr_req_i => P_WR_REQ, p_wr_rdy_o => P_WR_RDY, rx_error_o => RX_ERROR, --------------------------------------------------------- -- L2P Direction -- -- Source Sync DDR related signals l2p_clk_p_o => L2P_CLKp, l2p_clk_n_o => L2P_CLKn, l2p_data_o => L2P_DATA, l2p_dframe_o => L2P_DFRAME, l2p_valid_o => L2P_VALID, l2p_edb_o => L2P_EDB, -- L2P Control l2p_rdy_i => L2P_RDY, l_wr_rdy_i => L_WR_RDY, p_rd_d_rdy_i => P_RD_D_RDY, tx_error_i => TX_ERROR, vc_rdy_i => VC_RDY, --------------------------------------------------------- -- Interrupt interface dma_irq_o => irq_sources, irq_p_i => irq_to_gn4124, irq_p_o => irq_out, --------------------------------------------------------- -- DMA registers wishbone interface (slave classic) dma_reg_clk_i => sys_clk, dma_reg_adr_i => wb_adr, dma_reg_dat_i => wb_dat_o, dma_reg_sel_i => wb_sel, dma_reg_stb_i => wb_stb, dma_reg_we_i => wb_we, dma_reg_cyc_i => wb_cyc(0), dma_reg_dat_o => wb_dat_i(31 downto 0), dma_reg_ack_o => wb_ack(0), dma_reg_stall_o => wb_stall(0), --------------------------------------------------------- -- CSR wishbone interface (master pipelined) csr_clk_i => sys_clk, csr_adr_o => wbm_adr, csr_dat_o => wbm_dat_o, csr_sel_o => wbm_sel, csr_stb_o => wbm_stb, csr_we_o => wbm_we, csr_cyc_o => wbm_cyc, csr_dat_i => wbm_dat_i, csr_ack_i => wbm_ack, csr_stall_i => wbm_stall, csr_err_i => '0', csr_rty_i => '0', csr_int_i => '0', --------------------------------------------------------- -- DMA wishbone interface (master pipelined) dma_clk_i => sys_clk, dma_adr_o => dma_adr, dma_dat_o => dma_dat_o, dma_sel_o => dma_sel, dma_stb_o => dma_stb, dma_we_o => dma_we, dma_cyc_o => dma_cyc, dma_dat_i => dma_dat_i, dma_ack_i => dma_ack, dma_stall_i => dma_stall, dma_err_i => '0', dma_rty_i => '0', dma_int_i => '0' ); GPIO(0) <= irq_out; GPIO(1) <= '0'; ------------------------------------------------------------------------------ -- CSR wishbone address decoder ------------------------------------------------------------------------------ cmp_csr_wb_addr_decoder : wb_addr_decoder generic map ( g_WINDOW_SIZE => c_BAR0_APERTURE, g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB ) port map ( --------------------------------------------------------- -- GN4124 core clock and reset clk_i => sys_clk, rst_n_i => rst_n, --------------------------------------------------------- -- wishbone master interface wbm_adr_i => wbm_adr, wbm_dat_i => wbm_dat_o, wbm_sel_i => wbm_sel, wbm_stb_i => wbm_stb, wbm_we_i => wbm_we, wbm_cyc_i => wbm_cyc, wbm_dat_o => wbm_dat_i, wbm_ack_o => wbm_ack, wbm_stall_o => wbm_stall, --------------------------------------------------------- -- wishbone slaves interface wb_adr_o => wb_adr, wb_dat_o => wb_dat_o, wb_sel_o => wb_sel, wb_stb_o => wb_stb, wb_we_o => wb_we, wb_cyc_o => wb_cyc, wb_dat_i => wb_dat_i, wb_ack_i => wb_ack, wb_stall_i => wb_stall ); ------------------------------------------------------------------------------ -- CSR wishbone bus slaves ------------------------------------------------------------------------------ -- cmp_dummy_stat_regs : dummy_stat_regs_wb_slave -- port map( -- rst_n_i => rst_n, -- wb_clk_i => sys_clk, -- wb_addr_i => wb_adr(1 downto 0), -- wb_data_i => wb_dat_o, -- wb_data_o => wb_dat_i(63 downto 32), -- wb_cyc_i => wb_cyc(1), -- wb_sel_i => wb_sel, -- wb_stb_i => wb_stb, -- wb_we_i => wb_we, -- wb_ack_o => wb_ack(1), -- dummy_stat_reg_1_i => dummy_stat_reg_1, -- dummy_stat_reg_2_i => dummy_stat_reg_2, -- dummy_stat_reg_3_i => dummy_stat_reg_3, -- dummy_stat_reg_switch_i => dummy_stat_reg_switch -- ); -- OBUF_tx : OBUF -- generic map ( -- DRIVE => 12, -- IOSTANDARD => "DEFAULT", -- SLEW => "FAST") -- port map ( -- O => ext_trig, -- Buffer output (connect directly to top-level port) -- I => fe_data_i(0) -- Buffer input -- ); cmp_wb_tx_core : wb_tx_core port map ( -- Sys connect wb_clk_i => sys_clk, rst_n_i => rst_n, -- Wishbone slave interface wb_adr_i => wb_adr, wb_dat_i => wb_dat_o, wb_dat_o => wb_dat_i(63 downto 32), wb_cyc_i => wb_cyc(1), wb_stb_i => wb_stb, wb_we_i => wb_we, wb_ack_o => wb_ack(1), wb_stall_o => wb_stall(1), -- TX tx_clk_i => CLK_40, tx_data_o => fe_cmd_o, trig_pulse_o => trig_pulse, -- Trig ext_trig_i => int_trig_t ); cmp_wb_rx_core: wb_rx_core PORT MAP( wb_clk_i => sys_clk, rst_n_i => rst_n, wb_adr_i => wb_adr, wb_dat_i => wb_dat_o, wb_dat_o => wb_dat_i(95 downto 64), wb_cyc_i => wb_cyc(2), wb_stb_i => wb_stb, wb_we_i => wb_we, wb_ack_o => wb_ack(2), wb_stall_o => wb_stall(2), rx_clk_i => CLK_160, rx_serdes_clk_i => CLK_640_buf, rx_clk_locked_i => locked, rx_data_i => not fe_data_i, rx_valid_o => rx_valid, rx_data_o => rx_data, trig_tag_i => trig_tag_t, busy_o => open, debug_o => debug ); cmp_wb_rx_bridge : wb_rx_bridge port map ( -- Sys Connect sys_clk_i => sys_clk, rst_n_i => rst_n, -- Wishbone slave interface wb_adr_i => wb_adr, wb_dat_i => wb_dat_o, wb_dat_o => wb_dat_i(127 downto 96), wb_cyc_i => wb_cyc(3), wb_stb_i => wb_stb, wb_we_i => wb_we, wb_ack_o => wb_ack(3), wb_stall_o => wb_stall(3), -- Wishbone DMA Master Interface dma_clk_i => sys_clk, dma_adr_o => rx_dma_adr, dma_dat_o => rx_dma_dat_o, dma_dat_i => rx_dma_dat_i, dma_cyc_o => rx_dma_cyc, dma_stb_o => rx_dma_stb, dma_we_o => rx_dma_we, dma_ack_i => rx_dma_ack, dma_stall_i => rx_dma_stall, -- Rx Interface (sync to sys_clk) rx_data_i => rx_data, rx_valid_i => rx_valid, -- Status in trig_pulse_i => trig_pulse, -- Status out irq_o => open, busy_o => rx_busy ); wb_dat_i(159 downto 136) <= (others => '0'); wb_dat_i(135 downto 128) <= (others => '0'); -- cmp_i2c_master : i2c_master_wb_top -- port map ( -- wb_clk_i => sys_clk, -- wb_rst_i => not rst_n, -- arst_i => rst_n, -- wb_adr_i => wb_adr(2 downto 0), -- wb_dat_i => wb_dat_o(7 downto 0), -- wb_dat_o => wb_dat_i(135 downto 128), -- wb_we_i => wb_we, -- wb_stb_i => wb_stb, -- wb_cyc_i => wb_cyc(4), -- wb_ack_o => wb_ack(4), -- wb_inta_o => open, -- scl => open, -- sda => open -- ); -- HitOr ext_trig_buf_0 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(0), I => ext_trig_p(0), IB => ext_trig_n(0)); ext_trig_buf_1 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(1), I => ext_trig_p(1), IB => ext_trig_n(1)); ext_trig_buf_2 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(2), I => ext_trig_p(2), IB => ext_trig_n(2)); ext_trig_buf_3 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(3), I => ext_trig_p(3), IB => ext_trig_n(3)); cmp_wb_trigger_logic: wb_trigger_logic PORT MAP( wb_clk_i => sys_clk, rst_n_i => rst_n, wb_adr_i => wb_adr(31 downto 0), wb_dat_i => wb_dat_o(31 downto 0), wb_dat_o => wb_dat_i(191 downto 160), wb_cyc_i => wb_cyc(5), wb_stb_i => wb_stb, wb_we_i => wb_we, wb_ack_o => wb_ack(5), ext_trig_i => ext_trig_i, ext_trig_o => int_trig_t, ext_busy_i => '0', ext_busy_o => open, eudet_clk_o => open, eudet_busy_o => open, eudet_trig_i => '0', eudet_rst_i => '0', clk_i => CLK_40, trig_tag => trig_tag_t, debug_o => debug_trig ); scl_o <= scl_s; sda_o <= sda_s; sdi_s <= sdi_i; latch_o <= latch_s; -- cmp_wb_spi: wb_spi port map ( -- wb_clk_i => sys_clk, -- rst_n_i => rst_n, -- wb_adr_i => wb_adr(31 downto 0), -- wb_dat_i => wb_dat_o(31 downto 0), -- wb_dat_o => wb_dat_i(223 downto 192), -- wb_cyc_i => wb_cyc(6), -- wb_stb_i => wb_stb, -- wb_we_i => wb_we, -- wb_ack_o => wb_ack(6), -- scl_o => scl_s, -- sda_o => sda_s, -- sdi_i => sdi_s, -- latch_o => latch_s -- ); --wb_stall(1) <= '0' when wb_cyc(1) = '0' else not(wb_ack(1)); -- wb_stall(2) <= '0' when wb_cyc(2) = '0' else not(wb_ack(2)); -- dummy_stat_reg_1 <= X"DEADBABE"; -- dummy_stat_reg_2 <= X"BEEFFACE"; -- dummy_stat_reg_3 <= X"12345678"; -- dummy_stat_reg_switch <= X"0000000" & "000" & p2l_pll_locked; led_red_o <= dummy_ctrl_reg_led(0); led_green_o <= dummy_ctrl_reg_led(1); -- TRIG0(31 downto 0) <= (others => '0'); TRIG1(31 downto 0) <= (others => '0'); TRIG2(31 downto 0) <= (others => '0'); -- TRIG0(12 downto 0) <= (others => '0'); --TRIG1(31 downto 0) <= rx_dma_dat_o; --TRIG1(31 downto 0) <= dma_dat_i; -- TRIG1(31 downto 0) <= gn4124_core_status; -- TRIG2(31 downto 0) <= ddr_status; -- TRIG0(13) <= rx_dma_cyc; -- TRIG0(14) <= rx_dma_stb; -- TRIG0(15) <= rx_dma_we; -- TRIG0(16) <= rx_dma_ack; -- TRIG0(17) <= rx_dma_stall; -- TRIG0(18) <= dma_cyc; -- TRIG0(19) <= dma_stb; -- TRIG0(20) <= dma_we; -- TRIG0(21) <= dma_ack; -- TRIG0(22) <= dma_stall; -- TRIG0(23) <= irq_out; -- TRIG0(24) <= rx_busy; -- TRIG0(31 downto 25) <= (others => '0'); TRIG0(0) <= int_trig_t; TRIG0(4 downto 1) <= ext_trig_i; TRIG0(31 downto 5) <= (others => '0'); -- TRIG1 <= rx_data; -- TRIG2 <= debug; -- TRIG0(0) <= scl; -- TRIG0(1) <= sda; -- TRIG0(2) <= wb_stb; -- TRIG0(3) <= wb_ack(4); -- TRIG0(31 downto 4) <= (others => '0'); -- TRIG1 <= wb_adr; -- TRIG2 <= wb_dat_o; -- ila_i : ila -- port map ( -- CONTROL => CONTROL, -- CLK => CLK_40, ---- CLK => sys_clk, -- TRIG0 => TRIG0, -- TRIG1 => TRIG1, -- TRIG2 => TRIG2); ---- -- ila_icon_i : ila_icon -- port map ( -- CONTROL0 => CONTROL); ------------------------------------------------------------------------------ -- Interrupt stuff ------------------------------------------------------------------------------ -- just forward irq pulses for test irq_to_gn4124 <= irq_sources(1) or irq_sources(0); ------------------------------------------------------------------------------ -- FOR TEST ------------------------------------------------------------------------------ p_led_cnt : process (L_RST_N, sys_clk) begin if L_RST_N = '0' then led_cnt <= (others => '1'); led_en <= '1'; elsif rising_edge(sys_clk) then led_cnt <= led_cnt - 1; led_en <= led_cnt(23); end if; end process p_led_cnt; led_pps <= led_cnt(23) and not(led_en); p_led_k2000 : process (sys_clk, L_RST_N) begin if L_RST_N = '0' then led_k2000 <= (others => '0'); leds <= "0001"; elsif rising_edge(sys_clk) then if led_pps = '1' then if led_k2000(2) = '0' then if leds /= "1000" then leds <= leds(2 downto 0) & '0'; end if; else if leds /= "0001" then leds <= '0' & leds(3 downto 1); end if; end if; led_k2000 <= led_k2000 + 1; end if; end if; end process p_led_k2000; AUX_LEDS_O <= not(leds); --AUX_LEDS_O(0) <= led_en; --AUX_LEDS_O(1) <= not(led_en); --AUX_LEDS_O(2) <= '1'; --AUX_LEDS_O(3) <= '0'; rst_n <= (L_RST_N and sys_clk_pll_locked and locked); cmp_clk_gen : clk_gen port map ( -- Clock in ports CLK_40_IN => sys_clk_40, CLKFB_IN => ioclk_fb, -- Clock out ports CLK_640 => CLK_640_buf, CLK_160 => CLK_160_buf, CLK_80 => CLK_80_buf, CLK_40 => CLK_40_buf, CLK_40_90 => CLK_40_90_buf, CLKFB_OUT => ioclk_fb, -- Status and control signals RESET => not L_RST_N, LOCKED => locked ); -- BUFPLL_640 : BUFPLL -- generic map ( -- DIVIDE => 4, -- DIVCLK divider (1-8) -- ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) -- ) -- port map ( -- IOCLK => CLK_640, -- 1-bit output: Output I/O clock -- LOCK => open, -- 1-bit output: Synchronized LOCK output -- SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2) -- GCLK => CLK_160, -- 1-bit input: BUFG clock input -- LOCKED => locked, -- 1-bit input: LOCKED input from PLL -- PLLIN => clk_640_buf -- 1-bit input: Clock input from PLL -- ); -- cmp_ioclk_640_buf : BUFG -- port map ( -- O => CLK_640, -- I => CLK_640_buf); cmp_ioclk_160_buf : BUFG port map ( O => CLK_160, I => CLK_160_buf); cmp_ioclk_80_buf : BUFG port map ( O => CLK_80, I => CLK_80_buf); cmp_ioclk_40_buf : BUFG port map ( O => CLK_40, I => CLK_40_buf); cmp_ioclk_40_90_buf : BUFG port map ( O => CLK_40_90, I => CLK_40_90_buf); ------------------------------------------------------------------------------ -- Clocks distribution from 20MHz TCXO -- 40.000 MHz IO driver clock -- 200.000 MHz fast system clock -- 333.333 MHz DDR3 clock ------------------------------------------------------------------------------ sys_clk <= l_clk; -- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a -- write sequence arrives to the DAC. -- To avoid spurious writes, the DAC interface outputs are fixed to safe values. pll25dac_sync_n <= '1'; pll20dac_sync_n <= '1'; plldac_din <= '0'; plldac_sclk <= '0'; cmp_sys_clk_buf : IBUFG port map ( I => clk20_vcxo_i, O => sys_clk_in); cmp_sys_clk_pll : PLL_BASE generic map ( BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 50, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 25, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT2_DIVIDE => 3, CLKOUT2_PHASE => 0.000, CLKOUT2_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 50.0, REF_JITTER => 0.016) port map ( CLKFBOUT => sys_clk_fb, CLKOUT0 => sys_clk_40_buf, CLKOUT1 => sys_clk_200_buf, CLKOUT2 => ddr_clk_buf, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, LOCKED => sys_clk_pll_locked, RST => '0', CLKFBIN => sys_clk_fb, CLKIN => sys_clk_in); cmp_clk_125_buf : BUFG port map ( O => sys_clk_40, I => sys_clk_40_buf); cmp_clk_200_buf : BUFG port map ( O => sys_clk_200, I => sys_clk_200_buf); cmp_ddr_clk_buf : BUFG port map ( O => ddr_clk, I => ddr_clk_buf); cmp_ddr3_ctrl: ddr3_ctrl PORT MAP( clk_i => ddr_clk, rst_n_i => rst_n, status_o => ddr_status, ddr3_dq_b => DDR3_DQ, ddr3_a_o => DDR3_A, ddr3_ba_o => DDR3_BA, ddr3_ras_n_o => DDR3_RAS_N, ddr3_cas_n_o => DDR3_CAS_N, ddr3_we_n_o => DDR3_WE_N, ddr3_odt_o => DDR3_ODT, ddr3_rst_n_o => DDR3_RESET_N, ddr3_cke_o => DDR3_CKE, ddr3_dm_o => DDR3_LDM, ddr3_udm_o => DDR3_UDM, ddr3_dqs_p_b => DDR3_LDQS_P, ddr3_dqs_n_b => DDR3_LDQS_N, ddr3_udqs_p_b => DDR3_UDQS_P, ddr3_udqs_n_b => DDR3_UDQS_N, ddr3_clk_p_o => DDR3_CK_P, ddr3_clk_n_o => DDR3_CK_N, ddr3_rzq_b => DDR3_RZQ, ddr3_zio_b => DDR3_ZIO, wb0_clk_i => sys_clk, wb0_sel_i => dma_sel, wb0_cyc_i => dma_cyc, wb0_stb_i => dma_stb, wb0_we_i => dma_we, wb0_addr_i => dma_adr, wb0_data_i => dma_dat_o, wb0_data_o => dma_dat_i, wb0_ack_o => dma_ack, wb0_stall_o => dma_stall, p0_cmd_empty_o => open, p0_cmd_full_o => open, p0_rd_full_o => open, p0_rd_empty_o => open, p0_rd_count_o => open, p0_rd_overflow_o => open, p0_rd_error_o => open, p0_wr_full_o => open, p0_wr_empty_o => open, p0_wr_count_o => open, p0_wr_underrun_o => open, p0_wr_error_o => open, wb1_clk_i => sys_clk, wb1_sel_i => "1111", wb1_cyc_i => rx_dma_cyc, wb1_stb_i => rx_dma_stb, wb1_we_i => rx_dma_we, wb1_addr_i => rx_dma_adr, wb1_data_i => rx_dma_dat_o, wb1_data_o => rx_dma_dat_i, wb1_ack_o => rx_dma_ack, wb1_stall_o => rx_dma_stall, p1_cmd_empty_o => open, p1_cmd_full_o => open, p1_rd_full_o => open, p1_rd_empty_o => open, p1_rd_count_o => open, p1_rd_overflow_o => open, p1_rd_error_o => open, p1_wr_full_o => open, p1_wr_empty_o => open, p1_wr_count_o => open, p1_wr_underrun_o => open, p1_wr_error_o => open ); end rtl;	gpl-3.0	da8c79ff3bcf097e084fa7a24e9d0ada	0.516363	3.034204	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/xor18.vhd	1	8,446	------------------------------------------------------------------------------- -- xor18.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: xor18.vhd -- -- Description: Basic 18-bit input XOR function. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add default on C_USE_LUT6 parameter. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity XOR18 is generic ( C_USE_LUT6 : boolean := FALSE ); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end entity XOR18; architecture IMP of XOR18 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; begin -- architecture IMP Using_LUT6: if (C_USE_LUT6) generate signal xor6_1 : std_logic; signal xor6_2 : std_logic; signal xor6_3 : std_logic; signal xor18_c1 : std_logic; signal xor18_c2 : std_logic; begin -- generate Using_LUT6 XOR6_1_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_1, I0 => InA(17), I1 => InA(16), I2 => InA(15), I3 => InA(14), I4 => InA(13), I5 => InA(12)); XOR_1st_MUXCY : MUXCY_L port map ( DI => '1', CI => '0', S => xor6_1, LO => xor18_c1); XOR6_2_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_2, I0 => InA(11), I1 => InA(10), I2 => InA(9), I3 => InA(8), I4 => InA(7), I5 => InA(6)); XOR_2nd_MUXCY : MUXCY_L port map ( DI => xor6_1, CI => xor18_c1, S => xor6_2, LO => xor18_c2); XOR6_3_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_3, I0 => InA(5), I1 => InA(4), I2 => InA(3), I3 => InA(2), I4 => InA(1), I5 => InA(0)); XOR18_XORCY : XORCY port map ( LI => xor6_3, CI => xor18_c2, O => res); end generate Using_LUT6; Not_Using_LUT6: if (not C_USE_LUT6) generate begin -- generate Not_Using_LUT6 res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0); end generate Not_Using_LUT6; end architecture IMP;	bsd-2-clause	c17072acb9421830fc3ad935d452f40e	0.467203	4.144259	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/input_blk.vhd	2	28,006	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block SAh83CYn+CrtyHs0wyLF3VZv7cA1BH4CvBkoLi0+D5t++bHzQKzTaWdgRcQakBSVQfoCVQ57Dtcu /gfHTdwkyg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block T8mCWsTo81Bff4GR3bCqwHvlpS5llu0XD0bVs8KMe1b8xOVbAQ0tlBpPX+11PLa6S4Tx52HdCMid Ji4wsQAC0dlhvOCdo4vfSKwt2GCvbuSZRJuPlKEU9A/Jp7oXmp5U8qURf/uF8dZsM5rKIKAc3kLw TlxqVAsBXLlaKjJnqnU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block wmClIagxRVsaBkVFxQR8giGUjYRKy4pvBXPzDRK1c/MNyglPhyuQLTfRqM+MKzsZtJmI0/l4Jrhd pNGPM1aKVRbogyam+Z2c1W89AwhrDmK33fdxLDRxhlWU6IvTA9VJJ/G9TDuUWcZVNb6DTwluEs2N DkeqvaUTAwPJfnkFi1adjsfcAfp37ObxlIwiRn0cdVbSEaCu5zI89JE/Mod7sWEDKUXI3JNeYVZ4 MDhA//wl1sRLmOCHrR1kt1zebehHC7yamnc90ypwaek4BCme2p+7KZKI/x1kkr4tdcSNrQBRbhqu mWfoCod/aFHIygKeq7wmAg6IaVLn5XIdtIFEnQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OQDS5QzbdigqBbuTfyjXAHip3WhAej0wpUsGwXP4uTxQcjoiYdPPVW88nLKTBI8rwViYTb1vSM31 Amk84oATYU5rt7aKJNK5NzkyeZg2UJRCBWXipqQWWKzmOOUEi0DRNpDkJypYg2OUxfer/O3iF1yC ZkQatpBquyhsjRWeP10= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Xxex9T7KxI7m/X0Yh6PnC4byFdfdmi06z/WDE7fgqH/SJtIm1IQLBkP+wmsZn8Mq5Oz128ru1Rbp yMwjjLB52n+0J5ZAtaBT7Z2PPwdorbQ06n30Gyhtdo4YBNOIDMCXx6NjP8WMZaKyqrmgOaq6UIkQ lTdXjpXcdUyzHhJbj81gldXMApAc2PhhPO3SbFMTlgzLZl4rs24dXvVQrpRlS0ka+Y5e0SQCInh6 HujQDR5JuGdZYjf158i2Xvod2ds25NWN4fRyKciir7b+6su4DT1uYBGkl1MZ7JiEfaIe0ibAxp7i 261sdm9rzvRuiY1swfKdBZXfXj+RIJw5PrEu3Q== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18992) `protect data_block TLP/NXUyqvkYSgNXANUCkc+DjXpO4zDUJ0QmBRzzZo5I4eDcWHvP0yUoSjoCc4RvfWWK897ULGRc bPA/bSIJ031kSOnENR0Ka7A5ujtTt+EdNZytuQkJdHdIPQ1+7mjXC3HjX4xyR+mWIQ2NDqku40Xm 4Di8vJ+i2ap+OysgOP83RBTYDiRm0BSL3w0JAK6aDcS45IRAIIbxrXAz1hWydy5Jn/dA7XFOElKr PqEOGGsLj8pPfUHlJ6b4ygytRTafqToSCqhUaagpAz2+V2oo1XCn5vplmBFO8SuxCwXdHtVGCo2o 40RGsAvQqon8IDZ6xDtVxj1K9nPLAGwntFMKSPOR309MtoSh9VQPAiwiXJSG1hXtVL5mWCbk9jE7 52RKOI1jL/6d6XFNHNNtCIfLR6CK+pRp6vO8biHpV96Xuz93aOSWtnei9LANfHCT91960vrfCqfU L7Gi6cDo7+HlYq/5Pk/JSnrSf6OrYAj9S8stD91lgloCGKuBwwuM1+GYv8V8cZB5ionejRRdRegw NhIbJ6Z6hqkHJSoQCIEhWt1tU+Y2Z1e643bdXe7t87xfEYdh0Dlu/W4xduzZE8huPatzy3Q+zCkf CoNiBxzayuM+8fWI/Mz375+dPAbE4eyiH/tpWWP139FmFeW6EGqEgqF71jPIpRuNLcQa7UnWREpT a43wYj/BQtPThOFRAejk+2ZOSSYHi4Qa04CoXZSwGjwPawDJdojAQtSR99hLGlhmxqsZgK0yNbVH zVbjM1soCHh7bvQ7bX00Ghy2ONzWp1+MSxbZoh2O4FQco8GqCOND7FsNcwuz4O9d82K7Rcb7KUrs reT6TGPfO43ka5nWEnSupKtnr+Oaa0h//HijVdKYwhy00hRy87hLJLcVxAze8mBB/qOmP8feBAtG KWq1cHzaf+o85KBbVxMDWPgiT6BrF83KF1tTLCDLtUG7xqyDYHZqhwoXYTinOZguI7RrhK+R0R+c ucdRcfykN+3EYd5cv2E2FRpWnfNoGmM/GIK6Jsk3wUU+mlE4Aw7rCghsyBdENibluDkul7fEpvbp 0i0qyih0HDiLx/GsBTsGLCwnVeE6Y46m/D/w5mTmFSc0QvCZYmCvhyKb/omgP2lVoGYRwJaEnc6P mfs7BZWXAIDzv6Tu/vifZO5achgo0nxyCPNB4aTMvRGi2vB3csoZwMFI7hMpKyt3lMC1n83wtHMl G1fe9ohuuiNC4kUibj3dofTiRyp3PVjPiapfbqBAv1FNgb4uYXJAKJPQcC8ZrLasL2zCufeOX4tQ Xe/a9c3s4xKtdu4ymo53lCHKKf3sNpaJNu3WTiXfIPGquwuVhAJUvkR/DqNJz0R4rK6RUmbmruFQ g41lU5S0FnTnX3AEVt9x3II/jBT5uVHy+O7aFMWMnbhorf93CkXsC3MKW6FE3OZvrv2Tyv9FBA6u J8XBNq1h7BmQHv3zGgHtQ3W4F68WbmysfwEMmv7NG5M648FbjW993Ko7kbYrUwsxSJ4oGKLPe/ir ShoAn92AEt0kTbi2c6R0oKpFkWkvb9m6Dz8B4/YMeMP5hqgIiSD45Ug6yOgs/aTyd5Utmpyrp62H nqghC8Wly7zG9b8+VtST/XyJlwa3zmIhCqbemxRmXOczAgBIp0SJbacnyHJH57RZ6ZzCMGzITB3/ ZeIqXVDWEhr8S5uvmhhMZK7PX4nfGGCv5eV2zHQPotoTL52UcR46UeEtoVJSxhimewYARCI3s90d Br4zP15lkGkf38vGFu92y9UlzPo7ehV4dVU0nO0ZNeThcDEwQnNSa+RVoZ59OcmXiPcEVqWcERwl Bdc4HPkhifcIHOLZbINLOkq8aT5B18SZdbqidkCg0HGErOeLqLo7FVFZEY35b2Kq3yhfaMjQNmZy Cgtc0O537SRFEPR8RvWWXve18FWJR8ikuXYOZ6jf59aN+yQGaxAMZ71SX/4dItQ+RY9fhj1U8iTf EMZNIZ+ilS2CHpM/cSWCgtpNsmE+QNLfMKwImqhCC4nosqzeH3mvKFi5NCeCxpGo7cRsHja3kQYV yZIS6GjE4yVnAgRhxfYDUPEmnOO9ye8DG0SlVqrS1zC7rPLuGN8g/hRum8xUkcIFNTCsbdqpOalT 712ke6dXuk1uGPWfXJYuVQZDzHsyGW9lzfF6osONhD0zBWCLz0QvB9cVF2zqqWDIyEC6rX4PN4eg vWcBOKHHM0mrGdQKmuhD8mPQdryThpPFLX3hmHyrY+b2T/iW7+r3X+PtevmGBhAnCmU89hRFIkzg R/Rg6b9lpeag6I7bmdq1Cn9FffqEEH4+FitTN6P+RqsEXzCgbvEmGzYtuZf2vC7TDhcrKVLel+HC 3BgzalTdEA+D0Ch3DNmz/YSWyNy7H8cOv6BkV4kFKr4E2zMtS88JHnWi+I8XcS292u9GXuSDs+CD z6SoLmg2j1mYymkDJ/450GgqjNLj4ZhEA/jrCfuSQC6TF1ClqHKzyRPV711ZTTQ8f0nxrS9cQ3Pa ysqbKB2g3YaMXo40VuC5d0LojRxrRFJiVf1oNB+1ajLGOToPzhbJjhSCng6jROVv7hzJSQ6ppDzy m3PQw+PDTsYl5bDy977o70mIzYImuNmw+ZXyargTR55kO7CicROrr1KqHifXQ4UB3sSdewnhaf9/ ljFd7faXKTBPkXtgNe5jW5C63PBXOBvf+S+pMF2ebs3oejYMN+XRIejgRCwrUraStot0a2oN5MWO RNMNr3PC1IlL8VqQWSt1eZZdQx2vFzqjTwvwzksDObytqn4PWKrkSVqZxohiLUNePbcd6/+96iUr LsvwpaaKN4TiYh+yUZVE/86NPuATJyjQKZyoUopauULVMhjGQTjfGq/GV1xkLS3FxzDqkm8fsUHV oh9EyEgqarqXIn6IXIEW+XcOfRrFi4jQ0memTBxAd8ByFa4Yps2d6ofbLOiY8pw1bVNG7ECmO93o 3iIR6iMA0JTiJ8zCh/4lEExKq4v6lWXt/lTlJgIWS7lZXTJA0OMFd3XdZ25cp0LaMWmDphv5NKjt 0XF7xxc+Jrm0gy0QEqup6jN8Y0wvX02bNvhXZVXknJlmGZ2aU5B7vrRBin++sQQJw7bjo476luIQ PbBg54DLG81/iAaMG+mT1Ujc8UMCp2I1kNs7YCAPJ7Vw5/BLOWtoj9PWY8NqJlX61CKuueuxPA/v vJ+ty/uPaJeNi8BoNH2tbVxNe/CckNNewISpVKEB2MoM43cQ8R2of88vfdBG2q37TWridHZ20Wti EkFApL7lucFH/Pb2nkOQIuIKGFFFUYLyO46xr7IeYAzvIRnvlM+InSpVbYgkPZ5nI26xZCektPFy fvTEU/rQFU+Y/dzLON7wGJdsBp1ag4/B9L/UPxlt7wsZmdwH9sv8gCKaaQDdeCscXryqDWDKIsmH lS4HEgm4/uj4ai1OTbj8cKKoCX/4Fd1NT1TGGWGprhXQzmmNWULBInTrby76342tCFDXT0rIVnNY cYD2M7xcNlcqxbippKZSBsa/UR1mjrSPfQu3mZH0CoPhQbZTQNDQUXCpRqA2zji3V5he+wYWSjRz Go2UhK88QkMibIwbSwWDAD1+TaP2pnehbNFguMZ9feBK4iNGQZQWSsT9YUjNPvQBrcHrLelvDKkY tylbFSHOkfMCOJwWy1PyjcuyxI4yfufJQ31Z1OHEklGcvpPly44BtIX5Jomq3YJ5wgeIzf2ZLmq7 9ShUtEiLuJhwJ0va1l5BsztmFv6qDAp0DPc40lyw0FQ+MFRC1EPTqsHS/sVCH6k59osV54CVWiWU fdLbnR5FsbZRiMqNo3sK/nikkKsA/pSmoY6yhfD5vJLSf4M3LjnyOSUaQsSjvSFbHYzZ7mYvPJbA FYmmqdVRko+XVmZNpwrEtX6iKZwmLB/xobLTOVyXapIUj3ACZWQFHexhiUG/13+GV1HJABLhNqDH Z3UNc4jUayx59HZOgttVZ2xTit6rbcbyh2M9Too8in0QfEtD1+z0ODv7wB8CC32M7KiLNsMJ3DaW NHFlOw5bLPS4o2G9Sf4xZ/gSJ5om2bZg5qw0NetWXt03xDssx3oiPxW/0fd+PWI3hfHE7ZtRf2WL Yv5glGL5GBSkZ9UW7Y8VcginvV8u/btGPF16lwc1wMwBg4rLvGG0CB/G1qVjUVWXr2rzefI+5pnA ohhz6hv8o3oAOPgJhAaRfwlyvR9yFXCmWFXDJcejm2LdnqogorvwBsZruXGTmvMIDvb6HQP3Pxe0 S1ILuhfR5uWB6AIxHoudcK+zcfOoNoUPlkrXU1x5Q8NcPf0ENtVHn4Eo3y3muE81IEMNClJbfkn7 tsBJwDFtkdo2kgnZvll0kpznO1vPOnPAtpfaDUzIv2T8eYALJrWZQywWd390J95aw0UmMzul7lBg bjXy2YTReZCxUqEsyLiQAxWK/oSeUh/h3Bhhh6xL+BfdcZ7VOm2WguMXacwZci2z4nE78XdWEB7D 4MUu9U3pjgFqVLxVhKKVIkFrqVG34s2ccuZQr2aWwV7sx5vDHz4MJfVJr6V11qFsiV6+fju+PSrB fAJiPParhU7NRmbTD/V3jJ2WXds17UikIqujVLUa5sbUnBYS45wmQrZJapLYcdzoSj889br9D1IA uFg8USiCKm+/Tvw0W1TyCsHhgejnPoqnT5zuaSiXZ7DwxzcEdBEzohJbtKUVnY1Wa2c3n9xyPHaB A5zfv+xoDh4Lqb6Xn5+RmIDbjzm3I6MXXu5vErbKieZrrQlFDL0A00oBOTTdcCvmBVe5QRBmmahx m+0JPO6LDYrRlRwIX2F2K802V5ohikFCmgzxlc7sr8yaImzaUR72wtUiwfgOlNHJzKF+LlmOy5s/ IhCAyvTSu8Hf9Tqy5tNKHi26++5UolG6a0U0KyXEuTKMEuVN3kRZP3f8TSY369GVwbqcQcW93z3o 1nYzC0USZdyOov7ViugWNEdS4x70wwt93GkQNEd2gqHrKGhMK4M2tqqVCgoHRkvi4D0YzUM8c/mk yqXBPf4tZTCsuKBxbnRawwHbt0a1CWxZr7GoQ9O87f9oGiuwBbWSdyRh35/PcQ6GhGgZMKWBNcE9 aSrsUo1QJ+J4uYQZlQBXJWeqKKgtUR/WdBvPHG6QpYtzNHB6GqUoxJYC7iIG6hdijUvNUa0AuoRW lC8bD/0IKUJYROoSPSWm+wdFZGvdrncPovFHHo5P6hEbI/KO4tsvg2Ub0LsEpzS2+x+ZFXlsb7FB +e41E9BJfgVXWKiuJbOh6Wtww19gOWv9pweU/AVEqm/V5nMMy6X1GZWtLX71tH9GGEr/LmHUBAsR ABFPe2pSXX3R+w2+EHmW1YZK5OTq0M6yWBoNdcsDwBqrA/3eNTeCCR1yzbUIcQnJ89IUw/fELisn 7Loolgjl8trXf5Vm/JcWEL+ZMsm8Rqk9nX2wwMwDwPd6uSHUiyqhAJFP8UsDxekYh9iL2FQJqt9f 3r0oX96C/YyKrSpy0R/CsN9dSasfkkJiprHtLlj2gChHmMt+Ki4JOAfQSq79pJwgCik+zcy2zjhV eUtxkuHJuUDquJvVYE8cfR250H6WhfNoYQqUf8v4JqGNTm98sEcOoMEnVI10i8TrdZg9ZXm0QySP KfUqocrWvfH9tqAJH1P/yqiZuG8AXSTz9kBbTUKacrjBAtAAkJ3yPCv4b9NQ+SxGXmq5noTNSGeP ADsCV7C0wNhK6kB5lJAo+07DBgXcRV9E2IZyysQ317LboGicU6jZZa4oRnzYsFWxzCC992TJ9pj/ FZZSBSlh6cZXfrJPBI+t07D1G4M+9CmQ7xYDfAhr97wUyTvcOOu7VI12ibLY9CRstLHhRyroYIvC zVOuPMdqeAue2AXELr7CDzpHjbrlBtqUjmJ4YYzMpyEge34J9THivJLuXzJyU0xOQA/rCHmr/Uv/ VtXXWc4LJcs1DncMIPgTUcpn1vHeVFKLUaNxKcqG2UYXsmW/6HHUw4QlWoIcchE3kWPTkb0335Fp xp2CdMbNkNnijCdWF4dUcCcwL+R/ub5TsEjhTqbNWKf3te6WfHTbGQyGkuqKpCa4/RbOU3aRgLyl vtnIVeUtbfxwLPI15p3mVOKAjOFRYFQtuUrxDLX7xz4M+NRvZ9kobuBWEIrqjPURLaNMc46JT3qe K7FZXNCH+1Eqb7rSfPBBUSq0/GjPNybaVyRtJ46MYmdlUJteLLbNSUnkrWG2DVGwcgNUBSE0BV9k RtmUCOVk2fe/VkkFlygbKslthm1eEHkhyIy9Y6kRFRdQS+VbaGT2xarxvW9BQAO9UPgSmlR60gXn YLV0TfqnEIznX0rngNxkINVY9IqRcePYINtpOzA6gbIF7ESKV6e0ierC905a/34JMGUQJ8samM1F E4+s2Kxng0BCZEgHErhTq6EDHLSMGYdpKoU+N05tD06xocfCdDiZRY/u2LX+Srvgm8E1eJSXwNO3 vYDarFBkTzLMrfEDPfpBYQsOhbZd4GnZAXDvrOuik1XSo83iZwsYEcN1YUSVFO+FsbVafL8iiAqQ PHJ9M8j61mCmS1PDbvh7lxCmDkzOaeOw45GR/fmp9pPnmZzA+AFQ9HLMusYL8N95X+qGQdFWIB79 ZKRawQruzcHBW2PhZ574J0nwFvNIkd8rCxPSsmKe5zda1fp/DsbXr+YMHV6OyQ7jUubYHrtR3mMy Ypn9X9GlGSy5Vfh8b3S3ZyvpZfBtST7NkW5nU3av4UCFEHqpyYdiRnmX3+LXWx2hE61p6NmgxLju bQgppiPCB4D8lBxwg1s7qjNFVo4/ejn3HkZnkHG8oMMamnuZtMbx8xtYj1y37ol6aP1LTyIQkcv5 G3jyO5RKoj5qHrruZq6NyFDWQvpFQ9NlpLR4KE/G4IraNVBfUgR0Bul3LW5FFo0Qip5dCWttXhYW Xjm+RQnyZpZl/6fLK1MQfnf1oJtFVqTBTYZ2weZvpp+cTJgLJDkhxIzpEpfZSFH8j3VAdFlTQH/r MOBsNA975nmpskzF9TyVBjNIBaphfLSKJwpgk+xYUHc0yKw44c1IeULA4TqIUfzFyzrMly2ns+ib GkCMjbxsjOLuHlb2JNsR1w+SxTjRYn4BOGwyM+Bar8jXYriHCO10Ir5MI13GEfPmJTtMsmQ/G+qg 0Pv5j+kMSbC0/oIvXPhepX9Sf8PDGhbDJRGVv/emcuQfV8LKyFvxlvwX+TjpZhuArlaKOtE9XLuy Yj1e1tSvCXelPq9Sz1pixpPde6oF4nSJidVk6zTgLC+rbtbEF5IsZt/NW1RUg9o2fLl9C3C93vES erMO7dkI3uw1RVK2oQJg12/9ZkM50O35/FS3aNM3TDTVnQJQY/yLPMK3CgLmbVPDecucEX61F9sm EaGcgI/9c6V2sXQu5RolVIfziNYmepfXfGsa7PbPMTR5kJvjNK9ZlZWIrMU890ZnUv7c5wHHls9B ueHl7UMQdyd97x7vUClu0lWCl++nzIOoj9jPrpcIB6pb+XItMQC4NFomT1YQc6rtS6P+yw8eWui1 flyVimLomn/omGL61+nQjten7j+yWG/0hp1vZwuf31Iw4XVzf63AmUrLp6iBvXq/EQ13eoO9/RDr pEoFTvWT+bWvJauxv6aQQ8EPDraTnvpRjROLLBTMQoVRm4ggVc6tPda7fhVaHEOAaNQsyGDjDdkE oNRHbagYlOmAEnx3TbE4/97Sr1rpeMcZ/w5p8tJgx3EgSwOGHpN+bjExhhkCJ5jHdI3jrJYvWcmP b5AlhJldvL+KO+zJfs0VCtfQtMTQ3DyUdRZ/73tTbqhinO8vGK5W6BbHPPBd09kKUE6GWvIZnNR2 DrDu7y6WaX6jXZ3zfde5ifgolXm61lDoz3pQd9dvqCaY8EeG9JwOWIa9mgX5BZAyIDt8TzQp2LCP KwqfttoWw527tONR2fGsPdtk2FMJ+ypHdR1UGUv/43I+n5HvFLAQD/Dk/j17F0cReT5w7HetHcxm Dt7bSTjdGVMLeUFfDe6PElDQKo76EQbrx8N+5ARBKklGVNHCGfIXhqfo4UUy2jSlw1ZvoQKJpqZp aGhJuVmQq1OjjZMP2gdUwE4EnK8d8dJ2XUAUpUiEIPaJXqjLGztGlENO+wSjWicX5xF/Owsc+djS sxn4nKS9nmTynOfvgJVthRYFJ48P6ZpZgQfat8m1NLPZ0Pehu18c95l222TXuaYnkarXUQ1hFGKl OO55p4eZU6BQ7f9/KiQ2JJsJv5fDmkcjBL5AJ5QwO1Bosrc8+FV2YXUbwluNh5rs8QYGFS42U2qk dfuMeXi+NrJv20TLenXsL01wMg/yVbu/vMgH+gvYW+K2cFc2IDUq310E2XDwl2goj94oRysZU7fx si5xC48dm07l3CmnUfG/bLxaBNQobR5mdJ7ROWFBq3/TfJrRbKmOCbuYM3O+7ljKUkAn43c9mEm8 AT0aRop3IZG46NqSrUPHpADyuqIBxbl6Zv/we7z+ZTq7niJWNdEopPsJNTPQnceA2NQ4l7K0nMj8 Wzf/G/a4WDUORUq7FfOKrhg6o0Cy0/uvZJzFKv8/5QA/1PYT4zVxj22Fm5onu3q50zOEkm5xg5S7 q1D2WDZ/9kVssMM8/IAi5Ptd/QE+bYx/bb/gbG+oh6DpeW86AXN/63znbz/u9eREOgNoU0Lmw4E+ xrZaPD30KoRr6BheTrx54nzi86Knt8I4NxszFlUtapEz8ROKFBJoc6rN1Zu+/Ak743CDm0WT0GkZ ATYRHtd98Dkr+AiKgUrd3tbl4b44gx8SmjCE0y3ypTTUcdPgbrUL05kBjblA146snfeXQnqpASaW dwO5ASX05S/2BTXeib0LQ0zqBSs3/4hpb7DUePlfbeucX5lueEnsE04Na5etJJqSvletmVuw1IHQ Zuh5dWo8k2OWDzCnOTTx3t7+s/k/thFpRVzs6R5XDAp2an1ILO9j2nppK3cODKhHCxh1NBxSYB/r J3dRqX5PUq9eW9XsyjglaDajIMpdQcV68eEW1p3UY2t6fCv+8nYIqhDE/3EuE8fRiUSOXD1MXgtC vboIbPER54zgNAoW+b5dcbLB5kxhAXtDYSejUGf+YBpXeaOkNzT1WXvMT0PyG3keZVeKanKdYHYc I/BkH0uQ2pX+rJFxVPYceS/9jThE5Wd39Ji7xb2RBPYXPnclmUNRTldt7nXcWGmi5PvDE3B8BvH8 VsrhmDnjsGHcGFl7hqM4S+JLfmFMQGictCM6vD8SMMMj9IVkqgP+sTYbIdsj5QRL/Y0YEpOvOLWz tDJrO8nVECy9+ep5N6/PEOQ7bit2hhhaVHHjKu38Yebko9M2375owuZdfJ/XkIjDtqNyY+vZzEur VQBoH7h8EMGUDQUC5kPJQjBxPO6mMZn+Y1QGUr00bzIsmgy9QKhSAzieCaUtysO1ALd0bTOJMk9O w2OD5Ry4hr7d5bijqAejkcnlH9n/VDeNfJYmdtLmBHHjXU6jV35CAyYtpzpLvx4c01b0ORJNlAVU 5FQHvzeL0DV6Gsvdf3Ax3bwBmq+mL6RsMwwqvvGfZhYHVQE1qaFVkBFiqLjdRvevNmotH6a+VrB4 E8hvH3NUVhPiafaEL4CfyVAoP2iXnCSsIFvtfeZ5U0TxA+5PxHvpETsrGP9Cashv1W3CGCUaRZhs CHp0CLhraRoaNTUGVqh/IZDRAhKdwj3oRiWXsmMPKjJQ11Q0wTpgO1dPd+9/JUrA2vBDcQLHyvvW fWSUKSPkyBmnA0/CuFA1WHa4wxwArLXcWlkXYlAsrjBEp5mbqr1Fd11oewWpR0SUcsPXVq/UDOj4 FwgL03rfzUK5bDhvDSHT+684lKEMrxAnwG+Jc3zMkREHvO2KurBpxeYFY6YI2tUOjc1zhK0C0avX hJSUq0Z52aiSBN0yRIKg7TdabzsTmn1h0YzMxsKixKNYyQ9yZfFMSINYITZzG0HznV2Pcb6gI7Bc AEhbkRmmAZnvdajKsdK0y6q0XUaURQgyJfLhCwaV+e/p4mod7haw+MEQ1H+3723euqLyUch/+hNT l42zYGsqYnu70dS4l+6jxxlaQXbLKfQukRUNk+Eh8BEjc9CaHKX72iFy9+V8SBjX7kqboHkem1TJ QR/KQIRN0Qpw5crUf4xF6YE6dVz1U+/1gGI99S5gaaLKQ+j+ndlH4WT2D67cjhDU+Ar7qyXcOuA6 PpRNAWACIy6e64aLt1ZYbcrh7xtonlYQeG0/JyaYHlqRttLOQb9MPydh+4osuG3P7UImf5RBi922 PfSLty3H8/4lCvNfCPg5tjMmsQMMrLiK40nQ76y/cmgXF6W37UUDaUMjUOO56EfAuBePZpi3+c27 7LdDhN1dcUUVPcHSyzobJ/+eEPj0PTYD2J0/fsZkj7ZloFI0SHXZfjCXDh6K79Lrpe0Fz6QkCiDw fYIgzhXFrLJx+oRdYRsiGqPWL0aKJpTvof5RrZNCNrO8gCx5pOY51mz+pjY2z3u7sRSg5RKTBNrv mWkb8LjNinHrqDC9fKWRFwSLTu94RiXvJNXRJ/uEjOXdNNj9ep7yhgiqARSaxQ8hZh/zmfJrgxSf t1HSYBZiiGQvGGHW6SB4/mWzzSlHTU8d6KMCwD3jObh48ohrbshdmFQtSRmRuAX4t2ZM3qkfDUoj YOCe3ilQxqXbk6uTRll4xI71mnHzOdtnd8X4T69AF+ScIGlk5zcUEQhyY/TGG6h6TNlIW/oJoX5Q pz2G2msb1wfXAvFmGeuyxYEbewEF7+RFzA8qQb9j4sKwOTpvo03APziL/JHrlFkabzmJJ+Oa3ViJ NqDcAnjg9pUMzQLZq+GUImAi0rSlxnRrklU+UTJbyW85hYFAmam6JJk1sJApBqVB0fto+mv3dntf v2NjQNISU17k5cjCL7hf1VvDql0qbDf5pq6KUyqdS+fiX7EW/i87NAiue/LV70Qbw1UXLJUUomjs on0dC9F26KvM3k5F3721C8GwI17CNa5L3r9NcHPuP3OV74807HwLYjhhbGRHyVSX4ijMRn5Ms8wt iSRs1MZ0wB/PWBBnDxaX3noo9LpzG+kJTAYY8boICvP4OYMR2I3stuxDjK/OipvelH5pxt3cB0zl /oZhvON/1JVx9VBJPqedGP/EY0WXK+i7a/dpJQ0KCZCFbERTXgF5aczRR8k3awLlVSI7ScgNzFHx ZL6fECsZUnkKtHtOcFpiJegcKb3k38QdgoMIqmGScNisIsQKIfBgdEF1dMdiPjzZMrrmRnrxgkpf a5YOcdWkucTJBVSaydiUFvBL9MDOUwEqZqPsvFTRnHRtGftPiebf03elU7c0VUGpQKNtHBO2JRd9 Oocqn2bSLbAeYuwvgYZT4mxJAlFlEj3699siAmrr4Fm/lqaeYEBF1jY8zT+amexG9nNITC4TBxvb yfRzpdpR2DM2cHWke7Nip4RXtwaoeeKYBfCiMqtcpiMGz+AFS65V2ojelpqb8Kqd1bVSyZ6V6mAD 5+Y6G41ovgwf9FpPPxtDqeoT5w6daaf8+k5Qs7vxWP0mutj/vtJ5eUhZuarqFFsGdd/N17I73lbz KZIAhNmy1vyacwUxlQeWUS0mAJvYPhAm30w41pzK/CcizpjRA7thvH1boEwGws1fLd1FFLmk2Z2L C2BoA/537JRT8p30LNAjzGkDGbRvG+ei4KnZuP3eM2pLWCAWH4tOHR+Z6RxVbJt79sXmdPekh6ro RAfFRSUGSxBSpXvV9oW1vNCiwfWBlOIFh18evZt/xgyP3iZQdlB/nNNZq4qWdJvYC/P+TrbKxxFo et2+GFeM6prMhNu/xITV/mQjrw3G/Tk7dGJxCRuhd4JbPo6ax5TgvgmCEcMkyK/bont/+jBlAX9y dn+c0GK5e5aKq6uFtg+GaxdJvxLLsNHdkf8zIko6wElkYTyyv3mZauLZKIxsWsGgnzN71Mp/Lxjc 1CbPaHizwmUDluiCAoQtoWMzneRcChzgJLnooODGlGuiNkle5bF4qrRoapht54L25WqkELkLpQVg YbQNBKimGk+ImxJ2C5WwQa/znLB6ZYfK683eh/EbwaCTq2LeEMKEKABTOlYrkV1x2Vsjy0+tRDpz eB09i3hy/3yWTp0ykoos2lP6k9mA1qgkEbHKDRyd5T2zEhU/wM3iaGNVYVIEo687ogUhjHkiJXUE gNzmD+I5e+Tr1UVqom30A9XdwT24MSmMlK2L6TG81d6L6PWaVNWkCmuGbhhmfLKjb96j93EMNKQ9 UD7wW25kJuGjYoaD5/SvLMegcOMbOAz0DahS1Ep7SHWaPAibv1hyDfrEzktElDZkg+/LkNxq2Gfo +GeYWwu1rVPESyxX3gD9jUkRmoKET1lYzROcZPbaTk9pLWC5+6pEcO7uJnaFZ4T1ZoQhIWLr5T4G rTpLJVg/aAryzx6U6j7gvrMqwX0KvikcP7N2FMIST6gaE3dLQWt1faSUunWbztVpysnuYdRUXmLJ hOt4DAXFZK3vyVUJZKk0X4kCyRI5yhx+po88CgzMdVulJr0o7vnQBQO1mwWUt5GYapxfSJKlBTVS RmMia0jvQjQcmGTG5VZwAsVIrDf6R5BeGjfOv5CBMwi/soU2uZs7BiZEdPfTZXx+tpP55V0ITs0U eKTVy2MajaOOictn+FG622ELblsXC+vpleqFp5FKsVjRrokh8WFGrab4+xwcnr06JDsZyDCqezCB GQS5dio/NqtmQKzmeaRPRonpDH0ebRBXzAxZEHCTR2S2IAQThfphRqHJMssJHC7i5LJFm/JQJ5wG HQho8Hb+kNtagpkaN9hie2ZJ5eZIg6jzSFRZsQbbfdKGpn3MTA9QsK9cE/AE4zsquAyEMvtG+PwV ju2AZJeZm76vQJ4TeRe3EwFiXIPxI72peFgX/KO/dDzW74nA10ave2Jp1NYOCqKlnPCE3u4QmNaH OpnhTDyApv/eML/N5t3b0r5B8ScLeineM3NOl2rWNW9+Zs+FU8VdrL/3oToQCqgl5RcQAns4hblN ZF9UC7XrjdeLwSTKGbFnc20s8xvIuNd7esC6OCztglWB+/6NxgLep9NHL0T0kgr2GKF5oM2WZcvO uLyFL+Bi7DVg6qffCbGu00Eg1cSHmL8N+oj5YRfO1Z34XMUeJnmdMR5G1SWDeUMYejueXg7WLcDp fZfJ0qVCq96sF07C5HyKGK1vCy9qLKG9g/XENUJ7afQ7FXHgMX0ALpCuWEb7nFUtgQNgsjV6fd3H 988kYXBEEnqWhjvMA4XpxMGvXG2qAGKyp5/rONDk6nL6ftWekbYk2b6jajIsYOlKyW2SY6eiETYb zwm/kU3YnTktT0AqaET6YRmKP+7usX8vMgn545qqnFx2JFO8vZstK+dBlmYjEYw+58bsS632BS7Z V+dHWJPwrUaLT0leZP0pdPda7ErzFaEPWkyN4B+cbnveyR7HbRnwm9Pvxe4KLT1tv5pwdptzwzfT JXA/oj3ZGJGjvtbpkpD9600qQYCKqhwWKaNAqK5dko8WNcVY5oKuuaWEiqYGxUqsVFkXvdtILQZd guWIxWINmMslPxtBrfAkyEuMEeoy9m6i8RwKKxGXWOAl+ueItW0++KypicZ8N1T0iIokuLtCIK0M RFNRIcU5ODroYj3fHOloznTPDksbcvpU7hBcKI/ljmIZH5raRYsiHjhubjgzL9hu9rW++c347PuP Eb+oAGfIULqiTq3pgwFPa7kutPkMo6bMyrJIhkci9ZSJ/ABn82O5wj1dv97CRtycV3CjMRweSfwp xtqSNlv4NbYSPEyKg/nD4iF9PQcrPlGQdOkkS0CGwCKhklMObFoAOcOqDlHSpcrvxq8oV+oZHfo7 +6Gg7eq/QYeGSBKzkC9LTfo6yIdBLffkp7b1IO0eu37YBSeJn6D+REd5E2eKZ32fhCLT3+IJen2z didvY9MRnhQPfGxV/RGwz1W5q+XMdZiGN0toA9vD+aLoDYb0fDKBtgWXr0JPgoZ2tDkFyhvrtt2Z rW7rM8cfd+NLkOGDRmsoysa7/YgYPUu2cBOfK6msh1oEOufcST7uOr9zzw7hLvBFEV3dMY96Dd0w WPK6MWl10YH67O4wDHruKsAK0w1OlHqDRBCfMIvg57r/Wd7Y/jB52Y0kfGiX4GEgnZah8MuYBnFd ubKM+E1On0dsvV5EZkhc9UEnGZLg9r6fQ6Mow+Ie+e0ZkT6QUevn0B1P8V8VloF9TxB6BIImNZxJ kujSRi1ku+j8/oVpZ1m1TAPWiXSyTdAyH+YdGnkjhLZvrKQZrBL4Z1197COualvxgSoZBwYn2WbT ms+TscWiRoTNkaP8Jl7vSO1Zebnc7LU2TQwPlka0tRcy2foh8CtraRE6wX6A/tqogWQpb+btQtQy i3bVZdTv1bF8StGdEQtU8g6iG/ZtztTcVdfqFV/KJNRCe5jPg8aAvRXVfrsm9RFGK6BFp5Og/66P l9xkTzPm3+4+vQiUfkRQ72QQd69wetgwr0moVryb7/dmcogP5p/+TXViSzd0CftQ627MjJsxrS6l n7de7579PvSBNfAcK40m+b0NIsAIskjclt3cmbT44wQTs6d4d3pVdLRmINoqnIpzfc56Z6236J7H aHpBUqi8R9rlP1FzTBmkboxu0Cf05PTYmfjl1mQw9WeDob9dqiyH/9tMXvEJ1HzprTm0FOnAvIWP G8Xbi4NFNqPQkSfZVh4/NX5+dISX2IMCXjhvImCrGlyD+BOe91O1s+eHNfbBCNiaqNDzc7jRJ1Kt 2fIUlCayH6E/msVeknAuHc10pft++HUyudpd3vlUDDlFX+tmeUHGwF2LXXKOakU9oFboB2kgyMdq c+Duch5pcajpCehi3OujVkEXeJ0W2/2/cpV8BrcfC1SmV5dsGm21RDo90Y4rIxv61UIF9vw7BReg 6aEnf6KVVd+K8oPU4SFaC1SE9totav3VqBbCWqka8fw/Jh4SNAshJBN0RnEYTDDmblbkz0zA2KeZ Zf8HVM+dFxWVgZmV/qnHmlHfxzYLZMXlylR88rDXmRBpqyfJV19hzx88PG+BFSxUW8e1a9uRQmSH vSoTRFF7FKodhPIdm9lzOX85yZaBlU6ITQnhnzCqGCIQFrKpcyx9ck5S/EKXAX/XfoZQJnDLTAao z45JiKpZoXv5uDG6E/VP6OzZMD8rwss7wwJc0QAgYCIkA0yjh4SmfzE3F1JC6qNpnbHMFnXRLRVZ VaKZmD0BuZab4XTTlaiI416MiPMLDsq18FScwINFOp24r0qCIZ64FHncaIOgve2xtSiQOaes7LGk IL7ho2H/E40NxPWKjmtL7YJ/Tf2XBSLMUw71uKCMnRLkX+gYWs+xys0tE7jW6rvVe/HDDwzvo0bC AKrcl0nlujnI0uxLnX8rR1bJkk2C7rNt1ytSNFNw9d+AInx/doUsbez0KV+QGG57+Sae99UAGnz5 fk7RGNRFts/qkWpOy2Vkl/+ikkeOt5i/n5TWc/WpTEhup6UDiuceNYIXmA8y8KfCYAbH7/l7SeO6 AeyI8KYfxpQP5WXxFER8Q50EOvgcjV/zz601SP7J5EBZeEDyrkZNJBE9iABbn6a2bYPlnJH6CVM4 3826KrSF90z2QGrk77xEXbIrU0bCAZW1R26zvJTqAjMzRApod7waAybDf8OdOrt/6NG8sVBUCgA3 2MHP9EXNR7jV+zMlZyii9FzRbGrgfa1Qdz5acRU1V7cTdoYJqe9JaRpyOICMerImY57Uga9ez44n DL2bwB6G1kg3X9faLr1+dtrK//nNQxXOoCNEgCY+mpLn3Kns1jtFPCkQycxy7q7aa3G3ioG2Gw26 MhazwgQfw0bgqscc1ChTu4ZhgTO28qSuygBfDf4qVM6mLcgOA2EvSML1A1C9xqQDph8HkU+qSN5X ASfXdwC6fXzG5NWvkZhVtS37FqaGgypNwqzwtLeqXtAai5I/ZzUWS1Jxjcl4jCaCFVbQ4vLekTfg T4Sg6O7ip/x+uTtjp7XAuRyl3qcq9a0t87mQpRlRhowoAeWFPHjnJLYGCnWc50g/kCzEVMUbPjQh nb919dqRx0XO0+wYMqpWYtky+qryd1af+6SlIUL5BwzhOP+WfHKhHrAjr/CbiOWjs0SZRpCZvqQn cAGHBNY4MsOE3z8OwAWQpKbiuXcL63ZUhb2tpEHjH/xh5A+D95nkgBI+W4phT5zkH/tUFTo8vAH0 Yr3V9rLcQibaq4ColEWDvwOmAOPUiAGVwn6buwxFYuVMNJ1pjxNEfDThkzXh+4DLsqIPBkt7JhRj 4Kp0Gua+YEerg3x4Xu+A84uF/sK+Mb/GcDCMdWY5GchNlFlBJ4/N1jvLaK+EubtoSOx/Ok8F0X+U P+EgWIV/tPp/fpaAgR1ItFKvENDifPuigmzQom69K0D8Srk9Dhi4lVwImBwxZZ621wRlDTaoKZZR nwLXvJwy/sn45jP6AQOInVW0W5T8ichsDimQVdq47rFK3xhLLyBfpOFpmnNZ9YsQqHMLWhoGF7zw 7D8TqbYpL9/Qo6t2c00NhshHO7o2JQisjy+cyMVhGujLWv6inqiayJ/YQhhD+2mc/D7QaCdMByO0 FlnVTzuRLIMoAhZ7fNAL50HJTu/0diejZdN0JPd1LZzCB1Lrllc/VoFxmGwMPpCS/1c0lLgMKrCM IN2SU6lcg+KS7fpKSDhVJgnkVXJwOiaeIS3JVbSpAoFcKqRRnUHNIcjB7rtMupMRdf6FsF/X+RO3 VAzIjHj8ierPqNWgODbi4ROL15pcS4oHkvSdWwpE0fbHuBKot7tfe2BUTjL5vjbGxQsTmikuig2h /3ucKsytlldzqAP46KkHKtFagJR3PAdid7528wl1GHc9cW+spFd01hwRoHnIdIAfxDQE1RsHn1TF xLgA7L5/i3T4YVQ2sWrJuAAwJj9A+w7QBrll62+a1QLseLoXcDhlbIleQ6f9YT6/nMHAkKWAuVgO eT3R1MUqHj3mtIfesVYjMfgWv0KgDfEld3xdTa7K0HN2fctqn3ClqFnmyLz9/ioufl9UZvl9wYfW h9VAm7wMybTgg3xRCHLwz1Aef+Vcoq65XCAd7dmHTJVPRW4awlrG34c7NE7O2QrMo1fK8tM0PyOc Ks/YvRNUqhsiEf1AEiCTLgS6fyY1m04E7k2HxlJoUAgAov8EMR53gGWWglXlwcwnpt6oIbFAG/Am ZitNcKBsHQBESX4ai9ZuAl1gxIRZpjDs4PBr+7ZyriAfASIUMTfL0us6cxJKbbRk1WimS92IxLFE qmTD4vZA2PF7k1ihJbF0wkWR7GSX+MY6sp52foHzbatbVyF+y5f431jWiO/ZW/MAiiX1dkvHISov c7awrhIuyIJQygBxA3Zn4ZLz/5JDvhZfODGbJCCzvWM5MB4hz+UoP/Kmn12AKt5nFy3HJPmtlm/c 0iMEf0g26gQJgW+PlgeA1tBnlLMokzR5e2YtNCG9FlLCYVcUuO/P+YBYpUwQD3NCagrG0zPgIWJj YrcI1auJfp5kK7HblncbtkLPtsMiepuVaFRA9yOQon5IbxTSurRg68DEz8xjp7G5p8JJAFvgBPXR IrGZ4sNv6FEoXWx/2UpkJkX9GL7dci6d5sA4orugFJqMg9QXpEg+My+CBQsS3wL21TpxiF3e6djq LMdEGACRg17hUPamIaLWZLO9GAQiQpfbZpECXeO7ucf+po/b/U5KtAxtbz+itwo77p7neU3BcDMw hrkFeoo08rA4qFInLBtvoctfxo5eRv9Icqo7mE+UeuuNj+rw7f1bPgmcR9ZojYDh4EiUWtRQYJoO Zz0iZxaQhDomffL0kzzHzOCsLM4sZreRFGbbjfHd/6EUjbOMU/6zOzRQEzsOQ6B3ipONVfzGv7L3 VzdL07McKo9qCjQe3HNCqDdfs17GWrjzuNnNuVDgk7XuB3OKncZeIb6U6u7xWdvWy0g6xE9wnEp9 kWzVArwT89jFqqLvB14v6cZvq1KTZYTSjfOuv/t1WmeaYoOpl5F6xUkxGVw1x9iz39bpVNsHtPRf iqZJqaiYjGTWpuj1tGvVk3qSh4d1f5oPFV/dzglmyA/QbXS387la/lUYXROyfeo7Vu4h28kvUgKf 688tRgMRCU3TkwTkdNO0cSGb5lny1IL4tZODyn342aJvm01c6u0ckPFClVyxLBBx37TjOGtxw1gq vjl82yMHo19GhAzVZe+18jQnFc6CPGtfmDRkMrPteu8wTMVRgAbNNpcLI9zhkYEhyfYROoz5loA1 QxF8fHKO5thd1a0wzruIetWW4bobxBEmrx7avhQSSTbEO3oN+EdAFQaCNNYPS9ytGoVb03lzXDtQ 0HA4XXZuzn5ahxkSA8QG9GgoimvJsjoZkmh5PngdEwvGFYXkOdkDmDRABS4Ve5Tko1rnJg6K3tsE MeaitKFeGmgei9R81zF6UJCIi414gy5in3sFsi8crQeqvMpP6KDiKrK9okHDSK61OHmSV+kAjJ1k g33T5VSJDYCQ9BuNt7iGwjWc6OlA6zXZxWpJQe962QmkKIYNv1F0XXaKdzjzJcB8JChKE7sNH7iM WYi044ulId8tx20FMG7LJkyxlPRzrLY7fYssITsT5c/FThtNdonlgaVxxilptD69y38NGi6zNhtM rEiJzC9waImH+mqgVewnSdvPl6TD8YthuhcScv/d+p/i6c85pU6wNZbLNOMJUo+mFbZ+pHplmXDM wHkc9+vR7DS2oQ+UKx5Diwhbog8CeyL0IBG2CVynDrXZj/9PoMWk3Ja/5EbY0CfrbdenxKdTUkAg 0FDU/A/GMCA24Y6Kt2gwe6goqwQs4OfvAXLparjFWUb+MaOTRyncCjo9biwAhJQVkACz7Lhda6Mn njJksvVN39/ZAUaSEMvoP8KPpEB6Lg7c9RI3HPnfRbDXCK6sYwvLMLxMNqqbFUJPhEq+uevAOc+M fUNtxG/E403oczyWj7Ifaz52UCmVi7UFSM7SbdYLH2mpxQE/l/sPEvzl/g+/9rZHa41ASIV9sLYk OtAf65zUuHGADoiP3ThqEnKVkXkrXIP4flZRMTb/pMMiDvGSkvV8+NGseahlJglnqphRk2SUOUJJ qzEEHQhwpFl3be8UdXAQlCpjlY6rrlIogw2AnbtsRth3roONH6g2wkKmJgzszwKN9t2WP52d5LEm 48/BtGBozthujQezOsbOuIOSXuhWVGylvtrH3owkhSpY9Ek+kxkNOHMJXNkUrHu0uRagvoa80sUL rVPrVy0tA2NRS1qLs4hemep9+ytpeHamjRcFKWM9FLNQrxha+2gnfqibd78WwLvBkjUM3wKWJZTy U1TFYmgdpk50B3wNJbvE16FIMLpEteEgOjWjMnSnh5REM14u0w9ikunqdc+vUT33kKipmKxGBiJ/ Q1mtoB+CExxUCuihCTQGlJSZWa6HY60nrWR6P8yYW/IuXHwnGBvA/7QRZ6jZf1834iPJzRNwwnQ8 G5P9XWZ5YD+8g8Aq1vlagAcUVSobuaVMoUmPzS9Zl5LL6hC+OkLDL+JvRB9n6DDjOhq5MsGoo96b /N67fPhM7K3NGrMb4IJ9iRdxDmOztlKakDu+ugXqwpUethLRqFYAeJPWWrKdy5pv2NY6DWiCGRHM qLD1z7NrewCn2k7acNwZ0hZG3cS+p9RMEkLORQ/lsGCw7xX4Ywn/MmHF60FpInCn7Z7gFRZ9BStZ QBPoJpJjeQmB2awD0vb+qn0VFe1vmItitubigOpmppuD1incTbldPoABeb4ovFYJ03Cjg4dsauVM 3lxuTX2wPmq8FM2QOrM8NHavzSSDnVWTlkmUL8HvRzWMF5UqkEMTx/LrEUZiuqQJe/p4ZQnkaZmy YJZAiJvpmyOJaQA3xMAtlhyCJtSp3+QKr7VTXJNES0v/+tqRRwxW6SUwSUjb4M6KP8ZizLaadZzd amhww89PytxLOwKptLIYAsOOGoliQ4d7vZssN2F/IeWrWweSINS1VK37f+6gT5hD9VYINrlHlvJY 10suqScD5dCHDoHj++zQawrwZ8HhMfHMa80gYBgOx3z39oG6KLGubV9DtVm95QLHtlqx9rHg+e5X RdlsRE0AhJPxC7L/0Y/F8jdDCISTLajIeFNx9cpoplDNKlaaYrbGhl5yMnNjmZ+JRW3rIHc2ZpkE Jwo3KjgipyNeJmTh+rANw9j9t4aEFlaUxF9IOYch5A5ajRqE72lTgMNNvrh3d8vQmD64BA5eVP/z nf9YjQkFQShQMrWUjeyt79A8MKmkXIEXEw78hpAbD1fQXNFU1VXb1+9dqOfq6GN8rOZFvFFrHI4M qapxLLXLMtFrliWm69nl7lsrRN1qkcwRFXCQ2l83eMWIuUP0xDADIczpQGBanoaXGmzZKf/pj5Dw 0CVNvNFU7JVqlZW+P/ASDeMpX/FMOqUmIaMUCCf+guIziUvK3/DGvaR797+Op77i94OczCVqru7W kD0PVfFMo/9bJVW0iKC9iUyhOeDCSqV3zaUzXZNkIekHUUQlkAYuKHD9GFq550DXpfbH/Jt/BeEj wsJqg6t6b7MzvJzAfgevtyCIn8XASB22HMUgljQh/mH6iSrSWQnDWA5Yffxd/ix40GjiaWeuAywY EeDtfosj1bADiGwoot7M8TPFIEhLypeJlGxd8p3X4OHmnd2vPhZ2aQ1YWGGzJ/3DC6USP8hAyjrb g1FIWX32vrrxe7hDEsUoJSX1nzRiMN1WaHWDA8qU09Bj/oHEbGXsmamFfkCcCybebbB1U81Zr/sW mDMj9rRAUAJfHBjdRd6E5+gKH15MIQlDppUo5oZiVgHXCH2U+SLL36iRNNchhkulGu7vy66IOKI7 Fe+O7EMvnvGMEbePTdEr986XMS5V1Gj9qE3MV8qfletzT8hrZyf5+9XZ+NaNFQsuPbR4XbDj4Jqu MJ2mcz26QflfNqMcAVxzNTNYF6VujpQyLVqmaIRbcAUHlZJdDohXry1TBb3UvqU2fpuZ3hTKvbug FkfzUQSv8M6Ky80BBtJBBvjFssM3CvF040zHFZn705GZ9G32W0HMe5Xzugwd3Yb5LWSYrixKMFeH vVQHi0IGo5nORIRGJ58EKWQ9qFySCzlMb9Wjqqslg5QdDO29apz19mbGnFu+yqUPm21KN5hX8xoj tbVR9eT9ZIgQjxPZ/K2iZ0P8y4SJnAbsn9cmtCQctSuN3AnO+oecRLv/he22FjxK7E5S6XAuyh5h 0y+x2w4mKBkxFK2sGsiBRgs3ECuhk6qxiL6w421DFn00AlJDLDCTzqZwhO6emOkg47ZstAUXIdQK gcU/oFUGCKzWQF9ZwNGfV3GpHb8w0M4PuSsQS213r9GV/TSSQbMqCGDyI/icaXXZrdd+aC8ELasy CieGvdKQQKy/fs0w8eZXBM8W5BVENFpo8425jntGibTgHbkvJ5iK/pzsKJ1oNXyaNbYiWsg2+hE3 qKVTwZpnpdWD2FA7cDCJvq85K/8d6pQGsHezRItHchtQon0RSIuTEgP1CeFzQRGMh84asu95SMqp ntUvB4r/yxxIdiJJ8IiupL6OlIvmfWjNPGSU2QcrpvMYosDupvQoj054QVcriw/XcgodX+CXNt/U JPbbjzdcqbZr3K6TKkk8e+l6pk/KU5omAixDlRNVBTynAt6zgYrPi0S45bgpgpi7wFYDNZoiebSE P0JtBsQD/h7uLeIGiXwgnBA5D1UrJGoXf5n7FqvurjxEEJYjzk6+i8CQ1cq9IqlLi4ltWJvjF0Ot 6lNS1XNpubzJnYJW5hZ8OtA4f9Wm5xUhCLvHSdHwOC3TH5xOoYhpYeYl5AAqA2MjqJWTUTw09ljz O11ydRcKqBWmV0s+bfGXyydYA8AYbxosWade4ko22ceznlnDuUuomxUtPhER+O/IVZbszWb+F3N2 VxpZmOXBfKPlgaggsIU0AXCMrqurAKaxaMbktnLoIgjlStQGqPumbcQdtnCX7iWx7rQyVkkXOG2B 2tUgEXEZT25w+xHky2nYKbCUpSyfoNYYOUeaFKgmsDXIXgDy1I4Wg5FsgcOqB5AJ0JXBPwpEHQZ4 Z4JZrFKDAs7O/ck6smeWZtLckFa8ai3BPcOowWLEn+P6nKryVeUNwj9x21Fzb1mgphj0RBkX/a1f toAAY1JT2ohWfzXBVeLZkYBybalLeK/jVOF8lnJiGJlub6SaTxXNGlLXFxnHOJ1jLyJi0DHQLdxS ZqSPwFuvRjyesJ0PvkLqsnkpO8Qu8Bv9pPlXJsBR0rW9CKF3JnErqOpdZh0gLzoZ7uGwA5J1vbS8 4DMMhhhQAuHkj4E4NQt437gpDj0ZMh0zBdMdDhI3KTeh1xaeqOQJiicp5TKEoYwL3ycFpVkLfc6a y/2iuFSt6gHPDaxowHiGmJlPcjr8jNl2W7sd8pv3xiuTJwHDHVft70gFTT2HVDT2ECRDoI6WaLPL /IqJZatOw2697JzlqOL0DBK5R6z/y6MXOu2apMyHpQ0z+HTd/00y+9F2PwF3hW4/FlAcFV8NWpL+ I9H2gwbrAyAehvP6+z14vDsbkngc0uraMhzZzttXFi1rrCxxD9vNvKDxHh0KR/ANgIfQZGNqghHG xcIjr+ovf8f3nrhAKse+LDPTH5qnTi92raRAK484DtImTluGBH1Oyn4Qz7S6DW6A8NwtE4K9tW27 CxHXaEa7mpTtTCm0fP3qXhFIhSTXg71+L96KH3jh4uLGhAu2ZjL0ez0eSyC1whpRr2nnoqcBTev2 5pmibWmXkO3kK4ksCgOWZ4oDJisYoVQJmOh3SIsk3KzFZSHOEPx94gjuH+MbuZ+lOGugJxzZEsZE c7nX98A1clW0dOohqZt10+6oJTiOU6b9TuI85MbmR19Hslcfr/nL5F7dVUw4DvNTV2SoGnFpT/It bI7whChTIWPXMzJsOi8AcFZUhtpghctt6RvCOyCVX5lmU4fPVTIn6OIoNaq/G9jH2ysg+lWXcWr2 Q909n9SyK/N6bkp5MUcEyQB9daSKW3yoMrpqg09jBkhXJjRSZK8nJSR5gJiScCPAqZzvWEx33l2R Y7za5k9OFpywtwSc4uiT00+xLe383MxxGBTZ3JUOqiFgf0QDPXtyp+3pjbFyPckd8x3sMbXlE2hL /tU2J41PZplWtbxl/Ctu69sQyPg85HKnnKpIMFdruSrIxv5zyYChQwMicq38t1bExhN2CVG2BOET BHXpAN0fXb+/r7ui3SHNtZFtNC2dSH9D0hYC5LbpAe6MRQLhhshqu6zBYvmw9sSI0jbgIzrHhg6t LM6sI2/T83+oON8zaZSc+PwPfer2eZlLyK/1+2GHb6SJp8bL2f339JyDt8pNCVXA/HUZGhXS2x6o dcMGKu7LfnT9BejrfAszg4uWWQaNz0TjKdfdZlJuvCublANi0ll86M+IoAe8Oxy4YEOp0bPrqUs3 YZoWxo9d7943CDskUh7Nnw4k6hHPi5gIgtJZzdQP/SK9s9ODgmhDKLFghxzbKnCJYYW+Wru2SDqc kQ5iCDH9nzFzepAliYrrJ6Yr7DuDEQabJ4RkUJqoombSpKcsxKbj08IvcoSBxHYiehZylPQHDJyx GOki5iCkJGiu1B2jtZuh04EJYBPUAyfewQeCuXMUNfKOZvq7HzgOLdiafWHGs7M+Vpuk765vBhO2 Nz4lFizXYPSdeTfTgS+JJUUP1E8j3zejWS6ZtqtVufIrGYvFoxi3DXkBtv9wySbo9l8srgNA7j8l BHd1XdXXR4Xyk5thD1wZSaL18DNHgApMKdFpe3xeG3P+8I2CLdLkWPrvRpqaW/IXXuwdOfOPqAiZ Psz89rheCB9QC7C9WolXvopg/cR1Ze0CPny6xd1YZ6w5kisVjDO9caIuOEH4v2zrdEcgDzUjM1Ns cRLyGm+UhEtdve9PMGYMRgOok/rw3yH4wFAEqHSOUFaI4yfOegMBSOMi4qH/NqZTkHMc5gARVuTc Ml0R4q97spRM8VYG2gN2hcZkIM7Hn3RVWpw+IxkqFQSIGcYcpUHc9lIHXuhADa4hrOCSq1vtI+Lr yhdBSEROBLJrQukSVR9V5WS1hgG21jHKwbUS4UWKOpa01ngcMboCVLM1A38Q/MrIhzpQn33MCX9R D5Q+e0fI3TMCI+bGaJTWmYzLHafzLxXQaggL9VypzFbwhwdHiTG8BqerCStZQx5crXW2QR/ac9FK LHfWuHN8+vXRAAXl0Pl1aIZZxebahZetKLYfzjVM0UNtMPhf4aqaD+WwbtBmy+8DYOzeZfffewH/ 0S8GhR+k4AvSIMH+kNjpQfybcMUH8lJPitHWIEAtxH1a4gTB53qfqNP+rgSlmce1SPKuF3TDEvBO GhU3YGiv4mc7VFOMVZjhUPz0cz+isFcOenVx8vnjqWilFsYEtqunZnI0aEGEQN1ZcjaZMA5ULVRA CnDwjOy9BCxmaupN3h6MwQQTu//MNCv6Egs/eONEPmHSqNKRQrYt1U9spxWgjcj4GtdXZhgPtOZ+ RrnyCwy5qUoF22EBYgo+g2xAM7NFPavnA7iVhyi6o2F0EuiDqFYYvkk/qGmz+SNkCPoYtpTUUEeA hSwdJfdgqy8IYA8MM/PNS30sldD7tzm0Nv+Q/Rp4PGmijatNn+3Udpjt5wGSjgiNRyjeRmh+RIcf tAAn5NKX/q1TDTRntcxhhy/RZ1MJQiUjypmr4Xrn0HqGUR7jL7tZchg2HJLuhbdK2TTOeUyh1B15 3Ph+A5xbkx+7vX3pHDacmlMWDIGODXYtWRm00Ifr6ubwv0vu2HtD716/GYHXqvzKzmu33bqZk26k UWBOhlpli6bMValgqvFJvW0E/Kn5oGEhJnEQO22o1DyXgFiD5m6KhZP3EJ/h0+uscQvSP/I7zzFu 0TviDCZiNBXxTU+CD8Vp3iyuPYZf0EwiPvkc1860PcoELUWfMtXLlL//e6B1WLQRImlI5IqINoq/ BURNl4rd1BM5X0whVCDxYwDhr4ssWqZVBCTxh2DGAp0JPYPuXk0nxg31X9ltVizgcm3aThxW0J2k 5iLtU7Os8XCYABJUGaHU0GzAuuFIbf5lS0uNRbUg/S7CI+3u2pm2i2NZN10NVdarsJ5zxPgpsyu2 5Ag+CD6yPBZMXWYCOW0uESpwctwemaNwN9/6KIvjFwRwyZIV1qr8R/spZKJaRviNuAZdJJXhynvZ 5IFlbHHaCCJX5uJXBYtNzebQ6irgAQt0EJNGbkQIZp++HrZQ2QXlNEahISwsQLXqA4Bx4O8W2dTX c6eLbR1nNnI1fKP9HhiCCle+XcVoQxd4/84v4SRXeGJ2rF0bSQ9R7Z3Gd6ALUq69h91n/0j/WRhR xGxW1pKg8GDZSGo= `protect end_protected	bsd-2-clause	3bc8a28404fa76f3c6bd5c0143b881a9	0.945369	1.850658	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/case/rule_018_test_input.fixed_lower.vhd	5	589	architecture ARCH of ENTITY is begin PROC_1 : process (a, b, c) is begin case boolean_1 is when STATE_1 => a <= b; b <= c; c <= d; end case; end process PROC_1; PROC_2 : process (a, b, c) is begin case boolean_1 is when STATE_1=> a <= b; b <= c; c <= d; end case; end process PROC_2; PROC_3 : process (a, b, c) is begin case boolean_1 is when STATE_1=> a <= b; b <= c; c <= d; end case; end process PROC_3; end architecture ARCH;	gpl-3.0	5b433484b6d9a8701c28658472894623	0.4618	3.308989	false	false	false	false
cwilkens/ecen4024-microphone-array	microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/cic_compiler_v4_0_viv_comp.vhd	1	11,904	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Z84vKbp3QwH6lKW+3V3OSSO5FD4zz8y0EqVaeZDjU+UBq3V7ktjxQjRP1cxvCJPWGV0MOHb3Jy+L BxCu1X3nwA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block E6lvFfL82aiG+DYyiUODR7/OvOZcSTnHbCmkxWqEKJE6eNZGxQ4HerEOlrasLpNDqKfvbbJ/ZaHy Ao5sFLbF3sMAbrzb2i/u6yj7FZCsiRw9rad7LAMHw77L/0qfaiN6mLNTGml5KMHZ3+GOQDVyRg5E s/BgpSviUSG/H+tF3cU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qzxtR1NGFsXt01AFjrWirtwQO0+2TpbvVBi2mglgH/PYzLR0deBprPoclDlQkPTVmwxtSDwlB1sB mhiQb75wcU5JGZbAmYDSu1AGtxTS1blja6HL0NqBicN4sdwsIY2NIQkDZm6XaQw7Z39ppWnWfh/G RcPMnjRRR3dKbuIFwPZt9Q39Jscet0YHPyLwzel+Y9DptvednrH2YqV1yeEs6IvdgW6ZDN08OrRl 6ShcIjc2ONLNE134F4OR2iZ9N79/rR950eXEIc1nk4kA/RrvAnm7y+9JhZjAABYF5zPx5+MzL33U m2lGGX5FYwBok4Z7JhRzPb7NlXoSLeQvPsVbHw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jLBBuI+29JyW7WPnGUEhExWCvDxR069cCqeQhmUvzzAq17K4sQN5CaZsLSNz90P43frw4EOUEkfK oeUDdYQMoJ4/oIhBU8NC4h8yB2UpB5+EucFlPo14ZqMfPMs3dkVJ11i2NgXTm34Oepn8qQyHZyG1 kxBhn60pCvxeyn5cGO0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block d5h5mKTIkW8Gy6BCJRqEbhRsdezlBIM3ZTR9MOAj3ovBxBWzkq76pvQVO5FpTvtuRmqe4Pvnmu9O AskFM/I/EWiC5LcEcL6/PlnmydaNUVHAVrGlWTZ5h6JPN2C3qWfsxlmCKVGUjgexwZpOwluOAphd LAxL/48MwWTtGpRADed6w4gT0DHhANwhEwP6SYc9+KwztZD18Olh4n+alFO0a7zYSN60YO5SnMS6 6UZjwGTtqXLldqQeoYo3+NZkBkzX7pCDLjFTJa72VNyShZ6Llcoe8X6cEJ+uSSzPy8e/wdRYkR4v HnjnA4NpMClrVb47dkR9hAdZ+gjf/OtVrZo42g== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7072) `protect data_block 9ZNnLnu5UeM0Tx6PFkDSJwlhYzqGwReXAR6qc/GfYCfrfu5hZyeianCtFJjQTDbv7ByVLXoj/EFk 27lzuRHdn6hIoDeJ3P9VjLoKJKfTBVoB3aqAuj6tNyrC0kjf+ufOtCKccbvq3gnpB24It5P9M4R0 TzoRv4ZTpnDn3j/EMeP5C140rfCU1pGr95fsxEo4SqJr0Ag4/lY985yhIy7jNWl9rnlXXB441zyr t854BiZr50VGFEFvl1snoDyu+Pz54IhfqTQgTNi8k7FIo7rxi1VHRVIk50gz77wx3XlIuISj02P4 lRP5B6jXns2wj+HmUOo2GFCrUZv3WBUfOTsIOStKz8xLjKli3VWyQooDHGA1AJ4CoY7N6hGIE0Wg l6HpvXPSWAo0DwDXEONhmoZKWbgcylXwP1VLDr+WR4MQWxEOFJa43hPzFLrVlKijAr70+gkgLYS/ 6dQtAHHdG1DWLsnahC3Arskig+ZoYSWzvlGRnUwcnCga4B2TWc1MDyz9HeNYNe/BxzKc6F5Crqn9 hV+8xAK2VVo98HLjTmKAHyRH7bORrbaqpv3J5yY1g4zx4JjAYXfy0nd3/RMM1to957HuTzFCz2VX H9MUA9wzwqtbcKQmF+OraollFGEwLtHm3Fye+bNqiu4MGUTKkzFKtAJ0AWpgO7x5XfmZtjzMQD5S E4q5meM7Og/2xUJjh2hvI5fW6vZWbYKYP5O2rqgXAQVh6fNcoZIBuKiLEQ/+aqJoqjxHmuflbOrB 8lZQfPYGN3rSbiAEw6hueaf8udgbxjd7e8Opu1pCW1gRhH6XKdA3r8E/RUBjqKpW9tqDvXBomus7 5uanQvujcp+TEoLV9N2376FrzA8YmA9+L//QM4UBvMWEqfG7Gke8hUnxQbJG65gTXTOZw7B02QPY 4cadsbs5XYJo3V2mPl5Ueb7bgx7UIobzMWAm5QIuKg7Qv24D5ArNRTjlIdriX4TejIkDsDvf+asc QnyL+vkDYDNVh8i/AyxaJzEQ1PrRHK5OIo1rvZJ1oF5zhTs+dpxu5+auOs26r07SwvO/k5yk6V6e ZKORiZzesHd5DXro2aqV9qKgE88WbrUDl8h6BJbt0elKQPIbcXRZVLisipMUclNVf0qLDdiiT/ab JJW2NzuvAJ+NW8EEvdFZtMyvlefk+mQ6y/AUnrI08vGOinMIBWgIHC0gUIjQM11cmN1JFOXE4pEn 6j5S4ys3ShDNModqeU1u/4qhJgjeGjHrSC8ZUSDqNWktoRs8OAb1zX/6AKHS0g7q0ahhpmAOaPFb cxY9Ar1dTifhjyJm4jhd0LWTgfzSwLzaAtK+Q+l0T+2NmZ34zAoPO3Qe4YE0/WpkHqvCVbYUI4Es GEjlbpvlNhJZm9U6PC//zVNU5f3ZbUuVaZ9cC8ZjXocGc1yyef24tcJxtYurKrBmL0jLqcLex72Y ZNw1C7DAm6O8z4z6SLKvGIMD0kOxJnLaeKYM9e35OADDIGxAALmZixbFKJcEvZkqyDZ+QhUBg6f5 Yabb+bmBFy8s2NgVxprZyirRRWXsPkH2RxipsIpRk1ndGoy5WGy4LMgEM3FvoYCdf1YxnRElgEqj 73G0/Q9KOYt/laTsgqwdyO3AbTKvFB8l9arAaJwPHWYuzUH4IjFbzMC9gPryUShQMCOUFSZPRR53 DMbpuCvd6MvIsrsGnFmF2B4rls6kds80iETr0pMAh1uzRWNBRDt1FswpN9xIRbEXj7EVnTou+ssa iW/2V7pF7JG+be1arlwgtIVicd/vAZmNipBwec7jUheUfuK50B5U6sV7tdkU/eUkqWRcS0hEBVFt UNtGXNo7f0r3lYTyFcgsyjtmX4GS6KT77ZzkVGX0m15+dLfUEObMxdd/6WAAq/ZNksKcQciNxgXQ umDOUEkURAk652dcLmnOj+/BXaflb0w07p+HoM+ld1Mw3Xshk42M4QyRWrjOTUuvq5rhPlXMwpiF Y2XWVZ6UTdQMkO18REav1q0/r9sspdMEGyPXfninL75kU01rxiVbCw7xmJdl4+Skhx14P8WKspYC tHO8YgPv7eTuf2kOBWWOSQaVMF9tn8Xrh3f/3Zza2nxt0Y6qB5RxZwfVgDQ/p11stVf1z4ZrjIGh DjBjrK4ec+VpiOn8ePZDBqZGUf4NAxdpoHTM4yaMVgryTkGAgn0Oq1TJmwjtu/M1KJlnUTp288LB OJB4TC8PCqEuSIGqTZcCWsfU1q7y6q2Msj5vSMt0Gbd3adKUNU0yCDMrBTkaT2hxDkHMSDY4NA/R wpfNIn1wh80rK2KUfEXPbz2GL26p0xXpVbzm2Qqil9PQTCnF3GXy0B3p8GPKf1eZ5Y2tsKaCXpCe 8fetTkdK8aM8NnUHVuHYs4H53bL151Ec/XPth/4W8WL7DTH/WOorME2PGAp4Tg4fokW4wbheb2nq LXMPsLn22QqcUYz5S63kVBCm5k43/n3G8zgf+QS60MrzWPkJwn6VtSsTtP6pDdOv0G6eCKtPM9Q8 VfW7+qM9XZjQb6Xpqe1lVW6ZtNYalhCSZgLOg+5Lw83T01IVzfEJgLZ1TuTT4iE/Kj/i7gFB8GqD hkgSfch1fR4N1Q0FwOdrRY9D4WAY7ad3KFlAlaJTONcYbOQA4jjRXwAzKvGMJfy7bF5EjY4FvpEb r4sGAKzw4h2Yke2H4hE/s3sIIRMDU/v9333pvIDxw3KhUncqUP4tYt1G9TEZGNyP+zrAgZRm7c6P 4M62pKnUetJMdjFb6gpxJxfuuSLVawTzsGmwqFoOhfX0QR1desFLye+wr0sN+fMI9b4BBjZwYCyz BwibXy7BIZCwT81JLJ4ehtulgPnNdOgm0H6XCHypzB98XalqkpIE61+ROEMBnCNRGknBQf3+cUOa QP22iSpqok56XZuHCjlOg5yn2H7iBWRllj+y284vJBQBrqp0n1g02XwFIEkCbukItk72pS+Avv63 SZaRYzhnAZ/3elAfnXovHN7XOWLi/s5IrX5HOO0hULyxaVH0ADE2dw4bKbgUdDNMo69HRvX8DRzc 2cJinjoJHv8jxf6/IJOT0FMo6Ck/zs6d0Z7/O5YaJRKzbff69AMujcF4BWKCG1zDcH91FdJbtYdU 8DCDpEeyHGKpLI6log2qijNt0iIcteJwRio4ZfJ+sYnP7KZMAnxi/wNFGndbUcfvjhbHzwVBj0a3 Yi/6rGh0JLp93A+xLh6vi01tWQCX6OORyJ3GRFMG+n4VcKnpi2p3GAdFjGrDWcUdQo3KWxM6VIAx zVfdCLR4V1xoyVX1u5Pl2g/5UaDkN/skP9Kok+9IMe23fTuYi0nbWuEQJlNrE0W4vK1nrf1kAZpn DpRZ36Dgz3ZNVaiV43FXGC4M3JRcEtIHY0r4+509EcGU+2aVihguNHNsV4n85qAUr3FGyhqI+LSp kGsDQHfhFLZuA0g8w9Rj+Vu7Mie9V6XrB4dnEqhD75QW6jv6TJdffFuMahem8Hw2mTuZR/EGpwx2 IR85zEzQpkiJMSuibudcfH85tVV8lq6lfoMxV1qTiW8bFN2eoK021uLCtqLnP+roH8uGhvVnIKFA ma43XxlEwLGQpYL1/mWzNEIL6RXyKoL9IIeK4i+gv+uPtl/zURlWoVWu1vMCqvVtgjFLfpVlosf7 JjpoBK10owOTQVdUMM47zshy7dW1XxsiISal3SfXFYPeo2xxUHZD0DxiHiwlyKAHxXZQRjq/2NlT QXxcvlTF1ct1pR7SFw6JZFIrukt0+NmvN6BCbbi03ln2m6V8UOrThp7OXZiZKUmwlPG2W+66ZRPm 0K+P5dj4keNn3ZeE77AY1JSssooRxLVmYPZCxgz/h75NvetfNG8T647/s63N2Z12KQqcVIUO1OWJ bf2B1drvHTdEh0R2TcuTEM2ZL3S72xJDEjHdLXuUKLJvNIy1Nxz654x4Zj4yfK/m3ysm1XqPYztu auP+pUrNm4aLzwgVWIz0f7/46KoBYuBsCVr+7N0cRPlSSt11dw+5opS7edpQJPz1cn9d3c5Hlt8m DmXs7txaecJF+OFPLAaikIyxZAtQE4ODQXxRH7q2uT2qAwrwRO4qziN6PBqAugaezeht6KRXkBnB rQp8/0hM0a/LxOGVumLvQKPQAw8zfcN3PdSE9z2uZjj1r2uT9jVqZeXGuGvrmW8D5SZbUJxoXZJx sYDIjmYbAIH387YpJ0kh0QmwL7lY4FweXv7kG/LOso1Uau4gKl1IWSdds6/3++YThyaNVPWoubyS 3JpXPAWehdaTLaVVRQ50GABV0gzKT7kvWo8M6UZ14/ikO3V4U4P4iEEG1P9rPodz7XWu8IXt87tv NgY6dvzamay11Wl4AsWoRyknSG6M3S3IGM2B5dTgqXksh611RIhZvqylpmSfqCTCoWINg1Q+e7MP ECYQtkWt0mSEwFyWhx1w0tfIYSQ/GUVsIWQrcDrAI78HHT816Q72MNcUiUu6pdFyVmj6npyb1oBG pBxAW3Htsa/KvFyrPyyALYElvPFKj2CMPH8x/bDFKIGWS4WH426fux1+lCeIA3H8wfH/9wBV9Jzp e09g+ukbwSmCdB2h+Lb6byJ/auf7Zq41pekAT3pvpz7E43JdiLx7WWWMBaQcvrBC3b4Fp/KYrWse h7f38dmUUnCsWpDp/PdsD64gbLRLcEFzyBBPESknOj94lTdCiXH8VBQ+gAz77czbuZQqmcp8L5HO 0bisviOiTfaRLwdJpFfv9MQt1NK2gqWwz1fCAJ0Q5t/ZJx43OJe6RRK4STwoQo1uYI/PcXVw2vMW 7aUvmpKBMubfDDgaN+u88n5nCzrM1XkrUO54dfyROeLQnBdGcVmQsRT8Gp0U3YykLdd3OmwRr6fo T+l/IwzsHrRcjd+g9RvJ/woXVP8cf4njX252jwEGll0z1IHUE8gPY9ud3GEbafzaUNsbMxm64Htt sPQC5cNHZzhBnTkKJThWDBEuyKK/hO61euPGzts3QugwDpcwWQ1RSVSpcrtSnkCPC9QWzUS3Qs1x o5KR8ddpR8m+cbLzrzsXkElLsQ6FJoTZ+oyGyjXKiTHJQ4eQ0+ly3AZ4kZ7/j+56epugThLwr5AH KlWu+/wKDZqWS5he9jk+tOHXiH3hpY24kemWeZGXTBv9uXTSNSc8FFPxRLi8MUq6I4jvs2/hoedV IzqHM3/JLo6J4PTsGmOqExnG1RtUqWa6l1Ac4YZxEZtxKA4sDuRN5I8bDDlokIOPus9edD8o8qIq WosYUYMac4X/eS4ec7UtbQkqAlEEuSrPG2a88gupXNkrwYz8a4cWWNlp0mwOg3kkOufYGdvTEI5T T+CCxOjiIL6/9N+S/ccGLpfNaQYZ3sFKlvs4k07WFp1nSeRhjZeQSamHI3fvNt0adK6WQYN6ACcI YqsHwc11pT5hgvf3IcZ1wbmn6WB/sNQwRWPnML23OsY2WNmdI9FFBDg6y3zI18u5pWt1DkGvH0mv ckdhVAVF4AJdkx820TupXxt3TyChFHMJ1hbxwk/xqT8bbYY/awKVKJwLyQfqrOlxM9vCchPbDoPO ARlM4lUc2E4EjcYljRV3CtGPgDVP/KD8HAdfFGVm3yJX/cavTjhfcVEYLmABVod3wypMN6blpt0Y FOHN14f1fCybAfmZO55PnCKWOKEw3b01J3TldQhilgbCZMnlI25SAAb2zVc+Dqc1kMUtxRmXU+Z0 0qwHTICzujra/vlkvLXobW82byCXRSXUN3GShbO4zCGgTaS0uR3t4oJUgBJpmOKgUmi5DAryt3u0 WAitLHL7557MzUaoQTPhlmkXMNfxPDbsxI6pgTxSdhG/Q8wc+E9lwT9btX+Amez4kExP8PxEQlqs ME808iBnKwVplgxP9zNeYEEoVnhhmC8nQmQc6kWlzuLVFYFMj38rUYSysTysD8sohkfSTeJJvJo3 x+Hq2eSENpmwxbw35GEhUJKXv/Hmz5QOGFczlXC8D3lYFVyz7Q5t+o/A5nEm/heFho2EXCRiR2lb Y5W6YbVJxXylGdFJN3QtByyLhpcY5Nq/EFshreH0onH+mAakh6Z6Kj81b0/zhWEnRvl2PoVmSsAc kceAiboY4Df6yVxteJG2NTXCiReHnaEWgvnZcqI1sa5nQSi+IgRuUlvtNjz/MxRirFAAml8kyx9r NbposrtzolmRuyMwdYZ/fS3k750QtpFhf1U9xXDGATxlHxkglvrXoTBUFZS7s6XAps1rOvnUUx5l p2WP0Le5yoVaIjCnbSq+w5wLGG/WTEj7Z8Uco32PVGHbvazkWNejyXEX9UoGm82rdfUNzTXPQxHl neoALJKMkJtwtbUDHAJOh/SolyqTPiO5wZaNoDPDiPfwy8p033kBi3D64ZpeGnXAvqkgAN1D5QN6 PynNP6Fj4KSC7h9PS6uIeJ5z0dEKAL+yQ7L3Ddj7UgvsShs0jAlJ6AP6h7sSFK8i478VfBhZwBim 2RBaGRijrV/UPSXDWG6koIhNcC1eBcxtIrqsJbrpWVOCUirtuCYT111xAlpvBZc3Vh/1+s2WNXic WAoKDAOZpM2YL9qypethZsV0QT1Nbg+NtO8NuGF7Cos1JnKDYB83MMaTJOVJUtvuaYaq8tltfRoj oo79YgZfCchTWsg+eSvpWFBvXhr6OFpmImLV5caplo3CuP66c7k5IQa/0mTIkDQ3cU7QFYMleE3h JNIJ6vU4eK0Kftclx/e/kMUaf6DokXZ4Nsn/o8uHKPfIM9LZWSqRPRv9Z67v0PGrVr+Hp8RRt3oL KEwkuuhrdR0m9PnzPIDbkB8Y4nuVZejdUTa2rHANZDYzm/xXpxM3T/WJEAvqCCeRIoqChA+blakU AVbG4Wpb1uF3PQdFa5ZwbfK+Fj6fSqapaEQQU+RxqGPAj4YpDADTeyD+c7hSQH6AEhq2Aw3pJqQp Sv90n49qs5UaU5PMetrAoIg1YNHYzXAkdhPS9kRLmLXB/HIgtlcGB/pyicGk7qfFu6lX3VswzcHQ JqLWWghdyo6pFyECPCi+E27/d8bM3uv1tmvABnI6KwJGL40SAYai72nbyPgVXzrDNBqc6WAfA/V9 zV3rhBEJ7HiCsXzZFlF/8TKHhwWevbsgD/QywlHUuYZ8E6kJ9UrQYSjeO2TRXc0ldUM3P34g9USv f5j4rHHbcsv3msNs+91CT6Nbrfy/QNSB/6lo7b+Un3uyTGtkeYWkkQRIB3dkIo+LDTbSw34MFWKQ /0zWTeZMYRrGhPiUkStxZoMfi81YtlqGrxRMAKjT40KVeywGtyzlFZJgJanzcvN+h8I5cZsePpsY hawvuvkXg5zjUUfCx/sjBsjYmvNw5GjJKF2ANQ9r5i93QgQS5MFeJJuG33F2RUVIMztia0HmCGH2 SPt7Gmp2BfwBoaDyF0X5RrAudKkJYh+c0fT4nLUJ0fhaIUc3B6kdKI7Ws56jUgM5VvZHvex060iN Q+tvqPZgv/dfbw/XfwWITT/Zds7rPGPspkg8RT+BWRfcf7OP21X9LcKQrmWvUPEDC0Ck9SZ16sML I+8QswhP5KZvpkilJfZ4W+SfIc5i6ULA24h1N9qpBmnKx99VcXt95lNnPdXBwuxPNXHwH/USJcsk N4sVatwhwbNT/WivqUXo9MHNCDJYFPXBjyyP52+jc5QEGUQBFpadF0aOkeAxaDRHQIy7/igPWc/x 1NLxZBZ5ncrzev6H2RUZ3aT5Z35qbLrkqmH/FRFCUl5b9+cF5X01u7MfvZdpnt71tNQfrf3FqzIe GYEZ/hfdcIJ2lHiEVD761LvZeI9rZ4VsJZh5OhwO1Y9QDfqOSrh+uRliN2ePZ0CCsE+yg8QOFM7Q 46d8kVeRqKBAZxCPD65mEhU/pbZBM6awUEwgdzfsnnKaE57EMMHGA5/P/Hyt1OftPWfh0IzJ+S9m 7jRQkYWhd0de7ekxRidM1qacWskfijJ51eSWaDVnssJkQ67BLPMddZgB5ul8fPukkOY+h8L+kWbV UPaNOoHU6cUVm/SLWBlbDrQ/k64+enc1ImyNEpcBpMnIyRqWww+Bsx85W8QJokz3XeWAgDMuauQ0 MOkI6NZwOKPxw4N3o8Ev08dKaSxsNPft57LGhTh0kAm1bdkibwG6G8OHO6cWvV8UZUSJ2zwzY25o rgUZicPuxX8D8tXDCZR7jMQCJnt1O3JPWcs0CihOvkc79xAjiil6VD01rps3NyDm/p4UHmDhSSwL WKWv4CW/g9E2PMcr5rMPS4iGxzNy5IA9AFFgFDTDJ3YT48d4+KuXp5t/oyiGfwbpjmWv3Gykuk+a oFXfKWbeua83mvP4IVpIbNzJXCZNa1E6kpAaTGM18sZ8XnkWDPSaZAj5UPHh8wfSe+q1EiHmuB03 QXEtITBkL2T//caiYnjGlHtxLTRx/2Dwyoyef+NKcSjvrJBXNxqrHv7vShgiP4kro46b4wTV7VwR FdrbKK268A0yuXJAUdKxRyApXn8bE8qCqtz2nxxfhZv8Jzic1JwzEvaN6sA/eizeYQCgKrIoVBAh Rx1ru9dHdgHDI+MvT1TUbzQE7kcFklCEP3pbVEijjUQw2NRL7m/DSvDijTTqnJtfZIvtXU8MhwiY z24tsnf9118xFNOhQ1hyWZjrGNc/O1rYjqixu1dqAPgazYPQxsWQ32bx7AqGrgr3Qi3zDLadIMdP ImDlKU30DHHaXHAfj4vXG+RlA9VlqrNiue4BZNg+pqyJsl9zn2GsPxr7wbrGjqp3InJplJIfFiPR BeHs+Q1qc7yyfhqceMkeF1vB2j4MGcqJNqEY5SZVmsPG0EDHWOjjy4Y2at2rlioLy1b3uIqIZzve 0xNljReM8EmCj2FMiH/UqK+c5dyCseYmSNVv2vtbiv4MRJBAtlRgMnkispwIaKWyNIvop4LNXBwz oFnFjgP83hlbKre8H1d/pceoMt1ysn5UtmS8VzjmNyBg2TkJ0Tk4sMTcDXsSd8h7xf7UXrLZVfi7 1py5wt1KK29wfUz9FNtRuImAs1XomaSHnyElRzQMlEU3F/v7ckSkzqEvVJCnY7eOLzxB8/jxGhtu iRrSgiRUMLz/nhIzu9tatZCB45f3BlpJdbQBsSOxaevfDmfP72Vgh/8iV4Sj5QYKfuyfMqi7M43Z ftmXEbd8NxYpKFIFtCYLvWgR+RhvRLFMzpl93qzpZLo5y0Y0haDOh3XEdAsqh2PBXU1Tc/m2wX+s JHbtvNUu7/AsjLFsdsJKJqA8pJZygD/IhzspTRNuwTEIfjNrshtre/jr0vmD2Ue/8FKYpk9QJd0Z r2uF/u9QXNsovadV05JUgr3BUVyvNYUHbRxq2jKauWN/x5pCEOnW8ID+TuN4owkW36bbaKBDfuyS MeyaRRwIguQ1E+BGZp5I3kt/DCCBMKjiRfWZ67Lf1+9zCr6AgOJDB2j20mBOdHA67O2EIrnY3Pd5 XcgX7A== `protect end_protected	mit	19bb0b07b4fca4f084b8989be862d4c2	0.930696	1.877603	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_status_cntl.vhd	1	58,183	------------------------------------------------------------------------------- -- axi_datamover_wr_status_cntl.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_wr_status_cntl.vhd -- -- Description: -- This file implements the DataMover Master Write Status Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_wr_status_cntl.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 7/11/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- -- Per CR616212 -- - Changed logic to force a coesc register push when a TLAST error is -- reported by the Write Data Controller. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_fifo; ------------------------------------------------------------------------------- entity axi_datamover_wr_status_cntl is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if the Indeterminate BTT Module is enabled -- for use (outside of this module) C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1; -- Sets the width of the data2wsc_bytes_rcvd port used for -- relaying the actual number of bytes received when Idet BTT is -- enabled (C_ENABLE_INDET_BTT = 1) C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8; -- Specifies the depth of the internal status queue fifo C_STS_WIDTH : Integer range 8 to 32 := 8; -- sets the width of the Status ports C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the Status reply C_FAMILY : String := "virtex7" -- Specifies the target FPGA device family ); port ( -- Clock and Reset inputs ------------------------------------------ -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------------- -- Soft Shutdown Control interface -------------------------------- -- rst2wsc_stop_request : in std_logic; -- -- Active high soft stop request to modules -- -- wsc2rst_stop_cmplt : Out std_logic; -- -- Active high indication that the Write status Controller -- -- has completed any pending transfers committed by the -- -- Address Controller after a stop has been requested by -- -- the Reset module. -- -- addr2wsc_addr_posted : In std_logic ; -- -- Indication from the Address Channel Controller to the -- -- write Status Controller that an address has been posted -- -- to the AXI Address Channel -- -------------------------------------------------------------------- -- Write Response Channel Interface ------------------------------- -- s2mm_bresp : In std_logic_vector(1 downto 0); -- -- The Write response value -- -- s2mm_bvalid : In std_logic ; -- -- Indication from the Write Response Channel that a new -- -- write status input is valid -- -- s2mm_bready : out std_logic ; -- -- Indication to the Write Response Channel that the -- -- Status module is ready for a new status input -- -------------------------------------------------------------------- -- Command Calculator Interface ------------------------------------- -- calc2wsc_calc_error : in std_logic ; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- --------------------------------------------------------------------- -- Address Controller Status ---------------------------------------- -- addr2wsc_calc_error : In std_logic ; -- -- Indication from the Address Channel Controller that it -- -- has encountered a calculation error from the command -- -- Calculator -- -- addr2wsc_fifo_empty : In std_logic ; -- -- Indication from the Address Controller FIFO that it -- -- is empty (no commands pending) -- --------------------------------------------------------------------- -- Data Controller Status --------------------------------------------------------- -- data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The command tag -- -- data2wsc_calc_error : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- has encountered a Calculation error in the command pipe -- -- data2wsc_last_error : In std_logic ; -- -- Indication from the Write Data Channel Controller that a -- -- premature TLAST assertion was encountered on the incoming -- -- Stream Channel -- -- data2wsc_cmd_cmplt : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- corresponding status is the final status for a parent -- -- command fetched from the command FIFO -- -- data2wsc_valid : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- has a new tag/error status to transfer -- -- wsc2data_ready : out std_logic ; -- -- Indication to the Data Channel Controller FIFO that the -- -- Status module is ready for a new tag/error status input -- -- -- data2wsc_eop : In std_logic; -- -- Input from the Write Data Controller indicating that the -- -- associated command status also corresponds to a End of Packet -- -- marker for the input Stream. This is only used when Store and -- -- Forward is enabled in the S2MM. -- -- data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); -- -- Input from the Write Data Controller indicating the actual -- -- number of bytes received from the Stream input for the -- -- corresponding command status. This is only used when Store and -- -- Forward is enabled in the S2MM. -- ------------------------------------------------------------------------------------ -- Command/Status Interface -------------------------------------------------------- -- wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); -- -- Read Status value collected during a Read Data transfer -- -- Output to the Command/Status Module -- -- stat2wsc_status_ready : In std_logic; -- -- Input from the Command/Status Module indicating that the -- -- Status Reg/FIFO is Full and cannot accept more staus writes -- -- wsc2stat_status_valid : Out std_logic ; -- -- Control Signal to Write the Status value to the Status -- -- Reg/FIFO -- ------------------------------------------------------------------------------------ -- Address and Data Controller Pipe halt -------------------------------- -- wsc2mstr_halt_pipe : Out std_logic -- -- Indication to Halt the Data and Address Command pipeline due -- -- to the Status pipe getting full at some point -- ------------------------------------------------------------------------- ); end entity axi_datamover_wr_status_cntl; architecture implementation of axi_datamover_wr_status_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_cnt_width -- -- Function Description: -- Sets a count width based on a fifo depth. A depth of 4 or less -- is a special case which requires a minimum count width of 3 bits. -- ------------------------------------------------------------------- function funct_set_cnt_width (fifo_depth : integer) return integer is Variable temp_cnt_width : Integer := 4; begin if (fifo_depth <= 4) then temp_cnt_width := 3; elsif (fifo_depth <= 8) then temp_cnt_width := 4; elsif (fifo_depth <= 16) then temp_cnt_width := 5; elsif (fifo_depth <= 32) then temp_cnt_width := 6; else -- fifo depth <= 64 temp_cnt_width := 7; end if; Return (temp_cnt_width); end function funct_set_cnt_width; -- Constant Declarations -------------------------------------------- Constant OKAY : std_logic_vector(1 downto 0) := "00"; Constant EXOKAY : std_logic_vector(1 downto 0) := "01"; Constant SLVERR : std_logic_vector(1 downto 0) := "10"; Constant DECERR : std_logic_vector(1 downto 0) := "11"; Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000"; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant STAT_REG_TAG_WIDTH : integer := 4; Constant SYNC_FIFO_SELECT : integer := 0; Constant SRL_FIFO_TYPE : integer := 2; Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH; Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH); Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0'); Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH); Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH); Constant WRESP_WIDTH : integer := 2; Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH; Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH; Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH); Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '1'); -- Signal Declarations -------------------------------------------- signal sig_valid_status_rdy : std_logic := '0'; signal sig_decerr : std_logic := '0'; signal sig_slverr : std_logic := '0'; signal sig_coelsc_okay_reg : std_logic := '0'; signal sig_coelsc_interr_reg : std_logic := '0'; signal sig_coelsc_decerr_reg : std_logic := '0'; signal sig_coelsc_slverr_reg : std_logic := '0'; signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_pop_coelsc_reg : std_logic := '0'; signal sig_push_coelsc_reg : std_logic := '0'; signal sig_coelsc_reg_empty : std_logic := '0'; signal sig_coelsc_reg_full : std_logic := '0'; signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data_err_reg : std_logic := '0'; signal sig_data_last_err_reg : std_logic := '0'; signal sig_data_cmd_cmplt_reg : std_logic := '0'; signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0'); signal sig_push_status : std_logic := '0'; Signal sig_status_push_ok : std_logic := '0'; signal sig_status_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_s2mm_bready : std_logic := '0'; signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_wresp_sfifo_wr_valid : std_logic := '0'; signal sig_wresp_sfifo_wr_ready : std_logic := '0'; signal sig_wresp_sfifo_wr_full : std_logic := '0'; signal sig_wresp_sfifo_rd_valid : std_logic := '0'; signal sig_wresp_sfifo_rd_ready : std_logic := '0'; signal sig_wresp_sfifo_rd_empty : std_logic := '0'; signal sig_halt_reg : std_logic := '0'; signal sig_halt_reg_dly1 : std_logic := '0'; signal sig_halt_reg_dly2 : std_logic := '0'; signal sig_halt_reg_dly3 : std_logic := '0'; signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_posted_cntr_eq_0 : std_logic := '0'; signal sig_addr_posted_cntr_eq_1 : std_logic := '0'; signal sig_addr_posted_cntr_max : std_logic := '0'; signal sig_decr_addr_posted_cntr : std_logic := '0'; signal sig_incr_addr_posted_cntr : std_logic := '0'; signal sig_no_posted_cmds : std_logic := '0'; signal sig_addr_posted : std_logic := '0'; signal sig_all_cmds_done : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_wr_valid : std_logic := '0'; signal sig_dcntl_sfifo_wr_ready : std_logic := '0'; signal sig_dcntl_sfifo_wr_full : std_logic := '0'; signal sig_dcntl_sfifo_rd_valid : std_logic := '0'; signal sig_dcntl_sfifo_rd_ready : std_logic := '0'; signal sig_dcntl_sfifo_rd_empty : std_logic := '0'; signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_statcnt : std_logic := '0'; signal sig_decr_statcnt : std_logic := '0'; signal sig_statcnt_eq_max : std_logic := '0'; signal sig_statcnt_eq_0 : std_logic := '0'; signal sig_statcnt_gt_eq_thres : std_logic := '0'; signal sig_wdc_status_going_full : std_logic := '0'; begin --(architecture implementation) -- Assign the ready output to the AXI Write Response Channel s2mm_bready <= sig_s2mm_bready or sig_halt_reg; -- force bready if a Halt is requested -- Assign the ready output to the Data Controller status interface wsc2data_ready <= sig_wsc2data_ready; -- Assign the status valid output control to the Status FIFO wsc2stat_status_valid <= sig_status_valid ; -- Formulate the status output value to the Status FIFO wsc2stat_status <= sig_wsc2stat_status; -- Formulate the status write request signal sig_status_valid <= sig_push_status; -- Indicate the desire to push a coelesced status word -- to the Status FIFO sig_push_status <= sig_coelsc_reg_full; -- Detect that a push of a new status word is completing sig_status_push_ok <= sig_status_valid and stat2wsc_status_ready; sig_pop_coelsc_reg <= sig_status_push_ok; -- Signal a halt to the execution pipe if new status -- is valid but the Status FIFO is not accepting it or -- the WDC Status FIFO is going full wsc2mstr_halt_pipe <= (sig_status_valid and not(stat2wsc_status_ready)) or sig_wdc_status_going_full; -- Monitor the Status capture registers to detect a -- qualified Status set and push to the coelescing register -- when available to do so sig_push_coelsc_reg <= sig_valid_status_rdy and sig_coelsc_reg_empty; -- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and -- pre CR616212 sig_dcntl_sfifo_rd_valid) or -- pre CR616212 (sig_data_err_reg and -- pre CR616212 sig_dcntl_sfifo_rd_valid); sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and sig_dcntl_sfifo_rd_valid) or (sig_data_err_reg and sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212 (sig_data_last_err_reg and -- Added for CR616212 sig_dcntl_sfifo_rd_valid); -- Added for CR616212 -- Decode the AXI MMap Read Respose sig_decerr <= '1' When sig_bresp_reg = DECERR Else '0'; sig_slverr <= '1' When sig_bresp_reg = SLVERR Else '0'; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_LE_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is less than or equal to the available number -- of bits in the Status word. -- ------------------------------------------------------------ GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_small; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_SMALL_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg) begin -- Set default value lsig_temp_tag_small <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg; end process POPULATE_SMALL_TAG; end generate GEN_TAG_LE_STAT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_GT_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is greater than the available number of -- bits in the Status word. The upper bits of the TAG are -- clipped off (discarded). -- ------------------------------------------------------------ GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_big; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_BIG_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg) begin -- Set default value lsig_temp_tag_big <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0); end process POPULATE_SMALL_TAG; end generate GEN_TAG_GT_STAT; ------------------------------------------------------------------------- -- Write Response Channel input FIFO and logic -- BRESP is the only fifo data sig_wresp_sfifo_in <= s2mm_bresp; -- The fifo output is already in the right format sig_bresp_reg <= sig_wresp_sfifo_out; -- Write Side assignments sig_wresp_sfifo_wr_valid <= s2mm_bvalid; sig_s2mm_bready <= sig_wresp_sfifo_wr_ready; -- read Side ready assignment sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_WRESP_STATUS_FIFO -- -- Description: -- Instance for the AXI Write Response FIFO -- ------------------------------------------------------------ I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => WRESP_SFIFO_WIDTH , C_DEPTH => WRESP_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_wresp_sfifo_wr_valid , fifo_wr_tready => sig_wresp_sfifo_wr_ready , fifo_wr_tdata => sig_wresp_sfifo_in , fifo_wr_full => sig_wresp_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_wresp_sfifo_rd_valid , fifo_rd_tready => sig_wresp_sfifo_rd_ready , fifo_rd_tdata => sig_wresp_sfifo_out , fifo_rd_empty => sig_wresp_sfifo_rd_empty ); -------- Write Data Controller Status FIFO Going Full Logic ------------- sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and sig_dcntl_sfifo_wr_ready; sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and sig_dcntl_sfifo_rd_ready; sig_statcnt_eq_max <= '1' when (sig_wdc_statcnt = DCNTL_STATCNT_MAX) Else '0'; sig_statcnt_eq_0 <= '1' when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO) Else '0'; sig_statcnt_gt_eq_thres <= '1' when (sig_wdc_statcnt >= DCNTL_HALT_THRES) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WDC_GOING_FULL_FLOP -- -- Process Description: -- Implements a flop for the WDC Status FIFO going full flag. -- ------------------------------------------------------------- IMP_WDC_GOING_FULL_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wdc_status_going_full <= '0'; else sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres; end if; end if; end process IMP_WDC_GOING_FULL_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DCNTL_FIFO_CNTR -- -- Process Description: -- Implements a simple counter keeping track of the number -- of entries in the WDC Status FIFO. If the Status FIFO gets -- too full, the S2MM Data Pipe has to be halted. -- ------------------------------------------------------------- IMP_DCNTL_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wdc_statcnt <= (others => '0'); elsif (sig_incr_statcnt = '1' and sig_decr_statcnt = '0' and sig_statcnt_eq_max = '0') then sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE; elsif (sig_incr_statcnt = '0' and sig_decr_statcnt = '1' and sig_statcnt_eq_0 = '0') then sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE; else null; -- Hold current count value end if; end if; end process IMP_DCNTL_FIFO_CNTR; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Implements the logic needed when Indeterminate BTT is -- not enabled in the S2MM function. -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate -- Local Constants Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3; Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0; Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1; Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2; Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1; -- local signals signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); begin sig_wsc2stat_status <= sig_coelsc_okay_reg & sig_coelsc_slverr_reg & sig_coelsc_decerr_reg & sig_coelsc_interr_reg & sig_tag2status; ----------------------------------------------------------------------------- -- Data Controller Status FIFO and Logic -- Concatonate Input bits to build Dcntl fifo data word sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2 data2wsc_calc_error & -- bit 2 data2wsc_last_error & -- bit 1 data2wsc_cmd_cmplt ; -- bit 0 -- Rip the DCntl fifo outputs back to constituant pieces sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto DCNTL_SFIFO_TAG_INDEX); sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ; sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX); sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX); -- Data Control Valid/Ready assignments sig_dcntl_sfifo_wr_valid <= data2wsc_valid ; sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready; -- read side ready assignment sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_DATA_CNTL_STATUS_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO -- ------------------------------------------------------------ I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => DCNTL_SFIFO_WIDTH , C_DEPTH => DCNTL_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid , fifo_wr_tready => sig_dcntl_sfifo_wr_ready , fifo_wr_tdata => sig_dcntl_sfifo_in , fifo_wr_full => sig_dcntl_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid , fifo_rd_tready => sig_dcntl_sfifo_rd_ready , fifo_rd_tdata => sig_dcntl_sfifo_out , fifo_rd_empty => sig_dcntl_sfifo_rd_empty ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: STATUS_COELESC_REG -- -- Process Description: -- Implement error status coelescing register. -- Once a bit is set it will remain set until the overall -- status is written to the Status FIFO. -- Tag bits are just registered at each valid dbeat. -- ------------------------------------------------------------- STATUS_COELESC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_coelsc_reg = '1') then sig_coelsc_tag_reg <= (others => '0'); sig_coelsc_interr_reg <= '0'; sig_coelsc_decerr_reg <= '0'; sig_coelsc_slverr_reg <= '0'; sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY" sig_coelsc_reg_full <= '0'; sig_coelsc_reg_empty <= '1'; Elsif (sig_push_coelsc_reg = '1') Then sig_coelsc_tag_reg <= sig_data_tag_reg; sig_coelsc_interr_reg <= sig_data_err_reg or sig_data_last_err_reg or sig_coelsc_interr_reg; sig_coelsc_decerr_reg <= not(sig_data_err_reg) and (sig_decerr or sig_coelsc_decerr_reg); sig_coelsc_slverr_reg <= not(sig_data_err_reg) and (sig_slverr or sig_coelsc_slverr_reg); sig_coelsc_okay_reg <= not(sig_decerr or sig_coelsc_decerr_reg or sig_slverr or sig_coelsc_slverr_reg or sig_data_err_reg or sig_data_last_err_reg or sig_coelsc_interr_reg ); sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg; sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg); else null; -- hold current state end if; end if; end process STATUS_COELESC_REG; end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT -- -- If Generate Description: -- Implements the logic needed when Indeterminate BTT is -- enabled in the S2MM function. Primary difference is the -- addition to the reported status of the End of Packet -- marker (EOP) and the received byte count for the parent -- command. -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate -- Local Constants Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH + C_SF_BYTES_RCVD_WIDTH + 3; Constant SF_SFIFO_LS_TAG_INDEX : integer := 0; Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1); Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1; Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1; Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1; Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+ (C_SF_BYTES_RCVD_WIDTH-1); Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1; Constant BYTES_RCVD_FIELD_WIDTH : integer := 23; -- local signals signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_data_eop : std_logic := '0'; signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_coelsc_eop : std_logic := '0'; signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0'); begin sig_wsc2stat_status <= sig_coelsc_eop & sig_coelsc_bytes_rcvd_pad & sig_coelsc_okay_reg & sig_coelsc_slverr_reg & sig_coelsc_decerr_reg & sig_coelsc_interr_reg & sig_tag2status; ----------------------------------------------------------------------------- -- Data Controller Status FIFO and Logic -- Concatonate Input bits to build Dcntl fifo input data word sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7 data2wsc_cmd_cmplt & -- bit 6 data2wsc_calc_error & -- bit 4 data2wsc_tag; -- bits 0 to 3 -- Rip the DCntl fifo outputs back to constituant pieces sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX); sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto SF_SFIFO_LS_BYTES_RCVD_INDEX); sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX); sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX); sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto SF_SFIFO_LS_TAG_INDEX) ; -- Data Control Valid/Ready assignments sig_dcntl_sfifo_wr_valid <= data2wsc_valid ; sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready; -- read side ready assignment sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_SF_DATA_CNTL_STATUS_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO when Store and -- Forward is included. -- ------------------------------------------------------------ I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => SF_DCNTL_SFIFO_WIDTH , C_DEPTH => DCNTL_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid , fifo_wr_tready => sig_dcntl_sfifo_wr_ready , fifo_wr_tdata => sig_dcntl_sfifo_in , fifo_wr_full => sig_dcntl_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid , fifo_rd_tready => sig_dcntl_sfifo_rd_ready , fifo_rd_tdata => sig_dcntl_sfifo_out , fifo_rd_empty => sig_dcntl_sfifo_rd_empty ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SF_STATUS_COELESC_REG -- -- Process Description: -- Implement error status coelescing register. -- Once a bit is set it will remain set until the overall -- status is written to the Status FIFO. -- Tag bits are just registered at each valid dbeat. -- ------------------------------------------------------------- SF_STATUS_COELESC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_coelsc_reg = '1') then sig_coelsc_tag_reg <= (others => '0'); sig_coelsc_interr_reg <= '0'; sig_coelsc_decerr_reg <= '0'; sig_coelsc_slverr_reg <= '0'; sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY" sig_coelsc_bytes_rcvd <= (others => '0'); sig_coelsc_eop <= '0'; sig_coelsc_reg_full <= '0'; sig_coelsc_reg_empty <= '1'; Elsif (sig_push_coelsc_reg = '1') Then sig_coelsc_tag_reg <= sig_data_tag_reg; sig_coelsc_interr_reg <= sig_data_err_reg or sig_coelsc_interr_reg; sig_coelsc_decerr_reg <= not(sig_data_err_reg) and (sig_decerr or sig_coelsc_decerr_reg); sig_coelsc_slverr_reg <= not(sig_data_err_reg) and (sig_slverr or sig_coelsc_slverr_reg); sig_coelsc_okay_reg <= not(sig_decerr or sig_coelsc_decerr_reg or sig_slverr or sig_coelsc_slverr_reg or sig_data_err_reg or sig_coelsc_interr_reg ); sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd; sig_coelsc_eop <= sig_data_eop; sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg; sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg); else null; -- hold current state end if; end if; end process SF_STATUS_COELESC_REG; ------------------------------------------------------------ -- If Generate -- -- Label: SF_GEN_PAD_BYTES_RCVD -- -- If Generate Description: -- Pad the bytes received value with zeros to fill in the -- status field width. -- -- ------------------------------------------------------------ SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate begin sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto C_SF_BYTES_RCVD_WIDTH) <= (others => '0'); sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd; end generate SF_GEN_PAD_BYTES_RCVD; ------------------------------------------------------------ -- If Generate -- -- Label: SF_GEN_NO_PAD_BYTES_RCVD -- -- If Generate Description: -- No padding required for the bytes received value. -- -- ------------------------------------------------------------ SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate begin sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required end generate SF_GEN_NO_PAD_BYTES_RCVD; end generate GEN_ENABLE_INDET_BTT; ------- Soft Shutdown Logic ------------------------------- -- Address Posted Counter Logic ---------------------t----------------- -- Supports soft shutdown by tracking when all commited Write -- transfers to the AXI Bus have had corresponding Write Status -- Reponses Received. sig_addr_posted <= addr2wsc_addr_posted ; sig_incr_addr_posted_cntr <= sig_addr_posted ; sig_decr_addr_posted_cntr <= sig_s2mm_bready and s2mm_bvalid ; sig_addr_posted_cntr_eq_0 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ZERO) Else '0'; sig_addr_posted_cntr_eq_1 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ONE) Else '0'; sig_addr_posted_cntr_max <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_POSTED_FIFO_CNTR -- -- Process Description: -- This process implements a counter for the tracking -- if an Address has been posted on the AXI address channel. -- The counter is used to track flushing operations where all -- transfers committed on the AXI Address Channel have to -- be completed before a halt can occur. ------------------------------------------------------------- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_addr_posted_cntr <= ADDR_POSTED_ZERO; elsif (sig_incr_addr_posted_cntr = '1' and sig_decr_addr_posted_cntr = '0' and sig_addr_posted_cntr_max = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ; elsif (sig_incr_addr_posted_cntr = '0' and sig_decr_addr_posted_cntr = '1' and sig_addr_posted_cntr_eq_0 = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ; else null; -- don't change state end if; end if; end process IMP_ADDR_POSTED_FIFO_CNTR; wsc2rst_stop_cmplt <= sig_all_cmds_done; sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and not(addr2wsc_calc_error)) or (sig_addr_posted_cntr_eq_1 and addr2wsc_calc_error); sig_all_cmds_done <= sig_no_posted_cmds and sig_halt_reg_dly3; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG -- -- Process Description: -- Implements the flop for capturing the Halt request from -- the Reset module. -- ------------------------------------------------------------- IMP_HALT_REQ_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg <= '0'; elsif (rst2wsc_stop_request = '1') then sig_halt_reg <= '1'; else null; -- Hold current State end if; end if; end process IMP_HALT_REQ_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG_DLY -- -- Process Description: -- Implements the flops for delaying the halt request by 3 -- clocks to allow the Address Controller to halt before the -- Data Contoller can safely indicate it has exhausted all -- transfers committed to the AXI Address Channel by the Address -- Controller. -- ------------------------------------------------------------- IMP_HALT_REQ_REG_DLY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg_dly1 <= '0'; sig_halt_reg_dly2 <= '0'; sig_halt_reg_dly3 <= '0'; else sig_halt_reg_dly1 <= sig_halt_reg; sig_halt_reg_dly2 <= sig_halt_reg_dly1; sig_halt_reg_dly3 <= sig_halt_reg_dly2; end if; end if; end process IMP_HALT_REQ_REG_DLY; end implementation;	bsd-2-clause	49b7c5af5e777a1b9e30b32a37cdc8f7	0.411564	5.10646	false	false	false	false
cwilkens/ecen4024-microphone-array	microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/cic_compiler_v4_0.vhd	1	14,842	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block hNU1Fw8N5flzF7Dghvh6XU+XL4livwFhgUKirojOUYwyKIKeUh7nyLwO0FOegpo/MFH7aElslmiH WCSdhyjBDw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CXbqVSsRUpRk0hgCZEc+6DFcI860KQJ9aXS/R/aWZ44LeB7n/KNhjI0UvOcvG4qKgedNZ18erSkv 4NcXxTL51ZANLRW4vV5G63kqA33/oTvqZ29mRbUlE01gRDQzOR00+nqjWzfeKHex/3Cd0Kje2bas bOdiv+p4vxl6MQaFL6E= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ICxJUWvywkTB2IX+xrIyFqh8q5LbfBkmhGNlHsAFyOjP8AutiwPkvKMJPcbsaEIMkoxqclzys7Dh VksOjN+EZIcGgVAo96+B0dj/e4nBqTDSXWKnrRlZ+BdwlfBvpIiohPy6hN9lxsVVfHBGAWd1uYBq muudxpLZJ20aVw0jmgVJPWtYzOCt4b4bD5XF21wn5V/98y48G9iJ6nsnADHiz6HVCRbqD8A8AXjJ engogkxMp+5sqFmnE6DPcE69qg/lum5Hu8+Br/xleC+NZo58DezDChri/UJrviiXT1lZisxtTQ0k 3yxPD76y72VYT1jciKyc0UD4GlLzZ3RpE41GQg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 1okb0g9l27Ks0+k2riB5pSTUvnU2Cmc7tZSLR0VauQIiKfZYRt569YCYIpKCZMOI6dcOmrhZ/2mA k4Hin6HCBoTVr+rdfv0hH1txb2ata4EMDg/cqSAj72EyNYbkuVaTHDyFUlXDq8vHoES3VnPTbo+0 SuOpbgXutkKZOPemao8= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block RS+gKMWH/ErKVYRpmPl5v/MXxJm4H8IkrCOWuAET1H/zTcAOZoEFCLKY/SRSHPv9xRMOIOCzlWlk +Nkd22GRGnDjJyDpbjBi2A1o3lGHsesDzKSMedwMs7h/wy752JwVKXzamhtVYwElE8b7IQ8tqkAq 136dFy9NCwW4iqecOxR4xI3u2ECR6BTJFLXYi/scLdXXAhUQb8KkOwBtohMzOTmXRDAAQl7TWKbw rmADAtlFXG4uWvoJYEU8C48xsE8i+WItDtK/Myk09JrAld5mIhGqacTd6jjmdBN7b+cs2aZ7szaw t/pi4HPhfg0RSAklB9kxNy0t1EV56cQb7tAubA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9248) `protect data_block 8Lff6nfhbdeB/jQQjslYvQMcIi/OoiaCgZGTr3lLta6wK48AwIAxrUUCHkaZjO+3mPLRc+aco8O8 X2pdZ+YbwiBuWYDtAIMsp9EbtZO2vXCNxMnDs998gQaoEvO8hT1FzwLdQlmdRXq/W1r6s3wvgm7A MljRzrYTFukTeDWNetmQPvvEckwOKZhfjm6eJZxZQ3vBT7rTMRJrJNYnUqP6Boc5R90uBlDiuOaG JYLc1LNCrxS6Cio92dZhBJwgIImzAHQY6PMY9Pk+m4xH1+w+tBtpsN/m0NeomEwUB2UQHKBh4sKr xBjGnOyPW5ATNrrRuz6xPEAFWsV1eQy2JNRZ/eaiC/oxI4bvdZfiKO63qCv+WVVwLV1TOZ7oK8Ru EZ3y2CKNaWJQhapbfP8Y3XK6pW3ipAbOvIXylkMk4zLQzCC5EwQfhBVmaKdRiWyWL6kKc5eGOuE6 GEuzrVjBG7QLxhlCYxHlKJDpM06OsGi9VF68889frlHn9pMdcNTwJrzsrOkz61jeh3DdwaCIJz8p I3C3HsRb27AdlKgk+ZGodRHpp3Rp4zH4QvnSL68t+H7dcFK2RK+6KTOgdvIP4GTIx3DY10zRfx4j qDJDn0OI8PxHCowE/R6rTCbesllxA2rLHTltwSvogXGaY91Hg5Y83bsDCLHHHTt1ngNbUhgDcDRc uJLr5JO1FvqdO7lR08uptHO6r75rSRZOHuwloa3ezjrGcXeRhJ4iXG/gVpWynl19hHpwgDT7o36G PXTEBQTBkBkB5DtfgNx15AOrTFLT/pNdLZth3qBH8Ox4XcLWGNOcdhPlACbbBgsGzqLFWmhVEkQi 9rjqlw1zQqBiioqtMfAPyIlLnhDTsJmE26Z+BmHufxJROqcz9BLzPa6G9sRyFSa5BontJkgtFPeJ 3ZSJ6fjqYRhjQjoNin3b5raNew9EKfWFGMR29ZHJUrURZDJnzOhnMFB8k8axC3S13nRx9Ea1gnHv zshBKZRyyjl+otZQhfzMG0NZxW8eHIC83S17ItLxgdyynZnicabnt9oXlWZaYMXGYn4e3/IjRXor SimFaS/yc0aq9QbCrLXuNHZ/5pU0qc0F+Ei5uzVXxFySUXbARnbKyv5hTbrArvFapZOaMmwjbtrz 8RLSCVL9Qnfou5izTdOa4hKav7NesICNainTWqdpodCKWtkxT8bQ53OxeduLCJKuNIoSrMIGReBa GhPg9c7EbBT6JyRt+f6xq+wUpRfglM1MWhjSjQxbp9Dv+CURSXVmwjkbHx5+EZEzvU6UQM49uI6V pORDj0YtG0x/kRqnL4EIImoiq3DeF9BbksMqnvUZmCTqkB5NXQJeQfPU32pclSNO8F8fuMImIG3k tWtpyZP4mSdexDHj2bJ4oDYWk6Z0FpWn0eyFTU89ximBQ2c9DtRghrhkUZ0KxqauLaVenY6UBIJ4 dW/JAgkFxrlnihbKWOaGiH1nfIC4+dgN6MyBJaVaqxH5FQlPGcNR0cee21Uv793VWPL0oHbZuokH 4fYpVUaReDeqP8j5KBQBEhDYIT4EUMTVVbj7CopUEYhgj50ZIUUJXMXE0D49cPmobnJ3HoCf/0Al Y1yhTnV0Jhjro4ieC9FfHXMIegyxTWpa5nSGMJP3rpkFCzBGOBq8IiIBYS8sj0ji5/5JkZP9tVzu ZMJDGviMe+30FaFyHh8oB11s8c/lPW1HrupMRpdzR/4d+NjuN+pVkEonTc6N99QWGdmbok+NOfTv Ks9uYumKyMnE11XUSX/pMSvnFwboJ8caH9uQPnaWu2XXrwQiXyvU7KaaJE2KSmXQ2Yt28J3zmoLV EIJhYP0urrQACRbgVYaRz62zyDqE+gkh+v1g+hYM7d9vAHRUDIp81K/TvjCpeaofgoq3dSrS3g0q 1Ue06C5dWE5c8roP9eRCbJpDuSyrJrhbSVhXoSRWI5FYKLwFJRY8bfldTPpefcq/kmbQ56otvAot 9HDyb0mdRHvDCzZppzFbNDDsYN6pQCIp3+KP/qEEo3EHAEt6LcUQDy5UbfQJKrAs2o6Pg54lwIoL AvPXyq66Y2y/g/zaor7Kms+1LyRDIKaI31YISs2ZTh1TBMiHRCVBMjVMFL4fkB7PRzrFfGNahAJS Vpi5/h7owA67h/MoGEWQP5m6lFg1gzbLF7Um+CzaMAU4OU60kL48my3YxPtP90voe5NqKtyh4aBD g1HkZLlp9cjRM7qOPQzrXgphzNGd+5I8aa83WjUjrHAauxOdnpCRfevLTyYwjnsHtEcZX3vnu+zz Qlzn+HFwsqBgwBGoCnYOwMtecvTXR9ml+DJ6gYinZVOPHABxhAnt6NslCiVfeq5qcdLa8w+IXKU1 kK9N9ivr7UzerjQobYswj2ZsSf4M9oPHqw/pm0Fj2rAleqUheXVVNv7nIDuRQGApN3QT4WijpUaW FNXoY0AnclfXw09a2XVk6ICgURcXgkzfc+WNY4rYvkllM4A7tIy0KDVrxvL1lsjoybQkjx9+hH3U Uk+9MO5GOwduvMshY0wVuQMln+7ZETTnNbcykmiGZrzuaevXc+7azfWbxV2utDv8LesCoY3BZOj5 BKcEmOuYNLS6iiNrs+YRVZO/q8RkVeS3MCkQuvFFGAkASYECM+NpV0MceH08YtGnbsX1s3L50lvp 7VQBRr7T3R1HnnBmvyw2VU9QZ+eGaUJ8gEU3nPH24Nxl+rwQl63Rc+9QH7LSRN5s2SSpwtj7KUPx 1bqxVrsQYJvsgUpPDY3VPWCz6lsMwDUw6kK/PFrPYpfI4pGZwRSG6HFFYSTPxmIY/igBA+JH6nOv 2ZMuPpouutNWNfoU+CnccuJ15mWsSAD4BTbrRVhgUxW8IT6jNAKUzE2MGGbqs2PwoSPcsx8lmy03 OGNhii3zws+GtTdPrMl1KgPW2mMCqsQl5G2mrYEVB8G7IwnDEjXg2clLYsxQYHAMsnbkhPv6ybFb 9x63mNgrTEIfrn+78dz7FPuofc9KhkkF06rrH96B1bs5SoK59WYMdkh8t+FrLVRGLNmwCAMBkxQP iRGb8RTIENpfNNUZpuqX3yRM843xDhOGf9oMU6BO/VUS80xDpt3HxJlTIoLiVHKTCbd/o493jPvZ AbcsC4dQ6JrEVbZu1dqgPFEApanejqt7Ic4sbIlDmeOVtFO7kwdB3JnY+htkNDvfslNiKxvYZZuD ggPltzJpqlG4gKt1AhQXHXDnwrO9tZ4+IBJi+a1i2GpmCWjE4EeZLsU7UCWb8cfBvo70kfGPhKsn iTNrOU7BUCQpwGqfqE2TgYrgZc1+FurOoaErY7mrWy0iGLaOZYCLQ1wsxTdqgreTQYWTB2eceI5g qbN0AQuyF6XU10PLIhpTg0AElVT6pKl+vodzVH953IdQOo7c1TNwMjhNhOg9ECnsXvxgaTw1+MlC qXqbaA9F5aqgPiTowjU9tiCtKfaWNliw0LdXGiKlnROXSBzX7j5LW0LjJzWfDOR3HSY3jzwxDZBb wfmNA80DaN8qCZ9iWOm1hzyXdhlIkxmyZF0fHpBpgvKcCN/1OrUGLDUazzWvm/9nXk8JElMzsvIL oZ0JJpWMNqLeBRwHAeMblfIhx701OeWTNmXKUM6RlMDYxcjrE7lfHZ3ZH5PrNgDw9UqEqYhc1THU KHfCOEkLzo9DmlYfVoPgsRIfylNeC+BMbyR4yb/ZlKv3pLx2q5EFB99ZqCboGdstL5irlQgnW+5/ z8KUtPWFn1X9igOpLvJuBI8khYtDzm4GLBQEH+tL/D8Yzqm6R8cPtZXNTJqr5Qox2gVA6s+O5J5I xGB5c6rVwIUI1EIg9M3x3jMQ94W7pJN1/kXM6gSOOMTlQTrt6ADez6yyL33QaKauQC0CGrS1iv0t +clzq8TcgmnEnWbQVRbpAfEebcNrJPWJnLUUbsdRk03p79Yo2+dqCHqUG/mt331Nr+gWBbNcSflh yfflTiDFrNpIPNg7GEdK/IN5v8k1HMj/Atssmi2fMexc/mQc5gWRxNWVLshC8xoaaCIBXX1NL/hj be+l2MH/sAUc4hUqPLgHr8lf+B6SrjH0hIH/VPXv1IqNsxILP+IJm5otFrXBTyJ6Eul8Gr9vbHEH hPBTgPpZAja/3gWEkFw9ypMGaC3g6q58p0/f/fFR2uaVqa+m/XRfVybd/Hf9uc4E6Qe9WADERUNe Zm5d+IhuduRjlnPySjPzExzMJTfDoTDqw1daOhs00d0dy8TvIR/l4Y61wOwheKA9AKNyoc4CFs3y eZOH5P2Fr9fzC34B+L14czRD4RR+5kOx+Vs/NrhY5UR0Ha0Li73EHeFPa8xQuN7OPdWPuUd+k78M 15swYouKz6VI4FqEeRzhSE6nu4KIOPDUheZ/AIp3E7mZvLCvYfRoavWIKTCKaStQXESe6XUqibt6 6GszHom93Bhs+zeAwUK1ZP+ScV77DzLYIJ0PT1+wIhD5c6M4WUwZR7ulLNuUywEX8PcWYwNARl6J gGVkWAxx45W/dMkxbT8nrbIeTVi0tEggPmPcTD+j7pnyfqMb7Iqd/2dXey6a6uqLX+Edl0h4FdP1 jCVSmJxk81uUWYPeFVzh9iN6UKWn4ISuNx0f0mEqKDoxIkT0JkiJXwsGGFuYACWTkKY6sPgxiHjK Sl84O3Atfipfcp5gCPG9PjxPuuPrl5aTbLLA9oLIwTZg47CzqqjJTzhWyiLPgpKFXjw44ItK5d6C 6FNyjDlRi2/EYpikPhjdg2u/1BBBWJ4KvpRmLZ3xLyNtRtJ1P4/+nqyy46/P63fzPDYQOAavTbvV 0FPoEaRhxvuRTwHB/rQRc7wv1+UUjx/0SWVyHZxhRjpd/23W7zqcYnttPE7Y6T3t0T3MflUjivTv HeS38N9um7P2TIoVMxROuNFtzW3xKT82JmQog5lmEo+eDA9y7B6atZg0vt35JAED+e2N0hw/FmW5 7kr6n+STX+Oi5uWb3Tf65+UPtmyBxFCmK48E0XhbA2HGUQZLvnsORMcZD3k4i0odJVaU/QCF2XVd SRpIJv3G3AFX4uin5KStXUErb8tOe1SQ6CySDgJD9Fp/B/E4Cdo9JWC20tgYRdDptnyON9pAcDje GJ6KWWl77h6+y1wVcjAfy94EpANY8boZNPrNPZXOf7QS7ZPwdY3yA3xP1/tPaZ7zwpKRPPUzKGHl LV/GlfWilUJPdYFhziSKQEbr2c37a8EQqk52ofCUmuXDQK1nCUUrMSYr/Khm0ctsA5V3JEMIQDDv SILWpbSxdWWEmD9PiWoqAsnkMg9bIkpeEa73B7XUD04+kSZmVJ4V5wC5Xmr4CYcivdOaijmGBBK9 pgFaXm7yziinqIXlF7KPy07NpIsui193rTc9QOWwIWXD6lpFJs8GmuObD59AXvRV9Q+ve+BtlNj5 D3p5CWhrhLtYhWb0FPC8ETaX9WGAdP/VBXhLRxXSh8wpODiwRxID5xCT+69JJErHt6H6UnunyuQr QMMg3Xmb5YzlSZFaqqjWfxl+h8xL/wriCaLqSt7/EWPDBjpGq5y0dX3bdq3+m7Bt9JLbqp+APbdk JXVUMFoQIbJjg7aHggffgN8a+sXVkBBmAe24Kg2Aei6tOpq8kILhAqxQlgFD1+wxXTO5cUIR2rz+ sK6PPuz68gJPvNneDzIoueSmVriY3Wf4VFilvu7eF4vVAW/c+xHGexXGoOAKUD96dXKQ3u32Vg2D 0RE3HESdUy8bU9yKF9k+hSL31046kBWmFzPLZoBud9BX5xJJMcdvi7EyQSueYcclRVNqsQ9x5pKk c/LD3D1hjobG+aifrVz/VRLQ2/WZ78wmWHiV86N04892BgIHqhUzVJJQGGVQVMcjX1fFCoEAdFZT fA2jeNdQ33p/b3py4/XI/mct5axOq8wc5LUWPnMrUwhbfOzZDFi249F2tzzRgqUK8kXVzjoaeGmP fth/Di6ZY2PHmUqZBhLSX3EV/GxuAVBI3+uBmnwHElTZhZ5SQdKXozDFP6UgQtnaK0yw0e5BBipz UZ5s4bTDmmaAEezBMRFnosWFp8F08y60MfbmnqNxJgR8SnIbgkYe7BXCnGcbVd/pTxuhzYxSL2Yi 5loM66obFecjMZchRYaDdELyfVXqk8IPbiFKXINQnXfCxg9en76yAJ0SNplG+eO24dMCUVu6/aj0 b+ukCtHPwtOk4BXmBNzXRk12BXXOBbszslXRGJzq4NZTjcksdeZo70ltpkWu35Q5ze5AvI3QKyaa EAmYYf9Igknu4G8qJn6wzYkQ3ZGsMjJp0gsLGwJbANEPt5zHrg0rPKGy8NLNJJrQLEo9hoxZUUKv VKD5WNjdwlgVi4zFGZ30xj46qxxOMPnKyIb73K/PCCnyFr3lBdMNvCL58G6kGG7pg5qiqSO3hw+j qpyO66S7NHu+usw4b/89seUDmdyzz7k19abep4CwwcO5aF5KTCaWFluWFK6+VGXGxoMA0W7HXfDa 6xIGRp8yj+nKTYtQuOX5ZSta9ct54vwOwFKX0kOCP4h2I3HSeb/jPx4r2pAwzqWm/BTfIw0CtUPX DTqi9mlZ0gvblQKm/ARwcAx+6UCwubn2BihvuLLZ9B+i+Y1sz9l0Gud2aInu5/ipWh1MxtQLDprR CucDNEVNqz4Ph8HKD49u/Q+t4kNMSCj4nCGdBzzQzKLMRsTaEc9TlmnNWu6cJkUTGjCb3HofPsd6 wRpLI5tO22Mt2lgl7+d2jcyAMctiyjCsyjvsIOEMGfrVfRsoBcE3BadfHrA2edkosRLGlEXLgX2z YHHsZXHpBXEQpWJQr/G3EDJTEqqSO1vwllp28hbWmRiLCGosYFeYx7USobrGQvTc7zu6M0P0sOP2 3J/5FlD8SRIgBtK6qxRzJj/+/Hea0nrAJXWTteo13wv29/bEbrlhcA6Xjr2rWBKRvDDGFhRPWaNe 2fAAK25iPdKkLPc9oe2a66kEyBGiuyEig1/DgpkfLHVDkQRkr8Ooerzi60TBWHhCwoLTU2TV7O2Q M2ZUoEawkMzjTe/tK7Wh96zlcHoqsb8gjaNeV7wTGqPSJD0wVYnLqJ7+uu1sXFt0PsVNhmrn4yaL XOnw3H1LnHVC8WVo5rkYOHzaJSLhVWyP2SQao4sLp8pqG3+qG4QhsAu/aqQIMNSjtdGpecZFLkqX VknhvffKoz+DIksPWf4Tq9n9TwQjRP3ddq8mDvAfRCiwsTRCy1eFglQw4xQmN6I9i4FlUYfKdzeK /dzrKTJq0AjtvKDTQqdw03ksYQp2HEURYVPzQn21B9lxLQyUR+7mefZqZewG68WgFdXRUdjhZ+5b g972czfPc9KKTCdTJrOSlQmp0fCUUsvCOCuOJrNEI0er0eVSkC9GfgMs9OO1ra/hl0WVlHZfFTLt kXhmejlMjPEx5m7n4m1/Wcf5gRPficCT2X3fdBBWGBBtz9z4qmUMsCdK0KCypCpGA0Ej3C8+zCNr tdHoTwOAwWHQrsr8xjaOv/uySuyaB5A9YDQwvP9OV8cSNQgUCitAwlnCb15VwujqWdz6jujo9Vus SlStCVNXN/q6v3tL9eQFAnP5IAHLDaAzImhKynbiRTr9IOoGBJKYaxTMCC+dZdz+K/UykysxIb+/ UelCBz57pxMUvR1NEVPeo5HNGVgsWRZRhqx76xPef8RApICE0dpn/Hlh0oBKLim2Pr0uW0AwX8lq r3Bv9wtI0scj90454cpxcwAA4+t8GjPTb4AiLi/9xaFzlGr2cOMr9GIkU460JTDidn55Mv+rm//F /Rt6Z3Eaj/TuMMjCNQmNGkfA9GwbsWVZe/LI+ijzIPac7/EIHXrP9VsASmfsBjF44I8GTmIYgeV0 jdpjWn04yrJJvpCi1dpgYJm8gKCaAJg3opUJKTUmDmW7zcszqBIgTIx81y6hcQQNKBQvod5sEP70 04KK7jJZdOP6zprBpQNfpFwpdtv9vFAywb2sl0mI+HLvVCDc5SG47wjpjgG4nn/NG4Eesyyp964V 7GiFbawLzMEMlQyCvO35kQjRWGsU6stO5bLTPBnBhv3cW4z1hHHx0XPBQvduHjhkyLrpErvPpXuz eZXhK+DBsGgMJkas9OaBBgIQ8/fvjYtbV+BWoALk5TmDTmA2uFJuZjdvgrPfaU20GUzRGKmrKGbG 6OTCx0JbuYzQKrmc7/HIsmbMIbz725EcwypP5cX/avjT8pexnBXjNHYgWO3S6/wp8UZY0mCi8SsZ rXWFaktd17YYG/LXCu9+Cz23m3IR94IRU37js/xhWKOaJLOsb5Pbz7hOwbChLvCtJGMNC6pUO0g/ 6zQmk2ygt3gw3D1o7xMNIVXW6n0uMpBC1bzwYnUYw83ESSp8CeuiJaml3LwrYKefR2JBxbM076KG ZEHWtDogw2fTB6BjkEjUFcJgSrtq7v1M1ZRorrAcTEFfs1oBNCUBmxtrKf4kh0Xb5jXtic8hyBxy KCai2mzYRDR6lxtRNw904t16NaaMi0yHFJKZO274ELViQRGjTnjmOLtwaR2Mv9ERb+eQ5tjEfumi JiMnpSXhEkjlrBGqN7Vtsg3zLEyBUt5/kZ2reFWtEw6iSJaWbPMqUl2IHLmb7lyHXIko3skU2iwk mAl70zgkJNv/a4RcZoUvq2OY9qAZtevVzlq6YLtRbGr4deH4gtYhSlCgIutX0F0gcwvD0aKUaZn1 cQZJch+Eyr/WYV5wUUTlR8YuclYd8p5obqhVgPPzPvIncvzMNpYsKoZRlwNqrkO3s/HsoztMmBzH IdR2MipYEPOclOk/eMDfnGL2/xapw67/bWWDOu4hv++frJuAnLKjJhc0Hznx2IL3WUOvl1YjHLG1 fc9HWLnwLjN7FEFmriKTePDyO9qVTavZqvQyCKDQEXyhUojsQzGJ8REGiJVjtBbsYMhyW09A4qLC lwHCguzOp8YrAcuJlmJmBmujXhBqICXoz8Rr0ukiysjhWINR5Suekthna4/fKRujSrmLwQ6QkBAi wCcmNJondvSGtdDhOoYvYXd2w4DYl+vQiwqX9x5b9HkK1XnRf25EAnzg1sJvcWBC3RG+PEQk8B83 fOGLJOSFzTVXNP0nz3eSxUg7QDhWMPMvOZ1qnScZf204vh2kSnwXb5NOFT+G28UkfBPW7j1JA7pA O2F/nOUIgLMHvQX2A2j2UPQrWDhEFQPcHOItCNPpBxhQ/cqKrvLorY2iYpEci7VH2GqGu2x/2B12 H/FJ1Xq6F8nksIzrKyHgbAAPCfLGjOtxF6mJCT2MM85DyIL8mAIbRqhQsPM0zxeJ9cW3yCCoAAld dGmAK7uZEPDGcav38eW9G4+8oWTL29AAdnyXnL05OMMqSo3I7QbKtttf/G7i6RgGMPAsTaDuYWyq C1ARLc2wJw55+PsQ28Hqur6kdqvhypIKPXFFy1Cu3tp1VpeXRxO7zq/LNsa2KAN20f20JdqtYPzW c7KNo8V8SXQWZEvsFv90VrNshGOGxzeYXQcXA5ZLIVa9L0i58LiGaUFrYBDMEduevl4Q8AqBXHlB iUiUxPWoCfGSGeE7XYmKjDOC2h0y9wvJqV1w1qQU6VA/JiHTEhvK47dmRYcGFC0ZiMDIbiWczixU v+iLS18FD8vrLK89GzkAoY1baFRg7hzdF6oi0NzQLw3JHgP+BKxhmfjPmxggKGotN452Ev+TiLGk 2elkKOhfdCSZqGmw7slLGJW0x87Y2RnDXEbtvzDE+d8sPa62Nah8OMCfOkYYz3d85p1yAQKPGenj AN9/ZZUd5aMBl8DL+SKe7p/XoGMrbnF2SlgX0BvpDSWknx3OlZJDRJQehbc8WKPMBuHpER9nzU2v ZSewtmZPl8NjJhnLwm+DQXdHNQtoF3+WJQKfWSSJTxDrBgbvd1hDma2LeSwlUf5B8qr623MKvFWX gbDy598O3R5RXIjktth8LRv4Z/osFsjYhXKrFDJfdkhFMEgZ5l1V5BwHBDSokIgOAdGN8N/5Qlkv MCNUO2SdZ+z/WIevW3aalSgXKiqns8ZiKOE0gQfTXj+HdoB/ZFTjssgrKXwOcoA/y/p9DHLWjc1z JQyy/pOQL6x9YoZfQaf7lynHhztdQlQAui7uNu/Bdw1qSQSJZUnC1GVCZvZRXrmXU0D0cVGk9P5E ToPKjwEfvOFOIMzlCNYY9/tOImas7g2lRXafAPa3AZSFO+VZmObtQpP7GvuoVkSyAutTbWCWKLTH 8szDT/3kumiM5SErDKiUBhEO0Yg+ahw94qHWMuniLgErhAXuMP3rMd9yz62rAEBBKU70aSD94YY9 DgDw23wAaL//HMjJuffm7RrIIW4tF+dT+WllxQLJU/HMb9STgIEirxeZO9QFr5KKcnrRYKl1yze9 csLa/H3gSY58yM2k9rC13ZjTTy9r1BEF/MEP6aTBxgSMkl7fjDcTmeP58sMad8/a4eLEg6QjY3Wi 3TSgF/ernqh2p/pMzIivCWuC90YoWINon4IH+VR2vp+wiXJ4E2zKOkwUyh2pnERF4bgTLwAORxPc LebgqXSKSiUJGHjIoD3tJRobve2Yjn9CHV3KA+bR2NKZHC/TZ4BnzW50H4PvHOjDHC83LgZWkOD8 95ELh9sqMP+ejfaXox2kbMptD1oj4SjlwLiwafe6U5cQoqeXOQgKsbthmoPDxmGx+O9qsdw3OjCM CLtw4HW26bOHPfbd7J1Oe3BBXriYyFUM+yIoiQuhZ4FEPHbEXb5a+uxe4dAXHEAwTzzse43izXsa WB3BraDFhu0MAIpHsCIt7tFQo01UumVuJ7iAYHxe8WFEUrBtzVhAipP23R/ih4Zt7FMAZ2enrH6o V2LRbXftDP6khEFzOxxxEBfpEz62XjvLqv8tFaP3xZTrOo8S4kZkVPhMfl+H1MVtEEh8uRjaXWRd BeTGZC8yO5DmnNJY7cQdnJpHm9r+fc/WDzerLrRoIdvoaFtr2+ePAfV6vw4gsxzx7Rq0NTeVtYP+ 0sMvMwzI/CBe7bOF1WKSW84RxbgP9w+ykNAlJ+C4knnICPUaZVAqEoPxPCodrRG4GaTqLMovdIxw H1xIOQBtc0noLF4fzG0Q+JQ1S38YS0nJxJnv6x9BdqfEu/FZvDATRHAZZ5yEidtr3WQQemNAlcrM W5YXJ3T+BoUVfV3VUVfx6GamPjClp73VADQjKXqBw4r43l5BsK6hidUcqsXs8w86BxHla2ejLY2F jEwhc7B5xyd9bdOLUNUCLAcxkW4CXCf8Z1q0ULtphsk+4ku/PGMRv5zgvQsPlN5PzqsRG0mw7xyV 5PeOKIIKYI61qlbj25PuTc3eef9jhMYndd80r3X3ZYxBlyYXeE5wZje0owUk5ibKdX+xVfNSaGLR mMNZK2OTRFUjYKK2p2PUEURwzq1sMGe/dBY2YJxEJVmDmReiFujrzyG2AKziGIQvblouXVCIKaqU a8I5xPosV0B5KxyPn7nO3U4m8a4Bnrsd1KJEuCgP6MmIyL3ayMo73r2+2HXHQIMeLqKxeaxhfx5d NaHIsPRhebDE2fG96XkU/82Ftn+zQs0saA/3I/rwzvgnOn3v33VhSJ6x71EIQX3B2ZGvKQoE47Dw +JR+sMpIqoGXoR/qAXUXGofFxvM4um2foOt996es4+/hGDBflawGUHS3oJpTnBn9RjdQnUvhjxUi hgSa17/HAY05mSeTxp2s/gAeqHuH6Yj1osTw6ZHPjpB4uVheiptnZeN+m3p84qhBBFGogvC9JM0s WKN0oG6UpcVXbaykxebvSuKO9QSyFNLKw1drA6qK1E2zGVP1u491FDnf9x48kBmBzyrpV9b4z+ol 44C8QtqxNDS/7EoKyFG70LS/Umxyh+U4U38WxJWcyiZMahTQ0OAnyLba8mfw1v5T0PEI2AQZG8RA Uren/IVS66rETSjj6ykVtcfCCTD0oAiIjL3Mrw+ehi2kiW+hWqw8OVuzuUxymOuGlhIkR/n+KGJY 2SLjzWKmq9+LQsATR47KQWoB4M1oXW4Br+jXmjZEvds5z66hWUHyunW09bahf7INEmhSQffgQpYt bo9VFr2v0i4Y7KZ7B8q48EXtcmoLpY6rrgHUDQAhYDG7dVBfxorAz00kV5icTa9UcAoEw/qyatwH 5Jal83kwczDPXrq0rRteFwh2UJNwQ6u0Fkhn0aIDcwpCo1efPUAH2BOYOwpY+I87aCxUUA7wxpwu 2Y/19NQ1kwY9hv/MamTDoyZWJuBSpspqjqfakEl+SzzKcrJ+6yUPD99nVogmvO2r0MFF0drWmbhh M7l6C28wta9j0HY3EoBFw8Mkwsp1mX1CpTlhOos5ye90J9SNjRYpOrzQK+1C5DwimRob8/K9A4hi 8wdEA6aRGHuSH3vlDpc= `protect end_protected	mit	6893f32e97b894fe1d24571eab361386	0.936397	1.884698	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set.vhd	1	31,018	------------------------------------------------------------------------------- -- axi_datamover_stbs_set.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_stbs_set.vhd -- -- Description: -- This file implements a module to count the number of strobe bits that -- are asserted active high on the input strobe bus. This module does not -- support sparse strobe assertions. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_stbs_set.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 6/20/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added 512 and 1024 data width support -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_stbs_set is generic ( C_STROBE_WIDTH : Integer range 1 to 128 := 8 -- Specifies the width (in bits) of the input strobe bus. ); port ( -- Input Strobe bus ---------------------------------------------------- -- tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); -- ------------------------------------------------------------------------ -- Asserted Strobes count output --------------------------------------- -- num_stbs_asserted : Out std_logic_vector(7 downto 0) -- -- Indicates the number of asserted tstrb_in bits -- ------------------------------------------------------------------------ ); end entity axi_datamover_stbs_set; architecture implementation of axi_datamover_stbs_set is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function ------------------------------------------------------------------- -- Function -- -- Function Name: funct_8bit_stbs_set -- -- Function Description: -- Implements an 8-bit lookup table for calculating the number -- of asserted bits within an 8-bit strobe vector. -- -- Note that this function assumes that asserted strobes are -- contiguous with each other (no sparse strobe assertions). -- ------------------------------------------------------------------- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed Variable lvar_num_set : Integer range 0 to 8 := 0; begin case strb_8 is ------- 1 bit -------------------------- when "00000001" \| "00000010" \| "00000100" \| "00001000" \| "00010000" \| "00100000" \| "01000000" \| "10000000" => lvar_num_set := 1; ------- 2 bit -------------------------- when "00000011" \| "00000110" \| "00001100" \| "00011000" \| "00110000" \| "01100000" \| "11000000" => lvar_num_set := 2; ------- 3 bit -------------------------- when "00000111" \| "00001110" \| "00011100" \| "00111000" \| "01110000" \| "11100000" => lvar_num_set := 3; ------- 4 bit -------------------------- when "00001111" \| "00011110" \| "00111100" \| "01111000" \| "11110000" => lvar_num_set := 4; ------- 5 bit -------------------------- when "00011111" \| "00111110" \| "01111100" \| "11111000" => lvar_num_set := 5; ------- 6 bit -------------------------- when "00111111" \| "01111110" \| "11111100" => lvar_num_set := 6; ------- 7 bit -------------------------- when "01111111" \| "11111110" => lvar_num_set := 7; ------- 8 bit -------------------------- when "11111111" => lvar_num_set := 8; ------- all zeros or sparse strobes ------ When others => lvar_num_set := 0; end case; Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH)); end function funct_8bit_stbs_set; -- Constants Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED; -- Signals signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0'); begin --(architecture implementation) num_stbs_asserted <= sig_stbs_asserted; sig_strb_input <= tstrb_in ; ------------------------------------------------------------------------- ---------------- Asserted TSTRB calculation logic --------------------- ------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_1_STRB -- -- If Generate Description: -- 1-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate begin ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_1BIT_STRB -- -- Process Description: -- -- ------------------------------------------------------------- IMP_1BIT_STRB : process (sig_strb_input) begin -- Concatonate the strobe to the ls bit of -- the asserted value sig_stbs_asserted <= "0000000" & sig_strb_input(0); end process IMP_1BIT_STRB; end generate GEN_1_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_2_STRB -- -- If Generate Description: -- 2-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate signal lsig_num_set : integer range 0 to 2 := 0; signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0'); begin lsig_strb_vect <= sig_strb_input; ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_2BIT_STRB -- -- Process Description: -- Calculates the number of strobes set fo the 2-bit -- strobe case -- ------------------------------------------------------------- IMP_2BIT_STRB : process (lsig_strb_vect) begin case lsig_strb_vect is when "01" \| "10" => lsig_num_set <= 1; when "11" => lsig_num_set <= 2; when others => lsig_num_set <= 0; end case; end process IMP_2BIT_STRB; sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set, BITS_FOR_STBS_ASSERTED)); end generate GEN_2_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_4_STRB -- -- If Generate Description: -- 4-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0'); begin lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector -- for the function call sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect), BITS_FOR_STBS_ASSERTED)); end generate GEN_4_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_8_STRB -- -- If Generate Description: -- 8-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0'); begin lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector -- for the function call sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect), BITS_FOR_STBS_ASSERTED)); end generate GEN_8_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_16_STRB -- -- If Generate Description: -- 16-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate Constant RESULT_BIT_WIDTH : integer := 8; signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0'); begin lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector -- for the function call lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector -- for the function call lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ; lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ; lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH); sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total); end generate GEN_16_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_32_STRB -- -- If Generate Description: -- 32-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate Constant RESULT_BIT_WIDTH : integer := 8; signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0'); begin lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector -- for the function call lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector -- for the function call lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector -- for the function call lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector -- for the function call lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ; lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ; lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ; lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ; lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH); sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total); end generate GEN_32_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_64_STRB -- -- If Generate Description: -- 64-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate Constant RESULT_BIT_WIDTH : integer := 8; signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0'); begin lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector -- for the function call lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector -- for the function call lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector -- for the function call lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector -- for the function call lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector -- for the function call lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector -- for the function call lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector -- for the function call lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector -- for the function call lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ; lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ; lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ; lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ; lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ; lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ; lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ; lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ; lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH); sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total); end generate GEN_64_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_128_STRB -- -- If Generate Description: -- 128-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate Constant RESULT_BIT_WIDTH : integer := 8; signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0'); begin lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector -- for the function call lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector -- for the function call lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector -- for the function call lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector -- for the function call lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector -- for the function call lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector -- for the function call lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector -- for the function call lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector -- for the function call lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector -- for the function call lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector -- for the function call lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector -- for the function call lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector -- for the function call lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector -- for the function call lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector -- for the function call lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector -- for the function call lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector -- for the function call lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ; lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ; lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ; lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ; lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ; lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ; lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ; lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ; lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ; lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ; lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ; lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ; lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ; lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ; lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ; lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ; lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH); sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total); end generate GEN_128_STRB; end implementation;	bsd-2-clause	a62f262c9a70673cb1e231f99dafce7e	0.441518	4.467521	false	false	false	false
Jorge9314/ElectronicaDigital	Impresora2D/TB_Reception_8bits.vhd	1	3,946	LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY TB_Reception_8bits IS END TB_Reception_8bits; ARCHITECTURE behavior OF TB_Reception_8bits IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Reception_8bits PORT( Divisor_Frecuencia : IN std_logic; Entrada : IN std_logic; Mensaje : OUT std_logic_vector(7 downto 0); Confirmado : OUT std_logic ); END COMPONENT; --Inputs signal Divisor_Frecuencia : std_logic := '0'; signal Entrada : std_logic := '0'; --Outputs signal Mensaje : std_logic_vector(7 downto 0); signal Confirmado : std_logic; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name constant Divisor_Frecuencia_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Reception_8bits PORT MAP ( Divisor_Frecuencia => Divisor_Frecuencia, Entrada => Entrada, Mensaje => Mensaje, Confirmado => Confirmado ); -- Clock process definitions Divisor_Frecuencia_process :process begin Divisor_Frecuencia <= '0'; wait for Divisor_Frecuencia_period/2; Divisor_Frecuencia <= '1'; wait for Divisor_Frecuencia_period/2; end process; -- Stimulus process stim_proc: process begin -- IDLE -- Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; -- BIT DE INICIO -- Entrada <= '0'; wait for 20 ns; -- BIT Numero 1 -- Entrada <= '1'; wait for 20 ns; -- 2 Entrada <= '1'; wait for 20 ns; -- 3 Entrada <= '1'; wait for 20 ns; -- 4 Entrada <= '1'; wait for 20 ns; -- 5 Entrada <= '1'; wait for 20 ns; -- 6 Entrada <= '1'; wait for 20 ns; -- 7 Entrada <= '1'; wait for 20 ns; -- 8 Entrada <= '1'; wait for 20 ns; -- BIT DE PARIDAD -- Entrada <= '0'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- IDLE -- Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; -- BIT DE INICIO -- Entrada <= '0'; wait for 20 ns; -- BIT Numero 1 -- Entrada <= '0'; wait for 20 ns; -- 2 Entrada <= '1'; wait for 20 ns; -- 3 Entrada <= '0'; wait for 20 ns; -- 4 Entrada <= '1'; wait for 20 ns; -- 5 Entrada <= '0'; wait for 20 ns; -- 6 Entrada <= '1'; wait for 20 ns; -- 7 Entrada <= '0'; wait for 20 ns; -- 8 Entrada <= '1'; wait for 20 ns; -- BIT DE PARIDAD -- Entrada <= '0'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- IDLE -- Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; -- BIT DE INICIO -- Entrada <= '0'; wait for 20 ns; -- BIT Numero 1 -- Entrada <= '1'; wait for 20 ns; -- 2 Entrada <= '1'; wait for 20 ns; -- 3 Entrada <= '1'; wait for 20 ns; -- 4 Entrada <= '1'; wait for 20 ns; -- 5 Entrada <= '1'; wait for 20 ns; -- 6 Entrada <= '1'; wait for 20 ns; -- 7 Entrada <= '1'; wait for 20 ns; -- 8 Entrada <= '1'; wait for 20 ns; -- BIT DE PARIDAD -- Entrada <= '1'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait; end process; END;	gpl-3.0	2d1d646577e6823ba86404ef107aee49	0.502281	3.366894	false	false	false	false
spzSource/MPFSM.RegFile.Sort	MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/Controller.vhd	1	8,076	library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use commands.all; -- -- Holds interaction among ROM, RAM and datapath. -- entity Controller is port( clk : in std_logic; rst : in std_logic; start : in std_logic; stop : out std_logic; rom_enabled : out std_logic; rom_address : out std_logic_vector(7 downto 0); rom_data_output : in std_logic_vector(27 downto 0); ram_read_write : out std_logic; ram_write_data_port : out std_logic_vector(7 downto 0); ram_write_address : out std_logic_vector(7 downto 0); ram_read_data_port_1 : in std_logic_vector(7 downto 0); ram_read_data_port_2 : in std_logic_vector(7 downto 0); ram_read_address_1 : out std_logic_vector(7 downto 0); ram_read_address_2 : out std_logic_vector(7 downto 0); datapath_enabled : out std_logic; datapath_operation_code : out std_logic_vector(3 downto 0); datapath_operand_1 : out std_logic_vector(7 downto 0); datapath_operand_2 : out std_logic_vector(7 downto 0); datapath_result : in std_logic_vector(7 downto 0); datapath_zero_flag : in std_logic; datapath_significant_bit_flag : in std_logic ); end entity Controller; architecture Controller_Behavioural of Controller is type states is ( IDLE, FETCH, DECODE, READ, WRITE, ADD, SUB, HALT, JUMP_IF_ZERO, JUMP_IF_NOT_SIGN_BIT_SET, LOAD_FROM_INDEX_TO, LOAD_FROM_INDEX_TO_READ_ADDR, LOAD_ACCEPT_WRITE, LOAD_TO_INDEX_FROM, LOAD_TO_INDEX_FROM_READ_ADDR ); signal next_state : states; signal current_state : states; signal instruction : std_logic_vector(27 downto 0); signal instruction_counter : std_logic_vector(7 downto 0); signal operation : std_logic_vector(3 downto 0); signal operand_address_1 : std_logic_vector(7 downto 0); signal operand_address_2 : std_logic_vector(7 downto 0); signal result_address : std_logic_vector(7 downto 0); signal data_1 : std_logic_vector(7 downto 0); signal data_2 : std_logic_vector(7 downto 0); signal data_w : std_logic_vector(7 downto 0); constant DEFAULT_COUNTER_VALUE : std_logic_vector(7 downto 0) := (instruction_counter'range => '0'); constant DEFAULT_INSTRUCTION_VALUE : std_logic_vector(27 downto 0) := (instruction'range => '0'); constant DEFAULT_OPERATION_VALUE : std_logic_vector(3 downto 0) := (operation'range => '0'); constant DEFAULT_ADDRESS_VALUE : std_logic_vector(7 downto 0) := (operand_address_1'range => '0'); begin FSM : process(clk, rst, next_state) begin if (rst = '1') then current_state <= IDLE; elsif rising_edge(clk) then current_state <= next_state; end if; end process; FSM_COMB : process(current_state, start, operation) begin case current_state is when IDLE => if (start = '1') then next_state <= FETCH; else next_state <= IDLE; end if; when FETCH => next_state <= DECODE; when DECODE => if (operation = HALT_OP) then next_state <= HALT; elsif (operation = JZ_OP) then next_state <= JUMP_IF_ZERO; elsif (operation = JNSB_OP) then next_state <= JUMP_IF_NOT_SIGN_BIT_SET; else next_state <= READ; end if; when READ => if (operation = ADD_OP) then next_state <= ADD; elsif (operation = SUB_OP) then next_state <= SUB; elsif (operation = LOAD_FROM_INEDEX_TO_ADDR_OP) then next_state <= LOAD_FROM_INDEX_TO; elsif (operation = LOAD_FROM_ADDR_TO_INDEX_OP) then next_state <= LOAD_TO_INDEX_FROM; else next_state <= IDLE; end if; when LOAD_FROM_INDEX_TO => next_state <= LOAD_FROM_INDEX_TO_READ_ADDR; when LOAD_TO_INDEX_FROM => next_state <= LOAD_TO_INDEX_FROM_READ_ADDR; when LOAD_FROM_INDEX_TO_READ_ADDR \| LOAD_TO_INDEX_FROM_READ_ADDR => next_state <= LOAD_ACCEPT_WRITE; when ADD \| SUB \| LOAD_ACCEPT_WRITE => next_state <= WRITE; when WRITE \| JUMP_IF_ZERO \| JUMP_IF_NOT_SIGN_BIT_SET => next_state <= FETCH; when HALT => next_state <= HALT; when others => next_state <= IDLE; end case; end process; -- -- multiplexer to handle stop signal; -- STOP_PROCESS : process(current_state) begin if (current_state = HALT) then stop <= '1'; else stop <= '0'; end if; end process; -- -- synchronous instruction counter -- INSTR_COUNTER : process(clk, rst, current_state) begin if (rst = '1') then instruction_counter <= DEFAULT_COUNTER_VALUE; elsif falling_edge(clk) then if (current_state = DECODE) then instruction_counter <= instruction_counter + 1; elsif (current_state = JUMP_IF_ZERO and datapath_zero_flag = '1') then instruction_counter <= operand_address_1; elsif (current_state = JUMP_IF_NOT_SIGN_BIT_SET and datapath_significant_bit_flag = '0') then instruction_counter <= operand_address_1; end if; end if; end process; rom_address <= instruction_counter; ROM_READ_SET : process(next_state, current_state) begin if (next_state = FETCH or current_state = FETCH) then rom_enabled <= '1'; else rom_enabled <= '0'; end if; end process; -- -- reads instructions from the ROM -- ROM_READ : process(rst, current_state, rom_data_output) begin if (rst = '1') then instruction <= DEFAULT_INSTRUCTION_VALUE; elsif (current_state = FETCH) then instruction <= rom_data_output; end if; end process; -- -- determines the states of registers (address and instruction), -- based on current state of FSM -- REGS_CONTROL : process(rst, next_state, instruction) begin if (rst = '1') then operation <= DEFAULT_OPERATION_VALUE; operand_address_1 <= DEFAULT_ADDRESS_VALUE; operand_address_2 <= DEFAULT_ADDRESS_VALUE; result_address <= DEFAULT_ADDRESS_VALUE; elsif (next_state = DECODE) then operation <= instruction(27 downto 24); operand_address_1 <= instruction(23 downto 16); operand_address_2 <= instruction(15 downto 8); result_address <= instruction(7 downto 0); elsif (next_state = LOAD_FROM_INDEX_TO) then operand_address_1 <= data_1; elsif (next_state = LOAD_TO_INDEX_FROM) then operand_address_2 <= data_2; elsif (next_state = LOAD_TO_INDEX_FROM_READ_ADDR) then result_address <= operand_address_2; end if; end process; RAM_ADDR_SET : process(operand_address_1, operand_address_2, result_address) begin if (current_state /= JUMP_IF_NOT_SIGN_BIT_SET and current_state /= JUMP_IF_ZERO) then ram_read_address_1 <= operand_address_1; ram_read_address_2 <= operand_address_2; ram_write_address <= result_address; end if; end process; RAM_MODE_SET : process(current_state) begin if (current_state = WRITE) then ram_read_write <= '0'; else ram_read_write <= '1'; end if; end process; RAM_DATA_OUT : process(current_state) begin if (current_state = READ) then data_1 <= ram_read_data_port_1; data_2 <= ram_read_data_port_2; elsif (current_state = LOAD_FROM_INDEX_TO_READ_ADDR) then data_1 <= ram_read_data_port_1; end if; end process; ram_write_data_port <= datapath_result; datapath_operand_1 <= data_1; datapath_operand_2 <= data_2; datapath_operation_code <= operation; DATAPATH_SET : process(current_state) begin if (current_state = ADD or current_state = SUB or current_state = LOAD_ACCEPT_WRITE) then datapath_enabled <= '1'; else datapath_enabled <= '0'; end if; end process; end architecture Controller_Behavioural;	mit	aa1921cf7377b2f1df66af087b6d5b0f	0.61788	3.167059	false	false	false	false
Yarr/Yarr-fw	rtl/kintex7/rx-core/gearbox32to66.vhd	1	2,153	-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: RX channel -- # Aurora style rx code -- #################################### library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity gearbox32to66 is port ( -- Sys connect rst_i : in std_logic; clk_i : in std_logic; -- Input data32_i : in std_logic_vector(31 downto 0); data32_valid_i : in std_logic; slip_i : in std_logic; -- Outoput data66_o : out std_logic_vector(65 downto 0); data66_valid_o : out std_logic ); end gearbox32to66; architecture rtl of gearbox32to66 is signal gearbox_cnt : unsigned(7 downto 0); signal shift_cnt : std_logic; signal buffer128 : std_logic_vector(127 downto 0); signal slip_cnt : std_logic; begin shift_proc: process(clk_i, rst_i) begin if (rst_i = '1') then buffer128 <= (others => '0'); gearbox_cnt <= (others => '0'); data66_valid_o <= '0'; data66_o <= (others => '0'); shift_cnt <= '0'; slip_cnt <= '0'; elsif rising_edge(clk_i) then data66_valid_o <= '0'; if (data32_valid_i = '1') then shift_cnt <= not shift_cnt; buffer128(127 downto 0) <= buffer128(95 downto 0) & data32_i; data66_o <= buffer128(128-(to_integer(gearbox_cnt(4 downto 0))2)-1 downto 62-(to_integer(gearbox_cnt(4 downto 0))2)); if (shift_cnt = '1') then if (slip_i = '1') then gearbox_cnt <= gearbox_cnt; data66_valid_o <= '1'; elsif (gearbox_cnt = 32) then gearbox_cnt <= (others => '0'); data66_valid_o <= '0'; else gearbox_cnt <= gearbox_cnt + 1; data66_valid_o <= '1'; end if; end if; end if; end if; end process shift_proc; end rtl;	gpl-3.0	d8754e737856a86a4574addde67fc6d6	0.471435	3.71848	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/instantiation/rule_031_test_input.vhd	1	545	architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : component INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : COMPONENT INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;	gpl-3.0	440c69315cb811f4185a4c8823bf5a72	0.486239	2.809278	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_queue.vhd	1	53,845	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ********************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library proc_common_v4_0; use proc_common_v4_0.sync_fifo_fg; use proc_common_v4_0.srl_fifo_f; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_queue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_INCLUDE_MM2S : integer range 0 to 1 := 0; C_INCLUDE_S2MM : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- s_axis_updt_aclk : in std_logic ; -- -- --****************************-- -- -- Control and Status -- -- --****************************-- -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- updt2_active : in std_logic ; -- updt2_queue_empty : out std_logic ; -- updt2_ioc : out std_logic ; -- updt2_ioc_irq_set : in std_logic ; -- -- dma2_interr : out std_logic ; -- dma2_slverr : out std_logic ; -- dma2_decerr : out std_logic ; -- dma2_interr_set : in std_logic ; -- dma2_slverr_set : in std_logic ; -- dma2_decerr_set : in std_logic ; -- -- --****************************-- -- -- Update Interfaces In -- -- --****************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- s_axis2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis2_updtptr_tvalid : in std_logic ; -- s_axis2_updtptr_tready : out std_logic ; -- s_axis2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis2_updtsts_tvalid : in std_logic ; -- s_axis2_updtsts_tready : out std_logic ; -- s_axis2_updtsts_tlast : in std_logic ; -- -- --****************************-- -- -- Update Interfaces Out -- -- --*****************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_queue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_queue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs -- Number of words deep fifo needs to be. Depth required to store 2 word -- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2 --constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE 2); constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2)); -- Width of fifo rd and wr counts - only used for proper fifo operation constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1); -- Select between BRAM or LOGIC memory type constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16); -- Number of words deep fifo needs to be. Depth required to store all update -- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * C_SG_WORDS_TO_UPDATE)); constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * C_SG2_WORDS_TO_UPDATE)); -- Select between BRAM or LOGIC memory type constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16); -- Select between BRAM or LOGIC memory type constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16); -- Width of fifo rd and wr counts - only used for proper fifo operation constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_lsb_sm : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal write_curdesc_lsb1 : std_logic := '0'; signal write_curdesc_msb1 : std_logic := '0'; signal rden_del : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_d2 : std_logic := '0'; signal updt_active_re1 : std_logic := '0'; signal updt_active_re2 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; -- State Machine Signal signal writing_status : std_logic := '0'; signal dataq_rden : std_logic := '0'; signal stsq_rden : std_logic := '0'; -- Pointer Queue FIFO Signals signal ptr_queue_rden : std_logic := '0'; signal ptr_queue_wren : std_logic := '0'; signal ptr_queue_empty : std_logic := '0'; signal ptr_queue_full : std_logic := '0'; signal ptr_queue_din : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ptr_queue_dout : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ptr_queue_dout_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); -- Status Queue FIFO Signals signal sts_queue_wren : std_logic := '0'; signal sts_queue_rden : std_logic := '0'; signal sts_queue_din : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts_queue_dout : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0'); signal sts_queue_full : std_logic := '0'; signal sts_queue_empty : std_logic := '0'; signal ptr2_queue_rden : std_logic := '0'; signal ptr2_queue_wren : std_logic := '0'; signal ptr2_queue_empty : std_logic := '0'; signal ptr2_queue_full : std_logic := '0'; signal ptr2_queue_din : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ptr2_queue_dout : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); -- Status Queue FIFO Signals signal sts2_queue_wren : std_logic := '0'; signal sts2_queue_rden : std_logic := '0'; signal sts2_queue_din : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts2_queue_dout : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts2_queue_full : std_logic := '0'; signal sts2_queue_empty : std_logic := '0'; signal sts2_queue_empty_del : std_logic := '0'; signal sts2_dout_valid : std_logic := '0'; signal sts_dout_valid : std_logic := '0'; signal sts2_dout_valid_del : std_logic := '0'; signal valid_new : std_logic := '0'; signal valid_latch : std_logic := '0'; signal valid1_new : std_logic := '0'; signal valid1_latch : std_logic := '0'; signal empty_low : std_logic := '0'; -- Misc Support Signals signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; signal writing_status_re_ch1 : std_logic := '0'; signal writing_status_re_ch2 : std_logic := '0'; signal sinit : std_logic := '0'; signal updt_tvalid : std_logic := '0'; signal updt_tlast : std_logic := '0'; signal updt2_tvalid : std_logic := '0'; signal updt2_tlast : std_logic := '0'; attribute mark_debug of updt_tvalid : signal is "true"; attribute mark_debug of updt2_tvalid : signal is "true"; attribute mark_debug of updt_tlast : signal is "true"; attribute mark_debug of updt2_tlast : signal is "true"; signal status_d1, status_d2 : std_logic := '0'; signal updt_tvalid_int : std_logic := '0'; signal updt_tlast_int : std_logic := '0'; signal ptr_queue_empty_int : std_logic := '0'; signal updt_active_int : std_logic := '0'; signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0'); attribute mark_debug of follower_reg_mm2s : signal is "true"; signal follower_full_mm2s :std_logic := '0'; signal follower_empty_mm2s : std_logic := '0'; signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0'); attribute mark_debug of follower_reg_s2mm : signal is "true"; signal follower_full_s2mm :std_logic := '0'; signal follower_empty_s2mm : std_logic := '0'; signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0); signal follower_full :std_logic := '0'; signal follower_empty : std_logic := '0'; signal sts_rden : std_logic := '0'; signal sts2_rden : std_logic := '0'; signal follower_tlast : std_logic := '0'; signal follower_reg_image : std_logic := '0'; signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1' else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ; m_axis_updt_tvalid <= updt_tvalid when updt_active = '1' else updt2_tvalid; m_axis_updt_tlast <= updt_tlast when updt_active = '1' else updt2_tlast; m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0'; m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0'; -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- channel 1 updt_active_re <= updt_active_re1 or updt_active_re2; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active_re, ptr_queue_empty_int, m_axis_updt_tready, updt_tvalid_int, updt_tlast_int) begin write_curdesc_lsb_sm <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; dataq_rden <= '0'; stsq_rden <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if(updt_active_re = '1')then pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor pointer -- Reads one word from data queue fifo --------------------------------------------------------------- when READ_CURDESC_LSB => -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(ptr_queue_empty_int = '0')then write_curdesc_lsb_sm <= '1'; dataq_rden <= '1'; -- pntr_ns <= READ_CURDESC_MSB; pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB; else -- coverage off pntr_ns <= READ_CURDESC_LSB; -- coverage on end if; --------------------------------------------------------------- -- Get upper current descriptor -- Reads one word from data queue fifo --------------------------------------------------------------- -- when READ_CURDESC_MSB => -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. -- if(ptr_queue_empty_int = '0')then -- dataq_rden <= '1'; -- write_curdesc_msb <= '1'; -- pntr_ns <= WRITE_STATUS; -- else -- -- coverage off -- pntr_ns <= READ_CURDESC_MSB; -- -- coverage on -- end if; --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => -- De-MUX appropriage tvalid/tlast signals writing_status <= '1'; -- Enable reading of Status Queue if datamover can -- accept data stsq_rden <= m_axis_updt_tready; -- Hold in the status state until tlast is pulled -- from status fifo if(updt_tvalid_int = '1' and m_axis_updt_tready = '1' and updt_tlast_int = '1')then -- if(follower_full = '1' and m_axis_updt_tready = '1' -- and follower_tlast = '1')then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; -- coverage off when others => pntr_ns <= IDLE; -- coverage on end case; end process CURDESC_PNTR_STATE; updt_tvalid_int <= updt_tvalid or updt2_tvalid; updt_tlast_int <= updt_tlast or updt2_tlast; ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else ptr2_queue_empty when updt2_active = '1' else '1'; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate begin MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate updt_tvalid <= follower_full_mm2s and updt_active; updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active; sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active; VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then -- follower_reg_mm2s <= (others => '0'); follower_full_mm2s <= '0'; follower_empty_mm2s <= '1'; else if (sts_rden = '1') then -- follower_reg_mm2s <= sts_queue_dout; follower_full_mm2s <= '1'; follower_empty_mm2s <= '0'; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE; VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then follower_reg_mm2s <= (others => '0'); else if (sts_rden = '1') then follower_reg_mm2s <= sts_queue_dout; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE1; REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active; end if; end if; end process REG_ACTIVE; updt_active_re1 <= updt_active and not updt_active_d1; -- I_UPDT_DATA_FIFO : entity proc_common_v4_0.srl_fifo_f -- generic map ( -- C_DWIDTH => 32 , -- C_DEPTH => 8 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => ptr_queue_wren , -- Data_In => ptr_queue_din , -- FIFO_Read => ptr_queue_rden , -- Data_Out => ptr_queue_dout , -- FIFO_Empty => ptr_queue_empty , -- FIFO_Full => ptr_queue_full, -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then ptr_queue_dout <= (others => '0'); elsif (ptr_queue_wren = '1') then ptr_queue_dout <= ptr_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or ptr_queue_rden = '1') then ptr_queue_empty <= '1'; ptr_queue_full <= '0'; elsif (ptr_queue_wren = '1') then ptr_queue_empty <= '0'; ptr_queue_full <= '1'; end if; end if; end process; -- Channel Pointer Queue (Generate Synchronous FIFO) -- I_UPDT_STS_FIFO : entity proc_common_v4_0.srl_fifo_f -- generic map ( -- C_DWIDTH => 34 , -- C_DEPTH => 4 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => sts_queue_wren , -- Data_In => sts_queue_din , -- FIFO_Read => sts_rden, --sts_queue_rden , -- Data_Out => sts_queue_dout , -- FIFO_Empty => sts_queue_empty , -- FIFO_Full => sts_queue_full , -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then sts_queue_dout <= (others => '0'); elsif (sts_queue_wren = '1') then sts_queue_dout <= sts_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or sts_rden = '1') then sts_queue_empty <= '1'; sts_queue_full <= '0'; elsif (sts_queue_wren = '1') then sts_queue_empty <= '0'; sts_queue_full <= '1'; end if; end if; end process; -- Channel Status Queue (Generate Synchronous FIFO) --*************************************** -- Channel Data Port Side of Queues --*************************************** -- Pointer Queue Update - Descriptor Pointer (32bits) -- i.e. 2 current descriptor pointers and any app fields ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- Data Queue Write Enable - based on tvalid and queue not full ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid and not ptr_queue_full; -- Data Queue NOT Full -- Drive channel port with ready if room in data queue s_axis_updtptr_tready <= not ptr_queue_full; --************************************* -- Channel Status Port Side of Queues --*************************************** -- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits) -- Note: Type field is stripped off sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- Status Queue Write Enable - based on tvalid and queue not full sts_queue_wren <= s_axis_updtsts_tvalid and not sts_queue_full; -- Drive channel port with ready if room in status queue s_axis_updtsts_tready <= not sts_queue_full; --********************************* -- SG Engine Side of Queues --*********************************** -- Indicate NOT empty if both status queue and data queue are not empty -- updt_queue_empty <= ptr_queue_empty -- or (sts_queue_empty and follower_empty and updt_active); updt_queue_empty <= ptr_queue_empty or follower_empty_mm2s; -- and updt_active); -- Data queue read enable ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable and ptr_queue_empty = '0' -- Data Queue NOT empty and updt_active = '1' else '0'; -- Status queue read enable sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status and sts_queue_empty = '0' -- Status fifo NOT empty and updt_active = '1' else '0'; ----------------------------------------------------------------------- -- TVALID - status queue not empty and writing status ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- TLAST - status queue not empty, writing status, and last asserted ----------------------------------------------------------------------- -- Drive last as long as tvalid is asserted and last from fifo -- is asserted end generate MM2S_CHANNEL; NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate begin updt_active_re1 <= '0'; updt_queue_empty <= '0'; s_axis_updtptr_tready <= '0'; s_axis_updtsts_tready <= '0'; sts_queue_dout <= (others => '0'); sts_queue_full <= '0'; sts_queue_empty <= '0'; ptr_queue_dout <= (others => '0'); ptr_queue_empty <= '0'; ptr_queue_full <= '0'; end generate NO_MM2S_CHANNEL; S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate begin updt2_tvalid <= follower_full_s2mm and updt2_active; updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active; sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active; VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then -- follower_reg_s2mm <= (others => '0'); follower_full_s2mm <= '0'; follower_empty_s2mm <= '1'; else if (sts2_rden = '1') then -- follower_reg_s2mm <= sts2_queue_dout; follower_full_s2mm <= '1'; follower_empty_s2mm <= '0'; end if; end if; end if; end process VALID_REG_S2MM_ACTIVE; VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then follower_reg_s2mm <= (others => '0'); else if (sts2_rden = '1') then follower_reg_s2mm <= sts2_queue_dout; end if; end if; end if; end process VALID_REG_S2MM_ACTIVE1; REG2_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_active_d2 <= '0'; else updt_active_d2 <= updt2_active; end if; end if; end process REG2_ACTIVE; updt_active_re2 <= updt2_active and not updt_active_d2; -- I_UPDT2_DATA_FIFO : entity proc_common_v4_0.srl_fifo_f -- generic map ( -- C_DWIDTH => 32 , -- C_DEPTH => 8 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => ptr2_queue_wren , -- Data_In => ptr2_queue_din , -- FIFO_Read => ptr2_queue_rden , -- Data_Out => ptr2_queue_dout , -- FIFO_Empty => ptr2_queue_empty , -- FIFO_Full => ptr2_queue_full, -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then ptr2_queue_dout <= (others => '0'); elsif (ptr2_queue_wren = '1') then ptr2_queue_dout <= ptr2_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or ptr2_queue_rden = '1') then ptr2_queue_empty <= '1'; ptr2_queue_full <= '0'; elsif (ptr2_queue_wren = '1') then ptr2_queue_empty <= '0'; ptr2_queue_full <= '1'; end if; end if; end process; APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate begin I_UPDT2_STS_FIFO : entity proc_common_v4_0.srl_fifo_f generic map ( C_DWIDTH => 34 , C_DEPTH => 12 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => sinit , FIFO_Write => sts2_queue_wren , Data_In => sts2_queue_din , FIFO_Read => sts2_rden, Data_Out => sts2_queue_dout , FIFO_Empty => sts2_queue_empty , FIFO_Full => sts2_queue_full , Addr => open ); end generate APP_UPDATE; NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate begin process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then sts2_queue_dout <= (others => '0'); elsif (sts2_queue_wren = '1') then sts2_queue_dout <= sts2_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or sts2_rden = '1') then sts2_queue_empty <= '1'; sts2_queue_full <= '0'; elsif (sts2_queue_wren = '1') then sts2_queue_empty <= '0'; sts2_queue_full <= '1'; end if; end if; end process; end generate NO_APP_UPDATE; -- Pointer Queue Update - Descriptor Pointer (32bits) -- i.e. 2 current descriptor pointers and any app fields ptr2_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- Data Queue Write Enable - based on tvalid and queue not full ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid and not ptr2_queue_full; -- Data Queue NOT Full -- Drive channel port with ready if room in data queue s_axis2_updtptr_tready <= not ptr2_queue_full; --************************************* -- Channel Status Port Side of Queues --*************************************** -- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits) -- Note: Type field is stripped off sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- Status Queue Write Enable - based on tvalid and queue not full sts2_queue_wren <= s_axis2_updtsts_tvalid and not sts2_queue_full; -- Drive channel port with ready if room in status queue s_axis2_updtsts_tready <= not sts2_queue_full; --********************************* -- SG Engine Side of Queues --*********************************** -- Indicate NOT empty if both status queue and data queue are not empty updt2_queue_empty <= ptr2_queue_empty or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active); -- Data queue read enable ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable and ptr2_queue_empty = '0' -- Data Queue NOT empty and updt2_active = '1' else '0'; -- Status queue read enable sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status and sts2_queue_empty = '0' -- Status fifo NOT empty and updt2_active = '1' else '0'; end generate S2MM_CHANNEL; NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate begin updt_active_re2 <= '0'; updt2_queue_empty <= '0'; s_axis2_updtptr_tready <= '0'; s_axis2_updtsts_tready <= '0'; sts2_queue_dout <= (others => '0'); sts2_queue_full <= '0'; sts2_queue_empty <= '0'; ptr2_queue_dout <= (others => '0'); ptr2_queue_empty <= '0'; ptr2_queue_full <= '0'; end generate NO_S2MM_CHANNEL; end generate GEN_Q_FOR_SYNC; -- FIFO Reset is active high sinit <= not m_axi_sg_aresetn; -- LSB_PROC : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' )then -- write_curdesc_lsb <= '0'; -- -- Capture lower pointer from FIFO or channel port -- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then write_curdesc_lsb <= write_curdesc_lsb_sm; -- end if; -- end if; -- end process LSB_PROC; --***************************************************************** -- POINTER CAPTURE LOGIC --******************************************************************* ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else ptr_queue_dout; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- updt_active_int <= updt_active or updt2_active; REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1' and updt_active_int = '1')then updt_curdesc(63 downto 32) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then --elsif(write_curdesc_msb = '1' and updt_active_int = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --***************************************************************** -- ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; writing_status_re_ch1 <= writing_status_re and updt_active; writing_status_re_ch2 <= writing_status_re and updt2_active; ----------------------------------------------------------------------- -- Caputure IOC begin set ----------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re_ch1 = '1')then -- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active; updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re_ch1 = '1')then --dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active; dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re_ch1 = '1')then -- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active; dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re_ch1 = '1')then -- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active; dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; ----------------------------------------------------------------------- -- Caputure IOC begin set ----------------------------------------------------------------------- REG_IOC2_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then updt2_ioc <= '0'; elsif(writing_status_re_ch2 = '1')then -- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active; updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC2_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then dma2_interr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active; dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT2_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then dma2_slverr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active; dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV2_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then dma2_decerr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active; dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC2_ERROR; end implementation;	bsd-2-clause	fb0861b80792293beb48c1a83d196805	0.434079	4.280547	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sts_strm.vhd	1	38,384	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sts_strm.vhd.vhd -- Description: This entity is the AXI Status Stream Interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sts_strm is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32; -- Slave AXI Status Stream Data Width C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_ENABLE_SKID : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- s2mm_rxlength_valid : out std_logic ; -- s2mm_rxlength_clr : in std_logic ; -- s2mm_rxlength : out std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- stsstrm_fifo_rden : in std_logic ; -- stsstrm_fifo_empty : out std_logic ; -- stsstrm_fifo_dout : out std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); -- -- -- Stream to Memory Map Status Stream Interface -- s_axis_s2mm_sts_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_sts_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_sts_tvalid : in std_logic ; -- s_axis_s2mm_sts_tready : out std_logic ; -- s_axis_s2mm_sts_tlast : in std_logic -- ); end axi_dma_s2mm_sts_strm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sts_strm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Status Stream FIFO Depth constant STSSTRM_FIFO_DEPTH : integer := 16; -- Status Stream FIFO Data Count Width (Unsused) constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal fifo_full : std_logic := '0'; signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); signal fifo_wren : std_logic := '0'; signal fifo_sinit : std_logic := '0'; signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_cdc_from : std_logic := '0'; signal rxlength_valid_trdy : std_logic := '0'; --signal sts_tvalid_re : std_logic := '0';-- CR565502 --signal sts_tvalid_d1 : std_logic := '0';-- CR565502 signal sts_tvalid : std_logic := '0'; signal sts_tready : std_logic := '0'; signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sts_tlast : std_logic := '0'; signal m_tvalid : std_logic := '0'; signal m_tready : std_logic := '0'; signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_tlast : std_logic := '0'; signal tag_stripped : std_logic := '0'; signal mask_tag_write : std_logic := '0'; --signal mask_tag_hold : std_logic := '0';-- CR565502 signal skid_rst : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Primary Clock is synchronous to Secondary Clock therfore -- instantiate a sync fifo. GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate signal s2mm_stop_d1 : std_logic := '0'; signal s2mm_stop_re : std_logic := '0'; signal sts_rden : std_logic := '0'; signal follower_empty : std_logic := '0'; signal fifo_empty : std_logic := '0'; signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); begin -- Generate Synchronous FIFO -- I_STSSTRM_FIFO : entity proc_common_v4_0.sync_fifo_fg -- generic map ( -- C_FAMILY => C_FAMILY , -- C_MEMORY_TYPE => USE_LOGIC_FIFOS, -- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH , -- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_READ_DEPTH => STSSTRM_FIFO_DEPTH , -- C_PORTS_DIFFER => 0, -- C_HAS_DCOUNT => 1, --req for proper fifo operation -- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH, -- C_HAS_ALMOST_FULL => 0, -- C_HAS_RD_ACK => 0, -- C_HAS_RD_ERR => 0, -- C_HAS_WR_ACK => 0, -- C_HAS_WR_ERR => 0, -- C_RD_ACK_LOW => 0, -- C_RD_ERR_LOW => 0, -- C_WR_ACK_LOW => 0, -- C_WR_ERR_LOW => 0, -- C_PRELOAD_REGS => 1,-- 1 = first word fall through -- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through -- -- C_USE_EMBEDDED_REG => 1 -- 0 ; -- ) -- port map ( -- -- Clk => m_axi_sg_aclk , -- Sinit => fifo_sinit , -- Din => fifo_din , -- Wr_en => fifo_wren , -- Rd_en => stsstrm_fifo_rden , -- Dout => stsstrm_fifo_dout , -- Full => fifo_full , -- Empty => stsstrm_fifo_empty , -- Almost_full => open , -- Data_count => open , -- Rd_ack => open , -- Rd_err => open , -- Wr_ack => open , -- Wr_err => open -- -- ); I_UPDT_STS_FIFO : entity proc_common_v4_0.srl_fifo_f generic map ( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, C_DEPTH => 16 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => fifo_sinit , FIFO_Write => fifo_wren , Data_In => fifo_din , FIFO_Read => sts_rden, --sts_queue_rden , Data_Out => fifo_out, --sts_queue_dout , FIFO_Empty => fifo_empty, --sts_queue_empty , FIFO_Full => fifo_full , Addr => open ); sts_rden <= (not fifo_empty) and follower_empty; stsstrm_fifo_empty <= follower_empty; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then follower_empty <= '1'; elsif (sts_rden = '1') then follower_empty <= '0'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1') then stsstrm_fifo_dout <= (others => '0'); elsif (sts_rden = '1') then stsstrm_fifo_dout <= fifo_out; end if; end if; end process; fifo_sinit <= not m_axi_sg_aresetn; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write; sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif((sts_tvalid_re = '1' and tag_stripped = '0') -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; end if; end if; end process REG_RXLENGTH; s2mm_rxlength_valid <= rxlength_valid_cdc_from; s2mm_rxlength <= rxlength_cdc_from; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- register stop to create re pulse REG_STOP : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then s2mm_stop_d1 <= '0'; else s2mm_stop_d1 <= s2mm_stop; end if; end if; end process REG_STOP; s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1; skid_rst <= not m_axi_sg_aresetn; ENABLE_SKID : if C_ENABLE_SKID = 1 generate begin --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => m_axi_sg_aclk , ARST => skid_rst , skid_stop => s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate ENABLE_SKID; DISABLE_SKID : if C_ENABLE_SKID = 0 generate begin sts_tvalid <= s_axis_s2mm_sts_tvalid; s_axis_s2mm_sts_tready <= sts_tready; sts_tdata <= s_axis_s2mm_sts_tdata; sts_tkeep <= s_axis_s2mm_sts_tkeep; sts_tlast <= s_axis_s2mm_sts_tlast; end generate DISABLE_SKID; end generate GEN_SYNC_FIFO; -- Primary Clock is asynchronous to Secondary Clock therfore -- instantiate an async fifo. GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate ATTRIBUTE async_reg : STRING; signal s2mm_stop_reg : std_logic := '0'; -- CR605883 signal p_s2mm_stop_d1_cdc_tig : std_logic := '0'; signal p_s2mm_stop_d2 : std_logic := '0'; signal p_s2mm_stop_d3 : std_logic := '0'; signal p_s2mm_stop_re : std_logic := '0'; --ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true"; begin -- Generate Asynchronous FIFO I_STSSTRM_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord generic map( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 , -- C_DEPTH => STSSTRM_FIFO_DEPTH , -- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH , C_DEPTH => 15 , C_CNT_WIDTH => 4 , C_USE_BLKMEM => USE_LOGIC_FIFOS , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => fifo_sinit , AFIFO_Wr_clk => axi_prmry_aclk , AFIFO_Wr_en => fifo_wren , AFIFO_Din => fifo_din , AFIFO_Rd_clk => m_axi_sg_aclk , AFIFO_Rd_en => stsstrm_fifo_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => stsstrm_fifo_dout , AFIFO_Full => fifo_full , AFIFO_Empty => stsstrm_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); fifo_sinit <= not p_reset_n; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid -- valid data and not fifo_full -- fifo has room and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length and not mask_tag_write; -- not masking off tag word sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- -- elsif(sts_tvalid_re = '1' -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate signal rxlength_clr_d1_cdc_tig : std_logic := '0'; signal rxlength_clr_d2 : std_logic := '0'; signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_d1_cdc_to : std_logic := '0'; signal rxlength_valid_d2_cdc_from : std_logic := '0'; signal rxlength_valid_d3 : std_logic := '0'; signal rxlength_valid_d4 : std_logic := '0'; signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0'; ATTRIBUTE async_reg : STRING; --ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true"; begin -- Double register from secondary clock domain to primary S2P_CLK_CROSS : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_rxlength_clr, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_clr_d2, scndry_vect_out => open ); -- S2P_CLK_CROSS : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0')then -- rxlength_clr_d1_cdc_tig <= '0'; -- rxlength_clr_d2 <= '0'; -- else -- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr; -- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig; -- end if; -- end if; -- end process S2P_CLK_CROSS; -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes TRDY_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0' or rxlength_clr_d2 = '1')then rxlength_valid_trdy <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_valid_trdy <= '1'; end if; end if; end process TRDY_RXLENGTH; REG_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; elsif (rxlength_valid_d2_back = '1') then rxlength_valid_cdc_from <= '0'; end if; end if; end process REG_RXLENGTH; SYNC_RXLENGTH : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_d2_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_back, scndry_vect_out => open ); -- SYNC_RXLENGTH : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then -- -- rxlength_valid_d1_back_cdc_to <= '0'; -- rxlength_valid_d2_back <= '0'; -- else -- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from; -- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to; -- -- end if; -- end if; -- end process SYNC_RXLENGTH; -- Double register from primary clock domain to secondary P2S_CLK_CROSS : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_cdc_from, scndry_vect_out => open ); P2S_CLK_CROSS2 : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => rxlength_cdc_from, scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => rxlength_d2 ); P2S_CLK_CROSS1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then -- rxlength_d1_cdc_to <= (others => '0'); -- rxlength_d2 <= (others => '0'); -- rxlength_valid_d1_cdc_to <= '0'; -- rxlength_valid_d2_cdc_from <= '0'; rxlength_valid_d3 <= '0'; else -- rxlength_d1_cdc_to <= rxlength_cdc_from; -- rxlength_d2 <= rxlength_d1_cdc_to; -- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from; -- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to; rxlength_valid_d3 <= rxlength_valid_d2_cdc_from; end if; end if; end process P2S_CLK_CROSS1; process (m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_valid_d4 <= '0'; elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then rxlength_valid_d4 <= '1'; end if; end if; end process; s2mm_rxlength <= rxlength_d2; -- s2mm_rxlength_valid <= rxlength_valid_d2; s2mm_rxlength_valid <= rxlength_valid_d4; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- CR605883 -- Register stop to provide pure FF output for synchronizer REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_stop_reg <= '0'; else s2mm_stop_reg <= s2mm_stop; end if; end if; end process REG_STOP; -- double register s2mm error into primary clock domain REG_ERR2PRMRY : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_stop_reg, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => p_s2mm_stop_d2, scndry_vect_out => open ); REG_ERR2PRMRY1 : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then -- p_s2mm_stop_d1_cdc_tig <= '0'; -- p_s2mm_stop_d2 <= '0'; p_s2mm_stop_d3 <= '0'; else --p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883 -- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg; -- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig; p_s2mm_stop_d3 <= p_s2mm_stop_d2; end if; end if; end process REG_ERR2PRMRY1; p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3; skid_rst <= not p_reset_n; --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => axi_prmry_aclk , ARST => skid_rst , skid_stop => p_s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate GEN_ASYNC_FIFO; end implementation;	bsd-2-clause	30086459e8a880da5bd4391d6b4a4bb6	0.447035	4.017164	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_v8_0.vhd	2	19,382	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block aCVHNLRL8soMwgirb4igYdy+w/d8MsAkGS3ESRMsTr07DnKVy3RTnJ9RtYLA3I+MFSh681EbheGN wOr9xTxo0A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YjKX7hHDAbMBc5ZteypfutOS5A5c7hVUrYY6mAWpruKdPwT/ntU77uwBhl7ztC9b3c1NBILLEc0J gsIfTEXoisdQQgLcohRsNQCnpSTvaSYmrN0bK5pNGe8DfSB5DqW2RcqlVXa9LlZYu7uc9FiTA41V s5HCQJEnh3DQy8T69Uc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tIQpokMnxX0wpy7fRnd/O1KwmW5fUadWhs/fWcCyduFMy+bJWWMADfVSuYd7YlnybyCzRyFNBiS3 SelCP1dTXOz7RUqRvBmLTUj7lt7j8p8ZwjUfLA35leKw8lFAup4iKpOR8P2MqmcPaSsHKRddXKRs nmQZB6b/RPUVYEmctonzrMwzgpugn+0WszmI/iqshfLwuegkWo2rdcfYcHEiX8Bm34zlRSjMTg55 NHZBq3cJxKEM/1Vb4I7O98CB+W+5E+RZmURDyZOkC20AR5a7jN5MMwgSxsOIH25aXazBbJS/RaIg alPkkcH/HmQviV25uIFcSRFm0r2b84uS5liNZA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Ij2w24zZEehSJgByNgalrX9zQ/FmZgkUvva63ww5wYDd7xg7Z2tNw/jR3Uq3T8DDG8+EuGauv6OZ wzZjF8PP/sXDW8XwQiz+PpGp0gJjzHoHcFwcQDqkm4k1WgMCxjjeOeYQzZZMMqhcjCsa95NNz9+r qYBVJFxDHVw7IcB/s5E= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XQe9uXZHQ8tuqq/muDjCfWPpeZbVoAuLjnw9oD51W9b8XgYuPumUg6XDfkoWoUvgDhUj0nX+JohN AEVeYKieJr6Ybdjt4lEQgvwBv9jovxOo72D67DEgxx4Xu1nEUvg+yBbWrm32WCnWTrRU231EIX8q Gu9olP8WEYAX3Fi4p6XewkVc0Moa0lqEpXmHuOPRygzvnVAIiM31MMSaMIt4JiCDs7f/qbqzrftZ s+erAHXMB1oGtybnkTUmhVPG4PeqBE3jcx6mWqKlR9Dl42XhbpfqIfIR6HGPuFcuJ1p03eA0p0ZV qhN1M4rdey0jf2i6KA1schp0TrfeUfKEGbhDAg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608) `protect data_block BsHbM8W7kNfkoYsutF02xo3+pujCXiH0Ip/JIvnJqewlPhPQ+exF8cWK/SsSuN6zmRBH9MyyR4pX ghsiKvu43f6uXljfjBJ3Z+c51Nk8WJmzg8BgKNC9AleJcIQZwAyryM7KVM8P4IiU1LwjMxXnuduN yK46XJ/88Uk7hFTr8spku0H0FpxhO+QcyHjYECJJhGrPvZCCLr8bOZC8KkWWs02QUXWsZr76x32Y vVzdRlQpb/CjfyMtaXMs5WngCcKHDlXYBwPYUggLXhEAYhTa0RAHnXv35HsxW8YcZk5YXpozbKGr cKcsrbMR6Md8NZR90KsvuANqDa2eY7SRVifIjzNdEu15+1AGIDn9AyzcY86B4dzCAjjWRpc3cvLB EEk7jc5vJ1MwD2aqz49g0lf7W0y6qepan2ucUqWCLpUoWOQOJITt2Hqp7UHheO68JjvbXa/IfeZD RYgSclUAocjzkN0cWPTiZtg5SbyYSefoSZttuNyPHwBJBvorlbArezdGimsasUa44YN443V4fmEw 4vvEWE8drnXgxgnsQSu/Kuy0ExjsL+Dfu+P82D4nW9kCTIMalU84UpLXgtxe5SayklU9xHam8xeG +WAW4/knwPYqVaG+YPBfD7oB+ZdXsO9edBORs7PiF5SlF/r7z8I8ksrnmJ7ghQSf/pgQag2MnxVR Pgv1qkC/EypiRURCs3ym/H/m6vrBm5NA6fhsfvay8AUL/oQHSVItnlp7xcDiErnj8+8J3H10CBOE TTS2SMDXZmSVfjU0+VUqmmXK25K0zRkkmXOsVv3zB7buxkw4WEPQIb3XW5399tE9r0NUoGJaeugO 7pGfzVnQ1L/gM/pwLvNFg5iOGVPbfmyEMCBIym9kpVHd7a7K7urNCa2H2gK0MW0UGiJMGeL2J1mu eyqLumPz8M3GzvjSiUvuaZpc6ak54Icz1NWcL3cW0sj6x71ib31/5eHIMg+oweHkTvPe00DILK70 4+BJju+wM5QJOzo+1HJZj2IoEe2SCkQKBrbA8P7Pg8T66oBW1x0sfSDOx4kd970VcDwQiwCrolra +7cqXODlfCIH7ebcVsV9d3UsG1iHmtmTJsAIRt3HI6Cn1qv2dgtv7MC6rSW3tz5IYqcDLPKRD7I5 zuNooC+jB2iUCRn3jWr/PoQmE3bY+bqBmIILfHaxvrG9AUvxqSk5EakAJqQ+oPGuUuodHeZDkfqH 89tfWMh8gGUwFsgXH0IDrhldCcW6t054OJ04c+oJGhgWwopkhzGXDRc3NJ9G69FrFx1Hq2+foE7j yijR5FwLlKg7UOWFpz7q38pQBHmYjhjmrG/M8d60jtuO8dK5x0z5NSNLekL+HmRIkXCeDCgP89w/ emXgvlYWiPsI3AlM8d/x8avyrhB/TLod90D744ouTNiTwfA3FTb8O98yJnysMIhr8vlqO4PiOpkx PUdnTvSSgHLmHjwTzrMr9gJExT8M8zhAw3N58Q+3Fp+n1S/L001wcwjSEErp3XxWjJS5Q7nxYShP 9+PZRBOBAFYXtATvvM9WDl90VGLcqRgU0pU72y1tEOubpSea4ulq9qQbvTEoW1VoxaSads4xdTGg cnTiwDHQ4SjlK6zCC0g1uAIe7xJdx44LdCxoEXmGu2lnXq1DzBz29WgJoC67wXK5V/lsypZrxJb8 5bW9BJTjlh87Gc8KW46qtId9jXuE5kWDParniX76p33qFKRLqm4caAyKxRblFihGtOZVZY4hccp6 Pg74UviBTeDL+UheOEHFZeyrm85nWop/0GW4XAHGch/BNjcf1xU5k6ciQS/X7fibBKX46BgbTlK6 wvFSSlgyfaJPWEvjRKhUyDizGDrGxOHTJFmZw0axJ4JCmv1vnMHZK5HP07zbMoEn5JM7qmY/r4Ub RvZxLj8RiST0oV0/9kCj5O+uAKFAhrkNo5hYpVxNooG4bgqHD4fK/Di1VTvE+SFa2kJAZvvA1K81 rUslxEcUyb+G8YAcnFE3PHZX1UlsCtDUVms9IBaFApm7OlycMb3ruNDy+wkbKkEtPuxuVR7gvn5I bUHDnFh7jQEd6G0hQrVgfnBtSRROx1kPW94xudln65x5onkHeyAGtJdBfc+jRvsZZ9FcdaJLKsUK ylBX+Pu5D9YTNLc4WMwjP2JkJ2U8/MWsG4nmU2rUrRHmDFLJQeZVxcCb70v77xJH2yuX65g2z3m+ KsOfecoX5Bz3RhsV8mCpHmPzRG7oHpvAQb6G3pqOZRhXYJ9LkcRiJtV1dxlCzXAsduYr2RKpQWa6 Hpp7O7qpnTsnGkjTCMWmEeobkFQLB1yI4vB9n5QXQZpoFGHWO/+PZo1beXVESshlktt6Lu2HQTfs uP1nxmwdleev5iG2VqHjJe+xc+e57/Wb/7SBoj0fNErwDOf0R1G8/z+8yDm4r7jz2dzyxfHefzos awYTpYUshypnQdeMOONODUHVhjG4blUcQHAoi6Qc8ORZf0X+TOWRLHClQOMnZUJUrY+9sBBehyTl Ajlz+IEzWJLtTbp+VwRKfS4avzrboBhoImn58v1cxe8mfG3UM3BVyEujn1P6vc+uGRzoUxleaTxT VVg9OCrGQFpukmw8HDc/y0kscuT61NYNYFJzxFmkE7DTwLkt9QZfLaVksJBjh8nt0VjAvXfJ9x24 2TEEnyhFtRhF1HR6RxrdZP7kUVbXGoH0RQhQhFRVpfLiPWKIAIolYu2h4R7DzCwXXSM5uEpvbWME kJ4Dm9KXP0g/Pq3Fo4IWJxMYI7rbLttVOVR0oaRN+9muUELa3LhVe/qm4OHB2t/TeaaYZB0uPPNL TdsSAXm88SzXnDQei7JgSikG97BjBXhJWCzuu1DH7aiOcLBXgprVTFn+WkoYP64wgAkgrLpo/VC1 iTmEzS9dg4gkmb2h++xNhIfDz8J5Yypz6b/VixYaUO3aUSKLlT+Lfz/TLI2mgPtbyuW83pDQwx5+ 3C7C3znRzlRntA/qjb4JVyl01KwtnmE8S9A7t6VryU0OFp36vXI1ed2MzYfLh09BMyTj5KKsA2Pz Ub09lzAnLb710lUzVmHLuwShxgvhDRZqIVd3x1veajUYvf+kBYoOwISaVmb/bqV9knqOi+hW+PnE MO0pWgDcJ6HWA6RQjD61b3ZgIA4YCl42frS9eUeeyEU9Z96OqE5tgK7BbXRpsVu78RklNZdZP96l GNCoY5FJcRYTfVzESBoRTwccDOAYJ07Jo6rQqayHivV84/S0u2DmG7xo/dzPRMqVGKwpSgT1kvJA sO2IeILrPwl2I1bk/td4CX81k5NiyrETXnbDQsH6hiZ4bsfCQs37Snl3pI9mcZzUq990CU8w/NZn O0Ls3bbrtZfKHB5LQSgXF1L4kci89/WKz8EqBeWkEJ/arohzGqyKOn58fpGSEtUz1QxIJSkn0n/R 4sVgcbu5tuCulOOjEEg2Yn+mwVIaQHouTbs+ivwSNVkIjOaHnyKvloUJ/Ob4UQTqIf6s7Mw0Xvt2 TJHsWzpDT7tmefonp4XPghL/sNgGhLpMb22fKeYpktmVEOYb1zVrUXxXXY43s/253XqASCR75esM WLIO2Y71tRfsIUkBZbj4hlRvhUWUdfZKt3FugPVq0dQWypgcjryx/hEBA7MWaw4omo3q7UHzVyDP /pHkCKuQIzz0Vp/zfgCLKL1NmwY/cN83Jse+Uo9A2KFmO4iHUgLns16YFs3jx1mWksFGmg35xEYI 0SfsCboYzeqOqE6O3kTwFXoy8FkOrWaksbeF9KaKoz9dWc+mjzNRnkwRb3+cvukEOMEGkhSlqp18 CZVGDOxmB8Q8Dm+k9Ahq06KHgCVIIKH354bNdNJBAt1MdkOY0Hd+iEDARDpKNCcV/Y9LrQbzOF5z 8B9Wm/67opOT3TtyH7G/gkDjvGcwDqycm2xHqYZBVDjjTMPCatSwQoWs/QzIVoOzculL8nrxuE5O Ke5Cnw58w69aTGsxFGWnn60eMcCCB5e93dcpnwsuJmiYiC+SUORG+Vsfnmpm78yqm1QNJhz4Hw6O HcWmx4Vh292Z6iNeq3bBdnXxJYc84WuKLot8wVWmDn3m6xHrOwcfkB7fZI6ts5NaChMxpvMIRcfv Xk8fMQuqTrsRvqFxACbdLnY6T56lgJPviXtv6fZK4mUKmf++atYyY08QUHNRv5Z8XrKhqb2hrTh4 qAGsOKZocT5qYPff49cHE6Bnh0luLkl8YVC1XHwWTL3wEVGeTvJFR8OvoP6gM92671ba+oXFlEa5 tSq44Dyw+S2RCW5EDKsirpz+NtD2GcRHHakjpbYv3eSJTTEmd94SzZVMXe2rCCZhEnIchD8bwrfN QXuNmT3Ed/SkxKEzbzUgcRdfo1vxYq0475k9soH7WMb9FX5Ya9jTCOVEXjEKU25XEx6xRIPtTCn6 3sVhIq3oPkwAMat/Dbt/TGtKFMmh8rmX94gohlgJE5Au43+UhfL5Z3dHby+QTj75tvndi4Wh0iyy Wyvxisrde608k6am9MXd7YRFOeHGJhnmGv9VUXFYA1W48m4cOlnIiqlyaAF9PvROCVPYMEVeXGEM BYcFblU2Utcdq5wrU39xCr7l12oLczpL5XqVEiwU+vt8LCnUZGBmHEVSM3tRNyOWOfaDQF+MkuP8 tPkekvqom8TbV/Vd+JFsG26DHWhQ9udhD9KYo4rbFuXnz/naS6MkMu3n8kue3Nu0WRRIDQkYGfpJ D4Fq5YX+A0X8Dr2vWIDASa36jPA4GNR7AQsgJnLoRYBZqmhn6Dwcfd+k3uY8ZWS0WMBLy0Kj/ob7 fPxpjwnvWL8eIwz2PfmPtDRf4u/oBy62DGZzF00cEgdbb+fb98I0IQw5eUP7AaBk+wMXd+DhyBLi yWJOoz/slRUUSy7HOGJ9q61vW3AWntnoP1CCMuW8RNx84dokG1AuhK3c2nyqB5TlUZ5Xrl52G6Pv 7FwuZP1VYs+uMAnfv2HJHoARGf/LoR2H/AVPXCw3ZtRFhQCW55F4o4iVioipi5lkYzZSIfJE6JxD 9GnRIwSmGdqIMogOZlMJdFk4jqXNVyb09x4VkJBXORZgr9R6kimPLqWKeWARTOD8F41c5VxvyrI5 tyaJsEIVfjdzcFGpunedHdADeM1dYq+r4DnZJlq50yIzat696LvLc18sQX23CV980Fq7I/WGO4nh dyJDrlxXqfwQTzvMgX8ZiX89iV8t5DiX+IHkBuxDvFvd8YHMX6yt/GThrykFpqYkzTQ/AsQ2zFQp vltaBmAZq7tkfOvpy38NpZz6BNkEhJFxWIisDNg1WxXXTHLEENivFTsanPz1ki4Bkub0vT52U+37 XBn1vHAYz7AzFoeFMfc1B8jHdbxrukjBDKD7ko7xHxPtchMnXuIMZGA7V3yEFTEPLLz2pUwOOHY5 ZyMDgWjLuJA5rB0jqHimiskIW8rSYt6B2zjEEQTXej8uzn7kNzM2U0CSj57onMgcKKLtz6ZBxmNs /MknSFAZpjbmfK0nBint5W4toVfcRr4dGFx+L0U0yQLijk4mFHF0T2hnnqDDTcxqdQ9kUcSnoeEH DzOdWzxwQPByyPNe4Mc6Rb13MwMHqAq8nWvK+OZxWgNmnC6HOqkX0lMWXtqMsAUuzEIZxuo28is2 8ZHiAnyOEGxqKLTr0LG0Gf7RO5upJwKUM2sPPfu2a2LI4lWcbQHq6UtAXgMSMVZBnJFlw4C+ef6X 6fpIVvUZaNM9uRFPm5JXhXX42nKMGr7VF6U6joGsGQhjZ5DDZ5fSUJ/hgUUADvKXWN8Eb7q4zroq +rAiUnj1VDDVXs+7J+P1WMKpoCS+ROAGwceJi/6jWSx0fakQZkqWtfOi/rEtb2MkOPrOx6Eu4xWU r0qk3FMnxkkIOn7lG4m4WU6GEoJ8hdAKceUQ/SmfRMsyXfUlqj1dnq33SKYFUDKrl/XLw9KgIQQa xsj4IVNivVXfKQpuDqN/FKm/k4WutaNrPsMIFd5SsTFC5Qb8h/YfU8ognjpi5Xwl8a1TZ3Yzg4li 7HoHAu+z9LMm5BtVJgItpfkgtbyZcmog8pVstGJCyGfU9eNM35IWb4pY0K2Dj8craq8RZU8GG20F Rbpse0ZznHbra5Byewgd1G4LbHwxNAXVgUrrrvGmKZ+2VHiGqglqNakmjBM3nI9zbutniBC07fjC UlwcEI/Bb8LA1DR8owz4R5pF010rmjsbQrDzNXWVOGhTghM5MIcd1bIbQckNmTY1tkMzhR3NaoqL P5ilfBNk4L08uvezqIE2tq8Omg2R8c4ROZ+nq+4I8ep30ZMngt6ZcCHxXcw18AhL3gIhLsJUkCR+ zM0wL/uXAInli/FLTOO6v2/JlQRYLvI3SpR4YdpEUOb7lMegZX0THASbGj5v2QKJ2PBl1fMkSEbc M3MvRfB7C29mfjT1AWfvfT7sg6FV95VYEhpa1lgT0jdKdZcobBFSH92pecDHszrhh3VWZbQy4CGs b2CxBnlJt9rPGoh+wr3vRzPYHb1WCrwsWZr0+ClZdZXVSBSCM8lBgig25DSP6f2Fe4IXd06U/pKA +lQcrf9o0Dm3WUKTQJ+6y6sY+0Frem1GIAa/Jdm3su0H3YGIMXMUeF4OsYIGXpu390q78vJ+xg6o ADBSc14Z1rwF7Bsy1EFPMyEBBIt7jxsjanQf9M3RBDJsy94/gTmjWyWYHBbpvX8h/a52EI50woan 9lxMjO9qY/Tfu4uRTbWf0Ed/GeweEs+YByU+fZBJRDJOa4rY+OYpHWZl2g4vksqrvI+3lazu4b27 LLYNgXILPAHltWluorRl2e74sExwiUuIVgUqZueOkw+ojyBtyxhPt2/7LKspuM38tOvk4FQiGyW2 jBfVJTQoD2jvc4Gmfn7MSjnT00ndxlullT8sdEuUQ1oIbKcauEN15lS4DFRu+RF+9VUn3l3r+vHD buFSzjd63pQ89hhlUQmZ+Ch/woRFJvGM/k9twlKyidWVFmmx4OB4I7+fV2kG7vptUncbMz7mxDkD WhutcU68kGL1csB8avWQjRKH4CT5eOffy1YDbF8Qpn8S1MV0fRDOXdR6rk+75Hscyl842gZkZR/u g5j0oU4hFmaukk8Jq7BspBTZGIEOB2UupSiNEwzdyuPCShwzud8tJGsNJty7elmLgiQnsJuMXdy8 ybZFPB2nwRWFLWXzJCUl2QdNP7NH0YCSYnFYhHw62jqJeq08DJ4FUS3cu7hxLTIvNpAxtG6yyLV6 b7TeCyguugz3jxw4aVsXc+fDoEbWqoxM1NX51NcUPIhegd13Ig2h/3obl4IndyCN5IRpKyWp4pEz VCJxlByIZal5D99sdLprItQEQlL0AEpoe320lpYKI/t4bjPPIemh9FQQWHJdj4eLHpejPKfSqgBx j1amX6Q8jDoTCpJXxpEm8xlXaesrhFPNPD9ZE2lo6P8ggmXZFtyz4uvvA6deUOYhhrURoPkuAJR3 JREGCyALfJVHyH+3ZE+N330udQgZOt5G4xhmlgkmBBvYjDPRC1YMH29KJlc2kSK7ale4kSMas4kW AeZHprUuwJFLzXurbZG5XkzVUH7oEj5/F1eg3HVa0l0aJNGCjL8SF6CnBRt0t6Ot7mn4L/ehrxgD xn93kVtso+M1uBi55l0acafLkF+UDP4GnYAVqc4X8BAB9u+qd9DrevNjHTK7M/IXp4iPSySLzuz1 riQjbFqI9prvI0FVMmi+W3VjEPIzHlb5LGyZ2GyrndVFT7yxUxMac7nCUsFP5M5VFgDVw8jWMBBl 59FbKh46D6t7ZG7IZaiWTYOivE8kHgJNc7kp1OHrhA5DNpDJUS1LvjKLzV/Tm8DpCPzH+4N00yXm qbhf3hNDfibZ1Ob//e6TOLLkEtKqe9dpYgj9OEZapXzEcl/twyXk8Mv8B+JuqpsLjSKQLfpuECaY aGi5emB/6uMfVpZTPoU7jG8GvyhuEwwk7NhJDOvOwqV0ARb+tX4ps1NfP4asJ0RzOJ/B/18nEea1 Elprwp5oZg1O/5dvi8VP7H2aF7k9i5g7XfYomnZTXiVoc0UyaecnMGwf6VVs+FrVzYYa3uLosmdL 8MNZaw1V4WAfuRShq20Q+j+kFu7unYChElz5EXif1BBKf1IUFEmDN/4ZNvxYDtjoWBxUB40loFQZ LpRgPCfsg6770FQkQiZdjuptWLMw/oFOXSLfQyeujhZI9wO0Zin+y4EZ3A6VGLZmlXwEDGQ+4z5I f+j/tvWKBSIOETQLkSv4OogLp5kFQoK3NUdx5zhjfk05AKr2GuoDh9pcIzNl145Q+G5111g4n6Ye qnRgKDJ/ke55999uVa+/GlcmeWy6oZ/VP6SxkeGq6DPY2YRcn1RE1LoALGhyv19T0sIGHYFcO02t yJ7vonThKeJ9PZKP7f4xKXY9BKyH2NyzV0ls7RkIDGh1RAUQZwHNDWKOliWyFBHXX0LmIJTGjU8r m3NkSicGYMQmrrqHn1vQWn2hQjgF+4n3lQldjcbr4hS+d9+bkZHCxdpj1X60D7ZkMjCJP6yMB1mH Jn32//b2UmSXzZ/tv1bLlahPa4tQN+UqR5l/C2UkR6qH4RDvGnz/w7EGYwjWWa8aoh9Kz77+c1iL n3JDB8NVBcOzgm9axkFbqLET2URLUbThDgabcu5vhmVjTYC7c4QWIga9Xw8kKDSS0sL+dAdt9TVK g84tXyZamMsb5JqSDNPsrut4Z7rtAXt0+qKADB7rA1Tc0WQtq4npGqzClqkH8mzL69taBVBBwE9r P96IHRdsGOo5EUQ11wmUEL8wnAWgJRZu77duUgyWFdp19HksWh3g4lPe+YxRbsiaoyFO1zDwLRXc IjB1D4XusH4Zr2tDyjbsReG19VLwsHXJRJ2ba+VIdzltAH9FV7YY+5kPBHYQcslS7bEgi4p2c0s0 6ZPHOGIE/niDWcYRREIxCf/f3hjNpDOXMirWNG72CyQbVbTarO7g7hNIuyrpHJ0vqLAepUHWE9w+ rew0/ZUXCO8WgdqSasVnuobQWUGyncKqWja0AW9fMZNoav8HpbOtyzPZSjLFjLap5pe6zR+bNbPr p8MGm2SBZ6BQB5Sb6H6vYqEj+PQwdiwd3JDrAcPeVIISkc7doQsSjMzbfNFbqeRBnu4+RCDxiXid tC20SXUuHZeXiBYyU6KX6hyGfr/dtOeywZBFow9Gk9/T7vzM9AsuAnLfqyjCT7nuuXGALFB94ZT6 BbxuY6mFq00bbSMEJhSY6VeJMgTXPaOyDZjVUFVAkDWZMMCTOtpWc8BzrTArtuLL3KHVGM09guTi xlP5uTJtQRDygfd5+EwnxRHtXEks0elr1S9/LaJvatHT1uKtNBtjnq+UJEhK6m2V15IyFGc1Vh9W UW+MbMc9hS8QnLWFZn62/g/wGUHdtUmKm+oaukEAF6hqMUAYNhjEvdrS8yjuDFwgf8pEDFcoYYdV x9K7OBIVo5WDiT+sCsmy/s/ghH6GGyMn5DbYX2zzwIx54lvPfOTfQMmaDo1qQoW1h+ckMn2WpRUm ZTSXt3HBafQOOtBcHS6lclApZcnDECSBKvIoqa1gUWcpVqnRvmYyTAhDZxPlSi4X2T5g4srkLCt0 hAx7lFrA6K2MYNhnTHgpEtojGdYV0t5ew/0LVu1wvakSzw+ANR7+Dn535iGihZdUzH57R2BCnRLK 3gqvGo/ko/MIY6n5c8RbYmhY/vSBUVo2n7nWmpExX4gKIJ4sNt30Xtx0T3pfYMKZ3Sq7+wkB2EZ8 AjfGxvVvIS6twfJeSa3yxKMdO0/LcOgVBtx8uI/ArIF4zEC3/ztjriAIna1PR8kqRa7VxgzuOpKI OVHD6DbfFx8lbCkAuOZgUY7LAFy5FWK501WSudaHCBpxhTLUIJ7SghgAOnhr401EfiRVKuOxJFq6 L7jE3uznhIGwzRDMgcsELdCGFaep+KSVEGLf67UcR2Cf7qvA4XclrlzEWXaDxJqbWHjYpHVnSZt+ j3UjcxWdJj8x9KYHtNdTSBQJHmr4EyMQu/k7slfugHVKrccMs55iW/P7Xd85dV9O6t7WRSGm3jfu Zl8XINbQFj2D6zC9HdRPZ2K2A/KR0rPciMarQp4IamroUpcwNShwlaSz7mvpsTjcPDO5qsudDUKv XyqvJg6KWPNmnpNFqLyl6Zc5oLI0xbmQnkC1N23UsJhseg+gnsR+pIUjFWK22MEqCcb552vmPdMF BUpCs7xbgpAB3iUZo8mOU1MlxwZEprS+VzBZmM2vAG+DuZwAksUMVkTF2q//WiLEXIW/A8dYspE/ mvxTMdAuwCn45ldbovfAoRSFZNzz75t8VjHmLKDgyRtLaGQn0bRh9Xs6I11Kwal0d45Mwria9lEG ZRYAvoBm0jbkISirh7STt3sclu4MyZbW19F+a0M1ihluBWeUowm1CD2X5vUf9zQiZYb7PmVW4xPw U28OhJTtymU5R43sqf080mW6RxmIfITHRp70G9q3fLs4ktmwCdDXzmokA03dE3F+bAx1G/La4TqE 5uTETRR0nPysjwW6HV0o/XQprfWmUe+6zNt5bvHt1FGc6ZpciXovjwOyrOm2cre3koxlb/oHlc2X gEV+wTBzvAvK0zJwBbusREiUlZ0GSEaZi/ARA8tK6lDqCHroop9D+oEihQNsX3xD303Jy2vDXZrW YfU3t1rzHNKrJm2mCXSAF7qhnvKwz1SBX2FIeJQz2LL/znspf0Rh4Fg8nUtFIBYSU8yK4S43I9/M hcHUewsPjl3dUOwjWwskEPut7tEahww2Q3URfC3fZQ9HWe4bVVdYBdzUOeJQDJII/CbAuLckTRmd ws40Xmj3EYzMYaaLma+I0O/FyW/fcl22TNZI0PXul7qpY/So9DdwAGBNJhE1pzRUr3tck+UlGChe 85WKZM5ekcLkbeJ+9yOHx+Iqtrfrz8Ql166B2MapIyzAXEvbEShnllPVH08i9UXGGmUefT6cs6qP V+rdewM7t5izmyH13WYX2+rrLBUMHZsbQFmVnaetZw2IIDmHUQ5Oo22SoAAwHgsdP//lt1qwtMEB x77mi3jhZGSxmkw5fOx7qzh8q9200FyVVJumopobLtgyflQexBtDrUXm6d9RBy2kZTIqOwH0d5FE jFc9oVlMrYZaYoEYvlx5ZYxJPBrEfPHXf8P2JfF6uZFgNq86pT3rLO6dVzF6O/Tj6yzggGuxDm8G L8KGOzILRyCNcDoTuOKFjB72o6axmpgXEI5d0uZgZCr7iKwQaqs0iV5bHoPrz9nVW4OXYfys7m1i 1LP7D/DOgpvePh5PAlQoHMZFT2yiXu1+y7mVBRKNMACtXi1pz7a5Ub4NoVyCsURKzSyMrwaUQtyz 2kDXfR23JnMoBjxdCOFiLoSZ1VC9oDHiZOXwbYdLSnLkIbGPNyBt/9Df+2vpmim56p7nS6zRbKQo cBSNNnEmY310JQo8yNsIknUwTKgXwkl23Dwa3KEoRfwCC+T75Pp0/rMELsXBYmtdHwycI55s5o2i ojh/b9DRKN/RBN62PuIYMr2O1kCbhlz5tVjbH47vOiqhdXecLi/abJWgUt9wSxm6HOsWCu7ZncbY 4Gy9KdDPkm1kiNRWrERlCCyWFyBmCmJ9fKX2qn+pDza4Dwsbe3ZOxuAJApNuRngVJaZgiR8Tw8rt w1fkjhHB+UF28r9R8nSJjFr6HWpozEI8/0r+3O4pU5icpNfDv2DMDBsLDGB2VKrAxpnUOyAwFjFO YSKMi9NUtZ7k9Hz781vVfWxJQeomtbSZY706wQmuGJOpA4tv6hNKnEQGgWR2WCXfDvwaDmjpnngm 37vcPS40rwHVzqfSCRacLEeV+jRedQmR+G9ecz0JFRc2quUa0GmVdTlldbFwrp8FABPU3rKe8JNt QwnqU5a6dPkh3wV+aGtg43odBCTLSBfeWY0B+buStnaVTjw/CM/ZQoWKO4mCXUxu7zqf8sKfFhJh c1FjBRS7pE9orApP8zizMOjrZpfNX635dEeYQ+DnxBOBPaHqbEJw/XuPBVTxBLgK8AKIHdT9mVA+ uRXfGg0ju97Ay+0LY+z611ZAzOjTZ8Fp/ajl1V8OAOim2pJnl9+2gbg/sTAZfbuH64uJZXqRhfZS I8WBGR/gPci2eTMvZlwKfK60SxX247sqtnYq/N9ixmcwmyj34ppQ7uTirzH/o9JRzbNvtRSxVuIS QpCbQuGF4Q2wxh3OnFtlfIfEHRyF/89K9Wyo0L8KwiA6aPd13SCe1PQU0Oa5CUB2e27MZzkWY+pT qCh2zqNpYEJulHxEnYG2NGJdRvHl4Yj482H4mCKXVYdole4PFgqYDhDghywJ0HoT49wubbGPEpcM LCskdNrCf8uDEEWUa7vLTzUYMrPu3FJIyJe7wwtwRVEqBXH/8ESpKQuJmC19TMvHHWGE5VsN6wmA DHGP3w5O7XWvbAx/7O66qB6xGB2p6h+b0C33LCPpjJJvGP2z4t+zYhPsCSpKWYN23YzaYnYmR6Tm FnNko3oeikK6gPRodIAGS4nZ0N8C50Cd3HtHasRy0z+73sB7JE2MZB4GXnh6D4uvKBr1KoUzudwt yD0H97gUCMMXbGnzZELjc0hv6kOffkbTAaFwzTS91334FvICYoKj3r6qx79JfoWRqxsVVD62xZ11 jShiuG4UxLGj7TocqL8TXGSsy4GSq0k348N+FAeS6iYWVl+fdPAQikkAlQNDN44I1eEgnsIpCFpI xLih+4Uoqa3ZKY3FTX7UY1Z6b3vDm0eEoUOQZIrAfSRXls1dr+PTy5XxKWSii7arO8TTO+hIa9NQ jTMwhY2wzUmFgUSE6oAW8s69r5JQfFE5imVTn23f/pMfMlTgIKKOhlVHKa1pMRxXGjejoR7JWssS v/UzW2bSpocae26pUrZ1YomzOM4nYQePSfXDUqCuexoXZtnTh9S54uJouSOMc3mpMElZv2bAofxm XlO04ytxQsEKQp+F4efq9E7YuYA3w77f3e9kaYJrXhg23obqZmlbnQyNVt8R2TIsD3pxjhHJkuNM qAexF1XZQWXxaM43dAHfv6vIk2U3jy0f55Ns0JYk8/gBotK/dcikffQq8SDqaR15FDgfvJE6OkEd MW46AVpFJ9KJ9mxFSR7XR0y7QUfrKYSlvTgyJohvEDfEfwSEEZBuiF/De83fBg7xskQqWOiz4bFs pbRiW6xSby6rTujjRP1cD+tLnU99weBl5vulvlexahsTEAC7IbunwTho+GpROwN2rr4ulucK5CNL U+K3cnWd/EGq9gHtY7psJatJbbYpeHMtHTrdBad0sP9vFumdL5FtxeS+YULI3XVJ0kQ6rE8hGxf3 oNtWenVlh192lFLsqm50dR/E6yNVbQbzFNb6mqxqE66K/0/BXT+p5oDYzsBBDrgTxajP83QUTV9L MUt4RetbbSR6wOp6np2sAEtT3CRK21dll14wAG7ljegHQG+kA5y1HExuCcf2LvLqXMAw1q99+sRq e4S6jS2ypwilDFJGnBrbZO/ZPAr16zWE1AAcFz9D0EggaxChbmwZo8LfiPPXK37eQhboE6SxOYdH VMGL+iDFchUAsTCJsiNAjUkxtaq8qVsS8Omxe+RR4nCY6FGV552E1iMULBAcCusvwS0GeNLD8zbx nWmoi+D0dw7J5JkI35bmoEkzhRG9+OI15Y5pGHREu4OHxS9EaVQmq0IPDUUdkw+yU0TCjrbnvAvT Sx/08Ql3JYuMyIn3XAcbghEcNFDsFa1QphhNCm42xQivxRhkPF1d+xsm3ut51PT9QtNBiLhWCmxZ /dV6cEhMx1x2w4ZMFRq/0YdYEy7XeUq4XhYsOrspfHiBrRFiUxZN2wqlTr4/rP5esY8Nxx83qj3x bHTSTgLm/YAJpVPbRULCi9mdSQVCZw2j1ueQtSkfnUc4ng39ee5SMTwf4o0Zi1cCC+pLqVX7+RAV n4GHk7ngZQGj8Vfos5+7hL2quhJv33YK/T8BXIdOwCKqyydaOQMchQDV7MAE+do/X7i3gbpr6CbY 85qnTec0xpMHNTG2U73iqGXT4vI4QzpMKysdCKdHYbdJsswuuKscxid24tgVQol4ZRqDlRnFhLj1 fiMr0OMy1c/pTjJzm9iLigbaFWAy9jCumUNJhiZ0mpd+hGTLTDVRwpZB92xpfWJvYanUqy+yPbUV r2QL4YZ4xQaiNbvWub42onfXYpVK4EaUw8rZoMWYjVISKFIEW2UEofoO4J1OLr94b1NFho80Kzt3 6f58g4WkYydb8sFiBl8tM1/jAMclLwYn6/wavdhYQp8azxGLQgfHYkTQGpAOdONd2YuKm4LWV4jN TvcXuHHCiJvHZtz9+W0qWz6zEEwxDA5M+RVlwabk5qtMcSxh+7IzDMIn7uQFCgdd5+gb2vyMu0tZ knH6LFNBfhnXoG3DDCu8wBaoG63fkMFEbF9bpojfYLHXX2jSG2E6mOL+V6Pd8yPV9JrUOC6U9bha Txm5ymcA/gy1e1LOrDiFB9ZdZi7Zz7WxNs9mu2NWdLYmeXvPpKQsl8b2tAghd52BwKtvIH6gwcT0 N37jub7a8rsW4wvyexrrem/AkeWkxC3d3k05JxiMRTGbb7g7rdOS/+zV1z3gR/trbhMioQhf+sY8 7oDQz6f5sbKTBjdF3O64mAIPRU6egaVqZGoTpJziLabDojBjAaL82t8wW+ewQOJ7H6FjQiIfFPAB pkuxBQPNCRo0S6iZ/9mOYzdsdad4RYGA7DRXORvhsBTR48hadUuA5vLljb/Eat03zJdhw93b6fQC uVp8qOA42orYZZA3NSH4LjPUm/0ZLWpUYndojnj5Sm93aDdrJPk1MbMij9j5hpE1s6jaRpARWLcu FUgA+udne03fD6AH8oUfRWbH5jYx5PGjMXHLgWmGrTNd8CqzMpZ4PwX7NkVd4v94qhL4x8SFiCG7 T4xd4WxCDAW3iDNY1Tx53ivY9Zons2W38BVHkzCv72UTlsyBuGjnmIXRCbVUW3fq8DsHdivXBb3F gijXEexxUnAX+OZ5nb3fz0PTH+Qx/diwqi1Rdr88EajJMhFT/IH5FG9Dx5c8IhNs+Qe6pFTtTLh5 AHFZPl557IG/hPGl0g761dlBXEH2WAdLTKj7aINyFB9FiDKdV9CFTFkC2r+8OOtkJw+NF/QJxgz2 O4H2jKTl0ElRsiAnpElLU1wFPUnxmv1GGY252nNJu/HkJ859CvVugrotS8BFk3CEMsnnS5L8NJBW l4cdKwzcINgeUXUCJiGiiS/NQQe0lxyZfQ5SgbY1/ilTexseZqXMXAhmOkp2ro1eY2L0oCYaFh6a RhgBBpx7dZ7+qSZrjLHHeGD4cUi0LiH5wG577A0JT1DB6bUPpdf5AlfFcTC/KzKrtiSnIs4empm4 ZZgwpy4yTUVcHquo2/nRSDhCrU3+xM1YeLvVQA4hOt0nylbWmNPe6wulpWB6hL2cTgKxfvRnLoDh pwd2mRvgL52gNYhZrucp/3LqgUmboJdYwW3iKO9W/2dIr0bu/7r2PTafpGU6g8wqdWsudCuuE/lF tIbKo+yw2r4WBRHMd6csngzMj+p5jYu+CprnQJQ/fYedPb2lHzvmG2qnk1DzwU1MB9/0+2VLHqGB 5XqdmbBz27kHZwNquKk0r3SKAAq3MZI0UscpOUBgRRjDrmHYtRU69hBg9p8wI+2UXXUx3VGI1D9F TZNv68FzZJjCSnaOU50zCTMNijAEv5NkNZa4kW8MyeuwRS1DFXI+g9mAHVpAWb7KLSOyDND0Nd+S qPhBaLO7oO/3/bwEivodAUW6nsLhs92OCztWW+SApMeoFFYZg94i9aYTUVrShufAiRHQhs2QZ4ok D5ogrsRKU6a5/svWV/fqVon2n7GOQA36+adwVT6ZiPHCFVPZ90d6/zlOwM8dC0khrwGEx0x5zKhw g47yxo7tzNbpdmu96bEGMKHajhcVHMpk/QYnXNvBrFgQQW1TPMUKhpjhp5GZ0EVBV2+g9bE9hDUo s8JZpWYGWv8sh6bQuajPpg5xGmzWnyAalOJqUAdXiFLxYIbP+Im5q5qGMhjAuCMc9HuXlZaOTAwo H7NYhVT3+JOOjgwouwfFSU+P87Q6pAKtcL0NVws9tGVXqwwflNwqhMbioP7jnJpzqhMuoxjtZq/S G/lxFuEUxbD9PpVMcqE6yVqes562Zc1K5RR4b1hhK78+pizoU77PEI3R7nLzRfJRQ8U5dX60gZbn QFG95xhE3Ssrh2eP8lD564/fhwooJOAx+NYY37fyoQlS/mvC1/e5dzKzoZzTmENWOZcFgxCMm+8Y rjb3tvYd666ok0vwgE/2EcClmLjO9OF6GwGC2XGTUKNTg+RjcgYMwXixm/eAiKY5iz1iANMyh2i6 ULD53iM8nPxZWFiDF15f4saOm3QAlSQuw9oJ4gypi+BlPtod1Zkdlx2+Wtfe3nezA20fU5kfTehl d2rhWckJtbHkPxMJS67O3UnTW68PNf0safzbR75Sals51pYOHgkZTYNi0LTaGVAFDueHTL3ALkGI qLxNOLgFGnF+2KsCBd7JV2I4UsfbwfwHOcg358QOoxgRFZQMM4d0ZZ179HwMnFGD2RRsBVcNXtek MMENZLPDXnEZlZ2an8COQ50a2yHw4SqtkwSl1Eoe2i1wUcISAiJzm+zdKQui+iyw4DJQ3eblEZbo OfrHzZhGIsy0wfjhicO3iZJpVolCZhwkIOwLooDE9Z+RoQVfl9+7z4l2b9WQ+Te/caiuLGwDgQox pN9eCFST6+KSexelLHqP4jPT+xBuc1hJSuoLXny3PwuLH4WdXnZodTbKyVMCvRpePazkUzq42cfH B14HqxypeG2ymkU= `protect end_protected	bsd-2-clause	d9a013b73cd003072454e9cb662380f0	0.942266	1.857759	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/styles/code_examples/spi_slave.vhd	1	34,119	---------------------------------------------------------------------------------- -- Author: Jonny Doin, [email protected] -- -- Create Date: 15:36:20 05/15/2011 -- Module Name: SPI_SLAVE - RTL -- Project Name: SPI INTERFACE -- Target Devices: Spartan-6 -- Tool versions: ISE 13.1 -- Description: -- -- This block is the SPI slave interface, implemented in one single entity. -- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard. -- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'. -- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line. -- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two -- clock domains. -- -- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o. -- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch -- signaling ('PREFETCH'). -- -- PARALLEL WRITE INTERFACE -- The parallel interface has a input port 'di_i' and an output port 'do_o'. -- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. -- When the core needs input data, a look ahead data request strobe , 'di_req_o' is pulsed 'PREFETCH' 'spi_sck_i' -- cycles in advance to synchronize a user pipelined memory or fifo to present the next input data at 'di_i' -- in time to have continuous clock at the spi bus, to allow back-to-back continuous load. -- The data request strobe on 'di_req_o' is 2 'clk_i' clock cycles long. -- The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid -- race conditions at the register transfer. -- The user circuit places data at the 'di_i' port and strobes the 'wren_i' line for one rising edge of 'clk_i'. -- For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one -- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer. -- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time. -- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle, -- if continuous transmission is intended. -- When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'. -- -- PARALLEL WRITE PIPELINED SEQUENCE -- ================================= -- __ __ __ __ __ __ __ -- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock -- ___________ -- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'clk_i' -- ______________ ___________________________... -- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'clk_i' rising edge -- ________ -- wren_i __________________________/ \______... -- 'wren_i' enables latch on rising edge of 'clk_i' -- -- -- PARALLEL READ INTERFACE -- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete -- word is received, the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'. -- The signal 'do_valid_o' is strobed 3 'clk_i' clocks after, to directly drive a synchronous memory or fifo write enable. -- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'. -- When the interface is idle, data at the 'do_o' port holds the last word received. -- -- PARALLEL READ PIPELINED SEQUENCE -- ================================ -- ______ ______ ______ ______ -- clk_spi_i ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi base clock -- __ __ __ __ __ __ __ __ __ -- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock -- _________________ _____________________________________... -- 1) received data is transferred to 'do_buffer_reg' -- do_o __old_data_______X__________new_data___________________... -- after last bit received, at next shift clock. -- ____________ -- do_valid_o ________________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'clk_i' cycles -- -- on the 3rd 'clk_i' rising edge. -- -- -- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. -- ------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- -- -- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave -- -- Author(s): Jonny Doin, [email protected], [email protected] -- -- Copyright (C) 2011 Jonny Doin -- ----------------------------- -- -- This source file may be used and distributed without restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains the original copyright notice and the associated -- disclaimer. -- -- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser -- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or -- (at your option) any later version. -- -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more -- details. -- -- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download -- it from http://www.gnu.org/licenses/lgpl.txt -- ------------------------------ REVISION HISTORY ----------------------------------------------------------------------- -- -- 2011/05/15 v0.10.0050 [JD] created the slave logic, with 2 clock domains, from SPI_MASTER module. -- 2011/05/15 v0.15.0055 [JD] fixed logic for starting state when CPHA='1'. -- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries. -- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core. -- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets. -- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches. -- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce -- synthesis LUT overhead in Spartan-6 architecture. -- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. -- 2011/06/12 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. -- 2011/06/17 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. -- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock. -- 2011/07/29 v2.00.0110 [JD] FIX: CPHA bugs: -- - redesigned core clocking to address all CPOL and CPHA configurations. -- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite -- clock phases from SHIFT_EDGE. -- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions -- for each state, to avoid reported inference problems in some synthesis engines. -- Streamlined port names and indentation blocks. -- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core. -- Simulated in iSim with the master core for continuous transmission mode. -- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit. -- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes. -- 2011/08/04 v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic. -- 2011/08/08 v2.02.0122 [JD] FIX: continuous transfer mode bug. When wren_i is not strobed prior to state 1 (last bit), the -- sequencer goes to state 0, and then to state 'N' again. This produces a wrong bit-shift for received -- data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and -- sequencing from state 1 to N as long as the master clock is present. If the user does not write new -- data, the last data word is repeated. -- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word, -- the slave will send (others => '0') instead. -- 2011/08/28 v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when slave is desselected will glitch for CPHA='1'. -- FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update. -- ----------------------------------------------------------------------------------------------------------------------- -- TODO -- ==== -- ----------------------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity spi_slave is Generic ( N : positive := 32; -- 32bit serial word length is default CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase. PREFETCH : positive := 3); -- prefetch lookahead cycles Port ( clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers) spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core) spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output di_req_o : out std_logic; -- preload lookahead data request line di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i) wren_i : in std_logic := 'X'; -- user data write enable wr_ack_o : out std_logic; -- write acknowledge do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge. do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i) --- debug ports: can be removed for the application circuit --- do_transfer_o : out std_logic; -- debug: internal transfer driver wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher rx_bit_next_o : out std_logic; -- debug: internal rx bit state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register ); end spi_slave; --================================================================================================================ -- SYNTHESIS CONSIDERATIONS -- ======================== -- There are several output ports that are used to simulate and verify the core operation. -- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing -- circuitry. -- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the -- synthesis tool will remove the receive logic from the generated circuitry. -- Alternatively, you can remove these ports and related circuitry once the core is verified and -- integrated to your circuit. --================================================================================================================ architecture rtl of spi_slave is -- constants to control FlipFlop synthesis constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge ------------------------------------------------------------------------------------------ -- GLOBAL RESET: -- all signals are initialized to zero at GSR (global set/reset) by giving explicit -- initialization values at declaration. This is needed for all Xilinx FPGAs, and -- especially for the Spartan-6 and newer CLB architectures, where a local reset can -- reduce the usability of the slice registers, due to the need to share the control -- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice. -- By using GSR for the initialization, and reducing RESET local init to the really -- essential, the model achieves better LUT/FF packing and CLB usability. ------------------------------------------------------------------------------------------ -- internal state signals for register and combinatorial stages signal state_next : natural range N downto 0 := 0; -- state 0 is idle state signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state -- shifter signals for register and combinatorial stages signal sh_next : std_logic_vector (N-1 downto 0); signal sh_reg : std_logic_vector (N-1 downto 0); -- mosi and miso connections signal rx_bit_next : std_logic; -- sample of MOSI input signal tx_bit_next : std_logic; signal tx_bit_reg : std_logic; -- drives MISO during sequential logic signal preload_miso : std_logic; -- controls the MISO MUX -- buffered di_i data signals for register and combinatorial stages signal di_reg : std_logic_vector (N-1 downto 0); -- internal wren_i stretcher for fsm combinatorial stage signal wren : std_logic; signal wr_ack_next : std_logic := '0'; signal wr_ack_reg : std_logic := '0'; -- buffered do_o data signals for register and combinatorial stages signal do_buffer_next : std_logic_vector (N-1 downto 0); signal do_buffer_reg : std_logic_vector (N-1 downto 0); -- internal signal to flag transfer to do_buffer_reg signal do_transfer_next : std_logic := '0'; signal do_transfer_reg : std_logic := '0'; -- internal input data request signal signal di_req_next : std_logic := '0'; signal di_req_reg : std_logic := '0'; -- cross-clock do_valid_o logic signal do_valid_next : std_logic := '0'; signal do_valid_A : std_logic := '0'; signal do_valid_B : std_logic := '0'; signal do_valid_C : std_logic := '0'; signal do_valid_D : std_logic := '0'; signal do_valid_o_reg : std_logic := '0'; -- cross-clock di_req_o logic signal di_req_o_next : std_logic := '0'; signal di_req_o_A : std_logic := '0'; signal di_req_o_B : std_logic := '0'; signal di_req_o_C : std_logic := '0'; signal di_req_o_D : std_logic := '0'; signal di_req_o_reg : std_logic := '0'; begin --============================================================================================= -- GENERICS CONSTRAINTS CHECKING --============================================================================================= -- minimum word width is 8 bits assert N >= 8 report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum" severity FAILURE; -- maximum prefetch lookahead check assert PREFETCH <= N-5 report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum" severity FAILURE; --============================================================================================= -- GENERATE BLOCKS --============================================================================================= --============================================================================================= -- DATA INPUTS --============================================================================================= -- connect rx bit input rx_bit_proc : rx_bit_next <= spi_mosi_i; --============================================================================================= -- CROSS-CLOCK PIPELINE TRANSFER LOGIC --============================================================================================= -- do_valid_o and di_req_o strobe output logic -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a -- fixed-length delayed pulse for the output flags, at the parallel clock domain out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg, do_valid_A, do_valid_B, do_valid_D, di_req_o_A, di_req_o_B, di_req_o_D) is begin if clk_i'event and clk_i = '1' then -- clock at parallel port clock -- do_transfer_reg -> do_valid_o_reg do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs do_valid_C <= do_valid_B; do_valid_D <= do_valid_C; do_valid_o_reg <= do_valid_next; -- registered output pulse -- di_req_reg -> di_req_o_reg di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs di_req_o_C <= di_req_o_B; di_req_o_D <= di_req_o_C; di_req_o_reg <= di_req_o_next; -- registered output pulse end if; -- generate a 2-clocks pulse at the 3rd clock cycle do_valid_next <= do_valid_A and do_valid_B and not do_valid_D; di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D; end process out_transfer_proc; -- parallel load input registers: data register and write enable in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is begin -- registered data input, input register with clock enable if clk_i'event and clk_i = '1' then if wren_i = '1' then di_reg <= di_i; -- parallel data input buffer register end if; end if; -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset) if clk_i'event and clk_i = '1' then if wren_i = '1' then -- wren_i is the sync preset for wren wren <= '1'; elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren wren <= '0'; end if; end if; end process in_transfer_proc; --============================================================================================= -- REGISTER TRANSFER PROCESSES --============================================================================================= -- fsm state and data registers change on spi SHIFT_EDGE core_reg_proc : process (spi_sck_i, spi_ssel_i) is begin -- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) -- state fsm register (fdr) if spi_ssel_i = '1' then -- async clr state_reg <= 0; -- state falls back to idle when slave not selected elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update state register state_reg <= state_next; -- core fsm changes state with spi SHIFT clock end if; -- FFD registers clocked on SHIFT edge -- rtl core registers (fd) if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers sh_reg <= sh_next; -- core shift register do_buffer_reg <= do_buffer_next; -- registered data output do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag di_req_reg <= di_req_next; -- input data request wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization end if; -- FFD registers clocked on CHANGE edge and cleared on idle (spi_ssel_i = 1) -- miso MUX preload control register (fdp) if spi_ssel_i = '1' then -- async preset preload_miso <= '1'; -- miso MUX sees top bit of parallel input when slave not selected elsif spi_sck_i'event and spi_sck_i = CHANGE_EDGE then -- on CHANGE edge, change to tx_reg output preload_miso <= spi_ssel_i; -- miso MUX sees tx_bit_reg when it is driven by SCK end if; -- FFD registers clocked on CHANGE edge -- tx_bit register (fd) if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb end if; end process core_reg_proc; --============================================================================================= -- COMBINATORIAL LOGIC PROCESSES --============================================================================================= -- state and datapath combinatorial logic core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg, do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is begin -- all output signals are assigned to (avoid latches) sh_next <= sh_reg; -- shift register tx_bit_next <= tx_bit_reg; -- MISO driver do_buffer_next <= do_buffer_reg; -- output data buffer do_transfer_next <= do_transfer_reg; -- output data flag wr_ack_next <= wr_ack_reg; -- write enable acknowledge di_req_next <= di_req_reg; -- data input request state_next <= state_reg; -- fsm control state case state_reg is when (N) => -- deassert 'di_rdy' and stretch do_valid wr_ack_next <= '0'; -- acknowledge data in transfer di_req_next <= '0'; -- prefetch data request: deassert when shifting data tx_bit_next <= sh_reg(N-1); -- output next MSbit sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb state_next <= state_reg - 1; -- update next state at each sck pulse when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits do_transfer_next <= '0'; -- reset 'do_valid' transfer signal di_req_next <= '0'; -- prefetch data request: deassert when shifting data wr_ack_next <= '0'; -- remove data load ack for all but the load stages tx_bit_next <= sh_reg(N-1); -- output next MSbit sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb state_next <= state_reg - 1; -- update next state at each sck pulse when (PREFETCH+2) downto 3 => -- raise prefetch 'di_req_o' signal di_req_next <= '1'; -- request data in advance to allow for pipeline delays wr_ack_next <= '0'; -- remove data load ack for all but the load stages tx_bit_next <= sh_reg(N-1); -- output next MSbit sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb state_next <= state_reg - 1; -- update next state at each sck pulse when 2 => -- transfer received data to do_buffer_reg on next cycle di_req_next <= '1'; -- request data in advance to allow for pipeline delays wr_ack_next <= '0'; -- remove data load ack for all but the load stages tx_bit_next <= sh_reg(N-1); -- output next MSbit sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle do_buffer_next <= sh_next; -- get next data directly into rx buffer state_next <= state_reg - 1; -- update next state at each sck pulse when 1 => -- transfer rx data to do_buffer and restart if new data is written sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb di_req_next <= '0'; -- prefetch data request: deassert when shifting data state_next <= N; -- next state is top bit of new data if wren = '1' then -- load tx register if valid data present at di_reg wr_ack_next <= '1'; -- acknowledge data in transfer sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data else wr_ack_next <= '0'; -- no data reload for continuous transfer mode sh_next(N-1 downto 1) <= (others => '0'); -- clear transmit shift register tx_bit_next <= '0'; -- send ZERO end if; when 0 => -- idle state: start and end of transmission sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data wr_ack_next <= '1'; -- acknowledge data in transfer di_req_next <= '0'; -- prefetch data request: deassert when shifting data do_transfer_next <= '0'; -- clear signal transfer to do_buffer state_next <= N; -- next state is top bit of new data when others => state_next <= 0; -- safe state end case; end process core_combi_proc; --============================================================================================= -- OUTPUT LOGIC PROCESSES --============================================================================================= -- data output processes do_o_proc : do_o <= do_buffer_reg; -- do_o always available do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output ----------------------------------------------------------------------------------------------- -- MISO driver process: preload top bit of parallel data to MOSI at reset ----------------------------------------------------------------------------------------------- -- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit -- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic. spi_miso_o_proc: process (preload_miso, tx_bit_reg, di_reg) is begin if preload_miso = '1' then spi_miso_o <= di_reg(N-1); -- copy top bit of parallel data at reset else spi_miso_o <= tx_bit_reg; -- copy top bit of shifter at sequential operation end if; end process spi_miso_o_proc; --============================================================================================= -- DEBUG LOGIC PROCESSES --============================================================================================= -- these signals are useful for verification, and can be deleted after debug. do_transfer_proc: do_transfer_o <= do_transfer_reg; state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug rx_bit_next_proc: rx_bit_next_o <= rx_bit_next; wren_o_proc: wren_o <= wren; sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug end architecture rtl;	gpl-3.0	cb3a9545fa1daa9c283638a582f93725	0.472552	4.738092	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/instantiation/rule_027_test_input.fixed_upper.vhd	1	565	architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : ENTITY fifo_dsn.1clk_fifo port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : ENTITY fifo_dsn.1clk_fifo port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;	gpl-3.0	eac4bf39ad58fbe7561a75bdee997f37	0.493805	2.742718	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_sf.vhd	1	50,791	------------------------------------------------------------------------------- -- axi_datamover_wr_sf.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_wr_sf.vhd -- -- Description: -- This file implements the AXI DataMover Write (S2MM) Store and Forward module. -- The design utilizes the AXI DataMover's new address pipelining -- control function. This module buffers write data and provides status and -- control features such that the DataMover Write Master is only allowed -- to post AXI WRite Requests if the associated write data needed to complete -- the Write Data transfer is present in the Data FIFO. In addition, the Write -- side logic is such that Write transfer requests can be pipelined to the -- AXI4 bus based on the Data FIFO contents but ahead of the actual Write Data -- transfers. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/21/2011 Initial Version for 13.3 -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; use proc_common_v4_0.proc_common_pkg.clog2; use proc_common_v4_0.srl_fifo_f; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_sfifo_autord; ------------------------------------------------------------------------------- entity axi_datamover_wr_sf is generic ( C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4; -- This parameter indicates the depth of the DataMover -- write address pipelining queues for the Main data transport -- channels. The effective address pipelining on the AXI4 -- Write Address Channel will be the value assigned plus 2. C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512; -- Sets the desired depth of the internal Data FIFO. -- C_MAX_BURST_LEN : Integer range 16 to 256 := 16; -- -- Indicates the max burst length being used by the external -- -- AXI4 Master for each AXI4 transfer request. -- C_DRE_IS_USED : Integer range 0 to 1 := 0; -- -- Indicates if the external Master is utilizing a DRE on -- -- the stream input to this module. C_MMAP_DWIDTH : Integer range 32 to 1024 := 64; -- Sets the AXI4 Memory Mapped Bus Data Width C_STREAM_DWIDTH : Integer range 8 to 1024 := 16; -- Sets the Stream Data Width for the Input and Output -- Data streams. C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2; -- Sets the bit width of the starting address offset port -- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH) C_FAMILY : String := "virtex7" -- Indicates the target FPGA Family. ); port ( -- Clock and Reset inputs ----------------------------------------------- -- aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- reset : in std_logic; -- -- Reset used for the internal syncronization logic -- ------------------------------------------------------------------------- -- Slave Stream Input ------------------------------------------------------------ -- sf2sin_tready : Out Std_logic; -- -- DRE Stream READY input -- -- sin2sf_tvalid : In std_logic; -- -- DRE Stream VALID Output -- -- sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- DRE Stream DATA input -- -- sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- DRE Stream STRB input -- -- sin2sf_tlast : In std_logic; -- -- DRE Xfer LAST input -- -- sin2sf_error : In std_logic; -- -- Stream Underrun/Overrun error input -- ----------------------------------------------------------------------------------- -- Starting Address Offset Input ------------------------------------------------- -- sin2sf_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); -- -- Used by Packing logic to set the initial data slice position for the -- -- packing operation. Packing is only needed if the MMap and Stream Data -- -- widths do not match. -- ----------------------------------------------------------------------------------- -- DataMover Write Side Address Pipelining Control Interface ---------------------- -- ok_to_post_wr_addr : Out Std_logic; -- -- Indicates that the internal FIFO has enough data -- -- physically present to supply one more max length -- -- burst transfer or a completion burst -- -- (tlast asserted) -- -- wr_addr_posted : In std_logic; -- -- Indication that a write address has been posted to AXI4 -- -- -- wr_xfer_cmplt : In Std_logic; -- -- Indicates that the Datamover has completed a Write Data -- -- transfer on the AXI4 -- -- -- wr_ld_nxt_len : in std_logic; -- -- Active high pulse indicating a new transfer LEN qualifier -- -- has been queued to the DataMover Write Data Controller -- -- wr_len : in std_logic_vector(7 downto 0); -- -- The actual LEN qualifier value that has been queued to the -- -- DataMover Write Data Controller -- ----------------------------------------------------------------------------------- -- Write Side Stream Out to DataMover S2MM ---------------------------------------- -- sout2sf_tready : In std_logic; -- -- Write READY input from the Stream Master -- -- sf2sout_tvalid : Out std_logic; -- -- Write VALID output to the Stream Master -- -- sf2sout_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); -- -- Write DATA output to the Stream Master -- -- sf2sout_tkeep : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); -- -- Write DATA output to the Stream Master -- -- sf2sout_tlast : Out std_logic; -- -- Write LAST output to the Stream Master -- -- sf2sout_error : Out std_logic -- -- Stream Underrun/Overrun error input -- ----------------------------------------------------------------------------------- ); end entity axi_datamover_wr_sf; architecture implementation of axi_datamover_wr_sf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Functions --------------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_pwr2_depth -- -- Function Description: -- Rounds up to the next power of 2 depth value in an input -- range of 1 to 8192 -- ------------------------------------------------------------------- function funct_get_pwr2_depth (min_depth : integer) return integer is Variable var_temp_depth : Integer := 16; begin if (min_depth = 1) then var_temp_depth := 1; elsif (min_depth = 2) then var_temp_depth := 2; elsif (min_depth <= 4) then var_temp_depth := 4; elsif (min_depth <= 8) then var_temp_depth := 8; elsif (min_depth <= 16) then var_temp_depth := 16; elsif (min_depth <= 32) then var_temp_depth := 32; elsif (min_depth <= 64) then var_temp_depth := 64; elsif (min_depth <= 128) then var_temp_depth := 128; elsif (min_depth <= 256) then var_temp_depth := 256; elsif (min_depth <= 512) then var_temp_depth := 512; elsif (min_depth <= 1024) then var_temp_depth := 1024; elsif (min_depth <= 2048) then var_temp_depth := 2048; elsif (min_depth <= 4096) then var_temp_depth := 4096; else -- assume 8192 depth var_temp_depth := 8192; end if; Return (var_temp_depth); end function funct_get_pwr2_depth; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_fifo_cnt_width -- -- Function Description: -- simple function to set the width of the data fifo read -- and write count outputs. ------------------------------------------------------------------- function funct_get_fifo_cnt_width (fifo_depth : integer) return integer is Variable temp_width : integer := 8; begin if (fifo_depth = 1) then temp_width := 1; elsif (fifo_depth = 2) then temp_width := 2; elsif (fifo_depth <= 4) then temp_width := 3; elsif (fifo_depth <= 8) then temp_width := 4; elsif (fifo_depth <= 16) then temp_width := 5; elsif (fifo_depth <= 32) then temp_width := 6; elsif (fifo_depth <= 64) then temp_width := 7; elsif (fifo_depth <= 128) then temp_width := 8; elsif (fifo_depth <= 256) then temp_width := 9; elsif (fifo_depth <= 512) then temp_width := 10; elsif (fifo_depth <= 1024) then temp_width := 11; elsif (fifo_depth <= 2048) then temp_width := 12; elsif (fifo_depth <= 4096) then temp_width := 13; else -- assume 8192 depth temp_width := 14; end if; Return (temp_width); end function funct_get_fifo_cnt_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_cntr_width -- -- Function Description: -- This function calculates the needed counter bit width from the -- number of count sates needed (input). -- ------------------------------------------------------------------- function funct_get_cntr_width (num_cnt_values : integer) return integer is Variable temp_cnt_width : Integer := 0; begin if (num_cnt_values <= 2) then temp_cnt_width := 1; elsif (num_cnt_values <= 4) then temp_cnt_width := 2; elsif (num_cnt_values <= 8) then temp_cnt_width := 3; elsif (num_cnt_values <= 16) then temp_cnt_width := 4; elsif (num_cnt_values <= 32) then temp_cnt_width := 5; elsif (num_cnt_values <= 64) then temp_cnt_width := 6; elsif (num_cnt_values <= 128) then temp_cnt_width := 7; else temp_cnt_width := 8; end if; Return (temp_cnt_width); end function funct_get_cntr_width; -- Constants --------------------------------------------------------------------------- Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant BLK_MEM_FIFO : integer := 1; Constant SRL_FIFO : integer := 0; Constant NOT_NEEDED : integer := 0; Constant WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits Constant TLAST_WIDTH : integer := 1; -- bits Constant EOP_ERR_WIDTH : integer := 1; -- bits Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH; Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH); -- Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN); Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH + --WSTB_WIDTH + TLAST_WIDTH + EOP_ERR_WIDTH; Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1; Constant DATA_OUT_LSB_INDEX : integer := 0; -- Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1; -- Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1; -- Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1; Constant TLAST_OUT_INDEX : integer := DATA_OUT_MSB_INDEX+1; Constant EOP_ERR_OUT_INDEX : integer := TLAST_OUT_INDEX+1; Constant WR_LEN_FIFO_DWIDTH : integer := 8; Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2); Constant LEN_CNTR_WIDTH : integer := 8; Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, LEN_CNTR_WIDTH); Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, LEN_CNTR_WIDTH); Constant WR_XFER_CNTR_WIDTH : integer := 8; Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH); Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH); Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH); Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH); -- Signals --------------------------------------------------------------------------- signal sig_good_sin_strm_dbeat : std_logic := '0'; signal sig_strm_sin_ready : std_logic := '0'; signal sig_sout2sf_tready : std_logic := '0'; signal sig_sf2sout_tvalid : std_logic := '0'; signal sig_sf2sout_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2sout_tlast : std_logic := '0'; signal sig_push_data_fifo : std_logic := '0'; signal sig_pop_data_fifo : std_logic := '0'; signal sig_data_fifo_full : std_logic := '0'; signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_dvalid : std_logic := '0'; signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_wr_addr_posted : std_logic := '0'; signal sig_wr_xfer_cmplt : std_logic := '0'; signal sig_wr_ld_nxt_len : std_logic := '0'; signal sig_push_len_fifo : std_logic := '0'; signal sig_pop_len_fifo : std_logic := '0'; signal sig_len_fifo_full : std_logic := '0'; signal sig_len_fifo_empty : std_logic := '0'; signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0'); signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0'); signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0'); signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_sub_len_uncom_wrcnt : std_logic := '0'; signal sig_incr_uncom_wrcnt : std_logic := '0'; signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_enough_dbeats_rcvd : std_logic := '0'; signal sig_sf2sout_eop_err_out : std_logic := '0'; signal sig_good_fifo_write : std_logic := '0'; begin --(architecture implementation) -- Write Side (S2MM) Control Flags port connections ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ; sig_wr_addr_posted <= wr_addr_posted ; sig_wr_xfer_cmplt <= wr_xfer_cmplt ; sig_wr_ld_nxt_len <= wr_ld_nxt_len ; sig_len_fifo_data_in <= wr_len ; -- Output Stream Port connections sig_sout2sf_tready <= sout2sf_tready ; sf2sout_tvalid <= sig_sf2sout_tvalid ; sf2sout_tdata <= sig_sf2sout_tdata ; sf2sout_tkeep <= sig_sf2sout_tkeep ; sf2sout_tlast <= sig_sf2sout_tlast and sig_sf2sout_tvalid ; sf2sout_error <= sig_sf2sout_eop_err_out ; -- Input Stream port connections sf2sin_tready <= sig_strm_sin_ready; sig_good_sin_strm_dbeat <= sin2sf_tvalid and sig_strm_sin_ready; ---------------------------------------------------------------- -- Packing Logic ------------------------------------------ ---------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_PACKING -- -- If Generate Description: -- Omits any packing logic in the Store and Forward module. -- The Stream and MMap data widths are the same. -- ------------------------------------------------------------ OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate begin sig_good_fifo_write <= sig_good_sin_strm_dbeat; sig_strm_sin_ready <= not(sig_data_fifo_full); sig_push_data_fifo <= sig_good_sin_strm_dbeat; -- Concatonate the Stream inputs into the single FIFO data in value sig_data_fifo_data_in <= sin2sf_error & sin2sf_tlast & -- sin2sf_tkeep & sin2sf_tdata; end generate OMIT_PACKING; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_PACKING -- -- If Generate Description: -- Includes packing logic in the Store and Forward module. -- The MMap Data bus is wider than the Stream width. -- ------------------------------------------------------------ INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH; Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH; Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH + EOP_ERR_WIDTH; Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO); Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, OFFSET_CNTR_WIDTH); Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH); -- Types ----------------------------------------------------------------------------- type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(DATA_SLICE_WIDTH-1 downto 0); type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0); -- local signals signal lsig_data_slice_reg : lsig_data_slice_type; signal lsig_flag_slice_reg : lsig_flag_slice_type; signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0'); signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_ld_offset : std_logic := '0'; signal lsig_incr_offset : std_logic := '0'; signal lsig_offset_cntr_eq_max : std_logic := '0'; signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal lsig_tlast_or : std_logic := '0'; signal lsig_eop_err_or : std_logic := '0'; signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0'); signal lsig_partial_eop_err_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0'); signal lsig_packer_full : std_logic := '0'; signal lsig_packer_empty : std_logic := '0'; signal lsig_set_packer_full : std_logic := '0'; signal lsig_good_push2fifo : std_logic := '0'; signal lsig_first_dbeat : std_logic := '0'; begin -- Assign the flag indicating that a fifo write is going -- to occur at the next rising clock edge. sig_good_fifo_write <= lsig_good_push2fifo; -- Generate the stream ready sig_strm_sin_ready <= not(lsig_packer_full) or lsig_good_push2fifo ; -- Format the FIFO input data sig_data_fifo_data_in <= lsig_eop_err_or & -- MS Bit lsig_tlast_or & lsig_combined_data ; -- LS Bits -- Generate a write to the Data FIFO input sig_push_data_fifo <= lsig_packer_full; -- Generate a flag indicating a write to the DataFIFO -- is going to complete lsig_good_push2fifo <= lsig_packer_full and not(sig_data_fifo_full); -- Generate the control that loads the starting address -- offset for the next input packet lsig_ld_offset <= lsig_first_dbeat and sig_good_sin_strm_dbeat; -- Generate the control for incrementing the offset counter lsig_incr_offset <= sig_good_sin_strm_dbeat; -- Generate a flag indicating the packer input register -- array is full or has loaded the last data beat of -- the input paket lsig_set_packer_full <= sig_good_sin_strm_dbeat and (sin2sf_tlast or lsig_offset_cntr_eq_max); -- Check to see if the offset counter has reached its max -- value lsig_offset_cntr_eq_max <= '1' --when (lsig_0ffset_cntr = OFFSET_CNT_MAX) when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX) Else '0'; -- Mux between the input start offset and the offset counter -- output to use for the packer slice load control. lsig_0ffset_to_to_use <= UNSIGNED(sin2sf_strt_addr_offset) when (lsig_first_dbeat = '1') Else lsig_0ffset_cntr; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_LD_MARKER -- -- Process Description: -- Implements the flop indicating the first databeat of -- an input data packet. -- ------------------------------------------------------------- IMP_OFFSET_LD_MARKER : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_first_dbeat <= '1'; elsif (sig_good_sin_strm_dbeat = '1' and sin2sf_tlast = '0') then lsig_first_dbeat <= '0'; Elsif (sig_good_sin_strm_dbeat = '1' and sin2sf_tlast = '1') Then lsig_first_dbeat <= '1'; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_LD_MARKER; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_CNTR -- -- Process Description: -- Implements the address offset counter that is used to -- steer the data loads into the packer register slices. -- Note that the counter has to be loaded with the starting -- offset plus one to sync up with the data input. ------------------------------------------------------------- IMP_OFFSET_CNTR : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_0ffset_cntr <= (others => '0'); Elsif (lsig_ld_offset = '1') Then lsig_0ffset_cntr <= UNSIGNED(sin2sf_strt_addr_offset) + OFFSET_CNT_ONE; elsif (lsig_incr_offset = '1') then lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PACK_REG_FULL -- -- Process Description: -- Implements the Packer Register full/empty flags -- ------------------------------------------------------------- IMP_PACK_REG_FULL : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_packer_full <= '0'; lsig_packer_empty <= '1'; Elsif (lsig_set_packer_full = '1' and lsig_packer_full = '0') Then lsig_packer_full <= '1'; lsig_packer_empty <= '0'; elsif (lsig_set_packer_full = '0' and lsig_good_push2fifo = '1') then lsig_packer_full <= '0'; lsig_packer_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PACK_REG_FULL; ------------------------------------------------------------ -- For Generate -- -- Label: DO_REG_SLICES -- -- For Generate Description: -- -- Implements the Packng Register Slices -- -- ------------------------------------------------------------ DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate begin -- generate the register load enable for each slice segment based -- on the address offset count value lsig_segment_ld(slice_index) <= '1' when (sig_good_sin_strm_dbeat = '1' and TO_INTEGER(lsig_0ffset_to_to_use) = slice_index) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DATA_SLICE -- -- Process Description: -- Implement a data register slice for the packer. -- ------------------------------------------------------------- IMP_DATA_SLICE : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_data_slice_reg(slice_index) <= (others => '0'); elsif (lsig_segment_ld(slice_index) = '1') then lsig_data_slice_reg(slice_index) <= sin2sf_tdata; -- optional clear of slice reg elsif (lsig_segment_ld(slice_index) = '0' and lsig_good_push2fifo = '1') then lsig_data_slice_reg(slice_index) <= (others => '0'); else null; -- Hold Current State end if; end if; end process IMP_DATA_SLICE; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FLAG_SLICE -- -- Process Description: -- Implement a flag register slice for the packer. -- ------------------------------------------------------------- IMP_FLAG_SLICE : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_flag_slice_reg(slice_index) <= (others => '0'); elsif (lsig_segment_ld(slice_index) = '1') then lsig_flag_slice_reg(slice_index) <= sin2sf_tlast & -- bit 1 sin2sf_error; -- bit 0 elsif (lsig_segment_ld(slice_index) = '0' and lsig_good_push2fifo = '1') then lsig_flag_slice_reg(slice_index) <= (others => '0'); else null; -- Hold Current State end if; end if; end process IMP_FLAG_SLICE; end generate DO_REG_SLICES; -- Do the OR functions of the Flags ------------------------------------- lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ; lsig_eop_err_or <= lsig_partial_eop_err_or(MMAP2STRM_WIDTH_RATO-1); lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1); lsig_partial_eop_err_or(0) <= lsig_flag_slice_reg(0)(0); ------------------------------------------------------------ -- For Generate -- -- Label: DO_FLAG_OR -- -- For Generate Description: -- Implement the OR of the TLAST and EOP Error flags. -- -- -- ------------------------------------------------------------ DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate begin lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or --lsig_partial_tlast_or(slice_index); lsig_flag_slice_reg(slice_index)(1); lsig_partial_eop_err_or(slice_index) <= lsig_partial_eop_err_or(slice_index-1) or --lsig_partial_eop_err_or(slice_index); lsig_flag_slice_reg(slice_index)(0); end generate DO_FLAG_OR; ------------------------------------------------------------ -- For Generate -- -- Label: DO_DATA_COMBINER -- -- For Generate Description: -- Combines the Data Slice register outputs into a single -- vector for input to the Data FIFO. -- -- ------------------------------------------------------------ DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate begin lsig_combined_data((slice_indexDATA_SLICE_WIDTH)-1 downto (slice_index-1)DATA_SLICE_WIDTH) <= lsig_data_slice_reg(slice_index-1); end generate DO_DATA_COMBINER; end generate INCLUDE_PACKING; ---------------------------------------------------------------- -- Data FIFO Logic ------------------------------------------ ---------------------------------------------------------------- -- FIFO Input attachments -- sig_push_data_fifo <= sig_good_sin_strm_dbeat; -- -- Concatonate the Stream inputs into the single FIFO data in value -- sig_data_fifo_data_in <= sin2sf_error & -- sin2sf_tlast & -- sin2sf_tkeep & -- sin2sf_tdata; -- FIFO Output to output stream attachments sig_sf2sout_tvalid <= sig_data_fifo_dvalid ; sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto DATA_OUT_LSB_INDEX); -- sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto -- TSTRB_OUT_LSB_INDEX); -- When this Store and Forward is enabled, the Write Data Controller ignores the -- TKEEP input so this is not sent through the FIFO. sig_sf2sout_tkeep <= (others => '1'); sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ; sig_sf2sout_eop_err_out <= sig_data_fifo_data_out(EOP_ERR_OUT_INDEX) ; -- FIFO Rd/WR Controls sig_pop_data_fifo <= sig_sout2sf_tready and sig_data_fifo_dvalid; ------------------------------------------------------------ -- Instance: I_DATA_FIFO -- -- Description: -- Implements the Store and Forward data FIFO (synchronous) -- ------------------------------------------------------------ I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord generic map ( C_DWIDTH => DATA_FIFO_WIDTH , C_DEPTH => DATA_FIFO_DEPTH , C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH , C_NEED_ALMOST_EMPTY => NOT_NEEDED , C_NEED_ALMOST_FULL => NOT_NEEDED , C_USE_BLKMEM => BLK_MEM_FIFO , C_FAMILY => C_FAMILY ) port map ( -- Inputs SFIFO_Sinit => reset , SFIFO_Clk => aclk , SFIFO_Wr_en => sig_push_data_fifo , SFIFO_Din => sig_data_fifo_data_in , SFIFO_Rd_en => sig_pop_data_fifo , SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs SFIFO_DValid => sig_data_fifo_dvalid , SFIFO_Dout => sig_data_fifo_data_out , SFIFO_Full => sig_data_fifo_full , SFIFO_Empty => open , SFIFO_Almost_full => open , SFIFO_Almost_empty => open , SFIFO_Rd_count => open , SFIFO_Rd_count_minus1 => open , SFIFO_Wr_count => open , SFIFO_Rd_ack => open ); -------------------------------------------------------------------- -- Write Side Control Logic -------------------------------------------------------------------- -- Convert the LEN fifo data output to unsigned sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out); -- Resize the unsigned LEN output to the Data FIFO writecount width sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH); -- The actual number of databeats needed for the queued write transfer -- is the current LEN fifo output plus 1. sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1; -- Compare the uncommited receved data beat count to that needed -- for the next queued write request. sig_enough_dbeats_rcvd <= '1' When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt) else '0'; -- Increment the uncommited databeat counter on a good input -- stream databeat (Read Side of SF) -- sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat; sig_incr_uncom_wrcnt <= sig_good_fifo_write; -- Subtract the current number of databeats needed from the -- uncommited databeat counter when the associated transfer -- address/qualifiers have been posted to the AXI Write -- Address Channel sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_UNCOM_DBEAT_CNTR -- -- Process Description: -- Implements the counter that keeps track of the received read -- data beat count that has not been commited to a transfer on -- the write side with a Write Address posting. -- ------------------------------------------------------------- IMP_UNCOM_DBEAT_CNTR : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then sig_uncom_wrcnt <= UNCOM_WRCNT_0; elsif (sig_incr_uncom_wrcnt = '1' and sig_sub_len_uncom_wrcnt = '1') then sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len; elsif (sig_incr_uncom_wrcnt = '1' and sig_sub_len_uncom_wrcnt = '0') then sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1; elsif (sig_incr_uncom_wrcnt = '0' and sig_sub_len_uncom_wrcnt = '1') then sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed; else null; -- hold current value end if; end if; end process IMP_UNCOM_DBEAT_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_ADDR_POST_FLAG -- -- Process Description: -- Implements the flag indicating that the pending write -- transfer's data beat count has been received on the input -- side of the Data FIFO. This means the Write side can post -- the associated write address to the AXI4 bus and the -- associated write data transfer can complete without CDMA -- throttling the Write Data Channel. -- -- The flag is cleared immediately after an address is posted -- to prohibit a second unauthorized posting while the control -- logic stabilizes to the next LEN FIFO value --. ------------------------------------------------------------- IMP_WR_ADDR_POST_FLAG : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1' or sig_wr_addr_posted = '1') then sig_ok_to_post_wr_addr <= '0'; else sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and sig_enough_dbeats_rcvd; end if; end if; end process IMP_WR_ADDR_POST_FLAG; ------------------------------------------------------------- -- LEN FIFO logic -- The LEN FIFO stores the xfer lengths needed for each queued -- write transfer in the DataMover S2MM Write Data Controller. sig_push_len_fifo <= sig_wr_ld_nxt_len and not(sig_len_fifo_full); sig_pop_len_fifo <= wr_addr_posted and not(sig_len_fifo_empty); ------------------------------------------------------------ -- Instance: I_WR_LEN_FIFO -- -- Description: -- Implement the LEN FIFO using SRL FIFO elements -- ------------------------------------------------------------ I_WR_LEN_FIFO : entity proc_common_v4_0.srl_fifo_f generic map ( C_DWIDTH => WR_LEN_FIFO_DWIDTH , C_DEPTH => WR_LEN_FIFO_DEPTH , C_FAMILY => C_FAMILY ) port map ( Clk => aclk , Reset => reset , FIFO_Write => sig_push_len_fifo , Data_In => sig_len_fifo_data_in , FIFO_Read => sig_pop_len_fifo , Data_Out => sig_len_fifo_data_out , FIFO_Empty => sig_len_fifo_empty , FIFO_Full => sig_len_fifo_full , Addr => open ); end implementation;	bsd-2-clause	9c96fdb7e61a300e197902c81c09e91f	0.418106	5.006999	false	false	false	false
NicoLedwith/Dr.AluOpysel	Works/prog_rom.vhd	2	19,877	----------------------------------------------------------------------------- -- Definition of a single port ROM for RATASM defined by prog_rom.psm -- -- Generated by RATASM Assembler -- -- Standard IEEE libraries -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; ----------------------------------------------------------------------------- entity prog_rom is port ( ADDRESS : in std_logic_vector(9 downto 0); INSTRUCTION : out std_logic_vector(17 downto 0); CLK : in std_logic); end prog_rom; architecture low_level_definition of prog_rom is ----------------------------------------------------------------------------- -- Attributes to define ROM contents during implementation synthesis. -- The information is repeated in the generic map for functional simulation. ----------------------------------------------------------------------------- attribute INIT_00 : string; attribute INIT_01 : string; attribute INIT_02 : string; attribute INIT_03 : string; attribute INIT_04 : string; attribute INIT_05 : string; attribute INIT_06 : string; attribute INIT_07 : string; attribute INIT_08 : string; attribute INIT_09 : string; attribute INIT_0A : string; attribute INIT_0B : string; attribute INIT_0C : string; attribute INIT_0D : string; attribute INIT_0E : string; attribute INIT_0F : string; attribute INIT_10 : string; attribute INIT_11 : string; attribute INIT_12 : string; attribute INIT_13 : string; attribute INIT_14 : string; attribute INIT_15 : string; attribute INIT_16 : string; attribute INIT_17 : string; attribute INIT_18 : string; attribute INIT_19 : string; attribute INIT_1A : string; attribute INIT_1B : string; attribute INIT_1C : string; attribute INIT_1D : string; attribute INIT_1E : string; attribute INIT_1F : string; attribute INIT_20 : string; attribute INIT_21 : string; attribute INIT_22 : string; attribute INIT_23 : string; attribute INIT_24 : string; attribute INIT_25 : string; attribute INIT_26 : string; attribute INIT_27 : string; attribute INIT_28 : string; attribute INIT_29 : string; attribute INIT_2A : string; attribute INIT_2B : string; attribute INIT_2C : string; attribute INIT_2D : string; attribute INIT_2E : string; attribute INIT_2F : string; attribute INIT_30 : string; attribute INIT_31 : string; attribute INIT_32 : string; attribute INIT_33 : string; attribute INIT_34 : string; attribute INIT_35 : string; attribute INIT_36 : string; attribute INIT_37 : string; attribute INIT_38 : string; attribute INIT_39 : string; attribute INIT_3A : string; attribute INIT_3B : string; attribute INIT_3C : string; attribute INIT_3D : string; attribute INIT_3E : string; attribute INIT_3F : string; attribute INITP_00 : string; attribute INITP_01 : string; attribute INITP_02 : string; attribute INITP_03 : string; attribute INITP_04 : string; attribute INITP_05 : string; attribute INITP_06 : string; attribute INITP_07 : string; ---------------------------------------------------------------------- -- Attributes to define ROM contents during implementation synthesis. ---------------------------------------------------------------------- attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_01 of ram_1024_x_18 : label is "86C181F181098179A000872169276712680066C087D1663F68124D3967118781"; attribute INIT_02 of ram_1024_x_18 : label is "6712800287D166C0880148918002815187D166004899A178D301D201478980E8"; attribute INIT_03 of ram_1024_x_18 : label is "822B0D11800287D1680187D166C0680087D15341682687D16600524151396827"; attribute INIT_04 of ram_1024_x_18 : label is "823086C1842186C1831186C1828186C18781A0018002822882324D9082324D98"; attribute INIT_05 of ram_1024_x_18 : label is "690C671468088721690C670F68088721690C670A680887516914670A68086607"; attribute INIT_06 of ram_1024_x_18 : label is "670A681A87D167CA681987516911670D681D87516914670A6818660780028721"; attribute INIT_07 of ram_1024_x_18 : label is "87D16713681B87D16714681A87D16714681987D1670C681C87D1670B681B87D1"; attribute INIT_08 of ram_1024_x_18 : label is "87D1670B681087516914670A681587516914670A680F6607800287D16712681C"; attribute INIT_09 of ram_1024_x_18 : label is "681387D16710681387D1670F681287D1670E681287D1670D681187D1670C6811"; attribute INIT_0A of ram_1024_x_18 : label is "477187D1663F68124769CD014E69800287D16713681487D16712681487D16711"; attribute INIT_0B of ram_1024_x_18 : label is "670C800287D166006812477187D1663F681247698D014E69800287D166006812"; attribute INIT_0C of ram_1024_x_18 : label is "85A186C18109854986C181098549800287D1660068126713800287D166006812"; attribute INIT_0D of ram_1024_x_18 : label is "3C0086EBDB017B1FDC017CFFDD017DFFA00386C18109862185A186C1810985F9"; attribute INIT_0E of ram_1024_x_18 : label is "8002875B4748870187D189018002872B4848880187D18901800286CB3D0086DB"; attribute INIT_0F of ram_1024_x_18 : label is "A8110401041F053F45414439800287930D1E8D0187216927680047696D006600"; attribute INIT_10 of ram_1024_x_18 : label is "000000000000000000000000000080024692449045912580A829040180002540"; attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3F of ram_1024_x_18 : label is "8648000000000000000000000000000000000000000000000000000000000000"; attribute INITP_00 of ram_1024_x_18 : label is "3CF3CF3CF3CFCFF4FCFCFCFF0000140034CF0CC3D38430A0004FF3CC00000000"; attribute INITP_01 of ram_1024_x_18 : label is "1A04E3CF422422488BBB400000013F4FD3C3C84F0F213CF3CF3CF3CF3CFCFF4F"; attribute INITP_02 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000000000000000000001FE16"; attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; begin ---------------------------------------------------------------------- --Instantiate the Xilinx primitive for a block RAM --INIT values repeated to define contents for functional simulation ---------------------------------------------------------------------- ram_1024_x_18: RAMB16_S18 --synthesitranslate_off --INIT values repeated to define contents for functional simulation generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"86C181F181098179A000872169276712680066C087D1663F68124D3967118781", INIT_02 => X"6712800287D166C0880148918002815187D166004899A178D301D201478980E8", INIT_03 => X"822B0D11800287D1680187D166C0680087D15341682687D16600524151396827", INIT_04 => X"823086C1842186C1831186C1828186C18781A0018002822882324D9082324D98", INIT_05 => X"690C671468088721690C670F68088721690C670A680887516914670A68086607", INIT_06 => X"670A681A87D167CA681987516911670D681D87516914670A6818660780028721", INIT_07 => X"87D16713681B87D16714681A87D16714681987D1670C681C87D1670B681B87D1", INIT_08 => X"87D1670B681087516914670A681587516914670A680F6607800287D16712681C", INIT_09 => X"681387D16710681387D1670F681287D1670E681287D1670D681187D1670C6811", INIT_0A => X"477187D1663F68124769CD014E69800287D16713681487D16712681487D16711", INIT_0B => X"670C800287D166006812477187D1663F681247698D014E69800287D166006812", INIT_0C => X"85A186C18109854986C181098549800287D1660068126713800287D166006812", INIT_0D => X"3C0086EBDB017B1FDC017CFFDD017DFFA00386C18109862185A186C1810985F9", INIT_0E => X"8002875B4748870187D189018002872B4848880187D18901800286CB3D0086DB", INIT_0F => X"A8110401041F053F45414439800287930D1E8D0187216927680047696D006600", INIT_10 => X"000000000000000000000000000080024692449045912580A829040180002540", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"8648000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"3CF3CF3CF3CFCFF4FCFCFCFF0000140034CF0CC3D38430A0004FF3CC00000000", INITP_01 => X"1A04E3CF422422488BBB400000013F4FD3C3C84F0F213CF3CF3CF3CF3CFCFF4F", INITP_02 => X"000000000000000000000000000000000000000000000000000000000001FE16", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") --synthesis translate_on port map( DI => "0000000000000000", DIP => "00", EN => '1', WE => '0', SSR => '0', CLK => clk, ADDR => address, DO => INSTRUCTION(15 downto 0), DOP => INSTRUCTION(17 downto 16)); -- end low_level_definition; -- ---------------------------------------------------------------------- -- END OF FILE prog_rom.vhd ----------------------------------------------------------------------	mit	798ba7c7b4943cb9ec43507215a7ebb6	0.735725	5.044924	false	false	false	false
Yarr/Yarr-fw	rtl/spartan6/rx-core/wb_rx_core.vhd	1	9,504	-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: RX core -- # Outputs are synchronous to wb_clk_i -- #################################### -- # Adress Map: -- # Adr[3:0]: -- # 0x0 : RX Enable Mask library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity wb_rx_core is generic ( g_NUM_RX : integer range 1 to 32 := 1 ); port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- RX IN rx_clk_i : in std_logic; rx_serdes_clk_i : in std_logic; rx_clk_locked_i : in std_logic; rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0); trig_tag_i : in std_logic_vector(31 downto 0); -- RX OUT (sync to sys_clk) rx_valid_o : out std_logic; rx_data_o : out std_logic_vector(31 downto 0); busy_o : out std_logic; debug_o : out std_logic_vector(31 downto 0) ); end wb_rx_core; architecture behavioral of wb_rx_core is function log2_ceil(val : integer) return natural is variable result : natural; begin for i in 0 to g_NUM_RX-1 loop if (val <= (2 ** i)) then result := i; exit; end if; end loop; return result; end function; constant c_ALL_ZEROS : std_logic_vector(g_NUM_RX-1 downto 0) := (others => '0'); component rr_arbiter generic ( g_CHANNELS : integer := g_NUM_RX ); port ( -- sys connect clk_i : in std_logic; rst_i : in std_logic; -- requests req_i : in std_logic_vector(g_CHANNELS-1 downto 0); -- grants gnt_o : out std_logic_vector(g_CHANNELS-1 downto 0) ); end component rr_arbiter; component fei4_rx_channel port ( -- Sys connect rst_n_i : in std_logic; clk_160_i : in std_logic; clk_640_i : in std_logic; enable_i : in std_logic; -- Input rx_data_i : in std_logic; trig_tag_i : in std_logic_vector(31 downto 0); -- Output rx_data_o : out std_logic_vector(25 downto 0); rx_valid_o : out std_logic; rx_stat_o : out std_logic_vector(7 downto 0); rx_data_raw_o : out std_logic_vector(7 downto 0) ); end component; COMPONENT rx_channel_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; type rx_data_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(25 downto 0); type rx_data_fifo_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(31 downto 0); type rx_stat_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(7 downto 0); signal rx_data : rx_data_array; signal rx_valid : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_stat : rx_stat_array; signal rx_data_raw : rx_stat_array; signal rx_fifo_dout :rx_data_fifo_array; signal rx_fifo_din : rx_data_fifo_array; signal rx_fifo_full : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_empty : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_rden : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_rden_t : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_wren : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_enable : std_logic_vector(31 downto 0); signal rx_serdes_clk : std_logic_vector(3 downto 0); signal channel : integer range 0 to g_NUM_RX-1; signal debug : std_logic_vector(31 downto 0); begin debug_o <= debug; debug(7 downto 0) <= rx_stat(0); debug(15 downto 8) <= rx_data_raw(0); debug(16) <= rx_valid(0); wb_proc: process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; rx_enable <= (others => '0'); wb_stall_o <= '0'; elsif rising_edge(wb_clk_i) then wb_ack_o <= '0'; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '1') then if (wb_adr_i(3 downto 0) = x"0") then -- Set enable mask wb_ack_o <= '1'; rx_enable <= wb_dat_i; else wb_ack_o <= '1'; end if; else if (wb_adr_i(3 downto 0) = x"0") then -- Read enable mask wb_dat_o <= rx_enable; wb_ack_o <= '1'; else wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end if; end if; end if; end if; end process wb_proc; -- Arbiter cmp_rr_arbiter : rr_arbiter port map ( clk_i => wb_clk_i, rst_i => not rst_n_i, req_i => not rx_fifo_empty, gnt_o => rx_fifo_rden_t ); --rx_valid_o <= '0' when (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) else '1'; --rx_data_o <= x"DEADBEEF" when (unsigned(rx_fifo_rden) = 0) else rx_fifo_dout(log2_ceil(to_integer(unsigned(rx_fifo_rden)))); reg_proc : process(wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then rx_fifo_rden <= (others => '0'); rx_valid_o <= '0'; channel <= 0; elsif rising_edge(wb_clk_i) then rx_fifo_rden <= rx_fifo_rden_t; channel <= log2_ceil(to_integer(unsigned(rx_fifo_rden_t))); if (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) then rx_valid_o <= '0'; rx_data_o <= x"DEADBEEF"; else rx_valid_o <= '1'; rx_data_o <= rx_fifo_dout(channel); end if; end if; end process reg_proc; -- cmp_ioclk_640_buf_0 : BUFG -- port map ( -- O => rx_serdes_clk(0), -- I => rx_serdes_clk_i); -- -- cmp_ioclk_640_buf_1 : BUFG -- port map ( -- O => rx_serdes_clk(1), -- I => rx_serdes_clk_i); BUFPLL_640_A : BUFPLL generic map ( DIVIDE => 4, -- DIVCLK divider (1-8) ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) ) port map ( IOCLK => rx_serdes_clk(0), -- 1-bit output: Output I/O clock LOCK => open, -- 1-bit output: Synchronized LOCK output SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2) GCLK => rx_clk_i, -- 1-bit input: BUFG clock input LOCKED => rx_clk_locked_i, -- 1-bit input: LOCKED input from PLL PLLIN => rx_serdes_clk_i -- 1-bit input: Clock input from PLL ); BUFPLL_640_B : BUFPLL generic map ( DIVIDE => 4, -- DIVCLK divider (1-8) ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) ) port map ( IOCLK => rx_serdes_clk(1), -- 1-bit output: Output I/O clock LOCK => open, -- 1-bit output: Synchronized LOCK output SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2) GCLK => rx_clk_i, -- 1-bit input: BUFG clock input LOCKED => rx_clk_locked_i, -- 1-bit input: LOCKED input from PLL PLLIN => rx_serdes_clk_i -- 1-bit input: Clock input from PLL ); -- Generate Rx Channels busy_o <= '0' when (rx_fifo_full = c_ALL_ZEROS) else '1'; rx_channels: for I in 0 to g_NUM_RX-1 generate begin bank2_1: if I<4 generate begin cmp_fei4_rx_channel: fei4_rx_channel PORT MAP( rst_n_i => rst_n_i, clk_160_i => rx_clk_i, clk_640_i => rx_serdes_clk(0), enable_i => rx_enable(I), rx_data_i => rx_data_i(I), trig_tag_i => trig_tag_i, rx_data_o => rx_data(I), rx_valid_o => rx_valid(I), rx_stat_o => rx_stat(I), rx_data_raw_o => rx_data_raw(I) ); end generate bank2_1; bank2_2: if (I>3 and I<15) generate begin cmp_fei4_rx_channel: fei4_rx_channel PORT MAP( rst_n_i => rst_n_i, clk_160_i => rx_clk_i, clk_640_i => rx_serdes_clk(0), enable_i => rx_enable(I), rx_data_i => not rx_data_i(I), trig_tag_i => trig_tag_i, rx_data_o => rx_data(I), rx_valid_o => rx_valid(I), rx_stat_o => rx_stat(I), rx_data_raw_o => rx_data_raw(I) ); end generate bank2_2; bank0: if I>=15 generate begin cmp_fei4_rx_channel: fei4_rx_channel PORT MAP( rst_n_i => rst_n_i, clk_160_i => rx_clk_i, clk_640_i => rx_serdes_clk(1), enable_i => rx_enable(I), rx_data_i => not rx_data_i(I), trig_tag_i => trig_tag_i, rx_data_o => rx_data(I), rx_valid_o => rx_valid(I), rx_stat_o => rx_stat(I), rx_data_raw_o => rx_data_raw(I) ); end generate bank0; rx_fifo_din(I) <= STD_LOGIC_VECTOR(TO_UNSIGNED(I,6)) & rx_data(I); rx_fifo_wren(I) <= rx_valid(I) and rx_enable(I); cmp_rx_channel_fifo : rx_channel_fifo PORT MAP ( rst => not rst_n_i, wr_clk => rx_clk_i, rd_clk => wb_clk_i, din => rx_fifo_din(I), wr_en => rx_fifo_wren(I), rd_en => rx_fifo_rden(I), dout => rx_fifo_dout(I), full => rx_fifo_full(I), empty => rx_fifo_empty(I) ); end generate; end behavioral;	gpl-3.0	e2a34a0d68078197c3e5db8faf61fe9c	0.559975	2.72087	false	false	false	false
siavooshpayandehazad/TTU_CPU_Project	pico_CPU/PicoCPU.vhd	1	1,867	library IEEE; use IEEE.std_logic_1164.all; USE ieee.std_logic_unsigned.ALL; use work.pico_cpu.all; entity PicoCPU is port( rst: in std_logic; clk: in std_logic; FlagOut: out std_logic_vector ( 3 downto 0); output: out std_logic_vector ( CPU_Bitwidth-1 downto 0) ); end PicoCPU; architecture RTL of PicoCPU is --------------------------------------------- -- Signals --------------------------------------------- signal Instr: std_logic_vector (CPU_Instwidth-1 downto 0):= (others=>'0'); signal InstrAdd , Mem_Rd_Address, Mem_Wrt_Address, DPUData, MEMDATA, DPU_Result: std_logic_vector (CPU_Bitwidth-1 downto 0) := (others=>'0'); signal MemRW: std_logic := '0'; signal DPUFlags: std_logic_vector (3 downto 0):= (others=>'0'); signal DPUCommand : std_logic_vector (10 downto 0):= (others=>'0'); signal Reg_in_sel: std_logic_vector (7 downto 0):= (others=>'0'); signal Reg_out_sel: std_logic_vector (2 downto 0):= (others=>'0'); begin --------------------------------------------- -- component instantiation --------------------------------------------- ControlUnit_comp: ControlUnit generic map (BitWidth => CPU_Bitwidth, InstructionWidth => CPU_Instwidth) port map (rst, clk, Instr ,InstrAdd , Mem_Rd_Address, Mem_Wrt_Address , MemRW, DPUFlags, DPUData,DPUCommand,Reg_in_sel,Reg_out_sel,DPU_Result); --instruction memory InstMem_comp: InstMem generic map (BitWidth => CPU_Bitwidth, InstructionWidth => CPU_Instwidth) port map (InstrAdd,Instr); --datapath unit DPU_comp: DPU generic map (BitWidth => CPU_Bitwidth) port map (MEMDATA, DPUData, clk,DPUCommand,Reg_in_sel,Reg_out_sel,rst,DPUFlags,DPU_Result); --memory Mem_comp: Mem generic map (BitWidth => CPU_Bitwidth) port map (Mem_Rd_Address, DPU_Result, Mem_Wrt_Address, clk,MemRW , rst , MEMDATA); FlagOut <= DPUFlags; output <= DPU_Result; end RTL;	gpl-2.0	87d1e72f53579bc390cf4820e6d19c26	0.631494	3.406934	false	false	false	false
niketancm/tsea26	lab2-3/rtl/pc_fsm.vhd	1	6,039	library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity pc_fsm is port ( clk_i, reset_i: in std_logic; jump_decision_i: in std_logic; lc_pfc_loop_flag_i: in std_logic; lc_pfc_loope_i: in std_logic_vector(15 downto 0); ctrl_i: in std_logic_vector(5 downto 0); interrupt: in std_logic; pc_addr_bus_i: in std_logic_vector(15 downto 0); pfc_pc_add_opa_sel_o: out std_logic; pfc_lc_loopn_sel_o: out std_logic; pfc_pc_sel_o: out std_logic_vector(2 downto 0); pfc_inst_nop_o: out std_logic); end pc_fsm; architecture pc_fsm_rtl of pc_fsm is signal ctrl_c1 : std_logic_vector(5 downto 0); signal ctrl_c2 : std_logic_vector(5 downto 0); signal ctrl_c3 : std_logic_vector(5 downto 0); signal s0_state_sel : std_logic_vector (2 downto 0); signal jump_case_sel : std_logic_vector (1 downto 0); signal ctrl_i_PFC_JUMP : std_logic; signal ctrl_c2_PFC_RET : std_logic; signal ctrl_i_PFC_DELAY_SLOT : std_logic_vector (1 downto 0); type StateType is (s0,s1,s3,s4,s5,s6,s7,s8,s9,s10,s13); signal next_state : StateType; signal state : StateType; begin ctrl_i_PFC_DELAY_SLOT <= ctrl_i(4 downto 3); ctrl_i_PFC_JUMP <= ctrl_i(2); ctrl_c2_PFC_RET <= ctrl_c2(1); -- register generation logic process (clk_i) begin if clk_i'event and clk_i = '1' then if ( reset_i = '0' ) then state <= s0 ; else ctrl_c1 <= ctrl_i ; ctrl_c2 <= ctrl_c1 ; ctrl_c3 <= ctrl_c2 ; state <= next_state ; end if; end if; end process; -- next state logic s0_state_sel <= ctrl_i_PFC_JUMP & ctrl_i_PFC_DELAY_SLOT; process (s0_state_sel, state, ctrl_i) begin next_state <= s0 ; case state is when s0 => case s0_state_sel is when "100" => next_state <= s4; -- What is the next state? when "101" => next_state <= s5; -- What is the next state? when "110" => next_state <= s3; -- What is the next state? when "111" => next_state <= s1; when others => next_state <= s0; end case; when s1 => next_state <= s7 ; when s3 => next_state <= s6 ; when s4 => next_state <= s8 ; when s5 => next_state <= s8 ; when s6 => next_state <= s10 ; when s7 => next_state <= s9 ; when s8 => next_state <= s10 ; when s9 => if (ctrl_c2_PFC_RET = '1') then next_state <= s13; else next_state <= s0 ; -- What is the next state? end if; when s10 => if (ctrl_c2_PFC_RET = '1') then next_state <= s13; else next_state <= s0 ; -- What is the next state? end if; when s13 => next_state <= s0 ; when others => next_state <= s0; end case; end process; jump_case_sel <= ctrl_c2_PFC_RET & jump_decision_i; process (state, jump_case_sel, s0_state_sel) begin pfc_pc_add_opa_sel_o <= '0'; --Default value pfc_pc_sel_o<= "001"; --Default value pfc_inst_nop_o<='0'; --Default value pfc_lc_loopn_sel_o<='0'; --Default value case state is when s0 => if s0_state_sel = "100" then pfc_pc_sel_o<= "000"; end if; when s1 => -- Empty when s3 => -- Empty when s4 => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='1'; when s5 => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='0'; when s6 => case jump_case_sel is when "10" \| "11" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='0'; when "01" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "011"; pfc_inst_nop_o<='0'; when "00" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='0'; when others => --Empty end case; when s7 => case jump_case_sel is when "10" \| "11" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='0'; when "01" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "011"; pfc_inst_nop_o<='0'; when "00" => -- Empty when others => --Empty end case; when s8 => case jump_case_sel is when "10" \| "11"=> pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='1'; when "01" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "011"; pfc_inst_nop_o<='1'; when "00" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='1'; when others => --Empty end case; when s9 => if ctrl_c3(1) = '1' then pfc_pc_sel_o<= "110"; else pfc_pc_sel_o<= "001"; end if; when s10 => if ctrl_c3(1) = '1' then pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "110"; pfc_inst_nop_o<='1'; else pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "001"; pfc_inst_nop_o<='1'; --nop for the jum calls end if; when s13 => pfc_pc_sel_o<= "001"; pfc_inst_nop_o<='1'; when others => end case; end process; -- case: default end pc_fsm_rtl;	gpl-2.0	07585076911592881a8731c6aa955760	0.451565	3.057722	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_scatter.vhd	1	69,756	------------------------------------------------------------------------------- -- axi_datamover_s2mm_scatter.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_scatter.vhd -- -- Description: -- This file implements the S2MM Scatter support module. Scatter requires -- the input Stream to be stopped and disected at command boundaries. The -- Scatter module splits the input stream data at the command boundaries -- and force feeds the S2MM DRE with data and source alignment. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_s2mm_scatter.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 6/20/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added 512 and 1024 data width support -- ^^^^^^ -- -- DET 6/29/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Incorporated the Indeterminate BTT mode overflow absorption -- changes needed by AXI VDMA. -- ^^^^^^ -- -- DET 7/18/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- -- Per CR617164 -- - Added TSTRB fifo empty qualifier to the overflow absorption logic -- in the IBTT mode case. Also added additional qualification to the -- sig_gated_fifo_freeze_out signal in the IBTT mode IfGen. -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_strb_gen2; use axi_datamover_v5_1.axi_datamover_mssai_skid_buf; use axi_datamover_v5_1.axi_datamover_fifo; use axi_datamover_v5_1.axi_datamover_slice; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_scatter is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates if the IBTT Indeterminate BTT is enabled -- (external to this module) C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the S2MM DRE alignment control ports C_BTT_USED : Integer range 8 to 23 := 16; -- Sets the width of the BTT input port C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the input and output data streams C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_FAMILY : String := "virtex7" -- Specifies the target FPGA device family ); port ( -- Clock and Reset inputs -------------------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ---------------------------------------------------------------------------- -- DRE Realign Controller I/O ---------------------------------------------- -- scatter2drc_cmd_ready : Out std_logic; -- -- Indicates the Scatter Engine is ready to accept a new command -- -- drc2scatter_push_cmd : In std_logic; -- -- Indicates a new command is being read from the command que -- -- drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); -- -- Indicates the new command's BTT value -- -- drc2scatter_eof : In std_logic; -- -- Indicates that the input command is also the last of a packet -- -- This input is ignored when C_ENABLE_INDET_BTT = 1 -- ---------------------------------------------------------------------------- -- DRE Source Alignment --------------------------------------------------------- -- scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- Indicates the next source alignment to the DRE control -- -------------------------------------------------------------------------------- -- AXI Slave Stream In ---------------------------------------------------------- -- s2mm_strm_tready : Out Std_logic; -- -- AXI Stream READY input -- -- s2mm_strm_tvalid : In std_logic; -- -- AXI Stream VALID Output -- -- s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- AXI Stream data output -- -- s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- AXI Stream STRB output -- -- s2mm_strm_tlast : In std_logic; -- -- AXI Stream LAST output -- -------------------------------------------------------------------------------- -- Stream Out to S2MM DRE ------------------------------------------------------- -- drc2scatter_tready : In Std_logic; -- -- S2MM DRE Stream READY input -- -- scatter2drc_tvalid : Out std_logic; -- -- S2MM DRE VALID Output -- -- scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- S2MM DRE data output -- -- scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- S2MM DRE STRB output -- -- scatter2drc_tlast : Out std_logic; -- -- S2MM DRE LAST output -- -- scatter2drc_flush : Out std_logic; -- -- S2MM DRE LAST output -- -- scatter2drc_eop : Out std_logic; -- -- S2MM DRE End of Packet marker -- -------------------------------------------------------------------------------- -- Premature TLAST assertion error flag --------------------------------------- -- scatter2drc_tlast_error : Out std_logic -- -- When asserted, this indicates the scatter Engine detected -- -- a Early/Late TLAST assertion on the incoming data stream -- -- relative to the commands given to the DataMover Cmd FIFO. -- ------------------------------------------------------------------------------- ); end entity axi_datamover_s2mm_scatter; architecture implementation of axi_datamover_s2mm_scatter is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declaration ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_index -- -- Function Description: -- This function calculates the bus bit index corresponding -- to the MSB of the Slice lane index input and the Slice width. -- ------------------------------------------------------------------- function get_start_index (lane_index : integer; lane_width : integer) return integer is Variable bit_index_start : Integer := 0; begin bit_index_start := lane_indexlane_width; return(bit_index_start); end function get_start_index; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_index -- -- Function Description: -- This function calculates the bus bit index corresponding -- to the LSB of the Slice lane index input and the Slice width. -- ------------------------------------------------------------------- function get_end_index (lane_index : integer; lane_width : integer) return integer is Variable bit_index_end : Integer := 0; begin bit_index_end := (lane_indexlane_width) + (lane_width-1); return(bit_index_end); end function get_end_index; ------------------------------------------------------------------- -- Function -- -- Function Name: func_num_offset_bits -- -- Function Description: -- This function calculates the number of bits needed for specifying -- a byte lane offset for the input transfer data width. -- ------------------------------------------------------------------- function func_num_offset_bits (stream_dwidth_value : integer) return integer is Variable num_offset_bits_needed : Integer range 1 to 7 := 1; begin case stream_dwidth_value is when 8 => -- 1 byte lanes num_offset_bits_needed := 1; when 16 => -- 2 byte lanes num_offset_bits_needed := 1; when 32 => -- 4 byte lanes num_offset_bits_needed := 2; when 64 => -- 8 byte lanes num_offset_bits_needed := 3; when 128 => -- 16 byte lanes num_offset_bits_needed := 4; when 256 => -- 32 byte lanes num_offset_bits_needed := 5; when 512 => -- 64 byte lanes num_offset_bits_needed := 6; when others => -- 1024 bits with 128 byte lanes num_offset_bits_needed := 7; end case; Return (num_offset_bits_needed); end function func_num_offset_bits; function func_fifo_prim (stream_dwidth_value : integer) return integer is Variable prim_needed : Integer range 0 to 2 := 1; begin case stream_dwidth_value is when 8 => -- 1 byte lanes prim_needed := 2; when 16 => -- 2 byte lanes prim_needed := 2; when 32 => -- 4 byte lanes prim_needed := 2; when 64 => -- 8 byte lanes prim_needed := 2; when 128 => -- 16 byte lanes prim_needed := 0; when others => -- 256 bits and above prim_needed := 0; end case; Return (prim_needed); end function func_fifo_prim; -- Constant Declarations ------------------------------------------------- Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '0'; Constant BYTE_WIDTH : integer := 8; -- bits Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH; Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES; Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1; Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1; Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0'); Constant CMD_BTT_WIDTH : Integer := C_BTT_USED; Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8; Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH); -- Minimum Number of bits needed to represent the byte lane position within the Stream Data Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1; -- Minimum Number of bits needed to represent the maximum per dbeat increment value Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS); Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS); Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS); Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS; Constant TSTRB_FIFO_DEPTH : integer := 16; Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit 1 + -- EOF Bit 1 + -- Freeze Bit MSSAI_INDEX_WIDTH + -- MSSAI Value STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH); Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1; Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1; Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1; Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1; Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1); Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1; Constant FIFO_TSTRB_LS_INDEX : integer := 0; -- Types ------------------------------------------------------------------ type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of std_logic_vector(SLICE_WIDTH-1 downto 0); -- Signal Declarations --------------------------------------------------- signal sig_good_strm_dbeat : std_logic := '0'; signal sig_strm_tready : std_logic := '0'; signal sig_strm_tvalid : std_logic := '0'; signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0'); signal sig_strm_tlast : std_logic := '0'; signal sig_drc2scatter_tready : std_logic := '0'; signal sig_scatter2drc_tvalid : std_logic := '0'; signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0'); signal sig_scatter2drc_tlast : std_logic := '0'; signal sig_scatter2drc_flush : std_logic := '0'; signal sig_valid_dre_output_dbeat : std_logic := '0'; signal sig_ld_cmd : std_logic := '0'; signal sig_cmd_full : std_logic := '0'; signal sig_cmd_empty : std_logic := '0'; signal sig_drc2scatter_push_cmd : std_logic := '0'; signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_drc2scatter_eof : std_logic := '0'; signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_cmd_sof : std_logic := '0'; signal sig_curr_eof_reg : std_logic := '0'; signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_ld_btt_cntr : std_logic := '0'; signal sig_decr_btt_cntr : std_logic := '0'; signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0'); signal sig_btt_eq_0 : std_logic := '0'; signal sig_btt_lteq_max_first_incr : std_logic := '0'; signal sig_btt_gteq_max_incr : std_logic := '0'; signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_eq_0_pre_reg : std_logic := '0'; signal sig_set_tlast_error : std_logic := '0'; signal sig_tlast_error_over : std_logic := '0'; signal sig_tlast_error_under : std_logic := '0'; signal sig_tlast_error_exact : std_logic := '0'; signal sig_tlast_error_reg : std_logic := '0'; signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0'); signal sig_tlast_error_out : std_logic := '0'; signal sig_freeze_it : std_logic := '0'; signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0); signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0); signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0); signal slice_insert_ready : std_logic := '0'; signal slice_insert_valid : std_logic := '0'; signal sig_tstrb_fifo_rdy : std_logic := '0'; signal sig_tstrb_fifo_valid : std_logic := '0'; signal sig_valid_fifo_ld : std_logic := '0'; signal sig_fifo_tlast_out : std_logic := '0'; signal sig_fifo_eof_out : std_logic := '0'; signal sig_fifo_freeze_out : std_logic := '0'; signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0); signal sig_tstrb_valid : std_logic := '0'; signal sig_get_tstrb : std_logic := '0'; signal sig_tstrb_fifo_empty : std_logic := '0'; signal sig_clr_fifo_ld_regs : std_logic := '0'; signal ld_btt_cntr_reg1 : std_logic := '0'; signal ld_btt_cntr_reg2 : std_logic := '0'; signal ld_btt_cntr_reg3 : std_logic := '0'; signal sig_btt_eq_0_reg : std_logic := '0'; signal sig_tlast_ld_beat : std_logic := '0'; signal sig_eof_ld_dbeat : std_logic := '0'; signal sig_strb_error : std_logic := '0'; signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0); signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0); signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_clr_tstrb_fifo : std_logic := '0'; signal sig_eop_sent : std_logic := '0'; signal sig_eop_sent_reg : std_logic := '0'; signal sig_scatter2drc_eop : std_logic := '0'; signal sig_set_packet_done : std_logic := '0'; signal sig_tlast_sent : std_logic := '0'; signal sig_gated_fifo_freeze_out : std_logic := '0'; signal sig_cmd_side_ready : std_logic := '0'; signal sig_eop_halt_xfer : std_logic := '0'; signal sig_err_underflow_reg : std_logic := '0'; signal sig_assert_valid_out : std_logic := '0'; -- Attribute KEEP : string; -- declaration -- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration -- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition -- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no"; begin --(architecture implementation) -- Output stream assignments (to DRE) ----------------- sig_drc2scatter_tready <= drc2scatter_tready ; scatter2drc_tvalid <= sig_scatter2drc_tvalid ; scatter2drc_tdata <= sig_scatter2drc_tdata ; scatter2drc_tstrb <= sig_scatter2drc_tstrb ; scatter2drc_tlast <= sig_scatter2drc_tlast ; scatter2drc_flush <= sig_scatter2drc_flush ; scatter2drc_eop <= sig_scatter2drc_eop ; -- DRC Control ---------------------------------------- scatter2drc_cmd_ready <= sig_cmd_empty; sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ; sig_drc2scatter_btt <= drc2scatter_btt ; sig_drc2scatter_eof <= drc2scatter_eof ; -- Next source alignment control to the S2Mm DRE ------ scatter2drc_src_align <= sig_next_dre_src_align; -- TLAST error flag output ---------------------------- scatter2drc_tlast_error <= sig_tlast_error_out; -- Data to DRE output --------------------------------- sig_scatter2drc_tdata <= sig_strm_tdata ; sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output sig_cmd_side_ready; -- and the tstrb fifo has an entry pending -- Create flag indicating a qualified output stream data beat to the DRE sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and sig_scatter2drc_tvalid; -- Databeat DRE FLUSH output -------------------------- sig_scatter2drc_flush <= '0'; sig_ld_cmd <= sig_drc2scatter_push_cmd and not(sig_cmd_full); sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset, C_DRE_ALIGN_WIDTH)); sig_good_strm_dbeat <= sig_strm_tready and sig_assert_valid_out ; -- Set the valid out flag sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush --- Input Stream Skid Buffer with Special Functions ------------------------------ ------------------------------------------------------------ -- Instance: I_MSSAI_SKID_BUF -- -- Description: -- Instance for the MSSAI Skid Buffer needed for Fmax -- closure when the Scatter Module is included in the DataMover -- S2MM. -- ------------------------------------------------------------ I_MSSAI_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_mssai_skid_buf generic map ( C_WDATA_WIDTH => C_STREAM_DWIDTH , C_INDEX_WIDTH => MSSAI_INDEX_WIDTH ) port map ( -- System Ports aclk => primary_aclk , arst => mmap_reset , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_tvalid , s_ready => s2mm_strm_tready , s_data => s2mm_strm_tdata , s_strb => s2mm_strm_tstrb , s_last => s2mm_strm_tlast , -- Master Side (Stream Data Output m_valid => sig_strm_tvalid , m_ready => sig_strm_tready , m_data => sig_strm_tdata , m_strb => sig_strm_tstrb , m_last => sig_strm_tlast , m_mssa_index => sig_mssa_index , m_strb_error => sig_strb_error ); ------------------------------------------------------------- -- packet Done Logic ------------------------------------------------------------- sig_set_packet_done <= sig_eop_sent_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_FLAG_REG -- -- Process Description: -- Implement the Scatter transfer command full/empty tracking -- flops -- ------------------------------------------------------------- IMP_CMD_FLAG_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_tlast_sent = '1') then sig_cmd_full <= '0'; sig_cmd_empty <= '1'; elsif (sig_ld_cmd = '1') then sig_cmd_full <= '1'; sig_cmd_empty <= '0'; else null; -- hold current state end if; end if; end process IMP_CMD_FLAG_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CURR_OFFSET_REG -- -- Process Description: -- Implements the register holding the current starting -- byte position offset of the first byte of the current -- command. This implementation assumes that only the first -- databeat can be unaligned from Byte position 0. -- ------------------------------------------------------------- IMP_CURR_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_set_packet_done = '1' or sig_valid_fifo_ld = '1') then sig_curr_strt_offset <= (others => '0'); elsif (sig_ld_cmd = '1') then sig_curr_strt_offset <= sig_next_strt_offset; else null; -- Hold current state end if; end if; end process IMP_CURR_OFFSET_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_NEXT_OFFSET_REG -- -- Process Description: -- Implements the register holding the predicted byte position -- offset of the first byte of the next command. If the current -- command has EOF set, then the next command's first data input -- byte offset must be at byte lane 0 in the input stream. -- ------------------------------------------------------------- IMP_NEXT_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_set_packet_done = '1' or STRM_NUM_BYTE_LANES = 1) then sig_next_strt_offset <= (others => '0'); elsif (sig_ld_cmd = '1') then sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice; else null; -- Hold current state end if; end if; end process IMP_NEXT_OFFSET_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIFO_MSSAI_REG -- -- Process Description: -- Implements the register holding the predicted byte position -- offset of the last valid byte defined by the current command. -- ------------------------------------------------------------- IMP_FIFO_MSSAI_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_set_packet_done = '1' or STRM_NUM_BYTE_LANES = 1 ) then sig_fifo_mssai <= (others => '0'); elsif (ld_btt_cntr_reg1 = '1' and ld_btt_cntr_reg2 = '0') then sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE; else null; -- Hold current state end if; end if; end process IMP_FIFO_MSSAI_REG; -- Strobe Generation Logic ------------------------------------------------ sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset); ------------------------------------------------------------ -- Instance: I_SCATTER_STROBE_GEN -- -- Description: -- Strobe generator instance. Generates strobe bits for -- a designated starting byte lane and the number of bytes -- to be transfered (for that data beat). -- ------------------------------------------------------------ I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 0 , -- 0 = Offset/Length mode C_STRB_WIDTH => STRM_NUM_BYTE_LANES , C_OFFSET_WIDTH => NUM_OFFSET_BITS , C_NUM_BYTES_WIDTH => NUM_INCR_BITS ) port map ( start_addr_offset => sig_curr_dbeat_offset , end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0 num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1 strb_out => sig_stbgen_tstrb ); -- BTT Counter stuff ------------------------------------------------------ sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX) when (sig_btt_gteq_max_incr = '1') else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0)); sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0)); sig_btt_lteq_max_first_incr <= '1' when (sig_btt_cntr <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv Else '0'; -- more timing improv -- more timing improv ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MAX_FIRST_INCR_REG -- -- Process Description: -- Implements the Max first increment register value. -- ------------------------------------------------------------- IMP_MAX_FIRST_INCR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_max_first_increment <= (others => '0'); Elsif (sig_ld_cmd = '1') Then sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) - RESIZE(sig_next_strt_offset,NUM_INCR_BITS), CMD_BTT_WIDTH); Elsif (sig_valid_fifo_ld = '1') Then sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH); else null; -- hold current value end if; end if; end process IMP_MAX_FIRST_INCR_REG; sig_btt_cntr_decr_value <= sig_btt_cntr When (sig_btt_lteq_max_first_incr = '1') Else sig_max_first_increment; sig_ld_btt_cntr <= sig_ld_cmd ; sig_decr_btt_cntr <= not(sig_btt_eq_0) and sig_valid_fifo_ld; -- New intermediate value for reduced Timing path sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt) when (sig_ld_btt_cntr = '1') -- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value; Else sig_btt_cntr-sig_btt_cntr_decr_value; sig_btt_eq_0_pre_reg <= '1' when (sig_btt_cntr_prv = BTT_OF_ZERO) Else '0'; -- sig_btt_eq_0 <= '1' -- when (sig_btt_cntr = BTT_OF_ZERO) -- Else '0'; sig_btt_gteq_max_incr <= '1' when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH)) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_CNTR_REG -- -- Process Description: -- Implements the registered portion of the BTT Counter. The -- BTT Counter has been recoded this way to minimize long -- timing paths in the btt -> strobgen-> EOP Demux path. -- ------------------------------------------------------------- IMP_BTT_CNTR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_eop_sent = '1') then sig_btt_cntr <= (others => '0'); -- sig_btt_cntr_dup <= (others => '0'); sig_btt_eq_0 <= '1'; elsif (sig_ld_btt_cntr = '1' or sig_decr_btt_cntr = '1') then sig_btt_cntr <= sig_btt_cntr_prv; -- sig_btt_cntr_dup <= sig_btt_cntr_prv; sig_btt_eq_0 <= sig_btt_eq_0_pre_reg; else Null; -- Hold current state end if; end if; end process IMP_BTT_CNTR_REG; -- IMP_BTT_CNTR_REG : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- if (mmap_reset = '1' or -- sig_eop_sent = '1') then -- sig_btt_cntr <= (others => '0'); ---- sig_btt_eq_0 <= '1'; -- elsif (sig_ld_btt_cntr = '1') then -- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv; ---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg; -- elsif (sig_decr_btt_cntr = '1') then -- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv; ---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg; -- else -- Null; -- Hold current state -- end if; -- end if; -- end process IMP_BTT_CNTR_REG; ------------------------------------------------------------------------ -- DRE TVALID Gating logic ------------------------------------------------------------------------ sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and not(sig_eop_halt_xfer); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOP_HALT_FLOP -- -- Process Description: -- Implements a flag that is set when an end of packet is sent -- to the DRE and cleared after the TSTRB FIFO has been reset. -- This flag inhibits the TVALID sent to the DRE. ------------------------------------------------------------- IMP_EOP_HALT_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_eop_sent = '1') then sig_eop_halt_xfer <= '1'; Elsif (sig_valid_fifo_ld = '1') Then sig_eop_halt_xfer <= '0'; else null; -- hold current state end if; end if; end process IMP_EOP_HALT_FLOP; ------------------------------------------------------------------------ -- TSTRB FIFO Logic ------------------------------------------------------------------------ sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr; sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat; -- Set the MSSAI offset value to the maximum for non-tlast dbeat -- case, otherwise use the calculated value for the TLSAT case. sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai) when (sig_tlast_ld_beat = '1') else STD_LOGIC_VECTOR(OFFSET_MAX); GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Merge the various pieces to go through the TSTRB FIFO into a single vector sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet sig_eof_ld_dbeat & -- the end of the whole packet sig_freeze_it & -- A sub-packet boundary sig_tstrb_fifo_mssai_in & -- the index of EOF byte position sig_stbgen_tstrb; -- The calculated strobes end generate GEN_S2MM_TKEEP_ENABLE3; GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate begin -- Merge the various pieces to go through the TSTRB FIFO into a single vector sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet sig_eof_ld_dbeat & -- the end of the whole packet sig_freeze_it & -- A sub-packet boundary sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position --sig_stbgen_tstrb; -- The calculated strobes end generate GEN_S2MM_TKEEP_DISABLE3; -- FIFO Load control sig_valid_fifo_ld <= sig_tstrb_fifo_valid and sig_tstrb_fifo_rdy; GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Rip the various pieces from the FIFO output sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ; sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ; sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX); sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX); sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX); end generate GEN_S2MM_TKEEP_ENABLE4; GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate begin -- Rip the various pieces from the FIFO output sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ; sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ; sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX); sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX); sig_fifo_tstrb_out <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE4; -- FIFO Read Control sig_get_tstrb <= sig_valid_dre_output_dbeat ; sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or (ld_btt_cntr_reg3 and not(sig_btt_eq_0)); sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and sig_valid_fifo_ld) or sig_eop_sent; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIFO_LD_1 -- -- Process Description: -- Implements the fifo loading control flop stage 1 -- ------------------------------------------------------------- IMP_FIFO_LD_1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_clr_fifo_ld_regs = '1') then ld_btt_cntr_reg1 <= '0'; Elsif (sig_ld_btt_cntr = '1') Then ld_btt_cntr_reg1 <= '1'; else null; -- hold current state end if; end if; end process IMP_FIFO_LD_1; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIFO_LD_2 -- -- Process Description: -- Implements special fifo loading control flops -- ------------------------------------------------------------- IMP_FIFO_LD_2 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_clr_fifo_ld_regs = '1') then ld_btt_cntr_reg2 <= '0'; ld_btt_cntr_reg3 <= '0'; Elsif (sig_tstrb_fifo_rdy = '1') Then ld_btt_cntr_reg2 <= ld_btt_cntr_reg1; ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or ld_btt_cntr_reg3; -- once set, keep it set until cleared else null; -- Hold current state end if; end if; end process IMP_FIFO_LD_2; HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate begin SLICE_INSERTION : entity axi_datamover_v5_1.axi_datamover_slice generic map ( C_DATA_WIDTH => TSTRB_FIFO_DWIDTH ) port map ( ACLK => primary_aclk, ARESET => mmap_reset, -- Slave side S_PAYLOAD_DATA => sig_tstrb_fifo_data_in, S_VALID => sig_tstrb_fifo_valid, S_READY => sig_tstrb_fifo_rdy, -- Master side M_PAYLOAD_DATA => slice_insert_data, M_VALID => slice_insert_valid, M_READY => slice_insert_ready ); ------------------------------------------------------------ -- Instance: I_TSTRB_FIFO -- -- Description: -- Instance for the TSTRB FIFO -- ------------------------------------------------------------ I_TSTRB_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => TSTRB_FIFO_DWIDTH , C_DEPTH => TSTRB_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => sig_clr_tstrb_fifo , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid , fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy , fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in, fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_tstrb_valid , fifo_rd_tready => sig_get_tstrb , fifo_rd_tdata => sig_tstrb_fifo_data_out , fifo_rd_empty => sig_tstrb_fifo_empty ); end generate HIGHER_DATAWIDTH; LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate begin ------------------------------------------------------------ -- Instance: I_TSTRB_FIFO -- -- Description: -- Instance for the TSTRB FIFO -- ------------------------------------------------------------ I_TSTRB_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => TSTRB_FIFO_DWIDTH , C_DEPTH => TSTRB_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => sig_clr_tstrb_fifo , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_tstrb_fifo_valid , fifo_wr_tready => sig_tstrb_fifo_rdy , fifo_wr_tdata => sig_tstrb_fifo_data_in, fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_tstrb_valid , fifo_rd_tready => sig_get_tstrb , fifo_rd_tdata => sig_tstrb_fifo_data_out , fifo_rd_empty => sig_tstrb_fifo_empty ); end generate LOWER_DATAWIDTH; ------------------------------------------------------------ -- TSTRB FIFO Clear Logic ------------------------------------------------------------ -- Special TSTRB FIFO Clear Logic to clean out any residue -- once EOP has been sent out to DRE. This is primarily -- needed in Indeterminate BTT mode but is also included in -- the non-Indeterminate BTT mode for a more robust design. sig_clr_tstrb_fifo <= mmap_reset or sig_set_packet_done; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOP_SENT_REG -- -- Process Description: -- Register the EOP being sent out to the DRE stage. This -- is used to clear the TSTRB FIFO of any residue. -- ------------------------------------------------------------- IMP_EOP_SENT_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_eop_sent_reg = '1') then sig_eop_sent_reg <= '0'; else sig_eop_sent_reg <= sig_eop_sent; end if; end if; end process IMP_EOP_SENT_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOF_REG -- -- Process Description: -- Implement a sample and hold flop for the command EOF -- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0. ------------------------------------------------------------- IMP_EOF_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_set_packet_done = '1') then sig_curr_eof_reg <= '0'; elsif (sig_ld_cmd = '1') then sig_curr_eof_reg <= sig_drc2scatter_eof; else null; -- hold current state end if; end if; end process IMP_EOF_REG; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Implements the Scatter Freeze Register Controls plus -- other logic needed when Indeterminate BTT Mode is not enabled. -- -- -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate signal lsig_eop_matches_ms_strb : std_logic := '0'; begin sig_eop_sent <= sig_scatter2drc_eop and sig_valid_dre_output_dbeat; sig_tlast_sent <= sig_scatter2drc_tlast and sig_valid_dre_output_dbeat; sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set sig_valid_fifo_ld and -- tstrb fifo being loaded not(sig_curr_eof_reg); -- Current input cmd does not have eof set -- Assign the TREADY out to the Stream In sig_strm_tready <= '0' when (sig_gated_fifo_freeze_out = '1' or sig_cmd_side_ready = '0') Else sig_drc2scatter_tready; -- Without Indeterminate BTT, FIFO Freeze does not -- need to be gated. sig_gated_fifo_freeze_out <= sig_fifo_freeze_out; -- Strobe outputs are always generated from the input command -- with Indeterminate BTT omitted. Stream input Strobes are not -- sent to output. sig_scatter2drc_tstrb <= sig_fifo_tstrb_out; -- The EOF marker is generated from the input command -- with Indeterminate BTT omitted. Stream input TLAST is monitored -- but not sent to output to DRE. sig_scatter2drc_eop <= sig_fifo_eof_out and sig_scatter2drc_tvalid; -- TLast output marker always generated from the input command sig_scatter2drc_tlast <= sig_fifo_tlast_out and sig_scatter2drc_tvalid; --- TLAST Error Detection ------------------------------------------------- sig_tlast_error_out <= sig_set_tlast_error or sig_tlast_error_reg; -- Compare the Most significant Asserted TSTRB from the TSTRB FIFO -- with that from the Input Skid Buffer lsig_eop_matches_ms_strb <= '1' when (sig_tstrb_fifo_mssai_out = sig_mssa_index) Else '0'; -- Detect the case when the calculated end of packet -- marker preceeds the received end of packet marker -- and a freeze condition is not enabled sig_tlast_error_over <= '1' when (sig_valid_dre_output_dbeat = '1' and sig_fifo_freeze_out = '0' and sig_fifo_eof_out = '1' and sig_strm_tlast = '0') Else '0'; -- Detect the case when the received end of packet marker preceeds -- the calculated end of packet -- and a freeze condition is not enabled sig_tlast_error_under <= '1' when (sig_valid_dre_output_dbeat = '1' and sig_fifo_freeze_out = '0' and sig_fifo_eof_out = '0' and sig_strm_tlast = '1') Else '0'; -- Detect the case when the received end of packet marker occurs -- in the same beat as the calculated end of packet but the most -- significant received strobe that is asserted does not match -- the most significant calcualted strobe that is asserted. -- Also, a freeze condition is not enabled sig_tlast_error_exact <= '1' When (sig_valid_dre_output_dbeat = '1' and sig_fifo_freeze_out = '0' and sig_fifo_eof_out = '1' and sig_strm_tlast = '1' and lsig_eop_matches_ms_strb = '0') Else '0'; -- Combine all of the possible error conditions sig_set_tlast_error <= sig_tlast_error_over or sig_tlast_error_under or sig_tlast_error_exact; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERROR_REG -- -- Process Description: -- -- ------------------------------------------------------------- IMP_TLAST_ERROR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_tlast_error_reg <= '0'; elsif (sig_set_tlast_error = '1') then sig_tlast_error_reg <= '1'; else Null; -- Hold current State end if; end if; end process IMP_TLAST_ERROR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERROR_UNDER_REG -- -- Process Description: -- Sample and Hold flop for the case when an underrun is -- detected. This flag is used to force a a tvalid output. -- ------------------------------------------------------------- IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_err_underflow_reg <= '0'; elsif (sig_tlast_error_under = '1') then sig_err_underflow_reg <= '1'; else Null; -- Hold current State end if; end if; end process IMP_TLAST_ERROR_UNDER_REG; end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INDET_BTT -- -- If Generate Description: -- Implements the Scatter Freeze Register and Controls plus -- other logic needed to support the Indeterminate BTT Mode -- of Operation. -- -- ------------------------------------------------------------ GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate -- local signals -- signal lsig_valid_eop_dbeat : std_logic := '0'; signal lsig_strm_eop_asserted : std_logic := '0'; signal lsig_absorb2tlast : std_logic := '0'; signal lsig_set_absorb2tlast : std_logic := '0'; signal lsig_clr_absorb2tlast : std_logic := '0'; begin -- Detect an end of packet condition. This is an EOP sent to the DRE or -- an overflow data absorption condition sig_eop_sent <= (sig_scatter2drc_eop and sig_valid_dre_output_dbeat) or (lsig_set_absorb2tlast and not(lsig_absorb2tlast)); sig_tlast_sent <= (sig_scatter2drc_tlast and -- sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition not(lsig_set_absorb2tlast)) or -- (lsig_absorb2tlast and lsig_clr_absorb2tlast); -- Overflow absorbion condition -- TStrb FIFO Input Stream Freeze control sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set -- not(sig_curr_eof_reg) and -- tstrb fifo being loaded sig_valid_fifo_ld ; -- Current input cmd has eof set -- Stream EOP assertion is caused when the stream input TLAST -- is asserted and the most significant strobe bit asserted in -- the input stream data beat is less than or equal to the most -- significant calculated asserted strobe bit for the data beat. lsig_strm_eop_asserted <= '1' when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and (sig_strm_tlast = '1' and sig_strm_tvalid = '1') else '0'; -- Must not freeze the Stream input skid buffer if an EOF -- condition exists on the Stream input (skid buf output) sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and not(lsig_strm_eop_asserted) and sig_strm_tvalid; -- CR617164 -- Databeat DRE EOP output --------------------------- sig_scatter2drc_eop <= (--sig_fifo_eof_out or lsig_strm_eop_asserted) and sig_scatter2drc_tvalid; -- Databeat DRE Last output --------------------------- sig_scatter2drc_tlast <= (sig_fifo_tlast_out or lsig_strm_eop_asserted) and sig_scatter2drc_tvalid; -- Formulate the output TSTRB vector. It is an AND of the command -- generated TSTRB and the actual TSTRB received from the Stream input. sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and sig_strm_tstrb; sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT ------------------------------------------------ -- Data absorption to TLAST logic -- This is used for the Stream Input overflow case. In this case, the -- input stream data is absorbed (thrown away) until the TLAST databeat -- is received (also thrown away). However, data is only absorbed if -- the EOP bit from the TSTRB FIFO is encountered before the TLST from -- the Stream input. -- In addition, the scatter2drc_eop assertion is suppressed from the output -- to the DRE. -- Assign the TREADY out to the Stream In with Overflow data absorption -- case added. sig_strm_tready <= '0' when (lsig_absorb2tlast = '0' and (sig_gated_fifo_freeze_out = '1' or -- Normal case sig_cmd_side_ready = '0')) Else '1' When (lsig_absorb2tlast = '1') -- Absorb overflow case Else sig_drc2scatter_tready; -- Check for the condition for absorbing overflow data. The start of new input -- packet cannot reside in the same databeat as the end of the previous -- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the -- entire databeat needs to be discarded after transfer to the DRE of the -- appropriate data. lsig_set_absorb2tlast <= '1' when (sig_fifo_eof_out = '1' and sig_tstrb_fifo_empty = '0' and -- CR617164 (sig_strm_tlast = '0' and sig_strm_tvalid = '1')) Else '1' When (sig_gated_fifo_freeze_out = '1' and sig_fifo_eof_out = '1' and sig_tstrb_fifo_empty = '0') -- CR617164 else '0'; lsig_clr_absorb2tlast <= '1' when lsig_absorb2tlast = '1' and (sig_strm_tlast = '1' and sig_strm_tvalid = '1') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ABSORB_FLOP -- -- Process Description: -- Implements the flag for indicating a overflow absorption -- case is active. -- ------------------------------------------------------------- IMP_ABSORB_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or lsig_clr_absorb2tlast = '1') then lsig_absorb2tlast <= '0'; elsif (lsig_set_absorb2tlast = '1') then lsig_absorb2tlast <= '1'; else null; -- Hold Current State end if; end if; end process IMP_ABSORB_FLOP; end generate GEN_INDET_BTT; end implementation;	bsd-2-clause	aeeaa636f85fc733a5a074c21b3d140b	0.436894	4.745629	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/conditional_expressions/rule_501_test_input.fixed_upper.vhd	1	400	architecture rtl of fifo is begin process begin var1 := '0' when rd_en = '1' ELSE '1'; var2 := '0' when rd_en = '1' ELSE '1'; wr_en_a <= force '0' when rd_en = '1' ELSE '1'; wr_en_b <= force '0' when rd_en = '1' ELSE '1'; end process; concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;	gpl-3.0	b7d3933e2e88188facae9010116e2d68	0.54	2.564103	false	false	false	false
wklimann/PCM3168	PCM3168/PCM3168_tb.vhd	1	2,352	-------------------------------------------------------------------------------- -- Engineer: Klimann Wendelin -- -- Create Date: 09:00:40 11/Okt/2013 -- Design Name: parallel_to_i2s -- Description: -- -- VHDL Test Bench for module: pcm3168 -- -- version: 00.01 -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY pcm3168_tb_vhd IS END pcm3168_tb_vhd; ARCHITECTURE behavior OF pcm3168_tb_vhd IS constant width : integer := 24; constant clk_divider : integer := 4; -- Component Declaration for the Unit Under Test (UUT) COMPONENT pcm3168 generic( width : integer := width; clk_divider : integer := clk_divider ); PORT( CLK : in std_logic; RESET : in std_logic; DIN_1 : in std_logic; DOUT_1 : out std_logic ); END COMPONENT; --Inputs SIGNAL CLK : std_logic := '0'; SIGNAL RESET : std_logic := '0'; SIGNAL DIN_1 : std_logic := '0'; --Outputs SIGNAL DOUT_1 : std_logic := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: pcm3168 PORT MAP( CLK => CLK, RESET => RESET, DOUT_1 => DOUT_1, DIN_1 => DIN_1 ); -- creates a reset signal at the start of the sequence p_reset : process begin RESET <= '0'; wait for 160 ns; RESET <= '1'; -- Reset finished wait; end process p_reset; -- generates the clock signal p_clk : process begin CLK <= '0'; wait for 10 ns; CLK <= '1'; wait for 10 ns; end process p_clk; -- provides the parallel input signal p_din : process variable i : POSITIVE :=1; variable first : POSITIVE :=2; begin if (first = 2) then first := 1; DIN_1 <= '0'; wait for 320 ns; end if; i := 1; while (i <= width) loop i := i + 1; DIN_1 <= '1'; wait for 80 ns; end loop; i := 1; while (i <= width) loop i := i + 1; DIN_1 <= '0'; wait for 80 ns; i := i + 1; DIN_1 <= '1'; wait for 80 ns; end loop; i := 1; while (i <= width) loop i := i + 2; DIN_1 <= '0'; wait for 160 ns; i := i + 2; DIN_1 <= '1'; wait for 160 ns; end loop; i := 1; while (i <= width) loop i := i + 1; DIN_1 <= '0'; wait for 80 ns; end loop; end process p_din; END;	gpl-2.0	e52b1f223b0edff2c1379b47bd1d0165	0.52466	2.854369	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/if_statement/rule_029_test_input.vhd	1	566	architecture RTL of FIFO is begin process begin if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; else if x = '1' then z <= '0'; elsif x = '0' then z <= '1'; else z <= 'Z'; end if; end if; -- Violations below if a = '1' THEN b <= '0'; elsif c = '1' THEN b <= '1'; else if x = '1' THEN z <= '0'; elsif x = '0' THEN z <= '1'; else z <= 'Z'; end if; end if; end process; end architecture RTL;	gpl-3.0	d23b068df86e27a43fb3a1dbe0c83344	0.379859	3.19774	false	false	false	false
rjarzmik/mips_processor	IF/Fetch_tb.vhd	1	4,914	------------------------------------------------------------------------------- -- Title : Testbench for design "Fetch" -- Project : ------------------------------------------------------------------------------- -- File : Fetch_tb.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-11 -- Last update: 2016-12-03 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-11 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity Fetch_tb is end entity Fetch_tb; ------------------------------------------------------------------------------- architecture rtl of Fetch_tb is -- component generics constant ADDR_WIDTH : integer := 16; constant DATA_WIDTH : integer := 16; constant MEMORY_LATENCY : integer := 3; -- component ports -- clock signal Clk : std_logic := '1'; -- reset signal Rst : std_logic := '1'; signal instruction : std_logic_vector(DATA_WIDTH - 1 downto 0); signal pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(0, ADDR_WIDTH)); signal next_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(4, ADDR_WIDTH)); signal next_next_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(4, ADDR_WIDTH)); signal stall_req : std_logic := '0'; signal stall_pc : std_logic := '0'; signal jump_pc : std_logic; signal jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0); -- L2 connections signal o_L2c_req : std_logic; signal o_L2c_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal i_L2c_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_L2c_valid : std_logic; -- Debug signals signal dbg_if_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); begin -- architecture rtl -- component instantiation dut : entity work.Fetch(rtl3) generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH) port map ( clk => Clk, rst => Rst, stall_req => '0', kill_req => '0', i_pc => pc, i_next_pc => next_pc, i_next_next_pc => next_next_pc, o_instruction => instruction, o_do_stall_pc => stall_pc, o_L2c_req => o_L2c_req, o_L2c_addr => o_L2c_addr, i_L2c_read_data => i_L2c_read_data, i_L2c_valid => i_L2c_valid, o_dbg_if_fetching_pc => dbg_if_pc); Simulated_Memory_1 : entity work.Simulated_Memory generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, MEMORY_LATENCY => MEMORY_LATENCY) port map ( clk => Clk, rst => Rst, i_memory_req => o_L2c_req, i_memory_we => '0', i_memory_addr => o_L2c_addr, i_memory_write_data => (others => 'X'), o_memory_read_data => i_L2c_read_data, o_memory_valid => i_L2c_valid); PC_Register_1 : entity work.PC_Register generic map ( ADDR_WIDTH => ADDR_WIDTH, STEP => 4) port map ( clk => Clk, rst => Rst, stall_pc => stall_pc, jump_pc => jump_pc, jump_target => jump_target, o_current_pc => pc, o_next_pc => next_pc, o_next_next_pc => next_next_pc); -- reset Rst <= '0' after 12 ps; -- clock generation Clk <= not Clk after 5 ps; -- waveform generation WaveGen_Proc : process variable nb_clks : integer := 0; begin -- insert signal assignments here wait until Clk = '1'; nb_clks := nb_clks + 1; if unsigned(pc) = to_unsigned(16 + 4, ADDR_WIDTH) then jump_pc <= '1'; jump_target <= std_logic_vector(to_unsigned(8, ADDR_WIDTH)); else jump_pc <= '0'; jump_target <= (others => 'X'); end if; end process WaveGen_Proc; end architecture rtl; ------------------------------------------------------------------------------- configuration Fetch_tb_test_cfg of Fetch_tb is for rtl end for; end Fetch_tb_test_cfg; -------------------------------------------------------------------------------	gpl-3.0	f6dfb479b01cdbca9cd8fc3d0c0be4e9	0.455026	3.84507	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover.vhd	1	74,527	------------------------------------------------------------------------------- -- axi_datamover.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover.vhd -- -- Description: -- Top level VHDL wrapper for the AXI DataMover -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover.vhd -- \| -- \|- axi_datamover_mm2s_omit_wrap.vhd -- \|- axi_datamover_mm2s_full_wrap.vhd -- \|- axi_datamover_mm2s_basic_wrap.vhd -- \| -- \|- axi_datamover_s2mm_omit_wrap.vhd -- \|- axi_datamover_s2mm_full_wrap.vhd -- \|- axi_datamover_s2mm_basic_wrap.vhd -- -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 6/2/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Updated Burst limit and min BTT used calculations to account for -- the inclusion of upsizer/downsizer logic in the datapath. -- ^^^^^^ -- -- DET 6/20/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added 512 and 1024 data width support -- ^^^^^^ -- -- DET 9/1/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Fixed Lint reported excesive line length for lines 404 and 530. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library proc_common_v4_0; use proc_common_v4_0.family_support; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap ; use axi_datamover_v5_1.axi_datamover_mm2s_full_wrap ; use axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap; use axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap ; use axi_datamover_v5_1.axi_datamover_s2mm_full_wrap ; use axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap; ------------------------------------------------------------------------------- entity axi_datamover is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 2; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Basic MM2S functionality C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0; -- Specifies the constant value to output on -- the ARID output port C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit MM2S Store and Forward -- 1 = Include MM2S Store and Forward C_INCLUDE_S2MM : Integer range 0 to 4 := 2; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Basic S2MM functionality C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1; -- Specifies the constant value to output on -- the ARID output port C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) Store and Forward function -- 0 = Omit S2MM Store and Forward -- 1 = Include S2MM Store and Forward C_ENABLE_CACHE_USER : integer range 0 to 1 := 0; C_ENABLE_SKID_BUF : string := "11111"; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0; C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input ---------------------------------- m_axi_mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- m_axi_mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------- -- MM2S Halt request input control -------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------- -- Error discrete output ------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- -------------------------------------------------- -- Memory Map to Stream Command FIFO and Status FIFO I/O --------- m_axis_mm2s_cmdsts_aclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- m_axis_mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ------------------------------------------------- s_axis_mm2s_cmd_tvalid : in std_logic; -- s_axis_mm2s_cmd_tready : out std_logic; -- s_axis_mm2s_cmd_tdata : in std_logic_vector(((8C_ENABLE_CACHE_USER)+C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); -- ---------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------------ m_axis_mm2s_sts_tvalid : out std_logic; -- m_axis_mm2s_sts_tready : in std_logic; -- m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); -- m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); -- m_axis_mm2s_sts_tlast : out std_logic; -- -------------------------------------------------------------------- -- Address Posting contols ----------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- -------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------------------- m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- m_axi_mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- m_axi_mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); -- -- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); -- -- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); -- -- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------ m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); -- m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); -- m_axi_mm2s_rlast : In std_logic; -- m_axi_mm2s_rvalid : In std_logic; -- m_axi_mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------------- m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_tlast : Out std_logic; -- m_axis_mm2s_tvalid : Out std_logic; -- m_axis_mm2s_tready : In std_logic; -- ---------------------------------------------------------------------------------------------- -- Testing Support I/O -------------------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) ; -- ------------------------------------------------------------------------------- -- S2MM Primary Clock input --------------------------------- m_axi_s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- S2MM Primary Reset input -- m_axi_s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- S2MM Halt request input control ------------------ s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : out std_logic; -- -- Active high soft shutdown complete status -- ----------------------------------------------------- -- S2MM Error discrete output ------------------ s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------ -- Memory Map to Stream Command FIFO and Status FIFO I/O ----------------- m_axis_s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- m_axis_s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- -------------------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) -------------------------------------------------- s_axis_s2mm_cmd_tvalid : in std_logic; -- s_axis_s2mm_cmd_tready : out std_logic; -- s_axis_s2mm_cmd_tdata : in std_logic_vector(((8C_ENABLE_CACHE_USER)+C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); -- ----------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ----------------------------------------------------------- m_axis_s2mm_sts_tvalid : out std_logic; -- m_axis_s2mm_sts_tready : in std_logic; -- m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT24)+8)-1 downto 0); -- m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0); -- m_axis_s2mm_sts_tlast : out std_logic; -- ------------------------------------------------------------------------------------------------------- -- Address posting controls ----------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- --------------------------------------------------------------------- -- S2MM AXI Address Channel I/O ---------------------------------------------------- m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- m_axi_s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- m_axi_s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); -- -- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); -- -- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); -- -- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O -------------------------------------------------- m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); -- m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); -- m_axi_s2mm_wlast : Out std_logic; -- m_axi_s2mm_wvalid : Out std_logic; -- m_axi_s2mm_wready : In std_logic; -- ------------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ------------------------- m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); -- m_axi_s2mm_bvalid : In std_logic; -- m_axi_s2mm_bready : Out std_logic; -- ---------------------------------------------------------------------- -- S2MM AXI Slave Stream Channel I/O ------------------------------------------------------- s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_tlast : In std_logic; -- s_axis_s2mm_tvalid : In std_logic; -- s_axis_s2mm_tready : Out std_logic; -- --------------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------------ ); end entity axi_datamover; architecture implementation of axi_datamover is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ------------------------------------------------------------------- -- Function -- -- Function Name: funct_clip_brst_len -- -- Function Description: -- This function is used to limit the parameterized max burst -- databeats when the tranfer data width is 256 bits or greater. -- This is required to keep from crossing the 4K byte xfer -- boundary required by AXI. This process is further complicated -- by the inclusion/omission of upsizers or downsizers in the -- data path. -- ------------------------------------------------------------------- function funct_clip_brst_len (param_burst_beats : integer; mmap_transfer_bit_width : integer; stream_transfer_bit_width : integer; down_up_sizers_enabled : integer) return integer is constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0); Variable fvar_max_burst_dbeats : Integer; begin if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc If (mmap_transfer_bit_width <= 128) Then -- allowed fvar_max_burst_dbeats := param_burst_beats; Elsif (mmap_transfer_bit_width <= 256) Then If (param_burst_beats <= 128) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 128; End if; Elsif (mmap_transfer_bit_width <= 512) Then If (param_burst_beats <= 64) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 64; End if; Else -- 1024 bit mmap width case If (param_burst_beats <= 32) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 32; End if; End if; else -- use stream dwidth for calc If (stream_transfer_bit_width <= 128) Then -- allowed fvar_max_burst_dbeats := param_burst_beats; Elsif (stream_transfer_bit_width <= 256) Then If (param_burst_beats <= 128) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 128; End if; Elsif (stream_transfer_bit_width <= 512) Then If (param_burst_beats <= 64) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 64; End if; Else -- 1024 bit stream width case If (param_burst_beats <= 32) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 32; End if; End if; end if; Return (fvar_max_burst_dbeats); end function funct_clip_brst_len; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_fix_depth_16 -- -- Function Description: -- This function is used to fix the Command and Status FIFO depths to -- 16 entries when Async clocking mode is enabled. This is required -- due to the way the async_fifo_fg.vhd design in proc_common is -- implemented. ------------------------------------------------------------------- function funct_fix_depth_16 (async_clocking_mode : integer; requested_depth : integer) return integer is Variable fvar_depth_2_use : Integer; begin If (async_clocking_mode = 1) Then -- async mode so fix at 16 fvar_depth_2_use := 16; Elsif (requested_depth > 16) Then -- limit at 16 fvar_depth_2_use := 16; Else -- use requested depth fvar_depth_2_use := requested_depth; End if; Return (fvar_depth_2_use); end function funct_fix_depth_16; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_min_btt_width -- -- Function Description: -- This function calculates the minimum required value -- for the used width of the command BTT field. -- ------------------------------------------------------------------- function funct_get_min_btt_width (max_burst_beats : integer; bytes_per_beat : integer ) return integer is Variable var_min_btt_needed : Integer; Variable var_max_bytes_per_burst : Integer; begin var_max_bytes_per_burst := max_burst_beatsbytes_per_beat; if (var_max_bytes_per_burst <= 16) then var_min_btt_needed := 5; elsif (var_max_bytes_per_burst <= 32) then var_min_btt_needed := 6; elsif (var_max_bytes_per_burst <= 64) then var_min_btt_needed := 7; elsif (var_max_bytes_per_burst <= 128) then var_min_btt_needed := 8; elsif (var_max_bytes_per_burst <= 256) then var_min_btt_needed := 9; elsif (var_max_bytes_per_burst <= 512) then var_min_btt_needed := 10; elsif (var_max_bytes_per_burst <= 1024) then var_min_btt_needed := 11; elsif (var_max_bytes_per_burst <= 2048) then var_min_btt_needed := 12; elsif (var_max_bytes_per_burst <= 4096) then var_min_btt_needed := 13; else -- 8K byte range var_min_btt_needed := 14; end if; Return (var_min_btt_needed); end function funct_get_min_btt_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_xfer_bytes_per_dbeat -- -- Function Description: -- Calculates the nuber of bytes that will transfered per databeat -- on the AXI4 MMap Bus. -- ------------------------------------------------------------------- function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer; stream_transfer_bit_width : integer; down_up_sizers_enabled : integer) return integer is Variable temp_bytes_per_dbeat : Integer := 4; begin if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth temp_bytes_per_dbeat := mmap_transfer_bit_width/8; else -- No down/up sizers so use Stream data width temp_bytes_per_dbeat := stream_transfer_bit_width/8; end if; Return (temp_bytes_per_dbeat); end function funct_get_xfer_bytes_per_dbeat; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_fix_btt_used -- -- Function Description: -- THis function makes sure the BTT width used is at least the -- minimum needed. -- ------------------------------------------------------------------- function funct_fix_btt_used (requested_btt_width : integer; min_btt_width : integer) return integer is Variable var_corrected_btt_width : Integer; begin If (requested_btt_width < min_btt_width) Then var_corrected_btt_width := min_btt_width; else var_corrected_btt_width := requested_btt_width; End if; Return (var_corrected_btt_width); end function funct_fix_btt_used; ------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------- Constant MM2S_TAG_WIDTH : integer := 4; Constant S2MM_TAG_WIDTH : integer := 4; Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF; Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT; Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE, C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH, MM2S_DOWNSIZER_ENABLED); Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE, C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH, S2MM_UPSIZER_ENABLED); Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC, C_MM2S_STSCMD_FIFO_DEPTH); Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC, C_S2MM_STSCMD_FIFO_DEPTH); Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH, MM2S_DOWNSIZER_ENABLED); Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS, MM2S_BYTES_PER_BEAT); Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED, MM2S_MIN_BTT_NEEDED); Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH, S2MM_UPSIZER_ENABLED); Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS, S2MM_BYTES_PER_BEAT); Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED, S2MM_MIN_BTT_NEEDED); -- Signals signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0'); signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0) := (others => '0'); begin --(architecture implementation) ------------------------------------------------------------- -- Conversion to tkeep for external stream connnections ------------------------------------------------------------- -- MM2S Status Stream Output m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ; GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate begin -- MM2S Stream Output m_axis_mm2s_tkeep <= sig_mm2s_tstrb ; end generate GEN_MM2S_TKEEP_ENABLE1; GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate begin m_axis_mm2s_tkeep <= (others => '1'); end generate GEN_MM2S_TKEEP_DISABLE1; GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- S2MM Stream Input sig_s2mm_tstrb <= s_axis_s2mm_tkeep ; end generate GEN_S2MM_TKEEP_ENABLE1; GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate begin sig_s2mm_tstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE1; -- S2MM Status Stream Output m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_OMIT -- -- If Generate Description: -- Instantiate the MM2S OMIT Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_OMIT_WRAPPER -- -- Description: -- Read omit Wrapper Instance -- ------------------------------------------------------------ I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_OMIT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_FULL -- -- If Generate Description: -- Instantiate the MM2S Full Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_FULL_WRAPPER -- -- Description: -- Read Full Wrapper Instance -- ------------------------------------------------------------ I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_full_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_BASIC -- -- If Generate Description: -- Instantiate the MM2S Basic Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_BASIC_WRAPPER -- -- Description: -- Read Basic Wrapper Instance -- ------------------------------------------------------------ I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_BASIC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_OMIT -- -- If Generate Description: -- Instantiate the S2MM OMIT Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_OMIT_WRAPPER -- -- Description: -- Write Omit Wrapper Instance -- ------------------------------------------------------------ I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_OMIT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_FULL -- -- If Generate Description: -- Instantiate the S2MM FULL Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_FULL_WRAPPER -- -- Description: -- Write Full Wrapper Instance -- ------------------------------------------------------------ I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_full_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED , C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_BASIC -- -- If Generate Description: -- Instantiate the S2MM Basic Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_BASIC_WRAPPER -- -- Description: -- Write Basic Wrapper Instance -- ------------------------------------------------------------ I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_BASIC; end implementation;	bsd-2-clause	554ee9f7e9f5cadc24d288bc28227b99	0.400768	4.190677	false	false	false	false
okaxaki/vm2413	EnvelopeGenerator.vhd	2	6,777	-- -- EnvelopeGenerator.vhd -- The envelope generator module of VM2413 -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use WORK.VM2413.ALL; entity EnvelopeGenerator is port (clk : in std_logic; reset : in std_logic; clkena : in std_logic; slot : in SLOT_TYPE; stage : in STAGE_TYPE; rhythm : in std_logic; am : in AM_TYPE; tl : in DB_TYPE; ar : in AR_TYPE; dr : in DR_TYPE; sl : in SL_TYPE; rr : in RR_TYPE; rks : in RKS_TYPE; key : in std_logic; egout : out DB_TYPE); end EnvelopeGenerator; architecture RTL of EnvelopeGenerator is component EnvelopeMemory port ( clk : in std_logic; reset : in std_logic; waddr : in SLOT_TYPE; wr : in std_logic; wdata : in EGDATA_TYPE; raddr : in SLOT_TYPE; rdata : out EGDATA_TYPE ); end component; component AttackTable port ( clk : in std_logic; addr : in integer range 0 to 2 (DB_TYPE'high+1) - 1; data : out DB_TYPE ); end component; signal rslot : SLOT_TYPE; signal memin, memout : EGDATA_TYPE; signal memwr : std_logic; signal aridx : integer range 0 to 2 (DB_TYPE'high+1) - 1; signal ardata : DB_TYPE; begin ARTBL : AttackTable port map ( clk, aridx, ardata ); EGMEM : EnvelopeMemory port map ( clk, reset, slot, memwr, memin, rslot, memout ); process(clk, reset) variable lastkey : std_logic_vector(MAXSLOT-1 downto 0); variable rm : std_logic_vector(4 downto 0); variable egtmp : std_logic_vector(DB_TYPE'high + 2 downto 0); variable ntable : std_logic_vector(17 downto 0); variable amphase : std_logic_vector(19 downto 0); variable rslot_buf : SLOT_TYPE; variable egphase : EGPHASE_TYPE; variable egstate : EGSTATE_TYPE; variable dphase : EGPHASE_TYPE; begin if(reset = '1') then rm := (others=>'0'); lastkey := (others=>'0'); ntable := (others=>'1'); amphase(amphase'high downto amphase'high-4) := "00001"; amphase(amphase'high-5 downto 0) := (others=>'0'); memwr <= '0'; egstate := Finish; egphase := (others=>'0'); rslot_buf := 0; elsif(clk'event and clk='1') then if clkena ='1' then -- White noise generator for I in 17 downto 1 loop ntable(I) := ntable(I-1); end loop; ntable(0) := ntable(17) xor ntable(14); -- Amplitude oscillator ( -4.8dB to 0dB , 3.7Hz ) amphase := amphase + '1'; if amphase(amphase'high downto amphase'high-4) = "11111" then amphase(amphase'high downto amphase'high-4) := "00001"; end if; if stage = 0 then egstate := memout.state; egphase := memout.phase; aridx <= CONV_INTEGER( egphase( egphase'high-1 downto egphase'high-7 ) ); elsif stage = 1 then -- Wait for AttackTable elsif stage = 2 then case egstate is when Attack => rm := '0'&ar; egtmp := ("00"&tl) + ("00"&ardata); when Decay => rm := '0'&dr; egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7)); when Release=> rm := '0'&rr; egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7)); when Finish => egtmp(egtmp'high downto egtmp'high -1) := "00"; egtmp(egtmp'high-2 downto 0) := (others=>'1'); end case; -- SD and HH if ntable(0)='1' and slot/2 = 7 and rhythm = '1' then egtmp := egtmp + "010000000"; end if; -- Amplitude LFO if am ='1' then if (amphase(amphase'high) = '0') then egtmp := egtmp + ("00000"&(amphase(amphase'high-1 downto amphase'high-4)-'1')); else egtmp := egtmp + ("00000"&("1111"-amphase(amphase'high-1 downto amphase'high-4))); end if; end if; -- Generate output if egtmp(egtmp'high downto egtmp'high-1) = "00" then egout <= egtmp(egout'range); else egout <= (others=>'1'); end if; if rm /= "00000" then rm := rm + rks(3 downto 2); if rm(rm'high)='1' then rm(3 downto 0):="1111"; end if; case egstate is when Attack => dphase(dphase'high downto 5) := (others=>'0'); dphase(5 downto 0) := "110" * ('1'&rks(1 downto 0)); dphase := SHL( dphase, rm(3 downto 0) ); egphase := egphase - dphase(egphase'range); when Decay \| Release => dphase(dphase'high downto 3) := (others=>'0'); dphase(2 downto 0) := '1'&rks(1 downto 0); dphase := SHL(dphase, rm(3 downto 0) - '1'); egphase := egphase + dphase(egphase'range); when Finish => null; end case; end if; case egstate is when Attack => if egphase(egphase'high) = '1' then egphase := (others=>'0'); egstate := Decay; end if; when Decay => if egphase(egphase'high downto egphase'high-4) >= '0'&sl then egstate := Release; end if; when Release => if( egphase(egphase'high downto egphase'high-4) >= "01111" ) then egstate:= Finish; end if; when Finish => egphase := (others => '1'); end case; if lastkey(slot) = '0' and key = '1' then egphase(egphase'high):= '0'; egphase(egphase'high-1 downto 0) := (others =>'1'); egstate:= Attack; elsif lastkey(slot) = '1' and key = '0' and egstate /= Finish then egstate:= Release; end if; lastkey(slot) := key; -- update phase and state memory memin <= ( state => egstate, phase => egphase ); memwr <='1'; -- read phase of next slot (prefetch) if slot = 17 then rslot_buf := 0; else rslot_buf := slot + 1; end if; rslot <= rslot_buf; elsif stage = 3 then -- wait for phase memory memwr <='0'; end if; end if; end if; end process; end RTL;	mit	f24a27e4c463bae6fc3032d2dc13d0a6	0.491368	3.835314	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/shft_ram.vhd	2	17,157	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block omNAiYCkVgSpwWQRAVcNRmuVjDasJ7fqBecood6uQTvzwoer3VBmMrl/sKgXm7PV8OHd6KFUTW4j 83emWzmDUg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block IaH7PVbW+RwPNo0qPm77xsP1bwSgN5Pcmrj58RwcvtTJDNH3F9E+ML4deTpljXJX6IrcaUdM2fNM ImiRygT+gNJqQohHgw4LjniGngO6OqAzjoHFaty+7DxViwIxpXBk7b2Q1GhKRKAEsQ7lddj/6x/d 4CGtJastysBrrJIcFbQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Ge471IctsRp49yURxoMNLow/OTPMRjr6NPV2erpJ9mo80k07ietT/lb8QskCLaX8Q5gAwn00BfR4 D2wUNUvm3L/neIgvU2m1uMe2f55wNoZSu/qopn2UhnDs2QtIwG8zI75BYOcuRxM/NvnKbQKe77R5 o+y6K8keGMD1r935nsUtzvNSzgGueB3icYvB38NAtJvMzo6Ad+gaDzNZZAdAHj1f8QQNuewkrFIU 5nWhoM6J80xziaERJ3HbNlRMU1HGqSkW3uhlRZnMMDbCuIsSPo/IAXGYsGD1+0KjTMczr2LEMZkK fZKFt7TWo5DpozLWa2nIMYcUWkshdXxhjDkTtQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fY/cdQmFQ+zAfd/CHO9RZSw4dau4s8GrEQbRh5HbEGxAQvIHnFVvGRkVLHfHgtH9ZMBycKcc0871 CofFMdbWe0fsr1hyYI+8gRnD7Wj8KUs+N0Qhv4VZAruvhj6Bbf+rWDnKXPzVwS3zEoCTCkt0BDZD aHjASTSOAq7owypnPfU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block BArrUpKvws2Un7xsPVYAW6wuAm0/EOtH2Gl/W0jc7gYlPv2wxUO97GKivsBofywjFoGtB3haW7or t2P33PhXIHrNFG8oKURg4tEPCT738HDZxwwdtQ8GUQIh592wuBm74VTPGDqhfQnfJvEFKrDpB6Lh dt0W+Sh728R1BmkO860vI0oBTFZob3BcKK3Y0oqwJsUanjWVmczXn+2agzrUSgEI+DZOSezq5lRZ JuGFUxRPpb7O86+d71NQf6KW3JhysnoaawZ0/APwkxqA9Cs3es0fkOAmDSfc7/+ZPX+BePycquBF X54xG6uM8J7fqk1enX6UXADv+m7sB5G1Vn9xWQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960) `protect data_block V7jnI5Kn6xyQkIOmBVDJEC60punMuYgTWL1S9XCO02XfS22iHL7vDVg6zN7iWSP4Dl6a7lU2vNBw urPyFcDOwKMXKkVCx3ZgXbnagYWErZvUznXVN1ZHOtMuZsMJTk4OcOIyHtec0G1C1xBuX1yj1OfA KnOU1T3pWuVxdkcL1ykQjcvn8N5OGWDtPKcKyvXm25DeO/3KfPULXPhpuoAMaVYoDE1pnhUop5BQ hwLOubJ8d81oGCpxpRxiyC25gqkyh6YwT8mUyK5snipwSY3it2fWueiFASt1rl/NILMxKrh6fopx xnNJS7eG7QTTcJv+/PlfkjNJ/lkb9LwINN2bopeaA1LokYr36vlfCClNQ+ouEkSpgnAYKGjvUtBk zDUN9o6jadAsLwm16udP/IMyJ4tR87NXvJ1DRIUJuJQMFSciT5XP2OTYWp2ibPlwHWlWooqe4/ZQ h6HJn3yvDDk1H9LiPbH/Amqw6vUyKr2VsaBEiAgtw6rH8dZPv1fpA79KNhfrOpqixWZ3dU3iG9P+ 5NoHcD86fR3ST2oUPIWXA7j5lPcqvHTlk4ZswP2nHPjZYgq5/UkrjdHaXhbHjMB1NarPx6mRs7jq 223fByGtaAgDUsHQWJJtD7A2Uucd/DrTiKb/3rlhutnJpl+rRyfHgiIV0NUGocGFsS+23zjVOVtY GTSsERt1279CMwwHfw3+fZE7q4fYPf2xphL/SiD2K82EJfXwYxJ1fs/i6XiUee3J7RpC2VTf5sQG k104UVw+FjDeaV8l8PC4DuQkulSzN231o36tbxjybqdNU5bFwGynQFptJrwejMCtG0DIBonkpUFX 2QZwBPsqu5ule5EoS3Xm6r3v31ZdVegpqnDya/PsBgVfeMao/b07aomZIxCpmDkRNVgvRV1Qfya6 wjZqLryulkwIJV0680LrxCUuZaOHCMMTO1QoxJfWqv77r7nQ6zPToNzyTM/LnPmKDTVexGRqmnDN RLHgpCQw7E5ATv8UAN/ALtgVIjqMvaG9xjyJ+d/HlvPg5ccAvPuUMtaxf6aLpSRn1rP3z2OqhX9Q 2RDVeyo0XqRalXIS5AWLQLpsAcZBItRzQgNoI2p44btiINIkesPJp3+YA55CdGnT6TVaosO4/qUh rsvSeMzFnxhCgN+RNy5LPjIyAP22aON92R1hDx3VfBEw3/5ITdJC5MhJo5YrnQuUHJBiriR5wayg 1TsZzKw9i2QlciU5pNQS5tAWqP9Aw0yXKSjOmKASEZ4wT5w6cu0+lTZ35PyEjKRgwOK0Vv7km7wp 1xoU/8zRobsVFkfGH5kXfiuRK5kKYiREijgf9U8xXdPT1siqrYNov3TQMj4Rj5NvrH7/mUoCQupM CLuzgQxSuiKkoa6RxXvvr6/rcwHpKfdWoTEQoRGvalIr23qIELYuqkKDei7ZuljKpnYNRLkbqhHK AOHxcre89bJMuI2SbZ2k4Xx5MwudykrifXYodr0TySnQojzChadovLrqigEEj4FGhiYquxpHKPKL rO/A1XzpPBKybj1PV7NVnVkKlFOA+wGD3Rxk20F4rr2koix+nPTDrqjAy2zesnrZFEe9xBnIPPnH nSyNDfZJSXBSENA+AMja1/jOYnTHblI38l+oG4+l6ZHvz+ZzyTLIOG/1Yb+Nl5WPqBtA9tsFt/7u fqkrZnKVxbYNeiaCNPDy56IHcsr9s77aklfNx1tYzHE/eXqJ6RDGpfIoMKtEVaf85aJ6xoj1ymqs pRoeZakH//Ec0Qa8Nhmwn4MNNSxVIZQE4iIUPLeFN7WKkk7Y0bpsF07S+OSvS6Jfvx2cdaVUvB1d ihuWqSOEwwSbUVEbSVZiRl+IjNhzOB36BBKdrFpKOCh2OvyVFG9vNAuxjFNbuR5fPcndn2VKpVBA ST/fyoo2mQAUc5iLp3lJrjKsEYlieIqr9GMzG1ghy6S2Kw+eOiWeVi6HfVSuvykCZrnOX0CxCypB pt0UiuUo9nin1EGl5FnX6hvKzaZmdUZPcXHhDY2GQLe6jHNjTiZ3a6ZDWIHyQnlYHmVdCUCUaMS6 Wc6V5F4LKpYxwSEoYyi53XCm6cK5SwxCnf309relrTF2kjkg54FE6Vvc8b4+lU7My90yYDTGdI7B S+gRaTo8sOv0TWMvLhFl+TF7il/N2y3d+iyFpf6pIukalhqUnGnB20mpDAiTR3BJ7cybAYNsjZJp 7RRjvCOUND6N/PYJp+e3E3dzqbdfNHHVVpcFihqgz955CV5mr2CDUjnecRxgPtjS5iidhjWxYOI3 f31FPAm1TDb/fOG17rSB5DxcmlBfJIIO0w5V9TLSqdxQzwsW210cfiL7NmJbUl7M2M5cN5/4D9cv hfjLJbvobAAzRTa6G8rHMNW96ZDtbZt0c6i555GYMEKcOBv34omkyliPHLxt5u4fukfI3CGD9Arc pHSYQXeyouR7rG4hCgj8wq8mgqR3ie33XuXWO3vqvdAJk+36eyH9Py+1vaMtviuuAzQgV/X2hTQS cqif/m3hDXCj9Gxy95ym/ZhklZvLCovlTG6zzqgixRuy2g1E0KpI9Et+A2aZWUzHz/bKy6TIJCUn JwA75hZ4eGgfoeteNBoHdchHn0zpN0y6/T6wUug+3m7v3Z5fdvvIjvfhzzDDEkYZy51rOG7sX66s /ksKivJnqp9GemHzJToyUHOR8q34QOAc0Qglis6pyvwGmu4vJGwXrFOqLPZfn4T0YVHnC6T/jI2k AZsM9Rn4T646CY3EA19FWdshP5LobdLTKZOWQGd2nJbBGMffYSwvk0EDDcxO0S4yGOySmfLN3Gdg 61L93VO1zNjKi+bXbflYf8AGYod51gswBJ4AP6e02xmgqjx77wyXGCBd+7Q+BgrpM5SNodpFEP0f NZ8FxCjJk82DKdnH//6clMHeTurNlkp2/x+hsNjiPl8dLMMCTSm1CQD/BCNl05aAS973aD1GFL/4 WPCrmWpff1lV5dTmUWKHGMVu/N3UiqwBbmNM/FLTsGBxOujN16byzWRnrAc3BIa01ooAgLxmN9Gr CTvgYyU45UajraicPb0Kwjor0xOn+rYvpsGMCh3SJq+E/Vu15+QlyuGnnSb/mH2bxChVj+VZSOEg dLC8KtRsn2U0JYEd3j6u8gTxgSYFbAsCaNlzlc8oX0yByvPIcGb/8cjvLCNR3itriBH0TjecT+YU AbGOLY0lPhCHojQ2AevSknwoEgAD0L9UTPNCsm6yrKDB+J1kfWzgf+22pK14zaPzEzKIyEE+oAtg 900RTGlw0ekOwV4ZCGHUbrXL+k7gVy+qN3BgZC9I87t1IZp6hQcDBkMNRrNXr5TDypFc+NHM/f6r 6zJ6kFX7/sCfC/rGCKsEoodW4gO2NoQFeW9tDlIuLgbsMhwI4y5VoHXhpxWrg37hn8CHErfNZmyT VxIKKe6Db8igN74ksk+ErtBUzPxwLnxrWCw2YYiLjqdh0SkqpcPDjIY19bO7gRlt5L9TSLmjFchc ItxNBD/UGsXSDs9+aoGTqCz1MoeJbCxFhZo24TkehLgBG69nwDdp5fEXiuN6NoF72QJRZPYyGeHr bz2yQhJ7jEzdqAQKGLzdtoAUpEO7roCocO6XC36h5up0C5Soslyi+ve1xBbZNcio+NO5KOLtdfo+ 0sHQmLWlxMa/+B94kbpGY59PxNtpZqvHqGKiKIDU1BjOs5NOKlAvNo1hrAQm+FuDgodgPgTJRJND bB6V+oP8QrkE1S157Rj8Ip7qR6V0FLe1sU2nOVO6bw7eZo5k9m9bYY9dA2yzuwPYH4a5tsxzFNFO qZefMNpe1p/QRttHLomcAWfd5siIN75aBd2bXiopGcWO6WUiEv3Fi4HX3wD8Dx2H3SjwoP1LCWK4 xlSyLYocmVemo3Rq9Xw5IC3Riur2bv5d9YRYanScOcqHU4iuFHKnTB035puX3Br2uHOx/U0ILQ/H p6K/6r3EmFrCbHCMFm4L5WAJhFWPEJcfBZVNWOBLp6zX1VKKq27SxA4B7Zc9UnTZfTzu7Uhe9qym OsWIYcdcqatmi9+mZay0nxxujuniBcfpZqv5rDJBfaPm8vVMQI5XxQCsfHdgqOX6Ngs+iAj/x8Tv 1ZP71iK2yBkBAEI2XynnaRNdCCKsRjE+hK7plK6Q/K9Z9aakXdahZuSoD8HsYBV3GZrAqd1e6uiY d+SVUHnslxMVVVsBiZudgoRw44rhVK3qHjx9fag18CjCqIj3bIH7in+44U6CEvjDOHZtIB2+9ZOu ePEDghK/ljkSj6bHsbLmJ5s1DbjyhrkMkKLQ4fNjqKVTWfyBlSlYRQXfGk5ydr7ChCIsr+fsUZTt qBywK3K+P2aW9ACvfiXEsF/ZTEr+BDoCoftLMpVDcyVoyAgVIwi388djPURVrrkngaQ7oVGJqsbV OJjqxRajvad6vqLjNqIcXqMrk0uB3oaXl1Hlq5aOoDpGK29Q6f8uTiRZLkYqY0f3Zm8xMwOGk4NE a9M4PhF/M8iRM9nDk83D2K9vpxTiiA4S5Y8MJRSOkEXzky3SWutXhLsErnuCwnEPURyvoMRoL8CG XbVnxAqN7q9ZTghR58VKrD4/MXBYwkamZqmEmkm+4OpmIT9Oqz0BeQ+irXd3aEw5hZM4NEizIQ2C 3me9EeeD3SZm/axLzY/yJoNJ1IBCYgCXuChjS3oJQwS/4t1Rc/29oDUCSkOoMCyNR8/PjrVzSxy3 PlhpE/9BwnIr42ev+hFbJWJgQrxBIzosOmf/5zugAhbJ2KVuHk5Ddb7ujpO5yRR7FVsrtzMmeQli DFfIGcAvxP7Pi/niWx/HOlUum+MslY+IonKjkf3IdNQuHwP1Qi01/8giEGCX+VfmFZ5VOaFp7njF qEnQCUbzZcfnyJjQ7IxyBocHk/mOE1HM0wQi8X6WJ4MwhougwUVc8MyvBfGvKuZLaknvSXdpSMm/ PawH52khC6FraGOj/C5NcqLJrIlNR0X5p5lSNUaUkNW8H/eo+F5E3SHPbl1HcfNATv7KBlTBJd/f G+badCilzOiCpterkNEvrRA5eE1630sZeuYp41XUavhNpQ3yIi1tKT2eHOrOaZ8Z8gdDe06PeCEj JlWQ+Tg+4QZXBixET+TFwR3i56KVAgYDVfGZmDv/rF5lW3e1DaczgQ77WkhVMUD8+tycf/bOtj3j ljPd8V3gG4Xlt2Q5XboDK583Jk22Ian49lnDUCtnAPDM6l05qxrJjJdaWZKMlz+BMJlFBS/7tkDS yPVDcTvwWOWJ+phg3YbEQiFonJ9WldsTsp5Jqx1cinWWwkFGQZH0kay2nx15fPd70jmj7VDJWGn4 k61Atnqx3HnkouQU2B+zGzml+BlzownJWUkTbYSIw7qeYg7I/pa0hwV7wBV6qh7Q7A6ESRsz44Pv 5jecX+jNPphNNx6BIzhvWs5lnJsoEpGQEidw8qQ7sdehmCVOMutfLW4cxHHsBD3lVhfpH1hIuOPS JuEHHfpAAzEkqKk/XSq9cJLWvmGHiaByaugFECwvgtbGclRE71rvbFyXeZD5/oEi9znBc7CnkP6r azQzVYtITUIT8s8flXl2ki/gDJnQFq/kSJRIZkK2tkBM/41vkr4bloCiTWB03Hs953gF2LEJd0og h5pLovTW3+HB7Fil38xvqF7+O5SPaShjg30Z8Y4CF2sz7vfVR+qW4aUvKezl9aWj/2Q2kfbIh0FT ybEaXohCmdZEgL3PjXoRMQ/l0gX2pHQnY0yHLoEPQCs2bBFGsvrx5JhItPlWUUNPd97AA2hLryaE B8jyFE7mPRey0ixE0+A43VPJgqPU4WBlaYAS1TSzI0X6XId8ctnUdqgn5MD8JgIFvIC/odp+KrsW oYt8OsES8D9ni/OiIZRZ9tC1+uCQsEQmo7KYSNkKKsXLvZ6HwdQsayl25WtK11ARCK0hJ42o8J3U TIQ+bri9GfQ4qUjkzIAKMn8v6PU8nYpaDVyAhVESdPrgkYDSAY3A5+5ko4RhBF/0yaD0LXsoJ/rD swXZUGk/tJ6hec4kbRVJTOkUsJOGzdKb9vhJoROG2iXzlCRhtsqBOdDpioZwlGcyFppFs3AsmX5e zznFenhjDyk29+41yPJjgrXkkTrduiG83a6YB3uhUx142QuVYOX47lbF+6tsl/mGJkWZVZPyrDM2 SFPuHvMjAqhfj9YEVuUjmOHNhDlyHmwfzCYRU1tgz/MeBF0BOBcU2qv14ZMPAMhjNdslxxx2R3Au 5ZXHS//ECV6nH36lXOT6ovVpYmAlet38nNkf/nwIfM61FpPVg+9ZuGampOYhGlB4Xjnevf5tvgVQ kkkJJe7diN2GSc5KZL0oi/w3DIpuctQCpL7XjwNMt5VMRzm2DZrddkLye3M//G38YzbemUkRK18z HxXskARWphAsZhl34ym4Kf4A6REa7hc+jMytxlu/A/kPykBy+WXy63UUJ1+fTW6I9JdO/3q9/jbq Ketwo5U1uNXIV8dpL49Y0vnkJHJLcq/Yg/gquOBoK/P+sCqhmbeYVsTGxdur+qxMbkb7ep9eaVLP 8pQDfjApevJLOznmxf0csR8i5HIdiMYRmJb6RFXhSj3daP7lNiBIGqXr8hGiewEC2GR0TA4Mi9zQ 8md8ez9jIOAHadPAih5I/IXqbflghjCBpCV65+908/veZI/LyYgyzexs0id7oT2BmBsbVJdlSUjz 90uHd6r4Qcb/1X+WXo8zmMm/JONxeR0WF4EPZdcDr0EdnSy36BHPe1+N1PPrLAU0Zx3OiNVhHemq PL/+En98K5X2QRvjpH0QCi/KgS623lnP/O/BUxu4TPxWaPs4E2LkYu0b98klKdBGBfyRbhZCvG5M fo9qdrueZZWFnjz19707l/M7+0URJBmBUhwDECoTDjWK5oU+fe8ULMy5w6yknn358HBVAmCOYll4 wf5O2M1tMegJlRQrevR10kYo7pVnvnSZVkn/qBHnhsNAa2oCnlJgwt8FwFrmjBb2YRg40pBcV/2m x2k6Akw3vYAGldfkKUCPDYTjaVMQ3dSzzn8EpR0kQCEjUhkuCs2dxttKHI3w+2iV3REsXl+X0q8P x8YNiAoL85QTdzDtX7fprww1rrOtjmnUypz2MG8WSNRVg9ymfXOF8Yqb59gmVcYkT1faBBHUCBhI RyGY5GCjS33YcnG1dA+bczsp5r/01it/G6gT/mOJ4SzYzJXe56+rORttFA9UfbVMf9Ysg5V9G9bl JA8lGajqoHGi2w/rp/AGPxFAeqZYRPrzLZq/GVCnQ3L+Gauoii4p73gNVCjm1Ndw19XIqMOs0hTi h1TB/flka0bRBLYPePCbuMVTND2OVj24tPCvhcQdkXeu9Vxml6aMEml2/bGRCJDegwpCA6AcI6OO QJMAqZumdxGSaUORNj0sPtVNjWlB20EwoovgL1Ams1Hp72PRBen2fwHw3KdApeZLWfvW0EBVXMxs Au53gnh+IvHOuWTJN/PBGFKZU5lPmI5eG0Z6kgjQCgiiWGLX4pwOF11E29LMdqmPsgt2ZFnqVoV+ +OIf3MMYrpm2bIIu2sO1FsGbSUNUNFr4jyzQqYU1fliEB/p8EbXcLoOlQYblZsnK/nDZkc6BNUrl jQXUX8xJoTd/fCSpWxIcYzmCXtEx2atibiYO14xdCb7Qvr5NrFtbV3NbOousK/WOdLqk5zmmvLk9 pDMxhbNqrZvBGSBPvs8vvsnHvIXk97h5awRiRBdszMyxxwuZQ9xVHCkF32ylvnQU5Dxs+b0/hQ4H MbEjSIkB5GQ+Xk7yi4E7RD/tdQYz96a8sYcGGe6qNfakH7f7aNe9vLAHOCbGa2d3AS7bJPCvts1a fe/tkWpW1rMcKcXiS4Y1ST7m4QpAPxQgyE+wk7MJMXoJ8d1B35IsKCA4/Oxf2dSWjdCsLzfGMo6N Jp0jThnD9lEVd0RD/fC0bf2dln+u+jhnr28ZQtbwuvTnWjHVHehfAuVEqalbBF1uJ+Ykh8c54naW QTGkBO6zs2cCQLia0V9MV43qXeQraS5hDyyC1in71eXi01rvrh6kW64v6gcMyYoNFuLB7o7/D/C/ 65nI66jCK+joOTte0D2IUpL8cgJPlh8RrcQennHecYm8/HqSD4TUJtjLcgnz13WlplV6ruhftVWq FCIHQpjicO+NyVIMikcoDT9WrYftL3Rq1/4PZCZN8dRxXT088lA+Xx+r3VRq+mjrG9WBZsbg1y1J iFXjk7vMvtpI2Vu1NytrMc1BciYoKByoDPmHJ/5yXBOHOWoT6HCfWFrmO3lTduoakhq0bRwX2fDw IRQlkd5ylMAq6vuwqU4QEzxKtxinP0VEBGHWYLTU+2daVVO5723DhBYgRavy+PLtyYIISRF0C6Ad oGVsSrPpCNSYhZbzd3DY9/+G7KneYaIhqYn+YWkLHk8bEyR2UD3JX0CaKZriJdjvt1DYRpePA2q7 YpmQednFht8hbpJnlWD7Pw75/kRQHckFCByNw16glAWIvjhFJ4Dgnyi7H8Nfdw3c/AGB2toWu/T4 8PwMyhuIh8/hjtWmgqMurz4nZFfyiuWrXYvYg/ywyiRLQ3M5Nzi0xZ97uxYT3e7niQq0y9nBA23Z 04NEpDj0i1pRrVjjosJI9twoV/+LrDLy6ySml1qv9ZMtL+FwvF2Y9G6YrDhUfz46lk5Arkxly4Ew wg574qk6HoN0HC5prBdkttFy0dNwjePzUz2lRlPynE4CyQ3FTUR4fF6oVtp+jz1Yxb5SO+t1Uwr7 0DWkMLCqdF6ZAJCYFFzwoZM545GtblNW5x4ktXN69UrMng4JK7jiKcHdzYcmkBBpQQR3Fd+zL8ze 5PNX79uFochONHtMX4Hosz4KeHJDcgmbzKqltDbm4ka9tl2+zuLHS7lJAnDrUUFoVSSe4lm0ErBK nRTQVeT8PNZUvgFHk+yxi5h8pF2Z1rXvZMMn3HVkbJ49yXhACWEzH3tYXlLIfCVp3uqobEN5PSMA SvmTpKrJmPSxvcqthi2XAlSzJgJemXIjjqaBeSYkZG7DnD0UxVgqqkYUzuxCcEsVV6XpPmEjf96u cWZFilIpXS4/zTHyRMIoEdaT1KdgPmNeO4rIwRqnotvR9h6n16rQ5zHCEu/fn9+ny56Dco1uBng9 x23xmSWQ4oNIpk1hmxSNtVDNe3MRuU/MM9wYT1yq2jJA6hTy2ztPmCxdIEFjHpk8oHxPQTVwYI6T CiNq6mbgtT73j8OHEQYSziD8+c2xTzN7JMGIIg7G5EYRdrKDK4UwmeHz7cgUn0BZ8/z5/fVYeQUp EC+/7RotMJeklkzKZhjRk7rjF+7V7yePmgrcLU/Cc7L3jesKUCQN4Sw1GvO15oaa+Rg4VAzJwkwu vBZEOBnvQX5Dsd/QMOZvgqlknW+1Nsc5o4LWnfVfVt3GbKPGtQxkG+yVK1uL71AwY3bxgchwBoel qo+Rd64I9hd+N3W5RPXmvJZ0l11izG+vTcXeGVP/NHQIh01N1w5Tp/cgcXRJMGd4jWyirx02EEQw 2YVOU3Fw+P2cEbGqjeVisvGBn4jd+mTvSKGg8fB9PNLJvc4Y7DDM8InkzjRKgnYmTOWOhJV83lyt yn0In87cp3scIma3fD1jMmh6BYfYKGR/ZLoJOKK0Kj9YSU5h2UnzstnxkdJRcimvYiQaO8QaCj8K j+xDw7vBMash7jkZf0nC/ejz1JAyLLEnw6XtE4XxaVDEGKCPCi4wdcPuqhnhCqKZy/aHFVUPeUni xQs2uT6Gx5DQ9rh12KrWzKdfofZMiNRsF8lPirH2MJs3F7kH6MOIyayZ2AF8TGyKNsHnmx3gM9R3 9lEDCNjw/ON+gTPzeEjEE3qfXiDKU9dVADK2hghHuBbBCZtG4XCKymG8cnNM0jgrBTEPf5MOhnMC 4/4co5EuVoVugTFzGSFIf0biVcH9AzodyFKT8A/rnvSMq8EqI/baysCbktFtdk7KlvZ7//AIE08p vy9944vajPW5vpba++kv00fibHzDRYQWAAP/Jr8hSN+cjBxOQVI6MovKJ+fHRCkXvWxA2RC89Lzl n7FYjHYolHa2V8Eb1kVU9gh69occiVJ2ItiffdKsa0fGqV+HD9t9uZ8UzWErK/T0IHSYwODR52Ff DkuuZ78DbVREL7ywrwszQhz9PE9SO9eKT/e3FpDFex9DQvPKydPR4FWzQg7Ry0nVm68iTdTmq9rY AUltVsfZkkkyXIWL3llyJs/dpj7kkWOJhwbhr4q0+j19kbP7TQXZwb1zKAeKFpGxfOWuQUfbTK05 zwOmGvK94GqJzg4HlyFLzJgwYHU0uWvwG/rUbw92XJ70s7M1Bzm0bR7pJic6EOE3qiFNleRnPyv8 jZkxi/eAvtxGdDLKOKm+d6M9UeH9VXIG1OEOmVNBP/6EZZNvFNAft7zWNN9Lb1/+2zrNY2CX5y+P YIY7XbIyX1Yh2meRbtZXAVCbXb7pulRlBOW8KwQgE8SoeHkr7AXHnnqk+WWHkRC24ZlR0kytUStx LyivKkt0aNR+gNFvPSv4UaufF1TMBxroEXBhUbKBGrMCeFjnVUkles18O5lkqiANoLMD/CMG6hEv oEDndtPpq0X4oPUy8HzqJVHxcq30YHpzREkySJa8mcFa8ueUXYlIea+WUso2s3Np4YCLQkTbNxY3 qypO7rZhwVCr+oQbFnsSqX/TaTyJuv4HtOgxg1g8AdCbSReQctAEQX9/4a3+VfoWzdTk7HY6geGQ gHnHu30yiees2DAbaE0lxUsRvYMvDJQKWENOFF9mjhyTBZKlMlIadMZRnR8eucCCQCDD+StDA2oY HoITGf3xxz7ZfoNxzlUQue9bbuylgs4vH8JD6evovgodDM4lKbFNVKP04JwwdKUsvXnTwKXPOjs3 73torfqfBwxWYriuFVFVv+IASJo55uI+IT9zjnUTw22qACrGQF0QoTJWznE8p0joclWyINSXLfAR 0E0lzROI5mUjxfQ8DuMuzfYlzmvuC9IYNDh1egX5JB8tgxh7uZ8VOB9K5Pf6VSlk1R5A1bP7FD0O Kw1negyE9jZFqz5zfRd5mQCiT/lSpqfq2ORDkSZjfgTcsCm7MOYLOWJK98k1ixAXyCWIJ7TD0ul5 h32MaQ7Z4gmGwRyqtxCEHkuV4SvLQOlx7U42q+Yw/WYNEmvIsEP0fWBTiGya+9Ik960argvIoZrs 7Wsmn4Hu2zsNuRZKEo9sMZtMypTPz6AS/qMkDhgA7dyOL8zQ8HFKjdUAYbDVR0GTkpY5i2xUa2yf KUHnyxG/5O19+PW49V4bo8ChS5bL40+CqQftPzAm9ave6ZYF6g52gN2jYi4aW1qqRDxc8Mwf/Znt df5q7O6QVa9hQPJ7wEO3KG+iQsgwl2OpCz2tVPeY1UvY+yLCaz4cOTHcay075waCjFhvR2fzgRzs Z6VlNJRvM9GMX6hpgv1ZzNsdahMRog1Pd6wzMvb+6JA94rykXvdSy0CIUWVsjTkfClSlpP40KBDZ 0BVvESURJGz1vAm5m6byw4ct2fw/fZu9jOUjWYdBH+l3VMR1R9Kb8CtPKBYFkiyqRTPCGiOIB6Ah 1bRJ+FIVu83+vMdbsxKRHeGDIgBYH96tZbhml+fS8zqXYx5KRsLAx8ng2tkYXcRJ721Kgma6nsEn GDwKh9CQdCDQIyfTv29p/NGWIpw+z1zpSROkMq2G956YCkOLp69TYHng8HNs1un1R8lAvpzVwoiH aDxEM1o0AgQeXgErB0iaCHKLuZBclvROra0x/3t1GhOJeP6GUHZPdxgSpoeuhHUeGrRpfMQRlfn+ pIN5PgYfwyCANand1eovWzqJDy13jLS2/aMMzrHZ9bYv/Uv1YzSffNIFdk5l4AUyCAAddsBYU4bC cCgOseP7vAkGnz3ztz/LIC5okfqiNX1lodnhJpE5/OgQcei7oiOq1SdPvf1YLkE7T1b29W+1vd/O OsLvdpcJzDSJxozbXNkIxASmMJu+T/yp7RzuN0imJPzSW80cotvRIObj16OQjiBQKes7XTlm4bT0 TTNQJwrW3uhyrvaRP9tc6a+0COSTjVGsN7PW89GDAKnNWDvy0KvD18NLuoOUamjWvdUP7dQP0l/u sCXQsmU/XlkqYXZkcaHxRQPhBzHQFZw5poC/ojnxjXpLOzq2V2qTdnpkE67AexPyoZRrpJyCfiV1 3j8LxIXA2pUUUMQM2e2WuZ1r735yDmRHR0mS9dCCKCZAB7vxB9TUuEOgk5CnIiWr2UIG2sowwvE1 DgLMpyjp2U2PyThAHCm6+XyWW5vqABbqZjAxSiPPMSibyN5aEndnH0l840fNWvKaDLzCM8ZZe0Lh Yeix2co0MBFJat/pAPXCDKnTvtSOvMF/cEw+EEvOH+PMqWtLEPO/oaSeb5sIotgQI5On/B2vYSBw Ov9uijXFHm25uVVmUJc2WHUg32+51YCLCoIJrvJJJYNtkb5vZCm+cWCyVJ7Xm/rEio5T8bjjvr4l tSe2AfB8V99R12Ul84K159p5edDKegwfoP9uC3H9H5jFdtvkUReaBkHcN3Yeptwbimng+AC6khHl j7K84WgB2MfjV3rNu4deoVam5haVB7/8Q/ALU7XzdDb71vvqZaisE112S79vQrFl73lyigHN+cc9 2onQN5E3iCt3vjFXcROlLO7K2InJtOsf32N7e409+o50X0cDxUz5OXvVeBTZFHiF3lPCGeHAtRAM 6YWCiz1FwILMum4AedRSaLHmZCp7hTQhMHqm03hHlKxzizyL5WWq3Lc0j7qEwMtFvnCiUm1JubiT 8vAdYQ8LVDDBJj/3RBTdBCx1PMWzFsmwcglfAqMXPcB6rdcD6wWwPlQx0JdM0p6BhGE87FcjoOuB 0BhP5pOi3GCrld5ZNLed5EZck+fwUS+iJ/bQw37b1SU6TY0z40Eje1E13/8p4/gN9ZmxT9CGxkU7 Uo7lMjPRjMSDXp2q3NNyyPUydSCnv2Y1L7wKhguhj0oZcR4WqXw9u0lWWUvJrK5t6S3GkWnTNm+0 sXmXkJ4G0uDM3kh0koPeX0ZggGWOEL8DKQ2B12OzqjZzBBd6LjX0v0ApVRGJFl23tgz/bjgvORAy 5wBNE/18CyG7bwVxR1KCJ/ue1pur14rP7SfClbNMKPqIfLk31WMR6h6vQUCICET5K5YzepTHpvsd 7v537jIYISUUJCLTiJq4g6jbrDdq2m8oGbABvu52XSXZpC3mfl8XWkQkOjGy9/FyBmE2D7KQPtbu jJ/Xft7lwi51CbHTYKQHwd4RKUqloZxn47l+GRFcj+H7KFRZFCgZf5pnKZMvgtYYh3OS/OsIDmQK IwXNtq/2wutdTETAiXS4/yA6S5WPRPFJC7LQz/ieKM+YmINc4oh9DX+Y5bM7GxLgwhiJ/wQkDm4j YJXttsCcUmjcMBBw1er2L2Bu+BuzeAi871ZH7r1noK9JQvqeJVEIGByif+mjLUyRhSOFiYzLBi7D umbVmYiYyl44pMOhnfRjDBZdri7zFpBjJncSGxNLpwDZaBSTNWTgdnGFB9yxdDyuHg5y+fRSDIav Fsrsnk5pO26DhcUkr7lu+9giQLgleJ1SXgoKv/KFIFLT5ZnKnILl5Vstwjjgp6VrcaMCBxqZK+27 q9McNGGZCMvhqLwxJ3BBYKPFbkm42KPDfsLQz3c5RVbgJwkqulWkS/+xUQ/PUEQFXXtegMV0HzW7 g8bOOW9xJQOv4IK9DzOVENQx8uMApgAZPzVXDwKIRlEG/oVou6P7b0qrQMM47Bsn4crlVgKAX27A 2lB04xNxRYIM2C4C0A2eQsQ7UHIcoV5buOvZI7/CL+hgxVsXGnJ9vkhYhMpYZ2EZE4ek4GFjrOGm EjYjFdevwLzrWcROkVWtykqzW+IBA8X7U4YsGZnMIZLnsydA+vPGE1IOaQokFLRHs+OHWkNaqoN5 jlnBt6WJzQMWE6UEzhglbQvsOOSUb6MCEPPREpXBHUNYUOzdnNZ+47VLdBw3UVWVvs0wllCGfRMn 97xIGvV678P3bV/6IBeecJ0a45x5kIa9XsHQnp/MLPe1x2OxM5hcw5HVuGAuauoDIIoqpNAV0WZF X/g03voJkoaeDXmgCzn3J1Mbdp6HsFnjNh5vkDgKXNDMgkPprn19wiu74+bRHKaBVKQfecg3zBU7 fsuoHuy3fQU5qbZMXqbQH/YoLOPuMoYCA6B0DEqS0x+Mdo7JXUkUYiI0gH/qU9nbnpFhtCrKnrTU /MUYOeMhRp+olyXOwj5QoPjRwm9MBVXUf9lVEnaYaQlwacEIu+3jCstxNYux/afuOB13C1gHhklo mvF+VY+JzS7hNBXewXqP93wqQ3mthqzbaJLFxHJbkfyFXdz9RPXlHKTyT6m55OzbNKWtzRUhamM+ 5RjvqzCUSbWHKhqPipBsN6x2dnB53fRBb9e6T6gj1VIZGEH3c59u6YZDRJYtYDuZvXDmAO/ueW1l CpCK3ytCLyovTceTPCKozhZM6bHF/wkR+kH5JvciRyGF8OX7qHw8yyovN0kq6L8QEseP1nHOvtZU xANLGDAOEmMsgO25h37hcmEN/rccrKueBIrIrNlCJ4njswBL1yBVXJ7VXHJh2mIrtRZydW2fygNB VFVAya9C6m1mc1KwWQkGUw== `protect end_protected	bsd-2-clause	77d65ea15c36bd598f9a038385e2acab	0.938218	1.876928	false	false	false	false
siavooshpayandehazad/TTU_CPU_Project	pico_CPU_pipelined/FullAdder.vhd	2	728	library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FullAdderSub is Port ( C_in : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; Add_Sub: in STD_LOGIC; C_out : out STD_LOGIC; Sum : out STD_LOGIC); end FullAdderSub; architecture Behavioral of FullAdderSub is --------------------------------------------- -- Signals --------------------------------------------- signal NewB : std_logic := '0'; --------------------------------------------- begin NewB <= b xor Add_Sub; --this line is for changing from add to subtract. its add when Add_Sub = 0 otherwise its sub Sum <= a xor NewB xor C_in; C_out <= (a and NewB) or ((a xor NewB) and C_in); end Behavioral;	gpl-2.0	27b3c82e325e959f316a4ef934c2b3b1	0.498626	3.772021	false	false	false	false
cwilkens/ecen4024-microphone-array	microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/components.vhd	2	77,934	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block NCnPn9EMfeeGkNOZHewsk2qZjbTkxCAiyhgG7pHWLqc2/977+UKlUqmmzmiUQIt3UMbuuZNtFyNy wNAW6QoPkw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fu6Zvf3+vM3aj30F1X+kRlfGyKq+lu36azwkAmQ/sAgaosjIVnGuNPUqezfuzTUsmFODFsE3ticq UZD59nfmPkza5fxdJXTk8JHVsdZzYh/7Z+niwN039ic1DiU6DrJjV7OU6aSS/+FS+xgIBqumAVZu fmnOhHvUNy5Vqf7e/Tc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ou/4ZMNrjfjESNRf3k5gNrbFQ6ZZS06x09izPEG+Gb+4vjMlkQgfTrxxDViYYIuIkGJvNZkhOq8c cOjDPX3Os/3aon/vqyPkgGNOGoRU9d2wLMUi01z2uHKAbnX2w7cmTrGWDDOxkqGhpc58/JwwWas5 ZVcGa2yCq6rK4knf6BuRloi5w4Yv2RL+WRJk1Blv7BlxtW2er4THGlE2ndARB9RaukSWfM900Pze Sgonqy+HCkwzVO+7zwMo6H17zjhc6ovcjozMnvzvlGM5ih/H3/n3uDC0hv+yEAJ/tZrRky4/j7HZ DgwUPKPnCA2KtARPPQAbkEzdc4TO7A57PEBdUA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4T4giQRoEvLDG82I3rVBwAuv3zlXlryL2P8ddyUrgGgIqBIFJq41WJCeE8Zy7Kasxw+AexW2ZYvu US4V/jYluC0CifBp4JV4GSeM4A1VlmbGhKV7aqSjjXdlTUFCmoozW0bXKlA3XugyA3k/u0GWRZ9m phOZ5YXCgLPQB+SmxCc= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hxCvbq3L1ht6tJPA8Gl/HytlQsz6C8Tl2nQ7RXP2Rfzzc0ZB7CiJ1A7jshFp+Ub+fQkd3A535skn NqOz0IP4XzdNaaX6x4Xw7WF3elmtbjpck3LDefChLY3V7W5P6STG7D0fN4EoU2Wl3B6+/Qks19rW sU+gtK3inD0okvDoku80j3sywxOCgJBkKaaP+yiYTqvH1/DkTSLyUaMsOnwfbIH8mLn+BxQ91plM fZddw8yJbLCPBGvJoguOjdsntL+sBpErBZ0iFExFZ0KL6FCf4lw1n9pMkI9Sy530wMUO8jG2sw1U IUN9voJbajwjfjBaeIb3Q9zk+P4Y9KzOP8tSlw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55952) `protect data_block 2UwaJ1mZXkd2cQop4Rg6tMFNqoJQIeYa1cfyafVUZ3Q5XPyy+HyAnKtfvFr8CnwgZaUgLQbPnDIe 7yepapMkvEcK5iKDv3kn5eNhNszGFfyRZ8Xy/B2QqIgdM+VKZdwPKIVqVgitpp2YZ2ktDsU4xdNi RKC7DeiQPbScpu9M0Lpega6oD8J5dOymjtjxFcBikkdl4ffMdFCSCDPf+a0JvOtTMTBnJhhdxTfL 0qMLhdX6+y34MBlvhN5iVv1GFzBx6dpIy9fjGsz0DXX+Lf74CP84jbHQn0t/H/oI18WtVhUYkvIs LwWMqeKSUU9/Yg/J8xsF8PYQI2LoUFCGj3on2IbA6zaExc9k8kSdH7VYu8wI/cA/7Oo1CCU2R2hn urtwWSSNNdXbmWXfLGefzqiJNzPRLYdGiXzf4dWFj5uLQQ9sgq4oEtD+wiIKLDF7ZhLIgdvDNdl8 lfetlQfWdnM0VGOO3jMvE42pUOKUeRLLAPquKQeYgr9eP7YrxuVgIvoiejRjaFwjn4GgsvZzeaF0 vwJpVSQnkIB6rzBBvkTKT7cXdz3GKDkkeCGCOqLYd0w6fCmN/Kjvi31in1t0KJNX2lVAYCiNMWhw /4cX/cZUQ/S5Tz6tqApca+IaGZO/Jq7iDl+E3qHWq0zL31LP8yvxmFB4DYruv9u9lMWFguOiZpBX OG2Rh/EZa7zkqNHGjqdszSJ8oByhj3s5gxBr146fxcCrxrkM8AmIZY6juoVNbaQZ69wF5wT22xWB dKDwUV3WQffUo9cy32nk1FfUIQ/Tohq3PRj0bI4j9JGxE8+sPHfnEHTo1KLOjLrC2fGff4K273Bg 693+aenFRjPOKy99+Uq1fFnANvGTfgRFpod5D2VsO7NAPTpeGZb8BB0Lx7t+6LFtC1e+W1OBDetd 6dv93nNjtw4naPMsu7Uu3BUEZ9uv6O+QXu9gpHmhTOH07ydbv8+fPlIdo7zazq8HpyR5v3MVjv8O 7pNp3hJGNVDGKUrNj0o5wsnTlxiWMjyL6lU8XoFGlrx3iJb6do3XOzr4ngPjRCl/ROAm8ZgiZNiC fDT+EjfPTOC3zTJJ55wuzpQgixwF4x6X2Za8lziQ2A6+fhaq7PqXRRqyT9EvSy9vnu0+Cj+301RE RhVg/xi1N81LDf01RZr9Y6NNpmkYjAUXwFihMAW9LqVghLzfupGviE+pxtYxCE2/PhYlISkoQANo jE9g5nkhtOCYGOUI+dXDP5I5CDRtpFuiNLPANJyAcF4i3fbzGsNAes/49dno8BNvRCdhLW+U1SZd HHKNu61vLdZmBNe2ALwU4KDjsBo3EO3eGHl+7iAakJ5A5V3zPAkiuvez2O77rxUnRRCVEcPlsQWm oXOv9btADiS6s/YYGvidEdjduSZyOFBDZg2X9J+xVkGX+LgAl4RwXOKHtrcESnktjPNdNAJt051x OlzDeC5xLX8X+KOZHBX73nb5QxoulXLgfwtCB/c5he5TshHSHYUtPSNlJWhMvb2b7DDpbNRJXE50 IWdM1pGHzuXTYXjGsUqLM19FKOfLV+S5hlWuSEj2aMRK52JVXqJbwAAqAgNQBMYu+nzO9M54jddX Kdq6w5vUL7FSelDlRf6EnxtVPypKfjGKBxsJh/5mzMiOC/KfYeYtHreHsbGJ1fJ/V7+uEHMKc7Fb ijCKqZQO+St14mLJOIU3DHGSLn+nyeUdXoV4XOqS8M3aE/NTNEhZyNWZLgOs+wfQQ96E2BCbjSyU mscbjUOGR5crmAx6scIWR4dIAF3PK2y1mv0wbDsDMG9GYi11Shc2eyo/Pj2f2FAtxIRapCYQS3Nj r2uio4hJO5KYeh26FAWWAmiGJs2kcFhAXoSIlfV9iCcb5Q3igENN0sMvZpMebY6bJrRHVxlMxPdu rgzjahUNs9e6BMSulqTxnFJSqPIH1E3vqYgPmhQGxkURQ3W2vNTMj4wDiN3CZ/lurQiHWVbg9QGq DdGafdutC+00rrqaUt3fqs3KT0KAUhbbj4OdhwY3G3Y2kgOw9uh9SrlMEiLHphXXpwuTPELPc+LM ipCdaV0e6Lg3xC7rNTP1/DjnPo2smgmlkoVejHq8NhVvvWdfiC2gr31p2WkUoi3ncPh+a8DCyiQl udBTT4nYoyP7+jm3cbxDmxPIqMaiAaYzayQnh8S4LeyHgIximWwp/ilp1BhQyKYu7EbKt8j9CPMs BPeMbHhn+DQCV9XK5fav1GvCpw1vSI9UlFwHqpQh0kfrp1Buv6xM+N3qCy1UE4od1JP4+UUiq+aB nrngL2Ypz8KpCmKF2IhiOxt6on9sCnaZxcthTAziyWc100IWgWOyp3aOiXFgKE/36ewixXv05TpG ePnvLhRpnWS0LDDPzeOr+vZ1iaOp/UEVqJJK+73yErj2zO3IBUTKCimFhnq3RAs5PDERqrlmtyp+ jdweV0pwFF9HBGDOxFw+xYYf6fR80KBM1qhS9quWKJULAK/OEfd0d0M0R7khl3gPJJNelr0j9h4M 2gKsIICH3LfCJgPSQYjPS3WlGrpqx7vB94En/ir2gLfJs2QPZen/81bYHtqB2eJMOEIGDTCMKI0O NQYpWCXpEkcFX4FqOsC1y8tz7qDsf2jaawhyKAXoqrQ750phd/9XhzcBxRSpd6UA2KhNZ3yuYQTP EDopjYR3j7hs1O9sb15MkntZazLws5xlANcuItHXifbg6XRR/XehF7U8Ero5Ga5MbLHOGyQq8DlV CEnsSk9aSPVTCiC72oW5ODBj0h0aFfA9U2nI1GBvPv01M6hZdz3GJN7pw4k9kbCn/SyHhfEw+SaD iEfJ7YxC8kycKZY3DBXlqDkwel6z2Lny8rR8NBq+fdHrSc6vtnL/vTFEftq5Kz/jAjs05oWeJiU7 ++HgZJgRC0B5cTkVeHaefTaPWJTFr/ql1QTVIXgVk093bXcdvyWCuH1xYyHCuskfLC5c3TpS/2G+ 1yrXpgUtHB7FP+vXFLa8EyqirX6tY8S3EpuWvORkezre0MsKN5ls2RE9pzzAwTl/AtDPdVO0PwXG zl9/eZ61lUbvFqoPAcg89v6C+SuVkDSuveqXhkYfBCaNoUJ+g6RqIDZRcLWSa+449VXBzpxjpYzv LXd0rmIvlXborZexdz4kFpkrNZnqmkCwjmqfLaZze6bAbaMUOb9tQuvB8FQoNjqdHPoOi/pRO0Ev gBq9YStjnr+xI87Rpqz4MUoBSnxZUYnJBQIeE1+G0ZnGQcrBduQZXIzaXy6bUhXaMRBRaTQp7ZUl zpnaligqlDxcU29jo5eCOPWLsLrPwsJAyjtQcQzJGgo3YZ2lovAHDE9F+IHSITU4LicfFOD+1wgZ 7P+PdJiiOhplqgWLAgBtb0AssMDadjNejWpwAI0XcHCirQJndXnao3t1AanZTHw5itLRXHGPxce/ +n8t5mfDt70lj7BZp2wyK+OLjutju+eV/vlUTYe+3YC9ZpGmEZOPLeWlGIuHpvZiHAQs4LFo2Ta0 BYmauWN1cInCM1LUO/UboyHKpSIDe7QTgrPkPc7b9m/m8hUNI2Y+2oahRlxK7uiX4Wk1q/05WftU hf0uazQ6DnM/pttnwcXLJwR81k9BFYXZbunaMCxtBzdTg7wKJikZ+yZNPkDFsTyIvmgPpzvDP1AP I5rPvrxRnEi+C4K0ag+TJo9X7qDcFf4Kr+wnUp3H/HNM9twTGhIx9BQ2Ji2Oz0FwS37R1CZsPPYh RY+7CnHy15HncMPY7HrSc7RXhP5YTRx1DOsmIEAACz3fudN1UGnRcX20SI+VZXxjo+OrVJv97hJz J7higyUWK6MhNxOUzb/Ae7UxtKnyfw9l7uucJsECBYSGTVoULEmncGaxpsLcwuOVtlzCXhOoTvWj kXz5T93qHTsxlGe0mTrLaw3toqqmJqgDb0K9VyBYgB7nkqPu5JBakxiIyZhiY2eiM4xdnZSfbQL8 236jselF5YAtgqDdB82oBsoLbqC0EbZI8TbPAQOG7LQgdwSPM5La8czZDGOx2Foc5RV3+u+UGcf5 +VFTwNB6m5N4AtttlOn9XyyBX6AadDg4uIreVG0PCueXNwp3ZFAKbgVYw2FUsJ+PuaGF5rSWseGQ h+6tfbHBuJcwEfM2UBbUWhdYqk71VtpvNSbsamVCI2BMiYyI39t3K8FopqIjB2JSE28gEOqNkjPH FRfoTCQXykDmcL4cKwlhzYnrH73NjQL/MJ72Fs0Vi5K3VnDyhOV/ip4xWN7ZAdeCeV9I9YqP2Ska C1DDVe0sEQenbfHX0aCOasRlw7YYGxI/p9NVPknUupyaM0xIj+lerpUCM3LgKVhTjuozVMRpyO5o b8NFRr+lsDkcYI9EpYoEcx3wYcJZbu1IcD84vg4FUfWXbBxUKE8DcDluZqTiKKZdM+u19jhjNlWz GOfvafMsd7PbTmTpD9dpiV9p0yMb4HKVTX0+o7Mj68Y3mhk7osYbgRaFfhBlVeoXjCabAGlWeL9+ KXW5C8yM/PBQXHrfumr+7RDKfPOgVtPx8ANsxckzwxq7zMMHFnCw625o8TM/TQ9VUoZgBReeTC4H x5Jb1jWp2AXG84gJ+fIu+d1UHjiZEyfdyDB8Usv3aS4jPBT7c2NEgdDvK11fzUB3Qt5hBL24//rr O1B8nEKS1o1L3jLrJooY1Kn+aLVdQlDGnkTCjQofmPpOEs8E4ebfAH3cPb6kkgcwGSM0R3/Z6gij nDNiwCht0bfB7M0jNr/XgOzTJSICa/Z5h8vPxLSngEGDBDCHYSqIdsJgxbfmlmNXrKDOvskh8xnV DVE9IG/RxqNVEFWOIMhBmV/iWTssXpOYbobSBhX6vdmeCpOo9IBeEDNfe4KvEPaAMpvW+FYJDOY9 zLryyY7bCIBFALazK4EVLLeU1TLmaXlDYQym6ga2g5oqLP+p/h8dFKxBhmHWCj+ybAUjsM44G4ji f1uXNEK4mBeE3XEFxMQlSq/yAzyF1J7HxcIs46jhl29YkraQaHJ+uE0U7ahGmZZ60hco4smg++t9 BsSoYn1tOU4mf9TNENT3FGkLzFxHWQoEKqF6SCogBoRmaBzW6+LSy4OG00qbbzkoaX6kFnTxJMX3 s3UveT3Ow+IakjVH7z4I5+M/wFF2yHG6P1XJbTHpEK/rsR69FOVZVdcqwwaMXDi6mj2H8wxKLeLA NPuod6kKojaMvyhdqmWHXx68yC3UYNdsEgtZnhvU2hmlkY/uw/mOoLk8TW9y25syrDLBhwMIOp0A fslDOOdKjowVjydtiEzowSUyVzohxDTi6tJb143azzmuiauG1uhVjAKReM+erMVpTeti/CDxM/tI YDeWE6Z7NAJ5itpeYzf29I3uPkvIwEzjUyNUy0nH+L00bSYYYhnJEumNMwCrlOlxvEBnkWcjXq6k LyWWh38JIxBNCRXXTc8p0lmhhdkOizj42+xLe08ns1J2p5cpzoVQpEKdrvik0OJ8f3SDTeEffat4 vXU9d6kAZls3E9tAs0JN0b+Nu8/q1Aio9Az5zinyUwBUrTQv5wboibv0pDGPjnupVmy05J5JEv0K nSZTamgbyfFBJ3h2IRACIKWXFRmwtC+NJgumkzoMVs3qitJwzOWm99W/lIjUy9/L9gxUzU4GZdqR qmbEsnECoRGxdvw1U2lFE+fUyQelNdffGapvfxlpTCpmzc/rtu8rHZxSpAxWqfCbsLcYF5x3wyyR taMdSh0PUttYp+du+N+mo+KQieC7r5599iho5miaO2JxCtbl+QFPje0XKmXJDMMdkCILxKVeoHvs EdCbAAPSfynHR0/NH/WsbrrRrZfPYi/eWSnPhWK+2q0L8ENJHiI1SWx121eha2+Txz32wFbFX2Qk QfWNnBsWgSGDXuUNu7Ht1dte2hLbT89g+q+8rhrEB0fX6YLHiWE841lzH6q7hTXcumiu1qi/F0zZ QKBURVZMhfGhL3Plnf3RLcn9HBwxz9wExpqCVAXQDRRKMEukJb0HpjtBTBVXGNd7BM/wUqzigLrz icJHgvxSdEI6FVzCmVXN1i0s2U8fPyr7pA4KUeEzlRvreF6wuhthi5moT6yLoz7vFR9stXZBNS/A Te95VoolM9XydHBKFGGgzeeaL6yPFMk0I1qkkm/mZwcvZEBWzXGnPp8DWWwuhuMY3//Gg3J4ePHw bRkAOaD8Dxc/CLeFMq06y9Q2JMAbQ+F3EE+Sx/RB4APvdMjC3vs4HWGcn82YU7LquXAvSYXwefNA jhL3yJJEzjkHZfnzaQEB6cCWygLicJaYHSWdVqO+FtdVerjF+uKLHJLdFpj+d05me71Pq08ZmLcg 0lXH0vKQt4cokgtt7qm/IwYr1elxTm/7fVGSiJJ2VH/XydXgA5zB3ggNzd6gSsKG8ge+dLbmn58g bXOrdh/y1uI4f0Kag9+VTe1YTevsXkaa4CJZ6EpQw74Z5HHjMCTLByjMHS280ovYsDFH3qvCCQXk apYf/ziSRzgQeunyfTur3hA70QoOCQ9+XqNExcHhVULBr2gbcx07Vqe/rv+XevNPuBtO085uKbJQ Dagb96M1GPvvetOBEp5sozkEoUux5x2u//smmpe0sf2OEI76lq1mJzvQNl4HZXaELxWJuOJXgpAc zN1JVo31oicJQfouquZlIQevBa3ES/pzgumNXC7Dbk6SYg2psSHPEf3bONJf/yEQYwBa2jUC790q R+b08C8xKZM5v+IsdAxX786wW/TJSlvmXAh0ax1TcnavTcqmpANYOGNys+eeAK1vs16uGe/dlhvI oFvJqadcN0KqRx6OXr5eesNlHoRstJeN+QVjhU+Vj0G5wPs5WIiN5XrDpbm2iS7wN2LpLL0r/FYT vyPaxn1wNmlYilmwduzEY2Ar0t+uwx+tZbFHrxbZ1LwxbRNHJIJ23MH1KNaGkX97baFfkr+qk+oy O13WvdgcqiJcOkywNifMcDYWc/qr/OXkcVunz5Jy/9g/v5AwmkAzPepLh6MpoYf9aHzZiviFfOBl fFeLBXGv/+PvZRxcYGPFZPzC+9rdwXtxaC05gvhmUxT1TbfU9b0JjsTqODKEBcHrwENH3cY/NV7N iw1iyfBJmEd/KLTnjyMYYYvOsv+qSppKDqhcGh2De22q9sezH1213imYRyc64ugynugn35qlj/9+ 9wlfoKsPagtwkXj8sKi/KKnqzLQtNSYmMG/SHx0AhmN26Xj895lfgQQlfpr8XFMReEbtspLxj2SM dHCMh7ITxiksP1uDbSDFOp9fRpGsR/h7sd11bIh3gt4pbUspgSzdQogp4hI/O5SngGtfvZ45ugW8 Dr8KaNX/7T/zWZs+lyzwUgtACV8wak/ZlGRE6yYZQ4toG8Piraskad2XhjziVA2vNZiNqcUa41pw DjlaMmXv4slaXHZb8ZC2rL/KyuT0xACYrJHhB6TtDTAN27KGHN9Re1Vc3Z+xCxPoI9T4coJxUfsR lHUfhR/tjKgs8ThkGVuzRNvYiedj+59J8m8/b1u5d5svlZMgMmymZ2bvCVKmBiWzBdLVqICySPcy eLMuBkOqnQWZVlCt4qN5B4ClNeVqRPZKag7c4SnvyNjCHUHp6hTZ99v/bLu5XeRAQwlIpo5+xKZa 925A9KKC2KYGJT/UHqlwOPcOuvPy+RnWeKpO3+rfcK2rTPN5CIMOk9smUh3vfpcLbSBqu7KZgKij CgfgL3+R3wiTaay0zUIuGVs9BOtGeeoSlW7Sft1xSgQdOpvH7m06ymc004FiH/R9PCNjzEVHo9AA PGZW0OpzclpBhxpQ9ODkOI33hoSA4+zHwMDJVOky/EZYNxP3VFShX1j570D4JzjVu3HYrK3ZFPZ5 KnOOMg3Hga3NaRPScxTO/WtBsTFuoI+h1PX9b5xweephZ/dszLznvq8vX6Qrrv20fNx3i+QLkmei YMvmhPhvL1pu/T8fD5b/hDENZz3GL+XxUYwrhOeVR8sJGmCwYp69H1MFFwAcpsPtaP5999Tuuz8D cZtRBIaOeg4lMzezAw8iim2zaTdcHkTEP5UGFmC7ge9fpRrZJJTf41hWZAAvvwy4tcDw0k3x6Zlm DE5baGhK9iGryt48pXlWnGxl9aqANEnKowSLrZ/s/YB8UecW5zbOaxN3iMhPLaG7maXf4np2kIsi GX2okJC3r0/Qqr+g8ChrN6yzNwd7OYB9smBu1HavUPSG4Ngh5qZKBRdqgEUil5bc8SxkKDfhIcOE aPM/A5PPKYSwYgmRKaEr6F/e+KYb9WP6663KRjZ2NgME5ocAuu1VFMF10expV2BRQV9Axu/5ibg+ saPIci2i7FYlwyBtcr1ERUZFcLQTI/Be5dkpaC1uSwnrTYhA6YCKtfmNGM1WrpcvjAWiTVD6uEy8 whg3qy+yORphmHFnGlqS9Fw1ZHMKF4GGo3lvFvX6T6qkQKCl9qVJcE3EtUt+5tFZDWNU440qMnIU pOlnwCefWxuxi8zXG2nRiizuyux2gYScAwphMbpYH53qvOROTbHg4UXjIllcAnFIz1G1sSOExCZ5 c7i8WiTyN79kzZNp6rFSfjW6Vw5wSezNEhsWIci8siRP95AYb17RhbqVOLjqk8wIjGJY8VRTG1z5 qE74JViHMzXhGKNeLPp6YUVBvLw+g3gkP90TBNFYSCKweU+J3+qJnDdoMVLPIEL7LgCG0AbD9uzj RQCGas0UtYOmvflUnWknb3BuNdoweuOBwktxD7XlXm1xhUsw41TWTmK2zoDR0dJcwFmFaen+1zUG NUnnU5z3t/kg84JiAhjVt6Ezz9RnMs9/mBVBWK3gLnpB8IesEvPnRqnD07KsYwcWFwyxupf/K6Qo +MsV8fh1FGwpS2jALKdUFxnRshAtkrmQhjdwOBOsaPwi53kx1hdu1ao/FBdFfOtbbmdDPWLsqnGo sH8cYemgsI8jR7+6OYdyJlhxcbGsbniY2sMA/WLRXpbJzrD1smQxZ4MM6dCeeGEmKaVVY46q8ZDm VlITni0LJ4PBlDfW1lQdDYDkgdr4rLI16QUCHQmdKYwIfe8Of/7z0lJbtyyoC7QMikytLYcKsDj4 snugSFH2ky0XX5FopfFD5ubSwVeNpGza1PUQbI5lmodFTqQXvKc09SgOLqBdpmytNpHBJFxbwNc0 YgmtMtXsgf1g/GKQe3rSY2kOZflk2woHXYW1yswiinxzABYRuzUF2JuGUgpkrYC4Sox5yxxVpD/y SafzMXUbfZXoIMulgEQmUXQ6xyREqfGA2YIvQHtQrQMUyYND4lGVYFrttp/fieEHXA3Sebu8xJ3O jZMfL/JzihlrsFagGuL1KJvReri9bpi5dq5hANxtI/4a+BYVHaKshkXOUFlurfopFAjfDksjH2MR uLDY6WghX3pRuSZ7u7B2gvkOTItxWOeT//AdF08uw+Hq9dpOPe7rszv71c3gajxEXz4B9vmt5Rj8 qxgak+Xl7F+xcNMjooXHJgOrrWiUty+fqs+bMFwjKhltiFeFXCn4BWKe7A6qTbkhVf4IMFTo/Ach D3Bzsbs8NlXPGys3Nbvdx5tFDkwHt2upeBhF0qqb3N9tY353EaH04OGew3147R7w+pS0rfEbaY3s YAIKM0tfOGz701i0ozTXD5nlyy4McLotnvKHk0VGaVn8I4WlNivBuBGEl/B9BcPzHX+A+uVd8KPV lRV4AiHZMXM6Ei+7kQVNPC+zPGQjkfSiVo5SEnpvGSBDELpZRqqjFIoVsbCfXtUhTYsN/PlRl4B0 XZXdYOiJxCEW49sYnnGR8/sw60QCuZeqrhaxN4sFrqwsTfeQtsszCs+v9JCMqlPdBv8Sc9ArkD7x TN/A7FDYe4yfzOUAVEkHzjTZ0esIfAP7TypdFcQWklzZegNxaiGt5ytyx0fhOw9gSaKxZ0xRLBoB mx/Z/4phKcyZxUihk1cVhJMiEwC/TifmHI/2guqrYRWstWYHAfgavNxSgc7lN1oNgIQCK2h3ASiI GXUUjKVp6fauNz7n0E+d9ODl5KLHe2HFbfmIf5xxOSrf1Zly2Hw1uRwpc3nvPEIE7+p4ogbUJA3+ RDsV6K3p2ZYrKfM2MNgf2rTof6bHD1BK/6MCbjVmZ8FP/oZCfcLLZq9jLc7xVsmPMMk94zZJ806a VUQ38uXdr7B4ZkmvsGYCqaDk2An5sWTotAFAqL0VEp3TZQnR+JRAgLwwajuj1SU1e+GN1l+ADDg8 bC3HrCgDv3bYdIryFU0S+MR9axKALnF6J4Bc/eQmps34Qf6Fuvo25vAbcyFYN+PWDPu6xhuGcDdU 7w1O3ypU6O3ogbmOTYbFu9afGY9q2mc9m58GjMAj6GYswjydJP0g9QUqMyzPx5OI4XZdp+OwQIoL ZN7Pex5s/O9sgsaH2q5JS5kc8K9RAc8N7r2z7hT1N2651eoBtB98yGkIpzmfcmtdaok9Lh98pso6 wHSB01HwOE1WTKvGBh0gDN/4JphtpTDQfsXWlz9iAPfIoSAypB5LMVDgk33P5vXmaC6UtFFJjysp RPVJJj37FM4Dz0OGVRWxMPrxuleIXUushxd5LSEGBIz8NsTIqxkbpLEJyhEP6Qk4DIoevZF9SWP/ qT4uCtJl0EfkzzqYd2nPu/LXsS2Gh29pBJa2388Gx2PRahzMZQuUE9GThTkFg3U1FGUnSzDSqVLQ r4v10Yx1Qi4Q1xzMDg4DB9XIvvfw932VCtvmfCvZ9wMGWZMwqcLSKPbmFZyxc6PtXK8ZrIxDrp+P 91BRSjrwtLeTm1UizCQVx47IO7da/acMoexD3mG8ftuF7Y1D1Iv2ZvOOWOQvXG4JSKJoT/wQ72Wo LL6Uxj2vrhpIn30Kf/cStxwU3732Xv33BTTNKUeGz+nYnLZnePvMPXGniiHU7w2B90IKfNnXfngQ eT8Jh7XAUfq8kbdgnrxCzjLmGBYNIDBAolJMhIKX5kv0SOK+0CSfATkkT41iWFpbXkgLzUrC+XTZ vuvERYEFeXthZsJfEKGnQyF2P5ypn99cElf2c29RzBx+/rI0eUtrzpH1hxe7O6gjN/LDg/C/vRqE viPCNci9iRRZgIGpvtXUdpfV31Mhj8yVj+F87tv55YEReicbYHRXOT+QpT0VrLct6c3gbJ26xnmS aJaxL3zCX+4bQH76IDeQ8ekrw3rPQ8iJz6s8UowjQgkGAUo9r5RvSfTwCBzKbdaTO1ZzfuGa5rN0 Hhe3zHJEsW29vxuaEK1sYAWxxno8JySDc+wY/VUbwtOfoNIxcY+xPA7SVWylOWzQ318noQODhz74 a/Pg3eUxOGXEDPI40CSkddjWTmBTrbAV5vw+MgFhUTS9jABvBjrunqVf2cPSiC6RVgyFl8+rhB0D RUYpyC0HGMJQIn1I3i6ZtxXOdtrAv6bP4HmoL8jsE2AKCcQadq5Km4G7ocIt9NaaQ4lE23eNDas1 8CV25GHjxN1D6HQD+GljiVPZoi6DRi3x5Q7nnEDgYPtc9734B0OdZIL77nh8eJnC5J+BO/BpAbu0 ftxtqLUZwvCOuhkO3g6RCmu20YXdVmS3OzunXf9peud6LWNGVqWb8iwOa/mfusYNafMzL5J8USVj Z0PK4Xjn1nAZi3DupK2RjNSNnzxHdIMH2JRRPrW1207UdWqzrSTAW8Jn75mQ6oCSl3uGSOr7WZbk 4LnDz3d/M9Agg0jqgoGVsEpc7ihqwqDjriwJRkUOWjT3ETYcYEWI2LdfaIL0iOfPWLeHjIpAaJmg alBD1+sM5sZWYdch0hYzLXC4AN/g/S9+GBvjNbXt+E8XsLc9EjXaPPkbz3vLGEMs7pDfLT5cZ0zy EFH0jxUWNvVTrTD9uAJLdMV5tVExo+tccshQGSErOtWvmtAHiUuWXqFeZV8r2V6gAUuOj/bhjrQf LP50YbecXhQSKTbSYK9/HFwkga8daKocZW3dbVr0z+7Ku4vdsNhv0x8QygSDw4Mgw1sY2f4ArQlS 0DlPsVfZmw/bT006Lxm3SPtOFxwW49NjNJOsoGkCGpohIEWNVr+p61ZiYQA7UgcTxMq0RwJ7hKsV Zt1Ui19mej8m2mNhtlI4w/IqKg37wB65crdyIMdojea567GfFqTVoFt6hKf7dn/bpWIp6kFVJJMg GALAv5FbyOzult62C1Ri8epqUPaVzLwTKrqcqdIZBt037jxY3H/oz3vny4K7kKhxL/gtZy+vK/z7 xECcBVzHItTV4Jtjk3islsao6FiDJoHrHJr76+uk2XYDVAgHLLYvraWa4tiHrCvo7E7WFoDjTEFI 2VrzYHcQgQp7RIEdgILs1eNHEB6QMctbObAyJ/xxeoyy3Ng9MwV07WStISuYA75YITQuUgzKrhgs GvSyBzisbs209Z+gdnjI6WjycMuzwy4HR6rmV1jBW//H519dM/hbSNbw7jmnKAN4IHJMAtpS5K1c 9XAYAohcgWswQy7Cksh1x0uxeUGE/sUXsnJ43dSllswfmeT6lUoB7brkCOVBEcRT3xBHHuD+PCzD wqylqpCO6ON4fW4jCnc7NXY9Jw99EOlbNWO+pxZm0yBpkLDCQRsMezINjnvARML9+flzFIxbFFhp YtpgntXx6TIdISlRdy5TK9kyeeJM0Kdqy7BgKzYECd3BKFO5X55wb+ZL3+/vE8EbW350JW4g4Bp9 w/sAlqsmKmeztuBZZc+8xr1LsYDV73Cvk/Ovp/c3ANxG4yUjWQagfsNhlFH2Clwf4nUXw2xzZXQ2 iMN1DV4sHksA/f3FhnAlMeZYce24IBvvXM700ThflB3Ff5zLE5DbUD+oURKAGGYCY5QYvEC/gveI /td6J2UShqZkKhFgCLg7MmWKYURj5VPHrG1j5ceXbLLp+DmmgDMKTJqUMrrxQIpPuz0buxwSRDTq hTXFx1euYfxOvQZDEGWzi7zup/RaCo9iIluWnzuBqGcbiDWu4QSqVWBjbUoZe2A+jyiZtHWpQy9x w4LxNBud7pJbXevKVyoo2+lhaSv0GfrQLLxXhDhUeor+Ux9g/zbT6lZkyaKEsqRgcxD7XwEaNON3 kmujLEgFU1PRvfLU/tcp/rLlPPo3kFHJqPyCaIRGXvhS7APNyw3x652V+gMKghnTZnOLOTBSYHSU bECcJFPIZBZ0MqUFiESRiChAmybi20Kd6vYvc8esh606PPN6wlLJZCU8GvlDMODjYW/H8vPKTIr+ 8Q/Pha2GYBY8yMr8F5aMkHlA43pEw6I32FCqbI/QQJ2NZFl8h9hcihSCVLux3wRTZK44B5dNaAaK GtbcSMGcQdlaFUPvtInBh7xMurPmLE+8jBRCPvzBsNg5mHYFmq94WWs99IJ7BLspCjrZD8etbzYV tJ3hvS3e96hwJuwdeiGfgge5slxKX+LUAmnOPAhi2ESB0a7aU2ATfsmY74H5meyWxg8TFoB4SNmE XCNxvqwSy2uXewhk2umDHeyII8tUI/VO6jU8vwXPEvPh7wY5jOlGU5hn+dKjbduNCWcfdb2TOUzG LjdWCnBvyuvRgTnuMzp1Ndrq1lwiC3w8bqG3/08uxyNn+QGOks4CSd/aPSDqDTuPrc8D5eA+Jo2R QeXXqKulrciLyWcN+ryiijw/xK4DwgHRGLDMF4q7YP5asdKztRSM7b8WkuAwbBaGhYpkSCpvo9Hl Ex//EivAe9NkFfnQ8qTT/STPJ62USasyXl3TqLqSpVg5FsIKmIJw2yh8rVY8+XyiiuPXQWSmnVcU ZNHOSUezR4ipRbDcqNwRh1GnxxtTqjSrnL/ChjFOvnWvoPZt8ooER3ploCE9lQZ0qFOedcQp+lOR SDEDXoUdNF2wE58h1sEUliCYDNhXruucYOoiZBtjNFuyV+hJmj9STSQzBLVxXCRg4dzWnZgnEPQr s/oZK44jEcEWf0hklu1XE5QDdjR/RkyW73tjxO/hguo2V0lgM8i6T1nBex+l5kFhFeMmAgGYjX/D jb4PNMR9LKsG5kSdvX4pimlJ/DBrSOR1qfxYx7npHoKKp8KtGgfBaTYOGu8dghpm7KusnLuTmgbC pogVm42JEHMxuu3uLTKN28bGkgadJZcUIGaf2o9YSyg9nAGFHA/b6XxVbcHgcTSGbbxILykNoyzX 2M8gxMcp2Kqi+O+WR8hVhslgFS6PzS+iU6wUpf3iW+LLCXVcV4PAAK4Bzrc/M5vUlrK46vZA9zZb iiUJeQKvqzKSb3CoqH3es1H+KxUT5anpMdhpa2JpnoN1riKv55sKdKJFvCc+RnsGQZ3/+gGU2zC+ VlJstqKVTRZWyoT13W4OFaJ1KQAhicleSSltI8HgaFpDe5SAZKncjaqkA56ARVuwTxgespT2ckEB eQzvMYKuS8WrQrwxBsnaBx58BR/99anzPVshwb4sMhUHptAcMdJtqRLQ+zh/2saVMP+jV9ocbjSP LVcB0jGXc10hVrtT4N9NFYKQy+lZCqiATs94WZlE62uGQry5Xa2PSk90i4KEpVKdyTSlYFl1+zxu 1tNadHOC/T5HJt1ok48hfpQgrEoCsi6OccLaFBZGxa2IrJutU37yxcNx22T5IewWENTuPA85Ghf1 BmeGzz7Q6b9UuvBCcs3/LTWvkO0EmiT30j5MJU090NXWOLxHpAVHRKRR+R5WUYVN+zNQSRYsDvn5 5oi+O+WJ22InybZK/wliwgcJYeTTEepPfx3KlL+1o3XWxOxXwIJKleZlsUAfclA9VLi0+vuEvjYH i2hQV5lu0yz0GpszUIVrqpdGNi9+e6y7cnA7xA+Jj7bRE3lx/hgMzUlo6KdYQaFZnO/y5W3TSubX bUBMILvJf7a0cqTDm2HmZiTNs8lMI5MEVMvei4Y/zskwtO1SqZLAs3Lgj7OCHNixY49GIppcc/My iurCKorUPj6AbYhfWPafitvPuqyeDJZP9rnaK0QS1nR94jSXCLjWSHraGBujnYifpKYKkln7el04 S5G+c7L2Flvbi2+GMWEFsm40xemThksdvJt/N60zh3f4IpJd88sE0Oeb0FFi0sXUXQR11kODsQqn 6rOil4BvOBYj3EEurXdUOGGeiRZ+P0FcrS0sPMc5W3mz6uQ7XUewbJPZ4TRrhh3p1nB04AQEFwCR 0BdDcCMQRDE06CRMhwhbgCx2ZuN8Bi3jcWL/MWxNS0L6KyQ20TwgL9ALyLcz5HHuhmuUmBzilEKu OAsPsQS8CRhhe13BJFJnpsrEQPYMddk1CMORkIaCeljsplpF5s+R5qp9hyEXe9X9e0fRzqsyueZA C+fuGQzfsCWIFn0bvwOyHRCcLoIKqkm+f8puAcvhY0LSZBzPKMFA80KLGD1DK4wFCVYvHJLXNWzn j6FZ/PXJHbWKTc0J48JtQcftrQonlUyzvu1w0dTH1+eMsKPixUqgRwzQd/k5QOsugtAj4X9BefRT yP3UN+4xWp9Egm/vAlpnDbUhg2KNcwrZdhM9S3v2a7rshn+S03GlnZMYPzKuIp6crisrIW83YsQQ 3+S5n5EpWEPXPeij2accV6EYCPs3Xxu5jv+JlUfB/gfoOW7YpUg8V0XOt0auPs3bFU3FsHurorKs 1gENXkhfKXqZkiD0TJRhjyoAaAUYYoI8wtur3KiZYElESQpS3P1hH4rL+uHMAD9YI91Eqb6vz3/6 x8EGEzaGonwwYxysETH6UUHgAlV3E4O8CJdPJ2VcFXUpZUUOEg2DdHODkCvlmulTqsy1KLfX8WE0 zZjq1qeh0dkdf4v2v1gNExBfOa4NQSgGnC5FEcDzUwwZN7DEd6RkBXaUgbTf0o9IWGCR3NKKtNFO Xv0ecfm88TWcW+t7jT4Ds9d8DVLQsUQ0jz6zjsNjYtgoQpYJILviCGl/bGWMC7EJmrL/1lpHsiIV RQRX31FI4rCi/3Ia3Aiz5jGYMiJiQFHlzoh7HDun++JXftikU+WZFAMXddeevXssK2d54abXnvyk P0/eAtEMyPQrx79zxfzL8Zet7QQq/W6na8cHZBI/ABZ05FQsTmoLtxshsY/7klOZEnjI/vG5Cg9W q9ME93T1jXNQV3+7YgLh9aB8Fju5aB0XTKmyuyVtuhygKaKNpDj55/uxaQSwqPbWIGsv44vEO3tG XmS3DSnawFB6DLYwg8cYkM+Y9VkiLytpUaCCONYARx19+s3G60f7VRsdFxl+LPi04LN3v4wCjLs3 w6YCUeLQH2DlUfvxC9V6leveGR0lrKDsmIW1DAwOf3YMACdcnbBAA8UyeJhxbmatqZkDLTLfG/P1 dcxfvLrWsxH5eSSK6a5q7AhlQbmWUcJSpNBcMNaq+Q3kanh1FBvLhz1vVShhv4fICGB5iH/AecFZ L3Pt2XUOwkWmKWQhLcv1PxYLElVN4YwQhaxr9/Sz9Fi1zQRJtGxWyyushUod2i7dnx9P3F2GKL7E 65p7ylGYmsQ3tWXbd6Z3oNLVPwIbFfMX6Y1oOJ8fiWSVIAnrm1LW3x884YLLyZphR/zz9zwrhSCU BFseIORvsrS0L923v2/jYz716NzG/PrTry1Rz2LAV8iJ6mqET+kQRWOE9RdIkzA6gjl3trCxVPnd Z1CbIa/G6ncJuQ8BjPCCJNbF13sDxqDejm4J5d8UqvLYExpKDRxZUVg93Lfx3tYigU78Pj6aovjU j7n4mDQ8ebNrLrssjXGOnN+yw1GS+TYBbuW4H2fRvgAFuIcxVVs97Ehlbf0rjyEbM/HBbiRlv3+e d4P+Rsp5jiBzPCkJv226wF6r1rg1n4CcSZVhnySMVhD1Ygj8tdyTpnXmC5qfsmmEvRDtGRLrnEJW Vf+dBrVhCR0finHmrvNMuN+TYifp9XP3Vy0vy9f3vd7J1cfxnd/zqOmzhi3GhBhIfTb/YWJELQO1 we//M2EB0UtfKN1DEA3USHjd81U91OPgxzKI0xTmU5CJv0nevk4x+JAUomDHgNONo28mThgleqp+ EVRe5mD6t7Ql2yk/vfJ7z67R3NYAIcQzzOXMrnAGwBBQu21twQGSIyKTnccZ38grVnDj9//mqnog 1eVFLLRKMwg0I6t/4FGD6Qr6v0ylCxd5MckwXHr83XJ6/0WEdEQCZd9+IeyXKieMFYbYs0LV8AE+ DaN/0SWDgfdb2Q706XlAwfP0g+jskSKc97mqyMU8p3XsXuoVkMLrUoAhrx400ir2dqqiDS7YCKB9 2wQIkkYyJjyn0s+/f5Kv3OJyXwSohh4ZOF6WGglGowag3UkUvleXVcuc3DwrpWJpdedSrEC+j3yT VgKjVPs+O9dz99Dval5XaM4m2Lld22SBsUDaKS+YrWL66DSLO8DgVUAJJhA5wlluPYX9F/XEGju2 iW7iC4XPiDWFBF/ZLIRZXxi49aBHSMvrwvfClC/9mGRSJmsTA3DdQmXRX90Va0crRXrNbrmxaXA8 OuUYSHT47MKFj6P2UvU1YGkxdAVXt524ARhZLMFN1ishHjU/tY74pgkYFWKSwJfeimWWAHd3+WSI 2FGUFrpbdaDLpGOUP6t+xTYP0for01fRHqhXK3bMWxLcVkPZOFLX6QqlJEXIVHwHecpKO+Yxwjwf iiW7HzFnmSP1nJFWKw/FcbYX71y2s6tRtX1m50hX5UqXEbtSZQ5gSpMt8Tekds0fJ7dGdG24ZSwB s66SWa/xU/ZpF/0lOY62+jczdjsrMUPumPjLn5IgnIr940gFpbwxtu52X1QBw7PP1rprFrf8X1Am PfAaLF4APHU2tZUpN5Tb31Z64LgiGxO0R47yIbW72PMehL4Xk0zhS54Ny0PS/UHpFPeFqIYj/fvt DNiE9gOxigZmntHovpXnok5hwQWEBv8eYVgigCtdCE3HWozEPVx3nnRXcVcUQxDiq4uzAqILJugn EykE72lgpq3td3zgqH2heUUUm9Jr3Q8ihN1WMfAkYxnYjXUfcVoarRQCofzzd+0QXr7a2U8F3Jt8 +3fQ1xa4KOWd7HL++MAMtp31WcLOl7ZAuUHLu8hd1qAzsRu7jxYNSkpG1MoH03Tm1pVauwP8fbbS fUCBo3xiM68t4F3qlR3V3JbzDkVzEvqKkxF90rkfVPSAVvCv2TbAi3o/QrTEzR4hedn8fhyOzwLi haBriKuRNHrtdp5ZsTApLRDU1FEL1coAaYwP9mErm/s47V5Ava1ubJKBok5VIQxnGsOQ2rWbo/Wq EZGGLfDb2ZhyYYEOIxKtMLrY1E2UHTgsZPWkLAU8g/i2gzjGi7+cucEBsHZjg3Dkt4wRAkyT2u3D qM3JUf6fBsSUHp794T9H3lXUyyEzyyUGdzUsygcXFI9VKqNqng6yqeTd6UOKM3mwbKh2NYIjO3kl jIhSXIdM9ig4KLS1HKzNIXww6LUsswUuiKsXQTMwiPQwHnannRimLftLKvP1OY2W78i9x9UhuPk9 KcX+t2Vp/FKlcu86zV6c0xCsZAZP8+/HZA1PtwfnOdaFboeRFqadm5RVEJ/JkFuG++MDJCroxgzu rrxq7P0v4IhLu+Ps9cbk2vacKcvEq96DUi5ia3ytj7UI3lZGr8bQFV7AuRet81yvmPEnHpj6SKrN FIdqyAeXz/7VBMe/lf+afe/yy927Yj20wtf+4ygnVIb7v3qh8xsEZZjK0J+eQONwUEsCKq0CweKh YnHsLPZhr4qSOlOZjLVcdlSJ2A71xvFNPuL3ZB6GYHGMIrxXBngBnSO33fUeGQsrQwRCNAeQXH0E nASWE1jAufywy/0kHqN10lNFiIh1DLdNeVSbkq8ZaxfrqB0zUuuTbPZr3B2OZW02jwZU5a0MUMoz Bd4qs6yhMmz0cVRLNG6oLx/eX/5t8mHnrYeRbsfjzAzyc+yzwTUeryiVjt0JyJOhMKJ1oa1IZ4cP D5GcurdEnaRBtDvonbZz4Fw2EQ7Ni+P8kIB5y2Npz826RlHSOzDSizmEFlls582Mr6GNfAEt2SbR Zt7wmhZtu6DdF1/Lx/ore7HBiZMjl1jhWREAhqjLLwD2DxswZ4zOwso+cVkJaJmshIkZyhnoRivO WavEpbIoj9x0qSWqjiM0zyPPwO51MEugHewZfzRzL3b+XLlKS78E1a7GYZRPW/testwo+FA6In5z gzE0uf/78OzIXX5froEms9ObRpmMP3UGdAomSlxJKRQZt2BAH0ZjOghQ4YUogNoT5olWsaKf5zGJ NDlWDtPF+TpCVhN129XtBXZD7+SahrNfHWQhXyELV5uU4tbkvdz9stzqXPhkgJBZL+IXBVPbEP8/ hClfFzD07CsN+kf4h8nlRg4P53AUv8sZCW3s8tQLzQwqQc5dpYCSxaxHJSeU6WCZKOTRJ4zIy3eI vD3iegjHGls0gbhDoB6TUdeCMKLs+Qkqkf0wx9KbuuR0PHRabR4THLJ/rNSRdza1Q3le83fIZdhQ +YWYcHnjJZ/xtoor3MpmPgiAo84Rstwp0TYUsOzjVRwGyjUbcD079p2Qyfp1mWspn/+pyu0Iaie/ 2K4zqAmBUToqvHVd6NLIPgIg3TMVL3nm512zM6WTaEQQ6G2yr8wXxqyhlY2t0VjnRlUGhQsksp70 TVaPTPPneNdVtUp2IPQau1TKttHgind8mhLG2nQzzNT8hh74RHFxx/KDgUR694tXoac7nXrQ1oM3 6Lt9Nl9bs3Vn8cPp7qU/LvCbMCb8vxQXe/42/8wpvR+Tn12WM63CmmyHzHIbIShOhNbZlWw5zbwi FT+h+ftE7qPFNzh1Y0zEA1Z18JmwDsqcVIOfI4ww6Vn9wj2ExuzZBkBFZy8xoIS9LcWyMSsxHnQu WA8hc25AXPc/gBoQwM7OhqWaj3OM//DNpnhoh3pgnmq+n5eKI67uz4UySqEABqi6Ywd0kloqHpFf ou266enzNpCHsolYHxgaayhL4BPWp5s/qSaHv4edqB+5yF/7/RuMkZ1JL5Qj4NoyMfWdtO7aHnpn ZFESKtra1nu4E4VH4iFgwm9Q0IL2NeMsHjgWeb8cxU3CvrCgo4yQWBFACuHh+tkFI6v+Imhxfl5w a9rQlGvVEG59p3g97zORix4UIDZD7nwvoKs7nil7v4eLLyDlMZgvpV4FasL9kxLumuuQFodjFxIE kCCBxaMq/L2S1Z3B04iTbe2MP7ySwcsWCiW0l5tZZvRdWj2ExJboMELNztnXH1+7Z2C2Lxf3J0MT h7Prlb+odjA0DNfanzAeGap2GP1rYnw0y3U/R7y3sTNf3JgHA1zGAk4bODFxkHxVchfktgjxzOU4 BgYoVV1QdHYnMmmvjIelnHyildoZQxeFSUzvLQf0I8zHDAig6a2AB2ylG0B/TpkounnmMJjnJbnb N+vGWDb+DLFEB+hxILam4rYSXPfqqOWQHlrLjbFAMxF+ws9uTDuok2atYgF4gHSWzicYZqeugySF E7uUT5ngrtcJdlsSs6OCphVh44kdJCGPzmdgQSwYZWloc4P+Cajp2tswmCm2nhXhaPdPNKc5rBQ6 L3aEZHeJ4wLx9QeiW3KghRGXN21bpwGD8uLiNIvBg86HX4ZZRFJ4IIof/hCKdubsgSoPNxJWWvkc DwkRASeq8hKmIUkL6OOKTw1sM/Ije3n7V+0X2kNB4PTV3HWLXTKxS9TemsGhVo990rZsa/lvoYnP Jg14CFPJL986FAdI0Jm5S768QsoyohxBaNn3YjNWUi8TXDpK+Ge8DtYNJvjqtd7eVVJlVNJmn8xv qw0rGDdVZKzeSTGEpwGpYEL7myOD04iJJFh6jg5FhHia7hhFY0k1k3vyhZl/sX57HW3mFc+/CEwS zTsbgrDj8OoeP3647DaO2GeA54GLGcSQwbeX7pAtUoQahiTGPZPh1uCHbA3+1gAvG/qsVRTYeSyC 7GuCYnpYrQP9naDNRqEXfI1vhz4uaB1Cc93iG32NcF7ymRmnRP04kSlfwgpozepalQgbD1Vf4hjy Bdq1W6MSxb/VXaQ3+GkzuyZge+XWnKXy+LwV8KrSohGaOR92srXO9HLl0CuTlcEEfnp335ai2b9Z 1TFZgGPmsZ/J51855mswXSMVJwvWV+0UWYxYUoMcuiqrP4CiPMomnfGhOHkctrvWdVBa3E7mmmZy hLpnk3s1nr7KhN5ilVXHWzupfduX9ReSAqMRK04lCh6c1Cat+G0SYVtXwPV+aySU3OptDB2KkrrW vxCjFg7sFBtwvBBIec0pnVq+gf7BXhZABlcnr/VrYRQ7e+3DobUlFN3AcoUo25WVarADFLOttEFT HSEuWkwzktDPurzkGjkKm+wjufM3TOC9hnK1AIimuxQWs0GAMhV59ud9aPLSOnXioOHObgreVxxI CEzUahTERN6MQo8vRbvX7QNyH8pyUZbcyZ9jSpfVdwvDNJR2YBQx2chmjMVdl90k4uitXiQDoaEO KCu1HYrrhy2WszQlDCK9RB9VSI3H/dIjo7OfJ/hYuNoBi81S+ZFakQn681kvxVFxZ7sUhhGymXOt elyg2filfg7zBxebyw4sXFxHy5XAZ5W7saGRrS0s1phbasXwN+rNiJahVs8wuKTzRW86nWixswUc MvVRToN4dwFdIr9E0MhSNnWtAC/DI9sEHJj2sXLzedg6WiFKIk8/xHrQUxAoOZ/6Tx3ttjcXCC4t 5UKqcTGXK+yru6xFROUTNm/5+cUW63aHPXicg+Y3B+cEFrTbMgd8s/BfsZjeYeXm0eiGtfNlPRxF 8QTtP6EHqtCHrajPxOrMfU+lWtyDGqnp1mLtOXl8bxYLlHrSyUswYBrRwyDfCuuMCY/1Tsesi4rh SU+vVXKw0u7gOJT7fGCSNT3WnFEPLNDVApKjGHgXuhphXGycn16Oeh+SRwBses6gKxGRmowPtFBT KcYWwTCPDBApfldG4Q++lVDfB77LJF4gWRRr8k7adACRvVAwBLN8/TNUbgcBreF4b2mdlN1oPeew TsJlWLPIeiNXluTrQHo16iKw1w5/2tv/9AFmYATVbFiUMfCxPj9vABMKm1wr3u1BGkMJ1fenSL9e MMV+ko0pMNYZvvMi8FewvMai/miVTd2YD2Y8kyJwZKQ6iIfGQmLtE5G+tchcTvHFdGwOFReXuq/1 yte865N3Q9cBQbhGFIpYp+Sdfqe58fvvw6TMdL1kkOBbRS43+SrFDXpADekgBUROVrA/Qx+mU29x x60EVipSn+cuZO99cbEt4/L5MmTdLUrf4M0olmZj2U2pNzQG+9H4PF7sja+SzJ+swXL0uyuiy/9Z kMRxg+YZGEuPLOl+ROGxjE55xuGcbrZ1YvJ1Oc85y4cEKg/WTrEb7yiKOxD2HoqhtEmkXRIBlKIL sbA8if1jmR+sUvvPFcM+S7aJa3MspkU93/ptkS7o5rIPZHwuBrg4sxpMo6uJqOrmJM6vSVmr2cqT kajwU1PiDflQUifPMw4AdBxBjO1V9/pih0azoAsJlZMNzBVb4iSvXgRXKjvbEG7Z4xEB4NoF9X1C xzBarZvPFu5XCdRj7kea4oBW2j21jxHvPe8Xl/3XnYUnMPzH+/UKCh1RjK4IqcrhJOutgF9JWRbt I8b4ulZhI3lDXrXI+tt+gDhct1oGaFdqDmqR2rpPVPBGkjahAHAnwktENeIYTFpcjGPUWoayByFo jaVr0IuLEsPQ0V3yxDLA+gQoNrZSrL8a9sMpb8wU2cqj6PoiC0VmVY1SFrXy8hiifxwPcBfqe9QA T7iRWh3lJLXE0/k8uWTHLj3AsZ1USH7YvkJpryUzKTDIbICcLrzrtpOWNIL19p2YbQMIdXBCubqv OLV3d8BG/2NecZc8Vpy//FmibXuG/ADE7vR8COSXIc7IJlWXkj+n2Ygl5n8kD0pMAFk14+Kmhz5v isxVhgF39sngVMgkBZhm97ltiFP435HX1QjKmIAuHsk/hbcql4ekzULdi8m13IguWrZCeesAo85o 88wJBGYj3uYoWBOMeT3SuWV2i1SlAgTYA7hUhCyGfxtmFdywyCJEB5C6rhkHPzneIiKxRpXqAH1b Fcm0zVMgIsXvEzTwlSwicUvCCtu3uTmnHg9//sayHcd+4ymOfy7/7u90h6bGH9Ea7qjHZQoZHp8h PeKMo4fk6bNrGWF32zwAtk/qNQgjk0VFVWkzDvTKRz1J/Ivrjnxb8L9Mf0Ae4wiqIt0Lj9Js0vgT g2hdmF5g44rkS0bnONiQtPkUucP8Jz7/D5yqwT++Jm7gKzSenVTR3bTVFCpXyqD1OWvsy4Ks3aCX ajNn0uORG8KN/ocj2lo2E2ZMvD+z+XYk+qD1PYdE5Bt2wny3txO0IHdKoaG7vkpU3rKRYl7Pg4Lj xwG2qzsQ2FDYB1QI38/spVDr5Jxf6Ck+BIsNpYFe1t4vrkSAeazRBKL7OJD2KW8EveLZKZ6uCD8D XMyEyFLkRcAc6pWRJp+w//bh/pgfSeM3FJ9jZ9jHEzqDj6p7q+XxrsX2rcwwuhKV3g1Bg8jv5bBH gTC70cW3eWVGk+NAOvQirX8i7l8TlrF/fnggucsiLJlTQ6Gn9sBvmbuMO8Gctfv9hy8Zqz3DQkth db3NgPOIr9hB6SFDgkqGcXStZsOBRugOblJjN/OgTFiFulm83qrBzF5hIEmtmM5bZ5wTSu/PjSoC xXeHzF6Cns34EZkD3e0gAqKDqGco3UkezQQVzAgfqFK1vZdGtRWqCNP5ryxabUk5RWaiPsre7k68 cDzQPU+gUCPLgmnFkOWdGWVasOeXFxH6imZw6MXNuy3xXaZlPLITrT1O86CtJ8U+fJQi5KxQgaj+ vJLoqwc3768qFZAeO772+bIZP7Arby53Gp7f0OELCwry5m4+YNAv5uQ9T6ILYEkPfV/CAn5XWL0j A8CxXFQTX34l0gR3MRlo3E2Bv2I86Vs2H92RSMSC19xiflENzT732amo3aRf/MqltAM8MNPrdGlq F/ZMOqv6K1Qejplc5ROmrq+bP/q46S7W2SSBoFwc9fZtzbbm1Nztf25fnQUIO5xSKZrJhW6KiJL0 RcyvzHR32JIMI9ROnCnv3r+4pZkqfTmsB5aq16KNLO5e38kQwcaegJ5903jNHfnuTcvQ4Y0r5hcI n3358XND+27DiSKGCZ0ZX+Wc/MSt3+LqZmLGo24qPNrxuWzuVxz4wrL0D8jRPp4EvJuof+TCaSvb 79WaodWFxZqnPS3Czlppp+kYF+0AbRRDTJplNZW9hMV3KuC3JhOdpTfkfDSH3HE3OGzjXGHd7BiT Rp07OyerJB0SYFfilv8f9SaBBf46iDi0WkYuH+0z0Q6UfFKtJt7p6slh7N8i8I/lha58y1Y9vQtb 2e+QJlcT053hVHVRSwbFVrPh+j4JbFORyVSIdDR2QlonVZM7fP8QmQ94H265iMBX6WgiYksEzCkS jAUPsTtFim5j+shjtB5Nk6hX9eB49gOpCLae5E+Xq4BIDfNKbtOj4zsZuoRkKBf+oDLSYO1yO1pA xcM3QXVDbBgkp6P8pqgZz6V4MuCMWgiCVQK+UWdQpoWvgSHkK4qG9MTD9+E2RnsGKm6puJpAf8aA oqE+HKZpWPCFBWK+pvLsXLPUYWz9Tdwl8sMq88/jPMNqfQ6SADiaoct5gnMDWmJwVLPPY5DU01J3 8gEVN/6y4ytCB4nHs/yT7smRVVLS78gYzS0U2KsobMNmTBYECruqhcOAko1YxHo2fW+vjUuiFm0R h6mjiBt7KqzAawx+lW5M9l6uay1lN7EUFTeFXdoSV5VAaE0gcZpuk7MyKh+lRzranjOsoJiJ1bL8 qLz5O9d3ricfqOULsz3wEdIAk6H33nxSzPhK3s8XuU+xu8WYxT6stTK5wLinGr2YIFX7djvZhvjX yMEAdxUAQz8eaToGg2ks6SXwScV9cMn1MhsM4mcU5aSJxTNr4Sr9Z+yJgn90ELAbmxsKqsv3bgXt txzClW2xQIYCtVesHfUZzZIRJDBS1WnxGy/N2KGKjC5u1oE1F6BRuPzvu+atSUWMqKVTtNQKjP2U EKARUxS8tLwnHY7leIhSrqUYJ4xDp9h3FTBo8twPpIlPvJ05E/TLYSY7cdJ1sm27j1CNG3KoSzVT F5DuK7EYUMOHSkdpnhkdX9vsFu2XzS076dBv7c/DNJnjxpH9pUtgAxSmTP/nxovPhuvgI5dOJ7zq Y8x75vSxDvX0cJLiQBKShIF7cNRb37vMYykBpLfvY2Ye2cqMuTP1XW3onZctJQf7ju3J8I4rfd61 fxMSvkazdEh06zJl+P7VAqEed1R8/v9TQ+ojUryIgIKcw43xcHusfiNRuekUzj8o44YcaV+gUxoV 55bCaGgzOCH2LiK0AQCPHBIjYgH8M+6c3bFYrnp8QK2EzrPvikHiHBJtnWVU4uklD5ORAY5uWhIs 6mo/vl+YIm6cB7+Vcxq+ZNWgRxuXSk78cHz939iJQqhNmIKkOAQjNleMZcXcXSqN7JTUposLmG9Z lQq/g2Kr635wd81Bhwr6AxiU2etnw3wFwagEODCRej7vVzsTDS63U1/BO2Pj0Z1zzy5GBB14k/U9 GbIFezPMEH4u7utN1hZvPZc4OBUe/QellP4xfi7xYcVr37yWhw3x/o7XRDa6Q544x/8f0dFDujvs bbtxjWFNxdlmpsU8Hfr2pqlENO0Ub1wwNmRDT737E4EXeQjll3+tyxauAGd/xprJA4QKbWvLTtwr dBLbjt0+Dz4/D4JiFfeS0sasCFixggKwFs0t+Kt+vA4/uObyK3L7/FIK8v8LQ04pdiL22vjbRq6v 8ld/q5qmO8KCy/MVTt5I4LKlS8gGStgHQmUwnyvA+9dyGLXHw6BgPavm5YyDeiDJ8M4FiDOKv5lN bCYFX/OGTww+zj6W2s2xuHfu87at/NeDUh30ukhpVqqnj9sYvW7d61On+9nPv2ndXSkFFVZ0/aDi SAdB7n75KBBYuhyzdFkeAzOYvBThNp3Ah8NmLv+0XMwH3rb3EpKTido06pWaayyRxaeACHWFALs1 y76rv/AHB5Fz/wMdRLiZmYJ11aFdE8yHYoxB20ieyql59gXgVthHD9LaNSSnLIj0vDZ2veory1A4 LL9x0KMmHfmOjGyCTJS3wqdW01uwNw09V2+0VBFruKCVPET149iSPccdjwSioZiWOMgEa4UNo7sf P3RGxVUzzE/IJOadtkM8sKUl/ZXbsUuXf+CoejPWkGOYUJyNckA+2MwXfZJH6HlvxoBTnnHuZ1Lu 5G4hAWzWeluSa1Fgg8hpKZhBh9zUQ4bRWf1NnKIFGTzlrwThiI5LaLAtxNt3FksYjw0W+93dy5Fr xJ/bd0OpWeQBdl6/WmXeSjZhUxTYhxHBOWaSF3LOjfRfHNRbb7fR7/hE833D7wZn4XZoNlVlYUyQ vAY1K+zRL6TnZrax/Ol9raGGozPCFd/CoxqSavGxsunL4T8lHV+9e8bO5jYMfRR9MeKYsiKFS35e K+C4HygMtyg4C55FVx6qE0qsEgVs4NXASsBtd3lsgNdqu7YshVHjPNEswFdor3RKmzFLojdBG+yN DHF0Gi1owYd2XNMbppmChnkKL8gea5ErKAxy6LnCQLPhO7gcSo8YRuSzlPbospWpYbcvK7/jBpon VHhSeEpwieUUrDgL7vW/3XSEG5t9rvg+wyCuT8uX/iI9Jg0jqLeYNMtTnMWXlB6nkHgGmsLh4e+n 3Nj5bM2B36vlkpE54lr0jLJfMz1cIUHgxppX0vWOVTZT73CNLccX1q75iu+ZeRQHt02MZHEl4icd lhJ5UgpHUo8TShm1sRMJkZ3dC//tJq7U/8GVLYnae3WwollaX5rHUI6E04bMOIjWwSm/qrWygWVH A2IPjOD4MNfmSYeIey0MQ4+FbXtMXKo67YyJRDiZA8DuE1jSDuFXztYGe2CApDdK/rZI9PhWHNX0 6TgZeXIN4ycO7LQI1C/rGi+JGpG1zOBwMi5pB/JJAqxR2+i2LOtUhHswUwcXTRx7+9yudYZ86136 2cAUOSH6nL/wCcAZmMsAJLt1D62DvKEvkV/f5VEELO7bl+hlmcqae19wYXRzS087lTtbtJREF7kX JC0CR61nRo9xaktnPLrEat6xm4CE5dC/gniIfvpzZKAtetaSlG44U8tvpufZDafHvI+SuQmWDpey IflD9dxpq1/DKOPUT1dlZKLEUX2US7JZNk1YQiVLjM3fQ94ZgvC79Vv1oluEVkKjcIAUA5Z6Rnav OHZl4TcaqlcoBawuimrfFSwqE8Jmd1Uf536MlqXPgbBIoWsAomP1lxF5nYmTa0+AIPqBfw632ekb Xmnw7LeuwsYGQ+wd8WBZIHFPA9P1qqa7IAZZnfXnuKYXoNorRHB4V8Wr+4ltEjUckqKmrd+iELuX FUvt4L1XnHhyfbeIUej22ySI9avY+AsXPzhqagvQDcMkTR4o8Umc0A8xcXkx17OLreq1pG3t1rWd rjbfu4iuSi/ZF+Wtl4nyuJcUCAGchwErl+XpF2g/9gu9WNgNLhHn6iFwACeRarusV1OM2hs0Hoog S/V9z8Qvt/YM5aPv4frcfEYNA9XoIoGsOcP1ORgg3bfqouaPLsoEnV7NtODZiwhhLKXFpNW0e1FZ 31JBujYMq6t2Syyv3smDZ7YgO3z2hm5+9rCtaXBUdH6P/rhlQcoqbZQknh7XXbehcHQc9LVmwQDj iGzvcVONG2qU+pxjwqYYvHdNVOM27WnfgWmmoXttuRaraVYpEaJGI5iketUAkOISnKLXv0WOfUwE e7CBuNWjsfofC3oFCVLSBhXONq8lhuSVBrDFu++2d7pNWj2F00XnFrwO4zKP4EkB5rNkW5SV7vO3 FMY1M/niS56CFcmWbGovObn1xEXAJ0gVnld4HOhvOz2mKZpe6z3z9eUwaUYFVzZEWCWc6CWmKiMr aLrqa0cbYt7Kn+iZvO8O9zM9h1YF+kzw0hTSWbTxEJ+Cqq4aW93Xe34I6ai2fhqAGVonWiDtm2WR ExR0+uK14HrcAGRW62qfwiHkRavFW5B0I9RYsGk9R6vI2gthtJy7DF0r0f8YQbeORMIIGmDfz0gk C/h9lvKLLfNgFnw4PhFma8mrAxyjK27wJ/HoBmwN7kYM5JRNHeaxeGEO7lDxzCWlGmlAom8hEXBk nzg1/3wv/W4ThIMxoXHpITJ7grzsH/CoEhYZ8RXSLSEZxVx8Rb8EK3D7bXtRq4S7IgeKkL8vTgTk pmJeeaIjiFqXoDLzl62XMcD9P9HW8XHkca9riHkHPjonTMqb/G5B3mPoXuF0+jpzegwvRo1sJUxe NPJ28zLo1k+8CxYVhL/WauQ3iBWVCSFmnxi1T1O1K0aZ50sSGm7yLDUlO366BUKNfeJBGB4ab/WV QtIcJVLnPIYwjppFTwMX26K1DuahKonKj0dqFO9WNS8TmZHeOaILTqYRe33Tag4pkGVZuAlt0cc2 PpvfkNT1YZ+jTd4Ye7l27BuO5Y9QmFaBufFKmZ+LE5A4z0iDvNNJEakYKyxiqFmXdW99eY9ZXnjS kEiSEOJ1uFC1URFnvdQOcIKH65a6uefELW0FLMsH92/HI/Vo0QBTVwDrilKlwNcz6DwHBxH92uNd d+LBS7F37kP4QUPKXprAIhtcONcN5Ls42++lbzQGQrIpd8iY+G9YANE65lfYxETCmO53XOD77iw7 iXZJN3ufOdXR5VDfa78+mEtaa6O3i6OYRGy2zWhCHdY5rag/Nmik7QQI0uRaXr+g4PMMXrMD/2aK N/EP9g7zkzTvasHkgubTvuA7maiZp7KhqKEd1MXwnW2vLwfm3FPpye+w8jdZtC/eUBLwydhp3Zv4 O+WNOtaFZ79YIE+FvfiKvZDl6v2+J+rQO3LAac/cmLpN2niogm8Khfq8seTuDL4ozTosAqUaUqga RYElEfYTKvnFeYhuNbcXu0RbO/itmEAj6lolYQv+XPgMCweL9kE2aFrxSuWyMwSeYfcmSeK6nBmc pRB/ZFpwiluNA5axZRuxNE96Mh7UJalSaU+fuuLrDqKrSXCyuSapqM3z5Lg1GS+BDSEYewjc/kH6 lGnlFr5X3GrRjbqYSswXQUZsVEuLye3s1wGjiEcaBBK/wZ9QegqTAESIR0dCIAnCdGzZXdkg0FwY T4V0GQZ+xCj5LhRyGFxFhiEOm0uj0vQqJ0QvEyZBBOUP6N3qEoaA/j+15oPWZ8HOLJ+cIEcmTdlL D+WOQApQCq5XqJ0uQ2sV/zc/NCbLs380fpG0KaMYVyjUQK2uu5L12Thc0433m5KXBLJL2oFLspan f0e6O3Vkn9gw/jFSo25XXmwU8qjhXggbY/9PYJ/NWLegYDK+VKVpubEBULvDjQqMtnLr4RyH7DOO 7Z6HuduXeouLepngvLpyB5EwHsLDZNMLMdHYTUjh/+/Lw1Q2pwYPwRavNyTE2SyKYorM9WHLt+h+ yiH7fe2z7Lm9SNMzvcBcD2B2IFAWvl8Ei2KVE1qEGyvAGJ5VrVngjKY49peixvQ//ZM92kjoTDhm kruVcEyZTqR/Z/SAP6hgKZy8UQPfgy781SF9/HnRl13MdXo6v0pzT4vz4VBCGqPw28AcwZzBAVKU FSNLBpFiRlb2L86GsdF3C3GFDZ4W+Z2H74oRVopnRFPit4ZjgIO97fK8kU7xay/FKguAqIzDn3Lb z4/srYg0U0mphyQGNi6gKU+qmNJaJWc9gEGGRcpnvqy0/KfAjMD5lRQqME/cnMjds29RuZfTF6IV 8YsqDAIk5IM/Xm2anS0qvJShrrNvxUqFyiiOB8LF1qqB46L4p/E/DjzX74rbKcr/5gi8S8FuQXvm jGK+X0pj4b9NBBBKKlaEkK0zROkenizLne4WarSnWsLb1533Dr9yzvUiA55M2FNgBJbGaMvqLWvL I5IYUrhSVy2BJNMbXCArKdWMRXtqc2c/XEIw4UV2UPUpmqQyVYjnMkL1RLE1EF5grDpeS0Y4OsmF P7PklQBb4IsDwnIW0minG7TngyaAsGF2JPakvFxXVSo8fUCn9bpCq6IFvumAkq3mg4uEAYbY+usO YtNQYHWcrz7bwekSeROZILGzSOBRBbeti52TVwV1bDJekpu7iJ6jwTveiRW3KtobbACc1tlW/kfU 3eaoLm/VmC2qoh1EFoiFR2TWI4Q9FENmFmP/15RLh56oauBEAjJGCFs1EV0eSLEKKVkjev58MOmn wwbustFOVqI99qCVT1P/8bPSXDzIse+GGkxOTZZobTxlkpG6M5jJuswkluPj9lj498G9qU45f21d IbHNHj8I3/H+hAwN3tNq9T9NvlAVA5CkXmvzOrmwP6xSxtbo5IGdNccyl4RBGktsr1V+5bnYYg0c XKoTBa8rmhUyENg0hgVZfSK1/jQkLx3aOpk5bxSyxnAp+M0B8n39+zOt+aCwM9uTiqWZv4Ps0Qik enWcumrPqbDAOx1qqRFw3M8yzstrnqWSOH/xagni6aCFAPnQloIevCEtbGAt1wq+FHz3bjB2yQXR 9YoTM0ZjvUxXXmZuZzxjKqeBoYSW24IL/2r8iBSAGYtD8/DBCQU+/r27RRa/ht27+zHM7xQMb7zb c2g7lolMMGyel3o8Kk11ufK1P97tQzlfFDldKMXlCMGhsaC2uHxPAx3/o72TStcWpAoqC1s0LVl1 IiuBtfEHSrjTaUVnruFDFXEgU2PFkRys29onr2KuNWwc+w3o/68pMQaU+UD+R1D+LT1BhWOzowTg goVQbfdQpFaouKEKT5EyW2NvSYsUqvTJRX0SkqX8EAPQHmQ4RQGIEBTzeiPz9fUg7+YIScQCc0pK u/8nB7ogP4sTRK1qb9mv+fi8Nc4Le3Mv8mY/pH+AaOu5+Wz068jhAxBF4GGf+EJnpfMsBFb7srLM R1FSQzFKAM70Hwshah9l6RK5YQ4ySCjoEAwoNMZB53/N+C0srk9QhU7FXR0pak01Q+UBULIE80CR Igih3TT0Cigi65IgPrbE5J9IimeC5LjoNkPzjsxVET4CYTe9sOmnn5BYvYadmFbMO5s2qQlBVkla 4DNp0HINncwMW/QxPpoVnyl1XeV8foMh2HTQUDaVt/szLAndTLERQ6t9qaUtpRanFsbcZrugRjNv cZ//uV50582/nvmcTK0dYHIdVKWccwerrSVKqVYL6FygB6RGtFG+JNiGxxKK32TUcPXOiODDpRVR PCTgUWFGJcaKiukMhLNcyyvcI6U1AX/kwfLhBLN+vu0/KkqkzxX1KJv/TDEW4ftCDvmsABb6jgn+ 2Z6vmVy5ZBGS1bWDjyvjIgJXcr+plBG3E3kHhiUaPhLKMKZ7RLZpv/Ece612UaSuxif77r3xkh0A KeJznfPbChD6RGU/kL3NTg5nSMykjdPTS/qfzWX91+5x6nBZ9XMca0kCTwmdhEryRoCRKeRT3MoV RQKvAs+cO0k084Nzf80FYFZa6KKYapcuCqdb0ktNSByu85tYd75YPMYir/z2Va9ZKZhhFY4w5fWO la+fz+42/vrvzkc3vYar+VGZKlQWESc9BfgBSfL4Bh/B1UWHncs1iVoXEEu4ps/+IAdC5+7qMNLX E87S8TunWr/788dtA5Gf1hhVxLRcuhw5fL+YtMkGBmbdjfjlgZ85cANIy7Z6hzLU42gtwtt/vSB4 rda6B7EXuVZrelHkDcSsGmXi0TP5AK0AfTCm8j20H8qwdhe5gg4kXlqaeVylWQOv7mmRkDpu4HSp YLMDxc28lE8GaJifi0noQO/YVvvIpOQ8FzrTMRmiWfFbw0EdF0ckKlx6SyqrShv32XZ7BRv7950c 2s9izfO9eUdcKOnUD2BzYGozgi5q/BMepPERQnb13eQ/7ZsKhkjVAcTcw09QWMqps1UevyaOW37Q rlu3e6+4DDJvqdZjDHp+mbwnWdbOPdZSnBvPE6apMAKzgVXd4D1BlGUN68g5RIWcbr5p92E3TfMx wdiW5HuoDGSt/Jk/ic4/QuHrxjA8CJEvg8o+0bq3IKBQrqPJC1AipQhiDITxc3em3hr1O+lkHK7V 0PkTcadoWa9t4dNjoJavwzRd9QxJ49kIaQvzuaK46V5Tvc0HQmBxoUQxTAqSykR80eMzE+OddpAH wtn0qxdAugseUNq3KaZ3t7DVoP9s6VLngU3cqE7aRIgOWkRuHxEizvCVyc4DlEkUimbPXcehz2wV ngNzuEc3pop+PF7X3pIw++LyHjo/bzJLeZYFYFS8jurrmMCBwLH+c+7J5yJPK4JjanZ8GQGzNBzo dcMJmaOIastM1jD7uTfE6MRYzplUh/yMiDVUdfQB2zgpbgF5PuIpRiUxJ8smBzG1XU7kkYncyDX4 8uVpWlhqlCt30IdxHM8T5Uaz5hzY+3JKiZXhs0HWgQTU3ovJiwhGu+fJU0fAy2WI6kX3VXy9BIUa Ab3dbqZphsj8N455E8RMKY6vEanvaimzB7P5KKQwlOfPnolHeSiZRrJrYPibEhNDSlUml+V1lpx8 ecATEKFejxMkumzIBjE7Q6IY0vjf/VhZKLyGkcBkrHc++E/Em9UIyGesSO5PpccEm3BOzFEAtXwO 2lB2OCpc9ajhebNULv8uUM5LfL/jtolxwXzMhMiv+AqfxF2q8lRsf1gWnJspLJYoIlOhhqQ0Ucl8 LV90KHKiU4VaQeUZRtDzAWcqMFtb8nP92nhRpMUdXH9qoG5mO1r1DJWbuqsagDarMt/j+IsTBBbS zqDojrSu1Qk3NK68hnLl6SULrLkpTAOVjOkAkMZvvLgUu7GKxg0o1nh3+K/F027xyHUyR60xPCDD mH9OSPCyXxvpvJfv6NSNx+zEuocdEWCq++P3KAwS3jsWuOzmO+qPKumpNYOpGEVD136rQcg5W06w kipClS4Qsjjg/foORfgHi5fWZ1WM59j1doFt/eMoa99ec5P8RGfx10r8J7n78j2VKXcnta5TM52m 7XZlUwA/Y06QUo5cwsvII3oF+rzc9B9XOb40pGwRjkP3J9bwbNXjHvdaFsYYP/3rUD1uOCKGsIgs hxFP5UALR2miW3qQmJzignCeh00vSnA2foSogH1bVt+dUIavJbjAEnkB75ifCKEnWITCoSl6j2rm Oe+DRHUKT0VALs5Lwc3CPNX9m1W0oM232eKBvTi7mUiS2PK3C2NDFLW/Rho+ibJY7Z9tbHwpwcVW deApaS7ah5T2UkY/k0ToNZBU/dL52kalaTY4sRRE3Rw2vJk42jhLGqmaBht3FWg5qBCThSFIIXCI zMa3ekXyyApFp0WRqaCFg4SWrcm5ijS0Gk9GJvFg51muQ6Cm7i7wLLpkN8bFktZQSL8PNm4P8yrX X3xBGvCYlSWRr5Bt3xwiAfCduAXyX2ppACGArN20d1s4gwRZRmcuTR9g2D9jz4nJFAbTs4M85T4A qcDeD5XXuBNOnc68xipXVDtw4ENwBWKl96U6OhsjJ1F4xrl7Q4HhatIRrwzjP1Azxg6v68J5lA7s eDCkgO/rAoqpjoOdg/liAQK97nCLK1TC0guAQ9TnVSowG0GjT2nVzIgYvYmMUPR131DpIm7i5hQx 21WM2DSyoqq9k8i46KorWaXp4uAO1PcslwYZwOZmCHX9dvKDTb3NsdllrffpoP7heScv2lZa0uVK F4IQ6jyiho6bz4JiDQOTrE++C5HDHHHkDX3YX03xwnomBM/D7Y9Yeaepj8Xqc1dIFjmTBk49ynBt BuzNsHkkxbBWF+mBcEgNN7WYfllgC5KtMP3aHidKBd6P8xHNAD8q92nrjQ/vcoJksMea3OfCKPFJ mPa/kXF80NFMlKBW8TyiCE0UUWfOALxGcrV2e6DtLMqMCL/7PdOAtPZl6txx52hiZEMsqvZnelKc VrsXpNdj4nXBa5+YuHVqZTuuvMX2cJ14egjwUe06UAoxby6xcrFLWD9uPIg405Ws2ykV7BurbUuK Yd/lxfRcJPrrO0mQrosyUtXf4zPY1bU3KnoQmj5nXCfyp2lehBbFJnsDoVPGiNhXVZrG7ZlrIa0r jEZdssFV+qROU+qAaDRbawqXlJcKmiVFpCsANFXqXmqAXRt21cXwxKZziwx+F+kWz2T1+u7RmEZW L9Lx1NRD1G9AhrK/L3320v6lAkd8qRHNEnjVBzg9LM2qhzmYbrG1o/MQkv00/1UdyOpfsSlvyaft gdvRZBorGHe84bPSNBMr4maPtj28YRIZvy7RZfy7JcGMMYc6k8Kwp73ViAal5hc8lbPG+9MEI7Ck YfnyS1hZU8mIC4dX0nMC+tjowI+osD/mA+0rBsrZ04erdDA7si9F2u0yZZ2fXp3sZBHMfc+z6jOa Gzl3IUHBmcSUDSScxmIZ/6v9mgB5WKVbjifEJ0e517niDmwcHHzGlnd4s7meVtzZfiNqsmeGqmy/ tZmcHA/T/bOrzwTkylh/lOKd/3W66WDx1P9KCZJAEOjZP4KxwgsWjPQw0q20oKrtzITVkOxB/i4c 20J1NR/PtQ3vnp6lyRogRGp1AItqgdgvJetlfWoXT+owUaTxuw8x/RcRAhDPayDpxXU2rLHf8bSn BYmRdlHO7OH3ErUE4Wx3XzbJAuHBLRTIGjkoRsLl2nBwOz0KfpIN4XFrr7TvlNj9No9icFRLUQTB 6fbYDgwpzVE/f8IDfdVWBJpgAbUQ4Uq3WJCm0mV7BLLIGymtNKVFg0PHxyHgS0EUTBeDR7LdyD+C qPZRcEWoWNkThvdLfvjwyT82/e89oIuU7V7QELPTqYsTdggMaaKGTxRm1gPx7vLoQdlZnrpdcTQX ZCURv6IJAstHVKeg3yIZ1wpkzikV9zlB6iUa7nC8LyjzPeCUo82Bg+Kd+vQQuWjJZB48EauxslgI t0lemz/NXQ8scfp/7n/pb0ygnr4Zs5+R63WUBzPE0EdRGx2uhkcCBxUK67DQIrEu+nx2lV1GveMR TwZ2i036lOP2ckFYs0/scQg4f0QkFRDVNMh2j1moxkYuGrXA0pddrAHYCasK3hoDjLp3ey1MWGG9 PEYbuY1QDTtwjyUMrFddcom2act+tljd4P2ixxuYSPHgH0RdXiBIoGsVkPIpvvf4Iqz8yy8T9Tct pmMLXNlnYGP1PB/If6RjJimz7NS9w5gAXPglZE2JPCtY7cvrMBQrY2imqqb+vQSu8RPQt/oDR+ps dQ5yrvE0zVe8a3FeY0JA55tt0xUZEzHBoHk7Z+Dv53Zp6edZkW7efiYTI+8LQ7YmOXFEnObUWcDa BMf6iZVYqGwoEGL4WnngbgPLQHdX49LkPwdy1Qg9cMymhNT47VWiB4TvIGT20EjVmoVJvU6wQZT6 /cgf2KDWJ84gqtlcD7dwpWZM5NIGcpKkgj9MmuBGIoK4PXondLP/N3jcppiwk7sIwrxGBBpcnl7M jCQZz5h91JfV4da5KkVJ7hh6NeiLQE4OYDSGpQQ7JV14jqjYN+tV53q3vJLWSpZa0daYalbzdI7k ubWDBiHvvj9MlVcK+vBP/uFZHGn4rNLiQt/JcGF6WQvtuXo2iwa14xbdb92lKZVjXQwlUX0oe9c7 gK6DmM3O05meu+dhYxV4EP4Qqme741PLMHK4b9qPwX4OfOxU5u4J2mrQN6efVBL5r/64ZFQTvm0T SquMZPYaBJUy4oy62al7Qfl1d1c2RJJ8HefjWTpnCxmnYtnTdtZgv0KoizTzGxA9TUEuRvhjeO3N 7Qurv8Ysl16I27CSvHOOakJDUDdcG4MrYEDSy/cBkFnbnx2Cpa11W7PWxH28c84bReog0VPB4AnZ RcDm0tQKYk6piToghlywhNXDpnNDhyNrHoD92y76dBtkGT/NjPFJGt9CQHImzbFt1Mj33cNQhfcn pDIfp38cJ7bZK8pV1l5ODNPRVcKrivxNekAEDNcDtkRxf825pn4YgF0VrY0PfNvnLB+xpldrGCYc n3A2zYP0vaCyqtIyKINcE56B2jw5Kkww45U+67wdAqQvX044q92gE3Sz8g1wkffm+ua8RHVMjAYy sTmve3NXJY6dyLqa3AYQNVm+jMAvpJvf5IuHY1WVln1e+L4fnhLqhJh24so/LC9lrw5MpptqZC/B Q0moe01O9hRoNLGjyclzxvQZxV02+3H8YGZhNXNk1wgUC0LeAJnwC6GVoVFOJhCEq60KmLKv9gRW n8iA//2h+qx8RHZGGKNu9IHrHmJG/cJMErtT3qWg/WJjA3hn9rTmdwR0AWiAuYnxFLmBb0JI/RYL kLVZvGfGz+N8kcW5ngF/GiCUJ7ahX/X6l6XlIUJMrmMx9J/QZUtEmE7iliTR5V6GrX8LITBrPcaO O+dgfmQQ6H/PSOLnv1an3b+9Hb5MTJCXl1OvDXRcENmqnp7/L9Gvh/jVGr+9nuMBLWX9wKAxKLv0 r42PZ56AjeKIO0aW7kp4ATAz1XxQXybb0PAkGk+pLPVtnEDaeOPJUTl7ZLN0aOPoFgsGX8/4eSqC THz+GPSyHnRLYEo0wh67MEch1Wn+2iG8hIzquXyZipe8nCv908bdAc+vc/aifjtYbnRT6McnrKE6 4Dz/eTIgRQ86PXszxjNlUx5koFbopP7d1aVhWf1hE0XzWp/kTRNDyD2aTK2ebXEOgl2NwNi4o2RJ JCuxhz4tN5XyWfQ2YAnYW/LuNMNry7MuL+pCO3k+j9WZdML6wxtyLoWg0CpddaAfTRhhrqqFmb+T XKdEoObZZXefJvLpkTCKzP9jokU2PbjWLTaQHBiDbJ/zJ8tNPKrmqF+i6W6x7KwtVZqfC/Tg+Q8g HXXTsswmAdhI8Sn3uZLHKexTk8W5XJ4od5x50uISFYwTg0QMrU6j82rd1PPio9QUnBh4DLM3HjY8 4OBB78uXC0ba0Q623lF3u25kGon/umHWNDTW5tCwMSJT81LK+c3wAHy4m7zZsABsIHg7JtzdNmGx rJBL3LbuVl5tlNMFZKF2mdmvsbzADMJOKsi9zd6JdxJsIpq9hYXlrZ8v6qe7YrwQxadxhV18jhYW oHTmRAPYxtCzVTrMrGKBagNi6ofsmDaQvyZcjtNSZUdfGd4IFjrNOErIh2nwDABW+ULGH/8HYL5f FC7Z/PYbqwk+C/4hhix2K4cOjfT9oNRq+jEDpZu371RUhI042Iv1emoFDQV4/Xt0uryPfCkEIj9R V2TC6EDkp7hC7amtUmy2PudYlrvQn1Ci+MFhk58lh8XEAxC9VnKZfrM3uTvXkxVCfojAfyIUipoW zM/uoLiYLGBpdJZXZa4jd9VvbL6eG1Pf+ess7IdxF8yJTv9trXocVUF4CcR+Z8MPOFIr07QU2hKl BXYj7uiVwEGdFqSrAqCoSGI3uXQO63EbradQnzgwrP7VSbBb6UkERKUTn7kDVoGT575v7WD51Z3w d3zsZ5tUkauL3TdaeH53HJ/OdjCR/B467mxq8EVlk/A2NXEICX5QI1Gzs8Ut8TGk1l7B0CV1JxN6 IRkCkWsd5Jbp7lMYpoCx+ZrBdkZiLHDVL3FJ3guZm+7c5tl/Mn09FYD/lei3c5Udv2BQs5rJhqlS Dy0BilE/see0To9X7sXLKfpgCxtUjC8hlwK4+RJRtp7oM7Ts3rAdh8jx6MUdcqGAs6kKmP0PF3CP ir2vIbluoFmbNgs0OFc8H3OOooA7ggvORpluA9yB07yp+31DSSN6HDqxPGhNrrGZ9HUsYlhaKuCm GOBND9rXFWOMxr/4Y9r65bXJU7gmq+oOeZxUC5vHGbPqUZBW+tWuuKOREw/gwf4ojgjyGBtc8469 wUZ/spvZP6zkSsaWI4fF0Yg9U20xeU2yz++MdLwbi+90QyKJ07GJ2jK4gixypU77MZ35Nn8IjNnD woTOe+KL11XIjZ+/0eZNKN+VCCY8OJ2nTjByy/i4n9NqIzDRs9KSN3mV503zeYjNe1WE3tWoflhJ Z3RLlUSq2L7rLwtZc6M8FhBTGWpHEpnD4DPKtY1b2yRxIL+7JjjGyGFNo/yslkRdhB+2phVIWzpK jldxsUEvuj0evhoWOItwmNQxxdDMdBxES067ObRna7p8rvZtXXkqfZnxXcrgWGMtrOekIJyH+30P S5dIsq3fjWvNCePuZXf9O96cYDU+MbwemRIQb+HDSVo44/gtkzJx+hb5Eu/6x9C49nfDL25tm/cu Um/HF+cij5a7SNu10FRBXhG73N5V91UOWPXmGsxk3VZg5wV9THxOlHW7PISLBSnyp9MQEJXUNSNW 1x3ZgI230dSteGVVIXIJWJoCCECwUpuWOgi8ZFidjhyNFuUs62q5OfLj4EzmsSHeD9lrEpZK6b71 1pCbXfJFwyxa7/ZPDXrwERRQ2LBzltS1XPw0GexZQeF3q8niOQuppg8A1xa4X6mbmwmd1RTzlRr+ XFVBnBZJU4KKVd276/aXPYp6BOPU8bpJ8zpOr8JNl/V0pt+Inxcum7Hv8d0oaZBEPSkWtZGQqw5k XE9LHgXczqMLtgAx7UJRNc6HsQF9w31oJ1bssT8A10UnAxdMJtRyTGwL5twhj/Ovk/Z/0gRa4PFZ 21OVy5hontG6W+PXydDPAn+3T5rxEMez4Nj2wV6cG41BAHU1DBghlHrevX0Y4f0uq/djnbSqrcTc 8DUvf/TkpzWcavZbzaNuI9YNWjncETdyA6QrFzOaZZpLklp4iBaAzP5dDJVHDwX1Y/D7i48uUfsg 4hpkIJ3ZGZRNwcUKR/JLjnwN5pRAzfsoxfXUlbKPY9cBSy7nZxCxTnfN3rQ0aitt2nHup0GPV1Qz MIlwcwaSeHgn2EB4l0a6AIO/xe7GTUDffx/ild9nvaPbi2WNiCjB6AgiSXssbvme9dlwJ5+3ibmf HuemdTbrYgZSa1NCSUwDYO+eV01mvsA8K79q9UxBLiZpI+8bbdNwNSXRNzU14uECI0Q860lMOCbf dwz5dKEn6uIaCryQe4SKJOJG4RH2Lyc0zeWE3hwnIR3wmPPtFMJB5ysSw+Ju/How6iQx1lZPp+Kd OQwNTwdVtBf+80bc2UPzcCLZvTp2+GRXmtmCJNDgz4Rih79KhnOVnVIMjHkyyKdfpuLWhQnp9ZAi j9OAcd2mne/hmPvYt0w/y4+02Y+sEDQ8Lo+/+lRH0U6Vn9kPIJV5Xl88ob4hFUYz76CB7BmPpw/R 6cuaE85SV7v2u8pyG3JCh87fsT8+ldkGbuUtzHg17ws8hOd8Nj9uWpkIkQA23uYvaCFcGJVwpCCD bxxGKwJYNotpySxmhFq863rWFy7D9mPkrnoSVU3tqEG6d8lxRKI3uCwzA4ZgKrHWxWUc78ue0xMD HRpS7Mwu2rClkb5icNSBF1nTs53zkx2fPTiBQu1rkqRwFAaHaOkdK4tfemsdPAOQm17AylhDFdIA i+5H/XUT6/yXZdSr6E3bRdO+5p6FsaQBDszTtie7kS+PyZ4cTgp2oBt6yHADavz1HjKiJbcTf2Nd SHESkDB02RwBk2WSVtsLUY8xOKDVOhTfFDWnuYXLvamqQXqsRNLxq0kDUIE63rNItdFmPsDk+bSN lgy8dNJ2ghVlVK79MEvFiT/iq5LCiQ9KXtwLtbXUEdjOzpHAxMix2kxzVvqNREeYBPXaQYpdrR3B ZXCrD0jCcjM8RUXiYYRVXFS1vBK/hvMDONjVnFEkvyTALVLWYsa0gmiGn6/MYFjoAxNODr7tR3Nc E7PNzv4On1O6K3PxYGkqtawbYc9CSqepLLsv7mbkgS1oM7ZvVQKwSTvmWHQ/8Ij1Pzcaf+01p/eu 84SZlCIhgbEI+oVMmgxVrcl1BBhbb3iXAJTQKf2jQhvdgS55mkBqqTtpc1B2eS+GfWdyBcvbhoRT DP4o2asTCgNPzm3WZ0OjuEAcSu3OhwFRi04VESjh0T8iqIbv0HZXjLlNbnIJDXhHH2ubYYIIseRO 6LqqzPKl4c50pAZhi1imK8yvVBZbymBZ06EmvoKJuSheywkD6LNdCBdkIG2mh3aP+4QruO6GnSpO 5AQ1SK4xI/CilvehEB+STdnRMgKx9YLiJL7t8V0jGcuZFvg8ndUrR7uTXgMHmJoe0lvqdHrwUVTM pcA09XrSOLCJ46dgox/u0DQX+Vke47IBekqBNeRP8uXxl4DhNXeFNM9BKOoS+dcvQvQXTDN0lKHG tFOzgiKxREA+ZTfPE5Qj3lxJbvub6xOuMEM5baaxRxVVUS7cYxi9mJiV2AG27exN691cbRwd96Rn FolwQKnjJ5TVO02BwRNmY7LLWVHUASmFaBpokzWRcwvexzrlFVIpl6u5RmxslYWQ0jN3p8fiN52m KrLYuosb2JK7IbGULEmS/OXBogMrkF/snz2qH9bwRW38qkwL8DVvw1pb99ARFewZPRtVZE9x+nYg VyKmCrBmHA5Qd5lzg4vLe2V//XPbQu5GOu0NkUC0nULk2cBaLcwjSoHNYAfMds3Cn9lyr4vTF1pE 9b7D4dmUdZHgKiRbrLzCPVG/rmoMnXZtz+sMQlHuxNUKuze5/oD0skYkgmTOUZdYneo9z+C1oqMe J2JV1SGTNRmXPHL5mxrgUtjdwREC5gklfmqoGn1Fi3TQTvb/N/wZeA8vftml8ih0p+E8F/naYCy7 Z6VJRTDsmLaUuYVhx7h3aJWDyHZ7DHkC5/9NW769cWGtZuyyAxrB/es4upGxsKYtFyLZEzf+atN+ oGdx7kmY9oMz7FEB7vXoowRq2HS3vNCuS+HbAOifWXUtFWyg6kniDezohZh+J0bzL7/MnopnRWN+ FpR5L/CKL64m2M9VvwjIScVswzO0f/ywNUsSPXQhEJpm1xPq7f1jjuwAJeBexqFv8tso1yT5EsNI r885fWmmOF2xzrI42hGgN68oLKz1uleR8vyV17QnsqXBS7qX9aMISlkry6bHwMixS5Tx92cq7Jw7 x6rwJxuF5mXPRnBktrEnf3Co4ma8GENR3+lBYemEMrsv29GbMshQgd5kyw99r/DOpwjsdDm55B+6 bbUHs2zL08PalQVIsTASlvJAb00e6KHikh7U3Df1ak9GO6qHIsYGF9/5H77b6bETlQkDJk9yB7W7 rzP211HZnEdcM581JV6zEvPcJka7GVFSaI8EcyNTV+ZtANlu3mJ/9mb9bPYLxFjsPPsVQDaE6dtq 53PkNRJdwaQPwKomJJB8GfqXD08k663WGZ6/qhlkRJeDmHv34q/GbW3ETU42/jLCAFGi72KNKdWu cUSPOK5BRz3SGudQKjAIb1h2gtRPMCtu5y6hVBFyHYoS8e40Ah6SH2shevSXQPGx9v4KGpuZSpRq oRfz4SA4m1eVPM8LcuQtYZ8STmftYNGdYS7PpBW9uxGjtnNYDWRffN/T4Jz2VndpeZ6RPY6Wll8r CPMbRCKkX3Y0eq9OOC1RLBP8sMQyhAC2B6FZARU3S9OUe205Fjsb46o7gywmHjTKrKT8ikKzd0iI +LQrW5f/eINeA9jx0qzlzpIO78ti49HcVsr+kSsfDLOf63VDKfd6M3KXmznS+cwx5CTzVZHooWNx +Jc5KHfhhz4mRUj7mX/DA1/JXG1L4mjhA5SFXX84Oj3JPK//aEXJj9StB4cOO5WewPp4Iq6CmyRs KQcx/Q/qjho59T/DF96HYb+1NR1bdnihLFKOnijJ9FtEaTDZ09rRwOTcwVjlbg9eC0v4vf9XOzDM wUBG1XpTHdZNnv6iz2Sl0w1mmL0TDBIOmM0aPA698nxCwUJA5cTU6qe40lS0uAXSXE+FglXy2FPQ /xjBom7j2wQXfxolFWokP5Enq6IEh+XmtiGvdIcu2QJsEptt8RYMyaxuKdIB2TUVh58ylZDb8We1 fv8gEmFkLFhvKhD6y8MMgKsaL7fm0hXXIJag6QbW/aeNZtbdu1ZYvtme9t880mf009jSXdglMZKP dXa1iSjE7APdM2zybefPm2mkjuZqW+7PDpW4TmVRh3mdwibYCw8X64n1+lcys6dyXDkXhPsvZ1G7 tQPtPWAZrkzhc3h8Q/DuquRZMQZIWDkoM0VHTyFwGVcBC9i5KORDzisg07CdwwIAx+ctOSv+ArjS xMG42VNz9/d8HUJpu0WIP4xSIMPbOLSd23HzY1AKwpcNbjw0XHECH+si3SCVvmMIGPTsUlliZXq2 ZkojktVTmLuraxCyLx99I0jmD/DjFFvY7tjvOUpEQeMq/yH8m+jniu1w1oVHMYLOaITFeKVfmDjm uv/dwqVgqsJ4FkgszR5ydmAJBIhlN/O1Mjrq+o5X4iCA5Ys+20RMEKnJddg51lGiVoBesoPR3Ufm Ygolbyifir8umrPHytyPyq4plxe9RRQTi3YH/qLr7d6IFfkHdhprHhWr8DPBeGHcyE8wwdzFrnoI jOr+omj8VkGGsGutA6643O43TPywVl6jyClcXPliJMspCQN+8ow7p9uJ5gQ1C3pYwvjSQk7NGsxM KzRdabRnLK5mt83LcKI4buypbkXkHmm2b91Kf+stdCHWcjJQXstHiTcWnwp+RivJEOp+wh3FZikZ 3rti9iCr0j2j47/Cxhg6rPhMQswgNv649l9Q3h0kfKIASPUjJJMnE3IyS/tjqryYSxKfbkh6KoUl TzLQ8v2bF/FpA+YLcNLzCZV5I0fCyePz+5JwTXMSTnXa+Y9u3yVPdSitUSFOamBqmI35fBqKOrKU fAVPAXJIumtpfzzNJD5qRBP03Sp7saAT+UVZTSxPOKZfRLKJHC1/4m3DXksXjT6x/5aMsMHaW9RF 0ej5iQhkswvXlvWRr1Yvn8qGC5j90C57iM9//YONo/9yjn2mi2lMALod2Fd2C7QA6pagbFfylzAp 2DHllTCXfNTqTqpBPBqBQFMaM8sZtQ+7sd6E9yw1jQYSGYnLEykX1N3jtGnNbs8MWF68RidJR5Fi z+OIalpY33Eo29jvqIvOcCnbIJoHbYZeZSeP5MM3OGGfD3+RO6+NVsFObnS9TgMaVH1ZZod9SeGS 7Q1mVwOBuAsTnfZNiiJI0R0Ho6NomqNhsxsaup9RhDUC0M8Ss0dv5nmfZmQ1HDU8J+zslrVnNG44 vx47zv2UjoGyOvclghKWqBv4UcnkpSpfiy1a9NkEBT+lUZffBAOlUXdbaTxYAdE7sCsjQsb3Hn7D 4p9h7S/otu9c1UisOsGs8Y9gSP9NtieqFORX7KMGvn00nDOyHmdB6pIMxMyX44CgKX5c8pSkfBfR vCtlUyC+FJkyPKh9lsG+DWLql2VWJr3Nnvdoo19ZkSNMlox6WVdmNQwCRq8y5LVMR8C5vlY6TF7d xHUuNZ0ekpY/KdT4/t2kqJ6IZmuWmACR8c2fcGTzGb5E7l1kPhRVxwJpJkDTFaolVEON+tRSm1Ve LP6wKcgM3+5hV9k6SUckoV3wFArNPKPLsLXZG7qmQMxVRUBkKcNW2rqjod8Es5f/g/igGrKHLvHI /sJXod+FMBWyG/M+Y8GTvLvnkXyh8FQo1UFb3YGkng8lACvIel87C8+SKPF6hhamRLlMLXzT0NDN E8Y72/VcmuKBYFBO7z9bGBks8wxhH6Li05d4lm6u430vHhIxjs/EoMuYk8EoHzjV06WNGIJjbMdC SzkDX8ZJSVTvh28C+aItK7WF6WRYxC5FC0nz9n7uK8/yqc3uySy2jVCcFQQjvODj61ceY+HpvNvZ /nUG5GSbPnJ3/gEAkCDbTe7qvbtEHZRsGmAPDqtyivYcKoOM29xtUs7BciTvtSDWZuxme36UpsBg M4nT4thOEwt8U4hjDsbAhHYPS8lDRXYSXaaph0bb6eowhq9dl+uTBpR8XVjmbIqUljZ8K1fHb4Cm SsXR2eKB0Nw9rhvpSgH0i4FjXycvJu8DLbQw5yvzo/AdRLm6bXN6mGDs4LUArzQCV4vxXPgO0NJh +cVBuHRS6mz306jRKmr5cD3kCCutbEb1ZO0sEPHAkHsVlRlGaJ+KjtaZcrhxSvNySk/8TaOomS94 xOcKXu/jrYT39lL9QFpvXuHDnihKR8IBeR0zuQOfXT7PVUeTUxwqZtfrn9xRYOa03sfpjV6FgFqe qRRBd669z4KS+HT+0QIk9hwLOuBAlT0SEKiw60zdzBZAIW99TAWxwF1WQxTDedHxqKM14vvDXzpZ o09d0DPKmVg5ehM1WPrg7yTg3qNZMl5CIr8/NrSlljWhJcO+RfmH9jsi739Yzra6ew2VML2e7lBB 7HmVqBiaYILe9kwoKaARpl4P6dmI0VyKASZRvacQiJ6LsDydEeuBKevcOVkp8MW+pHoi+iW35gYp zXQpMh5fXmw2LlEwF8TXrxVODhKN5AItOpPHqRFy/7eFQ20pZgBEymFjwCOvHIOM+jf79CujFPti z9EXb1barx2XXAZ0Yi+kwbtWFRSBpVfRjeQn7+V6qKDn1n3BX6APJ5zgm1dbKw4x/WKuVq7C3cs8 TFbkqqLaJsMxsAbDZeS6mLq03EIdYCNyjeNR20WXispjksm94wfHi81XkowEcd854UnriOMKaIdC iPg5bjA5GKGh3QS3OTokJ7+eisaoZPIEApS9JjyYlIVU5A5dCu+57qm7iFdWhTzAg1X4hXnmHMn9 Wk2c74kloXqBN9KiP9bSWJm3xZpiwhINAArQ9j5fo9NjNvCNBS612mli5SB8vuUSSFLNoSkX3wOv l73VN2FebbzKQa+bh8b8hz/svc3LRpYg5W6PxUz7JQuHAh2r17P2optlaTSlAsIbV+5W56it9V59 9zpS8m+Dn9h6gj/R3Z0+FE4w9/y1BIMA3YL1BLo+lmf5HuItzf1nmDgXoLVO0xPHsQpEH7jlOPZd 0oO3Z6y/wmutCi/MHsrDr5L3jOFmM7uRt+FlbWtJdGOOhpWCeWw8br8cFjuVMYNE5GJuZ95oDH4Y OUj/gRQwdTsAV+QREhjFjYKRaPlMLqXVvfVsIAsClviroKIo/0BZSQ0ZULOGUSvP1UtMdjTDWGeU 6mBu7iPF+HarNp+Nz3+7w353QhMce4t4eNr+V2EgYLeBxWJ7gBWnw1V3BshynpzBkLbd0TAw4gfg /52HPXF2uu4MxG2rO1qGZ8zX/5NQ5UPx/2YP5B3F2e9f6TF43WAOPxwi7QvKXaUD707CNvaEu2cI JPLM4jJw5RJ4XSKalRgVu/LR7mHVNCrmFnZhKEIyjbZy7Moc3ZTI8EBWKE4sFZj+lDdWJdJU0aac piDnOYEMy31roWQrkv2zqQ6L/zsNnIoCp6JOSkdH4LDyD55C6Rsj7Yab9RPfKU2SnK0baytDC+YV 9hbn+W8napA3wmP7S9HIHEzzke2ruIZi6A+y0LulN88w1pLZ+Avyjs/N6DY/Lmnj+sunM+Evr80u mLUgSECFm9/GNA3x5WTIELG73wJKY0wC9LtiudhPX5s9ND/+nTrFFHn+3JsJSpXm0spJ7mpMmNnC YHLoBNJ3MmoNyJ+kf5TzClzhtl0VxJnn6dtPFNtBjzefzndnHEqIIpZ9WvehCJCBe9ZHRHm9oQi9 KhEbltbwLIYq+jccap1WaY9B9tcJOppV4+NeuJmnXyM3GHDWhk7+r7sVR+AK3+pEoP4xxb2d3bVf xWQvP38aP6eLnkMhuVLOS7lJWpSxyDuBG8jjD/n83Mg/hE/n+U9akABBOkq1i6TvB43zboiBhE1B tgPvO5gLxzinLfz/zXCaxzx7haJDZl0pJylZ2G11K2W3ZBIuxGPh0VkOs8WQcLnVtB+PGoZoch57 rI+JEdKZEV9emy6JssT5AoVeoFEzMBzwxdGoLfFKK98WkszUcxaK/hZ+LuDdUeuW4WiLpknMmSqn fihRXYps83IM+9S/X0K+exTqwDVG/lmWgQoZhGvDfaMLHBhxMZMEJbuLY7s3ladGScwQ02/8dzlV 6ftvQK5zjTQqCuLZM8my/d3EtVBJuTTfG2O0o3OCT5XGZXiP6a4MtQSvtyYQx6DEZgMFxGA3UySh tkxOSPm6E1AIZ+cfdVWhNr3ySMU6J62n8oEs4lmpRbO94V6yFNoMSf3xZpHbQR5EvsL61e1utH8T OJfaaqPqkKMs+Rq8pl3RbR3xk3iPY6Uh3xFoHuzxbPv/zSl/V7iANJzrgANTSgeGLBH5Yi+w5yd+ 2+s7idE7fo+HyYJQUI7X6LfZh2Wu0Yv7kipfsXkEOFYhLqQCwCHoJRcIqzoWGoC1Is0wlIgTjtkG l3k4bPIuwi/DuyS3rCHcW58u/YlTYZg/C5YJIQ+40xmZAbm0qgxTbttyQai170LNhtdW8m0Hw3Af hZGejODeH4pORXp3Ih/iH7tq+f7daRiS8iKo+yCoUzcYdkJJg8jVdq5CRIOZabJF5ppVgSuZtuHj MgZ/UifPrUzeDAIkAEM/9c/ONCXbytF0FrjKqhTeex0cR6lzXAxlRURjD/VCk75cF1kFkKhPFNia IDBDwM+XnkxO6xbLmw9QNuZFj/pXR8hvBN5KV0Nlra4xB9ywAL3Ni9UQjYJ/PL/hq3J6u66v+0Nn MeddxbxlcAxImllGwQMdSw7XYqaEjFr6FSxAxRgskOpfBP6My5hSkzfHktT/t9c1aV7g2QPdnWtT n4X04tKVVNfbZBs6V9hLqFsN2caiPK4i14452fXeTPeHjVDiYEzVVLhV8MlTVbmklaIP+2gtCwC+ +ra0be868QRxgvz9NIaPhoacGiop6GUk5pqQeW5nIe2058FPmGnbKBQAmmA21Aw3/+wW+fD9c5/j N7jfTW4+eAAHzpyw0HxaKOb8+3pMSLd30Q3bzZ1N740YnoLvSUotSbcMdPkLWih+yOY9ZUh3bboM k4LZl1+JTVXDcIaRp5+H+HHl5d4v879tgVRSFTPVgLRSTkykjf35HYa0OdIN+hPkzm4v8f560g4s KGoU8PL8Qkl0cRZDj6TblPIi0E+p/mc1xXeiylVVDW5TMcmhNOz6oVT2MOr3zDoN1m3DjIi0DuOx BCNgpZt/iMbMvP0A5tVi6v4uPlMapDsEkSKnLNh9NXcAAFgNDTH4xV3aptXqmBHFtbjoojObkvDO e130xe2ZUEsidZPlmCKb+LXoIJY5eR7caGpGrnU6uXkNXwzeNDEzV5GOjkwHbm3x0XuA5syIqh2J 1IZjXn8sX0t0DiDyA+s4iDJZR6w+MqBBKeOk0S2RlX4qgAIgseSH6A7J7nD7KfK6OEUeu9wqqpmV 51XnKZdX6XiwH3XeVamG2AVQH+nmNDs0UqC7Qw9cwMYkoZ4LFgo8cOMWxQqY6c76ZLqqP716PpNu poU/mzl8v1HviseXuw+ofrhdJAbnO9ZXK9z2rCQh+C0m61Q0niSqUZgynx+gfwnnwalpAxEjff31 X0CvTW680kpCn435wdwbeT5pCPks8070XteofzlFCSK1apb9DkXSit7Dvr4TfuNOe1Mzq3kinjor MGpbr4pxvK3qVlbWNnMOkideJX64v/whiFQ9aUJPzkAwQBF8kp+1XtdOZ7kFp6SDnLvaZe0z+jTP CgMBk5Utp9XiQ0mxBtTbdTfwTRy+c451Wvi0MULkefljrV1SYvKtaBzl9mci/o2qyK3HhKdrjWYa uKFdFGtL72cNWxFSrET+GSfyj4bV5ohbeknY82J7n1A/s9q09goHzE1cU2+U5JrG7UMfNQ8av0Pr vvKJO+gD5BZfcDn5y3AMcDAK8Zh1oa/W2ZFZ2lcC9n1ex4SnCQSbnOk0hTnhdvhUbihJ6Nd8Gn8S seMrr+lFF28sKBvQfSKJpjF+YKa2xpkC8FGVjnR96XlzoAjPC13BmK844NNQWRFAzsBrqW15dW4C K2pW528bP17nuL4CL/98YZEQUShEW71x66E/5I6oFLWXyHBG/pHVxFHvZ/4yy5W5qi37Xfr9D5SH tYJBDVv/1WPdXdZ5FqMTUzSDgpr2EjxTONaKHnLvgNhME7HufgO03xF39i9r+LewnCQaVR5FogBl PhgehXviaBNW7nJGA1pQDD1xTUBhpilUviU7o1LzazRGrQtiLbIyMK8YZTHQq92fmTSxVdc4rfF0 VNZqaT146+A7/rcFlf6odvfXQxINtjTGMe25Ypw94HYL1bbGllC0FFyG/1uh5E7YsCReOK/pcL7Z PA3qsC5yTpDQspvkOBAYekIiq1oyCgXcKoq9R6cXGyd2dcnMF/nF/txbeCQ+zYRttMT8CTZPV7jj zNsRMwmOL4bfEXQ4aQUTV1gjfOjMFrTDuFkLWEIbIUPQK+fEJqH/YD7Jyv2nAQa7O11M6X29nrgs FhiHh5UEefRiN6foAIM2tydaPClfpAGDEVg7oVE4wADP7eUASTtchRrG8g4GW5RGrG2Qhvwjz3ZF vssW4ogeKbrBu0pz7HSyr4PSJdqSTEAZ2SObBSmkfrO5gOVr1BlNKFvXBIQSOA+mCm2tr5NaJfjL hXxb8kb2pxgzqaAnuxPylcp2W+kQIYguCYC/gPRLMx4Na2w+GJLdwlCXUTnS4kC4OYnlH4U9ybJ5 iAcU384WxE7csqOuMyioAgAWaTqE3Gxybg78ysqcKHp8KrlDBTW4O5hUR/PyFNY058eN0aHnJ8Ur TmJXniNXPDaH2lmFOyuxDkiFkA+Pp+Kz0aqMMbOjp6Vii2zlp0JcHCdv4q2/BuBC43KIMUuAyPO1 Vxr9KExjk/K6KloIoXMcgF3KfuI7OUg45lXYfe6yvq5fGHW/02x0R0uVG5F0kGb6mzHCNU1PDrBD A4bx4u1qP6GwmSny2k75LFc/H0wVhAXFNYrEiwCvDLcu8q7FQk12+OG8vFGeZn9lzoATETWAyGwy LjdqjPpSEeI/na24xYuYOgmIn6WBK16LuLeexulYktv/ZYeCpI/ETB0YcZetYtHxaO1/wc+mK106 i32lHzv8GSm1nai5Ow0ECcT+AwmUfZ9qFw743loXWqMb6i4m7Xjcx7EGskCus2CeJp7pcA0bHKKf ZYebeiqquLcPZGvVc4YcRK+y+1JjkNNPBHkUi564wvsvwZeL5XhoCoOFBB+hGXONWKb3kMQwufN9 YUsUKZ/PiMugK1+7zt4atUwXWtfshoAnHkS/BNdyb83DpPc6AMXMKqt8zNeGaVWnNlr5vcpIplQI EcZAYthwi5o8PHrP9PV2aYzijMtq0P8XZR017/TojC4+rCdaQ+rSQ1QTRTwdPpm744/5YtNlXCcA Ifpa9hxSYuSifiHWSEuq6Oz6x1v8msKOnift8C4fy38wVVkwBPuNBEgMpDU2gc+iB9ysEGdqjn2y DoFzo1IriTMJICF20v1KH6ETzXX1qaNE8G29TehEXUKK8Qt1Y1gY9iDbNg9etDyz2zsZ+hWoZlPS +Pm58tOUe/Im6Eimo+dEbtAJiGC5wFMovt0bSRZVxsONWZnrI7VOeAHZ+lwlVgrjK6eRAVDhzpd+ fw0offVnZfPRqYRo9pJTT+DQHm15uMGTxw1QD2l5AZYCa2BZk2a26C5hazDy+SAQdcg3VUDs5POh PLjWyXkajzxPx3soM9CqJzEgtK6h4Nmy7GAPxzkKo1WZWomxQgqjwq7C3mKpFwJgOLXCmHrYgzYO Ws59/eXdRYV/iIZNr/d6TRMzROLuSXvm7hhfL6LfQl8gTOylV0Fh+CfH91r2ACfUDjsyBT2U79mn AOyB26klLMzucbQCgoYNFlhGObibDZmILBfbAA/42+g0RpzYL7wdAmnskDqDVE7BBaj41wYoqPYN wS5DdR7pUgCGhYpV6NzkSb9x0yJT/9Qd6Do12qLCOOauBLGDhb+Fwif6UE3YdRipHph4+mVYabHP 1Oqleh96EWGkMLonBqCWeSUVse/FQglquB0qsezew7ldVoKc4VFBLC6HTr8N4RY31QKZIrUV9CB8 /q3BXvWJwIO6HPDg+aENVsEMR+yvGGB7Nfz5W9awHQwXIMSrgMjGckbubyfhZbiJmTfwB2ZxCQ4c 6+rlqvlASyQZpBhnu6Vv7VHldjQ1U11amRQ/Y7fCV99r4RDB7UA8Spx7gzPuP2O1gYolMpy+M70k AwAx6OggrDy2K72r5E6aIbfBseJ3LlvLcQvxnnKbMPmI8Umu6FV4TzLQ6iMZFboYPH/5Wmb887TT 3ql/pWiKiAMRnHO1yD04IIo0eC0vqNUw2A0p3sdl/gDFg2wXnnrtZXgVfDgzK+9eHwwlIsctfMpm ayTDoggCM0ITbXwFoQba3gO3pq+Wli6tTRtBiUDlAob2vwc95Qkz+N5RJgTEmT9Oj8Xk4mlHC2R8 qZbA+gK0IE9Tu9zr4kiW5S9upmJAgngq1CAVi+A0ksC0zVmEKcVdtQQrbPfAcMybgy9JYCE0Azfd kDISNqQmCa6HNMOfcXg4T+H640xVC3/NIK+ITM+KlDRCUY5XzcOTn84+vpp6c+4M/PmeEDb6h4VW lrMt2zIwMmHymgyYz4peIPCcx7SAQxIyNpXljwEHwB5a4PV1Ya07XoMGMhvvZ66rRZQdFHe5pTnk wUVE7guz4TsxfJKsGbaqQvpnxtElJejwWtQIQW2Qn1qgOUvt3snMTxqZgvw8wUxC4nRTSw1USKv7 I+kaesKyRZxdhPWecanRW+f7cT2oZzP1SuZHiLnf6FJ564BndiaS0yquDHt8rIE43c7FjuqXxzqj mWrTlPJmp3lrbsfXiuy3kr0d5XQbdannIuoICpGZTsnOHu83wiSL7LJwlvjhcKaMdJ4YNjpG4uQm aDP/TiDMO6XPuqT81oVrB5A6R2f6YdmGTnN+3cZD7qCbv1K9o8gg6ToiUv+dhPd9/+SKfctdaH91 4v9Xb9wX+uzs7I1Qf6y8Aw0roSxUC6LeuF6l4DOKJTsrMIwWwfRM4d6+bhIFtWyWt2VXwkBG+uNQ hqFkms35fihbifLztmY5OuVqHlXJHui/mOwOj3AtBzH49Rau/aQZuGH7yl9ARqecgMEiW2qmkbkE ROx+j5cilk1HdJEsMzNGOBn2VyQZxtB2R6qbSP3xPAPkUrjXbsMQRDhqMFQbT4yTyu6l9tOkMOjw VPMTTxRbsEN9maaNkRmvKZ16zmp+PEyApq8vKawpEFTIT5F6uDb62F1TSxVea35MDh1ijVsc+PLL n8nSLVLkWrW8Hlhta/UmkfVz0S7Pip3/VQz9cHFVCQ1hHTUdeFC5aXOyy/J2x4AOB4gMwqKT8Ymp u1sC6dKNSrOA2kTNgB6k04GRB75fR8E3FRWI1djdiSRlhhAuJpXrKHTmRieI0/nsHh067dVVU5vA n0eV4YaJchhyQ8VUJw1h50m2vvyQhtloqpLUnXvEcvF5U+NF2vCZeHvVkG+jXIQaIiNK1GNykv4t 06z0gj2UNQhOHKpQzR6KdI5+Ep6+6EAudj8K31h/1MKeqCCz9l7EKcxNwMa34dZulKvwbLE2h9Qq ZQcx3XEdGtcyvk7taHBUKhqNiHLW/mrzkL5cEmm3zT/OrEfPuT/J0vLin6T8rES5OamEJrPSJmte ItljPxc5YNUEidUHAUwAdYyTKqdDdqwHa6uEtzklzdaTLTu3twKT7lhUrWxMqRlAq24TfsBuvm3e c1R+U5uYK/LN4UTIgihjvPE5FxgR9EYmVcTrf0a+FNZWo+dFiRUs5hppASJcz5mU2akwmsrAyslk K3tIi0jA5gvk6Ze9YYNDlHlPgAaFqBA9JtZAzBPUXaRHDuHiH2zWC4SAg0NLI8kEZ3zmICm9AyKs EIvSfikHlSpBoPzb2yQoqtAGZQK/WdQJA2byryaJ3epQWdftuM9lS25w9xX/VWMmGz3mvpHnPkkQ KYjLsBrKfcYsSW7zzmQvA+Hv+jlJRyGCZClnelZHraflH4Y4bnZLNpXHkdgVpdzxnJ40x5lHnM26 0sWVuU0Z1O1LrubKorxM1shbK70Rk6gMV2NGdyQetrT+O+ZPg9IPD3o26E2SQkUssmbkNdVwVekd 7wxvOP9tXAiqD/MXoOrqeWuGveF1NNgnh9JrXPkcAIPnSdU/IzXTIckHftJPa/8gSt7qW1awo6yX 4w7XXFgbRATuAKBh9iSPr9uxfGr1/S4G8WX/MkJ0lH1iQGDT8l46i+j3kA7/w5jXJL3t4aZgHuD+ 1mNTbjuNmKbU7NKmp3cwnkC5Vuk1DoGVUOQWrWjFYm9sFtqP4RDmr/GWz2A3j6Ft8/4dBjVvtiJ/ GzsXp5rmrxdHly/JJGBrtVuIVUfOh69UOud8IHneBd6M2Z2t281SWx4lCkeceEK+CO8HW44fpWaR JUetOVadPFbAi6TpwZ9gr8MF12ZUn/3uH4EZgItWHZxHdgrvUxFIL0T9gnSrhCcDP2Lm4CVMNS6Z bg04uAssFIFPRZ8qc8cnzUOdwaIp7cAsGTcLYXJw77Udww32hic9gwF5H0F9ld/Db3pEbbvwA5kf AZk5hsl6keYGsmvTTWYPHcBslucrf/C+zimiBn4ML9ydDaqpvhNscUniRNo/DeiaUTRZUhrnez1k 8jNRSTYop3rkOkJ6utY2y0uLEtJAVfUMFsqPZfKWqkxbPHolWi4GofZw8y81s3FcFZKuOLQuQAe7 HTdDzpboj9E1rIImrS4hjcMsAMRJAeyWxxiI2Ed3ZDuJJwWQXZp7uLxVxS4bTTrG1zNuJnEvHUkw fCNnXVieT3abi0/r3GlqjnEeeo8O6IQ9ZVDCi8oD5UyG+XFkrqdprG5AH0o9FTUPIW3fCzsche52 kfscEzYphXuIMkfdgDbDiBHCqjzTesQbuK9w6vUMVSmalZCOBkHhrwirF7pMh+CRO+DcgYhI4zb3 pr7FeS5Ip6iEWy/iVCKELiDJ++wJUXrGK9IKzm9W8qzuavWyiG8fPmQwXXRcIGSQrIDTL+cCTp8+ ml4lwjaoR5y7nB+FEkt9uCqB7V61L3W6Y8VhQyi+l/7w5TBdLWx0dmquZxfAWmUGrWPOeGcjlfse zppyiBN3jHH5i2ah71+sNLeTgshgU4ZDyapyc+cOT7/U1DKjQMBAcjfIcjDXrLz/GYtrigOh2b8c VUalPUr53VoR/3GirXNapVmDnHWZugMgBNGdnCnWvCLZLx/rN04hcs34xflbZvUGYLjj4UWO7ppv giWlbB+3vJY37qNmOf2374TPZKr7lt280rT8ue4sTnPYdMo2D7xz44jo08zjozIq78ivixeNjUXp siFh7DI6qkVIJC+DTRv1JfBXKLHREaIMpZ2YS55i4yH5YHib1x4bHTp4QmCuAr94xXlPUgt+fpVN 7bryj0t63PgjFgDAFUGc0lhAJxx4OG7LUdW2haYo0gXWFSpUcrtOLT2SShzXSHb8x8zxIiF0Pi9F J/aPrwmaBoTSgJ/517CNDuDAQ9DO07ADSbR1BiBYAub6eHmqSA+vJPjepTGq7kQ7G434gk19uGz7 jdjCQVvCXm0NMdhMAhEzazwxiXecsaxdcn/QKODTndDrBHxf172AeFq+RM4WtohP3rLyjABZ3lRw N+TtXeFUkT6ntoZB+0grcFexkEZp88MV2XR5xydNe5KmIHXn12KDcJ6XVTdBYMaJfsq0fhgSXkRq YIsow+HGm4FkuWJ6r4CZ5TsZlOVTVejBAsuqZKeSpx/XmwWVc4jEdrqZz0VgpN6SJaGjGCyEPxDz ZNwv46RnVEuPvxc0Q17OR8YwuxHyqJPRHosuU4LTZjBtx8TsZEjEOHoh8rD0nJCEBJdQ8Rzn9JHT a9+nh6RQ/cn2SE2DvOHXDd1CD/u2X2Z8oS05zgiDNdEyvhGOEigW2REYRgFfHIPODXtbHf9XIla0 I7H9PISFcXmxl//GgF0cLjHGhGEikgYo+WMaSpgBjSFBTJNq6jr6lTQlk4XcYEEHvehdNVSk5ljs Ib8Zl0zVXoNod3KPpWJM3h1y/lfMgUvQmrz2S0N0+swK5iFpsoFu4o0UpyskRW5XNkS2YpBbm7nL T0nWce78KcOy2hAP+HZPeQPuMyA/PBTxpU8XFNf+3G01EX/BqvfOfnXXFGGT7agmkAIxKMVbcnBG OwQU6lBOctQu241CE6PSnix+k8gv0ceHYLN4DgiKJDzXAKQSm7m8Cor5td00nbfAdqHFrkyHq8CZ eE6bBull80qgVlLCA9apMizVFdnCbTcWKINPuJJbvnQZIaXZcsgsdwXajTzvGe/l9Cz8aGK68dsR rZ06F5GxLJLurm7DD9216q5at10HgesSK5yK3DAsYu6bQlQUgyRA99mArMcoJnHf4P8jAq2ZMHhZ QJu4JP3fS+UWvzulu+KOXfMV7NDMHoWtoeJMf275eXppAF47VPKbPEmKnsEdxfw0Jmrb4IopNciD Ao93Mddwcnil6VUYdmQqnQMC/ALBNuVvwBk9UJFWS4jDBVt47vjwCRH9GHt+bBP+WEJCJOCM0ey0 LGcELfEW9IhdKi36SLQPTsk8RRgbDYSVdfx7DCqDXkdWV1YTLFf7xFKK8SWDSYJetNB2f4PI4g2D iUlEajaC9xCH/851HxCWQZxEf1LUuZaWkpxGPTsoAyOMGip4BLUdgs0mLBaVPZnQqdA0XBkctIQ6 YZSW1epv9D9hpc5tK0HvkbcODj+yJHDrFFnmvz3ufV+Z14YPVVUFiKl0sbEsqsprKkpSceyVl7fz MoR+dk/tUbtI2tMuEsp/XnHG2RbQz+DcT3Y/VQOz0fJs/hBLbuBrugJuxYQ1ww89RD2LFA3ZwLal fs3GlQWH958kfrrasBYRorGVKDJxrnv2iCGIeHO5rP3sWIyFFDTKHkbNGklrNw90RcGODb3ER3Ck r/UCzFArXK3RJMawm2ugAFCVqNfhRg6Ito8P5d+JpZ8TPGjU7y0CTubcVdSsaMn4+Nu4lJvSxGcP +OPAEShmzo7MdUFvBuVrTM/k58VsgKmqmfh4qxxWS6Jjf7sPeK3KQMV+teEcIRqrfxj1oMiu5vJx yOwS04pzbhltQYuqFknh2NWFxdt2sla20ZgJc42tgrOFYz4+VfNJ5YZySctJMXLgjm0UxQdmldkY veEg1HByoOUAnAJHhg7MHAaicrFLCg3Pm9A0SS3UA+soNiJv9/oXLveiE84HUYlzhBO0LxG/WakR B+gIS1d+8a4Ngrd78XclIpXPBeVqfrBobs5oa79irGZtJcPszLv0DvqgHiONY2Ui3OSuimGNECwu 4lPDj9Fj0F7/pDClYVkC8pUnqZgi4qOVbElJytNwtSvIWlJMwNemJzUGgK67rjyzHd93ppM/5vEi dMXn6oimIfYCY3jBI2hc5qT439Z9dkgXqoabcOTzR/4QbLnEo6v9v0yYVa9wQwBJB/HiiRK9/J3K NtHPsBSob03MjQgualQxSR6RPQsoGMfJdByOEwJouPtoMoaArKOhIJ0GruL/OmCkvbmVEKBNcHwE fivBHxF6xDu4Tsi6uhietl9Hq5H6VbGceAr+FSsx/th+bfKVdaRHxwI4y0EQB3hyAitadAOkfBQp 1WvVbrob9Ru5g7qGuP8k4ljgL0zP53FHBBcMBiXYRjtFczqPuK9/d5ffNadkaod+U3K//2JM2fkO qs74cdGM+IP9916om5+gbMbklIz+vkEiWje7C1YPbTUJUogSfidTCU4w7X2HyFL5rFoM5tZnsTLd aPFjNNkKHylMmpDEg4gjKiuKmgsrB3rNMzHWgmXGi8sISySqKVr2ERIoCMM0fwynAhcxKdVmsTTP S+c0yYbDMqaK79itV/fpAnt5cSjJxGiJ7UjsynFFclbdTxFVhx6oKiFWY4Pqqu0xi7HOiG8yT9PZ lF8CPwMq37ZVO2XECMS1XAL8rfaiIGYYgs5lrGE2O9SCXgl+6kfUFHfeNei13dFuZtqy+aBSgzf5 FrMZ6ufAxq+MHHpa+pZFe2sGX1ezol25sdtx2fvEIQwcgPxOeV+rk4cfw4DGM7XCtx3618T5dnG0 mCs4eb3uo6kNYnsTiT43Yui1eC2otgKCgYEHlAe/+qit9GtJeZ4MuDbp/SN9FrCBC11XUXnQKsbI t4jia9HVWBEudf8LDbWDuiYdfoRad80vrlLRxyhCpWguiwSb1psZFuY+0uwADLF0q8Kk+lZRE+jr hMuTap/gVegsNmIyX/kM8r7APPnIGeUxtcDZ1NuwG0Snp0cAz5faq8hgFnz7llA4bKeho3ya6kAg TQuheNI+e+gFI5NHlIS4BD5XJ28nTBe3YMt1eg5NH4Rl2PJlqmJ0wWiJEx1SQCD8dIM9eCM/+G9J 4l34s65Ag2h3wanDfyyG+LA1F6tC/CtapHRob/TnvvIE+sXD2cvxsaKWb+PPQ+rAfka2my/2XKdu da0eq1XY7Rxw26ltDJ41erOqlsIbSZ7tGGt98IH7NAuZkvgzTfoHHOzuuH+CI2m1VSvDGBgMKd9A zczUkm/jab6uZKGgIwiEl8m73mq6b6yP4ym4Xu4CtlvsiAJoTnrViQbXH9CR6wffoi70Z60RzpAY tULLJFcSGwEgoyFHcq1SecXd3OoGXKDApzaEiTScRt01EH3g9V4NxopkfRxxn4sG9br/QOf6OVvL SbX/oYhE/V3qWfjtcHMGj3wbo0ykvw7sD5TtBrYRVF0KTVdFDBINZ/KIaIZGirT94jxV+OdmWlip SlWc1+FP7eMlO34EmqXqn35Sn5kG9A0UJUkazdRjs/t9xSOt/mJToKQ1QHwKxYzMvs8Mxp8oUegx mEGlk52LcVqyhDsWqQw/LqJLws2Pkbv8cCYitU+EpfOtQB5NSjxbavISkFoLUbPwDLv6wHJPxkPf UM40Etsms5yAEk+KKOY1vTBfJ6JceZQFoqmCd4l4rJWpzCYS22ZhNduhkeTIra9b2wioSbnscPIc gzmhjoqk1tBl243+Nu7cvmyMW4eGjwPX88EtmLzJx/P7Kw6iwEVmKPGb4UhwGgM039ZXWx1qkCSG oF+RHid618neFyhj2oJwjLIJ9hKlOc4ufpT8RuTBlWgzmvS1GuRg9IstpXblCAOHBGDne2K9e354 UBuf1LOpnCoiBWcORqKVanDKtknnziX0p2zAGFKazUFlOOllSlBGYV9/+p1IRDqwcfmN7/+mAu8d cJEkUb5dDBeoFObmfUsj+hjDarRRlb2lqpMCt+ed9Es2Dj7Jnc51yVRulAlda41oaYVQ/4K98nNW P7XmI31G3rwkmkG88qp7OsRb6t+ZcKmW9emPbSrBaiv8UDePMqdsC16m51DTnnti0OidoFOycJjT N2gB2f1/XJgzQVkNBfqLDhzY9R2Otw1R7WDnwWVz0YZOzlEhi7coulvbjbZ0pEEkF2XEht6gnt9+ lMzLqyh48rJfyVs5SU63epKCwIcn4WYXj/p9Vn7hJEvPej2bJffstlXwtkpptwJKHsdtOlD7+GVH qJvzyfSH/llcvJtetxWgKDi46FSMtsRXC4r/G45ln5slmP7kdSnYVAJv0PzKAcGNQqRvm1yd5WYZ t+Hj2YSopMt+qJjgaxRGCA/G9ecfclXLrZxAl+sCxTKoBlCtwWzYbt8B7XGD+HyNvTysQ+tuVTCA DRrx1jHJIgDHFvC0rDqmc4uctQ7Y7gIGOJ5iFU0QHxpJ9HcrMKeksIQwWnPq/zcTTvb1ZApl4pXh tcN9TjM3vKJoB+Wfqvcaj3/Om0w8Ud2mC93YdDBw4Gud5+jYyNfcXZWo+VT58QxF3hWNOu818Y3n IIy9HJzr9/gs1dW/lc6t8ff1f0srjsLDi3LLNBnqnpO2BTXSjhPB2LkWTiCeD9kl3ooPj8H7npRs oLnrYs8zMxyyC2w0OsRQaXjD9zBD5pHF70rPTE3IJMFkqPO47T9vzSEheEfVSbm0xMI7ldZ1N/2B RfC4yrsE6k8OQiUWGyYsmZQPbDCnxvITYPLRvfRqUI2Wp2H0LuhF0ZI/2vRAV6KC1GM4ONZMOJOl cAKrj/FslmoYEXoA+hQThxW7Sdb6ZLsszbIACRypLFQlAgQVb7MV24p1KoQeq64NB0jpf1Hw3b9o ZnGYPr5/d1f3LhPayYu3P5xUd5PC0XdebgPGwcSbj4QAKfTwybT4F73FQunYRaLnpRkE9ktKKFQY 7j1d76hTVopkjaCkoQV1B3DQqIT4jsyTVjA1QYz9LsIdOb71P54trub35kEOqcg627uSVsBb0pHp PEFdhS/j3w8mNjSdEkfhG0dVyqOJ2N1IlaaAmDMShe64hXp1i8jxpH+acNOs6wfJKVXDgORAnH0l fj/NVnE8oV5k8/tbf5JVUOJNdX9zqgfxgd0Wjvs3aIy9z3cBBk9RW0ROGZo4e1b3ApcdnZDxIPB+ ORqxWwsnGcjWgSRmxmyGLCtzE/x2Be3yyl6pbVyIUDo+7rDEJ8kRuIjzKX/22Z1A1n6dQiFqM3lj xiVsKjW558MbwQXVqpMZEaNdlMGuUpPMZUJsP3bFPb4uuxj0oS/6CrZMFjGP2wzrDmxkXOZNw4Aa JSGRsy17JZs/BEivdUbmAYQp3oeqgpLtx2CpLNRFReO9mGwk9/OsrEIU4jTtanafLuwbzGx8ABCF wQbZOL40C1h2j2ek7BY8E1r7287ypFGZyLAUQwum8yV9INdXh8peaSLau1zTXjjp2WvHbvCWsR5A 3qqZ66NhND6LZzYPnpvLitAfo5jF6d5rRRvrW21xSFQrFDD5cGkoPF6BVVf0qVXy18QG57D+9TOd HDcUUh4ASvFsNwCzPquqzWx1LRcFJXD/TIQLsLth0mIX5XLp/N9pAKnJhew+imDbBFZxeUyj8ElB xVb+fe5GvGdFRC/OMdJBYZrAqVAp7E93G/EBsdO6BgfeiEyXNzvfGSZJ3XJP33ObwyfJNkZeuA6z RUnviWWV5X5eHaIjrgjuhM8g1YJOCF+OG610oDlYDnKK4A0AJTaJ9gs4wpVI+FUYH/uuzts/zvdT zIMU+6JdzQscW9iYS+IOCI02I49K1EZYfjYDxl6PYlgmDkVkV0D13/ItCMz2UFr+SG+nEQ35CXuo yNeQ7dvJXN99lluha/YM26EY5J1ubfa/SSNCvCOPqV8o2xRb49E7menc9fQy7VBAHgcQzjuya7+x F3G6E9yT9F2Z5EMyAr7dx8iDoYm7c5QHDsXMnh31iTcbqJW9nnmd3/A641a5XERCAy46ODHJbTuJ 9CySMQtL5oXPL2bN9JliWIvHgaBDFI1ROWSXG9k42TCA/rAxp5B3fUz3TT/D+jJesmdiVj9QI9Bh yqETBTPh6XC5eEEHWm3Oh25bDZaB51xyH32bbtEaMcPb7Irwc7kPSrieOksZtads9qncIzF0isNN EbaMl1wROCfVfLL/JpDkJxZ8KRPc6UPNth+BdFH/lTSD0VEr19Ed82Z9v6ksAFV3iCoV15U1KePX wMLDwP/1sTtWcCHBnO65YDTTV0TFCme8+ZmHmo6uVFfE4f5l/OS0zkmvnwcaErR0ReiFFoEK6jj8 qN+Ev4BN9vsmNVK7Cdc9novs9NI7EcquD2XRVNpzx17MQUwLRuy7S/xTS1El0K485P0koWInEmrR S0FF1FF0JhT2umcCwrmdZ2L0G1061qwDqsOHPAeM8G5jZ5Y+/jmt6zvvVpxTyUqkSiYdkhK/wmLt jzu27xPlNXwiwhqwMJd4kSdR3A9lI6MKezV5pzVdLQZdKyxvp73fK0AiWVSEwKLR9RQMjjSX1IIP 6tBhbZ6qMqMyeUdFF3CT4U1mZhFfzEUEQ5lDPtJnKPa4Bwq14ZJ0P1ok/X0Q5FKEHb6z0iDMTIRz /mvkBWRdexxmEOXDg/Zlx0L8p/OKxCc8Gy4soD877ZwW/tnkqsn6EL0+NzYs6TlZuYxF/mP52piV r1pu55Eyfc+pq9hwrDLHMCeG022ecc0EuMOtarRD4U+XuRcI/p0skn4oopgLBgDvy6U97Ka3/TDq RyZN+uNzeAb26p5eNPyZnmRo+mLU4EQ/72zymgS1N/oAhgX9QAeFkGxCWPc6NAUMhosobSehmJYD W7JOw8TKua3l/n+ZQGsn2T/LGPo9THDaAeYRVFNqyV26cg9aAa1sj0Zd0NXWJPXDEWT6Ia9ELdOh S6tbmd15tRJXqx38WxwWJvy2+6bLDluqQ8hqYkLgzvnpQHpZEpfxYaK2hDk4mYGteKvpl65NARiv gHg3OwmMEz7dWNQYkTag8eNgHQptmMGjQG00oqIgehWaQoTZ2mLFlA3HLieRowVwsulMMHyFgN8v BxTJWTp2tkU7//mYYwVtY8AXf+fXh46eVmlWQ0pX5mPB9jR659hK4aFAKrccet9/Akim1Q5h/eFp e4SM0wv7JI1oPBJ/XGtOVXxijbAEFJjU7NWqGHgBFPb4fQZsw1EUIZzekQmwx8M8I0r96c+2rT0N h2YBYvFNnUCCQVsqw95m3OGBFs8jRXi2hflz1j1GagW7xUYFtGxQ0k7KrwsmV5NAMhUsZEWWX/4x 9+3FJN9BRYxDp7lRMDp3mBGkAIZWGRxiQPpVo7g2G/jaVIgPZ2Gp/s1l2dWBYlpraI7gs5EpgimP oKzLLceW/y6bR29mmvv8yBRA7pylA2UtXvWZJdPl9FzfRGylT8aE7dG8MpGzBIP3g34ISPLa7ejp TrYY5SWtlGgyysJqGGq7XfeE2D2kBtI33V2f4WczJs6FHud/eAUr/8D8wWTcZq8pTfAgpa3TiJxI cQk6e3bxbZs44IdnmEoq7Wa+sCBVFkEdReEnWMhXlux0yH7y1pQiR1do7p0XWmI/4c1XWUS9/Xja FSu+mFDrc102+8PChX24LRG7ps/KAEckey5U24EDe56u4hEOopVfwDJbatgNoh/7WLi7qmB1ycig /LeZy190ggbomVEdHjphet6fToKpWKoKpjs4tF6xMpJTpuIwnYySqyo87aNRhSsAmERrhJJgMO9w v1G6MbZ9OzFYJEcCcToixFperLKvaz5AbPnHpMBAytJqvzm+5x58YIsMH15TBjQjNpBNnFGg6PQj mU39bHvR9JwchsHMazs72VbWswwxzb84i8T+/uziMlMoyCvVTETRxsXLWXVieruFx2QEB6b0cuoQ rQaXugU7Ph5nR9Ib1HY30Lzy7DH8anhCHYYc4X1PQGloI5gZ6P4BNC/rA99m61pCNfagJtf/8+AO acKirgIStV39IGpCYeoUu9VvtL0X1waLonudUwZwEICkwsfF1YNogRt0GVE/FL+NgqaU8jMtkz3+ UKJCtTgei3wpKii7/3cwdP58XjlADlOFZ3S9PmHBVxsfM9liDRHxq21UUbaUIt2nMbOjgecMGoXU awuAMRcblpadzp5S7SGt6Ny4BgJIA0tGUGycrkOObYpYVSxw/nulNELkpoJS4jHbe5UlZ/Vj2W6r 4uds+HPvARfqFohzf3qAlLEiX+/PNfkS524EENyM9Is4XLcmKwlH3dgfI2eaYtwJA3dxzoIDOGhd 3/LtZVYhGorruftP10cMHrpssh1+FVCzrbmhHVjn06ZqGbjof5rQ8Ec29P1ZhaMllh2ZG6g6aIOJ pGmMXqtP/4MEEsR12pPcKGV1ihKmLGAmmNQMuqVOw2+a/UtDWflTRf//W39UgIXHo8BCYm0eA9G4 eaSO1e+tnA/9NJMBxZaePFn82N8ZkvLJXT7sgiSbYzrTjGODkgXGO8vNPpFC5UJExiGZG5ogcX+n R79WqLEgOA6z/NZgJ+ox+oBgxFGn6iLeFNknZGyK1UtJvBikPc1luWLQ1HEkteMK7mvVNg5F3SRR YkOSzDNLRBbZ3jkydYAMDkVMY5BwZ7u+vdj+mjGj/H+hli5u8DdcrEFOHdkMPFw9VoCTF7q1EVZ9 4wtWlTxXYM6gqLdMuZy+TIP1UFw1BGF8ho3CGUaXz4mZPghnzQX5ANE9czS6NBWTUHYZhE8DTVXu PhwomYg2qhegaMa8pwblfmJLEPWe4HCdNj2sndIVfoilUWtpQ2xX8raUTq2Fywcy9/tJMZqBixKV uF1F230fJADVesvNQXGBaaKA5YkoiJBDEEutfWMg2jw+CNIue0rDHrXpUFyaINq7c1tAzlxNak2R embtNi/t/zv6oMxT+YHuKc5QGWGd2vmibsPgryb8pRRvLcoGShDrvuH/XrCnpQTClLL1gbItoXq0 3/fLC7BzNmPSPmi/Czt964xFuxUmg4PJ++QafAr4JcsZqPwjwcIqjQWr8t8TVrwiH7MkjsEWr7nq 3e9ob2cPnnTblS3HrKMtkayeO7BA4X6aY3gPAKUnxQfBfgrSCBfjo/wHmm3Lyd+3PgHaK7akKqQ6 uMBXCQj7xQSLZMlUvzdTJKRMTPiKvcz2sMuLSU6Agf4IPoNvZ9uuFK6Ip5QdcIiSspAkR0ptHze7 p9HE2HKs9SF5nnC52XXRsdLuJO1gfmeUrEUVqonZ/Au9EuK1gqxlHhKo1IW3y64+KoWF9zyf+Dup KZ3yAg39uUJEyMTVGqHAzHn71slR69UaPPL0vlDPlBdT22wP0po8SD00N703Mou5b+k26GtvgzTE lvfWxgnQf31pSlV5v7xlkD3EPU45q7PJo5ahchCogPV9JEuU0xKNmkkSOfy38RBq32SbvnptBC/h TLwj9LbvG8nbT58OJJ653FfG15Ztsg+QlBokSPMjBRIc9BDyB3S0chEaD9grOHkQJtt28wXRLl0/ zGaA4+vu7yu5e7d6kOXT6Pyl3cbXLE5/X81kqCX4soEPP0bRCjT2CbORjOkNslKo0xCJTv77GC5F mr8U+YVqGwUyOwDgt031hHJ3S+CqeeTQNd4/EwMzUub1HJxSTCJ2CZ8XHeSrn30q9fUsKdIfhAEv U1FX+u3nrLM+ZBJ4JPNmoyLrUu1FVat/vIOD5rpPCuaTg+2bBQXLT1bAtdGcFuAd5fat5pzuU1Hy nt4ZMaxfW9V8uWdGdZNFOXvvYDefcq30fx0SRHQyiQaiDtsc25u58aah78P1M7ANIl10uw2fQ0XC gA/f28GEqs07FiaJpZHIThDLtLDL0txakRFP7DHkP+9DmF1tlJwVrAwK+pF6Rd7a1n/rMtmNjpJI bPguKo3DRooPskzlNSYgwiZwytd0QzfnQck+jYpQUH3cZ4PqOPmGU7dsVT82EqJZLyCBzDb2R7km +uOW+QOcaPosaBRPw8dCRGdnJiXsp11qNvx29Byj+wnNAtk49njL+7Nk/DWBUuECYXUAsCDjJcZx YSCBt6WOIi+umkOfc8qCNv4SJicZgU3SvAZUQqZNnE7Hxpyrb/+Sz2sbqrfeLhBM0v1mfYDv+/WJ 1yyzZb1H8E6GX+nTPN6iwLKCg5QtE0sfznBkrxh7F/B1SjxMwmYUPCPX8LsX16/XSxTS3dIZAQrS dU4BwZ330dDycXjkeXh6I+rJrGXqV+wj+r84yyXfftX2xDB7/JwEzNmDN25b0/+X4VIIVVyAeA/K Zi8LTHw2DYZbsIvGPk+iCz9wDgkey2di4fmvqlcrIq6d9QOx0nXahI9X3XjKEl7soMbohGrV2u5x 1xPeSosfTiRbiE3zz6cNCWdr4GRGPeWXb0RL3qfBKyFOX/uo4pzg0yvaoyCxr4y2yA3KGh/hlzJV lJTBmpVmGmO8Y6WfRtCoBsAqQakPXKyBtrnNQV2cOglzVMi6lrC+hCF0oy4xjWEDoUGkI8YTq653 84uSHz1q5oXonRxyVY7B5UUyW22AJxZX7pNmLyKloRy+K9CVQLs6jVM1VE3ogzkrnwJL5y1aF7o3 pDYROStp4R4jiaXZmeGO4deeawfpvLwYpyBrJRBLn4BjQNx8nT2k5uQmurcTEHkHrN/NR4tr3duW eKLDh3yLa2XoLW0+QgJqUtJV4DIofgabTxWHVjpSzDcCcMUYkqDDNqIsoT3mIUMt+gBuCy0I2piS EuuPDAtf5vEQ5UtEWzjZVWx5e7xiZRnKWNWWQ9q47VMuTPa+9/YdOzmNl1CgzU4xGBMh8iFRISno iFY6+lwjnhmmvaiLKmtAgrBl797w8KRir006ehCio/dw/tPQkyF0pVd765myCqw6TaaS0HOBWnzO dlUookn2vL5HCpebV3mPGMCF/FExDlqyuverVI5/Ikb+9VbOp065NW2z0TGJ6g0gvVs6otQFRNlG cUBsj1j8vF/xXAKG1a5gwx7n907z0mTlMk+/05ZGHUkvSFyK/eXt/ScgwOtb1IV9fAFGtyKDRThi iIeHbeKKRVxl8kOOMQu5Tc4i/1inSxsgow3uKbQQew7Ya4IFhZ6DNbX0ryGN2CFBOKxUpOYaX1M2 63fCXRv8KoAHnbLh9ljK8zxL/83NS3wgjCVpbwHVwAyl3/9lloQlZ269RJl5QfBt4A6AA8GMrHBJ 0YAii8EXTUIqHP9U6wURtxYTRgDhFb3HqL9aKTr0y5+oCVt60dYsdx4ByXOinKEI/QhwM9G4TDer 7pio2YsUMMgqJmmXxBQylnM1RfeoRSdyOnJuc9P7CUzCkKne0ktZypTe5XTu3dgPZA0HJvWNzLCo wvnIlqhCH+PF4R/nzptirgHLGzcM3VXOGRuySY+01kbg06HUsKBffei6nJE1vfpE2x75h/A8KrRw teMXukrbPBMqvkPv6ZMFkVZgBLtNcPm1w5+b+qScP4MYYFIsKcDP7dVcDPCMVW/VNbR009jsLd1i zUn5S09s2J5cJ0tdFG1an4Gjbs1tpQjp5EG/MPBvE2/rliXKnenK+e1nt5v4BS/SlNxBqmqHkEM0 WuXJk1cmgPmsWjwLZQHdpMrO2ptejRmsDlbxJPse0zILYJrONjD4OTS2c8C81NASCMYgXslf9d9V L1gwsVB5KyZt3AdnvTn55f5PE2ho3ypyWniOzSQpAlLYwUTF8yuv9Z5ie1TNqhbJ6xLA0vcIWR1p fAllsPpwh0kIA4T8cK/p2zEsUkBHhl3/MLmgLO/2rSlyXKrxHLIb94y5fRkHcnf+Je6brluBwdpy rez4qmbleqqrZox57ng6zZZRVWOTO6lgKfAcdvQqKMr6adIElss7Wrv5ruCG/Cbs2cQNQIQVQ9Cx yNuI5A7kaJYpaUcHt7pep5XuUizgrdu+sUorbLevlzbSc3zLAno662fl9S/mD+VzqrdrZfrW4RqD E6YW8NP1I/f3U1XPhBRXmocE3tsfci0Cr0BD/s9v2i8cFJCxntR7kmnnGk4eg7Z5KGDBwAPA/y6W qTdew0rQCTsnFOzyUASj82ltJeAeb0Tbv5J88F8Gztk9gkdqJGTHOvezQKnybYCiAK42EtXX8vnQ lx+iaW/U5zIpegfV5d14pIColdm9vNSp6t++0DyhRkdLmE6RGJ1CCg5ZkvFQqcuOcjf6czQyl1Vw n+GZ3u3yK7wwxCpMvLFVwtlKebzKfwcIwO8Mn8oc9xwI2zR4gk5vH9JL8qGGlCFOS05LFuJSYgRU fmbgQUlVNAklH/5cXwoXK0jb5myyyC3ObkSJI/BC6YVjL6M9hHTuQY94rLsMwfSrC6AzkArcVDFI +UOjr6oTatGIwOT5lNeGQIh3wsnRIeVZDeMGwPOaIiq2+G3zo0N4nmjdA9OUUNNGW5kYtYqtxJ86 zrt/pyVEQA6j/4t7wKHTRTGRLcIjLfjacuGJuGj49axDKZWS59nkGxQNkNkO2D3ok9N/evlwX4uz +VrpTvxEBka+lauEcHj/ljzWPM3me0mAsXaF4qzUuMSiazE21s1ekxBS2+0FjVt8yv1Hq0Zofj8O ZysDFucwvelv2elyhQnngrTEOMRjn4DVuAh/OV+2P521ba3dNMJBlTMvX6aGq5wPVtt4X/lcPBMz gtOZkeDkqTzpPh54NK3Kb4qww/SuHPthkfsKjVHovPPHEe0KFIcxvxyVQNIIsAFJsXPx2spJXW5S 93F3k5mNHZ7UaHcnIIq9uS5oUij57Lma2sObPbRi7JpYpHXaHgOybC/g6EAg4qlH8g/2dgdiVIHz lO1gVvyGYqbfPaGNa+3KoUuii3bjwiAxipatZh3vF7V2G9kg57QDmY6Oc2VMVkHZCcO+419tj3DE q1kDY4AKIxz5B2jPmSumAWJ7H9QhNK8lptw8W+SsDgKeViH96XApw/in3kmgEg9Jb0iT7/5YpUA9 5efgb0skhfvLNFu3JZbWrAJBUyzEk4ypfKndKRzhjTGMtPd4s4Ori09XCLhRKsNfj27bWf7BCNoM EygdgMOQL4dmZOQPFPThGnYotL0F5XoByRghMoZwH21/QLPOzVhZbt7pkmt+6COoxPJjdZLxIcRA Rz3gTaLnnPS1MhVB4zM+pARP0hWk55YDrPfd2pNko8T8WCvKGl0f8Kl/omRFxJkDYokif9SDhMrT 4f1ryHtoNHNajtwIQXRVKvT1b6NAlw3/1eZBrqLPyQ7qKkTTD+mT6KUBHq57HAkq8Tt4jg69qyVz 4GE/ret5bIwEIaBYw8cQYcurzqhcccKv9P28DMIYYkJ3/Snv9EKXlay0hLGBpmBbwJapEA+DMCE1 LyXHP+4wKd4kCt+J95DxmtTrEhxPKWSAbhc+r6/LWYMZKxTWH17ZVyB6SyJMZl4i9UFCYx/zwqHN 9AEp9RfyY6ZxX4vnbcLF0ONUrCm4D8LB3IDUeJPcTIfUYZCLc/r5MZK52K4Pmbjam0Ny3b0TkdRl FR9Ky4YhpDTEgIEI5ybZBYi2H6Ux3isq5gvBXN3zaA93WU2/ZP6ytecATH/nUFKXFga/hWk145Fm D0q/gvieLiXA//UBqbvW5FOEIC/tqlQdM59atLVbUl94n/9Mi8qTNaPgdp+JNbm7iCBqsT5Pp4Ud XP8Pfpp5Ljw6c5y0oRgmQiPfmCcT8s8RjKXA8f6L8A/p9bnspqAIond9Am+7XhvRYuhagipc0XvX qPro7VWD8W7eRif6CrxfGYFBJ36YC7+jVT3dhbqrd8uIIF0WhQ+dvTCC7yoRwY3rgP+IPCsus0Dv hckoeW4B5Zi906iyaA3n+TZIo/Nx1EkvPAfqCnlLHoVDAyuuM0zZxq4PM/8mZNebe6CG+uF/SpZV ubMFQ1Wk0rsvLZXNr5Sozsgm5kAHQoA/670/SJLFt3lXrLhnoNr2agbPMxUJFkRJ0KdwNLbhh8Xn IBjcbqzYHkaUYuV6oSqVS2v44vqODyYtXHOaWCTCFurt0hod0cqkxqbnKLJf3DxBI9YHrIJzn9VP BGmoAIPLAIJVW+p/KgsmC+ESr4xRwAZkIDTn17Jw+JRuLk1B4MKZhGwEIimmjercLjdN1pE4vSud LGG5GhGw4FwEWVNElxZv427TWyzbmpN/3kmqA1J4PFDLF4ermBMXvClZ1rrwrH0TKR0fuXcFyKOx Z/JPCxFDSsok9zdm0AUasxYwUvHpQA0BX+Yq0BLG3NgmOmhnCEGi2xRFaRsP12jpJxCRFf0fG+KH k4VYMbNCetn31Rdx26slXq4NzWl0IjO6I9uiYndG7Ikmi86c3+2wT2wS8rWT38SXGLX7sY4TSXeR 2JbOh9wdt/myM4wi0LzaDL82Pc5ZGou/BZxWRSi98UZnscH4SGZH5wnrBwJFCM3L4tUYwCLanGKn ALMKv6XZannoPmbs3yJs1+NXhRmrUWDeUQPlRTSuq1qQ8WJ9XMIh7b58D3YaOtdkHseQorjl2esN 3eAJPwY0jaZZ4nO4lQBL3q8WLcQtU+UYwnH6jWrE+PxjrgYRp/rxIyFS3yUj2JC1thwMGe72QY8v +OADQHHQqkf8/+FXS5ozJiPol+rxtJJy960mT5IY7yB0ZSk0NAkIyEYSeQASmr+coVZS5RfrDmr/ T48FORRVh6MgBQGWDaj7Mkr/ApLou+3sasfZii5gA5OCm1BBjFqYcsqfGSSo0N1X+U85Ld9/qAkI a3A/lmvLwMSY/SVKy/G69t4JF63C41WNBUR0iP1FN+KRwR+rBIWZD9gqSE/0FmDmqOh8qWXoeM6W LpZzICOQDDFLhFoiQuKKJBciqUflwluQ8I9DGl2Fvxg/WMGIvjX1cV3pxsIHwsFrbNRU8MwOUk3o KM9f9OqqQzRFDbwzkhWwWssheEVBCrtovhlwEekwjSMmeDEtLkiIhtRvt4pvlcsyaTPJDRNKzL/M soxvgNEqdwSEicK4YXzUBqkRykFhISfsDnhwMXpuOvDsIsXk2WEUDhL4NYsINBEDLcH0INfgJuuQ rifozBDoWKK3Rs7I5RTYQXF5aHFpGngOuCjF6kEJ6WCc7B3Vt5I14giFLKT2DV+azN5tGAVr7ogh fY0rAF5OoAnQLZrfEy18AwBmNeDEZ53n8oPChiT1ZWwecL9dj411syybXFAQt/pcy2j+GsZD06GP 8OYZW2wcs0Zk3+ykHfwEs/BPOz2robMgEhb4Ap9FETbfDCrH38S1kUI7GUm+RIOEQSSQcjLbylC8 0eF9CvOxrtb8DV8O/AYG4SjLV30Dc8qblyk8AyfLaJXj8OaBg2wjIHG5B0uIrZUUCWiHCp6Z+YtU LbVPFDQUxEUnQYD6+DoucwzPuN04IIcOZ6U2zQ2mq/OUGzS5mf3CMxszdwlOrONjnN82ZP+QmbTd mE3CRd2ndToDOo5o6XfX8ev+8GuO2EigBKWk3MakLQOFJLRPgcBHU8Df/nqdHLC9nOsvTePonod7 vl+lH+K7vEUGUQrs7zpZIXWjEUZ+9y2VAm/DKyS1kRcvO9MUhEEgLv4RON2aoe2v/EFBPPI1Qv5A Ai3S56fZL1Z4ATQFp4V8yTerO1n9CZ9qKAxCrSjfmjm8CqFtu8Ti68slWtrj3HmHG0gEhqzbrNKM wHYl3c2Lyd8KES9EIC9FEeZLcf4yv/hdUhnBFiCTBIftY3qvom5QC/PpnyWsKPHZ0eXrS5HNJguk 6BrACQkXkmvaQyiyGAKI7j05tlBpGtxmjlfJUdQm8qHZs/ynFTItN9tAH8TDXBNUPgzMTM7uBT1s AcqQxTuCUDMHdt7P8gsjrpass1WLdU79fwhlgtJTk0Akeep9DCU2EawXuix60anS7/b7Y5L0Eyex MsFuf0VQ1eQjrFVTFvaPbvJVDRIh6HL7wekWe8ShPA5or/cYlxR9ssTXgRdXYYF7Rj+K3Zma2vXc njic6LJ/4BRzrAiVUCCxsDOuOaV+uvtKOHc1cZDlh9x807gR6MQQq8sP93tPDYtgmOMiJZlHZEo6 0jhu9lJbNRRMaDkmbgntAgCO68QNChnFHB8XzH7VW7N6i4kr4vAFquK+1R1dPbRSVyTGuyxDnOdS bM0NK07S9pBKaqqTPSQn+qsy/YfMjVCEJ13TlkrCB+OGDuU+SaHV2/feG3liKKnvHtHAq9t+MTu5 VeACQeOaTkBdyo7656oV3sDhESf/icHJRH8KXWumGQroGicz0sJgd1n9TJfu7OIEwL/b/4PWOxRo ICp3ukMOyr87zi2qIMK5oY20i9xkJfZ++DlJwZNuzlcZmp659D8tB/LZ37VMhShl9KxnRXo0Pm/7 0y/5C5fXiCiRBCFcm+al+5OBEc17R+G/BmZaQ/KnODgiJWfQbaBBgX+49OK9VT8SQ/zgJHoLy9M4 EHUaIskYmorBFyE4pdKOl6DhZ65hwpItF7y5D6JPHJ9d7zzIOGrLGGOzE/VRmcfs6EAvUugUfKfE 3LPme1ExLbPcHZag+Qr4ephl2UXjJZK2k/oUNnzSakZ57nk4uLppGRYlFP5iI/MvdW5tFHW00w6k ot9lu5vPVkwWs4+iDmKylS4QRBOAcb8MoKPSZ+84M02lzTmZqsyDu3OHUIup/2NA1fH8uSKPGUqV 62uzLdJY9qoi23B1KDNWPjWHWFSLcsmompgOXvm/WkE9p1SjGUHilI/+b3CID9aXzxIAaCBfctA6 PFFb5WDY1MfYfOxOMQPMwPMSQR4EvCxgC3TaMvkoO8b2k95OZ2vYCLflEFUPfJLsQm0JW1aZxlhs zHKL7VX0FocDTnn0zu3oRoQ5nRSA7i9JQtTbZHWmcQni9sJ2v+4Uqr/DObbEq949+zx3xFcaEPRQ HtpGuZ7CO9nrVfefC/QhkKtjATSN1pfxFOPmaCf83aFRYpWKU+HT1UMjHbqW4ud7DrQHEPiBbghX DgHn64ToLnAHaLyajtlvE9dEZNKPlQzaF8tOsmNjXWjOkAaUOLamjbsPA14h4Xty/FGlveeK7wZ5 3BCoO39g3XAQli0+L7iXwYAIwB9LEx6495kzzmQ5E+48Q4TCSZ+g/WylD9S+i5ZRHKib+NhMeDh0 TgrGabZ7tpZYY82SHw6Rm08zrqY34Opkyji+kBsX8swkgltaRWRKw+QxcZvRU3K7KNz+HVJORefL 7SPwjwR0QzEFuTsnUoZRREAKx5MXl8SnfuME9ypNwIcye55idvdLRWn1HsD0MF9Xh6d5/CEnCXeY /uW6gsrN1iqKVpX+rTL2T0JQcKj+TyZ8jD8olITn/vU8GpXd/gltcjEGirMXUyAhuU1l0TtN02nm 6REK1SUbCPX7yqJqLWoQj8OGjmrWSzGNjN74JCeXv4AfXU8VQyGXG4YW+xainEflP/0qY/3bNw1+ 1v/VtSNSLAETZwtnetnYBGosz3Nh6W7u9qiYBvmNKixmmdRNdWATPlXnd8Ml1dEbUSTMv0A9eCU7 mDLoXn/K6ttF/M1RkK0VGIu/9+afj3Z6gQ3xm1F989AVj+cIQZIa7aBQI84oc81b/BqB9hyKTvco 1bwtEZ2KA3H3EY7xH4l2dh953ETkCGZb8Z2cJSuBEaVuD+vQW1fhRFQLj7L7taQA2pjFjeB0VH8g dutWwIlujE2k6wnTESV18iUh00+radmn/8iQ2F4I5N0QJ8jcCo/UwIUsjLkWCCTKIfBFD5CucTpg Pm1f4JmWCSeR1hWVL/X1U02D5zNBiE8ySshY0SxLYPzf34chmDl1d+fTsCOEgPwbvEulMNZb4Rci QPrAzC6NxWM9A21S3edgBniS3qSir/tP0hnPrcqEQOpqvie1HDB9C2Gv7XCu0eTF8Ff3rsaDKuKt JV4Xwo7vLucr5qFh701uVpdxhUFNeRATaxrljAAIV9wuqQ5lIx9fdaLirHNGA869wg5lcTd/rT0W DLNkk+zpcCQFUnz7CinCv+OTzbY5QCTSl2EwAOoqMtuy5VrTsmwpxNrDmvy3bxkQwSRVs9o7DAEr coRLxqkmgYo5Haropd9kWr/1tj4eWUsz0JAZlq2ft1hTyNFtg8kxQ+6hyOYLZL/G5tyRdyHZYssf OKq+5Du/4CgXvRGCfkeBYeC+jhRWioM0SGkAJpFVqpHZb8mGxh9hrama8rwpNfRwVPPJ1zzK6r4r 41JJl4mtSMK94WezK36ZFTgxY/d3gBpf/k2scR+fKVyTnmdf8oAHJxwaGtJ9z700QZQaNU15VkzM pyypqkUte8RfmKGSlsm+cXvOAr4lFKFKzRuNCUX9AKhZxyrMAUcunfQX3KUIFG5lcaZ6z/e8BA2U 5s5TBhebAP7gN7IHAOwJBr60UaU2k+FMWoQMyXN5qLaYMD7EugRPIuPp6ZNNHEwUOc306XL6aQQy ltLctDobQmCeMnDlol7c+h2hSMPRfdjrpSH1zw/PeRW1/LQBbwxDHfS7/2RXAfca3WE6y4xokn6O h/AFYaxHYawL8Z1gU90Ne0Jy4v4pk9eoCOYgrkFX/etmEKJQxoFcJtpXSTbaL6K7NN8OnXJwc2CZ UWISiW2eaGpXoNNvEiE1/fgjtESgJHbJoYw5W3sobOp85pMw3aOJg69/wpP0VMSDGcoMdztFzRuX UVAXMDl3ie8zDeSkG/iIgY2t7OGl6OC3DPt+CIDnWdK9jZG6C3dcUiQ50k+myN1Zf7KcVoP3vrGi vzcFuu26xMxQV3IrRnOVNHMflS2TQZhzpmvODAiDPiZyj5Rmbqn7aWGDh43LguwQK7IPKjrBMjY6 oLzs0KSfYOgwMnBDRtrRIdevHJbMMqWRt6R8AoTJK5gxdMZEG6nOnoPvdZD2YW6wjHGZ3IAhujsB RgNp5Pcyg0Wugv7EQz+WK/v3jY6+TC7QTO6N3HKqmkBUMZgIlVJI2qglQgm3yCqmifMzmHf8MU0g Miwv8bC1vh4vNtqV8crOWmjfN7jwGHwlgELqJXil7lhjdMh5CNa4mD/tDNBDuIynIGyE8iT+EPYl Crsw9rpEvhB7guxvWE5ZoVBNd5HnOlQftkUGxAwet2u4OqHT+fzFEWx6C/dwdzkWru553w7QVk+8 t8xmO3yQ6DpITH/b0jeaKM3PyaXP/0KHvHIQOdNiuNy9goyN6gL3U2cc/5j+F7PVV/SPv+O6YSk7 8xe1h1W8Foi2s3Nc7vCH0H84oEkZ/85x+H+KAvam1Zx14H205Hybxmq3RKYkyvtfmH0QjgbxrMzC LkLlRBrxefMg3ie8WsNi42si6zopkMMELsJDEUSjRW6TDEsXNl/bS6bDhvUFe0zSeW5w7BtvueK8 R7uDdtqSCrcWuPlhVnpCYW/EG/cut68TmgnTdVaotjZLJv6DQe6uXKX2Fvgr8uQXaj2Sc7ebvRAd FCVZouH1KURd4a/0KJVkNnMf8VqYUV6aT0LHzHwYWL0RCCVOxyZy/+699DxoG+VTm9Ltzq78PtSW aFpvlmZyq4d+a5DXyn3Hzp6RfTGpT2y0DKzWEIhfq69wc4VNNh7PUBz0qRjRnk1GRH8z9G5rU/kh WuMoHa6U2e8GujvqjAtMMWA9CtsZjXKlLmbpr2SEQgFB/DBqyCUA9PpyiCwm5Awp2fO1ZPEACvGI xvedH7jFNQepZRGXOChlRhzRlx2HVLVyp5s7GDBdsBK8RQsOvQdn/NvbAGHy3GWFsT2IvIvtEHmU I/3aHs89+hOiE2Ru8MDWqEtlN9dSzcjavaM4Z+tvytDvZnJpzMYLNrDm3Ekw6iDEs7892C2ZULBB G0ccl+dHE0iwMKbIv7axGJjYnDSSEaezaLU0ZtTRFH39alzK8pHcfp+hCesA+JSyNhR8dkoqNPEy 8y4KWKgTDCrwAUdKrQOA3S0/PZc9ynD3OKF022jlL15Uvsk+AUfN6K3qYt/ljUtghAuDNB3j3OsA McafVo5QY7zb50BjXEZ6+DMitNYzX7xzAaVvv3mlOaGXYgSQSMTd4mPFtkdLjMEMrmA6u2DJMOn6 VPrMdjq4O4IiPputFLEEjbq7zJg6Ko6fkdZdcJqjB1Vn3+srHcnFo9OoMjipJ0jLOSrqhh8tIQZ8 dH5ye2xtUV+jKcnrru0vDVufrXU6GG7VhCdg6reWsOyv6XMP8ga/UHRNfGj6k5jJK/qm4HTArXOK QrQYrq51pB1kGym2Db8sH28iIrxp9URdUD5FpjEYlxpFpCm75ki8q3HGGHMu8xdoXgoZbycETndd U+KcDT0ac3PSh51e+gQMGB+wvvSHPOQhZH8va8PoT3P0MZ3T6+SR6jGAiS+9iOMpdk3a2pPZhZIS 54WkU6DgWxWGTfuRfpNd4LjJBRnGdlAFy0yG5zY9d3Y8h+w9d/3TjWir9mH3m21ZwELfaeLoaajg TEvZslarivxfvYMoNQZdY2caxC9j/RKwqUVSN6CTg1u0ao+pnIqIarJcWxhX+U5H6dH3rMYlPl5e a3AyqAN5lZxadAfabmKZ1YcYpEwojyzzM3z6ZZlCTxxWnstyjmdIJkxQ0VuYdw/eeVY//ThntbkZ /yUaNhL+H3M0V49vHf9F8qf6U+O/sHsRrFe2KQcFiqXgf7FiY4OlUPZcOPRuo7DkLG1VCBUCd6sH Elqi3B7ronFIjAwLyuoT2DiFVEgDITdNQEMNbfefnI0zTtLXuO2NFZnwC1RDQSJRJbd/tS27d7zh YYBPFaw8OMa3ZXH6GjewiNXHJpuYOgtFBeHPylcGHpYK5aEl3MPvTzauy4qSbqjc+da53w/vhLjd d9TZAINlDt6ZtklY3LF6z949sQlxf1aqq5yTx9nuNSMJBzQB03DK1PHDERRbbZIVjrvWGSxN9Wgx eNMXQ9QeSmCPaayRoHW2MTjXk7G+Mwh6OEJ2VmXMUo5peyzmQDhSK6RcrIo4yxs66RUHOU8jr92r z+rbDIqfYY15HNQo3pl6eVRhQXlbXgB65x3qrrctql2ZeByswFm/2ZB+hbMmPLdpLEIwLwYZr30H vMAz52aDfVW1HfYd4w0tZAZzFffpaVPTezpP28jk0ANxpMwK0CBgJVoVAQBQdjsFXsgi5k7mVYpf o9abQNjg82puHEYgpK44cRZJHlKUgYr8FJaaVTJ4264GP29YOYjK7hBODyKljovt/0Rn1yBe5I5I UL4H+O1PNACEyhp8Fxa/DFnTlykNHVTEFIrv4BjpHVCiQuvBjVqtlc3BDXm//c1hmtjni/a3Xhxm w+SVx+RNwa9Kk1P7y1y/gwhRHFskYsJBtXRiSuYDcS7Ow9laqcdAytPjfYyxXvC/NDrqsJYGNUVQ 823hdkXvQzuIuCFGSZ3nOgk8Tn0fs1xAocO0v2QlAikGLpx1xRc4g+RtcLkhp2LIkP664z0+9IgY IB6lEdDMnjYfdattj1T/ArR59FaEj/nyusuMTY3egk1VKDDPVTWEPwpyi2h1RvFPSv23Bi7fm0dG Y7hBzOUTuzE8+xjNUDW5kuQ2w9/Waqss4o26p6bvo60c0ENfidBOpMBJqBZCYHJmxlHNiseVrJpv C/dFPnUdRGUbmrdPlba/+Ez4gikk2Hn4/dE6o0L0ZeWCgiEACLji6mlnNtmPci9zCl7D6LU8pcof J9A/dQPFKsN/kTIiseEooDgQh7EnWzz6kDoNZa8c/fmiUxIhHSISCoRwCSRmqLE7Q4oRoyZ2CO3R omVwHsqU8dxSIupMGkXbkK5B5aS9VqWZy7iemvFUaZZrKNn1UZEjOL0ITBnNbI3UO7TVTsW7cOpn TPiLDn1ViKF8tXACtkx3uvblRcj3OumEosj4gPLr4FVGDJCMq87ol2Qd0u5P81niwFnl9KOMN6jY AGz33GgcRe5RJOgc5g6IcM+EZMSwSHDLlx4NEJFiCXJtlMOdRzMj3mK8WVktlrEeg6+ZxJ5qcU+h K9PlXH6cjatLb00ltBctPzRHFQifzdi7y0DEU8jizCn8da0= `protect end_protected	mit	af4ae16fb33be0fdace808a6599a3885	0.9521	1.81974	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/builtin_top_v6.vhd	2	52,905	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Tm+pO9cWjnP6SGHGIUORi+Qy3ZPKJPc5Do/wldGLv+79HykTzAUPZjf0NDSnxG/NwyDyNf1sRy4e 53mlcC7Kkg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block nAe+7S9bIXjryeeLTMUBL+JHgnMEq0jcRlFgKILMIylhACCBGZsF46L9wUs0Wvv7QjDckMnV5HQT Sy4NgPjocveCUApkXfjDURz7dNJWr1XF7aBVWWJuZIG3ziDDcBpQm7VMFPSpmvz4KLmzeCmOqVfE 9ciHLBKHk7X0AHDS67I= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block JLesE8QBzw0zGuRtqT4qUSTc36KQV/9psE0Rh3RGZoKfFjeZtwU+SPmg7MX7kYJvN6KPv9LiAYuz w6HvlBzLXNBLCpykgbFCQ0MNBUyv9uoWSrUAXq6u2FpEUSjMdR9658e2LpdGAgv5vcby/zuTZmS2 OayDLc0pNuPfa9CwE/dgGThMEkeBWllWFZC4XNk7Ei94cVR3PBIZTgJEst+k8dvafZAePcYSflZR pJgku8OFiKG5ZyBPQQ5KWNteu/40MZKu58bjSLEsZbJaFe858QNBv+e/jhh7+4jL8y5rOqdFvsFc wILgn/xQ7LZjnt71MT+0FVdl77P8BD0Bg4p3EA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P8LDT9HXJ0k/lbQ3U6q0+/gfU7N7EG0VXNxAcHSRxItrj2iyedJlFdeK6kiE8O0p0OPEiDcPwJHc LFXsevGlBGQZN9RT8LepodPQWFyAA2zMqyQ7Jp4DgNUvDHPIdx++myw9cSGa+daXyarBv+dJg0L1 FGYoDF9VRBHxOrJnTEk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cWHAJ41oL59SLCBUSOY4SAYDh7gWLG+fAi4FllcNcSaPYRM4Y0W930vlcWo+455Vjokd3MJVqRol nk5JPY0divTkOcp0AJzvkI0ytTeHFfykU0m9CqEhPHszQE6Py3SnieX2mrtujfLK+j/hXb7a1RJs YumlE/Y0fe4jFKG063TPSwqnPbvMXimQCETOWTij0tGSzfghJNbYdk1vERfwdjjYTzZhvq8WTuur STYGKOoIxxoBhuTqITTBga2RT5vxryR5d4qLN3ocoF8Ay/s+BMXqMVEqCJe9PPJd9gVlKP6M96I/ C1AiSDaDoFdrhcG2aOR3Vvlx20/P9McsOkvx0w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424) `protect data_block KXAbWy6Y3kLMWJ9C5pGqRplWc+sj6rl25TzXO1OcO6pA/wq4AVJcewFSFA4o2sL96+CGCcEdgMrN QCjXi7dmSeA4wfkG0XTtbvy+2S+Z2JEscOiHPdEmfzfAyphmFPhkiNYB1GftKcUOjI8wkPgvaeMp xKJVv3xOzvrgz3roNDnFhV08fZLV1PoqVGBhmfYA5HzXBfUkFmkITAzvnzB8gG+Id8L+MwOzaGra j/dqD6nBcfxBKxJIyLm26mhBvbo34VpvvTaSDbh0zei/OG2emm+joHpzkQ9eXlcbwRSFymRCjuH4 3S/fA/eur1fwKLVk9RuvpxHyBO4OpL3gsTvkAQS5MIiwBluWBojNRguRUlr6g4Ba8kLd90hUnupF oRKbpoGb5jSyr9sk5QYRCGoNY9rMI8wKKG+I7YsC7vktemp9X0/DlCm5Ck+S9N1/TWUBdrvepiO3 urcE0rm7JzZmoaM3U6iFWYpiVJ1vqhAYSTL2r0nZR5g45kYDTf3bC0zgTG8HucGh1wBKjke8AS66 BRIvrp/SfSnqRrT5c+gD3tat9AZD6WTbnznqCHFhhcSa6GNlslhWZNQQnETUT4UjrgemEHcZ+f8Q LZa8/fchMUirzlTfxs23O8dWADfXaVQasD49oqYtYbvU6ybhYQw5DsoVHVCrXZbnTvealiQ0kVj6 eFv3bYdlNU5Y4RebEDFi5qFreuOxrxxfraNKx1BNy4aqlualRq4RIxf0Eb+HpBk/pGzpvqPJUP3q 39limBXM56jUd//51HnnvpzafjJue/nwY1Tm5tRXpKuDaNzzFb0U0ZBiUiZlucbcEeJDiYX/Ekrm DlAkkzEIjaG5tPRtk9thaC+7noiX6D4Q+b//m0EI69MjTfDdPbHJr4wvndT9yCOSLezlR0nC0r/O iIhW9DJOZCja6Hbp+eLTzZ7DAkMj//3zmyV2BOAVoEpGQdYpRloEj/jwzrVjYLM/i/jTU8eO+ZNr HBt/sPKZ071kBc05TaxiHdmRFhgLyTWnBlnAM6VqtuFkrij3+iWDf2eN9w0p+NC9ESSc3BEpqTRh /g5b/tps4pFF5P4bnDjWX4FC+X73VToIIB3gkSqQqY6xZdAm9T5R9Fy7JrIBKu5AhPbcfueKmEJj ifVHxPfZddb3U242hpplBLMZ/Hz/4l/pFZRFZ45+JEjC5eVE896mAUdNLJ1Blu/eIfyx4+75SCss nCP2JlbAhTmJKlGy2Rxut+rdKh8V/rzTFDfKcZnpFVr6CxGSNaX+mp9BTxeq3bQ27C6Oty0EMdTt HrEjmJLJxjxAEn4Uaxjaso49BWiIb+HW5iHZsl6Y5q/o5h1ccig8vL1DxoQIojF3xT8vUqWy0GzM 2ZMAbf9+O2Id1k3KSYYC/EqJTJcO0XMxvCbtb+Hm7T89CX9wok9SfvvgtIbDiG+Tvrih4BR76HH9 kAKrBU6HqLBkVUH17JS83ckxsZb8ASbFLpyxk2UHpb0xK+DJtsnV/LMvtScr0uHjrLOnSxADWZxa PsMf5bxtwk+gm/9AmPEqZRsuUggzceMxE2MZdOs+jOjjtX82JXtHupqHCO9hEh/xyo8t9LrRyh4j MyWmAPP/OUEwmc1vLTBdE8c1lO1ViXqSn6EiSFpHw11yrku13kkn7ikE5LwxndYXjfKCxlj5HV3X IQCWSz/3t407xeJknkSYXe5lv61IN7lnUZX0IpaD7geRTg3HFMVf8hoZU5gmDQDkgTqpqU2x0aZJ 1S4FAfrJ0/qpYmOAjP8QLD8Kwqso+y1dwhlsappl6yenXJiW9hesJ+H0VzukCizOJSW80hCHBtMs EyugfAdm/vcT6Eh1ac787dG2h5PSqDWaFbKJ63VAdSFgVUYVHZfXQ7p5BQp0HG1bsqVKu/yGp/mm B/ndRIB1YanTG0q5F+2rZ/0LRe6BoZCBAn32dW4LgtKW/PY4/tnU6dQoDzRyB2mLxaSnhy4I1e5v ugPGJUlS6DY1utt102lHjcVWb8t5q3eeK5IDIgzGTZU/a1qgLvJZ+XoWms+EmyZgNaFWmzAlx153 OgjUatydCxNXRFm6mm7ifKL/JujhTXEQPIBwidPVwYVuP6GKWCS7kmmE9RGWYX5vTrQQbgeMwqdW nDC4dI2ZTMIStw7GlcXSyQrJ+aH22Q8tyL6mNmSPqm6LeBpWbfjgQgCiuCDbunMk+mchDuaJmVI2 DEZjKfOZG7p0k0fW+mf5qtHd+F3xxjQz/iXYygGXUO929JXUDYc/fbKNu+Om03RlGIc2e1SQYRvr TB50Q9i6TxRqA9vtJjTkEhXKpHQKmcMgabgBzh3tV/h52oVWLhqDRxvWzKI68x8O10E1cfF43+HP qztiWNWjQKhYc2yVTD4J9n+p/f0epftCHyHqAZ3Ly129mGdvwSDnP7Mjbc/tCdWCU5onpfRCgYZg V1O5w4LT/b47tIx5x0QwOaItI+M1E6d/F6zn7fADmpmTScDbI9Qs49r9DjvB28EbLDixZ8HuK2EB QldBWQSmwX1HkkPkaHda4vgZnTobLJJq2D4+2P239dOBsMD3r2uxBwhblsHmgFr5aLNoSfclGkyS k+R3yP+S7BW5dqfFEhofKb3miujwKa/9Y0/nS8qG2J0CnMlpg61xsoA5VUHCFVh+ZUo3084h6WED 0vhowrDJN1CCXzxIxpcXq4TCVs7VUh5Gbz+4CmI08yFBs8TIb67a45AqFUS5G8FVOxOmlrh8vmV1 cSB1Dz2T+vepoJVfxDU5gvrQ5sA3baVkVbqD8a9TEvV2efGIzM9RZ8oi3ij1PMpNiKY2At8x47rq fPg/AfPb1dCGU3zmcAxw7bz6eWIz/yJ/TMUmTBlRsdKfpEZPrRNe7fDquIWqHoZIH+3rjeZ5vlQu 3TUL9eAXuRuKl0mFq4I+3kmEX7aXZpvYvjQbpaVYcxe9u7QwLndgyThMIozAL8o9Q19b4xJtD9Ke 9V2yb0Qen0XZjap1ExksYASafRPu5Wowx7DdSltjkf+VCoHv01KflhtcmCxswSVGFhyGPXfBEj87 Qo5qQ6kK8Be7C5j/oSPpEFMXiX90eyZ6qJOZ+Q/kQabXLmDHTuzK00tBlqExoTFIkad7Tq15Ooat 2uQC0Uh03tYW0gJPLkJAFAm7HomJrueEPTo+VrK+WI4Xeg6G0k0Mr0lam8Qj4+nhit85JUy0hfkl /oo76PRwgvf0o2ZvIwnvsCk6Uyx0tAfXibEN/CTZm/DoTpR+B34owwlGnahCh741RhKxeom0WxpF HA4McY8CpSxM56FmOgf6e+6Yi9MARmxEcLUwvFzNj5P7w4ttWXdlf4riBfma8kHQI25BIfRbUwGq SnCytLxY8qbotZzNByVICzoTD/XJE35DdIbUtmhlIadnpl+WuyZ5q35Lupa/KV6pdSekngAyQDV2 2vIF9yzoPYuPneiNXeOmjZo/bn/QPMXe9dEH+0W3oQCrElIiXKs42EteqrKj+oUwN0zbFIkKLWFz 9XzulCFn+XzNyD6c5BsVp7BKl37AzZF5FjqaDfzPMXAjkvqr4Or+XCSy807dojeqVpavHTr+YwsN Qouj69mD2W7iJWGNvDDjLs7xEDT4uMaDoPqC+PhLUtrMGjn6CpQceN/wpQNc8CJPzmAVwM+RxJAV UCVB3OJsi+Sxd8lkeuK8wRYGHAuCxj94Kv8t0EaXXp5x0B01XZSnBjWlxIJNiEqIUvfEC5R3XV1F /xMa1IG5NdilAZhaiEQzwjOmIFR1IBFBW8UKRav5a/z63UkIBk8nN9uEwhedepNE9PtKBofCIWTp mGLYt88Aj16NY/nks4EID/UOvCJ1rZ968IlGnSb5odcVx1/TkIaiAiCrJb/P6PtWgdgUCYIpFM7k kRnd7Zn6EeX/blfgk/vD2HWYLDSjTpHYh8Cef9+MVBk4vqLSAZc6Ha7SGuAM/lU4fVykeN+Gy4SQ XgUE9FVSluupFcnNKOgzXDhae0Fbcb5rfeHSdcYJzKi2EpPAZswQwJTbzw8upsFIJzHnlnr4FIPh K+FIAxu3eWUXVoKkfwYAqEaDpu4QsJHAOwrgnUZv0DD6mrZqRQ+jfAYSGTyv4981JHndwVX+g1iC 4I02jJMt3rIJXYGAp3G4dUeoVUSzLRo9yDssfOhF2RVnSFXV0YR2sBMEh69vzOSLpLSSeABOdTjQ 7lnz3IRLgbIGcJSBgoQvkXvq4aXaGhhX0KIzchYpfy9AVV9jz1ro7w3CSR7i9iHhV4ANfvaEYZ22 wznwafHI20b50VZnvGRAC5TrLzHYHJtbCUb3r+UpxYdTuOxmEW93mSRsgq0bmAgrRr0Gio1Gf/t7 /H2DxieVrABznKP7HdrcYlJK0pUUGTqr1JY1VDSId9w+QHM1ef2MNv8Ts2ZZLdltxmMrnI/LLPP5 q8EmMECYy084EGl6jMwwFbaBL1dzDEg+5xbMJT3BJ7XQIA6FXVIih7WYFViEpAABo/2zgHN1wVp2 2yX7UaXIBuut/okrvtc7CAY6RZ9TlGdrwX8G/Zi/mFg1vnrY1Rym3BDIiBohtUYogJsKXhkp/fVf 5tCYP7PICqHHAIof7kJ5J+6Bc1UeY88a98QGbPaKkrOWEREHpNJ1g1mGRgeHV1dQCym1TnZKPSjE R9DaOaiWQXKyIiulTW8vhzRPICichr8uizGqLDJj7hHtoHPFnjJKzdyfR0VM3ieVY1fvgniZrvAy pWTPhTlEhfjfdydoudAwYbgqULSfuwFemLEReL7jd6/v6hSFdNKIHshx/GRF19CKKoI4sEKcoHOA WAHhWx0L4RhoMqUtqOarK6JCMVGrTvr86KE4EbIo4xM6Ssd6SyCOkpy5sb9Na92OXdU7k4zapyQw CpWQRsnHeeKpqI/lS/IhgqKUJHeL3aBqa1f6AD6O6iSeX77/34sqUAoXQsZq4Q5igroeLHJH/4cc bfnHOQO/wZOGmcqxPWN37DlpYQSzmecha7R5xRUUve55EQR0OVJSAi8EOjAeaEVbBQL7/lvNtdPm 0G0VDyXULP00DOznTyXa8ygR3QY6KEnIrBiNbkE3Aie4pdUqjnPoOzAuDEkoIdANiI4UZM1UgHDl TjHZk7ZUX6SjG8mls4GROUaI339tOkdPgkVKFqsvTL7UHMpbDBuGFtEX/ZSf6OPqgmS2/1bNlDpE DBXNzFlt/lE7eBqBMW1Qafm9iUfubFnufgwqEe+jYbpfzIEU0hCnoVZcoYcoYQOBk0wvVsl79pEh EwW97X8YF621XF0lhgMvlotFwvSyqcCHgQL73xJRHTakJZqVmI5R2eUq8Xc48YcW6Y60BJj6GZWG 7JcW15CWFkQXJr9e533VrndIo+LwA7sjd0+b1aKES5YjYDeTW6Hf4VJXx+XOSBi82S7y+bHJXKes gdWySYME1cnMX/W9AdBnmrMNLUs7FH0kTpAFoBRcOczz/HeL4ajVPAiAgNPmaKWpGOBRV42QeQL1 Xz8ge2b73FYCwvY1G0+rCSStJ0UajKTBO1UnjPXpuuG3ZB0RggtLg3yoQ05zx6U5EFLAAx9EEwXv pIEET8iVoX2uuc/P0FGacsLNU+uRHGDXagtDZO9ICgIm4wk3v16Xc6k9p7HZb2rGVUtAYogbTH63 LHhFhPhS+uLBDSPprhTfrAS+k29nYZgpG1IWFBFZH4hNguvXpg21dqW1BcvDbF1SDOQrR7qL+y1d uiyi3ytR+U8ckkYh+oIZn6x32zxLqw/AWgKmr1Wd+OFFDTz8zgIDoVSLJzwPS4zuQLaC0o7MXvjA kBO0o+S1uIIhGPdhBSGFWtUlayyTpw6DrFJYEJk0xZWNKm9iZY56xIZW7v0mkxksn11PRTzZCq2W 7+Th6wdmQcvEnIq+C0Bk6wBSJgeq9KHEGBG7RQhUH23yZRaT7FmYC4xAaAsRWvfEsXfvdwcMJc0P UK+PDuXysZWY+WM+6aBAT+4+fEr6r/n6ZdgInfmCWyI/OFkoiyl8q4PzMHUlP6BvdL8ge4/ix21S QQL7XhYdUpQ/GYdeYi34RF6C+GYJlUkhp0In6sZlVFptBPlztoLKt/Iyux+4RZ67BImA1hjlSXUs 6EbfkytLW9uyaZxlUNrC87CNPYrWmXU5S+mv6rzAKLyY5ONuDYbi4WLUGqTiiQR7wmWbOepxTK2G eCHFw97JpbsmJ8M5IuS/BzHx4AL5UjCmqc1UrQ7aEEy2rzvK8EXRwDQdancmOdD2yuSK/LYGkfRk jZD8FgSF1YPx5J+Yg6Fsw7ym0Dv73pdMtxTS1Lp8z9q0zFN35GGI69YJvc7D1/cYh5KI6F95v5cV H9DoHTU+MbG0K/t+zkSlpd7hBgM1Vl2v4HjHHhqtW6/uMi8BW2dI1ZjPUVnviy+CxP5DABTKl9sh r9HThUhTD++YSNzSnJWm6iEipfX7BHLfLvDr9xP/mkZlV3FN4pUsSRgGyekU88PccI1LnPmLwT6N YDmqCcniUD8kP5SYsiOJ97kJC80eNLLo4iMZHkIBwdti2dKi8EC9EoBW3/jN6CH/LCyc3SZNFvbN eQ7HRbxOzKy0f/V9us/2h4IffxGzJq5SCUZy55ItDIK7HnlxomquApVVKmFMoFFsklKSGv1rdf7s KnjgNMleD3oeunA6F757S+5Pav1nzrHkba+AHxheLu4hRDV+gyFyYGWqtzFb/95SL8UxCPZZRfmp aNbXErNEIKG53zapo8naSkK+sn+urzVAGGXQezyEXxRtT+fqHohnnPGbeDfk0s5DFjgnibgFUmCi 82TcQ+kfmSNUnRnpijeZCeCRXXT9fFsZFkvfFnL9BaTY5B1Ji0sLDyx5SotV+sbQWu8jelkWexVe QLL6zmXOC/68yzTuD6UW8ygeBhkdpq8cauL2jmc1VlDFMzauynQ7TBUBHT4ULKhkkMa/W8G9Hj1Y ADVIIfFFuVwBIq/EnxMt0DOfOLWPI3+gWsrsS64zyiP5I1bDym1I0k1LNLlENJl9sp0er8Kljfun zAGrQ9b6oLreX3o/Rpe/tkH8tUCzEaxsFf2LHjjXsJ18aciPBIkB3HgEEO45r8PN/vDy67BaOCgb IbGabCI6lLkxaPxnehRjCfs6Z6wb9QQ9+Gnf5JhlYV16szrRJwhV/La5Hy0285ajEbn7+bNVT+Ua Sgs1JFBhAPh57P9dKKLxb/sLIsChPLJmLQSd6P3pNPqw+VsM201XBySPRSOgxOStlXYOgU3IgONq sCLuxoS+Ew5J0OSr6I8JBey818acv2UoYXGRbG3Z8hrFSEedDexD/nsAdITm6gAzByVjkQ1IsqyF jAb1JJp+Hp5Bwfo1U+sTseNOKRMFUIV9l0X1WZ9wkd5ZY3vYSIAZCrk2L8AI+UmgF0qH+o7HKT3g CszvqzKJ9JjcY1BrUqE1h+PFzp/rFyv7K+rXSdLb4Iv8ipvL81MtH7c2Kr/njUqVQsihevng+COx 4/pCah8MMMWFPPMjqIDQf10k64pUMJ208gjNN7O+j/jaxHfS+QXYy7sZFlNEW9WRv98WbsqOSdb1 lkuyRDSp+jt0XJPukZ9V5L9nt3o9RglyYf9stBB0xSJpmby3U2ScMj5t3hBkPqHXK/HtK4823ZCb OBKG59ABRKKxbneASEMWowRPSXUcdpDrhAXZ+rJ1K5zT+rBvPurRCD+cl+EYcjmUC73n6j6Z99rM Ao7l1bZyq5SLoppDPB0HGmI2g8yMZO7qyAlqjTN0E/rg7Zk/n2yrpTrGQfSh6q47FXyr274vgGxA Se9EXWAUGxAiLDh2XCmq+l1aVihxej2hJLZrey8FKZS7khvZZ55ci7P/c3CRqHXrquwainrVpkoi u8TJ30FQWNBJxabr55Q4qpWmwfSk6DG21GVlpfupjlBIWe1RKGT5WdKICt1P6MqwSH+6/RIHk75T c3RxE8zXeM6XuHx1y2Gp2/wWG1wSi4UlcZTqlgXP1KoU2WMHsyE4rA7geSynsZb3TZrVyvLjWC9t CS0AL48lKC9jgWkkUsc8dGNfrguso6Pyh4NzbTjd2cPMgAeRNryPMNJwdNvL691B8QwZSEU28vCq jFNolxvd+3uNFUWPeC0B5GtvAzVE7M2UFKlYM0gGgZ6oVYRDML3MDuHPLJDwmjsBWWDgKaqDfidq KDaF6+P7dgD3BMJP93hXTTxleDg3YpWMv+cIAPClk5gIhWAQPM3kBMClkDrylppd4GCPTbpGicBJ UYnV+pv4PeW0ZhbYSQWCDzedRKd+ZXVIrbNBfctFW3bSP3sgxFexotwR+2ZE+bUV3u0jsWjiHPbC PyV4M9BGEKtc1ckfOtpR0S1TsdKs798spsXEzNRxLlrGKztjQz6I+eOuQBliPyJOfrLidsPdqI+K hx0fvOF+gTFrlLmWIi5Q0SVMTRMyVgtBIdm8toz3dxRoMMLH2bLT+JLbwJcDivXTHM5ZNX8i8Pd9 hbzDBqiJ0d/Y//S1BufOZO8kAm2A9SUZ1H/qxdVxzd7alz3FO3ZN1mAB7pTE7BOItMC09iFQPwkH jWWvOsngSvIceLfPRT66+6UB2PtEmK0jhHjoKmW3wmxCSp0Y0aJ6FGQpBPUjesRQzCUI/5ESFKDj 5DWCeOLqEfmCHJvVyjUzNQ1f2S+pcb0Tih7Q8uIaUQoZJfEJdbeb94cGb0MJ19/Ln7AxBJRve3Hw sWyFEjvGU0A6jzACBiYorgzOWuFQuvuZSwV+jdj/OKOGWm87lp7l7CLyb2TVuLpKkXQiE+xNwI5b 9X9VEXS0MkOzTubZ55o6TSeSraBpiUTyK7nD9MHZqHDbmYOUN6ivDFKURTmMXBNNnnGuzzxff5JY ddWMx3ABTInW68VMnXz9XSn+FrrlpM19kxip3BKa2Pk7nG2xJqcngJdIJYiCJbcj6yWJKJWRSDp2 sv971+lDk/P6FivTZ8fyaDELtv3lPji1yyVclrs1hRzpbCG+iuK/D2piWFkCvyCEbkc7JfNBYvh+ P2FYtrQBpV6fXZ6pANJA7cNRuDs5Gf/3y3DsL0Ct4dhD3YieBFcjfHvdO5G8pxgUgbqNHEIpinbw S5tM7Rw+QK37SkmWE2hfUUTCUhGd4pfIZ37vySFbNqYy276/1BZil3w/W6EbAgZvldSSigioE7Ux 7YU0N6861P3fUDk3UFI07G8RNP35WwVTDLFHqs6wIN4nIGgJaOnoxpuRT2/aIOBvTpxBsuHX6Ev0 JwGN1XfQ9pppEK8EgmesEL1PkH9nr8GdzsesJ7yYMpKk1qqCZ0kX4l2klzIJ7w/gTw/GQpuFrud4 n0evw/TqOpc898G89NjUdgVOTrCDEzoROT4UIbaSuS6ilbc9/8K/BuomPRrpKjw5ZxZ+OMF5VCHO 9DFyhOyZ6Bkk9yL7htmwnfgxJeHl9VA3UmyqyWITCbgFmSxSfnBoNvH0TC38QQr9GDJP4ChaD/Gi YYbYKL+KxXLixnd4S39yoQheguca9dY3pctYbR046mx9XWuQsD/EeInlir9/m5ANnsLF98ebeZu+ sOWx+M3d1svE8WNYfGHgpb9sLdJpCcaIOLPZWNeFNZpzvIbuPr9mi+mSI8zud1OSqJI0qnDWfwaP zkx9BNE855qJdo5d5xJ81dM9kTFAhVFZ33rKx/D8ltHV+IXP6KIrm+XwqoUcDoyKtGxlqXtUVdbb 0LrCkojiQKtdgdBqlFB7wc9AP4C4ANOXnwSoeUmpwNVrsGiNEIRooUhRb/wrb+w5TYPSCjNa9PrL aMmsmaWZUS/5E+Rfk6eMsErG6chAmqv53g4UvsoJXRVxcXGXgLN+nfU9m2jm2XE7G6ijO4eUDIhN ho6aH+eZmNyJzPNQBKn+UBT9rq44sAuZvP4aT27Y9DWMF/eygdOv37pEE81byeJnH2/ijhCLXgAY u/8yiOWEbJFHsZC8dRwOReKNOdqjLjdx2Keyx//ilbRYZTQ+IMeVhA7OOROtzu2aXvfn35BBJi9/ fwZrzvALtivRvDEFvWbCLkXb4pr6FQvZkkV13dA51JDfALFix6GgIs6NLPcFbO3DExZZfI3AnN56 7GxEGnmLCMqr0q7R4PWvfoikuEne2EYrqnwWtPAN6+KUjuq1e6Be8ricHIe+aNDQuz6+OZVkfNen n1FI85xAO+kzw0WUeHUbrSGOIbp//pEMguAwDltfTW1v681kuvdP4u0eFIbponzczK5OjKuVlK+a Mm8df546vINJkK0hbLi/oirk1gH2+gsog75ADHAOtWdrOHK3nE6mPG/coT8FQqUZOqPDP7/EloNd E2SV0E0G6GMBGALcjAwC6MrXfNlX1iwIj/wTD6dhxDJWgX8Q7tLeLbkr8v47LYB3TZVgdyhFlPyq LNZiNK3l9WBt0y06TDU4b3mos5hsvVjLJCJlnM2Hn9AKb9BDOYN5Xp3Ny1HUI/kxWKcie/eoz/4E 5I+bb4sg3k+6/DbeOrVfo4aoOdwU2vnyehRDGLNolIsCIbIrgucy9bvxeIB5G3s/JittzcxCdmQ2 TIYZ/Z7BCFobyEdkeAfDx7XsEC1TkZb1UtSafFhiFFbHDMjO9pI6a2kbd+E321kVCWfo+/dqTCZ2 0pXgeAtBxz5zZNbyUIQDALPxL6wErOeQj+2zVRzv29LVtJZnEgIELRj69q4DkLtaaNvL5y2pcUMT eqjQMszpYmPAKRx53Xk/wHuxiIhdSrBc30UcL4dDQ+JKmn3XkI1nQxO/2fvpaIZ3QzBDVYiUahJR mmwbj+Y6Qgj9jXGJl4e7fm9Joo9je31X2ZpiL5Qavg3YgiAq/NXwJ1dyJMMOR0e/9m9HkE6nph3u PflgSX1Qrolk4Q1Y3VVNuhL0AITITNWbnn14xlJRGUkEQBetzasUdSqiu/Unr1lBvugUXkgLwxyi A1aT1TB7GKXuGnneJIYAi7gnPPtk3PA3twbCpNln//W4f0g5FBcwTFz3yOFKOwjYH/J468ruygxj p+Pzj3c6jse0Jb/IaKO7hcmmv49vynJDyfXGzx6ylmIK0CfwazqsG5SX6DiLONIa3yaTzGVPhQoq zKUFOLrLd2TE+ssH3xw1Mkt6vwvu6y33DWRljOfmDDmvOsInWae0ZY8RjD43InuTgI5jFwGOXr9K OfxypqgWph/4NJYIFP6HI/z/MbdI6KjYQXT28d7Neixhv3MxyRkBrEUJ3jq0GXbF5pNFOv8dAu8K ZW4E9DJpsOhM5afB3z0DubH8r8lCGfIRx6/A4DgvcAZkQV8vQb3XPP1TntacpZ25r1uGczn7o0gF baXHJKYftCO6llOpnY9oS0EIIfYuuOz1KdZYweh/qbYzVBN8i4DTmRnrCUck2WO+iFOQPVEtO88s Ds/LnR28f24iD6kD/AxDIv8tpB2wnGwKKfFuuVF6iSRgEdECmzayd+IC263OsHyEobpoJE9SKDbm OI5g1c79VxFJvqvm9SXjyVy6+WoCADt3ZIHr+jchOxWaIm6AlDKu+k9Hfp9eBVF3Z87pLCLcOPAW IlDeBtauvSebjtSV7mzC/faEv7eqyHyc8DVfT6NMyqmXqLfrSWeFLdFhDD57Xo5D2nN+Ovw/dqyi Cdl5h+Ngprf/X6OMe/al4wxYF/vC8UwyCydZvKo1LnEw31nK+xgfvYq92cQBrmrPGm69lmdD7DGq 441jticSeqcGMKClGH/VaAu/5ENHHaTPQNxKIWjhvwpMCMVgDUc8PAgoEd9Qi1TH/8WA0JG7T44j vx6ZJOIw5M+RZpyFM3rG7zj2Ij9f34feCujTGkmfnlHSvIrDTT77kZDCJDIfB0tOvEVl0rvjDGGE tVaqew/IGXxvXoxGBe4/y0llVsz4Rgdi7qS59u222/TzfR8c2VjUPPZGj0XPD9a7l+HmI6S1+wtW DEwwYUJKUfia5zK19egBLjcWC4XM3kTZKoocjCibmXvAwjtZwRSkBGqLMegqI8pyZRCmNNbNmrYG 3qkh/gaYQFONeenXXrZESQqhvERqkdo7jecSEouE1jINMYaT4vKWqVkvryMpO+515l7pMrMP5euF 0ARcCaBlqhhBt5FQWGYWf0BS5Q/gRpSeOnj7RDjI3DTLZtreiaAtlpJ6YVqqv06maDgPNqN1r7wT 8qOnErNXoUoWf/Hxv1KfVE0d2FNnOzq803bvTJUK6zoFSa5NO/lHk85VSEnLyCF82EGvGY8YXYPT hYWnaK/hsPg5b7ONnEhA6vudKalfHWfJe/Ad+3q78u9Of3PDT6P7d/Wb1NomA72FhearTTHVJZwg 1UWAhz45cr34FG6pkP6BaGm9udn+wAlXP+OgIKx+/T7MY4zy0n8Cfp331MwfhpjYAG7zUF8QKcfj 25bPjW+j9EhdsY2B5gp3XFibOD6a2G6xY3r720sfn+l5BOfP1G0HtOsVtSkpZ676zOJz1Tz51fxl HhHToJBMuKHTKeuwjpjZGecXsU0GC+VpaNsauCEq2BGWn5EjyFy8s9x6rVMxN6Sh/zaiXZFvaXvq Ub6S9lS+KmZ660IYMYJlnHlvWrwIzkKPBV5+qNfaBJwy0NYTZIgMKeYGGJAVbOJCMA6LCYEqXS7h Hr//qWKVAxH41bWs0g1zwyHX/W9zsyUngUWgIypeAcwPCBSJ0Av1y7yswo18z21L3kL2oQXUhSJ2 clRo3bIz3VSvd0wHJ1j2lD5AIJ+CVWhHnz4RnGidt/LIZgi1P53l87Rri72G5ZNqr4x8hUJ+/P5+ V9SXbtrbtaXFiX1QAwiclRBc3J8H5Wp7kIUz39LnFu23XpjXPgqREbunQ73S9nEhQUquJ1IvnldV QowStR6/rlEAMLHIUENSzLotHpgO2SaJY1enKVz9wBqgMJ6IbWm0ciiTH9Hy/Mhta8lBCfqEmzal acLOkRnqkx/JBxFkXonmuEQxf+DI0O/dm8OfJIzAcguqnbyJdufTEJyuJCK2Mm/R/h/lOiJ/5XRR DxzWMaC4iyLkCH0UBpsGxzawZzzDPJOsSR+YHxKDPizMVg32XPdXKSYt+pdw8v5SXEFmSNjA2TGX F6DNTmYJNq32785z/umQTCzqohmJp6wgnSo+F8tUI4co/2P1YoqeAujVZuSpukNBaaQ5WOp/oY2U EYDHzOYpWkGMssAW7O8NeyLqBicO+rbbZVEQr6OZpiEcbtRPizaALTWn1Ado93x1WrUPB3L0rzwD f9hSGHx0t1gUFPVG9XPAqKta7O0rmR/KCwIZhtr276Nh66L+zw7AQ5+uGN7XcAYQZpEMI/csT34Q Vs0stlxn/kMOzr8f9nnxIKGI2xvncIzkVGrsC0fftNvnMUqr+iMhxbMPenV9vxSesu8C29B1ywT6 mGwMqX/OtFxbdqcCoWtqM9fmL0DEXd38xbpqjX2Lu/Jw436cEoIgymNqtnbqM85+0GQ0YYYTa6qx n4Fff3/voZ4t5Zlq4tcssaNWrzldr/s9gdpN2oU1gK9Lvshu9I2fh1QRN0IG/mefE/nQ3mXWW3NX MBgH3jHpveR0eTsMFqgR2XMJr0vYuo+m+f6b0wq9JEGb22d69rBJ2WrWe8sjNAm2Sg3asOhPJBh6 79kX1BTH1ghZYYKO+cuajIGhfw8tmuSyH+ZbYEdoqjAcx/5CNq1dlX6phJHnhf9EnIClX9DUXcLE 51u4wNgpSzhNQfHLjPJb3fg8Kw1FXJ7RLYK4vBP43VbjHmlPpwqQxOft6OqFEAAzP3UzMPIkKDBd x6HZ24DJLNgfz1Y0b8uJU/vKEhFOGEQWFvS+2c3BxOYK9r9/7La3GlEHQfnLYIbNcy4XwxPn3ED5 u3ZEZnvUvTmFfV1CCOCXlYQuNm76Nws2032B0sdBnXkrCv+9vLfR/RALarQ0xjGRs1MtTgY7j6o5 kAB4WldUJLHauJ6hDHU4EVrmvHyoju8WeZ2GcbxDhPiTsqLMLd6fHcmCwhc8DiivrUT8QQ5op578 fhrotSUTNmG6P1ua1VMQa41/uxhc6+1nBq5M2g+Hy7Koar9ARgjGthvYwx6bchQ5YMJEE6oUBqyr h12H+wa4xuRwc3zAiVDUMSkQDf5FU1DrfzRXi5NKWgrYsuP/fQFeJAQPeBtcBay5N5VZ04Lz0Rhd xmYlxshwPCRHSkIhFAd5QgYrts+f+JMnLMWlvo0DQ+VpV7m9S6XMxU6zaICj+1oEs5bS8kY4o061 /cANT2JMgYWUsIZGDktC43mcyNxU6jPGaBG9qtODiTwY28ZugK0Up9HmVh8gZMJ4za81W3SpXqza pCiodoFMhVNFj81bGYQYwtSFQuRKsLK4D5MBeDWHO+Fb+r4dV/LNL4V4TLTfQmK1pRt+7BeN5yox miMy7FXX3269FODDvpHspzYTsncyMM8p3/O+dqvPII6XjDrHemBPNR4l1hjRD7Zgkfo7F6r3il6c 5MDoiNQUndaGQB4mLAgHKYpuabWg+0okzjj7d2JMQXlRo3smL27xtxh5nX809je7iU8gU8B0zvga RX/6y2j5CtmExE/xHE5FmZrhBlYtOk2DkiBSIS1KLxbrEl089PX5/Kz4TPHzjFbRGX5zxvopF3A8 c8PhuRGti8q+JkFPg5mtltHOWlCToHccnlivNTTwktk0ox+xmqOJhAkBy/tjO+6vkDj7+ooukVSL IRHxUep5rLO9tjRIj8kv1fLYPKIAJ+7hLsP2/BGH/1co/okMXSDO3L0DJzDRHucN1NqffAavK6JG 80SDwsZU9PhMlfayDBBu9qf59vaIw8f90nZX5XYdL9W8h/Kkp7shS8aBE1N/nHhEdxUrfENozxnS OUbwMsIeafkaLvqEbYpJ9jE4WyfFSnnR1R7zQxrfmF2gksujzPAHQB+jTqWtLD6YccbRcF6UgL0T wfYhW5ZdE47xbwFBKuqzoWu68rEZQFb60VVzJWErsDezW2CZLqtrb3qzmkES9vVea9Q1uWIAKHIJ ZCQVW2IucJhpm1geCevk1l+x92vLsfHSgDLCqMZiK6DibVBXs+w8NDyat8JjymVNV/SGjKhzGctG wNeLabegqc0g7NmZiSgimsG0samVcXSvGB+gR2jGVDeVapA/5HkE1RS49U5BgGQgzZmrp9OzXMeb LDGb7M87ZBRsXmfATmEhOExabSWcSZLvPskPTVg0ARTnqs+cYMUDIJVIM5qOxrqOp/c74yE2EaFO 5UCS266A6Nhw+FYB42YFoTYtnOeXmtjv6HfTeEnmxp8kHo2BcIJhriwoBdMvPKc1vGILPLtfLPNr AY5roVGBhv3LdScZiBT3Xg7llDXuuUZjLV6nxqJ7JzmV+IiWJuL1QTsIJron4487HDP7nzjoZ6Ll 4geIktTHRSutZu7KX+6686OgxT3HvifMEENInGEcTE2pcnwwFLMY5JLkAKlCCoNk+JCkFW60TEvU AlbYgTkx5kfCuAAJgAR+rSgphOLuzTQIme24fd1w45SkLopNRyUoVMiP5JIh6SLm90fxqSAb4GCI pwhp5dziNLfqsRHeP1eIBkj69Dmq/mChhsJB5cU8rZPIcNw5QDrcu4VRxP9jCuLoWtatS/JETkuN AGCHBCDmOvx7ULCPcSJT7PMw67PkD6zfMhFgMzMh4VAOGS38SjRIRufiinx1KlN0D4Pq2mYiBPvZ joHuL+p1W3vKBqgSG13iY4GvvxxWgqQIqiZZxkUo+w59IyHHRv7Dv9sxrAfe+g1hbLRsQ6hRIm8X UWs3+H8ZfM5guUBUGIGqpveyHWkVbGl5kEmelbYcoS845wgrcJkZS5udqSzPQ9ThJjvz4WENIdlF 0GwbKGymsH9k6yfR6re23ZovtL9Yopg26SXVFQySmm3Ojqmpt7lNo84dSbBkoEjnHS3p3eA7foss DIeSpRA6mKY+yHVS51qNbY/+1N6IB57gBq8ki2YHsFaP2a4BiEKqKmcZXzGvKpB5tMVyiOYy2RXW s+Up/trNrpAdcdqxrfrctzevEtL8A9k0LlMpfFl26BDmkMkcaV785NP1IQLKiGYE/2T5bhSkN+12 G2AicTTpFrT/bEEkLbuf5Swss0GdT+w2ilzo7xTxjVJWnjAFDT9YI9OGC0qqEG+f0QDjYdlfUg48 pQXPcRigsftF9tYx+3ehhyZjEagS9Kx+NwCG0jGI+1ei9ib3wqs2tqsPjH6iELLaidLVyXCpIzwo 18g/3vnWFYU78PET2OJwA5j4EBM5hKcpe91wAfNX4QVIJR5Oecjp1MSCdaNCHzsBI8YiMFTvtG45 69rFOe4QIEjwulUArGI8SMAEDin7Qnm/dYz560iwWrXgjlLwkl7W5W8Ibz3t8+0IVKIi0tRB+I+5 vX1wM9bgbN8A7nm+VFYdAhTmSY2U5FXnZZjBRn/xJU1tKZFnKnIMq3kXPddfwhWNCvUItHuJJy80 Ojly/SVrn1RjSJpGB7hCtje/u8rVaA1lkOMIUwHTKTJWqkuBh+mZLkWwj/hUK7maWxsHF+qWiUBb n9obJ1LnCbk9aReYEDMvsyvMmv6AGCnOkmZeCmOgMIlVeG94fBskc6jmXeJKKvKYZucV5o39+uNX uys/Pk1IEy5NmHjdTZMq2tfbD1lB5YP/D2yPSC7wvRFnYKOdSeBCr64RaC85WYqlLh5V7pANh8Jv dghmooI7r+ztxF2sReFenZfH7N6iSsJl2EeCojnC0f8qRQ9yK9H3eKoTAMKpaQO7QcPbUE+p09Bt QKjfAE9JdB36IsqtcaAfMmwKyoF5sy0/E75yevs3pM8XffyTFnYmSBP53ogcl7Ll5mbpTHO+ZbQB i6MO1+xuHO1+2ibaPQHpH29kUOadrN5N+J8XdgQrrXQAh+Y4UZ2LRlHn24rbxYP9N1aIAxGgBqMx Qj8l0IyPg7T4dxwWOGGuSPR+7OBh33rVyZbF8cMCfuhQY0b0M+T+XtSz/jZrkdi7ym9zXGWpWrWO T56OkVVJZjAOHNNipXN3/KYetH/iH10MR8RCJJoVofNxgyuQmwwtu6CGaR7F/CWZ4A9PWej/63/6 49Sv6zqQO1m9aHiw6+tvqSxsnpenJt0E7Red9MfXibFPSRIj5sHq94PxhL29ZLBy60R35m7BNU7s 0GnRfzwLm+EPrsV0MnfKJUUZXTtxTDUW+aMiOR7ZQCHXc9VsGsXdwvenzxUv4b8PVwE4xex5CvG1 4ZwL09GdDVyO49tXtmhNMULa/4uiwg1T/++LCRrvybFtYGDDABahy/3pNHwfvjR8hyKveMcOxbJv RvGkcW2RNzG9et1lbpkYLkLuS2lbMYE/W+2ZGNExhG8193HMFdfxUrMb9ZolGYM99qs6kCRNPZN7 tm2t3Ly0dB3ubuCIU6WayYL3yE46oOSaIOoQuejrrrvM47GIRCezvkFU9vaXzSgrMVHCXy/cHhga 61hgKTpJG4/sNbgPNtqCqKKmFa3Gu+74Em00WOttS3oFqxmfrWKAmp/Vw9A587PIQybUnvNXU9PZ 6qBncoOxHGqi31U/gMRBGKiWLaeEp/cgdbFThMIYSlfHXq2ZUV2YjHHt1paJbs4jPZI5/eNFB8o1 tyuvLSLE+rnmbI+QfAhI0YJaoE8dQHLV/zyETg8IZyA8guCZTv7IxVkKxeTeZCYU9MAB6JMm/4ik ZhXjPHXOLoy7PyXXdDgJK9QhrpVkSF4jIq4zDNx+okVBw8ZtGPytsUBW9tFBXzXn2bBl9jS8dEi9 xM6bxy1FWR7hAFlUyLivTGgXoketsTGQXwW3z+9779pUo2M3iXtwWXqB1OVFfN9fJSql3eu2GaUe MMzTLPyOCir4FQEYNdmzfU1SzTvv/ZzVPFduVTtzyQQKCnmgEKLuuuVEl2gDKeWiS8z51UyUZcsi Ur2PGpKjIDYW+5jCh9Yyol47qq/PoGZNZIWcqh7ms4qrSOKJS6Wu3qNA1bNkQA9JJ/I+8ZRlVM62 ralO6mxpX0xqhycyarhRjazJBjAOCLKVziOt7cJnQFYUWvINzRocqgbkKAKnfZshTBb9pxnTK+H9 wCjv8Q1HTZ6J5RbNkilEawQW3nfK94cJ4sJVVLEjm3M1F1cviZcekHToRPJ7OPLyGaZEx5Aa2fJJ YhARyVHM2lmXr2BEyVMoxMpN3jBCdY/ja6bynRAqDJCxbFp+xLppmXo31yxYhmsq8iZOvQWxjcuv uXs+1AWN3/0WyUnhD6c1dOGyu57PNbextdCZMFlFcTCNIhlsN7rj6oUxZzRW1yURSdt3Vt34Ojey WJsl4Ys/a82c+euxt2760gfOAYaifKN89b/UZ39jcr8hOl6hQc5QRsJF3+RV5nzcCnyJ78xEKbEX TpiY3UNaa5DDJnki1eLHQhhYX76crJ5pFSLA0/T18xslFflnxmkK+stFj++VBCuUhglDq8XMXZ5+ B7BLH+tVzDW++Xe+tkgoQ3CFWAkDfSTr3KKLnQdHzPyC3kvoW4bBNmeIReNvbvvhtcs/q+XDMXA4 zuyrD4pMAz1C1jbztAx8OM58E9UAGjVeCFadgDkUAtg8Hi3CRbHDqA42GcqHwlYopJwSkScWrckA AtuJWbpnFbVXXL/DkjJISMYWY2Qv4h3t9EzBvLUB49CXI0MJMQNkxigqcR2cvmbvnN1fVRHIXgwG NlCbcVQ6w2UzbCg3Zmtb9XOV1WOcIpHBh+3LatQLce5ALI2QcaQR0iOA/Xg+MpVzVZBsWrqDn1OA nBWSwGPih3uXUaxydbPHp0dGCuBqaWOE4PXAV9SbrwSifyUpak6T4B9Nq8/Dxcup9UuAzd0CnPX/ aNXr80iLx9g0Qpe0em8KwecjXU3A0Nov16pm7owMO5c3Gv8Pm0MSD6e9p4TOkj5pU8eLNca8M1oD IYFwhOXAOhrXZSO+7dapCMrIuMnWwFA0i9hRQVMrPcnPgosC/0ri9lQ+tVSUctQ+s8eQJNNaa52n kU3HqgPcU9TVo+ifvkUkA6AAHPNCZ8T8va6O/xPx8Tf9vhViYrfs/+ZVdwd327UcThN6y0LSPkZx hrs2Gh+HlkNNQglUmDfEnNMEKiNabJ3mJMoGQZHOf++MYn1ftF5Xj03xTsQ1pzbNpZVnztK6ZFEQ eZajlO8mqkDwGYS2Qfe54vWHws7jg2QHDL903tk9Zfcx9f0nYvWC6olFqM9/+4jeE4PyQ/XHIaTM CmlILmjYgK/9l9Lxej16IRq+E2VC4KH6Q98fTAK84HpWDtMua9hL2o7fQP0A5on76uQ0P5H7Hhn8 7OtQPpp8y6wnBN9RmV4eFv3fHI3lCJFuSDCD29d1hWGa6M51zi1bxK27lIMXitQakCx3yVzYtHHt GTBxn/V8/jjTETVfDNj2PagV4XjGt9ZQIH6Uz7A1baWzJ0Q07KodWYEWRZa9idLmaB5N8IYLxwNX Em/eubsuxFp4sYAvzPXs2Isgkw74MVG7iIVtV9yD+AnMYJKZ2+SoydYuA4hJxwUmzeV4mIcsdm1z shvMKt5euucN5ZBinl7krieAIkcaCClTIMrYQHUQhIyPKWulH8DsMEl3K84jqBtfWxUfqkLVFLE2 KVN5ctBUIDZ/Vi9yc5snb9Y5t7CANzAQ1xBUh+4cIWH03bjHvQLBKg8IVjUnz1HWfj9Ds09pP66e Ad7CFPldm13L7Nyp/mEslEJqShUDciMmHzj9F4vVOJNGv2hZCPamWFpY8Mc/h+5+8vc/d6mx8ii4 OvDlt+BQZZjVXcc2nJrpez50Z+9X4VUqsg1B1W5YKXqQAjOVgvl6+0cV/HMFjeZUkZOoSVFMixWx rLswZvk0b4yTbg9s8PDLnrXEChiJ6RzoyU4SeEB3jdS56cui0Nh3NsqnsYxpTWxQ4nyMoYFSN9Hf tsnvRlIFZT8xNZSsaZ5E6B6l5kwHZOAWC7vVa5t2oTDlURzqwUM/q5IAIYqSlqFU/HddlxPxhsr2 SJtzumaHGYnIIT39z3Gz1t87zcAescB3vucOtZcLr+4OCRG4R0DF5Tkwlg9anuCFpaynoeJWq6kd D22qDQuv1+yvukVKjrI8lhJdQubnEofqz1Ub8YeKRuUtHdanuwzAxsiCbJk0PDeWnptHCencjB+/ 25s3n4iyKZsPCltCdGr3YjoVGrMPdhz6G9oDwAqMpWZGmjJaQloANmRJJZIy9OXhiVSe4yRYO7so nRNehgBzUg1Jc6sB1YsWmXbli2bNLNEjYg9QjW2q1QeOrb6ZmnUZiSLQ7YvyjokS7UNwaXnlCY1w SHz16TEdV8mVmDMvzxRgIc61HnwW6EGQ9k7JYVsgMAlws2WEJFYF/sg5J23/UQzbIqk+orhEpBUr TnW3ws/rIUZRF1CMdEdY68MbBdpxVn4dba5uC0wR8D/ZaCzbKHco6p46s5tlWvVTD26QBAMv7Vn/ ns48G9jdp/C2bAvrW3OsEVDWSTESCMhdlkO9yQEi0K/UwGE1LGZH5H/vL61yPUlAahoyfWqKYOsY EcAO29ZR4U9KmPsrzzhi8h2j9ItiDnMH3GDO/xrgQevv3QqYtdk5mFXr4pGcK2EQBPTVwYp74WaC xQqyBfRYdEgTRfSEbGmSqxP/C8GXqMDj2PJxuGIffDLcb16FNhJIHmGuYQuYg/7jDlVUCCZP+F5G i1xJPLBnl9i+yQOtI3tmLM9Vm8+t2eTvskXb6lub+HWLqS+ZO0hFPVcFkffVH4OlvUTXbz048C8i Pi9ET5I5Vep/UC1D0Z35uO7PzweBdWIDUjYMee0zXDA0/FUvfuSs7XdFidAYNXtxoH9gp0vuq7h1 GVrIkumERhZzLkYZZkyYdu/1ko0WGt7GwuPlpcJciLcQwhcZT8ky2bq//v9lbOqBEjZeD1h/19et 3dYJ2b1ofc60Wgf0KwoA+MQopfD67IiFFXoKGWAJLfJAz8vEc6umbvrkU0c06jimRwPOOh11/xG+ T/ALxDAwgb1/qz7IEtlisPpLPT7N2HO5jqRNO8sry+0u0B23ur1sysEKWriXDGLvvHASTW83h/Q4 RAFs5eoIxvGF0IUG4AS4yI47Kjvflguc1c1tFBTm/lHntgUIvUiWjL5m/xcyX/Hm3OG4t4Z/DCfE oCpVQqXxWU8CsAzy8by+ofVVEroc6+Uu2m5KpXeqKYxUlo3lyo15d4CONtxYxY9o69YJev/KHhsi QDprPNuSJhf+c0wfAqOfIHUsVYSWxzOI5a/c9/sSObdil8AHXoYZZiqkdYhB4wFlmC+LAIGr2m2M EDzDzlfQGqum/0cpN79UrEUsv5O/hM5unZmFGMRVx+6z3QRK2FwQwnT/vkhucbuW/R3dRC6TS8lK gCaPCoxMArZY6gv6ylSaj0dnJ2Fbr37ybDB25rnhgcT+auKz6blcuY1kJ4CjKplRfsh5F9K5zFOo nkLciY7BAQbLSoFstzN6EYJsPyvQ2xNClYmuqlM+61NbSyIICTL0Kt5cVRuhO1ystrhindPocnsl FF7ESrUnW1MqM/whIghGLpaJpgHPpPAFOqB3Tn9vkSXQS+AIfCVg5vlqDIIxGH09ZQakfhO7iCwq uOXw5Rw/nbMxfob5sJoN+q/34kiAS32awLIpsbT8/2Ot3hEyLKLWeLk+LEg9cSeO+JjjSR19dBwW T18r6JZdaOPLfb9preITyOBQaIAWK+MI8BmPfExumb0Ddy0hs/bm9GLkUT9ZzgpOvJ7sgeJRLBhl B7ad7UTKwcVeHJ16wZS8u7Osh39ZXrvtoO6xRZpdbafnHOJLfQhdN0n2AuWBWSDBtc5YNOquBRhR hdSs3nhiloP/YVC1xgnDZsAk/p3vRXkfpTTjXjfU61BwPArov/qi+MH3GqZX/OmYY9+UPIT9dzv7 GmiBn5Y61NG1Xq8i83Z5L5JWrGHTRAYJx79iPhUq+x1QoVkpGtHmgg6cBNmfgy0nr8IUs3eK5lAf oOfW3VL/d4Apq83tK5v7pzA4Zm50iKPiwg98fEeeiBglm22kWWBaDg1+O+2CdseF9nywFxgJAAKc pZ1gz7K1BAImAA0Mfgbpy4PC1euTm5b1VZnaSFNhYNNTQ78C8aB0OBASpSsKthnRahMHcTJbqxhk MyfEowT+yZegG3FVKoSDhsJ/PWWHCgbaVpBmSNBkWnRcb0YCeSMdkSipAZWBqYEv5ViUeuk1dYKk oaetskfE5Fry1IUYVHI781rR//zWMp5RAVAJE38U/8FhR0mCTUKAp8tEhJEOPf9Ca2cY0qSD4bmO wPkJ9QhJ+Uu+pdAVOnal0aOVBsosooQWuB8ZZnV1A9A0XGVQUAxsJ+JJHTj+mNqs3QvJydwK7fRD 529Bm7gT3562fGiKk/NdSMQNWgBdvQ0Q/rVDXocRY2+9XkLDUqikP/NksWMiarbeJlB9BVPGlI4z h5PE3TRBZUscH5gWDaWfW9yZX95jXstPS741wcmz49OIqiSSRjbzjuLaT5uvcKa2XrRkjCRD6rYw lkUtA11AepiIpRA6rsSQf/2alHqYe9HOS8CzOvCItjW5nGAJtnXgXIxSWRlf3NdGZPFLjVQ8Qv3C TO6A5wCvXxEBk4fuwcdarbHP5UWTs8ijk1gtTAeUTwiZNUz8woDgv5YJYrPBYFug0umy+XRa8ppP 7ZOaT8k8MtueJVOX0I+K68qPR6XZt55HKog/pooonqyP0DUQq2Qy6n1cCOHtMl8thYKbPGdCFEmK mT/8h+LKSSwQtq4EhXfjt9p7kpjpeDm0bK+/3/JWh/IRHxhaW6x5gbhjfHwCvt69XE+SZV5gUxn/ QDwoedm8dXZBcuwSGb+gRJEsSUhPKGI6oJJPV0Nkf/a/hhz6m4h4gYyuf9DCFmFJ6a6adgAkRp6P tdw6IXx6sCX/zmgJUegLkYCYj0wGN6g8hWcz6jGbrmiTe4R/emguNUXsmUItPZcO3E2PJYxRMgPi isVCmaTEl5f7yaRF13b71XVubYnFh9M1MTyf9qY9eTr5smgQhnPOYPrGj7NZ9+uxe2shLpYkPD6B 9AoqXoGfnHqC0Msj9Yt485/5CrvXLQAkx0mbyArx6HXEBLYf06jFLrTFLu9z0rk4RvlQ0gjlNTn6 kWmWv+yX50Bb5XdMgZ8RnFka8LbglWkiOVGeD6CIAPC4wPV+962cscPY5OBNdPjg2VWuHXkhlSSE 1b9OMPm3QUe0QlUcAIy++nxu59Tt/HgYaIv73jihN3KfvRYrbBKzgwzwqS95DREieu4x8ioddHSV aCXltDTR5R/DL5I9ZHBXYOvL+4cthaOU5BkDhzk3tL0+DRDrM7Y2LZUy3uA1Th9pzDfiOMz0H5rC mpUYqdcfBXNyFqlY6KtfzDzHRwfkZbG/siDPU6ZNpBQ4ECqZpq1y29tWHoreawpB9nT02zMtErIj Op5McnWHpBuZBhVdVYU43I/g/3Kbg8j4hduat2Oc9VEYs1d2NByGWtK7DcYlFvC8cPa7vmcwOrOf HZ6t4sBAwIkKabXOGfnaZWsLEmyVjZxh30/w7T5+ZV0r43bXfTLFR9QJoGl9MkJT71PZvZZN45el UiNvv5Q/y/2sZ8kgKwwTwvAPTd6PHZDmSwrIpn56MySpJIXVTZ73pgSCKRM/e+610iDVDWbkFXMV LsPdKxEQbCt0Mq2R8tdXVXlBviqYtiWtdY533MuPFCsRAjFxxRuCC0Bi8lJN9ckQ3epqosB73t4i v/Y5mCjGiC9dBuB81Sg2kNmcpK1teHlGfUhTh9VEPQwyM/gC5ZnSpEiYX7GcA54FpSqas9Nwpwaj dxRttYUjBuae6GRxRSFY1BBw4j4NXhK3bJMS2wwxBncdiuzw76YFsrGk9XOlfsx5bqEgtVhByEDA IhuXQrNshD9VSivPtJLBDbHXLoqIdDz+2F84A+EoQ2fvUY1dz7pOK3pe4xaRpjltx5KWyaJ5wlWL 44g3ubXDNoJsV/fzD1CORxXZFDtdtEY2VAdNq6ExVa51/phyQwaDLBjjQcxZdTYMeg+n25bhcbhM /TRCnPpgEt1QnC4pw65Eax0H3jIixZxfbFw7ytZMeIjWbAeoNFQ7joQYBbgLBZnpTsDEM/afDrJz TIb9O47edwphkZs7WOc2lCMGWnFPupBGnjN/flxhLoNAkEWZlArKBE5HjFplgeNcxpJSL4FkphVN naaTO+u7VSy0m/Jaz2vxNvCaxC87E0VIO+WAzP4RIbeOY9TUWSaZjZ1pCMsjx2JcEyDEb6hQi9l9 Stk8jzTsOXqVUO6yFjnz85bQqD1gakH8DxFDW3fdlgHyCTEZV3L+9E3hgQP2mf7AsomUz2p6nPDJ JPTK9Koh14kLmPcUnOPhBcL4P/OHFVqUvrU4F92LGlTFO/SrcfsRKbTtBWndezzdYdsCvIed8dkl TIls3AlMJGBackmAx/KA3D64wPFMGYAn486dccIMh9/Y8USPOVB0wHxReADjjEGbTgGpstJ6PYdP 9iLQWkz/+DXrIlJeFVY0dZh/yArrymQCgbkNlFBPd8qYMoBmzvLU8y4F4LMDnxW9Wh8DW/sIgiNx HBOHOh2mU4WXPiAo2/NmPRlS+LLcFT91hjYtowayPs1n7AlLtiNdoeKlj207IpK4/UvBOHGiqvZv VFqx68MYFGli2O4X6n7pRL6bgLPz41HIzG8Bctwk5pX8gHdDbiqGVrcJT1ddmMApuOkhninjwjxM Q93V+efuaHBM9fM1cPudAOxQdriaZxG9hBCN+uYzQYZqW+NshJYhXeFAU/I6U3lJKBDgc1tshPNd +VpRU97JZe/3oj/ege/UjU0Ukt/nRfKijySwo5YyJIh1QFVZZPf5iSKhMxeRewkjmlxE+lt4aUtJ D9tXrD1vTxojaal8r845VSGPd3io39z8otrgWJoPusyD5xp1u8kM3BZOYEeFJc5Y9/UyA69iAEH/ H2JsWmrKnXWSmqygW+cpVzVvwOuM5awjjV+cvViuiLvzwAW2tR0w6sML0ugJZ/t2UWNXfRyzFCgv sglwFDsSTHucik/yO5m3CiR86BJCSFxgYn8sBLnxirpzgAYqtS1hthP9BaQR8CJQ0kDuLWAxJmGf oXWU8y0sfOpvJSArIxRgJb2zoEh+EDKsuJlom/CkCmTeiCD6yZf0PNgRowJn2lZYVq+WyTkMLS5k F58cO0yO1kkq3hfwtOB2wtm+uUA/pZFkOYur8GKXNsSV289yfWwX/oqZLDkLshPXlANmdZkYLVaW ck/4i3ASXVWUf57kRGAyavS3l860S5akEOkpRPdcKX2HMYQCt4UlLJ51Mrz1papmqp1dtQYO5Crq ytBL2RBCXQ053r4CVa/fq7O9mJDiB8bMTgEWU5/g2p74sn6eqsHCF+fxVFTkthdBF+i9X4KmEMWV DYDQalpb1xdwIB5Fms2n4Eeo7mTimhBg1Y9kOXrbRHSfhMug/1ZkXsl/Pc559+mozIkwD4ku0z+y rZWYFlTVghD/hhvYOdkM/j24Yn1RnrvWs/8QY17egC5zUjuvhJXtFGulihIpFdzcDtY9QtLrWuEZ 7mOpi47XVfya1LRdERJobHPxX+S9Da9yX3/GFHpknaHYqcvZ/ZNYwIXt2BZQpOZtMyuDxbImmNSc m2rURo3wH8RL4qILgc7neUORf/d714nmehaInWOrqB584kEt4chebIJaOHyDQHvrUnkiWjL2pL7R j7QowIP9N/FIj6D3Il1l3dD207cR3Nr8XYq/9ZMTqjkYBbSsljkJzInaL2bm5oYM8MOHL9YZ+Nme 7qEmeuKjHmvNsDRiig8bIuvZPNq5WegvfhXDouaZR6jH3ldt/aWiPTLzHDynvr2nj0KftqiFsAGc fu3eN4d/d5Ki992Qmho2U5Ub9ZtfGg/y7v1qMzTTHylmS6n7kDBdos/Wg4abu5dmMeRcvMGBCNo1 7LNbBiVWC5KWNTEcbbsR0hkiSk+6FLpSkhX7vFkKjI/PYq/blwrfDYkcREYUvpXiqCjtp29ua6OE Ivstn/UsP50YlY3Pq2VrXjNHhOjEUPnlHd9ls8k/pXiJgfd/gL2VHDxCD7GRzb9lGagaLT7e8jOs XkQjq+qKnPcil659YNkfUNY7Fsls2uT2uu1z8/mfjreDfSpQAVUqo7o6avXLx2O+arCP9cbt72Zm fxM49D6fXEjWogP3KVe0Esor5PNYrWrbUxeHKS3vDmx6ZO3ZG42HSWNfMVY9q9qSJw6OoSZ80Hip WLn4OY92DRTMQswHUxvxBBf8gtxleECL0l7DTUoE1dyJ3vshhHTwx7rWp2MoSDIGFkbmSzjcIVV6 70uhFB4uAInx2YV97F6C/1rwo0ADvE72m+aejJr/BjP0MKVyiddWGYacMmcVj/HtlVTi50XKnLOV Deww5H97FDTyeSXx4Rqe3UqYHypMYJDbXJ9oOC73Px3yEsGjcewBHBW9bcs5ALBPehuxXW5QLs/b CCyS0w56zKP88eRrVCPr6sd85Q2038kDWdrATKDk7cxNvS8PcQvflx+u6xEybHSBSpRvGFp+T0KD EGRiZMyvD/SLYTIoRuBJJIyePr5cBOuu2Wg6KCMPpmT4XFRZwXnKbKfFDr12Rx7MYfznvNMvZj2I OpClCs0gm3OX5bSLX50J/zwbetXR4A+gYGuUKB9qSYrXKVKYMzGqBZVK+69gKEqgx4uQBWVkNtji PN2ErBkeVDeeFkFrJKW4MysAz2sMwwX7KMqGy0T+njl834bLxoq0teJ+GysMsYzXXthyG/51CvxB 0m/xwE16/6NT2NjXlVjhY10UyZDghSMVKxXzV6DWOziDbss+OYIemWzh7+l5nhl8sPyd0Xyxis5M pvNgCwpMAtzZE82vY15tzS193k8Vmu4OPN/Cv9iQqNLNW0N2VB4GyqOsxLri4Aq8wUHO55cDATFa 7M/End/jXSnIrhrB5Wk5Er4pwqZCHT4nJTIaGhBYh/C/WFekUh3xeo0pww5ufGS1OysB9Qz/G95v mLkp3sY5qggmrHqPRQAIkf/tgw6UUnJf0fdHpdFUv2jNecMDxdcEDFnY31Elo0vV8M9/FfOOe/7l VpLM7Q/hyzSxdkjQtvUCw+5Rv3z0nlA9DTQpE8vhFj04iFRN1+NTCxf9Z+Luz1oViHcFFi+I9XhY anwlBWskm5kGjuoRKQ2d8X4dHS3lvLHsWXjbfsQA0/9KaiZx0LduNw8D/PGaf2meckQgmc42hqlN WXXEqCX+zPS2IYHbP5lOzqRMXJ/zWPsfujgqLmjhBLk0nF7Q0/uTTrTmVFyVlpolSVRPKyN8OzBK ay8yJtNsECCSKtDQA1PKdkjDrvn5PDZR9zKvAq0LtQTvRQnfqx+9v9UJsMu6C2eCkY5ppt7LPau4 UOf+GulZ0AAUUX0SWEYr/SWiuqFqsx4SkzFsPsJSWlc0HPzs3AhYcWMqaLKOQbHoUjbNBbZ1ARVF Skh6/k5HXNNzCQt9NYO/j9v8t8EumMDykqEA8mK7Y2v1DaWuI1M2iTX1MfbF98Eu+C0BJNxHHkrb rxLkihLXIxo9bdtBJWB2oI7AU9ILwIyiTM+ykbfwmkvMzEONqdJAPofNPnKDlOXruvVw8uqmv01j e4MBalAIPnuwTsrLZcv1uXNzVp2wrUlj9sMyPGUTgLY/2err0pYNmxLg41aSpripTiDAupMyXVlF bNQgHMGaXnb1KeiAd6L+ucS5vDz8XuSt15TzXrth0ftHVOvAnX+FWrjnmtx0BoQtFN3VCIXvk+5w V3rkPJJjDmcfmNnslVCQj6VqHbRvth/EeTu6keyqnF0veaMT1GNTDZbPom2XsGYYmJA32I4xKZyr 8dVI4dslHctuulB95q/Q3IK7MHwjqCKQGkMGThQzvQIylWvtWPyQ8WkXXCot4e4Z/+WAEFQaRWFo vdS3eG4Dtx0xF4tNZ9weidBDy2w1uO0uiHYHPYzeyXcxTjRW0cEKbppSF0y59KCRXIRFYE5iXjK3 ImhUgFVomM72By7YdUKb/N2ss5dnGqQH/kwa/X7NkiQSGOCM1mNMw1ldA9LjWK5FHubjj8mqOgSs 7ZA9u0Ov5qLKHq7teIBNkd5cT/taCmECuO+4bXItqV4V9QaKHRYXg/2gH6R62ImAg1hZHplw3Vpj pMTeaSNOJW33ozqUNRNXKK2aKhOHCyCAKLl/O3uxknSzo/jYqL62VEzYS4TZ+WPLc9TKoUuGSgkK CRanye4McT8oQjBKx6f9mTGJ9rMMfZcq52Nwwqr6msLvekjprbWqgvl8vyTgqCMUAtfvGrrZAGWf p9bpTS7UBbjPr+dgrz2b0kY7aamK6nvi6+3rkbs4sAHwQG3WQEojF7RkXbw3l2ITTngjfkHSqfne +RmaQpdSRx+TX0XVt25b8eFn+FbNMvAIVfO7/RqeZ5BhbgMyqg28TS7dohoqwVNxiKOAdY+9jANP pWBoX8CXlsWnE8+k69ANIkX7HgLCqnnUZ2jHgwyh+6jHDTVqgpiFmsFW7I+EPqzLFHJBO1SHsj6e 9H81EB8qRopNXswCquprm1AnOxM5F52TqZcjM7vKxnlycQ3JcXsG/V4Fvclx/+iWVDHHRj1Hc5Hg 4F/S7vVNTS+oRhxnG3ac09KPlQU87lzRqVH8H8A7TXG3Hnjo3zkVC4NF6TKZEdb2qkhvxpH9Saic cQCMenP7LPMwyIx6MHnSSQy8DFEE7TEXTJknd9x4KTBOLM5JdeXPxt0+OTD7CLjVCaBl39FWZ2h9 174NLoAjFzovdXMjb0UL/X90Ea0lv4FC1fphID9Tf6cjeAdfW3x+88lRvjxoX+swFZkKIMMdTF91 wIt1r5+f8ZYEJyQbgyRKVbOpcSDglyO9N8cLeDQEM3J2e0tDhCkoM70Dfp+xOZnq7FUm81ANkmQf uIDkbC+ViiTP7sYpOdA62RIl0JTC8zs5LnBWuMBPAWsWg9ytOdmPe+EWS+FTWraCieXE0jV5QUIA u63BZ6E8j833K6JC29SoiBYuubdS7n5kZHC03YQuZKbi8Te/NnkWb0Zqvc7tsZo8YIwLGHON1Z4L Gcxnp3jvbzBRgTypL3QP4emYbBcV0Ny5ZaEEpheZE97cWvNS0ot98JDg1sMGphFlpLWy3HSTzYFJ G6emHbw5roxH2JdzWzbPDXFIzAuvozd5l+PuirtH3kcq1Eo8CCK5UDa07pdlt5X+X6xG1kflUY/V m3TO/VlXWutwKXxNI2kW54/Ue0Y70heQHw6KHHfThavfF6cVLAgtNujT1LxaN1I6jYXstla1bIP3 CGj54CO4PQkbDs26CqcJNh2NsKu557ajSrNmRDmSSvX3m+m8OnsP19Olf4ieZU+aa/ox0icU4YCV uhjdd+I0FcKQ+50nF8Db3ZSs6hQ8fENYDZMZobNIWUrGANHDbwmLu6+I8CYKTZJgOy/bYHo0aap6 Dp1J1QIqraThxSrdFDJROQRLBrbyH2IOjiRGqK7oKtsihtWLj6n2+w0vQIzeIgz2GU60OWI64i5M nwjXycK8B8Okw7fdsWUYOc1d8Y1aOX45jaIcFgA7dmmEUene2s1xv7fJ4IhtDW3H7FrvqmGYpNbK zHcD0iGCL4zsuaAgMBsxeJRbUlln8VwHqZo31bd4IjjUPEBdu97I0cDZ3LR4GFXwdf96EKk2h+/Q uIy0FQl/3CISpXHgCdr6up+z6jTdFD7iY3/5H20yWTXkOzBpy94veoaOrxCX0EGKj+BpyEC9C8QM HAXiEUELHVSoyIMWwlaaMdfF4VVLYwZyHnO79Hso66yvNZogDRSz/B7I+Qp8ovGcY2BPLlxqMG2O EGWq+F7ebK7eVkFTdBeWP9FjnnqX88DVo+A7d5yQjoz+vTeS6YmtZXKaUaLj8kJMgkdMJB2mB8Pu fKfCASjog8nQTx9+lxHtClAlb5G16mEmxrvXogQgW6/qbhRKpL0O2gIdB70RgE1zeM9DUiB/OOmN YmXXwVCDOUGetbZxm2zlTqzV1DsN4+L5/CGlEyj2HWCkaZED/WlM4dP9O1NbsvxFTXleLEMaSmV3 FT57YcSncjsirUuQUvxzilnzVDXqmJ3kiyr3kdCfoCK58JvVxp2ryk7Zc7ISQbg2m1ogvHs/3tJf BrHRsGQAdPaaOozkXywDxhGXA5c13gGeIFwxdMSBlrqCDRkcW2IPM+Epv905mi2pOr62nNWhrV82 7iMCHINDkAhkRASWocTEc3S4c0tOQQlgJ/fWRnLMVBQTY7UkDlEWx+hoXnDpxkVLRkgo55DqGOBW OLKhnH1YMV+MPgRhBzfE6XOIUCQ8pGIM4pruGu8uwulxiM8a2wA2+fX6QU88Lx3mOpCmxOzulacr 0u5AuWtIu0+y/CccrzfFCUrXrSVIFu68ONWqIFwyZzVHB64f8dDN+iVrYSGOHwSx2P5pOdYx7QFp LsAcqWZSDOf5GRJYCbzLcRw2yBQjYzv8kRB2VTGFKMzRWejBwfS4pOSGsKNrgfdRUBZ8SJ9jdvhy nDMIybwo++p6CpEt4hCvF3Nxep9J11bhynbqTtb9vpJDfTaBK1yGGD9awu5GnasxYMpOFMINZuIa H+ZiJS/mq2GIfgGmWEfv9ksgnn0PQbUvG1Z/b+S0UuIvVcoeVwaQgjvcaKUC413sATCXvTxTN2V0 qantkbnJ2Rn8A2suGdKyscNp0uEEWgGotCT4ypmiJEVVobEpV7liIA+wSlWky6RvCsALXUUZiakf zOOx+2nWR4XvnZd8PS3hTakwwyM7Qb24F5TnCA1ol2ms4ox1cnOL70GJ6Qg1M6WSQ/bGzhnJUjy9 oXdefyf4yy3yFIg5Grga+JpI1IbWXV+K0GHnbHUFlmPgbm7YfrVYUpoa6NvNQ754x1zaVWkzQvrt SzAn0ZAfIFZPtVKpYOHA9ARSf9eAEoCbJOJE2mk32ktqjNNHKbMhvACebIu7vxzaMSMEaXXVytRL 6McfLFrrJ+V9NYye1jFeDtuitkL+70Qh2EGRYTvM68zzS+Es+TSlQ0RdcgAWNrSuUTut3PG1Gdoe BCY62dwRDnuO/dJXyDfqN7OnhrUn2vsfvkMWWjbkWKmX1Eksenq5vN8Yw/UHv0qlpEJnpLM4dody qUwZf5tmi7yp4fMc5EZK+QQAzkqRHUzfbKqkaHTGffL6e+zB7o0w1l6I4oUqkljF36zuIVG35o2x mrvJTmJDb04m/gsKjdhH/rhBHyCvQfPCoe6RKauSl2y1ljs//GbXT4LkzKw4NUL1gkxsexnRVw8F w8iayfht3ZgeFRWK1Z6cSeHhBKvBPc0NGSBNt1Z6/RGHmx08HM/vrs+rgexuFJHAzObLpPlslrXg qUEuOcqGJ17BXZBnzbnXwUqGJWs+bACiblVUNDQXZGNhZmM33yvYmhn4aMEqPqeNd4rHtrTSD9g9 msEaQGdD4wBP5LhNqm04aXstI53iGiUP/Djv0V2QMbznnvKVUfo29SMd8Wwv99Eq552WV8p63woT V31S/YdEuO5vGI2X/E4xtdztUD/DjGNq8TbpglAuGb7dvnQDdibYAUOWewoSLXOjD4iR8Ry1zOwM Qt2IDQZT51Qzg1UFpjQHhjCqfVP9G027R3IRECLxd+DVLw7z5bmPmx2irUqqqpPgvJJ+2GwtyJfY U8QuFnb/AOYuLtUR0o/yTjdqmR6aMCFmOm91GCg5WM6dc5KW1pOLjf1UIL188ghqcMwzxHymCoQs EsNKWB31oIB5A649p4SJLzrhdtfJ3LdDe8cn1vpL5pAU8QNMpGoDMslNYdKbqp9ENoUd7eQkRN/3 qNfgB1r4IQ0iF5mP+VXf5EqopxZZ9dBgk8FnVpdx+C/e5b4sD/TXZ5zhJa4KQT0WbU/wW6snROYO ihHaT9h7zduyfaQpY6Pz2AGqvckShUrRGq2qdnIgoKHSptoyE8FvDdd6RAKB3ATirW4FnMMxgJHb jdUi0VK6U3j7bQPo8+0MJwWlWAPP06cnmoTzkG9YRG+wmCWBUjktDzP7A/d/7w0dCACgJZL0mVsr Sb1RHrYjUTL6/DvrFyBLwFI7hOwRe/GGO09r7hgoN8/VH5nSKZBw8KBdcCnhU3bKYdhPmoLK7wUO charaiyrR02PNNBzpd5zkyv+4lVs8Vdzh8Q+XYW4ujiXrSZ0/hn00X3PnZMzOJmvD3TkUzTSBNhv tYNgWUhAja69GcpOA7DyTgPregV40YzidRhltVe7n7x/H2xCXKHVjjvIBg8/22lO2+4k1/9r6Xpm TOygpBWGatkRNprJx4I6kMl+o2srkgRttfqU/NpnMpLgLbXzLPqKdYYinjMEmCI9pMZs3YKmjA7D lCSqXqIniv4pfP/6DZuN6ResOw8DvhtFDpVPhStDdjCDDtWQA2MEdAkwSPj6q+tt90CiFo0zLXor eh5iymR1zzbU2VaA1OJIA3KsISaTnESD/eqnFULh2ei3uNWgFnRK4j8MoJuUEzzlqA9cO18ZejJQ kngusxsduIO5HYxN55oJThBHpdtLQmdsm1cFD9zYUULpntuI5due63haPVxQplp1mglBa8tZ4OQw Na54B/y0VEDo+Fa7haU2taet52WYKW2NxgChcE2NrICt5yurUR0sim/yw6Va6a6BjzJCP3X9K+DX UuQb8hTmx6nr/Lir6WKAHsdC9Xgk7dqKeEX4+Ok7Th8BdPVLFCoXKSvdceZAo6W1SPskGK4hcqgd 0qaQhD6qzMvXaBWWhjT8boSHPxQLh3GHMab/cgGFChsLZenW4U0cmRqjRqbMyMAS8+5N7O5FZT6z U8LsphDtNf4cseXvW7KZSxL/Cj7zfnCARUr22VU8d5TlZWXez0g1jggzw5evLfyCiEsAL7E/+qXE Jx4ygebaKUzsndg5IBw90S/5mZq/++FZjDrjYKJXH/IdzlBvSzA6yVmAy9p1HFHyRSNY7L9cMSdb ORNS/3ZDNpz+inD6ArMVc9qlFExYfBqhHNufui/IqNl7jANAYX9QaTRNorEuYDtyAn6voQcYFiS2 dy7hovTzCAV3SuUyQErc4voCAQJ01pNt1LJhmm6lfxxKKTbnka4FTuHO7IM2HO+R5RbLtJXaHFfW 4hW9+qRpEmQ1DNT+mTH7NW0OMPoyQAFlxq8boMyKOB/sL0++6noyelI3NuWEguwkyXz+IQn/UkWh XOatYLzNCd3Y8NxUlHu2uZWdc/VzuUVKAIJJX5FqD6RdTlgnzeq9hda6hZ5Q5Y1DJN4TegjNQNne l1RUAUmeqqKXLOcwJ/lyFCXhQw/tD+RJxT5wVNsrbsyTrGIcLTBMTGehv2wDYsza6+cbjhN7xpIx R32nIgx+slF6zN6cp2we8F0uhqF4HnP6/BXYXnqgy9MVsBm4hHz/P1SD3JGlitGHcFYkOi5QZsqP +meuEuhVBp8X4u+UXVNugLATDJsYyyQEuhkhabg99t3Fokq4uJn8zhDCPL2pDkSBkvQN93Zu2rg4 t3rK4HpiFYuAa6hNkWK2ru+HkGck22s4Fn4ialYvY8A5ZBb/RPF4rOkfgcgZy7mKKF9qhYhuYzhw KrzJ6G4GuUhuXGZr97PHbNlz9h2+BHO3VWkGmhNxuLc2JGQAa/QtTDCmLA2ijPaneHJpsPW/Cg29 Tan2OsOgDYkJavcGoPOekC+ni6H3C5RbJ6WJdjAkSctpR/8A9sc+0fV1LGnByRu6USjgyZsoMbFb /kNMdbwNM6SLMBLethXqSG5aICM9AodfnM2pp8lKbex94AmggLNL14qNo/oWS448S294p4FSr2Vs HFYr9Dm8XRgty8YIf8Bqjha7kW61rCobaM3N+PjxK2ItJj3e3XWQRfeVUGOx9jpcca3v/w4s6fLf s7oTEsq2Ub09QWXuHo3jEjcvfJYFyLuhr9vkZycbM6z8psmfAHtMNyLtPbm59xa5OYK9uBIcK+yq 9oXx9RkkOOjW/BVWU0KmvNbog1i7WFIbVf4i0dKOHzbstsKfWmyqEdKodHDgRDTNffBsjx1bwJ/I WcvLapR5jJJekCEpAiUNsdP0yaO2b+eVh1KBiU0l/KQ9aeUwY6kAyxpVLsJRJcc9pGWt0s/lFvu1 poIR3yomIFTaiZ7esZHVgYKF+hp+StuMkeGwpb56a1EgpMuAcADeeZWZZH3ezA2fXtzKATffa+JG iM5LYwDVP1AU9un02WhyNDyL/yUwX1p4kf6WDRbWCO6tl19/BvJGan3HemDXD3RSyW8QVfUwSJ2o omoFgxQjpNjk9IHriSXISV2TpSDs9Z7uk7GeCa6Tkon/kACt6ycn3m4uw7KxR90osS3swxpZcP41 E8U5KWGqluHFuH8ztARgKB01hpZsKdoON3QlxKyNn5v4rzSpexaJdMJrCeGWt2La0/LQzy+DS/MS DyrP2Ulxd9xMEjRg7seXaJ/if158EtqcsOL6U+q48FTwl+7mqV4hmFNg4ejU7l09CV+DtgQgdmSc zv1WBOBapSnbLvDcumzGR6+Q29oEdTWgxRbD9MMalpisMPj+4/RHLGuOdztHk2Fs4sbKre31cDOJ cHCt4+HweLFo4qhWSNLFxoHucFqM85uLwEs7Hn3wG/jb4l5y/qOzXeOBlko681XtSD3pSg7mPsGe 1os5G0XN2Aw9V9K6SnrSGhVrbpXZPH699KwUxkSB0/vD7dBEgsHM5j9YWUK4lUdcHji48XA/tQiS RcE0Va+i65QnPlNKX3l+KaJ/jHBWeoIhAo3jzfNdsEAMUVK9bipNu4loVMnWM26UcnocDnsOnWVC lhspUqeTyp/xraWoPBcLRU5PFbQSQ32O90JX0+ms+Cu9PCXWSNcwkZ4bQNlOGwikYJvxxEU5EwSM 8EHuXVpqDGZkZnFTBX1AaVW9kb/7NLU/ug/h/rRVlfK+KjnCM0A30IaXTCQ+zMoRg66K+TJwktKS O1e3yCt9u7Ej6kXlTIftg2ciJ4Ig2VO219WbBcUwsjic4SFC//tQKVYfsQCE4d2T9BTxNxACGK4c XMsYMiedE2iIfc5EKckBdkm7icF5vzGQ8qePahF2Zwp3JRnNMRCvTYLe++1spQYzDaBYklS5gnqu +Lwa/Er4UVgGIvkeef1eeoaQ+4dwHVibKJdTZ7waOWooFtdR9Ljn92AXm3nIwHaMXWGijSjJWSwn it7yJZThEbxabSgurABCrDh/UfYBnOpw2U65pv2FPzr9EFfQDO7CzxAHlC7nNmbxDweN6ckyNOAN 6SjiJF+rGCHtVsfxLNXZtcjX2pwgdZoICrh1Y3o/eKuHk38U+KNPoFu1YghVHKTdYycOX/5HWA6e UP8EAy9TxPgLG7KIdLTn7B1cnDbyUiQ+IGYqXY3LPV4S3lhVZJUZuwcFbwcaMd0FQmTxoqpuJNwe u1Px6e/Y4EFWwWZeO5r0ZIfgP2qNGZRu0m9XnVHyHq8iDErvXrTGgtJm3YeZ4ehZyuKKJQHLkuCF idO/kgQi7vMv00E351MS0ye4zFUx+HWNgjm4HqQ92HrkuTK8ou6tdqA7vLu0XTRQ/242WelB2w5W pTEZuXKC09/C6PNyRyVcQSwIVwZRdFaGWGrUTb+P5RkWNPV9Op4CGA6BAmh1OybRy2/Wq5uCCl8i bO5rTHHJlReEnwQrQUzKIQ7DmCZ2rH4WkKNBilAaskUSbVErQDlOs/gR3gFtoVkV8A4YA4LPLsWB cHVm5BvfaHpzQR2VElVLa5mIIahBu1eFTbzpdlSv6i51vzDUOQHrYmjj09NKiMiQx4fxTVe2Zenq bjxv7Js1zrh6qRDWRJLrpuCU+rPTp7n9/2VY4BwoVHlygj1wp/rlidAaCl7sE/AE/Upu6ajoO0Uu PjRNnm9mAGxRKSdf3GLIQMc74YEEXLBV4OPLrDBSE9Y5kfidW0GKBG5uME0jEMtDWEwNgYQZZHix VyD2xRT0w53ivaFfkRpqZCCUHfEWtQ385VSgoPQmE3ZlN9uTIASD04ijed5KHNpZDtXaSOvGydjy 6rmJvJ+c0cjPyi4x2qyoLuDTAa9PCzSNZze6q6MCQ4k4MY0//7FcS373vK2Al9fsyeazaE6Jg2a0 DdUZt69qJopdrO6nKNBkikQuAB/z2t5z9/NHM1CA4J5XFvMjiphC3aGVkVCxDTmAzI+GxWCiMGl4 RNv0g2N/G7l2//DqfCJQU1sb2DKbEBI/NGwMeDOKhzzVtIG1y7fexzgRCw2biXK7GWBKYXcRb6DU pDITdJb1d3Ch02u6Q5RWPieTU+cfPJEF2/0sawl2LXbTybgNEpbZ+43yzMblsykwD7J9czIMOSzo 6W7NhkpUcP6avGidZD2EfLOSZM9SJsCTSqU111BLIFUBPVERX1RiIArcs8dFnGhm3cPT4SI6KS9z ZWUTh38y1rlj1aUBczY92LuPCCSN79lVnUVT9gZx0cndAsd3U3Suh7qCMSNGeEYpzbbTRmBkiLBD 8xugIv792VDHPa7hpfUCh2epA1C6Bf2BuUEcGE43Y0ZbSjS+Urr7+nlL7XhliOtiplljd7uzmCkn hDl7+bEf91xX+NUc2auZ7k6nog1w/Cf8zHfKCoQzFwM+Y/dxOSW21N7WTxeL7PFA7FWdYuG5uoo+ NRToAlyTtz+uHBkvOr2gHKiVZpSR7Y5yi4zOCsD7evQNAl+suzwFs+cHWkY2ez3nyM/Ki8+dUJ6y JSZ7/3bQltgpmr1erduWKyMooqheb97sLq6rIssxxZhec0Ku0zoFZa+wsVtM/3QxR41J/FRZY0HU Mdn3saHxem6KXw5ylyIYcqId8EnRFwpdM/Ygzoa8/RCVq/9L0MixOvLj/FLCEwUSlYLFm5M6Ht/2 wkITx7mAeHJ31a+BwG8YbjH8Pwnp0G4WQOoQ7o6wz/H2pQpIOIHSy6d6AeBsDgvDP6BPyhfd8tbD F8LpIRGuHqNCcqCFk8RMYchlLhVUxf5HnJxQ0DUUYIe02ra58GXfzOJI/4Sog56J6HKVrZVzT6ZF VP/9CmL0bGHYz5cXJAeYJfln6PpC2P3HaR7W/I6ciXUsJrOoiutECS6gLARrD0Iv1tzknEm24rMu 8/Rt9gy0bw9TL6j7GCPmGtaXuUjVwAaPtxE5sdrUX9L9pWZvTF9Px0s3lpqQ5K3NZmLdij1nQzbh GLh5ozlmTAgNqSxbA5UW3QADWK4gP2/ZcY1PeKztDe3TMaGt1Yttn53f83Ypwytqury9RMVgLf0K 7ziLsYdLaGD7QQWMpK7bhZ+OIqIVjG/xU6BiH7V6vJViHDIRP6Jei3WfQcVtafra+l2V3VuF9bgL Ng2r6Pnde6Vl8hOl062K2J1lIavdL1rzJvh0o0e2AJH6Fcfkj1JiNrpUHGKS0v2gsWqMzlVxGyoO 1GGbgRfL/GnptLAzq4e8kUAd742YfGq7dWO+MA6FsOUXWRmXz72gvU9LGZEjmZhmtEzrStYdKKW0 TviAR2aSbeQvLSlKtG4/AFGvcYTQMcN8SogZk6ThOaRl4LEz+04fDVru533PKkY+usxsTxjH4P5V YupmVyJAsYRyfEJhWrtTUQD8wutZSlD1zXSyZseNn0ihSad4NfMkyxAdrkR6uGNgbFL2/Qpk8YLC wmIhUO4ZObN+DU2CFESK5LgcglGA8VDEESDKt7n0Y9yFpFhbQCkIS4sIubbfwHWX/IuvBbSsfZxY KB4maCC1u5T0qYw9AOpB0ZG79pC2wZ1NVOrewEPJV8u6DMYyGv/fbh7BNV5rb+p4s2bOlhUMJVRz YsndC2js4oUtzJDmZIO2POAhp2ddPRGJaa7knwPY/fW0GChmR21Zf17hQUTLpOC+3Y58RZmHrrZP vbd/v35eV266XidkWTRpj17SmFo3wJ9+AS+fZFSTr3X2g5tAOOIaNXMwAn9NmuH5Ecfj5KH1k8nD PZtI6MvOdCBU2qcQrfv5PQUcb0TzzhOsQluQDOQLttU9BWNDMqlGLYkq6zJpS3vSI+3HQ8M2XH/q z/xsUAWBrSMPSOJ/V7hpk2IEcEWqWFC5a+6mGmQXO3oynvfOEr5kFYyGEFReBAQ5SRq7M2tD3hIJ 6W63jsIAKofAgDgn0aCC2ZS6HfGWYyOKsjM8joqTQW1IYGz3BU6n4Mc5Dx6FiNOAz2TUijBTw7Og hac8xyz/SXZ0zJTbI1Z01RcUF3nWhS3MF0DQUL92nEV/8i9QpnoWY+amw151BFpZMGAtPumIHPKV 5Nv/gMW5pg7R78jZH3+IeQqWe+9MXktBai2DQ2P7WidoUle4sIqsWgw4oTDR8OAANKCyEcX6ai2o OBC20E1h58pUeeGnr72saB1Tt2jpwmLRBDBPDLnOTwWwRn4QccLZvgoHiH8yDY6Tv+YbqQYfpfKQ lCyfy7nqhWZhptycVvri+SKnBsnUrX5spJihrSYQ2h752lmVhXKKSg8fn788xNumz5PbHLmu14RT Q+NZ60542edB1e8GWj0orz4k2QRA4BYokIop5IlS32BRfqF6bQGiBPD+u3TCTmvAoSu2URza+iRj RCDokiXxjnCvUHZn57lUwZ2KgM+8SYVyASwwTUqqUnx7DCM5jLX9TetX2xbmmfcDoKOAGzHW9Cv9 tocC0mDifTHgfvatZY27YfT2ADqNWM1cL3njltPyPZR4CxAnPEQvu4Dbwgh3b42j9OqyORztWy8K Y/TlCNsH06JCHt5jo51d6X8rh9GW3XOQ1S0uU4bfJkMDZCwghOzCAvSMyKONydKKYv1J3kcXT/wv juK0DHy/H30pV5VPF1WP+QvrMQA8RIPQj6OF3DrKjjJ55n37OCc3Uu/dNp78qp3C4N52aOFO0a3t /cd1Na/HQK3JEgYc1Y5zlUGX7goaS0FaRioRjl2NKMAh1ww0rNUU9u96GLkwSMAZPkq8EukhZF0i NlDvL9yXksN3UHem/MOE3YhGAWNei0ianTQVxCgujtvDbNOTakMPZqBtMyZ7+32G1knPSKpBrYUX DvG4+e1qtyjyZPQBw74EatxsDfNkMQlHFYrVYqJo0vHBA1G/zG1cbcaBRWiser4VpjMGdvs74Q48 VaQH/N84QDsaSHSNsh1uJ8kH5mji+NwfojCFWJtlKQG2hr0IGcD5hJ0PkAmznvODeSmrM1aTtpLt /gUqT9PqGs6xVLYSgmTU33bR4EF0a7gDOa2mZMBGjmFTnLnbDAX1eDk4z2ORUIptU+lJGi5dluAg mTek7zLlmWoKHuxUFGxWOT0UuEw+jPQGh2I3XI8TEXSvunG6qqe2+iswae823rNvtDH+uuI2P0PZ t0E5WVg24uCowq9UnWPx5aAFB87dnuKCRQqXbb348XM2Fmiei9/hA+Evwzv+ebxTY5FHQd64aD9I tBvzEwzoCYO9i8A9IHJCBiBPoyexNXHyYHYM8opJYa9fBfm39D2rItKGCy2qUcUi28R5h4fmsVH3 JP5Nb8Rt7yZxlvkg9dj7O8CAXdV3a+Zm1kW4+F1sgi7vPI8MAEY5GWHt2EAWMKpDrbuN6i5qLA2a 0OH1bgrd30AL9xFg4M2iWuuRwMAH9HPUc56F8fPFkdNiVj3Csd+39lz2ubPx46fzoPQcEPbcTTLK S5yIGo2rvVDceFPmtHwjKQam1b/Sejue4S3Yg7V9FohYO+FmEAwoV5Od2jhTVtVNd7wJgKPDq+Zr 9Bou4PKKGlLJiCzyuXAnYT3g3KMWT397tJ05+ZG3ayuQHU2wlzvbvs8jOusDXrn4E5vc8yOLdXdr BHJRfeykzKTgqRqjwTwp622vfuJ/QB6fYTeuVYkNycDcP9/81Ca+NSFtF4HIfN1JGJRUKs4yOuWp Pv0ovqKpwYt0vlc/aMXfqT7xKqq7rbu5RA00u6xJFxrhhSqjNamtpkmJ7wMbThZBzybhNKgiEElm 8pbC6SJQCbpgIOo53RMwb6rsOvSHHyI67UC5jSzelfwssnwG+8JkZLlww1IWn1QQENnhQhNTXrFe bZdHZQVWnLAYLl3lAO2ghaqPWXI1thpgkaJkTT+I9wvmtX0TcG2E8+MdAhBnGpd+ZhMthUaGJwyY nGhp807lgz8Ij4MGPe9q81jLZn1rkul5JsGcF6EX7kUtbLN6LzVi8c8TN9M/ndsczcO/DTWK9jjH GQJHTYU0NZd67axFyq1i93OwvBiIEqeEETuWW6SK82QN0Se0ei4BKl0/Ku14JpIfRPgfq9jtfG9w BHotXCoSwTvjnBlgz7NosLmPMFLYuup5OZY5WRvvdaEHpZTQ0ooYbReXMi0Onw4KqT9wHykeKvIN ixYYPM5OEBQuQdBkATiU8+i+oT58bIuYU1LBsjogunfcL17uL0BDvphhM9Vczpe04l6KmVlFKTIb AJ4pcGblP46HNcw16n62i2p6H5a6btF6UQDHx3kGOBzPwCM1d98AVzDOy63BkDV7ask0W6CPJkyd dG/74u6Vr7hMzzlzAtTVUecB+Y9gafD5zDHUEgRIsKF/p57OqEKaFHqzxZFnl2RaSt5pQ7NgjpM+ iWaHw0fkKUu8ZFuAZwmkIsHgcJwqvhZ/X0JEwQWvcpMt0fnv9eCJFDxzqtjkxAYoNEayIjZ+84BE L6KhzNbBUKyZHGcJU7AvpAyXQGOH8UwtKytftq9k/qSiNYvQlEgY7oHvq8mM5yVjICwnFUCtQRzC 7OZ5mPaPZflleRqIW7k8KAjGzPZVUL2NFQP44/i0TC9h09XcTWURU+Wl70HJkwcvkVEM/JomHNUU ZUE+OUKjGhyWUsxy3x9kwZT1hG0pbm1mmeflFZNusUPzsQPWvc5l3jrIQ+2izE6GWaQOuT9jD52I Jj4pergtl9oul/fdavYaMvaITrdjHk6PRd6uqtwwk5TG79KTVaBSqqPIv5bugj2FGp3nK+TZIUmf 6fbqhJoxJYfdOZpy2gM7tFsGS22HoPuWXsYDL55Aszje0Uk/TY6JnL30HmlRjiXn0d24/JVj8ixM WQHpMbqvZnf2x0RFCG4qqHI2j4cRU27JLYEFmjxn0nWfOEDQtdcn50uR0vEjWpK8O8KWXGxbBlwl KwpUyc4Xq+D/SwNM0kYL9rmiEJCR7e8YG0e5ZUs30kpOZLkZjmULGE8djvkVWYUwgjyM2tzTsKFq SZ/fLHQx3q4poxpIP+XCm//LMhp0+7KCk46QitAkYoT9wrHBoiCVDfT4xvnbclxVqMPkYopbBNRH jzB9CyLseaNV69XAqpJvZgYx1h51lIsglDie19Io2+5bJso/2qNkbOji3Flx8q7swiHVi8cxucOD 2VI8RwyuLIHqPSSmG+X/yl6yoY4gnjzoN+Jfspy95jpbPsQIG2QH7MjPd+7WI5/J+Se0ziP7gvwh rWQh8Pi2fcYDsu/7EU9BaKIdjhDgpF/9hAXitj1eUaQpzuP6CsB8PeyRgy9SQKzheVf58jYjO6Mv CISkEom5fj4AAjcnVX3J8FHwuz+Zu44AqM1cqE0TRpLjW0cEdWpM64yGR1i7IqjHM1WAH5Ncg3Ow 1hW+TuEsfZdTxl2oS4LFK/JSgZGtE2eWDAv8xIyH7LXSTPCi4u1fc519fILZkp91FJA05MwnELNF Guju9yHSCiz81miogNM7UB/S+KxY5mqZiP2rCz3sEorrEKdoZC6HKNCXH9esSK5yxsPJS3LBdxqR YbBESxjq/Sc0GRZ1nm+fyKl0eJoPf/Bxhsv+fvh9HCVcNTK/nvCZezB4usRQ3xJJey9VDXP5qfOb MuBRQvJVKOGZbZZE9nN8V1LXf0R98RWhAnBipBr94Pbf8hrxx5UZUeAWci8K9CXlszgq6713Q/4P YqP48qMNflfKQ1mQ5/iCUPU7AQvpV3p5VeVE9LtnpTqJHDRkw32E1IDcomMFZdtxwpeEt8d2Eo/j 36vnFqrpr4Lz+GyStA+7AUIdMOfkCScqzwkju6iPp6HBnyUkHUlKDGSh4LMQSegM97z4UbHJKK1K o23vCN1LIlrxlJQ0SRDCDy/GBIJBpmTQ1xJ5Ounl+n1Q2WVs2+oJwUDTjBzE90aNo8/z+MD2um2A n1Uvgqw6bOuCrfeFoRxYVk+SIH2oJWO4sXsGHd5LejrZDbc/HsdpAPbxfWKpSn9/o9TJriWgEhfI Zwcj7320Ifm3agYAIk/dHM4GdvZL1P0xSgbJMxkF1A5OriTjKzr62HFS2DKQ5da+FAiGFhJSx7sj XPxhYZww8xhgruCSUW36qtExGWO6UnDxw4MJ/j5wtBuG3l943bc+oTSp+bq8IYAETdVelUEiMO9h MxkTF4vJ/72PmfOcXT3eaqguyoC6BGOz93lzJcQu5z0G/exFBOUwQOBJW6SCAEnjAoV7JRfN4gZs 5LY1KpDmKXc3EOZT419jmHudOsJGrfpH+Y5CLJMhQ9u0ZqMfOr5tSFWuNBYutKAgsUg2ne18fNT6 /hzNJ2oqU0g8uVrWyUvCCLCCNkUwO4EU2Pye5NM5J0g1TjfY9wWU5iUSRxlHESi1foBw8JvuUpgU Cj6KeC6/5VQIPbbH+e03VW+bFxJYCTfvGbh3kRvx10g65xVgIEz6IUm9Cv8IRiDxF9f94HvHlCNS zMHqIQWb4V0f6wY0JDaVIC3pI+oT3dIudp+5yeV/Np2NQUESAucQfdpJg8OyIoppdfkkE08dxq6L PWvkIoyLjESxpgDj7m68UNiUnV0AxVtcgi588p6W3bHovz2uX2rBMNnJcpC1BXF9N73xDxdYvyjd 5JN1LunDS+fnLKWPpMAixM3QOOh2nkUg7ofI7IycCUXGfjbJ59FsjjYqxk3xlhfoKHTIiAMrKg+i dVJgtPjSCD0Y8tP7d3HM31IcRtO0gXTGIK2ql/gSyaupc+eoaDq6XkqVA7b2gqiWsbZVSDxh+sws bh/2gT3UR9tOLf047/azXCmxZOEabkuuXd0Y5HP4Xp7sXSEvcBOSO4x2UJgAXJtOOTlc1hz1fY9+ DxHTxyXHf7afhTcUkznftF2AIe04BE2iFUWPvQ6sbwav2mTSJSYHsieFzMwJ1dBy6F8XHGBt0X05 EFhFD6wf+VblDCo7hdpnTorSZ6uXAuhETC5jAyBVMjAmk5q70ch0iYNB9ObiVL+Z0rEvKByNslrO HOZkFzmc3fB+xq1XV8qANpXAuwPthQiVSr7kWsX9Xv0qBARcgt8En+hBXOexcqkTCpb4SN+zbsQd /18sSiTt5Zu5cu3hJJa9CkcEtaMg2hUI4xUYX0umWWeB5W0i8NUVqUYIoOoomZltpcyPgXUW7VQi 18tdnRPTWTEyCtbrUGui+zVmUdqZOTXyZfgatR1UdxA+t2g1z+JF87X/COmUX6x/jKuGLCoZEKwC yvT5tbCV3cdI8XF0jXW636T/ZyAmjs2Stmzm9zn8Vf2HDVRRqV+hwNFBHdOrY1VUN9FfPtEzB+b9 hWc2UXR4oZA1Osp0UNuzGfO/aXGt9KVfQOIrlfKVAKU8P7VnVm5Mbzs2fye71bETisWfzpgEzauc YIKEUWpjNtmnGDsSxBlt9VVG6IMBo1LGZ+PWbZNbpMjfxcFAlFjE01EAZuKgYb0Brn+mWzPY5RT9 f8WxNrcCMCRN5OmBNfMaIGcof2e4xps0yHsNQvVI6Lj0i9ptNF5DfUgSjlFhERi0q/idEZt5Xfuf Gyo2mBbkiZA4ve6+JzTSIhBTC982ytqKqjm4OXSJq+7rpyj64kgVEI9bxxB2M6avhQil3OuRPHBH Sz4JC9jC6AhRbC0Jei9CUaATr56wx0J+nYT9FJmY0pU7Smv3FGmvDuFyiDSSs/vN35GVjEUcd0qS xvvWMh5XeoK+8ip/0EOMs2y6wC8tIXYHNL8ipmZfU3ChFoxHtXsRYUlvI/GDCMi2UOJn2cDuZ1Rx enyoxiLjE+V+VVydEoxOUSQv2WyEwfQbTEAjp/2wB+VU9WscNm0LwoNnWzpUf8p+rUcS89HL9Fqy r90WhDmAdg0OlRReIo/yyTA2awmiB/A5qMmwrEj6jW/+Qdr6FkiwerJtUd6ZS6YfgnUmWjcAh0Q2 wVJUqYgtuFyCcqWAMktQiiZyLkbBp03f+k61GJ/NKotlJBqssoN5EC3YiheQRZiuFwZEFn+F+BAH lgSQL+30bbsf/qOuXHKquRVk8L7sPucgHZHJMjLXZUSIPYwv5zwFFv6PHkBdkNicXw5QQVTt2c8D BUferjogCHYhhYslTkMALKrr17vFFcbdOHPJ2fr5sbJ59lme9XCt7yK06qUNo/oRIId7FVL6PCe+ qgO1E+oipN6JdVy8S0W83IlP9G6svWmontD/h5kuFeaTdgYW+pgg8i8ByFC6qEFXegDllwryWd2E dImhmGn4pAE040lnmB3C94G5UFu5KYJYZvSEXvmC+Oue1yJfg8kEJWbVktYh8RL9goQIVGEoUO7Q 01D9UqKKrkkSyJp1er6CZucRqwQGCTeTCdNY2/0xVjT8fQv1odd/IBxVpVK1J+2viZespqJhS/R9 4zWNrqv/L5a1sWd1P9K6l5h8ngnDtxf0E7fj6rJa8zEloVemYOlTHguYsPhxWr53mDq49ZbLRILC YJuiMLYQUAeDmHtfIchxyjc6W+A+nAbsyOWqiFY6x+Y8UuuAQ5TMxaDxaAnZpWHqKxQwMM/gLC2J arqAX4vgM4GtymnWd7Lnj0jwE3uSvpUbt0AeGBAvdw/50J6bN47G3tjcJEDzjTLB+/SGBJiYP59V Gv8V2r4hakR1qBwNP79yWVWLD9mC/6vic/DVPgJg06e8ZrH/AQ9zht6ZGAIK7oS/wh0mzOBUBkhI aMs01Lo7eKhVxRzknpxDXeytnl+LK/lOSCRK7+tnCMaHdrHBRAXURIzLdEA3qCmfW+Rb0itbQMdW X3J9zfkixVOsyoYS2E6luPX9YcxyYuzpwTtEnF4ILRLfA2otlS0l0lQ4SGaYlBZr31RB6yY923FL F0WxerAOqsR9PkNtu+KmoyPdJs0f2zpHOQ8DI0dLiSDtcCIHxep/rsewFCZEyr0pDfercZAjhL9j dyvJoRXEFOi5oc17em5I6Pi5jb/ItvEK3cUa8mt/6agM6brsup97gXiJ1NrX+hjYx03FZbVh4hS7 sbbXc/67IuYdgq5qmAUMYP4KwzVUDbdmM8DgiO5YVxfLI2z3k3yHnGydLUlp/W0Lw4EoGmHzE2Fd bgP5bW9m8aOUW4Ia+l5L5kgHYF6bznURQelA5poZqEtQL9o5EvgJdu240vQMmdfMutweYHihg/Ft nsn3gLDZ/6knQPARo758AjqGwahLuVLR/Mm80kH6/2JLbj8FsjbD5T86ZISruBuHofB1EntqdqPD 39cGKswKwSFwFSk5oEOxSS0MQh3DXfYsbI8FmRggpm+u109J5OleGmPVeGCqOPW3KgMQZeeugCdm selcS7fCh9JYfVaQy25dkuVrnUdWAGPXSweDuYHnxcfC6XB/lEuJnZmpIWnQoFXWkGEKTN0UvBd0 P5fPjtALLEG45SJeG6NHD5b8KVvlxtpPuTu+3XcQsbqoJMkaqghhESSMM8qtJuyER4zXjh7TShv9 UX7y3fmbLGP1PqPOXwylccanvPhnM6l6pim16U8+i4F0Jj0yD1uWRaPwy+zsppBPnafoocLh3oYG /QV7QQhsWArd2Rsse0Bc8gKnzuXdSpCExXl6L+f28iVYCMuW8/hiXZJan0YVhYQ9t9IBnEA6fYOo Lr+EnHHoBzkAkXpLfkRsUFjRwuem4TRdWaHdr1zgmA9V+N6QVBqXTqZSRD8aN/rBnJYv33BNb7nS J5ZBhzhs4sj45p9sZ7tfetZmyQrg8GCeuMeIrjoRnsBfmrdVpq8I0w/rBHLrvzX+Pc/MPk9MFtxA ym4PdKeLSPK1s9yRM1B6OugOjkjoh/hJ3GMmdtoCkAWMGSSd7x1PZN3cFylUyUDKQXOoCcSUGJKG t8deaRJcUgzI1nqMxtZ9kh8YBTlFnSwxJXNt+n1FmelGvlxQygnC8DqiJ7BXSESu38wqmoo+3rZf WNWsS04RuV325SinYy/k+tlgoQpNumjnLXF/hfqn8B/eSB96Cot4YpVNwoYzGIlapE+zqnCtGuB6 nfZWw1MjjhLZbFXUHC5PZqXHPC5kVUsADaJoukpJ6x6DpKKPDCB+NtkpVdd3ZlOjnOR2Fa2rvLNe tGU1qCf4/V0PM1nF7gIoWo+9gjo/ytENFyA2Ws7sLX2fHDur7Kp9xXWFRqF3Vvs11HrHidqSC00/ YRyEDD6dyf2Y2uHnQLi7P8p7CUQX8KrmVmhdbAdKEA5VnA6wLWSfE2KZX/FGudUVk3Wt9RUOzzgL wXom08jurTSEtyoolXnhfYwXSUmgxjz4h+YFHlfeqN5k1cEy35XQAUpAtJpKtXDhGP/k0leD9Q58 tRPmYsUGJ78lwXOq5R5p8nhFNnHAdr7oMSD7GRZeS4/1gYlQH4AIp7XhakIPbKTRduu+hM6cDzCB QpVgRUGrnfrXnsvDGgGF5av0CYb9Y7HLdRUGZpzUoRYlCUP7vTPuHENJaJW+S1KZBTOCCzd0/S5w g9ECLvi1TgSY1smyd5aGOvmpw4EGXJlEtRQVyhu00taBLXDAblKSJeLgdmJkhv3N9MYaUZWvtJEo 0il+7LzCVyn+cu7lyFeG0rFR3npH0lBJ42VS2qJ2RcseeSy+/jVyHdCUGeLKagd2vWNG42MYsnob Ekjom4Au4gl45hZnuk9fAR+gnebzYwHcFj+O5ITEQukmkBTC3kQgLnNd+9CAli8uu+zyJ2igP4Fx 7sbRuSmoWEl2S5Ov6MYdN99i9oc0MyIT7HZT+WrZONFu3A8wFNSOsQS0RAnqro3sbUQr6FeppNvh eywIkBo6A2pUFUfAExI6NY0mI/3WmQVwNYKM+i+bvH+80g7RWr5bMeG29qi+Nm0/yxm4ZiE3H6BV /ZP2KyvfCCapI3U4Bfv0OtNPK6KHBWwVnREtXE0qqAL0un9lWdoLEk/mamemK8qWDFrdULKLxxlf 3436Up3Psy1qNmupF47dZ5WTOBxGXua1mYwpvU41qB40NQ7CAEtA3Dap7n/agaTDRRt3xe87RaAF 0zQwNZ6bDUk0ZcN/rGIrNSEeuq7lpE7smriwjcydRsvRJgj+VNW336wXdz5J/gsU8mKTvs4pJSkS GdOnU9bGzJrgb7M41zS1pFYTdHUI21YW5P1qQap6vdfE5TAOqeKB8Fw3J+r52p9CQTGhXNFoUBP7 o8dXLxkgphalqempcNiITuQeuBn+rvqIwXL5eY6RNqcFHNB16B0ONGlcusr6rza0sfIok3nuaGFo YmYhlZnDQxcylzIhlNid/wiUCdqxwHTVTcinRpYHmSFizr+oCXCpznHgD5P6Ak/xr0tbP9KSktDf WPsoawS0oEVVQUo5ZRf2SmjuJgL5VqQj2Bchi8NSC7PUa0gJQGNL4qV7sygeN1j2EHFFs96kRppB hJlKGdrTXQ5eJ9vfpePTaGzMliAiFwQv81wQMZfWPA3+lsFTFNz+PpFoPMbYsUZe9x9lYtsDTfpQ ml6c+032EGss+LYcQPvLcMv4Ix3h5nwXE237c12PsZHt6nrqh3+TMQAqkPhplmyblQRSicbap2uC aRWQ9QAs3JAyoGim/2RNCNQGWAfyup6U5qmYoFA968nHKPO1/vXvF9cTShbnvuIE0SOzkUaVrLnc ig0oSj+fYlFOLAGJjdjfIhfaJgiSJBhvmZ8By1ZknBj97b3BxLPR83HF8UGRg/O4SYh7TX+dnVcJ ao7kJcgeAqm/r+BftahJGUNH+Qnyg4pyGu0kT9Lp+ADnPwpgPFAt6GKb9U0QmhkUDRiS+qD1lgJK fw3DACUvDJMVvVeH7IB4jfsj9DZf2ed7NJZnUM8PFtikSIUmOpDE/w/VtCBGZ+etZUtTi/0KVDHe B9BfYpFjShqFuWZVFlxK2JNETDiC8c9OdWBUIlPx9o+kj2Nw0mplGsa65ASGyZtIkB9XPSODVjii i1QeQGfXY8TG9xyc0ixPhpEmcTBPyLstdloZJZvX5Bxlwr6TRkU29xGekUMAJkDV2i3drQxHIzbt QpuNDgdM5p2KGhrJXqvBUQ6zC13JTmBPf9pzgfaM8WTbQvG5lJSU92zC41giQ9aAwVCjF2Gal6Sf 7xDRo4TyvwxisHxfE8CkuPvkzOAoOsdmdJMCT1/IYK/HjjfIGjt/89KZ8T7vow5RkPJd+RTg/LWV XCY+shCAaNTgdZ4eT2jS7QsCC81HIRiFSXngY1VK5UlTIiUYRkMDc7s9C+YXU/Y6ty//pLOhMa1C guq0168iLp1CRexo1R043inOXeDcJyc0NnyQA1YIfJBwlRooXOofnCe9f+LzPPcU74PPur3seiPB AnnQ/PeaZLo3vujRDZgimgqeXEs3batgV8mr2OfwQ3NgVoKI5WaIHpgDK4RffZGW/n7EMbhBrBHr qH2QKYVhN6cfgRPWd/nNAmHUnrgrzokzrOmUqvFVriKFNbBqDDUJYZBpnVgh5MBQQtbMLr5DvU02 09L4N1iaVfjclL1IeXRlREMrwWCn4RyDtnpdcxWdraVj/zODEHsA9jLkgDNtb8IyG2OOZ6nlHwys KLBrLImUnRbLmeNZ7eN51GO2MiOcOhh2QMn/SbyzPGCXRgxoA/oRPhR8z9Jx3ucslv0tUwXqlryS 18K0g20yko60NvH/wcPwF9jGhX1eF+kvICWUf4wjZWAqcJkFIcSMhoLeybVTsc2GWY6a+lOKUeoW pO43CwxBy/+LlHlE0iNCfrvybxHhRGxR5R7fhRIIOZt7AoqnyYmfAsFNKdddOCYNviuFXqtmW+0Q EFYMWJrbBTGrnbkY/mE+ZcWksqHI5s8RtM5CIX9brkKiTjRvo/6dJj1YOqgjKRvbb4VBFfm2gLh0 9NfqPFcUAQhynxrDah2cT5RRfGnkpbiugVX2MKN+XsUU3N1+Mpv7LjChSEVVxVUv00442zf40t46 YW97pmRkt2hVuMVv31/NVGF7bJ9DUEHo7Ywcq489k66mLy+C4l8/37jw+fXx1fMOW423HLlOqAsm INwvhEi5i/gyj1FAckTRrVjGuYdPeEG6kojPj1JXgEKPWyxkJVg3Yk89t/P9IoT4xND1LSGYSIks 5GZ1QEC3RZhNSU4IwwO2rlOdextKaApK9sHb2yB2GBjLRcK744EOPM0aXZZ1bsN8sOS0m1MamSrK kk7LZDUZADbyJCI4bxQ3Kyo5Y3dT2XpYC0eOx0UzFHBjnMxEIDSlAOrMpsoR64fKdYOgTvvb0jTc p+4uGySvXcQeeLbygZ7ZPR5WSSkB1MBOTKD//ftGda6dLd7OhjFAu/VWqy032pljsubfUm2co83k ZxOloZovn4dJ7TFDJMifV9p84fvN/L0DyKlqglZS9codOIT+zeCcxJCTsxbHBO6GIXAEVzpok/Ng xRchvYOO9fyXhg1EDzJNjo30l7bMAcUkLh8wRd7U4RFmWvarY3E+J6PjzJR9Q4vYNRlA7yBXgZPl q/FmB+Nii/Zwj/NJW7Ks/21TkxDXvml5lnr2GJynq9DxvOmkqovmxTDAYj7yUYX3NaTqqXLdOMCH DC4Ok3d6b4ZsmPC+ie+ZF+7TeE1uYRPdRTZ1wwvtCZTZDYmzoJVmJkIknpmqOa1Uuxz8EwnQ//tv rdc6ihiBRhNAXqrmygniVlnGcQzM59rcVXaJ+ZeSh5Vx6gJLuuRI0nk4InEjY+hNU//XWjmpgCsE VVC9JzcnQ5Bi7G1hXR2bpH62lHrttZWEKCJKHMsDgI3R4o3mowSmBCzPQxZ4Q05+BW4o38HlHyis Qg7CRWGip7DOexA2ynsoJHzbLglKRBwr0Bf8O82thpsIj74c9+zpaupkvjOrWeJN9UsgqHrQPheI IWm8ZqgUR7VTCeZLbwx4QhC6On926mFrvdT5fwEsiRDWcj6ao7sS6lIUz3rAKapwCgPyCEZUTeKc aVBkEXIn1fIW1zvsxMTk49AzTQxVPzEERu0/16nfasgugmIch8tvQRqD/OqzJY2w5Lu/Texqdjn9 nvtfS82kvrRwn7kEW8xc3viZt8vPLU0kxN+G+zFXhIOq21+1Sg4KZyP6bl1LcUAqFvLSIbLrBCK7 FJoMI6a7PjUmB+QtJvQXssbjDZf667xmnmJOp83EOA0= `protect end_protected	bsd-2-clause	fd47621c4d17c2a1bc0f54a5b8ff6b44	0.950024	1.825695	false	false	false	false
rjarzmik/mips_processor	Caches/memory_tagmem_internal.vhd	1	4,755	------------------------------------------------------------------------------- -- Title : Tags memory with arrays implementation -- Project : MIPS processor implementation, compatible MIPS-1 ------------------------------------------------------------------------------- -- File : memory_tagmem_internal.vhd -- Author : Robert Jarzmik (Intel) <[email protected]> -- Company : -- Created : 2016-12-15 -- Last update: 2016-12-30 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-15 1.0 rjarzmik Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cache_defs.tag_entry_t; use work.cache_defs.TAG_ENTRY_EMPTY; ------------------------------------------------------------------------------- entity memory_tagmem_internal is generic ( ADDR_WIDTH : integer := 7; DEBUG_IDX : natural := 0; DEBUG : boolean := false ); port ( clock : in std_logic; raddr : in std_logic_vector (ADDR_WIDTH - 1 downto 0); waddr : in std_logic_vector (ADDR_WIDTH - 1 downto 0); data : in tag_entry_t; rren : in std_logic; wren : in std_logic; q : out tag_entry_t := TAG_ENTRY_EMPTY ); end entity memory_tagmem_internal; architecture infer of memory_tagmem_internal is constant blen : natural := ((TAG_ENTRY_EMPTY.tag'length + TAG_ENTRY_EMPTY.valids'length + TAG_ENTRY_EMPTY.dirtys'length + TAG_ENTRY_EMPTY.ctxt'length + 7) / 8) * 8; type mem_block_t is array(0 to 2**ADDR_WIDTH - 1) of std_logic_vector (blen - 1 downto 0); constant MEMORY_RESET : mem_block_t := (others => (others => '0')); signal memory : mem_block_t := MEMORY_RESET; signal raddr_reg : std_logic_vector (ADDR_WIDTH - 1 downto 0) := (others => '0'); signal rdata : tag_entry_t; signal bypass_waddr : std_logic_vector (ADDR_WIDTH - 1 downto 0); signal bypass_wren : std_logic; signal bypass_wdata : tag_entry_t; function to_tag_entry_t(slv : std_logic_vector(blen - 1 downto 0)) return tag_entry_t is variable o : tag_entry_t; variable i : natural := 0; begin o.tag := slv(i + o.tag'length - 1 downto i); i := i + o.tag'length; o.valids := slv(i + o.valids'length - 1 downto i); i := i + o.valids'length; o.dirtys := slv(i + o.dirtys'length - 1 downto i); i := i + o.dirtys'length; o.ctxt := slv(i + o.ctxt'length - 1 downto i); return o; end function to_tag_entry_t; function to_std_logic_vector(te : tag_entry_t) return std_logic_vector is variable slv : std_logic_vector(blen - 1 downto 0); variable i : natural := 0; begin slv(i + te.tag'length - 1 downto i) := te.tag; i := i + te.tag'length; slv(i + te.valids'length - 1 downto i) := te.valids; i := i + te.valids'length; slv(i + te.dirtys'length - 1 downto i) := te.dirtys; i := i + te.dirtys'length; slv(i + te.ctxt'length - 1 downto i) := te.ctxt; return slv; end function to_std_logic_vector; begin -- architecture str process(clock, memory, raddr_reg, waddr, wren, data, rdata, bypass_waddr, bypass_wren, bypass_wdata) begin if rising_edge(clock) then if rren = '1' then raddr_reg <= raddr; end if; bypass_wren <= wren; bypass_waddr <= waddr; bypass_wdata <= data; if wren = '1' then memory(to_integer(unsigned(waddr))) <= to_std_logic_vector(data); -- pragma translate_off if DEBUG then report "Tmem(" & integer'image(DEBUG_IDX) & "): [0x" & to_hstring(waddr) & "] <= (" & "tag=" & to_hstring(data.tag) & " ctxt=" & to_hstring(data.ctxt) & " valids=" & to_bstring(data.valids) & " dirtys=" & to_bstring(data.dirtys) & ")"; end if; -- pragma translate_on end if; end if; rdata <= to_tag_entry_t(memory(to_integer(unsigned(raddr_reg)))); if raddr_reg = bypass_waddr and bypass_wren = '1' then q <= bypass_wdata; else q <= rdata; end if; end process; end architecture infer;	gpl-3.0	e70fbe8e5f84512a7714a21620219d3e	0.498212	3.674652	false	false	false	false
cwilkens/ecen4024-microphone-array	microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cascaded_integrator_comb_funcsim.vhdl	1	528,561	-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014 -- Date : Fri Sep 26 21:45:05 2014 -- Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cascaded_integrator_comb_funcsim.vhdl -- Design : cascaded_integrator_comb -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a100tcsg324-1 -- -------------------------------------------------------------------------------- `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 201664) `protect data_block 01Q5om3T0jCWxQJMbPhryVrOuGifBYcZDUP8T0QtHy75UmU3O5m8uX51FqSh5mZRqJB2aCiEihLs PWSaAvVnF0gG0owiHlIuHCWeL/iBQqlxCFK0vq2u+ArJEahDPzCfJnMZgKGrIuYD59aAJyL569fD zB+20DmFuR0Rg6Hni4Q2Rldua42fLHgsmoVciKe1Iq2y/RMoPT/U8OHdGvw6Wkb/M/9LHvjZQRU8 Hr6Qz30q9LjEMGVK3CDmLbbbKh4HUTZih/Tu9WrZWeAVaSpvBx807QEAzINcoEIjxMSP6UCgS6bk Y5inGMlhwxdRugO1Fq5KpvbyKAWyPob16zzQmTNrVhR1+yRu7zxnmBbDKKOj2Iz0LwhrQt/XDp4a 7QHmXGvpB8+nLEa71RAxntZSlUvtRVztEb19C6xxCyUg9p/bLZrTngw0dY8yYiP27iszi3VadSB9 l8iM8Qm6DKjN2hNSNBv4E3YHBU0v9eRZvteKFq+luMRODAzIJ5tlGfiwe5I6xitxtq3gZ42g4Ybw 1d7jUc+UV6TAqutkIQB9r5VwWwb9rndOl7ccnNCqHpoAIsuVpAMNCRkRZ9hyzavs2wu8luzaWlHE XIHJSflpY8h9RE4kpCpQPAUY6iuNmUupZDam8I5pcrmHVDI2FgqyzTzDzSPk9J43JnGzDh8FSo7T TXqs4IkJqUMmHohvGz5rpD9rR2X2VuRgEcoEVNjfG+iu52ny9Flco/aporshH5vubaO7MhiepExQ axqe/zg3D2Sp022cbhP+p7fjYiLlY4B/ZIyyXTNmk5L9b/ZfSEOV4UzoaRYbbXM0x5cp3FVrFO+y MR3YRLzkKytWW//1WKYU1NtHBd9WVE8ROewwsn2g5sxK7IouOZimrBfKamAhMxgeCQoLZP1IEtw4 7o5DP6pTt2UD6qNJ25yXT8UnOSf++ngwSkz8p9eGs5bi8D3jB7LOCQb7BT6qm4u5iT1FXbe7rSma reba8XLrwAl8Gyv+EE1e84j74byCFjN+aNBYsmZlz/i8h33b57BZ+0zkidWAsnqZllXTKSh6LKVG 9CPGUWEQBG9MShItZFdKUbi9ZgFwcptdarZeSLQAN/7vSe86OZ3AfAPEQoJTQrnNCEg28Blb2q9c laLpdBr4Ng1IcQM97Gp7qI0NqS7cZnhaTqZPmVWBytEWM41LImKv7QlYzGZDTYF9XdRgk4idddCH aAGEBsjFMN7BdxPuwRH7ESvSHi56d+NsCkF62MIon5lMuXKbrpqt3OLdi2Ln4E6LZvKJCNZH9ewz 70AErybauLTlzM5Em1YC9Wa32pCx5HXeLLT3kpeiHj+d0UtITrgCkgkuFiRoYZ5Ix0XMl4bRl7g3 PHbnKtVp35UM/3n6hJY0WKs7vlI5kzPOT3r0/KFt12NVcGDJwbMyCC3KPfFLCOWloiMcmUz0nw4A KTsV2roiw3rY0skJ/oCKUBV2K/37yoU9Ai5gdPysnIvWG6Qa0PTpI/ai9n6gbG4anTXNB97udMVK TnFPywA8tVTKkI44b4J+JOsZ7CYVH4uLUHDgSgyTdNxsAytfRn7IqHq/5iIQ8mpgxj/g29zGAk+C MuoGyYXOk1JJsjfELHYTv69lUM+kBzru4nVbD5eExnTVhD/wboXJR1Mp46QVdsv3ZrqG0WYzd2ON v2p+e5ebK8OuvfTIZxjv36FnqMvlaESXhKGQZ1DU6mKk7HwGQO1qev2c1WO5I/0N1+NXNlSdWndF 77srgcweLTOdnfVaBlGOOmEOn2ePCDVSTGQchtInyhhHfqXACFP0NWODNXL0froqo24W/p5fvdUY wtqjuUPwY32E9O3Vw86RWiOGyVYqqz8iR5I1IH+HyT8Y6Fnok9mbka3419JRNnRpdT/pKuY7czdr SEGPSpQMBuiKGYddK32pb+b2YE0zrLSh4b2kVLOFonNLt91ADBTyGCgGk6N+7s1uidgsaqYJuw88 +xuQL/6BWDouIU9WSB/G6Q3dsAKVtSG61QG4g8+Q+Is9X2fyVpFPdtwWARDGsvBQffsFe4nkIAAM 1bKH0NkI/kbSx9Ig0Lw0KYv2ao6Jtt/mB8HuYam0+0NlLEbTYpayfv+6ngJEgUWhonY/iSFwae74 V7EMLjex8Gy85vtMGbpNr8PQp4+wv+BveVaP+El8WOlxuqNDSxDAufIpFgNzEUQQX019qT3tLpLK 334WMzc4lYdSKttXmAe0pQccavQAqtI3yr/G02MmUgqDycpSMg//e/29GhkDRhnE+A4dPx9WNC+A prV2fwlRCC7QP0iD0U2XiWYrugyMEa/21JS6US0g3Vil5EJgXo5CzoL5gE754hUZnLSbnADBTmKY TXaTGpGlnAiCA+zpQzuzAvhep2DsFE7dgDh3VoLUmr6H2fq12pm1GKkoGKw1E+4bIJyF7KSgfFhW Ha5BIteqJCOkPLrNENpNuZ9iayjrUseAjnQ+9L5tZlz3rO5D7pwNvVBELpDPnsypj5j7Npbqx4RO 9LL01vFA0TjYr/WA8enzr6XJ+oa43mqWMPE0k7brB+c8aEcTmJdiN9/ReB2Ek63XrmREeEmiCT9z JUe1LHSJF0Z2S//vUAM3j5ToG4xREAey8tdSH5+ES94vRrU9ftMxKMe+lQHAljjW0oGEbZpvpB29 lnfkArfUAGx2DCIf2euHIKm9gMsL5CPrdK3clGifYXyTJmIS47Xs95kGQr/lgs9WJ+8JAWRPPuhO /UvjGXvt9aMMGfkBhFWi70rqP1Nc/2O0Q7bfb905O27Dhq+X5nsAJOvxTc16RDDvz2rQD38gkS76 UW0dB9Gmh8+EyRCq9sDKpnH1R0sWOmmA/FB7N3Lfcf+9IcBcRHjQ6xtJo8iKIc4zE8Som7kMxSOF 5LfCgsjfVH0ZwEW/n99aMMhnvHlGmekZQyffZJ9mHz6dy+3GZsYFpuUE9sp7+0EvZoeDhgLcOPDB bZVMoNulDAfHaYlm2o93hOExXBBZJF9+DGLBCMj0meCI/0A73k/CjWLCUwxE8pUIQcOrtWTPuHJQ cTnzoOIAxR1NIyq0CRJJdHDN3A/hnKAcOqeRwbS+0VduOqydj2QFYvoh7nMUeQxECdlNvSDwJXgq fm4TO61JkQOOflsh9dyH9ErAAto9uX9wd1YF+N4z5vUJNvyRaQYn9SsL9i5ZvvErQ7OcFWZD5Udh 2hFW+EUG0e2K7FDGDO2qKLPCpoH2RFRaXhfhdn0BntqGexUa+1+ZYLXX3PvAgF8jguNI4rcpdEKM FPbRb5Bf75JNVRHYrWS9n1K8pUbd07xumhGGH7NFR342a6mPI2sclgC8tQufwut+tUsMJqMVhwTY hxuwyNNACu9O73zBJjqdW+SJFJVc/ndYjmxdiaUh3sfCevqxC2rCC4DbEBUvmbtmbI1BpEIk4OOd /GJ3dkN7cokTbxjJsdgDDRyDzsSVTFkR1qRrpzBJAeaj6AYpUkilwbVzwm1WTrPw7arQFX8VyYkK acmLqtnqGhJhXh8EDzbMajaqQp6M6geLG/juqoknNdXjaZ4Tj3C9rrZQoE5YZQMSScPqxM2eTbLj qIEEkfruSVP+DtpD7AK4YiAaN2IfnVapCQKCVyTtoVGQAHBlCPcK2JO8Y+8kEAkbSOp4/DxAxZUt BtoVZih7T6zwhuJ6dZU3RwOeBetPmWUHE+YCmNBPjp22xHyK8KFJHPwd+YBSd3v7g13bkxGpVbbh lK9uDeXh4c7QPs72n0oVUiWrXczBAxhfF7ljXg2cksU+HSw4Iiw2MbQMgJGHmhsgbBoV9GCjPnh1 NmXEacOkm987h8D1g06j5IMpk0Oidv0JPo8EVe+Z19zB+bDg3paOKBZXCghf0/B/z+2mSXxuGpGB ixCyGWfkAOcb8YcB+bptmfwh3BSDYA50X/RP6aDk4FI8J9De0A0u+Jw/mB0ZQnbGK8UdlpXCjmYT l8TFmH8jQEMtOJBXBv1XdnW2S0RCwdyNPeGtASLD0KuEsJOdfvTtgnjK6eMURAE/tixx2JHqSwPx BYO+G1dNyAcnXsxzAM+irCLXVKYjUS9TdYTQjeZvMJ1FNLbA0KATS35wkT0BlFHjppIvE+kviD0f 7R3sbxTlg8zPyQg7w2CvrxFh1iBOyVlCzv3egy8U5PK18ZwqTlgEfdG8NPKbbuNY/ty5S1hGOCum QlL7ZuQku8LkOutv8JRPz+rpJqeRFCZ9GVWyAiGQzQzo1/3VxQpJdhxGx6jrJKKbAptezduE2rGP JAsbst5aemQhN8sretRtBvOLML6RK1D8txZLzoRYwIfMZ7QwLiSZTpDqi5L1a66rQblG27C2Ib3q 3TclYqAyY2Vhy1Ve/+5dtZb7NQq+kQ6B5h+0xlvCmiBla+qGXL5nKOV7qQWOBpL10drjKIDxxbR5 En/hRZZcRmbJzipN1KRTlHbpcDHEcrAgXFSGKNu0qAmUf6SYRTwr0fXFk0vWFBvG3V1+3QjYhy08 bQwRae1Nk/207+Sl5AYy3L/z9ngxxFhVzt+DlDA5ia+M0xRkSy3/w7DRRwo3AojzVXI4Z510Dpwl J0qwymTOIP0wlPVB7uSdsheBmqyt5XEzymsKAPx0VSxNy+6GeTjjLDfzmJqe02OEqw+GxYzpSeED FjgyomaCq2WZobgUdqPsUqIFswNCIck8rzhSFwRLT5bVaYUa7qasoblRcIbce0kFsS4lONtz9fAr 84zqF3ynPB2jEHx3rHJUZ0BPLt237zU9qthhz5+W6jEEYZrMfhWcXA0Rq6rAslHJE8L4OeYb9vjC D3ib20+h3q+TKfrGgDHdeMKEjnJvPawU+8Ly9mSyT6AdrQYETgZjrUd73697LdvxQv7GXhga6LI6 Vb48yjSG9EnV0E1RIZtazJstl4ePmvC3LttrDo8Uy2OCm8UVzkQu6V9r6/jmEB4d76VJzTTfrzHL ks0UhQeZJA90iVcne7Ctxdt3L4tl9f8TG5AzxH+IQqxHy+Ardfiprf4lPWed6QphulUONVE4KUKk VmHO6lke3gd4Tw9swSRVd67YMdY1HXDnYdGLUmvoapRFyKtuxrfWFJ9/3Ep/1zsvcq8qKeTSKkmu o/NhuAwVPssz/Q/spT2Je2iNDJ3sLfwFb4XO4wDvWyyRD3MFbgeeVpp8PaCeeSTa42+VFn8iTYJk XyxRSss1SJOdb3QtKqyPNlAd3bp6V+YudaSDijqNKkRqXfOFxC3zoyozui2IkbWGDW3eT/P0Y1Hr CWoXmBjR9YSosE/HvZeIjIi4N9XLFkqfifdIkmapLYfSvRF6+2/EoMRcvLoG0J3iK2/ZDutw20gJ q4aP/NXGAKijShWJ8dcLcCbODcfI400w7cjvvGmNl4vveaH6NKqOL0LXgfW/xPONe/sJmMnSSvDL orIJyJoeu0htjAKupKlvnykiXWIS68+FgXv0MXZ0QrAcJaDLrjQZz9a+k0RipWRNDIxAyq0FFQOl Hg1anBZvUhxaqeLcf8HcYcCBHxGltPvrrUKu9fLZTKGTYzeKwrcBC9n1bwZCvVb8Y71J4G5uwRYT M/FFXlizu9legMxZRS80H2NADo3B4RUJ+TttD0umbTpEYzdeo9DKMdhUFtgvENEWFMg19AOBkv8y /SWfX0sp3wBVjpVPQ4IiJ1betE4/w2ueDeIYxjklWnK1hKA6sIkTNuN36WgCoatzlAcm1j8O35IY PnB0gxWXc3gLLtuP8FalFxJ+focYSqiXm7zWaArvbdrX1vYSTqadupx/ITk2kJkljjTHP2Jld2PN v7weO7Nk+oaqW+3/Gt+JCrO6ZYvQtPdaheQYD6FWeKtL4bkTbAicjJP9pcWTY3qEVq3VBmLDMaZA 5tydXngFgRKrTEAvMaIz8WFCExj2wLz0InDl9XHur7NbUDXuU0NIUpkB3vzceSD05LHrCEyJkNgU pTIWIjPozH+MtlbXTJHLNWoUmqYHciqAHefX4QnHXNbv7CkklM/li6LJRab07C6jKIXpfFUYFg5T /o8aZX4jf5+6aD/DZ2F2pXkdJpSes9txGiy9v4ulOrxhY5EoB/ZlN7pMCcOpD7n5gupTDzfRttF2 YD58GsaSgYHlWt0q4lJnMisF2IHdQ7Fet0i1pdnpRBjBgEgiCTwme5RNRwtEWXhpu2JDRKGbFgOt edb0Om6SNjpk0DZeXMSYR6s+OzIr55Xak5kaZcDHJJ05LEDS1lNXdoIrBN6slZzZ/cSWePe7BBIT Vus4/iMJ6Nfw6ULMsZaYQ+yIP12ZeuJ1CmqRnsdtX3dwVOdGVS7otzlYOJU7U0IATmVjfkZTwxMg 2nbOYXTrYCl6aF+PUsDsNOpqR6MyZZE0Xrik+nVt8t+U3Qm4KdKRy/t7iyFuqXbg2uEIeU8XEhdv xsE39lDMZLulJLPRyafkIiKYKvC9bVxkMvU3zGOVUQ5kvtCPYMY8HbpL31nGKgwUbJ+SPIPQ0c2A nr89IpDFbzQO9rWz45mXuWT6i6AvMoeDQIBLe4MRvQS4y+Sl3DsAZ7Of3Ucl/xaIWGcCFw/2oErG EQEqln2uww16qbsCj7oBgLVF24V/dUj6eRj5NIOPP9UTT1BtYXQsb+lD4qjSakWoVseIGcTbBDeN 5GPE9tbbcYT6vYyhbHUM3hRSps+RQlJmZGr3QDhYrn55A+an5KXZypyZNH1+PCfBrFIbQekl6gRA qx2a37k6XQMgTsZc+ORD7dCe+n5OiSDmASMvkYlTgJMnHsZJTEG5w2t8lpH1VRWJ6F+TP+mdtzQo CH7lnknDM11G2f4vbp54aBqEIjzKYRefoImFBW54v/35VCXqtu1o7od0rw+oPOSd7ivt2PH5Nelf V200GZiuDNHml4lfSRPmkCgREEAakRkfH8DdvClQ+4nnMVYOSZxQwvl2++hVqPwcIeO7ZtfnQEOm ZMzBAS7qTGx2Fjtnjvgk9qkO+4scEFVzICeQvrwDJXN16q1B0iBWY2aE3wNADr5yuW0Iqsqtikue fyiKKILtbasJs+8hkpz/ob9b/gjcoNeX6OzORda7mf9L0Oeo6SnR8Kux/0IRf1G3hxtNj6OZdg3o r0D70dWb3kWCTgFQpMaSMFcHKIdMqx3orJG1ii1iIen0d2S3TVtFD8AQtfmPVgEwA/vTt9CdmV9g 6fiemkGO7mlggySWoheWqJ4m5C7senE0kbOhxrMw2n4vPHAHWliHgQFW8T8AylyRuWi5HsyR7ZPr HlMYvg1fBKqAYefnCCiTbnUCD6rnYLpC/HBKob4VzHKHT+p47lordrkbEGcRxGGLosZf4Flq/dFk hjpMzegVxbJ9NMXJRPO8ws9mWYPiR/zwx32UamQQqgrBSu3e6F3mf1M4owx6kXmDoIS0GWVpspuN z1RiQzm23XcDCS06kKYlf0YuijEJLpavmuHB2GhjDMex6WRy4D64vaNg61mtUHLmQ+I+N89ot/BF c9iecZo+kWav7YuzA/FigA+Cv6IIz4SYbnRc9HiUDDYHsxnpyQCJJ/GnNscNETtXCF7KyD6fO/UY eB4jNn6qlXmQJwc//tbmFu19mzP99JEYPKqniT6XSGnG4sP/OlOhRkgHKcWQLUEE37Qb7MYMHfXy fjQ/+ILl3UzNkVHfM17IeuclyMPTmOb8cT/e5qJR01Vs+v4ROg92kjzYiHZps1/oZ80AXalRlTva Re0MihMDo6QNWsNUyxY2l538/ERlgvoDTQzEfHf1/mqe+i/k1gi1xo1V9/+PCyXwpEqCOUbjH67r T9BKETQ9nsgvVi8+K54tcmAtGXh/Tv09HAgZ21bDQcpdBMJ3e0tf0EcvyMEnlJsBBJF1ZA7ns6HZ VmppUrW2PpTqMy4qqmqQ/5K6N+7TR6OpEEm3nXwpDxyrYWTQk2HjTgMAMBF34U8WCpze0OC35rkf jHxINKRyg/U2Rx1gGVI+jycHCeNhjWktFPLfQ09XcgFahJSlg7UDOmlOmgZj2NGeSK4rRHD5Ss7R DlZamtp0zP/Cdgd1IcgDHsFy/uP4swCpwlSstiJ4YB4PT3L69mc30zZiMcEHs2cjin2M9YZM5E3F p3BZh3iS4NBN86NAE1KUGY2Q7nD08DnpjXYHNZBWlIEiwvf8IRbX/fH+3KpI2MMTFfsecLRXMujs WD/Y8kyPI5GpOIHn/7Vz3AOEsYRVkKyuYx8ODfv5brBZTLDyauoHNP4sDJlCQN6rz7Y4qp4lv5pk pMs3ICTvk10BfidmO1jeeS+lEsZBZ0U523TVHkexlUCd7wJim0PAXES8uXacsNfeZNZ6o/gULbdE J41E8z3UlWckIS5aOzRQ1YJQ1wHpCYUSVMFdMJcM9l7BTGCMDvzTugTEu0SKBF9KFa9sVEjcT9k0 SkxajR3cbLDTH/H06+vyg3+gOrmWMQkUPa4AXhnPlfAD2tXSjGPWEXbmZKEiXTdZpaHs++W1O5RC pe6L1LEnWaSSC+33ndtuGL62YmqMrzTvgtDYLEieMx+Fg74Uc2GJ9l3PVhc//Ye11vHY8zlewPia aEGFRnbvAy5/X3Px5+2bTFWIKAh4w4hZj5Q2XSpIJeEzEMvGOLV2MrXv/lMaLTAdNNfC5RZ/ld/f DbBM4J5DQ+alRZEwsD/ZqfrJtD2sN00dBmCXh/WLJiqh6jpzG8yDL+4hWCdizar3SdsmC2LLnJyw CrkoNdCc7kTxEaBsA4MjfRB4jJKOgmQvBhsqQCXU3qllvkIxoZ4TEn75Cz3oJRdEEyjwdaeG86AA GG3Mg1axcGW4ks0QYXMDvcFtoAv1QtK4dBmg9ZYFCyntB/VoPggwJwrg17zfsBrXs+A+CuJgP0TN Rk6k3CE1N8A+uu91mkemLph3hwNj3mpZAmPdLodTjf9jQ8cvxj9jju4t56G4iooUjZntonwbvVKn 5ojxyaPGKsFETlsAaxowH2907MhbOrroMVk98nQ5PQLqZ+dh1+7vXVRfYFJB+GY2j0YmX0ICzz+2 VGQ8CoeLe+EzJ/A9HOY+b1y2YnHoneFyTtsvedd9vo1Sz6zXzd4EYmIHn7isWrYfXXV34Gag+aW2 h3Th3CV11iYBK8zKrhUDT6YKd/CkaVgrZEk4YKOSFvSGu8NmTkABNjxH5hTGgdB6I8mRdhe4diYA 4De86q0OtvMgWOSpCwC5ucFYF/LRx2AKrhHVOurgn79a85p93KXyaSxnOiCPH/wdP/3EB2GVmkrK ndiMGOLdRyJqCtFflQ50Jo8D83StYGduMr4BwZac4dAytw3K0i19VZ9+9YBaGquu3DuY/IcHWgTh hPw1jnO2a9cHDFJTTFCxievekzbuQXEoMClwjuA2+x8LLArfQ8TLDlCynF9XzuZTfbEL2Svhn/Yt lFu732PQ6U86RIHzHR1K+dI6qNMWXx+75aNu85wDq4h0zD9cNwVul5rGOIC4QLQA7f+wK/Gmv6KS 8QIHia7m0R+iKijGnnPxuj6ybDeptT++ru/X793gWiLFWlwfCQtISxkj9OPB0dO6YAdhWOEzbgbt KUp3SqY/44pqcivZSIsBALGN+9dQx9CnaWpE4zwnzD3QJvXkSbgJklPzTL5gZuLdtTY/07A37TcB 4IzhsnkAHh5E+Vo2zjG3+FjCcsw6LIepXL5dovGMzEQJLXxiiWr1P3B2sLe61NFTwU8xnLXh9nrl FPP7AyzVKY68TY5lnzlhgV63Oudcil1JW7jmT0VWqyFKMI/DdLhgzVl42H/kfSvijR37KlJ2/oSp KPmKw7tDwbWZrBKiCijiv3gptXOztaKstQVORZTQCqEpSxKxpijZQBp3bXjmNw+XUSsevD6iAlIg vT5VvukHL3k3eRltmEqWUw37Jpo0H0r1MVq1BUTfZLyRXPPZvs9owag2uHLHfwPVxwaL5S8nsbUk 8Z6pXV53YZkL1sFuRod/8wqkQ7qeofx+ZfVocMBpmBMJv7KfMd7PjZ3K6JzjhuTkRykH8Q4r9VkG 4dAQFw6xaPB3RhhtkgCxp3je3Ey5sBaBTsV88EV8/KBeQfcZVsFiNd7rRPrw9ceZvmmYLPzH7aKq M1ZPDriepfzNMEfXN+lz2ozcnTLj+TtiutQq/+HerCEcPmJsJa+eGkdi5yKhAt3eZIOEjyWdkZIR J5H+IUNeoRVFioB2KRNDODVMrYyoBZHfFUzjynsUTvA7HvNkr7/km1UO8pEt9OjVpIgLHpN44anc CGBcGtz4dT0CqM84ZtZfTNOSaKv8LRAf7dbBFh2b9uFhbht5EJmt4DSLSUKM6g9fKvJkm6QgFsLv urWaTy4R6Y85JLC+dpEovHk2woTTZUS4hayIJLcK6+3RTGFWgDqCTj+rMarUODhmjv/NUrnC1sce Hf/WjmNddS0taUQhKfR/rD600WUDBBCKET3cCqNe9UX/0qvj48p3w8NOURJGcQEW7oQI6S7FRXhf vQhOQpOsx09R14DDXgPiuM7e2li0s9iLlyovW9WLohdrRvS3XQ1RVb/N1RhSVcyCjJMmn64FM7+M dj8og9RwI5Xo4KRCOJM4Ybszci/+EhNz8uGjCQlPGoqQnDHjGVksKD8yRJBy1yqmJMX4DwPHVmBs A9+yyOsFp2MX4Wp2aCJSgxAaMrUtBdDpqne2egTD9CDjDcwpQ3hEojr7zWZduUlhH3YznqNZi49n oGeuxv1GuGF1GN9ikrcV9+ZKClcDQCk9tGjhbDOqMpd+0G8+lP2+wEF56rxZducjQysLurntwiq2 7X+qG1+n5ZKOpLsQeluTBVzhEvsVGlapsuxNgObfObhpYM0XN9DqmzW6wMy0wJoNAKlgdFeKxhqo +0SEKjAaxOGocLNR4b9vFHhwnpDsdUN1t/jIwi211DZc6QLlgbsNpSiHKlMSUEpAfzRrl6EZN3zI ylJTZjmDXkwdO9f8eIxqzKWfau2p/f/JqW9FuoXmpBK9PS7D64xgI6/1+zVBbUARZr/csy+uMwBs EogmNfotFz/hvgfudSDUlp7IPc3gpYcN97dnrWSyMW1tmUBuM7DOVJmOae5R/sVXqtjZBZr/Xigc Y5wP/7oRCA38Yi+pfTCjd3iOiVOGMMpR1Y4Dt3DCqZh6hjBN0xIgMk+szZ72GSGdSGuEx9rm8Y0+ DH6dLcJknAXWwgMOZmSAxyXFkTHWH0wARyoqYbgJCNIMBqOSJy9WW1PSNUJAE58Lfry2HuvnMJUk 3Vv0MR7arb9s+mr1wvs//foeW/IPfQV9aEOAVdcQJVk+qUM+P75aq35CRVQ81XKL/9P3PbBCOCX1 rfaX3Qpl3bQJ6lxIkhNfT2lGBt1raeejJULEIJFFEyoXRMrEboaVgTVxcw3EyW1NT0sLXoShvKCF pYMWv14390D63vHkcsIX5F3lGEst8H7N+Nud7CdOhCrCjie0kCrT0kJgw/IRZIu8/PRNfMc3rvJT 48Z9nLf12C6JyWf6+GtmfsbDdHWRC+IiWzG+lvINA/aJDg5QuYSTX70dANQaZAAixpbp2vGJHFzD ogPjCqMZ3k8iALzPcymm11b/jhH3OGEMN/fVHxx4HfXJRfq0AEOBlxzGyhA75Vyd+gGBik29qItT N1wYFBigk/FNGB5pzKgDXx1eNt+Q4gp7SoOQPtyXPbZBauUmYwG8sumW2xtSV7mNegLWpKJ6kNmH n5NgH1LTnnuFJgsumJP7CJobagHzyhdrvQVSKHZvE00/53gBhkKbme/8TWuF3cOTRj/bfwZmycm2 zWYNKcns/7zRNDvxK8OEFvCK73lZ/CDAEo3ErECnY5jXpqdSIDyneBvErQCZLQvC2bQGhPgdBas5 FjXC4jyMudRInIg0QmUlLo22xt7w0X+Y7QtfSIce/bD9zYwSIArU8G9easrEfdAWPdh2IrVPtHfo dIGLqHC7Z+MUyapnqu3M3d7ltKDQfBVqW+P+cKT3utjxYzZyfMjgMz3GWMvu5uXeGzwl0hKwuAqD Dt+8uWLFINb6cEsOr0+WA2HAOWIIOuJCFeoiyPzFhR2tpfOSC3iwzG0tgXQYD8w01VucAd6p2fJ5 WAW95LKY22xp23oJXhNLZSdeo/APWw41AJcn0UNmFewza/y3Hn1AhA5EYq8Yci7w6L2TrspeBNdC szJw4eFQzCHyNayZyzgbzzq0Atx4qQaDWK1k9LLKuP6NVX0VjDOGBibKekn5suvJX3zNOCdfK2EN e6jBaV6t2SnKQBg8YDPvUh2OF/ojTz9tREbRaH5hpwpWLu7++XAayQVBo3v2NpASZaoKpARgRsLh HHAwkPvSWo+xushxx2HPHsHxlFmHf72Bw5W5776TuWD7AHzv03edXyHFPClx9PNPriRTzRFCYW2H ASvSjOKEDrCk33ilntM9fSWoWa3jqXuY5cDNyn6L30YDce5t+MhaH5tIrFrwm6GZ0FgSlUsTzOLg 3RruOTwSS2Oa0LC8giKDjWD3wmZ2/hexCXNnmzPi+OUcHHl0rj2CSKEkOXtX6yUSlOtA/0Z1OQn3 qO9DVm9SRXZQstJt8wk6I2fdxDDlc0/DhA5yqT3XCLoXgnJFA/NWM7AEGxrfsFTIcvULiiJnOa3W 14qsW/rguCbOxQVGDnsMLOiZKOIo66R4pDltDoXfO64k4zJSWioaUrg30VY/vApzruOsw5ZIWPvL cxWK8PPpbQfmYupW+i1vSO8HEMuP1AgV7M4lh9T47WF0JVtLtruRqK4tebyr4aUULCNX75UQRepp rmEgMATHl2MBOFg5mx1RlTLTFIJvYG6qTw87VID/sAy1fcER/mO2NnPbOtRdfPgigPvJDTul8C+Y GOjIhZ6pCPxdMzqRTPvuWIbos9+l7N3TpwgN/FPkZQd95go1ORF+jifjcP5UPBCFKmu65/mLBkyy td9KdqcK3k5mSg4ghb7X6VawYfPiI6F9ceEctLWf5dU1atNuXFkbG8VN1rrV82vahRSZF5W8JXA7 9dadazHU33Y55ZIfi/djC/q2vGEFhL9dy46gKPF2LKyNCIGRAtdXSR8+5IVo9xCWZI03g7MxQ/p5 6oup1oeo0Jk0uR1D0lX60lWocR1xZpUJndJ2Nh8L3TLePVnLzd/gDBTmK9o0HPw2Yo/Ali+9qDwA kYoXyK4wUHQixA62c5rc+R3fuUEcqsQXHVvlPK+UusvZi3pwkF8ozUrDpFI6Fy2WkpirsGFBUXwJ UlMtJD1K3M8J6t1HxkD/dPPPBXbPOmGBl9sVvrXGeqeO3sFA/A0egqW7jexgafsVrlLoNrpxWDWb 5ThpnCD90nK6GwhSKSkBZXTkG431rZT3Ufg9HepsqK8hUfhOhgXgJRhUsClRQgZO6v5jeLmuHbrm nnUn8dXxSl3h0q7UuHRma/VvpJQQDmGHQiUIM2eIOaN7cTmBQfY0OcQtL/l4VAvkAX3XuhweUZCl gU0tQDZV5H1RkcBVZoAmxHKk2tnbBJNogTdDBvDaniMUYe2YK5aWqSi06tWJmLFlSe78mnDnDnIA KL8OO7MXjBEY1y47vE/yRvCcbMH92JBaYz7gG4QQD3r8GkMjJvan9wqeJc3SzGhZSanGDOXb3vQg juvdf9bM8xydA9GLI4KToZqXvBQPYPQKjK1FyH5kwes0fLPqFZiVej1v3n9Fly4s3qZB/+5HQVLs 36L8sMnE358PGjhzQ4NA8CqCKRYcUb8RMUe8KQK1XEQbr6EaOEavxD5Enl8pnAyCjWFaPye3DA0W YiwXJuVIQQGwK6edeQGlfeDG6x3QzuHG+HVvVNAFY2EsCX1UGgXPhxP3wGlardUc9f4JYXEEH3ui Nf61dnBco6dd+DOEB3NYsxzG9p2jIFfJ466Y32rfNhunF5dTw6J9DzKhMNLbuZXA1hMcGtDg0Ofx azuz9iyj7XU0tK1+v6o5Z3s17MYJ/u2HA6yiWrbYz4dLM/Zih9abrd6bly+0hPs8+Il8x81EFfn2 cFETgobdMg0gGP2r6zb54WRfIAFsrIVhmBekKntIZN+yM+udLFdReKbr4X5wY4j8SD2iz5aZ7Mvf Y6P/aTLJyBQ6w4WkyjaQWbjGY8+/T4RXaCBzGhI8fRP9r2WfhfSb+jekd3ni/pMMuyAkXwVt3RJJ H8YkwVQiO8aMyERfShgNDEimbtUhLKcJ+tVOeWC8aqSUI1DOxEKT7q7TYXhcY9cqILOvPjeSkfUI vrUuQOX361fRrx7zluREGmuRjRohBGKsXPdPy5BSdF8jHYl1ZmkwzR0jtXqTKL54bEU3QKoJAlBT gcaal+EXDb/ABThQ9ZjGarl1Uc3+9nIWJYr+oeyLh9Din7eoZ+vUxVy5fH0NWwbptI0tbmFlFo11 pdDpy41RHQjm3V5b5GLDdcPfXraxC7O0F0BvQVk/7OzaggDEaCYJKouwxmcFED8vWVbUfo2gQZ6/ Yr52+WZxODbZnG0Y05cPNjPGmjc50MIZtGFyGQFB5LD5SIKcTzHpqahTfTl88OFw2AV6DLV8mLEz mCoE3bCuGmsMVGpYmKkYQoDj+uHrVKYhY3gvlKYBkqXByNYJiz1z1XhUPyBlQB45sVVIuQHxyoFF MY0D8OWByGKYAOWCRXLzyqFRYSy0ALKvSaSBgCI449eWz0blYZJJwyV2g7A1REwIKCGHBmqhQTDy PVN7uVAYZ37K4roi1rtKx5fjpFmnf98Q2wPdHIYdvmKt5gJAYyzDDadhgA1HJtsMksHTsUEmmVs/ 0K1slgiNlEK5aecQgdMb6ekgkuU6Th04XnddUu6jZ0NMQMWpGA1BVwJA0CxKnaIrPAHD2OPdgY5/ WRI7b35Fq2nUn252nxyhiSdd3ZsYn8pjpCY8AagrowclhK3XK7L0O3AnkXKPbHGUAlemEBwU6jii Uv30nnAEvkN5BENA3A9JdaulLFGX4N+59K6eaWzWZa7NuvIkFWGyxY0mKkcaeEzy5AG/esKiaWNC ecDev7nQxqk/nAAeXHiPylraEIwWxAzG7TZ8WCSeizJVHp5sj+lh1SoDKyocVvq1JdJVXIj4qLSb G+xP0igP9MT3G7sQlkC3OcwSt8XIR5dFW108vfUHpGg/NWIFOA69G0zlf0JVznxc4Y6wvHPVnfmI yRXZrME932IOudWnRW5GEzSGwugPuCxQYREtd3qzqcoMjYvCsE0xHRkVyGOhP0zqdqszAhTn6FwN x1QqoQyGYPiRX7hOWmTg6pdFpZzhe7y0CgwlyefqPczo8DL8gnkyls29hN1Hl7GFDv/PIhAQDh45 3oniyM6HW5Dj1CvAHoosQ6itYXLaJK9sfhLsbTJ0DfdUD9gq2+fSNButlyTr2InkhxnhDcrbgWtq 1iRkHU5PQQ0C1OqGcXKLm3PUIQK4M/o3XS12xjG/AXFQgmIMU/1EbHH+rRZ3yRGsYT+u6DDcEyYn ZxTdwPuq53B/c96K2NsVTTrqjNAedHr5VDhC/R9OzE6TiCPveh+2z4bpnXH5q0k77yReFVTarvJY +lgug0KPy0nelo8MpS6kxsiudiFbY99Ytn9eDlgT9w0dHwt1pqZyRfM+Sh8mG/Azd7iVBi/slBTA PZubgvjGKB5U5J+qPGR5/MirWBTMN8KEaP+Ow3vETJS/ctBHWhhzEV3FfT/nSzZH5dCDw5D0tadt VJ0sam9s/UV3pVcSoBvcxUnyF4rLxC+AToWYnWjaxGczXVr192TBjI16XyZGKHpimd15MTiRzgIu O7qO6RyYljcEvyo3lgwgOLdQ+2S458fccaNJfxdW4Em7WlC+7PDr/jdzAhKb8w5svW4kkI3b+MH1 ZNv/x0t9CU1+hMFlPocSMt0dFxduIHVlem21zopfMgYP8ZpDbMg7xh5BmHvUEkZaCusHu/lTf2Oy Bbb2MtYOTka35JsT9KG20l7QBsG5T4j0MhsdJKyozys0WnTgRmdu+b5pj4gv0zMkaaf2kObmlfZR x1P3aBCmMzBFlktQxZJNwOd+rvwZC+8syipNfrOr2DH14fqHLV2kGKW+Og892INWgKfm780LLQOx KmDZj3fYTWt9tHMRK401BhA2YFnP0+r9BVfrCJccijlclkvE2flp2rSsqe8ZfpNioG9LPeWRCpGY jI6W9yzwlN1nGaB8hAo4oTRPc5ke9MS2OAGxJ87dJ1ZGVUQXT4jAVHrBPZts0xofNJKB1nQ6IUZ2 Dg8O3cPY9iuptG1bfaKsiY0IZQdFkgAp/opnt1tqIVgITPzCZJ5AsdbsDUhJnc5w/13QPX+u6SI5 +cJ4eakBj9/+lW7Xm8/CvxqTqyx5TNZvdC5kgWh9is9WMrKwSwF5yA30FKnFJDNxDKRhVDunC6L8 q6M/vJEEb/5HFZa5jm/e5jBtMpgZG7n2jPyPyvx9G6qp+k55F0kXNL1l367hyrhokpBFaR2O/glL POWMNJemKHL+/H3w3oU58pR2exvz2GexZt75Bk/xBI7Z9lZEygew2KO2xUuh6W+vrg5zzLhZnNiz 2rkgUp5DuyCREuu8mZt07mN63i9V2BZacVcYbAcY1TNrV2ACiOREBDANZ+qp/1f/0tTh9oh1McRq 2d9lIChAQmFWbM8T5wuwelXcm3Rxgp4+NkDwySNIR0rn5nUq5mwO79atx1iZO8kwEKAWOVhB75qL Z+K2phRCZapqKXhgNsNWMpW45HPbIJLpmOdV5LEymv+R0ZfCMACUerKd35U+Ue1tVtK8KAGczbWv UGG+92TFFLmmOBpFnxZH0NgFPIzOKQ4WsiKwlTFQ6t2H5g/FoF75hqJEexRtJTZdyp95iWNdV71K P/ktZX02a/ld9HZ+bj2aR+YFnVoJtS+POcTDdie53bwAj/fi8GBZwI5PCv7AfQXel8g7WHVFehBc zfFhRW88N653PaPboYkWV4o2fqzkygwyquOWTuFcoHllvJkPcakpCubXTjZ3nJ8k9cNQlB1c5gPZ 4YgEckNyk6mcPiG+pdASIwtdVAbxLWn7ny6tlxau82ZNgykFScW1JNTRxFM9m+xBZyFKQXLMXnvK 6ZPKhhjYaBbbLWrzzzJHQ5/J6/y25y43D7BDCQq2kiSXXHJSQDA0TEr2RC/eRjhPH4U80iQPbxtB e/cZf41ztepAndgKmUkknB5OIp2SFf0K2+lUyOyrJ552Zq1mrfxhLuBGxFzSih9L8AL4hI44mBx3 Nu5x/zD0DcIpIYxzYsd02M6vMU6S5TJ5cHq8+pMzuB9iKSmzmHparvSOzSPEhvK5/OTASbCazoB1 ZNaW9u70Ebj361k+CnjfFGRMHJx6hW65Ex/96d9WCWocBkCATMCmj5vT0ghV1D2LvQvt5xql8jyE cNeOLVcKrMuFPs0FjViBTswc2QsY/rBIZhsc8CDmSCWDFCF3WskDa6m7AzqvnnDPF+XYx6Y5XD4Y VOPobE1H7kHxfo8+Gh51sgJw1SQ/HMDgfvmCmhZOFRB1f7h8Yidkj50Yv0memTDDnbY6MC05AlLW qZIrhdOUvDZZXSKeuIi/NQ1auw+0JpxfMRrvNcYOZUugrcLF80L1IClxITubQLpTG6r1WJGVFvo2 h90REZ67WcXuzEyy5xiBTNKKdTZQextGVknNLyHrrUoDEBUqeqUKADgpyV0wevethEfPdIs0CRbn QWf1kvSqn4G1esJLxUf/7g+Pxn8LYNDb8iHmJNRjnbjEbWLW4sU8l+NDhymSmFRx2SPPSIxzBHEe QPIqL/6ZtAYPBNuncv25c5bsZl7VLWuLAnt7UIlX2GYjuO36HOiVSCye1sQ38/T2msxv5ie6vrnE 0LIhc5DhgSPSxvWWFHMydGWMeRk0lMsPI2XkLwVkPMM7wCfWI+DK4fpnKvilYh6OoyrKJ6ia9MdJ 4AbouNkdzQ7VzMqarX9OLIhghWYYk3X2kMYNtRjlZRFgpEa8ZSBgC/QBE5hHBhWyHN6JXfxvNMhw VH9xV3RITh1Q3DLTs0NYTdvp2BI3NOGanYOVL3AH78CpCFDBEqUWWcQHURVbVd9GKYGPCgQnjEiT BQPb2XGALd1bBnQJ3r4F14DF3rWbdWc86Auc+cxCkaqB9QJWCa9RAjQdSLHwMlXhNyCMqhs4za9M U4IgZH01p48LWcqDcwR31lktksggzsqo9XVboPXmmbqVytTmum+J3RSD2z8dMs8r55P2Yx6NrlTE BpbtGwaAxmGWNdb4s1YfllWyC2O8Tbbgtq2QVtERcFWoPJ++jv21wr8iu+m5REEP+62JtUUadldK G1cRYEWxWuVPp29w73pxMKTLo0A3t/bng49qqE0zcttX8klMhEyiSX3S+6tf36FR2zkrZlkCOY7l NaHFlwDsMq+q1p17K3WaX1DIqBKAlUe89ogxnX73W4V7Jr0VHzGDdFVffzl0m+4ia6ayNIiwn+9q c3yrsnd4WRjQsBTgQ4SIwQkXxau9aqB4Y80e6EP0y3QIy+gqM2Zx+rXBSb/VfbEAMRkfzJXU8cK/ XpdjgwnSC96h0lzD7pdtTaa7pYxHJrv0E06quMZhZFqLCG7SBOFuxPjd9t9hYoYu/qI4JhquuG4A vlVuSECxfSF0U9rJ+/eJNcDfXyOFbjsl+vAW1bIa1wI1lx3053Ti51GRFf95iUNn9PLHGNdxilWO RCoJgYPJS0VRq7967l/2gN2kR6e3U6ZnRLwbS5LdCJE6V8OalWDrADDBgpAvXSg3dyIhQA68aHK1 Op6hPWN5NDTOQQVxISEx8z5IzvmRMzuJWo0PZU6BpBJ+K39FQhDQJjBkrXAi+o0+E5tQMAunWFCA gsBi4lkS7n8OpXgaGwZ/Mosgkndq9Gpd0AkX0Jktu4wbEkja9XxquyPWvXa1uPyC2AxEOjqOkc0W Iu9XjYU6pj4Lj0JmkcXWQtNbNnarqfTrU2n3jV7RYR9tsvUwttDI09KOh+P3zYUbL0hd8Wb4QcEg IynO/jqRnsUIBSHX2fwIrBhgykFmM+ZCGRXaECRG8KhVvzGogzNmDQJsdX6/5KmkQ3UytVGgc6cC PKFfSCQ2po9HgDyAxDwvNsqZSxUrtBun9nReDyu/6K32iONg2AGW//hBFgNP7tIuEFgmzpFsU73h E1j96uKvI/QQyg/UAsvdGPR8naVdojQrtwil6g6ujLsvXQnovCgWuum0uMwX3JX88XF53H9G0EUm LfrWv0ETIdx2WyIFj3Wza5TsANHm0QYPf63z0Eh+qrYz3it/zg3e3nb7/V6A4H+enOW+w7bh3nZe 5kKUcn66cK997FmGCRZxy+9OOrn54BNeg8kABdcuS68gasYi+7RFOhAZsiC8bdzQrwRS7Mdbie6k Yq6bkZaI8yVVqby+EsNv/IMZhCREnM0YPLi3F3beGizg+2LHtw56d9C71RrTT3BhBVTvIftWto+h hTJz5jtJp0Ps3xibiDPYOBaWcg9/BSAjRFlMdztaZYcQzoVIAPdbnB/TagHUQTJh0O277HTN4wnk HljowITHoyQFme4vAEsRNMtG0UxDD/jmYciWsvqmLZwArNlutPLd5M2cp0/36QAQE7I+BZ+7bEOl dmbhKqYBRmU6SRt6NHaw8js2QwdW8ThbA0qt5XLw+2QJqEb6ME8OBqzucPvzQKleO2fE1D+jvoRY P2R0y406KJO7laVsBR1UBjKmZgO4CCQED8BKcBr/T6mwk2IoWySdTn2wK3E62kZpuJ33GTR7jw3L px3RdeEDRDw35HdVgAx/UCmnAfpEwh0EDCfRKOIGnL0L2w06wQU77dBOoFeV0jO4lqT3v1MkvRnu JqcgvU53iOtMJ/vOKyB9/Is33VxN3468frN0JizfaLB6gJ9l179gMQMHcMVmWznUtxhvQZPklfxp qnm/qcgB5cBRq/rG9ORV537G6maEC7O5rXpq2+x9JVQv8wHEF3JEQ6GKdL4LmMjo/75V0EwMFmi4 CK2+hEIWdUpC21BfdvjyDgZfdizWrNH02B+0vE9M9smdm5dCG98ybQET8FTK1Lo76gR1qfGS0wAp fVMMmWt0VND9ZMzrwVRljxqpYAKlXAQfY0R/xA6tCxiV6t1LQnUGLyFwGBTHG86e4p9tEOUQ1281 l5fgALlv5r7ao8Nkg9fhwGWkZBPmY1zIlqaiZokkWTstIeXi93XxTxvs8ARekb2VzGlM+pCELWTE uDzjT3+C1kNJha9SWZDhVjNrLWaxX6esR+AgMT+oPdqsyjg0tG8C9JP7bjXqMIZbh96i56dnLA6E VCUAcZoMQ5RRMq2+SLN4VDd/G9kV2zvcC+FiT7sdcRzpPmaPCtVDb5krS6H5L1tdXuuDz0hiQJjO J28KWXh1m1cyzoedSvjZjs9JFGc6JIeGVXECOaFLddmfHk1p3cpam48i7b8M6e96qXS+8BLENXfm /qOg7d+JJsXLCQ8Af1ZXpcmz263pVdN0UqF4REEZVeBGLe4rkN9WPuNedO364kMpv9KiwBke1X6v 659Xy6u7EDnARQ600/ItP7zGi+EhlUa7wizxtn3wYdnN2NK15jKZQffORYo3v7GqcNHnwd/Jqr2o LWo3kmwytUwBPbomnlDf/swAVOaHP0769LTsR+HzRkUnMsxYbQZLXs3FSpJRIHDI4RrAwSWQArbY JSx0Oc7U6oOKHw5x0BcK9lK79UUrdzpW5lKEQNbCGwywsJc05JFI6Db22zx3BWr01wXvU9rCSkvM VS5bd1mMTqyQMmOLkfZv+zZAjmGDFIiO2zLqYSxWxKcLYWaXgHgdEko/ujyGwDwo5HTTbq3nNheY FnaYH95s05z/7lEtJg5BQwGqBMc3znw9EWtT8EsTKvh29EQJJ4+MWDeFHkP7lCsC2r9Gw0kvk8yY jucoagwHK4cZZui9vTZDPcO4ZzPL2jaxvYrydDmmK8s8v8HP958/bjuUfiii5QEWToWEYjt/KXvg w2mLQhk4LaDojLuEqeuQvugm7DtorHsNwFNE4wMeZ5HTsxR8Wcl1fbz2Nt+O4o0XmrTwQZlhmBrP S+2NidfLqCx3PccBtE7CgFtAlftB95L/meDShXKAQYPbltZPev71nI5USeT9OE7Ml5jP1s2VispT gUwQ0m6NRcG9xo2fcp5r7Mn+YfrH9Hnq/wIdilfaJTICUfIl6h1x5MmNKuF1Y9gm1ArYlx+Zw68Y vbQ2dhCcPvCAIJobN2aDNVMXBUy3Fe0BQSznCysthvYin+YU6LNIFYZeXXYy9L3Qj71o1LzdlHik lRRU9LT0qsHp2Ftclf8db80Wks/je105O2/uRjVGR0oz+qkg6bJJqKoX8cBaqV/Z1GZ/UExZnYhP 0vVt52BAa+1np/WdIc/oYhukoxy/i0F4G2u2ro1QiRnLjrcE7RVMWkJurK3MjZnwcQjqJHpkZnQT cwUEgRSjLZPQ9EKYkA/5seM6m2lwYW94H71PH9DMDrdAnCvuZ4CnTeS8QHfYWfQcouscNm3wtJNe 79C8xKahRP5lXQnN/i5teikNz3Xjki9skCpxe/T2FLSqsgxDNImzXaLOIZ7YbydezeJkeketpmcS 1jRwOyjSacjdp2JlgvNicvl8US1erJWS/+0veYG6PDOvRmSF8nRKqRNlkrnyI3JD2/GmewbzV4v4 t0HKIdk1VOGvWBjdxXzbt396vnE75gKDwQpd8nnt/YmeT+KCANpXDyvun4nU2LwMe0X0przTBM3I v9J1VlZZVNmD3wm1RS4kj/+T9gMGMQuQVnr8T+fhuvx6T0FKayCsIfZlKIAtBh1hTJJUCsM9N8yg sdJKtYC2ZangqSUdy+D/D8D5yEvJ/kjVcIxw1gxABYzDpBw9Pn7Xfvva67NyefE1urHm8++QoEC9 OuJ98lzacv6pUg5ESbQ0n8HVZ+9zyVwc8IDnicW7CH4XUMvoqOAr8OXkZdZftJm6n81BmarnnnNM d1LkOcRwytPMw4QxhBMPBoKWZr3PMN8QOl6hpTGkfYM8HCX1qONbWIJZQ44/5AshnrzH5q/1TXAX 6AjJQa5Z3BeMG5BqzSjCLZM3d4hO+wxVXFLbwE6ZfNqtYmEhWiyveF7aSdQURRgkfJsJhvK2xiiN VLoEWrW8S15gMmf7yXfi1LNwMe7Yn5nbQGhC5ov8yxdIJdln8PF5yXeeRm8i3xvVYJWbgPThkv7q WKQ7gBRKOws8LoKXQh02d4+wG+0JkOOaeXZooTgvbbmHUgvZZWM+jF7YDLCTHXqNyRp+dMG8/bmz wjArAeBBiFQDYnyZ4d6kPfunJO1KnJYllG1JxVhs0zvpmQVD4Fh5JUHuyRsbV6/ZHLARhlYYk2zB z1aW9XhZA3mww83z9NfnHJ9TPlC7l/GfPvtdWOjp2FKViu51FXhcM8EPKiHlMvGOB3zK5NJvY7cz n59fG9jbTB23NoN8dbaOOauvviRdZhGUifoyByPz3yrYqSbpqOs2PLSOLdKh8UcrbHuFoaeWQPX0 yXMltuUpb/YiEeaYdKLe6amr1+dzYOMFAObbnXsQSjwQme1c6XD3JsUTmPfpVnqCzmFPchxtuS8F aB6Eom9MI1MNzOQGbaW36vNyXXKnU05wCKM3L/Maet+SOJuS856qxCqh5uzbf9yo+iUpnCOfxbvr FgoI3tUiOcHuSeN4qnBqZyAFkuw6urRvhAq+ZZsTLstTaDl7txw1x/jCOuU0zOZEZbE1x9fHve+5 eG+q5UO7oHUoKAfHOYAiD+9JgTSxGoc5ITAqexe5Yf84Ba1IePYunbkUWc7rg80wdhSYLKfA2mMi kYoeUcENgXC8dgiKNTPgrdOd8cWVNGPv3DIXTeK39lTWCUSaQBJg9YfQMHvK5Lrj+8dU7ATMhoIE hnlLyUVJWG9fJ/bHvE95QgmmDPJ64k44UnnzIsNcu4U4iAdEq3Q4aoXKYDNdF4wA2EfOO0JhdYlm wWRg0842Cqqup3xOKb4gQUcxOou1cD1gSOHg9k6awoVLGEjuFuSyhh8dT88+0bzdWzY4bPdACdzm jfP7lhU3M2AhVX+4oa8etmNPLU3GhvRscdnyOORH8UURdJ/d7bzLPfxNs8dY87yB5Lm1+InFO/eD cZVtpT/BB9U7+7VqyUQHaZ2G1i9TKREjrdywJVXUj2Z29U/0FdAz5bxg2Gw7vz9LOIoi76YUIO2F JnKuqalKNIbWeqwMFgTGN6XSj1rgW/Png72HgPLIuFPTEQYjr6ZXcra06WIBBN7Wm9IkL5C3LsgJ rxHqds9R80qht7sahxwmdgvXO2Y+nqMDsM/5n91Ss8Aa2Bat/WwX8PjoBtO6wJNluLwjU+zPWjUj 4wOKacyW8Hm/CqhUILlrH1eRSFMKD1rr2Cu54OkhPva2LSC4i/v8xjFHJ/+iM64nlknNpQ/KJlzj erT8eLjoZRNk/sRRdE6eo8U9PxweROA4vrian6q5LXK0AShsjlgPg1g8sAd2t7+7jJmuviksJ775 icvgB9j9v2YT4IkX2wpIfp27UJL0bkG7PQeoDwrU8wPYFJoMXB1Kk5Mm4SmQGOHwFCSYcCuJyTwY pF9rHQHzaMSb3SijM90YK5n629V9KM2JBEMvwQjvgX2khwZ6pib5xJM4QJkfDSqFG6Q9Wj0WdPs3 4DZqfsWH9ibiwyGvIXD+ODLQ6U5zV8GWP+WyDfwYItxu6/Biwco67nEQj0ay3CklbyzhzuECz2pa Umz2ZEbhtKpiVEsjAjK1njPXjwC8gYhmaXuHTZCDKPnJSy0HJhQVaxqUKqniDMTxssLwl39s2AzQ V3oiQMolR7XrXkL5bcKHTEZmj4Vb2a9p6wNryGNJWB32vJh52inlixkHdYrZklrzJWJdt+O4gaLb HpCgUA4I9dpnJrrRMa7h26VsSmQe1A+BpSI7YyW5tCtgwCAT4p9aJ7Itj/8o+1kWFatugGTAASSw xymyEVBxBp/GmiqaaZ9w1CINnsohvFfOzzTwJXdYhvs/y5/FUMMTmmWiBEP+ZLVTxV+KZ20xQkaM nnMn0WMB8KfhiIZNt/8JsR/dz6yQV+M7VZluhCp/ojWpeoe0egWC1o4M7yhHG67nNges8KO0PpO/ hZJi3nbIl6rRsKNs+LLtl0+CRy+4o7aGIki03oP8OQAlGz6bq4wJuW4gnY5ccvMVx7CVOzQCb9tg GsvNCmrOaeDUA8MEHnpdCzncZA5eco1m2VvoYkkJj9BZXrVoqeWV5Wa+3TrJtNilkgrE0CT6b33t erG/+hjB3M82Jpb21QwbL77F+8F7bxzlTeVZbPrCHIskJhbclz8LsYvCIo1A1tRCRoGbs/4cl/GJ EllCEc5TDh6mpqfkX5Hd6tH6mbJDm0SJzpOCigk9z+Uv6ThFKpECAyCgmJONNnFi0G6VxYdrWnIC b8uA8QakC4dMcrT/2oRXLfSEpa4MdUw2VcYYItGl1agoDR/2NwMAIWHnDscNB4+3hoJXpHrUEidG xBr34uXBUp4aQInVeBT8jFYzw9G6zvlxPvxUzjhPqlL1YCMRiBJ/ntw0selS/dRWYF75WbdIa1VE HYYCKztGgUvW6PUWiL9JGopF1llQu2OjsuH3QuH3FwDdP1IfkO+zHdsAWdntVQqbLVEM5D50bxyp Ns2+WnDwP8WSAOOZsWHEF5AjMPSrFYZdjPYbL958hlgduHOgsdcYgD3PA55/Vu5FWVzDIYc4fgho fbVzRXaKS/eSr1DRQENwG4FYXOidd4vrpX1gmxX1aRN2MEOS//RSqX8V40LvLm/6QZhZkz73fCOM SJzMUegen77rKr3AruT3/uF+v2faqQhX6nReRFe0aDVNgMjhxaBS2m6c8Xc4tuCctOcTc90XWm0X VJnAMCvdEUO2IDWPIR/GgMwlpEt5rANJoli2qrjwe1xJ5qn/sSvZtOvMVZxPbEsTf9L2rSb/np0x l2jwO+o8svFTmdMxR6bVGhYTXv1x8D0bLINw7lDGm9TKKkIfzqJTsy5NPHwh45+XwWerJXtA8mi7 RLN98orS36LH42ArVPEpxc6XcdGeJg4B27Efi/3MxZPiOu66socPMCO5RjZrE9F6UI5Ry0ipu8+l LXEK2Xdj6uDK5/I9x6OBgAf3nO2EjOcOSmDbhJ+w4MTnmEB49DxZsK4h/Z53QQ70NPk7R9QhzNnl mb7ZvtcNAeqv0bQz7jYo2nw0VRrKwdnx8hGtC+qIkxjD0igBXBAIVpkNAX3vjdBllyVHS93b65nR 4ZVUgpSuz5m+el2Kp9BPjRGi/eT48anWNO8IKmMSvBLdjRJAe3I3eRaJyhJi2gCNnDDs953WWMHq 3MtrCQNPfLE0NFHCdLPdyk/fE8uWdXloj5znUviv9sv5j2b+XTBqYPp5o+rKFnCOSx31c9QqTRSN nz37K+eIYPhJpqtR9QuO4u7CplEq1JPNh0WokTq2LCBUs9TMW2FARt0tPzQxY89IyG3FCVM92++j fZIYkpeX4A+z8Wkem3Gy8bNC+ABSfEc1C/0pytyIbvilFP4thcIixuiXIl0j+bcciv/mW5uayUZE qY0BPvoi8B4qTEYBgwfezdpOqlJ4M1boLay6lvx33xE9gkKPMIlHHxNBE0N7JJ6ULR/st/ivEHmM FMJThzCPPIeQMMo1jqEjKX9C5INkZu96GO7dVKyWpUm32dRpNu1mJd7p5AeEIM5k9qsNkbGHRnn3 ydUidzBjU7GpUamcZ3aMWBNry7xYdKiYgEG7n84PI0XYSGAFWwgMO9uDItX2NAJ+wtw6Rtnwy4q5 jKgFlVL5k9QgCYij9XVrHgxEapHYfuETutwlTSElas4ILQoFXsk7qMjAj07Qjs5mWOmTmevX2wG6 9qpb5jr5sHxp85BJ/XZnM13rFYvb6DS0Fx79EXKd/vXkPwgrmT0t8XW0HjrZsmM5UBwN0csrGEDV fqWVowReFqXTzAAa391toUg2yKaF0bVbdVAgrDs6YKEHLir17ZGr1uEdmsyBSqLpIWAqhDlgjl2x p/5XWlF5Hk0XJRY+uwM6rCt1YVQKnh0iQ22YyyXJ4jAx2sGAlB65TRM4sn63xtunN6jvhbPJYyvl hLnCoWazVaFzOWmA3k8HXy1uK5ypWytne2fwux0PMX8DIsqyCidkL8xbV/4e09P8+RY/yqYXGlCE He66DwO4ssER0L7hDkwLREQtFzLqWwQfuHjV2mc7RKMfa3qADWS1KCi3qRRmPN4ugY8cIiSZRbs3 0auSguwc8QWLrF6/RaxHIw+TN6T9JjDLJ/kqhgo9TYbbBZGYOt46u6GwjYAJVTKf1otNEXvrhTfl mKGV8IQobeM4NSAJJVdNFkeYAl9OpdXL+lZniM0RwonD5I8AaDovDXEv0Cl55ko2LukOV9UF2K1z kj38wWeDPbqDyj4uzd1JJrVntuBW5rivg8XSGg5tp5NluDSetYLAWAuumYevW2qzsIH6MCIsZeJP grAb8zj32U5a/F8CvjtUg6LdqvyIbi7L5tulyMQhQ38zFOj8h8w4YYVdXH0EFv2g26lFP/SxToi0 I3BS9cvWyZtHA05kTE/xEj9v9fW+EmBZ0jovNFFhpdGZNxNSUSmjC3dLhZQ/+yRL5gQoxRM+nSUi qwWYn2D6MQKQrP6y3jnzzc0bXz7loIi6DGb8jMSWHBDl2BGyat6OYq2zj2nDZO0yaHWUgeTI8KQ5 afHaA887WSfvZDQtRtSg+DDjgKFC1LSZC2f81/z659030mUD/FlAeRFEot4d386npVoFJ+XC3ZOB NrfiygylxaWFaE/qiaq2RTbxNxl6o2PScJO+KcKvVaUtwTV6LgzUWFRPC5Jx2mGaqVNXSZp4/J25 7tUDWcs1oRgnYe2Epj33Gk3owIX9nXhwYQRIXS4K6dwkqn9Q3xrHeOZRd7Ga+58hZDnSmUwYFMd+ FP8jf+X24xT7azGBCj24IZzPh5T4ta9PoAz2cVRbtUgCJYbkufP96hTQ+pK5l5FqwMhzG7LqTvRY P9U4L3vG1Kye6yzYHGhpRkeudW9yKeeCS+F115UT2h8KkuLIhOe0XgOvTOwE1vtRMB9RBYzvD0jG cnxHZYs4BqiF8WvG0LSPSm8YylLq6uN4KUxYU9aNk8ZF14f2HIvfwN8r4K67VF//SJeq5snf8X26 2nJaUFaOY+xwGoT++kuR4Qnq5YVwhExGI3/DDNgRDtCrExJrtC/Xvo24Twrv+VbOabR9wyUiQjmX anW1PVrIVG9TFst/IGlMZCkfuQEhk7DauDmikLLZuZErrXh7ee7agJ1LPhTrqLBQLKRCAzcKFbse G15USTPJgNimy8SpL4sTD+NpHC1zrpRY77bpTLprlOEuDiqe2BuYtgCVAsabVh51Aj104FOywsRK uGja7LHIZewoC1wDSupVlVeN5s7cuah2EebA9DmCdHX1uvvUXsp6WfKOI4gn2ZjzJaz87JddfNwr VbSxJ9Hx5oN1OvXGtfYoRNDttlcoJJDOxlA/n323s10gIi6QSYgmkhISyXy9HuKLqduEtNN3b+6G bZtsqXR9GC4NqQMgojwubICG0wyZoOSxyda0yg2HkgiXtAq1TKOXcQytsj3PMOQnEr0G9nFj56CT J3T6gC9Ewqemvn8If18HB/SGCMHvZtGXZtRTvDM65kbURBdrpRS7dIPB/b/DDpCHm+0Vr0VOwsqX NcQgxufZSSxef5HGsHBhyBSzX+bdPHp3NONSTaPF9zyi4CasCFaJW2oPwIlFVDxadjDn0tNEGFah 637lWZpCbWg9NWOD5k4zPPD/E8+7U+rPbidsFyH7epwBtgVqVegj4K/uX3eZ44Yx9cGfh/Oi4gxW DFaioFh7RFgPjwpoQ51UAGjyXoGDYacPlWd444Fi/crkbHPVoDfKf3GZWaq2KrbzK4kEbZ4yqEOu tLsE7v3KvpHnlLsdBMEy7kUjGCk/NzSc305m4Ps3ab8pJrrgeGdpM8tS2tNkT5nHuqDrhB/mWjqC ZUIVG94f9ivnWo1lSupQyjuzrx84p0y/s+y9/Y2hkbwP8uoV0DOWd3iLo8DmcXe4xTEZcBruxxwx fLqVmGRYPzKkG8K3zNJH+aorDIgcfmQ2b2u5EnxLl9LeJ0Rx+/iYTQZxlWAIQCP4xTeM5NHRncYN Qkh55nSAQDP2bPXTxUh99CbE4bF084U5zWHOR0/BaxtV8L/7ddOrkfEuj//vHcu4JkNwc5bHhgLF q4n2MJU7SOOa+ZnAjVO/ekXYkH7aGxuZVfNuqNlxVTeSR1eRkkD2ijTXXkD44p0bQ8naRciKGI1X IFYJ7JC9oBNjEWxISXJSxzG/c22WdjPL4oCZXa4t2bB9Fi05eiBN+11MS/yPUq5/1xcjPX7DPEB7 V/jv9/Aqb1bhO29EZWkaSoN9Yg7koDzKZh+PL1d2DXm2MQqj9Tl2LzZkUFR/507EbBrDDEszoPbz GF+1itJO9x1xM5opU+uvwrc5tv318ObyaO/pl3cvBQvnNYy06n3/VA0W7oYPn5Q1rqbSEoC1P/x8 xNYCxtJG41O6jYhIhZ2Q0/FKOgbIVGwtxWl4G7GPi99nH+Jk3o96r2vBfZHAQxpu6mEkpiMMWIqZ aqkiwQREB8L7qOhxh9fYAM7xrHlD7dSHLPvn0VYOY3B45AqvFyDKuq7yJGgsUP1UmZXNDxpxwSSL RARXs+vBHgefZYOxYeMLdLedbW5gGcT/fiBBJw9BRiBBJawkfPTlimF508hJDcdTA5rzoL0A6Wl2 HNTE2G2VaCEwMqAoHGige41Y1FRsTknJJPZzTS8fbz5DH7FjPxydwArBSV+LtANV6tqt34tjI7vi sbyz9jlvc9sHNKsrYx5EuzRkfFzWHL50WNudO/JTDLUeWfZ9oD57u8vLC+8icT9EGx6iwm5BumuZ 1Sz3wsGWoMfp1khCbxeIDLBK7ZG0oS3XtBYBEMsbMvyuiDVekF2uWvsGY48w+vjEimQCBmftscGC Nb8BYmHPWf8a5PhE7rN97USQ+UZETqYhaqxypadqZ1LCE5uoFayXjDvY3sRP/6J3IGqwayPyy5NR X2hWVjqUfVXYThacBN6fK8K6Opma+rSpKfWK2HYLaCZ1gpEaWhDDLnfeEdpSPlq3K5QIBELe7r5Y krkT82lEWZDbpikNhOBqu0GV1GMKF42uVkOBQOELk/7MaXVItH0xdh3rL8XL9FKsJwil25Gcpe5x NQ6Eev2BEadJa/k3NIcIiJbqpcAMqwwntgyyskZNFGBBEFd2ZZcQVdB7UJoH85FlGHKGjtfYPy2D 3vMU/4DE3p0wDzGTzJa4hRizKAOCA9qpF7S+FzSx4cF0YMfwDIsB/ntNxH8fP1McgJ0oyyUDv8mF FbMfB/5mRRdoe+N+K9mm+pchxcVE+lRrKsWKHvuSNuBaHjHRQimXnx0ExUu9fVdVYUg0qt2dDzUH 2dEggq290TM0GGoNnz0DXgZHvD0NZloXaJfnfmnjOwqI7NLyAn8ObppiJDSqx91kQ68A0LgxqmUP Q6o0MTsuffjl++EbnZC9ZlhhCNngvZjt0IRhk6jDsWsEQGA+q9+BsGb9smO9AkL4NPuOXVm64oFB Oy/bIP/+2/YG+dhTW+ExFIMKHCb8ZEMofor0G08DzwXNuCsWL1OpbAz7tAWESKAnVTi7/kApyA2m eMj1Z44a6UjxEYnqZOlfxi6qt/cmddh5N0NVJmv/CPvJU/iv6XiQ1xPmsaHfEpwZzIYl2pwhj/Vk OmxfgI+bpMl8Thf2ZorWUt3uNy7UyMsKW/bmqu2GF/rqFGgBFUhwdOkAmW4nxUGcO4QGZpE4w5aM dajGt+fEki8GgfKwDHj7raQi71s5m1r5LZMBXEkbdQBKgVpbhiqMTbf127ETDHGlbAxYpgIbVNT7 Ah1A5cOuOX99VDUXVBap6NJVa0XXNBPdstRd5VtgMyVqVvFBoIZyLdEO5up8HkMVpAGPpJcp+41A rMbpjULe9wIo8Z2fBB76Ms32j6iiPpgPG/5S8Nh3Dk3IVPS99y3O1emwHCXovgrF6AJtfH/wT2T8 a3S/SE3LkQSg6q8/qEvDZp8/hP3vShfYhqxYbu+2+ThoshFlep5Bb73ucID3fChuL3cZNYPGNiAa kD3xhfLGRETQ2rEfbhCFjx8FO4Xub9WBRvWDyzEL0pm0SZF0ZMbagpJcaXCxnqxsCnkAJeUHzV5G FodlN4vze1g7YQH6CewuUxlmJ0Bbodo2EiBeeYoQzqBv00HvQpebTOuCmMua+7FHfsW2ot8lXViy KKVVGJ4FPPYcgjd5e6+bRNi5FoJfKuLNoElTUdRUtQ9sOCKDH6o3l6Mmr2Qoe5TrMfyU3eoXwJ18 wdT3maqV7BLQQHPNmSwaOHMU+HMBSr7uDcpu92z0tRPOz9FMNrL74OdKOfv+r1w0Aq/LBRmVHvN6 DsFjOrjyGKER7wT3GI7lz4VBV0PDBtuXYsb85AMbmcBiL03SpPLzT8D5I1v+/71ucw41Xav0wFwq hN7KihvY7U+4f79s+e7nfhFYZIxphxcB9lbEW9ndht/rMZZbBExoEe3B/aCTEfc9UH6N70odxELZ 8TgpxZg/VriOU2aCb6EZuJY6yoHMhcr7k5O3B4Ac5KKthRdTxjT8ahzSoZOcwMGp3YPE46vaV+PR KyoR1/6z6Jf9ZPZK/0wgOZq8oW/BYqV+5up6VfkK+K2dVf1zfRsqigQ5AauDhxoJ9qwKaNPuJZL9 FI39wMbZhRzaF4+Tr+gRYWzRwV16TYbdF0U+itI/pdtaYDV2gcvTI2nu4lhnKlLZmH/6507c7H+y J1QqALETaqrTHNdPLanBNdtc9OW5ky/+y7pczbzUpiDI/lAyQnT0CDwUESDzKyJAq1qJVIPTfHse qADH+b86XUsqE2IUcYXygPTRu8yUPi00eQ3R5MwJTfcv5IOltDRFaSUcJeYr4uzDD7VwBGeQfVOM DyqhDmhBDzVWmOL4aCORvB9uY2/BO1K8b3O991+ZlymrUSx2RSiLwPaiStp8KsG1yFHXZ+faKxe6 VuaL/oFCQdc/NCIruvmgVFBGPtAT//XbA4um77M7x57hmb8jv+dYI0IEMQJMd4dG+Q/sCY0rj9Na miA8GyN2k2vLcNgXdbCDPd5MJiotSmwQzC4J/5nX8p/S/f6ARRRB+x01dsnZ8MaZ0Cmjw+XGmWmH G6CxC9vEflEq1GSSgDNVQyEw/dBWEZkn+FW1+Ct1RaOzAIIm4orBueg6smDdkmXg47XL0iTHB5E4 djcfhIvG5yrEFQuF737AFrt0uDEgwtU56AuECRcl7IgTixFw9hZr9ooAXq4EgZHF8Ku0RxJRZP+H NqzObXUN3X+Q4AZ4gyCorpLf3dlWV5D6CdxL44hsJaiHaWtavKM3Mruz6uuptOmlUo0HYu5vEyXQ BkTNSFpIk0ozU85Y5YvdaQGwV1e0ioDC0vNHyvrQannhgo7HNq4mFHUQnqmqb/+4kD4Hezd6DDAs bw+XdEy7YD4S2D5mN1h9+WMhHwPUUSzWhtgiSNBFcITa41jtuJB7+mSGGaWgt4tf40+6paYr37Fi ALTABB0bMiYIAFx+cN2lYT2RDJ4PxRsMXKWf3TZVdOowS9fFbQ1l8Cpr4j+8Khg6E/EwNTGcnlb5 c6oPvzvOqraNv9G4tQW03GYjPJUVjbH4WQYIh5DSSeaHY7FRRNHvzoKiZrKaUZvqEbVPMoK7v+/4 wNwyDQRsKMvOUApRu5VAgYtwiXYxY2ffIG1qmUgqvNgqM9YwzkLWVYbOvFyhKXJleX3/35aUhGI9 AtL+DpJa6w6AeOXQBuBIc7UwwCwSNqdmef4xsIb7kHQKVEuJNlFeyuDRn8TJunIHxXqnxJO1oE7x 33xiV3yG3Wh+oXTqzr6H+rXq3Lo82MfuOVEqnUs/suYclNl5p46+rrmDESFHrSa2Nbdix5N/8fwl uG8uwXbs3jcppmHbX7XcZGfbJZsH2841DiOJJw8T+f5mdfVNTsrjY6ybnnY2sDZEeeVr3AyEPCWK 5jQPB/Ll36uX/Ee6NLRodnYGH42go3/Aii77WUKKzI0pqLM5h1wDM+iDt88MzHb5MyQ0EN7Lk3SF j+xB0QDyZDl1gM5YCcoIACXK3A+tZiu448zXIkk/nS73Gs9AkIYI5sV6LAnBWp2FWnXqFhviXQtb uSCKmoKzKixhKr1rT6PalKD+6FFpDq5pcuwxdVDVyn10C7XL6iF1Dh1uJpriq0maZVOZKz7/PIMq GfE9H4JEN2ri+FFZGliyQkK2QQDGAmZcKTunpQdCjaIhavQ7eU8qv02mvXYO3PBQcn/5HUd2BBJi G0MB2qr6e6IWFlb33BwDJpMU0rMiJ0z1hpfGqR51TaF3jdC3xaikSJRyDTXOqB71IXxokm+WN1Fm 8nV+Yc7JPxgc4+KC4ZJRjDq4yPrdBJkbd994tC3//IJvwqLmz4WxcP2VBrB+ltEqgs8+8M3fMgtb TFS7qR46RGYeS9nIL+UBUHGaoMDZuyIQQ3FqhV1X9Y0tQrB5YVul9Xo5HGwbHcYfIbqNhKLNmQK0 5TayWhLHzsYtD/ATtXzxbILvetk+ijUSPuniN7RS7UPtpaUiz5t0dwyh9l47C7mcdlK9GCDl06D2 LgdOu4cUH6R7fA+H0cy/dWUpSh2REojqzWnNgdiiJg9A4FRrwy1uHSKnqsLzCwV3qk9AL98xzG2X qDh63mCnmA3svjUd0NRa83NYKKKR9egl/WiF39v9D5yYD7pKHajNwABgP4T4jIOcX66fp1yhB2X8 pcL7qqYa2UslB4lwZC2kuMiy+Vr6Gd+nRqc0RaqPbyrz4VXxG7IWI2F0Y1uwQfpcCBHyYRVVufOi 7Z4+YJuMovyT0cpJ7Nh7BfpxpRxU/jwG+pujq9yQsF0qZevWuXiYeV7ZdjNpXBiMTQ1LX85GLjmp QgFK0ztNnEj2pPBhkK/rjY7jdQeeN5tvcwfi7JCnBJ6SzVmy6BKLbQn4XXHAd+I9brSjXsGqNwJn QUq86yamAJJiHmsPh2avLZRHaIzhbt6TXRULqq1PJAmP1NP2t1r6g8dXQxSHKrRVjmTP/J39AVyw PA4PgnGi7Qgbg1j1Jc8Fn9nA93EolYLINjwbvubcTM5WsJdP7bP7cuutkF/zOV2purpbdl95HhMn BZrFzWdRt76r+NCUGvf4iGdfcEf/h2Cvm81/u6avGLphQuThzW8vvmroZPEfw6mjRcuSejUX3Lw6 74HI3Ny79Tc2VL/dJ17DRGyarQQt7EvwEGJfFH7tvyF0FDDHHQVygs0Ul+PEijvAkhj3Pfs9ZyhB AW074WvB2idVix6QObKjLPnMeXiyLhxcNcQauDisvpQNh5MCJZ9zm4c0xsnb0WdT6OMaqWP5Xnst ALYUmdCZljv+kI+vdgeCVhGsdEQtmEXS+bRlPE8h6PTNnr2KOAT8s6wAwUhzgI6vvnWL3A1H6Rqe 6u+i5MlkNxHP008qrJfR+ZWFJy2Z9wfs8s0S9WNpEjVXopG6UVGMgA4fJuRvs/8o3IRjGvGPU2Bd NTe/PQpq5QWza6cPpRPRMgRJ6PA93NuMbwsMt7oThQt1a7jc+h1wEdsMjupTJurqJ2Zdr/S6lmgR v971YTpICOSJvZ9L/PTzfFKQ8BjD9cn03ZdIYeWp8AEB/Qv68pKF6qhnOVBIErDqXcb89+0We/7D /dSRNbK8Qw8Cw76cQ9B2xSo9MiiCXA5Cvu/HwICNupHfhAkB+98OvhOrhy1F90c5eLwYAw8Hbf/R mvoavMY71MYNHNLeMKB39vny0gNw+U+FTmwuid30xpJy5ox44XvWycOSHCjeVVNfOAYa2/R4mzah Tw90dxTQa0Suyi1pbKYAnTtmYkpvg7QzhZzVAZF6KAuHiVYYw6bjuQdNorWODYwqhh1/8fPSM1o6 TD1YqBqvhCJCzRIIsDSs4FbHXwoJeZocW0pTYaQotGmLbWZHrDMRfyEnUD+dXmnEAkf+acaraNa6 DvZqzS52pwyem5rfZR6q1n8NxklPjSbb7KOiCmW+0Hw7djd5oW8fhMJdihxKpbQdXp8gN0eGI0VN 6u+4h9wtqArctFQ158NbedbXGjzTMdFSi1SM+i64J9NzQsWYIqwppxV/1pixLYfnt2sHUegHOS6j cctHfly5D72HC1YmWjPXs07QxpCfdEHZu+EfU3jym8XMXgYvGfeoRE7OO29u6xVzUAxu3yfxuTRu sSalRMjTTEoiDymAbOHmCV/bMsURVhrid5PPRMdcgqEoVN06B3vcf2VnkC8GZhQXMBbNnoi2StcE yfa00YimSxQdASHCcsqbRDMHIAP72QoSoLeH6xIO6q6McKX1Yo3ea9k/b1LKRpfuBHkwCoIVk2l3 2I6WDeiE86MbGwCpxKrD0fKCIrdQrX81aet2KIuF3K7YkgvIlHLpHO5BFvj94JkrkGHgK3jE1Ivb ennQZj/iJ84nn7pbrpFpz5Ou66eWxz7LQ5zPUPPMxs5vHPP+YPrWy3YVzoaolzLT7W5x+iDU9w6c kdxV1iHEuckdnRE7y+DsmVgfk40fS7cgDYpXt3FQYX4bVP5UystqCExcs7TQD6iD/Ct1iHFx2NQb 51iBtJYZfliosMqPaa3VfxCLe3QxIulSOar+IUeA0uI6kHSWhP9JjRFyVeEt0P17ZIGR8NObHp4L CGMWIh0WfV9rATji8PuJXVNaor3NWmgb2hjXNXB2BpTVTiu9G5Vz8d808FYsHv7fl/mU9+B+xzfn ldKY/Vybh1u6ZJRcJgK8nhAanjySwlYtEz45nUVZOGai/SAAyzPV3nbKwvYuVQvzgaLGYMO0pPbF 5Ss2Ib3EVuuu0gQC0NRmUIisI4cWjo4cwBhkfGjGV7C9nC3ALxx22AWacfRcZx+vAiGvTHBP9sah VuHSaU3ar15ABbhRATb6rmN3567hKHuyQFIh5w9wQ8zRs/FZBP8MTu+2uL3bCR7w55qCvXACmPcI 1gP5ilN5zKvTHXOGiiXmFg+rJhlxPhfRpohjNs3D2umg0MMKYvFCAx2D04YjXcMmB1k1Qg5IilbB i4nfdMHZyGRW/5iOfxP0b48/BoFH5FtHxP7l1a2TbIDerQLIKy2iQdPYSRQyiaGuMqbfbvB1qMzD rc7iqzosIGTJRTKZoSXpvisNwnw7LQMAGiD+ggPP196FjsKRi903QnIMCcJuusL7vmk2s+y48VCB 6YSPhPww3MjBjWMHapxLuWM4Hn7yGpG7xzRkWS9AJdEyLiBgKfnkCo9S9hr23qwQQRwYTXwZOYKB 24r0Swlqf+k/C4xepzIF4W973z1QKe8OBOHYP2RHBmHzPIdujZYeBALtwfUwYt+8uQV362pPc50E ipNov70XQDMEqb3nOCwBxzJFziLRh/1lhvnM3yx2J0tp1JLJwj7jsexMAT3+EHp4REg+x7B6VGTd sXVFlhCd8gUVhvkBuc4OF8LdsHcAF43AGhgu6AJxko2oUrAKFJXddCOJeuLHqISr3UnX2+mZLQR+ VmfjsTK1kposj7wZAr6k23itBYzQibGQn/DfFWSxSuv9+jzMkhGGuec0Pi+ZB4tQ7gyZ6bivx3m3 laR3EOOpEsflFektZsmwbgDEx2FS3hhTTx3wX1k9x1ltxuqTK8C9MZxpl9NlKA3enEOikTQ0JCh4 242+8CoNiI3+Gl7BzpJ7LE5pHmGVKz3oq6vHN9p7xS62/Dn+bboC1VI9bvNw/1EHUeemcz8GalFd k5TnLRcyktraKrxPnRzG+4UzVujIsw9RyH03/0C2SETjrq46aMOtYoiCaV5kkl22wmF/oAah2gnQ DEDWQeINBR/9AWEkuuZl40bhk78g3uW1LeYAnJ2F81IKbam/YTvdpwZFOSfy6cwE+ry7fsvCKh3O WjEuQ4Nm/EVkfJLaQ2ERpc396+7oPxJd2+CayprS8CRHs8aGTbYUo8lWOfrmbcH4w5E/Uie2/Di+ sUiCXqsXD3hDCqLSMnpscXwUZL5xthVd9GF47H0brUzY+eoe2Nh2ebD4gBRfizEd/NN1VUrV9Ai/ ksTM+qxTkIylAU5DN1WlEsbZqdF7hswJQirdnAbcllBsclugFP2AAmredgd83+6G53G7A6m6RUxS S1pStgu+uKUI0HXtx7l7EPtgGmnooCjjieksHfnH+J0nvxT+CQft9HFyjaRn9PevmVO5/rZNfgtf IJhXF3OtTMUVlCKo6xzMEVqbn2DBFl6Re6bhE621z72IDHAT5thrknUUNbgbkMWNt77yH0z1nrag HLFGkQamqSW1LcUbhBU7aujbz4TCER5ap+5HPqXPj2Ky1Pzgu4coU0n+qxR8AMtgtlDptZTdxLFI wfi+wmPBMpBjKzIlWue1/VJxdBsV69fdrW4WmejzmpttWIdeWbWK0+R9zaNkmcnuU2rjVBwaSxHO OBlxrCZP2Kuej4Dd5VM+9OG/Yu9JVOkPzP4f5LKaayNR72hrYA0dztqXpMXC/9jtHnJJOMhYAL/6 mXHrELQcfQgYebAivCJ/oWTsnD03lomzzgMff7YrTcZJZPb9GCf4aSbpbTwGao4SCZptYdjl18DG 8mBBaFxHnxaRkrj3F85hdpjl/+l44dlR6wnUZMXc3kLoUbahMHT/tExm9a5fjeQREdW0Slnhp0Um IpQCLBKIdFOI6eMD+4usRG94YNKSRntMaR7SaJ70j87D0WNEw51P+Wwid7yD2gs1xQEid4CmviYq PAyvzkOdO30S8PcIGYt2mFwfsFWMM+SUbinR+Ap8TpHDD6Gs1ajbYDmxC1tSER+qG4PkUurr5ICd X6vTIbOd8btfaCxU/PeoQVXUMnrpmfjgynlQuXhynsj4pfz4SG0of9aoSeyzszA4nFEqJavyV6R+ tPnM+LNmH6011oB+0Qxsesl508kp0ptr8cyVJca1yMA3D9BYHGDGqckaVnzQcD+7zSRpwcdE5coV neimt+LSZRpDFQchxHdzOBmI+OYiNOZVJOllNo/KfXd727+4bznjFGXKXrMbSdCm8GajNAP1kdER 4AQRH7oNJRTWTRGI+KxCfoDO04lEGptb6rgUGe3/11MZeOMx5Bx+hKXFK4SQ/ajY7j1d5Ne3Uz6z qQ+PEJTNm3H2QALU2zpcQmg0dQMKIkvUBZ4mXDhawpb1MnfT9apACdlTZflXY/B9rOPhndIur7hh DuKfzmtgI8qEOhUb1nGIrR/LT4eMWNcyZpwG0xO8WT/1lsC8yJv/kS7RxpjFgcquBVTtJwzs+pbB uZu4EIak4OhtRZYEZjWwOQ1Z8PkGNg5tR/qfbOaWFEo7LQpYs/OtGS/rNXPNcJzP2B9WcYH5k4ib IQb6Fe6Rp2jddbHY125Vg1WyEqNVh1xWkcVFZ9YSwXVQI+cgtYTeu0CpELd9hYxk1miig0KLj3JO Jt+QdtJWCxoGCRG7msi1/kj10P6RxqfLPX9a9N59xMjSI0tJd6ZGOT4TPj39TLoY+rZjagxgc2rX ro5aNEP4+dNbaR2qVZ8HZiq/YukQM22C6h6JACo/JaE+UyAx0gvwpZk8RonviwugzGOaYtRiN7zS 3uch25Tv4SuxJmu0PcmpaihKXZ5JRefe4sJqxbrJu4dCwjmxu+qfJ4JR2ao0Lb4XLSeBgE5Tp4rz Bo3beVeY3kGd6/rb6lFhsXTOLujblFGhBBo93SEAEEZ10xO+sdnljQVbk/HVcR2ICGQiK1MtrDFR RgQbsV04I7UaOupdWivHGEhp9peYJ93esib0pYjfuDw3G1SglbRTCEqZ/suIklTAmonNH3BCvQpK uAIZhJRuzf2M0bkgbGzm7gYqqppyZPL0dTCz/awb93FPwOLhOVqOU6YmcZTfUXZYlIXk4dJc5f/Q M05sDS6C03gPofD5+8aaN9Hk0rXAufj3szoeXlaWdNIJ8LhJnDSc5MNRJYNv66ij/KDNjRlkpp64 Dq0em3abAFPLmRpk8OzmO0MPYzbYICjJ8czlLhuvpEIsLevutNe4kZ0cXD+OqbZ/E1J5aGTcRmz3 +1LA+xQnuEOsxkLvJdLRNq2VJkEBSVE6EzOTIvdDWlavtYkYpdmeHp/wjkN53q/xT8UeCnIJaIPx PqdMKQhbQmSHva9L8J582kvSf8eqxKoxTvhYpuI2Zdkx4f3eTRanrjTNp/yXEv719JtJ5gIyJPNb xcbvg3yigiUboMRMXRPQzbZ4lLKdUaV2whIXTjsWqm+zEL16Kudy0A6NnG/upVMo2QGKH703H+Gc Vwtm2vaVC9VqbMwi6pqcxTsF+FZ/4nyLB5RTAl5NRP/TSYQzOXD1uo2Dg/3UJXLMD9I3w98VpNl4 EZ0dDU/E//cxDB0PEowozV15H/0kCrq9WKE1g6RiMpbVCXQNQ0qxvZmHhyW6e+NEo6neYQp8r6Ls DBOgXL3btYyhn5TWEowiIamnTonT4JiHuStZf6F6zyRy+qmqVrW9858hzrCTDSS3snD+g4iJ/ade pab7jV1wa6etdIheuEsOlXg7kCADP9BdZvwKz8txmrFrXfZ88MLZkk+1yehmN4wUQ6yq7M0zLc1T TtQ5V12JJR6bziRWtUf0VmedeKDUBVfXSeyyt+GbUPSUoVEfMP4ythDPsi7KJ+dIlcW1XBEt793m aPaIxM30MGXgFl1ljb9z6eQlXog8B0UU5fENqmGIvO3qvTcKDoyA60L7p7fa9ff7WgipvzDZwL1Z kP77WY7AGx4lGsRJZ8HfkOU12p3ToXnbm3XkR/dRqrfwbFv5pU01srJnRBhumo3uzrLYnkJgJbiB HxFVHcnZfUvUtFYUEGDwKfwWhAVyPnW9a5YNiBcTIqhLxyPriuJXTTlC7PDF10l61CLmERzD2sgt V+V276eGoeau8H8nRbOvxCrk1HBAKEkeds2QH+cijLLQTMW8gg698rtbwYMvHFBfoONHpOdeKOnK 1au033FxPHNuxHkuQdoHP3guzEY7V3UVctUegAulxgGn7CV7gz/KQYTYvAbZxIRhQkW11R9u+1Rp aZ75fx4J6X1OOuhqmwWnQpg9b/0YMUSJ0OSsYbS+BT3Ifj0WrK3zK8cZDnfTwyS7tstXLuBzsdRp 6WNBwsvMy4fgDOlFk96gQ9QC4JnAuP0kufGw7RtMFwRTZvqSX2geOORzfIdgabMjcvVl+LTcU3Zh v/RFMc2qDR5Nvntc1fU1hCid5+XMypXVo5TIonuWPZAX2xkjPfNZ4IO/9MUhntpLrmqUEVd2C4Ep pYqVov5N6A0kMW2ZkVUo1NkhOM9Nmdgy3o5LDReyCBzFmMqsJmU24oyIKs0OCKxpHoKRuDbYumxn eqDWDFtry6Zy/WIwpj1ubhSxX3mOUKjrdyNFEZ2fUQgZ+MlKueIFs8Fm2fctiH9BaVOUlhFAh2Lu ugtUscUyy9DiaVptjgNd0fCj4Jj47v7KD2HJ+oDiPoJG4B2t96voZFUiqhTd/fI6GFOL9Ts4JAc2 xnQVXY8KTBH/LCPUoDbxqZYAhsY+vljxI9uy5qXPfoFaI9LgvaNF2lA17Agda3R9Io/gntxObF5a ISi76eMfYbQEovBY0KiyuzNSNUCwf//bStwlSeNQVdxicXXFjaTFnt5D/C51sxjJ8C6oT51hVqBg oeqnorBC3jXdp2YLdwNW0YuW+S6UHTeMZsC/2a69OgWFhIMNK5K2pXQiBQy7I3IDINOkBUAsu4A+ 8H58WdkfJl4jNdbA+JdPbbwBIYuX8F+HI+5SzEbDQwC2uJ8qNsnL5sQ7erPDfVPG6kG6iVRH6Mjl M2ZpDX3+j98lmWUzj6nipYHATM2OlNbhzgRa9rbpfROb4NQXX4Zv6vz6QVt2cLSgC0ifF8J79lwO /hj31gN17jw8csbyAyhWDO8hS7r/iP4oPT+GaJVAZcUGP6kSSz9mojrS5h8I1AjSRefhhp/DSwLa OrYiEUHKBlkYXc0vO3K61lNAp9FSkVIqXV1CIHZKl57BGe/FR/gSSMD5hdv58+1W9T+3Z0fU9QH4 7Vo5WYX9MOnSwE8zXDMVsLc0q4uvK4au8HW+INTGPbWQNTzVOkM7cEggXWJl/zHTEDU3t8OTahJQ eDwn8it0R5hgwRdB0Ue/oXCHL7Kv6MDXqzPIiqA1byRs6kO0wvLb2nXuua50Z+mwqfoDcipMkUGZ bqbLMIqL97zfhFbLHOwcX3PigWytaI55VOC9RCTls7Ux9mqLyNGfmlBU2vTzsFnTXOHgh0PvBFxM bSSEPvhQ+O13tjoIX1f3t7IzlYPnC51NZQm8rqOF5L5/SUjqA6Rvqaxjsay9idFjOwOASg8itUPl 2vHPu/lVLngLMcqqjCT2zWVJ/0VeKwJWUYhv9S89nfrt63Z53DQhfrtxx2MVIOeHfWDUHLScQgJL VVfRxPbVpxNgQesA5qXjSQfh/ewQ17WFhiqPOQnSc0mzhZpxhgSVkkqBoSIT2zEDugLOp5RLcSaW Ya9YAwK1C81+/M29xzmwk/LQI2HzwMkLlIsoJAezXQpuVtJSXVmlDnEtNTd8LMwZ91hBf2kdjgsj vt/pJHBxbsLMq4hmFbQHFUtmdQM9H0YPgKQsMvI3GsbcXzz3XdUCNpShhOyruf5ispCPYs/swX/V wL4clSAcOiQ0dkrgOvRySK7j5XwS6px0Gmfya7fQXudKGkhI3zwUdNDRdM2D6/izkKRl83cEx3/1 W4ZVyBHRyd1/UT0zSNw3FR2zSSrV4DO5m75fG6ZyWYyNi9AlPDKFTrr+DVDKWuXnqwrOkbF3iAwd N9AOwD5erhNrd8arj3ADfvd0IcKHUk+RlQuK14OyHz7XiHX2GuW9Czoq4TdMQorFsyVJASNWqaVK Lj49R830dnbnlBz/cOx/9m1N7B3Wzrf9Cl/PE5CcSooGisA9wzbVEE5ULKlxD9cO6Md13YbbEEuU H56jgKXd17BRpHYUIfzwGZh1JguJj8MGwTPSzo7d7M5CXl61oGM4mX8zvOWYeTJXqhNUvKbMM0du cMoFLh6zu7x7iN0uT5MLc8iDKvOmmFwr1qGqguZXWX4bf2y83TVWz8DjdxCSCPQCRceK+TNXtq8R AYfiXL0uwT1+vJmQj9fg7YRb1IYU8J/BfE8wDjnHcWnQJ+P3pybNkzPsLqBsb0gHYFEDhbTLdwgx KBTWSISS7cNvgEQ8QAEZdDJF945BjBuE1tVxqh5X+HGEHeOcw/nV/68lEm04M9vNaniFKGrSzDET O3XFrIH51exqoe58gyijJvqPBk6bCVnJfm4NSh1hO6gOn1wti0c/u7e9TLUyBcQc8+PMt2P2ocUA NDq8ZlaxXYucah6EpPzf/+g7d0rADsZqE+NofPqNZINE3TayPjs+UrzdatCMWOouc/6+bO48POfS 7ApPIgdtSN5uIm8qxfWcvVxWCmFgvLr/lnemG8jwSE7IK6XQUwAN+W/60JiY4fJFU2u6GjHrHyUP CRYrFf12JfjI1v3DnvTafFrqLvds/150Eoo+agpstXqJYdB1DPQw2YY7KfwvquxW1ftyZtxmuIVv UtKUJZMs1LcNJFeVBc+M80P+O5Vd9HkK8gy3Z4hweEX+GYpgIsAagxyVD53hwuUgV7uQFjWmhNa7 fYb4Y50QZLw73AubdpiX8p9lhl8VrMiB09MM2ryaX06J6wEFn7oX5zwFKfXJNyHDwMhVCrwbx6Md cq9pVRuP7dXIPcVnCIvXA1XYgaIBZA/CUaP3LwA+yJ5JW5Mmk6696y/szwfNH453dNymKVpqjtaJ tlOooprOqOHL2zbvTJOt+CVt+9GaybyXPolyCKrApJeyiYYmrOvX4AVX9pu4VI/xTCSBNEPZbLaS JpVvTS/c6ZqjR4rR7kWTJrmDVealXAjcVWR5Oj6odyu67n4C90EXMWlxZJGC3/ZEnjg4UnWy2lxH w1f9OTbSK+J7x8mS2jkGghw2lAUFeJ/I8HOlyf10OK3lw0YEhKVWgXRAP4eLf52JoU4UNHzrhCVG 2p39Wd8Q8im/+c5uTGQGgF+KXJzgxbsrRsR8/G6SRpj0dZXH5c4aKnvDjaC84I7MLvx2sEJQobaf si95E6b00FrgK3cXgI29tFHpNx470T0fYLmQyca28WNVUj9RZCmDRYp7Mu1G3wxayzGOTEVy8Rxj Nl07OtaS+gjzGeEJM5+1P5qlJo8/jaR8v7Z4DMW9f/QD03H9Ae6BZqjjRovv1JT6RrYnrUYEXt0G SmRuafKxmW3S863wfh9bHEqy+T9WALaf3Z8i2TsGS6aR2hdKEIH2pCEJcvqgYiCxn/2A21O7f4Rz 3IYOZ2Q64g5lI+PYuc3oyVT2CJZQpKtPLNiQE3cggUuomejfFiV2OAQF06OmHJopsfvAY7yzmFVY Vtl31leOY4HfwAIE1a9MrSka3bPEPZi9MPXmt5DjfV6+rbzDHe3IjJc1fkEleeD/MTNcCWKQtEIE l9BlVeChacLrEe1r7Hbcz9FSId7v7D7QjhwEjzZWyuPn47qN0g3wxdrmDI6JMZQtXmm48svxGLys 2/lj4/lWfi11G1v6QlFQNeoz3v8Is9KUXA5+vEcTYkTVZfO62k8lqyd0YkjshVfdpgutaq+60Jan IbNOhZ4n9u2e7q5MmroTA5FpL4oieZXUIVMHA04Wkg5VWDsvpInlwNj6xJ42PLzg9M7dS717Tu8r IMcSchkmcocY3fk89B4NzuyIK+8VzlqRcvi21JppK3CRjGkxeUH5DpVDIMMNyL3c4furv17N0PO7 jJn++fwMynWLyAy0pXJBEPUB1p/FPQ9rvEC+nJyKeOUndvvQN2i4ed+DlEfUxzC37eODpSWl7jL+ huLiI0jiD9KUXMfK8Fvn1J6gYjrYl/6xlFQxZ5t40kOSawd+tmY81pqZL56XiGeUDbA7DkQiGkNQ bpxJDQEwc/YVIjI6V7jdot55MRyuH03IeIt+ZqFHmjk8cIdlqzmsLkNS47YFa3bG0SS+QGWDwAYB hZgH0b7NnhRzK/zz76Rfo75oogPRuQdm0wZEkXIUQYnMSqsp/y4ZKoZugO81Lvx7nGnTbXQ/UWnm A0Fq/m3SExJog5cfUP+0YNXLJjzcOShzi93KkpRlc+tHgdmn2MztMbGO9/9d3kzaDITS9fv8CZ43 GiO18pYIpzG/OQdUe8nezLDhT0+4YOqJh0P/qUuJA7U1c40kDvzjtAOIEiLUNoKGpy1rlsQNk0ZZ kqsMKXYS13k7iA5FlffNi6j29O/kIjOvlQwD9AwCI4Ld5pbZ1KRaAQwTiIKJuzmAnVq/noua8s5N YF3ku4ZPP7Kwi4BsbPfAV65QKxnINGrg5zCGU3WzqoTX19k1OKHDY3oiFVEiLxvbRq2cIDJMAV10 baLVBbA2M2AdGeGScH/Nbb1G4sxL5kNeKyqF0xFhFEnwXn+rCTi2J4isKfxIZMRWj4Bt6wvPqWiI HhJd322G6Lpyh0cmangnc3IUZhcoQjDj6R0qRGL5B0T5csnzM21pJcxGb4j93bskmZ0ezPU3Xt5x aweki4KSz/2NaoTcOvKQydjVr7QqSvXrvpdpvvvcDHKSR/ejn58ajPhG0Sz4882oR3mA1NFK8+WA iXhP8utqTy5zFXoXn54tGYDNwYKMLdQuA9wbMParopuBd9N6rBLPLYM0VJGHH6HCnjk3a0UvsHTu JZXqmSpgPJtAAN74JoG11vtjZeRk6xmxaSW6C9nAKFqUaPK3TsPN/Sr4bi//zgu58OrL078D7gsH F70aOzCMgQF6fJX9rrGGR2qqtSN6BTYItw2rC2jQnd2Lkvp8/FF8HIQdepD1B7T39R74Jbodi+dm RTuhaEpp2IQOZqV9hVumEYqUQn6wHLxq1AlW2jxT5u2ZcaSsWI9wy4ccnC8of5Le5Nye5HE6FsyB CDBxh5sdhf+RVr1M1X7d7BYXDYNg7xOuGckkZT/3I/moETaYEnqbhESMpcXZY2042nwvzm9JBxtZ 46+cjdur4GfL0QHYM0/JrAP71K7Jq+5STw7sEy9zbC7U48qByKZ1c4ZKNXX3CbSnHBqjVJWLr9ip NQy7tlQKINq+Q5GLwKrDT+6FZSGtD13IF+6BiDunhOMtYMD4vbHYU49WtJfWeytTK3jAgxYUkMMq yY0OXBBtHK8upzerzvck+jQu9bqBeFp6rJeb/HQPFmKOwvdJvtdwsDr1A3JZ+2DXo4yL34OXVH2o mHe9po2OqcxnhMTUMBu229b2LHZzHA12FXDYrwoTfzD4UYLtMmtI5NC10rpl2Dch0rhRL0ccQRTn 6P9k8PIMJkZxsOT0L9a3Q+UxMFaJB87oVF9c+eTBVF+QH/D8kunZ9OFze2uH1z/mjWqvaOmj0Ur7 8KAgydfr6MelT2KAEnb+aOce4ndVhoVE71+5fdvjruE2SbXq3Zsy4qcKBg3WGLxm3tjfwwnok/NV OxztQOauipAViCcoDKVY3Xwe12ipv3nsZzCN9f8uRewVosOwI+Gv6lS90AMqI2NHFgN0DFHMnePE E7yEZ3jydb00Xx1cOLKtGjaY5VGr/46bXaRBz3p1iM+nihkhKzPbT8JiTsJbR+ksSJKbECzSnM+/ LOaVptASsLHuY5F8Q6WKt9GUPPsa0NWSgiFJ5Iv5O6qAsdHFIr7uPEtUsbHoduYkT0phv/OivJMI WY5ay/CrnwjI0qXxOkeSyQlJd2Uu3ls7GVJP2DT0TztoAIxLsv3OxxI6i3HS2G1RV+1M8Mt/Nza0 Vqpry+92slfMXNmJIEwyN3lomNAqEDH/G1Qo2gH8KbxY8C6jmXJ8E94MLOz64wGQWv+lSsFoor9B 4LvQx3VnEiofcFQbvvOVK4Spzd/kibKLMOzozWhUbfZwC+F+BgM8AzR7+QXT/pNqEQre9zTg7tTD hHK0Wl9OXNDSiVwZWDjFKUv6NPtluMD2s3y1oNMXD4ppPXm1VjOAFEgqbl9BVPzJBtgLi4/iHDWx a9RkoK3O7agmXBgX/APc+n1AKogCJn5I+faAY/BQpOE3ci7iB6rNLIakYRAUy03MobCcAcAGy1aR 8hmO9p/JusLh3tQpwmuHtEJXbUmmKw+UQ49hw8mPvFEJVde2tBF7KxiX1PD9N448yi4I7BEUvd6X uNt+xM1ItRCn3mANeNRAIljMtZk6iayPhk77FQih9Vt6EVATba2AqT5oyaJ3hLo09u/a3j5pOiNY o9t0b7LsEAbwWf+cNEvFjrBdX3Vz1tCmw3JoWT8QPDFgSQcoL+m9qSMsL1A4YXH/0NbsHIgnj/9Z 8ekvZyzJ8FOUrwr0VHe3FW6HFwP905u8Modz96BIn9UPeYTKxxukLVa9xt11ju1aC2VlsNkPlS7m 4lJbJl+SCIHFm2G3wr5/tMJF+yGP3jUyDRooTVhBGuRkOdvPJu+V+nrv/c5oNosFQsBCQJNHj2NI mC2A9BeHIFAZeR13oWs9YayRS7vSsKqMvcxR7EcryGUyQFCPKYjQC+ur9qwuCYRZclnd5yKkQmFq T8olSIp7oqyAzsNFkvRwxR2OTEmyAzQbELk7GWfy7TdyPMlfKjkyOTC2EJQB9FHrAZRemTh6lIvz 8eINerbimkOj1pehJl7VW9Xc+Gg8YAsFukDAmflJtNf6mX+2laHg8SNrHUbl4ySqMTxcZT+tTu8o N2lAoCqwVfTzClGjQ4iLL+i+qVwFINsYpkTjG9ovfGQVQC3Z0KgPOQTRpVxnnnxLBbIeNeyDunkd 8UI42rsG2+NzOoQz7D7iOuEp83Lyeyd4e1Jo9x8W91VJmaJqZ7pQB/57xI0jaA05PcWveUZUc7U4 hIWAJDxB0WB8qMnWEKo1DM0G2ncLLUvtGfXtrw45jGU5rOg+VgGrp+b5aJbNyFYFfshfp59rK9x5 Ja0ttoWl0wOC8K7YkhEVQl8sYEtPVJPKoBkTvBYIHi9calf6yErHr+R81NchVMumFyjfCdmsvgWw K+km/Q6zgxUgkb8P40W0oI55kaja12lXJUpIMcEeSlfylwJades5JdzqsHILAJeDVTX4RVqW+8rY 44tnE5rtwcXNL8h8pw5H5r4ZvkbjUNgkNEAtgYPxDlX5uhIBJ9OE1QqaObtNIEwlgmcOkXWJXbbI TafjTKlwl70tpdGz1gKw0QPukvbOaBLWXgip3h+U6LTeLoQcr6BcK3VMCm/bMFaiec19wvOucPhx UEz7IpN51YIHYEdtVc0oCBxUE0Uuifyuyyndlor9LmevOCiK1MYyGfjIfgdmQOXERJ2zv1yGRC/P scoP0KA2QEg4pcmbjdKJ1004CzeOE0cj8MKuNGLSufvfcAmyoxNIu4GG3eAWE05lepR9AlgPiXTo 705kwNGay6Aa7OfuyT4m9uUORt7F3lQUpJ9WLYWSX1eglBjM4zZykzroI0eXI2Cf9mEFQO3j/ZA5 u/5OjOTdjJ6/0yErcnQcZfAsY0ZjQBIQIbvv8Ff5KPT97YLfEkFB0US8U+tyrtUcX0aYvMTkb4SL ednOHu/9mHimgYjk3cbYdsPPmIHxhT52j1/hitiMF1DeDnwXInGGi68lrBB1jf7UoTqepPbx6rBg HJgh7oE9uSIdcsItlqa3D+IiUFAbU14knA8nJtw9r2KRyH05CDUQaY/coZ9sLOtTGHYOJapFgdNO y1DNWiFlQtdrBjN0zPVBOw57sKLJLWIMRiHh9MNgoG+U+C27qmr3g4wGog6uyDIaqFMeF8pVw6bg XnwXx6YgPOrxWBVFQfBp9VQ6MZnuoSkTYD9WCsfoaC2cNKz87Tdg5r6IQ+RWg2PF1Pr6o3Iqfsr+ H336LB2KDQSccgqCE43dOk2KfF3NmBxgvYh4DK/fwy5BNfOmF/78xAiqjJCQE6+ebGNq40T2VDMz TO+LZEcMO6vLvAsQTBcQtjNMc4G3HSvNVEc1mWZFmMNC0H1NKFhFQfX7MAdAiSog11mxnSJhVwwH S1xRSvDXESyCFAsqz09AWk8U+/jmDuvB9akr1CbhAUOINV/jA0qEqhcNp1lBKIcHyumY0oE7ebqk ryN9/HfDuVIB5YKPMu7gVxamPoxPZgjf9NH7cxHwVEXT85sMmVnbpRT6OfinjQNo+UlHbkFZCGvq Ka4RbahI093NrsciAB8AycIQzt0LBkwBqVXd3iiK7NChr2HP4mMRmTaSg+ScNcZwhKUMor54Ztmy mCrk/QrROzozWXv9t3yd9pnTscxghx37usGteSSecdI4TjTn8beo+VkREvurw77UHGhkZE9t+LyW GICr73TF5En2EscSMzSL83vzO+p9HmsCLgfDOkznq0ktplbFSFamHiJYNYCwTcIdKXdGwujOBa0u m5aH+TLmROtKAkRJgZMeP5m5EJOsZojYgnNOyhCqvHu+ajkgaZfwDKLGnPSk/aYrVei039rxqWo5 +QdvYkJB3gGp4I9FzQFsR8zW9auH46KYqffUnZ9+ShWIn6eEMYlenpNglOgkOrAkp1aB5GBBr6EC eMIhTWiWIl+D81mV9f9/Hj9ChHXaTvKD185qjnWzJufulmWkL4fLter7z61SzUXKfrntbRdlAgwB iVAAnuPZKJSkt5t42sJz9PWKKwkLK2vwzWNqK22WuVAvCZoDVyNdXxRJH83dA6JZUxK856XoWx3D nr5lWGXOUq5g8i+fjilQlPLgcwWG2tXWyKV1l7YoxJNDHbyRqZkyvFsgtfqmt6riasoOvxSfUMF5 jML18oP10eERMne16RDvwVtza6+rkEqF9yOOOT7/bthMTRn+q06lYVgcXyqib6OqeC54giQ75PGN r9XhsjDRPt82HIFqYq6uZvXe3D2IuZoC3Fgp+muGayKzCOejp6JeKpo4MFNQOv/sOqpqp/Caf906 FeHf+Od6s73QomZQSaj/UP209pJoHJzk1sc6aS9SWeqrucZPhVl+KNm0KxE6GFFSAbvC6eGsmgnx d7UxuGuPRRjO2qQSfwj3+OonQKttTYYgizY21Nd+BVxUxC2N/MspZ/aMaRckh4I9ODQ5vG9cW0rl MxPKhtfmRsVZxBN1Yndph4uXo8IA6yMfBjqINHqc4OCgmOCh9+JpEgCSI9FifD2Acx+hClMZGOFD nRAuD3PEv4NZoBScH06uvyd8QOSEtKlpiDWbZCCeKFVhIShu1gcFHxfA8pO+Wr/8Wd12eJ9RpIkR cF4aT2KbokO8LrHvQijyy99XA3fLyV4AD4+pcK5xKd19XEf+bTEGk+S/fWOc5CvRZy+8zJossrxD LGWDPadaXykioFKcP9M5gqFVQQBWY4EisIOk3JQG7orWM8OlvBxGQap/L80ldidetkYyQpRUaqu/ gNoDQRTy54FnJsGI+zs41dN3KQAniy5qn/g0AGWfV3GI3FL+RqrXpsTc49JKKKQSip+nYB/IRCsZ ZPhC2zi+jf+ZiFlFAxjFI5TMmLrefh+M8PhC4PVj/y/4roOkeE2TJ724X9PDJ4VKx6Us3IiWfSvh bAHPbdPWzcnYl92powiqyj2N343WDt39bquVDudbYJN5+fHkHuPXOS3Z8ARt0SYMirvnolYyohgp r6YLdN5jZS3QPnnoQiWMrYE/hIv+8d1m6ziRBulcqxcZEQqcj5lzxx3i/7JxThVVsQZqsZqZwuW6 QuXWmJP6stkz5i+73NBfyZ7ybxLX3iYWH59RpRKNHSMFE5F6GtI5Az8v0wbPLYrBSTyb6zDHrpUI JcAaMIX8TgLlPVKk4N9ADrL7C6sEqjhVw2G8U6e7/edIsYm8aw0sXmo8ur1LPTJwvArhZkynMDfH 6c/+mWqCiCSsfJ9Z/wprlyQ8pXvt7vXSnBfaSGXha1Eiq44R/H0Sez9kM0t5cRczVijmQGkwE9ux 01F2Wd5vKMlYR2O/Y+R9EbDUgoOzVUq+F2/BeDLtQTadAMH8lwFAPsZceFAapOwcnY4e0wInTCPq yCEGuzRGZhaNZijyv091THCP8msVN99YHEHvxK7Rzf2sE8nVbcVpOv9vLwUciRFCfaW1wMy+FBn4 /HHX1wOrakajd5XDT7ozcLZYhWqh6WhJ9Blzw2iLPz3VQraAcgb37ZMoqzhPUJx8h4i6/5HCc3T+ L4M6udT9oBHOvNb0lMXeWAxMGHsXYc06Z3OQl0H7DAFEGeEn+4CjzrT6MQhQ5o6YzSXFMb/Yt5ZG IXBV8mMKNxlxoRk64rdIS2YkXnIyYnuOwMELu720EyF4PeWVSqToBlApqJc2UtMpKwiZw97sRXOS /WdxpHOrsUxp/8zgDirIX4WCwIa0NuEHwWZDPrQ9+u3EUR3PP+SZs6VOrWcg/FZt64QRzdV5v3X2 U6MSZtJx3rEYlIF8Sq+A3P5zrZurYP5+nxymkaTc3f3UmSiTqpGXqlCOoLDDJ4XLg42BZtvzkgcC s2yzQwCv4cJ+4zSmMYyUowTVVgazZ6P6Hzvane2CvCJ40CX7uBb5ZZ3ZIYlhVC3ht9E6j9yecgtL UAJ7tHY7Js9IT+44A71LJxU02MFiqoqfRqUpw+YlP1ki+ooZB38AXpHNYZpskoxyfv9i0buDGQTJ tkzRFfXZX6dHXjcfta+htRV19q7xbHDC+kUAFA7FQYYF38pgQvoN5csapWksJhx8J8r0D8rY0rkj ssYZqBLnoTwXWqI/mmb+YcpU4fMHW5QeGmo7VAm1t08Ackb73VW0k8IOaHss7LyiX5e9HLqIkuXO QRg4MXnU3C0LxcnuDFQ8qIKMi+ozyRKzjO8hcIX0dcmKfBT4B29ZsqNW94Nj75Sh+1Y7dWuu+oiL x7duYzfrEwKCIoFkaMi5EW53U7DmluRnEQfvTPm6NtcftobBgNL3fyCrlhzEnhnktHZbi3FiY3sX WR4wnVmz/PWYt/ClS8Ii47D9hV4vJcmWMkn6FLsq3cUMEfjWKzfnk7p06ZX8jAxYoAiaqIPjOZRH Ms+YV4omJ4bjXRhf2UbYEga1N2wfc3BAUaRsIXZL8BFzciLkoyoKzgeXJEteOhWjnnB3H0aN5qey hbts97vmT7bPpmrJYVXxXOrLSwfNnH64DWe5aKchur45GFMnmzXwyTN+Tjrw6gogK4xOdpqlrQ7h cF0Xat6q/pTXiXKDC2YA706N2oKWhFSqt9r2Am3XVZlM0CN89N4Vvtc12VGnjBGgnT10vsyW+b8n ZES85zJSftkOoYaFD6TEdLDfus1K6mG6y0LcxngVYAyKLdrwXrhLskFohtXcXPBCgGFK+/WzMwmH 3k0gdDejWqGk/L+5CZfm+PuVLbfzW9nnFK8oFtn15whPBjX3PR2xTGq8Ij33/H5u11LXIlFaRxAv KZLOIaAbyDzOb+EDfPhtDSDW8YESW93ZKHo5kPdsOLO17lSnx2rm+RqN0u1zGXGFLIF0tpi2BoVW cq1axY3vRhNAjfF9VMVaa14A3qROxn0iI4if5lXjFyPZBp3Pm/Ufl6xUGxBURaWdPMkUK6bd+3VK 7WaMKE/bN13Z8elvJcXjVsaFGJE1cUPSuixVBZfBey6k03JoeDIg/15FpuCVb/91/oDoKa9zLViq sTX6fUSrBn6J2EEyIP0UtlcrZfPd5v9L1B2GRW6sn6PX2rVDCRzHTnfloE5ImSDux1DmxV25AsCJ RgfPBtQXSWs8WEMXM7o/uZzr6G8hItle8KHNja4sXGU2nFTx1cuFipCgszpEp+CLH4yAhb7758AW wQJ65AQJ+bJ404n9sJ+dEpZwXmhpYKOTLxdyC2FDQL1VEay3ftBorkPsvZ9u4Yd3mVCkHrp9FDdK RsjbHiYvrSGzR3nwCaClJ1dkbUYPg6zmWvQXg6jZo5fxrH6aWY4mdtTMji2L/pg5nxwjyiLrYRHB BqXyCmad9a6MkEKX9QnaswZ1BsZSgK9p8FMQt1sMn3ZY4+BFOr/BnOYojeeAE+A/xppu87Uia4GE 6Z2jGfC7UYz2Jq3gCtxvlReDWY1EKXTCfaAv06rPnk4xoVP+BiVcbGa+UXiDeyLhe9J/xvfvJ9h5 YB735jnm6IGJhX8sOQtLzk4sVVEJ9i1CKvoRKNFMRkt5MuQ4OSntvL/LxUQlms5FPHdUc9txiXWx 8f6hIRVniVQ2fjre57A/K1OYf/RxeD7UzPTEfVyDkMYFXTj1KlmgUG/SIL1fycJ6BtjQ3B7qgoEz gOJHFn40FOMooaPOwhM4DpLVlyImvjmPDKTNQltPUjQ/mBgA3/VD2kSKNOPiX1OKhEYzpHpcndxS C00lD3JeHACpTMK567TZkZzA+nqkFVgDyy9B8JykdDpFiJMhLIyKAxkNlOZVrS7AZ5g2Ns9dNnqz NN3P1NyV7hWbvALGF0hGF7tTJWQDKrpnuqNi40Z85wclhnoeAR46o1L6n+f5R1GreYlgPV2EHcml CyzSqf47M3Fi4zLpuiz07Ts0kYCQ3l7YF6M3V6YfmtBvg1BlOcNgac9coPAvzsfbVyWZv1q/REtA c1PTFX1za+3RTkW/92bA1sKoMoHGI6gfz1chf7B2tUoPFywIYlKXf6xaw5m7jahydGDiUYeh5wKb Fl55JCctk8p73xjnz9PzRezPQjJdTVOO4Syg5rwJwBb26x8AFipbFDYO+AFKmqFbtmYPq1V2NkG/ N3Vq472tD2gI5JoNwLj2rSdr7WzsfnplmKhtYq14jrDAZLxg3iRpZfBUG4DZf4yQnZ/XNB6k3TSN olL+gmKJuSJfjgCc1VyFv74XaP9PKHCG4gyhN6h3hpUkLUMozWqY4IDU3DXMPxcgsXvh3gojf3nU fOMz/ho8NXmHfKUYb9EVMXckD2pmwfvJXOaKlxWlUQN4ixtn3yFttDiqQId/15QvpkntJCaVRrNy ruPvg6yBMr0DlbfrTSZIW0eTSEz9VYhsLYZtnvYEimXjfzSA/77O2y8q2gLjL6Fd04UdTlqN3pm5 WU+miuKJDWRBIyTomdcSWau6l31k5dv6vjY8VyoDemUSFhUAih7899rVf0exakeOMvgdQBIq15O2 UWCH86RUsPMNLdegc/TLUyBsiyEAW/j6AlTnEoF+P+7XpsRGPEFfhoEZRwFSyT95N8mHBqYpxW0K Mtn3NqwKdBkBWLca0Icgycwb1Hg2oSz8W1GTrOox/lghcDf9PtybiPbq5mmeI6doLv+a+ilQowY+ r8EIbjp6JZKJm3gPsFYphm7DJ/LGxqmYYPsq7OObrVqeRr3hhv2fJ909COQGg4TzvDc+4EGTr864 4nrddBLFA6Zp6aEwr9r6F4fLWpvIZrqw6JlmxInlNYTi1FOQ69TLURaq/4sTZEvLsufnwy/G8QZH r48pVLEuKy5UgmBUVolKAAEZwn91s+EmY28qzwwrs5DSpxTsoyPB6DA2hIf1v2RXmws/vk728Qky F3ru7Jnan4VjDXP1Q+NACJpLkKstZTjUWMhQgPLCZwmi1JQUAJl3p9KzrC8pEm/rAD1CPUwkLqFU KmQ35mazc/xvBGckj3xrUGPclfQYQ0c/iDIFkSVcu43QKFd7X4q/rL5HmEo2jhOb5cChzZJ0/CPF dnnaOoLGz1pgShB5QnXlqXkhyc7Lxhdl7ZX/vQ6NKiQQavbkLT2lsRwKGvMDSJizVfeVPvWYPkUy 7xgV+rikiTFmYQjB26skVQmkkA1WNzQBqyd7ifmnMf9uMDTrhL+sW4sRzIvr+gDkqzxEM3f+t6Hw mb1yIJPRk1JRrlhIaoiC2Wcx9Vv52Fe1C1nvE6z48l0cLHLJrocwA+muivJel+zLQhdQW8uP4U37 GkdGFF6viAd2wQum4SvIBLEvPF8cYcL0sruTc3Y4w5F0rOwCHuv/1NmQ6UjOAIOwmNW4S75ymkk1 Z1q6Ws4+7E7nsYRHqMcQlchzTsF2IS5muP4/JfKZrbN+eIsD/Aqkjxqe1ajVPIQhZeZSVbaTILHl IqdoKN+XWSvTZT+WUnXckYHiAeEY56IJ9HIaPM46jtl5pySEOSpt0is3CDVtSWmfJcACQsUgs3T+ 4WglXlliNh3L2PL4ErXrXGE6xqVD1gPNIAP1fnZk7nISQlzIbJG3ZVhN5GH63ucihN3x/y/0nEt2 /wLiyemZHbvMp01IO0NrV7oWXXrng6FSXs3WC1qjic3zitaQxnqNoRrLqbQyzXWIJXru91nNDVep ABdM666UL3WuOZvoWC1abhm7cTsLJfWztdUzrSQ8dSePE1JYuyE2WyVdvKOd6+dQjOYUSbWoUeuv 6lVNFw4dlE1t/8vyFa/GUg3kQs2s2SNklWvgqMkYtvisxEKZeSE4sc7T4hTDNgB5FNdNffpkogET DKwJTF+rS4m7heJCzuSFisdKrML829iF30CBmtnodAhGf4dL4nQszka/+MBFgx8hZ/8JfQFuglow xfc9VpeaEWRwsaOpV1jAOGDo22VwM2xkx5qr5sOhLpYMky5c6MM7oXWy4FFkXGKueQYuS3tRARUD Mq33AQ5tcfBiVdot6urvyyAm7UdYsUX12nf0MrSNWtmvV2/7tsiEslpXoc8kHgK1k//DYphuahJW Wh5Ke+A/W+9e3tG3kQzKmf6jaIuVz2p3hVV9nsyD+AKL2SPGnoh/avrAf3XjXbpzmZpOXwnokApy VH0YhQ59XTx8yy4763Z7OCEQT2nIFTERoBuzb6W8eAgUFuqZwy5F0vwx3svu4JFCqZTb0Y1IlRtO b+lbOqxsv8BK0LqZ6rGDDNOcI5VVQ9R3HNewXz2Y+EZo9ePEzbqOWyvsOku1hV6QKR+b1Fmznkmc HDOHn3xjQEAonZ6/JCcqpoXY35Msi92pe1cBWM4Nj7ZkVfIhYEEkCY0gRBN9KtIRCgFmB+A2cdDX unmS94v77ueDSXgwrh1jtVwREbmQBkhNN9gUUoh96NzRWfNnlN8dNLWvtgHiH3J2LRKq/+qKeugW TpS1jk0a3Auv8pwPs2esucBu2J7tP7lABvH13n96ZcNFLxKtKZaTdtia8BcP+lXkFgfUTDmWPxHK bF7A9CXBsaPthI44Gf1RPfHyvA1oVGFyFTcBJcsmZ8r7Rzj57kt8h86bEEGkekAOYmh5af/kmrwf x+V87cVtlKppC1QSBJ/YAaVZekbJ97xOuZ+jEoGjepyVV+i6GRC9d3jQAWZ/wLCTlVRKdicqM8GC hB2RY3O4250MmIBSVhCS/a1MFSVWOdoXcUrUIumnA6s1bilmZNsjiyFqeypBu822wR8vqlEZ3eUW /2U81lSGQaI9seiC8f6OpTbF2dUY9OvnCyqO6oes2BjgoQpT1RZgLxpPKt3wI7MTbHK6mEgPEBdJ s+Zgxl4cJyWjmflLEg1az/kJ/dbl6JQllZRRxEGDKHvjK1LizcvqRM+X7+wViYd72BYYUAOegVs9 rx2e9z9b6zhXoY3g2b/EFqCfEsRTAu0ZCgd3hpOBAQKaSxCGjtvDEZTaDM0jZlrFlmt18SpLg023 KLrmUecW82VZXBhgUv07kKyWEvXE/hMp8CbcOMGVAZThAnCSnEQk6gF4M67ma/C5YQffxCpg5fpr sFbuIjGq5Kh662wM2hK1erxnZC+MY/teEVuDss1xuxoJArUyvSESQrRNEzP/y1xQi3ODqkmkRuwO a/+yimSAzUWvqvpX4hFqCB9gfYFqQjXopRhpGZPZ1p0ybJZmcIF0Pr8bWkDJIc8u3aQUALpAWa94 1RUjRDTNi0+C8CJ++BoqR5mUQJZXyJ3OXjrmslpXoceXDI0DgjIUrZkzVkDKqNAyPUtzoIDd8Kri izkvhOKTY+uf3EPGM0K5gMdY4byZMFf2Nloe1/zvsOPTyov7Jt7uAHvGY/xVSQLrXFmnFPsHT53w AEvKiApHtafN5jahEXwaP2Pj2l2dKyLbeMPpCAOuZLcszrY9M3iJxzQK5zVO+ipBJIN4F+WpmMXe xmulYyNE7tfn0XfJjepNLCDToOuCaaX4UiT8FnHbJmDrsUA2ZXiU9QYrk130+MryNhT+Ax5AqPFY Ib46vWHP1aDR5t/mULTkB9kmY/OdZMEOxWBNgnxtMSM2RG26RZFbRog3fv6tGB/wWSZ+vs6puw1w YxDG5d8bSYRoouMBklyg4cSIOSX0mlu0prxp+KMuRdcZszgsea12HuiXQjHTL2bITPhRbBQEQqYh G7CAKYH05rT31wCZnZ35r2YTMitVd81gDQIQpgs48H2w4/B7Kfy5vH2diWWgviynoB+lVD1BNqoF 0z66FhstnNcF/S7TL/jsfPIzQymGc3/FX39Nj+LQJoLemfs1K++t7bJvtTKzTsRJyUsaGkh7o1et HPPTtP20JglFJphpDEoZO4SbUHKNpE7Elwkcf46jgUfIwtS3Fpp0wAogefOL8vWn5WMx4KeMQLio uC5ZMJkFFWD5QzR3li9GpI5/LENLfUooTn5zNjVviapWa8GQcZH5xSe0NySS77svio36M49jyDM1 8wlhH3Nadr9WARM/CcrcViqx6jjAID4okPEeP2h7vQe7VwsUGF+QxNmaE1KBUHMSVxHTqy7ZHOw8 nrDvIP82paNHah+0E7Z4IuCW1VJKJdIPquJuATh0F8whb6fbBwXVystXlw9XaVAfotY7xqkujgPe sTjG+YyogfSbAs9TO0izi+Me3HcMg/201qyUI0u+KZVmEz6o1xPAKiQBS+R1Cmb7dEbWikStDZiO ok2yEZuuboJRubAx4bOmbFQOcQkv9tCie89+cNlK6siJz8tOpZad8/TZ04bqNiQcCIPcNABoEE4M kjqIsOPltWmGDOjPjXYENi+u1C2yU4Tv98Vg8vYa4d1b5rY1TtA00K+pdMSF+KgfTpFMapTId9xQ kLQ88ABUIKnZi3abSGBqMJx0sOACcPNcuaTXnsyvVeutABgsdbv69SOZAbh20Q2a7eliDKXtrpJm W5VZo4eTjZWNcgd0cb0ZTowwXHbD5fetRCbZAzpLYC+q9SfqgQ01BMmhqFVUC+fklQHX0gqw+yGt UPOMmjrQmFWYewS3jxroS/YebIiE9JzqT6AVv3v7K/pNOjsNvEdRPLAzLKJ4vcxj9oJU9cylENFt gnC/F4jokutWlhVt4y2GeYCaHEvnSCiSrZ3o8Frtn5CGx4x4ZZU81RX0qgDEWlTZmkyRTrXLSQgO n3Q3h7mu1Dmimd26b70e2hOrSU+pJKAxeSzEV+JKjgmskY238Ojg3PciPFHTeJe2FUVe3QSw9q6a Z//7C4JZeRQg3k1DW+q9kpziI5DJ19DoBYBjdQhfkxZi99lTcVXfyKujA/H6f+Jc3iLqvSXh8chb CMZo1hBKCtC7n1L/dRrV0LeIk4ud2LDM0v/M3lKWmD5Iw5jrcLRGYHXK88pNM2N15gxLC2L2gW6q CvJS+UmNccBt1k/cf0RMPxeYnIPHTGRogY6VWhfhskrtzDZOApsHH/Fi0TeWoiqM7gRsnHVTteZD D1wUEmuVYqFauL2113cKwEfsx3WRmqWNANioh0C7kbIAd+NkYDJUsRTE4eJO44TXtWQjk5TZU1ES ONIJXzCZqcDIoX1fV6a8Tp1q76I489ld2wAU+LtcY+gclceMcpi75cNazyZ3s9ub+6BeNPtlegF8 R9e+Dc+lMh4mU8DQY4H9sNTpcOuIRIQa3w1TQzV0eYBywlaJ1UEPGOYeg+lx94ljCzps/48xDx7e 0ETnrjy6yNjZkfvAnNepF+tCNpOwSSBSDWsCXsfPKgDorGdoMf+4p30Ni4n5TrX81+3nRn3iBXnV LC+es6tx6xdEVy1V2IOeIfQdML+zACzpRCOMef1fe6WxaGnlRnP9eRz4pOBdhUtgtz6fBpWNaAtq rv9uSZ5jqJzupRk8lyvX+mzEaxwn1DF4PNU80NCUjj4wvx8aTa1Xuy6xgV2eO4IZDECcjndZs/av xuCv6sY6iq5nSavpBZE+JRGVL+vrptMVPzqMDL2wRiKJWOLWEScJgG3F95Kgn/mL8DQQjfNZgF+A OIhNtvStvz2F4vkWQbWPlYt7UlCtfpT+2k7gQ38vRl4uBm8X3pSpirkG2AWvUh7H+1Wx4Oi4C4YR niiC/4K8RLZRzjz4715ol08ZhSZRwW/KyVbKXbZhx3PjwfiISRE+l2kS7cLtlVJYaJKixQWrQ/vf fulbCsao2WM9cGy3kOtJlt5yJfTHFNx98j6Qp/TIBe/ubGxvhqEC63o/hjATDKEsmEh3OdDuq7gC RkZoMAh+BJcGxDNgzJxNFoC4ngcfTJYTSuJUreOBqrodAd2/I7NdX+eOEbX6xygTbl5RR1rl+GUM sDhTmBXiEUOqPdZBaXJa2rpMTRPJ7biVZDcRUnbIgN9G4PUdAxem2ck9M/OuBJ00gGWgYo9fyR8s 5Iw2YPn+1iuGtVgwVcXvE5n/gsHKxpFagdXqdUFzthwJ7GUIf+to+pU6ddSigvG4ANUIBgFuTBre T++GjuZ/Z/ObhWqTRUbLCVyX3PHKJb1OJ2aMeB/nDsOJ7YIaw5gisQiI/uCu2vo2ish0KrjSnGY1 BetgQDvHRUYhyGSYgBI10o95G3I+4rVlVWfR72/Rmf7wVh+D694r/A1NrsvxEaaSjBtDQ9+E5y+O pyf4Jy47P+4rx7JoIlQtXw2S0XFyx1xhGJYKVoYrf6IoSU+hXbyf/ycglOS1LC5oldNE5C4KwC7y ToBAyj1H5xqcjj5rW4ZeYcz8d0wVbLoHac7JzkcCykvRa6qtFT+LSRup00W/6JIOEiSgoiJo9Kme GfnhzQjX9jWqIz58oeuDmrxza3hE7eQZL7tAEwC+UoPtE6ugYNBrgL5IkpDBfwGkFceOu5stpaQk SHF1N6ig0o+L17PdVCwQzqf+a/lUzxubE/CWx6mzqchA2ZaRa+Sz+IzDxqUrnxhC2ZRn3KyFM6nb JrJflh2nXWiG4q/0NDkSJSkFdu7eQ/2Ow93/oknyLyRjmsBEpMSR3uC45USSJCJZyjyJ1jkhlbPk W7U06/5SlppbOzRK9Q2k2HHP7ZffTrXY3WDKAcBfQZDrsmzZkmNwjBz++2jzNfMW0trDwaKGTIkB qUX3cvJl4uDBMlZoKFBZko2DEe7An90bryOIUQ/kPLt3toli88uhvHgDbFT5xztR45j7dX7S3LPE eetOWTnJVKG0NsUnT4VeIAh2XLE5yWjcNg/wwrcYDnJD1Bk97VH6OONPofP4qEJNQ9c6uv5aTHvs VtkrlYmewLxAz42I2cN/o/v4/ckeivGmQZ7aGbicExKWCKx9Y7dJxamvclIEiXmTsJmV0CIaPSlk HpZOm4wzBTQ7DNfNmvETO12/lDojnklh6GL0yQhjAempr8mu0K1GVSWOdZz2jiCGxmDCLo9PgCL2 OQFg+CUszz5BZTC3/Ll+YxHzo3EqWMR/uc0WMQxfcFrWK9rrGyswGb+8PLzm8dKiMW1py7p7b1vy A1Avq1/7tE9nkAHr2pTPZtc+Qc6PKfmimmmi7zHlqo/TwVJ0vlHdO0aXqR/gnxIJYdsN54LZ1010 uvXP7PE4uLgweSjBlM6jRuC5WJlGAF1wSAcJv+SlzxLv4peBoj1z3enxNQRKcIKLMb4INp1c6nnI Q/VYXUkUf5lF31Dia6U68aMX92vUJ/AthIw8kLS7VZ0IeMeYN0jqIqcecmS57n0mn7XrrarqdX0a YvVlH9fWpa0YWS5q8PINTyvv0mDuI894JChI/on3EPc/23u0Lkxak1Bd1+MA+C/ppsHpUr3Yqvzp EfYme7qSB8sOSqqat3OUrP2TGQ1D2j/0uTUpJnHj7enUSaJIdlBH0PrH9a11+N2v1rOwts3bVSbB FNBKfsrF9NZVrlFj+mq+LzQ0/bODQC1gOoFCyIlKL8WBC/SLYsZ1OPkHqrf2Ty3NRThk3i0s/Gqh n74WlGeYCSl8aFsMWA5QGJS1nakeEqfurPcfbKLQEqoi5ynU4qzWsu9Z7+6HM+r8oBb2B9+K1OO/ yJG4o0GvPcr5KFlm9FI/sWwRp+KcTfL8H1t9SBGwQ+aSEcK4n+Z3S9RfZn48DmANHc7Qaf7igT5B kPFmZgbaSQeFA64TmDrVAPcVsGktmEflhAo/ZwEVMyviGJ45Vjoks0DqBG3yyHK4Yi7RZndajfGx K+IrzGSndjnJ83525uGc5HUE2BZkzsQTWEgqoD61/Hs7bfU+Iv0xs//eVNeAJ1ZdwpuHlj5YTsoH zSYpcPeFw8Mzh187RsupAfDuP74nKsTw4nfA1iwU6FDzBEqG9DFJ52vxprQ7KYqFbeI5EO1oHc50 5ovGDL0Ou3Ge8bNrRQrVvT039nnUzwXPXX7af3NUVjJz7sryjawePeYVY7SPEEkigMeU42tu41L2 0EdhyoCwMtTA5Lnewc5vP2+7nN2hHzmECY4fpiF0nQnBnrXKJT03BoRrDvAYRjY92XNZ0Astgemm vmp7uBrOP9d16Z2utYkb2NSJh63ub7HH54X2btOZ2wzJsvCwSO98ByqYb+ExVIAub7drElLHso7Q m1bhvIp72gVtb1JMHBaZknIxIsot3f6PFIA5lbXZ5F08SPRYtgDFwXYgi4L9yPZVAPmltRj+mz3/ tx69DcVpAtpVWFf1tbeSMTK3TeNLBPEaNlhv4kJ/+H9JkZOS95YzXDmJl7/5SzqgmQULOWi2jZ/z vSqF3SABvegxU16YwC/4AwRhy1MJlxYK93LfQfWHNZ4Ur0ewhK/1oofuwsQebP8Rt1yKxZqwQB5s hb2Izrx6wJAPIGMGkCIxapqMgSdGwYDQtBQ3V1KQICltGjaoEqZad6CJ/P+ScXjWojkCkHcUknQt KUdRWC4Zoz1STY/lTiNsqqACPGLVe77xrrkyPm8bzZI779NegILw8+3xb6MB+ek71obkaQ1PxLoS pIo/JyWCmrQGOpzM0y9A3OjjTlmxMfzIbZweb5U5FwNe7/bixQLFYCJ6P3ZfYlbd3T9ToHVGTzwx HNEy+CAA+Hs4qU45Edoj2AUNCFueor2nffcq0tX2EJa6hu0m2bEodK+XQlQjGrb4rKWfBDCVQoVV VaTd9SmVBowpFHqMyJISvPLYPmvxPKCNjUh2A29vOhS649kmQ/4jpAHxm4QaA75CraB4ugvoADDM aF7UAHFK1s8leef6/nvw/IhwCm80KuK/+lwkFBLmU/U4XBtycOqY2XqAzBSdm/pES1p/YFnSWPkg vKbyT+BymUifsYn9kbjEGrQB9idpHb6GMqoWtSkNmH+dVMVxoDyXq+ovlUuN/Iupi+vpKOFcFull Hm/deQ3SSehaPEMeGCy74SjOwBjfripQlqpddD+l56wkjlNXlmUmAEoExGK2CtUbNSRzbmYePy6W rBeiTvOhqfeluUkHItL6m48pgOxIABBMhT3umsLxGFgDayGdaKkTFtZsJBnT/R3dP2RvBwLGYF2J sClwD5PI+BoVTNlBe2IGeW5iC1QBRHg53uAUDnFUeNBJr0MLpmxGA9PER0YRMedxjngoRTZUZUxO 4rdsSUzYasPpdbj4FZ19nzX8iJpW1IZTBTLEuuoMlFadE339QqrZDbMs/SGbIQe+CZ26FaVw1rF3 XsrV9HjGmpPUcgx/Ki41Vxlrb6bVblJ5BqBgZoU5yDkQmmTxJSAAZvFuoqlN417LZwynVhdUuK0I oaMQNCmW0Wo5ru/YO+Qc0EG1nqH9YbbRAstqx2DzDdNoEiQoFGRH1+yFzafYDIoNyGjz73Y2d/t3 K1x2dLWZYoe7WQD4BVEsbxAUTm0pnGQWVnM0radPuUywbqiVtj7MXq8SXWGX2bEmlC2bauN1y35h RbqXG/EQ4KDnxRRh36xnxp0CFDEUltskD4Ns/pMJpqIZaQ/mcIz6s7OiKLmIznWF3BW6Qj69kE5V zjPKlrPOgOtciWjODcLkFoQHywwv+bzj1yFD268u6ugkXat9O5UZ/vLEKbXy5MI6ga82rciYCGHC YgiK2uo4F2NhWoN5jXKlJR0vIkoEPmVNJ0icrldhueb43V0k4JdyqU8O6TULoaMCwWt/KtyXa1a8 7Dc6MhylL7+9sCm6Bz7uGAr9WSgqQZVPB7alguvFCeqBi9t3cXMeNZiXH5u7zkyvEi9fRQi5ijzJ Iyhn/+NbMAF7fL8jV6fbsBXO/ehEZnpW02Ct9QuXULLHW1D511od7Dib0MLqqKJp59IAaWXKApK/ P9uOfJlIgUav2LdbDfFhC5MGGvODhcCzmumRYYIlU1KMpJQ0oGjP0PWMHfL7sUNi0pMIK3oCrZil riX6D496s1Zf3r2uvoQRrAHya8i//Ry9PjnrzTKvRDsWWbbpEMIqGuKwiJG2fzCnRs6GYBbiADZV wwUIxznYMTfxioXibclcy+dKVAzl941SQiNYOtFSpH1sNkLog/GskP5lR3t0sQQ2T6C2ZtWc4Y9Q zhFCRImpzcuhLsInoH6S8J6OQkKZtP6gCtHNIc45iuJWj0p4hYH0gSnPBL4BCPmKKF4sxBiLXYJ/ vYKVMxD+n0AYPL41aanmJjKfkEgnwpMJf9Fzsg1UlcwveUYMOzu2m/BI1Kus5zh/FRSVCHtAKpBE Ilv8A5MNotPvp+tanvTJPcBn8Nhuf7mCPaMg5n5AseyXZPJiThhmyFty0aEbtEVf2d/+dwbrWvJS oLgfgGueO+6LWGrbVSE28VlzHsiD73Dd64RMT/X7p11JitOrBV0c1urV1Bh8ewwF+HERY/nvi24g KdbuuauUAXhpWL1nWYFmQipkmrv/cGQxQqQYJw0mCfEAMwUFIMdaoxbr0dFbIq7d8nyg440rzvkt qF5J+GI6H4lzu312pW9YS27G+If/AxdajalxYP64VSNHwFvYtIKGb2FUHqflruyA/URrB/tht6sN kbxeJHEJgSrE8CfK7Q9q3J0kAijMNmxMCd/4VOFav22eRFtvR0E59S5K8TsrQiYiWuKSPM4tC1a2 eFMWfXE61itEgZmaB1lDjBWOQMW/iNLqclXzFxHpljFOfl3U5krOioFxwsYJAwgygaSzYXNTD7wO 0c9djsaJGUrf3STDXmhP65gmlov47CZTbx+fyhJgX0l7ORDfy8aNLs4g/5v//5HmKcvyo6FNqzy0 JJrdRbNXcgx2DT0+So0KidF3VcI8WLIn2aK+c6kzIfIVgYXW6JlW1AMHSgMLnQsZAk+1s235paSM ppqY23fKrmcOvlDZ8p1IlH9FjkJ/p79SO4ith3gFegNUTp0o08ZaiYh9m5Z7wOl++m9rcwn0f+tJ GaYAqHJAAZLBsWQXsyD4lhu3iu6RmLP6ilQO15GhoaF615laZcIQqGEBEQBEJDi/OdTyhD+fLgTF eu83qwnvE9QT52LH8dDbIYFkAjrWxlsGC2F2x0zuQI2BQyjHNjSsLpYIqIXnuHIggkSvGIHJWe8Y vRB72AMp7/IvMzEeMAa5SmrjQDk+TEQz260bM+kwbMrRHNaLHb42vgN0P6rm0YPOkXAehCxsj1Jo opRyexFmcfQzNVb1If7cwa+3lavjMACtdWHeD5/WneyQv5kfb6lUWBnpFNpSSDAHLn8N3AKau/k/ bKUGI5pto4jzjr2tzBsFssFDe7qSQ9S+2IpMYpJ99IIxMkyeXurZIxn6UzCkW4hQLNBRz25DD17d 3QwpkOYVihsqVjkKm4fhoHI+qMr7hZ5OCIm3z6MwrJ7XPI8aXliNxZJqkGjj/Ao9vbKSPM70lKMl 2vy1uYz73rGR/X/LOq0gZPGqw7QFPLqNV1R4tl3RNv2ZjWayNuJPQ85omHdIQFdHIbSTBVRLB46R 4VeYc6cWXdt6OPNdvL2inW9djfX63mtO9j/zn0r6z+QC81hIfwaXzfoyfLvuX8xzvGKd3ut9Vlvu AN1raXgMzIzjvsTwU7IUApKrgnv1K/jNj02yWHxJCunwq4jYbo9Cpi6kLTCyX/JJRBnAUW1jILsJ klcKbZsavLXtFd9FGKF5+vMQaX9kLBsH+F22mpsKv4ygj1mXOwm/eeCYMtYQGx8gzfycfeNtAiUL QrdY+uD/Qt3vgGfF+iMD4MXcumQatWSCjecccxrQ+ZYHqWkNcaWQfKYIpQjSrIK9y+4zPxaUzxmc JYIAQosgvM0Sw6Sh2l/rtx4vqR/WQhXZe3J6VdXbCwoiyYZfOlSNmTusLxd45e51Pfb0WmlzpOFN hUk3yqDqJHvQlhDsb/68Po/FkJJaZSfuoNkevFs9L+7WWNCua9rD25XLsyNCxk4A+VsrWXHt3Kbm J9mY4lgO+TVXBSIjqW/CAuMKWpgq7093TAoXRrN/gNvO/MdgDUmw72m7lrKJubgx35Rg4BvrClo7 Hjmx5zJLbMufLRNID9jKcvHpoa8cG89HHU046nc7sgNCT64xx79F6U/v8VNLhDnxofOXgDXPcbCH fsiO5JX7LtZ2+deje9V8kvcmrR3tCKnocVfOgdKKmEMK01yp1LqeDB3hEEPKZ2n2sYqFPWz3NmNg lyt3p8CtyQfJjBqMTawHFXzlLi5TtZydYoqnMXfDEDaIdGnd25h0PyvQXe7lBb85etVerRT5AN88 IIGr7QlYhl1nZsxJRaEl+dm+Md9k1oHs3jlmOTLIKJ7Viyuc0rgBhetPqubFwzEHSrRguepcL9SN 0gqIv44izGS4+1Pa78cRfExeN6XkimhD6G8/0urRd5sR2cG2zkjnhtdWoU01C6sL1fW/mdvxZFEN NWkmA99NPETawdKCkq+a5rYjw8Tld7g0Z0Fz+kzdQDLkyfKrbuW7Vvqkq8gTSO4E+UJd0H/mFj9E gdNS/glU5pIveaRiXo0r2qvHVxzIG193jduct9GJPbDxAxC3d9Xiy9+x8pNhxcNWESLv48Je2a33 z+MUqPrLVy1Bqb8bkLi9w/72QP9W3zxiRrnXKo7hUnI9gaViT2AHIBURx65pga/phX8le6VAO99n V6ZThH4chyxhFSMZutZSzPM8GQO+hwTIQmFJyeFb+tiu9Y+owYJrF1I3i0sMolUArz+mwqii+p72 d6MYrtBrQJU3AjvegyEmU93nSHPv7br2CvKle83fnaZem04z8SAw0QzRwNqV/GsxHrU2zBwrFWjT syYL56G4VVxCRBYM4KjJtEhW90YeJNZUGN3U+eB+VtIsbWKgcQBOoQy9d3pRHen3XDAmlB0l66Ob C5JJKeThZpKu7XvWJPD/KBQBLC3E6ApT0aSY1rGpr9CIi+BUMZJB0WWqajf8BVZTJi1fiGEMOhKJ i3H0krEj3LmJJ5mpOjwVxa4/LmnFGDfMfJjfzwiXX/c7eXAoAiY6/4nFrcCOSlYh20Yhr5KEv9fh /Z6O++9vytw+wxHFsg9+R3po+3DjuWZ8t3lvAduaYjnCMu0USV7iqzgZ/0Jvnu1JeTWA7I7ArW7K XVaw3j08JD7vfivIybwxHSDklKklOWhFh4Ynen0J+CpEp9KnKVkUpJpPnzpWkgYaSa8LmDWOAaNw ZS8GLlch29RHPk8haO++uby2WIFolY/PxyFdaW+40mKqfKsRhkJ4LxeTAQUo8/O3uxpkRjhoiXUr rLagVpPsfXBdn6mUXxMuLPCFzRlXjpLcXHUhfMEn6KQwCBqnhRvz1dzz9yjU525OD58MFyFyG0C4 jyyux+xoNEzF37BzLsV26SL9mpx0nf/X1ZuzkWUPTppc3e17pdVlP4nb1XenKVLD+wuBpvi7rz3f TRaihBVZmTAV87+P1nW2wKDEzWaGNaHj5Y7fCrQALGa+Fc7gDWkkkGZBGSAzXXCX8TmMaQLkzD+k y7F9rks0AVmLwE6n2FaGdbKIMD9LmtigR9RwgQCMyh6c6WvD1AiE12AI0CgkdNb+OPS1wCOPPOSd LqSpkO/NS+9ICLBY06nvcde9cUplcbVcysVU/nQvIUt8QXeiVQzNyZfOdvNlh0zYRKZenBb6nD2s y/45PL0eCLyIMgcjU73K8OVW13nWQgNYxPakUiuRDKS7BbXAan/cFBRFq4/5GfPPN5QtxLiJrKw2 RvqhdQUmVe5/y2LXarnxi21CIhlGXVRNd+O4bgnrV/Ug6t2PyUBjAu8a3zcnFPphiRFj7wYEbQ2/ /Iil55T8EYBzMK4b6xgJqH6+wnF1mjSCyU4m1f1OTENDQ4nwOeVKeUS5fRA3IHfukRTSWFGFjaY3 nP6YYJgW7qvCgLs9PWWEdv0v4LeiIW9WSTRiBKYfgWrJwyD6T+shXd5Dn0pJZ7WS/3jj9emtUtVA IMvIjt2ex7FnNQ//z2Y2017qL6Zky/lcq8RpRd1vBxsKQ++sTtk0gzGrXusTEKjOtjNlz+Q9c2Xh ksPi3OfBu/b0IodAkInkRq8VuVeI0AAPGIN8Kp2F22oHJOtA1SM6DMOzmRBrqvS73IyYEEGW53Zk gBtpSfGZqIxsd6MiAR4Jh8GwdetIIazk8sPyyNgPvX2LDBmd9GW2GWRAO0mMCvkGw4OKmGuOjsYZ T6TCHUIO/F8vZA4W8McuQE8c9XZYY5uq2qn8fb7E5ufUB71m7cqRuCXrOQpM8kiEXpRivZ3E0BqU 6ZGWdmInn+yEL/chgYPgoS/zCtwhfk6Z8oSETexlxAaFajKW7aaarI+An9QemjlI2unKaAuf9R9Q jzu3QETfQu1qJgedL61HGS5ALBUyAw5J1h5GQstVssY4P2WufgpVtCflSIaBrtRSPL8r8Anh31dx WOBoq4xAMMJxXBqwoFwpGT5UKlwPs3F7j/OxMJ4tA9UhTl6aotCw53m0Mn3nu6hmNq7RWWnN8nvl A70wn9l/YJkeo26P+bHostjbZsPvnavo4jJSRY8WDUnT87gPS6T6N6W+mvDWLZ21QotF4ZJKpuSu ukNuPEl6GCob21V9M0M/5zvfrEPrTBIhU50Wpv5/RmPPR+X51olCBV2pR6kHCANduFwLqtzMLG5C YyzR13NWreDnCWFvOlnGVbHK/4qQzHg++W/3csSfHziqud1xl9jFsUdV+pa4GRk+FFUrZfFC0DEK 1rXNFSlaYZLU/4zPDQx4G9GTXEGf0yAXcWcizi2XAxQYDK8bVQtFoQoLXHOXvPBSEt/64f2IYNms 4GViOCc8R6ICy+pyoQcFX7EAtlVB7vXHXacx8hA2XeP/F0X8fFgBCIS6mAj+4GVzNuwzKLhFpaUp jLpbkHQ78Xu5fHZzsI9wxhh1C1sL/ylYnUp5P58RMlNRa0GXCFuh6rekL8uKRtGRQWv67b4do3Fk n8WPB1HAohje9l8yEcotE2dEYZlYpIK3lkDhG/P5gbbF0Gpi5zjD7kiYhgOxdL6JnvvROOzzi1eV pQEHPqjw3YzIDyjOx6M+QRtx6g8f47OhDZCZLmQDmsduMbawTW7y8yO07ky0NjGoc9nnxo8wJYd+ +oqPOeQBgsBjSnw+dbky0XOnQO86pa8Xs18OCYjwQlYBgaRP+H1P2vHlMWmGSYOvhduxnQgKf7q5 JKpivWVg/YdJOizVAqJW0bFg4kqWV2MBUAUYnlST4HUjz84q25SbNZsYWp+OFv91TvFXTsmmgbjZ 96E3NYCn86iVaaFQcup+s2PKmzYuLZdIT4nDtDocYJcUGTjIbVovfn5MAG9RO3Av3cKfbqHpxf9P +XEsv3RhdfVIW+JdjCCCPsefjQelBCWO72MGqanvs8ANAvE+iKDufzFBXya8e2c1rZaMznx9eM9h gIgwPS+rVO0O6OuIIwnmt3vloigs9ILvX6bvKxTA70P4PnGhEYQ/NBgk1JzCevwZNNesXW++RLf2 KbTPdvgcGPwfaUX1pdmfzdS6dqLpsgB+nQo9xLHHEnL9NLssmHbVnASNYuGJBT7z95og1fXZwvhv d59D6Wne5BMRcFPHnAlzkCf4wTdcNsmiM+kwmFQ2oANHk9cuyw/1D03NLxQsQX1sUQS/+2W8shKu MGur2Wgqssn6Roa2iemoRZD67xNL7EDmNs7YLKP06jnsw53Y3kz6i0nt6NkTD/qIWyPmyZS8caEg sd/QBIrVaoHiimrNkiImBABibeAV8WzKiTNyT3VyBJ2EI7sk3U7Py9LvzDVb3/e5Mf6AOgFaD12B o9PAwVi18Qy4o87UB77VTD455FdYVo0kbv9M4cEbv4l5MlJxCFtyHK9+ZbySyovekHk6UAQ/tnvV Ezpq9FJou9XSHolGgUzcV0kawvqzuXtYzNUQ7uXJYrSy8CxulloiR3Q2wQLbmlAhoPA68XzOWCUS 6svFaMRHQ6HmUpF/mm0iRY+bLH3/tuQiYJawQsArzlzrHG0P1RNM5dC4I6aLF06BKmaIoz6ZtnTS /S8XtqIsB0EoJi0CMfEVSIe/XD8RLbyBvhfY5boQ4ccxl9xEcYowH7ZvoXxNYamsxAXsQukVyuvc yCYCZftek1PqGYy9pb9cfwypUGCAK7DZIZDV3jAvaXOAonxSZH4rUqJjJhpUEhL0OWhIWe1phtpE Bog9sLFqNK226EPiNO9BjfNInqiUw+n0Y+CD1zWaZmGZWE0ncjcr8sMYQm2HkRY/IdM2ffG3WUG6 o13cjqD5dbRDvGa04qYe8j+j/VxC2ulW2J5ECwgwpY3z2jgVrhSte4XtHMyn6hIk+YqnQCOlM1Hs 6EI8Ko1rQPzAyssmBnhhY4NdzbpHiOndf7WbjMgdAAcE97fdEsafVfShUtc+qhOg7pbtgt2p7oCg LQxDWzd5a9GlUi0g4iwNhFBDfAMtKGhZ6mkpt4zVthB+ZKwPZ65v2BeVH4GMMwiJgvTY608yDpb7 M6FCZIFowU0ext38Gah5iZw5sNwo45Zrnd6a6w/bbIH54CndUeDRs2jqH0u5ClkEi/86XXYy6gmI +Blehhzlqy8lPCWXNA7vDLHj0YrH8qO3Jra80fXlEeN9J8NIhkDVpiYdIOR1nAhiyEJ28HFHtb36 CY3rb9NnSlVkRsDh3TpWONUqDWT56BS9I6DixWIIHD8ASyhWKiQ5VSshyYjGm1XVWwZsdIF/ObjS mjrdXOYZ1R/zIqe+VhJdOWIb+i16RaOPtyEhfzXupGyamM96vSBE0aDE0HLIr+pD6abUxDOja9hD 7/yC/0soG0GO+kcjUd03dg85AH7ScUXhtt0fbcb8FPwuQmMqwe8gfyrIVyvk4wJrncgFN4QUUdec OSn4zQmHPNUfslPEvEWGqN1MlNEn02XVe5CQ7BozjCJFaJhIfoCwng6XyjWNRDZbkON5UV+iLVxl aZ5BDSttkhY5S6p1nDUBbfBvfmi7O0HX41NsLmlY2AOwJgddyppep9unUKiAAON7OoXM4KJJ6Abj 6S3GWQVrrngi97gEcalFB8otDxWzyKD/nH0rjskXJ0WeE6swhH+WrwGscKBoOrsH9j1siE4MWPXL dIEqLtxSjxO3KZj0RyDIzp7Vo32FkcBEk/dTBuxbhkNF5/sUJP+KpzRl26EVAz0ews1fBobqIuME 3UDgKet8U+h6Tk5G2ZLlvDhPbEgkd4ZtdyBCJ5Icqfb2dC+mZKqheaeQNNp8eA/AY2PytdCfvwSh 5GYvBMmWpt03UAoZIDAsAc+9h7rLFx62cMQj6IlopDZlsTleqsrK3giAVSSUE2gNQWPJAwLBcyGd X/rCk7npvbjejgTqMHb6+Q/8jcUuREBBj+f+4uLHtB5+wWmYHhIfR094Wsh5+chahlNBUsgBdMOG omHdMsv0lfsiwjTk2cj9J2UDNgFBKBJLyKE8bMqZh4Hd28ntQtRc7nVMs6ntKazmmWn6IGqiEU1n JKgDFW78pd+9Pjcne4udA50jpqxh7sjYYnOdGucpe9etOcDUJe85MmaOYSbB6rloKc9fhLs4c4A8 eFlSz6cp5jSMjI7CyTicx0NMMwGuZNbikRGhI+L93yGlvCq/mBU4I4PrJUBYcmQy8ShHRryvQXxw g5vqyMa+6ycw1fQ5UkzJp8c4Beg3zs69HL7X1cB4yAXI/QPCAuH5elmzqx95knNuxtuTXkarL5vE aHA5FZzkgB0FYxZkm8T6qHsMvX6JlP5HH2JQPUTPniGx73JffLPG7R6O9vCYtkDRM5WCK+5iyZA0 6MjTYr04d2VWTaWNNV/Ws27o+y0Q1edX44gZYKRAmqoWNHQH5c/t7NfWR3tT+pdTbEaHGsIliOxr Cw+374QsS8RrZ6tWolL+5AYOZ14t1mQ2QRzwEtsxzGjVGRtmLOGm3PsSeso9dFymcfkJCx4t1Jjm JIXU5tcSR6MbON4mXVWGGlam6uv+4Swfej0DXF+5PeNQYFFpQKiYpL3xXK3ZHnbgdtERWI62rE3Y XK042KcaGeCI8hfzObcB/LCT+eTlxJtUK7n1n+Xx9X14DcgJZHWm+fVFuVE2iNBJBAZurSTABYJS V1Ceqf2bbmHr96iSl13JJgyVumMGqtEkEV33aq8ShQeEPFmf3GPwdG7roeTj+2g++L6g38MNaYW7 AcrMI0aL5/nRv5/c00WD6yNkNHJjTU5QSu6HRXkN2CR8gwCoRXYkG7+2/ImX6DvL0ETKhA47SVD2 mTlHyGqSchuqiixGu6HkEVAPxK/poiFd+yFeFzHJP3gR3Kud8CSVNxwbv7i9vlY1ULOrh0j+ZJ3I 84FTjBClmMkxgpcuFoPImUQidLsw6XoZv+u4UcQ0JqB3mgvyCts1h2sQ1SuJb8CKGIYFTZssAYQU gcRYn5qJbv5m2oZJjIFbt1/zRTWtFTAgQ2/D6sfiI4CLa2sv406fBoLN7wP+lzMn/tEgd4iYxdvX y16enQuzD21CtzoU+4J4oqelNz3HpbPj83DH7NYj7ilgJGpGNl65xYp3fggD7GHdWpm+1N0adU2y dox288J0s4XzJ+nzK/N2Qm8hckJ3Ol5sOsByaZQdwr6xWsk56BVLOSGoceHqzE9F1BwYKUbVgdOX 7X/fPz94iuFexjcpBRIO6rWFPUGp8WDnJ1fj0plZZTDVoW9ely/5INQsxcNr8MRqj8Jzt2fuzuRW qNamPU6oeKdKtqch3icG2mA+4UR5ujJ3TWnqd4X+s0mglJq6Ybl5U1qneJQTVFfCafy6DaOEgc6x 2g5jmA7qTTgLcaoBZVgw4BhGMtaLFijs8i1wi2/m5qIX1PJEpZdypwAW9JheLFtQl7EYmY3hBWuh CpgaH+2ZtDC4+91/JnJ3ZgDDm90yvVxHPL0L/HKS/hhocVltAJeU3jocMLnPD87NUBv/+QJltmvU +Q4NSuYFk8mR7HmbSrcwzzCtx3JbFbADcTaATqRGEbWjvPT+I8rApF5PEoEWNse6HR01k1dGX8DJ PBPQ4srcoU4C7unCLnus118oe59+xUu1923dQiL1MS6LRKbvt1DZLVThWhDZOvaFLFeDUKJfVPrP UL/W30ks2Lu5//vot8WBGycic/zZJDz3wvmUf+kyelBa8lTLIX+SLaFiUJvpZJD47X8lXuRJdkIi K848Ot6TdYJbBGe1/7Fogh56hVxBbxi7xKpIkv8pXS9eekfP2DfcQykJGEhLFYeyWrNF4/BtWNtk IONO80MBE+3I/metflLZlbcTAZHJV0TTLCgtM7hnQX/l30BOSfc49u+5BHjBzJ32P6Qw3mlqmYPb cHpFjlegx9AXvPq/MwZnyV2oDZQr5cNaPKCX4zNabjA5FartNIDjtIbgqA0Vkjg84omfV53dVBoO QJWkVV2/h+x1Oy97OWcNsK0Lk41oJy7n2lKpLpF+u0dkJi1iulGDSc+RiIIKM1JhotX8lpp/C0ei h1kgCuMLg1xg7/DzE2U6Chy3O5X9xfs6jGyYtehdxFdD+6jC5QPyGG79xXt15jski37XPdiPYQGv x6FLvrdcBvu1MXLn2rttdef3l6YHWzfu71y0DiHCouyxEDmfXEneD0rP5XeVulglpDKaHO1KbRD2 WsxPdLs9rovXfFQjjXMpU4Py8DkmFeXXJH2bihMmdd+4QnckV74Bg2UgD6Z4CrTJi19nTKtlcs6a jgUtk3rSYGSZr39IJUqxC1mvopA+zFDo1j85jWeQvYHCqqSTS8x/o+GmfESURMLFNjyhVOXAFCPB 0U9UeqyKZXjNozsIJ237q81ibxXBGUOXNfQ+KOqsWvTFpPRTnZ/x20yf4zrhqdN34ihjb/rMZBoG c8jS9GVb/4TnmaJJAZJmIoyLAdqZPmxT0h7fGfYeMVbuQLm+vQMKOYmPwSDgUnjRJ8wN+kofWoC1 ewTahu7cr4Eak9/sUd54bwbzW7FdJEEHBSxO0iEJUXlm0Px+EDJokc+SkJixcedG+fUjskvMX+z8 D+TlgqdArOKzPuwzMaW80FpdS6BRMviOiXdPrv75VGoTY/vWAqMMP/l4FaMekxhXaJ/lCjG7DYiQ LBQ7T14KjpqjvPkcnb7x/cqQ7Q3QqCuZi7MDdRDZ5tVIJB6/RgBP/BECOhmxJjxTP3n1k1WhjhLD NmD5uXdNOJGJ6re0HrkdoyrtW92dJ7vXnjwQEpcJgQY9env9JqfLFvvboSKofvj5h6PkPYSbpO/+ iRpJU+v8X86FVU7XGWE8CojVPBGpTPc4YOKu37Rr1lcT7geHQZnOSg5rIcmxROLRl5fu5U0jPqCl zx1OvHq9AgUQKJZgs8LuiByWfWT8VdMoUx+TMrGFDWXtg4yhf5tk4YuOUiXcyDqrEG4TNATL0Xju wIa2lmpE5uqVkwm3Z9hvjuhMWr49LJ5q4djKVaOdI/a0ene/TfZuViYcPruhC/3j4hFIglhccZnG dfIIHww5wC+h6u9k9cYBS/LWb5LMcDzHniLyv8BR5nKKhpA/XMDnXV1KQGBXrN3jhux8CcdabAga c2nHmNAogcWsF3WoLuVwXrUPxaKWj8fffOnayWEc3srnBnyLHRHSxqPRxr7nsBXvC63r0RzG9hrX 0wofIq2QBPimTb1OZQvGtNm50X8eDHjmVuGNI7d6T9ie7CYmTr14+pnz6FfF/iZfJRkPEUJERLVL l5SRdpW9GZWPOsNGH1q6sL3UIRQYXs1/gaHwpt+TfIMNw4x/2ZitlhVTVrYWkbUtQkP5R3PdPNFA PbTs2+h4jLRo5Y+9teIL8dLADWhn7Q6x89wu02zSCqM59phPs+FJwQAU44ZhBJ1gIlp5OseVuFHX 9cZhOiMZRsMX+/AgmBIzT8I//eRzi2AXlT0kp23FLHJV++B9hmIIBtgauAXc8XSdfNZJBa4bvr9K LyZyukkH9miLfoIsxFoabkhvu1jI5skATADDlKhhG5BFVPFHmc7mAnw5mQtWGFznpUZ+PcBC6/P1 Ed8CPmbgVAl+UrGPcnnsQCBkz6xdqa3CuEUK2SDf22UbkKm2BgV00K3TcA2BuShGMOo33TxmKPyV o2FkgV41RfsLF3ajNRBwASj0Btl3q6frp66f5frkGGQQDqaXaPj+aM7yNR+tDQaEfij1oog8Arbl yULmPFh+2WQmfXct4+MXPp6S+2wgZ6ZkfSoO7ucY6tX7uhOprVqXTG9RnnRWa5c9fbtBa2KzgXyH 55HnCK06GbISXfZoglDGUnn13pxIE9m18lS+6RMQ4wMBwEL0Igdn3bEQeW4C7GfFg7MXSvYEDh/C wIqqBry7oGvuxUyZS4nEqYO6IWhhya6CGzgiUn2VAcD/ec8rWrIzJQN7pC9uNZ9KjKyLN5weKwVp lDd1Ywopk78uC4rs65oqaUpjoh188sRqYIFI6Z7VEyn7u4iixrazNj7HihjoZEYuPjGGVKSa8d0u 2F39zooadtz7mBeIa8D5xbK211E/nTFDFDqbgA2mmvUMFmB8nusC5evAJHb7q459frldiO9hUOm1 xvKTGaI3+vMXl5JQOZO2zjWCv2382N1eOyTzmZoJ6DxCbMufRXTq+/fgP++xeEBXjpnZYWM+470G vH8iG4KlSyrjg6DlUZfSE142OyYiHtgXeFpsBbMyXfIKKYWYt1mB5FkBryVxDE+SBlf+7RSr3bqq XAB+BRuGcVWCWjKUrEJLn9D3RibRMiRX/H8ff3AOUawPZWtZj5r+bdTJU+aJ9mUfNtO1Rilz2FbU V7/p/CaYzc/GSFzEIFzvwzCPfSZh2KHta+OQ63a7290xuF6HQv+tO0K0AdOtAsGulkeO1LgtULqP 8RWQ146z13SPU7Y7m+E048guOOeXKiR0UrXg+eQyOw8ygEh1RVF8mwM5bYlNrhZVxTj/MmAUuUTf w2mXX6JfLxwGq96I96gd8GLx7z7Ky0j7MmW+GHj/Sfd1G1h48Bkof6oYfQPb0jl9ft9a0J6ykelD pHOuBMQgZkisbY6E3fGqQPSyzRcXKlaDsmLsQpQQniN3q61+d+Kz2ThrAEtmJcAuQWLtLyBOeMZS 489L8v6Q6GyQhvBp8Gubki3h1US4Hsr+rxTs7j4ETSKYA+WVU6/CbCN6Qk2pzZxbUchS4hol70PR MFb8ILXc3AlHYgdD4B6SgW9y01uSEepHXGe64ezLwrzu/AubiDxihuyklWGkOMa41iHZCh6r+m/7 wRrIMCrwQ9eFA7jychf7+2inA2rHBdiGNuA9ofAdhJ+v9ocDdGdKtrNvXAJ1tXbuszR+Qc7YHAe4 mcYFfD7hZ4HudX7IAFKKbVm3dTRVpXoj97jISByfsVbun3+bLluwZzjbu65GPkN8jX9KnXVQPH5z RfY29E0LS1Dnx8qsAWQ/P5xKTIFphEucQ2LGXurOgWt/TCqL26bJ76Rv9mWegjVeBSBZ2USmGCQH H4NBd4ZOdSinJy8tQ2yDlc2WSPDzP+BFHUuqhnDUsYMPxGpKpobDGExMQlG1jjm7eBEB79HkVbtC KpQJU2TB99JshEkOYfYLvtLbHONk+d1rHGgmPwXGC7JuBKi9O+uI7KRtNK98nHryhW4lyuukn1Oa L+lOBPKpJaiw7AoF7jz9baqcSASzp6tmjNTrZZRT5isp3voynvrV+7EmmF5Idl9zegqnUh+ZHKwN zeDxcFV+NKSjS8STHizpzMwLlfbkl8B9QKeD06tXxF1fhtVgPUS0NIsW5fS49GB2v1IrJtK27OWJ VF4mO9AIxs6Ai+uoReiWi0QmTvCf9d05ITT/yc2gGWDj+NT1H2oExz30zrb3Rs2Fcb3D1ou4U6cm BqX20C2vfsVa9NkWXibm+YCchljsYmvt8UVFLBGrPgvo8GgL8ZTeRRM+Sw+/oTHUEcgYGrDmKTeS hsHLHCzpvyhWrpF5nNGsgqGpZ+OLE44hd4FOS9rCe0fXA3/VMiRLMRMxIpAqhw0ofYLVG7jUe82k s6gnzJ8m0nUwosHsZ5jHyQ9hGo3A/YJCyFjbDxuYWjDOdegey7sEcZSD8aFEDgt3sqtra83l+j6i 72TCT2Hcuni2frlruqxwOxOo7rEaegZuUlzsigVWDmRwIzEDnfNC5K20QWimi5eEjj4gw9K5IF2P M0zh5yS+QBPxu8MrGcjbXIJDpxc30lvEbXxEslXMPxfqv90xh9pMD3msejyNFCX9GKiAu71HErih H+pYcqzt0gf31OJjH5NYCglB0y99zFOcGhxGAzUuvqJjlXderrCz5of2XpJXPBmBJtcsRFlfkil/ D+RGyyyWChCoPdi81Uq3qUF1A5R6B6Gt7A88bn2JCfb3r8zD48EW02itxjFJ78slvAyvxx0o3z00 LsBihmZ+AZgr9D5jA+VkadqLdsFgVppjbGils65tGR5gDTtv7kMHH1fAGsrauqr1y5wJSuS5C/AO dly/InDzNBB/+Kc/e1EcNFpm2/zzh0ad9XJN9f0CuZmE1z79FpO9v7G20JosHl23v/jp1rvAgDE9 cHrC9z24/Rv7dQTW15dbRMcFvWweXBCsJ+6ad0UzJPVwLlYyAjm3M2BrxkCe0YjgAwYK8d6phF1o 2URxaRoC9ZH5Bk1uiehugRtS1F3jLHmVhtP6LrApxWO+mMR6nA1IBh7tAgnz3yTXrUIWNawFfZmq QH2mW5hOcdgB3TT0LvoYuIhqB87i8csw9m3I5fhkSdNu+s3BNc/kV6U3mjIHbV743uUvw0VtlX29 eZqKWdppzXcAc07LoOlDzMBDPKY3Dd/HamT4A67AoM2clKv8K2GCChgfeq5TnFT1oFLOuqTpoyjf RBjri8u2FxvByf7Msp55sM6jzYCm24tmRMFdYHnmR1xeV80QIFqngwywcxrgESB19pApd7hYvBF1 s6XgGLwDpe3VIzl8DsT8JN5IPtwRxmD0XXrK7iIuF2adrJiUEwWNKaRGNcGGsMajNj9NxPtrd/7O sH/knUcvgyVfJZN30QC1HUhotDvVOPD3Ht8puFuPp47jafteKES2ha7D4ZIudkmYqqq2QLuW7BpB cwDwbKp8RK057j9JMcwDiSXRvYR+2k9TPg8kPRbTiJHqh9Ne8JaW98jaAAP4n78Rd4jk6N0cZSm3 X/Latt7mptXAdt1tQsWaK+5rk4bz4hkYv/5SAwWczivhAlSd0tYCKD9b97caxALa07ah5b7TY0kq wl+CvXW7fv9w0vttox3lFzSnt3EaMhPu61XCKOR1bmcAMPu3mPfHE3WZgTXIxfIRkid4YW276/p/ mzFrpdVl5Sbd+8S+Hwp7j6YH7tYZFoNdqBNaQDl6EzWB3z70gi3iiwZw2Ee8HPbKhEgsmwHEP9yk uakFK+BCLr1QyznZWt+56/7bTbLz77X43BWgM/OKVtxsOT/S1nzF+zNrbqo9wuqIW5hHbmq8+YEq voArmNMkOhiYOT677NiVNrX0C7okTemNctarSLgP4jzicv0FTztPTXDXTIL9tY7XX/rPubQcUZdY DEeWerTM9TOCNEdytbIjVKp0zQja4lt+cS99vcI26l24e7cVH1v5RNrvm3A/lL7++h0+2vIjlyh0 UxzFrlcOfJab+kLI1BzLi7RW/FPyj9Ky1xgPhpAYK8o6c8tj04HPh0ZagXlDYv9wE8vFRMrlRLB7 Pczck65N74PizfnHj4tBTizMOu46y8mBnr9Au4nf3rzD36T+eTpZFvwG1Jb3Vy3JAoytYwzK/sC3 wRb0r40Di8OllomQtIeNKv6+o004nKViFODGlRYVPqB/vGhAtKo6qA1it1houhq9pzSVV05p/WUV 07IC3EQGsgu+ERsZjqwqvtpm/cmUZtxix2F7RQiW+RZhKqZ7JIpqfqdwCq5t12ZaBCaqucUC/Dfy Tx3kxJPJAUs9jccVZ9YvtbKdNY4c4iDJYdt94Nvmh3v60eXdinFfCU05YVGXMVvAdTV5ylueVXGS 5FeWsglimgcK9YfJy6oqk95tqgAw1EazyCPcd37F0Sq+7QSJBuK9ev3lV1Fpa8hd3rdpnzYAWU5j wGTMHwJA7rFFwJPtDINGsfttloHNplMWPJjHsbBM2CA7cly0jj7C3yYyOCIJPPLOZmqZk0W84sQY bUEZ/tQi2bYHgzKZNnYR84EW0POjIywfoe1+Q53xKlCm4pfXnhJr+EcHY/CTegHy64eGbf4V39c5 v9NXDvBKUw3evYhsbQRDMZTzLLrSDShKx345KPNGr0LPZHuoae5zxTKe4N0GimnpItCifH2kbgVv Er0u8kikb/LEMphRvmNSGSWHCdzPrTDMrjaKuB+qxxPV20WTJ8HVr6reB2OhugWKm2eIa53abdfo PcL0bqQTF50k3dOCkV3tqv7tjxN4xegPEIB6LquGR/CLxmB5vtvjnHeXtWMxXWT96ezjLtfn1G3W qKbCGCZDUcpgpbQcEDO4h/Nl3QheELFjIo9TjI4N39ooA726nlh6BV21zoy5sA/qt1y6t3phXyoi tqiLxTTeUclcNfrJvO56laDIVYc6fZhGxwBFVHqz3lxxDKE3sygsaHz17zDSa0vw7xZUVlo4n3nT xftWptXr1gqAnNSsJD9Z32QfSzXqk4IwZLrd9n660Sb5TzPiyFxgOS+4SIet1o47jWDhn5UWTH2P z19feaP32VOff8r3q3zFdg/vS5IjdE53IDAF0nUMvjvYEICGX3WxdWBm5643c6tdEGz4etChpcQN 902FBlxtkI5twhi9tIYUdpGR3tuQUNKkWqUrfCVoJuvX05EyWBJyOCqU+6D9oNWxpTD/hkg49zIH kEXvLe9VIH2ms4RB9IIeLIluF0z7fGsJFOD9h2S7sXCP9GDzX3Z+WSQIejXPNORSTnMDOC+NnQ49 kBGt9R+e5WMY1B6ZBBiOAI9h1SSqNNk1ooh5mlXhCIZvSiIrBcncML3KK3jMmTBiMpDtxHt6yX8S medBp7HkvjOnZAaK0ty86pVE5zSUhwsgMLlFicy9bDEQU0BNgVS+SsA+DNeXIRcZb7yPxGD664FM ++71a/nBpMEsQuDsvQA52DYppes29cage8rCIaDkSGFjos5cEddrUvX2LcvNFMrp+R9BnVpTMlH/ MwuHzZUCGx3nWLdrBl/gr8vNk7RkmMJgBxXrIg9BAu0ZcwijXHk78zOYuTIclIq4dTQv+nqRFVQY VLdIZy8LOgPF7/8WhkhUIPTKnMtiXVzhTqzjldM/wxOAM8/vNsPjxhhxUQAycvM/6BTqQt2/yz5d aw5CoVl24j9adpXnGlXwJFwik4t/y3NcEOfLhHjMJK5GsMZY2FdXSdXsFnbJ5J4HTnLdL8gJlvjO 8VszMng24Nb8Dy3CwZIgTqxSWPCBOAAjuCtsyIXbiKzH6yCb8UfANY5Btjivl3Wun0NvfgFj1RTq gh8VlbUrGngFWi0dboPkGvB7l4pMHVOlnNeuVYBKUhumVUeyNAVVSS5G8TRnVVHnD+b7/aJkLCkJ n51bHdIb3KRUuahp8SC1hmjzZqWMe+2qHusGdqCnRWsiO17peRmGuV3I/R2f2VjeluTD6JsN1gio uDZ9hu4+i/M/SywFeUD5zxOXHsZfhS9Io0sRLDs63Em6846Y/EidT6y/TI6F9Eihiy0BM9MF7Mt3 scczHOt5IsHX+2KCS9fVGzWiQpjrq51WhvHXRy1OCQASOJQ1OjmKl7+NC7HH2lZlLzMJcseOlMXu gMtpdqQ1HKIkDYbXvnI6S0cKC2fDXjlQNdUtLt6L/2f8W2l5cYBJ5KKYzFViDdBgEcFSQyJ/uCX/ 9nXNdBM4sISnwLShvqUEA5EIW+0RVM81jRwG/MmXNjo33ZVvG5aAzY2F8nwg2obZtCr4UPD9nEWW NLRpCGVDZHn0YnAXOPhClxoLcKaxtEwBUUq89+QGp3k1iEMElbQKaqfsoy+iMhPTIzx2nafh5FCi 9iMcVJP7jQ3C26QlKihkEMH4SRREV5SD7RYakIkp6G23XNTHu5WsWRnW9bWJpsjgOQcFe6fwulTF 0I1Mgft+d9nP0FQIBORnRTav8Lt+DFckioomAsAMj1v6j0FfqMyY6pWRBHky9NMoT/oxTTX/vJhc eHG8IMGvLXh4YbNoF5zKM4JLCHL+ABsqSifnXx50ycdeme5G2o81BOrjdvJCNmEuUsypOpiiMr4T wFJUWzAWoekunbSsA3lNjF5hiQ1nLzT6dgdRpbiWaL9kq2aSMj6U7MuY5hcJ0s4abrHSDGGaNKkW Q2rH8THEgJnfll3SSgIlyrybMtJ+b65SgNFGQf9SkT4w9IFRmrBo50o63PLhk3qrjfHc99QeNaPG BFGt7Xt4WlXIFcklv0+0e/4Qf5+k1uoC8uZ0jww7woWfNg3UEykuppYYUYaNONNOeVdEOfQ40hGW UL3fxKERSzfQ6+/yWez60qmrpgmy2bWTcIuTVmU5ALt147kmKBdX7xC71fuKni10CPQUToDtrc5U Lg7pFITn60rj4RefXkUppx2r7YtD7fGvUVPZ8m+vQgdWBOroN3VeiB2hHo0wlCleqTnESbi7h40R fHn3saqlARdg2vVXaNK8gSuGIHMCSQFUe80bdA+q/OMX3IseqixGLew7rLxG86jj3X+VFwH4fg/2 Kj5JyCi/zNb6avZ8yhQmkg9uYtjog1HDHPbwsZWMIWkfvvEsUgPEs4bWwVk7egui/5uFbdc1QE/w kS4LgZ7N3lB9oi+nCcB4TniSztwPpZNHGcYw1f0JJM0FqwgeBtCK06VKRZWfnGmaZmWM+cDIfMXh Lsdtymu+tkqXWHx4jLFHEwWyyVeHD+z325AM4aCKQaIkfO4Yk9ZLUxIWwGDYGsFFwNFd43qIdcmZ a4RV1k4jkZGXAeXunzAf2j61VrrgCA3MMdU7OD6MtOivJuC34w85YvEUL3PCJPtMGkIYtfGUA6NX 2xYUFyz9fVi9Peepvyhn/w9E+tCV2vnzU7M8RH+OCMhwoTOMWTiZ34SHwbUiH5xMqBzr/DQb0dO7 CJdUA3/Pv6sbv6XGGV/Qn5vaOBMUoRizm3k7zjx1bcbyUPM6FyCzBgTmfQtuLiykhus39N8pnl2f Y8hQoVswQbCB3V3AIO2yiNBG3vHNj/hKattZQyA7XIEVdXgvIz8c4kNZbzy52WZ5gkrhp7EKuTqe hC4Qb9mOKY+s44GutzipATKyxM6Yvj0ELO0JH5yItSSnMReyH/mgTafKYYtk13JXleyUFKRAOMT+ NC/GoB6XoBh2yIHeQMH+HhankurNBYQ0kw9LyD5baQ7ijzv6Vyoa4iNo+5wHgRQ/zy+XQK0az0tG hxkEvEjajfm+vsorw2EoZbuubur0cuoHrgwUiWA8UOpGCGL49DKWpCnH4FPM0Tlc9wkC1MtIqngF wbUt02FiMdW6ilhK6rZa6I4rOGAOp5L+NXrcB5hwZSCbZu6ltz/RpRqfWTuRZLDIUOQ1NKUi/KtU 885K2SxdloNx1uCld4h1taoEH5OzpykSnNq5L46WZRGzSDJouA2mq0o8MNrmgvg23MBBXEJMNP8z OpV9PW7PI0Hg12jKya9NKig0ETGuqzUBbCworuaaJRnHPCCI13jC2mfRuIrP0krzXhwSNv9b3CCm zFtnOli50V/WnWzuOxsNFIR4tMBmpitYDn/nH5byTIyRl0XoFXaIHY8pXwkWQNPU5et04chx6xWO VVzkKjqSVg+OYqHoG6LB5dgtV7SVi9cCOJMmP1/kaUh0Hdgg8Xy8xLOYy+eqaDGvHBn0sb7wlcuE Q1kbKM51MKiiHmJ6LNXfUJqGSVe26JIN7Q3kjHfN9+J4Ivcn2X8pPWJ/HjCj0eKBTS2FAn6zzo0G rzSPqwlgSJFRZgOP9N+2S6DTNCl6wilJM+mnBXBvt32UtDQv2syc/+6UfqJAN0e+9lryNU94fZOp fXq1qZ4zMA3Q7BHkwj0Ju2mlBIWOpOQoeLm6R7M7mPDa4TCeFnSLz6/RA+xDkhZjJlrVHaicvGD4 bLUAmqcKZkLRuPxv72CsaL8exZd0mFldvtf8Y65wMjSIdPZXaC/P3OugLdo3UlYsp/GVtkyh3V3y B5BRHXqDawp/78O6WgKlp5UDeZ3S3SNocVBASqagWlNdCcZXFt8QBkho+nlqjsbu4UZ3WPer8Zju cU0ruTG3a+4hw1+87pJBTo+Wu07sSgJn2byCCZ9o2RpRBQrDD3cFx8ZcXU4Jx2fNGaB/5lBXe/lq ieYZ8os2rwulEY++IQw/Y3xf47mEWrpGN/jc8vvQA1FGnBQiIgq00Rbwa6q7fLqWwCh1GnD8dNi+ Wd4CCx2FT+bNFcrJ5R4mDoKUnQMFVNWi/Ab9icd20uzCtR4PkJABfOM3z4su4vdaTAcGFtr1CpBE FdeP4HNsookj5qGIsFZcKqWoh5eYu/dmI9zhX3CndHXU3/xKCGuK4ADCLVOdZ2cF76ZQ/gcEy9jU f5dw0J5s1sYUjM93rWxtKl8H6FNypWE8OW9Q/ap0zTU+bKqHRV9mx9hTrn7AtfuOIutic0DejzlT IfR/UMY4FlE5LfVNKsg4S5IUySbfpIenXLjf/47ipiZ5hM0vRqJWZThM7yjv6Yc825VG+ZG0FoYb sOde3b8c2e6yV+5/pxK2h/9dcBURoX5vyVd7ratqZJinAJR7nwWrPymzlIi/EeIhw/VIkjiOwiu2 G1p+XySanIEPgWLuF4H5q3jvVCNpCs9GPmE0LlGNpB6O5JLbmX1CsqSlfX16MenbOysOOJZQvrwn eJAi/w22wbDvUl9dJlx/i0iLezxp3kraKexTclpnQHNuikv1vPejDAxaMf3fPpJjtF91EyI2Vg7n Jo8UC11NG06gBl2BMMLjp91qN6JmklFSiszXZVHTJxQFJoYELBdBm0p2AkEqerdDT9NdwQyKCICs q41mSOWjYVOVvoV26jYy+qzzbn5aLkKI6WvZANxW/rL7h8XQdoAf8ZH1tdifpeyAOARp17CBi8se MZzSPvizGfiuiPiThkjMXvatfzA8XR3p0JXwINBQFpiZaA3cgxE163yW2WVOQrF6LBFOml0xC9Ny pzFAZxCVZom642gRRtCj0bOOSJrao+OmeM8EaFULj76kCGGxgPsdlzuA8PBJMz8AMHyByxTcyU2C vqS4BPQr/hNfaMJh3IArKe2sZBCOSwlNamhwTiOt5Eb3xE6UST2rRsPZwsNVOwxnPM2k1RTh2ArZ ne2HZttRpvLia0nzEryI9G/ypiRpyuoQQPgcsfzE1FQ8QMnZegdL1hPKj4ah97cBR8pp0N7IkQgz nR8K/HtNg99hEqBGvfwdOmv6uWw+IxTCPhL/kn7yc+0BtCrC3kz9eGpav03D+WNyyVXnXy6g6tmS iMpiS+LKixG0ZvJ+ltNBs2BEqM9vxq4ieMOVCq9+TKkcB8F/zEs47Mz+Rgiy/uW0F4Hli6tux04c abv1+LHcCcRxCb4k5jsoi9icHyLbe3hHnMvqswfgZ4ZZlUcF7dadb7+SZvfKzlulRGaDmRO40WMg tqrMXHyhDzx6nnqjV5Wl9mDx6ZycBgatgS2NV4XRlNADmNJZzDSy8/dGjRe5yjnFlvBbqVGUvkGw BbgZRLIvBJh/jU9baSi07gLJeItPgbZdx31zC4UXPiowUJu9PLpaRBfWrOgirT7lMJE1QJdyFVNr C7dyZ96eIb+cCfeh+2SW8PHFl5+qaWtBYCkVc1kjwW0ZXBs5UlDloRRbZVIdBWlR12PZcaA1r9RN CHS3cZ8QqY/I1nqQoBvVJmZAIrR2ivDwi+kutVy7ibJCh1IUB6wVlCpUQsI4TI/kbUR8zOmpx7lc dnKEEBpG87Ur1yImfx9mno7YqaAbQxK6Qc1zHGP/seTfb6B1QX9wCseuJkyRsbvFTlX+7wUUEqOC PGCRh5OWqy6+6QwmweckLc59tzv+z5+kpLBpf+Qy+MXvsFD1ERwCpGbFtG094NYJH5R7qwiC02mQ OvLVuQTuWEK6wNfvQheo9Zh7m7iQ5K9rVMuknVvZtqoSclxmzTmyLuMCsBewCdRDoOhW6tWvZYin C9bV4aVLuEQpPaV2LtWOD+eUSYXGjlJh7bQiYdh3G4xXTImCLXUOUZNdGMty0ZSTg6MJEDPjMYCd u8egHbwe6X74wXOuppb96f7j2xXwqrs6LaXVQ4OGnqurKylP3rpz/njv1KpPRyqltFutKG+rsooC mzFG9Je3qJp8xEa+YlR383WGSnnk94QPp70xjItuQvJLLrSXgUYihJXug4o/MvBXbzFFG86/0bD5 8AjBheUheVVA2xQw9LCduHKKzqQ+2B5uK6RBP5Kawivf40EG7NH6MbaQpIExSW9hsrlB3E9MEbLq IItbb5sMgXGxQgG6MfScfsgU47WMyfPB6WGU3F1OWI6FiX0cbwlehCnwjPzZGh3aESMlUvSKYztF +yr4SLcIkL5TMf5V6+dBsy6QVXq6V+9qh8xJWStXSLNzbC6lQkrtiXtTbyezTlm1+7t6PQSIRoXg bquLHyehPGrKz76UU/exyck2ljZpsVM0Z+Q1bKKNcDswQbdQ3tWDo1kNgy3fxVIkBYW/QFG9Ta+H VKRhznZMf2dGzD+EbBLWOa+0uGfGGugFpdPG1IJnzeLjmI+n7fhb/0wT5/YfZ1ZvK9c6d1emaBp9 hNiMw95X8x6RAukJt1yrJkOPi0BEqiA2oTfZmWkPWmltwOi9wDgozGmwF3n66tbSb7++BMtQXR0z GkfsmObttqt0xpCVgS60w9SrN117kOlzDJmYGqMrL3aurNxQtfjZoHW7F2PtWwwPcAmq+aqmpePV /CrOakzaL1+OC8UDCsHNGzerVV+Jy3ix6H9sMPDU67ej0KZBO1fBmyvt718L0VpATOz7hGAPnB1I VvMXjYdobLlVU6XWQKajG3f85qtdu+S0fY8LNkZDw50BbLWxX5GO72nclh48MeOGf/Xlvh527xyn 2LEoIEiSMRSuAvcd1aio6QputLvfWX/CmC0xEJmDbu62+JLQJyCirb4xyxkjFeQ8I+YgVtaJ0pSs a86lGqnwuoMEXs16J5JSfgbCEaMef7MSinx0X7LEWwnD6mBkoNTEBtXz/4TB+KpdamApsFTkTR7Y QXNnxVze5ewkR7u0rQBwvDVmfP/LWlkTu/TGI+zmDNV64/4fi2/zY79oVRL+OB8YfY/khAe8QlpZ 6YTqWcCG8X7Eq6zzpw3tLu80PIbkctSP1sxU17VIKSr5ALKzm/JF4L6zE1RQ9D6wlin6sQxdizqm RgkJhbhssXATlJrZOQLwpciKc4LRBzqwA7pAAJWeTG5lSToZDxKuJcNoYXKxlHvRr/FyiuCWyv3B 95SKb/zETXqUGz2awrqfuu2WIKq0VNhvdgnZCcqge4xhm1r7NSBEJdDY29/GLZH5s8k4WgmNBM+U fS12iyTUz7BSJ3zZ6/s/nnyoNLG9ePspfgZCFGii+IaUwDKCXLvYvu+VSellXeYKYQszImbz1n84 6HKP8GFDBjVlW1FuxVHUpsI6xxrNKPDnA7rSct1rdPWogg/KW203zzj1fVWbLWoaPwTci5gWIQB2 4JsiM/Yb3QzHkkY27t0EXElKRVjb92KiqOcVhdcE5ejBOT5b7XLhCkrY3o1uJLsmJxscjAShxHlF Oo8uofu3WF5wSiws02f4THNqCVmzxi7bUaCh/KImSLKPuyc/TblsHxGO17ktFFSzs12OxeOfzvOB QTEXvDfMQUJYLrrnmKWv713mOfbeI4xUynmEQYvqBkh+jrtd+KykpgufU0Q8iprYP5u0w8vsY8Hn idv+WVnc0pNPAIEhaWnLScXz/a6/fxTAzYxvD99CKcdXzQhFlKu6fpGxdj8g4p3gJUOWSSvFYTdg Kc5L0ac4RkNzxoke/3kp/Y3z1Cb5EMt6A1YGBXOhpIYpgdqhwag1mejz1SdhbaxxrxbmjlVEUwt2 wwLnqli6MS0j/wS4LkVNG36fN5FI3w78YAWB/M1FFFVLOUFP7s91EEP23ZeX2JyZsTfJpgCdS1Uu 7J2mvh2DFMO4vxwCmXyq0wGqnodFtwuc/9vzQrWCVTi3Y5Q1cQB1mciVq/86BXDg6Bgm6f+sp1pl Pq6gPJzaOsY07M82oAPS+Q18eJvOdJ2TLZgujMPC/69J8yu/yXRQeJ3zgC7AzRQ1E5sBr9u0VCEo hCpSa3i/AVpFGiWMgEF5zlF1bphdpTLivZSmnsLI3IYSYaguP3/zl8UhPb4NImYRBgqI6sV9BDDp woh+4Zed5h8f3Cn9wsGfmb4kfChCxTuPWSzX8Vp58NNcZ0r8vdBEcaewNT1QCdM67Q5mdnrX/7Zk yG9QkzwEehxdFZzGxUTNGjZEgThYAOLvFrzrwEm76uDb/SOduXpZGyiXQh6jJk/n4ExNqQUpE5lw 6LZ1/nhAsGsatUEB+Ye5J7U7oqpJisOshLwz+cuCGZOB0ccy5wNQtmdJkK3BWnhk4DFCn0mfN0YB w/2ngQ1nwAJokqDpACN5mF5Ks34fSeEcDEpBquN36rAm6PTp+dia9B032qYNH9K33It39yWJLydn CqR7ulJm39E1Vh6ros8E5kPHTcu7PdDmtdMahGTSalDtxRjWheCne2b80QIErTgxvq+P6GB7Az3k HhHSO8oDNdbzQD37VPvQhMIvxjtyxSzJdjUMtkF8YedNn/O7oByDATQWFdPfsRNv5NXG7PDgV6Mj sttSaamDV+8xVJ6bZTytxjJoL8gR9GK9T4HpmaA6blX/12hRY2rC00gkb9u2NAG1zvUQoi3Mv0i+ LnyZ7wy2SLKvB9bbXvaixCMCpHFNOdSP/G4PJwDnx1RHg+E9up8YjkN1wsWiqVpHMTevrbuUqMxs uGvYzKoxn+CZkNFAClvl3sFEcdtBWGnTA9kVqMcJAhT41ThzN7UltTOfkTBlgqQK5hiyVrObeY1G o3u7TnZgjFe2VoQQreYbvPhclFDmtpzu4GrIQqnxEUHuQ1E4TseFq2o2zzM2aVjQaOJtSxX0h0Zr GQJxqQlqQBAzHd5UwlHqHrDHVx3TRpVkxzLIvxWrrir7Q4SFhlOzCoQKqVpu0ytbSjU1Q3IEnj1J kmTJJt8OrpMXn1JmTJYK5ZQcCKjwCdICtSyc0g0ZJE/ruG+DQSIHG+7Rx9eJEl7VCS7GUjrqs/0u y+cCj+gWfsVBHyyB0biHQePANLfvuKnOQ6YBD0M1NpHhz3Y4U1a05xvjAOPS3pm3B+YnMvlsBwco 26X4/1odiGj9Jp/Y7XgvqOim08XZiytnQq2IYt2K4popQXl3UrBMLZq3c6VoCefV4M/c7q71p+Dq 8iLp0s36wSi6H+ZZWQ13vanq6qrSd23AW0rNofC9kHNVmSIOXssWeKsjYG0QJHicHXWCcy7JrRGz c/TVN8Z8hba/bztNGZ0/IOHLLjhLZVCFNtrZ3OdYk2L+zJtKaJyTy/qLynW3B2EibjBnoZgWsEFb kxyhtJZseXgU+RctdHFv+/CRB5qDtaYc4A04tkPYz1zuvjsG+dOWmgzoAF4wP2Ov3Lp1CzEJYieN NoP8uZMnVgBnz8HF3MMnWg6yuTI5hbt6ONsUXIgilTi5qmgZlmwy3qulhJaS70iBvbz82dSwtlh8 6CEDt6wbMa32oauriOcPUZahi4ifogFLlkaZW9L2wRSS0FfIM61cFFmFlYbxWRP/zUKWdhQ6RnIB +/s20etyeSNNx7nNkhgVnjR/niKZ+T2H9oUz/FNgbjRsTlCkkt+VJ0SsDfm34/WGyzKD88f1EVFi 4rdCej/ldOUntmUqqYp3C6UAgaC8gKzqTyU3hKxOziqabWDPXXM8mBTAanloQoElBwntp0ZjLfus A6gzelWAXk4+5rj3y+mpLtw9JNGGbnByhwoJQxyXOJUAlc47AvwZUVuxyYqlBGm9abBEZdu3GsnF /AsD8I8Qclom3CNxbf7dsSKlGws7INAkk9hVaIN9WyjjZ/+73MIBTbSHCtOGoI8TQwTmQ59DGUqt Wb+k4PEXE91hBFHznUNdiixjRgkjis4xvSueDfL5NKVcvzoHP2euA8ytRz6jfLHCPI5it+hBNP/g 3odTQiE4H/mhHmeX6gP5SuFeMFPSvLcd88vkwiKdsSE3bDrLFlPOLYKSE9MiStD/crWVULtTrZsF gNYPbkoli+8gx1jkECdkmPmrvg38hiFW7n8GJEREanHHqlI1OHvI/2RZ/5cyldd/2ZMyyo+w+9Vh 6bxJlonxwQ3/e+3TgX0/8dNrxEaCYvjBA0jKwOOgepHqkrZ8t8V5DWAhAUy9iKj4XnwvyKdAEYtT bgh+h9xhddjmY8lQ/aoZQzlkyWr6gPOIY6ZZ9F8jIORzZp1MVnlDiJi59uXUE3FM3/YrMV1d+T1h bQ0dmxnUbajJCiawaV1mfbr6JEtx/1GlAJv5liJJle4vxNj7OW4ddFzDUzBCclkeGViJoWMB+VHT 3AlAvc5jWq8snFQMzOou1PG0p6ma3j4Q4HO57Kzu8iWSrMc/MOXBLZx518/YfRkyJvNq4oqkPNWA xJ4506zqRHL+ZWPJNYXBJBpclX7brkXTI4qSz/br7jz9fNwuekvI+SIvnnhM+62IJSzFB6QA+LpP Ctm/IonumBHKEE/ASw0iqyUdQTEP3nafjkngNyd73+qbpi/JRnxOg1Jz+cYgKPRlr5vv0ZbxoPdA +rH58R5DbMy87HxCBA35e+FlsStHUd0MfqfWNLF9kifkY/JLaTTFH6OUayc3qcKRRG2+/F1GTvwH AbywjtUd0JeBU654P6/dXYjJRPIlLil6M+3EyeEH+2RrBtISp/84kOflLCZ10defFiWumE+h8tV/ JbgNtZCsZPmdqD/0EcI/N0ryV3LYrzCL//R7t/0TTeevNBQ1bJap6Am9TPIzjTv0V7BLHVlAt0hI /yz8lKB0Rj6U3sN/h7oIyXgOX3qbeZtTCV/Dte8BKKtz5YgITuX1I+W2i4sMyflPwYOPFSwmC8l7 II0H/a3SWUzb7qmi7DRueSTuYVl1Vwz5a/n7cBnsks4tvygwh/vBVsf/3klXJ3869sQF2bty7dUJ 9MWr1tWy2udQCV49C/IbSLvWZLHKI54sM0UaPYHBeyb5iEJnn3bYFKSpR4YPWQNTCWtrKV+cefyT MCJ/+83XfcCX63y0rguLYsPR38K63JxoqGqlamZytXkUnyijBp5HZVfh6NZi7y47rc+LLjz9kYWs YW+AFIxoPvzCoG7MxmQ1rStnAZ44750wTUKt1NGzy5tknXljbKBTeB0nFRGvb0898QFUEmnWK9P6 0gzvJRgSyzg5La6b3d5Oc4AEuvZ3VQSc0zmRuew47a57Gwa2EdvgSwI7NAPmD9l7br5Zhtdwvnbi hjPloKCVNJpRJygHABuHz7iJKuo5ikDO+kM0fKmc/6MkEQ0npTggJHw51SBeJl1gvhjTBQ86ptjr G6wZ58QUb+ccHk2+RG3cm86lP+R4UhwidMQb4J3dfQhO7/3gur5hNig9rs7aPANSHPULQYfin/TN WBb9gfI0v7OoBVFlonDgFA/aZybfTHL+1B9/rnB+koqJQ7ly5EYTViDejKWJ2iV6gPULDeGOmNu4 MP/+HrY/NWPEfx+piHpjb5Xsf3lHQvzOs3mZ+M093j3eOq60ptOtFzQTeZoGO5MElabC2Lk8VC4i UOuKT1xO17tmuqhUIIRyHNI2SdVgonhos5A7B9gNDtJDYjIUcydjXKBm6MdURMEwhVtuFGOCEkVw CPTXhNaw0gwfVIeeYavYJ/rzR5uiijGSUcbHtH0xHanT2OLsjF/sXRlGXMEqKjjuTtudEwkeRHjJ TiPKS/0FwDgC0VAEm5OqPZAkLsLwzL/BV7t+OfTDQj41Lndrri05b48q07XnkPMkRsMWeAHpEQhY oHt2TJx/oTE9Azw5LdYIyIBVyL3KPfgij6joyf9XIyQMdSAV27dWn2Tp6PEP+QtRW5Lc9tbNTZVC +6Yno3xx07yiRyfQYHmR/O/yYUxjIQq6nFTGVCJwhEdrv46NpH4/jMXsGDlZebOQehUrCpuStRTy 9GExw7u4VpIlXX51zzSXDs1INMtDEUEd/9rtqBnrc5KYqWUeI5nh5LGiXXEMaipHdZCnLL68LdbH 06gqeZI4zU9b4Nw8b0kG0A4F4IF5YiHed30AJfHxh3JsCe948Rs769N4lrsnnkpOrKLLpngrZCwO 68HigMiUtx6hFnlYr2UZsF33gnrr8AdjCDwFD8POEajENwrhFkBdVzuq8vOxYBYK8glPwkYYCm/+ JU7XxJctS6D0xNvpT7peVSSkM6/3B+YFXkW2oddY+N6iu0pZq7GLi5nMhKgoYhAZlVGDvAompvSc qtxhW9TjnxlzgOpvPFseXZPfAath/92mQOKtLg5J6Xwuujofa2+rS7ue/hSSiQMihixsWUS7y+1h EIrSbKQ+oKsM1Irg+fPBFFSE/wOIVUPs0ndubvephwm6KuTDiWNoWcgx8kOX9pk5Rdn22AnmAIZu hKsrBb0yQr1gXXoOT3tmF8zmIpgcOq8F9ZNzCqiGRDQpudqgkkG6PmNcJYiA0bbVhsWhJMZK8WK/ XDIC6ry9F8Id8QfHyPt0pl/fiEePtUcPF7IsBpJmHz3ERd/1FQcN6N7HTNW0ImxRqsG+p/nmG26M HbRVmC6I8E3C0dxgF3z+xLpBUIWKCKDV/k8Q8CnKrE4a6Lb6GoX+e3Om/zpy7fsqDZhH6GYZnty0 fIGdYmwkZCdjpzv+nXrZ5Xk6Dg3NAX5Gu/yprBKLTmDtso0LfEUTTujDfOYeO33DDFNq2+4jpxGu ApkPpdS1Xrkia6bU4o4rrqhMHzQ0FhDhRKgiZY3p6Hk8jehXqgPDxfk3eBHnDSIOOXD3qK/SKAWV HUzT6ubSd1l617u76DoDgd/pG2miz1ekqpsfCaXC78ZJH6/yrm59NvRVu7FbkKyi3aglK3k6Jgbz 4iE2rZ0yfu5qr71y85J4vI9F38PlhYtFARJYNznZMAmR6WGuDzcrBbrGyQ77fNpq1GziYWlxHiCG RpodgJwKFm0CMAy4uRuZ/Z1yFI7z97eTsRJOsm0/iWa02Vq6peY6OpDJUPb3D+P2VBBPwx5Xpyo8 VGTFH9RXx9UzH1uNEk4qkjBzyYkr8M29G503AT2kKtzVxADeuqehDaBfThkdsWmN9JZDmflSCW6S fMAGqP/AWLIdMk63J0KffU8WnbdPAYFgObrXPAw3kMstEWVFkRA1IcjBe8ZZMF3r0kql+9d1MV9Z pa2yzWcI76hij6S3A4Q8f2Cdi5MHK7BTalCr/awarbOFGsnqo4doNr3UK1iwgMtC+xA3Za55Czft pNV2nmr4Uxfm3PRLGEnZqgWlDMD6LVjn3TgZkt06Izp+VEq1XVMgcKWMPe/udgJAvyP8sYKibAJw 73tRWUbS8hVlKdkz7yIW/Hl44fA5He3EmfcMNEZzn9gxvSiUmbsygrwJoSi9JVfx4gnAKZyROSku NcIjj2pjrYcvTOq+xoy81KNtdSlXNMcjRAD2PDuN6RqEnXbGpr6V9QDS0Z6m4J1M4hSYquoXOG2v P5BScjT/wlyYxxY8lEWFi5PoJhbfbpEfEYdIVKPpMcPEEp4RGyBEhQbSHehOAMte+81j7Ys7j3DH mH0+cZn8ysnXN5PFpp2kM/048Lu2qyCgx+R68qaRNsB7AohlSTCHaKtl0vpsehf2oT0cHzMg3ueg NJJ4d2PsXMqbHkWqLrtZBgphvGLLEIHXNtVosV1a09XjaM/k2lS41wX0ALwVSmgwDGbWBXz69l5/ si9pq9xiagvtEGvyVh9jimJCznZRzmuHLH9IVImOOIWrKXOQ+Z1a5Wgq7yhC9/hmXuIIFdxkoudT ovkedypxdKSnwINx2jHrdXpPpvDR6FUdaRfgyGrSb6NgcL0owWesdNuP6H4jBK+fFMyF5yQkAqw9 3G8b7ioovnMPZPXTOvxsoMujx395Cy8yM9vCp/rxMnkD5c6mCrZpK1zSEMR5RFuH9ruaGfXrghvr 2mTZUu4zDaIGV6VLAEcjGcKrWGr1JPyE94MwUqkehhSNJj6dT9hvC7RCFC/AYwiSZkqvAlFLbc5Y O3F/RX12emJEzpfcCKtj+rERuLg+y9QaEOkhI+2dqxodwYZWokK+ZBHODWw5CCxNKsgRlVLUgqI7 KpPs67HYKXA8sC3uMbb5b4xkxg0Tj16mdtcGTktmWVNsDfwJuZkmORGXNRsLOCnTtM5XYqNY7zsH +tJcU5pgrdPygZtblEbqkQY3uIfTyRiHyMsNtVZZETIm+Orx52Ls8/zk48wP9iqE1EnwuHXA40t+ 9z83XgxHAZzhZxAckTxK4k+Qrd2O/uNx2dW0yYE/n423CBR/o3y/hrWArtIK5J3GuRLbdW2Z7IrK M4k4A2snY6sB6fiWNX4Cth+VSSOxScRKzV9bjLJHgndQrLIhYUyi8HJcZ3jWLllGhCfgFws27z2b CzHCu4jmmH5b5Dz76UWfpEWeuPd8VdOP9vtlYZNxvg8CDQrfIb9rQOOuzSPluVkqNCClOCm21EhF iBfjaqCy0W3S2vVxCieGwrvk5gNHnwV2iWssbO5AK/M/D/uEG17fXPTm1nW+qcZbGxt+/Upkz/YY iRGNKTQUm9JAZdy1fpQ1Nh8QkgjiFZMO7G3w61xDDvcFsKeYt5wiTH1Zkm9091rgntiwV/y/Yk5r icBWNg48QjVor7BF7Q4TZy6XfhSwxa+9PWbtmP9gu4kpKTMWoA1WnwcrimcWhPyJ36G+5DE7mffO 8OTzqiVsHA5xSrmKL6mwWO6Y1lcijOJWv/RaOyoDmzJrwckOtK6lq9GGQNvcR4R5nQzsb4ys174g 6VuaB1PN+A4uRElIXPah2P0xUs4N7dFffr4snNFf0+tIn+0aUVPbm7F7MWGCE4MRQx6B8bQpf+DV hrJCE67Wsx+D1gazIXifyhtUQTBQjRTNsIzRXHXkqF9sZwaJ2dMdSsVRYRU5QL5oKNtlRR1skdaY flITyaju8VXQ9ygbOI18NiSF/MN746NpGoIV5Z9/z9WbjX0vLCetKfVfDDyHFOd9PeHQLyRtJTMR 1xNV40u1D20w+tKeG9eP4ndjkJ4wQ0LUkDvrF2uUAL1r5wh6vqFHbT8DWz/jAYBZd1ErqaLkubkV mpP14rCo1B75oRnXpL5hSPByWu5TnUiP6qMtsiSvtX4AY92L/afgOPRn2/6dtNs6iKt7ZSGJdq2M Y6CtDYUol8q3FLuw/GS97u41JENIWbY+fTzWGXO3d2/NBKiPD5lMw72DcEdl4GCwA/gr+aTY7xB2 YN2rVU8+L6XVfDcAoqORjVbDwC71xyzyyvd5mfOT88i7HotV3RHl13TCtazqpv8BYjz1cNrcXvsP j/6Eg0ixoZbvSKpUQ2OB3oK8MbbbUxtXFErGC/V3IkUtD97Lt9hf96Q0crKdUt83en46mKCMArcl KY7mmqgsDOTqVw/KIVJk73Iee+vVQSqeYrEUjKhPspuTwCmJM/75ZiODiYZciRiBSH74oZRms9eb hCULNhx3wj3Nc/uI6cYaz96/J/xiM+FD5pIgiSagPZZAFbGf0ixWBk2VylqUgk2ZCvIC4Vwi6dZT quEeg61kiMLxBjmJ9Vbz1MhAkKp61VJFiwyUJ33MFqRA4WhHgdqjWoYDGxuXFnN3SBydjgvduaEd ih715QUnsw5y9/FHTqA5Ak57/dBVIcZioBcSvR7KiMfhsRKjcSqGRChqNcyIEg2V2M4g2scPCTrs sF2GqJ/alyf4haQV0IPjeMuQn5uvolyEIBESM5xqXmf7pG7a7JexWdbeNTTVtokLbYOaaIysn29a szSOiC5VUzAeNRhcP3reyra6rjq0NhuhkT6tosTORNj1x9Ib+4yeuQlMk8jI685R4Pr7FswgmLsu ExgJ+0iE59a55JObBoBNDRI8hiEn+nz/iY60w1Ct3yOOd2DCC5BGZhCDhIFtczVzgPJWtY8T0Ney 8UJ48ZfGL9niavrWptyKvBF6CJCaDGwFr/mvca8nKWtiUftKBuxiNu2Wumx3d0DeMFpUYEYjCWJM mYyVEdX1FlI8MshcL08oxt14i8y5TgOJAnZw8JIvqVRvyZF/aHSQdvnjiuC2AbbL2BUsPOhmi9MM G8mHZaxgYY47ME5mOhdl6O9+bAi72ZgZntIVrxTVZrfVtIeBMKm+GQecsIVRHaCptbt+PTvatZPv EduUl9ED1n5XHDb+BTqHxoG8UHJuYiLyBZEDDQ+8m5b7nUjRzgR31FiN0lL9mUc6kGfTOim9FFBo lrPQjrdWlFqn1BHT4i48SsLVtqfxSfbjxy19z/N4X4GzGinljNe75bY9S7l1dAH/SDxx7qf89+qx gsc7+aVwADg/G2Z733J/2cqoi7sPBbHvzSI+9MES7yRp9hEONwgA5hXn19LLh8HWE+i5IIvBgNDQ risFxvIrqvS7yzTJmuGuySYiOpBabI4DWbca8NytL+/7NtEY7O+/7lf/YrMTyDUl/uu5h6fcuMj3 LWzlVBF33ZSlXtG0VVJ513bFbWOnInE3vp4JX6oMgwBDoShmcTPCRx5k6wl2M1UCrt8JnlTQnRyN DsSg0YTxmo1SvntcR3M/8Boi0LBodQeVBS5mghxPPXStq5ZP2NybfvgAqCy9M2yMssGigiHd2Fwt V5gxGYyIPhBMyhkCoqSZ4UZeRIvO+lnhCBRLNBWAM8AmygYmu7c3Co8T+h/5VHlO+Z3kgqLC1lBp eyIYbQeVPiL2M3f/b7+z8BfjlOBvT03/4C4v8qxQXMtkPZ9hgP4ZrGXjFR2x1zwMWVlHCgXxcnmq HAXINDIoPOg2A8Xip7f8+fuiykqBLdYYIRQFxuXu4F6nMvHEbtjahdoY9ZrZ2MXKZyEmp33/oIxb pJ1/QwwGTZNw/j7DhTq4+WeoWCysnNV6ZKVEMe8JpVrbP0IRBV5wnyZTPbZrg9AAUS4qs4DHXXk7 SZPCcnwkW6S7u6LS3FD+EW36k0OdJth2jLmgPpG1YQHKWr+eyVF+nuiBSPHuDEVvBTilxbU8U9WP OQKqFJ+XoXYjZiNe7L996J0237ys+1bn5SQM5ogVR0U2rQKMNlTFr5wvv0qJD6DlaN9bJwak+rDC GHdk2HovsJlEbULPOyrasxp/yyD8nnY+DhkODeY1FczlITxZaEVhFdDUCin/EBFSEUmmlPo4CStL mZGIG6lNGgLmj1xJuo57NQtVd/kKb4PHosqABiemV8DTkCD5a+gSggXrIA4qOaZJ1FK9HSHrpXbS /00R9ZQknh2V8yI+HmBT/NiTyrLwkrAaqpoJVPoiPBSCWxtuNcqwmnjTVDy5wXajL0fYfckz0fSg SiWWr3NQ2JFvvEcr9gJt5jzOzodoHf98zoNhsoWlQ+0N8uCllxW6yRfOCdVvRoYEQCsKeZTWLSW5 237YRKjgh2X1CQNZ5SHdXRyxPMfmfvIUsJ/O5uKkYfZp+eM/wkhnrvTTaaaDXrz1tDPXmSNl+lgb 1H8SDF8t4JtB+AWrc1XVW5erVIsMpElP5UqGYyKTwWTx7Tx3KdfdCpVdOlNj1/l6pfSDrCtkPS81 FCn9eOK5bw1HSiywTarg2B6w2dQSeU3hop7Kz2ox2YltmFz0/C4PtN3mYx/sawwvoZ8IXTiLKyp7 ZFoWVe+Lp0tMzck5EF4MYzY2lZmRV4s/snU9KorBhW9m/4ohrOVRR1OxDB8iARBzsBMTSCbsOWER GVu12aNgppJpD5IoO/50QlYooNL0YAGjliM+ZorTv+6pJpX4iWypbr8H/BDK5RnfRGtDcTRAC4oc NRqf2B03tO2LEPJM9nmObKpxFWbys6OOOackkkkIV4T7n5wvfK9xjuy9Md8NtkADZC2+J1GbPikg +divRD6X6N9yQCm2AHa1UMUWIHvwYZHDoQ4lG+FIDMqnNUZZt/gWPz7iZTFgjteLkt2iCT/w62g0 VfrL211VL1iXJvZyhc4ubSnSo0WqSH+1QNOFd8+o8JR2gyNxSUoEEaI9OKxyn7ZdDZmql9kne73C tTLSkbDG/zlPPIFuOvL2c3yYLK5lqHzvQbY1NygxxomWQeKOjlscELTgxdcDUxSvJPo7v/4LlmA8 vxuPdj8cF2RaIwRZ4QtFwXjv7jQUD3b3Z0myvcve71LupqfwW1J+pVkStt+oPKj5tiNeRrgtMzsP RK8p9strOXsGOfVm+xWCiRr+HEF3xeHCoH2do8BLCOjsPgB9LplCJJle8yhCW7Y+MCsrWiIQl7LX NOx4XeIvw/3Sa4iJbrIyto89cGPde/qdx0FV1YhKj5jmIhAJHuwmUnKnBhx2ICcGnX9kO+qxYHoo MQMdyU9ZpUMYff1I8+VyOI/YWEi+De0Hc4wJMe0hf/h2tK+EXL/rVUfpyn0+nhUkt0dXhj5Hl3YB Zv4koSfazRzcTcXf1KGXr+1Kp2zFHNu8ZOkLaHMkxFO8u9GYUijE7aE0jZ0JI0Lc/yDyZYG7oMZy rrEGK/D6/Umg2ZdLh0gRFz9dTAs/Ki8ETQYYsy17iP9rzL9a2NCFLl7IL1rPw6evAcNYItQzanxl HJCfrv8OVY43M1N69WOPAjKArRQLP9ZeWmZrCN8uHAbnp7Kr04EPAN9M3XMofzHanz9s0NBq/MeN z3shRxlZ33KRnAXuB4OGehE1kPBMOmyXnuztAJwAPEK1R7sXzRz1krw2KjhNWemLlbxNXsLESEjY J09+dWHfv/xjoUl6i6SIkfvg9hnJmDHoFtQsdsEYG4BHtSa3+5VPrSHjl4A9WJOxAwnB7/oQLJM8 7kDFWEtNhZ8+y7xyq/HP2A57CVBBHhWTZ6xWwq76558++hD4c/8J3Y9XlrG3jJF677SsvOc4Eoef KgIbmp3bfKDgit0WAhyL+KAr2PHwuNocLEClCDw2mbkUD94fXOaYC98n24mYK9CFpWN/19PU3Hc1 WPMRjQCx58beHkyXfoT5aKRu3LsHZ+/l12aZsn7rRFxfKcqrpQd41uZCTRmdyG25jrEloJWIdQGe t9lYFM7jO+3d20Tg3MBSLc7bmoMgDSjf7ST0pmbrHJpTGSR3Ir945L2RZ6pb3ZCdncurkNUe1LKn 7R/XR0G9kEqhQlJbEa/qPCyV0p2Uf2L9xHOoKawQvGDXy0fdjHDTlIi2PAPRqZ8PvQywEg+0t+sC 6VQceDEGaToVeSmRss3/FAQ9WuhxLjp5s7vt+Lwv3iIqho818UKIxs50nTdmg9pAsRv2Zxhgliij l/2plOpTocWuYebreYvAM12hcsr9QJvLfPZ1v1rEskHfA1kATu9cOLcq0Ke1AUDceqnWww8y0DFa xH9ruYacoOAPrMTe/OLCc9WvcrOLhjs4hWPEHs0Eyoe0G3QbpjRQzNKCeCvwq3V3bK7ZGVcTr3Hc YF6oyPeadqY3sk/DBKON01OvQZeF6HhNM9CIDt/HF0SovDoPjIvpwj9+WyOL2235EINetJbo5qEY 6EEaSCspBeA1F2npJBdKbZEo+fVpP/7vHGqVEAMRWkY+kR7qU9AQ31ZK+KxbQFOZ1EQqY5/zbrnP kFB1Jenaxu5TpWU0368z+sCfqHbLssxDs+UrziuyhfqKKcPfur32fu8jikAklPplKGwyy8VJ/xyp JkUj5R6WFaOb6EDwXyIjNArPWLnNS+J1M+L+t5x2nBdSXQqux20dCC+n+KNqNxTZfha1kcT9K+2f BENLIup8KF9ZvBTu2Luf0FyB37iWZ9JqgQgMqj3XQK5X5jTQSRAV4iCRUOUEL15ckMpNM2SkSaNS tbYOhV00E5z9Wncd008GLS6FDG+a6Z6dqXU4InKeEey9s3NjIJTyXzrBV0wKJe+luBc52C0m5HoO Zg5bs/Zm1Q6SBRpt38B48NZC0mGppF50NqhIVps8a7pI1lxGMbiVtewq/XMz/aXSZdu/eJywxlPC YtMwSPDKcIQaDnFpR+n5olIMrf8b4ZUjHBQU1Kd61vcThtCtPiexgZCjA/n+XefGDfZQrxsx1f4B SfYe/BtmxJft4f4v7rqAgipMsKUvIYkFZiORBdGnvAlCZs29+fe3ywAZ2fpzFJwruIk58rddQqGb UC7KrEFhlEhFCvWvJvjKxj/lNsvL6t3EwKahncJEmLx4YKZuyIxUPskNNfN0z/jEVLJ9gkIq911J 8o5IgbKWyIzFhxWZfq6bAYFNGeetTb1n1pKZzhpuKQo277yoAQNZzeczdt8ustXCxOOvyRPcfMYp Q/0bFoPwZGVVfrQN2tHwnmUkF0qZnLUa09ngrTCcui9bQDPwvjQgc8GTQQeT/43e44TY9QEzpmfG ElsZmAncdBk9K7amcGHnwvLvy9bGjJzSpTUA/UCHzbmKgm6KW4DVcdDa9FyrX2TRItbzJv0IzeAf 2Ug05Lyd5aXItoGgQEjxUtnsGCsrJRAjZqrhuGx9icLzcjpHB81ZAz9JxbYlKcUz+A54VmT2Znev Nu7pLA3J5dod7QppuHCPACZiSXgYi0+eoS+He/g/z3pu1EzJez/xYwA7F71j9eisXxSTrlTrMmK+ LoTK5YP8+Em+ABsda6UWu8/6vmgOsSPPiLk3kF6yz091jpjROIxeJwTPd1tEJp4XXX00HoVF2Ofl RSQaqsnnnb5kK/MqmHrvdqOI/JRe9QROVZnbUtqYFetZ274BPkRWT/wQeFji1jxHhA7nHY5Z2dla uU8F3NrzSGpVqWyiC46ve2GKQbB0gu1h6sKQqavTcG4g5TDzQsQhCGHAcLD8Y6osPzjPJ6iWxhYZ FUeIIdhYPFxs7UPlzI8ePFo3I+ZtlN5vQdyJrc4+eMNz+qhswcU0PYEI2ZijVD7LGjBGy3jruV/e cAuprBA8xc0FmUbt+5lVAEc3WS+a7yr9puV3VXubzkjWW+nrJgQFCXlcQm8Wi1JOac8SdZR1nLMB G2o+s+i/rkWS0FnG1WU+tVybmgpwS6hO5CRbCPTx2abgPcSPVo5x9QZnlR2JNurE8AxqH7vmC1Mu G3y7CidxEId9QX1I5QtOMw8XweBm8TtEhunU7Bh75H2gx/QqrwYguHRx1crEo5GQw09Y10Q26P9h nm05QcoHo249EffJLYnS6K4gXuwjSIfRsafeQLL1fc/qqF6OcCJ3ORIFX49VjzEH+chjLMOKhsTi IcpT3LQuGO7pXuek18NXfxrHuSDmFYe+WXen/WW6KxuMrd2EUOCosMruwwEK9QFzorf8N5xeFRF/ Hrc1Ft+QsJq6Ew/WpESpqlG0BpNHbs+BNpU+0QwktpJ7g87aC8/ebYCo5TZlFwYUJCfBgo4W+oui z3lDCk1yUAFAOl66yGxMaDcneDIuZN2yIODTvCpOzMgQ1tfzUTw70qsHokJuc2ks9knxCGPH1ikg fk++GuGTSvhXnSmBIayFRNfhEFiQ0g2hE+gMClXqDi+dV+73EZKWtyD8gQ2JFx+r8x6GtIWW0imZ uPttBrmjfhLLCen04DwVjpiekW0Dqsce6ZIx2+QQCDNx3Z5J+o3glbdJHWth/MKheP341qpCFhhm urh1hx4MWQdz18875pCoJ91+U+bRfeu8S3ctVZ7xB2qOl7tbAis2UimU5LLws9MpmVuTnMrwUnqG RBXKgQ4zry6eM51/nBg8tuzzlJBoyUTWUkfieOrxOfGEw84TXku+6J05e0Wi2N5BHwAUryFL094+ gtnDs+kkmXHkhzKu518Jei1zJMZRcfvLrMcs7s4ptt5HUf1V6x+FfnAH5THxYyhE+zjS7QyS3RYg i0rW+CIrx5z84AziyRKQiwnKVinAT7Xb+vbP2vl2Dt1RRMMqIhSm9iwSjxZA57bPcMcjtq/9BDVY DGzlaoA3gLL7T2ZQVSZN1HKzskD/zenZ4vNBGQs5lVwnLODQ+LqjOdw5Tge1Ar6fgdmiTlsLIzQ1 wJLHxMT2tZM4KvtAT3/O84Zam+Bx74x9UBw54Xk2wd3y703Hoimq6lhN5ZXy6VLoXvqr/OWyTnUR 0bsYsAjv9XpvjoeHK5wUpDMqkBa7L3vk9cSCSjdjVFdOSWY7C0yAXEVdgxE2F99Qpr+qYGCc31gv 7iwrV3z/sqvAazAru6weX9RJj2AB2WGbgrITcnpJ/6uPs9nQ9DSr/qEFXchiZuDiZgzGm4Veqmlv 3oZXDd/93EdCoT2PC5kp+T0SfLb5qYpZWLrrkGsiSBWB6nlea+z/gLdWDaxPpa/xhmJOlJYyjzEs TzcmFycUGscKYM8hBOqBTy+p6SUHP+BmrcfbD30pJ3Beu4cbDTo78mgbnsVDTMj4+KIO4zb3Js8L JZl9WjsNvMkGmQIHZNdX+1sIwVdlbco9p0lEf968iME/elbsLAi/0VqzV6Ha55QxiOisFieEqGcV 3wAeimRHLTSUqxFBDjPuuTH+clAO8qyvuKZEOpxX+OrviBQd08UkWj058c6LNodaPVVtKIlkUUBv J/i5Ivj88mdkXN1IuQSnYYoOUWUfmacVppWnwr8XPACjmaAOy2JFXFBRqsXLeaxKVd1dsyrIDYnQ a+6KRZI14IDxWTRF5zq5kSeb3MS7U5tU0bBiCihiq5QrIwzMe88Jc+tNs38hHMnCpVyPU+DFVicN hI7/Q35AlVfQBPF6rwUv3rP5uq8HLpIhIlmnGnL2sc9uZ/FtTYmFQbF8ODV7RX2R1FzyHxuxGsWm 5dyMZ8r+ck6c+8YvQlQUe3XaSgUl4q3/QvCLlyxLjnsjNaIp3873IgKk9YGsqJb8G4P0ptgzZfkC c/nZi7bKiYKnPac6kA9qH+JntbND3fjhe/cgzybTB4mBae2f7loiRJVnml7oCfN4S+LLtBosJRuZ 9hMaSto3a0WVOi4M7mzbprxf8/MysGtVI4rtAsI1X0xBXTNk6PdIYHHG7EdWEv1Asjq12ZL2Axyq gZV5chaDis4jc08RH2eiPJiqIecId2r0depepG3KiHGSth1NPqXbW4/sYhPRJY8AsfVSp43TfJue o4dZRPOxVY6p81mzkTOxXs5Zc1mtNjBYoXhCrB8w2haX6ZgFFbe6XIuYOstb1U9RfE0lp5696yDi VfjxYXuJs9uHU/xJoj1v8WMs7kdn3/T8xXeFWP+c+x+auvTBTMkkfGDDJ5TzWYDUGVxrVUeI6SVL FriXaBmopotOyo307De3oqCyk+gmI49YjrooAJwO4AaHeTsRf331ZfovHEvtw/lPXxhx2gBaZp8J 4HzbVIG04TMFd1gv5UKPHITUaqFZRZjP3Ad+FR9YBHp+24r14ohnn5pDMePIxYAswY4N8xYUPzvu GSylN8PFznBt/dMCT/Q+7gSjB+4GIelMAAtp3TCAT3tId1f8jaeSo+8fTlrsqqMAPzX2hVvqJScp N2IExrKCIXMvF7G13KeFYAcOzboEhbAB5rNpw5tg5d7zgR1qGe+jpvhnhSih6a9xDMobmDBXRI7F +exFOx+ZzidoJtE5uzv8GdI3SpJ8J1WBxbkeQOLx9XzT7UIPmIT0lFgK2h3i4jMQWwzfe0BOjCPB KMAExbIpoMIWWZT7wMDa8wrK3t+kSJ/8at8YXEl7ifsiqruor5PFsiMwN1Q2B8nLOyH5921HDvmA N5T2c1brpDrTCzRmTYGPc/LhXqk0d9DcVLK9pmZhoN+tplMiY/jifEuT7rg7uQXaWkF/0dwnwTsh VIgRbbve0p8iyY48GNGWPU+Xnek2UdckQKxpRchQ3bgKt6UdLSaTQPjQpGil2G6LxyQyCsPaaukN THuhrrtQc114SS9KTgkvrFkvWSYb+E5MyiQC2XK7PMIA0ktPjeity7T3FtPH7JUlr4S0LBQ4jOB1 2AuVtkFDrP5pQZLbVIqXNNMiOstTrxxjEJvOMmEERUIfFeoRnyjN8BRxVLGYe/tUdfGB48UKDNQs 44ECxElGnEnzsHzlV7D5taBI3un28obDHjfcngTRTlQHsD/UIY4YJkuEW1i341QKEPlA8gYlpQ5U 0POmv/vlogOSN/I24xvpR+6679EbH23YzNRbgUNVfcFjZpxzPzXR4BgLdLNVTfbVXt9YMY9jIbK8 h/Nx0xy7nd8sXGt3LfTPy7Tz3SSkY0lYjebZ0Aki3yhseF16w9lFdQklvxCthLjD5CosKNsAQ6Nf uPFt6jeF2DIPjomdXX8r+RzFX1ZAyPS+lNRGYY4Sce684rPAkxWlBoyic0LgDPPia/za2xiv+oqC L3CTUzr3K3qNmJlVKZBVht6tbHAXhok6bfozGWYs9GEqUFYabAud63d/DJ0NEn3fXocOcg5rqOxc lWFoKa8AMFWl5GxcKGXjhkZgTr/Ky94FsYDPAERT216j9gz53FBqLvOzo5Ahagkb9++Kk2+H/xxJ HEpkO6oRrcUCkn8jOVhvFn/VENnV+vQoMNviLbXhLgY75m2xFYElNkqS9yjwPADBK/x+o6de5mNk M1Oyenwc3HTY8vEwYnarbVpTayRVWVt3yiYpBX+/IVYNzGBSS1c9xJmnZDDLVJrYfjJXbyThPo4K sPwWVWhY/wO0dxVBBWkyThLj9n933WeDRByYSAho9EC3xIt9drQ0sfl38xrjfvXXGimyWcHN83X9 tkM0rENkNqaJvB+mUAdQ3P6k1w3z3pmgPPnCPolaoAynPETAF8+YqizAgcJJlAxsxk8X33aownbY NF0rZzQOs3KEGuA9p3FYJiFHDsmDg3rQ9HElrkr7xAoUvjHH4jLd+/b3eksvP0j413w50jcTPbW7 LEC+j+53IriMicItmLqN9Ir8nMa3xxCdNHr+mbSBiDdzK6fXgQIm1MOkKmc5NZX042tOPf/h+dtr JnezgdqMFoz4Qnd0Q2kSYZWh/vPACf1IvvCj49PdA/YXunFLn6Z+itKXC4bu2WPnjmmVkYsW6Sc/ h4NPDFAqPbpl/YLt5JpOp2PJthfP9k3s6jO377zr+2W0s3dPlN+i0txvPFyGcEwfcbmpZZ5fCfBs 7Hm2rgQP4sQZWvLXe0vCmWpSQx4/TsBwcmpVnaX7qd0zOtX6CT0+VILJcknPbABkc0tb+wdDYnh1 RqdDhyn3CKrdNprALPJl0pXKKhiKdbksOGhkPIToiqroshZJTrYKu60t/Vyc5vT0FEjn9yw/USX/ PS5zLKb870pyJ3o5EJDt9mLf+gsEzQr5rbfR2NF53QWlvCLVVfLUnNmx6ZGPwM7/DbKhRTFXqK69 WxnojnhjXeTmUtx+6W3irMamsNeYe0fbSyQLUzwhou3IAOujuI9GxgQGJWFGTxzNcVf+6+mYEXTC 5JFueaEOSwjt/hEVLU2AHpYQuVyPVO3XlrwbZeCYfYJqkRLr2UzsZo1UhP1WLztOghYmIKuNZ9DJ R2MX/v0muivC7TQwk870qy6gaaJZ7gf88vrmcNpo1daGf+nEQsQb020A7G4rpj1PNeWUTsNwqb1P C7vXWKMPm2UYrSbpsiHpCopEg+YyErQsqukPLXY0Odgla6hzCykX3Mj3AGH180t7+1NhgwTphO8o uiVvt36iAdk78h0lxIxdsjQBSUC5o9CMxKY8KMwFN9fMy7mGjMl7YGCa5/r14EmnhPBuIf8BJMBN uKvthJD0ck1OetQ7VqXcZtavjPtbDxQzrKRO/mPmgD1T3nm8WJVa9hymX3mLiJdK4WWSNkDHMNEs 0f6pi7lbHJBSRbwU/qkYRRLH+HeOsD/wb8S6mMgVQTPZVIxozCJcXmwNNOItKl9xw3G3R+xkhRj/ oNAaNL6ZGtrNi+igxRAB/AUN23RL7O0sK+2U2Gv0Fxsi6Jn/mbwnh7zOtWOvQZIlVDCaz0bJS8X8 I4uAO+87aovYgB+mXAD0BCRqzQ32/yoHGtjQRNGzlKjh/Al+FnUL0Woehw+LzK9JEnEZzEwCueDc aEo1GjuyWM598jFsin54MHmXAEByGybfMgcVAIR/0Y6cvTjLwKCEmJVPGI58qff9ud4rco9qRq4g 5djgSs6sqV6glyTaYD2fkDOf5k1ZEPp4U1Ch82RHGAOUo0S+rsPtTmhWnIwrXa1A2tnwiwpo90vt gqW3UEh3YPhVZrcyW8UV2ALHpnv1inZnZh/e0s4ZZ6HAkWHxaxKgoePCga5ENfMUah4T9VHHiocx Lq2xevaEWJOW7plWo1IN1Wf5i6sJ2+IKIFwuk5iKnk4e24XALqcWlmzAJM0unjWrNdNZSQCNMwhJ 9JWiVN6I9HCdxF1wcoWkQCZcxVPjdMrtvu/A+CcREA9T0+IsJTFsLxcKA5C6b3sc1ZLmGkpsv1Wh kZt770Wc1W1A2ThMpnZQr+Bya71aAC0XVx8ioCD0BRN8lqSX46zBk8xM44OR2T7W4BrnMbCRwkqm pqWuJv+3mp15CYND0Px/bUxNBdGwWkuVlj79oo+yra1BYxdtLziBQ57P79ULYUigGKmLL+K27h5V djxEzzH1N1hz8nFcIDLya8/I/NzSjOZJc0osAk8z3ZOPQD5rt9BB2ol2L+/HMuSyclhcc6SAlR0+ fhHPUOD+mzJxA+Z8jlnCsPo78sjjknSqosqyBXefD42MuJ6nExMcqvbxOHYAgRgGLZKykpXwTl4h aIddHtK5VqcjnjEIK2EG2iYI18775lX6ClLKKYjcYC9m3K0FOrhfQm+0G2X0QHravl8npJ0uYFd1 b7/lF53T0Bzvgya19BS856r57odZ6cK/CqpsXma9QExMUzW+ZXpwFFJPIa09pJC4Y3QuobAaDfX/ UwCyRiT4VgkXLKR3bGZ5XW74UWIWShT/mKx/5KqnAlHb4inewqwg8SxZanDL4qos8cbfx+euTBLs 7Fuvo6lGhYNbzKkKuMVOAgOhiQkMrnnS4sdEuGcb+4Df6B0eORdBhCr5rsUkY5PjsgQfwZOgikNa rBrmEjX2NQrihYJcZtDegMZVWg6XX9p/kmCZ87RP7ygeOS61ymYGoZwVw3DNIyfIYM/bi0Dst1Am QRIjFlwCLx7xFFdRI7/mu+xLpa8jf+Kdkx2bRroGQHzOBXxidyd4AQ6jV2NaSJ+yifwfkhsXC3XT nWiuBr+Oggw2ucFZivlO9ClJS+mylEWV9eWQqG3XlM29pje4Q6cnRoEa8l89/bAhOsv4xz91GoVB T+XMN/AH5TddVPGl1h7b8NR0KKknbsFhlr+tWZadNQ5GcYCZzvzhSJZvByGP+CZDl5YUfZJrM1Uo 5JAtvMxJkbbZyin51DKsuO2QGrhexDMv1Pezsx1mSGq3wvPOOEQGnQVgsUh+Now3LwECFI5gLeoj pBY5CJQ4C+v8ppnfldlyespXhLhyjxHD53r71ejmKlZqFB1UQbMPvjvMJl+Ea75jgPE6uvL8yR14 1WsTry32mBRNleDg/ZSUq5Sr/Tf3tuNNl0gNSqJsj3W5S8u/9y9cCkW1chUqJbZac38csMG4qevt bEAitdiC+Fy8psJgAKbt8FasnYmW34HRgeZuJ4S45Ii5ld4JIyC/xsrhP/lBlasZJwa/5OyS0WnZ D8ZLXmyc2FuOWBFffOjD/kb9G3uYPcTZmkA2I3mDAv50bk8XCp/7mB49nGJ/ySzW4HLqW6Jp06sW +M4RwQlQMFzDChparZPWyzqkCm7CZJfxZUEABUSH/O5P6Ga9pgIPZoA5xQOJUHeu/HFUEC+yg5Wv uh3TmYOkEp15zPgjNkTdFmIBLanTSr/3qgaEEp+VioQP+cCbINio0FMNtZaPf2NSg+mMPvR5oZeS IF0QiZSy7en2PCm1MQWkonEi206rzpZHbeG047bd3tVztd57u6wEmQ/orhnGYlx6UG6CpbxAdjkp 9cLSEzMglNyjS7x+8bQ23nBKgGouZA8/4pxsiq2eG7u6J2fVhIG/4qxaFubkqebmZKmHOlVUwXrj 1MPwA9P1odnGV47DHzjSrc/lIJPbrhZzVi5WBj21/R9fAAF7kwgdhhaAHHg/BNXFSqDUQK2x7cfG XnGxNp9eeNgjZNgx0QsEV3lu/I3fLMvxTpNIXyeLOq4kmkQCA4zYVcIzT+bg6/KyH2qEDcM9svPG Kdu0GTeTHWAdL0Ok1tPramYawwNz8K+lsEUwN0xwKNljOYUhPaZgwVpenRtikFlln6OTN1gKoMbw r0TUodRhv9+RDMOfvCeoBupQfWmQvpQXgg9aVnU68AdlVoeDktsfvpklboWc1ytLWPCHVRiuVTtM ZFd6FkGvQKl/lELgfxsNgH+bc1mIggQrVnm8hjif7vjWwVXw/uzpNxmUsfyOSfHbt3wV3aPBKT1l +zs8Pe5EU3MuaaAOFOh8Lr7jwxHp31q3MCKmxpXXOVce0UciaXP+Ih/U4ZIP3sAbipGJeP4MKHAN 3LMnRLwgZMhMnVrnpSLcv4l3HOgOhRT1wVoFEGmyzEN0xSbRERfqAvpm4m78uydaFKPhwclI4tV5 ay4xU3LdHlFsBWw2nEZ7DbqLw2T9Pq2Uv+YguoSqf4rY6coxbAqiKtCgevvCMIj6UrSc3l7RNfhp L21DxW/yL/WqOgT40TRHml1JUtXHPz0zb/Ov+h0rKN99euVGfFfkDeX03NXaeB2XCwdlrbpIPWfA ZbMNMTCeh0HockndjIGSYRXmfAwFfF9YGcaHIwWQgBL8Y5G1C6j54KDVpM41z4i7LBqJ41vuO+oV VGY0IhlVdyOrkpxfLuJvzNrP3r9lPSQA8oXnHz3WGOKWHgTbKsqVrHAbY63JiyWnR6lfsytQyNtN ypZxzmpMkf5M6ZU4H55N8rxFkzjH5S4puWk30L9acG4rnNj+bWqqMe8WvRVJVqmARaoIFGE0+vUh pGowxjzOuYl1yK6Be3Pxa1RQEm0pxSEZBkZKU/W1yb06mJ6R/mMENl2wabUhWNiv3unTargTBDVc hP1eNfV0Cw40GJnIdAMBx6brCZLBJdDQuXRxkNi5glG3syVRTtUQ+xeH7X16yYEGkeCqRpWuiCIn VMHJab0koGZpSHUyK5f45knCkF3HpYMKtfblS9Ly2R9rQ9GJEbE4n7ZN7Zyy0S35GA3C/XE9mfnz zBtJPIIe0UzBYLaxKPi3kTk2M0Cks/9IE7jqI9vSKIBr+ZLBGPiJ8sC1PCrMxQT2E3Durg00kCa/ vb1HKrgXD1g3fcPyy17OwUd5t+eUFrcVsOfMrqhTqgPoTn+5Wxr4tuM9UdKLqQtkOH7zOpv9zXqq bbQe6QUC6ntJGgvYkqAR55Sx/G8BgMfZZHSGo67jSmKv9ZhwFQAKxbYybg3/gbX24NQ9aP3RMzR8 kvuiy+XF6oFYjVwPxnarEDuedMntiyhZtGhC0+duLulP3eUq184KDJys0jXxGsRDIYQ5h3qhX0Io BW5NWx+QBnbDs3xLY+NwQSN/JQHfEU9PtsGAzyZ1up+TI1+Tr8LQFCw1HsC9M+4+zeZ7vJ8k0wSf gocvtuGwtbqfC7wNgbR8/R2GyPehg51zUR6GDyHlBop6IOjhGUwL0YGnl/K4CiV94omGmR93Vu+E aOVtyrHAvc8b4Qsx012BIf4u4O+sraTtywIbWScNP/vv7VUOV4gCAAZieAcVlo+lxoeZj1DM/oBr mKELAYC5BOziD2L/bkVrQfEn5jysaMcoHk+V4O+5ZDBan5AvG4rqmv2jHea/hZ9LM6vxfrevtcml eGxtR0ARvYO/F7XZaA8wfRxx5jGynqVm7R+67+eRDIncxJImAcFNeTlgIr1NC/8ZAg58iU+fdDRu T8S2x+AqQuhf8JwGqspEPJVmx9grNvDIHeQJ/7o1RiHKIG9b4CxGznWbjIVyvxpK9Zhemj4PfJXb O3XVCIMkr53IC0qIaAhr+mhHtdXZuGSLrBsMIlirsbWZRRp75TfRgykr1dx5fkBMcz21WM1Pc2Jh hqdBjAFopAx6hzF6n+wZ7YtHk9TxEyk7JPbuF/v3yFo5uyHTsxXGrJbammsO7wB2wPSsSRFFtXgO k7O4M1M6G4hipdA7+EdC1Jvt88cGZRbQ79pxEpZbgtKOvEmfGokUFbkIvWEAIwz8RBjh7Zxwh/pa 9TK+9rF+TMNmlMmuE2PDqGOQAgY54+oxGx7DjFgJw6W4sz4J1IS/2adM+6Wi+cyhHEF3gmXyrFen JvH9CMrGD4DjnnWF0joAdmZlX5whjDbVWZA7703o/l8oIaxqtLsuwx0mBrRgxdR63UZbhHDUxmz9 sJxP6uD+r+lSsb3ArdYhO7yTQ0a7V+f2032aq3MFKWClRUOYMrsZRe+nIaN67HMDS1k6QO0GG7lk t8Eg9M8UrLlPW5cS2gH2pdIDkT/SPQAHJgwfcj9znlrJ9coUo1kPxM4ORkifMXLqjVq0dytKY6d+ xjM4hYN7+ovyjVlBmJFLIeMW3X3jddsUs6AacXh0UhPErSD2lQmfIgTTMrpo8ihO4M3Tyb2NKXnR +fx3vSxtiyk40YiTaFMYlO212ZJ4cfijdyphD1z12U8rVOyUmMcHJdEMcv0WziGwScSJwlDF3l3B XDd9oVJCD7aAXk7kC17MUtpYHan8vYv3olNQlW/lDquqxx7s+0+SgYT+mno7Zpc0PLfyizsAxn+f 2o4Q5TEwSDk7CIrNCw/a5R7xcVCPP+SCX6bmD3/Xg38krBDkQiTexFDMwxvizKu8I5euftuaOFhD 8X//Wm7lXGnZ2TceJsXaXzupzIyAX9LVZwF0A1AwRsWrOGCngBam2BbDMx/q7owKWgN+ytOwUxZA 5v2vjWT2AEuFEEYxdcvqaMb/qX8bWhZDmzuVagRdgg1xQEwIUjFdi8N0FypDRxGBqMuylC7fmgGX /Df1eVQ/1yT4anjcrPEGs1xESi2X6aObqsNe26ZizJUpm9+5SRM0uSTCeQpC73CJ/IwKQdg8/Fx7 iC9VXifGl3oNxSQ8snfCplDuVl3WQBkW38bhvFe8c1L3vhlQslEKi4VCB9vjf3umtsZ+YfJp4D6G /OAJQfdGu9x+2ao9vyZ8TKHr1GdioBSOurqGiCLcclYasQoCcURSH5rhZBwE3rOd8S2eZmRYaJ18 NFTRDY487rWM8mkNVe+9ppUR+Emom7kS+FvL/oQDff1nhPsBjB/vx2sjihlf0ni0qOnDFOpBIR8P gYi+Q8kuhWylkZUiSKuUFYvEu344BIMaUZagNJEbr1oX8Vexhqr6r3CC3fX92qYZo6pmapCaIshM XxINa0Qlp3AYsIpNe8eawGixc/HdbnXg5yF0ZWtUj6NxYKbfB6Hl0rP24hBbOwEfFIWcnbd843oq m8InrDUadWsAsTGfuSqxqtFeiJ0w337uXGXN6wOM/ZSmUYDrx2OKK3ZbKg62rk5yn0rI+Jth4pER +qpVyOjg6oXNJY3nTovzcsvFjssG9OEgKBM6NxsqUTDBOEvMNgYlFSg/Y0zb6fF+cqA2qD5W0AQ6 hUWOt16u1OynqMT8KX4S2E4AKpJVetgqiIxJ2dQVrQ3HGTjZ/N15mpj4cXnLPpdSvf9+/1Hv1r2d UqhZ6t5wY7YCJKsn3T6jH1KQ21sOVRT9gazpV+rQJZLYEt0viUl57uvc/tLkoi3gH8RgxtYqGtRw XLWSzdxxfnbInNvUgcmMMU5OoT1uAL+j1L+vgPqDIk7NtLTzmNP54suXKfVGA8v6UOA6i0WQD2nY VgguhUrBKx/wcHIIpZBiq3lMhtdFdU23UVohkiFgMirQ4Ptd4kyJS3Wi/cElPODp//zR4kT2oj3L 0xMBe5bWziGvO+IAnVMH+36G3GKOg8vwKITFxAbYXuxcfjv00dYY9yZyUoNoPMGwAXfq/dMx+A4s pp1yj01p4IGGWsl6LUyh4yH5g+ZkGrZ1VBCR/waI0uCEUuWj6oOKI2SixXxQpe6d9XRx0ZjFJ6vO n9hIqEpD+AkyBCyUsdYYL0JnG7CT3P3HAsEZMwE0XogCAcMz58lHcgGHyzkGq5EIxiSTIimo7Ouk 5YDCYfjhUKhtyj/yvyFZ0OMg/aTm1USw6ToCzMQDg4i6A0DBAK4U9mU122RHYlCCOBBEF1qizOwl cqNxzHjjl5cdKCQYgqRjpvBN39UjnfuKAdxhNatr9fxv3Dz/Nh/s2+3sgYDZbp/XCCCUdVKfP2fn 1oQGyTkESTzheDn5Q/OOCbso57dpg1USm9EmOA3j++vvsJ5d9kcX8NKsZhkJC4wn4zKww0cnvePU JKIODe3tFUnCXy5mVbeLkjVoZI7hSH34ng0jZho67EIaR+FBLNKvD5/7uPNXiIgL6X3dhqQSSQU9 CcAZ9PQ8fK0BkouI3Dm/oqIGh9ymCAYeXP9qkYBHp5N1sgIXQtEwW/Es3AV0+U1Bf0pimCXqxyAK akXDh0UK0jo0EOw+LetZePPL86TpSdAqwvcB/DxKavrbBV54nP/SHrhWKV0lxdXrx5bfH6t+4fB3 NXZkWPeOWWfUJPQS6PUkXuaL1FCggptQ4zC4gTK5fqyJ8MwJhxnl/yn8jf4VJTtGC0GKQf6qXtWf DOIN4IqRdTR2Zu2o+j/HnPQgeCiwi/O1ejyo4Macv6tRsDJ3Br9IIg9ePWxObeUyQoM5ZIejooho AN5xdEYE1nOn3wl8luyQ0gwT+I+LdmPc3BycI/Hs7WIey4WebwxCf2YRr8o0hNKmBq0FPAd0z3EB E4yKhIiEV4q3VGsvSYmvJ+EMbYl5fhGNXPK6pixaavwHWaxxDij3uudHSh3C6f1CYks6HVXF9IhI +0X6gz4ndxl8OHDojIP3pykyEgOZbhe5qY6Ajx0llA+JGjog/R0Q/Z8de5ZzMXZhYV8S/iLF0p+Y 5qjPTExVbuSSkyF6g7GIJsIW/s58qJ3IOKObDV9v2LMOKr6Ccd8DkXFpdlvwllaULl3HJVQOGU3E AYPFWHSLW5YOmEaJHz/3RjIVEknMiqDPLM0mxh4vBJaR7Ny9kHm3Z/6+eqUpxEFbEbXwQL6E+25d B5Ytf6xHLmXmWd12+auGo8tl+L0cSGfXCVX7cpcdq3JppKVM4G8cxSkh+niBeAmPnb7Ya9Y/cw7d VWC6HK3uYXUkZpZAx5LOmlQpzf7JtVy1m+obO9Pz29iUbhY1oO+aIycPHjGJjDkKtSxfEsUHdlpp 3kkQF9g3UiifUZcdxYTD0b6tH0bNwPbHWYGyrtLo8HFIiyztVPNjsChAgbvxqOJIwBQr340+OFt2 cfAl3CL2nR/vRqtNs7fjCvLTXWyBWUdiuMrA5Mr7G8HsjagsddThTtfbH04WYFrjUeOFJxAn5xJS edU5rKROOWeT4q14Hr8PIgBYRbkwRQ9m5+8Y/3knjwn4wGoX2VX6rdYUoy1xI7jJ2ZR2hZ7Gt9uT rNkz1fmLAnbBevdq47+EMLVG/agiDc5TbZZ6p1MUcWleAvtzAQEjkkp4lfGkV32XJPmIOrlLtFrU oQ6KaEISvU5d1PrR2B2UqvxmSVgdUNTNDfQQ3YSHa297/vQMJtV7DVO8RHI7Cdl4orxMZVMwuyCM jJbc/IHHuMRduKXfBB0kbgj+ILIDivOR8EsGzW/K7/4ii8T7Fdc+lv7GR/Jw/bM7GHQ+1/I5dIzf cH/EgJMD6/qjK7j9Yldcou6FOIKkYByncJmAKoncc6diGnOw+uKCQF80QJB+1Hb8t6n8CevCpOWG 82yOIoI/+09TidZV8V1yVufzXXuWYK8iRSYSQ9pp2T/DOhV9kHxoJWxZG7bkWa7vKubN6TQIRGzm 6fyZzf4jtr2kzWCvKGm6SDSEeO8umK4onS0h7MFBfiMjHsdrvzi6rsulqZFisX+QMsscWNFGO8v+ q6IQoQS4To4hZMXWkbYPgmwR9JeWZ4c6WXI/60ZggPhQ65Q5HfztH6dozexe0ZXJYEUAnWmYNlzw snJkn1mVyU86IKmPMyB18I8Ojm5xdBEF+i3oD+v+jbx4a1w4juzUfx7kjy7PkRUxTMBTET67QDJI AojK88sPYEfc+TlYb7vj3WbLcnvSGe8ryOiAwh2e439f5U3LYYMrIx9i41aNm5CrM04BYj8i0LcV 1y94jBkbZax4vZRDo3syk9/jSs4EcKtT4wCiJtMGy5VBu3jV5tTHycMH8dpQvvRng9vMT3Xrs8oe PkssbCHT3A91OYsXt/FROBwMEAHaVr9iOnb9MihvBbNjkuO10Knycdxso6sBZ10vuZU1LP2/PKjE Q9P5cPqEpyuBT1bbuNmiUgzLJm5LrvFCxelDZy105yicCR9BLjeo6/y9B8Bd/vnc6EU2ePO4yafd +UvQr7DXKAXa2eNT45Zzg7j2RsKK1Nw1nKuhCvW8Cok0RdEUjqLl01nk2y55YHgebA6WdR5fNX+w SLqXjDjc6lZcw4n3eJggwr+1tZDsFlEWKO1IHj9L72bvQXj2/gPYpmYM6bGAESxn088oF5whg+kN 6LjaNZQikYAZXyvrZRK+53nXdcSROSekHb8DIQnqzh6MafAskPoZblPsb2rJQSOl7p/PHrsBre4I IWv1cj4jv7IHGsN6ZI0AjeorDoGTyo2LGY7Z5qkYk5CzUc2aIOkubTBS5S2z81kUvy0Q7erI/Var XiFGFMBqm6el6ePCSY5/KJ1R9Q3rE/JNlZBSASOPiFZbeYPPII8E5KqtcCO8hab5nsiJDQf/gnMc B99wrZX3csa2SN12qHfeaoOB7/cDOZdqCRZHUa6kd6XwmoO7MbEAx/OOTyxnOYIzXU9pRWUdIkwt g5Q/NBKwCCmD4hLQpDIUu9BaIhD69m1+vYHqUqqf9oHQxVf5slx6qbpLMbI5M+8rO7qZFQFAV7QV tlNO0DVdMiqcleyILxc4Z03aS7MY2Z8Meqr4ex6lJfaj+5b/ootLCGvGnIDB2eMBG3hzEEgVnvRE 2zHtMZsBBJGuHt17nx5vdh+jPMbrRvGC+PZwUymTygmR8ocPk4MiB0teT6227Fop9AFpdENVTmy4 vlh80aGjZ3m/PdAgibTbwv4zKeFJk04+CCIsIy10v06muN8cGW4v5n45EZ5SSJDFQl5mklJ5xGk5 RnjZZMpPFpUSw0d40gm1Lm591D7Hj0QB0g2eYJygzai4Qo89BIwit96WThbOpAmiZVNVWSm3O5Qd AmQpbXdQYCyE/VNczx6A9WO8EXvF9Db2YoCH4MkC/TrQGMHtlwxBCLZhV0zp2lvOXfqyxqQyICLg FYEaa0t/7g7q/ZRHOAY9s1s7+XDmYyzGtHH00KErKc/oNrISOSGw76qtkJYN8IuycFhOw3vzOnIV Q9TXReKU/oi2Cvfc0ZEpvuYYU1tKUSxFKaUsrjHzNFJBWjkIbjhuammJlzzAYSnybEFTMR7Gb00a 0aIoheDx6bQRXtqmPhYlzO1oQU5kM1EeYpo2+4sWXQlgLpKm7JvsRcd1rLDrYvS+qaqKMCmjscCw Re20DNyykEHaCTCVPq2v/HdVqVPOfbkuuKhtwA9XZ+k4Has39UHHnfjlMG/7V4cirG3gsmEFPVVW MU+p+/34psocS/TDuJpcrclORFj6MFPsJ3QQtZKF9OgIaGqxxwD6dsSSkmywHD2ZRFi7xZvud0P/ wuTTe0B7JX8Ny5AmmlRlv1lWMxVa//yZomXXKBpA5AmIkgVN+zsjfRQfgUbU6Z51fuEe2Wtzz9hB S7vsG4mVbE/jWmffiPYsxA5C6/gY5UQMbf/te7z/nl7h1bnLSNjh1DR5xN9jIy0Xra07oRxf/Uz2 i39SXXlohHwkO7JNBU9eK0YI6UdqxX2/efqWWIA9xpxrY44ae6oeQ0HpQMbQsIuwiA+ENNBQOLDM SRH5/eJu57PN7P625OSuSKhP3QnOyRtJupIADcahsMPd4nXt77D3x9gcnVwOOXUN1Ub6IKi0/UgF v5vP54aX3w1TC9F+kGGUQEul/43jdRNKzWp/wBpDk4qq1JE3pHxDS7irgZWeAmZhugkXGxIN0tDh HEpLMC5XgIJ5+12gMoxoTub9e/axKBvm8sR5t2VOisQHJ8HSLiYzxEfgEbzxLRq1ucrC5h4fJYh9 eFt/9lqlGxmz4mz6PJiFSHkIfc5gEKSKExMSwlBbOO3wQ+aCbAMupYKgB1HEE4k1ocOMTgo7xg9e KazLoWsUpy3xQhPYi33IKwal4Zzd00AS0OE8jF0gvMrICPD+WY1BGrBP9Jsh53M09gdavZEGfPXN Z34WFRRfj3IFms5FDgz6XInSMytpE2xevninxzeqE2bl4HjTKcv/q1rC2+wDBCzvcyNI1IoWSg8c hjzaSrl99x+XvthbmKg0W4n2FN60VMTx/tATizTuZPGJsE/In4CfHX2faYYrTamyhUk5l4fj7lgQ IFeL2XybxxkpKIGEOBZ+YpxHERqO9g0hq/jXDCDaXP6Y2IEY8RbGVdzv1w6pYxEc8NUoRUlxuuMv njUQvsTLPHGHixN+nBLVKDIqMeLh3rzbtP2BcUPQ+mh8M7zKLFc3BIaOC5ZMJOzwj8lqJZy5uwA9 w8Id1WWEzGjMHaieKMiieIe286uAF6iCqGfj4USPCzlUmvPxhGDBKIDwqBZ3W8Gt0VAqUhShKjdj xCl61sG0kpFrQ4Uy9gj1VNcEXmq7csPQGehM87hsQdc5+iOdKtl3N75Ti+O4kVlfuG+EEI1rvWiz FiuoYWeDNx/KRWOrB/3Maio7Qvhy647zhxveUutyXTK61laSPp/+Eo4N1UrVBswhnkIJvwsEtmfC nBuhofe59j8RKesUTJiUqcfchob6vapYGyv3MfRkitbK+tKV8CbqnkMLHzN9VTNv7jGjPZE9/5zY S2D0WYtA4TJuPVOheWm/V66hNMPF9y+ZaX5H7bcnpXmQpyqRZiH6u7vqGuu1K1gav9BMwhk3wpOU reWiSv2dQcYVOs8GDt11ILAoSKQCEnpIwY361wy/jQ7k+bAvYpCB7vjR9C5ojViTgPUf4tKkjEQ+ 6cg3Banhnrw25wJppNWhH0SdSxEyt2QsKsiDU6Hun27b7F1Tm4GekRZC9xFnwt2UoErAejeEDek8 dHcgaQxB0gGnz0cfmL/J/U0PmZR3AAvP8D/GWQ0XcDMV8ft2ATVrmOX7Ry6HEAni1VgEd/qw43iM 9JaIutj3bPYRSSQDQqZmkfNf5O2TH7aIBt3K+89q2kkCFQASaxj7xCYE/e+K8hKrwYxv9a60/6eT BPkCLbo5e6/2HKU5Vlo9vsrQDiwNEIEClmYxCUB9MKbm9V1pm33ZKPv9CqwrlpPL6GhopOIHJseM blEf0HLekC/zdLUDLlTpD5rApl7jsRohpoI00vKAuqmIos6hfHcG5QrGM9hZ8/jxu7uQ9FWAbWpA awKB2gXFqMciRsb0IX0wUO9VjwjRU8e3ZrCpOWoachhWl4MEF3XvUYgtnsjx2ZZAEzTM+8bDZkOC hgDiwK6+94uMe++FtVHw232Cy5d8KHx68CaExShYiCJVfevQJPPLP8NuHbJikSI3zZPclPszLDri GQkt3ClX5+t7QluuN0ohmfBWU5yA26BVgdFdh9u63j3w+F8D1xyvFU8ahc56pX/R8okd/IWA3qzb 9n62qr3q2tNEtI7Im1dUNeIUkh4jXZ8pQNc3lTHdXDy/d50TLQPHC6iLyiQ01k7vHiqL3nXTTuqt Bv0wuOFFStgxftiO7vf4BpTimIibyx4Fa4EU8qlx08GqXZcOmG7f3mhdglW9Volxy4tDvPK3J1iz qgP7PnBxYaRI454ImNSj1/fmmdIJI7Y6Hj9BjJfg9EDkhuBuJfW7x2YjGNx5cFZ/QvZ27eLryD9y SLaKw8u5aV9F4jQ18H9AqBJAiXhWIzaIH+NxsM7frAox2glxYFQ3NiihdRbpNSCUr8v5nfPWoREZ cqWQPB/PlvC8AQmNbtdQzM6aJaNHJhMIoG0hPk2cmwvDdai3yto5ykf5ZtkV3A6ayXIYInkeR/zp jMzZYE1d+TTY2zK9I+mNhWQ0zfMcTok1sxJ0eJsY65V64raPUFNm2h5vZ7AcIBY1TNdNI1puy2Jp 460/4JXv9ahK0099VKYPYZOb171LsJ9XMciBw7GI5No8/d9xWnnYH8vuxAJhK4SjbueFw+Vw6uzl uJDsNrRx8oS5pIcHz4joNeEwzhZ+q97C3QhWswxc7ZQncx7v/JncX66AgmYN5YysqLSeXu1DmX2R Cm3Y0BcXd/DYA1VL5rVtbD2ADPxfGMK8TJc1NgCWj3exYDy3Zn1XEka2tAejZdUKTaPVQ2pj4nDA OjzRiRiG/gsEZ5Nk+GUi8AD2g+XTgpfp09krPr+mvsFrMYqJenuDh4r1plTrL2coUY2gdNgrs6An 6tTV7WZkqTaK/EaB6/2xDrSwhTSUC98TQxZKhzrqDFUVIH+jJkOASGA4hDtljQjYLZB5WemotTVZ lHpdZ9SY/XH+ECtBezX8Fif3udWIZCJOr3V9CXnVfTsFQDOUMa38jypQcNUxV7gASEgHqWPNdA5I NuV/sXdoX/w3VZ9qu2/Nn4a2KH4KsGZC+r3QYwBXnuAwb+dhU48DZOKDeSqKzz+UCpIdkzUMguKd cBot0BDwyXE62aEBuq8VWnRuJp1I3WWq55qQPvf35YIzyluLKqeZ6xfKUUK2sY2m25ZqjbOKmOdr r4UxdJr8IWQeAVnU63wOnBSCBKi9bTzbMUYScCV0bDWi+0zAt1/gcL8XMd1y98IBTrL+bxbxAqsJ UaIcbYeQRsXoxpupCDwPGbZi2XUA4kxv8RJ9dPFpOU201mvLpcfgGDayui9DecC2tFSRPCu/Zr6A oje4tbKEvavGT+CP+69lNC2TyAZntolOS8e0a6zrA3NFzUbcd+/hBCkKshprkIqbxeXIFbmvyUg1 nZWJMXVK2wcpIMMpfKj6YRg5ieoWUyoPc1ORryGn5SitNAaF9osFGdIm+dkrcAa9035oRM7GXhhU 0PdKHsVmMLE6Qr0fSkMqvzp29yDZwDVVKmpJolP7ugFk1hAmnNHCspM6uedaIROfBT4W4gzd1KaO HjbayywBQSGlCxP7oeDkt5CuI18w7pCo9ORotUyCZ4CtLPX5EoaQk4XmcQe28g23kCVOK8biNbkQ o+JCzFFK7+sa7Slo6QXg3YO5aA6s2iYS9Ppj5FWqU4xwkiDXd/+x/mCoy7bBb6RZtN6WPVYElaWp d7/emDMy6h7HC1HzqjNWkd0TdKjnVfLvW/sw3MkHgo56Srzp1WJktPyhcfT2is9MIeHvUIZzCRBS 4nGylD7YhKSlLgb7BdxBplPrY1sgwqAH0184Ap/kq/r4tPrfjQ83/YqmQ7ie3EKm7r8z8TFQdlgA Tikb1wN1Xc1S7F0Zq1l7Oz3FqqRjcI3AE+vKxID6a4mNZlRJKK0cJOohQzWrdlsxBZO8QtlMWK5P kJC3Fipk0BiI3E7SFs5AUkNVQtr8igOmmfWKaW0fK+RMTvs9fXOMlxyKEXBExzjFGKUuJn33O6py J+P2Wgpraf7gd9Bohpn52HdZgMkSuRnA7/ICWdqZjsjLFbyxNoiykwsFKxyMM3FV9MkpFvPBI/wl 4khrk89cQ97Ne24LGHvbufr5/wwf3sfKfn3e2GWIY6LFjO18f16djyEUWR0ZX88iwM0aMtvGxul9 +8s86oMU5mtdT2KejO5oBoTKLZ2O5WRUmnQIddCd+VAvX2cKx+VTmucwiFFjf559W52EasVAHqCT C0EqCI3YoDozA+BzOnxhtcpM4LkgwHxF3/xi7LL0oyKSlOY9rbUXXi3eH4WeFPgMtEXOKISCcOmh XAIii0M+poDmQysm5Td2lAjIC16Y0CtlDCWcQwkW4n7RnOm05bPErB0Cn/mHkERC9XHWFgN6PAdg cs1OHRdKDACOXX23egCxmdH1aalRBg/tASHUAjDp0w1cQ7V4HM01rmBvXuME9QcgKpzStUxNw1N6 FIetXp+khvs5Ggrh/0vBi9Lpo+Kcri205OC7SAdfWUzso9jUfXKs/RvUw+zhecIWg4f6HIIT31ZH btBm+tEYC7GT+z+xRf5ZNI8TxoNMj6oNb5EURcnIUjE8iRAzj826pkaY5JEUs3PEUF44P/+YTk58 IIUUqlnZpSvIA8Ptqv1RELWEj9f59gQdgWxqPIGRx44xpe0pACgzdd6sMeEp+C9JR+w18qQas0Qf xlp2LaysBaswFGZbxaIiPYg4TSmkmgYr4MYacb7yDtvI8f4a1x/G3EPnJt4FpsMxg6renM0wC/P1 VH1NWo0a5erkAtDQagvgmEO5MaNJEgxjLXALBo8msSKPg4YD5YJ2CkwIcoItdIE5RV7YHOb4/F+p H9Qwlg9PMJQbkLYgmaKkEIY71U9xaF1Ucj10rqLclRpgmvuivApD0Rc1yPjLBqjS1aBbRa5i+nYi BbEmCb8fX4O16UOaKRWZIp+6kOm3iJFy+p9Gj1pAv6qXK+q2e8bJ5J7VEubRRvBf54xuXajLVTBj QSQqwZFT2S+YpZ78d5vCDYsfVsqpIShPQ56V74S1fOFoye5ge1xUQSYy4Xiic9VkRFVqMdwsUZta VsnRuhqLl2iEPyWLWvjoDJX8tstaTy8BNnt3Gv+EDL9bj+pY7Vp8kj1Fc/QHYaUsysPNXCz+TJpn iaVObjkKzNqJOnJNZOfxG5HWr19w+ZLeMc3DJi4da+PIQkXNpHk8hy0L/BiAaFjNvGtkzSGztDw9 HO1KlAgXtzgYisOZztdIjvU6WPK//F1drzlWY6lY/TnnzNrM5glGF3tGYBsOSUEK5pBDdAYry2eI A7zhDbmPoqU3F6NYpPAwzWXv9j2DvEWWKTKfvrz8LTz/HUDuSheinFyoAwpNbFoGrDb22RfHaoHD e9F4Y0Q9+z0zZcQXklVFcGdnALozi53RTCn6CWS8rzK0dHsFwpCxft/cys33UkGr/PvCM3xYAQJS 3e1GZcZImWozgEvDixu/3KffCY38NJ6VSlElaPcBcvRcL6ovi1JRsFxSGwGK62UGBKBsqJ0Om/sf at9UHCMoXpawmNVGG5zvpMGvKpf84x2AwVmwFNqneabTZk9+Z2RJcB5MGxUkPjn/7fXA312lr9qz cE+vksp+1MaJld7m2ouI3WbOszbFt79bQkUGdNZaYcQaEijp8XAhn7qmTvUxKQi/N7K948MjgFmc RPWLA5VazmUbSmXhgzyr6KEA05agrpDQq1VfgzqSEFF0+PmZ4u0euQztRK1VRy+/WbMBj66QnNXo 0KmHEmsoKpt6rpuuFkeJokJtBU8lNWeZrbNyq8tsw+eOHC212T0jWSejoXAXuY0WMKIOGewzbi2b TNdrfXC6YPGd364xSu8DhiKXLtOnVkmqaNuXTzGRiCwIGpgBFfZ3OsQzf2CcdAH1P3bXGH1lsMis KttxKECq+9AGVIiLJJYqmeV6veMjYzx9r+2z7MpUW1jhvgw5x0MbKqOhIB4j721DvJ6H5UOIZZ7x BKjv5cSTCFTl9zodmjboNIpRSLTCFVd3/YYqpkCN67BY4uTK9rdjhb4Xwu8t5xZ2mgWvLAf1A7S6 PXlZZkr23sutW3PURz5GXrnoGKT3kz215iaIGM/Q5Z/Z9kHrrhTgfU7JZCJtUE+4XC72/cBLUsRv 70po2JSkzsyjz0BQixRhr0yY3yaTVhIHuubPEDfxs7UhuxOQE9EPjmzSfJo1/StKztDr8BwkbJBW d9vGMjhdR+/mr6uMhSdJzGmr65E7Fx+odWB69OB1DZrThPDEttr/MFZATENf6NuqTm7t/KdTyKH9 CCsCZBKepsO9dBqD5CfZ8pJCqcW+PnubUyJ8MFLGp5U/p1Uu34VHQN779NMEsxZgsMGvOLFsXkK1 sNfOcTMb71kUsdT9e+QMaJE4psg+hgmEwvtb2UWCXVakebfBQUdMqpTbLp75Wt7qM6fXlFvIxjIZ iG4oTq9uqhuLvKBdI+4ZE2+V7l0FiNpof0CU+1HE4z16+XISQ5LdoIHf7pefVA0AcTgPHwjZuind HxBX3qpvGBXC4eXndNlxDuyyPN45EMj9CacTgA/s/T0Rf2AGk10fh/qJOu8xm0Be0U2lIwEnfY5p r2HbZyUtP6mShFoZBcytcujjrUM4nAAyL+W0i0H4nmhMaHREe6iLG26zWTwyanYQSdhO068EqkDB ieQm+NzdktdQipqhOgXE98AINXR6ftggjUWg6DVQG+fOJihqnar8A5q6kNXN+5+8Q1z1GMLhaorB Ba+0WRjvl8R/S+KwNJ839lolb1UFST5ATkjuSe1eGZRniLoNbu/0OSYSOi7X+ylT32Ei5YGsnRRQ Bg6hLqQnbvgiKObmpQVOPnOwRcD+bgJk9Z8OVJdKSgebDljNmwefY3VPdyZcXha7j4hx2fRzrohK yr5i6IoL04kjx8axSqc8u3bxXWe3+Kr3v+cRONAkcwdYBY5g23Xx5wutjCOaBfXwGzm0F9ZSQhix Ngu3vpS3u9HZXnZXVfC1dKtq3DBzWQ2h2tsbIVs+X4EPpmnZUw1zWKYf28Ox6L8g4u7fLJao+gaA RPu5oLtcx4Z9YFx1a9rRrL3r54wYnqFAtIks6Zwivr553A4GK1n8KXZ5C7frTkbc85KY3cyDhpTC h8EqWnhpjvPHAMO8gGsynmZ9Y2HuKAeoTrbDyvSgf3+uixYz9QU1bf+nb5h/+rAjFgpTK3l9kY5j eXkq64NO3FKSvGNcsOM5wS/KYtIRHEzzdLzbzVc5fhP0iwB4A7k1++hJpChpb7Svt4H+Kw3LKSCj u/nEhyb9sKz1Xq+0eUe34lJGPrlPOXbUKFBnL8s9J4JBRCVwtB3yBeqkNu3Vv2Suke8nR7dfZD2V vRvn857ejXVIit7mXIjOT+wtwTOQSQqRAYpIcUxAXUB3I5fAZkAw4Ozz5jOujWZcjMbfReSQ1e/N PbbMr00YF32MK71rIYdvaEb2LDpVFjUmLBdoHR+v58j8FhLxQdDM81+tcIPOxqmDTrcu+zGz9dg0 v3hCwn4HbyI21kx0ObKAJPUM1ijQWs5QfYEb234LA/q2DWur2Imee5nAJzluVVqRVFj+p7nTZy0z cryUYvn2qU1C8XS5iwpfwSG+fPI42UPuxu214g+DaZvswc/irK4vYfc+LNpGmvb3BzwRXVEzkEae H/HNmIjYZfOcasVpWprO2XYZmqiL2AWT4d85JzJER95P3pJEBtHQIaPFQKlsDGGj59SQawb165bV L34N1XX3YMzlVa0LI2BiN/CuXxNAz7SpwuZCL4+T+w6RWlSH6bS9N1/ZwiRCQ5nOsFxTgr4MVL6U Mibk0QOKqVIwS0a1UtpQVPQa1siJOOkOryTdQrh4m4HIgAfyczHHtKFG3lrzN/WiS+a1JOPqiEi8 NGvgb2XcWQAcaSnJ284z7hD0C6xO5RtAkKj/tGMOWkjzd08qXTC36YNPkw5U+VcLccXNhA13P7/M I3ahgOH/+EYSf/+MucV90kfgTkQoIrXibP+Zd2E2s7+S7gaDVoIHxpHkuzKLt554LgZsdwKyZBdv LPNfG5Dq+FR4vyO4pgO0NKqvtG73WnxONK8FcdVWE7XL457HGV3iNDfPKEOKJoBHytgcmKBfbMIx s47HlsOoCiLycclDLcao2/2JLY1AZVA9ALL3+T3oTuk0JZR6uFn52D9TIWzHqkLF6oKFPml2cvug x8zbtf9BuTdZO6DHpL49YKiqTlEipL5BQXZCy6Y3pApkETwjrSWvbwj7AfKvr6698IsJfCrEoe8T TXK6d5/1zJBL6hlSwC4LOu+tvsX3iuy8A9bflyi+RQJ2OjRoswUT3JUkssp39vhmWolao2ByOJRx gbUcq8XrtPnW/1wCRu5nzjZCS2C7CFMkupiqdmW4FCMNkh3GJxroPViQMqOEBRxb7tkCaL+IQ1qK rComwpOSU9N0eVQK7SDmg1GG3TJuXM834MmUOdrSOJQPc9gTn6tsDawTmOZ/6oA/nD6dCpzsjyLU 5uwkSKGSqApA3eoZY8b+w6z/7ALmTN4b6Mr/nozVdzVN1hNXnnQVA/ZYj1tT9KcwZfvAC5LqCPxn YkM3NYEx8k2iHuhlUlYUjtNC+WTzSmU5uaxcWay3YoSgvu0znqshJR3J8Qubue7wf0S30d41RigD QzJ/c18zVDHHa2w8oKCV2/mKkBmW/dIUGxRVkb6mtBEZ5G+akHyZs5GoJYR1C/Ivk7zKsEDBw7JD Ep6XtfRi3OJWj1JSXd7OXDzl9tNcEpsHpK30v7b/gja6PhoYi6hZWMLBE5xqzIfP0oaus/CtFtXz T1rDfaPoK/hT6klnGnFd4h2hzEYEN+6EUiFD/O/gFbsgyzRVOqjruHLNpDkvEyS/FK1zKqBVEUts wrC2ryYYtW9TGm8PV2o7VFR3f/Q8HyH75gDxBezB9f4dQ8Vo6Cdr2XXeSpjl3VnMnJwChNlh0VQz NyFeGvFt+MHC/GEopP4xh989bwM1IOLjfs1qOXJqsdXNQ2gJZqIYNlgcwk0/ZL7NvtCEh7U9ma6h YaCNBCazLrkZb9qBwc+isbQ21WHBdQCFIdR6L72SdTn47Wzy2dk3btU+J8RUIZlksNkR5Di1VWKP hGTDkjIh4y2QVhzdAGJfarPXIaZUjn+dIv7NMSRNHIFW+DGMOBpYz/lnGPnRK1SixMSA+bdFraWN ZCHvlJoqYY32xbaXCcsHPYqfe0rt/b+XE52IBnxr6vGatwz1kYJ7lgdMuEumLoovIwnEHKgMQvrA NKP42Ro/2EDp1v3MssI4zgsPyHw5tD6eGbpU7X8bEyXMzgl39wzIlsrqGJnoa16ojjTxiA3IZPfL yZu5nDlAN1SNIZUpOc8u/5x9KdWC+a8ddrYXZbRYnxIAVuFNntOIUzJYxVXLyc18hIuBiEbvizx2 5b6hymph/5/y7ks9PF0PUwNjLiLLz/04feltKNx1kSNVJvOi/PioLXu2shh4k5yxbXpe5ecZZIP1 7LHsxRPgBAGgnIJmlDVXVoF8FMBZBsqBV4YG3d1W08rCdS5/+5406ReflYuMZrsvRUYEZF0b9HU4 bnsR34Hy6rvMdoTV50TwKKpdQLLDic7/N0at+8n0sc9wKXAheegvPTonqkit2wT3xQ5nPwSR6CkR YayqBa+X+l7erABg7xf4iDDrI7/wkZTfI6Izb69cTNQtOLRk2J8zGcalB2VIwRYV4hZo2woUYodS 1DzMa6vQ9tN7/3S0Ng85kMgTtmlHWE305EKyGXG0FtTR5MHa2tVLfOVsZnDeWJgi8zvESgB0gGbo YmeECtcQAOUzhwfYvGUHA+05/Ju2W9VwBOquJVPo0eEUoK8CoxHYxw+T6hAk4ylPUM1DIW8oCYAs muzMsF96OlHoIsz5Hq1bvoCFmTg5htCGykuUnx33DY2XdjIsSfHUt55i6BVsHOx0q8/vXJTVuA21 EhlpZMz1VN8KL1FiG5zezZgFjo4o4/pSQ6G6GGoD2Fo8S+h3I/MMN9rwOs0ZjcoL2bf3f6hHS19x tIUJfKRjU7mtkP0djA4HnlkzdCz6eBYtSUistkXcNYK1Y4lMPgX8BwRu4J4o/MRabHh4lh/bj2nS a8ejGoMWBkpnPVl/4Y87oGSC0iNRsJ6yNPa8Lg0gn4GK3UP61O9mvsDJFNHQfRTce9dsmov5ZKZY NbCbCg2zOLjQJBHvV58Or/R+ijygVZdinfRoKGqihkOT/BdYMrksUcNEsIWb7tGwS59Revp5Ghns 7Tgpz1TucGsKHlXy3hUyCxHcLUQ1T0KeAD+d4sD2Uei9iHSxgjv4IFMYixAaUTjSbWDJScoeQ3yC ZzrJ0j5Tg3DWRp2e/bsur5UaAistJTGFyAfOj+/YgGOWMDoxSXvsPOlhwIae3RdY2th0pTtjZ1GD fDocpisYVfb43o6Ekqkn+cGll1tBKFIuWjl5tXby622BMCxKwHBm6uy+yOvwqy136CxLVwoQOsyE 8ActajkSF3ifbcvMi2+Xj0eSJ0adN25Im2sNtluCthfRvqQpLyPiQX4G1I8FfH7dgwl/lRQY44+V mGhYGf+TqQbPFLSsSytMCZRtWE+FEfm3cMlgpPxn5c3r68gPR0m6msxLhwASrJCXJllGXUTQQ9T/ rg7uuOfN/bvmOMoIFnbW1GfK3ITdWA8ScHXUMSQsE3htxCLN4d+hnvAd1w1aMOGG697BbwvXGruQ mBpqHDq7lIYJLXnucK1kEtMjMYINC0jimNoOqS4gB/qUJtg6rdYBSgpQCPWIpOSRATSIzNj+mp1R j+j3NhzdiPWXFsMsnG/aQ7kWCQMQ4zx4bzIgT9pCwKXCBafZ+h7hIThk1QnDrNwgKbHcez+doJiO U/oRYu8pEUeRukQJWWvKGidqu12jYrnJtFs4Vik4W30n07+nL+HvWuOuW2PPv7tyk1S+kE5LPE3x /3i2sk/3G6E32UkxyAr8pBFAar/ypGc1x1A9e/ADbUxVrw6PFp1Xyk1t8fH+QSeeuAYu/gbSXbjj MulZgZ9A+FmBRHRSoxsUIHQM73yWHvDQ2QEFcIrKYHGBbxvqusdzIrW78nARHYOUw3I2HtNcygJS R3gPU0nZRgKcFRNun+45Ka6IyS8ZLxk/ODnCsjyYYVeuROpVSFBaRdhxA5so5Sr7Y5yPNuCs3OEh piGEhUJrm3EZCHeUPnbwW/yznl9nPOyMPuqoWJ/FbqNWhaYWLdTDmbCJpliOEKlzIQWY3v6CA9Q2 MPS67uqRc9pbhCvGTRAdzl0c8vA5ouEkGaC4S03pZ+jxy+KSn09NJN88lUYQmJCbvnR3q8AwLtNV 4avEXzmtZlmVnspnsZhj9ZK4GDT3Se004VPvdWbRU35+zpMoQfoNvv6CtO2mmgotIvRNIi+rFD3C pq17sGytj+ONVumfArvN8DB2vvOxachmy0AspRqU17srxP+fnB1hiUjmwPb6ax/CYlDgyII5F5oa 1WJvZXM8PnxtKCLIcNjS13CCRzdrk0vqu1RGp1oGNJRnGksIhF6T1JGPafeDI8BjNSztwzlTNXFg qFqvCu5jcbT9S92nQEF4kKlPMsy02WQ49U6m/Uxe6CWez5FPZDcpblTwD6tVZeCP1LUVu/Z1tArM zm5VmpWIHCi1njezbdc46qvNzsIN+/f77aIVWyaT+0ICGPZyL5+5qVgiV11D6OVJswIaNtsh2G+c 6Dv4Joy5cMygQefFR4Ix/sDdPx8YPLFecesVjmlzH77KGgYmUvs1iARC6kly1wwHIG2LbtQsxM94 kTRg0KQrMmrUD2zR351LRQ1IuQpdW0Tls7lahK5YOEIJbLpIK7Bdp10ArzDPaioYpGnOlHI9hHPR ax5LejpCz9KDW0sMNsljsnBP7PSlgl/Ph+QvmY/NxddPnzYslzlm+BOUz+iHIGWqpZeOkgzuha2U syb1EQUf7Gt9/A1zLkTsdD8qy1pDvmmUDMV7Bq+SS/F0P8u47FC3/rhN418m+j7L5SK+PeAoV4Jr ADmk78SDOCyCgqu6tNuC+Hq6W2beMFsrRL2VMCA4jmaA6f0MWFf/03U0YxywBQbNFUbsMc5vbHcT BiFoWiGebABbMBOsjO98chUd4lPBZGyS+A3yNZy9vStcZVHP9jbXSKyAf2LckcKDtPYFwZAAzLFa Zli3L3jmCRg9tZxzPbYEa4zHQjNk+sFi/O5WBQB0Wh9i+pDb+WFsJifVnyP48WcWcu4YzbvWI36+ s7/FMPk/ldDnAq9GFE9Ab48/k0VWKwv/q8NDEKtiI1SuBzuRbWtYRRvBazWw1G+Zu9knrcYGL//4 FF8mxFiXs4I8kInUPAeLEF0y9CzgfsGw1Gw0xkcLm6AOzOu9Bgv3xGas51CMKevnQa2TNJR6WRW4 dahFY8WWM6WyJcacXjFKQfwUGD1nGW9DeNkF2yPJ2DljvtGlm+SArtqT2YXj+E4TwinUgLMe7AiB lgp8Fx2YtA1Q1s9fwJeV+UvCgaG6zHA0rCj6JXpdBUa0CEBrkCGfMUlqg/QTWZRmmwVLcmW7VkYk IH06E9W2BzJ1rdhsrL2BEQRj30KoDyFmt8BLiKxuAozuW6yRgoIctBZqfecV3ET+YtXNMKaIT3Z9 lYKDbkDf92qRyKa89/3G3/uy5bt8dbh+vKJOqXtk56YR6f8InMsQ3cuB/mjaAn7H2gCZ5BU0oB/k M2TGV8M+Jt4ZHkUrNeXd2x/EYcZAPJ5nMc8pitDTAmT5iFPVxvZwiXotmopxgcWw8LudjmPHAAZg Vnzf98H3kMpaNLOyvFoxtNeYF92xCezJVcxkOZvpPcpOPdFCRzQxYn9rP4WMKoMN4FP7rgjRZg4x Nm4QS3NN9V1Hnh+ha06MmKjT7X2yChCwBT6IKeYX6b7ledCmEzhOxSgsA72oV1GJZO0m8+h8evtw y6hVMoQjTJAZVMuobECzYbZMw7Lg4jTj8X6q2eKPAhmLI32F6L/8BYuSKUinoTYadZX3k1gdRucL zwKmikU7hAmKPPx5HMiI9sq3bcxZ4AWdmSNmqbn0xw366KI+1W/wFwyv1jJxvblK4mSHUwQj+WO9 jX3rtHd6iXreNmFqUc3gT8YY0zLX1aUDtGKL8QuOs+hy33aWZKw5U6ehHZAZu1G8/eEhYv6JSf8V zgTYKIolpt5IUCM2KZEq5RmOGvagWldY7fEM8nsEJ0Tysi0Qg1lF1PIUnc3FtWXgcREOD3XCgb+Z 57kRz+H4esXTqbsXx2jJjZiv1xbBPhC212awqtswLDBevp+d7kL2n43diOKgZL6XqTevR52p0lnM rSEA5s1M3kWZIO1R3F+CqTjX9fVwNfNUH32hu4DAKHXCJO/QU7kFQ+FYCxOea6oXxHf0PNgCsVAI O4wlL972TXvCpYJxGekY+y6maTYpPApG4KWXBiSTP+o0MD8O6Ba7xWdD/3YvVZSnl5H3XamhjKER FBRJl1gfqfPXq0LV8vycKL1jeSAbnwnlYu3mPuKwbVa2PN8cTaa9DEoSo2210gEEHqw4CusMS1GU QokgqLb1xwjXafov06OHsoqxZwpmx+GKr3EjAbTrJSNJJH6Cs77q4adnjhYXrzVZqup/ji9AvUTg WMD1KftSDWLhl2x083nYxi0aPP3t9Pvw8UJnKxcK9E0nYzQ7jshW+TKMY4H4OK4ZzGhFKCcQpRGF esmtftOmGqo5AmcTY3A5tcyWRulBrvqJkKGXFhJL5hqNarM2CTvtRHWsPLNg2zZV7BayT/0gBO9r cHj4ivPsNlmQKWQIUkJrM9MIWmag+k/MlTVIOw0FoHX6bHOr989quqfhVlSIAPV3aFgDHqY5DJPo ZTvXqgOlplmND7hXv30I/E5BGPujIqBzPTSeAykCtbdPVpPMJlUVZmVjkwBIEovVF80E7p5qPNcW mAg+AFkm6ooMJY1O0QBMyS69kI2Uz10jBiEdGqxbGGJJDw2HBIG/UnZUZm1t/S4Hhu37fEXYKiUo JL/jpKWxe4ML6ehmFJBqe6d8zczkLfr+xDCGN49iFnAGREh6G5qaNTMMJBtEdBgphaW1uY6WGFA4 N+4AyX4b7llvGZ7I3X8rYdfWEVC5e9ywHt+IV1RcXfwDAjvNBWZc3iqYc4vTnEhp1LRZrW07bEO6 sIhDzBGey2/yi4wkrCKsb7IK8gW+TUgkA+kISkUDP7bEoD5Ib9XTupmj3xdCrGKLrbBZPZcwYMwl FY2THiGlQ7qZ1/bLpoRrJf++IdTfjRzxSU4fZgxao3SO6gkwkiZgu/Sdko9PPqZ0qvxeacm99y5k 89sRtOcge2d8+/X265QhW3hNERq+O8efeLyWzIvP4W8mwaiGVzl370qtXy94slyfMOtI15ZNA4F/ VKmvR1ol7QZyS7HFnBccazLfLgbr4eTE0z7Vv+XgHSrgtmqRkTJSbcV1P8+Ym5F93faDMnpS6M+7 36UipZQEm4fOGyVB7WsI4LeQzZvUsErhKW3nCbYl5Bf0UADZolg/L9vMJjHnVkvY3/EvITsGhXMi xBTR0JogvjOyKP+bDcZYPOnZmD/uYeYlLXTJ05mcJ0JNcKMbZunILETbL/db287Haqne/H0BlEfH kpCz43FxBSQvHn7WBybA8/rkNkqR6IfL6abI8v4ArR3DjTByce1JRZ9kfZkHUydoiqw/Q8cEkH6Z vD5G5WMNncO2wj4PgJ8+XBrBTABiuKuQIL6AyuoEE2qH5wi8xrfUEB1su8v7BRAennGuAkZQD9sU 5L4RiQ0Y13V+ZSCRHVDc61q8/y2DcLWPFD0Yf/BvPp4DMvVNwTfxf1giS9URy1rHdkpOmyMUvtGx 3QbVLcFB5VI8YMQG2fAmLKZJQB3OX1FxhSSUNyEanBo5RQQlyTnTWNL0IDCyTlIQ5JPAR+a6Mqui IugLvYdgupbwPQsvPslt5Vye3OrBxlCH0sa0yAOyxZpfV9wVvnicz92Yo2TSsAZ5qmqPBWEOr3EF No/nJQ9zWDl6UXMSGNYBoCvWlLq9lcQ+LMSvXnkVoz66pwK6XRhs1qR9U12lvbZh9A5DhjqNhTJt 1n8Q21uK5ZWaJjFY8BdXB/m3RnREJIUeR0LnNizwncdRb+qjfQOHknYfg82Ju7HMrhittVMwDYmC rDlznnZDakbYRR5ABmu9dfG8bB+EchpmqUQBkrdwtV8Ui14l0PxcHRuHXKiLcBb16Lp2Uoq7tR5e uQ/AJ2qaK3rAIyQay6UBOgh2mDja4IshPXcHjPBOllFRtRFcnO+9y2BqfJCvKqBiujLb/5L00LsK QtR27SXXMxFOzSBmwDluit5Kfuec3zkZUVLKb8DWrhHOx9umO6YR1MvYcf6iPGfDKgFhDrUwLMTi PnMFVQrp2CzsHfBq7cDKuBOLkWiGBtsHgrWrtRF4Z1j2yqxqk6fzoMn5Lz5GS39UQGfhiHw4ayZO MB/BPodqckocrLfCNfo1s+P6aYO4D8ia5N7fsFJ0pI++GZv/3aZsAgsg4c8f11pdrOKnTIyCPCeB WMQTIGog7F2BUFJAX7W0a1Jh2ybzOK+JgtRlVx4cflN0h2lM49nHhy5fDCyukN0mcDcc7rCOW1g3 +68Pwus4gthCNDBAhnD7j59m1LQJfNsaAlCTOo3oTTsr2yB06xNe2bAG+YwGIvEnsNfV6OeFZVib 9EVfiZNV6y4Q3cMa4GSTedHxlbTiLTxKVb6YI/YjI1XgX7DZlfOlpueIg7b6aEmyEPHCYvIpjuub QiuZgkICuzaAB5/2Kucdr+zUVNsnUE2FOIX/SqEpu9trUXzC2n4pESTVmhYcKsfoGTiQuWxHjJ55 28txehsPKMw8ZZC0MoKKmFFkPhPZq6BzP7qltCp1dMDauxBm4qfzOuu6HtZzlhBuoJ0TYsfVqpUv HZsiF2OaEKV2g7JbY3+5PAL+X0jf0DNlw+isJxCdoYXcwoRGXK817eBcxq0wpN46xTbBwEDXXSSw 85/EJIEbR57hWNK8k3nG8e/fackBVxcZexFnljyTF5qffv2GXE6ew9HfF6WqqN1VgWy/F6evvbSN mc5mC3KgoGbrNQQWAIwj2b56cRmshZqomQl6EnrvICO27nt4/EGV86ppBJh1I562e9uEUyj5BoK6 vWfSjc4Ys2pCJF/OmLyh6z3whIGTQXZi1di+lyXcV7MNw9FOU/eTKzCmdrI9G3Ykc/H5si0g31ti fGFUqtaPJLfNNp2uq7bjJWUxdpQTCz2iJD9G6KdUdBoLnAxMcOjn8M159frqc2kIBI8ZVsprYRof sWTzvbnyF/UrVAMoL+tU589eJC1CulRiJdroFXcKG8N8fx4A7M0RQN8nyZi1C3N1bq37t6Pizxpn l4N5sXHWIXJM4CRVkvq5S0qJ19YiZ1d1Yl8oksI0zhrKAajW+rPjjUWSAnpmaavYBuPJzlcaV853 wsHH/iZhIYYNsh1KOXDEDxqdDgIpK7mn3ixASt0t91g9EpxvhVYOAvbGz0bFlNQHU+lrEviip6gi C23AyfCXSNGyo4edP9i5k3yCGxVYKeVVWF7ZipI0Halp8F3HdG7JwPcJh4pR0EGAhuLfQmxZd66E MGz5JPS39iY9d5Mb0VT2IBla3Iwly9g5t8En+1hs8dfCOSsHk7oyKv62oVFUG51CJdwtYsPJ+aTc cfb1zFTtnpKnUl8i6N4eCvFGTYxHz0NkJpl9izG4nBUsboGpF/B1rVYHSb4A16L3LCfKExA9tdNz vH4jc1eGc0ESlII+6nRiF6/irxWjQxacwByR7Gk/RbP9LHdoJ4F+Hn4IJ/2zDIEMtMYZDawdI+Pl 8hQ40Hi8DfbHo448k3rkX7NUeWxIg1DniSvlIgQOFvJD68YxBrJzWXLFnASbRreh3LBWGjERPkvP DkoqaDpC7g9nyTEx9UfZZcepwhDdyVZq4I236+eqNSzLJKVSG70Tu2PYSbJSEOy5wR6V8Q+4eimt WvHGaRKZ9d4QEGEOT2zyj8qJ4AFlOnRbVALZjUAaU6rU+genN2nt1XD5MucJy9VvQVCL47iJM52U mAzroji1ntj2oF3VW+dOtNlHO8SP4UXE5pIL8jn8iV89RbfCdlnIM5pq1XNTRwXhpf1vUYvsy58m EphFhzRB9tdYcvhZkycfVMdbCaWEQOAb6YbXSCtNrCwTpbXTiSENxjjZFVKL4697Ky+vt/wlm6Ah R6siO3fLBrUVnWsXM3Jiag32WXh6l2ZKrlck0JHuR+QbhZoAgjeofGvNchGe+N/Aehc8Clljwtl8 DrdoBWrpTL5Gdwqzu2SRA+bhH1RqdK4x+2xXwqwBZlny2bJQ9S36V6iD9eI+EsPQPqtBJcMsy/L5 2i6kZ4WJp2vPu9IfK7mUhXvm37sL5Hb6grezl7Ebd9LYIutUUw6drQWLY358dfNHU2NjdnSMA7mh DUNAy5CaA4K9ZT+sj5kktEu6d9lMSdd3QxP5VJpFEVmp7g/ypS3LPQftmtJq0Nhdv60lMDYzxOMX XRDhCjO9nAYFhHyFdqg/ofxsnFKRzaDPenWVV88+PD3kx7SuaEFE03yeCdJT9LPIH62ehh8h+uZK easwq3U4PMM4w14bgXv1x/kAe720jAK8Kg/TN3iMtbNRxYDbvRNWAoyRwkYLoImQUubzji+P8LNM 6lZkJRXwjkYR9dGA7IafjA1n0N2+QxdTlyEcU20b2aJwdeTaefKourxd7R2hrYJmI0428RqyuApr uRv5FrLbehg23ESmlLNtqP+DRCIxcTkjOZDRJuJA/jH2Dd7IgCJID32wbLueJetaYjz0u1Dy5y31 kCLtURjT3v5i130ogBZDCAp2stFBplO9C0tVY8LnhQx8NCTc680gZpiVpZFnIuEZ71MBlt7lTGs+ hlctNchJtop6ZlsrUYznfE7zu0U4fCVmdNxNs72VpqeTeDIbRFrAYL6HnPeqWx/dhch6hXf1NdPR OcXcIU/as3z/3Ui253Dk/jUst4bqmN9xd89NYODi0JRrD4kTIorFLXV2hwHqNY7cEo7OjYYEIqTw GZ9drVhYEGidtL8Pz48u0i6ghPobOCjGsFgaGquWOOb73kP1Fb1GkXohr3ubwZMYaVmW23RVoa0Z U+3Les/eB6C8B8g9QR1QEhhNG2HZpJOC2MKJhv18qo8ITNpw/Pv11h1QXpylSyjG9L3Q1HduYneT k1UbmfEXd0IYu1Yd+2tqFqEDsmwp2ct+P7lDHegsaiJf8fo1zSYdgrzXu+fS99ovDN8fQFUiOrDR IMWvSx4LsxeSc+6TAIUaiWjQjTuIYuC+o39mJfkILzej7W7UXhO/gYly9G1VBrwKqmDC6pKFdnPN hyzaKZ1/v8XpPiVH2Hwy1XbuGAHtgWLu0n5qsUtTZT9jfQsS5rd/RiODWepyM1LXBsn87pQpugWA zU/0UypW7J4o22cWP72+EabOfvibE/i33D5ju64PzpnByxbk5t6YX0R7gn+SbeWD3FPHmzEpicm6 chiu7vUsw9aAk9oZ4ONhSr8jirs9miw2pZaXLv57Tt6Yl3IxEQi+R8mEoDYHSlHcKHnWGEbBV1YC YT/NsoCcHZVyly5ivo7LnJtHUhvLKAjxqKaGF0Oka1X1NSymTgatbqsedeqmE2nYVnr8vDv95FPz odKEM7XL3binvZANJsE9LDEyorKRi3ocaxZJeXzPUzQ8lVKKeUXaNa8Ka1fBRRJylVL2rK2vc2mM U3IOME2LnKStdH7UKFG88xyEJ3JWS7S2yoR5cAhX41f48WLEGNrM9J9SEBsiDHJEpxU1os9HBFqP HV9uUN8Qae2xy7CXZOqj7cKFNAKO9OYQZ1I8enMpMhXJxtdjYD2XoJ35hG5FI3GCqOm1Fmb/8Sha 78gfFTxm7H53dyVXvxuAQbVuQ2crXHcd9S9Cz7zUaqUfyJOT4vfKqjKNo4281NkTk8eRm9uTLUXU VgNpqwjmFoLy/wUR1TTH9XjgfXVxSf/IWBS0VSCDZkyNtG7olvKq5ZhIsRpX3DaIy/3KcZpg5Fjp EYegy4uXqg1CLh9ULh4kBo9ltGCrJg/Q2poaJgE+nKGPwz3ushD+fNpsAWkakx1lgU5WFr4Xl9En vdMMB/QTHTDJSDrH4J6KtUOHjgn26HThjBCaHVJ2YpXFIpzzPMYlzfmd5gOz7JXuPLjwhhCBc4sK iVfvcdtQVmtUXpovJ0c0pWrSU3iNr6DqkofUoRxbLgCNLkYrZA0HTAy1OU37tAZq2A2ihxU8oE+I eGKmrerD19Zlv0GZP5/ymg4SLqPPtzZiAbd8aXKggQPatGqdoVBNnopcOrQVDgYS0QJ16YM1QqFw 15dxXup8GE0KsBBBhzK5dpx6ZC1UAQ9trjrSod9KrXcyQS0jvtUYo6x168iVfRy++BuCa4MsjGdM KxRSOyzxgLyVUQFmUJSoINWZyN6jCb2CAnTTzJa2bZKawkKStR2n5zY1MPsC0qsCbJGjFgMEoSR/ J2wdb+h+9OSPT3cu3hnIHr3/9cqNDOHVOA+S2BXN+2FxVgQZYUCLCVBO4oNXxco6SRDiyQAg7T6X XPmybTarXzgWXNOYHUKzA6I/TIbMTzBIJK30qD+W+EKs4rfKfxBbl8Pd/0PSKzwIauznxQersrPM 2ZnBmvLgmpAJ5kJ2GvZtGMlvRVzHydsGJE0k4WeCpDbddd2Tvt4uB/cD0U/mlp3yalX+C6yEXsuq R4H0tf5EMdqzSS5hxB4rGAAVjL/7bL/VekB7eXoYu+J802XnFuhsdaiCoWZGPuKwMtBPvT2Zbk1+ gEsLa6wsDD4ErbVOHy0JeLELRkGWYPmNKK0sVXuO2PrMHje8qjqtCcIxT5zFy6UpMRskIqBDl9LI asBlAxmiBBMUlJh0MW9kDEsZ3gkTBbWtOYurdi0ORS2QOGFBfxqQIKLZWGWN/Y5xoI6cltOVgvOP YAtJdQuJlNnjbI6g3jFcNrl+CqP0bqBJPN12u9fB3Z9yvafCZaoC2RQC6fTJ8CybuaHbacipeQZk jDWk4FSkmIMdMIpixD//AVEW8P1bEPtss6B2UNMaXKEMa5IA8ayB1vWT2qfb2xFVQEcOdM7QUXmp g0XARj0opC288p8mZa+OV/jtPA90goKj0tnzaX5wRIG+ET0VfxQ99M3/4LLELbNXmHXXfY/k60bQ 4Lp/N3aZf625cQJ7qGYzxj0AXByajd/SiPs3zbWe91eghharIaKO70NDrEEXaQtMVjzoW1BL7kbe SQ5iWGG3Rw/cSYhkg05kqrG30As8owfOTu7tyXgPXU+90VU4pUak+fIGkGDzCieNjZu4RJHCFuCM rSzl6qj5+XXPTpEEEdYDB6Htbn8XGGPxlTQ7gZcwl4goC6c5yxH8lU4xv812CqbowCmLr9tffxVd jr+b5c9UPUxq6BgAD34Ba1rZwDKYMPL0Z7WZX8MyS6D0ibXNZ9NG6mkty2wJNQSFYMc2REzsPYyK Xi2e6w5Gv+EDnhqk0MM4cmt/kjU9b+qxIqX38TAMPQXibmCXxUUxM4dxwLB//TmqHEei7uFWyNn4 w6hvWKUE2PR1kz0f0u/8iyM7g6+khZPo0MH67vF5CTE53LE40DSFnkhv9QorYk9qhPqac8RQgajD bH8nBZrg2sisgSZgC1II5a5OavvTgpJOwiRuhuNJMw3PHuHA4wDKQfnCZVowUAy2NlY7Gr5Vp3PN J8TW0hF2IFbhe0vUW15vvZT32LCbu+x/LPBLvb4OPvY/Nc2waGLbB/IlkNWyjfGL3wbkaAPxzJIy AvaFjbPir0UfVfXlV4S46nBRZ+tazPfNqbceT38LIqkwWI3W1Qqlhjt9TaXq6Q5Y/DNUiviViB1O zv2+8N41nz9dpRGeOWouiA7J0OC5/iW7nB0vd/ncPqUzXGDlMl4lo5lMFNMKe29GZ3hqLLaomecM /4eSNZTlHc9DM6/9yCMdXDNSfPQ8zCAw2/W+r8SxI1ULyR4egy8Shim/8yEODAW5NIyHOR1dIq64 Hefhy/Laatd+AmgZDlT2LVrOFz0MzJETpMlnu47wGC5jBC3xe+AfvOzJbUAfyDfZMOKbAryeeAht 5yvHuVr1r75ujswomV/jfuG0iiAnzVKHB3SCFc2nW5skNlalQffgLiooQSx1dm7JkObWq28ORxgC Oh3PTWsFKm9Y3MCHt64z57znqSOUUYKH0Rpc/ZuTjNRZMZ8SNit/ccpopSwDdn1d5Sv2PCOoDnnT OyH10nCQVnhAeuaFerEMrdI1NCHkun1eN5DmzYNxv3lz3fs21gDXk5UTCzWSikBsLGQZAPigD8lH kbuaZP2zIiWrtBbzewkNbWjuF8AeulJNi3BHecuW7gg0+Fl0agOI3Eu0YTDh9UOawiaTDio5N1zw pKpejCiiIkMSAjpJFbUgUfNnTJuKPpsylBDwEV8dg5JqO4YSAUZGIhYKRsMCI703caiIkoxYrsI2 ni5qzCQ9rcc0Nrp1btqITQwPQm9dGinneDfaSIyNifIm2wPiab15OVsRf/d1m8CdMWvuU/ufs46u vBYoLXy5GrP1AMJYHPs3A05PQ7UzQ6PgM+UYZgQBTKBbre4K505MBH92qhA6JOJpTaf5Ur3gGRLl QExHyfRDcxAe8DM673HBvsROBq3O1EcMAb5AkkcQxXAKkC2fMGDsGttoy6jP1oAq3yixbcuWLs1s +dpqFRnHvSKx5pV03yvXKGPwERvRk2TReqHzY8wxASvAtyFr44o8F51rN2rVSiyMA2dktu+jWIt6 S27UBRn4Gu+0zqeU8u0dg0qEYlB+2nNdlLnaUOi8t87aKMii1RipGrcO6LH6kBQQrZuHoZQIxg3E MZCK+lXCTC66DD1xrJxZw8mScepHyCkV3po/yNCoPfiDirR3peoyenM+8nIlzKnSG0UJ7ZtXyzWd 2tjzD5es4aHDvQFLNphxSpdlen8M2i9290WK7RgEkb4Y9k6gKGNtJS2YNE54UXL97F11McRVicn6 IAvKo58f+JW5WspWDG94lKkAmKNjJvTrVKSHw2P/ONZtgCdgrDXVv+bBuRyzY3c+56bOzmKv7ewY cYP8IzHD49qkZ2L7Hy+axrdNRGU8jyq4Bc5EIRrrOqepux49brtKMWWgjBLaP6eN2l94WbHsAC1u IWVT1rXxtcagSY+dG5w43R163io8ZQXMK5NaNk6JPYr+PHiz9KYNKMEA0Gpi/OvG37HB4AkuZXGv 6J5vfC3JvhN3bVTM4aeJuggMXgF2qS/39rswbU93gxawW244KCaCG6VCV1Mejxy+LjNf/vHH7A4u C+fZkjRd7fRR6zJnuAzFy2t8dniY/RqSdAPcmtbyrHJGOOQbCM7V38qOayJgJ39LA3eOBiTl8HmU ABFGaVTqgkVUvjGgZ/s+l4t5Hv7FVoxDjKd8FF5mhxTy6J72wqcXHoEqC5c3rCiU4oupgYHygQh5 d7eGBeRZTdw8GpMkI0b4TTTXD7rNql8523zDy0iesdzLsHzxOPO/nmW1iapm+iitsQIrIAVGbR8n WfyIT03Hv6o3LgIR+eCgjMQBif8joRxOL86dpiIptASrvX10cIZPHFxNH7siyQoIyRDuf2o4Rqsn S6vmOFLDzrasB/+k/meIkclkhf4fAPxweqbAHtcjKwqQoFJGYTW0ib2P1uWNtF6JMjioNOZil1zr h1osjHq0BCRRydW61pBF6nr6LZLCwOXin+FXx1hIVejenXq5En10+ux5xu6pG5ptn0joXZEqU4xu tv8nGgCCSlqhUiSouTOuQp1KJsw6WH/oAu8mGSlxE+zO8TN+y4F4utvxIBb3Hr+Ufi0U7vT1dV2W IXOVawgffrB5eEjcSuMq+nOhoFvkhr7l7SsTWLun6+ejAlq11CBvfjqnRiSE5/7SZr/5wnDRLTt5 DhlpOFsUZMjVrcrCy1EMJ71/5unEjEOxxpAkgWQCjsAsx9VEe6Gdn05CU1x+hhyFL0UzbWQMUO4G iAbkS3CsaP3JUzOrdS+dzfVBSemu+0YONYpKxp5qy4r+E6UrX/uPZR++acZWx2fAyTxlLUpR/Q54 PIe3Kt+SO2kzVE5Q3E8U042HjDAHS2Tqy9DP+w8MlAd49ShKErUWWM7sCc9YATg3wsZXbLWtI7hw g6bkhoM+ScfosuOcVezV7oBdijr5QGLSvmdpHvYd96EpWnqb1/QntOYMbkZRKnT8QKGtAdvOo/tU rpXkHO6vMBa5T21wDUiAmzz9y7MCPjK3DHYG5XvsdTIcjkAnrqC/nJXzUUFvN/uZVmnD+z1jNnL5 HQiBb0G5yC4sOBni7PIcJxsOWKC5uMKR49eX8wQtnIzvDQ5pFZatMt2FuJKRsGzhnvZI63NfYH2B 8KyaxrcMkH55C3pPSk40/GxIDONS/DGoON9dYksLJ3lkrqcMJbjIEr0PHZa4pfZkG3dVL8OD0M3X m8yJ0WH55jyVlKD4QAiOfY3t/72N6qxErieA6c7EKMcW4prdeStUyq0J0JiSShi9g5OjQ8DhPIVP rR5n+NYrLP6BGI+YYhnpGjcQNXxxyaR4p5gmsPFxOb/8xsUyXVyYcAhNb2/ab30+MKNjukHfvOn/ bpWZCaE7AjEUIctX7hbGezjrdp41H7N3sLp7wQKqs7ZId1wHAa6m0u2T1qDqA/d/KpT50mRZLq0k yA/XCvf1Ppa6fNAI82iY5SM8VRnTIdVkIYHH1cY8tzlAVynK20AZGG07DQnY7fJxnswar7Xw9ai8 Ei1DUMJrzzLBfSnkrUxlIfLs9nf8BxFqOLZEc1tcZ67xwERd5tMsAyUixxrLSGIcg+VX77OiEfHw lnzVfhsnmfpqDzzJWieEUHVeEVYeKRNDiT1jHAklAe18haBiVBVsmItLp2k+OBF6kPEtVwpZtVr/ xR9kJN4MHUXcALtr67v+i9SGy2doCcBFscb6+yvMGodsz0636Niy0tNsyJ+6FoABQp/1SKwMXnxo ihcNw/s1Ryzvb+VVGim15V+m3fPa/Sf3XGw9ykWMBMus0p/tBvdbUo9aTsqY255H4STRVjRDfPl5 iy+P1X7cs8sGkjcSeU0GLeqbqsJ3n+bfaKxKejXag6eY7aSKb9KV7wxL9TPsgM8N0qTG/RwhIRgP /NI9ypjuu6SdpLkIfc7meOOPvZ7O6LKsAC/QsvSj0mAHUMM8m/RAh+MxoVKkdWTae4GsH2gnXY96 sWEAktPFvJ9qhbItkeIRoecibwAcQFXS0atsHT9Nk4ZUjg+4Xwgd1WSItC2CMPDJSbz5mH0xazQF HoIZXmCIW/fOVm53eMl7R8PMAzA43k+s34NkjmzqRAt3ICm1SZnPG+hxJFluAtQ0kxvLV53Ji3rY 66HA56eOL1WOh4z+IRF2LWEv8K0DsN+EFpOXHC2vFyOunvwqRZIV3FdI/8P/3H/kR/1QoBI0+e4Y U8E+/FzB68bkGAS8LvFO8pIdbNqmdSb5tlg6S1iWP8BlrQMdSiqb80P01+sg56BRJ4Fuz5uLb3b0 1NxQU3qv30G7wnBYw25HjaDibmo7Y5iJhJk42BoDvif7YY0AyPLC1BvJvV19L8oAwwAkd+Xgv0MC LHzFQzVGdwi4RPfFkPolRcfIwnIzzK8nREG7fT0fgHO3J0ECbb5jZWrBdU+2qQ2YhcBcmws4Omm9 qBSuel5gZjNIA5L2zBNsDKEWjmBuyLIaUP5nv7TWGVS1wP51QlYpuWIqj1uyAIH31gfbRHtzse8F /GG5JzH8HS/+i/tGTcAcxXBorXOqChBz9yJmvPonEDTZ99rvlZqGndjF/0cejreHstjm2cBy8EuF yirb+RapF+G5qANzQ3dsKfK8J1MuYrH+s35JdeT9s0QjVZ+FZPSUp7yoySBDOAuF7PioIgnp4u/s 7FKCEuaY4C1TOvm62vZ9qy+Nvg02vyuMlZ5bZJ3AGsoEuVDStwEFUQndlZXp5nt0G5w49MRDf2Ws w6HULZBUiGfDrMkqLawbUBi/lrTfY1HzU0o03xHFMc+5jQ85GZ0mliKbt8AXBfApcMBw66YUGnuu DH7dcIgcu942GfdjxMPLXPkaa+hUbgbCdfgpn46GEY4ozaecSYAaPvVnxHkdT/6gVD78XAVxPIEc s8edka7U1pQTwx+prvl+IyeLj9q/hZKUN2nbdMmnQVB1l1inxamSD261zL1LRYDgKp5thIV3m3e+ qsrd/2Qy80pYjRv7RGNkCEl6gXiiYxV9kNyd9TApEoVSPBuuMTwy6MIAqKhcG46cv6kymt1x2Ix6 75/MEch1I8Y3RSRqmnCys5rkq85kkGdO+IlzviCgMuM4+hahlP3JzjFbQGLN9EAAJbEAmyPz2Dve rBDFPGbX+7Ne66ekUrwAJY0srWcL94iXEbq6xx5OMoQpxNYuDHpl5xhCI4YvYSLJSszKY1ylPyvr VN7odZyPgEIFD1PpMorcL9wT6o3dWLJh2EhMQ2wa/zEv6ZJnXOGWyM6D/DeyAHdOVGIagGyV6g4u Kipl+w4RtrASsdbQFQmFX9g0pVBcXURlpLqXNy/arP2rIqJHHtTq+i4On4ZusGtG++YMU6ZD4FZa VXSTKEDxlRDYAsxjy1T2ishRir40NV7qpUobJ3jIAyotdS6ay/j1d1/CW0db2QFDkRJL6PDU/hHh LRke6RHJu+uJa7deMP8ipRPHCmATvYZr0sui0am3wjk+furZG1D7uS2Swv/Gzw8IOsYW258rcvhG xN8n3/8TTP4e5rPWUY9BwL4YYh7yS3PkkJh0UYDhP/8xWv9AqOHtqs+Ib6MarGGMUVoxapBdK/Lk twirt5HWP4SkgQCOYH9AbZxKJZDwksymm/gqC0uNrwUSxj/REVA6Fvy4HPTB3Ook5EIX1kt5CYim e4Z7SkcIYQq99tz13K4YxelXsoCWe3UKzX0eNXRbvwCkkIkSNVRUofjmVUlLUMG2CuAID3kS43LE GsqUaLUf6aNu+ZZp5pEAm7q4rdyqWhJxkuyq+e6T1PuJCNbatK8yrBPGvj/NaWo04WCVJFX0pb7H bb9MxYcmXyBsv87U4P5vY4ChdyQwMuxCuey8I3dt5iKg9bTeiT4Bc7ogF8WMR77OXnthhS8hk0uR vsh96ldE/AOoyqdG42byoP73LZzFl/J7rVa8KkUzgxoeFl3GhEhWbUgrXfKQkl/ZDpqb2HmwJx0X IjDmBc4ix9kU3XEDDuuzd2bsqnc+d09sJy55i/zojFyTRbLLtjWZPDmWiPY0pObHMcX5SUo+tR7p OA0DlxDD49YMxnT+WdJaUhJoBh30vIuXTu1zBU95zocSoYzdK+SPEBet2DJKyb14MUrjm56qD1/a xcvnexrDlcK+za2avRyg6T3zRiWVCUn/LQ7Oh17qijpbdu89AtjnsWsFTK6yFzWwyyjwHO73NnUm h+x78oxg4kH72eMa/pik0lkZH11Wa8CNd/PZx1fqeADsK5hJ/piehxokVpF2V9+QEcjGZwcq+Ilu tyq9kDi+t1H5/ZX8dVhckGWR7B64AbEj3YarB75ON7NVczCxRxvA3yA/8AjLMECQYJVKT5lSWJ5K 6DjjKvn5wkm/Omne/C8vs/k84R+9aNB8BDsw2dtBkPIokemcMRBlPT2tBELG0dFsQQRWAQskBBuC PRgU2lH2QT1aKdhGFQpNeNhyH+sWG9RVckFg9XTHIKl1RO0Ma60KYxiuXow3gWgf0OaMqJ0lHY0g A/AVJETotj3uO5eNomjxb5/bEGz/52o/XuhVzNmGVzxkIWCJoRjMTaKqqpY+2gD3mFSnaQdlBfSd NTr38fCcXZvkVlYhLegx609KfB8bhbK5xSh0CruFR2j48gB85zCfYpKGsFZfBI1NMRBk/uVtNRw0 xdnwF+ipAuqWfY4iZ1SvNnsAybB+54QzMkvuW33g6CVw5P+53UmbFKP1fXbPcoU9st6bbXHA5yvL pzf+zkrLqR2GTL1hw2SyDA2b3ozyH9kXSZXzML8itJHIZu/Dben+Cc1UUjqd66Y9cY6G46wodJ7e mAjnCCrh2pyutnXM8Jj7AtBKE29MXwZMMcnsAk8EFs4GcMaDpyPhD1BzC2tiFCPULORs4n7p5Xkx kxJ1dQxer7JxC8FZFTi7PCy9c9fGtjENo9+nU+s1DdNxIxtQp/zvgx8MpmBVQd/2ps1dPbK5f+zk zJkhlPCOPeXtJ+hetYYtZBBZ+D3t78VLGFbWzmu9M8T7FiK8Jk1jKVkBknFFDqcAtYavJAbvh+GL pIzI8MOR5Ul2XTdlTxECwJM+RYfUv9a3GIw7DnRQFTR5+WkWt2SUQvynKOK3yhCfPvafihsFKHhB nEsSzmCclA12bcDWRKJ0gmjqP6IhtZBXaQDVl/6NTNOC6gMbUp1K2mhJspL3cnLY7lIZNgoXgacf DprU4Nwz10zPeXuIrXpvmVPvU2wn4RQrgqRVtc1MiA3UMV4ESMd0gMa6OYzf8dpoqABeJbCWInOc egjh7ZwlblLocSMWACuQXzo7oeL83xEZCHZ+Q494EpLITyahC1mfHEk8EwLdeSiDNQ+jy6V58cgx pSLc/WRDmD2GTaII9uNFFb9j80lqz3t9aUTKvVm4jTmE/O6x9ljKFjB3O1R1LFt8fZgFEMd2oeQz jSAUoPZhRxouNhn3C2dUKcoraRGvSDWvTl/qJv7SNod96OMdkKt6llrEEKns8VBzxeLZsAwy536X 9g5qWtyWZ7jwrdsYSe/GfsQFzg+M+ZWWmQuY0WjJbr+f7AiWA0nLxTwtxM8UUoQchhFE4VvXUPRZ LAE0uuC9bAY4bRBRUoojVAAhEET9Qt3VYGhwyh4pM9byQxNteHYaf0CWzCAUrmsYO73kmKZ4RA5V JSptj1b5JKb1HCXwSFxnVIGMSo7EOw5o0nDwWcpNd5ufaKEAVPsII/51hArKFure02ECm1PZp7C0 Ke5i7PCmrxB33qvHYj4SmmdrQSojZ6NYrUoz5QsPJ7+hGPvwmJbmyPOg95/hB5hL8mnTNvm54EFv 9eUTupRBj0mSun/8q9gRB5rn4GkTyii28sxFLY3vmZyw96IG4Nq9jLGYKEPAuek827i9aDdEK//P xxT03EYhaIEAbuUEk0AoWIsxmXNaGeEC4+jGYoY8ywdD/EdtGAbKKluS54E9WdVOj+VBd2v+pkvt ja454f2BGd6XOJ5GPPLZZfzoZTEijaAArerqc4IdyeUpMUUwwjmAIbaWmgvNZQfXzgDRHr2/1cVj wrxAPDdtVLRAXa6ybpfM8UFx6C3tK+OheJYgh2fqJu0hYFhXyOLdo8EcRMvfY4/E2vCnCmX6S3Tl r8l0AG4waZPv9Z13lqk0Hb/nPKn5eDm1XmXvFFuwaONxdcbf0+fmZ7KNkM/eObvzj4g5tH2FRNiZ XHSZHX0zrRZRtXOicNiRle/nkw86z9XfkW28ZAm9Gz234vg5i2IrZ+8bCMZ464lk3bp1UiEJEeym v1VXNNHbpEG3nf3niJtdVv70L/7lCO/GCofBEW2Rb67xYzaRCO/s51mXijf2QShXrbVyuG5l9fH8 NVSHCGCwZt4n1CWnNhZkEG0F3dutlg6qx/UgPe3PR1RPFpdP8y7x1EIH8eMqMfDXNZ5gfYAn3Zo+ uTDjL6z5FdFF/14UuZVP++LZKloDa8JWzUM3z54yd+OcNyMVWuwz2CW63d4ZuQM7H/asZ8RjcCZ0 H4XziCwas52fZCJ5Ka8uHqFvllg5w09SNtezle83iikCQBQNpQ1ykS1bbZOfYHjIwxQ001Gy14lR TPQlggiuMjmCRowHQE5Np7wc4wlf+u14ZVgeP8Uks6IKqWA/T6Bkd0ni8OWtn+jtVyS05ZtQujz7 FWn1qjy5KGW5OK9JTosdPFWqLumGe4nF2wSukevgbSe3akpLB45Hv+5c4XE6gY4vVVdREK5ffw5N jJWwl2OSWX890cqgO/eI7Kj9yxgpisFnpcGu3fk+gV4e7eClbCAZTdD76FJRpCOQ7GmnxKFSiTNf duwJ0meM4nFXk+Zz+F5rjvIeQhHWBhc11BD2+A1EPfkanhVUm7LvB3XjU0wmlCo9mMPLQGvrg4qs z6misptVZWp/qbqtMU6+u+ansZ9Oj/7PNRNUEzOE1WJ/FqPmPtLgTP7ARpOcrx8QNKgZppcn4byu uUHAq1CdjXG+MFv5l8FTkDol+2pWI60E3zTuRHleR1iaJws+r9tu/YT1mX4Q7lxSygpHsfF4ZkYF 178RTK6U5XhqJL4s/TyBnbFsh5ppxFn/iJqTWXRubdzisLcrEhYr81mjkw16NugVHJK/X/fLfrdy e3ORwo0/YdjSpcMSUOsgPxcZDS7tXyNZPe2YSrOYEL6EYUyBjR4p+EInnctbrABD1RlEthRARaIY 4O0K1YQAMEvKWnoUY2iPg9ngYOCCKlMGUogOHkgM6dJHKCHtheg3gQxr6zxKj5dS4ybvBw8P7ymc 90EBiNjGPXdmRwQwk/99qblU3KLEgpJcq+4o3hAYSjIGDwTMfbiMEezzxzvIRwcw1/eluM440qEm cCjPkkaCTpaMZPHXaxlyt467H6Ijw0hOLmI8LnYx8K2yq2WMuXa0eOFgAlP3Yq1ocWT15Litst33 okNbbwxthsSZjIFuaGADHCi7wQgcyzuZ9tLWnYUF6gM0ytgrpdqpxbUMBXFxiuOtkIKwMyqQc8k0 H5YGoiGpjMpA6NkeOAHF+eiLoSXh8bcdmzcmZ7SNTf2QZIDxJZrwy65F4YzZSQad2PsrBGNf2EDX l/ev6QCNPSorvd2e04ZtH91OuqFoNpY7NSLlY80w23+Kc0xXjb1y9FGTeRbD6zMug5NxMQ2VGPLW vJrbIsgl0/F1t4XfpO5D9D6+gm1D/wTswFk50de53coHi1ra8jwv8ONuG4JdTOmGHMvP8+rfYt0D +Pf0hPjFoRlrXZ1l6m1YQzyndggZ8Irn+5cPUczMv5hhJQSVCZ7Y3ZjSfs3guyiAEbY/8OQoC+xg r6c/m5HuaoDItzTuFY5hu26Sjwr7YKxM3GHbvqxs81U+aJ1HHZK5kGVJYnEP7s+9MU75DgBBMMly WyzkIQCB1vKO5v0YCtv6bwkWeBujl3eocxV9QfDgYr9RncjnbFJ7R/q1EM9MrxXLEw9GUokW1G4x 2UdA2Aem/qg8mvf0URF36qrtsMRce0KOtHrx2qeF2LoEtypj827XZQK77GU4cTRq2PzgYZSkoGu1 5y5G/rwYMI0p7JKEv8PxN0ckLgf1xpQp3UFoUlpuyyNkxhDwiB0QHoYdryPnx/oCEzS02t7TJ6YG o+QTj3JJtI1lFAFaBQr+4RGIPAvjacIGikwxFkueTWqGJbYfWk+ueuy6QkdQDkj9stQ0TWfm5nYz a9QJ80VpsPuMGqQttNsd7Rt/x8S7Rx78GIV4nodJoYEmQY2/SrDKeie01J/dNWzMoCYthIDQ36+0 7Gatg1ey+5MMC4T8lKJeqQ1VhkUOY2q9b3NzDD/N/n/G5ePuun/4FlVvFSxUoMl6prElY5RXG0ri O+pW2iEpOSjt1FTbfZOCB7e9zJPj+CKob2gkqL0r8xPE874PnM65dzdtD/jOqgzXfNq1s4bo5xXu VtSj3hH9XqoZNp3+kF0YpgqEDrAKRTLSGlmCdou+do3Xh/caJ1kzSl1HXPUYzWKuCwirNoM7GIQq JwpNg51gdWOu5s9oEAUi2aLKHf1M1XlldjEmKh2r/5QEg+rUDlPu0Dj4kMGOjXAUp4D4Z/5KoVqK 2xBrMOQ9sEPRVXTOp+00jhB8wlbughKZrTW3822oksFEJThZL+86muOFbsG+TnBGlF3/zM4xkf9z ETKF7FtVcZg/fZryW2utiAxMH479HwFAIRKTWKoKR4MnaYXpQJSziVlVKJqgDvRI1v3k7fj2EyiE Yt2IX2a4sB7Va3GncFKRYutaeP61obYBBHjAmF9S8QCzUM8Ooz1yHrvEONtF0Ibq1jL1hmQ4jWy4 3Nelc1AIFIT4Izg7nGJEnsZWOiX9zItVgJsdEyalTwc44qsXWDBUtG4FfphKt1x8XpaNqSZwn+s3 Hncv/MesYy6wDWjsnIveptIymehDdjMir8EDRacIJ8GXggjGz3xIc7thEubSVznptD6jsI1LrWhL klZR9TxCCOKqhCxcbgX4uFy2g0r/gCfoNWWdwKMkM5Mzq0VIjyam8cOsh1GqGAZp8snLvV8y8jra vNF7dzrQaKD0uA42bVNrGQMNS3OLOu59ZpsuziO78THbgJQpJLs4/vRVkYPEOs9+AXevbKJl3gws +jgUTaRQtSPJKSbZWhPc8Bs3NTZ+e+9HN06wacXsAV3H2qb3fPvo1z6J5c6Fsulp1g50i3y3owfk wnPyUXKdtcHnIdZdkjRNzN9G0ZEOv8kPOHLq1P3BlLgsINq+BuaF2b+1FaaPpJ86BOPxmjF3On5n kU/F+Oaes4j/sCcDKIv1thh51cXIqPVNBbhUMV2dWG3imhDi1TQxA7ZhITBkKiNrGTNiCOHaC3LR pSEnAP4yUvg2BpR9WUG/V465aw/Smxi9yteyyxtTJsb6XceEbxqczK/gTUrDGU01JzDnccAMtj/Z xH6oeq/OoR7Ti8b4WIq/Tmq2j1arAd7enJLFPTKBwxcinuN3KfKD8VOEjT/YiuuCpQ+6zOS/CriK zqmNAsU7fDhOW+8pG6iYpyUsz8ehlNtzDMGRrq9lZphegDOrGlI1V01GiwaXMyC1ADAp4XKuQmy1 9Y6KecM5zyaYegi5BZVDUk8c67LiF+aFHd7q8drpWXrN+0yhvJ1TRU/1Z2ZYWJgiRWL18G5CXxac +2cLbcXndIbozgdlt506ESV+mF/ibsLGzU4mJ6SvZemHCngUELiCKMQpyhEZ1chye2GzCykOIgJ0 FvsPpRJB8D71JWVAdzC/SnCTyTcSs+aeDetPX/MzbvHRA+bYKw9NGSsTZQxOzPbJg2fCBtNOGnv/ G23zs8D7Hyai5F/kWxITskuNMr9szuHzaNxVjp6fWJRdhTiG75aZ7VvFJoq5Bt3Q+BnNo5FUVS80 lFOOwUDHJPj9VieIK9gmKr4H/39Rj3RsT4LPC7+/Xc+/Os1YyHKXxBD1IoGv3zvQb6jvBEphINjf h0PPj+BLl4FBDATwoARjYGC1568lRef6yUoJ/9q0o4Lqle2d1iH7AZHuCfp0Dy1oIbg0IUK6O1iS ZIReS5eXD3nHqAW36GBwZ99sAPilaVZTmCoDywfgDSIRcMdIU67z9LiFkwAV9ztB/tmY4hU45H9m 6hYsMjB5bHM6Hj0oxpu6ahQqyIL/lRi9ryHwGVRD5fDR+cVz0Xh1vGiT3itRuV2GlP51LQydGeJM qTJmHj2uAEzECyRaYv68cHcjF7wzgVojMao1u8q1yCeDsiFXUSks8Wfs/26X0hHx5ui0tiXFhrWQ SJRBclNntqq1KfuzsZ9xnCQ2FGuKfLLD1iHYU584iEnH0BQFLJB4M5Qeyf1459mGD/MEqTJUWMr1 0Bo/Gt4LPVabmu+NLg3zRyO5Zo+Zuzmb295lF/U2C7ZG+nqA1okgkqluIUPcboJG4EmGoXJf9Coz bg/529B4qF3IXJidUf7oficKjqAzID0X6z74zuvQh2rHHJh7yHRZ6D00xrzTTC+HEBneJyg0NGDB 6mN6GRkHFRMThYFLbENJozWTzia+Fo9PsnX4MfkwjSYnZJcHJFoKqbqHpEj3EwUDGvx3DBst54uN wd7p3heFgSf1kSNjHcV4LnpIM5ic8cYFrftdgQCEvzFZbSNOt2tc8AKOdrhYuF5Qo237AgQ/ITJF 34lCLiENNvyXYlhnSocs60LOJodKk+Ip2LVb+G1tQlINQSzoAmj5ZftXQQXGvB3w1cNwwK6vZ3iL 15nV2ZwsXtKEbZY+VkBwzRpCT1TqJFwIOsjTs83ojo8u8rmIzgtXR8Nn3BxDVpZRxLvfUeUx1FMz qEnRe3LcHtvWSD8O+SZnElfZaN71gO8oKrnq2wdxGdPTKIlZOqehICHXLL7RpGQwAa/xPmHFIJrP geHolk4rzuT4/VHJq9h80TpJXdoH8yCCky8Mb6qpX5+NDPhPAK1P2kM8MWPvInG7+vPM90kw3xVZ xNq/ZQKx3zmWMfVev5jhGIZ/miwZe5RFAUsHLc2TJjmBUNGp+OjdouRPzeay3PuaIKKjiHppNUKd gh8/aArnACuDSsHo2r79VqxtCqgILO4UeEfjp7aGRs0NY54LXeOInlGt6dN+gqqg7+gl6INjO0BS nQ5uynoKGdjOhVEs+X7wuJouMtQq1Y7J2lp4q9/JeuKqLQyamagAkcftMdfbHHX+wfpmjG5UDd2c rxVJaldFhDbhmyZpBQkI0dzAes2TSI2tcHZKTxmKr3LPi3LL1kHAanm18vFXG7fw0f28AF4zxsk7 U1qPH0nj4R5sWEdZlIXkTvNwreIhcKDQ/1zorVmC9xm4GGSPg+Aeu9gKJhA9QWDjgygsmlpsarY/ 9NB4QkcZG/nx9Mi/6OoP3qug/KRW4WhiM8tKeMc6RKO2Iyuj6y/w7uUwkeCB/5+9oemP4NlCI4cu 6CcuyeZug5sCFNPsnMAAP/Gw8QhGcDdoMU9hi96fhI1A28OadCbdm4rrT0Uzx4b/2AUd4BKojghX GuEjxVIjIfz5jKBQAp99+8eOFs9YCVDjsKV4pz+Oab3Vvt3gjRysc99bw4dgzfgSql1kDjKmtqU0 urW75cyAZzZKHW8S60oJzVvuqsvUyj5SyrsM/GKD9WvjH0bRyYgi252u5NvMbTYAJmEeIJiXLNhn TKh/rHuzMr6zueEkb5JNACupmVaipSxT43yhp/EhAQ4t0JkO2NN/qbYUM8HNA+M/FU3G5D26h8Rf QPXy8nhhfsvFo7qhT1CBBRLOJtV5pGjvl1BggaQG6XbvciQsPFPDzLHmU3MG5q9/d0hFq9T9fQoE SwgVOZxNdVJkxw3TwizI0/LJMiZNq2Y1FPfXSqAMHbJtRvT/C1CKhECeBuvB+ODxXXFZn3bhldgS Juc7KUrS2UDN1UWwAiqckIj2H7FyOg9vMRxxETM1JTSnZWjvrXZC5Q18TF7CPWQIiVUwze3MZi/q HdC7Qzo1smHXOuDXuFcw9nmYxCpADyR93Lv/DU7L5cKjQRo7Rb79VInoYMGJKnGkwZMGHiabp2Tq WNmLV06YGvlk4b/E3qOASDNnNfYIsmC3X+TC0p7J+1MqoWGKfiQH2VvyQnUMR60MpQhzI6QVb9VB 6O2oN5ZSiB2fJOH7DT7tIXirP4jAF+i/ONcUwZjesNh9QnpGejIy5SV7CR/dgeNxfmRtHpDvSrrE mYi8h7zOKg7b8PwPZN0aSE2n52Dq/kDiha+fKAPN8JSCyzPM9DAUjDttqX0zCAt6CaqQUHgOlrgD 9u3Se8fAG47Vly8JD/BaH0jidlhDNT8Ny82/y7YCidQ5vdwmDp3EioknLj0IRyzILiP+fC5WzHOH 5/GmWKo7L5HWgoiGe3GmWW8WJdV0TINtDXAAC2OZ8KQjr+b3L+3J3XDs2s2ekSVvBcedNyMBa/B9 /jbiAy1EVDyiC7dl9P7t0Hfp39gqzwNgFce+2wE0AEFPLtinusrC+isEbYoTEnkA+swNJjYdahy+ V6LbQ6krZh9+bemxnInraBmMJbV6tKodi9qjcZGpgXbAJMUd1J9wZ7aEUnMsQh7l1zPS21TIJWIh HS/zQ+9mXnzdboxr+Z0D4o0uFF7Ibr7n9Y5gvpaJ5Z4jHg+iGis4SwXEeQDgxA3qQ1reLD9Cg2Pv 3uzZZOoLOzJTlzPf6UKW3tANPpFHKpQR/CJs+ZmQbPg4QcUWJ+RYhuPN0Nn+9pUyyG8hNXb+XfW0 VzH2agwRhaUIRgpmChTkaMoPRKArUGL8gG2IJ4vbrAV7Y1pAjcAO+atIFzJTADeflewFwQy3Z/zX wKthYO8JnsBCqQZYvSNN4+m6eoN2L1fTSC8W5fdMyXIi5jRzB01AxURJ/DcHCMHQ/OJZn2jn7qS8 qdmqSaXi7m+rtSbbrPSsTrNKStbbN5FWHWxxwdkMpbOTseEVMlmOm6JSZlWEV4+U9ekOh23I8rPQ QUYBKeieMV/Yig7qscV3GkwuqAKJfHf8IQGYnyQZEjZyJRp3etKP7UNatzvJTXgUrNt4mMWlZ47/ Ei8fktVy66pQAYAXwGg5twouR/pdj1voabziF8fbZIhah+8N6rTUMZaMsHjTjRgctzG9drE+2gdo NkTqfsX2WjSnDDd5Ofh5eFGrXe1oT8Uk45Kvlkril9t/KYmGE6Bsj6iiWh3ma60oCGBz9sViDLAh tRRyAM8g7eo6U+pt2JGbI6SMtIxwfsO7OaezmD1So/sMiUJdfpjv/q6ZnmScsT1EGIVWL7B5SEWR sZW+Noqr7IQjyZkmZGvOv/VDUJx0JNPs/8WLHxap6rYpeOXQ6Q99GiY7DpJqPZc7GAWOFP8BoOAx RisXaLotD65I9YbZRkErNbk3/WYA+5zhMP4/MBrASnjDVKkQ4GHQR4XMNf87urEtIAJ8gr/r/RD/ SmN7KOVT9g/NS7jHanPSWCE6OyT1UrTRt1C4wjwWHG9Ze1j93BPnaku0njCYLezL3xP6ouS0fmkc 2Eqj8AypnfmAmsDB1egMmoJLONHRjPyvAHfmWmOVz3g6cRF09Nv4u01U72Mh0QWEgDAvsaJjUCWv 0EPYyGENYofdz8dCxfMhulD7yw8y858UWveUTdMXMGJBL0jWUdThEeYiX375xmzPHDNphrgoqXMY zoGbCE9UrteMDC/ZOjkCiXRkw0PYZ/un32xQIAFrrjpk5kljDbHiYBSNUuNkxf8eC9tqxTI7mg5x J6qVIDIDJEXMlLVqx1f0IgRFrSC6bNaW24+PmW1WEsEV1IHOwV5wsvdAn4r50OS3H0B1YrmHhXOL ZrcPRJjcuYLndh/UN9Yow2/B2F9YSrRumkEbNvmMC3jX/pipTpJOxZlH2jDMYG8FC07ShB97wFva qdlWj4UPbOZveuyzkKOGOgQ0V4RdjZ/dO1NG8p/MHrGOaEPfHoxo+nukcSHbIdJkBVuZjTnz0JOW DqpRJgP1GjQAlTC9HxwaxvoZ2LQhFZ0bNPnBsbIIQMCPCG8+rSigEXl52GYtfuOZ+Va+tsQ5sYue RyJVcMnM6uI6nhHOMBK8D47Z89Hr8dYKA+GP4LG+uwWgeCiMQrkuLY+Q8nNOCvjpViBkeF8mgjrB ttnojHdQgU83PWnQb39vBlunqkUQ72fUIwY8t2qPqbwaW7K3za3/oikIxrS9EEjTkhIWKATGSyvy OyZK3XQOoHa5Zj9hv9ev2y6AJHfZTm938mQD2uwAVmT4X7ZT5c+19h6WyVNiU3xdhBhIBbPiZiGi hEYZXmJNqC6EvRIsF7h55TWaQqJwIim18/tfDmqkUaL4vv6rDDloPxitUSZvNa+pYVUcVomIUru9 4acbSlPJGDoh6iRyRzpgE9ZYOezIMDqztBukylugjPiRkCdw+0/FZfFgiWEO8624X/Bif/+G847C MTMjq/ZXWGHTQsZJsClBToj5Q0Hfc0gTgC5VmLOCzgN4GsxdnAfvZRC+2zuyMZvpFfEDIyOxLfbk Pp9MU131NqyjAFq9kgZeupOs+41oO+qYQi6MK8UIBSWl5HCz0Vztg47mJ9EuRvz265ZErJrvS22S WfzaKUxPmYz9mqFs6ImKbAVTzX1p/7woBRNpQlPQt9yEf2hViKQEOnYQqMszL633NCFon29k+Cf9 4RN3zyf/ZuXZdTYpu9cc3nN+VV2doUmtfXIaHPabef8cRwc1A7c+tNn4FB+yXBaw2yJH0gl5eUM5 nFY9hrTu6OI/uEta/WphTFaPJ62ay3aXxZ+A+LJZdy+MaLMgIBBYckAo2UFrWx5SfeNMSKsjw9MJ J+ILrmbe7+RJUSFAwz9uZUz+TkW3deN23EkBm57dZhSKTJYLeUwG3zzBUaKKVTr2ve8nFxTYkYES KPaZvNPSlRJA00gwV6uAEdvnivCqxnK1SUzm8z7xrbxsc3ewwHgnyfNcmJFiiKDU56ZBLLPiv64G oHx2uNO5ozEtYOViQ6QI60ZQLBQCPeOdEExuARkcUneaVlKM1cbEnTNd2WGlY/wlNaBn5wt00Hem /G8gTCTODnYlMB1MOWbT2QCTpvjccYq/40rQW2NbXWh/aqQm+seAlMPqjVgWvR5Lg12mgVa6BLmH QyxNAGsnyEbve9Pj1m+22Gm0a4un+PeGCSuqnaszZYxLw6L99uMZizDmT/yRj2wgMm+qhMuEDPdO JGk/KnhsopAMAUV9qr+flSKv5YGRqbqGpallt+mikvOtV4G/2GWciDuKvPvxJrHd51BbpGkvcOgO m1FpLHK14FA8YrTA8G8rr116+xUiArxsnO3XA6qcCP2KLLC4lXUAIk/JCMI87ImWviUEWmWnAlXH 17SEwXx7iGGstmyYtR4/Noy0/Z8RtL1FvHIkU5RroKjTKnPUWBqkQ0W+OOeMSwim08DckXwFNDe/ PXzF+eZ7yXaBU0jDqxrxkClHzmyHIq7R/HDy2EjIcn7r3emIEB0+s4OHpbUf6h9g6gpL4sJXmp8I 1EYA5WF08scxipYFR75V63Ty1dV3rTWpZ/FiEyuo4+s9vGDDm36ySOX2YotM3S3EOyW88hIlYrCw FwYSRJFVIJboB4T+nIsTH+CQcfPkQc9j5LLdB/DbA1k85/QRGKeI4A0sEw9fdLxJ7GnjzwXpuGYJ jY4ioWBuOom24cvt5OgnFHW2E/yBdmtzNkuwBsmSc65mrpeZdAxAqKSf56V6ElWuntC7zXTUXOiH t+6gnXqyPowSkJozzHg3/rctQwskxKTcc3kflIVbImo2M4rXMhdrxwFRX+O94qfpeFfb5xCy4JIg TuPjVMuRMMXbao40oCYjHBazTA1V/IRE24l1LdPNmiNLGO8BOO4HpPXnbmlRnPWDWT30CwfeJEXZ 2wUgkkXl3PPuy/Olgoo45VPilY5SUzR4t+yimfSGgs+CkvOzOL5WJh/gTja2NdsYnSUr2pYhlMgW OpkxDruBllDR/jdjg5GiA0QvRGwmqo4Dv/zixc0+HmlMi+tax8fttle2KU3h6Uttx8SkVPHxvD2P AopdYx4iO1lcLseFXyOvcbuIPCgJjriIjHsd04h9UpKBZQUp87XBn3r0OXBM3cL7NQ5y0GYfFed5 TXHpAJfzm7htcsUyws1yDQ8pcaX0B3jzaJQckUnSf6Lza2pAwkL2MQU04VdBxbaK8mJQuybUsjCk dK9Q1AEMbginMGeS0H4UDAU0Twhdu/6+oISym3xXJHp3527jwFJMtvUSBdqaqEOn1gJLpcjkCLyU le+RtGKoWtLx8++YdNnPvvpMmOAvTofHM6/SxMLLRTxjkaw57QJoOCBYbdil9SpX707i2QGTi/5w TjS7FGRH7ie4XfLyWkMk0obiGpd4pw2/aY+ulcEK4D1bsAqh9IxPCsIwKB6Jc7y//bGcNRm87btM iA+W+e0S+2PzEUK4TwN76AH5MxiN8EibC9gyLIawZzVQAuzP8CRCINjI6+4C2ma/EOvJFmcGTNnA MZ/36uViDdhcEpUOCkbh/LD2li9s91kZRBMnuyRMeZTkiquq0tCfEbQtTmsEiZvMoxQz7NkXJdXU t/UTQsk2EVf8AuGm/AT5raReE+x15/xrt0Uh2Y0TG65Cg4BXsWGSZ8HYnP2jESmeOATmezHYtK4r y7HLN4mPnHdPPAWrEu8jWt8JyEnZ3Jo+gNS1eoWquyjZNMeW3feio9kDQMJBKS/vwGyOXVGQedNq FpW9jG1dlTzTAX/r1w3qBnGad69auh2CdXhBmGPgGe9AO8y0Uqvaj9YLeE0wxnmFXDRg1fF8Bljt 678Y2S3OzfPvqpKVksFimLU6x2UsxlfjmR8mjhBlt/nv1Vk9ecPsDjB6Kj26/UzkCIqKZM3pQ5fm bj0tmWBAjIfLMX953yDuAMeiLJmTIaiMmw5wzqSQDDgPOgUFISQUNA9Ftke3RqX7F1aND61SPVB/ RprZZ6Xy5pVQpdCS79GT1F1Ik3J13BtHDpQf6wVEN65OCLH2EOjM5crVlAE3bX/YYsYCjzezGXE+ ozcmrUBJs47BQC1OANw/uFkCfHYTEMvOTWmi7DJTnTesB8f9M102yiKTX9Ezb2suSj9TUeDzBHdU RQFn9RP/HiIvEkFTPmd8GPBwXCG5Zgk6lm1wn+my6W/PZHPcmGaQg+QsnOUALIS1DCr7KiKnBZO8 t2u1ZhE1oa2VmL1oQOfcfFCRzzUM3PDqZLaMHU1qtdTmH6wkECR4TafykQm5iBPZwYc3DdvPJxDO CKWhTy+yLoXKAvsTNybnJ3iLQJeLWNDZ3QvejeLj0jqCp74v+mqRMRFL+qpf5fnb58A/Boi4SYbi ak6viv6mX4/833X+mniA+XK0NIFkPKXXgvzXaKcgGnP3uqletzSan4wa9G0+HoYKi/9hxdfBpeUb NfbtF5Iwazi3LiLlYn2OGz7pJkYwGRb4W+FrOVXa/ITJmQ9YmxPuyMX7immjvhXF3FdS5xmyK0Kk OJ1rGn0FUOTftqQQodTZtVAPnWajWHI3U4i2i3sRTBkCBe0GLfTjEEROlSuWh0NQUOIEE0+FxLrB +R5R1joN2WWwG+vCtkRisodVaDXdH8oSyb8rLrsLHZAIlNNA+Wy01xqWh+mYb/yddwlNA5N7NDqe vDYwghqfsmWWfMguStskvHJpO0fl1caIssF0xbxw1J5JgF+cPSjqeNWa60MWu7giVawObTt5yJUB vEwWyUljJTaV9xIkbiMIobtp8fz5cj2KlViIZyBCuwGqOXoU1Qd9mgLNXA68cVCwEiN/HoBsrrLf bwPiJAXfEsafDLItZ6eCqakDU4M8ATJLMJ9cYqvQLHb58NNSgvi3neTmCW95+GiGuaCpUkFjCa0O gG1/rwYwyL4ttF8H1O00zx4mD1dIbJ4COq/GAZk+9Wrm7tWh+zh2ADfmHohWGrKPMVCBvP8RBxpd 24rU458wtMofmWLxVx7g/VP7X3Rww5Cffft2o0MnBPoUa5+sHDehWWGPgY8oCRKaf9Xz5pGhnDq7 wEOmSA+QAEuGjKsoBOFiu6FGjUSYw0cwDrakoVX1SmMyvt6+5exbgCOKaAKoKECy3JFbz/swIxUV LrAQgyPp0P2cZZ7SFD49vCNgHCFydIPA9iXnNgf4zwAbbPBBUhYXE1ZDpEEze6U2Wa+nhIF/0xtl u1OufW8BFFVAHEc2FZKcLtQO4saTFyGYfrCujlh5cYMPCmujAbo14nG+h1o0oHrYTVQPJDmGhrvu tQLiTrIfFsFFo9Q6Fafnmqd9Y9QQNBIiKmyjP00IxtOFevHFs3IS3tZlI3p4jZy/zWOWkRC/lf1+ p2ShE4XphqP16NhndcftB/twwn7HPZrr1zOGs29AroeGWKkXP4R1BDUtPA90DaVokJ+qVGxRyRtp 7ZNrj8AiRbresMfYjV8f/UKKiSsvLIJbxLSzNmTd48WmGytEHzML3d8N8tYpG2rS3JKyqSZi0Cuc RstQddlN07cP4oZCReD9VjJIVLXUHfT187MD9LWUfIE4DJK3AfqFGJmFXdFADMkcVcX9njI2NKLo l6t5Ad3KFQydREu/whYHdwytDnVf4SPWT8f54FY1F6+gZjwdTVyjRliLtkW/B+TMB0nIrBW8iET4 S91SMLzvYphamyDwjfEKrefQkR5+pB1lXpXgPhIYS53gJYsNqc6E+gpFdQBtYGlS46GQ3yMZHEre p81F7Oh2OyrP0kIffCJQHq3p4RA80BiWMnZ8uDW3m+N6z5u1Z3zZ9nJhzUwNKbm936AuEk+86H8r Jqv5sIrk3fJg0BSfDX04n+kZXzT1QCccXs6Q3V6of4uqPBk5vfaQXFbeUOo+VXdYsh01m6fDQ7mw NsgT9PO+0NUgmwle7GF4Z0qulL5/KfOE+hQQ5htzIiOAGYv7tjfDADhZrNiLggkERR3b+/XKcFNz easfEY/wJoobUcKsxDsahYW25dtOtpIYBuFsMtUrE0PzOJTaXdDCPYfbQmoagteU1rCURn5OTKuU HXtCmnkH6mX5Bw/8ZXILkZxLrJFaig8gahjofbTl6Qh1qF9WNLQYtVlzFwdC8ApydQDA1G12RHf0 t/9hde6jAyt6h4npBwy7IT/Z48Ef02VNCpl2JzPZqPX46g/jm81heq5F1mxQwcDuNRXAarpn0cxL IIn6FldPptX+IfQm/z5vvUj2gHCV2Uhfpk+abeJP0esB6ns31qaI4rvL/GiwuaCNBjSicgFId3dq zvIRqtYo+Ustl0A24qwkymIhmfAgnwW7kiUrB4PkeZWFG98gd+jMs2VNoWg8w1Iq7ja86BxY7000 P0/BOW/yvKU23qNnzIK1qJwJ9Hv/gAECqYULvmOzZq8XdaqevJAvVoYbFWWvqU4TtyRjUGPhMPYR Wo3pJrX3+BtRR0TOItT0oLJ6xeIrOf3MlaAO36gkkmXfn+qO9FzoZDdUrpoYqlcnUhENlEPuEM0B P3TuC3OJgwzycxLa4tiN+NK6abE4amNrxREo0rCpoPBwTEbyvdE/xbVt20XO7szo9dWQXXzG6yq5 B9iwC9f7eoEDm1uZfU4E7ssb9bwHDrJPoxenTG2NughdaV2NHzfcpiLnAkFnG2GxXjH2Wp6njAVT 5BWHWFk/RJa2z/OIIG4EQviwyihIhPAvfVzn/ugE7zNmES5SfgRAnJBleTXiBiT5/uIaYf8eP/Re UYe2UQcgrd2HMXC8Pe8k+3fL3Jh/LacJY/aVs733L31O+h+rSw2EYZ5UY2PNuWnZjDu6c3VPHppA 2HhiBX4FuRtMJAqqcZfMIRlTNuD8oK8CSS6t9m7B4lPxKu7FMNCBRrzY6px3bguveCxzQAiDG74Z NKSQ+sTxzT+pPwGOjBw+uDVs6pCJAZDSue0LNqIpWNWGY+hoi0ZPptcqLyxXLe+axRXm+uWYJOSB KXtRpUQ/1qb/PeyDiqfwbrFfhIDAIbrMpDrdH/T5ozLpt55qVRw8RmybdGUPH08T4KbU1zqTfswu cm8aGM84XVO1f2PeCWHbX6Azvy1hEwNgaOWPmsrrdiOYZ1HnvkPSiWKHLsbPO1A0FAyjWVZoss3C 7t+834garca+mTsK2S9ER6ObL5aIbb2ksS4H/wLSy0SQenK9jNIc9run8HHohuhjCOIehnvQ+3QV fmKR55LKrrxaWBJdpZLLYhFbxla+t+Ojl6po6fQD+t98FBeIWwkj+sOpCZyTrFb/fL+DJ2y8DV17 VXOIXnt49UtclW0/EU4A0YvXQIZoYFxzPXcuadvw9yyWpNq1qTbvhilU7h8ar5a1JQO49IrGw9rD a11dmxpJ1nOB6pbrkfi+CwJy1n6DrAka/r6OYhvKSnLtZbL8p0kmutIHJ4/e2pk5LoZhmqK73DJA 4KErxzRF+2PBsWkV6QuGubaZ84URic3QX5g0gEopdRfybL/R2WH9JKIFQPK4qKtBCqkP1XDiB7Se cS/yXR6U05vO3lWfIjZD3H/fgbfxoRhLfbNrVzmncBDyZpQm4w/VIhrhdFPDSEb2vuv4H18yosok 5b1H3n+2i/GF3OmmJvmnoX9ebATsgw78wLkzqyTyOkGjDOB+zhPKLB3ppqPdUs5I9un6813yusZR EE3IjM97Z8/wchofdYaYNF1ZBtTBx7gqKTbs3Hgr6L6ZHPYjcoq18U+O1hWbL6LU2RsEd+auCjLu 0uLyAG7i7KyCaKdlhXxAH+RNmIwonRO5uha7hJZScxHtYR9Eu45OzlVj/Nezu2Vo5/xD8o9gHKwn nCIMewnIzV42gLi0U54r278HD5LgldkJsewB1BxDMcGBJYESbsEZAbkVGvJLrfGN8iQRcdjIRQ3/ tJpXObvdiGjXVO5CCtRs1cTx8QvSenHy+kcIjzrNFO1Z1Ith9VnBxr6boJ48vzRlhhJZfLF4Z/T4 5B3seg4p/X+lvasUcYGcWqBk4md7xCtumT4Zd4MqZQ5kYcNIefJwIQ9bTbwiDOVfPwZHvVSRGEpM Joi8luIQABB1egA6nJWya0o6fByf6bLVaTi49U8aSdZ/+yhLXiA52l7rsPVu6cPzj+p+tFm1SdvU mGPa47kRgjEsnGoMYYT0xCXnXG/ofrkAQwVG3t6pr/MgDQ1Hrx7FHfOdeP373RpbT9pDcXz07Xlj q+Neuexr+l3kWQKSfTTHLNSWtfw6pIVJxDd8sxabeDUbBe3geCJxCI6xu/DYtdN8OAzy6ib75E2r NOvBrpa8yq3S4h2qK5TICMmvRETzf9oE59pP4e6cyKYC618t7acJHfCH4VKuJS4mtMXbddToqolh WetPxwuYm4MTyE6CNee1S6ZwDa3CUoW/IFcp9hxZWM3ZR68u+UglpYnozpIOS+6B4z6aUuvbTKaJ QrWV8DMKf42zn+p5bXvjVzjHVcAcITflGKgX37m1hlGGZ9VO1cqv4nXzGucNSk2v1yVZh/QHxVCu tUqs3CIPrj5Y0RKgOqGYjadkzTLvYzcboUt4DnWiC/G7IU6bo93xZlJLFay9JV3hOopWA2xV3eph pxj66Y++hXrZabgRh9O47CKP55X8Y90dncDaYZMliWCU60vO6mTXa4hGkeVkfGWy2EDU2ngwTZ/A /AX9guFdV30k6X97HXOkUpawIY4txk9NhzCZ1HJ3/IsgdjIoW9KPm/TFcfdINm325fgJ2olJiyqh Ba9vGdhUZlmtutJ3ESEf7BbKVhZ1ZhrpfbQp2DZywGdC2fxgSuZUybGpKvjp2B7kRS2JtVMLqkIb MDyQ498tWRwqpTcJ+YfwVppCtg2Jn+7pe/EhjOZO/Of/Ma4snDZMNZSoU1OLHja1HYWQsNWYJ9// ni7GCDTBnjJjwJNDelFU+tTOjzpH+ZZvAoRaBX6jPm9sqHtQuHUXB0j5xWQ2ltbOK8mStDdHVsas gvoDzIDs6f3N8UW+ivLK1zdHVMb68XXWs9cY3Dxrxjl/v962+RoUo5Rsoy9ZbXnafdy2icVokP7r 3QAl+4NA5pKSbF/5UvV0jrMVRm7cJTYDnSyYhzU7VkaX3vyusxR8uDBCzKezU9pgAneyTudashu2 J5KwaygTGCtmn1BUelPjivOaKo4ATtaipNPYaR5kb8g/MCYxCr+kKOO4XCBLsh6sQKx8iBHCL57E oGSiRzOh9Juy+J1IlVKghYm/6TMgpEdJBhoUJSyfDEfy+yjpfXn8Apuqvxq6Q1co1yA0u0otYBTc DOtmLkv1BIPyo+3wqFdbRc5CiXtz0BNDaSlaPCbUFk9IkumL4mcqBd+WW0ZkJ/lNbpjBLlrofUYJ t6YRGN96G4ZdaieO75ik2SE+c3X5+RMLhJdEBx1IwjJ84Nari0sSB5JI9ZRUVFSlkjvNhyvv9WOA +4xUhtZogUozzRL1Trbk+vLEqO9IZn/dihpH9sMM+oq4hraB26jTe6FyV1v2LVWylh3GoC51Kx2E b5Txg+bEk+WQrALrywT60lEBhnj1tdOmVvlCCdrgw8g7MLZiJ91a6FJ5WbIRujuY6QnDzh802rzO 9XF58osX1Q6SuXIES9YzwhiAmMY585IRL2j63ysXsLcfIGtxWhbpgKJ/MXFUbXm8TffVkWVU2BU+ g3WEoCd4YV3Ui6UwyuQCgGLOTabHmnQSDB4CGqjzmh0mW9kn6UpY8fdhCroI+5qMi+ephw4gsmFF ZxyIMvz0qIUeuld8mRNmcQ+Pt/LiOVb5UO95Ih0N7GNa7+7JwAxkwx8nFlC7p4679pwAyV/n8uB5 wU19SzbSqC5dWU9u/d2gxlvERAI4IKvPCeMXScYE8y9LwDHZkzJ9+aOReC14PIAhdEZICKC3yJ9n 6qZC+zWGzDQg7gZozRNrFzKJxhij9MVi6F+ZxTE40pbdsmPE4X1M2k0yAq9tr4FghgIrv9KHfLv+ t3gfxnYyMVlDr7XE7lmywcrb5LamL9CeP6ZpfOA9NMSLWwzgE/7SmLdZ64D9KjmoI7iOsIKA4aGE QwHQjPlKJFQhdiNMl3SRvsIUeetpDOOGAqBRi6f6t6Ka8SQuOHDgql+4kmqApBRfHHxhUIw27Ezs 9yMKcEUAl7oFCCthdDXwnMkQnAIlyYCCbC7LXQW+aCkoWqVoPYKlT9oLK55zFdVLdFKk+dXJ5gjy dum4YTGmSLSeQxw98E/66A5QOrL+p+Lwu2+CAaXPW8v2ZuqQattHyRJM3JXSzqBnv34b23lhQ7MO cA8PyH5Fb5gaqiOTaLYupBDg0NezV4XXLw+QEMQIo4XNj2pE7QOCBOVSFB+gDTszdyerFMAjscOV yXVVmKXCrurXGWyH6YH0pWyp9QJAc4F6Sq4JYVWWTJH7j/XwbapDKHR44fhVHc6S2Dlvj0y5Rub7 oBtVWOLMsuycMtl0EdchUswzkl2qdHZVVMWYYJZ8NnTt3qltM0o1VQUJUUL5zsIr3NVHWNL+8uWX hnMvI1+MKeNKduTgabxvIJf159EP+6ep+NlKKVec/k1PkuYv8WQaCqAJCBnUdsagfNhT8VePGSqY Tzv5raoFwLMHAxjFodAcvjtGtVL/qZpF8UQFBogkfejPQXI5TQgh9O1MMtSlHcQ8z1wJ4bYV4AxQ VV2D5dVAYgrfgaeLzbNNFJjMVDU/y1Tdx7nelGc9AgppuOlGqnfldgn2c2NIxrc8OXTuwXpg7dlf hr2grNFd46p4nVFfTp0fVUbvspSQL8j1SZL9PyLI4gLBC+YdPKIZ1f33oSUNfVuWSTKv1dsPqyMB ju488Q6wuXN5EqK93X3rzbjYIhI5Cf2fraRu+iFQpGjeJWQm8E8dj128Bf9N5PBMcbvl8oKxmFzL 9IbqxipqukLm1nQjv3eR+jLVYt/2eUoswhzQo3D49oZ3KLlq89Ccu0DPqGdn97lkyxo/Suc3uNN4 aOBqItKHzx2UuB0uEMRkZ2WSLb5Iu4814sfQkU8YKsYj9KTh+3yHWLMhIudcnRPnICMrO25pFSJA 1chvm1sqRsdDlXMgOQEmm0bpx9eTtF3cY3iLLa6ohHOqQNg9kvlx1QGtfUoQZ6x6NRuOb9UtjI/o gGwAPvrfFWkK98Wngs+UbQNGqbRZJgwJfXTGyRLB/3fuCOXQGuzVABcZXP8qJ2X7ymfDDJSaqFyw N3rA9qpLolJAQO09G975q2P3GLpP9KANPaeWt9T2beb0Dw1p7iaqNyEFOgmM2Jwcv2uUx52CejkY uR3mM/ev2e5/szKZffYJrKcBrpwSdhF3eesWKOzRImg+b/lm0OTbmErUD+dY7KHfuQ/CKr1K58f5 agXp0F+hsg1u9uEHkvAm9Y7oRJsgvMs3iJMUj6eMhiwrMUWohrnTpiRHfjgKTWOjBYcNvL9uoOfI fBALVwwjUkjDh36kM3msaroyogC1wd9Yubtv98zSo0CJQrzldHji7wTmFsDGdGbz24RlgswxYStz /eJGbizXuyH6h/lkRsyVKDiIwpDL2bAd343b3UEN8wukQanzf35qVM2/d4nrNva5cfpesSaSrzVC rS8a2MbKiH8MH2YqTKjN3T4OZJnOHzHypOTKCqE5DhArsD8cocZQz0d9ndrIuDyqpwPyO9hzEvJl 8qg69z8NIJSEWBQLDreIenUZNmHj+dsjOQsszzsFYYOYXM48BHmrJtRmFWo0uYrfJrx7VuTHXJT4 SQaKdMy4cJlaVoMkFpQx2uTvg4bafhzcjRstEBSU+GUzYe/vwzOGKbj5V2RfctJu2LK4aEW3x/a/ kI9vtW5KBLhTfxQnTB4AK+qw6iBpGKIIH4199VO6qvHBNl3Cd4eql/N4QTvO8SDc294TZorit+RJ UaE9Q0q57YavTl8diRCyF7+D1MiAdrpZt8oZYktYxe//s/LnQPky7RoKurecW+x5L/nacswpvKF+ hymmpH3R8KzISUALKoJZWzQChvG3BxIrohsNwwvRj0zhSa8f/fEjXgVkPV30eqpAmJD9Od6R2UMm 4PtOl9tIGrgJHD5oUerr7jw8mFmDPlcR1/0bTQG2vNM45xcCwIYXOObXa2hYY0lyouSmqFnujjRY 2HCVQLfRY1C/sOTps3Tf3u31CUN9fwEIeTBHt+JwSRhHFKyDXlmSVWyBSmiD3NzCR2kkxR+LtsX8 f2ANFjqrw7W1BFf5PLZZH+6a5cjro1ZHZ97HC6pfbAXJYNnipHoZbXhEt270Yn0NQ0NA+kU5dp6K Jp0bUnAS0+gBsYq/6r4XLLCFjkxBFfnQFbETJUo4N+/SnRg/4K4CG2lia7D4G/3jYlNgbT6Nld1j elFlfIlxJJXQ1f+kBbWMI6HHNrXhnJYrDkTZ0Az3gd5rXzS55wGz3c1dqoP0rS6DPLMt++cXoPd/ VI944Odn+ZmvrsTsFhYmeYR8yrdtpoEXKHN/Uy+y9bzRoivSj78HhCkpsgN3568lHXzCjkewPP55 FzqUUtjGCYLfQpNM/18S93Kcm8FdZ8yFGqEdL3Wav2ydoyTFY0ITE+ngPPTHLXA8f8ZZc8D60LMw w8iQczIKffJx3Jz9siFJUra55c8sNdSESHAUlsAKD0dP4WiCTO/GWy3b4u54cvg0My72VNfN5DP4 8UQFMB/coExZr/9rSjPTOKvgZU5UswxTO8ZcZ1eBgRtRqr66lvXzy0aEeLo2q4+IKSDWRCxsRxQe jvwy2K4D57/10Frh9CkCWJw0Lz6FBIue1OWIHHUBeWg9B1eVa39bRq/CdmkjUXwms1ysxKc4pux1 1g/zRhzRjxJm8pqVBdT03HuZncmGbjVNwk5GacelJzr6JO4mi86H9tqITXEKSF934MwP+uLBXNRY I8TvDORxNqYywJ+fHdaQ7gA4Yrv2ZB5Zm+Mk7ErXbIA7OXRfgZ1nM+4SvgI6hZMOVIAITgIYJgGE PzDTz0a1hQ0BosBQhWcvXQNUUOFvAfSN3VYmFQmSQIXUtiVj2JDk8Mq5PgVdR/m7lff28PtknZ8E zdTZH6Sj+Acz+xWnltivh/Lr4GmYo6bgOL4Sr7UN2zWnlMIDguWOfdys2T47TLNSYUHFd5rWON9c VKWTC+xZkB/ikNlZkW4d4pA7Us6QkIg//NsMoHkJhCR5uyg2JwhoeUaXJGYQCT7IXPflxzOGZ34P wXOpoLZWZfweXZ8Sm0I/l5ru7jCUwPUK/NZm+g3OnZykzdGUNx9CNNnlaCTgdV0aOxv9z48TJCHC dH5pQ6UJV7ACBwsxHgjgzmgximBqae/4ug0YzcSkoemrCUqpspfYD6bXqNk8znoBQHI+JBPNZ3AU xeCL0FTCvzqv7SnDn4xHdaMPZpm8ztWGYE0S9jpqjtzmvq26P39Kl0JKMSKZLo1srawqI2QupzqO p8SpKKFSSaI43wXEbuUKJVqsZ8EFXMB3jM5h4EOOnz4/tY/k5VqHor9cOE1X/hKJ1+UIpekEWDOA uwFvS3VeVulEj4K3+0t3qnfftA94Ad8zhX6nXS6tv7tnLdyQDBq6zn2qq8pkcmzWdCSH8J+tbzbe 8/JzFknMsSz+lNlwGMm+u+oEGcf51kugVDzVzUfcDF0Ykjt9VrjrLz671iRzggIY9PDZ9guoo5NK mQNOsFU/Alua1PymununjJFUafe1UA9E3fKH9xLBFwY0QWZtoaynSwgTBcJ+FPybESiIv9C+7yRc jQt38aggO4jLqAzLZ9qlv4RJKbuxFk9lXKOeu+O2OAtSZxomGl/GjZ2XHdDEyWgkzNf+VbKxceb9 FK2cNnrUj1MM31EFwjyl8NlIA1/iFzYn0NMuSmZhehDFqIOk+aYXMAAIYMc8C/2FtXFK5rtm7K+r NqvNjLHhxCTY+v6WGMAN53/l84eUrraAva2Q1lqx9B0K4N0N3k8Q3+eO0pN1QzR/cDbigJvWAO5W 1ZLujPFgQ6c9OYG4ev3KIgYyG9voLu+6z+CZl9GmcGj0gPjRFiQGl5PXIhfMmOQvgivd0xJMS9qh V4Izs+k4wRyoN9zF5oPPk1uyk4jruA1X+OScwumpPkBH0Qp/aQ3ZWYlHMfviCerDYUNFO8+ieEcA czTsyDD3qkpW0EDY2CUPuCBUY98JZeNw8vZmx6xM8YVv9JcOtOor35Iaqk5oxvNMwx+daKSNQxQV 9l7KPj4mqPIAijljRyPew+AP0zImrIfGCcjCDrdxD/EJAgB+uhnGX6/f+/EhuzfnQlkIcyM7NsqV jUhNwXXfhmHlS/aRciujN0xUz/izyIEqjrFXgERl7XcYIdLw+M7d41rsucyq/D2EM6/a79Efw3de pdxuZ4kvuWpuBW2JhRm1G9EPiAE3dR1pJA1XIBayl2dJYPGsZyaGvEUBiFVUn2YHSceiu/vdrsvb G3g7qA1CeYxGpngSYhpi/6DDn9bmSUBu8eChD/Rj6zqEibobA5fpyxtfcAc53b22N0MQesyEOAzY MzX7+s384H7Do6wYO546c1HXC0AuZmHKtv9BOwkeN53G4Cqh9veypw1+4cPYzAxcdXt3MQRToEu2 XH8UV2mFw9qnKNRsnpAMuUzUsojZ/P1H2Ct15VyVLVsS6jG91vXASlZN8CSKl0Yept1mAf8/KqfB WHn2PvuGL2IK6h3+2qOc85FQt9XYhrKJB7cizSEBD+nIWEPwNikRBiKwWQqMtfx2d3J4QNJZg/7x 5oCWJ26kIAIDKBLbfWv9Wv4o6lkdUje1sEm2lv3q0zDnlOfaHXDx1y6MyBdpM8HGbFdnonP4OnZ9 /SSvAZuIXB1ti7Hg9dZO7JqoUY9lZQV1iJkpqMMLcHAru0s3+2zvOauB6ox4EeM2OW+a3UV7bahi RQAand3lNURB76L6Ufvk4zMePLdyvqHnDPDvI41GL3GU6+ggHoRYYxlMyEKDpHxS1lSTMhIQuZFb BT57c+1fUvu0+0guAHJii9l3ZE8nDXXeI/9MO+2l5J9uT23JTJbxLkANcyac3NsYjgyRZuNK5clm pB/x4hMgwnN7vn2HsH7QJmtK93rNdyKo42VT4nISK4EWLL/raury5V/e/mU0yCaPcJGhMMqq2zsT G5YRvmJV4EsKR2HUbGhzITk/ltNNMG4ABOT6UMbgEWPbSJ8MLPQmDZ0Yp+v2Wt3x3hoiEtn2EcCy 9ZnLTWb/1QjY5BGeV2alqnLoG7gtIJj75w/9hUxt+nx8lvHCDHYIE+C7K/gqj6jFwBlGrGE54uDZ tVnGGSNVYbMhq1qg1vhNLFqvIGm/XUoWWdinPZqFICaEKHwYmkaPFj2fMU0OAT18aKSW3d+VbegJ /WQeN+HsctH2AYcF7Vrk4Fq/rS5wrD4JmySD2oxMS0IQaNEbwCsEseqJ7VlAu0E3ZG3XXmAk806N RXd2jD/7mSe43C914/+CFab1Gbp+Lc9LT/jcVP31RL9KAhaF9L6+O+DHRrlCvn+o4rKBBKFEynTS L2wPYciOsfNnPmXG1unVL4c7FYnxTUsC0dWcdihsF4Fnp4w+QnnejSCTXUW4ztSpwn1nTmIG9WFG Jd1F+ae44/7ZkR8BLEW2cYMYXBmsimhb9u3jnFINICZR7MWP23vuq4LW/E/XRl8DcL4ERjN2RYly WXsdm47VzkoaeWXqbVyLZXBzm8TdxRWT2e602ezTa1ipZcoMpC7bNOdwSAPTKtsZL7Q7UD4p3qN0 dsCv7ack1rtOsnaT81gaeh5jGF/lk+hZaN5bO7yZA2lEaa3ylPkXrizagedbxuji4A4TWyXBXLwe vlv2abZBSlPLHysdAvWki4yL1peLKw6dQg/soqTAacmZDAoCliBnJDi9Pm5Wkxz6jZ2X9zdvocsq vBrm6rnMNGwjMA0nk7C9bQj79FTJ6paOzm+rSPhP8zeWFNVI99TtbtvKEleEPW6u8PftYFVZyNe8 Z8/YVvpflMClMxIi9TmpNkPsm4D64QATpcLzj4tLGpM1c3tQ3L1hEaBBNjxwZ5PpEgTv0ymD5PIV kpNp8W0CaUfwYzlKlv8+bOvK54RVs+/a6KF9NrDpmckaEHFg1OwUVlYmFjCg6AnEu6F8wNKwM4++ 7tFk8potKmGD0ATe7N7qQnaVZPZgLQM86V32Zdk25F9MywTL+iE/+qaCTNPVZMPeD3bOUSOGIpTg gxReFfGLKjHSKxZLQxoAblAt4zjG74qFW93TD+8YFp6YfIITygaV+HbdraBARGjgU/gCbmo8WGeV ztBorXrTQa0NILG9cM+9oUXZiVar8/ulpAz1K5e/fNGArDax91AfpLsAKx8CHl/jo25ntqtZu7A8 8nvaOUC+TOWjlNjbB/wO8Gx+3hd+v4PpTvU5XizWG3tedJHpgT++PYM2x0TQsqHPc+LYQeZBef0H fGZl3LgeYclW2Um6iueOuq8SQageYAINCUEBwNfco9Cd8qidME1QLQdAmcfLoGfioQjf2DgSCvsI v6a4ZPlVCk+PtrvEXrhttiItdIYtsw9cu1aBS479yRvcAIUd5ZsTrhYwQ+5fG0XhON6BRL/Kh9PT Fl3qbejhwthQ8s/pfbUDYB3lDIs/cP+bZpXgdaM3pHY2gN5oLkDzqq0tVdcTWT7rKpt5AkoaWJD6 QF259nmobM8u4dm3/Sx2ZfPdUeZIaDs0J0xl8//QEJY9IMyPIERsYDLy0bZGm4xAI7+/Zp40w2Hq RllK2mFghfCo7s7xHqW/t5ZaxC38ZhLeKZCdsqjCo0rRduGz4nZXkzMP2ybUuriYjTDnN0gdT/v2 81+gRYpNZliRPjbymxew53zjaKurxSm4xBEu3AIwmGWplyK93+7RsZJQ33D8jPu5ib6KniWZaCRB Jw5GIMCrojHNdvqI0ybIG2XCvgkV8ZoW9qndXdIrwo//fCHimEtzlMVc0b/JfT+rrl7nDa0+WZMH Ym7KPKZHgXsfhk3b68yEBq1nntT9S12MWISmiGVriabL8Sig8H9+qEA1EectpoP+NJxuM0PbgfXW v3QFA9E3qjsJVF/spM5g0jp1CqUqTNqejH0BxhioMcEat6xwDHxK0kxIRY0w2wSXBP4l1TYhYkal o/bZJp652a9yKRJMHFkBxFlr59JUshnGGRcq5pBBD4kKm9OtocOpYcWjAgvctoewcv9Ea4O71Elk KZuuIFK4z3fpfTfv3eMODE8KHXX3yFGtrJo7Owm4WH5yzEVDN3399NaA81s+EJo+9rzLc61tMx19 9yflDyUeBKqc1JRSXLa/NzDTBQMGLliG5kb5p8v6BtWNOcXEDW0GZMStnhyXcGK22CYcz8adFAdk fAxDwyTy7TXLq4eLlE+yQVfSDjTg48MgY1X6eDgUwzhB5b3wWKaxY0ggJWqcN6tDkpIsTSWpoGnC DGosbVFpKd9udw/8KI0udxZflHtfXwa+s7KtNRPfJf1xIXRa4V7S0Z2MHAllBVfbIUV9UFtQ7SiC hYFotn3I9Lv9CvHKlaGYWIrWHnqt+cQvkBeGtMd4+dehbK4z64h7/fQW/Z7q1HgBsTt4rmBaoQz7 yn+vTl1LVWL6oOvCQLYVNtS/mgFVAd5dZmEDpbhohoZtBemxDxrATMszEE1Af/gDwuPSoa6SJLqc 6e1byD/WhjbDdywCffFCyY7+iwr+kgBPMF9vsBP7s8rj7kC5s+dRIfQGBPSS29OKg+vpDy/9Om7G 5JOm4AifT9Dtsc/V4YXZRFwEdDsxtdz5J80eO+GeANEyuO9cGJupHi2u3rKIOgfKC3UjLkn4sDBR YzC7XLT4KnF9lxOojLDDL9VLCALlx/vwas39RKh8190OZyuufmV7MCl9nAlzHZtd+0dH93JALoys 48up/udfJk24NiDULNqlwv6UEf88FFly0FOiOJylyspQb1STKFyi55J+2hfIOvQExyYFWqHpXbwz qK2AwmaSxuJR3UO/RtHQLdRPj3mmzV/aFwF6VXqxK14WUQ+HPEb5kJ/uDHVhozQYBHm1qM3qtWso 3mD5pOLN5lhxd1GcdEEtaDHQBiGjUHki4FwG3TpZvRYrD9A2VtLUhtf8zhuW3U3u3t+BA8x2l7Qd gtOTuqKQ7MQes+phgK+lVJf4IfTmbHjfHzpxA3LWSJ2ENX+Gm7+IVmL7+6SOtELhsvUSK+zErIUM jTu6XSFEpVAZDyviqbm2BdWLkKhfoj15UptSEFZFmlOwRVermxWnbrrnqo6C+hOgZfX109j3O5k8 3ppLJ/0/UcSvJ458z3BHc3w7rNNCazBqR20eAtb18Dg/hj15nmdv7sIWRI4Y6ryIFmlfi9A5MLS/ S6sVq6IY/D8z6m6Aq88ohuRTBgwYIldhZoM2KatrJ9QxMuo81x4+oRZ3A1YeQOrvw6YxScPlEzdq nTgrfebgKaKhLrUA3tzxdwmyh00VxhgCWa55svwqmzb2RlW2Cvkj/Eb2FF6hUdizdkyEvccMlhnC VrV/nAcN670gAosxlfF8tYE/ZBhSWFoaCSQLEPs5gsE4wIvCJbs/IY6GrJO5pc72ONMsl+TXw2zq rtt9WjPytEPdxe75DWqgGaD/WsDnmtd3hVaFK0OF/+39DRuYFtYgl8P4E3lQ6zXM15HSNiEgbmVf +OkQTawUwCt33zhAHTpBpw0olvtyrmnwoZnbWH2sxEPYllH5TbV7R1/lW9FYmzrkLhYeWTkH7vZo xKAoU/PhAggW+l672k+AGLz/BVqi7FwdDKVsfdUSeuNkc8F14tPm3qAZgxTKvEnFali+dNYGlS/X uu63rPKROcIdMsmLg8VJ/aTs6NbOmmJgvKICVBGkRNyqPPA58RacXTbAP+Y3mYg5RJUKujzyWt9O mqYjXTrt2xGO7ZS51SurcclwLsuOgbfGH+tXfwDF51IGSMeOF10bLVzXGqsQqWU4t4ox6neDNYNS 0k+4feB8/rGpIIq4UMEhb3vdSHCQfMrDSElaz3fPwKs6NYsD6n6KIkRSYu6lZl6yWXYgdXbWX8dR lAZ4JtGj0hvnT5075w10MMMZIn9lJPZeRUdLbFLP+duw+pgbdlHjVcaa4lqLK24Vce7OdB+YYis6 b0rTT7cLYo7vLl8J68t1YKdvJz3bH6F+zO6k/aGEphg4FK0rIN9sU6ydkqY9jMuxFNpCbllzY9Vl sgQnxpgx9puESWAzhlgiFGY/TKE9uR+RRILlCtugl3EAnW8vb0T9Smjy8KQaLEV+87E/+c7zP+Vz 64y2K8tdBFa2Mi8j0T3UI6RLb/pobm8cYIprzJjjCVdlp+hm7mbVL07zqlkeGYDJ+quee7R8p3xF wHX4nD1tJSu6N1MfUZiY59cUPDK97plOmD0bGh17rP+g9gdMtFV1mjs0erR+qG3Vw/sLfAnWE+As IerFpsCovaSCT9LzHy4TnPFlUkyV62yOkw51RjTGUPUMfk7S04Zg3qXKv/wWwMlOqGgszV6EXmH+ xU2pgo1kzN6KuzvkhmikMw3lcAoSILMo2PORSlT0W2L6noD3n11A/eUK0BjB/p4OS00vSLcmG4l8 PoZG6dDr6E5XfVf2qJswV7PY+kP3dWlpFCcsS9KOhDYA9S3/imwJMYXJb2TDYt/S/Gu3/kgONYOP jhoDApZsILl8Hpyw7nw4jAK2qYGs7zJuu7q7LCnzufjaKCE6XSMRE5rhW7aqXqL27ystoPe/hqSS vryMtaKgumqrcp7V0YRY4luk3CECL6yCm6xE6+JZ3HXC/m9Af+L7/WoDpd9n5FUyo1BuxAb0a0Cw WpnDx5+PHuK1jSE2MvtRBuW4hLP3RKWmaZ2p9soEeSED3ePHPLbimg1ZsPNnNxYeeSCZ3410/dsK wVadePbu3jAyISKm7SPX4DjC9cg9lUVB5R6udN7B/l8C/r7GUyUiPdaqSU7jxldXvUyXn958rxEG b+BTDz/5NfZs1N2NPVI9XSoqWJ9P+u72UdTSVb9IxE9rfa5jVpIFC4UnBhPE4m8X/x2Bl5vzvd5b xLLgZAovX7dhN9vr7p7oEhyMDv1JjoDuKbDC4jDdFf88CtY2tOWNyrSKnS5mdhzvG6TORjmLTC9s MjUKtBnAhg6619Ay9MSIiLnBiurfpOUSVFKmVtUIRVLNvEuu+3NQpC6YI09rRhks6ty3iwvP9ygx 7AuBTa31DHZgCcT4MY1n2RaJv65UkmxzIROOM/W0HlizfNbZv5XHMs4g7cMUZH3i92mZNA+A7XLX a0O96gW+WlnhkeTXXyHlo2dPU0E98W8tuyzoLq3zG3sn4u1Og+w5hbHZ0ve3CeiMjiHIZ/0rjUbL kkrF8bsyLLbIjPIJkKdTlq9twPFU76QoXODYFDK1xXx3un0sdlFZw4ccf86ONLhpGTHAPrm/ghO+ gEIZq3w04LkcOHkFaRwcVRO/Duc0cFfGVfORLCtrsP/VCEcNK+eHCf/jFTW0Ep88VaVS1+B60N8o MgerAc08hDsmqLEbvRPIVNhQwYeW93TxMME2uKVV5p1UbVVmzjsNDge4dx6IWeTKtaaZIv8uSKay wrfJ1kY6FM+VEH5x9YpPsC0tZtvUflGBC3+u8a1Qz84PUo9a05oBSU1vsN4Z6edA9M3f+w7nk25g zSklwzzj+3YCTwwZ9cneBiwrE63kSBEbRvX+PCmRt/0tLGvgAsdmb9xQDleF1OIVqFiU/PO95bYw 1QM7P9DWd6+Wsj43wS0vjayZqGawkf4anwo1mDNEVMjPWrQB0gBPa8Xj67WdmaqS/dl6l6dzVn3t 877e5tz+gsr+BSkQxgbGU7/oLyT9tPnV7guBQ8XVwgJsVZkBtHD56V3lsibq2Tk5kLDRz9dcdvc6 Xe3NJLjhdUlNAau31nNWfN8L6Go5Z9A6iXurI3BqXGmSH1DlGIKHn5szdCxvST3p5fJ4tYxavQJl 0WosI2cEHu+HN1c7/hF9YOeInjabSmJwUyWxPRQQ93rW18+C681APCKf28wPzn6DtPgifEdoyhfA 8zWRp7x/L5dF1wQIqfhanQbpKQIrAzOdB1Dik1+1BAE4PTcaxgwZyqUUijahaaILauinLfp8Aw6g /BKK0FtwvDr+YpsbttWJHBWJP/IPMoDU3o0Eey17w4oKpXnSMmCVYT52du0QTHba5OOPdXL2YMhT XX2l4ntxkSgxxEdmy0tJUxqFYrjha/6g+2T09wl+JFzxlQIspMrJT4ijSWnjk8horJppk6TUxoVv zjv2gBihkMgmNkARxL4XNmzLo+myrFSX/VwiYR95Nv8d2DuIL4miKGguvGlm8CLhamG7mLRLIETy ozUUFAEJ4VaQM2uihgvaqpYV30nx7c3tq9sVUW7AiD+/2sySdysPM5/kUCTT5Umu5CIqW0nrnBnj BvaFyJemUw9snnSSZdBVzCZZxbvSTFsn+6tigqvpYCouCtgXpCTGC/q72HKAFuZ0AeWchRPXgI+y ZNFagFPV4nKtOr4qFHF7BvqgcNfW5y6eFnjPywl28sPimp0uh3tZLLToxesD9zGMHuTC5XvO7Ih+ ZN0ZtjGveb+zJ9YxjNA2WH2k9QdrNriC4NkW0pT7W/hy2mYL7crMlUCijiz+utR4FXMTsefLM/2r GgBVwucFgTPhZHB+BCvFGEpBmdUR4qoRWhphN5WKh+A7Z3LSLsVxWd1xYUct3tVh0ltiRje6YgbC 1IzGJlQecnxqZZzJ+bDKGgXL9XLeuFwmHPYbCH8C+Gm8evhANWXqYBNmmqlzLnNgew1+QuJL8WT1 o8PJJSKnAmK0VX5rRcrDRbTB4+FD8zTxA+/jAt3eZ3j1Mmr1ZGDgadlPYRLOYcIEPN2ufMnGwA7I mrF5IjLDXIv0fBVgjuAUkLkh4YlqUOte45lMcNsIOr55G+IEdtMT6IiGIEMeJFRXQrawojZ5k4Cj PAemFbyYfZzJsg+SrIhxZYRdJ6tij/4BpgRr6twK+zJ1YtmRraQCnLfNQQI1n9rRFQkowwLXYMv/ YZYdDfwbsERaAkwYX9Zn93g6o0QAYrTx1Ir4gld2C7CSYdxn+UcOHGt3jaZhWaEJbukIQ7IbFBaT uOC+Ojtfs8Ysc036NftHkyci0ahNQZq+JqkdLEqynGzEkDHyhUXIHK3yfs5+jm9VG4JcE7cH79sS XOkZVMYx86vjScyACj2vwBc9bz/MtzY/6j9LB2/IyAygjH+UCVrg5GXsFdVhKj42Of92KNh74Pip EMIOj8zNkaKsVscjjwyBbD5J4fM/YcfNL0nr4iPR0RzKP0V7Q+nWbBp3vulD8AX7106phYqQdAjY a3n+NV4kL3NEbd32YF1JRiw45GpznYUw906T36vYDhKOqi5gFk3f4MOs/4G1zqtF3Sz2TuJj3j9k wxeyKLXq37RB9e+yXREMAMtAMFpHnZZTlIORYiz5KGpse2aCS2jW+vP5TRAhoRkTayeitixAKtun bFchEHJxm34DI9PLxgZdBOK7+4xZIZXc0TLeuOg7JTqi9T+ev3vhCDuGtDmwF2+0bfQ/6P8fNdsB F+NQPuIYaVIsqMp3N71lpk84dW25JC4DHnJWIMWaw3xO3UBHqE8KuaYLOUhWffxIHX0S89XJ4F10 H3jGhBS1s2yIDh18ideVZhoknBZazNJIoc9f5X7ZCIRRaWZSiJ53HpkfxBrR/JuskukmCXvztoIA kgoVAMUMaFr7K5gF+vEYVI22hlybTbg1cmKhJaYJa9qUTFUHiFPoOfIXHaT8M+oEUdGE1pSdwn4t CTu36qIV7gm+jbRji/wt/LE6y+U8ojK22DSqZ4RiVkL9wSHVmm/PwfihC5IhhPn9YkRRL7enE4qi aVUAqqjHVGE7VKzbyGRfK9OfIVFoXG4kilvR8Ake5jOZ7ma4mRh5e3BNyAY4ZyhUK+7/IweL3aZZ NIbSZPiQPiIIl1DUvIS+Igw4ZLP0YhD/HwcPi3HcqTfQRFt7pdDGJ8JRMWI6eZP/La1PiXLcDYQb jEkeuOZmgWCZVZj4+htYfz0YSHMCzC5TGPpHp+oBtujmkuVS0z3c+wobQdV3fjD78y9v2EJMN4Y+ GmqruPXaOt7V+nStSLxKdGcddBdeNB1PXG9Ukay/clKr/JpHvY56bsJ09B6udlesqmmhBvfBtE7f re2XVR8kfLh0yoA7gzqsAgV7PFZtskRrTg4mUNXdbjSM8k0z4Lv1S46TQo67ms3U0dRCiRITA4Ch mE9gm97OkWIfDkQrU58YUPD/OkjEWX6OBTT0YYvIYTSnpB8e2PeGQ1HHlpdKBzGLcKnrPzX7yaQJ HfgifzuuQ0feUVIeX3ws+O3Srcym/y4RRpAlZi8ywxzanY9pFHy8RPfERH2yZJdBVwMqHRhQCkyU vWkBVqHu7AC4npXYJGzwtncLxcJrwZpcCUWplMML7Vh0VPZMCwnZRyo08TnyzJh0c4RbFb+BIVnl bFmqMhf9Z1PUEXEUgz2bUUgXr7ph7NyELT6HSz5i0JAQqM0t+UsTuu0skal3uwVgSJ86ezWHAAv/ TgDCULf13rH7j70a3oXyjK+fa6xEKfLD+QRTq/FvN4xYJdtNH8zhZvSa3DCOJSPZzUli6OVwi71p NeYpqA4l3hhcdswUERjK1B7RKSZQmnB5GWjKpNecdsoUcrZH8qtyUO7XNgXRxd9PZDfX81GDeurM Gq861gbDelGfw6Z0R1wlLqaPZPIkxDrFOSkMH1qNO2azgePM/9xnaNm5V0r4q1fP8h11jLsqiBGi hlq4HuTHoSIQb2Gi+WeS/PsadvnKClaeX+FiUoDq41mlIhr/nNSfM1dURZHbiBtxLIOWAUNQToAp sPkzVWDU+0oll6ZubQMas6ZNrdjbVEkC5kezOLAk2nR2ypa4Scwq8rlT0qYtrpQOV8SHcUaBWYXM LQ9ZVRJGl2W+c9yliCHMXhgFsILRbhfsRvrmzX8erJ772Ws82fwXv2QtJ1Wc1xkxscEOWuqNtCUT rXc35xGBY26THus/eruNgUGJy7s+xRT70s7H7CEmdw4gcqGTz5/oSJ5ZqDhQH4mUD4oAkPAHKNSC eddUxlR2KW06IPNheVSeyun0xn/agsHs1zaUBRyk4Nj+tHMnkH8BzuE4PpCwpoGzMTaEbvtip+bX UmEToGy5FhVPk7WmEyL2OtoAhOlW8vz16rVT7mWpDjhNewVlBF/wmAQbxCByasP9ZW1Ny9ibVF9D BrHSpum8gbQBh+OTq+070pyiS3lmU8xeKNLUBDoDaYDcXQAkekl93M4l//ojBatL7+Z5KB9UEIBu P5OQmUEqxVVi2378cGsPNAiCWiNJinUC/XkJWNWnuXz20UTH369og/ecsKuNK09elS2LCZG/TYtt vCfGFx9lTSEeR5QJN91RWoQ6rP4ddS+eUpPveGHJqKYOeUbJN/9UYiBIHYHD/KsdDbbS+mB+RxNy Erc3bkyxsl492Lymc7jPfoEp9NiUDQ9eDH4XLY8T3w9Ec9G1ln+bOd/8n8JVyNyObQXXdN3t96HQ 8PUrqOFUPqJL5rsfSettc+28ZxfyRgjuEXmNK3JIzWuKl78QPxk1ElaQH+zuAlLwbkvIsERCpkkc lMrgdYAjnC/rv2OcxQ9s2bkimlAq+nZdQfJebBp3bze+T7FfQHkXavHu7YyJpMmFBRCatPsIO7tV /Dn8Nt4uc6mstorvLbdaYPwtGne33Dou3P1yzIHGImupo1LaJ0RNv8NO76ROPdHV2HpHSSbxzT14 horq4iMDQgydgAYpPV+zEbhx5A8cKt8SLr100gfS/Jnv0M1YRYl4d6tYNlQSlOu5XXt68s+AKiOE ddKsKVFZsLNVhgAL8rHXc2XNx7q6oW2D1qYn71MIIivW2Njli3rcTVeqHSXyHuNZQBHuZ0xH1SND 1EzWlrmgxSbRiUt0+VsuVyJ7py4+Qv6cZpRWHlLiOG9A9jwSCQ7hKZeVs/9q900OlmGZuU+xbG2C yn3/Vw1fqtGucs2jIGRzXNFnL0TaejZV9WWRBlni287W/kjnSJdSIKB4eUr+wOcNX3+4uJIuCZqS M5BQw1znNSJtX0jUN6CEF3S5jO7eg8k3jAsCPjC08BajY4lQU6pqiMWFfKd0Z09wgglqGgeZfsB4 /otYNLMDOu1gOSHLWOGhhZfQx4HPWXzZFi1FwNEMgGqm+SfjMjGDiaLdmbgkXre/4rKyEcIPO8Nj RjJ6BbN+JLyc4mzHTdT4QEpH38onbkp2j0f534feudmYYq2c88HHmusFVBBGZM7PXW3a8z/DAUWM jEic7wZtASx9W3nBBJUI6C01A8H0McIpOZ8O0N/kSuszSgh6TDrCbZOzAsQfRGN0MuBNra9LOZUq zRb22cOLod1kyxRAVflOU1RG71URvJhSRlomsbYtpqonUwlxJGA6uexbec+kaCTp8OL2ncreheKr fejddHHE8w+Nd3zPuBjBC/7Fze2U+TBKOLumIvRhMyyEGocvcjAbWz36ng7p2o4jCA+cPXATS04P VALFmr3LqFC47EtwQzJycnsoonlbaA5tva9JMrZeZTXNg5fMDQE/k12cO771sAPkKYPb/t3r5bhJ xvdOnCtql6T1Rca9u1pF8OOnjJV9/IqOREtp9sFzivSJ9SFDJSsDV5Gap07cEwAzpwJ9uYo53UlT JaTZ5sF3OXCp/Ja6AqZ93VzOjefLhesr/E4EhHQEx+iqQ/o8zfCWX5oS6uJlb2X+KRk+MEGK7RbA wHymR4BSF0qLZd6l0RmeNYOw/JrWRXKJ4xa7lLGsnvaR8fCY+UcWl8AEoGPOZwdU0JhnVsnDM3sw Oryt85+dB0gUzu61+Ygb0smFo4PFLWXD8HEnf7aQSfX10ncj8HJrGLs17UKQULO8cW27v+yv3Rrv p283rryQ15mgpPVuKqH9h84QYQ5/2mQweB2qFBXnrV6eJ9x7ZavV6cR67b+osN7Nxos6DKqeAYbP 0dtHTOIIiUxvwDv4U77IN2sgTq9/PcLUN8/sg/CYM9OeYSmeGLNyFqDy8RwjVaMZSSkJZ4UvuNor rbnd0YWOcd1RvIU6WJWh995ojp8kfQy8gbnGaKNoiRQjkwl8TkrK9qC/Tg7RpsqY6VL8LaWrIupE E5F2XqfeUGIDuy9GwmpUzz143OZ8qqgyYlPai5rbFqV8VQdhOpvzkUI5PEpThQG9xe2QTpJpBl7Y wWfPUky3EY0W2OijUqL3uf7FU2j4KT+aSHgCHfLxQffgkwwMFJHJJ5J8nEbhbkdjH7XQejRLB38k OBJKDPVLmnmpxWU+uilNq7nscjik2hHqVzSsf8BQAJfYr+yM6kdMUwK+H3W9ewpcMDnupGrauyq3 S2shUd0qJyeUFZkWd9vZkBZq2V2+byKHHYCiszq+7etcoVNQFcFkKODWdB7l5rzekTOshogP4B0P Mg+Eg6BJDzt0edz4ZHL4ETMLeVFqt/0VJNsLDBOksKnPF4THl+mCoVFPEc9rZHvxl+slmPXIOtux lf3+7bm03NXzAlFTCE17Stpx/ypRBvpXSHF3jS5TxKe5n/K2Qbs8GT96ApNEeq1JanufCMcYdixg 6zGWCnTD3mKFycw/PDEOW0WxGvsFXQj9TNro6JgK5EasOnmAy4P/SRZymqPoVHJfmFzXUfUJ+5bk V+KAxpAQ/RSd34NPQbR+SK6bXivUPMTju66bYs2pN0a5IhsI0y2qdrOONAo/8lGRukRrf2BYRrEK F5nmOFnuVEsCvQRJT1zPadbgrrV8Uv9qUx2FLaM/NFWkL4ThLiiiRjJyRjUubK8FAxvF5ACkf9lh X7Wc5BQA5fYe8HVmg8XNRDu57vBiqDxO8eaVqvuz6fO5VfoDfnex9o9S+NX48D/ZIqjr4MbPnjfg PEC3iVBGyxvYpCzihpwM5o5ojKwrbnrDw8noCqicwOupmxtDKhZQQXtr0nP1D4WR3+vhhhKOzsJk pS4DVwBoI5PCh42OopTFFryRZtf5B2tUjo7vvrgt1GjIoGCIGH4SsmMWw1nBgtbeRudZh8Je7yWU /EUnxRUJpKfk+q+eDWJHYkC02opdPVHRDHFywPJN6AuT/RWjOLiFYortlRhJXKHnbRx43NZMDsOY 7I6q2CjEyR4EgcYQ2T54zAjJ4QbVYxR1ouVhP44lsl+db2Fd3KYSKx+HVqHftLZdUp3KxeAzbtdQ DHQvKU9TDEwhpoQBMJdtcz/elg3JWWoK3wul3NS1ZDO27U+dUP5NWDkSBj5d6OriRnmYdC1E0nse 4JHbAecxXNys7dHXpgG+ddLtQXJhsihh9C0NbGVnf4SJQIlXk20lHkpv3N8qzuJ+Hrdf7l4fBQPr HHCPndHQNsGbG5B6DkIJGhnT23pqkQpwrvACjZojFlyJf321Sejzyq+HccS94usKnsGOfHI4qgsm QsAMi9sw9dA37R8HtADfkSgQQe8FQNBNJALIamsuCivV85quy/U6FFqNjOMirYw+rEsTrJS1lOsD FCrlRgG2/u1in8RWULsQ3SknOXjkGSIhFI3BUL5upFaRd96tjxlSECz0BVxU1CqYXiwjoAe44ymb UbG1FgjzIQdTwZUppTuoadJWmxfjeb2PcpIKqIg/5I5GYRkhXbKFAlnL4QUQChQXT6dXOybleSEC y8P/vUu3DpiFXhhrYx6Vq3D9CW1mrYRmqQnDRj9TbZAaw4SbYjnEViVz8E7B9PNfeZVlOZEyp32t UUbmAyENg8pV9CKTRcI56J/sqgWAAxvg2ozBQrwIjNQzAs3Tn37fQ9gdIwPcJUGkxYo3zMrPmJ6o caLHKmMoMGOIN6hxr3hKqEH3T0ptufPpcWWq6yxAwxHLwsGRyT3tFx8z3e4AvOSg6mzNyYf0NQnr c7qqvpFJVTITUhrb1brUZ5sR+kMpwSjpXJgOia4JrnFadd11K+W/NtTZAsl0ut/bD/FDc7nJ7TKv OU2LwyPpqamqCh8F7L++nQHs0Avijqs+nZ6a2Yd2ul7p8iwFkksC6Hgcb2ZHH0cGM08OHzRbvTxy IVUv1xr4lNnwWofit89IHPZKpi+ZKxO/RECBwdBQwU0fpsu6/QkwRHqexLUUPc76Hxz08fk8z92P tYgQW3T+82Ah3KkJQzJhYLSPTLYzFGHpJF9yCSqOjMle/vARz25X7V3CEuJB3r8bPdzUHgkb0YY/ kxKv6w2oY/ajn5starui00OWNdhErv5AR/RqNUelx5yA3UEJxWgIcBMv4Oa1mHvFG1m3FZuerKrR jeJONZP729Av/Z3ikuWJVTAkPmAuzr6E8I+4tK1m2ujqBltssaKl6BhdymqFrbEJJZYUZ72dZHm6 OHywDGtOLMv6prWlZKNjB4RK7go/D480wM0ijPWivOX0oR40yC2JIJF0I6MvM7vpAYNUnx8Gso4t KA43g3EbPJtjwWvZGeLFzoI0hD4V5cm9L9PModz5BoIwiJ0jwK6ntM5NN4kmZXsQt77ObmearNR8 PCMq2hyM72rLoik22QbB6GIkyLDyaewMkXH42zm0vfEa++e1b4lgoesyYRRWtciWGzYdBDhw//KX 9wv8TMEbXXzQKTecRXnlS2CEACJ33XO+qsDC3H/FbGZYEnmOG1WXyW3O3kzNYrMVpUXohyqEUQCs pufxFTd7vu8JRN3OPRsRIj563GMN2SF/lssf0jslydSN33qSNcEsIDIJIBsqcRDPJBH2VmDpyPR6 QcgRqG2tWzGckFI/Btx6ykHZmyz345gKsV3WKlE4Uon8cfZuZ/Zr5Vpn6V6Y1Zn8z8zTczeML4Uq H4NaGcmFDGyeRfj+nubZDkc+oZZrn2EsrK1NLl1v0Ae5C8YoeFKHIfDT1H5WVw74oPX9p7A2EwHN bXFoDz1HP1+Vqy62X5EWLl2n6O4ouWJ9rdL7V1n0rQeIax3faYpSQIS6U1+HVM1X1pt+clQutfpr DMw2KSAifKV9hmCQDHdIZ27QNpkL9lvlNuhropRoeDN5SWBBa+OvhHKLg1muzuH3GmAb+BIZTZ4a CEzmmfZsO5oXaV2Uh+rIFwuxYf19GbNw6hbW1EN99yd2tDIfhycYRYU5VzDv5pHJELnaXVwsfRXe TXZGzLHwejTfvQuWrDckPMQ8aSj+Fkm8Gu0YfeEfVtJqTaZZ028O4OaWWstntMql7y26nl50wHgL Mr9Gh7qVlwza7NZwbegFyP/aGmbpfaGeixecDxAkhqPY8XXl7r+QBCBactna6kDLFo5NtAiUjBKH zjgRizBJDkQbeT0PMlVZ2a5S2XLJiUGOUtbb61BfcoV4XXCFY7okH1XDL4fuNUaHAIeqc3ShoMCq eZ8O9Rp4lyLbkcB6ytQeE77dAXNMlgkqaNIQEiPhMwggDR4kr1zcY3HSRHMww44bCWajYycT9jmR iobNlOq+4qa5zCXck9pNF8PEnJ3SwkygSptJnPUNpcqQXmDdqoMwWR02cIAzE++LPPf19Bru+Mvy U9UlNYXVuIwAcwqtFQ7w9m2QtGsp/dASB6mAa6by5yCmA929LX8aMTCmU2taPP7hNyq8aBjn4wJK JQuju31shpR/vLKXLy4Ovr/kua/LrldGlmIM/qGoaQC6vp0VtV/zcCKOte+JNEkeB3w+VXx+CK0A 8ozxbZcikP6+gFWv8T4dcZsAe8CmMOA2RwHamafCIUe37kcdgP/JF1528kqw2ehhaJ5N3TPXw6U+ A2c6hj4vdUoeaJ9Z7/MF0QhMx62ONEgX+8pHIV5SQnW4JTbJPkPWMj8qj1nr4BnmIUT+WT+Am8bc a1kc/ZeHgvSJdzblRUD5H9cWRmALDCbvSL6TLoWEr1qUPEYpTD+j4vAw8zsQNb6MJCQyPQVC668k gEa113d0gx6VISdTptwYHuxccwXHBRSS4bQfUtrb0hdtKcET4GouPdfd8hoghSFhipbWcJivp+Lc nstaHfReCFhaxEZhB0sBEU+yQ1aeBq1asBbndo+RHkpQrdR2y/7TLFQ1e0DiQ5RmGb6dJq5OBEzo Uqs3HlQyKl7LllN6WSkF/AMGYyYeQ3D6FFJJ3MJ1zVHnta4I85Dzr3N0sFQfbZFZktM0FLVculZG D1nPtmAK5iRdsrkYe1O0WgbzfG6m4Vlp2HKXQb/NEUgrspJttaezNbGZDX40MA6kLFf3ye9zdjBh YOXWAxgVRAbfBqiwTIKVllvFF33vCmMQ0JN/hwfNErA/ZwCbqMpCYTmH/W+CTdyC529e3NtBFn4Q XVyey1LTL6AMg8o4w9ur2y6hxg3+4x2rzEU455PTeCvQ6Aslf5xmmirNtmFHFh9yFVbwV5DMbtr9 PxxG+FeK/KYZG3ZgH1wT5d0B0HKyfYtw+6OFR6w3udCZwJh71SvcniH1wI3HW47M59aQEDyDNHIm RD/L5iHHiaRgLaHweLTV/ddiqBRjlEOfTkd4YJwVD3Z8vrcBPJoEm850w6WpxjhboG8Hb1ehTxgH 8aF0uB16bHezaiZWBSOqQxOCt1qXYcnnMdir5hEbCiJibitrlRGaXrrWNJ6LCVw8xi4xvewqDPqS FIiBSVbAwShP9xclZb3AQXZEwuG4E9O8O5n5q/cH4GkbQ2zep5IZm/3UvhMs7iBV6oeQA/4oREIs GhmlrZ7nz0MFY3CDyDr/tj1Vj/e26evLE6TKP+pHzvfzLZbRsRUvjh1/BPtgXo/G72Spv0tKgdx6 W3egB6p5nitn8OiFv2KAhqcCAudMiZHHERllWhI2WfFD29Pl6JaQbe9sxbcyQuMjayXhqRFsU42s /vNCKHu9OM65ersK8IAvULOaDJdm6K3y2Z3j9EZ8QKz9Xrzbpz/MffFTs64HI98UC8MBPbYrW8C1 maMZAVp4r3az0sLc8+vOVv45z/8T+iv+YYnzhNa6knIQSxtL3LfbewXrqSB/aBHq3GUILjiEXr9n CYZdEg8g7yR1451t14LJCkfv7gd3jvxtbhwhcQK410wd+wxVmpMYgSL8/dcrWCMAGbbADsQu+ukB SIFEf0wpJT9GothPgmArJiXV7PytX/BGk76kNS5IdAJpC9UfD3gJJsgRHVtYG7XDjiVxkk0ouu6P luuXokHBZFNlor4aPe6t5jk0y/DYm0xSIz0rF2C+Y8B9JXs0YyGFr2H9QLSguSw4Wpboocot13f3 q7M8YhAYDZELkPsXWhgvjcptxFQMNx3qyjc6WhGmcqSNZa2SqyZqqMZXRLOBitlRK4rkf27wL1gX WphtJ5OUNT+Y3muSmlqS2nYIxD/TBdkwsUfPNyVVNI9YV31cEyb8TtNfxd0Dh0ZoCup5STOdBjkP Z8iID5KOm3LMgsW9lxTUM7s7vd+ANDldOit4qhBUCp/5oq77BfVi2oFbHD4yUxNw0UoXXhoaG5g2 w8c9pQkngFUwhiKTR1Zn2rkDN60ij6bCZQfwxFFihGDgZMk1ChF4mzA5b3Va5oG3KO8NrmUEl8ep B9NSh3Pn1AJREdaRcMdhSbtED5eTMx2muz33x1p+5Qnf9FbtFBdu+/5kWanslvtLNVsTqETfRHzM yEkWOuZwXSSQ3Kgi5Vk2eJeeQMGpwctKuPjG3Y43NGnpOAadyHPZAo4dApAfohVZGqLfR2mlvpmN yjPnKzPckKq12g2BIY5xxNM+RnvOG3gLvnLVR6aNu+6/B8TC3NHGlpX/U0LznKr6HmfigJR7+W8R Pcrg7W9ptgkATpioIDPkS/6gSbOVcA/PaX+mzmncShQ86WQ6OaZSazRGTyCL/5YMhXjpPl3CvgnC rOmhWxkRounawfvutqVZ2V7CsBrjMw1P9mNxWoaJNbtXeZGO4/VebN8YKAN/ys5lS1905szJVdmq 15uJNcjdfXP5ibmuqgolh3GaJeSWion0p/tMZHLJJgbdohf7C0s/+hCC3TjwdPe5Sw9UFo7egMP8 kj7QWWL9f+BN87DQtc9MkkXQrWbq5A4xOTz8AOVn7VzAd2/AWQlXPpVlWC0QCWbzlE/rdrN1udpa L9c4uh75gNB4fxqGdKWRw3fiUFv/+f61PHVkGd9tle/3pgxKRFjrkJpMAhzDtXLLdqukOzaWQfeH 5BGYyxuyLO37CWQoz1TLT+14zpx+XUFTPINFPys6llARPRH3J5wyicy06ckWta5LnIYVsekqPL8t RcTY0t569U3mxw97FRsYvbzHfCqGRva1TM0Cy07ylITJysq4YpgAj4QNvsiq3I4af66F87Xf9cCc gfCUXh4SBTxSpuzrrTQS0M0Zg2FXZiNGkrZb6hGVXMgrfD7t4rBs5slKoSQJ8lDAzPPl8uRAGAlQ AUp86HvNxkvze/sVIQwo6YsnuUjI3wDDF7ZN1As9RVIXeuCyjlPxAh6Dn692bLJCAmg1xRAeitBE rA7htkSqDUFWoh9lk4ujuxjXtpd20+P4HSKfc87uACmTS5Val4H2rWQUSuFRiefFyhJf7KDOJYC1 wRTBiaSTCla2Vx3BbBe30guLX7SMyNsIx5/7AlsJOebTTGeH7mWkbiablTew4jJKg3vfVSAyMRfa ++S6JrsJSUIekNLrN//5JmU/+GPOCQ9zPBH8ONm9msrtDXwnmqz5nyxXEWvTTTrIU1HrOkQaSCWz jyjY4ngtX5p+sa/oUf3yT7EVB2XTUBuIS+xZ/u+VjST+IlqwgY460eC/gfDiADU3zyj1gympETp8 ukwjqQ8DAJasNvWGg7yizlUB1MUspuya7kJ5k6S+de8aWwni9W4SC1fYw9JQpBpBmFOrL+slrwIp oTkxo52G2z1NJPTZwesDQaN5OOMvANG9ua5LB7FUQQUexqJrFWiKlLPwZJ3+aRQaQw6GKO3LJNea PGTZgrz2wawEGkKYtC7egMkMQA7OtGZXi1TcoJ2NH/E/epassiu6Hjfw/kIG7WV2oiLgcS6YEw0n 8ayjcB+PcHsOfMjvV0har1jSmHNhYnioR+uE+FcJqTLG8XFRWQ5NZB+/8ygn74lXEShIoxXtQCN+ 3g4Id+8X9VwygRbFn5j9ljPHr5rzxnM/Utuk0yroYvVgcUfWu9PaDf0U9JOSaNmNP5kRuWtPnonq THWyW7Av/61miWqt+pFaYs53pPgDcgz0sR9uee576Xco0KkMEvu5vfCUn8prIyRBDkjF4/h5b/Tp GEP05SlyKwVx6DtMwsm51BzF9fTELkKyZBBMc8SGMg/JlD64kYy4BF1aQYBxHaapB8E+as8WzV7e SolfVnM+BWWUh6D6TO8mQlqgluxGhJU9NR1cFR59i4Ckk1JDTMqNO9ni9q5N6NNtqnnenMBCV/DA p9llUN3JApGiV0i+HfWWHazV+IsrdsONFA9qXfFamjhUINkDgxWjem1yPtkJAoqHxCvh+oyPzxJm qiH7fZ6qGnN6QvRhHzD0+uTfTMAOMDtSVzpjK/djO1M6/54Uew+iKyMr7/2J4OjRxXrXlYjnc8UZ vWUZb3dC7YBEZeHnMtAfLmPmTGiZzogCgFADTUcIY343H+Ybkn3ctnpqWjR6c9IpbgG1fgtw3oBa MtKO5n4eAZqRqogfuNdNJsCE3oHVkeJhmLi94CLiKH+p/oUBUkKrEXOGjYzr1WCGcpN8EWt7Xr8K Dxz17ftsSEAcD9YYuYiyE6txcWlk6SztSGWMXgwGdc33En6OyAEQ2vuacKqoH0xGIhikxYIsms9w g7TMIeX7hjdg7LWoFzIIuGS1iBSolvScbqo3dXdJ0dbZrnEW9muKAO9N2qpOuR8XfIpcKHKIpOQk he6yVmm/i+hE/ty4bsV+SY9vHHEzY+Z6TIRK+EIA134yJdi2f5Npas2hufn2j5XjZ0tRUtPe3FEX k/XA1TgpATKslYVKXZxKmwJJd9jBViw4FE+AKnxJpCIrRQdVqjatoZyz8iewJ5+vh2NDb62JXNHu Axb0ghLHtep4FnNEmjgBuumYkHP3elCDkP0SXbT8Nj6lPmImIssKxqv94rLMS2D7xid3wrVEliAJ q/hZofgjkNLsQQNNsLNTEqa+gYbEE/0Yvp2VRe4lpBtRVKJdvCdIQyaefmPF3GLNzWLFBzy+YziF S3/xm8X05HW5B+3wUxTKZTZqowSCQ7OFDVGY2SaPrpQKmMZXcUQdU75Lue0llh+3WfgN8cZPIsgz fHOOw2tjpyc83fHo8QfHXzOkJy9d49/UsP+O5VET6gWO6n3oZoN4/RYXLrvUUMfyR0DL3iAZlsie gUhQ52aEHV31ZbQ4UExD2zXOGOZ1II3F/UQS48XQ+QGYemiEPFUTa6T8J8B34bt1UxxtxBMa28p+ jxv4RdkqD+lw7TQamofYUhahP3MJjwUNBZQn95mzQ+xrSW5Jf+dMUl1jUPDTeqCyB/YbayxQSwfl 6qTbIy1r+RHobXQIsrfa6TRITzkev6Te2jzlsr/k2iVEb+zjS+imZI6KyGjMHwEYmppxr2zGN1FH kSpnkW0I8zZwAe4clVCgOtnApaVCqWEWIsnRlZGMEokS3ZcIFItUfoUFxrIir1fgYTzyrhatKASu 7lEkPul3YFCL5hcf08Vwbqo5mF8+D/GYssxxADPE9PUuF5iPW8kMLketEtuDHXilgteQ7veBVDC1 8r7orqZeVWlQ7h0nOHY9zgtuPktJes4Ta5qEGlOtuDq69gK4+P1T0SeMm/ZjVQRNg8odDUm/5Etk ejxcuxtelB4qsqJ9ffCiR0HXXxkmCloFaey4pPf84Q1gd/bg+eOhyb6iRVnTWYvScDDuZgJOgiAy 5fqOCwC9wpYy6kpVD+tRqO2WwJsvDHFKgWhFY26LYmg6kCCkSJWONGtCgVCsInqkqKFUAY53UITH YQbirK0ihPn97yEqeO0d3inpXtv9GrfZiX1ITdKMTIGfOit5JkJM4OqPm455FtmvsGcBzOVHcP5D bx0hzCHpBXGg6+pZiaU7QXv4HlgMLTvSDTBlv7D5KuuAnNQ3ujGn+ZQoNWyJKIiwaQVCvUnNHGYB 1G9mrnXjTzmrAfD93Z8gbR4XuoQ8H9JKRse8Qx2eaVN8/ts/qHDRxye92IJNCEe8fdJyDJHwcKvI yvjsGydm+BFxqHCMwFZTHal7CQzpJGnPb57v8isLGQ5jPeBKaWI35nP/ux/PgC9Awt3HWhPVxbTG BuM/V48y4fVHiAGbG9XWblD3oXLE2xH7M/JNZs/WYTWi7weS7FlrSnIyCbxPloTDLA8osWzUxyhQ IV9miEkEKc4p9IbrwkF2Df4a58yY5AsXjrHFRqNf2dLDa3aYlgGUa5M5okwWzWgjj30c08dvk8rR w9Pp3AEQTc2Bg/3pBTWr2OzGyWxsywsvu70sjFtcUE+psqhi4OOcPLzgTZdKpONdRFObxXzJ4p8W sJzUb2H4XPMvhgscCZmARPF63Nw2jAQoNYzdPD8pGtMtcnhbY6ThEDnGKVBd8bGxYCglwYBmyRQz 7WmEkBtYn3QtyFyrOWuY8VJ0f59iQvKpLhZi232hilRCSW85Q9pMO+yTE+dxe640ts/xGz+/gtPw gJ7LXaaHVFi7TI0r4eyOkGPIuaGZ/BrG4U5wY7DfQbw3DvOeEq13BvRYH49NUPqKzWsAKvy1klbY WgFSUe7+YW6f9Xi8scBYlKvgzxTwGPMZgIM786sTtOuT+IONTgFqvPjgg6oVhHraNN9uOqrz0kjh OBCMSbpUA6TVftw5sYUk3DCIJu7OoPbHU5dhBnL2FWPOxKuVTeHOVJ/a/DkkajFsIYGxw6gSB/pd eFV4sIqQTDhJxVaPJ0ojc0cTti1HZSwnq7Svgh9kMAixk+Cq1xeKa3HxO+/QPON0ldlVSIBnlEk1 UBtkJJyM6tq+ofPEDdlG1jyLyyaYg7KMvqYuabz+xsk3c9gVcx83VjH1ZpxZNorclx4rnMOE61HK XlEepir6rao6k1lNEejHH2jmgXkSET1+NbFEZHASSygOIbjc+302mjyG59DQEbdx2XB1g8ZbW5mN wtYmbumng9hEDzc6SA7O1KE/jC86vsv3AS4YN85G4qQMeC06XMnCzbO9kdp8JztLwGcCDaxOsEzN sEstQ0BBaYo4lkJNCw5vOKx8wT8DP8Fyy4HUw3Mqo1dXDBtx+SVMc26QGVxMCVJlJuzVB61I8V0O uYkDIY/NiLD+DrMLiyieNABz2FwjsX9rEGUpffu9m56+wooglxl1z0dQNaOq6PolcdDwMRu/hwe/ s5+Nag5OjqGcWBmfFedyDhGpDFTK3cz3QE4ZQ32z+0Kg9BMfpCmZy6XtIcfqD0rBQ/YmmMGqnsRM oJ6C7rBc0bq7F9qNY/vCqGUk6ncE5o3405A9/EmhcEE+GexJUjEHbo1KrOYGANn828srv2ZBMnzW 1SFNb5ZoAFsnAkksPyCjnwImXjjTra/6YbORY48M+6WSUkCVkqBwcTjA9eYVMdw+yfKUubnIroy5 H1Kp3FSaPB1IFGhPuilUsVIrG57UbzzJS4m2YaVsDk6xpt41l629qGkT/3yoHwjd+SdNoVNqw1sH 6OSGmwmbvpnXFZbmJrVYlKTq8Ta0LarV5HpEFOxt/euouh7Sbg0s+eMKuLRzjcTVlZlLX56yddWs Nd2bmZt2YkNwJQaKlxJskMgIETWnrpbSCv+r3zpf31kQj+aNXoVbNIKOcov7QGNfm+rpfQk3LOYd RWB/mn9JSoHVOGzDTUMnXBgtra7VxIIxPkddsVlIcESaLgf5wu/cKPPq8GsQJ22/IQ95kw3WUFEX O2UoBTjkNZO4b4MWInrVOCuiAiAuoAgzFXWC9PIkaVD+pabjga2OaRh5i4Oc5ML3xwr7sgk/vE3A SNkjwUFwXZldmCLCW9jiqviq+ULJ+nkQBLhYftlvF6WZ2AkNV1EX9jSqFtmLOifHsWxg5z01guOt EGEPY5b0Xd6dbME9gnpsZVaQy/MkmgFTiNEa2WbNU9vasZFN4RwcQb3FfbzktzTJFdFS6YKZqSgv uyGl6AdC7STOV/tQkVPlJsKVssB8pHimLCY76SGeQ98L7LcCEHJF3b/si7CgCYgHF9szhVa5JZRZ PNa4XHjwjzz6DRg8dK1B9UCpz9EfSwqeAxXKPiVZUtYzTYb1Bg3/YMl863Cvi/Im1CCl8QP8D4kw 0hyszlQ9GwUiqs1KJVxPo9HF9bIXa5Df65kEEMsucHHQ1EqDOA6YFXvMHjAa0Itw3ZdZQunw3IGf FMPqjyQUYc9zBxUxOFO28iWd+8CC4Xq+zT20Jqaf9VQokkni0dnnXiqR0w80QVnESRPZucENbDQ8 7HSiBKlMVx6jG5570dH3oR0jw03wq04kxBSE4a0Pw12TCtP/GBXEZc/CX0JJG/+bcwprBxxfC4Z6 DAR8i70FIk0U0ZuGjXZavwQTWfeX00uO5Q2jIm6nVOKoiRLE/+SJ+Wjb75xjUU/L+CxsJPT3TxUg eAzQ0I4OxBC4oJr+AdFWB9WSFgTydsg5dj7Fq8MbNovAgn5vCxWAkaSyt+7U6/GVLX75OzOlpWbK DrkVYRth4a4rO86lT8woDRzsTnBPes9BriX+r/uscVG38r6ogNcCr1OpwEWKLqk9Y34kPwsHlgz5 6DGk4wgLHpu0/EBYRrmzlpUw8zVGtmZiGvOEZTwnBV0NhemBPPnR8mEJTAxcsk0sBM784mEQefRH e86GCV7EDz31hKL653UoNSsiOwa5jXy1vZblajTdyfLuHCke2Z1zaSmh+V75K0LSYFjVCrIxpiZ8 w6mHSlH4qlX33vPTWucT5qCPf91trsSv88ByJO6Q1xCxqqmSjYYPchJZplzUBgwPObvEyB8bZPbt JV61L6DK26MgCP+AXFGsH0tdkT/Wod4EVT7NwfTI62qtNPFUHREKnTsl48/pABxCEEvFbvhz8phx etqRXv4w82ia8cChOYZhr0eplRgz7OgQ7jc/9eMrURz7/g3QgyzRp+jQO6LkB21babkKTN76QGw/ aJtJGXnzYzVYbyJ8ZXgUdbmpnra2f2Qdxs0YPcUwndDZIlwE5vZ15PzwZeYpF5d38dLznnkvF77V RtdmiUvnniEAZPV+01k5/pol2WMULhPsUaj/uhu0ABck2m6ULyhf3+IfKZcYH7EF3OB0Z6hA67Rs yX7GTFrx4TcDIH5a/fEWHr5BatdPGTVGfCwVC7OqqmuxqVnEzge1VoMOvWVDgB9MdTfMCaoXAgIH zCkmh/FO1x8auL6LAjdSRGw0EmqV4Ur2UzL8K10/p+UV3BwU/kbExl6pGHMyYYM90mtwTTt6MYYB 5gzG4+F0R66TlMTBXavGdQ/ltxl+DpODEZtKx97p+KHJXtu8mzQRSJCaxWgo4VsWvqxazzdXt+Hn ExyDvGiiy5k/aag9yEIQGFGWETTBn3rVPQ/s6dnEjfupq82hUHVBOZ+MR/LqiPy8O6KfYwf10S9X /p7il/5TvZJTAutK67Lz8PVALCc21sSBPU/haK+AFQDr1ECFHQ01udZl/uuZySTzKSMvFz8GR7DA 6tNJweSMUmkMevnSZ67GXbP8qtIUWZgewvvL1Es5Mj6D725AFudWHfCvTqO1g4mzFXJ9rRObXYvX HceW845jf19R8bBv6KZjzaP87K/ksfehtD/8Qc2J0uSEw719vJhm86XUHPM53i3t2VWiE7S631Rq eeVNdx5RCmH8/9h8TU+6csvBJJy1wJLUxDtH/jPgXfSfCR9cou7mYPKuFNJXByghJ0ULphnGuEue RciFaSAHvHlnijD5xev6s5+KJ1l7PR6Yu0Gr+ikIMBpZ+8CfeVWsikA7A2LHT7gAvg5doY/COt8B oqDqi6PTq2YnM0/N5eziOILf5Q5F37vOy7kBPXmRy7f2D4gAb35jVSXr0t7I/KoA/Xue9/N0TQef rUh0VfieRGv7C052IxLvVKuDIwxMBJhH61jVBLcEr+5jajMVhnrgoyn2bOkJvZuBj0hSK8r5fd4C rnsu6nSOMnuXkqHoiM5Y+h8xXBd+/O+ZUcrYAJ5VXiw9VVN3m+oHKCLg3RXVOiYmHcTTb/xyLlNg k1Q0QdNiC4jz/2g/fm1lTC2l9SKU5+qBx1IEHSTHX2w62/QWhS5zbfmggDUKMocHMAdXnscxY6/Y zHVroQppSQh+k/yk0GsB7ZTMyqqoWwUSsvob8hmU5/8KSOR8ngpdv947ZVm0gBsllNUcQNmJ6Bw7 R0US1F9yoHssOxMobnRvA3zWVZHrxnHxE/D/qxEfTr4pufGm3HXhQaWrF8oBZrbC9UdKkP9ecg6H fMeicCMF/ExlStRKx4DT3mvsI4oYmEgJvOEeyy71DUTmFHw45l5vuE7QGrpn0R0LvF52iIgaJmRq lo36DIFdUnoPXI3hu1My13FxsPCqGrgoBUKQXRJQbm8WuHO6PuUl84arfaUag6lJFFwsnnjEHAil CtTG38ogdU1/KOuYLafw00NvXAbv3QlRMEnjMDmHrND52ESLLdGFfMJigv3HZOt41XaVsuIA8zMc kKia8Y6kOSz7lnEHwK0AfJPNBbHqYiYPEETrbNl1HpDpon+SkEIPRElClc98PIJtngfuBA9wyp2s aJ7UZou0a7eceZU+ohczjtxsBeN4DEjeKlEcU0Rliqcwr2fFknTclxBhg7i1tEfmkZmALpYxxJeP 42ieUKYMqvL9D6P9cHLh5K41sLdoJ2IyuFvV6B/mXyA/Jx4JjoLB3mpr94fXn8f76K1Gv0nTvDqz eqFyTJmmt059cc30a9CHC41YZRnB3zHQ+SkMCYAb7ZaP/N7z+QThqR0qVwMaerENQvo28vGjkIaS oKT8zdoohZCoHIumAHPdhVc8nC7Nr/ccHcwE4E+cgtplF7z7MBW+zBEMSAStniuw15cFslaG+ARa bBnW5PIR7mAOA9SC++i0D5H+B8/SdXKEeoQaABx+jamVk88SH3Du1NzLDt3nFu9IejlO9KIOP3m3 w2CUZwkSVooo3bGZeE++RyrOulGlA/yqpKTJDXXsRYaws6bq6/Ucc+r2/nhTwVlUgLIkWe6VqsBX 52HuaT1NzEdhsIGzBJVYKVK2TR5+IDopqAZdR3W8CwzDt5/YwALjuxt47V5TOJHxggXC5OxgkIKP gEKUAE/KX66ZjF0u6t94rBLwzLd7mkt406iSyc8qb4C7UsbtZGHvtjmG9FWZh907VxaM2QRiLxNB FooI5LGSUWLiPNRrSQ6M/cBurWVOXmm2XaaGwfYBY8QkGGzdgKvJn2XM7Xf6NeSf0gk8s6WY3upH DjmnbnnIFopGu9q1GXHjG6jCkzH0scMwrSJS1QVp44KYcihfK+/Cz12AjrYGMgYXbBzaAFDzHNKZ U9UdkYsTifaeu6LiQnrijvhHFLcnw+3N7Aio2xMBFVT7Zcb9SE/DiK5aqWP0y0Nf2CfrkznPA6ip gDMAzG+8RvoDXMYtp+uftUKvOAeXh+UVVI4HrcqeOC4fZDIIbsLFNHH5AKJWFWt8Fun8vB4uWag/ vVvPRl6VNgcjyTo+U0A30QCb3+Gkrn/FmepeGgYpOOrXNrQ8MZzV2G7uX+2U5ZTiDMC3UeTPU77M zXziTlTNWuk0M93ZpLCnjECJ66zNrwnlE2H5afWBcMJON8iIHNr21fIks9NSs42MUyFH8soVasIN JfA9p0u2Vapo4hW4EETl26ogLsxSs+dnSXs7HagsGu29dbzZWW52OduPxe/U/CNEkfSErQoeZUOB lUASEuJeVKft2D1vMULu9mtI/p17rKgnMN00hmCDcVKmiQmLk1/e1TXccTx4Zt6SUzDOe/REn5Sa D2a0CkiJ1t7f4JHJ3FutjtlG+BtnpyVfrvwiQgWYRhw+rJ++AeCo5EQpFkm8ptxz7hTpJ9FkRi85 mUsmhUxCR3uq0dHL5b8qlGVB6Rv4+gyapQUfW1QFN5yhoty4X1F43NEHb6Ytt4fO6hdfX3lN9WXE mrZGaa3/wyfWvAtUbTcG2nstgyYhcHzN71V38hj1Q1JdUL3G40PMpb0ti2vOlwPKcc7+W0m1N726 hEHm21zTbSktM/oOiLuPoyXT2IyOQ73TyRam3rHv2QsTMD7qj/6I/kjyJlEuLci8NB13vH5vHCG3 84RDXGi+irYtaKt8hwI6bVgzK9XCniMuiOk7M9nbSBiDjda635rDmAaEEhX+q2kPWNDxoYChwPgR BdLzG94r7BDmJ08vg9uuOCYTrzfipge4307mRhP5bUqZIMl/ZRJX8vyX3jyyfNvoMkPGTVpBeNCD eZWr7rLMP49KNEUESg9gBp8Yz6eY91rOeoll8enNh8zT1stX8Be0SZP6fPVDEPRC4P8GYyDT8mqV m73m4cGv0NRecFgoid+eXnQV3HE1pNR0DgZdnPDXZ0KMFYZ5cFD3jgi9dbA8JGBmSQ2kO0ZQqIq6 EJIusrKITtXRmbR3663cLpq9OqRQYeX4eV22349JzYs+XU88NlYVFD0EV4n9upo6msXTiGPEvduU V+2LycHtiS17vYU1U/sv/L48pcAEJA8m0zFtIXWWASpSrFIdQIgSv1WXYn5ZcedAFNWJPoOoTR0U nP3tqTd8DyH3CB+NRl2DO4BPvdGf5lXfbZLM8WioklaPFUsz2ckf+9/DzT6KaSDCLd2eyngKePwS LehpQWt4RjdSoCAC8r/YiLR15DfwRWIT+q71LN1s9S6z1RDK6EfdXXamEQPiEllmFL/xOCTCqoQG iBnZFcT+YCGl1Rr2T2Gq3Pyy9GBTeqcTEjEwaF4QFL1MuYPECdHgID6d9GWubcqaAvoZMlH7ta6T YJfonOxB8alUajUeYb+i0gtvtrbI231XUxJqJOtMYptOUBL1YLCinarNiUa+DCyZx+e7lKHpVkne B9HECb19Z+VZrtg+ZTG6yFrUZSG1qPWOztYYQYmOIaCuDTX5dv3Uw3nUU2DKyhtxMd0M4Rpen9W3 4+K9jT12r3uRoT7ps08RcqRc0mKJSVJcJV0SeOjwENMitTj1MrpfXWMqFqa6GVZC8VJLBa5v5DXu yS978kTxVjzs2i3gzQzJ1LcHlqW6ckAOxepj+rP+gSZkd5gNBwRb+ttv2ES4xM+znBMHW2M9n1sO +aGeCpv3IrKtFNHDGr1Kt/EZdBi8A2XV3Co1vtkDhW/m+YIGFzqNp22CtXvbTnbPcPAZJGrLOFKH Hx39sAtrH8Rpx0MQwoi28mFYFM+6149Va2E46sQAlvg2rEYqc0KPWHRrgJfCQFAfn0+Uy+MPNiS8 g6Jd4VNgrahHJ1TxnvKNBXL0II5CQGzpblD2GwO4AdSytKbY+NIlEYpMZrci27TC+my/wYonMmdT p+4HvRIeTHQd75a+kpdbnUkeV7rCqjO2ZIhulM/Gakf56c1IHuaWwXD+xIjINa2pZQbvttO1qYK1 USLK9WCtmQAs27MnhDLr3yyNBmAhvQdjuWpSRzDqdjGIKlKk+vhAwyOOmYeJ/xkvltJ0Wvq0Wbvt 5+jFSSdeoOnO98IOAmPuWKTaHmn4gv8Eur4Wqgsc0ZjlU5O2w/JMsCMeupgtGpayIiO6N8Wa97ms VcifwdSFsxYOMbfGhyYNc71dVM7INSloTblkHds0uMFkkHOQzPWH6xpNvr87Uf6fqyoktTe8LbkC rdpum8rY1sx15m3Ws1uaqMpdY2RdESLeQScCc9WLvpjiNJoI28++c35b3Sev/Xbspm2V71vpejeI Orqp3jpT8ndgtwmDhphkmW1AgGJ5UZ8+M0ie/lG5sWoVDgJQ61xSDK3+ObrhoxAbVSdwQR91faQx ZaYkrffBPJb0pGc/ydcPQwNNIEFO7xooaeCi2AVn1C00BVOXS7kVSufi1n6Vajhrgfliptju3T9E uheJrKtrLrAOBIf3vAbcOJD2ByCbfVirdv5TI969xpZ+31nu+5zH+8lg8FYlOeoeTw2B5YvMuBJ1 pt137tUefqbT1aDXtY+qV21cjDEyJuso5lL6eOowrea0h7F9bYXc1e7vM2ENOY9RnXSIX12DXS7A 8SIs7CxkvdIG0k9Gv6smqk34fIsuTsiae6rLJsFQXdlqJNWek9LCB4jXgjMx+rLu3imBK217Wqy6 D2rw43vxZB+swE2+9hnTRU2ApTVn96NdLzxs920z3/RTdMX+yeQ6S9urD2lsoTwhwZ7/SHT70Qc1 DVDhTFK+M+52oki/9t1uKyIOmn/BkE3c4euOoSRTjVSQeR9HyqzYXtsCcR9RHu/qB0pI6TYQdsgg SOG7BUiv/i5YC+GAZfA9PWSRVhLrmbiq4AtlP1iopjDjLyxVDYeISkENikkQL/Ng7220AQkW+Tjf LR/Rs2MsU5dNqygX1LV/83MUQS7cUYT4PNcnAaDp5C/IiDa2w+wbAxBNu4DGpvVXZ5tXC0JqjOna VofvJgcBXJhv4y0SZB3//bf/TH1gfzZ6IRe1Eb+JBr6MP8+MLLbQv9UWHMFmtdZvLABVgzlj+7sB Y2o6p75sXaSxvEtuaS3edEDL4/Q7Mi95AGJu+2iXFuwpH2SPQhNWjPEg21hXjCJtOftX0ZEDSxEl R+pSyKUHVkNf/dFjBQK/K4DizIO51Nppw4dTC/Mndj36pRZx+xEtLsAx9clpHl4POZccq0kAgbRe 83r7WHQdoHPerfZDOjFdQyo7RzWFlmAaT7HuWBFobJ96tWXgCiHonzu36eHpUzcYV0Pbh8afITBy sBO6rIqGXSkBpjLuQxtKI+Edtw2LJhSPHt7Jh9Ecn4oHNoShgPXNHGHEJQn+z5jHu9hWi93VxM0T 4/PiUAUyGrUgqKGKZdGvfj1HiuAaNRLi+T4Ub36bz2+MLs9PYZRo1au+UYAjIsZwAF4fZhmvMORu z9pIgfxaMxiWnLjj8/8Bpt9FlrTSlhThOpbQv5y5Y9RK2bPQGnsfVT9pYqYFMpcCyF6I2qomEx6v LiguClC670cHjCuWGAGrFZgEa4ixnrmBmXj2e2pjHxqgKJC0UvcrSBNiMY3jpd0m3IwoJTsWosNT oRaerEdwgxyjobmM0T0aKZIBGXbnVHrein2Idr8H9IEoinaAx0NbkNB8eqMkw1xkP17B4jmjML7L AoF1v1eG8aE9bNsWwZhZ3YBLEYEXAvcRxBm+IBxmp52ppgtdsKVCqhRIhXfV2bZFetZIcJAbAmnl EQfe+05Joh/JhsiQYrxJFKLk8ok2tTSaePKkcWW+j4ZPCiS4KyxQzzS93C4KitYfK87UY8lE+/P9 CHr/IPWIeXIXYqObQNV9gVDFGTTPAO5aJn7J04fV6CAseDtcvYrbiu28LozRWw0mg4tlnmkUr4og OPpnee5Y5Hq47Q8q4a+pYeWoEl1LRDX9MXZGmiehE5G7UF/kwcQjm35j7joXpSljyF/hBN27Vkci 2iSpFxpqmKzHotnp3e/gcnUjpkPaB759dzPLb+gLyKXAjYQjsPw1k5+xI8UN7epX6pTSCRjqHfyY rWrEye+QDULtVRuIZC11jf3K5lEkMgiGwT11vOMvSfgaH+V9q7YN+rVPs2IKBNbaohTFij8Oy0dm CP4FR0UYdylY1TAJZ0Qh1f68+M/u7idVGjtodO4GL23ncpU2LJTjje2l5Xmra/A29PiDAhXf0Q9L LJAD1YlL0bes8f5DqlnYAZrhQUbaAlSH9If3ZUwU4xmHAaYFmtlmNldooDgVSWrq1dqOUw+N8tK0 TTui9MKwZE0ZFG3/+8W0WtigEs38lvLpcepmSDQCHH42tvugV0dISmy+/vhoFN3iNETeVcHJojFJ hCtl5cnu9NYT0v/rq+7QMA2FtMByJemuNAAPdHqqfAGodSitGYsaIKL9WHEbs1Ax20EfSnRYENea KYDO9m8KOse36MSsK2ejmSoLXPuVUYPzAGkuDXatNiVdAoxWJpTjWUxYHxEvetWFJaS/bFWeAvRL ZO0Roq52vAwxWpkVMNy4oUkKsNSFI+O4if87Z7whTn71OGamxWYnvr3Q5jAceVOIiSxUvk4WMHHw EIntFi0QULAIeZuuq8K+JKUzEeEmcTMDOpj5jzNSM5ogqSG11J6E071R0WddtxfCyfDDRdYxC3lK ZRV2f8nAIVquzc7FVQmbp63N1PHe7RypfzrijkHxQHpgUdp2Yhr6riTH7PErnRLJhnDlinDPj1TC sR73BSnBwU+dm92P1jOYH36G2Z9LwAtlY2GpiBQois5wVLfCgFRPZemEK/DyV5p4jLywzRtrqj82 UNsAy2XiVG9pQNEf+3RxMdo4tfeWZjmkpPrTMU3JE4uss0T0L1URlPiVQsKiwooI0XdBkZjvB3Ln zmmeGkToYmiR+Bb5X3AmOeupbw0Z2sMe7d1Fsx02eNk1GKPla78217mMgBwSHxvivvDzHBKWBwuD v2egIj5Sqonsii8UlyqRYI45Km8UcE07uCE92edKRsUTtmX1Ni+3M/qnYwfUIiPrrZyIz9PXKnmh I0XRZp/MOO+Wzx5SyuCs/4SNkedKGV2HKV+lsygq1fCt+I2+dOVAmPOmxpSxEV6fU/+2AioNE8RS Ae5B44uwjz0QuO63bvrmkc58mVdhZAQw5279ayFKphIXGtFs30zqCfkRmrrsmNb648vk2EAMRXN2 49KUmUtysouxPACMbwJNRumESsQIzS1XjiugVgFPp/C6ThJHrz6GviSHE/7o44pxctR4udaIBOyo rulsGbyxyKN9iqbfRR9+3O6uU5hKEkkP+qLHXztQ5X/8S3Zmf2Lb6uNsJHNfzioZ8Re8aznqdmSC /QP0ID4Ienky7IZDQA6rfXR038pHhB70a70g45qwwo7AyTf88i22VpfgJ+J8FkKAn3hUMYeJPggZ Plelw/fDFY+WJdg7EqehFhYK2Oj2ohPlQferZZIp3EVPTcUI5NPO1TjklA2LMhxqgOHYpnLwPLUx H3K+EwW6lXBMfii8/6X5JdXD1VAoE0OFCxa7kR+TJSs8iAgN1goRHLTBFr8n0ziXNj511adbnnJk gFP+JOIuohw4TR4hLDDVXWbJOw33a7RaaBKA8AOtWYCI8JfYynTEA/EKJHzbCDeQO0p0SwnEeyxB CWTtDP8/wkquWhBEm0Pbvb3rCLy5D9dORQQlqvqnXmEuypkWayWDRgGAazT6kmu6Hp37KTVj5nou rRUBAebzoLKbps8OOS6494dnZgKn7JcdTFeIfx8dsVbdZEc+gPt0OLQPiXMr1RBFPTebJ1UCBo5J zFyZkOiLULD9mI9jlMlNvM6DzXwzYV0Iiv197gF04mLq3BJxCRZzdkJpWk02LpqAk7Iswb3lXfH8 KvPDIN5PAP9QN3muvye8NBNud4yZ5eQF5KE9hXfs/QjB9iQb/VGMqp1S2SG8PCG3kCT5p6Qc+OSK KKtlPwbytW67iW3eO+i5eLzM81KaeXvI+j3wSVizcqAn102MHqloNvE/NaESIjb5jt6JEGKDPiU/ SlE7toe1Fp0Axra0TGcW9HufP8/mNe9ji7B2ByHORWu0N45juScwZKlSgdMr19c/PlhMcY4qUcA3 viFtd8r9n/tPkw8QgriS/wNxomPh0lxdRAhrTKJYMj3wDe/cqJ0G3/RFAIW6ABtxLjZd3cFWB7zw J/zIsw8VVwRgxkBY4Ulyr1e7Zm+qsgUvaSRZhCMjELcEbIZZbPzvAqX5pKIgMmtz1+XqQ0cw7fwA bGu2H0I1NIG1kd+b7ETcOwD1t7RqLo5TaHuAKhUgw5IXaKnXNAV+IsoCSLMGgBrWbbVNM2mFjF6n wOWc4ZKnlX1Q8stHHcwtQ7TypROOmDAjooz59V1AKZusvRSYSMP+jd+ubop7JlfmO1xSgz3vm3Ar 4UC5X+i45UZx4BnWx7RTMtWWF3IR+UfM5aMDIbiSCxuNiLD2w+QNYYYmuqUtr2Oqgh6JI18EFQMz MEb1sX/bErmrssmVj6KbsLARxXZneIFY0T4R6LlHMyq9ERZ8WS4W+zbK3YvH7d/FggeaZUELBA0j xDukYj2waPgC9cBW4nwPaI9x/PyKoXxjJXY1S7/ATyi9McwRsrYGRK64YR2UtnB83BrtPMqhWG5M yFCOsk1FjIt53jhR9nbFSwv2KxySXQFvKzilMA6cYXWvY71OE8/9v0owbqw/m0VN65cNcRrSQBcz 6WBVkZzeCE7GfqoqsbKfdb+hKiT56yCgN0PoR55kkFD/5tDbzAeeQXPx0/S9R/KKFQJZlCZDYwOu DMT2LyLfpgZ0eJds2SchfK4ikj9znB+qRZLujsSBifTrk8e5B3YprajkF1yv59lf7n3rkKOTRudL fjbN5m9geUc3ldibPUvLDXM8+4C9hE7+PKah4/UIAH+x4ds2Sj5uGRSiXltA1hPr9BNAuAS/NSF1 nrGW+eRA37YLt5Q1hp0Dl6bKzM8YypYye3F7IRFBXR655g+Nv0EJxgOcW/8jEalKIpGXjAAIBWVP DO4Yi4LZFWLQo0W1gfmDzcRhD3x3C//3kijJdqf8FJ8Kd9bmW7ZoFkTajlnU2kli496glNB7CeQA O5MgAmMIRUTIiNN8qFxElbwfrZufobxgBPpkqNWJkRir+kVYThC2skVEeB03mMLlnqjsYP+rKnbq aaEDboG1WFRahB9hQNJ9LDRrCXG5fi4PAC76VpL7UKnRMJSd2xt2t6tQHeIi2pqs85Z0HbIATOxb jPxYXsWoomnxIWUJBO7vCXXvV7+oJQkCAOh6N9NilozJ5TNo9bBXVlDn2lQSlZ3QqZ/cZWqeUxC2 rB+6DwtYLsqzFaGshSzUTGnR3hPxANfd9ae/KSnUrXVBgrOVNsIlOjFPSPuv96T7vOMYT9mJS6o5 rH67aB/7TPsnw1b6qc+Gib8E9De6Gaq1u5EOgazc93xViUQO2rlhIcO/3vOmDmKvWZxZIo05fEAN ZpDNTS6y5hL8KmPdPEri6zg7hLZycpMEbQcHcL6Iusr8w+kM4kVOvW2nq91OV7B86fvoeo9oQbUk +ePyHJ1YnsCiyXcT1W00L3UeiHyjqfHM0CM0m5y2MJ1QJvnQPxeB2hTEhM2yKUjLnkfZfl7CnlU8 G4Dt064Jzjv0thvgrga4nDalHFH3WPsF7AcxzZPWu8h89do6UXXxbgZoIDH2L7oFpbH8YCAOwgZG BT/JJQkLt3uXczWqj/8qnr8exNLkKLQb5xf5H8Fieqtv3SMVH/PGYFSo9ToRf96TrmER8rZaPN+g gKPFCLicP4JzhXLLqUJoQL/A5OPAzhLtHc8T+MQWJZ1KApqfGUugRvsIVeweFLUqgTeQ40IrcxmW iJ4J3cLMJricAvUWiRgaoESbcCQ/yzfXIODxpbZP5BeG1c4ZOR8Gx6QwHJ7XoobGdDykk8aZ5C4h G/pweo571kf84sTxxMRJKTP6s9pwcYt4qGEyQqLR4i80NJAzxGq9W7fRPi1PTN4KyAhBi0SGaZL/ OOAYCurYeXUHDnJK8n/rQ9nYfiDvAQEZ2ZqBArqOEa79Rr0GitwXdWMBHLezGJ4FRB88xtwbPaCJ FRdDMilgDUXlUB0yj55zQgfKHJTVVEY08kvy0Q4gTlGsUsc72dSH9pHaTxkKsQpdHncLNgoLSx+n cmVQje5nTnhjB+bIF6W2PcNKUN7+wJMoaqsK+d5eDe5zFemGn7jJoCSOtY3gO6Z47x//bkw3tKK1 Or8Iff5aDTPM095H31aKw2JNeDwvNWv9W3xBXVygi8IM/jOiPEg6a3nL6jtSyEs1HRxlK7ocfZTv nRjIAwY86rNAt2NhdZtT5hABV0cAbGdaqerR7KT7ZQwT/gtguUUJNgAhO56AumERNKoi/Pxe9cNr vRLleU/i1wc0pvB3WmiIxVXvrxhriSTLdKcQYf4VcJihMeOGxtDqE1NvORTug/tc8wVL9L7RQXDO XX4dk8JjGy+TYjd4IIRS8pTFWwlaBM+ZkQy/hzKtcwfdLaJZg2R29C9SICULtpA1b5AIvse3kEPI h1wQQV9YNldTNmCS4oZpXb/L/XAHpSxRJJ+T4XG0DaPIhc0m8mzFhie6La9uK1ato1FvXYgh47A+ QZzI3rEvQLhLt8FJ0QeRP3BOuMGMgrbk8x+hNngKpSVclRYYQNUTXPxJd9tAzI5eD8IVNgL1k7jZ lPehxlX4fR06yuioWNrUr6WcrJ1IV2VaF6fBcGMY7lZLmhAo+Ohas3tSqcFGXetTYba2HjPdkPx6 nyAMe1ZoAtKYYJJW3NWb3nFBxX0uxtPrVyX2n1QhgLxOMsHErP675B8ezzjtVbtaAOirf05X/OpR MRFwDiywg0ixWaZn0zmqsXstbr/QjcnOeMVnhd0N3s/WGwzCBKR/mjy3RwN9e2qbMfgYPYmW7Epi N8T5BGpjxzi/Vl4PWSruPqckdaMaY5Y7cv6sRB1T5yaWls2uMYDPVDugVvpe7d20LL7pan1vvnfN fGOHl9YRWTkpMD+mzeDiZ9EhXUDgONVzQ6B1kOZpg10I6w84hGR+X165EsMM0mbLqpEAhVYpBa0w GzTcrrQpxfiAkrYLZsleJgo4kPX/qpOQETRu9a1ubzh1Su6HZvGL1CO01nTlBMmTMiTDY2ieXOMD Cm5QRhPe8KjA9d/jkIGECioUK/dVDIbKaek2iwr81qXHppZdvG4Z9unBQjHC/LdRp9TuQYoQj+sb h9hsjgY7rw89USVamuRkgf4w/aFq9PgeLibqeh6m+NMY1AO8EPqLLXNA2GYuAZ0bgoSWvqcAzon7 q/oADjN8PodLfCtk7Qcz0TPxeEG1OmakiWCa7aIJ8R9ITfcdKaDsY2dVsczLs8ce3GSHsK9/zCAa gA4KfvpaBuf1TZyDiiQiXWEK7KTRTf+93Aa/3JiF9TXUhwJc75hyz6TFAn73DlwEjv/y07I0nBrK kLOGY9z1Cm7TR0956ek4gK7/dubq+rD28mGHHklKjeUuvrap8nj18rwMJDtAFnlZ8/F8vZp7SxPe TKy4AJfuoWZydSyavWF6M72jwPA8gWqyoayUQeHsOCWIk83TvJRQ2Uv+NoCpmb8KeSd8wysjLS0S W5mzD9C0SmzDuTsmAMFA/GAUYJf7ra9H0VosZ2JLmjghtb2TLgPGspQW1WhfoAMr2WLV9i3ABrYC hEK6dAVxUgROxQjLNiWjGMdWvq4bfk9IaXfYBmXRs0cWzVB4oZS4rleat3aXYPfHn9VwXirRV56d qitq8ufcjoPwlux1MeVvld09EuZyvCMoQF0DBbPIY0AIgAqK2RBAhjbRmjwLitTSVPGuoGORzxPy SE+j/R0aPEGp6Rh+pqmXZ00zBEfc9iSYO9l83/2VGDoYnqTiZ5c4H/1cT1cya8dWVJHAwDb20Zku egYqUsqiCMziehY8V4rkRLDhqd3aDPiycpetftNatLWvXkxC6m89F8/DOwIkhBM8ykCU7pQrsfL2 zi7NyH+ApqSP+AAgcc6661cO7Ph2j8Hx73xLCpDY4Vb0F8CKsPppqGdLIp13QXoUEvvAkVL7vKPx T4IIFLp+PLpvLYpwgnSFDf7Yupukng8UTcCLs/CUThPl9cClXT937iVw8icXS4rHFsRksPmPNMQS X7LDoFoVkAxPw+2LhU4Wl6qzwSWMQtwYfMCnAud1HBkxP1neDJ20L5Nb/FzrISjB14IOna2N/rwI 47J2w9uUXxV7Swf9E8ybwLJEAxNaXqD4GAT0vrwun8HNPs7nP8kge6Z0uYJQy9uomLEnoC1ySKF+ E+rES6oB0cjS2ywnrXKZqn1bWjm5G3WoGDI/nr5BjGRjZCLOT/iVf/97XFk3ffEz/rEBDXnN5PKs /ZdVzlkYEUDfnUp4a5Jw5XvLATBOVmSJQYDdfW5urPZ/JJ4pG9s4lEgbNUfAeb27uwFingZ3Ge+3 or/bXZr8LSE7O9XLYEWoGeTz9L2iXZzKb48aGv1ZuG497RmJXYgy3yS0c3ptzgHp1U8ZLo668s0Z EpugBglteex4PozAUkNGQAzrGwvQ6MJqmKvjY984hNe+xiiAia6cJgZzAwqUNIIfB61JHapm1fay nzzipAHpHEhwi92e8+5PL255esr6XOs7VYk3K76+jKr2Uryh9gnl/HxzpOsK1m4DmDw4yunwbD45 tfIMstrve4Ki/MJcrzA3me39s4fp/hIpCzbtQpTKqPLy2YPnlhQxS+XjwEonssV49D7XxfKA40CF IcRu1heOvJKu/N4IAy5kk2tL1iziMrq55icBaYe1HZ3FxtoKTz/ScZe9+p/l2Ch3B+RqgRldXgBZ 7SDKaJxpgE8HLc1AvJdZBIY+cS81cNQgkSMzjq15yEfr6LIVvOEV54kt366zlbY5PG+7AyJQb26O ql5yJRXTmy7aS5VUmI4cmIrMyWvPepn1SuiA29xMHBKEzIWrLPPn9X5gHsSpi2KcXt48IHzUT3mW R/bIlnjpVzXyn7rojrkAfz5+BpTJdK1QmG3lRwhpht6hy6VowPIIf1duaNYc8mAlo/RXSOSucwM6 T6ry2CIiRH1GGMYu/gtcTyN5p9ivMZaLPW7K9vwsYDSyiyp7oLuWuWQGfwY7ZCSmPKmZ66n3yxf1 ZpVgu+ZF3OvX6yS/a8uVApKd1yMNb+IcJ6fAxL0RzDIzOrv2axSyfZL6YP7JDNRhzMGK74KWEUYB AtD+G17bDp6g57x0vo/zPMvAdCHzW+N7jP8ZuWefx5ULSr66WrLQZOq6eqve7It9edbPmrZi34cx vwzLWaB5/aVuVmlGQV3F4yRdkLIZsLbEXGFEO2NjHhxpPU9aSxeVYH/u1o4skBaOwD5dZ8XkTmSA Qv0S6jl43lTm7DYDzqo1PKUvrMui0Q0RgoDy4F7FzS748BtGvELvJSMl+F3IWDmERl97ybgM0aoh e01qONZ5S9UqKeQrVs4oaLK40RDHOmweDSPqzJ0yjVMpic5medQDEOd3tuNrlfW1pi4AhonCX2MQ rd7uRbThakzCwHuc2jqXAAA9/JNNdn8d2PoD2810Mov0o2GUz3hUpysoa/QyYPpjwT4QF6oQ0KPX komnERRwG+C4D8tifXEZM30tfaYoekN+eifK+3w7nNGiYjHjzds28PiF/ntOpYW+iKssKkTaTIsy TMsW4mSak+Y4PhgeqEKrB+MphIXuat9w5SmwW7A2Z9jC/hW8J8QOf+OY4rHB7X/6ui9iJPATgo6j V+sZ4T+oX88BJARVpnKhBIC0bUrKyErmU3Xc9Li7XK7y8U5DTPJWdAtdrYhJAIKrQQlTN2VQHbz5 8B0hIAP3pxLx1RIVk1q1J6EURHcJafQ07ywMOR1/D7J2Nc+8mCEW3mYADDH5YYnE4crOZkpHSmNv V0U0MQuI+0Fke1vRLhMC5aXgQYyl4VEgJnmTntTtwGCcIba0RdaBrI5qHwL5fKhgbwMoGYfwXcec z43ppTLq0APkquPll6iSu2t7ZSX+ivPwLYIUI9h45u4dOOREeWsosOwEnOlD66/Bm/4UlBgd0KX8 tGOLnYRS12Ced90ghZU0u0bXGV4AtuLF5Rqt7yPpNESagkx0MrFNdvbXLvPh2jJKHA8EKkTp3WC8 BM1ii/d+27x40oUa97viHV8tP1cefFWt7JEytlIt+nONdqgBVXIAmJlrZq5UMd0MeONqJioRAiEa RXSG1Uyc6NMOM94PRSBegIGF4DiJLUeAJBGmSDEzKXkNmtOfsopbUGi20FzzfDnbdanDzxjzs6Ox oyBDGcORVrdm8kve2/IX5o8QvippfFdh2qOJbBt/tttKlKSoWUq0ZsOHayX2z1Ob1d2ZESXOw3/g LDs79rumG9daHyNA2IyIdss0TxQqUfDD1ofCboEt4Gzs6LP2RS3qT2VGaCWYJAJeO84eQWX+c0/8 ZaYo+wsFU7lkre2zww1f1uGPbjtLuIpXW/YTpmESQPbhL4KBf1LRgwAUcwhzCDcYRk+WQe5GRlmL Mn9ImeWRuiWxV3LM3odvFcQ0Q32sU6lTSdlgQtSqh23fC4xLyyC7hDgL0gkQeZotsiUBcjrYbR0t jop4XcvbXSvFrw6Y8omm2QlF8xyoJxY814E0rUBheqNoM/IpzcV5nSTOnypRPULfJY0r2Iis2mAu /6mp8X5nx507ntT25I4FSZip2O21/bUGdJHK6DOm17qaRPnnqV+3IIfVjvPFhnrvnaS2T5EVQJOi 1j8/K2YlwFtBEp15pq+C5kUIjMxoOUlHNXy0RQ6gAoCCSyzcOzNosU37nyYz3PG+lxUEpEFSRBIx guoGFr2QlyoxjJrixOl4M8o+F6A4VUMhLuQeDGCBfg9VwuTDcHfadnofafrKMZEffRcRucMX1DAO C5RyHd6XyQ6Z1msZBybNUQmGEyxdahWbzc14Ruu46Wuh0InMHg46YksB79eXGDjznXeOrIQLfxYb Nw+xhvQSNf+Ne+pBxQDJu7vuUpXwqbmeY8Wn8hbiw6Bn7A6ERkOPfm0/oINyWhbKfkcqj7kCj8or fsX4hPP4hhXC2oqDkQ+gqgKhK5S7RhrRn5/NIy+You19ey444OzP1f9QnZjvz0ckmw9qgHn9oX/U +/AGpcR2u3Ug0t+7h0A25ybJ9xEnYuIlx/6kPnfXNQkt44Ye1k6xX2YKCjRHPAE4qkuIti8yvWxJ MSSkW25UtxzoR7mKt2ISN5sMbqtgVr+JR17DU7TxXeXehSyrLB3nO4pejnIDbsocHtMhAiGQGsrc pja0QrWXsryh1WNqfsCOj8bRCCNZRlKOUtxmdzzkLxJRCh4BmKY1Ue/IUb29Apn7KAj5CQKjpWPC +zR4IjG/0k5rqPnxo3Qr2M76Mfb09BmlKI4OR0AMwiMRbNuPdvgOXxO7zOyZdnZ6kx+5bf60tVX9 sMx6XTLot8qIdmrQga6kxjkQ24duWy62NkecsbiogYdCddxmUaTPOYXAkZBQZR+Tz6/oWSC1orPt ePizqgEtqhyjFU6TCEAAlDKJT1f1pldHhIjOq75nDZh8Ba10ydLte8sg17YRMqNk5Wf0S2DJ1hRc lzNNTciZX6NMbMKTNYa79eU4t8//fFSDgNuVDBz4dDMX8n9BXmHQ21aS+a1spN7UlZ42LoKrGywj X2NX/qq+jzn5o8/aAAmkEh8A2+Fk04aF2i22GUZyrCRmclwjzfDkI1NoJyAR/3SSp1WRNSe9bYcS wLZZr86vmjQ+S5YRvGL3Hv53nZ1LqIfhEfc4Sbkedtrs+E+tRGywF4gJF+Eb2dIqWCqhbCMTAG+V i3vL5ig7TMkubUUzZr4ZqGJLtbQBqf+D0O71gj2mKcaE+CZZgwRD6P9slytwqFGAM6idNvdqKJhD X0eELjDnO7/MTgI8DsVgsKqK5Wc/PsxHGPq+evnBojq88HtzRiahP0vTO4kbu6gJklJ6AjX0MZEX Y+//qG21hp7/RUz+uELs+mOIRJdBvfABAeBi3P+Ej7y3dviZ3KQ0MruNThAwfaBZ17ZpALVC3LU/ sY42ETUp0/R4TBuBa46/asyy9/DxppEszMVnL2im//5dYSp0OF5GSZS4Xs6D0D2KVL6SBdg1Va5f 4RVUyYKoaMD+kaWDcEoxsDEaeWutZWJPnHtVWkFYfxsE/a42UvOH27XjLj4mGwGiz+ow7ld+MJKQ P3hor0w4eUcK4gIKx8+CAA4LSiMniQoJcoQAdeivrhFl6xqfMVotL8SEYNLa+nKK+0oPJshQUz5d 4zCN8zfvsr39VkWr+yP4O78ZJShqkqqLS586pMUfQCvUgh4mr6ct62jmaH8dLkzzFDiAFg3NiKDc zpfiaX5JU1qz2qM43ivZiDyb4JchFWx6jNi3fKlB3iKfdVpZChsDYmyPYN38QmyGrdxtvDxGMv4W R/iN3ydNhC0wg+8O3+Tr7Yj2vMUh7zkuRvHfQJlBrj0q8x+VoMjvJsKKbW3MgbDMJQjCK6dioCVd ljaTAjdTZDxCrDwhswcBYOxevKngNak50x9FKP//00z8RZWXFpt3r6fFkfRFMsoh60kTe+7F2jLH uPJiSdrWaW4OlhayQaYpJvu62Vha/bOmueLLJinhe2wa1VlI+cUbg7AZ6pbdyI0avTz/1EzD8RT6 AZ3TfBPb5hNSiQ7XxIW+eVyUVTNP7UNU8JCf7uHnf4kdMs9I1I4aBibKtklOXva0V0/MfdkSGrhv 2oZMTFJc2/QHn6BNBmmPkOe5A8bZgXFZDiZU7Dld5F21TWB1SDvvRYiSz7Qxbh8lau6zvfMpiCp3 dLNig/gSZgoRLi/n1q3hfuIqatr/uri+dzuFRvGuXmkr1w+0AHqLQOSKwhuGzAP8Fzk3JFjNFrb7 H6v07PfAN10WBGuKoxK6OMppHC2HwZjb7TfR14DVnT4944q5dxgHg2KHaEhCiZQLyUTXP7XOhkIq CsFKSR1WQncQP+xpZbtVRWu3cWTCgZMNzfv23/a6ROfpDhOuzU8bcpQMKd/e2329tnn/p3VZBzxb uoECN+vMKSOtXtWNCvCWWlPmts1QWXmBEepfqyNDq8Iti7hY+TboJd72mc2YZEP+prEEjv6x4VRX VMvYraDCiqXi3X3ggqRr+oVey7ijIZQabc3/YQXquHos3l+EEKu6yuZ2FOyqJOpCjACluSxNaOiE 0uogLBRqFDbuhCGinhcnoTm9MbRza9hyxn2em7yxe9JaujBE6wX2nHK//YwOs+gemPKQNg+mZ88b vPFuoz6mwgcpEmcD1gm8CIje4stxhUK6XMgbo/K0HZNLaA6PQJPFRIppiZrHqieIVC5sIA16kPjF 4R0jtJuz98YH80oO1mhcAJddtolT3nvzIMxj0nBLRKwM5CTzT65y8LfV5IFQ+LuRPCHWLVJsat8t YVWJDFQNG6VHgCoDalcQbTGSZpE8n6+VktmMnwt0HmDxk5turvRtz0OQzcffjkLdc1uFh9Dto5bf omY6eN8L4xRaI9uTD+U8xqDJoHRXpTGI+AjGvtspwZFpmnXSrEOMTCOoIS4RLFzKRB9Basu1/5Ya q1YRb+a19Mz3jPUD/KWPPoaRP+Q2rVX/MaseA1Tmvl+mm0A4M6sISqCie4dMgk0qNenyDwhSXoaY SEWHrWvQ/6OCy5a0zyb0YmreBtglvDa16gccsNAySGbBAgeC/KYJY1n5WwmWU1UoWRMhwbbxn2Wt GEJOZSH2YV24jSOSMWilpNVhwZSkeXCQyxRgqIcZm/zIaAx4UYGMPm9zfdWP6bpVmxGUx92Tfqjy MrnAdas+vLLGNiAbnJFP2HBvVJHvKbTMBHZbF8vnoKuD6yBhh/YF8PFgyQ5xv3qqXPK3mqugGqOm gp/dOvmNWUJXCZRNwKyAL6M3dBItlFglUPVmcpDtW8bNF2ti1yJEqrn97IPxhizdqDcaHR79aKSi 5lIIDoaC1DkOYHltqAn9J1zpclH2SqL4cv/gltoqhFp8NBYb2oq4e1qDc1PV4+LnXCP1+RXNC6kV eHhiK7ZIYl7GrBYbT8gz3N5+dtDJ1EKaRQtxIishldrhC4taLzyhl/Ux5gA2g9tfS6TITkvm6kP9 kK0U23ABVUok/wfWW9u1tvb2Cxe9xDq7OIAweLHC/15VcnCF6iuq8L9HQSykd+Ak3cV6+e3/bsVA aTozahTwo7QC2/+jYT+ZCMeUEJ1yl0p5ZArvKbycWnHrWXsofIA3zLJbKw4t1QhwiNBOyJsRmKtM w/Zcitm4QNOx+DVn1k9UbbAG172lpXXsEewuYu9l0hWpiM303is7HaNklo7+2aijxRifdWJLrQ4l WhO7I4j7/U4UMpG9uDWWC2EbTSIGl0fzpAPBBrDczuHqZkbv4QgrAC8vfJkT5KHUm+K6v7P7+VPm lI/2g6U8SnBTKmPxEfcNWgP/73y52rw7pQTDuQ1sTJdPKxClGD0L86JMtGFL/8rwzmQzgYxAC3gj DGww0HrCGrAHob8Z09AVgPXv3ev/iku0qiZSXlWXTVxX1KSAdee1DwpFbLbJ3zHT3vdIclEM1A90 Ox3f36dlnlvLhHNQ+yZCHbmjK025gJGTRdlW8ytV3m1N4nCm748r1tMapBJ0x8PRGqWpgLJNEIXN p4fYH6ermkWaLNzbirkO9PT6Ks1UubEc+bUI8IR+8fcB4ZF6QYwHDeR6u7eMjbsRURe6+6O+E4lh kOv/Y/FfLrMyQB8tVGdfJWLn4rdibxNaP8BUWjy7NKyAVI5HTqGd8BW88IV6QlmHJgcQpB3V0zPC fjL+P0ZfzFvFP4k2hnytUniPfU0/eZNu6fCBGiupXPKh499DiXv1qo6PafoUVXg6z94Dx2YNHGF7 qp5VyPtArwfBGMngZBE5aAi8cqtOyHNU3hk6Fv1I8+5UU/L+qRhfiNqGc4XbSbquz8mMIggf8yo2 uxmRcGbxvulbYW/6b3iXbjHwe8Nz1mHMzGggIs8dNqfw8Ne6D2gMJAsPwHcz9FWJoR8oO51N1CTS 4DhotD90R7p+CwL097CDNH1Fh+jYi3h8u8S3FTgPL3DQgyjaMvWzyYPcb/9YKrmViWhNzPtjqakz ggcfNbDXuUln8KWDHT6Nlrwf5hogl1U5uR4hzK4/cjtNcFT7BBaRbh4vrD08SMddNxB9r6Y9MbtU 1Uf9XwDdWEylTCaMiHppFJ/YVtTVzsjXU1mNNbCYZmwmqQlsaZjLJoSvh8vI8zo5vTs1SEPgFohS v+RivEDpEVHJ1qy91PHyVsGpv0KifPI3IMtn5BRK0S9DOb60NAf36NwFuapi1H6TAn9OgUotslA+ 4Mpl8ZRkXyjViInz5fqCb9eSIZ2fVcAsm3+iZOAnPnGJc5A90YT8J3qNLl33pzMXccByXJc42DDz R/S4+fPd0QoNG8Yw02u8WGev/56yiz1bPadeFKZWtOqopwh3PFRFCG6w2pop89xpCdaEC42zdW29 yHNgxullW5fe6U/+Vw4/6WVJni+cmUvBPeDBhj7C1dSHzxsmPZqpbhAGmw7CiwIE73PhZ3lyibsr 9dVbvFDI3Xkns8nWfMjHvSCQC6YwlBlbuY0lMA0zOmoh5xqavMp8quygLKEo2P6GlcmfTXBCcIDN nxT/YOEs5BmJm0KMYJyxX7GBeUk7gKDsA6+rsVwKW8gYThuZBhzn/XE9aXlYvnBduL7kpFSnjNzO rcs2rTXmGP3OI3RDjJuyAGg+n1pBGnYC/P80CtxVc4FcxS4BWomFEqoQYhM66SCql0kunVhLNWk5 lII34fSls8cH50DSFvUsByeXR8YKCF+9ZlKgOfcZE2DRfjV+ErCZ54DzxR/NOHyX14OoVh91UKxz 93DIwngi0yPVjndZCJgiTub4Agkl7RFAv8ljyIy90/ZimemVtd/YSADQW6ep2C42dMYbQCNYaffU ueVjTSHPwqkfEat96FE00nv1EZybt2ifK8utqJbBTXZ175FFJg07Xf8ekGfVFKIX3VRKG1XGcv3B v0nHeJQGqJp+wvYPeZhCIihh7fbAzbqK2f6BSCwtmPjcXwgCTlRnIK1XnYJ1isXVa12dBAVbRIVq 3kZGv5efZ6Q27RczoKyjH1DeS6z4PVT+wNB5KtX/znMelwP+/Yk++EYrfxKwfMEOc3aOLuou2u61 hIurCQQqkVUX/io/1VPORvzi47sbYfFSRsytAxC7TZLihJMdcEoEzjJPiriqMbVdeJdHehEUAq0x LJYZ8lDFqUeciT7qCyUFeo8cMYADQnfUUctOlR16FmE5qjB8H12zm7xoWs88USeYcySbDCqLoQpV N9A68yOSGuewuwe1y0Acg1BG+Z4241D9wntg6dtaD48xkAIfsSTjhENHaWGFtd6iIhNGJK7ZL8NW WkBFyBTIaEWM1qI7/tXkLI6fzVxz23atdrNiB36Piwqta05lmuPB4gNE+ht0FM3ud9muF8T4xD+5 PWXcR4+08oovgu+03XQeuaG2o2UU+IWDRtX6Gh0n8emIUJq+DSFy93LkT6yPtM2qeA46NtAY287H tnOCr+5WvInAZQGirVACR/Xgl3nn+KugLZ4LaGD8xVUbXaSuBUckgaFbtSuWvJphGDIoQhlrVMAR KZ98AOmV/dH9M3vzL9HI6fla1MXmsjy2Vdy0fj/0z3tbNIwp2oHUXq0i5BNImAbDnC2JdDRocpN+ 9MvqW7+8fGQgqnZhT9KXlPStEjN6URQJ6tK2NBeUefUYidPFvXKv718o3tnJMt6Qgm9Pl1uCJ9ok 3KbJaJ06KKHdMGLCUR+0uRGSUsXcaPSJSn5uqHM0BLQkL1mbkKKqbCM8IhcK0c2A2aH3csIfq7u1 Q79I+QUEfmxO11BdYRzcq4IPY0h2iKjLVRY4puGIzCjzo9W/gw67uB54qsqqAjE9SuZb2tvR7v84 lmXxedw4i+0hMGcdkCJN8AZ7xkUruXgvAjK32jZoiCofgDR2cN/xWj6s8yY6mof2DltrDtlTTXo8 ECgxMCd3lIOt3E8QPPrvzeGQjxmitxsSY/h5GhZyFTfl22236bB8xgUtGNVTpk5ugfbeZLkEB5sv 793d4AVxXgw48XszGAIKrMb7cVKh+5uGqBF4PeQ5SzECbkohZmF19u6EA54wRBv18hdEgRsHkuzL AUeiYv5Tn58+ygXDXXcihhmbSEj5Xnbdk7rHrWF1nGxQIHFXQFM+NKjcJEs6qLUGeTMYmwDVsv8Q aOXcAfUyiOlxQn4U2o2qgrQUKAmssvyatn+wyyPAurOipEgdQ79NKAz2ncUgjo7W9c50fJ/vis+c /85tB2F7LWVUSl1GbCg/+YIgpeFhIBKEPk5rT2cI7L0O243MbUTh8rikBhFdQW3blZ/T9VEJ0fVy NEHXHWiIgmMDjkd0Scd1H8A/DR8XSZ6pt5spTtEA91m+FKlXJy/ukbFu/n49ZQgOt5IWQsywPoXy Nf8QD9NJXuRI1w/nBKO+ZbEEZzvjb19Mev+qgpO9MxNRNp4SwUHAf/nB37eODO0ljuxiorAn8ycR Eim+WNFJWxZJB1wyh4+N6+tdvp9OwWL7MuycLw0VQhyMBzcystmpPj8b70B210FTkNTDUT8ir/83 5eIgaQ9Hu5C83gWPfBMbzqK7AzvF3/9dSVohpaj/Yplmn0QiSxgw9X9ckNUg3o5w3hHnLTsAZmuf nkyJUTVdkdCN1a1En3G1KDU+Th6bL+/1rtdJBoAQy1/B8EMEeAbZvlyi+ImiV4incXstwFd89XSB Q7tmlwvJ6C3ex1l1pJdRoLB52J8UqqCrZ9xUwCX0zE1sTAee8FITwV/1/0uk9XUa47xhDpxd5s0J g5cF7WcrRLGejMex2zJm9X2fv9sYjXypK7CjyrbECiEBIcxBWYSqWaf0nmxZcbx+eoKC8h+m/Qrx ATnQ+etKnBKI5GDztCnQU9nrNpu1fthfYLB3wYdrVXO+5OJoKqzfncvglc+Afol9TF/4xdaDgTeX K6GuQvBxcgMPH471WRg/mmkEJ4ydr32Oqc3qsDxL4DbR50W40y3+YnUfK7JW6fI0bS5cKTAKP8F3 zqrAmAUvHQ1qAWzLcNYouyM9TwVJSTa1dHJsFhgioPHru7OX65CMrBlvSVY0dAHY0Brb0ZvRL87Z SQf4Ttu1ShYbWKwdFrfjrsXLIrY11u9n2Ot1Tk+yHWaUBzRRpvwG7fqTgMCITleim0YG3udQvVhg UbDqJHSkZD8QLeE911i5krNe6FK/qbscK6GuZM3FHOjR/rPWVwKK6QCwmE7uR+8KYRZmb55WqALI WCISpsHQaC7n9OqRHUg6WfNF6iuTtSjlhl8T1EP0jBcRPcfyfiiAMg6FGZa91XWSl0DTIwC0Zhc6 pn8qNZ9A9QqJSUVDV75RMJCJhhiHDIa5CcTmelypEmGisf3NVkpxBlaowkvSPAqrqRoJpbpz9EJN 5uU2nk/iYmsdyozgGXsyVID17qTcjF1CsOAZOQZZR08sLRXiLXH71Vtx76IzNwkKBRjYddY4/29S 85CqvFNqnmdxYqMM8utQ2sKhTIv3KtOP04gdnoUtrfXQOFDJHxoBZfsZwtZHj591A1tnynGkZi+j oeluRL9R9C2kRe2aGXZpB1TGtgaPhem5dcJfEFT8hcG8gNRlDgl6ndh+PchAbEQguQ69cqZQiq8d 6+MrYl0R7vrkTnM7rUM2JprAexzpqNnXpcs8P6GedkYCTcCG6lwuRlewOEVkCSHN878b7D6hCvKZ 8VnsPCX/yD758Wil3P4YumWZggQqOvCpMn/0PbuehLJQKTHw97CLwG5yG63PUuccjP8RLMvkhbgF GpX+5EThD5WlKcEa0+9Za4Ulb5Zu/iQlyMrdkJb32Ti4b5FshJyIKOMCEqROgBAYiK90Qf6FkxRC sOBlKgC7P+Ci/6NH7wvt6PEOfh3tsrdHXtsaLL4Mnzs7UtkNbziwJ/87kkuaNx6yepMkB0DFeA2e xQqKq24rNHGzhqsrtMQQ5nEPscY4VtFQS6nt0aoxPTnRCtj5yk/eIBpgqiqwyGdjDu1lxP7boKev UbFvfKjiNKQV/p+oL3Dw+Uonh9eYT/V6WWRcriRG6yYaJA8vOBQV3AxJ7XBBFuU6h5IyCkHiMz25 vdJa2b9A6mBy/YyY1hvfxDsuAkTtTbgBswkP4V9tnfBeH2826RBfraGkxVtNVVxy1ipzPg7VMx8G b1yi0GnyMGxeEGNNiZyvrdh5YPLbt2KX7w17nEOt0hFK7zCEwcBT9jFftjPe0AGjqf7B9J2wc1iS KkXurJvlzQxCCAZmDSfIDTrkjOlJw+Rqb0PwtFWWu6pN63/SiJpZSiYsTHfYhmd8EJWnOu4z2w8h 8qLk0CFs4MIMDTfhOVl8PxqlpBmq0Jehpam7w2vkGduAor5OurkIT1bBMUQcLA5GsLOvHJxgkViL sT0+6pvkJBlyIoJ+c9iyalUUqMZXdYi00MqX3HKOb+yPuPCyQxHq4yIAMWkduEECoTFMpA88YEtm iZR5+cf5rGmPY3fXJPgKVtohJhar6olYx4twOYMSBvLh3cNWFlTIGZRfv3/UuDLeL8/P0wYruLcP cyyhVKlWV9i0iojnes9UrtenI9iUvrUg3jpoAyc0yyM/1CPHYYp5NIOnc921sVb9iKkbecoAHuIL Llm9UN7fTyEAX5/dgPp3N317GHpTzKXr/8D5Lsb+CLjsbKOe4otaKjvJ8OgNxQnM06N7GOMFZHfY cU3c5tXnl7oz6gSbA38Fe3Muf6Ob/OX5zX2h/uuSxCzjwaX/Eq6/l0iP7KiH4lCbXMydU4UTfXuK Cr1Ucvyt3MQz80uV0+zcELg1SypmZ9azkZz/voL2rT9NhON3Hcl0gNdZhzRUHX8RKuKFDMgTpwB8 0GPPLLsUam2/3HDxH5G6JAJpXsYFY2tByF8b9DKaV+Oxgnjt69E6wbYnNBuJau8qWWTl3o/FF6aQ 7ZDNaoXSTedTQ5LB9E8CR1WT4Vaa6ix+NY0efNAIzpemDKxHowS0EYiMzYmNUOxtcXhMTBWCDmMp lhLyy+/XtVWuCm7yTlCauAwFiaEGUeyKbXPIjIN+jtUSpTyKUfL4SXqvu13VwNrqrJ/axCAoVYaX 5EIXD6mcwOjNTMfp5ke9olQ5NCdCN0VMaxr/F8dMN+rYpTC9CllT4Xp45IV+Pf35erlWhvAnm32V M8jj+f7yB+wfdbLHpXrkwoOpFccdLo7QtisqFxAKUz1XXZlCHb4RfKNJgZU0YlQkH4ie1kymE2+a vow6RIaInJXxXkjrtGBiJKVwsHJj9AeIwVlcUHfPEtcUQcVtYqbOoK7SLgqCEDKzM0rPt2Gg6p5i iJhifDCAG/HH7tHMv3Z1UuhFbO6kBccrsWdXuup9yUtl5Y46HX9FzzvUEK5vYWsIrTjNYwqVrIbW gyO4DCvM/7BwxQBrqkl5wMDexrgz42uLLn2uR6cQpRCBBaZdxaVEszDdV4SmzQMy+dMafGLELKoS Iq8u6ipooqHQFmTPbb0DHr2iUKqQs2bFqRqrqxN2nvSHhHcnJSWOtsTbNCoD+RCZ1OTNCBa5hndY VfxZA279yETgX2pKYbPs78LYalr81yI4k4cwiamQYzOTYR9iztWkm2rnFAuEtM8IHr4grIGJZ02t xvd4PSGcudDO/6OqawGC0+ebt2Hcl4rk97hJbQtnqfyAEA0QzF8mUiD2pMyJjrZ5IBUpLQbZqz5h 4h1nJqWxGZbMpBbBfuSu2xBvEkelz0SQLu7PauTehBbMlOQHto6BlHxrhFhzNNvTkq0DJFo2OhXt WyBSJgzLjC7oJFeviBb1sOC57y+OTdbG2bL5uXWxCOGPcFkHGjIEAOoO4RQn5KdC+/xu/ZoNLa6B 8DqAR1YqoG4Lg/R3PpZW3PBJs4tmQbyKYnvH13Bs4nxarECFZSfDmQDdrWBAKT7OxpSM6QKSVjj+ +h1dtwjuqrBYVdHvxBSoNMTwWrJgV2lIbM4CuqCohw65DCdtKRf3+slB653EBhi5VHKPEHdP4c9V Hz6fVxZ81CLYY+iJAmo6o8HQP4HfT5L+Mkztksg2pnNCB0hDTCN9mifmPw9Gpm642rUjA6q/MmtB G7jSK/b0mJL7dgY3F542fD4T5rDUl7kAdyZGU2HLfELVYtxCVzmYMN8I+L+87g2HZEEYl1x4R8Jg Sl7VTLryM7OzUweECqinORrIMmuITiZq1lxY51YowFxUasCnVaVIyefHhpz8brwWnz2PhKxfqCXU 3fAMusD8jHHPfrvNIfEEg9vmlghJ8PNiKRApD+9wykN2Jev3AWCipj6fgdWo0tg3LzIFYQ/+vU05 jd+iTNDkIN1l17mqEUOYPlDtJ5OS3Xa/AFYz0GBGPsQi8kVc2NcPVh0ucnNrq068GMCxj3CaGICb Ge8f7u7WsumYxnhlABbugMG11SmR/swvqd0OXEzJUIcGQnoUptUb4SFwjfE6qPSsfE4zaCuaKamV HmMhwjviPAcKkz509G7dYoXJB8yunv35331tj0/a1iR9SAm0SsJa2dfxQJRCZLsX5Sb5Uw30l4Lm xxz1kKWaV/t17GjSJdHA3LAITXgcA3jjg/Lhk2A+AdjZiThProKboXmnc9njia4WOXiDvpCweUj8 kmjelRQyvHuV+gdFAYVi8LuSyfd/GAsfERxYhvEKMwGSF/OHSJvNGA2Avki8k8XDsu4kzPRHR1WK VZhOw2st3FZ1nvnc/X/A7Sy5vF2dZqAB0ee9kZzfI2fBKZ2KdvwVXxrcrPTY8veMNnk7MUnsa0K+ lY7DK5iKqniIV5ppsO5d3gh5XL0wq/pZ+0w5kQxUzTVx1SsTdYV4CQxw6eUamv9QaAyEfEQy9XvE EOsfphPe09STiruLHbt/03I98uqK80HDcuj993x6H0v5e7sro5tE9SpCjgE8NhBlzcy/+bTxvCbO q0xhk6cryL7VncR+NXevS3fMvBeiKGOV1/X0Alm3oLktIYpJ2w7jR+2BKemlpg5D39YagIe75xr1 1/VVbPcOGjUanZLwBEjrzV3CpO3Duyb3KOhNH54HoeNpZPKnNoPf+dKxt0xuSvpZrFd/0XO0PvRq o0NDe7Xysc0PQomQ+mqyNf2gSaAs9fZjtck36KD87nZQFd/YWT6wrz/tknswK32gF0dpSIFakVhx 0BTZy8Xtf7uJ2yP20S7D4EGHnZlVM0Y3bepW3Lpu9dgToN5AO/RDUb6U3n5gqVY/TGsAAbYTkW2Y spGfQS7qZ2QymkcwwEVYqcZMM4nE3X2VFVRl3PiBhNetIFfg/9y7kDyXQOI+9ToZiWOiNrsD33Bk TEXzEO0TzB5sER/0NbEquwoaDUaohEqWn0jjWisGU+CMjYV/+Yvyarb0y19JNZmi7S9m39CFP/mT MT7vQR4ttAsjuTCcMWdG76RCTm7JoUoAtHq2b6EDmFb5Nh8KCEunjOQW3r/jjEl65dKKbkaH6HTc BFVPqzfIbAZB1U/99GiU9+tS7qhw88n28mdzqcCW8LrnPQqn5XoKvFo3iJ+k6a6tJvoKmJ4Mhceh Jg1M5ww72WkD6O7YWCjqc68/QpDajdHL0YzM6/zJ/qQ4o+p/X06b0SEnYccVItiR6qnDBEQMZ8aw F35EWj2Eq7nw0IVElEf8vP0PIp1L/ChxdoUIfIYmrUyc/DLC1WmPGoGkbud5QV+Ad5gh3YUgdL0x 4+2Hv3EFzD5NXpExWJSWhn1EodsayLJvZqkSI5RLBizWt83rUNyGTH6Yd1FTldJ1CHnDdTT7fo/x ZI4G0uIx4wD4bLiB24JPeijibA0mr+zK3ynEoKx9ZSqbka4ZEjQTp+3uuqUgWP78Axkin2QnwGUt cGx7mPv+ql5ZAEubWeUHYYsLA0i4wf+aXf4+0W8+d9eIZyf52E3Y0txvnM8Yrg78N0aEeYyz9ugX reGFRsHz7EBCIaNn+6CejkwJk0BiD1dhfTDE+Bm1nfGERAmCNwAUv7AGibJkrQqyBirGjyEDAR58 Hiuy3ODz282PA0S3q0//GPW9ME+eYLar/8J6uQe3B3Yl76lM7wLndwbIwuGKqT1AebszpFYa5GTa spbIGyk2kJyGv1X4OuM4B8C6VTmKJ8vSMbr5YQKiGjwz11yvR4/ATnWyIXDX4VX7eZkSLORa/2KJ axWDIwJZYh0E/7fn7wZJ0rpaY1QV7Id7aNOqKo6S27d8VsWU4BfdjC7yKb2uYZQRYJ8LDN+ZxcNE tedmUoaOr+K44sZ+snXTJGUjEE6ga9Mj7Q/Eyakou17/ltCsjWlaf2ImcLqI6ylukWRK/H0HhABQ jKUqJGIoJhqESJgmED7+HsOnrNniXmh1sC2TErz4/TA6K7/pW47aXoJe3NLw3XwwXFR1cLOfmbCs 0hh+9Hs8l4AOZOzRAIwdFrLE870nvUOPc4cxeUg0MddXIVe0fi5pKa7to1rgBuQt9EO42rAQhH2R 30Vu7TAynwPCyenfoBFfIaRkXphuiSPdKTMELiUChScv1s352O2vVDHfb+p1TbkBG7pmtSg8W8ng zyDi9rBIja8iuTk08JrwVRcj++Hy+KkvRbCSV2/FeaHrGEl3Ug/rzqckXR7It6hmL7DSUSJMDeBb VPFJVLNPMmjcQOTMVkNtn0OgPlU/K6jPtW/jMySgNPXMLeP19NVW3A0EqKaf4NBCarNbp2D6MihN PYcUSMfRg8EamNkId/FZTs3iKGfs1jXCtW9JNN2vb2W5vXUoTCONaq0bucgVbSEBjWZbzQA7wdcW UMjRGiiEqRIWG+ixVPXZbLSKEinVl7o0YiEs4uZ7WGfjTndQtnVO6jhaOOh4S3wSx9DJCeaDzt2y qxD7PUe63V4vqUs6q/OCMQ6gw3HORRSvTsVIeZocW6rrJTqpIdEr2Lh7LumWbCe62v33pW0WoMQn 7S360fPKr3YPwueWZEcThWKT7r2uZOKFGIeZwzhP6lcLhCY+QyVzphkKnqBNsCS9Z37Qg9UEifjZ x0Fy9lhYTAOB5xYV8FyXrq7n7Wq7nUF/LKCUD5A3XzXX5GcfD+kYwdkXS0d8+EGR++aBfLIyxC4D A6Iadf7XFoW61PiqqFDVfxI/iZ6PlAkSTbLIn3huv8zhi24EhLgJ9DV05MM/dHIguHc/0/jfVsoe ZFyNTGGGSmCgqdqkrLgKlHQ/7HB/Isf0e3I8gDgZgmq5r6yMdDOPdl9XVHOvPiRYXwGg65GtVJMw fzTuMI1rriUAdEy3H+32UZkoXOxrO2kBbyExYZHzjlLw0331Xm7tEoBTcUgluHTYn3khw1NIflHo fjmqF31MXMe7KZ0qMr8MGiYDJ/81TkixYp7Hg2FHUzBj+9cxOy7+ImGCQ8M1m15TNk6XDLS5j1DD Ew3O5FcVuaTXP0poDWNYawuVal2yoM5DD3Zgu5cN6WMRIJIur7k8sE6RkUQ1gkjdLArajGGGt+Sy vlm/dzCo+nWHjMactsLioXnr+eL5GUhpZkxmYw6xmI1ZTsNo+ShPVXhDDKox4vTAbttn0UpmdlwR gWCU/HTG4HzkmUVcDLXRUIyYa2s1Z86txKwbIcowj2abS9nI6BaZZaxwwVylSMgTYdlXKuZj0v+y cuPfQ8JV9k9vMCv34pMPi9YHuZG+lOr2WfBuYzJeRLfWvBs0TyHTZbmEnalye92nvPpK6aiiIvYY D9N+aCFRxLCNh1kJHaeab3sFDbcJxmAvqOuYj5KgHcsrDmePg7d1zKpF9M/YiEiNLP3aIlZHSjP5 Z/ATtmtnFqhFQCJRGv3fuA9sDbpFRTtY6zgreURcG49i9sZ17DIFI1RGDK+JoqtglLwT/BGVw+uh 3HXw743hjDnyKQA5Whx4qqfAK/I9EaPidsN3AWPZVLboNweWgn7SaRMyju0UB0t+nTCYNU0yFc3j 7flruMAZMgYjPXSHdpAxBHj0YT5da/yrr/jaCCZAE5+vbOoN1bPuDjT3RFkXC2g+dCx0XTySgrIE DEMDz6R8sC8jZveeS0o9QPKpLxW8f6xm9UTPmCFMv9My9PsQISIgqd3XHD7dEQe8Knpfk4WCZOZ3 2BBfMkGBwigNsyudeuu7irobf/+ItBvqVFpPXhgVluHZCJEklVecm0LhSAm7vJ3lEx49S8X2LLah ApdHrVqEwUaRbvBp0fxUCMUqz40e43p4Cz98OeIDqLG8cYq7HDTXYAxWseURWSrhIJSYtrg8DE9M BHXHwtSuQ63OdQ9xKETrb/AyfAEI5v5/7DXyFNVjE/85ycH4z20O4ovHrjiQEn3LOclUwTIz6mxv nHgHDK8tEJuY1Onndgtn9HH/buFVPBiFJoc6b8Cr7yqb2Oc/7KibURTAREZhXQ/Yydmk0qvhuGx2 dqiucxYrXtdIBBrXSkysLk1P+7UAcQuiYj3HlIqOqxg7Lh3xTSMWO7UXUWBEK9KgTyUgGNcdNsMX FRKJErDG3I8XORYUXv6Snvr10Ld7HJ0bm3PB0TymBnciWWeLXVS9yd3bfsM13WFqJlSsCP974vdm bdhOlQBXXC+mXGlKNmKXEVVSaJC/rE+EE+cKBodsTooqDQzUhXtSsDhXKyR8oeexhSHaY/CiDBdC LLutbN77Jv8WyhVD5iO/uG8p+JrE213M15Rn+PdqaKkBA+PYBKJRxIqcKnPcBCNEMaflZEgbQcFq InqkZy5J+xyeaT0NvRhgOlcpGtCj3oYh68XNdoalQmXXXTS2Fbs1RyKlAxCObPhPXyHm0r7iHzuC TwXR11kZ8o2Px7/zQ4DlFU7ME6OENHhn69rOuJ3cc8eTmtgfqzQ4G6P0YduMHw75uyUZxEuAZ0A2 E1Kn0qQ8Wbn2FxyBpZj2kgxaOL3vFJL8ei6w0OnfuvXapSV1UH0Ozm4h+Evs3Rdy7tCye8UVTo8W EsFVfbJHLTDSot6wmUnRGcNJh4j3YT2fsUWzB6V+fqrV3mTzs7/zJ55Uq4GQjNr1cPmK1CObMdPX OBK+Dk/7mjQVKCisMkYWL29Sp2vIbSvuyNf3xcm1JBqolMOuwbZprQAr5ct9MiU7nk1MzAnsOGtX 7b6Kzr7ZwGL3fa/TxoRfDguia3EFP2k8VF8QX3q42nT1SnfQ/G/YMqV0uGbfoNcF02OO4vE7ikkl BdqjSxIvZdwwWRjU5ycjdK8vYzuYbd68x+VihaKfacwONtmr+bhbIoId5Zh7I5AbUR46FxFM9Zs8 SuS7pPyanmsgokk1qkvoMz2U/38KhiiKKN6wo8BjWmvzZLn2RKiIyaF8OC71SYQAl9Hz7rYXMrVw ao9c+rWirvjcK39RPhoQ28peYJRu3Z4MzEqMI3USW89F6wUvscn0B6CEiA+KQWW2kX/hxpo+gF1Z hv0a0Gxh0piP6IsNz7OiKc4FG3hEYw/fEJBt8W+soJ5LSdbduorEjIuSnTMfoQ9nrJ89KiwfWWNh UeNYUKDXhquAJMjKp/NIiQ7p54TY44b3BcAuqXROIBnKtw5Xdw9sCqsR+OCK4NKMgjzMDlKOY1uI SCJhm/JJcc7bA+VidxbusBt1Jx7BMBE0YoSf8G0PmcNQIgDdb5on0/6npx90Hr2RlGAsenLjMZSX f9j+qE/2+UJeNT+sUqewRdf7UP3yQWBhPU+dJqlyfvbXH/r9x6CfgXjguOebgkiuE1XGq4tmHT5W 64BKD8ndBzqTwTl4UcUN01PnBrDrV9PkbzEhlQVb7gT0X3EN3tsipHYM+QseGq4jW6kAMtWppXrx n1qQyF0e9oKszb/OpT+C8XLdUzFSNrwNFAGrD9d+xVWeqiGmqgcL+ecjHFsXnszQolAKD2IZ2avo 4S0UsUImG7+25L2wqa7yW1SL87ELYxdvaEIYXBN2e2LfC0fwdjBh2p871ItOy3q5CvQMmF3iWJJo lntf5tRcK7j0UmwcPXrO7RP3tr9TbWAVDgJ8Hh3CiE4nIesJ8Lp8it/cxmpVWcb+vEU7sxTEDi9b bDC64zkggMA3Le05j7h8iCeTs8Zhu1SVQC0TfTpRnE5oE3R4ogMUk4hO/RvUS3eeJCm4FHCJLzfo jfypM/NY6OFqccWxOgpHCrFrMeSObsK7yO7STdGr5iE8RH/PgQlwd56v9qnqnVFB4DsJn/WrtI2V PMLCyP0UXs7XmaON5K4ht95UE17gUyT/MEXz+sS+T+zmk10eyRrF5yUJ0NdEWDKd1fu/5T0DHDk/ WPIKZKxTpufKSN/U6ntEBnzTFKdalTcYUSz3OL4D0/foLx4xl+A/pZMXuELhMNAKFt73tc3b15Po aKeJLRVa4B//Das1saTwnR/HdS24tdfDztJ3eKEKPWhZzQdsmMhIzB0lpJagWY5sF4K4dMtk6xP9 YCKxzKT+yFUv3zjVZXXXBqjm0BMeeNSqlI7hMC/ekqRkYUkPS75SVDoU6tlTQr6iBmOwZZUHthRd hSjGlGCuFRxLRZnSIBxlavOqG1/m27+18zb+lsCRo5QsRV9Q5cbyFdSXPwfl4L+EuTvtQ4cLzUqX 508hCPTbTovlNN+XohIrzrIZWjnMnnTPByb/dHoRxkgAOSfgdMjES54+bQ9TeUYb8FPKybndN9im Srbgmb4pBKM7m8NtTKXUddJ82l4BFuA5pD83ux9CI6htTLzKA4mibvoroHUcGnlq0aAdx/DEPwW0 X43nMYNrqUxV9AG4AYiWOotdYmbOnDE7C8EghSKVXlHSnqxIvpT6Lq5gemK/sC7F4ErI7yNAnxPI 9dHTrDmRFuBOL6A51t38pdda5gjXSiAbIQrKJMAeEWkRyN02PCleKgt8P91EG/sncMVE09Bi+lYC 0xeKLEihef+3bt+WkforaP8Ie/Omc+lOpNz0MBpcXYg37dBG9nYsfnuBY2dq5eyLgSdxiwU5x/Mn brdnvW1uKormMEWMohaj09yf2GJtg2MwBypsrjCqbilZc++bkujw+WSRK4u8U9aLEvNHW+IpFbBr 5XsKxgc/uG9OAEhtMGEINT1ht4aq9vKizOn8mm0oSlNWzmPPMLHly6Dul566ofAl83vya7tXbx1X ZVAv4jhpaPv4UWqAWa4ye41bvJGCmP9Q3TxCQpCNoh4WTmnfoETLTV94lcJq6CsFqeYnol6EZQ6c 2zIHeBVACx2jysKMxpTXvgVHL83HpM/zy4pFkqCWhxgPic0CqWYBO5z8iIVa1+1Xk0qHXfjy7Ryn HBQJZk++eoi3J+qdIPN0Ma8/p5aKq46DFOWobNc6wnpgoHdCr3zPM3C8S5q1s0IVDNH5ouk3ZTgA Wfqv6g4wtWQjyHNTJkWEch+7qIgxUF/cEmI7bKkdBYnQGLghI+PbqwWrt8o7dRiWSxyubkhDU9Tt wEBvFyT2Pfh0S3VSz5dFVPDrPOcW93DukLReA2cwOwCR6O6whaCsb+M30e1YnsJY9A6LhlYzeVVL GkcCtrk0h5nkGyv/4pl9McqqCkZdX9DPX0hlDof3RW96jA60n+xwlS21joZXuNoH7l4MBeC8tCVe BtGvq2DF54Tof+oF6QH0vFNY0J5kSStFBk69zlclqAg+kzL8QrFZqkaM4Tks9qnbmaUwTunzYKm3 6XIeWo50FS9Aa1yJ4Hl637bSu7a7VibQsUZms6DLGyKyXfngdl4cCAXcyeK7XA59kt8TRZmFpRwK GzojakOEaUdC5Iq8CoxyOHR/aAlCUazJ/JULd+RFbCGMkeCk9/lQ0oY7WAc8HJch76DqxfEe81dl GblXDD5vw2DKvUuqImbEeNFulKYfjn9K/TwrqZdo8d/3C2EF7WX4Amvw4Ncu9g7yKLq2RpJNAhqG Hl5Tue0WNQ37XDaGzCYrjuoDm64eCagoklNBGC6chP7Zs9zNHqAOaQybjFgoYjroMYAFiIVR1FvR I5SsF8fEfw6pri133qTgsuhOxV9x8pG/Q07NzCraKbKAG+3XPsdgdpZd7x1GuYrVXzBDZxmBI4JL O1zD3QLyKyTdtldjywDSVFrJGpGLs9/RmU/yCBecSfUyfOfOGrT9ofzNjGZ5QWf7mpDd5RT4ghwv WTg6ybhUXwXsbokdcI4RncPXU77I4Dyc9AkIMOyngDvURUzulR1YElC65RRQj2ecs22TuN8NLCdr BYA/24NDcSNalzjjuxHXB8SWqtJY4MoYqNFgI76+WHVlZ+yE1Au6BuXVC3/syhDuxxIZ6Hc7SmKv Q3Ktj0ztZagfVstmmx8763cZ7I90aVpBZKorJzIQcEbyMcMg5FWHaIeLwnCDptQywJnSSzK8VLEU UOEGkENKEZXY3cm49HRnAw3jhztb8vnpCVIxL7etRM03BseR8huc/IVL4XHW2SAWv/MK8MuTWf3Y FAThTH7Fng5e2uXmQdhT+0r0mCm5udlqqOStWxpFGYk2AH4l1gnWHjluJTfxeZWUPvG44hiMbBaf ngngbSbWrF7IDcOV1tVBL4aZAK/YrejNz0bHLwlTw8IobOQFcbqgXFUqIs6RSHLDpcukw2dRN54D y0XmI8Nv+u6Rj66PsS3cYvSYN+4W77Y8p7r3anpRXcFlG1teXc7yYh1S8Q6Bvxip+hmoMAxyDrtz FffHUf/SgqXP+Q7Js2QP08EBlzjdxxhv7FG0O6qgrsckhj/tm1Z86azKNKKz3c7QoQJzR/e/rCeE XBwH/fD1qVi521QOOmctyX99K/05xwlmRs8x+4vc4XHFR63nvlbZDZTxEQD1aS3/UgR9R2wue3ls dEKShR1fFgQbS/jBxBOjbJOBGiLxZ1FjhPZlsRF4KVluER4TEOh+SO9i/zEB1wPbcXrB9fNzzfXM 2wkMDb6r5XQyvTg7jD2e2hzPDH6XiOwhjD0CCpHq5vM+rQ9RvAQE/kcpG411nvbxZoav8vnLcR8r HG0wNUBt9tp8Lz9fme2PWi7WWvqtt9IVlweR1C0UUCsx0bQCaosno2doE8wXovaop4AHFLkwPkNR yZ30bj/DdNZ/QfuvEqJ8VTabCPh2eXDlaodPHH5m3pbwXeq9ebgajeXOotsNqy3VRqupBtqA3z+1 KMR85Lq+jgo4cio3IuDF2aGbMQXn0UFEJ/HyhqcIUK1usQn7y+ztk0iMp6f8WqPKWdr2hnFmaPYB G9BLKJMrGsMwNzNLah9hMgccoUPXsaMzwhO8QI9SuTCee/HlHQcXnCXJGvUOGJrghhHv+El5ygQS Q0/Dym7ZSvUZz+mITV6xZ/BgOIca16/RSUC4Ujc0pFHcoy7dTXRyWS6Yqb+3ZlKX2XK1J5khDYJQ LOzh2KcFN4DiPeA68ft+289yfGCx3EXKa6CJxK2e2qrZ29A6a+hr8x8znqYZUpEE62GkZu+Zjtu/ /8jzXy7CYBT2r4T+yK7b8DFP5uoSSwbuzF81K+DLcu6nlQAmDsK0JDNJRMfxZSmzxt+lYxDJzgp9 I5D1tLGD/PEQW43SNbjzSyATcV5Ue7z+QtVY+bba9EaC6ZKiDDIEU//Pq+38tPqmsdUU7+s+g0Pd xo+eDjsTAmYmf5J0mDHQjTbrR6+tDQf6AwLWENhOwAo8LBMRrykyg5y5muxo4pIwxNs1g5pS0pjV rw2iPJzaUAfLqOXQ1DRAPg9dppsM1pJ5oe1DFDz2e+VuAVMQLix7zVDjlXAIulkDDeSkNydLIYXT I+6HCOkgiCPMLh1FVgm9dtlNS9DdpSMUrORtcCiGN9iLnQM/46VkvDDeANwHjuZvun54fK5ii2Ae PBkQEJ0UZGK/eg/QcfobHSBhIwfvuoAKE/gmXmAKmujGH8wafh4/jXnQT0tlvEDoUYtDhvJXThPd P367Uq8NONO3IwW8TqitfXyrzDlIDQpbs7lySBJGsp+tbuRilFZgFyZLNJWNuBRvHyFh1j1hN1yC QkKQSv2Rvh+M9tylrSkXDTp2nyfmfMgEnjguMztGmJc2XEw2jZy7rPBR8mpwlJ9Tmee2ZaSENNKd CTZdFbwGk7w+BGOYC05xc9HtDhBJ1DMqmHVlsqWKRxxlOrXN8MoWMX5bMAfz8qYu5NnDDqslS0EO c8EmP3m0Uo8o7tW9D3RKVq+RHSwFz2NkvH6dGWT51sKqg4PjVNOeSaMgB1WdOLSFpSOz0o4q9rrx 8UdpY1q2BJkb52oQ5nV+fq9qsz7+DILIXoRNWxPIIpHwo12pVGSHEKhmIZATGKrzefM8q7wwYi8W iH7Qm7MxHb5YMpNXKSm0HmrRc4gmJi2Dp49PnwemU9C3brW4zZO+FzFNHIAS1rTnp8AH/DiQw1dN /nsmVg7dN27He4Kqqp8ixd7yTqanTXyyAQ4cZGMA7j7bm3vfnFlmdZnhe6VrYdv6FJPvEDv2hGCr k7qCfvOMAMNW12JdT70veINAAS6pkZSSkUqga3VjxiNFDFz0lP0LdqN9p6JNm1dBoWu5L0Tdd4wA 0POU7e200fnkh7nNZwO5MoUvLQ3d/iQ4VR68lDxO3/dO04Hi2oQWLw3Tdsnbf+aK9D/Nbi4o1wvz 10AmBfdK/RCywU3pgW9dRzPFqZH4P5i2Z1cmFxKXzlCpThi7kmkbKcAOknaY4FA5nxBJKsxI0Sl0 krcPz2k98kG/+agpDyeaXnM6wia6ybmnwlMdF/C35mx9j37bRfYqVrFrYgjl1L1FboueELFiVfUQ Dxv5q/EKBliQhnyUBYynaMI0U6i4t/MnL6pvDV3Gocz/lVPpn3C2wNXpBRSfiSt21/fPF2bSTNLH bEsE1VmRFc0Py1aDzxLk7vC3Oqqjp9QqTPfF70FO3RFhpPqlKTrdWaLd3zdMG1Zraj2+jLd4Wyge b5vURwSuJFf8x/k3tBu5AGehNADKt3nRpIvjDXBzpDfQtTldN6BmDLbQq/1aT52MALgq51DT44nE ieUVKPAsO2szsfdnJPKJ6NPAzyvEnIIX46gLdfGnnL8C9br/FtzHzkPBT1d1ps0DJptlznQrirIG nrQSH04iqHNeAuDK+nRVfdXsQxV6k4Kd9hQNa6oJlfOeh0vl9CPcaqQAue9qgjImhUureUNnn5Yk Gpf5EVuq6iZjkyyn3fQx7NmDsQ1/9gf4NKNybbdakhQzPTNM6erDmCWDGEuXxCOMzyoLyqksCe8W eGNfBUnNl6Lr24NyzPqohel5cUAooi1YAJHHE+EuPhhbZQZopXy0iKSE7hSNT4d5yM5y1SIjgyrK RHnAkU+K42S1AWqHym1xDpJz57mkJ1ttII7/nuf8SsWHCf31tEEZUkdgXmkLEO92AI6eo8SicPZP YNO9kVI/OGzHZgQMrf7EKF7TbuC0ZopYqjCy00teoZ6RNv1L+qVFjdflyC3YBVdQjBuweOT0qRXJ 0xwWwyVQGKRYrcmeygAkPgKZxaeAc0+UzDvEcyKPtoGxply4I1Tpk13f5q0MM9K63etfZ4qymocS zX28aL+KBFr7nB7xh7XHDtWQyzg9x0MCdAsMdqLODazULVAW8jy0g2K0qZ5ktfu6cF1Bafo/N+/3 p/hVhhiOfnrT/nwef48ewPdLPa52MfU8btd9HyQn5QdAPKwB6mO8J1OXx5aXVBGM1coIf3Iv4bM/ 3mABacPJakSfU0CPbgxD1gCvg54FgF1hev1DtSe0o72jba2C8Witqu0f7TxfRXFj6s1fDUPGgH5M Q1D0cfXNtnP7kqIKGjrFLUFlAPySfMJMQENqigZF0qzJhgYsI+389+M7/pKTgw0/p31TEx/Z8opq PGWFpEffVGvqH5WZhacCkiafy4XsXDeO3sNmHmzubLJwOMzeojlEAHMfQLGxyPbwf7l3ijSHjxpy mIe/tmzsHK3/kD9pBPwOsqJOOZqdVM8twSzp95h4k0YYlOkV175mrZcYN81gChYFhqInyC3hnc28 HhcO+68VbRdaPx2UCOW2V3HWxMSQbgevWpsTVA133aNUw8w32teVpwBZZhGhWW/GgN/Eq08bzwHm WOdFBX8DAgeCpQx+4tdRB8nHauO9QB22fITULuzwauG3OVH/I6QW2/DtR0w4L0tl5G5NQ166B2WO tWsVa+w4bMPftVuIppcibmCCuGqChZPBu4Vj/K8f18oP0EOMubHybqTDSCZT86PDRR96ugcVXmcz zw+5kag3jIfgpr9ENZ/QgyBa6ApsW1VAd/0r8B+Km0B4hs5HEN3fK+wXvpZYmuwZWwQJq8OkiluW KPL0b/hv2ol+P7xImRwwJ0qFG3Fv2jv5ONFIHVvl0nezDvGnyPjuxSuNqhonALwHjZ6cWA9mHCsz cJ32s6mInaliSCWgWzeSOIft5tHibpbxuYUgfb/yI/h4h9RrPfDz6xdGigv8H8fl+6K6k7k1uezg u5x3b10obl8l3FWjhpsNsk1jWqwsL+1Cq4HohaKTMbM1YDY9PSXZ1o21hyj2xdu+hhGohlRqUqmw 8PVmlqVWpsutg3MK0s2jLoPjoVSZxqinlepuoKTRLb8xDcSa8jWyxh7Mz7Hf4T3LocSml/Tl/hy6 7uilRzXegSEqmmokPSQhv5ki4uEaJOPyhECF/aCfjIyVxt3m7lCQguVUlsYoFDiZhVWQ/jj5iUEP uFjtcS/mRJ9ZjgIZ+DbvF4J1LIQUm1YOKgyDyghx5vwrBvZ6KRiQefkWSGc2jt5dDcAnd/uxkBua 7vjdE9FNFDGNWIZgoYI7EIsxqb5tzD6x/B1pTuNjsHWN+r62B1CwfOWNTWSMGqs2Dw3gLv0B6Wj0 iTPCn4APyUbgN6dW45zUG8Ac+0OEwvF3QpUvJvM0Z/xbN2n9BvxKNGFFoh3Fm9VHcWFj4pHsmzgH 37Up8nBxn34JBU4KpcQkkUpdhmxeC+enMT5a4H0wU5+uZ+bt+KE/kRmh7bfNZzvjcpAtbGgiWsvq k34LOZlYyg1vvs4CDZFm2PG7oax4qwFCJbuweR0gpDu67qs5yrHHK1sI9K1r2XjgVGxERDs+bL7q gZKH4g8oMlk0wKVQ+NtqxA2VkMxCJtzOxREoCgE4qv+msNZ/+B1aFvDwKzp+k3xx/910Z8eScWmb j/DNkzPGUD9evEODa7r8h0v6xwuBT4Vc4YCoZp24TNrOBfEBR0Qg5A48mjmO54i0cN+8Cun9jV8w a+L/lqiWWMK25WcHyomP24URWk7kHCd6JRQzN/mRNYPTauQWON/pYTKFy9nZ3mep09kZVkDEvpYo rkUqH0k+y1TyJKk5RQn7MMl16Ary2z9gb9uR7fQ6j25zZQQ5gctq71OHp5FaLRAAxdEDS7Dem8mD f2mx1z33IZwVseaW39DA1UYfvD1134wC2nUoFY5NWGr8BjCXDWa7lCsdcrt0q+KamWqxAWgapzoc jyi/NyR3h+eUesNMo5nxfnK49GUrUx0NxBNHe97prF5Mpx3rM5qtbLOTlF9YaAVOJoCChYqlkrZM csrNrK56JwbX0XhIgP1WzPY+T+3d8sbH78ybh+Rn5+GQHvj1gyBTHycKJm6tLTq9EaWB6YmX2iVN CyRhslvywtEJJTFnzV7IrpOemLfxMrB71g0oCXjftYaTTYggObXgoOuqRjSV4i40xlBJA/Lb2XFm kNRe0aO97DP+tx0exJ4X8lsXZp/Q4BtUaZkai1hWYp37sFJBYoZE4n13vCEIcOdyoXny6x/h4IV+ 4TWQoQNMEVmaNqA1aWMsiYMLPG/h2vrx/x7+p/mEX39V51aLuF+lI4yhW4bLYYOPI/qnpTF5FR+3 qnV1c+FnCo+4uhHlYuCrMOer+LDteexy3CWimMOpSLPOsFkPh5cXLS3DBEXDtDaTDQTEt96SxCqj R4NTHd3OWVfSKbgBQNDLFCQIjpmmpe3QyrVkmOx0yGQbwt22fKZ+wG7c/BQ0WKq3OuvqXlDYFVyW 9YsX7tUd/yIlBIdto+QifWBaBvpW7wXBOrzmCaLaNlqA+7BFFrLNOFgL629gyu2LKf06cZBDKDqG LgISdX1dzfSDv+iLAZbCwPyvovzUtVEoXEhj3slNUaram8iKKdFq3POOTu/IyHv39I4Rkw42Eid5 fU3afHlZlk/nFBrJZQBIOqERppQ7L2txWeEDHYHnhvpY6COxhi6+KDVnMeM15KHASddaLzGBe/Ez 2br2kLjr7NblxwVtghoyEML7fcge+CkVa4wispp/yTq1iHtUI5HSvSHVbOttqzhDhnOiLOvdOXEf cFp7VIiJetRFa4cbLr8kstF9152IL1ETyEe1Bei3/OiiZW9iKE03tOLMKAW6TC2PLbuVvwflVwNF iY8t6c47RkIYVLNH/PsEveDENqKa23k+qkgm9nr2E86CzUuLi3CrWntltQJKvJzBcCnSU8EfpHbe cw9r0EXtWDqQrmDTX2phtGqL3/xbNxDNLnKYi8zv++hsXF2O769Szjs+XnehKE09faKpdELNTXtG yk8+C3ot9821d029kTnicp2nPU7Lwj5gfr8dSs3zU4XTtQYLSIjuanhxvfWxOnx/R7/z6b/9VsK7 8Fj05NhlDMk2Z8LyqiLlUi92By7qlXeQOi4WezJph+bMu4X2Ptt3gv7Czp8ZxbJVo/4VZLUpK5p4 A6LbDDLfVjCJI/of1VlOaKlqFpzLb5OU83ZkdYilSkvRq+vwD+rsEwOOYFcD135gNS/t93k6+jcA YSCDOTA2loyQy+Gq/mdh8kL0I5XW5bmf5FPWGv2POYYBaKv83RZmPV84xclvpc0HRJm2ZJKKtoub 8Vr61N9HT8YwViA63zlmyq5GoHWoVZI0DCQkz8MrnVBWvRuFe4U4/PbgHD7djuwxBOCAlLoMYULx E0IkgTn+ruwOZwFDWxaa4ATE7sL8XCW3Rj3F0XcilF3weNMA8JYAZqB7aJjf5An0X4SdT2F3q3nd CLTY/1G14+KE6sNR2TkmYGE8oJIMWpIgX940lh3Axpwc5XpaMQxxpSxZ8bMAyJJG7LCq/2BzTGqn PP7boGTcfmiWWF8Rxv1sGs9luSe2rmqU2bv0Nx7wpO9GDu5L89gA7tfBzDKesk5hc8mUdBgw63eT rmvtd7GrIQ7z3wZe4ug9YScFm0z2Df4sVb9Nkkob1wcdt/sXoH8tIE369WW4OK/um0WDgvtXKABo 5ATXFL4Zi3kpBOuFhAm3LABDT79MNP276SAKkr6ug1rcwCViks0w4YbACcd7JSJ2WQWxEMe6CtLH 91tlPrzR5P0v4m25DJsXmBHGVWEUeFacQr95FA5BGmtoTPcwt21n2rm7Mj/cOXT3b7EZDWzgJFN4 gQLoDxHZrgq/I+2J3jEA2i/9kRre+fC3T4YQcfLFpn9B8HNA0NOVLPtDidH2Ba/ElYGV88h5UygU x8Gs6Mk1iD7e0zE7eIiwLtbwoKbaD6pBrGxDKIifyvSuyrOFYDJx+ZRnAhRqNZ60YVfZcFw46wZa zJJhCR4tiKSLEbw99mO1nKjNIFp/JFjEvEXuVjm662WlcyrArzzdFGan7lMwbttGnWdSD9WaC0mP lYrmSjdgh5eK/eFQ9HIHRGRv9A4SwEs5TNekWooBG0cUrJgJ6Og7zcjyrQH/L6te034RA16rSYh1 beLZ/Um9C8LuYyjOcXZUjib4NW4ljrubUfVKePHe4aIKVVKbDKegsJDkCfitBxRk4rAObbUOjSgb unRs3nDGRPGOuyPc2GU86V1JC2Zqm5q5PoAnaapM+5tQwLscXpy60SanT8KNVWZavfuN8BztYdJZ muDYlEYv8bIS68FKp92YuWU2A1aPcbydmV8zAe9aBhTy0fUBcmUTE5+nXjALmzTnNhNM0MvT3bpe B6OlDQVxI9gvzJRGc16GweVUuKVcCykHVcwZ+ijHQOKSsU8rn749orzF7wCP7FlBA2UOfxjz6WYz LZKJU5Jdb/saubtpQvE2pY2OONskYR3BxyqnT57Th8IuuN9JIjTulUYHIAE4RE69QEiqlrjWH65h GF76Q99TMxJycGulnDbuKVyXVRYFaGr1gPyuf0GripSQiMrEr55n4rV4kod+3v+Qp5jK4yBuh4UK 14DNlUXXMBZE8smwgJdrvwdOlIbglMzRbnijKmJsy6sLL10CyvVd7FkibAgZKFlAs4Vl8oEDYguw UAZLIJJ4d1VZoNMAfaUY4hU3HDIJpnRwIJCk0ROPhs5ip57gk/H24up3t1klh3kWhyeXA+hS5b7g JcEj7GnACzDCVgRQerwpfVeI6ghAQruMOGNW4KfJmejCcmRzpG3No9gXWExqzfOKssS9VotFpHh4 bAXzyqCHa1Em1wgrZUFzw99rfwreGaWM3txgxUwNpXuKdl8NKgyY7z9zTgjGel4zmWzehNUFc94T kOgGGE0XfJ9AJbrOmBlUnvAkUUnTST0b3tnEqcV8GUWntnwKUXjG8VtxIy3y70EB8XQllfgqawkg evvPIHsDSIBoZvSjht4c7+E9u1jwOe6EVEIAButM+6fz5BYpj47bi0aGqajo8hpFFnJ2KClkc20B XES5XSREeL7lWvwg/rf804I9ZqxseMFE9USBv21AkxeUj1ZQ1yoD7DfMG/n03Uvlext+BitkfOwb TsTEfK3zVM2tSh+WUxo/smbmPj5VTmT8nWIevamuADiM7wR9zxDptHC9JfzgmdtadOHjuD/GiZml rZMDAgbvG2oin0wxvU+NHz9LCauCbhxwvil5NZlGyhClD95wCn5+ILZqGvReU87zLEEfSH8gYFwd qRDimYxOyg6SmUlH2MXoQgYPpWOUAKCjjiiQr5lM1THJr8VGwdWD1zGKfU+JKBQsE8a59DL/glTd gpwezucXNZ6cK1Fwv+NYLWmiM18Bo2dXeFSoENVpv9fu6qtvW8KlXxd6BcV75pIaxVKaAoZjoemS +oxsu5cZqqlEisCB/BSgcGPqcf0dIVm44RzNQjxeTUq/UYg2gqYLF6KaTFuyBG1BJoNdskNndNgX k0muBcwGF5Ie7zCweDKYLhZtFS+h+gb8AJLEsZny2GcGcPz0x1113fAIJTZ5Ni7nv8O70vgxQE+N Yp433I8vQi55w82WSHSvo9XhEF2I5JNP7kktc4d74OdM7WF6ZP0X0GcZjDppl9dQjEePkJcSy7Df 4183/KuXwmvmInnTpsohtYiTtHKZ+EHLPy00mvG5yFp9vFIJQnblYoeK/t3qgcdwcCWgs96j1z/s ClnWl14mnpi8dJs0KZtSX+zUJn/SPXOAIQX0pMhv9BZbD811sUQOMQdvuUPu2JjEq4zq8F9ik82S B3TSXGxd89JBMdediqMGZeOkhIpzZ3GPdfULDVf15TY0Mz25AlDnv93IFptTjzKZKPvQN4YuMUBA /f3YmxAbewbfePTwVF7lY3/1Xr9mJmtl95C0eHMIPmHWGtAsYxq4UgFQjw6NhBe8g/Ba5i5cwHWy 6td2jycTnzNDpQu82vWEFsP9xECQM1D0jcJRanAOEiwgy+29VHCByZoqNisRFcPxWeCW88hV5ciO XoXHma4FfvMFdngDCZ7X5TmkQ2zQNd/r83nPvZnHDPlos9CL/2EWS75mSd+Fg5gfzq/34+EdWlXr V7AyGRl3KWRPXsuHoxuWeZ2E0Prw3qPq/1ioTRuiLYoO62rXslyrx1AC+9zHyNd1SZzvk3jbJVeH YzYeyjBTvGjw2SZHayY3qJUvq5KotvsGfTRW+1G6wCBUvee4qbI3X/DjdzVXL1vereq9egNkzkZd y+ceVhxstRkmS4Aia0+lBwxGfSbCGkVgIeDOv/L2I2R7Aa2i9H8N7MoSrbvT/84C5sz6vRP9nAcL 7pRZQG5xEFVwxuWH8InnFJSnLcOzzD1LpTtkVoMY5+eOA/pbmQnvg5ZNtUb4wNrjVSX3FQdZ4gpK 5hYDH69nqJA95m6uRrncYqelya2rMqJmL5IqEOI4vKn01sfz1fwAasWhmNoud1rH5k/8vBH4hVdq h6KcAhG642bQwFRBKRkHA4z+lNp5q8txfjSda40lpju8qzrQ0xfmqQ0uFpnU9BSpbqcFoulzhgEU aCJyXvZLa9Btua5p2G461UjHRZG6gWrWoTdNZahRlRjJVWITZpEnriqNvmzRvYWysRc/Uzk5eGN7 +oI8EOr6RaH7XXoFOdKK5j4RJGS0WTNbsWHBZYSU1fV5Oc4yPKRYf4IgpOPRYw6Fjtrhe+AWp9D9 V6uNjp1tn9mL3Ujutcb9CVvDWy47lWrlky+Q0rIBpnGEG909wQlgeVtdw63iMUjz3WlsLLnVXEWf La9WtQ0Q2mdC3Lyoyxosoj7wrnOM1cRzfMIlN+r1FzzCkgczEaWw9hVnbPYPn526QDhz4YEtxqL0 mhdwgbcxmrf3DXqpKLxnbA5JBO6RGjKQ2H8WpyXge/wQV/yHARfLgu6pwM7/N9a5aBkLSn8eIf44 lEpb71NgLwSa3mp49bK8YBNIfijQcQJs/mk9eF63TkwIf6LuOUQIF7qOEzNB3z1QOcUXamYMWiZH OtGGEp7xmYaL3MSE8QhdSKtu8bhYTNtVeZEBFdG+63Asqg6KWDIDjs1jX53MGFUFN5RY2bRhdTYl oxvpORAmYVa82F4joYGti58pMu7SWGQyF5mOA3ucwjDqYZ3mfJgHQuKC4O4/+MOcFv7rLGixYmlz bWy4mmg+76mk6QFeYzEFitIHcGirxLvwdc6rq30A6YkZOzPzlSi43d7JodNVhP191KNl3uylC0jk 8HwzhlWW/2HTmobsvpn5j32QVZ5n9zs+N7iH7KAY9SkurrooM4YDgS/eIBJoXb9JWih4xtTWwTn4 S/6A7SNnOBD2cPpMONsnGg3OkK2+fedbq9YIIlHjLdzd75FBq4bdVMqmj2hBaS87l2IndbdxqQSa FKtmu9TQFPOlRatDoAEJiSMU7yUn/I/91AqQEDphtZ2O6itbMAcF8FFBbBHcEI/e4u1+urcxiMEy cUUdZAaey7VBeEWIYZ8aKxRjh6cyOcM4dBjtG3AoB7M66YeTuGRKd8T9QL+8hosyQkVLNaRputr7 Am1LBvh1unMT9vJhmf7wwVXAh41mkXFPeIWIQKBLu+08yxT3ap4O1FvT9nTlIMKBO7WyfgD7PMJj pIKaTFx26e7P+wdQN58WCtNTvEoeInznt8TI37JVl6Kcd/tX4HrHozT+VTGAqKYVd3qXgBzAJh3s p6+IrOuQ9yttE3PNcRpOtdUEcX96OR5tIp9DsVlHQocW+naH0QNCxxyzssuAaxymR/XPq3UAgGb/ HNB91G76IUQz2oM+7MBaKjj1jLUhVdrazE0frhCLlamO/IqpMDfJRIfg06vIedFGwVLLZg7oTbXB 45eVKInsGNPw2AOI4Dquyg5S8XPxwjhqPuiIGC+BUbH8n2vfVWxHR9eYvNZGbHROd8ViVAweqJoo SO3TovVqQZTAw2cguQ4OoGkRNGsvr2XFfDeiFK6x8axBADixEFFB3XTFwEm163A6e170y6YbfLY7 mhcpqNLCLFwvtfb4q5KqYqJOMcUBIEgch/GwNheh8fYdYC2e1uSvuCzjpe8ARY68ifunm4DcDSMo FAO8hmo09QuHGaGQ0jDgfWzM8ZUME7AdjVrR3b3IrzFZwyy/YfAPO7qntmwdqutnFGSJ6DWtqc7i H6jOOa/cp+/d85cN7bIMpQjttw5zbN1no+p2u0GEnDHDNUZTaKO9rsDjH4kYwqSEMGVSZcy+aPJe F77o06O7MtB2XOAHDzoyn9YmsHvM+qYTL0f6YD+trYyGuFRN0eZnZFaJLUiQYwC+tnC6NXhIeztD jRddU11l7GGQ2Ch0FJbUG/BL2fSfCGpJS7JFxZ2vQsguXT+WVTXQzXt8mDPeSNNEaHOJYH69awgV ey02NYPtYyzM6kP7c/aOCB8Z6jmyxtsJck9CbIMlQSG3C+x5+NSzV7CyHqIY8QazbvFlOvlKEr5/ Guuqh/r0N5DCwEHRQFM5GaB1BwISrLwdj9Z+y474z2H9wQOj767E5fh/+Kx73nj/vKbnvrAxNmpn wdSHdeNIsPxg69VOEmeKm4aFtXAJJgZDKEYRRGsjsykhbr1qa7a4qijmhUKvXVKnDsf93BHJzRAv wIM/u6516KTmVT6Cwj8dpLm4UvCeUT586yojgUax1ArG2eg/27ycvyYZ7xXHCDHDDBjyegSZRpHD kqvr+NH0VJbbSH+M3CGIfw6XvL1A2eHLUDSSZhhfjrmKjsf59g3jZFu9vNAmRRi0i88kfrKitMgE kS/10f0jbgxFL2wP2C0xF1G0EsYbaDGziPuoBGZZf/MfZmiRzZFU88ncF21uoKEgHMCAGfAM2SJh WjuKbtsXw/9L8KNZoEVIftt/jN60lQwOk8exQWxv3VxXjomeCf/3vb6Qrrt0cmxQ9F8N86rF/JkM KPa2XlMmwg5MQGTwM7Z0uGgCncRrvMqy4S6vHaj2ZeRFD0lEBaKx2hOGe1PeBlqzqICjcelAwAD6 ZIbEZ7izw6085CYaQVzn3NFEHiG3Ot+LM7nhxY+0f6+78J3j5RZBATq/J4+ogEPKOw5VqXoSuGn3 MMFNNqau3nCSCyPtS4Z82YPjexs6Uu59kzFF3HDZADJKFaHrDD8BCe7VROVTtU0H0ZP2KKRPQttt Wp+BvmfKZIBgY8lwxvS/pljVk2Az4jLIGQe0pbfZ/5GT6TLx4plp+etiFn2WSy9AS8f/rDO60A8f Nn9+MTxldq6c6TrFe22E4chwWR3fT+1nxvcEBDKADtwI3b2aME3dOshpnICMfG4/dpWcvimNmQQ8 ZEdVeOqkO+hDgIbwlBCOuMHQwh4YiNzHNAdHcRCzJRGW0hHZYD9dharC6MeI5ffL7RRcQE3n2i3v FTkhpSh7DZoIYzUGW6zP0/XwHw+lzLxfZHGHffTuoDBxVKYclhyROf+rgPIvhbIWZR+/inF2l79Q OHlQNCZftheLXrQpX24BL/Xs38uh4clZlkocXF3tRHCWz6UIbNzN5CjVdndknKM/rNCuHcH7CFm3 owFkWXm930RXR4SGXvsqMMxHTNgoKHi1oozl1Q+YIzy9E/enq+J8NGOkJr+d5si5Diql5deAgVG7 c9RDIbVNUSB4CsM1XZJuBq49wu9g09B2z8Z4W7e5UN4IZi9j84w7NtO6zVn/KMIDlj90Rmdj7Dfj I/2c6yTV6xTf32TzlUhNJ7isLExigSV3HlQ3PU5/tvannbO3XPGfMqJwe+nOpauc1woZxnNJ0B4/ 64niCb0i63k3/mfWfjhup9ZLjacdt3DIbbpstGUZcHiu3Y7oH8yYoXo/khDjn3Nxb+jN/1hlbhBq O/1K7ZLJSLuLBZFWPRZbGksmZ8MvY708NvQUROSLdIGz+OZnsztngw2DPyL4kZEwW7s5e83HK9bC D8N4D2sLv1x3MSeWQVXrYHVIO5STr7eqmN6SU/h4VVK17Hs9VNf0DLWZX1k3DwCC5RdZ52gt9YG3 gcJW1E4hfOOtfYaTfIWOBtpV71ZLQiiAPEK8OEWq0wqkR1ExlKfLpkNIi/0n3luvAmYYw8BQNd37 U7KHgCE0WtNkJcgLT6hcIhKS6fJlL9uArgt/trI2zuqsoHX8+soRqtfWuMN5zzUDENsHLSiSeA+D /7K6ho6fC/X1dKkjpAB+KnC4IEOKwU+C4G1u73D0lwZ4pyZKxDX7LGZWJrSF91odlw1HtdLL4i8h pVdlzUG47VGvFNGIaO8tAoDtkng816MjzMb51ti53HB29u2wB7Ajrw2hVH/AdfGaDFrGQklA0GST 9xAJYXiX1jng/3pBelvZggesnaI9p8NjwCOjw0zUAOfpIN7+S3vIZPVFTZyipI6eWedymxHbpbk3 zcrW+kcpUvL5Xm2UE0ChgJRbvG/eJDnBU7x9T3uUSdihGhBco0g/4zEWs1oDLmw1l+Hu5ywNW+xI QK8n2tYtdGAjPBEY6Nx+Zv5WfOTCVMzJfdW48t5K+55bdI2igfgNoRb542jD7EN1ZAx/oBofnE5P KEZU/bON4CR0VDHTGLaaeIjsXl3j/tsAlK5aCcg/FtssN/JO6aya0qcR43ya0r8NlnXPkdFEe1RZ Q/QY/ZWNShOfwp4yj1lx7/de+wM+C0xou1f3/1ZJYxHdskGn7fDfz0H9RaAT4LEJ7AHx/4vAv80J IWkYviho+cKebimt6wv8Kaq/6TsAgZGK/hwjzAVviFYCmT8OkbYWpgjjYZxVFdyHcwlJLNdVTd/w KbiWY0t8dBVGEGTbp2CFNMu9FBaaK3wQhjdgMVI135RcLywiCljR9CbnzyY2kMovhJKdI+8tBV9y WpMzMUuciWILwfDqr+mFc6X6u26VukUT2L07oWPl2DwSsnUIjiyCuvLNIz0xKbOraInVWAXC49xN WxIkQMXBXFn7BfmT9QeU6fjvE+Cg37KPB5ZJ7lzz27sT09UkPS/NK5E/z1Ym5ZZMJ+cy/vPUvUHq Joraei+di+8LEKh9ks0Qty1BJDsD16SR3izJFDwpO8NwD6P94Snc74qIcHqV2as30l4DowzuIQMr aRnoM3Mtwn2hHHWXhbOn0rFLPJIiJ/iZ8c4Z7TMh7ENA1VnUkrirmjItugnqWNZGxLj9pXjKQYET TxgB2kR/3PrZZni+QYrfHfU7bxZiVwssCiRRBJMKShxtBT9h3TmhjBCVr7UbEh9D5AQ3a6aCQzNX zOa6JJSIWz1mj+7wIY9Tp8HLOu29OJBYz5iLsHah8U6AAfXG8jZxBYIUKX2aFHWI811FF4DAP8bp eKkeC5PyTfBNf2aK0be0qV9vVXex1OZFRzfLMZPLj0KjwPS/IeTLuEUqrNRQh/l+aqy79x+/lqG3 NXE8fKwHZytQzVR1OK7VI+2SmuOschBV1wBSBS8yvIPCrQ5WVybkDcuZCIxLwhRe1bAAvJwtEIzb tzI/QKKpwD+R9hQD15inUenF5pyF7zxDFrRX8BKRGXEoZeddo8fQNYBigZIu8GmxqWDJICow8o5L IVoTeI4ZuQEUL7KIbgqR7BxFN7dBVJN4P8BBYwA2yl9kRwBk6nulNo9nzGPAA+Am2F+3Fcncdnwh fH/OwYebPR9SCpxN/NTVEcBCcUOqpZ5zwKCuHYJ4E5x14OjpYlDxjroKEmRWE5KXyjwlUCjTJy+l 4lAWKSoYG3gJHuQmIa91+hemB++FP/p7OmMnL1h5WAhI7iL4I+BCSTJHlkZtUKNVqKLF+uGt2We1 ymcm6VIDwNN7UVBsm7xKIMtQ68DBzF7ZNI4WKp6O9XEjSbRzVDSuZTV+I0QOd/n3GVeWJtzyFvyl a7789x9ICc2RVNtkoDrRBnnb8tksWHIJnF4kKILm4xvSlKXo5JY2Ms382t8U6Jjx4GykVsSeMt2U PGKDF1Rp1df+vu4qakFNzIia7Kp4vEcmP7W64MFkcoenu1vvWNoT/GlEPnL8NpFNKJ2JAAjuoV80 Z6XC481fKW63IBi7m6uuegdAHogvvifsPVwuHdjkivyZXjVSMSkKT4EowsaeJEnFUmS9YJQE6I0Z u4pVdpY8dT1e+gVvVpIBuZps4BYNizQATh5VLiPYJJrccFrWtxk7mehsBt/AIfKK0kR1CilxvtIQ po75O4K1Hp/qlBICycRCldeKsE4jkDbVmI9jPGrTcSI67h89mCXbiz/f0bCfQzzp863azemZEVky yeEJOmlmhNd9rYOiYpHL9WzGTDIU1Sqo8KD7FnSvVsYU8utQYC2cL2yjuJ1B/qlvvPltBRSIRy6N I7vBBxwdSHmszucIQh2HvIzvqrkMhVWWof4oPKS5GjxXjURTz4Nu+FYru2YtL9BPjVyuoE6ouBOQ pV+TEYB6hLK02gHSSONOgWFgzZcDnlAIR+ni1M3BgpyYpjxt6nXrIeZiVhqMKxM5qJt6E7OovATW Gpdw0/HOGxus4mk3Cv7h4L0Zo5dHRwdFm+G9LJrLJQnYzeR8hETmODBR/AvkRTiEetin6Ojp3Gpc zNUewVOnqjOYIKM3bEbL6gJLKuT0dLuCqpeQ1NcxmrMId76ef2cY8B7j/nhvKjde0fxLTQElVGOw zmuz6JJgZd6g1x5PJXSFTKuO5UnhAjZeScvtu46p9FxUa2Tw2XBGwtzp6c72vi8P8TMwYDcliDvN Qhahj/yAr915nAuusNEoLg6s6a9+odahypwEDQRamheBrqmO3t709z0u8pjssNDGh81RD6+gP+sF TXzOoLLx9ZWQJcWVlMbOUW5Gst8HA9SBY851baRhYI2UGyTUHOsSimRxVupDbRMuBy60l0OP36gk WbaL3U0rC+jWq4pQAPFuFOgfHZeNXNtCa8D1tlKoLtYwrOAufUnpVYbZt0H/RTUS88yGDpzspKU0 P5C0OcN0tN6P3mXEsrv6viSpfEjMjgpDKoMNDaBmIZa6X8idB9rNtCSIUDumKDHTkYYfQ3ft+HQ+ TMg1o7kTYEaXkFGmQ5hiwX7Y0VoXUsOsaBjF4QXXIeRaiU+N62kgAhMl2ijU+KiL4ylO0irqu5a7 PwCDpj2NTjZtwCQch8KN/Ub+qGiSGNMmWv4u1RvjVYilwV6ttqbfBKMynbsxfJ2IzvXDeRp2B3+N JMgnusTjebuA58IKCvzFMx+Zffl4sk7ZBCKPzE/j4mps70VS10DISgVzH/I5aEOgyWDLwmDpQVN7 7PBQj2DqG3JsixvNvfPHNUrwYkvBH9nup3kY15rmNaFRcUBCzNAyHgjnUw+KfxtDZyXEujngWB7r lYJFON6IxCEpStKbrv4Q1Yv8pM6U3NNbZAmc+iuzOdws6u4Cb50ssmIi5NtyLbs5fkWkvLDZkU9G u9pMZ4w2jZFJGBHmKEw9OABxS8ia7DzyFu28YclrZqTgo3PVayIJQLGx9OhTG36QrbhxTOSdxdw6 2BrQPS9SZwlnmEf9sHmkwPYJe4fRVEp9rhZjra5rS35IlVbbygy/6YND6jXdzuqKwSP8AyI3rNYq 64kvkvCFB9hv3TB6cPmp/Q9v6PFELULDVyR+Q/5dJtkTBXoE/XMAqF2ADqHpPlCfl6BEpxbfHEHX 6BYnCvzsHg8VSKhUD7cHvLlwXtskdq0IPdijQzkI5B0HViTEbLZ/BtAUAxAFbAeAUdUn2dq1Hms7 3GI5dI/vcXwITWXRc2egu05r3GtThbFBVpqtzreAB5noeqRCTv0hOFJSU0MbI1360StaJpMgxqND XeJonDtfTRhk8I/d0QcRWDKyr65jxTbHyolKgDexqZmA9X5prHlRW/iEAotNab8RQDdb2kOoLV+t HZIVabIFDpnDygTo9EiijSUYstaSmt4W2WWB6Ld51U6aJF0vRL3AsOWxwfvec1F67LYQG8sy1Fy/ CfSEaY157YUIc2AbQTxg0BeVxgey3oNbA1MSYF7V3jCLk3Oyo2aiRwQj9mN5kQNCQ9uch3BF+4ay +CGoCCAYpGaJNdUlwrvBnaztD1Pr66XZ9bPxS28jf9dhm508RgdsL3L2eF/zvZY/qVLGQ7de9+Yh YMB05TGVGwiu01YUN4DBJ9MWq3ytp9VA7wPuyCOHlLlF5e2BJKCm00p2QxVWFQgMOnJmmijit42R VV1KcN83xnT7r+Bz7UhdWvGIE0lvdkuUILn53sIsyZZMspNKy9V2GIRbKSAsJEjEXIzxuUTa/dEl QljB4OePG4eMl/d24a5Q8LyZafS/81jISQ02avCRVTCFsoQ95moHsL4vR+YibmCovjHL15KCwtMi oldkWPMMYAXh/25Vt2HBJae8ejc4B65BbwHoui9pJdP+nLxm50YvwcrCuUj40WqTRB/vIP6dlIzU rU64G0KCoelnJKVvyMBXz9QL5SE571PIFj5KhGzoNGhSChvYyNBGDRYRXWGw3jBKXz0VdVyrTwOG wPwNOqFF34U+TSEG+nZl5KBByV8RlPC1F/W0u60PKyT/AcxHOQR6iXF9FOTH8Fb2oj3RwtrliRUu EFxxW42NUylL1iavjOT/v2yUz2AUC1p+UbVtRYc10WDhqhapNjP5eBExsaZVSetBCM9gpIk+oNi9 axZ6wlxPQuSgYBitARFfrZsRc7Tdl0pmcjTdPc0vupEvQErO+v4EcCDatfnqZGObkCKf87FenNgM +jGak03NJDuAzPHged5w9Njpt/TnlzaJnXKInIdqQyUsd8A50Ev0ZwJn8XN/p+76RBvCQGYBKDNm hXMT2/+rDDrmKHpv90Oc9r8GkWC12RZMmw+e9J6UV56fhBbQOyUJOmT/h822Ds9krWFXHPBRWPv/ 6CAxrSXPYit+Mfi2frZTrqcVPXzYxHzxkii2ZUX0VXUouFRIhEFWkX5CVbJgSyZTxcFihqcF/r9Q rFA+pQccYqroe52wbu9o2bO+GmYw8G8zUpaMbZbWJ4f8Sn7ZSsq6eHO1Lq1FLgDnytUlvacEseO9 8unRuqCnGiZb2AZjrk2ul/KJE+96054K3Tmbke1f+3PELbgjwqP5bOaET8kJLSRVwIUm6Mm3mhvN /+WXtLp7qXa2Fn6GjARHnZIkTm2hovQZizFftaB/tuZaBM7+mbqmcU1WlMJBfDL3QlFpYrlrrY3d mc7yLkNpxWSthkG9jgDzqcYooj3EXBaXFQe//lhBSqssHv4McfunSlncxOuEHhwrPJQxRsF19TW9 hRAYCbBtkIEwm5suWfevIwBNqUMwrwaYRC9EG2ISSWyRNDErpX0bNaaRUzN4bfvIOxRaDcJKA3NH G0q/mUTKfe9sHieNntacsID6fOuDlascmVEAjdJOC2Io2Btp3Pmt5D7WD/Kbm/TWPYd4p2CLAAQk qS/fB+8KrN562fKh6f6BdsVWZp00fzyJ4ZRkk9j40odirMSGlUC1E7KUOkRhttVozsEWsu5Q/tcC U8+HUFhlUuzU4UyM7iz+EhS/2tyxAoFH1ttDyhMeJAuyhVKyYTR0bIp9n1qf1a6s3lLyYxbnG/9P 2ygT6WOgp1ZY1mUNd4xDQ7wJILqK2oyIC5qEZ8ymNx9klccUvNimRY2cIIMicr8nG7qGe6jdoeSt mHGiXYUoc3xi6n1PMhQAxmYG1lmv1ATBzngS9mM991d9SHxCLb1AEKyD/edTMaZI8KL9tWtTvZZj iR8xwAYTYp0h7s6z6qLjCq/zBEEhn+8qLrMVYcgP3qv1xlge9ztA7amZse10kJSB+Sougc5nPKAG 0AhgczuZ7R9mX/HmkxDUhq+xnqN2oR+RkrV3UY4WynrSwWsz+Q+MS5tBjSlfvUBlqXPut6mJZBx7 X3c+/hxSKHYQKeGAc44jXT1cZtWmx77N9AC/PDjoc3avPp8Aj+k46l2Y0aMJlw4HMrJ9VDfJCOjP OwldHkOD9wY16ojqn1cHa8F4QwiVHmHEDK8xDvrwmQkFnlgXImwO4XNgOKU2Jv6hl7F5qVmMGqxU pgXaakZeFeCBM2T7bHX76PunlvvBBFf0lQ9lp53jBp7t3h7EI5ju7irCMMJyHZapE7chxJLqzi2V KEjliuqEIRNE4x3ViqTl+krQgYpDtTTxH6FHdjXhq+5e9spP+kmCw1Y4RyqQ/GyrUvx8G8D6+gHy uqWrnPkqv2btEIP7mdbFWjFvtK7cI3RsFtQ33sVCSfVO6ldAb2XRKVjr02g4VkEhSLj5lP3+sF1t ikGtgFX3/glXgWalnClvwSgVARWBRJOqSu0mQIodP5sa9LF3ATzaptGW4VM84BaxFEbfm9f6Ybvr K7zeDzQ84y8b++WlvmZY12lvCDxSusIsGHipp7dPvBlGrG6BIWvrmX1KIn5wZfdifAJQF8uq/gnw H8YI0zdwpNUvGZ28cvT+cL8b9sGtv60n440WUK0+N+MzUvPtUI6A4Z7wtN3wBOn1Cmq2vfChiSZt ncMoM7e6JGYVXXB32kM0YzmKGnaGM8NlzHu7hJZ1CAjZJTygYAjbdlbHKmmgdKB8PcNqq48+ltZb V8Px9Pm29Rv4MFLTH2eUF03C68rGVmvTZo1MVUDcbCS22HKxDEOZFpZfTkgnk2VFyOZbxTmAkTtr wrY/Cm+JdtcohS7JDuOaV/g4nGvX76khEVm6OZ+7hL/7H6jbG1RvjKKnlp+7YudFZraa4EnbFYzi LHo0LBtlhdG4nRBr9LIJBN/CZQpFv/5j8lxfoYPzmOdpJX1X8oOxjn3rokVR4DKNa7gbPBmgcnSl zbaVt4NeEwH8rfQXexPlt9yLUgzgO9dYeE/Gt2POdaXRebd9KQd+IIzwwzn7vGfy6oi7etr8daAM BPlUwbYr4NSk9KQ+NPyFu5PKxNKrTPgXXsx0IK9Fc+M0YqDSvXsuwlqy++rvWodXtKw9f/goJZnJ RAorLt/tP7a5WlvjrIhPg5qc7WHKxWXs4FGg9dBmEHguDtRG5RqeVR7TkrIQo6s1xceMRPogrjQ6 REFikt2NjYrP16MZL44aoCcnNexb0YiTkas9Bqh4so2I90sqISzSwOKuM/ZT2EMZxOj8RVppdI8K UHJfWiUNxBZCRDPQ8Ks4IjJ8tVLp+hLTP1nwpD/tejCLH05URgCjXf/fuvYFcr1V9bOH9yQMbn+V uhKN+MvXFu/ZLVKwIsGMhMYRCi0i1CStnkBL27WCkdgGCJ/8CCeftuKlABf7LYFXW5hCyZKyd7OL q98WRh53RxJ0Eu8FVxbgWN4rL8Sow5s0RhEdNFnOuxjANpJrX7Co4z3y2sdkHOIBeVjsHfXqj6gU YNJaiN0h1diCtr/6Jr0euwZjfpjO5k62XhDxle13zUFbWEWOtvxcQRDR1666ulRcxMepEfsMBFkQ hGJHiAAO6lpkAkdGs3dt5SkOaGyh0MMBxbdMFQYD5GAB19FWX6SaChbdBnF5gG6VKdfHV66dS2dY MmZwVz+0VLCzgsLgduM1druPhqn/JnLh5U43LZAif5nQeLzMDqc3HtTUdaXLEpZJiZiZ8bKId6hE HsAx5IUDs5Vf+MRhEYLMxgDqo5I9asY2xZlNeNwR10l6M/YNeNWq7mY2FP4D0ElPa1gNcvA4WYsj Miq0TxVUn+bnSkgJklwJub9Bm5EKfmY/YSxCYLvqu4zveUreUDNKmZ6DEJzDwQxS4V3yoNa/9jKd f95S46OlxWv/0rTWhIgF6tUJuW54I9HYHBLS6JcZd4Ia8chEd+q1VcedTcTQDA4wdnPXC0vZzXUP Ysr/26pSnpQHTwo0J2GwR0yr3CQSP/+yBVazZUi441kEatPahEp3bYyvdfONxNkeP5rQ7ISGgeke WzXlC99U6zgUGXDtKjAy9KKzX4ny++EZGvjEDDciNaIpAKzbWOyEYB+rhRoOMOqGRR2T1AAQnhfH PsL3f7LEbHd7AiL9n1i0GAEd4dYp5RpUZ+qhGjVveSiYGxdmLUknu7jGsHeArGVCigGBJYt5w9uQ kRGo3G3X+FU6d5SET3sR1jnzKtmy0e6XxJuCQeXumrbqHOw2LiQlU/yiX6ln+oCtzdQOI6RpyGOJ IKN6kbBEFjluhj3fxHMfUxr3TXdNzySpVnkzPHChVZWhf8rd68xUo3tr4yF5lWQ48KSjhZSWLHf/ WZZVfpQmPHQoqLZ8DjyNjW8oKRmr1OIqx5gh3vMQkOip7oQtePA35ihSm+JgmBl/w/1DqY0wmEEb 5DIi+6OZfQlYGhvyZuT9Ot2DD/Hx/hSFcJCn8+5FZMVBlMdV2RpVGJA3sTjN3xpATTM+j62behTw tlXUrRzgI6vUPXU/FHg9owjD/5zuRA203inU4Iy1eUXTmx4r/lgEQ2wp+Uj04TFinVaeWw15dfWA mHLD4MOEk2coDCzcOPfIub/w2LLoavsYvwHOzlDgzWX4iQrjJZfDkRIlg8MJE7JVIHxGfRVXDNDa 7uD7KD7P7Aav7B8V/B8ZVdr3zmC9qIuSnsVMNFv2gWFOK5LX+EYDzwaTZiIBli7znMuPdVZ3HicV Ufr87Qi9KPOLc906MmsY5uTFeTQ+moIGsXh1QIOuSndaPlBtgskx9t3oidXmnAeYG75j2S9ZuA0v cbRHpDmUQRkWayQgB+UKe7Pnviqvt3gLFUnKH3JqrVMz4h3jvR/K/5UT0oCkh7vaXyg4ww9f7r7R T/pu7ijtWvFwf+SW2dijbxnpKtcO4L7kyNVNzs8HXxGZyrk1vHixNn7qeMToJS/vLDtUbFoZv4gZ evTkOf14EU8g9ICvLc/UAmOBb3MRoW0cqCI283n03215HotZqe4JIBZ4iei04wL1JWkNwxHK76Nw e/11Gyrdk7geoyd6rNaadr24A3CKLiJyx7KeLe9tmBz4HAOMf61wp1AXwDl1PIFnxF5HOOjGpZk6 bknvNbR4K4lZGPagl9Ky9ZB4Dh23YzeWR/74c5neXmdAXVdkL9ZUTQ3LcIfReQVoYJQQVsuAMC3e +r4ve9mexp8oTvpcinPWKNYxveHvSb/sWoqMNvxSJxMmuBmlcUklIP5vV/15a0MoZAkawCdmKynC yWp+JD4AeUg3O7hd5pzgohvzVu5f6i1BxKH0M9IfBpw1JcWMS74CdG7rAUQL5B13KEOQ8JLQ7+mx poes011mdQzuKaQZbBXd2TGExDHe1PEjIZH3Pl7d8SXreleP31GHcE842j9B2NpfXcDgmR0VB0Im M4wgTk765OfCOp9gkgp4ZDZh6CpRFKELF2J7L4MuiQLJLh+TaDrxfKEAz9qSUCYa+7cQFvH4Ea5E UEakWpkyVz89FCHo6tX7yPLBpyUNRpPP5QSMY14QgeqGfQuJ8mfCxtdos7nGTQLYBh0zsMH2jAVE D4G4/1HFh0eEteupfSxVcM/8NSs1/eMxhJEqOXFS99yzPtTYadzTzlg6AHtkTK0L5iferZrUyD9O K0hzX1VrP10R3gSBlYjfYnEz0D13uGSQkTMyp+SqZP2UQKXeLfsayBzNbRoL2vDtPpJ3CUuRw2ab 2Bjl05zXcw1ogn8GgYJ3okm4X9NwQt3Twu4fuD2Cvii9FfOeLVEUbT8Phf6ThFvHYJoKpHSHGdwT yihqvwKwLa81zLt2XZi2KKgyGgwt/Lrwl9+aOfBCDtu1HFdzOfXEiT4zr19bmRnSL2K9xxP8DqJB z195RfOKGlZDim77uBk+oH+TC2ofs0wIxTTfNpRgQ5pAveeQUT6owd45y4z4w6RLnpYI5ea6xqqn ar3q3oONmwB6mnxV/0sM6/hdbvbGm84md5xqYLGJ1w8NeZaiKKcsfosaUjIKfMb4SZ4YTglB+Jnm XX2cCMiW7gRo86pi1bZ1aT+/hhG5NI1BwmMQfGkO8t5cbUznX9VtU1ig5+z6CnG+mZ/uZla76yma sg3kTrv9AIEeKqRc0PTsSGpcO9ESNLc0e4GjALyWl37GFJhEhbDZr0gxuujX4PG9MaGQrfgg3oe2 fQ5WZk8I4kQGAr5ob++qHQUaif+nhpQCiZ0ARToKg5sBAemRd7rvOLS7lLdCQ5VdUCaZPWuOACui q7X5Y36lxiaPU/Lm9/6/YsO71m9v6KoVAv7iSnDNPrCO4CEdKxN3e3veZlol7Z17xFQaCO/dh+uM 35pTzZFgzJTiSB7VZq96YFHGAdzHScrSaoggciv0YlWWofyCw7apG47mxRfVkKUYpzohS42jz1t5 O6Lvsx/WF9hmvioUN4+m1XSOG4vOQ69ETjgO1uEdXU5NrFC+SjDpRn/50SWV/AUJISYGH4vrebJr gJfmFhb6ZmeKO0cY0n5XKoYvq2hUf9wN9xjsC68mIJNVdiQqvnX9RW66rs+hB1ZTULCTU5JGZh1d 9t9fjcsACcQIclOMAeZVjXW132UeENZbRc/KM5ur+4pY5oU8sbMg6560OYyNSeWyqh1TXYVi34aC 3clpET8Qn9IUr1Sf1cZNCtEM6L/sA9hs5ffKCLrtPXdDQ88BmfFQfBehvji+WtUjjwEt8PxEWIsG t/S39xBgBO+jZxg9z7tkTkrpcuOH8rmpqYwPdzrp295243OAzsVo38cPNiYL0G1aytuIV+ULQDd8 3tV2EcRYDgEPVf6r2rdxnq5+U0dXGdUdutYDXdqxAIeSBxvhTI1VVEWHwZmFsvaAhBupYHFVf4bO B08u94vS4g9E+mutdaJaLaPJhl5KcWaXherMuLJk+jdTPRr437C5bCBDe/1cJf/pCLMVjo/xum4z dgaOBbvDioCUd764yf9atSsK3FPwumS1Mh6ith0ITwAGkk8lKhdrA8QM1SwnAtfZ/Txm1dHk6Uv8 5V+0/nEKw/NNQL0p6frqQB4AR1se9rx/JPzZTDjPYBPtMwW8Xe+XFpvR0/kTgPQzx691ZJldXGm3 4+C4LDT4dieXtxCKzq8k+5nBMSin4iGmrwUz9AiyszbbiCS1OKoS2s7j0Qv6AsoaqQbtXvjFchWD e8qJDXkFBHMOOklivHQFYK9Qa3ra80u7svYa6w5YS7Wy2mSrrgo40FJFpF0BdeP6LgIK5CPickvZ MYyy/1MhUFMLvCHAtuRRPXdaQcLMPt2/ebA2/K/xkyb79lcXk8iY+n/WKwIsgymaAhcWv6nn6BTI UVlFmzQoaDLRkno1G4xFimqMb5wio9Ylz2KJVpG5wUZjFXj/BDJfx/qnzuZn2S0UV5H4dh1ZoOGn jCRZWdWy49Z+rgsd++45LxcaI0UbaAArcEI/7glGOWy9WaKmgIAXRKMa7/gbNI7pBpgcV2XVocZY YfhV0a6cB29+RG20OTk6Fv1Naw+dDyqZeXii9hX7P6wOrEq+4Yb8IW2V6oxQge4VGnYgfdn9AjdQ tcDgxLHS+xlZXlAbSd+ejL1hpgz8KfCdFbe5dDax2y+UfSMBd1z8MYDPhOEnb+ISjM7HcO27bdfP kVvJ5iflAoB+wGpcdsWsu4JGZe21OFVcCz+4XGmB75lcoGS8IJ9XpeCYDp4ZvRVlitJIO86O5+Xn vFz+Vq+41P67lwaCBZCNfElOZOR8ILiXx6u6zTNK59eAgGiscSmfA5ZKLomCTH2Qf2gphTvQ8bbG v2jDb/Ek15G37oJjDyDXbpDurNx5OXRbWORjvau6Jqt0ymzFPLcJTOQ2dkK3JeMVFTtGO8u1QRR2 uwNNeY44o6KC2omx1vFqFQsdD9Vh5En717WmRS2017JlmpocWaFWJp/uzGnOCIESpUDOBaeiXgl5 xTesPu/VEnY39PIxEm/fWg8HyxxVla7mMuPROP+MJGqHxiZHVMrre7uIzJknNUYno6sT/2dx5LO+ E2Qguf2gD1ocyg9o6UBBGg8Ji9xfEskAdrxbxMppmc5qbHcUQTn4nRJNHTyfcZjc9BN48Hz9/DVA /h/B4hwtVl5zAjx/EebhcpEMReca5vFO+Y3+4fK0VE97z9zCukkTIwic/sck/fhRejyLmQlSm/Lp esItoSW6CbhCWfpX6jUWwitqJlZO2E1gKLGCNViDEgS2DlaY/ebZ3kbWq3RtQnb5H0DdwFyS50iY 8o6JqCJZqPxNifnxvHAloXuXKbPPSuLqH/P4Wh6E6MI9XjjSVhOd/v278pS8Q8NnawSOxQk20O8S rG+lIRsWdNvrgdHHnvg3ld4UJ+8Y6t8VMkU1oc2+7NnsPF4nXSIwd/RIxvRhwbewXqd/89QapMC4 Jr/iLIAf4FGNdzfYBOIIxFR+XCyobywS8El86PwlrjTqmBT4QgacBqZYo1QL/NJppYL13Fg1Jj0s LVqjrvUYmVRf3LRzd9MwwNE+NCHldJRfyRSuQJrIw0lth6W0JecCsA0Ah50HdMj5Wg+o3OoVzxKI D8AqGiDS24Yt/lyD+wZFMk7tc9lRStgkBhJcDAnaewamHaIE1YCd8057AkFIDM0H9fJdggoDi/e7 j4VM0zMuKq01lI3lCfEt9XJFjzru0g+F3ooMdHOGqGEYS/Zx7vuhS0sxI/w4QmYx920JBM7iI/sM 7NjX3fPJm5LoBCwrJ1LE7d+wxfWAIjmGKq15AosBumDXQdXADccP7o7laCnaZnooOt8ng9PUYKjB LLcJswfMvUnq4xUlNB2QugeQk5wMMUnEZlg3nSM6yvmYJ6gunGbTXegSWEyuDwHZB6G5BtzGGVc/ +lCHmCkoe2ieo4Jl0RP5p1zOXcToc4cqY5OHPbnqFq/Nvu1Ffp+F/YbdfhQc/8r8yablOHybgfgH JuiiIJWbjvbsw+rfIjhUyR6LbudX9ZsE3/hh8MmseslIJI6qxyq73vgAXZaD+fv0nUmHTWaFYwkE 7finrQD9hnohe+FeXiuWyw9FUfi0gVLuY967TyGtmeIsLH4AjDPe4j1BYBSybZ0Z+E+l/UcllILB UcuWl4nCiR+vyYUbIXOcBUVlMhZGNINxk/7esq4JgMxDisBgoFE/1yr1PTypp2BNWg0sJ0wcNsX2 wKnE8xP3piSbNbcw8i47Dz57ukpXhSh9f+i8Ntjoe60KiG0h5gLEKlpBVMjO3T7jCGkKiE5ovjI4 1tkPkSQXobR8ZhJk1YBb35Xat4a3Yd9mYXJid0eMKu6I5ispMxnuNabQnMAZGewJzov3hwHJl0aL ZKdfzMvPqd8E2cqNCzQRjYNPlHb8CTHWTUIapbxAV+tINX73UmzIJgegddXokyg3P6GmTEUbEeVk 0CMcOYWI5I0Muu4PNaoZuY49YEWExRaaPX3LI3qaMJrZqW09Rrc2EUTWwhcB0Ac7HdPOr4tjxls0 61V6CltnlTLJ1MM/15kfphjQQLkbM88ceBgUZbg6SFzA18hI547RYDurrZKX9VOh2Ovo30juJy28 7kL7lXHoKjrckVuIZwhjjzKIFIjEWyOBaevavWbFP1AxGmtTECFlg52PrTRae1JJB3WeH/JWcL46 ApnW9IlcvddzjGrKz3heofRMcfP2b6TEqUdga+mce7R4CGIVeeG1tdNiQ27abmM4hQj/2pl0y4vL omaxUjFaetHfI7Q/dQIMdMjjOAyDqNMF7eOSZEmHpy69JE6ZTLsqeq3r3ObFnNzF3fDC5/glHwB1 WZGfXglzbul3UbpuMbVlm1zz1xgSlrOrZBm17zVtMlnID8VBtp7kIC/kbjLpuASy5d73pac7AMzr O0BHq0ETJrelKvCA8d1VHYBj2rNblqgQRojZOupgmHEyGfxz9vU4kMrsyfs1nDNdOObmXBFHepLe P2OK9roYvgoDoYUwR75fwg5rMcot6L6SgQkGwP+QoRTi4FGbZdGSnwNHA0zmDc0ZsFu9sxQoeZEG vp+Y+rTTCQBp25uv8usroOGAMaaQSgzFVHMA5YBRIoizzAjFs7sTohE4Ws0Ltng/NqRDn4OKtVsO 36oErSJ8Zqa05Xi7gXMqzjuFV191ncpcQW5q4d08aDmMzL/+35ic+6MGK5k/1o6DCDE0Q+rPTOwA b3TWUfSGDhOx0VJf/beaTHR3f8N3CIRmbJ5FvqY2qDU4tsDMQq0CUpsmCJ3rB34PJNExF7CWE0vs vlLX/2JqxlOq7A4HJoOORT3Pc6IWXNBe2qDmkK6+OsbYyvNRlx003l2ItI9X7Kiyg/JiaC2+YFmE ZIncqHzj3vcvyliJbcRDXHvCBZHikCYuFwDI4rR6oHEOpRA4rBWG3M76pxe71IIHVhR1Ijh0h11V IAnEbh+Dmgpz1eM3sUmLFhU4eqnbnVH7hUuVg966R+kNQ/galK0te+ApFOCwBsHd1ugLqt6/4Y5h awsOVSiUlteHFaKgwIB+T3lKak/Ox3NOn0yRztqDpqeTP9+AozgTzNVh05V1aGeFLixKDFoK3Nma gWeMhP5kPre2IKHlWUTrh51R2lN5GUeaPHtAJqvulgHzn78czDuryOi1BGV+q9k+A8nLBqItgAxB 1qrG8p9nxqa4j2OPMbm9LyjmWorujbAIjpe5ODyFZe6kTwYrJ1+6iZWnliTkokt/H3GjQHLF+r9g /eH+FszU+SZKTYRIk1RFvW0n1qdApApXVPfSMyQ42IITT+k5akWQtg15w/B/hTyeB07RnKBu8sis Uwf/3xM9UkxcMNXEr2Zr2WnC4hmeR8VrxpoYEMGsUyzK63B72JNuyZ6HTuFrBVitbeyCwggyQkQv HHOJWMIYqPm1M/OpijpvLuhW2J0brMjVjNKxYQwJGEAKOKSn19Ie7l8YCUglodHOJ9M8S4d9DBkc HkfRwljCzJ6pRKIkGpxROx2NUSeyOlBmrfMrkT8UK5TtBlhvy0OPmN69pgi8TXQvF2pbuL9HQ/2L QL4c7WxuF02s22oM1CMimsHkP7qGYsNUPpCZoQq7Zk36lHI0164gpNnPuYE3JWoz6Cch1snCNMYn +HIq51/5xNhdaGb4rt8n4PTF7pGSDTJGe5OX0jk7YCC20hvzLo9vxr/E7k7egPO2B4jIaRph6Dum WPXaOH0XZDp5E6KcFOHRn46RAR8FEDeBygj2RLrNaLsHrKexHDEWrKthsDcwPFURQsn67+JUkc6c Xhd6dxUE5MMSmrjiPSIBJACEw3UiKoYbI/fP6LEzDgoybQe6T0jJxkWmu2PYIN74sWMxbQ2VJl/J Xn8o8B67yrUwwInlLqzbkDl4MtbBvhQOeUMF/QzHmdSDuVXgHwe88Hf68oOyMzjtQCUpJg3PTyWW rGTp2E31fmIYJnAAk6Av0Eyy75AfJrJurtSzon8IkflYbsg1F2nVivSsnnDo5RMD2BQ2B8xwxR3/ ngd+YWX4QAK7xQoKCBcAtV1rPLOTkFWps79jh0JL59LvXTIvztFxG5YeHovuyet35RFfy1nbHUd+ sWOnZMzdCFuHKD3dpBz1jndvM1lyY/Wi/o4uZ23c+2+kuWy38RdNBwR26JJKVWxHy05UgZwnmSJ4 qOEgupCHboET9hJp8HfGix1n/GVBqsmcwEPfPweejJDV4UR/Ww+3PWBgDN3TxgsQGS3w77FK4+fA kvbLQ3pEYr+97aeqKoJPztqW99RI06sec1OBGfjjscMAjQZO/jBE4xBYIKDiopiT+NUO8jlB0n/q nLt2s610x0ir4ZfpAyNQ8Y3HVVmZskTBzpRol/9ovJN/jAActwTF5WjzwGrcvK4h4+DgPumzRW5J 9sNH5+VRfWOe1a4Xb/PDMGTfLKXappvr6cD7ya/CuvH55DgzFdgAjb9t/gOIy4d5vEagAyfMUPAT UgpDbufq9sWfRlslM+KVtoV4EhPg9ecPoJXEwSAXfPYm4xl6tNEF8ccVq5a7BPYpqmpNnLPBBFwc 8sEdYYYXBfhexnzmFmCxM5Z2V4x1A2yZSeV3NE7bSqOzWYjn2VYqzdrV77SXBLLzAuScZSbC1gHP Ad3cu+j73gYKDoX9OyWF9ZWk3iOWkvEziljiJ0T5B+Z5G2kZAhGhHgiR8qW0T0kJ9f545psAX32g VPa4tKOclHV3aQHztBair8va0RYsghu6QFPx2tLh/SlE5i4IulRgX0tn3l6Z32HbRGlo5IZK2yE/ Efd23J0Kx28gbztqX+VmKTsSNspsl8a9/qaPGVXZrd6gE7KdJG6ZP2pCbFEXcLJ50cm/no1RSIA7 L1rziddej2rWWE7FVzn7108AgTJVauhVUcHayYU65p5iplkLchqkzxEB/lhVGU8jwPybR6cW5Gzz pPFi5sSYNKomTmtsW+BKXsUCUukCvcZdju+L0ZtXCRRg9xbFk+2EmXv0us6F26hXe90x+l4Kv/fb H/JCkxo8r4eiM9EsG+dUQ8h1X/4vClCcjhJhiecZXrsshwbQpKps2QeErrndRTVnmPQam8fqaMxL QGe5Ac9IrU+vXB56SDnOSA24c0o0pqzksaw9wsvKtDCVxvXM8S9Ob7ukJ2h34m/WK9qeMFtreNds Okk6JvTzE/saRAEk1wtoeTO65yMxbKPo/06Ksr4myVM541UEKwbSzaEw+dvtrhaoarIsxXzQLz6U IfAy2fHtaW6LyBz1UY8lDEAoneyaxOhXgitY8e/n3phlN0yaJl4FDkBGTswAPoX7Lb23aT/Z9pBk DKQhCbxfWCNShdk5iV+n5HrxhmPQlUc6/xR4vDaiKsOk6ZeNCZaVYbsDuNVKfaWFWyXxo/s+MimU RiNbc7leBpHDRut0kpeMuAHihUcndP3tjZrfuh5Q4p5CA3OHltJtaJCmti1tBtstNye2VQ1+nHNV 94uA4ME0PqUMOTAniFxhZRwRDmbrPodRu0zaOVuVcrMY0zEyEKr3dNkfb6aeSs+WL3I1FBIxZbYN gjaIl/hyJ4+G7kC1jWF7K6iugGBazRcg5cIF9swbO++JCz88TqumI8F4+Pq9PhaRaJxO4MEFTREs 3DlkkrH8ToBc0dBReSxXuOqe2yk9l6L7+P5Raasb+U82wmyDgbVKsgFUDEmnFrZEqOsRfzRSWclV 3MFpa+SNoBRITFHS442V4b+2aZTrPLi3b0KhfS0xdhI+ptaKnhPxxNE+v9f6Qjbvzvy3DFFkd/jL qEVxCi1NkGPQCIfwf08ij0TiuV6HoCJWIrPQaf9CPW3IED2qduKJJGhndU6vH6HwT0Mjmv7XaO1c HoW6vhzoaWPZahje4fizIhAj4xUE0QV95W8PY3xljfv6XXC2pIeIFJ/dkCIkPjMfkzOuIov1XWfi b+DLEtMaa6+9lJBUsSgh7qHQ7Cdd7CbphkfQfbJGhnhRvZH8zkgwfWxSXA8FyXh0gZk1IqqxzZoP ps+Yy6p20kHPwkmNi35b3pSHYpzSuR4kIL3f0FQLBW/3wRKOv2QII/uA42rwNS6lo+k56NN9F5Pt Q4DsXd30lssivaHf7FiY8k5aJ2sCOigv98R2ZS6TwdAG7vlkYt5nSZGEmwejl2RA1FFNcFktyfUa ixpElVCwMtHzlLFw2Jz5ZQLSyhTwr5SX/25tUxtCL7mVmR3MIA78rlUuDuRhZPgVMp/bqbXLRZs3 9htqm6fkdqqJ29cj+N3x+79Ku7a1UsqDWDQjqscgj3Sf4rxJEy7D0m0N9kNcCvpMH+jAu4nFkyzt 0yMzGW/smYQ3M1GehHK5pb4Ikr7yhh3I+X5rdtDgL2e9XpcfEJKx5zk5XDzo/dk6oW7XYG4FTKII ygTXohqko28jSNbyK+T8X5mUj0AeZA7EjxWKa11NfPUoOGO0xdDqs8uMmBiPQdQfXZ05nY2C5soc OoN/AyMHM60jD/uzLJM2YzBZiobs+IGShXajeaeNA9LD2Mccv0wemP3OBjuJLhXhPfgAtAmdpTXw 1R595rdQtvG+KvdcJigRRnPaxGQLAOfxI+HWmjE5bIdKBalZ0lP1ofHyMTJGux604xx6KaewbFbp cBfqStJA4yqbyqy2jnz77xzH71G9tXopieUkhyvYBqR6gODfJaXXro1hotX+E+0zOupX2By8QnmB duow9GvRb1zJjXSzoYFAcuTbqMd84dknGuM+VR9zPzm9UPEkmlN0FZxByzKTVflfOV0eTwv0CZXV f6fJ7fNstBOVWt8cZZ3mdW8hxsas0ZG27dEaWehdaXAP/ohuKmivx8SQGi+uw3UaB5s5ilBuHDlO +qQOTNwK4owV3bH2S1NxPOvvq81wSCoy4CMdl+RbKEzBz3cbDl132pleyglHw/84+lLLD2Bgj3hi Tclrz9L380IWJfqYQ2Ecq+oIpNCMS8qJlFDkHmKvKqs8Ygk2C7POuC5kaKZ/hiegFipL8yIVfLcO VNLQnmw/HT3RwIJsvQI0i4F3dOD/J1UhgZ62pkMNoQgpTNhRICb9kuXKo9sOGgwxnuO9h/ZBvBzD BQMFtQW4oj4X3y8lFHfuDehtaEGp9ZZTYR3WO9rJ4+xCNKUFQwqcocRtEKHVxawVftl8x8Rg0E7B gYk49h6NMlHsrOBLFzgftI+YU6BUc9aXtpHAHf7jSz9VSsvtqIbUTvSHf/kdVdoN5t+fKXrLTe+o yT2M9T3te/Hn3llIj0+qZxfPsgu+P2kwPCsiGvjYN5hubC8qH35PcBu/7oT558+t8a4//5+yE2AJ tkRyDsLqH05j7Erp5O7WGYW9fTvA1y2onkit8NrbtVQe3NPWGbkhzqmQQTGCTka4LK/q59nwnXif dgytCwAvY/+4ZcxKOWH7YN5gKcknQF57AW2P9j2CD66RAQVwQiDAd0Eoyrpl7mzxFEpYBgUlULgp EBH9F0QCjoWJooCdbTDk/GNf0gfxS63F/Qt525v8z1yQiaDqMrzu5d9dHlgJYNs82VoosvKwladh SNp8zVyPG7a+HC3VhSrrEOVmZec/EpeFx8quYpX9RuH1lNieUY4eva7L7T10zSy8bXuH+hZ5FU64 VEn3fduQbI+tITewEVQ92Ql2QA8k8D8lSLX1yfrek3lwrZTjpysj++GHSbFt8GNuvuXbM6yuKHJ1 B6lTjj4d9a+lwb7S5p1vWJBRa7NWzX39ukK5/yf97pH/+AIHnhW1k5ixVWX7L7FS8qWJa0Nkbzgo 55r6WtmNUFfUz+KLkl8/+VLHvzuRcAPlOOeZfAZtcxrhYi7UyyB1GoXMjW4ZL3eKtNHXYtvNgZmO 1NDKHkNW47W9+Bay+M+3s24wOr/qLwFkWIPI+wQ/ywvcZEJIXJ5iA6G2an2dvdafn68DeUMW7Ptm nXkR+d8k38yF0muiLPiYauHy1jRIdv7anxJAda3Nx5vf7deJ2+liq9ZzB383zZrBjBArzmv9bXLK rCt2bePJ/WKa9JQeDN/wRzuV8YhgpitGGu7YpNA9XyBScvzr8UOE7Qy9C46e1p8QPA11d8qCC4of WPLUws3XuiXClZdpOuDrgtJ8Oyo/iV2wpvJyVouHhj4dp6H+7D3PsD0sRnJkCNNjGkkcovf37H1n 9aRM4gTGXTwTUFhaMyvxJy59m7m1Qy6HbUyp98yvi0SKX2uRHL6l5E6WrEb8r3n/xFKOjHeBAipv 4V728u/D2MnsO3/0n9sRmFSfYZye0quv/Jar2kk0iOEun0dUEYLaqiMcF1/t7Ji8c+YtEir+IBCA eHCFoi8OuOnNrXG68ETAZDxDqTP/5hUJCsANR2BXLVvq/nocpJpfvWGeyGidA+5JGfldndYJhUhH ES4R1d07ojLYN6mvYNvo3GkcMYiwqNtNii7Hh7rSNRgazGfJydCnUtgoSVhe8pqIQTA7FqA5MQKy epzpK366TDZ8en/iGYYl9Y8AZOa8Uc0jZkeF1DIoN8nozhPh2ugR8lWrVLNh3AmkdXEUI0MtwY11 SfYVHghFYj5Ce2d4n8836/q4LQEYo+lGchzfBa9J2XsO/BA4DBU3yEHnWlZEKBnyQpKnKolYMUTB KJX4qWoAlaS8VWTl4IFJlVJm4w2E+g5SaPIv85gFuFW2N+/d/NaNYSpBfwkHbu846Ri3jJIHcrc3 3Y3arE2XeTEpZ8fUBayl683gYnPz63mWsEShkhS2p+VrkopvfrRGO2oscn20U16GMPPYsd7s94al flvU6EBZ9/BSF++UjEpQVF4n51TF2n0/ufFO9BWFWvCQSjPiF7zLGPS91JVk/rHlRCoiXdMPTyjB c5DaZ9/sPnJgXGUkaCK4/EXOcKSdxPoo5tvcT9hZHdRdHFaix2veGUBdiGvkgZaOkjez4gtwZFZV KwsL20fRxjbKXtGNl2U18/BjSH6LHlq+VL6PdEuvfKX4XWI/zrFz1VdY7cmXUtP0w2Zzb3lDaUk1 ZNUtpH7gxlCPNs3QHMpEauOFjNlwSEXIZwcFB5U1lOev4FOyOCb0eS/SYvyR4Mlv/E+hkaw8GbsX boQUduMgiTCXAiSCbkRkN8h6NZ/FoJggsR8qbOVtatvf/5GKI4BaRSyiSGhX1V+KszgGRt3Oqx2M cNEz2n35xP2lNuUDbwpvIBlr7eJ5nlRF7ndaB/bfzHBWuiP5m7fMakRcs5xfDoVISJTlVgUpCgI/ ZHmPWBo+OFtOpq3AXAOAClPXp6fdWqAPzWMmYRAyS4uyKjJqb81gcjAJxEspjq0/v0JAV36IYhGd pRsppfi+NBHk/+jD5It/+HMLY9HuRzj5U7FCLeR/5uvWIvXwtxWihrVEz4m/Lj6uIXSrTxzAin9/ zSULGeoUL5ZJ65hGbvGx3xEMKNR/AXC/jzhIj50nE7R+SpXxjqCQM2kef54nMr1zJWzo4vVIj4t6 jo3zFKmdDplXI8YGhvZTbwoNOp7Vk2YtYVVVNCsvswPiu8KeMaM5ayjLRY9Ekyr+QdSlHwVCM7FJ KU2XST+q9hiJEYRsPmZRA25Y18DPeLj0V00qgB0+E2zlUB4rBcNJOrY5zT7E9bL9oXjNCvTUYVP9 Fuyjbu5CPZhqN3yJw6guS8/1TlDRLIqPyufLf/ZcYhFlY2YSw7jWvCnpDMrAAoPRwopgB+1cK4oG io282ZdG4XYB9fhzeeduNcHnEdtd2sIwRnQZDMvpNPV2u4T6c2qW7amwXCeVjHZ3Z1gs9aIkFvqo fVMOTPKaQ/iq1DLi47tNtL+SGgyFdQiCatN5ozM8vs55QlxN+AUtkUwM3AWS7B1tSAhspW7H1ylE aWryK5A4tg0Q7OXue4omknnrRU6eRb4GFiQ7mWvbBv0eIXMhcfvoje+j7VZkL1XXZ6+Kjygg4wDU JwnSHR3rGeUMAKYeaLhJU2Kteg7wiimdTNDCUg6zIearxoQ3kiawPD2tubI58NDusyTV11bR61Hn 68ZwJXSBlH94kzYBoE9v7T1dtaHU/Q5VafllpoyfxjJgyKq4rFcHufIPOednbrAYGvPLVInouxQx lkpbMxeiVMIDYpEm5rLHB9lyQFKyiMizW//bw/FTyVDx3a0Bq9kR+BMaGQQlrhePqXdCbX/lBPk/ +WXfoq7mQIiZ9AtBWq5+OM0V5EppxrqfHYBtdUdDtwyDGYlBPK0ls7EE7jvFZOOfHOWIcabMpuAB W0VSx5Xibd8FZT8f9p3Hu2AlooJS4TSfBjCrQOMDXydy+xzzkR0Dr82hhYnJM0935zqC3BctPGvJ TSRUO7j2nsUqMy2zDoXAebErgeYyRnUnqy2ayQmo5Ym7icfiai+mS8I9EiPl7BUbEuGPCV7tsg2R ME6+A54aZRtqCGeoQtJO76raBngw6uwiD0RepNmRcusfBp2MkQOSGvux6tZyHOXAfdhreN5oO+gS Ck3JXTbZ9icH+vc1bFPVG6pBzSOhIrR3/tbt5kihg4qDVruLG09yn9t3w8EVxdLooon5XnWXYOsw DO9Ciijps+IQ++KZOucG3GibFEyBe1nGOxROIohV0U17zRu4JNXpfTslBVl9ac567jmfsZwbH4H8 SLA0FMRShOPbK9aGFNEn88YpLJy4jPqecKAQpVLkuGPN4EQcN9KUPp3k8TfQoSYejEJYxCOOzKrq 4WYTCSbyKK6Ekq7VV6z3VZNivQt689VdOGrQc+v3Jd5T/S+ch/6i7wKGYwCNsGirnG/belKB8okO pSOjGWRncdP52GgT+fZMBnbfpucW/fuXLnSVtZV8AiKO976Q/jk0ISzBC53lAf4oTjhajIkEMXNA NOj2z4MbOePELY2RBdYqpaFKmV6RXXzTZ16CEqLfo6jjOitT5xJ1nRBl6CJajozhK2smNt2Y+7Bw fop0nX7uacECjqXuW2yuKXpmTmcEEAi/e9+4A7BX/W0ExkazKykiSeWuG5rX789oVcSwx5mhcGby M6w74owDeJ4SMoObdxfQenUdNbob+lvF+/VeIHMy9CIMhhLTw4F3ZKdR2ru62epfHwvs00P71w9a My0McAja/UePCEnyMpYSMTDsgN60PC2sg5NlPlnmWaOUi6Hl0kIxABmQgiTEDWX6hXjXrdwGMYcu y32wLvZUaPOUv0cVjH/sKONbgPiy9HGpC+soUzHb3QhaNx9wX45HogF9jRa10Es7qvrISjmcI+7c GKDEYIBo/Rvy4+139ZooFKPBFYLehI3tTSLSqiSRFGDQCl5qte+LNYz+R45p5f/4P8wPcON496mu LMX0K4ZLpI4LOsX1DRhO5HV1eKDLDB4yRzggp0QcaV6cYXQynjrC4pD8P7myBwETIOLHIafQ78cJ tT08nmQiSQhOaj02xCCht968+UvOigK6pn1N/EBhg83NQB2B1xlv+B5VtdLHpV5Nd6h2qVRh0fJA LNBekKbpwcZJksiDQTwkKpTP/ffdry2eJSqBfmeGEKYrlvmBT+kvSjFJRuAQHRPA8vyx9B285dVs BR41M22CCYH6MBxbXmH8NJ1H0mxqWyIp5Z/T9Cot6yXDxZJTfQD+4akGQC6GCnQj1hbbFqi/nlc5 VFshrQJvYVAf7fv5iwh58s+zpJYq2T/3J1jvZrl/mHR64AhfnxhK+g3VQaXkoIpTp5kUK56HhyYc gAPLfAeE4UpiTRTISVcM5MYu1f48FQi3O3sRA1ZNRHfnvJrmMKgvFnnMkZ0pVnK2C9XTsFbc6S5k b9uYd8t65FZGkBXCmjWVek8tcoc3Ej7CrfJK/+ZQvShBCD2eFzYB3PrbazPO5QPaU7LlWRsKsRdy U6gHqjbnroxkuX6a3mg73oTIdh6OnfxVaTMqomWnWvlPBynUnKyozcvoa96RnmVCsoDkyPWnoEx9 2Cwg7odP4JF0sYbH9TwSERPNoBVG4Shk6pxae6i8er6Fxh2vBnAxmo1hHSGEx5jLYvFSMblGY/wz axI9Ln747rldLyjQhpdBdpNyjyVMR9MSF3dKDpJpyh4szK0igyO16v8ZCxTcd/GNkQX7p0hf6PMZ fbbCYPgxETISifEqBKNpjBaj73xFt5ueUM93nsxnJ6SkJRVD+BKXlYcq1FsxULOYqpOdsx61+liX +mh/CJntO4NqrDQrJlf6DcD4Oa5p6VNlyhkek0VwBXRS+lznxoIR2+1W1dUXv1okyZjmdJwDeh2t 1XIBf8UBPbD5xgGIgiaNNWZUyyJvUF53m6gnE8wxBGD7uxudbgonh4G9m5QKQqn11LKZS8CJ1BAn 0W3leS8aehQWzN87iLy9edBVHdFwIZpy7TkHRUXLa7HngDOVm81xtQnzDcl7GbY9Q5SWp25UVSNy TBAd5VArGhFYtljQpPLf7KEJwMkbdhjcns+RAK/MzAdL3GUuzW8cjKBwZCOdXHACmWeFRajPnqic 9qLWQfywbAwAI6vOtYBbf6hxufWiuVxvRRNuG1TpEDDtTn6iQM/42UOBhQ+qBZRR2m0yeNjWiOXV W5XxnzQ0iC2cPqxdXIpy6EjNjx7zw85X1g5mWAQE3LPdffG31m579/XD+glqRMZSCDM2OqqGBLaG FZWeX6cLb3mi3y+ZkPtC0NzrXEOetckP1cISRKLCNlJsIs6Bv7+wsMhJtSI4Joasp+Wc1UA0um0L 8/dyrQxM7qJUw3kTlTPOkMjlznxs2RhudcefROAnADclqAT1Z1/p4+9N6MHKja7LueWRslENb1hZ L9do/r3DzzFSqr1AP3pWIWju2Qv3LZDTb9impd/B1ZeeV58iZD1oRve9YT4HTOW7bI8MR7fHO2UY RjouoooajNxxSLX0i+kXyte74FMHOPccn3D5azEMwv69nCm/sDSHnIc+CCKAsYXVFC1OCVOnH6vI oelm2w7Qf76ap2U+6C5jBs8VbAYl/Ef1gL7cdIC7DCRaeKeKaYa80eHGgIVjxv+j8DXVubCS35Je CpobcvvSidc6ceX9yYLRZYgn0NgRw7BRs8+b79tYXRHtcMWjtfnOPi21JFViWSwu6GOsQLmwlNG4 /Nv7RyEZGJOBNhCS487mu0mIFVGKApFcRwDcHP2OGoKjWxMk6q6H6RBUh+o8Y4FKYtCZQ3dhYWxH HNGZVJLPi8Isez6Ahoz+CHf8/Psh+ZfRHxuOBmDmauXqrfX0mVZIDJiynHDB5YejLEFOBiyQ7/2p gkg5fyQwg1pN5jEo7WE8eFQI08gDZQg1i/eZTfoO/DO4OEq1srWQOcgntDt/W5VY2MMsuceQwrTj wbQbmjlJvf3iZjWK1b9EY839/cS02vmr2WTC7Cf81o7EkoAN0LuOz7cATTJAmKbJ6ZDzPhYJfR1T u3jPK/Iq/SZmKoPNjcUoDj6Xwwd9uVoN/q7w7XRgqhKQjc6QiCOq+SPYUeJYTXQ174VijdTf22UP sZ6hNxlw27rNXNedbdaOlcBrrQODbCJEFVFRGUsAGif9oWFy4HijRGhplyyfP1opnIBR0/CzX/VL 6eEGp93lN9EYGr8fT+gf5Ru7r8uEzTITtaNF/XIf4lmgQB0BQwdbd7eXmQ6QhmFUmvp3JQ/ajFGH AIWuwExTlxwDPLtW9h2/DZaqCPii8tpdnh4R10SOAomsusu38TkdLi3UFn38mYHyYymn7VRc/wA+ 19XQ/c0XPU6evaYPUN/E/JsMDcAkbEtG4yW25o1tjSnsjZWlNkK6CobYF70hKsSldTEUJ0wadre6 sV63zXKkQsOx/VdOZZeU+/VV3Oz3jDKm1OF0WMPR9zISCxcQspbL4wXvatDewir2xcuZb/+kurvI V3xeR2h4FeGr+Xe5+AricfHo1ErIES2JvlyqI78iol1fiIULQ7hZl6jlNhjhIqfal70xH1ct23Yb Qss5grHQ1G7HajO1ICVydJC+XbuP05JpwR2VQoODA1cq67RAChlPxlGJOx8sAd0e1LM/czFSPgAS Aq8zEdIH7Gv/lXaD9Z8ySW6UDbLkNszqduqcA6Xf9JFTi//swD18cRL4os/dWvNfonMfFmOXWroI 5dWfM4JCl9o3VXoMHQgUceHaARNuUl7AMjGiocJLOSLsEYXtVSuOCzo8uW4DpVhPKEF2SvwkpScE h6YPgOzK0wotWBl547YmnAZDUqxaXpFo/L++ftqsqQbyF28oaoFRJmqVXvt1znZhe7VvHv52RR+S vhtgIIMXTEAsbzhmSruNd9Sz6AlDBs/CrjVyEvtUb4T9ZlCne6RlYk3oIAngcW9WjMw4WIq2CY8m cu+Spj25czq6Q/SZfa8jDqj25qUVlxLlsedMUZLplHr6rQZGGUUaVTCD/C3SLX9NKbbpLkUJ6Wfu SHWr1Q7C+PasBaiJzZRjot3SQifcw3buwyqp6egxaiBZfzSo43DJdHGITQRaHVYbfqlgLmogJUME 7jEuRkz7qkAHFn8oTjubhIGV+g8SzEXAzBd4dfpPeWVHXyxcGgUaxb79ZpXbh9L5spOLq4ziISU9 BRmb6OdD0G8PGc0aMTsdwxyl84lofsqdqhukIHxE9tNyuqEguDePKjZa7QNgn8J4XZ6e86mH0Oxx KwgPmhMpZgF0cVEW60pSJvsYFhW5y1BnP7/SSiEkn4QW5W3GqNKjBYTtCQQJ0D4oVzQF6OOehb4a C2h9wIF8vssKHTlcAUFptTuUS27qH/IHB1aU72ZVysaQeYD5GQKoX5CrTV2GihpyyxJ5jpmKVir7 6p6DBVlc+Wi5gHP53I2UfxHPjZIxVOCkpN6nx1k6LgYL5u/CUxdkLG0t7UZZH1r9u3QM1N/+66GT 6LfkH2JXc4cjdx0adsZzNWpOoZjk6DURDE9Z77VN4GDXKLO511Yo1tFhn4g2ehcwOb2bGw5zhk/e SUBOdQzuWf/jqHczvsLKM1tY7zrsm2lVnmuKXF1kNO0XY+o8wvrJvQfEzxiBcqoXe7XepAVTgEqj BB38sNhin5o+ckzP3gPwGO60++XM7hpePJwaIf0FdARrTswRPBeMnYjnIOobHRjcIRYPA4mA3G7T 3xTLWZVSDmWrg7lVbft+cTCIH4+qQx1I1LjZy5rmsRirubVzT47x+oTdALlHVAFKjcHgeMQt1f+/ dlN/QfO421xe1/mWwTywM9iy9pJLb2WNLiAtpkxE4rcfC4p/jZNnGq6tB52rX3AHeqFYK6zGtDE7 DuRszpxUTuXz7wjegOVuEhc4zhxro+t7XLJiqbBZvEofgxRekE55fn+aWcV7BHakLKtRpXMy31Bc Lou901PFaVAndnB1axNSFk7nWX/TkO+2ya7LRdSKCaasDZiMk3rZH4z2OvT6UIjJCsjMxCk32w+G nMmHeD1RPPXel4AOpFq/FERb2wjZtaI0TQjH+JLusCAOB0Yb2iUtnX/5Y1ymjlZ85WLXGoK6ZATo r3LLARvlVUU+sx2lRbe9KdB5r8USIhzxd9W0NHY5P0bk7FIPIqvq5stGGBTyHZYzjIIzrsGO0+HL w5P3hCtBrUBNjAVQXHmlWcpaRYJqIF0j6iXBNZ46WIdV0lIT5L3wknknLjoPFCz0hUUKbvVrwFHr 9m3RXBJyWIIqASNtqPE8gtUnXIRZQYFR3L0FTbWjyIgPsI4I8hIxQZS71ziT4u+vEZgo+QBB39Ol UjCAKs0JgcZwM9VjHtabEQzmhoINzsZjfbcQX7jofDU6E9n0JTniD1xwIVogDKOBfpIiXRMBh1fx PrXnAzbHv7WN2DRzt/bbrx5Cptce4TjrhvoojXGpNNl7guZONc2Vq7PlYi+pk0XF/vv8xrwPXILK flaElJNsZ56ldzFxJkHaQhNHLO356HDYB5xpdSf0HvAkT0yTEA+P9YzH5g/0cDzIKQqca9AQS96F w2pzruriVhsC+EYT8aIKurhnve0wd/IyNJ0DP3AJ1EabcNpSy2gx/yYa0Lxm/DfhcJ2v70TwNLaP t3Ufxv7B4CcAc+HHRoQ207YsI7SxW7VMUMtWhHHiNekPhE71bYp6gq1rGzoUAcCS08ktvigSkDHc 12RQoCd/R/nlF973btvhK1VJhQ9GYBeeXcTUB+5JaE+xApF89gBlhh0akX83ZvvSfzE6kJzvC4cG Vr+Ap0IQ6TAoDfDF4CjriyaIq1lj2v8JNGDbJW2b1oDQ6ZQWA+ZXvQtV6Xi8VQZBTd53jZ35gbQm TbU0U/+RHL4zhRVbA1dLuWN3AF2MhYaTID1j3jxYvpmlPIAJ+aHfMbWi0A3z1p5qKDrEf16a23iN kb8bDv3Mg9AZ0vKqRL61JVqEPvRRqNrwA2OY+HdGMxAbIPPODF3NIA2BjTT+rnA/x7MVxqVFvxg7 mD5gIxxYA7SvwFdkQ5XHqdTahEYxcUxJBcNDGWvBC+Qwcq2mlKsUn78igGx4+bFn7gCE/mBT1ea1 2WgcgsSxMHmTaNITfvsZWQ632qTT9/rHhIWH+OVM3r89JFstclrRgvbjK0QSzb2du0FcRGbMAY83 gXa7DYngAje+iCyjD2k8nFX7alH02kfklqFGOjbFUb4xiGENxAHsHWuY+U2t0Znx7mu2suqKx0rE 573YdLbFk+dvj9lRRxnBQ6lZh0972W3FzJ2C5oDPvv+VL8jn+cAnBLXAUDqo37Z0123xveyNrral 9Bg3bQWVN895ppZIz18xMQINQhSaxmCSAeRRX62/erXZ/ZmHVilKkrAowb11/hvvnsZ9q4FU7yZh PZDgZ1SI6FxFrsz+MePhCbtFKgysudB9O97zojoQHdMkOMu2bDyXDY2OZhvkqmkANx5M61NXOE+K l3swW+36y5TI1NCCd3V8JtxQOa08rGPgxzLC1CmTGqHugceK1sRmMqRgG91HfAE2HPp61ZeC4cf5 7x3hUfmc0w6BGh1nN0tCTD86i3u2en1pAqilSP7OVJimU3SyKwrbTGw4MgYlgp3rIBzabNNAGzQ3 IwE2+iANEkDvQH33W1d0LzqLdho8pR4yYP28O6Ax+w2FEJUr9RKFbL1+7z/3qKDG9cbOLDbN9UZR HnqWfs/urApLVNERvqRfrRa8aq1oBRNynDDdbcgl1NWAVj+L3y5SIOIF/HH++z1fL7IjHJBxDHnl lttesCjfBDsH7L345BLzQS6p9XvM8mvqs2mb9ZWyP22Coorveh3OR1au32PY+j7m6J+nIoICJmmZ spDMvKQL2UKqPKcMP7ced+Y0sKr0hheXdhXKbg9mzwVHHbtBIvRugtnauI+cMS6aG61IFqh/Gpei U6oIQfftUI+4APx5iG/SwLXwwKQG1+KeLKBRxxtt+HdOTu2/qt3fYtqJzopeKf9KsRaCzoYQmGr6 uQAUManl8GzefQS/fBnfxvOFy0WKMH6+0ycQkcCdLQS5znXixwK3fq+s5mhM/mVeRfxDSlJImFrf KTOZsRc5gKzmV2duVwbTxkN8qErfKpdUwQGArza2/bXrR4nCXM5H6joWKK+h+YGuhMtHRfPxGlm+ bm2QZpq3Wk1vclchq+D8wwRzbed4Cu7v5K8oKjwZsd5GXYkNky5YaRI5GjtJiWZU47+XLHGUrrg8 gFSe6TNqsHy660QhisvJKvuHlFTdsSWI9H7JStznUo6vqP95r8wyAENLELXAf8LzsKocsoPFSXlZ vW5uBXCtPONwTIizpcVY1vrJGmRgOIXDR9f4pW8/c3phlybZJyYOzfEhYHmw6Qs1+lU1fGSQmGwX xocIU1htSzMouCpg6CBLcLNlEICgYYJWdQMOxszVxG6G7mh6XFbyrpLGjcb02+U91RkJ7F9S0kp6 I6xiPJpcKGwLwXXkvwUMlojuBoNkW/iekpoyqboewBin2dNFtCIizv8AErVQV3rvBbvr74qYVSsI oETpHwepoi+C6Ngu9zRCcDILuRnRwugQ1ysjwJHbVYtTZBOS4IUi8xARQJiqoqRavFLSnOfRJoRn qb3rUdXvsSbgMxqb2H3gL59YvLH/9I49Lso9ZYvJgEcYyVxtMiO8Uwlyq4IWe6XuBTySd3pF75Gq riEj8MTX180unvtKvmnPHFPXuNyiOk1pCfafVZ1p2Dbc6fibzD1JXDHO2jBhGUzXlOaZwt02+LOX lqcZlowqS7iMmafqVobhED+ff1J30SZ1Dh0jOw89yJS9SL968iek54W/cZ5h4fjlfqG/q/UjHcRa 5mOP4lOfemCHC3/RuJ93oD/oJZ/0L/AL6GGRIJDPghVq1HXSbXiu4aAdGkCjwvB3F2C+0Lv2Jdz0 YNJ4KtplcWfdNDnTGFR5wDVuZdIJLOZR7CQx5dI+kCfXLm9cHhSYVjEoZQs0fcKD5QZEZsZfOufl yWjH+28vVAj4w2Qwpbi4dwIVd5sOXaiw+ozem/vz5HrrJNhyEMjGwi7FIqS6V4Gd0cqvfmQ2weY9 2poUl9UVjaK5JfLonpyI0NmBfTfiWipXh9/dxJqSuUikAFJzWIIOfaO5io+AgKbZ20v1DlyX/83q WxWAsJuFl6rLpbTEzOToOqVdeEYUhSjkeh+d+rc3V0gaSec9cl6rvLNZ5DJt7CQiJ6rkbvj2WJ4Y 6Cs/GcpWha5KHeE3lS65dzKb39ZudITtUsyW6Ehw4FMGKp0G5pc8dxOjZBHpqUgooPirC2pBAvfw 9TmLr5iVZSSXJGk7r9PwA8uRmgyl/esuXU73/qRop9MwQ0tTBnbj7n7GDU04mqUgkCtDw6Mg4Qzl swot5fweUUbRKGgYWymLZeUduwXsZECiVItHKex0F9vK3qvgh0MFGPbxybw3hs7NUquS3+sU33f4 7fS2f3qmAyLwG+Z5OPZ/FulDlK3uO+J5dH9+C8xUTiLYrIW1/EbHjeHcD4TAJ0EWOad3v+L2r1TT rgrx2iLEJoRzk4MKzB9SHxrR/vUrQ7k+6zlbOvZ+WdTZDB4v75SfNqhQXPLanPcelXuTQ6GBShvp JxxnKI2VOB+G8lVDkc3BmPixzHzBqtKeqNagWU4rE8XRK347t17fzZZODtmWTAM1i4Nvy3TuifGq HVOTWIDLonlOaZGEEymAUoHIV6/XqmVl4/HVRGoHWdTMnlRYEsdEFAB7iQiKD3rACQXZ18eQVoug F78sY3Qht+eSWHREd8OEypt510IzJYCTkuLJtIN4wl6sDiAm3ulV8frYOQES9UZVXdd1h+brmR4R PI8voz9GQaii37pli0Bvy7Mw33FUkBN9aP2+p806+6B+uY4Ig2ljG8rd2X3mVgcQZZqCsc6dGjY+ UyRYf9GvvOpYIJB88SilGWlmioIaRND9rJ9amlakDGvp4nD3sY/FyHrRCLrHZkk5WTNwZjdLAuGo olUZM3SnA/DLFGSL+v1oJwi9WgK7oCil/z15olcVf+gux42cp0yCiClLV4bi5SR5nYME4EcfCeOs oWkxwG8M0IveO447jL1oexaHCCGtsXwbQ50pdNdFTtLQzXhSN27fGXJY5nqrlx7af5PTFQ/tE/GE nFXWpQuHuog+sh5CYceCsflFmYJhEMT7IEx0/HQtbYMzxDKmql7jpOtUqU73UpYZmlFmzB+L7UOg zz9YZddgP6LHj57sorTbD+AHhkT/QE7GmFyqtjGDNZkO3NBWJLAEjmkP5tmlDPBh6JMoHUt81HsX XZ9Km2hgtIdkh4A11kJFKe9WsSsRjLTTnxTJHHeIC14KvEzv4oL3SVitYrv/yCdUtSqThxUyXzQv WNweNmHcbnXNtMpxEucyhcmAM6QMiIA5ecfkF5uyK6VcCHRCDeOG+/o0UlD3ShoGjnTmJitK594t oiaUFFuDjhPUORahvczjRaoahWQ/5X8SRRoXwvUr+6Pn86KYBk1Dmv+iEAabWpcXLx5xQbcuBZsD nMvr41bhrCAPOCF/+0nb79LG+MmOeB2Y+zOjLH5uuEZpnRB8yliLfTv3Dc1Drde2ncIkkKjw/F3X K47u+TnGcYH/aMVJAekUXgK5vbTtszmwp/uKP8zcDsX3GRSZsQA5uxXhB7I0C8BUdBNev24f6vVM FsHPxnKLH+sySt1C7EmFcvTb3vSllf5xJVB3sf6PnDoP6q62R9qOKUMcwtKn7kawUjDrf1u/ztTV J9/KaoYNaD151elXza79wkbObPkLvfhIq0ApCPwLh0JNGnKF7oVkD5ogz3DGfEq1cUjr7TAogZgU twZeQoRBGCFZWXUpOgM0mkRorV7xv0ADFLOoymJaRGXVq8LUi+Nt4wZbdVDnnj8Y+VusSclzI4Nt Na4JSW54cTtjsD5+Wo5ghp466RBa4I99gaa0HYqvOsuLA4RjeMde1B4L/EMQ8ksZaucHnRuNQdZH 3bpIvJygYOvcbrF2VaqiOWvdqdSuaHPr9E5IrY3E0Cc9leu518VUz8E8DDMfW18CFeT3BIiAoWcw eEcBwspuUPN0lbUcywtIP2Z5+HDngoY3qjofKXTrim//lvJiy+5IwyBIKfl5wqAXDfRFNzZCeQph DXejNO7MaYt/qz6Cqjl6WRsGZqZRNaBQc/zexWR/5KEa9ibErtadi9w7e/Tq+biqoHGxlwBPgg2z ym3NXZuDnwnnlsStNk4/VzCF8+/VVDToz5N+Y6HI5QeW8+FWPmzQ8VxnyCx9ZyWe8S9zXADn0yzt bqky4pYZ8AzwFG1V09EZ2luxmj/+v7tts92FShxmGPhL2y7WzB7ih7hDESFA0ETtsAfemhAedIhw h2vqn4cOE67g5AHdpCkwnWOwEW87jKjDNAwIjPlM9tG2bAZDIvxPprWIaeZYqH0jeBzqvsoqKOV8 ATqLIXItNrXhOFVPiMovxW57HqQcQh3sbVYEpSCnECBketk5zPiURy3I+plfESiL08B3y6l1bnIe Nn+FhKiL6d9aQk3OZUyGU3MULX9d5LW9HhxVN3TuwLBKRN4TVbWniojhB+epgOu/2761y4SEmacf FKxaHXolc8qasZc45z1GNIi7BtyJnc7blTVbY8nfoXkasEYpyo7ZrDFcxVleayKkIgcZhqowi9wp oLOYYFZ9yuMIxv7zFH5M9ztx5Ui30sZra2GdDNFCRyWJcTn5a5gxeVfIqg127hEry3zKeZnQWG74 wr8msL9OpqrpBAHxSQQRXwPQvoRflKknf7wtcX5zQ71+DDv8EIiqS3ArHoaeDEFuD3ZYcKU23m1e si196TTx3hDxHHDbdZ3pUYxBGdk/4aefjRQC+igTeVOmDO6T6Y4JEvn6xxarwz1ubVR2VHy4U0Yd /+3LAe8ZsMmrpNmLs0skJsRJZdBBurTEi4+E9kBJBJTkE5CvesQXn+4Hd6MPZm4O6bll/qsgHt6/ q3ljKBf9Fy0wejABMzCix/LtUlpdK2oH88yvtXVajx6lgy8VI6eHQsAgegq6ptWu+VIeraftzbW7 qie0qPlBLJbWRqj0fp1gqgvcyuF5cMWIrV+1vcqpJ17XsUP38RC+d5cXP1oJO8tFNB9rVOqM4ITa 2Fa+2NKQnqeLGfu+zrntKGtm6QLXGbMeS/bhmex/bqTv1RmeFmW5G92k0jR6agXSBb1Pse33z82p V9nKYB7fAsj6PCiq4dBuzYtqzhA3TQojJ2+b59pvc1rqqr26QH1LP10qf7oIzEpqHRBSTljtI7YQ uvFUl0EfeeNiSnuQenxjeZGORP5BXDUJrNS1Ps9SMvoWK5pWe83fuG6ddZyRjm8+mmYHfpw9Sqqe iv0h+zPnW0M7KrS2vXpMi15ZeZQ3CTyIJr2/V99PvELn61fIGgpoEJSt/JWGLvkWweOZjobXsudV kWdjoKlnZCGfQT93lZaamZVhqECv5YXfrSJ4pnfBO6lWfcKq1kaal1i/h1Jx9ZGgdJs+4NbqiIZb mCNoWGvs0Q7BzE4TdJo33JsuMu7l/b/YC7/nWDtTaMJ/3vLfO7VAO2k7R8hkd+bSEt7nu7PQQBLM adRu/ABuoo/0SwX81xHjFKA8WhX/Nw5r1YTx4TNCqJ3yOQ7wyVayHznVgVucyqVIvNm7bSakQsnP 0E0/oQogBJ7tYwBmYArKNbWQWauuR8XepCLLoQMjntlNhrY449LDzbdJw4K6+VEzCKWZFixKQJnL gt3jCQ1AY6UFjKB4tAFJ8uyBn8OmZ2+c2i/lkonFmz10xi1YRicL8blCisZbWmfV7iMx/nxIKRwD 4/g6D5Hy6PFOVr3cMU6CtTQEooWD5ZoPhYLnjntCW7wS1KT3YfBLx8xSWGTNpjq3ayrFA3On5SP/ MuII2EjI0v4zdzdR80gW0gB+Xn1ctShv43bxD1qE02le9PPjvZFv9p+XdyG9+dQpvXDUOyGbDq+q 6XurmvcSJjQxs54hSA1ZyzFwDzekdejvXTqF/p8Ai8pOz0SyQ0KNKQtnDGF01W9sUHte1RQJ+7Yt +AkVusOAYfCUhTKzEvLr14Hkoe1YV4oYPBfhWBtreaIwTLhc9TXRDSMeJAIub2BOCIngm2z6s9QS s+GIhTCOJqrkP5WItwNIlXa8wh6TqbZZSMgMtI3HzLoa7vw3xsCBkX21sQo/gFdDnRMxhF1Dkd3w W+6RYQhaBAKWigd25cPPtATGe0KNmqs+0x42OnGzCggsiI/ZcjHhVOwUf4orTSaLI2JrrfcnomjP Lt0MqZbj6xauda3Uh2a5fCsHBB6KSvdc8CEof/KRHZUF4M6hrSJuUF/3DiuZHdXGrXtjLRt1oDLp 243UKYvyMxApYESbwAxuRM/jVYX8OFWHIhUcwhb0UrRqn3UQ6lzs31nleDi7fJ4m4/GrzUObxUhm l3WjliGFMsjKE1XMT13ZAiVTPG6aINGHPs41PW5hOM+zyoVPQYqVZyC7oLjBOa4/t1OgZP7Lk/o6 OKEbr+UpZZlWV8h8oQGIUPkVICQdJQfaaSVUP/yLYyb/zqhmQmH3SQdlgI7FWmHXxvBBn/O5Iixq 49VXU5IBpvlMEelOekVNU87xBKR91COd9tfRPN14uJsc8x2MPaQ/CqzyIVmERThyomlXJzWictmy 8cLRt3luRyckFlNbv69vBEnYCgEalFf2BW250ib+Gbw9e6MJJ6f+0AYGLh+frhKe3niDNFy2hqtn 60UXfeBElBKSaKT+T8HfgfsbjEJtMczZ2YzlseTheM9xbpSgNl8SVHdS0IcUqECbntIKPFWWs1TJ ZJeqkhRt1LEXh6MoJMPUs9+B+dUHAGfAVxZ8MviKKLGtMAr9trUKv+U0ykaPN8v5aZ9tUhi7sNYE 01bby//L5f/wNqAgWlVBYnDuCeSYJsb9aPgcDrBkuNImGddCB7JudUslMZZQPqoJ/Wun43rv3Nw9 4ZjMLr7JMPZZmDTztMSV/XcjH6RbTlc0yiHIqNrWf0QuMEcfT7/XP1xwgqLc6YJ/Uu5lLdwg5aVO 1WhfheV325jyl6ElRxdbav5XzTKRleI386HISwookImGO/gJZHJNYA784snn3hU1R9E0SXUGYFBR 8btu61nV079KSECA4FL+z+LTbTfEMes9B0WU3ihb8vw/YhAEs4tkjO6jO9724k6xaZxtTJxDN8me /oBsnn88NJ2MKPyq5B5V/nLd3EwYWEDOJrntB/pmRsk8eHghetkLlnpz6KSmuWBHgVxHH62mxJv7 M3E0dUP9a34HJErqBH0ngcxSOEBnPiZuJiZAiSuJ1g1m4PmaptYJbh8icRaYqY4Ey6VYad5DxGvF jwDSYFTnQwsILtgfvy0ucxWHdrBpfiGZ913BtxlGt7H8yYqQzzmFIAQP2RFVE7gqjuIkU2Vj8D+/ 68L9K7Q3ZbxktBIYkKYUHHv/8E17sp+OGmT7/mv56Q6oSW6GqcbZZtkSp/pAnHMZz+T8zZpP18tH t9Th92KLbxtwDUIs6/pNS1ky7OAGyWHm2OaapgFV/B6Xzu+mSHDgRzeYyhx2LR1S7s3ZGbeOuiaN 0bcNzzvcV00UCEdEFZPqGfsMVh187DyUz/+juJ4eoCdvo2WcRnHgBG/kEmODx9PnBiXDE/rcGlu/ dPOiRerOCrYpnopXQ/GB7keCfx/E5cIjsB/e8STKQsyFB1/fGdrhM/64JcbUR5m58pDEI/vs9/hL NyUx1A3pjVTmWnRjkzD2lKHkja2rt3aUmW7Plr2tw5EweZBxF1Wiv0Gj3cGtFzbf/4v1G0IdHAbK TlX1gtjmKQFk/AjI4XHNexSvjWlxWqkMm4OQ3nWaiunIglX3NrT4FXnYwUUdYkHtBohRrbipmTg7 HbuxBpgBJ2aGp+udI573cParANVPCd/d2DC0ou6IVeCxXKnu26CvHpk5EsUMDoJUmU0nMAXSK1uo CignYh5H1TROmk8uBRp6uo+tUKy+g4b77/KKmSg25P1NeZ+CMo1BQbf9Dr09M/CKK8bb267njLv/ QUWY9viSNGotgdXw7VTrNukaNN4n6UsBB1n0bsMPaJ/XDVCOU7j10BDOgM1106HQVL8Pmh7fljT9 j35FY+hYufI6goKPNMESQHczxnRflj1+/CKwXdyyihFIV0nh/wBsNrp8BvZSdPXWwPVm3whlTogr r3lax54DtSYZa/jv+2c7fhttmoz5OztkfM+jWAIW0XVqEFt1G01AzdHaVqFquOxQHJmLMj8A5p5N s96yhwg8UBl9lLiJ0+LynWzqj81bCnmfG7/Dvucmq3aNiK2+TvRbrNrLOomP+7NvPE3cUNQw6Yhn m4xtCZLGjh9bHIeIhnR48jordNwGj/XQkozL5aV0YElS5hoUZE9BzWCObfBZd8CIV59ZZL48MQQb kAmD8XTVZEwx//7a6Ak2wKTa0qWQeIUTD6iH4tTf0qw/DuETf/YKwzL0Di6UAuKRse8POsRSwK4J 9MHdbP8V7XODCsmpZ8a+bkpLnnpcvOI8unROPEeGU4PvwYSclyZq6VWNmPD93YqjfUqAQi0Xvrl7 W/g+p18cT57x4/2sMGOA8vb9hlKmCKKPJJ7ehMa5i8bSiovxmL8q9DSPWsLv8yapLkvbWhN19ZjU Qs6pXCqOLxpFLeQYKLWMBoi9sk/mC0ZW17NqyunAPhCrevOPSJW26g4RvLL1pg7VrXCX56UgUnZ+ ejfrcgcdcCLq8eArhh5pyeVf97WbKnlxSNRU1ZVNYxKSFdaO0aeJpzEpmR7DjnqV9bXZ9Seo+AdJ HoTk4r2SSHVHkpQ5jrIWgd9aBdsqTYT9C8/SrKxchqmge/GvYM4zwTtq9lYCr9zd+/F1tfUGdrRu be6hwxpmwLFSluAvoLiTkZ2OIIUw3g9EQO8EfBLYIndjkvVJu/gCIVOMXePb9OR86WCgbmU1BmdH hXfCplgptbDl2kfkR/0V6GXyQqhwpTsk1piNS1/07kmi9VuYQOfzF4xjEwsFx7olPpFRyAljUmPK 7yyXG5NLi6XSnslQLuoqLnoFwhjahdD1ISTc+zbadcjkCJVSBKlCNWE8W9+2b+Erlclt/s1w/M0R Fa/6EVjSKnQ+uxdC1N2/BCjPShw9XfsEoS1SMG3pyQP06wX0DCCEHz6CaX4gy35eJYbifPS7cjow fx3h/L1epARh3qx8ywp2pU81no8shrHgdQQmDoHKCZ6Pfp8g58I/Pa8INf4T9sAQYfPlV/yKPr94 dxz1p1GTmYHeQQmZ3P4+ETAcQNOF87YEkj8O2d0hNexMS8d1Ss45CYRqOrURXFI/j9gHvdqDzcuw xqeq+bZJASS9veHQA/kIqYHZ5+FlPn3qPbPQRbyL5ElCtReWuWEQMq4KiHFgZpA5moejs8OUkoWG zREGt4a25jWm+uMqVfIXGe6Wrc91P/JEl5xenyaGT8vcLJETzyAGmSFDNUapHC4+bcZpJlOsu0c1 MHz+LkKIsmLpYElFqEsLQWKKNgRovdZbigW1CZqOsYagnTlA3/cdkxQz4zBIus+OTy3CP9hzZ2OQ aZX2t6RWcHwy+Wm9tomq+ONKPEtCuUjpktFqUTYxJn5Y1jbebsUbMQipSRP0BkhRKtMRpF696gHW 7XDkkVdfvVPnYeNkdZ34gcJCuBEPcrdM8J6E4EWWEdFlGNz34r8YTqeKfRUx3ctHT4/wTeTqs6fn ERi2ww80YKOJTsjOcfMPbLSlOHOM5EHD9yDl9IPeDkzD6lBnvW495hGIccRwq8q0Jk15ZIXb4HGJ TSVK2MPcHa8cfVpyD8oxKXohnmFKCzq0F6avYxnoNzxaqGWm1wcYqj8pCMTqCVd94t68c0zPqlWP uXE/lRV3sER66+iuWMwQXarOdZv5MeZELN1JD9hgL9cpiwpgNpC0xyqysy53WBVZoIadygW1/xMA AhQ+foHl6DA8xK+E5ZOIk86ykepd86SRfA6/pkZ1acPY6gIzjMYb3snCJXepVM3X4y1I0xDpSZMr gR29xTC6nC1FrK9X46Fqgui1aO4XXTN9CUOKEiQZojUAlye9MjLenFMLRsbMqEqrjZzQlMHCLmsG YXO/NS94lFyWZZI9Tp9Gvvd5MmKEvI++VzreY2G67QGqfYdiLA0p1K2rkwtZ5A6tjhxa1zAGz5yS 6o6rvUHa6J+8MedtKvYgnHL063IW3G42defKIvpmEiHX5zxbbsjGjXzD8C+AlCO0Eol1AHo0g3E9 k9axA0cPPck0zhdjSeVTOBZVHeXCGsYnOUMmNqRiM1MKJATobipcTlqmp70Agn6oeTF6ubKMMlr6 DlOe9oouSPjSBF73vqOdBXhEISgkh0U4PGZUJumEECDQYpS/X35Av3PpeZDjnd+aL9c+/2bzI6Hf aV2m2TMLBLwB0ZZBPnr4J9KRM0Hp5rD09XXCcuIz69xrtvf8UEdvbVGYgHWI0WcxUVHAWdKNflOy AcHC8AhD2DvNk6tIm1bIkrwi6tJ8swRKPwwjRZgF+9uAfuNTZfJOf+3YLzRIF6BhKUktzvvTgEpu idGya58GTX4g6yJORFQ3bdazpLe6hysRb04a8/UIhTTQyABUwInnd9KsI0Y7ic5UWY3oQAYgEP4J wvxqFeN999J9m3Bqu/epF+F6b52BQWcKWVt5xboJ5+Jk2/aJFBdDDvd6L+3b9Y7NiEHGDpL21BL3 4xjp6ozJ2In1URPCLwF/ujEzDaRNLTrtAwF83wgrCX3AsQwy7/V3JwmOnpTlpft9xx6AQ2MsaXTZ XZgB7XOIrxDCx27mOWXb9Z2gn7nkYovXDfQ0UgXqk37wS36AwAoRDBrl+JidIJ1wRaxtxAdngInC XURh2pgREFCK6ugu+RTqjFu8pBN8SA7AChqEfKSILluD8zofyaXcjxMKGF+lWMEzoyP7ue85oKM3 SSQXHdDG1Rd0BP7Jael5eWkvpn52SQIpql3cDaFW7Qwq1zQdz81efUYltupIPTII4CPRqKp64Q== `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 23360) `protect data_block nBZ1vLOKKFLxq/wFdE7anpwE7jHXaNkfMzNsf8hTMAqXri92qUV62Nhjw6GTGZ0Ddy9B2yl5tUH2 r91Gqs+eEflEVxhGe9+HEyTCfT1gLr0zp+dTzvfLzvMQfsYorKml4bc15vRcKRVTLsXu9+IyvzLf TX7agGGGn4NhfB5E7u8WZMJsKXIrORfsHABmPUAOGvEeVWE/bFzfFOz4EM4vV+wz1gaZTJvIkcdP CgGqqWULbUMuTUxkfaClj3pu3XNlB06shLqaaP0nQBnKvO40W14J52AEwMLHMBErSufy0fBxuwgG Dipvk+BcYLRhlKZNYomckAG/hPZeJGuxy2Yk6C+qNg5FUMMVB44Evc1k90j73RGwWPlfeEV/r6m4 Kngga0RvshaXMsSxSms0ksYO6aZQyKeK8a2l2OqWH9TzBGxrfjGfpdJYUk+wVUmSP1IkfqL6AePm BQk9jH6g3hQ4wBQbSpexMeKCfritybbTJdI86DWGoX1b7FagGyq3MZlhcWUlF/VJKqZ08fgbV58m 7yiAw2kvxUJxck0cF/ExRiVGjP7eR+yYzWXibkF8jTD75N1bmBdvK//SbfB+K/L6PKmM8s3bceG1 KkVQS9WnobJmYD35ZawlJC8siEd/fuxMxWWiJKCkdJOjHek8J7D89gqr/bFuw0j4+zps6ECpDUP4 mb6Hzaj/AIn8Xae/cNvyRZpfCCT7NjPnpOE0IH9SIYGASgmXS4jWvnEsIDBecB5JA6PUbY+Nzj59 t8HGKRKB/ugcDMEiZpvVN0bii9vdQxskDAm3GkE9HUszF62N4GjV8Sk2D5iyhLcWVAOVV2DtTx3R Jq5zFR11i+zfh22po7VYKkM9anoJuv4nS3L66HNOD6hYVm8IoCsgpXK7C/gM1RnK/eVLsQEw47cH UQgujCeK53k188nokCFsoMmlJpl445mBqaALGlhmvkKqqY/NoaUSUuZH+kaO1Ikt2PFjubNuRRpb nHbfxj+K5FqUuv5ksq4m0FhWel26vPeXFGgNK0Tvtys+XbN/+HG794sLzs+VTYQAhNslTBpw4Xgq ArvcDyYv2QOhlD6ZSd5TDjP+kTrygjoRXR48F51NKY26lBuGR5fWEi77tuqceL+rGs4wAt2nqPW3 zgMBh7mdspwox0uOu0g9oqMfqOHZEgZ7ej2NCLQlwCR0QV+5AhTyFgdZEiqXgxpkBX4G3BZRXe5Y TF83aLB2hzU0RjGFENDu5qBQaQzlw/FYXSRhlxaNwQLzzkKqfhHJ4XQsFfzn6HqQuEtWM+8gfU0/ hGdDCVUd3NnhRC+AOdxqq/d0pacOCmly8JonTyPWsQRc9hpJaVyVeLA/LSkCACLUFFZw9MegoJuf 5g/i9BwHeImI97IvnwEdm+UUS6qHTv6DLTUtqpb+kl+X258fotGVR5BfgBQ5baxfgO6OQ97QTROF 28VFzkZ4FYXOcL5No444Zrj4CU05yU2Px8xbqLHsWa8EBl1OINtFFTUTtjYhMa5kNSjt26RnZgeB oZjxymgf0xD44RhW7HbBVWING0/LMlZ3XdmLiSsoNiPQPXUjYAVPfx1vQQ+aLR88oWmpwhhf++lx TXJl3DCSdV2mKX8VPIUr2j80YBHZ1SX52o5fuNXuif2vRLPFFFvoP/0lT633ULGfLVKjk5YLiCWW zNr9thhBXvymzlK6WzuPhb5uJsZhEWJ6+mR4qxZr1X9qMXfEt3huG4NqW0xudv6GXy7KlKKAuITQ ed6I+hoULN5V0s9+HvWXX353bbQFUAhvI6o18A/LxghtsXyLbqAvJDqZySAoGcWnH0SLAiswkHzd Fc2zo+FYtfOZLrnji3ueuH+WRZ1DWEgJeXU5yrYxKDshg1L75d+R9kX84zCTyb3CTfa+UmWk5ofy EGTx92OMkLr/J5Bnun36V15cQkNp4J0wLS7GPFwEZARynJcfybuB23TE9xSwxVQuB46rLgiyGGMb KU9MGKsEvCtinUBw/CLikf6mdk8rAEGM87hwXN6uraXz6RKXW1rd3g41e5WzxxcKjp6JXq48yzp2 fOjbPEvarLXHIVpOzBgSsRr9GbciaBZ+LcCI0U9QGLcBPkVd+cpZLcKQ6rokKtYeJrSKqZLsMvFz r7S55+kOLo+9OYgZghFtEaIgbGuk5l2VVX7m8moiALUUozK+1pWXyXYaow0Ycv5wjdMmSeVYUuGG eDMF5/J/e9/c7D/bRb6hTw8suacSe09ePPZXEQlKZdBYHiqr2WAC39zRy3jFQ+9cPwf4WzFPIBkK QV9vgjtpzMwP6Zij7GtEZwCeVb5D99XJ4bfztFOcGPMrCrmjSce6itMW9n+prgnzjjDJBDsGbmoe 0LB/VyDLDnufGF1yKXu+o3kE7WM9SPPshd6YjReKm0xdjMwwER3T8TfCn3D8NND/BWSN87594OE+ 9S0yh36+crxMCwtzvN0vHYJVHy1WTXIPf+mOdgvUPLWyNwLKf5XkFKOsf76mP4XaIWNuTIUP6X+O LwwRktqbJYGqf1cCi+fTaIoBs4sq4wDDlJ0pEQ9sxvoy64p0aQnj0rODONDbwOjzZrEhP+Pl/U3o j7KsGw7Vdh7n5UjUJkOjXLg926Xwke7xA3/XYEruZjzR30lHl0BiILU2/RZ6xVJMz2ZdcwqIHxm1 /oJJPc8A9+waGHOBMcPbFFPaS5gGAZb/Tx1ueacMuNMyDc7HPFaqnBHbPYgr49b8eKPFYUEehNAy Ork8qWh27kc1KP8cejMt81ZTATXCsKLf/MxDvQMNog/hvKlpkASAHv/IuFD1zac4xskXei16+EMl m+fhwp5pF1lZp5gp1OR58dLHVkRklElEdGlLdDa8j9annFWS3CVfA9TzSIrY/3QUhZyWWKMf7/Gh N1MstdiGvN7OGbwpuCHafTXB/TJAqNFq24+hx5y/fIVo+2UHT3sAabK5jLjguTQF5Nz7EU0RCEeI q2n6soNt/ViY5bpNmL1v0s5f7jy0yZz/DDiOZmpMxiHf1M7t7OUrU8mG6JVef8V6ySXM2HviV95Y 6+M46uxcihKcvhpluH7JT3LRxsrR4dHlWajTjGbnM9HP/ekfaM4eFSGIvwBLmhJIu16cBgPRsdaW gtZZytAjIccu73OLU/T66/fGTJjdBUJPnaZHIFwJJFj2CTfTUirXFwfdQdXIqoCyt61l/JkXK36u L8kwlS72aGDdK3HDYBDWklH23tUhNN/Q92hEfg+NtsqfhuMuSF/wErjSEnEc4cvugjTC0bgt9atM 7D1/sodF0SMrPY7gltVv0i38iovx+a3pp+QdAxcpEqIZCdrBUXvS/oSPPE7YuR8vdqLHnSSCWLaM hQEGc5GbDDdYlElMjX9C+ShDPWoH1GdvvMt7Sk3riin3zbdmKEtvio6QpClM0Gk/ow1rqIaGOv3G YcE91v3Keik9R8cY3b3Y+M8qV+93E1k6EZMDUbNf8rZKmjbCDHhdAK+xiSRiQkH1xMhHKWmiDm5A le2qHWs+BtRyuvPyEjAVuovIQWbC+WnPVj5HF7XxWmHJcgLRT/bpOxwKq/IUrZ+HkKurc53uSz3V 1JCgUvYbio2eVL1oxeN2kPR5oJezOTb0STwCCHA8iziqMzJDUIC9OsFyesjoIkT/xBsTdFVrXlsm /mLsd1pr4prBYZKpb4ejyQd0bnP+9j3z0TotzmupZ+7/pUVL4NzXVXtcOoBOUnBCoRHAg7DCCr5f j3mgVZgzdxognpY3GiVCCQnzaf6KOt2yu/2d9Y5MqVDv7J7EnFnnYmE2ZeQ3x6FeS8bsaoppS2KU c/IopRnHtYf2BS1BlvNpu3qI/sbNVZz9/p1OuGGa9ImXlkkF9sRittfYG/U0HBrH3phAmR+9Zb7p 4xkvCMC7SN0A0ka6K6rwcevNMI1d80KZMKszogS6ZWrqS7GGwNJ1fEB+vzgO0tId29xdSPcecW3K OGeaj7Tq3OIUKcDwrYAHbxxnFOS7+vnQ7sBk/glAwAEOUgiUZJrivyNA0lXOixXCHTbWhk7bPJGo rEPHnbbPeDBZeTvQUaem6cb5Mp23uoSB06UA8jT0C5FXX9lp8zuaESBeEn1Jogl/bJTUIeiRAt11 aqmgqv79TcOmS2SS/6urbJOyYH3v5f12ve28pXiNMdZbNnn8yH53mvkYEs35wmf8roCj0j4vWwr/ 1tMY64ipU9dgWYgWRmlVLyutBdojkALkQYMDYcxHEnsqrYOzL0itNadxEyKuIJsZsIzh3kZfRndF OdDeHVLsicnYXXWESNiXi+rYTeG8cz+518YwwRIIlel5TNOSPEjuZa6Rvlbh1+hjhdj3IT0B+rVS Pi0fY/R1XHsL2j/fQwbKJNRtn8l0Fc5kOxjZu1yuv7oTab/rEHxxAhVKlZU02SJM+gm6yoOvxDmO TJdZZFffAGKUsQYwt43cuph6v6SiQYHbY+ytwnN3La/EqQHowEwf2Epzq+f4ordo1cWqaM+0jyOk lzdmtcPtXjZOqyTqerNf9CPnROViRvvZeRsti23bWHhCHOr8Aq8KQmR8woIKfReOiDMCGMkrn1Or zIX40S+TLGogVYFOdEPeIpl/nrfSLDPc2q+ttZ/JG7eFGwOAcO5AVcWrefSpntRSm0VG8XJsZ55T te+iqbs1CE/WQIqVfmFzovod7PEFTdgO9jxMn1JlvFSsutEnAKV1uv0zSH248HDsOWT81CIZRK+L Fhb/nVrcCSf0UGCQMPrKtLL3co7Fgt7/DEeUJ0x9vo3kZMZ/I0g5C4YvMIa6FJB2H2OmT4UQuFJ8 MEP/d9lhjB0ZFVOer6VZNbzoWzzUY2EBwb1uci9agS8c9Oc27SoAhlTxaF33mgnV92es1/0+rF73 ehkd+6LyL6K+OqtVQmwKyPtWhXqQqFLrhePwpk/HaUn6ii3ixymSmMGraDLSEWXUioJwBt0asD0K 3K7rlQM5xNAeqneEvQ637Pl6LvrYauYVpeYWrseoVvMQViIoV8cYKHon4ccvsu7OtwCdh7p3+WMr RWcZ9XKOid7JS2rmWUX+jQ/4fatDn7hKH3imuky7YVuRpRqs9lmL2V75SfhMB/pM5pWCZm4/zMI/ QLlh7P/m34Yqmw/Er5h4y4UMNliGn7UJdDYXc9FRkf6x6k1TNjGr1/KP60FzPWjKyeqndlfNzSIN LSTXPthAJ+vAkgTNK0Yy9J70eDT9sC64NHM2ZC/jlV6OpcnUQe/9koW/rt5EfhUZZWKSoAICrz6d 2vu4q30O2kLybyMhqTC3R90uPoekYejbxgeli0dOrGv0QSuHXDsqi9DaN+Ht1jmjidtSfzgSCaFK tzpj76FOoIVpSjccJygTHDWItGlC+RBOwTZ3AiUFORAmvtobvYx7gkMfAEKuEDuN2JfLd2h/Rv1B maLwFFqAsXUcQSRltUpq+mqhQUmw7b+f4x843yXPnyAZJvWy1+fOlaAYcL7/3rt+VMKVnZjBMSUO EjnOuXnuiZCVhLdGYc8Y23MzD/oxy9uSL8qheDkoQg/dXRMATWFv5z0bLDPUgDsxuEnIa486lBZv 9PesL/lRDzyitmc3/Vap8LaFbWvgEpnRkml6In5Hdnkz1GoOoZZjvlpG2x6AFjzVE6Tpumszs5hh lErcjVERh1cMtE6yipR6FAc/UV7JRy1LSqsP0qLEL2A/5Cp5scxbyt7K5TBBJXzcdpsEuMMWQWvV hxbt5U6OFmt+n7cIN0I2z83TiedjU/MilCPNFpAjTS+yFywSkviBm16jTVe9xbVgORx17YXj9t3z 9DbgBa9T0oS8J8nJ1cpDPAmQL/0tnC7zTus//1rKty92JJ7dohuD4S98w21bEVpg2crJbE8aDd1k ns3EW9E4qntxqwtJzwXPsiMX2myg9QnBOadDdz5UTRlyc5HWkaafUEu1ubmbu0y1OvfR87mMaurk 3r0/IpiLGTkMKdnJEOQj6nymcrt08jY2OY5fQA4ufP4ZGeQJ1QWTmt3pNvgYQavgQ6DGqZAu384f JnQ939fJYUpazuqz+DHVP3IB02a45MdbkGetRWGBedquPwf1sU2nzms3CDEkKyuwAnHweFwhgmwL pSx9Rg2Ngi9PNKSGAuHPrJot448qwDmlMmDRIMNAmS3DmPQAQ0lVe78RM+S5k+isNWwq/vld3ROD RLC8t9tLoZd67QFtGoP3hHTAtxADAIYofSjTfG9CvdpOoJxpfdS57/A6JdH0j1crzJk7cE002JAx O/7o09RRVHqdBuXVS7NSHm6e+4+0uezR2L+5pN+EGkSFN+PHWTCGyDznVA7zZoa8lrZtKaCRXMUL AHUrJ2bZvM9dBn3enOMFplUQ5W7vmvdJJCSa0AtnYnSWiYqj24FWTOmw2maSnfvAMufPP2uTC8Nx VRdiCiodYMWpayl6ga+zuP4IGN6olzRpHW2oSfpS54jEV8erG1DZwt+PoV/ocKupxy5+Zswz31xc Nz3lXYjpyeZHdQsG6g4g5SosC4F79w1slu9hrSTA+TCEMX4k41HOVnG3ER7y8GnZ/ZwddXM7YyNL a2q6OZWORFMxH/1KsSHkvoKUd5slHphv+ps9QNYnZHxe0gIA2x0cbu6bJo6n70fLIuTe8Hy7O6HA jJglvQ3SR2qcqhxG8GR/BD7309X87xjUHqkX0tqukofOuUYKrsWs84Ta0qYau3qowMys/id9aDmr ZD960rhKSq6xSTAZqtUr2CEBkABDwMI3p0+8BZJ/7xl0MvOUztdUjNo5S9kITM+6ilkRbqmvrpPx Dq3tYw+d2YIcGeHHF1pGH2YRtY/2ghUdaoRXYvhh0w4hhb0LNP9NtJ/w1OsgnTcRqFbTM+VoHTSi 2pqysrertSq87jnqJS/NDdSV+Mm6BdnyK7KOQxnFHkjqqCcyJZzgDgOxrp4zLpxGRICaJ/4HO8CE JIUQ2ObfMI9MR9VN8jM4oZw6DwYTlTcbXbztSk0QG2rNnEmEpmItVPIy9Qp4q064D8jX5FxDbu6I hSdJGGUscNZKjCaX4AguzNYebcem/zBz/DPnLWzCw8wV58yXLdTXkNg7irn64g+uTKqho493PSOc MpLYWaVzkvnf6KS5s7S2JBZHkIYMBGqk2K/Q+RWZCT8vMiKBUjGAjF5WDQIiYZ+VmeaMgpeU0Mxc /f2q+G1qInajx0/fcAJYZkA9YqYC2sl4YHyUpam7CEpLZesxpI77bBQOkH0C7dV0jPzXigjuXfUb ctLUZIW6hNF5cffBVrr+sLeTS+HAOKY5ETdQzVOYa/ly9Otnm0yXzyCJw1cXzN9wwdQtrHnubyb1 6plvkKm0uYCk436A3Ihsd9a0XvUVYp5SKn2BfNHlhRH3hL+Al7Hy5uaUCykBnICdQ4VJG6Z4hnP9 YE15C1FjUPnboFswz4o90Brwp03fa4bMBKm3/fSq5ck9b92/PWAMBTJiKxyoYxdQEwYvn28HrVA3 yfWtzbC8KAruSG4zBZ69wmI0C76/G9scY0eM6dwdBzAE0wXXi0Wn4hZF1tDmyMUBSaRGqe2Og+Es xk3t0SpnGbJCL1bU++ob0430iFCd+1iP3SZH578VfKQkVBkz/UIL30YE1dhVmOqXyU5xXncllUDs ZL9bE07QrVF6wGlst9xaj2+DjzAySCiRSWjkrv7HhJPIdGnK4464ZCybTzZzFtq7JYCamFwzQTG0 Vip3FMgRJ/ngiBRr16Ch2ZIkujDesWR+l7IQEPgSQIeyBjwKxsuEQ5bs6jEnRoPNDY1dTrIW9uYa eWsHgkYJE09O9QnkmGivjkwTKDNtpkEakA/8Dw5JizXNCdDf03nUNdQPcVpy94zrrwnN+TCPYQJA Ul4FaNUOdEZ8mlqQ4jsYNuEKTQa5w8Ccbgkpc6q2TVV44kkFSp46mXiI+mJcMG27VuqS7yxUxmsf GI8+9d+X7qGlOJH66KSb9FczxSrHpkrV2VcB2z6DISISCGKsbPHQI9gv8kUW79yuR8pWT1N4qM6R c30XOae4N9628jq+9hdvf7tCrav7VdU4KPMUgxx3l+PQ2VOrsENirtaCekWA2quOEN4XMy0q772Q dbyZhiJyCoa+WYgg7bBB7lCohQVHfjeGNwDfy3CAS5I5UWeWoZmXw60prxnMxhUX9CMhH/+p4uIX SIOpT/Gr8hxnPcstK5zpEAbxk8NASHevxAjvTpAZ842dP3qwpqWCl4wNO5VMhtNtefRpMyPZoPIR eSRjXLfDy/wdGiw4pJn/j1QqFUVukVHxiImpSeDwfQISeMdpERhaumV9UlT+xryIDxtc6CW2Rntn EWQZDlNM0TTpI+UTlMe5L/r6SY6MU3+6hAy+2EAhnf8cuargTv6gXMg8TsWgSSZFruWPNFSraRVU FkHe2bBk6pe1NlTz10k4x7qKI6FVHyi01NqU3VsUDczfA8AcKXFvFZ5DzKrPD8WPltHfUfzrO4ca MJPaCD2362ePx23FbDHW+nwC2lN42XsEVAdIZxJLq3dtUEQTMX8OxjUg1nZItXeKc0cG/282qjzY jxs2JRmYkQQpT8UJkVLWZdcK5s8/6uLD5raXfhhC7zRu0gPrs5IZ9X0hAWatqMDyP3NHDwr2Qwjw M84RxbwH20V3w3HiqBzjogQb5aVBiO8wek/oOdexyRRtnKneSk4bULGqRCPcfn116ywy0LsIi10h 9BFv0XpNIEDpNj/jqo371/LSLGWEil4aGyKkh+soVou8FT3TzXFfaK50pZZd9xwwfz03IwcW8n77 Jy1TmWfwlGjk4WF6IRFZ11+XmhVOLQC78SUV19r40dEROTMH2gg3aGp5GnYQPiCcCT0XeuUYGX37 yUvpuEh/ghEJhFiYuVueElqhl7doU3LCIkC7Djs54NPA64GTS7URqVUr53WZjTUqP3F0vUcJNfD0 SeaHL74itpd/evKrNmZhc0P6sYdxJJDo3xmOeqKW5Xl1EqW3pOb2gJ0YRlDHHtAyJS91Pznk50pi qW8t4xcRVt6P7mtE+NyqU0lrjxjTH/BSmB++axqzTMinRssKD90Q7kzmQz6D6vBjJ4vahNfkfQU9 YGSZIb1c3/zsGsSb1YSqMWp41ujT/Q9acCC87YCplR4FYraV5WH/joFcusrkpv7rgRcz3r+CvLrG 9eX8lQuXDiIbJh+1F8+5G/29jzOMiG5Gz3fpmj1z7fSW7V5WM77uNQ2v2he4YvA/9etSIYzWBpUO cwxBRGArT6fvYUXxi+6QQfuB1oT1cbLM1DDqU+FGPTXm0BF5WpPEbUQ+YFdu4d9OMSI28mHlnrTk 7pMzFqE2/wJwYYAwPrNlfJxQleCC+h806Zb1S0sy5lrLt8vmeaXy2JwgJSQHWauqMh82tciz//9Q 3RapQKVM+mcqqscmB2WmuavKoT4ZdRz6cVWOxxq5i2kgsYWq84Syr2Ir7PUhqxVHcJJXkc0205zq OX5Zt9hNzxdWoa7xD3hjh7FwY7oIe0j/6rZXfKdH01ADGHIxdRgfBC5YrcXf1VtZAGJ7IuKfa/2B JmtZaZ49EXUDfqu2t8JjXItGUkMnNi4WEcH+KcSIyrw3nKJncGEvKdeB38gAHwtiDH2sHBhw670n tskkIKoyUNlQiAlV2CDuREgGakGa5uh3U2LUaJtkdMBzW0B/T/Go3ICy4hNl3NVmi8Tu0TG7JdVu s6NnxBftlwZZDbtXHj608DEYbHNdC/puA+pBWBueS5LjUpcGkS6Fze6zyg/Ee6KLvkj4aFnMZlr9 Wb6t2Ijs4SJX1PAGd5Kz3Bcu4WMW8M8diu9uk6vs6uZplCw3evXWjTsuSIwx4PWf9Hf0EzvYpPuX +BQmA44g3An5LKxi5YVUfRFbjPMlBemqtJZtZfCMEq5o6fmkhB/w+xeUJWIzwwx8/a7s0dINRHc1 E7VB87XQgWafJJpHao5gN4Cy5FCfRfbIotEhtZCK/4LcCeTYSImsXyh+XeoyTJ1cGctzb/KgnLim xsu5x/7R6O8C96U4Q381MNbfNmTN7m7F8Z76VTxl/DDqTE5QhKFe3GM1xlNpRZnYIwjnXYtTeP9W 1uVyuiuVhZ7qMpZ1xrYadsSAdSDD7cWpr2/33v1u3eu1KN2e1iNZgLrwyeC8PWuskMdp1PYnPhma 4lMOFwZM9LcxJdJU+8ruAvptMQfdd2ryITypXd79pN7E/JL8ke8jCM9KAFq8pJM2x7N+txF8WMia ZFFjMX/6f64EeQIYiVIwykKti66OSeti9CVf4xbmbWy53L/8Eficab4aLS8v88PvB0SwOisdUjFw lxL8TNEHdGXQ8tKSRB//MMW4E+aKiKd8qGU1TPrWpTBknPPuykRqQsIgV+RKveQ1GYRqAn8/Eplf SAnL02YfVUV6vk78y+ZjmUUcTJ21ONarSbdj03dwfTY17NS8PyhzkpDP2oUeFHr25ToFlym+4zQJ f/9MGvjpMoTc2Rdk1XMchJY6awPKHle5cxPjx0bh7l+iaBXXljnnf/2qn2EIJkn42R7aYDvSXVkp 5C9bX1cIvVtJbCLo9HMwdVVmaSOakVyCWBkzTSCQAELDIJWm4menlehciX06U0XQ2jhT8ckGqoz/ D0EbayWVSCxD1YpMv+KyMS33hlQJELnEFe/d6szsggvdPWu64inKgLOdFuuLdc3XhVTadFmH3tcu guLWu6eGFVjOe9ceX+MXLV2ICRPap3pBEweYunh4/WZh4HhKHqNEpleC0nGMLyRgvCmT17vjVZDS LdOdrag8hHkXxs0W/cc4eUodIMVuavLe4YYouMMA4Z8llOs4/Hd8vupBZXP1UtH27nNX45g+2RrD dX9RYDVSQyoD/nggDhAlKtkj2gjcK2OhaCis6UIg9lgKjXcQw47qLq9A4ztNubLXunoN3FaXBWBl 328eqfuEUWIJGWbhQgEzEsOseEjyeiOcWXcGWVeQ+09vfaQy6gvs3cKnQ0R5Csz+NflBxN8qP29b auIGfacVhpU1Nvcf7yYNe0/A5iRQdoE9qi6fINQXfPL7UFmhwdaEphiyxPABBL+NPQ1r0CP2JY5w 0t0h/QejL+21UNNfLV3WMR2WvXVKUHJzjLLOUMJ6OCWOufJxjdt4dwX+tiBlkKV07BzRQF6rVpkQ T5oDryHKmHC0QP+dIBqylyk2q/ZrVkdQzS90miYTFaUb87+dd97YI0hDyaAeHanRHSnQ6RkuGH0X z1Ngvh0w2UghyCmLTKKD2eXC2ewL/ekRPDmH5u4gsuqzxScNst31G7CqZbJAieba8V2dXZIv+7v2 RG0L6eC6h08bY7voFgogiT571GFjpjhSeEQyNcnb+M2Aq4uqQjMzjF/juhuRoLWd42YVCC/7EXA+ BM9W028m08J+B1Fj/wfccNByeQO03gA2DqdJOItqp9yUVDtPOX1Dsi/EFf6eZtkhQiN8dO4nMKHd fZYPNDYU6Woz/DaWIla80/nhbJ/FYYOnqyuqHIHLdZgaU622aybSfGde9Pl7L7r7cTDzKKd8ATBA fBpj6Y+bHiqh1Pgh8uaSG1SScmNw6ePaOCUpnCyxRhsueS7oYJUY5J3PQpgSmB3I8IMG0vmWTJk5 oPkstguNACMu11nJ44cEcOqklmoXZQ7W3hsI9Hp9Fk3t4KqGEhdjOnnFNum1o+rjNaKoLOkh1xv7 WqJwx1Ts4f9yeKO9lKJrBbjEQs9Z0Slzphl8aVaGe/4JlJBt02oGGUq0D6DCZBsF/wsGuOKcZ7jH ZXKLiJ/tP0a3im3ZkgqlhwWjINZODIAxYkvGCMcgc0b0f0qFf6Uc0T1yyuFh2GYVgXdB051nNguW 2ZdqLJmeVTPdnma08hidDg80BmIxbqPklIRqHtNe3/ZPX4mvN2YAoF4QK+JqBbm/HLjvgk0hmqy+ qq4cM51seB7q6eZmR/wRBhFaI5OGV5cj3goH07+RRI9QIYpgs9hf5Mh9j4XGX8Ui688CPc9E1XdV ITaDXFAQktxt/NxbCQWAzl/ocT+lO5lJsFMnD+y1x8/8trfmrt3dFcAG+eOq9BXv+SbJoW21zMHK 1wlWxs1kWFDPdEjuQv5IQZYVJlsKbPy89xXKZU7W7NhVLrGa9fFPmIRV0xlqGTyB0PauRFoWO/kc QHSBk5K73JAsbHkWxtoTrMoPvPeOrJREuBKldgzeg+yxMv/7JNaU/4S4xGLhrOcbhMYftZIUAmnn XTC71RaxZVidH6nKNX9Q9qbAEy+500rGrgrPvLv2ZRmkHvqrbkfd6nqN5+deC95GTUSurqP78ltz FdTTwVjfEhqVj/WWN2O9Rc/2jX1Q2YlTwft00Y4FUeQJzZklGCDHBrK0SVC+gRMEmygqQwBT/GZy jPdVAGUbNxPrI3dAiS9T2eTaTVVrABqG2f8g9QvjEwcQ30mdXoWDEFR/Q9cdzzrmocFFsj0zJM3K 5piIEYW+T/foVeu7rzyTW4mwVozJUgEOgP+8MzgTj0F4BtUyNZDGlIYOQZAaBotHcvTFWm2D2xBd wfVWbuCqD/qEvE67yNOlBVeU31SwRyrB2wVrVfsKrTjXdKwzW+8q33jOe9WYg5tf9aPJSSgRVG/c 9FyuagCj+KW88L/jDJgg0sc1ANREV1tbnHUsRjeE/bS2doKzACd12/qUmwrmK/J299SdQDh2eyig RhfjixwjwST2C/pfYM9W1DSIau1X3A0N5YEmJHNwGm+ACfAAxbRrlKmhAwd+EQBxCNU5F/goGEeY o2+M2FJsJ3IJpqLy1UfqS1uh3E4ElSMka/giSdRHnQLtC35gHDiveCq3pBSnwuoXnPNE/C/6QcrD p6vlK1izUxlW3FPcq7KotXzlnnIeQGFnB6idVR+DFvus7xu1phniWUfbsEvX/YER/Grwroxv6lxd OnOAoqZtneUzJsQpRo/tin390ToB1HwKzM6V/gYyBUeHp0FzDquY9uST0+xROmKc/jF2ge80iz9n wPCNFLqsiv2Oo4bKrvT5eBR9euJk1pMENHPV2fT0Y9D02dpn9N7BV/lSBZ9smg2uaNL9L9x8lQEP u9crzB8JtTJiot1OGcq+MC6OFh/lv2TMQjUk3xF7QyivoaU5EF2l0xfZVwFwdQYX/tUMv6azqtFq K2xyEHfvRw4xDAWbid4FjY0xaW9TEcm+FOL2hbTWh0CVm+nYorJC4wj+aOWabHeG88bphy1bYQQd gEBEFX9oxkOmdzQUAtFn7aGkJ/Sx2OAoXHWERHMFIia9AM4kbLVQx6LRDdJ0rJEeFJ0QHROXYiFE GPa57Dy0G9hVatsSajAkETnUJ6E9PNCiENdApWiz9g5z5VIlYyvDI4V91Z2zA/YfwgnYWBemgKvY oH7NlFpUMDZRuDE0NpSmyWV86/c138b+l+Iq3ApWyquzjydPeEtr+B6r7ZSjfilRC7H3UqBLziTL XdMsmbi/6VCORwlLgZNGND7GxypEKkF6HC6J/jcbUpovHuOChFcX3DAxxw7paXieuXY/Nn++aTnX UsX/wv/RChk1ID4JQbykBjagj4+cuybQo6Cy+Ngb6iORdJ4RIvWJsLVSD3GE1ub4xJMRwFXuxW8f qn2gtLvAQ/Hxly2tJFoG4ClUFTZjRpQIUYJiKro/dDU10BU8KGHx9QvJkZMexC+d2nc90/YJa3W5 s6wWEPf64raF0LtiokwZ4Q0KCNnrSB0SfaaF/wb/ukzKgl9mUi9XCmt9Kx8BW3fw3UPbC7fBXtgr jm6LlnkGqvjgx4hA/GHxYST72nW25B3EtyfdE/Zp0unsRhh3/mhfv2EuKXM1wO8kmnclMTmg2NjE Vw4XZKPU8j7PshBkDdPgQbHU2oVTCIioyP4TXFfE6LgY+5vRgbiIl0dbNZoQjxmxo4ZAJrPfK9hJ W2koXrd0bhlT24P4SkqsVuAJ3kYoIHi0oFYhfUw51vXg2W+N/zEoc3JblJpo3xUmKuB7SR8iSoNP O8g9b8OcEQ6VuPmmX9GS3EPDS9aucm4EEQWIUvb/GX6dzi0Pnx6WQBdoL4XM2ejO8mnliFoGb5Qk YRpAXwAi4PkL68KxdJ1HH8jSnLzI8mz9giy8wHMqjtIG6+r+eykKol1LimiagxSltvacoE3kaxO3 /furT1GN9Mlyzlt/mum/2GzwV895gYdvLM8/OsgOTpHyyjTH5lMZaVFHlBckHuDj8aSO7AzzbTso +F3dPfENfWsq1e5WFhmYolxETcLrjyAtuI1AIwq7iULpRk1rIoMkKezVpVeh6tSmcMi5oV5CBpJ5 hNHdTRLuxKicOXIhXJG2QsheFk+SfyICdIKxsbih/r7ctOkWiZa4a6C6WnxcAPufaqlu4cLPsp5m ocTk3/+5Ajz016gElhyBYYOUz+MIbdPPfMCgQs3dTrMOmTzPhnZdd5QiDpHkTtJN9m3DMcOXXbou LVJTVASEMLMDt2b9aVhMsLpm2gSv2LjX5+mktBQnmZYLF8tUoqYZzkWwbBygxhYX9pGQH8VLZrrW OR5yXw4v8ZL1LxRwcKhhkHvnLLReA6azJD8PoWQZl3r7Qxv9kY6OGyPRKzhaJz9eB+UPNapSl7WM fwM8sAWCV0AosoJmTjikbgH1vFGdKsOT7drbyQOGazfqmMOJh67D1BVSjKyQy4f7g6HzIsiYaQwC piCtZpxiOrh58UICb0RKs1KmNpfZDfQE1Dbe6GZ5BhOr0MR1MCa1p249OVfvdbKs4c0YYwmoWaB7 zvcp6Wm5bVr0zYk047wCZUIKh1DjemYMLTt959FPC/VjQ3nO0qDT3xrQ52ORL3eOCnIwUwHY/ERY YnvtxAKiungvFfd4/xOFn/xRrEh3Nh8Ng3vtI12CQ9giNnFK8c3cKzUhxhVarA/SalsYZWlJn9QY CLBtt0sKV8FcE2jx/6QwpUU2SNIxyCoOutSSFxc63kydrPnRxbzlbgSTNuD/+1mPS24o7OpONzRt rPEnsPku8XH615RPXNurAXivEg5YierdeAAKdqUkEVmA53HTsOUT5Pe3cBFnQYD/Bin5YOk3sEll EVSCU4q0TQJPYRW0oStOeKdBd9XPbm5FG416zVcVC+d9fPFxX9NbUFUcYMTQTHUoFE+rIuWHjIUF wyHy7aKctmGkvKk0ElQRBsKtthKZP+fgNXXb9RSQJsnFSTjkbbn9LtP/OAqy0LjZOdu4PDQK8iCp 9wfZo+PbSdad5xoV0Ze83dXFkAsTUjrb14KCajPZ/5R5IMylrBBnzclSiozSAQ6UNiXXjBlW8/pw 65haTghLZ283d9VS04MCWE7jIQbg9/HPiL9/i3YzAzXMXplm7UEzNf4XYwIsH0ZvsZGu0i1c4Vld f4AISRWvbtrkM8O5ytxNIAPyDh69eMJnlW84IeT2opdzGT25keebOtKNmeLvwpR0qADGtmKbbdAT vtPilcaJ25c21AAJCmYzsh59WeAzG1Xji8Hlp0l7Tb0H26MShHvD76AeqxDs32CUqmMYsL46vD2f P+JMKXmOXLcxYNqmx+p42da6jNHC9UN8XWeeBCM6LamUIU4+55L1tHIE5Fa6J5Aq7u3rHpEHGzs8 4SuSMjZcwRGWitOLG3b/+Ues3IEhcufGM7OvHDd3+tVg4M4aKihcdMw9X5UVp93l7m9UAA9nXaxW MEybYoGw2l+KuX2NG8DTxTnYK0JAYCTsvjquOT8pdDdHf3KR/m96GKnyqzDf0nUcS+WuhWain9xR XNKKRoY31N4w5XJu2Yv+TIZCPizH+IU9yml3VpRlpwFCu0hU/lEyNDtXRDHaXfeIPAHTIfbTYkwF ZFzKlmyBZt453hs43uP20PgdnqxhS56wa5xBRxT+KUszlLQBRdTMzKOWdvPvXkwwe7W4pQ1sI+vk ItBZopzamsIrvFSMVCGTg+EgBvSFA1c3a0RTIX2btN+pDNPZ9BMh3I9kk+KoK1WKy5/e/SWSfhJa w2zRP/q6rBVx38vI1l/lH+H6WMfq8SD4JYOM3gpxMfT3nVl2+QsgCdKB29KeWA10ymyyt3Bdo/3i QyHY1v3C0xFKUHvM/6wG04WE9MclHPH7Dg8+dYJL+PCB5itwG/dSCiwuPYl5t0CVkhryqmWKXjUJ WRqK5wuSpDryr8pabR8wrZHVpXHQSHC227lkSvvCg5ap+JtUNsQsAZWNY7EXQE5AzCXeD1EKIj1K q3RFHdfXTOojnxeKLe7z5AdR4b6yWhZ3M81HJxYaFfZKfRIeuKWPfFzuZZNeZekeQwLpasYkwCjI /NApZHkRkwQzxLvZ+QI9WElElvc9RS7bwaGyOswC+tgEYR5+UnocojEyM+0N+E41VbUGMdnaJLoN nhFpJuDMcpgMwgfzykOOee4bPAr6O51MPfVttBlySOoqXoEedv2/mWK8d/OCEwpsx1WzTPVZZTUG q2RpNvogS1R+wOwkoDF4lGZZH2gEaSiCDZBJ3GgMlos/TntytYETae6xN/SKRJmHpQSZJ4M0cP8M oBiZpj79ObXNPomfsg+PPu9BFCnUiHVm5sginGcEHWitRbLDzAnRtf0uE49c2yrmwuOfZEzcSNwr Pj02wCIWsxoSEzU7DJlzXmFc8SqRc9J9gxa6w379IF49bOg0cjqf7zfQHNBbUOyT+0bIUA7nfcPo eQ/1sy2IYQz1lFFifCJmVDre/qEMYhyZgpBgCUz6iPHYNzwN3n2Vmr7CQYBZoOHlkdtYFW+8kg/1 p/hxCVr9QJVyLxOFg5xVWw9Ht6qYGTpc0vVe5yWHGFMM2QVH00IJ9dQ4wyP/UU9d+CaElfLryBx0 dOeLBLHUCtmNTmpQMx61z3dTrVXHmcEKAdChLOcVQhxGLFXrKyA5Ho+xR5HFFg8fBdP5TT2FRp/e 7DYOAiZL3n9Ran+3eKoSKIWHmKAuu4NEUznd4dTsQk2v59q2Np/ghQRYOUQXupXcyZvopILfRAwD 9JzqGSZTs2IbBlFuGVfD18Ua2gqfLoJW+svvX/e06wUcEX/OTuk5MfXoXpNONc8ZR4jXA1rTvRjd EMYslCWM6MgTvP/6u77QzYh7hQGNjt5qAuZW9VXlsgGluK71nBz4USO8Se3ewnb8DG82dFht6cYZ 8r9nJ89StgMK3jNRhEEm9RX1VnksYzs1PbEl0saeh3gQHtIJo/Am0jxrCQWUuE9c0j6LN9q+/Gwn hdosFajueRu62h629BKasJcpl2qH+OzH179b2nVrzufqd82W41I1HrMrhrOyPoitg9ajh3p6+q7/ qyoNqQH9yxFFNuVvcNR/oyLUmjMpSUhBsNlddYfkJEOw5N7nvxKv1uu6saNFo/wjnURWcKfu4KLf JhB09OtOGd9XsZvX+CxU0272UQsRYY3267d4pJq5vwM9anMyS8oen5XQ3ajSDdrtsl62eTN9K5KQ 0M5YNcTaA0c7O2vjdmnC+fviscba5K6VWWdbrWEUk3MlnD2mOpfZjoOvGwCQ8pvEOPWpA5e0SyJ6 m9XyRHvOkzUpRTim3H3QIsoBEhxUhDTIdQc6hsTXY3wfv1AI0b9nVN2oATar+rvhaKwUntSCxt7d X0gfyJRKxnNrlignNbwapFb6anNUEH6jcQ0L1CPGVcOJdjy/t7FoTUo+H4rb5DIzRFLQe+tPS5AD pX0q8F3QN6m1Abd6fAWJzV7yTtSwQ/nuxEokJa2EWHJo5nzUOA+Hgz8jjLH+gxsYyk1hiP9ie51j PFRGEc7WGlND5YOtxSMtfHRjQPuM4DNOdvgDjnn/ZvOHskjvfE49apDJjSBdCe6SsHGZyGIUPUVx Ug31RvYnONDEXDsz64D862SsVuG2/OW/9/AVQL013Yet4u7wEqldOct5IHDJf6hER9azi+ATBZNZ MJcMFvxvbJL/ZhvcNpdLKuPAvLVZMhtKkIVcnP1HOi6U5gpGl7r/ekBeaLS1dAq22jE7C37dL/zb h00+FUg/sVlDtaIvEFgaDjxjH7h+hqWXEP/B5gvexn5h+4inFbUXKb+nS+1ofliI+5hsg6LEyP1C k6bb+PP9LWoLIvqkpI8hO1s3l7IGCBPX61j0E4OJfbEYNxsDOamfB+E0btk7Gya7Cq94ev/CzeHg rhZXV/wYgJzfcnm9R0+Xyj3c/SKHenVN3jEZOyr/iUnS1CkubjIJaYJNz6DptyrSV/fUactcLFp9 Xt1qweIi7pVeOhoDAKgms1ZM6TItZJrifACOA8xp6vfXRpkZwdyMQZEJVmuyia3Hld3DibUXTgh1 neMlLiVAFFgaKrnDDeKE7AXlQujUhMcKcnwfHxvmwLQMqR5GrxisONVsnztsISBwe3moFVEfhGAg UfB7RjWstCTaNsZw6dbJRiHtMRWjgCxAFWTQ1DqGw6CkrPj1i/LrZVQOMmQR1eOGoQxqarV0d5EM C1MVME89foBT0YopR6iLgupM87JRgUVig5lBo5VqQWLR9+/yc+mvtiiHSTRblfU+vU2QC0f/U+HG bhlR8CQKEQJGBnK0aGv6JQcvB7U4ZzBKIbx+cNyKJRNlRYiqsX/QxQmRWzTFv07w1hv8hY84xnlj mD676pPYZ/7Zp2I3GrLvSMNyVUzO6s0qBivTOMSch5M+iP2ElCbkRgJi9doNgwV97MoZ2WNf+c5b P+s1CWBB7GObqa17AhCHXcxjmhbzzC7BqwwKG04u1rK2YxWmXiik4ftBwA5+sKirWpPdVxt2DKk6 h9XA4tCzSIjJ8JnarE4jHR3sX4X+vs62fAWAo9Xl01ofkxpVROpzorD4MFRoCc+hQ35IcPm/2E0R RHghTTfnOM5p0hE/4mdh73UDI1bJepnDQCx6B82E34WZAZBcSaHcpAs/e7ClJSgz5xXGjKqtN3T/ jJb1miOooKGGECYClovHR+VnQHMv5ZYwkz1VcOfZXu2YSbTMrrrey+2xAWB6R8/TMJoqm9t3Fb77 iWEdMpAyJx4mh4iwe1UBiied7lf7xdIqym9jAIyBdGGrLgFk58tdW4MxYNEgLWl/FNHMHyW6ivq4 b+NJlIsH5cjut9leUUvTRFXc4rNJzscvTSQxUhvZdGIV3aDcRnYcTLBB4c6N0Gf2hPshxuE21Jdi 7zr5NOWTL8Q1FFX95Pkuq2k4fkwDMHhfsrV+x7pwA0w2FoM4mxrpLYnHSeHc5HVqd2RHfGccth7B JKVFh1QhA1M004WldFu3V/UhbUCPKZ4/ijHJguv9iyMCaI8JqRHZCBhr/eKqsH5JUzQ6b7n1x1/Z /fzkLBzjtJZhGTDYQRE8fADgRpQB6Hn2G4XYZ/MC9bpSYbmNN7vxFxr5msfH4vnXPX2k0Da6Q8ea Bf6eJAP5t6bOOyCs/xHXgfJU/vBGBaZjEgpyQK6LvmGxy4/nGBkiKybAxdU6wTzL8hf38KbFMhGk phnGI90M2WdVTBZ261bE+7KNpBY/MEmR+Xue40UG6o4EJ3ItaRJSj8ydpdecaXPLD28iQw3JgFSe WidMQhrPvfwJRq+MtITbSBxGPJXiQq9Y47oQWpQqcYcUNc8saql6ckY4p1vQTZxG8PcNigj/yzGx JJj3UhaUHfb7dj5wkqF93tL7sriEZ7htClSJBX8tdg42IiKWvVuHiulJjKl4Z3vl5/2awYs+JdWV ZDc1P5lP9ZpUPtHIDNVAbriVNyqfPYkROTtJC3bFs3fEU3x0q+PLzmLiju4RD4eBwcjHjxvMZ4FI VgIPBPzFkq6yFfx2/uqugmC9HWL4LjHgr22JHrR3CkPyNYL3v0yggdgDJZF2po8GC3D2p6yQHilB HfHCteQHvKUT/OgvmncgfYUXy+txf9f43n4CSUuJQCbNZESENSVqVTqiWam7S5M10ve9qA+xpmj1 EHohUOFC5gfygNd/nmZpXd69Kvbv9PSNEqhH4Dn6ARuwM/ZHqO0StCgS+ozM8Ud6P7z9jkhdGM3o VM3jYUCkJVrd4KeHs4BwRt4UWzumFumbZEb4mpc7kpmrHLymTOuBtPxpWJwDeONyy7F7ui9xVU7h kfbO45xNw2owir97dT29CLpnv2aVN7B0cl9uCy2E/l8/BxYwzwbf+vPM5jwjkTz9c2ijE2XJ7D35 o+D2qSowF0D9KtR1r9uVxokNdAqCPhCsnZQGld/xlsKUtIwP/SBmgvvuYYomCEXA1kf3tY4LRKHG 3EDbfO41/huWENtuJOrb1AASsn5Y3mtdLtY6dR9Ql6YCRaD9e6yv17WAc6sYd49iqtKfh6rF30su mu9a+mVlB0+YB728I8e6qYZ3Q65MDyrJ2lFeV9avkvpMdeXENiLoBojNK2xvUlV9DEmQSi4YqXFn y+mjVARnyQFhA+TM+LuFKglmro6Uu/RMRbts8G3cKgbD8HQZuKK7aafm3OPQbg8IFPkAfcW6C1k2 ScBhDlSew3VnE4tulOevfWHUSI9QVmdVZw1ugdURYOxmKU4/cFEk3bhvmSEEOhH8BoClQUlMzZGf 1cobBi9k9uOMLcmV4p9J69x/WFgN00zjCx0Mkk8DleTnVDnRKchB9A1CrlJtYPvPpW9g2G+TwQhc +PjY25xwMx+mMN6EhoMqPwDmpDJAGG+8iZOI9AgWkC9W/VqzbYIbsAr9FOEKIR+lHtAiyOmDie2x /f4uFBss2s6rjZtHwyXRNd6fu0OC7Oa1e4XGU0+YWABnbZnXa/WjhHCs9KdqqTfqAq8sEhaxQYxi 41PKUR2iVGQ4FRGHhDR7PyTJvos/wt2ygvW2dIcxVX5DTP2EKQfnsgHvbi8xhimjHQlhVvPyrNwq jphD18/eN+pZ4PkrNJkQGQncmyAyv9q4MSEa8sWc39AvRYc0AHlvcPqwU58jXWcyc05wD99z0soC jkfrICT6gkhHoAw+iIOFNryi/aLk2Fp3URPeR/ju9Dz2jhitI+STN8BgPv8D0WCEO05HRWtrZd7p RohvMaNpTovchFSJrkLaXzvF3IJPZ6ZHeuPELpm0Nhv/Xg50TWthQYCMYcC8UBIZmZWpYsoe0vDC u0h/VaWDbhwQ7sHyAtCCFEA6FY2F860g48iCLSDyWsX2M8koNCZQj1PBAn+s8MVKWsasj0zB7MQm TRzpYlqUHwoBF1gef3Z351F2JkVyluWs60tKe0EINGjBq/+LwuNTtBt8iLh1w356mGLLFE2auP0a ag0yPGQOOOrHOKhH8oH0BBEBb8GO5EJ/qeykCEjmXkzugxFEl94uORkhYQL8Q/ork8xWdGiNB7pP jnIuuvAJ83uhuXtiNE4LMWVEIl4e7MSfawB0EBNVCCf1HbtIh7dzG0Znd4/jGeb4tinsaQrF8YwN eWRkKOFG32UnzhwN4+txnjWZUQ2iaCCHWspPm7EpSz1/mKWRyNd8OgMU48AUnAuzYn7vAkCB8shV HUN6Z2lz9AHW0ugzgkKvt5NO7Ob7tMXfzSQQRK1GWCbAiwrZ1Ad8Pc0RgT9yyPF7ccsQ1Otv9KQA b/ilmSY4WnbpDN/+qaGvAiscAr1AZk6qR8L3zVSTNKoYnGJQLKumdJFvxQcaL9J/Ejx8DLPXdqQl A0uUNDXnusn6+YxdA8sAgsNpskebS0XIGlWfgjzKWXr4i9YzkEvu8gWvd0f2YRRkLsFBF88JrGq3 0x4Q0tVLQRPOxF/g20Ccw0N/36lXDQ8RujXp2NKA91mgs/XwsZbztUTiI3Lx3/tU7iVGmQfAs6wv tjRGpOuSlb7C7oudVueHy28sNlRqIAyRXIL1jQBfxEn9klSodCCyA0+XjU65em1pFX0JbGTYmhBf MZ56WxsUwGDnF1r/IXWHrXjqRRuM/VEdJoYInpBylcwBrzsKyrO0kkCw4N/cMG1Sllq732unMcpk CAwYoCEZKnR7urwLm3Dz8a07z7WViW4E0MHLdZ7dldXc/c/zQ/K85xdgRlzsstncN9fmw9E73wGf phEaMQhyLwKUOLW/0PSJQBlIxmSXZl0eI2UlyiFdwGSO5BSdYQ9r2etnaNfZKtGvajXpcq3ZSbFp sywWf0XsQR2xsAFUdOZL8t5dEEhmzZ91VTjrXgnQ2GlchdbkUxKAb6mWIQngp4p1N9R2CI3jYt24 J+JYJLS6uS3ha0zFLNhSItkjGhqm9BSOaCoAiOGm8ZMzyJVrNH4JP9ssvtNOSk3isZnK/Sz0IZCe 9YTI8foFyeVHmJrS5oA+VMbiPtYQkgzxYNH808pGi0Z7YcggmbH6IHL8mynLL4fhnAYbNHJbrERC 548s4fiiHILtJWH3qyxHh/0UNkWBUpGpLcqTKHKv/4NEn5KnTOHHMM3FAU9Eo4S2d+WeEHlg0dKj l4KcotQT/ee5r6yCHSLhQsmsIV8lOwXnaamSny2cPBf85pYOJnBNEOZE/YLZYF1MLHlV5Do4lOUU WkWrX4qzaLk5bf+ovUHMB/xoV8XWrwXvi2U64kBpyGcRCB/Gf+PPoT9MsJ4c8LQ00Oa4d+59gaBA 8Uy6eXFYurJ0lynntnmT48x1BDple+fuKPkTHq+4VG+EOJANMd3Lmf1WX+ohrDqYNYEoGCV5ptXE 4kOk1BACU5Qz1n++4qsoSlWVljdLuMbFN7G2tACf0lAH4uD0+zXkTJ2HXeERxhn5cWNt58Q+DvTj qrny74q2Tqcr3JHvV9ZMDsKo2Vi+MInNZc07tQN0VIh9Ls5UsUjCQR7pFeq6dMlKnhfWWok0XxmQ tb1jiNRlf3ClSyYh/wWonruXzOcYnUKdYdL+67qs/m18+A+EVFtH7y0yhGWI0SCfxyuZap28GYeQ stsU3sjF616wdVwLm3D01Fpzj3fK0lOpJEZIQRn71p8SyiEwx6ekji7bCHqZrW6KrLvaTp0K0CQR 7+iWz9l7VSKeBNITTK9QfX0IMWfncFIm+Pp9DuGMhjQ6NjntJ0eLYlVem0xuPasaYC9n+R93iyzb yTMkeHT5oS0jg6BliUDJBScfYu2OYL5XVhVJeoGFmjE1Nt+wwqJdPi71S/yhZ6S+I4fDw7gU/Ewa rOInIRtB1kF8PtakkLs6cdMxmh1rr0m1FQoSbL9VaJUXnoApA5+Vl5HEjKzsnAACbIWyMmXJC06l dGYcuUdAlKDOZkb+VynxLRIXSiRQcWfeDmBF/wGJANzVr8VQHX0otStc3lhtRA82IyCC+oak+znS K0X3OQR2MV+TEn+o/1SNr7BB6MamkQ/DN1wJE6a0IZOU/sqHq3EdNtpw+oc3MwDZs4+DDCPulb8V TgmDkEKkieBO03Po3sE0aBsQUGmytJaRlELRqiJ3kyRF2oo/Klb0d9m4qpbtdk8E8MSU+uT5W48u N+++WoEMYKsrgXRhtuSkn7JK52uuCzO22QanSUexTQcOTEatIksYMvsoG34/rFaiNQblkCJLh2l6 hcPS2yD9aElHmNJwHgX95NQLPE+EWLZZCN67LcOGbhaZ3Pud5z1syptjK6QsBKGOryjvbls/vzvb /e1Iv55Mw6ja0ZoVtOm1S+Q1sQTHCj2V6FfQheLlcr7qFEbqgJmmp5mUeYxE2jBppVnaRBniNEHR u+w8oA0JBD8KlloXRm2JZ3L9jdtmqfoYlnv6xpmEaPbqLIYklxbouNQv7Lw5fiz6DF0OCN3On+oH Ts00FtP1KPicZkwLjJ6Zss/0Fc11jan8aEHJ10Zuy7982HtsSKQ3K1kAOKaOQcEP92w2JDSiCS9y C9FCarJgUII7dyW/Xv6hg9ylw75Mdi+Miersn+lOkTKQMdsVGCe77mpV0GUwZUkDQO2HLJDahbc0 gOVtSOVFwcE6sJ5/oCHwdNCzyKk6see6jI64ZVtl8N7KXACwNq7NM0pA7fQBk9FlUp/oKgKWhxHu OJGeA7EZk+hY+3AQ/hymH+3NDMSv600HqdhO7otpqKs9Y5OuGLjBa5EHnMxMMnNqj8Vr/sHahIDc muP6cjIbY50S+P7x4U8S4M5Yn8zIQnDUFy+CrWlHB9w5wzE/xdlEWgrV026ZkQ5pzgkBAipcsctm uXwEaK0GthCod6Zctxr6brGxRrMG8W9lJLNappg+rMXrjaClFxsfz1QCgikqECo1uN2zkTuDtkyc BIQVi9cvy5W+5NParo6yK0KBktXJWnVFeW6fEEY77WhiSDkpNIx7xL4uuoNDMk47DsMIMP9RC2Sb pYuXoxTFhHx/ik9PAY72hbs0nTD/1hM5SqOikmQVIebceZ8IJkk8QEJPwqFyyRyiG5ltfcKO7iDh MNzr60/Mq7He9bOx7QQ2NCBsUR9YA4MYpeOOy8pc97YOJcvH31VVSPi1M2fghapdcKK30BIWd1Hk GPF8bj0s2BnL95ATZD8ZM0yU8ltBoxrZyt81GXr/Qir0tYf6fuD1ZtjAbY6xfrE69Vcx/U5in66p WVPzRyjCKiq6kHnj1YJSgqYgzegDDJiUj+z8czB+FuyFDkkPDYC7wYFWfhmlZHNQ/p51GBGSfLBa /2BnWT//BepN1CSLI1BCHiQHdcROj4ln6msgJYmBkXtkaBh05zvTlgmy4W2jVq3Vrjds+RBlZwp4 7tGzzhSrKcfpHSzaoKkm2ItHiY/lEKZ/Frut2wzQeJr476TjTWOE5ruCGv92IVpYn/b00mk+ij8a /J8asv21buNAl7bgEPTeGSY8oBV4t32fFE+KnZHCSv2cHDFBHwUtWk72T5O5JpSkh4PSZ/YKXZmJ hQE4tCjkbsGe12SHqQWjwR1KV9DNkMlvAHrkj7nsP236h7pHR/UFciDCpK+uGrFv1WyGhN/JvOMp iCvuMwj2njjCkvtfVLpS6gZAUHRWbm9tp1ZcXFp8yCZoK50dHkFK/RvQlGoWFAu/p6h6MXeH1A+u 26+KygOzNmV15uc70A8cFd5qlVyAp31W+2J5sYFe+X3BFQsnImbtgpI6FGgeU0/r1/mqGukyOYsT cnFU8s7ZyqlqZfHcO1FPGNEkpdVc1M1HheUXAG9V/1ohQRXKckvV2iIA3FWV9zhQSo97gzjAWrVr k3PTV6V7W05uMruND9R0WtCPiqaDdnfTJFEZJ14Tpegjms0TxcEXkUq2wA1S7h2r5AFHjZ+eeRU4 VzS+N8NxuTOKhizWuS98A8Q7NWv5IApeQ4ZUU1+ULQx6JrmFrO/tWye8cRlu60QHEuCmLr5f7KSt E1lz7QJQIamt38Q6PVjUKhPzClgQDQ72HdNRLCvxjKe15TMLbEcbaxCOj2unYolttnk2p8gIbdu3 WmJ/ihqOybkGRNWxGlvpH6yt02qqjr8fLt4mn/z4N+/L9Z+M43O/AasHOz+IqFGQSLukqbTDUs6B MV1AACTUspzAsNjZVJfW/u5smqsv/8SWxMap3px3QngaxHQzblqHd/HdU18CQanpUv0l0js3/EBr pPELLG5A56xtHfscT4lvpO2BOIdPXEu92GPXnIf5aLhccjXTb5iKAiERRlC+pu+T9j8zze+nlPcr F+E8qgNHY2eniJSGckACMfCKvqKXoDXraVw2gQfiYgct0HC0UQMdgkUZBCVW0xe7V7/vabXCVfwi qJd3/qwEfhOkR+TZWGGKCQP86UZnHo/pZbXqQRQrQcLOYQMrZziLfZlOrYUcCjNgu9Iu+xUwWnfV rRniRQ4oUYvx4eZxZLTv6pyvdLvss8K7MMhGsGQckRaXi1UPfrGgGbNpJMsMfS+ZuCdk7vRe0nX1 AAD3hqcaz8BqOztvZAUW54saEh+gVIE1m0bp8Wv9Q7LamAiZ43dmyfhsvTuOPm+PPV1seUX02FX+ jLoU8kwuNDNxvJFvdHbSNvCNMpljaP9UMY/9ZgPh4+U4JU2OiLqt3JrT2q6/lRY9+v7IjwBS24Tc djbVKT0fTu7ke4ucnUreJ713LgN7vPzKQDxlIgmlZctxZXfSpLIMBEaTqpZPUeEFGSzBntrpu+9q 6R2/sC5/TVZl7u4W1h1uIb0f/WkbRO6ybtMDOzQ1qrMAfNP07vUbVHnyDvKk1bfS84T5oucFJB1k TE4nf/69kN01U1ASIHZ08IAnLMCz1X2f8vxw0LVS8hyPUwI8DEj0zpGV3cd67jkOQDlW95Rx+j7Y nmD46NaY99mAQd7Tm8FRJbxXbEtIB6f8TpV1HcEegnKB365R1xqrVohpRrUfjpGZXphPXCpnL8Sz KsEQnvZnECBl87S/AdSKDr8FUW8uDSksDD9UKU1x2SQvRMy62hwmuC36ZYUYgrUlpriWoB7d/2bO MZ2/7C4QflnfR+7zCsYMjWLO75bg3XixKV/CsChvtqmviKwQVX49nw3qdnajZcv1VD1bD8epX7Do Yv0HudGDKHgzNhrp199QczCkESV9YFhgaBWieO1SD6+2QZuj2LTvGtT4oGy3xfRdcpvRjBZfX21L 2evtF8R8cQRHV7jfa53z3weEbYd/Irpm8LbwomTpg2KWbp8mm4/IUyQmtCSrdGFVRNCAkOX+4cYg EIvJ3IClnfv31w5e9ZnNBZIHUKzoqYrZYymbqBiGWDZs64+BHLuenF4M0DG4upLUgufh8qui/0hc /9dBmnsxNSS6AMjOCYFQOBkaw2cu/jJYMhFfVV5z/0qZZ2ZMBguGjHqzygJDAe3xpUqlK/1fP9t0 OB0MBbVO4NQSR2dPgt1ObM9DYGUaG3rQKaGU7vjpFOxUxFgOktFrWW6hLBgeyNbZ3Zfvfqq/gqT8 ElkXvUqWZtnlhMXMZBMHaqXBo5tnFHKp6Hb0/lTuEJkXif9TyOBAtGOpGkCxH6mwPDTvmjdiUJol 9mhWzURK9Y2+QWqBsUzxx3kx3opCNLm+/KI1Yg0RKjvAXGiLMcLAQcuF3aPVYJiz2Rz+XJipvQ8w xL1mj0XD0QygmxYCwp7jsZY4QjclyZHY7NArWMzbKzD47RHXXfXFBZIKoBGpAuR2+ByBKx/aeVIZ uYX9hDfrqblbOEzy5ki03KluUBFE4rmrENu88sBUYiYWK3mOSg9LWBzMql0H1Vc2LqxRnlMiRO8F K5rKpn/rvaKjeGkWtjwAzevT5a6DTwv+G6xdz6ej70/ICAZGZN7QH8cnbAueUV8yZBtGi5yLIK3f f8AGyOOxOunEDEq6fCUPLzavaUdfJK7mkqVSnzuP4brUGZ/iuyhOuH85GY5kh79KPylN3JKw+Lhv FHiOFakRZL4S0i1X7BTWcFk1dJL1krfwr1Fwn2nePyKdQyf6qcnifMmPVdsnqQg3HfqahmLfTz91 zNRmxFMq9bjPkVC7WJkPB+pK4TFlxt/jEWsYvjpR23IjGzh+NMhQvNMmdVfshsaHOnM9HLtf9RYX hn/smYi6HCyTS1YPL+e+xvTjU2ZlbmcgJgIl4ADsIZxSdyag7UwdOS4KqDmpAOrOKOgDxsTu2wC4 olkGS0RoUvnvg281QylItPMPLmCZwQlCURvfXtIvMHUWZxhGkG5XGfMr8o7u5rNkWjmEqr4C8dBh z4k0eF+ERzbHFCasXD3/zJqWnuwKM7IAqFyis4T/KhByu66ghkBkLvQr9lLGZ8x9EcHP1VrYJ068 +4n5dTbLpnpa5viLBxDLtY8hwdn40IcEMaTBbWdL/OJhKWaDUxpmuDmmoXh0H7nzGj3WIzbcbWiP SKN7g1Kur90fCF7fUXr1BHg9yRjDpu0mBGqhZq83kWrkRTeVPlFH/AnUM9FvqAcdGYEYMoqew3q7 H396coc7RIBwXTLPHhw4zj+mWZfLnVT++GWJCVIolzD6UP40CLgZi04Turi1nsHcTlqIJG3D8PYz BR4LBkvV4Zifcyuj4R0q866EHw5TFIgdyafjVjlkCBYrJw6W6WM1qibDiKw07LgcKVgLLtQjjsm5 78z7rIx63vROypWBRXPoVUYzKEzOMrFoBI7j+lF72y+xOe5WXxUAusYuYwMmGauiHqSuwZEFcIdC UBPGMezdm0OFwhkEzt2HztGJry4WuAFANCBPc28IN/oAQGtpCAWwBcVnQi69EbSQ+93dJo3pXDEp rgmb6eEh1OOROKbgJ2Pzyq8UJpv/8Xc5VPbGAF3uZClEItZQymu6pRT2AqrXzKy5mbb1PjFLNGhx Righ1dJeYvothMmlXjSRKOkPp8dJX8cexMpL2wLNMKCUKzRWYQ8+kYRoVODPSk6Cils8AAQb29Dw D8zD6/aY5JtvpuxPtSbyZCZ31RHjHM3aiRAzoON6iSvyCgP3VxOS4ykx0p6dZxm2U0E9GdjxJ3+q ovid9O2fWZZ4hWYb3TrniQifHLt+27IqO/ZTkn5TaoGqHSssb944LuXEtGflmPnyw6U1IxXbPJES oFyAE5+FfQSqKw/vlaVbXq45ESD3gABoDFECHuz8kALAjXrXG0BMW9jizy5k2mvxzAtS//gJTv0k +GseethPGkUqMgHHgFbi9noubgsaHP58v1JLG2Hn17aLf1xIadxmlQtPXOIPYGETWJGv/+lBk5qE Dfvlugg/P4eyNxnRDjWa1l5mj21HTUCEgZXPC3MD+bLcEqw94A+DT7VMEDBlYghJ6St6noBvIm9V Z9fIUO0WhNF7Ohi9Bo/b90v/LPG/vucH+0ZXsbG78gZKpZiaFywC7aqCNfWIUMTg2e/HrwM0G2d6 TF411hANrAEuBUt/crFoSLiKxWXEX6oscD5t1Ua2wOGc8yrD1GwHtSP/kXaKNwBpqK3a8CDw9Mez RyslBscr8DBaww8jqBpdSO6Djl7p2uCiIsUqamk8DJKtoXS1IMYUkDR4ZTy8NbSFneTkvsUrB7qr K2YQvDNC4+oVqaATo6C1LcLxqnmuQPdQUqjV+ydv8rOLji3pH8okqu8crCYMy58Hzqi8UeAnmtjM LqwHZJsdFaga1gkwLTaScAR4tKvfOFRF3+efyngL1kqkqnUO92eUMpImBDsywe5N8JzHNs8EyCGw NMBm4r9Xz2i3LsftIkvByNsN805udI7syGvrqD0nwanhBXQGqo9oKHH2DaW9ltOTpu4OPIRTiABe 64zly939yP8p0Hmfac5D7bsqswjjjmdRTfu0ODmvtZYtQmrVyBepf+/Tf5PLzaq06ZznJfozTOMA qyM2b9u+MkfKhFl0BiBij7Unhup3kptJVbY6BFqPYTNUAJCPKV1NEisBre8QSM2g+Fq6f07eLUCD tAWZ9W67gxBXUd2ObpZ4vOO8KSVDchNLtY8OoqqLeewSd62rawdZ85UT3yvKgJHePW3IBCMo38CN qcFn+m5V3RnzYlS7fq6ykarM4jKZQy21lBcwPEDxT4KR0n42x1HyLl0V696cUzQ7HIfRq8h7xH3P d/0aK9b7Ey6lk51OPRqGveYHgoVbs3s/0BEm7plGotoUr13lu0HE2DaTH0JsbkIK55lvVmtFJHjt Y64dc0OQ7OmWZtspc3CwHV7Aks+SD3qW1RLOx58aJH02zLkoNNoMdMbnYcuXBTr7FR/vHJCYISHX 4l27W2ERJ+1sOE6DMTB5sPntY2kAgTa8CBrP76a+XjTTb/GoXZHteknHDOLY/oyhXNlUznAxZpqb QGP494YBG8zQ004iv3HySR2jTnEipociiSYWtHIm6XU1aswRc3uHvrQml4+13N2kjj5XtrzMgw2V P1v0czcEy2V1ZVl27ZR6Axk7Pvisr0som2k9dN/CM1KUDSthkUhpb0VQeq9vwtFpq7fJ/hJ3FxRf yRHxxcogbyxmsPLRwWOI9+nssZYYU60QaWyZs9hTEHLlwhTr8ovGnFBkKxK9ZVliV0bw/J1igSD5 bXSfwrCIZ++M8zZ0G66Mlb12S6t50mMyvRY8hJl/8NcrC0jseWNJbIj3xsjE5tZHRRWfuceSc0lg ZWYA68HhdFkagsfYQkFIQU2kQhXCdllTm+KxjrHZCduAknorm8QbKvLoQTqNhJGvz8eYq90PLrz8 d543/1ZsgIbJH/ah0I77h5f13sGPyJO/weeTr0osStBxTjQc0LSqAmVHNw4jlyyt3grAa5J9+mRg IwEixYlQT6s9jA3dIY2NFWzOKGEMLgtVtTiyGGSZW9rtplrUVNmic1jilA1sOqFqKBPqi2HjJ9bo QrSCRoYxJ4E3Ex1GqH+tlNzi6+L6Go57F81h3mhN4eOdc1Fli6SKmcsDRg0k6H7eFkjJw2sGXZ01 N27jmB6siG7gAg4mSyg5pOa1cmYTvF47AXq5Qan/+UtCq7Sq8oJEaeHT/wzSy04khLhj993c8Dmm dPEYoYl/2rN35YbJgcWLAomqw1KsxyT78Zu5O0YorzMv9nUNWJ2tcVK2cVCIdV0CsyMdc69Z5KUK SOcLtctYDSQ6XYY2KZmxhKyd8tgtBimmtEuU38vbgECKSRgvu4AnhjxH/mopnTJGLh6NsWbA8r1A cC/J3u3hkrSTA0O+O6XL87e43LD6UfHmzITUX4V/2hF70AQw2C4eEbxTZ8HPO/GtMrQSoy5DT8fD pRhcyGXg+B11ZDthLsSZK/PQ5NRxUkN81W0LQjUSW04uZXA9rK+/R9om4M2o8OJAEu3VUM2u9ROx pdprIozDfJWAQyEpbnRxWYD6xThLrwehxzrOceKO3W22BYmopOUKthr4HWC+Hfc95jdmRORLmGaT kj/12UJssOM5ISyslzFRJVGhJR+ETl0i3761vOvAx+7ky3reIfUvgQVBPnHLrO6gAQw6Du2QqpcO 4xOIxKiXP15OcO4xZatvb+qtACcCm68Wh52noBFNvaqvLa7e4S6iNNYGWr6aUmejSO0tUUprBGQQ Ga+zJAI8kj7QmU/YsFspnAgRwZ+S6jC5kPXi5IDRMPNR3oGEqfEfDM0aHDcmgosrXVLBbOou/KFJ /lTwCagAnmgs0Cn2nOIArgXpYuTQlzneuNWLLkA8qF28W4mE3W+i9yCj6zPe6VGpdg9L01z3cfg2 fOsKL2HHOMY0m90O3tmXH+GNkbs0Eu2GEgxNmm/XCkS5njdlJrbhz7w8OrTX4WfE/n8g9AU4Q5td algMnSIszcQ61Y3gSJt+6eyD5KE6UzA+rDoXBl5xCyrEungaB7qvR1cGoUdaKvlKIhvYVHAgufRJ Uzhgfr4G/sgPMCgVkxGJ/37ejV+K8DnkSDFM+UDra/Z1aQXcklG58p+BYXYdUUEqkLyWdi7X5XIs MfhC1BJE38icifWezZzFW2/jpKI9GV8ulTq7xAywt24TxY9gLlyyXmUsSO8KOHqEPZCrN/kRMBNe 7v00JDYPIjtNAixG+55EZjI+aty5QbnlndTFYE/dTCQsXgslvOVCEt0ANrRvgSzEvtDKM7PVc8tc LHwaktmyElamqYRyW4N9JQTs0TpzndBFpkbk3b9BmbCPHjsmvmr5xf+ZAoLejFw= `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 61984) `protect data_block CZyMVnx/yOPHHnyfAeG1brb8pDDJTPJEhPZLg0vZdzWDV7fCt9A8XspNxEJB4ahodoNkdrz0tS0q YbDBT80PXaO2Hv5ABxjKtPGDKbmygV+wuY+FwaUKL5u4fbK74C8oEhLSW7QppI8pnYBErBi05MV0 yh/eRXzdaieOqKSSrVzSni3AEXU0nponYkydGyuSjzmeqbwMNvQdfGghucEIus9GcLnVC7VKPtT6 cHN2eu3DEj0kbI0CVfgS5hwrqwTATacyG3c3RIBO5InTdYDYN7WYlRj3qs/10UjXKKGmvj5LBeg8 qqtnQkU2/Vx+RTpq0J8Uski6ztI0ep1Ry0T3dQQ3TDLfwVtTPMDawbroR66RWjczLhREv21NbPCL Y0zXBGYurC1GNV7DutMVOPCMtgyg9RgvghFSZzt4Jb65Or4EDBcgdwU7Gj34eM7izvQ6gAr1d24G l4Qk/nriT79xz+JsPC1tkBM6ofaMCkxpiB9aWu2VHoF3ACqBq3IGS3ZqIMRzUW3BaKkBqlNfVbrY DQfFwPYchAn2Ox37pInpCjG8ADShNsmL9gGCo5HKRmhgeWG09deYtmNndwm1uTRa6cLWaVvtUnVU aYbQ+DGWwwfRZFZFPG6T5Ju/rgju2AbOJJ19z42FmRHydP8zbPlYnHrWYUnb7omafxQ8sC/oQvKE 48rBQahUBDfI+vvDrgBkyxmLB9999X1jYAnnl+H6O8bzLSJThQc5NUiN0XLaPOlbpazTtoLqsNBA GIQVghG7By7ovFAh0dM8hlTL4RG7cj4CnGezNBjsoGlgbP04IY+3j+F9oYUgo8zCW3aBeo0jZooC d7Z2Dw9L8xQ1nQxK4ZdqciqTiw6OxqlTge0Q+2ryPNVzxXiQItFNSs/3SeHlngjsCeXviO5kWQKa f+/DPh1Zih/eNvTeU1SR6pDgzSSDFjz+SnMBzzaxQ7otRij9dOakN+Kuk0tcBp985EzQT0fJGfzH eVqF+YbiI/jegMH+QYYGA7yWUYk5ddB/O/KV/TvABQM0HCIa8UT5KjMDjHOFxN6NCXBQz0vohx98 F8TaI2vQwzTu/PSyuv9y6eRmmZRx//NIhyiuaP4N7XlHgtVrdJSi5vJJhgV5vtcU5G1tyJ3UF68k WoEIne7lR/KVe3Ymlmd8++6bW7GNLhvJjH7XkYHuhPowzQBmc8T8QN9pU3UDByn/8MFU6hTQqCAU NiVP0c8GReh/yVXtO1iFRRXjuQvtzDH3310D4UgVoMpcklXXq5fAtYkiCiv53Ju5kmqC0ZnG+Ps3 q6aiRwX1F6CM0Mu1R2hGajrmj5I9kQRpYOZojBDVWElGkF8hcvCoRh4DVTz/3QQrJEwWEGtVviz4 JYCIABgdB61K5RwQWugb4HMviWfhN1CeV2jj4QcsUokmpPQiYulgLfvY4ptgJK7jt28ro73f/rYf FFIBreKwsVUowKjS+BAZCCOBov9eYzYkK/++Z4UeUIi/cLMouxtNMpxZZRft+W0qGcavc/hCqAP9 3xN/RkXqmRNDa3zgPHmk4KcMigCRwn0ZVEb1N4BSvGz/Deksu0xHHuHhSqyIsuRlz9TOAp8b95QH 5yoHfXmE+P8SSH7WKxVFwdHomOPhylKVxmhLd6SNOfVEBEzg+yMBzpU5FED2l2r6IEr9vcncSPzu cCxdUDRKuBAsvqXw/cvsN+SAVaLNLrN/VveLnJylPdY+V4EQP2qXw5lOYVvbakQXlCM5nH4DNhmz q2wJgDaUecMWt5rEWvmP8pqZPjAm7q5WGnjRRbPFrJ4a55ZxHbFZiCPWKcHyiDWva60qY9qpMzRX Mg9KQPSa74U2OqkIE1YGvMYcep80kNjP0pO7yZB7rR+ERewoIWmzkAH5Ta7T/8vU3rLdS4YxXabi bGhynnDafx5GiPGoUIrwhvVOq7eT+rmFrbizXAjGd9+7JRgi4nhBPEVv7XXXHEallB0Rmmm65d1X 2JD1t5K6593IFsvwEZPFVXQODmrZ2ehAxe6c2BDYvE37s3BxkZPn96veSVHMIFQLFRdXEJAZao+w mgDU82bl2YTpBdG/miELK1v0e5l4xwzFfvkNkvjkt171+dyRK5evZiyWRqq7h+0HgkrkLY9o7DVU seE6XZwsv//C/2+P6kn1nE6ExiEoB95H/s6Hy6ScbOjj1wQJM+mvDQdiDH/AwE4CruRA10xc8mxB 1gDYfeYOOKB9xqB4DwQqSUwI1iQrlMGGASSXnppEDeGS1DK9vc19YuzIrkwxZLbTMdlUMKIVqBCj jlJiLz7fvOanM2xU6jyP86o3EIF3SSQRuXcU0bJgB+ClJqdr9ctyHNK8+N1aFX1C2KPa5BYDVh/7 20y7VsRbsjD1fYvA54kFEDBOmBmvM8Fs9ocfOLDxLR1/UqiofVe4NJflpkofRA3MiUnUd0f5HYKb Bx2niYN7TYlhzR/5rLx12oM5BkFhYytT6SgcVnqA5j5NvuS6NBIl9gRBlL0o39dacNcPyXq8PszM yDg1AWzL75WkxP6VH9jfs7Y4se4/nn7tT5T99fvyiT4+8RDb2wFFnZ7Nozcc4LEIoS0i4cGfpKIh S2XO8qCeAHTvLHQpRgwZ7+8eIbnVbibQY+6yg3M+r/qTLabNnJnjsFlG9F4yEPDT41GYab5NrYxh rfqNIChWtlbHkpf0HMmxiDL/MR64N4Q/xfFvpqyVct27ljOema5iGExzvZiMPBIwTaQpxXdc8rQq IoYWdvuzy++848IDJlbj/VFWmKz0SWJn0yAVaisn1TVi/dK2z8Aq/LIsc3hWUMIb4j+ZL8RzuDhY VI5CJFKQMcJtu50w8ANFb7Tj+eqnEXiGxkIe4s3CCq0pW2mytzIeuFPtUk9opo18ucy7AMJlWUT6 jlIrfKaRab/dBLnxxAaYxYoaKK3qDIn6B65yu2ZiJmBxI21fxMinRnIb6a7OIgG52PzIPcxp0IL8 zSHkZvVUC63sc7ddSNSrj/dhoVwDvWp84GsQB8Fo8BjBdqfFYBXIgBqqsQ4ToEGOZY3wan32wi8j QwDgJ8WE5UpQ1kKXfvlSdeFMBEw40STYKbjVR2GFrrvc/XOEaMhlDuomnMQebzDDuwppw7Coo4I9 3xGszSHgJSRVaEV3XaE30a56FB+JWNKI+cnIFPSxVx4khZmMufXXbSkfjNqGDcXoyg7WIjy5OX84 p633sqji48YAlGzGSMt3vJot4gh/LYtIuhbI647Z/aHNio+1XNguLSztIvLYM7YaBWpH1ikhQr1L cgeGHjCmmcIkzJQKl0iEFvaNTJij6WmU6QIPjKA8T8V3G0j+Bgv2Gm0628g3t35zrd9/MGK0S11t JcpZl5UZHIz70+IL+AFuHU2LH94Z2GbV+CeW7GGuy/FctP8gY7nYZz3Wxos5up5/OkV8XyRqs7E9 2ioWySrKaGgCV3WwVWm0ZIMooIivkanZk8r+O+yb+eopMEBIGdDsXGrBottsqgdNpEcNq4B3njuh 0oG7qxMZhrhIKySvPgkFNlM2GV0OcueZHaaKYiEOWXUcbonzWf92c7b78XAmBdOsUDgzvQg384JE FPfHRWGEuNqeEXi9I4c+AFPRRwk/nR71SxGObB+zhkvsi90xLZcXDpnwXw07tDR22qqrzP8T1tY2 a7po3sOvShxloVPIhOoEHbsL/selt9uCnn1myf6o1ABwjLXOf6KNZFbIiBOs+ehQbEhAVlU71Ag2 mW9WUgx1JCiya/c0MX2v4Ilm4MNwp5JXgLVOlyEwHe2+2myDeeKBAmJhT/Oaoqvd3g9aMXXhsgBr YEQ7vuZYQCSqWdhr0XwaLFpOJlIDRftucBQIglSbMD1Cv7R/O0rhd3KiphFW+g+QPLVkqgxcls5c kJATCDSK4g4UdTyuQa/CzlbE4LpUlBwnoJD2y3mk2VwO7wCuvN/wXxh4+vJTzYnDMFLl90jEplnA ReDGhJYHOolR9qQIMUiet1Ojv/1qe3iPnkSJmR5Wj3gvO69r8b4thzU3mPrw9HPLCTTn93507PZk jJ5Fx6jIZ+eSQTysq1n87uZfvfDv86bJ8Tg5aBsVggLezonSYtnvIx0pdz5fB51CDL56KMg+2NuS rRKzCBYJjvE1ZfCFgEof5gCifAArKSLQ65bh1nknGbFDa7s7Hjbtz/RK5Z7nIKXufm3eyS7+ZGaa qqQpFtvlbTrF7GIrq85Solx7K5ZEaBtx58S27XYGTDvd/B24vLNhzyYoGqLi+GlhTJMpN2eS3Ari ZQh9oYMRCvPoG1uNKOIac/xe0zuT87x8101Xj/xisVA0SUUzMLsm2g5mWjfYCf6joV9Z15dL67Fx jRmDXHRUpY5vHqcxH6M5tKO7KB43bwQj1DDfkFrPe6sI0U/XYCtlTuABU61IqMi4YBltoNntNjkk P37P1wdeH1tb/yw/MWgEtGzw5MFIfibVeZubr1OfTWmTXguer1MrELKZrJjogQg+dMOGEFHCf3mm iwLrpryTu+76viYszyvThM7CgCVj2McaAmmWtai9nGO8euC9ap+CCGbjooZrUg3A9zQ1RfCz3THz tfUGfFiBSFDr63sM82MbaSqCWO+pDd1aJsHR4oS0h1zdVKBfRNtjrGGdFbAY1QEoVJkzDhFc29BK iegSprUGzSaWqT4kJhGETPPDqTLtbyNep3fR9fsAfol9M/6wCTwVhlYVXPyhlmdhKkCJm0zsq736 W5FbHBKKSONkk79uLZFMeJP856Tnp9LJpsMUitzRvK+Cu6Jgb9RHwpjCslrUoz5KB0rH9so2axHY 5PlkyVAr3A69kLXrCpggZ7SFKzhOeLh+NQQoqbEBMcHmxKinXwhFuvzUYJcxv1Fr3h1BjN3d9zA5 YNK1u1PD6td6OnzjL75wnBtYRVJtINMUb+P0Kef8Vn16cosuM9hn7xknYp77mmK5oYFUlqTxxkB7 /XoyOp4b5/8g1UOMMoH1nyITXhdk9AIFBr6hAdiWKJfN0Lnu8zSvDX7aDVpxkHo7+MWWBkHnkh+w GVA4NPND/9n5xQGbQWc+uzpEPxqjXT/8FnRHj0PhNON/EhLr4G0Z1oKhyg6N8h+5lJZYbQv2UWqx 1tXJ5v24Uo/86/qOnpZT6pSJQOosCnbnLQUnv2xqFrN4MyACM4sBSfZ2CQQQC268uAX160qkB8q7 ygw4chPmt/R1rUVqaZ+YhAkfXYkVlMHwPkW0dq29L5/7mI39MXYITpDEU1RGQSrkwdocEAzLjDTj lTjXTL4sVm43FaZV5nhYFlEHSIRZd9DWuEqfUsJC7AcnyqyK2CdpBFakMnqLvZTxWGnrdPllh8XA JyMbQVhkm7zGQIWbvQq+zoWG91DUUXxAJLEY5RD0gFIO2mrscKfFAPkSoq80vD+hPEtOGpdk08UQ Dv04pJ5c1QkHiaioe7aEmTDeCTQIZo+liKAtKp4e17PwunLRS0Nok1/TxNHPaqwqYSA0lQU2T/2G 8mQ8fOGe4XnXxJ9FW+EQNjMSja1RL98+dYxwLxygc0u7tTGTgVpOwj2/iJxy0ArADZ7kJrJod7KI xY1VJJt3IWwdZLZaEsFgBKV9HGiCvW+sbqnBpEKUrFAA433mwC7VkfkDct3VUfBnuMXsRoKxGCHu P6bZdtZp7SiyeItrN9mfoRMgb4aeE+S/kpyG5voZnWZiE1L71L2XJerBMNqFuIkhAhEUTTnp905g 26CG/mP4mNbghOAnEj90AMZm9JPg2OVokMZov760EwOLfyC5SIfzbHlsf5E+nrdfG8jUdT9ZsY9W IqWyMc3SU037B02IBUYEV7gu0LZ4kaAmY/CRd+b1dNAzo37KlcOAFH0bRWp+9p4LLbM+BsVs6gv5 8d0GAxO3zHoRr76EfMG4VwutdASB71ue7R4zRmfAQxbCZFCRP5PMJoT+ODcFXfklpBw3v9D6BQpl JUoM7wd60yM7Jpl8zLYuqUlfGyl8Jkppkgzs2aTKNcqSSt5Xdceqg2ZBl0w1P4hF2lEl1rpSvhOZ 9uATt2B8Eeqy6ZD0nCfJ9/P7+l665KCg1Zqo2+zNHuaFXKclCOiV4vWtV8Cj2fMPUIsdFdbT1rqZ hCLJ7E4osmf3IMHZs4USB2chQrn+UfHnsZZjBuaFnlMjeVm5CkqPu6T5RGDO/LtyyPgN7u2pItCc EImxGXLR2gFFg6KFWU6K6wkepi6+Fmo2EdU/yHamC0Mn95j8KDWwBhHYqMP4xI0rsS41aDe4U2xl 04jevcO/ySjnRJ3xeNooE5KT9vUZsUjbzoaRW9GHguYSaGUiT4Op+32piszuRzuIK8jFkNkOag9Q VMXu+Ng1kgzJ9EhtB9yyxpUwPbqUoJEYlfiVSrJH0vrHrzTkpERoN2ntj3xEHz/BjmBOoRasDmts vbPTGoApbbVjvvS+wB8z+d9v1oC9Bdl/RRwjA23RyuIRwa4Z8UBhN8XV4ENjKPr3F4jzKIfA12eH 4C7IZYDlxp2OVxRfpMAAoCMLpRCeuNVMyztivCD74IHtOpsu2d9sftqFOEq5521nrKzbjQnCQ8bv /0q6FIBMsGyh+MKM8ekr4dmVcUV7IDOLeDMVRZ9aZCcViwXm2Xft+Y5Glm45WFoA2VRXxNYg7Y38 bKjIgOSTb1Vj6aLlPP0YdIGcMt0ng2Ydza7+A607ikhtJFn9iDk6mt7Dfcv5R+QpaXyNkNSGwAfX ppepjLkmNUKNRzj9P/O5EcBgHDPCSyF6lIX5LQWH8EZkqYZs5dfDSenvzWlx6TDtQawFoUjzsh8z A+25XLxKzAOBeLdgntesJ+pi6GcEDLp+R4/IyaUOLAgIWtBanB9cMPoNui/cQH9zbBg80afQ4Zp0 Woib5oO1A0sVvwnAHXG8h6x6ExDecqvi1O3WZfqf9LFAABUSD8MYtIIqMKiAelb8M142rNJgXtjU JB13cx2P7yil4HsAVClg9MYGQPTt9jSIFVkdT82HRL8+bL3BQFKj4CDkR1BjX0zaNkJgxHiFnIwZ eOVqb1PePasHdBbezTXP8A+j3O2tNjtqMQJgWzHGbt1DvNalpi7yM13wxeYpP8Kz+0kVQ76OZise Q7aPZ25gVHGLiTIcm/kjXj5sA210WTPrpItlx9WpzxpTgOJY29xfc1KcprPVNy4cPW1GuVvyXNl7 lYGGoe5ot8TilGCsFKwitAVBB9mnN4KFkdR/1N6rJb4+HOuxKtBX7ptf/vsQ3FyD2aLM3l/pnrsB CN9Zgh+NaQE9eCaoeuNE6YKtFw09SHpiJ8iH/1w3GRbMY0Nf/bfxGgzxZLv2Vt4nGEmmSCG6qz9O t3W5dl15gA5JlWDWZ3xVvll16d4Kpb8gsqp6f4MYA54ANf7dnV+jrNFXrf1TFIysBuQX9fg8sqW3 V8ei2T6SML/ViQ4O/BYQJdg1mZq9/BPnElkjIOq2iziI/uGEMLPZDyiv8dGfu48QCSOHkM7PnQh6 EYtPVutx5O1rqv8HYyFac34nA69ahic7qMf4lStIuQT+nSRy0DqImFNplvruweadPlr3qiPzWlVi fycQIvzxVH7fRVB7cYarlg/4VZbM7Z8DTJN4zK+oHe6HAqMkfzqxhSeZA7v558v7avGIXGaTvHCs XVfXwk80DmH1jRc2bYbME5fmBOD98XsN1/u4rITt6ywhictmh+slyBzauHK+d/5kUP14lt+Ho2yr InNjJqeZ68Z9hQkL5aV+VDrXDjUswGJn/qPSJXTiRjFmrjIHWk4BrQoOTw+f5PAi43FeLAdUm0Pi Tk0T7KlPTrtv0izTSb8zsU14WHRz2t1/SElZpxfznRijwDEBHPVUNshZEqZXh+32/VghH2bgvj5E /xyReDhTPUQgaHxURLKVvj1bNVvy5Ni/rJWhufyHF8V69/LWdolwNQQHHmQsKrO7tB/9/HwNbvfh FzHSwZH73JOs80Uu3AdsqXawoyEU9mVsM5QnrMCNB/V/DOHOm4ZJrydP/rP3r5ddQEDeLoGZDeLG Vvl+AmawIrs6CjgqiLS1Kp/RzvZGMg1/cCIK0IYQsegoxZ3ZVl06qZscBnLLg2J6/bQKlo3d35tJ rPK6AePXKakSVIz2Ej18v7p2jkMgLq9G2dIN3vYcFPm6IEQqJwKyfJ4v6uwCoU66o6RNXMttSniZ adC8NWHKVowvWWiGs6F6nIam9TELpqz/oYAZEn3V6j7xfWcx4pyHKnfgkVXIBMJM/TVQEWHpGUke 019FsKtsTNf8KtIVylVJrNoP6MuIW5vtam9RKFSrvyVUO4rPTl6dmWtW4vhGR+HSJaj22BMA0jam qeWIW8w7Uerhma4bLYm2CcZiQTA4XGwAffy95BMndDuNPkiuCQ1ax80ZVAmfwPI2uZa7AzCZheN4 74LI2ajDeuvGLNO0e3yYdoSvUJwS1IJ4EfXQjrhJrjhlYrKo7Y1naKeEvI8t1wyOmcWI66RMC1xY wMLne8EM40LgRF1dWmswDY0aQ2j4HGWuKltpHQdFMb2OSrz+sOZ+SoQxBSYLZ2+NJQtq3A1Wn0HX aPS8ZDtB6PHm2O6+fkacJzsgfN3FByMLnSKiI0nYo2MPnb/o23CdN6HBPx0nw93Foui1WTwok5su S8Eo82tA8JGGAuPacQGOoD1ls/YHGq/hQDmcnAxSKA4JHVT/+HZ6KeyrnQxZg63ax8tK+H1JSJsJ F1iUaSGvOXeOJBhIR826hf5FcHGyNJXq0Xkp42ugus22i2kJsDirPV2Ys/xU/kmrS/Jyt8aPTy2g vzZoSk6+jv99QIYraSJB5UlVRJL9FyIf2B+VnUJkVuX/gtZ+hCHzPPir7uEHL7G4akcC/V6D6vva HyobXDfFPbFDdR/1jBCjoaF6lnJy9RJlp1RNdPyib+1BccmjyKJAFAPC3fQ2vxToju79HUkkgcRd gd1i9Bm8IotOl/2Zn1SK6cS7D6s0VE79X3GYbao9nWJmxwyStjsQkIDEc7jw59K/aHrQBtXIP2s9 ZA995mi9dHYxm8co+Ma6ktYIfYWl41mJStqPYRog63bTCI1o7YIFO6NCiZoswptosRGGPTlh+Usx hkWtNQt3fsa7XKPuwrpe34jle8Mw8KSCqPoAt5n0i99M1LJ0vGci5LjW7keT72ZeFlvGMA4aO2ME gEIz3L4F1S6+od+Q49t1kg6B5jXU0UPrVAnkD0RUrHYzH+AcTL2799fTLFkXfkdaLY0DYH1RLt+a 6679wewe4wTvA+txL8mfvVydeLL4pXjNHymnk3TBWEqfK1+cs0B46BiCeqQ/DDlwZXjWbmH33gH4 wFcWH5Ak5PM/sUwiZRKdzsV3X6x/Qy7K4dHuPeSmshoV5LWJ5p6jExY4vmZFflDTvQHVG/H7GXuX QyVK8H9p25H1AM6eMP/fXorugo++8S6SVUHCBbv8++nrrv4M+p9ZaO7yTtptAauqFavkY/1CoG+/ UlQo53kc12ecwg5cK+HY3DdRheOXNSY93n2StgZdKVApZbdLzIQZApWQtIT2Wd3MLKSCVb7EAnGV 7PxqDNoEaaU5NzBNYgAwtd0W06svRxYX8AdWQq7++dKixqja7QPuTSRU8f9wxabO2bj/W8hd7Nwz gwgocM7fDMUbda8u5xgtqPKsvptWusMOl0huP3HlFIfwH3q1+KlisaZoAkKB615xr8oktJY9mXCo wi4X2qhH8Uq8QEXrfIj3ZUSfA5eX8U5nAFwtSb1GzLf1ESacNjP+pCBHy0j++6vzeQgr4/Wz8UCg ADK9JO+8KB9f0CEAq2jL3yCaBMfWJPhr1DTYSQKPIW/n9dobL3EeBmWraNQIZUWBnq7H/VezkxK9 vZAgVA39ezlPB92VNgsHvrT5MkPxxmEiGYRRPGiStd4W2Wdls7610NaxotrmEy6B9ziPYR6HNcAk GBxOtbpaDMMR3AG53M+o4NgobE30Z21liRnCgjlTUcVCcPdZgJyY4eYwKjzAzbpUppx5p53u1YTk ZCRjzeHL1lCOsHZJ0jfp644NJzG6omrzSQr14rnXqGlmKQGDLMwg8qlRMuGGZBCyzFes8iTtRMD8 BH0/2uhrH9CDP/mIEQfMyRRUcv6BQYtKeutnbVYQC1+x4IvCiiTYH9ylXLW7yITeCS3+s3gTi+Ul TEotS/VQasg4IVQUeJD6jdkpaE4kjZkdGbv3G6lx3McBTPebidbVVoqemj7aW96lGaI+Rk10DjWN V87o+3VHMrTiQ23KtCVPAEi74pBPP5EVnL4IdHNs/ABuCvj45X07FE6CD7hzHEmRZG0u1iZVS7TR ip0j6VizEoaWDABEcqIQIuWcA4RHqz2vNIEVcrercCoQ6EDcFVaXe4nkYzd573N9DkoRiYOVixjv b/tjwgR1guFLR3taCVUmUHfa046D3S1ZgOJlNG69mWM53qIB7NLGhV33BDCmSfKs6ODMPFYWySjT NTpnunYpjJh3UyeObgq9dN5/y0HKEmeWYcwP25RmCSmGSpMXn9rMHUtqZOFITakV/XMAcyEhuo8j 2KNxn2hK7qPDdMN5syHfM9diEpCPODi21apFgn+Pfowa2PALHjKfGpLgzyKX7aiOCfmX2UAZkB7g tlywj5GH/4h75R/hJNHXoTjrOMNONDTVfbbfZGFQqHxByvGowiaAs/CWHRdoYht1Yx0U5rZOjS4q dUplaDEp3P/G6WY+wlviHZCxyAo1duAQx5FC0g675umFEa8onmKArYYIMRx7r6M9Hkzf5R2XMsnJ JEs2pHF7hHgkbe9dRjUj1MkIaFOw8RwYJLcrffCD6uwigb0N+tv1BPGTdxTPgk4UgVfQi3GGUMLS zlbghkEy4UYBMUDx3iwbAReoNipheciy326cVbPWgAGWnMvDFUCVidLARWFtu7D2SYOjYNKIi3cQ QZJQEBdRvJCB3WSKDPgl/kg61OQggWrnfYvPZK9EgFZRVZ36yXOveC9M4lw4ICvgapMYv7QZO5Bh sWToo8Sc/j9LuD5UdMLZvYHOtB3NFtS9WERyFcQFp4XLqflpVHFhnX1F1bdJLFuTvf2xoymtOBYB H4iUhbIg+HNlD0LZ2+BPIqkgEiFeLDAb7yjHjDFyQ341WM5ktH9uD+a+WLW5zyyDlQCv5+sxDoUk ceSQQUhls4SZZwZ4UR3O3h3b04RPAZxOaWWyA2kiez2KEnzU80nKNgQkAenewdp1zhAlEX1ssdBK Q2snzjjEerW+IF5O5CYtYxl+v3OiY69v2BsipF2nlHK/cucHr8VpokbQSADEtOfvtjiNAIoSXiAL VC3mLytHvgNhMk+3lAF+4TChcdXc5qBwU4GFhBX3F8HgHBQOVAgvY+xP0rpnvjEQnomZ/7mdK+fN RidlwyQicgjkbvTG5QoTAIlWDLCNmPSsI7FMQ5AW1ZOeKdzHyITJp1bD8XXSSh+Iu/I1Yx3Y+0L2 2QEkUidXJMpvtX7XRZmBUNqr8U6z+pptI+LeLhC3TfDhRGQqlyZMGKs9prEH7aN3hzc47m+KniHS SRoerBkFkm1vohm56YbUkzulo/M/RIeGqadhxSsaixyYBDKX5KER29b8erHZclmT5jvuQkV2KXyH HzJzfrLDSrlgbldsVv6hSF8th6L24CLxcHaRkIn2AEG8mZ01H9IA3uBe4AgOsH5U/T7jX/0d0/81 3aZJCowhZiyhb/c2I1m4eKyVl40nHmdC7/zJXxzPlntDgoqhqhfsF6FJTfc00h7YCCtB/jz6Si6B zwt9RyEpRddfxGzV7suHtZySQg0pfReLXIDG/EkK8zxl1MIXdZaaWbo3826uBM8+WNvTF9mQdllO 7WpELNEQrFN+GJkmpXgW0kmCjMDO4edRZ3wYZ68EvLahhZ1/gsjjfehG4wbhKpCwqvM4F2rsBHFG Fvurom/Txdeus9whFwWkHxdo9AiBe3PiPzge3givOCA1kWExdDUsPy9wmD+psht7Vw2QaGexM4xI 8VMiCpmWhM96/vofVUn6Wyarxxn6r1v59+9hkpTg6hbxoM+0iiv9LqXO8KN7n3ttuGZ/N/8fyQd9 duXNzir6DrUrVbZR+8pkARGfaGcBlPdY6vsF+QKXk29MJEaGcFluPoeg//1KP/cOM1dv9MCjb5qX hwdLb9zNjSMLcGHHs0VhrV1XQUtvraiZrsF19Kl6FMIjtujLEFzBLuX3vbEhjVqLK7Kq6jHM1Lma K7PFKX0CnFINYr9G6k5mMflCGWJrMRec1KPVT4eBM66gUl+w61cRSJDnPJ8DjRbSY6dVEm3kn7jd T7U+CBtijextfv48C4eZ/aEq65s7s7YxefeA4KWKpCdN6yJwVc7ag4q6bCSpdFBemhYllTRBtNvt Tz3Hl0bCWL98DpeHudT5TOrsGJnSLU/G2oc1fs3T6pWe4BYMtOvfwWPQaoeNOlsSGCtGAbYP80iW POk53V2yZFWNZ3i1b4OBCwszEu+URbu/F9Eyz7TweqjAOyoRnAR8c1rdjgFgzX8e5znnelIA25bl pl2ZGDc0wcvA3NayAqUUc5ptqrqtAZ3woHyT7A7/PEh+MadvbZkBqlsgz72fXMfaPQg2gXpJ5Am0 /dkZGE33Kc3S4Ca+hCQ3o0RHFVGi4g4FLdfpfmur5b+jZgs1v6IHPxcIifYfCZ9mbss6MIq42qyc K+CyUtWm7rhGGrnGNNIVSgLDVl52L4dBHBiqKykJS5M7gM1q6/HYfEniVMb5b3xhIRwTfWlPB9Gr TvcTei6ht2nk3n78HId2WouB1tsNPxHKlsCvup22CYi8IlZ6ZqgibuPZI17hUtmSzs7j0pN3Di2H K13Iijw8hypskSb9B7bzzOrDKmxzJf9tgu/R2oYsWz6KICI7YJJfUaH+RmtREfouj3l2HLCho/N8 UBlkRuusunY8OHwT8TM0Auu0rZ//dGHSlNrx7dgB/Ibd5PCJgpXOLoa116vidEN2gF3l2IaRfctW KM7Yw7rJpxwHv+YE/Hlij1qE/0OtiG7AfnYv0Pb/L+cojR68htb+8vONriLsL4t1noIsK6GNFygB jw220Q5JOwwqAZ/4cQIN6eAmfzrSmLoEWDosE19LRt5vb+7sRLhe+91DVZgXtzQDi/MQl1csafpP ahEyAikY92UWw5jMnMJ2WMAjQ1QYb30yTG4MCQKvtkQ8LI/+n7ZnFuQwwAG+jVgsmkzQ20T1l/wW 9XMk6aVD+hZ2EbSGCF1ZIo73JKoKLFISbTWDrHzMRKg+u39FbyadJkFJg8o204FUb3ZmAEuReeYw aw9iogNsfvAksf/lU7vApt1E2eQ61QeH4TpeiGAr3gExeeSnFoOhRwtcXAyVy1NsBejm7qXqVjLX tC/PvopzPzDfYtkPW534sVUItannOIJ4LgFZ8RnakBt0C2U4hQN/IIW+Cd4QzX2ILvwypGKwUquP u/rxetcfAnqZc5mmGDHAz6e7PGV856/g20956qP6WZKKLQjywTinBfBkuxBiex3O2QmRGRGM4UEF FVdRbrAvAtBtvJGwUs/6K5sOT0tR+qwZpKDl1SlXNhV8AOxeUR05sw4vr5JQt8Ragrjq+Rjm45OM pB/WkiQ6QQYsU7ZH88Tc602pevmrsSGbD1tDrZLrkybX/TJQnGVkANfFUcHY0JPhs+KpLTtd3QSI ZTkxhiEKm1SMQ6GOrbyQOaCMoQbkIMzPw4IQ4dKEoEu+mINT4h1uJBIoVX8PIf0wI9wtmLK3ZXEM B3gs7GNXR0UOT3CffMh2B0sbtrla91MibIOgx1pSBn4+e8Tpn5X0hxfa3xXAmJsQYhFUYDkaiJ85 9bnFOzPoQKT/SdIAkiyjqnoCetcDwo13BVtxCBEUn/QXKHFZH8DXldO5LziePVRJAE7GIplvVIQI GJLSpspIJG+dyXdJJjqtrBZEN/+Pl8iXpsjiYL6BkMbrtQ4NfdAQVXE+c3k/GtkTUiGmgVulijSt SdHE68KCTxDleXaSdA25p9GYjeV/QFpbWqZ4uDo6QGNwwkb2nb2h2YQJ1ueA6G5wof2B2ewLeb9u p5YKUD2jV0ViUHrmXbxuam8DiF9jkLkeUCEGDgwSsGqcsBB+nS0BifA1WzYyRzdHo5ozJgJvFnaS KyfgCq6JxmZBtM+03k5G/brev7vCoge0JefMDpYupppMGBArSzqi72gYmEvvxWBMiT0tAVnZmKfQ 0TNowGmUOD8MOJnLOR8abIdnJikUqxFmNm9IrHyC1RMVg8xU4GX1+tu6tf2duXl5vTe6mcZXYkrR FdZzy7UCd+hbHfjPPHIOiFkLmGzmUXuCqMl1BfFlId6fzvAK+TU3P7MqKhp1A6k/7weel+MXxkfb s+FW7AM/7rcdzTvuEtzYSxEi0fKxFRxOc50C9eSzvSxx748iE3v8ebToaXb4U3mqRoC603RCM1pc n18QtNDsuU31JFq0aa4RVoUPK6wFAWj1nuWbRJyUcWWXhywxRIyyA6QqCanDFVVPyEF3t/wwuldN Rj/aQd2bdtv1tiXsYv0hAhOVr7SwYGF+KGYc9wo80JlAc7Hd9YEX12l19YXmHhO7XB8NJH8rPtU+ 3crXYlPFpTf1J21pzyGxtB65zNVQHpuIdAI8ygrk4K2UjgLnyANs00jmlGNplIAI8lRG7DpnW88P rhoHQZtYrl0pakB4ke0SiHvCnWirFV/2oUxl1va0eN3anafotinCJNQYt+C23dxmQHi6FhkKE4dg Bl6pQ9MzHFB2BcSVjihJi6V+Bzle2E0sXo0Y6QoPh784lIAIa05yVBD2R+R92wgIVaysYKlFP8AM MMpVqP3blQ+7CGOi1/IkjhcT0dq9SH1fz655G63kSXBTYF4I4ZqDAbgmIQ7uCn5h9+K0uKmOna/C kKBZMirBU1HvsHKgE8VEpc0coVMqfu8brjjVN9bxMtxvQfjFoPM2/HzBmrLDFhM21H5HbgedGepR 7dfu3qrKi3hjiHy0dtEtJzQina6oARWlJNW9OaQnh/yv0iKQqumWTV2oB8pP4SHJxvz5o7n3rOF7 yLxPyYYzILGfSiOu5e2mzmUYTr3h9nxsXLtzSFd2Zu1dtWj3RjBDJ0+nbmUtArYHDgleEAqq7zU1 ZgYPc+SdztrcyyQVIOWLpMzPA5c0rOT2JOLZv50z6RNqwNGFvZFa5TaYseZ5tB/H88fKgCmSo53c vNfaPGN6suUBSz3cw752lglvndPYuWZtrC2EW5J6yS5J/T33Ceo4N3vQBP8Ho30rtByZX/eKTkys i47AYwttEm0ehsXvOS0lbfs3QHLlpvrimdmCcqGH8umHb7dL+U+yvoOjjK/k4S41cL/sG+mdwZW2 5Adwyi+FeJI4MFTq1b3Mmc1Umvs2Pb34nonlsDMKV7C1IedLrt5cMVk0HZ3FFuz7sweRJTQTSLJ8 dASiqzI/Kd3KqugBiCO3MeaYxYgCjNj8jjBA4xj6jiFNnQH6O78/mXUmnI6q7rrHtcYN+yOVGGin WdbOjs1fDWKdmEJ/kYFw3zs2t54ibaW3S2qROo/Pi4BaoZwhK5QdgrFByO8oATp44wvZdqRCopjV hqdA9Pj93OalxszBpP9baKTEyoOxydsZARNW32z0OCKtYAzYh0SOGp/mVsYT/IRX/j5EasZ8doBV BSwJxALgqsVM/yZ1Yu43buJm0JyPzG63jSzlN5yQJsUB0UbTv+hWdg0LPWpbccaYZ6QPA9WA7JKV Piac0zCYFNEoUJXSwMK38b4+csy/GximWqfrtApZxoFp6/CtV8VPIkDv9VskpXe7E9vnOBthmFWy 7YD1NaF+d328NAB+Sd4Op0HCxdtz8NcyXFsDD/ooczhxWpGkjrc1/XT1LYwmBRHIVgB3hBXKyO6e PmqHzpBmAm/EJ3/bilgq0hkChVUL/rwiS99l54xJ+Aj1ZgsJqPEtopu2GNRCD9Sc8LfDsZJCITk5 D6S0r9IYTUJBDyZ2Ms7ig7HzQJnsGN1ifA0JTmqt0jw0rZG+B4m7omJViAXmdYPbk8iIRVq/p3Ot RBRTzXG3lATK6IYJEZnk3tjgGTSMOfdtX1X2GEQRDRSQZbSydwFYaV/1hulj3H5rB2HRAdj7yY/+ rcPb+qXdMv3Q5ErMVRprheIWAROqmAaN0nYeTnzTqLk0My5v5DOtNH9ymojBF9WQ4Qrq1RGCfSDZ ffRQyIqCcltdpTXnJnZ1pANg4uKjRtv48XFFnoEdTrkJY2z/Y+jGYe6l1BVQEuioiFyaZXlepuG6 HcCSWQj4oi934+b8RQPSgUwFCH16bquTMsmr7qQ9njqx7xjdXPOgUE6GLz60Tk1eTm5RrtnQVquT 1XuA7VZ9WQEZVi6vwJXcGRvmYLY1hREJuIIhe5j02lc149NJcVoVshagoBjVuufbMipEwbqD3FU6 3bdU/Jexzc2HyQP76q+e0TGbtxwpZWwk41hq9voAK/feaKLgj4vZLVKR7kdtLKRXdaV48sCW1ADn Qv1nEd4/TLRsFedUKCiO5zxN6SP0TBN8ycHKLWeboTnIpcnAfvYnDA+o1ow5La/SBsRBQw6oiAEe neRU/sbuxn3/EsERKA977HsLRRczbvdW58TA7Bk9XOTqXnqyigDTMh7yRHB+HaHdWBdcGTy+R1QM KNymHUk4+lzDZlTDij4GruatLiUN5tB9P+7Ap3x6lP40K1/+4ENu1sK0JAnjnnmtrr4QZnLmA3Nt S420kSCbidOHc/DnOHugn6eptkPDtUpO8Dq0b6e9Fv+ogDp10YCIpEwvfmIatPTM4WLsYqBhf5bV EGtu/3rRAz9QzoFRXjhoXlRjhRhXYNPZXoOglJnZgmSKESl5qnhLVAy6sm7wzdg4nb/C8K1t6iX/ fXihdcD4bmk3tm0hjMkonsxNOdyCCAW9SAydDYtLxjIAFnBCXuOs/qY+/xfrYp+AfNhPD04BR4sC C8N+7jSWqehebElRAxGvfh6xAUq0Ik2uQH61Y+iUsaWZ1aL0zKtkv0J2Fr8C9nEqv8DLVqXEdFzf hCqBWmjZz+S2dbdO3Y5m07PmwQFjDlLotOht6V8qz70GLE6W6X9IPs8ijdtUYPoybIFG3n+uCr5N 3Jl/tWsbxRYYLu3fKBYkVrO4CaDP+raQZaq2WZQCajabxjP+IDBdrW87utLwMpWp37aWIsv+kN5M LG9l+O7Zs7kYVqBRmc9cvvWGQRI142Lc5vaVyLSUtbT5A9jkL5nrbK5whgHEf7gHqinEYxreV6mm o4t3xJbLsOFRm6fv+8vYtzUVhMTaFX2S9obEStM70LtmbezCtqv/+P1gM4JSVBTn1G0PnpthNkoZ Y/PAFCJhtSi224ueP/GK9wzfXmd1iUzzZ8lXREOzi/odVf+uRnXeoGE+KK/lIR4qqF8Bmi0wVTdV 0reZHz3bDH/t8SWOoOpcu2w2pSO/OjYHhRpgUGwRqa92NUsas/QWmK4AbBAN5WTT0IOav7liWZha LqWMLfllb8q2Qi9aVPvn7hL/+eUlqeEPN03ZRfKjiuiJSarLDxlOc8yiPYshXo7CYfASzkrwXlfc l23Br24CRAmfpVWheqso983eDLdtu119Em5c0w1vUkkrnYpAu5M1jIjdid7t+xQKpd2u7tIM+Uo+ yAxw2i8Y3b0eJ7PUP8uezxg23fLCTovafuOp/d683Zhs2qb3slOPPch+XWQxuue7fXJzym0wvejl mXgBWVu8RrNHyRhPN2ht5SH29tl0GTtMahi3FI8F2usPnc5FJhMfh9msweBsOyEjFyeQwIrZzTii G7UNxB+izal6fSqYSH5p7dHwi+BzIqtPt4DPLaYeWPEpWJj5AH4NJt7thunxUCk7ROU5fFn73c9l BW2TM+axMGWDKFiPm7ueI+2ZWmtl1rEy1UDNne9wGRIdoNbrtUIqfCxQrKxhnfO+DlgryphhiMHU UWEg9TGegdcBDlb0nuvyzC7720/NX/8Y8v2gIqAJyFXUbb+WD1J4+xq4xEeIBLZABEJUJYoJS/Hm p7RMB3YVA4oDMWCyDoLbzIxMgxS8Clr1X6zoidqsUhb/zRAs4M7lRVP071Ikvmeblksy5s3rj9J4 xB8haiBPhk9zffIz3nyI8Dt6HpbpwwB1qudbSF1ojHGNlneZroo4vCIs2tILVKi1VX8oqt/Hw/jc B/Z4GBtXsVUkB9ZY0uyrMggzDKXrpsOv5XA0s+rKAfeWEOeUJgLDvy5RUl7eJ9X+jR8LXisMq+F6 1MRc1JvrzKHe9zHarVUJSTSYM07yahX0ab7mlKMoICxJhyScfb05uJstfPRDsfXQFtDn+fi6w/Tw qVqOfTD+Q4jsgUxjwsBnUtQl00KV/IG4rBbEBC7C8Rkg2+XCuJNjK2Uiv7gU3uhjszqOgd3PB9uL cFm+3pO3RoL04lAshpq2nRI/HZO2M2nbWym0eq+t65gFsV6m/qCPO7IwK4DOYZ3fP7GiLJvEVBUT FP1MbvHsPuvicrKJc6OKvTQiHung74CTgqwfPji5FNRLagWM5aEjItI64Mh7GuBxxkm44Mg6tfLw MulHnmRl0MxUGTTZAnNlNBLdSn5KlHnWhzEhv+3/Yj6i9lCOZWIprShAt5MmX5W4AyDHmsCNg+i/ dZFmVjoK/NNA5Vo8SozR7m9AXOwhl95G/TOWnnsyn0LUro/sYfO6p4VOywm9iI43DFHu/lDQ8mlv Qz8ZACsv58mtRAPf7/SSmUKCYCwQntGTef374wS/f0AL1FbRmUlcvj5gTrztpz2M8imxeb1lfgAQ a22C/G4PTUH8Z8cySoXQhSq837TgQ54UOVCf6Zn+logH1hQfSvGZY1NE369uqiZ/wpc3lhtzl2Q0 HSWhhtSz6d9oPOU2S2i1a+3i5qvXtZ1u8BrIYhmeUfR/ST9H0hjI65I4KRsvOfVEKlBFiPyJ8h8p xT9zlfAQxpICaMKQqv1d7HGDthE1Tw+l0svLEJPtmZVENG6TLokP9heCAhwi3rHZsxCymMwi4wRC KvU6xOzzfAHQJivBXE1ZK8ceU124BB68HtFJ3pTRV8MlmHhXJ2YRHaBCuSSchFXrUnuvnzrPreRg nNSF9aPUD1+zyXE2fy114Lva1HhmxmeQoaxDFxUWxYJB7ihNKmTnKNFFZ+5wuhbhKWUbybYDKHJw xnmg45e0+CCHfXActndNyFrH6cBhlq/Bmg8niaoWfBgetx+QWL++Zq4ot1w5bD1I5lE1hdCfR58/ l4pB6Mk79q33I81/WOVmZ24ip4LbKBb4lvl0O+XoVslqf+nB9tow2khBVFUzfgpjSgzgD5uoWwpV E+qSvThDAMv7kIH+QUJbPkPYxFkYhoR48p9VpBasPmrneqHq1m/Y1oYnngGaWDvnvQGuy+7p6isX yX85kNCgW4JjLC1oHzngqYvpix35TXBcZluYce9T3OQKmAvlyLgj/h3J305tcoQPUG58CRT+36zj gIOSIdjlt/deUlc5RqwhG8daAWrxMKl/DlbcTo8XIknXRrgKI8PpLZDT/RVfZ6eGQRScqYO/qR9g o51R7TKsswGh/qoYeP6mU140HbBXHYEK/jxGgMtv+cA4QpEbuHxXREOeaRRXjUQCJbJ8gKgwWkOJ enirXT/F+SV7GNfCKjdJg99bY46Ya19a21fzCa+WjTTjdJGJ1QxSB3PyGE4S4IlaQ3R1K5aqQCoU 3/iA4KFwQQAD5XKEL3L8vOnwDsgkrsohYvAPY4bHCevu6LKfAFgZ36TtCDbvu5xlvpXixDbowr1W jEgqUMkTguXhQ3oqhlCjwwBLnAxoZ6BWef+6IhmAl9UjY/t0dYM5jjLtzf5ulCV5rVX7VDqZWseI z3raLoy+holJ78QFW08cELM6s40JGZKhCpi7utnNgP23r+JavaL1QZlBqIJOJD1Jd+1go16nT3Np 1367BFDA9v+rXCm+tsn5tqgHoYPw/p9xKd61zY4FKbesCl/dn4kwevx1ZKE2oflex5E7Y8uTF6s0 ZAnQFvTGhtWQT7gWU6vzDzk2K6iiYlFlPbfm52QFroPcZFJvHAU0O9xsfNHYWhjcfB6ZNBMn08No fOJxfqClyG8k418ynPUan7mhvvTFin+IAGFSI0LQ5pvX2cOB6wOk5nZkEcc1jdaCniZ6FS+w5mzk gKwLa2wQ13BmwipFp9thDTChNlXiYCZnTpHHfJN1HfUo4+PKP9DVw9u/UJdtR8mOn1MYG3Y8PbUo DZ9lBn2aph4lA5SV5IvgiJsdbBPbX0O724EYhrH/NVu0HTg58aEDOLwJGuiuT6ewm/4WCmj4+4RP ri+TJN855OPho/CJUmqdPKiXcr+4B3VDUqOM3qsdz6pqU9OP9YCDPPD7/Emgd3nmVYSX3626Zjso BSjyFUu9Kd5QFwecvd356eIJM/TyyTidE431QMih2Aj37ZIAiCfV+RZZV9PH6T9ymeBioVS+2un0 Sf5Y9o7VcckED6ll0ds9o7X93fKk0SPdduFJu5rYwa8saRpJ6NjDE6h0ArZRLrs9CeS3psrT1k5P mZ7imUxqFABBnxf9Rfkc2gYC3fLtRgilTSqDLyWmRrbqrIkcHtodI75ecBZih9i+HTLkPHd/dhOk nonAx7RS1fJUkniYjvOlpUTynbPHqHtbtKkFG+y7I/rYzj9Bbn4ViGbfleLtWkOUmWZHKqR13HOs ZhxDh0aH9HKcWRlx3MjTyDnTHs0PHNyZrBEX4xIXkzdIutCzXjF0h+A3kdPMLA4Kc5sKQu58GINb gU7L8JdVXY9uqKR18bjbavD9ElgWHsduTkVTPHJu0T8cq3uttLMzu0WwVSZurAwPjRSw4pGY4hnP MXE2xqmqFDqo9UZJeRjjs5wAo8PngsdZCJjFvqxlSECeFb6W0JZUrod0N9Ct7lMQEdsCf6IJnTZl c6za056c9PYlGyovzUG1WgaQoDNQ4spQr1R7vk6aGO47QdnJXZnsO47s4G8uX+tpkC+ZqpH9B7J8 za4t3Qh/PCX0+aoa4HTTREQXHY92cKrIQecCB9TUmkWnunyRB8Rl6JwBoaYNWZOIsW8gRyo3jiom iVd40e8UB8hlutp3GFNoKyRreGPL/o3x9fgiEU1o+dgjGzaxzlAS/wQ9uizB98wENj94qPoMY5Mp 6WXlnkffV8lrUKxIbqPlhrcp/MDv1a93mUI1uJvhRuJpC+wQIN0RF7k+8nVmFKpXlcqeSL8jjw5q +lO0eknOUrsVxpdvLo68O9dxC+i1iWQxKVJYSQpCdkk0q6/JkU/4G8t8yJ4E29ifPkY4uDUDmPUb JaXOPdmmdzXuFZCtz1HamBTTGPha+L40fy4Mt57WbYW57sSCFFxs+H+8NxhDbPKV3Q5NC/NVmPKx jjgFyBN6vdvqz3LgLR9+SbzRwPLoppyVSHOwnE5JEkmIUtRbL0AI+aT7zlM62tIPQBkTl/ym6w/E WOkn81ibf6a/VUH0tXLZ/QghmSzj0WiJh3F1H5bDn3f6/Gl0v6FxK6/8fqf0thRZU+nKy4BPuG+z R/9OEVkR+tnZkGLI9zMDKpiJJ0VMHmPUDyTA/UmG0YYKIqkMu19gMtZxqawTVoSf+jKsFhXIiS3t Y7xIHsjbCZKjn9eax8vpaQUOoeQal9rKy7ItoEhZgZ2/QJbLjvtMEt1IhozE55E2Ivu+ZSoVLxlg UMuA0UCw2WYBDKgO0EUDY6tUcwqrzC7sSr0yXx0/y16uH0noRKVG9ERfdoP8c1DjiH1LfN9/lYoq PFm0TDp++1QQZWp81IGHxOVW6k+HTp3QrlwbGi2MYkFS4lIDt6OeBGhRtROSfYadolHJ4w3hSK1j G4Z2kKuQo/s/YQHmo4YBliv2968Ujkix5TilRQJ1Sv1YKQeYbprXOqeguKYy02AeZq3nPBPyw5e0 a61VbvduzeScun9jB+hIhWQLcUmX2RaF2FVRjsw/wLAdN637AlmSqNWZLc6cfNQiFiuENQ+NvBWP YyTmZdjuImXwgpZuCiPdgMDVcz+w4xsHSNjimsLyZ3dv/7ah3dU32NAYwT0H/KF7q1f7cVkTnFqD aADMNLh9JHOZHdpXP3ppO1DNelSVD3PX1aMkIZ6kJrAI/arcdo7RPuU19oxddACQkYC+9fDDqxE/ C5CL41sCB8YasR72UY7HydtkHtboaLoOuFjlecLVaA0vP7Sq8oION4uIrhHOYUQfY/JMQCUiht4Q Zaoe5iVxY4eroQ84ORtBiqiRRACA7olSAHeGeLLilOzIWF9jif41qLNntef7OIHq5+omPWCoLrP4 DCy7cNIOkGyv87XAbGbi1axcCUGGD6zePAqZ49HcThCZFPsfVXVVnzeYmIaT5e5cmrN+K8hNjk99 GVoIr9h+yXpLVlEJheKYQ4qAtASwp2HnGV6h2GG3jEQdrpufQDPogiLYDegCm6jTcCCnLDP5aKhw u9+pheWPG9YjdXI6xpZghkyAH8wWjphiCyHskZ028jxR2+pjlB66LgIOHAN9A2xnAk+JME1c9e9O mPar2mBnWotfmnPUs0RFEaukE8Ia5+xwHRCfVaGQxH1Fr/dR00Nd3dCeIZS1SNrFQ2OeWhifINjl RBcC1KWnYIY0JEBeaEcTSfUm7pDHsoEMKAEnwdy6uIT3UgKc8Q9WXBLNTsVoW2bqe+hmZM3t+nH/ eSNx5BpoR+LKy2gHzfoJwLspwFjV+WGtE1e0wpgU7UZwGUfqggKxhC3KlFkI0eJv1D24WGC3p4KR Ud07lnaRHCAb85fvfYm5GK05PAHU2cRikIZcb/4jeN3jiWiD9pPmjkb3CKGFp8RHPbcfzBROPO4z 44sOwObb148vDQyT2L65kvhu9JOonbTwmhTv8xPvp01f83d+7ua+jKGmbYakWA6aEfWWpgrmippO KEEcTQ/joYDIiARUnWhmJDdwQ1DS7ym9eTtc7IWbk/Z7vgVQjNt73Q9xxcy6mRFmx61Qhi4W02Jo kshGqt/p74iDfBDTre/j6FjwfTtq6Q1nyu1ehQRRzXxPAOU+f/81hWzGP8I1iD668n1Wpa1ICuWI F9yfF9czRChlNarXFxoPDsNeI2m7oroiqE4riVdt08jBzsIqAxsX3rYhQHTDHhHGMzzIvSHEYHB+ I6tdoyLbKbqgYqmj6L4CLXAj1kcVQJbT8LqDURT6cqqdDb2RwCExRXJIJ/zqpuk/2Lt7h2/9E8yo DTxshDTxlocQA6bxqAvR86uJz1Hl8rQnG31sR15UeTCt27LQRyX9FFq9z+SM1MNSfQIDf3ou7li4 oA8Up/LRnvVSUPS7dxw3OzRaT7QIL+aSNDFDzzpYrVafSDCQx7A9RvKRBfqr0K7bPMLKd+JhounQ lcj9j7mFDFCjbCwbw3sBwsvwNtcGQbNEKJKx6BuB08VtWtDnE9M/fIlXKDQN4LRdXSBNvpTXta5y aX0gq4u9Fd3nZwVbxhdPat2A7wO8TNYtZwBJNp61PeE0nbxpqKpBx5s4LiSTxSW3YVFsyY1wMPug uX2YBiIMCWArCVoz+cQdIfBWFLCT7NFdkqVNxq+4+PFtBALC6FhdQQfGJyOT1NgsGwDhL7pHKlhC 6fXzzb4p8SmAKDLWhDu8BzVvdwOWkUZRQjznu4Aa5/0LfOQohSLSN/nxeOo8Yga/QZKNAJ4giSFF r2/Dcx2ytpF7Tujdb2DKP7PIgo9pcAPqQrzzLTeSuFqipfkU9mAiBZMRgCs2ByaGiCRvj/bsMxcZ H9gkLA2y+UMPpbavvcooGesaNcJ+EacBcQvyi9xsJvmS964rG7tYZawBszFuP8ZsuRhoU0P+b3Br 4eIvvBheEykTu1147gZU2YqPTVDCOr0JX7WA5gHzSNeo/7ZSMwQgd30N41X95Z4DULcf6Lvg5p96 QvkBCBUCsFt5JSwZf4hAbsb5bIW3X3vTG4XXpfCgiWkWrdpQtAM1JqCOBB6EnQCfnXfCmBxhxShm AOSrkI/TysFV9UQlGCa7nNYVkzhjPzsCouimYapRzD+sD4Lwkgh36bmsdNtsTq1/EMRxlDFdpdgi GLUsEiNFSad3U31rQuG9dRnFb9AaQDNNOIF/zBAzIFfTHezPh3CzrHAeX/53SQ7SVNq457SaEIb0 LBtvmJuHBkpsJr0EwSynzXKdN9kmODPquSPL4xdUb5OS970Xm8JmB4JY4CGP/JwaeTchHrK0+Jd3 RX5Eu7TXm3375LRDPyHvjzJKnE8HddHIC1qFWG8UICOFZp0HmzaYXIOhCP9AprMwpwUb5KiLSpyy b8DKSk9njmWwSafvCOmbnhHHIKQfPeg+IKUeNGcjTW3nQULhM4Qi7ZwjyNafvTE7za8yDI0S5SC4 0zZvBkDVFuwsONO1A3HW0iHo9C2csgg49jMePU0izRH8MEhKoHuyLjL8EjELVwBsqw5YODj69Be/ 1dJb5Kny//yramuhVYDO5F88V2IwtojF64rgWXXPLj2ezbEPCisGZS9rwBmCR8TW5LwAktLKkW5a N3oHmox3t9YfBY8J191Vf3KBW8BS/naYK1uGyodKIMpZlQCbR5C0xp+t/YPqp05xYCrFtqhWJ0h2 YngOPCgB7UzN+xX6Nnw3y8GECjZWdnBU4b+KOWV4k4opWD+TeKaFloR6gSpJ1tgwGMw7n6a9aiFu rMa9Rp0MR4A3nLFhTa7fabgeVXSPnBeuZYR/yORnXC13jzNQGwC2g5F71kNhHaJ5DHRkEYaSIPk9 FMr7bzd3V3a1Xosg5lWLWs6Kc55+vIvsLMVRiejUmHfbEEzmqkw95r2rjpZDYGF+i8/yXGcT8D8n nKeGfcJiztXSjQNUufiHIvkbjFzctfVuIJoWxPEQR0/QkbW4k9HMd4lvDBDsZN+ztsYhJjHNWZZl tFhA/2h59YUPnR+mNFGmgqdazb68mANF+M/HhynHHQ112XzEREY7p7y8K7farTlS5PqpaNBebUUM MAXgGNHK8Wkq9y95ihaA3nLNFoyB9GfQb3W2ESv2zr2Fyq+S1OD7Lz0KttKL0NKJD8V/KgO52Y+0 crYKYPnq6sB0EeHYmEur+yqH+akHPHCTqvnUvctZZcgaXQw2gZsiiyFqOnqHKpoUahaXWC5/Z0GG eiEn2RwCec/IxJzT7ZlYDYLI9QWCdF8Cvl6NuclroqRkCr/IhpaXPkrc/dfpbt+tDo63f5nfddKw /ad2+LJcgiexfu3hlseFSs8u2euQu3jeqL/K2YzgsZQcU21vSmuhmnFx+5ogrNM0XxLbN1j4x4Ms oXRD8rC8rEhSBr3sdds/rgPZNovEnZQVKd3Dtj9POZTs38nALU5NHoz47ugBEOEtr9gXBlNv5Pvm Z04uB44qkG/bvZcuhrETF5fP5n6R4UTQV0msD1jqUfdJApftYuE93K++3TT4CaPDhoKTX84XiZmc eP3U6Rd50cvz2kLFA8BRa0Gd29oc7sJg55ajlxxea2LDeRgIBW0BNtp8tKLFvGZcHkdj68pALGXx 10+NK13a/dSsx8aHQ7rEUheNRXeZB4lHYA/vULTxconPlbRfAFTkSZAqNXVweSqKVr44/BvEl8fW eN2dSpc6CpGCF9WesyIHfxvdpPZDoRTD+17MboCLhUeFqjwok1ifkLU+6S18dOY/VSwrWf7WnHNQ T+3uJzjEuRyDo1WTYTWPCQWdKYeGyhW2o5t1yodAibOq5lFGQCocVkl8jOhqIT+rE/NEBDF4LTNy ao3u9k4r6kV5qhPspO1uZe1X9hxbIDnTtGlGj7UViUu2w6E2Dpeelr+wAHABpyYiWlIB9p6llfzb ZKBxSkWSSdv4/j/lYpQYrSHDa+f4jns7OfVI1nIEQFLMP7BX+5ZnXJXpJqCQONQ3zncDxQ/Y5ooB fde8mJmEpVL0bDdEvsY74oIoB38P+A9dOUyZVZxTx0XqbYb8fMatsnMISh63QWgDqzGsUlPR+bAT slsWjdeyNVlPZRWxrrQgo/oxeZasvMYg1791HfM4uxhhtG5PSAPuQdJ3gcJM4V+8iQrIZDPJ4Xgh VRowr0z3xQmoNihQWJ/Ea0hluEXQ1DMo6NrjFHQeaHaw2fs8O4CdmdE+PbpgqfrQeYn6FbX1fQPh 7/jJV0O5oMcAbHXBkmFTgWOROc2OycEN0W43TcUd8KKc4wG5SCez9MnuDDMVtJsSlVqNAYiXEg0U dFBCbMJDAGFG+1GNZlSJT8uUZVxDnC9jrQmojUkPCITbzs+OEVOMowcEZ8kb03vSIUnqs5J/dxSb 82yTmtB9dkecIjPhVE+aEfkcOY0l14xmNc+89T9OwS3nEGyQa06/2cJP6cZCp1sXqbmEAfVGsIpN NeTmc13axLAyCffAhnjH1NNJEW/cezEZtwB4asPg2qHGm4W+vdjDfhJHXozoErSf5qECaWa3NuA8 5+mhLSLA8iAd213Eldu+6ShwQyiIyOTXqlzZ+FiA/SGD81mwwOqNCaTPYHPSVoaSxmARjjzTgHkW oTl3nhnBgEtMZHbUqB1rDkxPrrX9qDQh1xBgcNGpe8AUMeMAihn8B/6ShVE27vQc0+5F0R9g60tZ 4JlDwYq5mvc0ThLsVaT7Ha3tMO8m/9JldwyKVcrQUS7Yuz+72qNw7NCORVtYLxbfpeu4cWVZrfY/ n/cAjp5rHjBUULKmIwMKxur7da3wa9z4361o8RKVh+L0UbUSjc1kWkkyeJUBCgE8OyFiQRO5SDYy lWVRz6gSBkNZnvfOleUgOrpg+Sd8ZMY6MvdysBSoUNwo9ildkNu8KniFTUA3Xza4elFBAsHvnn4x QbKCpIwxdHtu9if4L/0nhkFcGrgZWBMbvjmYm+mt/QrFD75hvQuTWsL09Rwo4oc6trxrXVWEs+dd 7OTTRCpyW3P/yXuc+RaTauhwGkcUueqUyX3TvuJZ2ZA39+XCjVaCXm9NuH3t+yKeMvXTAkHGZk6B D9PkQAxP+zOyjgOHQ5a3z/RR+cLy5cArgkzUwmrFJMBGO8+WW07OyXY3QBMQ7OM4oVRp+JWHUJL3 SSeKAe2p8/iX0S1K3NtCqclwQurnTrv4HUXTrvTU4rqYP6DCQWVNeGyguFo1BM/0o/ucnxwauwkH j3KOj97/+5st+5HwpheQkMnRokbnu51OwYD+7lbggWgOcjOVroE4/swV/WN/22d+i19R4LquGjxk GzKoLs3s2d5+FDZ5jG+Odq3PVhk05iViwiTvF4ZOl25mh7YNFkdrT04sqQz3AOBs28fyPJrHDJik sM36TF5Vg3qOgaqQl+byP7YpYZaDjAyFxkzEM44XTV9pNBAjeJRqJTvsKcWyUDbHEYS58YlZr0Il 7UuTl8dW5GSyt/X0/BJTDM9PfDAPlY8uMHsmDezXinPzAiwOtPGvWRZL5jjbM84jo+buHA83zH/g MFrq+OEGE/LuJlV+byCeMYYnbUB5dRo1F75VC1BFfj9Ocg8KMLK6fQwLk3KcMQdVNA/B+/PRAdxl 8pZA9wDpHsZAdlUiE9IMXU5IXorac/U1eQMRqij2Ev71zkt3OzVn71D8rOpXZ5wlcdlSKKamqkFa Vfpd02o/FIqoGZkKpK1A60menvNgq3AjWqtkCTIyIhBBnOs1kT81C/h0F+j4D2Svot9h25heKWw3 lkcNzDDoExjvgDLaEECt5pZeio4GdXd+vOJMTGWb6n+4P8YkqVtjFBIx4z7Mlhhp46wLG3rOAVBG YBBy7mtxx1grOyr0ImLpT4PAGKrIRt3m4FJp1j9c7jV7jzC0kRVOKiLq+VKQIzmRSo0WHwHZ0GG4 6gMfZseR26nq0JwnCOHOLrFz/ctu8s/xncheong7AbJibALtc+/j09ZX3wIDa93VILudlFKWoLyB y/4HyPK8POIWv9HyEw4Amkg1hD+D3EjKmT8QomdKP6lT4GqQOrkug7Q5rViZgbREC2Il6xEaAg9H C/msprYoXxfSy17NO3q7cXz8AtHRRdU5oGfAFFmAdCiqjBxyRAvvsuAaAFsUBGnqK6ocHOmD9d2I eBvoJqP7v7xC7M59taVezs9FC0e5rfcPJGAR7l0NHiVX7/Fa3TPtUuH878oM1+jZN+Ud9WpmLbBC Ff0lll9C45p7c13PHQuo6Wg/JAcvvRNSxQuu3D8dFHSJqOI3s8dSZpeGwzJbBWEPKU/rCy+ppTeP tAlNf+FduQB0Y14XcGXjGWHV/de14SbdywryjN7bpQKWOuFJqa75cR74XlLpzkEt73uoSmMblwbl vBF5gQLQVDmggUhAN6Xn/ONmZpCqdV2xhLJFxh52lWYyEdnVJ7yB4x4OANUD9uulnL6SdyRN6XQR 68zIDZG3Uypva6aB33YUj8V4MaUOLMBnPW4AQmmDV1gUCjwJALvuErwvztcTOiZcx8KJm/qZdc7M agGJudLPJ2Bq3/UTIgb7+P/XPo49/Hoxqyo+cz4YRREPCD1RsU/UeXalk9HNaxYk1LNQUJ/85Ce5 OCr/QPkpwh9xvFJIQswDKoTss+8dVhTG8F98M8obHrS/5LDUkLMMHX2yhkG0XY0gT/xnywDEDPkK ULvVVBJQkgFiLI1aZq6lIs+4oilNCv0s9mXkoo2IVWCDFuNbtzo0ced/yLZ9jtX1Oerm3HyrJs2W eLh/Okpqy974gKHsfKlODzoftNa+1oUCFgWNeAssqvO2aYGIbXIJziipD/GkvpsNliQfKUF0VhJe M7Fiy0D+YVNzoz7O7zjXrnCws+xpvx5WS/riyIn2xIGgTItuWrmZ8yD3Agq1MAtlbsw/VE0PN0dc RMlr3TqV3WlAxPFIJolxGpHe5+DVwEsIZ4pJ5gD2WiHs0V72LDnWvUzseSaCNERqUNt5KSICGXYj rt50xpJgdRm2tukV9rxSy6C8vp9D0HSijvG8vbLQ+dDvRQEbK9MUj3QiJi3ptdk0+7G37QRIChlU PZo/+YsnkQnxeyQjXkJcOFZvLaHmhmUY0B49X21jWe8Y7JzbUYN89Ev/0iE1FFb8jLrlxrHBzY8M VTcsHHzSOtKVIdJHTdMudlnOGHvpkCzqgcpjnffqnEL5euSKrDl5bJd9S6jzAlnI7+1oklmvutPr nwGAfg5j/PRFokdIZbGtJeaCOPzXqFyytZUNRd/MdUYB91n9/Wx2+UGPJQ7RQzi1AC31w4yB3GBA 4/rwNLFjpCIjRczWLBM3Iw9alR3frHnOB4RqqGa4nohpnAXtCcyRFG1YKsgNTzelR/HO9XvBgru9 AWcohrMI1g1kSqBEgAPGmTh3qonezPKpIvqCrObxmLLUZFeTlnHKQv5DgfHSq/c78BVHMkj8JWdR PHj3CBiV15Afco9Ac5Ire9O35QWQMxNUuCfLv86wtxTjyyzQqQiX0Oy2fZQYCtndPrwmRf9B0zWx Uzl+fZuP/MT06ziUXCJszkFHJ+J+e8U1U0uvUAzTYAzh08sdnRB574l/p8bUO/7sw/3X9RVt0aUh bkTaRzvU7iVGp207qXPMmx/VunJURfa+3Dm7d+8syiseg4Kw78LXcc/PPfvz5N6c1CcnpntgNWoY g6k58hZphBToiQKyxuWoR/Imxy1mgTrJ9SxUVdKg1z3Rtccq7tisJg99y6/dEMx/lHsLtoziSFri lhvbZKnmTvt++aoeQsk7fxDxowjklNLhBPJdmuW7hnHPtXyroVFXsE7RNVHn/0ay8I0AjqZalL3D 50Q6vx4NvWdXnOIgauGrJJi6+MuhNRjqZ9TiiF7SQ/v4dsrcifqXvzyhioA44eWuKFthBaUiVvM2 OKxvF9lplZcES8G33AJhA5v2pfUEs4cCVHnODK6Os5Exd0mDcqVOYxnS8i8VoOSaHAYsJxDj6s3N xIe961ynwsTbIqvBcZlX8m0otmkY+PqXg3cxsCE2uoKRmrsFWHxiPBb/Vxqau9faYILkkqpZVTXk PQ9EMOTbFLbuITrFjrwgYkXVVu7FNvI2ZDLkv4RAN6wHD3g6ikhkqNrWE4vv2VsE2jQxtVYJEwXI +MKUHXTRQG+Jr9w1joYR0kXhGGoA4WkdvLP8exB+OSh2NhNgbf4rIbY+0OccjBM2KfERxqEncmvE QdR0mKlAaDN5zgy13f+P1Liy088oBdEl7UhFKoAcyo6XFvuMrB5GX5T0vXTMfc+kssIPHyuCy4sr YPpySFyGCFXZcsJft7M+TlsSqjAmS+Wk//40u71Kni+dLtcQ0WYRtzl2AMTyyUt6b9bDGTnLRV0i WuBWFWetC4/UQQEsUrQXmLMCHr6SyV6K8F2WuL6GaTsr5DTG9RhiOYPDubIS7QOTHquWQ6f8wjc3 JyejHcpG+LEfj/ZFOlTck22oxWuYdUWEKB3JtaZywTf+42FXv1ryaTC8aGmH2ESPEeazgGvG5ED4 RsG7o0USvs/v6kYpOHzhaxWMMsB1VnZ6qWSLXLtKFXk3Qaemsn4igRdPgMBT15j7f5lDVC3aFVrx wV/0q9z0zkw7TtPcINJBr9syqCZ9+h1se3LWzXReK7wkyU9lg7IEVdiltFK8qoDmbsGp19AoDkX7 FPOueudRqtvDY1qGKj7nHWUrwcbd4GWWVqXXdRBvSPIZ16WrNbEZOpoWBmBbCQuAtUZzq+S26hBf QEg6VdJ7kxMNwOC7dZaHC5xymgUkvEjL01HfGh5A2nx9m+0hzV1XpBOAJqJ+OEsPmyfHsvbszmxp WqD6s2maU1tUB9KdgSFfxcTlr4jjaIEPOwQRgoGLXFZpqUD3GgO9rellERn9XTyIsaNqcLT3AfO9 w8eseXOPAqexLT+0V07V+d7Yib5ewV9XwE/lcbTx/clqz8r2XppbuioCh6OqKdMBuc7Pf6X/GCAR qGQIWMTECCNuOheWuC6NNN7bYC8VsPki6RZMHZR96mc6ftZQMYwSHY6LGD6pg8fFrCgqUZNkGKQj iP6zLfvkx9mTcrYdHCgd+048f/sEsemYZ37UXE9jYVHfTKvgNU8QFo2rs9jDkfSrbw5ZBTCbVn4Q 931x78H41MlIc7PHPtW/UVLu+fjw9lLmSJj0NiI3rXqjnfde3/ZU6B246AsgGcwgcPxpH1kqpyNi 49EbP2IBwowfPufqLC1tSF/TUE013y+S2ehNwTszWVyhq5QvAAt51GussgAimx9DGxRMVpM6C8Jy 3VRx86gS2FJN9x2zDTC7o4h6A+x4AHw3kfEmWDxjJ1VDMxIBwDZ+vIOMVQcMfiNUCvK3sxtB6goi XV2krqqOiKL7f/x63C8E4CXe9CgJjB/Pgjfp3QK+LwBuXGJGxbuF3bew8e3zU9XWxX9Yu7x0jdtE V92Be8/2oDRFYXTaKWsijvwsalZ12D79S39WP5FbrSBn8aQz3E95P6KeCmOeftYKVhk62BYSBNDu 6qYTBg5d3IEV+3MYkRAeAr3xSpQ5ALxj2KjlAmBt9+Q9hXK3a0Xej51tz3/T5BAM18KjJCZdizzD ObFHAPdwVZWwk8fbsACJENrLOB0WVdxlwCXsWnSZU+j4VE2DnnzaJQct7mf+Gf+bkGMBnH7uYUGq kJjPHyw524DJanv8/HgqLcuHqILuUGGLnXAHqGgZ0CfhknVr1SBurovGgXPG9VMESYsoAmNt9bVP 4VMDk4m8tgHGenbRIQz3S4CooP5dpdX16a0XNgzFUkIys/qrksF76c1iyT2s0T5ZiRiCy/Z+2F4N cDJ3ijsFeU8oywVbedjN/0RrnZbTURmLNZbbLfXFgBTXe51IkjX5nU3ug5ZQK30BQA/jzQfomSXD pg9n0lQOjqmeP+FewGNn2l26OShxzHCWGivD/PLTu/xGyWWU5W+FQhMPKlgRYGMP8cU51Vif0fGq A+zdUJb89QuK9fsdGMgtuorAUon/NiAUtf8h8Ug7D+IVGnQDf7nopB6YHfVhSOT7WVLY7YD2CJwk HezCXwHhr0HFi0sqYjd7OD2xVXXXyAeL+M3Mzm37SnoYvikJUBxN2sYWlpOGdW/qJbkXy3hd02zD /que6qKOSO89Os8TTVT+Ar2izJwPH0VU/ijNX3gZUBUd8HCWyv6uS88OKuvndaBkn914KJXlFaM8 FUX4tpq5XucrIxntvFmqNNlHNJa7qu5DgJZ+MfzvtSzigqj/PRAeTFUMWwQrY13ZvjYFBhA2exl/ GfmxdF2pycVMvHYoOxFHBbMplGsPCo7pM/XHITe0hN+aSAaf/2I1yqJV4qAXcWqz6WmBkeW1utsy 6uYBn3hhCMyRbBd95ax9/9JLAIGnf4evB+1/Kcv+a6wF5A5xG0iE12kZP3Klua0d1VuVL3L+7g+a YpkuEh2dvJisPa+EHWU3T3eS0537w9Awj/PYRZ0RhefW1eGv3MIyJE6q0Z1glLv/WSDon2B/Bz// id8+tJ/hNIG1PXea7oZCq/P1Qut7u+9U0ECQPHYqQ6pU4jU+UNSmtH2qA3FsRrKiM33SftVEFaN5 0CQg79H6kN2XJ14R0yOya255weXpUQ95qPDAobq8CAOq5dA2uLxSeTeb9LuIlEdWw1riRCNVE+GY vLYBd/Yes5/B9gPnA6MMajaNwxlrNAEp60JBzr4p9D94FuSokkKoAFVGf0q4wkgdoAg7mgPrdUOk sxU9o+ayVplxklRl4Ra7qHL8A3Q6lNzrSfA4eZSQc7ayLBZjd2uuLOoeqJpdswAp98yJWBe/6cLO KNwHHmsifwP2pjoV7oj7jEwVTSGfFjgLTpiCmzXeF8KWewO2zwXgqVOZmzpMdjjR5MyROZQfQ3xE jaH64rcs7VpadyRCGBErv487Yp4tIo3a9PF+m0oWbioJ3R/1pj5q1TI8J7Y4pHZdq0aynA3aNxQt 48fT96LY1+89axC45eAt3Bpn6GOIEqttiDRBdH9lTVz2V8JjVcC2Ks3d7lAAdc+FAvhLrmegfEtU 0a6IDC+8Sxe/GJIysh6RkEYBC8D3Gmh8oLDb2CzjRhvMLDeE7au0gdrWfP68nfbz0vcN5Ph2ZgB9 HpMOSpdmIiwly1IxkvbbdCEyf1uDEgC1k2iA5hleJKXv80w04W+Wja5zkglAb0XAivH/qzU3g3bJ QNHRAL2AeTcDSRfEp3fKfAWsTL9zkmEWV/YMcxEZdwJL5s0Eg973m0Mk67yyriOxrKR6URAD9eD+ QP4Pd8sdS/yy1ajQw6WuBBL5agRv7/Bx86Re1GcwuBmTL61vqQhK//UdJoQyiQzxdyjUh6DUBWOW mCCr3hlZuwFciVZxjGU8/8TMNGv0znROFnSLj2KsWH9ph7fVjPo+Y6NUNUk4oVeCwlThjgzvaFXM 2PMfpZ6jSgGpvLwfBYufI3Q0gAPQfzIw7zLfYWbsgKUTFCKxV232LDxN1TtNOTCyMHIyuOaBz90B NxYHmAgLJR6kOUJqvGL/YFxVkJMXbuANvyqVz4VWMipOxmySUdcpFEgz78jpUa/4fJZaqckWq1qb 08pLfZLc+eqXGY9UWSmuVAUVbYP1KwufJYEWcJ2doHQpsx0Gg8OjHcUFVZRghbKd4qngxvdSg0rr iGMjSpDqWIzJ0HKqQibrCuH5szExvlW0Jqc/Zd6tvdFG2fT5SVbLIuMNlfR+CNJXRltq9p/Qdm5H FQrwstHhLSUeIbTI647FWsnpyrl5vT26MP4Z7BE3AAShapsEXmR/FqjYuD8sUNozNZ1J3TcLxw3K PAKECI2u2JRyy24AIuEmZbh4wgn2BwqJOmzhms5VQ3yOoxbjRRUI361vDcCuV5uOt90O927GvhT4 ss8jcRuHVsd//iO2pEMwCJl4PtpfZl5RTGBV1yWU4JPnLRxShyVCz7NG6a0gdTZnVUmb48oqegQa k4JzGdDE1UdaEOTbpESmV5mWZiwa9AMuk2c/GjTwPDkS+4VlS/J4quxnoky0vuJiBfmxdeVYZjM5 hZm0ewN+TBHgCs0YzDIaVw2Yml5uEaJGNIbMxi+iAh+FydwKlWjobfYDnUba7Tj8DpHlGqV6yZ8U GtMW/rar6CDlTl3VL0pMaMlTsZuWeTJREbmJwPd53E8Hr2F0MXcHf4eKl3fheOajXzHNzni3BWfY OmIZW5inBTYIvU4F+y+CvNb8jw4ilckWKQ3RXH3R0VvmCY6RZ4c2mm5BeTV91XhEHiivSHANxhBW as4aelyiQY/5eu7ibgG/mLEQb/5wyDaX3NwQMSkzTbhFZuapD1fWeg9REFK+4TWF0BHwAfE6QWUc v1YBo2pONoag02e8nBaer2MzJR5hme99MXuh6EC8MArVzXQ4xxGbO2uxFIxuON5DMdoXs5dk8dCN 4RgSVCF1EfSRwNNKFXpjvSlkrntaoNXbRsIlfgC40S0a9R/k7vDG/dSVXwrfLxOl/dUyWBWDUFYp UI7uvFxANWyXemDb/XXHl/lns9bx4lTbfg7WeMhd6FSFi3efRMqAl7HSoh890Jb2+jf1caMcSvT0 /Y5KKxqD5PrdD1LfaHs6NrP03ZLalnbPcQqTilwVskcsNvsRuOPO890ZEBsBKS0XSQHCNTn57Wra cbUXO0gqq5VWoA2ldzDWRMb7zvO8x7FRomaljIhqq4hTamnwvTMUruHSZIgkOu+cV3XoV+aGqXq3 EtRzGqOxEc3+h3zDjy5jGiqeM7THKmsh1Lsv3Oge2eL6UeWpb1rcY4W9VlBdlSPxpbFGH+aB4JXy Y+VUEVL/UerxhIP31zeyEe2Ulxe7gtcmO81lXkpg6ZfXBVQ3ClH8dVTKE07rrRToHqil5irmE4mF PNQ450rdPJmNQnwVDR0vk8UyXhIXi7p9Ax4XVg0hEVbDCrfUrEs6LDipBqOvlNRI9AtxG22JzF1x 2lRFar9TSaolJkw1hj/a/vBH+K1nH93Vv+db0vlAWqrHfe5NLhACXfzFQvt83ifWgnC+Wz6aJLPO UmKiQ9JubdcAjD2++JC4WNfX3gA3ikll9HaC+5TCAd/3tGSJcv2DyWeF2APXSXbrKD0VQEBuLAB7 VkfKwSwEW5cz12reUjFFBlRO82nC4Y1rMvaBHZW0S/+a6z7WrfzAI0zbmoWMmrkt0CR1gCehIcAL qu63kgbucMAMwGSlLA2UOQUgHy7hDp2A/+Td0stYAVyzkfoxLBqYP9vwFK9c6X7ygBphZmNUmpE/ V1bjzajqAJxKMoruro0CQ70hdPJh1TAkAq+WOUzrCpLf9Uvjmt+m0Ke6bTpuopiI3BUM+fG/4poj zI7HAMZ+ZuPasmd7+jI6GPVGK79UefzjXWhakpKbqCsy0Bo+uFC5l5+DiO2vFLA6NcLrYoidyWKt Og7xbO+dFOXIxq31PG1i9zlpf0PYrHc5zRavKSf+vK2ARkkSpwwMukUmc9N62CeQKA9cWCz5O+Tm 5QDRvRUPo6KBKvV9Hc3JHTY0r7i1N4mIlpcboEs6B63ieNjiWVgkE5QCg5m3cSlAbOPzbABc8U/2 WoijQ5LcrawDonWaEEztOl1nnl8PCkH3WTbtS8lItrRJKREDUYEThLWFxy/Crwf0YhMbqIsHNtF6 hIqQF9nw6X6p47GA465bHQzoc/ymP0HYcsOdN1xvC5TMlsD/kz4hjA4G0E9IVPeD30OwDRHKG7xx pb+RzJrj7nRxM+0K+YWR6s8DQq1b2O4XK8ZIoTaDoiCSPiA9eTT48/MaaiwD02vz7luDagm/NKjO ZqNutOpObkgTcn2cIJCjAftxftUI3/HHecKCyrhB6QI6zVdw/Ncsvrpa8Um4bG6ywhR0zBuRXzl3 4KoKK/Y1U1YPrNaDHnO8VfQIHkTvgEW1MDWbsJkjaPkrvJa2t2ukuobmUe9MCL61aRH8GAtU/qK8 Os2L3DL3z/HHXA0kGW7j3hqQp7EfvvX1vJsT7rHAMUM0JHgkt8g+oDIT/mnT/mWYakLagstj8bT5 2yU74VuGycoy/6POXFQkqPXi0nvfJXU+TKc+cEbvi4j9F/zzUmOgYoy+5kSd72uXn/qmw1K/uLCx hJvMAgGiqMbbwkt2hMoAzlLLjOm63t3aJUE6NYllHoUedS7EoEKqGvTdy2mjlAI0qeUhnOct/wFB 0AtcOPOz5O++qxgmp4JUJsPfxCI9QbvRLnA29lWUGOVxeKAcYI8oqeuaKNXGx9LKLHRFpQxXY/sO WtLBqK4oAYV83opy0wCXqBNc+XwBq/CtWF2RqoZ8SHHLjvfA8SpSEnvMGu4K+l5Bn/yrDGH3p6BU fiHAchdKSXH/xgwepOloKX6ADhPfci5s7poqBCatIzHRtSHzS3MNVi1+eYOxeCVFKFPr+I3YfxoO n8PkQIZVI5SvS1UBhklAd3tLIPTqe8r0ZlgUlG10i8+7x2ERjCQqDtISGZ1uTOKh70od1qJpmN/Z C+dAAbZSFwwDEAVpor3QMdm0nR2nUAV1DW+HEsF90qH6NSauYXjP2c5BtraloHlDqwkLIi9OqrhY ltjZ/m6y4XORr7Q4H4gMUixpK2LN0MQpr3QWCI1OwnMGxYag1/ysQoMXWN2H8I9/0XeWnwD/R9ni Cw+zdTiNIqdaJwhcttTEDHfn/KSppM178sIP2o/bN5S0SIlkxhA9JVzSERNPyShIxn+sJquGXrlf 2LQh15JMzrCe5I1aS7r+2rOGmYuvx2Guj3ZtIdph22+pITozXBbmLVqJDKe6DpCXWtT23dBuh4lG Mfg+OdNjuxEixpC/JHK2dkVWAcsiuyZ5lf2Ub6FL8P0ppSpJSKqvhVfBBePn+D5u6yURfrY3Rvml 6vtoCYfdU9UkEBAzkBe0/Rd1eo/uxUmhRMbVp5BJC6SkQu+RrZbIo5H7fdWu4PeM9aAIHdPxY2KE cNl5V+i9Lc2z/tUpUKMF0iFCxFJuj5RIzDTnQxG+U5JNYagjvcxIeb34UfwDXhODWABTxSa779oD ferATcmmPYr79hesmxGPKr7qWI5yqkWn/Sxp7LGn4MyZR96Oybmo6T0rpiZxbxHT+SWsWHGt+O1s KwGK3XeM6SPa8OR+vVt9MQ7tIufJRQltDJH3aev0VwNP0Il2BTzXnLA8gfLa50DOPAU32Co5YkVc GgbHxf64+NPwhwokKOS4ney3irX6or1bRKWZ4BuYRRFzhhNSNnZbEYox6GbtgnjrXf+ZMqtYz3P1 tKs7fLc6zub/cISiVN2CbEEXAmLlTGJ5j8P2GTJIVjLa1ZziGn9XiBpDXv9mAxkgBOe0QImVXxV9 ZlA26o2vSjC3N6k0GtiwTPq+ACkRhsJL55bUQq0NzE5+jUwk9Rm8dsKkXnBHIhCYHK6Of6j9OgvJ A3SXaY8QC6c0HyINPNHRar/fmb9sjiVkvxHHmSFmjQq4bNZJFv0Pzar1AdQCPX0CmAzGEBm0EWkS lJXDxR0apPAj1RDfe5P8n6pLwK93aBJqT7TYtiYfImR0Mzqb9PcoSuZ63XISi5ygLxMOZnS6UNB4 UZh7BMvKucyXIelyaA3IQOBp+sMtHA5BnYvj8O7S4lFQg2Kc1zCdeOhJ9PpfImY3+mcVmNAsQyvp ijZJ54dgBYdlOmQbI4trD66vg0GkF8ZU9aazA+LAkMt9RSRvJ8BUKaTbMrin7QtgG2GtGOLUcLvK gHwJagtfctdSLZksD5gTWmoX5tIHTA8hjmPHi3VA+AorlrXUQxxrbf+fPgGdsxLqpkfZJMeoI4fu Ttzh+nsO3xMvJJUF248+KVAoTSc8Q1RGnihdr+gxL8mebvyVsgtc+bo3vvmcCzMO6nDUH/WxZh8I 1ESmKxRWfxbk/tAspNpO5ZljZPqyiUHST1+Xn/Irj7xTDIA0bcc39lBl0mRdQ1pFQYdl2ev+2MQO 4EpTjaguQkZ0dgmHvOaAwDRupBadfDr/BlkId3uo5Wma5NRmA24uGqX/l/5fIU7yX9coChZYAJay jLOiDtxIeTeBp5DKNEHxK3acmB33QGZvo1BF1k6Rv+gDasWoTAk5KLTjoNqy/FQ3/gVutFxxzZ3o N4Y19bCL8QG/Qjfyqj8SBgT/V7Zg8H1G1LsqcV0FmAgFZtK+RHVZNSnRNyoxTdQv3iTTUy920eEI Zwp17A1hIjm6YH593g+95wHy5Ea0mkPvaJN/HcfZgP4X8QU1B2UPNAa52aKgnsJuZ/rE64upbL7T SlXZFGLo5DR2HbachXuDAJRIp07eryPT/yER9HMYRkqyYepPIBJVTQgqg1x874xutWNz+TXZUUSj +jsWMWU0YySXRvoYcJyJZWurxzwssfDe21WsboIIrjAONe2acQgcPFJEFt1NUaLG+KVqBhbKkBzK JtzfDwOxHyjL3DlA+Sv0fuwBg91EkoqqBakLbjNKh7QL5M0a5mW0uKsGtL7IsCz79pXnmo1pUsRP 5rugSEOeifdjsREIdMGEI5CEBw8iXdRZHJzJKuvMCe9tjntPm6tdtPQAfBGGqZp/0YeDFV6kLxtU I0ptJRWf6gzKfwaYgwcuzI4PLvr8W8fsf9K21xtaS/C4Aea9yr3PEw5pVgxVYgkGsrIa98wNTy7K 3LsQFRQmdbFQcZSzSMz/7XUIG3zBACh4mvMa6uAXPe+PAeUwm9oHJKCUUti4mtnsUCpL5QqLXnap DK25YzKf6OlYmLp//toCcrmGPwPQhkZRVoHMkMaWC5SR3CFwlieqF/pgiCQnzP5hEVbATYkWEO/h JQ2f6U5H/91pAwBJhJmY1W8GYam4jqe3tKBaj+x/rAekEL7FBM+LiX3KYtw9AWNMjcrcJ8kbprvX 2nK5wSYqDUGFFhneea56fvelxGxVln0oVDapuJH5FtIBHQ4UB7K6iaQq3itnq3Q10PkQX1OYQx/K igdEK8JiQCiib6FKBdv8huCrHQ0XKZcMesyNHjsGOvT0q+xiW/8Q6oKiT/vdS+E7OopNKHhiH6B3 8F2hcK9pq8SxrD33uDO9V3yBJJQoRkIYHsEiyurHdII6y54AWgYWtOmX+sQM0kMXm28yOGpxngmi wCf0s8vjIw+NkM02lO7/x/IksGk3r2cn+deDs03hWR2B00yudIsMIHquvNYzry9SdGmLV6wfIy64 EgzQmY6dzK4ch65S54xGrHVuj2kRvQVfx65S9ehUZ6efmeSv2RjPXd5PXiCvPIZSG2tSUm8BLAiG dwnXxF+CohXe8twYBTOyWpo/TeUbgZJDS6NYgf9BD1vlV3XkcpxSCF9R5YJO2hWqtCWsI49QtCO0 F7Jpk3A3tqlq9QQFKQmch065ITP4B2bbS0Byol+ntI/49FOxqMin3X3sQ7MYgF5YnVGFVKV28ZK8 i5PMrg25nKkaY9prhkb69n7J+dL8h2Z1rxZd+47+Ny5o39Mar7lvpsqP8BS5R8X838LYzhcoLaaM pcbGBLD92KSGOxci0LhEmG7m2VW6WsTWe9mTGyOMOgXJo2OyXzepRT+fJnnC4kj+lUl/GRsSRJ9Y tmaIs+OsWpMQL4jXlvBQ36URynf21urum587Ehy99J4ff7gQQLI+PtXGvbmYVGmbTmvQGxQ8tvxp KsgdEqHxx3ZyM8k1ps41Y7WedQIXMWuZ89nIdtAGyIW7APHPmTzcXt900R1uPDWQolqEbRQrx6qn wTLkWzF4CFOeHwK+ipbJ7bN4pia/Mf1jT/xd2BuhW8dSwTJ3fs9KTK5nHa1j/mdPDTbMrNzqL2DS 9y/cK+vAJ7ch/Ak4xi0avMqQ4OKkm+5b8/roPoS1ZmFxUIWONX6QUIc6jQA/6I91o9AL2r6S26Xx L5ZDD3QPiKnbmalxT0hH0U5gd1eJ8+CkiXERVoilBC8TjFiEVqIgLyGAaZjzuT+YpV80arKzde6l YrW//za0HUg0cJSdJDuLRQr1b/s/iGRBuX6CcQGKxofSaA/8UVWMa6586k5VFvtZqaQUNyOJwE61 xr4LjMOQI1iBqbl+Ga/alagjcDVbxWMupQOJnMcXdg3Brj7mCvY+5uNVzVxpndRwOBtfHu1vLjYn KHPZdgf0VFtvcjNV8j0+8OeN1r7yXvxyK/dNrD4ZElBu0a+wikaE1hD1Q1oY/cEQrj4fvkGapf3V /zXzKp56fuCKGLClLZzSef35gphAkofwjlDAQRJGHBmLJ1rYqDHggapyT4am3y3UI85UFLFkrYYr t9z+Bcn92ca98LMOb6BPAUfvy6bFu9SyWcZ4quhZlMiA1Yqp8jQuTj9Pm3J8j0bOLRIunOju30Zj /WWK9MYSxUF2+GEKPfns3aG8PjKKLzHTWNWyFCWRQtsPrpV9OJorBPDg4sR4Se1oPiBjnZwIQ4p0 hb5JI9QxqHF+6J2d75w6nSQwZTMn/f/kyEtcDjKUkEstPIGc4RNjcMji5Ehy4ryTZVjr9vHhRMU3 LU2WhR5phrEMbSxNqbepIiaCeVQObG2kXNeqsDDgH115XWiaQD8y1o8TtukeOGAUoE/YGhJCw+uC B0fD8qnmy71MHLfOjlWx3s0TLOxVqcAVmR5HY73uQVcbY0OwyZI/RPdl2ZTvLSk3mSvP5mLDRalY FUY7C0IAEzVBtq8YX0PDFeXcj/gdb8La+Sw3a91DnkrLQN2H03JUO7+V9ecm4+HynPFQ7A264ApN sTDY4TA4i+N0cNaEiVWFkqwxRJX3xQGh+GuFD41eJkUOc/atBqBIOK/MoYDlhM1twjbnQAN0PzH6 g+fQjv6RYEIl2rbw9tOP6eSeGKksTiUrlVU3jmOJJ5C+n3ENN+ztOTOIPxHkv6NLylhyiQUhdvjp AcAOCdYc0IojHmfa1RcIegTcn5i/Mn4aY2OoWt9Pz0ZLAbdmDFCTuVUhA5lKHTXt1RhYKzXPcs6d 6HJyPufONVuX8c/xn9TF8aC5wTBs36fWO8cKHMC/Bgr2s5EbsolifNPSmYDipmldOvwaZoIv2+cc EffKIXW4IYXbeWQt567EA3r0PZvq9DycSoh1Qht7LG6BaYUjLEF9ekQFqRV7E7NFsX14Gxt3PmUj zA452pM/e1C2F0UFeeYT39gB5eOsEA2gyiq06xhuGj8NMEQ9oPX250CrLuaEBOW27QN4XlqVegsX NoHk3LvdneFyn7Rdqu8ugGdNJq/p4BRHJWDQU14o8YEAGHKIjEcC5cdDpTkt1lF7H6RnzIvZopCB Uua967w64t7WpN+N12YXpgeYbjuAL9HTuJyz7oLzVbraFK7jLMk9hCYUT5q9u9fGvh4WnlT77afp dfDWH/IIROVGRlpzkFA5PITzS2H1zkpK9Nc1EUfLxn5BZKAjjf9GXV8GYLMmEgAlEmBxVfYc15pd cj239NGNS0LGD6e/HtjLkSA09VlnzVjbQMfcqpDhQoETt1tQTprl5CZmZIu8O6CPQN6ZaQCIzwwH 16WanWJPxjEjiQ9ZbsFZ5gN7nkqqnU3Fi9HD+JmEHJg0OtPucQGef9Oyrx9Duxysv/M3c1UyMCKS BUBpaCCG+0g3P0CrDuDX87G5mRPE5pDCEMexcb0Xf3PQ2WGms/6n+6YMVIWghOEe8apIaWw6n8mc QH6pUUUJWPp8X5Typ3xm5atN56hIu1NfhRR6wNEHRvMjLNdQpXevHZ6FQwaQKFGWt5PyFmpfpXa7 GLw/y832Z82lbbCydF9haKLU7ow5SSfYknLXMDUERhLMOcs6hfbKC7YMAqpuKa6TrWW3Z4iZyNb1 RBfope0DbeivLk8vdUPBrkrjuHid0Y7FDBaVGwLIHtJ+WJThntQw4Ru90HRje3poZFpHxtbJRYoV 21uBb3Hrr0dBpLiR6xnXm8bFpjXr9Xrwi7VGx+a9RSnp4A4IoGOzdKVijCJlUH2MwZ793w+OVWaF KSdNfPMPLqzrio/Amv/4ReDXCnQNLmjCSrA/m8X+hm4OF6/bRQxhYZ8hwUHmFL1QvtLaKklHXaYt jEdkZlmuy81Jx8IAbyzJLpNXVdtWH07HmvTTp2EKjNi6g6qIFzbSXfZeAUZ4ufdPbe7RERb57Lx7 240rWZ5/KasJ2Ri5kedjN91ImEcII46wxpyFKhhGQusGJcvyrt+nmYC8ZY02Y53cXWVa5o1viCCh NQ8hv1r4UraVuxpZ2yo1L1Hdsop9/SAhQ2cgm5U2akgQfnXx/DLjh380o7eWvYgMfEqsPFDgcDzM FRt7wdMW/xDBaPtVsBScxUYCxYD5emnnsskhV7ViCBqiMaaePA/RYwGvNFjh0+10hg0xaIYC8zAj Mzjs7yr08mXq4LXYCTkLOtIg5d7sQA3taC6nZ0nmSY7KtEh+aUIMWzP9JBu0ss/WnNrNScHs+0tA ulZdIvMyWvt71v5o/xVa6DOg2IXHZ+604jvzBXZYjvld0IRK2qps9noJieHQwlPnpWESaVyOmtXW T/SRaAI2IN2scw669rMn/fv8knSNwMVrXe2KmZDxO+tx5i7zINzux3VrXBEt8YsdmQHTOOVuPodK WvtCo0/issdz/iP2KcXqNEYB3DtmNCkMkTxRVyZhuovwfMqoVfim9jLytTncQtQnHkNoUwIaRGUU MGPFVaxvP9KnqScjy/Z3JKblEDKsq8qdM6luAAW+N2P/T81xshn1n3eI0qaA1CTQV44e94XoqcwQ ovtgMxUPGuUNCdoXpLvxctbHb6kugXRwdejrkLxhOOYFL1MTRFAYMSccJTLJuuHfXgRJL8QL9uaJ TckIcznlZ5+VOYsnxg23YIFv7e5R6O0KpDag/bi+BoO0Jq9gmzFd6DcJ90t8C7VDuc7McZY56OK8 zWa9zER/9ZTU5uJor/OV1erSh/ppeHzMvNv47sOkOPPm+h3bhcETc7U+dC7oPXh2D64RmRXgzz16 rsq3B1giwL5vNjKKFuKAv2QcB/09GpLWCggI+MWV/nx7ZVRBxDADQjkVkHORAiSsSorZ+Xom4s/S dbVEfFHvSAo2c/MA/npEWNpsvklVbVVF8NBIXt0gwzgSa/Jywvu9k4ricnmXKdSryvJR23hr1EJd YYK6gEn/ZWbRZ9XfPd5QY45x3t7pYiUwOrS40kCPNJusRpsiZRJcDqD8ET79wnZMuV6YPvWj4MKa vMmI/A64BAVYs5h73VTLAyBJ4s/byNmMUbo7OUvqrS2Mo3TKZmpN64JDYe1AOdhULgAhqKr+wUe6 e9/9uGqKKBpfFIV4b+pB2Q/QnTxxmD0hG8iwoJmNvdgDYo7UUqLj9P4tkSRA1OxhcF7IDZb2l93C 7UvmaEH76mqN97I9ehAJJ0jUTz5oOLWffit2mSWncj3gmx5rK5xXPfQl5rzhODdYB4WDodOqK/y6 cOrV0rbsoRdWNe1vt6V1CvK+DZPuYq46XMosw2YsiS0qpH4CIHGuH6Cqlf+As/ZG8Ri07QF1CRaX Jh+1Uae9q6KsaaWHLqj4Q+gznbb1vtLaHcOjQzTFrSZ1BLDnWa0xMUYr9OgeixPqttF0s21WJIJQ OF0481cayTlRu6W/aienx8FvaJT/mX3Y36D6JRsHhgPcjfVkppMMqOi0P/B6iq2Cn4JLZoRziz9Y AMqX0PC14Z0qmw7J590nGnLSkE9AVDQe7yVP/m5D4+E3YwJ5vWzA3g57Mc6Y8ll+jlDKpKWOXMXR y1LKmMVdOU0Kx2yOKiNLQX2JE0IRihCAyFns5gWLeZoehYHcikm8m8er0C34IcNGOr6xLBrXFDZd gpKWD6O52snkUhnpedQQxWbSiyV0ydFEvUZfOTT7XIrxE/NL1r8A+uGrUiPS92EBYk/FY3yRBi35 llQxaGxO3M6K/DLmJwHVbD607N7MVS1fNcluu9xhWUJVIV1cY/zjp/wUoH/VZDlxVA0ZVwSZ8Guc +NYdoV2T/QnKxrY3+hmNONZMkps3rqSx4RWyxV/qAxnJFOU9W6B2ul2DCDMO7fMsq1SftNbw5Maw YXiV+fGUUevZ/5FhhvDimWWs8HPUFqBJKJ4QtIxkQHHsaIWDSapf64MKmt2Nr5nRwXqUdUH2Kfs2 f+N7/USMbpRdjvYefWEjUiREcVSoDx0gOMwC1cCPu8LDZ0bZYiChtkrixplSgoiNwbI8MIGssPTj +UKvj22Z8+Bz94+Cy4AauZN7VlT+DKlJ7ca1m/xEaatzEt7vHDaZWHZpjHf0C6ItKfJWdKlsY8BW 5aVH56sk+um/zDEV0IHs1+B688CaqTrKA+zmVheDi0iVtB2x8di3/Wi4hkGDmIufiA8Pgc1dJBcN +E8gsvGme+SxbuQg88UnSuCrLaD2KxUQadmVbvbw8OiYcvlslQ2uhAiFLnZCtOgzg7iFe4veA8e/ X6I+UR55FsiXxZkk/M7MECjo4PZjx5e1CZE9eYXx9/mACQJj7mYiCc3n1VL05pbV94DSgo701oui iHPxwfYJadFQjn1dUsn7LOhtDAN3wn2DbevA8Mcaomf2vYK7ch3hj+giv3A3R/DN68yeDW6Skw7f 8AKLB/xpAMmbpkmGdLnIM58FiDeRLVRZp+0E4ofnbdz4gsxA/wY4pJJelYuTKBPKyCUl22OKsfEl u9vgN4PsC+9CGH0zDWMjsJVUK4a+1q8FWN0ArlRFCA3SGM2Y9x++Rc6vTrRv+MahoBgRgPXKIYOO 0eUVa1Im1LQYY3a6zNviCgiwIfOpoyLdOarL1k3EKvhaZPcDZ9tBtj0rc8duEr5D1CTnENBZCvso FBGpT8NtmghAxxLfRujJppUSf88iz4aTuEg9nRIRAk4AgU66h6CFmWOctmwOjgF8r7b1eaowGlO3 TmiF7X0i1ZFTuIKwiRRd8HfwIm2vckTNfPtpBcv7Jy/IAvzJZeAPJ+l+n8fY26BgVhdxzuok0iXn f6X3C5mx6fcwB4AVOvm8m5LlFXmmsSlsqBjR7O6g2MsbxCHI7Ff6eUCa5xezVJMF9OQs2JgT2ohL ryAcjKF5lB3e+wJ3qLe0A7JwR3eN0M+3m1096J5SnKzAbejldWBjg05WmK6hrIxkqlX8hElZhF8Z mmS8oqjJZhizvMz5R+lnrNrQBGBmROYFqEMV1D6PxElh2hPiUXZ9o7TsDDfNJp/qayEMN1tj2Szg x+AmTD6B/81kQNh7gdz2iTsz08PHXBsnJMYS6bm7Eso4+tmXcJxE6SHIBOWpRIvumLau8LdfViVA U6nDhbehvkig8rUP9ymshHQ+3OuexHPWOUSqvXxQHUWeNwHMMmAwhcrgQ7Sai7waTPpFjyHAtFOg n2YSrvzh83pnzKkXnFywlbquZ1Nij2EkG7KBf70tDxWRXqnJKEULVIGnINbAvK0OgrtLQFwi97vk UnF9+kK2xPJL9jPEYyDMzGk0i30iUV4yNCuwIGUlohVC/7k9tteK6AuJmqM4NTkhE6I5TSfKhgSe yU1eEfOCeF4JJTlPQgtBHNfsr2fPzqnfK0DdZHw8nTMH9ABboJMX1jkBS1j6hSpmAHdU4Fx3X11b P3DtJ5ee4yp/30QXM4zO3A7d9xYjxFu4J79ZtTKFiQFltIBDm8ZkOxlEFIQKx21eepvqFbwL21aq Dt8azFyvSQipWQHClqBbCDvtNd4Dx/ikC8WUlf3s0c6y3AzCh8VSEU7cD5kn27D+7DnOTAXd0/Dw sl6Ven7ujWnoHJz5IuExfNRe3aFlFk6QAynU8pB4k7S1GxXr7Gr+xXU7jqt9vrxJcWaewrwHPtVM MFSKZ9rnL0AzqbiarMubmO4ZUOWGibXEeyAMCQYq+TYpLEOFHkkHDr/A8O31x+2xkBb7M1mLf9fM 7kdDRfDYw6zdkYMYXH+G71ZhRFo1GP9CkPl9owa0tXNIxfvGP7BE4qgQBKrOvZcpiIGlZsmNrsLz cpvS86hCRk94bq4TKDjKPjohSI/QRVb5rCCiw4BTZdGfstva12fCyVJft7ZSSeY/DA7v+D05OFU0 j1YeaDfCVJPk+9aaM1Hd2vdfrAhOYth/z5YbfXeOQ/OzROiZTxSo1UEgcfVnXZVfKwDSz1Iyqz6x 0mCxoEewuj2KLINInCy83Pl2q1B/eVqGSSq/EzfALS3Yb9oKdC/zlO7m/yJPsjXz6SlDEgN6ZZhd eoQ5zrYyL/HzHGmPMWrfaGcpCmtij7LqeObY7oBVgTZcQMDjBXGUVVIiAL/2J44kqVw39zhzDTSl UEsjMInhS6lFHG3CVPctrXD8Kzr7WqdAMH79Yum5bSkURE2wwc6/4OPNSffH6/jWz8mSmCZvvOlF h4tXsG7OPYnz/5ACCP//xrBVoKV5n/rvVcvLIvFkCu8Ux3GhTk2L5t0xIMykQuuSOUII7qAMOEDd bDFwTsMGT2SZWuy4Bf+g0zyIStF4cZ05jG8U3V1G9D3FuUOBfod1QMrKwcZAqDRs/eGj9yIfxIKb f0XUL/4SgwMOinwv+jml5IvpWlm8DF5D5DpVM5HZUssXf5nBBWTQt4F9Wum+1Aw/gx63vdqhGnei sI2Db+bukjNNZD6TJxml7IqPfwXoGPvmME/MLVex1KEUpjLpfiDJSKFFhmXpTeApu011fnaOBf2X WnsnQ2dACOYU4oTp3/PuwKE2WHuThIfm49WlvbIrlQ7VRYxHQOiy910XEeITgxN0NvhbIUVhj7KZ 4f8VwhrsogYVmFLUD0Tfy22VDdfPcl/56YDIJsblQLTb5oyjRZ1UqIvNxJ0QckWmumvqPp2A0xEy f/xyJb1/tgH/hCYWhODr12qyskUSYO9gxlHn0YVAFcI5GBjHEecv7F/sHEb1sN5iguSQdQb4NwyQ IuwHThgu3LmRUWMW007wGpxOfwb0aPDaxbKIyPvA6l/xFFuDkMKHQ0K9JZdWwXQ5B/mcl69/Gpz/ N+n/+DW4/cPXp8/+7h1jdBLU8x4cMNyDWeQQMxllU369AqJTXLv0OcfSht5lSHE1L3Xh2ayPO21v AuOKUt2Y5PFH3aQXnEnInHKWFau4+jvD7KooC3mgja4pKqOYvDfomCqCLgTtfAE5+lMnEgDn4VmU Gex1rR8ErPgx3z6uWg8Pbwt0V1RTCuzpdrHECy4jNlyPRlvNHsYiA5ofeoBht6oTFXsls11Y85jD LlvVyjoMeG+LBf19CG+HNnOwKpDmswC0qiE6XELuGRNT1g11G1F+O1VG1pRlZ6ycO0JSErhWWTqC wBJzu5zEZIknuFgCpw/CINwYWQns/bxXd+KDw4N5n2QyhUBrrpVtDgDP+2IM9TfYVLIEebW1EZ4a tFt10nODkulc30Ypfe+794+F6GG0S6ndvYtW4ouqR25Yqc/gaoqr+tODXDfj3khfBVEkspfrBaCy e+GW+rEp2+lxhXRR0IWkG42GBJZNf/BKFTMdHPkiv3o/buzMHWec0U0kQItkUNBipHhaOXTbcxL+ I48uTDJpl11RsbWp1INYGqJzakCyW36tHSwWzRq6iqZ2kzkTCz0A2TbPrPYmTe7vSEiqifOuKwh6 KYtc1XfHQOcFHWckqXDgjniT3QVx/e+bYHK7RLba3W3bR21tHOvA2ZzJnCdTNvlBoKfaXB07o+hn RsI+N2BA5PvqwCkytTRFbzxo7wMrxDl8EX6CTrKITgRv3p1BZQh/vt5N6EmuEr5mMRyZ5cA2759B tX7MF1JF37vrP6lNqW9Il7ef3NMzhonq60Y1ARqgjJZxpgxtSL2q4AQDZ+O1G6FKIA1znU9WPBvO LKmOjVXxwCuLrVXhbVVwlR4oQchOoSJIVMZismWeX9zkrTabZOvsWKanhOiwQkV0++2GlriV42wL RCvO7cbiIby7exZ0LrHr1a9GHc3OsMY5l0JqLnB/rE94a+X4WBzKqvmBZVumx8Q6bz3F0CwWkWeq TAhLZ3K6Ms6p8M0HiXh1QS3Ir97mVm4VyrgZ2BQf4MFJKwOIjw0cSp5GzBd9RAsHES21anlF8PPF kFhiawM4KPjIRQKS11CxbRlL2IAuK9KghicSnKECshw9qQ7bcnagDQtD4QKClLTKjstNV7pbC6Yv xzSX/Zzw4mlcCQiXva2H2kIjihjOaO2HVLnkIy0zPrJyQ6FjoB5A8hvU1MYpRnPI3/l0m4jUdHLg 4DvTAd99G/f181jybHl4YuW6H1sTwA51D5I5KnmThSaw/7r0kItvHjeD8wLoAnmSTXbOoqmfidBi 9MPbcemizhAF9K2Csio1h8puvG3a78qEoS9sPldxRssJ4yIl292W1H2md3vv6HvYyV7izNYpKRtx 2ubnrNO9TsYTUL9d7O+t23wn8/2VpdgM4uEHPP7aun6bFULxrv1Bps6g/NFafMYIuIHSwtXapn0u PDLCndBQMR7WrISP8NWHSdLIOI9HhH51ehjY2ZHtLr0ImYUmBW4VvtgJVV4sYN5ZDculhLuXvXba axYldqKKp6gCT310q1zTyfe3UcjuBtkYrPMFqwqqLCdtcT00BNBzW7GFS8/078Gv8PjZBA1bLtvu vVvmtSrpeqJ4mcUVJckiYsI0tdLcgTDJ+p0HKXJrdOIfTMeqH0AiaS3JbTwSJJ3eDuUiumn3+7Ft t27PLDBHsDMNg8yM8P2gzray+w9CtZQD5syqh8GysnJd0xEon6JoQeW/oy5X/+1gcZcTxcxqugor uvr7vk797mHHCpvz5J1dNPo1GqJHntNg9lV2D8bY92aPc4vhK/c3T8XxZtlzakEf4zjfaDK4Kxxn U90h5YzqGz2RFh7RzeHjgr+6SPCe2R+WTGOlLc+wf/ttgvvkx7yDRhzUK6ZjugUjLekF+DQzTWkk CUiyo5ZZBLNNSNn7GDpjLG1qH/EH6UdSKE9NIMTdwp0FqCIz+KNY3i8HjqY4NSBDaBuThpWU5tfC wsrjus9LRaQwpHvRU+FfJTdvLjYvNtJLExisujPGHOEJB8eEOMHPJ/tsvjuGd5kfDm6MZWLhaKE5 EntkILPJxtST6ihcWdYpURQPVymZ0Z5nJvFoEhjXIR87rm213JVY+tiFtv1Dj+A8nV+778SEBkb+ SMY+gaBgbv2vkO/JHdhbUntj8hn9+EAqKkavRMtl5LsFqggAezA0SFTwoVtL2bcp1yCWcrTH/DdK eWY2U3Y8ZPiD/c61x/hOdiz8dweBmz8s3Wh/bBCKb++DtplxaQq6Dz2y3UVLwivgi0enm7KeSbdK OHxcM1UKbVlfN3WmIIvAhlXslLyXJijabp3+GAwAsPn3icYuR3Eli9fFXatPil94bqAeXLNvU980 DXgYOSFcWoAMJzW0EdRzIS+guxpyfUqB16sWKhsqHwG9pPluwqchlukbyfNC7nYqeWpi4tHVZPzs PvVJov7jmptNmaN22mCRQ2YQkc7U5Mk3XB8cZ6hEN+S0gPiaV9aTawhuqHcW+p3VHMZKFbnC5E/x F2a7QY7js046ri4xyaZT/+nOfGGhxy//VLK5fNPyNyy9aAERzQXBTKrV2fv8KC+YME/AIcfAqV9Y GEEUUhefMs/Cqy2hXIH204JCj1Pn2lxiIgz0FNbqTc+DOMsV6BtNcZXhRhgJu9CCysgXle34Xzod 4XHDU0tUPeQ0GZ+aengfKVzhz33m5DYxZW4w6OY3327gj+CogZk3owZrbrkYJcQ79Da2bU+WHvef 0quLXYSsby496DIxbdkFG6R7m3sv9DegfyCN8WYPNRkXKfYlssnt9ka+oT39QnIkM0A0YUKcao5D grGirdRsmCDBziez4S0e1K6AKo38rpSWgLiM2NIktFbBAkv5MZT/tFhcCW2rQg4by4tpzKQfemve izQQknQdTcMALudVzI4DR9D4RyirFhMP63iIohX+Eyb7HcTzVEg60qSLl5ULTavpVkFEknhDcvAy lvqm6aT/Lrx5P2v0yWVSs6QgtZoQyhvh+G7RP8qf5stFFdp6Ti+/v5LcCS7ksAap0ZQraOuTqsyX 9djwzhh8RWuz8rKP6iU4sX1tzfErGi6MBb6qz0c8h5ZpJ5ZI9r3FHReQHtzlsu8QjRHMc2p0Ggwk Eml9NWn21IFMfpSyhDU2B2tUahqAUJUgqxo7AtQ0KSzCFoitCph5GvnBITdl6AyLowVHdb0E8/fg 5IbiZUJ50Kw0soVA9bvEP1A4bqukpLxbj6Okw8hBvDw4Y2cyLku7z8M5urZn05c/HqkM3eBI1WOG k/uEUezY4McvitRfErAC0fSu1qVrwrRq9lOxjzO2+ZWt+YoFEIMw8IkgElJvI6qHv7J9sBCwkpvb mXrsywD3t8E0IbI3V4M57TSlX/9ZZKWJpHL8Mg+x2jTYemqxLx253UssNiRxf+c8sTj7JXrCg3yM kdXUMFy8NsCq1NTHZpnC/8yqwMJCzCuFqIW9RnLEBnEdM+/L3uo34G3fLGl5HgGnhuXN3n+XGUVb sdTWQzdJu/D539n6IqhfbPwIO7YourKLB7wely42XkGeF2AV4bcKfTCs/UDH8nFsspHwyH1ZE+p9 VqxUJCKRHwsMnfuzfJ7VCfavDfnCyWp+Ib1uPh3YFVdqeVPk9oGZ/t2YYpuod2957LQqqoWBn4V2 9bkp0a+XX46NWo+qb1xZ9rfYMi85EwwO7s88PhnGhlsz6d4K1Tu/3KMpFlrD54zqesXZZK1iYCvh TXmAJXi+B4Z7tjKFvttLp0ISt8IzMjJrtTJFZefX2yIk5Gxa4jDcXMwlK/VXzRjQKKBTLxte9H4m UHrMhPk7mq3LIXFEtoTrK1wSfddWKhp/rXS3wZk5j2n92rBnrsUYEVEstJQhBeWeoQLfLUCYnfls KgTKmMX1h+mi//E3+Fp1W4bv6O+2FnDkUTf4HUVp6loh/3HCxgtv7XkCbBujvZeDQ2H/erfuPigt MF03z798CfDZ477OkiSJzSH1Ja9Su3rmuLDse7oHCadnr3BnTXBMX9yHDjMHp9Ea/Lyl1BaFxOIN FmMmQrmW1lRRLLODZ5+kMNFSNNxUd0vMg6tfkeRKYeUYZHvDHX7E8a5EQa3MuXaU42jIAGkz1TGw huGMJikI2M5i/wld/RJiVWZIDX11iQBxASxoA5H7CiERFSlpldRasrr/l4x/7eULTQgP36u+UDHv V9lklVdYciABL4rP/J01tIyO8fh73tBG+VdIyuxfP3Ddrk+xkKt8FCWzyf4u6L16N+CnBI0/zRdn R/xts696KiZUa7tjOlCOiMj4ZrDhFKa/r0edCgDMVwxyuNsXJgwdJsiW8RgRC/xK3XF8CeKrkL8k 2QBCAqJF4CzJ/HFkTp1KFCjLKlRy8iOLSar8px3ZE3pePiLpnA3ZqZB1axVX8w9CgOeXyEC59kqp YeSaUaDD60nhoKic7SSgeQBk4p4+TyWsxNxMI5sxHxI/ivM4MzD5NJWtLQl+FvMiiNSxH0ZZGW69 VqoR2ec5V2YqkBPCca3HDR68+yYzUK47yxg0UszW/XoZ1ZAo+MZwXWuZxTakeP41rgGnpR9mb961 4WXwHDuwsEfQZyxUxhpib5C0JZSX4FjDNyMG9b6F3NiDqsnscd082RVXW6w/myYe5GQxT6tOLcMa eJbYRIEAJ+4fvbGLFqxyDNzf0CYEu22WcXPvlHs19Db6oXfDTVKtNeGlRaYfnlJp27+gXCQtVJ19 Qc5PRTraOWiqey1bHScvbdQGiEJ+gRBNBvJNrVOG2DbJearJuySqxRG6Y5yeG4d58qhhzKcGQVMd jjq+9n7o0rh032VTek/i0p2mBQ19SW7e/575rN0aTxO7ZU/YfvrMsS35lDFNUH9FGtC1HfglaadX 5UKMx7XWGZhH1vY4mdTae8RR+Yq36Lq1AFEFf6PNmK8kniCr5DRBKIqy/3Za1YcIHybuTx2yvSnJ NB/fHKg7Me5QuJOxEnAasyuGVlSzZtRmggbn2h+FajunyzpDgKPnpwUOHiOQJZN9lmuC7A8Z3zYU ceAh7GqiRVOvbII2qZYBmkh6RGNsnPQuuZY1RXVeUVwjFPd45o7YfCPDQVOobWcBse+g2tTtrcYy Q5CIIeZDSXGEKZTZPAYv0cUJ5WvRv2FWgJIYtxm9/kbD7tt06mhB59K+LEipIBFnU9AZZuH26zmM 46pvtEuMfE9P7uqwiF+9/se7llkwBldtqay2U32/wwEr5n8k6Yr6oMGm8593b8+6oYq9REKEbcve 04V/WGJMeNfetLhINSf1UxkTy/WcWQ46ufAPxP+zY+akg8C7T/ErCtNEpXsBcncbt4zWZwoi5byh lS7HqFUIWfnNYrpBorXRnaN7VNA8fdC6m0v8K1KtBoeIvUhr8GwaBvGjvOJ4egjFSYYpYHvR5PDa N8maSr+76KzqxlDqA0jH2MvFnQzCND48p6yQRvLBeehOiugW6iekeq794fQsQaghDSfmsH3LuZG9 FBbfRkOcfPaepBCTzEGpXE0+wD+E9D8l4hpPTuZkUkCbIWMliD4VTvOLfDaLu2rrfX/orxglo0+W uo+sRRxTAi2nmgwyD987a+WxnNSrIadT6jdJBVVm2AIfzQkQ+a8WhDR1+iNSOjdWrub6SpNMWyso l/Iv6jOzwdfQh2ah1KAsOF3VWwaRZPQsQd0g8uTFWs43MEZaTl1GLvEIX/cJAIf1W3Lt6Sy/ShjQ PbzA/XUj9WC9zBxXW+xQCT1xqbfssPVYm8FR1GVjOZEBVmMhHyS+6Dl+7bK+Q3OoEr8vbZMAQBOB kBEEoD0Qc4d5VK+lrAIifEt8rjp+rMLUktng7pwf+0ZknXJ1rFh1yNKDBJOL9GkxRHewa1ceyIMe ttS3DqZ21mBGHtLP3Z0IM50rxFGuonC+LujmLaH2i5IKU/fn4qS/01BtvBZeF9aNX9NaTIExFplW vfPt0cEckoaY02H2sGQodySc17CJ8aUDUo1zwJpQ5E6+eHEYKtGaZFf3+x+BqRnaLQzUlUlYEHHw WeIzLA2fJn9oqm0hmA9BnG7TaH7iTMGo1BGPBhgQwLMDbrbVnJxJr1LfY1QbE9uy2uhPpOMF1ZSS h9pXu9/l2HJ2UCI39lHNocme8txXFBlwhgGX5TUqk8IjTqZNrGRc9Ex5OQ98ngw4N7ZeFZK8rnnx 5CUdIa6oEtiG70O1w1NkXv6PB/teqU2zZ4wyXQ2KkQK2mvq/q+aG3QvcO2CA2kVUPMAW88yPi9xv aRshK2DR1/lz4U8R93XLZaQavnAUpLZ4Nfp+wPfDsXdzwwN+ms+Vlij0eByVZZyRYUFLJ6PPaSWv lzSV8HdPwAFjHfBwmSQORaKphtPlAKEjlzB556v90/Iyg20TCO5VjUigjnsBLbCdX/XdFJuMy5ZU 5d6EbqtEgrP8/VXYyXTr8RjiV4SDtfojymfYqUXlcNLrvYmTdpTYSMHP074WAQK2Q9EisgvexzYx v//oBiNZpZZHHmxXx2Y/i55rKR4nhHMS/+xIiGSay8SBmLhhC32a5idg4wtPaPHdAOXrYfEdmjlK MV1VHbJwzNweEOh16aKRl8blLoS69vkJUSkskxGtLRepy1ewZxSdUpzrBGjbM/7M71iKDjwo/kod k4FXcJzVyL2ue2RTRFsAmADF5WX9Mp/OliScJHo/ZPZAEPieUnq2WGDxMzlYEz5vYbBFiM70FWoO 2pcSDx2anjkU3TkcuEJPnYvBQYgMHsBcVqW54BrRl5Ixyj5QGOG6omQIXe0DmTN7XYqEXXN8j9Q3 aGx1m5VrBOOMuWA357Oe1tA1zIPnZfaen2QtbhX3Bg13od2NuKYCiL5gJwQ9bqT/+MQ9B+JVO7tp lLIm+kLr60n8CdB3YJsHbYvVyQF7DZik7nfS48t1u91SSZUXNn64HEzFLvQ/zJvKZKEZhWR9xqCC zDthpFYIhCxjZ4SDBkfzdr/hqxK8lUKYMauPU/sYzwRHkfiro4t6NcpBMaBZin5qj49ip6W870Vu 5C8WPu5lfhxvHZLaB7SWd0AzFwVGVGmTmwgBAIY1aX3AAMEDgErYd469LDIxQH0oLlFBVeh/PqQE qSByvt33y2QQ7Rwzf+Gg+VwRujyElBMZMle4yXXGSjEM4FiWmqtsbHq78Qstg7oLSgdfKtCx6Q3E YvxPaDQRLSkjxgKclw5a3B/dS2tipuZK0NVrc897go8wPdrQGNL0CAgD9YxxGwRHusGwBDjMcU6W Epy5iBKQFpe0RD6W9SZ1SZyFmd00MzX+/Y23gMUrXeF7PenrdDxMDm3gphUj5h6mTyMx0T4RFK15 jV9K0xuFxPMsFiU3ZQ1Cj8cl99hBz7WjknqD/yie8B/x55RBRmpaExZ9pi5cWNqLRWcaz0tPUPrJ tTaCB5EcW45OeaDTuN3diTv/w8vE+j/G3/8xRjoTrLZJ/r9eZV+1YLvU5KsDyyrUcWU2cbjSkLTg PlQ5Qw/EsaNB5sDnlgmWYE8/J/DBi0LMm7CDzCuB7H18seSZLIGDccpZa3M+lNGOj5WjGa6OEERd m7N52AmD+Gs0y+VZ3lMtzlw+Q29+Gba1IRq4msySrK21HSzedZfOm8KiRnK6jwwUEnvZ68Zm+org Le/dYGPbVEiVgdeW78TRtHFg8rxrjVa1hbtIxovukXS9E2A/v68mkAD4XccyaKChYVqo1u0Qkael 2i6ogUOBeMYDQR8n8+uNpH3zCDQR5hcTkIQB4w99iqOFz9JFMTgf4DUI1asHvup11Dp+O82kVPCU 44eXxWvdAdNVkgZeAWlIL7kHN0fOZ24HIW5yjOKYivMGjfRyNXKT0tOQVd7EIOgBemlRGzouiPHv FxTLJi2alh2RmkU2acQgkdi6wnBZUW9LIdTFZe+K3RH8UoNUwUi6ctPx8G7+lcg59lcHhndIy0F5 3t2m5DXPYEQ8yp25kwkvrf4KFbygEnd3ZkldmxU2TxQtcsu6RnYdlxi1L+IvrUpkC9AZ/Auvh8B1 YqMJSDqkf7qGlaS6iuty515qagJ5uBCCWdYtlHU4QCaJpnLH3hZ3fXb3mQHYk5kaZCTVty6PQGUb l+qgS0LvCA68JUMFLc27CAWPpdZdFPBEQ5aNc2z5LNZ8BoPSDCmJBi1IRwyzTRUWNrORAorcTvtb W71NhwbZa6t0BdPNY4MB/3ENZqvbeFl/F2MYViUsz7r6v2fu4fCHcjxSCd3l5+d6ZZAASEiNsqDF q81bVnC3X1nnDjl0l3sm7fJZWMEfSY+TF8O66lV+tPW70G1KOqRXHurBBiAqd6MMikvbfWzRNLXb RFp4yhkmWuVdVUaTDcD3v+c0+RWsXrRC5/R+ehSKLThRrksaqAMrKnLp4tBeWPu76pcoF6eBXBg4 RlFEuSsQgSsBqcTQNCh1MspYlS/b/8+wcVMmOI6T+2a54m8zcMZ5MkgfVJwFnTehWkYhzjUHuXAQ yOluNpCDt/3ErAK8m2ICGCIaP1gpVaU/aKC3QQtkWbTS42yqvq3ZwZ96hpS+nRUdr68LbGYSASkP FBlxxtFJKjpwem2iXcbmU14iwe6Oh7UaNlwGyFKoy5u/dYyxHEhFxOEdfZTFpTvYTauo3jqHg1aQ vFo2yXEom3nsPb9ZxomqFm+WJ60fUEMlQn8SHi8Pu0OfWJZXP9LBKb7pk5tNXzQyXS/ZD3g4E1Mh hBkqDelAjMhNIT3WLEIH8RDAJkfysYtcPGMdzpjwpueTk4CrjTMnSmEafIyjICBzBdYJ8GwNp21a qEYQ0cpXfCN9vXlcr62RhWdI2bwuptlTcI1WjPUXn7Q5xobsSx2sG+XSBKl1JV63wkbQ/qn3Ro/I YVs4m/bG5xUWq0J3//N+Wa/ehJhqyx7XYY4yFukk5HAW6aeIni5NVKxru1N4pqx9UvMcZRRZ1E4/ nqJ5o6uXN92rfp1rp0kj6yKXhh/e3Os5qwu7SWQhzkya1XC+qo8bQcztJ+jQGuGyIasghmuzBKDS F1ZW2dCShjl1F9jKaKFiWJUWNMwnmt7jZN8qPK7NUowDcwEXQzSIQ7jBXJ+7Wk9WQJk2VkYt7CrD CU4is/K7T4nH8TgGwazvjnx/QmDm3+klk5DKPUzH1vf1/DFMzXZGlM0Pya7+NKezymCkwgryUnnr +gV0LAUq5CXYTsabrC7im5XkLTc+fbKvLFsaqFg4K63YgsFUTBl0UeWm9l6QmxTxkSbe9/EwW+3f 2iJes7DvmXYGRbl63q6c0owRndMCAIhIXXn4XRgai/hG1cDZ+uRyclA67JL32i2kfVTZ7XlpAdmK rmJydqUu3b3ittsGZpqAl/FwmcPghEZJbI/oPlXlmJNoZK5IT3YT2S6GvgnTnM9noWSu2PJMOOE4 KEPuhPO66MfKgGfE45QoTVhMKEXfWr8RORXsXvB7IYQiOat2AMd+CnNggQKrXPWWZcDhDZx1vM7l maoe1EclGvkGd9zx2KlqWVAAnjKRMbxZ9JJ3SdbyyJOuTS1cmlJQOWrRQzX/TBivIEJvP92vVtTj WULqqlj9FqmKGXfCgWKGOrdhT27z9WjlHeV7I/GyYdieOgL97zcdgh3/ZWLhtJ9GRuSsdTgkLtbL PxgIT7StOo8XSjP4AZq8u7HPM6eJY4sVTv086kaPWbWUMtOBoo2UM3xxP0iY5WQH1ijlipaYNym8 U30sDY6yqdynFAdkK/AnG6VogQkLHcbacpG3YABF/husfXERKTrpl8X3TuzOhr7r9pOOqkUYacXv gAQ4FV3AkIyMZSh90AUQpq/Vxw5V1E9ItBWM9n6gu/c5DP475HZQ5aSEEeT8RsKOpJp9OJGSKguh kOoi5EdKmPSeuVe5EmZHUUDWmSYKdLYYqjLoJZEbFSI8fNeXcPhu8V79EaZ7lZlqyj42WTzRByZn b3INKLqF87YPvxdSgi8wtlBxQ1BxC1XTRp8PQfVi4ejcyyzY9LZ7NGp5Q/B3oNSWolOpvhM2NzfP x0iw2ooVmk1P78UI1DYpEbq4jbI8r5iFiDPpHmhxTls8YpHfXFhsJWWWJ2yGy2u19XcvZjcfIqP0 DwlXmNFVlGTeKbO7u4QHQuQf2xyfE49zEMSaGFfz5sxaUBR+XjgTHo4jcno0p6kPndbUTEBnwQNT l25AnCKRFoRqXZuCfLSzsNOkVPu+MlwC927euqOWyiGhjyqHY+BhdRM971kMmCjw1WMR0N2I0CHC j17G0vs7zSFNFYKjS+JHXYwiMdgUw4vh2CAoFiKPAEn9tq3+IVEMvsFr6ALxeM0QSqvOOaSQ44rB 19hTIQ/jOum/Vf5nk1uA5ofiUHMiXU4lw8RlmPG8h2KkClJHzwnfeQxgo+G4PfV52hT7R7LXXPZs jUdIuaPTTV8PBh1Jnto0BXqCLlRVd3PaUzJz2YsbpRRI8fui2VLNwLk6Zwi9mtc8ZoLlYS+gSVvF oO88ncajfbCps0Aml2qfuKfYksk9SqfhTQyOLlrw3rqtuz1neOt5Jvz2k6ursASrSzaknE/EcSt1 REpdhkgHMVPA37d55NnwtcIR/MDkSG2Rjg/dAc3phPRAV0GYp6GpCiCiTISghwWyTMGRCIEQiDKv Q9vKUzPb/gd6qFGFox6SsnKr649Ru5Mjr1u3S5YpZlOhcev1hb2J4nluzqDQQ4LL79zdra7//uZZ nCDbjWYAqes9/YUn51rE73vHlX51MQPRGUw0NO/a0bzevEEsQj/P52eEdu91IgaM/OeG7uCXeWtI R96OH2Qa1vtjfFciSs/mI0Fn1HndKzPxxMa99Byrp00eplEZTTM+ryIWTICoQ+oFvA/SVfJQq/bW cXht9c8C/kwuYHCFdTFUUQtRgwYokMcyLx94fMj9cLNmeq5LNwPkIGzeIRcSl20YihTRL08Zbx1O a4LbRLnIKeqXLYXXMVR2EAHOsAKcPvaevrfW1WtZ+yF8rlL6QSXL8bvn1K2F3ejS4TRpsmcXrY/5 NaS2UTaXymcbQ6SjXeOed7RzxlfzLEY/Koyr/fcAiBENaUDWhMn/Xf6AUD39xpnhZvdcuqIIN5NP WW7jF0X71Y8I0e7Tr+krgYUtulYC1O0KbGMczE2MOSgeyuCOfJuXhfeAIqEnaSeUmEGh96WvwQEX 9Jr5Wn94YWfyUE6WTewlrZxAdR/5jz0kWiAofUqsBcbTWVzpQ+GrmZV8gVOJZkR0hjjdLZOYu7OD AD8o3d2aPiVMGXsXtRmMGYAOghOstXY/wrPTF9BKIykcjPjTvulcSPxUMOatx3aLBuc6y07zGYUx yY6WKXaVcJ4kASTK4nyiBDMSDPcw514ltauu6ldDKERd3/1YuxmoAaE3X0X+KsnlspmaYGF1GFSR FK8IPDKcrE1FAdSuV+yG4QUW9hS1BXwEdDg3bvpC9KmsGpkuHt4nfOtuSQTC4DChm/42wOQQ5Wfm wvYs/x+pxAqdepcbQ4z5BIe8rBGpgeIeRn+vrG+9OdEfBcWT/mRpeGW7ZcTUViYmxeEWu1vg/l2z /xtHa/I5WmYGpETGUdnBZQNwPyr/d5VYjNZ7glaU2d9bbHYYfdm4O8iXins+DMWmMOb4i23NZNcm FUC3pfUutG3DZVBXHmqYX3fnWAhCUDvlek++uqIhW3tunNMw0siMvr0tJ4ebkl5vvJWpoKV9qvIj 4A4jqo4/pc1mNFHUEFpzH3Ow3u2eNCQumgLTNQCfh4Zexe65aITlxftGNYB90WvHtTqqta0Iwr0D zCLj4Y7U6NfmSxfsRL2FZBOhQb2vV6ng5/hAcxlP28Y/dsiq44cW+D6ETwj+pa+PJO85pTYmkDt1 wgjmIlUtJRdohxs+LJgNWtez0TfgK6wy+LvZSO2/HogJEgpeif8dj0Qwc9MWnxB+lM15YgO8rwSl VBB2YJDa4PEAvWGDWgcVoLk77VYY3NONpT2ZbSf47AeGL1k8FzFW8c/Av5YwLWrnifXBvcND68ZL bYUXWFXD+/nWI5T2MDEJ8Y5WdfDHd+psNcaIFK9ot+40Y8wK3fqLrT6fs9aU/kuYmsff/fS7xzCR /UF2zs5nTSI2WYT572ZMrv/BHefERIjNvFff2WUL3ZBfWqpiszc0bc2enPvqxbVQhjrXz6aN7J/Q guVhErSS84lpAhiGW/ZdXNNQPqA4jXPi9M9EvvFgBojFodxQeP82qu84IvrWCgQ6KonrAAGm/EQv NXbfbUmK1xwyZgTnt0CBAcwpzy/aAmuNblJMcYdn7Kirm01ia0FqS/xYhPrOZ1p1w9DfAHvF9RAa mU1nHmaxIoNe03yIHyjNOBDZx+qopA3xkW9FoTTCuY+O9GDLa3qK+f5aFPkWKnOXTXrzKqxqZUX7 pyK+LyfQc7iLJks10ZuDBIb+KOu9Dhlv7gBqXtm8iIDPjXHsGpSuoFLE77oufW3va2RASXJMcJEK 3j1Ba28RnlhBbT+6iwpl1Ye9L3ejkpNLdJmUeG1iXAMImLKuBd2ZMZrslNLScgVUTbWfT59gWCZS jH0QOtsFFNftNbddCG9lz8dYBcczVoJpGRRwFACyNlhC89hxSbMgIRPlWbVdUNYXvFYtu47F8pMe XDq5BLqG74bx+mpB+tpg+kk5LStJY9txFtWrHbrXcbACCdtn4gZFB6xo55ZP0Z56qu+MLu8NueyO /yCQH6i+c91DZErCRJeTv5vrAoG+R7d7SurSQKCHLo95gmlFYXcd3EqfLOaf6tZzIcxQPeqjldww cMhfW6iBSN7OCRMuW99w0glTWrGsviTWz3tJzEbO8QWzpHC6fR+prHdf5o6ZI/pPejkX2hGGPLW2 wJTkFQXx4EfXCn0gDtk5jy92IXV5jSxWzRFRXbJSiGOCSv2wWzQarsA2L/3aXeru9nbO4oxtB228 wuMpQUlE8f/bUhyo8O0Bwo3UlzjNUuYc4fo7UWfHZgYr1KsqAfIQTMfmD2foLOt7Z9Z7ENhKeQwU tNkUXQ/U7lXljC/R6/fdM4IQbZ6E8GPTgxIaTZQliZn5m3AiZS/TtKKRF89oZh1YEkNZtYYOFp+2 6PRWqzROQzLlDqlMNtsxMFY3e8edI7DLcx9LVfrjglewRMEx0G7XH6q/eQWkc5nTxDwekd+jc/+c hyUY6uFUhBYajZt5gTleCATcDeVah0ytp4QtWE0OBIoHaJLHtLsZX2E5tgDC5fvWLtnKkvI1fvDM Y9bKE/koy06Dx2bAgv2zh966x4JRvtD8Yehq+jWV6OUlsPpqI2dKvlplE4+eBbCW/KG/37B0W9Wm OP6/pj/63hYeX8xrXjH0qvrdNEYQ8f2Lf7aiOUmV/8XRgnhfwkeW5ca9NOPBq94HQpJ6IAGgiWYr bVp1P03a0HKsI/jnI7OBXX3aGpmfZ9V78mSXalOViheBiRLwb+cM5PPyq/SISpc6I9dlsgZPokC6 EzUjUkOkfmgGrOiqZMc24rpcue01uCqGz3nw7bTGS7QIlVrHlrv7YuLFFQZOHQp/vUyhodDZVbc2 ihWVz07cH1Xa3Sv1nABXtz7WGBa003u766gUNHKKpiz9LNszxBoAKimaVOsnPn9BJRvoIkbx9HtY A75AsmyKD5y1Wvm56LNvYnX+MUdfbhHoK49NJfTwBi47oyiavYzKb4i9nSlujllDznPp3yhMxckZ IOGIthYqYwhb0XukS/q4WvQYI8DcF4Kkt8NE2RCh6YLnAyLJE6ttgZskJHPIU5aFqmd9KAVS2iQX 6tQ6Rdz2ODv/E8oSeWyg4d2MWJQ373+iB6ZcVZu6ri3khk4/ohbXELkYnfPHniodupjEIzl/3Xv9 xvQ8fhCbjW3K2xA+dAa9IuIsFLUj/XZOzFqmo+nGWLu/YcADE/1FEm52zKg5C1yJKyEaDi0YkKA+ RoiRT8ZcEaUU1tc36RTPRFPe44fN/qKnpzrniCqb8fF6zqL4jII8z4YraybBdt+tUgs/XrFKvWZ3 QnHDBhesqnc+pxDIzg6wxGXf/OqNqDp3nE2smcFpuRSsLqq7G7dpXNBLsZnEl/wm6rn+qSy3l7cS KFG2lXbCYhHISg2OEQsARkTcvJh/MvTrW7FvlMGwze7L8clY1bOx6dAsWirf/0viMXr5TFr8e1pE 56aMIOiW4ofxgM9TC5l/U3Wp2nnJTz5UvRHfjJrcZz9FH5t5g+wcz6SyM1+agZdVf264ESASTUe/ 3Y9EOZfVzCOmxygbrZYtNVuvfY5KawEu3F1hhdvtooku5r4E0RwctbdKXznhxyDUTuzy5x7Fb05c 1OwNadJ9qT8bXI1AZ8D0EBDsqbaTq4egDf6mvCd1xeVwK7QLtA4SARhA0pSCIq0CZQFy7cq8wSQ7 ZYDLhsG1Uz/JqsQaLwEIMXfbavRu8jIDtw7316cBtDUIyp21evMlzXK+NEzCYw8s/y+PX0GvhOaC gmla9vULq9riXHb1PoYCZUVW777BeoFAWiVfJfCSYqRRxEtaVpfJKDm90k0o8Eh7/XNcB6DxwlNA nc69AuRUHXAjB8WzZM3/qnSxSY2gLrfB8KenWInBOnjNRwNp+ui13T1bzmr8Iy28x7QaIBjMF2fg Ro1CGpY2r25IW1dqBKCwrS+QIryPNTy71epGB58KBSHc4dB+2TfoRSzLzoxkJllsH3GjHv2DxnUL tbcE4rYK3pm13KKiE8/VX+Vg6DYDa0IhIVqlu5nYk/ITznWuSs6/FW1LnYrR5sRiPkD/5v6Q1vWJ Ohb/ezHfc2w8/NU7+Mb3VkT2S9xNhgYXVi/rY+3zq9GftrUCB/pi9y3o8SuDcWrkNzMlXQq7qySo 7P6qrx/ZlV/+3F+blfuw5aKbnN1a/svU1RxltOlxQAOo45Fxl7CrmzRHogddKWVo+lsQOXiCRYqf ff5N39ooI8G61+kneq6UeFwB/i8UWq1dwfQi0ugjta5rceQSFtH9NCTQVVQacS88m7wLHrBmoSMW 1mMQ1OtPeanDdfNDfDg43wx4gPcmCNZiOIkgAv9CJnsmCSMoWrQflkLuh92OV7p8fSFo0j7iJZTW Pv6O1wx/mvFv6hiQM4pXDP2PW2Pz8ZnQsnPUJx106rL7SD9BCjnW3A2jNXU+JNlEVFGw1H+u8xqw kkHUguAR1cV7DI88FFELOLFKtYWDlg85hnx4zWClLKbMMlGd/csMipiZfYypL6WjH3Rb7aA9QaIN jnVWQ3I6vHqlxb4Sd19lMj8q5/qg0kmy/GU3f5bX9blW8RKCyDEgq7DQWA9l4nAyq3BVVommL+Vn Fi/sOWnpKUJ0VhDhx0TjVUr0NNMHUfYH9i73OIbCyoJk/+OX+42ckFmI8t1ThofmpMK2oJFQuwDU K+E11BPSsXJ3RyDVrpjj2ANqhaH+kUG3yWMiXERsnvr+F9Yh3w4rEhC3ATQfUjfdiAN/yurfdJpx 2dGpMegTN3vKgRzq5EivE1IYLPucjxNGuqIQR0eYvfan6VLB3ly9pZifV9EG84VQX2d0NA1w34u2 usoVd6I94TB8Diu2vl4rhavkb9KBkPWo7KXPyVzF0/iYyq1C+H/Qbn3O9mz+RlABekyGNp2A5CNc 5zQb8O32QMcdfGiPGFnAAK7Z+S5zQ212CbT3yjXI0D4fVB+Cb0dGf2o5cC6PBkCsvojiV9oFxp8Y VLG7U7hs/euygR0nEQzlGKF83iykGrMXhjLR6amWqJ57/6u08qWVxs2g+9ald0E10s09Fjlr8m9c AVP1cq5BlZM8fB272utKsRmjmG2bypDG0bSHynK2PF7ZuuQOj9JhuZeLqTGEu2pxkNVeSOHFHmBc 8OgPzRsmKSFB6GiXTWbmJF8EWB21w4q26DZS/3VgYrpT2J/VMnyHwf/KGiSCrcdnVLZ/WDKi0BMh FFQw7PQKXgOUQGjLlYaEIlavMHKXEPsQoyhfSbnhJuZw+iXX9a4b9SQenKgKKHKwxsmxDqjo7Tnd hCBiSKqLViai8cOK/QVtkUwWBrnDclN0j+3bmt8lRWrBQlQQ/IY56Vanlex0MlAmUYltbcevyuvg b/QwG7qqSzlr2bODPjEytI+Cewf93ixQoX1WJDOrRmFyrScssgGSQcZN2lAiPZv6gUvGOv6GDZQ+ LHiWQVPxsQw/vqX+d7zypVGfPOvmWKp3J08tgch4ZhPC4WZUrKU3lpBGNrJeDCHL31GTkf4OLBVZ czuchGkP45jCO/LxnGz56Tq1PPX/jJWdW5Og9SdyWPcn4IJQ6rjVVNwi/chqcGbY4RDwySEnBvk2 zJ2C5Lc9qXdhfaXSdhqQ8Bhfo9eQjHh5LziyEkeMDA9Mb4YF1ZRX8NNOrguhSjQIbBwr/QLkXqvb sY9oXJ8sRmIbtd2eb/XmlkeuN0QIqW5jupqBgCSmqh8WBDdgeXwguAnOpyL819EuZRnAGN5J2JpY C3UdniGrtI0aGI/UJPUpCMt/tKjLrXJYjQbBnNC4P7xQ+Om3xGIfPOBLZO6NxTjcVczYLUm7QEUZ XeVCedsjKTs/0HYUP6V8Ac+Y0SIrhNdkHcH1dNdS7f88WLK7ir9X/ILgsS2J5kqvFi1SfevboIVU FzRV+oN+L+2qXwsHF7P4sNCFoLc2kK0hsNHE98++gBEoBVJHHWk5HP0IgoxJuWeMy9zkxnb8uKsD FEoelWObSkYh3eOfdrqBawkkxzhIhGL568E0qQ89ryYt19aMSZw90O0Llsvh0n9YKlRd+65HaoBK b5SDLfziEhztfrGA1hU1IDP0At4fE76db096cuouXiKmJ3yQuY54Ph0GrUDs5fhuBQe445JFkp+Z dHex4IZGq5tCUmJnOczK1duQVCKGJ3twIqizQPeGJR6nPzMIn1n/wqtWLzxn4kjywJ5q7t2e6G9+ S6kyU5zIQTN3Ro4JfYfS33bW3+78GIZ4f0GGIwx0F6qVH/MfWHLsvJWACDat90v6M6yEDxx9n+MN 0gOsHtkZbb+Pou9M0DYpY4MoClxrMjdLOqlq/OiHSeuVqucMKlZqVT/F0cMNtL3roUBqQahyB0Yl XJQL2jdxN1FI1Nc1GbfJNr9hF8dWtPbeUzhQ6zQQIVFO+WbOj+X9pzsIXnX2qJoNXdgjvXz46sIo L3NhwM/2TqjDtFk+/benj49c4itKrHhCLnvXVRr7BSftXh1meBaene176rwTcJsYPOhAKyKS9XqW EByEVMLfwW8w0ApOnkrt0PykkyS/2935vO3w5YJyvvzU//64LOUnieGezLuvRGzJ3L4JhvpgvXJu mr06ZYGLO7zQvrsmI3geHPcHxpd5fMvW1QV+WNREXdXwVfwomkNlbJ58PGzkfcCfI+VAmzzx6RT8 ECYs33TENGfXdp/gXg8kcOBXHPrbz35sQG2aciba1k8uq6E0bK6/Ypy04/Lut3FDNP21ttgDbNu2 eksJ8rECmR7FEYLHWA9PIZFkmX1EORsY4PLBIU3qMz+u0QuGiyhdMbbp3xoad1w9aXEWI+V4OYHH d5IQtXlloVVCMDtOlFyDVniNL0EXnmtrNWRh0cIfqUF8iybkSIhuedAtIImH3Lbw7EXmUdKMQmaO /bvdCAZ3238qXUhIC4x3hXMrdEmkuk2qpXLrjFPCCMYk64p1dvkwi6p5JMYfEDEgsZI+ISeyW80f Agz8LRBEWVLp1WYGS84K9RRX6bOJ4LX7ntO0UKqgD+lolUsD5pWstGgKIJMDCkBbKzmVXvT92hwy ZRlNxMwDyLvI9CpOdlfvi+7Aa6hA0/I4TH6S36ld9590KO/N9LhZYwFO/OldvYerNPUdWiovfgYE 4E/i44dEnn5L3P6ZHliXOjPk9keNyjis/hZqYntCuAZvwHGPGSpMj30nFOH/6xyiAMVfJfzZC8LU LwsX/8qFExhqQ1bIBEXHhAw62B7piiQ7oLDPqkcXaNb6FDO1ePzzE5d1/2Gxaz52NRHXXBrGHeLG g5/SHdeQ48cqoHeo6kp6mavTJ7lekqG75eLekrel7RbCKOvfyHeRed9jOwEshdd2bP6O8fBBrYql xqpbUgBa282zAArfwyHbIXHJ5BOF6yQcM7kR2ywqa1N0YPWvrEdlhcavyKsoQOvra7azmQxneGwY EWA1gSgKOemPB78YpSaLBg5bNS/uiBgtrFShb2DHcIUyVrziwCT7y9gM/viq16Mu3DwiffevU8aA kVM6m5Kro12musPAjcADOxuyS7w15vNLQW50rMSn9fGVKaDHTkpuizQY3HH3fA98JF57O+4hOiho oouju59WDvW0kQCjvF3my9Xz5/5bYBGrZxKEAPPH8D0JoyD3AeXHFpmlUT0Jhrm4MbawvX3ycCcA hMD6Lo7l0bC5xvDg1hdPlMYjsA/e9nyyDtXMpzkgSisUmo4J35zsHuVMDWPMC7awPb7qG5b7T8ME J8QI/cnvKwMw3tKPBp03MI43tx3+hoarnMtfxT4I1cQ7RGx6MZilHgLLVdXRrWLVeMXRBDvwkARY FvFLhE0CtRg5GCReNKqIz5O1ey0tZysItludqbK+5JPW38crlc3YOdCiC8oHoOiZX1LojXZkKsMX H/BYhCXAJaU0yKCXKCvdS02/Tlz+g4vjCYqZuPD2Z0u/fRzPqDuao/r2gClflHI/57r40qzvRq97 EQYT64OeKGpOb3kCmubUW/05LATVjRDDlJwQwsTy2mhbZDIA9pxzGnGQkjAxnlxX9sXfPTgRN3op 2JgZDWx1ljf6ygZ0qbfSGPhrTc5Y6aQrWR4Ve/nF5fbWul+ONVfW1Wyy9UUYFvm38oBb1kI0VU2e bqGSnCTul/40BbRU/0d2fMpnfrDYJV+OQzSFNDAy8om/OvYa4d+f8rE1a188N5LeiB7uI4O06SaT QFIyLUI0j9jdpUhkQoLwJugGrOa3YpaOtRHvTnVwDjNbcmxfhgM/a52KpD3jC9k/SCcRlZ84ZQhc 3lai3YG7nf09a7j3BTTp+I1r+n+LLjw7VefMrjphlfx1jNSE2ZHspp1Uq50L3fbvoCxoI4svjpZy bcmn3D8sDZ78+cHsCph+ODoAbPP0wyjCzHu0fhUdpGnG1srFKnEORXsIe3LfoPeF0ptR8bGotR8p QkpU1ZryctbMMgiSPSVbQgAVISbePDKfg9csJAGJDTbILOQdmUh0A4B4e7pUAp6VvIyqxsPqlV+R JaT5FxYzJ79kxvZ70X1P7IodSXcKH2MdHVWVs6qU3fTgYAOgv7f3Gnlb6LdC/m1m1gCdZUw9wNtd yxRy4knPLPZfsBeJ0Pu65ovGVzgn26JlzgJPsX60q9Fjp1w6jZ/3wm4OyrP8vWdrH0BK060mnH8E Zt7B1vCLhtiVkge9g7PsWqlBKmO8Sp5TjMTiLUvWHukOuNoFhfneLUFPpDhevCglJLPvUCdZqXDP kk7IRNIBuNt0fKMDMZTDNf99e8qvxI23AeaU4+iWtt76OOfXirFUZtAG7jfuNMSP0ahn6IT2rRPa lsU8uP7LZMpJavjDlk+gHVrosOxwDA0POP3IDhX4WJNKVHeglvhjTlH3AE4CvgbYXQPIwoeXtXl8 +hv6p/u3noGnLmBFnmk+yrsj4Nzhum9S6UM+2QIHiMKqRiwRlcFv0yyx2nfAY3xyPimlqY/OMALq J816Twsd1sZq3aM2nmeo+NgLLcuI4SXGH+4OxQnhCbkChnjPZGkuSu9z0zELkn6S2AzLgVst9te0 GfA23V9kCkj/nyj/fZJeEV0qYSBeOEUusKlJ8FdiGs/lBbXirroVwWRQZ45nuu5wjo+vX1xNYTIi QweUmlvX19SJCUfz0y1Z62FlEMXpx2N+Ma8B+suSYLb2Xj+C7Q7IheQ/htKcNHpsAihA66iCwT1B sZe4pHn5L0z8Ooeq/PBGijxiuQfeIiX7y9FrN8RLU0qLdl8DE4U2yPFc4+8WZ78kUkrJNEFunTg1 g+XUJYe1mtcaO6QAI2oG/sHDBr+qp5ViSAOuIEfcbLWA9D1GiS+gXfWtg7ZV2dLJtfyHKW8EjDsE FJn0eiVPghC49YdSqQk5Wifr4RAQ3aiBWkqfqQgtuQ31qSUeULGcgksmDD07CXv/kOtS4nkPSmgg jiaeu7qUGWAogE+a/xnupViejxuXJfUetcuq3iJgmUC2RHoRrBn2Lu3wN22/BbSMhHQwP0cMF0hP 3ue2CwiUtGkbRiKrgCONZ7e7n4b02CLuR+6hfTzHatHihmdn3R+RUOUlWsbZq328FhmbT5A156o2 qvlAJEXz0IrhimpE3gypQPBIwV4Ly6KYlB6Rdywein2ulfqHyKQoqhfV5V3AmgLeWqiYyGTGoWqg ro+fuFMFKVjkrY6aj8U74110OeT6alrXH0/5+qZ0ZktH5+MfkEBHtJmCSZnvT96VfkZVlYD/7faj dLaDHxDWMHEb0KCbDKB/fSDVhWgxqOI3plZJv65xr7zATYHVtFUvSbBRPCahqThqFmeALvKT930+ 33W6u4gkZGwRES/rWyuwF8qrbPCCthviCwCchlbH0uopLoKkzzcvwJeWaq0vDZQOeftlc+iF3mkz LDwYdiOmTDXvEqGORY3+yzIJCeRKD1Xhvrf/Luu8djAL1km1r3gt7YzrH5iOEc3KXZVCIJyAlLr0 VgNqqjgd6Y1xMLPtil+Mk5Quv2nJ/MOUyXAoF/9+NfmSxBcBMJY/xIsQVF4zlNpqSmwDHCdNmPnF zN8ZcsQi84N30iI75stBcrGsNlgHVO22Gu2vXWtHEUyHykpryx2c1l8w9rDlL/Pfk4EmsWkQ187s 91KUemL1rFQsAz5N9rewW6bcAM1hcpNs0GePqLztRD9QKnubVkk4fQKNyDO+KPeQ+qnA3zCXY53S VHkh4bCQo3ySoAsLRfjqGwciSg7lOUuCm+upEjAcbDkD5A9nS7tbBzV+evTCMCRN7Jql++7U/Wzk 5lfL2fM1fuLAUJww2q4ueirc/CZYUEj/L0SZeCYnxBdfIYz5TWTGHueMoF2HPCb3VJncrCSTJ1pm VxGkY39NGaWp3NppiCA5/GuXxvxOzp0IygBFssLhsWR9F/KvVtdlZICJ7pVrUE+KKKvjmuORYfkO wtBkaggP8NjQy2Bh42YgvXIxmzGf2nQGDW9mTGweJzS768XYBQa3uqiWBTg2PD0KLEUZl0HbRkMc V8gJfE3F+2cOXUYdahr6Lppj/+jomVTyYLqpil16RjmOWr6OSBQHFDwurmmsCQCyTIyd+z4hoX3/ VXJZkc59BvrT8d4r3PqHndqsuF1hBxeU1Bx8Z/R5yN/dXwy4EwTsa5HMTFZ/MMFappSRpg7QZ1Xq 9hURAGpNiTPh3LRJD3wFgQfpbepvyRnJUTvZMeyoB0aAMqeLQLubqqtZNOR86U6qXPwzDKvrYnX/ YoMmH61K0RdUnl+zS0clM3rU8CW5G94FcYWTjfaT9IVbS/a9wcGPeupcx6n/t5KQ9ao+6Rt2fjPk Gugg8vrYW+JXKn8vhXryliATLUX9LMtRLKACIMW+q3kMAO5kNmJ2cqnf12Q04svOtmk73Ic7rvVV vYthdy+yMCZevP6+xQZ9YOQpq9FMvz5ZdP2YapeZymQXjP+MTh0DtCV73NopkCh3uM7l+LhRn7Z8 dpIn7hQZRDwyvDyvrd7s4nV3M4lIrPrOMApLzcZLp1n5PDYS+eKd+fVA9a+PO419XhDl8lUWfXgR 1SBTBeA3fstwKsIwbp/FJ61fy24MQ7Om6apm17Gwgy1Kkl0YDYZQB+iNSB5b6iUkUngyRo8aiVgq EQxgCHOI9zgKfoxMh958bHwSadiU9WkR8jtXIXiLidYoSctzejZu0H3cIq/3JpPFjPUuuUJmS3sG opt2ZNlNZZ1Plojdkndik+5NeGqYFmhaFOWDi9eiO3zGbnuDL38TGWl1x/fFDwt1qpkuufvURQWe qQNd4zDyvnfV1+mxENGwJhpJtPvRzGcAzqN/VL4KC5sn4rUuNKcOL+oORnjuP503jIywD/xhKtpn /oNcvqZVdPhQhgRow4YvqHGiRWqQhOFe+ogQrKifehlcyuJy6ee45H6bAdDYAx7ZFBB4C+axDt9n dbAisrdINRvlJGw/V9SJYYCwJDToAsq/hpMKpmu/cX/wR6JtDFjjc4pXfvi8bPOHtJ81BK9Kooo5 ZByqkxcICLSpvHxoGdV07voruXTI1dRbUBDI6mfEclDGJMwteEOg2Y7Qm6P3zC7yZXsaqxu0FZ+n 10sv9s8XNN0l7roJ0fnD0PROZ3S4QjEHvx9dd0vl5tZhOm7YxEPYKr9AIzALEzZTWx62m2kXGDqK evIm76kBosM6xe+fVU5H83tvT/XKzQfCpfmE1Q9u74te5pdIwnGjV7s/kvoHshygav5Kp8bZeHSZ 5bpJ66Q9zRHgMRisuFEgMInV5Q55kqznih8I0fiVlv5LANfqKPY6z3qIPQ7N/Q7XrWCX+NwteqLN Ni5N/73un9zyqe0iPoiFP1bIiBcct3RpmrzCOqqLb4YD3O86SIInj3KkDda3u4W6lt3UtaUQmoGZ PypyctoL+X8lhP/qltEzG+Imb6KefQmNKHJ6GS0i06hTu0ySm4n8mqin+kxGcc2Bw075/FFqLHNG SX8Pw1Y4zQUuzqEf39cG2dB0R1Rc/45E5RAXe5SkKaA5N9LiAubrOXAQ7zkVOmwOWt2tvm56oigP N8Nzmp/w7z7fGVMo85AZf2Ey0BnZDKEuctB7vAYCiLNm85J7sf6mCmCzSTLfCzTKXKsFWl9XovJd RE6OXdttKj/Dq3+cDXN/49pWnwKv1Tq+SuSQnAyFkB0bQjcnuqbLHne2s0JjR6fXBc6jyGogY+0r /BHKMF1/IBaWJVDLM9XsSIOPT0sd5sP/+S4o9yHrBNbgo4ZDafjRo5lNPHXs7OPVxrP3VuKoG0H2 ylKUYMhY1MHIJ/RTbxouDNDQo/wbAPLkpb5Iad9A3gDCjpSH2e2q3CCr4c5AHsaKTvP3VzVS53YY IPtLZBFEvWwKFRLTV3D5BTTfbV9LpV7wNXnh38vBiK3Wjcx6QJ4I3IZkumyhSuUprJYar04GIzsX RsYuG6mEZhrrwcz0LdpuobhKF7kklkGcuBvjfpmpHPM6cQ7NpOFvctQ4SpcfLwfyzRWtMtucBdeA dI1P6KxXVqGZYy0CTaOY1ST2LAfLEgyWOg459zQCqo42fFwiPrXCAEoPuA9iGr5jt9JKXjzJ52Gs IR0+dCGlB03qzpZxsBLat70LfVHin8tLQG65VBleA03hujm0pzhVW4scfC3ZObEYUTPd+E62N/Sa CxCS0XljSuYrhKjzJVCRNejRpscXKawueyzz1pzmis86tun8sWHBbNSZz0D2czZJMLFDNBC3EFsF PIJDv8WUXo/AEGwN+SIk4w6xv13AxxAKN0IVp+uM8E5YIX2swihxI4Aymdd606K5g7R7vo34Z2L8 VQFIUZotmMiNMV4ZFWAtdDcWMJc/rtnTOddKickxDVcBRmU2Pyz9OlNZeizEATW58tLxir7kaGkY OfQZOn/x9VsG5TPv1RRBVulaw8vXBv3BYEFMGrmrNnCfDS7csMj2UX10TkM4b4DVzWzXKWEgqVHX YpxQpwoW+a6ZM0Hyw/w6nJ56V7L+EngEvjWkRNTqHu4FKrASuavzqRe0CLJ7csvRI3olUOKkuIVN sqnQLVLmg8qC5zs0mBHjvoQe23qrdNe7V3YWw9a15wyUIvol9UKCAM9CBwS/eooVc0ufRqaq67SH kmtwa8TZHtnyjcRQfdoM/6hvdcSSF9L52b8EjdDYn8S/j+iEhxb8YD1U8jyi1Hjk+5sWn7crE4V8 Ws6rMdO13DHuNliDObp27JGiC9phBLqZTXHhBHWkVtRSevMUXX3PaN7J2ZMIzRNiR0OqdNtKOsPd Em3rfkGkl43I3EKECovEqquyvQ437rdaKsF9BQg9kcyrZdwyw6FMdURzsYgnc3mQCJFrl/E9jpDt BTdPnY+MijidDjJUz8gYLYEJZ3QaJigSDNyJTs8+MdkLAs0pVGsoT+Us0jCsTty5rCyvlI20Vd+F jl7Gq3BedyFbMI2YpQRLW049tgod87xNdcaNohfHU24xduKcOxS/VbmDlidTc+sRrV9Z9ewgvJQI Oka4G/oJD1z93MRJtM6KG4hxW0KwH2nlZZCBNyVcLaN5OegRLMOqBBEj/7CD3tHkZg2HYPe62PCX KZh6uloUCo1Z3YIIdEie6N59WATQqsmBJZGwiri7H067ytc3vGSnionsbcnqY5l9r6lnPIbHqAIt tKLjj0/dIt6YwDUOZkcYLb2AKDXGQlm1WrncxA6jD4nnqUzb8hQxVHgL8Oe5bCSfTxpQWSOyItNU /reiquRhlIy7sil9AVLYsZttDBvEX4UfjkbTvIOLLnVXcpVKkovomeR7gMG4+ByAZ7YHI1SOvzT/ Lh1ACt4ecjX3ALSsU8GVLY0ZaZBOozUUSj09cW/MX6xICfTkYxWI+jJi9z/kLl2Y4fmzvTdhJBFx l70D3BnYTbzYLQkGWn1V1quag11VioCgc0CKL/5HbeMYlMWVRA9OhAEiTxW2ooj5SgSIAun4MfeM S3QKJzGGN5pAuPUm35aPqjXQPJ+56i25DXTMOjG4b0NaBuOd3F2mlzr/C+zr4IluvjR/x353zN2U QEX6vDIL5O3Ixl36YVI6vvqLSZqxVU9Pt+F8IQkwZ6fcTd8Ad6nnsRRYJ2BGYajpev1rXZ2i0/Mk glxjRlRARTFcyZ7VTVl6xT4TjDxVY401qZ5MpPeP92H4bksnZYUwInzvJMtmIl2/NNykh+Wyqar5 GIkwzU1K6NgQIexVsN08fcf3H5JQONngfFlMQqIbKiNYaSbKlrMjQ1+CSujNHE5llpcI7EDhjJmd 3Y9/lK48qqFBymOya+28SBvRkPYGOTb75qAnXdp4iVQILIM55Dn8lXiOg7IlYXI9pZQjddaMWB4t j5JA87Z/vxt4d0wvHa4gLT31kjyYgyJLuOEc/DQWi56y0+WI96Lgv5yUQ54+yhgPTlPQEDBE0tex ghldW380GcgNG9rJlh9QUG/ZXPKAgDwy4B9/90LDOFZJBXcEjm357MbxsYrig7DMUM3K6iROpZfj kKtGQJY0uq9oGqT0ALlaAjTJwsS+NCAQRUInoF3p/POorDX0PhyguuCkVm2u1QQgYnNwjWOT7dEE 7L+1jKvjbacx8Jsn+odSOL4dB0vikzc/sHbdf4+8wYYktZxXcZ4RdEM9Rr4ugDZHYfI6n1JBbYMH vUu6OuXjazlXMQQriRncKgLZh9RJwEKuNH6XoGEWxYzLOGK3QASPW4kpEy4Bw2snMjKWWVXqgiNA 8k0nwTCvSDwwv3a81NWZVMRzhS/UMSAgEjgcOpbSZusBRBv/avBqqwJFz/eUO4S4w+v3mFpE2h5U 0FwwNZ7GMCHPwaA4Siddobmb2rk2sO3OYPZcRzKk9KtU5vndQ3fGiaiVGkW/iTjVCcZF//eq9Bsb p5Q494G3B3Rc0RwcKqugD/Lu/4M8HQXWigFy6cTmnTdj9WNsAWBYFdr+aR3ramiUq2TkFAfukVde tScyHZTKEastaz3DioJzUZpumtpAPS6HJAouo724bgxJmhmllhRxU2XPHi6yHUASKxYSqDBs5bCL XCP1Rq8vRhijbTNL7BO2A1LFLLNjhNWBDhGF40E0AhSRUIvc/7CXC76tlBdk1Le1k9Gx5sL45VvD NmgVBo0uJBTick0J7h8GRO2pCdPJMhwrQKJmtMAJSsNG/UeroYdJAmcdMOyfhLrAi2ryGFedCtrz ym4yPi8OZBCKTC5Y4zTL+Fn/32fQREsICtFnE/cGSasdkawWJeUau8B8r2wxbL95uXJ5U5GIxPbD DiY0oAcrdg4leRtEKfE+DIbdMtVZvSoxrRE6UGZQBlu/ZOdjHQNuIkittrXMVLusUujNoGo+kIbK NonSj7nmuK9zBIKUxMbWXz1Wf4ni8UI4szKcs7/Ws5xBc4DBXntfajpR+gHD4oZDd8+8PXJu85Td /6/kDC6baQ93+MKLkFyXfyHTJcLAGmpUZCm5FRt8X+/mu4DjGZN+Fp1R+NSmPqImH+AXuXOSJUYg mBpVnm93KN550akXPPGB4D5BY5pIsHJ3RAhL6kMHe+SQAqInYIW2T5j7wY/jlWfAvcyOe71ZqHg3 4dAQqmUaWYKqcJaov5aTvu2YK35PB9Jv7oD6h8FcepJ2CrD0MaG00UJaLk31YRVvQKrc8lvo3q37 6HY6sT7ohvxT4j/Itp2Mc0vqiRHKXK38QS01vmPcrJNXhgA5jE6w7f4nf+jGkH65wghhIbbuiTC+ a2VKSvKCValaSIKaVkP2crFOZwgNYobpK38I3OX4gmARvipmT01rCW74M4Zy6EKqWigU+oufIpg/ Ib4XEjtWAHPEWkxT6Z5HqFJ1Lc2A6QnPIdxA5uBSSGbBFMHwvZjV3pHlupWnx7sgBFo+ApqO7EGp enP+2GELc3C/bD0vKRsri6D4qPBfFuVwxi/ikImr/YBNcjuPsKCb3nomswDe4GaDFt4CPhUpVBSf 8RgyG9BcBBsJc5QVEWFTsItvIBNi16RWjOaDV6vBfekVMDORqJK1/dgyILMpRIwEoqZSE2+4LIQ7 1CHtBvgRS6YQqTU78nOdyVDYa/4Ry/865Ph91v46Bppy8ywlTTAJjHw/yzO0aGH7Tjnj2DE+D8+D uatVF5FxlzMouspt7AArz/SZclV/kHoWHPFsje+vAE45i+F+m8EgRNz11XoH+lWDxvsha2wZMVuP f3sc9TmdUg9w+AF3VDv7H8eDWqDdKEMmojpVBkMkI+PIwGj1gRRmSWL7MGBLZh+GY1iNqzflru9i VUHlDRrFB/XyHg0hwAjMWkx6SMmdP5vvfke+BcMubZcdP6LHpC/fYs6Wrcj80PYdrQaNo8vWF56X VHnQNfFXgpUOKzvl4XKq4mxLVLCR/TbOvxDW07SxumX7p+WhfGxn4HMvY2V3ZGU4kmSYNqZkmHjY DkB/dpvVdTIuAJyejQtnXVaGPW6dicZKv5wW/ghGl26Xsb0301O/s23+kJ7ewLIzanlaVIATZJQp f3L+bARxDbHaoVSrnmeN1ZsM2CO5JGqZqf2kqTPgzym0W2WEfeLEcADqDuBmFC4uc1waeUb+MBsm QdBFtE5QggYYtUzhZgzj7u5lbHB+QIB30zzicQyPlXswHrT8s99zIPej9njoNK7GgYIwXzWVfhTj CQos26utfc26ivjYdtO1PZ+13ClASArUKo/IS+UP3WhHxWjbpVSdcWzYZ8oZ4P6NALf5XL9DUHkT BrG3tP4NOwhBeCuPCZV1GMK0P6asDUZxnOFAsPrYuM4NDaXmv0Qzva4ZdJygAJWfAlew75k7I7lA 1zrG3gcS5DZjG4e2pTcs+n3qvioqBpBPutvBrg1qVtB5vuR6C3caztLmUJf2rbsjnf8LToxUYJHk h6aEogG1i+zuOeKz3G9IFK9Xj1aKM8fMoVb2EglSfnstOacX6vmARqcZVv8C2ztb/EBY2mTuGfZc 74KBkLOIwJcHt8IFcrF+VjLtB667NK1oVdu0a7ccQEY/uT8WAhDGHacQ1TGQ1mai8SJ+kJkZaqKa kTCvzjwepqmAs6FmCDDSzsKG52+p0agz4sxoKh+Xx72ra33sNhDzPDPBcflBwvf+ObuIwLupsC2l 8Q5W6xB11NkzkA+VNh48yJjESqKODVRJgLi3C1lp+DFB9v6nMbofs8/8FEoMoFFC6aGluAort8c2 jZgIalC35RxqblJz+PRUW4jYErKM/VTnR/McVtihNOCMASSykekd57p5PvEBV22pQwS6mP6dRaIW OhKy3JP0UmlwaTSg/jfoVdlkoi59bCAJApwWAza1y4jBo4dbWQyiAFRXRyeZN4+dWf9zrtocWspy EjGWllBJcQhqTNTVUI/XebPj/bwO19HczKAUWFlc1adXUiLTBhsZKxnBN6506GeOc5vNX4mzBard 7WP/0rwP6JGdRkFnCiJx/40JcoBqGuwch2XeCssTW/xCkUIuvkYwoD6aODTSmmIOQrVICHXvsrpu cfwcJoKhOtoulaDNc8Nlkxg1gwuanbhPE0BgydcGyjqaP3dgX9ZrKBtO53MfZAKoBj1aqp5yZ48+ UZh5IQo3ri+izgil0qjXcMPHdVuFRVAe+0cf7SKkAMXFBVcrt0qKLgMNf2G/Avf2duHB7eM4TlH5 TZllGjL8KBodTEZ0CHVSs04jIrHbrQ6cuBhYakU+RaO5/ev/WI0megtiVPt44ydJTyssyTSwnLaC TgZUxsfBewPP/lAkTIgMYBHjsvJKzdQ10eST06Zbodz3T87d+tuwnaGzKKJnXSjAWKgJgw5JI4PW M4nph9Bt/PrpSO/3OJEP95XZmQe9Y2C9vlSnwl6qXNlmnGGNpvpVbFMxcCcChQS14B5PVPV5IlQE G2SxHTG1N1JYHoFZcKcPJMWTo5W8A3MgCZc6QCSOOzBvzl426821Fezrn/fNhzCB23wFYidRP9Cq w8jf5QgfWSlUm4bvfhrij22XSeF5u2d0gZTtR5EtriMUCSUhbqzwrgVw1Pegh+bqwXkNVPeh+3u2 5qDpAzUI4LSaiL9Pht/ZWG9aJyCmGhhFK21+VaZyu1HfASwv7uyvfj0uIXMhw1D0eWn9KXxEfx+X pLCkVqt+yf7EAL61xDEeNfyQGcghpIAlnkOyymG3Q8KcqhHUPzkJNhXUIdMKFE4o9o/eCJURvdnq /zo4Ilz8e1OnlM1I+/2ksvP2VaOl3sGr2qpnIwsVWRESW2r11FPojRDe9HRqUqypOXhlzPMTJeLc 6iTe7qh5xXx9eYUegDH5UtkerPeCdlhQRM2v8Px2YzDpw7ga1khcwBSLll4JxVvdirK86x5CHnNu YlTRoJaeXlnrVCVgT6UinokrG2/1gXmr6gQS2y6uzfysPIqxZITLL6dtag7LhBJMqWjdgvr8tX7I DSvdQsWUSv/XHmowjhfsOEh8roHTFKz4YO2xuTVatmFsmHUQQ9pA/HsFUgnzOUgvirYetruLDI6D Fz1ChbVvfEIJepemW7JSpY9RvzgRQklKIGpz/vBf0twhfYvvjZENRa8oSsz03g+GONWI1biYpcuR pFajPGF+MXblM1U988NEzVP0Tgf75gw7EXI7QAHWWejPS3KnIJxVVC+J/nwXRn/R3Nx9TIUrH1Cv nfn4kege7QyDC8PW+7SoUW7+vnaO8zrPpS7Ge3pB6laCWCoYkr5NjtMyFyF7up9ZED0H2+bJXCfD UaGDpN5cXF5lIT8sHq3S4mQ4d+4YZVyetL012sH6DQondNceH3tG/VI+p8XQq0ZIAf64cGOm+ZEQ cimah1GIxeuGaQp4STfJFy/BTJWNe8swA+cJMx/02Gy6x/FLuxCILciPtf47AhXrQ1F/DHC4FanU 1kT6hRCqQwAgFD1TqWzmEfWyv9KSJPynbOqtpDzzt67Gz3DUw5uFqHZqbLvp7eI43PTl7FkW6qgb k4Q7Gc8fUD8yBlWlwPW380MEKQRA6LTXkkDSlsnlsSU8116geo02Pyi3YEVEHAK3EHI+UY6xE9/M 1C9kO+kr7+hd4XenCcLdWsMS5WpeiVg7oIt0LXSuAMIJePuar6VElxWRqySCswJFDQKN2vP4XSAC NAaJcfPcSFfIxgAn+dKe8iebrSOMF9MgbjEWUdFV7usB46w1L94o4Y6EToJB3txOa0xsvOg2zREz XRdb1FgPhTb8WSIoOvpP7G8nzBsBQvqSrA/97KgQdlZv1I+lZqPLaZrVMnHvwZixw5lki2Tr51Nt REhpu7CxhmcR1fDDEVjdT5ZWvsdDH4UyawR9IVyOskTzC3BaHq/LX5WWDpXFBviQ/gCjMxc4XmpR cgOV5KSGnx1LSoczQSwEqVGdZz1Ce448uxsDIPZYzp2KSVqXur9esB8WtuS481xOelGclzuD12ry SFgsIMyN6/6vrm8nGuDIIWEhw3kajOPxwFWrJRB/Okbxk/lq9ZZaomb5SU+sGCWW49Urv+Sz5tr8 Vn/zCu47q+9NOdE9sUU99OpUR69sMwkDepWBdg5vIFBPF6gokVUD8EhgkQ9A3mzVJkuYFhwGM3kI EAJSiAYFpqn/MzdtuwpIE8GyxTIQBzkd7e7+4ITBkfqLTrcvmO91rY+YRfIlzWkLTzFQDlGxMthg O/Kyu9WdqhM7DDAjq9Khuwfayp1wsDSH/Ok7ReOU5zj0XUoE77QsFSSJISCMu41TlaRDbzaLA9O5 g6dK1L751Kc87oXDUOt0SKXWKbwIEInxKL8/RYrrQL2veFYgv6lcCYNblZ/USwo0EF7rdZtazMZV jR+vsa9Osi0m25IwGMBJTQ9R1T/QC0jEe8+nothUCxyaevXSx0xkY+9DkOdXgqYQEfS/6kiJgBne C81of0PaRCFor4T6uc+KxAJ9BvGtZmpeE/pWSEpYYFZiJ2eW8aYVu0kbV9/PMp61+ttFBOhNM7ue rvdZWmQ9mbk3BrLkCH/Slt+OwacVqBTxD/hEwVR4Dw8ZNfWx4fDvBSHrbUO2+D5Q2NhGsrYe8kOD HlJ91coVsUO0Z+jd/TjHvNR1l1AXdIo5FmvQIdBSLrt+PicjNAKzvI/sDrP/+nWqWB7Fg8YDGWPS zb9So2iEHOu62NE/vH/aM7ZnMK3vzpDyxuf7VPr13QvukjKJBig9ej/gvoVA7l1dBdJiqcJOfbUs 9QSeyEJP1RusYpzAyjL2md4stga9RcUheOXoftNsFjIsqPyONKecjqlbtEKEH862ohErU1llLe22 k3A00fMbk6JljM4uosQjrK6AWtSjukspgbvZ97IhiYv9kUvM42GAij2tpR13DTJKlceorTsZJ7ZD KgOtNzLpghGP3CfJ/qFmfuLbYGbPPoTOzXS550olRXFWsbR4ztk+37eS8RrRd8XPpSUMuKpdxyl3 SU9ZsUxZ5C1LYpcTGUt4K2ZFOREamggrnn8v1X1BbALp12Xlzqk8S5U3D85N0YShoLv6E4jeotYU dyT+5SWeD8rTMcA4Sj6bKtWDkIXRsQeMOU5j9tXb10HnGq1CngRoXX/dW7n0pmFtwDP3izdO+w6g JkprQDoMBgHADleB1rITw2RlcIglN6ZfUhyi5gBnDc51Qa8i8Xt6JZyf16d9PG4+ljj1VGIE2xQO s9N+2jCfh69f/UKYG7CkMDNZniTYfxcjBGArXY6jhT4LM8zUrBrZTyBtwEGrEFcdphlgoqY87awC onvNoCgFTGyFy0VTxDL/ffIBSVfXhMiOLmBKXOxJTdy75UD6fepKrdadsjIDt8SUM5lrMoMMXt9/ 2rjJ+VTrgk8189PD9hOl+a0Shj1KbTXvFwkacgiz6ZpZbmotvT1PgdUOHfF5WWsFLTQdPwm/hQtv Oc4nUblUqIJbj0vok2P2N8AKcjc6JICAsg7atVAD88NtmqXYDvwiu8xhFxvdXvOG+VxiwqcFLc+A b1S2U4sRcMpXFQOaOzqdXHcag3xKim2zeN9JqCUNjS1ZXl+lVJN4YdtHOBZ/JbU7CnF0a8Xhh9Fg Ah9mHf4owyHkydnGN6NWTsLpPeb48AE8rtFLBgEtF/WRZ8b0lBYDwdFHXA3eE0/lv+sd9fJGjliQ g3BfRMeLpPYxBsZVKSNkuJcg6E/gd42no6ye5prVM/WfcXfwLud4xidgo1ChZDH0bYS0pNgbdQqP 7GTiW7ap1WPz5gU6hnypEGlSD4cqD0YzV3ZZaEw8w27RIThcQaOtD8eqSTNeXRh+jKiZiu4m+SRq GdL/WlRK6GllGNF+jdTb9GHgLdn7MNVWyL+C/itufbxJ6zY0FP690opKP9P6jQ73nS8HVvbdoMh9 G+k5RmEEhZOPm66gev4Fa896KGGbcvbpEEfAEpTMKGnCPI0T/4ddMs0rK+a991etypIBMiV5HFub 79fyjd3lRfdQoVgx+f8NMcRuzZ07WOsYgAABnUF2TlcU+LX+kjfBsqCjD9n6panw+kyuODGpG7IH dR1gSCfZ1RZAt3tbTU6qR0Kxr4KSSAk4Nqulu4ee+eWOcsi0t0pwnhECrgsvDzagxZWplFsZnhai 7+JJ0GFG6QTMAIU7XfTzG4jWneHUySy/DXa9XGfpDXTMiRs+X3HyDpaoL1LmbR0WCIDodJfn0pzU 3RkejoIXblwji08X0APLWOlAyZTRvjsf/9OK4OGXViwAhexe6i6Gg7Jmjm4/4p4h7VGrAsOo9iXe AEUoNoJiIDyE4IKn+yZ22dgM1izs8aAXNZgA2FX1VupbZ8CZpmGFNNLzTkUFV1tEQVRoSM6E7gMV YGlVOCSApPgIQJihhoKXOWkGNk+nz1rg8yawjHnLX7I3FM6IoZgYX4nLtpMvWSAazAsaFqrK+kdQ 6UCQl1ookDsO1V3umlneM95h8ktHStmALSghYooeT7WuXRvFiRnLYL+Fyalwc81pyDr/kE0DjqLo Yq1NDqbZLRiiS9FfGne7f/r7McMBlwchEPMzingOTXoSteYEEKaI4iqUrxqMNrhIiKEtHLgbG7RM XzJpKPe50feFuLoeRlG1amAp6EFBYlpbv8Qwjjl7TMbnyATHEDYj4XwlXXVRxEG5XJAxpsnB/5Xf j3xhuGlJhWGVy5UQnYXyWf7nbhdXi0D2DT6ZHXoGMaBIrmneH3xhV4WGL1VHqi+JWYL1RHFuCPJZ I6zENIjxs9Q58gTiDyoroNe1ZMzf5OnCCTR0M5h2XNWmkNfBtANi7um+PUj10Ir/p1sTmtDGsxXe OWRs8p0y80qpeE6Q/pIvYwen8dZ86gjKW97evqfUhiO5g78oya1B6EfiA5b4kwlBOkYmo6K4oO4q wKmU5cQ7Kmg9L2lhwqUvVP1WI61/9mPDgZilVkfAZoytAOQaQgFXGP3bTgjqlClGU6twP+RT9XtT Da5XIFueqB9HdiZUrJfzq0nKLDG4kLY0It5BBsqAC5DNddKaeJoxaBhaVwSBmg2d6aNV6H8HK9EV BgjgGJEvGu42sOJyXiFTZyRLMPE95Ts0OpDQSAsW/pGNjbtYs1yPmNCTvaDCSM4piyg4PUd3+DlH 23poXXshdL+3IV56pDBjuPeKONi1ke22JaUcAhZIs+PsYlUJSYtxfOW8F705Cn+i4wVorU+Sn45B Rg0d+hYAOF8XtpPR5JWe9geg9qauD7tfphc9OldoZlrkza5xYoR94WqysGuxW3/TzuAMW96zkToh m4Kx+uLUv6XRXwo7yHhDQFSRqJCifRwxPX7nFqgTMcICuYKSSO6kDVHeA6U9gadvmhpzA6KSg3P9 lePWQI5w1Q+smqpN+laOJlbktk7cRsQ5KpjswPEEuko1GMgrsVZ3uxCFR5iS1Ok83v1N3NPrModx RpJQOZ9CGSGwJ7hZCsGdwlK+uiecKBov3hE60ykDtor+jQcmqP52h+jG+dOmxWtwAIXt0olLUxcC pybGIAEyF+LsZ8ZwReW7BwibY1UKzspZ2vPhIBsEYAd2FjbnxERCPSzmSD7qJxaVSNC8TUyraKYf 9IB8+Ez/Gld8pk9qKBa17EyB7xpQm5J0pMYAzobS/iosHbHYIyFk4KtSBeqmAdhwz/yOzJSLUIfg tdZf4FkUyIRq8LR+5+Jt+asknaze/QeVefne3HfCmiYNlcc5ACpIZ6GoZvlF0Y+zfANIKcGPT64h cMIMvP3hk2RbHewVQueTHakhJO/35bym1fkGtZhtcV/mu0HwhWNMnK0TAtdtb5RUOLpqIJhdwojr eWo6AKVOYhhERRzlJQv0BlHGWEMfsK0vsReP7LTdipUIjSmn1RnXi7+XOhB2Ig1v7XEMdf2iE/h1 +fuYFPARDDS5wSe5JCXYhZImcdb25QLuhWLYPSziX9LGyy1d+itPkY90UXmfrcDy+6C2ZKB+XkUu +nFOXju8P4UtF5zspidslzlhqjhvg1txY4zhzzxyT9DuMXRKueCqlh19DPg3SAtPtFjXQ3bPcYjB fGjoZ0lOrEE4ZZk3LhuM+letzuFXkW7kTTFDpAU2EletkZpyp33nGhsXv3ZbSxymrLoCzdwq6lxy b9lLekJqPej4z3fWr2Vj2flLDQV7mv6FZVgdkpysX6PqA5n4LhJd5aeVKNSwzlhEFUepL1FtRL7J jzl4SwWN3/JYrC7YrC3qZT1ZYsvBsgAKhe8W+m1dtISEwgYJXe4Qzcv72G4sC0PYOjipKuiLzfZA 11iKmZdsyKEE0SeltecFMumJ9ZJ6WYcYkPEkntOwt+lglEn/7JQJHpsdKaRMVh/QTqJ33h66J8qy 1YjQUZ+Xhou4pIZ+IwedwNBlLsNlDzRnw6P0D9K/PE7MNUeWUUPJCdLFkwNU3/IFQFKbx6CjcT7G 7xEyQkr0m1XJf0CE+Lt/Qzi0AP50XKWCgasVnNJ5BKeR62SrvN0Uw+igFueHYsmMUiC/9NGjDVSS HGKLHq6Pwa2gsDTxeD3c0vxjt0hw6GJlM4O9Hw4D+9+q9moM3THCaoxvWMdpFqBkJnF+pf81ilMe gfMYP93XgyzoiniRszcBoujh0P+C1mm1X7XEGKnvjI15xxSt7WkjjBtwujAGNhDyPIM3WEOVgdTB fIJ1t1vx8WWaWreDEWMOu0v90xbUk92wSHd2+He0tuh5c0RcshWVBI6Y2OwZwKMhucHUlMkJdIq6 2n6ERfUI6Dks4fWjihJHbbxzIR7FU90chUd0G6lTdATI0iPgD2I5IKNvdMjaj0exUqRgPrIGKDdJ jcKz0kffmDUWqH96Oqi3MKatTWDqm8rwb+J55cdfCxLOyaE62gtHYSaw4H7BNfO4bl28G2XpULf9 iNyOnegQo7BbxZolHcu3GC1Rvh8k7awi9oeqQPiipLdwV7gtRjrLWuPR4mWWz2L9vEw2EQ6lom9g ZFtXwp87UeuillraueiXeM/N9rhKASuo8/FzVwkIkIQG3h1VoKgTGzICtwz9lYfsplRFoKlzwtyj 2xIWUli9rvuQ6m9gtBoBOuwwty1znNOO8P67+eb9VLGz9KAmbIYY/vJeHy8ew4HVQ66lN/+xMosQ JQtlpoUev3XzqP319y+7ndv3m04S876gG3eIS2Z9Bbw+v+kdZx0tTz/36yKS6VXPMMw1E+xvNXWp JHDdrLzY3+5dUmFax/yKxn5TSLh7arLureQi8urGN/RewWJ2d0tn2YJFI8XlW4/33O1qsXMY97Gg 72tfHMqv657n7Bx9ECP4WOm5AiUw/1ZbfYywJoqzKn4okc5IJveCnhJ639YBbEVIQO4upeVVaigK 6s7EkOtuQGfUcTZ1ScfInFybJ0czvj0IL9TaC7JYigcsgja0z3cVJaDjSkR2U94J74L2r8IO0zSA V+S3uaMAhfm8gT3BxCb6uLGG2k4a6RHLTu9J6nLYLjbgLCjgH3hGCnChW3ay4jqM9F8nrf815LLH 43oLoLfxiUqry/ObsqEjHsG0ILFt8ZNxXyRvvdPEKEJG4xrycA2iJfAAQgHObfD+rwDuDG4KbTVb ftNMBVnVa1QYq+9cNgXJKUEvfz6cqRotOILFiqHukMw4WkYRssE+XJqaUuOhfTlYXdItWXmBJBPe PXazIv1/PRJwPfE/JlVCko1+VOFPfR+jkpu39ajgoBG55ZNYRD5yeYfu/MdOc9dZIOy4uAGqqQKW Lwc4eNhQAaAwMDKcDwTrN86e+2XJPT0xlobjsThVTf/DVyQBgZ28MEWLwC/5plXfaKQs9Mu/WNA5 fzOTI6SPDNDsgWOc5JUQbiNS7Ms/ZC4Q43ezzBCBFvfaIZDtSmKWDmLhZ7CiBVdLbfVy9pp7UUXS /2XT3sd7b8lnrpjfy0kcczEIuKaplNgbNG7cYinTUgjwUGoqNdGB7dWddXTGzTPWyQJ0ST1m2IeI Du6nOnz3O1+1FecGd08XwAZTVqO2H7Y/bNjmzWcZ9Pujiq6PqBTVsveI5vH8OBf/SVXG4Qwk24ZY nFgzRQP//LjBgNhCpnx+La0NZZ7YvZP9rQsBZl090d+VKEmvhcEY8XDyig41U5trN9Eqgk1FTybj WLanEyWSDVEI5QeFibTAXrsDnw4zIVNiild6E1pnj6qOZk7wBUwcEkcVBfy8E+XjixDs2K+o8AkW Vo5Ka7Bwp3SeJxdrqiNHEbKMaU11q+DF6fcVbQhzfRlTetn4bQEJRUQqJzjOINuIEj3Qr/ssPVYl S1GEQXvtQH+MuOH+gA6UyXgh0ZfpVNhggg== `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 26528) `protect data_block EXRvfgPLX105DaxDyVaBjuOyVwr6P/tCMlDVfjC7yI8UuceF5KplFUGU2e6wIsGGSVRUiiA4uYOy jKWMC3EzA3JxoUIsyZlLqfbPE8CnhpMsGQF6MW+1suHWH5rWUwBX6dMiFNROBqXjaiYhLMfh8LOu zMlNIAC1jHuQ9MSv6Rd5So3VdRQ6Dk18p7HfGOnwCtTmwKMcJSpXFcK09/yBub9C9uGUGaRXKFh6 tLGBGFHqQvnv7/OQE10ZC7wzKT/iAmP1mExAcmyKoRYeHERxvqKuDW9KSPad9yXuZtOQau6pdw3N iiHTrwCCcOdKmIrLemXbWsHvJxFyrDnOQYdDOGojoi+b2nMcyuv8jgeJFVddebsC+toQtJmGrERX s6smcfTf6xFhURFij6KFRfz3gcVyiLE0E+vfCD4kVp/kW8StylJ+1wQpWjWz4VAgtYf4wtNpdgFN o/q+9wBT4nfUdxn54G/WAsJdfV2eZXX3A/Xn+/2y+Rj/4asinFoFzSdaDrVHlSjll4Ls8qjrNZGA vb09hUL3oU7Gfvwkg7YVE/b+RBuDail9OBqjX59rFzlsn3H5TuL4RNoa2kwy0ICmD2Y6wl0r3XyA 7UC6+oVUKBZUpUSIl/U/DT0ntLUakeaKRdp/L6nTexQq8Opxl8x6I460zuaMDeFQathIvZLE3hv+ U7qewN1Xdc5y67aUdxG/gGZxIbCJa2bJWgqMOfbBJ7BQPlVglswyqgRDBtc/DBKg/1cabQBknea+ IWIqeyfieJedMFunlxOWdkbIMGjOj2VK9mNehDsVGDfUOdajBIuz92G9fLBgbfnb7Hfb/U0Irnsg AJqcZhgjwJulGHWxR9Wkbz2TRlTY+B9gtNPXQQIB0nn+zZGOqBpNst5vFFXCEqHgdEdgZU2O10hp Vvv09/FU8N+dtFIAuHH+6NzEfLYOjNGx6rXxP9cm6D0QQejZs9WNdJArtgjP8rnaFx/A4/B8bWsb WRmSniOMFEnAZUKitf+C8r0H08UuZUt1oOOHDxl/Y3dCKxgIRea70bPjN1G8kMUki4AZwTaVLLKv U24sfpM5B6WzYiwO6DPlObEauOW3iUmRuWWapsoKLeEX9jyj4+OLvb/z74aNeHOjJnyGaAHuRZ8Y 1pTCTazcMCZZy02oHEUJAwXw9iyG0ike9zAmn3C1A2a5DtK19jFxI+QvcN3YSDZq9T9ocnr5lPgz TUiP65psWJ/xl3SpJTcmP0yreJqDy4mKwbUFjVc172NhkayDHcJ+3HpNcwGVn+nVfUpeE92ceJLM 8JTtDjz/2hroTi5JM0dRmPqkxQFNn10i68aL//HyrP1PL40/GDiDP7C3+MudsIHGgEZaLksKXLL6 TPEKX2mVerg5GANF8Wp0kTR+cgP28TSiradg2CR+GWWH19hl9f+59UF4ucSIB+s08c3bSchfMw61 +qEN3w5ojaqNlEzXWSYhlYYbt/eWKt4g5BQkqqs/EZz3b1IJXh5JJLBNpP1OaNgQZnVW0mSVqtXw gAgpIzD+iXxsuxnHJdRxk+xU18MPOrLcGwYNbACkYg3gTDzkCVYak5yH93fZqDqUYAukL5C4ZfwI ISpZiy//CqNpqnCh0GUep9JR7nQgNG3Vp9MA+2c/Ec6GLW9WLUt3dOTW0LrcNf2TOe3uhHzJEM7A D6Dw6LzYzxm0S8dlmpvsvHNBR6OY3fgzejjBx9nGd/2Qcx1EfotSN4ZkDgLpAPGBivN9AEw4oioY Tmyru9xAxnu3Hc82jgQNRrahUrybZNZUPTku9C+7DQPQxJ8zA2RaqYjpjtQFaWAFfUKY05wkoXcR Dtw8VsAdUlOOjR+KINmr7210hdyLzX6s7VreDG+F0Ypu0gTkXGBh9sjebXNhWc+3VpArHfzHQi45 owv4M+80JREZJ+C904fD0DV5AGhUxpZy0reBk5QrUoxqyIPQiFaNMlD+k1zzhkgH7R2ZQbblYLVB AyeFUVbhh0fcM4AGBIrwp9hcD/BYWBo/SwPsP9dx67zq5F4/pIJvM91kNcQiONgSNXJltD099mGi kjA1j+uk7by2uz78ZvEqEJpRn+qiaXwGcz6K51Pxi4jyVXa/c7WvNIyR6AzpwWkuDccoxSA7nryC 3PXcxZoqJ7u2E9IIoSBZvSz3G3A3m6OBKa8RXoANh+56zxE5Y4J+BnLdIYDPlIsbLRCOfUWYnXXb EQQt3Bn/N1cDKtZAjd9Moqnf00pOg67WrD76O8HGR5bdBwW27NUD5byoerrnPEkPgz7YIbURWN4r 3SfoN3PMfnN7GpSDUJiN+ATZl33w1wW7S85b50wuDhSAhHplvqn8QVQ1S2qsR4ZWBrSLMQcijkL6 6y2nttQn0er542l1Cq8E189eEYgLPWxris6r1BvLYLpbGhu1GWt3gtVWMEJ9TtEQemDzEBlnm7Mr /U2pXHoi/jLjP6aALwbhlUAnyDxnNCI2mQ34GFUAuCMe3gpJxEmicgmRWiH8qiJOISSXuKyM4czE +H9/yEjbkRbj5jmZfkzYGro8nHxMgseC39hMKgxUdnjC+apYbdtAydrRRGLvSoG4M+bO/lfQ5ABb D57dD9VfOV1ZDFTdHKTBESD2yeUePzDbJfcMxmXUzZxULXwxWvdYQ/dZQHXfAVvGmriHQbl5zxah TxFUIrAQUUAS5qUy6xd8qZN62zfL4jo0dbvRQuTJE+i6AOqEFB1kybgHf9oYvZydEEIahr8otZKR Qth4cgenVtE+A9bSEU6VfA3QTqk9TJJbXvB6qB1/kSUc2iYG0SiZM+8uUZdax1tbh1BOZh0HRO2x DyB7NRWsR4jlCUUEMczTyGjhpZ/hec8wEhFjgfGkEfS2HqvFoVR5ib5BNyzazxMGb7xHPNN+UEbZ PaDPY1FZfIqKRugqSqXKoDTe+277BNUUZ+7licQw+1YtEmf54eO5VpyXH4CTuXSWPB/xd8y/kuRb x6OJYbJlyxPOfj486xMp9o5kH35cV1BSKPJFV0f89RBIkRGNM9CvZBCgAhBWDnk6xBFFOLNP/fyX GRDKc6TwZAp4pKq9uLskfQk1gVd9ujSV46QGpri1zsTTvhqzw7EGCm1ZMOpD92uIcfLyL352uR9K 8e95DCMJEL+IItfIbfXwojXwB29wMHgPaIaU/8LJpNIH0ewUE7iUTEKVdQoV+bgqQkdBJ6KRQ27m M8Dblv+07yubnIUD2LukA6ClhkxAgw8geN4TjKmthu33ezhT7hFfRB+V0fGtCjP/Od3zOMEti2gM 7etA8M5JO4aZ6i2WGy7TEmtpTXjsQM6b6/uf2IUSNjl6Y3lp1GKgkvjM4rE6rchnOriaXiz3wMUN FSQKbueO4fGOabKD5LCw96UetrjIXEktD4AKV3e93WGEHvFxVpUTBLtPvEJI+n7i3f5YyY3uNQ+n rAWIyvLHTnDGMvxq6U0DR6fI0g7RLrxX4S3T5IcPkWWrqsMVZH0WWmbwWKwDZXsm7OveHojgyzLp WO3eEngDefIj6l5gQuQMXTckov9GUquDQac3geqLQXlIny3CAPD5uHdTBMLZDzLDPtMqG+2XCLEt VgpzDIveQ0ej0WUBDMczHKT3ZuMNCHchUmKhHcUVQVqdjE+0z1yTCAvG9hRo1KWotLRmvP11L25x XBLCBwJ8vBwzcZ/K9uUlndiwyAoMFikb+7eDCsz5aVDp38dyvWUHzqtjNORR9hHhvdzw9yryVY9V ZW0/Fz+93Monyw3iYcgXTYZZ2yk+Rviu2k5yYaSZ6CqbkrSjU3OVx5qXbeR9k6BDWVJTcG07qMPy uoxP5HmeS9VdPQS0A9TzYnI47wyyqHKqQg95VAJFB9n+XR58YWFmpXm3M9/yhqYFRVAB3MqFXqST esnaR57pSNhUIC7xXjHLCokEB/fF9DaXVOmJJ+Qfp3Y592EWrXCPj1LUTKeblFXOvmaGeI3hSH/B ZGYxISIkjB/+ntY8nopGal8a4p9iy3u7/4zz6JhgTBycRlk82JEUlo3B02oGxj82lADe5R4Asdtx +kVtVPvQ1t3FwoIHSAV6QhdD1UzrdoKNdX5+HtjMLDnt66Q7XHKaXkl/2XYlGxvSP3rivLUov+c+ /eaf/0RM+pUGxb5FhXxdXuyHeOP6B+2kPmqq4AcyJbKXU5bchcGWVNV7yvalg8xUkGUQbUvUYoIP CF5lqxms+I1cWhyM2aHq/H+z67KqYkqzMSpQNzyeMIYf1jAWXeJZX9Qe0Zih93q+PWHvoLKUBZj2 x4UVQDJ3qsPa0Ii2Z+p6Bt2EIQi+8EVa89SjIXbCq/jLcbzEN+EweCufX3+usz2Gyg/compSDVAK ll6QTm/H+B42J+glBLXQ8gCQzd+pHU9ccnekBsPN6jlOyetIlHctBfPlw6Wp9HfbuGBp5ABSPSPt Qwb5NRVBTB8AhhQRv7ijy+uDX6cCvCTuN722XjHBdjUYAxEHJJuUE4HGDm41jLRiJun7I6XToNiK 6V+j2MZvrViOC7YCQ7Ih1kq0s5JmfK93tT7JSH2buIHjkA82LiwwHjZRY6qYygDhMo7vZMvfxsJ+ inbShNGgRrpjo0uR/UXV2/tq2O1fgRaB+saGcrTwqP5mZNy8iu6JmjVTSC1Ncuo4EEDBzbJgdRXP 9uen/dmLwK1TPYlRPwv4qMtOBVdp3pX0haEorgWT3KFtks4vmjSEB+kQCNPoX7cK840tYtuWt4Jo l5kYiO2qqy1tcC1vgwl+lhakZQxKr+HuTOP5M4fuzhMk2pmHY7n/uvR0zd5hpZ5UmcpGMuqr9/GX JQDmrT8KB8jQdL+gKPF4C4mbhqG9iqKR6Q2MBxZSrQbrj59OMfT9yVQ9aUUG3NzwJqFkV+MyiEf3 tcD0f21iD9HY8uV88ETBKbGIgz1QycLEPLMIdXNfkW7Xyl1ZyyuBcb+aNr3ZQZFl8mL64Jt+cBFG sddI6gQ9Xkm+57M+Rr9z8uLRC4mIDSsy/bJ4xqfSy63MZ+SISJywzBOj/t0ag3vPNdsC4cvN9CtK v6VoLo0TmGu4CPlOIJffeLM2V4hv7GtQ60gUb302Zjv8kibzw+vYszBu+Su9xOTEOLPWfoU0bl3k wnpd7Rd3rhMgs5wxiLxfnQ+TQkMv5eWEVK5+1fDc3SKRApqIyJ9pvqnE3m4pS0pdvPEKBnmfYDwL 7uqdy+7F1qUTvaHBhxSNDMsd0e9zozKU+WYomLJWFcRbZ1k5lsjRJpvABoIdAIOWUurf/13YKUsW YMYGQZ/uUcowMOCS9ASXv52evOOGA/moxR2TOkEMlqh3dUgPvEL2ym7yuicFnY74UafG10KrVdrk EyOw0tYltho2+Y3OAbrbbWMEYoT+fHrygNxyTFqH6ryWYWOjOoxWYco+uEr0Xqbl7J880uk4xSR1 KUGhkUsjOlWtBZeO6hLEXlXYW2ZgxYIHOVMQQ3pRf83AgMNIBoTtb4Dk6/Qh15h6vlbXe+lj0p+n ObhqNrRQtC5Big5t4OReiL00X2QA6083hHa7myrpXFnrJR4m3tkxnQ1ZzbXqr68nOMj0iHozzC/S xUyUibVTnggJ4IjvPzuAWlCsDzVv22d7tMSGliRvRyZnzLy8KltQAkdsbCk4jdLxt8jPY58GSJdj toyBJGRKDR/Nh/GCr4TpRF88fN+OykzygAOJrz5Os+3+0s/XqLrhQ1cU0bc1iSeUO0dK6tfVpcCo QgKWOG+WqGmepsbBWqtZKZpPeNm+AoDJ74ndFfJeXVU6oB7B/yJLSkZ41ZhCJL8ZlgzXCnYQJQtk WaImCIzWkcf7nJBU4gOwRatBddgHzIuHKaOnQI9bIuhqcDMSOPZL/o3RIuXl+6FIMB+OdI/Re3QL l1iQg0kfu5tcmztvhZxPl2Eqcid4qm3p4OMllYV6vHsAIK3no0F+KRV6+g574cEkZ9pTbknS6d/p w82PwxjiNgDzsTFZDcQiTbCOjV71jpb67wBIytUTB+WmoRyd8aaBKaOJWUMew8QQCycylLjntfV4 xn19VXIgwvsqHIXRB6TKViQhXJGEl+gpqWGvnUz8AbKJVuLUtMb/ad8ZFRcpTJbEeFsc3NDqxc/1 z5bHH9CXPvrt3MJIerIqzmxOMrAdRSiLOD6GiWuRwd2Bvwj7987G+G6RmC1LdM69qGS+m/IwisWJ ye99m3U5kJe4FZ5hjNsqfWt2h2dBOik9vhMv5MWIxJkDUR3jmQuiyeLinG5Yr4Cc82VrowDPjd+O uscCa/DfoyhXppGEpl2ORxsvyzWv4sxu+o/vr3YdoXSJLfO7Zrmb61WkPtCt6vMKWlEqGlgO6Yd/ 3vz3XvQdGKQCAfqBfaoqLNrLxzYsjOGyke71l7B2KbcZRfA6IjdnWsue5iWWfP8cyZXC5S4tjtOc K9gS7HNj2RCtHAthUKFzfxfjbwtiasbcCM2oagsypPmVva6GIPzugG6P9j27QqshU9H4W8wf+hZR yWpQA0FAz9YeeVCQgNNZKa4UzQK33L4b1EtkmV//6hdSBvsyGebYfC1G0Zm8L0MCs6Mdy1RNSiN8 CO/NyJyVsB66u0QfAIgqHgx2asDrK93yUd2OvX6wMQ731u30e7+v6jXOrujawPXYLhQH4kWm2yLN zPKxIapHCzWnJ9CRGuks6jphZ+0cslZyplglX17PHZjxwQPDKCvtjxTiMvmy4vdbmwBl7cKOdckD W7Ryfc1DVAeIBdUdU+YWi+zjn4ELq3joAQw0/kO6ylLCREdeiVM2gOnlElUFFaFKnsEh+UzStf/N eOZ7EtAnT2Bu5xDW+n32yMAkUAy7XlBIhzLhAzYBnMVYScdQ2oH/wP1TUqEvlrqI5p92FucF8xEG XyUnQN2VELtxbhi2q15yvooGuBBx7pw1Vc5yU+vLADbvFqzmEqZxCkOJb01yct/VFAgHnRDRq+20 gq3Ntzz6ER4luc7e+RdgTKBcPpbXvMCoGk73FAUwNmgrpPZ+4i0uf/svmD0yCM989Y1IONXqi+nj I5retutFAEqVVYYjf9HCQe2SXDnIX+jw4O4l2pLoKnWIGfteky/cBNGcQ/AGVAj7MP3piZ/yHilK P6LRgiEMxcNBe9IZ+AqaTQ8iB9V7SyzZfojSl897NnstlUOWKc7MHspvXvU2ScxcCDU2jEySmIpM h4QCcddSbodWP6MPto2Da7fn+w/3W+g1MnmcXF99h+T/CHpNYK9XjCwXp2etKsZMlvx/oTv+itNj CGqU6v8bB979EOqtCNUcLeFHVoeW3/qH1Rv9VRjbYM++K4vdsfge/f4JAhgc/Vu4/po22Q0T2qe0 XAqejtFvf+ktDPY+6+GozP2LTHtLhmcmg8LIhrBtG+dyGEzJoXI7aCu3GJXX6O2beJz8RNc9iyON vn+oKAqwjf3Vonu6gZFNZLkjHZix3JBYQFqCx2BlEx2C3o+0urSOpd0Pqb02enbOYZ0hcr7Wxj/x xMhudnh2zvoV46MaTUiRY5ZYPwBlSgeIil6p0WdD5smwx4EEYq2ub1/BOLj/eWT3vA5wkzDUNE8P 44VkwqpWBUBbLzOaANKQmajBIphcXZLOgO7bpWyZFb7sbuLe09vLbmLdjO/9SG/o8jwg5VqVYl4K ujGCikAAKDHVSzoooP1rE0XrY4rPu9yO5Ph27DU7AivCbJNglO67BvWRNb73x5TWqlHXbwh9veEb x6cl0hT//G3J1gL+udBT0fiUzRw60MZPIugei2Hfptq6qooes5hpPCsxkiBp01miNzsXOOdp92xL dJWdlCTKWoH6B/9PycT6BE2EZd7nczxOAbqzuk52tOVV5Y3Ew8oclLGvCkdE1Auj7Y1QAsg7rGil m85fNGp1zG+jkRMUAFU8xvoP+2yFw6c2AzfbYjQPFNzurOctlqqiGZQwgMgRT9roH/uQNnXOR0y0 bH0gBE/tYQJYJ1WfaIxZQ90VNg3T28RcPgrFUz9UsRua//QZG6ViQ18ZmCtebBeYxFpXGTOqwYQl Zy5Z7IkolVJxJdFbglRrkLdhh4D5I4vKaegima2PXijnKN+iQ6E/7DK83mtnOyLiOLteMrVSxR82 5M/Fxp4VL3JNmy5FTbDFUr0hKnLmgecw5avSOsEZfv0pKjt7SNcGiUcOBPdhIRMGuJjexlUSwtnA 4/3FdXJy2gjYCw6t2sb8f5Qe5Ymfdtgnu9DJWzFP5BCVxESpxGDYGGZOu6grk9+9DHpB4toYbdAK V+BnH0vkhP5uj5R7L+72gEn5CzedJROQkm34Hs3o9wCO2qvjAM6EGFbh8L096DCtY597bNsMM0OO YpfBrfH+4Q2R6IJoP8AdfLDRPBGDzNmLdIeNlmAJHLpt2dQBSoZ+/N770wYJBnRxcUJ8UQSio92S xk0ByEm0SlY6L1XDBIci7LlcwuC1pPPhMMl7ZfqtwQTChxG2LQ5hDXFEL/e3vhwnL2GXe8iY/JxF uqMlj+Kgs8oc6jdUf++C564dQ2Apyt4RNsNPqlkqFfI8chaQy2VIdKCKy5MkqiqrdovIVfiAod1m RR3UVY/ai88RlP3GHLu1uxIHkUA94D1L96uoCRbHChTiPZbrKerGR90lrIZOEdesOK2FyAa9dI1j Snyzzznfze7UsK1TMB/2XTj1Y+nYcPOSNd97gQ9KD+rCVI8/G3Z2kocW7vLj+Ed1Osm6uzjJqp8K Fo5lhrI1r+2CYIoSMBAHUCGxvkyCQ8SFg/Lw6UuYn6UpWRmlLAiLOdV2yKzckmN4S/pMrnCmBBEt b5JOfyaeo9C4UanOLl47WwzErCWykxri8GNbtI7qBkaCNayT4Fv/Gdl37YcrttieLYAtuxRlmY/Y PEv70uHsjTMKwPRnl1Bxxab44YFdkn1JBdLfQiil98pHy4qBnVUBdtuRG9ztTCmire2qwiE7XMHQ bnGeIroHqz2sVexyE8/gndo0RiZHyah2HgHVI5FN+wjmaYlgolnJ2UcBGErhpQuIN25De0FsOhLE oeF9FdrJpaVNH0yo89RcLdUcXF2PcrkuHrCr5L5/grGKsRwyTI2po/d1vdqx5dtKsoSOQ5tva3Wl 7R6X/KmN8wDDXDeFTxmpAkHnJqiJm6vydZByc3PAFwY0axdsoreyEHGte0jnYXX7q5twdVV1tJ7c D6HZo2gDGMixeCqeGA9Nbqu/DkRZ7eEterWoz11d0L5NVNEkI/E+zQ6m8HoqtDD2s2tMffIukcmq 1Ou+/SWeFbjNvW+awPMJaQbZkRWL20hZ48kT4Acfbw0Cc6fpt0sfvXglszP5bjI0km/pUAMEu1d1 iJA+2W8UIPMxKyOdiFjonL6lzEH0bpbZZyNJvuaCgZLdU29HQ5/d4vzv4ZYHTWSxFeOyvPxcw3Xp MXy7rJHwdwk5YiukoObcPh3saxWWnglIoVa5FxxKnl7X/bOXrpI9Z9ywqA8wT9G6jkWvBCZgdfCJ aodpYQKn9pgmMsb+vqNy32fhjPBegP+78gyUHE99mlY7V1h6kTeWLO1fPz9K7InEB1oIk04qbexb +ZAJzhN7HL8hItmuNVI/Z8t3gOq3v6NxldOeZpoaOTV7aJtIlZKtrqH74lMr3fopuOX8KvLY7i3P e7RVd+bCJpEvAuqbBJzC9B9odDTGprrXkgbRvVZYCO/y7ZCSrB7HvCtW3TSDN8Jxsk1hF09WlvHF o/1KmHlFOPQPGvXfCOv2DKHWYYVhzRzmsyITvoO34IGKwYBsuze2puIuJoejQ7AXIZFYyerdlY7t c+3jm2loiqU7lubQeNBER7qUSKgi3H+7Q/3r2qCV+Cqp6QIaZOO7NTgr/gZhK6XLHCfS00WRWuoK wQutFXaEw2yfYCLPgK8+jYVfRpGAxN14oH0m+BWEdqUh7J1TzFSDoVEBgAnHaM9obYM0MZrkpPr8 6TxjYD20lAdw/jYwcua9NFCe8eVc3NSwRDNCMNxskDWR6pxfoBmBacFjKJ+wOx3FQrhB1XHWjB0a z4oYKgf7MEIr80/CY7e35KJdwQLAwvP73hONwFjurfZfJde9ugS+iLXApm+14/AHs8ta+NxP1DZR HcYB9T+zSnQKX/Y6VfvVbbEvDd2z0DIDhGp94GxVEr8ET5xFgs2QCALzywWLPRLSxnKIABSNJRhQ 0LJuc44C+uPpBIP5Eb8LfN6+yne48P0dEpTPlDxnLLk5YXSeB7mCuG1J6Fwgz33Zzc1cKLKQ1WoK J8trYqQqBO8ewBtbNV27r3suycmPYvzXjXrzuGl2kE+wOwitx2bJK2UvhT3sQvD5DkCFya5uel9H lhegnHwJoLIzotIB6JDG3132z04H4GaFFLkvIWm0SSaRb9OxydzdU6G3kCmsXPEOJRfcncqGJv+c FFFz4emD1OloxFxIPBSK+itjhXHumfGRV+K6OsQi/QegtKaSXbbMLsqR65n4NZ5bMr91llQOVGCk Rahu4y9ymrncYhrL1O7c8T2sUv9nzlRkbMWBL9BhVJvmH9D8k2gbE57e41V7Yimpu978lMlnbPby fJkl27yLTGQkJKNoBExiD1huzvyztbSkEMRhnfdH9u9yTs4zHZ8JE3ZPWhqWn3hONFWvYAupNX7P xAXZV0jx0gJ9RAKZvPCRY3g794CQWEhnbYaKFazEazhmqMhrcASVZv6CQm1lrfUynmoLfw2PYlPl DwCxNcp4hQ+3VALAeI8Y8l5doW+Kh4uPKtGKCKnweDNeNm2n0UPizr+SP6oycCGHD4fkzAIzh7oV mKObMneYRHRHlQ6yaWI+OCPcbLc0GzpG4o7JhNX5UZdKJzksDXmftnyFrlCfskCqhux4m8A671PO Hk6XpztHEc09CrOjXh0vePrtMsqTnwkdDHBzQo/Llb4Y45CnlA7f1WZBitqyRQ4H+dYW0TvzctZw lNCDgBrmqP20p5VXhuQdMDlKcc0FHqYONa5KKiBIIm5AidUMaQbbKnaO2d5GVRW0sJxAg3hq86wU cDbCW1WpQGkYdfWzYEDtmXablyItQAehBwjubRDVPBu/BC2nvzAUSxGb8mORn71Jyo+QwbT8V6hs gY6xbtNO6MXPuBlaWl5tReDMHAMoxx8srVRyxXYdrULDAFL6JrEmk8gqvudYzsMIw0Oal90j8wkK uIAEGDlW+nN0dwmghb3lBvRsEd+qsfg9SP0NrMFCdf8BqajlrueT6rN3xtJXoEb/DFWMHebZmfIn c9DLM+y03EvpDPgDOjTN51XyJC6OZCaFrUh9hDMx4dJEYdOKu9MUFhPZzVFA9BO3YPxmpY/hyuHY mhvt3D6HgGf+d/Tr9lNb/JJLw2HZag0zFeNZu8xTKfRc+Qrlnl3mZ3jL79FWTrzG27ov2no4zbz2 fdc57h6ydq3hsauZSS5pphKmwL4XiPOCFOkpHUnovvxmZzct3pnBSL+j/3Rzimq6h79SAd/PF/Bf QcqHBI/cTtv99MFEf1Am8qemBJzGap6yssTf+v6EjbgwBuAIoRCdckFs8zRLBq3SYxut1DFkAJu1 uUewakcq5apoFYEfwcHm5EPH2P4NbF5mjKqpy+D5WsXaBSUo1HDNk3ZpgrrJQrLU8iK4J8InMaIp B+Fadw0DYGrgVi3KuH+h+7x3tkbR3fVQKh49yJ520WkuDvFz1I3FPbkQDCt1bO7dj8NTLBeiXvgu cXta7+TdR3sW8KAz6NMnqU3Q75M070kfQD+b+LFfWkPjbUox4zAV9L4S1oKP3TWn+yLwJfxCq3RR PJZgQMJ88RldGe2NPo8TJoQQLyaUxFd3ywfmE0VcjqMkAC2jpxj3MsqQ2y2nF7XpeMctNmGsTIJB m0pGg/MW2YIOE31XYO9SDLb51JWSm0QCdLN+qA0dHYM+4RlUlAzGHJVHTIleJzJG4jPdYI8rjY08 nDnUMdfE/0fmhAg42z0eJ73BvNGR7hCp3QzPY5M35iOCOM4E1tX514lh1Tfpx9q65FLhR/WyOGae GbjNgUPmAiveFiQNere4jOwO9cJWyf5J9gIRV2cLI7s5xbgDCEI6cJtGEp2odKntDRTOQTsJ8ezT 9saMSJRJrrJbAbQfIDYFETbJNyFc7znddFsJ6w9v7jxlCiaRyQuoq1S9nGHoZ9pAXmkVqNoVbZ2F G/a+3TOMIiVd6qy3drNVHycEohXDZypoB/TbMUkwzLlVCvq9F4Pq5FCc79HE4CbGC6ViZe1gTViJ yinG3LPCv8A9+XURRc+w9DVTveULEpCWGb4BItMIny947vDeCNG8k46IypshL8tXiO5QuWl8UIYi GnGbBA7iTgtWiWMfQQq/WIZvsihqimoEbgk+xJyB8g+G2Nb6Zi5psCLxQll9kRqytGdlr8+5suna SlVx+s8jKViFVSW5dobNBTVgr+WOEgEJFH1yUhAoXRs4plfGE6dfFI0llxD37Y6V2GlovHdJPznV +tyHJpsH2H/wDK6b4fMfjVQ79ZrDu/sNVe4oB050FY5jETbOMi99mdx9cJh2K7dzmyoqYUfIqsUV B47nNfcSjPprdcpK1aVciOitAf8mNwWHk/jcs1yOSrszHVYymZHDykVuQgWlMJEXMjCtUL7Apr0f rF6vInlgJTch0NvJEvbGeqWx5yolYK+AKgdTpF+Xbj3TauKTME8ye60h7u99r5Ayvig/HSARD/8/ qtP7NGs4eA3FNuK+YXdldEM2exlRU+FiJJdA11L+xbcdtfwM5vvdlC7dFyQ+HWjlzXVbr4x9YAPF VuP6juxcDj7EQWaXJeGPF14WVpMiOvwiu3DfuiT3cIPiMaw+O82uDgwLGB5b3xy7pQn8dLUyJ2yn t8uToXqtJ6OKaJfLJnBdJwXe8Pl+IuUOPLqgtbsQcOsBF3tCn3FRj0R0Tk/5GfD2s6e56fujkr52 qU3nGLAW3cvY52jYPQ5GvpH7S/+K8BEEU/LifIT6liths0YbqpBVykUbtQ8X9EglVjKYZMPLtLBQ tYZdYGNYDY6nfFUGL9aLdhGGTQT9cMYQdovsBsqeF/ZYP/WxoMIL6cXDOwikTJXleY/FcYukAvJr 5ZmYUzMahrxv+AR1h8wUMgMml07UTlPy6LvG4JKP9H0m7NjkGgBILRkWkVk9VpnQKqqYCyrTxaRe VYP4ntgmod2IO/5qMi/02TV5Sbcjd38yiUUuqaNsnk0m9kSIYitHHfftpy4pfBHDfkCMdOnxkg95 6rqs43VPDhXnapKLk2x/ktNjoWkAoWirWlOV4+N1GOk3u4F7m50wLM7oUPN6yzyP03XN5zcFDt92 xRDL7HWZmJx0HDZvVEOGOfA+9EP6TLaNB1ve9M0J/EJxiZ6r6dawcGWCltNdRPPr2qO+NGmfCzjH iqR21ebTOApNlhH/PR1ML9K8pw74d95NZixHO88Y4YYSzr/mh3TJZViSoyp/2v6HmOr/yWiQZ65U 8x/FxajLoE0sg9XCg5pIOtItV+LPH7ABp2g6uLvx/8YZIGYdiXa1ZgpTnIyW4oesYEN06KvwHtyb Kol8oHFtw2AY+WlxfTrC3lwdRIoTNwi+zf5eZyvylbAR2ugrxah1mXVCznOrq1H5MWjPDK5NnVqC z1DU02KAVeE3StejISjhZXnXxyeI66WFK03mdaSUDnHzHf/ECSssI3e5RcvJcypNcAMP/vd9bHQE lO0oWSJOcHU5DBs8kljEChExNTN/7iV4D7XAVFoBw1Nu54EVUXOQmNwsYi8TpsIsbZtTgXpewbtz VYk49W76EsyyS4bGBSLAeH2bs+JwpTWbUOVFhsO/JKb5nDCCYMCbe5zOw/WGTdqAmMuZsAjJTGYD xqd/OWecMAckd/9+CnHRcLU2AETGnAaEBqQILPLAt0tlX2WKirjpg2sfQiNCWnYhW2za+ZLIHOcS s1mVFyvBiECqXhmhdgaTPyUhod4AnsFjX2/tPRrxkI5iG5AscA4X1G+Duye9QmYDsObb8kdPj+Hu VD80hk6H9OHJOfEA7MS9kpHZluhOzv5gj00RnTVK3Eu5nVgvHoIHK3vU1nfL6y9Wesc/gDctQcbI VbSCbXO0veX9f97szRsy5xlUByo9WiPr8Qx/nbAQd4dAV+GfscptsYbiGbGsbpX49W0hfiGKrbEk Mjae/Rzk3C58cR4ta9L/w3RzRYKOhocVzpRApipAQ1ThJzBQMcceAJ7U6psAy46ruJ7JC6/p6RNh nXeTIUwIjTJ1PvvCakxMxHdGver6BzYL4WzyGmv7U7UuVrZKoqRcOrx1uTo4cEVn8+fiBvEScm8k tFDyC8Mcmkj5ZIPOR5TTFVJ6dHf/K8iVUFFOLTcDIcrsaVBxLhKr04D4DPfMnt7mq+WiAPzv54L5 kuU8Acz+bXKcdtcK2TRGIfzsny9zRuBC0ybFBjJ9lfdVU8aJhNVLAepAam7/ZbNpgGe/J78Qvvuh 4VYqjoDcnieE7/Q3IPyYOqtjLFRbb+GmE+I7BdTV5VejvQlz8yzAGmh+Fq2jk9VTIiqDjkHAnawb EdjQVHmnkCel3C8mCiDPeMbyPOxC+u0wIuRX0q5ciHJpL2nQCmhw0Xlj+UeUQAebxgBxL2dnlFPY /hi2NAZiCsyu3qdJPe9iiMxK6MAKqVs+ID46PKZwpI0yoVQzJN5PUaO/9F5E7cARV2kc/puOwZdK L+jYhk0iB/dmoCQkOtvQOJkiU+xymi4mE/WgQTfn6bB0BPst9AOyHsDJumoOoTjcX8i1yj9EwYa1 mF2yNcE0/SvmhsMl8nh622wg9wveReqNelF/cTAcyq0B4mqvvBosFkXvhOVa+/JA9AZ1D8XIjOhH 93yGFkTpNIXrBVpxmn/b9uFitEPL5R1vfwFMWQi596zplFzbrY2gTXP9AF/mfoZTWPYtQGJLYM+b 26+QvV0MKpmz/SIvHa7Inkqp9mtmBkoRIlcAIeS9fsg0doqBCRbr27V6dBivVyA08YppI+5H+6tw zmcnae6DYGrTEkR+dGgnFYgrgYsWEOybfdhZMTeJbYjEr8AY43CsOJMLGwQ2lbZYTOECRxnxlHUy t5D5swCCWer89Rcj+QHL5ITbadLHea5MkDqUCwidYty/1ZCjyZr6FtXG6q5O51R6UCAoS7lbFoMm 3vBsPhYUIcABpCNTYqNpPN51OCx1fLwh1qeraUa3Ak6nDOpD8j3fWtnZqkqzm3+9x5HvAU7O0JMZ UeDaaKPqhFOic45q3bXqDXnaUaZxnuLLH7eZE41nEJKmBGNEsF/OBGtFUa2jD2O+gNS6USdZBSMN GbHIhhkz6DT2LQBy5xp+tU+xbmckhR0OcPrnotH0+rKJQIjoySAiPa6Xkb2LHNqsm6goihJNbwNf H6BQqbQuSH5nEzGH9GsmVA2Tqmi85nPCCZU3kyGantOgB2khxslAQto7VUMIKitEr87nBzwbyAxL +PHsXhz2nmUV4xT6GNdYjJnfZJYUdRLRCjy4EzZTpUbWgxuOJgWRGw6ZmgIi7lesCH6Tc4y1XF3R QUcUo2/QwNNYlPkR/XMXCZgDWesb1tVTQJIDaC9na0KLiKtMxhDbGuGxgi3tkM7L+p0nO85Od9Ru k+qMFujlYziUtZ+l8B/PHOVo+fsWZWzrk+dvdGL062fugU9CYAgAnrd3UJ9Qlyg0sHGMa2jLaRtU MAzGquB19EqeBV1TmP+kBYFSUhw02RodsE5LE3np8ZSSUmpdnwrIeW4EVG0JfWkyDu4oxC9OKfmg dn11H4+4oihxZet4O6afODApxILAer0zd4+rotpN0NUaE+0FvtCVEYtjLWfLFy6H4SDMtXla4gO3 mKESqIDUkbkHJWOjQqvpc7V8FzTKYhG4l/5Vrkwu7PYHYz+LKNoPuMF3IuLKifQyzjvx0BGdYh2/ ZJZ89PK2KjAmcSpOXwYfEUFzfc1BRoWVaN4OdT8QcmiiDjuzNPiHOYYVth3qlBteZftJSC+54xux 2dDtlmwl56bohLRmQa2kTW2hA3K6wGYhqKga7vbeVPDfIwx3NrhLvMIZ8jKGSK+s6F2XlDwr35w6 UGDfNfUFiTMtImSJ+YeVkjkkEfOkTq0viFI2GbV/7f3fP5LbzUoh4EP+6ahmHGa9Y3/Mprx7kXQU 4ax5qvLbWz3sfvUkUZdJUl5NdqOrxDPCmnnaI9p3bK9luDH8jb1LEQV4LkGdCw04R/8it29GWBx3 DkLRdkpUXIffz6BOvDQo4RSXTegPQe9WepmbwulSTx0Fdco3DYgI7HCmHSjqEgBqaVetJOC8NSbK O3gdNHSeYdL0j5+9swtGARAQzkD4BLqbldEsEK83E0elJ/GBRbRoxJ7xM9cobV6wYuSO62y8bTxc w28vlnUhI5Qurmc0rWnQlpqdMmFEWtD572OdzVmv3Gs8I3Js1s6NZ8Hu5GKG9PpawZt/Bu/JwF7G 4gvKH0w5pdcWH1zKXW6qxJD75WiZb05NRaLhDdNmhWXSy1ULpk+RrG2fbEO8BCUEGP6TvSYOGHUu ajfPijindOQmoVBIIQmmkQDmQlKMoRo1HRJn2bzRgjxR1sXsNkFJnY1xw4dUOndzuUTqsMF9TC8U dX2f2G3xWAi/zEWXOgZ21NxmrCZE/8VsRCmcCzRLoMy6ci5jb8CQ+teglP5ewB3/djrevkI2pmvB DXiKwnyUTiwYWHreeTxTgUAnyeifK+SToPDJ1sqBlFfSkRJ+TEYrwNDBMzlDOBzlWZ4N6/TjWRL8 FF77QNmUaF5hpqBIZz/35r/CYnUmTLs1Gojn/LjmnRVi+zr3CVOsvxrgO/wrrD5D1iuDhca1DUIf 91LVYEC4ogzyA3ZCKHdSCrlefjQmw9bPm9UFSwty5k0vPWVyFvmJKYncUQ9niXbJSDgwsuqTDfHg t7GIH6VYVIRgW/bcL45B6j0Nl+7MZuIvqj5tXSjgTcy0WnkPu04sUaH3V1ZQiQw0wNmJS04Qctqg 2oD8gQs/t1VLhiFjk8BxYSQw0TK7ZYTvTDCLceH30a22WVMxjrWnJZ2Yh5LJy89TpSaE8HktFguS BDwoLA3VWdaR+8zHMIQ2mBek3q78D4zT37t8lpTx+gbC9ND4rikpOV6ApF+9E1zeXIXyNE/NAngm MpXPlwOTTobk5nDnS5DUPKabNlsaZ//uvAd8oujCnisJlWrhttAduPNEtS5Sbr4A2rs13+dIvGRl IbKfP5VImbuE/xNBTfPUnQxsaE/XwVfUmxlxXlzA299+t57ngyg/5jlcpOk+qo7uQhcSIPUYABkB 4QLyMPmNJ7DID+vgW+WXmnzzJTCe3zbL7u7WH8Ozzr9DqxTjlifxv+RCL2OoEm5HjHbNI8PwC0Qe snRIe4Jx9kJ2rXNqbZzwDxOpvwfoDFLcVDRdFY0crbP3YU+5ar8tsylNTWp3mXbL+nz3wnXjiSyt /GV5g97+d5DgRpaOMlB0o3XvOj6KGZoWZ4bcAST/TxV0Uv82jz2xZuOAc/mAEcIZt6d/S7HVS/of FTiOwjg0Tpb8XWBZ5PI2DOBdpJAGRWsFBM9xz9S1NFvJlP/UgO0uykx2RByEfB8C7nAlqEQFrL0/ d1ltXfVZG4BP144EImWdwtBRR6JXWYJcoQyNhorOk2jJ3c6wSfMs2F5S/q6oB3UJYQf1WVH2sVe+ 88Lu4J1KWOshwNq6MQP40lmgja93L9MmNx85gN9jKRORElaDJuuCByF3hNMWgUXiZN99i8nAudsq d/RnYBnIkwB7LNcDrxs/TeOq6wtdo60voEWM+WMQO0SkJveLSfAk8sLHDl+uKthbqnvOKScLy6r7 ztIFzYnSGzuncv8wcfh0Y3nzdXtbb3k0Z9gaj7P366EkJRKsmSGjycvdWCxGdpHcyz18U4blFf+6 8P4+SLWibo3PI2RVyQeBV2iXA51Zd6yEMRvFEV++IH8BuJpL2LHw2H70WIZaoN4u7GTl7uH1gBTA KgGOzfmlsySg/usIOIYdx54TV5aqdfF73Gdi4JKj9GOgYQSU7nDqEIAItfEwdecgaxvAKiG0Wxpn MdupAXuKEaoNx9635/CqdkRCpITnc9I1ekG9NPA5qSOSKUidJ4LRf0hDelaF2Xu/ei/ja7SL6eDh oNYHP4Vv3S4KKrg9AX+AabHB8tO8XwRSI1NmugcsDHFX52FupvDEwfffXi2SJkqOUtJg/axFHZij ptEFAkcWZdfAbqTX5Oc7G5fXToupSa5O2uo0MKK94tpVQN/FgWn/13LDDNuvKIvavUe732YvYd+D dNVmRi+vh0mtgq2frhxGGy4/BjQxqVjzBnNEKo+x+BkrkccGu+jNeAszaNBaOzp/vByZDDSxTcUH 3EQ79e1r+5N/j4hQusvCOy9OKH5xtlEo1bef+yy4hVjpQVPs90hdPBW0G9U9MUHjvoclT6faF4a8 Yv1iyxJgqbWFJocvMpM6r0PSu0Bct+RnYAbTgz1VKCZFkbtNx1Z6nTasiCvuIRZhIM9DRpogYypz 9pTbbATgU+9vGE3dwhwkegdTo048smElk2iNOhK95tl9fgPfpkUG1GaNYZzBILJcl/vua83L2clc 5npw9Vd5I9LHh1TRtLAPQTIhK8C5g0OjL7eJfLrtD+BpzRaQ9FXpb3JHvqyQvvYc9k5fFX2RvJOi CpM6s60+sqrGjAeUY+mZX6sEEjqHZrW/CkiF4YrrIG2VgAwOsXYDkRSSS5i0yQlpdhSoLn0IQqY4 UFF4KUYT72411BCG8i76XAGiERXS3LL5eAvK+/4tcktAL7rYibGKPLErPMGKLGBCqFSpEzyv0WNz Ue+H4gCfG/ktguDih41i6xq0JlWIPK9X8oycDo1kbLZcCx9QNM9rP6cyIWdpz9mdLOKSYE/a7FmV maEhENnM7mU7XZ6clB8xxIUhPT6GZcSjz8H95x5xvK8msbTYx54hqUtUCUYgYgh9KA+9IzKcL7Hn Ltllk8qA0AVQAtHye77bIFMFaaEIb0sach6PvwUwR5u/B5193MRZjB+lDprlIPph5/iJ78gJXA8Z frt9sS4TLjwCfqNTi1H81/izcxy+j8r2LDcZYDYPkyHZ4qYgiEAwMT3a0e9nWb5196/5vP+mz762 9f+4NDf+/esAGrrstQXYYaFEbYA41LwpJGXixQEzHKOToT2sql446fCjanp9Q6vP3qyhKIX5cuPd rCEzKs/81JuK3diqokjIKUaSaU58sUVagR5KYmj/vv0M3mHlzVFtmM34Kuh0gBNnskhGq7OAJ9hn i524pj+S7QCXbQ3ervbHhFvFcib34OcsGfVDQf9TQ2t+xUFvlXRF+vjuqvOtKIPFxBhTs5jk4/HH dOUjVP8M8+rN9+d1FkcD1dbcQOWHzTSR9CnhLE0Sl8W/PzU/eX7xVNMxXehgGn20/y5e9ad+c1rd 8DFSW+39auMVM5DF3pHgQ0vZeKVNcJTx8VcFeShMspncJ3ebx0om/VLZ7y/ON6qlwKn99l5OBnmE wVSBzfzNn+fkr6cLG9WQF+NJo65MMsaoS9qwnzt178pR0MhPrS1bKQmh/ldSeIlAVHBS/4+SnOrQ cnwBDCsgHbj7ycKVc4KDPY6Q4Xy+sEikIpNYUNCWt2YEjBDhS4QfQ4hAfc6Akst9VCwpi5FFytK5 qO8rvVk9qsgSEJooHhwqJHLdp9XVTHeIXGF1YazWY1/d/TScQ5EoAOUL5X7D9qKXn9aygkFlAlVK ySO5asQX85smjUtnKykBSKq7TmbVNbbe9jCj3e2fXt6LZLe09TBUFX6rZu4kEDvOaSzylG8Znb7F VXASsgS5CmsiHcyStucByfKyAr4aq5HnJavHJvUkxfX8C8sqrkm9Yjw1vuzlngbXSTmR0mTRi7rV EJNqQ3xbslW4c2wWWiWK3/3mmgaBOhBZ9Rg2caGiMCwO/8o92ealuSVqmz2I5oSxGs/QLA//rKBc ZoI90/UpWwAx23OYxnLdyr7uT6zZPhsauYtON3qo1CT64alkYK0/GXD6AgFPfqT+Lozwy3zcpV7p 4L7VaxibrQGrK2OIi5aHZn9gQEI49NvR+Hl/aD29kOEcwWwRmKpdKfkw0FVWV/z+nlF7xks6dSnR r/1pDymxSQu52/kqQV9h6HAYaeusHKuCTjGjgAMAWIAGppMpD8Jh6PKwnGkZdR/3K0BKsXYB3ZVm xh17tuXpjlbw3uqaGW9ihqgC0aYFnC8Ei99PM8UQMijYsaQhsxy21NkjaULubzgCiPLvzxwPAUlU tXk19yqG8BJttxhxiLNmGRQuVFdf+r9FQe5RN7JtCsZaVOIdaJQLk1WopSxEkSLuyJhLtOixgBuB BfXvYHG+pN3qQ9iGkI2IrcHATqu0RHwfPLBpgWNyG+J3nPf8J5jQYzgmPNNOjy0sdmOD/OtqdsP+ GnXs/17/F9g5YKguHtWc77Ox5Gwef0enIaza0GKKLgXGBCafDuxqO5J6CnjeeE0pLwcLkecZLOdL SNUn1RmcRBZBylczuHnFXHT6yriBdwZA38NqHY4TF9CUmwBCOMqYkRWTX5su2qHFQZ4tu11aHSfG FWVfEhlzdKYKYNA92hdasLFHLHgUO6MmaODsLCrnipqeooXE5L/z+66p1nL85wuAXfsMrOFDw5X9 epGH4xeoVdE1aGpmZryritmDwuGQgBTE4V4gYLsLDqDrFDgIzPDrIZOY5QBgFEADqvYh9u/pJCLZ GQHgFel9YlawfslBDZX0rjWdQRPDBSqG0m7utmvIkwJWgNnugsrg7TD5ftNEDbBZiAnfUCd/t1Us Xaen9QUIxuOxIOcicsNV5t0dKsg0iQjCeqYmyj5272ffsCagviFHl4eKEGsHEMT78SXUiSWU9N2V xfm0U0oudFNvbOuFmxAeMahQWcoE39e1JjM5qVU49wGswsWkt/xwve3mWH7wAXe2xiBDelkju8lo e+3iobHlFBW82x1NY1v6WGHY8ucE4KLBnyeEe5aPwKc26XAPDf+VO+Jxel4j8pm/OwrPE1rA6Dck BwZoLuEjbJE/nlQd8E3lgA7kFJOccr33U0NkeJkfDh7A7inCu01Wskoc8m4exSEWkBQi9I3Eu+xL 1pKFXkaIyqEOERBFsXfp2hCxrYnvTbN7AAM0OKRHCy6hVHA2XEJW7uO5bQSWXa2oPARMPhnqUNxx Fa5aP0Dm+cpXoMtfkLs8xnhaBPGV/Lb/7mGVlOnvNF5/O9lUZ5Mt7g6iw2Yf5dCW+nQ/vpQf5YWJ gmxWDFeCWG3N08pR5ZWUBfMeZgmWZHV8ltNsrfafVRMpu41/bmGn4vB7LVtymGUrvjPT4crptOAG xPXNRxh6wBgjtD5ylpDXbr4U/+igOKkiSDdH4yXNHUwOoyxnj4wLn6Ln1AFKnlYoX0N+KYYI+aq9 1+Pe9tPxzZo19ski7XB2TdgpCGINTB8ZNklqiTXPmY/IJzHC0aZYM/dRAW5Z1o/go3oGMOQgAcIc uveUfJ4+XwQHEkBD6xD2NecLg3K7aIsgxQzn2Tj1XHUMBAyjJGpSOuKLS6kbgZ2Q5McfDRVUUa0W ts9cL61vhB1qB0bZXuCTVo4Z3n05NqXQIxxcakYteNnD1j7WgFAMTdnbae2qD8DcS2lYVxhJloA1 vguz41Rx/3xv6BBgLYI+J3tBfVnxueSyEZyozZ0eNdRUFD6++h8mtjgYqbZZcuQEdVYm4W2WqiYp otB50eIB3lbvb5OzKDDs1bXJVKOv50EkpwUWBqBFRnjIsqCdASG6sy4CdfR7lWlrTTNmvX/u585e 7EaYmtlfWNJCeCnQkpGG/dD3/8Kcp4TssnIBr1+xEN0Yi+wplTkeyQfGXO+9qrK5gKuQXG9wRdrL 48TYiwuFHDATHgSwmoUS0zPrdrNtNG32Up7Y4LYw9nQIAh9i9fjQCibvb/6O71LQyTT3cG9Xc7My uAG3qME8H9PtItwxLcAiBVzmGFc2/ROrzZKQMOCfeyQ2O1l8e0IEjGijtrYffP+NcJrB4sTZMzU2 +vw5Q6bn5g1JXttSrW1MXJPCr+6JabNMN6OXIiiD0DNoHNA3Dau+DoMj3qR/UubS6UthMbFhPA3W J1XIHhV1zweInCFwPU8MSyMzjnKb8tEP3FnDy8rAAuJXE/jeeP5PMxhO1fTEdOyvkA6jJwgmF6en 9Q0YFAHqyEWFc4pfjlsqEIhiMGU6HyysMaYLQE4yGDSVgEqJQrR3307IBDbhU4EfS7oDV9DQIVnQ qJFrd3GJNnfueWOZ4zOQZqDhp4lGmhvMHKv1dWTwGW3vzHicD+5kFHc4mUyBkiFFTi160rGyTxBP EKGanBtGW1HyEuix0CKCo51zjj4n8AOvVbq5aijTrSzEbCkb4vnfiwPRIe9b6Z80H78cVKuyAsel LnYdVuYdfxH6mKvDaJ/XwRxfxfH8mRk0lkoMnHO1YIf0f9Qx2QfEN1y3H5NbuItU1YN+zMcox9qm NyU6TZcxA103NEQ5R0gK9Y8ntyCYqa63tzFzKuvC7ieN5OJmG3PMzTMkljqz+qRX6CzGjTmCrWT8 GyOtoAV5lf52vWYQGj0TguvbQkvBCZGQ6gu2wCbyf6DXG0Z7Y7iRXEm242Ygz3vbsHTuqQBTkMFf X3YJmV3e8BfrSImNOFquDBVjTIhQu8McCuLrKjUNf+rSIlYRaKmoKsAo5aHhkzE1RiAR37Vsljxz cCPhKeeinXb3UPCXDa8bGmHNUMh4Fm+/ysNy6cNyGjCCQkRoGFmOCTqM3YiwkwECp6fDNslFS4+n 6/tnH8WIRb9M/0ETN6o785BxdgMXENZo9OnA+40Fhrbo6FxvTjl7Nd7otxViyD3Xm7R8ur7ZUquy GqPYq3/e3CRK641r2H7h7yeWBSivMpF3KjbI1TIrjElBGEuoOMp4zAYrCRFix2PAf6+dDmT/vUB5 r8ovELlSrDpfsZqXVk3FvMb/9OyBMOAxleOOWjoMVcbl5YhS5Sy0EBZP1iEJKgVSqX8LzjfIlYB2 BqUjYSK814HsnMoUskOKwMpG/qAF840kWhPTKE7XL+iSSum3HEdUb5pH0t/D5Kslz5/lGqN+OCYQ NFaho0lgDwfSk4cdNbutwdX6tQMWmZsPpS1D6+iStn6aK19Qz4Y5CGv1g4YwbtD12kC/0ETpVZnQ weCJewdiJUiy46uOFktNwpzakXZk3RNtW16wfKPCQAqOhtFnEVDIIrSlkZmZwKKv/JC5NEei5Qcu 4zuN+Uc3ASMNGUMrTee/UnerUCTiM3Hc2AIwYH81EdXcwp2LwNb3goYrWbM/ypRn0W2eci4S+qQP 9W7tk26ptgqM/5m/JWQLH6b5dGGwkWnBg+1FvTEqvQ/BnB+VZuNFg2khQr5m5e8RZqpKTIoCGids 5wDV9FhZUqxMeeM41NKNuNpkC6k/OFVmRk4wpKkLrTb6sHFG7JJ+OaePzZ4VH2g89qJRfvRnpj0P +x/hFVmvl5Vi6CDcajBSTBOAe1i1Z3VzODwpa/UkWs/UEGLXQ08SS/3V/CAlPLh4cpaBrmLQQyOs KoaQFZHKivhpxGepPZjUC/Hj+VZwpg+8k253hwmcKCzhkQlI22FSceWnUFjmuNDP2PB9c6X/CKiy QjZw1Ga8rB1TOLsrOmoIyvK3fx0A2F6og8XyalxaBM4tvc8yMGbLRDDlvomQDt0cLsxYDwpMGT40 8W7r+XWq5QN42Oo57294gUp8NxsjkTco5BJn5U/Z23ggwTIS1FZZ7XfxQ2NqlauzjR8iOJnVDo+7 SCgHxIXA4knKxLhuOe6iIUyIMfK+fcRRNZnhcfnoqzFdvjAj0rY6YZjvc0dMh6mzrSynJnDY9DzM Yu8zwcyuaWRd629PbjmXdHlaYFTuIHPdvVkNh0dWFTYRQu3YWTZCnx1WkzjloBHIucITXegeLDco 6SSfyBedJhWI5ak/4JX1FMOdix1GiwW4uUWK2s4CD5BMF6lNQmj4Qa3IrhC5Td12tWvb1bFO23e/ i3vJN2qmUBWFh0/+aYuwHUGa3qf1lEObTWJUd8eeeDQGRadTCImIgM6WuWB80mpwoVgctt9pH0ZU GQ1oxBB61csKQEbcnoTj6OJW7ygcKXo+mHe6w0lZ3VFyQZJIDpo5WCzwSrwE0IiaU6s7hknQ4E8J doWfH9QihRr6yb7SG0uiXlmnQN62j/HY7h8GGHuaN6FUsdKf+mNIxjnbUbcBevDh+5hfhzqE8JUS wPo/UWjIMNICsiBS1w6YYXzD2V1DCF1lLJ/tRXimdl3nQNAH9P0k1OqZHAM1MWqbah91Dg2/NMCp UhzKaBJaVlqDQVOgCxiKdfrfw6lYZj6tEyOms7G52En86wMxyyqJLXS57MoafywJcue0zUOQe88n 8uCN1opnzfUNqOzrtLSxtNQq2RhcXuH+13Nk7FsioSnzGWL2GAdPoErjbx0oCjhFTThZOumDeJpG /VP8vFzDMtH/VHSgX08XWNtgch0rST3e7j5/mqWPlS3tmodxnR6MCHITs//fl52GoJrOxWKvFncj QvGuBTlcbOy4ovUtJvKV7g/iMmYsVrltk+c/h2gdFd1N9u9f30nSBGkBLWdzvToJfX25SqwBA2Lv gP6OCxCowUJxmlnXE7t3YmPdHCCy8wNuvskBWdxlCXDk1GMpFp94NCfS5jUu/Jx3ev5Xdr2bZz2n EaKJmLYboMPDhPnannFNCSwq+x02Pu58JapZaAhs54g18Iu9Arpm3Mok0Elii6bdfxjou+r26Ua1 x9ahXEuAid+L8Mv3SJDAgROGzGzNTh9juXs4DiaT/e2d6CemIdCecFKh/TC82oaFlsDppJ44omfh GSQbDD+3O9EP8+3Ovbc2FoBI81y/X+8QsabeEr/L5BaMPivA7sVvFets3WQQgCbEzAPQ4rCpuXYT uKSp9m76xtRv7gb8cY2wgukWhoeOfYaqw/1txrWJW4BF95RpwU6v8qLma1vNN0ZUUhVwWuSKDCT/ IvVpx4bBhGAH00v6YCQ1DIgQh9hCl6Gckvl9b/O+9FQ3HTPcTQaFH34y4Wk+7Xucox7DsNVWYZtY /IseMLNS4uYOueq+Pasr/lLiXRmwqMTnUE9QWn52cgWR0wIoHRmp8oeCcC7284Q6FaHWWUKNXEzP KvAQolzavLqFcyqzl6l9PA2CVSXBb5knQwZV/ze7Tyb5A3mpYaLUBuxFqNyQnec/4+KLK7/6E/sQ rN9cXTPRkqYQIuqQGt09GXIMURdGoJpEd2nQL2ZeDeYsk0vN2X0H5M8xJH30acBxZ5VQxkftx4Mz wwCkDCPE7KwyV0hLFMz3zQ2ERrZquinkFilqWXWqqjYwpvt2WMzXHGGmjMEFAzVBDcGQjqCKvrkT UpX58uYxXzKRBiB42zlP5jJEHiUYIlSyh+QqM2J5JxAxEWjggwcbd8IO8+oxsaj23YNNhHUAvxaT bWhpQPHeY1atJT3GueaUZ2Z6RCj8ICXwxX7gajvy9DujoIqgmf/27wlDjpkyadGT4AYEcLGNC75H L07zs+D3ZNcgbCa3Piy6VtDBcU48iePgVIt8qNTYkLhDPxwmfuCGEkzUbMw388ao7B1fEU+oYG6g UjRiexDUqRUMRKtOEc2xnNXOEIecvuQIZ4WKE8wLNrhtPYVtTarB42iEdaFvYfUes3vM15TQggSm mdZKoXVPrRokTPoC94x6QgdZB6lkbT6F5MESYtuv87bmLFd8tC1bv2VVryGTNtLVcbEs904eMJ0H Y7oUr/kHlBNKKngF2BoixAyEnnWWM2cle+vxzIK7K/PD4SCpwZxkTbT1uzZ0xs2hTMU0E4o763m9 /+RK4KrNLHS798lMzQS/CDsujYLRZNsoUdfPEORwfH9OSPBgx0EBS+n629w/SXFI5ZB6MHEWCBbv Lq5suE3iCp3Ah7FLz36wnUjZxil8RLexYQXqq2D7KQgwxxAVNcdw7D3gmBczDC6B2dZbdgcoHxTb Y+r4l5k58+yYb83Qx4RKSRq4Ci+Nu9eCj4aJpU0FinjTwZQHitm8pmYN0FyuCHTSVmR4HwNqiR+k W76lYNDuAR6PWW7qb2981nghVVlDC5EFdZ/VUlpAllmjkQ3YqLk7VO1zSmeFRniHWVhBEzE39cjg FG+xKiovhyDJRHiYuOuBq2+jZVLwOxKmJWgRL9IK30XsPjvj1uFdjTbCp6dvDC2eH+qK9N4cp0ZY 3ntSMY68LhwxP0Tw3NDzgC/gyz5FeMlwlzKFCzwoyQsO3oNGuLeemmSjMPqL8KwPmxBR1/MO+nBV S+jq83TctCL8z+9+MzgTQrYIpkRP++h03eI1fxZGrz6ZfljlU/ehMiZYMLGr4GZL4ykJHJaFNxFy UJlRL0p7RQfqsv8hTc8JA7nACL6DbtufvmL1+SFSLc5w0ufnI0Rv+ArslWp1MpERMwtUjdiSfb3b ZE4O9TQAxR3ISuW02GMvxDrdHgk68T8lqosK/k2lUT4sg8XHqV67+0HEPmLyOIpBPgvMdrclcf4w hjv5PLR+PB6egBMbH+CtoP5pH32EWewBTXrR/hbXS01ffrH2JYBk9A0KIZ00ZFvZVitiway1leAf d64p27yG5p2d/ffDQuxs9LC+3lCyNu/k4ez+7Lm90rHq2adIVZeST46zVDVlYlSUzf/GIEvZn17b VHTV2icvM6jze6GN4X4kN1/lu8MZmgeF5cyYAlTXuuGLWF7D9rOLCwNIFbi2l+wYTVe0LEbCHhLE kzDMtoAHQu+jpw+L3xzhVH5rmMbWBrQlhaAUUrfYfmEHkvb6PgcHLjSf04Ozf/FM7ykmgzAMPVD0 QWjiKrTTr7wC52y2XGkM0jeiFvHzWhgg5GAw+IFmxzQcWEBMRPtIfqRdOrErvkmKuTGNTxF9ds+w Obe1bGdPvzappYRpY1AsDWojI+5sitEjlGEPv+M1pm4LROH6aAoDodgaZz9i3hl83pqItQ4c6EW6 QtoccQSTznlfKG8EpkoOP1E9zdPIMMyntVJyFYH3YeSN08BUOJ/ws6WH+lwKnAusrinSmZ+rarga 0Xr7qNpuyhFG6zL2UolVhdxndcfzMQyG5PhK47375WUEXGkffy4B3IBR6Uo27G7f2ju4+TLOun5M TvsdwYaFWNueROxvvYvMTN4mAob+S8Y//xUu8pmVgM89mSB3+TD5DaBfUpJTQcgqJTVwsPiiyWru ZXcP2ADeYwC+UZJ0Dhj9qP1SQFJ/w9FaqBc1nFRTMDqEeUZReTP/amDMqBcY7u08xNwxX4mtKjh0 zOhpNymHJcbfFW9Nzta+HeYKNsBIdQpeHn4ONV2IaDjZhQNDfLARMwFz5FlT/V8aFhaO09JsRTZe tXEF0pj/IF3w2lun6y4IV2APWm59p6Vh0ah8PCwgpcEjMjXl44uvXhMqlJ4yqwwKie/GJD6FCzSt 8W80kWSgkI2ai30j2buRx/AJc//bTi5XLJszLJaYG3H43H3zY7zmYXFW5196Kuhh7dSAolKOwb0s 4KIprk0NSbv5QqGCHwZxu6kTSdAC9zh0mI74A+5bzsKGb6nwyeAypsTmsrsqL6HAnnVn/TCoawmC evnu4mdnrVqpOwPDkNh6nRq1z5sVbfGL24dr3KBc6++lJ/YZsJriaahO0jQN7ne1qB/FDxwUF7MK CBvxxkTBUwweDzZWD88NangnJ7QMe0jHerKiZ0ZSRE/fr6fPeVQI1So2YPDm7fdJWD9iBGe6hrCK 0MloOvH3VOPE8iD0BL9J+GHivvzkBOuaEjdXmD/c+8RUjOdBKpCLeOiWRYwkbRvAh9mmXCkZ2Nix dhXF4TC3EnnOAqR/QCd+/wblJz0eRUCVcHesQn3c6Xn8VqS6efvHxZaDFHIlq0EjxwZnVXu+SA5b vQVWBnkqZf8fgBgsXerSaE/AboW4ASWWPNa1h8lkvgxoiVr96iZ37N6p3ySYfPrWDjnJQkZC/+Ud VCUlKzePB9nlxrwbv5QVbLKN8P4srTPD8qlFRHq9LsPeSBC/7nTtLn3BsthK4UTaajhRJE+L8LK6 wBmyskK0Fh/3IH4XRMnOuczoc0EYm4pJpGvgT03Jp3lRGFKOunY3Jx68V7B09TEc+z0+M/DMhKCa CloG7ej0IOcpPnZe5ggY1rKzI7CFIAJpfeIbKvBfyP3mRnpLeQS/8pe25IJkIH8VXeEEmtUtYB4d SX9TOjUQEB4pg/EcyvBB5ecLyOrKHIdl53Z+7d/r9qXZ2jILlcz1VZTjTv7EG/vSFdwlKYluGh8v VmPV/+1AWGDLkuBoQozdJpa+tV4mERerno2HV907yGYqITQxTbHg6Ur9KYU32TN2vtaDTa+DI4RA ZvXg5e25Drc/QTK0p3y9LJXakLSwzeOtfYYRxRzKzJNgiDBNIMThE22vrfo29pxbCCG+YrbdAR0n CvMSog0BOBiRWEBfyOAC00kp8b1bT9jGk4NpehKY0+rCfMOj3YbmfH2cFJGPbeKrl+F5EiMM42mI WT1xqxkH8UxbOOl5NWzVb2pnl/hiIjLNfWyLrlobj3Dbh6UEBIi7hyvTCMWuUwYOCw7KsRgg5sdb VX3oxX6OTtl+5xc6/ueuow0u3n0onSUZuNaoCzhO2APipqHo9QNhPhzr0Y1mflEsgc8nNsM12gE3 cwIcoK6g2iL+AN21425beDWLx/9OEIa+Sx4ZchhAsfxsL2W2l97YICEIaXme8SQqoo0UY4bdAz50 /T+Cxta2FIJR8KMXcZz9d3dGqSfoanGMs2KcX+j68I3OIufRzbVmcwRNEiAbea0Lmse8ppIK+tzx j71B0tLTK+CHWae7N+xZwvb8DiKahFiw5qOLISRzPr+7+Dpne+hvqveveAM/hSWgU+0k7zvFQ79Z Nhgv7O4gY2CvcXfeNGfMM3YVDkJ3MJM0yLTuHz1sgaeLfDl/MDJTxYKCSufuWwMbLZzpkNLiybX7 7tPExZ6qdavCLfVjRMir3+95gDdZj1GfE4VcVlKQji4u+0XJPJPo4ikE4s2jJPzGCJ6g5B/DS+1e 6GJwIE7M0AeaWlaMbrdm7NSVz53p6XC9LJ9Ivk77K88oMD33SvqS7tchNvubIl51UVO+CeSqzQoD 5MfhKjx+Q/aCKJZbpebbiuFto7DAtxkZlg5CHGGdWEcqOwj9ru/w7ai09F90DWNRqzs8NBS+/3N7 +wqIpgwB23us5Z82GZKFshq613oJoIzH3u0qb7b/V/H7pyWXUjP9MGnAoExe0aW3nzgPIfHlcWug DLPSUE/PitxHh1o9loHeZ5X6Y4B0giEUV0I6UMjzHhA6v5KSNgkxnVv6axngg3aGKx3De48LGJGX ELtML93G5ptrGiaV4l31Bj36Xz3ekPiaJOthcxdUDWNhCfAuGMH3/ERuUz5zd/7aRlQLRBo1bIAG pwbL0/VuMfzKiG186hXRxQ0azUKrxZSAdM1Xs90xgRSM2TA1mYgKpJR22upEtVL2mtKuD6lSttvJ D4jp5SA80BQxtXxi0lEJ1t8/Nvb9H7lBbs1AlXtZe6ZDbE7dl44i7GwndMJQ3ZOHRrjVpvRqPZD4 NjFYzTNe0vihjVi8AP9Wt/ia4K8s5M4VvaTAK2JfRKo8Y9iwxsS9NH+jaTr0RlTyqVHWeRGbNUmD KWlcl8PvpPIcqJHT21KFNTbUecUaaVTWYYK13hqhyeGiqCdvJi3yZG3brBaGKXX2ZGN0r5NgM3+F 0M2RS0ccePP+XiMxlmJvkxKYp+5y0VZQGFVZOlmru3CrP2ExbiFDi6yHvud0PMhVRRwn95MEnVWN Cd0DFtp2+g/L3v95+nS9wZCWwkuJWQxaIORmeeMs7KWRw1ydc1DtDMAY5n4laEipV9OCoyd/v4Vl QoELGAj/htIGIUm3ba6w/EcOM7FGHlmNxDobE02lqRgig4Q/T6c9yvUfCxuQPpAlhiOAbBgNN9qR iHFyC6NuhMqKug5Nx7Gq2/3WW3xeh6ucRJXUZtrlzCEW1x8BwBjhZ4l3cg4BVNTDoc5bPlqCiO7o A2ZHOzGzpyU4wmsveym08s93+H1G/pBN/fLBPUE4WXCNYc1hXGbS+zst+q8QGWOBB1e1M+l+M/ke o7cjfwxplmoFGcu6fyntzvy92Gbn/6LnBncLKDCRunYmpWHPpzQ0AMdqdEbQFhgYrrNkM/d3qvJU CmKRTXvtai/d383z6xOmwpfkaNdntFwPUr1vP4HobGkEUhncDOJFH/K335dRaCT9+QdmYJNT47Kc lciakoGBomBjj7x9N2ikf7d+cKYjgz8Rce/QFo7NBZPJ6QrM66cTs6E0Uy6kaT1bDazvpLz4uSEE RAMZoKvw0pyZByh3QYyg05d45eoKQxwbKExCyYlwzIZuQr3e/aGPfFbjQMWYD5yniS3y7X+ZRsLd X0h2NUCL7Eg7H8nll+/cxir8Rnio6zXxhCOueG7rDPiC2q+QJP2/Z00+kUGohchdXxRPQVjtM33p jAH1L1GSTJKrPp3UrUo5HCxQsSu1C9Ia6FSie/PjDgPmvZVMhn4ieFd/X80AnEZssnNPmqb/qL0u FNAkEgAgY/vbusmSt8lYollMQryI2FUhZHbMr0ZPntaEtZ77iIqcNiYLYxllnoOsIX2qR+3C1JBB MLFb9xIqGceTgTZv2ExVH0vSR1YvqIdgcBwRovlctyILl8gwtdkYlg2jelksgw/YTSdJY3wx1xQo 7Z2iq5qwG0FHY+nsfdDk3jR8BPkkoIjzKKMNG84veiOQCjAbOjxCrgHLJj1fcCocbH52CGcxnaD0 BYqVwH3du/yUHPN2ZBAyGBLBZAPVw24QSgD+r9ciYbRgiOA93GWDphontHRp9F6qVDhsLQv39Vns QIBnnZZKVJB7mKX4jjCCqJBU2ctW/sSZbTlDZDa/qbDslcDV2DujkvUiccdVLDSCO/+osacVzTsb joxmAzdCLdN7J3yj94Hs8JT9c4lyMwFtxbwqreyKJa44XLp7g0K+BSYt5kkJuwgGwZnRl5AnA5xn lE36/eE+EJr9/B8NI6ZyPm767z+s7xN6GT/VPDW2pNDxp/X4CeDEJf5i6f8b5q3ogstviWalAYK2 Wxik5Zxz6lg12ff0ObeD9pa8eauMWTyAWZeUj2yyqgjg6wkOz/WMYqAOSKBGI4Cf22wUzYx2d+Kd jp07vdXKsEI4a9x4B7jDUU6ajz7cGuivnmYOXbvlJ077RKoWwBFJXuZMJy+q6CwR4iFU/h0723W1 /J6LhX2pOcGZUsO9t8lbiMBqhb3lr6a9OjTNPpp5D/zAMORwyjfqQgEfl7BA9NweoxaT5IyRZaZ0 Y5MRAvb8IO85uVcC9dS4/ewngJDzMW8+X3amPaJ6b6RCaEZ8eHaEgjWut4ZrMxEzrVMQM01YO58B IASkWxYPt6Dy7fwzwqzsqUi2MJeKRMwaNLBRRlwHE9YVERA8thzJj4sZh9zJF5snVr9qPZru4Tqc nk39H1FhZOU9Ba0LtmhbU47KWbYA0HPZUkDbEvLafGg6yC0CTbh/7XZBJs+9O/WPJ00MxLSEmaGC xzzt4vvrESg/Bc8Ms3NI9+MlRmOB9hsW0WucjhtSVs0hVMS7Ta0vsvtYx+DgCLBe+RRnOIcJHB9L r5AIMpclRhvGr0rbvKxq8lglScX76A2BKjXl/F8wqD0rg/f/xR7mt4IYie7UZQw6qp5JeZXfzoTX JtYDFQ8tiBeJ89dllHcBSjVuxOBWFfIlJv9cxOkTxQvfqXPJ0Vgu+1YVjya5szMyO+mqlz5rXAtJ WtQh/fc3db8Xu2auA9W6SzFGMFZWrFRxoO16XnMppbxooePaW73lUB0GH4b2jOob3dIyrwz2MiSK vKbk6laxtabVxlH2TQlFgHyGol21mKdzZYHM7bL/yvFaPDkM0Cbu17uj3c8mAMPqPzoIEYk6A0Ja h5rKDw7N1DA6mk2W8uUxnyh86sKatLbBzv6/lG7FDClhdost5bPR8D+pOjOvTtD8UTiLAP9FloCk MHr3v7mmCAUlN9/EQOrb0pZHhRbrO8gVgc7psrMHq2ZdNhHZQXasF9x0qswvUbF4XMPk0YpnAhBD DRil0DtDYjeU490PPw+QKSXw3GCr12MOWKmg39UJHyGyIj5rt54x6Gfo7ar3Qb9t6RlHgB+G0b2x JBoCLZ84Zk+8h2FeQULj6pIbvl61LKm2rukE0qv3u0cyRTUHNNVyuhjFMTtT15fv6ZkPonUdJTfy h/9kr+EbwnEOFkIjOYYMKUWUJz8edfhRihP3/P1Wlry18rBL1/VSELil5z+dnCR234zUmCoDu7rB s3QE2dPQ/WzKfwyuRb6db8VDIPGNeWbdI6RYcSG+Uk5aa8h0bZaowQAz1MglwRN6yHQ9ZwRPZwMP hKkgiAcCprIqjK9bLXIjWlRTvVz2i94mjDaKAvIcGoclfooCvow3oO6gr2QaTVtHnMnlysw0EF1m PL2FyB8ausnjwEz9g2JXIVfpb6tUgiwKZCeLGSK2KQRCMeTSrvA5ce6Ky48cQjDKW/WjUaTZEqaM nmBVYsGWtFkbxcKLbuEfc3GrDzkYlMluWKfWljpX8bRX5sFIIc77gGW3dYYVEdBIo+tZISA4PUnp B8SJ2tMjp7qh4kvhvqRd1Cr/5XOvYfSknJtn9oueBUqHUxdrLz0nGtZ2K4RmJ1xXg+dI2b7k1zHr fzVV5shGPnMhClDnKSz8+V28WhPM+cGhDelbbvM5V2O4+2yLM3nCxa+QoVCUvFttc1/6gNuMJZ2m OT/cepcsOrXX2zc9vVpyM4mk3lfDlEQvdd30eS1Bzau6HwVTuCM6oRZOIzm/usQrSVdxH8OymhIl YavTWQRrqVR+JBkNrVrqbLJ0+HfdlkhVL5lq6gV1Dk+Vc1pKlhaS4Sd9jHYmfuxdlaBnQlz5LWTG TbopGR7HusXG5atOQz80V20qRN0A5Jqds+DnGuBIdKS02JqSOc2VmboL+lcRKjDDSoyIPxEoAmUJ oLYBbiJW/WopLJQYoqc8NVhbEFb+25Px/rc7T+L3uHUbxVaMvdiP2viwHnzuoZXmI7R9w0nS3TlJ U7cFNZdWT3MCe7EfB0BTKA6356DuMVtix2MM42/7cuh6nMOezjBDx6SBCT4zNr0SfOBRJmrcr6rL QX6sVoP5I0MHjk9ov65PrPd0TKizEkv1A4/rxg6pf9vU7GMk1YwdQmzoHgVYnyVA5iQcE+tjuK/g UGwQmX/x9Z7rKv1D59kZNQ/lkemqwyduHnAVinOGsJfLDrptZTpoTWnzQNNhbGbKEGhrjDk6/OZz kkhG1aGSEwt/cCpVee8ertyKmeeWdddrISln67Gn9n2vBNjD402Q3zeS1OkZBkUZYwv6jP2kJRHM o/Qwuz5auz3UJBCpD3ajVOW46UaEXMpcO4O3D6i1LagIqA61+4ja6jlbkLq5z9msWAm79twFVi+n r1RHGVlyrGVmIiWW/m3oLyIkF7pO+9n48TidsZOQ8e+GtwOfxd4C0kYexFJ0B5mzaQ1grs3Xw/Hu GGDd3ecIZ+Jxug97YgYez0YZEQSXj67Uw3QugRQKWdTSKZz+Ce7R5epUfZ7Uul1XdYHwjWJq/RNR VHDB+YVTetkIiYvqXmHj6bErSB0mEXL94iZqI1jr0LZpTnNrlPLLU9L5sdQ1JRWjmIwM0wExOe+l lu0Oeq9q0dd5AfgHg3Us1S6s6kuVYrl1jFL8upFMEZjeY+9/BCeUKpaiqSlct/0zlShRLoq6iBUm B2CALx8lCtl45YdZVyXKwrqlnmuIU1Xc4yeTpRUGhx2yVtRnIvg390Gv3/n8lmSLoZ1KUKFohJkn Mjid81zcQEfF41auVv9++r8X+0+3OSYmTe3QaJ/7XdhPWhid+PPWqmlWFN5Q5Yju0jr3ZYN3cr5m VUkpJuI5ISx6yl+FXimZRdGJz4vjMrYhvRKeGS1kbnUyVecb3dnW1+2AAw9un4eihxezAt45mBWP 2NrTXjQdRwJ/kX50FlhwPZ9QHqqeVwwL+gMUO5a5GafcbFIFkVjTkq0zH0g/RBsFQdz2Z73R/5F6 invbbWU1Y5RgQeJTOB9D1f67syUWwDtld5xuQYD5DdSM/kdJyreC+x1aE75RWH3YS0y/Fm6yqghr AZoWIRiSs84lukirum9K+RctMvcSvBjVn5RG6UbOi7ht/6YnDdIKQ9vLUD6os20PQtYhQLmgyP64 hW/oPGkCodJ0joGN934rYc7OauhGYKW3ZyJHUVuY3pJhPJkzF00RjE/EJDxZYCzjW9HrGDYc+Gta fhaXzsjjMruzbyTyeml88sXYEHfrMSQGNbC3pp/8s5l24BCzkXzR4MClBDtxwj1rgUb8SurknoR8 6xhm8lXZa7cRP8wFHbV9dGkg49GLzVCYk6LEvGABZrNB/BBgeI5HTzNjK9tgcau6a56EjCjB4MRl atBWE1vLAlF6xVFR9ddPfyVoRDJHHQRgCkRSyhlUoDJN7McqF2Ufa85UZAMA9KtsGiRuZWIUMUO8 XVjYmuHlELkdcx5mM2NVZ/ayanxTRmvK9rsyCIdZvi26pB/0swNkX14PQPYRYlwYb6ziXdZYGFiG bNVwy8G/KKaGAYEbMfRSjsQROYjel0O411Zw3aiGSKEztYeur4mEyn2P9ZbQkzSo40UzrDJu6jQK 1ySmfh1xM7BmpnwH0Vv00iqtE5mXkQgjy4zMbDtwKjlnskg9knx2pJNVJjQ1G5SqARUvG8NpY53M HMw4E+Tmmd14AlczAvfbilkn9u+AlXQpu+wAH8SFETZnVYw/LDNIv+dl0hp+L7gqZjPYIpxCV/48 FIX5aiZx2GcFhFD2m++0lFekh6ehLApyfu3aGF1e/czFYI2wzHXbMUgsZ0bRBW2jYBnO61rlRpcd wENXos4HgjwOGnhX24vw/7GEWpUao/ekos5KrVArpDJoh/UgYCBMdmLuI+Cy7XAO36RQPa7bR+GB WPf5F09I2dt9PxWxCSYrKtUYKMA1r0R/pbsFsWoMf0IP+OgsWEZbJJyriuBRlAbg/a/4xGdvNER1 z0JLBOZeAhVL6IHoyfN/Sm9/L+eeJud23ro19ShcsGtVf6Wg/61RBEFEtU+o0CePV2MlpB254z2G JpRtJDeMSfVhqxoYsIFtnTK34fTmEKjF7kUb7Lx+eAmmxNctKw7WUvl/U0uzeMwVVh8fL4EH1VN8 0O1M79uLFprNbtkFdZIooy9QmEeqUtjdoqLNdvlBTQzRhkTRXLZ+sV90Twh53eHsJsL3YVSH6PjC 9PIyZfHsoJh3n9sPhxAnw1cvUFNThhQMcQ7Nm/b1a4lKgX0iJtCEc6QAEU8h7dVO58ekGhC0i6jn 8doTIGkiggBry7VepQ6MLx5MBWpsbTWd4DBUAMlZvdyGJOsqSdpiCjNtcgbCeSf92CO+3RrrUVh9 Z2Avhq5ydhavIa+37rWTDogw3M3fcoYZv8lIqJ8uXKz4DfxC4pJ/ddpkPYtor3BX3GUq0gkN9Bpg uXI1TGy5XgG8rY6u0HrJiJ8Ni8f2qVc= `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 12608) `protect data_block XBRNufbYAgpCrjGiLzjSn3qZB9K7K8KVZDdjW/YXrmm1iB2BWmUw/4Oy3BzBUilWNMDznYPLRkaw oEr6tmVy1YkC6gsIB9hnBgX+QWJcaDqpYqzlJJZl7tP7BfJ+8/g85/10/4mvdIJ91EJwSY910quY ONiF92uPkbtsKvTeo+CptGVM+MO3Muj2rFFt4inhrM6dx/svNhAlIajJwAmce983X6Y9GJWUeMZF 44j4ex1j1rcIQhVk2B+dJeiWGeZH0lglW7alrRohATJw5hzGwjJhE7sQ9iXRcVsS8Lonrv22kFW5 KWfYsdTuXQseKiGgXaBWGv+C3c9qcUiYWAU3y5g1UpkF9nF4Wet32sKxrBR2PZXzWDIvJY/9+Dsp d2fKcduDcybSxqOavrdbsv1fPfpvun4fGqMzuePAk74iDBjxD1u9V2bSPYPrVm/ciDyOR2eNS5yk oqY6jroFWdlrWfBHuj0gVRrZyrsHnngOijqc3f5Wx+muvzpYlXuU4XH5izX3x3knewS422fhZJIb kijwstBX39pO2j8AsI4UIp1QfSo1miwNUFPgkn07it+M2/f9cuuQyLrnRs4igyki4Mrcw70vune4 0pjR0F8ZQ+EWATBtMCxWv3PUi0qssVZV9+rR4lvWj+34VtahpdsCpELnsy5BtNWK9ilz/oRLsWWx eIoa722J0p3d/+ok7iaSWEL3QWbTHPTJOiJXNe2sbJj9bBlgKhHwZbpwFUxkAecVDLyRlU7rGzAY gqv42wbf+WNqMjh/Ab0jnZrGNt3EqeyX3sDYe5QnEPpnvjrOcjEK7mbDDt1Cd7OPWtfdwaSH2gYL P7vsQ4Sylfqn8pFmXltbfUIZ2B7ak4Q/tHi+vxWjrNLT/aoiZBpR+y31Cm4YyAUTTBBUL97fxtuH JgUXYUkcZHkXL1KpAGfU+kEk5sGW+RmU6gRYxR+Csp9UaWNzpP8O/N91j8VgXKPnTolLEbJ2EI8E neXLm2JAXvqwebnURINR3c3RJJ1epxChhcW4+WH6b7qhUAevXI7Wg6u2N0RQAlIvVam/exbnoukr 0NSWjslZ88K4IuxDyB9MWZ/6rfJLPFHOvYh0bPXLYzN+yzlmxSXVg47SLeyPNXHJsdBvW4mE7FFZ SxNoNKRf0cczKydgxwZwxB2gsqv9/QK3tDNt6yw/ohEGbPmeT8EFRfiaAdb2cVBqgo+qSogVmgH1 6JtJDFnqnnf/0rpsRzZXAlQ1Pne+6Xt5G806BV7Xx1TOLG8WArqEq0XJzJgOsjUiNaBtWKCyf7iQ IgtJYQL8PfmQ6ge2Ez/cCDg/r9kc/fp24EamVxmGId/9TT32xAjX+RykGNBpNg2oQcMpUaK0ZsB6 PfqbVTQ9p1dc04IypIDrzZV8FWa78sMfZoXcjFHS/MC66d7LOi6+m5COHkI8Q83bvjX7cB2ib4wN IO+hdPKjcqbV0UBAjuyFBCpQbdRjJf8keknUOBSmW0kPB+oU4DKbKwGnV+jJFdd4tLD4Oq+2lhuN YqCb2zVQZrs6nDPp95R47NfOR5Ar2jnXP6hGSrfmQG70VS+IEbVcv5lz7zwagSzhVXfzatxKr07K q85aaIrOjHd4pjbvJC30Ftqkw+phEhJODEojy621ifeeaDFeiwp+psiUURnoATefqQM7b6k4k6V1 MXnvSQS68tZSwtV3jCclNul0iAHVUCiZgCpVj2iB9uH73OVgtMAa9NgSJk17AML+uUwcERe2vflZ SetjpyvowuWTUe6aNG0GpX52nqMA4WYEOc+GZuClmWCqcVh/BZ9+dMy43iiULxPZNJK7GNiBkJe5 XQGdHK4cUkirMCi3ynkOzCDy3ZUmNQaAWto6i+PKMyPzwlnZ9CAGA3NacRj61VgGDT90Mdn/a0lC D2zMOrD083IEMW3NokdddA4LahOjpbEK8eDLLNtbaH4nQ40yGMMTkvx9jzoKoYObkHRf2JZ8Adh/ 2q42Lo1xtLu00oWDoWJIXW1CmgT5M1SX1vQ3rMAWVPWG2VyTn3DvTZuFLObZnZnPchFj3fuYPCCj IDbSlql3fGG4Dy8xCDN3rvc72DQouRtqY5+cu8TENZYv3mh99MWnio34QFTVIRfN55Tbz2ieDe23 xAlJHtCoxsHEjb7aH0ywX+44IWmlCgWRjbY/60cLzuFPckGH7FHA8M9CBvERMewZCfK2pS0EJ6Gj 8FGneb91BQb8cOggrVFddCewzqhVOE7CXTsaRsfBhNpHlvVPnL4rmdSWp1p3seUBvh9zAmd/2iXz Go4XgrMefmuYifZSkfQAO7TkZmyub7GhoKVWrosha0SQ77+I0AIqD54X75063vpWFTOXjAvPEa/9 WwsZESe5Peb8TFy2v43uGN8gDWAQKa56zwXckynSKSXFn8yYuzlWMyDVHCp1MLrg17bj4rZoDRuO mLukemjOSS28XLHUv8OzMbcy8j5tbjsHs6sp4mwaA5hH8o3iYwWQ3HHwr7qwpOQT6d/m921LUASz 8C5Uxf4zB7ajYcZhwgqYemaa7b159CvMRisqggtw6f+4REpTaNnmei3456M8iQI728MePyY+FURx 9klwacBIhMULNka8HagIBcb0wxeXAQV06BKs8/yU53Tn30KbPlTMQ0MFBAFuGmCI0xDZEwZ3jYLh IWgcCojP9rYtGSI7jQMH5aINVoUE00IVdyd7v/2DJ0UI9fyTll2mZp0wvfzgZ70qvScRXSmvYIJm eeadqr5zZxRvNfZWaLCGuW+QM1dLHYX3FGQENKse1i/8f90dug6Sc6L8x65+ojB/pYGpTqjOxkxF rUYNFtO86peh3yo/3kOpAc953asSV4hOZQwo37xz4OWZrgKwom+9wUkWNhIG9nhBQoX4Pwou/CRk lqHTu0NglIhitZ4pWy7qO60HOaoprsUm/3qtmF0Tk5xvD4XTTvw0ilH1vq0j20Hx0Z4/X+es84Ga uET348O6hoFFAaMHD3tcqJG6PybjnoRlkpZPFYfukWUpgU3J8SdESsSc1ZAaqxG2JSJ/5OqnV1BD 0rU0cJm4P3bPH554Ki1DijDtJYZnvYIyViVL1DezG68/cniN32N0v1bYn8MwmJNbxcoloiQb09sb JMWTamKt0LhrFdpXDyALJyFdnQaAjKO5VwmlpjYUVSzdA4bS95/uar+aDfMXHXRchR0jM+PX6obn YyaTpJrd8qGBn0wiDOt084ELnuCYVWUhiB5fgkAT9b+K+smFs38EcB6QY1fDLdaufL5ghMuUr8gs ATLzyc2SEjVDmrPoId6xhwKm2OezApUO1+wm1wgzjIbtMj3KDiFctcE0yNuz3fvmIc77lrz3KI3M 3IQyNn3+uJ8ew50fvYPTec2pxzjT1GtovV+VQhnXnLyBOWINtmLzAgxqcqd1nVhP1xTr0XBpV69G 9UJD2bVan+Nr9K0OHkoQGtxg4BxtWMbh+JCmVIl3tMNzQN9mX+SRaWPiRfC4oiadYiHk0K1kKiZq CoB2AijR1lGfOAe2OIB12tGvmPyZF63Fs2lQrsBoi0ItNAvHFHTJ4zpNhRzDPmiIo4dsJRrega41 td9pS/hwY8WrBneBuOPMPY9LCv6rGr5kc7xJRuhOZWOiJNWNGdWcWQm05QP/wpE1GtUfuWXsRIWN XImnhGgLnMlO54t2dogGxrsVBj097xlpMNQBYIEG9a5yECTIax/1H63zIzSU5SOUNmvU7EbW0skR 8NVuUlXkMtkuL92bZzSqr3KCnRHqyDAkJAgDGCQyEE6G/C36lP7y7JKS8oWrPAw5U4Ny8rx6xkXJ SNY1N0vxCAfLF2wCFdDlbb00Szbi8Asi9w4OOQXvq0ZA2LazGi5/PvBTTCS8ImNEZTNvbGAjm+G5 +ikZcx177HkT4+GwSAt1tC19eWpgHbbnqLfZFXw5NI7o4uxZ3GLAhUAWbUEcG6OIrt5J24BsTusF WZNNNnwBqXlEL8N1Pw2FBQfOQLQqICkqMXBr/FQbjWudTMis/4/jkjGYOvv7Z1VJdGmgtiUNCFEy FTWS/8zI4c/ON3JzNhB8Lj9rzHf2WF6hXyFpTBZUkOkD4LLaz3ziEpOi3k76c4JK/rT6X2Mc6nAH m4g85oDgg56hq4FQCydAcExfLVhkBqTiL3RRCVKPB8JuXUZOzv6wsMQZgNWqXontlPiX1VwbDTcu K53bymM37Nc2Oe4aIpAcRqUUpVckbDEcq4tmP93k48Am8PCKZN9e7TNmHM5xCGo1q969Qd5JpN6/ SCFkhwbaexd3abPHiykoJ+BkQdvoqDM4PmpQxNG8kNTTfFuTIybR+kpB6uxrBj0pr3InXXOPv4l6 Lzkjec0moNCv3mDBXsU6NjEnyIAZf8IOLrxzoqujsG5TpOcZWCjDbOk3XjFSc6dZykZtk9sqdZrA 8otNiAQZP+cFMS3NDEx1VVVQ1kXqgksam26wI2PjeR+X9kmBtd+pJkqkbQ9879dvCUZSnTRV8ok1 h90Zc/CRadecri0vMcd4eHatbtaa4gUemNdV7qImfL52bqACEmIS1uDGxlBz78G5hQ3P3sY2LG4L rzB9qumMSYZargwKk7fQsq9GZ02/JjzGwlanc/oMHOkL4LsZJ3hgJJKSLeZk8RYu+sbnX4m6CS+H vVwOmlwq4eE/MNdzrGXVi+RQ8W4wDUw3kaojfwU0E/bhAjKwOYMw2SWDJLUKYlpE2TazMUGSL5el GA9mByuzli/d0ab7AFErAjrsD8MKRCLJiYTXPl+sVJmY1i6bAoMBzqbPur1FBWs7aPP7aai+I81N P2XktltDCxVCkOBwUeM8Nce4TgPcpOZ3yMSOJB7hR7Br3IAfzad5y7CIuw0NHecdm+0C52Of+Zeo BESgWxLnkICgB91Pr3hlpiP1FZgv/69KWJyhnsxK4HTbQhUZIjkkqI234imeHglIh394aOzjCBSQ 1DgGkE8ep+dI6VQ8X64yyp8foEd8/uwkrBne7kc6llbQX4IktOAGzAGDt7Kah6F7dtWNsPHPIBon HWKwl+bEvLW1UC9rytTEo9gCdDy/W7hWLconk3l8mRMhNP2fCmGtcB127npQUfSZ5Q6ErDUYHCGC 481qMeNmnp0cLf+rQsPA2lhfjz43SiR4zp2aQDbO2XpqXq7SBWebJGb0Z0p+FR2kv0uXwSreOcHP zjc4mFaQN5YEdZTUfr7ytt0WZalMQmGcKoL40enSpAP01Lw2LyDAfTWoydHyf5KMAa1qFSM2AEV1 /Xt8/BxjML0PK1LFnaOPToZGRnxOXh6Bxfb9bOnWEJ6aCuCzH87giU5vNq1vzCJ4DHM0rV+vgKS0 bLV9sXwAdUoNoa+mDb14+LGV3l8mAg+MImWSwFL6odmTx4iis9OakwDa7j9anyZDLbAS17nfj78O ZNsqzeGPXnpp2Wey9ge/fcritKQrOL/CPnwHBPksvZxo2jKXhgRXRRDpWihct5uCoqIcx1NxhmV+ WT/PUsJOjLyubf5lB030WkdYGGO92wtpF3KibDWbzBTh4DR/5EMiPZHZzrFFArcYBWfjTS0ftU0V z3hHv3hmzupuKhb0RuOx36mxyfLN8Q0FMUD3loi86rx1MVLUDrQsNEC+Wa6h5nzqwWVyWHDGrLAP 989DmtqHY5BmV4SWQqSlwqZgkNr5E5ClbHVGooBlfdKZTPFfpUZXpKVMGoTC71YU7mTE2Wbtf+vB dBcvQY6i0Em//xWwJxqkQDOeDD23X/kJmmQ0nNHKz0oMjsnw2/9llgAhPudUksbRqplFprkZDQUq ytrPa/1SfJN3+daEh4xmZhuGt+lRdliRk4uxPLq3FZDQnfHfMUI9orQBW1Tz9sKLh5IkF3waRfpO 3z7a7KRUOhmLZAp6epBNfX0mo5kfDJl5VvzA5AYNbFeywnkWSDg5TD5f1acMD9h/fGMt8Rrj+5gn yTxYdhTKV+EXqKiEI2Kv4r0sXvtQkRYg7Kr8ypwXqgY46BwoXVSff8DdgeYEKsBFbKhl6mGTLle1 NF4LDdasUNdjtyfpMzRZpQb6FhYxAdUZ8RLACrdMLOsXFsTe8ye5raG8CNCfLezQveWrLk8AOfmk WIQW47rxG8oid9TLUGC4ea2aFx0i9vodtOUag9skLdUdQLpIG/oyz2Ev8PXCcgtl5ppRRhMR4Ewj h9KIa/rqlo6vNvZ5QsQr79QpOKelNku+/S4+ZjWGT4etZEMYzEpLxSmv/1wmvzKjdW6AsYjHsh5y DUd23gAIZfEfpAucUpBSRd7t4U5qE5Hz90XPYd5ubDEKlmZcoaxR21+obCA1fCRWQ84Q2t5YnNbT N6AWa/gOnRnP8LnTH8WGGqAZ5GzBgcc6JYsYSDAK9Qlwh86BKFFBgv70touS7E0SDbvl7w/iR0Ns VjOnsxIkx+QqivC4moDJR6X2BFlJM3HzxSeNH+JAnkmBYlA0kkJuREFUBeoiEunNypyU2ZpPHg9W Skbvh8rgHDCuixCtmh7FXQaCFuBBih6Rwi00qGjNOJ7nSDKvIv4HiJvR6tLmNX+QK3d5/m30KdBW hqAbxWQa/0tjtdryT5kI8pCvhkeS74r74DusHTQWf6TZ5GNWniJxRREJ8tdxpEMwyVdYOsw8Zz+4 e6I0UI/BxhRoGT22HnCjEJWTl17B7qsVkpQHCKfinRYh2GH44ID0AlwciYHrbshAOtUntx6MC8a7 +hVqFfJyv3RP+X9c0o5gOY20iCEevEIC2bBkGhW3YPZTWM1gUMqPBciOnjbsJmPqrxCgngmfvtfQ BvQKVnhqMNzSKu89KczTyytyK4yCnG6lvAcIQckgiitJQt502bFqJ1z4kwKskp2gL1J8U/5r5vuH 5CZqS3OkivbEJb5yBPgh1dOuLARCWlw6JVRvU7EKB/6+ChgxBdm/TV6xIO64m40U0ITvJ4kxNLhB HsV1Y1qoze4nwiy09QrbLHBTwe8Zgwp/TC4vFKrXPA3zzYSM3xEXei3xKDuvFhXyBUVxcZrQY1ql fM/wGuAzu33Xca3T7aPprHfpNzJgI+LUrGVOIlxpnzWoMxS6Z3BAYkxaiBklTJDFpgdvB/vTt8X6 k4fdZrT1EsRx0W+zRKYooxybv55fRL/ugGRjKt0VXIgLZclX+AltA8Hw97HecX6FjimtwBXqM5nq Gmd/DwUwb3jn0HaiQDzu6bKhXBmKdS6gwtatxwMAVn2RlgXSQICyWEFZmEjeouloy41qO3H10mEp lt24eUxCyguA8g5TQLiH4ZMr8NYCUD24Knjm4yz2VUdD20tm1ogieHc2poH1qt35knY+SPamR7D8 wgjs/jG6z+CkoG0cCbjTVKBUUlCcXs4I15Wp1mb7NVYSFAlhb+WusEjDO09rndH5w1ITqsacRkvV +X3RlnMUEG13aFUzFHXiUIFUCMkasHGTxrxdqBHoC0IQGVk0spfJAJpJ8f8cCBfWE88BdtewAI1c dNfzJrqFS5t3Lx/cH502S8EBeYSft7xVlLs4Pj9GhyBlnzRN6RXo90zTfBA1NFaP98jiPiXfcmXL 9wgFVL108t8lh/qmaQNrhF45wgr5SK/2l053aZDhGAXwZxE8AVw+MQRzBuUDvc/NNC2BdF5X6nwG 8tXGmCe0C5IPBH4pc8dVP9s6rb6WytNQGQXQUAfRWimTMWyeoZp0nm7vaLY5lOi7GQzEVSX1z/Q4 tq5mwrkTPRxybAXSQ/3Pl5NCXsCCp69rbPd+sLCIAgfn3sybblWp7OCEWUxdtkcXBdAy9JakR5Jc oX3OYT57DeHfN8bvW1BcIyAiVhDuMi0lMsZeZfsLXurECPQk05lKHR8I05KYbOMrad6QB23WtX3g c6LMB3a+RJeJn8sTlO9yOX+qIXnTObrlrsc4CZvmJC1+CtADuoGZNvbeKsrqekkyzg6RYZKUbdR3 Tj/+CViAjQMkyWnlJG71o8lJyt/aAz2cwXdXU9m1INjqCpKf/rWSpyUNxRu4NXWa4FvFx1ixBQZF B0FUDd0ACFTTpQPQqIBAmphlIkWCJjOaZbJUZvUcqcHQrzoFdv5RlIUff4Fg7PR6ZIQWczHWFB8n P7LwGR0bT7aRLFmtCzEo9doeEFtBP2WwUAnHJPpMbBYH+KagXGkhjIzrnfKj4Qo8NGPSXQwxqZkb eJ3n/lq+iS/nHve6Rh2QhEUcJXMp1AeJlyi+81R9JV9nf5SDMq21zlUdn3qMqGDz1HqVUk186uhq iDt/wkM7zNKUOwEYjQjTRc03WyfAFiL+NlL1LlyLGl04gvumN0Z+sfsD94pyTqSMRBM6yzhjRCa5 oyXr+Mm6OsiZ/LPVkZsKqYmYKbJUHTPLsHnK76oCnrNs2vYMxAxeOj5ls/ZLkurYC1GpvQ2SD17Q k/Yre5AnB7obUzaGhi1ugGhREJTB301bPanugeWv6/WWY5lswXmoRhmUCKuMLkG7+a/te0Nz5eMC nAtEEav8kvOkS8oLbBK2QTjKBCS2xutMbV7pnXhf4Oxn3kujBMF4K9N/ixhZ/CJYDw6M+TqYuLRx 8K6xwlI4Ein1oODwN2eM4D67YLkV6hZVdACUsP83s2o8RM4lCPAzUHay45V2IShNyF8ku0oxCAOk t8rQFKLYvAh7+CoQ/XSfCfO9FsFjQc3X6u/50fnwhB473+550WuYymwswocyj6fOcoXD1fMBjkzS stmlko3T4lvNS4xlQlKJg+jMb72+IA0C/k8kSKNZPU7Y/5DP4ErVMn6Zgvm2ixCJt2FAHsujuZQX G5Mtpu4qRdY6lhliVXDSN22rDGdV+/faCUlMzfksMepyxi6ckgnVcnvJLdnKMdDMj18y3Tud1lIf P+zBE3rWq26hx+7BVimgVgIVFq4fbp/upW9H8SjGV5WAVcE4HVt43r4NK9UGFVBUETpgHTNLj6lZ Jn5iWccsi1lgID4oubVQqcKJJYLEhecDIjOJtL6eeJvmwkSTjN9DeY+E+MizzOtCN9wmfNPyP2NQ GFL0yOVqBjq6r1gM+HnKkyvUMBY0M1X2UGcAHRdfAoSI8qG1Nf4a9oW64tLqnt1gFW/jhQyuERGc w2lKpIUYW++Efz4uD3kegpT3+4HM/M6TbDj2OOhTntKpjcZ/041FLNVCNWsDzPKuUkrki189LRo1 kJBPweHEdpobXOfbxb3GvXExdp76nfNZizrXMF8sVGOqaEM9EYMpNZLIGtVZGtcTFpxQjPXrgSxy XpatC7po4JzS2k/MLG7uArFbTnxGxQH67yGVfHTviOUqaUDbByiZ1DS49Fj/O6IBYeILaJpT6iux NEd944t5ZiF/9NlYS2mmkG0GdjcpxuoW3OxGjwlAdNAaC2sR7lYA6D+kMabqvkHtw7VdIN7CtW1F hAVjENprIW1pnriQhqgtgpOvkS8DFx6bB23nSB2nz9Y9uEJxdw4ETht9dLjXZTFfEntaCGy5v7fm d8Puqi/HFfbSQkSmypxR4x3UvQqDZzu49L8EgRdD+SSn8/4iAexvFKV8uuadB5rDJBkKTb6Etbvr tKvToma5l8yryBircRJdcYw0d8L1ebw+JGgSmApVS/hL4Eh6J71GcaTrv75B8rCfBDO4kn6081AH VudRX/r8mz1TmGR5iwtY6DpzVvZfOQrm6etJIWWLcgL3nTCOSLba5ojUQqAj4tdywt++GSbh3SU/ AR49jUf80ZTN8PA0ySmFeM7UZPNtXJDFsVn0dDgH7aJZKSWgM+fzAH2qOsBuw8urhDebX03kbShN wmC7Pic3MbKU26e9kBgSQPUbmanrCpQf60jzSVP6pP06I489ngDQ12LFZaRMoy8gEmJtE/njTBmS bwBoY14NnttscfQOZRQcvoKX9Og10XwR8Mu3Iq7oB3rlQ+OEkIqHvVKVBKLdvNBFCWN+NUvW1J4Q KARGN9XUREcXrY6sT8Aqq+TNJMfvRbilHybHBkHXU/c+CEpsIdWmx0r5/mJs4QBH6IR/LU/mcHp6 BVJRtq8+/7ZLkizhUEE0zscYRI8qkXZzKyfKBVuZe+jxelGriLOHoR5/XsNS0wh4C8UF09Qs43+N 4paDESDmiGrIj004GosHtUWjXkhHSmtngQZrlaq0Q92PQDyJavUWgte+lmuT5YRqNkxadtEZoAm7 I49DMUeXNUPd7B47zFsJk3rrebrnLVDwW2cHcwIqW9Hkglkb+fX+j/XGOCwjEzTCOzHV02rZFYoI e09rdC4yDupXW0/LdfevCvHXcWhOCCwtY8IZ3ia9XN9r09b/EAGEC9N7RuOICGg1ZaHtqHgH9pzr X/KCXDrPY2NsaEZgXyqcFOxWHF1+W9MDn4UMW7mZ4PfNHQyjujndgrH6sxxVugVEPoEr+miPLqqh mJxLCEHhcUUlL4kN2pswE7Y1q68hd8QEygbNJ7abfkOP9nmAHkPGkGkFzaBWBuk6/JEtQu63k+s3 27BaiAeoBJdv79cpvHnp83xOCgp+c9bYxAKVqsHf6pbFJng1OCPXC5CUvbFM8Tkjnu3ytesX7nAX nCqSiCGCGl76JtYj6QgzdIMPAla5hOafiLPJ5BmMS8jlN3UAzDvr1e4hjiOoy4sxulhIoYQ+d1Fa 2D6FNxHULI4kznKOK1kUZJMJPRNlG9kvEA0v+l3/gVnVIQvybIIBYjrwocROW7yokEFjScE9kcsE q/GPXYhxG/Y0EQ2EHFNclX/gLGycELbmYrTPsnAVe4eKdbpkGrudkxENu4OZeCELpf7RUuf7o1lT DO0cKjDcQyPWk79jy5IztOCMu4marGwR1IEioQb9561TKJjKf6Ee8kKx+VGjaAMu+dDqqNTtvion 9XxR3TEoixY5hxh3OLDGHG4aXL1dhzsc7msATaZNyOHj+XlAfIXuSmhU8HYGLkjL2YFgyqTCHivf fnsWKbdYbwuIlv6xnsmpVjjSWKFjsCjcXJEtEEKt/EZKsZ0TM9WbhzlPjjpKHWpLD39Xv7/lS+RT TDapugWN7gYo9xj1D8CgmAFEX4KzptxAniBMk3Vr5/8vVypQAnEe/tbwFlNkHbccaL7Te6LaavfW KgZMd3tdJUf6hFUBLPwVOpeDEYMFfpviQZc7XnYMNEJUVSWLkBHxOOynLgt9b7AzAhE9h6+KWbLn QkZ7Xxvy3bWDLiz4QXlt8slmdJo3bUpvypUwfhMS4/OeMGptFZ9AtIXYStB+El2dc2DFDEKJSQYl I8ayLkSQHymCzaPeebzOev0p0V70kuMbTkJv3mT9LlIgVzUSp5VKxsle+SHYqGj2UiAJxV9uaajF 0RhSQSJXJTuctKZEFSHKtwp/m5DOjXQtGwMxqn5UZRG9dQHWSO6+dgZHA7F9cNfHI9+4q2LLJJWH C45htygk4Aqms9ypMGp/fW5pmOmXJfpVmXPSCwCnQeRHinMAj3UYUfEPTN0u5OsBlPVhXoySsI74 5QPUcSJ+l2u6S7q87LQdgCFZcI7Rx+34VHd7BE4gJe4GD7ARuL8Cy2qhsFqiwAN83U8EVVnnm7Cd FDXsZeGVMhzJLBjp6Uw6tZHGdcVJUW/1Y/3vTezDQFZmCTNRQ1KTNZnKdyCcSUpzN7Rr3jcu4Aav ow863KuCiR0LDNxklvNL03XmUDPPBudnytGfVBsXRGHFSdLvCTGdho4S/CZZAamni+RlP7383e66 npmdVTx1oF8ZbFtbdU/IsoowJAF5yYthOIqtScpqoWYtmSFEsd3OkaL/WMaurOibzPzcKuuZC5vY XHE1mXXQ0nw2UjetsfKZtXDhayN5j1O+ejLDc9elX3AlYXaNHoZIV1iCO1uKj6eDelMZUUF1kkBb TACOik+FXK6K2Fexn8GCEYzLC79xpAsw+ody3SLvcucq2IbfcnlL85eTFVqf5TgGzsmdED44Ivlp NzkNWH6QZaR877jnqRRMQTeC4+/uvY2f3DAt1/IM8K6tiLL3YhNqS1MYs8U38oXjDp494G31PgLI 22rUEhWyHPMpLgGJSnWrLFQylgacqYZGFbgjBvdOsq33hzegW3Tw7F/A39NtKjTRiBqgxWo9mMV3 L+S+Fwuc5zM8gru4XfmU1Gg355WlGSILMi3u59sQDKxYUs9bTiazWxAZ02Mh0v/VZSGhSaF0dZXm EAOPtnxDHYO+li4QCLoh1arrXChUW0deF7xi++Il5MIAYVZzMv+EA2kyCrc2/jEagE3dZodSkphJ OyaHOXRAQsLt4ge+VDSodIHakp9cpdiUu/k9WjU2PVkII5V/0akWNMKE66lEKW80qs7FcqZ+C/z1 h2HzVnTfJiK0OTXCeywZRMCmjG2JFeGBnBfO0KDBchyMv44hjtu0n9Tnd49vyrB4nRVJygfLIfX+ VNvCKugR1haK7VHG7YP6pcVWSrjkqUrpFrI2LAhjeRnhWKuNFQnZKUzHGFYICls83txpZvJfQO70 EaM8r5IJJLRD1Xv9ThOyjH0BYJkVwFSallHTnHOES34I541YlM8a2JkFPsgrgPdsQ/oCm/V4ATxY bWuIMCgorozdncw9DpzjrmQ1IS8fzLzV9Jy8CUIKKAsLT1Q7Wr9pRgft6cPyM/18mPlGrZkXrgv6 zllzg75KOIWUqPg5wm4myYU+eDFPS7mquZ57mp3LYqUxuE+hTHXFbGdF0PEB9U0OfiRCROubcTAi QIKx9UgaS2/3CNoqlw9a/2XkkJVu13c/jiUhUCkZ/a2/+62F/YkpUHzs1+hMKknoatBidrNPYn+A aZWiPmAp4uNh2f/pXAUNvhvOn2XuPBJjPsfiKcQwgOoJnEY3MLXUA3vXTSP2dBzWv2EvT9b6+jcv eyh4BkdUksxi6jRGnpn2pFXeFHsvQbgGW3hbDaC2OjDHR8hG7BNJDlcEvn5i2toDdPGYDxE0K4Qe kNWzFOzsaobo18SLcp69JnVuWJNXJbpjAyf6PDtfBOeZ3f1X0zTHBbqAufVC2iHLYWx7e21WEAMp jga+uSdEPH93kgQ1VUa2uAFTjv/qDdH+rPq5zu+PwPSqmtrwMuuQ9XAcN660GR8vzoTwnsanuHHs sS1uy5E+7Bx82/9T7YYG19KDsyCOfBpirwXXVY7hPC+shhOVHYCRvwT3qFn1Lp52lNkXz/ZX0nd6 4cnHSxLDtuzB/LVIVc2y2/KAAN1SbUUuwovmBV2DzP6Hgi0p9MhDkS/60YnPYpGiQEmnVBJER9Dw csrVEdShEgdHgnPEwuBPyrLYhOjhqXcJxnXvJJoNhq6GKs3zJdYBHkV1eeONgY3S6brDsps9hHz5 WOYJcIqOoYabRBVGkiSLUFk2QxMvulPqq0MLzsBSV/0KZFvDn0fo4NKck/CMhFCr3SaRVwAnyzIA IWOjM4omaCXFNymHxHoS/MKePdxOXWApNPd/7Qq0I58Ax62yHxiV2n/dt2+QjYi5nV6YB/C/tbb2 wIbNHesCaSpCkOl9fNoMz4n4m7uL1v0URcBXgR0RI3W/eXSSqtS45OXIQHUmBsA8rRnPsQVkbnfc cGdTGoWWqy7rBMHr6AB5jnbKqTNrmLnDBPgWeWzGFO3kua30X6ZGDW6zkB00oMOh3wvAsJFoapow y9Z+SKUosQhnSBDdxK4fiHKcLI9eordHfNNuC6d6bZkQtK8orSY/67+cYZJnXPeEzyTt5AVcz1wI vMbITBMWAhXbFe2opKcwBs81Y0L2pHrs+8l/51Cndtu8CR+3ajyS7sGPVaUh0fjfOt2KLgPT3vyd 6CAwNK4W7Z6R1ZXCCbVbDPOVNscVWzjcOty3A5/XXOH2vt3wsgvIDjSrPN8N+ZpLJWWdGWc2Dd8q AWVXP4IkgK3rcvuUq2BOElU2B1rxPkYEOrRQ0QyjqX90v1TL8sxVXOyuy5QxTTlvzmBIoWvNf7uM a7BOXGdVcEL2uZQ3OJheih91zgIwcvDSI2VPmqP71AYyU4HBNJngdDVJA8+CsT7OVaD8UNrrXd2Q fkpTJKY6D8+NOPDBXTR1XdoChz/XMEldrqtRiYssHQN2MkVpVXd3q2HZswo3KNfiney200/QSyj7 vjK5rcAuRTGwtyOPpu9BgI8o+FdtKobyqQSQoD99Y4nT8xtp6WNio3rvJ4jMyWwzWONnhYyC4Djo 8JP0+5qFpM/1KHFU1iatMYK+85GMc9i2eFmSk269OPW5S1p++wNdeEQuWTDbVfDmBtTEDUd3AUKk ogkuXKNA8Bax2ycNPuhK58zbfuwH1Goo9bNgD96CBPgPyNChqJmTLf6pI1M42Mbvt7tVRfBuRsLb A6M9YUZQvmAG/7gzIF+DmL7wIUy1fMZMcpGrkmjK0XUweyRSzjt4/c89CbAthrXE/8v++MMCK37W z3KTIM3mzpidVZyAThhDykBmIMvd/U1aKNx9K0T/m9SMEPTe4oMoCRUo/RwlrFQf/jNnaMxXKr4B t2o+S1XaRX3yfxzYq+LR0mQ9w04jMhjJqVGtKc0faqDdNHw7o68gB7CYt7giS4G77CoQcRwj1KUN h1qj+ad4FQOwyfs70KAphdRUyQrgyuak+BlUm1txnMU6xeSWE9uV1zvYZjwV20NSu/IT3VdIK4p7 RWC+lkXZE4E9nst0REPFADax9KtCSEzJi2rAgKcHOWDN0FhagZ396D0X6Kup9J1GJtsO1WE2DV0e BpLFr+zSxLBOWTy8rw7sTuWnzHAF+JMPR01qNOIlQ9ttRFbhq5uvjo1Vd4JEB04TqTBlUt14ozum 2DVooAnyxvtdkdRKmgxVBtY+Sr8YciCStC69NzTkGuURAffVVT/Wfpo9vLomO7UjDmc9TEXoklEY ayR+dF44/VZcqsS2eUzvE4/C/gSlVWifDEKOE/lRvOXJykkCxdDL4y6v30zdXep5oOXesAr/RvrM xElAJLayeuvDNWMTGDVr8EnZhl+rj7QK3KX/Iv0wW+2GKzoVIUEo7jAM/M9kl32zSNWvHuwXtsQr vwPRqXga8FcZVlBughr6jRWnVKiYOtsoBOGcnV+gs/hnHeynPwFSkBhEvXj82LQdTSy8qvrTvErr HCoMYR/Ll95DbEPbk5bZNBTV2W0dEu8SF48+zifyUV/0z5oX1DvGYXB9OpUWWgo8j8zuaZgFrpAB cUBGEf9s6LwH9HCylUUjh7BjMjRjOl4EYzTzp1uJ87FJ8L2laulm4r6eAa+NrJYzw3Ehhu+wX9Mc hUCyhJhZt1EYwysibLycNxg7UbucWgac6gaCOL5+Nm5pcyTn9v08gbQxarp7hDznyY4U858az1Ej SoHAkP6NSdWbhDvgirL7NDlbbiGkbHga2aHeZYUm2S22/EMkIIQqhiAaPNX5QgBRcK0yqFDv4LI8 V3Z150ZCXyzAzUji5WRGI3VuGjS7bNTf3ff/lcTUsFy92zfK6++9TI1FFffD1TfzwMah/Xl34Vxd XEGT4u5PBmBTQngAGylsYXgb0rshElADT7XMVFo65kIt2yn7L/BeizXdnxfWH7HbYpS5QdeIrFJx NDPSaHrSVKK37TlulRndsdSjwo0/6BU+G4MjFPx9RRMRGUhRXvSjriP4H2ZLgUApmeBpBI7IzaxO 8U2Gt+C4IZrlOwrWJ0mw7clPAJ4To2533ndbOic/dly2bWxsdvcws89Oho5YFcaBMKULRH+/nL1c 8FCnIQGXeJr8Smf4dykaiyvolMX159ZLqqtZuYG3w9WONT8SVjVHQxBDxhPJtiMycBqwxvVbLzX/ IGVsET6dn6dCMlrR62R2jTe33jXiSLdi01UTdNUWcMelJSB6chsPNVnIYLL0hOH0RN3vVdoj3Kab R+O1Ei8xXBlC/tJo+Ma/ylxbO7zFyb6jRpwLurku2PN8Ff/ziMcJof29I1IfDixLmgC/IzCzwVB5 lLwLClob/1YbCASQnnWf2yP4pJmYQHXxh7fwIddhVqGDAtHwtsZ+NFoI6BvH6I8iw92ElG2S8M/F tm57827y+J4VXTYX8k/Xwj2AsA7wJlmTY+pY3JOPtB7DzWqurYKC5TVW+KA2/5lEQbWXOG9fhLPC lyD3etlC93vv/6sBjwXzb0Nf2hJD7hEAVwO7Olzzt3vGZ6JetczfSTsGI4HQqX03T8J/FbrCIgJk auchMuMocFtX22LCClWrZ+Zl2GzqkJOFOdMFA/qjmLI1Lk2adZWQEC3ceaNNEtjIFT2Q25vVmxj9 ZCy1hYv9aTQMExEMqJZiJ83gch6g6gwuCSutoG9WtUmq+oCjU38mDO9PXvLiEukDztG+fZ0ERhTi gOwpawYZcbVySEej+jGbo8ZCl6/8+pIG8dgX7osx4E9M7JQhVPgrX6QedODFXSMcei8IFFl2pobj TLuG5H9LRmRFa3/Iq/ycNNZ8rm9cp57SB8lTE0CQSUaNdcxdPmI0CG4VpDE1ZDolmWR60jnOmdAw wCfAQLNqjliLpOod5sSEXlheqDY+LdHaa5etM0nTVWwiwdg14kDT8cRomcyJgrV86cZIN810NIm8 U7ZZAQIXsvFz0RUXN79d4Hv4NaBe58rhFHOfd7QYbhxEnSODwsGjP2Qn9C1gDpKLqJkrZtUtQqJc Ax3GqWVhSouARn3kNLVW6GRN7BXmxBvF28HU7eXGKDGZnRs+WZesOzVEApVx+5+h/SSvIqQJUo9x Q947FEeDsOcn9NfgsRcVIWhUyyfDvHF6uf/qXwgIq4ZamCwAzTkDBijHKkDfuiQU4jj3j99ndgnL PZBmlxa+kq3xSkmnHVKJPNVNjXVec/8dfb9mdKpuhGQQlo0bP8d0f9x7xsDFLhpHciyvDx+5jgto 4zPovLEwPkCgTDBamtTeIKSfS+rG5oQB2sdroaTEvQNbDWOHpYq9iX9axALTT/ONQ3LfzqK0sYAg NHVSqLoRRWtKVQE= `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 4992) `protect data_block X256/dZaB+mWsDOJBZUNoEpesdOh9yU8pts9LhNkboUg3+porPYcMfL4zuORiY5Imb+ftmM613oh AkArL6T8TiRJ+tJ6zDzjeSFIzEW8ej255st1KKwEQfc40URYVtyG71PxApdo5r9ToqIXH1Y70iNu CxWxrcZw9WpI6CV36uPw0aRuqpWmiYd0NuvwqIsb+y9n69Cts40TFghcQzwz6QSx8bIIY6QjeEXX FZ1F40vKZa651llX/Ezo9Y5hIGByf1Bkzhq9PrCkPsMOHms07T+rE+wmvkQpW97f1re64Cd1jQxR i9WJ2eAUmvSZKqOijZKDLNHTybEwpkWBILL4GM0zmS3HdUHJt5nn2N/RC+HIJEbtjF2Ayupsr44x HNrmwKqnsSlwQt8/sh+CqNj8ttgHzT2lcZLHzQ9MOG7mdlVamLWctqrRGrGJov/PDoEnL9S+lzTC vJnnQrLENe69kD5+cyp1up4Nd55tXgiqxuSSICIzPkbw/XDqY2kKCO4cgnQzjHvvZPOmN/cM9ZCS cHmmz7ba5UwZVI7CSpWO6xvk/eIRKLUqhEsxNKbNQCaysE3A8v9rCelFeTKjRShb2MjkAUD/dKUn +iv2+XJV6nQGZG0ShLIAE9y3wEnzK/LmadsLnUhSRyLdmxmkpRKvix9HBlr/IL/QF+SWGnBPREKU b9yUjEN1qtitrJt9UD2mSp3D+EpybchfERMUBxi/7IvgnFxsn5OmfvSkd2HlDuz1V5wUvjJS2LNg 4+T/ChKXnU4lOhc2u0eIpimQroDmRrMQ8XRzE84zktWLtdVpnE11sT1AKL3MPbpGqmPWwoDGM+Q9 nCXW4/eKHwymf+u0Wk97IXzWB5cdsEhjhJq20rXz0MZif26ke/oJpUHp9E8xE/ZorrmkVUBzIY2C KpYGKmF6Yw+XyzgQ7Fj+kH9jcj7Y9uf43FNaf+Qt7MC9Zskg6VVE3aXQz1BTWq+j4G5w9yLoMu6Z wWcqBsh7qNnqx2CCPs7O0f255GrhDp9m7sS5CAQgVt9jKX2Zaa4M3ZhVInznrC5hXYLVwxc+m2TA CMMiADFmfyhPLQANpzyv2yAZS0lfonPUwXqksAl3s9c9+fiiCNbnWqum2SbHb32x6OSgKcfN6jON xnF0HM/OFEbreIrJxhFuJ1KFYKv76wjqq+kqq1VCmC8hLoEIWsQM2AFp9xzeVUwHqBjdpkUEGgS1 kLH7ynja03B7eLfagW/GMpPKRp+TpOQ5GIN5myAnyGINoOxDReu6t86bDZyv5X4xaLS8deQeuzFz MXBMnRFaQ68vKCmL57qd4VPuXT+34rvKXHj+6UnNRXQsmkbtmxK28ZR+4rPw+GcLxQXuLMb9WhRg oYW9+VV36UarONSZz5Iu7eRSDhIttt9/D6fYB5SwGWaAXVbUGW8HmthPKMhiJ/IKjctRw5tpm+YO FJWTzV4C5O6VX7YdX/J6WYN/6BaSjjDrbM4mRZQ5YKws7MIl6dhvZ91ihgqr383WxIDA+qdxhFHa 37jukVZu7T6icxxOIwZHSwW3lp25cLo96K+wmRNuHfmiGlBKM6orjX2z+SJUTotwPtSCnJFUcQF+ g+9S8meouyf4165W3S0m9qKpE67N0bFEk3djdEKp2X+kLbHkVuI4szoj0/gEoHvYYSaCVfzT9a2w fsnywzF5mnucfW+Dzc4oJ9U968BNkhddBI5ILkS+g2CRYsbJwsecb/L6rHLt8R61B8BB7+KDylxh xQy8HHd8C0yMDbcCB7qaJ9EdC4H4OHesivf7tc3lNy2yyiEAI9KZ+m1ci4luqIa+3Rv9ED+uhLur DhF7TkNBrJ7MgNAGBLtLOZPtYTGuh0MsN8EKgVwAz/gYQPj9neJQB9DISPtLf3VJ/Qe4UgAtmJ4D 0fIfpx6RlTtQ9z/yTN7QGd5Dtz/KuS74namvQ5+PHinhsBodn4Ep+/gbSngwQGivVgV2iZqwiEx4 PFzwR1vKUe1zZ8let7Cbfzct7IjF579nGm7fyEozME1R/x2c0mh1Xv6iAE86NgqlcWe+Yw2np2ml wS4Dek7cK8SjjUtSNJUcmCpnb4MYSL2Rh4W1vL5uDyCdRB28FD3IsDcu78Qkwvl3y+kpXps4pWIG OdMRK0fPDEN9PCJFBC1TOEGli6bfx/XcCBPrw9d6FAsKjMw3kTQsHc3bMTxSqkC50RNkW5EeTKrC FOuKQxQNv9+2r4m7fz1007WMreXQOE6rwFi7xVsrV/AAaqWDuydQg1PRL42Xo/JDLKjQqEqgFNE3 460TClhwefuqSWxN7UoUiZ1ZtywZkekUsyeQkuSRmj1OqSHwk2vvedE3v73PAkFFZw4eKkMp3XNd 3QymN5lAb+QJrwKCaSTmvMttqmldoOUAyo5n/91fkwRZga5fieTk0XTnV9EDHTsNKJd1RXZpoaOg K7dgWWdQIC6kwHAzSkJEk2uHqzkPRQbSiDt0XHQkbiWXDwyhkbJ7Pa8b0LSqOK3WCmj8w/VJkOcu MshaGHUQDtBpJZW3dM9VAeSdVLwz4bTPZ9HofEUeC4qh4ItZIkJYE8Anm8A+CgYvH/XLx21aRBx+ qTai9ufzbIGSXwClxhxqx5iKXb4tETlY0BkfqPWP2Px6dKhhYFoIdzFixxcTswolgO3WFU9MQkEe zrSLUNwSUd1kezbXfrK/s/HIhVTbzp9N09uMnnlUQfR8E1Nx1Z4LTEkLhD6WadvH91DqvnC/EKwH bWBiv7vdNn0YITwmp5SrOOUd1yrtf9nWTzB8oXQaD307o3hKvZC0JlzMSEIDTEcng0RBKlbkevSz jhcQWzqRcGfKWWG/nei2ThPxJOKb51zGzlDo+1+JwEXGPVY6+MONmcZA4d8Z0p/tn3zbYJLupKnE s2xVZrxvbra/bFjpvIESet7Mw0aTKQEXqeMQ0EnglGkOEG3xgeDIxJr9Da2Pi2PTEjX7CzUJFWQi NNTM3YYzkBXJ7aSuGSk5W3BIOESQhTOZJ1wtdfhXqNBE3L9VWVNa2J5p2rr8Ds/reAr6OmJLqY2Y i2wvimQQlscqtBegOJEwW72EZpdWkjKC9Xl6hGE58jsAWZgpmycEI+o/qNO6lQTF7tUsRwAIoFAe TIEZ+T0zQoBxIQg/DQuintrv2ufEAHqmFWYuvm2O1D/dZogR+SjOXlcc2+KT5kgBlUCAQYEzXYwW Fl2vp0vqMYENcpB20wtHgKHEDVenKsIEezn1o3Hn8C9y0wnwdA1ye4YvaI65RY7fhly7htvf8wxq SAgNS+QUT5hKmypHhv3pIFa8xs/Xf/UqgWxjShPV7XTp1qh6AtTZxWco19fxGk+C/fmM+51OExCp BWWPgwfS5G+es6GtRLaGnyexvoPb9Ua9oi3oEzgJYQo6pbulBdGDMotO2g4sqGlgcAie+WcBagSK UkW6t9ccy9tL6k8kQ6GI8w52BCzwFCCkT06XbahPuGP3u/OVBtnKnV7e45bxmRqWvtDj5vIG0+II 0cS2FxrsVoZEu6XyFIq0eoay+D3XHFVubkyOIh8w+KNTWNJzuLzYTygS68g26rp1vwdZgtpRaH1q VPvOsGq0uGumpGXk1eeG9RpAFq4+xzRpHkWD9RekERy+3W8YpoWo8DKkbDMQtAiAvzPAITNpQmfV 5/blG82osVTQuSiJwvkGH2gs4NCbZ77VgCJ/dfWQA9iADY8QQjJvsfZdn7KztzYv8eMJw9AC11Zl 6M3D453cA5y1D01TtjxdJg0wxtd7mi2ORXWHkGr+jjMbMON2hNW/8KXYLaBvubYDn3FMy/bB1twU mnjeWpX069mA4lE0rK5KV4uzfKy3YtYcR4+XXVdlQUNeRoZGtiPBq626VgS4+fo8+TYBGX11EIEe 3wEqVGfIIb42x8xl9XmLBixhkeATTIkafy7L5kCKC6NH+89S5Z43io/8IYn7YWrNmcsppV6v3skn MAIEaohvDKsgyds4zwbd2mIL5KvgzEEYRp1FrxjlqSp/+POuoVHr1DbtJ6EywAuSEV/A5raz5W/c /+2FmYv0M47H7/l11PXw2DVAv0GRrpbvF8VvvVx0ojcDw5fVB86hzRTloEnhqjow+DkW/Nsm5q6q HR9tSaVqc51E8OdiU+ZYPHHgJv1O1qNVEE5VAu8ZFsf7A9mVqOEeHRUIgTY/qipj+katJS826U+W tlKaw+gVWdU2I3k8l9boVSyYUJJ+dRdbmMThtfpo8wR8TwNiCK+qkcuT8rPScdussrYHUrkuTm/1 MskqmxQJvxw9Kta+lJ2Wg17OIiEpo3mrqmc8GQiAJOOGyaRl+Nu3qYb5czE1Zha0PlOumRfG5JLx 7O7PKTdVm7QxMXwVsJ0+mqQVUO7RHU4avyyXWxYEQjKLvln8mOQv6Qrksv6BWiBjn8X6JbrAguUT PVD/9KyEyUJEuZH1iTB9BTmjoAJt/+ZVfLbE5PG2KIw2C0/gY2GM4Vv3CYAlJbuBlk4aSO/g1Eow l9ljkplNvBN3Rq78iX9Kulkm4Kt7qm8oIAVvFIGOH5SOkeQ2r2gFJ0f8Z//viagWYFd39TQR+Lta QjYFIxwzFZ8WUkL/p4cf9YDbstU6He01zEjdSAZdHtwrLbRRXlsvdBT7bZ4CRLwzwbvA454yUeff YdAJlwFqYe4e7nK/Wt9VTS9WshZ2jyI5CynYzbIvJ/I9yKjqtqmpDyy69cBosVwcGeKuQp1ZBPXk edTZ8jtSCKaLVcEj26M08KibalozhldsZhfLQjgRLBMmuAIhqVmpkP2iP47fAHg7Uol+NeB6XMW0 BdqLhrfAn9wiRPY6QUX0bECRMTMP2GnFJlCTAOELQn89zNEDmVq1+5OBVDM41x7xW8wzPXqlThJK hdJ3d+MqiEVIvzfishjvKY+2FD6Vls/ve+d6R6MLkMneR75dT0pq2Hr+n1uSdEE1bbTPZLTW+dC1 qQus/b80rpU7Hkeyic4oSuGcjCesnRbiQ+XE2qUe8lKjjk8go/Ge+eNwmlOOXnz+5aoej81u2fGz OVe0Py2vjvS+zi7V34VbiFTx1U1+FTCS4hnNNLPH/3EAqDM2fLOPesFzv+XjBFbkV5sIGJIJKT+b 5qREs15JY+cTKdDb4F9EHFXV1z6cf5lI2krJKn2T9KsdClt8F8jSIXAIK1att5Ik7bNqHdntghRK FZqXxLHWOSxVBm2Si3nrsVFTJQa9V5vB4esLFFz7XUvzN52jR/YO+kQjaIaDXzn/FS/2QSoIDzOd nfD9OdYJ2URfuJGRLqo4C/31FVQJ3Vk+V0Kbds4n6RMaMYGchq4MbNLEqcC+3knTx77wmDbjn314 1CJrTdqk34W+RCS85myZqNBTCH/Vbnf4+v+LDUB4D+rwSE1KAQ3OsvZUvebQd2Y3PYajOEfQgeQq ZXJDXiCYD8o6teHV9US0BmNlADUWLY/4SEL6a5KL7ggAE1YPynHihW3MlZ1upU0W35BKtbWlXEu9 ue2otS7Es9YKK9hORPTUyawTPylwhYCVTxm5fopVnFdgwrwD5bRRf7T8xFZ1wjib0ujovLUnCc8M WY/DrFPXHkGlcuTXsTsTnSlj0cxT5AvG7hu9V8U6qFwNyY2eY8PgXc8Ov1HrC4LWxY/l7eEDOJhI VmbZ+7ZIpG0e0ET6cJ1294wBRxmLYxQTYvGc6BfgNLPUoF0KbthkzpEGH7Dh/Y7RYZSd7iZHUSTY nkvYlxDz52A+3ZH9m+icJFCzNlyrZYb+qqM+c+j3W7c8+EenVN1+LIRTHxIEbsNTA3GJRxSt27qD xKR7wU+ICm9JK1EEUXBZlv0DTv4uF+YqTSw5eCnqAL1zNJ1SpNvGdcSUKOzonlHdDDc8L7mZm6yU bdpNC5f+vBLE+LcG26unZqPprPGgBw2YdlWwhz8fMn8yqWmUKgb516kDd7EWImoO8o/+bUkXvkSG 85AaWMoPtXUZWfAxm7M9XaWjIipF9+JDblGjMvUi1/idRy9m6Vz1NH0Z+GcDd5Gzvy00q4o3lLiz 5qQDPaQ8UTE1VHBlSmxzeRgfSdm3WFr/HxHykq/7+4gccY/0C9R0k2qSJlzksag0vR3p1OFcBcr4 EkG8rI5jpOAP1ElXQMYIXnLmA3+x5sZFZWN45V47ytqLaiPtaZa7615SNDUH2iZ1qFgZuOWm502S 46pM+DN8ADhj3L9yZ7s4xtugtihA63jIgXqc43PudL0Wfm3pfSAYVn8ec8noTbg5mpwnuAlVOgDu HL+XkQX+nNXlaC8fpKHytSZqTbwvjm84tWvunMj77fwOLS8AmagqlWscjwDUoT86KKxrsm8ZjCtN /qbS7UQshAJArxKapORXGNXkcD6ee1+YsgDKS37YwY2OYHtF22Zyreno1maN+F1nhID4fkAW1EA8 y5HzeD9cazwMewJDAs0tgT8Cso0qhViEtai/MMuCVn4t5tSq0CAONphnP9C/TUWxDt1CtYu0i92K LmnLDaz+R2sqvYqcMc3cJ0PAMVTu+N80/HSgtZ7MbXzx/cpFnsrxp//JVrFwi0d8/XbQjDZxFhx6 dUdotSfJQzpR213+L4OMrvk1aHI6HEwDBRpEqlMnJvQViwuS18724hDf1BubTVJcw7utt1XO7hqo SnQltZkEOyi9ewATRONvfq+sb94LH6KscnuCGC9eKWWL `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 19200) `protect data_block dok6f1PjRyvRZhS9BapubvvOv+OUZZNhMAqxhvkHYTatOP5iyiiWg832nAYrSfnDIcqLwpZ136zW AWf3grdWnIluMew27IDsPeMh+EXTkn/PePH+eMsznMT4Znn8OGCOujsftVERybUKTeY9wdokdzpD T0B54kMHFcNbk+ElGvM1BTYGuOw/lXjbdqob/QlduClVrOByiVUdQ2ZWotZMs837BdHno9bf6+ZB 3NB8IjwpWA/7ToIYDSbg6zAIuyUuHThgygQy3L3In2lDoBmtBfvylZaFUdx5ETIHffOGvC65i5k0 glfA0MWvEyT01OUZ9MFV704iFkJNT+zpbUO98rU3hSJB0jhiMnmKiL35LqE7XDuuw6RehplilL1m UgIS5CLa5Rzsp5nnmOgAvfuseDTS6b+iF+gCYMoPz2xU18aICEeVHopbdX2Tp9eTVXZ+chv8RCeR 6jAAR1rpJeUCqmBQb0wl63UhvbCyvC5XZCzT+LXX8StpAwv7CiC6WiFd4wocuujkvX2kkdubI4J4 x8pZs0k9/AE9h9xtfW9prjYZQLc5wcqcMNBT+D169HSOtHzBrzjesuxF85jELy4SmJW3xmOR5pD6 MHZZ9GBodb7Qh6ZPDM5irjm1myhYyqn+x+lkwY3NbUPzxfew31gDY8b6Lw+Z5sTwkBd+XGE27dOv Re9e91Q6A4ZpQ4UHiNbuGwfJQcN/Y1wy7d3rl0mkMepQ15xu7D4GfIrFq5iyGAha09V9Znh7Sdwz w5sXyzOPsxX1vXObMJsiAweDg0r0doJtcSh7PwGUHUOvnN6SqBAwXAyc+Ylq1JZbgqp8TXEEmJK4 UNZEidlYETNgU0PqS6T9E2O8ABkeUKj41aXv7jNZmL+6N3yZL6fXqNVR+XocPaT3S/EhiTCn+RDt uVwjirylJ1RUS1pgqHcQ46/mGKaBcLabIvZdNIHXuJTZwnHatJJC4uIIPGsj3bToDjoZxk9RvLG1 ukz2rGaSdxvyYfwfFTzxvePslDOeAVJH5lFJ4uQ7k5pprvSHk1LuiRJKKlwUj/PvtIJXYgv7UuXR +/XqU5zJloWBgWXnioVyG8SFzN7rzBVlliAhXXtqVafRiFLHFJ8Hp3oGYKfzMQjY80ii5A7xCsGe LCZ2WYChahZM81e2MitU9mM3j9C/YA6Jnf4t3rK4NMHCqghvR0EP+I4kFxJy1Ck9eKbUn/TFOl6b pswypTm93akQSlgPjjS6urz/AgLd19slZHmsvMaINH31JG+6OS8HngOzS4d5JgxBtjw6NQ+a6DCX ihngENvXdBLYo+Gn7I/O+vfHYmQDbrq5fJP5fzti2az+B7Ce0l7J33mdTuGdndQoe3wukPNS7siW zxLVI3+1cWzTm8B5OnO5uv+Gk5uaw1+bM/kEI1H19yaqZ9GMW/yGxBF84p5oohnDJzRrMoBxjYVG 3GEyxVlDkwndjf2FoKRBwxEvP9zb7GaQZVBm5iC1A0QPfFFGAom0QZoPNxC7dx8t8NDKIxuj/Al9 cWc+950lu9kp1FO+320kpCXLFa9RTbd2p+k6kx9jkxjkbZM32aeDxtSB9G8fsTM/IODBrr0TgZaj hnsbPndPLWrzXNob53bzqhUw+zInUuzf4W19isQBlwUpPsVZ6f06wzA6POkPqrKSJdC/HZOs1aBk kAK7S9U4WZTs55Zfs9LlG+n0V6OMKlFvvKmGBJDisHp/7UvUUE1GoY3Bimfw+DPyQTWGdmbb6u5O nIbqTt/HS7r8IUvi0VLGgsSprCngKl1aeoY5ngxUJrA3QfZkfv6lscKlP45Fqx1uvXKbR5o3H65T lBrDZodLF1LNw6sBl62FHmNJXngJ2NW1qVkf16j6D5PPrpRHt+8BF5ZhiCAwoW1bhfSNWmXn+1Wj cVrP3BNf1YRNbvKm8UPrQxskRagVboldQUEojszZscTMUhH4pcxkLR9ar9YsZIFFAJX8V5zE+Wnj 8BP2F2tY3qxm9kl0rS3TbMb1YHKyds8rJsRd1GKgUGpVT/oQcOkNADTCofjvWVYA9lX8XHPmX+aF OisQB3z4RW4Ok6sqte5tQ4R/bdWPo9/LYGEiO2fNghV/AB8lujczK206dxcIJDWNp3gKKzClNxNG Fahedr0/kFr9YSPV4ngg4Fef3aZjQ9YJI6MWD9eD8MH4PR42rpU/BTSS3MRqBD8O4UlQeqznbbO4 57x0xCT3yUXsk9zQZBbZtbh4wYD4a4TLDiL7VfF5bC+zUHA+YO4U3wDNns3Sj4/en19p9JGQHyqf +OaOOFrtxVFUkaQpjz6vxWVa7owDQWth5erXjBmIaxLmSFoN7jA/FXg0uUyVuBDeGEGBBInl/NJu /Vlk0peNvaPTgig4A8P/21V3hQr5Sv+2huQdx1aMVnKdbRDk5Bv1aOqzAVz8jAioK0kZuvL/ibQl HncRquZvQGzlXAwwCAK5kW/uLN2jKJAuMJSkpEtiPGbOkd3z9J4NEU12uOPGdh7d4EWxwxmuTs/t 2IL5Gfk7c2BAVuLx1LMceM1XFTETdBUhNtlQxuVyjlm+b54kK/ohDmyLtMaf86/k8UtO78waW7uU fcZyHL9IPukQ9dRJdvRoa1DKKgfgi7s2zSIctJBAWrXBQR09YAzZFQaBOugEYA+rnam9bNjClZPw +KYKY7hv1iazFdom+TBWsI75PssmvtZGHnqYKvsbcoNI01cjJ18Km6N+5xuY2k8qlE7zrQWX8t1c uYne1r1o3PGblsvfSG6IiFd7U1VShwmB/KQddcjOv+bjFAM7NYHxBBuIkOKkJhOhUSJ6S/t9odE+ gmZ9cM+hGGLFfWhtGODqBVUJ989h7zVAhlguIaRMKEt5RrnJQBkyuAYsULEyF+GZCtvCQcF+D20k EsVZH3yDYzkgN5qtJ+FiCwT+2bmvm4LatOwP6EmTGp8nVMfjUFTuUS6ZLAFXT249pXncgsN+9oDa ps0z8ikFCe4zu2pO5lGyI9S5rCUEikM5YTdGgtvG/DfTfKhmarW6nfvBFhpvHuN96Bxn/2pIUEBQ bJlHyx9AvrGG7e5G8eZzgRtO0erkfL8gcKotnPoBYmhDb6hsAi84RTJ5vIRRYv6pKwJWu7dtsIEM q19rUKmOmFJ0w1SuvvX7z4cfuQhKDY64gp1XkrnCTb3X13OUW7Z/PhQ2decruERcCusIbL5+tXsq z7OVLKgEppZV08LdyciTBAXWaI4aiVy+K0RbciuAwM9Tc8TtCbHcg16+RPm3oZGKsxSHkiTeOYkn C/9EbPe1LVkHYzV6h7vIazOSDHg4NagYMMz+Cl+BwG1UHcX1Mew1MtkFbet3E2fdbpWTBz9vhG+k xu/fIsr17gqhxWeQq1FG+Q0SSmGiXXadiHyS3I+Bhc/tLElyHsk9n4zdyDxRzJK/uJO/L4XA7LZY Xck4WiqkTL+aMxlhuo5OY0RTdxjJFrezygdEJ9FqChyVUlMsiOkeuVveJXFfvHTmHs9biLeWbbr7 90bThrEUyNoqLjdIQlrnPD7DDDm22Z0ea4jjd80vjNpQVRAdSu4GfbTcSsgTXAT1JCuoULhV3+Zp nUzmAceq2gsMkU6mzeDpna0bO6mC2+IAy830iJoGPwEptmDj1fXoHgKczR1y9qGHHt5fuGbh9EHz LM6wpzi2rW+uIORjgvxH1EGyEtlNnVFZAgxkfkYM1YPgy2UYDLf9zuc4i2dF+ApzSvAlrxudMKKz kbAawyjAn6k4DYd3OJsQ+Z/vyCkVyuqJRdfCLksAfun0kDXq0q6qQTjt/Yb6oaup44wxQUcIdBGW TCdMCIBJ9croFftF/JvaTqxlUeR6jVcvNjE1gDDBqcORTFMGFsQvrOfYCOAiFzTNcRNmGos1d4me ftFwjx75eiIXLJkTVaO2GIK03m9ov8EF//ex5ahsSno569tvD9SzXCuKXfklB3FqRyuGHc00tir9 GvK8tMr1o4dQ2ulI4xtwj2HWh/iqTMvEFVT4wooMarOFylC8aZE7dFPwh0yDOwgIZtbr25Vbc0IG j3SQIxaScl0dFs4V2EnNEHBCkUOe5HxbNVbEhGvaR3i208PjJt82Xtp/bSqtOmvsASIO/6K/i+7g Ftz2gAOGI8XGSO2LbOQMUd6YjHX1bOnGL+y9nh2umt2xaNb27eyGPL+zannGoK7wqYWj5qJRXH6v JuxpSog+opLqAKJWNdVlQ6d8a7/jlhET2vdjzehr1e75U8y0UcGYP6mEgXoX2yptdx5hYGuwYSjT t3wa6vYTC+mHSPDup8D25C1JYcLQ3EF+WCS9wjWpUP8G04fNGVD6Bk/GKgnd9EpR10EKMMInfbJB xTfRxUf8JB1sdkTOP7kExMb8J28xAyM4Z2Q8TVTRaDTUCc5NM1wPtkySAsYdcHEsPFFNwSqpYTwt CQfkKccRCpAFEWSBPXvQLoqDX2923dnoj997U4tCdGp5zgLwulU+CdL0ajf+My3m69Xn1zDDUMel l9kXlGWspA8+KXW5LGqcuOBg96NXYqfQgyep/nAKn84cQTYY6PQaCHZ7/2B+SaTE4BDfCpXaHMF3 V71BJrQH0UHUkMlpa8saa1bxNAd64ysQzt0tIcnftKg5VCTeeyn+hHd0GpjI2BZtv3GiZcUq8M01 2Ulw/XKtczAos0iJsOZhIKAMYJkakGqx+JPXN5jABSJAfJGYtrv2TIvOe4rC78RUX317PbpG+Ukx dYM8XRuUlFacD1FCO+53EPSpZKKjKlNcuTiJaSuC4BY7zcOdXKsSUze36iE25r9OvVUBMQhf/YY/ Hp9nstXjwcDwcwHGIHcXjwEDxqfkRy1bj/GL/aSL06V/9LHHx5aFQ0QCuLdfdsChmte3M6g4j86P v757e6jFCsA/srQs9W9GkDB6KuoqQfzrFnZkx2lDe+VPR3GDsyaW3qqF3tCH+uK7RWRodXqEaDPY tcsr2lyXDAbkknnCq7X9yKSLkzUTNB0EL8vQ7VVfCGspGAtEuw5wJdj3cv89ei76fi31bbzyGSTA JdTAd7j0A+aBnEHLXeP5oFvyWRZWIiKZs8OoOUrBYhGy2oSSzx3kB8fYGbswetMplaePzvyjgWsB Fa9t9/LfPm9kZy8ruxlZ6twYlwRVMvM+kPzgNatatCoabTXV4h+cDxtXhnRo8r/DJmfvJbA0/CWB j+QCYaw2SAM7XE/LxWedYCPhth6w+8+6tELycMSZcEPyLDsotjLbPSs/czY2I6JGgz0emj7pPX8D QKD4ClF3mJ2oQsebPbpbrqcxx9OlaPDXhWX3j25zVPkv/vakunGLcrbrIzGmeztn1ML3HyAWhchJ BebnyvVaD18EW+pbRw3WpCUyKxfBImaqAeehLWhvI8Q+PAqErk3bjMSFm2GEnyNjr8hjT1TzNmjJ qb3N5mgdSSatC7NgryvtDSUUQeptS7yF1Zl/gDppOupiG0RlVmzYM6dBRFwuOHniGXzIv0Z8xbtU x3pgbnkDVQD4yWIgIWq0i2tWZJQWhsb48K8Ai9D4YBiVAuMVrW7RLtIu073e6vkCxwBWi5HcWeUE pHheof6i04otG6iOYaElps5Fmlu8gCfvLqIIVZ+pWE/SXRblRvm4gsrYt6cw/GB4zvPT4AbRoG1T 8aY7+VHwK2zKwt+FyJuRvR9oRDGgv76NuvOSs+XVeMsf9MhvXUMEcfjpkhR95XhgO/cqu+Yu8Zlg 1cXJttOZalLOfCcurESn9RGbdbqdxLz62nQvkwDQI00CxMJp30z4gQHoSJ3b5jufC5eyfayB96rb JdzL6124AqEsMLAtfS1vF49Z4NwNA7UXLhylP5ujR4cztDRCph+l3/XZhnsTWfeBzcImuYcqJxCH BnGZD5VWpAuCbo9F0aWR4u6olrH7Pk4ml3CYRTgygXwtp7mz8y8lOonem+Mhdrb2zbau3B9znBXq LGVojyZmzmYCXDI9d//ey9B/vrdSDeELbeC2DtqEZkYuE2PhEptvjsN4VRQEovMZRCnN8rtfahCz tUc6sHn321le5kLYJUOBWwyAx0Cp8JxNqtCOMhqaLOsrKeIH9dQJd4IVNAaF13ydQtb9uMhZvFIy i7K+Hcei7IkoE/N9+DvpJfmVBwSLxCHdJi6RxeORlDQvWCirUKp2MCHFZZ8r2w9iDD57fDkhdJm0 4TPFqBa9bwFtKb3yu0JFpyd50elFCpjFakWqWaE7z85SoeG9vk1xTG+4NirGYkcIt9UkDs0L72Pc TfgeegFYTi+SoysC+wuSywUuuGh0aoh7NluXc4p8lziNUcBNclX8fowGDa48iTW2rzVMAd/JicQt MSvqU4/Gbv70vk5teXfFEZr6SpsmljFg0wYPjsQUWkOFQFVMwhDCKc7wpLL0cyK1PxS8QB+k3jYV 1tn8MVelb4uuR+9d2XKj5Osz6HZ8jifelrIWZ6ly/BCAFmE79ptTx9KFunvRpBKshPsiZmD1B9Dr rfruSKTP28BlLMgTPjvTJGn54C3CLA+EeGLFxsWaPexn4uL/UK65D6vSFYr0NB9+Z6uenjJWpY3B nsPnL7APL1slhXO6RR4BWOJ02qNxuL4AwXCLoaCHEboHdNRI8Zb7NjumcfMie1wu+mqYAVSBKYr6 JSC3l7rnU2KhSBHdKPwjY3md2JKJE0DKnUt11ZS+dEZRLx9hDAViMLQJP+11ubQzu7jFaunpvyNs dtIcl+n0BH9z3lzJKHnO2avF1UF+LCzdtBQpki3VLh6micrZuSyVXrud9JqpSGxLFkWHtzPVxNw7 eX/PRMz/4bzeZnQdOB+GMWl1tCRmZgFgg7BzlKsFAAsYJnZFbeDj5pFTBoUJr+6SQcWaJeRkdsru m7891p0n6VaTOX/LPK4/AN+sKiSdxZu2Cui69aSo1imkMAxtGn17xSJB+qevNjv0e7TwoKBOitSR Wy9buF9SBtTYE4FDo5S2Rq/trmOdBya0CAlH1G3YAbe5k02QSmSuv3uyskXGmqM8NBtz9zqCzSze 3z6gPOSDrWwMchDb6ntegaREyQbTOebOZQVwRqLa7j6JimBRrvvvnk2V2M0QHKZg/50c7ovrkJXi pc/e5KoQeLaS0++Y4gT6Q9htukSJujLFPrYPao1XgLBOU6YKIsIdm7GxfJoDk/fcHtUeg6slRQiC KErAnNM7w0V3L9tegm2BQqUMm+p8io7GgnWwnyb3Ah7LKwyZaMPvzdu+8ccctf8iwvoy7xSpA7LG l6T9souriHy21BFg45TjFMmSlrEShBAKhrM+AYjnH0vj1dXk9eJVP0gHj+/Y31LftKmFBHSovgCg rH98Zkb/GbFXmuqR/jkNc8kOJuomoirqM1Drz0G9GSGH6iloxtiaE6VIrbV2nAiCAdpzWlxsg1rm n+/1kB+6BWFv3aG+ggYsq3kjs1L8lM9VjL3LFUvnpT3QuK/jngyvo/kDEEsbosdDkzPhrKy4mxQw QBDiY/aJlZJjkXRAqB7+g5tp1Q15uZvoz+7K+Q6FtQOI6eReEepn/ofb2IgmOwoD6bcv4O5Hn7ub 5+NEyYQIZ9V2RFh7wEWrfe74oK9BBtjbzPkVj3j5GiS6qiFjByHnB6zrA5pQc3QyagvCpD4f8Tlr g+tI/SL6z/BY3ETpcrAwSknmogA9CLgXg6lgtLMLzhFjCDLuSWoAuSaQa7BNCOP3H0+SjK4kyjub 2a743Ayn82u0+MkitrXxHcs3LzeTw4IbjXq98J88FUKUSDbZgc0KMi7p/2ttgzU+/aqQc5JzSSaB HKO0UqN2opGglL6ITM33ymX3X/OmmbJP1tTr/eYlsP+4q0ZDJPJBGHp7gJPnjq9DqkRDZ+hFe+lV lWtM5LRCqN3gqfjWG6laX3CAr3wunRqy/ofXsmhBYI++KHLR4BE3wTf1D+pTeoexLBilrQGPbITk 2/9+SJ8UexpcLfUogS1dzafhDkStiLIEh2DLJqOWNNQpEDetlkiviN84WHxOOuZiCwh6BC94Ys9q pRpNnwr5fxFzq8F7MXv4RSj5tcJtMAvqq3cMzLdEHNST1hjrcciedAGCKSRYt0Ol4ONSDrc9APWC noJ3BvcOaR9l3PdYjT2FQpCqOHUNYLawZbbAcEz719tGdhawAos2chA9Z3PysytJ3WBhBhjzkjlk aSwmXfon1K+/DDOpadNfpJKE7uNWzno3+BuqZqrY7iHi7OF6SKXeIHHF+oqe82hSvWrzhrYZn8V3 zHaRAjNWliK1vvpaoN6k3izTG0/x3RRVyNYHgs/u5Eld9YDwo74SZ4aj9Nj2Qu3Go1D+QaF8Ba8e 2X13dVJ1Uz9GLXdUL0IEAdWaF0Z/+6bjj4fGKxw+j9sZwjMyfXXa/0XLIDVZtjNdyMzZ8Ubovd/8 iLnZ+2nXanrt9j7OA1wRGfBw2cKuG2PDfZhO5uVQwkq/DSMGsiFxhdbXQsFEojDd+LD1aJHBznIE cDt5iaUWPr09S5OjgNcs9RzM1XNi8s4qd4sHtlBpHlnTE3aRXIJSETQEJ2ZrV9gnL3qhCgUECojp BUdtFQ4hAHECiyVXLlsOe6U0BfzEE3dqWBV+0xEiD6H0kAUI3v2COE/3gVscuV3ON1Z0b5bcakeR RejKnDxUs6VxsTxlTNjz3mvk9IMR/jpqhzNMc3s2tspt8Z6FH9Zyeh7x4D/7Vv7PlmHeQdbKvxoj hS/Ee6SRG84vUDAkl9uGNuHHryUfewvJ1zIg8MRjpVNkPHr4haMlq/EJAOAA6MIQDECgt2Q0gLVw m5KiNDMkIs5lbE4XsmO9h2BCGhuhqczs3BAcLtIFeuVdUInFEaTHYhWnm5m3M5ntRaio/yYJIivX Uv28Lws70pFag/gb24CC45xDTAEMUsc1QHNutybTRU8PuScR8Gu5UKLNd3DGFYCiXFK7w+/Uk7pG KQdzaNviAB5cCV5KpEYcpRDa6/Tcr/s3V33RvvpBMJCwV19aHfDT31i18Uf0jwSY/1GSzypIcqtR sp8dWSgT27Wg9ib+Jd+mSv6uPfD5lputWakGyrA4TBg6tJM6yJqJGmJJQvYOaU4ImiqE4eQ6KX7R n3oFvIS+5API7zqUF0AuC980kP7VdrVA9gzVIDMBTfD46bGGFJxUhMoT3vSuEnFnwWUy2dOTzeAO dZzSj77IQS4No23Z8gEUM6CFof9kFWGTqyQDRPY1I1h2qNL8UORs6Ju/F2SIit8M3ym0RGrIng6D kwCK2lCnG1fJgLfiSxI5eAX3F/SIkA3x0IGET5pcEzkRSN1vj4PPczlzKKK8jszxiOR1nM5osw2x 38dgEvrJnUMxgrP7hmSVabbYhISGll5VdOQ74b99as4pEA5enj12uvfP8ISC56aHwOe+lkFeMA99 fh+J7PAT0SHRp6TXhcE/9gsYhnpyJmwn+zjJIs2yQoPWNdhhpKdw1sdmHQIqLFJcFIFG2di0sfc8 cUXGRRCKIqJG5cGzLmhAji6H2tMoaFYT4RLAh0monhWHyddTHxggG+iQxYXyBNWywA6gS834Ww9R +LUoABnK9Wn1apg4Jv00euQ5FhTuGBdfC1jImhxpyUExovTm7AaoPdifJiCwQAswqYvN1ryirzja yFGJDy/DFGa4wukdKmvwon71MkEFyVuLCYe9TWW7HDCHpSqS1FbD5tvFuuqUaWVTvoBfuVALD+My ifnHmA8wlD/2UdsPI1q8UNn0YNczJxsZfApWzvoX6WHhvg4CYOJRS6N5h6noDVIa0Db3+u1E0r7j cUkpBNEce7cgcUSiUZUo3pNJYkw2NNZLwRDAO0vtrzlWWIxgQuCPOtSIglzVXbs0rguhmGsJv2bJ wQhGgzKuf6KUQM3HhEWja0hYBoDhztGc2H9pVgyC8BZyKYQQvtfPl+KUlUWck+QiYaVb/3Gi9OrI 2Bvl68PsBL4XP9pm88NJ/KEAuwJt4EudPSLtbPvBVDm7s9Stv9BT4Tv9SRRXTgA+r1171yctl6d+ 6+02HvdNcO+St3oEyEzuVy7p1cXKyHCNuzbrlmacZjmui4NdWHwLR6aq4dVKNzLcT5exLLQfrJSM u1gmnXJGrXnI0hnoWrRw7tJupqyLCUi1RKLPyco/Vmj9f3hfA/XgSahgYWq96s8jur/vz18HeXhl LZvkZzch8v7WvqNukV3wiV+JT49lQfOHZ508QjIRXhTmNksOh/oTS8YOG7innt1ba+F/ZO0ifXyz qZtdQxzjp8l6x+eZm+H2SqjbRQUddd4oLfDoSrEapXwi3c1fcRiqkBcfxqsN9NDO7SJoxkjBaz1G G6Y0U2KY/MvMopx78dgCzBKMNpdajaujBvBNKDTgLPH8LZaoOTV5Q/YR6J9kvP12U2uxjSUY7o6J cVu4bdm84NosY//2ZL17HYenv9FTk012+xhO6Ix5niAOD6UDVu9ZigjcJA9r9eO9DSR5njzZt99V 9BeUBVDXw5eJHmBsQtlOZFA9oIocKqdf4bM9q373RD0tMnXmX2vzc9bASkj7ywM2ACHLLu94CKyG QLPWLZZ78fVnaz+6k0WhPyPBuTDD8VasBfROtbwRm+bMhVXx2LXxVgcxSm6zk7t1sstd1RlbbQ38 yBQbnYgyyTQIe/GbMITMMzoAurv0ZIQTNGrrK8pkpVVucNvGYJ9Twz8436YhNc8prGPt+xReq3Jp Qte+DQ87uTuohtdH0/AaR7MOj45+qbufFD/D8We+Mr0uwxR6p3Zntjipj2XVLfZ5uPz/IWBWkR79 UcPnFEcNwZqeO67+Kkx4536EusNgzhTwAVQeoARZfhiqgH4ktH/0Pn7K2dMZf6rSoeH71x7qFiY/ MOKWMvbzm98G3Tpvu4nFHnQj/RRTehxHnvsEOOqC0z9JsDyebYjGs3bZdaSjXpkUD4XFnt0USwCi RRKl0PQ5DVgldJf2xlsHns3f/ZRqEDtH3SgPhd5fkZxcTV8gOcbiHv82OMZ1AMg1S0C/X+kdVfJH V4wKx8ItOma3cUFBU9NTPMO4F5IB4jU+yEpo5cExIfL7x1u4Nl8TEn4O63F7fANQum+WN8jTuMxB bsQMU+t32XUNBjfDlDBj7tgWWa2w+XKGlQ8sEDdATGXWVXab1OfX8+bHhzswKArgo5JJBu58yZ45 5BtG3eDVd4hQCoqDh/EcV4f6iXzwQGwlT425nukLnz+kZeH2hZsX2T/Ppz/xlFeEm5lnm5T9Xo04 HjJa38cDzECpDWjQYuu3wCI/J3KedYfyuAAhhbxaz7mBrSC6jYu6a0GCOggOtD8HubB1Nu8Cb0A6 RJCbkK2esLkdiR6O6Ny4awm58DnF+hvlRQLdRfh1fwBq0BtIXl5lqijW4V2bIReWA5pjToipMPWK XqD+f8FNVVHW9WNO+95XgGnK5HLvCsthHcmG04GXkK1PSsIi/EaUBMKRZycxxCOnq4MMahReYuzA vm2nr9IRrkS0w6aZQZI38XCcSSLZEkFqD8iuQweFG2TCLeA6Ph0xkcHqAFT9x1dHns1Hcbex3GYj wMe/V87Sa5Q7zdICCJCd2RJAplu2YwyiwE21slM5X0LAbvk1u9MWqLXP6UyiddUiar56XQXpv5O5 8YFwa1EZUy+2MHKSRsjeHI23PZhRSofNNw4S9S9Bx+R9MYQ1oTXg4P4r07NlWSgA+M1n6WKpTzdg gVjHVvisFEDPa7oHR0kDq5s4gRs7z1Kg5zwkbRTK+bnLsTeq+7YqgHfoOdqFGVg8cIcs23sVqFq6 CGpzDombh1OZ4Ba0GiHWzBfsmCvVXxu2u4Hvyunio37yQIUgei8YaPy//Mcqr5Il7UEK6pAZnc40 KvrSMkmHnDzmqWFLdAZMZu1x2W+V/qukf7pgkVxNgSSnmmvMp73mNigkJU3rZnbiLOBepEWlJyKE T9r56kYZrGL1K9Afrv+hWwe+XixTJL4Nrt1nbnrvkYUz5irRj2HSNob54X4fOl3UKlZ34uqgHCrt q+7r5gcvMDjHFV5Ek0KyGtPlYpnMBFJuTwn+njVvx79h8yRU1UoSIQgxpKCZGDpcWPwU+SMX8LMQ yjSi4uLzQVGohOtyQ+SDLkdoZkTr1aFaWQ0LrKzVKB4PPxqZcoFrErh7QulJnoJIMx8NycO7xn4A cfeEhTOCIsTYb6qrh9Hz3I89f6lBAJIZ23gdCpJDUyuNfXXLYw5r/R3SgIpUvMDFt0YZPDPUAtRk RRBtQkzAxOXZ448iv1in1SykhRz8ey5RggYPiSo7Ys+OmSX9O5DKNgLgatIUIpp+9iPyibQ2C25d a5KDG03iOgouA/46q7yXwziTCgq9WfdxD0/vhwXwGNRVkGqWps7lFGzSt2IjXEgwmmwOxyQ8zVIY gp/uk32swcaOOJ5mFxrLT/HB1bgWb8sf72U+D6mqhAuLdGLwtSjtr6VIHjEv100POCmP7yTwRJNU p5yu3HjplmuYZbnDLkhZni0vwZAqFVyaCJ3RIQk0D2E4cZCVWbgniCHa34/P00hhdhyC0QJoR4hr 3SfQMjTUO996ntN+nv66JMLvpGHzBmEDgselHE//2wYcgNLguJX71uWKS0Rog+RVcOFO+Fa/Bi9C ElDWop70LDkWrLCHXGXKo933gP6lxVkDh8l4hjWOptr74Qhr2rUCwK0UT3qs+Hwz7SCQX/dbVwcn acOnfRgT5mg9vGMhjMzAOM+d4aLEoq9Z6t0a+yZGcZ+EDyUMczvBrrtSTdPi6QkvJCjvpdIF2xRT 9z3Gl/VIEB4eTRQhqDIoA0HdyRjc+3r4RXBZZffJbIhVl2CjTY0b4HiL/sebjk+qkPN5d1b/XcVL z8Kc8jNY85dmx5rwwm68m0X5CgVagnBsQmj44KHrZ8d4RAaHwOZcWzRrhO9qOESISLwOAl8t2QUx tKrR6ecPEZFY1sfwv+WCoNdfgNeGOBD2jpWf/gizOFGgRZ8w+2XHIRCzNbKq6eJQI0ggbMirb9Eg +MEgluP4lMynDHeXZ9LWu8cwRHbNW9zXa6+I+NZ87dKEUDCy5MlKIHA3QDxTpAXXXlkmwfrqQSas AQmxO4absXGmB5rhNYUk3yIcJp8aJk1mNJchjPpPvQwJkIn6uy0gFinfCGgMXptcw+8Ipg46Dfne nrI9eCBPNSye4nZsA+ZffN0DgWt0GYj4RLS8/mkU+L6Drr6KQwrlyd6NjNJ9qLEXJZyRmfxWFGdh S0F90H3CXh6yG+GKly+WeXNr5bhAub0RHMTSrdcxSWpcxUtd10eCB2U+KjmP8wYz0zqCjPmlUOQt q7cwvBNosFOODJuDU/q1M5pO7hbF/QXF6lPGHNNjfuH+dqetSAWeaLa+L5NDThf0IWqS+DEuAjEJ 7o30eOvW2eua6xYES+WnhfStLF/w5wy3FXlle8luMBVK2GfM8aBfTVeg5vVaCw64C8MGBnbcwNrT u/mOWtTt33bkisqAjomouNrwRTdfNavMt6IXXCwMy8Q/tYEhgs5JvlsmqK1sU3Wrt1dsyJVU9gkO 7S7781n2toiU556itkM5rAUSD+JDbuUEUOPCQ021oR/nAIDQgKRmm0x7H2FU7gyHX8oVLssdcmnQ wOJ3mOcjRDv2L22z+Hxw6ijPl3zw8sWddJPt943hWk9LCEZVJIxIxiApWnFCybh59xMraSZd+hFK 2GEYiULAsA9+uErdJP8LcnyTmb3kW4fqN1BLWfrV5Lj6nVOJCdZaf1U2uFUtsqRoAMRkGeb6gQrD GuU2azfT4BKpetEBABzOnAoDtUIdBPJ5Qscan7VLOoZWhXAQBsLaq+Lof8Q1HzIDz9Cdgpvj+Xjg RGM6Z/tDiVgNDkdput01vifq2UrAC6MVaDemS5HuY0PsWWhSLY2UtcsweS1QUwLkr7/xwBYrwdJ6 jartMsEpAL6zIV45DojyIudwbPsXEgKLWCOMG8/hcdG5ZEp+Y80kpEG5x3wyQWvchsY1FmXTZ/O1 mffeYSMydcJ22yhUZ1BSrii99oBfhmEKvkYKyuRNsYPGRH1GAvbBNxajUO0HD3gruzQ6AVnCE5ZS XEsofJGbyfExULZdoPYyfk01Af2Be/XI+67lu6c7WwfPFBOjt8TwvGtA9wNbDCUrfQIuvrAnu14O zCxDci90Jq+UkRDyVztIi3R/QocoMgwsHhKuHV3bRB0R8mCaMZhtCNxb3VnlTKOGL78lNnNqHROj Ipp9va42GSaE1hdZUsBFO9iU7wTT0h+6bIJ+TKh3qRngk1AWouJeSxn5QQqvTSSUhcKYZ9o46oir 9y1A43okbhh9ci+V7kCVfAabktoC3T+5nvhC4gI5vS1DD5DKiv7R65jnrC+1rcXVgBxMeCC/MH7s 2juFHnw2D6yCv45ZV1qlgf3aCeqEvTnwH5+O7dbXuEtz83OPo2hoTuXRlsxOmbSOePaTfMt+3R+A CvbE/vCSFkgqy+eHRZnoS2A+JPzxabMsukh15totem373ODW74loqg8JGa0Q3j6aVCkCcKXT6+xU uNxRcIZXCLeTiHPwAzujUVYG1Ve4bpTZypr6FuQwp8x8Dcz39b8XijlWvlMSIao4y/mFufsmLviI P2o8jmHpkdUy/7NGb3+9daMF+X4oeWn3wzz6WznS9EozvkyEeyC4Ac08i6i7IMfCFh5O5tC4dR59 Ll35YCnf5CXBQ+puGGrwn7g9fZelBrC613dMNGH6Co1SXu1dAyHIRrj+ELkoaAPrANDRnKDP9b13 sKHR36Y+qucf+Ea6OsQV7vuTmmYZXp3sd7VQNGugd9oND6vsQYW2XI78uy/kTvHY1OEwfkjcWwFu CEFN1gpH1Jj5shGqenklsGs/vq57Q3W16hH3PPH/P80NY5ocPoeRG+miRuQ14SrOZe1Gnfr3SDa3 l2mkgi4Fog79TGPgEcBP+A8zrfPBEZr6zU8qDMusxS3qDUxeNjhsKM8biupY075f0JVC5/NKQ1Fz h710GQQR1VI3CghCK79thmV684Qly7iF8PPm2y0kt1rw7e2V8BNT6FT652e1AV0zPdIrJcaB5dWt D12rtcQD8SoJba/i0NGQXjLBw+qUw0w7My317LvKBj0VuZl/iQd5Z8K4uZcjoC4pxz67bh9pAPkd EbA+GUW1cmsoMaPCPJXyv0hiCEZARiu4VI+l0te3YIuSLjlYM8++UtqVAVDdgFTzD7+6LGttfazJ ETh0Iyzw9qATlX3sW7Rvh6dnDDqgT+R51XF0TrQb5YPSCTynBJP/6VHKNUSQ3FgxSE0Q4D5i7Xt5 p4EITTFpNBfI2fD0O1uj0zvnSP8hwdAaMEPwXIr2QVRcAdb4Gsfzlr/k26+76ZE3yP4EKhoOYpp6 TwYCLc45PMvDlP2sh6ljaFtd+vTUplZY6R/y4TuqkPX3nkUKGfU82KKSRENtE2oHv/e87TrVLDuP rS+F3Dh736bFjGnXYee4VzUk42EnyggfLTnrAhXVIJWMt9xp0zAa0BlRJurZP8C01srRHCsMWGNe 3rrKhFAB4Bo/UV+dNFzME5DrkvvlFJntOPY0HkgkTX3fKowq1pe0ZrWzOmR8RGS6LYA+LS31L2u4 ORnAQDupPInn48WvjzvObuKTkd74CidvgHjkeyUO59bkiF9o04nb3GRKZF+VtsShlvelt36cqS1w tuIOqPAqV049UwYTPSKEjhEzHn9KkHep/znG20HcryPrABfXL17OD1AV4l1tRKkzTkOwMIFn11gV SU6kyRx/bfTwD83cT/P88DMukaG+/V5ibZC/hitDZl/hj8q9Y050i+HBXVrEDp4u7yUUJsBC0TU6 CbsNMwoxSuILDrQDJpTeWPpBUcvn3Iuxymt8sAqEGr2QvT5Vjw96qABJY5uE5MoBJVLVZcFOBOSX zV81VdfwHXBKzJX2J8XnJH+pRUcjzg0hYdwnj4dbjanCoGaNcBO2NC20L2uvivtS5vSkSDaWMuEB /kkhLnSF1xNd/8WereVN9mqwNLSMxcGdFZ8mR11bFTa1ZUt3hWcBHFi/hpBSrvn0YEI9d3xzUWWm Jndw6GrkNetZ71OsuqCRJmUtSPx/E5IOio/k6lkVFBaO9tiX3Zh60/VA040e6mZABIkkwGMv7es7 IXpxbOV9UdPhHYybf4tfaH/Bdx52RouGGM5iR+4Z5QkEKNLWl1UwIWd1MgeFjL49RLEKjiOqOgvB joVKGOpYBdY5thIo9T+qgiEchESEsUh0GAI32D6LpUQoTNu98mhqO7ZRDnGXTYSTbiR6/Zz3CKMt LJBDglRvgLIUmTmMEJg+T9e+0e1+RlOlH8Gd5m48pL0BuUPW2CJS0xad5t4cOSKGGRwd/y8vWqVD BmR2W49RPpb44NJypR5WixSXoOilN9w3ATSkeNmv2OW46XmmYpvLdflgi+zAPI2ahQXSii3gPKTX YusKFSO3JOAo02qMo0z5Ec0EjBj5iGQKJYIo/1lQrcnnU3MRLVWjwXWmObX2Owrk61jwJ3R/v1nV YgOECtHyb3rMUm+d8UPBcX+3vNXkECj6TDimag9S9UQXVtP2ECyWXmi8Z885vyKCE0rpSCH6sc11 cN4QG4Re5yXNF3NzELb7R/Ul9TuuL44MbvOq1kJzSBiNR8Qedd6OeEGOlXTyudOhoOIQ0jB+6zTy OFqBYXstR2DoFQ2Gx4hKbJidhzS7AuMu5gHwcFlTKgI1H3SekAuZTov0YfR7trd5nA9XVmT+lCKV X8pRPwaD7fGWY7D0JX9dJIFsfrJKxQaF2jxREXgq8zkqNhv+9EbyASGM5sdrM4WadplPD5V4fuJE FanaZ6/QA6GcicSkeuumnJRTFTWTjSO+1R4Z4MdxWhqvlwburxMGXpBltZoEna+OfLcJLSSjY4fJ kl2Qc2+/o14PrakKehxNd5HVWOlak9gZlFgx2fN2Vr6QKRklOeuc+uCjcJH7n7VDL0fr987meTJf 9mKig59zXKypze+Wub9amVWR7sOJg58YrGJLuT1z8hgd1XvvJpi8Lg9NkjeaP5tFVDoYz0JDKVZ4 +Qjj/RDEZ6HzfSgA5AvxIt/3zUHg72t/pi0/rDZSCVqsUC6zvnXTSrO79VIUktbj9Pt57UmX4SVP t7/6yYHhA7Z/6iGP85UQO2L1XPGwqbRVYuNJazGQ2jJda/jKPR6OljDv+zAhpEqv1u1xJti7PCN8 tqZWAE91c2L/zgfewOPbbezzTZ2wELFeF0WZK6C95PJlFpZFGL669w5Cbu82jgGpXTAP3/CQZwHP C5TCb7AxdKswUc/u2HttJoY8WsraTX/1zDBRn0wyNkRr/50p8blyvA07jabVn2DUgqiz8AltTyPK o01LW+ImHvyuLvKCxWM3mo1Vtyzty90Gb7kk4MsMtVmsDsaBpuAeGCQvpoPfD3R6X6JE2Dq/li3D Tup3t7ewpIfXSHuQop+7nEv6CZBKzngEfQc5NvGgj/Wf6Mk2uPdEPOMXBPMVE6FxZKKjqRZcflRE OwlSbZWWjqBZDXRR+FfxfSS9gQnqRvK4+tYm2v7VWKQBH3aMk088m+xzfj8KPRdO9TnKfHbgSOto aLKCQb47buo2lePTbZr1p4+YgCZs7G5Trs31XkH9Ss9vqbSN+ys6xYtxCDbv10T3EkqcLm2LLqHD p/SwJulO+nHHIgMcGAmb6QqIOcGKl26oFFBvzxJCvf14kbRmpFFN4wkZmSYuR1YbVwb+465NoCMq aOD4imDSrkkz5RA/22rLuNNoLjZsWy+3sTTacB2k51AYwNpw6EZH9+8JS+aMKsQcSITLZE0Ybxf5 ExEgghGwTFpZd0oAtgwb2oypnkkfjLZKp4J8vnTw0QsmvT8c16ShiHoGNHETRYpUcuydPZ2IQhVO YB3O9eNSy+y0+wenjb57khsbxn080syYfk9T8QMy38EovN5RPLoQiyO9Y67m0qDThVHEtu0t5eNX AP0YIgplVfwTxu5bKe/5g0H1V61kXyixQPysYgfk9E61WS+P4ZmdkegwfMZ/bf6jiwD4GlOQcOWb CwiaAGI37XvTdwq/9bIB6SK+l1pDcGX7Kkg7XNJWrVDyVGW1RXdY+lp5/E0qzWT8We3cYawdUqDc SVPtX+PmVCQu9mslMtDiSyTVb9py2c8oQDmzg5Uk0ibSAu0hpxz8pfeu1L1LFhuVn2wtypcbVPbR eHpX7AxSXQ0c7wAKuy3jtXIqXAqAyVg3dFh40vs/Fyosi+4S6Wck76+F/hmkrPsZh+BTAchAIfrN 01jDzYSdDxJJ6XMtKkmnPmiMw8rhoRnfVq9reNmMdR0nogGrCReh2fFUNQexlEg5uacXdOLOH21d VCjhQRQh2R0JlCeixo790kMHph5Xy3ZAxrlCMSRD88fgdukxGc5Y0lp4RY2B7P6zonPQ7DXNyLWa GpwUzNQHGIWfcA5jrKHX0RwLXEZOrFsVNS21mV0eKbhrSQOAEwTnn/99O0tt5OJgir1L7TZvnG+p zCZif+V66I8BH/1TcukISmGf68SjQ0A378XP+flU8ydFVrO3akJdjjo6xy9eSMqg9GntprLqqmHE Ox8NRA6elFPMjhFFssKGoU6b7E9TL6d5AiJP1o6JcglX8tvQoOG7iXwjqwRmDTBVlUaHVkdwxoim xZtGdwH6o9qtRSCt60glJNEMuDEWxGzb04Y3QJTH3BNdrDAfm9sYYMT+/6RB/32dquT0BwnYrr8d GkYUv/PHmPR3hiJHBdQNNwY6dz6oFxHkVhfzhgNTm84hJduKQSDSStFSUL3tr55MxB75ftGW7Ntd qEtEg3qhOaYFCd9pA17kDdc7q2fgeqnVUguJm81slNfDPIycZUlFboGTUvg0PQIWsVvDr8+2+1Pt k3s0YvqqEoIRAv7O/88DOu4Joi+QGfyYOXlyeyvhTfx/U9BykXkQXXmik6w6vSzsfq42u19V2ZBX bnkGt6ql++hQUPiXrSlqFtJyPBZUkIsAbhU7Z/0FyjNeuw2iXaJJZRmyjERRUBF3MDfWmJFfUKPQ jDWzwP3YKQt42rxZfZeuGncd6zH/m4yqqNk0kTfZXBUnTRI7aeyqE8p5vY2SnD3LN4MnJXjo36UE TFMPKyeSgRhY/3m2h8XxKt/IVgc4qvEKS/KN4qnyCQhoq3gznkQ45mZqUqQVVKzv0ntk67JY+JjZ rtVfprRRFMUVfL1L8DrxnzWcBAS2P0fZL3YvPNJlYDg581aW4bghKEB0jXjxM8fj4739pB/mDIGp G7OIlzbeU49NaACAe8M83sZnkCcUtW295jLhlv6HXHxz0TJHRWOT2+AvpjDgTVhFwqi/SbS3sTTJ cLA1DEASlZtADgNJazi+EIB4GVyu7Gtnum70hh3lyBnb4BleOegjrVmAZzE5/7Xftz1M5F3BV/Pa 419xeOuC0Qv/OWuayolXRF0pZIklf2EfMfs7G8Hn30UB1a4NNMJN080In0C70ZzliDog6GUhNWLm vK/h9KiMiSr7bMVuDU0ACx8s/iR6hR45iHYkTisNAiTxfXCGFv669mySVCiwrQj9CHqiuWnXY8Sd smdRsYZ9PZxg++qOFyYOtpO44eONL1KtMUR51LX3VgoO0lGT44YWKYA3TFuFwNIq7u3++YHBHSim VK2UjnCjxp2P2G3GNX1heqfxlb324XtADbaMg5IJ/LZvQXQ84MCuciqPT+XyjajubY4DV6Rv6Xi/ +Ng3S6WgNFCiSU/VK2Go6CxQ5LOPKKV9JmmQlOcCL8sSyXH8/K7S3nvgHJbde0efjpmnRr3VA1Fl N3krwpPhv15mQWSc96MiPXx74P52E6tRse7+pO0YFlh49MvIq/hkAspKAvY/HermSx+zikQIZ+jB BjHfQzAIL23pgo6VMFcbsGSnri74y8eOcGxv5VCUxNusXpR4sOhUM2mPgc9TvTcwxWdNRh5R2LC9 5a6TSq2oK6x3LKNMEFQh6O7QfZklFozfgcz5UAs88zuByphon42sS50XXhklBMPxHM0CLEqJKt0j 2XkOivIrXxuHgfIZ9q9wf6Dd7KR+oNp+uwWJCqRiAsNdyHP4OlG/2EUC8mvgpNjrQ9lzJ3OVQWxR UN72I15ZIYNAxE8RN3hQwgQUXi+iYvCvRTvY+oQ/KI04v6qM+TKfwGk//HhMLpEdR+9DvPuyxN68 yorPiq7Ts/P85M1KucxP7/S8I3ky7bmZFDJggb/EDPD8KwcgpnjIwFDK7LBWTcfoj2TPCi5LZduQ wQbImF3I65A4fnQo0MVwiwayQx2Eb0Zld3uJqG6E8JnKta/ViEbYhuYaUh1V0oZpO4GqAyL1NAUB fmNxOoMvqI1Z9SubF87UTHJzRawCePauBIYphQSbp1TqlfTz/OMPgrR+ayluSCmPtKeyD0p5G07c bOrpmDiEK7Fsj5QGWvHqxGE+iduU9rfoQt8KXJuKYUc5CRZpu0O57ImV2UmlOETSKmL31RWxHXFt A8+MKcTvnDijXWGgQtmE/XSDUlvvuK+LO5HgwKHcPbWhwmdtLPMFdFMXHIn6j9QJFYjSYf2kltcr sbxWNSCVV1xgYhVhQ+TL0uX0m6whautf8sE8bhhpeFpNvy473nh6vdRIG9lwSC/aRgmogLQNMJyy /GPS+UfVVSl6Byk/l3ieGrBiO8Tu/AfDoPzIZI1qbOfnn3Jh3jvl6QqVOSEyffoCowVHaG3rEcou We6qb9t2CNj6WdxnNhmHacha4L8nWdQy8Q9lk1Qav0U0mwvDTjwuo6X4wGt5BbjSmzTMgGIM3Aqm +ONMWOPMBvfBSfRa7fETKKHqps3LlBq5j05yZ1zledkGnwOiF5rrXwNXXxfMcPiyUsgzMFPx7yHw IdBqfaIfNzFV1cR3HbQP5FnBceaaAuQSIJRviFoQYX6d+nmRAdJ654RL5Cvrs2dAqataQbMR7cw9 o9csFc/qr8sdGdO7GDsySSIxlZ6Nrf1HggeAA4I5k+Nc8HzZKSLkFaImeqdZ5saBbGyRY0dJekrs RFAZFKSRkcawW/35E//ONM9dupksPZoDAbhClQuDXjrmhjeGWjUKQ7cEgqIVWjAcOLDoYAnLrnar OU77vl3sruK278KFkgPlozxJ3ZnRm8u0QHfsZjCheXfmFDh/rLL6MkGlt/oZFaY9SnsgT1M60fuK b4jhnou5hu70ln/8Je5vwgF6ZxEjd4fhzHinec1H9uwQObHfXtP2SXpBM94WNWnVRnaf02I8TvBf QQ5OuCpBfA9yhefTq96Whhkh6zfau3SCTkYLlcckJTY4pYThV8h0REQMRk9KvcN1UQa6vKzhr1K/ S6rgrIzXOHhDv830Il445uNNQp0/bOZKJyscTG0BPxujVnvt6qEmKbHv0Htw0DfjFT7NGInIlZTG uFZNgpOEaZPMbxPBvCahI40z1tGRd9lZ5Rhj/iHpi3gKklHQcINafKxeUKw2wZvIdBus6IzDlsSQ myO6Z9EpUSMUca0oZKAF6xcSAfLZ7poHciP5hHlUPeFM/SAz16P2nWM8gUQFY7lgWub0YIOe8o4K lCcL0vog+A7oDO0smSn+j68TOxqRdgr7a1TbFh3g2PVOA4+DrnAQN8wVBVz9BdKpAsoroKJlRPLz rOwNL4tVsc1DpmaimRKoUdOWBZHfZmuKolGG9FKrlwIljakEkTrUdm9R4/DCUKPDuYY4imq081ri 536zuceFufZUxs+hr0PI+Mq929NKBuLJO/UhI6hfQvEHN5vfYLk9TZhR0YlC0rU9jw36j+Q4bVdA dxi+Rs7ZsNbYXLljhqT26NdVKxnysMzGkkhm5dXFdCn4Xe+TbGANZzDK0cLOSrrwW4KZnsF6yOHA GtgrGUfHsUqOPJuTaJbuNP2AnynZBiOkCsR3DyrLcrBygZy4KjXn28t1iYhsgb7pgbGe8lRCN4K3 r8EwAfQeWwa72u0XnJdddmOU3J+oDm77i/HP+uETaxYuCiJ1XTGGGxvjYI/HtDv4Uh3o8/pm0uwP ETYuTGjdvll1lI9MPtDrUBij69jnnG/0BhTC4OCXlOb/0okRaT8nz7/WQqreGFaKWboh4yxmmiL6 2P4Ldn3pvqj1DCZ8H75DEuoTCm62JWp9gpm2HWAy4wgCV4i8KgzojZu2GCcQ/SmcMkxF2FxbEWS+ QSIixHgrH1n5FJpQTMDtcgXbm/Yvhx6rmCDXZUaSBAlcEeWH2tYjvVn6mZQFtdoCHY0t0wazYLAm d+Ws04xUZxZDKr72NqMuJfv5SGU7gtiWjgEskBa24l9mSMb7dmmIchN1BxdUGhQMsBQlikrej/Vq uXLaoM5NT761znLD+Hi6VcZoNVRuFfJNAvGNFZBZ7mC57T9EgzdKtQGozGIZi8EZpL0+YRyGJ8zl aJAI9fKfqkLItxrGUBGUqG6zWlVyEFCqHv5Lq8t//UqFyW4/oV3Cwu/jz3XhRStR5QGJbAXpHNp7 Qgq1RQD8dcWxJdMw3g7BtuEWJMP/aZlFIF78wSIOly38JD9wD5d3jOWoZLoJokQFLbcPiBaVZzvd rHnluMUPAtm6jCmCG6y+6mWULSu+zdfd+S6yMh7ONmax6a/JcK2aGjnpvA0gZZdgpKya3p0iCKnA gY28DJHfesfBA4bVnoonCrQ1rLWQbG/iEj6yAK/sbVKWQ11Kn19TQBtF9F/bI1bhNXjyOBUmpI9B 84ETwOi3NNzLiMq7YAK0Q4v8wk5tpvJRP042QTD4MERv7l5VcShN0kW3GV4JzLMsoFBth+bVJwgL Uizi5gQCEQMFJ3bt2P5Zld+nM8EFvF5R0DlIhZdfgPpLwZesmWl59E9LRuNcwDAeHQJNJzLSxfRj tDHX118zJ7jfwBBoLq1KC2eJWhRnnEjgzymosoSPmgE3iTSzgAoiGgxRb176nNRPrqtUmp6nw3L8 hIkjgEJNWJCHmPk4HZrTRPWO6LRAWE6gRKCEW7PyYsgTcuAnXqjvNcZ/lafahKqYlDWH6D4mywJD Dtg3SlVe9opZ8LMCDtvo3qz5K0W+jEnGwlzAQOOvGedMPjibv9q1HFrU7D8Ay7N9hfQgDBLhWID2 9Moy+fpyxSIoZnxjk72rw9+BWK2lrZuSa+nvDoso/aMI10wmzFzkECb3cHMR07f5XGdixkF/3qYy bqn0nZEzAqqBVddEiXUbaXxuvmj5MoHsnDzWMKaXsNPnYaeD2qFcqKN4R9Tzosj48ZxLgJ7LZhy7 AB6+A7VgSsRLPEA14ZDVZBXkyOYHGw0oFTRaO5dG0+nV514DFZC3f2YFx4IkXSyt7C6ASH6G9Q9L Enx+gwBjGNY22uP2qc6vE6unozuZ1WUuV80VXHiFU1gQ/0veUoxhzgtC6FDIlTGcYbduSEPDqQ+E OsyTi6pSiRBYlRe6g4XWKV/74Bcr7YiCL6RikxAQ1v5UzPf34EPG/5ZsKQxS3IgDxukkZNa0QfS4 CWEuQDmfQ5gjHCGaSQqkjyvCNuWY1RJTXFsy1f+SfqUWHCtMIT5CiXTS+UdCUx+o2FEoz41g72Zc rA9gbc+dsYUDiN6rB60qvFjri5gASUD/XkLQOorjivoS8E1oTrt8nfci8TYbAqpMXJnTlmV2qwcV JsYjnGkIhFIOIz5tf/1q5OkdLUd1Jm1yICxN/LGu79fHu4HHLIkW37rkgtgVq6jSoTYPEjFvGfd1 C08v0oL6pWk5fZI4pL5VOXDXtyhBy10r+sA5S/TQvZR5bCQS34aT871wHz0gxtVy6/NrGiz4hvwF vRgk9rnrqi3JDxtxkPdowVUoK4BeLjxjO8fBs/Tb1wz40v2Ep9VA8jeZpX45yn1vm8BC3ThCCpo+ PVVceIptBu/JwWXWh8R+BJYrHEkJoVYNxQAaVelwPm9ruMRA/BhzgQ+FlRYJowOAVwHSG0uyJ1WN GFZKdIPuMFE5xUnskaurGYdmzZ0rVUp4gljeqoub4VweaB0V7HSGDp6pETVScKEUCHHZlhryPTYP LNqf4fX+q7is8DU30BdTqxL3syOgA5/PeYHT1eVFTKQWrBZ3G+DfQlHaPtPCm79OUOAxAEgRf5C3 /d0+8B+a1R2srSuf2xQIJdkBqeFqOvaoHyQzitvQ5l3sGDg46hHnrZempiCuxowrynodSikK17jL B+kdZXuaIxCt6cIrNg0HsM5YgDciJqdZBmskAlpQAVIONXVmSD3oCz9oMrzGikJ9L9+v0g2IssUF UIRt+JxmQWMqzlz2Xg9Ivh6sPugV0QgysMEBgrpSI02Q/I41Hp9JGvtUC5qT/0HLNC/qi3OTgUeq ZfzIlk2bsMciDZOzNv93qt+ddD6vjOiZJO2FAqW0A7ytPnfHAiyPQ2u5wLCbOlEzT7sgCCyUAAYg aQwUmId+KArvchY7fT2P9xbtUEi3IKO0hFUilxMaavAUK14n2TScGzDBq7RoLpobpE09rvvIMhlv as7RXH8DBuOWiBwkLJNuCpQ2Q1KZd183z1qx0MrOksK7H63FDXibVT9Smy9Upz8w8IvPkDwnikqT OpO+7ZHmc+FKzWIhcAkNAn/SWpf74DmNvq4y+xCX9XYQnt9wn1X/K/ryKlW5NAW0b7LVH8I81HNm pCo96mgwDPxK+H5ZwXoZjnYs7ZweoppBCRKcYFDtf2Q2rxTPZL07Xvefhe+QVY7jZ+45ezj7bzfJ gG7asvESw7tofOtR93/LSP9EJRLVHJGo8wh9qCQZDYUQAiRS996ceJH5XtL0kTsaiUvDPiSQDYmp nvMytnVtuzhZGfeMGPnzA3iSGFVxCzqhQ3YD6TezfMZa29SlA9n7TMS+3qItiobjs3J1Bq/rTDMr OCpTp1bFHr9Nm2goOg9+lDobF8e4y20vzjGYotGbZGjKHlqfIfUZ9HmFPqQS7FPkOJHkAUj8a/Kh Li7t5l814ocYD0XA6hNJFR5i6ZMrdK+/g2ReRzZJmHevQQaiIoRsZQh0zATihlXqbm17nHV3uVmH HlrTeMgjUdJLOKkW7uD57j6VgiHplfH844AHOxQiL+MchRFy74ojSolrUUzuSpM58VbHohvk0+mc noUBGlatjndeaj3er/EeTmcRXvOLVL0NfnGZg41kCGR/43F5yv3JKWI8vr9ZTp64+VMG0yJs2h+X 8BvoSHGh3J4sTNFHUE+TvuyV1bwb9WDnvq5aKxUwCzRIgR8x63xbC6xVgO3HGtH0n6/LczcbIGGX VC1/GFJORg9aZ0KqJvGJYaDlelovsQMFg20uuo31DMxsss4nnJfqPhPH1n0PEp4NhMsFtXEaC7MD 8uGLcjIh0CKkqLUZL+Naso3pTOOTulpF/4QlNHK/yf/PKf+nVeTrjrDZzG5dTp1EbGClmrYSndc8 eDjWa3+aRgpdfkz0/3osEoMwpcLisQsoW6EZb4EoOdhxoyVs/yP57VdmaizOGrQssBDLeAuwzrkA I8NkhBe+3Ede2O3gGeKSXgz4Z5swG3cSCC5oAAymBhVRBBZswts32bDhB/CDWxw1b1Adim+6FvAy cKWHFChdODg4Y01c+Jm0KGDu+IX6Eyd0dtbtoRko5/g6AvHp2yyb225XM0P8pNKm9fKhIhBxhxv+ lN1xdlzS9v4FaKODym0QhBcfN18nYIUN8QgdQjrTr6dWSn01jQjWjBrL/ibpR4vS4oQHzM+EE9Fr Vjoa94Vad9qonL0hmIebAMKeFajARQY05YL/mTghuqtDrdEPq7F+qFmh+eIwK1XP `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 8096) `protect data_block L6FRAasmfbSpOrRTQqjIWn+0CMvDOBUCOytxE2TNGKhoCXp4/4T/y3kfG9M/XjhHnE01+Rz2m5jF TOgOsW8tDyoYzREJ1OZnR3xFOLOYqEC6Ir/2ct96WEWN8wsXW9SirJO3wpsLhDDKUHKy9ScSfzil 08dbiijOiB6AdM9EUtZ7xZzfajazGdi86ugQK7+qvqQU7DG0/csPAsGxNXwh9XM8eBLVPK3vbetd Ry63gTwGmyIFeenRYEvuzfr0ahPTiaLBWp8sjV7Q2yM0PHB9OLGciYgJOvzfP9/qHz52/zjLtaBa ThPGcXBsNcM/RLVJYkvciZrYMD9tennFnVGB7+H4ONtWcZ5/WdIGigRr0wnMRMtFOvGwWBk5ZW5d HqbzjSDQz4LxDQEZP2iaplpzifszXYSwwdo4zAeWs2MGxsh7TBIBfaKUKe7LKPPireX2Uz6kkxZt ZDrMqCwTKF5fdA/CL24G9fpsg2bc+CTQc6QIBbq629KUXFEs985ooinF23UoU92xxNHKtGwlcYnM eGSQUk3MpXUBN1JLD13ao+/BnrTB1lIGIjwue9YBi8Nyru6VhCfVjF60WMNUO9F4x+SY8C1V30xA qokiiNipJmRmBwkqpDUX8iHTMPq2gFrO3w1gK1W8TZnMZIJXIrAqh8n0wASz93Ob5hQsA4U8wkXd OkxTSlWFDNko3C073c6ceYDOXPK9H10uhvRLao9kj5iFInYVyRmhJ5bPhjhJex5OG12Y/JXcZiTT YeGPkCnJ5/AlVdLgarZFYVc4Gi6z/bje5wgo3HxHZspBqRwQaLNACOK+TSmBJw6uWe7XxazCfoeA 1RlCUi8b44aahWZ37uoBRVltCpJ2cGmEce0mxBX/XxmyWLW32FfT09f/E5cQSiZBhQ1EmaKauF6P K5msfRDBikfQpTrm8ClmW8CqitbD47c6DjlSMgpK5BkbIdX2i6nTSpoQPam/2qDu7JDOy8737/MU 9MRPhwCqD1rCN6N6URP4Umf1tmlqKRmcBt9gFpv6CYgp0uKBV/SFFXHFRcfWDTLkgqxla7b4/+5S SMl0NfAQiIpg5bfJ9dgBclJOSNNgREgHDFEYmw+vGwzNyzF1S7hN3LGukzHryPrrcIHYy+Gx43wq OEXipdudLdXLgYCX1Zv0x2MOZL/1K9BwnRfPfpWyChoNe1CgaYV69jpDhPc5FOoTkwSc1ItldeT7 J5IBm+cx2tLB2P3XM/4T+oZFaBRvDQS2VHR9ej6BunFR+04w+kHGuzUcK/LyTOy0NnPmbS/6VIGQ r5ANHvynwLaQV4qiXR8fTlU4uQc0IzHKj6FI3H8rdWd8Y+4BI7Ig8ziENIEbxbRM3ZoVEj0KJ0BD n8eH2ohRcdyDGvYqOVYJ2Tjd4tJOHAPnNtlvjrh70V/WNyysZFVqc1AZ4QxwNoe+XAZYR20K/44i nkYKdjKp80X1cjXS8iBxjG2GbBZI3LsBTvRyqZsQWYtyHnWluB66FmD5+AEx3HfHU3kPbNX0IJ4C xhC9oitQCsQ9rgyh5Fdl5fmHX0nIcMh/Z5K0a5Cnud7BcnhRaXqkrRdWgFUtaqvDCsuLkYA3/S2N Pb47+CrUKad7v+ochkH2b6p3KFc9MX3+vpqWHqjbbJd3wk/aJrBGDjsHpq3wiAuBZrsrQLCiq5u8 uNgU++mLsdp4o1Sc7c23oACwXnzBkNzrrcQTR9ZpcYYBDG7LK+bopGuA6fPioqm2VZJ9fT5U+BfI f7ziQJ+HNzn+cRjUomEj3Tkfmz/5X7fq/iq5ha4tDbsOQO+0fHcRxvK+GzFITADhpnCM4p/wp3gq xB8VDCIKAJPqAwtRWkX5BtURVxGEfU7GFqMAOUgjE1b8k5MJWlZ9t7XLH7c7krSNwhQqz82xNb0z K3hieXtHuKB6ylr2hFEMI8fVHGZ6j07q2MrVqtU6mv6y2FdHlzMycrkINMQWH5bLyHgJst6c8tm8 gubyJBMOQ4J52jIjaYPeZiuCgV3KBnlwpKy5pOlEwBMHI1OPSmQTuAc6cyv8vNSzP4M4ERS2i43f kVhv7ZAzBsbfB0datQ7R7UDXYzIxZY8/5WIdBh5/gUjJOXmVyrftMtSRMw05ksRE/LL7pW5gcMgJ Od82wSQJ1SYecKQSJT6ko8nMvM45AV3COsESZF1xiOVs4h6MSTKmSxgNcYgeKHi47FdyA9imgb8L ZD6uSA1xUKUqxMbir623NNXPs0dkYQhOFprHC8Ipexp8z+0kkBsdlxEaBCddnnmqBPcx4WmVW1/5 Gw9+0BSLWVDJvccl+hMc9C42d3kP7JwTJJV6vxp3gN2434fIaDo87Ic1urXkYduK/Xo1NouhgXdW x5o+EdOcoK38nH+IZT9nBOo6yV32x17nWNXXHtTTtQkYwZt/KmneME3WpOYxknVro44qprr/Bli7 d11jMwsqY5JGrakEwL/TuJYFCF0UmcHH7HU458pNC/MWCbN+cv5oR7zISMz5bhIqE8Ad8xs9kpX5 rVNfZXZw/wtjw0y3dRHJ6ld1fd/E4hgNVvXLM/FSC+WYASWJ9ZmTpiu38WexUiuFVm2LJOH/eM3d LVkRM4veyTdzJ7DOiy86hfGUWzWZDuVxMg09xZyGZFHAYOSYFKTs3benXHp8hmm81EePaT8tN2Vi czNu/gHaoPO0x54MEo3CHi8DSk4ilLY+0mXesSMHVJQMDo9ngr6f3qls/EqA25akQWW490lTix6J BSM4NL1yQY/QId2XD1HmHhuJXBqEylrKdsHtzcSatLLtMwQCW9a5C0LUawYoPlQH5HNZyjugcg1M 131CkGYd2GRFvI9nRiaHcUX6RN1Vl2aeillyu+hEMIUy2uH0TQJLR741skZ5+ZUAGu8exSX5WBBk EhkKXauu8NeSEEdBT5/xJN3DSUisO3tb259H35acdM5kL8dHNoIu0jWr83e7BzOdkMsrKb2rJ4aK wneX4HcyCDAC6bbh8ybccgmlIl2vWtGbdofSHlwdTg7CuWylc6ece7YKx15nSL9cUxznYbEymj/O MlWWs90WnTrRAmckScD/0nETZyiw6KmFgzuSiPRYOX3BvBBCVVBNzBoVQDwsBSALq/DHMkdJNN6o PyXgp56+H0mTc8bt2VHdKlF+tXkVd6ylI4jmUKIG2TFMemKr5W/xo4NoweSxeDgWZOe6sZFA1Y4G T2qAiSn8VsQqZmuA+NzpDT4VQK/GY4fal5P+TpdGxGu14jzHUoGUCBZQ2OmGGFxmllv+OCms1/bq TYC7harcXidchzVIPuCP4mAriJzSUqiHwd5Ddpf34N9U5gaVDR3raTCFmWfgGTGQmKGE8RszlY2L g100vz98DOtSkEWsRvjHVhvxgIXubhJOE4WzaOg6RKGMZPpDiZybnMQzn7fmJkBLY4f5kBLyK472 VkT/bbW/oxoBq5GDW0KEWc5iazehmdf9kfB4V5UBoYGfhdgmolDJkZWzV6xAZq/jRmI4V2FkvG3R PkwEhNLR91XYdEIVlW1Ws8VmPUZnbN4rmSQJhPJgfjJTQy2ieSgwUPTGqVkKk0+Vf6bN7h59o8KN AKC1VVh+7nIgk/SZSB7+lgST97oja0DsILj85HRiUyABzV3i14TrOXDuU+uuEypPPs+nph+rfteA w4WvZSoi+NpYdMPFXCjYrknIP6aX6/yZ9pz2pJYM3BC4zj0mlorozI1a/I6a3/9qIZhsE3gyLJBc bhJ70anm9twgoAhybhIseTgeuzsGzkmL9CrKTv/W0bt5s3xufHL/2YJ+rHNTcxERvKvJmkyUDY5T US0P8qOsEPER2MDw5e6KFIm3ueTaUH+gOTOSTVBrPAdIxQ+XFIbcGzahSPvTkbLVOVn5B8ZaNSpe +5ccYI0WYudcyGlqb72RL08GQxteG2FN8cYrn0d0Epy6D/y2wt7h/3b3InEzbqRaOkZEqaDuvsKW MnMcUlS3iFVwAl8Yf9NF9GgcxGkBxN5M/AxGNxEfhptucaIPKsrYioOGv1CQ+e1sSrdJHr4XznYn kFO4cALRKQq1DCIgPSGnSa1e1whH6LoAw3UIQOj7HBn285DN5ygNn9NSyAi1bmgElwQ450Qwg8vt hejtpxI2WHzd+jzm2TYWDx6S11xdpMaE//StMNXO4yWuwCMp2aogHrJvO0ItoOVxChCLnEjBOVUh K+q0PFgOoOCKQHkGu6zMdVcNuewO57LucRojWFg3sZoIGFuZY+gTclCPATDP8QwCk/TUOA61A1Qo Kiwbcc0LpCnuVo75E/OewwrJON8+v0rtCDim7/M1Kb9YLtdJhxnWxBgqEna6oyYNJrzfF/eynd7f cYgo+/db7LD90+koIEV96nXXMPPHhxq+fwjkJpaJ9PzgZpte65zUl4mCimV5a05kxE2KOEp8nSNC LEUhlumiSa6kBGeQtfQZl3ebH7P9Nwap7QUatH8OC1LfGHPJzq9A3PkoCypGOFzzvRE+grNRUoMG jQWhoFxOp6rW706APhuZF/FVsPxpCf/RlWDdqQAtP+xEQ+wpK62MN8G/bVKPjCuTx2FGr+zrKNO0 dqPtVaYuK0IRyZgE8k+zcDUIlXQB314QCxiBLiaXKBcl2H4tOOWg5kTdO4BhS9eUtqQPzf570MSA BH2CmBJWkKDJaBOfhunYFABJfr42o7zYAk3Hi+T+arLK2uKcZ8tsYqe449TYWq+j5UeQSN1IZVlr ehdnzf7QSGnh/5qTFWRoXUKYPtm1Vu2vu+qBlTkHUE0OdhzpvfEJ99QS3grAUTGVsHfAMnZvo/0H YEDyGr/JUFAgytnLXhxg4CdHZhozCd4nFFaBzi0Gao0lPEDzGQ0fD+JVFcW25QcNAXqfpupl4GBT sBtm9whVq0/jxAWqeYVUi0005+GqgqjBMPGWJXXh0A+R5PD/rDwbw7ETUkDKLhqrSWv3xkxB4DwT wt/CoDfC9w79MOoDLIOUzaiNcEhGjWF0Wma17c4SMfmYIdhh5KVNnyNjnAQ7qNNjr1UQAj2kjJg8 zg0kIY1API73RMWV31hEu0h7Pwm4dh8Qksx0xTXkOcm9QpDc3h66qLh+buhufUNXM01un56GP+mc fmtdRPac+Yt6M97YF+NWP85KOKJHMtRX52MYk4O22B5EOkpmZB5jWM396TieolJDzaylrKeOqgIq vlGDIi6jh5Jc841OEnff6Lj2mRNr8Dt0gCw3um7B8bmLtXr79rzUtN+P8L6zs6w/airtuCVyP0rf P5C8sZlJOBwhvligShEZ/2XStNG8Zx8L8kY90Lrr3EXsm/+qYs97KaNYU6CyV6/04wzwT/3qbJjs c56ka8iEVzMyGeiW2Ovmf5Tr35cr07zqbq5XP2rntGXDwnFB0JMsV5Gws6Np7Gqhiu1+rZK+QybX BA8+rPJtnvMrpHwV6/9dDEDhfVYI8Qy/aFAbqdvQbq2wi3ezk21LnQdEekiiswbyMXKHtFxRNMXI b7lFW5IMmC6d3Gza5qehe5b2S9dwqKjUNJRfAEbyHKUwWLvqdeb264Ldo3WYp1Uxp0qSIwPF6PcQ +GAekN7xX2uY4TEsVqK+EqC+DDWbwYsyWNEjBhLVnwHmCJR/ib5EPvLgUGasWmK1hA28wUGxjDFh hOAhHojW0ok+HV0daNKUuYzND1M+DlXCbDmGDLt7aiCWbltXJ1wkVIxjdPhvR4RXwcUCK0ZGUrQW w7VicwjzNnPJjB8vmJI1Zo3GNpF9z/1mv1+hcxq4Dfi7OtLqTfcJgIg+Ztch5uQyvBPk9IAELgIe xxbdMoTqgkfrIg/R3rfl2XKKIAhCThg+sMtEjk4wfZTE7jsHaEOTyrgBP1BxRBsJvs/YB9qXTDKP 55xob08nPkUgzHt7H+/VP36gI6iLem8cX5zVUnZzrhBXARa4TMKeKaHCVx2aVP/kzFPIvcIWAkgI tQfgE9f8hi4sfXAqbM4nIJvy+Sa989hXc0tZleiWF1PSC7hDUHfC8Hr0S+nJfY3HQpjYNxgNsvXZ VUAVQNpKIRBghbSxstEqxJozUQRv6wmWlyYVyKJPHlaypvWA6U0bKMxOHKOURVreRP/2btKZTP9V UFZkdmQ3+Y9GG4b+yFj0aaN5gIR3K9dkCieFuS+F+vDB7GXE7AOUDiT1Otr+TRDt9Bvyo8CmKX4o E3z9iPPPxBvTWqCXQQcsmo5fAk3GLDIPh6XIr6qVBlLDUVd26EAmFGeNlx3OOR4EdjHRWCV9IJtc 4aUgjzy1TJnpt1bIYcKTbav1NSaig76OGx2/rJ080zc9FzQ1GACLqdIuz7grQ8/I4TkjXicwOd8O gpDwDNyqC8r6u3emHqItSIiTi+9YBr2wfc6aEs+s5S/kjt8OOSORAEO/5CM3KMTjQhdlrLutNQF8 Gymd29ByadWNCjYz9xlOQD6oxavbcKcI8VwuN9xYL63w74YM8EIidLv0aA+MtBvY3o9x4htbGKcF /VrovJDj2sBQKmdC6ILY6/iy1fpn0jSvIklGsaH5gTjERdIvv5I6ROp1Rz8cRvGISwFRYDvcQGXg AJtwj4e9sRUD2mzMc6ve2DSokr81jgmXxwvUXTfBSE26kNEWTTXwBT6HMIto+ct9tzcCuAPiLLXN l/7oNyICXfoqsyKjW9Zh8203wCAPEHfLt5q36k/ty1CV+AeWaakoNR95fgakDoJCwxsXzJe+4i8h fV+OGG5yJVVgaHhGz+1Q8zcw9O9yEAkU/pxKFg978zz3CTUpHFfphunGj7oIAqWM/yNSN0U+vrhN QnoWy9/2gWsXc0641spIe5UDMDhYls6hesO6TJmvhJNfGLTVvYXroVadfn3vwCBCX1GGQs/7FbJG zWS7NzVeFa+TZB59186F9qJk0LP7sEAz8Vmz8gbuIS+rn5SWOqR2KMBUhBg5WltlySrLVAkWACnl /IV9vMvXcTKmXz9Zoq3W2y79mFWZKv7cOwaAFL6zeHGmLdsEbiImugU2Mh0YfVxXO0pw+m+veSpz EQDRQIngQc6Apzkb7ZxNICRdHC0BxeYURMFSibyAiqw2rzntsrevF60yzL8etRnNR7ULOmD4/7tV lsxXpvoTFnn6I9d+VoZ33V79INsGXRPjMngcIekLKOwcqyXfm46xpqrIJNbId0UR7LTq/q80ZzeK Zla0LdKQDxRciHK3NSp5GVjO2NuCMsSiceCwmoPsWU4Jzi1Xl6j5oUnZJppXf/0AOZ6QtcQEz2Mz sI0z5tON/GQefGQw8TvkCF28gB3FaYSnDsKHP51vNZorDFUGPLAEaSJt7fvciY96zrcbwzRpq8vu hDwBz2dOlOCfrDFb1NvY+PCSqrwg3z6nGlhV2LxZxjqYrC41tksauODqlxqao6WR54YAuAuEsnc3 TeB9dvGwcuIw6ROMnlkYz3FK28u26inggnPIQA9cE1SKT4AdznYG94FYjynp3pyGQvF3Lci/SaP0 NNUu+QLiyXIBy4/VjV7bderDoUHGt1Dv5kC7D7wCr0CazHgrv9Xwh9Lh5RQUcq86djvHtMjU4ENS R+OyremPPwIdvl88ItjD9aRzNnSVII0pK4SlWIDIz6wP/Sfz6fE+l4quO7tWEi9eQ/CYt8iMbyhd OrglJsiPYZzPW77ouRrT1IRPIgITZdOHLJUenOyQVP5qK5Axj6XUbUOf6S6uxclsi/6A9ROoRuPO 6H05G6TTNnN2ZGASSmoSTK8e5UiMh2tQlaD+WZUjWfZXMWqQdyIf0649pSEzrbjrsosMA9AyF170 jhXgwNgfZd14ZoB86T/uTGmtrKOxBPD4wXUnHxjrEW88cR0dn7SQYxS3B/NIdhObqSkVpO+l7JCK 6uvzFbj7Psa7d7JAlNaobr+Lt9iqnCByHvDgT8AjpAH5r8Pxr5vMA9lBTc21LC7DQTcxGaLQFMbQ sRfIiInRzd/NDev6uMP6COcXHnUDa0yC/2pCvd0Dv6s0UcimU4yyh7p7gFQxxbP9DxU/ldiWb9rP CTXe1j7zCxnnI4mvNU0zSawd5X6JfUssHmTgvbo/zmBVP19vrxbrDWzP/Mir1FBXo12alMFoqlOu B+N0Em7eZ698WwqlET84SMUsx1SlyhkxD/c7AiJZuAWXG593kgLYWN7u3UDX5nBTlaMLWQRIYt8i H+cjAGIuT+CTkXWpxXuKV9fOCR0KkZ4zWsL1CcmfdV15R3XA1+sBleThRAzUeMmZsYHzbin1J3P/ +kVkiIYIxuXybPTd0paFqMccO+14AGDvJa1hbZY6b/c5FNUJ7S96vqadiaFv7Y7G4jV/1fUL5Tk8 Yv3PG9mTPvGnu3Dup3/utYE7hyuFR5NL96jPQz6tMTJAPDKlH/DFRrF1SLB7lsbuurN/b2hk6Lbz oZnyawE14wPjWkVrwWw80K4D3bQqKHlQ95K7uX3g0ablomBxR9EkdzMbyxP1UlIkGz7Lhvr0y4dl p9N3xNYzZ5WXltoh1ZdTso1BKOGJFyHMNmwKY4mDKaSFgMi4LkVxu2C9C3soAFDyZyy5xsToBpp8 b+/aqTNqSrbfYVHlbbRPuqWhIGTV5Ia721H2J0fl95aWMfwxa1BmWDYRnH50MwikAgkJIRFoIPRF 3n2VIjG5S7m1TphOiHQ5TjfwOOh9AK/hWQ6xfDqS9/sXOKtqaP6WbWNx27fphMW8HjLaCZpiPAiw lnC/OP5c4qoe39AmjzrP8149rZ97xsUr/VfQa2ONvQsf+SvjRcN8xSA4ifIrJMZAFtp5SwLEwGoD 53LjjNSXCxZc/21T+55IQIbfatMlwbBW7coIYmEHlIOJnlVWGSOzIdEALddMUeN5acR1zbyAbg8P fblj20Tr4YEwJJw1N15Zymtvj+X/LLNbMJdvlFTNIdIDx/MgkeGkJK7k7USCLXMJynswPB+8Jwqv yNli8hT9RZrspVHkEyIljLn3UjBiu4zAUAByn2YocIiWU1o/3vchpzcyISKt0xP2r7iaN8kE9LN+ bIv6LT3tcVEOTy04onJw6tDIuYXTiZWRIgTacdv0Ysvx8ASr3WRbck6XTHjBneiPkLpzKs8TXSqX B3GqpSzo/Kd+fR6/ai22226Riw1Lb3JJbSiQPoWHQq8zm2/P7cXei7mv/x9AdWQxlbqIq0NQoU8d FuICw6t3XOkJLTyST4jQURfFQrX57dFPnsmbHpb+3W8PbtcJ8Zq0yQv0pQXV1q/xLhD5svhasGbP tDnwq8jtw1BL8RDf5TsN+LRqMDs1nkuW8YhNiHOjsIYqmnXfOdeZPN/gnb92CrBTXdrvKSdoZV2S 1VQCh4ETz+JMyt8/LoDx4bd8cqrV9SDi8eiPKsQ9jGOlT18P85iH78hTTR5uGHY6eFxj7FXC/9mL Bb0FC4Xq7LCy9pNoQUEJ/jUxE8Z5eQbfB4G9Ed0OczX1bvOKqoc073Ke+ycKD3TrKqC9zNvMgQ4I DjtGwpeIj3DbcQTpwkptuSokG2VGwNSj5exrPGJ5otK7qC5cisqNCwwikjQ9Pbw82gfctphwvXeX 2DQF2y8mauUAZhNXf1nsMbD9dnPWmbHcb5JMVp3/PAM5lMVftCQfOBDO5mAa7+o+tU9MvCQCfpnx QbD69MTQ8DQGoCR6KLrFu2Hftg0RW+j7coQDDfLYWm1ehg0NKP4+7WlIKYXuIZf8mQYc7VuCGdzJ rHMY+olH8D+u4LlHpRapxdpHaVy9+h2fgHTI8fSMMNqbJX78E5kIzZ2tDUxEVDP4Sjh7tu6gXplg 13ewIyjS6JbGiITsDoElqTC/QxScsujHJ8/q7C642dIS0RCA16q/MSY3bV94m6z50pzOy+1X1AqX aSevtbDnv3Sns1Rhj0IOWia4VR15UwOm94PXrUZx0rU+ByNikm7nTdbmWea0lZ9YpP46TiA8nN0O 1D7ogFYxPq1GUqqL+eO2nMxZyx5B7/M/t4WhB4HQszvXkMRtkzVaxEWptQQpqv9D8B9XhQeWjSeh aJeXcf5Ai0TsZMylx6zqg5d20kphFoOUMfeLNxrHdJWszKSP8Q+HxzrRkANy70NXblNIFXQf0Yv0 dViI//eZRLr3yHuC0hMk/K/3Amc8GHB1UJV0fTAfoCBotZV+zsIctl1so32Ng6KLJewOjoZ4b5gB sCLCKVdi0HOad774bfkyWCZF6USOHL4hIbTJIAsqMeisU9Grx1gyXmRSgwqutPMAe5ZbI2IVOntJ 3AlvKj2lJk4pzEBNP9CcSb7pbZstSw+do/9LpyI1orbHvFrAC/L8714LZf++hkXOzlRsJ2u37dXu iVPqSjDY/wVxhUwtTg9NkTs+FXVPrO2YL6OWPdH4z5anWNQeEQmY6Rpozu4oh9QxlVzMkVCJ/bZA l2zTxvkB1/lIIhCq+Up/v33bUxX9j0DvbpFQvfcbsxvGUAQB3fraGHqdZ5aaobci0Pe/qOwqgqRj qFzykMgABZiWqiCN+IuknS4uI/Qnt+SdiW2E+p1tx3bMzxKWlurJ9LH8lvkfhVy6kN9sgIsUloLU ifwK7s3MWcichaTc7uwvyLBzi2Mu/BZPATxKHeIhfKqC9ATGZ7ZZu1aWd80+OpLvRAPeAC546TTo AUjkxKlgLV2RsIztC1xiaWD26KVnx8Ap6LwjuFCbo+f8wEw8PvL5edH0OWcsFnJ5d/6Z6A0KZkiS UzQx/z+uBr4kPMq7zJP3WY3tKkZLry58lAuOtTOiFGcl2MEsD21+uumgA2smo85SvbA10XuBLRQ0 wBVcJ89eTgYzBH1acQl/i9sIHf0vo+zDE2F0rc3lTf+orwLVVnkF62AzHm/4Ium35gSargwSz+/g kcE= `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ is port ( aclk : in STD_LOGIC; aclken : in STD_LOGIC; aresetn : in STD_LOGIC; s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_config_tvalid : in STD_LOGIC; s_axis_config_tready : out STD_LOGIC; s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_data_tvalid : in STD_LOGIC; s_axis_data_tready : out STD_LOGIC; s_axis_data_tlast : in STD_LOGIC; m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_data_tvalid : out STD_LOGIC; m_axis_data_tready : in STD_LOGIC; m_axis_data_tlast : out STD_LOGIC; event_tlast_unexpected : out STD_LOGIC; event_tlast_missing : out STD_LOGIC; event_halted : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "cic_compiler_v4_0"; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "cascaded_integrator_comb"; attribute C_FILTER_TYPE : integer; attribute C_FILTER_TYPE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_NUM_STAGES : integer; attribute C_NUM_STAGES of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 5; attribute C_DIFF_DELAY : integer; attribute C_DIFF_DELAY of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_RATE : integer; attribute C_RATE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 16; attribute C_INPUT_WIDTH : integer; attribute C_INPUT_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 2; attribute C_OUTPUT_WIDTH : integer; attribute C_OUTPUT_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_USE_DSP : integer; attribute C_USE_DSP of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_HAS_ROUNDING : integer; attribute C_HAS_ROUNDING of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_NUM_CHANNELS : integer; attribute C_NUM_CHANNELS of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_RATE_TYPE : integer; attribute C_RATE_TYPE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_MIN_RATE : integer; attribute C_MIN_RATE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 16; attribute C_MAX_RATE : integer; attribute C_MAX_RATE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 16; attribute C_SAMPLE_FREQ : integer; attribute C_SAMPLE_FREQ of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_CLK_FREQ : integer; attribute C_CLK_FREQ of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_USE_STREAMING_INTERFACE : integer; attribute C_USE_STREAMING_INTERFACE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "artix7"; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "artix7"; attribute C_C1 : integer; attribute C_C1 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C2 : integer; attribute C_C2 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C3 : integer; attribute C_C3 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C4 : integer; attribute C_C4 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C5 : integer; attribute C_C5 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C6 : integer; attribute C_C6 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_I1 : integer; attribute C_I1 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I2 : integer; attribute C_I2 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I3 : integer; attribute C_I3 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I4 : integer; attribute C_I4 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I5 : integer; attribute C_I5 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I6 : integer; attribute C_I6 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_S_AXIS_CONFIG_TDATA_WIDTH : integer; attribute C_S_AXIS_CONFIG_TDATA_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_S_AXIS_DATA_TDATA_WIDTH : integer; attribute C_S_AXIS_DATA_TDATA_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 8; attribute C_M_AXIS_DATA_TDATA_WIDTH : integer; attribute C_M_AXIS_DATA_TDATA_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 24; attribute C_M_AXIS_DATA_TUSER_WIDTH : integer; attribute C_M_AXIS_DATA_TUSER_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_HAS_DOUT_TREADY : integer; attribute C_HAS_DOUT_TREADY of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_HAS_ACLKEN : integer; attribute C_HAS_ACLKEN of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_HAS_ARESETN : integer; attribute C_HAS_ARESETN of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "yes"; end \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\; architecture STRUCTURE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ is attribute C_C1 of i_synth : label is 22; attribute C_C2 of i_synth : label is 22; attribute C_C3 of i_synth : label is 22; attribute C_C4 of i_synth : label is 22; attribute C_C5 of i_synth : label is 22; attribute C_C6 of i_synth : label is 0; attribute C_CLK_FREQ of i_synth : label is 1; attribute C_COMPONENT_NAME of i_synth : label is "cascaded_integrator_comb"; attribute C_DIFF_DELAY of i_synth : label is 1; attribute C_FAMILY of i_synth : label is "artix7"; attribute C_FILTER_TYPE of i_synth : label is 1; attribute C_HAS_ACLKEN of i_synth : label is 0; attribute C_HAS_ARESETN of i_synth : label is 0; attribute C_HAS_DOUT_TREADY of i_synth : label is 0; attribute C_HAS_ROUNDING of i_synth : label is 0; attribute C_I1 of i_synth : label is 22; attribute C_I2 of i_synth : label is 22; attribute C_I3 of i_synth : label is 22; attribute C_I4 of i_synth : label is 22; attribute C_I5 of i_synth : label is 22; attribute C_I6 of i_synth : label is 0; attribute C_INPUT_WIDTH of i_synth : label is 2; attribute C_MAX_RATE of i_synth : label is 16; attribute C_MIN_RATE of i_synth : label is 16; attribute C_M_AXIS_DATA_TDATA_WIDTH of i_synth : label is 24; attribute C_M_AXIS_DATA_TUSER_WIDTH of i_synth : label is 1; attribute C_NUM_CHANNELS of i_synth : label is 1; attribute C_NUM_STAGES of i_synth : label is 5; attribute C_OUTPUT_WIDTH of i_synth : label is 22; attribute C_RATE of i_synth : label is 16; attribute C_RATE_TYPE of i_synth : label is 0; attribute C_SAMPLE_FREQ of i_synth : label is 1; attribute C_S_AXIS_CONFIG_TDATA_WIDTH of i_synth : label is 1; attribute C_S_AXIS_DATA_TDATA_WIDTH of i_synth : label is 8; attribute C_USE_DSP of i_synth : label is 1; attribute C_USE_STREAMING_INTERFACE of i_synth : label is 1; attribute C_XDEVICEFAMILY of i_synth : label is "artix7"; attribute downgradeipidentifiedwarnings of i_synth : label is "yes"; attribute secure_extras : string; attribute secure_extras of i_synth : label is "A"; begin i_synth: entity work.\cascaded_integrator_comb_cic_compiler_v4_0_viv__parameterized0\ port map ( aclk => aclk, aclken => aclken, aresetn => aresetn, event_halted => event_halted, event_tlast_missing => event_tlast_missing, event_tlast_unexpected => event_tlast_unexpected, m_axis_data_tdata(23 downto 0) => m_axis_data_tdata(23 downto 0), m_axis_data_tlast => m_axis_data_tlast, m_axis_data_tready => m_axis_data_tready, m_axis_data_tuser(0) => m_axis_data_tuser(0), m_axis_data_tvalid => m_axis_data_tvalid, s_axis_config_tdata(0) => s_axis_config_tdata(0), s_axis_config_tready => s_axis_config_tready, s_axis_config_tvalid => s_axis_config_tvalid, s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0), s_axis_data_tlast => s_axis_data_tlast, s_axis_data_tready => s_axis_data_tready, s_axis_data_tvalid => s_axis_data_tvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity cascaded_integrator_comb is port ( aclk : in STD_LOGIC; s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_data_tvalid : in STD_LOGIC; s_axis_data_tready : out STD_LOGIC; m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axis_data_tvalid : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of cascaded_integrator_comb : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of cascaded_integrator_comb : entity is "yes"; attribute x_core_info : string; attribute x_core_info of cascaded_integrator_comb : entity is "cic_compiler_v4_0,Vivado 2014.2"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of cascaded_integrator_comb : entity is "cascaded_integrator_comb,cic_compiler_v4_0,{}"; attribute core_generation_info : string; attribute core_generation_info of cascaded_integrator_comb : entity is "cascaded_integrator_comb,cic_compiler_v4_0,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cic_compiler,x_ipVersion=4.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,C_COMPONENT_NAME=cascaded_integrator_comb,C_FILTER_TYPE=1,C_NUM_STAGES=5,C_DIFF_DELAY=1,C_RATE=16,C_INPUT_WIDTH=2,C_OUTPUT_WIDTH=22,C_USE_DSP=1,C_HAS_ROUNDING=0,C_NUM_CHANNELS=1,C_RATE_TYPE=0,C_MIN_RATE=16,C_MAX_RATE=16,C_SAMPLE_FREQ=1,C_CLK_FREQ=1,C_USE_STREAMING_INTERFACE=1,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_C1=22,C_C2=22,C_C3=22,C_C4=22,C_C5=22,C_C6=0,C_I1=22,C_I2=22,C_I3=22,C_I4=22,C_I5=22,C_I6=0,C_S_AXIS_CONFIG_TDATA_WIDTH=1,C_S_AXIS_DATA_TDATA_WIDTH=8,C_M_AXIS_DATA_TDATA_WIDTH=24,C_M_AXIS_DATA_TUSER_WIDTH=1,C_HAS_DOUT_TREADY=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0}"; end cascaded_integrator_comb; architecture STRUCTURE of cascaded_integrator_comb is signal NLW_U0_event_halted_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_tlast_missing_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_tlast_unexpected_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_C1 : integer; attribute C_C1 of U0 : label is 22; attribute C_C2 : integer; attribute C_C2 of U0 : label is 22; attribute C_C3 : integer; attribute C_C3 of U0 : label is 22; attribute C_C4 : integer; attribute C_C4 of U0 : label is 22; attribute C_C5 : integer; attribute C_C5 of U0 : label is 22; attribute C_C6 : integer; attribute C_C6 of U0 : label is 0; attribute C_CLK_FREQ : integer; attribute C_CLK_FREQ of U0 : label is 1; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of U0 : label is "cascaded_integrator_comb"; attribute C_DIFF_DELAY : integer; attribute C_DIFF_DELAY of U0 : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "artix7"; attribute C_FILTER_TYPE : integer; attribute C_FILTER_TYPE of U0 : label is 1; attribute C_HAS_ACLKEN : integer; attribute C_HAS_ACLKEN of U0 : label is 0; attribute C_HAS_ARESETN : integer; attribute C_HAS_ARESETN of U0 : label is 0; attribute C_HAS_DOUT_TREADY : integer; attribute C_HAS_DOUT_TREADY of U0 : label is 0; attribute C_HAS_ROUNDING : integer; attribute C_HAS_ROUNDING of U0 : label is 0; attribute C_I1 : integer; attribute C_I1 of U0 : label is 22; attribute C_I2 : integer; attribute C_I2 of U0 : label is 22; attribute C_I3 : integer; attribute C_I3 of U0 : label is 22; attribute C_I4 : integer; attribute C_I4 of U0 : label is 22; attribute C_I5 : integer; attribute C_I5 of U0 : label is 22; attribute C_I6 : integer; attribute C_I6 of U0 : label is 0; attribute C_INPUT_WIDTH : integer; attribute C_INPUT_WIDTH of U0 : label is 2; attribute C_MAX_RATE : integer; attribute C_MAX_RATE of U0 : label is 16; attribute C_MIN_RATE : integer; attribute C_MIN_RATE of U0 : label is 16; attribute C_M_AXIS_DATA_TDATA_WIDTH : integer; attribute C_M_AXIS_DATA_TDATA_WIDTH of U0 : label is 24; attribute C_M_AXIS_DATA_TUSER_WIDTH : integer; attribute C_M_AXIS_DATA_TUSER_WIDTH of U0 : label is 1; attribute C_NUM_CHANNELS : integer; attribute C_NUM_CHANNELS of U0 : label is 1; attribute C_NUM_STAGES : integer; attribute C_NUM_STAGES of U0 : label is 5; attribute C_OUTPUT_WIDTH : integer; attribute C_OUTPUT_WIDTH of U0 : label is 22; attribute C_RATE : integer; attribute C_RATE of U0 : label is 16; attribute C_RATE_TYPE : integer; attribute C_RATE_TYPE of U0 : label is 0; attribute C_SAMPLE_FREQ : integer; attribute C_SAMPLE_FREQ of U0 : label is 1; attribute C_S_AXIS_CONFIG_TDATA_WIDTH : integer; attribute C_S_AXIS_CONFIG_TDATA_WIDTH of U0 : label is 1; attribute C_S_AXIS_DATA_TDATA_WIDTH : integer; attribute C_S_AXIS_DATA_TDATA_WIDTH of U0 : label is 8; attribute C_USE_DSP : integer; attribute C_USE_DSP of U0 : label is 1; attribute C_USE_STREAMING_INTERFACE : integer; attribute C_USE_STREAMING_INTERFACE of U0 : label is 1; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "artix7"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.\cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ port map ( aclk => aclk, aclken => '1', aresetn => '1', event_halted => NLW_U0_event_halted_UNCONNECTED, event_tlast_missing => NLW_U0_event_tlast_missing_UNCONNECTED, event_tlast_unexpected => NLW_U0_event_tlast_unexpected_UNCONNECTED, m_axis_data_tdata(23 downto 0) => m_axis_data_tdata(23 downto 0), m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED, m_axis_data_tready => '0', m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0), m_axis_data_tvalid => m_axis_data_tvalid, s_axis_config_tdata(0) => '0', s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED, s_axis_config_tvalid => '0', s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0), s_axis_data_tlast => '0', s_axis_data_tready => s_axis_data_tready, s_axis_data_tvalid => s_axis_data_tvalid ); end STRUCTURE;	mit	fff8575e4a9a9fb88808f0733533c0cd	0.942398	1.851644	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_mngr.vhd	1	25,833	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_mngr.vhd -- Description: This entity manages fetching of descriptors. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_mngr is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1 -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control and Status -- ch1_run_stop : in std_logic ; -- ch1_desc_flush : in std_logic ; -- ch1_updt_done : in std_logic ; -- ch1_ftch_idle : out std_logic ; -- ch1_ftch_active : out std_logic ; -- ch1_ftch_interr_set : out std_logic ; -- ch1_ftch_slverr_set : out std_logic ; -- ch1_ftch_decerr_set : out std_logic ; -- ch1_ftch_err_early : out std_logic ; -- ch1_ftch_stale_desc : out std_logic ; -- ch1_tailpntr_enabled : in std_logic ; -- ch1_taildesc_wren : in std_logic ; -- ch1_taildesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_nxtdesc_wren : in std_logic ; -- ch1_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_ftch_queue_empty : in std_logic ; -- ch1_ftch_queue_full : in std_logic ; -- ch1_ftch_pause : in std_logic ; -- -- -- Channel 2 Control and Status -- ch2_run_stop : in std_logic ; -- ch2_updt_done : in std_logic ; -- ch2_desc_flush : in std_logic ; -- ch2_ftch_idle : out std_logic ; -- ch2_ftch_active : out std_logic ; -- ch2_ftch_interr_set : out std_logic ; -- ch2_ftch_slverr_set : out std_logic ; -- ch2_ftch_decerr_set : out std_logic ; -- ch2_ftch_err_early : out std_logic ; -- ch2_ftch_stale_desc : out std_logic ; -- ch2_tailpntr_enabled : in std_logic ; -- ch2_taildesc_wren : in std_logic ; -- ch2_taildesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_nxtdesc_wren : in std_logic ; -- ch2_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_ftch_queue_empty : in std_logic ; -- ch2_ftch_queue_full : in std_logic ; -- ch2_ftch_pause : in std_logic ; -- ch2_eof_detected : in std_logic ; tail_updt : in std_logic ; tail_updt_latch : out std_logic ; ch2_sg_idle : out std_logic ; -- nxtdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- -- Read response for detecting slverr, decerr early -- m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; -- m_axi_sg_rvalid : in std_logic ; -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_ftch_cmd_tvalid : out std_logic ; -- s_axis_ftch_cmd_tready : in std_logic ; -- s_axis_ftch_cmd_tdata : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- User Status Interface Ports (AXI Stream) -- m_axis_ftch_sts_tvalid : in std_logic ; -- m_axis_ftch_sts_tready : out std_logic ; -- m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; -- m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; -- mm2s_err : in std_logic ; -- -- -- ftch_cmnd_wr : out std_logic ; -- ftch_cmnd_data : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- ftch_stale_desc : in std_logic ; -- updt_error : in std_logic ; -- ftch_error : out std_logic ; -- ftch_error_addr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) -- ); end axi_sg_ftch_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal ftch_cmnd_wr_i : std_logic := '0'; signal ftch_cmnd_data_i : std_logic_vector ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); signal ch1_sg_idle : std_logic := '0'; signal ch1_fetch_address : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ch2_sg_idle_int : std_logic := '0'; signal ch2_fetch_address : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ftch_done : std_logic := '0'; signal ftch_error_i : std_logic := '0'; signal ftch_interr : std_logic := '0'; signal ftch_slverr : std_logic := '0'; signal ftch_decerr : std_logic := '0'; signal ftch_error_early : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ftch_cmnd_wr <= ftch_cmnd_wr_i; ftch_cmnd_data <= ftch_cmnd_data_i; ftch_error <= ftch_error_i; ch2_sg_idle <= ch2_sg_idle_int; ------------------------------------------------------------------------------- -- Scatter Gather Fetch State Machine ------------------------------------------------------------------------------- I_FTCH_SG : entity axi_sg_v4_1.axi_sg_ftch_sm generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 , C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH , C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE , C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR , C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , updt_error => updt_error , -- Channel 1 Control and Status ch1_run_stop => ch1_run_stop , ch1_updt_done => ch1_updt_done , ch1_desc_flush => ch1_desc_flush , ch1_sg_idle => ch1_sg_idle , ch1_tailpntr_enabled => ch1_tailpntr_enabled , ch1_ftch_queue_empty => ch1_ftch_queue_empty , ch1_ftch_queue_full => ch1_ftch_queue_full , ch1_fetch_address => ch1_fetch_address , ch1_ftch_active => ch1_ftch_active , ch1_ftch_idle => ch1_ftch_idle , ch1_ftch_interr_set => ch1_ftch_interr_set , ch1_ftch_slverr_set => ch1_ftch_slverr_set , ch1_ftch_decerr_set => ch1_ftch_decerr_set , ch1_ftch_err_early => ch1_ftch_err_early , ch1_ftch_stale_desc => ch1_ftch_stale_desc , ch1_ftch_pause => ch1_ftch_pause , -- Channel 2 Control and Status ch2_run_stop => ch2_run_stop , ch2_updt_done => ch2_updt_done , ch2_desc_flush => ch2_desc_flush , ch2_sg_idle => ch2_sg_idle_int , ch2_tailpntr_enabled => ch2_tailpntr_enabled , ch2_ftch_queue_empty => ch2_ftch_queue_empty , ch2_ftch_queue_full => ch2_ftch_queue_full , ch2_fetch_address => ch2_fetch_address , ch2_ftch_active => ch2_ftch_active , ch2_ftch_idle => ch2_ftch_idle , ch2_ftch_interr_set => ch2_ftch_interr_set , ch2_ftch_slverr_set => ch2_ftch_slverr_set , ch2_ftch_decerr_set => ch2_ftch_decerr_set , ch2_ftch_err_early => ch2_ftch_err_early , ch2_ftch_stale_desc => ch2_ftch_stale_desc , ch2_ftch_pause => ch2_ftch_pause , -- Transfer Request ftch_cmnd_wr => ftch_cmnd_wr_i , ftch_cmnd_data => ftch_cmnd_data_i , -- Transfer Status ftch_done => ftch_done , ftch_error => ftch_error_i , ftch_interr => ftch_interr , ftch_slverr => ftch_slverr , ftch_decerr => ftch_decerr , ftch_stale_desc => ftch_stale_desc , ftch_error_addr => ftch_error_addr , ftch_error_early => ftch_error_early ); ------------------------------------------------------------------------------- -- Scatter Gather Fetch Pointer Manager ------------------------------------------------------------------------------- I_FTCH_PNTR_MNGR : entity axi_sg_v4_1.axi_sg_ftch_pntr generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , nxtdesc => nxtdesc , ------------------------------- -- CHANNEL 1 ------------------------------- ch1_run_stop => ch1_run_stop , ch1_desc_flush => ch1_desc_flush ,--CR568950 -- CURDESC update on run/stop assertion (from ftch_sm) ch1_curdesc => ch1_curdesc , -- TAILDESC update on CPU write (from axi_dma_reg_module) ch1_tailpntr_enabled => ch1_tailpntr_enabled , ch1_taildesc_wren => ch1_taildesc_wren , ch1_taildesc => ch1_taildesc , -- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) ch1_nxtdesc_wren => ch1_nxtdesc_wren , -- Current address of descriptor to fetch ch1_fetch_address => ch1_fetch_address , ch1_sg_idle => ch1_sg_idle , ------------------------------- -- CHANNEL 2 ------------------------------- ch2_run_stop => ch2_run_stop , ch2_desc_flush => ch2_desc_flush ,--CR568950 ch2_eof_detected => ch2_eof_detected , -- CURDESC update on run/stop assertion (from ftch_sm) ch2_curdesc => ch2_curdesc , -- TAILDESC update on CPU write (from axi_dma_reg_module) ch2_tailpntr_enabled => ch2_tailpntr_enabled , ch2_taildesc_wren => ch2_taildesc_wren , ch2_taildesc => ch2_taildesc , tail_updt_latch => tail_updt_latch , tail_updt => tail_updt , ch2_updt_done => ch2_updt_done , -- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) ch2_nxtdesc_wren => ch2_nxtdesc_wren , -- Current address of descriptor to fetch ch2_fetch_address => ch2_fetch_address , ch2_sg_idle => ch2_sg_idle_int ); ------------------------------------------------------------------------------- -- Scatter Gather Fetch Command / Status Interface ------------------------------------------------------------------------------- I_FTCH_CMDSTS_IF : entity axi_sg_v4_1.axi_sg_ftch_cmdsts_if generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Fetch command write interface from fetch sm ftch_cmnd_wr => ftch_cmnd_wr_i , ftch_cmnd_data => ftch_cmnd_data_i , -- Read response for detecting slverr, decerr early m_axi_sg_rresp => m_axi_sg_rresp , m_axi_sg_rvalid => m_axi_sg_rvalid , -- User Command Interface Ports (AXI Stream) s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid , s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready , s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid , m_axis_ftch_sts_tready => m_axis_ftch_sts_tready , m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata , m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep , -- Scatter Gather Fetch Status mm2s_err => mm2s_err , ftch_done => ftch_done , ftch_error => ftch_error_i , ftch_interr => ftch_interr , ftch_slverr => ftch_slverr , ftch_decerr => ftch_decerr , ftch_error_early => ftch_error_early ); end implementation;	bsd-2-clause	3b66ab27886894222a34b63a66df9615	0.358108	5.123562	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/fifo_generator_v11_0_defaults.vhd	2	30,145	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VX2fgfoQjr0QNLgHtDA+gIITmlZjMeot2NAaAq8LF+/WAkN+N3o/LK8V3H4iOAnacmZPDgnWWfzm IUXrGKyjKw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Jmn6FAdhmXuakV1kTd32dofEIXYMcQ9cNEIzCNULYtezAbv2IS7t4diEsuDDZKF0EmcvqgeZSIrG f6CNTPWlu6hk3H3ID/H9g0ADKEboCgjiZTAlsE+veN4r299owuDQOINMnpM4lBq4lqrted2dnbAn 9Yov+e7Asr7nO4ow8Bw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block vIkoPFwMna/K/3APKoT8OkCGwY8aS5wOXk2HwY/L3U0CD2AUrdRklOmxKRAVqmnB1C+l/+IoVP6h uDRnvcM4ByHLceKnY0rjNmxCZcyyAjurVPSudafpvphGND7hRdmk9PXJIgLz4rF8cdyRn3bOCohF q+LlgBJF+4PL62sw65KIEVS/c4G3k6ddZ77kQM/QpfmpZtU/7/DVzvR3aroaA6azvMv/1dfiQ9NI +UFZ6byFvMruf9kjGOStMfAk4V4RK/MwaLkRG0RFL83Df8U5CPD71pTIo6M2m5bnhg8LieS13JvM LyKBHRLrvgwQ5mG6OOUaZ7m3p0FQWL+yDjxxWg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block idChZ52qZGvxILHsTGTJHJCf52mhXVsjDpZGWuPMBhXm0bmHXIL7RtdbAWzdUq2yMP+dXiLXNQr2 eTdPsVFYQG4+I1UDOd3D4o1CmiO3a7DCTnuXfZU0gAD/BXT27uh2KDjHBopm6fE9v4Gsr6Vj5m97 XBa18Xy6PBtXyDBOks8= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block kCVpP0tZR4WjUyX8WXquJ7D1cmQMvhKl7iHiuzOG5Clhm7h4Q5aDg/Kcogvyo4eqnf6OGvgoyVxX uxfXWBMMTWs1QPmbCquCUZcw42hFsR0ywYtZ2U0fe2QUGY8+OKl/8/nHmaL2QZ/aHyxG/oLyh2AG tzhWt+eu8mMfe2pfDalb8haDbCATmLrYIqR1fyxT9+KSOLbcuDMhZt/SxHdCyMHNkMbRw9CoRcxd blmGRpUXewmeS5bEaSCbKAZcgtD4K89QwC4RMgPL/qk9ZUGzwH5taxZTGAQ4DjjA442eWe2pjduc IYE8PP036C7jzixFppaiMZBtTMVMsy74OSGyoQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Tr8hnq5qS15FRuDmaCMTXd3zDwsXudCBEe9DijbS+S1mc9Gv8nyFsS200zS/r4KN6dloZjDXNVRz 9qodpfdWmpWMld7MmCeGKFD4wytFajjYd0d0rVI6Byf00EtiFeoj1ZdLeaGK7LuhFJiUVkUQCsO8 nwuTF1SGydat/QYY9M9sOdZPfEKKYaJvDnKyGk5pyieq18Q5gWe8ykvsBfLyOLdjIVm8boo2u0zs BWeBltnoD3abC2rk6yA7T+D6MAnoEPJmeHqL6xgWJOlthsxGmvndGKssN27I2h1CxKTGnOO74KO+ k4nF5gQfMUrkUvbTdNszVgdqdUt/GPygPnzXJf8/iAnMyLzqQg+YksiTUirgEYYFlGmJmGpOADYv kKLocfol2iYRkqz+sQh2OUHlDX3qCR8ZBZwg/6m4ieZVag0xIIsmtHjTFWlISsjAEFrONVEG0VWk mDDnll2qz7cYa3eWk78aS5/W8Vcfm96G32jVDNOfR9yl7aaowOaazLhNzwTZ4UBH+mb3vlV8AJHa qtnYp0iHCo+7aTNTheS+BwBGvIE57Y56O7k9xCuuJlfnE6cn8AOo3ksXZ5Ihixk90h04k40aT+zn NTMZw3EtcNXqLkqWaZ5vNoI9G0o849iR22eUdONHZfnCiI0oqATauK7v8zpY1KseEybdKyKjoU6I SOFfpwn4rsoEk2SY90Ympe3agVdJxBh2X/wkDE63EDqcVjmiBTnwja94LhHruKw69Nl8QRAJ5s/t uD5UPmoMV7zMl/eNa3uz6fJ9vGKTIqnb4QyoYZeMVoM/Y5dI1naCapbtqO2fx9ydnfPjHGKfH/JQ ZxUoWrHLrOK0pYxa3pf+TVCc/NuEmeL3C46wByMT5ZmKNoXQmFoVFhwi2ivt1nPdwZ2JutYYBgOW 8sbUrY1AoO2gxM31dXKLMge/wIVHeKYHq0161iFY8UKPyA5nDv809VgEp665FJ7fqQ+Jon3g5Mvo 01kWLLCl+djbBnFzGFCJzu0/yQoRQ4SCvNWIObB4MBWnVNBSifZ0KTIQwNuqyLDv0JdQVzb0Ka6g T8WbhwMi2zpjGamSdV6oZLJ/ZksKXNoSD2MFUsdyZgWt1+uiOuUU7iatDPL2EHIQQ10MPuB2tNoV yUod/TbbOcpnwdJxjbwEFVs5pXZSH5L+TOAMCq97ZMTAiVNDTVVcNX3c6xk2Z8XzOTi2n7r8YjKZ lOzw+VgeN1IFPXt1T4eDobUApXffE82nCxXT7/I65oLQFXXOMTUibzwtJo166WVRzNno2kt10+eV iIHUq1w+latHrRPa9Oaxxg+VbObKUH5HKhn+HxL7w+T7+fnp/DdbwE+zX7nk4DqTf5tiIVb1Wxce mbCkH4akB0nwaXrUWngdwMiOlkU7JWzXdW9Z9K14kjykqRDKh9AhyZFnK5vvw6gjlt63IbL39u3C gZU2H0F8eT7dqa7yfnsXVQtSph19TTwKPMjcCqlV9c42vpj1hmU1YdyUZNEa4nXCSkQauFxz1fbO E0P4kLAopwbFu0QiRDxbPqayredSyKGsVHokw4E2ajFtZnNR/Jctb44Z0edNg16nk22W//CpgWSS /oqsntzZSiwi5n+r7UZDOjJvaEVD+CJTOcqmL6IfakmmxPsF9ZLaIwuuN/C5C0Y5aBN6vTGe4XUD i662GefLECBz7uYUtmbgF2aea9kqkfaRM5VLk5QnjbDkTKHkT1lNE4k14vuufEG07yGBMmD6pxzO DYLDxaH3iDG4cHvULLPmGYjf2fqqotxpuxPmqSB08G6znVkkRLiutj2jg3tzFyG0094rj/VgFyQI NsFcnlxg61bVfVOOPsUp3EaVUBaAuTmsKQkp0xri5KHM+ukHb5qi0/HhmvrWenF2FJc0Cd07j3e0 Keg86Mf/88N9KNrCzkbvtPNuulWJ2cspXGouCbsXlQR8V/r/S+MEnlhLf8qDcEgKpF+xWvtcGCNU PdBaxRGObZmy1WZfZiTxB4oXJDB68FJvyAIrMY1036f7a+UReB7mkwn0PsPkCYZekCb+q+I3qHZB MkVPhvLJ5lfVuS0RdDpjFmzRbAGr6H0u0ZDwqoY6hXkTqlNzpWjIRY0Lwb/e5qN0aHC2OXcPL5qL DTL+o+IDA85zlKh4WRITMNixKAscZwyq7JGQzch/93QeRQ1o9UnC8mfYamFZckZ+95HlM1kd+x1F CBLInWjCbMD1Yg1zemmTAn7PRdtvHgvSj2Zsmpzqs8oPidCgoooDL4y6kCET5hW3FeI9DIg0wn8G HQCohP6H7udUD2Zk2n8WrctcbH5/h0t+jBNIAX09nnSbRzDWLadOPnj3Zw5/0bXuz1Ljm+I5yuEU 0v6te5UtsI0jR+kgFBoFPywyNLL7/KXfLt3aGA/omZ88WA68HYRcd1Vv3ilcuPVkYMznhtxKe5b7 7AvXcpTqZkoyB/l1m3Dvc5NZ445EOh+ROryr9EGIzCDrBXygjqP5xiA0IxjOivc76IJFLeIv7qty WA6g3GgadR60Cyn/SPnQ1Nji4WqAT1u4heV6zIo3HIQAu24LJ+Mn2gAfuIjdic2FvSCtn330BISA VhWQIz1Tdb4chILn90vdbjIIDFhT2hWEl6kh9cJIARS7C1wvrlnNWjnujNDZkXB4XxT+8VlyWXol q6k8EGInVAq3oJq5upq4XBc/EIBY1rcNkgOpiTUeY6BzIIGaHsln2jFm3wzgtdBQvSG0kV+FKsXb dVNQM1895eRibrg1bqJ2XfWHJlT+o053Fl/Fok5CpqAnou6aMDphD0ovfjFJWLoNgh1CEaGK5PT4 6GoXZ/U//+/0JtauGZ5+64qs1cPplXTXIMarprWGKhPZutBWKaFWLOlLhb0s8fHZ4BmVzUkNaADG iIDfqzPNgDXSOTV4G2YOLpE+8nEnhj5ycii1cBx/dPWDyfN3u640U1RuuWi6vcZ6igIk6reLKeu1 HjCYJMnPQqcAGA7c1FHqk+4iBXmAv8BqJABtvxNiUjufl44DfbEQrJOWZxFzzyLO9VU1R+AIc911 VGdsaWrRKmgoJBgX0XZaxvu0k8a+w37GUV4Sf/q3zd6s4MI+kFpxOYRz5viqag+5AgXjw3++OeyI uo4GZKj7AAz961kDsv2CKasp97NiYZdri+iMbc1pz2GEJCMFzYHBD9/w6ywNT/UdnYhYtqP2R7GK MMgSNn6WSKu5vZOTGT46+T1MWZs5wUp2/HYY8Kcv9s/8lvpAO3Rui7qPdTnarWXKSlZzRIteqxaS IjfB3ZbcSZobJeEZIf+rrAPW3Jf6ZDQIbU+GA8Hys7qyNsAXS1qHiOrq+Z8nBosXE9djaIoo5xdJ xzgd6L1JKLS4fW8A5rks1k2SkqLovvEME2IcmIQpuHzAeCx8wE3Rk8pS2iwrO73uDBP/xVXC1/WU ZpzMXz6gPgZ4EWmrSScQSph8trAlZLMmzObrSbjEW0/SOa6ZozMiWaSbGJ2udhmaZ55nRsCoaVks ZXV6jOt4mhGiS8bxYF084v+1XTbbdndxoQ8Vsrvh5fNK3g+WfouwnHytVPtpWGpTmhgzEZjFzmRe E5i93nVPvz+pNm10OAH45EN0w0a9o7m2lyrpwx2FvKUalcbVMOVmOd2BqU5HlajjtEGwAqPsUpVr B8UeIwaJXjV2cYA/0Rx59Q4e5lLiuzDHTY62WLyY1mYUVW80DsfSPYNqUJ5r34EpWHZPJvcUWIHe 4zEA10JaXwwXvTWN4aLGOCww/2OmoR2E4UlZW26QKWUnkrE0LDL2sMT60UI0n8YdpN6SGRhwPuCU dBc5z5UMl+YHsoFXNpjd499BVu1Zkqm35cR4e3rZ41XDCmPp1AVsf48vpZHGlCQXHIargWHnNdTR 8haLEfN9B4Jf5ADxju55dCZEIBGrTyle2vZ0daAU/bfM9ryIITTGvVgetS577EYghQf5L2uRmOlh uJyOa54UR3Zb1znHk9X4kLg8DUfQbWd0JK5Dvx2db0Wk1Nr0NepGTvWLTT0IP0P1UhFkovxJjrle rcmhSdiaDgoe4WYAjWFz8g+ihCPMW+7Oexrptw2vgcyRQ2PhCsuEgMj4wdsZFOJWK92xYotzi3SY AqkmFH2taklQdL5I5wujkI4NP+Ol7bz1rcra2pKo4vdkiGdtUdP1OEFEmCqXBz5zjxxEfNEM1KPv HSGs3JwRMk0S9+RVA3sm+WcJIOqHewMWTs0djwSD4VU3pX6B3n8QU09jrBC5JHZaTPawpQln2VgH p9j6QBiZ+Tx/gPuJKZnmo8OZ0v3lQRTaPS+gidCjE2DqUrGa9OuQAMt0FPT0efk5g+b+h6z3KPWz dkDhoA6X1F1zEmQ7YLSNUZ01BTycICi8jPSI9vTK8D5QtdasXq9C+sS66yRQS8mDFoBN231Gp6P9 dny9cAq3lmnjRHxW2QJpEavhrkXiV1QekfkOl37YUXpt02PzSbsGaXWKJfuBlBgGKbH4Oes208Xh PDMrX90O/b569OmMjOpboadjl97OTgwKjUAvvAqHsBY02jt+T+cPW7XwpAaGmQ3EjREazrZAxmTv HsJ0d2NnJGlWfQBDjYM8LonO39Jly3gzaCBbSS30AbImPvlvP5dT26ouarGqLONc21B/xm9tT1Lh r0oWaI+szwmppHmaXgBNNDDBvMHLZy00tXxTSx92j9SQjMbcdvP5OtmjKLtoFRbBCRQT6vD3JRxe n8gTk9GCIfcKAhK7MJ6n1CCNPXv0V5uCUDmbrRmzXv9jZZ08hWnLqgCu9yTMszAoRO54DclXqodw c8cvDvnq+1CBlypNSOLskj6n+qG+DMgQ/2q/vTtAAtyufZRT83D7jnssQ0Zeew2UDlNJ5/UdvzsI fvDV/sfaiAwYhzZ5CLnCU4FySa13pOmXBYBDxanC0ttMhukdpRGy5jUjl32gMZMIg5l4kXmglSsR x7gUEE4vOAfWv4PjKgBYQ/us2ydr+2ET4/tbTKPFxxyfPl6pIfif+5MJa4iyGMVSbMdxlX7ojAI1 R/+PsrCeOhWwjaD7U+9KP672h8y9qgALEGRjz7SSwVG3t3YfIHJoEjh18EFzD6u3AGEnafa+381d 4SjBNFCARKw47+ZiVlK6ewtPjS+71G3qtz38GUkotHRN8QiJQveGOJDlOAh3FPO7z+ft8Wr4L1C8 zVL2Po5MMdOvmihdh2274TMu2B2EwdXOfdc5wOykb/ZYuGxTHljmUk5GWG/TzDM6RmeEWNSlztDK GmI4+BI/ywSR9MOlhsAV3lWqwBsZ067tsmcJ9sAHeztDYDjuMbaDcQWbjP2eyVu+YOl8XVPbDTVy pUb56dLf5WExTPoVEWhXYkGQkzkd7WAnXi8KLB+4b4hcZL1JN9RoRd9Hs3Wd5Q56Le6gm3+r+a2O 15KT9jvZVCX7UYivzRBQFeepmvh7qJF5tQZgSyLF3U6+fQYg5cUUM4wnIHrWm5aafZJs+e8+uCfh yQY5qfgGoFPjF15Ipnt3WwjfFNFExXqV3hiwZXLWkV2pRhWAgnzYQ7wfJKgJHs3cZwinPaqK/18f LtSRq/DaoONtxOhMB31Mj4WNjzvGFRikJA0LVr72bV04cDnm/xdI/xolej+JQltPr8SrXAsKR33d bi59BgNbZwc/3lrc1Qj2EIfCIdrqv/FBjeV4EOo1ICfkgOWW7tpnBCOwgUORS8iQc+MjC/XOlRrM frklPC6UqxlGgwpo/1YiEaudXUSrmDZzgu+u/eQcioeUe/G6uTb7GVHrGYMtfJeakSDbC+ijIRxA UgqP+NzbaiT3bRg3sud8HXp+/LKYDa7hdzyY5o97Of2LLLS6c+1nNnj/aGHJrmYtpKcE9U/vqQUT AJDUI4np0FJvvertzrOs8N3HikEEW+gdu1i6Tow8Dq7HRbk37qLtgXoGsQQNwdi7M6a2IBzphDVu RNAYRZNsFX/V+CN6604bSYihAd6RsWBHpB1Af2bnWwihW5REsTm5BbUK2JzY6BkSs8YyerFHDgFw rmdOgM0HpjchXLknPKWIhGxFilgbDMYDJAinTcK8MoRkst9EAUkOvTJ5GkYWmL2LffVtqUtW1eHl SMbLL/Cbq3e75muBZE+t8QFjdJpq3Xt+TGpZUYUXFTtLQ6YG7nNKuwZgDE2Cq9HQ6iyjgEd3jJ9w 5ZfQ4pwFjYzEVBfkoiuol2iWjIu5q8bCGt9UE9v3Cp3nIBcb8SHpl4rycbpGeTSemppCpUC4aBw1 HwOl519DKdOrJ0xfYagyGASwRe3hiyw24tGpijpLE+BT4lAcXqj+WB9fEDVwGDtkEuJMe5ISrYxr W63CugBNdmfUgWWLSeE+ELE15kNAMsUW6QNTj+1CjXiabr2lTaWs/jRX41RWOmtcpN8R4AyEjkML I6XqdAdDlfoBrphL6bdPfIWqupfgmW0DUkjZ690/iNWtal41xj9tBHwRdyz/eDePYiGGf4iGhUcl ro+9ZKV0lcL+8rFn8yt0lcvOJtopLsBKv4CmSNHX6tKbg3WX795eBKDgFgdJ1emN2M6NqXrDHPTc ePYFe3OSt4gVxWDY4YrfR9Glkzy1XcGUba54UBfLBEMG5j+fqkAqUJOWNERp82h4cOIe0G1WV8Gi El3rwitqRsfMu5GVWMuzyjKlE8G1dZGJGx0lGbMvulF/WZzwPyKnXdsvYwhAvBHg7NHjJG6HApen 9DNHS1BSeDkFHNfWuEMGY0ziMPausLvJbzllSNyySpgER2KK5J41HTxKMjdEuureqbf+rZ47xWRy WU/HN+fEcZCvdIgE4NCGW4COXBmufYP4QwiZ6DrylkSXhLxCjnW3TU/eb5vVOvjF4p+edLJhLa5A 5kVCbRq7s7fKVJG05uZBQuu6xrRmzrfwg6qhvTgumEWMs5h2quAgYOBFvY9zX04esz/cdBRwcsIG RiKEosSB57rwnmfGDlrP/h7rpE/2TrN7Mb9Fa5LnPQ33eehQ2VsQF7ntqyW3zsDVCSATGglodFio xwDL/C4/EBvQnIqDhUzzQLdMU5Ii23hyqvx5dXwiolI924M5SyfFcp3ZYH9viBpjHx9hpHTTRGOl 4VNR/NepDW9GndgvWT2h/TLQZZkIAUAYKx+1HjCfaLYYTZRNq29gRctuEI04pknbKtotgro9FVZk tJTH+eDTLnO3nELeqZzbf8lCmpt0l71uKvOCnQlraDTi66IihNgoDoOPMYA5orzObhVjBUrAQDk7 GpvJ7rPxFvqi8SFQcF+fPO3h7hFrpo8OCtwV0mN0L77WqTthuZaxXCfwA6Eq3twG8M/lvgiC/lCJ 6k9gJdTo1zSSCEHKOEL7MlDi2zKWImIx9PUY7CQre2Cd5NGTLXHyuh4fd3eH9ND1kBxEYfrQywe9 Yx3lu3k+GGRc9ZR0ivCqxYVucUOGvQRVucwMdvIcJzNO0s8Sih75k0ZsU89mTVaqpzITt2n19b8N 2DQ2RPYxH3H5FJLrnECZHhLrAX1oUDoHiUpni6NhP7uOaZQ1I7zNRW96wVJSSxL868LosheTcC+x 5pHX1uo4Y7m6/Dq2y7rIUyAW7BdMJcg3QOuoLRo9Smp4ToJkSO+dOzH//JAge1Z+oCyNFonI2Umk IEWZT6zqfMAKfDw35ds7fBggGbeev3lQxWkjNvY7k16vnlFMvPaMyz/BFgxQTKJ+qKBpH3S5svz2 7xiatr3lUZu8ymW61c3lDShJQzZbhfwmHdmhk/8BgYnDbBb61KVVUGMgzpKXMAmmwdhHnTjyfHT7 mABDzXPnd4z8UYO6Edm2guDEpL9GNwUAbYZ+6hPcmEak9av1V7ShoJdU/MPFTe9u8fVPORbtAFgU CLgs32Q0FiGEFmBfnV6+0iD7PgH2q7HhT9EDuy/rj2qevfj93U6vMXCAFZ6dqMleVyAuHu+/d/1q qsyj0YQuLYOrGBRIrxhfDe+r1NSsbGaTYJWMAls0tT8p+QyKcWn15vZcgNaAoXSHQz+EijJ4hMg9 XpuVT13YsqPKLBuiGRGpJK14oVlC6YhJT2rjBg9HT+TJtMQCUEzLTiPLZk9rsOrJvUQLLVq41C0x In8+DunWbVUG0dMxLkXm6eZY0BUW33DdN4GzP1sEONRt/K4g2lHITyjZbGOR3QjVu31O5y9U7xJj R4J7U57Fta/fpmJAkD8Od17vlcO5iylATTmptbZP5+guvLej0ivp3QByyd3z3LPzLKIVwt+5q8jM ww8oO3w1bllIXTcL9mSUPq26acd+yfh11NqaKuEzLlZlfTpuDiAvjy2cwYTADI960hcLOazKdtuf u/tsWL/Ch754hbcuiYfYfqwJOSJDqM1w4Ztft0T0YazG/0QYPx0Hxi0Qoh+c7zrJpBfFQTMlnNLR BcvXHesL4Wr6v97exHesxFoJ07IOts9/YPGEKK32IpBre7aLsS4j1aiKcsgN1V4W+PqRaDghZtGJ 631J/4SHILVm1KeXAqbQW8yYJNyXyw6AyCfbDVO3kg1/ZswjxXglZ967QRBF4mrzAfVY8VzZ1bFD Lfotf/gzRDjqVFgk6fF0FcAmqYFFrKJvuim5Y7XyT72+7Y8+Pc1fCI/jrnJnFd9QbeidN/aCRSUJ mmF31PNCuCQ7U6ddAWoGkUBDakmcjkMOYAqt64zRqiGqQvx86qJE2eOiFlc5yEuhXZCvFTfAjr9D ag7IpVp9U7nhkfReiniivy5AUX3HNT0Z8zu/KvknI7/JNsal9Y/SPyjaT8wfHSiMc3KGKULjA1O1 Jwrw5kqNIw02AHLveNqZUU0ocy4lvdErbv3l7ngVI21f+nAbOc+b4nurdaX+sRJw0ntEM4zfK6qR C7SNebFLHB7Vbels9MiLqK/mXBlCVY6v8WySlZGoh0CcLYf55h7QeP4OuQVe3mo/WQd3q1ACihki 51TVaYoYVCxSRb8caNiyYhOFOxBB1XeMj7sZJ40Bd997mfmsIfl1STHsSuP6fAQXvPCFg3qUcPgu UVwCuRCmKso3zTj/WRcPS+EVgDc2BlP/YyNhl5hob1FE2MovsQC8YX/Wk1ihpZyx/jdIGlIG/oMf EYix+F0vkKiJSlC57rMbGaFisyu/k5tPpJQSIFzEr82rJPJFsjnsOXxWKPGyEhAjEXzjmT3bC0CO Avj1zYG/CNJWQdraBAS4eztTdEvvc1sd7UBdDXxOTYmfIH1FsE7lUtlO6O84iafNBe5XrpN6SC3W EJIPFqipfFJTh0ia/znfZIG5XYDGqy2FqgDOVCqzEdF2nDf8BtsGstqHhDeFk6Lcr6EXePtRCiPS AAywmcXXohstukJsdi7Hf3O2EvvWcgH8eK6wyNSBoBCPbJIU1+ZTXFZZ8IcGPVAeI0OQaZ7d3oUD FtxCDasAdpeJcDnuDy+YQiWf/tlSXdET9cvYR1geZCR0ZKQxSc3ZVqSODCppIkrQTOC2UY0l/6xm 17Qw6DQVY2DjKZ0tgrkoBl1W7NarUiMjdFOtqKTrN7V8CAjF0vH21sc339aD9noakrTi7ELizxlL cpInmnMDK8oAPpD0sFh4jHqwDdW+/5rVJPzFYTY8OincaS8plA2DZ9/RQYAYM54s+Q+czrEITnP/ baOmLR8g8nvjPPTwvrqeiNu169/nf+EX2y2TPpHokySO5cURVDjIw6NbmXeg/K17Sb4qQ4WBFdhn jdVmUWsTfbCieTFDfGSi0JM3tjlQxLTBIldcyz412fRjn8eOhA5zwmCxh0Yg4j6O3XrYmxBN6mDs 8EBuG/IwmDCNI/+mk5VdiwTF/b1jzZzhRP/wZ1LJWLN9avuZyxU5w0Pjgs0x4IkDE+/F60EKBOen BTcOdRt6q/Zyk8XPQfPufHcEr2LlZ4spTiIGND0G6tUkC0R+QglZmRRlfLYBoAlBeUxYFWBJpPEm GtLRYWc1hHo3NKR+UokGVJknfRDO3ykiBzsdgyaLYRkzWqcpHEJAql8mZMTOw77Z3ej0wuWV6ADG Zt4lLkrRrbkn4J4fx2+ZR29/Swr4DQraR31sKJpZ/EBpluEV/8Lakl35Ret/KhkSV1NHcl2aqpxV 9vkXLth5nHSgff4gGBkaNDcMvY74r+7IX9E5QcO/PicoNy2EHWAtkPfxCuoA+U4jdoe5T+YHOelM 2V0E6a4fLsXh9Si9i8aooOEu9Stdt4wuGHR9ilLZPISZJJ94dCObxTV8jronlW7xOJ6V0CW/6dZ8 GxSwpS/HxFlRAqer1sLUaF/mcgV6TSjPyYqf1D9MTBnmvDJYi/qZ15MjlP19od7iaddGh+NYyINX q/AmR95C+YIRyN3SyE1RwW9aQOmPTJkiRkJQ5JxWndVLVBeoPBMQ5hXkdINMhZHF9U/AK4IXZVqq Pr4E/YXVbCBKJN06brvBqIiOkoNcmhZLNwSLw//NAZ+l+vJHmuqBzS7+Gn1q4KwM4wiKi8Sugkyr Xh3pEpjK3AYKcjGKbJpI/DcTrQIYA/Oqba7r7hr1BzpLJQ4sCxwWwV4wFBylW/43/bUp+r8vDrUU PgLVF+2wxKja59Esz5x8kYetTNv8Wxd9F42l4Fg6D6lCnarYGS5UvPLmWpR2GsDXNCUSLghyvjsf XMG4Km7LllI6fkLHQpfMWvbaiZ34bDe3obK+EFUDi/iE7zoZwZah2nWtCbI/gb9aBwAw7Yz8pIUa 4QqFnDKxm0dBkxOdinmhDKb1juw5e75nSbXCoCUS/loVyM8FnAY7ZEfjHZ/XzSXGn7vPezSkLQ/T hJegcX1Vlb/h9GsAJoSeZusbaVurpdONxgSoBtPziP4HcadNcXdtudNplB3vr4nfI71jnL5pMtFD 1UU/HfqTjvBkM7Ia27yAnw+9yc09Ei4PrMpsxyonrKDv93eMgkdbMJ+Dl80grRBELE4KDdiZZJmG uBO5tyP/2hV4oITIwOhSKSwdeUJcsx4X3Q8cpkBeQOVw/ORxv1aVu4aFetIT7/zyw0aOU9f2QVAm aMLz+z6TUQz1AXecFR8AXDrw36Y2WuwhcA3ucW5h87hZTuWFnVW5YltHWpthgieOhUj2HblyJaeA wmifD1vIZKShga7f8zUUrjkisOEvramtZ1t94Gj6VvV/b6W80pFk+jetmV6B0TluI0FIzouLqF/w AxGpOpl8F9XKkWp3AT1UmOa3vvGivpGT6LE/MSvjH0bowICOyrBkdKhI6IVpZUUEbiD8TZ4Dr4Fr eLNXIPQb/u9y9wxqV3+nAe3CWxWozNpULkDEzqWmTHETVBEtKGOVCFZ6IKaVy7q7Bv3Y29ao0w+5 0BPjKmn8gK3IhLoFiTnRx2njGG+vBzUPu8KO6TnD5nt5DNgWSEUgCLVAQCQkAuXq/gZeACXTu1V0 bbO2VC/mP1t8taxIU7qQY3quUqAMK9SeMMJhZtjKb+k/VrHkc9NmuHJ1zV4PenwPTFv1khDhmWih ZdC65HQtVbrtR6Ud5NxM+gRaWc7ja8dQh7B3lrM8NyZpELqL6wPiNfjT33kIljw6fgESUEVC89D/ MwBHwysYYI9CJPVatynDiXK1TZOqVeobH5izOr0600ZptqhY4jdwA7ED8377rOHAOZQQcNDkAvJN Wd+FG0SBsZE0iPeeSDigKKvCrt+/cJr5OFzCZUAPZePp6j5Wp+dG97Yv0+EMHwmQodYafX4q2Xjh dtTdO8GnjJokp/3HYiilYD8fS7kDG7hBCk5BBxdftG0yZu3669JoPaIUJGjR1Tj+88U2AxWcKMgZ CrRiJhdsJcoiK9FhtkutpBXnqB1gUm6U6pL0supyK1ZtzMQz+CNvFMmDfKwm6Fi4sQvCOCuGnfXy JLPHYtTtTfsxJnfuVHf24TYnaKLZqKKLjdk9bdNlspLhsrsJ6mCrIKIPmMsuNpDgS+oUA/jWNhuC uszuqnYF1gtq3yisPujmAGaQLrJBTmgsle5HB9wQ1bw3ky6PROSNgK+FhtA3m1Y6dtTyFdQwiwfT UxKfdNKWEoUM23/UreZzbeSbktZXvkIcMU4qFSHcOJCegwdQmZv3gY1bEDjgA6sduDJa48Desusk lD67w0QzqxDrbvxhuZipFMHmjW6mJEok/I/0B0juWIuXld0T0KHS6Bfl2WUHPe88HSnEF6TL5qmw c3EBtOkhKhj6GLRMly+q1V44FbjCzq/PY4+SUtN0qNpt3Ld7R95GWAmDGgZ1nM3+YKQvcQsX3JyD QQcdr85Eu4OMyOc4xXz0Wb8eagp2/nWdoCM90nbsW8loZR00NNgKvAKBjVjJYz1CBtDJh8AZY0yi RBSqJ2S2nqTzzAKt6Wq2iq6hZ2Xro1NZDAz+DStkvI17ca3UqcZ4xoKSN1z/qnfv/tfR3cWo63lq 4R5h6hvwi5Y1H91Y/ZyDykmfTRFVPwN9fwSQWjdTqQrzgSO6pokFIngPhuImksc1YeDGsEaKdoEx bCkEFzeFsak2eBVABQWhoV61n4V6wCMySyUnBIx9//qIkAPz23cB3rZohJd2utby56NBWmENvIOy jyAIxzFf/ucNEEfkLgf1evSLA6RiW3l5JbruGIJqV/Giblbcl9NvgPOgT9CQxKZ4grpq6fcRw2ZN +X7FRdaZ3yCx7MEAvrbQ6Y5xXRwutFov7dX9XJpkSBnWrMXRWRzv1lJ1FAcnMpiH47t0lYCxtE93 PTUR7jMRMvpbgWtHVpzTwn5hzNbiZaJ/2jKHOESnOPCVeaqkbalzL4E28Xj2BAsuxOZgP2QUIaFS mjdsiEVtFM263196+Lbxid+gMKLc9IJWo3pYKFVp0t99IH7uKp2g3qeY5EZl9IqCN++8GX3POKPJ bqxmLqUZ6/Bs+kJbtfIit6zosr7Zf7cIOsYf90+/mrtvIrVNUSKN/b9iQY8DRAdB1kxOsxsBQedg tEs/CnpIpIUbeJz47/0uezt7lwwdxVUqK663ZkBUQ4BSNRibRo3KvGJ3epUZL1Sua9C2JhZo/Q/o aTnJDtORv/c6c+/60v2nrkLh9s+vRNmutjilvTZJJbykG47kXOvpKhY/SrfdFFFCduziiwDBgPfF ecVW1cf6V5e2amEWx+k1YrlT/32vQK3hSGMO2WPg9yeUsTz5mrFpQP/ymuzZ8Vc/QjAg/XsbsKvs q1tbPo2Hx4Ap23CHH78QTixbd2mxBddattM1NrYutH33R7l3Ls19j5Us/ICFV56xZc1R+5xLr8se BGwpCfGOWwTiuxhdzEu2wMgOTIwENSJDM78ZjpLDIo2P3HN+WqjuBugdXc58nI2JBNds1YJwrq5O vhJsvBRfkxU9ebVV1tyE1thuCHUAaToXznt125tw0oizqqHawngqv75JfHSsZGK67sfGRM2f6fC6 M1zUfgLKJSLwSFAwdImNn/MQj3OFihZn2Vav94BGLaaT/n3Iee9fHaICd6FQdeRCOdEykmmRp/du nOVlNiWHrpqy9VaM1IouN+POYMWi2dZLuVSvS1Ish1H1ANbZi/9mJvpXngb9blntMW7RO6O7d2Ad S9uGqUKi+k9GbRmm09zVBcZW+33b5sKSzeI9dLyoqu0B/5FZ0rjIiFXVI12YfnMvXDRm5bMWDfW1 lTiuSuo+xfgNa5DbN+KvN/FS8lcl8vGruMqf5Ra94e4T9V2gW5RLqr94vbJZ57jDDkTvqsMhWYOZ TIhMVHa5yfZyog7Wl4XYE4oAyqCHkyKq6o5P3ziZQs3dDTRBeabgmSgdSKHFwxolf6SeoaWMrcBG V6xKlT8Clv23cehGcrBaDuZP4Q+nhqBePxg0cI5cLph1xya860l96f7Ub47aqbkMJPUsjFmuiW+P zreu4srsag83mArw4VyU+1U4TdNv2KrPREs2gPP6RTQzxemqIiy963D3vADEWhtQK3nnDWmWnpb0 G8OUBZIE5OKKTjfzvj1/LLpfYpv195TaHigbBNye2l7jCOogKC6/5UPwsOsD5BqyiUt9ieHGHFtI ydB5u/0nj8h4d4dC42oR7Y/vKeSOaqM+UvqhKw6whIvwNCMk03O/ZnQL9RWr9U+Ph5S8W8sXRbb+ mj0ROTArMjDwpDx23/++IfJCn3gzvo5VeZZXAbBufuU01v5MKVIMcbRw/y3YFwn8li6RXcFSGqav VG8pKqtYjpMGCyATCroqnsaImuaT23W0pmhcI93yh/XrVwdR7ZvfjAwGCdovewgMutgQHZcDIo+Q vQhMnZkoqLNPD9H3uf6oEu93vfoPYsXSjDyaKpkWlBUORRW/ro1pyy54VR4dW8fryTlJxxiAV2q6 kELTzivA4qYdUA58n2Qa3wRCSAZahvRq+u5V35y4MbdAPwobZ2KeONqCVhoXDUmxEe8c6X7349V7 RaYEwMIzFEV8NUojAxGDjnzhCQ5445D3buDXebCin7LpQ+J5WiCWdDZ4ShCrk3p8cjWW9+ohJPII JnJcYp99BDrQo2JKW/tksDWuHYQ663YR0VvrEOjRzYREUq41WkNORu2WsENHVJCmZ6W5KcW6jWEQ ujDsTExUtYtidoM5T5+GJEqSnvewMhyEPxtVe2AETvkGZovhNx+ByRH0xoHeqnGRkdRIjsH0nYmz RlDVGPGjHPl8TqeREn+G94PwHOvI+fPoKDGjIQTZ4ff6ILAqt0CAn/fJrUd0BTtXiK+fc6y+3K7N +qhoQCtZyQdA6KAgShIWDOAnVclhjKFDfGCLS7ToJs+8s89+OhuUBii2Ofxj41NpKwbyDqxpqD16 jrLYMPDLBpuRcQX6SnPdz+ZM0eH9xuGKi57ApzNQTw8WfXmtYOw8kSJw95JPdBxqj/BbdO5rcSLO eKGYw3EcitMOeLMTN4IqNrGZ0IziPgbm6KNSmjDm24uBiZzh44PU9ZHDarQ8FaUbqnZwoA1VwOvb pnsQhYSvcHzwfKJLQfMa0yxybFW5cVdNlVJOaybYwjo1/Jc6XBATuithl98q1LZCs82tQZee/xQ3 YLXnoQanU0/Mz6bwfXkXENcUZFgEKJan4se0LCj4hnvjxKn3XMZrIT3/ZKE+aov8jptBG9qGHWJm W7XDBP7w163U64b10jgVOX++WM2lOp7PxWGteIJXh7yP2RtjP6Don6FHfPfpEhx6apQU6SSqRR0A /lF2IKAWPre7aCcoYQGdb9HEtrzIevpfMxfBAAH8SsZtbIDXQDGdtPA7GrNVwcVTD3+RpzfCbJGY EX6ZRncTnhmnUAw8QbYkntvOYC1c4Z/gWUwuCGH1Zg214MuR+4RoKfZs0bRa81TcoAiJGlx56P61 ydSk0o7DjqsZ6HCkhsEc2bHlXHtZ7IVKQg0xAsFCIv87mSgPgXvn0voAjTuq8a2XdTEtYLXx6Fa3 wYigREXBo+hzdrKyFM4TELyf+qlsZmO9lO7Zcn7HoX0wBvUpOmQbIgJc2sLaww3IFxIRk1YCj6O1 OO0K5lvj/QFvpwFZFStiqoGmlXKuAGt70wugbJJ/OVulEGzVHiph8ZTS+d02XRLSgPbz5qTXdDaE uwpy+ho1hP/xVZDhDd9SiINZUrqG3XGOWtuHcBP9kkb+D5NNnrHJVb+HuapwF5vykhlWcqd/nHP2 i2MNqPu+ZlbIkKojvpV4KzE2fXqrfQu7ZPadbnRMEk4tEMIcWA0i43qCA44Y97CC+xPjQAM0lL3o ltz7x8KEGnZxh2IbozIMtPQs/G4ePzLSxXjqk5+MeLIT4NB7wOENH4vyPc7+pbrthR+GMtM98nVI QUkha2iMbJJEwgySff9J2wSOFXGU8gsjwHeHLXaueBy2T1V8gbLfhmZQs9XoeQ1ixFJL1eNZCFJd EDutsaumeB9TLGplro4AGVdIBBuQrhqEITowjWylaRf0C04gT/GtmD+g+aGbXRvOkd4PCHX9d9/s 4xmUT7JrmErOh9cEmRclY8rHkhPOpsomckp9v6W2Psz1y7IvTrrSo2B+kHxNJERYhWTelU42f9Oa RfxcoyvzDEemZYRwCHPTy2CA2fucg0o8b86PeatO5F1lmgUq1aNwg36PuDWOqr0nygB5s9cOnpxq jEo2DAX76J0GaUyfxzZuYvYxBut6LWeKa2UmCggNYa/LLbrXAyFRhjUa4l9PJ8UrOCT04uecV/px usN7fRQ23FNq7GTydLXNggyiUr8owqP21AFjYH3P8yjd1ojuPEggEGAZJrG4TW6NMP8UcOt2U4fa xcOQfou2fhpODfwAJpSCvNomyjB1d1W2qE5wMFWFfLBH/u80dNmcb3plQN33utrAnT9/KRPltOIM GDL69ouMBOyISHiijsdabco4peYO/EUxcypSmzdlAMsxiYrTk8uAyRBS1iGLLQik0oLYf1S/9dXA tiPV2IRMFODfNboNNXSBUaPZmcLpoKZdUSVoUQULyJuLF6YFPTPN+nw7ljkGvax+0lgwUWFQRn8V 894WMkY/5uHxyr42lEJ26hNs4RyeHO0EddyAPhcRXL2oR/7zIXfue0rpTdYfTd4jO+y/KYeelLgf FFDYPYMPTXAJjOuQDXaULzfGVvhom8iOi+rpMgDc07EBzrRMoT93PTC62o2PSLDBkV+BHujh23q0 ZQ+CmxJkNWPhDdjtJkH4W9XpuNd8MHkDX6C/KZ+rmAAn1vlb69hIo6zMX0AW+cyeGnOU8sTP5czn S2G2XUw5xWdQz2t69/9k24OC0sYxdw0opN0ZYFoYyxajkN4zdaAl/9NHTgZCUBNhaM8b5WmfT85j btKZPTBpGzuqjgw86JzRyv8CsiiY2cLyed70wzpWUGw6NFyZ10hAWMKRhdNW2vZT4y67clmAwafj a8s9/ticJ4gTVZ1w8+94+PofzZODREhDfq5zJjbi/Q/89fWp0JyhmaQgJec4esZNxRalB8ufbvPv 6gAHa7oY9cziUr+4FZaen4ajCtni6GllYW8D9lwXYzWPnq4kBYNkp8PFlfF2AxPQ1Y7A9/OtCu4g VvHygePzCKMDBUDtIRaLO3yyZMQZQQP+bgEet1WmjeTOa+q05//EyeTbtqPXXYjVNhDAgYjatvnW Nu5rt0bBFdkriQyp60B5B5dp4jFV/dcfggZhg1XoBVdph7TYSQULUIbW1SbBVyjNMia1mAk1fkPS Y7+COyAR7qmOE9O6j8bnQAoCIYXLfXg0s6+gG3W4tmfkGvo9dHULn42DOnORuz1kIl3fHD5OsIpv uscrF9ja4xXImrPemwkThk3WQ2P2ybucuGoQ9uf2SwI4o0OfVp0oBTq6nTpbe1hLGiwNJEIlQmYs 4un16jazmXvveSJW9Pz4rjadzxxEktXXqSReWmVsV1aD9GbFe4tYYPq96CIs0OracLSdzMmH73JJ 9bP/duC/RCF8eXMEJ43vvz8mVczjoP1zy7ymcd1RM2D1rmMVD/Mygt5KYcY4JZKot2n9hphmerO8 XffpEKsVV0q1MldNXAM8VeEMHJxKgvSDXB6oFKwHOt2oJhqnXI9FDB2XhRLRpmRbJkoEX0aiylKg yvHngtgkMReCrhDZucNUBgm3Tsh2i5MsdmF8vMSApFQAGkIo8C+RKxvdubCrDWaNwExAZ/USI4yC SaarIfd2y0PtZNKUqEx19yvFLT2hhYTu5a94mOcLInFm/v17VjvI2VPs+3Fpuu10d+XQQJgiLTD/ VWzGL6dlEtAx7HDKcSha1WNxdqJTBNeGzbmkAlYEiYdTXj5Fv3WrxheG8PuBdqhu0Pbel2AEOI8g P9QA0bKuAyzXO15fieK/yVZY5pFxP1KnI3a6b+MtFhc8ljfhFAX5DPUO1coWuVhdQhqwJQs3YgpT poYVafhVQj27/ZN80pOZjvhjOEeebtkr32ZRCINmZVXIb1KLg85wJR3/GXF8NB5fHaUlDnFlXfpu bjMwyDQ1a4BwLzSZzXyLaLtkmnzOgcBrrvOMAEUtENOrAI7T48z9BzRAZs9ex30VdNy29XOMMlqr ui+FoosVrjUMIPy77yjthnGHrkr3aQ/wRpPIJaQeuXsPgIUFEkB/2KwNPnprZl7M6kcXK7AiUKE6 MQ5X7uhYrKij8gt4ud0O2LzmAK2yLku7H2cc9yf55LRN4ZieFWiIc2bRrTPQUetJuYAdUau+4Esu 0Vh+CuvYpQn8ulB9LVSYJyvu6QqcrqIKygWZ9YMxcpXeAejbhwotW6gqjg6x+nsQzSaO3A8k31L1 ym4ZtoIK+Neo7SaBVaFNSRMgUGBz8K0xW+8rT6VgiA49xAFRzEpPsE6NDKryLFZDP8+MSs3YyV1q euBUIdnn4qQP2bdM1bmk0Ay4ex9rtqRS2IPepFe2/p1OFCWgR9OAT58hhtOWbFl4uFsurtP8yr4R ck1PFpvYzvNeJgKcYBoIx6QOY+H4X2kjx6KkQc+xmq9UrbZi8iN4JHOweliSb3qzlZ3FGZlRvqvW v1bjhfsExf3w0M1qWene5mxw8zmteDjzzwKbADFrAcmvF+WHWkBW2iRvcoa2at0j2wOonRyWkkzq qYbLvtb8BRuPa8fMkoJRhW3KlOtslHcEDsjqVnDiERTUrDYhN9gjYtEn4NxsKSPu+GrIHtxlrE0w vFK9bQX9PhxeJddzMnNJHWdaKD9Va2AFZFlOsTDaDLbaduXgzuqNlWg2+XwBcx6C5Cudsmr1Jx3M TSVCgazJJMygFRySH1LodfKMRjoTqNFgp2/uNvaKRZg3WUPWsB1JZpb/CiO3qAlRruPfZ0aKGavT mX7SYvg2s3U148Cqv6URGJ38fHLAEtyadMs3MgHcDp4FgayuJqNkJ7tdhsCiw3dFz7dWg9QWfPIj NCP2wrOuDTN0yFg/JyUdLh718zF9A616UwmVzUnEpSlkIiooqUOYVYx0J40ECR+RaH0STBTTwT35 /5IYxujzB7otdpANieEo3N09vUg0vBU67Wn3APv7DatkpZQ4dHjpEXDwWdSRgbNXMUjGe5YxqcxF 88l9jLVlGsIS0Mhaha1UUZh2AYFLtMlOEHtZWTwa7d1XtH3unJK8am7bsZZw0apBsAX9quAOAWiZ r32GeenrQVpAI+jS3zzzNbJwRLxVjzFx2kQHQGH9EDhmQ2mqS+5r6c9OYgnMEA/Ic8ErOo5j1p48 wzYahyUzyJwNENUbmaHGi1Pt66davD8XEuuqQVs0eYshKFEkU1VqJcMDvOMCH1FbCgMlYIdbIUWb 5mvfd7vq+0+XRKK3/wx8BYXj2lYq4On8N2Vw5FO5ug789cGwlatL4eNGtDHUhWS1Lpg5H7PlCr9S 0PHFJcdk9naKTngo+iQkidTGHl6r7Qllu+tIxJHvMX+OvTbqN9e/UTUGkkjrB5UQRAHQ12tkpCWk RFJoMWQ54X+8Jp3xQLtW/fV6DyFyd0P51Zo84IMVwTvvuCz0MIQgG2BRMQTX/GISr4KAQSskUh9M FEgVqJHAX+HzN7teCAVjqgV6/MMB/VO4EQmDc4jNv50byLOfI+IfoPOHHEAg9jsbVb063XwXtjiV 7Dzm2x8h5sKa8ZMoNVxDUO5+qmHUKcDyCKhnKYXn8Py2/41ShEeHJvcVKqpKblLB9l8oANeMDoH2 oV0JGm2tAOxdN/XpqHH+pN3JT1MdQstqNucr61lgAjTppFgaA5YHHJphJnP0RuJ4QrrApYB9MgsS kBQKpymLsnFCodxiJHaw9PQSQnCwZYAImTSeGMkL/s+ti7hxnXYCNe9hbunsnEMNXqiCXoBX9o8m kgbV6BZFPzgStTGUgQ3EDRvWnlw7EeKHFsXJ1ZiW1pRBIcHwRD1blemmity4ZwWXpj+ICqhHPFkz anff8b5yXXJsbhI2uIL8kXlB3E7AOxx2Hrp6rMuIvy2K4hxK7SHqPy5bdqdCj+yhLzWDwaLp47/d 5VFLo6bqPhH9a6LfrQGDujneoRPptQiQsKWQtxRgggEakLFw2IYWZbXb75ZSlZ5uDaR8SsRQkZ2k 91xWCnjhBllClS7WBhiJNrX9M6eZFzD9iUPlzmYhDTXw0QTRJD4s79vWvHaTxlW0aomYTD3Qgdji pUep/jwIoIJU6VSr7OAVTm6lN7lKN6H2DSsNQqHkmxMqFvo4+DoDSsXIHDuSmOdGzYJlsPxBxY1M tDbUz/rTy2jRMWTY3Yw9vxolygAmo1jfpwkfTf67WO27eRcqn0PgY6X1yKzIYNdEOfIJ+hx+VCjs IqZ9X1IATq8pBhbSVTC3BWcTvaWKlVzhEfT3oNyCbITvzJncrXAuMmpjrDnKB3X+/pjPUMpuUF96 99HOnceyIDzZ1ylZDMGMyRfYOetP1CwsTnZ156YFCCkAJnPwXA1Zt93EfIoyQr8I5CzyWJsQvpVd sI8+aW+IklEFtY20VWkbghZp45Mo3NX2TW59dq/Af4LrMizI8lzk5m/Y9GNjxnLRLEYmlJGpaBva PBAj6fhJQ/WIJtAvIYyxQvzFYuLfj+dxiOsvV7dP3e5zGoBbZnDeED1Hrth7K+DExEFfAGI1+LLf or2D8Qf2FQnoMNEKgajGwe4w73kW8OGlcaScepD3rXoERjf6Vs+yM40DSNVYAepkBzUiEEfmec2+ HpPBqhJPhUT0eMaCLk5p7TLhdQkFwPUT8UEKuqpRvni01FxMQgGqWPiiHuKfogATWCMlzV/0RXKg qsx/1ZdnU3F2awCi2V+YNbqLhH3uQSqkgPUZFdGbyC2zXp24Wgiqx/Oalv90tb20OrcLH8o9stJw aK+F5iELrROxMByQ4J32LkaMFxcpZdIAgqfsWUhk5+tU8h4Y427/ofFFGdKol5p3rln/17Zbtifv AX3xRpy+thbuJrAHK4e1+VDmGsO7DmCTdfY3Wnlheia4LZxAYivE8F/V7XkN7++yhFPKLEBQUkp/ QqM5ZIb/lCzXQJgrusZWEBukRaoa1awnWokUtUk5MGPd0ekMuy5NuwGR6lPE/DXu+R3yQqD22E9g L4CrDLd7FNvwI/9tFSGarhhnveo8rRkhT63GKohPTxuceleXpJR1zjxZ2llNGNRbXMlU7AjdgHa0 DClOOcNcNeglIgNUWg/foYDMw3H8p2Br0GXVCpVBjagc2rj6Ab8a/MVVVeafRtU/ULMvzdjhn209 tehwozkUSixs54DT3AkG5BND0Ek4f9AGe8tZWieJOWov5gxM3XZSSAKfIhrY0/53Qu0oDnxWZeEx Sb1JYKlFrpcQYPjBxPVGf0SXaHL6zdnU5kfuIJl7nDO3KdmXIQDC9j97lDyGcg+Z85soRtSJWl3A AFJiSxwkcQC8iI6aqWhfPOcqROOW7MpyO7AunUfuWAV6tUyPLc4VSCCtGG87h/DaVosIpmYBsQHT eEalZPOAFE4qYro+GzL72lO6DNc4nssWLvoOlQs2SkCQgaFJn4qIIW4joo/WmNJQ6jQJ8ZnCsNV9 wgKKAdWb0IB6EX10T+CypAnkhCidvxpIu84all/8+1bC5H2AwSkK1DjdeXuPMrDkLsba7epb+J3G 8uaBIosIRwqlaxeQQpolX12qPdWGTJymv1qOoyLDu0XxgA1U7SyB3t8Ipy5NDJ6M1vEIZsThRcdK GvBhd/ldYYQQjwaF70w+6Yi1hZ5m7tHG0ysnFKln1fjaDP1JLlhpMimdq0UmTtBVTo0UYNL53LMw 6UN+dC8IMxvBMepDr/3YtSRrrDbhL8xUZ5+VkZY761S5b0dh3O228dYd38I0gBGGPX86UpoX154I XacMiG3xH1DSIwtNz1U5IWhmRCzRB0HoLW2Tee6H8WtIe+zXpzBbbYRqQeY8Tko+uj0r66D8USwo V1Q1hpt04bMC2pUw4reL4fdW9vO04QiDe1GB8XUNApqSLz2Fxy2lDxGYeV9KaUC288FUbAHst9ab hv0c2RFg0zqxI5FMuWDDtey0XO2OQVCbOf8VyJe84jkSawj989HeUdXdi2DiW5cYZbGTEf9CLKlI NjFvlNeRaUinMfhPSGYf9GUIxKUevaUvtDgp6mesP73FeCB5lK9oyKVwmNwAd9Jwxh42p0pkSy/f yEIMsGRi8M4kY0xWKi8g2/J9qcd/GN1nrrYRFr7ZNurG8Bcb+4ssXOaAjs3TljWwUUky0RxQebNf RvBkg/UaAsp03qdESVSIzelZEzZ3YjTjCWTjx4Y93EkSzOJ0dsln2avvTbCXda9nH+XnEZ4hpb/P ChHZlcHGCuKt9lBtMnAop75yMAl4BjHZkIDLhcICkoIHQeLgFeuuukoIJQMPCLwDa6huyibBP5Bj HuZZHJPxbDjBS5NJXeTYQLI2RwCtATzafNdKwR4jbT8IRNIm7KezGX1nR6YBYZ2374fGqrDQcPdV 2XeRNeEUzg1UBmDKmmnVNiMlditfOMnmqJwLRUkthB5lh0pWHPkN8xhVPSygWi2s3f88o/nRvQP9 q9XNz8zyCxU8yDMU9Pbnh/CHqegdkhtPb0bxXetruyxbpEZ4qSgZMEImlE7aPFP1l4tKR3UeUg0l GkXqfNa8BtveFw7jni1Hc+z2X3pf64d/XGPW5KHvBS7oJDCwLBnteIquPc++fGx0L3nbvmZc8KJp buW5Ia1i7ZurcOk0XePyyTnkc7/WSSwX6uhptsWYXJ+VPAEaigyRObIvIN60ENDG28oGTzHA7zou hZppTKajEqwGhEHeK0PPFzS3EL/9XZ1jJ3kqh3fSy8UZ2+cqntBkAOuKYhFEIrKwEIScHzbPnBxw uIQhaXjJke/Ywiq79YXDP416F7F19uRD4Y4OAOqsI9YN2z9ZB3NbKkxEQywhDiwWg55sQMpb/Tu/ uskNZeqmLM8jt6c/agzZwnVcsheajaLY2bEBn+lYsdRrU5oroJLew4pXMDhrfJ7oY1iI005LBkeh 6clhyfypqxoz4Sk2CclJpgV+TfWsMlNxgWZ/Av6EkGlG+D2zWbrfHkVeDH/rp1NdY+8YfBtF+hip Vza6uaB1NKtRFfjPVa4UnVg+h+VHW9Jq9hqs29hQeBC46K7ssP0KgVJK3Bm7CGfb0J/w4EJyAxI6 6jJRa4CW9Msr+W/9hYSmd7UlnPc+y5Fm+kl9EYj+csU9sB52LQWB1ZvT9ebM+Jzf3c6RuJEsjiDr js9fBU+QhnEVqUFoLb/oinshf0yMFzw14Ph4ZzfxiC8JsSSuVQ7jC9G3cNzvAzs4eWPvByfxUQWN sV/kMEQmTWdeLux+SAEfn+RbNo42dSiTnSm+vPWVSVi/tSjUBOqBaBD4c1DnLh+75xSutmxZiZCZ ZVhIqpc7YsB6kXgQglPWD96uxPoDCD1HACpZamewzltIFErr9Tp7XfX2xH8gPl6ibiKZ8D2yW8PB JmetTCVvKb3jslLh27K+tglhvYxqZsvNvMLobzLYMpgSN48XB0YHDSJsxFUHdG6b04di+/yY4hPd Z7ZOE7IKbdp3ensL2FLOHqqO+r01MWTME9yk5PFCZzG9CIGsHbRP+K3TeAd3VHQqPe57scQRLmUP St2g2b6ZmtyLvMMpen+kWneEj+cO9UdJl3xCVOla0iWtZ/na5Yx+AxYPyEWFArWck7+lyb2Di21b NUPcJPV67rBQrmrfY4esarZV52Azr6Z0jEPUVryK+jKlj6rRfVqNJcNavNPV4fd5eW+nJapTlhdb 5EmtehsAIvUfQnk+I9Qe7vuvVBYv00JWQvm6kXU/w9cqH6303skp0KXVhYj0mgwvdoUrvjJoKzoz fvTCvpjFDS2rZluvZX4lFyUTRnogYWPGPN5HzzP0cMjB8zoDH8zIuC/UEHKK7ElvszWcIe8+idxn rXAoVkxx/oAkZ3d12E65w5zUyYocsppqj8WQ4IZomCZ97xFlE3QNFivgcUnyfZhvamTsxdFZPZmq 6oLriQWIZ/6F1c9hq7H5C9Id/58hRVnR0BKZ1mEnKkxwvvqWtV8Qv7NMzUNuU/TpqSoIyOGBaY2o R+vnlkb4XmRUYTskB9d3YK2K8KFx7IZJTzi0C4eTiGhPw5MS5aShKi03lQe2Tw4Hu7QZ7wihxq4l kCmcG/DmM0Vb0TmN9ixRZvVOgwDcFtZ5e3583nL/w/hvWJFk+TI8kDFIOWmHY+cNguyZ6FJ6w1Bw YeANAJC7u1UF4Xq5uVHiKd2gU/wNd/TXeTMxyr7mHNCV2g3UgfTY60Rr3gDL/4X63nR7gCmIUTfj 7GAI/Hribfi9/FScm+hLkWaca/CA96cfk5hNenCBB7CJzwd7bwOisTSlSJCRLaL0Y5xtvJr85Xx5 uB8CDAnE59jxDJ0Vgh6gUdfLv4Pjssqw0IBe/D0F5lQEuNAtHXDZGhPlc5u9h94fdtwSrGnbtP1z nJ9aNVklZhWsg6a2U5wsBRFogq9VpEXk8MbkClJkgUTQQn1cFkzKgZBZy3GVgwIeL/n6RILPOGny 0eWxiwLjmT8Nneidp72Kj+Kxt7QfAcGfrkTbN05hH11l6q5S5W5F8/N6hCA3R0eX3QoCHCfzSepw 6c1O2d/f8kP+T7xTktYtqHXQfjBJbjBFWSZpXu3R5KG5Q+2FKfcOv/NNd3dV0AJ9lqhXRZVsZNrQ Kylfw9Cps+fQnPTbB+eSxkiHkZR8s147q2pxk4LpsRpFA949zFRVdl0GrYyl/LguF91h5p2sCuv1 ePQualm7ShJQR8CskMCaw8PM0D5xcT9cMuGrV0zGk0gxttPqBUD5ltv7NZakRy1QuuA6u0jGE+1T Zi57iPzgzweEp8J9q1RaVczC8k+3bu924elEy+lVRGv7Fryp7oRs9bQmmUxxbOiKx1mqwhzpL8Vj bmVO1WYXdWmXfc3v1DMJxlwb7CBlLLEiSrMC/ny/jdvcTbbXkASa/QXhsoZ8tGOhodM9BYVru7vb dgAFXzrsXfaNY/Qdhm0Q5nk8qF6y0BOaxql7JxUeGYEr9yCLYRgCq1yp//NQBNTYX8unPQyVr8tz KQ4kWhuENzlLKuiCWMwWyOR70ZSNxKEbTI8toI6KmiM7s3OO/1rVivOtqd11geIe99dUjzKPBII5 4VxZDQ/Xa5O342rsbtgT4w6CfOjb9VyRNBGhKxNmzKJY0ACfftuCrddjCGwvx/U8B4Rn8oVVeYQu WDh7f8d3//jY9YvaFKLR8Pomj4MunNIarOtTTXZI2kn82jAOJwVEqfDY/eHhtaBHdkzoa02Z3lMq iItvfoKUtwxMyqhclMd9l2aLsjnLrYON7UExH6eTP172RkKopGYDfu1ZSjFXTo9vokhrzlc5pVE+ 5CqU5IoidEEOt+tj07obkL9+Fvu3xpiW90F0Q+saVINTv7DiDR1oUf4Nb8KuuwCuh7BLrDHgFxsI 1wtRaZ713nYoZvsy26kFaqktbt1AJte0q1zBf8nIrhaUZE3fw4SyTp5Wc6le6byOkrdMPjebhoor JbsO2E8sfdWwPFKxG4Jw3uH6IS3SbUC9ljieuds4l3W6PFJoZnkCRLB4cQt/DAM+mTQbIw0rH9x0 97+n+VSZRed1vAg3NYrs6JR2QiqBX+sfUovdOGmTuyP2BCWc+LxiTGg5rHIvwcUNx1t/pp8fxIwu xm7HayypTMNDnnxW/TQxZqryKw18zzmBwNUaIB0bGV4PodP7teAoKokmXEg02VZmTJ7P8hTAA7C7 agmAR1zuTL+YGo9PFZ/NhOz4bV9LbRUR/MdBOIWcBobeJe7PUpZW4Ku6mCiRuvfcd8XtefFn/VYk 4efdAwH1OrOhZnHV+PWY2vqtUuBG5e+OBsT+zB5JebVXjMHiatqlfOgtcXJ53HmM8FpthU7nFrAY fUGrb5VyrKTJ2KGHGjSIisQfuDcJLEkNts02Ko7F0cMjYmfuowJOZCEHx3LUsGmDP7G7LsErsoSv S457pMULWRX2o1vYBG75qCyFWHA1hoRWSRsVS68TI74tXlMtpp1pM/lPxbc8C8StbUUpfXyck080 qxcYLWYNgIWQdS7eUdf0+up1eFJXO6pE88LA2f/9SgyUfjqf3Jxg5PcwiUBACidD1TPp+R3mSVkW bdb0dU8lZQj297MI/qbMEsg/2Im41SVperCQ2EdeElspb2ct9i76Tss6KCMSdYhQtHDnvVhD8gpf d2csYkCxvJtTco6PV+FDYx5l2ZCX6RKVKniVt/GmpMBwGDUAPMdUv0+O3Yusl3WbVQUbEKAUKKaN xHnGk7Ogs1aTU99fSYD/fTjuYdn0eX6R/K8hsw+KY1T59rBS3s0kGhzWJ36mA5Fgzjpe4PMGvenh 1AhVKK5mHnMPite+w/zv7z+wIc2S5A458iqCH/TvxoX/pV5H9/ndD3YtfyjHRqKspw9IA6gJ96on hI8dgRfK4ADlOV9Z9IjWXoX0OP/twmWhxNsUWQAw93zEVgAtGgP+6PscC6h/JJ42js1niNWf18nc w4GRwFe2PxzK76gvIwrciS4lByFGv5wg7QvBpLufw4QqEHWUKHBstin7Bo+QhFMKB0Blheehk70Y pxRNjRCp1OG3+4RAS2HXxV6PNPrNh89upi7zb01eALzsPUbECXuSgvbSAm8BHlC11RA42qVy6kw3 +UOio/UPX1zg4hXhRkfqkrZZ3C+UN7VCMUvHrxCPKcC0mYSWtDpam712e33MMsq+ho8lZ7NAAcnC C6nmRwFlS3/N+MdUwFeKEIlvf10Ev+TrS999Xmo4/Y2Ze2OexqOPgftx1L4pObXJdiyG6Q0U3/UE FgUc4C1dKoQQiWSKRpimsydmoD1nokbwsK9lb2Oqqf5gLHjoZjmH8t6pp3fS3tbrykEiZRPdP0Lu tHHNg11F//kV5hYqWuCItz54oB4H5rYeRqBffOFB8/5XDibrXxFhELZdp4ZE49ogUtKNxyrxd9L0 TpkA3prkXzJqiZVUjURxr01s+Cmi6I7/1oonIU4ukAgp+oVMHC/q3I/XbftY0dzAQf5xK7lkZCXC Vzo4JuHJi7sFxjBj5NYR24d5eFNMpFX4DWVfp6a7agTji4dDR6e5GhOXA+sR+vSQFoHnUzgiXnpp Toypic0p0XZefIyEZ4QkW+WXj1ndIIlV87qvooA0T7WmMC0dBvNuJeJeSfO28tb36BRmjL5kKQi2 pYCK0VT3d1g2nAS+d+dCU33LJY/LX7N64t/WdX/+JbjnJErhhj771G5LY3qViQtiSankxwd2ZPrx Fbs1OIimpnLPCU169Ky472/StIZSQOy3ChwCl/ENfJX7IwqF0v3tUwj7YSfqECdo4+hSQ6OvRp8o upDcQTes1pRimYIg3NK1iIs6yvS/eXcLbyZc8bpTn12eC4e/nZgGo0vQIqbFkVZessrwTTQ0On/i bd7salIRJOu5vRvvRCahuBweiS23fQN0WkUa7YrWD52jGpekApyNiXbOMttIK91IV8fSHwezfTLj rsnJXRXZXGBglJiAH+Y5ZIdG/s44rsBC0Y5gbCNRfGkl54REjHhNSP4AItY3T6U94ZxhneTfj2Lx mVmnrwmgFp0PcJtpU/Dtue5X8fDdGRotwGF/7VmhB5Ks9SXAhYiI6TTKImwGOIfEi+PTQbKXPUts 9Mb2qDLxiqTvIj1gP7CFe1Asfj+5rgNgP4KplBneakQkXFntTy29YSRMUfYo9h7zhIdHNpUMO9I= `protect end_protected	bsd-2-clause	41cacbc2d7285e31c37d69cbb876e16f	0.947056	1.844521	false	false	false	false
Yarr/Yarr-fw	sim/sim_aurora_channel.vhd	1	6,777	---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/11/2017 04:01:21 PM -- Design Name: -- Module Name: sim_aurora_channel - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. library UNISIM; use UNISIM.VComponents.all; entity sim_aurora_channel is -- Port ( ); end sim_aurora_channel; architecture Behavioral of sim_aurora_channel is component aurora_rx_channel generic ( g_NUM_LANES : integer range 1 to 4 := 1 ); port ( -- Sys connect rst_n_i : in std_logic; clk_rx_i : in std_logic; -- Fabric clock (serdes/8) clk_serdes_i : in std_logic; -- IO clock -- Input enable_i : in std_logic; rx_data_i_p : in std_logic_vector(g_NUM_LANES-1 downto 0); rx_data_i_n : in std_logic_vector(g_NUM_LANES-1 downto 0); trig_tag_i : in std_logic_vector(63 downto 0); -- Output rx_data_o : out std_logic_vector(63 downto 0); rx_valid_o : out std_logic; rx_stat_o : out std_logic_vector(7 downto 0) ); end component aurora_rx_channel; component scrambler port ( data_in : in std_logic_vector(0 to 63); data_out : out std_logic_vector(65 downto 0); enable : in std_logic; sync_info : in std_logic_vector(1 downto 0); clk : in std_logic; rst : in std_logic ); end component scrambler; signal rst_n_i : std_logic := '0'; signal rst2_n_i : std_logic := '0'; signal clk_rx_i : std_logic := '0'; signal clk_serdes_i : std_logic := '0'; signal clk_ddr_i : std_logic := '0'; signal enable_i : std_logic := '0'; signal rx_data_i_p : std_logic := '0'; signal rx_data_i_n : std_logic := '0'; signal trig_tag_i : std_logic_vector(63 downto 0) := (others => '0'); signal rx_data_o : std_logic_vector(63 downto 0); signal rx_valid_o : std_logic; signal rx_stat_o : std_logic_vector(7 downto 0); constant RX_CLK_PERIOD : time := 6.4ns; constant SERDES_CLK_PERIOD : time := 1.6ns; constant DDR_CLK_PERIOD : time := 0.8ns; constant IDELAY_CLK_PERIOD : time := 3.2ns; signal tx_data : std_logic_vector(65 downto 0); signal tx_data_s : std_logic_vector(65 downto 0); signal tx_data_t : std_logic_vector(65 downto 0); signal tx_counter : unsigned(31 downto 0); signal cnt : unsigned(31 downto 0); signal clk_idelay : std_logic; signal idelay_rdy : std_logic; signal tx_data_valid : std_logic; attribute IODELAY_GROUP : STRING; attribute IODELAY_GROUP of IDELAYCTRL_inst : label is "aurora"; begin rx_clk_proc: process begin clk_rx_i <= '1'; wait for RX_CLK_PERIOD/2; clk_rx_i <= '0'; wait for RX_CLK_PERIOD/2; end process rx_clk_proc; serdes_clk_proc: process begin clk_serdes_i <= '1'; wait for SERDES_CLK_PERIOD/2; clk_serdes_i <= '0'; wait for SERDES_CLK_PERIOD/2; end process serdes_clk_proc; ddr_clk_proc: process begin clk_ddr_i <= '1'; wait for DDR_CLK_PERIOD/2; clk_ddr_i <= '0'; wait for DDR_CLK_PERIOD/2; end process ddr_clk_proc; idelay_clk_proc: process begin clk_idelay <= '1'; wait for IDELAY_CLK_PERIOD/2; clk_idelay <= '0'; wait for IDELAY_CLK_PERIOD/2; end process idelay_clk_proc; IDELAYCTRL_inst : IDELAYCTRL port map ( RDY => idelay_rdy, -- 1-bit output: Ready output REFCLK => clk_idelay, -- 1-bit input: Reference clock input RST => not rst_n_i -- 1-bit input: Active high reset input ); rst_proc: process begin rst_n_i <= '0'; rst2_n_i <= '0'; wait for 200ns; rst2_n_i <= '1'; wait for 350ns; rst_n_i <= '1'; wait; end process rst_proc; aurora_cmp: aurora_rx_channel port map ( rst_n_i => rst_n_i, clk_rx_i => clk_rx_i, clk_serdes_i => clk_serdes_i, enable_i => enable_i, rx_data_i_p(0) => rx_data_i_p, rx_data_i_n(0) => rx_data_i_n, trig_tag_i => trig_tag_i, rx_data_o => rx_data_o, rx_valid_o => rx_valid_o, rx_stat_o => rx_stat_o ); piso_proc: process(clk_rx_i, clk_ddr_i, rst2_n_i) begin if (rst2_n_i = '0') then tx_data <= (others => '1'); tx_counter <= to_unsigned(1, 32); cnt <= (others => '0'); tx_data_t <= (others => '0'); tx_data_valid <= '0'; elsif rising_edge(clk_ddr_i) then --tx_data_valid <= '0'; rx_data_i_p <= tx_data_t(65);-- after 3.3ns; rx_data_i_n <= not tx_data_t(65);-- after 3.3ns; tx_data_t <= tx_data_t(64 downto 0) & '0'; -- rx_data_i_p <= tx_data_t(0); -- rx_data_i_n <= not tx_data_t(0); -- tx_data_t <= '0' & tx_data_t(65 downto 1); tx_counter <= tx_counter + 1; if (tx_counter = 64) then if (to_integer(cnt) mod 64 = 0) then tx_data <= "01" & std_logic_vector(cnt) & std_logic_vector(cnt); else tx_data <= "10" & std_logic_vector(cnt) & std_logic_vector(cnt); end if; tx_data_valid <= '1'; tx_counter <= tx_counter + 1; --tx_data <= "01" & x"0123456789abcdef"; cnt <= cnt + 1; elsif (tx_counter = 65) then tx_data_valid <= '0'; tx_data_t <= tx_data_s; tx_counter <= (others => '0'); end if; end if; end process piso_proc; scrambler_cmp: scrambler port map ( data_in => tx_data(63 downto 0), data_out => tx_data_s(65 downto 0), enable => tx_data_valid, sync_info => tx_data(65 downto 64), clk => clk_ddr_i, rst => not rst2_n_i ); end Behavioral;	gpl-3.0	a28a48b5839e2fec9a3bbd6e72a19fcd	0.510993	3.415827	false	false	false	false
zcold/fft.vhdl	src/array_slicer.vhdl	1	2,077	-- The MIT License (MIT) -- Copyright (c) 2014 Shuo Li -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- The above copyright notice and this permission notice shall be included in all -- copies or substantial portions of the Software. -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -- SOFTWARE. --------------- -- array slicer --------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity array_slicer is generic ( data_width : integer := 16; array_length : integer := 8; address_width : integer := 3 ); port ( array_in : in std_logic_vector(array_length * data_width - 1 downto 0); address_in : in std_logic_vector(address_width - 1 downto 0); data_out : out std_logic_vector(data_width - 1 downto 0) ); end array_slicer; -- Function Implementation 0 architecture FIMP_0 of array_slicer is signal address_integer : integer range 0 to array_length - 1; signal address_unsigned : unsigned(address_width - 1 downto 0); begin address_integer <= to_integer(address_unsigned); address_unsigned <= unsigned(address_in); data_out <= array_in((address_integer + 1) * data_width - 1 downto address_integer * data_width); end FIMP_0;	mit	5620d7aab528e085540f6897ff0a0c36	0.705826	4.112871	false	false	false	false
Jorge9314/ElectronicaDigital	Impresora2D/antirebote_tb.vhd	1	1,132	LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY antirebote_tb IS END antirebote_tb; ARCHITECTURE behavior OF antirebote_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT antirebote PORT( CLK : IN std_logic; a : IN std_logic; b : OUT std_logic ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal a : std_logic := '0'; --Outputs signal b : std_logic; -- Clock period definitions constant CLK_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: antirebote PORT MAP ( CLK => CLK, a => a, b => b ); -- Clock process definitions CLK_process : process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin a <= '0'; wait for 100ms; a <= '1'; wait for 100ms; a <= '0'; wait for 10ms; a <= '1'; wait for 50ms; a <= '0'; wait for 60ms; a <= '1'; wait for 50ms; a <= '0'; wait; end process; END;	gpl-3.0	90a53cb6f4f769698b3d9bacbdcf5785	0.54947	3.162011	false	false	false	false
rjarzmik/mips_processor	MEM/Memory_access_tb.vhd	1	9,225	------------------------------------------------------------------------------- -- Title : Testbench for design "Memory_access" -- Project : ------------------------------------------------------------------------------- -- File : Memory_access_tb.vhd -- Author : Simon Desfarges -- Company : -- Created : 2016-11-28 -- Last update: 2016-12-14 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Very simple testbench for the memory stage module. ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-28 1.0 simon Created library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cpu_defs.all; ------------------------------------------------------------------------------- entity Memory_access_tb is end entity Memory_access_tb; ------------------------------------------------------------------------------- architecture tb of Memory_access_tb is -- component generics constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; -- component ports signal clk : std_logic := '0'; signal rst : std_logic := '1'; signal stall_req : std_logic; signal kill_req : std_logic := '0'; signal o_exception : std_logic; signal i_reg1 : register_port_type; signal i_reg2 : register_port_type; signal i_mem_op : memory_op_type; signal i_mem_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_is_jump : std_logic; signal i_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal o_reg1 : register_port_type; signal o_reg2 : register_port_type; signal o_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal o_is_jump : std_logic; signal o_stage1_reg1 : register_port_type; signal o_stage1_reg2 : register_port_type; signal o_stage2_reg1 : register_port_type; signal o_stage2_reg2 : register_port_type; signal i_mem_rd_valid : std_logic; signal i_mem_rd_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_mem_wr_en : std_logic; signal o_mem_word_width : std_logic; signal i_mem_wr_ack : std_logic; signal o_mem_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal o_mem_wr_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_need_stall : std_logic; signal i_dbg_mem_pc : std_logic_vector(ADDR_WIDTH -1 downto 0); signal o_dbg_mem_pc : std_logic_vector(ADDR_WIDTH -1 downto 0); begin -- architecture tb -- component instantiation DUT : entity work.Memory_access generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH) port map ( clk => clk, rst => rst, stall_req => stall_req, kill_req => kill_req, o_exception => o_exception, i_reg1 => i_reg1, i_reg2 => i_reg2, i_mem_op => i_mem_op, i_mem_data => i_mem_data, i_is_jump => i_is_jump, i_jump_target => i_jump_target, o_reg1 => o_reg1, o_reg2 => o_reg2, o_jump_target => o_jump_target, o_is_jump => o_is_jump, o_stage1_reg1 => o_stage1_reg1, o_stage1_reg2 => o_stage1_reg2, o_stage2_reg1 => o_stage2_reg1, o_stage2_reg2 => o_stage2_reg2, i_mem_rd_valid => i_mem_rd_valid, i_mem_rd_data => i_mem_rd_data, o_mem_wr_en => o_mem_wr_en, o_mem_word_width => o_mem_word_width, i_mem_wr_ack => i_mem_wr_ack, o_mem_addr => o_mem_addr, o_mem_wr_data => o_mem_wr_data, o_need_stall => o_need_stall, i_dbg_mem_pc => i_dbg_mem_pc, o_dbg_mem_pc => o_dbg_mem_pc ); -- clock generation clk <= not clk after 10 ns; -- waveform generation WaveGen_Proc : process begin -- constant signals stall_req <= '0'; kill_req <= '0'; i_is_jump <= '0'; i_jump_target <= X"01234567"; rst <= '1'; i_reg2.idx <= 8; i_reg2.we <= '0'; i_reg2.data <= X"FEDCBA98"; i_reg1.idx <= 5; i_reg1.we <= '1'; i_reg1.data <= (others => '0'); -- none, loadw, storew, load8, load8_signextend32, store8 i_mem_op <= none; i_mem_data <= (others => '0'); wait until clk = '1'; wait until clk = '1'; rst <= '0'; -- Testing mem_op == none... i_mem_op <= none; i_reg2.idx <= 1; i_reg2.we <= '0'; i_reg2.data <= X"00000001"; i_reg1.idx <= 5; i_reg1.we <= '1'; i_reg1.data <= (others => '0'); wait until clk = '1'; i_reg2.idx <= 2; i_reg2.we <= '1'; i_reg2.data <= X"00000002"; i_reg1.idx <= 3; i_reg1.we <= '0'; i_reg1.data <= X"AAAAAAAA"; wait until clk = '1'; -- Testing mem_op == loadw... i_mem_op <= loadw; i_reg2.idx <= 2; i_reg2.we <= not i_reg2.we; i_reg2.data <= X"00000002"; i_reg1.idx <= 4; i_reg1.we <= '1'; i_reg1.data <= X"01234567"; wait until clk = '1'; -- Testing mem_op == none... i_mem_op <= none; i_reg2.idx <= 1; i_reg2.we <= '0'; i_reg2.data <= X"00000001"; i_reg1.idx <= 5; i_reg1.we <= '1'; i_reg1.data <= (others => '0'); wait until clk = '1'; -- Testing mem_op == load8... i_mem_op <= load8; i_reg2.idx <= 1; i_reg2.we <= '1'; i_reg2.data <= X"00011111"; i_reg1.idx <= 4; i_reg1.we <= '1'; i_reg1.data <= X"89ABCDEF"; wait until clk = '1'; -- Testing mem_op == load8_signextend32... i_mem_op <= load8_signextend32; i_reg2.idx <= 2; i_reg2.we <= '0'; i_reg2.data <= X"00011111"; i_reg1.idx <= 6; i_reg1.we <= '1'; i_reg1.data <= X"01234567"; wait until clk = '1'; -- Testing mem_op == storew... i_mem_op <= storew; i_reg2.idx <= 2; i_reg2.we <= '0'; i_reg2.data <= X"00011111"; i_reg1.idx <= 3; i_reg1.we <= '0'; i_reg1.data <= X"0000FFFF"; i_mem_data <= X"ABABABAB"; wait until clk = '1'; -- 1 cycle stall wait until clk = '1'; i_mem_op <= none; wait until clk = '1'; wait until clk = '1'; wait until clk = '1'; -- Testing mem_op == store8... i_mem_op <= store8; i_reg2.idx <= 2; i_reg2.we <= '0'; i_reg2.data <= X"00011111"; i_reg1.idx <= 1; i_reg1.we <= '0'; i_reg1.data <= X"FFFF0000"; i_mem_data <= X"DFDFDFDF"; wait until clk = '1'; wait until clk = '1'; -- 1 cycle stall -- Testing mem_op == load8... i_mem_op <= load8; i_reg2.idx <= 1; i_reg2.we <= '1'; i_reg2.data <= X"00011111"; i_reg1.idx <= 4; i_reg1.we <= '1'; i_reg1.data <= X"89ABCDEF"; stall_req <= '1'; wait until clk = '1'; wait until clk = '1'; wait until clk = '1'; wait until clk = '1'; stall_req <= '0'; wait until clk = '1'; i_mem_op <= none; i_reg1.we <= '0'; report "end of simulation"; wait; end process WaveGen_Proc; -- purpose: memory -- type : sequential -- inputs : clk, rst -- outputs: mem : process (clk, rst) is begin -- process mem if rst = '1' then -- asynchronous reset (active low) i_mem_rd_valid <= '0'; i_mem_rd_data <= (others => '0'); i_mem_wr_ack <= '0'; elsif rising_edge(clk) then -- rising clock edge i_mem_wr_ack <= '0'; if o_mem_wr_en = '1' then i_mem_rd_valid <= '0'; i_mem_rd_data <= i_mem_rd_data; assert i_mem_wr_ack = '0' report "Invalid transaction" severity error; i_mem_wr_ack <= '1'; else -- copy rd @ to data and change data order (ABCD -> DCBA) i_mem_rd_data <= o_mem_addr(3 downto 0) & o_mem_addr(7 downto 4) & o_mem_addr(11 downto 8) & o_mem_addr(15 downto 12) & o_mem_addr(19 downto 16) & o_mem_addr(23 downto 20) & o_mem_addr(27 downto 24) & o_mem_addr(31 downto 28); i_mem_rd_valid <= '1'; end if; end if; end process mem; -- purpose: handles the PC -- type : sequential -- inputs : clk, rst -- outputs: dbg_pc : process (clk, rst) is begin -- process dbg_pc if rst = '1' then -- asynchronous reset (active low) i_dbg_mem_pc <= (others => '0'); elsif rising_edge(clk) then -- rising clock edge if stall_req = '0' and o_need_stall = '0' then i_dbg_mem_pc <= std_logic_vector(unsigned(i_dbg_mem_pc) + 4); end if; end if; end process dbg_pc; end architecture tb; -------------------------------------------------------------------------------	gpl-3.0	cba065bfd14c349abd377b377584a8da	0.477507	3.101883	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/constant/rule_013_test_input.fixed.vhd	1	607	architecture RTL of ENTITY1 is constant c_size : integer := 5; constant c_ones : std_logic_vector(c_size - 1 downto 0) := (others => '1'); constant c_zeros : std_logic_vector(c_size - 1 downto 0) := (others => '0'); signal data : std_logic_vector(c_size - 1 downto 0); begin data <= c_ones; PROC_NAME : process () is begin data <= c_ones & c_zeros; if (sig2 = '0') then data <= c_zeros; end if; if (sig2 = '1') then data <= c_ones; end if; if (sig3 = '1') then data <= c_zeros; end if; end process PROC_NAME; end architecture RTL;	gpl-3.0	6247d8659a310af9defb2a91caed303a	0.565074	3.050251	false	false	false	false
kjellhar/axi_mmc	sim/dat_if_standalone_1bit/dat_if_standalone_1bit.vhd	1	4,071	---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11/29/2014 09:07:43 PM -- Design Name: -- Module Name: dat_if_standalone_1bit - testbench -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dat_if_standalone_1bit is -- Port ( ); end dat_if_standalone_1bit; architecture testbench of dat_if_standalone_1bit is constant clk100M_per : time := 10 ns; component mmc_dat_if is Port ( clk : in std_logic; clk_en : in std_logic; reset : in std_logic; receive_dat_trigger_i : in std_logic; transmit_dat_trigger_i : in std_logic; dat_block_finished_o : out std_logic; bus_width_i : in std_logic_vector (1 downto 0); data_fifo_out_i : in std_logic_vector (31 downto 0); data_fifo_out_wr_i : in std_logic; data_fifo_out_full_o : out std_logic; data_fifo_in_o : out std_logic_vector (31 downto 0); data_fifo_in_rd_i : in std_logic; data_fifo_in_empty_o : out std_logic; dat_out_o : out std_logic_vector (7 downto 0); dat_in_i : in std_logic_vector (7 downto 0) ); end component; signal test_en : std_logic := '1'; signal clk100M : std_logic := '0'; signal reset : std_logic := '1'; signal clk_en : std_logic := '0'; signal receive_dat_trigger : std_logic := '0'; signal transmit_dat_trigger : std_logic := '0'; signal dat_block_finished : std_logic; signal bus_width : std_logic_vector (1 downto 0) := "00"; signal data_fifo_out : std_logic_vector (31 downto 0); signal data_fifo_out_wr : std_logic := '0'; signal data_fifo_out_full : std_logic; signal data_fifo_in : std_logic_vector (31 downto 0) := X"00000000"; signal data_fifo_in_rd : std_logic := '0'; signal data_fifo_in_empty : std_logic; signal dat_out : std_logic_vector (7 downto 0); signal dat_in : std_logic_vector (7 downto 0) := X"00"; begin u_dut : mmc_dat_if Port map ( clk => clk, clk_en => clk_en, reset => reset, receive_dat_trigger_i => receive_dat_trigger, transmit_dat_trigger_i => transmit_dat_trigger, dat_block_finished_o => dat_block_finished, bus_width_i => bus_width, data_fifo_out_i => data_fifo_out, data_fifo_out_wr_i => data_fifo_out_wr, data_fifo_out_full_o => data_fifo_out_full, data_fifo_in_o => data_fifo_in, data_fifo_in_rd_i => data_fifo_in_rd, data_fifo_in_empty_o => data_fifo_in_empty, dat_out_o => dat_out, dat_in_i => dat_in ); -- Clock generator process begin if test_en='1' then clk100M <= '1', '0' after clk100M_per/2; wait for clk100M_per; else wait; end if; end process; -- Testbench stimuli process begin test_en <= '1'; reset <= '1'; wait for 100 ns; reset <= '0'; wait for 10*clk100M_per; wait until rising_edge(clk100M); wait for 200 ns; test_en <= '0'; wait; end process; end testbench;	mit	870a7995e3f75571afc49ad05cb2a932	0.517809	3.690843	false	true	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_reset.vhd	1	23,163	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_reset.vhd -- -- Description: -- This file implements the DataMover Reset module. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg_reset.vhd -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_sg_reset is generic ( C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0 -- 0 = Use Synchronous Command/Statys User Interface -- 1 = Use Asynchronous Command/Statys User Interface ); port ( -- Primary Clock and Reset Inputs ----------------- -- primary_aclk : in std_logic; -- primary_aresetn : in std_logic; -- --------------------------------------------------- -- Async operation clock and reset from User ------ -- Used for Command/Status User interface -- -- synchronization when C_STSCMD_IS_ASYNC = 1 -- -- secondary_awclk : in std_logic; -- secondary_aresetn : in std_logic; -- --------------------------------------------------- -- Halt request input control ------------------------------- halt_req : in std_logic; -- -- Active high soft shutdown request (can be a pulse) -- -- -- Halt Complete status flag -- halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Soft Shutdown internal interface ------------------------------------------------ -- flush_stop_request : Out std_logic; -- -- Active high soft stop request to modules -- -- data_cntlr_stopped : in std_logic; -- -- Active high flag indicating the data controller is flushed and stopped -- -- addr_cntlr_stopped : in std_logic; -- -- Active high flag indicating the address controller is flushed and stopped -- -- aux1_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 1 module -- -- Tie high if unused -- -- aux2_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 2 module -- -- Tie high if unused -- ------------------------------------------------------------------------------------ -- HW Reset outputs to reset groups ------------------------------------- -- cmd_stat_rst_user : Out std_logic; -- -- The reset to the Command/Status Module User interface side -- -- cmd_stat_rst_int : Out std_logic; -- -- The reset to the Command/Status Module internal interface side -- -- mmap_rst : Out std_logic; -- -- The reset to the Memory Map interface side -- -- stream_rst : Out std_logic -- -- The reset to the Stream interface side -- -------------------------------------------------------------------------- ); end entity axi_sg_reset; architecture implementation of axi_sg_reset is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Signals signal sig_cmd_stat_rst_user_n : std_logic := '0'; signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0'; signal sig_cmd_stat_rst_int_reg_n : std_logic := '0'; signal sig_mmap_rst_reg_n : std_logic := '0'; signal sig_stream_rst_reg_n : std_logic := '0'; signal sig_syncd_sec_rst : std_logic := '0'; -- soft shutdown support signal sig_internal_reset : std_logic := '0'; signal sig_s_h_halt_reg : std_logic := '0'; signal sig_halt_cmplt : std_logic := '0'; -- additional CDC synchronization signals signal sig_sec_neg_edge_plus_delay : std_logic := '0'; signal sig_secondary_aresetn_reg : std_logic := '0'; signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0'; signal sig_prim2sec_rst_reg2_n : std_logic := '0'; begin --(architecture implementation) -- Assign outputs cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n); cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; mmap_rst <= not(sig_mmap_rst_reg_n) or sig_syncd_sec_rst; stream_rst <= not(sig_stream_rst_reg_n) or sig_syncd_sec_rst; -- Internal logic Implmentation ------------------------------------------------------------ -- If Generate -- -- Label: GEN_SYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Synchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate begin sig_syncd_sec_rst <= '0'; sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from); end generate GEN_SYNC_CMDSTAT_RESET; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ASYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Asynchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate signal sig_sec_reset_in_reg_n : std_logic := '0'; -- Secondary reset pulse stretcher signal sig_secondary_dly1 : std_logic := '0'; signal sig_secondary_dly2 : std_logic := '0'; signal sig_neg_edge_detect : std_logic := '0'; signal sig_sec2prim_reset : std_logic := '0'; signal sig_sec2prim_reset_reg : std_logic := '0'; signal sig_sec2prim_reset_reg2 : std_logic := '0'; signal sig_sec2prim_rst_syncro1 : std_logic := '0'; signal sig_sec2prim_rst_syncro2 : std_logic := '0'; begin -- Generate the reset in the primary clock domain. Use the longer -- of the pulse stretched reset or the actual reset. sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or sig_sec2prim_rst_syncro2; -- Check for falling edge of secondary_aresetn input sig_neg_edge_detect <= '1' when (sig_sec_reset_in_reg_n = '1' and secondary_aresetn = '0') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSE_STRETCH_FLOPS -- -- Process Description: -- This process implements a 3 clock wide pulse whenever the -- secondary reset is asserted -- ------------------------------------------------------------- IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then If (sig_secondary_dly2 = '1') Then sig_secondary_dly1 <= '0' ; sig_secondary_dly2 <= '0' ; Elsif (sig_neg_edge_detect = '1') Then sig_secondary_dly1 <= '1'; else sig_secondary_dly2 <= sig_secondary_dly1 ; End if; end if; end process IMP_PUSE_STRETCH_FLOPS; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_NEG_EDGE -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- negative edge detection, -- ------------------------------------------------------------- SYNC_NEG_EDGE : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or sig_secondary_dly1 or sig_secondary_dly2; end if; end process SYNC_NEG_EDGE; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO -- -- Process Description: -- This process registers the secondary reset input to -- the primary clock domain. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_sec2prim_reset_reg <= sig_sec_neg_edge_plus_delay ; sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg; end if; end process SEC2PRIM_RST_SYNCRO; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SEC_RST -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- secondary reset input, -- ------------------------------------------------------------- REG_SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_secondary_aresetn_reg <= secondary_aresetn; end if; end process REG_SEC_RST; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO_2 -- -- Process Description: -- Second stage (destination) synchronizers for the secondary -- reset CDC to the primary clock. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then -- CDC sig_sec2prim_rst_syncro1 <= not(secondary_aresetn); sig_sec2prim_rst_syncro1 <= not(sig_secondary_aresetn_reg); sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1; end if; end process SEC2PRIM_RST_SYNCRO_2; -- Generate the Command and Status side reset sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and sig_prim2sec_rst_reg2_n; -- CDC sig_cmd_stat_rst_user_reg_n_cdc_from; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_RESET_ASYNC -- -- Process Description: -- This process registers the secondary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_RESET_ASYNC : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_reset_in_reg_n <= secondary_aresetn; end if; end process REG_RESET_ASYNC; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_PRIM2SEC_RST -- -- Process Description: -- Second (destination clock) stage synchronizers for CDC of -- primary reset input, -- ------------------------------------------------------------- SYNC_PRIM2SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from; sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to; end if; end process SYNC_PRIM2SEC_RST; -- end generate GEN_ASYNC_CMDSTAT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_PRIM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_PRIM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn; end if; end process REG_CMDSTAT_PRIM_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_INT_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status internal interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_INT_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_int_reg_n <= primary_aresetn; end if; end process REG_CMDSTAT_INT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_MMAP_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Memory Map interface reset. -- ------------------------------------------------------------- REG_MMAP_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_rst_reg_n <= primary_aresetn; end if; end process REG_MMAP_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_STREAM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Stream interface reset. -- ------------------------------------------------------------- REG_STREAM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_stream_rst_reg_n <= primary_aresetn; end if; end process REG_STREAM_RESET; -- Soft Shutdown logic ------------------------------------------------------ sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; flush_stop_request <= sig_s_h_halt_reg; halt_cmplt <= sig_halt_cmplt; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_HALT_REQ -- -- Process Description: -- Implements a sample and hold flop for the halt request -- input. Can only be cleared on a HW reset. -- ------------------------------------------------------------- REG_HALT_REQ : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_s_h_halt_reg <= '0'; elsif (halt_req = '1') then sig_s_h_halt_reg <= '1'; else null; -- hold current state end if; end if; end process REG_HALT_REQ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT -- -- Process Description: -- Implements a the flop for the halt complete status -- output. Can only be cleared on a HW reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_halt_cmplt <= '0'; elsif (data_cntlr_stopped = '1' and addr_cntlr_stopped = '1' and aux1_stopped = '1' and aux2_stopped = '1') then sig_halt_cmplt <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT; end implementation;	bsd-2-clause	ea60dcc25f9b538eb0c591bbb73ceced	0.412425	5.469421	false	false	false	false
NicoLedwith/Dr.AluOpysel	RAT_MCU/PC.vhd	1	1,385	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.all; entity PC is port ( RST,CLK,PC_LD,PC_OE,PC_INC : in std_logic; FROM_IMMED : in std_logic_vector (9 downto 0); FROM_STACK : in std_logic_vector (9 downto 0); FROM_INTRR : in std_logic_vector (9 downto 0); PC_MUX_SEL : in std_logic_vector (1 downto 0); PC_COUNT : out std_logic_vector (9 downto 0); PC_TRI : out std_logic_vector(9 downto 0)); end PC; architecture my_count of PC is signal s_cnt : std_logic_vector(9 downto 0); begin process (CLK, RST, PC_LD, PC_INC) begin if (RST = '1') then s_cnt <= "0000000000"; -- asynchronous clear elsif (rising_edge(CLK)) then if (PC_LD = '1') then case PC_MUX_SEL is when "00" => s_cnt <= FROM_IMMED; when "01" => s_cnt <= FROM_STACK; when "10" => s_cnt <= FROM_INTRR; when others => s_cnt <= "0000000000"; end case; else if (PC_INC = '1') then s_cnt <= s_cnt + 1; -- increment else s_cnt <= s_cnt; -- hold end if; end if; end if; end process; process (PC_OE, s_cnt) begin if(PC_OE = '1') then PC_TRI <= s_cnt; else PC_TRI <= "ZZZZZZZZZZ"; end if; end process; PC_COUNT <= s_cnt; end my_count;	mit	e8a1640982361209b02344e3b1512c1d	0.530686	2.928118	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/instantiation/rule_008_test_input.vhd	1	407	architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below u_inst1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;	gpl-3.0	b12e9763e637e8f31e60c2ab3c7fae10	0.481572	2.787671	false	false	false	false
Yarr/Yarr-fw	rtl/spartan6/rx-core/decode_8b10b/decode_8b10b_bram.vhd	2	12,996	--------------------------------------------------------------------------- -- -- Module : decode_8b10b_bram.vhd -- -- Version : 1.1 -- -- Last Update : 2008-10-31 -- -- Project : 8b/10b Decoder Reference Design -- -- Description : Block memory-based Decoder for decoding 8b/10b encoded symbols -- -- Company : Xilinx, Inc. -- -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ------------------------------------------------------------------------------- -- -- History -- -- Date Version Description -- -- 10/31/2008 1.1 Initial release -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.std_logic_unsigned.ALL; USE STD.textio.ALL; -- required to initialize bram from .mif library work; USE work.decode_8b10b_pkg.ALL; ----------------------------------------------------------------------------- -- Entity Declaration ----------------------------------------------------------------------------- ENTITY decode_8b10b_bram IS GENERIC ( C_ELABORATION_DIR : STRING := "./../../src/"; C_HAS_BPORTS : INTEGER := 0; C_HAS_DISP_IN : INTEGER := 0; C_HAS_DISP_IN_B : INTEGER := 0; C_HAS_DISP_ERR : INTEGER := 0; C_HAS_DISP_ERR_B : INTEGER := 0; C_HAS_RUN_DISP : INTEGER := 0; C_HAS_RUN_DISP_B : INTEGER := 0; C_HAS_SYM_DISP : INTEGER := 0; C_HAS_SYM_DISP_B : INTEGER := 0; C_HAS_ND : INTEGER := 0; C_HAS_ND_B : INTEGER := 0; C_SINIT_DOUT : STRING := "00000000"; C_SINIT_DOUT_B : STRING := "00000000"; C_SINIT_KOUT : INTEGER := 0; C_SINIT_KOUT_B : INTEGER := 0; C_SINIT_RUN_DISP : INTEGER := 0; C_SINIT_RUN_DISP_B : INTEGER := 0 ); PORT ( CLK : IN STD_LOGIC := '0'; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; KOUT : OUT STD_LOGIC ; CE : IN STD_LOGIC := '0'; CE_B : IN STD_LOGIC := '0'; CLK_B : IN STD_LOGIC := '0'; DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000"; DISP_IN : IN STD_LOGIC := '0'; DISP_IN_B : IN STD_LOGIC := '0'; SINIT : IN STD_LOGIC := '0'; SINIT_B : IN STD_LOGIC := '0'; CODE_ERR : OUT STD_LOGIC := '0'; CODE_ERR_B : OUT STD_LOGIC := '0'; DISP_ERR : OUT STD_LOGIC := '0'; DISP_ERR_B : OUT STD_LOGIC := '0'; DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; KOUT_B : OUT STD_LOGIC ; ND : OUT STD_LOGIC := '0'; ND_B : OUT STD_LOGIC := '0'; RUN_DISP : OUT STD_LOGIC ; RUN_DISP_B : OUT STD_LOGIC ; SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END decode_8b10b_bram; ----------------------------------------------------------------------------- -- Architecture ----------------------------------------------------------------------------- ARCHITECTURE xilinx OF decode_8b10b_bram IS ----------------------------------------------------------------------------- -- .MIF file support ----------------------------------------------------------------------------- -- Specify relative path for .mif file CONSTANT mif_file_name : STRING := "dec.mif"; -- Initialize inferred ROM from mif file TYPE RomType IS ARRAY(0 TO 1023) OF BIT_VECTOR(13 DOWNTO 0); IMPURE FUNCTION InitRomFromFile (RomFileName : IN STRING) RETURN RomType IS FILE RomFile : TEXT OPEN READ_MODE IS RomFileName; VARIABLE RomFileLine : LINE; VARIABLE ROM : RomType; BEGIN FOR I IN RomType'range LOOP READLINE (RomFile, RomFileLine); READ (RomFileLine, ROM(I)); END LOOP; RETURN ROM; END FUNCTION; SIGNAL ROM : RomType := InitRomFromFile(mif_file_name); ----------------------------------------------------------------------------- -- Constant initialization values for internal signals ROM_data(_b) ----------------------------------------------------------------------------- CONSTANT INIT_DATA : STRING := concat_sinit(C_SINIT_RUN_DISP,C_SINIT_KOUT, C_SINIT_DOUT); CONSTANT INIT_DATA_B : STRING := concat_sinit(C_SINIT_RUN_DISP_B,C_SINIT_KOUT_B, C_SINIT_DOUT_B); ----------------------------------------------------------------------------- -- Signal Declarations ----------------------------------------------------------------------------- SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) := str_to_slv(C_SINIT_DOUT,8); SIGNAL kout_i : STD_LOGIC := bint_2_sl(C_SINIT_KOUT); SIGNAL dout_b_i : STD_LOGIC_VECTOR(7 DOWNTO 0) := str_to_slv(C_SINIT_DOUT_B,8); SIGNAL kout_b_i : STD_LOGIC := bint_2_sl(C_SINIT_KOUT_B); SIGNAL run_disp_i : STD_LOGIC := bint_2_sl(C_SINIT_RUN_DISP); SIGNAL run_disp_b_i : STD_LOGIC := bint_2_sl(C_SINIT_RUN_DISP_B); SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := conv_std_logic_vector(C_SINIT_RUN_DISP,2); SIGNAL sym_disp_b_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := conv_std_logic_vector(C_SINIT_RUN_DISP_B,2); --Internal signals tied to the 14x1k block memory---------------------------- SIGNAL ROM_address : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); SIGNAL ROM_data : STD_LOGIC_VECTOR(13 DOWNTO 0) := str_to_slv(INIT_DATA, 14); ----------------------------------------------------------------------------- -- BEGIN ARCHITECTURE ----------------------------------------------------------------------------- BEGIN -- Map internal signals to outputs DOUT <= dout_i; KOUT <= kout_i; DOUT_B <= dout_b_i; KOUT_B <= kout_b_i; RUN_DISP <= run_disp_i; RUN_DISP_B <= run_disp_b_i; SYM_DISP <= sym_disp_i; SYM_DISP_B <= sym_disp_b_i; ----------------------------------------------------------------------------- -- Decoder A ----------------------------------------------------------------------------- ROM_address <= DIN; PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN IF (CE = '1') THEN IF (SINIT = '1') THEN ROM_data <= str_to_slv(INIT_DATA, 14) AFTER TFF; ELSE ROM_data <= to_stdlogicvector(ROM(conv_integer(ROM_address))) AFTER TFF; END IF; END IF; END IF; END PROCESS; -- Map ROM data into dout, kout, and code_err outputs dout_i <= ROM_data(7 DOWNTO 0); kout_i <= ROM_data(8); CODE_ERR <= ROM_data(9); ----------------------------------------------------------------------------- -- Instantiate disparity logic block for Decoder A ----------------------------------------------------------------------------- dla : entity work.decode_8b10b_disp GENERIC MAP( C_SINIT_DOUT => C_SINIT_DOUT, C_SINIT_RUN_DISP => C_SINIT_RUN_DISP, C_HAS_DISP_IN => C_HAS_DISP_IN, C_HAS_DISP_ERR => C_HAS_DISP_ERR, C_HAS_RUN_DISP => C_HAS_RUN_DISP, C_HAS_SYM_DISP => C_HAS_SYM_DISP ) PORT MAP( SINIT => SINIT, CE => CE, CLK => CLK, SYM_DISP => ROM_data(13 DOWNTO 10), DISP_IN => DISP_IN, RUN_DISP => run_disp_i, DISP_ERR => DISP_ERR, USER_SYM_DISP => sym_disp_i ); -- create ND output gndr : IF (C_HAS_ND = 1) GENERATE PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN IF ((SINIT = '1') AND (CE = '1')) THEN ND <= '0' AFTER TFF; ELSE ND <= CE AFTER TFF; END IF; END IF; END PROCESS; END GENERATE gndr; ------------------------------------------------------------------------------- -- Generate Decoder B ------------------------------------------------------------------------------- gdp : IF (C_HAS_BPORTS=1) GENERATE --Internal signals tied to the 14x1k block memory (B)---------------------- SIGNAL ROM_address_b : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); SIGNAL ROM_data_b : STD_LOGIC_VECTOR(13 DOWNTO 0) := str_to_slv(INIT_DATA_B, 14); BEGIN ROM_address_b <= DIN_B; PROCESS (CLK_B) BEGIN IF (CLK_B'event AND CLK_B = '1') THEN IF (CE_B = '1') THEN IF (SINIT_B = '1') THEN ROM_data_b <= str_to_slv(INIT_DATA_B, 14) AFTER TFF; ELSE ROM_data_b <= to_stdlogicvector(ROM(conv_integer(ROM_address_b))) AFTER TFF; END IF; END IF; END IF; END PROCESS; -- Map ROM_data_b into dout_b, kout_b, and code_err_b outputs dout_b_i <= ROM_data_b(7 DOWNTO 0); kout_b_i <= ROM_data_b(8); CODE_ERR_B <= ROM_data_b(9); ----------------------------------------------------------------------------- -- Instantiate disparity logic block for Decoder B ----------------------------------------------------------------------------- dlb : entity work.decode_8b10b_disp GENERIC MAP( C_SINIT_DOUT => C_SINIT_DOUT_B, C_SINIT_RUN_DISP => C_SINIT_RUN_DISP_B, C_HAS_DISP_IN => C_HAS_DISP_IN_B, C_HAS_DISP_ERR => C_HAS_DISP_ERR_B, C_HAS_RUN_DISP => C_HAS_RUN_DISP_B, C_HAS_SYM_DISP => C_HAS_SYM_DISP_B ) PORT MAP( SINIT => SINIT_B, CE => CE_B, CLK => CLK_B, SYM_DISP => ROM_data_b(13 DOWNTO 10), DISP_IN => DISP_IN_B, RUN_DISP => run_disp_b_i, DISP_ERR => DISP_ERR_B, USER_SYM_DISP => sym_disp_b_i ); -- create ND_B output gndbr : IF (C_HAS_ND_B = 1) GENERATE PROCESS (CLK_B) BEGIN IF (CLK_B'event AND CLK_B = '1') THEN IF ((SINIT_B = '1') AND (CE_B = '1')) THEN ND_B <= '0' AFTER TFF; ELSE ND_B <= CE_B AFTER TFF; END IF; END IF; END PROCESS; END GENERATE gndbr; END GENERATE gdp; END xilinx;	gpl-3.0	f705c8114bd7875e31d34524e798f294	0.453909	4.044818	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/conditional_waveforms/rule_500_test_input.fixed_upper.vhd	1	400	architecture rtl of fifo is begin process begin var1 := '0' WHEN rd_en = '1' else '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' WHEN rd_en = '1' else '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1'; concurrent_wr_en_b <= '0' WHEN rd_en = '1' else '1'; end architecture rtl;	gpl-3.0	7deef51b2f7f8b6b2037627ef9dd5775	0.54	2.564103	false	false	false	false
Nibble-Knowledge/peripheral-ethernet	vhdl-serial/DCM32MhzTo9600Hz.vhd	1	3,069	-------------------------------------------------------------------------------- -- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 14.7 -- \ \ Application : xaw2vhdl -- / / Filename : DCM32MhzTo9600Hz.vhd -- /___/ /\ Timestamp : 03/03/2016 20:22:17 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-intstyle C:/Users/Yakov/OneDrive/School/University Stuff/ENEL500/test232/ipcore_dir/DCM32MhzTo9600Hz.xaw -st DCM32MhzTo9600Hz.vhd --Design Name: DCM32MhzTo9600Hz --Device: xc3s250e-4vq100 -- -- Module DCM32MhzTo9600Hz -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST -- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 5.17 ns library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity DCM32MhzTo9600Hz is port ( CLKIN_IN : in std_logic; CLKFX_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic); end DCM32MhzTo9600Hz; architecture BEHAVIORAL of DCM32MhzTo9600Hz is signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLKIN_IBUFG_INST : IBUFG port map (I=>CLKIN_IN, O=>CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_SP_INST : DCM_SP generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 32, CLKFX_MULTIPLY => 9, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 31.250, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, PSINCDEC=>GND_BIT, RST=>GND_BIT, CLKDV=>open, CLKFX=>CLKFX_BUF, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>open, PSDONE=>open, STATUS=>open); end BEHAVIORAL;	unlicense	eeaa4d06b336b75da4ea1eabf6e4af10	0.491691	3.693141	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/process/rule_029_test_input.fixed_event.vhd	1	434	architecture RTL of FIFO is begin process begin if (rst = c_asserted) then elsif (clk'event and clk = '1') then end if; if (rst = c_asserted) then elsif (clk'event and clk = '0') then end if; if (rst = c_asserted) then elsif (clk'event and clk = '1') then end if; if (rst = c_asserted) then elsif (clk'event and clk = '0') then end if; end process; end architecture RTL;	gpl-3.0	2bb78cc1890c957da9960692aad3115f	0.589862	3.287879	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/wr_chnl.vhd	1	186,977	------------------------------------------------------------------------------- -- wr_chnl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: wr_chnl.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller write channel interfaces. Controls all -- handshaking and data flow on the AXI write address (AW), -- write data (W) and write response (B) channels. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/3/2011 v1.03a -- ~~~~~~ -- Edits for scalability and support of 512 and 1024-bit data widths. -- ^^^^^^ -- JLJ 2/10/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter. -- ^^^^^^ -- JLJ 2/14/2011 v1.03a -- ~~~~~~ -- Shift Hsiao ECC generate logic so not dependent on C_S_AXI_DATA_WIDTH. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update WE size based on 128-bit ECC configuration. -- Update for usage of ecc_gen.vhd module directly from MIG. -- Clean-up XST warnings. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Found issue with ECC decoding on read path. Remove MSB '0' usage -- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Code clean-up. -- Move all MIG functions to package body. -- ^^^^^^ -- JLJ 2/28/2011 v1.03a -- ~~~~~~ -- Fix mapping on BRAM_WE with bram_we_int for 128-bit w/ ECC. -- ^^^^^^ -- JLJ 3/1/2011 v1.03a -- ~~~~~~ -- Fix XST handling for DIV functions. Create seperate process when -- divisor is not constant and a power of two. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. And general code clean-up. -- Fix double clock assertion of CE/UE error flags when asserted -- during the RMW sequence. -- ^^^^^^ -- JLJ 3/23/2011 v1.03a -- ~~~~~~ -- Code clean-up. -- ^^^^^^ -- JLJ 3/30/2011 v1.03a -- ~~~~~~ -- Add code coverage on/off statements. -- ^^^^^^ -- JLJ 4/8/2011 v1.03a -- ~~~~~~ -- Modify back-to-back capability to remove combinatorial loop -- on WREADY to AXI interface. Add internal constant, C_REG_WREADY. -- Update axi_wready_int reset value (ensure it is '0'). -- -- Create new SM for C_REG_WREADY with dual port. Seperate assertion of BVALID -- from WREADY. Create a FIFO to store AWID/BID values. -- Use counter (with max of 8 ID values) to allow WREADY assertions -- to be ahead of BVALID assertions. -- Add sub module, SRL_FIFO. -- ^^^^^^ -- JLJ 4/11/2011 v1.03a -- ~~~~~~ -- Implement similar updates on WREADY for single port & ECC configurations. -- Remove use of signal, axi_wready_sng with constant, C_REG_WREADY. -- -- For single port operation with registered WREADY, provide BVALID counter -- value to arbitration SM, add output signal, AW2Arb_BVALID_Cnt. -- -- Create an additional SM for single port when C_REG_WREADY. -- ^^^^^^ -- JLJ 4/14/2011 v1.03a -- ~~~~~~ -- Remove attempt to create AXI write data pipeline full flag outside of SM -- logic. Add corner case checks for BID FIFO/BVALID counter. -- ^^^^^^ -- JLJ 4/15/2011 v1.03a -- ~~~~~~ -- Clean up all code not related to C_REG_WREADY. -- Goal to remove internal constant, C_REG_WREADY. -- Work on size optimization. Implement signals to represent BVALID -- counter values. -- ^^^^^^ -- JLJ 4/20/2011 v1.03a -- ~~~~~~ -- Code clean up. Remove unused signals. -- Remove additional generate blocks with C_REG_WREADY. -- ^^^^^^ -- JLJ 4/21/2011 v1.03a -- ~~~~~~ -- Code clean up. Remove use of IF_IS_AXI4 constant. -- Create new SM TYPE for each configuration. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Add check in data SM on back-to-back for BVALID counter max. -- Clean up AXI_WREADY generate blocks. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 5/26/2011 v1.03a -- ~~~~~~ -- Fix CR # 609695. -- Modify usage of WLAST. Ensure that WLAST is qualified with -- WVALID/WREADY assertions. -- -- With CR # 609695, update else clause for narrow_burst_cnt_ld to -- remove simulation warnings when axi_byte_div_curr_awsize = zero. -- -- Catch code clean up with WLAST in data SM for axi_wr_burst_cmb -- signal assertion. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.srl_fifo; use work.wrap_brst; use work.ua_narrow; use work.checkbit_handler; use work.checkbit_handler_64; use work.correct_one_bit; use work.correct_one_bit_64; use work.ecc_gen; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity wr_chnl is generic ( -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type C_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) C_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_SUPPORTS_NARROW : INTEGER := 1; -- Support for narrow burst operations C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to "AXI4LITE" to optimize out burst transaction support C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0 -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ); port ( -- AXI Global Signals S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI Write Address Channel Signals (AW) AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_AWADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0); AXI_AWLEN : in std_logic_vector(7 downto 0); -- Specifies the number of data transfers in the burst -- "0000 0000" 1 data transfer -- "0000 0001" 2 data transfers -- ... -- "1111 1111" 256 data transfers AXI_AWSIZE : in std_logic_vector(2 downto 0); -- Specifies the max number of data bytes to transfer in each data beat -- "000" 1 byte to transfer -- "001" 2 bytes to transfer -- "010" 3 bytes to transfer -- ... AXI_AWBURST : in std_logic_vector(1 downto 0); -- Specifies burst type -- "00" FIXED = Fixed burst address (handled as INCR) -- "01" INCR = Increment burst address -- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary -- "11" Reserved (not checked) AXI_AWLOCK : in std_logic; -- Currently unused AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused AXI_AWVALID : in std_logic; AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) AXI_WDATA : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); AXI_WSTRB : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0); AXI_WLAST : in std_logic; AXI_WVALID : in std_logic; AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_BRESP : out std_logic_vector(1 downto 0); AXI_BVALID : out std_logic; AXI_BREADY : in std_logic; -- ECC Register Interface Signals Enable_ECC : in std_logic; BRAM_Addr_En : out std_logic := '0'; FaultInjectClr : out std_logic := '0'; CE_Failing_We : out std_logic := '0'; Sl_CE : out std_logic := '0'; Sl_UE : out std_logic := '0'; Active_Wr : out std_logic := '0'; FaultInjectData : in std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0); FaultInjectECC : in std_logic_vector (C_ECC_WIDTH-1 downto 0); -- Single Port Arbitration Signals Arb2AW_Active : in std_logic; AW2Arb_Busy : out std_logic := '0'; AW2Arb_Active_Clr : out std_logic := '0'; AW2Arb_BVALID_Cnt : out std_logic_vector (2 downto 0) := (others => '0'); Sng_BRAM_Addr_Rst : out std_logic := '0'; Sng_BRAM_Addr_Ld_En : out std_logic := '0'; Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); Sng_BRAM_Addr_Inc : out std_logic := '0'; Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- BRAM Write Port Interface Signals BRAM_En : out std_logic := '0'; BRAM_WE : out std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC(1+(C_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); BRAM_WrData : out std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); end entity wr_chnl; ------------------------------------------------------------------------------- architecture implementation of wr_chnl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Set constants for AWLEN equal to a count of one or two beats. constant AXI_AWLEN_ONE : std_logic_vector (7 downto 0) := (others => '0'); constant AXI_AWLEN_TWO : std_logic_vector (7 downto 0) := "00000001"; constant AXI_AWSIZE_ONE : std_logic_vector (2 downto 0) := "001"; -- Determine maximum size for narrow burst length counter -- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits -- resulting in a count 3 downto 0 => so minimum counter width = 2 bits. -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits -- resulting in a count 31 downto 0 => so minimum counter width = 5 bits. constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8); constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- AXI Size Constants -- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte -- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes -- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM -- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM -- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM -- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM -- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM -- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM -- Determine max value of ARSIZE based on the AXI data width. -- Use function in axi_bram_ctrl_funcs package. constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH); -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" -- Move to full_axi module -- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8); -- Not used -- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8; -- AXI Burst Types -- AXI Spec 4.4 constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10"; constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01"; constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00"; -- Internal ECC data width size. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Write Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type WR_ADDR_SM_TYPE is ( IDLE, LD_AWADDR ); signal wr_addr_sm_cs, wr_addr_sm_ns : WR_ADDR_SM_TYPE; signal aw_active_set : std_logic := '0'; signal aw_active_set_i : std_logic := '0'; signal aw_active_clr : std_logic := '0'; signal delay_aw_active_clr_cmb : std_logic := '0'; signal delay_aw_active_clr : std_logic := '0'; signal aw_active : std_logic := '0'; signal aw_active_d1 : std_logic := '0'; signal aw_active_re : std_logic := '0'; signal axi_awaddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal curr_awaddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0'); signal awaddr_pipe_ld : std_logic := '0'; signal awaddr_pipe_ld_i : std_logic := '0'; signal awaddr_pipe_sel : std_logic := '0'; -- '0' indicates mux select from AXI -- '1' indicates mux select from AW Addr Register signal axi_awaddr_full : std_logic := '0'; signal axi_awid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_awsize_pipe : std_logic_vector(2 downto 0) := (others => '0'); signal curr_awsize : std_logic_vector(2 downto 0) := (others => '0'); signal curr_awsize_reg : std_logic_vector (2 downto 0) := (others => '0'); -- Narrow Burst Signals signal curr_narrow_burst_cmb : std_logic := '0'; signal curr_narrow_burst : std_logic := '0'; signal curr_narrow_burst_en : std_logic := '0'; signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_addr_rst : std_logic := '0'; signal narrow_addr_ld_en : std_logic := '0'; signal narrow_addr_dec : std_logic := '0'; signal axi_awlen_pipe : std_logic_vector(7 downto 0) := (others => '0'); signal axi_awlen_pipe_1_or_2 : std_logic := '0'; signal curr_awlen : std_logic_vector(7 downto 0) := (others => '0'); signal curr_awlen_reg : std_logic_vector(7 downto 0) := (others => '0'); signal curr_awlen_reg_1_or_2 : std_logic := '0'; signal axi_awburst_pipe : std_logic_vector(1 downto 0) := (others => '0'); signal axi_awburst_pipe_fixed : std_logic := '0'; signal curr_awburst : std_logic_vector(1 downto 0) := (others => '0'); signal curr_wrap_burst : std_logic := '0'; signal curr_wrap_burst_reg : std_logic := '0'; signal curr_incr_burst : std_logic := '0'; signal curr_fixed_burst : std_logic := '0'; signal curr_fixed_burst_reg : std_logic := '0'; signal max_wrap_burst_mod : std_logic := '0'; signal axi_awready_int : std_logic := '0'; signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_d2 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; signal axi_aresetn_re_reg : std_logic := '0'; -- BRAM Address Counter signal bram_addr_ld_en : std_logic := '0'; signal bram_addr_ld_en_i : std_logic := '0'; signal bram_addr_ld_en_mod : std_logic := '0'; signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_inc : std_logic := '0'; signal bram_addr_inc_mod : std_logic := '0'; signal bram_addr_inc_wrap_mod : std_logic := '0'; signal bram_addr_rst : std_logic := '0'; signal bram_addr_rst_cmb : std_logic := '0'; signal narrow_bram_addr_inc : std_logic := '0'; signal narrow_bram_addr_inc_d1 : std_logic := '0'; signal narrow_bram_addr_inc_re : std_logic := '0'; signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal curr_ua_narrow_wrap : std_logic := '0'; signal curr_ua_narrow_incr : std_logic := '0'; signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Write Data Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type WR_DATA_SM_TYPE is ( IDLE, W8_AWADDR, -- W8_BREADY, SNG_WR_DATA, BRST_WR_DATA, -- NEW_BRST_WR_DATA, B2B_W8_WR_DATA --, -- B2B_W8_BRESP, -- W8_BRESP ); signal wr_data_sm_cs, wr_data_sm_ns : WR_DATA_SM_TYPE; type WR_DATA_SNG_SM_TYPE is ( IDLE, SNG_WR_DATA, BRST_WR_DATA ); signal wr_data_sng_sm_cs, wr_data_sng_sm_ns : WR_DATA_SNG_SM_TYPE; type WR_DATA_ECC_SM_TYPE is ( IDLE, RMW_RD_DATA, RMW_CHK_DATA, RMW_MOD_DATA, RMW_WR_DATA ); signal wr_data_ecc_sm_cs, wr_data_ecc_sm_ns : WR_DATA_ECC_SM_TYPE; -- Wr Data Buffer/Register signal wrdata_reg_ld : std_logic := '0'; signal axi_wready_int : std_logic := '0'; signal axi_wready_int_mod : std_logic := '0'; signal axi_wdata_full_cmb : std_logic := '0'; signal axi_wdata_full : std_logic := '0'; signal axi_wdata_empty : std_logic := '0'; signal axi_wdata_full_reg : std_logic := '0'; -- WE Generator Signals signal clr_bram_we_cmb : std_logic := '0'; signal clr_bram_we : std_logic := '0'; signal bram_we_ld : std_logic := '0'; signal axi_wr_burst_cmb : std_logic := '0'; signal axi_wr_burst : std_logic := '0'; signal wr_b2b_elgible : std_logic := '0'; -- CR # 609695 signal last_data_ack : std_logic := '0'; -- CR # 609695 signal last_data_ack_throttle : std_logic := '0'; signal last_data_ack_mod : std_logic := '0'; -- CR # 609695 signal w8_b2b_bresp : std_logic := '0'; signal axi_wlast_d1 : std_logic := '0'; signal axi_wlast_re : std_logic := '0'; -- Single Port Signals -- Write busy flags only used in ECC configuration -- when waiting for BVALID/BREADY handshake signal wr_busy_cmb : std_logic := '0'; signal wr_busy_reg : std_logic := '0'; -- Only used by ECC register module. signal active_wr_cmb : std_logic := '0'; signal active_wr_reg : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Response Channel Signals ------------------------------------------------------------------------------- signal axi_bid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_bid_temp_full : std_logic := '0'; signal axi_bid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_bvalid_int : std_logic := '0'; signal axi_bvalid_set_cmb : std_logic := '0'; ------------------------------------------------------------------------------- -- Internal BRAM Signals ------------------------------------------------------------------------------- signal reset_bram_we : std_logic := '0'; signal set_bram_we_cmb : std_logic := '0'; signal set_bram_we : std_logic := '0'; signal bram_we_int : std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC(1+(C_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal bram_en_cmb : std_logic := '0'; signal bram_en_int : std_logic := '0'; signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_wrdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- ECC Signals ------------------------------------------------------------------------------- signal CorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1); signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence signal WrData : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal WrData_cmb : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal UE_Q : std_logic := '0'; ------------------------------------------------------------------------------- -- BVALID Signals ------------------------------------------------------------------------------- signal bvalid_cnt_inc : std_logic := '0'; signal bvalid_cnt_inc_d1 : std_logic := '0'; signal bvalid_cnt_dec : std_logic := '0'; signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0'); signal bvalid_cnt_amax : std_logic := '0'; signal bvalid_cnt_max : std_logic := '0'; signal bvalid_cnt_non_zero : std_logic := '0'; ------------------------------------------------------------------------------- -- BID FIFO Signals ------------------------------------------------------------------------------- signal bid_fifo_rst : std_logic := '0'; signal bid_fifo_ld_en : std_logic := '0'; signal bid_fifo_ld : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal bid_fifo_rd_en : std_logic := '0'; signal bid_fifo_rd : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal bid_fifo_not_empty : std_logic := '0'; signal bid_gets_fifo_load : std_logic := '0'; signal bid_gets_fifo_load_d1 : std_logic := '0'; signal first_fifo_bid : std_logic := '0'; signal b2b_fifo_bid : std_logic := '0'; ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- AXI Write Address Channel Output Signals --------------------------------------------------------------------------- AXI_AWREADY <= axi_awready_int; --------------------------------------------------------------------------- -- AXI Write Data Channel Output Signals --------------------------------------------------------------------------- -- WREADY same signal assertion regardless of ECC or single port configuration. AXI_WREADY <= axi_wready_int_mod; --------------------------------------------------------------------------- -- AXI Write Response Channel Output Signals --------------------------------------------------------------------------- AXI_BRESP <= axi_bresp_int; AXI_BVALID <= axi_bvalid_int; AXI_BID <= axi_bid_int; --------------------------------------------------------------------------- -- * AXI Write Address Channel Interface * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_AW_PIPE_SNG -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AW_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- Unused AW pipeline (set default values) awaddr_pipe_ld <= '0'; axi_awaddr_pipe <= AXI_AWADDR; axi_awid_pipe <= AXI_AWID; axi_awsize_pipe <= AXI_AWSIZE; axi_awlen_pipe <= AXI_AWLEN; axi_awburst_pipe <= AXI_AWBURST; axi_awlen_pipe_1_or_2 <= '0'; axi_awburst_pipe_fixed <= '0'; axi_awaddr_full <= '0'; end generate GEN_AW_PIPE_SNG; --------------------------------------------------------------------------- -- Generate: GEN_AW_PIPE_DUAL -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AW_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin ----------------------------------------------------------------------- -- -- AXI Write Address Buffer/Register -- (mimic behavior of address pipeline for AXI_AWID) -- ----------------------------------------------------------------------- GEN_AWADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate begin REG_AWADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awaddr_pipe (i) <= AXI_AWADDR (i); else axi_awaddr_pipe (i) <= axi_awaddr_pipe (i); end if; end if; end process REG_AWADDR; end generate GEN_AWADDR; ----------------------------------------------------------------------- -- Register AWID REG_AWID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awid_pipe <= AXI_AWID; else axi_awid_pipe <= axi_awid_pipe; end if; end if; end process REG_AWID; --------------------------------------------------------------------------- -- In parallel to AWADDR pipeline and AWID -- Use same control signals to capture AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST. -- Register AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST REG_AWCTRL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awsize_pipe <= AXI_AWSIZE; axi_awlen_pipe <= AXI_AWLEN; axi_awburst_pipe <= AXI_AWBURST; else axi_awsize_pipe <= axi_awsize_pipe; axi_awlen_pipe <= axi_awlen_pipe; axi_awburst_pipe <= axi_awburst_pipe; end if; end if; end process REG_AWCTRL; --------------------------------------------------------------------------- -- Create signals that indicate value of AXI_AWLEN in pipeline stage -- Used to decode length of burst when BRAM address can be loaded early -- when pipeline is full. -- -- Add early decode of AWBURST in pipeline. REG_AWLEN_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then -- Create merge to decode AWLEN of ONE or TWO if (AXI_AWLEN = AXI_AWLEN_ONE) or (AXI_AWLEN = AXI_AWLEN_TWO) then axi_awlen_pipe_1_or_2 <= '1'; else axi_awlen_pipe_1_or_2 <= '0'; end if; -- Early decode on value in pipeline of AWBURST if (AXI_AWBURST = C_AXI_BURST_FIXED) then axi_awburst_pipe_fixed <= '1'; else axi_awburst_pipe_fixed <= '0'; end if; else axi_awlen_pipe_1_or_2 <= axi_awlen_pipe_1_or_2; axi_awburst_pipe_fixed <= axi_awburst_pipe_fixed; end if; end if; end process REG_AWLEN_PIPE; --------------------------------------------------------------------------- -- Create full flag for AWADDR pipeline -- Set when write address register is loaded. -- Cleared when write address stored in register is loaded into BRAM -- address counter. REG_WRADDR_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then axi_awaddr_full <= '0'; elsif (awaddr_pipe_ld = '1') then axi_awaddr_full <= '1'; else axi_awaddr_full <= axi_awaddr_full; end if; end if; end process REG_WRADDR_FULL; --------------------------------------------------------------------------- end generate GEN_AW_PIPE_DUAL; --------------------------------------------------------------------------- -- Generate: GEN_DUAL_ADDR_CNT -- Purpose: Instantiate BRAM address counter unique for wr_chnl logic -- only when controller configured in dual port mode. --------------------------------------------------------------------------- GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate begin ---------------------------------------------------------------------------- -- Replace I_ADDR_CNT module usage of pf_counter in proc_common library. -- Only need to use lower 12-bits of address due to max AXI burst size -- Since AXI guarantees bursts do not cross 4KB boundary, the counting part -- of I_ADDR_CNT can be reduced to max 4KB. -- -- Counter size is adjusted based on data width of BRAM. -- For example, 32-bit data width BRAM, BRAM_Addr (1:0) -- are fixed at "00". So, counter increments from -- (C_AXI_ADDR_WIDTH - 1 : C_BRAM_ADDR_ADJUST). ---------------------------------------------------------------------------- I_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Reset usage differs from RD CHNL if (bram_addr_rst = '1') then bram_addr_int <= (others => '0'); elsif (bram_addr_ld_en_mod = '1') then bram_addr_int <= bram_addr_ld; elsif (bram_addr_inc_mod = '1') then bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process I_ADDR_CNT; -- Set defaults to shared address counter -- Only used in single port configurations Sng_BRAM_Addr_Rst <= '0'; Sng_BRAM_Addr_Ld_En <= '0'; Sng_BRAM_Addr_Ld <= (others => '0'); Sng_BRAM_Addr_Inc <= '0'; end generate GEN_DUAL_ADDR_CNT; --------------------------------------------------------------------------- -- Generate: GEN_SNG_ADDR_CNT -- Purpose: When configured in single port BRAM mode, address counter -- is shared with rd_chnl module. Assign output signals here -- to counter instantiation at full_axi module level. --------------------------------------------------------------------------- GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate begin Sng_BRAM_Addr_Rst <= bram_addr_rst; Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod; Sng_BRAM_Addr_Ld <= bram_addr_ld; Sng_BRAM_Addr_Inc <= bram_addr_inc_mod; bram_addr_int <= Sng_BRAM_Addr; end generate GEN_SNG_ADDR_CNT; --------------------------------------------------------------------------- -- -- Add BRAM counter reset for @ end of transfer -- -- Create a unique BRAM address reset signal -- If the write transaction is throttling on the AXI bus, then -- the BRAM EN may get negated during the write transfer -- -- Use combinatorial output from SM, bram_addr_rst_cmb, but ensure the -- BRAM address is not reset while loading a new address. bram_addr_rst <= (not (S_AXI_AResetn)) or (bram_addr_rst_cmb and not (bram_addr_ld_en_mod) and not (bram_addr_inc_mod)); --------------------------------------------------------------------------- -- BRAM address counter load mux -- -- Either load BRAM counter directly from AXI bus or from stored registered value -- -- Added bram_addr_ld_wrap for loading on wrap burst types -- Use registered signal to indicate current operation is a WRAP burst -- -- Do not load bram_addr_ld_wrap when bram_addr_ld_en signal is asserted at beginning of write burst -- BRAM address counter load. Due to condition when max_wrap_burst_mod remains asserted, due to BRAM address -- counter not incrementing (at the end of the previous write burst). -- bram_addr_ld <= bram_addr_ld_wrap when -- (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else -- axi_awaddr_pipe (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR) -- when (awaddr_pipe_sel = '1') else -- AXI_AWADDR (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- Replace C_BRAM_ADDR_SIZE w/ C_AXI_ADDR_WIDTH parameter usage bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else axi_awaddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) when (awaddr_pipe_sel = '1') else AXI_AWADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); --------------------------------------------------------------------------- -- On wrap burst max loads (simultaneous BRAM address increment is asserted). -- Ensure that load has higher priority over increment. -- Use registered signal to indicate current operation is a WRAP burst -- bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or -- (max_wrap_burst_mod = '1' and -- curr_wrap_burst_reg = '1' and -- bram_addr_inc_mod = '1')) -- else '0'; -- Use duplicate version of bram_addr_ld_en in effort -- to reduce fanout of signal routed to BRAM address counter bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1')) else '0'; -- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal -- logic. No need for the check if the current operation is NOT a fixed AND a wrap -- burst. The transfer will be one or the other. -- Found issue when narrow FIXED length burst is incorrectly -- incrementing BRAM address counter bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0') else narrow_bram_addr_inc_re; ---------------------------------------------------------------------------- -- Handling for WRAP burst types -- -- For WRAP burst types, the counter value will roll over when the burst -- boundary is reached. -- Boundary is reached based on ARSIZE and ARLEN. -- -- Goal is to minimize muxing on initial load of counter value. -- On WRAP burst types, detect when the max address is reached. -- When the max address is reached, re-load counter with lower -- address value set to '0'. ---------------------------------------------------------------------------- -- Detect valid WRAP burst types curr_wrap_burst <= '1' when (curr_awburst = C_AXI_BURST_WRAP) else '0'; -- Detect INCR & FIXED burst type operations curr_incr_burst <= '1' when (curr_awburst = C_AXI_BURST_INCR) else '0'; curr_fixed_burst <= '1' when (curr_awburst = C_AXI_BURST_FIXED) else '0'; ---------------------------------------------------------------------------- -- Register curr_wrap_burst signal when BRAM address counter is initially -- loaded REG_CURR_WRAP_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset same as BRAM address counter if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then curr_wrap_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_wrap_burst_reg <= curr_wrap_burst; else curr_wrap_burst_reg <= curr_wrap_burst_reg; end if; end if; end process REG_CURR_WRAP_BRST; ---------------------------------------------------------------------------- -- Register curr_fixed_burst signal when BRAM address counter is initially -- loaded REG_CURR_FIXED_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset same as BRAM address counter if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then curr_fixed_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_fixed_burst_reg <= curr_fixed_burst; else curr_fixed_burst_reg <= curr_fixed_burst_reg; end if; end if; end process REG_CURR_FIXED_BRST; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Instance: I_WRAP_BRST -- -- Description: -- -- Instantiate WRAP_BRST module -- Logic to generate the wrap around value to load into the BRAM address -- counter on WRAP burst transactions. -- WRAP value is based on current AWLEN, AWSIZE (for narrows) and -- data width of BRAM module. -- --------------------------------------------------------------------------- I_WRAP_BRST : entity work.wrap_brst generic map ( C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , S_AXI_AResetn => S_AXI_AResetn , curr_axlen => curr_awlen , curr_axsize => curr_awsize , curr_narrow_burst => curr_narrow_burst , narrow_bram_addr_inc_re => narrow_bram_addr_inc_re , bram_addr_ld_en => bram_addr_ld_en , bram_addr_ld => bram_addr_ld , bram_addr_int => bram_addr_int , bram_addr_ld_wrap => bram_addr_ld_wrap , max_wrap_burst_mod => max_wrap_burst_mod ); --------------------------------------------------------------------------- -- Generate: GEN_WO_NARROW -- Purpose: Create BRAM address increment signal when narrow bursts -- are disabled. --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin -- For non narrow burst operations, use bram_addr_inc from data SM. -- Add in check that burst type is not FIXED, curr_fixed_burst_reg bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg); -- The signal, curr_narrow_burst should always be set to '0' when narrow bursts -- are disabled. curr_narrow_burst <= '0'; narrow_bram_addr_inc_re <= '0'; end generate GEN_WO_NARROW; --------------------------------------------------------------------------- -- Only instantiate NARROW_CNT and supporting logic when narrow transfers -- are supported and utilized by masters in the AXI system. -- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this. --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT -- Purpose: Instantiate narrow counter and logic when narrow -- operation support is enabled. -- And, only instantiate logic for narrow operations when -- AXI bus protocol is not set for AXI-LITE. --------------------------------------------------------------------------- GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin -- Based on current operation being a narrow burst, hold off BRAM -- address increment until narrow burst fits BRAM data width. -- For non narrow burst operations, use bram_addr_inc from data SM. -- Add in check that burst type is not FIXED, curr_fixed_burst_reg bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') -- else narrow_bram_addr_inc_re; -- Seeing incorrect BRAM address increment on narrow -- fixed length burst operations. -- Add this check for curr_fixed_burst_reg else (narrow_bram_addr_inc_re and not (curr_fixed_burst_reg)); --------------------------------------------------------------------------- -- -- Generate seperate smaller counter for narrow burst operations -- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library. -- -- Counter size is adjusted based on size of data burst. -- -- For example, 32-bit data width BRAM, minimum narrow width -- burst is 8 bits resulting in a count 3 downto 0. So the -- minimum counter width = 2 bits. -- -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst -- is 8 bits resulting in a count 31 downto 0. So the -- minimum counter width = 5 bits. -- -- Size of counter = C_NARROW_BURST_CNT_LEN -- --------------------------------------------------------------------------- I_NARROW_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (narrow_addr_rst = '1') then narrow_addr_int <= (others => '0'); -- Load narrow address counter elsif (narrow_addr_ld_en = '1') then narrow_addr_int <= narrow_burst_cnt_ld_mod; -- Decrement ONLY (no increment functionality) elsif (narrow_addr_dec = '1') then narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <= std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1); end if; end if; end process I_NARROW_CNT; --------------------------------------------------------------------------- narrow_addr_rst <= not (S_AXI_AResetn); -- Narrow burst counter load mux -- Modify narrow burst count load value based on -- unalignment of AXI address value -- Account for INCR burst types at unaligned addresses narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else narrow_burst_cnt_ld_reg; narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0'; narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re; narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and (curr_narrow_burst = '1') -- Ensure that narrow address counter doesn't -- flag max or get loaded to -- reset narrow counter until AXI read data -- bus has acknowledged current -- data on the AXI bus. Use rd_adv_buf signal -- to indicate the non throttle -- condition on the AXI bus. and (bram_addr_inc = '1') else '0'; -- Detect rising edge of narrow_bram_addr_inc REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_bram_addr_inc_d1 <= '0'; else narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc; end if; end if; end process REG_NARROW_BRAM_ADDR_INC; narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and (narrow_bram_addr_inc_d1 = '0') else '0'; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT; --------------------------------------------------------------------------- -- Generate: GEN_AWREADY -- Purpose: AWREADY is only created here when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AWREADY: if (C_SINGLE_PORT_BRAM = 0) generate begin -- v1.03a ---------------------------------------------------------------------------- -- AXI_AWREADY Output Register -- Description: Keep AXI_AWREADY output asserted until AWADDR pipeline -- is full. When a full condition is reached, negate -- AWREADY as another AW address can not be accepted. -- Add condition to keep AWReady asserted if loading current --- AWADDR pipeline value into the BRAM address counter. -- Indicated by assertion of bram_addr_ld_en & awaddr_pipe_sel. -- ---------------------------------------------------------------------------- REG_AWREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_awready_int <= '0'; -- Detect end of S_AXI_AResetn to assert AWREADY and accept -- new AWADDR values elsif (axi_aresetn_re_reg = '1') or (bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then axi_awready_int <= '1'; elsif (awaddr_pipe_ld = '1') then axi_awready_int <= '0'; else axi_awready_int <= axi_awready_int; end if; end if; end process REG_AWREADY; ---------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert AWREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; axi_aresetn_d2 <= axi_aresetn_d1; axi_aresetn_re_reg <= axi_aresetn_re; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0'; end generate GEN_AWREADY; ---------------------------------------------------------------------------- -- Specify current AWSIZE signal -- Address pipeline MUX curr_awsize <= axi_awsize_pipe when (awaddr_pipe_sel = '1') else AXI_AWSIZE; -- Register curr_awsize when bram_addr_ld_en = '1' REG_AWSIZE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_awsize_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then curr_awsize_reg <= curr_awsize; else curr_awsize_reg <= curr_awsize_reg; end if; end if; end process REG_AWSIZE; --------------------------------------------------------------------------- -- -- Generate: GEN_NARROW_EN -- Purpose: Only instantiate logic to determine if current burst -- is a narrow burst when narrow bursting logic is supported. -- --------------------------------------------------------------------------- GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin ----------------------------------------------------------------------- -- Determine "narrow" burst transfers -- Compare the AWSIZE to the BRAM data width ----------------------------------------------------------------------- -- v1.03a -- Detect if current burst operation is of size /= to the full -- AXI data bus width. If not, then the current operation is a -- "narrow" burst. curr_narrow_burst_cmb <= '1' when (curr_awsize /= C_AXI_SIZE_MAX) else '0'; --------------------------------------------------------------------------- curr_narrow_burst_en <= '1' when (bram_addr_ld_en = '1') and (curr_awlen /= AXI_AWLEN_ONE) and (curr_fixed_burst = '0') else '0'; -- Register flag indicating the current operation -- is a narrow write burst NARROW_BURST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Need to reset this flag at end of narrow burst operation -- Use handshaking signals on AXI if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Check for back to back narrow burst. If that is the case, then -- do not clear curr_narrow_burst flag. (axi_wlast_re = '1' and curr_narrow_burst_en = '0' -- If ECC is enabled, no clear to curr_narrow_burst when WLAST is asserted -- this causes the BRAM address to incorrectly get asserted on the last -- beat in the burst (due to delay in RMW logic) and C_ECC = 0) then curr_narrow_burst <= '0'; elsif (curr_narrow_burst_en = '1') then curr_narrow_burst <= curr_narrow_burst_cmb; end if; end if; end process NARROW_BURST_REG; --------------------------------------------------------------------------- -- Detect RE of AXI_WLAST -- Only used when narrow bursts are enabled. WLAST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wlast_d1 <= '0'; else -- axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod; -- CR # 609695 axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod and AXI_WVALID; end if; end if; end process WLAST_REG; -- axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod) and not (axi_wlast_d1); -- CR # 609695 axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod and AXI_WVALID) and not (axi_wlast_d1); end generate GEN_NARROW_EN; --------------------------------------------------------------------------- -- Generate registered flag that active burst is a "narrow" burst -- and load narrow burst counter --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_NARROW_CNT_LD -- Purpose: Only instantiate logic to determine narrow burst counter -- load value when narrow bursts are enabled. -- --------------------------------------------------------------------------- GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate signal curr_awsize_unsigned : unsigned (2 downto 0) := (others => '0'); signal axi_byte_div_curr_awsize : integer := 1; begin -- v1.03a -- Create narrow burst counter load value based on current operation -- "narrow" data width (indicated by value of AWSIZE). curr_awsize_unsigned <= unsigned (curr_awsize); -- XST does not support divisors that are not constants and powers of 2. -- Create process to create a fixed value for divisor. -- Replace this statement: -- narrow_burst_cnt_ld <= std_logic_vector ( -- to_unsigned ( -- (C_AXI_DATA_WIDTH_BYTES / (2(to_integer (curr_awsize_unsigned))) ) - 1, -- C_NARROW_BURST_CNT_LEN)); -- -- With this new process and subsequent signal assignment: -- DIV_AWSIZE: process (curr_awsize_unsigned) -- begin -- -- case (to_integer (curr_awsize_unsigned)) is -- when 0 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1; -- when 1 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2; -- when 2 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4; -- when 3 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8; -- when 4 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16; -- when 5 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32; -- when 6 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64; -- when 7 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128; -- --coverage off -- when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES; -- --coverage on -- end case; -- -- end process DIV_AWSIZE; -- w/ CR # 609695 -- With this new process and subsequent signal assignment: DIV_AWSIZE: process (curr_awsize_unsigned) begin case (curr_awsize_unsigned) is when "000" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1; when "001" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2; when "010" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4; when "011" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8; when "100" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16; when "101" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32; when "110" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64; when "111" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128; --coverage off when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES; --coverage on end case; end process DIV_AWSIZE; --------------------------------------------------------------------------- -- Create narrow burst count load value. -- -- Size is based on [C_NARROW_BURST_CNT_LEN-1 : 0] -- For 32-bit BRAM, C_NARROW_BURST_CNT_LEN = 2. -- For 64-bit BRAM, C_NARROW_BURST_CNT_LEN = 3. -- For 128-bit BRAM, C_NARROW_BURST_CNT_LEN = 4. (etc.) -- -- Signal, narrow_burst_cnt_ld signal is sized according to C_AXI_DATA_WIDTH. -- Updated else clause for simulation warnings w/ CR # 609695 narrow_burst_cnt_ld <= std_logic_vector ( to_unsigned ( (axi_byte_div_curr_awsize) - 1, C_NARROW_BURST_CNT_LEN)) when (axi_byte_div_curr_awsize > 0) else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN)); --------------------------------------------------------------------------- -- Register narrow_burst_cnt_ld REG_NAR_BRST_CNT_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_burst_cnt_ld_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld; else narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg; end if; end if; end process REG_NAR_BRST_CNT_LD; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT_LD; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_awburst <= axi_awburst_pipe when (awaddr_pipe_sel = '1') else AXI_AWBURST; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_awlen <= axi_awlen_pipe when (awaddr_pipe_sel = '1') else AXI_AWLEN; -- Duplicate early decode of AWLEN value to use in wr_b2b_elgible logic REG_CURR_AWLEN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_awlen_reg_1_or_2 <= '0'; elsif (bram_addr_ld_en = '1') then -- Create merge to decode AWLEN of ONE or TWO if (curr_awlen = AXI_AWLEN_ONE) or (curr_awlen = AXI_AWLEN_TWO) then curr_awlen_reg_1_or_2 <= '1'; else curr_awlen_reg_1_or_2 <= '0'; end if; else curr_awlen_reg_1_or_2 <= curr_awlen_reg_1_or_2; end if; end if; end process REG_CURR_AWLEN; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_UA_NARROW -- Purpose: Only instantiate logic for burst narrow WRAP operations when -- AXI bus protocol is not set for AXI-LITE and narrow -- burst operations are supported. -- --------------------------------------------------------------------------- GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- New logic to detect unaligned address on a narrow WRAP burst transaction. -- If this condition is met, then the narrow burst counter will be -- initially loaded with an offset value corresponding to the unalignment -- in the ARADDR value. -- Create a sub module for all logic to determine the narrow burst counter -- offset value on unaligned WRAP burst operations. -- Module generates the following signals: -- -- => curr_ua_narrow_wrap, to indicate the current -- operation is an unaligned narrow WRAP burst. -- -- => curr_ua_narrow_incr, to load narrow burst counter -- for unaligned INCR burst operations. -- -- => ua_narrow_load, narrow counter load value. -- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0) -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Instance: I_UA_NARROW -- -- Description: -- -- Creates a narrow burst count load value when an operation -- is an unaligned narrow WRAP or INCR burst type. Used by -- I_NARROW_CNT module. -- -- Logic is customized for each C_AXI_DATA_WIDTH. --------------------------------------------------------------------------- I_UA_NARROW : entity work.ua_narrow generic map ( C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN ) port map ( curr_wrap_burst => curr_wrap_burst , -- in curr_incr_burst => curr_incr_burst , -- in bram_addr_ld_en => bram_addr_ld_en , -- in curr_axlen => curr_awlen , -- in curr_axsize => curr_awsize , -- in curr_axaddr_lsb => curr_awaddr_lsb , -- in curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out curr_ua_narrow_incr => curr_ua_narrow_incr , -- out ua_narrow_load => ua_narrow_load -- out ); -- Use in all C_AXI_DATA_WIDTH generate statements -- Only probe least significant BRAM address bits -- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0. curr_awaddr_lsb <= axi_awaddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) when (awaddr_pipe_sel = '1') else AXI_AWADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0); end generate GEN_UA_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_SNG -- Purpose: If single port BRAM configuration, set all AW flags from -- logic generated in sng_port_arb module. -- --------------------------------------------------------------------------- GEN_AW_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin aw_active <= Arb2AW_Active; bram_addr_ld_en <= aw_active_re; AW2Arb_Active_Clr <= aw_active_clr; AW2Arb_Busy <= wr_busy_reg; AW2Arb_BVALID_Cnt <= bvalid_cnt; end generate GEN_AW_SNG; -- Rising edge detect of aw_active -- For single port configurations, aw_active = Arb2AW_Active. -- For dual port configurations, aw_active generated in ADDR SM. RE_AW_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then aw_active_d1 <= '0'; else aw_active_d1 <= aw_active; end if; end if; end process RE_AW_ACT; aw_active_re <= '1' when (aw_active = '1' and aw_active_d1 = '0') else '0'; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_DUAL -- Purpose: Generate AW control state machine logic only when AXI4 -- controller is configured for dual port mode. In dual port -- mode, wr_chnl has full access over AW & port A of BRAM. -- --------------------------------------------------------------------------- GEN_AW_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin AW2Arb_Active_Clr <= '0'; -- Only used in single port case AW2Arb_Busy <= '0'; -- Only used in single port case AW2Arb_BVALID_Cnt <= (others => '0'); ---------------------------------------------------------------------------- REG_LAST_DATA_ACK: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then last_data_ack_mod <= '0'; else -- last_data_ack_mod <= AXI_WLAST; -- CR # 609695 last_data_ack_mod <= AXI_WLAST and AXI_WVALID and axi_wready_int_mod; end if; end if; end process REG_LAST_DATA_ACK; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- WR ADDR State Machine -- -- Description: Central processing unit for AXI write address -- channel interface handling and handshaking. -- -- Outputs: awaddr_pipe_ld Combinatorial -- awaddr_pipe_sel -- bram_addr_ld_en -- -- -- -- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine. --------------------------------------------------------------------------- WR_ADDR_SM_CMB_PROCESS: process ( AXI_AWVALID, bvalid_cnt_max, axi_awaddr_full, aw_active, wr_b2b_elgible, last_data_ack_mod, wr_addr_sm_cs ) begin -- assign default values for state machine outputs wr_addr_sm_ns <= wr_addr_sm_cs; awaddr_pipe_ld_i <= '0'; bram_addr_ld_en_i <= '0'; aw_active_set_i <= '0'; case wr_addr_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Check for pending operation in address pipeline that may -- be elgible for back-to-back performance to BRAM. -- Prevent loading BRAM address counter if BID FIFO can not -- store the AWID value. Check the BVALID counter. if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; -- Ensure AWVALID is recognized. -- Address pipeline may be loaded, but BRAM counter -- can not be loaded if at max of BID FIFO. elsif (AXI_AWVALID = '1') then -- If address pipeline is full -- AWReady output is negated -- If write address logic is ready for new operation -- Load BRAM address counter and set aw_active = '1' -- If address pipeline is already full to start next operation -- load address counter from pipeline. -- Prevent loading BRAM address counter if BID FIFO can not -- store the AWID value. Check the BVALID counter. -- Remain in this state if (aw_active = '0') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Stay in this state to capture AWVALID if asserted -- in next clock cycle. bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; -- Address counter is currently busy. -- No check on BVALID counter for address pipeline load. -- Only the BRAM address counter is checked for BID FIFO capacity. else -- Check if AWADDR pipeline is not full and can be loaded if (axi_awaddr_full = '0') then wr_addr_sm_ns <= LD_AWADDR; awaddr_pipe_ld_i <= '1'; end if; end if; -- aw_active -- Pending operation in pipeline that is waiting -- until current operation is complete (aw_active = '0') elsif (axi_awaddr_full = '1') and (aw_active = '0') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; end if; -- AWVALID ---------------------------- LD_AWADDR State --------------------------- when LD_AWADDR => wr_addr_sm_ns <= IDLE; if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_addr_sm_ns <= IDLE; --coverage on end case; end process WR_ADDR_SM_CMB_PROCESS; --------------------------------------------------------------------------- -- CR # 582705 -- Ensure combinatorial SM output signals do not get set before -- the end of the reset (and ARREAADY can be set). bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2; aw_active_set <= aw_active_set_i and axi_aresetn_d2; awaddr_pipe_ld <= awaddr_pipe_ld_i and axi_aresetn_d2; WR_ADDR_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 -- Ensure that ar_active does not get asserted (from SM) before -- the end of reset and the ARREADY flag is set. if (axi_aresetn_d2 = C_RESET_ACTIVE) then wr_addr_sm_cs <= IDLE; else wr_addr_sm_cs <= wr_addr_sm_ns; end if; end if; end process WR_ADDR_SM_REG_PROCESS; --------------------------------------------------------------------------- -- Asserting awaddr_pipe_sel outside of SM logic -- The BRAM address counter will get loaded with value in AWADDR pipeline -- when data is stored in the AWADDR pipeline. awaddr_pipe_sel <= '1' when (axi_awaddr_full = '1') else '0'; --------------------------------------------------------------------------- -- Register for aw_active REG_AW_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- CR # 582705 -- if (S_AXI_AResetn = C_RESET_ACTIVE) then if (axi_aresetn_d2 = C_RESET_ACTIVE) then aw_active <= '0'; elsif (aw_active_set = '1') then aw_active <= '1'; elsif (aw_active_clr = '1') then aw_active <= '0'; else aw_active <= aw_active; end if; end if; end process REG_AW_ACT; --------------------------------------------------------------------------- end generate GEN_AW_DUAL; --------------------------------------------------------------------------- -- * AXI Write Data Channel Interface * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- AXI WrData Buffer/Register --------------------------------------------------------------------------- GEN_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin REG_WRDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (wrdata_reg_ld = '1') then bram_wrdata_int (i) <= AXI_WDATA (i); else bram_wrdata_int (i) <= bram_wrdata_int (i); end if; end if; end process REG_WRDATA; end generate GEN_WRDATA; --------------------------------------------------------------------------- -- Generate: GEN_WR_NO_ECC -- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA -- and AXI_WSTRBs when C_ECC is disabled. --------------------------------------------------------------------------- GEN_WR_NO_ECC: if C_ECC = 0 generate begin --------------------------------------------------------------------------- -- AXI WSTRB Buffer/Register -- Use AXI write data channel data strobe signals to generate BRAM WE. --------------------------------------------------------------------------- REG_BRAM_WE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Ensure we don't clear WE when loading subsequent WSTRB value if (S_AXI_AResetn = C_RESET_ACTIVE) or (clr_bram_we = '1' and bram_we_ld = '0') then bram_we_int <= (others => '0'); elsif (bram_we_ld = '1') then bram_we_int <= AXI_WSTRB; else bram_we_int <= bram_we_int; end if; end if; end process REG_BRAM_WE; ---------------------------------------------------------------------------- -- New logic to detect if pending operation in AWADDR pipeline is -- elgible for back-to-back no "bubble" performance. And BRAM address -- counter can be loaded upon last BRAM address presented for the current -- operation. -- This condition exists when the AWADDR pipeline is full and the pending -- operation is a burst >= length of two data beats. -- And not a FIXED burst type (must be INCR or WRAP type). -- -- Narrow bursts are be neglible -- -- Add check to complete current single and burst of two data bursts -- prior to loading BRAM counter wr_b2b_elgible <= '1' when (axi_awaddr_full = '1') and -- Replace comparator logic here with register signal (pre pipeline stage -- on axi_awlen_pipe value -- Use merge in decode of ONE or TWO (axi_awlen_pipe_1_or_2 /= '1') and (axi_awburst_pipe_fixed /= '1') and -- Use merge in decode of ONE or TWO (curr_awlen_reg_1_or_2 /= '1') else '0'; ---------------------------------------------------------------------------- end generate GEN_WR_NO_ECC; --------------------------------------------------------------------------- -- Generate: GEN_WR_ECC -- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA -- and AXI_WSTRBs when C_ECC is enabled. --------------------------------------------------------------------------- GEN_WR_ECC: if C_ECC = 1 generate begin wr_b2b_elgible <= '0'; --------------------------------------------------------------------------- -- AXI WSTRB Buffer/Register -- Use AXI write data channel data strobe signals to generate BRAM WE. --------------------------------------------------------------------------- REG_BRAM_WE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Ensure we don't clear WE when loading subsequent WSTRB value if (S_AXI_AResetn = C_RESET_ACTIVE) or (reset_bram_we = '1') then bram_we_int <= (others => '0'); elsif (set_bram_we = '1') then bram_we_int <= (others => '1'); else bram_we_int <= bram_we_int; end if; end if; end process REG_BRAM_WE; end generate GEN_WR_ECC; ----------------------------------------------------------------------- -- v1.03a ----------------------------------------------------------------------- -- -- Implement WREADY to be a registered output. Used by all configurations. -- This will disable the back-to-back streamlined WDATA -- for write operations to BRAM. -- ----------------------------------------------------------------------- REG_WREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wready_int_mod <= '0'; -- Keep AXI WREADY asserted unless write data register is full -- Use combinatorial signal from SM. elsif (axi_wdata_full_cmb = '1') then axi_wready_int_mod <= '0'; else axi_wready_int_mod <= '1'; end if; end if; end process REG_WREADY; --------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- Generate: GEN_WDATA_SM_ECC -- Purpose: Create seperate SM for ECC read-modify-write logic. -- Only used in single port BRAM mode. So, no address -- pipelining. Must use aw_active from arbitration logic -- to determine start of write to BRAM. -- ---------------------------------------------------------------------------- -- Test using same write data SM for single or dual port configuration. -- The difference is the source of aw_active. In a single port configuration, -- the aw_active is coming from the arbiter SM. In a dual port configuration, -- the aw_active is coming from the write address SM in this module. GEN_WDATA_SM_ECC: if C_ECC = 1 generate begin -- Unused in this SM configuration bram_we_ld <= '0'; bram_addr_rst_cmb <= '0'; -- Output only used by ECC register module. Active_Wr <= active_wr_reg; --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking when ECC is enabled. SM will handle -- each transaction as a read-modify-write to ensure -- the correct ECC bits are stored in BRAM. -- -- Dedicated to single port BRAM interface. Transaction -- is not initiated until valid AWADDR is arbitration, -- ie. aw_active will be asserted. SM can do early reads -- while waiting for WVALID to be asserted. -- -- Valid AWADDR recieve indicator comes from arbitration -- logic (aw_active will be asserted). -- -- Outputs: Name Type -- -- aw_active_clr Not Registered -- axi_wdata_full_reg Registered -- wrdata_reg_ld Not Registered -- bvalid_cnt_inc Not Registered -- bram_addr_inc Not Registered -- bram_en_int Registered -- reset_bram_we Not Registered -- set_bram_we Not Registered -- -- -- WR_DATA_ECC_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_ECC_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_ECC_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, aw_active, wr_busy_reg, axi_wdata_full_reg, axi_wr_burst, AXI_BREADY, active_wr_reg, wr_data_ecc_sm_cs ) begin -- Assign default values for state machine outputs wr_data_ecc_sm_ns <= wr_data_ecc_sm_cs; aw_active_clr <= '0'; wr_busy_cmb <= wr_busy_reg; bvalid_cnt_inc <= '0'; wrdata_reg_ld <= '0'; reset_bram_we <= '0'; set_bram_we_cmb <= '0'; bram_en_cmb <= '0'; bram_addr_inc <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; axi_wr_burst_cmb <= axi_wr_burst; active_wr_cmb <= active_wr_reg; case wr_data_ecc_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Prior to AWVALID assertion, WVALID may be asserted -- and data accepted into WDATA register. -- Catch this condition and ensure the register full flag is set. -- Check that data pipeline is not already full. if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- Check if AWVALID is asserted & wins arbitration if (aw_active = '1') then active_wr_cmb <= '1'; -- Set flag that RMW SM is active -- Controls mux select for BRAM and ECC register module -- (Set to '1' wr_chnl or '0' for rd_chnl control) bram_en_cmb <= '1'; -- Initiate BRAM read transfer reset_bram_we <= '1'; -- Disable Port A write enables -- Will proceed to read-modify-write if we get a -- valid write address early (before WVALID) wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; -- WVALID ------------------------- RMW_RD_DATA State ------------------------- when RMW_RD_DATA => -- Check if data to write is available in data pipeline if (axi_wdata_full_reg = '1') then wr_data_ecc_sm_ns <= RMW_CHK_DATA; -- Else may have address, but not yet data from W channel elsif (AXI_WVALID = '1') then -- Ensure that WDATA pipeline is marked as full, so WREADY negates axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data wrdata_reg_ld <= '1'; -- Load write data register -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not wr_data_ecc_sm_ns <= RMW_CHK_DATA; else -- Hold here and wait for write data wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; ------------------------- RMW_CHK_DATA State ------------------------- when RMW_CHK_DATA => -- New state here to add register stage on calculating -- checkbits for read data and then muxing/creating new -- checkbits for write cycle. -- Go immediately to MODIFY stage in RMW sequence wr_data_ecc_sm_ns <= RMW_MOD_DATA; set_bram_we_cmb <= '1'; -- Enable all WEs to BRAM ------------------------- RMW_MOD_DATA State ------------------------- when RMW_MOD_DATA => -- Modify clock cycle in RMW sequence -- Only reach this state after a read AND we have data -- in the write data pipeline to modify and subsequently write to BRAM. bram_en_cmb <= '1'; -- Initiate BRAM write transfer -- Can clear WDATA pipeline full condition flag if (axi_wr_burst = '1') then axi_wdata_full_cmb <= '0'; end if; wr_data_ecc_sm_ns <= RMW_WR_DATA; -- Go to write data to BRAM ------------------------- RMW_WR_DATA State ------------------------- when RMW_WR_DATA => -- Check if last data beat in a burst (or the write is a single) if (axi_wr_burst = '0') then -- Can clear WDATA pipeline full condition flag now that -- write data has gone out to BRAM (for single data transfers) axi_wdata_full_cmb <= '0'; bvalid_cnt_inc <= '1'; -- Set flag to assert BVALID and increment counter wr_data_ecc_sm_ns <= IDLE; -- Go back to IDLE, BVALID assertion is seperate wr_busy_cmb <= '0'; -- Clear flag to arbiter active_wr_cmb <= '0'; -- Clear flag (wr_chnl is done accessing BRAM) -- Used for single port arbitration SM axi_wr_burst_cmb <= '0'; aw_active_clr <= '1'; -- Clear aw_active flag reset_bram_we <= '1'; -- Disable Port A write enables else -- Continue with read-modify-write sequence for write burst -- If next data beat is available on AXI, capture the data if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- After write cycle (in RMW) => Increment BRAM address counter bram_addr_inc <= '1'; bram_en_cmb <= '1'; -- Initiate BRAM read transfer reset_bram_we <= '1'; -- Disable Port A write enables -- Will proceed to read-modify-write if we get a -- valid write address early (before WVALID) wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_data_ecc_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_ECC_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_ECC_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_ecc_sm_cs <= IDLE; bram_en_int <= '0'; axi_wdata_full_reg <= '0'; wr_busy_reg <= '0'; active_wr_reg <= '0'; set_bram_we <= '0'; else wr_data_ecc_sm_cs <= wr_data_ecc_sm_ns; bram_en_int <= bram_en_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; wr_busy_reg <= wr_busy_cmb; active_wr_reg <= active_wr_cmb; set_bram_we <= set_bram_we_cmb; end if; end if; end process WR_DATA_ECC_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_ECC; -- v1.03a ---------------------------------------------------------------------------- -- -- Generate: GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY -- Purpose: Create seperate SM use case of no ECC (no read-modify-write) -- and single port BRAM configuration (no back to back operations -- are supported). Must wait for aw_active from arbiter to indicate -- control on BRAM interface. -- ---------------------------------------------------------------------------- GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY: if C_ECC = 0 and C_SINGLE_PORT_BRAM = 1 generate begin -- Unused in this SM configuration wr_busy_cmb <= '0'; -- Unused wr_busy_reg <= '0'; -- Unused active_wr_cmb <= '0'; -- Unused active_wr_reg <= '0'; -- Unused Active_Wr <= '0'; -- Unused --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- aw_active_clr Not Registered -- bvalid_cnt_inc Not Registered -- wrdata_reg_ld Not Registered -- bram_we_ld Not Registered -- bram_en_int Registered -- clr_bram_we Registered -- bram_addr_inc Not Registered -- wrdata_reg_ld Not Registered -- -- Note: -- -- On "narrow burst transfers" BRAM address only -- gets incremented at BRAM data width. -- On WRAP bursts, the BRAM address must wrap when -- the max is reached -- -- -- -- WR_DATA_SNG_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_SNG_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_SNG_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, aw_active, axi_wr_burst, axi_wdata_full_reg, wr_data_sng_sm_cs ) begin -- assign default values for state machine outputs wr_data_sng_sm_ns <= wr_data_sng_sm_cs; aw_active_clr <= '0'; bvalid_cnt_inc <= '0'; axi_wr_burst_cmb <= axi_wr_burst; wrdata_reg_ld <= '0'; bram_we_ld <= '0'; bram_en_cmb <= '0'; clr_bram_we_cmb <= '0'; bram_addr_inc <= '0'; bram_addr_rst_cmb <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; case wr_data_sng_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Prior to AWVALID assertion, WVALID may be asserted -- and data accepted into WDATA register. -- Catch this condition and ensure the register full flag is set. -- Check that data pipeline is not already full. -- -- Modify WE pipeline and mux to BRAM -- as well. Since WE may be asserted early (when pipeline is loaded), -- but not yet ready to go out to BRAM. -- -- Only first data beat will be accepted early into data pipeline. -- All remaining beats in a burst will only be accepted upon WVALID. if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- Wait for WVALID and aw_active to initiate write transfer if (aw_active = '1' and (AXI_WVALID = '1' or axi_wdata_full_reg = '1')) then -- If operation is a single, then it goes directly out to BRAM -- WDATA register is never marked as FULL in this case. -- If data pipeline is not previously loaded, do so now. if (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register end if; -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- If data goes out to BRAM, mark data register as EMPTY axi_wdata_full_cmb <= '0'; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not -- Check for singles, by checking WLAST assertion w/ WVALID -- Only if write data pipeline is not yet filled, check WLAST -- Otherwise, if pipeline is already full, use registered value of WLAST -- to check for single vs. burst write operation. if (AXI_WLAST = '1' and axi_wdata_full_reg = '0') or (axi_wdata_full_reg = '1' and axi_wr_burst = '0') then -- Single data write wr_data_sng_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; else -- Burst data write wr_data_sng_sm_ns <= BRST_WR_DATA; end if; -- WLAST end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- If WREADY is registered, then BVALID generation is seperate -- from write data flow. -- Go back to IDLE automatically -- BVALID will get asserted seperately from W channel wr_data_sng_sm_ns <= IDLE; bram_addr_rst_cmb <= '1'; aw_active_clr <= '1'; -- Check for capture of next data beat (WREADY will be asserted) if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not else axi_wdata_full_cmb <= '0'; -- If no next data, ensure data register is flagged EMPTY. end if; ------------------------- BRST_WR_DATA State ------------------------- when BRST_WR_DATA => -- Reach this state at the 2nd data beat of a burst -- AWADDR is already accepted -- Continue to accept data from AXI write channel -- and wait for assertion of WLAST -- Check that WVALID remains asserted for burst -- If negated, indicates throttling from AXI master if (AXI_WVALID = '1') then -- If WVALID is asserted for the 2nd and remaining -- data beats of the transfer -- Continue w/ BRAM write enable assertion & advance -- write data register -- Write data goes directly out to BRAM. -- WDATA register is never marked as FULL in this case. wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Increment BRAM address counter bram_addr_inc <= '1'; -- Check for last data beat in burst transfer if (AXI_WLAST = '1') then -- Last/single data write wr_data_sng_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; end if; -- WLAST -- Throttling -- Suspend BRAM write & halt write data & WE register load else -- Negate write data register load wrdata_reg_ld <= '0'; -- Negate WE register load bram_we_ld <= '0'; -- Negate write to BRAM bram_en_cmb <= '0'; -- Do not increment BRAM address counter bram_addr_inc <= '0'; end if; -- WVALID --coverage off ------------------------------ Default ---------------------------- when others => wr_data_sng_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_SNG_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_SNG_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_sng_sm_cs <= IDLE; bram_en_int <= '0'; clr_bram_we <= '0'; axi_wdata_full_reg <= '0'; else wr_data_sng_sm_cs <= wr_data_sng_sm_ns; bram_en_int <= bram_en_cmb; clr_bram_we <= clr_bram_we_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; end if; end if; end process WR_DATA_SNG_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY; ---------------------------------------------------------------------------- -- -- Generate: GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY -- -- Purpose: Create seperate SM for new logic to register out WREADY -- signal. Behavior for back-to-back operations is different -- than with combinatorial genearted WREADY output to AXI. -- -- New SM design supports seperate WREADY and BVALID responses. -- -- New logic here for axi_bvalid_int output register based -- on counter design of BVALID. -- ---------------------------------------------------------------------------- GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY: if C_ECC = 0 and C_SINGLE_PORT_BRAM = 0 generate begin -- Unused in this SM configuration active_wr_cmb <= '0'; -- Unused active_wr_reg <= '0'; -- Unused Active_Wr <= '0'; -- Unused wr_busy_cmb <= '0'; -- Unused wr_busy_reg <= '0'; -- Unused --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- bvalid_cnt_inc Not Registered -- aw_active_clr Not Registered -- delay_aw_active_clr Registered -- axi_wdata_full_reg Registered -- bram_en_int Registered -- wrdata_reg_ld Not Registered -- bram_we_ld Not Registered -- clr_bram_we Registered -- bram_addr_inc -- -- Note: -- -- On "narrow burst transfers" BRAM address only -- gets incremented at BRAM data width. -- On WRAP bursts, the BRAM address must wrap when -- the max is reached -- -- Add check on BVALID counter max. Check with -- AWVALID assertions (since AWID is connected to AWVALID). -- -- -- WR_DATA_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, bvalid_cnt_max, bvalid_cnt_amax, aw_active, delay_aw_active_clr, AXI_AWVALID, axi_awready_int, bram_addr_ld_en, axi_awaddr_full, awaddr_pipe_sel, axi_wr_burst, axi_wdata_full_reg, wr_b2b_elgible, wr_data_sm_cs ) begin -- assign default values for state machine outputs wr_data_sm_ns <= wr_data_sm_cs; aw_active_clr <= '0'; delay_aw_active_clr_cmb <= delay_aw_active_clr; bvalid_cnt_inc <= '0'; axi_wr_burst_cmb <= axi_wr_burst; wrdata_reg_ld <= '0'; bram_we_ld <= '0'; bram_en_cmb <= '0'; clr_bram_we_cmb <= '0'; bram_addr_inc <= '0'; bram_addr_rst_cmb <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; case wr_data_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register -- Add condition to check for simultaneous assertion -- of AWVALID and AWREADY if ((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Check for singles, by checking WLAST assertion w/ WVALID if (AXI_WLAST = '1') then -- Single data write wr_data_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- Set flag to delay clear of AW active flag delay_aw_active_clr_cmb <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; axi_wr_burst_cmb <= '0'; else -- Burst data write wr_data_sm_ns <= BRST_WR_DATA; axi_wr_burst_cmb <= '1'; end if; -- WLAST else -- AWADDR not yet received -- Go to wait for write address wr_data_sm_ns <= W8_AWADDR; -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. axi_wdata_full_cmb <= '1'; -- Set flag for single/burst write operation -- when AWADDR is not yet received if (AXI_WLAST = '1') then axi_wr_burst_cmb <= '0'; else axi_wr_burst_cmb <= '1'; end if; -- WLAST end if; -- aw_active end if; -- WVALID ------------------------- W8_AWADDR State ------------------------- when W8_AWADDR => -- As we transition into this state, the write data pipeline -- is already filled. axi_wdata_full_reg should be = '1'. -- Disable any additional loads into write data register -- Default value in SM is applied. -- Wait for write address to be acknowledged if (((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) or -- Detect load of BRAM address counter from value stored in pipeline. -- No need to wait until aw_active is asserted or address is captured from AXI bus. -- As BRAM address is loaded from pipe and ready to be presented to BRAM. -- Assert BRAM WE. (bram_addr_ld_en = '1' and axi_awaddr_full = '1' and awaddr_pipe_sel = '1')) and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Negate write data full condition axi_wdata_full_cmb <= '0'; -- Check if single or burst operation if (axi_wr_burst = '1') then wr_data_sm_ns <= BRST_WR_DATA; else wr_data_sm_ns <= SNG_WR_DATA; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; delay_aw_active_clr_cmb <= '1'; end if; else -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. axi_wdata_full_cmb <= '1'; end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- No need to check for BVALID assertion here. -- Move here under if clause on write response channel -- acknowledging completion of write data. -- If aw_active was not cleared prior to this state, then -- clear the flag now. if (delay_aw_active_clr = '1') then delay_aw_active_clr_cmb <= '0'; aw_active_clr <= '1'; end if; -- Add check here if while writing single data beat to BRAM, -- a new AXI data beat is received (prior to the AWVALID assertion). -- Ensure here that full flag is asserted for data pipeline state. -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then -- Load write data register wrdata_reg_ld <= '1'; -- Must also load WE register bram_we_ld <= '1'; -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. -- Ensure that axi_wdata_full_reg is asserted -- to prevent early captures on next data burst (or single data -- transfer) -- This ensures that the data beats do not get skipped. axi_wdata_full_cmb <= '1'; -- AWADDR not yet received -- Go to wait for write address wr_data_sm_ns <= W8_AWADDR; -- Accept no more new write data after this first data beat -- Pipeline is already full in this state. No need to assert -- no_wdata_accept flag to '1'. -- Set flag for single/burst write operation -- when AWADDR is not yet received if (AXI_WLAST = '1') then axi_wr_burst_cmb <= '0'; else axi_wr_burst_cmb <= '1'; end if; -- WLAST else -- No subsequent pending operation -- Return to IDLE wr_data_sm_ns <= IDLE; bram_addr_rst_cmb <= '1'; end if; ------------------------- BRST_WR_DATA State ------------------------- when BRST_WR_DATA => -- Reach this state at the 2nd data beat of a burst -- AWADDR is already accepted -- Continue to accept data from AXI write channel -- and wait for assertion of WLAST -- Check that WVALID remains asserted for burst -- If negated, indicates throttling from AXI master if (AXI_WVALID = '1') then -- If WVALID is asserted for the 2nd and remaining -- data beats of the transfer -- Continue w/ BRAM write enable assertion & advance -- write data register wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register bram_en_cmb <= '1'; -- Initiate BRAM write transfer bram_addr_inc <= '1'; -- Increment BRAM address counter -- Check for last data beat in burst transfer if (AXI_WLAST = '1') then -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- The elgible signal will not be asserted for a subsequent -- single data beat operation. Next operation is a burst. -- And the AWADDR is loaded in the address pipeline. -- Only if BVALID counter can handle next transfer, -- proceed with back-to-back. Otherwise, go to IDLE -- (after last data write). if (wr_b2b_elgible = '1' and bvalid_cnt_amax = '0') then -- Go to next operation and handle as a -- back-to-back burst. No empty clock cycles. -- Go to handle new burst for back to back condition wr_data_sm_ns <= B2B_W8_WR_DATA; axi_wr_burst_cmb <= '1'; -- No pending subsequent transfer (burst > 2 data beats) -- to process else -- Last/single data write wr_data_sm_ns <= SNG_WR_DATA; -- Be sure to clear aw_active flag at end of write burst -- But delay when the flag is cleared delay_aw_active_clr_cmb <= '1'; end if; end if; -- WLAST -- Throttling -- Suspend BRAM write & halt write data & WE register load else wrdata_reg_ld <= '0'; -- Negate write data register load bram_we_ld <= '0'; -- Negate WE register load bram_en_cmb <= '0'; -- Negate write to BRAM bram_addr_inc <= '0'; -- Do not increment BRAM address counter end if; -- WVALID ------------------------- B2B_W8_WR_DATA -------------------------- when B2B_W8_WR_DATA => -- Reach this state upon a back-to-back condition -- when BVALID/BREADY handshake is received, -- but WVALID is not yet asserted for subsequent transfer. -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then -- Load write data register wrdata_reg_ld <= '1'; -- Load WE register bram_we_ld <= '1'; -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Burst data write wr_data_sm_ns <= BRST_WR_DATA; axi_wr_burst_cmb <= '1'; -- Make modification to last_data_ack_mod signal -- so that it is asserted when this state is reached -- and the BRAM address counter gets loaded. -- WVALID not yet asserted else wrdata_reg_ld <= '0'; -- Negate write data register load bram_we_ld <= '0'; -- Negate WE register load bram_en_cmb <= '0'; -- Negate write to BRAM bram_addr_inc <= '0'; -- Do not increment BRAM address counter end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_data_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_sm_cs <= IDLE; bram_en_int <= '0'; clr_bram_we <= '0'; delay_aw_active_clr <= '0'; axi_wdata_full_reg <= '0'; else wr_data_sm_cs <= wr_data_sm_ns; bram_en_int <= bram_en_cmb; clr_bram_we <= clr_bram_we_cmb; delay_aw_active_clr <= delay_aw_active_clr_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; end if; end if; end process WR_DATA_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY; --------------------------------------------------------------------------- WR_BURST_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wr_burst <= '0'; else axi_wr_burst <= axi_wr_burst_cmb; end if; end if; end process WR_BURST_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- * AXI Write Response Channel Interface * --------------------------------------------------------------------------- -- v1.03a --------------------------------------------------------------------------- -- -- -- New FIFO storage for BID, so AWID can be stored in -- a FIFO and B response is seperated from W response. -- -- Use registered WREADY & BID FIFO in single port configuration. -- --------------------------------------------------------------------------- -- Instantiate FIFO to store BID values to be asserted back on B channel. -- Only 8 entries deep, BVALID counter only allows W channel to be 8 ahead of -- B channel. -- -- If AWID is a single bit wide, sythesis optimizes the module, srl_fifo, -- to a single SRL16E library module. BID_FIFO: entity work.srl_fifo generic map ( C_DATA_BITS => C_AXI_ID_WIDTH, C_DEPTH => 8 ) port map ( Clk => S_AXI_AClk, Reset => bid_fifo_rst, FIFO_Write => bid_fifo_ld_en, Data_In => bid_fifo_ld, FIFO_Read => bid_fifo_rd_en, Data_Out => bid_fifo_rd, FIFO_Full => open, Data_Exists => bid_fifo_not_empty, Addr => open ); bid_fifo_rst <= not (S_AXI_AResetn); bid_fifo_ld_en <= bram_addr_ld_en; bid_fifo_ld <= AXI_AWID when (awaddr_pipe_sel = '0') else axi_awid_pipe; -- Read from FIFO when BVALID is to be asserted on bus, or in a back-to-back assertion -- when a BID value is available in the FIFO. bid_fifo_rd_en <= bid_fifo_not_empty and -- Only read if data is available. ((bid_gets_fifo_load_d1) or -- a) Do the FIFO read in the clock cycle -- following the BID value directly -- aserted on the B channel (from AWID or pipeline). (first_fifo_bid) or -- b) Read from FIFO when BID is previously stored -- but BVALID is not yet asserted on AXI. (bvalid_cnt_dec)); -- c) Or read when next BID value is to be updated -- on B channel (and exists waiting in FIFO). -- 1) Special case (1st load in FIFO) (and single clock cycle turnaround needed on BID, from AWID). -- If loading the FIFO and BVALID is to be asserted in the next clock cycle -- Then capture this condition to read from FIFO in the subsequent clock cycle -- (and clear the BID value stored in the FIFO). bid_gets_fifo_load <= '1' when (bid_fifo_ld_en = '1') and (first_fifo_bid = '1' or b2b_fifo_bid = '1') else '0'; first_fifo_bid <= '1' when ((bvalid_cnt_inc = '1') and (bvalid_cnt_non_zero = '0')) else '0'; -- 2) An additional special case. -- When write data register is loaded for single (bvalid_cnt = "001", due to WLAST/WVALID) -- But, AWID not yet received (FIFO is still empty). -- If BID FIFO is still empty with the BVALID counter decrement, but simultaneously -- is increment (same condition as first_fifo_bid). b2b_fifo_bid <= '1' when (bvalid_cnt_inc = '1' and bvalid_cnt_dec = '1' and bvalid_cnt = "001" and bid_fifo_not_empty = '0') else '0'; -- Output BID register to B AXI channel REG_BID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bid_int <= (others => '0'); -- If loading the FIFO and BVALID is to be asserted in the next clock cycle -- Then output the AWID or pipelined value (the same BID that gets loaded into FIFO). elsif (bid_gets_fifo_load = '1') then axi_bid_int <= bid_fifo_ld; -- If new value read from FIFO then ensure that value is updated on AXI. elsif (bid_fifo_rd_en = '1') then axi_bid_int <= bid_fifo_rd; else axi_bid_int <= axi_bid_int; end if; end if; end process REG_BID; -- Capture condition of BID output updated while the FIFO is also -- getting updated. Read FIFO in the subsequent clock cycle to -- clear the value stored in the FIFO. REG_BID_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bid_gets_fifo_load_d1 <= '0'; else bid_gets_fifo_load_d1 <= bid_gets_fifo_load; end if; end if; end process REG_BID_LD; --------------------------------------------------------------------------- -- AXI_BRESP Output Register --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_BRESP -- Purpose: Generate BRESP output signal when ECC is disabled. -- Only allowable output is RESP_OKAY. --------------------------------------------------------------------------- GEN_BRESP: if C_ECC = 0 generate begin REG_BRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bresp_int <= (others => '0'); -- elsif (AXI_WLAST = '1') then -- CR # 609695 elsif ((AXI_WLAST and AXI_WVALID and axi_wready_int_mod) = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported axi_bresp_int <= RESP_OKAY; else axi_bresp_int <= axi_bresp_int; end if; end if; end process REG_BRESP; end generate GEN_BRESP; --------------------------------------------------------------------------- -- Generate: GEN_BRESP_ECC -- Purpose: Generate BRESP output signal when ECC is enabled -- If no ECC error condition is detected during the RMW -- sequence, then output will be RESP_OKAY. When an -- uncorrectable error is detected, the output will RESP_SLVERR. --------------------------------------------------------------------------- GEN_BRESP_ECC: if C_ECC = 1 generate signal UE_Q_reg : std_logic := '0'; begin REG_BRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bresp_int <= (others => '0'); elsif (bvalid_cnt_inc_d1 = '1') then --coverage off -- Exclusive operations not yet supported -- If no ECC errors occur, respond with OK if (UE_Q = '1') or (UE_Q_reg = '1') then axi_bresp_int <= RESP_SLVERR; --coverage on else axi_bresp_int <= RESP_OKAY; end if; else axi_bresp_int <= axi_bresp_int; end if; end if; end process REG_BRESP; -- Check if any error conditions occured during the write operation. -- Capture condition for each write transfer. REG_UE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear at end of current write (and ensure the flag is cleared -- at the beginning of a write transfer) if (S_AXI_AResetn = C_RESET_ACTIVE) or (aw_active_re = '1') or (AXI_BREADY = '1' and axi_bvalid_int = '1') then UE_Q_reg <= '0'; --coverage off elsif (UE_Q = '1') then UE_Q_reg <= '1'; --coverage on else UE_Q_reg <= UE_Q_reg; end if; end if; end process REG_UE; end generate GEN_BRESP_ECC; -- v1.03a --------------------------------------------------------------------------- -- Instantiate BVALID counter outside of specific SM generate block. --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- BVALID counter to track the # of required BVALID/BREADY handshakes -- needed to occur on the AXI interface. Based on early and seperate -- AWVALID/AWREADY and WVALID/WREADY handshake exchanges. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt <= (others => '0'); -- Ensure we only increment counter wyhen BREADY is not asserted elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1); -- Ensure that we only decrement when SM is not incrementing elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1); else bvalid_cnt <= bvalid_cnt; end if; end if; end process REG_BVALID_CNT; bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt_non_zero = '1') else '0'; bvalid_cnt_non_zero <= '1' when (bvalid_cnt /= "000") else '0'; bvalid_cnt_amax <= '1' when (bvalid_cnt = "110") else '0'; bvalid_cnt_max <= '1' when (bvalid_cnt = "111") else '0'; -- Replace BVALID output register -- Assert BVALID as long as BVALID counter /= zero REG_BVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Ensure that if we are also incrementing BVALID counter, the BVALID stays asserted. (bvalid_cnt = "001" and bvalid_cnt_dec = '1' and bvalid_cnt_inc = '0') then axi_bvalid_int <= '0'; elsif (bvalid_cnt_non_zero = '1') or (bvalid_cnt_inc = '1') then axi_bvalid_int <= '1'; else axi_bvalid_int <= '0'; end if; end if; end process REG_BVALID; --------------------------------------------------------------------------- -- * ECC Logic *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite) constant null8 : std_logic_vector(0 to 7) := "00000000"; -- Specific to 64-bit data width -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. constant C_USE_LUT6 : boolean := TRUE; signal RdECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Temp signal WrECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal WrECC_i : std_logic_vector(C_ECC_WIDTH-1 downto 0) := (others => '0'); signal AXI_WSTRB_Q : std_logic_vector((C_AXI_DATA_WIDTH/8 - 1) downto 0) := (others => '0'); signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to 64-bit ECC signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Read_i : std_logic := '0'; signal RdModifyWr_Check : std_logic := '0'; signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal UnCorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1) := (others => '0'); signal CE_Q : std_logic := '0'; signal Sl_CE_i : std_logic := '0'; signal Sl_UE_i : std_logic := '0'; subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- 0:6 for 32-bit ECC -- 0:7 for 64-bit ECC type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits; type bool_array is array (natural range 0 to 6) of boolean; constant inverted_bit : bool_array := (false,false,true,false,true,false,false); -- v1.03a constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0); begin -- Generate signal to advance BRAM read address pipeline to -- capture address for ECC error conditions (in lite_ecc_reg module). BRAM_Addr_En <= RdModifyWr_Read; -- v1.03a RdModifyWr_Read <= '1' when (wr_data_ecc_sm_cs = RMW_RD_DATA) else '0'; RdModifyWr_Modify <= '1' when (wr_data_ecc_sm_cs = RMW_MOD_DATA) else '0'; RdModifyWr_Write <= '1' when (wr_data_ecc_sm_cs = RMW_WR_DATA) else '0'; ----------------------------------------------------------------------- -- Remember write data one cycle to be available after read has been completed in a -- read/modify write operation. -- Save WSTRBs here in this register REG_WSTRB : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then AXI_WSTRB_Q <= (others => '0'); elsif (wrdata_reg_ld = '1') then AXI_WSTRB_Q <= AXI_WSTRB; end if; end if; end process REG_WSTRB; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_WRDATA_CMB -- Purpose: Replace manual signal assignment for WrData_cmb with -- generate funtion. -- -- Ensure correct byte swapping occurs with -- CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) assignment -- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0). -- -- AXI_WSTRB_Q (C_AXI_DATA_WIDTH_BYTES-1 downto 0) matches -- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0). -- ------------------------------------------------------------------------ GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate begin WrData_cmb ( (((i+1)8)-1) downto i8 ) <= bram_wrdata_int ((((i+1)8)-1) downto i8) when (RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1') else CorrectedRdData ( (C_AXI_DATA_WIDTH - ((i+1)8)) to (C_AXI_DATA_WIDTH - (i8) - 1) ); end generate GEN_WRDATA_CMB; REG_WRDATA : process (S_AXI_AClk) is begin -- Remove reset value to minimize resources & improve timing if (S_AXI_AClk'event and S_AXI_AClk = '1') then WrData <= WrData_cmb; end if; end process REG_WRDATA; ------------------------------------------------------------------------ -- New assignment of ECC bits to BRAM write data outside generate -- blocks. Same signal assignment regardless of ECC type. BRAM_WrData ((C_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto C_AXI_DATA_WIDTH) <= WrECC_i xor FaultInjectECC; ------------------------------------------------------------------------ -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0); signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); begin ---------------------- Hsiao ECC Write Logic ---------------------- -- Instantiate ecc_gen_hsiao module, generated from MIG ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); -- Merge muxed rd/write data to gen HSIAO_ECC: process (h_rows, WrData) constant DQ_WIDTH : integer := CODE_WIDTH; variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_AXI_DATA_WIDTH); begin -- Loop to generate all ECC bits for k in 0 to ECC_WIDTH - 1 loop ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_AXI_DATA_WIDTH - 1 downto 0) and h_rows (k * CODE_WIDTH + C_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH))); end loop; WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_AXI_DATA_WIDTH); end process HSIAO_ECC; ----------------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: For 32-bit ECC implementations, assign unused -- MSB of ECC output to BRAM with '0'. ----------------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate begin -- Account for 32-bit and MSB '0' of ECC bits WrECC_i <= '0' & WrECC; end generate GEN_ECC_32; ----------------------------------------------------------------------- -- Generate: GEN_ECC_N -- Purpose: For all non 32-bit ECC implementations, assign ECC -- bits for BRAM output. ----------------------------------------------------------------------- GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate begin WrECC_i <= WrECC; end generate GEN_ECC_N; ---------------------- Hsiao ECC Read Logic ----------------------- GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( BRAM_RdData (CODE_WIDTH-1 downto 0) and h_rows ((mCODE_WIDTH)+CODE_WIDTH-1 downto (mCODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; end if; end process REG_SYNDROME; ecc_rddata_r <= UnCorrectedRdData; -- Reconstruct H-matrix H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_AXI_DATA_WIDTH-1 downto 0); Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin ----------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: Assign ECC out data vector (N:0) unique for 32-bit BRAM. -- Add extra '0' at MSB of ECC vector for data2mem alignment -- w/ 32-bit BRAM data widths. -- ECC bits are in upper order bits. ----------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate constant correct_data_table_32 : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC begin --------------------- Hamming 32-bit ECC Write Logic ------------------ ------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_32 -- Description: Generate ECC bits for writing into BRAM. -- WrData (N:0) ------------------------------------------------------------------------- CHK_HANDLER_WR_32: entity work.checkbit_handler generic map ( C_ENCODE => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( DataIn => WrData, -- [in std_logic_vector(0 to 31)] CheckIn => null7, -- [in std_logic_vector(0 to 6)] CheckOut => WrECC, -- [out std_logic_vector(0 to 6)] Syndrome => open, -- [out std_logic_vector(0 to 6)] Syndrome_4 => open, -- [out std_logic_vector(0 to 1)] Syndrome_6 => open, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)] Enable_ECC => '1', -- [in std_logic] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] -- v1.03a -- Account for 32-bit and MSB '0' of ECC bits WrECC_i <= '0' & WrECC; --------------------- Hamming 32-bit ECC Read Logic ------------------- -------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) -------------------------------------------------------------------------- CHK_HANDLER_RD_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- DataIn (8:39) -- CheckIn (1:7) DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)] CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] --------------------------------------------------------------------------- -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl -- w/ balanced pipeline stage) before correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_32 (i)) port map ( DIn => UnCorrectedRdData (i), Syndrome => syndrome_reg_i, DCorr => CorrectedRdData (i)); end generate GEN_CORR_32; end generate GEN_ECC_32; ----------------------------------------------------------------- -- Generate: GEN_ECC_64 -- Purpose: Assign ECC out data vector (N:0) unique for 64-bit BRAM. -- No extra '0' at MSB of ECC vector for data2mem alignment -- w/ 64-bit BRAM data widths. -- ECC bits are in upper order bits. ----------------------------------------------------------------- GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate constant correct_data_table_64 : correct_data_table_type := ( 0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001", 4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001", 8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001", 12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001", 16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001", 20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001", 24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101", 28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101", 32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101", 36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101", 40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101", 44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101", 48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101", 52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101", 56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011", 60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011" ); signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); signal syndrome7_a : std_logic := '0'; signal syndrome7_b : std_logic := '0'; begin --------------------- Hamming 64-bit ECC Write Logic ------------------ --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_64 -- Description: Generate ECC bits for writing into BRAM when configured -- as 64-bit wide BRAM. -- WrData (N:0) -- Enable C_REG on encode path. --------------------------------------------------------------------------- CHK_HANDLER_WR_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => true, -- [boolean] C_REG => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] DataIn => WrData_cmb, -- [in std_logic_vector(0 to 63)] CheckIn => null8, -- [in std_logic_vector(0 to 7)] CheckOut => WrECC, -- [out std_logic_vector(0 to 7)] Syndrome => open, -- [out std_logic_vector(0 to 7)] Syndrome_7 => open, -- [out std_logic_vector(0 to 11)] Syndrome_Chk => null8, -- [in std_logic_vector(0 to 7)] Enable_ECC => '1', -- [in std_logic] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] -- Note: (7:0) Old bit lane assignment -- BRAM_WrData ((C_ECC_WIDTH - 1) downto 0) -- v1.02a -- WrECC is assigned to BRAM_WrData (71:64) -- v1.03a -- BRAM_WrData (71:64) assignment done outside of this -- ECC type generate block. WrECC_i <= WrECC; --------------------- Hamming 64-bit ECC Read Logic ------------------- --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_64 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_RD_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => false, -- [boolean] C_REG => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] -- DataIn (8:71) -- CheckIn (0:7) DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)] CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 7)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)] Syndrome_7 => Syndrome_7, -- [out std_logic_vector(0 to 11)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] --------------------------------------------------------------------------- -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_7_reg <= Syndrome_7; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Move final XOR to registered side of syndrome bits. -- Do last XOR on select syndrome bits after pipeline stage -- before correct_one_bit_64 module. syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6); PARITY_CHK7_A: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome7_a ); -- [out std_logic] PARITY_CHK7_B: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome7_b ); -- [out std_logic] syndrome_reg_i (7) <= syndrome7_a xor syndrome7_b; --------------------------------------------------------------------------- -- Generate: GEN_CORRECT_DATA -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_64 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_64: entity work.correct_one_bit_64 generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_64 (i)) port map ( DIn => UnCorrectedRdData (i), Syndrome => syndrome_reg_i, DCorr => CorrectedRdData (i)); end generate GEN_CORR_64; end generate GEN_ECC_64; end generate GEN_HAMMING_ECC; -- Remember correctable/uncorrectable error from BRAM read CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if RdModifyWr_Modify = '1' then -- Capture error signals CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- ECC register block gets registered UE or CE conditions to update -- ECC registers/interrupt/flag outputs. Sl_CE <= CE_Q; Sl_UE <= UE_Q; CE_Failing_We <= CE_Q; FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0'; ----------------------------------------------------------------------- -- Add register delay on BVALID counter increment -- Used to clear fault inject register. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt_inc_d1 <= '0'; else bvalid_cnt_inc_d1 <= bvalid_cnt_inc; end if; end if; end process REG_BVALID_CNT; ----------------------------------------------------------------------- -- Map BRAM_RdData (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: For 32-bit ECC implementations, account for -- extra bit in read data mapping on registered value. ----------------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate begin -- Insert register stage for read data to correct REG_CHK_DATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH); end if; end process REG_CHK_DATA; end generate GEN_ECC_32; ----------------------------------------------------------------------- -- Generate: GEN_ECC_N -- Purpose: For all non 32-bit ECC implementations, assign ECC -- bits for BRAM output. ----------------------------------------------------------------------- GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate begin -- Insert register stage for read data to correct REG_CHK_DATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1); end if; end process REG_CHK_DATA; end generate GEN_ECC_N; end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Drive default output signals when ECC is diabled. --------------------------------------------------------------------------- GEN_NO_ECC: if C_ECC = 0 generate begin BRAM_Addr_En <= '0'; FaultInjectClr <= '0'; CE_Failing_We <= '0'; Sl_CE <= '0'; Sl_UE <= '0'; end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- * BRAM Interface Signals * --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WE -- Purpose: BRAM WE generate process -- One WE per 8-bits of BRAM data. --------------------------------------------------------------------------- GEN_BRAM_WE: for i in C_AXI_DATA_WIDTH/8 + (C_ECC*(1+(C_AXI_DATA_WIDTH/128))) - 1 downto 0 generate begin BRAM_WE (i) <= bram_we_int (i); end generate GEN_BRAM_WE; --------------------------------------------------------------------------- BRAM_En <= bram_en_int; --------------------------------------------------------------------------- -- BRAM Address Generate --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. -- --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WRDATA -- Purpose: Generate BRAM Write Data. --------------------------------------------------------------------------- GEN_BRAM_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin -- Check if ECC is enabled -- If so, XOR the fault injection vector with the data -- (post-pipeline) to avoid any timing issues on the data vector -- from AXI. ----------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is disabled. ----------------------------------------------------------------------- GEN_NO_ECC : if C_ECC = 0 generate begin BRAM_WrData (i) <= bram_wrdata_int (i); end generate GEN_NO_ECC; ----------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is enable -- (use fault vector) -- (N:0) -- for 32-bit (31:0) WrData while (ECC = [39:32]) ----------------------------------------------------------------------- GEN_W_ECC : if C_ECC = 1 generate begin BRAM_WrData (i) <= WrData (i) xor FaultInjectData (i); end generate GEN_W_ECC; end generate GEN_BRAM_WRDATA; --------------------------------------------------------------------------- end architecture implementation;	bsd-2-clause	5f18d2348e650d8c0a1f2c0ecac0c6ce	0.416174	4.795635	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/conditional_waveforms/rule_501_test_input.fixed_lower.vhd	1	400	architecture rtl of fifo is begin process begin var1 := '0' when rd_en = '1' ELSE '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' when rd_en = '1' ELSE '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' when rd_en = '1' else '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;	gpl-3.0	8acf6c44e6068b5d74722bd09b449a70	0.54	2.564103	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/if_statement/rule_002_test_input.fixed_parenthesis_remove.vhd	1	1,508	architecture RTL of FIFO is begin process begin if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; elsif a(3 downto 0) = 0 then b <= '0'; elsif a(3 downto 0) + f(34, 56, 72) - g(f(35, 25, 60) downto h(45, 32)) then b <= '1'; elsif (a or b) and (c or d) then b <= '0'; end if; -- Violations below if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; elsif a(3 downto 0) = 0 then b <= '0'; elsif a(3 downto 0) + f(34, 56, 72) - g(f(35, 25, 60) downto h(45, 32)) then b <= '1'; elsif (a or b) and (c or d) then b <= '0'; end if; end process; process begin if (x(k) = '1') and (v_y = '0') then b <= '0'; end if; if ((ctrl_done_d1 = '0') and (CTRL_DONE = '1')) or (dev_addr = dev_addr_prv) then b <= '0'; end if; end process; process begin if (sync_reset) = '1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; end process; process begin if something then b <= 0; elsif something_else then b <= 1; end if; if something then b <= 0; elsif something_else then b <= 1; end if; end process; end architecture RTL;	gpl-3.0	1492e91421ff1ffc1ca3d5ebd1535f81	0.440981	2.9	false	false	false	false
jeremiah-c-leary/vhdl-style-guide	vsg/tests/conditional_waveforms/rule_500_test_input.vhd	2	400	architecture rtl of fifo is begin process begin var1 := '0' WHEN rd_en = '1' else '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' WHEN rd_en = '1' else '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;	gpl-3.0	14bddea23108b1bda8a233e34e25356a	0.54	2.564103	false	false	false	false
Yarr/Yarr-fw	rtl/trigger-logic/delayer.vhd	1	1,125	-- #################################### -- # Project: Yarr -- # Author: Vyassa Baratham -- # E-Mail: vbaratham at berkeley.edu -- # Comments: Allows configurable delay of up to N clk cycles -- # Data: 09/2017 -- # Outputs are synchronous to clk_i -- #################################### library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity delayer is generic (N : integer); -- shift register width port ( clk_i : in std_logic; rst_n_i : in std_logic; dat_i : in std_logic; dat_o : out std_logic; delay : in std_logic_vector(N-1 downto 0) ); end delayer; architecture rtl of delayer is signal shift_reg : std_logic_vector(2N-1 downto 0); begin proc : process(clk_i, rst_n_i) begin if (rst_n_i = '0') then dat_o <= '0'; shift_reg <= (others => '0'); elsif rising_edge(clk_i) then shift_reg(2N-1 downto 1) <= shift_reg(2**N-2 downto 0); shift_reg(0) <= dat_i; dat_o <= shift_reg(to_integer(unsigned(delay))); end if; end process proc; end rtl;	gpl-3.0	524e9a1198e282374174318899b5a09b	0.535111	3.270349	false	false	false	false
Yarr/Yarr-fw	rtl/kintex7/rx-core/wb_rx_bridge.vhd	1	13,975	-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: Bridge between Rx core and Mem -- #################################### -- # Address Map: -- # 0x0000: Start Adr (RO) -- # 0x0001: Data Cnt (RO) -- # 0x0002[0]: Loopback (RW) -- # 0x0003: Data Rate (RO) -- # 0x0004: Loop Fifo (WO) library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity wb_rx_bridge is port ( -- Sys Connect sys_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- Wishbone DMA Master Interface dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(63 downto 0); dma_dat_i : in std_logic_vector(63 downto 0); dma_cyc_o : out std_logic; dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_ack_i : in std_logic; dma_stall_i : in std_logic; -- Rx Interface rx_data_i : in std_logic_vector(63 downto 0); rx_valid_i : in std_logic; -- Status In trig_pulse_i : in std_logic; -- Status out irq_o : out std_logic; busy_o : out std_logic ); end wb_rx_bridge; architecture Behavioral of wb_rx_bridge is -- Cmoponents COMPONENT rx_bridge_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC ); END COMPONENT; COMPONENT rx_bridge_ctrl_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; -- Constants constant c_ALMOST_FULL_THRESHOLD : unsigned(7 downto 0) := TO_UNSIGNED(240, 8); constant c_PACKAGE_SIZE : unsigned(31 downto 0) := TO_UNSIGNED((168030), 32); -- ~200kByte, magic number (!!) divisible my any channel number of to 8 constant c_TIMEOUT : unsigned(31 downto 0) := TO_UNSIGNED(2*14, 32); -- Counts in 5ns = 0.1ms constant c_TIME_FRAME : unsigned(31 downto 0) := TO_UNSIGNED(200000000-1, 32); -- 200MHz clock cycles in 1 sec constant c_EMPTY_THRESHOLD : unsigned(7 downto 0) := TO_UNSIGNED(16, 8); constant c_EMPTY_TIMEOUT : unsigned(9 downto 0) := TO_UNSIGNED(2000, 10); -- Signals signal data_fifo_din : std_logic_vector(63 downto 0); signal data_fifo_dout : std_logic_vector(63 downto 0); signal data_fifo_wren : std_logic; signal data_fifo_rden : std_logic; signal data_fifo_full : std_logic; signal data_fifo_empty : std_logic; signal data_fifo_almost_full : std_logic; signal data_fifo_prog_empty : std_logic; signal data_fifo_empty_cnt : unsigned(10 downto 0); signal data_fifo_empty_true : std_logic; signal data_fifo_empty_pressure : std_logic; signal ctrl_fifo_din : std_logic_vector(63 downto 0); signal ctrl_fifo_dout : std_logic_vector(63 downto 0); signal ctrl_fifo_wren : std_logic; signal ctrl_fifo_rden : std_logic; signal ctrl_fifo_full : std_logic; signal ctrl_fifo_empty : std_logic; signal dma_stb_t : std_logic; signal dma_stb_valid : std_logic; signal dma_adr_cnt : unsigned(31 downto 0); signal dma_start_adr : unsigned(31 downto 0); signal dma_data_cnt : unsigned(31 downto 0); signal dma_data_cnt_d : unsigned(31 downto 0); signal dma_timeout_cnt : unsigned(31 downto 0); signal dma_ack_cnt : unsigned(7 downto 0); signal rx_data_local : std_logic_vector(31 downto 0); signal rx_valid_local : std_logic; signal rx_data_local_d : std_logic_vector(31 downto 0); signal rx_valid_local_d : std_logic; signal ctrl_fifo_dout_tmp : std_logic_vector(31 downto 0); signal time_cnt : unsigned(31 downto 0); signal time_pulse : std_logic; signal data_rate_cnt : unsigned(31 downto 0); signal trig_cnt : unsigned(31 downto 0); signal trig_pulse_d0 : std_logic; signal trig_pulse_d1 : std_logic; signal trig_pulse_pos : std_logic; -- Registers signal loopback : std_logic; signal data_rate : std_logic_vector(31 downto 0); begin --Tie offs irq_o <= '0'; busy_o <= data_fifo_full; -- Wishbone Slave wb_slave_proc: process(sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; wb_stall_o <= '0'; ctrl_fifo_rden <= '0'; rx_valid_local <= '0'; ctrl_fifo_dout_tmp <= (others => '0'); -- Regs loopback <= '0'; elsif rising_edge(sys_clk_i) then -- Default wb_ack_o <= '0'; ctrl_fifo_rden <= '0'; wb_stall_o <= '0'; rx_valid_local <= '0'; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '0') then -- READ if (wb_adr_i(3 downto 0) = x"0") then -- Start Addr if (ctrl_fifo_empty = '0') then wb_dat_o <= ctrl_fifo_dout(31 downto 0); ctrl_fifo_dout_tmp <= ctrl_fifo_dout(63 downto 32); wb_ack_o <= '1'; ctrl_fifo_rden <= '1'; else wb_dat_o <= x"FFFFFFFF"; ctrl_fifo_dout_tmp <= (others => '0'); wb_ack_o <= '1'; ctrl_fifo_rden <= '0'; end if; elsif (wb_adr_i(3 downto 0) = x"1") then -- Count wb_dat_o <= ctrl_fifo_dout_tmp; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"2") then -- Loopback wb_dat_o(31 downto 1) <= (others => '0'); wb_dat_o(0) <= loopback; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"3") then -- Data Rate wb_dat_o <= data_rate; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"5") then -- Bridge Empty wb_dat_o(31 downto 1) <= (others => '0'); wb_dat_o(0) <= data_fifo_empty_true; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"6") then -- Cur Count wb_dat_o <= std_logic_vector(dma_data_cnt_d); wb_ack_o <= '1'; else wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end if; else -- WRITE wb_ack_o <= '1'; if (wb_adr_i(3 downto 0) = x"2") then loopback <= wb_dat_i(0); elsif (wb_adr_i(3 downto 0) = x"4") then rx_valid_local <= '1'; end if; end if; end if; end if; end process wb_slave_proc; -- Data from Rx data_rec : process (sys_clk_i, rst_n_i) begin if (rst_n_i <= '0') then data_fifo_wren <= '0'; data_fifo_din <= (others => '0'); elsif rising_edge(sys_clk_i) then if (loopback = '1') then data_fifo_wren <= rx_valid_local_d; data_fifo_din <= X"03000000" & rx_data_local_d; else data_fifo_wren <= rx_valid_i; data_fifo_din <= rx_data_i; end if; end if; end process data_rec; -- Empty logic to produce some backpressure data_fifo_empty <= '1' when (data_fifo_empty_true = '1') else data_fifo_empty_pressure; empty_proc : process(dma_clk_i, rst_n_i) begin if (rst_n_i = '0') then data_fifo_empty_pressure <= '0'; data_fifo_empty_cnt <= (others => '0'); elsif rising_edge(dma_clk_i) then -- Timeout Counter if (data_fifo_empty_true = '0' and data_fifo_empty_pressure = '1') then data_fifo_empty_cnt <= data_fifo_empty_cnt + 1; elsif (data_fifo_empty_true = '1') then data_fifo_empty_cnt <= (others => '0'); end if; if (data_fifo_empty_cnt > c_EMPTY_TIMEOUT) then data_fifo_empty_pressure <= '0'; elsif (data_fifo_prog_empty = '0') then data_fifo_empty_pressure <= '0'; elsif (data_fifo_empty_true = '1') then data_fifo_empty_pressure <= '1'; end if; end if; end process empty_proc; -- DMA Master and data control dma_stb_valid <= dma_stb_t and not data_fifo_empty; to_ddr_proc: process(dma_clk_i, rst_n_i) begin if(rst_n_i = '0') then dma_stb_t <= '0'; data_fifo_rden <= '0'; dma_adr_o <= (others => '0'); dma_dat_o <= (others => '0'); dma_cyc_o <= '0'; dma_stb_o <= '0'; dma_we_o <= '1'; -- Write only elsif rising_edge(dma_clk_i) then if (data_fifo_empty = '0' and dma_stall_i = '0' and ctrl_fifo_full = '0') then dma_stb_t <= '1'; data_fifo_rden <= '1'; else dma_stb_t <= '0'; data_fifo_rden <= '0'; end if; if (data_fifo_empty = '0' or dma_ack_cnt > 0) then dma_cyc_o <= '1'; else dma_cyc_o <= '0'; end if; dma_adr_o <= std_logic_vector(dma_adr_cnt); dma_dat_o <= data_fifo_dout; dma_stb_o <= dma_stb_t and not data_fifo_empty; dma_we_o <= '1'; -- Write only end if; end process to_ddr_proc; adr_proc : process (dma_clk_i, rst_n_i) begin if (rst_n_i = '0') then ctrl_fifo_wren <= '0'; dma_adr_cnt <= (others => '0'); dma_start_adr <= (others => '0'); dma_data_cnt <= (others => '0'); dma_data_cnt_d <= (others => '0'); dma_timeout_cnt <= (others => '0'); ctrl_fifo_din(63 downto 0) <= (others => '0'); dma_ack_cnt <= (others => '0'); elsif rising_edge(dma_clk_i) then -- Address Counter if (dma_stb_valid = '1') then dma_adr_cnt <= dma_adr_cnt + 1; end if; if (dma_stb_valid = '1' and dma_ack_i = '0') then dma_ack_cnt <= dma_ack_cnt + 1; elsif (dma_stb_valid = '0' and dma_ack_i = '1' and dma_ack_cnt > 0) then dma_ack_cnt <= dma_ack_cnt - 1; end if; -- Package size counter -- Check if Fifo is full if (dma_stb_valid = '1' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE; dma_data_cnt <= TO_UNSIGNED(2, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '0' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE; dma_data_cnt <= TO_UNSIGNED(0, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '0' and dma_timeout_cnt >= c_TIMEOUT and dma_data_cnt > 0 and ctrl_fifo_full ='0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + dma_data_cnt; dma_data_cnt <= TO_UNSIGNED(0, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '1') then dma_data_cnt <= dma_data_cnt + 2; ctrl_fifo_wren <= '0'; else ctrl_fifo_wren <= '0'; end if; dma_data_cnt_d <= dma_data_cnt; -- if (dma_data_cnt = 0 and ctrl_fifo_wren = '1') then -- New package -- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt); -- elsif (dma_data_cnt = 1 and ctrl_fifo_wren = '1') then -- Flying take over -- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt-1); -- end if; -- Timeout counter if (dma_data_cnt > 0 and data_fifo_empty = '1') then dma_timeout_cnt <= dma_timeout_cnt + 1; elsif (data_fifo_empty = '0') then dma_timeout_cnt <= TO_UNSIGNED(0, 32); end if; end if; end process adr_proc; -- Data Rate maeasurement data_rate_proc: process(sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then data_rate_cnt <= (others => '0'); data_rate <= (others => '0'); time_cnt <= (others => '0'); time_pulse <= '0'; elsif rising_edge(sys_clk_i) then -- 1Hz pulser if (time_cnt = c_TIME_FRAME) then time_cnt <= (others => '0'); time_pulse <= '1'; else time_cnt <= time_cnt + 1; time_pulse <= '0'; end if; if (time_pulse = '1') then data_rate <= std_logic_vector(data_rate_cnt); data_rate_cnt <= (others => '0'); elsif (data_fifo_wren = '1') then data_rate_cnt <= data_rate_cnt + 1; end if; end if; end process data_rate_proc; -- Loopback delay delayproc : process (sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then rx_data_local <= (others => '0'); rx_data_local_d <= (others => '0'); rx_valid_local_d <= '0'; elsif rising_edge(sys_clk_i) then rx_data_local_d <= wb_dat_i; rx_valid_local_d <= rx_valid_local; end if; end process; -- Trigger sync and count trig_sync : process (sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then trig_pulse_d0 <= '0'; trig_pulse_d1 <= '0'; trig_pulse_pos <= '0'; trig_cnt <= (others => '0'); elsif rising_edge(sys_clk_i) then trig_pulse_d0 <= trig_pulse_i; trig_pulse_d1 <= trig_pulse_d0; if (trig_pulse_d0 = '1' and trig_pulse_d1 = '0') then trig_pulse_pos <= '1'; else trig_pulse_pos <= '0'; end if; if (trig_pulse_pos = '1') then trig_cnt <= trig_cnt + 1; end if; end if; end process trig_sync; cmp_rx_bridge_fifo : rx_bridge_fifo PORT MAP ( rst => not rst_n_i, wr_clk => sys_clk_i, rd_clk => dma_clk_i, din => data_fifo_din, wr_en => data_fifo_wren, rd_en => data_fifo_rden, prog_full_thresh => std_logic_vector(c_ALMOST_FULL_THRESHOLD), prog_empty_thresh => std_logic_vector(c_EMPTY_THRESHOLD), dout => data_fifo_dout, full => data_fifo_full, empty => data_fifo_empty_true, prog_full => data_fifo_almost_full, prog_empty => data_fifo_prog_empty ); cmp_rx_bridge_ctrl_fifo : rx_bridge_ctrl_fifo PORT MAP ( rst => not rst_n_i, wr_clk => dma_clk_i, rd_clk => sys_clk_i, din => ctrl_fifo_din, wr_en => ctrl_fifo_wren, rd_en => ctrl_fifo_rden, dout => ctrl_fifo_dout, full => ctrl_fifo_full, empty => ctrl_fifo_empty ); end Behavioral;	gpl-3.0	b9717917d9cb14290b12ff081e8ca29b	0.593345	2.595654	false	false	false	false
tdaede/daala_zynq	daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_cntrl_strm.vhd	1	24,997	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_cntrl_strm.vhd -- Description: This entity is MM2S control stream logic -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.clog2; use proc_common_v4_0.proc_common_pkg.max2; ------------------------------------------------------------------------------- entity axi_sg_cntrl_strm is generic( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Control Stream Data Width C_FAMILY : string := "virtex7" -- Target FPGA Device Family ); port ( -- Secondary clock / reset m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Primary clock / reset -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- -- MM2S Error -- mm2s_stop : in std_logic ; -- -- -- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) -- cntrlstrm_fifo_wren : in std_logic ; -- cntrlstrm_fifo_din : in std_logic_vector -- (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); -- cntrlstrm_fifo_full : out std_logic ; -- -- -- -- Memory Map to Stream Control Stream Interface -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- ((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);-- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic ; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_cntrl_strm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_cntrl_strm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Number of words deep fifo needs to be -- Only 5 app fields, but set to 8 so depth is a power of 2 constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH); -- Width of fifo rd and wr counts - only used for proper fifo operation constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- FIFO signals signal cntrl_fifo_rden : std_logic := '0'; signal cntrl_fifo_empty : std_logic := '0'; signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0'); signal cntrl_fifo_dvalid: std_logic := '0'; signal cntrl_tdata : std_logic_vector (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0'); signal cntrl_tkeep : std_logic_vector ((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0'; signal cntrl_tvalid : std_logic := '0'; signal cntrl_tready : std_logic := '0'; signal cntrl_tlast : std_logic := '0'; signal sinit : std_logic := '0'; signal m_valid : std_logic := '0'; signal m_ready : std_logic := '0'; signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_last : std_logic := '0'; signal skid_rst : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- All bytes always valid cntrl_tkeep <= (others => '1'); -- Primary Clock is synchronous to Secondary Clock therfore -- instantiate a sync fifo. GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate signal mm2s_stop_d1 : std_logic := '0'; signal mm2s_stop_re : std_logic := '0'; signal xfer_in_progress : std_logic := '0'; begin -- reset on hard reset or mm2s stop sinit <= not m_axi_sg_aresetn or mm2s_stop; -- Generate Synchronous FIFO I_CNTRL_FIFO : entity proc_common_v4_0.sync_fifo_fg generic map ( C_FAMILY => C_FAMILY , C_MEMORY_TYPE => USE_LOGIC_FIFOS, C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1, C_WRITE_DEPTH => CNTRL_FIFO_DEPTH , C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1, C_READ_DEPTH => CNTRL_FIFO_DEPTH , C_PORTS_DIFFER => 0, C_HAS_DCOUNT => 0, --req for proper fifo operation C_HAS_ALMOST_FULL => 0, C_HAS_RD_ACK => 0, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_PRELOAD_REGS => 1,-- 1 = first word fall through C_PRELOAD_LATENCY => 0 -- 0 = first word fall through -- C_USE_EMBEDDED_REG => 1 -- 0 ; ) port map ( Clk => m_axi_sg_aclk , Sinit => sinit , Din => cntrlstrm_fifo_din , Wr_en => cntrlstrm_fifo_wren , Rd_en => cntrl_fifo_rden , Dout => cntrl_fifo_dout , Full => cntrlstrm_fifo_full , Empty => cntrl_fifo_empty , Almost_full => open , Data_count => open , Rd_ack => open , Rd_err => open , Wr_ack => open , Wr_err => open ); -- I_UPDT_DATA_FIFO : entity proc_common_v4_0.srl_fifo_f -- generic map ( -- C_DWIDTH => 33 , -- C_DEPTH => 24 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => cntrlstrm_fifo_wren , -- Data_In => cntrlstrm_fifo_din , -- FIFO_Read => cntrl_fifo_rden , -- Data_Out => cntrl_fifo_dout , -- FIFO_Empty => cntrl_fifo_empty , -- FIFO_Full => cntrlstrm_fifo_full, -- Addr => open -- ); cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty); VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then -- follower_reg_mm2s <= (others => '0'); follower_full_mm2s <= '0'; follower_empty_mm2s <= '1'; else if (cntrl_fifo_rden = '1') then -- follower_reg_mm2s <= sts_queue_dout; follower_full_mm2s <= '1'; follower_empty_mm2s <= '0'; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE; VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then follower_reg_mm2s <= (others => '0'); else if (cntrl_fifo_rden = '1') then follower_reg_mm2s <= cntrl_fifo_dout; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE1; ----------------------------------------------------------------------- -- Control Stream OUT Side ----------------------------------------------------------------------- -- Read if fifo is not empty and target is ready -- cntrl_fifo_rden <= not cntrl_fifo_empty -- and cntrl_tready; -- Drive valid if fifo is not empty or in the middle -- of transfer and stop issued. cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty or (xfer_in_progress and mm2s_stop_re); -- Pass data out to control channel with MSB driving tlast cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH)) or (xfer_in_progress and mm2s_stop_re); cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); -- Register stop to create re pulse for cleaning shutting down -- stream out during soft reset. REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_stop_d1 <= '0'; else mm2s_stop_d1 <= mm2s_stop; end if; end if; end process REG_STOP; mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1; ------------------------------------------------------------- -- Flag transfer in progress. If xfer in progress then -- a fake tlast and tvalid need to be asserted during soft -- reset else no need of tlast. ------------------------------------------------------------- TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then xfer_in_progress <= '0'; elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then xfer_in_progress <= '1'; end if; end if; end process TRANSFER_IN_PROGRESS; skid_rst <= not m_axi_sg_aresetn; --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- -- CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf -- generic map( -- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH -- ) -- port map( -- -- System Ports -- ACLK => m_axi_sg_aclk , -- ARST => skid_rst , -- skid_stop => mm2s_stop_re , -- -- Slave Side (Stream Data Input) -- S_VALID => cntrl_tvalid , -- S_READY => cntrl_tready , -- S_Data => cntrl_tdata , -- S_STRB => cntrl_tkeep , -- S_Last => cntrl_tlast , -- -- Master Side (Stream Data Output -- M_VALID => m_axis_mm2s_cntrl_tvalid , -- M_READY => m_axis_mm2s_cntrl_tready , -- M_Data => m_axis_mm2s_cntrl_tdata , -- M_STRB => m_axis_mm2s_cntrl_tkeep , -- M_Last => m_axis_mm2s_cntrl_tlast -- ); m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid; cntrl_tready <= m_axis_mm2s_cntrl_tready; m_axis_mm2s_cntrl_tdata <= cntrl_tdata; m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep; m_axis_mm2s_cntrl_tlast <= cntrl_tlast; end generate GEN_SYNC_FIFO; -- Primary Clock is asynchronous to Secondary Clock therfore -- instantiate an async fifo. GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate ATTRIBUTE async_reg : STRING; signal mm2s_stop_reg : std_logic := '0'; -- CR605883 signal p_mm2s_stop_d1_cdc_tig : std_logic := '0'; signal p_mm2s_stop_d2 : std_logic := '0'; signal p_mm2s_stop_d3 : std_logic := '0'; signal p_mm2s_stop_re : std_logic := '0'; signal xfer_in_progress : std_logic := '0'; -- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true"; begin -- reset on hard reset, soft reset, or mm2s error sinit <= not p_reset_n or p_mm2s_stop_d2; -- Generate Asynchronous FIFO I_CNTRL_STRM_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord generic map( C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 , -- Temp work around for issue in async fifo model C_DEPTH => CNTRL_FIFO_DEPTH-1 , C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH , -- C_DEPTH => 31 , -- C_CNT_WIDTH => 5 , C_USE_BLKMEM => USE_LOGIC_FIFOS , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => sinit , AFIFO_Wr_clk => m_axi_sg_aclk , AFIFO_Wr_en => cntrlstrm_fifo_wren , AFIFO_Din => cntrlstrm_fifo_din , AFIFO_Rd_clk => axi_prmry_aclk , AFIFO_Rd_en => cntrl_fifo_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => cntrl_fifo_dvalid , AFIFO_Dout => cntrl_fifo_dout , AFIFO_Full => cntrlstrm_fifo_full , AFIFO_Empty => cntrl_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); ----------------------------------------------------------------------- -- Control Stream OUT Side ----------------------------------------------------------------------- -- Read if fifo is not empty and target is ready cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data and cntrl_tready; -- target ready -- Drive valid if fifo is not empty or in the middle -- of transfer and stop issued. cntrl_tvalid <= cntrl_fifo_dvalid or (xfer_in_progress and p_mm2s_stop_re); -- Pass data out to control channel with MSB driving tlast cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH); -- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH)) -- or (xfer_in_progress and p_mm2s_stop_re); cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); -- CR605883 -- Register stop to provide pure FF output for synchronizer REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_stop_reg <= '0'; else mm2s_stop_reg <= mm2s_stop; end if; end if; end process REG_STOP; -- Double/triple register mm2s error into primary clock domain -- Triple register to give two versions with min double reg for use -- in rising edge detection. IMP_SYNC_FLOP : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => 2 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => mm2s_stop_reg, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => p_mm2s_stop_d2, scndry_vect_out => open ); REG_ERR2PRMRY : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then -- p_mm2s_stop_d1_cdc_tig <= '0'; -- p_mm2s_stop_d2 <= '0'; p_mm2s_stop_d3 <= '0'; else --p_mm2s_stop_d1_cdc_tig <= mm2s_stop; -- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg; -- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig; p_mm2s_stop_d3 <= p_mm2s_stop_d2; end if; end if; end process REG_ERR2PRMRY; -- Rising edge pulse for use in shutting down stream output p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3; ------------------------------------------------------------- -- Flag transfer in progress. If xfer in progress then -- a fake tlast needs to be asserted during soft reset. -- else no need of tlast. ------------------------------------------------------------- TRANSFER_IN_PROGRESS : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then xfer_in_progress <= '0'; elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then xfer_in_progress <= '1'; end if; end if; end process TRANSFER_IN_PROGRESS; skid_rst <= not p_reset_n; CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf generic map( C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ) port map( -- System Ports ACLK => axi_prmry_aclk , ARST => skid_rst , skid_stop => p_mm2s_stop_re , -- Slave Side (Stream Data Input) S_VALID => cntrl_tvalid , S_READY => cntrl_tready , S_Data => cntrl_tdata , S_STRB => cntrl_tkeep , S_Last => cntrl_tlast , -- Master Side (Stream Data Output M_VALID => m_axis_mm2s_cntrl_tvalid , M_READY => m_axis_mm2s_cntrl_tready , M_Data => m_axis_mm2s_cntrl_tdata , M_STRB => m_axis_mm2s_cntrl_tkeep , M_Last => m_axis_mm2s_cntrl_tlast ); end generate GEN_ASYNC_FIFO; end implementation;	bsd-2-clause	0606f2c65d4cf3ed33f98c63e14ca093	0.441853	4.139261	false	false	false	false
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0/synth/system_ov7670_controller_1_0.vhd	2	4,423	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:ov7670_controller:1.0 -- IP Revision: 9 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_ov7670_controller_1_0 IS PORT ( clk : IN STD_LOGIC; resend : IN STD_LOGIC; config_finished : OUT STD_LOGIC; sioc : OUT STD_LOGIC; siod : INOUT STD_LOGIC; reset : OUT STD_LOGIC; pwdn : OUT STD_LOGIC; xclk : OUT STD_LOGIC ); END system_ov7670_controller_1_0; ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT ov7670_controller IS PORT ( clk : IN STD_LOGIC; resend : IN STD_LOGIC; config_finished : OUT STD_LOGIC; sioc : OUT STD_LOGIC; siod : INOUT STD_LOGIC; reset : OUT STD_LOGIC; pwdn : OUT STD_LOGIC; xclk : OUT STD_LOGIC ); END COMPONENT ov7670_controller; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_1_0_arch : ARCHITECTURE IS "system_ov7670_controller_1_0,ov7670_controller,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "system_ov7670_controller_1_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; BEGIN U0 : ov7670_controller PORT MAP ( clk => clk, resend => resend, config_finished => config_finished, sioc => sioc, siod => siod, reset => reset, pwdn => pwdn, xclk => xclk ); END system_ov7670_controller_1_0_arch;	mit	606ce4eccf38fe8202c08fb43f4ba93a	0.732534	3.914159	false	false	false	false
loa-org/loa-hdl	modules/ir_rx/tb/ir_rx_adcs_tb.vhd	2	2,463	------------------------------------------------------------------------------- -- Title : Testbench for design "ir_rx_adcs" -- Project : ------------------------------------------------------------------------------- -- File : ir_rx_adcs_tb.vhd -- Author : strongly-typed -- Created : 2012-04-27 -- Platform : -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.adc_ltc2351_pkg.all; use work.ir_rx_module_pkg.all; ------------------------------------------------------------------------------- entity ir_rx_adcs_tb is end ir_rx_adcs_tb; ------------------------------------------------------------------------------- architecture tb of ir_rx_adcs_tb is -- component generics constant CHANNELS : positive := 12; -- component ports signal clk_sample_en : std_logic := '0'; signal adc_out_s : ir_rx_module_spi_out_type; signal adc_in_s : ir_rx_module_spi_in_type; signal adc_values_s : adc_ltc2351_values_type(CHANNELS-1 downto 0); signal adc_done_s : std_logic; -- clock signal Clk : std_logic := '1'; begin -- tb -- component instantiation DUT : ir_rx_adcs generic map ( CHANNELS => CHANNELS) port map ( clk_sample_en_i_p => clk_sample_en, adc_o_p => adc_out_s, adc_i_p => adc_in_s, adc_values_o_p => adc_values_s, adc_done_o_p => adc_done_s, clk => clk); -- clock generation clk <= not clk after 10 ns; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here wait until clk = '0'; wait until clk = '0'; wait until clk = '0'; clk_sample_en <= '1'; wait until clk = '0'; clk_sample_en <= '0'; wait for 10 ms; end process WaveGen_Proc; end tb; ------------------------------------------------------------------------------- configuration ir_rx_adcs_tb_tb_cfg of ir_rx_adcs_tb is for tb end for; end ir_rx_adcs_tb_tb_cfg; -------------------------------------------------------------------------------	bsd-3-clause	454544ccdf71a5bc3a09d6c4e384bf4c	0.405197	4.253886	false	false	false	false
loa-org/loa-hdl	modules/motor_control/tb/commutation_tb.vhd	2	2,121	library ieee; use ieee.std_logic_1164.all; entity commutation_tb is end commutation_tb; library work; use work.motor_control_pkg.all; use work.symmetric_pwm_deadtime_pkg.all; use work.commutation_pkg.all; architecture behavior of commutation_tb is signal clk : std_logic := '0'; signal clk_en : std_logic := '1'; signal center : std_logic; signal value : std_logic_vector(7 downto 0) := x"F0"; signal driver_stage : bldc_driver_stage_type; signal pwm : half_bridge_type; signal sd : std_logic := '0'; signal dir : std_logic := '0'; signal hall : hall_sensor_type := ('0', '0', '0'); begin clk <= not clk after 10 NS; -- 50 Mhz clock waveform : process begin wait for 50 US; hall <= ('1', '0', '1'); wait for 100 US; hall <= ('1', '0', '0'); wait for 100 US; hall <= ('1', '1', '0'); wait for 100 US; hall <= ('0', '1', '0'); wait for 100 US; hall <= ('0', '1', '1'); wait for 100 US; hall <= ('0', '0', '1'); wait for 100 US; hall <= ('1', '0', '1'); wait for 100 US; hall <= ('1', '0', '0'); wait for 100 US; hall <= ('1', '1', '0'); wait for 100 US; hall <= ('0', '1', '0'); wait for 100 US; hall <= ('0', '1', '1'); wait for 100 US; hall <= ('0', '0', '1'); end process; waveform2 : process begin wait for 600 US; sd <= '1'; wait for 20 US; sd <= '0'; dir <= '1'; end process; pwm_generator : symmetric_pwm_deadtime generic map ( WIDTH => 8, T_DEAD => 20) port map ( pwm_p => pwm, clk_en_p => clk_en, value_p => value, center_p => center, reset => '0', clk => clk); commutation_1 : commutation port map ( driver_stage_p => driver_stage, hall_p => hall, pwm_p => pwm, dir_p => dir, sd_p => sd, clk => clk); end;	bsd-3-clause	f61b2ac16d400e3f0f75adbcd9716765	0.459689	3.319249	false	false	false	false
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl	1	804,717	-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Thu May 25 15:28:04 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl -- Design : system_zed_hdmi_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_zed_hdmi_0_0_i2c_sender is port ( hdmi_sda : out STD_LOGIC; hdmi_scl : out STD_LOGIC; clk_100 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_zed_hdmi_0_0_i2c_sender : entity is "i2c_sender"; end system_zed_hdmi_0_0_i2c_sender; architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is signal address : STD_LOGIC_VECTOR ( 5 downto 0 ); signal \address[0]_i_1_n_0\ : STD_LOGIC; signal \address[1]_i_1_n_0\ : STD_LOGIC; signal \address[2]_i_1_n_0\ : STD_LOGIC; signal \address[3]_i_1_n_0\ : STD_LOGIC; signal \address[3]_i_2_n_0\ : STD_LOGIC; signal \address[4]_i_1_n_0\ : STD_LOGIC; signal \address[5]_i_1_n_0\ : STD_LOGIC; signal \address[5]_i_2_n_0\ : STD_LOGIC; signal \address[5]_i_3_n_0\ : STD_LOGIC; signal \address[5]_i_4_n_0\ : STD_LOGIC; signal \address[5]_i_5_n_0\ : STD_LOGIC; signal \address[5]_i_6_n_0\ : STD_LOGIC; signal \address[5]_i_7_n_0\ : STD_LOGIC; signal busy_sr : STD_LOGIC; signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC; signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC; signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC; signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 ); signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC; signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 ); signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC; signal \data_sr[0]_i_1_n_0\ : STD_LOGIC; signal \data_sr[0]_i_2_n_0\ : STD_LOGIC; signal \data_sr_reg_n_0_[0]\ : STD_LOGIC; signal \data_sr_reg_n_0_[10]\ : STD_LOGIC; signal \data_sr_reg_n_0_[11]\ : STD_LOGIC; signal \data_sr_reg_n_0_[12]\ : STD_LOGIC; signal \data_sr_reg_n_0_[13]\ : STD_LOGIC; signal \data_sr_reg_n_0_[14]\ : STD_LOGIC; signal \data_sr_reg_n_0_[15]\ : STD_LOGIC; signal \data_sr_reg_n_0_[16]\ : STD_LOGIC; signal \data_sr_reg_n_0_[17]\ : STD_LOGIC; signal \data_sr_reg_n_0_[18]\ : STD_LOGIC; signal \data_sr_reg_n_0_[19]\ : STD_LOGIC; signal \data_sr_reg_n_0_[1]\ : STD_LOGIC; signal \data_sr_reg_n_0_[20]\ : STD_LOGIC; signal \data_sr_reg_n_0_[21]\ : STD_LOGIC; signal \data_sr_reg_n_0_[22]\ : STD_LOGIC; signal \data_sr_reg_n_0_[23]\ : STD_LOGIC; signal \data_sr_reg_n_0_[24]\ : STD_LOGIC; signal \data_sr_reg_n_0_[25]\ : STD_LOGIC; signal \data_sr_reg_n_0_[26]\ : STD_LOGIC; signal \data_sr_reg_n_0_[27]\ : STD_LOGIC; signal \data_sr_reg_n_0_[28]\ : STD_LOGIC; signal \data_sr_reg_n_0_[2]\ : STD_LOGIC; signal \data_sr_reg_n_0_[3]\ : STD_LOGIC; signal \data_sr_reg_n_0_[4]\ : STD_LOGIC; signal \data_sr_reg_n_0_[5]\ : STD_LOGIC; signal \data_sr_reg_n_0_[6]\ : STD_LOGIC; signal \data_sr_reg_n_0_[7]\ : STD_LOGIC; signal \data_sr_reg_n_0_[8]\ : STD_LOGIC; signal \data_sr_reg_n_0_[9]\ : STD_LOGIC; signal divider : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \divider[0]_i_1_n_0\ : STD_LOGIC; signal \divider[1]_i_1_n_0\ : STD_LOGIC; signal \divider[2]_i_1_n_0\ : STD_LOGIC; signal \divider[3]_i_1_n_0\ : STD_LOGIC; signal \divider[4]_i_1_n_0\ : STD_LOGIC; signal \divider[5]_i_1_n_0\ : STD_LOGIC; signal \divider[5]_i_2_n_0\ : STD_LOGIC; signal \divider[6]_i_1_n_0\ : STD_LOGIC; signal \divider[7]_i_1_n_0\ : STD_LOGIC; signal \divider[7]_i_2_n_0\ : STD_LOGIC; signal \divider[7]_i_3_n_0\ : STD_LOGIC; signal finished_i_1_n_0 : STD_LOGIC; signal finished_reg_n_0 : STD_LOGIC; signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC; signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC; signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC; signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal p_1_in : STD_LOGIC; signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 ); signal reg_value_reg_n_10 : STD_LOGIC; signal reg_value_reg_n_11 : STD_LOGIC; signal reg_value_reg_n_12 : STD_LOGIC; signal reg_value_reg_n_13 : STD_LOGIC; signal reg_value_reg_n_14 : STD_LOGIC; signal reg_value_reg_n_15 : STD_LOGIC; signal reg_value_reg_n_8 : STD_LOGIC; signal reg_value_reg_n_9 : STD_LOGIC; signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC; signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC; signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC; signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC; signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC; signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC; signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC; signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC; signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC; signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC; signal tristate_sr_reg_gate_n_0 : STD_LOGIC; signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC; signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC; signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC; signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC; signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC; signal tristate_sr_reg_r_0_n_0 : STD_LOGIC; signal tristate_sr_reg_r_1_n_0 : STD_LOGIC; signal tristate_sr_reg_r_2_n_0 : STD_LOGIC; signal tristate_sr_reg_r_3_n_0 : STD_LOGIC; signal tristate_sr_reg_r_4_n_0 : STD_LOGIC; signal tristate_sr_reg_r_5_n_0 : STD_LOGIC; signal tristate_sr_reg_r_6_n_0 : STD_LOGIC; signal tristate_sr_reg_r_n_0 : STD_LOGIC; signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT"; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell THIS}}"; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of reg_value_reg : label is 1024; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value"; attribute bram_addr_begin : integer; attribute bram_addr_begin of reg_value_reg : label is 0; attribute bram_addr_end : integer; attribute bram_addr_end of reg_value_reg : label is 1023; attribute bram_slice_begin : integer; attribute bram_slice_begin of reg_value_reg : label is 0; attribute bram_slice_end : integer; attribute bram_slice_end of reg_value_reg : label is 15; attribute srl_bus_name : string; attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg "; attribute srl_name : string; attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 "; attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg "; attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 "; attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg "; attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 "; attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16"; begin \address[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => p_0_in, I1 => \address[5]_i_5_n_0\, I2 => \address[5]_i_3_n_0\, I3 => address(0), O => \address[0]_i_1_n_0\ ); \address[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00080800" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => address(0), I4 => address(1), O => \address[1]_i_1_n_0\ ); \address[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0008080808000000" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => address(1), I4 => address(0), I5 => address(2), O => \address[2]_i_1_n_0\ ); \address[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"08000008" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => \address[3]_i_2_n_0\, I4 => address(3), O => \address[3]_i_1_n_0\ ); \address[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => address(1), I1 => address(0), I2 => address(2), O => \address[3]_i_2_n_0\ ); \address[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"08000008" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => \address[5]_i_6_n_0\, I4 => address(4), O => \address[4]_i_1_n_0\ ); \address[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => finished_reg_n_0, I2 => p_1_in, I3 => \address[5]_i_4_n_0\, I4 => divider(7), I5 => p_0_in, O => \address[5]_i_1_n_0\ ); \address[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0808000800000800" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => address(4), I4 => \address[5]_i_6_n_0\, I5 => address(5), O => \address[5]_i_2_n_0\ ); \address[5]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF7FFF" ) port map ( I0 => \p_0_in__0\(2), I1 => \p_0_in__0\(3), I2 => \p_0_in__0\(0), I3 => \p_0_in__0\(1), I4 => \address[5]_i_7_n_0\, O => \address[5]_i_3_n_0\ ); \address[5]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \divider[7]_i_3_n_0\, I1 => divider(6), O => \address[5]_i_4_n_0\ ); \address[5]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"00400000" ) port map ( I0 => finished_reg_n_0, I1 => p_1_in, I2 => divider(6), I3 => \divider[7]_i_3_n_0\, I4 => divider(7), O => \address[5]_i_5_n_0\ ); \address[5]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => address(2), I1 => address(0), I2 => address(1), I3 => address(3), O => \address[5]_i_6_n_0\ ); \address[5]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \p_0_in__0\(5), I1 => \p_0_in__0\(4), I2 => \p_0_in__0\(7), I3 => \p_0_in__0\(6), O => \address[5]_i_7_n_0\ ); \address_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[0]_i_1_n_0\, Q => address(0), R => '0' ); \address_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[1]_i_1_n_0\, Q => address(1), R => '0' ); \address_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[2]_i_1_n_0\, Q => address(2), R => '0' ); \address_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[3]_i_1_n_0\, Q => address(3), R => '0' ); \address_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[4]_i_1_n_0\, Q => address(4), R => '0' ); \address_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[5]_i_2_n_0\, Q => address(5), R => '0' ); \busy_sr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FF200000" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => finished_reg_n_0, I2 => p_1_in, I3 => p_0_in, I4 => divider(7), I5 => \address[5]_i_4_n_0\, O => busy_sr ); \busy_sr[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[9]\, O => \busy_sr[10]_i_1_n_0\ ); \busy_sr[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[10]\, O => \busy_sr[11]_i_1_n_0\ ); \busy_sr[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[11]\, O => \busy_sr[12]_i_1_n_0\ ); \busy_sr[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[12]\, O => \busy_sr[13]_i_1_n_0\ ); \busy_sr[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[13]\, O => \busy_sr[14]_i_1_n_0\ ); \busy_sr[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[14]\, O => \busy_sr[15]_i_1_n_0\ ); \busy_sr[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[15]\, O => \busy_sr[16]_i_1_n_0\ ); \busy_sr[17]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[16]\, O => \busy_sr[17]_i_1_n_0\ ); \busy_sr[18]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[17]\, O => \busy_sr[18]_i_1_n_0\ ); \busy_sr[19]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[18]\, O => \busy_sr[19]_i_1_n_0\ ); \busy_sr[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[0]\, O => \busy_sr[1]_i_1_n_0\ ); \busy_sr[20]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[19]\, O => \busy_sr[20]_i_1_n_0\ ); \busy_sr[21]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[20]\, O => \busy_sr[21]_i_1_n_0\ ); \busy_sr[22]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[21]\, O => \busy_sr[22]_i_1_n_0\ ); \busy_sr[23]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[22]\, O => \busy_sr[23]_i_1_n_0\ ); \busy_sr[24]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[23]\, O => \busy_sr[24]_i_1_n_0\ ); \busy_sr[25]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[24]\, O => \busy_sr[25]_i_1_n_0\ ); \busy_sr[26]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[25]\, O => \busy_sr[26]_i_1_n_0\ ); \busy_sr[27]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[26]\, O => \busy_sr[27]_i_1_n_0\ ); \busy_sr[28]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000040000000000" ) port map ( I0 => \address[5]_i_4_n_0\, I1 => divider(7), I2 => p_0_in, I3 => p_1_in, I4 => finished_reg_n_0, I5 => \address[5]_i_3_n_0\, O => \busy_sr[28]_i_1_n_0\ ); \busy_sr[28]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[27]\, O => \busy_sr[28]_i_2_n_0\ ); \busy_sr[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[1]\, O => \busy_sr[2]_i_1_n_0\ ); \busy_sr[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[2]\, O => \busy_sr[3]_i_1_n_0\ ); \busy_sr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[3]\, O => \busy_sr[4]_i_1_n_0\ ); \busy_sr[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[4]\, O => \busy_sr[5]_i_1_n_0\ ); \busy_sr[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[5]\, O => \busy_sr[6]_i_1_n_0\ ); \busy_sr[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[6]\, O => \busy_sr[7]_i_1_n_0\ ); \busy_sr[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[7]\, O => \busy_sr[8]_i_1_n_0\ ); \busy_sr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[8]\, O => \busy_sr[9]_i_1_n_0\ ); \busy_sr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \address[5]_i_1_n_0\, Q => \busy_sr_reg_n_0_[0]\, R => '0' ); \busy_sr_reg[10]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[10]_i_1_n_0\, Q => \busy_sr_reg_n_0_[10]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[11]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[11]_i_1_n_0\, Q => \busy_sr_reg_n_0_[11]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[12]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[12]_i_1_n_0\, Q => \busy_sr_reg_n_0_[12]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[13]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[13]_i_1_n_0\, Q => \busy_sr_reg_n_0_[13]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[14]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[14]_i_1_n_0\, Q => \busy_sr_reg_n_0_[14]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[15]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[15]_i_1_n_0\, Q => \busy_sr_reg_n_0_[15]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[16]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[16]_i_1_n_0\, Q => \busy_sr_reg_n_0_[16]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[17]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[17]_i_1_n_0\, Q => \busy_sr_reg_n_0_[17]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[18]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[18]_i_1_n_0\, Q => \busy_sr_reg_n_0_[18]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[19]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[19]_i_1_n_0\, Q => \busy_sr_reg_n_0_[19]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[1]_i_1_n_0\, Q => \busy_sr_reg_n_0_[1]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[20]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[20]_i_1_n_0\, Q => \busy_sr_reg_n_0_[20]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[21]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[21]_i_1_n_0\, Q => \busy_sr_reg_n_0_[21]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[22]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[22]_i_1_n_0\, Q => \busy_sr_reg_n_0_[22]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[23]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[23]_i_1_n_0\, Q => \busy_sr_reg_n_0_[23]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[24]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[24]_i_1_n_0\, Q => \busy_sr_reg_n_0_[24]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[25]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[25]_i_1_n_0\, Q => \busy_sr_reg_n_0_[25]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[26]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[26]_i_1_n_0\, Q => \busy_sr_reg_n_0_[26]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[27]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[27]_i_1_n_0\, Q => \busy_sr_reg_n_0_[27]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[28]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[28]_i_2_n_0\, Q => p_0_in, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[2]_i_1_n_0\, Q => \busy_sr_reg_n_0_[2]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[3]_i_1_n_0\, Q => \busy_sr_reg_n_0_[3]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[4]_i_1_n_0\, Q => \busy_sr_reg_n_0_[4]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[5]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[5]_i_1_n_0\, Q => \busy_sr_reg_n_0_[5]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[6]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[6]_i_1_n_0\, Q => \busy_sr_reg_n_0_[6]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[7]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[7]_i_1_n_0\, Q => \busy_sr_reg_n_0_[7]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[8]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[8]_i_1_n_0\, Q => \busy_sr_reg_n_0_[8]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[9]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[9]_i_1_n_0\, Q => \busy_sr_reg_n_0_[9]\, S => \busy_sr[28]_i_1_n_0\ ); \clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => clk_last_quarter(28), O => \clk_first_quarter[28]_i_1_n_0\ ); \clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \clk_first_quarter[28]_i_1_n_0\, Q => clk_first_quarter(28), S => \busy_sr[28]_i_1_n_0\ ); \clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => p_1_in, I1 => finished_reg_n_0, I2 => \address[5]_i_3_n_0\, I3 => p_0_in, I4 => divider(7), I5 => \address[5]_i_4_n_0\, O => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(9), Q => clk_last_quarter(10), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(10), Q => clk_last_quarter(11), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(11), Q => clk_last_quarter(12), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(12), Q => clk_last_quarter(13), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(13), Q => clk_last_quarter(14), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(14), Q => clk_last_quarter(15), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(15), Q => clk_last_quarter(16), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(16), Q => clk_last_quarter(17), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(17), Q => clk_last_quarter(18), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(18), Q => clk_last_quarter(19), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \tristate_sr[19]_i_1_n_0\, Q => clk_last_quarter(1), R => '0' ); \clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(19), Q => clk_last_quarter(20), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(20), Q => clk_last_quarter(21), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(21), Q => clk_last_quarter(22), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(22), Q => clk_last_quarter(23), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(23), Q => clk_last_quarter(24), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(24), Q => clk_last_quarter(25), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(25), Q => clk_last_quarter(26), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(26), Q => clk_last_quarter(27), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(27), Q => clk_last_quarter(28), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(1), Q => clk_last_quarter(2), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(2), Q => clk_last_quarter(3), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(3), Q => clk_last_quarter(4), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(4), Q => clk_last_quarter(5), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(5), Q => clk_last_quarter(6), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(6), Q => clk_last_quarter(7), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(7), Q => clk_last_quarter(8), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(8), Q => clk_last_quarter(9), R => \clk_last_quarter[2]_i_1_n_0\ ); \data_sr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EAEACAEAEAEAEAEA" ) port map ( I0 => \data_sr_reg_n_0_[0]\, I1 => p_0_in, I2 => \data_sr[0]_i_2_n_0\, I3 => p_1_in, I4 => finished_reg_n_0, I5 => \address[5]_i_3_n_0\, O => \data_sr[0]_i_1_n_0\ ); \data_sr[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"20" ) port map ( I0 => divider(7), I1 => \divider[7]_i_3_n_0\, I2 => divider(6), O => \data_sr[0]_i_2_n_0\ ); \data_sr[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[10]\, I1 => p_0_in, I2 => \p_0_in__0\(0), O => p_2_in(11) ); \data_sr[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[11]\, I1 => p_0_in, I2 => \p_0_in__0\(1), O => p_2_in(12) ); \data_sr[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[12]\, I1 => p_0_in, I2 => \p_0_in__0\(2), O => p_2_in(13) ); \data_sr[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[13]\, I1 => p_0_in, I2 => \p_0_in__0\(3), O => p_2_in(14) ); \data_sr[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[14]\, I1 => p_0_in, I2 => \p_0_in__0\(4), O => p_2_in(15) ); \data_sr[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[15]\, I1 => p_0_in, I2 => \p_0_in__0\(5), O => p_2_in(16) ); \data_sr[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[16]\, I1 => p_0_in, I2 => \p_0_in__0\(6), O => p_2_in(17) ); \data_sr[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[17]\, I1 => p_0_in, I2 => \p_0_in__0\(7), O => p_2_in(18) ); \data_sr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[1]\, I1 => p_0_in, I2 => reg_value_reg_n_15, O => p_2_in(2) ); \data_sr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[2]\, I1 => p_0_in, I2 => reg_value_reg_n_14, O => p_2_in(3) ); \data_sr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[3]\, I1 => p_0_in, I2 => reg_value_reg_n_13, O => p_2_in(4) ); \data_sr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[4]\, I1 => p_0_in, I2 => reg_value_reg_n_12, O => p_2_in(5) ); \data_sr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[5]\, I1 => p_0_in, I2 => reg_value_reg_n_11, O => p_2_in(6) ); \data_sr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[6]\, I1 => p_0_in, I2 => reg_value_reg_n_10, O => p_2_in(7) ); \data_sr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[7]\, I1 => p_0_in, I2 => reg_value_reg_n_9, O => p_2_in(8) ); \data_sr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[8]\, I1 => p_0_in, I2 => reg_value_reg_n_8, O => p_2_in(9) ); \data_sr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => '1', D => \data_sr[0]_i_1_n_0\, Q => \data_sr_reg_n_0_[0]\, R => '0' ); \data_sr_reg[10]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[9]\, Q => \data_sr_reg_n_0_[10]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(11), Q => \data_sr_reg_n_0_[11]\, R => '0' ); \data_sr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(12), Q => \data_sr_reg_n_0_[12]\, R => '0' ); \data_sr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(13), Q => \data_sr_reg_n_0_[13]\, R => '0' ); \data_sr_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(14), Q => \data_sr_reg_n_0_[14]\, R => '0' ); \data_sr_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(15), Q => \data_sr_reg_n_0_[15]\, R => '0' ); \data_sr_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(16), Q => \data_sr_reg_n_0_[16]\, R => '0' ); \data_sr_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(17), Q => \data_sr_reg_n_0_[17]\, R => '0' ); \data_sr_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(18), Q => \data_sr_reg_n_0_[18]\, R => '0' ); \data_sr_reg[19]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[18]\, Q => \data_sr_reg_n_0_[19]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[0]\, Q => \data_sr_reg_n_0_[1]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[19]\, Q => \data_sr_reg_n_0_[20]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[21]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[20]\, Q => \data_sr_reg_n_0_[21]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[21]\, Q => \data_sr_reg_n_0_[22]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[22]\, Q => \data_sr_reg_n_0_[23]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[24]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[23]\, Q => \data_sr_reg_n_0_[24]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[25]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[24]\, Q => \data_sr_reg_n_0_[25]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[26]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[25]\, Q => \data_sr_reg_n_0_[26]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[26]\, Q => \data_sr_reg_n_0_[27]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[27]\, Q => \data_sr_reg_n_0_[28]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(2), Q => \data_sr_reg_n_0_[2]\, R => '0' ); \data_sr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(3), Q => \data_sr_reg_n_0_[3]\, R => '0' ); \data_sr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(4), Q => \data_sr_reg_n_0_[4]\, R => '0' ); \data_sr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(5), Q => \data_sr_reg_n_0_[5]\, R => '0' ); \data_sr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(6), Q => \data_sr_reg_n_0_[6]\, R => '0' ); \data_sr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(7), Q => \data_sr_reg_n_0_[7]\, R => '0' ); \data_sr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(8), Q => \data_sr_reg_n_0_[8]\, R => '0' ); \data_sr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(9), Q => \data_sr_reg_n_0_[9]\, R => '0' ); \divider[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00AE" ) port map ( I0 => p_0_in, I1 => p_1_in, I2 => finished_reg_n_0, I3 => divider(0), O => \divider[0]_i_1_n_0\ ); \divider[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00F4F400" ) port map ( I0 => finished_reg_n_0, I1 => p_1_in, I2 => p_0_in, I3 => divider(0), I4 => divider(1), O => \divider[1]_i_1_n_0\ ); \divider[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00F4F4F4F4000000" ) port map ( I0 => finished_reg_n_0, I1 => p_1_in, I2 => p_0_in, I3 => divider(1), I4 => divider(0), I5 => divider(2), O => \divider[2]_i_1_n_0\ ); \divider[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2AAA8000" ) port map ( I0 => \divider[7]_i_1_n_0\, I1 => divider(2), I2 => divider(0), I3 => divider(1), I4 => divider(3), O => \divider[3]_i_1_n_0\ ); \divider[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFF000080000000" ) port map ( I0 => divider(2), I1 => divider(0), I2 => divider(1), I3 => divider(3), I4 => \divider[7]_i_1_n_0\, I5 => divider(4), O => \divider[4]_i_1_n_0\ ); \divider[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"88A84454" ) port map ( I0 => \divider[5]_i_2_n_0\, I1 => p_0_in, I2 => p_1_in, I3 => finished_reg_n_0, I4 => divider(5), O => \divider[5]_i_1_n_0\ ); \divider[5]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => divider(3), I1 => divider(1), I2 => divider(0), I3 => divider(2), I4 => divider(4), O => \divider[5]_i_2_n_0\ ); \divider[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"88A84454" ) port map ( I0 => \divider[7]_i_3_n_0\, I1 => p_0_in, I2 => p_1_in, I3 => finished_reg_n_0, I4 => divider(6), O => \divider[6]_i_1_n_0\ ); \divider[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"F4" ) port map ( I0 => finished_reg_n_0, I1 => p_1_in, I2 => p_0_in, O => \divider[7]_i_1_n_0\ ); \divider[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"B0B0BBB040404440" ) port map ( I0 => \divider[7]_i_3_n_0\, I1 => divider(6), I2 => p_0_in, I3 => p_1_in, I4 => finished_reg_n_0, I5 => divider(7), O => \divider[7]_i_2_n_0\ ); \divider[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => divider(4), I1 => divider(2), I2 => divider(0), I3 => divider(1), I4 => divider(3), I5 => divider(5), O => \divider[7]_i_3_n_0\ ); \divider_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[0]_i_1_n_0\, Q => divider(0), R => '0' ); \divider_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[1]_i_1_n_0\, Q => divider(1), R => '0' ); \divider_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[2]_i_1_n_0\, Q => divider(2), R => '0' ); \divider_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[3]_i_1_n_0\, Q => divider(3), R => '0' ); \divider_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[4]_i_1_n_0\, Q => divider(4), R => '0' ); \divider_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[5]_i_1_n_0\, Q => divider(5), R => '0' ); \divider_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[6]_i_1_n_0\, Q => divider(6), R => '0' ); \divider_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[7]_i_2_n_0\, Q => divider(7), R => '0' ); finished_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00000020" ) port map ( I0 => p_1_in, I1 => \address[5]_i_4_n_0\, I2 => divider(7), I3 => \address[5]_i_3_n_0\, I4 => p_0_in, I5 => finished_reg_n_0, O => finished_i_1_n_0 ); finished_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => '1', D => finished_i_1_n_0, Q => finished_reg_n_0, R => '0' ); hdmi_scl_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => clk_first_quarter(28), I1 => divider(7), O => hdmi_scl ); hdmi_sda_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \data_sr_reg_n_0_[28]\, I1 => \tristate_sr_reg[28]_inv_n_0\, O => hdmi_sda ); \initial_pause[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => p_1_in, I1 => p_0_in, I2 => \initial_pause_reg_n_0_[0]\, O => \p_1_in__0\(0) ); \initial_pause[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0110" ) port map ( I0 => p_0_in, I1 => p_1_in, I2 => \initial_pause_reg_n_0_[0]\, I3 => \initial_pause_reg_n_0_[1]\, O => \p_1_in__0\(1) ); \initial_pause[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00070008" ) port map ( I0 => \initial_pause_reg_n_0_[0]\, I1 => \initial_pause_reg_n_0_[1]\, I2 => p_1_in, I3 => p_0_in, I4 => \initial_pause_reg_n_0_[2]\, O => \p_1_in__0\(2) ); \initial_pause[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000007F00000080" ) port map ( I0 => \initial_pause_reg_n_0_[1]\, I1 => \initial_pause_reg_n_0_[0]\, I2 => \initial_pause_reg_n_0_[2]\, I3 => p_1_in, I4 => p_0_in, I5 => \initial_pause_reg_n_0_[3]\, O => \p_1_in__0\(3) ); \initial_pause[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFF000080000000" ) port map ( I0 => \initial_pause_reg_n_0_[2]\, I1 => \initial_pause_reg_n_0_[0]\, I2 => \initial_pause_reg_n_0_[1]\, I3 => \initial_pause_reg_n_0_[3]\, I4 => \initial_pause[7]_i_1_n_0\, I5 => \initial_pause_reg_n_0_[4]\, O => \p_1_in__0\(4) ); \initial_pause[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0201" ) port map ( I0 => \initial_pause[5]_i_2_n_0\, I1 => p_1_in, I2 => p_0_in, I3 => \initial_pause_reg_n_0_[5]\, O => \p_1_in__0\(5) ); \initial_pause[5]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => \initial_pause_reg_n_0_[3]\, I1 => \initial_pause_reg_n_0_[1]\, I2 => \initial_pause_reg_n_0_[0]\, I3 => \initial_pause_reg_n_0_[2]\, I4 => \initial_pause_reg_n_0_[4]\, O => \initial_pause[5]_i_2_n_0\ ); \initial_pause[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0201" ) port map ( I0 => \initial_pause[7]_i_3_n_0\, I1 => p_1_in, I2 => p_0_in, I3 => \initial_pause_reg_n_0_[6]\, O => \p_1_in__0\(6) ); \initial_pause[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => p_0_in, I1 => p_1_in, O => \initial_pause[7]_i_1_n_0\ ); \initial_pause[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \initial_pause_reg_n_0_[6]\, I1 => p_0_in, I2 => p_1_in, I3 => \initial_pause[7]_i_3_n_0\, O => \p_1_in__0\(7) ); \initial_pause[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \initial_pause_reg_n_0_[4]\, I1 => \initial_pause_reg_n_0_[2]\, I2 => \initial_pause_reg_n_0_[0]\, I3 => \initial_pause_reg_n_0_[1]\, I4 => \initial_pause_reg_n_0_[3]\, I5 => \initial_pause_reg_n_0_[5]\, O => \initial_pause[7]_i_3_n_0\ ); \initial_pause_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(0), Q => \initial_pause_reg_n_0_[0]\, R => '0' ); \initial_pause_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(1), Q => \initial_pause_reg_n_0_[1]\, R => '0' ); \initial_pause_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(2), Q => \initial_pause_reg_n_0_[2]\, R => '0' ); \initial_pause_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(3), Q => \initial_pause_reg_n_0_[3]\, R => '0' ); \initial_pause_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(4), Q => \initial_pause_reg_n_0_[4]\, R => '0' ); \initial_pause_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(5), Q => \initial_pause_reg_n_0_[5]\, R => '0' ); \initial_pause_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(6), Q => \initial_pause_reg_n_0_[6]\, R => '0' ); \initial_pause_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(7), Q => p_1_in, R => '0' ); reg_value_reg: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110", INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04", INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601", INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 18, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(13 downto 10) => B"0000", ADDRARDADDR(9 downto 4) => address(5 downto 0), ADDRARDADDR(3 downto 0) => B"0000", ADDRBWRADDR(13 downto 0) => B"11111111111111", CLKARDCLK => clk_100, CLKBWRCLK => '0', DIADI(15 downto 0) => B"1111111111111111", DIBDI(15 downto 0) => B"1111111111111111", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"11", DOADO(15 downto 8) => \p_0_in__0\(7 downto 0), DOADO(7) => reg_value_reg_n_8, DOADO(6) => reg_value_reg_n_9, DOADO(5) => reg_value_reg_n_10, DOADO(4) => reg_value_reg_n_11, DOADO(3) => reg_value_reg_n_12, DOADO(2) => reg_value_reg_n_13, DOADO(1) => reg_value_reg_n_14, DOADO(0) => reg_value_reg_n_15, DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0), DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0), DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0), ENARDEN => '1', ENBWREN => '0', REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1 downto 0) => B"00", WEBWE(3 downto 0) => B"0000" ); \tristate_sr[19]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, O => \tristate_sr[19]_i_1_n_0\ ); \tristate_sr_reg[10]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg_n_0_[9]\, Q => \tristate_sr_reg_n_0_[10]\, S => \address[5]_i_1_n_0\ ); \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '1', A1 => '0', A2 => '1', A3 => '0', CE => \tristate_sr[19]_i_1_n_0\, CLK => clk_100, D => \tristate_sr_reg_n_0_[10]\, Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ ); \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\, Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, R => '0' ); \tristate_sr_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg_gate__0_n_0\, Q => \tristate_sr_reg_n_0_[18]\, R => \address[5]_i_1_n_0\ ); \tristate_sr_reg[19]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg_n_0_[18]\, Q => \tristate_sr_reg_n_0_[19]\, S => \address[5]_i_1_n_0\ ); \tristate_sr_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => '0', Q => \tristate_sr_reg_n_0_[1]\, S => \address[5]_i_1_n_0\ ); \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '1', A3 => '0', CE => \tristate_sr[19]_i_1_n_0\, CLK => clk_100, D => \tristate_sr_reg_n_0_[19]\, Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ ); \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\, R => '0' ); \tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_gate_n_0, Q => \tristate_sr_reg[28]_inv_n_0\, S => \address[5]_i_1_n_0\ ); \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '1', A1 => '0', A2 => '1', A3 => '0', CE => \tristate_sr[19]_i_1_n_0\, CLK => clk_100, D => \tristate_sr_reg_n_0_[1]\, Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ ); \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\, Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, R => '0' ); \tristate_sr_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg_gate__1_n_0\, Q => \tristate_sr_reg_n_0_[9]\, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_gate: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\, I1 => tristate_sr_reg_r_6_n_0, O => tristate_sr_reg_gate_n_0 ); \tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, I1 => tristate_sr_reg_r_5_n_0, O => \tristate_sr_reg_gate__0_n_0\ ); \tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, I1 => tristate_sr_reg_r_5_n_0, O => \tristate_sr_reg_gate__1_n_0\ ); tristate_sr_reg_r: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => '1', Q => tristate_sr_reg_r_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_0: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_n_0, Q => tristate_sr_reg_r_0_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_1: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_0_n_0, Q => tristate_sr_reg_r_1_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_2: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_1_n_0, Q => tristate_sr_reg_r_2_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_3: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_2_n_0, Q => tristate_sr_reg_r_3_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_4: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_3_n_0, Q => tristate_sr_reg_r_4_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_5: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_4_n_0, Q => tristate_sr_reg_r_5_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_6: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_5_n_0, Q => tristate_sr_reg_r_6_n_0, R => \address[5]_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_zed_hdmi_0_0_zed_hdmi is port ( hdmi_clk : out STD_LOGIC; hdmi_hsync : out STD_LOGIC; hdmi_vsync : out STD_LOGIC; hdmi_de : out STD_LOGIC; DI : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[31]_0\ : out STD_LOGIC; \cr_int_reg[31]_1\ : out STD_LOGIC; O : out STD_LOGIC_VECTOR ( 1 downto 0 ); \cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[27]_0\ : out STD_LOGIC; \cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); CO : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); hdmi_sda : out STD_LOGIC; hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 ); hdmi_scl : out STD_LOGIC; clk_x2 : in STD_LOGIC; active : in STD_LOGIC; clk_100 : in STD_LOGIC; rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 ); \rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 ); \rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); hsync : in STD_LOGIC; vsync : in STD_LOGIC; clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_zed_hdmi_0_0_zed_hdmi : entity is "zed_hdmi"; end system_zed_hdmi_0_0_zed_hdmi; architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal D1 : STD_LOGIC; signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal cb : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \cb[0]_i_1_n_0\ : STD_LOGIC; signal \cb[1]_i_1_n_0\ : STD_LOGIC; signal \cb[2]_i_1_n_0\ : STD_LOGIC; signal \cb[3]_i_1_n_0\ : STD_LOGIC; signal \cb[4]_i_1_n_0\ : STD_LOGIC; signal \cb[5]_i_1_n_0\ : STD_LOGIC; signal \cb[6]_i_1_n_0\ : STD_LOGIC; signal \cb[7]_i_10_n_0\ : STD_LOGIC; signal \cb[7]_i_11_n_0\ : STD_LOGIC; signal \cb[7]_i_13_n_0\ : STD_LOGIC; signal \cb[7]_i_14_n_0\ : STD_LOGIC; signal \cb[7]_i_15_n_0\ : STD_LOGIC; signal \cb[7]_i_16_n_0\ : STD_LOGIC; signal \cb[7]_i_17_n_0\ : STD_LOGIC; signal \cb[7]_i_18_n_0\ : STD_LOGIC; signal \cb[7]_i_19_n_0\ : STD_LOGIC; signal \cb[7]_i_20_n_0\ : STD_LOGIC; signal \cb[7]_i_21_n_0\ : STD_LOGIC; signal \cb[7]_i_22_n_0\ : STD_LOGIC; signal \cb[7]_i_23_n_0\ : STD_LOGIC; signal \cb[7]_i_24_n_0\ : STD_LOGIC; signal \cb[7]_i_25_n_0\ : STD_LOGIC; signal \cb[7]_i_26_n_0\ : STD_LOGIC; signal \cb[7]_i_27_n_0\ : STD_LOGIC; signal \cb[7]_i_28_n_0\ : STD_LOGIC; signal \cb[7]_i_2_n_0\ : STD_LOGIC; signal \cb[7]_i_4_n_0\ : STD_LOGIC; signal \cb[7]_i_5_n_0\ : STD_LOGIC; signal \cb[7]_i_6_n_0\ : STD_LOGIC; signal \cb[7]_i_7_n_0\ : STD_LOGIC; signal \cb[7]_i_8_n_0\ : STD_LOGIC; signal \cb[7]_i_9_n_0\ : STD_LOGIC; signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC; signal \cb_int[11]_i_100_n_0\ : STD_LOGIC; signal \cb_int[11]_i_101_n_0\ : STD_LOGIC; signal \cb_int[11]_i_102_n_0\ : STD_LOGIC; signal \cb_int[11]_i_103_n_0\ : STD_LOGIC; signal \cb_int[11]_i_104_n_0\ : STD_LOGIC; signal \cb_int[11]_i_105_n_0\ : STD_LOGIC; signal \cb_int[11]_i_106_n_0\ : STD_LOGIC; signal \cb_int[11]_i_107_n_0\ : STD_LOGIC; signal \cb_int[11]_i_108_n_0\ : STD_LOGIC; signal \cb_int[11]_i_109_n_0\ : STD_LOGIC; signal \cb_int[11]_i_10_n_0\ : STD_LOGIC; signal \cb_int[11]_i_110_n_0\ : STD_LOGIC; signal \cb_int[11]_i_111_n_0\ : STD_LOGIC; signal \cb_int[11]_i_112_n_0\ : STD_LOGIC; signal \cb_int[11]_i_113_n_0\ : STD_LOGIC; signal \cb_int[11]_i_114_n_0\ : STD_LOGIC; signal \cb_int[11]_i_11_n_0\ : STD_LOGIC; signal \cb_int[11]_i_12_n_0\ : STD_LOGIC; signal \cb_int[11]_i_13_n_0\ : STD_LOGIC; signal \cb_int[11]_i_14_n_0\ : STD_LOGIC; signal \cb_int[11]_i_15_n_0\ : STD_LOGIC; signal \cb_int[11]_i_19_n_0\ : STD_LOGIC; signal \cb_int[11]_i_20_n_0\ : STD_LOGIC; signal \cb_int[11]_i_22_n_0\ : STD_LOGIC; signal \cb_int[11]_i_27_n_0\ : STD_LOGIC; signal \cb_int[11]_i_29_n_0\ : STD_LOGIC; signal \cb_int[11]_i_2_n_0\ : STD_LOGIC; signal \cb_int[11]_i_30_n_0\ : STD_LOGIC; signal \cb_int[11]_i_31_n_0\ : STD_LOGIC; signal \cb_int[11]_i_32_n_0\ : STD_LOGIC; signal \cb_int[11]_i_34_n_0\ : STD_LOGIC; signal \cb_int[11]_i_35_n_0\ : STD_LOGIC; signal \cb_int[11]_i_36_n_0\ : STD_LOGIC; signal \cb_int[11]_i_37_n_0\ : STD_LOGIC; signal \cb_int[11]_i_39_n_0\ : STD_LOGIC; signal \cb_int[11]_i_3_n_0\ : STD_LOGIC; signal \cb_int[11]_i_40_n_0\ : STD_LOGIC; signal \cb_int[11]_i_41_n_0\ : STD_LOGIC; signal \cb_int[11]_i_42_n_0\ : STD_LOGIC; signal \cb_int[11]_i_43_n_0\ : STD_LOGIC; signal \cb_int[11]_i_44_n_0\ : STD_LOGIC; signal \cb_int[11]_i_45_n_0\ : STD_LOGIC; signal \cb_int[11]_i_46_n_0\ : STD_LOGIC; signal \cb_int[11]_i_47_n_0\ : STD_LOGIC; signal \cb_int[11]_i_49_n_0\ : STD_LOGIC; signal \cb_int[11]_i_4_n_0\ : STD_LOGIC; signal \cb_int[11]_i_50_n_0\ : STD_LOGIC; signal \cb_int[11]_i_51_n_0\ : STD_LOGIC; signal \cb_int[11]_i_52_n_0\ : STD_LOGIC; signal \cb_int[11]_i_53_n_0\ : STD_LOGIC; signal \cb_int[11]_i_54_n_0\ : STD_LOGIC; signal \cb_int[11]_i_55_n_0\ : STD_LOGIC; signal \cb_int[11]_i_56_n_0\ : STD_LOGIC; signal \cb_int[11]_i_57_n_0\ : STD_LOGIC; signal \cb_int[11]_i_58_n_0\ : STD_LOGIC; signal \cb_int[11]_i_59_n_0\ : STD_LOGIC; signal \cb_int[11]_i_5_n_0\ : STD_LOGIC; signal \cb_int[11]_i_60_n_0\ : STD_LOGIC; signal \cb_int[11]_i_61_n_0\ : STD_LOGIC; signal \cb_int[11]_i_62_n_0\ : STD_LOGIC; signal \cb_int[11]_i_63_n_0\ : STD_LOGIC; signal \cb_int[11]_i_64_n_0\ : STD_LOGIC; signal \cb_int[11]_i_65_n_0\ : STD_LOGIC; signal \cb_int[11]_i_67_n_0\ : STD_LOGIC; signal \cb_int[11]_i_68_n_0\ : STD_LOGIC; signal \cb_int[11]_i_69_n_0\ : STD_LOGIC; signal \cb_int[11]_i_6_n_0\ : STD_LOGIC; signal \cb_int[11]_i_70_n_0\ : STD_LOGIC; signal \cb_int[11]_i_71_n_0\ : STD_LOGIC; signal \cb_int[11]_i_72_n_0\ : STD_LOGIC; signal \cb_int[11]_i_73_n_0\ : STD_LOGIC; signal \cb_int[11]_i_74_n_0\ : STD_LOGIC; signal \cb_int[11]_i_76_n_0\ : STD_LOGIC; signal \cb_int[11]_i_77_n_0\ : STD_LOGIC; signal \cb_int[11]_i_78_n_0\ : STD_LOGIC; signal \cb_int[11]_i_79_n_0\ : STD_LOGIC; signal \cb_int[11]_i_7_n_0\ : STD_LOGIC; signal \cb_int[11]_i_80_n_0\ : STD_LOGIC; signal \cb_int[11]_i_82_n_0\ : STD_LOGIC; signal \cb_int[11]_i_83_n_0\ : STD_LOGIC; signal \cb_int[11]_i_84_n_0\ : STD_LOGIC; signal \cb_int[11]_i_85_n_0\ : STD_LOGIC; signal \cb_int[11]_i_86_n_0\ : STD_LOGIC; signal \cb_int[11]_i_87_n_0\ : STD_LOGIC; signal \cb_int[11]_i_88_n_0\ : STD_LOGIC; signal \cb_int[11]_i_89_n_0\ : STD_LOGIC; signal \cb_int[11]_i_8_n_0\ : STD_LOGIC; signal \cb_int[11]_i_91_n_0\ : STD_LOGIC; signal \cb_int[11]_i_92_n_0\ : STD_LOGIC; signal \cb_int[11]_i_93_n_0\ : STD_LOGIC; signal \cb_int[11]_i_94_n_0\ : STD_LOGIC; signal \cb_int[11]_i_95_n_0\ : STD_LOGIC; signal \cb_int[11]_i_96_n_0\ : STD_LOGIC; signal \cb_int[11]_i_97_n_0\ : STD_LOGIC; signal \cb_int[11]_i_98_n_0\ : STD_LOGIC; signal \cb_int[11]_i_99_n_0\ : STD_LOGIC; signal \cb_int[11]_i_9_n_0\ : STD_LOGIC; signal \cb_int[15]_i_10_n_0\ : STD_LOGIC; signal \cb_int[15]_i_11_n_0\ : STD_LOGIC; signal \cb_int[15]_i_12_n_0\ : STD_LOGIC; signal \cb_int[15]_i_13_n_0\ : STD_LOGIC; signal \cb_int[15]_i_14_n_0\ : STD_LOGIC; signal \cb_int[15]_i_15_n_0\ : STD_LOGIC; signal \cb_int[15]_i_16_n_0\ : STD_LOGIC; signal \cb_int[15]_i_17_n_0\ : STD_LOGIC; signal \cb_int[15]_i_18_n_0\ : STD_LOGIC; signal \cb_int[15]_i_21_n_0\ : STD_LOGIC; signal \cb_int[15]_i_23_n_0\ : STD_LOGIC; signal \cb_int[15]_i_25_n_0\ : STD_LOGIC; signal \cb_int[15]_i_27_n_0\ : STD_LOGIC; signal \cb_int[15]_i_28_n_0\ : STD_LOGIC; signal \cb_int[15]_i_29_n_0\ : STD_LOGIC; signal \cb_int[15]_i_2_n_0\ : STD_LOGIC; signal \cb_int[15]_i_30_n_0\ : STD_LOGIC; signal \cb_int[15]_i_3_n_0\ : STD_LOGIC; signal \cb_int[15]_i_43_n_0\ : STD_LOGIC; signal \cb_int[15]_i_44_n_0\ : STD_LOGIC; signal \cb_int[15]_i_45_n_0\ : STD_LOGIC; signal \cb_int[15]_i_46_n_0\ : STD_LOGIC; signal \cb_int[15]_i_4_n_0\ : STD_LOGIC; signal \cb_int[15]_i_5_n_0\ : STD_LOGIC; signal \cb_int[15]_i_6_n_0\ : STD_LOGIC; signal \cb_int[15]_i_7_n_0\ : STD_LOGIC; signal \cb_int[15]_i_8_n_0\ : STD_LOGIC; signal \cb_int[15]_i_9_n_0\ : STD_LOGIC; signal \cb_int[19]_i_10_n_0\ : STD_LOGIC; signal \cb_int[19]_i_11_n_0\ : STD_LOGIC; signal \cb_int[19]_i_12_n_0\ : STD_LOGIC; signal \cb_int[19]_i_13_n_0\ : STD_LOGIC; signal \cb_int[19]_i_14_n_0\ : STD_LOGIC; signal \cb_int[19]_i_15_n_0\ : STD_LOGIC; signal \cb_int[19]_i_16_n_0\ : STD_LOGIC; signal \cb_int[19]_i_17_n_0\ : STD_LOGIC; signal \cb_int[19]_i_18_n_0\ : STD_LOGIC; signal \cb_int[19]_i_21_n_0\ : STD_LOGIC; signal \cb_int[19]_i_23_n_0\ : STD_LOGIC; signal \cb_int[19]_i_26_n_0\ : STD_LOGIC; signal \cb_int[19]_i_28_n_0\ : STD_LOGIC; signal \cb_int[19]_i_29_n_0\ : STD_LOGIC; signal \cb_int[19]_i_2_n_0\ : STD_LOGIC; signal \cb_int[19]_i_30_n_0\ : STD_LOGIC; signal \cb_int[19]_i_31_n_0\ : STD_LOGIC; signal \cb_int[19]_i_34_n_0\ : STD_LOGIC; signal \cb_int[19]_i_35_n_0\ : STD_LOGIC; signal \cb_int[19]_i_36_n_0\ : STD_LOGIC; signal \cb_int[19]_i_37_n_0\ : STD_LOGIC; signal \cb_int[19]_i_3_n_0\ : STD_LOGIC; signal \cb_int[19]_i_4_n_0\ : STD_LOGIC; signal \cb_int[19]_i_5_n_0\ : STD_LOGIC; signal \cb_int[19]_i_6_n_0\ : STD_LOGIC; signal \cb_int[19]_i_7_n_0\ : STD_LOGIC; signal \cb_int[19]_i_8_n_0\ : STD_LOGIC; signal \cb_int[19]_i_9_n_0\ : STD_LOGIC; signal \cb_int[23]_i_10_n_0\ : STD_LOGIC; signal \cb_int[23]_i_11_n_0\ : STD_LOGIC; signal \cb_int[23]_i_12_n_0\ : STD_LOGIC; signal \cb_int[23]_i_13_n_0\ : STD_LOGIC; signal \cb_int[23]_i_14_n_0\ : STD_LOGIC; signal \cb_int[23]_i_15_n_0\ : STD_LOGIC; signal \cb_int[23]_i_16_n_0\ : STD_LOGIC; signal \cb_int[23]_i_17_n_0\ : STD_LOGIC; signal \cb_int[23]_i_18_n_0\ : STD_LOGIC; signal \cb_int[23]_i_20_n_0\ : STD_LOGIC; signal \cb_int[23]_i_22_n_0\ : STD_LOGIC; signal \cb_int[23]_i_25_n_0\ : STD_LOGIC; signal \cb_int[23]_i_29_n_0\ : STD_LOGIC; signal \cb_int[23]_i_2_n_0\ : STD_LOGIC; signal \cb_int[23]_i_30_n_0\ : STD_LOGIC; signal \cb_int[23]_i_31_n_0\ : STD_LOGIC; signal \cb_int[23]_i_32_n_0\ : STD_LOGIC; signal \cb_int[23]_i_3_n_0\ : STD_LOGIC; signal \cb_int[23]_i_4_n_0\ : STD_LOGIC; signal \cb_int[23]_i_5_n_0\ : STD_LOGIC; signal \cb_int[23]_i_6_n_0\ : STD_LOGIC; signal \cb_int[23]_i_7_n_0\ : STD_LOGIC; signal \cb_int[23]_i_8_n_0\ : STD_LOGIC; signal \cb_int[23]_i_9_n_0\ : STD_LOGIC; signal \cb_int[27]_i_10_n_0\ : STD_LOGIC; signal \cb_int[27]_i_12_n_0\ : STD_LOGIC; signal \cb_int[27]_i_13_n_0\ : STD_LOGIC; signal \cb_int[27]_i_14_n_0\ : STD_LOGIC; signal \cb_int[27]_i_15_n_0\ : STD_LOGIC; signal \cb_int[27]_i_2_n_0\ : STD_LOGIC; signal \cb_int[27]_i_3_n_0\ : STD_LOGIC; signal \cb_int[27]_i_4_n_0\ : STD_LOGIC; signal \cb_int[27]_i_5_n_0\ : STD_LOGIC; signal \cb_int[27]_i_6_n_0\ : STD_LOGIC; signal \cb_int[27]_i_7_n_0\ : STD_LOGIC; signal \cb_int[27]_i_8_n_0\ : STD_LOGIC; signal \cb_int[31]_i_13_n_0\ : STD_LOGIC; signal \cb_int[31]_i_15_n_0\ : STD_LOGIC; signal \cb_int[31]_i_16_n_0\ : STD_LOGIC; signal \cb_int[31]_i_2_n_0\ : STD_LOGIC; signal \cb_int[31]_i_31_n_0\ : STD_LOGIC; signal \cb_int[31]_i_32_n_0\ : STD_LOGIC; signal \cb_int[31]_i_35_n_0\ : STD_LOGIC; signal \cb_int[31]_i_36_n_0\ : STD_LOGIC; signal \cb_int[31]_i_38_n_0\ : STD_LOGIC; signal \cb_int[31]_i_39_n_0\ : STD_LOGIC; signal \cb_int[31]_i_3_n_0\ : STD_LOGIC; signal \cb_int[31]_i_40_n_0\ : STD_LOGIC; signal \cb_int[31]_i_41_n_0\ : STD_LOGIC; signal \cb_int[31]_i_4_n_0\ : STD_LOGIC; signal \cb_int[31]_i_5_n_0\ : STD_LOGIC; signal \cb_int[31]_i_67_n_0\ : STD_LOGIC; signal \cb_int[31]_i_68_n_0\ : STD_LOGIC; signal \cb_int[31]_i_69_n_0\ : STD_LOGIC; signal \cb_int[31]_i_6_n_0\ : STD_LOGIC; signal \cb_int[31]_i_70_n_0\ : STD_LOGIC; signal \cb_int[31]_i_71_n_0\ : STD_LOGIC; signal \cb_int[31]_i_72_n_0\ : STD_LOGIC; signal \cb_int[31]_i_74_n_0\ : STD_LOGIC; signal \cb_int[31]_i_75_n_0\ : STD_LOGIC; signal \cb_int[31]_i_76_n_0\ : STD_LOGIC; signal \cb_int[31]_i_77_n_0\ : STD_LOGIC; signal \cb_int[31]_i_78_n_0\ : STD_LOGIC; signal \cb_int[31]_i_79_n_0\ : STD_LOGIC; signal \cb_int[31]_i_80_n_0\ : STD_LOGIC; signal \cb_int[31]_i_81_n_0\ : STD_LOGIC; signal \cb_int[31]_i_82_n_0\ : STD_LOGIC; signal \cb_int[31]_i_95_n_0\ : STD_LOGIC; signal \cb_int[31]_i_96_n_0\ : STD_LOGIC; signal \cb_int[31]_i_97_n_0\ : STD_LOGIC; signal \cb_int[31]_i_98_n_0\ : STD_LOGIC; signal \cb_int[3]_i_100_n_0\ : STD_LOGIC; signal \cb_int[3]_i_101_n_0\ : STD_LOGIC; signal \cb_int[3]_i_102_n_0\ : STD_LOGIC; signal \cb_int[3]_i_103_n_0\ : STD_LOGIC; signal \cb_int[3]_i_104_n_0\ : STD_LOGIC; signal \cb_int[3]_i_105_n_0\ : STD_LOGIC; signal \cb_int[3]_i_106_n_0\ : STD_LOGIC; signal \cb_int[3]_i_10_n_0\ : STD_LOGIC; signal \cb_int[3]_i_12_n_0\ : STD_LOGIC; signal \cb_int[3]_i_13_n_0\ : STD_LOGIC; signal \cb_int[3]_i_17_n_0\ : STD_LOGIC; signal \cb_int[3]_i_18_n_0\ : STD_LOGIC; signal \cb_int[3]_i_22_n_0\ : STD_LOGIC; signal \cb_int[3]_i_23_n_0\ : STD_LOGIC; signal \cb_int[3]_i_24_n_0\ : STD_LOGIC; signal \cb_int[3]_i_25_n_0\ : STD_LOGIC; signal \cb_int[3]_i_27_n_0\ : STD_LOGIC; signal \cb_int[3]_i_28_n_0\ : STD_LOGIC; signal \cb_int[3]_i_29_n_0\ : STD_LOGIC; signal \cb_int[3]_i_2_n_0\ : STD_LOGIC; signal \cb_int[3]_i_30_n_0\ : STD_LOGIC; signal \cb_int[3]_i_31_n_0\ : STD_LOGIC; signal \cb_int[3]_i_3_n_0\ : STD_LOGIC; signal \cb_int[3]_i_45_n_0\ : STD_LOGIC; signal \cb_int[3]_i_46_n_0\ : STD_LOGIC; signal \cb_int[3]_i_47_n_0\ : STD_LOGIC; signal \cb_int[3]_i_48_n_0\ : STD_LOGIC; signal \cb_int[3]_i_49_n_0\ : STD_LOGIC; signal \cb_int[3]_i_4_n_0\ : STD_LOGIC; signal \cb_int[3]_i_50_n_0\ : STD_LOGIC; signal \cb_int[3]_i_51_n_0\ : STD_LOGIC; signal \cb_int[3]_i_52_n_0\ : STD_LOGIC; signal \cb_int[3]_i_53_n_0\ : STD_LOGIC; signal \cb_int[3]_i_54_n_0\ : STD_LOGIC; signal \cb_int[3]_i_55_n_0\ : STD_LOGIC; signal \cb_int[3]_i_56_n_0\ : STD_LOGIC; signal \cb_int[3]_i_5_n_0\ : STD_LOGIC; signal \cb_int[3]_i_64_n_0\ : STD_LOGIC; signal \cb_int[3]_i_65_n_0\ : STD_LOGIC; signal \cb_int[3]_i_66_n_0\ : STD_LOGIC; signal \cb_int[3]_i_67_n_0\ : STD_LOGIC; signal \cb_int[3]_i_69_n_0\ : STD_LOGIC; signal \cb_int[3]_i_6_n_0\ : STD_LOGIC; signal \cb_int[3]_i_70_n_0\ : STD_LOGIC; signal \cb_int[3]_i_71_n_0\ : STD_LOGIC; signal \cb_int[3]_i_72_n_0\ : STD_LOGIC; signal \cb_int[3]_i_76_n_0\ : STD_LOGIC; signal \cb_int[3]_i_77_n_0\ : STD_LOGIC; signal \cb_int[3]_i_78_n_0\ : STD_LOGIC; signal \cb_int[3]_i_79_n_0\ : STD_LOGIC; signal \cb_int[3]_i_7_n_0\ : STD_LOGIC; signal \cb_int[3]_i_80_n_0\ : STD_LOGIC; signal \cb_int[3]_i_81_n_0\ : STD_LOGIC; signal \cb_int[3]_i_82_n_0\ : STD_LOGIC; signal \cb_int[3]_i_83_n_0\ : STD_LOGIC; signal \cb_int[3]_i_89_n_0\ : STD_LOGIC; signal \cb_int[3]_i_8_n_0\ : STD_LOGIC; signal \cb_int[3]_i_90_n_0\ : STD_LOGIC; signal \cb_int[3]_i_91_n_0\ : STD_LOGIC; signal \cb_int[3]_i_92_n_0\ : STD_LOGIC; signal \cb_int[3]_i_93_n_0\ : STD_LOGIC; signal \cb_int[3]_i_99_n_0\ : STD_LOGIC; signal \cb_int[3]_i_9_n_0\ : STD_LOGIC; signal \cb_int[7]_i_10_n_0\ : STD_LOGIC; signal \cb_int[7]_i_11_n_0\ : STD_LOGIC; signal \cb_int[7]_i_13_n_0\ : STD_LOGIC; signal \cb_int[7]_i_14_n_0\ : STD_LOGIC; signal \cb_int[7]_i_16_n_0\ : STD_LOGIC; signal \cb_int[7]_i_17_n_0\ : STD_LOGIC; signal \cb_int[7]_i_19_n_0\ : STD_LOGIC; signal \cb_int[7]_i_21_n_0\ : STD_LOGIC; signal \cb_int[7]_i_22_n_0\ : STD_LOGIC; signal \cb_int[7]_i_2_n_0\ : STD_LOGIC; signal \cb_int[7]_i_39_n_0\ : STD_LOGIC; signal \cb_int[7]_i_3_n_0\ : STD_LOGIC; signal \cb_int[7]_i_40_n_0\ : STD_LOGIC; signal \cb_int[7]_i_41_n_0\ : STD_LOGIC; signal \cb_int[7]_i_42_n_0\ : STD_LOGIC; signal \cb_int[7]_i_4_n_0\ : STD_LOGIC; signal \cb_int[7]_i_52_n_0\ : STD_LOGIC; signal \cb_int[7]_i_53_n_0\ : STD_LOGIC; signal \cb_int[7]_i_54_n_0\ : STD_LOGIC; signal \cb_int[7]_i_55_n_0\ : STD_LOGIC; signal \cb_int[7]_i_56_n_0\ : STD_LOGIC; signal \cb_int[7]_i_57_n_0\ : STD_LOGIC; signal \cb_int[7]_i_58_n_0\ : STD_LOGIC; signal \cb_int[7]_i_59_n_0\ : STD_LOGIC; signal \cb_int[7]_i_5_n_0\ : STD_LOGIC; signal \cb_int[7]_i_60_n_0\ : STD_LOGIC; signal \cb_int[7]_i_62_n_0\ : STD_LOGIC; signal \cb_int[7]_i_63_n_0\ : STD_LOGIC; signal \cb_int[7]_i_64_n_0\ : STD_LOGIC; signal \cb_int[7]_i_65_n_0\ : STD_LOGIC; signal \cb_int[7]_i_67_n_0\ : STD_LOGIC; signal \cb_int[7]_i_68_n_0\ : STD_LOGIC; signal \cb_int[7]_i_69_n_0\ : STD_LOGIC; signal \cb_int[7]_i_6_n_0\ : STD_LOGIC; signal \cb_int[7]_i_70_n_0\ : STD_LOGIC; signal \cb_int[7]_i_71_n_0\ : STD_LOGIC; signal \cb_int[7]_i_72_n_0\ : STD_LOGIC; signal \cb_int[7]_i_73_n_0\ : STD_LOGIC; signal \cb_int[7]_i_74_n_0\ : STD_LOGIC; signal \cb_int[7]_i_75_n_0\ : STD_LOGIC; signal \cb_int[7]_i_76_n_0\ : STD_LOGIC; signal \cb_int[7]_i_77_n_0\ : STD_LOGIC; signal \cb_int[7]_i_78_n_0\ : STD_LOGIC; signal \cb_int[7]_i_79_n_0\ : STD_LOGIC; signal \cb_int[7]_i_7_n_0\ : STD_LOGIC; signal \cb_int[7]_i_80_n_0\ : STD_LOGIC; signal \cb_int[7]_i_81_n_0\ : STD_LOGIC; signal \cb_int[7]_i_82_n_0\ : STD_LOGIC; signal \cb_int[7]_i_8_n_0\ : STD_LOGIC; signal \cb_int[7]_i_9_n_0\ : STD_LOGIC; signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 ); signal cb_int_reg8 : STD_LOGIC; signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC; signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC; signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC; signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC; signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC; signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC; signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC; signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC; signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \cb_int_reg_n_0_[0]\ : STD_LOGIC; signal \cb_int_reg_n_0_[1]\ : STD_LOGIC; signal \cb_int_reg_n_0_[2]\ : STD_LOGIC; signal \cb_int_reg_n_0_[3]\ : STD_LOGIC; signal \cb_int_reg_n_0_[4]\ : STD_LOGIC; signal \cb_int_reg_n_0_[5]\ : STD_LOGIC; signal \cb_int_reg_n_0_[6]\ : STD_LOGIC; signal \cb_int_reg_n_0_[7]\ : STD_LOGIC; signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC; signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC; signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC; signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC; signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC; signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC; signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC; signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC; signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC; signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC; signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC; signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC; signal cb_regn_0_0 : STD_LOGIC; signal cr : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \cr[0]_i_1_n_0\ : STD_LOGIC; signal \cr[1]_i_1_n_0\ : STD_LOGIC; signal \cr[2]_i_1_n_0\ : STD_LOGIC; signal \cr[3]_i_1_n_0\ : STD_LOGIC; signal \cr[4]_i_1_n_0\ : STD_LOGIC; signal \cr[5]_i_1_n_0\ : STD_LOGIC; signal \cr[6]_i_1_n_0\ : STD_LOGIC; signal \cr[7]_i_10_n_0\ : STD_LOGIC; signal \cr[7]_i_11_n_0\ : STD_LOGIC; signal \cr[7]_i_13_n_0\ : STD_LOGIC; signal \cr[7]_i_14_n_0\ : STD_LOGIC; signal \cr[7]_i_15_n_0\ : STD_LOGIC; signal \cr[7]_i_16_n_0\ : STD_LOGIC; signal \cr[7]_i_17_n_0\ : STD_LOGIC; signal \cr[7]_i_18_n_0\ : STD_LOGIC; signal \cr[7]_i_19_n_0\ : STD_LOGIC; signal \cr[7]_i_20_n_0\ : STD_LOGIC; signal \cr[7]_i_21_n_0\ : STD_LOGIC; signal \cr[7]_i_22_n_0\ : STD_LOGIC; signal \cr[7]_i_23_n_0\ : STD_LOGIC; signal \cr[7]_i_24_n_0\ : STD_LOGIC; signal \cr[7]_i_25_n_0\ : STD_LOGIC; signal \cr[7]_i_26_n_0\ : STD_LOGIC; signal \cr[7]_i_27_n_0\ : STD_LOGIC; signal \cr[7]_i_28_n_0\ : STD_LOGIC; signal \cr[7]_i_2_n_0\ : STD_LOGIC; signal \cr[7]_i_4_n_0\ : STD_LOGIC; signal \cr[7]_i_5_n_0\ : STD_LOGIC; signal \cr[7]_i_6_n_0\ : STD_LOGIC; signal \cr[7]_i_7_n_0\ : STD_LOGIC; signal \cr[7]_i_8_n_0\ : STD_LOGIC; signal \cr[7]_i_9_n_0\ : STD_LOGIC; signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC; signal \cr_int[11]_i_100_n_0\ : STD_LOGIC; signal \cr_int[11]_i_101_n_0\ : STD_LOGIC; signal \cr_int[11]_i_102_n_0\ : STD_LOGIC; signal \cr_int[11]_i_104_n_0\ : STD_LOGIC; signal \cr_int[11]_i_105_n_0\ : STD_LOGIC; signal \cr_int[11]_i_106_n_0\ : STD_LOGIC; signal \cr_int[11]_i_107_n_0\ : STD_LOGIC; signal \cr_int[11]_i_109_n_0\ : STD_LOGIC; signal \cr_int[11]_i_10_n_0\ : STD_LOGIC; signal \cr_int[11]_i_110_n_0\ : STD_LOGIC; signal \cr_int[11]_i_111_n_0\ : STD_LOGIC; signal \cr_int[11]_i_112_n_0\ : STD_LOGIC; signal \cr_int[11]_i_113_n_0\ : STD_LOGIC; signal \cr_int[11]_i_114_n_0\ : STD_LOGIC; signal \cr_int[11]_i_115_n_0\ : STD_LOGIC; signal \cr_int[11]_i_117_n_0\ : STD_LOGIC; signal \cr_int[11]_i_118_n_0\ : STD_LOGIC; signal \cr_int[11]_i_119_n_0\ : STD_LOGIC; signal \cr_int[11]_i_11_n_0\ : STD_LOGIC; signal \cr_int[11]_i_120_n_0\ : STD_LOGIC; signal \cr_int[11]_i_121_n_0\ : STD_LOGIC; signal \cr_int[11]_i_122_n_0\ : STD_LOGIC; signal \cr_int[11]_i_123_n_0\ : STD_LOGIC; signal \cr_int[11]_i_124_n_0\ : STD_LOGIC; signal \cr_int[11]_i_126_n_0\ : STD_LOGIC; signal \cr_int[11]_i_127_n_0\ : STD_LOGIC; signal \cr_int[11]_i_128_n_0\ : STD_LOGIC; signal \cr_int[11]_i_129_n_0\ : STD_LOGIC; signal \cr_int[11]_i_12_n_0\ : STD_LOGIC; signal \cr_int[11]_i_130_n_0\ : STD_LOGIC; signal \cr_int[11]_i_131_n_0\ : STD_LOGIC; signal \cr_int[11]_i_132_n_0\ : STD_LOGIC; signal \cr_int[11]_i_133_n_0\ : STD_LOGIC; signal \cr_int[11]_i_134_n_0\ : STD_LOGIC; signal \cr_int[11]_i_135_n_0\ : STD_LOGIC; signal \cr_int[11]_i_136_n_0\ : STD_LOGIC; signal \cr_int[11]_i_137_n_0\ : STD_LOGIC; signal \cr_int[11]_i_138_n_0\ : STD_LOGIC; signal \cr_int[11]_i_139_n_0\ : STD_LOGIC; signal \cr_int[11]_i_13_n_0\ : STD_LOGIC; signal \cr_int[11]_i_140_n_0\ : STD_LOGIC; signal \cr_int[11]_i_141_n_0\ : STD_LOGIC; signal \cr_int[11]_i_142_n_0\ : STD_LOGIC; signal \cr_int[11]_i_143_n_0\ : STD_LOGIC; signal \cr_int[11]_i_144_n_0\ : STD_LOGIC; signal \cr_int[11]_i_145_n_0\ : STD_LOGIC; signal \cr_int[11]_i_146_n_0\ : STD_LOGIC; signal \cr_int[11]_i_147_n_0\ : STD_LOGIC; signal \cr_int[11]_i_148_n_0\ : STD_LOGIC; signal \cr_int[11]_i_149_n_0\ : STD_LOGIC; signal \cr_int[11]_i_14_n_0\ : STD_LOGIC; signal \cr_int[11]_i_150_n_0\ : STD_LOGIC; signal \cr_int[11]_i_151_n_0\ : STD_LOGIC; signal \cr_int[11]_i_152_n_0\ : STD_LOGIC; signal \cr_int[11]_i_153_n_0\ : STD_LOGIC; signal \cr_int[11]_i_154_n_0\ : STD_LOGIC; signal \cr_int[11]_i_155_n_0\ : STD_LOGIC; signal \cr_int[11]_i_156_n_0\ : STD_LOGIC; signal \cr_int[11]_i_15_n_0\ : STD_LOGIC; signal \cr_int[11]_i_22_n_0\ : STD_LOGIC; signal \cr_int[11]_i_23_n_0\ : STD_LOGIC; signal \cr_int[11]_i_24_n_0\ : STD_LOGIC; signal \cr_int[11]_i_25_n_0\ : STD_LOGIC; signal \cr_int[11]_i_27_n_0\ : STD_LOGIC; signal \cr_int[11]_i_2_n_0\ : STD_LOGIC; signal \cr_int[11]_i_32_n_0\ : STD_LOGIC; signal \cr_int[11]_i_33_n_0\ : STD_LOGIC; signal \cr_int[11]_i_34_n_0\ : STD_LOGIC; signal \cr_int[11]_i_35_n_0\ : STD_LOGIC; signal \cr_int[11]_i_37_n_0\ : STD_LOGIC; signal \cr_int[11]_i_38_n_0\ : STD_LOGIC; signal \cr_int[11]_i_39_n_0\ : STD_LOGIC; signal \cr_int[11]_i_3_n_0\ : STD_LOGIC; signal \cr_int[11]_i_40_n_0\ : STD_LOGIC; signal \cr_int[11]_i_42_n_0\ : STD_LOGIC; signal \cr_int[11]_i_43_n_0\ : STD_LOGIC; signal \cr_int[11]_i_44_n_0\ : STD_LOGIC; signal \cr_int[11]_i_45_n_0\ : STD_LOGIC; signal \cr_int[11]_i_47_n_0\ : STD_LOGIC; signal \cr_int[11]_i_48_n_0\ : STD_LOGIC; signal \cr_int[11]_i_49_n_0\ : STD_LOGIC; signal \cr_int[11]_i_4_n_0\ : STD_LOGIC; signal \cr_int[11]_i_50_n_0\ : STD_LOGIC; signal \cr_int[11]_i_52_n_0\ : STD_LOGIC; signal \cr_int[11]_i_53_n_0\ : STD_LOGIC; signal \cr_int[11]_i_54_n_0\ : STD_LOGIC; signal \cr_int[11]_i_55_n_0\ : STD_LOGIC; signal \cr_int[11]_i_57_n_0\ : STD_LOGIC; signal \cr_int[11]_i_58_n_0\ : STD_LOGIC; signal \cr_int[11]_i_59_n_0\ : STD_LOGIC; signal \cr_int[11]_i_5_n_0\ : STD_LOGIC; signal \cr_int[11]_i_60_n_0\ : STD_LOGIC; signal \cr_int[11]_i_65_n_0\ : STD_LOGIC; signal \cr_int[11]_i_66_n_0\ : STD_LOGIC; signal \cr_int[11]_i_67_n_0\ : STD_LOGIC; signal \cr_int[11]_i_68_n_0\ : STD_LOGIC; signal \cr_int[11]_i_6_n_0\ : STD_LOGIC; signal \cr_int[11]_i_70_n_0\ : STD_LOGIC; signal \cr_int[11]_i_71_n_0\ : STD_LOGIC; signal \cr_int[11]_i_72_n_0\ : STD_LOGIC; signal \cr_int[11]_i_73_n_0\ : STD_LOGIC; signal \cr_int[11]_i_74_n_0\ : STD_LOGIC; signal \cr_int[11]_i_75_n_0\ : STD_LOGIC; signal \cr_int[11]_i_76_n_0\ : STD_LOGIC; signal \cr_int[11]_i_77_n_0\ : STD_LOGIC; signal \cr_int[11]_i_78_n_0\ : STD_LOGIC; signal \cr_int[11]_i_7_n_0\ : STD_LOGIC; signal \cr_int[11]_i_80_n_0\ : STD_LOGIC; signal \cr_int[11]_i_81_n_0\ : STD_LOGIC; signal \cr_int[11]_i_82_n_0\ : STD_LOGIC; signal \cr_int[11]_i_83_n_0\ : STD_LOGIC; signal \cr_int[11]_i_84_n_0\ : STD_LOGIC; signal \cr_int[11]_i_85_n_0\ : STD_LOGIC; signal \cr_int[11]_i_86_n_0\ : STD_LOGIC; signal \cr_int[11]_i_87_n_0\ : STD_LOGIC; signal \cr_int[11]_i_88_n_0\ : STD_LOGIC; signal \cr_int[11]_i_89_n_0\ : STD_LOGIC; signal \cr_int[11]_i_8_n_0\ : STD_LOGIC; signal \cr_int[11]_i_90_n_0\ : STD_LOGIC; signal \cr_int[11]_i_91_n_0\ : STD_LOGIC; signal \cr_int[11]_i_93_n_0\ : STD_LOGIC; signal \cr_int[11]_i_94_n_0\ : STD_LOGIC; signal \cr_int[11]_i_95_n_0\ : STD_LOGIC; signal \cr_int[11]_i_96_n_0\ : STD_LOGIC; signal \cr_int[11]_i_97_n_0\ : STD_LOGIC; signal \cr_int[11]_i_98_n_0\ : STD_LOGIC; signal \cr_int[11]_i_99_n_0\ : STD_LOGIC; signal \cr_int[11]_i_9_n_0\ : STD_LOGIC; signal \cr_int[15]_i_10_n_0\ : STD_LOGIC; signal \cr_int[15]_i_11_n_0\ : STD_LOGIC; signal \cr_int[15]_i_12_n_0\ : STD_LOGIC; signal \cr_int[15]_i_13_n_0\ : STD_LOGIC; signal \cr_int[15]_i_14_n_0\ : STD_LOGIC; signal \cr_int[15]_i_15_n_0\ : STD_LOGIC; signal \cr_int[15]_i_16_n_0\ : STD_LOGIC; signal \cr_int[15]_i_17_n_0\ : STD_LOGIC; signal \cr_int[15]_i_18_n_0\ : STD_LOGIC; signal \cr_int[15]_i_19_n_0\ : STD_LOGIC; signal \cr_int[15]_i_22_n_0\ : STD_LOGIC; signal \cr_int[15]_i_23_n_0\ : STD_LOGIC; signal \cr_int[15]_i_24_n_0\ : STD_LOGIC; signal \cr_int[15]_i_25_n_0\ : STD_LOGIC; signal \cr_int[15]_i_26_n_0\ : STD_LOGIC; signal \cr_int[15]_i_27_n_0\ : STD_LOGIC; signal \cr_int[15]_i_29_n_0\ : STD_LOGIC; signal \cr_int[15]_i_2_n_0\ : STD_LOGIC; signal \cr_int[15]_i_30_n_0\ : STD_LOGIC; signal \cr_int[15]_i_31_n_0\ : STD_LOGIC; signal \cr_int[15]_i_32_n_0\ : STD_LOGIC; signal \cr_int[15]_i_33_n_0\ : STD_LOGIC; signal \cr_int[15]_i_34_n_0\ : STD_LOGIC; signal \cr_int[15]_i_35_n_0\ : STD_LOGIC; signal \cr_int[15]_i_36_n_0\ : STD_LOGIC; signal \cr_int[15]_i_3_n_0\ : STD_LOGIC; signal \cr_int[15]_i_40_n_0\ : STD_LOGIC; signal \cr_int[15]_i_41_n_0\ : STD_LOGIC; signal \cr_int[15]_i_42_n_0\ : STD_LOGIC; signal \cr_int[15]_i_43_n_0\ : STD_LOGIC; signal \cr_int[15]_i_48_n_0\ : STD_LOGIC; signal \cr_int[15]_i_49_n_0\ : STD_LOGIC; signal \cr_int[15]_i_4_n_0\ : STD_LOGIC; signal \cr_int[15]_i_50_n_0\ : STD_LOGIC; signal \cr_int[15]_i_51_n_0\ : STD_LOGIC; signal \cr_int[15]_i_5_n_0\ : STD_LOGIC; signal \cr_int[15]_i_6_n_0\ : STD_LOGIC; signal \cr_int[15]_i_7_n_0\ : STD_LOGIC; signal \cr_int[15]_i_8_n_0\ : STD_LOGIC; signal \cr_int[15]_i_9_n_0\ : STD_LOGIC; signal \cr_int[19]_i_10_n_0\ : STD_LOGIC; signal \cr_int[19]_i_11_n_0\ : STD_LOGIC; signal \cr_int[19]_i_12_n_0\ : STD_LOGIC; signal \cr_int[19]_i_13_n_0\ : STD_LOGIC; signal \cr_int[19]_i_14_n_0\ : STD_LOGIC; signal \cr_int[19]_i_15_n_0\ : STD_LOGIC; signal \cr_int[19]_i_16_n_0\ : STD_LOGIC; signal \cr_int[19]_i_17_n_0\ : STD_LOGIC; signal \cr_int[19]_i_18_n_0\ : STD_LOGIC; signal \cr_int[19]_i_19_n_0\ : STD_LOGIC; signal \cr_int[19]_i_22_n_0\ : STD_LOGIC; signal \cr_int[19]_i_23_n_0\ : STD_LOGIC; signal \cr_int[19]_i_24_n_0\ : STD_LOGIC; signal \cr_int[19]_i_25_n_0\ : STD_LOGIC; signal \cr_int[19]_i_26_n_0\ : STD_LOGIC; signal \cr_int[19]_i_27_n_0\ : STD_LOGIC; signal \cr_int[19]_i_29_n_0\ : STD_LOGIC; signal \cr_int[19]_i_2_n_0\ : STD_LOGIC; signal \cr_int[19]_i_30_n_0\ : STD_LOGIC; signal \cr_int[19]_i_31_n_0\ : STD_LOGIC; signal \cr_int[19]_i_32_n_0\ : STD_LOGIC; signal \cr_int[19]_i_33_n_0\ : STD_LOGIC; signal \cr_int[19]_i_34_n_0\ : STD_LOGIC; signal \cr_int[19]_i_35_n_0\ : STD_LOGIC; signal \cr_int[19]_i_36_n_0\ : STD_LOGIC; signal \cr_int[19]_i_38_n_0\ : STD_LOGIC; signal \cr_int[19]_i_39_n_0\ : STD_LOGIC; signal \cr_int[19]_i_3_n_0\ : STD_LOGIC; signal \cr_int[19]_i_40_n_0\ : STD_LOGIC; signal \cr_int[19]_i_41_n_0\ : STD_LOGIC; signal \cr_int[19]_i_4_n_0\ : STD_LOGIC; signal \cr_int[19]_i_5_n_0\ : STD_LOGIC; signal \cr_int[19]_i_6_n_0\ : STD_LOGIC; signal \cr_int[19]_i_7_n_0\ : STD_LOGIC; signal \cr_int[19]_i_8_n_0\ : STD_LOGIC; signal \cr_int[19]_i_9_n_0\ : STD_LOGIC; signal \cr_int[23]_i_10_n_0\ : STD_LOGIC; signal \cr_int[23]_i_11_n_0\ : STD_LOGIC; signal \cr_int[23]_i_12_n_0\ : STD_LOGIC; signal \cr_int[23]_i_13_n_0\ : STD_LOGIC; signal \cr_int[23]_i_14_n_0\ : STD_LOGIC; signal \cr_int[23]_i_15_n_0\ : STD_LOGIC; signal \cr_int[23]_i_16_n_0\ : STD_LOGIC; signal \cr_int[23]_i_17_n_0\ : STD_LOGIC; signal \cr_int[23]_i_18_n_0\ : STD_LOGIC; signal \cr_int[23]_i_19_n_0\ : STD_LOGIC; signal \cr_int[23]_i_21_n_0\ : STD_LOGIC; signal \cr_int[23]_i_22_n_0\ : STD_LOGIC; signal \cr_int[23]_i_23_n_0\ : STD_LOGIC; signal \cr_int[23]_i_24_n_0\ : STD_LOGIC; signal \cr_int[23]_i_25_n_0\ : STD_LOGIC; signal \cr_int[23]_i_26_n_0\ : STD_LOGIC; signal \cr_int[23]_i_27_n_0\ : STD_LOGIC; signal \cr_int[23]_i_28_n_0\ : STD_LOGIC; signal \cr_int[23]_i_29_n_0\ : STD_LOGIC; signal \cr_int[23]_i_2_n_0\ : STD_LOGIC; signal \cr_int[23]_i_30_n_0\ : STD_LOGIC; signal \cr_int[23]_i_3_n_0\ : STD_LOGIC; signal \cr_int[23]_i_4_n_0\ : STD_LOGIC; signal \cr_int[23]_i_5_n_0\ : STD_LOGIC; signal \cr_int[23]_i_6_n_0\ : STD_LOGIC; signal \cr_int[23]_i_7_n_0\ : STD_LOGIC; signal \cr_int[23]_i_8_n_0\ : STD_LOGIC; signal \cr_int[23]_i_9_n_0\ : STD_LOGIC; signal \cr_int[27]_i_10_n_0\ : STD_LOGIC; signal \cr_int[27]_i_11_n_0\ : STD_LOGIC; signal \cr_int[27]_i_12_n_0\ : STD_LOGIC; signal \cr_int[27]_i_13_n_0\ : STD_LOGIC; signal \cr_int[27]_i_2_n_0\ : STD_LOGIC; signal \cr_int[27]_i_3_n_0\ : STD_LOGIC; signal \cr_int[27]_i_4_n_0\ : STD_LOGIC; signal \cr_int[27]_i_5_n_0\ : STD_LOGIC; signal \cr_int[27]_i_6_n_0\ : STD_LOGIC; signal \cr_int[27]_i_7_n_0\ : STD_LOGIC; signal \cr_int[27]_i_8_n_0\ : STD_LOGIC; signal \cr_int[31]_i_100_n_0\ : STD_LOGIC; signal \cr_int[31]_i_103_n_0\ : STD_LOGIC; signal \cr_int[31]_i_108_n_0\ : STD_LOGIC; signal \cr_int[31]_i_109_n_0\ : STD_LOGIC; signal \cr_int[31]_i_110_n_0\ : STD_LOGIC; signal \cr_int[31]_i_111_n_0\ : STD_LOGIC; signal \cr_int[31]_i_112_n_0\ : STD_LOGIC; signal \cr_int[31]_i_113_n_0\ : STD_LOGIC; signal \cr_int[31]_i_114_n_0\ : STD_LOGIC; signal \cr_int[31]_i_115_n_0\ : STD_LOGIC; signal \cr_int[31]_i_116_n_0\ : STD_LOGIC; signal \cr_int[31]_i_117_n_0\ : STD_LOGIC; signal \cr_int[31]_i_118_n_0\ : STD_LOGIC; signal \cr_int[31]_i_119_n_0\ : STD_LOGIC; signal \cr_int[31]_i_120_n_0\ : STD_LOGIC; signal \cr_int[31]_i_121_n_0\ : STD_LOGIC; signal \cr_int[31]_i_122_n_0\ : STD_LOGIC; signal \cr_int[31]_i_123_n_0\ : STD_LOGIC; signal \cr_int[31]_i_124_n_0\ : STD_LOGIC; signal \cr_int[31]_i_125_n_0\ : STD_LOGIC; signal \cr_int[31]_i_126_n_0\ : STD_LOGIC; signal \cr_int[31]_i_13_n_0\ : STD_LOGIC; signal \cr_int[31]_i_15_n_0\ : STD_LOGIC; signal \cr_int[31]_i_16_n_0\ : STD_LOGIC; signal \cr_int[31]_i_17_n_0\ : STD_LOGIC; signal \cr_int[31]_i_18_n_0\ : STD_LOGIC; signal \cr_int[31]_i_19_n_0\ : STD_LOGIC; signal \cr_int[31]_i_20_n_0\ : STD_LOGIC; signal \cr_int[31]_i_22_n_0\ : STD_LOGIC; signal \cr_int[31]_i_23_n_0\ : STD_LOGIC; signal \cr_int[31]_i_25_n_0\ : STD_LOGIC; signal \cr_int[31]_i_26_n_0\ : STD_LOGIC; signal \cr_int[31]_i_2_n_0\ : STD_LOGIC; signal \cr_int[31]_i_31_n_0\ : STD_LOGIC; signal \cr_int[31]_i_32_n_0\ : STD_LOGIC; signal \cr_int[31]_i_33_n_0\ : STD_LOGIC; signal \cr_int[31]_i_34_n_0\ : STD_LOGIC; signal \cr_int[31]_i_35_n_0\ : STD_LOGIC; signal \cr_int[31]_i_37_n_0\ : STD_LOGIC; signal \cr_int[31]_i_38_n_0\ : STD_LOGIC; signal \cr_int[31]_i_3_n_0\ : STD_LOGIC; signal \cr_int[31]_i_40_n_0\ : STD_LOGIC; signal \cr_int[31]_i_41_n_0\ : STD_LOGIC; signal \cr_int[31]_i_42_n_0\ : STD_LOGIC; signal \cr_int[31]_i_43_n_0\ : STD_LOGIC; signal \cr_int[31]_i_44_n_0\ : STD_LOGIC; signal \cr_int[31]_i_45_n_0\ : STD_LOGIC; signal \cr_int[31]_i_46_n_0\ : STD_LOGIC; signal \cr_int[31]_i_47_n_0\ : STD_LOGIC; signal \cr_int[31]_i_4_n_0\ : STD_LOGIC; signal \cr_int[31]_i_50_n_0\ : STD_LOGIC; signal \cr_int[31]_i_51_n_0\ : STD_LOGIC; signal \cr_int[31]_i_52_n_0\ : STD_LOGIC; signal \cr_int[31]_i_53_n_0\ : STD_LOGIC; signal \cr_int[31]_i_55_n_0\ : STD_LOGIC; signal \cr_int[31]_i_56_n_0\ : STD_LOGIC; signal \cr_int[31]_i_57_n_0\ : STD_LOGIC; signal \cr_int[31]_i_58_n_0\ : STD_LOGIC; signal \cr_int[31]_i_59_n_0\ : STD_LOGIC; signal \cr_int[31]_i_5_n_0\ : STD_LOGIC; signal \cr_int[31]_i_60_n_0\ : STD_LOGIC; signal \cr_int[31]_i_61_n_0\ : STD_LOGIC; signal \cr_int[31]_i_62_n_0\ : STD_LOGIC; signal \cr_int[31]_i_6_n_0\ : STD_LOGIC; signal \cr_int[31]_i_71_n_0\ : STD_LOGIC; signal \cr_int[31]_i_72_n_0\ : STD_LOGIC; signal \cr_int[31]_i_73_n_0\ : STD_LOGIC; signal \cr_int[31]_i_74_n_0\ : STD_LOGIC; signal \cr_int[31]_i_75_n_0\ : STD_LOGIC; signal \cr_int[31]_i_76_n_0\ : STD_LOGIC; signal \cr_int[31]_i_77_n_0\ : STD_LOGIC; signal \cr_int[31]_i_78_n_0\ : STD_LOGIC; signal \cr_int[31]_i_79_n_0\ : STD_LOGIC; signal \cr_int[31]_i_80_n_0\ : STD_LOGIC; signal \cr_int[31]_i_81_n_0\ : STD_LOGIC; signal \cr_int[31]_i_82_n_0\ : STD_LOGIC; signal \cr_int[31]_i_83_n_0\ : STD_LOGIC; signal \cr_int[31]_i_84_n_0\ : STD_LOGIC; signal \cr_int[31]_i_85_n_0\ : STD_LOGIC; signal \cr_int[31]_i_87_n_0\ : STD_LOGIC; signal \cr_int[31]_i_88_n_0\ : STD_LOGIC; signal \cr_int[31]_i_89_n_0\ : STD_LOGIC; signal \cr_int[31]_i_90_n_0\ : STD_LOGIC; signal \cr_int[31]_i_92_n_0\ : STD_LOGIC; signal \cr_int[31]_i_93_n_0\ : STD_LOGIC; signal \cr_int[31]_i_94_n_0\ : STD_LOGIC; signal \cr_int[31]_i_95_n_0\ : STD_LOGIC; signal \cr_int[31]_i_96_n_0\ : STD_LOGIC; signal \cr_int[31]_i_97_n_0\ : STD_LOGIC; signal \cr_int[3]_i_10_n_0\ : STD_LOGIC; signal \cr_int[3]_i_11_n_0\ : STD_LOGIC; signal \cr_int[3]_i_13_n_0\ : STD_LOGIC; signal \cr_int[3]_i_14_n_0\ : STD_LOGIC; signal \cr_int[3]_i_17_n_0\ : STD_LOGIC; signal \cr_int[3]_i_18_n_0\ : STD_LOGIC; signal \cr_int[3]_i_22_n_0\ : STD_LOGIC; signal \cr_int[3]_i_23_n_0\ : STD_LOGIC; signal \cr_int[3]_i_24_n_0\ : STD_LOGIC; signal \cr_int[3]_i_25_n_0\ : STD_LOGIC; signal \cr_int[3]_i_28_n_0\ : STD_LOGIC; signal \cr_int[3]_i_29_n_0\ : STD_LOGIC; signal \cr_int[3]_i_2_n_0\ : STD_LOGIC; signal \cr_int[3]_i_30_n_0\ : STD_LOGIC; signal \cr_int[3]_i_31_n_0\ : STD_LOGIC; signal \cr_int[3]_i_34_n_0\ : STD_LOGIC; signal \cr_int[3]_i_35_n_0\ : STD_LOGIC; signal \cr_int[3]_i_36_n_0\ : STD_LOGIC; signal \cr_int[3]_i_37_n_0\ : STD_LOGIC; signal \cr_int[3]_i_38_n_0\ : STD_LOGIC; signal \cr_int[3]_i_39_n_0\ : STD_LOGIC; signal \cr_int[3]_i_3_n_0\ : STD_LOGIC; signal \cr_int[3]_i_40_n_0\ : STD_LOGIC; signal \cr_int[3]_i_41_n_0\ : STD_LOGIC; signal \cr_int[3]_i_43_n_0\ : STD_LOGIC; signal \cr_int[3]_i_44_n_0\ : STD_LOGIC; signal \cr_int[3]_i_45_n_0\ : STD_LOGIC; signal \cr_int[3]_i_46_n_0\ : STD_LOGIC; signal \cr_int[3]_i_47_n_0\ : STD_LOGIC; signal \cr_int[3]_i_48_n_0\ : STD_LOGIC; signal \cr_int[3]_i_49_n_0\ : STD_LOGIC; signal \cr_int[3]_i_4_n_0\ : STD_LOGIC; signal \cr_int[3]_i_50_n_0\ : STD_LOGIC; signal \cr_int[3]_i_51_n_0\ : STD_LOGIC; signal \cr_int[3]_i_52_n_0\ : STD_LOGIC; signal \cr_int[3]_i_53_n_0\ : STD_LOGIC; signal \cr_int[3]_i_55_n_0\ : STD_LOGIC; signal \cr_int[3]_i_56_n_0\ : STD_LOGIC; signal \cr_int[3]_i_57_n_0\ : STD_LOGIC; signal \cr_int[3]_i_58_n_0\ : STD_LOGIC; signal \cr_int[3]_i_5_n_0\ : STD_LOGIC; signal \cr_int[3]_i_60_n_0\ : STD_LOGIC; signal \cr_int[3]_i_61_n_0\ : STD_LOGIC; signal \cr_int[3]_i_62_n_0\ : STD_LOGIC; signal \cr_int[3]_i_63_n_0\ : STD_LOGIC; signal \cr_int[3]_i_66_n_0\ : STD_LOGIC; signal \cr_int[3]_i_67_n_0\ : STD_LOGIC; signal \cr_int[3]_i_68_n_0\ : STD_LOGIC; signal \cr_int[3]_i_69_n_0\ : STD_LOGIC; signal \cr_int[3]_i_6_n_0\ : STD_LOGIC; signal \cr_int[3]_i_71_n_0\ : STD_LOGIC; signal \cr_int[3]_i_72_n_0\ : STD_LOGIC; signal \cr_int[3]_i_73_n_0\ : STD_LOGIC; signal \cr_int[3]_i_74_n_0\ : STD_LOGIC; signal \cr_int[3]_i_75_n_0\ : STD_LOGIC; signal \cr_int[3]_i_76_n_0\ : STD_LOGIC; signal \cr_int[3]_i_77_n_0\ : STD_LOGIC; signal \cr_int[3]_i_78_n_0\ : STD_LOGIC; signal \cr_int[3]_i_79_n_0\ : STD_LOGIC; signal \cr_int[3]_i_7_n_0\ : STD_LOGIC; signal \cr_int[3]_i_80_n_0\ : STD_LOGIC; signal \cr_int[3]_i_81_n_0\ : STD_LOGIC; signal \cr_int[3]_i_82_n_0\ : STD_LOGIC; signal \cr_int[3]_i_83_n_0\ : STD_LOGIC; signal \cr_int[3]_i_84_n_0\ : STD_LOGIC; signal \cr_int[3]_i_85_n_0\ : STD_LOGIC; signal \cr_int[3]_i_86_n_0\ : STD_LOGIC; signal \cr_int[3]_i_87_n_0\ : STD_LOGIC; signal \cr_int[3]_i_88_n_0\ : STD_LOGIC; signal \cr_int[3]_i_89_n_0\ : STD_LOGIC; signal \cr_int[3]_i_8_n_0\ : STD_LOGIC; signal \cr_int[3]_i_90_n_0\ : STD_LOGIC; signal \cr_int[3]_i_91_n_0\ : STD_LOGIC; signal \cr_int[3]_i_92_n_0\ : STD_LOGIC; signal \cr_int[3]_i_93_n_0\ : STD_LOGIC; signal \cr_int[3]_i_94_n_0\ : STD_LOGIC; signal \cr_int[3]_i_95_n_0\ : STD_LOGIC; signal \cr_int[3]_i_96_n_0\ : STD_LOGIC; signal \cr_int[7]_i_11_n_0\ : STD_LOGIC; signal \cr_int[7]_i_12_n_0\ : STD_LOGIC; signal \cr_int[7]_i_14_n_0\ : STD_LOGIC; signal \cr_int[7]_i_15_n_0\ : STD_LOGIC; signal \cr_int[7]_i_17_n_0\ : STD_LOGIC; signal \cr_int[7]_i_18_n_0\ : STD_LOGIC; signal \cr_int[7]_i_20_n_0\ : STD_LOGIC; signal \cr_int[7]_i_21_n_0\ : STD_LOGIC; signal \cr_int[7]_i_25_n_0\ : STD_LOGIC; signal \cr_int[7]_i_26_n_0\ : STD_LOGIC; signal \cr_int[7]_i_27_n_0\ : STD_LOGIC; signal \cr_int[7]_i_28_n_0\ : STD_LOGIC; signal \cr_int[7]_i_2_n_0\ : STD_LOGIC; signal \cr_int[7]_i_3_n_0\ : STD_LOGIC; signal \cr_int[7]_i_4_n_0\ : STD_LOGIC; signal \cr_int[7]_i_5_n_0\ : STD_LOGIC; signal \cr_int[7]_i_6_n_0\ : STD_LOGIC; signal \cr_int[7]_i_7_n_0\ : STD_LOGIC; signal \cr_int[7]_i_8_n_0\ : STD_LOGIC; signal \cr_int[7]_i_9_n_0\ : STD_LOGIC; signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 ); signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 ); signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 ); signal cr_int_reg7 : STD_LOGIC; signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC; signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC; signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC; signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC; signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC; signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC; signal \^cr_int_reg[27]_0\ : STD_LOGIC; signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC; signal \^cr_int_reg[31]_0\ : STD_LOGIC; signal \^cr_int_reg[31]_1\ : STD_LOGIC; signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC; signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC; signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC; signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC; signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC; signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC; signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \cr_int_reg_n_0_[0]\ : STD_LOGIC; signal \cr_int_reg_n_0_[1]\ : STD_LOGIC; signal \cr_int_reg_n_0_[2]\ : STD_LOGIC; signal \cr_int_reg_n_0_[3]\ : STD_LOGIC; signal \cr_int_reg_n_0_[4]\ : STD_LOGIC; signal \cr_int_reg_n_0_[5]\ : STD_LOGIC; signal \cr_int_reg_n_0_[6]\ : STD_LOGIC; signal \cr_int_reg_n_0_[7]\ : STD_LOGIC; signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC; signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC; signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC; signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC; signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC; signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC; signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC; signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC; signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC; signal edge : STD_LOGIC; signal edge_i_1_n_0 : STD_LOGIC; signal edge_rb : STD_LOGIC; signal edge_rb_i_1_n_0 : STD_LOGIC; signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC; signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC; signal hdmi_vsync_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal y : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \y[0]_i_1_n_0\ : STD_LOGIC; signal \y[1]_i_1_n_0\ : STD_LOGIC; signal \y[2]_i_1_n_0\ : STD_LOGIC; signal \y[3]_i_1_n_0\ : STD_LOGIC; signal \y[4]_i_1_n_0\ : STD_LOGIC; signal \y[5]_i_1_n_0\ : STD_LOGIC; signal \y[6]_i_1_n_0\ : STD_LOGIC; signal \y[7]_i_10_n_0\ : STD_LOGIC; signal \y[7]_i_11_n_0\ : STD_LOGIC; signal \y[7]_i_13_n_0\ : STD_LOGIC; signal \y[7]_i_14_n_0\ : STD_LOGIC; signal \y[7]_i_15_n_0\ : STD_LOGIC; signal \y[7]_i_16_n_0\ : STD_LOGIC; signal \y[7]_i_17_n_0\ : STD_LOGIC; signal \y[7]_i_18_n_0\ : STD_LOGIC; signal \y[7]_i_19_n_0\ : STD_LOGIC; signal \y[7]_i_20_n_0\ : STD_LOGIC; signal \y[7]_i_21_n_0\ : STD_LOGIC; signal \y[7]_i_22_n_0\ : STD_LOGIC; signal \y[7]_i_23_n_0\ : STD_LOGIC; signal \y[7]_i_24_n_0\ : STD_LOGIC; signal \y[7]_i_25_n_0\ : STD_LOGIC; signal \y[7]_i_26_n_0\ : STD_LOGIC; signal \y[7]_i_27_n_0\ : STD_LOGIC; signal \y[7]_i_28_n_0\ : STD_LOGIC; signal \y[7]_i_2_n_0\ : STD_LOGIC; signal \y[7]_i_4_n_0\ : STD_LOGIC; signal \y[7]_i_5_n_0\ : STD_LOGIC; signal \y[7]_i_6_n_0\ : STD_LOGIC; signal \y[7]_i_7_n_0\ : STD_LOGIC; signal \y[7]_i_8_n_0\ : STD_LOGIC; signal \y[7]_i_9_n_0\ : STD_LOGIC; signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \y_int[11]_i_100_n_0\ : STD_LOGIC; signal \y_int[11]_i_10_n_0\ : STD_LOGIC; signal \y_int[11]_i_12_n_0\ : STD_LOGIC; signal \y_int[11]_i_16_n_0\ : STD_LOGIC; signal \y_int[11]_i_19_n_0\ : STD_LOGIC; signal \y_int[11]_i_29_n_0\ : STD_LOGIC; signal \y_int[11]_i_2_n_0\ : STD_LOGIC; signal \y_int[11]_i_30_n_0\ : STD_LOGIC; signal \y_int[11]_i_31_n_0\ : STD_LOGIC; signal \y_int[11]_i_32_n_0\ : STD_LOGIC; signal \y_int[11]_i_34_n_0\ : STD_LOGIC; signal \y_int[11]_i_35_n_0\ : STD_LOGIC; signal \y_int[11]_i_36_n_0\ : STD_LOGIC; signal \y_int[11]_i_37_n_0\ : STD_LOGIC; signal \y_int[11]_i_3_n_0\ : STD_LOGIC; signal \y_int[11]_i_40_n_0\ : STD_LOGIC; signal \y_int[11]_i_41_n_0\ : STD_LOGIC; signal \y_int[11]_i_42_n_0\ : STD_LOGIC; signal \y_int[11]_i_43_n_0\ : STD_LOGIC; signal \y_int[11]_i_45_n_0\ : STD_LOGIC; signal \y_int[11]_i_46_n_0\ : STD_LOGIC; signal \y_int[11]_i_47_n_0\ : STD_LOGIC; signal \y_int[11]_i_48_n_0\ : STD_LOGIC; signal \y_int[11]_i_4_n_0\ : STD_LOGIC; signal \y_int[11]_i_50_n_0\ : STD_LOGIC; signal \y_int[11]_i_51_n_0\ : STD_LOGIC; signal \y_int[11]_i_52_n_0\ : STD_LOGIC; signal \y_int[11]_i_53_n_0\ : STD_LOGIC; signal \y_int[11]_i_58_n_0\ : STD_LOGIC; signal \y_int[11]_i_59_n_0\ : STD_LOGIC; signal \y_int[11]_i_5_n_0\ : STD_LOGIC; signal \y_int[11]_i_60_n_0\ : STD_LOGIC; signal \y_int[11]_i_61_n_0\ : STD_LOGIC; signal \y_int[11]_i_62_n_0\ : STD_LOGIC; signal \y_int[11]_i_63_n_0\ : STD_LOGIC; signal \y_int[11]_i_64_n_0\ : STD_LOGIC; signal \y_int[11]_i_65_n_0\ : STD_LOGIC; signal \y_int[11]_i_66_n_0\ : STD_LOGIC; signal \y_int[11]_i_67_n_0\ : STD_LOGIC; signal \y_int[11]_i_68_n_0\ : STD_LOGIC; signal \y_int[11]_i_69_n_0\ : STD_LOGIC; signal \y_int[11]_i_6_n_0\ : STD_LOGIC; signal \y_int[11]_i_70_n_0\ : STD_LOGIC; signal \y_int[11]_i_71_n_0\ : STD_LOGIC; signal \y_int[11]_i_72_n_0\ : STD_LOGIC; signal \y_int[11]_i_73_n_0\ : STD_LOGIC; signal \y_int[11]_i_74_n_0\ : STD_LOGIC; signal \y_int[11]_i_75_n_0\ : STD_LOGIC; signal \y_int[11]_i_76_n_0\ : STD_LOGIC; signal \y_int[11]_i_77_n_0\ : STD_LOGIC; signal \y_int[11]_i_78_n_0\ : STD_LOGIC; signal \y_int[11]_i_79_n_0\ : STD_LOGIC; signal \y_int[11]_i_7_n_0\ : STD_LOGIC; signal \y_int[11]_i_81_n_0\ : STD_LOGIC; signal \y_int[11]_i_82_n_0\ : STD_LOGIC; signal \y_int[11]_i_83_n_0\ : STD_LOGIC; signal \y_int[11]_i_84_n_0\ : STD_LOGIC; signal \y_int[11]_i_86_n_0\ : STD_LOGIC; signal \y_int[11]_i_87_n_0\ : STD_LOGIC; signal \y_int[11]_i_88_n_0\ : STD_LOGIC; signal \y_int[11]_i_89_n_0\ : STD_LOGIC; signal \y_int[11]_i_8_n_0\ : STD_LOGIC; signal \y_int[11]_i_90_n_0\ : STD_LOGIC; signal \y_int[11]_i_91_n_0\ : STD_LOGIC; signal \y_int[11]_i_92_n_0\ : STD_LOGIC; signal \y_int[11]_i_93_n_0\ : STD_LOGIC; signal \y_int[11]_i_94_n_0\ : STD_LOGIC; signal \y_int[11]_i_95_n_0\ : STD_LOGIC; signal \y_int[11]_i_96_n_0\ : STD_LOGIC; signal \y_int[11]_i_97_n_0\ : STD_LOGIC; signal \y_int[11]_i_98_n_0\ : STD_LOGIC; signal \y_int[11]_i_99_n_0\ : STD_LOGIC; signal \y_int[11]_i_9_n_0\ : STD_LOGIC; signal \y_int[15]_i_10_n_0\ : STD_LOGIC; signal \y_int[15]_i_12_n_0\ : STD_LOGIC; signal \y_int[15]_i_16_n_0\ : STD_LOGIC; signal \y_int[15]_i_18_n_0\ : STD_LOGIC; signal \y_int[15]_i_25_n_0\ : STD_LOGIC; signal \y_int[15]_i_26_n_0\ : STD_LOGIC; signal \y_int[15]_i_27_n_0\ : STD_LOGIC; signal \y_int[15]_i_28_n_0\ : STD_LOGIC; signal \y_int[15]_i_29_n_0\ : STD_LOGIC; signal \y_int[15]_i_2_n_0\ : STD_LOGIC; signal \y_int[15]_i_30_n_0\ : STD_LOGIC; signal \y_int[15]_i_31_n_0\ : STD_LOGIC; signal \y_int[15]_i_32_n_0\ : STD_LOGIC; signal \y_int[15]_i_3_n_0\ : STD_LOGIC; signal \y_int[15]_i_40_n_0\ : STD_LOGIC; signal \y_int[15]_i_41_n_0\ : STD_LOGIC; signal \y_int[15]_i_42_n_0\ : STD_LOGIC; signal \y_int[15]_i_43_n_0\ : STD_LOGIC; signal \y_int[15]_i_48_n_0\ : STD_LOGIC; signal \y_int[15]_i_49_n_0\ : STD_LOGIC; signal \y_int[15]_i_4_n_0\ : STD_LOGIC; signal \y_int[15]_i_50_n_0\ : STD_LOGIC; signal \y_int[15]_i_51_n_0\ : STD_LOGIC; signal \y_int[15]_i_5_n_0\ : STD_LOGIC; signal \y_int[15]_i_6_n_0\ : STD_LOGIC; signal \y_int[15]_i_7_n_0\ : STD_LOGIC; signal \y_int[15]_i_8_n_0\ : STD_LOGIC; signal \y_int[15]_i_9_n_0\ : STD_LOGIC; signal \y_int[19]_i_10_n_0\ : STD_LOGIC; signal \y_int[19]_i_12_n_0\ : STD_LOGIC; signal \y_int[19]_i_16_n_0\ : STD_LOGIC; signal \y_int[19]_i_18_n_0\ : STD_LOGIC; signal \y_int[19]_i_25_n_0\ : STD_LOGIC; signal \y_int[19]_i_26_n_0\ : STD_LOGIC; signal \y_int[19]_i_27_n_0\ : STD_LOGIC; signal \y_int[19]_i_28_n_0\ : STD_LOGIC; signal \y_int[19]_i_29_n_0\ : STD_LOGIC; signal \y_int[19]_i_2_n_0\ : STD_LOGIC; signal \y_int[19]_i_30_n_0\ : STD_LOGIC; signal \y_int[19]_i_31_n_0\ : STD_LOGIC; signal \y_int[19]_i_32_n_0\ : STD_LOGIC; signal \y_int[19]_i_3_n_0\ : STD_LOGIC; signal \y_int[19]_i_48_n_0\ : STD_LOGIC; signal \y_int[19]_i_49_n_0\ : STD_LOGIC; signal \y_int[19]_i_4_n_0\ : STD_LOGIC; signal \y_int[19]_i_50_n_0\ : STD_LOGIC; signal \y_int[19]_i_51_n_0\ : STD_LOGIC; signal \y_int[19]_i_5_n_0\ : STD_LOGIC; signal \y_int[19]_i_6_n_0\ : STD_LOGIC; signal \y_int[19]_i_7_n_0\ : STD_LOGIC; signal \y_int[19]_i_8_n_0\ : STD_LOGIC; signal \y_int[19]_i_9_n_0\ : STD_LOGIC; signal \y_int[23]_i_100_n_0\ : STD_LOGIC; signal \y_int[23]_i_101_n_0\ : STD_LOGIC; signal \y_int[23]_i_102_n_0\ : STD_LOGIC; signal \y_int[23]_i_103_n_0\ : STD_LOGIC; signal \y_int[23]_i_104_n_0\ : STD_LOGIC; signal \y_int[23]_i_12_n_0\ : STD_LOGIC; signal \y_int[23]_i_14_n_0\ : STD_LOGIC; signal \y_int[23]_i_18_n_0\ : STD_LOGIC; signal \y_int[23]_i_20_n_0\ : STD_LOGIC; signal \y_int[23]_i_26_n_0\ : STD_LOGIC; signal \y_int[23]_i_27_n_0\ : STD_LOGIC; signal \y_int[23]_i_28_n_0\ : STD_LOGIC; signal \y_int[23]_i_29_n_0\ : STD_LOGIC; signal \y_int[23]_i_2_n_0\ : STD_LOGIC; signal \y_int[23]_i_30_n_0\ : STD_LOGIC; signal \y_int[23]_i_31_n_0\ : STD_LOGIC; signal \y_int[23]_i_36_n_0\ : STD_LOGIC; signal \y_int[23]_i_37_n_0\ : STD_LOGIC; signal \y_int[23]_i_38_n_0\ : STD_LOGIC; signal \y_int[23]_i_39_n_0\ : STD_LOGIC; signal \y_int[23]_i_3_n_0\ : STD_LOGIC; signal \y_int[23]_i_40_n_0\ : STD_LOGIC; signal \y_int[23]_i_41_n_0\ : STD_LOGIC; signal \y_int[23]_i_42_n_0\ : STD_LOGIC; signal \y_int[23]_i_43_n_0\ : STD_LOGIC; signal \y_int[23]_i_46_n_0\ : STD_LOGIC; signal \y_int[23]_i_47_n_0\ : STD_LOGIC; signal \y_int[23]_i_48_n_0\ : STD_LOGIC; signal \y_int[23]_i_49_n_0\ : STD_LOGIC; signal \y_int[23]_i_4_n_0\ : STD_LOGIC; signal \y_int[23]_i_52_n_0\ : STD_LOGIC; signal \y_int[23]_i_53_n_0\ : STD_LOGIC; signal \y_int[23]_i_54_n_0\ : STD_LOGIC; signal \y_int[23]_i_55_n_0\ : STD_LOGIC; signal \y_int[23]_i_56_n_0\ : STD_LOGIC; signal \y_int[23]_i_57_n_0\ : STD_LOGIC; signal \y_int[23]_i_5_n_0\ : STD_LOGIC; signal \y_int[23]_i_62_n_0\ : STD_LOGIC; signal \y_int[23]_i_63_n_0\ : STD_LOGIC; signal \y_int[23]_i_64_n_0\ : STD_LOGIC; signal \y_int[23]_i_65_n_0\ : STD_LOGIC; signal \y_int[23]_i_67_n_0\ : STD_LOGIC; signal \y_int[23]_i_68_n_0\ : STD_LOGIC; signal \y_int[23]_i_69_n_0\ : STD_LOGIC; signal \y_int[23]_i_6_n_0\ : STD_LOGIC; signal \y_int[23]_i_70_n_0\ : STD_LOGIC; signal \y_int[23]_i_71_n_0\ : STD_LOGIC; signal \y_int[23]_i_72_n_0\ : STD_LOGIC; signal \y_int[23]_i_73_n_0\ : STD_LOGIC; signal \y_int[23]_i_74_n_0\ : STD_LOGIC; signal \y_int[23]_i_76_n_0\ : STD_LOGIC; signal \y_int[23]_i_77_n_0\ : STD_LOGIC; signal \y_int[23]_i_78_n_0\ : STD_LOGIC; signal \y_int[23]_i_79_n_0\ : STD_LOGIC; signal \y_int[23]_i_7_n_0\ : STD_LOGIC; signal \y_int[23]_i_80_n_0\ : STD_LOGIC; signal \y_int[23]_i_81_n_0\ : STD_LOGIC; signal \y_int[23]_i_82_n_0\ : STD_LOGIC; signal \y_int[23]_i_83_n_0\ : STD_LOGIC; signal \y_int[23]_i_84_n_0\ : STD_LOGIC; signal \y_int[23]_i_85_n_0\ : STD_LOGIC; signal \y_int[23]_i_86_n_0\ : STD_LOGIC; signal \y_int[23]_i_87_n_0\ : STD_LOGIC; signal \y_int[23]_i_88_n_0\ : STD_LOGIC; signal \y_int[23]_i_8_n_0\ : STD_LOGIC; signal \y_int[23]_i_90_n_0\ : STD_LOGIC; signal \y_int[23]_i_91_n_0\ : STD_LOGIC; signal \y_int[23]_i_92_n_0\ : STD_LOGIC; signal \y_int[23]_i_93_n_0\ : STD_LOGIC; signal \y_int[23]_i_94_n_0\ : STD_LOGIC; signal \y_int[23]_i_95_n_0\ : STD_LOGIC; signal \y_int[23]_i_96_n_0\ : STD_LOGIC; signal \y_int[23]_i_97_n_0\ : STD_LOGIC; signal \y_int[23]_i_98_n_0\ : STD_LOGIC; signal \y_int[23]_i_99_n_0\ : STD_LOGIC; signal \y_int[23]_i_9_n_0\ : STD_LOGIC; signal \y_int[27]_i_2_n_0\ : STD_LOGIC; signal \y_int[27]_i_3_n_0\ : STD_LOGIC; signal \y_int[27]_i_4_n_0\ : STD_LOGIC; signal \y_int[27]_i_5_n_0\ : STD_LOGIC; signal \y_int[31]_i_101_n_0\ : STD_LOGIC; signal \y_int[31]_i_104_n_0\ : STD_LOGIC; signal \y_int[31]_i_105_n_0\ : STD_LOGIC; signal \y_int[31]_i_106_n_0\ : STD_LOGIC; signal \y_int[31]_i_107_n_0\ : STD_LOGIC; signal \y_int[31]_i_108_n_0\ : STD_LOGIC; signal \y_int[31]_i_109_n_0\ : STD_LOGIC; signal \y_int[31]_i_110_n_0\ : STD_LOGIC; signal \y_int[31]_i_111_n_0\ : STD_LOGIC; signal \y_int[31]_i_112_n_0\ : STD_LOGIC; signal \y_int[31]_i_113_n_0\ : STD_LOGIC; signal \y_int[31]_i_114_n_0\ : STD_LOGIC; signal \y_int[31]_i_115_n_0\ : STD_LOGIC; signal \y_int[31]_i_116_n_0\ : STD_LOGIC; signal \y_int[31]_i_13_n_0\ : STD_LOGIC; signal \y_int[31]_i_14_n_0\ : STD_LOGIC; signal \y_int[31]_i_15_n_0\ : STD_LOGIC; signal \y_int[31]_i_17_n_0\ : STD_LOGIC; signal \y_int[31]_i_18_n_0\ : STD_LOGIC; signal \y_int[31]_i_19_n_0\ : STD_LOGIC; signal \y_int[31]_i_20_n_0\ : STD_LOGIC; signal \y_int[31]_i_2_n_0\ : STD_LOGIC; signal \y_int[31]_i_32_n_0\ : STD_LOGIC; signal \y_int[31]_i_33_n_0\ : STD_LOGIC; signal \y_int[31]_i_34_n_0\ : STD_LOGIC; signal \y_int[31]_i_35_n_0\ : STD_LOGIC; signal \y_int[31]_i_36_n_0\ : STD_LOGIC; signal \y_int[31]_i_3_n_0\ : STD_LOGIC; signal \y_int[31]_i_40_n_0\ : STD_LOGIC; signal \y_int[31]_i_41_n_0\ : STD_LOGIC; signal \y_int[31]_i_42_n_0\ : STD_LOGIC; signal \y_int[31]_i_43_n_0\ : STD_LOGIC; signal \y_int[31]_i_44_n_0\ : STD_LOGIC; signal \y_int[31]_i_45_n_0\ : STD_LOGIC; signal \y_int[31]_i_46_n_0\ : STD_LOGIC; signal \y_int[31]_i_47_n_0\ : STD_LOGIC; signal \y_int[31]_i_4_n_0\ : STD_LOGIC; signal \y_int[31]_i_5_n_0\ : STD_LOGIC; signal \y_int[31]_i_63_n_0\ : STD_LOGIC; signal \y_int[31]_i_64_n_0\ : STD_LOGIC; signal \y_int[31]_i_65_n_0\ : STD_LOGIC; signal \y_int[31]_i_66_n_0\ : STD_LOGIC; signal \y_int[31]_i_67_n_0\ : STD_LOGIC; signal \y_int[31]_i_68_n_0\ : STD_LOGIC; signal \y_int[31]_i_69_n_0\ : STD_LOGIC; signal \y_int[31]_i_6_n_0\ : STD_LOGIC; signal \y_int[31]_i_70_n_0\ : STD_LOGIC; signal \y_int[31]_i_89_n_0\ : STD_LOGIC; signal \y_int[31]_i_90_n_0\ : STD_LOGIC; signal \y_int[31]_i_91_n_0\ : STD_LOGIC; signal \y_int[31]_i_92_n_0\ : STD_LOGIC; signal \y_int[3]_i_10_n_0\ : STD_LOGIC; signal \y_int[3]_i_13_n_0\ : STD_LOGIC; signal \y_int[3]_i_17_n_0\ : STD_LOGIC; signal \y_int[3]_i_18_n_0\ : STD_LOGIC; signal \y_int[3]_i_22_n_0\ : STD_LOGIC; signal \y_int[3]_i_23_n_0\ : STD_LOGIC; signal \y_int[3]_i_24_n_0\ : STD_LOGIC; signal \y_int[3]_i_25_n_0\ : STD_LOGIC; signal \y_int[3]_i_27_n_0\ : STD_LOGIC; signal \y_int[3]_i_28_n_0\ : STD_LOGIC; signal \y_int[3]_i_29_n_0\ : STD_LOGIC; signal \y_int[3]_i_2_n_0\ : STD_LOGIC; signal \y_int[3]_i_31_n_0\ : STD_LOGIC; signal \y_int[3]_i_32_n_0\ : STD_LOGIC; signal \y_int[3]_i_33_n_0\ : STD_LOGIC; signal \y_int[3]_i_34_n_0\ : STD_LOGIC; signal \y_int[3]_i_3_n_0\ : STD_LOGIC; signal \y_int[3]_i_4_n_0\ : STD_LOGIC; signal \y_int[3]_i_50_n_0\ : STD_LOGIC; signal \y_int[3]_i_51_n_0\ : STD_LOGIC; signal \y_int[3]_i_52_n_0\ : STD_LOGIC; signal \y_int[3]_i_53_n_0\ : STD_LOGIC; signal \y_int[3]_i_54_n_0\ : STD_LOGIC; signal \y_int[3]_i_56_n_0\ : STD_LOGIC; signal \y_int[3]_i_57_n_0\ : STD_LOGIC; signal \y_int[3]_i_58_n_0\ : STD_LOGIC; signal \y_int[3]_i_59_n_0\ : STD_LOGIC; signal \y_int[3]_i_5_n_0\ : STD_LOGIC; signal \y_int[3]_i_60_n_0\ : STD_LOGIC; signal \y_int[3]_i_61_n_0\ : STD_LOGIC; signal \y_int[3]_i_62_n_0\ : STD_LOGIC; signal \y_int[3]_i_63_n_0\ : STD_LOGIC; signal \y_int[3]_i_66_n_0\ : STD_LOGIC; signal \y_int[3]_i_67_n_0\ : STD_LOGIC; signal \y_int[3]_i_68_n_0\ : STD_LOGIC; signal \y_int[3]_i_69_n_0\ : STD_LOGIC; signal \y_int[3]_i_6_n_0\ : STD_LOGIC; signal \y_int[3]_i_71_n_0\ : STD_LOGIC; signal \y_int[3]_i_72_n_0\ : STD_LOGIC; signal \y_int[3]_i_73_n_0\ : STD_LOGIC; signal \y_int[3]_i_74_n_0\ : STD_LOGIC; signal \y_int[3]_i_7_n_0\ : STD_LOGIC; signal \y_int[3]_i_84_n_0\ : STD_LOGIC; signal \y_int[3]_i_85_n_0\ : STD_LOGIC; signal \y_int[3]_i_86_n_0\ : STD_LOGIC; signal \y_int[3]_i_87_n_0\ : STD_LOGIC; signal \y_int[3]_i_88_n_0\ : STD_LOGIC; signal \y_int[3]_i_89_n_0\ : STD_LOGIC; signal \y_int[3]_i_8_n_0\ : STD_LOGIC; signal \y_int[3]_i_90_n_0\ : STD_LOGIC; signal \y_int[3]_i_91_n_0\ : STD_LOGIC; signal \y_int[3]_i_92_n_0\ : STD_LOGIC; signal \y_int[7]_i_11_n_0\ : STD_LOGIC; signal \y_int[7]_i_13_n_0\ : STD_LOGIC; signal \y_int[7]_i_16_n_0\ : STD_LOGIC; signal \y_int[7]_i_19_n_0\ : STD_LOGIC; signal \y_int[7]_i_29_n_0\ : STD_LOGIC; signal \y_int[7]_i_2_n_0\ : STD_LOGIC; signal \y_int[7]_i_30_n_0\ : STD_LOGIC; signal \y_int[7]_i_31_n_0\ : STD_LOGIC; signal \y_int[7]_i_32_n_0\ : STD_LOGIC; signal \y_int[7]_i_33_n_0\ : STD_LOGIC; signal \y_int[7]_i_3_n_0\ : STD_LOGIC; signal \y_int[7]_i_4_n_0\ : STD_LOGIC; signal \y_int[7]_i_5_n_0\ : STD_LOGIC; signal \y_int[7]_i_6_n_0\ : STD_LOGIC; signal \y_int[7]_i_7_n_0\ : STD_LOGIC; signal \y_int[7]_i_8_n_0\ : STD_LOGIC; signal \y_int[7]_i_9_n_0\ : STD_LOGIC; signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 ); signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 ); signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 ); signal y_int_reg6 : STD_LOGIC; signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC; signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC; signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC; signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC; signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC; signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC; signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC; signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC; signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC; signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC; signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \y_int_reg_n_0_[0]\ : STD_LOGIC; signal \y_int_reg_n_0_[1]\ : STD_LOGIC; signal \y_int_reg_n_0_[2]\ : STD_LOGIC; signal \y_int_reg_n_0_[3]\ : STD_LOGIC; signal \y_int_reg_n_0_[4]\ : STD_LOGIC; signal \y_int_reg_n_0_[5]\ : STD_LOGIC; signal \y_int_reg_n_0_[6]\ : STD_LOGIC; signal \y_int_reg_n_0_[7]\ : STD_LOGIC; signal \y_reg[7]_i_12_n_0\ : STD_LOGIC; signal \y_reg[7]_i_12_n_1\ : STD_LOGIC; signal \y_reg[7]_i_12_n_2\ : STD_LOGIC; signal \y_reg[7]_i_12_n_3\ : STD_LOGIC; signal \y_reg[7]_i_1_n_0\ : STD_LOGIC; signal \y_reg[7]_i_1_n_1\ : STD_LOGIC; signal \y_reg[7]_i_1_n_2\ : STD_LOGIC; signal \y_reg[7]_i_1_n_3\ : STD_LOGIC; signal \y_reg[7]_i_3_n_0\ : STD_LOGIC; signal \y_reg[7]_i_3_n_1\ : STD_LOGIC; signal \y_reg[7]_i_3_n_2\ : STD_LOGIC; signal \y_reg[7]_i_3_n_3\ : STD_LOGIC; signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC; signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC; signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute \__SRVAL\ : string; attribute \__SRVAL\ of ODDR_inst : label is "TRUE"; attribute box_type : string; attribute box_type of ODDR_inst : label is "PRIMITIVE"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34"; attribute HLUTNM : string; attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8"; attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7"; attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6"; attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9"; attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8"; attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7"; attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6"; attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12"; attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11"; attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10"; attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9"; attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13"; attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12"; attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11"; attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10"; attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16"; attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15"; attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14"; attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13"; attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17"; attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16"; attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15"; attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14"; attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20"; attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19"; attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19"; attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18"; attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17"; attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21"; attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20"; attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19"; attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18"; attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21"; attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18"; attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2"; attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1"; attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair39"; attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3"; attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2"; attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1"; attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair39"; attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5"; attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4"; attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3"; attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5"; attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4"; attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair26"; attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29"; attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20"; attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29"; attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair30"; attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair30"; attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair31"; attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair31"; attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair32"; attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair32"; attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20"; attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23"; attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23"; attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25"; attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24"; attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22"; attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22"; attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair40"; attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26"; attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25"; attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24"; attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair40"; attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28"; attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27"; attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26"; attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28"; attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27"; attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21"; attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair35"; attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair34"; attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair33"; attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair36"; attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair35"; attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair34"; attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair33"; attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair38"; attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair37"; attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair36"; attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair38"; attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair37"; begin CO(0) <= \^co\(0); DI(0) <= \^di\(0); O(1 downto 0) <= \^o\(1 downto 0); \cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0); \cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0); \cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0); \cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0); \cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0); \cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0); \cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\; \cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0); \cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0); \cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\; \cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\; \cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0); \cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0); \cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0); \cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0); \cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0); \cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0); \y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0); \y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0); \y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0); \y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0); \y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0); \y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0); \y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0); \y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0); Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender port map ( clk_100 => clk_100, hdmi_scl => hdmi_scl, hdmi_sda => hdmi_sda ); ODDR_inst: unisim.vcomponents.ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0', IS_C_INVERTED => '0', IS_D1_INVERTED => '0', IS_D2_INVERTED => '0', SRTYPE => "SYNC" ) port map ( C => clk_x2, CE => '1', D1 => D1, D2 => D1, Q => hdmi_clk, R => NLW_ODDR_inst_R_UNCONNECTED, S => NLW_ODDR_inst_S_UNCONNECTED ); \cb[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[0]\, I1 => \cb_int_reg__0\(31), O => \cb[0]_i_1_n_0\ ); \cb[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[1]\, I1 => \cb_int_reg__0\(31), O => \cb[1]_i_1_n_0\ ); \cb[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[2]\, I1 => \cb_int_reg__0\(31), O => \cb[2]_i_1_n_0\ ); \cb[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[3]\, I1 => \cb_int_reg__0\(31), O => \cb[3]_i_1_n_0\ ); \cb[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[4]\, I1 => \cb_int_reg__0\(31), O => \cb[4]_i_1_n_0\ ); \cb[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[5]\, I1 => \cb_int_reg__0\(31), O => \cb[5]_i_1_n_0\ ); \cb[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[6]\, I1 => \cb_int_reg__0\(31), O => \cb[6]_i_1_n_0\ ); \cb[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(26), I1 => \cb_int_reg__0\(27), O => \cb[7]_i_10_n_0\ ); \cb[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(24), I1 => \cb_int_reg__0\(25), O => \cb[7]_i_11_n_0\ ); \cb[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(22), I1 => \cb_int_reg__0\(23), O => \cb[7]_i_13_n_0\ ); \cb[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(20), I1 => \cb_int_reg__0\(21), O => \cb[7]_i_14_n_0\ ); \cb[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(18), I1 => \cb_int_reg__0\(19), O => \cb[7]_i_15_n_0\ ); \cb[7]_i_16\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(16), I1 => \cb_int_reg__0\(17), O => \cb[7]_i_16_n_0\ ); \cb[7]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(22), I1 => \cb_int_reg__0\(23), O => \cb[7]_i_17_n_0\ ); \cb[7]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(20), I1 => \cb_int_reg__0\(21), O => \cb[7]_i_18_n_0\ ); \cb[7]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(18), I1 => \cb_int_reg__0\(19), O => \cb[7]_i_19_n_0\ ); \cb[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[7]\, I1 => \cb_int_reg__0\(31), O => \cb[7]_i_2_n_0\ ); \cb[7]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(16), I1 => \cb_int_reg__0\(17), O => \cb[7]_i_20_n_0\ ); \cb[7]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(14), I1 => \cb_int_reg__0\(15), O => \cb[7]_i_21_n_0\ ); \cb[7]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(12), I1 => \cb_int_reg__0\(13), O => \cb[7]_i_22_n_0\ ); \cb[7]_i_23\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(10), I1 => \cb_int_reg__0\(11), O => \cb[7]_i_23_n_0\ ); \cb[7]_i_24\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(8), I1 => \cb_int_reg__0\(9), O => \cb[7]_i_24_n_0\ ); \cb[7]_i_25\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(14), I1 => \cb_int_reg__0\(15), O => \cb[7]_i_25_n_0\ ); \cb[7]_i_26\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(12), I1 => \cb_int_reg__0\(13), O => \cb[7]_i_26_n_0\ ); \cb[7]_i_27\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(10), I1 => \cb_int_reg__0\(11), O => \cb[7]_i_27_n_0\ ); \cb[7]_i_28\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(8), I1 => \cb_int_reg__0\(9), O => \cb[7]_i_28_n_0\ ); \cb[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg__0\(30), I1 => \cb_int_reg__0\(31), O => \cb[7]_i_4_n_0\ ); \cb[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(28), I1 => \cb_int_reg__0\(29), O => \cb[7]_i_5_n_0\ ); \cb[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(26), I1 => \cb_int_reg__0\(27), O => \cb[7]_i_6_n_0\ ); \cb[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(24), I1 => \cb_int_reg__0\(25), O => \cb[7]_i_7_n_0\ ); \cb[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(30), I1 => \cb_int_reg__0\(31), O => \cb[7]_i_8_n_0\ ); \cb[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(28), I1 => \cb_int_reg__0\(29), O => \cb[7]_i_9_n_0\ ); \cb_hold[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => edge, I1 => edge_rb, O => \cb_hold[7]_i_1_n_0\ ); \cb_hold_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(0), Q => cb_hold(0), R => '0' ); \cb_hold_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(1), Q => cb_hold(1), R => '0' ); \cb_hold_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(2), Q => cb_hold(2), R => '0' ); \cb_hold_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(3), Q => cb_hold(3), R => '0' ); \cb_hold_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(4), Q => cb_hold(4), R => '0' ); \cb_hold_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(5), Q => cb_hold(5), R => '0' ); \cb_hold_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(6), Q => cb_hold(6), R => '0' ); \cb_hold_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(7), Q => cb_hold(7), R => '0' ); \cb_int[11]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(10), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(18), I3 => cb_int_reg8, I4 => \cb_int[15]_i_25_n_0\, I5 => cb_int_reg2(10), O => \cb_int[11]_i_10_n_0\ ); \cb_int[11]_i_100\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_16_n_6\, I1 => \cb_int_reg[3]_i_16_n_5\, O => \cb_int[11]_i_100_n_0\ ); \cb_int[11]_i_101\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_26_n_4\, I1 => \cb_int_reg[3]_i_16_n_7\, O => \cb_int[11]_i_101_n_0\ ); \cb_int[11]_i_102\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_26_n_6\, I1 => \cb_int_reg[3]_i_26_n_5\, O => \cb_int[11]_i_102_n_0\ ); \cb_int[11]_i_103\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_7\, I1 => \cb_int_reg[3]_i_16_n_4\, O => \cb_int[11]_i_103_n_0\ ); \cb_int[11]_i_104\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_5\, I1 => \cb_int_reg[3]_i_16_n_6\, O => \cb_int[11]_i_104_n_0\ ); \cb_int[11]_i_105\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_7\, I1 => \cb_int_reg[3]_i_26_n_4\, O => \cb_int[11]_i_105_n_0\ ); \cb_int[11]_i_106\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_26_n_5\, I1 => \cb_int_reg[3]_i_26_n_6\, O => \cb_int[11]_i_106_n_0\ ); \cb_int[11]_i_107\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_20_n_7\, I1 => \cb_int_reg[3]_i_20_n_6\, O => \cb_int[11]_i_107_n_0\ ); \cb_int[11]_i_108\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_44_n_7\, I1 => \cb_int_reg[3]_i_44_n_6\, O => \cb_int[11]_i_108_n_0\ ); \cb_int[11]_i_109\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_75_n_5\, I1 => \cb_int_reg[3]_i_75_n_4\, O => \cb_int[11]_i_109_n_0\ ); \cb_int[11]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(9), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(17), I3 => cb_int_reg8, I4 => \cb_int[11]_i_20_n_0\, I5 => cb_int_reg2(9), O => \cb_int[11]_i_11_n_0\ ); \cb_int[11]_i_110\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_75_n_7\, I1 => \cb_int_reg[3]_i_75_n_6\, O => \cb_int[11]_i_110_n_0\ ); \cb_int[11]_i_111\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_6\, I1 => \cb_int_reg[3]_i_20_n_7\, O => \cb_int[11]_i_111_n_0\ ); \cb_int[11]_i_112\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_44_n_6\, I1 => \cb_int_reg[3]_i_44_n_7\, O => \cb_int[11]_i_112_n_0\ ); \cb_int[11]_i_113\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_4\, I1 => \cb_int_reg[3]_i_75_n_5\, O => \cb_int[11]_i_113_n_0\ ); \cb_int[11]_i_114\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_6\, I1 => \cb_int_reg[3]_i_75_n_7\, O => \cb_int[11]_i_114_n_0\ ); \cb_int[11]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(9), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(17), I3 => cb_int_reg8, I4 => \cb_int[11]_i_20_n_0\, I5 => cb_int_reg2(9), O => \cb_int[11]_i_12_n_0\ ); \cb_int[11]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(8), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(16), I3 => cb_int_reg8, I4 => \cb_int[11]_i_22_n_0\, I5 => cb_int_reg2(8), O => \cb_int[11]_i_13_n_0\ ); \cb_int[11]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(8), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(16), I3 => cb_int_reg8, I4 => \cb_int[11]_i_22_n_0\, I5 => cb_int_reg2(8), O => \cb_int[11]_i_14_n_0\ ); \cb_int[11]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFE200E2" ) port map ( I0 => \cb_int_reg[11]_i_24_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(1), I3 => \rgb888[0]\(3), I4 => cb_int_reg3(7), I5 => \cb_int[11]_i_27_n_0\, O => \cb_int[11]_i_15_n_0\ ); \cb_int[11]_i_19\: unisim.vcomponents.LUT6 generic map( INIT => X"FFE200E2001DFF1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(1), I3 => \rgb888[0]\(3), I4 => cb_int_reg3(7), I5 => \cb_int[11]_i_27_n_0\, O => \cb_int[11]_i_19_n_0\ ); \cb_int[11]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[11]_i_10_n_0\, I1 => \cb_int[11]_i_11_n_0\, O => \cb_int[11]_i_2_n_0\ ); \cb_int[11]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_4\(0), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]_0\(0), O => \cb_int[11]_i_20_n_0\ ); \cb_int[11]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(9), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_4\(0), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(9) ); \cb_int[11]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_3\(3), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]\(3), O => \cb_int[11]_i_22_n_0\ ); \cb_int[11]_i_23\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(8), I1 => \rgb888[0]\(3), I2 => \rgb888[0]\(2), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[11]_i_24_n_4\, O => cb_int_reg2(8) ); \cb_int[11]_i_27\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_3\(2), I1 => \rgb888[8]_1\(1), I2 => \rgb888[12]\(2), I3 => \^co\(0), I4 => \rgb888[8]_1\(0), O => \cb_int[11]_i_27_n_0\ ); \cb_int[11]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(16), O => \cb_int[11]_i_29_n_0\ ); \cb_int[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[11]_i_12_n_0\, I1 => \cb_int[11]_i_13_n_0\, O => \cb_int[11]_i_3_n_0\ ); \cb_int[11]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(15), O => \cb_int[11]_i_30_n_0\ ); \cb_int[11]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(14), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_12_n_6\, O => \cb_int[11]_i_31_n_0\ ); \cb_int[11]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(13), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_12_n_7\, O => \cb_int[11]_i_32_n_0\ ); \cb_int[11]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_34_n_0\ ); \cb_int[11]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_35_n_0\ ); \cb_int[11]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_36_n_0\ ); \cb_int[11]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_37_n_0\ ); \cb_int[11]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_39_n_0\ ); \cb_int[11]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[11]_i_14_n_0\, I1 => \cb_int[11]_i_15_n_0\, O => \cb_int[11]_i_4_n_0\ ); \cb_int[11]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_40_n_0\ ); \cb_int[11]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_41_n_0\ ); \cb_int[11]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_42_n_0\ ); \cb_int[11]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_43_n_0\ ); \cb_int[11]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(2), O => \cb_int[11]_i_44_n_0\ ); \cb_int[11]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(1), O => \cb_int[11]_i_45_n_0\ ); \cb_int[11]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(0), O => \cb_int[11]_i_46_n_0\ ); \cb_int[11]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(3), O => \cb_int[11]_i_47_n_0\ ); \cb_int[11]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_49_n_0\ ); \cb_int[11]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"DD1D0000" ) port map ( I0 => cb_int_reg5(7), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(15), I3 => cb_int_reg8, I4 => \cb_int[11]_i_19_n_0\, O => \cb_int[11]_i_5_n_0\ ); \cb_int[11]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_50_n_0\ ); \cb_int[11]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_51_n_0\ ); \cb_int[11]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_52_n_0\ ); \cb_int[11]_i_53\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_4\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(2), O => \cb_int[11]_i_53_n_0\ ); \cb_int[11]_i_54\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(1), O => \cb_int[11]_i_54_n_0\ ); \cb_int[11]_i_55\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_6\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(0), O => \cb_int[11]_i_55_n_0\ ); \cb_int[11]_i_56\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_7\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_0\(3), O => \cb_int[11]_i_56_n_0\ ); \cb_int[11]_i_57\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(8), I1 => cb_int_reg8, I2 => \cb_int_reg[3]_i_16_n_4\, O => \cb_int[11]_i_57_n_0\ ); \cb_int[11]_i_58\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(12), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_4\, O => \cb_int[11]_i_58_n_0\ ); \cb_int[11]_i_59\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(11), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_5\, O => \cb_int[11]_i_59_n_0\ ); \cb_int[11]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[15]_i_16_n_0\, I1 => \cb_int[15]_i_17_n_0\, I2 => \cb_int[11]_i_2_n_0\, O => \cb_int[11]_i_6_n_0\ ); \cb_int[11]_i_60\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(10), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_6\, O => \cb_int[11]_i_60_n_0\ ); \cb_int[11]_i_61\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(9), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_7\, O => \cb_int[11]_i_61_n_0\ ); \cb_int[11]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_6\, O => \cb_int[11]_i_62_n_0\ ); \cb_int[11]_i_63\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_7\, O => \cb_int[11]_i_63_n_0\ ); \cb_int[11]_i_64\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_4\, O => \cb_int[11]_i_64_n_0\ ); \cb_int[11]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_5\, O => \cb_int[11]_i_65_n_0\ ); \cb_int[11]_i_67\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_67_n_0\ ); \cb_int[11]_i_68\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_68_n_0\ ); \cb_int[11]_i_69\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_69_n_0\ ); \cb_int[11]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[11]_i_10_n_0\, I1 => \cb_int[11]_i_11_n_0\, I2 => \cb_int[11]_i_3_n_0\, O => \cb_int[11]_i_7_n_0\ ); \cb_int[11]_i_70\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_70_n_0\ ); \cb_int[11]_i_71\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_71_n_0\ ); \cb_int[11]_i_72\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_72_n_0\ ); \cb_int[11]_i_73\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_73_n_0\ ); \cb_int[11]_i_74\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_74_n_0\ ); \cb_int[11]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[0]\(2), I1 => \rgb888[0]\(3), O => \cb_int[11]_i_76_n_0\ ); \cb_int[11]_i_77\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_77_n_0\ ); \cb_int[11]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_78_n_0\ ); \cb_int[11]_i_79\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_79_n_0\ ); \cb_int[11]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[11]_i_12_n_0\, I1 => \cb_int[11]_i_13_n_0\, I2 => \cb_int[11]_i_4_n_0\, O => \cb_int[11]_i_8_n_0\ ); \cb_int[11]_i_80\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), I1 => \rgb888[0]\(2), O => \cb_int[11]_i_80_n_0\ ); \cb_int[11]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_82_n_0\ ); \cb_int[11]_i_83\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_6\, I1 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_83_n_0\ ); \cb_int[11]_i_84\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[31]_i_33_n_4\, I1 => \cb_int_reg[31]_i_12_n_7\, O => \cb_int[11]_i_84_n_0\ ); \cb_int[11]_i_85\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[31]_i_33_n_6\, I1 => \cb_int_reg[31]_i_33_n_5\, O => \cb_int[11]_i_85_n_0\ ); \cb_int[11]_i_86\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_86_n_0\ ); \cb_int[11]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => \cb_int_reg[31]_i_12_n_6\, O => \cb_int[11]_i_87_n_0\ ); \cb_int[11]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_7\, I1 => \cb_int_reg[31]_i_33_n_4\, O => \cb_int[11]_i_88_n_0\ ); \cb_int[11]_i_89\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_5\, I1 => \cb_int_reg[31]_i_33_n_6\, O => \cb_int[11]_i_89_n_0\ ); \cb_int[11]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[11]_i_14_n_0\, I1 => \cb_int[11]_i_15_n_0\, I2 => \cb_int[11]_i_5_n_0\, O => \cb_int[11]_i_9_n_0\ ); \cb_int[11]_i_91\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[0]\(0), I1 => \rgb888[0]\(1), O => \cb_int[11]_i_91_n_0\ ); \cb_int[11]_i_92\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[0]_0\(2), I1 => \rgb888[0]_0\(3), O => \cb_int[11]_i_92_n_0\ ); \cb_int[11]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[0]_0\(0), I1 => \rgb888[0]_0\(1), O => \cb_int[11]_i_93_n_0\ ); \cb_int[11]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_20_n_5\, I1 => \cb_int_reg[3]_i_20_n_4\, O => \cb_int[11]_i_94_n_0\ ); \cb_int[11]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(1), I1 => \rgb888[0]\(0), O => \cb_int[11]_i_95_n_0\ ); \cb_int[11]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(3), I1 => \rgb888[0]_0\(2), O => \cb_int[11]_i_96_n_0\ ); \cb_int[11]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(1), I1 => \rgb888[0]_0\(0), O => \cb_int[11]_i_97_n_0\ ); \cb_int[11]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_4\, I1 => \cb_int_reg[3]_i_20_n_5\, O => \cb_int[11]_i_98_n_0\ ); \cb_int[11]_i_99\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_16_n_4\, I1 => \cb_int_reg[31]_i_33_n_7\, O => \cb_int[11]_i_99_n_0\ ); \cb_int[15]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(14), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(22), I3 => cb_int_reg8, I4 => \cb_int[19]_i_26_n_0\, I5 => cb_int_reg2(14), O => \cb_int[15]_i_10_n_0\ ); \cb_int[15]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(13), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(21), I3 => cb_int_reg8, I4 => \cb_int[15]_i_18_n_0\, I5 => cb_int_reg2(13), O => \cb_int[15]_i_11_n_0\ ); \cb_int[15]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(13), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(21), I3 => cb_int_reg8, I4 => \cb_int[15]_i_18_n_0\, I5 => cb_int_reg2(13), O => \cb_int[15]_i_12_n_0\ ); \cb_int[15]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(12), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(20), I3 => cb_int_reg8, I4 => \cb_int[15]_i_21_n_0\, I5 => cb_int_reg2(12), O => \cb_int[15]_i_13_n_0\ ); \cb_int[15]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(12), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(20), I3 => cb_int_reg8, I4 => \cb_int[15]_i_21_n_0\, I5 => cb_int_reg2(12), O => \cb_int[15]_i_14_n_0\ ); \cb_int[15]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(11), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(19), I3 => cb_int_reg8, I4 => \cb_int[15]_i_23_n_0\, I5 => cb_int_reg2(11), O => \cb_int[15]_i_15_n_0\ ); \cb_int[15]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(11), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(19), I3 => cb_int_reg8, I4 => \cb_int[15]_i_23_n_0\, I5 => cb_int_reg2(11), O => \cb_int[15]_i_16_n_0\ ); \cb_int[15]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(10), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(18), I3 => cb_int_reg8, I4 => \cb_int[15]_i_25_n_0\, I5 => cb_int_reg2(10), O => \cb_int[15]_i_17_n_0\ ); \cb_int[15]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_5\(0), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_6\(0), O => \cb_int[15]_i_18_n_0\ ); \cb_int[15]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(13), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_3\(0), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(13) ); \cb_int[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[15]_i_10_n_0\, I1 => \cb_int[15]_i_11_n_0\, O => \cb_int[15]_i_2_n_0\ ); \cb_int[15]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_4\(3), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]_0\(3), O => \cb_int[15]_i_21_n_0\ ); \cb_int[15]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(12), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_4\(3), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(12) ); \cb_int[15]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_4\(2), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]_0\(2), O => \cb_int[15]_i_23_n_0\ ); \cb_int[15]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(11), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_4\(2), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(11) ); \cb_int[15]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_4\(1), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]_0\(1), O => \cb_int[15]_i_25_n_0\ ); \cb_int[15]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(10), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_4\(1), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(10) ); \cb_int[15]_i_27\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(20), O => \cb_int[15]_i_27_n_0\ ); \cb_int[15]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(19), O => \cb_int[15]_i_28_n_0\ ); \cb_int[15]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(18), O => \cb_int[15]_i_29_n_0\ ); \cb_int[15]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[15]_i_12_n_0\, I1 => \cb_int[15]_i_13_n_0\, O => \cb_int[15]_i_3_n_0\ ); \cb_int[15]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(17), O => \cb_int[15]_i_30_n_0\ ); \cb_int[15]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[15]_i_14_n_0\, I1 => \cb_int[15]_i_15_n_0\, O => \cb_int[15]_i_4_n_0\ ); \cb_int[15]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_4\(3), O => \cb_int[15]_i_43_n_0\ ); \cb_int[15]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_4\(2), O => \cb_int[15]_i_44_n_0\ ); \cb_int[15]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_4\(1), O => \cb_int[15]_i_45_n_0\ ); \cb_int[15]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_4\(0), O => \cb_int[15]_i_46_n_0\ ); \cb_int[15]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[15]_i_16_n_0\, I1 => \cb_int[15]_i_17_n_0\, O => \cb_int[15]_i_5_n_0\ ); \cb_int[15]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[19]_i_16_n_0\, I1 => \cb_int[19]_i_17_n_0\, I2 => \cb_int[15]_i_2_n_0\, O => \cb_int[15]_i_6_n_0\ ); \cb_int[15]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[15]_i_10_n_0\, I1 => \cb_int[15]_i_11_n_0\, I2 => \cb_int[15]_i_3_n_0\, O => \cb_int[15]_i_7_n_0\ ); \cb_int[15]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[15]_i_12_n_0\, I1 => \cb_int[15]_i_13_n_0\, I2 => \cb_int[15]_i_4_n_0\, O => \cb_int[15]_i_8_n_0\ ); \cb_int[15]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[15]_i_14_n_0\, I1 => \cb_int[15]_i_15_n_0\, I2 => \cb_int[15]_i_5_n_0\, O => \cb_int[15]_i_9_n_0\ ); \cb_int[19]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(18), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(26), I3 => cb_int_reg8, I4 => \cb_int[23]_i_25_n_0\, I5 => cb_int_reg2(18), O => \cb_int[19]_i_10_n_0\ ); \cb_int[19]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(17), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(25), I3 => cb_int_reg8, I4 => \cb_int[19]_i_18_n_0\, I5 => cb_int_reg2(17), O => \cb_int[19]_i_11_n_0\ ); \cb_int[19]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(17), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(25), I3 => cb_int_reg8, I4 => \cb_int[19]_i_18_n_0\, I5 => cb_int_reg2(17), O => \cb_int[19]_i_12_n_0\ ); \cb_int[19]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(16), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(24), I3 => cb_int_reg8, I4 => \cb_int[19]_i_21_n_0\, I5 => cb_int_reg2(16), O => \cb_int[19]_i_13_n_0\ ); \cb_int[19]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(16), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(24), I3 => cb_int_reg8, I4 => \cb_int[19]_i_21_n_0\, I5 => cb_int_reg2(16), O => \cb_int[19]_i_14_n_0\ ); \cb_int[19]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(15), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(23), I3 => cb_int_reg8, I4 => \cb_int[19]_i_23_n_0\, I5 => cb_int_reg2(15), O => \cb_int[19]_i_15_n_0\ ); \cb_int[19]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(15), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(23), I3 => cb_int_reg8, I4 => \cb_int[19]_i_23_n_0\, I5 => cb_int_reg2(15), O => \cb_int[19]_i_16_n_0\ ); \cb_int[19]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(14), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(22), I3 => cb_int_reg8, I4 => \cb_int[19]_i_26_n_0\, I5 => cb_int_reg2(14), O => \cb_int[19]_i_17_n_0\ ); \cb_int[19]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_7\(0), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_8\(0), O => \cb_int[19]_i_18_n_0\ ); \cb_int[19]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(17), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_2\(0), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(17) ); \cb_int[19]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[19]_i_10_n_0\, I1 => \cb_int[19]_i_11_n_0\, O => \cb_int[19]_i_2_n_0\ ); \cb_int[19]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_5\(3), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_6\(3), O => \cb_int[19]_i_21_n_0\ ); \cb_int[19]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(16), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_3\(3), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(16) ); \cb_int[19]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_5\(2), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_6\(2), O => \cb_int[19]_i_23_n_0\ ); \cb_int[19]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(15), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_3\(2), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(15) ); \cb_int[19]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_5\(1), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_6\(1), O => \cb_int[19]_i_26_n_0\ ); \cb_int[19]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(14), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_3\(1), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(14) ); \cb_int[19]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(24), O => \cb_int[19]_i_28_n_0\ ); \cb_int[19]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(23), O => \cb_int[19]_i_29_n_0\ ); \cb_int[19]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[19]_i_12_n_0\, I1 => \cb_int[19]_i_13_n_0\, O => \cb_int[19]_i_3_n_0\ ); \cb_int[19]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(22), O => \cb_int[19]_i_30_n_0\ ); \cb_int[19]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(21), O => \cb_int[19]_i_31_n_0\ ); \cb_int[19]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[19]_i_34_n_0\ ); \cb_int[19]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[19]_i_35_n_0\ ); \cb_int[19]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[19]_i_36_n_0\ ); \cb_int[19]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[19]_i_37_n_0\ ); \cb_int[19]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[19]_i_14_n_0\, I1 => \cb_int[19]_i_15_n_0\, O => \cb_int[19]_i_4_n_0\ ); \cb_int[19]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[19]_i_16_n_0\, I1 => \cb_int[19]_i_17_n_0\, O => \cb_int[19]_i_5_n_0\ ); \cb_int[19]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[23]_i_16_n_0\, I1 => \cb_int[23]_i_17_n_0\, I2 => \cb_int[19]_i_2_n_0\, O => \cb_int[19]_i_6_n_0\ ); \cb_int[19]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[19]_i_10_n_0\, I1 => \cb_int[19]_i_11_n_0\, I2 => \cb_int[19]_i_3_n_0\, O => \cb_int[19]_i_7_n_0\ ); \cb_int[19]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[19]_i_12_n_0\, I1 => \cb_int[19]_i_13_n_0\, I2 => \cb_int[19]_i_4_n_0\, O => \cb_int[19]_i_8_n_0\ ); \cb_int[19]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[19]_i_14_n_0\, I1 => \cb_int[19]_i_15_n_0\, I2 => \cb_int[19]_i_5_n_0\, O => \cb_int[19]_i_9_n_0\ ); \cb_int[23]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(22), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(30), I3 => cb_int_reg8, I4 => \cb_int[27]_i_10_n_0\, I5 => cb_int_reg2(22), O => \cb_int[23]_i_10_n_0\ ); \cb_int[23]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(21), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(29), I3 => cb_int_reg8, I4 => \cb_int[23]_i_18_n_0\, I5 => cb_int_reg2(21), O => \cb_int[23]_i_11_n_0\ ); \cb_int[23]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(21), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(29), I3 => cb_int_reg8, I4 => \cb_int[23]_i_18_n_0\, I5 => cb_int_reg2(21), O => \cb_int[23]_i_12_n_0\ ); \cb_int[23]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(20), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(28), I3 => cb_int_reg8, I4 => \cb_int[23]_i_20_n_0\, I5 => cb_int_reg2(20), O => \cb_int[23]_i_13_n_0\ ); \cb_int[23]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(20), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(28), I3 => cb_int_reg8, I4 => \cb_int[23]_i_20_n_0\, I5 => cb_int_reg2(20), O => \cb_int[23]_i_14_n_0\ ); \cb_int[23]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(19), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(27), I3 => cb_int_reg8, I4 => \cb_int[23]_i_22_n_0\, I5 => cb_int_reg2(19), O => \cb_int[23]_i_15_n_0\ ); \cb_int[23]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(19), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(27), I3 => cb_int_reg8, I4 => \cb_int[23]_i_22_n_0\, I5 => cb_int_reg2(19), O => \cb_int[23]_i_16_n_0\ ); \cb_int[23]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(18), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(26), I3 => cb_int_reg8, I4 => \cb_int[23]_i_25_n_0\, I5 => cb_int_reg2(18), O => \cb_int[23]_i_17_n_0\ ); \cb_int[23]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_9\(0), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_10\(0), O => \cb_int[23]_i_18_n_0\ ); \cb_int[23]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(21), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_1\(0), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(21) ); \cb_int[23]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[23]_i_10_n_0\, I1 => \cb_int[23]_i_11_n_0\, O => \cb_int[23]_i_2_n_0\ ); \cb_int[23]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_7\(3), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_8\(3), O => \cb_int[23]_i_20_n_0\ ); \cb_int[23]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(20), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_2\(3), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(20) ); \cb_int[23]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_7\(2), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_8\(2), O => \cb_int[23]_i_22_n_0\ ); \cb_int[23]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(19), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_2\(2), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(19) ); \cb_int[23]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_7\(1), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_8\(1), O => \cb_int[23]_i_25_n_0\ ); \cb_int[23]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(18), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_2\(1), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(18) ); \cb_int[23]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[23]_i_29_n_0\ ); \cb_int[23]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[23]_i_12_n_0\, I1 => \cb_int[23]_i_13_n_0\, O => \cb_int[23]_i_3_n_0\ ); \cb_int[23]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[23]_i_30_n_0\ ); \cb_int[23]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[23]_i_31_n_0\ ); \cb_int[23]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[23]_i_32_n_0\ ); \cb_int[23]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[23]_i_14_n_0\, I1 => \cb_int[23]_i_15_n_0\, O => \cb_int[23]_i_4_n_0\ ); \cb_int[23]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[23]_i_16_n_0\, I1 => \cb_int[23]_i_17_n_0\, O => \cb_int[23]_i_5_n_0\ ); \cb_int[23]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[27]_i_7_n_0\, I1 => \cb_int[27]_i_8_n_0\, I2 => \cb_int[23]_i_2_n_0\, O => \cb_int[23]_i_6_n_0\ ); \cb_int[23]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[23]_i_10_n_0\, I1 => \cb_int[23]_i_11_n_0\, I2 => \cb_int[23]_i_3_n_0\, O => \cb_int[23]_i_7_n_0\ ); \cb_int[23]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[23]_i_12_n_0\, I1 => \cb_int[23]_i_13_n_0\, I2 => \cb_int[23]_i_4_n_0\, O => \cb_int[23]_i_8_n_0\ ); \cb_int[23]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[23]_i_14_n_0\, I1 => \cb_int[23]_i_15_n_0\, I2 => \cb_int[23]_i_5_n_0\, O => \cb_int[23]_i_9_n_0\ ); \cb_int[27]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_9\(1), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_10\(1), O => \cb_int[27]_i_10_n_0\ ); \cb_int[27]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(22), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_1\(1), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(22) ); \cb_int[27]_i_12\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[27]_i_12_n_0\ ); \cb_int[27]_i_13\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[27]_i_13_n_0\ ); \cb_int[27]_i_14\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[27]_i_14_n_0\ ); \cb_int[27]_i_15\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[27]_i_15_n_0\ ); \cb_int[27]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[27]_i_7_n_0\, I1 => \cb_int[27]_i_8_n_0\, O => \cb_int[27]_i_2_n_0\ ); \cb_int[27]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_3_n_0\ ); \cb_int[27]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_4_n_0\ ); \cb_int[27]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_5_n_0\ ); \cb_int[27]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[27]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_6_n_0\ ); \cb_int[27]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"1E111E11E1EE1E11" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => \cb_int_reg[31]_i_11_n_1\, I2 => \rgb888[8]_11\(0), I3 => \rgb888[8]_1\(1), I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_7_n_0\ ); \cb_int[27]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(22), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(30), I3 => cb_int_reg8, I4 => \cb_int[27]_i_10_n_0\, I5 => cb_int_reg2(22), O => \cb_int[27]_i_8_n_0\ ); \cb_int[31]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \rgb888[8]_11\(0), I1 => \rgb888[8]_1\(1), O => \cb_int[31]_i_13_n_0\ ); \cb_int[31]_i_15\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_1\(1), O => \cb_int[31]_i_15_n_0\ ); \cb_int[31]_i_16\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_1\(0), O => \cb_int[31]_i_16_n_0\ ); \cb_int[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"4404440444040000" ) port map ( I0 => \cb_int_reg[31]_i_7_n_1\, I1 => \rgb888[0]\(3), I2 => \rgb888[8]_1\(1), I3 => \rgb888[8]_11\(0), I4 => \cb_int_reg[31]_i_11_n_1\, I5 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[31]_i_2_n_0\ ); \cb_int[31]_i_24\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \^di\(0) ); \cb_int[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[31]_i_3_n_0\ ); \cb_int[31]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(30), O => \cb_int[31]_i_31_n_0\ ); \cb_int[31]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(29), O => \cb_int[31]_i_32_n_0\ ); \cb_int[31]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_34_n_2\, O => \cb_int[31]_i_35_n_0\ ); \cb_int[31]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_34_n_2\, O => \cb_int[31]_i_36_n_0\ ); \cb_int[31]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_2\(3), O => \cb_int[31]_i_38_n_0\ ); \cb_int[31]_i_39\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_2\(2), O => \cb_int[31]_i_39_n_0\ ); \cb_int[31]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[31]_i_4_n_0\ ); \cb_int[31]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_2\(1), O => \cb_int[31]_i_40_n_0\ ); \cb_int[31]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_2\(0), O => \cb_int[31]_i_41_n_0\ ); \cb_int[31]_i_43\: unisim.vcomponents.LUT6 generic map( INIT => X"00000001FFFFFFFE" ) port map ( I0 => rgb888(5), I1 => rgb888(3), I2 => rgb888(1), I3 => rgb888(2), I4 => rgb888(4), I5 => rgb888(6), O => \^cr_int_reg[27]_1\(1) ); \cb_int[31]_i_44\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFE" ) port map ( I0 => rgb888(4), I1 => rgb888(2), I2 => rgb888(1), I3 => rgb888(3), I4 => rgb888(5), O => \^cr_int_reg[27]_1\(0) ); \cb_int[31]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[31]_i_5_n_0\ ); \cb_int[31]_i_51\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => rgb888(5), I1 => rgb888(3), I2 => rgb888(1), I3 => rgb888(2), I4 => rgb888(4), I5 => rgb888(6), O => \^cr_int_reg[27]_0\ ); \cb_int[31]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[31]_i_6_n_0\ ); \cb_int[31]_i_67\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(28), O => \cb_int[31]_i_67_n_0\ ); \cb_int[31]_i_68\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(27), O => \cb_int[31]_i_68_n_0\ ); \cb_int[31]_i_69\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(26), O => \cb_int[31]_i_69_n_0\ ); \cb_int[31]_i_70\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(25), O => \cb_int[31]_i_70_n_0\ ); \cb_int[31]_i_71\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \cb_int_reg[31]_i_73_n_5\, I1 => rgb888(23), I2 => rgb888(22), O => \cb_int[31]_i_71_n_0\ ); \cb_int[31]_i_72\: unisim.vcomponents.LUT3 generic map( INIT => X"82" ) port map ( I0 => \cb_int_reg[31]_i_73_n_6\, I1 => rgb888(23), I2 => rgb888(22), O => \cb_int[31]_i_72_n_0\ ); \cb_int[31]_i_74\: unisim.vcomponents.LUT4 generic map( INIT => X"1FE0" ) port map ( I0 => rgb888(22), I1 => rgb888(23), I2 => \cb_int_reg[31]_i_73_n_4\, I3 => \cb_int_reg[31]_i_34_n_7\, O => \cb_int[31]_i_74_n_0\ ); \cb_int[31]_i_75\: unisim.vcomponents.LUT4 generic map( INIT => X"3336" ) port map ( I0 => \cb_int_reg[31]_i_73_n_5\, I1 => \cb_int_reg[31]_i_73_n_4\, I2 => rgb888(22), I3 => rgb888(23), O => \cb_int[31]_i_75_n_0\ ); \cb_int[31]_i_76\: unisim.vcomponents.LUT4 generic map( INIT => X"7E81" ) port map ( I0 => \cb_int_reg[31]_i_73_n_6\, I1 => rgb888(22), I2 => rgb888(23), I3 => \cb_int_reg[31]_i_73_n_5\, O => \cb_int[31]_i_76_n_0\ ); \cb_int[31]_i_77\: unisim.vcomponents.LUT4 generic map( INIT => X"9669" ) port map ( I0 => \cb_int_reg[31]_i_73_n_7\, I1 => \cb_int_reg[31]_i_73_n_6\, I2 => rgb888(22), I3 => rgb888(23), O => \cb_int[31]_i_77_n_0\ ); \cb_int[31]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(23), O => \cb_int[31]_i_78_n_0\ ); \cb_int[31]_i_79\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_3\(3), O => \cb_int[31]_i_79_n_0\ ); \cb_int[31]_i_80\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_3\(2), O => \cb_int[31]_i_80_n_0\ ); \cb_int[31]_i_81\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_3\(1), O => \cb_int[31]_i_81_n_0\ ); \cb_int[31]_i_82\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_3\(0), O => \cb_int[31]_i_82_n_0\ ); \cb_int[31]_i_86\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => rgb888(11), I1 => rgb888(10), I2 => rgb888(12), I3 => rgb888(13), O => \^cr_int_reg[31]_1\ ); \cb_int[31]_i_87\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => rgb888(12), I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(13), I4 => rgb888(14), O => \^cr_int_reg[31]_0\ ); \cb_int[31]_i_95\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(22), O => \cb_int[31]_i_95_n_0\ ); \cb_int[31]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(23), I1 => rgb888(21), O => \cb_int[31]_i_96_n_0\ ); \cb_int[31]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(22), I1 => rgb888(20), O => \cb_int[31]_i_97_n_0\ ); \cb_int[31]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(21), I1 => rgb888(19), O => \cb_int[31]_i_98_n_0\ ); \cb_int[3]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_2\(1), I1 => \rgb888[8]_1\(1), I2 => \rgb888[13]_0\(1), I3 => \^co\(0), I4 => \rgb888[8]\(3), O => \cb_int[3]_i_10_n_0\ ); \cb_int[3]_i_100\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(0), I1 => rgb888(2), O => \cb_int[3]_i_100_n_0\ ); \cb_int[3]_i_101\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), O => \cb_int[3]_i_101_n_0\ ); \cb_int[3]_i_102\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(0), O => \cb_int[3]_i_102_n_0\ ); \cb_int[3]_i_103\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(8), I1 => rgb888(11), O => \cb_int[3]_i_103_n_0\ ); \cb_int[3]_i_104\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(10), O => \cb_int[3]_i_104_n_0\ ); \cb_int[3]_i_105\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(9), O => \cb_int[3]_i_105_n_0\ ); \cb_int[3]_i_106\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(8), O => \cb_int[3]_i_106_n_0\ ); \cb_int[3]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(2), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_0\(0), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[7]_i_29_n_6\, O => cb_int_reg2(2) ); \cb_int[3]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(9), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_7\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(1), O => \cb_int[3]_i_12_n_0\ ); \cb_int[3]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_2\(0), I1 => \rgb888[8]_1\(1), I2 => \rgb888[13]_0\(0), I3 => \^co\(0), I4 => \rgb888[8]\(2), O => \cb_int[3]_i_13_n_0\ ); \cb_int[3]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(1), I1 => \rgb888[0]\(3), I2 => \cb_int_reg[3]_i_20_n_4\, I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[7]_i_29_n_7\, O => cb_int_reg2(1) ); \cb_int[3]_i_17\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \rgb888[8]\(1), I1 => \^co\(0), I2 => \rgb888[13]\(0), O => \cb_int[3]_i_17_n_0\ ); \cb_int[3]_i_18\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cb_int_reg[3]_i_20_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \cb_int_reg[3]_i_33_n_4\, O => \cb_int[3]_i_18_n_0\ ); \cb_int[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[3]_i_9_n_0\, I1 => \cb_int[3]_i_10_n_0\, I2 => cb_int_reg2(2), O => \cb_int[3]_i_2_n_0\ ); \cb_int[3]_i_22\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_6\, O => \cb_int[3]_i_22_n_0\ ); \cb_int[3]_i_23\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_7\, O => \cb_int[3]_i_23_n_0\ ); \cb_int[3]_i_24\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_4\, O => \cb_int[3]_i_24_n_0\ ); \cb_int[3]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_5\, O => \cb_int[3]_i_25_n_0\ ); \cb_int[3]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_73_n_7\, O => \cb_int[3]_i_27_n_0\ ); \cb_int[3]_i_28\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cb_int_reg[31]_i_73_n_7\, I1 => rgb888(22), O => \cb_int[3]_i_28_n_0\ ); \cb_int[3]_i_29\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(21), I1 => \cb_int_reg[3]_i_57_n_4\, O => \cb_int[3]_i_29_n_0\ ); \cb_int[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[3]_i_12_n_0\, I1 => \cb_int[3]_i_13_n_0\, I2 => cb_int_reg2(1), O => \cb_int[3]_i_3_n_0\ ); \cb_int[3]_i_30\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(20), I1 => \cb_int_reg[3]_i_57_n_5\, O => \cb_int[3]_i_30_n_0\ ); \cb_int[3]_i_31\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(19), I1 => \cb_int_reg[3]_i_57_n_6\, O => \cb_int[3]_i_31_n_0\ ); \cb_int[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"1DFF001D" ) port map ( I0 => cb_int_reg7(8), I1 => cb_int_reg8, I2 => \cb_int_reg[3]_i_16_n_4\, I3 => \cb_int[3]_i_17_n_0\, I4 => \cb_int[3]_i_18_n_0\, O => \cb_int[3]_i_4_n_0\ ); \cb_int[3]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(2), I1 => rgb888(1), I2 => \rgb888[0]_8\(1), O => \cb_int[3]_i_45_n_0\ ); \cb_int[3]_i_46\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \rgb888[0]_8\(0), I1 => rgb888(1), O => \cb_int[3]_i_46_n_0\ ); \cb_int[3]_i_47\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cb_int_reg[3]_i_44_n_4\, I1 => rgb888(0), O => \cb_int[3]_i_47_n_0\ ); \cb_int[3]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[3]_i_44_n_5\, O => \cb_int[3]_i_48_n_0\ ); \cb_int[3]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_26_n_6\, O => \cb_int[3]_i_49_n_0\ ); \cb_int[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[7]_i_16_n_0\, I1 => \cb_int[7]_i_17_n_0\, I2 => cb_int_reg2(3), I3 => \cb_int[3]_i_2_n_0\, O => \cb_int[3]_i_5_n_0\ ); \cb_int[3]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_6\, O => \cb_int[3]_i_50_n_0\ ); \cb_int[3]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_7\, O => \cb_int[3]_i_51_n_0\ ); \cb_int[3]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_26_n_4\, O => \cb_int[3]_i_52_n_0\ ); \cb_int[3]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_26_n_5\, O => \cb_int[3]_i_53_n_0\ ); \cb_int[3]_i_54\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(18), I1 => \cb_int_reg[3]_i_57_n_7\, O => \cb_int[3]_i_54_n_0\ ); \cb_int[3]_i_55\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(17), I1 => rgb888(16), O => \cb_int[3]_i_55_n_0\ ); \cb_int[3]_i_56\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(16), O => \cb_int[3]_i_56_n_0\ ); \cb_int[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[3]_i_9_n_0\, I1 => \cb_int[3]_i_10_n_0\, I2 => cb_int_reg2(2), I3 => \cb_int[3]_i_3_n_0\, O => \cb_int[3]_i_6_n_0\ ); \cb_int[3]_i_64\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_5\, O => \cb_int[3]_i_64_n_0\ ); \cb_int[3]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_6\, O => \cb_int[3]_i_65_n_0\ ); \cb_int[3]_i_66\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_7\, O => \cb_int[3]_i_66_n_0\ ); \cb_int[3]_i_67\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_44_n_6\, O => \cb_int[3]_i_67_n_0\ ); \cb_int[3]_i_69\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(8), I1 => rgb888(10), I2 => \rgb888[8]_31\(2), O => \cb_int[3]_i_69_n_0\ ); \cb_int[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[3]_i_12_n_0\, I1 => \cb_int[3]_i_13_n_0\, I2 => cb_int_reg2(1), I3 => \cb_int[3]_i_4_n_0\, O => \cb_int[3]_i_7_n_0\ ); \cb_int[3]_i_70\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_31\(1), I1 => rgb888(9), O => \cb_int[3]_i_70_n_0\ ); \cb_int[3]_i_71\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_31\(0), I1 => rgb888(8), O => \cb_int[3]_i_71_n_0\ ); \cb_int[3]_i_72\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[3]_i_94_n_4\, O => \cb_int[3]_i_72_n_0\ ); \cb_int[3]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(7), I1 => rgb888(5), O => \cb_int[3]_i_76_n_0\ ); \cb_int[3]_i_77\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(6), I1 => rgb888(4), O => \cb_int[3]_i_77_n_0\ ); \cb_int[3]_i_78\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(5), I1 => rgb888(3), O => \cb_int[3]_i_78_n_0\ ); \cb_int[3]_i_79\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(4), I1 => rgb888(2), O => \cb_int[3]_i_79_n_0\ ); \cb_int[3]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"1DE2E21D" ) port map ( I0 => cb_int_reg7(8), I1 => cb_int_reg8, I2 => \cb_int_reg[3]_i_16_n_4\, I3 => \cb_int[3]_i_17_n_0\, I4 => \cb_int[3]_i_18_n_0\, O => \cb_int[3]_i_8_n_0\ ); \cb_int[3]_i_80\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(20), I1 => rgb888(18), O => \cb_int[3]_i_80_n_0\ ); \cb_int[3]_i_81\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(19), I1 => rgb888(17), O => \cb_int[3]_i_81_n_0\ ); \cb_int[3]_i_82\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(18), I1 => rgb888(16), O => \cb_int[3]_i_82_n_0\ ); \cb_int[3]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(17), O => \cb_int[3]_i_83_n_0\ ); \cb_int[3]_i_89\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_7\, O => \cb_int[3]_i_89_n_0\ ); \cb_int[3]_i_9\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(10), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_6\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(2), O => \cb_int[3]_i_9_n_0\ ); \cb_int[3]_i_90\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_44_n_7\, O => \cb_int[3]_i_90_n_0\ ); \cb_int[3]_i_91\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_4\, O => \cb_int[3]_i_91_n_0\ ); \cb_int[3]_i_92\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_5\, O => \cb_int[3]_i_92_n_0\ ); \cb_int[3]_i_93\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_6\, O => \cb_int[3]_i_93_n_0\ ); \cb_int[3]_i_99\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(3), I1 => rgb888(1), O => \cb_int[3]_i_99_n_0\ ); \cb_int[7]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(13), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_12_n_7\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(5), O => \cb_int[7]_i_10_n_0\ ); \cb_int[7]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_3\(0), I1 => \rgb888[8]_1\(1), I2 => \rgb888[12]\(0), I3 => \^co\(0), I4 => \rgb888[8]_0\(2), O => \cb_int[7]_i_11_n_0\ ); \cb_int[7]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(5), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_0\(3), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[11]_i_24_n_7\, O => cb_int_reg2(5) ); \cb_int[7]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(12), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_4\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(4), O => \cb_int[7]_i_13_n_0\ ); \cb_int[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_2\(3), I1 => \rgb888[8]_1\(1), I2 => \rgb888[13]_0\(3), I3 => \^co\(0), I4 => \rgb888[8]_0\(1), O => \cb_int[7]_i_14_n_0\ ); \cb_int[7]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(4), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_0\(2), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[7]_i_29_n_4\, O => cb_int_reg2(4) ); \cb_int[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(11), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_5\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(3), O => \cb_int[7]_i_16_n_0\ ); \cb_int[7]_i_17\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_2\(2), I1 => \rgb888[8]_1\(1), I2 => \rgb888[13]_0\(2), I3 => \^co\(0), I4 => \rgb888[8]_0\(0), O => \cb_int[7]_i_17_n_0\ ); \cb_int[7]_i_18\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(3), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_0\(1), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[7]_i_29_n_5\, O => cb_int_reg2(3) ); \cb_int[7]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"B0BF" ) port map ( I0 => cb_int_reg8, I1 => cb_int_reg7(15), I2 => \cb_int_reg[31]_i_12_n_1\, I3 => cb_int_reg5(7), O => \cb_int[7]_i_19_n_0\ ); \cb_int[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"5959A959" ) port map ( I0 => \cb_int[11]_i_19_n_0\, I1 => cb_int_reg5(7), I2 => \cb_int_reg[31]_i_12_n_1\, I3 => cb_int_reg7(15), I4 => cb_int_reg8, O => \cb_int[7]_i_2_n_0\ ); \cb_int[7]_i_20\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(6), I1 => \rgb888[0]\(3), I2 => \rgb888[0]\(0), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[11]_i_24_n_6\, O => cb_int_reg2(6) ); \cb_int[7]_i_21\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_3\(1), I1 => \rgb888[8]_1\(1), I2 => \rgb888[12]\(1), I3 => \^co\(0), I4 => \rgb888[8]_0\(3), O => \cb_int[7]_i_21_n_0\ ); \cb_int[7]_i_22\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(14), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_12_n_6\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(6), O => \cb_int[7]_i_22_n_0\ ); \cb_int[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[7]_i_10_n_0\, I1 => \cb_int[7]_i_11_n_0\, I2 => cb_int_reg2(5), O => \cb_int[7]_i_3_n_0\ ); \cb_int[7]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_39_n_0\ ); \cb_int[7]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[7]_i_13_n_0\, I1 => \cb_int[7]_i_14_n_0\, I2 => cb_int_reg2(4), O => \cb_int[7]_i_4_n_0\ ); \cb_int[7]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_40_n_0\ ); \cb_int[7]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_41_n_0\ ); \cb_int[7]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_42_n_0\ ); \cb_int[7]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[7]_i_16_n_0\, I1 => \cb_int[7]_i_17_n_0\, I2 => cb_int_reg2(3), O => \cb_int[7]_i_5_n_0\ ); \cb_int[7]_i_52\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[3]_i_33_n_4\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \cb_int_reg[3]_i_20_n_5\, O => \cb_int[7]_i_52_n_0\ ); \cb_int[7]_i_53\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_29_n_4\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_0\(2), O => \cb_int[7]_i_53_n_0\ ); \cb_int[7]_i_54\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_29_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_0\(1), O => \cb_int[7]_i_54_n_0\ ); \cb_int[7]_i_55\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_29_n_6\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_0\(0), O => \cb_int[7]_i_55_n_0\ ); \cb_int[7]_i_56\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_29_n_7\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \cb_int_reg[3]_i_20_n_4\, O => \cb_int[7]_i_56_n_0\ ); \cb_int[7]_i_57\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(2), O => \cb_int[7]_i_57_n_0\ ); \cb_int[7]_i_58\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(1), O => \cb_int[7]_i_58_n_0\ ); \cb_int[7]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(0), O => \cb_int[7]_i_59_n_0\ ); \cb_int[7]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"99969666" ) port map ( I0 => \cb_int[7]_i_19_n_0\, I1 => \cb_int[11]_i_19_n_0\, I2 => cb_int_reg2(6), I3 => \cb_int[7]_i_21_n_0\, I4 => \cb_int[7]_i_22_n_0\, O => \cb_int[7]_i_6_n_0\ ); \cb_int[7]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_4\, O => \cb_int[7]_i_60_n_0\ ); \cb_int[7]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_62_n_0\ ); \cb_int[7]_i_63\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_63_n_0\ ); \cb_int[7]_i_64\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_64_n_0\ ); \cb_int[7]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_65_n_0\ ); \cb_int[7]_i_67\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_0\(3), I1 => \rgb888[8]_1\(0), O => \cb_int[7]_i_67_n_0\ ); \cb_int[7]_i_68\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_0\(1), I1 => \rgb888[8]_0\(2), O => \cb_int[7]_i_68_n_0\ ); \cb_int[7]_i_69\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]\(3), I1 => \rgb888[8]_0\(0), O => \cb_int[7]_i_69_n_0\ ); \cb_int[7]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[7]_i_3_n_0\, I1 => cb_int_reg2(6), I2 => \cb_int[7]_i_21_n_0\, I3 => \cb_int[7]_i_22_n_0\, O => \cb_int[7]_i_7_n_0\ ); \cb_int[7]_i_70\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]\(1), I1 => \rgb888[8]\(2), O => \cb_int[7]_i_70_n_0\ ); \cb_int[7]_i_71\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(0), I1 => \rgb888[8]_0\(3), O => \cb_int[7]_i_71_n_0\ ); \cb_int[7]_i_72\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_0\(2), I1 => \rgb888[8]_0\(1), O => \cb_int[7]_i_72_n_0\ ); \cb_int[7]_i_73\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_0\(0), I1 => \rgb888[8]\(3), O => \cb_int[7]_i_73_n_0\ ); \cb_int[7]_i_74\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]\(2), I1 => \rgb888[8]\(1), O => \cb_int[7]_i_74_n_0\ ); \cb_int[7]_i_75\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cb_int_reg[3]_0\(3), I1 => \rgb888[8]\(0), O => \cb_int[7]_i_75_n_0\ ); \cb_int[7]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cb_int_reg[3]_0\(1), I1 => \^cb_int_reg[3]_0\(2), O => \cb_int[7]_i_76_n_0\ ); \cb_int[7]_i_77\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^o\(1), I1 => \^cb_int_reg[3]_0\(0), O => \cb_int[7]_i_77_n_0\ ); \cb_int[7]_i_78\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rgb888(8), I1 => \^o\(0), O => \cb_int[7]_i_78_n_0\ ); \cb_int[7]_i_79\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]\(0), I1 => \^cb_int_reg[3]_0\(3), O => \cb_int[7]_i_79_n_0\ ); \cb_int[7]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[7]_i_10_n_0\, I1 => \cb_int[7]_i_11_n_0\, I2 => cb_int_reg2(5), I3 => \cb_int[7]_i_4_n_0\, O => \cb_int[7]_i_8_n_0\ ); \cb_int[7]_i_80\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cb_int_reg[3]_0\(2), I1 => \^cb_int_reg[3]_0\(1), O => \cb_int[7]_i_80_n_0\ ); \cb_int[7]_i_81\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cb_int_reg[3]_0\(0), I1 => \^o\(1), O => \cb_int[7]_i_81_n_0\ ); \cb_int[7]_i_82\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^o\(0), I1 => rgb888(8), O => \cb_int[7]_i_82_n_0\ ); \cb_int[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[7]_i_13_n_0\, I1 => \cb_int[7]_i_14_n_0\, I2 => cb_int_reg2(4), I3 => \cb_int[7]_i_5_n_0\, O => \cb_int[7]_i_9_n_0\ ); \cb_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[3]_i_1_n_7\, Q => \cb_int_reg_n_0_[0]\, R => '0' ); \cb_int_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[11]_i_1_n_5\, Q => \cb_int_reg__0\(10), R => '0' ); \cb_int_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[11]_i_1_n_4\, Q => \cb_int_reg__0\(11), R => '0' ); \cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_1_n_0\, CO(3) => \cb_int_reg[11]_i_1_n_0\, CO(2) => \cb_int_reg[11]_i_1_n_1\, CO(1) => \cb_int_reg[11]_i_1_n_2\, CO(0) => \cb_int_reg[11]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[11]_i_2_n_0\, DI(2) => \cb_int[11]_i_3_n_0\, DI(1) => \cb_int[11]_i_4_n_0\, DI(0) => \cb_int[11]_i_5_n_0\, O(3) => \cb_int_reg[11]_i_1_n_4\, O(2) => \cb_int_reg[11]_i_1_n_5\, O(1) => \cb_int_reg[11]_i_1_n_6\, O(0) => \cb_int_reg[11]_i_1_n_7\, S(3) => \cb_int[11]_i_6_n_0\, S(2) => \cb_int[11]_i_7_n_0\, S(1) => \cb_int[11]_i_8_n_0\, S(0) => \cb_int[11]_i_9_n_0\ ); \cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_28_n_0\, CO(3) => \cb_int_reg[11]_i_16_n_0\, CO(2) => \cb_int_reg[11]_i_16_n_1\, CO(1) => \cb_int_reg[11]_i_16_n_2\, CO(0) => \cb_int_reg[11]_i_16_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(8 downto 5), S(3) => \cb_int[11]_i_29_n_0\, S(2) => \cb_int[11]_i_30_n_0\, S(1) => \cb_int[11]_i_31_n_0\, S(0) => \cb_int[11]_i_32_n_0\ ); \cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_33_n_0\, CO(3) => \cb_int_reg[11]_i_17_n_0\, CO(2) => \cb_int_reg[11]_i_17_n_1\, CO(1) => \cb_int_reg[11]_i_17_n_2\, CO(0) => \cb_int_reg[11]_i_17_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(18 downto 15), S(3) => \cb_int[11]_i_34_n_0\, S(2) => \cb_int[11]_i_35_n_0\, S(1) => \cb_int[11]_i_36_n_0\, S(0) => \cb_int[11]_i_37_n_0\ ); \cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_38_n_0\, CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3), CO(2) => cb_int_reg8, CO(1) => \cb_int_reg[11]_i_18_n_2\, CO(0) => \cb_int_reg[11]_i_18_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \cb_int[11]_i_39_n_0\, DI(0) => \cb_int[11]_i_40_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0), S(3) => '0', S(2) => \cb_int[11]_i_41_n_0\, S(1) => \cb_int[11]_i_42_n_0\, S(0) => \cb_int[11]_i_43_n_0\ ); \cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_29_n_0\, CO(3) => \cb_int_reg[15]_0\(0), CO(2) => \cb_int_reg[11]_i_24_n_1\, CO(1) => \cb_int_reg[11]_i_24_n_2\, CO(0) => \cb_int_reg[11]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[11]_i_24_n_4\, O(2) => \cb_int_reg[11]_i_24_n_5\, O(1) => \cb_int_reg[11]_i_24_n_6\, O(0) => \cb_int_reg[11]_i_24_n_7\, S(3) => \cb_int[11]_i_44_n_0\, S(2) => \cb_int[11]_i_45_n_0\, S(1) => \cb_int[11]_i_46_n_0\, S(0) => \cb_int[11]_i_47_n_0\ ); \cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_48_n_0\, CO(3) => \cb_int_reg[11]_i_25_n_0\, CO(2) => \cb_int_reg[11]_i_25_n_1\, CO(1) => \cb_int_reg[11]_i_25_n_2\, CO(0) => \cb_int_reg[11]_i_25_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \rgb888[0]\(3), DI(1) => \rgb888[0]\(3), DI(0) => \rgb888[0]\(3), O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_49_n_0\, S(2) => \cb_int[11]_i_50_n_0\, S(1) => \cb_int[11]_i_51_n_0\, S(0) => \cb_int[11]_i_52_n_0\ ); \cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_28_n_0\, CO(3) => \cb_int_reg[11]_i_26_n_0\, CO(2) => \cb_int_reg[11]_i_26_n_1\, CO(1) => \cb_int_reg[11]_i_26_n_2\, CO(0) => \cb_int_reg[11]_i_26_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(8 downto 5), S(3) => \cb_int[11]_i_53_n_0\, S(2) => \cb_int[11]_i_54_n_0\, S(1) => \cb_int[11]_i_55_n_0\, S(0) => \cb_int[11]_i_56_n_0\ ); \cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[11]_i_28_n_0\, CO(2) => \cb_int_reg[11]_i_28_n_1\, CO(1) => \cb_int_reg[11]_i_28_n_2\, CO(0) => \cb_int_reg[11]_i_28_n_3\, CYINIT => \cb_int[11]_i_57_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(4 downto 1), S(3) => \cb_int[11]_i_58_n_0\, S(2) => \cb_int[11]_i_59_n_0\, S(1) => \cb_int[11]_i_60_n_0\, S(0) => \cb_int[11]_i_61_n_0\ ); \cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_15_n_0\, CO(3) => \cb_int_reg[11]_i_33_n_0\, CO(2) => \cb_int_reg[11]_i_33_n_1\, CO(1) => \cb_int_reg[11]_i_33_n_2\, CO(0) => \cb_int_reg[11]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(14 downto 11), S(3) => \cb_int[11]_i_62_n_0\, S(2) => \cb_int[11]_i_63_n_0\, S(1) => \cb_int[11]_i_64_n_0\, S(0) => \cb_int[11]_i_65_n_0\ ); \cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_66_n_0\, CO(3) => \cb_int_reg[11]_i_38_n_0\, CO(2) => \cb_int_reg[11]_i_38_n_1\, CO(1) => \cb_int_reg[11]_i_38_n_2\, CO(0) => \cb_int_reg[11]_i_38_n_3\, CYINIT => '0', DI(3) => \cb_int[11]_i_67_n_0\, DI(2) => \cb_int[11]_i_68_n_0\, DI(1) => \cb_int[11]_i_69_n_0\, DI(0) => \cb_int[11]_i_70_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_71_n_0\, S(2) => \cb_int[11]_i_72_n_0\, S(1) => \cb_int[11]_i_73_n_0\, S(0) => \cb_int[11]_i_74_n_0\ ); \cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_75_n_0\, CO(3) => \cb_int_reg[11]_i_48_n_0\, CO(2) => \cb_int_reg[11]_i_48_n_1\, CO(1) => \cb_int_reg[11]_i_48_n_2\, CO(0) => \cb_int_reg[11]_i_48_n_3\, CYINIT => '0', DI(3) => \rgb888[0]\(3), DI(2) => \rgb888[0]\(3), DI(1) => \rgb888[0]\(3), DI(0) => \cb_int[11]_i_76_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_77_n_0\, S(2) => \cb_int[11]_i_78_n_0\, S(1) => \cb_int[11]_i_79_n_0\, S(0) => \cb_int[11]_i_80_n_0\ ); \cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_81_n_0\, CO(3) => \cb_int_reg[11]_i_66_n_0\, CO(2) => \cb_int_reg[11]_i_66_n_1\, CO(1) => \cb_int_reg[11]_i_66_n_2\, CO(0) => \cb_int_reg[11]_i_66_n_3\, CYINIT => '0', DI(3) => \cb_int[11]_i_82_n_0\, DI(2) => \cb_int[11]_i_83_n_0\, DI(1) => \cb_int[11]_i_84_n_0\, DI(0) => \cb_int[11]_i_85_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_86_n_0\, S(2) => \cb_int[11]_i_87_n_0\, S(1) => \cb_int[11]_i_88_n_0\, S(0) => \cb_int[11]_i_89_n_0\ ); \cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_90_n_0\, CO(3) => \cb_int_reg[11]_i_75_n_0\, CO(2) => \cb_int_reg[11]_i_75_n_1\, CO(1) => \cb_int_reg[11]_i_75_n_2\, CO(0) => \cb_int_reg[11]_i_75_n_3\, CYINIT => '0', DI(3) => \cb_int[11]_i_91_n_0\, DI(2) => \cb_int[11]_i_92_n_0\, DI(1) => \cb_int[11]_i_93_n_0\, DI(0) => \cb_int[11]_i_94_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_95_n_0\, S(2) => \cb_int[11]_i_96_n_0\, S(1) => \cb_int[11]_i_97_n_0\, S(0) => \cb_int[11]_i_98_n_0\ ); \cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[11]_i_81_n_0\, CO(2) => \cb_int_reg[11]_i_81_n_1\, CO(1) => \cb_int_reg[11]_i_81_n_2\, CO(0) => \cb_int_reg[11]_i_81_n_3\, CYINIT => '1', DI(3) => \cb_int[11]_i_99_n_0\, DI(2) => \cb_int[11]_i_100_n_0\, DI(1) => \cb_int[11]_i_101_n_0\, DI(0) => \cb_int[11]_i_102_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_103_n_0\, S(2) => \cb_int[11]_i_104_n_0\, S(1) => \cb_int[11]_i_105_n_0\, S(0) => \cb_int[11]_i_106_n_0\ ); \cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[11]_i_90_n_0\, CO(2) => \cb_int_reg[11]_i_90_n_1\, CO(1) => \cb_int_reg[11]_i_90_n_2\, CO(0) => \cb_int_reg[11]_i_90_n_3\, CYINIT => '1', DI(3) => \cb_int[11]_i_107_n_0\, DI(2) => \cb_int[11]_i_108_n_0\, DI(1) => \cb_int[11]_i_109_n_0\, DI(0) => \cb_int[11]_i_110_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_111_n_0\, S(2) => \cb_int[11]_i_112_n_0\, S(1) => \cb_int[11]_i_113_n_0\, S(0) => \cb_int[11]_i_114_n_0\ ); \cb_int_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[15]_i_1_n_7\, Q => \cb_int_reg__0\(12), R => '0' ); \cb_int_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[15]_i_1_n_6\, Q => \cb_int_reg__0\(13), R => '0' ); \cb_int_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[15]_i_1_n_5\, Q => \cb_int_reg__0\(14), R => '0' ); \cb_int_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[15]_i_1_n_4\, Q => \cb_int_reg__0\(15), R => '0' ); \cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_1_n_0\, CO(3) => \cb_int_reg[15]_i_1_n_0\, CO(2) => \cb_int_reg[15]_i_1_n_1\, CO(1) => \cb_int_reg[15]_i_1_n_2\, CO(0) => \cb_int_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[15]_i_2_n_0\, DI(2) => \cb_int[15]_i_3_n_0\, DI(1) => \cb_int[15]_i_4_n_0\, DI(0) => \cb_int[15]_i_5_n_0\, O(3) => \cb_int_reg[15]_i_1_n_4\, O(2) => \cb_int_reg[15]_i_1_n_5\, O(1) => \cb_int_reg[15]_i_1_n_6\, O(0) => \cb_int_reg[15]_i_1_n_7\, S(3) => \cb_int[15]_i_6_n_0\, S(2) => \cb_int[15]_i_7_n_0\, S(1) => \cb_int[15]_i_8_n_0\, S(0) => \cb_int[15]_i_9_n_0\ ); \cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_16_n_0\, CO(3) => \cb_int_reg[15]_i_20_n_0\, CO(2) => \cb_int_reg[15]_i_20_n_1\, CO(1) => \cb_int_reg[15]_i_20_n_2\, CO(0) => \cb_int_reg[15]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(12 downto 9), S(3) => \cb_int[15]_i_27_n_0\, S(2) => \cb_int[15]_i_28_n_0\, S(1) => \cb_int[15]_i_29_n_0\, S(0) => \cb_int[15]_i_30_n_0\ ); \cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_26_n_0\, CO(3) => \cb_int_reg[15]_i_33_n_0\, CO(2) => \cb_int_reg[15]_i_33_n_1\, CO(1) => \cb_int_reg[15]_i_33_n_2\, CO(0) => \cb_int_reg[15]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(12 downto 9), S(3) => \cb_int[15]_i_43_n_0\, S(2) => \cb_int[15]_i_44_n_0\, S(1) => \cb_int[15]_i_45_n_0\, S(0) => \cb_int[15]_i_46_n_0\ ); \cb_int_reg[16]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[19]_i_1_n_7\, Q => \cb_int_reg__0\(16), R => '0' ); \cb_int_reg[17]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[19]_i_1_n_6\, Q => \cb_int_reg__0\(17), R => '0' ); \cb_int_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[19]_i_1_n_5\, Q => \cb_int_reg__0\(18), R => '0' ); \cb_int_reg[19]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[19]_i_1_n_4\, Q => \cb_int_reg__0\(19), R => '0' ); \cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_1_n_0\, CO(3) => \cb_int_reg[19]_i_1_n_0\, CO(2) => \cb_int_reg[19]_i_1_n_1\, CO(1) => \cb_int_reg[19]_i_1_n_2\, CO(0) => \cb_int_reg[19]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[19]_i_2_n_0\, DI(2) => \cb_int[19]_i_3_n_0\, DI(1) => \cb_int[19]_i_4_n_0\, DI(0) => \cb_int[19]_i_5_n_0\, O(3) => \cb_int_reg[19]_i_1_n_4\, O(2) => \cb_int_reg[19]_i_1_n_5\, O(1) => \cb_int_reg[19]_i_1_n_6\, O(0) => \cb_int_reg[19]_i_1_n_7\, S(3) => \cb_int[19]_i_6_n_0\, S(2) => \cb_int[19]_i_7_n_0\, S(1) => \cb_int[19]_i_8_n_0\, S(0) => \cb_int[19]_i_9_n_0\ ); \cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_20_n_0\, CO(3) => \cb_int_reg[19]_i_20_n_0\, CO(2) => \cb_int_reg[19]_i_20_n_1\, CO(1) => \cb_int_reg[19]_i_20_n_2\, CO(0) => \cb_int_reg[19]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(16 downto 13), S(3) => \cb_int[19]_i_28_n_0\, S(2) => \cb_int[19]_i_29_n_0\, S(1) => \cb_int[19]_i_30_n_0\, S(0) => \cb_int[19]_i_31_n_0\ ); \cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_17_n_0\, CO(3) => \cb_int_reg[19]_i_25_n_0\, CO(2) => \cb_int_reg[19]_i_25_n_1\, CO(1) => \cb_int_reg[19]_i_25_n_2\, CO(0) => \cb_int_reg[19]_i_25_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(22 downto 19), S(3) => \cb_int[19]_i_34_n_0\, S(2) => \cb_int[19]_i_35_n_0\, S(1) => \cb_int[19]_i_36_n_0\, S(0) => \cb_int[19]_i_37_n_0\ ); \cb_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[3]_i_1_n_6\, Q => \cb_int_reg_n_0_[1]\, R => '0' ); \cb_int_reg[20]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[23]_i_1_n_7\, Q => \cb_int_reg__0\(20), R => '0' ); \cb_int_reg[21]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[23]_i_1_n_6\, Q => \cb_int_reg__0\(21), R => '0' ); \cb_int_reg[22]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[23]_i_1_n_5\, Q => \cb_int_reg__0\(22), R => '0' ); \cb_int_reg[23]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[23]_i_1_n_4\, Q => \cb_int_reg__0\(23), R => '0' ); \cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_1_n_0\, CO(3) => \cb_int_reg[23]_i_1_n_0\, CO(2) => \cb_int_reg[23]_i_1_n_1\, CO(1) => \cb_int_reg[23]_i_1_n_2\, CO(0) => \cb_int_reg[23]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[23]_i_2_n_0\, DI(2) => \cb_int[23]_i_3_n_0\, DI(1) => \cb_int[23]_i_4_n_0\, DI(0) => \cb_int[23]_i_5_n_0\, O(3) => \cb_int_reg[23]_i_1_n_4\, O(2) => \cb_int_reg[23]_i_1_n_5\, O(1) => \cb_int_reg[23]_i_1_n_6\, O(0) => \cb_int_reg[23]_i_1_n_7\, S(3) => \cb_int[23]_i_6_n_0\, S(2) => \cb_int[23]_i_7_n_0\, S(1) => \cb_int[23]_i_8_n_0\, S(0) => \cb_int[23]_i_9_n_0\ ); \cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_25_n_0\, CO(3) => \cb_int_reg[23]_i_24_n_0\, CO(2) => \cb_int_reg[23]_i_24_n_1\, CO(1) => \cb_int_reg[23]_i_24_n_2\, CO(0) => \cb_int_reg[23]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(26 downto 23), S(3) => \cb_int[23]_i_29_n_0\, S(2) => \cb_int[23]_i_30_n_0\, S(1) => \cb_int[23]_i_31_n_0\, S(0) => \cb_int[23]_i_32_n_0\ ); \cb_int_reg[24]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[27]_i_1_n_7\, Q => \cb_int_reg__0\(24), R => '0' ); \cb_int_reg[25]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[27]_i_1_n_6\, Q => \cb_int_reg__0\(25), R => '0' ); \cb_int_reg[26]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[27]_i_1_n_5\, Q => \cb_int_reg__0\(26), R => '0' ); \cb_int_reg[27]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[27]_i_1_n_4\, Q => \cb_int_reg__0\(27), R => '0' ); \cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[23]_i_1_n_0\, CO(3) => \cb_int_reg[27]_i_1_n_0\, CO(2) => \cb_int_reg[27]_i_1_n_1\, CO(1) => \cb_int_reg[27]_i_1_n_2\, CO(0) => \cb_int_reg[27]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[31]_i_2_n_0\, DI(2) => \cb_int[31]_i_2_n_0\, DI(1) => \cb_int[31]_i_2_n_0\, DI(0) => \cb_int[27]_i_2_n_0\, O(3) => \cb_int_reg[27]_i_1_n_4\, O(2) => \cb_int_reg[27]_i_1_n_5\, O(1) => \cb_int_reg[27]_i_1_n_6\, O(0) => \cb_int_reg[27]_i_1_n_7\, S(3) => \cb_int[27]_i_3_n_0\, S(2) => \cb_int[27]_i_4_n_0\, S(1) => \cb_int[27]_i_5_n_0\, S(0) => \cb_int[27]_i_6_n_0\ ); \cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[23]_i_24_n_0\, CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[27]_i_9_n_1\, CO(1) => \cb_int_reg[27]_i_9_n_2\, CO(0) => \cb_int_reg[27]_i_9_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(30 downto 27), S(3) => \cb_int[27]_i_12_n_0\, S(2) => \cb_int[27]_i_13_n_0\, S(1) => \cb_int[27]_i_14_n_0\, S(0) => \cb_int[27]_i_15_n_0\ ); \cb_int_reg[28]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[31]_i_1_n_7\, Q => \cb_int_reg__0\(28), R => '0' ); \cb_int_reg[29]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[31]_i_1_n_6\, Q => \cb_int_reg__0\(29), R => '0' ); \cb_int_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[3]_i_1_n_5\, Q => \cb_int_reg_n_0_[2]\, R => '0' ); \cb_int_reg[30]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[31]_i_1_n_5\, Q => \cb_int_reg__0\(30), R => '0' ); \cb_int_reg[31]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[31]_i_1_n_4\, Q => \cb_int_reg__0\(31), R => '0' ); \cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[27]_i_1_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_1_n_1\, CO(1) => \cb_int_reg[31]_i_1_n_2\, CO(0) => \cb_int_reg[31]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \cb_int[31]_i_2_n_0\, DI(1) => \cb_int[31]_i_2_n_0\, DI(0) => \cb_int[31]_i_2_n_0\, O(3) => \cb_int_reg[31]_i_1_n_4\, O(2) => \cb_int_reg[31]_i_1_n_5\, O(1) => \cb_int_reg[31]_i_1_n_6\, O(0) => \cb_int_reg[31]_i_1_n_7\, S(3) => \cb_int[31]_i_3_n_0\, S(2) => \cb_int[31]_i_4_n_0\, S(1) => \cb_int[31]_i_5_n_0\, S(0) => \cb_int[31]_i_6_n_0\ ); \cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_30_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_11_n_1\, CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[31]_i_11_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => cb_int_reg5(22 downto 21), S(3 downto 2) => B"01", S(1) => \cb_int[31]_i_31_n_0\, S(0) => \cb_int[31]_i_32_n_0\ ); \cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_33_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_12_n_1\, CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[31]_i_12_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \cb_int_reg[31]_i_34_n_2\, DI(0) => '0', O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_12_n_6\, O(0) => \cb_int_reg[31]_i_12_n_7\, S(3 downto 2) => B"01", S(1) => \cb_int[31]_i_35_n_0\, S(0) => \cb_int[31]_i_36_n_0\ ); \cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_37_n_0\, CO(3) => \cb_int_reg[31]_i_14_n_0\, CO(2) => \cb_int_reg[31]_i_14_n_1\, CO(1) => \cb_int_reg[31]_i_14_n_2\, CO(0) => \cb_int_reg[31]_i_14_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(20 downto 17), S(3) => \cb_int[31]_i_38_n_0\, S(2) => \cb_int[31]_i_39_n_0\, S(1) => \cb_int[31]_i_40_n_0\, S(0) => \cb_int[31]_i_41_n_0\ ); \cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_20_n_0\, CO(3) => \cb_int_reg[31]_i_30_n_0\, CO(2) => \cb_int_reg[31]_i_30_n_1\, CO(1) => \cb_int_reg[31]_i_30_n_2\, CO(0) => \cb_int_reg[31]_i_30_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(20 downto 17), S(3) => \cb_int[31]_i_67_n_0\, S(2) => \cb_int[31]_i_68_n_0\, S(1) => \cb_int[31]_i_69_n_0\, S(0) => \cb_int[31]_i_70_n_0\ ); \cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_16_n_0\, CO(3) => \cb_int_reg[31]_i_33_n_0\, CO(2) => \cb_int_reg[31]_i_33_n_1\, CO(1) => \cb_int_reg[31]_i_33_n_2\, CO(0) => \cb_int_reg[31]_i_33_n_3\, CYINIT => '0', DI(3) => \cb_int_reg[31]_i_34_n_7\, DI(2) => \cb_int[31]_i_71_n_0\, DI(1) => \cb_int[31]_i_72_n_0\, DI(0) => \cb_int_reg[31]_i_73_n_7\, O(3) => \cb_int_reg[31]_i_33_n_4\, O(2) => \cb_int_reg[31]_i_33_n_5\, O(1) => \cb_int_reg[31]_i_33_n_6\, O(0) => \cb_int_reg[31]_i_33_n_7\, S(3) => \cb_int[31]_i_74_n_0\, S(2) => \cb_int[31]_i_75_n_0\, S(1) => \cb_int[31]_i_76_n_0\, S(0) => \cb_int[31]_i_77_n_0\ ); \cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_73_n_0\, CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2), CO(1) => \cb_int_reg[31]_i_34_n_2\, CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(23), O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1), O(0) => \cb_int_reg[31]_i_34_n_7\, S(3 downto 1) => B"001", S(0) => \cb_int[31]_i_78_n_0\ ); \cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_33_n_0\, CO(3) => \cb_int_reg[31]_i_37_n_0\, CO(2) => \cb_int_reg[31]_i_37_n_1\, CO(1) => \cb_int_reg[31]_i_37_n_2\, CO(0) => \cb_int_reg[31]_i_37_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(16 downto 13), S(3) => \cb_int[31]_i_79_n_0\, S(2) => \cb_int[31]_i_80_n_0\, S(1) => \cb_int[31]_i_81_n_0\, S(0) => \cb_int[31]_i_82_n_0\ ); \cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_14_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_7_n_1\, CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[31]_i_7_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => cb_int_reg3(22 downto 21), S(3 downto 2) => B"01", S(1) => \cb_int[31]_i_15_n_0\, S(0) => \cb_int[31]_i_16_n_0\ ); \cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_57_n_0\, CO(3) => \cb_int_reg[31]_i_73_n_0\, CO(2) => \cb_int_reg[31]_i_73_n_1\, CO(1) => \cb_int_reg[31]_i_73_n_2\, CO(0) => \cb_int_reg[31]_i_73_n_3\, CYINIT => '0', DI(3) => rgb888(22), DI(2 downto 0) => rgb888(23 downto 21), O(3) => \cb_int_reg[31]_i_73_n_4\, O(2) => \cb_int_reg[31]_i_73_n_5\, O(1) => \cb_int_reg[31]_i_73_n_6\, O(0) => \cb_int_reg[31]_i_73_n_7\, S(3) => \cb_int[31]_i_95_n_0\, S(2) => \cb_int[31]_i_96_n_0\, S(1) => \cb_int[31]_i_97_n_0\, S(0) => \cb_int[31]_i_98_n_0\ ); \cb_int_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[3]_i_1_n_4\, Q => \cb_int_reg_n_0_[3]\, R => '0' ); \cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_1_n_0\, CO(2) => \cb_int_reg[3]_i_1_n_1\, CO(1) => \cb_int_reg[3]_i_1_n_2\, CO(0) => \cb_int_reg[3]_i_1_n_3\, CYINIT => '1', DI(3) => \cb_int[3]_i_2_n_0\, DI(2) => \cb_int[3]_i_3_n_0\, DI(1) => \cb_int[3]_i_4_n_0\, DI(0) => '1', O(3) => \cb_int_reg[3]_i_1_n_4\, O(2) => \cb_int_reg[3]_i_1_n_5\, O(1) => \cb_int_reg[3]_i_1_n_6\, O(0) => \cb_int_reg[3]_i_1_n_7\, S(3) => \cb_int[3]_i_5_n_0\, S(2) => \cb_int[3]_i_6_n_0\, S(1) => \cb_int[3]_i_7_n_0\, S(0) => \cb_int[3]_i_8_n_0\ ); \cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_21_n_0\, CO(3) => \cb_int_reg[3]_i_15_n_0\, CO(2) => \cb_int_reg[3]_i_15_n_1\, CO(1) => \cb_int_reg[3]_i_15_n_2\, CO(0) => \cb_int_reg[3]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => cb_int_reg7(10 downto 8), O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0), S(3) => \cb_int[3]_i_22_n_0\, S(2) => \cb_int[3]_i_23_n_0\, S(1) => \cb_int[3]_i_24_n_0\, S(0) => \cb_int[3]_i_25_n_0\ ); \cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_26_n_0\, CO(3) => \cb_int_reg[3]_i_16_n_0\, CO(2) => \cb_int_reg[3]_i_16_n_1\, CO(1) => \cb_int_reg[3]_i_16_n_2\, CO(0) => \cb_int_reg[3]_i_16_n_3\, CYINIT => '0', DI(3) => \cb_int[3]_i_27_n_0\, DI(2 downto 0) => rgb888(21 downto 19), O(3) => \cb_int_reg[3]_i_16_n_4\, O(2) => \cb_int_reg[3]_i_16_n_5\, O(1) => \cb_int_reg[3]_i_16_n_6\, O(0) => \cb_int_reg[3]_i_16_n_7\, S(3) => \cb_int[3]_i_28_n_0\, S(2) => \cb_int[3]_i_29_n_0\, S(1) => \cb_int[3]_i_30_n_0\, S(0) => \cb_int[3]_i_31_n_0\ ); \cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[27]_0\(0), CO(2) => \cb_int_reg[3]_i_20_n_1\, CO(1) => \cb_int_reg[3]_i_20_n_2\, CO(0) => \cb_int_reg[3]_i_20_n_3\, CYINIT => '0', DI(3 downto 2) => \rgb888[0]_8\(1 downto 0), DI(1) => \cb_int_reg[3]_i_44_n_4\, DI(0) => '0', O(3) => \cb_int_reg[3]_i_20_n_4\, O(2) => \cb_int_reg[3]_i_20_n_5\, O(1) => \cb_int_reg[3]_i_20_n_6\, O(0) => \cb_int_reg[3]_i_20_n_7\, S(3) => \cb_int[3]_i_45_n_0\, S(2) => \cb_int[3]_i_46_n_0\, S(1) => \cb_int[3]_i_47_n_0\, S(0) => \cb_int[3]_i_48_n_0\ ); \cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_21_n_0\, CO(2) => \cb_int_reg[3]_i_21_n_1\, CO(1) => \cb_int_reg[3]_i_21_n_2\, CO(0) => \cb_int_reg[3]_i_21_n_3\, CYINIT => \cb_int[3]_i_49_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[3]_i_50_n_0\, S(2) => \cb_int[3]_i_51_n_0\, S(1) => \cb_int[3]_i_52_n_0\, S(0) => \cb_int[3]_i_53_n_0\ ); \cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_26_n_0\, CO(2) => \cb_int_reg[3]_i_26_n_1\, CO(1) => \cb_int_reg[3]_i_26_n_2\, CO(0) => \cb_int_reg[3]_i_26_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(18 downto 16), DI(0) => '0', O(3) => \cb_int_reg[3]_i_26_n_4\, O(2) => \cb_int_reg[3]_i_26_n_5\, O(1) => \cb_int_reg[3]_i_26_n_6\, O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0), S(3) => \cb_int[3]_i_54_n_0\, S(2) => \cb_int[3]_i_55_n_0\, S(1) => \cb_int[3]_i_56_n_0\, S(0) => '0' ); \cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_63_n_0\, CO(3) => \cb_int_reg[3]_i_33_n_0\, CO(2) => \cb_int_reg[3]_i_33_n_1\, CO(1) => \cb_int_reg[3]_i_33_n_2\, CO(0) => \cb_int_reg[3]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[3]_i_33_n_4\, O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0), S(3) => \cb_int[3]_i_64_n_0\, S(2) => \cb_int[3]_i_65_n_0\, S(1) => \cb_int[3]_i_66_n_0\, S(0) => \cb_int[3]_i_67_n_0\ ); \cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_2\(0), CO(2) => \cb_int_reg[3]_i_34_n_1\, CO(1) => \cb_int_reg[3]_i_34_n_2\, CO(0) => \cb_int_reg[3]_i_34_n_3\, CYINIT => '0', DI(3 downto 1) => \rgb888[8]_31\(2 downto 0), DI(0) => '0', O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0), S(3) => \cb_int[3]_i_69_n_0\, S(2) => \cb_int[3]_i_70_n_0\, S(1) => \cb_int[3]_i_71_n_0\, S(0) => \cb_int[3]_i_72_n_0\ ); \cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_75_n_0\, CO(3) => \cb_int_reg[3]_3\(0), CO(2) => \cb_int_reg[3]_i_44_n_1\, CO(1) => \cb_int_reg[3]_i_44_n_2\, CO(0) => \cb_int_reg[3]_i_44_n_3\, CYINIT => '0', DI(3 downto 0) => rgb888(5 downto 2), O(3) => \cb_int_reg[3]_i_44_n_4\, O(2) => \cb_int_reg[3]_i_44_n_5\, O(1) => \cb_int_reg[3]_i_44_n_6\, O(0) => \cb_int_reg[3]_i_44_n_7\, S(3) => \cb_int[3]_i_76_n_0\, S(2) => \cb_int[3]_i_77_n_0\, S(1) => \cb_int[3]_i_78_n_0\, S(0) => \cb_int[3]_i_79_n_0\ ); \cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_57_n_0\, CO(2) => \cb_int_reg[3]_i_57_n_1\, CO(1) => \cb_int_reg[3]_i_57_n_2\, CO(0) => \cb_int_reg[3]_i_57_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(20 downto 18), DI(0) => '0', O(3) => \cb_int_reg[3]_i_57_n_4\, O(2) => \cb_int_reg[3]_i_57_n_5\, O(1) => \cb_int_reg[3]_i_57_n_6\, O(0) => \cb_int_reg[3]_i_57_n_7\, S(3) => \cb_int[3]_i_80_n_0\, S(2) => \cb_int[3]_i_81_n_0\, S(1) => \cb_int[3]_i_82_n_0\, S(0) => \cb_int[3]_i_83_n_0\ ); \cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_63_n_0\, CO(2) => \cb_int_reg[3]_i_63_n_1\, CO(1) => \cb_int_reg[3]_i_63_n_2\, CO(0) => \cb_int_reg[3]_i_63_n_3\, CYINIT => \cb_int[3]_i_89_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[3]_i_90_n_0\, S(2) => \cb_int[3]_i_91_n_0\, S(1) => \cb_int[3]_i_92_n_0\, S(0) => \cb_int[3]_i_93_n_0\ ); \cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_75_n_0\, CO(2) => \cb_int_reg[3]_i_75_n_1\, CO(1) => \cb_int_reg[3]_i_75_n_2\, CO(0) => \cb_int_reg[3]_i_75_n_3\, CYINIT => '0', DI(3 downto 2) => rgb888(1 downto 0), DI(1 downto 0) => B"01", O(3) => \cb_int_reg[3]_i_75_n_4\, O(2) => \cb_int_reg[3]_i_75_n_5\, O(1) => \cb_int_reg[3]_i_75_n_6\, O(0) => \cb_int_reg[3]_i_75_n_7\, S(3) => \cb_int[3]_i_99_n_0\, S(2) => \cb_int[3]_i_100_n_0\, S(1) => \cb_int[3]_i_101_n_0\, S(0) => \cb_int[3]_i_102_n_0\ ); \cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_1\(0), CO(2) => \cb_int_reg[3]_i_94_n_1\, CO(1) => \cb_int_reg[3]_i_94_n_2\, CO(0) => \cb_int_reg[3]_i_94_n_3\, CYINIT => '0', DI(3) => rgb888(8), DI(2 downto 0) => B"001", O(3) => \cb_int_reg[3]_i_94_n_4\, O(2 downto 1) => \^o\(1 downto 0), O(0) => \cb_int_reg[3]_i_94_n_7\, S(3) => \cb_int[3]_i_103_n_0\, S(2) => \cb_int[3]_i_104_n_0\, S(1) => \cb_int[3]_i_105_n_0\, S(0) => \cb_int[3]_i_106_n_0\ ); \cb_int_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[7]_i_1_n_7\, Q => \cb_int_reg_n_0_[4]\, R => '0' ); \cb_int_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[7]_i_1_n_6\, Q => \cb_int_reg_n_0_[5]\, R => '0' ); \cb_int_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[7]_i_1_n_5\, Q => \cb_int_reg_n_0_[6]\, R => '0' ); \cb_int_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[7]_i_1_n_4\, Q => \cb_int_reg_n_0_[7]\, R => '0' ); \cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_1_n_0\, CO(3) => \cb_int_reg[7]_i_1_n_0\, CO(2) => \cb_int_reg[7]_i_1_n_1\, CO(1) => \cb_int_reg[7]_i_1_n_2\, CO(0) => \cb_int_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[7]_i_2_n_0\, DI(2) => \cb_int[7]_i_3_n_0\, DI(1) => \cb_int[7]_i_4_n_0\, DI(0) => \cb_int[7]_i_5_n_0\, O(3) => \cb_int_reg[7]_i_1_n_4\, O(2) => \cb_int_reg[7]_i_1_n_5\, O(1) => \cb_int_reg[7]_i_1_n_6\, O(0) => \cb_int_reg[7]_i_1_n_7\, S(3) => \cb_int[7]_i_6_n_0\, S(2) => \cb_int[7]_i_7_n_0\, S(1) => \cb_int[7]_i_8_n_0\, S(0) => \cb_int[7]_i_9_n_0\ ); \cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_38_n_0\, CO(3) => \^co\(0), CO(2) => \cb_int_reg[7]_i_25_n_1\, CO(1) => \cb_int_reg[7]_i_25_n_2\, CO(0) => \cb_int_reg[7]_i_25_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \rgb888[8]_1\(1), DI(1) => \rgb888[8]_1\(1), DI(0) => \rgb888[8]_1\(1), O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[7]_i_39_n_0\, S(2) => \cb_int[7]_i_40_n_0\, S(1) => \cb_int[7]_i_41_n_0\, S(0) => \cb_int[7]_i_42_n_0\ ); \cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[7]_i_28_n_0\, CO(2) => \cb_int_reg[7]_i_28_n_1\, CO(1) => \cb_int_reg[7]_i_28_n_2\, CO(0) => \cb_int_reg[7]_i_28_n_3\, CYINIT => \cb_int[7]_i_52_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(4 downto 1), S(3) => \cb_int[7]_i_53_n_0\, S(2) => \cb_int[7]_i_54_n_0\, S(1) => \cb_int[7]_i_55_n_0\, S(0) => \cb_int[7]_i_56_n_0\ ); \cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_33_n_0\, CO(3) => \cb_int_reg[7]_i_29_n_0\, CO(2) => \cb_int_reg[7]_i_29_n_1\, CO(1) => \cb_int_reg[7]_i_29_n_2\, CO(0) => \cb_int_reg[7]_i_29_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_29_n_4\, O(2) => \cb_int_reg[7]_i_29_n_5\, O(1) => \cb_int_reg[7]_i_29_n_6\, O(0) => \cb_int_reg[7]_i_29_n_7\, S(3) => \cb_int[7]_i_57_n_0\, S(2) => \cb_int[7]_i_58_n_0\, S(1) => \cb_int[7]_i_59_n_0\, S(0) => \cb_int[7]_i_60_n_0\ ); \cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_61_n_0\, CO(3) => \cb_int_reg[7]_i_38_n_0\, CO(2) => \cb_int_reg[7]_i_38_n_1\, CO(1) => \cb_int_reg[7]_i_38_n_2\, CO(0) => \cb_int_reg[7]_i_38_n_3\, CYINIT => '0', DI(3) => \rgb888[8]_1\(1), DI(2) => \rgb888[8]_1\(1), DI(1) => \rgb888[8]_1\(1), DI(0) => \rgb888[8]_1\(1), O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[7]_i_62_n_0\, S(2) => \cb_int[7]_i_63_n_0\, S(1) => \cb_int[7]_i_64_n_0\, S(0) => \cb_int[7]_i_65_n_0\ ); \cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_66_n_0\, CO(3) => \cb_int_reg[7]_i_61_n_0\, CO(2) => \cb_int_reg[7]_i_61_n_1\, CO(1) => \cb_int_reg[7]_i_61_n_2\, CO(0) => \cb_int_reg[7]_i_61_n_3\, CYINIT => '0', DI(3) => \cb_int[7]_i_67_n_0\, DI(2) => \cb_int[7]_i_68_n_0\, DI(1) => \cb_int[7]_i_69_n_0\, DI(0) => \cb_int[7]_i_70_n_0\, O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[7]_i_71_n_0\, S(2) => \cb_int[7]_i_72_n_0\, S(1) => \cb_int[7]_i_73_n_0\, S(0) => \cb_int[7]_i_74_n_0\ ); \cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[7]_i_66_n_0\, CO(2) => \cb_int_reg[7]_i_66_n_1\, CO(1) => \cb_int_reg[7]_i_66_n_2\, CO(0) => \cb_int_reg[7]_i_66_n_3\, CYINIT => '1', DI(3) => \cb_int[7]_i_75_n_0\, DI(2) => \cb_int[7]_i_76_n_0\, DI(1) => \cb_int[7]_i_77_n_0\, DI(0) => \cb_int[7]_i_78_n_0\, O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[7]_i_79_n_0\, S(2) => \cb_int[7]_i_80_n_0\, S(1) => \cb_int[7]_i_81_n_0\, S(0) => \cb_int[7]_i_82_n_0\ ); \cb_int_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[11]_i_1_n_7\, Q => \cb_int_reg__0\(8), R => '0' ); \cb_int_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[11]_i_1_n_6\, Q => \cb_int_reg__0\(9), R => '0' ); \cb_reg[0]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[0]_i_1_n_0\, Q => cb(0), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[1]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[1]_i_1_n_0\, Q => cb(1), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[2]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[2]_i_1_n_0\, Q => cb(2), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[3]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[3]_i_1_n_0\, Q => cb(3), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[4]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[4]_i_1_n_0\, Q => cb(4), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[5]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[5]_i_1_n_0\, Q => cb(5), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[6]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[6]_i_1_n_0\, Q => cb(6), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[7]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[7]_i_2_n_0\, Q => cb(7), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_reg[7]_i_3_n_0\, CO(3) => \cb_reg[7]_i_1_n_0\, CO(2) => \cb_reg[7]_i_1_n_1\, CO(1) => \cb_reg[7]_i_1_n_2\, CO(0) => \cb_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \cb[7]_i_4_n_0\, DI(2) => \cb[7]_i_5_n_0\, DI(1) => \cb[7]_i_6_n_0\, DI(0) => \cb[7]_i_7_n_0\, O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \cb[7]_i_8_n_0\, S(2) => \cb[7]_i_9_n_0\, S(1) => \cb[7]_i_10_n_0\, S(0) => \cb[7]_i_11_n_0\ ); \cb_reg[7]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_reg[7]_i_12_n_0\, CO(2) => \cb_reg[7]_i_12_n_1\, CO(1) => \cb_reg[7]_i_12_n_2\, CO(0) => \cb_reg[7]_i_12_n_3\, CYINIT => '0', DI(3) => \cb[7]_i_21_n_0\, DI(2) => \cb[7]_i_22_n_0\, DI(1) => \cb[7]_i_23_n_0\, DI(0) => \cb[7]_i_24_n_0\, O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0), S(3) => \cb[7]_i_25_n_0\, S(2) => \cb[7]_i_26_n_0\, S(1) => \cb[7]_i_27_n_0\, S(0) => \cb[7]_i_28_n_0\ ); \cb_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \cb_reg[7]_i_12_n_0\, CO(3) => \cb_reg[7]_i_3_n_0\, CO(2) => \cb_reg[7]_i_3_n_1\, CO(1) => \cb_reg[7]_i_3_n_2\, CO(0) => \cb_reg[7]_i_3_n_3\, CYINIT => '0', DI(3) => \cb[7]_i_13_n_0\, DI(2) => \cb[7]_i_14_n_0\, DI(1) => \cb[7]_i_15_n_0\, DI(0) => \cb[7]_i_16_n_0\, O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0), S(3) => \cb[7]_i_17_n_0\, S(2) => \cb[7]_i_18_n_0\, S(1) => \cb[7]_i_19_n_0\, S(0) => \cb[7]_i_20_n_0\ ); cb_regi_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => clk, O => cb_regn_0_0 ); \cr[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[0]\, I1 => \cr_int_reg__0\(31), O => \cr[0]_i_1_n_0\ ); \cr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[1]\, I1 => \cr_int_reg__0\(31), O => \cr[1]_i_1_n_0\ ); \cr[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[2]\, I1 => \cr_int_reg__0\(31), O => \cr[2]_i_1_n_0\ ); \cr[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[3]\, I1 => \cr_int_reg__0\(31), O => \cr[3]_i_1_n_0\ ); \cr[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[4]\, I1 => \cr_int_reg__0\(31), O => \cr[4]_i_1_n_0\ ); \cr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[5]\, I1 => \cr_int_reg__0\(31), O => \cr[5]_i_1_n_0\ ); \cr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[6]\, I1 => \cr_int_reg__0\(31), O => \cr[6]_i_1_n_0\ ); \cr[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(26), I1 => \cr_int_reg__0\(27), O => \cr[7]_i_10_n_0\ ); \cr[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(24), I1 => \cr_int_reg__0\(25), O => \cr[7]_i_11_n_0\ ); \cr[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(22), I1 => \cr_int_reg__0\(23), O => \cr[7]_i_13_n_0\ ); \cr[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(20), I1 => \cr_int_reg__0\(21), O => \cr[7]_i_14_n_0\ ); \cr[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(18), I1 => \cr_int_reg__0\(19), O => \cr[7]_i_15_n_0\ ); \cr[7]_i_16\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(16), I1 => \cr_int_reg__0\(17), O => \cr[7]_i_16_n_0\ ); \cr[7]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(22), I1 => \cr_int_reg__0\(23), O => \cr[7]_i_17_n_0\ ); \cr[7]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(20), I1 => \cr_int_reg__0\(21), O => \cr[7]_i_18_n_0\ ); \cr[7]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(18), I1 => \cr_int_reg__0\(19), O => \cr[7]_i_19_n_0\ ); \cr[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[7]\, I1 => \cr_int_reg__0\(31), O => \cr[7]_i_2_n_0\ ); \cr[7]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(16), I1 => \cr_int_reg__0\(17), O => \cr[7]_i_20_n_0\ ); \cr[7]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(14), I1 => \cr_int_reg__0\(15), O => \cr[7]_i_21_n_0\ ); \cr[7]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(12), I1 => \cr_int_reg__0\(13), O => \cr[7]_i_22_n_0\ ); \cr[7]_i_23\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(10), I1 => \cr_int_reg__0\(11), O => \cr[7]_i_23_n_0\ ); \cr[7]_i_24\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(8), I1 => \cr_int_reg__0\(9), O => \cr[7]_i_24_n_0\ ); \cr[7]_i_25\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(14), I1 => \cr_int_reg__0\(15), O => \cr[7]_i_25_n_0\ ); \cr[7]_i_26\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(12), I1 => \cr_int_reg__0\(13), O => \cr[7]_i_26_n_0\ ); \cr[7]_i_27\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(10), I1 => \cr_int_reg__0\(11), O => \cr[7]_i_27_n_0\ ); \cr[7]_i_28\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(8), I1 => \cr_int_reg__0\(9), O => \cr[7]_i_28_n_0\ ); \cr[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg__0\(30), I1 => \cr_int_reg__0\(31), O => \cr[7]_i_4_n_0\ ); \cr[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(28), I1 => \cr_int_reg__0\(29), O => \cr[7]_i_5_n_0\ ); \cr[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(26), I1 => \cr_int_reg__0\(27), O => \cr[7]_i_6_n_0\ ); \cr[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(24), I1 => \cr_int_reg__0\(25), O => \cr[7]_i_7_n_0\ ); \cr[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(30), I1 => \cr_int_reg__0\(31), O => \cr[7]_i_8_n_0\ ); \cr[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(28), I1 => \cr_int_reg__0\(29), O => \cr[7]_i_9_n_0\ ); \cr_hold_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(0), Q => \cr_hold_reg_n_0_[0]\, R => '0' ); \cr_hold_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(1), Q => \cr_hold_reg_n_0_[1]\, R => '0' ); \cr_hold_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(2), Q => \cr_hold_reg_n_0_[2]\, R => '0' ); \cr_hold_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(3), Q => \cr_hold_reg_n_0_[3]\, R => '0' ); \cr_hold_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(4), Q => \cr_hold_reg_n_0_[4]\, R => '0' ); \cr_hold_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(5), Q => \cr_hold_reg_n_0_[5]\, R => '0' ); \cr_hold_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(6), Q => \cr_hold_reg_n_0_[6]\, R => '0' ); \cr_hold_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(7), Q => \cr_hold_reg_n_0_[7]\, R => '0' ); \cr_int[11]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(18), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(10), I4 => \cr_int[15]_i_26_n_0\, I5 => \cr_int[15]_i_27_n_0\, O => \cr_int[11]_i_10_n_0\ ); \cr_int[11]_i_100\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(11), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_30_n_6\, O => \cr_int[11]_i_100_n_0\ ); \cr_int[11]_i_101\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(10), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_30_n_7\, O => \cr_int[11]_i_101_n_0\ ); \cr_int[11]_i_102\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(9), I1 => cr_int_reg7, I2 => \cr_int_reg[3]_i_16_n_4\, O => \cr_int[11]_i_102_n_0\ ); \cr_int[11]_i_104\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_104_n_0\ ); \cr_int[11]_i_105\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_105_n_0\ ); \cr_int[11]_i_106\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_106_n_0\ ); \cr_int[11]_i_107\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_107_n_0\ ); \cr_int[11]_i_109\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_7_n_6\, I1 => \cr_int_reg[31]_i_7_n_5\, O => \cr_int[11]_i_109_n_0\ ); \cr_int[11]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(17), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(9), I4 => \cr_int[11]_i_24_n_0\, I5 => \cr_int[11]_i_25_n_0\, O => \cr_int[11]_i_11_n_0\ ); \cr_int[11]_i_110\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_14_n_4\, I1 => \cr_int_reg[31]_i_7_n_7\, O => \cr_int[11]_i_110_n_0\ ); \cr_int[11]_i_111\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_14_n_6\, I1 => \cr_int_reg[31]_i_14_n_5\, O => \cr_int[11]_i_111_n_0\ ); \cr_int[11]_i_112\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_112_n_0\ ); \cr_int[11]_i_113\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_5\, I1 => \cr_int_reg[31]_i_7_n_6\, O => \cr_int[11]_i_113_n_0\ ); \cr_int[11]_i_114\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_7\, I1 => \cr_int_reg[31]_i_14_n_4\, O => \cr_int[11]_i_114_n_0\ ); \cr_int[11]_i_115\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_5\, I1 => \cr_int_reg[31]_i_14_n_6\, O => \cr_int[11]_i_115_n_0\ ); \cr_int[11]_i_117\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_11_n_7\, I1 => \cr_int_reg[31]_i_11_n_6\, O => \cr_int[11]_i_117_n_0\ ); \cr_int[11]_i_118\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_30_n_5\, I1 => \cr_int_reg[31]_i_30_n_4\, O => \cr_int[11]_i_118_n_0\ ); \cr_int[11]_i_119\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_30_n_7\, I1 => \cr_int_reg[31]_i_30_n_6\, O => \cr_int[11]_i_119_n_0\ ); \cr_int[11]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(17), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(9), I4 => \cr_int[11]_i_24_n_0\, I5 => \cr_int[11]_i_25_n_0\, O => \cr_int[11]_i_12_n_0\ ); \cr_int[11]_i_120\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_16_n_5\, I1 => \cr_int_reg[3]_i_16_n_4\, O => \cr_int[11]_i_120_n_0\ ); \cr_int[11]_i_121\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_6\, I1 => \cr_int_reg[31]_i_11_n_7\, O => \cr_int[11]_i_121_n_0\ ); \cr_int[11]_i_122\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_4\, I1 => \cr_int_reg[31]_i_30_n_5\, O => \cr_int[11]_i_122_n_0\ ); \cr_int[11]_i_123\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_6\, I1 => \cr_int_reg[31]_i_30_n_7\, O => \cr_int[11]_i_123_n_0\ ); \cr_int[11]_i_124\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_4\, I1 => \cr_int_reg[3]_i_16_n_5\, O => \cr_int[11]_i_124_n_0\ ); \cr_int[11]_i_126\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cr_int_reg[7]_0\(3), I1 => \^cr_int_reg[31]_2\(0), O => \cr_int[11]_i_126_n_0\ ); \cr_int[11]_i_127\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cr_int_reg[7]_0\(1), I1 => \^cr_int_reg[7]_0\(2), O => \cr_int[11]_i_127_n_0\ ); \cr_int[11]_i_128\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cr_int_reg[3]_0\(2), I1 => \^cr_int_reg[7]_0\(0), O => \cr_int[11]_i_128_n_0\ ); \cr_int[11]_i_129\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cr_int_reg[3]_0\(0), I1 => \^cr_int_reg[3]_0\(1), O => \cr_int[11]_i_129_n_0\ ); \cr_int[11]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"8EEE8E888EEE8EEE" ) port map ( I0 => \cr_int_reg3__0\(8), I1 => \cr_int[11]_i_27_n_0\, I2 => \cr_int_reg[11]_i_16_n_4\, I3 => \^cr_int_reg[27]_2\(0), I4 => \cr_int_reg[11]_i_17_n_0\, I5 => \cr_int_reg[11]_i_18_n_4\, O => \cr_int[11]_i_13_n_0\ ); \cr_int[11]_i_130\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(0), I1 => \^cr_int_reg[7]_0\(3), O => \cr_int[11]_i_130_n_0\ ); \cr_int[11]_i_131\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(2), I1 => \^cr_int_reg[7]_0\(1), O => \cr_int[11]_i_131_n_0\ ); \cr_int[11]_i_132\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(0), I1 => \^cr_int_reg[3]_0\(2), O => \cr_int[11]_i_132_n_0\ ); \cr_int[11]_i_133\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[3]_0\(1), I1 => \^cr_int_reg[3]_0\(0), O => \cr_int[11]_i_133_n_0\ ); \cr_int[11]_i_134\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_39_n_4\, I1 => \cr_int_reg[31]_i_14_n_7\, O => \cr_int[11]_i_134_n_0\ ); \cr_int[11]_i_135\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_39_n_6\, I1 => \cr_int_reg[31]_i_39_n_5\, O => \cr_int[11]_i_135_n_0\ ); \cr_int[11]_i_136\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_86_n_6\, I1 => \cr_int_reg[31]_i_39_n_7\, O => \cr_int[11]_i_136_n_0\ ); \cr_int[11]_i_137\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rgb888(0), I1 => \cr_int_reg[31]_i_86_n_7\, O => \cr_int[11]_i_137_n_0\ ); \cr_int[11]_i_138\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_7\, I1 => \cr_int_reg[31]_i_39_n_4\, O => \cr_int[11]_i_138_n_0\ ); \cr_int[11]_i_139\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_5\, I1 => \cr_int_reg[31]_i_39_n_6\, O => \cr_int[11]_i_139_n_0\ ); \cr_int[11]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"6999696669996999" ) port map ( I0 => \cr_int_reg3__0\(8), I1 => \cr_int[11]_i_27_n_0\, I2 => \cr_int_reg[11]_i_16_n_4\, I3 => \^cr_int_reg[27]_2\(0), I4 => \cr_int_reg[11]_i_17_n_0\, I5 => \cr_int_reg[11]_i_18_n_4\, O => \cr_int[11]_i_14_n_0\ ); \cr_int[11]_i_140\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_7\, I1 => \cr_int_reg[31]_i_86_n_6\, O => \cr_int[11]_i_140_n_0\ ); \cr_int[11]_i_141\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_86_n_7\, I1 => rgb888(0), O => \cr_int[11]_i_141_n_0\ ); \cr_int[11]_i_142\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_16_n_7\, I1 => \cr_int_reg[3]_i_16_n_6\, O => \cr_int[11]_i_142_n_0\ ); \cr_int[11]_i_143\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_27_n_7\, I1 => \cr_int_reg[3]_i_27_n_6\, O => \cr_int[11]_i_143_n_0\ ); \cr_int[11]_i_144\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_54_n_5\, I1 => \cr_int_reg[3]_i_54_n_4\, O => \cr_int[11]_i_144_n_0\ ); \cr_int[11]_i_145\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_54_n_7\, I1 => \cr_int_reg[3]_i_54_n_6\, O => \cr_int[11]_i_145_n_0\ ); \cr_int[11]_i_146\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_6\, I1 => \cr_int_reg[3]_i_16_n_7\, O => \cr_int[11]_i_146_n_0\ ); \cr_int[11]_i_147\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_27_n_6\, I1 => \cr_int_reg[3]_i_27_n_7\, O => \cr_int[11]_i_147_n_0\ ); \cr_int[11]_i_148\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_4\, I1 => \cr_int_reg[3]_i_54_n_5\, O => \cr_int[11]_i_148_n_0\ ); \cr_int[11]_i_149\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_6\, I1 => \cr_int_reg[3]_i_54_n_7\, O => \cr_int[11]_i_149_n_0\ ); \cr_int[11]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_13\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[11]_0\(1), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[31]_2\(0), O => \cr_int[11]_i_15_n_0\ ); \cr_int[11]_i_150\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_33_n_4\, I1 => \cr_int_reg[3]_i_19_n_7\, O => \cr_int[11]_i_150_n_0\ ); \cr_int[11]_i_151\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_33_n_6\, I1 => \cr_int_reg[3]_i_33_n_5\, O => \cr_int[11]_i_151_n_0\ ); \cr_int[11]_i_152\: unisim.vcomponents.LUT3 generic map( INIT => X"BE" ) port map ( I0 => \cr_int_reg[3]_i_65_n_6\, I1 => \cr_int_reg[3]_i_65_n_5\, I2 => rgb888(8), O => \cr_int[11]_i_152_n_0\ ); \cr_int[11]_i_153\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_19_n_7\, I1 => \cr_int_reg[3]_i_33_n_4\, O => \cr_int[11]_i_153_n_0\ ); \cr_int[11]_i_154\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_33_n_5\, I1 => \cr_int_reg[3]_i_33_n_6\, O => \cr_int[11]_i_154_n_0\ ); \cr_int[11]_i_155\: unisim.vcomponents.LUT3 generic map( INIT => X"09" ) port map ( I0 => rgb888(8), I1 => \cr_int_reg[3]_i_65_n_5\, I2 => \cr_int_reg[3]_i_65_n_6\, O => \cr_int[11]_i_155_n_0\ ); \cr_int[11]_i_156\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_94_n_7\, O => \cr_int[11]_i_156_n_0\ ); \cr_int[11]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[11]_i_10_n_0\, I1 => \cr_int[11]_i_11_n_0\, O => \cr_int[11]_i_2_n_0\ ); \cr_int[11]_i_22\: unisim.vcomponents.LUT5 generic map( INIT => X"0DFDF202" ) port map ( I0 => \cr_int_reg[11]_i_18_n_5\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \^cr_int_reg[27]_2\(0), I3 => \cr_int_reg[11]_i_16_n_5\, I4 => \cr_int[11]_i_15_n_0\, O => \cr_int[11]_i_22_n_0\ ); \cr_int[11]_i_23\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF0DFD" ) port map ( I0 => \cr_int_reg[11]_i_18_n_5\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \^cr_int_reg[27]_2\(0), I3 => \cr_int_reg[11]_i_16_n_5\, I4 => \cr_int[11]_i_15_n_0\, O => \cr_int[11]_i_23_n_0\ ); \cr_int[11]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_14\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[11]_0\(3), O => \cr_int[11]_i_24_n_0\ ); \cr_int[11]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[15]_i_38_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]\(0), O => \cr_int[11]_i_25_n_0\ ); \cr_int[11]_i_26\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(8), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_11_n_5\, I3 => cr_int_reg7, I4 => cr_int_reg6(16), O => \cr_int_reg3__0\(8) ); \cr_int[11]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_13\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[11]_0\(2), O => \cr_int[11]_i_27_n_0\ ); \cr_int[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[11]_i_12_n_0\, I1 => \cr_int[11]_i_13_n_0\, O => \cr_int[11]_i_3_n_0\ ); \cr_int[11]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[11]_i_18_n_4\, O => \cr_int[11]_i_32_n_0\ ); \cr_int[11]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[11]_i_18_n_5\, O => \cr_int[11]_i_33_n_0\ ); \cr_int[11]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[11]_i_18_n_6\, O => \cr_int[11]_i_34_n_0\ ); \cr_int[11]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_18_n_7\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_7_n_5\, O => \cr_int[11]_i_35_n_0\ ); \cr_int[11]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_37_n_0\ ); \cr_int[11]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_38_n_0\ ); \cr_int[11]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_39_n_0\ ); \cr_int[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA8A888AAA8AAA" ) port map ( I0 => \cr_int[11]_i_14_n_0\, I1 => \cr_int[11]_i_15_n_0\, I2 => \cr_int_reg[11]_i_16_n_5\, I3 => \^cr_int_reg[27]_2\(0), I4 => \cr_int_reg[11]_i_17_n_0\, I5 => \cr_int_reg[11]_i_18_n_5\, O => \cr_int[11]_i_4_n_0\ ); \cr_int[11]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_40_n_0\ ); \cr_int[11]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_42_n_0\ ); \cr_int[11]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_43_n_0\ ); \cr_int[11]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_44_n_0\ ); \cr_int[11]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_5\, O => \cr_int[11]_i_45_n_0\ ); \cr_int[11]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_5\, O => \cr_int[11]_i_47_n_0\ ); \cr_int[11]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_6\, O => \cr_int[11]_i_48_n_0\ ); \cr_int[11]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_7\, O => \cr_int[11]_i_49_n_0\ ); \cr_int[11]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFE200E200000000" ) port map ( I0 => cr_int_reg6(15), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_11_n_6\, I3 => \cr_int_reg[31]_i_11_n_4\, I4 => cr_int_reg4(7), I5 => \cr_int[11]_i_22_n_0\, O => \cr_int[11]_i_5_n_0\ ); \cr_int[11]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_4\, O => \cr_int[11]_i_50_n_0\ ); \cr_int[11]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_52_n_0\ ); \cr_int[11]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_53_n_0\ ); \cr_int[11]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_54_n_0\ ); \cr_int[11]_i_55\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_55_n_0\ ); \cr_int[11]_i_57\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(16), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_11_n_5\, O => \cr_int[11]_i_57_n_0\ ); \cr_int[11]_i_58\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(15), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_11_n_6\, O => \cr_int[11]_i_58_n_0\ ); \cr_int[11]_i_59\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(14), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_11_n_7\, O => \cr_int[11]_i_59_n_0\ ); \cr_int[11]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[15]_i_16_n_0\, I1 => \cr_int[15]_i_17_n_0\, I2 => \cr_int[11]_i_2_n_0\, O => \cr_int[11]_i_6_n_0\ ); \cr_int[11]_i_60\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(13), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_30_n_4\, O => \cr_int[11]_i_60_n_0\ ); \cr_int[11]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_65_n_0\ ); \cr_int[11]_i_66\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_66_n_0\ ); \cr_int[11]_i_67\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(0), O => \cr_int[11]_i_67_n_0\ ); \cr_int[11]_i_68\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(3), O => \cr_int[11]_i_68_n_0\ ); \cr_int[11]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[11]_i_10_n_0\, I1 => \cr_int[11]_i_11_n_0\, I2 => \cr_int[11]_i_3_n_0\, O => \cr_int[11]_i_7_n_0\ ); \cr_int[11]_i_70\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_70_n_0\ ); \cr_int[11]_i_71\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_71_n_0\ ); \cr_int[11]_i_72\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_72_n_0\ ); \cr_int[11]_i_73\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_73_n_0\ ); \cr_int[11]_i_74\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[3]_i_32_n_4\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_14_n_6\, O => \cr_int[11]_i_74_n_0\ ); \cr_int[11]_i_75\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_41_n_4\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_7_n_6\, O => \cr_int[11]_i_75_n_0\ ); \cr_int[11]_i_76\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_41_n_5\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_7_n_7\, O => \cr_int[11]_i_76_n_0\ ); \cr_int[11]_i_77\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_41_n_6\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_14_n_4\, O => \cr_int[11]_i_77_n_0\ ); \cr_int[11]_i_78\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_41_n_7\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_14_n_5\, O => \cr_int[11]_i_78_n_0\ ); \cr_int[11]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[11]_i_12_n_0\, I1 => \cr_int[11]_i_13_n_0\, I2 => \cr_int[11]_i_4_n_0\, O => \cr_int[11]_i_8_n_0\ ); \cr_int[11]_i_80\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_80_n_0\ ); \cr_int[11]_i_81\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_81_n_0\ ); \cr_int[11]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_82_n_0\ ); \cr_int[11]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_83_n_0\ ); \cr_int[11]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_6\, O => \cr_int[11]_i_84_n_0\ ); \cr_int[11]_i_85\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_7\, O => \cr_int[11]_i_85_n_0\ ); \cr_int[11]_i_86\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_4\, O => \cr_int[11]_i_86_n_0\ ); \cr_int[11]_i_87\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_5\, O => \cr_int[11]_i_87_n_0\ ); \cr_int[11]_i_88\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_5\, O => \cr_int[11]_i_88_n_0\ ); \cr_int[11]_i_89\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_6\, O => \cr_int[11]_i_89_n_0\ ); \cr_int[11]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[11]_i_5_n_0\, I1 => \cr_int[11]_i_14_n_0\, I2 => \cr_int[11]_i_23_n_0\, O => \cr_int[11]_i_9_n_0\ ); \cr_int[11]_i_90\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_7\, O => \cr_int[11]_i_90_n_0\ ); \cr_int[11]_i_91\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_4\, O => \cr_int[11]_i_91_n_0\ ); \cr_int[11]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_11_n_5\, I1 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_93_n_0\ ); \cr_int[11]_i_94\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_94_n_0\ ); \cr_int[11]_i_95\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_95_n_0\ ); \cr_int[11]_i_96\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_96_n_0\ ); \cr_int[11]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => \cr_int_reg[31]_i_11_n_5\, O => \cr_int[11]_i_97_n_0\ ); \cr_int[11]_i_98\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(8), I1 => cr_int_reg7, I2 => \cr_int_reg[3]_i_16_n_5\, O => \cr_int[11]_i_98_n_0\ ); \cr_int[11]_i_99\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(12), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_30_n_5\, O => \cr_int[11]_i_99_n_0\ ); \cr_int[15]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(22), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(14), I4 => \cr_int[19]_i_26_n_0\, I5 => \cr_int[19]_i_27_n_0\, O => \cr_int[15]_i_10_n_0\ ); \cr_int[15]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(21), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(13), I4 => \cr_int[15]_i_18_n_0\, I5 => \cr_int[15]_i_19_n_0\, O => \cr_int[15]_i_11_n_0\ ); \cr_int[15]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(21), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(13), I4 => \cr_int[15]_i_18_n_0\, I5 => \cr_int[15]_i_19_n_0\, O => \cr_int[15]_i_12_n_0\ ); \cr_int[15]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(20), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(12), I4 => \cr_int[15]_i_22_n_0\, I5 => \cr_int[15]_i_23_n_0\, O => \cr_int[15]_i_13_n_0\ ); \cr_int[15]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(20), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(12), I4 => \cr_int[15]_i_22_n_0\, I5 => \cr_int[15]_i_23_n_0\, O => \cr_int[15]_i_14_n_0\ ); \cr_int[15]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(19), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(11), I4 => \cr_int[15]_i_24_n_0\, I5 => \cr_int[15]_i_25_n_0\, O => \cr_int[15]_i_15_n_0\ ); \cr_int[15]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(19), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(11), I4 => \cr_int[15]_i_24_n_0\, I5 => \cr_int[15]_i_25_n_0\, O => \cr_int[15]_i_16_n_0\ ); \cr_int[15]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(18), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(10), I4 => \cr_int[15]_i_26_n_0\, I5 => \cr_int[15]_i_27_n_0\, O => \cr_int[15]_i_17_n_0\ ); \cr_int[15]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_15\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[15]_0\(3), O => \cr_int[15]_i_18_n_0\ ); \cr_int[15]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_49_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]_0\(0), O => \cr_int[15]_i_19_n_0\ ); \cr_int[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[15]_i_10_n_0\, I1 => \cr_int[15]_i_11_n_0\, O => \cr_int[15]_i_2_n_0\ ); \cr_int[15]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_14\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[15]_0\(2), O => \cr_int[15]_i_22_n_0\ ); \cr_int[15]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[15]_i_38_n_4\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]\(3), O => \cr_int[15]_i_23_n_0\ ); \cr_int[15]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_14\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[15]_0\(1), O => \cr_int[15]_i_24_n_0\ ); \cr_int[15]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[15]_i_38_n_5\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]\(2), O => \cr_int[15]_i_25_n_0\ ); \cr_int[15]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_14\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[15]_0\(0), O => \cr_int[15]_i_26_n_0\ ); \cr_int[15]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[15]_i_38_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]\(1), O => \cr_int[15]_i_27_n_0\ ); \cr_int[15]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[15]_i_29_n_0\ ); \cr_int[15]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[15]_i_12_n_0\, I1 => \cr_int[15]_i_13_n_0\, O => \cr_int[15]_i_3_n_0\ ); \cr_int[15]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[15]_i_30_n_0\ ); \cr_int[15]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[15]_i_31_n_0\ ); \cr_int[15]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[15]_i_32_n_0\ ); \cr_int[15]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(20), O => \cr_int[15]_i_33_n_0\ ); \cr_int[15]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(19), O => \cr_int[15]_i_34_n_0\ ); \cr_int[15]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(18), O => \cr_int[15]_i_35_n_0\ ); \cr_int[15]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(17), O => \cr_int[15]_i_36_n_0\ ); \cr_int[15]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[15]_i_14_n_0\, I1 => \cr_int[15]_i_15_n_0\, O => \cr_int[15]_i_4_n_0\ ); \cr_int[15]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[15]_i_40_n_0\ ); \cr_int[15]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[15]_i_41_n_0\ ); \cr_int[15]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[15]_i_42_n_0\ ); \cr_int[15]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[15]_i_43_n_0\ ); \cr_int[15]_i_48\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]\(3), O => \cr_int[15]_i_48_n_0\ ); \cr_int[15]_i_49\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]\(2), O => \cr_int[15]_i_49_n_0\ ); \cr_int[15]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[15]_i_16_n_0\, I1 => \cr_int[15]_i_17_n_0\, O => \cr_int[15]_i_5_n_0\ ); \cr_int[15]_i_50\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]\(1), O => \cr_int[15]_i_50_n_0\ ); \cr_int[15]_i_51\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]\(0), O => \cr_int[15]_i_51_n_0\ ); \cr_int[15]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[19]_i_16_n_0\, I1 => \cr_int[19]_i_17_n_0\, I2 => \cr_int[15]_i_2_n_0\, O => \cr_int[15]_i_6_n_0\ ); \cr_int[15]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[15]_i_10_n_0\, I1 => \cr_int[15]_i_11_n_0\, I2 => \cr_int[15]_i_3_n_0\, O => \cr_int[15]_i_7_n_0\ ); \cr_int[15]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[15]_i_12_n_0\, I1 => \cr_int[15]_i_13_n_0\, I2 => \cr_int[15]_i_4_n_0\, O => \cr_int[15]_i_8_n_0\ ); \cr_int[15]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[15]_i_14_n_0\, I1 => \cr_int[15]_i_15_n_0\, I2 => \cr_int[15]_i_5_n_0\, O => \cr_int[15]_i_9_n_0\ ); \cr_int[19]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(26), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(18), I4 => \cr_int[23]_i_25_n_0\, I5 => \cr_int[23]_i_26_n_0\, O => \cr_int[19]_i_10_n_0\ ); \cr_int[19]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(25), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(17), I4 => \cr_int[19]_i_18_n_0\, I5 => \cr_int[19]_i_19_n_0\, O => \cr_int[19]_i_11_n_0\ ); \cr_int[19]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(25), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(17), I4 => \cr_int[19]_i_18_n_0\, I5 => \cr_int[19]_i_19_n_0\, O => \cr_int[19]_i_12_n_0\ ); \cr_int[19]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(24), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(16), I4 => \cr_int[19]_i_22_n_0\, I5 => \cr_int[19]_i_23_n_0\, O => \cr_int[19]_i_13_n_0\ ); \cr_int[19]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(24), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(16), I4 => \cr_int[19]_i_22_n_0\, I5 => \cr_int[19]_i_23_n_0\, O => \cr_int[19]_i_14_n_0\ ); \cr_int[19]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(23), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(15), I4 => \cr_int[19]_i_24_n_0\, I5 => \cr_int[19]_i_25_n_0\, O => \cr_int[19]_i_15_n_0\ ); \cr_int[19]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(23), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(15), I4 => \cr_int[19]_i_24_n_0\, I5 => \cr_int[19]_i_25_n_0\, O => \cr_int[19]_i_16_n_0\ ); \cr_int[19]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(22), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(14), I4 => \cr_int[19]_i_26_n_0\, I5 => \cr_int[19]_i_27_n_0\, O => \cr_int[19]_i_17_n_0\ ); \cr_int[19]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_16\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[19]_0\(3), O => \cr_int[19]_i_18_n_0\ ); \cr_int[19]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_21_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_5\(0), O => \cr_int[19]_i_19_n_0\ ); \cr_int[19]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[19]_i_10_n_0\, I1 => \cr_int[19]_i_11_n_0\, O => \cr_int[19]_i_2_n_0\ ); \cr_int[19]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_15\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[19]_0\(2), O => \cr_int[19]_i_22_n_0\ ); \cr_int[19]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_49_n_4\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]_0\(3), O => \cr_int[19]_i_23_n_0\ ); \cr_int[19]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_15\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[19]_0\(1), O => \cr_int[19]_i_24_n_0\ ); \cr_int[19]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_49_n_5\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]_0\(2), O => \cr_int[19]_i_25_n_0\ ); \cr_int[19]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_15\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[19]_0\(0), O => \cr_int[19]_i_26_n_0\ ); \cr_int[19]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_49_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]_0\(1), O => \cr_int[19]_i_27_n_0\ ); \cr_int[19]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[19]_i_29_n_0\ ); \cr_int[19]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[19]_i_12_n_0\, I1 => \cr_int[19]_i_13_n_0\, O => \cr_int[19]_i_3_n_0\ ); \cr_int[19]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[19]_i_30_n_0\ ); \cr_int[19]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[19]_i_31_n_0\ ); \cr_int[19]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[19]_i_32_n_0\ ); \cr_int[19]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(24), O => \cr_int[19]_i_33_n_0\ ); \cr_int[19]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(23), O => \cr_int[19]_i_34_n_0\ ); \cr_int[19]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(22), O => \cr_int[19]_i_35_n_0\ ); \cr_int[19]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(21), O => \cr_int[19]_i_36_n_0\ ); \cr_int[19]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[19]_i_38_n_0\ ); \cr_int[19]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[19]_i_39_n_0\ ); \cr_int[19]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[19]_i_14_n_0\, I1 => \cr_int[19]_i_15_n_0\, O => \cr_int[19]_i_4_n_0\ ); \cr_int[19]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[19]_i_40_n_0\ ); \cr_int[19]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[19]_i_41_n_0\ ); \cr_int[19]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[19]_i_16_n_0\, I1 => \cr_int[19]_i_17_n_0\, O => \cr_int[19]_i_5_n_0\ ); \cr_int[19]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[23]_i_16_n_0\, I1 => \cr_int[23]_i_17_n_0\, I2 => \cr_int[19]_i_2_n_0\, O => \cr_int[19]_i_6_n_0\ ); \cr_int[19]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[19]_i_10_n_0\, I1 => \cr_int[19]_i_11_n_0\, I2 => \cr_int[19]_i_3_n_0\, O => \cr_int[19]_i_7_n_0\ ); \cr_int[19]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[19]_i_12_n_0\, I1 => \cr_int[19]_i_13_n_0\, I2 => \cr_int[19]_i_4_n_0\, O => \cr_int[19]_i_8_n_0\ ); \cr_int[19]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[19]_i_14_n_0\, I1 => \cr_int[19]_i_15_n_0\, I2 => \cr_int[19]_i_5_n_0\, O => \cr_int[19]_i_9_n_0\ ); \cr_int[23]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(30), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(22), I4 => \cr_int[27]_i_10_n_0\, I5 => \cr_int[27]_i_11_n_0\, O => \cr_int[23]_i_10_n_0\ ); \cr_int[23]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(29), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(21), I4 => \cr_int[23]_i_18_n_0\, I5 => \cr_int[23]_i_19_n_0\, O => \cr_int[23]_i_11_n_0\ ); \cr_int[23]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(29), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(21), I4 => \cr_int[23]_i_18_n_0\, I5 => \cr_int[23]_i_19_n_0\, O => \cr_int[23]_i_12_n_0\ ); \cr_int[23]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(28), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(20), I4 => \cr_int[23]_i_21_n_0\, I5 => \cr_int[23]_i_22_n_0\, O => \cr_int[23]_i_13_n_0\ ); \cr_int[23]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(28), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(20), I4 => \cr_int[23]_i_21_n_0\, I5 => \cr_int[23]_i_22_n_0\, O => \cr_int[23]_i_14_n_0\ ); \cr_int[23]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(27), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(19), I4 => \cr_int[23]_i_23_n_0\, I5 => \cr_int[23]_i_24_n_0\, O => \cr_int[23]_i_15_n_0\ ); \cr_int[23]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(27), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(19), I4 => \cr_int[23]_i_23_n_0\, I5 => \cr_int[23]_i_24_n_0\, O => \cr_int[23]_i_16_n_0\ ); \cr_int[23]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(26), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(18), I4 => \cr_int[23]_i_25_n_0\, I5 => \cr_int[23]_i_26_n_0\, O => \cr_int[23]_i_17_n_0\ ); \cr_int[23]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_17\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_0\(3), O => \cr_int[23]_i_18_n_0\ ); \cr_int[23]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_8_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_6\(0), O => \cr_int[23]_i_19_n_0\ ); \cr_int[23]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[23]_i_10_n_0\, I1 => \cr_int[23]_i_11_n_0\, O => \cr_int[23]_i_2_n_0\ ); \cr_int[23]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_16\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_0\(2), O => \cr_int[23]_i_21_n_0\ ); \cr_int[23]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_21_n_4\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_5\(3), O => \cr_int[23]_i_22_n_0\ ); \cr_int[23]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_16\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_0\(1), O => \cr_int[23]_i_23_n_0\ ); \cr_int[23]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_21_n_5\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_5\(2), O => \cr_int[23]_i_24_n_0\ ); \cr_int[23]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_16\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_0\(0), O => \cr_int[23]_i_25_n_0\ ); \cr_int[23]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_21_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_5\(1), O => \cr_int[23]_i_26_n_0\ ); \cr_int[23]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[23]_i_27_n_0\ ); \cr_int[23]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[23]_i_28_n_0\ ); \cr_int[23]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[23]_i_29_n_0\ ); \cr_int[23]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[23]_i_12_n_0\, I1 => \cr_int[23]_i_13_n_0\, O => \cr_int[23]_i_3_n_0\ ); \cr_int[23]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[23]_i_30_n_0\ ); \cr_int[23]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[23]_i_14_n_0\, I1 => \cr_int[23]_i_15_n_0\, O => \cr_int[23]_i_4_n_0\ ); \cr_int[23]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[23]_i_16_n_0\, I1 => \cr_int[23]_i_17_n_0\, O => \cr_int[23]_i_5_n_0\ ); \cr_int[23]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[27]_i_7_n_0\, I1 => \cr_int[27]_i_8_n_0\, I2 => \cr_int[23]_i_2_n_0\, O => \cr_int[23]_i_6_n_0\ ); \cr_int[23]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[23]_i_10_n_0\, I1 => \cr_int[23]_i_11_n_0\, I2 => \cr_int[23]_i_3_n_0\, O => \cr_int[23]_i_7_n_0\ ); \cr_int[23]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[23]_i_12_n_0\, I1 => \cr_int[23]_i_13_n_0\, I2 => \cr_int[23]_i_4_n_0\, O => \cr_int[23]_i_8_n_0\ ); \cr_int[23]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[23]_i_14_n_0\, I1 => \cr_int[23]_i_15_n_0\, I2 => \cr_int[23]_i_5_n_0\, O => \cr_int[23]_i_9_n_0\ ); \cr_int[27]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_17\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_1\(0), O => \cr_int[27]_i_10_n_0\ ); \cr_int[27]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_8_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_6\(1), O => \cr_int[27]_i_11_n_0\ ); \cr_int[27]_i_12\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[27]_i_12_n_0\ ); \cr_int[27]_i_13\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[27]_i_13_n_0\ ); \cr_int[27]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[27]_i_7_n_0\, I1 => \cr_int[27]_i_8_n_0\, O => \cr_int[27]_i_2_n_0\ ); \cr_int[27]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_3_n_0\ ); \cr_int[27]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_4_n_0\ ); \cr_int[27]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_5_n_0\ ); \cr_int[27]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[27]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_6_n_0\ ); \cr_int[27]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"4B44B4BB4B444B44" ) port map ( I0 => \cr_int_reg[31]_i_12_n_1\, I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \rgb888[8]_18\(0), I3 => \^cr_int_reg[31]_2\(1), I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_7_n_0\ ); \cr_int[27]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(30), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(22), I4 => \cr_int[27]_i_10_n_0\, I5 => \cr_int[27]_i_11_n_0\, O => \cr_int[27]_i_8_n_0\ ); \cr_int[31]_i_100\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => rgb888(13), I1 => rgb888(11), I2 => rgb888(10), I3 => rgb888(12), I4 => rgb888(14), I5 => rgb888(15), O => \cr_int[31]_i_100_n_0\ ); \cr_int[31]_i_103\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \cr_int[31]_i_103_n_0\ ); \cr_int[31]_i_108\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_108_n_0\ ); \cr_int[31]_i_109\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_109_n_0\ ); \cr_int[31]_i_110\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_110_n_0\ ); \cr_int[31]_i_111\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_111_n_0\ ); \cr_int[31]_i_112\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_112_n_0\ ); \cr_int[31]_i_113\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(4), I1 => rgb888(2), O => \cr_int[31]_i_113_n_0\ ); \cr_int[31]_i_114\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(3), I1 => rgb888(1), O => \cr_int[31]_i_114_n_0\ ); \cr_int[31]_i_115\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(2), I1 => rgb888(0), O => \cr_int[31]_i_115_n_0\ ); \cr_int[31]_i_116\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(1), O => \cr_int[31]_i_116_n_0\ ); \cr_int[31]_i_117\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(6), O => \cr_int[31]_i_117_n_0\ ); \cr_int[31]_i_118\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(7), I1 => rgb888(5), O => \cr_int[31]_i_118_n_0\ ); \cr_int[31]_i_119\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(6), I1 => rgb888(4), O => \cr_int[31]_i_119_n_0\ ); \cr_int[31]_i_120\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(5), I1 => rgb888(3), O => \cr_int[31]_i_120_n_0\ ); \cr_int[31]_i_121\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \cr_int[31]_i_121_n_0\ ); \cr_int[31]_i_122\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(15), I1 => rgb888(14), O => \cr_int[31]_i_122_n_0\ ); \cr_int[31]_i_123\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(14), O => \cr_int[31]_i_123_n_0\ ); \cr_int[31]_i_124\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(15), I1 => rgb888(13), O => \cr_int[31]_i_124_n_0\ ); \cr_int[31]_i_125\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(14), I1 => rgb888(12), O => \cr_int[31]_i_125_n_0\ ); \cr_int[31]_i_126\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(13), I1 => rgb888(11), O => \cr_int[31]_i_126_n_0\ ); \cr_int[31]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \rgb888[8]_18\(0), I1 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_13_n_0\ ); \cr_int[31]_i_15\: unisim.vcomponents.LUT3 generic map( INIT => X"60" ) port map ( I0 => \^cr_int_reg[27]_0\, I1 => rgb888(7), I2 => \cr_int_reg[31]_i_48_n_2\, O => \cr_int[31]_i_15_n_0\ ); \cr_int[31]_i_16\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_1\(1), I1 => \cr_int_reg[31]_i_48_n_2\, O => \cr_int[31]_i_16_n_0\ ); \cr_int[31]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => \^cr_int_reg[27]_0\, O => \cr_int[31]_i_17_n_0\ ); \cr_int[31]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => \^cr_int_reg[27]_0\, O => \cr_int[31]_i_18_n_0\ ); \cr_int[31]_i_19\: unisim.vcomponents.LUT3 generic map( INIT => X"17" ) port map ( I0 => \cr_int_reg[31]_i_48_n_2\, I1 => \^cr_int_reg[27]_0\, I2 => rgb888(7), O => \cr_int[31]_i_19_n_0\ ); \cr_int[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000DD0D0000" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[31]_i_8_n_1\, I2 => \^cr_int_reg[31]_2\(1), I3 => \rgb888[8]_18\(0), I4 => \cr_int_reg[31]_i_11_n_4\, I5 => \cr_int_reg[31]_i_12_n_1\, O => \cr_int[31]_i_2_n_0\ ); \cr_int[31]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \^cr_int_reg[27]_0\, I1 => rgb888(7), I2 => \cr_int[31]_i_16_n_0\, I3 => \cr_int_reg[31]_i_48_n_2\, O => \cr_int[31]_i_20_n_0\ ); \cr_int[31]_i_22\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_6\(1), O => \cr_int[31]_i_22_n_0\ ); \cr_int[31]_i_23\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_6\(0), O => \cr_int[31]_i_23_n_0\ ); \cr_int[31]_i_25\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \cr_int[31]_i_25_n_0\ ); \cr_int[31]_i_26\: unisim.vcomponents.LUT2 generic map( INIT => X"4" ) port map ( I0 => \cr_int_reg[31]_i_63_n_2\, I1 => \^di\(0), O => \cr_int[31]_i_26_n_0\ ); \cr_int[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[31]_i_3_n_0\ ); \cr_int[31]_i_31\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => rgb888(22), I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(17), I4 => rgb888(19), I5 => rgb888(21), O => \cr_int[31]_i_31_n_0\ ); \cr_int[31]_i_32\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(23), I1 => \cr_int[31]_i_79_n_0\, O => \cr_int[31]_i_32_n_0\ ); \cr_int[31]_i_33\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(23), I1 => \cr_int[31]_i_79_n_0\, O => \cr_int[31]_i_33_n_0\ ); \cr_int[31]_i_34\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(23), I1 => \cr_int[31]_i_79_n_0\, O => \cr_int[31]_i_34_n_0\ ); \cr_int[31]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"95" ) port map ( I0 => rgb888(23), I1 => \cr_int[31]_i_80_n_0\, I2 => rgb888(22), O => \cr_int[31]_i_35_n_0\ ); \cr_int[31]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(30), O => \cr_int[31]_i_37_n_0\ ); \cr_int[31]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(29), O => \cr_int[31]_i_38_n_0\ ); \cr_int[31]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[31]_i_4_n_0\ ); \cr_int[31]_i_40\: unisim.vcomponents.LUT6 generic map( INIT => X"8888888888888882" ) port map ( I0 => \cr_int_reg[31]_i_48_n_7\, I1 => rgb888(5), I2 => rgb888(3), I3 => rgb888(1), I4 => rgb888(2), I5 => rgb888(4), O => \cr_int[31]_i_40_n_0\ ); \cr_int[31]_i_41\: unisim.vcomponents.LUT5 generic map( INIT => X"EEEEEEEB" ) port map ( I0 => \cr_int_reg[31]_i_91_n_4\, I1 => rgb888(4), I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), O => \cr_int[31]_i_41_n_0\ ); \cr_int[31]_i_42\: unisim.vcomponents.LUT5 generic map( INIT => X"99999996" ) port map ( I0 => \cr_int_reg[31]_i_91_n_4\, I1 => rgb888(4), I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), O => \cr_int[31]_i_42_n_0\ ); \cr_int[31]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"82" ) port map ( I0 => \cr_int_reg[31]_i_91_n_6\, I1 => rgb888(2), I2 => rgb888(1), O => \cr_int[31]_i_43_n_0\ ); \cr_int[31]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cr_int_reg[27]_1\(1), I1 => \cr_int_reg[31]_i_48_n_2\, I2 => \cr_int[31]_i_40_n_0\, O => \cr_int[31]_i_44_n_0\ ); \cr_int[31]_i_45\: unisim.vcomponents.LUT4 generic map( INIT => X"1EE1" ) port map ( I0 => \cr_int[31]_i_92_n_0\, I1 => \cr_int_reg[31]_i_91_n_4\, I2 => \^cr_int_reg[27]_1\(0), I3 => \cr_int_reg[31]_i_48_n_7\, O => \cr_int[31]_i_45_n_0\ ); \cr_int[31]_i_46\: unisim.vcomponents.LUT6 generic map( INIT => X"6969699999999996" ) port map ( I0 => rgb888(4), I1 => \cr_int_reg[31]_i_91_n_4\, I2 => \cr_int_reg[31]_i_91_n_5\, I3 => rgb888(2), I4 => rgb888(1), I5 => rgb888(3), O => \cr_int[31]_i_46_n_0\ ); \cr_int[31]_i_47\: unisim.vcomponents.LUT5 generic map( INIT => X"817E7E81" ) port map ( I0 => \cr_int_reg[31]_i_91_n_6\, I1 => rgb888(2), I2 => rgb888(1), I3 => rgb888(3), I4 => \cr_int_reg[31]_i_91_n_5\, O => \cr_int[31]_i_47_n_0\ ); \cr_int[31]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[31]_i_5_n_0\ ); \cr_int[31]_i_50\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_5\(3), O => \cr_int[31]_i_50_n_0\ ); \cr_int[31]_i_51\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_5\(2), O => \cr_int[31]_i_51_n_0\ ); \cr_int[31]_i_52\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_5\(1), O => \cr_int[31]_i_52_n_0\ ); \cr_int[31]_i_53\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_5\(0), O => \cr_int[31]_i_53_n_0\ ); \cr_int[31]_i_55\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int[31]_i_100_n_0\, I1 => \cr_int_reg[31]_i_63_n_2\, O => \cr_int[31]_i_55_n_0\ ); \cr_int[31]_i_56\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAA00000000" ) port map ( I0 => rgb888(14), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => \cr_int_reg[31]_i_63_n_7\, O => \cr_int[31]_i_56_n_0\ ); \cr_int[31]_i_57\: unisim.vcomponents.LUT6 generic map( INIT => X"BFFFEAAA2AAA8000" ) port map ( I0 => \cr_int_reg[31]_i_101_n_1\, I1 => rgb888(11), I2 => rgb888(10), I3 => rgb888(12), I4 => rgb888(13), I5 => \cr_int_reg[31]_i_102_n_4\, O => \cr_int[31]_i_57_n_0\ ); \cr_int[31]_i_58\: unisim.vcomponents.LUT5 generic map( INIT => X"BFEA2A80" ) port map ( I0 => \cr_int_reg[31]_i_101_n_6\, I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(12), I4 => \cr_int_reg[31]_i_102_n_5\, O => \cr_int[31]_i_58_n_0\ ); \cr_int[31]_i_59\: unisim.vcomponents.LUT3 generic map( INIT => X"36" ) port map ( I0 => \cr_int[31]_i_100_n_0\, I1 => \^di\(0), I2 => \cr_int_reg[31]_i_63_n_2\, O => \cr_int[31]_i_59_n_0\ ); \cr_int[31]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[31]_i_6_n_0\ ); \cr_int[31]_i_60\: unisim.vcomponents.LUT4 generic map( INIT => X"7887" ) port map ( I0 => \cr_int_reg[31]_i_63_n_7\, I1 => \^cr_int_reg[31]_0\, I2 => \cr_int_reg[31]_i_63_n_2\, I3 => \cr_int[31]_i_100_n_0\, O => \cr_int[31]_i_60_n_0\ ); \cr_int[31]_i_61\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[31]_i_57_n_0\, I1 => \^cr_int_reg[31]_0\, I2 => \cr_int_reg[31]_i_63_n_7\, O => \cr_int[31]_i_61_n_0\ ); \cr_int[31]_i_62\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int[31]_i_58_n_0\, I1 => \cr_int_reg[31]_i_102_n_4\, I2 => \^cr_int_reg[31]_1\, I3 => \cr_int_reg[31]_i_101_n_1\, O => \cr_int[31]_i_62_n_0\ ); \cr_int[31]_i_71\: unisim.vcomponents.LUT6 generic map( INIT => X"00000001FFFFFFFE" ) port map ( I0 => rgb888(21), I1 => rgb888(19), I2 => rgb888(17), I3 => rgb888(18), I4 => rgb888(20), I5 => rgb888(22), O => \cr_int[31]_i_71_n_0\ ); \cr_int[31]_i_72\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFE" ) port map ( I0 => rgb888(20), I1 => rgb888(18), I2 => rgb888(17), I3 => rgb888(19), I4 => rgb888(21), O => \cr_int[31]_i_72_n_0\ ); \cr_int[31]_i_73\: unisim.vcomponents.LUT5 generic map( INIT => X"99999996" ) port map ( I0 => \cr_int_reg[3]_i_26_n_1\, I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(17), I4 => rgb888(19), O => \cr_int[31]_i_73_n_0\ ); \cr_int[31]_i_74\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(18), I1 => rgb888(17), O => \cr_int[31]_i_74_n_0\ ); \cr_int[31]_i_75\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAA955555555" ) port map ( I0 => rgb888(22), I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(17), I4 => rgb888(19), I5 => rgb888(21), O => \cr_int[31]_i_75_n_0\ ); \cr_int[31]_i_76\: unisim.vcomponents.LUT6 generic map( INIT => X"CCCCCCC999999993" ) port map ( I0 => \cr_int_reg[3]_i_26_n_1\, I1 => rgb888(21), I2 => rgb888(19), I3 => rgb888(17), I4 => rgb888(18), I5 => rgb888(20), O => \cr_int[31]_i_76_n_0\ ); \cr_int[31]_i_77\: unisim.vcomponents.LUT5 generic map( INIT => X"AAA99995" ) port map ( I0 => rgb888(20), I1 => \cr_int_reg[3]_i_26_n_1\, I2 => rgb888(18), I3 => rgb888(17), I4 => rgb888(19), O => \cr_int[31]_i_77_n_0\ ); \cr_int[31]_i_78\: unisim.vcomponents.LUT4 generic map( INIT => X"6A95" ) port map ( I0 => \cr_int_reg[3]_i_26_n_1\, I1 => rgb888(18), I2 => rgb888(17), I3 => rgb888(19), O => \cr_int[31]_i_78_n_0\ ); \cr_int[31]_i_79\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => rgb888(21), I1 => rgb888(19), I2 => rgb888(17), I3 => rgb888(18), I4 => rgb888(20), I5 => rgb888(22), O => \cr_int[31]_i_79_n_0\ ); \cr_int[31]_i_80\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => rgb888(20), I1 => rgb888(18), I2 => rgb888(17), I3 => rgb888(19), I4 => rgb888(21), O => \cr_int[31]_i_80_n_0\ ); \cr_int[31]_i_81\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(28), O => \cr_int[31]_i_81_n_0\ ); \cr_int[31]_i_82\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(27), O => \cr_int[31]_i_82_n_0\ ); \cr_int[31]_i_83\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(26), O => \cr_int[31]_i_83_n_0\ ); \cr_int[31]_i_84\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(25), O => \cr_int[31]_i_84_n_0\ ); \cr_int[31]_i_85\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), O => \cr_int[31]_i_85_n_0\ ); \cr_int[31]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(2), I1 => \cr_int_reg[31]_i_91_n_6\, O => \cr_int[31]_i_87_n_0\ ); \cr_int[31]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(1), I1 => \cr_int_reg[31]_i_91_n_7\, O => \cr_int[31]_i_88_n_0\ ); \cr_int[31]_i_89\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[31]_i_86_n_4\, I1 => rgb888(0), O => \cr_int[31]_i_89_n_0\ ); \cr_int[31]_i_90\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg[31]_i_86_n_5\, O => \cr_int[31]_i_90_n_0\ ); \cr_int[31]_i_92\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => rgb888(3), I1 => rgb888(1), I2 => rgb888(2), I3 => rgb888(4), O => \cr_int[31]_i_92_n_0\ ); \cr_int[31]_i_93\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(7), O => \cr_int[31]_i_93_n_0\ ); \cr_int[31]_i_94\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]_0\(3), O => \cr_int[31]_i_94_n_0\ ); \cr_int[31]_i_95\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]_0\(2), O => \cr_int[31]_i_95_n_0\ ); \cr_int[31]_i_96\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]_0\(1), O => \cr_int[31]_i_96_n_0\ ); \cr_int[31]_i_97\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]_0\(0), O => \cr_int[31]_i_97_n_0\ ); \cr_int[3]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_12\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[7]_1\(0), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[3]_0\(2), O => \cr_int[3]_i_10_n_0\ ); \cr_int[3]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_31_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_41_n_6\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_14_n_4\, O => \cr_int[3]_i_11_n_0\ ); \cr_int[3]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(1), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[3]_i_16_n_4\, I3 => cr_int_reg7, I4 => cr_int_reg6(9), O => \cr_int_reg3__0\(1) ); \cr_int[3]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_12\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_2\(1), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[3]_0\(1), O => \cr_int[3]_i_13_n_0\ ); \cr_int[3]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_31_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_41_n_7\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_14_n_5\, O => \cr_int[3]_i_14_n_0\ ); \cr_int[3]_i_17\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^cr_int_reg[3]_0\(0), I1 => \^cr_int_reg[3]_1\(0), I2 => \^cr_int_reg[3]_2\(0), O => \cr_int[3]_i_17_n_0\ ); \cr_int[3]_i_18\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cr_int_reg[31]_i_14_n_6\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[3]_i_32_n_4\, O => \cr_int[3]_i_18_n_0\ ); \cr_int[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(2), I1 => \cr_int[3]_i_10_n_0\, I2 => \cr_int[3]_i_11_n_0\, O => \cr_int[3]_i_2_n_0\ ); \cr_int[3]_i_22\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_5\, O => \cr_int[3]_i_22_n_0\ ); \cr_int[3]_i_23\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_6\, O => \cr_int[3]_i_23_n_0\ ); \cr_int[3]_i_24\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_7\, O => \cr_int[3]_i_24_n_0\ ); \cr_int[3]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_27_n_6\, O => \cr_int[3]_i_25_n_0\ ); \cr_int[3]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(18), I1 => rgb888(17), I2 => \cr_int_reg[3]_i_26_n_6\, O => \cr_int[3]_i_28_n_0\ ); \cr_int[3]_i_29\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \cr_int_reg[3]_i_26_n_7\, I1 => rgb888(17), O => \cr_int[3]_i_29_n_0\ ); \cr_int[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(1), I1 => \cr_int[3]_i_13_n_0\, I2 => \cr_int[3]_i_14_n_0\, O => \cr_int[3]_i_3_n_0\ ); \cr_int[3]_i_30\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[3]_i_27_n_4\, I1 => rgb888(16), O => \cr_int[3]_i_30_n_0\ ); \cr_int[3]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg[3]_i_27_n_5\, O => \cr_int[3]_i_31_n_0\ ); \cr_int[3]_i_34\: unisim.vcomponents.LUT4 generic map( INIT => X"BE28" ) port map ( I0 => \cr_int_reg[31]_i_101_n_7\, I1 => rgb888(10), I2 => rgb888(11), I3 => \cr_int_reg[31]_i_102_n_6\, O => \cr_int[3]_i_34_n_0\ ); \cr_int[3]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => rgb888(10), I1 => \cr_int_reg[3]_i_64_n_4\, I2 => \cr_int_reg[31]_i_102_n_7\, O => \cr_int[3]_i_35_n_0\ ); \cr_int[3]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg[3]_i_64_n_5\, I1 => rgb888(9), I2 => \cr_int_reg[3]_i_70_n_4\, O => \cr_int[3]_i_36_n_0\ ); \cr_int[3]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int_reg[3]_i_64_n_5\, I1 => rgb888(9), I2 => \cr_int_reg[3]_i_70_n_4\, O => \cr_int[3]_i_37_n_0\ ); \cr_int[3]_i_38\: unisim.vcomponents.LUT6 generic map( INIT => X"9669696969969696" ) port map ( I0 => \cr_int[3]_i_34_n_0\, I1 => \cr_int_reg[31]_i_102_n_5\, I2 => rgb888(12), I3 => rgb888(11), I4 => rgb888(10), I5 => \cr_int_reg[31]_i_101_n_6\, O => \cr_int[3]_i_38_n_0\ ); \cr_int[3]_i_39\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \cr_int_reg[31]_i_101_n_7\, I1 => rgb888(10), I2 => rgb888(11), I3 => \cr_int_reg[31]_i_102_n_6\, I4 => \cr_int[3]_i_35_n_0\, O => \cr_int[3]_i_39_n_0\ ); \cr_int[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"00E2E2FF" ) port map ( I0 => cr_int_reg6(8), I1 => cr_int_reg7, I2 => \cr_int_reg[3]_i_16_n_5\, I3 => \cr_int[3]_i_17_n_0\, I4 => \cr_int[3]_i_18_n_0\, O => \cr_int[3]_i_4_n_0\ ); \cr_int[3]_i_40\: unisim.vcomponents.LUT6 generic map( INIT => X"E81717E817E8E817" ) port map ( I0 => \cr_int_reg[3]_i_70_n_4\, I1 => rgb888(9), I2 => \cr_int_reg[3]_i_64_n_5\, I3 => \cr_int_reg[31]_i_102_n_7\, I4 => rgb888(10), I5 => \cr_int_reg[3]_i_64_n_4\, O => \cr_int[3]_i_40_n_0\ ); \cr_int[3]_i_41\: unisim.vcomponents.LUT5 generic map( INIT => X"69969696" ) port map ( I0 => \cr_int_reg[3]_i_70_n_4\, I1 => rgb888(9), I2 => \cr_int_reg[3]_i_64_n_5\, I3 => \cr_int_reg[3]_i_70_n_5\, I4 => rgb888(8), O => \cr_int[3]_i_41_n_0\ ); \cr_int[3]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[3]_0\(1), O => \cr_int[3]_i_43_n_0\ ); \cr_int[3]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[3]_0\(0), O => \cr_int[3]_i_44_n_0\ ); \cr_int[3]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_19_n_7\, O => \cr_int[3]_i_45_n_0\ ); \cr_int[3]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_33_n_4\, O => \cr_int[3]_i_46_n_0\ ); \cr_int[3]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_7\, O => \cr_int[3]_i_47_n_0\ ); \cr_int[3]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_27_n_7\, O => \cr_int[3]_i_48_n_0\ ); \cr_int[3]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_4\, O => \cr_int[3]_i_49_n_0\ ); \cr_int[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(3), I1 => \cr_int[7]_i_17_n_0\, I2 => \cr_int[7]_i_18_n_0\, I3 => \cr_int[3]_i_2_n_0\, O => \cr_int[3]_i_5_n_0\ ); \cr_int[3]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_5\, O => \cr_int[3]_i_50_n_0\ ); \cr_int[3]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_6\, O => \cr_int[3]_i_51_n_0\ ); \cr_int[3]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(23), O => \cr_int[3]_i_52_n_0\ ); \cr_int[3]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(22), O => \cr_int[3]_i_53_n_0\ ); \cr_int[3]_i_55\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(21), I1 => rgb888(23), O => \cr_int[3]_i_55_n_0\ ); \cr_int[3]_i_56\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(20), I1 => rgb888(22), O => \cr_int[3]_i_56_n_0\ ); \cr_int[3]_i_57\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(19), I1 => rgb888(21), O => \cr_int[3]_i_57_n_0\ ); \cr_int[3]_i_58\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(18), I1 => rgb888(20), O => \cr_int[3]_i_58_n_0\ ); \cr_int[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(2), I1 => \cr_int[3]_i_10_n_0\, I2 => \cr_int[3]_i_11_n_0\, I3 => \cr_int[3]_i_3_n_0\, O => \cr_int[3]_i_6_n_0\ ); \cr_int[3]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_6\, O => \cr_int[3]_i_60_n_0\ ); \cr_int[3]_i_61\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_7\, O => \cr_int[3]_i_61_n_0\ ); \cr_int[3]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_4\, O => \cr_int[3]_i_62_n_0\ ); \cr_int[3]_i_63\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_5\, O => \cr_int[3]_i_63_n_0\ ); \cr_int[3]_i_66\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(8), I1 => \cr_int_reg[3]_i_70_n_5\, I2 => \cr_int_reg[3]_i_64_n_6\, O => \cr_int[3]_i_66_n_0\ ); \cr_int[3]_i_67\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[3]_i_64_n_7\, I1 => \cr_int_reg[3]_i_70_n_6\, O => \cr_int[3]_i_67_n_0\ ); \cr_int[3]_i_68\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[3]_i_65_n_4\, I1 => \cr_int_reg[3]_i_70_n_7\, O => \cr_int[3]_i_68_n_0\ ); \cr_int[3]_i_69\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[3]_i_65_n_5\, I1 => rgb888(8), O => \cr_int[3]_i_69_n_0\ ); \cr_int[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(1), I1 => \cr_int[3]_i_13_n_0\, I2 => \cr_int[3]_i_14_n_0\, I3 => \cr_int[3]_i_4_n_0\, O => \cr_int[3]_i_7_n_0\ ); \cr_int[3]_i_71\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_94_n_7\, O => \cr_int[3]_i_71_n_0\ ); \cr_int[3]_i_72\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_33_n_5\, O => \cr_int[3]_i_72_n_0\ ); \cr_int[3]_i_73\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_33_n_6\, O => \cr_int[3]_i_73_n_0\ ); \cr_int[3]_i_74\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(8), I1 => \cr_int_reg[3]_i_65_n_5\, O => \cr_int[3]_i_74_n_0\ ); \cr_int[3]_i_75\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_65_n_6\, O => \cr_int[3]_i_75_n_0\ ); \cr_int[3]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(17), I1 => rgb888(19), O => \cr_int[3]_i_76_n_0\ ); \cr_int[3]_i_77\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(16), I1 => rgb888(18), O => \cr_int[3]_i_77_n_0\ ); \cr_int[3]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(17), O => \cr_int[3]_i_78_n_0\ ); \cr_int[3]_i_79\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(16), O => \cr_int[3]_i_79_n_0\ ); \cr_int[3]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"1DE2E21D" ) port map ( I0 => cr_int_reg6(8), I1 => cr_int_reg7, I2 => \cr_int_reg[3]_i_16_n_5\, I3 => \cr_int[3]_i_17_n_0\, I4 => \cr_int[3]_i_18_n_0\, O => \cr_int[3]_i_8_n_0\ ); \cr_int[3]_i_80\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(0), O => \cr_int[3]_i_80_n_0\ ); \cr_int[3]_i_81\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_6\, O => \cr_int[3]_i_81_n_0\ ); \cr_int[3]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_7\, O => \cr_int[3]_i_82_n_0\ ); \cr_int[3]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_86_n_6\, O => \cr_int[3]_i_83_n_0\ ); \cr_int[3]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_86_n_7\, O => \cr_int[3]_i_84_n_0\ ); \cr_int[3]_i_85\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(15), I1 => rgb888(13), O => \cr_int[3]_i_85_n_0\ ); \cr_int[3]_i_86\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(12), I1 => rgb888(14), O => \cr_int[3]_i_86_n_0\ ); \cr_int[3]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(11), I1 => rgb888(13), O => \cr_int[3]_i_87_n_0\ ); \cr_int[3]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(10), I1 => rgb888(12), O => \cr_int[3]_i_88_n_0\ ); \cr_int[3]_i_89\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(9), I1 => rgb888(11), O => \cr_int[3]_i_89_n_0\ ); \cr_int[3]_i_9\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(2), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_30_n_7\, I3 => cr_int_reg7, I4 => cr_int_reg6(10), O => \cr_int_reg3__0\(2) ); \cr_int[3]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(8), I1 => rgb888(10), O => \cr_int[3]_i_90_n_0\ ); \cr_int[3]_i_91\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(9), O => \cr_int[3]_i_91_n_0\ ); \cr_int[3]_i_92\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(8), O => \cr_int[3]_i_92_n_0\ ); \cr_int[3]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(12), I1 => rgb888(10), O => \cr_int[3]_i_93_n_0\ ); \cr_int[3]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(11), I1 => rgb888(9), O => \cr_int[3]_i_94_n_0\ ); \cr_int[3]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(10), I1 => rgb888(8), O => \cr_int[3]_i_95_n_0\ ); \cr_int[3]_i_96\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(9), O => \cr_int[3]_i_96_n_0\ ); \cr_int[7]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(5), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_30_n_4\, I3 => cr_int_reg7, I4 => cr_int_reg6(13), O => \cr_int_reg3__0\(5) ); \cr_int[7]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_13\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[7]_1\(3), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[7]_0\(2), O => \cr_int[7]_i_11_n_0\ ); \cr_int[7]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_16_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_18_n_7\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_7_n_5\, O => \cr_int[7]_i_12_n_0\ ); \cr_int[7]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(4), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_30_n_5\, I3 => cr_int_reg7, I4 => cr_int_reg6(12), O => \cr_int_reg3__0\(4) ); \cr_int[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_12\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[7]_1\(2), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[7]_0\(1), O => \cr_int[7]_i_14_n_0\ ); \cr_int[7]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_31_n_4\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_41_n_4\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_7_n_6\, O => \cr_int[7]_i_15_n_0\ ); \cr_int[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(3), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_30_n_6\, I3 => cr_int_reg7, I4 => cr_int_reg6(11), O => \cr_int_reg3__0\(3) ); \cr_int[7]_i_17\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_12\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[7]_1\(1), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[7]_0\(0), O => \cr_int[7]_i_17_n_0\ ); \cr_int[7]_i_18\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_31_n_5\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_41_n_5\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_7_n_7\, O => \cr_int[7]_i_18_n_0\ ); \cr_int[7]_i_19\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(7), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_11_n_6\, I3 => cr_int_reg7, I4 => cr_int_reg6(15), O => cr_int_reg3(7) ); \cr_int[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"555556A6AAAA56A6" ) port map ( I0 => \cr_int[11]_i_22_n_0\, I1 => cr_int_reg6(15), I2 => cr_int_reg7, I3 => \cr_int_reg[31]_i_11_n_6\, I4 => \cr_int_reg[31]_i_11_n_4\, I5 => cr_int_reg4(7), O => \cr_int[7]_i_2_n_0\ ); \cr_int[7]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[11]_i_16_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \cr_int_reg[11]_i_18_n_6\, O => \cr_int[7]_i_20_n_0\ ); \cr_int[7]_i_21\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_13\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[11]_0\(0), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[7]_0\(3), O => \cr_int[7]_i_21_n_0\ ); \cr_int[7]_i_22\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(6), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_11_n_7\, I3 => cr_int_reg7, I4 => cr_int_reg6(14), O => \cr_int_reg3__0\(6) ); \cr_int[7]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(2), O => \cr_int[7]_i_25_n_0\ ); \cr_int[7]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(1), O => \cr_int[7]_i_26_n_0\ ); \cr_int[7]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(0), O => \cr_int[7]_i_27_n_0\ ); \cr_int[7]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[3]_0\(2), O => \cr_int[7]_i_28_n_0\ ); \cr_int[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(5), I1 => \cr_int[7]_i_11_n_0\, I2 => \cr_int[7]_i_12_n_0\, O => \cr_int[7]_i_3_n_0\ ); \cr_int[7]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(4), I1 => \cr_int[7]_i_14_n_0\, I2 => \cr_int[7]_i_15_n_0\, O => \cr_int[7]_i_4_n_0\ ); \cr_int[7]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(3), I1 => \cr_int[7]_i_17_n_0\, I2 => \cr_int[7]_i_18_n_0\, O => \cr_int[7]_i_5_n_0\ ); \cr_int[7]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"99969666" ) port map ( I0 => cr_int_reg3(7), I1 => \cr_int[11]_i_22_n_0\, I2 => \cr_int[7]_i_20_n_0\, I3 => \cr_int[7]_i_21_n_0\, I4 => \cr_int_reg3__0\(6), O => \cr_int[7]_i_6_n_0\ ); \cr_int[7]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int[7]_i_3_n_0\, I1 => \cr_int[7]_i_20_n_0\, I2 => \cr_int[7]_i_21_n_0\, I3 => \cr_int_reg3__0\(6), O => \cr_int[7]_i_7_n_0\ ); \cr_int[7]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(5), I1 => \cr_int[7]_i_11_n_0\, I2 => \cr_int[7]_i_12_n_0\, I3 => \cr_int[7]_i_4_n_0\, O => \cr_int[7]_i_8_n_0\ ); \cr_int[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(4), I1 => \cr_int[7]_i_14_n_0\, I2 => \cr_int[7]_i_15_n_0\, I3 => \cr_int[7]_i_5_n_0\, O => \cr_int[7]_i_9_n_0\ ); \cr_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[3]_i_1_n_7\, Q => \cr_int_reg_n_0_[0]\, R => '0' ); \cr_int_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[11]_i_1_n_5\, Q => \cr_int_reg__0\(10), R => '0' ); \cr_int_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[11]_i_1_n_4\, Q => \cr_int_reg__0\(11), R => '0' ); \cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[7]_i_1_n_0\, CO(3) => \cr_int_reg[11]_i_1_n_0\, CO(2) => \cr_int_reg[11]_i_1_n_1\, CO(1) => \cr_int_reg[11]_i_1_n_2\, CO(0) => \cr_int_reg[11]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[11]_i_2_n_0\, DI(2) => \cr_int[11]_i_3_n_0\, DI(1) => \cr_int[11]_i_4_n_0\, DI(0) => \cr_int[11]_i_5_n_0\, O(3) => \cr_int_reg[11]_i_1_n_4\, O(2) => \cr_int_reg[11]_i_1_n_5\, O(1) => \cr_int_reg[11]_i_1_n_6\, O(0) => \cr_int_reg[11]_i_1_n_7\, S(3) => \cr_int[11]_i_6_n_0\, S(2) => \cr_int[11]_i_7_n_0\, S(1) => \cr_int[11]_i_8_n_0\, S(0) => \cr_int[11]_i_9_n_0\ ); \cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_125_n_0\, CO(3) => \cr_int_reg[11]_i_103_n_0\, CO(2) => \cr_int_reg[11]_i_103_n_1\, CO(1) => \cr_int_reg[11]_i_103_n_2\, CO(0) => \cr_int_reg[11]_i_103_n_3\, CYINIT => '0', DI(3) => \cr_int[11]_i_126_n_0\, DI(2) => \cr_int[11]_i_127_n_0\, DI(1) => \cr_int[11]_i_128_n_0\, DI(0) => \cr_int[11]_i_129_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_130_n_0\, S(2) => \cr_int[11]_i_131_n_0\, S(1) => \cr_int[11]_i_132_n_0\, S(0) => \cr_int[11]_i_133_n_0\ ); \cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_108_n_0\, CO(2) => \cr_int_reg[11]_i_108_n_1\, CO(1) => \cr_int_reg[11]_i_108_n_2\, CO(0) => \cr_int_reg[11]_i_108_n_3\, CYINIT => '1', DI(3) => \cr_int[11]_i_134_n_0\, DI(2) => \cr_int[11]_i_135_n_0\, DI(1) => \cr_int[11]_i_136_n_0\, DI(0) => \cr_int[11]_i_137_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_138_n_0\, S(2) => \cr_int[11]_i_139_n_0\, S(1) => \cr_int[11]_i_140_n_0\, S(0) => \cr_int[11]_i_141_n_0\ ); \cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_116_n_0\, CO(2) => \cr_int_reg[11]_i_116_n_1\, CO(1) => \cr_int_reg[11]_i_116_n_2\, CO(0) => \cr_int_reg[11]_i_116_n_3\, CYINIT => '1', DI(3) => \cr_int[11]_i_142_n_0\, DI(2) => \cr_int[11]_i_143_n_0\, DI(1) => \cr_int[11]_i_144_n_0\, DI(0) => \cr_int[11]_i_145_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_146_n_0\, S(2) => \cr_int[11]_i_147_n_0\, S(1) => \cr_int[11]_i_148_n_0\, S(0) => \cr_int[11]_i_149_n_0\ ); \cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_125_n_0\, CO(2) => \cr_int_reg[11]_i_125_n_1\, CO(1) => \cr_int_reg[11]_i_125_n_2\, CO(0) => \cr_int_reg[11]_i_125_n_3\, CYINIT => '1', DI(3) => \cr_int[11]_i_150_n_0\, DI(2) => \cr_int[11]_i_151_n_0\, DI(1) => \cr_int[11]_i_152_n_0\, DI(0) => \cb_int_reg[3]_i_94_n_7\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_153_n_0\, S(2) => \cr_int[11]_i_154_n_0\, S(1) => \cr_int[11]_i_155_n_0\, S(0) => \cr_int[11]_i_156_n_0\ ); \cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_31_n_0\, CO(3) => \cr_int_reg[11]_i_16_n_0\, CO(2) => \cr_int_reg[11]_i_16_n_1\, CO(1) => \cr_int_reg[11]_i_16_n_2\, CO(0) => \cr_int_reg[11]_i_16_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_16_n_4\, O(2) => \cr_int_reg[11]_i_16_n_5\, O(1) => \cr_int_reg[11]_i_16_n_6\, O(0) => \cr_int_reg[11]_i_16_n_7\, S(3) => \cr_int[11]_i_32_n_0\, S(2) => \cr_int[11]_i_33_n_0\, S(1) => \cr_int[11]_i_34_n_0\, S(0) => \cr_int[11]_i_35_n_0\ ); \cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_36_n_0\, CO(3) => \cr_int_reg[11]_i_17_n_0\, CO(2) => \cr_int_reg[11]_i_17_n_1\, CO(1) => \cr_int_reg[11]_i_17_n_2\, CO(0) => \cr_int_reg[11]_i_17_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \^cr_int_reg[27]_2\(0), DI(1) => \^cr_int_reg[27]_2\(0), DI(0) => \^cr_int_reg[27]_2\(0), O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_37_n_0\, S(2) => \cr_int[11]_i_38_n_0\, S(1) => \cr_int[11]_i_39_n_0\, S(0) => \cr_int[11]_i_40_n_0\ ); \cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_41_n_0\, CO(3) => \cr_int_reg[15]_1\(0), CO(2) => \cr_int_reg[11]_i_18_n_1\, CO(1) => \cr_int_reg[11]_i_18_n_2\, CO(0) => \cr_int_reg[11]_i_18_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_18_n_4\, O(2) => \cr_int_reg[11]_i_18_n_5\, O(1) => \cr_int_reg[11]_i_18_n_6\, O(0) => \cr_int_reg[11]_i_18_n_7\, S(3) => \cr_int[11]_i_42_n_0\, S(2) => \cr_int[11]_i_43_n_0\, S(1) => \cr_int[11]_i_44_n_0\, S(0) => \cr_int[11]_i_45_n_0\ ); \cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_46_n_0\, CO(3) => \cr_int_reg[11]_i_19_n_0\, CO(2) => \cr_int_reg[11]_i_19_n_1\, CO(1) => \cr_int_reg[11]_i_19_n_2\, CO(0) => \cr_int_reg[11]_i_19_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(16 downto 13), S(3) => \cr_int[11]_i_47_n_0\, S(2) => \cr_int[11]_i_48_n_0\, S(1) => \cr_int[11]_i_49_n_0\, S(0) => \cr_int[11]_i_50_n_0\ ); \cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_51_n_0\, CO(3) => cr_int_reg7, CO(2) => \cr_int_reg[11]_i_20_n_1\, CO(1) => \cr_int_reg[11]_i_20_n_2\, CO(0) => \cr_int_reg[11]_i_20_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \cr_int_reg[31]_i_11_n_4\, DI(1) => \cr_int_reg[31]_i_11_n_4\, DI(0) => \cr_int_reg[31]_i_11_n_4\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_52_n_0\, S(2) => \cr_int[11]_i_53_n_0\, S(1) => \cr_int[11]_i_54_n_0\, S(0) => \cr_int[11]_i_55_n_0\ ); \cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_56_n_0\, CO(3) => \cr_int_reg[11]_i_21_n_0\, CO(2) => \cr_int_reg[11]_i_21_n_1\, CO(1) => \cr_int_reg[11]_i_21_n_2\, CO(0) => \cr_int_reg[11]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(8 downto 5), S(3) => \cr_int[11]_i_57_n_0\, S(2) => \cr_int[11]_i_58_n_0\, S(1) => \cr_int[11]_i_59_n_0\, S(0) => \cr_int[11]_i_60_n_0\ ); \cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[7]_i_23_n_0\, CO(3) => \cr_int_reg[11]_i_29_n_0\, CO(2) => \cr_int_reg[11]_i_29_n_1\, CO(1) => \cr_int_reg[11]_i_29_n_2\, CO(0) => \cr_int_reg[11]_i_29_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0), S(3) => \cr_int[11]_i_65_n_0\, S(2) => \cr_int[11]_i_66_n_0\, S(1) => \cr_int[11]_i_67_n_0\, S(0) => \cr_int[11]_i_68_n_0\ ); \cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_69_n_0\, CO(3) => \^cr_int_reg[3]_1\(0), CO(2) => \cr_int_reg[11]_i_30_n_1\, CO(1) => \cr_int_reg[11]_i_30_n_2\, CO(0) => \cr_int_reg[11]_i_30_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \^cr_int_reg[31]_2\(1), DI(1) => \^cr_int_reg[31]_2\(1), DI(0) => \^cr_int_reg[31]_2\(1), O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_70_n_0\, S(2) => \cr_int[11]_i_71_n_0\, S(1) => \cr_int[11]_i_72_n_0\, S(0) => \cr_int[11]_i_73_n_0\ ); \cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_31_n_0\, CO(2) => \cr_int_reg[11]_i_31_n_1\, CO(1) => \cr_int_reg[11]_i_31_n_2\, CO(0) => \cr_int_reg[11]_i_31_n_3\, CYINIT => \cr_int[11]_i_74_n_0\, DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_31_n_4\, O(2) => \cr_int_reg[11]_i_31_n_5\, O(1) => \cr_int_reg[11]_i_31_n_6\, O(0) => \cr_int_reg[11]_i_31_n_7\, S(3) => \cr_int[11]_i_75_n_0\, S(2) => \cr_int[11]_i_76_n_0\, S(1) => \cr_int[11]_i_77_n_0\, S(0) => \cr_int[11]_i_78_n_0\ ); \cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_79_n_0\, CO(3) => \cr_int_reg[11]_i_36_n_0\, CO(2) => \cr_int_reg[11]_i_36_n_1\, CO(1) => \cr_int_reg[11]_i_36_n_2\, CO(0) => \cr_int_reg[11]_i_36_n_3\, CYINIT => '0', DI(3) => \^cr_int_reg[27]_2\(0), DI(2) => \^cr_int_reg[27]_2\(0), DI(1) => \^cr_int_reg[27]_2\(0), DI(0) => \^cr_int_reg[27]_2\(0), O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_80_n_0\, S(2) => \cr_int[11]_i_81_n_0\, S(1) => \cr_int[11]_i_82_n_0\, S(0) => \cr_int[11]_i_83_n_0\ ); \cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_32_n_0\, CO(3) => \cr_int_reg[11]_i_41_n_0\, CO(2) => \cr_int_reg[11]_i_41_n_1\, CO(1) => \cr_int_reg[11]_i_41_n_2\, CO(0) => \cr_int_reg[11]_i_41_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_41_n_4\, O(2) => \cr_int_reg[11]_i_41_n_5\, O(1) => \cr_int_reg[11]_i_41_n_6\, O(0) => \cr_int_reg[11]_i_41_n_7\, S(3) => \cr_int[11]_i_84_n_0\, S(2) => \cr_int[11]_i_85_n_0\, S(1) => \cr_int[11]_i_86_n_0\, S(0) => \cr_int[11]_i_87_n_0\ ); \cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_15_n_0\, CO(3) => \cr_int_reg[11]_i_46_n_0\, CO(2) => \cr_int_reg[11]_i_46_n_1\, CO(1) => \cr_int_reg[11]_i_46_n_2\, CO(0) => \cr_int_reg[11]_i_46_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(12 downto 9), S(3) => \cr_int[11]_i_88_n_0\, S(2) => \cr_int[11]_i_89_n_0\, S(1) => \cr_int[11]_i_90_n_0\, S(0) => \cr_int[11]_i_91_n_0\ ); \cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_92_n_0\, CO(3) => \cr_int_reg[11]_i_51_n_0\, CO(2) => \cr_int_reg[11]_i_51_n_1\, CO(1) => \cr_int_reg[11]_i_51_n_2\, CO(0) => \cr_int_reg[11]_i_51_n_3\, CYINIT => '0', DI(3) => \cr_int_reg[31]_i_11_n_4\, DI(2) => \cr_int_reg[31]_i_11_n_4\, DI(1) => \cr_int_reg[31]_i_11_n_4\, DI(0) => \cr_int[11]_i_93_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_94_n_0\, S(2) => \cr_int[11]_i_95_n_0\, S(1) => \cr_int[11]_i_96_n_0\, S(0) => \cr_int[11]_i_97_n_0\ ); \cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_56_n_0\, CO(2) => \cr_int_reg[11]_i_56_n_1\, CO(1) => \cr_int_reg[11]_i_56_n_2\, CO(0) => \cr_int_reg[11]_i_56_n_3\, CYINIT => \cr_int[11]_i_98_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(4 downto 1), S(3) => \cr_int[11]_i_99_n_0\, S(2) => \cr_int[11]_i_100_n_0\, S(1) => \cr_int[11]_i_101_n_0\, S(0) => \cr_int[11]_i_102_n_0\ ); \cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_103_n_0\, CO(3) => \cr_int_reg[11]_i_69_n_0\, CO(2) => \cr_int_reg[11]_i_69_n_1\, CO(1) => \cr_int_reg[11]_i_69_n_2\, CO(0) => \cr_int_reg[11]_i_69_n_3\, CYINIT => '0', DI(3) => \^cr_int_reg[31]_2\(1), DI(2) => \^cr_int_reg[31]_2\(1), DI(1) => \^cr_int_reg[31]_2\(1), DI(0) => \^cr_int_reg[31]_2\(1), O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_104_n_0\, S(2) => \cr_int[11]_i_105_n_0\, S(1) => \cr_int[11]_i_106_n_0\, S(0) => \cr_int[11]_i_107_n_0\ ); \cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_108_n_0\, CO(3) => \cr_int_reg[11]_i_79_n_0\, CO(2) => \cr_int_reg[11]_i_79_n_1\, CO(1) => \cr_int_reg[11]_i_79_n_2\, CO(0) => \cr_int_reg[11]_i_79_n_3\, CYINIT => '0', DI(3) => \^cr_int_reg[27]_2\(0), DI(2) => \cr_int[11]_i_109_n_0\, DI(1) => \cr_int[11]_i_110_n_0\, DI(0) => \cr_int[11]_i_111_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_112_n_0\, S(2) => \cr_int[11]_i_113_n_0\, S(1) => \cr_int[11]_i_114_n_0\, S(0) => \cr_int[11]_i_115_n_0\ ); \cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_116_n_0\, CO(3) => \cr_int_reg[11]_i_92_n_0\, CO(2) => \cr_int_reg[11]_i_92_n_1\, CO(1) => \cr_int_reg[11]_i_92_n_2\, CO(0) => \cr_int_reg[11]_i_92_n_3\, CYINIT => '0', DI(3) => \cr_int[11]_i_117_n_0\, DI(2) => \cr_int[11]_i_118_n_0\, DI(1) => \cr_int[11]_i_119_n_0\, DI(0) => \cr_int[11]_i_120_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_121_n_0\, S(2) => \cr_int[11]_i_122_n_0\, S(1) => \cr_int[11]_i_123_n_0\, S(0) => \cr_int[11]_i_124_n_0\ ); \cr_int_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[15]_i_1_n_7\, Q => \cr_int_reg__0\(12), R => '0' ); \cr_int_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[15]_i_1_n_6\, Q => \cr_int_reg__0\(13), R => '0' ); \cr_int_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[15]_i_1_n_5\, Q => \cr_int_reg__0\(14), R => '0' ); \cr_int_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[15]_i_1_n_4\, Q => \cr_int_reg__0\(15), R => '0' ); \cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_1_n_0\, CO(3) => \cr_int_reg[15]_i_1_n_0\, CO(2) => \cr_int_reg[15]_i_1_n_1\, CO(1) => \cr_int_reg[15]_i_1_n_2\, CO(0) => \cr_int_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[15]_i_2_n_0\, DI(2) => \cr_int[15]_i_3_n_0\, DI(1) => \cr_int[15]_i_4_n_0\, DI(0) => \cr_int[15]_i_5_n_0\, O(3) => \cr_int_reg[15]_i_1_n_4\, O(2) => \cr_int_reg[15]_i_1_n_5\, O(1) => \cr_int_reg[15]_i_1_n_6\, O(0) => \cr_int_reg[15]_i_1_n_7\, S(3) => \cr_int[15]_i_6_n_0\, S(2) => \cr_int[15]_i_7_n_0\, S(1) => \cr_int[15]_i_8_n_0\, S(0) => \cr_int[15]_i_9_n_0\ ); \cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_19_n_0\, CO(3) => \cr_int_reg[15]_i_20_n_0\, CO(2) => \cr_int_reg[15]_i_20_n_1\, CO(1) => \cr_int_reg[15]_i_20_n_2\, CO(0) => \cr_int_reg[15]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(20 downto 17), S(3) => \cr_int[15]_i_29_n_0\, S(2) => \cr_int[15]_i_30_n_0\, S(1) => \cr_int[15]_i_31_n_0\, S(0) => \cr_int[15]_i_32_n_0\ ); \cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_21_n_0\, CO(3) => \cr_int_reg[15]_i_21_n_0\, CO(2) => \cr_int_reg[15]_i_21_n_1\, CO(1) => \cr_int_reg[15]_i_21_n_2\, CO(0) => \cr_int_reg[15]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(12 downto 9), S(3) => \cr_int[15]_i_33_n_0\, S(2) => \cr_int[15]_i_34_n_0\, S(1) => \cr_int[15]_i_35_n_0\, S(0) => \cr_int[15]_i_36_n_0\ ); \cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_29_n_0\, CO(3) => \cr_int_reg[15]_i_28_n_0\, CO(2) => \cr_int_reg[15]_i_28_n_1\, CO(1) => \cr_int_reg[15]_i_28_n_2\, CO(0) => \cr_int_reg[15]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0), S(3) => \cr_int[15]_i_40_n_0\, S(2) => \cr_int[15]_i_41_n_0\, S(1) => \cr_int[15]_i_42_n_0\, S(0) => \cr_int[15]_i_43_n_0\ ); \cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_16_n_0\, CO(3) => \cr_int_reg[15]_i_38_n_0\, CO(2) => \cr_int_reg[15]_i_38_n_1\, CO(1) => \cr_int_reg[15]_i_38_n_2\, CO(0) => \cr_int_reg[15]_i_38_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[15]_i_38_n_4\, O(2) => \cr_int_reg[15]_i_38_n_5\, O(1) => \cr_int_reg[15]_i_38_n_6\, O(0) => \cr_int_reg[15]_i_38_n_7\, S(3) => \cr_int[15]_i_48_n_0\, S(2) => \cr_int[15]_i_49_n_0\, S(1) => \cr_int[15]_i_50_n_0\, S(0) => \cr_int[15]_i_51_n_0\ ); \cr_int_reg[16]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[19]_i_1_n_7\, Q => \cr_int_reg__0\(16), R => '0' ); \cr_int_reg[17]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[19]_i_1_n_6\, Q => \cr_int_reg__0\(17), R => '0' ); \cr_int_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[19]_i_1_n_5\, Q => \cr_int_reg__0\(18), R => '0' ); \cr_int_reg[19]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[19]_i_1_n_4\, Q => \cr_int_reg__0\(19), R => '0' ); \cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_1_n_0\, CO(3) => \cr_int_reg[19]_i_1_n_0\, CO(2) => \cr_int_reg[19]_i_1_n_1\, CO(1) => \cr_int_reg[19]_i_1_n_2\, CO(0) => \cr_int_reg[19]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[19]_i_2_n_0\, DI(2) => \cr_int[19]_i_3_n_0\, DI(1) => \cr_int[19]_i_4_n_0\, DI(0) => \cr_int[19]_i_5_n_0\, O(3) => \cr_int_reg[19]_i_1_n_4\, O(2) => \cr_int_reg[19]_i_1_n_5\, O(1) => \cr_int_reg[19]_i_1_n_6\, O(0) => \cr_int_reg[19]_i_1_n_7\, S(3) => \cr_int[19]_i_6_n_0\, S(2) => \cr_int[19]_i_7_n_0\, S(1) => \cr_int[19]_i_8_n_0\, S(0) => \cr_int[19]_i_9_n_0\ ); \cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_20_n_0\, CO(3) => \cr_int_reg[19]_i_20_n_0\, CO(2) => \cr_int_reg[19]_i_20_n_1\, CO(1) => \cr_int_reg[19]_i_20_n_2\, CO(0) => \cr_int_reg[19]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(24 downto 21), S(3) => \cr_int[19]_i_29_n_0\, S(2) => \cr_int[19]_i_30_n_0\, S(1) => \cr_int[19]_i_31_n_0\, S(0) => \cr_int[19]_i_32_n_0\ ); \cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_21_n_0\, CO(3) => \cr_int_reg[19]_i_21_n_0\, CO(2) => \cr_int_reg[19]_i_21_n_1\, CO(1) => \cr_int_reg[19]_i_21_n_2\, CO(0) => \cr_int_reg[19]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(16 downto 13), S(3) => \cr_int[19]_i_33_n_0\, S(2) => \cr_int[19]_i_34_n_0\, S(1) => \cr_int[19]_i_35_n_0\, S(0) => \cr_int[19]_i_36_n_0\ ); \cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_28_n_0\, CO(3) => \cr_int_reg[19]_i_28_n_0\, CO(2) => \cr_int_reg[19]_i_28_n_1\, CO(1) => \cr_int_reg[19]_i_28_n_2\, CO(0) => \cr_int_reg[19]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0), S(3) => \cr_int[19]_i_38_n_0\, S(2) => \cr_int[19]_i_39_n_0\, S(1) => \cr_int[19]_i_40_n_0\, S(0) => \cr_int[19]_i_41_n_0\ ); \cr_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[3]_i_1_n_6\, Q => \cr_int_reg_n_0_[1]\, R => '0' ); \cr_int_reg[20]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[23]_i_1_n_7\, Q => \cr_int_reg__0\(20), R => '0' ); \cr_int_reg[21]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[23]_i_1_n_6\, Q => \cr_int_reg__0\(21), R => '0' ); \cr_int_reg[22]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[23]_i_1_n_5\, Q => \cr_int_reg__0\(22), R => '0' ); \cr_int_reg[23]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[23]_i_1_n_4\, Q => \cr_int_reg__0\(23), R => '0' ); \cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_1_n_0\, CO(3) => \cr_int_reg[23]_i_1_n_0\, CO(2) => \cr_int_reg[23]_i_1_n_1\, CO(1) => \cr_int_reg[23]_i_1_n_2\, CO(0) => \cr_int_reg[23]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[23]_i_2_n_0\, DI(2) => \cr_int[23]_i_3_n_0\, DI(1) => \cr_int[23]_i_4_n_0\, DI(0) => \cr_int[23]_i_5_n_0\, O(3) => \cr_int_reg[23]_i_1_n_4\, O(2) => \cr_int_reg[23]_i_1_n_5\, O(1) => \cr_int_reg[23]_i_1_n_6\, O(0) => \cr_int_reg[23]_i_1_n_7\, S(3) => \cr_int[23]_i_6_n_0\, S(2) => \cr_int[23]_i_7_n_0\, S(1) => \cr_int[23]_i_8_n_0\, S(0) => \cr_int[23]_i_9_n_0\ ); \cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_20_n_0\, CO(3) => \cr_int_reg[23]_i_20_n_0\, CO(2) => \cr_int_reg[23]_i_20_n_1\, CO(1) => \cr_int_reg[23]_i_20_n_2\, CO(0) => \cr_int_reg[23]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(28 downto 25), S(3) => \cr_int[23]_i_27_n_0\, S(2) => \cr_int[23]_i_28_n_0\, S(1) => \cr_int[23]_i_29_n_0\, S(0) => \cr_int[23]_i_30_n_0\ ); \cr_int_reg[24]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[27]_i_1_n_7\, Q => \cr_int_reg__0\(24), R => '0' ); \cr_int_reg[25]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[27]_i_1_n_6\, Q => \cr_int_reg__0\(25), R => '0' ); \cr_int_reg[26]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[27]_i_1_n_5\, Q => \cr_int_reg__0\(26), R => '0' ); \cr_int_reg[27]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[27]_i_1_n_4\, Q => \cr_int_reg__0\(27), R => '0' ); \cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[23]_i_1_n_0\, CO(3) => \cr_int_reg[27]_i_1_n_0\, CO(2) => \cr_int_reg[27]_i_1_n_1\, CO(1) => \cr_int_reg[27]_i_1_n_2\, CO(0) => \cr_int_reg[27]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_2_n_0\, DI(2) => \cr_int[31]_i_2_n_0\, DI(1) => \cr_int[31]_i_2_n_0\, DI(0) => \cr_int[27]_i_2_n_0\, O(3) => \cr_int_reg[27]_i_1_n_4\, O(2) => \cr_int_reg[27]_i_1_n_5\, O(1) => \cr_int_reg[27]_i_1_n_6\, O(0) => \cr_int_reg[27]_i_1_n_7\, S(3) => \cr_int[27]_i_3_n_0\, S(2) => \cr_int[27]_i_4_n_0\, S(1) => \cr_int[27]_i_5_n_0\, S(0) => \cr_int[27]_i_6_n_0\ ); \cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[23]_i_20_n_0\, CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1), CO(0) => \cr_int_reg[27]_i_9_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => cr_int_reg6(30 downto 29), S(3 downto 2) => B"00", S(1) => \cr_int[27]_i_12_n_0\, S(0) => \cr_int[27]_i_13_n_0\ ); \cr_int_reg[28]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[31]_i_1_n_7\, Q => \cr_int_reg__0\(28), R => '0' ); \cr_int_reg[29]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[31]_i_1_n_6\, Q => \cr_int_reg__0\(29), R => '0' ); \cr_int_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[3]_i_1_n_5\, Q => \cr_int_reg_n_0_[2]\, R => '0' ); \cr_int_reg[30]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[31]_i_1_n_5\, Q => \cr_int_reg__0\(30), R => '0' ); \cr_int_reg[31]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[31]_i_1_n_4\, Q => \cr_int_reg__0\(31), R => '0' ); \cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[27]_i_1_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_1_n_1\, CO(1) => \cr_int_reg[31]_i_1_n_2\, CO(0) => \cr_int_reg[31]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \cr_int[31]_i_2_n_0\, DI(1) => \cr_int[31]_i_2_n_0\, DI(0) => \cr_int[31]_i_2_n_0\, O(3) => \cr_int_reg[31]_i_1_n_4\, O(2) => \cr_int_reg[31]_i_1_n_5\, O(1) => \cr_int_reg[31]_i_1_n_6\, O(0) => \cr_int_reg[31]_i_1_n_7\, S(3) => \cr_int[31]_i_3_n_0\, S(2) => \cr_int[31]_i_4_n_0\, S(1) => \cr_int[31]_i_5_n_0\, S(0) => \cr_int[31]_i_6_n_0\ ); \cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_64_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_101_n_1\, CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[31]_i_101_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1 downto 0) => rgb888(15 downto 14), O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[31]_i_101_n_6\, O(0) => \cr_int_reg[31]_i_101_n_7\, S(3 downto 2) => B"01", S(1) => \cr_int[31]_i_121_n_0\, S(0) => \cr_int[31]_i_122_n_0\ ); \cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_70_n_0\, CO(3) => \cr_int_reg[31]_i_102_n_0\, CO(2) => \cr_int_reg[31]_i_102_n_1\, CO(1) => \cr_int_reg[31]_i_102_n_2\, CO(0) => \cr_int_reg[31]_i_102_n_3\, CYINIT => '0', DI(3) => rgb888(14), DI(2 downto 0) => rgb888(15 downto 13), O(3) => \cr_int_reg[31]_i_102_n_4\, O(2) => \cr_int_reg[31]_i_102_n_5\, O(1) => \cr_int_reg[31]_i_102_n_6\, O(0) => \cr_int_reg[31]_i_102_n_7\, S(3) => \cr_int[31]_i_123_n_0\, S(2) => \cr_int[31]_i_124_n_0\, S(1) => \cr_int[31]_i_125_n_0\, S(0) => \cr_int[31]_i_126_n_0\ ); \cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_30_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_11_n_1\, CO(1) => \cr_int_reg[31]_i_11_n_2\, CO(0) => \cr_int_reg[31]_i_11_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \cr_int[31]_i_31_n_0\, O(3) => \cr_int_reg[31]_i_11_n_4\, O(2) => \cr_int_reg[31]_i_11_n_5\, O(1) => \cr_int_reg[31]_i_11_n_6\, O(0) => \cr_int_reg[31]_i_11_n_7\, S(3) => \cr_int[31]_i_32_n_0\, S(2) => \cr_int[31]_i_33_n_0\, S(1) => \cr_int[31]_i_34_n_0\, S(0) => \cr_int[31]_i_35_n_0\ ); \cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_36_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_12_n_1\, CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[31]_i_12_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => cr_int_reg4(22 downto 21), S(3 downto 2) => B"01", S(1) => \cr_int[31]_i_37_n_0\, S(0) => \cr_int[31]_i_38_n_0\ ); \cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_39_n_0\, CO(3) => \cr_int_reg[31]_i_14_n_0\, CO(2) => \cr_int_reg[31]_i_14_n_1\, CO(1) => \cr_int_reg[31]_i_14_n_2\, CO(0) => \cr_int_reg[31]_i_14_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_40_n_0\, DI(2) => \cr_int[31]_i_41_n_0\, DI(1) => \cr_int[31]_i_42_n_0\, DI(0) => \cr_int[31]_i_43_n_0\, O(3) => \cr_int_reg[31]_i_14_n_4\, O(2) => \cr_int_reg[31]_i_14_n_5\, O(1) => \cr_int_reg[31]_i_14_n_6\, O(0) => \cr_int_reg[31]_i_14_n_7\, S(3) => \cr_int[31]_i_44_n_0\, S(2) => \cr_int[31]_i_45_n_0\, S(1) => \cr_int[31]_i_46_n_0\, S(0) => \cr_int[31]_i_47_n_0\ ); \cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_49_n_0\, CO(3) => \cr_int_reg[31]_i_21_n_0\, CO(2) => \cr_int_reg[31]_i_21_n_1\, CO(1) => \cr_int_reg[31]_i_21_n_2\, CO(0) => \cr_int_reg[31]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[31]_i_21_n_4\, O(2) => \cr_int_reg[31]_i_21_n_5\, O(1) => \cr_int_reg[31]_i_21_n_6\, O(0) => \cr_int_reg[31]_i_21_n_7\, S(3) => \cr_int[31]_i_50_n_0\, S(2) => \cr_int[31]_i_51_n_0\, S(1) => \cr_int[31]_i_52_n_0\, S(0) => \cr_int[31]_i_53_n_0\ ); \cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_19_n_0\, CO(3) => \cr_int_reg[31]_i_24_n_0\, CO(2) => \cr_int_reg[31]_i_24_n_1\, CO(1) => \cr_int_reg[31]_i_24_n_2\, CO(0) => \cr_int_reg[31]_i_24_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_55_n_0\, DI(2) => \cr_int[31]_i_56_n_0\, DI(1) => \cr_int[31]_i_57_n_0\, DI(0) => \cr_int[31]_i_58_n_0\, O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0), S(3) => \cr_int[31]_i_59_n_0\, S(2) => \cr_int[31]_i_60_n_0\, S(1) => \cr_int[31]_i_61_n_0\, S(0) => \cr_int[31]_i_62_n_0\ ); \cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_16_n_0\, CO(3) => \cr_int_reg[31]_i_30_n_0\, CO(2) => \cr_int_reg[31]_i_30_n_1\, CO(1) => \cr_int_reg[31]_i_30_n_2\, CO(0) => \cr_int_reg[31]_i_30_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_71_n_0\, DI(2) => \cr_int[31]_i_72_n_0\, DI(1) => \cr_int[31]_i_73_n_0\, DI(0) => \cr_int[31]_i_74_n_0\, O(3) => \cr_int_reg[31]_i_30_n_4\, O(2) => \cr_int_reg[31]_i_30_n_5\, O(1) => \cr_int_reg[31]_i_30_n_6\, O(0) => \cr_int_reg[31]_i_30_n_7\, S(3) => \cr_int[31]_i_75_n_0\, S(2) => \cr_int[31]_i_76_n_0\, S(1) => \cr_int[31]_i_77_n_0\, S(0) => \cr_int[31]_i_78_n_0\ ); \cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_21_n_0\, CO(3) => \cr_int_reg[31]_i_36_n_0\, CO(2) => \cr_int_reg[31]_i_36_n_1\, CO(1) => \cr_int_reg[31]_i_36_n_2\, CO(0) => \cr_int_reg[31]_i_36_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(20 downto 17), S(3) => \cr_int[31]_i_81_n_0\, S(2) => \cr_int[31]_i_82_n_0\, S(1) => \cr_int[31]_i_83_n_0\, S(0) => \cr_int[31]_i_84_n_0\ ); \cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[31]_i_39_n_0\, CO(2) => \cr_int_reg[31]_i_39_n_1\, CO(1) => \cr_int_reg[31]_i_39_n_2\, CO(0) => \cr_int_reg[31]_i_39_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_85_n_0\, DI(2) => rgb888(1), DI(1) => \cr_int_reg[31]_i_86_n_4\, DI(0) => '0', O(3) => \cr_int_reg[31]_i_39_n_4\, O(2) => \cr_int_reg[31]_i_39_n_5\, O(1) => \cr_int_reg[31]_i_39_n_6\, O(0) => \cr_int_reg[31]_i_39_n_7\, S(3) => \cr_int[31]_i_87_n_0\, S(2) => \cr_int[31]_i_88_n_0\, S(1) => \cr_int[31]_i_89_n_0\, S(0) => \cr_int[31]_i_90_n_0\ ); \cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_91_n_0\, CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2), CO(1) => \cr_int_reg[31]_i_48_n_2\, CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(7), O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1), O(0) => \cr_int_reg[31]_i_48_n_7\, S(3 downto 1) => B"001", S(0) => \cr_int[31]_i_93_n_0\ ); \cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_38_n_0\, CO(3) => \cr_int_reg[31]_i_49_n_0\, CO(2) => \cr_int_reg[31]_i_49_n_1\, CO(1) => \cr_int_reg[31]_i_49_n_2\, CO(0) => \cr_int_reg[31]_i_49_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[31]_i_49_n_4\, O(2) => \cr_int_reg[31]_i_49_n_5\, O(1) => \cr_int_reg[31]_i_49_n_6\, O(0) => \cr_int_reg[31]_i_49_n_7\, S(3) => \cr_int[31]_i_94_n_0\, S(2) => \cr_int[31]_i_95_n_0\, S(1) => \cr_int[31]_i_96_n_0\, S(0) => \cr_int[31]_i_97_n_0\ ); \cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_102_n_0\, CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2), CO(1) => \cr_int_reg[31]_i_63_n_2\, CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(15), O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1), O(0) => \cr_int_reg[31]_i_63_n_7\, S(3 downto 1) => B"001", S(0) => \cr_int[31]_i_103_n_0\ ); \cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_70_n_0\, CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1), O(0) => \^cr_int_reg[23]_1\(0), S(3 downto 1) => B"000", S(0) => \cr_int[31]_i_108_n_0\ ); \cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_14_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_7_n_1\, CO(1) => \cr_int_reg[31]_i_7_n_2\, CO(0) => \cr_int_reg[31]_i_7_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \cr_int[31]_i_15_n_0\, DI(0) => \cr_int[31]_i_16_n_0\, O(3) => \^cr_int_reg[27]_2\(0), O(2) => \cr_int_reg[31]_i_7_n_5\, O(1) => \cr_int_reg[31]_i_7_n_6\, O(0) => \cr_int_reg[31]_i_7_n_7\, S(3) => \cr_int[31]_i_17_n_0\, S(2) => \cr_int[31]_i_18_n_0\, S(1) => \cr_int[31]_i_19_n_0\, S(0) => \cr_int[31]_i_20_n_0\ ); \cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_28_n_0\, CO(3) => \cr_int_reg[31]_i_70_n_0\, CO(2) => \cr_int_reg[31]_i_70_n_1\, CO(1) => \cr_int_reg[31]_i_70_n_2\, CO(0) => \cr_int_reg[31]_i_70_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0), S(3) => \cr_int[31]_i_109_n_0\, S(2) => \cr_int[31]_i_110_n_0\, S(1) => \cr_int[31]_i_111_n_0\, S(0) => \cr_int[31]_i_112_n_0\ ); \cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_21_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_8_n_1\, CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[31]_i_8_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[31]_i_8_n_6\, O(0) => \cr_int_reg[31]_i_8_n_7\, S(3 downto 2) => B"01", S(1) => \cr_int[31]_i_22_n_0\, S(0) => \cr_int[31]_i_23_n_0\ ); \cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[31]_i_86_n_0\, CO(2) => \cr_int_reg[31]_i_86_n_1\, CO(1) => \cr_int_reg[31]_i_86_n_2\, CO(0) => \cr_int_reg[31]_i_86_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(4 downto 2), DI(0) => '0', O(3) => \cr_int_reg[31]_i_86_n_4\, O(2) => \cr_int_reg[31]_i_86_n_5\, O(1) => \cr_int_reg[31]_i_86_n_6\, O(0) => \cr_int_reg[31]_i_86_n_7\, S(3) => \cr_int[31]_i_113_n_0\, S(2) => \cr_int[31]_i_114_n_0\, S(1) => \cr_int[31]_i_115_n_0\, S(0) => \cr_int[31]_i_116_n_0\ ); \cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_24_n_0\, CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1), CO(0) => \cr_int_reg[31]_i_9_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \^di\(0), O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0), S(3 downto 2) => B"00", S(1) => \cr_int[31]_i_25_n_0\, S(0) => \cr_int[31]_i_26_n_0\ ); \cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_86_n_0\, CO(3) => \cr_int_reg[31]_i_91_n_0\, CO(2) => \cr_int_reg[31]_i_91_n_1\, CO(1) => \cr_int_reg[31]_i_91_n_2\, CO(0) => \cr_int_reg[31]_i_91_n_3\, CYINIT => '0', DI(3) => rgb888(6), DI(2 downto 0) => rgb888(7 downto 5), O(3) => \cr_int_reg[31]_i_91_n_4\, O(2) => \cr_int_reg[31]_i_91_n_5\, O(1) => \cr_int_reg[31]_i_91_n_6\, O(0) => \cr_int_reg[31]_i_91_n_7\, S(3) => \cr_int[31]_i_117_n_0\, S(2) => \cr_int[31]_i_118_n_0\, S(1) => \cr_int[31]_i_119_n_0\, S(0) => \cr_int[31]_i_120_n_0\ ); \cr_int_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[3]_i_1_n_4\, Q => \cr_int_reg_n_0_[3]\, R => '0' ); \cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_1_n_0\, CO(2) => \cr_int_reg[3]_i_1_n_1\, CO(1) => \cr_int_reg[3]_i_1_n_2\, CO(0) => \cr_int_reg[3]_i_1_n_3\, CYINIT => '1', DI(3) => \cr_int[3]_i_2_n_0\, DI(2) => \cr_int[3]_i_3_n_0\, DI(1) => \cr_int[3]_i_4_n_0\, DI(0) => '1', O(3) => \cr_int_reg[3]_i_1_n_4\, O(2) => \cr_int_reg[3]_i_1_n_5\, O(1) => \cr_int_reg[3]_i_1_n_6\, O(0) => \cr_int_reg[3]_i_1_n_7\, S(3) => \cr_int[3]_i_5_n_0\, S(2) => \cr_int[3]_i_6_n_0\, S(1) => \cr_int[3]_i_7_n_0\, S(0) => \cr_int[3]_i_8_n_0\ ); \cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_21_n_0\, CO(3) => \cr_int_reg[3]_i_15_n_0\, CO(2) => \cr_int_reg[3]_i_15_n_1\, CO(1) => \cr_int_reg[3]_i_15_n_2\, CO(0) => \cr_int_reg[3]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => cr_int_reg6(8), O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0), S(3) => \cr_int[3]_i_22_n_0\, S(2) => \cr_int[3]_i_23_n_0\, S(1) => \cr_int[3]_i_24_n_0\, S(0) => \cr_int[3]_i_25_n_0\ ); \cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_16_n_0\, CO(2) => \cr_int_reg[3]_i_16_n_1\, CO(1) => \cr_int_reg[3]_i_16_n_2\, CO(0) => \cr_int_reg[3]_i_16_n_3\, CYINIT => '0', DI(3) => \cr_int_reg[3]_i_26_n_6\, DI(2) => \cr_int_reg[3]_i_26_n_7\, DI(1) => \cr_int_reg[3]_i_27_n_4\, DI(0) => '0', O(3) => \cr_int_reg[3]_i_16_n_4\, O(2) => \cr_int_reg[3]_i_16_n_5\, O(1) => \cr_int_reg[3]_i_16_n_6\, O(0) => \cr_int_reg[3]_i_16_n_7\, S(3) => \cr_int[3]_i_28_n_0\, S(2) => \cr_int[3]_i_29_n_0\, S(1) => \cr_int[3]_i_30_n_0\, S(0) => \cr_int[3]_i_31_n_0\ ); \cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_33_n_0\, CO(3) => \cr_int_reg[3]_i_19_n_0\, CO(2) => \cr_int_reg[3]_i_19_n_1\, CO(1) => \cr_int_reg[3]_i_19_n_2\, CO(0) => \cr_int_reg[3]_i_19_n_3\, CYINIT => '0', DI(3) => \cr_int[3]_i_34_n_0\, DI(2) => \cr_int[3]_i_35_n_0\, DI(1) => \cr_int[3]_i_36_n_0\, DI(0) => \cr_int[3]_i_37_n_0\, O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0), O(0) => \cr_int_reg[3]_i_19_n_7\, S(3) => \cr_int[3]_i_38_n_0\, S(2) => \cr_int[3]_i_39_n_0\, S(1) => \cr_int[3]_i_40_n_0\, S(0) => \cr_int[3]_i_41_n_0\ ); \cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_42_n_0\, CO(3) => \cr_int_reg[3]_i_20_n_0\, CO(2) => \cr_int_reg[3]_i_20_n_1\, CO(1) => \cr_int_reg[3]_i_20_n_2\, CO(0) => \cr_int_reg[3]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0), O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0), S(3) => \cr_int[3]_i_43_n_0\, S(2) => \cr_int[3]_i_44_n_0\, S(1) => \cr_int[3]_i_45_n_0\, S(0) => \cr_int[3]_i_46_n_0\ ); \cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_21_n_0\, CO(2) => \cr_int_reg[3]_i_21_n_1\, CO(1) => \cr_int_reg[3]_i_21_n_2\, CO(0) => \cr_int_reg[3]_i_21_n_3\, CYINIT => \cr_int[3]_i_47_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[3]_i_48_n_0\, S(2) => \cr_int[3]_i_49_n_0\, S(1) => \cr_int[3]_i_50_n_0\, S(0) => \cr_int[3]_i_51_n_0\ ); \cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_27_n_0\, CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[3]_i_26_n_1\, CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[3]_i_26_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => rgb888(23), DI(0) => '0', O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[3]_i_26_n_6\, O(0) => \cr_int_reg[3]_i_26_n_7\, S(3 downto 2) => B"01", S(1) => \cr_int[3]_i_52_n_0\, S(0) => \cr_int[3]_i_53_n_0\ ); \cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_54_n_0\, CO(3) => \cr_int_reg[3]_i_27_n_0\, CO(2) => \cr_int_reg[3]_i_27_n_1\, CO(1) => \cr_int_reg[3]_i_27_n_2\, CO(0) => \cr_int_reg[3]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => rgb888(21 downto 18), O(3) => \cr_int_reg[3]_i_27_n_4\, O(2) => \cr_int_reg[3]_i_27_n_5\, O(1) => \cr_int_reg[3]_i_27_n_6\, O(0) => \cr_int_reg[3]_i_27_n_7\, S(3) => \cr_int[3]_i_55_n_0\, S(2) => \cr_int[3]_i_56_n_0\, S(1) => \cr_int[3]_i_57_n_0\, S(0) => \cr_int[3]_i_58_n_0\ ); \cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_59_n_0\, CO(3) => \cr_int_reg[3]_i_32_n_0\, CO(2) => \cr_int_reg[3]_i_32_n_1\, CO(1) => \cr_int_reg[3]_i_32_n_2\, CO(0) => \cr_int_reg[3]_i_32_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[3]_i_32_n_4\, O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0), S(3) => \cr_int[3]_i_60_n_0\, S(2) => \cr_int[3]_i_61_n_0\, S(1) => \cr_int[3]_i_62_n_0\, S(0) => \cr_int[3]_i_63_n_0\ ); \cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_33_n_0\, CO(2) => \cr_int_reg[3]_i_33_n_1\, CO(1) => \cr_int_reg[3]_i_33_n_2\, CO(0) => \cr_int_reg[3]_i_33_n_3\, CYINIT => '0', DI(3) => \cr_int_reg[3]_i_64_n_6\, DI(2) => \cr_int_reg[3]_i_64_n_7\, DI(1) => \cr_int_reg[3]_i_65_n_4\, DI(0) => \cr_int_reg[3]_i_65_n_5\, O(3) => \cr_int_reg[3]_i_33_n_4\, O(2) => \cr_int_reg[3]_i_33_n_5\, O(1) => \cr_int_reg[3]_i_33_n_6\, O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0), S(3) => \cr_int[3]_i_66_n_0\, S(2) => \cr_int[3]_i_67_n_0\, S(1) => \cr_int[3]_i_68_n_0\, S(0) => \cr_int[3]_i_69_n_0\ ); \cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_42_n_0\, CO(2) => \cr_int_reg[3]_i_42_n_1\, CO(1) => \cr_int_reg[3]_i_42_n_2\, CO(0) => \cr_int_reg[3]_i_42_n_3\, CYINIT => \cr_int[3]_i_71_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[3]_i_72_n_0\, S(2) => \cr_int[3]_i_73_n_0\, S(1) => \cr_int[3]_i_74_n_0\, S(0) => \cr_int[3]_i_75_n_0\ ); \cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_54_n_0\, CO(2) => \cr_int_reg[3]_i_54_n_1\, CO(1) => \cr_int_reg[3]_i_54_n_2\, CO(0) => \cr_int_reg[3]_i_54_n_3\, CYINIT => '0', DI(3 downto 2) => rgb888(17 downto 16), DI(1 downto 0) => B"01", O(3) => \cr_int_reg[3]_i_54_n_4\, O(2) => \cr_int_reg[3]_i_54_n_5\, O(1) => \cr_int_reg[3]_i_54_n_6\, O(0) => \cr_int_reg[3]_i_54_n_7\, S(3) => \cr_int[3]_i_76_n_0\, S(2) => \cr_int[3]_i_77_n_0\, S(1) => \cr_int[3]_i_78_n_0\, S(0) => \cr_int[3]_i_79_n_0\ ); \cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_59_n_0\, CO(2) => \cr_int_reg[3]_i_59_n_1\, CO(1) => \cr_int_reg[3]_i_59_n_2\, CO(0) => \cr_int_reg[3]_i_59_n_3\, CYINIT => \cr_int[3]_i_80_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[3]_i_81_n_0\, S(2) => \cr_int[3]_i_82_n_0\, S(1) => \cr_int[3]_i_83_n_0\, S(0) => \cr_int[3]_i_84_n_0\ ); \cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_65_n_0\, CO(3) => \cr_int_reg[3]_i_64_n_0\, CO(2) => \cr_int_reg[3]_i_64_n_1\, CO(1) => \cr_int_reg[3]_i_64_n_2\, CO(0) => \cr_int_reg[3]_i_64_n_3\, CYINIT => '0', DI(3) => rgb888(15), DI(2 downto 0) => rgb888(12 downto 10), O(3) => \cr_int_reg[3]_i_64_n_4\, O(2) => \cr_int_reg[3]_i_64_n_5\, O(1) => \cr_int_reg[3]_i_64_n_6\, O(0) => \cr_int_reg[3]_i_64_n_7\, S(3) => \cr_int[3]_i_85_n_0\, S(2) => \cr_int[3]_i_86_n_0\, S(1) => \cr_int[3]_i_87_n_0\, S(0) => \cr_int[3]_i_88_n_0\ ); \cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_65_n_0\, CO(2) => \cr_int_reg[3]_i_65_n_1\, CO(1) => \cr_int_reg[3]_i_65_n_2\, CO(0) => \cr_int_reg[3]_i_65_n_3\, CYINIT => '0', DI(3 downto 2) => rgb888(9 downto 8), DI(1 downto 0) => B"01", O(3) => \cr_int_reg[3]_i_65_n_4\, O(2) => \cr_int_reg[3]_i_65_n_5\, O(1) => \cr_int_reg[3]_i_65_n_6\, O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0), S(3) => \cr_int[3]_i_89_n_0\, S(2) => \cr_int[3]_i_90_n_0\, S(1) => \cr_int[3]_i_91_n_0\, S(0) => \cr_int[3]_i_92_n_0\ ); \cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_70_n_0\, CO(2) => \cr_int_reg[3]_i_70_n_1\, CO(1) => \cr_int_reg[3]_i_70_n_2\, CO(0) => \cr_int_reg[3]_i_70_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(12 downto 10), DI(0) => '0', O(3) => \cr_int_reg[3]_i_70_n_4\, O(2) => \cr_int_reg[3]_i_70_n_5\, O(1) => \cr_int_reg[3]_i_70_n_6\, O(0) => \cr_int_reg[3]_i_70_n_7\, S(3) => \cr_int[3]_i_93_n_0\, S(2) => \cr_int[3]_i_94_n_0\, S(1) => \cr_int[3]_i_95_n_0\, S(0) => \cr_int[3]_i_96_n_0\ ); \cr_int_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[7]_i_1_n_7\, Q => \cr_int_reg_n_0_[4]\, R => '0' ); \cr_int_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[7]_i_1_n_6\, Q => \cr_int_reg_n_0_[5]\, R => '0' ); \cr_int_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[7]_i_1_n_5\, Q => \cr_int_reg_n_0_[6]\, R => '0' ); \cr_int_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[7]_i_1_n_4\, Q => \cr_int_reg_n_0_[7]\, R => '0' ); \cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_1_n_0\, CO(3) => \cr_int_reg[7]_i_1_n_0\, CO(2) => \cr_int_reg[7]_i_1_n_1\, CO(1) => \cr_int_reg[7]_i_1_n_2\, CO(0) => \cr_int_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[7]_i_2_n_0\, DI(2) => \cr_int[7]_i_3_n_0\, DI(1) => \cr_int[7]_i_4_n_0\, DI(0) => \cr_int[7]_i_5_n_0\, O(3) => \cr_int_reg[7]_i_1_n_4\, O(2) => \cr_int_reg[7]_i_1_n_5\, O(1) => \cr_int_reg[7]_i_1_n_6\, O(0) => \cr_int_reg[7]_i_1_n_7\, S(3) => \cr_int[7]_i_6_n_0\, S(2) => \cr_int[7]_i_7_n_0\, S(1) => \cr_int[7]_i_8_n_0\, S(0) => \cr_int[7]_i_9_n_0\ ); \cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_20_n_0\, CO(3) => \cr_int_reg[7]_i_23_n_0\, CO(2) => \cr_int_reg[7]_i_23_n_1\, CO(1) => \cr_int_reg[7]_i_23_n_2\, CO(0) => \cr_int_reg[7]_i_23_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0), S(3) => \cr_int[7]_i_25_n_0\, S(2) => \cr_int[7]_i_26_n_0\, S(1) => \cr_int[7]_i_27_n_0\, S(0) => \cr_int[7]_i_28_n_0\ ); \cr_int_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[11]_i_1_n_7\, Q => \cr_int_reg__0\(8), R => '0' ); \cr_int_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[11]_i_1_n_6\, Q => \cr_int_reg__0\(9), R => '0' ); \cr_reg[0]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[0]_i_1_n_0\, Q => cr(0), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[1]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[1]_i_1_n_0\, Q => cr(1), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[2]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[2]_i_1_n_0\, Q => cr(2), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[3]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[3]_i_1_n_0\, Q => cr(3), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[4]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[4]_i_1_n_0\, Q => cr(4), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[5]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[5]_i_1_n_0\, Q => cr(5), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[6]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[6]_i_1_n_0\, Q => cr(6), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[7]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[7]_i_2_n_0\, Q => cr(7), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_reg[7]_i_3_n_0\, CO(3) => \cr_reg[7]_i_1_n_0\, CO(2) => \cr_reg[7]_i_1_n_1\, CO(1) => \cr_reg[7]_i_1_n_2\, CO(0) => \cr_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \cr[7]_i_4_n_0\, DI(2) => \cr[7]_i_5_n_0\, DI(1) => \cr[7]_i_6_n_0\, DI(0) => \cr[7]_i_7_n_0\, O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \cr[7]_i_8_n_0\, S(2) => \cr[7]_i_9_n_0\, S(1) => \cr[7]_i_10_n_0\, S(0) => \cr[7]_i_11_n_0\ ); \cr_reg[7]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_reg[7]_i_12_n_0\, CO(2) => \cr_reg[7]_i_12_n_1\, CO(1) => \cr_reg[7]_i_12_n_2\, CO(0) => \cr_reg[7]_i_12_n_3\, CYINIT => '0', DI(3) => \cr[7]_i_21_n_0\, DI(2) => \cr[7]_i_22_n_0\, DI(1) => \cr[7]_i_23_n_0\, DI(0) => \cr[7]_i_24_n_0\, O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0), S(3) => \cr[7]_i_25_n_0\, S(2) => \cr[7]_i_26_n_0\, S(1) => \cr[7]_i_27_n_0\, S(0) => \cr[7]_i_28_n_0\ ); \cr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \cr_reg[7]_i_12_n_0\, CO(3) => \cr_reg[7]_i_3_n_0\, CO(2) => \cr_reg[7]_i_3_n_1\, CO(1) => \cr_reg[7]_i_3_n_2\, CO(0) => \cr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3) => \cr[7]_i_13_n_0\, DI(2) => \cr[7]_i_14_n_0\, DI(1) => \cr[7]_i_15_n_0\, DI(0) => \cr[7]_i_16_n_0\, O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0), S(3) => \cr[7]_i_17_n_0\, S(2) => \cr[7]_i_18_n_0\, S(1) => \cr[7]_i_19_n_0\, S(0) => \cr[7]_i_20_n_0\ ); edge_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => edge, O => edge_i_1_n_0 ); edge_rb_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => edge, I1 => edge_rb, O => edge_rb_i_1_n_0 ); edge_rb_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_x2, CE => '1', D => edge_rb_i_1_n_0, Q => edge_rb, R => \hdmi_d[15]_i_1_n_0\ ); edge_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_x2, CE => '1', D => edge_i_1_n_0, Q => edge, R => '0' ); \hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => edge_i_1_n_0, Q => D1, R => '0' ); \hdmi_d[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(2), I1 => \cr_hold_reg_n_0_[2]\, I2 => y_hold(2), I3 => edge_rb, I4 => y(2), I5 => edge, O => \hdmi_d[10]_i_1_n_0\ ); \hdmi_d[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(3), I1 => \cr_hold_reg_n_0_[3]\, I2 => y_hold(3), I3 => edge_rb, I4 => y(3), I5 => edge, O => \hdmi_d[11]_i_1_n_0\ ); \hdmi_d[12]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(4), I1 => \cr_hold_reg_n_0_[4]\, I2 => y_hold(4), I3 => edge_rb, I4 => y(4), I5 => edge, O => \hdmi_d[12]_i_1_n_0\ ); \hdmi_d[13]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(5), I1 => \cr_hold_reg_n_0_[5]\, I2 => y_hold(5), I3 => edge_rb, I4 => y(5), I5 => edge, O => \hdmi_d[13]_i_1_n_0\ ); \hdmi_d[14]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(6), I1 => \cr_hold_reg_n_0_[6]\, I2 => y_hold(6), I3 => edge_rb, I4 => y(6), I5 => edge, O => \hdmi_d[14]_i_1_n_0\ ); \hdmi_d[15]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active, O => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(7), I1 => \cr_hold_reg_n_0_[7]\, I2 => y_hold(7), I3 => edge_rb, I4 => y(7), I5 => edge, O => \hdmi_d[15]_i_2_n_0\ ); \hdmi_d[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(0), I1 => \cr_hold_reg_n_0_[0]\, I2 => y_hold(0), I3 => edge_rb, I4 => y(0), I5 => edge, O => \hdmi_d[8]_i_1_n_0\ ); \hdmi_d[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(1), I1 => \cr_hold_reg_n_0_[1]\, I2 => y_hold(1), I3 => edge_rb, I4 => y(1), I5 => edge, O => \hdmi_d[9]_i_1_n_0\ ); \hdmi_d_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[10]_i_1_n_0\, Q => hdmi_d(2), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[11]_i_1_n_0\, Q => hdmi_d(3), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[12]_i_1_n_0\, Q => hdmi_d(4), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[13]_i_1_n_0\, Q => hdmi_d(5), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[14]_i_1_n_0\, Q => hdmi_d(6), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[15]_i_2_n_0\, Q => hdmi_d(7), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[8]_i_1_n_0\, Q => hdmi_d(0), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[9]_i_1_n_0\, Q => hdmi_d(1), R => \hdmi_d[15]_i_1_n_0\ ); hdmi_de_reg: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => active, Q => hdmi_de, R => '0' ); hdmi_hsync_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => hsync, O => p_0_in ); hdmi_hsync_reg: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => p_0_in, Q => hdmi_hsync, R => '0' ); hdmi_vsync_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => vsync, O => hdmi_vsync_i_1_n_0 ); hdmi_vsync_reg: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => hdmi_vsync_i_1_n_0, Q => hdmi_vsync, R => '0' ); \y[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[0]\, I1 => \y_int_reg__0\(31), O => \y[0]_i_1_n_0\ ); \y[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[1]\, I1 => \y_int_reg__0\(31), O => \y[1]_i_1_n_0\ ); \y[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[2]\, I1 => \y_int_reg__0\(31), O => \y[2]_i_1_n_0\ ); \y[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[3]\, I1 => \y_int_reg__0\(31), O => \y[3]_i_1_n_0\ ); \y[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[4]\, I1 => \y_int_reg__0\(31), O => \y[4]_i_1_n_0\ ); \y[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[5]\, I1 => \y_int_reg__0\(31), O => \y[5]_i_1_n_0\ ); \y[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[6]\, I1 => \y_int_reg__0\(31), O => \y[6]_i_1_n_0\ ); \y[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(26), I1 => \y_int_reg__0\(27), O => \y[7]_i_10_n_0\ ); \y[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(24), I1 => \y_int_reg__0\(25), O => \y[7]_i_11_n_0\ ); \y[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(22), I1 => \y_int_reg__0\(23), O => \y[7]_i_13_n_0\ ); \y[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(20), I1 => \y_int_reg__0\(21), O => \y[7]_i_14_n_0\ ); \y[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(18), I1 => \y_int_reg__0\(19), O => \y[7]_i_15_n_0\ ); \y[7]_i_16\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(16), I1 => \y_int_reg__0\(17), O => \y[7]_i_16_n_0\ ); \y[7]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(22), I1 => \y_int_reg__0\(23), O => \y[7]_i_17_n_0\ ); \y[7]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(20), I1 => \y_int_reg__0\(21), O => \y[7]_i_18_n_0\ ); \y[7]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(18), I1 => \y_int_reg__0\(19), O => \y[7]_i_19_n_0\ ); \y[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[7]\, I1 => \y_int_reg__0\(31), O => \y[7]_i_2_n_0\ ); \y[7]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(16), I1 => \y_int_reg__0\(17), O => \y[7]_i_20_n_0\ ); \y[7]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(14), I1 => \y_int_reg__0\(15), O => \y[7]_i_21_n_0\ ); \y[7]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(12), I1 => \y_int_reg__0\(13), O => \y[7]_i_22_n_0\ ); \y[7]_i_23\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(10), I1 => \y_int_reg__0\(11), O => \y[7]_i_23_n_0\ ); \y[7]_i_24\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(8), I1 => \y_int_reg__0\(9), O => \y[7]_i_24_n_0\ ); \y[7]_i_25\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(14), I1 => \y_int_reg__0\(15), O => \y[7]_i_25_n_0\ ); \y[7]_i_26\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(12), I1 => \y_int_reg__0\(13), O => \y[7]_i_26_n_0\ ); \y[7]_i_27\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(10), I1 => \y_int_reg__0\(11), O => \y[7]_i_27_n_0\ ); \y[7]_i_28\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(8), I1 => \y_int_reg__0\(9), O => \y[7]_i_28_n_0\ ); \y[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg__0\(30), I1 => \y_int_reg__0\(31), O => \y[7]_i_4_n_0\ ); \y[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(28), I1 => \y_int_reg__0\(29), O => \y[7]_i_5_n_0\ ); \y[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(26), I1 => \y_int_reg__0\(27), O => \y[7]_i_6_n_0\ ); \y[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(24), I1 => \y_int_reg__0\(25), O => \y[7]_i_7_n_0\ ); \y[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(30), I1 => \y_int_reg__0\(31), O => \y[7]_i_8_n_0\ ); \y[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(28), I1 => \y_int_reg__0\(29), O => \y[7]_i_9_n_0\ ); \y_hold[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(0), I1 => y(0), I2 => edge_rb, O => p_1_in(0) ); \y_hold[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(1), I1 => y(1), I2 => edge_rb, O => p_1_in(1) ); \y_hold[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(2), I1 => y(2), I2 => edge_rb, O => p_1_in(2) ); \y_hold[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(3), I1 => y(3), I2 => edge_rb, O => p_1_in(3) ); \y_hold[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(4), I1 => y(4), I2 => edge_rb, O => p_1_in(4) ); \y_hold[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(5), I1 => y(5), I2 => edge_rb, O => p_1_in(5) ); \y_hold[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(6), I1 => y(6), I2 => edge_rb, O => p_1_in(6) ); \y_hold[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(7), I1 => y(7), I2 => edge_rb, O => p_1_in(7) ); \y_hold_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(0), Q => y_hold(0), R => '0' ); \y_hold_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(1), Q => y_hold(1), R => '0' ); \y_hold_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(2), Q => y_hold(2), R => '0' ); \y_hold_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(3), Q => y_hold(3), R => '0' ); \y_hold_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(4), Q => y_hold(4), R => '0' ); \y_hold_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(5), Q => y_hold(5), R => '0' ); \y_hold_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(6), Q => y_hold(6), R => '0' ); \y_hold_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(7), Q => y_hold(7), R => '0' ); \y_int[11]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \y_int_reg[15]_i_33_n_6\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_29\(0), I3 => \^y_int_reg[3]_1\(0), O => \y_int[11]_i_10_n_0\ ); \y_int[11]_i_100\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), I1 => rgb888(0), O => \y_int[11]_i_100_n_0\ ); \y_int[11]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(1), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[15]_0\(1), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(10) ); \y_int[11]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \y_int_reg[15]_i_33_n_7\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_22\(3), I3 => \^y_int_reg[3]_1\(0), O => \y_int[11]_i_12_n_0\ ); \y_int[11]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(0), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[15]_0\(0), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(9) ); \y_int[11]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[11]_i_38_n_4\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_21\(1), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[8]_22\(2), O => \y_int[11]_i_16_n_0\ ); \y_int[11]_i_17\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg2(8), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[11]_i_21_n_4\, I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(8) ); \y_int[11]_i_18\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(7), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_8_n_6\, I3 => y_int_reg6, I4 => y_int_reg5(15), O => y_int_reg20_in(7) ); \y_int[11]_i_19\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[11]_i_38_n_5\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_21\(0), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[8]_22\(1), O => \y_int[11]_i_19_n_0\ ); \y_int[11]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(18), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(10), I4 => \y_int[11]_i_10_n_0\, I5 => y_int_reg1(10), O => \y_int[11]_i_2_n_0\ ); \y_int[11]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(11), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(19), I3 => y_int_reg6, O => y_int_reg20_in(11) ); \y_int[11]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(10), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(18), I3 => y_int_reg6, O => y_int_reg20_in(10) ); \y_int[11]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(9), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(17), I3 => y_int_reg6, O => y_int_reg20_in(9) ); \y_int[11]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(8), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(16), I3 => y_int_reg6, O => y_int_reg20_in(8) ); \y_int[11]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[11]_i_29_n_0\ ); \y_int[11]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(17), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(9), I4 => \y_int[11]_i_12_n_0\, I5 => y_int_reg1(9), O => \y_int[11]_i_3_n_0\ ); \y_int[11]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_6\, O => \y_int[11]_i_30_n_0\ ); \y_int[11]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_7\, O => \y_int[11]_i_31_n_0\ ); \y_int[11]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_4\, O => \y_int[11]_i_32_n_0\ ); \y_int[11]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(16), O => \y_int[11]_i_34_n_0\ ); \y_int[11]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(15), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_8_n_6\, O => \y_int[11]_i_35_n_0\ ); \y_int[11]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(14), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_8_n_7\, O => \y_int[11]_i_36_n_0\ ); \y_int[11]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(13), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_16_n_4\, O => \y_int[11]_i_37_n_0\ ); \y_int[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(16), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(8), I4 => \y_int[11]_i_16_n_0\, I5 => y_int_reg1(8), O => \y_int[11]_i_4_n_0\ ); \y_int[11]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^y_int_reg[23]_0\(0), I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[11]_i_21_n_4\, O => \y_int[11]_i_40_n_0\ ); \y_int[11]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^y_int_reg[23]_0\(0), I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[11]_i_21_n_5\, O => \y_int[11]_i_41_n_0\ ); \y_int[11]_i_42\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^y_int_reg[23]_0\(0), I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[11]_i_21_n_6\, O => \y_int[11]_i_42_n_0\ ); \y_int[11]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_21_n_7\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_11_n_5\, O => \y_int[11]_i_43_n_0\ ); \y_int[11]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_45_n_0\ ); \y_int[11]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_46_n_0\ ); \y_int[11]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_47_n_0\ ); \y_int[11]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_5\, O => \y_int[11]_i_48_n_0\ ); \y_int[11]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"E888E888E8EEE888" ) port map ( I0 => y_int_reg20_in(7), I1 => \y_int[11]_i_19_n_0\, I2 => y_int_reg2(7), I3 => \^y_int_reg[23]_0\(0), I4 => \y_int_reg[11]_i_21_n_5\, I5 => \^y_int_reg[7]_0\(0), O => \y_int[11]_i_5_n_0\ ); \y_int[11]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_50_n_0\ ); \y_int[11]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_51_n_0\ ); \y_int[11]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_52_n_0\ ); \y_int[11]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_53_n_0\ ); \y_int[11]_i_58\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_5\, O => \y_int[11]_i_58_n_0\ ); \y_int[11]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_6\, O => \y_int[11]_i_59_n_0\ ); \y_int[11]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[11]_i_2_n_0\, I1 => y_int_reg1(11), I2 => \y_int[15]_i_18_n_0\, I3 => y_int_reg20_in(11), O => \y_int[11]_i_6_n_0\ ); \y_int[11]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_7\, O => \y_int[11]_i_60_n_0\ ); \y_int[11]_i_61\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_4\, O => \y_int[11]_i_61_n_0\ ); \y_int[11]_i_62\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(8), I1 => y_int_reg6, I2 => \y_int_reg[3]_i_16_n_5\, O => \y_int[11]_i_62_n_0\ ); \y_int[11]_i_63\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(12), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_16_n_5\, O => \y_int[11]_i_63_n_0\ ); \y_int[11]_i_64\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(11), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_16_n_6\, O => \y_int[11]_i_64_n_0\ ); \y_int[11]_i_65\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(10), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_16_n_7\, O => \y_int[11]_i_65_n_0\ ); \y_int[11]_i_66\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(9), I1 => y_int_reg6, I2 => \y_int_reg[3]_i_16_n_4\, O => \y_int[11]_i_66_n_0\ ); \y_int[11]_i_67\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[8]_22\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_21\(1), O => \y_int[11]_i_67_n_0\ ); \y_int[11]_i_68\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[8]_22\(1), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_21\(0), O => \y_int[11]_i_68_n_0\ ); \y_int[11]_i_69\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[8]_22\(0), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_20\(3), O => \y_int[11]_i_69_n_0\ ); \y_int[11]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[11]_i_3_n_0\, I1 => y_int_reg1(10), I2 => \y_int[11]_i_10_n_0\, I3 => y_int_reg20_in(10), O => \y_int[11]_i_7_n_0\ ); \y_int[11]_i_70\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_1\(3), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_20\(2), O => \y_int[11]_i_70_n_0\ ); \y_int[11]_i_71\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[3]_i_35_n_4\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_30_n_6\, O => \y_int[11]_i_71_n_0\ ); \y_int[11]_i_72\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_44_n_4\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_11_n_6\, O => \y_int[11]_i_72_n_0\ ); \y_int[11]_i_73\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_44_n_5\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_11_n_7\, O => \y_int[11]_i_73_n_0\ ); \y_int[11]_i_74\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_44_n_6\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_30_n_4\, O => \y_int[11]_i_74_n_0\ ); \y_int[11]_i_75\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_44_n_7\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_30_n_5\, O => \y_int[11]_i_75_n_0\ ); \y_int[11]_i_76\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_6\, O => \y_int[11]_i_76_n_0\ ); \y_int[11]_i_77\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_7\, O => \y_int[11]_i_77_n_0\ ); \y_int[11]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_4\, O => \y_int[11]_i_78_n_0\ ); \y_int[11]_i_79\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_5\, O => \y_int[11]_i_79_n_0\ ); \y_int[11]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[11]_i_4_n_0\, I1 => y_int_reg1(9), I2 => \y_int[11]_i_12_n_0\, I3 => y_int_reg20_in(9), O => \y_int[11]_i_8_n_0\ ); \y_int[11]_i_81\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_81_n_0\ ); \y_int[11]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_82_n_0\ ); \y_int[11]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_83_n_0\ ); \y_int[11]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_84_n_0\ ); \y_int[11]_i_86\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_11_n_6\, I1 => \y_int_reg[31]_i_11_n_5\, O => \y_int[11]_i_86_n_0\ ); \y_int[11]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_30_n_4\, I1 => \y_int_reg[31]_i_11_n_7\, O => \y_int[11]_i_87_n_0\ ); \y_int[11]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_30_n_6\, I1 => \y_int_reg[31]_i_30_n_5\, O => \y_int[11]_i_88_n_0\ ); \y_int[11]_i_89\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_89_n_0\ ); \y_int[11]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[11]_i_5_n_0\, I1 => y_int_reg1(8), I2 => \y_int[11]_i_16_n_0\, I3 => y_int_reg20_in(8), O => \y_int[11]_i_9_n_0\ ); \y_int[11]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_5\, I1 => \y_int_reg[31]_i_11_n_6\, O => \y_int[11]_i_90_n_0\ ); \y_int[11]_i_91\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_7\, I1 => \y_int_reg[31]_i_30_n_4\, O => \y_int[11]_i_91_n_0\ ); \y_int[11]_i_92\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_5\, I1 => \y_int_reg[31]_i_30_n_6\, O => \y_int[11]_i_92_n_0\ ); \y_int[11]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_62_n_4\, I1 => \y_int_reg[31]_i_30_n_7\, O => \y_int[11]_i_93_n_0\ ); \y_int[11]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_62_n_6\, I1 => \y_int_reg[31]_i_62_n_5\, O => \y_int[11]_i_94_n_0\ ); \y_int[11]_i_95\: unisim.vcomponents.LUT3 generic map( INIT => X"BE" ) port map ( I0 => \y_int_reg[31]_i_88_n_6\, I1 => \y_int_reg[31]_i_88_n_5\, I2 => rgb888(0), O => \y_int[11]_i_95_n_0\ ); \y_int[11]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rgb888(0), I1 => rgb888(1), O => \y_int[11]_i_96_n_0\ ); \y_int[11]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_7\, I1 => \y_int_reg[31]_i_62_n_4\, O => \y_int[11]_i_97_n_0\ ); \y_int[11]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_62_n_5\, I1 => \y_int_reg[31]_i_62_n_6\, O => \y_int[11]_i_98_n_0\ ); \y_int[11]_i_99\: unisim.vcomponents.LUT3 generic map( INIT => X"09" ) port map ( I0 => rgb888(0), I1 => \y_int_reg[31]_i_88_n_5\, I2 => \y_int_reg[31]_i_88_n_6\, O => \y_int[11]_i_99_n_0\ ); \y_int[15]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_28\(1), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_27\(0), I3 => \^y_int_reg[3]_1\(0), O => \y_int[15]_i_10_n_0\ ); \y_int[15]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(5), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[19]_0\(1), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(14) ); \y_int[15]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_28\(0), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_29\(3), I3 => \^y_int_reg[3]_1\(0), O => \y_int[15]_i_12_n_0\ ); \y_int[15]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(4), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[19]_0\(0), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(13) ); \y_int[15]_i_16\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \y_int_reg[15]_i_33_n_4\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_29\(2), I3 => \^y_int_reg[3]_1\(0), O => \y_int[15]_i_16_n_0\ ); \y_int[15]_i_17\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(3), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[15]_0\(3), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(12) ); \y_int[15]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \y_int_reg[15]_i_33_n_5\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_29\(1), I3 => \^y_int_reg[3]_1\(0), O => \y_int[15]_i_18_n_0\ ); \y_int[15]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(2), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[15]_0\(2), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(11) ); \y_int[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(22), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(14), I4 => \y_int[15]_i_10_n_0\, I5 => y_int_reg1(14), O => \y_int[15]_i_2_n_0\ ); \y_int[15]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(15), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(23), I3 => y_int_reg6, O => y_int_reg20_in(15) ); \y_int[15]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(14), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(22), I3 => y_int_reg6, O => y_int_reg20_in(14) ); \y_int[15]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(13), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(21), I3 => y_int_reg6, O => y_int_reg20_in(13) ); \y_int[15]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(12), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(20), I3 => y_int_reg6, O => y_int_reg20_in(12) ); \y_int[15]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[15]_i_25_n_0\ ); \y_int[15]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[15]_i_26_n_0\ ); \y_int[15]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[15]_i_27_n_0\ ); \y_int[15]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[15]_i_28_n_0\ ); \y_int[15]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(20), O => \y_int[15]_i_29_n_0\ ); \y_int[15]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(21), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(13), I4 => \y_int[15]_i_12_n_0\, I5 => y_int_reg1(13), O => \y_int[15]_i_3_n_0\ ); \y_int[15]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(19), O => \y_int[15]_i_30_n_0\ ); \y_int[15]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(18), O => \y_int[15]_i_31_n_0\ ); \y_int[15]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(17), O => \y_int[15]_i_32_n_0\ ); \y_int[15]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(20), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(12), I4 => \y_int[15]_i_16_n_0\, I5 => y_int_reg1(12), O => \y_int[15]_i_4_n_0\ ); \y_int[15]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_29\(2), O => \y_int[15]_i_40_n_0\ ); \y_int[15]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_29\(1), O => \y_int[15]_i_41_n_0\ ); \y_int[15]_i_42\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_29\(0), O => \y_int[15]_i_42_n_0\ ); \y_int[15]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_22\(3), O => \y_int[15]_i_43_n_0\ ); \y_int[15]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[15]_i_48_n_0\ ); \y_int[15]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[15]_i_49_n_0\ ); \y_int[15]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(19), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(11), I4 => \y_int[15]_i_18_n_0\, I5 => y_int_reg1(11), O => \y_int[15]_i_5_n_0\ ); \y_int[15]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[15]_i_50_n_0\ ); \y_int[15]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[15]_i_51_n_0\ ); \y_int[15]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[15]_i_2_n_0\, I1 => y_int_reg1(15), I2 => \y_int[19]_i_18_n_0\, I3 => y_int_reg20_in(15), O => \y_int[15]_i_6_n_0\ ); \y_int[15]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[15]_i_3_n_0\, I1 => y_int_reg1(14), I2 => \y_int[15]_i_10_n_0\, I3 => y_int_reg20_in(14), O => \y_int[15]_i_7_n_0\ ); \y_int[15]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[15]_i_4_n_0\, I1 => y_int_reg1(13), I2 => \y_int[15]_i_12_n_0\, I3 => y_int_reg20_in(13), O => \y_int[15]_i_8_n_0\ ); \y_int[15]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[15]_i_5_n_0\, I1 => y_int_reg1(12), I2 => \y_int[15]_i_16_n_0\, I3 => y_int_reg20_in(12), O => \y_int[15]_i_9_n_0\ ); \y_int[19]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_26\(1), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_25\(0), I3 => \^y_int_reg[3]_1\(0), O => \y_int[19]_i_10_n_0\ ); \y_int[19]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(9), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_2\(1), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(18) ); \y_int[19]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_26\(0), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_27\(3), I3 => \^y_int_reg[3]_1\(0), O => \y_int[19]_i_12_n_0\ ); \y_int[19]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(8), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_2\(0), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(17) ); \y_int[19]_i_16\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_28\(3), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_27\(2), I3 => \^y_int_reg[3]_1\(0), O => \y_int[19]_i_16_n_0\ ); \y_int[19]_i_17\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(7), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[19]_0\(3), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(16) ); \y_int[19]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_28\(2), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_27\(1), I3 => \^y_int_reg[3]_1\(0), O => \y_int[19]_i_18_n_0\ ); \y_int[19]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(6), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[19]_0\(2), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(15) ); \y_int[19]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(26), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(18), I4 => \y_int[19]_i_10_n_0\, I5 => y_int_reg1(18), O => \y_int[19]_i_2_n_0\ ); \y_int[19]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(19), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(27), I3 => y_int_reg6, O => y_int_reg20_in(19) ); \y_int[19]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(18), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(26), I3 => y_int_reg6, O => y_int_reg20_in(18) ); \y_int[19]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(17), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(25), I3 => y_int_reg6, O => y_int_reg20_in(17) ); \y_int[19]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(16), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(24), I3 => y_int_reg6, O => y_int_reg20_in(16) ); \y_int[19]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[19]_i_25_n_0\ ); \y_int[19]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[19]_i_26_n_0\ ); \y_int[19]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[19]_i_27_n_0\ ); \y_int[19]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[19]_i_28_n_0\ ); \y_int[19]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(24), O => \y_int[19]_i_29_n_0\ ); \y_int[19]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(25), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(17), I4 => \y_int[19]_i_12_n_0\, I5 => y_int_reg1(17), O => \y_int[19]_i_3_n_0\ ); \y_int[19]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(23), O => \y_int[19]_i_30_n_0\ ); \y_int[19]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(22), O => \y_int[19]_i_31_n_0\ ); \y_int[19]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(21), O => \y_int[19]_i_32_n_0\ ); \y_int[19]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(24), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(16), I4 => \y_int[19]_i_16_n_0\, I5 => y_int_reg1(16), O => \y_int[19]_i_4_n_0\ ); \y_int[19]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[19]_i_48_n_0\ ); \y_int[19]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[19]_i_49_n_0\ ); \y_int[19]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(23), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(15), I4 => \y_int[19]_i_18_n_0\, I5 => y_int_reg1(15), O => \y_int[19]_i_5_n_0\ ); \y_int[19]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[19]_i_50_n_0\ ); \y_int[19]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[19]_i_51_n_0\ ); \y_int[19]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[19]_i_2_n_0\, I1 => y_int_reg1(19), I2 => \y_int[23]_i_20_n_0\, I3 => y_int_reg20_in(19), O => \y_int[19]_i_6_n_0\ ); \y_int[19]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[19]_i_3_n_0\, I1 => y_int_reg1(18), I2 => \y_int[19]_i_10_n_0\, I3 => y_int_reg20_in(18), O => \y_int[19]_i_7_n_0\ ); \y_int[19]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[19]_i_4_n_0\, I1 => y_int_reg1(17), I2 => \y_int[19]_i_12_n_0\, I3 => y_int_reg20_in(17), O => \y_int[19]_i_8_n_0\ ); \y_int[19]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[19]_i_5_n_0\, I1 => y_int_reg1(16), I2 => \y_int[19]_i_16_n_0\, I3 => y_int_reg20_in(16), O => \y_int[19]_i_9_n_0\ ); \y_int[23]_i_100\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_19\(0), I1 => \^y_int_reg[3]_0\(0), O => \y_int[23]_i_100_n_0\ ); \y_int[23]_i_101\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[14]\(0), I1 => \^y_int_reg[3]_0\(3), O => \y_int[23]_i_101_n_0\ ); \y_int[23]_i_102\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[3]_0\(2), I1 => \^y_int_reg[3]_0\(1), O => \y_int[23]_i_102_n_0\ ); \y_int[23]_i_103\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[3]_0\(0), I1 => \rgb888[8]_19\(0), O => \y_int[23]_i_103_n_0\ ); \y_int[23]_i_104\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(8), O => \y_int[23]_i_104_n_0\ ); \y_int[23]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_23\(1), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_24\(0), I3 => \^y_int_reg[3]_1\(0), O => \y_int[23]_i_12_n_0\ ); \y_int[23]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(13), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_1\(1), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(22) ); \y_int[23]_i_14\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_23\(0), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_25\(3), I3 => \^y_int_reg[3]_1\(0), O => \y_int[23]_i_14_n_0\ ); \y_int[23]_i_15\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(12), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_1\(0), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(21) ); \y_int[23]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_26\(3), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_25\(2), I3 => \^y_int_reg[3]_1\(0), O => \y_int[23]_i_18_n_0\ ); \y_int[23]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(11), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_2\(3), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(20) ); \y_int[23]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(30), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(22), I4 => \y_int[23]_i_12_n_0\, I5 => y_int_reg1(22), O => \y_int[23]_i_2_n_0\ ); \y_int[23]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_26\(2), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_25\(1), I3 => \^y_int_reg[3]_1\(0), O => \y_int[23]_i_20_n_0\ ); \y_int[23]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(10), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_2\(2), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(19) ); \y_int[23]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(22), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(30), I3 => y_int_reg6, O => y_int_reg20_in(22) ); \y_int[23]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(21), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(29), I3 => y_int_reg6, O => y_int_reg20_in(21) ); \y_int[23]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(20), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(28), I3 => y_int_reg6, O => y_int_reg20_in(20) ); \y_int[23]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_26_n_0\ ); \y_int[23]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_27_n_0\ ); \y_int[23]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_28_n_0\ ); \y_int[23]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_29_n_0\ ); \y_int[23]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(29), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(21), I4 => \y_int[23]_i_14_n_0\, I5 => y_int_reg1(21), O => \y_int[23]_i_3_n_0\ ); \y_int[23]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_30_n_0\ ); \y_int[23]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_31_n_0\ ); \y_int[23]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_36_n_0\ ); \y_int[23]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_37_n_0\ ); \y_int[23]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_38_n_0\ ); \y_int[23]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_39_n_0\ ); \y_int[23]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(28), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(20), I4 => \y_int[23]_i_18_n_0\, I5 => y_int_reg1(20), O => \y_int[23]_i_4_n_0\ ); \y_int[23]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(28), O => \y_int[23]_i_40_n_0\ ); \y_int[23]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(27), O => \y_int[23]_i_41_n_0\ ); \y_int[23]_i_42\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(26), O => \y_int[23]_i_42_n_0\ ); \y_int[23]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(25), O => \y_int[23]_i_43_n_0\ ); \y_int[23]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_46_n_0\ ); \y_int[23]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_47_n_0\ ); \y_int[23]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_48_n_0\ ); \y_int[23]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_49_n_0\ ); \y_int[23]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(27), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(19), I4 => \y_int[23]_i_20_n_0\, I5 => y_int_reg1(19), O => \y_int[23]_i_5_n_0\ ); \y_int[23]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_52_n_0\ ); \y_int[23]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_53_n_0\ ); \y_int[23]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_54_n_0\ ); \y_int[23]_i_55\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_55_n_0\ ); \y_int[23]_i_56\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_56_n_0\ ); \y_int[23]_i_57\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_57_n_0\ ); \y_int[23]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[23]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[23]_i_6_n_0\ ); \y_int[23]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_62_n_0\ ); \y_int[23]_i_63\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_63_n_0\ ); \y_int[23]_i_64\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_64_n_0\ ); \y_int[23]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_65_n_0\ ); \y_int[23]_i_67\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_8_n_7\, I1 => \y_int_reg[31]_i_8_n_6\, O => \y_int[23]_i_67_n_0\ ); \y_int[23]_i_68\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_16_n_5\, I1 => \y_int_reg[31]_i_16_n_4\, O => \y_int[23]_i_68_n_0\ ); \y_int[23]_i_69\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_16_n_7\, I1 => \y_int_reg[31]_i_16_n_6\, O => \y_int[23]_i_69_n_0\ ); \y_int[23]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[23]_i_3_n_0\, I1 => y_int_reg1(22), I2 => \y_int[23]_i_12_n_0\, I3 => y_int_reg20_in(22), O => \y_int[23]_i_7_n_0\ ); \y_int[23]_i_70\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[3]_i_16_n_5\, I1 => \y_int_reg[3]_i_16_n_4\, O => \y_int[23]_i_70_n_0\ ); \y_int[23]_i_71\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_6\, I1 => \y_int_reg[31]_i_8_n_7\, O => \y_int[23]_i_71_n_0\ ); \y_int[23]_i_72\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_4\, I1 => \y_int_reg[31]_i_16_n_5\, O => \y_int[23]_i_72_n_0\ ); \y_int[23]_i_73\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_6\, I1 => \y_int_reg[31]_i_16_n_7\, O => \y_int[23]_i_73_n_0\ ); \y_int[23]_i_74\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_4\, I1 => \y_int_reg[3]_i_16_n_5\, O => \y_int[23]_i_74_n_0\ ); \y_int[23]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_21\(1), I1 => \rgb888[8]_21\(2), O => \y_int[23]_i_76_n_0\ ); \y_int[23]_i_77\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_77_n_0\ ); \y_int[23]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_78_n_0\ ); \y_int[23]_i_79\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_79_n_0\ ); \y_int[23]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[23]_i_4_n_0\, I1 => y_int_reg1(21), I2 => \y_int[23]_i_14_n_0\, I3 => y_int_reg20_in(21), O => \y_int[23]_i_8_n_0\ ); \y_int[23]_i_80\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \rgb888[8]_21\(1), O => \y_int[23]_i_80_n_0\ ); \y_int[23]_i_81\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[3]_i_16_n_7\, I1 => \y_int_reg[3]_i_16_n_6\, O => \y_int[23]_i_81_n_0\ ); \y_int[23]_i_82\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[3]_i_26_n_5\, I1 => \y_int_reg[3]_i_26_n_4\, O => \y_int[23]_i_82_n_0\ ); \y_int[23]_i_83\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[3]_i_26_n_7\, I1 => \y_int_reg[3]_i_26_n_6\, O => \y_int[23]_i_83_n_0\ ); \y_int[23]_i_84\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rgb888(16), I1 => rgb888(17), O => \y_int[23]_i_84_n_0\ ); \y_int[23]_i_85\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_6\, I1 => \y_int_reg[3]_i_16_n_7\, O => \y_int[23]_i_85_n_0\ ); \y_int[23]_i_86\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_4\, I1 => \y_int_reg[3]_i_26_n_5\, O => \y_int[23]_i_86_n_0\ ); \y_int[23]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_6\, I1 => \y_int_reg[3]_i_26_n_7\, O => \y_int[23]_i_87_n_0\ ); \y_int[23]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => rgb888(17), I1 => rgb888(16), O => \y_int[23]_i_88_n_0\ ); \y_int[23]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[23]_i_5_n_0\, I1 => y_int_reg1(20), I2 => \y_int[23]_i_18_n_0\, I3 => y_int_reg20_in(20), O => \y_int[23]_i_9_n_0\ ); \y_int[23]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_20\(3), I1 => \rgb888[8]_21\(0), O => \y_int[23]_i_90_n_0\ ); \y_int[23]_i_91\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_20\(1), I1 => \rgb888[8]_20\(2), O => \y_int[23]_i_91_n_0\ ); \y_int[23]_i_92\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[14]\(3), I1 => \rgb888[8]_20\(0), O => \y_int[23]_i_92_n_0\ ); \y_int[23]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[14]\(1), I1 => \rgb888[14]\(2), O => \y_int[23]_i_93_n_0\ ); \y_int[23]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(0), I1 => \rgb888[8]_20\(3), O => \y_int[23]_i_94_n_0\ ); \y_int[23]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_20\(2), I1 => \rgb888[8]_20\(1), O => \y_int[23]_i_95_n_0\ ); \y_int[23]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_20\(0), I1 => \rgb888[14]\(3), O => \y_int[23]_i_96_n_0\ ); \y_int[23]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[14]\(2), I1 => \rgb888[14]\(1), O => \y_int[23]_i_97_n_0\ ); \y_int[23]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^y_int_reg[3]_0\(3), I1 => \rgb888[14]\(0), O => \y_int[23]_i_98_n_0\ ); \y_int[23]_i_99\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^y_int_reg[3]_0\(1), I1 => \^y_int_reg[3]_0\(2), O => \y_int[23]_i_99_n_0\ ); \y_int[27]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[27]_i_2_n_0\ ); \y_int[27]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[27]_i_3_n_0\ ); \y_int[27]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[27]_i_4_n_0\ ); \y_int[27]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[27]_i_5_n_0\ ); \y_int[31]_i_101\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(7), O => \y_int[31]_i_101_n_0\ ); \y_int[31]_i_104\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(1), I1 => rgb888(3), O => \y_int[31]_i_104_n_0\ ); \y_int[31]_i_105\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => rgb888(3), I1 => rgb888(1), I2 => rgb888(2), O => \y_int[31]_i_105_n_0\ ); \y_int[31]_i_106\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(2), I1 => rgb888(0), O => \y_int[31]_i_106_n_0\ ); \y_int[31]_i_107\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), O => \y_int[31]_i_107_n_0\ ); \y_int[31]_i_108\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(0), O => \y_int[31]_i_108_n_0\ ); \y_int[31]_i_109\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(6), O => \y_int[31]_i_109_n_0\ ); \y_int[31]_i_110\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(7), I1 => rgb888(5), O => \y_int[31]_i_110_n_0\ ); \y_int[31]_i_111\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(6), I1 => rgb888(4), O => \y_int[31]_i_111_n_0\ ); \y_int[31]_i_112\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(5), I1 => rgb888(3), O => \y_int[31]_i_112_n_0\ ); \y_int[31]_i_113\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(4), I1 => rgb888(2), O => \y_int[31]_i_113_n_0\ ); \y_int[31]_i_114\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(3), I1 => rgb888(1), O => \y_int[31]_i_114_n_0\ ); \y_int[31]_i_115\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(2), I1 => rgb888(0), O => \y_int[31]_i_115_n_0\ ); \y_int[31]_i_116\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(1), O => \y_int[31]_i_116_n_0\ ); \y_int[31]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \rgb888[8]_30\(0), O => \y_int[31]_i_13_n_0\ ); \y_int[31]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(30), O => \y_int[31]_i_14_n_0\ ); \y_int[31]_i_15\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(29), O => \y_int[31]_i_15_n_0\ ); \y_int[31]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => rgb888(20), I1 => rgb888(18), I2 => rgb888(19), I3 => rgb888(21), I4 => rgb888(22), I5 => rgb888(23), O => \y_int[31]_i_17_n_0\ ); \y_int[31]_i_18\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(23), I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(19), I4 => rgb888(21), I5 => rgb888(22), O => \y_int[31]_i_18_n_0\ ); \y_int[31]_i_19\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(23), I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(19), I4 => rgb888(21), I5 => rgb888(22), O => \y_int[31]_i_19_n_0\ ); \y_int[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0040004044F40040" ) port map ( I0 => \y_int_reg[31]_i_7_n_1\, I1 => \y_int_reg[31]_i_8_n_5\, I2 => \rgb888[8]_21\(2), I3 => \rgb888[8]_30\(0), I4 => \^y_int_reg[23]_0\(0), I5 => \rgb888[1]_0\(0), O => \y_int[31]_i_2_n_0\ ); \y_int[31]_i_20\: unisim.vcomponents.LUT6 generic map( INIT => X"000000007FFFFFFF" ) port map ( I0 => rgb888(22), I1 => rgb888(21), I2 => rgb888(19), I3 => rgb888(18), I4 => rgb888(20), I5 => rgb888(23), O => \y_int[31]_i_20_n_0\ ); \y_int[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[31]_i_3_n_0\ ); \y_int[31]_i_32\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \rgb888[0]_7\(3), I1 => \y_int_reg[31]_i_75_n_2\, O => \y_int[31]_i_32_n_0\ ); \y_int[31]_i_33\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \rgb888[0]_9\(2), O => \y_int[31]_i_33_n_0\ ); \y_int[31]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \rgb888[0]_9\(2), O => \y_int[31]_i_34_n_0\ ); \y_int[31]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \y_int_reg[31]_i_75_n_2\, I1 => \rgb888[0]_9\(0), I2 => \rgb888[0]_9\(1), O => \y_int[31]_i_35_n_0\ ); \y_int[31]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"36" ) port map ( I0 => \rgb888[0]_7\(3), I1 => \rgb888[0]_9\(0), I2 => \y_int_reg[31]_i_75_n_2\, O => \y_int[31]_i_36_n_0\ ); \y_int[31]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[31]_i_4_n_0\ ); \y_int[31]_i_40\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => rgb888(20), I1 => rgb888(18), I2 => rgb888(19), I3 => rgb888(21), I4 => rgb888(22), O => \y_int[31]_i_40_n_0\ ); \y_int[31]_i_41\: unisim.vcomponents.LUT5 generic map( INIT => X"BEEEEEEE" ) port map ( I0 => \y_int_reg[3]_i_64_n_2\, I1 => rgb888(21), I2 => rgb888(20), I3 => rgb888(18), I4 => rgb888(19), O => \y_int[31]_i_41_n_0\ ); \y_int[31]_i_42\: unisim.vcomponents.LUT5 generic map( INIT => X"7FD51540" ) port map ( I0 => \y_int_reg[3]_i_64_n_2\, I1 => rgb888(18), I2 => rgb888(19), I3 => rgb888(20), I4 => rgb888(23), O => \y_int[31]_i_42_n_0\ ); \y_int[31]_i_43\: unisim.vcomponents.LUT4 generic map( INIT => X"BE28" ) port map ( I0 => \y_int_reg[3]_i_64_n_7\, I1 => rgb888(18), I2 => rgb888(19), I3 => rgb888(22), O => \y_int[31]_i_43_n_0\ ); \y_int[31]_i_44\: unisim.vcomponents.LUT6 generic map( INIT => X"A999999999999999" ) port map ( I0 => rgb888(23), I1 => rgb888(22), I2 => rgb888(21), I3 => rgb888(19), I4 => rgb888(18), I5 => rgb888(20), O => \y_int[31]_i_44_n_0\ ); \y_int[31]_i_45\: unisim.vcomponents.LUT6 generic map( INIT => X"6CC9C9C9C9C9C9C9" ) port map ( I0 => \y_int_reg[3]_i_64_n_2\, I1 => rgb888(22), I2 => rgb888(21), I3 => rgb888(19), I4 => rgb888(18), I5 => rgb888(20), O => \y_int[31]_i_45_n_0\ ); \y_int[31]_i_46\: unisim.vcomponents.LUT6 generic map( INIT => X"157FEA807FEA8015" ) port map ( I0 => rgb888(23), I1 => rgb888(19), I2 => rgb888(18), I3 => rgb888(20), I4 => rgb888(21), I5 => \y_int_reg[3]_i_64_n_2\, O => \y_int[31]_i_46_n_0\ ); \y_int[31]_i_47\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996699669" ) port map ( I0 => \y_int[31]_i_43_n_0\, I1 => \y_int_reg[3]_i_64_n_2\, I2 => rgb888(23), I3 => rgb888(20), I4 => rgb888(19), I5 => rgb888(18), O => \y_int[31]_i_47_n_0\ ); \y_int[31]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[31]_i_5_n_0\ ); \y_int[31]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[31]_i_6_n_0\ ); \y_int[31]_i_63\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \rgb888[0]_7\(2), I1 => \y_int_reg[31]_i_75_n_7\, O => \y_int[31]_i_63_n_0\ ); \y_int[31]_i_64\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_87_n_4\, I1 => \rgb888[0]_7\(1), O => \y_int[31]_i_64_n_0\ ); \y_int[31]_i_65\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \y_int_reg[31]_i_87_n_4\, I1 => \rgb888[0]_7\(1), O => \y_int[31]_i_65_n_0\ ); \y_int[31]_i_66\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \y_int_reg[31]_i_86_n_4\, I1 => \y_int_reg[31]_i_87_n_6\, O => \y_int[31]_i_66_n_0\ ); \y_int[31]_i_67\: unisim.vcomponents.LUT4 generic map( INIT => X"7887" ) port map ( I0 => \y_int_reg[31]_i_75_n_7\, I1 => \rgb888[0]_7\(2), I2 => \y_int_reg[31]_i_75_n_2\, I3 => \rgb888[0]_7\(3), O => \y_int[31]_i_67_n_0\ ); \y_int[31]_i_68\: unisim.vcomponents.LUT4 generic map( INIT => X"E11E" ) port map ( I0 => \rgb888[0]_7\(1), I1 => \y_int_reg[31]_i_87_n_4\, I2 => \rgb888[0]_7\(2), I3 => \y_int_reg[31]_i_75_n_7\, O => \y_int[31]_i_68_n_0\ ); \y_int[31]_i_69\: unisim.vcomponents.LUT4 generic map( INIT => X"6999" ) port map ( I0 => \rgb888[0]_7\(1), I1 => \y_int_reg[31]_i_87_n_4\, I2 => \y_int_reg[31]_i_87_n_5\, I3 => \rgb888[0]_7\(0), O => \y_int[31]_i_69_n_0\ ); \y_int[31]_i_70\: unisim.vcomponents.LUT4 generic map( INIT => X"8778" ) port map ( I0 => \y_int_reg[31]_i_87_n_6\, I1 => \y_int_reg[31]_i_86_n_4\, I2 => \rgb888[0]_7\(0), I3 => \y_int_reg[31]_i_87_n_5\, O => \y_int[31]_i_70_n_0\ ); \y_int[31]_i_89\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \y_int_reg[31]_i_86_n_5\, I1 => \y_int_reg[31]_i_86_n_4\, I2 => \y_int_reg[31]_i_87_n_6\, O => \y_int[31]_i_89_n_0\ ); \y_int[31]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \y_int_reg[31]_i_86_n_5\, I1 => \y_int_reg[31]_i_87_n_7\, O => \y_int[31]_i_90_n_0\ ); \y_int[31]_i_91\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[31]_i_88_n_4\, I1 => \y_int_reg[31]_i_86_n_6\, O => \y_int[31]_i_91_n_0\ ); \y_int[31]_i_92\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[31]_i_88_n_5\, I1 => rgb888(0), O => \y_int[31]_i_92_n_0\ ); \y_int[3]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[7]_i_24_n_6\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[14]\(3), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_1\(0), O => \y_int[3]_i_10_n_0\ ); \y_int[3]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(2), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_30_n_4\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_44_n_6\, O => y_int_reg1(2) ); \y_int[3]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(1), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[3]_i_16_n_4\, I3 => y_int_reg6, I4 => y_int_reg5(9), O => y_int_reg20_in(1) ); \y_int[3]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[7]_i_24_n_7\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[14]\(2), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_0\(1), O => \y_int[3]_i_13_n_0\ ); \y_int[3]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(1), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_30_n_5\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_44_n_7\, O => y_int_reg1(1) ); \y_int[3]_i_17\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \rgb888[14]\(1), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[14]_0\(0), O => \y_int[3]_i_17_n_0\ ); \y_int[3]_i_18\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \y_int_reg[31]_i_30_n_6\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[3]_i_35_n_4\, O => \y_int[3]_i_18_n_0\ ); \y_int[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(2), I1 => \y_int[3]_i_10_n_0\, I2 => y_int_reg1(2), O => \y_int[3]_i_2_n_0\ ); \y_int[3]_i_22\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_5\, O => \y_int[3]_i_22_n_0\ ); \y_int[3]_i_23\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_6\, O => \y_int[3]_i_23_n_0\ ); \y_int[3]_i_24\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_7\, O => \y_int[3]_i_24_n_0\ ); \y_int[3]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_4\, O => \y_int[3]_i_25_n_0\ ); \y_int[3]_i_27\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => rgb888(18), I1 => \y_int_reg[3]_i_30_n_4\, I2 => rgb888(21), O => \y_int[3]_i_27_n_0\ ); \y_int[3]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \y_int_reg[3]_i_30_n_5\, I1 => rgb888(17), I2 => rgb888(20), O => \y_int[3]_i_28_n_0\ ); \y_int[3]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \y_int_reg[3]_i_30_n_5\, I1 => rgb888(17), I2 => rgb888(20), O => \y_int[3]_i_29_n_0\ ); \y_int[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(1), I1 => \y_int[3]_i_13_n_0\, I2 => y_int_reg1(1), O => \y_int[3]_i_3_n_0\ ); \y_int[3]_i_31\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \y_int[3]_i_27_n_0\, I1 => rgb888(22), I2 => rgb888(19), I3 => rgb888(18), I4 => \y_int_reg[3]_i_64_n_7\, O => \y_int[3]_i_31_n_0\ ); \y_int[3]_i_32\: unisim.vcomponents.LUT6 generic map( INIT => X"E81717E817E8E817" ) port map ( I0 => rgb888(20), I1 => rgb888(17), I2 => \y_int_reg[3]_i_30_n_5\, I3 => rgb888(21), I4 => rgb888(18), I5 => \y_int_reg[3]_i_30_n_4\, O => \y_int[3]_i_32_n_0\ ); \y_int[3]_i_33\: unisim.vcomponents.LUT5 generic map( INIT => X"69969696" ) port map ( I0 => rgb888(20), I1 => rgb888(17), I2 => \y_int_reg[3]_i_30_n_5\, I3 => rgb888(19), I4 => rgb888(16), O => \y_int[3]_i_33_n_0\ ); \y_int[3]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(16), I1 => rgb888(19), I2 => \y_int_reg[3]_i_30_n_6\, O => \y_int[3]_i_34_n_0\ ); \y_int[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFE2E200" ) port map ( I0 => y_int_reg5(8), I1 => y_int_reg6, I2 => \y_int_reg[3]_i_16_n_5\, I3 => \y_int[3]_i_17_n_0\, I4 => \y_int[3]_i_18_n_0\, O => \y_int[3]_i_4_n_0\ ); \y_int[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(3), I1 => \y_int[7]_i_19_n_0\, I2 => y_int_reg1(3), I3 => \y_int[3]_i_2_n_0\, O => \y_int[3]_i_5_n_0\ ); \y_int[3]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(16), O => \y_int[3]_i_50_n_0\ ); \y_int[3]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_5\, O => \y_int[3]_i_51_n_0\ ); \y_int[3]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_6\, O => \y_int[3]_i_52_n_0\ ); \y_int[3]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_7\, O => \y_int[3]_i_53_n_0\ ); \y_int[3]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(17), O => \y_int[3]_i_54_n_0\ ); \y_int[3]_i_56\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[3]_i_30_n_7\, I1 => rgb888(18), O => \y_int[3]_i_56_n_0\ ); \y_int[3]_i_57\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[3]_i_55_n_4\, I1 => rgb888(17), O => \y_int[3]_i_57_n_0\ ); \y_int[3]_i_58\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[3]_i_55_n_5\, I1 => rgb888(16), O => \y_int[3]_i_58_n_0\ ); \y_int[3]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg[3]_i_55_n_6\, O => \y_int[3]_i_59_n_0\ ); \y_int[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(2), I1 => \y_int[3]_i_10_n_0\, I2 => y_int_reg1(2), I3 => \y_int[3]_i_3_n_0\, O => \y_int[3]_i_6_n_0\ ); \y_int[3]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(22), O => \y_int[3]_i_60_n_0\ ); \y_int[3]_i_61\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(23), I1 => rgb888(21), O => \y_int[3]_i_61_n_0\ ); \y_int[3]_i_62\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(22), I1 => rgb888(20), O => \y_int[3]_i_62_n_0\ ); \y_int[3]_i_63\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(21), I1 => rgb888(19), O => \y_int[3]_i_63_n_0\ ); \y_int[3]_i_66\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_6\, O => \y_int[3]_i_66_n_0\ ); \y_int[3]_i_67\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_7\, O => \y_int[3]_i_67_n_0\ ); \y_int[3]_i_68\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_62_n_4\, O => \y_int[3]_i_68_n_0\ ); \y_int[3]_i_69\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_62_n_5\, O => \y_int[3]_i_69_n_0\ ); \y_int[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(1), I1 => \y_int[3]_i_13_n_0\, I2 => y_int_reg1(1), I3 => \y_int[3]_i_4_n_0\, O => \y_int[3]_i_7_n_0\ ); \y_int[3]_i_71\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_32\(1), I1 => rgb888(10), O => \y_int[3]_i_71_n_0\ ); \y_int[3]_i_72\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_32\(0), I1 => rgb888(9), O => \y_int[3]_i_72_n_0\ ); \y_int[3]_i_73\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_19\(2), I1 => rgb888(8), O => \y_int[3]_i_73_n_0\ ); \y_int[3]_i_74\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \rgb888[8]_19\(1), O => \y_int[3]_i_74_n_0\ ); \y_int[3]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"E21D1DE2" ) port map ( I0 => y_int_reg5(8), I1 => y_int_reg6, I2 => \y_int_reg[3]_i_16_n_5\, I3 => \y_int[3]_i_17_n_0\, I4 => \y_int[3]_i_18_n_0\, O => \y_int[3]_i_8_n_0\ ); \y_int[3]_i_84\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(20), I1 => rgb888(18), O => \y_int[3]_i_84_n_0\ ); \y_int[3]_i_85\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(19), I1 => rgb888(17), O => \y_int[3]_i_85_n_0\ ); \y_int[3]_i_86\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(18), I1 => rgb888(16), O => \y_int[3]_i_86_n_0\ ); \y_int[3]_i_87\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(17), O => \y_int[3]_i_87_n_0\ ); \y_int[3]_i_88\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(23), O => \y_int[3]_i_88_n_0\ ); \y_int[3]_i_89\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_62_n_6\, O => \y_int[3]_i_89_n_0\ ); \y_int[3]_i_9\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(2), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_16_n_7\, I3 => y_int_reg6, I4 => y_int_reg5(10), O => y_int_reg20_in(2) ); \y_int[3]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(0), I1 => \y_int_reg[31]_i_88_n_5\, O => \y_int[3]_i_90_n_0\ ); \y_int[3]_i_91\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_88_n_6\, O => \y_int[3]_i_91_n_0\ ); \y_int[3]_i_92\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), O => \y_int[3]_i_92_n_0\ ); \y_int[7]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(6), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_8_n_7\, I3 => y_int_reg6, I4 => y_int_reg5(14), O => y_int_reg20_in(6) ); \y_int[7]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[11]_i_38_n_6\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_20\(3), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[8]_22\(0), O => \y_int[7]_i_11_n_0\ ); \y_int[7]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(5), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_16_n_4\, I3 => y_int_reg6, I4 => y_int_reg5(13), O => y_int_reg20_in(5) ); \y_int[7]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[11]_i_38_n_7\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_20\(2), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_1\(3), O => \y_int[7]_i_13_n_0\ ); \y_int[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(5), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_11_n_5\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_21_n_7\, O => y_int_reg1(5) ); \y_int[7]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(4), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_16_n_5\, I3 => y_int_reg6, I4 => y_int_reg5(12), O => y_int_reg20_in(4) ); \y_int[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[7]_i_24_n_4\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_20\(1), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_1\(2), O => \y_int[7]_i_16_n_0\ ); \y_int[7]_i_17\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(4), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_11_n_6\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_44_n_4\, O => y_int_reg1(4) ); \y_int[7]_i_18\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(3), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_16_n_6\, I3 => y_int_reg6, I4 => y_int_reg5(11), O => y_int_reg20_in(3) ); \y_int[7]_i_19\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[7]_i_24_n_5\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_20\(0), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_1\(1), O => \y_int[7]_i_19_n_0\ ); \y_int[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"E888E888E8EEE888" ) port map ( I0 => y_int_reg20_in(6), I1 => \y_int[7]_i_11_n_0\, I2 => y_int_reg2(6), I3 => \^y_int_reg[23]_0\(0), I4 => \y_int_reg[11]_i_21_n_6\, I5 => \^y_int_reg[7]_0\(0), O => \y_int[7]_i_2_n_0\ ); \y_int[7]_i_20\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(3), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_11_n_7\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_44_n_5\, O => y_int_reg1(3) ); \y_int[7]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg2(7), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[11]_i_21_n_5\, I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(7) ); \y_int[7]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg2(6), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[11]_i_21_n_6\, I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(6) ); \y_int[7]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_0\(0), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[14]\(1), O => \y_int[7]_i_29_n_0\ ); \y_int[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(5), I1 => \y_int[7]_i_13_n_0\, I2 => y_int_reg1(5), O => \y_int[7]_i_3_n_0\ ); \y_int[7]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_1\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_20\(1), O => \y_int[7]_i_30_n_0\ ); \y_int[7]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_1\(1), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_20\(0), O => \y_int[7]_i_31_n_0\ ); \y_int[7]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_1\(0), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[14]\(3), O => \y_int[7]_i_32_n_0\ ); \y_int[7]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_0\(1), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[14]\(2), O => \y_int[7]_i_33_n_0\ ); \y_int[7]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(4), I1 => \y_int[7]_i_16_n_0\, I2 => y_int_reg1(4), O => \y_int[7]_i_4_n_0\ ); \y_int[7]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(3), I1 => \y_int[7]_i_19_n_0\, I2 => y_int_reg1(3), O => \y_int[7]_i_5_n_0\ ); \y_int[7]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[7]_i_2_n_0\, I1 => y_int_reg1(7), I2 => \y_int[11]_i_19_n_0\, I3 => y_int_reg20_in(7), O => \y_int[7]_i_6_n_0\ ); \y_int[7]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[7]_i_3_n_0\, I1 => y_int_reg1(6), I2 => \y_int[7]_i_11_n_0\, I3 => y_int_reg20_in(6), O => \y_int[7]_i_7_n_0\ ); \y_int[7]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(5), I1 => \y_int[7]_i_13_n_0\, I2 => y_int_reg1(5), I3 => \y_int[7]_i_4_n_0\, O => \y_int[7]_i_8_n_0\ ); \y_int[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(4), I1 => \y_int[7]_i_16_n_0\, I2 => y_int_reg1(4), I3 => \y_int[7]_i_5_n_0\, O => \y_int[7]_i_9_n_0\ ); \y_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[3]_i_1_n_7\, Q => \y_int_reg_n_0_[0]\, R => '0' ); \y_int_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[11]_i_1_n_5\, Q => \y_int_reg__0\(10), R => '0' ); \y_int_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[11]_i_1_n_4\, Q => \y_int_reg__0\(11), R => '0' ); \y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[7]_i_1_n_0\, CO(3) => \y_int_reg[11]_i_1_n_0\, CO(2) => \y_int_reg[11]_i_1_n_1\, CO(1) => \y_int_reg[11]_i_1_n_2\, CO(0) => \y_int_reg[11]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[11]_i_2_n_0\, DI(2) => \y_int[11]_i_3_n_0\, DI(1) => \y_int[11]_i_4_n_0\, DI(0) => \y_int[11]_i_5_n_0\, O(3) => \y_int_reg[11]_i_1_n_4\, O(2) => \y_int_reg[11]_i_1_n_5\, O(1) => \y_int_reg[11]_i_1_n_6\, O(0) => \y_int_reg[11]_i_1_n_7\, S(3) => \y_int[11]_i_6_n_0\, S(2) => \y_int[11]_i_7_n_0\, S(1) => \y_int[11]_i_8_n_0\, S(0) => \y_int[11]_i_9_n_0\ ); \y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_28_n_0\, CO(3) => \y_int_reg[11]_i_14_n_0\, CO(2) => \y_int_reg[11]_i_14_n_1\, CO(1) => \y_int_reg[11]_i_14_n_2\, CO(0) => \y_int_reg[11]_i_14_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(16 downto 13), S(3) => \y_int[11]_i_29_n_0\, S(2) => \y_int[11]_i_30_n_0\, S(1) => \y_int[11]_i_31_n_0\, S(0) => \y_int[11]_i_32_n_0\ ); \y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_33_n_0\, CO(3) => \y_int_reg[11]_i_15_n_0\, CO(2) => \y_int_reg[11]_i_15_n_1\, CO(1) => \y_int_reg[11]_i_15_n_2\, CO(0) => \y_int_reg[11]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(8 downto 5), S(3) => \y_int[11]_i_34_n_0\, S(2) => \y_int[11]_i_35_n_0\, S(1) => \y_int[11]_i_36_n_0\, S(0) => \y_int[11]_i_37_n_0\ ); \y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_39_n_0\, CO(3) => \y_int_reg[15]_1\(0), CO(2) => \y_int_reg[11]_i_20_n_1\, CO(1) => \y_int_reg[11]_i_20_n_2\, CO(0) => \y_int_reg[11]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(8 downto 5), S(3) => \y_int[11]_i_40_n_0\, S(2) => \y_int[11]_i_41_n_0\, S(1) => \y_int[11]_i_42_n_0\, S(0) => \y_int[11]_i_43_n_0\ ); \y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_44_n_0\, CO(3) => \y_int_reg[11]_i_21_n_0\, CO(2) => \y_int_reg[11]_i_21_n_1\, CO(1) => \y_int_reg[11]_i_21_n_2\, CO(0) => \y_int_reg[11]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[11]_i_21_n_4\, O(2) => \y_int_reg[11]_i_21_n_5\, O(1) => \y_int_reg[11]_i_21_n_6\, O(0) => \y_int_reg[11]_i_21_n_7\, S(3) => \y_int[11]_i_45_n_0\, S(2) => \y_int[11]_i_46_n_0\, S(1) => \y_int[11]_i_47_n_0\, S(0) => \y_int[11]_i_48_n_0\ ); \y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_49_n_0\, CO(3) => \^y_int_reg[7]_0\(0), CO(2) => \y_int_reg[11]_i_22_n_1\, CO(1) => \y_int_reg[11]_i_22_n_2\, CO(0) => \y_int_reg[11]_i_22_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \^y_int_reg[23]_0\(0), DI(1) => \^y_int_reg[23]_0\(0), DI(0) => \^y_int_reg[23]_0\(0), O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[11]_i_50_n_0\, S(2) => \y_int[11]_i_51_n_0\, S(1) => \y_int[11]_i_52_n_0\, S(0) => \y_int[11]_i_53_n_0\ ); \y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_15_n_0\, CO(3) => \y_int_reg[11]_i_28_n_0\, CO(2) => \y_int_reg[11]_i_28_n_1\, CO(1) => \y_int_reg[11]_i_28_n_2\, CO(0) => \y_int_reg[11]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(12 downto 9), S(3) => \y_int[11]_i_58_n_0\, S(2) => \y_int[11]_i_59_n_0\, S(1) => \y_int[11]_i_60_n_0\, S(0) => \y_int[11]_i_61_n_0\ ); \y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[11]_i_33_n_0\, CO(2) => \y_int_reg[11]_i_33_n_1\, CO(1) => \y_int_reg[11]_i_33_n_2\, CO(0) => \y_int_reg[11]_i_33_n_3\, CYINIT => \y_int[11]_i_62_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(4 downto 1), S(3) => \y_int[11]_i_63_n_0\, S(2) => \y_int[11]_i_64_n_0\, S(1) => \y_int[11]_i_65_n_0\, S(0) => \y_int[11]_i_66_n_0\ ); \y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[7]_i_24_n_0\, CO(3) => \y_int_reg[11]_i_38_n_0\, CO(2) => \y_int_reg[11]_i_38_n_1\, CO(1) => \y_int_reg[11]_i_38_n_2\, CO(0) => \y_int_reg[11]_i_38_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[11]_i_38_n_4\, O(2) => \y_int_reg[11]_i_38_n_5\, O(1) => \y_int_reg[11]_i_38_n_6\, O(0) => \y_int_reg[11]_i_38_n_7\, S(3) => \y_int[11]_i_67_n_0\, S(2) => \y_int[11]_i_68_n_0\, S(1) => \y_int[11]_i_69_n_0\, S(0) => \y_int[11]_i_70_n_0\ ); \y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[11]_i_39_n_0\, CO(2) => \y_int_reg[11]_i_39_n_1\, CO(1) => \y_int_reg[11]_i_39_n_2\, CO(0) => \y_int_reg[11]_i_39_n_3\, CYINIT => \y_int[11]_i_71_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(4 downto 1), S(3) => \y_int[11]_i_72_n_0\, S(2) => \y_int[11]_i_73_n_0\, S(1) => \y_int[11]_i_74_n_0\, S(0) => \y_int[11]_i_75_n_0\ ); \y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_35_n_0\, CO(3) => \y_int_reg[11]_i_44_n_0\, CO(2) => \y_int_reg[11]_i_44_n_1\, CO(1) => \y_int_reg[11]_i_44_n_2\, CO(0) => \y_int_reg[11]_i_44_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[11]_i_44_n_4\, O(2) => \y_int_reg[11]_i_44_n_5\, O(1) => \y_int_reg[11]_i_44_n_6\, O(0) => \y_int_reg[11]_i_44_n_7\, S(3) => \y_int[11]_i_76_n_0\, S(2) => \y_int[11]_i_77_n_0\, S(1) => \y_int[11]_i_78_n_0\, S(0) => \y_int[11]_i_79_n_0\ ); \y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_80_n_0\, CO(3) => \y_int_reg[11]_i_49_n_0\, CO(2) => \y_int_reg[11]_i_49_n_1\, CO(1) => \y_int_reg[11]_i_49_n_2\, CO(0) => \y_int_reg[11]_i_49_n_3\, CYINIT => '0', DI(3) => \^y_int_reg[23]_0\(0), DI(2) => \^y_int_reg[23]_0\(0), DI(1) => \^y_int_reg[23]_0\(0), DI(0) => \^y_int_reg[23]_0\(0), O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[11]_i_81_n_0\, S(2) => \y_int[11]_i_82_n_0\, S(1) => \y_int[11]_i_83_n_0\, S(0) => \y_int[11]_i_84_n_0\ ); \y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_85_n_0\, CO(3) => \y_int_reg[11]_i_80_n_0\, CO(2) => \y_int_reg[11]_i_80_n_1\, CO(1) => \y_int_reg[11]_i_80_n_2\, CO(0) => \y_int_reg[11]_i_80_n_3\, CYINIT => '0', DI(3) => \^y_int_reg[23]_0\(0), DI(2) => \y_int[11]_i_86_n_0\, DI(1) => \y_int[11]_i_87_n_0\, DI(0) => \y_int[11]_i_88_n_0\, O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[11]_i_89_n_0\, S(2) => \y_int[11]_i_90_n_0\, S(1) => \y_int[11]_i_91_n_0\, S(0) => \y_int[11]_i_92_n_0\ ); \y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[11]_i_85_n_0\, CO(2) => \y_int_reg[11]_i_85_n_1\, CO(1) => \y_int_reg[11]_i_85_n_2\, CO(0) => \y_int_reg[11]_i_85_n_3\, CYINIT => '1', DI(3) => \y_int[11]_i_93_n_0\, DI(2) => \y_int[11]_i_94_n_0\, DI(1) => \y_int[11]_i_95_n_0\, DI(0) => \y_int[11]_i_96_n_0\, O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[11]_i_97_n_0\, S(2) => \y_int[11]_i_98_n_0\, S(1) => \y_int[11]_i_99_n_0\, S(0) => \y_int[11]_i_100_n_0\ ); \y_int_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[15]_i_1_n_7\, Q => \y_int_reg__0\(12), R => '0' ); \y_int_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[15]_i_1_n_6\, Q => \y_int_reg__0\(13), R => '0' ); \y_int_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[15]_i_1_n_5\, Q => \y_int_reg__0\(14), R => '0' ); \y_int_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[15]_i_1_n_4\, Q => \y_int_reg__0\(15), R => '0' ); \y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_1_n_0\, CO(3) => \y_int_reg[15]_i_1_n_0\, CO(2) => \y_int_reg[15]_i_1_n_1\, CO(1) => \y_int_reg[15]_i_1_n_2\, CO(0) => \y_int_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[15]_i_2_n_0\, DI(2) => \y_int[15]_i_3_n_0\, DI(1) => \y_int[15]_i_4_n_0\, DI(0) => \y_int[15]_i_5_n_0\, O(3) => \y_int_reg[15]_i_1_n_4\, O(2) => \y_int_reg[15]_i_1_n_5\, O(1) => \y_int_reg[15]_i_1_n_6\, O(0) => \y_int_reg[15]_i_1_n_7\, S(3) => \y_int[15]_i_6_n_0\, S(2) => \y_int[15]_i_7_n_0\, S(1) => \y_int[15]_i_8_n_0\, S(0) => \y_int[15]_i_9_n_0\ ); \y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_14_n_0\, CO(3) => \y_int_reg[15]_i_14_n_0\, CO(2) => \y_int_reg[15]_i_14_n_1\, CO(1) => \y_int_reg[15]_i_14_n_2\, CO(0) => \y_int_reg[15]_i_14_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(20 downto 17), S(3) => \y_int[15]_i_25_n_0\, S(2) => \y_int[15]_i_26_n_0\, S(1) => \y_int[15]_i_27_n_0\, S(0) => \y_int[15]_i_28_n_0\ ); \y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_15_n_0\, CO(3) => \y_int_reg[15]_i_15_n_0\, CO(2) => \y_int_reg[15]_i_15_n_1\, CO(1) => \y_int_reg[15]_i_15_n_2\, CO(0) => \y_int_reg[15]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(12 downto 9), S(3) => \y_int[15]_i_29_n_0\, S(2) => \y_int[15]_i_30_n_0\, S(1) => \y_int[15]_i_31_n_0\, S(0) => \y_int[15]_i_32_n_0\ ); \y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_38_n_0\, CO(3) => \y_int_reg[19]_1\(0), CO(2) => \y_int_reg[15]_i_33_n_1\, CO(1) => \y_int_reg[15]_i_33_n_2\, CO(0) => \y_int_reg[15]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[15]_i_33_n_4\, O(2) => \y_int_reg[15]_i_33_n_5\, O(1) => \y_int_reg[15]_i_33_n_6\, O(0) => \y_int_reg[15]_i_33_n_7\, S(3) => \y_int[15]_i_40_n_0\, S(2) => \y_int[15]_i_41_n_0\, S(1) => \y_int[15]_i_42_n_0\, S(0) => \y_int[15]_i_43_n_0\ ); \y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_21_n_0\, CO(3) => \y_int_reg[15]_i_35_n_0\, CO(2) => \y_int_reg[15]_i_35_n_1\, CO(1) => \y_int_reg[15]_i_35_n_2\, CO(0) => \y_int_reg[15]_i_35_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0), S(3) => \y_int[15]_i_48_n_0\, S(2) => \y_int[15]_i_49_n_0\, S(1) => \y_int[15]_i_50_n_0\, S(0) => \y_int[15]_i_51_n_0\ ); \y_int_reg[16]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[19]_i_1_n_7\, Q => \y_int_reg__0\(16), R => '0' ); \y_int_reg[17]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[19]_i_1_n_6\, Q => \y_int_reg__0\(17), R => '0' ); \y_int_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[19]_i_1_n_5\, Q => \y_int_reg__0\(18), R => '0' ); \y_int_reg[19]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[19]_i_1_n_4\, Q => \y_int_reg__0\(19), R => '0' ); \y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_1_n_0\, CO(3) => \y_int_reg[19]_i_1_n_0\, CO(2) => \y_int_reg[19]_i_1_n_1\, CO(1) => \y_int_reg[19]_i_1_n_2\, CO(0) => \y_int_reg[19]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[19]_i_2_n_0\, DI(2) => \y_int[19]_i_3_n_0\, DI(1) => \y_int[19]_i_4_n_0\, DI(0) => \y_int[19]_i_5_n_0\, O(3) => \y_int_reg[19]_i_1_n_4\, O(2) => \y_int_reg[19]_i_1_n_5\, O(1) => \y_int_reg[19]_i_1_n_6\, O(0) => \y_int_reg[19]_i_1_n_7\, S(3) => \y_int[19]_i_6_n_0\, S(2) => \y_int[19]_i_7_n_0\, S(1) => \y_int[19]_i_8_n_0\, S(0) => \y_int[19]_i_9_n_0\ ); \y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_14_n_0\, CO(3) => \y_int_reg[19]_i_14_n_0\, CO(2) => \y_int_reg[19]_i_14_n_1\, CO(1) => \y_int_reg[19]_i_14_n_2\, CO(0) => \y_int_reg[19]_i_14_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(24 downto 21), S(3) => \y_int[19]_i_25_n_0\, S(2) => \y_int[19]_i_26_n_0\, S(1) => \y_int[19]_i_27_n_0\, S(0) => \y_int[19]_i_28_n_0\ ); \y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_15_n_0\, CO(3) => \y_int_reg[19]_i_15_n_0\, CO(2) => \y_int_reg[19]_i_15_n_1\, CO(1) => \y_int_reg[19]_i_15_n_2\, CO(0) => \y_int_reg[19]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(16 downto 13), S(3) => \y_int[19]_i_29_n_0\, S(2) => \y_int[19]_i_30_n_0\, S(1) => \y_int[19]_i_31_n_0\, S(0) => \y_int[19]_i_32_n_0\ ); \y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_35_n_0\, CO(3) => \y_int_reg[19]_i_35_n_0\, CO(2) => \y_int_reg[19]_i_35_n_1\, CO(1) => \y_int_reg[19]_i_35_n_2\, CO(0) => \y_int_reg[19]_i_35_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0), S(3) => \y_int[19]_i_48_n_0\, S(2) => \y_int[19]_i_49_n_0\, S(1) => \y_int[19]_i_50_n_0\, S(0) => \y_int[19]_i_51_n_0\ ); \y_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[3]_i_1_n_6\, Q => \y_int_reg_n_0_[1]\, R => '0' ); \y_int_reg[20]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[23]_i_1_n_7\, Q => \y_int_reg__0\(20), R => '0' ); \y_int_reg[21]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[23]_i_1_n_6\, Q => \y_int_reg__0\(21), R => '0' ); \y_int_reg[22]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[23]_i_1_n_5\, Q => \y_int_reg__0\(22), R => '0' ); \y_int_reg[23]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[23]_i_1_n_4\, Q => \y_int_reg__0\(23), R => '0' ); \y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_1_n_0\, CO(3) => \y_int_reg[23]_i_1_n_0\, CO(2) => \y_int_reg[23]_i_1_n_1\, CO(1) => \y_int_reg[23]_i_1_n_2\, CO(0) => \y_int_reg[23]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[23]_i_2_n_0\, DI(2) => \y_int[23]_i_3_n_0\, DI(1) => \y_int[23]_i_4_n_0\, DI(0) => \y_int[23]_i_5_n_0\, O(3) => \y_int_reg[23]_i_1_n_4\, O(2) => \y_int_reg[23]_i_1_n_5\, O(1) => \y_int_reg[23]_i_1_n_6\, O(0) => \y_int_reg[23]_i_1_n_7\, S(3) => \y_int[23]_i_6_n_0\, S(2) => \y_int[23]_i_7_n_0\, S(1) => \y_int[23]_i_8_n_0\, S(0) => \y_int[23]_i_9_n_0\ ); \y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_25_n_0\, CO(3) => y_int_reg6, CO(2) => \y_int_reg[23]_i_10_n_1\, CO(1) => \y_int_reg[23]_i_10_n_2\, CO(0) => \y_int_reg[23]_i_10_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \y_int_reg[31]_i_8_n_5\, DI(1) => \y_int_reg[31]_i_8_n_5\, DI(0) => \y_int_reg[31]_i_8_n_5\, O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_26_n_0\, S(2) => \y_int[23]_i_27_n_0\, S(1) => \y_int[23]_i_28_n_0\, S(0) => \y_int[23]_i_29_n_0\ ); \y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_16_n_0\, CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1), CO(0) => \y_int_reg[23]_i_11_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => y_int_reg5(30 downto 29), S(3 downto 2) => B"00", S(1) => \y_int[23]_i_30_n_0\, S(0) => \y_int[23]_i_31_n_0\ ); \y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_14_n_0\, CO(3) => \y_int_reg[23]_i_16_n_0\, CO(2) => \y_int_reg[23]_i_16_n_1\, CO(1) => \y_int_reg[23]_i_16_n_2\, CO(0) => \y_int_reg[23]_i_16_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(28 downto 25), S(3) => \y_int[23]_i_36_n_0\, S(2) => \y_int[23]_i_37_n_0\, S(1) => \y_int[23]_i_38_n_0\, S(0) => \y_int[23]_i_39_n_0\ ); \y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_15_n_0\, CO(3) => \y_int_reg[23]_i_17_n_0\, CO(2) => \y_int_reg[23]_i_17_n_1\, CO(1) => \y_int_reg[23]_i_17_n_2\, CO(0) => \y_int_reg[23]_i_17_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(20 downto 17), S(3) => \y_int[23]_i_40_n_0\, S(2) => \y_int[23]_i_41_n_0\, S(1) => \y_int[23]_i_42_n_0\, S(0) => \y_int[23]_i_43_n_0\ ); \y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_45_n_0\, CO(3) => \y_int_reg[23]_i_25_n_0\, CO(2) => \y_int_reg[23]_i_25_n_1\, CO(1) => \y_int_reg[23]_i_25_n_2\, CO(0) => \y_int_reg[23]_i_25_n_3\, CYINIT => '0', DI(3) => \y_int_reg[31]_i_8_n_5\, DI(2) => \y_int_reg[31]_i_8_n_5\, DI(1) => \y_int_reg[31]_i_8_n_5\, DI(0) => \y_int_reg[31]_i_8_n_5\, O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_46_n_0\, S(2) => \y_int[23]_i_47_n_0\, S(1) => \y_int[23]_i_48_n_0\, S(0) => \y_int[23]_i_49_n_0\ ); \y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_51_n_0\, CO(3) => \^y_int_reg[3]_1\(0), CO(2) => \y_int_reg[23]_i_33_n_1\, CO(1) => \y_int_reg[23]_i_33_n_2\, CO(0) => \y_int_reg[23]_i_33_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \rgb888[8]_21\(2), DI(1) => \rgb888[8]_21\(2), DI(0) => \rgb888[8]_21\(2), O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_52_n_0\, S(2) => \y_int[23]_i_53_n_0\, S(1) => \y_int[23]_i_54_n_0\, S(0) => \y_int[23]_i_55_n_0\ ); \y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_44_n_0\, CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1), CO(0) => \y_int_reg[23]_i_34_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0), S(3 downto 2) => B"00", S(1) => \y_int[23]_i_56_n_0\, S(0) => \y_int[23]_i_57_n_0\ ); \y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_35_n_0\, CO(3) => \y_int_reg[23]_i_44_n_0\, CO(2) => \y_int_reg[23]_i_44_n_1\, CO(1) => \y_int_reg[23]_i_44_n_2\, CO(0) => \y_int_reg[23]_i_44_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0), S(3) => \y_int[23]_i_62_n_0\, S(2) => \y_int[23]_i_63_n_0\, S(1) => \y_int[23]_i_64_n_0\, S(0) => \y_int[23]_i_65_n_0\ ); \y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_66_n_0\, CO(3) => \y_int_reg[23]_i_45_n_0\, CO(2) => \y_int_reg[23]_i_45_n_1\, CO(1) => \y_int_reg[23]_i_45_n_2\, CO(0) => \y_int_reg[23]_i_45_n_3\, CYINIT => '0', DI(3) => \y_int[23]_i_67_n_0\, DI(2) => \y_int[23]_i_68_n_0\, DI(1) => \y_int[23]_i_69_n_0\, DI(0) => \y_int[23]_i_70_n_0\, O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_71_n_0\, S(2) => \y_int[23]_i_72_n_0\, S(1) => \y_int[23]_i_73_n_0\, S(0) => \y_int[23]_i_74_n_0\ ); \y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_75_n_0\, CO(3) => \y_int_reg[23]_i_51_n_0\, CO(2) => \y_int_reg[23]_i_51_n_1\, CO(1) => \y_int_reg[23]_i_51_n_2\, CO(0) => \y_int_reg[23]_i_51_n_3\, CYINIT => '0', DI(3) => \rgb888[8]_21\(2), DI(2) => \rgb888[8]_21\(2), DI(1) => \rgb888[8]_21\(2), DI(0) => \y_int[23]_i_76_n_0\, O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_77_n_0\, S(2) => \y_int[23]_i_78_n_0\, S(1) => \y_int[23]_i_79_n_0\, S(0) => \y_int[23]_i_80_n_0\ ); \y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[23]_i_66_n_0\, CO(2) => \y_int_reg[23]_i_66_n_1\, CO(1) => \y_int_reg[23]_i_66_n_2\, CO(0) => \y_int_reg[23]_i_66_n_3\, CYINIT => '1', DI(3) => \y_int[23]_i_81_n_0\, DI(2) => \y_int[23]_i_82_n_0\, DI(1) => \y_int[23]_i_83_n_0\, DI(0) => \y_int[23]_i_84_n_0\, O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_85_n_0\, S(2) => \y_int[23]_i_86_n_0\, S(1) => \y_int[23]_i_87_n_0\, S(0) => \y_int[23]_i_88_n_0\ ); \y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_89_n_0\, CO(3) => \y_int_reg[23]_i_75_n_0\, CO(2) => \y_int_reg[23]_i_75_n_1\, CO(1) => \y_int_reg[23]_i_75_n_2\, CO(0) => \y_int_reg[23]_i_75_n_3\, CYINIT => '0', DI(3) => \y_int[23]_i_90_n_0\, DI(2) => \y_int[23]_i_91_n_0\, DI(1) => \y_int[23]_i_92_n_0\, DI(0) => \y_int[23]_i_93_n_0\, O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_94_n_0\, S(2) => \y_int[23]_i_95_n_0\, S(1) => \y_int[23]_i_96_n_0\, S(0) => \y_int[23]_i_97_n_0\ ); \y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[23]_i_89_n_0\, CO(2) => \y_int_reg[23]_i_89_n_1\, CO(1) => \y_int_reg[23]_i_89_n_2\, CO(0) => \y_int_reg[23]_i_89_n_3\, CYINIT => '1', DI(3) => \y_int[23]_i_98_n_0\, DI(2) => \y_int[23]_i_99_n_0\, DI(1) => \y_int[23]_i_100_n_0\, DI(0) => rgb888(8), O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_101_n_0\, S(2) => \y_int[23]_i_102_n_0\, S(1) => \y_int[23]_i_103_n_0\, S(0) => \y_int[23]_i_104_n_0\ ); \y_int_reg[24]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[27]_i_1_n_7\, Q => \y_int_reg__0\(24), R => '0' ); \y_int_reg[25]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[27]_i_1_n_6\, Q => \y_int_reg__0\(25), R => '0' ); \y_int_reg[26]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[27]_i_1_n_5\, Q => \y_int_reg__0\(26), R => '0' ); \y_int_reg[27]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[27]_i_1_n_4\, Q => \y_int_reg__0\(27), R => '0' ); \y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_1_n_0\, CO(3) => \y_int_reg[27]_i_1_n_0\, CO(2) => \y_int_reg[27]_i_1_n_1\, CO(1) => \y_int_reg[27]_i_1_n_2\, CO(0) => \y_int_reg[27]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_2_n_0\, DI(2) => \y_int[31]_i_2_n_0\, DI(1) => \y_int[31]_i_2_n_0\, DI(0) => \y_int[31]_i_2_n_0\, O(3) => \y_int_reg[27]_i_1_n_4\, O(2) => \y_int_reg[27]_i_1_n_5\, O(1) => \y_int_reg[27]_i_1_n_6\, O(0) => \y_int_reg[27]_i_1_n_7\, S(3) => \y_int[27]_i_2_n_0\, S(2) => \y_int[27]_i_3_n_0\, S(1) => \y_int[27]_i_4_n_0\, S(0) => \y_int[27]_i_5_n_0\ ); \y_int_reg[28]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[31]_i_1_n_7\, Q => \y_int_reg__0\(28), R => '0' ); \y_int_reg[29]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[31]_i_1_n_6\, Q => \y_int_reg__0\(29), R => '0' ); \y_int_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[3]_i_1_n_5\, Q => \y_int_reg_n_0_[2]\, R => '0' ); \y_int_reg[30]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[31]_i_1_n_5\, Q => \y_int_reg__0\(30), R => '0' ); \y_int_reg[31]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[31]_i_1_n_4\, Q => \y_int_reg__0\(31), R => '0' ); \y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[27]_i_1_n_0\, CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_1_n_1\, CO(1) => \y_int_reg[31]_i_1_n_2\, CO(0) => \y_int_reg[31]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \y_int[31]_i_2_n_0\, DI(1) => \y_int[31]_i_2_n_0\, DI(0) => \y_int[31]_i_2_n_0\, O(3) => \y_int_reg[31]_i_1_n_4\, O(2) => \y_int_reg[31]_i_1_n_5\, O(1) => \y_int_reg[31]_i_1_n_6\, O(0) => \y_int_reg[31]_i_1_n_7\, S(3) => \y_int[31]_i_3_n_0\, S(2) => \y_int[31]_i_4_n_0\, S(1) => \y_int[31]_i_5_n_0\, S(0) => \y_int[31]_i_6_n_0\ ); \y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_30_n_0\, CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_11_n_1\, CO(1) => \y_int_reg[31]_i_11_n_2\, CO(0) => \y_int_reg[31]_i_11_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \rgb888[0]_9\(1), DI(0) => \y_int[31]_i_32_n_0\, O(3) => \^y_int_reg[23]_0\(0), O(2) => \y_int_reg[31]_i_11_n_5\, O(1) => \y_int_reg[31]_i_11_n_6\, O(0) => \y_int_reg[31]_i_11_n_7\, S(3) => \y_int[31]_i_33_n_0\, S(2) => \y_int[31]_i_34_n_0\, S(1) => \y_int[31]_i_35_n_0\, S(0) => \y_int[31]_i_36_n_0\ ); \y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_16_n_0\, CO(3) => \y_int_reg[31]_i_16_n_0\, CO(2) => \y_int_reg[31]_i_16_n_1\, CO(1) => \y_int_reg[31]_i_16_n_2\, CO(0) => \y_int_reg[31]_i_16_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_40_n_0\, DI(2) => \y_int[31]_i_41_n_0\, DI(1) => \y_int[31]_i_42_n_0\, DI(0) => \y_int[31]_i_43_n_0\, O(3) => \y_int_reg[31]_i_16_n_4\, O(2) => \y_int_reg[31]_i_16_n_5\, O(1) => \y_int_reg[31]_i_16_n_6\, O(0) => \y_int_reg[31]_i_16_n_7\, S(3) => \y_int[31]_i_44_n_0\, S(2) => \y_int[31]_i_45_n_0\, S(1) => \y_int[31]_i_46_n_0\, S(0) => \y_int[31]_i_47_n_0\ ); \y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_62_n_0\, CO(3) => \y_int_reg[31]_i_30_n_0\, CO(2) => \y_int_reg[31]_i_30_n_1\, CO(1) => \y_int_reg[31]_i_30_n_2\, CO(0) => \y_int_reg[31]_i_30_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_63_n_0\, DI(2) => \y_int[31]_i_64_n_0\, DI(1) => \y_int[31]_i_65_n_0\, DI(0) => \y_int[31]_i_66_n_0\, O(3) => \y_int_reg[31]_i_30_n_4\, O(2) => \y_int_reg[31]_i_30_n_5\, O(1) => \y_int_reg[31]_i_30_n_6\, O(0) => \y_int_reg[31]_i_30_n_7\, S(3) => \y_int[31]_i_67_n_0\, S(2) => \y_int[31]_i_68_n_0\, S(1) => \y_int[31]_i_69_n_0\, S(0) => \y_int[31]_i_70_n_0\ ); \y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[31]_i_62_n_0\, CO(2) => \y_int_reg[31]_i_62_n_1\, CO(1) => \y_int_reg[31]_i_62_n_2\, CO(0) => \y_int_reg[31]_i_62_n_3\, CYINIT => '0', DI(3) => \y_int_reg[31]_i_86_n_5\, DI(2) => \y_int_reg[31]_i_87_n_7\, DI(1) => \y_int_reg[31]_i_88_n_4\, DI(0) => \y_int_reg[31]_i_88_n_5\, O(3) => \y_int_reg[31]_i_62_n_4\, O(2) => \y_int_reg[31]_i_62_n_5\, O(1) => \y_int_reg[31]_i_62_n_6\, O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0), S(3) => \y_int[31]_i_89_n_0\, S(2) => \y_int[31]_i_90_n_0\, S(1) => \y_int[31]_i_91_n_0\, S(0) => \y_int[31]_i_92_n_0\ ); \y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_17_n_0\, CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_7_n_1\, CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1), CO(0) => \y_int_reg[31]_i_7_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => y_int_reg3(22 downto 21), S(3 downto 2) => B"01", S(1) => \y_int[31]_i_14_n_0\, S(0) => \y_int[31]_i_15_n_0\ ); \y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_87_n_0\, CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[31]_i_75_n_2\, CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(7), O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1), O(0) => \y_int_reg[31]_i_75_n_7\, S(3 downto 1) => B"001", S(0) => \y_int[31]_i_101_n_0\ ); \y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_16_n_0\, CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[31]_i_8_n_2\, CO(0) => \y_int_reg[31]_i_8_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \y_int[31]_i_17_n_0\, O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3), O(2) => \y_int_reg[31]_i_8_n_5\, O(1) => \y_int_reg[31]_i_8_n_6\, O(0) => \y_int_reg[31]_i_8_n_7\, S(3) => '0', S(2) => \y_int[31]_i_18_n_0\, S(1) => \y_int[31]_i_19_n_0\, S(0) => \y_int[31]_i_20_n_0\ ); \y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[23]_3\(0), CO(2) => \y_int_reg[31]_i_86_n_1\, CO(1) => \y_int_reg[31]_i_86_n_2\, CO(0) => \y_int_reg[31]_i_86_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_104_n_0\, DI(2) => rgb888(2), DI(1 downto 0) => B"01", O(3) => \y_int_reg[31]_i_86_n_4\, O(2) => \y_int_reg[31]_i_86_n_5\, O(1) => \y_int_reg[31]_i_86_n_6\, O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0), S(3) => \y_int[31]_i_105_n_0\, S(2) => \y_int[31]_i_106_n_0\, S(1) => \y_int[31]_i_107_n_0\, S(0) => \y_int[31]_i_108_n_0\ ); \y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_88_n_0\, CO(3) => \y_int_reg[31]_i_87_n_0\, CO(2) => \y_int_reg[31]_i_87_n_1\, CO(1) => \y_int_reg[31]_i_87_n_2\, CO(0) => \y_int_reg[31]_i_87_n_3\, CYINIT => '0', DI(3) => rgb888(6), DI(2 downto 0) => rgb888(7 downto 5), O(3) => \y_int_reg[31]_i_87_n_4\, O(2) => \y_int_reg[31]_i_87_n_5\, O(1) => \y_int_reg[31]_i_87_n_6\, O(0) => \y_int_reg[31]_i_87_n_7\, S(3) => \y_int[31]_i_109_n_0\, S(2) => \y_int[31]_i_110_n_0\, S(1) => \y_int[31]_i_111_n_0\, S(0) => \y_int[31]_i_112_n_0\ ); \y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[31]_i_88_n_0\, CO(2) => \y_int_reg[31]_i_88_n_1\, CO(1) => \y_int_reg[31]_i_88_n_2\, CO(0) => \y_int_reg[31]_i_88_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(4 downto 2), DI(0) => '0', O(3) => \y_int_reg[31]_i_88_n_4\, O(2) => \y_int_reg[31]_i_88_n_5\, O(1) => \y_int_reg[31]_i_88_n_6\, O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0), S(3) => \y_int[31]_i_113_n_0\, S(2) => \y_int[31]_i_114_n_0\, S(1) => \y_int[31]_i_115_n_0\, S(0) => \y_int[31]_i_116_n_0\ ); \y_int_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[3]_i_1_n_4\, Q => \y_int_reg_n_0_[3]\, R => '0' ); \y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_1_n_0\, CO(2) => \y_int_reg[3]_i_1_n_1\, CO(1) => \y_int_reg[3]_i_1_n_2\, CO(0) => \y_int_reg[3]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[3]_i_2_n_0\, DI(2) => \y_int[3]_i_3_n_0\, DI(1) => \y_int[3]_i_4_n_0\, DI(0) => '0', O(3) => \y_int_reg[3]_i_1_n_4\, O(2) => \y_int_reg[3]_i_1_n_5\, O(1) => \y_int_reg[3]_i_1_n_6\, O(0) => \y_int_reg[3]_i_1_n_7\, S(3) => \y_int[3]_i_5_n_0\, S(2) => \y_int[3]_i_6_n_0\, S(1) => \y_int[3]_i_7_n_0\, S(0) => \y_int[3]_i_8_n_0\ ); \y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_21_n_0\, CO(3) => \y_int_reg[3]_i_15_n_0\, CO(2) => \y_int_reg[3]_i_15_n_1\, CO(1) => \y_int_reg[3]_i_15_n_2\, CO(0) => \y_int_reg[3]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => y_int_reg5(8), O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0), S(3) => \y_int[3]_i_22_n_0\, S(2) => \y_int[3]_i_23_n_0\, S(1) => \y_int[3]_i_24_n_0\, S(0) => \y_int[3]_i_25_n_0\ ); \y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_26_n_0\, CO(3) => \y_int_reg[3]_i_16_n_0\, CO(2) => \y_int_reg[3]_i_16_n_1\, CO(1) => \y_int_reg[3]_i_16_n_2\, CO(0) => \y_int_reg[3]_i_16_n_3\, CYINIT => '0', DI(3) => \y_int[3]_i_27_n_0\, DI(2) => \y_int[3]_i_28_n_0\, DI(1) => \y_int[3]_i_29_n_0\, DI(0) => \y_int_reg[3]_i_30_n_6\, O(3) => \y_int_reg[3]_i_16_n_4\, O(2) => \y_int_reg[3]_i_16_n_5\, O(1) => \y_int_reg[3]_i_16_n_6\, O(0) => \y_int_reg[3]_i_16_n_7\, S(3) => \y_int[3]_i_31_n_0\, S(2) => \y_int[3]_i_32_n_0\, S(1) => \y_int[3]_i_33_n_0\, S(0) => \y_int[3]_i_34_n_0\ ); \y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_21_n_0\, CO(2) => \y_int_reg[3]_i_21_n_1\, CO(1) => \y_int_reg[3]_i_21_n_2\, CO(0) => \y_int_reg[3]_i_21_n_3\, CYINIT => \y_int[3]_i_50_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[3]_i_51_n_0\, S(2) => \y_int[3]_i_52_n_0\, S(1) => \y_int[3]_i_53_n_0\, S(0) => \y_int[3]_i_54_n_0\ ); \y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_26_n_0\, CO(2) => \y_int_reg[3]_i_26_n_1\, CO(1) => \y_int_reg[3]_i_26_n_2\, CO(0) => \y_int_reg[3]_i_26_n_3\, CYINIT => '0', DI(3) => \y_int_reg[3]_i_30_n_7\, DI(2) => \y_int_reg[3]_i_55_n_4\, DI(1) => \y_int_reg[3]_i_55_n_5\, DI(0) => '0', O(3) => \y_int_reg[3]_i_26_n_4\, O(2) => \y_int_reg[3]_i_26_n_5\, O(1) => \y_int_reg[3]_i_26_n_6\, O(0) => \y_int_reg[3]_i_26_n_7\, S(3) => \y_int[3]_i_56_n_0\, S(2) => \y_int[3]_i_57_n_0\, S(1) => \y_int[3]_i_58_n_0\, S(0) => \y_int[3]_i_59_n_0\ ); \y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_55_n_0\, CO(3) => \y_int_reg[3]_i_30_n_0\, CO(2) => \y_int_reg[3]_i_30_n_1\, CO(1) => \y_int_reg[3]_i_30_n_2\, CO(0) => \y_int_reg[3]_i_30_n_3\, CYINIT => '0', DI(3) => rgb888(22), DI(2 downto 0) => rgb888(23 downto 21), O(3) => \y_int_reg[3]_i_30_n_4\, O(2) => \y_int_reg[3]_i_30_n_5\, O(1) => \y_int_reg[3]_i_30_n_6\, O(0) => \y_int_reg[3]_i_30_n_7\, S(3) => \y_int[3]_i_60_n_0\, S(2) => \y_int[3]_i_61_n_0\, S(1) => \y_int[3]_i_62_n_0\, S(0) => \y_int[3]_i_63_n_0\ ); \y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_65_n_0\, CO(3) => \y_int_reg[3]_i_35_n_0\, CO(2) => \y_int_reg[3]_i_35_n_1\, CO(1) => \y_int_reg[3]_i_35_n_2\, CO(0) => \y_int_reg[3]_i_35_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[3]_i_35_n_4\, O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0), S(3) => \y_int[3]_i_66_n_0\, S(2) => \y_int[3]_i_67_n_0\, S(1) => \y_int[3]_i_68_n_0\, S(0) => \y_int[3]_i_69_n_0\ ); \y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_2\(0), CO(2) => \y_int_reg[3]_i_36_n_1\, CO(1) => \y_int_reg[3]_i_36_n_2\, CO(0) => \y_int_reg[3]_i_36_n_3\, CYINIT => '0', DI(3 downto 2) => \rgb888[8]_32\(1 downto 0), DI(1) => \rgb888[8]_19\(2), DI(0) => '0', O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0), S(3) => \y_int[3]_i_71_n_0\, S(2) => \y_int[3]_i_72_n_0\, S(1) => \y_int[3]_i_73_n_0\, S(0) => \y_int[3]_i_74_n_0\ ); \y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_55_n_0\, CO(2) => \y_int_reg[3]_i_55_n_1\, CO(1) => \y_int_reg[3]_i_55_n_2\, CO(0) => \y_int_reg[3]_i_55_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(20 downto 18), DI(0) => '0', O(3) => \y_int_reg[3]_i_55_n_4\, O(2) => \y_int_reg[3]_i_55_n_5\, O(1) => \y_int_reg[3]_i_55_n_6\, O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0), S(3) => \y_int[3]_i_84_n_0\, S(2) => \y_int[3]_i_85_n_0\, S(1) => \y_int[3]_i_86_n_0\, S(0) => \y_int[3]_i_87_n_0\ ); \y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_30_n_0\, CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[3]_i_64_n_2\, CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(23), O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1), O(0) => \y_int_reg[3]_i_64_n_7\, S(3 downto 1) => B"001", S(0) => \y_int[3]_i_88_n_0\ ); \y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_65_n_0\, CO(2) => \y_int_reg[3]_i_65_n_1\, CO(1) => \y_int_reg[3]_i_65_n_2\, CO(0) => \y_int_reg[3]_i_65_n_3\, CYINIT => \cr_int[3]_i_80_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[3]_i_89_n_0\, S(2) => \y_int[3]_i_90_n_0\, S(1) => \y_int[3]_i_91_n_0\, S(0) => \y_int[3]_i_92_n_0\ ); \y_int_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[7]_i_1_n_7\, Q => \y_int_reg_n_0_[4]\, R => '0' ); \y_int_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[7]_i_1_n_6\, Q => \y_int_reg_n_0_[5]\, R => '0' ); \y_int_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[7]_i_1_n_5\, Q => \y_int_reg_n_0_[6]\, R => '0' ); \y_int_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[7]_i_1_n_4\, Q => \y_int_reg_n_0_[7]\, R => '0' ); \y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_1_n_0\, CO(3) => \y_int_reg[7]_i_1_n_0\, CO(2) => \y_int_reg[7]_i_1_n_1\, CO(1) => \y_int_reg[7]_i_1_n_2\, CO(0) => \y_int_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[7]_i_2_n_0\, DI(2) => \y_int[7]_i_3_n_0\, DI(1) => \y_int[7]_i_4_n_0\, DI(0) => \y_int[7]_i_5_n_0\, O(3) => \y_int_reg[7]_i_1_n_4\, O(2) => \y_int_reg[7]_i_1_n_5\, O(1) => \y_int_reg[7]_i_1_n_6\, O(0) => \y_int_reg[7]_i_1_n_7\, S(3) => \y_int[7]_i_6_n_0\, S(2) => \y_int[7]_i_7_n_0\, S(1) => \y_int[7]_i_8_n_0\, S(0) => \y_int[7]_i_9_n_0\ ); \y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[7]_i_24_n_0\, CO(2) => \y_int_reg[7]_i_24_n_1\, CO(1) => \y_int_reg[7]_i_24_n_2\, CO(0) => \y_int_reg[7]_i_24_n_3\, CYINIT => \y_int[7]_i_29_n_0\, DI(3 downto 0) => B"0000", O(3) => \y_int_reg[7]_i_24_n_4\, O(2) => \y_int_reg[7]_i_24_n_5\, O(1) => \y_int_reg[7]_i_24_n_6\, O(0) => \y_int_reg[7]_i_24_n_7\, S(3) => \y_int[7]_i_30_n_0\, S(2) => \y_int[7]_i_31_n_0\, S(1) => \y_int[7]_i_32_n_0\, S(0) => \y_int[7]_i_33_n_0\ ); \y_int_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[11]_i_1_n_7\, Q => \y_int_reg__0\(8), R => '0' ); \y_int_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[11]_i_1_n_6\, Q => \y_int_reg__0\(9), R => '0' ); \y_reg[0]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[0]_i_1_n_0\, Q => y(0), S => \y_reg[7]_i_1_n_0\ ); \y_reg[1]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[1]_i_1_n_0\, Q => y(1), S => \y_reg[7]_i_1_n_0\ ); \y_reg[2]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[2]_i_1_n_0\, Q => y(2), S => \y_reg[7]_i_1_n_0\ ); \y_reg[3]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[3]_i_1_n_0\, Q => y(3), S => \y_reg[7]_i_1_n_0\ ); \y_reg[4]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[4]_i_1_n_0\, Q => y(4), S => \y_reg[7]_i_1_n_0\ ); \y_reg[5]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[5]_i_1_n_0\, Q => y(5), S => \y_reg[7]_i_1_n_0\ ); \y_reg[6]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[6]_i_1_n_0\, Q => y(6), S => \y_reg[7]_i_1_n_0\ ); \y_reg[7]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[7]_i_2_n_0\, Q => y(7), S => \y_reg[7]_i_1_n_0\ ); \y_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_reg[7]_i_3_n_0\, CO(3) => \y_reg[7]_i_1_n_0\, CO(2) => \y_reg[7]_i_1_n_1\, CO(1) => \y_reg[7]_i_1_n_2\, CO(0) => \y_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \y[7]_i_4_n_0\, DI(2) => \y[7]_i_5_n_0\, DI(1) => \y[7]_i_6_n_0\, DI(0) => \y[7]_i_7_n_0\, O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \y[7]_i_8_n_0\, S(2) => \y[7]_i_9_n_0\, S(1) => \y[7]_i_10_n_0\, S(0) => \y[7]_i_11_n_0\ ); \y_reg[7]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_reg[7]_i_12_n_0\, CO(2) => \y_reg[7]_i_12_n_1\, CO(1) => \y_reg[7]_i_12_n_2\, CO(0) => \y_reg[7]_i_12_n_3\, CYINIT => '0', DI(3) => \y[7]_i_21_n_0\, DI(2) => \y[7]_i_22_n_0\, DI(1) => \y[7]_i_23_n_0\, DI(0) => \y[7]_i_24_n_0\, O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0), S(3) => \y[7]_i_25_n_0\, S(2) => \y[7]_i_26_n_0\, S(1) => \y[7]_i_27_n_0\, S(0) => \y[7]_i_28_n_0\ ); \y_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \y_reg[7]_i_12_n_0\, CO(3) => \y_reg[7]_i_3_n_0\, CO(2) => \y_reg[7]_i_3_n_1\, CO(1) => \y_reg[7]_i_3_n_2\, CO(0) => \y_reg[7]_i_3_n_3\, CYINIT => '0', DI(3) => \y[7]_i_13_n_0\, DI(2) => \y[7]_i_14_n_0\, DI(1) => \y[7]_i_15_n_0\, DI(0) => \y[7]_i_16_n_0\, O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0), S(3) => \y[7]_i_17_n_0\, S(2) => \y[7]_i_18_n_0\, S(1) => \y[7]_i_19_n_0\, S(0) => \y[7]_i_20_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_zed_hdmi_0_0 is port ( clk : in STD_LOGIC; clk_x2 : in STD_LOGIC; clk_100 : in STD_LOGIC; active : in STD_LOGIC; hsync : in STD_LOGIC; vsync : in STD_LOGIC; rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 ); hdmi_clk : out STD_LOGIC; hdmi_hsync : out STD_LOGIC; hdmi_vsync : out STD_LOGIC; hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 ); hdmi_de : out STD_LOGIC; hdmi_scl : out STD_LOGIC; hdmi_sda : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4"; end system_zed_hdmi_0_0; architecture STRUCTURE of system_zed_hdmi_0_0 is signal \<const0>\ : STD_LOGIC; signal U0_n_10 : STD_LOGIC; signal U0_n_11 : STD_LOGIC; signal U0_n_12 : STD_LOGIC; signal U0_n_13 : STD_LOGIC; signal U0_n_14 : STD_LOGIC; signal U0_n_15 : STD_LOGIC; signal U0_n_16 : STD_LOGIC; signal U0_n_17 : STD_LOGIC; signal U0_n_18 : STD_LOGIC; signal U0_n_19 : STD_LOGIC; signal U0_n_20 : STD_LOGIC; signal U0_n_21 : STD_LOGIC; signal U0_n_22 : STD_LOGIC; signal U0_n_23 : STD_LOGIC; signal U0_n_24 : STD_LOGIC; signal U0_n_25 : STD_LOGIC; signal U0_n_26 : STD_LOGIC; signal U0_n_27 : STD_LOGIC; signal U0_n_28 : STD_LOGIC; signal U0_n_29 : STD_LOGIC; signal U0_n_30 : STD_LOGIC; signal U0_n_31 : STD_LOGIC; signal U0_n_32 : STD_LOGIC; signal U0_n_33 : STD_LOGIC; signal U0_n_34 : STD_LOGIC; signal U0_n_35 : STD_LOGIC; signal U0_n_36 : STD_LOGIC; signal U0_n_37 : STD_LOGIC; signal U0_n_38 : STD_LOGIC; signal U0_n_39 : STD_LOGIC; signal U0_n_4 : STD_LOGIC; signal U0_n_40 : STD_LOGIC; signal U0_n_41 : STD_LOGIC; signal U0_n_42 : STD_LOGIC; signal U0_n_43 : STD_LOGIC; signal U0_n_44 : STD_LOGIC; signal U0_n_45 : STD_LOGIC; signal U0_n_46 : STD_LOGIC; signal U0_n_47 : STD_LOGIC; signal U0_n_48 : STD_LOGIC; signal U0_n_49 : STD_LOGIC; signal U0_n_5 : STD_LOGIC; signal U0_n_50 : STD_LOGIC; signal U0_n_51 : STD_LOGIC; signal U0_n_52 : STD_LOGIC; signal U0_n_53 : STD_LOGIC; signal U0_n_54 : STD_LOGIC; signal U0_n_55 : STD_LOGIC; signal U0_n_56 : STD_LOGIC; signal U0_n_57 : STD_LOGIC; signal U0_n_58 : STD_LOGIC; signal U0_n_59 : STD_LOGIC; signal U0_n_6 : STD_LOGIC; signal U0_n_60 : STD_LOGIC; signal U0_n_61 : STD_LOGIC; signal U0_n_62 : STD_LOGIC; signal U0_n_63 : STD_LOGIC; signal U0_n_64 : STD_LOGIC; signal U0_n_65 : STD_LOGIC; signal U0_n_66 : STD_LOGIC; signal U0_n_67 : STD_LOGIC; signal U0_n_68 : STD_LOGIC; signal U0_n_69 : STD_LOGIC; signal U0_n_7 : STD_LOGIC; signal U0_n_70 : STD_LOGIC; signal U0_n_71 : STD_LOGIC; signal U0_n_72 : STD_LOGIC; signal U0_n_73 : STD_LOGIC; signal U0_n_74 : STD_LOGIC; signal U0_n_75 : STD_LOGIC; signal U0_n_76 : STD_LOGIC; signal U0_n_77 : STD_LOGIC; signal U0_n_78 : STD_LOGIC; signal U0_n_79 : STD_LOGIC; signal U0_n_8 : STD_LOGIC; signal U0_n_80 : STD_LOGIC; signal U0_n_81 : STD_LOGIC; signal U0_n_9 : STD_LOGIC; signal \cb_int[15]_i_35_n_0\ : STD_LOGIC; signal \cb_int[15]_i_36_n_0\ : STD_LOGIC; signal \cb_int[15]_i_37_n_0\ : STD_LOGIC; signal \cb_int[15]_i_38_n_0\ : STD_LOGIC; signal \cb_int[15]_i_39_n_0\ : STD_LOGIC; signal \cb_int[15]_i_40_n_0\ : STD_LOGIC; signal \cb_int[15]_i_41_n_0\ : STD_LOGIC; signal \cb_int[15]_i_42_n_0\ : STD_LOGIC; signal \cb_int[15]_i_47_n_0\ : STD_LOGIC; signal \cb_int[15]_i_48_n_0\ : STD_LOGIC; signal \cb_int[15]_i_49_n_0\ : STD_LOGIC; signal \cb_int[15]_i_50_n_0\ : STD_LOGIC; signal \cb_int[19]_i_38_n_0\ : STD_LOGIC; signal \cb_int[19]_i_39_n_0\ : STD_LOGIC; signal \cb_int[19]_i_40_n_0\ : STD_LOGIC; signal \cb_int[19]_i_41_n_0\ : STD_LOGIC; signal \cb_int[19]_i_42_n_0\ : STD_LOGIC; signal \cb_int[19]_i_43_n_0\ : STD_LOGIC; signal \cb_int[19]_i_44_n_0\ : STD_LOGIC; signal \cb_int[19]_i_45_n_0\ : STD_LOGIC; signal \cb_int[23]_i_33_n_0\ : STD_LOGIC; signal \cb_int[23]_i_34_n_0\ : STD_LOGIC; signal \cb_int[23]_i_35_n_0\ : STD_LOGIC; signal \cb_int[23]_i_36_n_0\ : STD_LOGIC; signal \cb_int[23]_i_37_n_0\ : STD_LOGIC; signal \cb_int[23]_i_38_n_0\ : STD_LOGIC; signal \cb_int[23]_i_39_n_0\ : STD_LOGIC; signal \cb_int[23]_i_40_n_0\ : STD_LOGIC; signal \cb_int[31]_i_100_n_0\ : STD_LOGIC; signal \cb_int[31]_i_101_n_0\ : STD_LOGIC; signal \cb_int[31]_i_18_n_0\ : STD_LOGIC; signal \cb_int[31]_i_19_n_0\ : STD_LOGIC; signal \cb_int[31]_i_20_n_0\ : STD_LOGIC; signal \cb_int[31]_i_21_n_0\ : STD_LOGIC; signal \cb_int[31]_i_22_n_0\ : STD_LOGIC; signal \cb_int[31]_i_25_n_0\ : STD_LOGIC; signal \cb_int[31]_i_26_n_0\ : STD_LOGIC; signal \cb_int[31]_i_28_n_0\ : STD_LOGIC; signal \cb_int[31]_i_29_n_0\ : STD_LOGIC; signal \cb_int[31]_i_45_n_0\ : STD_LOGIC; signal \cb_int[31]_i_46_n_0\ : STD_LOGIC; signal \cb_int[31]_i_47_n_0\ : STD_LOGIC; signal \cb_int[31]_i_48_n_0\ : STD_LOGIC; signal \cb_int[31]_i_49_n_0\ : STD_LOGIC; signal \cb_int[31]_i_50_n_0\ : STD_LOGIC; signal \cb_int[31]_i_52_n_0\ : STD_LOGIC; signal \cb_int[31]_i_53_n_0\ : STD_LOGIC; signal \cb_int[31]_i_54_n_0\ : STD_LOGIC; signal \cb_int[31]_i_55_n_0\ : STD_LOGIC; signal \cb_int[31]_i_56_n_0\ : STD_LOGIC; signal \cb_int[31]_i_57_n_0\ : STD_LOGIC; signal \cb_int[31]_i_58_n_0\ : STD_LOGIC; signal \cb_int[31]_i_59_n_0\ : STD_LOGIC; signal \cb_int[31]_i_60_n_0\ : STD_LOGIC; signal \cb_int[31]_i_62_n_0\ : STD_LOGIC; signal \cb_int[31]_i_63_n_0\ : STD_LOGIC; signal \cb_int[31]_i_64_n_0\ : STD_LOGIC; signal \cb_int[31]_i_65_n_0\ : STD_LOGIC; signal \cb_int[31]_i_83_n_0\ : STD_LOGIC; signal \cb_int[31]_i_84_n_0\ : STD_LOGIC; signal \cb_int[31]_i_88_n_0\ : STD_LOGIC; signal \cb_int[31]_i_89_n_0\ : STD_LOGIC; signal \cb_int[31]_i_90_n_0\ : STD_LOGIC; signal \cb_int[31]_i_91_n_0\ : STD_LOGIC; signal \cb_int[31]_i_92_n_0\ : STD_LOGIC; signal \cb_int[31]_i_93_n_0\ : STD_LOGIC; signal \cb_int[31]_i_94_n_0\ : STD_LOGIC; signal \cb_int[31]_i_99_n_0\ : STD_LOGIC; signal \cb_int[3]_i_35_n_0\ : STD_LOGIC; signal \cb_int[3]_i_36_n_0\ : STD_LOGIC; signal \cb_int[3]_i_37_n_0\ : STD_LOGIC; signal \cb_int[3]_i_38_n_0\ : STD_LOGIC; signal \cb_int[3]_i_39_n_0\ : STD_LOGIC; signal \cb_int[3]_i_40_n_0\ : STD_LOGIC; signal \cb_int[3]_i_41_n_0\ : STD_LOGIC; signal \cb_int[3]_i_42_n_0\ : STD_LOGIC; signal \cb_int[3]_i_59_n_0\ : STD_LOGIC; signal \cb_int[3]_i_60_n_0\ : STD_LOGIC; signal \cb_int[3]_i_61_n_0\ : STD_LOGIC; signal \cb_int[3]_i_62_n_0\ : STD_LOGIC; signal \cb_int[3]_i_73_n_0\ : STD_LOGIC; signal \cb_int[3]_i_74_n_0\ : STD_LOGIC; signal \cb_int[3]_i_84_n_0\ : STD_LOGIC; signal \cb_int[3]_i_85_n_0\ : STD_LOGIC; signal \cb_int[3]_i_86_n_0\ : STD_LOGIC; signal \cb_int[3]_i_87_n_0\ : STD_LOGIC; signal \cb_int[3]_i_88_n_0\ : STD_LOGIC; signal \cb_int[3]_i_95_n_0\ : STD_LOGIC; signal \cb_int[3]_i_96_n_0\ : STD_LOGIC; signal \cb_int[3]_i_97_n_0\ : STD_LOGIC; signal \cb_int[3]_i_98_n_0\ : STD_LOGIC; signal \cb_int[7]_i_30_n_0\ : STD_LOGIC; signal \cb_int[7]_i_31_n_0\ : STD_LOGIC; signal \cb_int[7]_i_32_n_0\ : STD_LOGIC; signal \cb_int[7]_i_33_n_0\ : STD_LOGIC; signal \cb_int[7]_i_34_n_0\ : STD_LOGIC; signal \cb_int[7]_i_35_n_0\ : STD_LOGIC; signal \cb_int[7]_i_36_n_0\ : STD_LOGIC; signal \cb_int[7]_i_37_n_0\ : STD_LOGIC; signal \cb_int[7]_i_43_n_0\ : STD_LOGIC; signal \cb_int[7]_i_44_n_0\ : STD_LOGIC; signal \cb_int[7]_i_45_n_0\ : STD_LOGIC; signal \cb_int[7]_i_46_n_0\ : STD_LOGIC; signal \cb_int[7]_i_47_n_0\ : STD_LOGIC; signal \cb_int[7]_i_48_n_0\ : STD_LOGIC; signal \cb_int[7]_i_49_n_0\ : STD_LOGIC; signal \cb_int[7]_i_50_n_0\ : STD_LOGIC; signal \cb_int[7]_i_51_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC; signal \cr_int[11]_i_61_n_0\ : STD_LOGIC; signal \cr_int[11]_i_62_n_0\ : STD_LOGIC; signal \cr_int[11]_i_63_n_0\ : STD_LOGIC; signal \cr_int[11]_i_64_n_0\ : STD_LOGIC; signal \cr_int[15]_i_44_n_0\ : STD_LOGIC; signal \cr_int[15]_i_45_n_0\ : STD_LOGIC; signal \cr_int[15]_i_46_n_0\ : STD_LOGIC; signal \cr_int[15]_i_47_n_0\ : STD_LOGIC; signal \cr_int[15]_i_52_n_0\ : STD_LOGIC; signal \cr_int[15]_i_53_n_0\ : STD_LOGIC; signal \cr_int[15]_i_54_n_0\ : STD_LOGIC; signal \cr_int[15]_i_55_n_0\ : STD_LOGIC; signal \cr_int[19]_i_42_n_0\ : STD_LOGIC; signal \cr_int[19]_i_43_n_0\ : STD_LOGIC; signal \cr_int[19]_i_44_n_0\ : STD_LOGIC; signal \cr_int[19]_i_45_n_0\ : STD_LOGIC; signal \cr_int[23]_i_32_n_0\ : STD_LOGIC; signal \cr_int[23]_i_33_n_0\ : STD_LOGIC; signal \cr_int[23]_i_34_n_0\ : STD_LOGIC; signal \cr_int[23]_i_35_n_0\ : STD_LOGIC; signal \cr_int[31]_i_104_n_0\ : STD_LOGIC; signal \cr_int[31]_i_105_n_0\ : STD_LOGIC; signal \cr_int[31]_i_106_n_0\ : STD_LOGIC; signal \cr_int[31]_i_107_n_0\ : STD_LOGIC; signal \cr_int[31]_i_28_n_0\ : STD_LOGIC; signal \cr_int[31]_i_29_n_0\ : STD_LOGIC; signal \cr_int[31]_i_65_n_0\ : STD_LOGIC; signal \cr_int[31]_i_66_n_0\ : STD_LOGIC; signal \cr_int[31]_i_67_n_0\ : STD_LOGIC; signal \cr_int[31]_i_68_n_0\ : STD_LOGIC; signal \cr_int[31]_i_98_n_0\ : STD_LOGIC; signal \cr_int[31]_i_99_n_0\ : STD_LOGIC; signal \cr_int[7]_i_29_n_0\ : STD_LOGIC; signal \cr_int[7]_i_30_n_0\ : STD_LOGIC; signal \cr_int[7]_i_31_n_0\ : STD_LOGIC; signal \cr_int[7]_i_32_n_0\ : STD_LOGIC; signal \cr_int[7]_i_33_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC; signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \y_int[11]_i_54_n_0\ : STD_LOGIC; signal \y_int[11]_i_55_n_0\ : STD_LOGIC; signal \y_int[11]_i_56_n_0\ : STD_LOGIC; signal \y_int[11]_i_57_n_0\ : STD_LOGIC; signal \y_int[15]_i_36_n_0\ : STD_LOGIC; signal \y_int[15]_i_37_n_0\ : STD_LOGIC; signal \y_int[15]_i_38_n_0\ : STD_LOGIC; signal \y_int[15]_i_39_n_0\ : STD_LOGIC; signal \y_int[15]_i_44_n_0\ : STD_LOGIC; signal \y_int[15]_i_45_n_0\ : STD_LOGIC; signal \y_int[15]_i_46_n_0\ : STD_LOGIC; signal \y_int[15]_i_47_n_0\ : STD_LOGIC; signal \y_int[19]_i_36_n_0\ : STD_LOGIC; signal \y_int[19]_i_37_n_0\ : STD_LOGIC; signal \y_int[19]_i_38_n_0\ : STD_LOGIC; signal \y_int[19]_i_39_n_0\ : STD_LOGIC; signal \y_int[19]_i_40_n_0\ : STD_LOGIC; signal \y_int[19]_i_41_n_0\ : STD_LOGIC; signal \y_int[19]_i_42_n_0\ : STD_LOGIC; signal \y_int[19]_i_43_n_0\ : STD_LOGIC; signal \y_int[19]_i_44_n_0\ : STD_LOGIC; signal \y_int[19]_i_45_n_0\ : STD_LOGIC; signal \y_int[19]_i_46_n_0\ : STD_LOGIC; signal \y_int[19]_i_47_n_0\ : STD_LOGIC; signal \y_int[23]_i_50_n_0\ : STD_LOGIC; signal \y_int[23]_i_58_n_0\ : STD_LOGIC; signal \y_int[23]_i_59_n_0\ : STD_LOGIC; signal \y_int[23]_i_60_n_0\ : STD_LOGIC; signal \y_int[23]_i_61_n_0\ : STD_LOGIC; signal \y_int[31]_i_100_n_0\ : STD_LOGIC; signal \y_int[31]_i_102_n_0\ : STD_LOGIC; signal \y_int[31]_i_103_n_0\ : STD_LOGIC; signal \y_int[31]_i_22_n_0\ : STD_LOGIC; signal \y_int[31]_i_23_n_0\ : STD_LOGIC; signal \y_int[31]_i_24_n_0\ : STD_LOGIC; signal \y_int[31]_i_25_n_0\ : STD_LOGIC; signal \y_int[31]_i_26_n_0\ : STD_LOGIC; signal \y_int[31]_i_28_n_0\ : STD_LOGIC; signal \y_int[31]_i_29_n_0\ : STD_LOGIC; signal \y_int[31]_i_38_n_0\ : STD_LOGIC; signal \y_int[31]_i_39_n_0\ : STD_LOGIC; signal \y_int[31]_i_48_n_0\ : STD_LOGIC; signal \y_int[31]_i_49_n_0\ : STD_LOGIC; signal \y_int[31]_i_50_n_0\ : STD_LOGIC; signal \y_int[31]_i_51_n_0\ : STD_LOGIC; signal \y_int[31]_i_52_n_0\ : STD_LOGIC; signal \y_int[31]_i_53_n_0\ : STD_LOGIC; signal \y_int[31]_i_54_n_0\ : STD_LOGIC; signal \y_int[31]_i_55_n_0\ : STD_LOGIC; signal \y_int[31]_i_56_n_0\ : STD_LOGIC; signal \y_int[31]_i_57_n_0\ : STD_LOGIC; signal \y_int[31]_i_58_n_0\ : STD_LOGIC; signal \y_int[31]_i_59_n_0\ : STD_LOGIC; signal \y_int[31]_i_60_n_0\ : STD_LOGIC; signal \y_int[31]_i_61_n_0\ : STD_LOGIC; signal \y_int[31]_i_72_n_0\ : STD_LOGIC; signal \y_int[31]_i_73_n_0\ : STD_LOGIC; signal \y_int[31]_i_74_n_0\ : STD_LOGIC; signal \y_int[31]_i_76_n_0\ : STD_LOGIC; signal \y_int[31]_i_77_n_0\ : STD_LOGIC; signal \y_int[31]_i_78_n_0\ : STD_LOGIC; signal \y_int[31]_i_79_n_0\ : STD_LOGIC; signal \y_int[31]_i_80_n_0\ : STD_LOGIC; signal \y_int[31]_i_81_n_0\ : STD_LOGIC; signal \y_int[31]_i_83_n_0\ : STD_LOGIC; signal \y_int[31]_i_84_n_0\ : STD_LOGIC; signal \y_int[31]_i_85_n_0\ : STD_LOGIC; signal \y_int[31]_i_93_n_0\ : STD_LOGIC; signal \y_int[31]_i_94_n_0\ : STD_LOGIC; signal \y_int[31]_i_95_n_0\ : STD_LOGIC; signal \y_int[31]_i_96_n_0\ : STD_LOGIC; signal \y_int[31]_i_97_n_0\ : STD_LOGIC; signal \y_int[31]_i_98_n_0\ : STD_LOGIC; signal \y_int[31]_i_99_n_0\ : STD_LOGIC; signal \y_int[3]_i_37_n_0\ : STD_LOGIC; signal \y_int[3]_i_38_n_0\ : STD_LOGIC; signal \y_int[3]_i_39_n_0\ : STD_LOGIC; signal \y_int[3]_i_41_n_0\ : STD_LOGIC; signal \y_int[3]_i_42_n_0\ : STD_LOGIC; signal \y_int[3]_i_43_n_0\ : STD_LOGIC; signal \y_int[3]_i_44_n_0\ : STD_LOGIC; signal \y_int[3]_i_46_n_0\ : STD_LOGIC; signal \y_int[3]_i_47_n_0\ : STD_LOGIC; signal \y_int[3]_i_48_n_0\ : STD_LOGIC; signal \y_int[3]_i_49_n_0\ : STD_LOGIC; signal \y_int[3]_i_75_n_0\ : STD_LOGIC; signal \y_int[3]_i_76_n_0\ : STD_LOGIC; signal \y_int[3]_i_77_n_0\ : STD_LOGIC; signal \y_int[3]_i_78_n_0\ : STD_LOGIC; signal \y_int[3]_i_79_n_0\ : STD_LOGIC; signal \y_int[3]_i_80_n_0\ : STD_LOGIC; signal \y_int[3]_i_81_n_0\ : STD_LOGIC; signal \y_int[3]_i_82_n_0\ : STD_LOGIC; signal \y_int[3]_i_83_n_0\ : STD_LOGIC; signal \y_int[3]_i_93_n_0\ : STD_LOGIC; signal \y_int[3]_i_94_n_0\ : STD_LOGIC; signal \y_int[3]_i_95_n_0\ : STD_LOGIC; signal \y_int[3]_i_96_n_0\ : STD_LOGIC; signal \y_int[7]_i_25_n_0\ : STD_LOGIC; signal \y_int[7]_i_26_n_0\ : STD_LOGIC; signal \y_int[7]_i_27_n_0\ : STD_LOGIC; signal \y_int[7]_i_28_n_0\ : STD_LOGIC; signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 ); signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC; signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC; signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC; signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); attribute HLUTNM : string; attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0"; attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38"; begin hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8); hdmi_d(7) <= \<const0>\; hdmi_d(6) <= \<const0>\; hdmi_d(5) <= \<const0>\; hdmi_d(4) <= \<const0>\; hdmi_d(3) <= \<const0>\; hdmi_d(2) <= \<const0>\; hdmi_d(1) <= \<const0>\; hdmi_d(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); U0: entity work.system_zed_hdmi_0_0_zed_hdmi port map ( CO(0) => U0_n_16, DI(0) => U0_n_4, O(1) => U0_n_7, O(0) => U0_n_8, active => active, \cb_int_reg[15]_0\(0) => U0_n_76, \cb_int_reg[27]_0\(0) => U0_n_75, \cb_int_reg[3]_0\(3) => U0_n_9, \cb_int_reg[3]_0\(2) => U0_n_10, \cb_int_reg[3]_0\(1) => U0_n_11, \cb_int_reg[3]_0\(0) => U0_n_12, \cb_int_reg[3]_1\(0) => U0_n_72, \cb_int_reg[3]_2\(0) => U0_n_73, \cb_int_reg[3]_3\(0) => U0_n_74, clk => clk, clk_100 => clk_100, clk_x2 => clk_x2, \cr_int_reg[11]_0\(3) => U0_n_34, \cr_int_reg[11]_0\(2) => U0_n_35, \cr_int_reg[11]_0\(1) => U0_n_36, \cr_int_reg[11]_0\(0) => U0_n_37, \cr_int_reg[15]_0\(3) => U0_n_38, \cr_int_reg[15]_0\(2) => U0_n_39, \cr_int_reg[15]_0\(1) => U0_n_40, \cr_int_reg[15]_0\(0) => U0_n_41, \cr_int_reg[15]_1\(0) => U0_n_77, \cr_int_reg[19]_0\(3) => U0_n_42, \cr_int_reg[19]_0\(2) => U0_n_43, \cr_int_reg[19]_0\(1) => U0_n_44, \cr_int_reg[19]_0\(0) => U0_n_45, \cr_int_reg[23]_0\(3) => U0_n_46, \cr_int_reg[23]_0\(2) => U0_n_47, \cr_int_reg[23]_0\(1) => U0_n_48, \cr_int_reg[23]_0\(0) => U0_n_49, \cr_int_reg[23]_1\(0) => U0_n_50, \cr_int_reg[27]_0\ => U0_n_13, \cr_int_reg[27]_1\(1) => U0_n_14, \cr_int_reg[27]_1\(0) => U0_n_15, \cr_int_reg[27]_2\(0) => U0_n_29, \cr_int_reg[31]_0\ => U0_n_5, \cr_int_reg[31]_1\ => U0_n_6, \cr_int_reg[31]_2\(1) => U0_n_17, \cr_int_reg[31]_2\(0) => U0_n_18, \cr_int_reg[3]_0\(2) => U0_n_23, \cr_int_reg[3]_0\(1) => U0_n_24, \cr_int_reg[3]_0\(0) => U0_n_25, \cr_int_reg[3]_1\(0) => U0_n_26, \cr_int_reg[3]_2\(1) => U0_n_27, \cr_int_reg[3]_2\(0) => U0_n_28, \cr_int_reg[7]_0\(3) => U0_n_19, \cr_int_reg[7]_0\(2) => U0_n_20, \cr_int_reg[7]_0\(1) => U0_n_21, \cr_int_reg[7]_0\(0) => U0_n_22, \cr_int_reg[7]_1\(3) => U0_n_30, \cr_int_reg[7]_1\(2) => U0_n_31, \cr_int_reg[7]_1\(1) => U0_n_32, \cr_int_reg[7]_1\(0) => U0_n_33, hdmi_clk => hdmi_clk, hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8), hdmi_de => hdmi_de, hdmi_hsync => hdmi_hsync, hdmi_scl => hdmi_scl, hdmi_sda => hdmi_sda, hdmi_vsync => hdmi_vsync, hsync => hsync, rgb888(23 downto 0) => rgb888(23 downto 0), \rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\, \rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\, \rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\, \rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\, \rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\, \rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\, \rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\, \rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\, \rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\, \rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\, \rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\, \rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\, \rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\, \rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\, \rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\, \rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\, \rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\, \rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\, \rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\, \rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\, \rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\, \rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\, \rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\, \rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\, \rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\, \rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\, \rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\, \rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\, \rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\, \rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\, \rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\, \rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\, \rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\, \rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\, \rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\, \rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\, \rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\, \rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\, \rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\, \rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\, \rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\, \rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\, \rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\, \rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\, \rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\, \rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\, \rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\, \rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\, \rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\, \rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\, \rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\, \rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\, \rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\, \rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\, \rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\, \rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\, \rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\, \rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\, \rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\, \rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\, \rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9), \rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\, \rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\, \rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\, \rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\, \rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\, \rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\, \rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\, \rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\, \rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\, \rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\, \rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\, \rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\, \rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\, \rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\, \rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\, \rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\, \rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\, \rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\, \rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\, \rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\, \rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\, \rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\, \rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\, \rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\, \rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\, \rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\, \rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\, \rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\, \rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\, \rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\, \rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\, \rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\, \rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\, \rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\, \rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\, \rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\, \rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\, \rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\, \rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\, \rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\, \rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\, \rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\, \rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\, \rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\, \rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\, \rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\, \rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\, \rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\, \rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\, \rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\, \rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\, \rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\, \rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\, \rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\, \rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\, \rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\, \rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\, \rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\, \rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\, \rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\, \rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\, \rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\, \rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\, \rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\, \rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\, \rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\, \rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\, \rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\, \rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\, \rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\, \rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\, \rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\, \rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\, \rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\, \rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\, \rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\, \rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\, \rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\, \rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\, \rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\, \rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\, \rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\, \rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\, \rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\, \rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\, \rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\, \rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\, \rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\, \rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\, \rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\, \rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\, \rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\, \rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\, \rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\, \rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\, \rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\, \rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\, \rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\, \rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\, \rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\, \rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\, \rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\, \rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\, \rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\, \rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\, \rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\, \rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\, \rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\, \rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\, \rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\, \rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\, \rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\, \rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\, \rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\, \rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\, \rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\, \rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\, \rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\, vsync => vsync, \y_int_reg[15]_0\(3) => U0_n_68, \y_int_reg[15]_0\(2) => U0_n_69, \y_int_reg[15]_0\(1) => U0_n_70, \y_int_reg[15]_0\(0) => U0_n_71, \y_int_reg[15]_1\(0) => U0_n_81, \y_int_reg[19]_0\(3) => U0_n_64, \y_int_reg[19]_0\(2) => U0_n_65, \y_int_reg[19]_0\(1) => U0_n_66, \y_int_reg[19]_0\(0) => U0_n_67, \y_int_reg[19]_1\(0) => U0_n_79, \y_int_reg[23]_0\(0) => U0_n_55, \y_int_reg[23]_1\(1) => U0_n_58, \y_int_reg[23]_1\(0) => U0_n_59, \y_int_reg[23]_2\(3) => U0_n_60, \y_int_reg[23]_2\(2) => U0_n_61, \y_int_reg[23]_2\(1) => U0_n_62, \y_int_reg[23]_2\(0) => U0_n_63, \y_int_reg[23]_3\(0) => U0_n_80, \y_int_reg[3]_0\(3) => U0_n_51, \y_int_reg[3]_0\(2) => U0_n_52, \y_int_reg[3]_0\(1) => U0_n_53, \y_int_reg[3]_0\(0) => U0_n_54, \y_int_reg[3]_1\(0) => U0_n_57, \y_int_reg[3]_2\(0) => U0_n_78, \y_int_reg[7]_0\(0) => U0_n_56 ); \cb_int[15]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[15]_i_32_n_4\, O => \cb_int[15]_i_35_n_0\ ); \cb_int[15]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[15]_i_32_n_5\, O => \cb_int[15]_i_36_n_0\ ); \cb_int[15]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[15]_i_32_n_6\, O => \cb_int[15]_i_37_n_0\ ); \cb_int[15]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[15]_i_32_n_7\, O => \cb_int[15]_i_38_n_0\ ); \cb_int[15]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[15]_i_39_n_0\ ); \cb_int[15]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[15]_i_40_n_0\ ); \cb_int[15]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[15]_i_41_n_0\ ); \cb_int[15]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[15]_i_42_n_0\ ); \cb_int[15]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[15]_i_47_n_0\ ); \cb_int[15]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[15]_i_48_n_0\ ); \cb_int[15]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[15]_i_49_n_0\ ); \cb_int[15]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[15]_i_50_n_0\ ); \cb_int[19]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[19]_i_38_n_0\ ); \cb_int[19]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[19]_i_39_n_0\ ); \cb_int[19]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[19]_i_40_n_0\ ); \cb_int[19]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[19]_i_41_n_0\ ); \cb_int[19]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[19]_i_42_n_0\ ); \cb_int[19]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[19]_i_43_n_0\ ); \cb_int[19]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[19]_i_44_n_0\ ); \cb_int[19]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[19]_i_45_n_0\ ); \cb_int[23]_i_33\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[23]_i_33_n_0\ ); \cb_int[23]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[23]_i_34_n_0\ ); \cb_int[23]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[23]_i_35_n_0\ ); \cb_int[23]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[23]_i_36_n_0\ ); \cb_int[23]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[23]_i_37_n_0\ ); \cb_int[23]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[23]_i_38_n_0\ ); \cb_int[23]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[23]_i_39_n_0\ ); \cb_int[23]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[23]_i_40_n_0\ ); \cb_int[31]_i_100\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(14), O => \cb_int[31]_i_100_n_0\ ); \cb_int[31]_i_101\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(13), O => \cb_int[31]_i_101_n_0\ ); \cb_int[31]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => U0_n_13, I1 => rgb888(7), O => \cb_int[31]_i_18_n_0\ ); \cb_int[31]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => U0_n_13, O => \cb_int[31]_i_19_n_0\ ); \cb_int[31]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => U0_n_13, O => \cb_int[31]_i_20_n_0\ ); \cb_int[31]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => U0_n_13, O => \cb_int[31]_i_21_n_0\ ); \cb_int[31]_i_22\: unisim.vcomponents.LUT3 generic map( INIT => X"95" ) port map ( I0 => rgb888(7), I1 => \cb_int[31]_i_52_n_0\, I2 => rgb888(6), O => \cb_int[31]_i_22_n_0\ ); \cb_int[31]_i_25\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \cb_int[31]_i_25_n_0\ ); \cb_int[31]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \cb_int[31]_i_26_n_0\ ); \cb_int[31]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_66_n_6\, O => \cb_int[31]_i_28_n_0\ ); \cb_int[31]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_66_n_7\, O => \cb_int[31]_i_29_n_0\ ); \cb_int[31]_i_45\: unisim.vcomponents.LUT5 generic map( INIT => X"99999996" ) port map ( I0 => \cb_int_reg[3]_i_43_n_1\, I1 => rgb888(4), I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), O => \cb_int[31]_i_45_n_0\ ); \cb_int[31]_i_46\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(2), I1 => rgb888(1), O => \cb_int[31]_i_46_n_0\ ); \cb_int[31]_i_47\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAA955555555" ) port map ( I0 => rgb888(6), I1 => rgb888(4), I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), I5 => rgb888(5), O => \cb_int[31]_i_47_n_0\ ); \cb_int[31]_i_48\: unisim.vcomponents.LUT6 generic map( INIT => X"CCCCCCC999999993" ) port map ( I0 => \cb_int_reg[3]_i_43_n_1\, I1 => rgb888(5), I2 => rgb888(3), I3 => rgb888(1), I4 => rgb888(2), I5 => rgb888(4), O => \cb_int[31]_i_48_n_0\ ); \cb_int[31]_i_49\: unisim.vcomponents.LUT5 generic map( INIT => X"AAA99995" ) port map ( I0 => rgb888(4), I1 => \cb_int_reg[3]_i_43_n_1\, I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), O => \cb_int[31]_i_49_n_0\ ); \cb_int[31]_i_50\: unisim.vcomponents.LUT4 generic map( INIT => X"6A95" ) port map ( I0 => \cb_int_reg[3]_i_43_n_1\, I1 => rgb888(2), I2 => rgb888(1), I3 => rgb888(3), O => \cb_int[31]_i_50_n_0\ ); \cb_int[31]_i_52\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => rgb888(4), I1 => rgb888(2), I2 => rgb888(1), I3 => rgb888(3), I4 => rgb888(5), O => \cb_int[31]_i_52_n_0\ ); \cb_int[31]_i_53\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000080000000" ) port map ( I0 => rgb888(14), I1 => rgb888(12), I2 => rgb888(10), I3 => rgb888(11), I4 => rgb888(13), I5 => rgb888(15), O => \cb_int[31]_i_53_n_0\ ); \cb_int[31]_i_54\: unisim.vcomponents.LUT6 generic map( INIT => X"000000006AAAAAAA" ) port map ( I0 => rgb888(14), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(15), O => \cb_int[31]_i_54_n_0\ ); \cb_int[31]_i_55\: unisim.vcomponents.LUT6 generic map( INIT => X"2BBBBBBBB2222222" ) port map ( I0 => \cb_int_reg[31]_i_85_n_0\, I1 => rgb888(15), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(13), O => \cb_int[31]_i_55_n_0\ ); \cb_int[31]_i_56\: unisim.vcomponents.LUT5 generic map( INIT => X"BFEA2A80" ) port map ( I0 => \cb_int_reg[31]_i_85_n_5\, I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(12), I4 => rgb888(14), O => \cb_int[31]_i_56_n_0\ ); \cb_int[31]_i_57\: unisim.vcomponents.LUT6 generic map( INIT => X"9555555555555555" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \cb_int[31]_i_57_n_0\ ); \cb_int[31]_i_58\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAABFFFFFFF" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \cb_int[31]_i_58_n_0\ ); \cb_int[31]_i_59\: unisim.vcomponents.LUT4 generic map( INIT => X"7E81" ) port map ( I0 => U0_n_6, I1 => \cb_int_reg[31]_i_85_n_0\, I2 => rgb888(15), I3 => U0_n_5, O => \cb_int[31]_i_59_n_0\ ); \cb_int[31]_i_60\: unisim.vcomponents.LUT6 generic map( INIT => X"E81717E817E8E817" ) port map ( I0 => rgb888(14), I1 => \cb_int[31]_i_88_n_0\, I2 => \cb_int_reg[31]_i_85_n_5\, I3 => U0_n_6, I4 => rgb888(15), I5 => \cb_int_reg[31]_i_85_n_0\, O => \cb_int[31]_i_60_n_0\ ); \cb_int[31]_i_62\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[23]_i_27_n_4\, O => \cb_int[31]_i_62_n_0\ ); \cb_int[31]_i_63\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[23]_i_27_n_5\, O => \cb_int[31]_i_63_n_0\ ); \cb_int[31]_i_64\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[23]_i_27_n_6\, O => \cb_int[31]_i_64_n_0\ ); \cb_int[31]_i_65\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[23]_i_27_n_7\, O => \cb_int[31]_i_65_n_0\ ); \cb_int[31]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[31]_i_83_n_0\ ); \cb_int[31]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[31]_i_84_n_0\ ); \cb_int[31]_i_88\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => rgb888(10), I1 => rgb888(11), I2 => rgb888(12), O => \cb_int[31]_i_88_n_0\ ); \cb_int[31]_i_89\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[19]_i_32_n_4\, O => \cb_int[31]_i_89_n_0\ ); \cb_int[31]_i_90\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[19]_i_32_n_5\, O => \cb_int[31]_i_90_n_0\ ); \cb_int[31]_i_91\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[19]_i_32_n_6\, O => \cb_int[31]_i_91_n_0\ ); \cb_int[31]_i_92\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[19]_i_32_n_7\, O => \cb_int[31]_i_92_n_0\ ); \cb_int[31]_i_93\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[31]_i_93_n_0\ ); \cb_int[31]_i_94\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[31]_i_94_n_0\ ); \cb_int[31]_i_99\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \cb_int[31]_i_99_n_0\ ); \cb_int[3]_i_35\: unisim.vcomponents.LUT4 generic map( INIT => X"BE28" ) port map ( I0 => \cb_int_reg[31]_i_85_n_6\, I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(13), O => \cb_int[3]_i_35_n_0\ ); \cb_int[3]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => rgb888(10), I1 => \cb_int_reg[31]_i_85_n_7\, I2 => rgb888(12), O => \cb_int[3]_i_36_n_0\ ); \cb_int[3]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int_reg[3]_i_68_n_4\, I1 => rgb888(9), I2 => rgb888(11), O => \cb_int[3]_i_37_n_0\ ); \cb_int[3]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int_reg[3]_i_68_n_4\, I1 => rgb888(9), I2 => rgb888(11), O => \cb_int[3]_i_38_n_0\ ); \cb_int[3]_i_39\: unisim.vcomponents.LUT6 generic map( INIT => X"9669696969969696" ) port map ( I0 => \cb_int[3]_i_35_n_0\, I1 => rgb888(14), I2 => rgb888(12), I3 => rgb888(11), I4 => rgb888(10), I5 => \cb_int_reg[31]_i_85_n_5\, O => \cb_int[3]_i_39_n_0\ ); \cb_int[3]_i_40\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \cb_int_reg[31]_i_85_n_6\, I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(13), I4 => \cb_int[3]_i_36_n_0\, O => \cb_int[3]_i_40_n_0\ ); \cb_int[3]_i_41\: unisim.vcomponents.LUT6 generic map( INIT => X"E81717E817E8E817" ) port map ( I0 => rgb888(11), I1 => rgb888(9), I2 => \cb_int_reg[3]_i_68_n_4\, I3 => rgb888(12), I4 => rgb888(10), I5 => \cb_int_reg[31]_i_85_n_7\, O => \cb_int[3]_i_41_n_0\ ); \cb_int[3]_i_42\: unisim.vcomponents.LUT5 generic map( INIT => X"69969696" ) port map ( I0 => rgb888(11), I1 => rgb888(9), I2 => \cb_int_reg[3]_i_68_n_4\, I3 => rgb888(10), I4 => rgb888(8), O => \cb_int[3]_i_42_n_0\ ); \cb_int[3]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_19_n_6\, O => \cb_int[3]_i_59_n_0\ ); \cb_int[3]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_19_n_7\, O => \cb_int[3]_i_60_n_0\ ); \cb_int[3]_i_61\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_9, O => \cb_int[3]_i_61_n_0\ ); \cb_int[3]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_10, O => \cb_int[3]_i_62_n_0\ ); \cb_int[3]_i_73\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(7), O => \cb_int[3]_i_73_n_0\ ); \cb_int[3]_i_74\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(6), O => \cb_int[3]_i_74_n_0\ ); \cb_int[3]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(8), O => \cb_int[3]_i_84_n_0\ ); \cb_int[3]_i_85\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_11, O => \cb_int[3]_i_85_n_0\ ); \cb_int[3]_i_86\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_12, O => \cb_int[3]_i_86_n_0\ ); \cb_int[3]_i_87\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_7, O => \cb_int[3]_i_87_n_0\ ); \cb_int[3]_i_88\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_8, O => \cb_int[3]_i_88_n_0\ ); \cb_int[3]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(12), I1 => rgb888(15), O => \cb_int[3]_i_95_n_0\ ); \cb_int[3]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(11), I1 => rgb888(14), O => \cb_int[3]_i_96_n_0\ ); \cb_int[3]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(10), I1 => rgb888(13), O => \cb_int[3]_i_97_n_0\ ); \cb_int[3]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(9), I1 => rgb888(12), O => \cb_int[3]_i_98_n_0\ ); \cb_int[7]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[7]_i_24_n_4\, O => \cb_int[7]_i_30_n_0\ ); \cb_int[7]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_24_n_5\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_9_n_7\, O => \cb_int[7]_i_31_n_0\ ); \cb_int[7]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_24_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_23_n_4\, O => \cb_int[7]_i_32_n_0\ ); \cb_int[7]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_24_n_7\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_23_n_5\, O => \cb_int[7]_i_33_n_0\ ); \cb_int[7]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[7]_i_34_n_0\ ); \cb_int[7]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_7\, O => \cb_int[7]_i_35_n_0\ ); \cb_int[7]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_23_n_4\, O => \cb_int[7]_i_36_n_0\ ); \cb_int[7]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_23_n_5\, O => \cb_int[7]_i_37_n_0\ ); \cb_int[7]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[3]_i_32_n_4\, I1 => U0_n_16, I2 => \cb_int_reg[3]_i_19_n_6\, O => \cb_int[7]_i_43_n_0\ ); \cb_int[7]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_27_n_4\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_23_n_6\, O => \cb_int[7]_i_44_n_0\ ); \cb_int[7]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_27_n_5\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_23_n_7\, O => \cb_int[7]_i_45_n_0\ ); \cb_int[7]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_27_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[3]_i_19_n_4\, O => \cb_int[7]_i_46_n_0\ ); \cb_int[7]_i_47\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_27_n_7\, I1 => U0_n_16, I2 => \cb_int_reg[3]_i_19_n_5\, O => \cb_int[7]_i_47_n_0\ ); \cb_int[7]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_23_n_6\, O => \cb_int[7]_i_48_n_0\ ); \cb_int[7]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_23_n_7\, O => \cb_int[7]_i_49_n_0\ ); \cb_int[7]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_19_n_4\, O => \cb_int[7]_i_50_n_0\ ); \cb_int[7]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_19_n_5\, O => \cb_int[7]_i_51_n_0\ ); \cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_23_n_0\, CO(3) => \cb_int_reg[15]_i_31_n_0\, CO(2) => \cb_int_reg[15]_i_31_n_1\, CO(1) => \cb_int_reg[15]_i_31_n_2\, CO(0) => \cb_int_reg[15]_i_31_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[15]_i_31_n_4\, O(2) => \cb_int_reg[15]_i_31_n_5\, O(1) => \cb_int_reg[15]_i_31_n_6\, O(0) => \cb_int_reg[15]_i_31_n_7\, S(3) => \cb_int[15]_i_35_n_0\, S(2) => \cb_int[15]_i_36_n_0\, S(1) => \cb_int[15]_i_37_n_0\, S(0) => \cb_int[15]_i_38_n_0\ ); \cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_24_n_0\, CO(3) => \cb_int_reg[15]_i_32_n_0\, CO(2) => \cb_int_reg[15]_i_32_n_1\, CO(1) => \cb_int_reg[15]_i_32_n_2\, CO(0) => \cb_int_reg[15]_i_32_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[15]_i_32_n_4\, O(2) => \cb_int_reg[15]_i_32_n_5\, O(1) => \cb_int_reg[15]_i_32_n_6\, O(0) => \cb_int_reg[15]_i_32_n_7\, S(3) => \cb_int[15]_i_39_n_0\, S(2) => \cb_int[15]_i_40_n_0\, S(1) => \cb_int[15]_i_41_n_0\, S(0) => \cb_int[15]_i_42_n_0\ ); \cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_76, CO(3) => \cb_int_reg[15]_i_34_n_0\, CO(2) => \cb_int_reg[15]_i_34_n_1\, CO(1) => \cb_int_reg[15]_i_34_n_2\, CO(0) => \cb_int_reg[15]_i_34_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[15]_i_34_n_4\, O(2) => \cb_int_reg[15]_i_34_n_5\, O(1) => \cb_int_reg[15]_i_34_n_6\, O(0) => \cb_int_reg[15]_i_34_n_7\, S(3) => \cb_int[15]_i_47_n_0\, S(2) => \cb_int[15]_i_48_n_0\, S(1) => \cb_int[15]_i_49_n_0\, S(0) => \cb_int[15]_i_50_n_0\ ); \cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_32_n_0\, CO(3) => \cb_int_reg[19]_i_32_n_0\, CO(2) => \cb_int_reg[19]_i_32_n_1\, CO(1) => \cb_int_reg[19]_i_32_n_2\, CO(0) => \cb_int_reg[19]_i_32_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[19]_i_32_n_4\, O(2) => \cb_int_reg[19]_i_32_n_5\, O(1) => \cb_int_reg[19]_i_32_n_6\, O(0) => \cb_int_reg[19]_i_32_n_7\, S(3) => \cb_int[19]_i_38_n_0\, S(2) => \cb_int[19]_i_39_n_0\, S(1) => \cb_int[19]_i_40_n_0\, S(0) => \cb_int[19]_i_41_n_0\ ); \cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_34_n_0\, CO(3) => \cb_int_reg[19]_i_33_n_0\, CO(2) => \cb_int_reg[19]_i_33_n_1\, CO(1) => \cb_int_reg[19]_i_33_n_2\, CO(0) => \cb_int_reg[19]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[19]_i_33_n_4\, O(2) => \cb_int_reg[19]_i_33_n_5\, O(1) => \cb_int_reg[19]_i_33_n_6\, O(0) => \cb_int_reg[19]_i_33_n_7\, S(3) => \cb_int[19]_i_42_n_0\, S(2) => \cb_int[19]_i_43_n_0\, S(1) => \cb_int[19]_i_44_n_0\, S(0) => \cb_int[19]_i_45_n_0\ ); \cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_32_n_0\, CO(3) => \cb_int_reg[23]_i_27_n_0\, CO(2) => \cb_int_reg[23]_i_27_n_1\, CO(1) => \cb_int_reg[23]_i_27_n_2\, CO(0) => \cb_int_reg[23]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[23]_i_27_n_4\, O(2) => \cb_int_reg[23]_i_27_n_5\, O(1) => \cb_int_reg[23]_i_27_n_6\, O(0) => \cb_int_reg[23]_i_27_n_7\, S(3) => \cb_int[23]_i_33_n_0\, S(2) => \cb_int[23]_i_34_n_0\, S(1) => \cb_int[23]_i_35_n_0\, S(0) => \cb_int[23]_i_36_n_0\ ); \cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_33_n_0\, CO(3) => \cb_int_reg[23]_i_28_n_0\, CO(2) => \cb_int_reg[23]_i_28_n_1\, CO(1) => \cb_int_reg[23]_i_28_n_2\, CO(0) => \cb_int_reg[23]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[23]_i_28_n_4\, O(2) => \cb_int_reg[23]_i_28_n_5\, O(1) => \cb_int_reg[23]_i_28_n_6\, O(0) => \cb_int_reg[23]_i_28_n_7\, S(3) => \cb_int[23]_i_37_n_0\, S(2) => \cb_int[23]_i_38_n_0\, S(1) => \cb_int[23]_i_39_n_0\, S(0) => \cb_int[23]_i_40_n_0\ ); \cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_27_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_10_n_1\, CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[31]_i_10_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_10_n_6\, O(0) => \cb_int_reg[31]_i_10_n_7\, S(3 downto 2) => B"01", S(1) => \cb_int[31]_i_28_n_0\, S(0) => \cb_int[31]_i_29_n_0\ ); \cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_75, CO(3) => \cb_int_reg[31]_i_17_n_0\, CO(2) => \cb_int_reg[31]_i_17_n_1\, CO(1) => \cb_int_reg[31]_i_17_n_2\, CO(0) => \cb_int_reg[31]_i_17_n_3\, CYINIT => '0', DI(3) => U0_n_14, DI(2) => U0_n_15, DI(1) => \cb_int[31]_i_45_n_0\, DI(0) => \cb_int[31]_i_46_n_0\, O(3) => \cb_int_reg[31]_i_17_n_4\, O(2) => \cb_int_reg[31]_i_17_n_5\, O(1) => \cb_int_reg[31]_i_17_n_6\, O(0) => \cb_int_reg[31]_i_17_n_7\, S(3) => \cb_int[31]_i_47_n_0\, S(2) => \cb_int[31]_i_48_n_0\, S(1) => \cb_int[31]_i_49_n_0\, S(0) => \cb_int[31]_i_50_n_0\ ); \cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_19_n_0\, CO(3) => \cb_int_reg[31]_i_23_n_0\, CO(2) => \cb_int_reg[31]_i_23_n_1\, CO(1) => \cb_int_reg[31]_i_23_n_2\, CO(0) => \cb_int_reg[31]_i_23_n_3\, CYINIT => '0', DI(3) => \cb_int[31]_i_53_n_0\, DI(2) => \cb_int[31]_i_54_n_0\, DI(1) => \cb_int[31]_i_55_n_0\, DI(0) => \cb_int[31]_i_56_n_0\, O(3) => \cb_int_reg[31]_i_23_n_4\, O(2) => \cb_int_reg[31]_i_23_n_5\, O(1) => \cb_int_reg[31]_i_23_n_6\, O(0) => \cb_int_reg[31]_i_23_n_7\, S(3) => \cb_int[31]_i_57_n_0\, S(2) => \cb_int[31]_i_58_n_0\, S(1) => \cb_int[31]_i_59_n_0\, S(0) => \cb_int[31]_i_60_n_0\ ); \cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_61_n_0\, CO(3) => \cb_int_reg[31]_i_27_n_0\, CO(2) => \cb_int_reg[31]_i_27_n_1\, CO(1) => \cb_int_reg[31]_i_27_n_2\, CO(0) => \cb_int_reg[31]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[31]_i_27_n_4\, O(2) => \cb_int_reg[31]_i_27_n_5\, O(1) => \cb_int_reg[31]_i_27_n_6\, O(0) => \cb_int_reg[31]_i_27_n_7\, S(3) => \cb_int[31]_i_62_n_0\, S(2) => \cb_int[31]_i_63_n_0\, S(1) => \cb_int[31]_i_64_n_0\, S(0) => \cb_int[31]_i_65_n_0\ ); \cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[23]_i_28_n_0\, CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1), CO(0) => \cb_int_reg[31]_i_42_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_42_n_6\, O(0) => \cb_int_reg[31]_i_42_n_7\, S(3 downto 2) => B"00", S(1) => \cb_int[31]_i_83_n_0\, S(0) => \cb_int[31]_i_84_n_0\ ); \cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_31_n_0\, CO(3) => \cb_int_reg[31]_i_61_n_0\, CO(2) => \cb_int_reg[31]_i_61_n_1\, CO(1) => \cb_int_reg[31]_i_61_n_2\, CO(0) => \cb_int_reg[31]_i_61_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[31]_i_61_n_4\, O(2) => \cb_int_reg[31]_i_61_n_5\, O(1) => \cb_int_reg[31]_i_61_n_6\, O(0) => \cb_int_reg[31]_i_61_n_7\, S(3) => \cb_int[31]_i_89_n_0\, S(2) => \cb_int[31]_i_90_n_0\, S(1) => \cb_int[31]_i_91_n_0\, S(0) => \cb_int[31]_i_92_n_0\ ); \cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[23]_i_27_n_0\, CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1), CO(0) => \cb_int_reg[31]_i_66_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_66_n_6\, O(0) => \cb_int_reg[31]_i_66_n_7\, S(3 downto 2) => B"00", S(1) => \cb_int[31]_i_93_n_0\, S(0) => \cb_int[31]_i_94_n_0\ ); \cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_17_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_8_n_1\, CO(1) => \cb_int_reg[31]_i_8_n_2\, CO(0) => \cb_int_reg[31]_i_8_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \cb_int[31]_i_18_n_0\, O(3) => \cb_int_reg[31]_i_8_n_4\, O(2) => \cb_int_reg[31]_i_8_n_5\, O(1) => \cb_int_reg[31]_i_8_n_6\, O(0) => \cb_int_reg[31]_i_8_n_7\, S(3) => \cb_int[31]_i_19_n_0\, S(2) => \cb_int[31]_i_20_n_0\, S(1) => \cb_int[31]_i_21_n_0\, S(0) => \cb_int[31]_i_22_n_0\ ); \cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_68_n_0\, CO(3) => \cb_int_reg[31]_i_85_n_0\, CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2), CO(1) => \cb_int_reg[31]_i_85_n_2\, CO(0) => \cb_int_reg[31]_i_85_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 1) => rgb888(15 downto 14), DI(0) => '0', O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3), O(2) => \cb_int_reg[31]_i_85_n_5\, O(1) => \cb_int_reg[31]_i_85_n_6\, O(0) => \cb_int_reg[31]_i_85_n_7\, S(3) => '1', S(2) => \cb_int[31]_i_99_n_0\, S(1) => \cb_int[31]_i_100_n_0\, S(0) => \cb_int[31]_i_101_n_0\ ); \cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_23_n_0\, CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1), CO(0) => \cb_int_reg[31]_i_9_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => U0_n_4, O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_9_n_6\, O(0) => \cb_int_reg[31]_i_9_n_7\, S(3 downto 2) => B"00", S(1) => \cb_int[31]_i_25_n_0\, S(0) => \cb_int[31]_i_26_n_0\ ); \cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_73, CO(3) => \cb_int_reg[3]_i_19_n_0\, CO(2) => \cb_int_reg[3]_i_19_n_1\, CO(1) => \cb_int_reg[3]_i_19_n_2\, CO(0) => \cb_int_reg[3]_i_19_n_3\, CYINIT => '0', DI(3) => \cb_int[3]_i_35_n_0\, DI(2) => \cb_int[3]_i_36_n_0\, DI(1) => \cb_int[3]_i_37_n_0\, DI(0) => \cb_int[3]_i_38_n_0\, O(3) => \cb_int_reg[3]_i_19_n_4\, O(2) => \cb_int_reg[3]_i_19_n_5\, O(1) => \cb_int_reg[3]_i_19_n_6\, O(0) => \cb_int_reg[3]_i_19_n_7\, S(3) => \cb_int[3]_i_39_n_0\, S(2) => \cb_int[3]_i_40_n_0\, S(1) => \cb_int[3]_i_41_n_0\, S(0) => \cb_int[3]_i_42_n_0\ ); \cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_58_n_0\, CO(3) => \cb_int_reg[3]_i_32_n_0\, CO(2) => \cb_int_reg[3]_i_32_n_1\, CO(1) => \cb_int_reg[3]_i_32_n_2\, CO(0) => \cb_int_reg[3]_i_32_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[3]_i_32_n_4\, O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0), S(3) => \cb_int[3]_i_59_n_0\, S(2) => \cb_int[3]_i_60_n_0\, S(1) => \cb_int[3]_i_61_n_0\, S(0) => \cb_int[3]_i_62_n_0\ ); \cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_74, CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[3]_i_43_n_1\, CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[3]_i_43_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => rgb888(7), DI(0) => '0', O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[3]_i_43_n_6\, O(0) => \cb_int_reg[3]_i_43_n_7\, S(3 downto 2) => B"01", S(1) => \cb_int[3]_i_73_n_0\, S(0) => \cb_int[3]_i_74_n_0\ ); \cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_58_n_0\, CO(2) => \cb_int_reg[3]_i_58_n_1\, CO(1) => \cb_int_reg[3]_i_58_n_2\, CO(0) => \cb_int_reg[3]_i_58_n_3\, CYINIT => \cb_int[3]_i_84_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[3]_i_85_n_0\, S(2) => \cb_int[3]_i_86_n_0\, S(1) => \cb_int[3]_i_87_n_0\, S(0) => \cb_int[3]_i_88_n_0\ ); \cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_72, CO(3) => \cb_int_reg[3]_i_68_n_0\, CO(2) => \cb_int_reg[3]_i_68_n_1\, CO(1) => \cb_int_reg[3]_i_68_n_2\, CO(0) => \cb_int_reg[3]_i_68_n_3\, CYINIT => '0', DI(3 downto 0) => rgb888(12 downto 9), O(3) => \cb_int_reg[3]_i_68_n_4\, O(2) => \cb_int_reg[3]_i_68_n_5\, O(1) => \cb_int_reg[3]_i_68_n_6\, O(0) => \cb_int_reg[3]_i_68_n_7\, S(3) => \cb_int[3]_i_95_n_0\, S(2) => \cb_int[3]_i_96_n_0\, S(1) => \cb_int[3]_i_97_n_0\, S(0) => \cb_int[3]_i_98_n_0\ ); \cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_26_n_0\, CO(3) => \cb_int_reg[7]_i_23_n_0\, CO(2) => \cb_int_reg[7]_i_23_n_1\, CO(1) => \cb_int_reg[7]_i_23_n_2\, CO(0) => \cb_int_reg[7]_i_23_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_23_n_4\, O(2) => \cb_int_reg[7]_i_23_n_5\, O(1) => \cb_int_reg[7]_i_23_n_6\, O(0) => \cb_int_reg[7]_i_23_n_7\, S(3) => \cb_int[7]_i_30_n_0\, S(2) => \cb_int[7]_i_31_n_0\, S(1) => \cb_int[7]_i_32_n_0\, S(0) => \cb_int[7]_i_33_n_0\ ); \cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_27_n_0\, CO(3) => \cb_int_reg[7]_i_24_n_0\, CO(2) => \cb_int_reg[7]_i_24_n_1\, CO(1) => \cb_int_reg[7]_i_24_n_2\, CO(0) => \cb_int_reg[7]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_24_n_4\, O(2) => \cb_int_reg[7]_i_24_n_5\, O(1) => \cb_int_reg[7]_i_24_n_6\, O(0) => \cb_int_reg[7]_i_24_n_7\, S(3) => \cb_int[7]_i_34_n_0\, S(2) => \cb_int[7]_i_35_n_0\, S(1) => \cb_int[7]_i_36_n_0\, S(0) => \cb_int[7]_i_37_n_0\ ); \cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[7]_i_26_n_0\, CO(2) => \cb_int_reg[7]_i_26_n_1\, CO(1) => \cb_int_reg[7]_i_26_n_2\, CO(0) => \cb_int_reg[7]_i_26_n_3\, CYINIT => \cb_int[7]_i_43_n_0\, DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_26_n_4\, O(2) => \cb_int_reg[7]_i_26_n_5\, O(1) => \cb_int_reg[7]_i_26_n_6\, O(0) => \cb_int_reg[7]_i_26_n_7\, S(3) => \cb_int[7]_i_44_n_0\, S(2) => \cb_int[7]_i_45_n_0\, S(1) => \cb_int[7]_i_46_n_0\, S(0) => \cb_int[7]_i_47_n_0\ ); \cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_32_n_0\, CO(3) => \cb_int_reg[7]_i_27_n_0\, CO(2) => \cb_int_reg[7]_i_27_n_1\, CO(1) => \cb_int_reg[7]_i_27_n_2\, CO(0) => \cb_int_reg[7]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_27_n_4\, O(2) => \cb_int_reg[7]_i_27_n_5\, O(1) => \cb_int_reg[7]_i_27_n_6\, O(0) => \cb_int_reg[7]_i_27_n_7\, S(3) => \cb_int[7]_i_48_n_0\, S(2) => \cb_int[7]_i_49_n_0\, S(1) => \cb_int[7]_i_50_n_0\, S(0) => \cb_int[7]_i_51_n_0\ ); \cr_int[11]_i_61\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_35, O => \cr_int[11]_i_61_n_0\ ); \cr_int[11]_i_62\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_36, I1 => U0_n_26, I2 => U0_n_18, O => \cr_int[11]_i_62_n_0\ ); \cr_int[11]_i_63\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_37, I1 => U0_n_26, I2 => U0_n_19, O => \cr_int[11]_i_63_n_0\ ); \cr_int[11]_i_64\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_30, I1 => U0_n_26, I2 => U0_n_20, O => \cr_int[11]_i_64_n_0\ ); \cr_int[15]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_39, O => \cr_int[15]_i_44_n_0\ ); \cr_int[15]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_40, O => \cr_int[15]_i_45_n_0\ ); \cr_int[15]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_41, O => \cr_int[15]_i_46_n_0\ ); \cr_int[15]_i_47\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_34, O => \cr_int[15]_i_47_n_0\ ); \cr_int[15]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[15]_i_52_n_0\ ); \cr_int[15]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[15]_i_53_n_0\ ); \cr_int[15]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[15]_i_54_n_0\ ); \cr_int[15]_i_55\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[15]_i_55_n_0\ ); \cr_int[19]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[19]_i_42_n_0\ ); \cr_int[19]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[19]_i_43_n_0\ ); \cr_int[19]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[19]_i_44_n_0\ ); \cr_int[19]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[19]_i_45_n_0\ ); \cr_int[23]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[23]_i_32_n_0\ ); \cr_int[23]_i_33\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[23]_i_33_n_0\ ); \cr_int[23]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[23]_i_34_n_0\ ); \cr_int[23]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[23]_i_35_n_0\ ); \cr_int[31]_i_104\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_43, O => \cr_int[31]_i_104_n_0\ ); \cr_int[31]_i_105\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_44, O => \cr_int[31]_i_105_n_0\ ); \cr_int[31]_i_106\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_45, O => \cr_int[31]_i_106_n_0\ ); \cr_int[31]_i_107\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_38, O => \cr_int[31]_i_107_n_0\ ); \cr_int[31]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_50, O => \cr_int[31]_i_28_n_0\ ); \cr_int[31]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_46, O => \cr_int[31]_i_29_n_0\ ); \cr_int[31]_i_65\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_47, O => \cr_int[31]_i_65_n_0\ ); \cr_int[31]_i_66\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_48, O => \cr_int[31]_i_66_n_0\ ); \cr_int[31]_i_67\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_49, O => \cr_int[31]_i_67_n_0\ ); \cr_int[31]_i_68\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_42, O => \cr_int[31]_i_68_n_0\ ); \cr_int[31]_i_98\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[31]_i_98_n_0\ ); \cr_int[31]_i_99\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[31]_i_99_n_0\ ); \cr_int[7]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_28, I1 => U0_n_26, I2 => U0_n_25, O => \cr_int[7]_i_29_n_0\ ); \cr_int[7]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_31, I1 => U0_n_26, I2 => U0_n_21, O => \cr_int[7]_i_30_n_0\ ); \cr_int[7]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_32, I1 => U0_n_26, I2 => U0_n_22, O => \cr_int[7]_i_31_n_0\ ); \cr_int[7]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_33, I1 => U0_n_26, I2 => U0_n_23, O => \cr_int[7]_i_32_n_0\ ); \cr_int[7]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_27, I1 => U0_n_26, I2 => U0_n_24, O => \cr_int[7]_i_33_n_0\ ); \cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[7]_i_24_n_0\, CO(3) => \cr_int_reg[11]_i_28_n_0\, CO(2) => \cr_int_reg[11]_i_28_n_1\, CO(1) => \cr_int_reg[11]_i_28_n_2\, CO(0) => \cr_int_reg[11]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_28_n_4\, O(2) => \cr_int_reg[11]_i_28_n_5\, O(1) => \cr_int_reg[11]_i_28_n_6\, O(0) => \cr_int_reg[11]_i_28_n_7\, S(3) => \cr_int[11]_i_61_n_0\, S(2) => \cr_int[11]_i_62_n_0\, S(1) => \cr_int[11]_i_63_n_0\, S(0) => \cr_int[11]_i_64_n_0\ ); \cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_28_n_0\, CO(3) => \cr_int_reg[15]_i_37_n_0\, CO(2) => \cr_int_reg[15]_i_37_n_1\, CO(1) => \cr_int_reg[15]_i_37_n_2\, CO(0) => \cr_int_reg[15]_i_37_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[15]_i_37_n_4\, O(2) => \cr_int_reg[15]_i_37_n_5\, O(1) => \cr_int_reg[15]_i_37_n_6\, O(0) => \cr_int_reg[15]_i_37_n_7\, S(3) => \cr_int[15]_i_44_n_0\, S(2) => \cr_int[15]_i_45_n_0\, S(1) => \cr_int[15]_i_46_n_0\, S(0) => \cr_int[15]_i_47_n_0\ ); \cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_77, CO(3) => \cr_int_reg[15]_i_39_n_0\, CO(2) => \cr_int_reg[15]_i_39_n_1\, CO(1) => \cr_int_reg[15]_i_39_n_2\, CO(0) => \cr_int_reg[15]_i_39_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[15]_i_39_n_4\, O(2) => \cr_int_reg[15]_i_39_n_5\, O(1) => \cr_int_reg[15]_i_39_n_6\, O(0) => \cr_int_reg[15]_i_39_n_7\, S(3) => \cr_int[15]_i_52_n_0\, S(2) => \cr_int[15]_i_53_n_0\, S(1) => \cr_int[15]_i_54_n_0\, S(0) => \cr_int[15]_i_55_n_0\ ); \cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_39_n_0\, CO(3) => \cr_int_reg[19]_i_37_n_0\, CO(2) => \cr_int_reg[19]_i_37_n_1\, CO(1) => \cr_int_reg[19]_i_37_n_2\, CO(0) => \cr_int_reg[19]_i_37_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[19]_i_37_n_4\, O(2) => \cr_int_reg[19]_i_37_n_5\, O(1) => \cr_int_reg[19]_i_37_n_6\, O(0) => \cr_int_reg[19]_i_37_n_7\, S(3) => \cr_int[19]_i_42_n_0\, S(2) => \cr_int[19]_i_43_n_0\, S(1) => \cr_int[19]_i_44_n_0\, S(0) => \cr_int[19]_i_45_n_0\ ); \cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_37_n_0\, CO(3) => \cr_int_reg[23]_i_31_n_0\, CO(2) => \cr_int_reg[23]_i_31_n_1\, CO(1) => \cr_int_reg[23]_i_31_n_2\, CO(0) => \cr_int_reg[23]_i_31_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[23]_i_31_n_4\, O(2) => \cr_int_reg[23]_i_31_n_5\, O(1) => \cr_int_reg[23]_i_31_n_6\, O(0) => \cr_int_reg[23]_i_31_n_7\, S(3) => \cr_int[23]_i_32_n_0\, S(2) => \cr_int[23]_i_33_n_0\, S(1) => \cr_int[23]_i_34_n_0\, S(0) => \cr_int[23]_i_35_n_0\ ); \cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_27_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_10_n_1\, CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[31]_i_10_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[31]_i_10_n_6\, O(0) => \cr_int_reg[31]_i_10_n_7\, S(3 downto 2) => B"01", S(1) => \cr_int[31]_i_28_n_0\, S(0) => \cr_int[31]_i_29_n_0\ ); \cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_64_n_0\, CO(3) => \cr_int_reg[31]_i_27_n_0\, CO(2) => \cr_int_reg[31]_i_27_n_1\, CO(1) => \cr_int_reg[31]_i_27_n_2\, CO(0) => \cr_int_reg[31]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[31]_i_27_n_4\, O(2) => \cr_int_reg[31]_i_27_n_5\, O(1) => \cr_int_reg[31]_i_27_n_6\, O(0) => \cr_int_reg[31]_i_27_n_7\, S(3) => \cr_int[31]_i_65_n_0\, S(2) => \cr_int[31]_i_66_n_0\, S(1) => \cr_int[31]_i_67_n_0\, S(0) => \cr_int[31]_i_68_n_0\ ); \cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[23]_i_31_n_0\, CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1), CO(0) => \cr_int_reg[31]_i_54_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[31]_i_54_n_6\, O(0) => \cr_int_reg[31]_i_54_n_7\, S(3 downto 2) => B"00", S(1) => \cr_int[31]_i_98_n_0\, S(0) => \cr_int[31]_i_99_n_0\ ); \cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_37_n_0\, CO(3) => \cr_int_reg[31]_i_64_n_0\, CO(2) => \cr_int_reg[31]_i_64_n_1\, CO(1) => \cr_int_reg[31]_i_64_n_2\, CO(0) => \cr_int_reg[31]_i_64_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[31]_i_64_n_4\, O(2) => \cr_int_reg[31]_i_64_n_5\, O(1) => \cr_int_reg[31]_i_64_n_6\, O(0) => \cr_int_reg[31]_i_64_n_7\, S(3) => \cr_int[31]_i_104_n_0\, S(2) => \cr_int[31]_i_105_n_0\, S(1) => \cr_int[31]_i_106_n_0\, S(0) => \cr_int[31]_i_107_n_0\ ); \cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[7]_i_24_n_0\, CO(2) => \cr_int_reg[7]_i_24_n_1\, CO(1) => \cr_int_reg[7]_i_24_n_2\, CO(0) => \cr_int_reg[7]_i_24_n_3\, CYINIT => \cr_int[7]_i_29_n_0\, DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[7]_i_24_n_4\, O(2) => \cr_int_reg[7]_i_24_n_5\, O(1) => \cr_int_reg[7]_i_24_n_6\, O(0) => \cr_int_reg[7]_i_24_n_7\, S(3) => \cr_int[7]_i_30_n_0\, S(2) => \cr_int[7]_i_31_n_0\, S(1) => \cr_int[7]_i_32_n_0\, S(0) => \cr_int[7]_i_33_n_0\ ); \y_int[11]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[11]_i_54_n_0\ ); \y_int[11]_i_55\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_6\, O => \y_int[11]_i_55_n_0\ ); \y_int[11]_i_56\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_7\, O => \y_int[11]_i_56_n_0\ ); \y_int[11]_i_57\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_21_n_4\, O => \y_int[11]_i_57_n_0\ ); \y_int[15]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[15]_i_36_n_0\ ); \y_int[15]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[15]_i_37_n_0\ ); \y_int[15]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[15]_i_38_n_0\ ); \y_int[15]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[15]_i_39_n_0\ ); \y_int[15]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_68, O => \y_int[15]_i_44_n_0\ ); \y_int[15]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_69, O => \y_int[15]_i_45_n_0\ ); \y_int[15]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_70, O => \y_int[15]_i_46_n_0\ ); \y_int[15]_i_47\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_71, O => \y_int[15]_i_47_n_0\ ); \y_int[19]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[19]_i_36_n_0\ ); \y_int[19]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[19]_i_37_n_0\ ); \y_int[19]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[19]_i_38_n_0\ ); \y_int[19]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[19]_i_39_n_0\ ); \y_int[19]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[19]_i_24_n_5\, O => \y_int[19]_i_40_n_0\ ); \y_int[19]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[19]_i_24_n_6\, O => \y_int[19]_i_41_n_0\ ); \y_int[19]_i_42\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[19]_i_24_n_7\, O => \y_int[19]_i_42_n_0\ ); \y_int[19]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[15]_i_24_n_4\, O => \y_int[19]_i_43_n_0\ ); \y_int[19]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_64, O => \y_int[19]_i_44_n_0\ ); \y_int[19]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_65, O => \y_int[19]_i_45_n_0\ ); \y_int[19]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_66, O => \y_int[19]_i_46_n_0\ ); \y_int[19]_i_47\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_67, O => \y_int[19]_i_47_n_0\ ); \y_int[23]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_50_n_0\ ); \y_int[23]_i_58\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_58_n_0\ ); \y_int[23]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_59_n_0\ ); \y_int[23]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_60_n_0\ ); \y_int[23]_i_61\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_61_n_0\ ); \y_int[31]_i_100\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => rgb888(3), I1 => rgb888(1), I2 => rgb888(4), I3 => rgb888(2), O => \y_int[31]_i_100_n_0\ ); \y_int[31]_i_102\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \y_int[31]_i_102_n_0\ ); \y_int[31]_i_103\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(15), I1 => rgb888(14), O => \y_int[31]_i_103_n_0\ ); \y_int[31]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(15), I1 => \y_int[31]_i_56_n_0\, O => \y_int[31]_i_22_n_0\ ); \y_int[31]_i_23\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => rgb888(15), I1 => \y_int[31]_i_57_n_0\, I2 => rgb888(14), O => \y_int[31]_i_23_n_0\ ); \y_int[31]_i_24\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(15), I1 => \y_int[31]_i_56_n_0\, O => \y_int[31]_i_24_n_0\ ); \y_int[31]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \y_int[31]_i_25_n_0\ ); \y_int[31]_i_26\: unisim.vcomponents.LUT3 generic map( INIT => X"15" ) port map ( I0 => rgb888(15), I1 => rgb888(14), I2 => \y_int[31]_i_57_n_0\, O => \y_int[31]_i_26_n_0\ ); \y_int[31]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_32_n_7\, O => \y_int[31]_i_28_n_0\ ); \y_int[31]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_35_n_4\, O => \y_int[31]_i_29_n_0\ ); \y_int[31]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_58, O => \y_int[31]_i_38_n_0\ ); \y_int[31]_i_39\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_59, O => \y_int[31]_i_39_n_0\ ); \y_int[31]_i_48\: unisim.vcomponents.LUT4 generic map( INIT => X"1002" ) port map ( I0 => rgb888(14), I1 => rgb888(15), I2 => \y_int[31]_i_80_n_0\, I3 => rgb888(13), O => \y_int[31]_i_48_n_0\ ); \y_int[31]_i_49\: unisim.vcomponents.LUT5 generic map( INIT => X"81560042" ) port map ( I0 => rgb888(13), I1 => rgb888(12), I2 => \y_int[31]_i_81_n_0\, I3 => rgb888(15), I4 => \y_int_reg[31]_i_82_n_1\, O => \y_int[31]_i_49_n_0\ ); \y_int[31]_i_50\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A88A80808008" ) port map ( I0 => \y_int[31]_i_83_n_0\, I1 => rgb888(14), I2 => rgb888(11), I3 => rgb888(9), I4 => rgb888(10), I5 => \y_int_reg[31]_i_82_n_6\, O => \y_int[31]_i_50_n_0\ ); \y_int[31]_i_51\: unisim.vcomponents.LUT6 generic map( INIT => X"9696966996000069" ) port map ( I0 => rgb888(14), I1 => rgb888(11), I2 => \y_int_reg[31]_i_82_n_6\, I3 => rgb888(9), I4 => rgb888(10), I5 => rgb888(13), O => \y_int[31]_i_51_n_0\ ); \y_int[31]_i_52\: unisim.vcomponents.LUT4 generic map( INIT => X"6559" ) port map ( I0 => \y_int[31]_i_48_n_0\, I1 => rgb888(15), I2 => \y_int[31]_i_57_n_0\, I3 => rgb888(14), O => \y_int[31]_i_52_n_0\ ); \y_int[31]_i_53\: unisim.vcomponents.LUT6 generic map( INIT => X"6CCCCCC9CCCCC993" ) port map ( I0 => \y_int_reg[31]_i_82_n_1\, I1 => rgb888(14), I2 => rgb888(12), I3 => \y_int[31]_i_81_n_0\, I4 => rgb888(13), I5 => rgb888(15), O => \y_int[31]_i_53_n_0\ ); \y_int[31]_i_54\: unisim.vcomponents.LUT6 generic map( INIT => X"366C6CC96CC9C993" ) port map ( I0 => \y_int[31]_i_84_n_0\, I1 => rgb888(13), I2 => \y_int[31]_i_81_n_0\, I3 => rgb888(12), I4 => rgb888(15), I5 => \y_int_reg[31]_i_82_n_1\, O => \y_int[31]_i_54_n_0\ ); \y_int[31]_i_55\: unisim.vcomponents.LUT5 generic map( INIT => X"99969666" ) port map ( I0 => \y_int[31]_i_51_n_0\, I1 => \y_int[31]_i_83_n_0\, I2 => \y_int_reg[31]_i_82_n_6\, I3 => \y_int[31]_i_85_n_0\, I4 => rgb888(14), O => \y_int[31]_i_55_n_0\ ); \y_int[31]_i_56\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => rgb888(13), I1 => rgb888(11), I2 => rgb888(9), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \y_int[31]_i_56_n_0\ ); \y_int[31]_i_57\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => rgb888(12), I1 => rgb888(10), I2 => rgb888(9), I3 => rgb888(11), I4 => rgb888(13), O => \y_int[31]_i_57_n_0\ ); \y_int[31]_i_58\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_35_n_5\, O => \y_int[31]_i_58_n_0\ ); \y_int[31]_i_59\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_35_n_6\, O => \y_int[31]_i_59_n_0\ ); \y_int[31]_i_60\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_35_n_7\, O => \y_int[31]_i_60_n_0\ ); \y_int[31]_i_61\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[19]_i_24_n_4\, O => \y_int[31]_i_61_n_0\ ); \y_int[31]_i_72\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(5), I1 => rgb888(7), O => \y_int[31]_i_72_n_0\ ); \y_int[31]_i_73\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(6), I1 => rgb888(7), O => \y_int[31]_i_73_n_0\ ); \y_int[31]_i_74\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => rgb888(7), I1 => rgb888(5), I2 => rgb888(6), O => \y_int[31]_i_74_n_0\ ); \y_int[31]_i_76\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_60, O => \y_int[31]_i_76_n_0\ ); \y_int[31]_i_77\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_61, O => \y_int[31]_i_77_n_0\ ); \y_int[31]_i_78\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_62, O => \y_int[31]_i_78_n_0\ ); \y_int[31]_i_79\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_63, O => \y_int[31]_i_79_n_0\ ); \y_int[31]_i_80\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => rgb888(11), I1 => rgb888(9), I2 => rgb888(10), I3 => rgb888(12), O => \y_int[31]_i_80_n_0\ ); \y_int[31]_i_81\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => rgb888(10), I1 => rgb888(9), I2 => rgb888(11), O => \y_int[31]_i_81_n_0\ ); \y_int[31]_i_83\: unisim.vcomponents.LUT6 generic map( INIT => X"6666666999999996" ) port map ( I0 => \y_int_reg[31]_i_82_n_1\, I1 => rgb888(15), I2 => rgb888(11), I3 => rgb888(9), I4 => rgb888(10), I5 => rgb888(12), O => \y_int[31]_i_83_n_0\ ); \y_int[31]_i_84\: unisim.vcomponents.LUT5 generic map( INIT => X"FEABA802" ) port map ( I0 => \y_int_reg[31]_i_82_n_6\, I1 => rgb888(10), I2 => rgb888(9), I3 => rgb888(11), I4 => rgb888(14), O => \y_int[31]_i_84_n_0\ ); \y_int[31]_i_85\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => rgb888(10), I1 => rgb888(9), I2 => rgb888(11), O => \y_int[31]_i_85_n_0\ ); \y_int[31]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(4), I1 => rgb888(6), O => \y_int[31]_i_93_n_0\ ); \y_int[31]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(3), I1 => rgb888(5), O => \y_int[31]_i_94_n_0\ ); \y_int[31]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(2), I1 => rgb888(4), O => \y_int[31]_i_95_n_0\ ); \y_int[31]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(1), I1 => rgb888(3), O => \y_int[31]_i_96_n_0\ ); \y_int[31]_i_97\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => rgb888(6), I1 => rgb888(4), I2 => rgb888(7), I3 => rgb888(5), O => \y_int[31]_i_97_n_0\ ); \y_int[31]_i_98\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => rgb888(5), I1 => rgb888(3), I2 => rgb888(6), I3 => rgb888(4), O => \y_int[31]_i_98_n_0\ ); \y_int[31]_i_99\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => rgb888(4), I1 => rgb888(2), I2 => rgb888(5), I3 => rgb888(3), O => \y_int[31]_i_99_n_0\ ); \y_int[3]_i_37\: unisim.vcomponents.LUT4 generic map( INIT => X"8228" ) port map ( I0 => \y_int_reg[31]_i_82_n_7\, I1 => rgb888(9), I2 => rgb888(10), I3 => rgb888(13), O => \y_int[3]_i_37_n_0\ ); \y_int[3]_i_38\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => rgb888(9), I1 => rgb888(10), I2 => rgb888(13), I3 => \y_int_reg[31]_i_82_n_7\, O => \y_int[3]_i_38_n_0\ ); \y_int[3]_i_39\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \y_int_reg[3]_i_40_n_4\, I1 => rgb888(9), I2 => rgb888(12), O => \y_int[3]_i_39_n_0\ ); \y_int[3]_i_41\: unisim.vcomponents.LUT5 generic map( INIT => X"99969699" ) port map ( I0 => \y_int[3]_i_37_n_0\, I1 => \y_int[3]_i_79_n_0\, I2 => rgb888(13), I3 => rgb888(10), I4 => rgb888(9), O => \y_int[3]_i_41_n_0\ ); \y_int[3]_i_42\: unisim.vcomponents.LUT6 generic map( INIT => X"9669696969696996" ) port map ( I0 => \y_int_reg[31]_i_82_n_7\, I1 => rgb888(13), I2 => rgb888(10), I3 => rgb888(12), I4 => \y_int_reg[3]_i_40_n_4\, I5 => rgb888(9), O => \y_int[3]_i_42_n_0\ ); \y_int[3]_i_43\: unisim.vcomponents.LUT5 generic map( INIT => X"96696969" ) port map ( I0 => rgb888(12), I1 => rgb888(9), I2 => \y_int_reg[3]_i_40_n_4\, I3 => rgb888(11), I4 => rgb888(8), O => \y_int[3]_i_43_n_0\ ); \y_int[3]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(8), I1 => rgb888(11), I2 => \y_int_reg[3]_i_40_n_5\, O => \y_int[3]_i_44_n_0\ ); \y_int[3]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_19_n_5\, O => \y_int[3]_i_46_n_0\ ); \y_int[3]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_19_n_6\, O => \y_int[3]_i_47_n_0\ ); \y_int[3]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_19_n_7\, O => \y_int[3]_i_48_n_0\ ); \y_int[3]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_51, O => \y_int[3]_i_49_n_0\ ); \y_int[3]_i_75\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(15), I1 => rgb888(13), O => \y_int[3]_i_75_n_0\ ); \y_int[3]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(12), I1 => rgb888(14), O => \y_int[3]_i_76_n_0\ ); \y_int[3]_i_77\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(11), I1 => rgb888(13), O => \y_int[3]_i_77_n_0\ ); \y_int[3]_i_78\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(10), I1 => rgb888(12), O => \y_int[3]_i_78_n_0\ ); \y_int[3]_i_79\: unisim.vcomponents.LUT5 generic map( INIT => X"A95656A9" ) port map ( I0 => \y_int_reg[31]_i_82_n_6\, I1 => rgb888(10), I2 => rgb888(9), I3 => rgb888(11), I4 => rgb888(14), O => \y_int[3]_i_79_n_0\ ); \y_int[3]_i_80\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_52, O => \y_int[3]_i_80_n_0\ ); \y_int[3]_i_81\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_53, O => \y_int[3]_i_81_n_0\ ); \y_int[3]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_54, O => \y_int[3]_i_82_n_0\ ); \y_int[3]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_70_n_6\, O => \y_int[3]_i_83_n_0\ ); \y_int[3]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(9), I1 => rgb888(11), O => \y_int[3]_i_93_n_0\ ); \y_int[3]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(8), I1 => rgb888(10), O => \y_int[3]_i_94_n_0\ ); \y_int[3]_i_95\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(9), O => \y_int[3]_i_95_n_0\ ); \y_int[3]_i_96\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(8), O => \y_int[3]_i_96_n_0\ ); \y_int[7]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_21_n_5\, O => \y_int[7]_i_25_n_0\ ); \y_int[7]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_21_n_6\, O => \y_int[7]_i_26_n_0\ ); \y_int[7]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_21_n_7\, O => \y_int[7]_i_27_n_0\ ); \y_int[7]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_19_n_4\, O => \y_int[7]_i_28_n_0\ ); \y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[7]_i_23_n_0\, CO(3) => \y_int_reg[11]_i_27_n_0\, CO(2) => \y_int_reg[11]_i_27_n_1\, CO(1) => \y_int_reg[11]_i_27_n_2\, CO(0) => \y_int_reg[11]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[11]_i_27_n_4\, O(2) => \y_int_reg[11]_i_27_n_5\, O(1) => \y_int_reg[11]_i_27_n_6\, O(0) => \y_int_reg[11]_i_27_n_7\, S(3) => \y_int[11]_i_54_n_0\, S(2) => \y_int[11]_i_55_n_0\, S(1) => \y_int[11]_i_56_n_0\, S(0) => \y_int[11]_i_57_n_0\ ); \y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_27_n_0\, CO(3) => \y_int_reg[15]_i_24_n_0\, CO(2) => \y_int_reg[15]_i_24_n_1\, CO(1) => \y_int_reg[15]_i_24_n_2\, CO(0) => \y_int_reg[15]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[15]_i_24_n_4\, O(2) => \y_int_reg[15]_i_24_n_5\, O(1) => \y_int_reg[15]_i_24_n_6\, O(0) => \y_int_reg[15]_i_24_n_7\, S(3) => \y_int[15]_i_36_n_0\, S(2) => \y_int[15]_i_37_n_0\, S(1) => \y_int[15]_i_38_n_0\, S(0) => \y_int[15]_i_39_n_0\ ); \y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_81, CO(3) => \y_int_reg[15]_i_34_n_0\, CO(2) => \y_int_reg[15]_i_34_n_1\, CO(1) => \y_int_reg[15]_i_34_n_2\, CO(0) => \y_int_reg[15]_i_34_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(12 downto 9), S(3) => \y_int[15]_i_44_n_0\, S(2) => \y_int[15]_i_45_n_0\, S(1) => \y_int[15]_i_46_n_0\, S(0) => \y_int[15]_i_47_n_0\ ); \y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_24_n_0\, CO(3) => \y_int_reg[19]_i_24_n_0\, CO(2) => \y_int_reg[19]_i_24_n_1\, CO(1) => \y_int_reg[19]_i_24_n_2\, CO(0) => \y_int_reg[19]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[19]_i_24_n_4\, O(2) => \y_int_reg[19]_i_24_n_5\, O(1) => \y_int_reg[19]_i_24_n_6\, O(0) => \y_int_reg[19]_i_24_n_7\, S(3) => \y_int[19]_i_36_n_0\, S(2) => \y_int[19]_i_37_n_0\, S(1) => \y_int[19]_i_38_n_0\, S(0) => \y_int[19]_i_39_n_0\ ); \y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_79, CO(3) => \y_int_reg[19]_i_33_n_0\, CO(2) => \y_int_reg[19]_i_33_n_1\, CO(1) => \y_int_reg[19]_i_33_n_2\, CO(0) => \y_int_reg[19]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[19]_i_33_n_4\, O(2) => \y_int_reg[19]_i_33_n_5\, O(1) => \y_int_reg[19]_i_33_n_6\, O(0) => \y_int_reg[19]_i_33_n_7\, S(3) => \y_int[19]_i_40_n_0\, S(2) => \y_int[19]_i_41_n_0\, S(1) => \y_int[19]_i_42_n_0\, S(0) => \y_int[19]_i_43_n_0\ ); \y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_34_n_0\, CO(3) => \y_int_reg[19]_i_34_n_0\, CO(2) => \y_int_reg[19]_i_34_n_1\, CO(1) => \y_int_reg[19]_i_34_n_2\, CO(0) => \y_int_reg[19]_i_34_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(16 downto 13), S(3) => \y_int[19]_i_44_n_0\, S(2) => \y_int[19]_i_45_n_0\, S(1) => \y_int[19]_i_46_n_0\, S(0) => \y_int[19]_i_47_n_0\ ); \y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_35_n_0\, CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1), O(0) => \y_int_reg[23]_i_32_n_7\, S(3 downto 1) => B"000", S(0) => \y_int[23]_i_50_n_0\ ); \y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_24_n_0\, CO(3) => \y_int_reg[23]_i_35_n_0\, CO(2) => \y_int_reg[23]_i_35_n_1\, CO(1) => \y_int_reg[23]_i_35_n_2\, CO(0) => \y_int_reg[23]_i_35_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[23]_i_35_n_4\, O(2) => \y_int_reg[23]_i_35_n_5\, O(1) => \y_int_reg[23]_i_35_n_6\, O(0) => \y_int_reg[23]_i_35_n_7\, S(3) => \y_int[23]_i_58_n_0\, S(2) => \y_int[23]_i_59_n_0\, S(1) => \y_int[23]_i_60_n_0\, S(0) => \y_int[23]_i_61_n_0\ ); \y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_27_n_0\, CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_10_n_1\, CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1), CO(0) => \y_int_reg[31]_i_10_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2), O(1) => \y_int_reg[31]_i_10_n_6\, O(0) => \y_int_reg[31]_i_10_n_7\, S(3 downto 2) => B"01", S(1) => \y_int[31]_i_28_n_0\, S(0) => \y_int[31]_i_29_n_0\ ); \y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_37_n_0\, CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_12_n_1\, CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1), CO(0) => \y_int_reg[31]_i_12_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => y_int_reg2(22 downto 21), S(3 downto 2) => B"01", S(1) => \y_int[31]_i_38_n_0\, S(0) => \y_int[31]_i_39_n_0\ ); \y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_19_n_0\, CO(3) => \y_int_reg[31]_i_21_n_0\, CO(2) => \y_int_reg[31]_i_21_n_1\, CO(1) => \y_int_reg[31]_i_21_n_2\, CO(0) => \y_int_reg[31]_i_21_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_48_n_0\, DI(2) => \y_int[31]_i_49_n_0\, DI(1) => \y_int[31]_i_50_n_0\, DI(0) => \y_int[31]_i_51_n_0\, O(3) => \y_int_reg[31]_i_21_n_4\, O(2) => \y_int_reg[31]_i_21_n_5\, O(1) => \y_int_reg[31]_i_21_n_6\, O(0) => \y_int_reg[31]_i_21_n_7\, S(3) => \y_int[31]_i_52_n_0\, S(2) => \y_int[31]_i_53_n_0\, S(1) => \y_int[31]_i_54_n_0\, S(0) => \y_int[31]_i_55_n_0\ ); \y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_33_n_0\, CO(3) => \y_int_reg[31]_i_27_n_0\, CO(2) => \y_int_reg[31]_i_27_n_1\, CO(1) => \y_int_reg[31]_i_27_n_2\, CO(0) => \y_int_reg[31]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[31]_i_27_n_4\, O(2) => \y_int_reg[31]_i_27_n_5\, O(1) => \y_int_reg[31]_i_27_n_6\, O(0) => \y_int_reg[31]_i_27_n_7\, S(3) => \y_int[31]_i_58_n_0\, S(2) => \y_int[31]_i_59_n_0\, S(1) => \y_int[31]_i_60_n_0\, S(0) => \y_int[31]_i_61_n_0\ ); \y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_71_n_0\, CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[31]_i_31_n_2\, CO(0) => \y_int_reg[31]_i_31_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => rgb888(6), DI(0) => \y_int[31]_i_72_n_0\, O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3), O(2) => \y_int_reg[31]_i_31_n_5\, O(1) => \y_int_reg[31]_i_31_n_6\, O(0) => \y_int_reg[31]_i_31_n_7\, S(3 downto 2) => B"01", S(1) => \y_int[31]_i_73_n_0\, S(0) => \y_int[31]_i_74_n_0\ ); \y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_34_n_0\, CO(3) => \y_int_reg[31]_i_37_n_0\, CO(2) => \y_int_reg[31]_i_37_n_1\, CO(1) => \y_int_reg[31]_i_37_n_2\, CO(0) => \y_int_reg[31]_i_37_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(20 downto 17), S(3) => \y_int[31]_i_76_n_0\, S(2) => \y_int[31]_i_77_n_0\, S(1) => \y_int[31]_i_78_n_0\, S(0) => \y_int[31]_i_79_n_0\ ); \y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_80, CO(3) => \y_int_reg[31]_i_71_n_0\, CO(2) => \y_int_reg[31]_i_71_n_1\, CO(1) => \y_int_reg[31]_i_71_n_2\, CO(0) => \y_int_reg[31]_i_71_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_93_n_0\, DI(2) => \y_int[31]_i_94_n_0\, DI(1) => \y_int[31]_i_95_n_0\, DI(0) => \y_int[31]_i_96_n_0\, O(3) => \y_int_reg[31]_i_71_n_4\, O(2) => \y_int_reg[31]_i_71_n_5\, O(1) => \y_int_reg[31]_i_71_n_6\, O(0) => \y_int_reg[31]_i_71_n_7\, S(3) => \y_int[31]_i_97_n_0\, S(2) => \y_int[31]_i_98_n_0\, S(1) => \y_int[31]_i_99_n_0\, S(0) => \y_int[31]_i_100_n_0\ ); \y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_40_n_0\, CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_82_n_1\, CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1), CO(0) => \y_int_reg[31]_i_82_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1 downto 0) => rgb888(15 downto 14), O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2), O(1) => \y_int_reg[31]_i_82_n_6\, O(0) => \y_int_reg[31]_i_82_n_7\, S(3 downto 2) => B"01", S(1) => \y_int[31]_i_102_n_0\, S(0) => \y_int[31]_i_103_n_0\ ); \y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_21_n_0\, CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[31]_i_9_n_2\, CO(0) => \y_int_reg[31]_i_9_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \y_int[31]_i_22_n_0\, DI(0) => \y_int[31]_i_23_n_0\, O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3), O(2) => \y_int_reg[31]_i_9_n_5\, O(1) => \y_int_reg[31]_i_9_n_6\, O(0) => \y_int_reg[31]_i_9_n_7\, S(3) => '0', S(2) => \y_int[31]_i_24_n_0\, S(1) => \y_int[31]_i_25_n_0\, S(0) => \y_int[31]_i_26_n_0\ ); \y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_78, CO(3) => \y_int_reg[3]_i_19_n_0\, CO(2) => \y_int_reg[3]_i_19_n_1\, CO(1) => \y_int_reg[3]_i_19_n_2\, CO(0) => \y_int_reg[3]_i_19_n_3\, CYINIT => '0', DI(3) => \y_int[3]_i_37_n_0\, DI(2) => \y_int[3]_i_38_n_0\, DI(1) => \y_int[3]_i_39_n_0\, DI(0) => \y_int_reg[3]_i_40_n_5\, O(3) => \y_int_reg[3]_i_19_n_4\, O(2) => \y_int_reg[3]_i_19_n_5\, O(1) => \y_int_reg[3]_i_19_n_6\, O(0) => \y_int_reg[3]_i_19_n_7\, S(3) => \y_int[3]_i_41_n_0\, S(2) => \y_int[3]_i_42_n_0\, S(1) => \y_int[3]_i_43_n_0\, S(0) => \y_int[3]_i_44_n_0\ ); \y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_45_n_0\, CO(3) => \y_int_reg[3]_i_20_n_0\, CO(2) => \y_int_reg[3]_i_20_n_1\, CO(1) => \y_int_reg[3]_i_20_n_2\, CO(0) => \y_int_reg[3]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[3]_i_20_n_4\, O(2) => \y_int_reg[3]_i_20_n_5\, O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0), S(3) => \y_int[3]_i_46_n_0\, S(2) => \y_int[3]_i_47_n_0\, S(1) => \y_int[3]_i_48_n_0\, S(0) => \y_int[3]_i_49_n_0\ ); \y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_70_n_0\, CO(3) => \y_int_reg[3]_i_40_n_0\, CO(2) => \y_int_reg[3]_i_40_n_1\, CO(1) => \y_int_reg[3]_i_40_n_2\, CO(0) => \y_int_reg[3]_i_40_n_3\, CYINIT => '0', DI(3) => rgb888(15), DI(2 downto 0) => rgb888(12 downto 10), O(3) => \y_int_reg[3]_i_40_n_4\, O(2) => \y_int_reg[3]_i_40_n_5\, O(1) => \y_int_reg[3]_i_40_n_6\, O(0) => \y_int_reg[3]_i_40_n_7\, S(3) => \y_int[3]_i_75_n_0\, S(2) => \y_int[3]_i_76_n_0\, S(1) => \y_int[3]_i_77_n_0\, S(0) => \y_int[3]_i_78_n_0\ ); \y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_45_n_0\, CO(2) => \y_int_reg[3]_i_45_n_1\, CO(1) => \y_int_reg[3]_i_45_n_2\, CO(0) => \y_int_reg[3]_i_45_n_3\, CYINIT => \cb_int[3]_i_84_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[3]_i_80_n_0\, S(2) => \y_int[3]_i_81_n_0\, S(1) => \y_int[3]_i_82_n_0\, S(0) => \y_int[3]_i_83_n_0\ ); \y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_70_n_0\, CO(2) => \y_int_reg[3]_i_70_n_1\, CO(1) => \y_int_reg[3]_i_70_n_2\, CO(0) => \y_int_reg[3]_i_70_n_3\, CYINIT => '0', DI(3 downto 2) => rgb888(9 downto 8), DI(1 downto 0) => B"01", O(3) => \y_int_reg[3]_i_70_n_4\, O(2) => \y_int_reg[3]_i_70_n_5\, O(1) => \y_int_reg[3]_i_70_n_6\, O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0), S(3) => \y_int[3]_i_93_n_0\, S(2) => \y_int[3]_i_94_n_0\, S(1) => \y_int[3]_i_95_n_0\, S(0) => \y_int[3]_i_96_n_0\ ); \y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_20_n_0\, CO(3) => \y_int_reg[7]_i_23_n_0\, CO(2) => \y_int_reg[7]_i_23_n_1\, CO(1) => \y_int_reg[7]_i_23_n_2\, CO(0) => \y_int_reg[7]_i_23_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[7]_i_23_n_4\, O(2) => \y_int_reg[7]_i_23_n_5\, O(1) => \y_int_reg[7]_i_23_n_6\, O(0) => \y_int_reg[7]_i_23_n_7\, S(3) => \y_int[7]_i_25_n_0\, S(2) => \y_int[7]_i_26_n_0\, S(1) => \y_int[7]_i_27_n_0\, S(0) => \y_int[7]_i_28_n_0\ ); end STRUCTURE;	mit	5bc8dc83af012c539e3a80902cbec615	0.480129	2.23181	false	false	false	false
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_util_ds_buf_1_0/sim/system_util_ds_buf_1_0.vhd	1	5,806	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:util_ds_buf:2.1 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY util_ds_buf_v2_01_a; USE util_ds_buf_v2_01_a.util_ds_buf; ENTITY system_util_ds_buf_1_0 IS PORT ( BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END system_util_ds_buf_1_0; ARCHITECTURE system_util_ds_buf_1_0_arch OF system_util_ds_buf_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_ds_buf_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT util_ds_buf IS GENERIC ( C_BUF_TYPE : STRING; C_SIZE : INTEGER ); PORT ( IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0); IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0); IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); OBUF_IN : IN STD_LOGIC_VECTOR(0 DOWNTO 0); OBUF_DS_P : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); OBUF_DS_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_DS_P : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_DS_N : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_IO_T : IN STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_IO_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_IO_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFGCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFGCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFGCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFH_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFH_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFHCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFHCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFHCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_CEMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_CLRMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_DIV : IN STD_LOGIC_VECTOR(2 DOWNTO 0); BUFG_GT_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT util_ds_buf; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF BUFG_I: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_I CLK"; ATTRIBUTE X_INTERFACE_INFO OF BUFG_O: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_O CLK"; BEGIN U0 : util_ds_buf GENERIC MAP ( C_BUF_TYPE => "BUFG", C_SIZE => 1 ) PORT MAP ( IBUF_DS_P => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), IBUF_DS_N => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), OBUF_IN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), IOBUF_IO_T => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), IOBUF_IO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_I => BUFG_I, BUFG_O => BUFG_O, BUFGCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFGCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFH_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFHCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFHCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_CEMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_CLRMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_DIV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)) ); END system_util_ds_buf_1_0_arch;	mit	5053240f1b435396b002343bfe430f46	0.680331	3.356069	false	false	false	false
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl	1	10,123	-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Thu May 25 21:06:44 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl -- Design : system_ov7670_vga_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_ov7670_vga_0_0_ov7670_vga is port ( rgb : out STD_LOGIC_VECTOR ( 15 downto 0 ); active : in STD_LOGIC; clk_x2 : in STD_LOGIC; data : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_ov7670_vga_0_0_ov7670_vga : entity is "ov7670_vga"; end system_ov7670_vga_0_0_ov7670_vga; architecture STRUCTURE of system_ov7670_vga_0_0_ov7670_vga is signal cycle : STD_LOGIC; signal \data_pair[15]_i_1_n_0\ : STD_LOGIC; signal \data_pair[7]_i_1_n_0\ : STD_LOGIC; signal \data_pair_reg_n_0_[0]\ : STD_LOGIC; signal \data_pair_reg_n_0_[10]\ : STD_LOGIC; signal \data_pair_reg_n_0_[11]\ : STD_LOGIC; signal \data_pair_reg_n_0_[12]\ : STD_LOGIC; signal \data_pair_reg_n_0_[13]\ : STD_LOGIC; signal \data_pair_reg_n_0_[14]\ : STD_LOGIC; signal \data_pair_reg_n_0_[15]\ : STD_LOGIC; signal \data_pair_reg_n_0_[1]\ : STD_LOGIC; signal \data_pair_reg_n_0_[2]\ : STD_LOGIC; signal \data_pair_reg_n_0_[3]\ : STD_LOGIC; signal \data_pair_reg_n_0_[4]\ : STD_LOGIC; signal \data_pair_reg_n_0_[5]\ : STD_LOGIC; signal \data_pair_reg_n_0_[6]\ : STD_LOGIC; signal \data_pair_reg_n_0_[7]\ : STD_LOGIC; signal \data_pair_reg_n_0_[8]\ : STD_LOGIC; signal \data_pair_reg_n_0_[9]\ : STD_LOGIC; signal rgb_regn_0_0 : STD_LOGIC; begin cycle_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_x2, CE => '1', D => \data_pair[7]_i_1_n_0\, Q => cycle, R => '0' ); \data_pair[15]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => cycle, I1 => active, O => \data_pair[15]_i_1_n_0\ ); \data_pair[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => active, I1 => cycle, O => \data_pair[7]_i_1_n_0\ ); \data_pair_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(0), Q => \data_pair_reg_n_0_[0]\, R => '0' ); \data_pair_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(2), Q => \data_pair_reg_n_0_[10]\, R => '0' ); \data_pair_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(3), Q => \data_pair_reg_n_0_[11]\, R => '0' ); \data_pair_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(4), Q => \data_pair_reg_n_0_[12]\, R => '0' ); \data_pair_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(5), Q => \data_pair_reg_n_0_[13]\, R => '0' ); \data_pair_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(6), Q => \data_pair_reg_n_0_[14]\, R => '0' ); \data_pair_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(7), Q => \data_pair_reg_n_0_[15]\, R => '0' ); \data_pair_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(1), Q => \data_pair_reg_n_0_[1]\, R => '0' ); \data_pair_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(2), Q => \data_pair_reg_n_0_[2]\, R => '0' ); \data_pair_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(3), Q => \data_pair_reg_n_0_[3]\, R => '0' ); \data_pair_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(4), Q => \data_pair_reg_n_0_[4]\, R => '0' ); \data_pair_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(5), Q => \data_pair_reg_n_0_[5]\, R => '0' ); \data_pair_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(6), Q => \data_pair_reg_n_0_[6]\, R => '0' ); \data_pair_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(7), Q => \data_pair_reg_n_0_[7]\, R => '0' ); \data_pair_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(0), Q => \data_pair_reg_n_0_[8]\, R => '0' ); \data_pair_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(1), Q => \data_pair_reg_n_0_[9]\, R => '0' ); \rgb_reg[0]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[0]\, Q => rgb(0), R => '0' ); \rgb_reg[10]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[10]\, Q => rgb(10), R => '0' ); \rgb_reg[11]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[11]\, Q => rgb(11), R => '0' ); \rgb_reg[12]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[12]\, Q => rgb(12), R => '0' ); \rgb_reg[13]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[13]\, Q => rgb(13), R => '0' ); \rgb_reg[14]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[14]\, Q => rgb(14), R => '0' ); \rgb_reg[15]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[15]\, Q => rgb(15), R => '0' ); \rgb_reg[1]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[1]\, Q => rgb(1), R => '0' ); \rgb_reg[2]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[2]\, Q => rgb(2), R => '0' ); \rgb_reg[3]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[3]\, Q => rgb(3), R => '0' ); \rgb_reg[4]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[4]\, Q => rgb(4), R => '0' ); \rgb_reg[5]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[5]\, Q => rgb(5), R => '0' ); \rgb_reg[6]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[6]\, Q => rgb(6), R => '0' ); \rgb_reg[7]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[7]\, Q => rgb(7), R => '0' ); \rgb_reg[8]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[8]\, Q => rgb(8), R => '0' ); \rgb_reg[9]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[9]\, Q => rgb(9), R => '0' ); rgb_regi_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => clk_x2, O => rgb_regn_0_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_ov7670_vga_0_0 is port ( clk_x2 : in STD_LOGIC; active : in STD_LOGIC; data : in STD_LOGIC_VECTOR ( 7 downto 0 ); rgb : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_ov7670_vga_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_ov7670_vga_0_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_ov7670_vga_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_ov7670_vga_0_0 : entity is "ov7670_vga,Vivado 2016.4"; end system_ov7670_vga_0_0; architecture STRUCTURE of system_ov7670_vga_0_0 is begin U0: entity work.system_ov7670_vga_0_0_ov7670_vga port map ( active => active, clk_x2 => clk_x2, data(7 downto 0) => data(7 downto 0), rgb(15 downto 0) => rgb(15 downto 0) ); end STRUCTURE;	mit	7fb98e94afb35836da219f74a8f65606	0.506569	2.785636	false	false	false	false
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_buffer_register_1_0/system_buffer_register_1_0_sim_netlist.vhdl	1	7,575	-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Sun Jun 04 17:33:00 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top system_buffer_register_1_0 -prefix -- system_buffer_register_1_0_ system_buffer_register_0_0_sim_netlist.vhdl -- Design : system_buffer_register_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_buffer_register_1_0_buffer_register is port ( val_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); val_in : in STD_LOGIC_VECTOR ( 31 downto 0 ); clk : in STD_LOGIC ); end system_buffer_register_1_0_buffer_register; architecture STRUCTURE of system_buffer_register_1_0_buffer_register is begin \val_out_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(0), Q => val_out(0), R => '0' ); \val_out_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(10), Q => val_out(10), R => '0' ); \val_out_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(11), Q => val_out(11), R => '0' ); \val_out_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(12), Q => val_out(12), R => '0' ); \val_out_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(13), Q => val_out(13), R => '0' ); \val_out_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(14), Q => val_out(14), R => '0' ); \val_out_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(15), Q => val_out(15), R => '0' ); \val_out_reg[16]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(16), Q => val_out(16), R => '0' ); \val_out_reg[17]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(17), Q => val_out(17), R => '0' ); \val_out_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(18), Q => val_out(18), R => '0' ); \val_out_reg[19]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(19), Q => val_out(19), R => '0' ); \val_out_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(1), Q => val_out(1), R => '0' ); \val_out_reg[20]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(20), Q => val_out(20), R => '0' ); \val_out_reg[21]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(21), Q => val_out(21), R => '0' ); \val_out_reg[22]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(22), Q => val_out(22), R => '0' ); \val_out_reg[23]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(23), Q => val_out(23), R => '0' ); \val_out_reg[24]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(24), Q => val_out(24), R => '0' ); \val_out_reg[25]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(25), Q => val_out(25), R => '0' ); \val_out_reg[26]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(26), Q => val_out(26), R => '0' ); \val_out_reg[27]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(27), Q => val_out(27), R => '0' ); \val_out_reg[28]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(28), Q => val_out(28), R => '0' ); \val_out_reg[29]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(29), Q => val_out(29), R => '0' ); \val_out_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(2), Q => val_out(2), R => '0' ); \val_out_reg[30]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(30), Q => val_out(30), R => '0' ); \val_out_reg[31]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(31), Q => val_out(31), R => '0' ); \val_out_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(3), Q => val_out(3), R => '0' ); \val_out_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(4), Q => val_out(4), R => '0' ); \val_out_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(5), Q => val_out(5), R => '0' ); \val_out_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(6), Q => val_out(6), R => '0' ); \val_out_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(7), Q => val_out(7), R => '0' ); \val_out_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(8), Q => val_out(8), R => '0' ); \val_out_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(9), Q => val_out(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_buffer_register_1_0 is port ( clk : in STD_LOGIC; val_in : in STD_LOGIC_VECTOR ( 31 downto 0 ); val_out : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_buffer_register_1_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_buffer_register_1_0 : entity is "system_buffer_register_0_0,buffer_register,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_buffer_register_1_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_buffer_register_1_0 : entity is "buffer_register,Vivado 2016.4"; end system_buffer_register_1_0; architecture STRUCTURE of system_buffer_register_1_0 is begin U0: entity work.system_buffer_register_1_0_buffer_register port map ( clk => clk, val_in(31 downto 0) => val_in(31 downto 0), val_out(31 downto 0) => val_out(31 downto 0) ); end STRUCTURE;	mit	93a42abdb21ab09c4dcf4ee3d1cdc502	0.486865	3.101966	false	false	false	false
loa-org/loa-hdl	modules/signalprocessing/hdl/goertzel_pipelined_v2.vhd	2	5,089	------------------------------------------------------------------------------- -- Title : Goertzel Algorithm pipelined with BRAM -- Project : ------------------------------------------------------------------------------- -- File : goertzel_pipelined_v2.vhd -- Author : strongly-typed -- Created : 2012-04-24 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: -- -- ToDos : The throughput can be increased by: -- i) Reduce steps in pipeline -- ii) Do not wait to put a new value into the pipeline until the -- last result was processed. Alternate reading and writing to -- the BRAM. Need to store the address of the the data -- currently in progress. ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.signalprocessing_pkg.all; entity goertzel_pipelined_v2 is generic ( FREQUENCIES : positive; CHANNELS : positive := 12; SAMPLES : positive := 250; Q : positive := 13); port ( start_p : in std_logic; bram_addr_p : out std_logic_vector(7 downto 0); bram_data_i : in std_logic_vector(35 downto 0); bram_data_o : out std_logic_vector(35 downto 0); bram_we_p : out std_logic; ready_p : out std_logic; enable_p : in std_logic; coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0); inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0); clk : in std_logic); end entity goertzel_pipelined_v2; architecture structural of goertzel_pipelined_v2 is signal start_s : std_logic := '0'; -- select signals of muxes signal mux_delay1_s : std_logic := '0'; signal mux_delay2_s : std_logic := '0'; signal mux_coef_s : natural range FREQUENCIES-1 downto 0 := 0; signal mux_input_s : natural range CHANNELS-1 downto 0 := 0; -- outputs of the muxes signal muxed_delay1_s : goertzel_data_type := (others => '0'); signal muxed_delay2_s : goertzel_data_type := (others => '0'); signal muxed_coef_s : goertzel_coef_type := (others => '0'); signal muxed_input_s : goertzel_input_type := (others => '0'); -- inter-instance routing signal bram_data_i_s : goertzel_result_type := (others => (others => '0')); signal goertzel_result_to_bram_s : goertzel_result_type := (others => (others => '0')); signal pipeline_input_s : goertzel_result_type := (others => (others => '0')); begin -- architecture structural start_s <= start_p; pipeline_input_s(0) <= muxed_delay1_s; pipeline_input_s(1) <= muxed_delay2_s; -- map generic std_logic_vector(35 downto 0) form bram -- to strongly-tyed goertzel_result_type of pipeline -- \|35 ---- 18\|\|17 ------ 0\| BRAM -- \|--delay2--\|\|--delay1--\|\| pipeline bram_data_i_s(0) <= signed(bram_data_i(17 downto 0)); bram_data_i_s(1) <= signed(bram_data_i(35 downto 18)); -- from pipeline to bram bram_data_o <= std_logic_vector(goertzel_result_to_bram_s(1)) & std_logic_vector(goertzel_result_to_bram_s(0)); -- muxes to multiplex one of the channels to the pipeline goertzel_muxes_1 : entity work.goertzel_muxes generic map ( CHANNELS => CHANNELS, FREQUENCIES => FREQUENCIES) port map ( mux_delay1_p => mux_delay1_s, mux_delay2_p => mux_delay2_s, mux_coef => mux_coef_s, mux_input => mux_input_s, bram_data => bram_data_i_s, coefs_p => coefs_p, inputs_p => inputs_p, delay1_p => muxed_delay1_s, delay2_p => muxed_delay2_s, coef_p => muxed_coef_s, input_p => muxed_input_s); -- control the pipeline goertzel_control_unit_1 : entity work.goertzel_control_unit generic map ( SAMPLES => SAMPLES, FREQUENCIES => FREQUENCIES, CHANNELS => CHANNELS) port map ( start_p => start_s, ready_p => ready_p, -- output to the bram bram_addr_p => bram_addr_p, bram_we_p => bram_we_p, -- outputs to the mux mux_delay1_p => mux_delay1_s, mux_delay2_p => mux_delay2_s, mux_coef_p => mux_coef_s, mux_input_p => mux_input_s, clk => clk); -- the actual pipiline working on one frequency and on one channel goertzel_pipeline_1 : entity work.goertzel_pipeline generic map ( Q => Q) port map ( coef_p => muxed_coef_s, input_p => muxed_input_s, delay_p => pipeline_input_s, result_p => goertzel_result_to_bram_s, clk => clk); end architecture structural;	bsd-3-clause	f6089eaf5317dedad86604886703ea07	0.525251	3.586328	false	false	false	false
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_c_addsub_0_0/sim/system_c_addsub_0_0.vhd	1	5,365	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:c_addsub:12.0 -- IP Revision: 10 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY c_addsub_v12_0_10; USE c_addsub_v12_0_10.c_addsub_v12_0_10; ENTITY system_c_addsub_0_0 IS PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END system_c_addsub_0_0; ARCHITECTURE system_c_addsub_0_0_arch OF system_c_addsub_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_c_addsub_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT c_addsub_v12_0_10 IS GENERIC ( C_VERBOSITY : INTEGER; C_XDEVICEFAMILY : STRING; C_IMPLEMENTATION : INTEGER; C_A_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_OUT_WIDTH : INTEGER; C_CE_OVERRIDES_SCLR : INTEGER; C_A_TYPE : INTEGER; C_B_TYPE : INTEGER; C_LATENCY : INTEGER; C_ADD_MODE : INTEGER; C_B_CONSTANT : INTEGER; C_B_VALUE : STRING; C_AINIT_VAL : STRING; C_SINIT_VAL : STRING; C_CE_OVERRIDES_BYPASS : INTEGER; C_BYPASS_LOW : INTEGER; C_SCLR_OVERRIDES_SSET : INTEGER; C_HAS_C_IN : INTEGER; C_HAS_C_OUT : INTEGER; C_BORROW_LOW : INTEGER; C_HAS_CE : INTEGER; C_HAS_BYPASS : INTEGER; C_HAS_SCLR : INTEGER; C_HAS_SSET : INTEGER; C_HAS_SINIT : INTEGER ); PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLK : IN STD_LOGIC; ADD : IN STD_LOGIC; C_IN : IN STD_LOGIC; CE : IN STD_LOGIC; BYPASS : IN STD_LOGIC; SCLR : IN STD_LOGIC; SSET : IN STD_LOGIC; SINIT : IN STD_LOGIC; C_OUT : OUT STD_LOGIC; S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT c_addsub_v12_0_10; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA"; BEGIN U0 : c_addsub_v12_0_10 GENERIC MAP ( C_VERBOSITY => 0, C_XDEVICEFAMILY => "zynq", C_IMPLEMENTATION => 0, C_A_WIDTH => 10, C_B_WIDTH => 10, C_OUT_WIDTH => 10, C_CE_OVERRIDES_SCLR => 0, C_A_TYPE => 0, C_B_TYPE => 0, C_LATENCY => 0, C_ADD_MODE => 0, C_B_CONSTANT => 0, C_B_VALUE => "0000000000", C_AINIT_VAL => "0", C_SINIT_VAL => "0", C_CE_OVERRIDES_BYPASS => 1, C_BYPASS_LOW => 0, C_SCLR_OVERRIDES_SSET => 1, C_HAS_C_IN => 0, C_HAS_C_OUT => 0, C_BORROW_LOW => 1, C_HAS_CE => 0, C_HAS_BYPASS => 0, C_HAS_SCLR => 0, C_HAS_SSET => 0, C_HAS_SINIT => 0 ) PORT MAP ( A => A, B => B, CLK => '0', ADD => '1', C_IN => '0', CE => '1', BYPASS => '0', SCLR => '0', SSET => '0', SINIT => '0', S => S ); END system_c_addsub_0_0_arch;	mit	dd55901c45e5564c696234dd529fe45d	0.643616	3.479248	false	false	false	false
pgavin/carpe	hdl/tech/inferred/mul_pipe-rtl.vhdl	1	1,566	-- -- vhdl -- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- architecture rtl of mul_pipe is begin mul : entity work.mul_pipe_inferred(rtl) generic map ( stages => stages, src1_bits => src1_bits, src2_bits => src2_bits ) port map ( clk => clk, rstn => rstn, unsgnd => unsgnd, src1 => src1, src2 => src2, result => result ); end;	apache-2.0	b9affe650de8447564bb3190844cdff6	0.476373	5.168317	false	false	false	false
loa-org/loa-hdl	modules/peripheral_register/tb/peripheral_register_tb.vhd	1	3,803	------------------------------------------------------------------------------- -- Title : Testbench for design "peripheral_register" ------------------------------------------------------------------------------- -- Author : Calle <calle@Alukiste> -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2011 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library std; use std.textio.all; library work; use work.bus_pkg.all; use work.reg_file_pkg.all; ------------------------------------------------------------------------------- entity peripheral_register_tb is end peripheral_register_tb; ------------------------------------------------------------------------------- architecture tb of peripheral_register_tb is -- component generics constant BASE_ADDRESS : positive := 16#0100#; -- component ports signal reg : std_logic_vector(15 downto 0) := (others => '0'); signal bus_o : busdevice_out_type; signal bus_i : busdevice_in_type := (addr => (others => '0'), data => (others => '0'), we => '0', re => '0'); signal clk : std_logic := '0'; signal reg_readback : std_logic_vector(15 downto 0); -- comments for the wave view of the testbench type comment_type is (idle, read_wrong_addr, read_correct_addr, write_wrong_addr, write_correct_addr, sequential_cycles); signal comment : comment_type := idle; begin reg_readback <= not reg; -- component instantiation DUT : peripheral_register generic map ( BASE_ADDRESS => BASE_ADDRESS) port map ( dout_p => reg, din_p => reg_readback, -- read back the written values bus_o => bus_o, bus_i => bus_i, reset => '0', clk => clk); -- clock generation clk <= not clk after 10 ns; waveform : process begin wait for 20 ns; -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); -- Read from correct address comment <= read_correct_addr; readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk); -- Write to wrong address comment <= write_wrong_addr; writeWord(addr => BASE_ADDRESS + 1, data => 16#affe#, bus_i => bus_i, clk => clk); -- Write to correct address comment <= write_correct_addr; writeWord(addr => BASE_ADDRESS, data => 16#54af#, bus_i => bus_i, clk => clk); -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); -- Read from correct address comment <= read_correct_addr; readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk); -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); wait until rising_edge(clk); -- generate two read cycles directly following each other comment <= sequential_cycles; bus_i.re <= '1'; wait until rising_edge(clk); wait until rising_edge(clk); bus_i.re <= '0'; wait until rising_edge(clk); bus_i.data <= x"4321"; bus_i.we <= '1'; wait until rising_edge(clk); bus_i.we <= '0'; wait until rising_edge(clk); bus_i.re <= '1'; wait until rising_edge(clk); bus_i.re <= '0'; end process waveform; end tb;	bsd-3-clause	426ec433e84c133af17fce663baab898	0.478833	4.24442	false	false	false	false
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/sim/system_ov7670_controller_1_0.vhd	2	3,747	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:ov7670_controller:1.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_ov7670_controller_1_0 IS PORT ( clk : IN STD_LOGIC; resend : IN STD_LOGIC; config_finished : OUT STD_LOGIC; sioc : OUT STD_LOGIC; siod : INOUT STD_LOGIC; reset : OUT STD_LOGIC; pwdn : OUT STD_LOGIC; xclk : OUT STD_LOGIC ); END system_ov7670_controller_1_0; ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT ov7670_controller IS PORT ( clk : IN STD_LOGIC; resend : IN STD_LOGIC; config_finished : OUT STD_LOGIC; sioc : OUT STD_LOGIC; siod : INOUT STD_LOGIC; reset : OUT STD_LOGIC; pwdn : OUT STD_LOGIC; xclk : OUT STD_LOGIC ); END COMPONENT ov7670_controller; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; BEGIN U0 : ov7670_controller PORT MAP ( clk => clk, resend => resend, config_finished => config_finished, sioc => sioc, siod => siod, reset => reset, pwdn => pwdn, xclk => xclk ); END system_ov7670_controller_1_0_arch;	mit	3a6e86a241014057e31609a2d83f2d0f	0.721911	4.037716	false	false	false	false
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl	1	4,177	-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Sun Jun 04 14:48:58 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top system_vga_pll_0_0 -prefix -- system_vga_pll_0_0_ system_vga_pll_0_0_sim_netlist.vhdl -- Design : system_vga_pll_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_vga_pll_0_0_vga_pll is port ( clk_50 : out STD_LOGIC; clk_25 : out STD_LOGIC; clk_12_5 : out STD_LOGIC; clk_6_25 : out STD_LOGIC; clk_100 : in STD_LOGIC ); end system_vga_pll_0_0_vga_pll; architecture STRUCTURE of system_vga_pll_0_0_vga_pll is signal \^clk_12_5\ : STD_LOGIC; signal clk_12_5_s_i_1_n_0 : STD_LOGIC; signal \^clk_25\ : STD_LOGIC; signal clk_25_s_i_1_n_0 : STD_LOGIC; signal \^clk_50\ : STD_LOGIC; signal \^clk_6_25\ : STD_LOGIC; signal clk_6_25_s_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; begin clk_12_5 <= \^clk_12_5\; clk_25 <= \^clk_25\; clk_50 <= \^clk_50\; clk_6_25 <= \^clk_6_25\; clk_12_5_s_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^clk_12_5\, O => clk_12_5_s_i_1_n_0 ); clk_12_5_s_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \^clk_25\, CE => '1', D => clk_12_5_s_i_1_n_0, Q => \^clk_12_5\, R => '0' ); clk_25_s_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^clk_25\, O => clk_25_s_i_1_n_0 ); clk_25_s_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \^clk_50\, CE => '1', D => clk_25_s_i_1_n_0, Q => \^clk_25\, R => '0' ); clk_50_s_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^clk_50\, O => p_0_in ); clk_50_s_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => '1', D => p_0_in, Q => \^clk_50\, R => '0' ); clk_6_25_s_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^clk_6_25\, O => clk_6_25_s_i_1_n_0 ); clk_6_25_s_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \^clk_6_25\, CE => '1', D => clk_6_25_s_i_1_n_0, Q => \^clk_6_25\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_vga_pll_0_0 is port ( clk_100 : in STD_LOGIC; clk_50 : out STD_LOGIC; clk_25 : out STD_LOGIC; clk_12_5 : out STD_LOGIC; clk_6_25 : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4"; end system_vga_pll_0_0; architecture STRUCTURE of system_vga_pll_0_0 is begin U0: entity work.system_vga_pll_0_0_vga_pll port map ( clk_100 => clk_100, clk_12_5 => clk_12_5, clk_25 => clk_25, clk_50 => clk_50, clk_6_25 => clk_6_25 ); end STRUCTURE;	mit	535e7d159a568a2394c3893ae83aafdd	0.546804	2.931228	false	false	false	false
loa-org/loa-hdl	modules/encoder/hdl/encoder_hall_sensor_module.vhd	2	3,209	------------------------------------------------------------------------------- -- Title : Hall Sensor Encoder Module -- Project : Loa ------------------------------------------------------------------------------- -- Platform : Spartan 3 ------------------------------------------------------------------------------- -- Description: Connectes a hall sensor encoder with a 16-bit counter to -- the internal bus system. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.bus_pkg.all; use work.encoder_module_pkg.all; use work.motor_control_pkg.all; use work.hall_sensor_decoder_pkg.all; use work.up_down_counter_pkg.all; ------------------------------------------------------------------------------- entity encoder_hall_sensor_module is generic ( BASE_ADDRESS : integer range 0 to 16#7FFF# ); port ( hall_sensor_p : in hall_sensor_type; -- counter, set to '0' if not used load_p : in std_logic; -- Save the current encoder value in a -- buffer register bus_o : out busdevice_out_type; bus_i : in busdevice_in_type; clk : in std_logic ); end encoder_hall_sensor_module; ------------------------------------------------------------------------------- architecture behavioral of encoder_hall_sensor_module is type encoder_hall_sensor_module_type is record counter : std_logic_vector(15 downto 0); data_out : std_logic_vector(15 downto 0); end record; signal r, rin : encoder_hall_sensor_module_type := (data_out => (others => '0'), counter => (others => '0')); signal step : std_logic := '0'; signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down) signal decode_error : std_logic; -- Decoding Error, currently not used signal counter : std_logic_vector(15 downto 0); begin seq_proc : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process(bus_i, counter, load_p, r) variable v : encoder_hall_sensor_module_type; begin v := r; v.data_out := (others => '0'); -- Load counter into own buffer if load_p = '1' then v.counter := counter; end if; -- Check Bus Address if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then if bus_i.we = '1' then -- TODO elsif bus_i.re = '1' then v.data_out := r.counter; end if; end if; rin <= v; end process comb_proc; bus_o.data <= r.data_out; decoder : hall_sensor_decoder port map ( hall_sensor_p => hall_sensor_p, step_p => step, dir_p => up_down, error_p => decode_error, clk => clk); up_down_counter_1 : up_down_counter generic map ( WIDTH => 16) port map ( clk_en_p => step, up_down_p => up_down, value_p => counter, reset => '0', clk => clk); end behavioral;	bsd-3-clause	d2061eb9dbb28767338d628b3daa318d	0.48364	3.976456	false	false	false	false

siavooshpayandehazad/TTU_CPU_Project

pico_CPU_pipelined_MIPS32/PicoCPU.vhd

1

6,316

--Copyright (C) 2017 Siavoosh Payandeh Azad library IEEE; use IEEE.std_logic_1164.all; USE ieee.std_logic_unsigned.ALL; use work.pico_cpu.all; entity PicoCPU is generic (Mem_preload_file: string :="code.txt"); port( rst: in std_logic; clk: in std_logic; IO: inout std_logic_vector (CPU_Bitwidth-1 downto 0) ); end PicoCPU; architecture RTL of PicoCPU is --------------------------------------------- -- Signals --------------------------------------------- signal Instr_In : std_logic_vector (CPU_Bitwidth-1 downto 0); signal Instr_Add, Instr_Add_mem : std_logic_vector (CPU_Bitwidth-1 downto 0); ---------------------------------------- signal MemRdAddress : std_logic_vector (CPU_Bitwidth-1 downto 0); signal MemWrtAddress : std_logic_vector (CPU_Bitwidth-1 downto 0); signal Mem_RW : std_logic_vector (3 downto 0); ---------------------------------------- signal IO_DIR : std_logic; signal IO_RD : std_logic_vector (CPU_Bitwidth-1 downto 0); signal IO_WR : std_logic_vector (CPU_Bitwidth-1 downto 0); ---------------------------------------- signal DPU_OV : std_logic; signal DataToDPU_2 : std_logic_vector (CPU_Bitwidth-1 downto 0); ---------------------------------------- signal DPU_ALUCommand : ALU_COMMAND; signal DPU_Mux_Cont_2 : DPU_IN_MUX; ---------------------------------------- signal RFILE_data_sel : RFILE_IN_MUX; signal Data_to_RFILE : std_logic_vector (CPU_Bitwidth-1 downto 0); signal RFILE_in_address: std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); signal WB_enable : std_logic_vector (3 downto 0); signal RFILE_out_sel_1, RFILE_out_sel_1_in : std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); signal RFILE_out_sel_2, RFILE_out_sel_2_in : std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); signal DPU_RESULT, DPU_RESULT_out : std_logic_vector (2*CPU_Bitwidth-1 downto 0); signal Result_ACC : std_logic_vector (2*CPU_Bitwidth-1 downto 0); -- Register file outputs signal R1, R2, R2_FF : std_logic_vector (CPU_Bitwidth-1 downto 0); signal MEMDATA_OUT, MEMDATA_IN: std_logic_vector (CPU_Bitwidth-1 downto 0) := (others=>'0'); signal Mem_Rd_Address_in : std_logic_vector (CPU_Bitwidth-1 downto 0) := (others=>'0'); signal MEM_IN_SEL : MEM_IN_MUX; begin --------------------------------------------- -- component instantiation --------------------------------------------- CLOCK_PROCESS:process (clk, rst)begin if rst = '1' then RFILE_out_sel_1<= (others => '0'); RFILE_out_sel_2<= (others => '0'); R2_FF <= (others => '0'); DPU_RESULT_out <= (others => '0'); elsif clk'event and clk='1' then RFILE_out_sel_1<= RFILE_out_sel_1_in; RFILE_out_sel_2<= RFILE_out_sel_2_in; R2_FF <= R2; DPU_RESULT_out <= DPU_RESULT; end if; end process; gpio_comp: GPIO generic map (BitWidth => CPU_Bitwidth) port map (IO_DIR, IO, IO_WR, IO_RD); ControlUnit_comp: ControlUnit generic map (BitWidth => CPU_Bitwidth, InstructionWidth => CPU_Instwidth) port map ( rst => rst , clk => clk , ------------------------------------------- Instr_In => Instr_In , Instr_Add => Instr_Add , ------------------------------------------- MemRdAddress => MemRdAddress , MemWrtAddress => MemWrtAddress , Mem_RW => Mem_RW , MEM_IN_SEL => MEM_IN_SEL , ------------------------------------------- IO_DIR => IO_DIR , IO_RD => IO_RD , IO_WR => IO_WR , ------------------------------------------- DPU_OV => DPU_OV , DataToDPU_2 => DataToDPU_2 , DPU_ALUCommand => DPU_ALUCommand , DPU_Mux_Cont_2 => DPU_Mux_Cont_2 , ------------------------------------------- RFILE_data_sel => RFILE_data_sel , RFILE_in_address=> RFILE_in_address , RFILE_WB_enable => WB_enable, RFILE_out_sel_1 => RFILE_out_sel_1_in, RFILE_out_sel_2 => RFILE_out_sel_2_in, Data_to_RFILE => Data_to_RFILE , DPU_RESULT => DPU_RESULT , Result_ACC => Result_ACC ); --register file RegFile_comp: RegisterFile generic map (BitWidth => CPU_Bitwidth) port map ( clk => clk, rst => rst, Data_in_mem => MEMDATA_OUT, Data_in_CU => Data_to_RFILE, Data_in_DPU_LOW => DPU_RESULT_out(CPU_Bitwidth-1 downto 0), Data_in_ACC_HI => Result_ACC(2*CPU_Bitwidth-1 downto CPU_Bitwidth), Data_in_ACC_LOW => Result_ACC(CPU_Bitwidth-1 downto 0), Data_in_R2 => R2_FF, Data_in_sel => RFILE_data_sel, RFILE_in_address => RFILE_in_address, WB_enable => WB_enable, Register_out_sel_1 => RFILE_out_sel_1, Register_out_sel_2 => RFILE_out_sel_2, Data_out_1 => R1, Data_out_2 => R2); --datapath unit DPU_comp: DPU generic map (BitWidth => CPU_Bitwidth) port map ( rst => rst, clk => clk, Data_in_mem => MEMDATA_OUT, Data_in_RegFile_1=> R1, Data_in_RegFile_2=> R2, Data_in_control_2=> DataToDPU_2, ALUCommand => DPU_ALUCommand, Mux_Cont_2 => DPU_Mux_Cont_2, DPU_OV => DPU_OV, Result => DPU_RESULT, Result_ACC => Result_ACC); -- MEMORY Input select MUX MEM_DATA_IN_SELECT: process(MEM_IN_SEL, RFILE_out_sel_1, RFILE_out_sel_2, DPU_Result)begin case( MEM_IN_SEL ) is when RFILE_DATA_1 => MEMDATA_IN <= R1; when RFILE_DATA_2 => MEMDATA_IN <= R2; when DPU_DATA => MEMDATA_IN <= DPU_Result(CPU_Bitwidth-1 downto 0); when others => MEMDATA_IN <= (others => '0'); end case; end process; --memory Instr_Add_mem <= "00" & Instr_Add(CPU_Bitwidth-1 downto 2); Mem_comp: RAM generic map (BitWidth => CPU_Bitwidth, preload_file => Mem_preload_file) port map (MemRdAddress, Instr_Add_mem, MEMDATA_IN, MemWrtAddress, clk, Mem_RW , rst , MEMDATA_OUT, Instr_In); end RTL;

gpl-2.0

b251491bebedda393dd89aef551c259a

0.514566

3.361362

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/instantiation/rule_033_test_input.fixed_remove.vhd

1

559

architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_ENTITY_INST : entity FIFO(rtl); -- Violations below U_INST1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1:INST port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;

gpl-3.0

0b05bc9512f825c9a1dd5e820cdf7375

0.483005

2.753695

false

rjarzmik/mips_processor

Caches/Simulated_Memory_tb.vhd

1

6,735

------------------------------------------------------------------------------- -- Title : Testbench for design "Simulated_Memory" -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : Simulated_Memory_tb.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-21 -- Last update: 2016-12-29 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-21 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity Simulated_Memory_tb is end entity Simulated_Memory_tb; ------------------------------------------------------------------------------- architecture rtl of Simulated_Memory_tb is -- component generics constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; constant MEMORY_LATENCY : natural := 1; constant addr_zero : std_logic_vector(ADDR_WIDTH -1 downto 0) := std_logic_vector(to_unsigned(0, ADDR_WIDTH)); -- component ports signal clk : std_logic := '1'; signal rst : std_logic := '1'; signal i_memory_req : std_logic := '1'; signal i_memory_we : std_logic := '0'; signal i_memory_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := addr_zero; signal i_memory_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_memory_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_memory_valid : std_logic; signal addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := addr_zero; signal next_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := addr_zero; signal output_next_addr : boolean; signal first_clk : boolean := true; -- clock signal cycle : natural := 0; -- test signal test_block_i_memory_req : boolean := false; signal test_force_clear_i_memory_req : boolean := false; signal in_read_continuous : boolean := false; signal in_read_always_memory_req_on : boolean := false; signal read_continuous_incr_addr : boolean := false; signal read_always_memory_req_on_incr_addr : boolean := false; signal read_continuous_first_clk : boolean := true; signal read_always_memory_req_on_first_clk : boolean := true; begin -- architecture rtl -- component instantiation DUT : entity work.Simulated_Memory generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, MEMORY_LATENCY => MEMORY_LATENCY) port map ( clk => clk, rst => rst, i_memory_req => i_memory_req, i_memory_we => i_memory_we, i_memory_addr => i_memory_addr, i_memory_write_data => i_memory_write_data, o_memory_read_data => o_memory_read_data, o_memory_valid => o_memory_valid); -- reset rst <= '0' after 12 ps; -- clock generation clk <= not clk after 5 ps; -- waveform generation clk_cycles : process(clk) begin if rst = '0' and rising_edge(clk) then cycle <= cycle + 1; if cycle > 1 then first_clk <= false; end if; end if; end process clk_cycles; process_incr_addr : process(clk, read_continuous_incr_addr, read_always_memory_req_on_incr_addr) begin if rst = '0' and rising_edge(clk) then if in_read_continuous or in_read_always_memory_req_on then if read_continuous_incr_addr or read_always_memory_req_on_incr_addr then addr <= std_logic_vector(to_unsigned( (to_integer(unsigned(addr)) + 4) mod 16, ADDR_WIDTH)); end if; else addr <= (others => '0'); end if; end if; end process process_incr_addr; read_continuous : process(clk, o_memory_valid) begin if rst = '0' and rising_edge(clk) and cycle > 0 and cycle <= (MEMORY_LATENCY + 1) * 7 and rising_edge(clk) then in_read_continuous <= true; read_continuous_first_clk <= false; if MEMORY_LATENCY > 0 then if o_memory_valid = '1' then read_continuous_incr_addr <= true; else read_continuous_incr_addr <= false; end if; else read_continuous_incr_addr <= true; end if; elsif rst = '0' and rising_edge(clk) then in_read_continuous <= false; read_continuous_incr_addr <= false; end if; end process read_continuous; read_always_memory_req_on : process(clk, o_memory_valid) begin if rst = '0' and rising_edge(clk) and cycle > (MEMORY_LATENCY + 1) * 10 and cycle <= (MEMORY_LATENCY + 1) * 20 then in_read_always_memory_req_on <= true; test_block_i_memory_req <= true; read_always_memory_req_on_first_clk <= false; elsif rst = '0' and rising_edge(clk) then in_read_always_memory_req_on <= false; end if; end process read_always_memory_req_on; read_always_memory_req_on_incr_addr <= in_read_always_memory_req_on and (MEMORY_LATENCY = 0 or o_memory_valid = '1'); output_next_addr <= (MEMORY_LATENCY = 0 or o_memory_valid = '1'); i_memory_addr <= next_addr when output_next_addr else addr; next_addr <= std_logic_vector(to_unsigned( (to_integer(unsigned(addr)) + 4) mod 16, ADDR_WIDTH)); i_memory_req <= '1' when (in_read_continuous or in_read_always_memory_req_on) and (MEMORY_LATENCY = 0 or test_block_i_memory_req or (output_next_addr or first_clk)) else '0'; end architecture rtl; ------------------------------------------------------------------------------- configuration Simulated_Memory_tb_rtl_cfg of Simulated_Memory_tb is for rtl end for; end Simulated_Memory_tb_rtl_cfg; -------------------------------------------------------------------------------

gpl-3.0

f41776ba64f993650ff9e9bdd9327293

0.507498

4.013707

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_dc_as.vhd

2

10,777

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block oN5tQGv58ad0TQklq+ppWUJeb7KNziI+enTXsg5uou7kjLrVMoZMjxkV6jourW354ejkuKrT/kAD Na4sJwnObQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block FJ6okuHClgRqD6ZirYpockIZO9fK2XpcheuWxJbU6nlx70KpsxYoCyupKKngvK5C2jf1ONvlvroj BkiNOfoH3PNzIoPKcYti4SH2ogIAmxCCm/FSG2Y+ze45k0DndsmjFuu1l1fF63sy3XNvzijc2ZjQ pxn+5OMxmWiB1rBCGCg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block T8yqDgkeqDZWBEiLh685sm7+Ou5Sn93bKceOpzQP1xPHtpWXmwAbpAwbWPwTYU44J/AXx130r72u vhrhqArSpaXtmy5Go3PHf7nvTpoLzNXP7O0lRtTI6I1HZC9ACIWoES4AxMDXxebKjK0GzhFqYjYB 5F1Ipq6tgGdUxmyXtc2/A18c785S1dklUXS1f5Ii3HRlZemsU+/9t7cySD5EHWSiTIF9sx+7GmKL UjCU9MgHaGcioSCpXxB6Ur+ju47QOfVzKXHHHox64+sOal2Mhhur6ma//2TshO0Rzg3jy14sKsT9 QU6Fcdy2kBNwCBj8O2tAgFfM5ozHMQ7ilI2qLg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mu2sas6InMk1EV2ILj0n93KttbGY4SP/9/xti0Nu96OPFobz+j0qvQ6FkFC1cEiHwG+ol8xFWMVh //IZYmpuAsyQNdeuZjnqSZm7EMWS/cMo+6IncixBL+zZEYkY2+0Es1UOK+ljAgYWHiwEp2FHfgRJ 6es7lBB5FypyplCcOMw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block d4P9EjiQtTxgNXURxrnK8qSPqHjHt8xA1GOptATncCNOFJwu0ktb9wrtWChHh72FQ2cIFKub8WP9 ealyFk2ZW0OH1E1pU2UkIaNVZraKmxdq9gaJK3s5sSYqSHM/Xm/7MzH5b/bIt8eH3nAgEgSdtJKL hV/8eAjjDO+wYpUT3mDNCT8aC5OyCe8TipvETFHFBCBo/CMAt9LU7Hb/Ku7IKaBtIZr2s9IsHrI6 X34+j14snZ/alsLlhNyaXTIcgA4izC+bsl219s9XrniHDjZHKUW2KOx0QX0C4lGCVSrvUNku7y3F 91XqLYJYmDOevgbfe9SAYLPmR7hFuiYeD5riCw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240) `protect data_block UuzWrNt0cjl7oHFjPBZDlq+weV1NskmPnuVZdUKfLHKm/l7uODLgPYKYsMgaRtWdeKtfTg6NSgN3 LVUnsRrQEOrIpqrhK5fiPF2MLt6Y0H87O0EWeDhjM1A737tmqZKlBJg5DDi67drLL1R7G0gximV/ la+kQo4CE8zdij6jYtCpdkNwP1CXNjZFVQG/RYBZ2HBV2o6Xjy1gq7bBSdQaCnCWYc3qntJZnBs9 ZalbB+/CSagRcC9EvIn24gDC4Se68RUDS19red9k7h5sS+e9bN9EJ1mfaYsq/cIbw/8P5nllg4FW Fa5zN+HORUnMNvQWDOvw5z6S3+wAURhhev6prvSmWatiMrjb4qn4xii0hrVFNU0azvFKnL55HyTU CkYSAStmxM3ir2pvBWAmMPl18uEQw4BLHIt4LS+K672hr9LSlF2XdFG6MQS2xsCqUeO2wTomakEw yMQDbsGMjm5ipF7WQpEDosHJUxJczJWH4i2K3ly3GD+UaG+F6D0v2j4cu9ejDNN2r08Hvw8zLmAU 5lzzGB6RVhLtYrFh5kturZt6molXpNDnu1yV/FQ21Uya2YVSAvB/MOBWugUKjHqv/LA/PNGD6tzn fB9j9n2grPeYqeCvQa4kId+VOq0e9229/gnYXrrSFgezsoOHP8Etu3Q/AYe9nIjBhqsKWa1k68uG TkxHV6SzoTCQZ99tr9HemlHTabKLfmKsFy7pa3KUr6Q/cMfT5ARoGY49cvtE4EktDlpJorIrToac j/e2+PZuowDN4TrkjE7WIFMFQcqEWo60OR+K+I5nXNZdYSjfeiWc06UDBaCB2GOgGmAP3VXJTBS1 GmR3gkS/oqjBClhVbvjxpVhpdDBrMxP7/eObiJTuTBXvA/KcaXguZmZaV7J4N0f69n28Ozh562R1 XTluT07glbnYvp8W758pXZW4sFewKmv1QbA4XRFTIXfyZPu9LB/6nlmg17KS1WESEUEZwMP9Kfec V3UoDTniOmv5yGY4DOO8I3By0h02M7XAImEmTuikoizwUIDIquwYzXsMrhtKBSZxtowHW0djTxY9 kXlRsC1yz7kMimHhSpcQWodlc1DONvgPsvLdz2MV1FJFBGcnvr2N+F7bmUkA2jVAWECf+n2B4Pil /biV4/3EG6jydVVuiZEMTRcsu5UIl/MCu2Lnuau7XGnexjxUkxI4tS/k7RhwaVbuaqE+g9q+PTTh /lFj0X7avInSqF0nqp2Yq820ahGEehenHlz54Rn4tvVigiJa4nrBwtpLEEBP4NpyDkb2PKvZmBHf gN23mVT3QqaBl5poN//JueoLkoSMhl/KgiBgY6oGiViits2LXCx0QTI1G8zNE14/14hmz5LfZtQ4 r48HU/y3yKzNDuSSxwKAf5N5RVeTJcDrVv+4iPzgUE9dhIpzG7uiICRcYutIE+qi0O6N8+PCeDrw 0JYvjKfIanLDn4hNSzMsVqsDtqTZ7OL2xscNGRGmJirnqdgyg0YWrl9lIFOYJRSYp8bUHaDb9D20 P6oVdchHzr/7c/81siMBmvVLj1hfh8TWqKiIgWmOmOEO2ur26KwC3DoEolurQYtde3TV0vyJJOKC OtdZV8nKDQBuZ0gxpa0taEl2GfLcO72NTWTgFQ0ot+k6q+evp1pSmPPvp7tCyaUNCgzXb47KY0mk pYNUlTvGNhlTrzxjkHLfqSIfoyH0dqiPxcseI0UsnB1e/nrS2Y2sLrJ7HkwXiIPT/YYYuC/YFE1e 03tSS/0MY5yaCEGCbIhvouAS8zdtWaSWmkCm5CBOZGwd6SWnkj6GChus0t0Ae1xJ5FyStY09/d2J pq8jhAlF98jIarFSSi93LQv9wsK78z5qayES0q7xXODV3+f76TFB1G0wAhhqIKVntKxM8Cfq2cF1 VT8t1uMqzKYHFf6AcA4WmU+CtiWS7U6e5YhSs7kGK6ImBmG1nXewSh+o5146KNOBnjfBsQK/hVer Euzk93jwlYr91CEc6HIH2XoUxC9/ENeAQAhw+ZuBpLi6B/zXO2A7d3QAx4Qg8abKrYkDyviGqe9X u7InXUpyeVziAvMug+ztFyGeliKbvZW4jYR2SNoF/cl4rsbeADov6mYW07JgKCGDKBfkq3PdJu1c MEJTCbu7i68iU7g8YDtb8yKy0053ds88c+6Wc+C97hk8u1S53Qm75zlxhtPmzFThOC0+mp9QIiPx pTDrcFZNLj0ahueWiRd+nPACguYKc4SMoc1TU+azBD3j0Q/kgCVNQ5IG2nqLm+Ya3/STp4YOidNG FqeiNyUKeBovPgat7C6CCDvpHsb3Rohgxk57BDu5gShh2WJBGFgerFDLKyp3vq8j2+2JEyT+i/0d fK77pxQLxYrA7zJCngYhbLbHNmyl2IBH0WIa4m5E1qGYS4H+ci+PNIjDlr4ZSJuISsFC2UC9gnuc bJjgh5wCl5yvMeffbndG1spcLXCEeerKNCEOJI4WsBjbqFXla8Xdarj4/d+9q15UeJv3kdpVVJmn LwaTo6tVRb85eaZ7o+sS0EE/7pS3WTOhGJk/RRxNERpMe6D4oYppqYpylR18cM0oDp45rW1ecqq1 GXdh2FP8dlLIaZwgQTiFNmSeCQbfNhvntjoPgx3UIZDzmV39QBrzzzEy5kmOY51GeHziTwehWuoW m4eyJwp1Qb3dr2ZWQtqwWCQorcXQIkSSQbCU+3IfzwUvk1+VjVPt6ZA5qpphwDx9sJ7oRLR1PUr2 XuC30kiY9eAguwj09lzxqCUONQpzh33X1lbsjljSoSKkvqVvrFSDWa3xJpUR7/InJ+7v25UPotPL 1AQizxnojVWc2smBF3L7mVP/N0rqIpjiivIJsgDo7LFbeKlXjTu6ZRPXbOdqXWnKwfyxsK6a3Epf wqD5vp8U7Foq5JXfVSNDYo/Ykuya5fooodPtcT3RkoaTQRV82L9u7TcL8DdSdekxw6Hra4i2AoJy 9j6WB0dk+RAGdR8+TLhHq88Ttr/55BoS4hf4joeuPtOCizeTJuDg8CEtvfIiKbL9b5gqG0cSIMCj XciIyDV1X4pG0DYSAlEe9WUER/QBVMydY+5i3FyF4pN5On9YFNcEMgoBVKy/roi+LxYZbGqhxLpH aDiFuPJTTd3yN8Q6+v1z8CxX1TY9qsqIF9+g0RiV5vcKFi/H/kYYwT7V3ILVV0l2BtitjjgHMBdz g0XGMeZHk1laKtQeRMj59C0WSiOLIxNTZOR8AgRitvuYBeioFhPm6q30IEWpG25JFfbNAHvUA/u0 pSsikK1qlYmjVllRJ/BoAhEK0OTfL6EYUdh7RXT2CINNARMZM/iA0DGL097s26Kbs3LGum9Wm6CU Ka/HPmVfNw8uFLx3nOZlAuZFFDkXjtcFwCS5Ce6y/1Gsla4IM5XajVORH4+5vORJF8tN5vrLxD+0 nmP+gWb7XM+uFQb73kJR1V9A1b2TaQqGI2JrLTUXb8MYGSDSzTtc7TvrO+cbTjKjgjbL+qGYoE2E ttWqarSK2QSj7SBth8tjbulLI+bLxRvCCo5/iWyTRneTPVbFzWkEk4UIm7GHhk+uj0m6dUxX8X6/ LLUcwHwJZerqdE8vute13BWp2Va0CndYT5OmTh0XGI2gkdgoKPlnSp6Fh2QsgtWPa+PiUr/2sajS eSfHdCLoiLtVs1cKMIE1qB7XSeSUuhCmEO8ChLrkmgzbUqaB6prVchCeSjiiBMXD7E8CIR60+cNr RVpQBjin77C+1jXn7qEp6dMDefITVHkxJElfivikwXtXVoRNLFAujbI8JZ5IWvY6G20gRs0hqSF9 09Zfct3AjdX1+bg3L6aOb+9NK2Va987AGKz97uT+2WL9W4SFegKO2rhVYSLT+gfftrr1eiiEH84E zcfIGdnrjeIGPxpyxxOUlYAyl6XuZ0tH8liEkIUsFqOUU0SO306YJ8Dr/DO5meSnzvzaU9GNx4XU atVSfq6z70QB8F92TkzEMXsdbyO8p3FMs7eUdMfV2Potgwnop5M9fiG6G/JMF2iqcCaeIJVFCDBV btoHC+6a8s9c7iF1igryazZgSTPiy5ERN1eI1W8Im18uyrkxLaL8hI10oD4RcBxJLXYy/9mdaURV V5RcRuOJATMEB/YkRqTRi8xfmx/nQ0jSSFkErkzuEhFI7SsfM+HC19GheL2KO6FRn6BCS5CTGQ0S H8no7O7Y477a0E3dO4+l9YJjpUUw+zur34MklNww166JrZTdoS2ErZ3oFgbvj7DvrF4xwew0Inpc pOIytQvxRbMx/42nnF2lDMEC1Jn1Qg0xg/MW3iEdNVDRygMBZ0mfPefoLBl/tg9Eg95DWXBpFvzK bAEdwQSPwQaeqYOJnR/o3IGpYre6Qa/4Jyt8//Zf7PDqkdE95DdtlsgkmLZVh+jh63JfnhHqiEb5 4k41h62siAtxs1QEA8u1EmBf5YMesNUHTE4JTCh+FyczBjCEPXQNEnqLDnEY39a+M/zalnc/OKlW gQ+T84cPFOHcQLqcmww8CPQuvpLl3/taMCCasONXpaA8R7c7WzGj6uJVkVPYMgTAfl3bKwV3jco5 Qsj0UByfQbFfBo7kyG0MtqlycL8UKiEmQ3XJBbD1IoTYXcap53q+Wn+EObFAARMGSENqsI2Ibw04 pzQm7Ho6LrS3MTonsKh40HVqoE0jYZm/xpP3ARhcMlS7XQB6yIn7v0yXUzdrK2D/kWgWwoU5mNYP 0q79WxMAYwGfzCRlsf8dn74WSEhL4l6e1lkiWf7lxqnK+R5l/OfJHfIt4F/ZlDSxejLeiloTLZRR ZTFsuZs1TftLKjXhiTRJw2ctFS/8WUas7FBYjLBhTg97Zdr2H4IxNHi1rjfBZCiN8V13yeD9ofEH kBRi19oXD0KkynYPm71RIlXy5lvXW+dWy1qKJtjnGrc6M3bCK8+3L/9CPXGklGkJCxhFQqagJByO aLwprCcr1Mm+RJRhZD5N0hlKlWR5TtXlFA3T5S/LOLNcbtJNNMm79vqPi7FPuU40i3ykxUVWhTSt Wv4sSGDBU7TT5he+x5TTn7LL39pr4RgT3HAPfkz+HlSe1UVjMb2WhhLu7az73yPrJfQ2ludFLJkT orf/Qo7Gygmof2+dP+ZEeeQg6jeGjg3kQA/Wre+rVlWVIjEfEgQ2z3g4adz46DhK2lk84jPpqvAo 2YlosgsNlEfopf7E7iAxyQPyfHJoe/+3erkzKvY/ssq6/vvTPjDuM8kKjRhrSbea4I5XY64RZKhm i5XOMIGXE6DaxibYOXwBL5FntBaI/Zs2qdz1kNFut0TEViYeqDc5Ovq78n6v5iawEdUFqmN5Q1cW eV/Oat5ho0RxBBk4FxRFwhJZNfbAGyCOrM/TibL72YYbzp6hMBFHV4zHO0/KvRoToBHs1R9/+AXI gJcXCCJf19ayuy4UrLmYtA3LNcUvU49jvk8EKxtG8igtiA4ZNLzcdvlzZPVLePworlrs7AudUHUJ qo5VpcmnMeQD3t0AgccH76qfdneuWld1Dgnv/IaOwuKtQLfcH75B20cZBf2iblfzit7WmOEgoMi1 2zTNacrLkPdeff621IBOz4CVPlvnQEqsZN4WOx14Px13/bOXkmnaRqQhje4U7GSDdHmmeU4F7RT2 nM2/4nVw4d3P7xwcPYbwvGA1b6dxZHOVW6X+W3SQbAGz55nJ64bM40fXxOD9hr8elVBqgY6prvvX ok+r/hpRBO07W+Z2JOK4w2K+rekN4xe5K0W2jrSmDt3qD99/7HX7t0wDgG1RREktM3Lcz2R95ycO CF2cdtzHB2Bq/M98xrtCvrBuRz8a4ZDxdbIgRm+JzoWrTXXB6IluO5v9CZkB6vLTXiDB2Y+/1qaD aKzc3TP5SfzkH7uLvRjg8DyOpTfuu5adYwyObmx8vgWOpS6IATP/3w0pa/uNnXbOVuSQ/iS0AbHd AIc58lF5CNPdBDVPh8Yo1xf7httfcZGO7iGySHtEKGxWtDiXyFbqUA2rxYMHIVHY5C3O0CQj7VGg VUX5DCD9FbJKjPRmuS8lVTZ1e+MBUwFtLvX2YZnE/KbD9ZtkD2N/6GhUPeXuiRir9UfdWOGcHxgx MmXmr53JYAq8syrQc6p3FhKgdrKocO3F2aXCZbJ0XRuDNvvfNG96l0JfvpFrMQ5Uto/uJBFpAB2c ezC3OV2zpweFCdHLC6OewXwcTOt17E+w9S7PNvwnlOm5snkt7SbntYKgmZmDdshkJmJdMyXI40Pi dWpOnYs0sw95aEKes6qdZitjVMMFwsfVwV42Z0YbQFk6n5hJMsWRWbLmuJbJX8Nf6CTsncEbMbSn x1AwoUVId/WWyVx6PrwmhiuKZSSvQ2eCCwsSoYZRsGjUXqAuhWssqcF2hkQF6fTjri/h4fbJR002 Hl45l0xeYG71+fh5ja5KDXpfk425s8rTWCAPFXNndqiQB0VTOy8iPR5eIPA97D61vZk+oBjeaeoB rcr/aAkHsmXoelOyJyHfrrCHoZEfMOsyv1V/H4FTnFOH7dRrHpXXwQ72Xaq6uDCDfAR4PUmFPB4O WL03JI+qFQh1C7ZABGG38IkGPuISi3EuhREl9VPL/0u6HIWRakeneB3i5o9ZmoWjAUCNq+7rHDNu MVewa4zJV36H6uKnr8WipgU+4y2Q0uj7woC3ICgGuMSG4coAscotMz3WbF+7bqMmc98BYyTtdK8G WdcxZdlujxo/ryx1lsP4zM1/6G59RlUnoatPawGYJciDcbPOaintg5yno1FKrqGo1bDzN1IPgvyJ QdoVLoainGWZfE4f/0UwnIT31QlsGOjbMuY+agZ3Pd17vP6OnI067ma90uIhnY5Yo1fChmRfdPHG puViEoVIs963S9FeNs3MpM7aNKi0OFcwVhtOoCUCM7qySNv8Lf4/wEvD4upb6x2Ti4v00CaQbqcm Pb0eomO6BO04b0rA4Igl1Bz+dkPQR3gsR7BUcAc9Ckxl9z46W3GHioHdXuaYx9eZfIaJk96cKtti FVkujXrA21Lf0lOW5K5byJuWdIMLDazNW6LsWqydrMb4iKK2hGe56XOHpNA7OXBOadARHR9Qh16N DwgYsxxiLqSEasV+w8KwronPVN4hBqd1sRpp72M+klbweZlYoXKzOijQvH63bdQ/+dNhC30SD+qB yqRN2PPSZXqOIX/DBZxIsfTXl4waxWMU3EUQer/dGh4EUOEvSfh1CpoVNn3XlVu+TcN0/gLu/nqH YuqgsP8GckBSYS1n6JUbEq6sIvm2Qd4LyorhpLYIVHvvOFn+lRrRuH1ozizOlqSWo8QUjwJQiARZ ktW88EV4I3CWVC6+CAOfG7DL418Mtr8eP2tEox9su0f6a6C56vdBCirBDGtc9ZyVxgNuxJUSrMDw CvM4htehadZ0YgwLAtS498RQwb5+NDnt0x0XhQy/k7CXLRRE7s3+YYlveaH1KVfVAxHIlHJwbHFd mc714NpAFKYuqKst9GHiNRn+siu987ZfY8MHv2mlogYIwwctNq8P/Z91NDleK0ViCUVUUo2Jn4XT qtMd2bpB8JdcyCf/qzL08jGJYomUPR3CukNxnGo7TNqgl1PcI2SG9m+N/UMjhyvGHcotDsw1Sm+J 1aEfMXOP8HewBUt+MumHQsS64WLcNkjs/mqtGJzhGGBOjocbnX7ZdfxO2f3Kjfp1jCbmNCIUSsXS PcIUpqSutw7gwkWjZI2dpaVHckyrEy/m6MjrdyTYO5UnSR+dxZhnJpG9VhV1Mm3vhytxyAqvZY6C WwBwzlOMRNPgnRU6bAF3VNxrSeSqLzDHtGk6uGwEYTCS+o02zarErWvvfxJ+Jsm30CDcmd2B8VEo FrfSbiAEG3EWvXK6dBwuYpWCcqXpEeVnV2cxGFS0X09mkbToB1esqu9tO/QYrhKGB9fFLlPLKKn3 CeIlitFtZPb2WmDxonVIHouLYthuAQLWh7T/hPx0+KUT/CQmBr+IpIomkUHRR85HtvhlszErTMZ3 dEB0fzsVoY2T7HCnIHAdS5Sa2oLhpdDeGDtl4KS5Pw/W745okMKaMWsPt4gmMkJBlT2bm8xq6Fnm bI5otqEUv0AkHjYQ+mpRAwMglk5l2kvDkSGYgug+nKza0iNl0XGAIinkaHBYEQrVFuzANnj6zA2P ozE1aAxWkVXkHXsANMTRh6tivseOE9bJa0UkF4xXY/LGb3NfszyyejiKHwQyVX9PFLLpghVYG9xO /sByX+Fru/6hvOj4nEYSpjSXPUUV4mY+YB9hFbQwOy+9or396/x7yv9t5j03o/jhpYTGu2rjgQQT FVfOXetxp9hSnlJDNqVNIme9obAucuclKNgP `protect end_protected

bsd-2-clause

7e41f6fb813e7fece779f90556f09ffa

0.926974

1.892029

false

Yarr/Yarr-fw

rtl/common/wb_addr_decoder.vhd

2

8,328

-------------------------------------------------------------------------------- -- -- -- CERN BE-CO-HT GN4124 core for PCIe FMC carrier -- -- http://www.ohwr.org/projects/gn4124-core -- -------------------------------------------------------------------------------- -- -- unit name: wishbone address decoder -- -- author: Matthieu Cattin ([email protected]) -- -- date: 02-08-2011 -- -- version: 0.1 -- -- description: Provides a simple wishbone address decoder. -- Splits the memory windows into equal parts. -- -- dependencies: -- -------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE -------------------------------------------------------------------------------- -- This source file is free software; you can redistribute it and/or modify it -- under the terms of the GNU Lesser General Public License as published by the -- Free Software Foundation; either version 2.1 of the License, or (at your -- option) any later version. This source is distributed in the hope that it -- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty -- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -- See the GNU Lesser General Public License for more details. You should have -- received a copy of the GNU Lesser General Public License along with this -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html -------------------------------------------------------------------------------- -- last changes: -------------------------------------------------------------------------------- -- TODO: -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.gn4124_core_pkg.all; entity wb_addr_decoder is generic ( g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address) g_WB_SLAVES_NB : integer := 2 ); port ( --------------------------------------------------------- -- GN4124 core clock and reset clk_i : in std_logic; rst_n_i : in std_logic; --------------------------------------------------------- -- wishbone master interface wbm_adr_i : in std_logic_vector(31 downto 0); -- Address wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select wbm_stb_i : in std_logic; -- Strobe wbm_we_i : in std_logic; -- Write wbm_cyc_i : in std_logic; -- Cycle wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in wbm_ack_o : out std_logic; -- Acknowledge wbm_stall_o : out std_logic; -- Stall --------------------------------------------------------- -- wishbone slaves interface wb_adr_o : out std_logic_vector(31 downto 0); -- Address wb_dat_o : out std_logic_vector(31 downto 0); -- Data out wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select wb_stb_o : out std_logic; -- Strobe wb_we_o : out std_logic; -- Write wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall ); end wb_addr_decoder; architecture behaviour of wb_addr_decoder is ----------------------------------------------------------------------------- -- Constants declaration ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Signals declaration ----------------------------------------------------------------------------- -- Wishbone signal s_wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0); signal wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0); signal s_wb_periph_select : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0); signal s_wb_ack_muxed : std_logic; signal wb_ack_t : std_logic; signal s_wb_dat_i_muxed : std_logic_vector(31 downto 0); signal s_wb_cyc_demuxed : std_logic_vector(g_WB_SLAVES_NB-1 downto 0); signal wb_adr_t : std_logic_vector(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); begin ------------------------------------------------------------------------------ -- Wishbone master address decoding ------------------------------------------------------------------------------ -- Take the first N bits of the address to select the active wb peripheral -- g_WINDOW_SIZE represents 32-bit word address window s_wb_periph_addr <= wbm_adr_i(g_WINDOW_SIZE-1 downto g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)); ----------------------------------------------------------------------------- -- One-hot decode function, s_wb_periph_select <= onehot_decode(s_wb_periph_addr); ----------------------------------------------------------------------------- onehot_decode : process(s_wb_periph_addr) variable v_onehot : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0); variable v_index : integer range 0 to (2**s_wb_periph_addr'length)-1; begin v_onehot := (others => '0'); v_index := 0; for i in s_wb_periph_addr'range loop if (s_wb_periph_addr(i) = '1') then v_index := 2*v_index+1; else v_index := 2*v_index; end if; end loop; v_onehot(v_index) := '1'; s_wb_periph_select <= v_onehot; end process onehot_decode; -- Register multiplexed ack and data + periph address p_wb_in_regs : process (clk_i, rst_n_i) begin if (rst_n_i = c_RST_ACTIVE) then wb_periph_addr <= (others => '0'); wbm_dat_o <= (others => '0'); wb_ack_t <= '0'; elsif rising_edge(clk_i) then wb_periph_addr <= s_wb_periph_addr; wbm_dat_o <= s_wb_dat_i_muxed; wb_ack_t <= s_wb_ack_muxed; end if; end process p_wb_in_regs; wbm_ack_o <= wb_ack_t; -- Select ack line of the active peripheral p_ack_mux : process (wb_ack_i, wb_periph_addr) begin if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then s_wb_ack_muxed <= wb_ack_i(to_integer(unsigned(wb_periph_addr))); else s_wb_ack_muxed <= '0'; end if; end process p_ack_mux; -- Select stall line of the active peripheral p_stall_mux : process (wb_stall_i, s_wb_periph_addr) begin if (to_integer(unsigned(s_wb_periph_addr)) < g_WB_SLAVES_NB) then wbm_stall_o <= wb_stall_i(to_integer(unsigned(s_wb_periph_addr))); else wbm_stall_o <= '0'; end if; end process p_stall_mux; -- Select input data of the active peripheral p_din_mux : process (wb_dat_i, wb_periph_addr) begin if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then s_wb_dat_i_muxed <= wb_dat_i(31+(32*to_integer(unsigned(wb_periph_addr))) downto 32*to_integer(unsigned(wb_periph_addr))); else s_wb_dat_i_muxed <= (others => 'X'); end if; end process p_din_mux; -- Assert the cyc line of the selected peripheral gen_cyc_demux : for i in 0 to g_WB_SLAVES_NB-1 generate s_wb_cyc_demuxed(i) <= wbm_cyc_i and s_wb_periph_select(i) and not(wb_ack_t); end generate gen_cyc_demux; -- Slaves wishbone bus outputs wb_dat_o <= wbm_dat_i; wb_stb_o <= wbm_stb_i; wb_we_o <= wbm_we_i; wb_sel_o <= wbm_sel_i; wb_cyc_o <= s_wb_cyc_demuxed; -- extend address bus to 32-bit wb_adr_t <= wbm_adr_i(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); wb_adr_o(wb_adr_t'left downto 0) <= wb_adr_t; wb_adr_o(31 downto wb_adr_t'left+1) <= (others => '0'); end behaviour;

gpl-3.0

6d8cc41d9ab7d8e18ecbe510ee9fa16b

0.496398

3.753042

false

cwilkens/ecen4024-microphone-array

microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/addsub.vhd

1

16,419

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block iyLMoRkq8KweSXb/OmiUfaqOAj6jbJITEqxvBgE/jUzhW0RCfnvOo36gHBUdDtFnAKoyFuUHiy69 fx82Km1Tzg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block J1bTW+xuCgfsRF1zdVwqPHCrDAty0YhqrEZfeGbg/VwnvDcdoMSVUaz8upv0EKwQF+L4EwMcjEv9 dhR5feonU3gMHZnaO3/Ro1symRiTC37GwMaOrLUp4EjxiFUlfzIBqxxPRh0gu62P8KuR9kHOh0Yp t7+rGXHegImBEcBcdqE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hPPna73xF0f7y6Na91ioJYvNx3mAq+WSNuaYsFgnW8gpumRZGNJbyCNkhOilWBBRjSOvhVoxOZy3 GYqqGJ/5965xWrDLg0WfVKbk/TfzPJ8gr/e7J9zZEzNg54RgcobugAO+DGibLEFEfhfLAOFXpv/2 6c5sDKIp/+jacJmmZveCaP1X1oglH8Af+A7YOqAIom2hm0aTFIqF0czwBOaJ8/LolISU4jSIxTYL vwJJcY7WMjapXoQ04wmL93IIT8mR6z+UiQ1I5grNaZdUJyN6eAY0L6iW9wQhVe4H+sAt9BF/Wb9d ELxi9DpxjOvggchMMjYBnGpeIyztdOxRv61DTA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 0OVcAsV3fB9hQUJQXo9MT0XNI5xANhjWjnB/R9VKfA3sxb1BrWn7m9vnlpo9NVYiFuAdjbPa0+M0 3um9dLE2RiiQ2Mvvd0AMA7vBaVGeiKGMpxF/ks68FaEesusfTiAicS+9j9+GzzUD9FUoDyKNJFZx MIkpqTAsNhZKcdM/xTI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Gr2odoPMguGX+M0fLWWZNn5Tbb+TxZGInwpa2GGPXnVUaV9L9zuahuvXmZugRjm+XCrwWfyNLOj0 HDggLbt7bmF8+cORvJcmwsRrrNJfkuDr2k5H0xw7n2hKiZ/ZSXnTGEuDvmHbE2Cqr0JAsSoIqNqa hvVgEvtjD+lL6Avz38NkdwSx/k1d5AKfc6lF1hpTDR6NBDW+Fpvmqql9bVAWQbBKF2+7bCgcCCuM wHpENYW8SzPvg6pH5W1nyKp0k+bPOpr5ntSc9zGlrTgVS10MQb9UUjHZy7hZBiDAj2zdfjO7YlaT t+Qg2f24z1V8gkJwAN/4dAzQQXS8k+YGnxFD9w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10416) `protect data_block flaJS0+sE2jUtvWfB86YlOMP5tXkpL9xuV+/3VGgNg+WiS/EZCPmSwF8GnsWcdKJpnNXmXEbJC8w CSkrr/F9ZyCU1DcdiZfFRTQxC79JRlH6b9KtICE5r0h7nOVN2XthikB3CQ9nMluWGzVXvw2O/+FS bwtuvBfWtZJepYeypkUUY0lQyDJYwAmcoVQx+pIaodfCjtfpYdgUccfW7R7zh/XdfBpJbtV36pyy cOAGohsEb2NwMGK8u9lt7ELIfJ9gDWEMgXyoH1jQ2DM2xVWGgSFh6WoQO9aQB9zxAwfXCf2QKs6t d9uUQEefCLdNWPBuxER5DWwItjFPOr23yjbY00jJQ+tKxK4MAEawaxRasxNVDOB8BO8+c5nU7psh mHmu/B+2COg+2sGeiNdSsoqxrllNOhUda7pnaTvF1ZhAzOhAwFv9WiVd1u8khA2Ea2agPyezqoEj /wigvm5qbld8gvifz+8RIIDvx0z46Zs8W/uBvFMciO9+X88sSzi7KEzNgSD6SyrAJGZ1gqaolloD 3be9GODQFNNDofu1zBfAQJaGV3tfkiOPe/oWHjwzyCBcNMcKrwCQ+IAbVrhapMLwvz3Z9dEr4Zqo 8G3z9k/b75vRqjY902k3/HInbMlRT7pZzkY1RQ4WPPJDcwaRTJcKBq3e+9xuJUH6uJbo9F8wmSy6 dvWJhTKGB6RBThkeg7v3hZNS8KSzwx1CoCChP/4sBLwnSagGa4ThDY7N2f7+AfqPQcgWObLEP3GA c1vpVSaFmcNcLJPfOXaf1dQyeL8G5EO6kuhCCoBGHG59kyV0VssGrXJKBwSxbvQKJVK1kpCJyGy5 zHS/UqIIwyu1h3CeVxz7Ql1qp4kOR572KroiRg0FRTtvpjKSRrh10PJvKsZyjE1zzOdlZVVJ+1+x OsHgdcQKIVn7nSORF/NgCqMr4T/hvdxTXbSBE11ztfLVvA5kfcNmpotVRKCEJqINhagGSHL5s6u3 ebE6GFPtypqE8t7HWaeBH1I01fokfD2FEetYQy9EqKYMNEkZNJGw4sj8F0kh0hPTM/BmXjk8vVs7 CWX7/f6mhw2thb1K3l2s+LNrUj7BeZ95cyP3l4tARXlFkjhRkryz58236PDNRAAHYC+dgbSTBRyf Bu2X9GAirTxiU8k+6Cz73u89/C2iyPRy9uTQURk2jWQXGucsrZLjMqiWXlA02Rexh9qDfbxCmCpo vDV76y3s6WrdDzZIAxjHXdqtHWLGAw/nXyH9ls50m0nO8bVn57glHszA+JFzJc9m2ZCjUnikzVFJ en1S3BIGOyIwvhVg0OvfvlC/T4W6lbys6RcNzZZCJZBIKL0F8X89uYjfV0Kdw4N1RLhafpAN/tuq s2oNhfUTiyDz7sX4CZlMKp8dz/ycCBJU3ZVhnv7Zp4x4LZFPvSbaCvMsoEt5FlBLghPS7asEj/bV FEM5Ky1A9/iqrGbdCfYm53TX4pk/yf7EtGQiOBnqxhLIm3yhrzW2R+VExkLt3zxw4ScnGidfaciG 1LV7T+xBEwIbt3Ie4vgeOgjUQkLofj51HjMuexIvhDPn3mzbs2cUuS8ZmDo2CrAkij4pjLHpXCL2 kCIyhDiqAyxqyIHquVN9PWPGUZ6q3C7v0nY4mHXGpOT/hnl82ZXE6YU78acfWe/FVLsEmFLBIXaQ KF7LiLzEWqhsOBkP6qUF/yXxUZnQtV7dDkfcEh45alARusBRroQN6mxruUTe/OVdB+qMMjZSc0yL VTbLEPiWkya5tdDKXUSdGv6jWIrZyjZxnNq07cLxVEqZ5fSq5dYm+sEb+psC0zWFiDkg6s+KXPvi Eu6T7iNB8FWF2kIw1dLRUobZIr7uB04+QeUECT5eqV7dV4Dk/bIahAwrvauqXk7On3T5P+Z3qKQW 2uwLtIIvpk8JRoQSF8JbQ8xLeN/7lhkzxNcyi5rGaVwYcnSZ1B/GZzaGqCoKRUBRZDQSRAhHLQUA /4NUSPxtm/WrN7RZlWYG1vGVErtTJOYXPSkrg2kCHiKehpflzNTIRaSQe5pcqY1mBmZQRIhAy3Mn fkNVKB/JWQYD7MKHJLmIKqGtjbLzNBVWA0hwghRLLOIfYPJv9iPkejdLAq2zlVbz2RE9lhguJmHp sYUiD6esDWGwQz1/PfMjoQBJOk9osn49rm2fTfmA6lgYYf4a4NS99XB1vc5PF6kxRkOqvJ4PnsW1 uivACoGxbQewzR02+p2MelxLJ1Ddd7Z/olZ8+Fsoy60Q2vkvO3zTpgh0sk4AG/HCwiFaP5dcXE+G 5P8lXWx2jxilY652YEXbmIrSbBEwTLK3LDq+ELmzKAu218V0c+ZFYckls2NW13blMx27gQJpmQaJ SMDr/rOIAO9MJXt9v9itgWHfNp7WV1uvXbFYnhTY3UUxRQe4SL9kLC3UmcB71VPz8VcCbTWg2eC7 HCokG1qY24PfyZbx+LHaJ8GZzLqlOyTBSh3kE9g/ObJk85pyrk3nywKrh92LoI8lTtJZDhUl0Yvb yGT15yEr9saCvQYVb1duqglFnxCuJ0dM8JxJHhnAzHW+8i0Mw/zgMg1i0A+xokiImwfXXuf/V1VU KqPizrK2+GlLU7HutoIVFt2LaWttjZnx6vO2IU5bFUaGn8/bzH8VJZp3L9ySmeppWe5eQTJo3mSP IVQ8nsLbQbylqXJrezYnEkTzzFefjOzaKDhwXHkKh0SxLnn1JvGKu81thLatJR1BskJm9GSUco6s ZX8/RNC7N+TimvnC5Cuh86kqT6gh8BJBxbvxHfKPPMmBfCT9hS818ydLQLKuJWJ9hlmnpUOnRjYJ 4UbqB81qs/UJxkhZ41vdweHC+VUsUqEgn26J2NNp+D3m6pUfqes4l8FMtuqJm0tMMimMhOBbrr46 anKW9KjxqHHi+insjWSJVLPRrmOeZ4hxSYVCoMO0lqQneJzhVYkW+1T+mHBtvU5ZQdyjpiiXPgwD tzdz1+7m2DVtRT4ru4k28t05oPxawdPsCRSWAvahABCA7kRK/+Yf9wNEhg79CchJQYsDZwCLOAJh 8b8odvnAPATf4DXioRLOQIYUI7qtdcForKIXHcOaUYMq+ZqTmKRzxKKGRrI87rVZBGO7xGc9juZX v5RpritIjWkXiVXY2lBMIEAvG27h4yI2xKvF72QPaI5j+D1Ilfc7u0YUp0LUj1yFixRsDY97CxLA ah5hHWiMOjE1wrh7qbmb6A24OhF4PXSvN9UlZ/FYADZL6SjqS99VOcgTU0cX8E++CwZ3vmKVWjRK i+vqGItcYjvDGJmafoEswmITu5u1ZfNUwM822WmFMyPS+e3hRNi4E02HCR6nhmc7qESewBkcy7cw /D1WaT5Dp3Ug2knxcvqJxdSZFhCZ1yUX9R4yAHMRHaA+Mx1vBwb7cTCz+YQ/SQkYO9PQ1axE6wIx /Dank2kjRLioalbsnfoWYBe31paRPW3EHu6ShrxwPXUVP8vFuUcvAoMuhfs6ZiDo7q5PQEjbP0zS 1tLaNS/XEcDpV//hFRXiRfr6e6L5P8RxYRlZ0rgxFu3MkHOjcF2OYgvMe9W+UVW2ESt3M7LVD4MU HX+U/vPp77fmJe2xNWoAmgEI0Sfw/e1lSd31z6Rip7AIo6tN7SMO9zrVnWzQ1pIMw5UxnTwNDJMP JKhiMobu9NEWARnEDMThCH62gm2qM4mSuCvcOGrsUc/k5N5FA7Xo9qgcc85EC3CQgz8QLOilqSAn /Foz+DsLl8DX2avRXIMoWE0YXig+/45cXHeHGdArwxskzW8gE/0qs4dcrZkK0njAJ5CSdMlfrzjA R4yV4vxkcG19BFo/VjHAQqi5wAnN18sbv4hOMfnM01le7s0FGIG+b2pU+h4WnOXjidT5GeV8F6IP fLFwm9r4D6xI5Hz5TcfMr/Lu4z2swXgMZMHvgPjId0Intjje2LJ8GsNiR3j2whsN50gfyvm50gWR PZ7MWP6ZxeDxeHYM91u43m5mQl6QK7qca4BzJR6VgFl05m5l+BNxYVetM4zvahDYv+q4gGkbCUte NJCUws3VdEMaSlbBDqixmdTDYXNFYSqR4Ud85k8HholBITXwZm5dEE6gkq7HevPyD8xLQk8j7V8H Xi6pFD4++jVzqNVmMFGdVCTcD5Z3pXin7/uVOnFYNkgNn1BeFhKf/1Fa9OIWactdUrz1AqB9jpx1 WtwTeedVjGPKUDLpW87X1opZ/ldlQVSMN9AJM7X4qFKCBib1tUeTC9oyu3w9rDYZJ6wdMc13RUFU bbjh2TnPeFZRRYtCH/bQt+UQ59mBYluYx/GdcX+Dr3nWP0gT+nYD2PCyIukMIe4ms4Lr1QRTqn9W Qy3oT04ANEcdA+X2+PmFn6xvzIOE2MeoiGB9EFyuu9Yu9w4Zf4dU0p9hb3+kPzKllkv/YjrP/Uc8 PHH2bnvpfC2OLNPfOsDg7ZjGingXYbwj6eu8S3okqFsCs9vsy1n6HEZj/rmiaCHIJLD7U6Jj4NZP EQzmXk1raeaMYUp9GcDuogB6Wbz07vIm1Vd1pCwdxHSwH8p7PC7fywvVQm4xvge/5Hx9uYChsTRA wZtM9ZluoXnVCfhdUoYXlp5tjP+0AXvZrypmy8XDYkOzIWGH9md+IXEX1p4HloVdrpFXXbRfuNbO xd/3d7yTzXKlRbay7VVAG0M39KyuBlvDL5whn2jQlGJnmKEgXV6tevCNhA1T1D4cZ8kIG47hHhZw GxcGiKT0eMa8r0oiiZGQ0gGFQeW0+lEkvDPYc5aYnKBin8DQtgbgmY5Cq9IFcroFFXS2CKUioi/N QTZK3OWkiiim06d8Ll20hBlATge4m8CsDB/hvhbvEv6NBdIXZdSqhXvDT2pJ8S8eXwTsIW3j8Nry ya2NYEX8uSiR2OoEw2ZfuKtvWB7lQAnC+oKZ58ppjQhWne/bVqtjyLULqN2pBrVHAVoJFvKaQP/A we7wOxqlzi+ZaxSmgpSCAFMju+8+Tcp28dXpiK/GnA4EvbK+SgXhc5779lkH+WFdjAeVQhOj7H04 SGBDZMsG+T8naeeErJ0/88Jg4Krhg0qsXvxk8YFy4j9ePx/sF//d9rr4HjkbZdrsERUVII+XTylp PctvyN5FCQjNWnWgkdjIbLBJzu0Aag8ybI/jrLGYR3qJNwKuPYid+v947pepGv741StOa+e8YcNS OheUrAiRtc5OES61wFTWmnwIdCjxWfObpIYDND2SIiWiqwUM6TlhUpmlPndr1q4ZXxZOS1n3qXnq ftjvs5k1bSvM3iOdquq9M27ORqAoQyY6NKlayxX3cDisYaB/0Qq+H2W1mNPPVY5hFCQFzlW5fLVZ Voz0yGJBHSFIcb8YqRXuMTYul5S0XZ+3NE/nmwR/sc5gFiMKxRhNioHTpgod0k7XQk/Mtw5Tzu/0 41/93Oz//YsIf00hy1g6F+67RLa5f52TxAHTzq9F3rvfFq8i9i2a1QU1k7i2DpQMltfGM6OnytFA I9y9yL4rPUSIc3WC7hQ6XanZmnyoj8j7gnNrMnaZfq1LtNy7Ybxu3P8m2gck9/SD/trxdeOphrWu S1li/Yx684p1DiJcZO5ep/scrlgVb6lc2BDfxGWP+OPmipF9fjKBYD4XrvwERV95K8FDhdiWrICf DGQBN0STRgE/4s3KNNoXd1LZWaKZoUVcMDLbs9m51BYExEy+w1uvZcS9itVkEkJVPXNP7SvVTX4J AgSJa7JJk+3C5IPpDvlIIW0j+18JI0mNI3UrZ4FWs2sxEjbUifXxAniCci+tbMTQeovB+BLan2NF Dm2aFQNPe1c6lRvHNON2xUYW+K4ZEokTKZJhXCGxRxXUWRkRYTNw1NCEPbph/7D4uyeFS24lxcaW YTseniBRJXDUEOt/C6MJUBkSLWxrXJHpvAkx6o8Ls6RPuxQIzKDjkcn2iLgpktGEplam7qPT6xlr DwGEG2uGVnwWTJCEgjp1Vr3JHUXQ6eUNu6++P53W3iG42b4u9s/6sNOdQrWLY0rBjFfY6XNrSFFs /RE8p55lg9nXbfN2IzjV1N8BtPz7yo77SQ24JQ2EETLWGvHxlPM+3N0g87XqcLNVhL/jpkc4Wiqk GNbkC7MmCU7pgncGj3SCcDe3BOAZDwpwkRRTVEjrYFpNwyxm5C4QE/Amjqji5GHlAqu86Wu7PafR RFMREU5eoV7OH5xy9trowAZ3L2mS+J3N+YLFvHq5umzhil1kF+NJGecNM8pNrYAwz0SE9JWgSPhV rAHAJ22mDOrOpDqSGWR5tfRXxdz5CTl7dcxRssvBmx/ppX9SWQKh4D/uFxrpQJIL14SUAB2K1wti f2jORQdxconFo2SD0N40KvThKZfb13u/yb0yPViGPVguWBc/FsXCV0UNoyJ9YDvhhDyWgQdMzny3 fP6HfEaaLogCW0cMvz/PT3SP5VjNHY72k0ZEbZFDNJqm98H95koZwLy6AoawnK0lQCWtgjcEDZUu Bfo2+GpRN0wQSNC1jfxXMeP3lMKJjg46Hrq9jX6TVH14iaLfq95/n9Mx7SdV5nByUQtVURBZJ410 Fb5DPK+KxvHwhVpl8qJege6tCaR3hkvpvPiOPjks4a5TegsUEa7umYto+GxiI2wTptkmI8aKFDIj nk5u9YzMrVsZGSBrXg2qqxlc1VbBor7WrPvQpM/8e3LxwYp6sB8JPXcLhVHBJTQkLdD4adWxIl4D COs+tKE6SNf2CNRXELO5yiwm1JGNR7cGGlFzCqAHfHnvPpc998QMKtz/jwkebHk3qtG9wvVSKOPg V3ZxPBYTpyX0lYulNTwLduU7bLzwi5sO55927mFigJ7tT1PgO6585Jq0xlVCMGy4KuRoOeXOhNDK 6KS7jTLsC00F6/lY8TAqCv9GhB9YSSuOuN9q6YmSHylTksJMePnOtKNIsq/Ut7USb2mWErkzgsOA JNjq++XOWjPu4jHhBAko2FogmFRxmvYQPDITykw3Gp2ZVWGuJAcYkYczzIfIAzP9WPO2sDoG9S/r w079I2WBuIWUuCn5LAqD0X80qEA7vlzPr4OPqEyPGdzUsKDWku1a9iiy1/mHdfWP+Qp/E53/zkYG xh1GG/KdoHXHoH9/UP/9CeOpsw4b6cj59XhUQFrD1MUkXiXzC2NhhIuvm8R9OiXmlCf+CoF1hCGP VZ9BvgYLqv+zz2yaUkXL9pXOx74RJ65ED0c2OiojGhMZbBP1vsRoNPQ+TH4leAu+uqLVZi9JyCc3 86jzH6iRCC9cnR0WByl8P79JlpgEJkMLfjPIUM3DTWVvNCzuIzlLqSjsEk1juMViWSAQR/gWiSQd 8SJWj3tH7DZLCodvIKdVgIqhuk9XIoDkMBRTk7nkWoi8nbnFRNZrs5q6fMdtnRGO552oVtwrO0LA FFbb6kmZMHdNoIFq5abdLfPmLTGWpaTJk2dl7oKIILZo/DNnYvUZX05V1vC1soAc5I1k6Pz9b8ES /m9wmRI+1ZLhFSCFhbVrMge4ZsITcQf2SlwCnZWWlzb7esuJT6Wem5mtnN6ZLz2vFIMwk0Kfp7yi 7PdYF7068yxo3H2fFhqIOYU8ujuxBIey0ErZofOxEYVhjGBOY9laR0cRtj9dkNKZ3oSgABM96ihW BBwdRg/0V1GKNfgvhlcfyzOYnpwolhgyFFxV8I/QjzaqT7xYKMor+kXACRl2ioRObSlvLi73JdK5 f3N/VAeXIFzO80BbYROeyEcp4TANCk8B05dDxv9aZOs7qwENT041uf2Ijb/cEojgNL846YjRx1RZ DIEJCAJdmvaietCGuOzGEjom8mQpUvs40pWfj/rJ3aLjuV9Anvu8CO6gDi8jbnbGVeTguJLF4w6x aUR/rezRxpUuB7tNDKYrR+bufhDvrxt7kgEs2M1oLTLY22w+1lb+vQKMNsqhSRfvL/vloH+ExjLN dVsQaIFBu4aiYZjZPAnuy3wXC/WksHbe/vYxDERYWVYIflE7aAFQw1N5rTxSJm7jSo1vnhTn1VZH +zq7jNpkxn+otIEwfSw5OHl8J8SqgnPs2AtlI/qJGdVXVyhD/WJkKC9qNIuM6qHq8daJ25tlU1dK ufEGjkQ3cxi3yHsV+DdhmWbdy01ewlZ9D4O3bKGdl6M5Jb2iIcTQ7oX8rERiLVZff2dvA692JfM/ DSrA8ihQF7iHhIM3gIiiR6zl8WREjbdODB7AJu+ZbkdayxbZs8f3tFC1lcNMm0xsueh+GqVd3Q/d 8ZToBX8epz/LkLh90sdhzTjhdrf4KKhkVjGar0ZlDY+k0O+EliIN+JCrd54DKVOnF89vjWs++d0n +qCQQJBYxviTbus7MyEi2QzSNrqcTPs/82aGe1Dhis3FDzbBuKDm7u9rZ+JWHzwAiSVxFuzbm3Br RFDvV7iXjUSNsI/1+gAPaiG5NNp2UJbhLny8cxpJdhrPMO57pKZSnPTeoDC7Euhjiag8yVw322UM MVVJaSZGSY0n2XOr6DMiIMR43DlovTmG8iFNFNqrYg+JUPpUVkt9E89CAoyPKngjS5wlhp4NY2Vc in8dvvcnN9vD1I7KSjxglHrSK88FDYQB5c/xIBf6XuE2ApykEkKroLgmnqTIyUjXm4wn8dmZiaX0 2ggiPDj7WTUweFgY64M7+dS+vAdQip014z+R2gi7HrHbx0F28iFrvZbEhdjjmT3+kdOj0aswYnse dm3O1FHmat4m6cry6er4mWGA95qbPAz9KDE/FmWd9ES1q4JbxjCRfvvOf1SmcTWrTdkeA7xm4uUD rZMVtRyTanQ6/NjnNz8Hahaiz1lbIZm8nWKwAWuQciQ6DqdrAIOVtgwmhLLrhAurLogxhgFN/rYC fk833QxLbDelETBOgdelIGSeVpeNvoBBrQbdDn0K7SHsEyBWYpx2+Kq7qg/X2KcBNGCyBfqe6R8s m4Ik0QP5f++hfIJLhDpq4u1k4dyrBTXVRz/dPbE8k/ZLkz+MM0xkbLIGzva5Ckys5beivV9tDatu lH9BAZPfX7Z8EuhrMfmfXIRiV0MTV0HPtBViVPwHKyJAxWZvLDFfRRBwgpV19saWCDs7NEVZglcp kBP3za6R+YYanMNrIDi19h2Af+Xp0OsvqEDG9IdQuZQRoS7Ot608i97MnOrlkR6ATiJLNvmaUgks 42Imjbe2QNaP4VsnwWHtXAZ/x2WfB8L5r/R5jqdZw5JNPoRvnsiFUiC+pPg7YQ3HQPJOgFlQYbfn aynFd7VCq8mJwHDD2qipQfZLybwz8VzDD/n+lKWctiVXzdnYnxwKZelH7MCkOWDfY5A9xQecBkXA xHn7vczfRA/TIswBnK4R8r2pcChFcvrJkhD9rSryQo/wOPwWrxmGuHnfAzKDBj7mnQh6KzKfYY6x 2425fSFKJJ7dgDmBFWvbIiwEOP1fR/LxwTmr099opAguAJCzxfs8a6PUxCp0rURnfdQEeFnwkkKM NYPjqUitW5Blu+bKzQiow762sBEoEL/U6wuos/v9vjpptyMQdKM/LfEepc1YSrdysEHjxClMwAjm 85gaT+NgILoKLGwj/stCjzVupc0PsKfiJqMKYTCnoWXzaIpy9eeeUFSlLOO9gOWlECEEAqClXwaP iyvBMmXMoqMUFIEw9u1s9xUhLghaHZwWPaOEzyv3/ontub/uAqJvp3//EHJ/Cnmrh0JaVLRVUz95 9/YkyMdggrwuS8f7ySthgMiUbWVdbKy2FtxsJl8a28Dmlg0U7e4qi5v9/0UiC7vclZ6d0zyMGMjU UviRV7Ut6A3CF431Ur8rjQCh45li+j2Z9cubWQ7jC43zVkQBZG2clFR4kjkdlozEGNGAH8mNLFQs xMx45QU5BHZ1ehkuHK3ao2mvQCay8btC6GjtyJQqONGNBkkWsBNQazL5zJhm2rX6aR8AJB73vs2y 7C12PaMgnJyIpH/4PgRcgYihKz7LdFmpXusuh9rS2Ee7htJwMZd0xSmJ9gvbvtx2fD+iIm+xtq+S BCvFpOu+L4hqvb/ye0SIamsUjf4ZFsGU0ZUCIbbbEuJe2kBW7exp7MbQyNdQ20GBs0QcfMtN893y 4fracR/0CmShi/lBRKlbOiVN0VQVdORab1WTg6Z8RMg35upjutiuWemTGn5JQ8pQt74TOPlub8uN mTWgr4fk84iiq3XFaG8Qzv1jH/Yo8wUQGhXHKTWMCW7sPwhrzgnvU1bgQ0ojeP1/eCLZnWUwKb3+ 2k46fjg2pRZRRict7hVdIL+pfwBdlBfB9TiwKeeT2rXUcoEYAFIjYzhGmeWZGg37mc6IS+3DEaDw 8JBP0YJiR9dMCw1e2LFA9GsJJBYw4xW7qIWIXtTlzxmkL2fBXZpmMVrZV1cAGv+r6khZwM6e1BAQ UtvlR94tbWG3TYTlIhgrsUZtN3F6mj+x2GRR/zKGY4sGFJCQQJQjP5CoORbZdk7zKDYuyHRkSiu5 v9MU6FVaGsGywLq9accuQjP3LjG53GbZfWlvV3f/8hVMhQcFUj8WmOpymzZfDyQU2VoDfOw8ju71 qFjdAgpyslDc+8iaE/oDV4zd55ceCsymJEAtDZUWx42MKY5STuG1mt6eS40MnpBIbe/4tkj9JNLO qBU4nKN2Pm5oPYAPvjqKwSSjpT66FS4IXsZKTIE9/vM+y2NfIu90VBD6cWmHMH20ZRRaGpHaEmFB 1xNEk2ihOONvGK0sieOZmDVLd4Jir9x3085ksA86bGVF1W2jOgsBbfRYdvO8btctdqx24qsOS3fi S665KslAY+rdl9nACLoWSpz5cBvu0mQzvH++CUkajQYG01lmkuxNcMhI4z6OY1bI5FeDXAUtGY31 8UCeojQ90ekV4Hxd3ggic1pXo90upI/Kg3NY/Jssg6rCcQTMThJ55Lfo/x4NShgASH9jDiNTbG32 2U5P9X6/dTcvdsOT1rBeKchbMgxHpYa+xqLk4ZYTqN0oPT7XCc9yEocVhB6Sw16cMA0JGTzwFAxu 43AnE/tuW/j2IvnIk0ZLlWXWJT6F062q9u5gTgO18itZIQGdofF8/k/MbiD9uRH46tBc8EjgW3Nl W93smxHZO288VUCn4wZ8Hs+4CdVyZ9P5v94kr7pO4+rUPLSbhL+D2yj6FEfXZOgaP7Vxh8a7VtJl dAk5Sxbm9D9eGTLqM1Tgga/dmGXBpDEjK214QP7uyXqM/jSA2sepaXRMdIRSru5Kjm3VDE6zHugD 7Bk6LdPLjarzHscmi0YIpghyrzgsaEVXd9nBgUp+Qb/2Ht/9HOSCoI116nPp4PenHIHOcBN/C47W xJioMj4yyI0FzTAXmj8UhZxVNmevBEc7aqgR0aUwcKRQN0TYNRpgdEaMThB2Dw0Z7yo2RcZ5Bh3n OUw7ch8PraMuzcPSLcInusmjCJTLXYAL8g1OklfiCs1XGPpQ2BlXGFifm1hfW5NDrtzpMb8fmkqw TtOCapIcbwLvtcpPCFrTWB8UmK/7ccRrrf0ftypCMzHrnA7OvzKGRI0s5G6TRwPm3P/LbG7VXz5n hlW9sAyIXuVw+ratBmycv0J8aR5AaasqG1OH6U+4oDUYQupkWYItzjo1fF5kzfogOyZfJMpYL37D oXBdoJqTkQWGf6EIdvucz7Oxfrf3KhxGdR1vJtlLGsN8FiA3GpSDM5KBfpmmje1PrBiJPHI9lweO GmjydKHW9Xy0Djib6lJlWldwz5q3ag0XPM1VkdcA4EkogLkPjpZjvDr8A5bvqwNIfG8KJ19pMk/F rgeFSdArd5+Mj6Id2rAXmRKaT2m3N9gTGJmBtB5dpT4/umLb1snQQBXX2fbxx0JR9iU55B1b+90z 7atOUugPjKHTwL4UmNFxAVtD08WLNaWbzRqCw0idgd1yrdHi+43JsnXTBDDIHKoJEv3kSXz0OyVh jnygGBkALY7nOrVlEMoGDNZN13h7dLsYrW8ZYtxRcoEMC/fgWMHFn7hFabuUNs1fNbstqbHIXxZQ 5EoF4AOWd+C63Qjyx6UHrf/cZM7DUjQsLMgexJTW6QkpoqzufvvIG15RYsVf4RCbg0DDiHlPpF66 rpR95hILYMv7avePDtUKuhmW7MhjX4ADX/ekOIeReiNb6YoA0dvqU+m4p6alRAwnlyT99scYhMXM h7nyPkSyJ0wsGDBwCfd6z1Hna/wjryr8sHMIcIUvSTWr3GQ9Mhi5jNPKjdibzvGnPwY1KmlxZ5Ce spILSUti6Il7nc8466tG29f5cbTl704OnNtFDWc7NJSe8oQ5NEZ+xo0GwksM7h1hChrp/o0IKgKh GSN4RIfTBGUL0IXd4/7gFMeT13MG7gzyA72iPq3G1P8w1LdSWRHQw/RX7TA6FK3IJrF0Yd5ttj5p oI0/D3cLoep8TfAtvGPun7gb/n2qVlGdSGw8UsZ6p63jds7vKa6VzrtI3Zn+nG78HMRPdFK4mFHv Du5dV+9FAdIutFMsAFAKNnhHf0aLAw1fjroNqUw1CWcizZb1ZT3Fm6/3hdtF3sEMfhwGa9k7byWh BxFysym2O5TStwTTV4SFuuKrUGUstUIaj+/AtPkS2IsL484EftN9DQsgQM9NOdGdfBjFquUegJ+P HE9BGrmIIOdw8Pi4+t1xzzZr+DVkjkWIzw0p813L1Y0X5yJ+o9LEw+rqSMcDexTzRF7i0MjO7Cyw aLSdJmn8x5HujU6j9QfI5DMrBl3NLqeB7uPBkVLZd0FujjzBWf1g3FZSFu26Qg3B1/tJSEr6crG7 BqxYR4enA/FayWoECNsbPtCEgi7xoBZuCE7HbqWKYEsh91mmvLrEjNfg5o/4k3bLp19YC3Rs4c4b WR062yi/ovUhQLfV2YYuuz/SdzyvdARn3aS4oKtxLj4Y/o/38vzK5wDm1fbM+82c9kd2SatIV8Pn PmKZwJgWwWvniMCrrPOk4d3xKF03fxtrHyNeoxTmZckneFdNt3gpodRcLu0pziq3BNwB5Pq9DCnd JxV1KHPfKQOV53MI+Jabz/Ppy/CWo3vIn6zwApnBmCjuCYtSftabb0CuxAEcuYsAf6gCxXGvN6OL JsliLRLVweHEt0nCgGuVCFPyiYMbBVNE+MwKMzedijmOSIzZPlspBtvpb+l3MdV8nSyVkh01AJiT X+6fvW41zpkWwQkFbMEnyEK0eAxlfOLby1ALO2IQwZQ5+KEFtevnjc+xp9+7z+EeEoVFLCe3Ch5P ZNP8fJWxR3y9lIVpdczoADfxuc4jiqTMxnN7xfF9KvIJwXfJj0n3m6/1G1ufUeGdgsFQQ50OKXNh 3q3lrjbuQFR3SHXeHQFyfUrqoZ9Nyq6ofBvM7dRlLJhAVnDYz6kOvpny061gbB3Bj/LUxmVX4bVu GMlF6C1TcbSHR9ko1Y00/7OTxO+cEkaUrCDF1wm4t9oc2SyA9DvaWONrf+JC7Tuq+EViJmDV5vnj w5Sgay0Js1Q0CKoYd/1NtT7WUHEvaZe3EOWkaUuJ4gOUCtU1hjkvvIWjJh+WnHwu0yDb7nyOrtd8 A50R4gJHsipCAxfinIE7eqL5RnjVTSTb7PzxcKpVIQdoCQ3oCQnTqpKqSnvLx5fqxBqYCyzPvAzp cxP/K+qcCA/CDp0+jD7hH9VBi6cDdLjwFgFocg7NkQeCkFpvLWV/t9tJ6q2k1HhYjThnGh8yy/9B syiluPTm50G5Q/1tdo/bS3Pjrbkp5ADJRtyzVaEr2oTwN6VACFlz3oG8j641KGRaAJEou2OUBdWr 8nC0sYvkPhsnmS27SH95z+kJq2tUhUnVLgVMyLUJ5jkGQeHShXUeYCe/Q6ZudLeKQ+Xi08ci9IQI A8XxdCueCtMNsk9Qu0IsZeRoSxAz4K+L6bYD2jDEEMGdyObURGf66SlglDhgbRl8cRKSJ6lPbKC1 bXtGXxbCFqb7quGNtjiyayclOiuARMBj3w5h79DZCttlTOB9XObRGJlp `protect end_protected

mit

5d9ea72c88e7387d6479ce895fdce603

0.937877

1.86516

false

Yarr/Yarr-fw

rtl/common/common_pkg.vhd

1

2,695

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.gn4124_core_pkg.all; package common_pkg is component generic_async_fifo is generic ( g_data_width : natural; g_size : natural; g_show_ahead : boolean := false; -- Read-side flag selection g_with_rd_empty : boolean := true; -- with empty flag g_with_rd_full : boolean := false; -- with full flag g_with_rd_almost_empty : boolean := false; g_with_rd_almost_full : boolean := false; g_with_rd_count : boolean := false; -- with words counter g_with_wr_empty : boolean := false; g_with_wr_full : boolean := true; g_with_wr_almost_empty : boolean := false; g_with_wr_almost_full : boolean := false; g_with_wr_count : boolean := false; g_almost_empty_threshold : integer; -- threshold for almost empty flag g_almost_full_threshold : integer -- threshold for almost full flag ); port ( rst_n_i : in std_logic := '1'; -- write port clk_wr_i : in std_logic; d_i : in std_logic_vector(g_data_width-1 downto 0); we_i : in std_logic; wr_empty_o : out std_logic; wr_full_o : out std_logic; wr_almost_empty_o : out std_logic; wr_almost_full_o : out std_logic; wr_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0); -- read port clk_rd_i : in std_logic; q_o : out std_logic_vector(g_data_width-1 downto 0); rd_i : in std_logic; rd_empty_o : out std_logic; rd_full_o : out std_logic; rd_almost_empty_o : out std_logic; rd_almost_full_o : out std_logic; rd_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0) ); end component generic_async_fifo; component wb_spi generic ( g_CLK_DIVIDER : positive := 20 ); port ( -- Sys Connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0) := (others => '0'); wb_dat_i : in std_logic_vector(31 downto 0) := (others => '0'); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic := '0'; wb_stb_i : in std_logic := '0'; wb_we_i : in std_logic := '0'; wb_ack_o : out std_logic; -- SPI out scl_o : out std_logic; sda_o : out std_logic; sdi_i : in std_logic; latch_o : out std_logic ); end component; end common_pkg; package body common_pkg is end common_pkg;

gpl-3.0

b164dcea417e0d5dc667da2c2b3a2ce0

0.547681

3.159437

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/instantiation/rule_019_test_input.fixed.vhd

1

713

architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : INST1 generic map( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); a <= b; U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); a <= b; end architecture ARCH;

gpl-3.0

18f557418c975828b296ce7915330318

0.430575

2.670412

false

rjarzmik/mips_processor

instruction_tag.vhd

1

4,598

------------------------------------------------------------------------------- -- Title : Instruction tagging -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : instruction_tag.vhd.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-12-07 -- Last update: 2017-01-04 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-07 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- package instruction_defs is -- Smallest 2 power with at least : None, Fetch, Decode/Issue, Execute, Memory, Writeback constant NB_PIPELINE_STAGES : natural := 16; type instr_tag_t is record valid : boolean; tag : natural range 0 to NB_PIPELINE_STAGES - 1; is_branch : boolean; is_ja : boolean; is_jr : boolean; is_branch_taken : boolean; end record; constant INSTR_TAG_NONE : instr_tag_t := ( tag => 0, valid => false, is_branch => false, is_ja => false, is_jr => false, is_branch_taken => false); constant INSTR_TAG_FIRST_VALID : instr_tag_t := ( tag => 0, valid => true, is_branch => false, is_ja => false, is_jr => false, is_branch_taken => false); function get_instr_change_is_branch(itag : instr_tag_t; new_is_branch : boolean) return instr_tag_t; function get_instr_change_is_ja(itag : instr_tag_t; new_is_ja : boolean) return instr_tag_t; function get_instr_change_is_jr(itag : instr_tag_t; new_is_jr : boolean) return instr_tag_t; function get_instr_change_tag(itag : instr_tag_t; new_tag : natural) return instr_tag_t; function get_next_instr_tag(itag : in instr_tag_t; step : positive) return instr_tag_t; function get_instr_change_is_branch_taken(itag : instr_tag_t; new_is_branch_taken : boolean) return instr_tag_t; end package instruction_defs; package body instruction_defs is function get_instr_change_is_branch(itag : instr_tag_t; new_is_branch : boolean) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.is_branch := new_is_branch; return o; end function get_instr_change_is_branch; function get_instr_change_is_ja(itag : instr_tag_t; new_is_ja : boolean) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.is_ja := new_is_ja; return o; end function get_instr_change_is_ja; function get_instr_change_is_jr(itag : instr_tag_t; new_is_jr : boolean) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.is_jr := new_is_jr; return o; end function get_instr_change_is_jr; function get_instr_change_is_branch_taken(itag : instr_tag_t; new_is_branch_taken : boolean) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.is_branch_taken := new_is_branch_taken; return o; end function get_instr_change_is_branch_taken; function get_instr_change_tag(itag : instr_tag_t; new_tag : natural) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.tag := new_tag; return o; end function get_instr_change_tag; function get_next_instr_tag(itag : in instr_tag_t; step : positive) return instr_tag_t is variable o : instr_tag_t; begin o := itag; o.tag := (o.tag + step) mod NB_PIPELINE_STAGES; return o; end function get_next_instr_tag; end package body instruction_defs;

gpl-3.0

48b8bf9dffe6a6e136ea320eb1a64495

0.484341

3.943396

false

Logistic1994/CPU

module_ROM.vhd

1

2,054

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:39:06 05/11/2015 -- Design Name: -- Module Name: module_rom - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_TEXTIO.ALL; use STD.TEXTIO.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity module_ROM is port ( clk_ROM: in std_logic; M_ROM: in std_logic; nROM_EN: in std_logic; addr: in std_logic_vector(11 downto 0); datao: out std_logic_vector(7 downto 0); do: out std_logic); end module_rom; architecture Behavioral of module_ROM is type matrix is array (integer range<>) of std_logic_vector(7 downto 0); signal rom:matrix (0 to 2**12-1); procedure load_rom(signal data_word:out matrix) is file romfile: text open read_mode is "romfile2.dat"; variable lbuf: line; variable i: integer := 0; variable fdata: std_logic_vector(7 downto 0); begin for m in 0 to 15 loop for n in 0 to 15 loop for o in 0 to 15 loop if not endfile(romfile) then readline(romfile, lbuf); read(lbuf, fdata); data_word(i) <= fdata; i := i + 1; end if; end loop; end loop; end loop; end procedure; begin load_rom(rom); process(clk_ROM, M_ROM, nROM_EN) begin if rising_edge(clk_ROM) then if M_ROM = '1' and nROM_EN = '0' then datao <= rom(conv_integer(addr)); do <= '1'; else datao <= (others => 'Z'); do <= '0'; end if; end if; end process; end Behavioral;

gpl-2.0

1565b7a4c309c0c94d36a3f80d09c871

0.607108

3.164869

false

rjarzmik/mips_processor

Caches/SinglePort_Associative_Cache.vhd

1

28,239

------------------------------------------------------------------------------- -- Title : Single input port associative cache -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : SinglePort_Associative_Cache.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-30 -- Last update: 2017-01-01 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Cache suited for an L1 cache ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-30 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.cache_defs.all; ------------------------------------------------------------------------------- entity SinglePort_Associative_Cache is generic ( WRITE_BACK : boolean := true; DEBUG : boolean := false ); port ( clk : in std_logic; rst : in std_logic; i_porta_req : in std_logic; i_porta_we : in std_logic; i_porta_addr : in addr_t; i_porta_write_data : in data_t; i_porta_do_write_through : in std_logic; o_porta_read_data : out data_t; o_porta_valid : out std_logic; o_porta_rdy : out std_logic; o_creq : out cache_request_t; i_cresp : in cache_response_t; o_dbg_state : out cache_state; o_dbg_cstats : out cache_stats_t ); end entity SinglePort_Associative_Cache; ------------------------------------------------------------------------------- architecture rtl of SinglePort_Associative_Cache is signal allocated_way : natural range 0 to NB_WAYS - 1; signal update_alloc : boolean; --- Searcher type search_t is record way : natural range 0 to NB_WAYS - 1; way_found : boolean; way_alloc : natural range 0 to NB_WAYS - 1; valid : std_logic; dirty : std_logic; all_dirty : std_logic; data : data_t; tag_entry : tag_entry_t; evict_dirty : boolean; evict_tag_entry : tag_entry_t; end record; signal search : search_t; signal state : cache_state := s_idle; type flusher_control is record addr : addr_t; way : natural range 0 to NB_WAYS - 1; sel : cache_line_selector_t; end record; type tdm_control is record re : std_logic; raddr : addr_t; waddr : addr_t; we : std_logic; update_way : natural range 0 to NB_WAYS - 1; wtag_entry : tag_entry_t; evict_compute : std_logic; end record tdm_control; constant TDM_CONTROL_IDLE : tdm_control := (re => '1', we => '0', evict_compute => '0', raddr => (others => '0'), waddr => (others => '0'), update_way => 0, wtag_entry => (others => (others => '0'))); type cdm_control is record re : std_logic; raddr : addr_t; rway : natural range 0 to NB_WAYS - 1; waddr : addr_t; wway : way_selector_t; -- write way by way wdata : data_t; end record cdm_control; constant CDM_CONTROL_IDLE : cdm_control := (re => '1', wway => (others => '0'), raddr => (others => '0'), rway => 0, waddr => (others => '0'), wdata => (others => '0')); type porta_control is record porta_rdata : data_t; porta_valid : std_logic; porta_rdy : std_logic; end record porta_control; constant PA_CONTROL_IDLE : porta_control := (porta_valid => '0', porta_rdy => '1', porta_rdata => (others => 'X')); constant PA_CONTROL_BUSY : porta_control := (porta_valid => '0', porta_rdy => '0', porta_rdata => (others => 'X')); type flush_prepare_t is record flush_mask : cache_line_selector_t; base_addr : addr_t; way : natural range 0 to NB_WAYS - 1; sclr : std_logic; sdata : cache_line_selector_t; bclr : natural range 0 to DATAS_PER_LINE - 1; bclrena : std_logic; cline : cache_line_t; allclear : std_logic; fbitset : natural range 0 to DATAS_PER_LINE - 1; idx_rdata : natural range 0 to DATAS_PER_LINE - 1; tag_entry : tag_entry_t; next_victim : std_logic; end record flush_prepare_t; type refill_prepare_t is record refill_mask : cache_line_selector_t; base_addr : addr_t; way : natural range 0 to NB_WAYS - 1; sclr : std_logic; sdata : cache_line_selector_t; bclr : natural range 0 to DATAS_PER_LINE - 1; bclrena : std_logic; allclear : std_logic; fbitset : natural range 0 to DATAS_PER_LINE - 1; cline : cache_line_t; tag_entry : tag_entry_t; next_victim : std_logic; end record refill_prepare_t; --- Tags data signal tdata_addr : addr_t := (others => '0'); signal tdata_re : std_logic := '0'; signal tdata_waddr : addr_t := (others => '0'); signal tdata_we : std_logic := '0'; signal tdata_way : natural range 0 to NB_WAYS - 1; signal tdata_way_alloc : std_logic; signal tdata_wtag : tag_entry_t; --- Cache data memory signal cmem_addr : addr_t := (others => '0'); signal cmem_re : std_logic := '0'; signal cmem_rway : natural range 0 to NB_WAYS - 1; signal cmem_waddr : addr_t := (others => '0'); signal cmem_wway : way_selector_t := (others => '0'); signal cmem_wdata : data_t; --- Fetcher signals signal porta_rdy : std_logic; -- deasserted when porta request ongoing signal porta_requested_addr : addr_t; signal porta_requested_we : std_logic; signal porta_requested_writethrough : std_logic; signal porta_requested_wdata : data_t; -- Cache line flusher prepaartor mask feeder signal ffeed_sclr : std_logic; signal ffeed_sdata : cache_line_selector_t; signal ffeed_data : cache_line_selector_t; signal ffeed_bclrena : std_logic; signal ffeed_bclr : natural range 0 to DATAS_PER_LINE - 1; signal ffeed_fbitset : natural range 0 to DATAS_PER_LINE - 1; signal ffeed_allclear : std_logic; -- Cache line refiller preparator mask feeder signal rfeed_sclr : std_logic; signal rfeed_sdata : cache_line_selector_t; signal rfeed_bclrena : std_logic; signal rfeed_bclr : natural range 0 to DATAS_PER_LINE - 1; signal rfeed_fbitset : natural range 0 to DATAS_PER_LINE - 1; signal rfeed_allclear : std_logic; -- Outer interface signal cls_req : cls_op; signal cls_creq : cache_request_t; signal cls_cresp : cache_response_t; -- Debug and statistics signal cstats : cache_stats_t := (others => 0); ----------------------------------------------------------------------------- -- Internal functions declarations ----------------------------------------------------------------------------- function reverse_any_vector (a : in std_logic_vector) return std_logic_vector is variable result : std_logic_vector(a'range); alias aa : std_logic_vector(a'reverse_range) is a; begin for i in aa'range loop result(i) := aa(i); end loop; return result; end function reverse_any_vector; function get_acquire_new_search(req : std_ulogic; state : cache_state; rfeed_allclear : std_ulogic; force_write_through : boolean) return boolean is variable o : boolean; begin o := (state = s_idle or state = s_searching or (state = s_refill_cache and rfeed_allclear = '1') or (state = s_write_allocate and not force_write_through) or state = s_writethrough) and req = '1'; return o; end function get_acquire_new_search; begin gtdm : entity work.tags_data_mem generic map (DEBUG => DEBUG) port map ( clk => clk, i_raddr => tdata_addr, i_re => tdata_re, o_tag_found => search.way_found, o_way_found => search.way, o_tag_entry => search.tag_entry, o_data_valid => search.valid, o_way_evict => search.way_alloc, o_evict_dirty => search.evict_dirty, o_evict_tag_entry => search.evict_tag_entry, i_waddr => tdata_waddr, i_we => tdata_we, i_update_way => tdata_way, i_wtag_entry => tdata_wtag, i_evict_compute => tdata_way_alloc); gcdmem : entity work.cache_data_mem generic map (DEBUG => DEBUG) port map ( clk => clk, i_raddr => cmem_addr, i_re => cmem_re, i_rway => cmem_rway, o_rdata => search.data, i_waddr => cmem_waddr, i_wway => cmem_wway, i_wdata => cmem_wdata); flush_feeder : entity work.mask_feeder generic map ( WIDTH => DATAS_PER_LINE) port map ( clk => clk, sclr => ffeed_sclr, sdata => ffeed_sdata, bclrena => ffeed_bclrena, bclr => ffeed_bclr, fbitset => ffeed_fbitset, allclear => ffeed_allclear); refill_feeder : entity work.mask_feeder generic map ( WIDTH => DATAS_PER_LINE) port map ( clk => clk, sclr => rfeed_sclr, sdata => rfeed_sdata, bclrena => rfeed_bclrena, bclr => rfeed_bclr, fbitset => rfeed_fbitset, allclear => rfeed_allclear); controller : process(rst, clk, i_porta_addr, i_porta_req, i_cresp, search, porta_requested_we, porta_requested_addr, porta_requested_wdata, state, ffeed_allclear, ffeed_fbitset, rfeed_allclear, rfeed_fbitset, cstats) variable wt_cline : cache_line_t; variable creq : cache_request_t; variable cresp : cache_response_t; -- Tags Data Memory control variable tdm : tdm_control; variable cdm : cdm_control; variable pa : porta_control; variable fprep : flush_prepare_t; variable rprep : refill_prepare_t; variable acquire_new_search : boolean := false; variable force_write_through : boolean := false; begin -- Input variables following signals update fprep.allclear := ffeed_allclear; fprep.fbitset := ffeed_fbitset; rprep.allclear := rfeed_allclear; rprep.fbitset := rfeed_fbitset; cresp := i_cresp; acquire_new_search := get_acquire_new_search(i_porta_req, state, rfeed_allclear, force_write_through); if rst = '1' then state <= s_idle; cdm := CDM_CONTROL_IDLE; tdm := TDM_CONTROL_IDLE; pa := PA_CONTROL_IDLE; acquire_new_search := false; porta_requested_addr <= (others => '0'); porta_requested_we <= '0'; porta_requested_wdata <= (others => 'X'); elsif rising_edge(clk) then if acquire_new_search then porta_requested_addr <= i_porta_addr; porta_requested_we <= i_porta_we; porta_requested_writethrough <= i_porta_do_write_through; porta_requested_wdata <= i_porta_write_data; end if; case state is when s_idle => if i_porta_req = '1' then state <= s_searching; else state <= s_idle; end if; when s_searching => fprep.base_addr := get_address(search.evict_tag_entry.tag, get_address_index(porta_requested_addr), 0); if search.way_found and ((search.valid = '1' and porta_requested_we = '0') or porta_requested_we = '1') then if porta_requested_we = '0' then -- Read cache hit cstats.read_hits <= cstats.read_hits + 1; if i_porta_req = '0' then state <= s_idle; else state <= s_searching; end if; else -- Write cache hit cstats.write_hits <= cstats.write_hits + 1; state <= s_write_allocate; fprep.way := search.way; fprep.tag_entry := search.tag_entry; fprep.next_victim := '0'; force_write_through := not WRITE_BACK or porta_requested_writethrough = '1'; if force_write_through then cstats.write_throughs <= cstats.write_throughs + 1; else cstats.write_backs <= cstats.write_backs + 1; end if; end if; elsif porta_requested_we = '0' then -- Read miss cstats.read_misses <= cstats.read_misses + 1; if search.way_found then --- Way is found, but data in the cache line is not valid state <= s_refill_memory; rprep.way := search.way; rprep.tag_entry := search.tag_entry; rprep.next_victim := '0'; cstats.refills <= cstats.refills + 1; elsif search.evict_dirty then state <= s_prepare_flushing; fprep.way := search.way_alloc; fprep.cline := (others => (others => 'X')); rprep.way := search.way_alloc; rprep.tag_entry := TAG_ENTRY_EMPTY; rprep.next_victim := '1'; fprep.flush_mask := reverse_any_vector(search.evict_tag_entry.dirtys); cstats.flushes <= cstats.flushes + 1; else state <= s_refill_memory; rprep.way := search.way_alloc; rprep.tag_entry := TAG_ENTRY_EMPTY; rprep.next_victim := '1'; cstats.refills <= cstats.refills + 1; end if; else -- Write miss cstats.write_misses <= cstats.write_misses + 1; force_write_through := not WRITE_BACK or porta_requested_writethrough = '1'; if search.evict_dirty then state <= s_prepare_flushing; fprep.way := search.way_alloc; fprep.tag_entry := TAG_ENTRY_EMPTY; fprep.next_victim := '1'; fprep.cline := (others => (others => 'X')); fprep.flush_mask := reverse_any_vector(search.evict_tag_entry.dirtys); cstats.flushes <= cstats.flushes + 1; else state <= s_write_allocate; fprep.way := search.way_alloc; fprep.tag_entry := TAG_ENTRY_EMPTY; fprep.cline := (others => (others => 'X')); fprep.next_victim := '1'; end if; if force_write_through then cstats.write_throughs <= cstats.write_throughs + 1; else cstats.write_backs <= cstats.write_backs + 1; end if; end if; when s_prepare_flushing => fprep.cline(fprep.idx_rdata) := search.data; if fprep.allclear = '1' then state <= s_flush_outer; else state <= s_prepare_flushing; end if; fprep.idx_rdata := fprep.fbitset; when s_flush_outer => state <= s_flushing; -- pragma translate_off if DEBUG then report "Cache: flush @" & to_hstring(fprep.base_addr) & " mask=" & to_bstring(fprep.flush_mask) & " at way " & integer'image(fprep.way); end if; -- pragma translate_on when s_writethrough => if cresp.done = '0' then state <= s_writethrough; else if i_porta_req = '0' then state <= s_idle; else state <= s_searching; end if; end if; when s_flushing => fprep.idx_rdata := fprep.fbitset; if cresp.done = '1' then if porta_requested_we = '0' then state <= s_refill_memory; cstats.refills <= cstats.refills + 1; else state <= s_write_allocate; end if; else state <= s_flushing; end if; when s_write_allocate => if force_write_through then state <= s_writethrough; else if i_porta_req = '0' then state <= s_idle; else state <= s_searching; end if; end if; when s_refill_memory => if cresp.done = '1' then state <= s_refill_cache; else state <= s_refill_memory; end if; when s_refill_cache => if rprep.allclear = '1' then if i_porta_req = '1' then state <= s_searching; else state <= s_idle; end if; -- pragma translate_off if DEBUG then report "Cache: refill @" & to_hstring(rprep.base_addr) & " mask=" & to_bstring(rprep.sdata) & " at way " & integer'image(rprep.way); end if; -- pragma translate_on else state <= s_refill_cache; end if; end case; if acquire_new_search then -- Cowardly, we're only refilling one data of the dataline rprep.refill_mask := reverse_any_vector(std_logic_vector(to_unsigned( 2**get_data_set_index(i_porta_addr), rprep.refill_mask'length))); rprep.base_addr := get_address(get_address_tag(i_porta_addr), get_address_index(i_porta_addr), 0); end if; end if; -- Default values fprep := ( flush_mask => fprep.flush_mask, base_addr => fprep.base_addr, sclr => '0', sdata => reverse_any_vector(search.evict_tag_entry.dirtys), -- s_prepare_flushing bclr => fprep.idx_rdata, bclrena => '0', allclear => ffeed_allclear, fbitset => ffeed_fbitset, cline => fprep.cline, way => fprep.way, -- registered idx_rdata => fprep.idx_rdata, -- registered next_victim => fprep.next_victim, -- registered tag_entry => fprep.tag_entry ); rprep := ( refill_mask => rprep.refill_mask, -- refill_mask => (others => '0'), base_addr => rprep.base_addr, way => rprep.way, tag_entry => rprep.tag_entry, -- registered next_victim => rprep.next_victim, -- registered sclr => '0', sdata => reverse_any_vector(rprep.refill_mask), -- s_refill_memory bclr => 0, -- don't care, value is overwritten anyway bclrena => '0', allclear => rfeed_allclear, fbitset => rfeed_fbitset, cline => (others => (others => ('X')))); cdm := CDM_CONTROL_IDLE; cdm.rway := search.way; tdm := TDM_CONTROL_IDLE; pa := PA_CONTROL_BUSY; -- default creq := (req => cls_none, addr => (others => 'X'), sel => (others => '0'), cline => fprep.cline); cresp := i_cresp; for i in wt_cline'range loop wt_cline(i) := porta_requested_wdata; end loop; -- Combinational s_refill_memory if rst = '1' then else case state is when s_idle => pa := PA_CONTROL_IDLE; when s_searching => if search.way_found and ((search.valid = '1' and porta_requested_we = '0') or porta_requested_we = '1') then if porta_requested_we = '0' then -- Read cache hit --RJK dbg_incr_read_cache_hits(dbg_stats); pa := (porta_rdata => search.data, porta_valid => '1', porta_rdy => '1'); else -- Write cache hit --RJK dbg_incr_write_cache_hits(dbg_stats); tdm.update_way := search.way; tdm.wtag_entry := search.tag_entry; tdm.evict_compute := '0'; pa := PA_CONTROL_BUSY; end if; else -- Read of Write miss if porta_requested_we = '0' then -- Read miss if search.way_found then --- Way is found, but data in the cache line is not valid creq := (req => cls_refill, addr => rprep.base_addr, sel => rprep.refill_mask, cline => rprep.cline); elsif search.evict_dirty then fprep.sclr := '1'; fprep.bclrena := '0'; else creq := (req => cls_refill, addr => rprep.base_addr, sel => rprep.refill_mask, cline => rprep.cline); end if; else -- Write miss if search.evict_dirty then fprep.sclr := '1'; fprep.bclrena := '0'; else end if; end if; end if; when s_prepare_flushing => fprep.sclr := '0'; fprep.bclr := fprep.fbitset; fprep.bclrena := '1'; cdm.rway := fprep.way; if fprep.allclear = '1' then -- Cannot launch creq yet as the last transfer to frep.cline shoud -- be done first else cdm.raddr := std_logic_vector( unsigned(fprep.base_addr) + fprep.fbitset * DATA_WIDTH / 8); cdm.re := '1'; end if; when s_flush_outer => creq := (req => cls_flush, addr => fprep.base_addr, sel => reverse_any_vector(fprep.flush_mask), cline => fprep.cline); when s_flushing => creq.req := cls_none; if cresp.done = '1' then if porta_requested_we = '0' then creq := (req => cls_refill, addr => rprep.base_addr, sel => rprep.refill_mask, cline => rprep.cline); end if; end if; when s_refill_memory => if cresp.done = '1' then rprep.sclr := '1'; rprep.bclrena := '0'; tdm.waddr := porta_requested_addr; tdm.we := '1'; tdm.update_way := rprep.way; tdm.wtag_entry := rprep.tag_entry; tdm.wtag_entry.tag := get_address_tag(rprep.base_addr); tdm.wtag_entry.valids := tdm.wtag_entry.valids or rprep.refill_mask; tdm.wtag_entry.dirtys := tdm.wtag_entry.dirtys and (not rprep.refill_mask); tdm.evict_compute := rprep.next_victim; end if; when s_refill_cache => rprep.sclr := '0'; rprep.bclrena := '1'; rprep.bclr := rprep.fbitset; if rprep.allclear = '1' then cdm := CDM_CONTROL_IDLE; cdm.raddr := i_porta_addr; cdm.re := i_porta_req; cdm.rway := rprep.way; tdm := TDM_CONTROL_IDLE; tdm.raddr := i_porta_addr; tdm.re := i_porta_req; pa := (porta_rdata => search.data, porta_valid => '1', porta_rdy => '1'); else cdm.raddr := porta_requested_addr; cdm.re := '1'; cdm.rway := rprep.way; tdm.raddr := porta_requested_addr; tdm.re := '1'; tdm.we := '0'; cdm.waddr := std_logic_vector( unsigned(rprep.base_addr) + rprep.fbitset * DATA_WIDTH / 8); cdm.wway := to_way_selector(rprep.way); cdm.wdata := cresp.cline(rprep.fbitset); end if; when s_write_allocate => cdm := CDM_CONTROL_IDLE; cdm.raddr := i_porta_addr; cdm.re := i_porta_req; cdm.rway := rprep.way; cdm.waddr := porta_requested_addr; cdm.wdata := porta_requested_wdata; cdm.wway := to_way_selector(fprep.way); tdm := TDM_CONTROL_IDLE; tdm.raddr := i_porta_addr; tdm.re := i_porta_req; tdm.waddr := porta_requested_addr; tdm.we := '1'; tdm.update_way := fprep.way; tdm.wtag_entry := fprep.tag_entry; tdm.wtag_entry.tag := get_address_tag(porta_requested_addr); tdm.wtag_entry.valids := tdm.wtag_entry.valids or to_cacheline_selector(porta_requested_addr); if force_write_through then tdm.wtag_entry.dirtys := tdm.wtag_entry.dirtys and not to_cacheline_selector(porta_requested_addr); else tdm.wtag_entry.dirtys := tdm.wtag_entry.dirtys or to_cacheline_selector(porta_requested_addr); end if; tdm.evict_compute := fprep.next_victim; if not force_write_through then pa := (porta_rdata => (others => 'X'), porta_valid => '1', porta_rdy => '1'); else -- Prepare the writethrough creq := (req => cls_flush, addr => get_address(get_address_tag(porta_requested_addr), get_address_index(porta_requested_addr), 0), sel => reverse_any_vector(std_logic_vector(to_unsigned( 2**get_data_set_index(porta_requested_addr), creq.sel'length))), cline => wt_cline); end if; when s_writethrough => tdm := TDM_CONTROL_IDLE; tdm.raddr := i_porta_addr; tdm.re := i_porta_req; cdm := CDM_CONTROL_IDLE; cdm.raddr := i_porta_addr; cdm.re := i_porta_req; if cresp.done = '1' then pa := (porta_rdata => (others => 'X'), porta_valid => '1', porta_rdy => '1'); end if; end case; end if; -- Control signal --- Tags data memory if rst = '0' and (state = s_idle or state = s_searching) then tdata_addr <= i_porta_addr; tdata_re <= i_porta_req; else tdata_addr <= tdm.raddr; tdata_re <= tdm.re; end if; tdata_waddr <= tdm.waddr; tdata_we <= tdm.we; tdata_way <= tdm.update_way; tdata_wtag <= tdm.wtag_entry; tdata_way_alloc <= tdm.evict_compute; --- Cache data memory if rst = '0' and (state = s_idle or state = s_searching) then cmem_addr <= i_porta_addr; cmem_re <= i_porta_req; else cmem_addr <= cdm.raddr; cmem_re <= cdm.re; end if; cmem_rway <= cdm.rway; cmem_waddr <= cdm.waddr; cmem_wway <= cdm.wway; cmem_wdata <= cdm.wdata; --- Flush : cache line mask feeder ffeed_sclr <= fprep.sclr; ffeed_sdata <= fprep.sdata; ffeed_bclrena <= fprep.bclrena; ffeed_bclr <= fprep.bclr; --- Refiller : cache line mask feeder rfeed_sclr <= rprep.sclr; rfeed_sdata <= rprep.sdata; rfeed_bclrena <= rprep.bclrena; rfeed_bclr <= rprep.bclr; -- Outer interface o_porta_read_data <= pa.porta_rdata; o_porta_valid <= pa.porta_valid; o_porta_rdy <= pa.porta_rdy; o_creq <= creq; -- Debug signals o_dbg_state <= state; o_dbg_cstats <= cstats; end process controller; end architecture rtl;

gpl-3.0

683307fe74a3cc433b583d4a343ebaa4

0.498495

3.656954

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_sts_mngr.vhd

1

11,936

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_mm2s_sts_mngr.vhd -- Description: This entity mangages 'halt' and 'idle' status for the MM2S -- channel -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library proc_common_v4_0; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_mm2s_sts_mngr is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Any one of the 4 clock inputs is not -- synchronous to the other ); port ( -- system signals m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- dma control and sg engine status signals -- mm2s_run_stop : in std_logic ; -- -- mm2s_ftch_idle : in std_logic ; -- mm2s_updt_idle : in std_logic ; -- mm2s_cmnd_idle : in std_logic ; -- mm2s_sts_idle : in std_logic ; -- -- -- stop and halt control/status -- mm2s_stop : in std_logic ; -- mm2s_halt_cmplt : in std_logic ; -- -- -- system state and control -- mm2s_all_idle : out std_logic ; -- mm2s_halted_clr : out std_logic ; -- mm2s_halted_set : out std_logic ; -- mm2s_idle_set : out std_logic ; -- mm2s_idle_clr : out std_logic -- ); end axi_dma_mm2s_sts_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_mm2s_sts_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ATTRIBUTE async_reg : STRING; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal all_is_idle : std_logic := '0'; signal all_is_idle_d1 : std_logic := '0'; signal all_is_idle_re : std_logic := '0'; signal all_is_idle_fe : std_logic := '0'; signal mm2s_datamover_idle : std_logic := '0'; signal mm2s_halt_cmpt_d1_cdc_tig : std_logic := '0'; signal mm2s_halt_cmpt_cdc_d2 : std_logic := '0'; --ATTRIBUTE async_reg OF mm2s_halt_cmpt_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF mm2s_halt_cmpt_cdc_d2 : SIGNAL IS "true"; signal mm2s_halt_cmpt_d2 : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Everything is idle when everything is idle all_is_idle <= mm2s_ftch_idle and mm2s_updt_idle and mm2s_cmnd_idle and mm2s_sts_idle; -- Pass out for soft reset use mm2s_all_idle <= all_is_idle; ------------------------------------------------------------------------------- -- For data mover halting look at halt complete to determine when halt -- is done and datamover has completly halted. If datamover not being -- halted then can ignore flag thus simply flag as idle. ------------------------------------------------------------------------------- GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate begin -- Double register to secondary clock domain. This is sufficient -- because halt_cmplt will remain asserted until detected in -- reset module in secondary clock domain. AWVLD_CDC_TO : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => mm2s_halt_cmplt, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => mm2s_halt_cmpt_cdc_d2, scndry_vect_out => open ); -- REG_TO_SECONDARY : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- -- if(m_axi_sg_aresetn = '0')then -- -- mm2s_halt_cmpt_d1_cdc_tig <= '0'; -- -- mm2s_halt_cmpt_d2 <= '0'; -- -- else -- mm2s_halt_cmpt_d1_cdc_tig <= mm2s_halt_cmplt; -- mm2s_halt_cmpt_cdc_d2 <= mm2s_halt_cmpt_d1_cdc_tig; -- -- end if; -- end if; -- end process REG_TO_SECONDARY; mm2s_halt_cmpt_d2 <= mm2s_halt_cmpt_cdc_d2; end generate GEN_FOR_ASYNC; GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate begin -- No clock crossing required therefore simple pass through mm2s_halt_cmpt_d2 <= mm2s_halt_cmplt; end generate GEN_FOR_SYNC; mm2s_datamover_idle <= '1' when (mm2s_stop = '1' and mm2s_halt_cmpt_d2 = '1') or (mm2s_stop = '0') else '0'; ------------------------------------------------------------------------------- -- Set halt bit if run/stop cleared and all processes are idle ------------------------------------------------------------------------------- HALT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_halted_set <= '0'; -- DMACR.Run/Stop is cleared, all processes are idle, datamover halt cmplted elsif(mm2s_run_stop = '0' and all_is_idle = '1' and mm2s_datamover_idle = '1')then mm2s_halted_set <= '1'; else mm2s_halted_set <= '0'; end if; end if; end process HALT_PROCESS; ------------------------------------------------------------------------------- -- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors ------------------------------------------------------------------------------- NOT_HALTED_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_halted_clr <= '0'; elsif(mm2s_run_stop = '1')then mm2s_halted_clr <= '1'; else mm2s_halted_clr <= '0'; end if; end if; end process NOT_HALTED_PROCESS; ------------------------------------------------------------------------------- -- Register ALL is Idle to create rising and falling edges on idle flag ------------------------------------------------------------------------------- IDLE_REG_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then all_is_idle_d1 <= '0'; else all_is_idle_d1 <= all_is_idle; end if; end if; end process IDLE_REG_PROCESS; all_is_idle_re <= all_is_idle and not all_is_idle_d1; all_is_idle_fe <= not all_is_idle and all_is_idle_d1; -- Set or Clear IDLE bit in DMASR mm2s_idle_set <= all_is_idle_re and mm2s_run_stop; mm2s_idle_clr <= all_is_idle_fe; end implementation;

bsd-2-clause

edafe709987cf66ec75d55d31f6ac66e

0.45501

4.433878

false

cwilkens/ecen4024-microphone-array

microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/single_rate.vhd

2

370,178

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block qvnP+TCG9SuXRvv7a3rmuAv2C6rsYM8jAKFPno/STh9idqR5n0FK43o3aY0omE0ZwrzY2ttHqnIj 3dqICvMRlw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block GBOodxVyVUrkAi59/KekQELXvq690plpxovv4wFnUwDONHz0YOQk6eJs/2bJDQJGejj9wuVDqsbg 95gtN/U6GB9hHLJIX9sliuWeFQwGDPNn3O236v9ZTpQMiWuuja0hofL/S999Mqgr3u0cbTNoYkdE fs3C94VadzwBdg2guhU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Cp8sEszpVFNPLJPbdP65Nzx/o8LDk5SPLkg5C3O8IHenLI6lEcUl5CEFNcD+mQzHJLbB3ViDw5OZ sgSNOhpwRRTqjSPTxsdLlccEWzLDsox0Z/Suhw56InB+FChiRoMvwza4YKAkrc0mjoslVnYYOLvY 03Q0eCkX+SSnInS439o1sjZOOOua09vETcssSw3+gamMWM8ikrd3CoLzo8+E3VpZu4xFZVyl2Ow6 cacHGQmFeanhwzkrMvbsmRFeT9LmjLq+lBUxpwJGJr2w9sAJ0MZFqUwo8xyUHzB8x4oZRQo2e/w7 cJ+zASBCZsksLQQ4k9p1S5COjfq4YudL0nH/bA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pa8yyOZJFNW+wentPuYPmJYKYoikN5fKHznWMzdv7L8didyyoHPytL8YzqL4fwRIBlRmogb/E98u fBDEldyIabwfxetVJOoLC96J75pfn6s08GUEu50qfO6ne5nrYpXBm6rLgqcAlL7ZOYpNkrNXXTrv zjq9I8LcvtMOD8N17Jk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HagCWHSO/Xsb1R5I+VaMowWwTeTXVdAudCC77O1kf7f5N8TsxigBkB7r1lAKxGgbrhJmGbCbdPPv sc4tSQGz+l2hTPDz/7E/onmC8PZo3jnStfGPUiuN5D+kgfYW/Z9/1IyYWsoof3wsdjy+1CzG+vd0 uyMOeu+yCf2pLJxP1VcmeUT/ya+wVBaDRcPou33SroIYIPNIJRhTtxPOGkokQTIkDXStEKfhU2Wt ZdVXorAtCb5O5KE16dibeZasxjhJkW1WqFfpcx0FM7z3ntCextcpI7pbpW0yrzGqITyOHwmCJiGe Rs9RdBls7mIEhyC6sBY8Mdt/h0nfNqgp7VYi7w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 272288) `protect data_block PpNZ/e3KODH8af1haqCiAcrXGybbF7Uym0XDpYm/sBhNIq3hbnvm0dlevSxu6Xhq9JTv/ja+e617 J8kWSUTddKptqXsvpZbLkLFwNay+N0AWqyuFWUP1u+9H5ZwkG3uWgUrAVn92bHddKsn+Wt6vqZmL uMZxCXLNBRLmSWCM6U9PhflDO7PQVKq2xyVDBotkFc9x1M42AuIGdPqILXugUZgdzq6j18KlgGyk 6l0nGQdEjASksHLZEzk5IjmftdH5/gWPx7TPxj1WGCBnsOoey9MOe/BQFd+eACHjaMZZn/dvy0X3 lwqwEs+RZikTmNHGVWPl2fXoOPW8cTocvHiFVHdqGuRHyBc0E5NwrWnQe3mK81gjIjg9tylrr3yT qVTEtOC87rTfNip5aQOE7NyC+Qptc2pdODWCCGEVkGPOG5Dq6CiiMLAvaQuQU7klcnIvABK/1Eb1 M6i5btMBG3Sk1LdyNJNssBTiORO1bQStALo6fqVcZKbjDx5DVdfxsNlJbfXBJrjUvzHyjFIyxhVl wbVMmWdk46rlDyGBoVIuSZEUDTJJohbSzlIauLs7YQnDAmvk73cclza2vJYbSh5VoQtH01pjZ0QX UWg+rCGLKhgJYPduxLkFTQ24aMcZRc/1usRcgut7cfbcy1Eo5wCSSvN3/h2KEALpnnFwH19p9yPa e8A5/I/5+dNsMcDWaRMN4u4H8jG9wOAEayfo2t70iq70+OOa3OUBVUS+HLclNtkEUC1hw1FOGmam gk+I4iKbVHn3fcdV2ys2YXDetX812IZs24Hm8iqbFYzTMdSfJnVquq4ZmhZcjnWQDcUqHRX5IYVa d0yEaCIvqFYJsLxGcdCqELXm2ZvvhAzA1Xh9si7mi1nbrb04wEK1HlHXw+s11Jm4E9wIHZdauRRf o4Xs77Pzgv3TOPUcpSbht7ZN4h9tlLMiE9zFRJnONNMYADgLu88BkkKyYwln4iUc6syZYP6UlW1L sdbzreCCz1jpTKF/502NkQ5HdAlAls5x4Jk+0w36bohlGvI8XxaK3KSkaYl5oSSZbrzb03EDNZWM nQIv7Lj+EojGq52bAHHa9UQqYF2CklQUKu96sFT21NaFt6hOBMY/QON2uoBAKwcKLyf3jAOHiN/e JmT768qjlZEpR3/paTbviNi77YEvyt4mxnHwGgotsqgdcjoFRXxEj92CZ/7AvhmWitSWDp2/rsx2 qKKwZSODMBtSthpJdYZuMad6gJXShRMyleQeRg4OTxuZvrRfXvehx+RpvCkW/uoVWv01/CWMOuJA 4zUZPPkrLOtW90ERQui5Zz5pGuycLzuLn/mjUH2JtegKipesLXQp5WIXNBolqpWT/t5PxjgAOiPY /miAazNAPHjzdVJtGb0JbcTzm879GrcFrLZRiP1TzmqFQOwmjonYul7hY7x3JFM4XHn7cr8SwF3A B5I72A1fluHdc2fw/Qj8X49PVC+oX83JAuW8BhRW6WJCF5YGglBHpMpXgRxAASp5NlsOhKFhrnhq yyjIYFw7FB/7czMp6xNjii9KB+vhr/IvpDPnyS/uGo/Ty/lIbLur9f7mx+oRmHOhjgvour9EGWsi 3liu4P8fcD5sSPQiXWjCUqIdpA3czuvZUUG2WoFNp3494nId/qqZWsOXMgUqIB/Xkb0cXBTYl9nM W2UTKY/IeOEPh/ccAwG8Urj3uPFWszuTa5mxYxOb/bRzIZBsE1BpMDmF0NT7PJQ3QSBUlOjU/D/h c57mN995yxjgm/74vPIF/Dapwwy/wEBUMQmbWJ2Xujkgk9M/UlFgKTvLcRdV37GFl7WODuz7Utdw iwi7yaAceHQ49oHeWH2g9yia+Q9/s7NLBvF+hJ9Trx3LFC/ZTJT6YouROGq/ZM+MtQe7tfS8Gm6e EbrBBbGhKHJ+20dEslZDp22jAQ1sezg01MxeD6FoPIme6nh7woavT0DYfKDSn4V/waRWKU6uoNUn hUcsP8k1jHukT3B8F8yjeH28AUH4JvqEgBRtWAq00lPmfPvDS9q1KuTmD+uxnnMc062ukeVpCGE1 WBz2VTmRrdvkjWAsWTnpYH3lxcMAw861AkO28Jpb2C0mM+n+/sEsMsmSzoJ930WxXWcU+muIi6t4 KYOVLvdejLFaU6uz3sLbh43HAPGbiOp8rfcQqeHSuJKV2TBb/wWDrBm+Px1OGhI+ZOn8YUhN6O/j 2O4bpM8Z2R6/R8kpxJBbCQWvMw5EYTBcBROOVuEBjB0vh7y1GGHFek5WBNiki+vsNoVyo5MZUvyT dymmWI8yxCy/coGsTZLnGB6UwHD2uuS6P7PanKMSNTFcy1Mg1lNc9bOV0RMir17++2ouQBqoeyZ6 c5M6ITuz6+xBVWEZIc6h8SVYhbznB4EDGolHl7PJNEt7rgQbubNa+9iXCG/p4EPCGg7bkcwX/KRV pyJgxAlyL7awtTygx2C1qHrl5C/qo5TPxq/uvU0fW3pbkMLDDvzXY8Kt+ZeGxg7J14WDCTPDyWVd qzQGE1i48qK0TJOb+T3kkWZcTWJ4+5Au5Tl3YnGdr5lBzSawl4bIFKXYxxCBTuANkLeFnLt9HWsM khmOIcilClWDvnTO4G6ZysEfcmg2MCFHZKmzSjKnQdNqtGtusO+ItFGIJEGDuQU1xbY9hy2d4dkk 0nFDZmfiPJ/PMZHQWMhIa+FFOWic9RJBGNS2gHdoVFcVv7kNM6QwAEX8mpcU0YWKkOLcKmCp/y1k 7m5bu1+2wbauGKHlygh0WdjiLz2IqxP2rNXdvFAN/BXp6mSZy7oLNuRLLllxOgpEwPmkNHjYvW3z BQ3m2T5jjZOXA4vzwW6Lv5rmrabDfx+KxTreHBiIfra9mt6AQ1DF6LIUqVSKkNS8HWEivFgUCqne CqHRGCrwJs/lkxT+4YkxLgHlgALtv1zeDZxlBQbXxw5Vh0t9MPL/YS1qjvZs9qOwne40pxjOs2I9 N//h6Q1HGC5MegAvqGpWMOMez/COBBn0+0xAxcFg9fjHjnDDMBACeL3T33Ez0Ec75SLoN2kOWlrC HgvYEXW1/oPHKHvcukGlPsRrKmcLs/f1Tz5zdpU3pOMdQ5x6fCxfsdecSwEslhaStsE5E0v/B9qv nvGvZhvh1WK0ca6ox39NpzAsm7NF/FtJfjYf9PbTUQg3e+Dqf1uCPrhzjGWtaVLWlTZYmsqZJU9h AgWMDEGYZ6w1qaMBzytBs2AUjsRhFXPvqJQqDnLk9bEOEemcGdXVfdZKLE1cR7C3/ESyxh8N3GNq tMDdHf0pQpk1o+vZGV0pJ2isABJT/+k4oZ5/M+9L6vsS4TlaVpjIvoz9vlVeagJSRNQ/eLF+vX8+ bYyu2dBGV0PjkG5ySdEV0+0/3jPHuKHwzyJiG6EHwsg8cRpAjt8w8BVu3GEql3dqMwuGwgcfdoU3 w9D1c2VZpOga8ID5j9PmeSVLEoNHajG6wilyu1pSINMAj7HnEbHku2xQ1BRyuG0taFRKS29mw1zF yKaN75UW2vUEm7KCe56Gs6tu1fhKtUtVFCWVgxIcuZfJWh44iQEXupEaTPD/jqlO8g2AifoDdpP2 3vhgnqcwLDjOt8uZzZsMA4/JgzV6haCzJYZDwxZ/hCEKA+hxi+EqUXz+6FIeRgiMB9sq6rcNEFqE wTpro+Us9hckcHm0nPAHT3aZRVBpixaejNfLjgFisDNTF9Q/PkRdUghRhtKfZGXmUTEyAzUIYCTH BizFVvuqz0SCwtKfYChRhwtjm53XIVZk0lbcChahNwcaWrnFisZZ1nBRVmhql6peeHKWlYwgIeV5 2YmzHoEvpidTay0XUnioAZkC2VPmHpIrmnE/bwSmfDG5bJ76+4/9BmY17d1Tp50YVRSL2vVKBo/Y Gkw4+4l9ke+rjWFpaIbvvcqj1taezl+dU9syKzTktZX7KYybHr4KahAfKEUbmGWUi9AlrDdf2VS5 5EtHT4vAen4S/4Jcr0ykckmNsr0sBOkFJempCep7SRgGSO29G8d5XhCm7X/bYrimsVayUCkgF3En pKsE9mw8SHjcVjn1A30QM/LTjzwetJzbmaEUy2z6jd+lY43yPLxlU9g+TW/sx1kBpfuyR0LMEiWT pnMS/xZrCl3q2Yql1tc0K6JjNtQAYLlBzW2r5tftIQdKvyLTrAnyPiXw21TxBTo2HFOQGq0CKfUY fCFt0J4GfJ8Km/ghL2L1W8IhjJ0hq7NtrU3aGcc1FfovqVOmZkWNKjEjHciYZZHd2yhgfCcl0oCZ UgDmpBOWVklm3XJd+QMySvADHWq9NyyAfwBjsN906tnHKmiFcbnsCS11mkM7FQRhoGrn/mjpl3EE OJGPRMZobTgBmAcNdxdtGo3EAhN3e2WhZQxzkPe4/1CIlz2oM0neQ4UYJ48zTrOoBZ0Y/jSXzLJj k+xf/4EnVLTwoUyZFi+xieeOZO6KykpWYZYtrqdACwEhVtB/2sVsVdiFl1iS2jiTvOwA2heRT98Z Y7gfNt6N24BCRGvDjsJCuWAfWFniOYrFKLQ0RBBE56lzsH2Fn81D8sQz5wm4C1UJpVxKcPVg1Dnp F97DPilV2NL2j6RoZ/VLisps+FbRFwkCZlEBdubjUYaT4N3s+ozCZCkISpCZY4nVwfn5Krjz2A7l GK1ikxkxhZWXfzB5IDWcjr8PoekwL9cG94gl/6ria7AK8ZTr39mRTlMjYzFP2MlwIvfN/1A6YaYI KhK7k+Ue/PzTx0/9p+iznJHTYV5X2Qk3V2nlqYG8q2jFlZ75xUF/qZZEBSxjt5NbV6zrHwB2+sJo DGeedrA/RWnjBlEGc8H9UYf4Iut2dbcisZrdY0evbjl6tN+HiZORbSVcwKmDZP6pbg/877kW7fe/ Fo+hiLDOHMPkGPPuqmWyaEs6rccror/iN/zST0INrmRazpGXYDD8Jr8FtLNFC7Z+Bya1PU5xJsWe HU86+vk++lVBgMA9DVGNjWGnD30xrAzvv2pbe526ZltnVMU6EyGtDV3C0nDi1uVxWnIPuoIr81J2 a0bfV7ZAY742nk9Jg9/KnzYTThsYmDXmAwWUKdOTDzbLxvBRn35H8ouIgoGIkKU1ZXez66PaXGqx LpVYMfh7cpbrKKfs+6D2JxFYlGiS3rqQJCBZc3uZdMlAKJz1TJX9I0suGFqI/r+Jyi1GZ48Tcwhk IDHFP/xJdNVZzvBpSdEDo2Ges1euUhWKyYX1pujez/AIfabHzzzl423E/aOc1WKtLa3a2f+XRROG dJ7liSBYNENWIZD2DYFNtbWvslY9ZQWVIGhr6d+MMMwWTpEE2OrJ6StURVch2XFrYmACEPxsCBct LpeAhf1OuhVi1jL0QHJ8tqND/80QdRBNGPcH2rJXl70c1zoouuz2IzvkV/VrFR3+CFq/01lC5xvO XxOIqsvJQOwYIogOsldfQfYS4z35Ntrm/ABAe2Vkx5Sv8KVz/nkMtOlmHzt92VlUq9xGNdjVjfWs qWRe7gcCEqyskenmCDviZkvaSB4niEn7ueM5mzmUuwRNaFMl7ndiIRF9lbyZANBzG141JycjUF76 NDoda1EEdYTbeFDQnV51FQaaA6MYqOWkuCP/3T9o4RNkNwYOmpyQYV4EuLw8taDPtRxdlPx3qFTt /aHyTmi3RNP3aW58y9oeAZLO/QEEryh/bRowkVC5NsrxadPXnvOtb/WIY+zW04gFdJsvE1v1Av+L Jaj3tP319DW8vqUoBi+4X4XHNwAjxJtQgl8vs72HR2ET0HPoTUdPWJOVDFSRRTi0aHHm4ulHEu4Z rJz0MMkYJMKymDrXIEEbYmIWWAjrUvWlDguYoP3B3eYCknvJBASMUvXbWrnBY4A3fUYe2PqhUxRp T18120nvLlVZR4efL0/fCDADdd1TsPwWCSY0AtzwjGPJ5qhY3b77p7WUr9wJaTv2CR/E9parBznJ R08d6nJTWPbT1kkP3E4Tcj0VmpGoVkV8X9xJx4cpSHewoWPrRa++bE5AMPHwW4wRU/G9zk0Js8BD EW3TfQdEWNU8fWzVlYb8BUcRflKRRvll8RsKmuSn1wOvaAMtP7Id7nMjBwPDZQKavJIq1pVqKgdk G4tt+ir4U7TBN5EXbWfv7WnIuYQT42ns8YYk8HXkWt/JGfu/R8vsNl7GS7zruU6TX6S04clMyPkl eFmsZj8VBVdNxrXiQI+5IBiveXPB/DVy1wNwx23Spx/qDSlmxBKWlOqOauLi1eIXrC55BbvHJqVN RLWB43Rv9/NFqg3cJgKzMb/TU0WxA6pODO0xN9DUKUimykk4BCuORwEcmRyvc3eXEbMFwNvKj9BO m1L0rFBon1YQHeQbyuI4qwBkQkM9kOJJjGfoFLShjWjjfXsgY/rXpHXEB1kgfdYR59h/nh7yJoNO VhtILmnd54joXwctXj+cFyX3T5UublD1znCOX0Q1GUucar82RgwuBxKSZKnvXK+BlHCZt2G8ofD7 dKlQSkclI8U8mJt09KjyyQ3gGu4oQeGV9TWb9JbF38J1PQ8JmljzFFwtUX9mb1VSIWik2DqGwY8U x8LknSge1dsFMp68KKnKQgHQjEvisJAKozw6OIhfAQXpG+5ybYi+GLcZxdciUwcn27G3+F2gsqf0 pXONR9/AYGjvetRI6K32fQ4xv85rxaWIC34zsw+ToWZ28b04+97g+OuNH/Tdn2RzFHiULSoCkEKH OcEQmQ+7X+uAkGo4f35Lkf5oYKf7x9mUk5y/u/ayP+PCPL/fONAHwN8Tmip1+iiYG19jCzTk1T32 d6GNmoQ3EY3A8lysWutopjsyF6YpG0pumY1GikiO5eN8oRROREX9tZVZVaS8FaYnpc4Is8XkD87u rMaGqHSeR+LsEcuXeZsLeJoYsHNMoVI6vaThA/lhW5jRapVgQibxRRZMJmy6VLqUbnFwNvpFNm3B 65BQjAxl9eRXI0+BJJ1GyhML/8Nvt1peIygwf/ns1pGtoEpKEbGj0+A7TnGfA5t25X4Fs8+OJwLn PxXwNywHR2f349eEjYJuCQvEYsmBJbg+/wVTh2lMBWatywTBcHh3dL9dAw1dc4ODICJDc4GOKLy5 0quGTfOWinmRb9yi7V/sZSN+dmRk8KRlOTkfXgdOFrMXsl+ROTIoH4xDsw7wYO/dspCJG0bQx0d5 /KEX+pI/NUJdBoM0E8Jfaqqn3Ie9KD947msnvOuCGWbel1TN+u6eQSWnMES2urpoKRwfvSvpBzg2 sGV4atKYVt0932MesQ6hll+QGk7oCr1dq5RSXSibNFDmrPA7w+GTc7MswTnxmNvDaOOqI0nOYuXK LPogBs4NQ/Ny07uHsbFXtfNt6OYwijo6HseHNl9307y7jN2gEHx4fBwuV0r99rNbGBvR8kPNCStJ wHSu6hwIlEwhvGZpjVRoeFzomN7bQRF0cPdzfTHQQtLkwESfeJaUg2wVzpLZQCghAXDv9dQ0VxiX fqYi49OcZCakT6hizABQ2hWxWcQAar+bYf3pbm8IYl2hOTxOh4TlmSPexQd1h2wJiOrmTCaADbVH DhCCgWxx025LM5rmQ4EvzYDQGuq6jGiAY6SM3NBC+Sy1THkn6hd5lmxQGa7xc5SfWW1jb++YDLQg jqpnfdAsMh336Nf0g+cBB0TL7QWkEQeUwQl8/dqm2iEV9ZaSKLvzs1P+ZsHqp+lEJftDtK+3AEZL +dEqxTbIa5C1DmjEmS3mQmwrS7K91z/d6JwYRSbfSveHUEQ8cYmsv3Mrd/HaeFPprjvaqiz3FMWa nh+aS1zXbw1j67fLuUnPNCSoITcngYebT5dYjnS/vD0D7Wc6pGEfrUX3Ug+PPgAEtVYOaJVfo2Wc JPmU/vX8BNvM0jPQQGQsFzmNtwcNRP/omZ6NMFlNx0fOxZazuO8dRZZ/Z/VPtJdoqrUPgPYx2ZEA Y5U2QDdX8ryyoTLBRYMqnjte9ptKp1nM58LK/znLjn1YVmeukb09MRV6PWi9Z1JWcYEQ7xM06T+S 5T5bFYcv92tsphGClPYNlJlTC/CW7QM/mAP/Ck2+kUcZvxkobkNUZmrhPb+0fP8+cujaOwbtt9r8 dWYwNI1WrpwvTwQGseZucM38BAwNZ+7nUy4uROB9zP3dsvdEenLcl3mf2wCSrYrsrVvmE2M8yWNw 3796Pfo9QUom8fwxIaXnT53S1tb+miN6xqUyPbnoHehc6O0ivOmc8eUGZA69ppoD3LJoGDT8dqMt NdAoMfkayMozBj30vMIwxdZdw6a3bpDCaDdtVAGiVXcSOD8q/grzJ4wCqZP+JY/d54QZou34orzw EFlbHzV6QkPR8YZ1swXJqdN3nDJpPN2fp193qDB+wB9+vJk+dBiz1HRke+prwJ8G548uxFZPaGdM H6kGaEKfD4+5SnGS2dn4yMma3GBFOdLVlTM6f6zRI2bFwohSPljL2XaotZOQDQdwVCxUrXPdj3R2 9Osy5gnhhWM4ABz1Hkuu7NLD5ZP3Gf8f60zZJqraVK21C0Q56UqiXngaSl26iOv5W9JGM5CD/KB4 2AYL6zaRkXjaLeFVy7M/X5q8GBvN1QSqlTbO86KYnJyRyEP7HtECJCXuTH2+DiITh5upUGS5459Y JbPnqnYcGYyuagrheUbbN7iCpGDeGPZUleMVIntNl+ZCUEW0v1CbftRtdpNfonGWU4ZRWs/D5kV7 criVMFzgt+8Xs3XVXmiHjdxs7+iaJsZZ5wCO2GDTmGwTBxg8lWO0E7K3t9BWAZ0XaVqf0HKKhwTI TQZCoUkLsGLGr2LKMTnSkQHyIIMOxFa1nq+kcAg6EJNf8TBw03FU9etQURwJFd+K5kmWD+Xa8jTL eJl1L4CEIe3tAKhITV13LIrQeiB72w8+bWkBKH8h07YmChNP9YfcUmOMYFedqNKttrNDqH1N/F9f bnvpXRp91Ip1LpOJoHf8OLZDnczUqlXKrUDVK1lUqfBkrfY5+BqPM4ACNQ+LYwZU1WY+cJcIy+bF kW92d5jwcjuviSCyyGHKj3IdPgjf4OEm3OkYRwB4tZhtp288ub1wiDAkJ8zRiTYG5tQf+itdEfNB 6Xt++9OmF2x53U82hSMOBmTjA0AgyeYuhdmSPON2eG7ZgzqJZTInRjDiK52zS1f8ZMp56UhKwzwX zppdxwNUApyunkLqlhYRzwcf1W6079tC8+9IAbMJS6dEP+hnLbJbw/ul7GGWVw1jEazkZvMWefsv 0JuzfAITYm4Xy3NA75I656fgeIv4tDBAShitsFMpSn63uFBuv3gcizQpALHB8vk6qRhI94CQ0nS7 YuiAKAgBu09+lKo4b76c1pxB54SzR7ZiUO8p4qAo0/zLzsiyCQHF4fHrBNnXVtvE6dKuo1SZbS+X wBl+gFRCMAE511+hdLFh4ypY+ddnAQH4bo5QIzfeRnRM3L3ofpu+td5dNlen63faHB0eojXw5cyk tldcIgtjoXlE9mGLb6LqSiPXzrLq7it9FBipqGMzgHck89Uu1VoVPptPKUrJBiBj6DtKq+CKrytQ ufB+LkBTn3o+SrfHDIQjy04pejcr6nTyKVEgMsIryGyT6sjlS//9UmF5uANsipmU7DfH/MYa43jq kUbiDRy3tYEhP85NvtEVwZh7PtJOiNKX+ndOom72MXBjyPzmAV0d7HQCEu4yq5uSdX1a/FNb/Lvi HHc3EZGA5MkNS1o7ty3i5bi9TtxeyExW/uGzReG0aZ8iqhJnzunYdGfJrO8zXUNw9VeZwBqJIMU9 c7ZZkbjCBVGrCmz+FVgbVRJgxyn2zooNkJxeCClAR6q2f+4yL8WbDHAjYGdqpSkPrpYEBIpmIXLa PTv1Hb6BOFXTo2A7kWcYos0xPK80NKirfBfxuyTf1VlCaoAeqoY7z0YcATmkwGiQlwlgafqgsF+Y TMCcbZM1Dkf7kwXnMDa4Wha2balizrAldc6GsPiAAbj1+mFluWMaPcDd/7j8NWqS6JDDk+RFYgkK NgbT3Iv6ve74b3Y8ePzOcJWoh7jm3wSk0+TqZSQAv+uDu3oxvMamJP4UvGLtZydWmiTTlAMj0NXR YWp9VhZL459fM4OrvZBZoNjc0uNILCQQUEl5OE4hPb7IC/NJ+Scu+cS56IrjH6bmh7c/VK9kXo2w zM+C0KCzxSsnr/IBvJCQ8xgs6U/OGQD4LG86HUHwU92iVq1ZUJiYqKbQgFhiKAxeVlv+D8BW5IED mifLmLpP/sb4R8vZBk8oWz5tseFmtIZAFlXT6sld8zhASkKPiz7lWX/EEOaeZfQIXu2Sc5R8JBqv zyBQ/lAA7iGbANGTM+baP9gSJRuEZ+uzB1dsKSwyx0US+yoq9jVIwHn9O5tD2zSj5NjV862SCY83 uJyFZpQTFhpokwrgCPLop/8aEmlmxZCoZzxUnqGodjFjKi+WVR1/1+8bcAZFgSuMEJTdy77trn0r N/q1EOTPm3nCgFBhWuyhxpgdEVm4l3KD4uiJ9yr+ERzqWlc3dnMt574vgvC7nLyAfoyr/6s7J8VX apluf7vydKJpG0VJUC5/8BtnxrwjnPwBidSUcMD44w1IDsL46bFUBlYgyCD2iicw6++TIBGQfflx PUE8Ra7KZyfVjwZLSjJbu7crXyn3+neCudaNkEAJHxm3iIQWhiyuTEGgonUta73v7If26haAWi8U v1rrfBYMmKJAdaWm+iE1N+A/qsg45MQsPk8xyk6EIxWh/sQD79LLyi59vzw9x4SAHgHbHEWgycGp ZnR6zl1vj4o25EeJde+X0P/OqF5E4Uw091OuEOmQuAndUL04yUu+w5gbL3btDo79zA2Eo57hcC6b 8xPf7AjLce0RPF9ppQ19PhiPeLfCZzfB8u8pFTzo4YuXotz4G9O6ky6zRZsB3QPVtaEBNeDxHPRc Zu0SuzCoAk/wfkn3HNXjdb9p9OEdAprq5rrin0/ek6VfdkZbEiXfOFy+9I5QdzfRW/SK7f5Yl+Bd Oup/+sivVDkcx08j9mLSBmKVXSS0ciYnZiUTvYotzuBqVlaXalRmMTmNKJ8cq522cEwWq1zQXRer SUmmf9q5dRunPTR46HSDSRBQeD0tDC/+GSDL1DcR76JjgcXMeWrk2402mimC5vBe1tPcGSwzJ/3L s38ttQkSgculGVsi3kLK9+TbJbIEnaMM3B9pt2IHpDZiOerUiJ0+NT+QGintVCecT9SZIRHzv20w diXkEKKHGA4XJLOO87Btv+K0kvaX/+VeLZwj7ba10b9Dq+FFzQiRx3SOxlCu+0MAWnzjekImaHVY xQgWJLk+bDDmwr8Hboec8AQ6fOV2FonQC49G5tD8oLNGv9qOYHCNQ1t1LNY9EzaTwlQqbi/YImQh FRq7VFNgAGLw4pMlgGwYiSCam8sVbOracj/MoDmYuafAF5JDNx9UBvP2Ushs8HCmZU0+ppF8RAZA 0DRkHodKEbFwaLeiC4PdMAXwFLDwFe9PUpml6qihAmYcU5Hdsy4iTuGJizzMz5bokqVJZpXla8wq DAbQdJ0WlDwb58d1XQPWIV0nIUTK90K46argPOmEjAR9uzlIMk9BkDEEZIz+zX62u89R+mUXBKuR fEeYjY4X/7YMK9mU7/DiFgixYPBAHIdULif9bq+vECAGQXrOwXxA7UyiV9iXEyCd91O8pRPoYWby DGU0AP51Y65WYjrnIkS01VLPcIXs6tcTJNS6TK5yRu5xB+l2m/+SGQGApcbaWNrVKLX3g6lyysk8 seR6hxrFWvteCr/EhpRrea2L5KLfIS11NEeg+cmuTm22oqG0dps6DqlmVicax191VFOVFX2ZEi8l cpUthkcWrX9POR6qp+FeG67DA52E7aq7qhoE/NHaw8oP3U3kkuRLGWcHYkxW7PKKECCg1mjCwLXY wRhjHXfRx3xV9aMsGWuuC1USTz4/l0x9cwTCm6dwDTSpThh8oU8VY+MDucVoLMf5sUd80qIlkTzX I4Z6bVg1FT9eiEP3kDaVeJXRmrBXEM3Rp4UbbU/MOX4qiuuUkRcuwXs8ZgUCPaV5P1Gp0W3kZcqI DytrlUoDAyWomus/e4qWZ4O9xDulA4SBH8TzxAWry7SBnt4cDhYUfwMfBm4hWILD6j/Jc6RgVgUY YcvzVMyiD8UV3GkMo+83xF3JM98yuwu3XjdcBszcRuvoyzqWkhHZf062ahAtDM8eIB+16+FLgXvt U8sXpP7iQsBOgwlDe44AQNl6ajd7qPcQqJSvLJ0GGpc+Lyn5HrqQpgg5HL1PqqXn0COpllPJcCKu s3fAvBe7WaJswO4qxa6yjdqnxwyz5gYVEH39AP5RMDeeRhL3VMwAVD62Dj2oWlIMQcGe7zvH0CJ5 1yEJGmUJJ3BRvY2NPUv1wAZLNgNsgtj74o8CyotWXFO/VUGrnuqNgbfFkS5cEP6MA+/Pgklq/JGP N02tKhad+uz6FVOaYWcqfnCXXKEqWZttgdYzfjSqCdXbLbT1ExMbhoIxZtJ9Q35MLMUlHCRLIJJN 3IoZeP/suR1wBnVaOQFcp6hSEQ4dn7RbHKyDAvNRa0dOBBP7TbUclRxJtvMOkP38b87ZD/E1oqfM rQsKCJLaDpsK2c0VwJ2gr72WaQTJEL75Ws2OqLwHVrzJD6O/fmMtxwgX0zq55Mawqh533t/ml8bX C+gKcGjlDOXsUoLjFPa8tfqLinNQjwAgRBsVGwC4d3TjCQ0PpxFoplqyc+akqn6UEOUP2e1l22+k HhubU9xlp6TjIkFdzZwmuXSzYJ9+EjLsMnCoxeJprraFNhlx6ovkZfC9dLezfsv0Bkp1TleGVhD0 k14XrSGQPxbW0bGKG6Ndadk2fs6w+Kr3pNc0t5+FjjgSdQcLVLCFWfVMYa/iAGqBtZW1YBZeALuF goff3YA8OQ52pdFwHthJyAHo6IhenabTFC51LAv0zyuI+W8oPfl/WTmRPW3vywtOft771oHKcygX DuRmblMELYCjj6dgsKBhBcejhfvwvzUdmhfiYYr7EtO1D/esAmfWMSftiX7sx+BK9byc7eOhxfCV opyE1LsiN6Z9FwUCxEAiKHui+LkEvBgcTOIFOQs04Dh+LVkYoJyK1wwUozb0TR0W54oMdz7qed57 g3423A1K03JRZUiJWMndzA5tcki/Xnk+ZmEk5oimBswLMVkvLBfP2zUp6QPrQ6Si2vLTyHGmOavH hD0cIIMo0mARzyqyxWz06QIdgz7TsxELmsHS1FeJ6V/tZTFKD3/zXV1zX7WqvXCretJB/WAqJnFC Ppz7it0QxbTeI5bUa9/wmWyB24EXDri++MxV01O2GhZEN0t5YvpLDN0FT7Q6JLq1wQJHxjZKnnZb RnmjpHuXUYJggxobZ8qT1iVcHzsR0l6aUtwAqPgJgXhMno7OaNldiW8LdnbSw5fB2TjXnY+JClzw 55bKHkCG11cve27sUC/SOXtNtMXPThdVAZxJE1zupxtOmscldsTIBUtpYdUbRr3gjQuj3jvgVnBX cZuio3I5XiRMNjK1crZDmnuo5lCUTQvdQWsywGW2GwWh68Ay6rkXrJraQB+agkpbf3KUm2KbGS38 u/UcEyztuie5GIAc2fW8c3Ia/8uuS4D3Fi20zNe32HgC8+DIPtZocMfEtn/d379yPy8xFoxcYej7 Eficq1tG8oi8pGuMhK2vrgPw7a2DTBy3o0mLEFxT5Wc0ubC+nmXgHWEzljFcTc1wX+kL8iRjITlJ x03R/KyeF09FUIRySMgIBni67A/RPiNoDxYPOE+pLHYdRe9QyGP005dJqdnP99d7iKriwwVa8FA7 VLMoVJHG7XhfKaDZ1mms7dXgwVlXOP5Z78P8AsBAZE39XyQCsjSFHOWBR3Sx9931c2Pjxh2FLfjf sOrG++SSUkq2TsaQgS0onbT9IC4fXwTZqVbQBILjl0WTMvC2UFoW0JP+ppi1eeUcEKHuLWY2kAUg tnE2poa7xZiPJ4NEq/1i0WOFeoWxRgidr5ddBwkIrS1nWDJjnhnUfbmAGHkWlXoJBcXqdyTlh1rk MEBHfYj4Y4wOabd8hPfGTgIU+v1/IOCT2O7KHhpBGsh70ySW/uxuUYpmDs+L7mQ/72ZvpnPSLRpV /s7btX7aeQQKhBzjb+g56J7b2twLJt5O+/5iM6RK7X5ylHPvACLEFUlyHuiAaRjQpVra6amL74uf VCME6mQliXOb2/GWlTjKJtIQ6BLS/paPrSqjM3vTqDsVerCiRHlbwwSiiMZOUPtt4kd3SmorQrT2 3K5QrJKD12WAtDYvhnQOnyteHqixrcl6RTqRfuW9CNAUWe0FwnzwHX/WDHcO+0rFQH0n4cx4Q7q4 1JNsBA0r6nSoDBULqfKt9Uqw31bD3ZMZK7dLrB0QkjR5ny2QEGiR5vhe/1i5yBxU5ZTsZwBpaH1I 57KXD707Nw5elV5MeXr/8RFkbfj+aaTEJxDiYV7ZLCHCnkoBnmYMpgOYESAiRF7xLmGzQY08oXgu Ot+0rMwcFKvBt2ToJ2ssrJ0G5swdKHindx3ZPb1LU0BnrZAPCfAgsVAqHDec0K8KpKhFPfs6MpaY NK5KVZdEeKw7ykNJKVMiXzTH7ygtZL9HHVOD3KFE8FAE4dj36O4WLJDdPiQZ/To5dvumP4vFfAw/ wc20lJc0jUdTj6fHWgoiN/rhXzsn+iVRlf9NG/dfEb8ZEL/rJZwaeo7GnN92ATWuU9w86OHqBb7x XMbPLxofN8jtocm1lTlYf6+YO0yApztV51mbTJ27F9SYeWFpo6MRy3K6xv3pQ+da9G7gibFBiguW XcOn32Q/6MAKK8hyZqryYDCxgtfJc+WzbhWopXTv02l3OjWOffZSt/4T34n5KwyKTzdjzyykp+4e cuy2jSH9WL5L8BZQuS3eI6o0SqHYi+2J7xOKUkZpANO5kKFZZT53nunDWRDFPmKIjhoqRocTO14A C4EKT+ebErX1dWeEQv5/GR5wWC14PMTSSTE0g01ow3aWz6YEfNPDfTtrHTk265oD52TA9xDOQxrk uHwYdjS2rwn/1tS/BDhiOoHzd+Rc3DbVTfOwgEUAhA87H8hnKJdVgvzM4lwqO89uLXDWGM5JcUoI M+f2ZRMuZu8dE1vNhC6BCZ9QI+L66s8WzDaV8mokJUmyPwZWOPXNkELzziBNY0pnXJtYuWDQmFFj eI5tU3uNv1GzU1g7m7j/mtTY4hevdV7eaSdXzZXPAXlv76CVY64G9ZnmE75wq2CWnWjNXqTmA3h9 gzWu0loru2Dbc6UPHadV1WGJ2ig6MfvJP2OrpxrHhA2T7de9PHUCu1Hw7C8aYEF2WGzQn/gKRVg4 6HiJDTfujmiZWCLy36I8G3rk5M+PpkcB6h3DQMD+yxk9bOQyLMjuJaWh1I3z00SdKp60oTYe377r 7obzWft7jDbcgwgghOLUqkf404BN7UUhy5O8xtsIw4XVv6CknF2gZev1XieeP1cdm3t+m0i/PHLr N9v558jfQOvZk7OlKHWCdNXKPDyUu+GLKKOVMyb7Ku9UWL3kqvwFeQnFgh1yrXyGHq+/51iG+c5U +Cqx9HMlDN/owsckcZwyx4vXsVnC3fYDAyb0PaHtTKlTvAeaV2o3K0/aIy8+Gzg1HEo5QalFOPqA VX9GOMspLpATF9bWsZppJfT4fB+LbG3uMSQdQWt8fgaKH/x/LSGWIgLFQpanRT29B0FTE/siMDJQ bVInDTzr9R5cis82ryi+Dm6EFSL+x5b921hX5x46a6pCfdV1xfw9s9uoQxZHZYhbGcVyC3qjwCfI qH3gGoiX2tN5Td8AYhOXbpQbyAvEzP4pFIvOP1lwxzcVgt4m9spsFsc3kNDhKcRcTu918Aqvs9FX 3bgWMJDX2lpwaEyKb8jX6h88TzIkg57C2uMFGLXJ9uOh4tMGFJuWhD74qdzqtyIwIciLTjpogzxB JwCXm6Q3LI27Okw8t/87lk4hDhZJn4/xqMRzbu8K1T+/EkMiwlGnPypntMnYk5C2cVR0sEP6r68b RTrr+nmUOVIl48nHA8Xy9fCjfzW/L+BSPsCEBImQIVKrpn04af8yvI+/cpak0ETgmnHDwsLke8gD iCZPRIkoZHFnhkerr883jN4flS9mPM06JxMZ+O0M3/THWg3O5GaKTPBCcvh86KJuVpae0N5fyGyf w/Z55o2+ta+77FRLGXLMDPhcHkMxOvwkiFrbBcPTlYHoHd68AkRGRo8283SfFtpKdwUs4ltbimNo YLvUWzLSTgf23krIotq1Y9wc22Pn36p06KVut8oCs9V52NvcFBp4xVKvxILIpNUlJxIJYgi8BjL4 vhfbv34gG16VdYCpWQpTW7VI+40ACAanfMObAeQ/6jQPS0Y/+hBTaZQD5J1xt/eovGHRPOHh5quh WEzH33Nhs/jykg09ukLROqpi0WMVYNCx/NStcB+a8NxeDEMW4GieeHw7KH0tHJH/kojQTPFRHs/f 6oJtFcvYB/q0w9Sr4/hzqehy4RBc0kxkz9NJe9galkyzVJvMfo48gFq6ltKfSqRpUh6Tnb24ZKef +IxCAZDfZG7BnoiLYU9eP+maXKsMqZJlJOIx1jNKAxwxDGKeFSlCuQTv0at3dOJpJTp7q4sYHiVw 3CkIwIH4Ata9BQYizXN8mMzesI+ct7Vvsg1dthqpLGLk5SNomVYCZCNXgsc4UqOmg5nENAGgMLPk 8HSFFb9GASSFgUdFzy1FyFZjE1B8QRZJhPaySoIO8IeK8G/ABlN/k0/9+mGYUJVkxJXoERRfIQ4y X1ldtdxurqr15PSzcrqwUAWx0py6UpzZRDNu7U64JeoXWmMhISfniL9TLgWGUEs36ShA1SY1+d9f EjFBl/fzKt7+opMVfEGFOFt1YM/grz3peEE7XKUYgQN81hJZvK9DLqiZKiJexEMVzyzNpbDw2J2/ Q67O9ksQN/sncT6NTj8Gu0CZzKwfjzKeZYAt2MFiNdqUzAhw+hnfHpdtpPgfkzbBrisfLfbzwjGT mtTCCysV3MpXQSx+7J+dvC/eqYR0rMJJAqtfS8UiHZwp9K0ZnGe6wXG8INNcuIJVhs1t7YwtL7/E qgTXYskuHC7wMm4zLzc5d6GFWGfWr8/ufRMyY1iFVE0IMUJ2NtQIQtB7RKL37YihZeEQ4BJPdQ7y 410sxX8Dg8dLGWbkzNd/2rfdhAzjiSnxahlc9vR9WcVp/uBbzprys/AF762xTRNHgbGJ+kY2/Uox PWlcEuyrPeHXKHiKPxSIBGyOalZ/WONSgJVemCf5tS43CZmiNiwPiL3X1Jk99NagV3YIWtUOxLYC nOhGkD5vcyPikuJLA5sCnKVjFA/jtUh8PZizB3dRYXa4KEgSH5Jx4KT9oLo/Ixtr9FfTVLrEgYJQ uZj1BnpALzYlqun81Pk9pD7UD/HIAbqB5hza4nch5RdMF46UOYfoNG5OhQLkd+tAgtJ7hHEUyB2+ KRn14cgUoRH/ZNJ+b55RhjhHTcZztSVQmzciAt8px61GZt99bYYMn6EVlVuoI9AUOAqsJ8YwSWe2 kGYHzGlxhBudcdtlrUqzWSvj6wfRK7LfSlyF9wApFp3CLMNZzEedF9GHXjS0Gxe75r02tHqmzi4V O8bJYZEC/wVh2wexVruPeFdtEChcCPeZS3IrHzlvPyMh4+gqEfrArCdE8hC39Lc59S8JdeNM+uaG 200p1ME2NVndGLPrpARH5GTZW4qJivqrNO20ppv+n63Rizt9OaT6dd4zWud1a0BujyQWGOnFLmHH 9xsfXEmv2LBNkFRBMH2iRloYq5i4yeKrV8JXG8bTyoocH/CHGx7+JvRS3+022jf9nJjYOYkwLNsF laWpgWbgvf19g4uWZxZXPAYPok+k9G/qUWL1F5AExQeZh/5neaPENF85xAjJbzEYm5MzxmjT9DhY 73nRaisyml7QFVge94tOJChmnlT8cUOkxvJgZTUrXJ144NR/gTufnt7AS/8EZBICgQdTOEeC46Zl bpkwRWD2PhabTr/J+t+hP5j4jn0atBbKtQTR6KZyLBrdMtOb+iZCvy2d16PaAU6TEW+MsfdjGw6s TRM6MQuiQ7kW/wv1U5BAlmk9bKBBhkwO4EtF4rfKHp2bIQTP8Ke6LrBgv7M84mbiIkV5Zg62dAg8 3NpZnBp0Xf+jBzT+m5CnY1v06Ma3EdCbNdpgpVeKgDVu3tR7rFHzaaPxbaRLqZdbgT+YaJbpFtJJ cTwM6N/JS35EJ8tVw6+yMJzTYanO+PYiktossmywcC5z0dRX6DSvFBzDWK9z612SxzVfL2ErwpxE wlU111T+YS6YRObstgKvlqYeSCacN7/PCmLJHDBBW3dvr3R9wDzYUOqN+2yvdNctGlSCJ39KchVV ezg4Zia+OeiBgQpWIblXN7Zdb3IMiDLIH94SpomxYYkFZ9MqCvs3j9Io/SsU51QYl407zur13/D+ 6g7gz9gT8//OA7cJW+1KfU+gt2ln6mJ+i6IE6alvjUS5c9r4kHvKSN2Jjv/9Sq+80mmg+Kd1fcrh 2tyCbWb3I+r7EPUZXaL1As8gMwEOMblrqg8m7edkKi6f6ARF9Rtr0sKG9ii428RkjsMnxIXUDDh/ DiEPcseJIlsjdngMrJk+4xxrfE9dTFu7PN28X5PV1WuP2VQLmXq8AAYQyQwbsIrKMgGdo00B7cup ERXsO61/sSPfwo1X5GqUMs1vEfsasLbK3tpGW06u2XsUTNBdZKtO+8xIKQHjsljmsNvt7IKDReZT MrGcdr9wHiU/CaDDBy/uWaHo3SZkp+/z/4hmtVNuDYInLpdTxMW5pubPuBDHcxNyaKCmQ26WurLv GP/IZ78nxTIw3mEDygf7xikcVK4VdGJCVrHcaK5vR6J0gcdKzgeJWt2i1bbyEf9kMu6km3OMXEPK KsKvCMl8mapW9wxmcmcDocZpKPgjntXMZQhtbnR4hfCsw7vmJ5R9Nh7zbMOv6MNRD5EF57JbMBSQ Wt+dF5PtusF1VYCnnryd5KWuM5RQ/aV3jHqqB4YJ78yDq5LktN3PiNoDEIJA96nROPQ0Pc+xksDS JcK9+ZH7ckmb8VOpN1dx3C04dd2Wq0Eq7LLIltpfPS67/fm8iknUuL5OqE8SCKRy6J9gVkWQvlpr QmIXxV7bdyMraueTES6C4KzEz5HywTXsG8BOOqiv3ec6eEigE+PQ3tal4ZobnQIwM72dngcnyLzp ZVTFqFXUUid7r8QK8VnIZqQYWZu0UB5zcexsm27+GYmnustlt5kJNBpKBCkA3u90ZWx9EjQ6uZEF Eo9F5MGmD5G7cJ8rWgtA75Js1Y0aIwFR7FGkJUuDwpQA4MtSI+32f+fhroqFVER1IBiyJVBxyyzJ Sic2EGsuJuUOR/hKvSiNQAoUGOUY4wrwozhkT9enGbLVqa+0uBRKWbE6AfMMNqamzyDzRmwEwhqt EGhvyxMQq41eDReMeZ3bX/k/gxz1JL67AbtdpKoj26eOb3cFOsUQdLCZuSZ+tZVGZ5923n174YGC q72EYwX6NJ6jiHLvZToMLHKQBZD4rOGCciCG5etf9SLKYf/LunsPnwo7epaGgOJjeWyUH5OGrRyx zH5rB+cAHO7x1/KCpIgsN4TFG76hrk4BRPW679t0maUZ2bBhlDlAIJWiY8w36PFIz+c1JPmODsic mq5UYu3e/t7Vw/Z2Xhq1h8Vju44lmvXxfWafzrL1a2Mxgvrx9REH7sVQDMEK0afW5kcUWxL22SHz Z4hDbB20p5q31Y1psL62w5heBZKMuK34FSKGH5SdjBhl5WlSoqx22R+UhINDSuJ38mr7C6HZFJki ZK5mx0fRL1+HHPENOpoyq8KNH3O43jDoGqKwYHdoguQKyNdtbbKXQdhVXa202mV4HIBEag+NWcJ4 hwqdMxsR23ZK9HifCSKVEWLsgtIZES2y6UJGFAXlfSQW5Dlg/5xrufGgB3bRlp59rtr3LHvngq67 oNtNZU/ZhnlZXh9QR8Si8khmxXD/L+L2lDrG5WsSSHSed9yFVZ1y2Ak2Vm60g77DziGs4U8BCluv zi/C//kNl/sULL0Z1U+EQiUtDUNJfbT4vV3O1mYmHj0CySjBvqo030I3rGvi2rkD82OwJ034vvoI aP+MHpdcXUIXj+RejRZp1AR0ZLaaomfyw8QtaY2QvCEvWNFPCbmt7pE3rb2Fs4/B/jMjGDfVSks4 +LakuIg9Fb0inMnC9C3jylmnHY3HoinwZXWTMMEuDsqF0YnBm/zumQ/DgDOyiCb9KJXckZ7sV/Vu BiA7O2Zq8I92MxgChOWaYKtUmxJyXhHqg9yj8ds/BvX4Yx5Z57xAUlYv1fR4ntXkmaUFRjmh8thF aCVR3QNWhzN7HOdWnZpSstMVtNhJNBjmkIepn2/mQVcnfnWL3juD9jkkCJQTKCtP9IPxWnwT1AfP P1QvMViTVyyaBWiGb56PCMhTov5uRtrdfCWMZVVqEbiH9r8CPsQntOvRqbZUQGYZfYIXlbzMyEOx VAxu+n9bakI5TjealChM1gUm41vGAWlCPgQLibtVhomTsUPHl+d9XM7wqtDyVKZWfxZPcQ5d2izL r7xcxqe4BvSy13v7myPkNLf5aDmIB6fIE3j6HaUCxvDidO61CnlLLajNWmISUHNaownx6Y0zGAR2 BwFWhlv3V1i9crCq+jvD6r81FXKbnozB29NwvzqTZ1jg+FHQQu2cWR3XyNul9yeJova0KxbZ87ry KJ9uLHGfewbCPQ1w0gjBa8KuD0nNsmBKW5vcWlG3NG7NdJag4ZojIiliVVnVMvDD+ERfavr8YokT MhyOesWIT200vSj+AEP3WYtkKJlgejRu1S0t/XRi0ILJ1TzRYNjPn4Qf65xgqDGeGf4yDT+VB+g+ HOunfQyRTE8okPV4trFkIa9oq9YtricT52RPHHJ+FFszh5Fibpf+al7xfWSppj1BUHXkt2HaCA3i Y/++q4msu6R4kQK2X6t1mRZtTK5MjyXmghCBFmH9cbiRuHfQF9+ZLnRjQ+6ccY42cRpnXpm25ndQ rF2UQuTHy5VF6J9cWzxeQ4Vq7JCZ25B7j4AQTKhk28SWVMmRVWFMEKWJ0Gql9lcX52Qp8j+n/x/c sBJq9giIpGLEMMjEeGuFX2qNPYV2hNyPiRzBATmDhEYryMsMFXK4jruNTSvenZLTxPwpDkCfSToR Vt7l78rxDcjOMP57Zx4RDBl8BZzhAJ7A4hzk6I6upRj19r7Dh2rP4IxQiEv8lidVCtm48nU59hmy A+twVT/D4odECjDa8BGEYxScQHi61w5kByt0pRlQCMa9uViZQ+l4044k9fISYesFmpmSyVZITDQf bKcxAgOk0OpTnAx2iSwpVRdQwartLqzMztsmPsLtCd2uRlAMz3E/YlFI9o/b5opXm6wpc4i/6ZkI 2unvT0o6bqGZ8QfxXHT/7/cAkIFCtZKSTf3FfTx/IbePZoxyvgAIZd+XLQ7YZpxi5PIKk1V5re56 dzZbiOHSJQMEQSvOKBjKv48sGi16YfGdWH/HWVEMyy9yNKknza0dgGhXb5WI7ilJd2u7bIZoJ42r ONttFQjlz/snqlu0+9JzkmICWj+2jCb8aThK4uNbJApggD4ZlMEIucR64wBKwOCLfW5sQ8FBsBXR eYXSjVOTcnc/BqfRJIdyNE/HnZslDalovXS2pE0hAn01vL4uBmZXbqILb6p0hpO8TQIxiyUkzgyD ShsbykSeHYUY2DnmIi055jzWy4rVLI+mHjuZ+0DGgt/tLUtdhDu7AjkfA5gK/U+xUv1hBfpM4w0d lGc9pXSqaiLtBLd8pRVYEUhrEv5sg6IvDYXhyeh2hAqNyDKs6CXsn228Q2Jo8+4Oz8cS7hEOPoZ5 awyVq4XO/mEKcmgKUVEeEkpmPHsIOJcsG1FfWhTAGrNdEQOYALih0ycVW/yDprprA5yoF9EK2/J2 c/MD0Dh1rE7k2BCAJd/d53p397ibiHUxVk8X7w3LFA0q2ySbmYmQBl7CT9Yc7mfLhy80PgxbsYYO JCy23xi4shUO+fsNe2pjDLFwKBlLa9fIfFLV9I8aQFZANEGMNtxnHt0wMCfKvlBXbDlRaufNjJHf gVRFWoadziIszumYXGPAZiDG7ZfsAwP87uCQ3AhXV+my2mgGazCSKyeUASLH3gjDhQqpcabtGvEn p4sMEEpLB01yHamLBDZCXwByDXhKQ5jwzXkGpP7XAwVwNR6UOmGMMXJPOdjUXxczqr2hUgqlkO7r 5a1Mo7EXiSneRAFP1UPIad3ILV9GszsKmMOopfF+dBfLFWJ7cHvxIt71moG+LVmhQ676v0/+Vtfy kMPz2bsZv9EBwfZkezgcVt2fzXYfIAgsO13VYcVX1XenEPMU3A5p1poJUECzVhNdJUDF6q+FBaHV OFgopWOzM2SThNp7BnbkgTCXw9s0Um/9B1MoKLuHv5IWuejjMcNMnpxJlCKZwqDfvVvYdiGyckW5 ldQueiDmB9Z7rb4jrqFOondbDeyHON+tsW/QqXhjJK0G61ggyd/6rx2Gpt3twHAHd4vg0ZQnNjbV n58sY4F3Evrpjzm3ANfDrjLxWPbseP0N0UqISTRrWfhw6iLEDIbLifcIqYAM745sN1GXl7nGvi3U Wul91EYt2zVzm1lpTJ/le+JCggCQOhrp+buo8Edd94fS1LPy+cmVNTb/eY8OjyAcjd93m55zRyzR ofsni/n7VFKiyhaoqo5tgmIfzv8bDzPJYEpyOpfB0VjaX53X3KVrQP5Y3UUkkX3LUPpOaBGPWwjV NEq7u3uSueAUzC6rCzUwzIMpfpu7/vkUV7NBhYq2T/Q0612GDj4qz1k0o1F4WWZN7gKH/iwA5vmX Kv4P7tp5YHMbfcRud9KrB9rzO2iQeE+55EosSc3DO0R3YpfjFRPejkThovSmaeqFtNCGAHYRbIzi DbwBEqQg2dXh7b1YL2SPlNvEhtG78f8f1ezm2cPhUa2m71CqpsQxeQ+FqiBnKe/ASdHOZN4lNCY0 Linh+clHCFii9vcFV1rc6Yzf9bRCev3CWLdaP9MgTtRQJMkBKpRY7SPx1bj75bhSObLQ0keWoUcK wrfBuJaKLJq4YdRustBxWd38xdh6DjtaaU+MDamr+IJXlXq1i3bvVfMCt+YurFbbGq1INi1/v9SW mYeGmV6z9bhSISNbvUevygjl/x+7V4gBzS4cxDZwx7or5qQLbFWwZeGuvR4vgSceGoGe0fjRe2Zl zsDLlm4qxKocf2dqNm65A4R27yPqIQBr73YNhotPLTfDMgzdgvn+ulkKbZ3W/VIdyVRuVBXeBCYV pxqtpsv3pHXapRZqhFA1Qsm4oHIQsWSD8HSdKiPWg5t6Vv60Q/ou3pvcvmkxEr6uV4BmPkeqflba 63CkCGCFdtJA13l3s4lv9OrCqyQsRBQMp1nLc0VAMLn8zCo3AqXlSnHLX/gyQqSZr4cZCd9IziHT itpIJdo6VV8rJB2lDgGe3rta0SzIWWf4Ye92UYx1S7NkXhQ1OF3H9PFi0jOm8Jz3SFiP4vod55/z QjZKE45epwnCbuB6NpYfyJEPiaxz0o4hrPBkwEoyX792CUEYzvTDxD7cCimadusgeBG2iDpi7T8w 3yYMFrOC3lpVH1VFXRYf7SFlJRr8HDv/WSMd10xS6YZ2LEvvDGnAfvW+fNptJBCML+qoZ3Qgm3MJ /5h5tYXNub9IxOzJIT9rR2GV8J56kA/RhGOlE+2r0eli3Ud2C5Kt2i6cyDBriIZs1QQ0PeKftrsx AS3qhwHg1Oz0Vhl1R20NmMjrWgIcnmgLJ2qLopADbuSVpQnGLQ/E1FStiGv4BT2Ad88OTmCqRJkB jWgvlfK1xspx+obYcrNR32I6tRm/jZH7tHn5Zz3c45z5QNIBBCZrJ2J3aKXBPT94kqiInwdBN42c sVi9RhPO6dlFl3CkI6RcZLvM6zWLmtonYD3mthDXtuHbm+kWoci6acbQdAlREhble3N0MPqjNUNF a6iRy/AStHI1ysLU5DRhuqphOKWs1K58Tiv6Uw7v4sjU7RywV/o85of9K9oATRKt6OXqhow+HRrx ctD9DonSYnQI1F2dDkgPR0mHtFs9RcOvxe+IN/Ue12fA+l4+z9GaC35VojZqHGLhQ7oPr56ifTIo aImi4HZqo8WEK+aXw+h/X252m1ocW2c+93snsH2b1gOSecU6TZkbMuYt1WNwiw398wXTngI2a85j LjZ2ez6TtfTifpKoGcYsqNFq9je64PXep2lY2+eVKi5Mn1vKCo1jeYaGP1haXczhOAV9XhjG3aIF wEa9in8eQJKo/FJRjBSue4Rrh+pHL+dpwJ15ZtXEgUUKQkzkzOVZxJ5NmlIJNuQN/lA5MjqmxREJ 0SR5TgdZ5rV8jp9Vb/5/ar2HWYxQeVXvFJ0r4I5Te+V8tISGnWcLtX35JSB7wn2b9akFxylb8m0S 33vHtTK6H7qKB06PR/yw80VfTIGXmDe2AQIHLzITgv/hS9Sc6DI9ugTpuAKvjCJBFa+HkKf9+48L zNpPU4RK/gGfKBUzRuqWVaCARBTLn/PmqS4F4YdmZK35W9A7brPRurtjfOCaoy6F7HlZGjxd0glz 41xDVgdq8uZ7PwOV4DMPuzIYqYi4fE+65VhIJAT0oeIorHrUzw8ZmoK5J3XlaokCzg0RsoFY5AfD LhWH0BkYYtuXehcuG6mv/7CTiafQ0+09DA3d5h3wy69VivmvsTYDf6ZQv3VZ6w4dokPOg5IM0ovH zmX1ZwOpwRGRgXMymoiHHFRg4r2gf7LZPsydUcPk046yx5ZTzGpqbm3AUeSke0HeZHRvqei1bQc6 0vm6F14GFM6+opJiAhua7IPQ2aMYWG0NxzKIT/oXQaqrWWfPnwFgOFfXqc2spP1fJk+wLcgKpku8 yliRnAzPymYseIrrkeum1YOJ2lklwOUAFieGMe/KpVqt6Zqm3flNi7uWe8uNlHMQSXjq3NGH2w2Z 5o/CWXu3WfitF7tsy1kOEQZZw0eGl6h1bwGKh465I5WPU2ndDHe7SUOYqIi6Cyyre8NucUviWX8y f3Bn6XamCmqBnJFb7r12l5qm0hdyIAj5qUQCuw/9SxvvQdO3xFTo2JYj7sHG3GiKTrbFBDQGR9P3 uAc7ryhCEUaA3blozlZ8PyDEGV+9inIXgJiVvdQzvOKXPYmGIGFM/KCiRC8NYPcaLF3tKVt710Px 6JAGDUFNKuyy7i3blI72qEXuc+EsPhWu90CbSe9NC3K7pPYgZ/u9BJYYWAFgIdZ73gtwXRTJpZq4 3vwpe6CQPC9hx70yF7jkW3Mv7eL93zaHOMqdk3p26yEGDZUK7PWmuOzQEgliPEj7CPtWsC9rVZpy U2wp43apDKSGTl7V0qhIAtBt3dkNRDiGKfQdzZ+siVODDMRrF9HUKKsjOMeAhf3NoKPk+Oa1LF2Y 41DbCAh36WfhP5MRLOMEuYsfo2lI/f6PG29OSLmdV4FTFD1+P9pruRPbaJ3Q8FGoCRva6F8YxwmB jgikT/WBw8h3tnxsE4n24Rayx7rVLINAOzMpsGy1+EuX2s6KYz8J2AR9902P7P4sEbe1d3/+rxXk aALLBv3vtMwwd3IefXgaU3lcnRDITQIHjjOJM+0RFZrkxEA2uJeyuBzidRpahjhO4LLjnx53fR/K fhJvFzWhIlyPpW5aHKqE3eUeX+teBpYR1AO5nOiZjHXPZ85zXCKkNDSeAx4h7ZbDXNvxj70S3cPU fl7cpPj1wSxZoXJPwIz+hyUiyGTAx9Z4bvuRJmg+5KuocAuP659hY+gOjZvL1aUkkribaR2gke0q Zm34ho0duD+J+yl/L1webJvxfhGYjvnR8Nlr2chElxpt34U+uEbq2BagyNd56zHPMDVhVzTR+N5g ZLA/6za/Hh1xxfq+ASR/dcWshawHff7DzMnYlpe/KfITRHZ1Me4L6Br30hXd7td2dz3KgtWp2nYk 407/QXpJKpKnzcDZEg7Ep8MUFrOhb6pn/R41rDNr1yprNRxiZNgd2RPh6RQHPyLm48gT1rHXUiPs w023i/kCuZ6I+UndP/no9Fjc1JnNiU1ywBYw1CmHPMDiVk/fGSborfZH8MMEzd/pjGuBNynqa1sV MKgil72hBgH4UR4cwLkewNw28GCuzipj7F7LkA1JuaA/CwAhVoYjEuyOxV3luLiKcEnIIde2OK+D L9ddzvVQ1tBXY11NhTkRG3IzGI6iB0Ji6imY6SBgv8/temSD8AuVwpfZ8CGzXk/VrN/EIoUHR1o0 lpYMcML8GRUsYbQMc8tvbAEVKFO3G4sVluJuI//GrCWZuT5JIN9rg3beS0U/6Uh/FnpnIALCiCpT /qtPUL1+lxsBVHgBwqCQrEW5TpZl/RAA9CoGHSPvwjhqM1Ce0prn6negFWOoSWLYAvHIcjupBi4R dKAsNQJqf6Um+lsvWazlVcXVpqWx8SP9UB6yyS2vAFsoOPMnNQIK9JGg/CrTlgaLUl6Aylk+jLW5 50tTauciOMnl+158pNY/9I7Z/Jx+R3b2qWwdfZ2pserQPwzV9JaRhzn7qMuDoZdfATq8Rl1mpxYB YhsYviTMdXQyOPHekzssc7Zf7JIerBFAnH7271+LV3GpSDM6oIO6ifH69o+v0c3GSdXsCnzrqE+h XR45Q2xEkHlf6ycCv04IlbVnWW0vP3hC2x7UsReLsJmN9bqGFWg195PDK2PA3kFGUNmcgnaZWCdY aVLVI/O/Fdt64E2liDpJk7+WOOJKen2ZyQrRWBnqcN8ooWlTGVCYATE1rUDqZ0wuTVvvqQ+Lavdp pwh6V3FkJhpgTRTKImHSl4iQJCjgdJ+OYlSG/CgEOpkTcgcL2yipgr4HUeqmsgBn8zX6Xf4rjF5P S2v+dBTTjRHoXAnFFntbqbInOy36RwfKjnI9rRI4Q5e1dh2bH2j+4ZuM9E3kN+fg6yRPTWTZa/jq miBc/5RkqnyL6qPAAHLsNcPVZ2gJlJd54gLj1D1h7jhCdJqCPHl2ZIi0Fy7M1252P/DB+8v3LCRp BRCe8g97fqTfPcSqlTmJ6drwvdqI07igOC7LZQhAOm6C4Gan/GQQ5SQldvlpRGUrEJN679gYLpQ7 V9McIkP0vklWiCPoB+RzuJKjjbVVp7Fl46Nn7GAQ+TnXGBH2IT1aRQ1PK6IRVDCRUfK6wd+5ax5K Ba7Ga9eXi9+ewBIKJjn1u9kEfPKEmze49fNEvLNZSLg2tiT11XzA8emnGlGCS0erjp5ojcDDLDLV bGKI3lxd1QjvvTMa3gaapoA/dRfTvi/8pd53wSTDIDoudENAx+UmIxoD6szU61SZfn5P6fl2nc/h rdAzb68RLwhgtZB5SK+8JfVTxsupPUq/+trHiwYia1JtxIr3GBXm4dlJ6Au5qXpH/BgCUZbdNktH T5tDNnsfh/9ym3/hu3F2b8miEGTZ237iRTIr1/z8UKwD7RTnlX4EGJFBILxmDqDFQSIBBG5VonpO PbN/VtcrJTeJ5UwMT48DlcXEH9BVndQnnyUSAkKaHSvl7Q5AVVEjQMAQQsyy6gYvVRMq6YW4q5gi IeoDSdkJzaFlBJ8qWTkPXFNASDCBvMV0W/ilqxj9n+gS9YRO/skXO/9dtrItGKJbXPFZOISD5V3h Rpfsm/av6HE4rXxZXLrSz4HxPXOWajsoYAPEMYyJPNIZr69URNemVCXpLxunyx3BN0RATWfcJYDs hdHuMOSoRHIleFgaaCRnRu59dB1C9jN+XHyLRw/a8g6I8XGC4HNoAIwTjMXyCWeFsUqpETvyL7eX P0YBuGcRF9uTx6Err7mOGsqjdW+3Jvj3TZfEuLFQliZflTFF/Syj7lDvDpP1APHYlP3APZpoQD0a PRGA7ltGHcnjychxG0dKrlkzlwTAeVM2aJ0Ym3To9QP8qzVJPagHDgR0PnQ7z3QcP7uTRldEpwgF IzjDgfRS66NwiVOvs9QjgW6CjN0qhEr2jy6aOH370Nsr9gogO8lj6DSTgkuSgWdg2tLFrkOJzGR4 +okpCAqSaNA99zZjrelQtCG+HvZ5wMnCncZpmFb/VdZ3cEOzM+Er86hK8lh7Wjsvwj3Q5KELDp0/ ctoWBQD2KpfIgNtL7J/efQbzGO7AgIAXxDRU6fCb/LZk4fXYUKeMUM9i1YgVTN0kHv9R6BZeJ9I/ zu6MI9fsY/NJn223q4ZPLOUG4BRCP4ojDdKWO7kdhSTK9rXj2G/N44CIU3xzBSkD463UeR9Cwang TPvqR2rVbTeYqIRrkvKNxrfkjDwrLwnP0wLjBXmMNo/ydF+gTHzkoaIYuWBv6Vqr+YCopRw3WJBi mJFc/39aanxNefkolWCTZBzCj6sVrVUPr3EbnqLvFxg5vMSHZj6yjWO5p94njCpTF8pAc56lUnd7 WLRfWRUHwqgf20bpoxQJ1vqX8Knre+xIrNtrrz4EmrgXfFpkpw3fZoJa6bK8Xp1w0SaQY3sxJtUY s0pB3sRkAkHQIR9n3CWu0Nb+Nkbp+3jTFriutoLOYRcbHRX6wvAm1kmO5XtsbGM1jckeRFgIKWed CpKkYeoaAbFbBaDlzlYLUViE6cdwXknErPqwm0QjKvV8vwOJYYgrP1j/AlFtJdObS/Q7lgv0je/m g9FXl5uO15f/K2+fkzg674nlkafpe5AcdS2PnVNr+6/DdT7hY2waoQmHp/Y+9U8RrL8bLeCZLzVM f7ELSoVTilDmmkmG8JWPsEo/nge0M/dIRsQcil5BrKKPZJLpGcD9RFTTM2TXIcMib+DfGQKRRZA/ oulAtH3YBAMl9WFE00fLpKqlryrjxvSgTg1GZzXNleakXJuYwpEoE0mCM8j+0uR6vLYmBsDRwTQl kRhy/nQ0qtlI+/btLaXBLpI6SR+HUO/SNZ6/U9kTO/EA7GcyhBNb4uyNnvHCL/7VKxcQHAmapKSR dA8u8bjYr3AA/2Ir8rcltfMlOtibqfY0ph1RA1X3fGTUBsT52Y+VtnmLTz7JQ7wI71Y96FBEbR0L Mbvm1AI2voAO00mHHlL1ZEJ11AIa9VBIhXoiJuLGB7MOHIgwup6NIjIMQXDVTkUCgC1FyWgrIBmB xAQr5crwF+E0kFueOxyQs+NyiucBqyubp6OVyvALktVVMFJ4UD01/rkq37e6M800ZVrimbp62hB3 ixoN5RxhbDa1pfVxkkoMtPoHU/IYS5vEf6iU5+xQ36BB5vqxXfSeJmCJ2GJ23MUc/Ej8K9ymZSK4 h67O9U3Qo8kY/XDNMIKpKU+wWsSsSDs20T/cthAJWRTHye325zxR14ZmPRU4hpBMcy13xRPSDqUz J3K4R4akMinKdJU7QJfuLZli1uMGjvsRFMMgfelPlm5dA9keqdZ5M50eRDqXqrUriAoeJ1DoAgsN CBGCygcZ3Hjnjn2Oix1wLnv4OVilAstmMZL+/I0Eho5Cd5p1vYA3RpMy8ELLE4q0Gxhmn8LHZB5V wcchrEi2wYxbYBot3uZBTEAU/AIwt+tq5X4IeBdE8UgMkXJpEYr8Neeqs7kUoO0JmmFs9GOjhMZp IYvxsqTaN+ns/lx5Ifz/2Y1oawUQ4Avu6MQ1JwP44IMouoHrLUd9iSMKNemqPlDwyscrCC9e9YCr xiHWipXJmAwPSl6x2EVi6q+B3dk4pRmTUnApOIchhQTmhLpUxC1Zp4JOY4v8E62nzWSWNpw+gZj/ c3vSJbuU8qYd+OmBEmCwTqtV3+VhXV9OtNbaEw7B5y+PbHMr8xVxPXwqJ/WoT35Vhn1iuYCsEjRz KFBLuRigFAJLSCy9dhHklNDEH8NtMYdKLCe2BPEls0Z6nUjrwYMFQlsnDV89H0Uq6vhfx6+lpNjW AXyymOf4HUtQHHTeaOG8ifK84iGNmspRX6BbaMlGM02JGiZQeqNayP3cNZSqVgbTmBMYHnje8dK3 O32MJLPEWtWjh4Rsp561xG6ooa/+nTQBKI8Y2ilkmPbA+REWhO3Z02ScKB4ROpcTJsEhSwDs5o1K kbwMumEApXTGQ8vJPeadQUglJ4SzYUPoeefewD2dk3eB0sZdQ/dA49MHjyxj79QkKOt/a4Fe7X1B AM8ABKYUXOw1MFxRzPnsE3JVyRy13V/t6io/f+TR7Fiw/d6Jqz6v+ImtzlofRmkJBaqTQRJAblPO Rejk09AjmoWDnbvEWARtOjsAEEW6fz0l+bK/DeLqqErsP/2Zu9v837vAPUsGMdhaoHgsKOv9c7Fm KT78fKdMd2J5QxoBF3lfU/QFpk8BlLiCMvgknrl9Dp6gapVnp8sRQhiL/p0/ORTLe69QfTJobUPE h28Punw6rb8FSwe9JWXrFs521CmDz/0XdIr/VnLKTAjgDqtH5sqZfaTCJlG/XnpP+Eqf08NFlvqt vkj6cWJ3U+FPvjpQ6rUqNN0axxDpnAcsEKSANjB4I7hy+aq3Ap58goMK8sVv7lLkZGdZ2ckBs6+2 CUNwkQ82ckN55MaaLALKeslnVd5XqBhjeEHe90mfn8qRoT0ITNxlsgJ6np0Z05vsMsedlW3yONBz j1VUhNQFZMR96vXREWBajDkzIYNY4gge6PrFPxXpnDI1pUAYQEWBnQXG9OWDLDEsfmSmYj2ksaQi UPvCHUhyVWb59vjxz7yHBr47sNUM5reNw+/6xdv4CwA/p/rhsrwTg2T7TZkPp1rqEgLbPibmNOc7 wovThXDmrtlVKT4T4Iv34Y0KZl4Mv+bMoZDTkDSDbbVrEjjfo6vs1fPxCU4mHHPaql9cql9h0xEn 0hHzj/LXW0GZHsb6rzoTyi9RcxeMviheRV5uptI/gXMcEma4dkvNFARbEVOqq+S9SvlQcwFejHS1 TBdtAVTLVX1HcSy03Ev3RGsKc27y10ePkXMXyIp6c4RfF3Hbc2oLzYg4OHfNCra5huEuhrnDFMpn BjTSPTGmpfFXyQ8a3dfxI9ViL0fQkfJxp9iLa9Vmo53ad3WbSPbuDBZ0oiXyoPamqY1gfay4NZ3A SnSIXP+uMNM/rjf436NZVi1DneEe0Y+0Jy3p1rSyBOfHNXPY9B9xwdJ88oy45DJq85OqN3j5y2Cn Up9lo9NT+HduQyE7z5DQcEjzkXInKw69oL/XHipQOgNzBp/ZKX90Jlix7ODtkSK0Uco5L8LYMhaO QpyxTFU06VAuOU0vx8qUgJ8XTfnemQkdVFPPtFb1kp2Hxdaqzc52QCeH8Be+tUtVYhgd4k9/sClh zrGHqmKKrQBde/JQDWZrUUzxiu0RBneudbRYyko+9Izi0BE9aUErSOUpCTMab0lrAWGjXU9ClS1X mQOQLDkzPK3+QzCXrlnW4bWLqaKKwZINdcAddncp7O8o8UatCMVNYXzq7ktdVuqN4HT/UmNk9jOX JNTCIgmpprg3kxIt90FLV9+6fWlSNaEDoV934vsVhLtAiiRlMXVrfpLLwpECr6Eq0x0UM6HmI7R+ cPvlFz1MTuUgg5C3/ePBesWlKaAqo5tU/aAYlwJlR1Vl73JgDL/Rb/byIG5IkXzOnJTLmJLPKzph JURsYohV+ZZ6RBQ0e6bNOjooEWe+0o1i8VZCGtJX2v3xpeZE189lS0UnMjkHagrKUM/PP/R6UbVz Of0w6t8l0+yVl+9x01fVsjmhQsCyE5s830C8YrS1oGAR2ZB9KzaJv7sSCnW5+C75a2MzLdnVA/Zi 9Fqda1IPZSPPeMLtMO19hZyMTwu/4zeyWd4MR5agMzGseb6/8drlIzKwUbjViY0xg05+tDeewUAw LylsffWMrh++RUfz56UU/8GyoOog6ad/mqeQL+7qL4SgxHuwQqployM5CBcAImnmSic+AyCXL2y5 rDOX8tYrWbzp6H0VTbWt/4rrKSyDzQdnIqVniIFyzbSo0Vd2GWeo9ywFFhRQnsWiddZzhyYZqJIy wMpyRdLo9fJH9eRHES0qeQHbb4FhiRgWZJSDh+Imjair5cBdXHrK0CjoVHCZk4AiAGAaoxt40OD1 LcEZpOe+HO0zbbEk63RChJp0Wu69Xmw8YMC0XfPSEoHmdrFRHGYOPGB/5SV5ch4eOe+LXjULw2Vi rzhDMAY7YM85u1RFXzcRGD5TdMolGxBbTo2SBZsS5oNbWZYm1dFvWeitoXyTPFfHsB6NzylEXMo/ Ac+trQ5ZboN1HdVXtiGjNrafNMAa0Hbe6ApoO1CirlHufsiNxBEfYQRuMubiwfuSBvPVlnFygl/J jrEpT0DFLA1iHPjgdYkqYB09OmyGTLkmra+0orBxr0LkhG95Snv0g8mHfzcuzjCAoJd34XpjrYz8 BlzaMUGzc8XmlR3yoyqA65L5Rq45pn1OXny3AySFOROuDOzAJ9FiXFrwxDUI7lJSWIeUaYuAmHwj EiVcCB2mv2gkNaiEg6cILehlhi9hc33uoGd99OHP73xP9OFFSZ2HAk9UtBhC62uz+EwAKYfe7S3Q 7cDcsJUEZMluko87X3HIWZP0uK7lQhyRl/zliaw7crNS9KUf2mAMFQgI7dOSGPr9NLXoYBqz7hMP 7mH+/ZyrrvwUTeH9MArYC0A1xFlMjJxhEf+JT1oI5A/Vo2I2nFUHB7yzRTHYvueWxbm7CC16rSyk 9xy08gm7Pk7TTwZyQTL/7l+Utx0yBf0YucI5fj4GQ6RvCaxR8fKCpvLNJJryZUA+cXaDFp+ao6IC SVoxtaqExa5vXC9HCUVoDILTp8pkThaW+FVhM9AEBuxpYjXsJtgXz+xn7j6Z/bl3XjCH0/ldvENM mqiWOBtBXagIAcVP//sdwOHVr3+EDbPEawD3ACP/Xim7kuz+2cc7/O8Ib/mxe1C4Tid8i0dHe+sq e81M6PC5UlhFI7/nlTj7CEoGrqTEQxBqiZoMrIKVDJwvtQXB6JipY+trfz5oZ3l5XePmvzcJij+9 mH8aJmHLdh3hyqCpwgCq4HwTk914FIoSN+DUJlb+Nd8uB+V6BwDKmSNusFv9QLYKahyaVooPd76R xxxG4woz5ZZjhPXLNtHlTKxV4VMaFJlrCinnvMGLd2h3Jk0X1lw9857mxAZlee451x4wed3Ebsh7 we0M1qkdoJJK6n6mjDnnXgPLs8wXpkv04gY7ShIza8QDT2YUgqJ1YhPe8ZSTTViREz3zoSVSz+2r cHYKuktahrb29myYXBx1jVlndSMchTYUVDlQFqKn3HX4LFtjLFodT+88XaEiZCf1vLBPIufqIL/0 iIYu8aq0Mh6acLCnlsCq/Oe5K4VwqTeeAa81nNbN6cv83XPLR69xajisSqYL3SlzaRb0RZORygd8 IfybcnTPjI2cK/ub8cfp7Pq4soc8iZTDsSis2TOOKeOnr7hguwQ1c2Zrn3GLLjJI9N/+tYqdnjAH oTJdMGLrmpmIDPTQvy19jryZ4HhU3rbzYhAPRlDwYL2W05PXGaE7Nnxd6IWPdac17MEUUCqsMloN A0AHIXjm1paYNFha5mQYUyxcF61SINlzrsWDS3pqeO351u/PHAz7oZd1eWnA7dIjkhLTRu4XC442 siCkxtG4AC4jNzKp7gxyiMcV5yw+Tw9cBxGGMq/Jl5pzzYFbveLdhpp08GStSkRPsoYZCEj8xl3a GKXFwVCxTIMIsEJ9x5Y36R9UrREtap4pMkkpx4DB+ND7DRUQdBWpmCSMcAbHykErDLGqKSjy/J2I oS66j60Briud4cxwYfR/EMeRNap4mlrGiJcJvubc3/sYzkkE3eRnMVzNSW/scSrOIDwI35k554va /2NuQDUYlVBXICh9vJ4JyMcGGsx0E5fP2MY6RxLwLk5F0xLOAXNQLo6vyEYVQUFvAlQx3nKjlb7c diprgue80ZaMBn8ZABYtUiMCruHadl2K3pwa0Nk5dA7h3fzCVMQ598c2z3i3EzCCZOO6k2df+yDR 3dgs8mjcdD0z4qeVMLcJCYNrNSkoWBLMxjvZCmnSi/BiY2bPWhJMBb7FKbTRN19yX9JK9MMIZbTt Z79PRl9eTAeqYP45FRmaCf3KW02y9J4Api9yb8BXqXlQ3LlymsKk9Pgphce65t+bVeliD6yMOU8z rFSxaEjjUTtmteZOQXKUtCmmfadYQVFCuOskPpyanbjU1fsXh4JTmg+RZmxeC4HDkqnpAgtEu0xV 5TpLcJnggHDJeCanEk1NPEC18rYJZQtCVRRoJUs5DwqWQwtyfDjK8YQ4GaiF/eJAiuf9VBy/SELn iaIvnTg5h42H2TE/ZJil1SuweMr5LmRxfLQLioJQ+hR78t/+i03XfTAKQOQhZnQyMWapJ3uQLZIH PLGB2ug2cjyGaOehDvwt+k2id0I+NcJdaMAHaEaEjOiwEni7pMAMZPlK3GcYxYhGm73zcBa8kk5U hKrS6mH5OhGEuhjoMfqubvqB3cND3nxGwYS27Y6sSP3Hnpk6Q7BNhlIFUbjtcn9RfG8IjsaNIcmM EzP9o1gfGr6uxG8zRAt82uh8D+IjWZ1+l3beVzMOsqCB6t/n3fVar04we/8hVruwySXREPbm2Itd U7ERgdpigRjz0mcgIhOElYyxoP5oZCzYDFPxVQivCvkriIiQ3JzFNIGPm8vqYGs9wpbOjJpwF131 jubIMhRwqyFGY/QK9zdW9fazV5+sY/1TRB4sLo4ZkVAUCSo8eJd49YQMePaWvSJMDuWo8io/y8tm wDHitj+/LtEHTTP5Y+K/oHfRhY6FYN15GasUmFxfk/jczzx5+8jPDraMQti6GPADWfYx0YmdJqm5 +k944wVZIrX8TOBs+bSI9cwljhum6yDkUjW9wnFvIeUY6wGPVjZ0GlvuhzjS0DX41HbgJOQGw++h 8FZecT4/3LcjRdPe4xehB7x8N9/z1Wt/CYJHViFYmTP4gXp6ha8oEFFdrvs2srIKlIWpQALTKHM0 qC6znULxQWIchllRqgfpA7tXJvNWUALL5UNOWzbZdgv8TEpZxZtIEtFLaZoDAYGBPpO+xMRy0BWd kkjzWRlABFbJi2gxtYO1ss6C9hCJ5z65n6o17vKKMpQv4/X3UJKge4hBObHzzPnc8rrqGm2ZyJoN eNwfRpO6EEZ7iO25hNW6b0Wns/2Rj/BmQIEGXZKrbRaYEvIPgV8Ckm1yulk9YsFa8wBLQEWmnmlg VIfJtCseZV2r1UHxx5LZ0YpvYFQOKNFJRHqEQaGjT465cWz+z1Wjgv0zPZF91j49MY8lhYzP2SyI KvLTIKnNjd6TqlSaqqkDvtDOMPwaR2sKAyp5tUGmPHPrKiwqMPNH+/n9iftRQ6HAORjGCMjYSUoO dys0sGwCzvxNRi5lXhu3aT8+hEr0Tyzkxr/r43D/ZKWXPEREpDTiSbdcC7jM7bBoxH9JFCRTJwqa a2hYDAJG2disOoNNWiRn5h7xGFddj/ybtvckLyVDgZNIGG4AHKN0d5HUV1zoLEhkRSkeJy/WIXE4 Pm8MQL2Z/CjNfn2tUGaNxQmiKlL9qE/J4142l0WB0IXgniA08u1G2dZ8RLrBXFihh0b2gAEkwl/2 t83HMw/4wqWSdmJfRoKC+kldZezlGCLZBHlCwKMkmvlOu1fWEcqu/WHDNUWdwPqaYQ8wDfid1wbm eQ39aBVCNRUny1exZigJO5JpFuBKGLJTMXszFw9ZuJle+F5P+WoPqaZQpcqzfShUjsAzHBE8mSQO FuZA8trEYNGd7ZR3kisB8TVudT4Qp1h3VmYw8vwKoYVETy9tDVw/52h7yvIfLSOtvwiIJrOXF2jU o+Xh1hrb2XFmubRrN8lQOLptT0J7EmwUuWZYrHthY/XX8T/kqj3WbzqZ+PbhrQHa+44b20+lNxlF +Ux6TRFG5JwpkVmpNPxjQhGrXYtAyL3ZtPCh9srx5oGYEBMKlmjQ11C4ahb9fKhfSlO6H2E71JTx 1v/deL3Odc1jPz8iluB04DuGnggtC7i1pDqJKiCUnzY0QK7Me+xatW1zWpx7mboB0uPKYAIJVX8H 2NJ0pKiM8gd+NckhvPDyMWxOYTXA5/JVh7lTYuMGv/nJnMKuoFeJOlLIKjobZULefjah+OLoyi+E d/Y4WNBOz4oELDDq80SEN89pBgdlrQbOUkDs8uuy4AWFk3tAIzK7Pf1LaEx+Tw4oo0+ITur5YXEG uMgwgNem6rQuJrLD5BXTyuxGsf2/uaebgHUiiZcpSDH0qjcc61ZYwuqaSOFKDxGFyJgF/OkFLIUw ceSrddEV5k3uaCCAjwR17f/ZAQrK9+K8G8PPiIZl5v9H6N+4HNYG+tWTERLq5x1VPh6SRh2KnHH8 qwyYvTVIdPesjTQNf5vetRv8cNkoxStQAqNfk8gJXDk8eqI1c0pHD/wmLZkPC4L1FxJvO6WW2CvL DtTffIgAnLbb++Ydwh1VUUhV44Wz8fTQ9AhTC6MZ/M+LHYbOYXk6srHb+MUs+539wqxT5Yi0sI5q uDvZE/ChOu66ZAB1N9Oa+b1+RQrXxOMgkqh3j1Cgb20MMUijTgcz+rsVgOjbMBw+XH+C2jaT0AQV yrkfT3pDIX4pZnrB5JEzjkqPmwXGt8fm1OL61w/LfIb4UyuBpKS5jQcgNbL8K15huIxFbdSel+rT 769JL0lFn4yGDFPOLNyk6GOOItiQxeZCv8VNMDVyMfO7cR57vpKSu/v3k8OZvg91ZCcjumkZVqsH /kC+W1kOOxxPHC2IgRgZgKZbf3AnLDr5L/Eahc+YbbuRAKq74jSFzmsjsG9TVAIULE9mgv4ELeSB 41Go5E+gCgd9aLZXSqna3YScUaRXJGf/sEPkNBQYDdtceqXuJue0jBqI0B8hhSI9En/E5IbsRV/S 3oB2uZX0piFhiGNSel7bPVVG0s26LAv1v3mG66UlmYnVwe6usY5eK6HbKYTlKvRkPVttiUxFC/vP 8Qi4lNFtFYIXBRBGwu+fg9iSy1LgFbyDr5c+O6hBD7aRt+nQfBCwewA9a7HnAhGyUYW9gOm8Wtq+ G1h24EyDVTypGytD50NbfaoeYyRAH/hzECC1Pwv2eXiszG+Q9iiE8SUaXo4ByEO7MP2aBExuBh3G iW+4WkIFVRe1pPbyP6clQUr0W3npEIzi+lKMSmi8+BWuAi71otCUADcJ8/1fBKJJXKAR6DayR/5t ixmGAFIezTUBzYaXY/szLU5ZCWi5Zx8QvCtePnvPlXe9P8cm7lOxJFHW9ZmEik8Hca6wtknUSXKa +jxtjZgB7ROAY54qIgVm66wOHR2jDgdxv7Ge7zD//02JgUtVqXrcXyARXHXxWr748WQ4qvxpl9r8 p0wyoA3D8o9RngDYJ/7ZEgXJC4dZHooifptKJDxfGRj2UeOy+n5t++A396MCtjGisen+7AklpyRh AQl82W5LUvFFehuF7a+z9hHcWM0lvK6DwRLEle0hXUUn0xFNAYYyCxYH+mUM/Ytqp4YMlxViC0z1 3ST0Y5Y4LXrUWvOPbyYjXbyncgGfzT5bv1qKV/mz5Dy0HVE2HSeS7VVqQnLq0+AlJhg+aLAi4Mp8 uVs1hQNJDxFHNPcW3LpBZlH537FjlPo98JxppJICJZ3cU4rpKPud+AD+27GEUFsz6h+GOyUePE9H K1f9ylVDnLJA8UUvb9bRvroDYzb9ICzbp0fTOWzN2kdlBCovOWZVS25mTpkM7z8uBMkz51J2JJk1 6poo8aa5tqTXCsUKM7tpbAFdLwm4nmiPlPwqqMBMs1dmuPYz0WDT8HjqF4Alye0cjokiVfn+gwgw X5ygYImST+H5RFYXWc1GsUH64rNhtdpyIVe8z2kmo0avfjBIqZMllFCZ3ZxGqFmzwXHgJh9+wcEY FB2PLeQW7AFRbPVx1CuQgmcVUOp6vhvaaXMzS5O9Q7pmvJjaZ1OqThfkY0VQSik6kgyoc+UZOJT/ 6d8bhLjQw/C5nPiQ13sbUDtjW8Z0ZDU7DLoXBY6TIwV4Pom6mctYpcM1oA//tjntiwRQnSkyAVq4 IrAXVNsHh+2ple4ryP7GMyjHB/s+3OLLTmSx4nwWrAwaiCAfb/l9LEQCQJegDT7r2iIEjWjORdZR C+3vFYx3ExpetQe8eW4wWAJKKywVbdP3PSX6JEVASmGuBVCeg7Qxnfw6i8oLkG6acXv6oACaBTNN a2YcpvK4AtLAabyzERQDvLLfOTjPI07iqM1L/rePHzIXViY4mKNH5wGmvTWAQNKOvxoYO6FRZF73 MIFtPMTKRSQ0DM5L4S36cLIFlZopP5C6YQzzZt8wFzZM4rlLbA0DenCo+3TIs+/FyjXSQvkL2Bxc daK3XUrHAnXQ2k5YNA4O3Qc+NKR0qnNVJ7O1WGuccSfuiURKQyCMUHCHP/6+gzHZ5wRmsMlQdvqL eijfUGmZlCU/2zYdBbvh+o5YYUs9+cYjDu89sKeVHP/p0jaUQPHYKeWmg1HDGsFSSNne6vmEBC85 Almj4vX1loF+a52lzthnDWSnfTH9lzq+KlK9NI29yx0FXTeH03XKGm/umwb0jDZLg+hLWsdWMh0b 8/5sIA079lvrFwmqE92tTThhX0FKXdVNmpAJXRJQ29fRlOhOQAzjzrX9s+YJUKp4dLqXq0SkqUVf Hta4mwQhB6Mte8v4a65DqgW/qddAUcPZiYFSRGAFtMKsoOKjtGYhUiLFj2tLoE40bmI5qBa26GNS BbHSOyZuRaLIM0G7ZYR47xyKcxOOLxtqB2yMQc3D03pvc8KNS2VssYZGWwN+Q5NGX93HMMruNTT+ aI1zfhM+s37QCmt3m92n/FPTqD3or1/e4EQPU8F0HfEWoLPWkYBG/p5whNv7nV2XSYJAp0Uk2oZe pudplHX0VejykyFgXmfJKM5baYebylcidH5JCu43e7TD27WSMOqiJyz/mjdwU3gwOUoojua0KH4T Z+hoqZPKOfNNypZFzrAMCsPx52zzXLsrQqlGpXehaoERGHSOOiizkZXSDTtyjKf6OiJOhoM6vOxo gwlWKNrpVpAK6877VFVvVkauj8IETxzNDvbN0FfrGxKKFHay4OtY3vZcdBlCdSa+fw6OLwBIvJyn rSPhLV+irTgli5sZmcKE3JXBhGiyDWX5JjDm0pds2LnZYf71jRynAV6ZlEv3cg3T2kQGMQlMmROT LvGOUIRkFk6bq9uOxWzAuUTOIsvWEtjxAHivUzK4ruGNo3cr6H5WjxRtf9aOemkr5IXOTBuRZXEY NWoVbQt/xqaN+w51MAa2X3nbNwTPlK5D81Cks3bxQIYSV8hqAMjGDKXBih+DVJVz3HEX8g2kH3sy m+7/kV9G/dqqDKT2lSqcj0kBFUJ2YhqJrFGTmuIWSC4Ueqg9K8dIuwNI8vvqGZvD2+YSZPcuiteU iCctdodpGU2dLrwP2oUQSdA2bQsdLZWW6LEJlSDmaAF7BSwdDQJgaSoHKGTsUl2k5ghrJayx+aiu q9vbYATmwWCH66kQoIEybRidXBaN6BowJZetb4sIQRWeA2wXuwqqX5z/6XxczOvCtjVjj8BuZWHO 7A/dkFFC+x7SmFghJVcTw99u6QffVwOzFEh9VjWHYULz/+vwnjFmbQyLJm+vuYFU2uyz4saNoaYA tCw2ti18dzhjy87QU6EZPHE6f7fZu16iDcffSYh9wk308HZUDpNWPNJlJ0U/12X7BTG52FXMhXLC rIvbMsIh0V2P5JST2SqgyK9lvGhzX4Q1gbXTGk1WK4vwn8vsfni8dH7hu9lTeP8ccA1LbBuW/Psc Ib/VKhmAiqSQcMg8r24cdEDF5IIHeekohCOK5SQJD9LcQvyuEZzUc8ugzFDJtiElMqFon61OnDJL MfzjuxoXAloTm2gjEHJmZY64tW6NTxyuudlUAzCY4xlg9NKYdIHog0IZeklb0CEGNG4pnBewHNBg IreAfbZNyXtDehHjqb36BrGdNvge9huxO+vg+Es/vEPq5BWWT4mY98dIdfJs9P53Ag/Eybn+Obe6 Rbdr5oKRSlvTSVlbdBuVcRjLT7EUuIWVTB8B7Ec9oBcOE08emwcfNtpXlnhpiaQovPKY20HI+qmo ukFWJrEByuqw372sXOIKIE7sswEH4h/vy52adUO4CIKvQcJLtNlL2EBcu8rN+zfHtRhy8+tP7gai 11MsRnJ9wttM4b0nIyrOS7b5fXi2+Wowz+nBiVA7T1MVlRVZ2cwVBbWP1+5JUXzww6LYyIuMzvcT AGy91aorFvgBPRXxaWB1Ed1R31Ekt6f4Y2r0tNn4Gd/8B5g8JxpchnVjhmmK6mwEIBDiD0Vq9bPH GQTjT3vev4MP0axMobNSo8fF598fxc98so98cMzFjiZv1VeKt0m8KYdM73187CqP+QFW1rQL1w4U k0AVQofR1GBDtSFcCWQfEzRQUMmIPGeC5NmmDGjOsEojdATnNQ2MML2k//KQRbCOyQejhDvILXy9 OxU2OxBS/oNyqMM+61OO7mZLrLZYmKjSui5iu7k1hV8ym/59ZFGsjDA4XAHz3pXDvrOcZxYnmrZd DJVHwsv3c25lL7Ah4/dd/3yhSWUkMfCEDCCKaH/iYvnhAVN3J4KqkBARDQWi95NOQ/EwpIgo0vyb Jupqw8X6AXOyhpyIAlJiRUeKZ+6qWvPZ3klNgVJkwtWZQWP1y389mvxwqjbLtmoblcEMObnlaDOB qG6ptq0PeIy8IOpXi/+X6fon407r7WVpd1REvqatuo3DY3Zd081qWQQgKVXyAbP1uO4CnMnKeNb6 CRWmo/mrYW0tHhDxbApJufs02/VGS4PNNR0qYlGd3xFFS9ddfFwpVRwBeXAk4xXFhvpQ3Xk5Z8sD MoSBO2RRKN/321sk31gThbrAEskYPdSytJRzgEnia+yO/wOmGG4iFVkwovRXGiZQMPbFPUVSK2sv gT4RGDQDMGxc+zU5z/LBrj1aDmeRPfN/2XM/HeltZXTNzQr5LCNYV/e3uR7stk0LxQE9kfVeqXD7 TYpKEIZRXckgiL/65i8HKt19gifQHMMFT018pk682hmMZ4bFgla+5rd/SmOy+8SvBegDTh6guiAP cJOFf4ZIlJuPmNQCnUJ/90FC8R+Bki2BgNE4A94IuQ+4QXg2sRR+pjaez14K4BiyjtCE9MwjbPm5 uYVfoizlZXEzQe51Fk9ZWPYLbMxL9I2pWDewiSzN5C+hU14q0W1HJnkfw9fDKhH1ovHbUFGiGhZI oGvMgSa8mRju6isWfyudHQR8ht8LyleBwdFMfvKF3YSZrmAAZ5xI/9mvG9ay7G7yG4a1H8j8Cm3e p5Jmdt9d7KrMeZaj+OeIM3PBczbbHZZGwR9sv1oZep9L2In00XcrR3D7rh5lGd3RZU4lNM4XjqJU hUSvHP6fISYrEGBCRh/hYGx2uCILaUomrbTeBDjP02jMZclQjphczIPsj9O7+DpufJ4eDFO1pRcj dyaqGthpNN+6/KJMtb93Cg4DFJV3IhGYLKpKadUVePk0Hb0LyhwpsVD4f3e5ddJPYUE8DH05/7IL aTXumVuExc7EZhL0eg38BvMNoVC1sSGDGvlhv22TsuubmrthIZVR1nO0ZglO/3LrSwAIjlRqQOCM 2nAh7rb6iTkBPLNcpS6BE3inVB67Q/adaDbzRxEhPZUOezADEvJ2auUJWBfb1e/FRlgZw854CZd3 VcZHL3ggU1hx4Zb6jCs1p5Et2bOXekrENsxMOeCINV7WPbcFrKoeDMXHgHoJqg+i1ZX/SBC5Vhov bT7LOTLIGFkz+UUaNK67HOusx7o3y9TlNFqZNGHPCQvoK+GutNvEA6Km0PVlmbuBRakkUORaV5Jm Dv7QMPjMeM8e54f4yPluid7mIK2Hxf8d40dbu3fZgWToReWtucj/859ynQ1EC8MnIFARNqaCVpRl hA+bUMHAwVWVbiRBNlIO2VQhlzoDD/PN+ShJjX78Wljt/lTyXovXWdwyNRaYh21H9MlTU7QMgyiD 3B5GMQbJSYTZWleDrzwOZmQ9xqNayOcV9dW+ylGGW78OpDMjjjAK5C3oKB27EU05MtoaSLVcUwEY QEqg4ry0C2opAlBeFsxo7n0MHYAfzqElSkZ+ZIZ3RoreOqf/vaQD6VIDaW++pcr5Yeb9Bae9IZae uN/zBIMD4j+w9ikQneKPibZfz/n82crIDc18RXarv5FswB8zYATzN8JWbwMsBjwB8PPVLE5fyaR8 AvW1ACALWj5O7IIJkX4WgkB4N/CLcL6WD19052HAMfAXjKaBXAP6S51DEp0xbZHRPMd9WDAltDdA ETJS1pKM2+aDf5A9EJC41QRdhrKkn0Q8mphKBosGl3N09FLkRpNRc0qreMfl0fDlIr0KU5i8LZ3D VWH52x7agqEb9ViRhHpi1WkYyXlgpJlDOaU1rnp/JYurj4lTSrIY54ANT0qgqBRfNOHEtgGCeYKY rzglWDMbMNSXtFmFuw9pRvJaSCm+Tfl850KqprleKMriqhpAHdFxbBiYm3XfiLksuCQ1SpLf7fRc owy6iOjH5YY5JJz+nmUQN2xvyyQIC0ZRTER5QS0Er6oMg69GqWnmdM/t+d+vTgnP60Q/HKsVvUeC tMbiJ0PS87dmtTQLFdFjhlWv+MHn3wfEs6LXmBXqhNvwyV5jHJk+gZfamzUsjRfhkqXCbVfHWvCr Zb7s3sNJ6VUYa738n1hwsk0L2Rkcj7AHfU9ouERoHlp+luKcYyBA34mhgSpnxKghM5Uj2osch2eo 33i93Tyy5HYYaByPTlr6WqAOmNIpPhRCXL70YIapi5gfyrjtqGx+Yl6ph9XFeiZTWId02BB57Ps0 CulKTSjyX+gJniSwPqjLTuzMGKnPngVcAxytFAdJ8YILO17FAOu/NCP6nJiz7rcc7E9uTVmhoVDN e/eECaXFzQNCNwlYsWNVtf3ccAS5BDNeo+ZJ7Jdi8/TwB/7zdRfzzLV6HBaqfDdgNOvjappLT8f5 ljNK+ONMNI6BixMcLIFfcqHcl+0X9oKjOOansdenQ9/NtBGHyCdeEZ6aN/k/aUnu9Y++YzpH4voY j3Q/moTaQMzTAMn6m5htJO4M1exfTzLTwlyyKS6tQUiUdBq9Da9+a80YsCDLz5OAuvUpFwzEqwhR fQnXPLk5+pTunkqq3zDOx+yld6LOGaouO4cwgo6/4LWd27y5kfRL7G+O0cwIrtJr2bPphL8ctTcr magYaIcRaBw6R69CotNOdfh44xNA3B+Pm4YLQE13Ysu4dBTnfiI0qYk+PgiYG97V+6/EZro+PKS1 jErExPchCh3RAiqaVSNZuv72SrVkfB4BMIvI98kuNTGPVAVQqxx4TRMyrWyq1vNDagubrhoG8auc a3n1dtvpKg3hX3OMz7KakIkLeDAdDSPrqEyl6HslGhyLNnMR3YnwaU57uLf5RzxwhCPwMd/4ng7s 9/8MxZI49GpVMkMsE44dvTsvI0ooxZNMNGl6Rh5F4sBHfCqRyrk7bGPCXhM30Edxa01JoRkiHupk OdWIAtXwWzBmucm8JuKPpr+ce4pBHH8YWyV+dnMAub4d+D+6fBbtiPnyHgmXvt6CnSrfp8D9qSpP NqocnIzTFI8zaiCYuil27BcdztfYsr2FLVdrpzD+1Zme0WGT0J/qcmSd1c1csKP9zC/nIvUfJ+6g PPPY2/CUkPItYmRTII6+JBy8oEcMhTfI41kOTUbqU/jpdVypBovBrWOxTPPU6NUGckDqSrE55NxD jgi1gGDq9fWUCOEUMAo/71pRDvGsHMMgoqFm9jH531dcm9Qf2KPDGybWqfyFFbFbMyjmLWQRnqxE R+sMYQw5ZHGebkkKyt+uBV01O/LzqwhFRG8ax9aWTpAXFfPa/qMV7ifz46PR3fGfC9g3Y+jref9f RVAwZ4G90rcNWfGoFKSGXt0+rctnxO51kJH6dBZSXqCBiYblb4Qa7h+i1tm7kHFczvIbK6M+IAZJ sOEkIIT+bvuvKVPlrtSxO1ejHGQz/eTr3y78COzU7xcKUwTkxQKFiCEJ0DjiP6t+etJJiFkhR3sL UNKVuTQudSBfO7C8eHaRFoQpvXnf78wkMKxuHJx20J6y0QuggKZLgCLDS9Klg+mscsNAYDYtyUSF 7gBYH/IJxlx8WMsckrexOEe2wAonSmJBAdtnxs+7fZQUMfjxAWSFkK25BbRin1obWANObQcxEbUu QTkhqzwKpw3coKuKOwsrQ2qHmxDjFtg57Snt0hDp11FmNr1WIy580DUfouZ9u4r/p/KkUbEXVPEI P5rKzpys2p3zbW/YRIVTYD8ZF8sdSasEDTPU0pl71v84t9wJRDmgEBq9e/hUAYnkD0v4d+BD6psK WpsG3X1rhe5IhQjS8d4XCuNBDXdhziJCtmrPBzasP4yC0utZlJGGqfy6NNI/H2uGmgaVO+d1xgzo NY1riZaovj/qAGILkTADWo3kywaUAzGhkPfKo6nbvrlQwX1putOyzksSGFUYMjwQnHBA0xMVB824 zFbJch3j6qFjLxs09NgUsLJIuf3c09ZAwXKfwhnVBzxzi7lctj6xraaNhCSQsp4CLu7BVDRSSQc9 3XviI474itl/2YcqoAcgon5UbP+FBDTsGuYKR5vpyC3gvfE3d1XmemfI2O9/8+eiq128XSMPDzpY Aa/mnBLU5ghqCO9RCuJlID1etvs76glG9kHNeWGgme+i9cNNRDFS/5HLb9yjNBDvX68SjV+9yQrF YJOTv+ISheN6xOgovMY6orwkBml3kwxgGTmKqzT6qt8D4nErhMrh+cpaykTC/aHXOQjUxdSYHNzB efGsB+sFKY6IBF8bNMI7EbluXW0y0yLcPeb2LYPw4zDoz9ewLV0z0J632lAjdwz6VHQzAiPIQtPT LkmV/mWwX39nmhJYD16wNYL/S4ewgc9h9GHSoJIaJjvZq9DrmsybU1gsDJUwltDf/Vbsbo5TElQo Agzm0nX9ngvVrtnYcM4aMvF+J1Om0IPdxyO6ourVjs8D1GK+YEgMB1g7/8RhZpfYooKU0PFFZ8Zy yaJ3BLZHzMB3NVZoeaFC3jYjo4ER9n1/WqgkwEQiTwVV9uD8tkjp++YQfrzaK7M2SouPaprXxKif 7Qx3ERT3ucRbXLlLt6GtK8yP/+s/bEn2sMWdThL9Okj7wH9BaE6OzKKm0uHlRlOfvwUmD2Iq50sc L/4lRrsqD8FB7BiL6v4Bd59WmTPl4VS/Km6sKxwQBe76YbLn/fFaOGo7coVV/bCa4QWCUNdYtPZg 6EopGWl73H5yM2GiREoGzAO4u2xgbk8gufazKqEGARohLvetMwIm4/X0AfW5XWNtAYC+dbgJMaPS MHKs+4Rb6BRP87yl4GKBoeWGzaHWTyS3PUVrsvo53L6PazLCDksNajFR5NtduHZhi16dZllhmvmt Ra+gfJIq755L1nSIxOCxiDBbqhqJWCU0gQ5vCwW4Gc1Xo0aB5mtSALaAkrOch6OilRqO5T4/hpSF NjyGAV4AbxNJN0dMp6mpcsFBi44uWnCjOUYFmZd/drTYG8hUxc2EynIaXFoT07ooazD0Z9HYrrYx WRB4lFqzEBxiuf9QqeNFtk01ipOm8jNePcdychpwAA6tobsRiKkf/2XpX0F9QaHtjJuYHvidbzZM 57e/w8o8jwTlhvsr9vg6QWSZ8IR0X/2FYdRy8Q3eesHpFzS06r6FAIYvDi7XNnsJCcQmPEXomABG 6MhoPqMye4hXhOqUnrGmEZglUlyh09gy2ouWuT9SoS8mnjqZVR8uno0D8uL+SY51Kv+BqUNBAPcM EhG5Z7UhwCeR1cWtn7IH65iLc1pzdv9kA4Eeb9nqjz5cUV0+OOfy+GP8Yu3IPjd7IQbODqNbN1Nu tyjuCKTC9ZFBCmc5OGR60oTjwtGIzgc60MyaXK0JsTfr1eN7dNrUD6c0P5I/u6jqbhCozIt6Qmxe e7qggwdkFGGqJuv0i1CfrNy4RiR00mDqPWCqpGFuiT5CIBI0v6mVe9saZf0GKlNPXf03FaDYdJWj jJ/AfCJbHONR7hTYC7Vv/l3AgYp6JVZsaXqXMK7OSOXk5gJZtoMhV9S2JD6gouWy2CWBOGB3P60g fmUzKsV7HAs0RfzlPeQ+J/zxpSEt1YCWc8vftsLpB4OQtKm/6i82578R6gWdbKWXspaZTcjnyvRd 7cXS2gdcaLaVEBEppZHwDLPIhR9IAM4/zHCpO0TQ1fbipGYPS9/1kDd8mXyEb69MbNNRdlseEO0h SVoHP3iNyLsjshlNV9C7x0q0sNwc1yT+AtjG36Xp0XRZDuQEyVvCHVlTgI5HAjFvvp3wCq03MvF7 8wH93YQQv83s8Bj2sXwPvaF0aQu1iagWJYJClRob70P2lxb4jhB4/hEixsVFe6DSDw9kj9r/cjoI kLEw+khHp5wZn6sUjTI+6EmXA9hHEHOs5vzJ7uTBOPzu0Zncb7MKb9EPYyuhkeBDvW8uZXsa7ewy Zkus8t39c1H8RakjyrrWDx97LQs2XlxPL02c8bXPArIQnrKjbi5LO0078YVHdWmVsJoYOphApPje RaldD6n8/G2LDWrOfn4sXLqoJ0KmPW9w3K8/XmUVkN5DngyrlSaFVx9+MOZBw+aq0vB83I2ZS26T xqMOTvPs5CB1DnuYj7AynK7XVOA10mv2hqJ/KKL2oFOw1mHM9r8Bh1gTgUwE2ouHCCJGJbTxYN57 N3zWgyzoe+xo9FiremA/8lY8wCqLob4Ea/y79S0RKKwtUqsJWRcpT4qIGe3DZ/DB6z8ZRYvjT0xQ 7jvG+n3Xf4Gy9sqEv3VprLh7Il1FgVk4qQVGDZyySXhbGKlfv0MmtT0N9HWm0v3fffir6k26WJee MJEFWPdxjLH8QLGG4NT12ZG962Nkc3MVGus1kNpS6w3FfSk6us+07QafDoc0lQjiE8iLyhG7USUW 6vI0vbUfKT/x4nzmxQ+cM36a1RRZxXOVfEB9kpw/+gqlSO5P1YhRh1yK+yr1bUagvw64CWD4IExp yL/NZVzOVeMEWpI34Ktmvot1mYxzzZ2DFZPh2596PMupfVqCGL5MfiAR4hDn9WvomUnF3D7Xhtjj pmA6du2Qdex5jIvkp7mXPOSX1KF8CaSThfNEVZnsHyI7QAQmjnkYaLT4AFSzhXPphdBPALn9/13E Rcb2+RtDLvfywiwHOg8iyOZ+vc3i6aZQ7UH/Pf96k6Ryu8C0toEfehm+OoVSn1ReS9m6euQXUwel pBFalGQFj6F/B/vSzENk8wXitsPH9T+5fn+1JHSfvepiM8UQjPeEjDlXbntbxim07polVVcROJcE uobVGjHvAVZbvC9pYqms4RAImSXCR2uKqDWz3I5GePCciP5AefOslpuP6DZQ9b5owxeqhGJn8AfV j6zL2wM1PSBKsPovwGFQnqKR3BMafHh6jNfPxH97hri3AI//h7Ht6a32SoRA23/+s684kFGo6sQt Xlp7ypuLLO4owjsYQu+FS415LPAlqMPejczhJ23XH8mH3EX/1VuNnRvyGcxgAQYXA1AdZKGLEhtM uBuZBO2djQ6f1o497qo6r8ZO64+VSF/1VJHWTZBXmxJTtsW5f9HqxwM//xk9xs5SAE7B1ncAPs6p ZGWkaXi/46AwA5jOdAJRFquyAeGpaLnkMH/nxbRBi9ZRFpfD9tU3v4Q8VblK1X1ecp6m0Q3xx4PK 1wrQNccBmlKpdub8mFF5gXIjqEFCVtD2NOe80AWb7gtkuChLL08Wr4R8grkeEHhg8iXXlRiZxQqP rkHpKYwCApD4372LaTYPDlmoYqeqWCqD1btcpswge/1ZQTbrTIo8dVfq1MidipoetYm2ZAnaA4fP 8+GkNds7xDuL1lHLhz+rj/tUDay6dA1bg3Uo7ntb8EAAEDQE1c6CruRiMAIcfcdPxBMgghfnU78h 93KQvX0YZGleLi+TL8bqk4E4km28IUbuoAtmRH5BV6w/9eXsupY08bI3IDGtOAMKAIlvy/gXqAif qOZX4a85FcCBXl4CDpBFL78OKVQsELcP3AajD4NuSx5vUyR8wE0hk8W2mtzAyyL4zhEL8lhvnJA+ 2W1ozEr8dqSzXWrMpffW6LFmiZ+EEXo3ub0bRatGd7PkVGsasrfUM6/ybE6UBu5U4AwfaUEa8am9 EKXBNhQTfg797uhCyLK5/de69HeKq+nH6pOGQNxUzFDn0lSXS6FeqzdeoqMdxgV7eNN4SRVD5N2n aBVr+I9o/RcJPQys1w+I2JKgLMN/xSgW1a6bSlIQUJkCL3fGWoGAuE26MBJ9ugQ7j480GBCb/dmH r+YtQhXeEivxuoBpF634KFGNwkUabzQhQQVps/U9Zk/dlKBRBtXkjgUlihK7C/VRnvTNAz0X9xse 2XDsSu78VFnomNhBieTqCZD8XrpWKzTqyMgJO80thc/ygcrlQDItWHKLh7YvHBdZB1HsuiELHe0o 92eKDcqHf642hig69B0iBM326uKecGz0kHI+cMelaPlKX1plud4AUl24PjTXWderiFsbjElHtK9X zxt2oaa0o1F2v0MUI2yV58wvF/aKOVg6GVZBFA6WtqFlIAJoD7Q04vNpGIsQ2IYeRMVEnnxg8OSA h/+DS6eCDWCIuk3v4g8OjuKHrjAVNE6wmIaPiGtCFtPYDigCSrAn+PiwiUHLEJT9aSLZPhB1mjC8 UEFAdA6KQiSzVbQOLYn93hT+oLoQCe7QPvlGVS2tmHSg62t4sAJa6HsXCN7wmS08Hi1VPOAtboRY KuVUEN3b9wZJBzlLid+HXk9t9L2zZkIQxGUm2fG1+quHnbtNTobBY4NkUTMSoLEbB50Kpk2M4VzY kfeNUFDNnpnuYBFud2oyCxQKPKSPm3PecyqaQBCub8kzJOVlRpas5M3wEPxrF8xt1mXJtTSd9lc+ 2l5BxLVQ5RjN8yQtwLsZgMJ99hyRyMELt1pwNN/YvDlyxYDqIWK0aWNOoZMiEd0er+rxN4ChEO8e cUQXVm4FB4xVif1hRqCXKgUaIQJWkm+5G4UTlu4tMs/1yGy4TEmvm/czy3pfZoCgNeQUHYHP+Ar6 2POJUDXdnnYSyi1oX1qO1HZ42s8CVn1iDQdkmn2sTY1evaP6lfWNG9Aoe8mXbm5ErX8HuZ9TGdKb ZcYg0NGPc3SwMCqK/Br5EAZwCKF0uwQyFrARU2sOMUUOSe+VlQtB5BtWjv/nbs075plVPxXHROI7 bICuGbTSCYeM1Grod4jcUTxCodTHV2B6jP3ZLOMWwf/Nm+x9335qFpPyiKvgCnmSmpqkYzifH5+1 D9c9kVg2WhEo/pvvKjp0Z338t4uLJRwVuXM+7jBo2CQsNBlpnuyVRPS4xbMJPR3ISK0+eXKZIKd1 r/d1GQdfXp83QdNglqnAJbFcESEXsrLvinLI8JntCtUNORCYDPLGAs6tJNNY0GPlFndsBXANx2/t T+BWUuI3Yf31kHp0J9E3pkjUHkNoW8IRgwTApffLh0tZhQfydGUUggHdOwFBCf5qEuCJCnQDkET6 SI9w+C6u/Y7aHzbNBoeb1J4a/+tMVV+twEr///9jdC86otB9qRkaiRyiRy3wHv9ux78AHLDpa+fl Bq7CkXUBwj21aRzt/znPOu/bzqHf69LrY11aGVMcIs/QS3bovDrzFGH01B8YD+h1DUoH/Xavc5JN er95RJO0yLFs8n2hqG6O7ZzLufZiOb2aZ9tEJw5NDID6dLMrves364s41d1DCugaCPqC4KwC9oob Sq8v6drbTZ1uWnq88NpHlJZ0515scAafDSv/HnKS6OSwjW9Z0ux0mQuuhpPYRpQBHUE9oRkkWsv/ 5LRYJDUHMAGdDCkUcvsKiW303Nb3ueKhvgl4saRWOZZoG8lVHpsAM2+0Styfl3Ok1Us2A3R18II8 Ky7p04vjug/UvMM0x2J1CbPNeUKXhaHEkf/3IQtSLEbc8dDu9CSMwODJ3S49S33AX5JaCNjM5mis HKkx6zIMsWeCWIFmV6cXWAChWt2veT03QJnLeahJF9NFppvBrzDv0dmtNZ4TInd+S5uTk29Wzeia iyRluQjHsP2ARbuvW5hAZv5B+arjlhvDoxZy3fqkbJ1VRfDfhY32It94lpZguZEio6WmCcC9F98M eglg1eSJgXV2PGPhgMC0xoOeUcIpqkH1CwfqBva9yOy8QBHbsghm0J2rE8H0dTml0YcsTuXAcGl9 aejKvA46ERzeiL4rkTQXbm0U+RAJOmbAbeiWct1Or+wl3mFHA2Y2unnIhUqnxKB8xa/VXaAbIJtI Q+6W3xpetVXGLFQfKsOzjkyDJT76weL7hJv765384MBFE+/VnqNoQub4d2E3J4g4LQFtwMTnFIUt ZoyL2ijJgpZ2J/eQxWbKKrM7iTeIiGRCXB6yDKIs/elxENZbMj6WQQmcrg1awmUfodrkTP0eSLBg 9lMPC9P61CDwrGwZpNfkGbc0Gr8SN4sMgnQfvEipNWkiP25tV4ajZEtA43e6qm3w/EzC79Z7BnJw RjPfzuS/qlmt/SPuI7M3nZ7YY5cnxJfnGFhK1khuR35uHlr1r1CQlrUdcFajk9xy8VbJUgwkN9tl rdlvOC7nHZn4gGWIEAnbrRUHD2tUK4MhOWnmbXSk8A3kROwgC8qanxDoK3vr8RjUn7RppASFlplM 0y3BGMGlhKiOB8adX6AD/uGJsKMO9hh0brTwXpO5Nz0AjPSz3zdxpQWuvx9MC0t6CRksJofdyYnN hreaqR9IP1uQbnHc701Mjj1X1mwhj86+UthoqhAq2TTsIF945ig55GK/y+F01KzFp0pw7Wv3Fhf3 hs9sY1JLXguCq3ej2J6p4PtusUbcu82lomh02/xWVVozb+l8KU02Y0GAmaNMTbrv+Vo62nDZx47l wgdjgTt5yupZXs1TguSn7qGebZiY2gdXYc8ljRoiSCDV4ePRw3FltyDVwffB/E0Tgx6RUbdRrI9q dk+KIDzGMW/VWBtI1yZHCGPOGLZD4g21YG1L66mUjRZDznXOdvvCVCwrh5nAndqzMpx3407PeX69 GVEP59kGE43RX2+bLdPu+89WakP/c4PF3vmtFnfxEvFFwLYJ9vW0XySYHPxmUIHuR9tHUjriREPp /4Scf+OkOv2+5c+X6UsAHIi+uJyYRO8KYyaSeqT3A0kogxUEckGIvYzHFjDZ/kXajBq04f5o0VdX sWz2FQTkeEBf84d1dYyOnkaAeEAqnQz6ZfCCxuJSajgjmIjcQxc8vRgnn1nSD/JraUITxn6IGCRG y/P13croUpFyGmnimX0V3caSqVtt98HSxWfp8asChEZafCkeH9SOT9y1qbpQFOY4XQGeyhGQB90g SyhFPk/BPU3HrsKaapDrhSlGEY5mXfQ6H1UBQvommtK3Hsx0aWiu40KiE+O8zmR0xLJvbQ15jD1s bBAYljCzzJZRoGlKXTrlr+aORkF9FFQXth/iQibziSHT2MdMUW40VGCZskBsEi5G3Xh7WwCtOdqn 8rEDrwv6veLOEQIGbuinXDQjRArZSerZr8urPC6xpW9nm45ZN1+JFHHNUYAC1LGfkfPW3qDbp70w Q0ahUPcYxgtedpjtgm9nlTU4/A00EqUswvhgEJyzpgrgVycWTObRjO1E7NOohFivWMlma1cN+seY S03TkhlswCfZe5Cn0TX3u4OiiYm4SsH7AVh2j1yiN1mfoLmYzz2/6VjYY6pVoJT+BqAIltY0GjSN sFcq2L0opw93hFnQFFUNGXW3nMdRfdli7qai9OvZgUY7O1xFYYHUKCbpfrzhVJsqLl92Y3huKJE0 2T7RsN9JnXCFcayY3lDTd9KIk+CQRiHCexWnjFUB7dMcB7U3N9kvfeaXyWqlqtj6OvHoP/qZBKRr DMCsEC54SGC9Mkls6BKbadLh/R68N5uyBehk+/MLv+2pOllbptJP6KDOc3lq8an4jbqJ1VQf4aT/ oOXCqbaRdy+JndkTfuLm4Gk74XhbnuA+cbshUNednvFI/BxiAJPterQkoq63gMJ+KzYVcOgZ5NWf ZPV+n1u1lByrz4feZyTkhhzWdlVyf0F1ke1zwojkIlYhm6hA6x4YIDuGPD4hkmLStlxXgnPULE9G yYFuzPz4F3V/+97DVP73Y6PaIvzPS0TL1fFhotEczoFL5Q9un+iail2EDQqWqBMay2kIhzoqvBF5 F8p1uiOEYmYpPwRrQcLJLhVkieSCsPkK0fMQEstig7k81DKr2fv6V0XtA4FgohOQOy262xk5Q6Uq w0AiMWEyjUQdAEDluJB4G5IBSs+aSf4DmFd5VCpymNlBW54T1yi70bVuxWpQpKbBGdepskY87CKe 8ZXh3fkfX3HvpZj6F4rfCVfbdFNNMPfQMs91YXhCg1c3JcVhi0twEhJA7n6R/pJ5N02xhU7QHRL3 tLxblv2t+yJI9ZXaKS649PpJqhOwxdHPRJHbU65k9/8Et6jva+QhGNniRdGIVJVsJdxs8r3G0rr+ nuRgvKq9SrbziFwNEqG9cZ2s+nBK2Fa/GSlp9RB42ovPwGrygLTnZ9a88FA0qfU5XeP2WO0HZkR+ l3sDteFz5h5oOfitPc64oHzj+xUwHn9Gx9y+qJzbX5u0VgpE+A8C6TCrJ6amEksxMTy4e0qQDaTQ 2unuCSM2vOrTNm7MqYdZKKZB5h0RW/czZ6eX4qURyUUQPsMpP8+skWfJ+V7GQpWchYpQLasASvoy 6epfJ9ejXOECea5SAMTpbV6bI/jv+cI5LEnoPLJ+hoHWMlKCzCvreT+seyq0kIehHt2TSPAveRRf I/LnFkONohDRtTFA0wiyPBpvQEftKbtuIK3lUqocVcu5FnlUGne91hCzQnFX97lcDrJ4ivxRnWfC vpovPCf/3QeOh64QLWTSVHx5VdUwoiwxbMqT+ixQsx9vuzvd4ub0LImC2hXE5dtrj2cFlPZeEA2u jhe2+Ba/KVKlhMr8LSVwyrKWfvWytQFEwMtALkedDiPrugdHMlefoaYMzFHdJ/fRTuSmr0v+P9q0 mzmKkc+koOh7X7p24FwnvFkspjNsBGvfwZKKR+e5qBl2O3vT1a5b50fMyNOtraNwMabB03XK5LLo +HRpMXdYZ9EvUt3yHLaBvOofiamNvjqPhroYF6n2wyUBsWGw2giRv+BIJINHjAEFh8p1NVAk+krc 0MaqJMVYxhBxg028xFX1k7yQvNVva7TKjOwg1neQ/X2nEqEmw61jo6D4frnh2mEm/7nCxPTCgMcu mzOirgokh2bqeA30ZM8gq/pBVj+UPQcBdirzwYtvJv3uiCzFtw5N9NIwaelNTd+RGtWu76noBmDE +WqCmrRDxVWr/vRz/HjdJm9yRXwuPrczhdoH73kR4+Mt0+/ZaMZPgIigK+75vFcuZeQlcbNcytJx Q4FJuwlGqYHOP9jg0c+k/4gpk5wJlbKIr9zndcW8BbrMZZ378q4JzdrPqz9CukBYhx+DOl3AyHg8 aX8VoIlb9MEcEN+XcPTm1d9nVErCHd4gsK+stw7hiYTRTAcIm+PmrpjV2ng7Usl3FYP47AZcusuL nHWFvd62D1boNiLq9Ogg2FpT0Dux2DvmO/JvaEcXHy/+iRntXfvttnlBxuFr1M0QKygngQjhUOzH S/KvzLCCkkc24SOmFmfMlI4fFzAjDZ9m+1J3qBww64TF8zeqn3pQfCQ8k5lP4O0FoXfvq6fJQXk8 t+CIuVX1nmeZXg7PC56iU62Esr3LWLqI+WWNHWgXZi7/Sx61rT6UOo2vK4DwmVKlsOm/ZNAILo5r Y5FCuWxcrCCyOE2tH9OviHZH44oBtdRijFrploECqYep0upqYjva5sGjhR86m0EUfz7YFICxDJI7 f1FOI/6qQApozQRWrL8U2Daomu06onIKpRXE+HKVm0JxlDUILIqLJ5DJ4S5M59dx4rly2KaZ0pfn TIvWpMvnmUrGQk1mjFnr5obTyYsed+4MPGVsJ8MoM4YCRUy3Pn8xcJPiW00ub0u1jMVnHTmUyM0U SEqKybquhG3z2GZJw/NvCl24Ih9qi8Moc/6lWJGjvPIzDhVHCpiYxjMpopAIbEPSGkk3bxDDRZg+ VZu3KjAUDHAJ0LJXd9yzLO7je1JnkKx9OyczlIqWzKICRkVHwuPT/1198pFwCQBPD2FgAZvnl0Q5 BJFDfEhIu25tPj6GZnoB9KssGGU4/wh1xEYotOYv9N+GR/8eAr9ZFBlRPIRbZDQ+gC8n2H1timna JwjGYwtzCBI1f0B4IAjH8EtnFl8O77/PUBnx/u0k6N1FeBuJkNqs9I33TjpeOv0x7pklTgUmWVwN F27IYsUzplR+zQoMyOvTlHdCQaZixODXUiquwYpbCccfAtJhif+GyW+wnxUjPG046ACFbubXqOFK tkHMXqxSh2zawoNr+3u3OJ8e4EDrsOjRJilSAWLLUfpGhFvQkIQ2E3s0lv1BdyQFB+DKsnW6jeIO tmSq7nGyGB0Ew6W/EKwNIG52Z6Y+DmTiLaLsyKbr2NbG7AmZuoGDid0TwkW/SfSNT546h3ZlqlN4 U5oyox3GZ6rggSiPEoC63I6c6AsieGwV3T1B7t9JeU6yAwvzP6ehNuOaWobQsPhVqr6jvD1NE1Zb Vt3oMtjhQ3879mWCPnx3aDm40Lpr1jGjJZ+zdklhIfFjVs3GsPbfLfMF6yY19Fk54m+5/BlzHnrf RkXXOs4gqDYu8pKOl9+FeoYZgji+yvwagJdp63xHKZs9zG1vRiL7CyMV2YdOWvTI/Y1zePtpiLOL AnC5bvTQ+cT3kCBb6Nhr+pOMktOGwTCndpmuaEdXrScykyAq8EcaXPDkdBOmIo7eqno6W5UFZAQr nuEKZsSTT6wkKVXxR3UD8bP4Whb71eYOUnRgH95QLMfmm5HHYo+AJJ4MglHG5kgSob3uITIEA8ZD qAh7JZQCFVFXl4PuQnnNuNveKFy4X3WE7EwtO7l5RQrHZptu08NCh/tWSFP/pYAwpG8+4R2/qZRu 3KULxOswCH5VZCE5VA1Q7okkeNSPmkccESQ/D1h3cX8X5IWX8s5WuHeBOkFRzEAA2cQM0NKciA5G s3eOmEwRO809t6N0aym2/xucsbepBLb1jarK26fGIUVWbkg1+/NJ0MLTDz7lhTX8pvvNU9KQnFIg p0LRn/b/CASUnSwCDPE7EOsHpyE7vROgHJDlL/5fpvYM/AJJcUk8O7/WOVzs/dj90L8d4jR+MMev oCD1S1iu5N9U319oUKm3/IyFBlfI/3PlSeyv2C2mB8gDUK374WurXVTuFL5XLVap1sm7ocyNjFmI rTB4yZIasgQMNzJreta95qYp70B7nVD/EZrnm7vSdzxPslmCdy7pOMFz4iJWX0+YUYPlZqC5t66M uTxyBErssjdFDDEmSNXqB3bZneVrWtB2nk4H0CTuxcMnxrtddr0BahZ1EBH1my36aAim45r4rPTh jUy2NAjaWoxyUBW0H7vCiQwcPb67KLQ2pdwyDKPLOlcu2SYLCy6sy8zI+Ar9UbIpSGHki57PI73h 24SW5Dn+67HYFThmOAMARVIS0gaO2VBW9eeKrYJCdQd6KTRR+/VDHSx7wwoaCU6PlDVWO6udVIWB +pnAhS2FeSv5+ECVGqgtJdLr1LqihAoeCzdH8SrHtkIwksjcbGEyKTUImKX6ij8Mrk6z+7LK4FNY Cm/396NOUW7vnevtYwnmp9ER0vB69+CbCI41PnS22ZrZcF0Kuk34btaXaumly2YYgzYNKUdmZGx6 MaMi5N3WO1CirJfItERjv8ykbJ5jyWlBVY/ITE5ZzKzTYggQwDIeBtOVscMjznQoeUCooqEmlNmn 5yNMy6PUqGeOjQYO6iFL/DsThpWQ5j6GMfedpOyYtS95vtSTN/4OE4kZMApO8XEWKkMv597o0gUR gyC3sSbtb9kNDiqySgoXPHjjEnRp+lcJaWsdw74Jc1Bcf+QzCmusvLKfXogK7rjA3cXzrDUy6S2K +aH9gVB5/4oVV8tuS8ruP1vVAeGFdVzurGxsXNUlrxYHFwH77JPZonqq4J625LiYpfoLCOhlMOXS fcDKSY8NcCb30SCgh6ekcurBNiSI4g+b4HcP+bbiMjSBZ2A3BppyDlS7jGG1WWQyFfIc3ZKT1jAV 03aEpMIxcTs4GLNYp4bI7U1rVei7eTlwXsUaHVkABcanAs4P1xP63Sk17CF1zzEBi2ZyXNXM4D04 M5nBJEnZLh0d5iranudVUzKB+5z0VVUj1a5JupS2ITrWWv2RGLqoS3nvJA38xdp3oS2DAFkyQybx gCOGWGqcFJ1Q/DYhVc/A4HbfjZiGHJ2B9ynIOYHK5LRajxNkom3iaP8rXqpSlhGMdxf6bvnYt7Sv pUHCfX2q1qOHm0GtgOSNp9Jt1FZi/LHX7FoqF4fy50vbLpvzKFXAvx97K2t46z28U0x6bLBDl5mZ IKq2TGqKyDKf/x1+1iq5ISGtkWgdqEd5718Gi6TxqwG0J2lgI7MHm6SceyfQ/5mqBzZGOqxwo+8n F9LNL87KSF0zNDEShQL8yLI2k8i19spPYGWw4nQx++YwZZhoOFMlOs30Hzb/hkGg9TRowFD+PzyS JEMUEL9Hjy2pMd9KRRzwTs2+DwKbjvRRALSbHJvQDJqZf6TpDgSnJhZuGf98hTo5oimdABKjyUaf hDvTUpFp13xKII/it3ywM72tI3cwJBCl4hkKmVOcJegPlfPNk1xYayCFM2HxzWiZdv5wQzNVh1/Z C5M4PA56CsQ5wLYuiEanMb5b35zzHF+IlvuZAnP7CjNuapjc3aScFM5y8bSogGrRa5DpnbWLStKN QzMnF8R9d3c9bA/Z0KjJhlIldxSOged4MSH1aFXEffKYpDcUKws5ck+BZziQZsCFRoakvWb1QMd4 QjGu42kN22CuJ0WKvSsv8yn+LFCfflGqrf2SsresFH33ZfWsWg7iIYBcMbmQULmVJKCqUtxPgc4h JpGKhVrk2DcqWdnoF9Sk6Zy/n5xldyKwZBCsrUylOeHxvV6xHPdyJ6kSLANq3Q8j/5ulRSljAKrt HBlK9vosz2ptcNtYO5XunsPVQCz7kdG6WWqdI7z3zqX1zDDctY/kToKGyTSO6kEjr+dV7jqp66UE XDzDzi5RwaJnf2P9m3Y+5Ic/OHWmLNDpX45j9lr1NlApC4IudcLQRnO7Jausn2PrIgKKfu/vV52y eJ4eSw+6fpXfddInRs/ZhM8xjaEFxUUbPI1zG2tlhiyhwlG1X1w3LROfIzJz/R5TPZAFHbRVE+m5 MuSdovr/I9KKbCoCnstkcJFNgjwF/VxCLN3TP/HzvrR64BKc94LrwLcHhKyNcIUR76yqUZltg3+e f29XW69K8ANGwCJsm1dnECSOaGrbAocqRVRs+fn+1hzqYcwKg1/m7u4tEkj0xskllC/oIVznuX6m 2EM4s71bHZmYD1CClo0XD0cgVmPzUYJLaXLUxyWk5CPfHTAk/dUa+k8iviJWgdrPdGWJTpji0gP0 W9IAsYtQZQoAK8ZTGcR1gfJKrgKyzweWrWPmzTDH6OwL9U02Ua+8cULu3WPJ2qiCZQ/JZJJyQ7Xj /sas5qEA1r7o8+3QHGbGXSmdhy9XfvxpDrmjSvzhr6pwQ7bAWp5f+Yp/x/5jVklJ6ss89AxHJQV0 mhf2+z5baHg8MZw4OB6wjr6fStXgvY3ZIFa9arTOAF38V33xT1T7QrWy54k10oNwcnp2wHg15I41 WRD8Y4nY06+AgYe7mwobaFA3klGpC291HcL2S8o/jhPt9QE9hJY5vOLz71zwfI84IgM2IsREQkE0 9eR8SONTSqOihBtj8RAQckgoapywLhIcqotC0UdRXL7ensvjBISMsCGhxUQ1m4W0XSHe5ggazVQ8 TS2AK//8HUcRIDHpzgki5dohu1AQGo/AmlxxWW+XjX3Pu/aStNs5dGifMRj5gfiw+ozHeGZ99fbU eaGPFulCxvLBh7MRc8fyyX+y+q09yR/kAwuYYVb7dg/dhZe+0A/+b4uins0UH0/xGu9Gt6eNnh3G eAXlMevpeC80YpLDLrU3e8KZMRMu7wmM9FrYSK8/rDVbHk4ftYmYV4GvP0erjB9ze+nwc7FhcCVk voLdZdgt49UHdvDpRhaS4QuBec6QbJ/2i6hY2uCjV1XRu0vd1mGFUU1QaBRyHMy2GgSz5vWtoy2M TGyhz01LvTLZK53HUdV8NkDxt1dkK/hglZqjnWlCKYB/yqPkBD/vBS3wEtLoeYqhOkUgIReRJXJv Q0Ad4KLQNJNlBdxDZ+AEnZfpxgpw25pDXg6S0J6weogLKqVFp5Y6ZNCr+TVOnhH4xw8EvbNbCTgy U3Q6+5+3uLRXav+otperHvhcVZxgJWVQQTsgE4Ih/loGiZoFKoOXFfvSRu66mfnUkHOix2q0u/ft ueIfExMVRkX2wIn6Kj0Jvc3Mjd1x6yD4klBSnDQW9Nc0AO4BcE+dL1AYePXiM19Sp+2mENJx5T69 dpGEcWk+uoqFVCu2/8ZJx1JUzevi7yeIJySfqCR+jyrvGxOi/8S5zPzOYIhD8I8epjfuFt2+C69Q atXzpKfCPAvgTGxjdAQvktPOaFGD5yk3tJDOOoMIKmNgL+qSMmJHIDAuBWXz51LbVzRT1e5OZ38c 2g+yGgTY42+LVk+Rno7rzepHltiMOo2NP5QazChlQCFy3QqlpXPrK6LaNJUYibVrKanTmWUKGnrl L7J/i1UgJt9/wsvYNtkivD5bePvAjOKkW255iO6g1sbkMxRb++ddNaA0RSHJxtZk+OIF8L2/1A+p rtXLu9d6aLiHys6yo0+QQfiNMlx7l1hcVXamTTM0vC1OJ0M0m7UcDL4xqmnACgwh67cCJiQpW6UD /PxVne7JtJjwqDayhQIb36eTkhl4TiekpN94vml1pAorOgxafhIh1Mmrjyl9Og65j05hwIkibVlb DtVjpnwFE9oS1tzUaf+sTtLI+p7PEPdiFcOqeDwgJScDMkJbtQD496dMGr/U5irIYG3YkGaKt4lp 13zMeUWBBHoLGnvqH/bMLqCEmreM0U64E3pKxClgXGlFVXnkZjTFBRKxClX018c3yURJ8fzn3Kgn qaghaEt/llNm8G1k9vfiVULg3IxScRGU9VEr1NwT0h9HAktFYxCIxmSsdouioBTzM/QMsHQEzXAA MSAUfzvF8YssPaFpa4U5jejNCP8p6iY2ebbKWYMjSwt4puE3NucUqWyKWp/+E10YTyWmwapihk6S mH7U+zXZ01kF8hedpdKDxDacj5mdoN251BBwCS2XDy5M7iI4V5QG7AO55m569ItzfMJAY8ZXCJr8 oq4CsIFGu2PvRVIuzTa7QoBxHUfcvZVtHmVqfe4qrdUQiyYS/Xnb7bVRNSfr5h9Chrr2oLnk38HJ viBNb4GQpvvY18UxQbCaH/XAj+v8hDTCCAj37mJ+Znk7OCT+6gpSGqv55510SclssMuRw+ZssF9w k6U6xdfNODvrdWYDDrvZ7B1uDjeif9EFwWEABPh++HzEcKYTmLOiaZQmPN10GwCcDBohpyKnmH8T QB8T5gbiz+cR3rFiZS44t6vmQ8QxXw96UuIT8HClWFy1cYu7rU3M4J7okns+4f4XzuN7NTnmMzVa xksd+pdN2267f79/bGa818uXdjWqKmAJmZOLs9D8KJZfEMCvL4YdSzG87Tnr6xZR3ab3BpD9kmeY kYlNg//waoTy7E6i9FbdOoLrgJWarAMnf4f2uxPwkORKOA5hJucyqJku8qfD2BCYhIpy3t+f+3V/ wMorT+JjhqO6rgqpNp56zlBLl73Tz4NJldJ4nE3yqi0UimrwhApfc04vpf5lKrF5vKOPQV8czla5 ZpqXWDTkUKp0NsGeTHZlNPwx2Sp7d1+ZXH7sLjuTh3vFpTCXs6GsTAAQfzJ92PvSCak2nXhP2OEZ /OJ/AZZ78Lix45Or5awmWdgO0jyh2BJvOHk4E4FoQ+IiLsLIgDM+Pa68xNwk4IpWWwDVHs9nxnih LYgEJ+pBwkNl6l+60Y9WM5lFLjkFu7zlRdxfUOZrwteyK20Q9fVi8DNC/3py+YTUs5VWpuR6HlSt Rk4YQXCj1YJVKvwtJ7FljtVKcBfx6JMigFv3JjlQteDWQFmaNbD1RK2mfk78R00SerMag7DJpzDA 4DLrsz0+N9IlH2Wm2188nvV9wnWgAchTAK5JLTWJ/7GLqGGaglq4xhYi4DFN7TVWOZ+BHZ/DFy7n z1BheLim5RVszkPVuxeqcOIut2wrfoa7+bfUzuaS+nEkqSv9bc+Y4Z26qG0kfnXpcHrC+trr8GLp rYqzZbTn21radvEamg9G6XdGRP7GFFNOXddKtusT9xrlvv1Pbnuf5u8MYkdcBYlh5IOZ+BRw5mZN 9eb3Vtkdf00B7fAFeX0V2EcM/c00appUkBJLpzvwO/8be/XysyasYjHdu1NBVglJ0imNZZeY6juV PbG9IX4Iy1lIhtuFsLC+g8bck5Efg3mzMiMclZrNAJ0d5Z0xgEaJlcPzUV9ppo+Y+ISPPSCTOn3L hBUDDi3locvVkCOLMc0/fVxDjGd/DG0AmkicQT6uVoQnh0sZWY4zIlG89DzjW7WpMNkcbp6Ajd2L Vm0zEtWPFMmsGiz8svS9BRmBSAI4x4j90KdOUTCNCmhJWDIIBBsPsEyl8eeKjzNrcZBQrwgLSgwm TeJguS13f+ri0STko+iRarlXSXDSh2RGtKV/tvcqOOBkIgSnUmkaxduidXNA6KDIt6eIQlAuwZc9 aBNSoqDbTQY7urwPFlbrde3iRzw5v2YDdb4re8xA6JN5NnX8TTmGKNFEK3gCEp6JJYe/PXx804aU KDuscsUC/82P5Qaf3m1KDhNPh7LBamodMZ6o6ONd1xWqAEyrVKNdW693d+5FJq7xl6gIeR8AHynY TyOy0Z8p5JG1zBw35yw4Tk18BBEuiVqCxHWY4b8E6rQb2A22Als7q8J/chxSCEvaxtvD2Louamoi eJlsl0aHRqdI7+LIU4NxEW1BsvyFjCGwk+Efq1Gk1fSIqnoSS5JKBx18401qCQdYM39O884uQ0jW Mkwu5LtrD+sFE6deNMZS8ht6AkHcSfOxGu6iDGCyydDjN70Dn+IdVJn89/L1U7/zPEbPgG52xLIq Ef3Mlegv8mzg/BiNShdAdu9j8fGwxKVNQtovpLhbIJxMdPAMvZDKgLsohCqvtfw5SMH9FQ4kR1Er +yu4E2qI1Ft4F986FtCZirp3Bz4VuAIlcfWvBrBS9j2L3MBdJ6OCzVhSiOEuqk3nJ399aRfv+isR 1c13CSXqWzIT428Mj3tpj5tVtwnv3O3ax9YhHm80SUgtDl9CnAmk1FFPDjRZN6rkhDrNaI0LqdCp Lv3Iv5FIelKEKLt2xxm5fZLmqAmrkKvIEBCeL6TpTcuysvJ483oT/VE34U5j7UUC/aK7/iA0MnPD ZzbO1WykDeddTn7qiG0xDe7bu1mlxv6ZNVxp4Q7dLXyuXoHFTECHdrYozk/vWOXF381+G0VJqI8Y PIGPzaNRaFvEv0TMZLIzSRnf8fiT3zLOj9GOjzUkomI552qSMD6BiMTnncfj9UOlJqljftSsrOGm vi+P9qw/xI/DnqZ+QjZzQmDBw2Oqs4+ldjn+zTk2n6BXSj/Xg3YEQ9YnZRsJOWKi8uZ7nKQ+RkHj npev/3zcCpjdXQfcmQLJkP0cZjGilxUjgg8ZeND6TmttVDawkkrdlolLIOc+NU3wDF1VWvWZANCu BgsrWmbEaVGqi3MZWSOe9zwC7eGlt1Ybltyd1NmJ5ybiI30kfGRwYENuDHM5guerTOWg4//ornbS MvLx8frjJjJPwJJxDDShlTSGJOtYI59GvrciuIE5KeDPpD+wLEgW9DlLs6qRIMMDxjgm6ugDf3p1 dVMJDINusUaSEl+aCDggZFIomt5RbYclPmhtxDBpcGPKAFID3l60/LDmzgemlWSqnUg6r2vtZxut hq31EksgJTaoFfdBaH7htpOMCuEZyXyxT+ktvIVy9lYDoS5xxDbL2NIIvtVXneCS4bs3X3sCFcQM pdnjm+Y7+gxkuT96uc9FeAmXpMGzPZuWAPfySDxSxaY967U/VFXEJNJwj0LwxWX7erjnE1VQsccC rUC4nUZNZmYq5SlkQVMvROOJ7OPJL4HknNUdLs4KYUqsDShGu2IpyodpLMg7/7wRc1LyimSnxXoh jo+36ASss93bhOj02UofTI/YjOg+nCpMfq/cZbQeuH/IISsPza94ys5Xue9NyxQgLD5fur9grbRw sxQJhP8QPrSbkAx79HlHYX73cWdLxwqyN/GaJhWTIZxNl1Y/wqt8+GcNR4UEKBjst3CV1XSrOqTp DF7yfiFs5GXjudosqFraARLbPPiEY9YdUpeEJ1FYByvR+PV8IxLEhS0J87FkgLp+4kv3B1P8DT9y 1m0IK0b6EVRGMpxZrKUd+5nwc5uT9vY6O6wFfK5Iz6jMkKn3FKpEcHZu7CWwTD99ejdy3fDNlz+u w8PwgIzA7gfGiwgvqnXG1jrwNoW5F2/23B6CafkUsmOaWY5j2vY3XofJOXfYQ8tv5KFO4waSrKhD 10G7w2+Mwl6hqfz1+lOghfsQgYuWPXjcQysiPTT6XZa9OS609kDDy/M9F4FM3dgySkmceDUE9uTh DJXZy32NVOLKbCBEo5pkC3qDY8n79jLmiNAjcl5OsLKlMQvnyVgiMHDUAwJmwwWl60ZqLPNYkyAN NU7yLKGMkJP/RRvlJeoI8MqzhZR+7IZsZD8XfIu+zS5u5rcrOzUHR5zZduNHNpDHy3AWDJHWBR++ Pa2d4RzdT8LNannK8xYlMIKUYgItJ7slJEXpg+md3tzDaK0aRXu6fg2K8krwiwZfR7xr48t2dAnr I4TFMvD4pWN5s73PIsOmNCei3Ve8WQDr9n1KdMsyMs8aezwcH09wh39RUw3ubX5krzDRiXtm7cRQ cGuY6r9m4vKFj3xsX2OuMBjtJiFo4J4LxHq9zzziZ0THKBE99PXYPlb4O/hdznaUp0BF16/jG81Q dO58uI6W/vkd3h4hIBd0fQXRT1KO+a6dRlwRMzAlAAhh9H06iXdGiRsrmAvs4yaphrD5lfzL6GZH Usd5oSWiRd6xZABdc2YABnhd//Mv51AOYkkl83yt1ziDTmJtbOKtq5KKEoS248oNQx5RiglRzRFO cJa8y0++m09axz2o038WVOKhRwRRtDoSe0nTSee2GbrjipVqIjL3T6EOHyx8l0xEnWwSd/9p/Y2b GgeY3bfdo89uzzv39S5FDhffFAiN9NMjIkWXLXzyvB7kRu3vGRYNrnVjvVzVRGmXEec+b1zLOJ0F 5Ahxgc9z9TfqBgN/ZtHj1dPPwrjUFa7h0phgHnnJSFsDCc3MpqqKwD0Phw73lWUfPSECo2MTRRCb reO+g1cboCigyMqAqHl73rOMfz2NakKMo7xXtCv0VmVYcG5r9ExPWb+5Iyt39QI0F87hPKi/esFR 37+NDXWpgM1/E2qFqhsk/PM1d7y5O9KvDrEgQjFq77oJf5BZYbJc2dFEDz/PEPweOebNRpG9ovii tT+BbH5EIc098wWedpAt1Go5X/MdK8USXifZsIUMwOe+Oj5gpSF0BhKbeGgKl6ocml6P1oMv1bEa 5OCOQC17nZLPc0ruXSqOui5//WJxV8SqkLdUdD5hyRnuZpGk5Wp7eU+qV1UWQxRJznKICMFFiGiJ 5jSdQloMCsurbasaHHuRMH+kIAvFDNMoEMRI4XGd0zpaeOgQdBOBVY2Irw5aynJQHj8PzW+iO2T5 T6aY8DBN3lvpBmdGSNUsHv3ZPkbOXhq/myDfo7Zr2NmgZawYdYAPvUsNHRcvmpAw5J6mkzbpAthf HLs14XVToKEpEixNQ5if+YxOzaTYkirf5mrnCeP9FUT9f6AKQjnAVrJnkSETX8gAvXU8PEp2lcaz 1/3CzRhKrEz9eYYgin0TaaFEPkoffYV4fK37WCXW+HyS+Sh2vAyjqq+IrOyUj4w9IeSyiECQwP2W DC6U5Xl8VX+fIWoavSJ/ALb/SZe+JOPFUpk382ar0hzpDkF5dp62GKOnq29ZDUYvwacnMVgxEC+3 jRqcjrCwFn/4RdYGQhCSFRSoe6b6nAm29/VTo+aOTr9U/4m5pB87pEnCQAG24LE7uoLXlXeWorIz h87DSgqK2/7pU42QG1gxpaE4u1NfvpGh66gAb1/pzYT/RTA2RkdwjopxovYvdipTXUQIH6dqt/90 ZCdLSfljXH8XvKPmpO/j/GYVm3+CMRAfYeTAlklyRpsfL1crYFA4p1eBM29e4pBBBIbdH28LQyxX t0Qmc/FiPsMtpbORhC84KwRw9sE0gj/As/UGIuDCkhdWPbO5SVhsNwRq8cwAvtlKEPY9wecVf8O2 o2tgTNagkLMvTbZRF91uZ9XD//3CozlKpg9iKYdGxM8/3u+k9Hh91neWgzRHMkJ48QQF/aka+yd5 ULnpg6q0S7pS0zhphZEjeEozk4T9h9rVju5Z0YlkNFgLNznY0zkjGSxFumTSgsMmYxZ0IJ/t2GTC 0yX9cMb4whMADHHQou0Z8hLzA7XOX5Bok+/fdhqtcwU+HiAnWd0MuWZm4uI8Nj4SrHFpj7kCu7t0 1HAHmm0I5f7q9wSXyusg2jNEjPpDKWn5RVAtyBZHk+2i18QgoZGyVhBQ6EJoDdQaUmz86YaiqMQB f6qTeVPrQghjsw9xMutMbW3qEeHph0wxJ+T30gNll4xislR7N2dVkzFMhQf3OShMnH7G6CzqSuVW yNRLNkr+CUnTS4XbjGgMKvuCttmAj1PvumlaNmu/T4y1AgvkLw6bRQX8Iw8nSSIynAVRUi4vyDKr Xo0hWsEWZuvOKQr5+jtidU9r+IbFgldvbsV37hGcVTVU9J9pcX8cp6l7XCuH6ik6f5/faq4mWAdF T8563asgElFJ7agsY8XfyAe0Xe7X31MzWqGlo+PtfiYYvqRFkKJ9zO7KU+NKePH6Gk6fCyUtRJQs JnEH0L4KSigNBgwTfvS2y8xMTyjABrhAewwaL/jbWUX5lB/K2YhYAE39chLUVrK2vJMhCpYVjdzR k5F63HERfI/NnWxHtith0+IefIH2WBApjVVA8L3GUSxtsruoH17q4kEnMlm5E3161y/8qifKW77c QZDHL4oeT7PXIVrotLwJj2PqHACQCORBpH51+OVc1fV0uo9MgE1SUzb/YtilJKQ7XUHyCuIdLTR2 sBB2n+X7+IAfO+3Fti7rs19KY3GIs3bpkBiipL1Oav7kHL6kDSpgWEVyUCZoFmtrKCTTi6q4uKKj 1dqQduoYsTJIOa2GCeBmUZYldANKwJdx4YNIwB8UnIqorK5H4MAs4hFraD4UIOIjOAepqkQNr3fs nOQfkjUcRXmaMFQTSTGyKgq1PFY5MZUn1Wk79qbpZnZFaRDdp6zkAHchMh1pXFkmaHAKeg2YddNx eMa/jpj+SNiPhPrO7vE3V98XT40wFhkTSt6SeitI5vDcjXYR7KwRpwnOxsRTLdoTiCSvAkEDVyRt 1K8lB3aeQmvi4C8DaqyWwNy+KysGW+esPe052qerq/ZN4TCEyPkhSclgvFSlLchLVBcocogodT7O EO7dwdFnQv6vd6uN+E1gmXMy6y469osJ0slQKI3eSy6ff5y4oJ2sOvW+CVl9lE1nCukL01uMnmbY glzGearHGOajoIJQ26hGcrQgjdk4Qij4uxmDaklb9ORiB/u6CzyVlUNHiJeu+TkBpj7431tcyS9Z 59XD6PX5uqGnIL+PZ07cv5iDT5Pe92KaqbpbxlYmBOsOjWGvStsInk7djvBROMvnz2G6zHoSuzlm 0sbKHjJIAF/ptJT4Egay4MRSa9jqhHGClYjk80+ITadnQzQWyYWcBfWAK3M5m2S1egsB3ekCCimg U4eMYyhl2ji1g1OdOsqh3dtQNLgO2uhszJaMttnQrjqGAcs43TIZIFSo+OY7bKw4o3bpwn4favPP RNies/4GHuAkU3jpR2h5BueHSYLZMta7zqa0MhBjd6NNDDn0WmiuVdZc363G881Hjrf3qwcLx4+r ZixAlz3rL2Eilec8wRlKtSO4vMZ2/biPJEu8Fc/ePAjjHCzcdVDIyXLeuTfSJs4cR0yjqfI9juCV P8vMA00oYOoCocwhqrBAdq/lVXr59fsus3oVkX4Ga97ilapdguXvzR7uhayHxBaaaht74NILRAbT WQ2r6z/DH4cFkpbX8UU5TU/9sHfPprueZmr7K2vLu5TeSc9NcOqSEvh7SpfP6MEa6Yl/j/mnDYzT kaEvzt+4ZhWrWRCMGqqd9cj/mgsXgPAZKPETk48lvf+Qkgm8v2nN1PLc3+WbeIhuzXOBHdeSydSd YCLooWJGMRLZOpKgsKFlNOL/0p+cgFk5DmTp9v3ZcqfCHf5QunrVauh+E+SHDzhHtPSPya4Di1N/ pD62/e5JoFg3ugdzyxv13UcrahL1S5qP3zN+Oz+CPEMdj1+2G4Vibk+tegcPoM4BXPAyNPx6RVO0 hLdsqku4bNQbG1QiEqH2BuMnuHtm9IjsePZFX+njPgJupqN+mTQwLOP/cTzx+B/d3BxaWPEunrNr QESwQ3n7nd8E/P2uGN0eONm832lAOwq162JUtkACngBfufn/irPaVZVg2Uu7Kt6PB4yutPLhXb2K 4jwX3sPmxMdRbzTctKz51M2+COw/FyyGQKbzKbpw+8oDSafImn8Oq2R0BHnXLziWQkjIvrOQS0H3 fJFbrTognX4c2+2B/yPXcTgcw9Nqty+jZApbJaG/Sf9DNTydqESizsehfSt5shoSB8gxWLQZYPOe caLWIr9Blq1EMypokfgALk+6xeGlLhSbmFUVMC2oS3iRzvBR0BaFzPg0wL4y/srF6E4GvnzfF8tM 3w8A6Hcji06ufeF7duWek2NAhCcmI/LWzNnLUOd1b+pq/QoEwdViDa3Tq0wWQR59fyOUg0IZncFg d0NuqXT02Ur0lGETR9o1B7jn6Nq+Hb+SeHePyykIOkRLUFIgsaVXVjmyDPgHcpoA3UCb0MV5rIuq mFkqftirT9uhYRIGkpHG4htZW8t8LIbBlqHcLCc8NjpvO9WfzPxrw5I3ikkb5+w3EG9OwFyXAxq7 ddGDrUNTuPTSVdLoqivWqffu9Grs1sr9aJKHuvqcLkfUsO0meREBBxJCjivlXFFDtohpdVBpjuv6 vc8QiwrLYr8CGIxL4NnbnPWFfv6g6N0le0/qSu75fWyIVQcNKoh9RsAb0b8DqqGoVQaPxKCK7VKV s/9PV6JMvX0YTKoif4oPidriqfPLGq0WInMYf6utOSI8SlCFUX1zuuK2LX6+bmzQFDbuuZWYlVeb xgLx32dIRaxAGPn7Qa/PzrsNH8b50L8AUxt8tUW4g5OXw70TafYVVxCurq1AR2MmsnbrU/ItdEc/ wiEhffLQtWXqoYY0apU7qiMQvlKVr3gUNcoMNXH+ZIWZRpp/h6z+nTbrggj3R+qMk7nyO9a+UcB/ tm5PtK9GLXYE9sfG/98C8dmYucZKT50hf6o2Pp9IoflzSr/AhFLVD0KDronK3ZuW/ge75YP9xyFY LUMkSLldFmsaJEkY/IRmB7fYLedJnWbZyZ39ZNmh4RCnDMuqMKTHYgjW3EYGC36iV+OGGFzh4QLJ krKOjP8llOw5e8qM4+dILoVbCDG5yvENqomAS737JRZcE6AGvcsiydyDD+RHC30bx3XVSi1vBDGg Eyw0xZ4sC08QGqM/zc0R7qwxAsbR/E2y8nSFftIyo1EW7ieBNivALcuBCzAjKXt2cUg6MT2Ny7/Z D1Gl1iPBoV5Z7pwCKF6m9HgK7Z0VaDkvedlSqgswvBUDNpW4Gv00ivGNkp2pm80MYiwDtKpa5yma 7OKluiszd5msMS3iBIM4KARHKwBM6kumngWP1cCNCYNCtmiTWWFQDQyODuPu2ezmfXp8BPCIW9ZO QEnZZzgNZwGs3A7JQSCRJr5gR2A9v+DS5fEDMhGSL0rMPbSbVu7rGs/Uo3o4SPTyWnxc2o0XWPgG plaNccrWPr+OeCbv0tKW+Tn8ijRUAS7heTt644a9P4CtmuWZOflCPMKm/a5umwFoUXBtmuqkX5Z+ 86Fk1UckOIw5gD4QqjBbvvMLYHkNaOGeJoj87QXVsJUvWJjKK26L4K8fu5tfoTs8/0NbMOl5u35v UYS5D+UdhbS16x9SWeJhxWDT29nZAMBdemmcXslK5ZiqhHx5voICwZrG1cVpBx0fvqG6nLV/is4n iyTbNUD4G2MvUW0xTij+Sz25smofsmLQBSpfqDFscCsd+vN34ZAZBmAOFXGORa0UQCAZXFVdfY+k O/POOqYav+tWi0V7hlLETd59kBNW/N1XqYl7HxagX/zKbGaVmGaseNnj9AGlmN8dN9RHQAG3PB// MRbW1w8VSlw6NhQmDiqLhbpeAcoS/hj6QK8uBe27U9Hmi20jNXpQ6348rWOOr4guMtKR8L4xhlIL PvHWaC1uyKtEyE3v+AW7K6KIyb1Ljum9GP/OBbu4d8Za6zOFrKeJLG2Br/MubC/HZjyDWVuiPfnE FTr7NvtCJRLlz+DqtyOpWzkeIhQq6jVwmxVkpQBS6+SBxm7qePB84uRpQX2UNpx4Bi/w+OYhZLGR App7sx+KTzCEJ3wH4tScyNDwIjgYVFmXIaAUQf2itxS6rSj6K7SWnphoerdXjTns4oVYvXznuwQY 6CMlDR5JWZie2cgmEVWzhq3t/mEfjbw0PsFTv2uAd9ESujlmzBPVCPN2IqijfJKIJv/IjbXOWh4p nSICS6uTMz1rLg9D6bnxkabQl4mBxRk5vUk6XFw66uToSZFIIki8nG/NnlRFG4NOyBm6f0l+6YNX g9FdpddT6TqTxHICW+7GS71anW6rz2Oz3Iw3nI1oXHV5ZWXygPlIGRsY4IVEy4kvDdf3syimeaqr 80qPmgfoZIfQvBPcM+eQj6p8Rng4i076HmE84SpNkExYlTZAgGKO6MWigtfIjI9xR8S/un912b4D iliVkfQSgT/lnLOzHMkOaOiKIIttj+BDD0eDf7hNJ+fpcT8VK2ucGafqTdv730kwIBqCJl3iGM2J e7eBNvxNuvSiy92gPj4bm5xg7rOnzoYVILZqV3ksEtxTcfa8vpzCNXgCuTYU5mDTf5Iyooc4Q48d aJ31aixzJZYGe4M764lGdat/xjIIZKhqkonqhCRIQo74hh0svBnVGhyeIlOKgE63WvWZUB52MzCT n12kxzq65lCBdXiUM/RRoOUJpWmKu0DweXY0YuqmggFTMMtJf1vbBSgytSiWsh73r83BMh2EMQ04 uaIuxeVAsH0pPhFAWpyynoUeHUYAf6v6QV9jveoGuYaTk2N5TAxz52ymzWyna+eV83yXKf5Omt6Y 46gI5ImOYhfi+UIOlaEFYrYMrTCMv5a2YbMLk7Kt8Hg1FQXKUZr/8qAbj7RNznzcnTC+xttpJ83j hyd6npYLBJrrTcjnmType7BOwVPQUI6+Y3lHOQ5hSX0w5atzImS3VOEQmNviLlfa9LZRCVuRiYXQ Z7ZWbOXignlLo0JxZtqHtyMUGYdf9vXvKK7cbGPQzPMM2l8QLh7nwBPiGj/5lus6o2S1CDTZQq+r hCXvOnAp/9y/uEMuNlVfdX3HhTjhFRvswx/KdFdjBCVvJ+PLaqkRzPTjKJzyJ++TPeimlCg3Yj9j k5ayvSM4I1dxuw4FkwS5LFEEZQY5f6H14oxlEUPwJAQHNDSN1GQ32mabc4gl2R2+wU4WKwVDTs3m zLM7NDCPa8ozDjmtRc2JO5MpZXZd3BZJXXyHkuOc8IRjwrVi/1aBs30WA8ePNOxw1obhXq9ZGRIu 4vNo4UzxhVKzOJwwj7UN4NLLBn+U4uPpS94KSV0S/HmzA+lpQwVRg546hKEwPSVtSCpNGrdqw2N+ ZgWL4LZCeLb1JJVyFu1BfRFPwyWdMtiLEr0zC8IPi2WYvNbw9+XRplEB610T4xycgOv9tsCqfUKb 0gZcounqL33aDez3JMDMajKud1TbO+XnIPePLxKOCueX2sX7qUIOnxdVq+0SrhCdYCXmgcEcAKBx m+1vQIudqCXvLfHoLZsJoHsG1MOMgnbs2l6J9qQj9M/5wzjiXslnSxYKaCIDFRVmw65MjtfPs2tq DQyZUR8oNh1xRhTEFf1oG/9PNNsR5JgMpIvVyx9VeVLcCWm7H2CTi2onoaGzQ40W4381d5FdvEnm Y/PhlVaOj4uYyZt0AqIiUNC7NEL445Jh7sKLyWEWOmzT87Kke1kmG5aWsmNKq8pRocNVfnzfGJ1Q VgPBlceWuL6Iili/MDWRcHrRXGRDiUURaMJjXhoR5/aUaYrkfUOQqHKqA5EjmqfGwpIICZS4Vhsj 5Oj2HvG5YPAR6Qgbrd+d9cMa5ml4jLgY1j1PCHPHT3VEzIH50Z1fHLmN0kFfdO+5HoZnaeXme1kM EYPTI3WaViNsYur6Mjc6uOxLockOvicWsjORdv7h8t27AqUEETmkeZvOnmhxt+F4RkDkMI+XxuLX sbCIqYGkhq2/OtQyhtpFygztdvzj6wcickO3wu5fuVNfzdKiM+XysEr9k2qT+zu8574Y1M4t6UvT VzftBA3wxmbi92Opzw9BfhMiqsflr07jV5C0b/G4Y5a2Yza9M4O4OjXk3R6iAujvrQpoj/iwp3vS hG9749NwEltGw8Hs2cZ72k6qB9sHJ8UQT4AKryeN3akv3yp+wf6vl1NlUUet6KnFXnW4c+mdVgH9 34fpdDCcITKvpgjOyhKCHZLkJWvQNNYuAKC1X57LK/SLezkzZGp3/iDi6IQw6Y4IDdKneiAleTCK LMleK9eicbt41IgfnHlnDQTXomksKJrzubmYSiS4l5lGXvqP2aNn/hp+j7wa71z3XhoIgkHxn2Uq G8Sw08p6wyM2RDn/sLOuz7D5uDkKtTrDeKBULFRHreuXztc8j4K/c/L22qmL5wXUfOO777XRZFBB I95ZDmJy1ArmUqzx9vopmd496uhoIRTMgT9zIVC0R6zqry+2QPbxbikk5SvjYhuHLdslo06VxIcV +sjj6m2SJkY5Y1pSgicaCHhEambTJ1Qbb3hqWWMN1amAx4mvKzjn7uR1wK/jXpmWITpMh+cxzPu7 DgQf4/XmfrlMTnmlguaqsW3GmLK47Lq9bectls8Vgkdzxf4CadpK1gm41aalxEa7+aSiAzJ5Lfpo UvwwQGKt5n+GJvxlpmIVTsCIUWLNL44NEYF/iQElsGoTfHzcgTuVRyC14A1YZf8XJuTTMOY5oPz5 rNiMefv3evBw1I/QFZmLC9fJQDXRiOvHIFpjxoqWW1dSYx78ezwOy+P/97QA97YDLWh+Ia/fTsLv /2UT9vF1YIvw9TJNKlyv736R5HnnYV4she+5AiURVpL1CAfoKGL+/XLPgooxLiWiSC16eVA1F8Vm pywad4iwW0laPjVijBLWEplnPQspVGvl69Q7/7V/tld+94NYsNJseKrab9Uyw0IQf1Hpp7sPaWBJ iHqW7c+2VU1P8l5M2XdmY7FC9+8iZxllY8TafXFY9Oq37haso9BSoPNl4jpJElZGNoUFzrJo7gR7 IDJXysrs45hVtiF8rw2yaE/0XMUaeQiwaIskrE7DqLQBjKz4p8cVm5D+dFbNvWbabEGqbtDFeVIV HGhRTVcvLOcyXbzGVCZpFCf2bhDQjsDqI6XUOdIX4aSP1OXYCCOCX3CB3EiEjumYyb0lkeGd2F8f kwAzbPp/NbFz+9YgfkgStdTaRPGS6vXxqWfiarQomg5W0lOLplXyVStAUCrnnn/1ogEyQHMFefRc lizcZLSH18ZimUSO48d4kKaKlsU2RtRZGZc8/oeVzTNMeODCWIrLhlQSJ+m2zF4RyrbePX5R9FVN I02XQ2v3lAuVuncE3BSF6eqAajkeqXiOVRcL8vBOjDSfS65hVuURSGhpL6etV9tjgQUnkqxxyYdW CoCXSip8v/QwJiyKuGIdomAS4PDOY0Z9LSufwcUn4bicIcImH2Ai/lLHEgxZXZ/DxxbbepdfUVH7 s/wnlROgCD/6qyhMY3cqbOx35g++gNfQjdO8mzlYOjhjWgoiHuHTAuqbUYK/htruJ87zXAo1f9wF mx7rIdje2vrDgcrSyAGwFm9dtJa+qXgEh19Y8d2KjI9DOasdrGWeExLupNL807UkDeTx57lhngiQ h4q1zvlv/Kp1A6ivNiJI8OZq622sd9NP674IofcOZ0jpYJ3cnTQzESFEoOS7ODPI1MaNTRkqLJqA 4WUpBHyXpILjwbYchEY6zpxFyY5ms8OQ2OWtwabIZzpWCFViGDnfMLwQcegWYlZ2jz/z9hIddjnQ b859QGdor5451GMhqNVDtvaJGRYOG30OQOGB/oLJtU3KNmk/fnK2ln+gUVAuXg8FPYNwFoYdW89y 2TzKfkBivtmdDL3gV6R+rxtjk2F27RPmSCQcU/QZnA9BV5kinIV8nnZNw038ZYmQa2yrahiifmpO AeLqterowo/pT57rE0A6Ce4Glx58tiJEZIWZUmRXuyCM7qdjWsPdIn75KpmJjMZxKno1Mnf9sRpO iZ2UszxcGRj1/QLjYfYUlRbIo5DWVtEiEWqZQyhrXTGNDmkR7lD4Q7qzWr274Rr4Uwj2oHDuwnHi 32K9Tw6JLBZ9jq28gLgAu/QbDpmwoUXm/hmlu/jCl+o7UP/KWM7r4bZ5Jhi3/h/Gow44Kn88w4qq Zoc1rQyLIH/+FtZDLohyRH75Hnansnba+j3AtnQtYqOfQA5pKO7LrsAejxLFGU7DkibwUEvQqYVa eM+2anBXZpotHCI+2Xyw4iRwRUuaRY+xCUHNEK/KapM7HfAjk7ftQZrKynj5mqgtJBsrTfkFP8Um CWCAcuFMY6Ke5xkV5Re0Zp7MV2WO3vnn+AX+iOYeNXInP2HawWAo2AGKMMci+87BYFJ66rciWD5W eizpXyw/eHVdOxj0bwHsWmMP28dx3eG4Qn+S/hgfufF2YF7bERg1G5cj37pr05SePvzAWw40Unu2 w+6NEOGJThVThiABF5I7f7NzFwNXo0VWK8vvRyOND4yxewuZ9RoO1mjCkeZrXjpA2EMc6fOfMSAK mdf8bX/fITrcuDoAl1CzDw3sE46+Tc1I1hke/w6bc52DmfnQLwOuCQrG0+jWhqnX9b9T91s2EL0N 0r8pAVvWAHPaxdQIL8fTLoxdZA5cf12dvaUfLwf0DsNMczuCbSUjMA0PChzcxy/klLnZwRSaaPs/ FlvZMTh7Zc+TQs6Cj/HMh01xj5+D8zXZhhV3Ob/mSdl8I+5hfQznyN3MbmPGubVYP95YtAZe1TxD I65q1ha1sw+igaTHvDX0pjV+lWmOsG70qYTMv2xyS/XILTG+JvktboBvz0LcfKpzfJICLnkDa9a1 1w+JLJq5sIH9VQGhREBNYGEXqumG5GvxhaFZSSD9xcD09t7r+8r3V6VeyCzEBVhKVmBW3uRmIlAT cNXdcowMVV9aFh+8110XGjFlo42dKdairvmMy7lk2Pfc5YWEY2i276N7gc/emPwk6G7FJ7Kqbwk9 9LUouWZoCRx/KjfL6JHJYzC4y73pAkzWsL+Tur/iHozQt3QvnP50D4enhGOjVUkqbQr9UJ5vOSj/ UjPZhY3cTrv73/s16ACWULt0elQdSW3mUbeSO8VygE5vwN27l6rUw/8UZ9dpDLZVIi1uhC6dAt6k uSzR4BJ5WTATax6gDpKJ8hKa/C/81WE/lqGwTvrdb2dmBoD2QHWZRefqMGktBpHi25xO6VU3UG2b cfwLH5WdUH7yJ2BA8GASb6Vk7JM9m2C/cXZx540Rubv42XKwrBifP5Zw+D3dixxaenuWFycLKy22 hQx8Vtiho70Rx8c8ldEzvBd4vfVu51jIQcqfFdMvMv/bDUwRwaiHv7pmEWvqvbpCfV9p0ug6vd3d KnG+qmA7CQWzcaq/1VufWPfaSwfBH542O9D6ZBI1h7FlJYgrQ683AR7J0Q/7KOlAgOy5C5USaJB7 V7TqvE0mYBMQ90pQ6dOOdzJ3rTXMRTYGbhxCNq4ZNU96oKsjHwtVNxp+9rRuSLHfNchQCO/BMaWF 6mb0bTzyf+kBPqC7gGkqeUegGzPiTVgsPBEE8FDly1nPwodVlFF7VwKbM9wXMQ9+l3Av2vBOrT1J 6KJEiw9Rl6g6NN1GYQr2/3/nLIsWJL39bpXNUeUAu18ieMAMePlHlNSk/ZhD/IeNF4v4N52v23on pR5mYcnlT7F3T+Ib7MtvXyZqw7viofQbnP1a4IvSRwlardJ2R5tPzwzypd7+ATcYNxrv7tHdy2oW TZzZvtQqGfJNCuzYi+jIp8Qenn6uV/JpEE/0OGz0ZBock/fl6BRIFKfhQmzFTo6+RdHJcfIf2HVA 2dYkAVdcBQngT/MbZmpXKWEx6pcVSXskh249Q8WIv07szDh5uciFD4zMgG9+DtBPczQcyV6gSvp/ 1Okugu6LEQ0v1tgTSUQRFV4xs8nEa34jY5OECGtfieWV4WKabQ5gecQrh3Kl/k2O9VmLVCy4k/Nr KMzHlg8JPE/QSNjgUl+IcYzzYSiuV3kV0CiTm+WdfMl7kpHyYX8t63kiU2p2Gici2FOZAZDmfnzr 3sUFma98lOca5vKVOKWHTlcoWMea4hfUlhjeP7cSFr6GJ/Ey3KRNv9PymqH10VhqxXFNTWKiRk4o yRim7ujUxDn4w+luKz5fmWFKCHu5Z90INh5WpNGr+vDB2GpjT+8obbbQvwk4qFcXC32vwIwcTcYy R/r/+/o/trK2y6v1ZXDHsa/PZFnnhM3c1bf+JwX/nWFJlbLx6+pri87ICuCPAFVj3piReO4h4mwp qoNW7UkexyeCJXLSf+HH7LbJeG0gPX9rgsaqdG2qq0DRYnUfKC4ZU9BQjVsTr/dx2Z8Kv6b5ELTL T+Ax7a7A63nSaB3JdEWot7SIdBSfN03Gxsy5A6V61RpPNtvEd/cyxLS3sV09gYDPv2MywvKySErU 8QMyN+9JcBWj4qM02xXehzf7jHOGoY9xrhhCWI3s42cq14D1ViRPKx3RTk7GfuTl9ZAlk9YgC119 5xRcV08E8zBOeJqcbj7bhq9hhoOPKi8LrGI77ONhdrHzTMRSuM7f3s4zhZMTW6U9QJU4qyYhsqxs AZlvNn5BOAhdG39cYBkePp7uqqsw+ZCFy2/8IrkeXShPlvcsE5tHqMGQnaUGgvaPqpDIsIlqCrmQ yg3N4BUGKECuluVPq+4C2INcRXp6kyYHwOYFx9oZjXkg+Z2UBMTVNyvEBIgNlDdDawXKYykMUxGh KofXuOg1AEPowzsXVkv/DiMZaBQkRBGNq7r0pIShKd05k0AsE6uvLe3HPUtDFwQPMH92LnSdRvaT N5bO0IG9FRLAPg6nOkh4Ux1RWUS+e/1DOTFlKgMxmKXrzGKsWQt0iaFx8t+gbbRF3wl7gI37aSI0 a6conuYbOP46zWiClp+0rgjsTuZNYvIRIX4naQa+EM8TdQIS+iqhDvbfeYVVt+DAvWvIQaF12YhE bHPgKhaxhdQEPH9DwO4BBJzjYm0FyTMQ1zfYiqG9GK3Am/rpDXJOf7S0xLHmH8f8aom23bm6JRBD pjeYnHNwLRRwGbqINhtlMD8GSODfmn/MwJgjmMsTtN2vNuLqvpzl1sT0VZDL6EP2x4x+yjIfSqb6 ESTWM6XHooyQGquXTuWQ60KljQqsPie6BhgjZlSEhNXZmkCudSrP/dbeM5+0gVNJ19B7aMPjTlWM cuFU6meImhx/cdFVUTauBhvy6sF2x1d8Emwx2nVbOjqJ2oWeuc977Ef/LwKBKmCoJpxdGOe88crS DnLwjCLCbi6S5v14QWjhQ6n2Vs835cDDpT2ehLnC7rQtDRyMOuEfZOyRZDu1ZHSAKrCc5y1rZd7B Ey8dqAMdixvjlVbZKttVITGN3OB1stqdaMywUNZ82liy+lmiPnlm3QqmCUmHy6s1ouslLOpBDrHG KIzdNfPBVVWT7C7laNQJPKwhIzBxMVSXPctFIClPSTS/8Dz5NAkTYFf9Eaux+GblvQhlOeC+WG/z L4z0/GJ2GfRYTbUnDft4UdOm9K5KQEL7w8q4K0wVknUp+vepqtoTunIy/rWZBySQnvso4ymRPurL jEO2lM5IcFA4hSvhW80cJKt/p6yiE2Fr8vGVxGvvjk3Hr4gOv92PFxHj17Jguvs1hcgdb9r09KCy J2ZaAmhYBylUZxRb2otgEyEimXm4Gs4szZBICmgxKFdrKHTfOXOcKyq5fez7dlv5d95cpd6eIwk4 Ooxx2OqsdPcuNerZkV7qWJATq/TpIAfQEedCKNaNWJuNFzm8IgsI0H6Rah5bR9+VfDGPF8KtwFOU /F0r5D5v7UuYrSP650hyT2P9vXSEygNxIr03mhKmgvpjIOKDxwgwcocvCh5AWUgiBxKS/qDFsJjH xVvxFSdN3hppDO3mad9pAWMJaegCOL6fF7utVKTZZuExWC/SH+d7eaXdGAXxE2guNlC8oF3+M1gi A9rQZHBz/WS03GfafDf0lFuOH3oylaoWbq9oNgJC7qzo5jXLD7Sx/g5G3FEwFIcJP725RfKlBiJZ BO0Wu0WU9KNsZgIb2HayMer/I75fbpP927qRzbnEzsBMy4a0qqslGGteavWCZ60IjX16o5rXXQ+c 3PNz/WVPnYJD3Si2R02IWSj1bTKrQu0Y6s1DGrGjVEP737V3xPUzIEmakWXMziH/jTI1m3ZBPPmk 6J4P7ZNyefezYcV/hy+/D3BNONrkMgu2gC+UOvfLvsPnA5etfijDj3hQ6YzWYE4RzdCV4gXXkhyo AOeYsstiJc6yfdGjSfxqEPkYrk1TgitvivQQ1Hot5ovK++h3bICIFaVV5QzHk7WrTenW1KAZeOF+ F1t6aY6I48o6psiDldfT97QZD2GvjpV8bFhXLjMOxQoTm04ZpClbPjTNKFuF/qsVb32lAQiQ5asO 4NyXHCYBXWZpoaNo8SiQ63QPNDvmv5xpnpm0ruHwuPEk1jA17cXP0tl7jD/iVSQslaQD1Ccgd3d/ 9yTL2em5R5Tijd3Rhj1piQOLNRXS97xcFx7Da4vN8RwKJ7ujbsOW9LoeA18BRWxMqMewi5tlqXJx qUAgMj6q5ERkStDpMblI4KMict8JIaXyUDF+zI2dhyrjOj1wS50hrHVZ3Ns3j08ClncK/xCFLfOe faFlaSpg8XqaymQdonLVQmp/ucPg1BKbdU2ruN0uy2qyU2hHWl7B3IfPqTALwPDa4CK9BY4OEZOh cEZD/ZVdCDGls0tmqYwg7RpmkA2PGLixABWZnjMZsGC5PH4UhLvkJR8FqU/8fSkl3ZFArJbN3mbU jcAsjg4sbbkDBLJlRft0Wuj1fJSa8b/BQ+5xYiEsQHWZeZpLsgfQdwfHH7YUnFduRQAfqbPmiGBw oUok2KtQRA1PlV+f3m4Pkizh5kXNW7rQGHjtal5gu3POzogG9eToi42w0oa4dOgqwQckPBO+dazS x1HwrjZJsL0tHFfk5NRIcVFbhGDDbLoANa7RQgXK3cC6Kz0AwAAvLJvH0i5ln9P3WFuTemPKjUIi Mk+0r+9ffDfA/M7MamdncYtNdNxjX2fgscrJkFwaBu4HqgR4zrjgrj27aONO/bDHkHrykonJQV1M EqyQwvQf0wCliEryLie3O714DKkKYhXsVj0dmfxDDrQ2L200KXMW21/ccDsDUJntGQVGxS3dG05S 4x682lP5NpJdEr79sWRzmx3rpiSclmHS8/qO/IjEkBsN6P9B2fl8h/IWjaKhQ2zjSGVpFoJUceal 1QwT8uFxC4c7g2Ioe3d6273aQQi7Kphe9GThKC29cNtmdJnBXVPrse3eeFV06dO7yxNjcU0sdJ0F Rh3KtXyJ+Iu3lHOEsQF7vyVnx4Pkg7PHA20taXcM3jEKnzANZK3Ujf0JhQzAFM4N9VHq0GqqCS/f oI1AyxJjEqcd5jdBq2pjqx18S71/VOwQ1nHZ/xACqcPme+XoafgRGVqZkbeMmvJKs8HoDTf8vjiH 4XL/MZlvGyw4F30cv8VJDlpBaBCRcIqkrCmUSeyft5TiLMeZwkpeg9AvorYcmC3koXJCUf7W3kFB 8Hwak7ZDv71v3H+E0LeLedHH+9Shg3SpgPDyJA3HgxKMTUcZBe2gp/pO8pmQlvnBwsY4wi6RdfgZ Y7x+9uykqxvKUrH1jQUIG5gl3C56VFKSgJKX/SxpmeAJZFSViMXWyS2f+1v+tqYypnmQDrs6K+KB ky9Q+0Y3U+t3a91W1hjJZS5bd6FYG+CdS6m4JfmhyG5sVCMHV4tSM/CLUC8sHK9V69ImzqjBVd1c Qlrob5leoPXYvS9WFHqNYYn51Ijy1J3H4xAJ1xAu3m3zi0h6ITnI8ZU1jMeqsDKaYTA0RzOe4S0q aup8MfGlWMJCUnH0JBex0Xyqw1t3MMV9/Nm9Y5GGFNlE3yXDAA+6UvX4ujB+Oj1eD9A8aJ+tqYxi +LYlLDLREJPGmaoCoYpUhEqPFgtjGsDoJ+U/7fxB5iIBvUlihnV2Kh0+YJ2zMmlS2tWMrKLh2A7Q IUNMAZA0t1FzrV2RPFv1hpBLbFbJXd+Jus2rmwCBjGLmuTiRzzxlHxmoq9Y5UKZ8R61EBHmtg9hs h+RaagjjNXaRzSi1vVu+nzlLmqfpWYhnJ61EzxVeg6JZYLC5WByHPK+2zUwRtMc8KLMml50u1kB+ k+fw2f4AzwHPSS9UhoW8+93PV6Zg0ayIGA1qCt+M4VJwhCtH7aLVRFm9K3/uHCOyFxHQeLzrSilP r8/H8/7J1Iqu2cE0rfF8BtTGMoZLvhLf3ePrxanHjFWb3BXVkAGbymsuinODRC2xoyn/2ajSyVlR tLkQxnlRl2Kwenwkh9+XPguRmj1P6u4kEKrSPTJSsN+Yqonfpi9/aulgJWasisZWwOPNZ3BfTEsI gM5cyer/YiEzf88PSw2/5ZgIZQKJtOHuVTIPHMqhBGNAS9eTgvPf9O2rnH+Gypo7AMKb8sjUERON Srs/44YAlix3ZdBh7cfSfVkxxM9uBL02lL9C5QI8OBBQ3ahcpUnZsKIx1nBp/wIkGVbPIpv61owG bmePdvuwr+zMlDD6apxGdBvKNxe5xdt251UzRY2peu94OwfqZTFHdGzP4sJRiOsGaLPHkffa7cqH zqnrd0mQ9O4PcmAmAdz+kGVz5X4tBOwOAZ8j/5wQS0f6NQsIk7sqC4d7fyJGxz9FEHmUFq9N9Nw6 9rgtZrDUS8nDludolyu61FicjtVdyW8ur/f8EXXcZK0Kh1JE9Uh/+NnsqLeaALgSIhaW8db3uMbt QsFOwud/D7PFTiM+juA4y+2bpR+gsk5Am0dZ+zsayNeqBllHeNc0zyvQB49ig4djk5uiSdhKvwHH K1+zVrIM3w4N/bYtvBLOmqi6vuvLaCT8yF3yeu5r4GrjhURxGGj7AkT7uXF1kL5QqUCTvWIP8Yz5 OYsJaU1NNuFU1gK8kaIlsrOmYJijWvcgCxinuxSwfg1Zw3U3VI5HzBCgEK+Iey1T58BrPvTs9lbj hSVF9Ts5CYSTgpvT5M75OmKyrPTwFMZx15qevr60w5evWzYBCZCUfuxhf2lFkSowLvm2j20fcBYI 1mhgDEvXvwRryVca4LAVSlG2TblPbJ+Y9QxKpFMoUfRFW5Zz8sb8YkSWjNDaT9Bc300rQMPGOXMS d4t2lklBXawwm2ryh0FlDJFU6WdgWLJTE57PwFHqgIK2EySUHLdFYkwPvf4VIa2KH0ODdVIb/geN foQd7tVYqenyfpL8g13bGtN3J9d+4mffl6tMWzAWoIc6Z+w+wChGpzg9NYEAF+PVHuvoQ8RtH8le meIVxTWs4jYl5A4ueiRe/oD3tu9BOLeRrFgfwUpcboIrFeMZvy1QSHruItHHfeJK2/0aWfpIzVrB Q/dat0aaXYlW9RTE9nm23tPdYPzb4U3ji9B+6shzTcoXN7/RbSdFat27sqJyC1g++vNVBzd9acQx nqeHMOPvSBNE7nLzDelSpvxXjArjBqGp3f9Q4OvlJ/s9kU/WnmpVT+Xjntmv/EYJo4AJcjhtQNmX w0jj30ErTG15CYA96ZMP7zmowlOEFIvVQpu3OT60yShmqd9cTokNHVZ1vKDYhBLnBrKGgCd7H8RO 70UwoP8I/zcPRUWkBr2yCWyxtyFD68cT0rYe6Fxwkm67e/aAcN6IamtuYjq4DPORjiqfD1JPFGUP EwccP0ruiwDSKEFaj/SlZtP0iV5dFPnk5ANT9U2EZ4raaIydK37ywFgr/X7n9juLaLixM27PFwNO pEOsh3h0MmgFXW35hwaLv4gmB3pTxypnuxJT2xOU6mZBZ6ep6UebTCqZsl5IokNMCgQUnk1iXsLn mhlzmOGycaOBhiGc7LzAXjfF1Nwlxrwy7hxzykKhzGaqgk3jGTWYW+bargcEKz9QUTI+W4mSKi2a S0ymFEetlhe0cq4dpCON7bjGVFhgbpvxZw2J4Dx8u1OEd+7dp3BoYBJhrH5d480dHuotPP6sJ43p ENZ8ilnw7HQnqbvFDe/EJe7gZ9NLyLSwmenvGCn3gZudokCApvB91Kqk+wXaRDzFCx2/z6Fae/Q/ AbUs4heic0rUpPOF4tlPZrWvN/tA4g3EntNUUDQqFLpUnw8nFhkH+0mSim1ZG+baPjqLXd/Rxn1B hYc/bj2j77j31G9QDvPkyP90FPQ3iND92JIUJ1CA6Jou29Fxa+r0mO3fet1RE44e+yRZuA2cMtxT i8IorWoa3e9/4KTxbcTazQWHsFwuUT3CHuEGEfKj6wRx34C5CzbeUUuIwGPNFQCpCriRmRSPp7Au T0N/qVOJoC2dzqRrs1Y/mZsWjgQG2AI0AkZgj+OP2fpf3mvo+5TYs9toM/SXfwqql7JqxLVP4UF+ 4IYap5a55qxNyHiR/VjnGDNEKfVWlddyKvu15lpJvtppKu6ZCzqIL8owyvjIVB0jdX2xP6bRl7Wl gOSc7/9CxW/uDStvNn62AWWmU7qNqmCp3qvgCj27wDaFv+SXmNJKHT9xFBKau0F0m6jcCr0SK2np TM/laMShTWzzT/Eca/xpjkCWHky6HYwGP/PYHGDX9MQ4r39bbM2f8y1NgkL3kPBAwavlBJ9xLLec lEtmE2LXbR0qlXm4B2lh4rhSYk6EnVpBNLrgE0TsL0Awzlesm0X3Kahe0R3qvakMPCpwu0l+kuJ+ C0wciPvgVdTFvm7duLdcISObGHdybIP+uI0QEoBo374GF6ZRsdWgfRCq0CeW2NN1BGqzRdVOy+TB 8wn8egqc5JXInOAOsSXmp4wN7VZgcr+Q4cZId/XzE3pOqQqvYOWY/vUKBvcrvrdq9rTlGoYeHeAj 4wsDmUIpbHVIJ2lW3zbiUXnIqyM9O1MmFcTeRsPeRy4CSVOfamkj9mW1Tsz8IiA3tWQvlPcYCkvu b5OD1HyQ/KesfVDnp9JIE2c4zbjbN8hISeZ4V5DSf0yPxPn/TWTgSVPPIumud2BMonrI82m7Sob4 IfnFjbsfb9UK0xrlPqpHTgKh/g5Zh5a32TAHc4QxxzwJBbXXI9GJ1StNVKauRlSIGHSqBlhmLax3 3hCQ6PyLagEnOXo//EXs8ULMDILtzxeCSUpP0WwxgnIhJrRISlEj7p2gRBR9jFX9VWXUrmmZbVPy vedkUgcBEiUrA/Ulylik2ISUET5xZnjT2vflmoJBQHnfEUm/gEgJbt39AYnQXiykAxCvm2YVSdmg b3KFaElA9O/pe1gL+lqoGVtbQ8uqWoYiFtRs2JJNHvjAId+/4JOlCjyQcYTHV+I95GuMvTSSrGEf ygzNMU3SrLNIJruE83brmmXHMPRMmUVtqh8wUlSdJbjW29vyZTX6Ew7ZdYyRasLgn/55RMySu6eK yRlrZzwV6LrL/sVCvfh0ARDtBK6y8+SsWUGPDB4Ko8cgwtH2Bt0AS//BqgaTVpAJn2xnsw2+UZbn +bnW42cT5FsZ3ds5RdWrzhsakP7DIWB5fbYQRsd0Ze+xLA11zlOHrxd7phxDITquggqoSYQ9vpaz 7bTeAV6wfl+czDlFCJXShezCu6WTC0jcuLWkRL1cPb3Sb8N3cQ681SirW51ZsA/eYpeJQk0X7tuL zDMROeT50a2lWhqSHKzGWHff0SSqCG5Hh20jGTuW0bNHgm6/IAUmtAhcsPkiEEP3mLuhSOFLUSDs A+IZHeu/JY4KRn61I7dO2+Doj2m8GF0Pob9X4+3qsaWOJ3+ulQyI5j06/OOB7TObgbV6nMc5V7b7 r/GBce1snANZ9w1OsI62/LaaX+nhgA1/ADBF4kxIB2SV2MfLGF9F4UgrY7KAFZi9htNr/VlhIC5l WTr72BQDeuEY3XEBCRdGlI+h1DgGkLhvwZVvKzeh9BYz81ySmIrz0PpOaj7i0ApXdo7Oa85B1LUE gLPsNvGBnL96s89NlDand+KnNnE6EgpHQ5GZA4yNt+azBKkcinkbd3vAYAYANw5K528pG5/yijom HkUynXHxl86mb9iLwjKmux3IKYmuigJ6hSq3lQJz8/a14DHxsREwe/bOt+DWmpXAnCTDY2f9IlCb 5zvsnIEamQPfZeA6z10fjx+hTtpuWeY8OsOpBjBj5SS7+KMY3Mp/NIZv/WzCP80h+lthnzzVzDkK UdrHRQ994OpBgRLj35wTbbXrCOLkpP6DvYqdjd7m8WzdRX/OXHRA5mVVTKIlQ849eCihYYg+4VpM 2nIFN0qbjobkhFaS7bwaLXt3IqF08VC0TTSgBocbGVg8+Sef3Gy/9XSw6uWODHeNx0E/LW2Tx6B5 Tu9kEq7BRr+ACGNFbZsDIzCmAH6Oaou53k4Fqz5CoO0JfnxaXoE1BQXwnwwS135H6XgNA9bB9rCg 9fZFjoDtQr2fgk8T/x+RflnfqsaXgN40TZmFDqs3/3f0W2cqoHTy8WlXBA4o6U5k+1RkFrUGUev0 dc6dSmvL45Wx9tVVZYok/9QWCv+vpSOVSIDUlEaFwYVezax+andkVn9WqNM8nIbHfcYorMKQbVrd O7RBkGNHdd6lFEzTw2KZuMoDQrvAWgLaXKzCUggo4SvX+0ZhyQYfk7P3khXFzSP0mUkPe1PLxlzJ XRoueeOcIyNO+TYhXwbXDxB+/6x5qOBaMnS8cHb8Ik5iDHoP9LBRcDYMXv00o3wA27+Xm+iYMB0s VHf0G9vcWjnvEB/lNwQhTluUJKFfK360hBHgPaV7/BsGQ2hOdRlJtNzES0B/V6JjlWVo/ojIyjMM pcAuZqJasqZRAbyf5rDWY+JAPadpKbMaEQEF9ynFKXpKQkGo/N7UCfcYmLtl4LdMx+fRDVPL17RO +lbmIFyA5hGAAHWj3sq8am+nGBFOanJsyJ8KUxxo2eNTY0C4RUpS4vNplOZs60MkYp9gyeyiIX7K A/b/YiuQiLScZnVZ+IREj5KNNZanRW3ZbtNH0I3dFf9C1Bs6ZeQXhzc6aTV73YsEctj+FRc/VwOp a5F0yyplNVwQr4URICJ4VXhiy9uaS8VY4xj3sgG9IjJUsFIkYB4cPKuX6yxto24TIvVIxPitB5oL B3z3PJvcXal19QrR4tUPgMEW9b53L5LJoJVc+3YU3wSnmv/8sA7EUyW/AxOYXuY5O/dZbC12614N UdbktQPW5plc9qtXjrWJqTl1HusbQowVOg+hEDMGECH7XlxB8ZZHkqe+CVIVo1Yqgwr6CQyPVogs /+pWwTlglLnw0jCNoScraKSVIWt/KC5cXJbJs+9zxUrQ8qKnQqaQqjPJHE5H6nBIRjRzvSy3L9F4 T+bSk8M7CNPTlHW/ysI5euSQg6gtmjWHz9e6xfqIFtDmYVs2kytXAe7Loku6fKIrEYxeCSZYYR/N sxyOeie7JCI0FaO4+ONuVQetNEHkZYIMtc8IFPj/tjyGaS99oTlY15BOhh578/a849NkMHnZ1Q5i 48Um4i6EoDm+EjwwzUGjLV7sIKnnGPjwRsSqo54u9voT2dGeb5+i1h4Ft8xwDma3XkFeBEpD4L5o mYuI28R4KW0gltSyIvBBSOpaEnFyrHf0AqwkhIcjOQ2fwkOChFfNdyU5LL96D2jBgIwoaNwJjXCf m7XCnSJNz2WxTdvaLUpTjvA8Q24WjBO6mVtjM3jCkIRPeMlrI/ey6mhG+irKTdfPROaXt+8zUEkQ 0SIZgWBU/nDh6zfKu7HaAhFu+ZAN2ssTiJpt3dWtFvkvauFhEEU74J36UvSIq+60ghOXBqqvjgze gdari5bZYX+cHmMR5u9avgVCelpAWGbNvoXeDXXwgXzLXEZjxn2MH0t7ZOqz6iLahzRXihZRzXKs 2RmBLGZ5MhOZjqEeZ38EzpzBHrpWIZQzdQvbdnLpSybCi4V0c50ZA5U9cjK+QSf0DKSsEpwepg7g ZbOzuVc1S7VqI1RonGhCzDO5od9BvV7XX03m5pOAR1ZbfVwinYJtLh+DxgXFl+1ep590zNdFdXFp s3fd/M9kyBeuPOP1Xs3wU27LhS63n3pekl+YbsiIDwPwb5oEyJU6XCotNKpTUkC4y/W2CP4qF3S3 QFNhKyS7EyQVU2m79Y2FW8IioNH12b3LTVQrflO7f74VByn+HdyCES4/pIJEB8Kb26MKZ0qZ96dV 0rNOa1FeG2ov2FzdzSjJNpfD5tlbLzd1vX2SNcUcpnWYgmtAQdK/m/izhjb4lf6JCXD4a0kymVZF Sn5xrYitLUSlR/9dLUpMq/ngHMMJMm1OYbHNoh9SwALMfir2wqrBpG9OwpOKCAIo+XSASayhMtRs 0MZMQTXVPEKWx3fYwpqAw3AeCGn1YZRuLzbcANwWymG4V5qThlEWg05iCW0aSawXiHbR+SGanIve wfcEkrgqQCGFdM4C5JfqB3gtm7hR2K8gFqZNpBbA5ya/QfEZeAdZgwVEVcQ2UO3EbEXIThKljrb4 L82y1m3zs0o3o/rTDV4LZPaRUCz4RixJmq/uRj79MP6w0gWYd5IXQbSa1XYL4mOSa4gNsRwapa6X BFNBCVbMAgPSdaprofbTh6U0kuXZ8yBod+4CRzNrRYbnPIqYH8I2+n5JHOaKhUq3t3CUjQ62TrkT E5tBzYg7JK09wsihjicjQcrh13wBa+JcH6XPPUzb9nHJvOdGCe0BLPcZcXaeVMdHeXAyH2g8MUQC NkKYEav1uckYOs3zAKiQxxGdFNFFX4DUR5xFLEFH6QoPosA9D8p68YWrn/rlDLQXzBu9zSIw4Z2C sqIyJ+ayR6hOLQFZDBFmFxP5BGXQR1GkN2chOcpIVf4b2jXyzzuKFEITKiQAUvlA3IU+nkSblmIg YhEcOv0RHBHl6is2paU9QkgYJABwbCzlMO8wilYMC7fLu4CwseJjcviRY/1IXi+6LodojFK4qU21 PpJzQPPukJye3KXyeHyhnENbtK7j0fdXSNdYJfB7ZWIfNhT3MpFvx6qa8d8sIPsO5QzjvGcsQyeF iBw9iMOLC3gfhTyOk1g1cBile98AfU6PSRsnh9HPWBGEaSZ/ryaJOSB+ODUaE9jbJAcFHVMw8kXt nQ6S6WcpNibk/UU9q7Colny3dOnqulKmwNcy2LND/flZAtZfx0FymBOw/gizdd9YgtnPYbjr3qRR eU988TZbvsWtuto+0ERVrgBvGqVVTb3cnmYbXmfxhUQFAmR1ut5jv4HJlhbWeRl5R2yEzU1iktj6 ItBAWdG5JYRgsU7FJsh+L+hiAC31u13H+uAOunkAifyuhdYKQ/SZNJsCrpOCGJL3ikk+z6EriqGi cRxUFIyZqmHtfzD63gQXuykGhYprHp4CM1MUQ0V+dAisFOnQcqFt0Ny7mmLfQYRsPX9f+bzfqfmx jn6MBs/3RAHGiKEagIn2vF6/c2rzfny5pVVTdPYPL0Ybsjsfmdn/BuzT+//uz3cAICbJwf1aQddh MRpVoS1eCGW83siMlqu7PmrSyyT68BeIPlHHl7NGPN8gAi2g0STiZ95IAVzkAsNQrGZy5VGDbyTs wsunyNHqMacv1EDr+8+ioVs4yE+aMvJSmNc/VKY+GCr7O0VSAMblTUPycBWqodCagfb83GQ2P7yy s4WXMtK6vf0v9NXv6yQHn8cWydAlCEzUAFVAZ8F2X+8N5vdw4AOHZ9NyvBbe6LZ+8wNnGifEDf5J /Zrc7uH21Zd7tGHQhnWNaHl/wb7HVyZjrwadfZoP0PC2OL6E+5HQJXSm2R/4tErRUrjwsaMbdowq R4StaV2e+yq7P2ZSb0BeFP8i0j0RmtGX33z1fIvMdXxeZ5zdQZ3CkIASj1n2kSh/FKaIwvXH7hU7 J/mQm2KJvVPV+sErhwNcBN6Np8X2prEZaPgKDFNr7EgppH6Q1h1fu8km0JIFJTnttZbjyTAIvYAw mchBfCvGbuX3JixCu9IiSdvXew5EdpgshFoT1P+KWSDZo3Uqhw8Lv0D7CZyV0e5Gyc+QlT9lh+jL 4eA6dF/RTLuZJ5NuYH2c4h5UR4Y/s2poONJjmtQFcYcYAlC1t0p9LF4gvH0XwQpEvD6dIHHQkz8+ u2qw+TCNHObvGv+JN8mIItsjuExFCud2IgQVgT6Bi5OKUUhCg4UqYvMWj9Q+MFOa37wmAo6727hq 8OotC1s1f2yqbqi9hhWtPI1LXd/N/gag8fJb34GI7uziRo+KGz1iPnYRjW0nnuee1PL+LTWxwFP9 apja5rxyt7xmeDdUBMq8oT52uJyHntRbTQsD/JQiYiPu4rdfBjjDtFKFO0kv40ZUM0cJg83ckrqi Aj9WeT6cNPPJbqA/+vVO+T0lg25mv6uXEHNWUtuE8/7H2Gb5ZxtnDwqgFeNvCCBPNXTJ3mo1zs4T uubZaczv9Nn73MCrQeVl7klHvNGYYuIaQIks1m0na5pHw32/QEk12A/uaiggn2RVGZy4YvsvQ281 ZEL2zKHi557pgbcbv0Tehx9VOO/4B0l2VdVjzZbnAKNrupRBnm8OhBlor3wQhRA9wFBqZmRIHcxp dIJ92wxHl4af63cqqYuGhNJ2Yj9dQg7yVZTh2e8fS1lyIzgAlPDk4Qxwq7h0RVjY/zLkVVHN0h/U +x3qFX0c4c5GznHw1MRBUKzlLB9GZdXtrl+4p4E5zf1nWXafTNR5Em8nxzAPO7djCdHV1fgnqY+o WuFDl2ZjOyJ80b+se0QJ01XmUGX29KRzs6vIROOhL0iXPNgB5Fpsv/LSTX36k+bq7rlK5JqVku1x mpSb69YJKO1wZLA6KdIQ5G9VQkhHiAmJvOSJWyo7gTgtYYzNHF+6uRcO0uU6FL91Tr4dR+1kWcLY +z45I4Faoj/2oxy42alCNeONHAdP4vkObqJbpZhQa320DYXq72IeKeqduutR2CkabciK4lgBzQay SAJHL1aSDX3dIz6GD4DbGYiD3Sr03nfMeEtB1kU5ALHTvv52A0hJvcuXcPIhIMMrduzCwlEro1+L 5FeUpyUBt8l/jeSq60sWysXfdBQgtEixozC/RWWHM2eOu7C1DoXGwf1T8a1iDAXzhbMxvS3HJW2t 24CzyURMjNY8rt8bA0hT0uIP+Fz4bHlC3gBlQl+wKKWmXFfrR9dzS+uN6g92CQjI+0I1X4LH3KPO wp11ERtIyby54U1lN9A/W3UkMIOMNfgRTosxQKfZy/jPDTDkl/gax2tcFh0TblgFej/yohgWwWGV ZBBrbYJ9bd0PshLjV9qC1dIaGZDR5YbDr6IedgZVs5slIm5Q9ZnniMEo9sYRlcSC/V1LkoZw+38o /zI/CReNrSr4iTjqI6mJehvArLxidjG7ypkaDVDU9WvyB9uFxYnmYcq8RtyHFBBJ/aI4AUrQFBmk fkt+D2PUtPb/57w4pLTs108pJaPXR7t7v0jOiJB94A3T+e3IjPeOq9t3qdkBm4VkByXfkj1ieyy+ x1kZwO+KSAf4kzB4aX5z8wPl+I8EnJGzW+iLa3+J9cIMA9/NvVzsLSwZQ2DWC+6IuKRf2/RI3wzx sZvSHucatflInVeUvh23z2cKc5jUn9tj3fdzmVxOPE8JkUi4dTPgA0o6njgrfDpcbG5FB3U3lgFI YlsMCf4b/7uvwIw6fLqHpLhMR5i+8RUpA6cwXPifus3H5q8jLyjU8Ubq3jJQO/L0k32Rm8uMt9js 4dZTxGWk//0I4pSeArm9UxQzvW8KD6sWUmYAz6hJGCRsVyKdhJSTdw9doVI0sWYWtidyY+uvRt8N LtXZ/Kof3LXpCK1o8kC6/F6TpW5xhNqX3kwGGddlY8ONQRfwv0XUF4qvB8chPc/spIqVAKLwqsU4 CqahAJyi1hUmyhk7tTH5jfvAd0h7l54HeR5OgdUtpwbXmHI5HfZKeDTK5xXCImjT59/4bp7sHZD3 ZdntyBit2a/oGQzvpvEgc6koNS/hzaVE7MFH3UabhU24WE1/FwyTYW4nSx5tPkS9nzhpmimfWBqe MO/mF0/AkQq76oqsTX/zR9ibMvXKDc8Yy8OkMHhrWohQbYhmechkjpv5UZ2eJL0LAC6Y+rN94fpK vhnCKvJb122Zs3euJ37nQwJNXrDPEOoHTn92xyc2p+L+v+hmCAwMePhIJgcUMxCpo10F54sKwQt5 10fqSOI8+xg/1a0QZ4rvF3HVpcGAspON8AabBfoQqAU3djmgdRT0ysxMW73q41ROilRgJSZpESxY CIbBfEw1zS7fP+VbnnyUicEm6EeTqFBGQq0fnz8AtBf+XiDY70Tk+lSCb60zg3lF0L6GA61hn1AS Mo9fE051rmfKPjOoakD8GgDQqLxGep0aovKLRabvd068HOgecYkRaZU17mKMRKLc1pJYciFeZ3zj qH40gnUr6WKY3AX1Jn+Kh0QLHmV+A/ONh+yPBUbxgiUW720X/xwFpCkjaxJCbxidLeB97zpmiVeZ GqFRzo3o8bdyU9pK+SOMVoKPJ9eVEjTiQ1Tmwlm1ryB0QdEX9RgmGwZMx1j+UC483l2F+fWosJkP i9G5Aed1NMKLH2top/dMwOmsBBA0Lkz4NQ/dk4R6SCDpCNFYFQ3lNs4ahSJ1lx7QOyIzjacGgfHx nkp9oq276R978GcHmNuXVzkSR7tJJbE/RdRhr+4V4ZEzAgNMorsLJfwMykFqlrfrlzLPlFRChR5i wpK6tNFXrp/twR7/HYv2qmTNruFVXdGjB6qsoMe2naptmj2nyRTteMJMvI5lkNwLiZnSoFT515MN sbYDFM2tf0RiQLyEW2XMrmEiVs8zrn7SZRTVuhxMnKD20X11o5c0/PSpzh2qLSoyUNmfzC5PZRPN 6aNzgLcIJwScO0nrv0OLjNxwV+wazZRsyxFISyRERg8bWAwWozQ0z1Pr3vvJStmt9SglzfTFvsIR HQxDE9LX4NvIGeMrxxO8/3xKGXcBMhlXPyGJaihqdkNdjs6YJDWwXUUlSqgxtPAzqelyQOQkbN9a /Uh2/PXERnp9EHqyVmwFpCse4zWH7PjJ0w8+915QAxxPSCh2hLmBWbP7D97fFpyRtl81oAWgnEfV jjmvEARSuFn5Z/Y5340cdEejQqfsTrRk5StIJC8zFTbW9XnLZVbWzAItUS4ZfW5AN89pjQ5YhWVC l4fJ33dajhalhTgtvYgOd5SngAg0OMw3RfhjvyjyEvPUWq8VJluWiQNWyqG0iNcqmDp8/4kH2QVc n2EtYmAaiLwmCwHX4p2q7A+XowYkAUM2vEI2XKobNNSiWskg35C5aolSMyPKOe5oWtHJTYjjJGAf q3UxN9Jxx+YkzvTlTgRDaJTkv1EXDxivpiDVjwCLc1bNoPv7nk3TCKCXDKWuv8uaFlqGUIzbrQVv IOz7BWQs3zaIkICSYGHHBueyLXgNCt4zVtlVh/aaX3yQDrlL/91sPK/SdqEI96sbjTKy5Rys7x7M opMAU4snpttVxoWSUraYzWTnx0y5AqykzUf+UrlCsM0vfPPUX75zH47hch97pTMdtHK7qq819/sO slrlKp6NXZ6XTNanxqW7Qpn/OgL4q/lN8H/T3D2N4bUBLN2rN+wSj2k2DKTSK8MX0H7lcXJtlOQe kMnZljYI74h4tcViAXRhDuDZHPtH/eE2PkjsvvOxgAyhc17SNX5aCnPCb60dqvxnSmySMkCE2hSz y32BjvOTNumPcq1C/B/38BvlxMTWM41PeYiqjqEQKfL8LTlG8bo8ge/NXHK8Y3HJfbXhzOX3QPBh 2eMd5tWCHqg+vCC75TTmD8+k4mPaBYnqzD9loN20Pc7jmu4moFN0yJAU1FNoiiqAGRapwmjBnUwt j/nM6xCw9/Vgj4d/jgIqn+VCkvgkGpFI0RAIOnL4/gDNTCNEMpazQ5pwAE73+Cn1n+6NYamVme7a PXJrXS2Ls3a4gLHU4l1wp5ujR0aYNaKDMGcusBOOwjZGaKNK4HY39vEzwY/3HY2aUDG7qC0lR9T9 HYsohT2crgKtsFrDUxM1Mqaps1JX6Ac2uv/bb+LHn08xL6XmfdTL8NBZ6q+67A3nbb1yoAO385Oi VKnEtlwQ8F8g5/YXCAS/+7uHFWA1EmYpl0R0xsykaHxOpVoPhoW0WIBlqGEHs4WFvOD5hxR0X8Zv dQYXz/w0YFAjweo3vw4j94ZeUYrD1TVUxplm9Tvmy4YgL1Fhe5cB0RPF7SuxQnOisMgCZ1Iik4GM TsI9zfO62JxBveYlNELXQm8xWbIoG2tTDij2M4ir7K4nKhr97ulD24zjVVaAzGHcPOn715kjCviq q30Be8LTEzJaOiNq+xMU8F/SMylXX/sNJasKTwtutjZ8M1ggYCPA5q5AeNi8jOeG40D5/G9TFrfD YIrldlQoeBpCu6gZUXWRAgRiqcp1K32fSmghfuJBOGXKSYSHh7iR+AHHgYjcBZtdi58TigijnYvR l0R53qaw4FM1mdQMGdhMSA/tiMdq7FmtqgkGzA9VC5um44Ilv2hPTnxbXQHeMVb39QPdlvsSuc4U NILY8Hh4v2WXMJQQKwXmSwIu7HmfHQ5LFVjCwu6UIW3+7wc1Pcd95h6fI9ARvP4JcHFXteY0nTVn Utjw20wRFCX8+6l8PJ5ex63Z3aAIxlJzOEoUh4ygXaRVVLwTTGSJeWAcxGQdlahZNLapckHqRVY9 YYjoBcA3X1rogEBzT2rIO5QjO3PUZVInENfhClT3VyBVKmYrxOm+E2F9q++dZIoPgviX5Qaw7s+Z S52gFq79wt9r7e+sZHtHMNXQnl3dE3h87DsptKGFaXCE2PqQM3Po3vnOZkujCSUxwP+EaQ4vAN2g p7uY7Ear4E0pm3TZaeBhDxwBlVsN5wkE1EXcBjnKUQ4HsVUI+kZ1uIQYIm0OC7eHKStMUeSw8LPn 5NDTxi//BJ/tCR8SowrLkqsapdR1eaEMG82Uw9QskBm5msNbEnoqd8iPiaDpcuFz1lHNLiFFcyK3 JnbUyq5oNwr1He0EV0rO/hyXFb4u4cU6EWXGHtx1FQpaSbkaiEbqJPiMZlTGv/8Y1/eBOJnqM6jI vGkoQkN9vqTlGB3WXUy6VcN42S0TnpDXJxRpf55ZZ0ow4OQbwOp4vgctHV22s78qzGwAqnYJvkSa xsP68ScHwyENOApWb7R5DPbeTt4JY0cFm3Z8RJ2uywfqMOH++8FGO5G21Rq+tFA9pYgICQJDUhN1 cFIrgV4c6CKHXQrTbsCyLhNhVlSPdffgHuqD1q6hxnPO4g9spiWxYz9qQajKLoeCGy2Gr4VQfnfE twuL4QdtPIHYuSlp8Fo+E2UFkKlsOttLntN4UTzfv9zlojnpDBwUKUIM3phFd23dxKrQzbP4rLeg 6m/Kpt0eJSKN0XTi5Nk7LofJf6+poxUrY0zlIB2NT/bkWap9R87ki26OqQPvo469/ElzkBIwFJZC /7dir871ei5YHGPKeyxmEWUg2p9FaqqzQO61pOmPGQWMf4gLv4ridkAXgJeEfzUxVrnqUClGw+Fo 1dGUOajTq3S/hQ3J9eFIlwqGBKM8PjjQuVy80CV1YEq8sEaIRAR9XXhWIFj2MXvaxnAh8u8Rdk0n 7i7/Br5X7k17tgRdjKuPYAs+tquesH8QmYaAkvAHYvYNKomDDpmm08FGW6CcOacxssvtXUm6bBoi ABo8wvE815yz0KqBRsZm42AJWadX04n9ubKyuC0EKMueclwMe/le7VzjejmG5/YukFQ9rfQeocNK KfePSU1xBM9UxbO3LsqRUfID6q6UWbv+oghZr3lndusX2njpFe3zRJgdwCvj/0bkBJvyXUinEiJ0 4amCfSxjTkd6qC6nKHOcpYphe8z//76AbGsMP24e0y03Y97UKbr9avNw1GP2N2zXSVdrD2RKL+i+ WU+skBC8dTo8eGi/mmMQBldPDmcXONtYSOAATzf9OMvvADwnJrR8ufDm6xm3VcXWdv7Tuggkn2cb ys9DFanSLInJIzoL1zPnk7SwSoz49tdVW5DkaJF7WpTVE2+4XY/LryBzOThVnVPelnzeTCxlbQb8 JkMvSqpKseHvp2VBVTf7K+EM3qMM33HnvHvgDz7wemJSrcUX5CMHmi7+bcW8yk3Uj7uoU+VU582K f5GxRlMNlBEX3hcGjU0S9XoISu1VyUXuqp+2XK4W81TEC6Kv3GtIuSb/KewdBHq2scofsYlGA/sc yfdw4hzQeFJ90pOV1/BeOAaoCNGO1r2o8QINqlioOBoNB16BVxO8iY0gLYWL85kHkU4AgInlPD+S JNz/5ER7vyqPRuUNFQKjXh69xg8R9kI7Mcx8fCtKlcfSXrucgn+EF52C6Q1+MMnvjQxp1dUb4Uoz yHTdHsfs+QdptDpLrMtdrRhZerLjJ74pGv8Zc3OoXMhb7h6Exm6haUK4XaTl4inagE/6EqJ9W69p 37NVB9JnRYWmbnXBX3Qp8sQBcV1CafsLys1XPnUz3y9EutAC0Un9m2w34pRb/N9QBa7Qv7dJOTjE yne44yOe+mmW/vPWV0ECR6oyHFl9sn23NrBpSYse2S9mTX2Z+9avB988Ar2Lr5HMRC/23K97RGyZ NsVAG3lTE5gq4HHPB4c5iveHjcjux5CcXk5WeXC7FyLhaJHDtm93119MRyjIyDcsYTRohP4+fz07 03RCEmzfmsrTEFbJ2e4yqt96f8cK8cuDQbRa2gHXCJS9vHzSVDb0eRokvzoZJpFA48snjY11O3Oe lFF0jRXW96nkvLzsXIwX3ITYyLOzJjGqQJVrZvY9vBZrykeGpGZJ10d+cH68wkLIdeM0XQ6XjEmz ODmUe9gjtq1SHdPNAongtmDWYwrnM2APiGji9mikhYWuJIhJmGaUwmUq7dmuqjD0gPegVw59ehQq /AXZS130idMX/zqsCT5w4ZNvPogyAkeaBcsNVzq1ae8w95gy3Yragi6rWjbsv1cubAXcSPELjMAA eCyXE/FxOxS+WSL968AtEAecmG4STgqvpWGmgJJtgY63JELg/DvvCZeTKegOfs7Bl67L/zi2a8z+ r47tHIaylKXK7E4RjhMRJxFc8meWJzGdD+Luahonu6HaNaxiHeQT0V5Qlq3Tv4AM2TioV/+eQ6WF DbQTDGLAKsZJjeTnbxn2JDJfU1pgJ56WD8qsUILM2WHjgjGwwUfohVYpMZVNTP+eiTqtaaybI9AG PA/5nct3kkk5uzot/34IelUjL/3qKf1H4iNnKYu5uWsxjI3A8ZwMuw9Z3vwk0H2ZMP6DIITDQvIq HR3LGEGubbsZTF3bZf4UPxnUy6JqrujrJVooAmEALtPnq0SsZE2YzTI97JH7NCfkqZFerZhBizEZ W+F09eBCwa3wsekyy0wMqVZFrRrvKDghopmj/TYEZ/t3qHbho6VIt0aAyOd5QxgGTPmzhHcDKBQh 2TUc10iwJwMRNcHibWvidHbNOUogOHNquvCtItH8rN4/QfOb6hHbJtXeqVEbM9564jS1i9k5j+CE wLh85WUN9IhT6vj+eqKedPFl6TDmTx2OfM9VXBzrQhWOG2twC7LPG8mRFIT/8SoRTG2vG4XDvVm3 0ypHei+XUWNbwLfEqIpvJfMLWpyVEqixopD7W1v4Lg8zXRwDPqFZME2JjvnzQkZc01iLkEK6R8TT kRWXlNjOjAujWLvHmu5RTdrrCsyseP/XOAAVJAXQA+9vWxWQjGU1aCAMdAflhF0FK6JCAtB66As8 jcYGz9qKbYTGqmr8h/CPWkmTgfG83+Mb0jsB/Srs5PT0SUc1VW8vTYBw7JbUNaNOnRo5IYDqADCg ddnG8s4QDaWXvc6Ch+Pt1TUwC2ahQ2JXYqxD6X55F0i2Qz3L9yXFLXSgrCI/XDqsRRt2TahrEAHU rQJV7fs9gzV5r6V/szaC6K5RVqnzVFGVqXySYdge62oYzJBjrn6hEilx6SnyMwqiZNQX3BO/iGkj XY91+b6Xoy3nAbjAh6WKOKEjzfp8ORBA2NmV/rCX34EXtKTSzHR81eptM9u9afqK7foBSLXutZQK QyNbxIqlqSP3wEFCwrZmqB84dGGLzcoAWNAbTg253jA2KNQ+9AkE8ZnGHlWa6uOFeP7xyx5b9TbF tt+SnnihjvG9CbFhzKzuq8NEjsdaVvlub6YZGBf0W77X8vo43tF5eXhZxHgDGsTgO5LyNMQuyBSZ RnJ3cOGO+LiLBZ5iJHshQZApFNJzU3Wp/16OG1Xpkga9ZKgsW5qFT8U8pxPuovQaOFZulJce0+UU LBcinBsAP5hBCy5EQz85HFI0V1kRiXPTYBsGAT/Kg/dGBC/Z8U0+D25DvzCO5Zz5KVevc/VQ8wX3 VkpEyPcRaZ8FCxTL4yUrEifLOP1fSt6N0fZq7nVA6eXfAErs5qS9cj+09IsZZV4Rkp2M9Gw/l55f L0X2ZGcBoJYC9LPLNWnVgcFJIRquxuDWnXvMzGcXJpeeOO2qTl8K3LmpJE2xgUQgEgiLA1Kdj5LJ WKgUXr8qAGcZzpmnyYxzjL5/GtEC4R1UZWwpxJtfbuYpqkvESBgGpo2v0nihp41LPBF4ESSi5sYz FIr/jXWSk7MzEalNNxe/qTTovM3o6DFpIgY/SaBAmaaZMLLfA5WlR057gDAeWf2qnp9uu+Y4LO12 yRPDya3ujnkRzRBLYe7IwA5f1ALR9bg0JngPqjQ37X2QSQTf/k11O7Ph/RncbgIvVsJXQjMJCq/u jKsnwK7dVSSbByIYUV1Mg+IqBL2asOyvKf+IaXf0NxPrfdCcgw7uuMnyocvs1v20HMUM+f6OWsd0 o3F02JqRclQeGmwGCP7gFXwaGcH0MNCCGF0biGbooVH+WGlsQLJ7o3NFFBVeZNluCfOqCbv9vEzZ PutUDtfrgOEqo/qYdNroJd848mLDRPN9FkYg8DVRi+j64DlSJZB/6MCg64yuKAO6GDLfaqUSBvmc /9C1vMf4tbUdr1R9j/p9JqzQCNEYT1xEmR6ipQfuXZ0dy4paIk4OUvX2ikOljwrI5HpvunAGyryS CP/3xcxJUEsooCHhcwOCD80U57T/u4dgrl/NTq3P//hP/GdPKkTjK2Ue7K68HMzMSORnjgG2zLFV QsX13vqMm+VSr0xadnN8UkWSxfpH9apq9Kc72z7x5eNrPWZFygAWNGmP/0DbPikdfczPofzU0Vif SaEH6VEgKBKuAcsfKwWLVWlZXM4d75OjRvGbu9aJ6WnJMa/O3xVZEYW+Ms91n67QBuIXgmZGE36r aKvpeJEuGq4DXw+Z2fexLNiKLbeEy2nbR8O7OWFBvkhrzb850dYEBgC8RaqtsiddC4h6/8fP1I2K Vwp8GXbTEA8JzdOVtFn3TP4SC0H424V0qmaHl5eR1M8GZeteALYrS1VtV9h0M+1KKAW4sB4Y68ZK 1gfqKN4ifx3K/C6AoOP/nMkb8PKO13HTDtoF9U131MrzgH+brUgk3UR8vP3IQmJ9gTIbeR+B3Dlu 4dVMXtWBi9gv1+p9bcF568YQRGpIaezXoTn/oNHc+lrLczMQHOp1OINPUGyP93qVLwh4PHtIcAKG 5gwRnL6+/sPjjXevf2p9RPdEmX0mESx6N2Bn98tVo0QromMwRLhz8KlK968cGLfDNBdG4cdLbPWK s+/Dug/yVwAf1Ofueh5rS6/5NxpATiMwMZrKiJF/O01EyD45bKuqByrWjLwrXiL6qjnf5E9gJLje sLSuz5JhcpaawmqJDzFqymB/LVrD2yCUsRNMnOYTlkaTcwYes2iLuxsalQvXbpgVTyQ0OOE5eeWD Syq2cMuWwx8XPfUmxf45JSbFs+Nqefh37g6T7qOC91KOekCEP+9p3ONNpm50XgL6eNy27h4cm64y CwKux9mD6o9LM/OYdioQgJU4Q9SvciwssJKzSMCvlmrzMmnH4Zpa5gz+IT7LAV2Rgfvw8t7Qos2i P0NF0HGYsbGKycaG4E0NR2VlcRcar4ZAxpRdXehlu3tjnMpRgj8rjy/xBBCSq0Ms/WOH7mcxHiNu JStt1hvQzXzat2E/mMTaYi/MJ37lacasMNptrKm+GUM+KJhBJFzt0GW6iJhrPpMwMNvbfgX7ZnQo ojAb6JeoPmfKQfAzARO/YWxNt6b1V8eGwFx5cHe9Hv++9EzupmrI7bQtXIQf2JmZ9OqQS78/ro94 o/NKzCJjkJyzt6ILm0ChlXoLpP2VYGWNdkPuXhiRUa5cNqbc/3BzCCSvCvfqY2qSbWbqC+qSmT9l DNm0My03l5D4HPjOu6+fLPpCWhWpk2W+zFTV2sjwc/dNpxr134e/Ycub5DI4pAJzZ3rQ/mN6bseA D5z8js3ElBeOur0/nHg4T6YQAf7NgYUMJCsEiMZjOC1z7odQP6vUKEEvYyQ+hVuqpFCq2jJT4igg W6fvNeZXWjUyLqUDgd4oHWbofrmyRpwtlqi7T3Y2q4up3tgKjhPA+tkri3IppM/pY/Fuv9CpK9cX vCmPW17pNmkgNR52acYkLMSd2g8oOQdJfh2YYS/5gKpCyYqe1oVwgDejuyxNlqcNFhX23Lad32EE hLgMDB3+OuYyYkp0UvT06nao123fTaAByQgqweU69QDXxpliOT0vqUVyZZziSJct66/jVZOYucbp EMt3P5gGv2HoO/yTcoEfz6D5kkR+qseki0cxsnRAnf2OdcfrLtqGIsOX3jy/cwv2dyLDcT2dECtl Ztn183awWJUyhOz7P89MqzLKpQI4Ucb9XPfTOWDg1AydlUXcXDVmHm0Uvn0Y03d42AAmBJsQvw3p Zt28PgJlo3LmDIsm/Pe+nCfhBt6tSNOBlC5xZi4PbpmF6cVVnDm+7oZ3yj/3qNCXQg5iFxe8j1T8 Ep7jRBqMQHwfuxCIJbdEZ3FI3sDU/3JXAe/g7i0DgIhrL+8utbH5rDINgRPWUySI5Xl5hzwwsjNY PA9jz32dMQ/k434KSuTz5PylWz80r7v3Oacwsnt2DeD5ossrJF+WarDiB+mtPZUL7K9NUuoZ8Kzp 98BgxtXu6bYvlDcvqgUcuUH/RW7qwwaxWYFH7VdZB0TkJ9eyXK7lBDFa/O2duU6CkIcNUeO7MTDm S3yNvys2QmVMVbInEB9HdYxzJzsn/YbkkXbB4W/IoSO6U2iHpzjA8wkbllwNPCu5Gmq87D+jTb2P e9zasY1dYEWPFnFweCS5lnGBZqSOXmIgmY2UC36CI8tjM+fM1NENXxbqy0qbhQtMewPUmcbIDZ10 kS8ws+/Wnsd7CDdjcyDhmZ9GiPTLwXE3Pp37F2x4fU+5yQNsyEQ3/aQgg3CBXOwHcpe5cR+LaPnx obujmIFYEHykBcFAeBU40AKWUlXHFpiEk3eBrwi0cTKYK15U8kkCbdrNklW0nvvmlHHCFTeqbF6J EoQxlTbu2b4PUuDWsBqouHEfIOOR8g+rmxoRmWcuvZ10r5OI2WVmFHLbbYFbfux0xTn9koFA1Fnl mqUuL9xHR3nF27MGRJ/ucBr/lxsaVtcS+uPbDYk+bgzbDIU8eqUsNE1RwMBbyf5+5My3Gp4S0Fpz KC2CEwp3dhRvCQNBMx8LPqmOTB03Oq+vMx0EnbZAM2nfh9jBFkz9PIQYuR0yS7OZtiBN/2VMsbgq AEOUtM5kvBPqK0I3evMjJdy93lXtkqpbo2RUXL+Km+fATXA/F7ekQuzjyNiybb7EhnhvyxxrazJw kRA8z4fFeEfpgwgCeEzEr8TQkkjxK7X58ia5lMcqw5CGDhW9f57v7uMiQ9YHXbyulHnwJ9NAbFPC 0eWMh/VmY1Q69ru7EGWAmwYMEvy7mJEUkRhw32aC9m1MyShOJX44k6kR1bEQZkkAFVxvPPzRQznU RRepBK3yShVM4Sntw4DoEHuesZHxUcnEjC1O7VVRdpQza24RN9WatGLPq7u5QDnHA0BCKe595NDS ARRKsa0UBUPwsjzNuq4OPWQANG5ZfqPPaouOK4Zh/nJbo8qxGQ8nPNTR2E7D8nTcZlcp1aVOnDDG 6QP39u0IbC1Vi6qT7zwZRcfssUJjBa4D0WdzhfXIxi8RVNwjYWZvDRXbER6KnAmkRqOZboLRawTU Se3g29M76YDxFucGrElHD4v7At1znamGvC+QWPfGkQjF2od1yh07ZZrrR9Kghdp9MtMW2c6CiKSj 18eLQgvhO2MaUhMCkeQjDR5xJA/h5FAyGSHqfOeuZcFXG9p2jFvKcotSy63Qv244AKfHzrdA1hLy TeQTjQc9vHGpYKEIvlXaB5CcQXsZXO5vN0Snv5KUpOr3KGsivpp4nraGnXEuXT87QnGE3x5tLB13 cVG77ssCVshMY/zznCU6kXX1YQOxJfk9xGJLSviXEZ36xOD6wCMp6uO7TFxjOJm4iDOlmEWUxeNE d9UpuSiO7lnOGLYoM+RioZfYsIzwHnA8IppHOmGlqDKE1XU6Xvvk2HPLuWqNl3tCXTTJuSb4xNW3 rYVL0K4vWmQA0nyoDfVQsI3ryhbh9IkdxnyxEj4GCndVgaZAklhavCmGtJ7czeV1agIZGnJccDpa EYNsO04QPg4BFXcelfXk0MGxoiyrx76Qv5daYQ3PtQqi9l7jKGNGfi09wpQ4vXb8iDek6yf6AT9v HXvO2sJVna4USdD1BCpn3QMpxonr/SV1bfvdLF1MRoExa9EcwptAFsK0ThJcCiTQKVSVCR+Ff/+j tXwaqCH9dH49XdPt2S84l+DAcfINspHuUxyugYHV2elK6XjvVUmOOl8upP31xQQV4n3cs8utiOBv zaPzOhHPCm6zlGPeNXhUmKfc7N/7HAljl7ViWcwB/jJAKBYOgtwlugen0vPg7fpnznqNVSIiXYVR 0CguHj5i2Bp0lm9oOzldO+WXwxoNExkWga0lXOwbHmSRE+rFX5BtN7+CnanNNu7ThpTaLZ22OnP7 iacgKgZsU3SV9s4EwwHtflems7hgaO932jp2RsVRkAo5W5HF3fmraicED6X0T/cjEAXoHibbB+2e P2J2SUw7hXbZydLL9X133E6PfE3AJs1kRAgd83+LkrsKwwM4Qgn2GnqANsGd8kh1LgK+4qZEDbTD y6TCGhQKwM/6bqtF7HM40i567L7kKsJ94TySiY2zjBEAe/ODm9H4U3TIyxyGZA8YpLElrc4UmGcY 0gAye8nD3XxwxcAWNNvRSpEk4+6fODW7PBQhqClVeJrS47hBq8cMPMlAaRk9PH+gMqe7kj+OMkUM Lo6zKbqqr40GOtExXxuDBrYoB/gs3DqI0eKX9uUS6Yfb1dgFCThIgChgBr3NCloY15NfiMX7woTb vSLF78KiXrUQ52lSW/p122jIYHYOK2XtQC0O/qx+vQIxvqwITSpLVX7t37O9GhIKG2syL/B8jOUW sHDdLJCxlK5JjLnPREFawEgNEkhE+NVjBCZ0VtdJLTJQaCrPLy0CsbnevAZ7xciWuMzYBITpT93o o2WMK9EkFNc2u3JEKKk9TI9zocOn0G24VFD+NiEQly34AYdZnGsVMW/9ngBZJpnekyX/EUNSS2+e PfxM48odL9Rq3KZ5NJBsiJN0axDvXOqOZTw4kPDjdHSvhNSHc7kaVh2zCytbCanrBnCCiD5E1bHZ EUbjFVFqxSvd1ZSIRGIYMlnodZBWVgymU8aP0dR0cn/WAzyIOp4/pcSF+qbqebsXrn+LSvzTR210 3MjVKNiiUOgL8GEYVwq/9hNcex6MIjXaqol6XuDq10ym1Ly4zsJBpdnrthXR4fBPqnGFklMJWSt5 9sq7AyfT3OqbIsoO9AfTVlgiZdtcu667mB37fPFRNVlvS6ayfvts89YMAfIvoRyYektbM0jqv3Gc CUlEwLW9rSaseEXq8kEnf9c+EXXMQ0cDC/zaSK9jWdETLjJLsdhaRpdF+9WeV3Th3mpY6IGzhcOb 7GbzgQNh5GYuKX+K1xS3HHksnFa2oKVEIgsOutW3AiEAhzS1+XPFD/6aS8t6ZLXc7/evVqtONPoj 6aeD91dH8chxbDu6UOMFYSCKfY2mDQEeH76jReTfuSGEXxqOzl+uprxflOUSpEV/nPF/HMvp/d9z jeF/ytnR0jJ/Zw9C1xQ1KG4MYp+0Tn8EihK5JLXh4kQTItNafyY/zUlirrroEYVvZAt17jfx2h/0 xrHVkIEAF91SmunIorwDySD//4STBsMtc86J7Xxbrb6zHUAtbqnJdDDBZ0WAQZzMoHkUHg/lod2y rSCV8CVMbDTY5vUO2Kd3rW8ZR3eH7i+Qjnu/e+H+Biio4ET+tFzU09eFnNPi+HmiJ9J9319bkc8S 8uO/VWQeb0sQm5wDZ1RgxIejLedYeTej7UMsiXmr7/YQac1Y7U458dXPfXwD1f22doj0ly0aAHlX WpGyVxQIyjHMOQs6gnxy5hc9es2ODtI4erOULoRpN9ID/IbQR1XoYJ25eCZ0BPwt7CDpTgsI3/Xu 5StdI6iBqa/UvZXGUH5SwscNV7rGE4v1TX8watxrNBYpPblF/JpQ9maGQLSHUO6H1tgyD0KCOPxQ /qmHBqdnAwwrm6z4OHfHvG3zsgrnhul7ivvFmNSQ7we9X1kw0ZYmMJAZzGP9KFXj/T1SoEv3e5Ei wrw8bRPGbWEz8uSeswvPsKD9UmhV023VGkPI2m+mrdWC3s69z7l7rpebwlb/VFt3pu9R6/62y7tl wrkud1H8gMvxkBO99LS1mYzLUjYbIqU14E548jaoka8W88eT0QamDnaDqF5lVdUmhs7C9VREgYzI F2DITqoG+CU9e1hDvRMU1srxUvaoFioYzr9ymuxyGlKr1pR85gI+MhTYTcm8nqAQr7H61QZ7ZsC/ WgU79E0SD27TdGerRoSPCfgwuE9NFqCUaBsRv4WXAeQymtaAkd8j2qYIepzGSw38aFTfnEouy472 R6iH17/0oaUvfv3X3dvIfxuVAs+kC5eSL5TQPNI9LHi2oXOw9BJ6tj2Tu9bHr8Hv+iNKUEH0f3+v tK8vS7W0ttqe1545HLt81o5WDzATA6zxSnvW2gGqCOAVQ3wh3qKptGTOfZOY3VTsoYGDO1cESCYS 5LOR5SaXS21i1GMp08+EcDs7GL9cTWb57v0QowQBnZHha8isOUqCLPDcpl/5mvL5MbV+MeopDkQA lXJQVY+NQQpdT4PKWrpmW8KrxaaYtbH92IiUFWUMwcxXAhKQKfIfum9gyGLp4bR9JDxY8Fi5gbos liTt3cQWjgwAV5jFKxe8ZnDnOIMnBjc63Z/H9jXcZh+9v/OGc1pQMIV3pmbKRY4s1NBWKsxaYq3W 0eC8m85g/3Ay1c895mI9tzoJvucYJq3/F33BtCgrSRUxFAAA/6Z6SSsQDNcJN9eO8KaEEc1OMdd8 1EPs6biRvAgaQnhkeGwYMNvu6K1qLq2I1pPmUNHiTI9hhiSsd/luDyrcb15GMR5bSlRxWTkoqvig N3L/erSzybGI8eE8m7B1s4Y3E1TO9qd04lST2DpFXWWbIlpGSrgGyjipR28SfHFOfDjgu2giYJWz iKIaiMhClPfwShxh/2tFfKwQcEpsTW+o3jGXHbxEkBFbejYTalibGPNOIvf1l8eRPI7Nrl0NqD90 R555XjSjmtlu7cd9PY0uEctkZj83XGcsWbLQ7mg7eOKmxo9VHX/glt2Zag4A7HLEyRkEYcCge8V6 MJMDIpuYod/6alN9AyzFg4SO6+FAGjwZGEnErr9FFmNvuSmRMYocD119N3EkXqXbD5TeGim7iKnl VSiTHB/6B1KwLLeDrx++F/MHXylE6recKrg0IlDV9T20EvlzNr6ilhGwMEfQIJMrJIz2Q6ir5xuR J6GfNbnBQaRX8sgJbaiZcAh375Ifun3sBoFAHs5tM5d3IFKq2SSDLrljSGkQrSJd+uM8JIZaR2F8 T54/Y3SCLdbsmVnkKeybL9rfzh2tOwjRZslKtRWDM2WvLVfXVoOxhs0lJjTpg8qZY9/RPAesyfOx 13DIzJ0nnLcskX3OoUnnWGZ4vbp/t+nrl6WNYEqn1leC+iL4X1bP5qQePyEkE9r8f2ntetuCE3NO doWY25vFKqpmeHHkJUFYR9dQjiYzjt7EapaZ30Ae+6pMAi0gSdP0m7ZXOJpN939P+hq5OFetJxpy TvMteHrJyjVyhFJW79i3mkB+hwn+bpZiNsi6E6TcvNnVz7xI2S57xGllglHgFuJAjZA98nJ8hp72 HK3GbG6RMcoXXWBqPKJhJMlk6p3X3/i8QvH33cvxJI25tu8XTOikV0urijjXSD9CMM4+hL2xzF+0 +wGmuLqdGVtpIPJRT4D1s98nbgUYdc2ZkvrNJ21JXK+it9IP4SdHxgA3yC/mKXWLKwZTt3vsHUeE BcFpn88KV8OTTMR6O4rKFEny3OFp3Mv8qC7xE05bRV1Wb57O3URcDB+tzvwQGJ2sC0sq1da+9beU F97egAwaD0ymEc3ohvAFjF/WkeGr2xiVU9IhPctZCLFwtpkW5Bn7xXrXbjwsTxLNjBSoxLqHGtaM tfmG9bz4mCxY3mfJ7DuXk29HiD1DFohVYinj1lpxSXo0KL/A3vqf9m3q/VKyxG9QpOGqhJTkSIER NqFOgeY3RuWhxBUce3bh/4F8Td+3Wf6rgPGjTdAorW66zKNEQdSckgPCeLvjeF2tJHwWAeczIcUS CWlxXevEP1TdsFrWmw6mc1Pii5hKtDHrkZKaRw0N/+yi/o4if3vxP422b4kuQAilbcVDKZfuYRO+ uaEAU+z4HMGqONwMjqQM31whVG4XYPz56KeoId5URs2oTNu3OpXqxUh/kxQj4lPZX7P0FgrIuEmW FTBx5a0aspR8StOskW3kN7AI8+fd3BeXEJN0femHr65YdFayF8AnbHcEr1Bt5YeKmXJxyDtptfkx P/yUduO9lzQlf4WSRyIxdrzp+uGBywx2SwUzlj9jHMZXBQvDXCKT5J8R6jOXIr43P+CZsgjuNeco HV3ieaz/6M02ImPU7hsh05fOOF2m9t67PpF8jdzxbmaTxKxP6UGwCXZB65fcerJtpi7JhP0o4oCD Nph3vXWtNniurCKfXMrAvM5i12b3ZL9xy5LbhhiAziJecD36Uk53/Krpin+yJ9oLidDteNk8BTrw 6nJbQyMP5kVUtX/gulGIAw40pLk64GX9KaNm3fiu2X2F3ZnKa2NUIBu6xpBwSY3u1oQ7bCjgzw9K 1SprKJm6ooA/PyYlkSX8jIeISZe1LITquja5/GJSoLREXi+g+fu8pUkIwATtOWRQPVxVAB5JNPiU X09+qOaQNvuBpHZuFFW7jBK/j5jQ2CVQZ621oqJTh8TM/5VhTJfZ1hAEXIPvkX+kerv+WjZbgLj2 PqcnWIlso4bySORaeHoxMI53E1hoiSa9Q0LtlAOcUI9JTklgBu/dXVc+XdbHGc52MuZtYw4z3eqE 5018f7bMN2b/abGT5vDfs2lNx15Ja+WSY7D0Fk4X2FVI6Zh5IjW+f5u5XUCWNmpkiNGlGEMRlXZw bXyS0QqX1B2OiwcZkp+YstJZJ9ifzLrc6RTL5mO0NP4VaqX0jJWVNi8RozIY72+gmG4vnQ/EB9q5 IR4ygyfJiMhmVpzJ/y7/PbCKDeVG3NvM5P9xcVy82WDj8FrdTgqT0wUG2Cv+llk9nzB7Xwa6yoTa wVFL8BLP1KzVNXuvgsmDdvwuzZVRK2xBxMJGemiQcuLWfRp8npbe5pYvOoY6C4DtYQ3FKrjFDlfr 1gCtie1JYIL6KLhA1Z9uya0rc5/O0BKqgfx5hmKvBbZLNYGWWE7YmTpfuARRz67NNedbCQBHdzHT y80I2D1K7UC5/hy8DiryUk0zHC2nvTPVx2nHwa5W3L8QFBe6M2ti/QC771PcqAiHrWaTgjp2vIJ3 Fj0Rf0/3CmfhQhPl/JD16YjAML7dbebxjeT25KE/5kwfLVsU5DEMNtECLp0GTJ+F+tz9vT0Mel1f mV7WKZALi4Dj7B5rmcf2onHGmAOz2dlq39VjOGFJckzuJg9GG19rbdyktp1fYlfwleRj5ZoeoJNq rBBxSCzAUkWrDKJmClxXe5QQRVDVIJUdkZTfyQnzSX0ai2drscaYHyzvYLj2rISslKiChkt9gHxj NlvFV6lhmZYLSCvasxQCTHXSFVSaJPvykRUyiq9Tvp7TNtAHO8JN+fxywbqxj7aA245i1Wb6gC9z jWCx3s1af0IWNRtLDducfMIjyZygjYDLMU/lGz78QBM6Qyji75SfkaNdZ5IBSEhBo1EMqZIM5Kh8 fyS1XtYPnFSMYs8tNGOoeN5uJQGsR8meSf5GlYdjZArvbgOa+G+gfHu9NQ40nfCq+AOMOjyFzIOq Ip7Fk4Yw24zz/65wSrfNSqw0TGliSiGBuvejapxse0WAx+pck+HqlD+dxAdd1xkl108gmBOmGFct vwIQNqTWho2sYRKZg8OIUvc5jqaR8Uh0nXGn+WaQwNwPmpMQTlUtEy4j/cXqMWKzk1Vfl7xXQt1U FhxGFqrxPc1tB27viTSIJCkgZVrlCXUrBaBD1h37l6v0NroiqvJErk1glzJ77V256y7E+QO7A03L rmmxSWulwZ+1QVg9pOSao6gZTvJkG+k24Mqt3Ce0fsxG+U7QblLuOZgEoyvu/kah//cxJSvHFGXn AL9RS7e2r4f1l9GDWzsry6hmBKbzZkByMaI7iHMsKDRnNe5bMrStWJXW2yWfFgyi67gbfLwYHyTS cbZZJJRJIr5Yt8bKuIEjRA1pULMrkBpNJl/Dy1pLcnbvwmfjdcM46nuQwJQuV5sKp2YnuuYq8tve HaUJcnQKuhRnMZYJ4uRvSHnVINfxhjoFxydooG5yhhT/usw/u3r+CGkmb8d3IcBj79xPbXdWXpbV xGDinZxL6FDd/vmRfScXrdASkLc6eXbX8pm6uNg5Yxgwx4ocmgKoeQuTLFZ4ahSY1/D3Jp4BegGc kTAoleccNwxtpmmDplhYdRj1zem3WynI4AecB43NsKt1+oy7aBdmHk7Zbw1yuYzX4zkx4CWmjH3l W5wwhvPPhoic0GnoSFhik768ngXguj4DshptpJN7hPXDgeI7LcUAnIBnMlYIbbaPlX41CwO2PrTO 7q2oSqCipH3Rehugk0Tb2ccL6+2N/iv8D8CAwWVjSRIdmLMb3iy8IWr4PtvgqztsSfl29tnGziQp SCP4jCJ19V7j0uGn7dm+MBvWsXoYoDQMhl3Y3IuWg4uE0H2HNxVC8mcKgLg0IXavJlrS8aafDFbY Zo9WQvJD+AVeBHI62ogpB+98TuGfFH0vO9gnZtiQYTJlAaD1aSg9p1MVruvbmDAnoHOfxEIoJmRT gPIa41kzHbGMx4Sacnk6BVrt4HxRBga5oy8JOrhrhNQvUp3/pYSb4pD+CgzqED+roPSIqQHLxIW+ b4D7FhNZxYxoG6NFl0t63U/0u5G+TYv+6bJJ3SSI5RyAJ/FQh5wFQufFjSfos3QXur6ia/fEJxtS xXfeqcCzZUziQPk6LDH2yxJKnG9AAqPnEHn2UPhoXCYUGprCBirEga06VvpXREYcvM1xt65r07Em iBPzZaa39AcugHB6FMG2DS904mYj9IFRJOFtSyp4b77UwVs7x+VwOa5SiyqOvLz9aZ8mCOT1knw6 MmCyE3rk7A2ORaQQX9gXkwC8EFVlLeUZ440perEArIFiS5V2KrNDXDBAFgt1vpgsPQCbuqY7vukN WyeRX+Vh8bbnEH6+cFaLL+gQ6TIFaZqojLX0FbiIaPHBT1z54mhSbQc2w2tez4s+eeNOJiow84i3 sUgtyBPYwJ74gsB9TNBRQVtrqgUN0GAqR/4pk2Zy1IPqjnQQAzgHIZwxnqjOI0ABuxvlVbAgZc9u efnVQxaFsKQpBUbY10shmUrIKgKmG42y5YpxVo/O4b8aRHOhiR/sMot84QgOpnPuBuiTx81ptJ3H w3hUHYyPvMDkkvkG8Lc11qDZRvo3UU68TZJ3ImcTZUF5RARSJuXTn2pQl5qtw0wobhLTzxf8UfRt WivX1+u2mKQ9zoAmsH/hb8Lp4C9oQlH/XpJiLEufcoE3sS3uuCQPkWwBFxLT0C32VcFCLRAmPyu9 vzD4lCVZRXJ2lNsigPh0cegM/GqA1wjjtYd+PIjmHrhs/ehTz0Z5d6HeM4qWfOo0QQBwaL3hh5+f r8dyFnyIxMBnVjI61/3T6c+hn+gCBpvrbArF8dKlZXvHJEvL1pmDvF3DRN/nF6xD/Uf5/2WumZSh LsjslTllXZWxbzqUWQUYpve+xFD8a+SSueoYtszaaeMGdoSZpMwqmy1r3AqjtdYa5Kk2kIl9+IsH PdZzYqKV5IbjoqH/GLd85T6P1kuNWtrUfVU/WHaEPM7o6XmEyPfUWH/KyGE171lRGHPavUPNMSvg CF2DIwi1IFfWCWtJW9wYUrcQms3NA/7OlrZ6/Jk61H4zxAMhP3uXBU4cWAy7XdDeKmvkmyQ0VhKq sDNwnlPw2Tw1fWxu5b0GL0xlW6t5JoUDTWXWWHzLVWHhppgFKbDVizihFs5k3thGukvo/nGsIpss nSTaFfe7SPYiqUBacEwUou+tcYZCVFK0VUSvPk3+Hw+Ep95eMi0aTt9XAT8ER4xxDOIOdbytse8j /rVsUpyFlGCrtFV9gJyrgGgvfQCEwnMSgIhAtGzMi5rtUmrtVAGT3TxRLOvuwu0HS9x61GtsBHPK AhY+9wk/zJMSsCNKidfWVNbNwKwVgHmGPXm2lJtSicb9GWfW1TIK6qxtcGUQOLuNVKf8MyeO3iTx 7o7ojGb216TRqebMVDm+uGcEUgpBmZFarYr/Wlp7Obe3Jhad4higcH8xAq62xU8PjZQBHSVpmHKJ fBwjWdyMfe6s2Yjol50gu5U7j+evt4g+6pjqC7OU/pdMK1HV8jxbdAv6sRHnV7zyqlVs4LGVbYK8 wDKSDi3VksrjY8F8lFJWZlJ1hDsrCT1rVsgkUL8UY/OhWHBo/2WyAz2BrswJNDMfYSQ98aLunnxo 7kOaX3hmyxoTNmnLS1VZ4SpLYrfYMLyEcHYw2bQQn8igo05vowKmDOjjlNCIcekHcgvSaaCgGW5k b6c2nudo6GN7nyXlV95SbxliLARo97gzlvjLf7rwUAj/Ph8yd2GuJk6Nxe+qpS1TO3sWzrwrKTtS O+1A/M9pMJoAbiNGesS071uNTM3sjzHGPPm40/7iTjt1AUO3WD5SKkPPVQZRtossMRCNJIoRlQeR UJU/n1+BS5nykM+t3V3O69bhx8WOnaK7fm4PExUGU2+EbEFUjgxInOpMx5owdtjFFS4KJZSqQVgn ABQII/DC98r6b/Y+N9+ONZi68AHt9VTTASp5y69H8k3AoyMBchd0hzVCtzud1khe5UUQYQIbyzhQ pzLi40gqywZ9qtJajQOPVie2r6VBclYpUZV/Wt+JK6ZcBlpk4syI9z3YMWsfiZSGlwJ3/Y2JBvLo liya8jdees4FdQP7MFACCO/DBh1jD9cdFhg8/RXKVmoJWJRQcOn2SVrjSbQJBn2gEiMjrrl3PAA+ owfsQAT3RlC5Bu09VmIQ1bQlaEh7lvfp2hPC7cPzCmPovNLSts5kJjHhAJsotaRWBxTWGHeoQS9H dgVhwqYLcKw8FK3gdA2RRk+FqjmOuXxFEPk5GoQXPTLSS5PGGAFrflv8mTm06/tridCiZ3PguOSE 3fPaPCiIXoM0OLJKZ1RTzScRv3Ws0dJbcdniDavJa0JunBytOLoALsrtOCeslkcmU6x5ArzOLRTj 0RB8aSVQhY2pHFBKuBxZTwG/XVL7L8c56i/EwejIL8h7ElDHYUL3MeDr9y35uQmXiE25dBqYYlmt NtIh94D3ejo76bWvTMs7nP6+78KEKJ7FHAfJKmc7nGXVk9rjr9Vp41k2npgAJWkDpnAtHy/ZPB0l IrRBd+thduUjVyvm55dL9TNFSc6ErPtyYQTIsD7c8NeNxc834B2BCjg+WNqcwlOXOTBwhyg5wmXM 1vcw4L6x/6N9xtraJeaH/0uMjV3AvDdB6/X+slPb+9UiCaChfoU6Y+5I23wy9YQVIFRJoDwh/Jmg 00wERVrz7WQffkihdNbQBHGKIEYxeLf8RRfU2ynbAGh4zlEkCvN0rPs36yBDnGEwDvnirXoycGJ1 gUvO4xr2tt8uoQcpB7USmnUaEwgI9bR/ph0uOvw7EtkMrx7t44DG5cCFEFmWy5OGG7trFPsW6SeY Ag2C2eNAkDX3qYrWPQPy8CfjQZM6gyyPJfnWBuiKvd0Coe9rTltEcniu1pH8zNwq3PBdaW4YDRAg kV8Kd7XQp3NQ2f7Q14/Ud3GNk2WtazjsPOLIb15G2L3D8bvNCOvEOZnQGRQFVn3vMzmmQSMvQmZk vGJ6PJzH7kw5FmNsJcreIpEM5H6HKQpjhy6PdCAUNzL9NBmgL8NMQIzy/BeIrmyMbMrvpWBh0CFj 3yh3yKUXvdr0DIduDeaQ88V4Ep0HmCivjWPxAENQtxHVSKWFdN/qEDlQgWykHuMhrpIufbnoY5i5 KRbDmYXqkTJmIlkarCfgSVnRffq5iucD9jC2Ph6bp1COKctZX1YiabAjt0NaoDVOCuOioWqgagJi q0nSxtCMykrLyhgkZy/QnaJB6FRXnoXGy5Uxu/Bvu6Xp1pJaZNm22dnyFfdDbeBu6f+SbImW1Gbb /0iGo5vakwzd7GsCt+p3Pv+kfybG27Jhee4jzCw9PJMouSrnW3uJMQ4WZ7SM0EBu7APX8it2PLVh hxtCZniIw6PRny6DV/ppfV1flirUn31gMT/Q6prZIxRszBnMWZP+/f2ORFZT+4zx4Bk/D81baIp9 IzFpEnEDlElpLytLcy5f1wEKZwiHxv4k47flf+BM2tli72HcZvQOSZAPz1TCzjoXVgfKIq6JVK9b KbTsdffCFmHwW7kyH2qtLXHUn3LLNVU/BpdJLy4+SNOBxzZcZYkk68bfhGX6ButsnzoQj+5IAO2G yvE2ql8bZT0s3Vi6t6/PJa24HYf/4M/AaiHQY0XK9maDmEVR4544NZwxMVKFwQqWQ17QtloyWZ5z 2F2XQTvFhQ/6VmXjhLyMmh7SjFprE6hwcMCKgmeYYST9YA0AHntXg8RUIdFUBlbWfHOCu+X3ogIp 92dd+d7aA5mecAXR1p3AltdR2JQ1NGzIncbTWBMjQ1dhfMiZTVkznMWlfZ4EcLvlAJJPfD7S6vLM g9ek6tDWe+KQ9SQdfcf1mC5FsbEDF8a5S5ZYf0DjNt7TGKjueYYsQE3xEYE9/zhlTtK0w1ZCWBLW 1+sFwe0Q2rdez0ZLfGRvmDDBqOqB+S4oALxaQf/a++NQYOGYIxF0hVYiXwSOO11yEflZCszZc1Gk BdhFngFYWokFPEHgvPFja+kANPwqm2edImwJbNzg4FQRfnRtjYIi9oxFvIC4mfeKYqjStSBuWAHY 6HqYRtA9GB+BEI+MeYrjfh3GFv+m60WFoCwX+mymq8Dj47Z+nX8dB0z3+rPIDCfDYOmKr81desTk aRN51p+OHC8T7B+AXKDv+tgeUZvPKAlV0v8qOEzHUGaadW6tMwTfQ+KeL7Z7IF4g6BusOqUMnvMF tRWQHFhrIyiozOenE1wBGW13xf2tFRM2LyTiE3xczhKOuBFGw7Mx8/tZ2gYdp/4V9o99TSEHAJVV FB0uGOKDI16yCHbSSInWiutDeIFXSQtFcoE2j+AK/dD/G0dndfXMaGREq6ZXGVyzsUWqjnv/BM4G KslPjKAYR60j1wvSI40ClVb3GpeOnKQ2Vtq6srdAfuG7eCrVLhb47hbPiv1cgwSrduRFCrgMR/Aq EitBkB3hmBMun4QTOZe+ObUKFwqJHC+uvYSKS3EHNzXLLe94NvHG5XJEEke/bPIpmNADJQtE/Z// g9s3rgNw+9Im2dRz+v/6AZu+xlCWEaI+VytbuLEb4i/ZnlHVhnETmJZjIIkraV67Rff7nKpOI3xv a6xL8fWdTMzxxK8eO3IM3BdHfD3lmjy3sJGYgYudsi+DT5tIlcUw2siWNKWtUl4do9QEEYjyiPVm WauMRdZRXJvSYQZBXPeF/xM1Fkrw/E/svQ+fmRyh5TmW/56yHyNo5W+03hHNizSWtXnKRoqlJWQu E1yXQmDGcQhGc5lj5+OkJNUqsaMaI/RkkE0mQYETea10GeX/Yt9yI+05oy6VcaSnzTNR+juMlWbe z4RaKJhrkDbGmpgFobwwgC5JLa8lNb12OVJApvr6WrCEiGwXfqmX5BPFKA1A36ObvKFbKiDlqTQv sETCDXF6dohNHCGh+zYIr/0pObu5g9v3Viub/G3Q8ARM4I62gF4PM0ccTH+t0RuTDhZPkxmMaxcJ UJ5yjnOCKkNOEW50McX5zQsESiLDs6Mp3HJ8tzzw6EN68yi0A3cxl2bSNJkDRMc9tsptES8f7gND AUOaJSqsP94tfoJ8cbwAHIx3UsMH5L7NkUKU8sY9X+KtuYUIwEtevOeFdAoMQb9+ui110/let5Zt mTq36oDMvlu0VwEWgmuxw1nmzV7Z4btjFjprbyPgxm7eXnH+wwSaHX+mBcytOm/rukyv3zXqbwYb pPhij/EqBt8KVdY9z2T9gj0eDVa4W71pM+y5hgjmbwED1p4g1+uN4S95OgDKckaZ3DkjyUoQqkBS /UPirH0K2YurhzGde/YfIhUkCr59HEcXA2JkRZTmGSWwDURlosBe0lMPY3RG2dBoRhBvzXmHWCOi fdSFGxH/f+flV9BtSGVvK5hyCxhU+of42s+LKDGScLvX9zfxt44nFSNhcBFiTwvFhVLoUhhDGB/B puTGO88i52CPk50SyAInWaHy0sQaGN3qMhb1doKBRD1lH1EOUotrmzr7C+qyfpKsvxb7GWHW+QmD wLN9kEf3LPUs+CLEZdbgGSUYab83FU66VrxgrOVVWvQeAAlLXmh+AjxGsO/uNnk4MysqI7zO2H+i ghgSzN4KlqzNYhEVF8fef+dfVz6CE2f6m4Q4MoHuSH662hzelvSgWaJqyAFr0H8nO9JN1WuqamRc C1jZq8JocPzFzYJJj3dXkBo82eq+1YY1cRWIdhkUSQZFp/hik2eti8RRNQuRWSB9drH2tlVSUs4u 7coAJTrAgc8nI9wLWXFyNrtUcXSQyTLuzB5CWWWPvkhyTdhJ1cL6w63WxZVciqNWMxqKp+fiUiOk TBOlnOrOj+OKC1WfQcdojUbF9sLirejohiEnrBxc5XcQWomqnBQwR89FfDfXf6UZGUr8Kg6RHMaE zRzUCYjjkzWRKbKzzG82iObC/9YJ0F34Esk4yzFiFWcqIja/OmIvMN+tbxifjm/Ao53xLAgQSQDg Y9R8uEZqr+lnS1G9ACBH0zFEBlEl1DxAVDkmYlvMccVjnTXQNlO76OOpkrDeBXAQKoIL/cPumEBq x7ZxaB+J4rI2mxNa2CDaVEmHBFWlzMZIdPzGHLi3LCCjiJ9JMr4eq7qfjdUSLiEr2g1+geihlDwI LdD+wXwoXLrvNp0NdDeUKBFMLuIYwMmuAb6bg/mtTyFcWJPZCA7q+UKWMND1REhlsgLMAiKSflbF ctrVrhMdRQvOoVRjPuVPtEIvyxjOl4u5rJ9rpjd9dvWVclHJGRz44Ke6iKqMAcJi4a73fmYNcj+F LZpvzNoI7wwKErA+dANadp17SY6RegNmu1/5l0CNVHLJl0gMjgFXk3hZmYl95xj2Dg4kdji0V6F8 Vbq+a0R2DLsS4KLtI6b0szbSLpuX0FsjTZWUFLWoAtYXahTt7anQ0/hD9qk8o47ih8Ka8SDlPCGX dvHWU7QSUpH+MXmS0CJIigwnSqB9hgya3KQNA0SS8+7fTPZoI5h3D8xZSsVZJ251TmDC0ubO2t7w P5guGQQ0I94jQFbVIV6E+cWnvRZcTNH6zjh6J6iaS9CS0ks9TSzDDNHKq6yC11/ho/5G6XCFBkfH QUDMFDCzqqE/GeCz/RggJIYPb8exjrXgRcuZJmoI60RHKkv9PhxOGS4UN2C2dOmG7BWuGQ/2j4kI M0TV8+oFr0Ym3nIUG/s0/3vNcTMpcgsBcgVk8/6vjlbmr7Ucnd1mCUE3xiOVWCMvrUzeVpo6PUpD bn3igo6sKZPBQ4a1eJFeEtuWpm3qBYvBIrCU5eqJteQSPTEdCLXPpE6tl34fihJiwHyTGk6LteZ6 gsp8PgR/fBTqeEkGgmkevZ1pzyFIj5z9OdtuT5FWbTYQA5Bn91SF9IwKgh6cEhFLPfkVVw7iq5x0 M1U9nvWKlr/xXlkl89oIp+gOkYptqiMm/D9dL+Tt/QYIcaDgNaCSjiYWwWOLQiGeQn9WHPbnbgk6 tyrq114j6OWBSKKMXLiCVOymwFnxBul4RGrJqqIUPiG7Mlzyjgi8FpgoVKMFKt1ufhjxs/3RRCIq 59EQLWZEVr1bzyEBq62V47d1IoRNo11NjZZZqrLQjmEsH8Li0fnF3MwjYQ7oP+uSGq+0jYI3eseD cr4OBxSzGPOfkVHOXnPcHpHX8ncoM9Zq3nlq+chJ3Y9fiw+6OW7oRugb9RhCMj6r097P3YUAh64v bZ74DaRJ4TWuZ/eoRueV+Ge/UIk676yCKBJN0f/Wpl/WlRMgv7orPL413dbkqG/FKflm3oOFKuo6 lEgc/ZWDn1ELSrQgSAID7Sa8nIg7bhNqffFa615/+o3uG4RYgH6NEkY/yUHJROL8qwVyxfLZVSK3 VZWWNmhGjfhApuRCMxt/jHWQqI+EC+IhiVBYUlxQwZ7HnLeFwm3ZROj2R12bsjvlc/XYVFwKspkR dZwS6wFPdywAUQqOidLhcxHsj60FUF8BEV8ZqAOy6/T2sY4zXamAleaNWBQQugeKxQVdeABcq5P1 fD7Ae1h25Ha/DzOyIGTAyuboU6/I1psWvGiKTyJYEpsaH0r3I7vP1uLY/4q3X+L5QOEJIKwGGt1B MdVBUOQew1AmwP0wIFvM+/O6zNGqLNpiPEz6jemOwfFHJ7pSacYduCmjqJrcXFZVntDaEbBZVC9p Z1fOxj+Wyk6wFdzS8tyD3lyz5s3rd/ohM8S/P7TPYieb5yQTYwMcOsRudCbi97+T5OhsIU6IEHH+ 3r3EOdkRNnGlhEacmAYU31Juzd6b5AxIbxuvJlZMNYd1Lw5rTLoU29ZAaKztv9ZqJsOjP+OSnULP VwcORiGBIyJt0tlxAg3Ty1tAK1rf3BM0uYjcDrBcdaQW0wlC9ZbQJYXs6rj4MEDciIcOzqC7Kv4n ZSlMObDloj7g5xI+ucZZkguQu2heU5Bk1EsO6iqFfMHVyLnRYHJPxd1p+wDZrhKxVfoppN66ib4Y cmJn4gyms+EJh7aRJv3VTmrfK+QpejCL0/TJAdgUw587zzDD1T1Zd7xV0Ozklxhe/RwtFjPaZAfV crUmSzVfBKcQSKs6FUDZ0V0wLt10qeCcwsC7i9mPaGC056RTQyVlLtTCUlsAttH+tEhZA68ZLaCS lVhedxv+N1ywxyg2zE9BFMRT92/8fW3XlLVtCERK59LPTuKH7bn8P0t/uVPMOWX0fqZqpduKE5Db bWURRejIu+xAjPiiuHW+wj84IfL6yPCC0E7CblB+EprpVIj49ZlCdsOxVXOGhcahV0gH8qyGab1j g+fqEnXTheeBPY+Z71qPqCedX/IC42GgNnojM8oO9gtDU7rhRbMjffU5LHjrMF3JvSz+Hqop/xcz he7obVjv6h7cazi4HbXOxEswZVzv/b5lolRGCcWs2cZSeOJNVVq92DKT5OcdIwydC/9K9Zg6z4Ty T38GjJbbwE2OZkOB/5Vr1AvIkMtjavJEGSUtiQ3kKCdYFv4pePJtQdand2A6aOEJ4//bMwN4AoXH f50jAFsvTBw3ZN4ikJyYnCGDTJ9Sca/iq9aXutPLTzeuUQN897b6rSVlf43PydlsSVs6pVq6Lwds hSRAABERPH71cBfFvfW+Qffs7J+J4ATZ6XIBTeu65jRx2GP1sThPAMQLiGk4K65p68Bj1YvdCzsG hXHNF3+RS3IeT/juQHPCo2Oxe7MDDAmGT5yC9/AnKmm/SynMEexXDWtiwN77lKu8Fp7w5/fuQfFC Un/YbCNCAphOthF4xYWZNua2jFZxJgtcg1YbLTOObi+R7Jtu9CJQLD23i7wYsS2gqq2SeVa8EZdA EGYAOChK3zEtUtfKlBa9ud87Py4tJrsGxKLGriD2IwWxcJjwgnNU8wRScK1xqZ6fY8pkILopx50/ F8E2SmwZ03EAv1UIZXchfaWzMIgMg2pguf7Wll/TCCtpbG6VDkxHpWfxIupXTsHL378jHiSCE6e1 ldvTF0t1gcOnb3ixuYn0RWLbNwWfvl/Lz86K062Dzusqzf/aDEEZ/rjzSlxp78bEppVj/2FO9z5M XSxmI2phdqsye/KEcNK2cbC5g1sZKnGyZDUBdJdEPhvWiSc5RrhIIBZCkNwReGwHwKgEBQqfI8+e bfnlhAEFzDwDU4WH2HA9JSjoPJu3VOh01zPAXl7vwTkpTyBzfwjRq8QhiXNMXzxLtK/JFf1jFkCe KJtf3dJUQ5fWEHXCaF1WVtpDaOXcbf/PA0nr4YErg2r98zC3aJEzZ2MJk4Wg4iPy1/Zd+48seDba dRpWv3QcKh5slisEgvDArY98VQ1C7+h5F/5cVeFxe5OfR1RVJkUNrL6py1V7gypHXaPMOHiv24kh 6/FyJOs+ftX0RBYaVarlxPZVR45C1YJSGDJOi13cxrCb775G1Hs5DRRixH+MDDnXzt0af7bNBChc sgCcdgnbsIqbuWS+uqEc7rdfBoqX6furnjpny7h5o4VwK0myrH8Eg8Xew4DVJLObKtUmUv73RTWk O/WJ5ndK9yGSnoDezf1LN50knP6mtja33grQKVCUxFHWWQNjDwZ3zosNj0+5A/V8aYFSjKbvc1Cq 4XfroMGBYWosZBr+yGMz6TfZLQNlQlo5scLB1uQ9uuuVuNuug3dN1NcfIV5fIeEwFOS5SWK+Zsp/ Xg7X0NM/Cc2tCzLWCgFRL1DfzB8UqevAcB0mM2DhZL8tbWex8WM6XuosRvbvSVYKYRlHRMgsrCq5 GlS+K2yDa51Uzn3sqFepaj4Ks+lTXE71YRq8nXVXC6cjhMOnPsa/ZqSEG9rwnNtbyxFhCN2ILcQe KqQKWwTeNRipFL75wPcwKnpKWujRycBx1MtRg9fuGfnO5ks8BLizSQYsuzK1PFLpfRZBwuzampDm jcY3/46cc+gl4fe5FLHmxDw0Wkpo8tF/B4z5l1cyKf1pa5f0rQ46M6AVgYD6uoMlWWISL67aG/t5 0bfPlQpraXe9V/4751lu7s0kg6663r+n2BvE52jFupcTiOF6N8xxhGB+5EeahGfGenot/FvEtZxc wrYkkRD858vIPQoNDSXEziH41uJVkB3f22JBeNPdIe/PK90Pnxe5dRCeklcW6EAr9r3jC/LFVSHS qauqmwTXn5rCg3/kZ/Ocf31/xSqwhZ05SFdOP3oKCclr1SxT8hXd80fb/LYYPJZnfFSmkUZqG1DJ 3NPpUBkxnAib2Eqw9XizG04gTNqqdAZ/30oyXlolIwgjf+fiU+KrdDaxWuyekpByOPwDV38oIarf BIgh8SGdV7/NA4PTF8qNWdcEaKiM7YjOifpZ/coVp7+OHZo2Hgrz84Tetoo+6PjLP+/0pgHI3Niz aYeD9uMolJBnmXFc7yqqCaiJ2zxGRxZ1KQHb+sbPfjMidlL2zbg3cr2i8BvzfUhU57qppv0FPjrM E9O9p4XE+rneH5Hd2UPJQeQsbRXT9b5kEoP7K6pRv6h8cwkPpN4rKSyqU0b5QRb9rQ7QjBGaCCZE ZdkLDKb8ekprkMcDQejdinwF3kxP20G3FYjUxx0zXE1/WARvE8ARlmtzBvvuFsTFpVEA+EA7NRmr fCVSZTHXerwwctqomeTb2JS47G7vxmY/xxb8ckm+KkTXYTZ8UJ1W1OTiDyrzbHfhpWts9v5KFe7k 97uYpGBsC2kPljiUpC2xBm5NqWTUkDdHWgwsS04de0NnqijMJ9p9G3HdoXnSdghLG7jiQiVQrU9T Zdw5+Mz5NfFA+5tDRsCGWrJ0+PSA3JDoNkFBVxcJlbzDTcOAWtRhi8huhaaNp7waHeVjPEdE9b1Y lNtQ6XVVAUq7N1JiCrEraJQ3nymN+93YXSGvRO7LYtiU91gsAacoVv4bJQ5dcFELvx1zMozckGvd jM0qR8n3GE2foT8n0o5jUCAs+wWCo89k+H5ENvvVX1WCSezClHZ+7tJsiYEqedbBLBTNrdAeqFb/ jW6dYzf5Sr1BKBJimyqWqmO61FPHPabCWR+iDvSwFrJXz98JDfWeBYxmCT1hqpssli71uBy+y3qh BqQwW7WPKOCWijOtGhS3bBq+xxuk3i0j2PfszwzVx4WGVJZJ4S2Luo9Ml4AF1bgNpjP2hcH3dH0s VXtEykovyIhhMqSVjV3dclD+oNQvowg307mCxciECr4xRzku/TYgTDhhQovXkjP5VzyaYSfyWjXz hGSxx/CDHfQnQKARMCCEYou1PuY/xdqrTCT15zO9d4DvmqCXgTQUKnmdMtYFmMEEYJG4s8mxCl+R h2RxPB0t1gmK3l0XfMAPs6eRoI8tIerHwm4mWxqP2kZwkkyuXT/ruiSwgxnt4ulc1fEYCdGWBpDP OFINiQseFeiV4hVLlb+iLPNlS5VurfK06vGVZfjTu7LDPA0gPtO2V+M6q8AlGTLjqm/9WqUhLCaa cpajYREUapg3oMph3+L7CtrYWWy36eabsbWcuq1JQNlHWovA7BbvvjZ0CwHg393LZdRnb/Pr/vcA Xs0qy5mcSmQgm6sQQuYlnFjxK5Y6ykAYCz6Y5c4TF4oKwC4bCOpOkWJlH1LnzQ6FNsf/3BBFkNOl EBadKN5tdprYFEAWl83zOViZr1c+RYv9nWYyQ9zninyCfkcRZM7OaVB+mvFMZ78z13OPA+nhntfU 4t2sPUpsQ4ODaQQ99SDdYO1xYfwsCYLAxaT6PPEc37by3M26EI2B/sYRV9USaU+Ipjwyu5/Ht1l6 /crh95WUSHNew+5plvWKuwEmH/x6ZSOj5vbVqZ3fouQYgbgy2eSgDCUb6jG0ljaave9ia30BhEb6 8UDUrDJq2mQ8xMBRuWWwfZSII+3RGdaDtFPZYSZwmGT9acUQmqLmnW5F6aO3pwG8mCvzWcvCxFbq jHuFGWkQSVLm9NGSZhRi1qPZrBAX2rGt8SdlGw/1oQU6Xbtqw7MIUwDUcnrrW2QLF6JBRSJOFt99 2DgxdM6Y7BM35EWfRGfDM75tiE4X0jNGGOvVmrPfunp7jylCCFIPs5KXEchTKhoLJz3VY/C0Zdy5 7zkdjtmaFBqlUAq7NWwxWdYCIuFRurFa/upw7Ju4+PUPR0FLRvpMmsznnjCUzNNPGSZLGjwya8QO mIoBfsV46Eez4xfrP6ox9eBDNNq/5eEZC/LVfv2K3ILQt0XXMDN1VmlVNv3dtQYbf43zxJgSqYXE UtSi7a3I5eOGgaAhF3GzxrQbU9xb11hC3VZjXeJvYZxI+CVIJOfId796f4mF05tzGQ1dx6nZCDUk eKflUUkmEWr3lCnCl/H0M0rVi2cS94B7ObU3iOVPvegCZDLjAHe+vTxRRumgOtx2IXyrDAu6SDGK W1TY7ivcU/iAOtfhcXzuaxCT7sfaw+rfScNmLTr6foxR6gmr2USJApAXAh/xCw3YLm4Ig7mehWhZ O5OF2CARmvT31ALbVkacP9zQ62/0FTHO/cWnTHw9CrQABzRMb6l7csOwFkR9Z49djZvzRRhqvqL9 1jU6uwf2/LIU18+O7j7KkYwoFQRkmRrKcBlGHkuI7s6f1qWlgC5PQXyjXhU43uecj1PLG9n1PrJz chg7K0D3GHeGFKx/FhlHqcZL0zzBsYVVuyk0JU/JQv/ffpUQtVbRteHNXjXEqdIIwanFTcMZSN0f fF1LXJRzJSkCAHekuMt3FXU8r5pqPBM33z8SoPMIKrjHEhfzLxBxKVvh7uuc5pVZLrpL+7SOACSL hkly1NXdFU1qaRbzdtKXuQqA49oGkR2i6yyChySWWHF1t+Mwf/dQr8Ei+R1xFm56klhckYMAhdY9 I4KTTNZNenxbhSUWyvuUrgGsGAYGLvbmQZjuDXRUVy1K6RnCrUVGawpooTnb3rBphp1Yo/aLIuCQ 0VqnlN1aHjLMiXOJHN26ZFMwSELm+Eb7hktX6bsobgIHLZ8fiUhEj2zz3eXVQs5CquNYbn0zD7n/ lI0I7u8+iVBWEH6O8Ef4DdEsXFoRjGscb7GvuzaA2ZyLPw0ndCvfGO9s7UN1Ue1ZBQWWa5BYzeGz CBPTyuA7tzmyYDhehJtp1/HyAIOJ5Yd3DJ/dtU22GIz1uPkPANIYGNiVjOWlxOQAQ1pzXjsscl9U x4O36XTvEU7IqLwwWrXuoLpYEOrEb2HMjaNbnWin0jxnm2Z14Ah+jJ4O0RSjUQm2F0FA+YHvBr/R Rza+9ZXa8x0J/O2+upwLQc3g9s9cZ2oIg/EwTxnwvBdEpw18mNXmTqbzZ6ZQ0/jnm2HqQmml0vgT nVlZaB0co70pIkTlWIb5LWZI0RtjqSsxnoOv68kCp3KgcWMrZkczONmvypVogFcOVsCl/R7bSMhL b5TpiMurQXUGQIql6d1kf931plvhJ8vSB1b+oFPgG9tcj4aMdrN/HbvN9Sa/Nu9RcOr/pVb9PHwG D0xNHu93AT8/dadlzGJk241xwqbysxYMaJKwEh8r2+7j9svv0c7bcziibp21irfjXKRE4n3QNuSp prP/YPUJ8CpEGYmK2XmCu1wd8H+stbg2gG8xiaso9F4l2jNtetGJsMtWECv9MaiVZbawbsL1lnQH RTn5ym0bBjtbp4D5iQmgHX+foznFyNm6/6p62BbUe0yaTP0W3GSoAm1ZB3/Pyb9j+zLduKk8Efbv uA/FVuqYO/a7QO1vWu91z8QnLb5vb5HlXnqLF3UG3G4wsmOnL22NrqIgauevIf2UF/jKEmEHqtQO cfIOq7pV1/SFf3W8gA/ii0azq8jNUyOeFpo+fPOHPj9Kq+vQ3Vtecp/7bcf0pRwuFOdbtlapFwi/ hsQ3zyWkgaEhUq8KLF6ugsKNYs7FNtcpZCNcJj+D9voG5/wOgBxc+cWROTndyyY3+Lm3RwQRh2hk ci8qvhEYwKr6fyfHh175McYh4Xy3vXwivnpKPo56/sYTVvY1oi3ZC8Oupd9Uwh7u2IaJspLvxXDA nTsSSi4OJtGpP96XmayQIMFa33RJEjSWnX14vn3NXHZcOMUXSIyj/kUF1n/ByyADCUT5NjlFeDIb m7AhISgpXQXKH89MHZD7FrgPDfRZuQ4a1A+l9ImRu6wOyUnAVnK+VpqfZAQTvoQw3ZgQ50iyvNFa vjQYvvohuaMuwoTXuye1N+pfALSKRSFFF5dabvNFq4ZvGw6WlGgJZG4jCSBhRMsViyn5eYHn0yQX PEfw8hEcCOLSTYqH7+nJcRNY9DirLKIV240PaUi1RWXWSz1FCQ4roYoTv3mRd4eIcmshZ+l/U6ad rB4Ln5Gl2Gc0homto2OGtKVVrvjofMZuqQLs4hccYQghE+TXTsUgs7bJnokRTWTJU7bjqbVRWimI i4ZXoEbuuNCpv+Dqum9Qq5gIGUk+OZ2qLtSaTJ3npcLvnzZBZL1yEPgODWMqpRu5Xiuaxh80O4ah RrKraZlTii80BZvkNOw77wLUuaUq3GhhsitnrTN0lpOeTEIWlAtkz1ARSflRjjhjfVu+4qfCX78a bi8iAxp7u0NcacXx66Bmer3CC+slVoi8nCayE603tpebfSVMNGLTwtMGmUMHX6g4om8iObx07T56 Nx+HZnOm3JU0Hx/sUGEQymv6wh/PYJRDwbMxRpeDIojDpaZs74J4Io4PA5MBxfYVtioqSMGZZR8j VUhTUw3CWlz/CRJmxnPHhVFvqe+YcCWdR+tF4/ayqtFwmhzV7BGXft0DfkL9IkkEKOpccLIXSzsM tFAISxCvPgg6+7E3LVJmQ2w4FlG52y68Mz2mH+YPu4jrOuy2WaLYw19CcTcDvIdPUGMGB3SaOqT9 nyz0PlgwGTKiZtWQxNFqN43c06FMTETSKynSDuTGQDQZo2YyqoQo/Fvn8UEqupwnqA16zFu1hFmX 8mXKbJINquy2o2OTI+kPfbdFlw0O9hZ4rpQ6uB7kFyvL+JUN42Cmo8uwiFdvw/RJUV2ES4nH3/rE uMBT+c8XzWqWEi64/603FQwirrm44sKitNwnEvpx1mnng2xZDkimdOdbsS2NVBw7ZEgfy/Sq8uw7 4WBPcmWswHGbkN4txVYuRXTXaOq5i9aO5PKLunfYGBXMB01ZSjZ/5Q6EHFmKNEGk6N8nwMTLLkKq YYxuuYfxOP+PHhF2DQWD5JyzENqmSE//6jRSWl16E4GFsSK0gDcH8DSETCKo+OAv9usaNRZXNGNg lswGzOWSBqwNzxvUjck5swc4lnFd42dWjiYKDhReDcDnKht6mvkWITDLRQrsCoPgH9bhGQ3eQCj6 EifRmsyFL86opOgx2kfRqPW6Ge/3EGR7pNK6xtoHAgmC2Pv6Me4i/pGvUGI1J2kiZZ+4ePaUsped NcQTgha0nERH+trPTHJDhWUhqmmhSHMg5eV9/zbrJlRWFy8Gb3enBe8VQv2VN5SCI46nZLRgdVQb QqaaovFUtu8A6zZEOUjRtIb+EYYHccr+d42D+QcokiZzqLbY8q6hp5CzWR4F1jOROeINFbQtf2sz CxmC4QMXGnHclzZ6SWZxre0t/3YlgIAseaApDIqDECEEcpPGeuKgklHiWACFcrnTVAL9MuFkx9Fy x3Tu/ym3EUubWiGgMKyLAdHL+2X+bu9/aTN6afAdKDOZFUEI0QRVwbKy925Ym1EkrAl18Bg939Xm 3aKmk/nvpJLD1+frwKkrN4J9/PGHxKCEA1IQpuWTpyNN+iXQiWNJRNGZ6hc7VoCzL3+CkxkOALSL EboIL+YO9iVJ2e8S7KVkZgvVnJelcS/TYbypJR8lADmNK1VnIL0yOZ+/4dtWtcf3Iyrb6C7FPD09 z2eCO5ffRkVLzgAf7D1ym0Y5w1i9wrF2g4PabxB6X6buc1/x9WLvl+9ynnjujOgyr9aoA2oxn9VY mGpZf7bhH/zSuY27AjDGPi9GATVQ4wJRz9BqpltLBshmNr2Fj+rBphhFgf1OuTw6x7F87hfv3H/m 9cZjQ2+LcXnesoSchEKdDG+zaImtvuRfs2f5oXvIy4CZCB0lODIiL7k66YzlPUCOXgAKvQzo2X/0 Jz4xCg1wj08hUlccNvh5aEFaHPdyHcxih42PGjFZaCWfAOVo7ykPFUZMJcCPaLQXbh53Wi9kSdMC Tyi459YOvlwOHOP+Xe/OnABi94/Ky5YCmzFrBwwr2LIjWL5e63UiW9EtMx0Yqvm5TWYE3PgbZ2Xv OPEnsE7BjggndLCQKGhn8IX/qA7QNKwFm6nBDYTYVnBlPceZa6KEMRa/FQjYmetGY5w2ZDhTAd1G kVWLwgPWbFxsPBx+RlmWCzEdK4urEMxAa9jMWqhYlqvFqTayUviFVrIg7dLdSQBHVzmirxaxiCcu CIMJxYrHgRiZDym5Kw+qLITi0HzKfbJfauAX6yyvdn+3JNzspzhqY4dq4zV1skxljYhFoMWeB/5p i7h6HFoP2Dok0/ce9xasT80M4hMYr+7ajIiMXUdJ3pg14rm+ScdpIVlATZ/bVDYOu0uwLEKBxkAS eez/6zvnw/S+yMC/btpDWT53HflFt1iWTcwko3r0qRS4Yl53OdlH0z59aIDn/QWt2rs1KMbq6rqJ FfoUpSzekclpTnOLCwKTBOAtQGKEZdhLDe6umb3ImGHNCBt3yZP3htTZLsx/6Q8znKgtqw0jSWGD bCcvQNt7CW3C9ZZhOTFKWAE7TlXChfCAckjrfTE4ouON44RVkF5ErrBxB/tNGteMFFx9VyufcRcb TA2/AB2zdwe0owxr1IUBX38VdfV9U6SkjN1siwKsDkGmZia8CyI/HTKL3jTjJl1psn92bxFohs0e 32VEsDhu4dcrne2eUd6J8xqd1D7VuI4f4MklcXqtsiX1fukRGCFXmoWYWsFcPgB9CGJ7VKpxh/83 OvPnmYMWqYW6sR3z7fxsJPkXMfJws3KnwwodeiDHVoplUZOwaKelpd9Ty7VhphzfiHyRH/K+JH/g /gcpv6ZnyrwP+GSgPIaLTe1TptrUh14BcDBxtuZmvVUfW3cZnfrWC7I6pGjsdfQS/i8wUqEqp8dc arwGhvGREtxHx4E+d5dL2ZbzJDFUhyZW+5KtTx9hqnNChzNed0VOBP44xbrMt8RhPg+wJtm0EzJR t0tTAQle9SjMU+hN/qhLC0VjF5JyYQosf/+wujsQt6gGqJDezK9B4ac8vXKW9lp6lU3whLI4vcgZ 9E2n2sslAd2BglVM95Z5aij4k7H+XuPH1LWHXrAl6RjTp9cKhOH+GDoIlszjEStAuH3DrPVhXqHk He1jJL9wabrXoJgiYGnNpqmknexl9ByRQlXXvQ4d4K0nyMQ55VcHMQWg6vSojxwpoI5rssgDsoq5 eV/Xj0lR4W7h6FRk8zIwVSn3gUg0lN8W7ZZvGj/269DDDZh/QLXJUwhK+HNWd1kxyV7XAqM7eUNu ORIxPh9gpBQFfoiOp8JvrWRtsGZvU/lBaWgN7HdxJCd7OLXuuOwPT23FCgyTEEtHv2sUMQ8+AofE 54Go4mncJ+FTMN7RBwvWPhztOwDRA77TSfUhydLUQuRMBG8lKtiTT5Pk90F/2iOdxuyTUQkylSH+ 6sRAhn1WSrAIiJVXuMxgJtGLlqT85CYsWKONIx34pRSMOo/RtoJNA0MlVl0V42hGVeJJSmxW15LT PRYPGO3nzaxAHJ1PqHB0anvm4vUcV3WX42q5ec2kWPDRvwiPCGmD1Yap656QVLoh1ilZVha1lA/g 1jnqWuloB2fbZQmFWitlmYpXyWt9jRdyoJ/a4otd4+keDog8gVn63guV/GPXj4BxnhUY7sqt5QvK ADV8SrBuIPOrL1jrAIg3qXNppcEU6rIe1KPi4Wc9Dm9CJ/6gUmPIVDo5TayWQRtMMCL838zFH1Xi wi/jLGA+6ag4wi+aN65ZQ+h3LH4x4t3Vy/82IXOldASq0XpE3y7I/MXajwkBpD1os+1zooryZg86 9zq/aveLXP1VIqRON20agsM3j010fZki9zJH883CYSc91LYxGl9hspIBvm6u0WpCiNn25DA8hNZI 1ZRXQnkdbpnLH4c6Vaj1c68alG3Y8rqcknK3BjNHm8DK5/dS9eHco8qr4YnAk/mhnaOXedhu4zgA 7g2qStHNhwhvP4uqsnsxzBJXhqkv8TdtLSQVJ5ac8p7CX81SgV383nlLpCyglRTK3YZC0ux6Xjeu US8JpcMAjJa+JPe8eSZL8+6vgy92kWCRRCjZtL5iY1HTXmB9KwaWKbDY68HbAs+6pYjs7ry8InBS nFQk8oLiFEPxIz4jqgRqlBMr48aNttcTo0MbJpJMt4zzD+qHygcHrU9aRJDrrYo9moapDsiF98zu oUSfdlDNrsKfex6WjAJdIk1Kvggj0ARRMZo5zBDKImoz7AxHHAu3ku1ggAfYaSI8u3QtvkwNj44A Wt2eN0OzYYx5833tqy0Z24ynuojgSE1OGf3CkxXZWOoamIyY9Uft7iJw92yWwq140Lhrzy4jYTLC EfDypYJSDDqBuRR1SC8leNZiI2l0Lgf0NcU6A96W63pq2Gq++hgUUaMoyvucuf3Ccd7ItOzL+VMN ecNf7ZphAby9aW0gsV73xZ1FGWZG4VyVDM2K2W+Vpv+BlcJIyDM9L0P6Hv6Wkxjqse/nTcBtLN54 aAXXKmvcPUV73jQ0ZrlZb/CNJMvMONl6CuM86a2Lhi7vbNrJ+DKEvgNAtvL5YJtIdU0z5aEayy6F a/4yHnnb4zWVh68M75FU3Ve9cyFssYZYOT2wpePafA6tzrXAgL4Ic2fhMgPxhzMnDH3LkeEdjPAK ozdcc3Ou0jNUE5mZJWJ63YVxd1Sfo0FyrqN2ejjfi1E+UBjnWf5Qu+CsW6dsXbFpFdjBqLPD3yfw 3P2WoYjJLD3KgrcLqG8DFor2SnfF5EM+J1sGPJXHt3VGPcweCnWjZuhEMOtFD+po8dFBZ4qBHkDq uczyB3rV0n/Dkc2CqRGieGknJEukkDe4X4fak+cfOaJMtdeTf8/5OadAC48O0jbeaHeYEidgOnEu KlZDvAPQm0gh3Zt7rGMraXk3wfoaG/zhfvUWiJSJPjo/SaedNCGUN8Nz/tjeKWLpvChRctv6TgO9 fj9bGhhq36mYZD0CWBCOSJoMXqXuzChQ1cnf+lXJD9MudiyUn2DYDXNj4a3GQ6s3wKABdb/9th1M Sx3yLImAvqZWiYWXn7FfiqnxWUEcxKfZEQ5Xzs6H4f+GI/W9r98i2BLe7oDzEXpW5kL16b8az9Mn 0vTUnl7cLFWWI+tzMOY6N2XDpQ4aOoGhNnS2fcmIVxAB4kNl7pzsvkkq/EMDY00Ilr4HDeMWoh2b MF6ZpVgIDzADQVK0Y1cZPVtNpXZ7OlD6xwPiWtaACPS6Mj2mgBo1tEPyyK8rxMNjDwKSR5xAgJXh +P0KEIkwFPxL/IA5VyAMc92KW33eWTwSk6/o69R7hTpfRxiYY32bEQx4mG/jMmnnsH+HGFFE4qBX 3t1fRGS7xUhxYBu9REE7lCnJE0YJgGsRARvTIzit9TCqz5XLBS3QIcX7he/swfwuFX6gkBRf4W3i YpXooFPqSi6nQ1zl+0uhGgVDwKn1+cXCV8vA3dTaPT9VpgrgO17ZdLMCZ9c5XGdaZvK7gUXBCbIN tU5EkheE4hHvvtYdxXMN/8E9jY+ovaxfQVA/HQyKFoZzIn6XGp3/B1s0NiVN8mMGrQ+NUA9YrhEC ZyNJ2obizLoqzSpPL7Xonm2PzQW/ECzTEn+ZxXcqs2ZzXwhDD2d8IT9r/Ng6FI6p49cVphkifogC +ZdDaeNEGsHGeH8tRmVgV2AOWxKsoxAJfjT9K0y3tpKS8K+WCHdDrYeJnFyVBf5GoYvyvl+TGaZi xA8tg/83yPkq4DFe6RA6HrBYDjCJAfHqGysMOET8bPeNYV4NxkfQxMG0vaqWeJP9Bahh0ZdxOJfz VOo7EW07vGIqOdz15HhKdH1AGe81Wi4ZXk+oSHM5+px84spX4TpZteDqCrhMuOTM1pK3cIr6t0hF rwuhCoWnXX0DVtLedzJdWutDKZ6CuyEJ7R+Opk1RjT7Q+19xOu7TZUsVR59scGqhxIQGvcz5eH/4 9OUrOc/ljrk6K/Taghb6dlFGA0On44Tuxey3buRSeShsP6/M3qGe6C+4len1FnKbedHh35aaruOc GI7IrK5Gr0sk3QBt8j3IWke7cw7SsyVdBVOCEU04nZnE7YFfflcqYqmMDW4fUr6AaiyX0rbBle5x ieMt/5r1NzHPrW8T7HR/FemBPjddHHOu8PYn88yCicFCY54NEgc6zQd++TmQ5utm2iNdB13+IxE9 BQwXspj4/kkcHIFanFX7VVmmTqMzjQNWYfvipyIlc+N+FGY7iDZD+IP8FNS+ytuc3wWOSbkziT0X iWzkAyrPnf0WY5Eqx/vqCtRcobwqnrfrhlQe1hWh/TLCdt6/q5gfYl2OP553kXVFjGu9gVuVyGEa My1c7LEz31Df708jmMwNX3ePcB3Dbdhd+f+DARkhjGSkGOSFmBQSV2V3LpzAkprb7dwoekmoQGgG H1eJeqEUP2vLnM4ZinMetLn5pZ742tHO/S+zsnbDktlwhlza/eBljvFfk2NtMNrariQ1Zs7hb858 i45uo1QeCMX5sAbmNU86cdY5o4vgQaoEEtWSSFS+kWcoOSGBuF1FXopyrA5lLcVLZ7sIoA5bx+gg QKzsbO3+yLIGwLTdDrNJr+ymhH9mOXQ0dkTJNBt+jqtdQOyqJInU49o27f54fi1kFgi16WhPAMka gcu6o8/rajuV8VmYvEUHfC6CHN4FBhgr6dmGdwZBTpiJCGfj29v6sSl6+BzREnpMnRurvTTcFG/c BEKUBuiyYOl8sGtbI1mzp8hMVXvRrotLForjV95GgXszOPjkVVygObrDQ2hGXj799XwErcusODio SvaUYvP0XJgsf3Hx/osZP91IAbuyCCbVbOHe9GXrn8dL8NWxk/qtlm6hPRs3PaJoP0J1BrZy6hMy tOl2i+zl4ZtQQ56GgRMTLquKp+oc5QUKrUVb468JTBmyFdOCfEJ7FDAj97VvyD+nYUipEHfrJCiI axgagVeyVdcM80gdNNV5KODMVlgLTwNm+WAKn7ndxqmD1vrKIFx6FbrUvR8+iVxYjg0MhDY4BTua +k/JCm0MW+m7WAErMtAb+Sn3af461LdILLTfnVH6n1NjakcbQj6aNncF7LknUR6PvscGPHEuFsth ckJTOQn06OXAjHiFxVO59fQDFAQzKsGmH/7J2dt/bfUwVPJg9HZoOlULMs1VqnWzT0cQBUc90mLk s0KPV+5Z/giw/0pWMjxkht9X4o1Yz2qOjAABqcOGEuqgB+haCLfP9QHWnqZvgNVjbfjGIE2pk7by Nr7kIs2USylQWn5erUuIA1jcMVAhqopS7e2Anm1RmPwZQCxNKr/GTD08JEO7dsNoKbW2WsYk3d/n f9tZcv+3UvSQdUv7d120Nl0iaFHrtx7bsUYJasLPr0Lwh5yt1grSh0yGM7WmPyi+3O70EPNx72wA /wJE9Qd08ITZAI8F5cR4FyHVDXNMLpIc1b6rJURFZLZD5ITsNf4pkiPCbhHxYJaJ1wzYAgV5ybb6 wgNY6DoT2El2+AUHAJf85ftdY5+7983qOnKHKy++4r1f/H2/DpXoJwy6GfSJY0tJns5K9yq+Bec8 /eZNAsvpiY/tFFrepLCoAU06GcZE07lTAnO0leAblpkIUOr4Wp2g1FvewHFhDQboHAQLs1mAfH3z mjqfpyuE2MDAW2DG5wnpfv87toF3SlvwA34hy4mIAei/uJJLbQIsPBHEe5HmKtVwG7xKpdWlTqoN fxixFib6YrQm1RucDzUxzdO271uxNBDdobD7aG7sUGg/mGcdXdsPL5W5iAgqoAvX7MdOLCQu3qVq BKfI2WQTAOXajzvOfjKxm/1Z4Wxzv0P1Lpr2cF6XEeaUPp1e/xQQ7fjLX2Bl9/+Udp7yuNtKVjNN iWQNgMgG79R4OgfFQbQgMArbXFYBV5sb/UE5kxGhuFiy79FudO6gGhAGHBiFrpvv/qPGLy8YnVUa 1GVVm9Wlv5u8IayumGndKX4P99adPdHuZtLtZBunrmezq/zzca4/uB8azO5tJL0hrYaUzW015D9S YRPBMMHULJMcbKc21xRskeZ8uRzw1guBnt2956vDJJMrmHcC1KgJ6Zcckzfsn338PdO5IQabFoaU uAlHx0u4O2Sp5coff1FM7hm2L1sG/T5ctTLy5lvFA6oa/8UmRobjTDP0ikJX4yCjJYa3rnYZOPbV HoM7iuRjyZSa/v7yOdvokE/LPLryKG0x0UtjnnGCmf5vOjPMgoKEEOkNLTjO5kzBQmvtPdqy+0B+ wh1H3bCp2F906Yf3XxlRj4JbNl77mrCY3apwmRF+7Brz0XArQU6Eu7kC96QBqDAUQb+rltYiVx9n nEICz5gfwOKfxei+pkYLWsDM8LxPr7q4xXhCAPeDYdw15WQqC0Ogrey6dZLBNwdxgi7vNjmzUPLh xT+rEAmF6k606kJQKHRFu/TzHBdC38NwfTyDaccq5U1UzRxXwYn+AtGaDR/NG8mcXOiWPOlA1ggj 286tiv+vbGCvHjFWqrzRc7aApViM8dhTW43YhBMwYhse1ku3odECc3o9jIkhznkuNNdExIYFDP/R 4PlfQXPHwcowz5SwILiIQe0EBXesHUujWa+OMPAnL3RJ9xt7/CbG65W5vNVF6yPOBQsbUxHbh0da HjjBEvfs+acgJIFREkSy7OU68gIjKIsDhjU0wAeV89uC50gaBI7NK/Y2JBSJ5HY5a01a0V5F5uuc mtnOjoQPWMQPkYnonO08VTmIgmExRV0TSF9Uk75QUfW4OIahrh/1+fHULGRZJM4KuxL3/jRcfVlb eTv8AmN9Jb1j1DWkSrOQ5yQLZ2cSsIlNBT2IQiSzjXXFa/VodW8ubBIhe84NnhuUxKipSyl2v5EL 3MO/E/iINyGEi9xayOuHEqrtUIUnu/QK4TMkxcFEP9mehZvx2LuMnpcTcxmo9R6GHk38BmHgv15w yfWdQXCdKkmWs+Q0L5AsK4SwG3CGCneDupD/2aJjXuWZthr3LxYL5SB9UoX2H1w5IN5nKlXToNPF Zvl5JyLAQU2IusUVAGcPIaUCZYk4GXRv7Cugd785ykBAhijDwmE0+pHOZ9DtfTQ220Fq/ioXf7Gt mNbRmkuJPI1WLvU/gHINYOJV7sD9aS6wnWneNM/pzQ1YkgDunsWnrIKeVoouzhvYbk0jirEISjX2 44SlIGPauN/nqr523TBN0drJq+clRsZ3t5Ej7OsfsoAwKX3akaNXu07PqiSNG8UtV60mn0ASI66S /HyWngiksXqUpKE0uK3g9yx55xgTES2EX2eWW5OmWJDPWh4GR42sjRw1IqxT3+wQLyLLT4ep1Uz7 NvO8Ix9DDnYjV9bQak8DpU+STIyGqE+jt3PZ9uWzFUZuMxgy98gnU0Sv38iRg5Ahb6RAOg8Z81eC eyu2w4qn+dNQBXjPZ+uAAAFFSYF4KQBtl2L6PJO/j4KCdT3e9Fc5++Y6a0Wwxz4CkaqgmKAwtV11 ksL6NmiSOrSwab5A5lPoCkEAoh1yb9kxmI5olanKPx0aVp4yQ3QYa1qlLZ44y6x1FLnQc1D9Jykb N3vg9AV6JMyCQJd/01nw8mtx55XmHFUjQUXGaPtNKyR3eOrqxuhZBgprYoKqcf8Ft9y28KTIo9KN 4vY8GIklFtnn3bOCcHaPUnnwH7EsTftOa1dHTy6x54FxWSOhBHzqe2RkMw6VKFcuqJIT8RQ+1PCd 6fBkQd8f5i+m2icsQf4nV4EEWr4yCrujL3U4aKmRyPnJp3zdwKJbR9rcwPP4kTSOnL5PZyywBoAV fYNMEyLrjwtVPwbXJ4czG5DiLwiKw02hSwUa7o73CO9hMJw4RLyoi8AOTqVEcLgpEU1cHfcgpvzl ObJyQI8f5IAI6BZX4DKXLfkvRDi0DTOCBOXKd0csPzhS1zaJLnUymhi936KKygWVT+Ox6mXJjVNZ wqiB2CtOXEW7qKm0JGhNtM+ThpGp0ilPkieZqmgs5m1JMlqozntL0c16lCVyyHLvKC28rZxrCn00 u8NysJkYClBqvjk3l2NEgYM5AclwGho0ZM9121jIVYNUeD9RHlmlXIWlsA4cqvLff+egTqKmFui2 qfZc75k1pcECp1HAlUUNhIOOE0GGSKaFgtObPjx8jquRdNrRuSFK7lefxm5MwpzwLXsT7zuqoZzQ J3Kl5JdLpOcg7VpVyPjKWmGw3BPvnbMOUVOfzTPE9kjhZhgrIzFQMcdZDGaIQUXSyYKpvWtqcZPB ypF05voY+oUEfdw5sttNLk5maxvWTDAweFt+AfIcZ4Dje16M7DMfJKHWAmGK+md0Kg1Z4jk/A+ZG 7wu91zVAP8ZJj52XwdY7R5wza517KmvCvfUCbkMqMp8WoKkauw4KztvRvlcN4xhGcY0qyzDQM3lm teBYBkVfE78sXB2g38kmgdyEQFxP//CmmHpmGNHOpu+qfuFqoj3T1Gw/SGg8PJ+bjAYHS8Wa8ilC M3bSbWjdVx61jeNShfYWpkQ8x0JPJ1hLwue6kwpjC0Gv37K17HN3o604TNhJo8xEPi27m1ugfO4J PSJXlvB8xN1a0UPBFTmbc5+3VJ8FhjjsUR93cY2fdIzSmO+oJTENIodzg1OCjAsM8OlqbN+90iD3 ippzyNG3cAnxEWu7rNyRbzeaeWwQA7jWIWL6BQqP2eq9dHDqO9tpGWHfhAWwXvddZZrIBdgh5mtO /lNAdZWrC69H/SYgWtwn/D8fap3V7PFqdj/TdOgK5vE8xYM8VpPa0EmuZNcDDMoeG1xMc/8Q0Oq2 /Ql7+BxTBxyG02qhO07DkQAow5VGrd6vf7GWbOBAQHYckN31lBhb8CpHqBuhGi5y3A/YayrvUZ7m MYwxhN4iw31IXAkzDZArrsoy/+fnEQXGoul55hYPQvHQfSC3x6hwrJ6I2GGIQGq35d+NLjzO34U6 d1hBNUM/HGlMapEbmKTsKptRHYYlkyoO5Bef6aWmzTKfHZJfcFlzC6W8xAZh4HqusmqWX2k69vG7 EuH3gbyTs8VOGjutskaRTuUNWTE0NkfIxLJWD2303T+hNqk1l/w6rdM8KlJA8x7uVMFxSCQhgGAE qatPpuz9GsYlxeijqgP1RqJl2Q4MU3sg5UG7W6Pb57BJlTObruFShE8RYL0MdCuEN6sKKwAx8lUq Emjn2CvZB5nckclBh4nazyFYhNkiVGJKjRNWtHsRhsWE4X5Y1b2kAO8ezatoBLXMit+8akp/9b9p ZOpx6pdm1Q1snRaCwBYtPlKGZFk7f3ZhHlP7dOGk2sFqTpGccGzPQIKQtHSxlZaBA5iYG5yYI0Qt T3Gc6PoNXg5NebzLzEkADOizQQi+W35SkQSmNbfMAE5jKmF5/3hDDNaCZTuzb4uZ1uu7prxptdht UczsA4zD9RSWQpvBq8mK19RcENYZKLv0+oHEHimsvJGQ1IIjC+BV9PIrdn72I0kS2UJpPjI6yhXo 5fCkI+kS9pRyGFWPUuWjr098xxW1wMPug5JUrFjf0hDhrlrjcMnAeVy8wtdKgBlGme6aQiG2psmN ARuhaibakRqWBfQRBNvNR+tz5gHPk63C5D3sXFecUrsngGs3G2byF1tRdAnhFjbxDN7f6ebZ5Cfd WoneW28WPQVXdqndyGC/HzppwexPnHzIij89Zku/4e9q8SFZuajKaA0tOwkE7+Z5uz1EIzW6o9Ou 4teGM1sEgPNKDJ8cRcWXBgyH6Et+duYXpZcq1y1oakkWEX3bFrxosE/UxihAUKKV+ZeYORrf4c1d brhQxouA8fqMwGEqzdJHMNLUcFxorj1C8NqqHTzHkufrMdKpt6YhepXnEIPGFZ/bPQhKgUXW0iiv p6cx6Dag81VuVAm0pOskW6Vzbiyxkij7d1GPO7vZw1rUkoSsFXNnTxsY3IMVpvepyv9cDClww4C+ WT42oDC+U3vsGCZlB+jOe+nho1cEZDkhYidOIGiaEWQK1e6ofOTT8ntNBi2egnVSL0nr29QdkDKv 4IHVR6u/ALKqdNzEHjB6p/X5XZbNn8E9siQdBkJXNApVQPvNLRIL29his7OH5XuaGHHE9fLG8mBX w9pMHZq2E3n6m+Ha6yDWf0W+i0sURmSOaszANfVj8nuoSBirYCp+cIuzNL0gkDYfVjdJMTpdm15V 6EfeRYGE9XGT8eZ7lHHqun5hM/jsmA+eQGpP5FOGU9LModsm28rfs979HDw5zN6oahd3kr8lAjnE J0Mu9pZ2Z2mlj9xZE4ixg5a772Wi60mX8IGjdwUDJIPPNZPbLpsSVKWPH0m3Qo9ybTvSWaZwha+g cB30HVTpIgzJAQkjQZJUYWZuIg16PebU3dl6IzXgqM+cv1k7WXD673ELOi0bdRAcgtHO8nbZnvVv CgW25VorhmeTZO1C9vdXxdQTZ4gzrpSDoWf224XK/2ITCzWpZQmPIhXutNni6rvcuHuYfttBOTfz wVniSEw8HEhxjuP8OYqxt+UeTwIkB9nB6Vzcp68v4a4NDLBDct9bsFSqh8a2aNWcsVWVmeBfYAwD 8ivqfaTz6S9fI2lcPuDS1ito2xh0EGKvvOCcOlrn/uK4Pvfg17wO1BX3e8TQjg90U6KLpSM526GV +GWUcV4rA40t5P7XvHPOF606V76etbvrUa4mBOMGFMgo/cQKoKulhQbweFPmfSuulghR5DxHZey7 QUSBFrg5dm01eBRz07+qhyDbWqnG4PbWTUxE/LHWJzZFwGtuIETcup/5WqnN+22qiqU4clbAsscp 5UAQOBJ9ConvTh1lUYLMPwDWey1lYSrWL7faoHDl1VKr/63woNnBkL7lhdPTZ8l48NMWCpc3QuZ5 eD1S9pluO+aAQCdpdinDYiYLa3mm96dXo5qWotKPsqQ9k3bu7Kciw/UTGQ8DuyafdrRdYD9oCR2Y 4OO3G9fA4j40V2u6mxYpLD9yewTvL7GzqohPaGIzpioXwrUuryNKxd5AXUvcLIV2Kr9CewWORdTI 53Lz0EnUfXQzMV6QarexTiQ/GRIHuAyNy5LzOkMrBnWnPeXtEZ1/qiu1z+QHulwDjrUFggbWwt9T ynhXcwsJnT6FamRtgFXTAeP9lv3Rhz+DMmj+HWYmAgcKLrUZ8zO96nX32GKEpb6OziC2vm2TCGXt j0yiNl8PsMk193pQfoj5wAbeI8fAV9PIPOQudbymu1N54Urz94+ZS62HaOYbVpuNwR72D7XPMza+ PGnB/yZIciwmeKe1Hcjk7CB2a1d3SygGQSmuPveZKo+6SfukhMQDZ5VBpv9XwR8kdWjgrrK/VMN7 voNTM6PpqQddj31RCXJzVLeSYMqfzNZKML1/Is+eii3IrnWTLJeXrhtXV/tO4BjUvY8aDKfMsTD3 uKYfOX/66ptErwRP+IUIo9hi3WEXY2sPA9fZ+dvoPjanF1kXVA6Dx1eaYqFsXB7RoqjIptEaL+5e 4547wZXr/TrIPhu2xBw0aiUyYlugoiP4yqu4HpuYmvre82HcVm0076iqJXWp5bNOCR3HhmjAsmWd MNNYIqhX3/3l4plCl2OWKcN+VgNRD3O25HLO87GXGpSh3bw6rdpSmA8X4IsAyE7vjvV+cmv4IYFM 997s9uT0rnjtjT5DkiM+RbXKQVJz8w4yY44L37dR9sLP1yp+c62HoGAp1XvQywgrUS1d2Y/2y4Nn y8VYDjFZwQqcV6v+iOzmoKNBnx1yxnUVkrMgsGLjky/iGtkAoV73kWx6IaJWyxkK1Ud4U8+D6Wle JGjtMQP3ME3qMK+xnPqnPbYETcnu7xSBQkobeEg5G3pcguNgh8GqQN/o4+u3bFdo3ywO2fJRw2r0 wKnhjwQQSpJbjJnglz14D3iEmLs6pTQNCXBPZFbiuqkzpdRFBzK3yIrlXe2Y0sUb4ckFmLcYj8xK KurD53NZA+oaoISKrRYGt8NSJoZw9WPkx4T6JFVX5Y2ekTExzg4oxWL1FhiG7U4gmvdviiisQsjj U/igSBSgtGIcZzRSw8C39FMZJXj/YKrIIKJDvD8JyugJHexCZc0+sVCWQuN3vHmWl8qewQ3w0EuW HJCgjCc07OE+yNXf6ZgsZENvYxFuhto35w1cFg0/RGNF8dP+DQCeWqcKb2WjnjmqK/XchOpUp350 WhqXMJS6PK872ehLLmoJvDQYRoLHqrm5kKAx8NR2InxiOn8q57lXLHt5r60qys9rMNwI7y9uJU7u TtQDSqHTTYe4m1JeEUbpKBw2xraB/r5zZ2XbVMTxLfPt+tHyGiq9JwOf/5j3uHDZJYYtmc2xnV3Y o9/eUvG18neDou41FAAeu5VIRBWQqvs7KGXnW5viJl6h16AJT0iKf+cfXULy9W/YYqFPZLEn1z7y G/BStt89NjizegfagW6pRRdb1rAC5EtPfT7+W9XYtk/muS65fCW+IT4yXkS2Q1olGISsJ+Zf+s2Y 64bWqB9NOQZKbYooImwVOt6/K6iaa/aPS4dWi3rSkybff+bFKUHay6PJfM52/JDJlCdnjekszQUM zKiiaSGBgJeMt2ZkmUsS5JNU8O0cPOxA+QUGrQJxLffsAmsRv9Kmdzcqr3+gKpsgxRCnUsaCcBXd mDwKAVGBeUcv7ol60T6ye1z+5oGNB6ZfVanJgPTJ27mkkH3osowHjg0q0Y7z3TwOM6QExsGB/y9O Pi0R8+Fx9ZQfDLKzAdMasTK/UUp1Lrx/fJ3dMdhdK1Cq+H70s6PgiEyrMCmGVYFy82sgPCp88eR2 sPdcb+n/O4FFQlPAzwA77dwv6xvq0UR32CQ3sABM8CZEzSPqXJaHbW69C7dZGhXQRbucXhqSYCB1 OZ3u2d6TVHNvmRKeDYS3YlWApG1Ji/O5D1fv3GvnUUzi5f7gtNMcD+sUQXPM6ThxUt+ahViudTcE n9Fv0paUG9I1uPstcNv16muV+24LVUS9WwW3be6kCXL2nQnLIVk3lFmdbIWy8DpxDZkB9DwKqPCm KMwxayFVPAl5MQ5S35sVcuXDOCL1W3lU1vz+hMVNSbWXD+ZfTIMP7S7h5Rv9yAIzzeorX95QbzR3 iJzRqibLqKsGOtL1zZWS0oS1Lls+k3agCOQyVa9bwuMhPy5yW5oZP82WXapCdJtoxMdFjVDdU/tS cuvYUlYl6Xziub+B23NyyRkLWw+cPfPErHDeVXFCzrg1EwpX0oeTbX6ec1xJdVCXEi0KJJGcjBQD 2shVbuMBwlzxk13CY3c8/1k5XN6z2nq3SHOrVMDIHzAvyFUrawXep7/JOWgLqgUkV8wmZF0oi+YM XaNjFez5QvkQWqm0Lf7J0Fc0bmDk3mjn4qNka9eLtjZjn721IRkR5cdHsqCwBt2psYbq0Shm2vWw QGWBxHWPzOZ6KLNmLHXseGstqtDIqiPfaPtDTzGHyqb7HgWPQ95Z/L8WJAemhxQiBc0r0NUNtvmU OdQKHmUHc3PGwyhFkBpc5wN0sb5MVy9y20e7w/3qwQGHAbfbzLi9jY6Z7uLuI7ph/6Gp7iBSQdtd fDRzFEqL4zN4xcoY79SW9IxfAKh3d07ovLAEZeaLmjfZZbBd6xGQheiRTcp6sbpaZhbbxfjdZPPv Jy/VeljmP9UdYsLFvm+33OlIT+3jEdoCiKsAzUM/8kF+ywTfFiKvUWmtPcTzz1XdpSmLp3ChCZOR aaXsM1AUyl9nOdnWklW9IoXjS8lccQBaqOhiC/VJlJrOJJauI+wyJFwkLB1xxYZlREq/sIdnRKIA yYSoCd36uxkG1R+P70vzC5tUmV0RbJqVI3OyVuOoP/1qjwBhnyhIpfuq/OvNQbTwkk2iZ2nQEzf5 IbXoaLj1ZsUYCRMtazu+8NUumSaVwdDU8AFBi1uuMDUF1Wa0oUXqQYOoZneRpfDtjISgB/i/GK4L MtVzZO+5IMVe3DV+PbOg+n2djfa9muTB9Q0wkOxhv0WP9MCcv2ZQtJ17vBGbuBh6GfdBGuIfL5RO WnTSHLSMsbLT2ERYeRnycdKxM6LLdtHq/FPzZSK3C8SEjBAMFJmeQoFGSlu6fAaMJ5O2OtNOFx1g RFu2ZGTYE2MjbowLM5Y66KWd8FowIGyqrcTP2dNt2MRezZRBibRREBQIWRsDDbgGGJBFI//YnIfG X/oJjmTbKIL0XRsH43uvWGQFFM9yBZtLnw1satApSBzRSTWVEdAkBlAXAp/E2ls8oI8xpkhA1Jty xsuNVpFxDHzOQdhwYv+amoGqRS5fW6ORJuWQYdl78VLrqcusnYSEY7d6pImexRWjiOj3Q4mlsDGW T9RbAbARqVawzYtb6wfbO0r6Z3kaif6NR/2B9GAvoYh8nu/YCsnlgPJh462bUlJFnkrUwWxMKv4I yhmx8mYAeCZwqzs1CV3xx+k7/Vq/a45OuaJECgmD8hwAXKfytsBFK9xgsQO9wkp9qh9Jbs54zQZX xwpxKJfQ9TyXn8tfdd+AWS3mfv89HOZFA+BL2JTNd/eWld3yzWvQqSB0beAX5VMKZe+37P/24zZh UjxXOD7LNS3lmNRIGA0hgEzHOnI8em37LuNTweOMot8fx839ANnpVPZfcaPICDyvjP0kClFD4pny 6pKLrnBr7vvzZ5bLrvA9i3vML3aEQdgHtskGwShgsEfolMWfG465rulJAoCYtet+Slk1ffZ2GVwj gFfWBDeJ5htX3DpRZrU7D2PGHXE+BjboObwuSxNj56TbcxwvBZ/lLpXfTQgAZr7p4k9DXRnnYmTr p3glEPsjRzJBSJ1KulmMjldbzVeHv22cC5zQJHg9ip3u31Usp/tW64Mz6IfhpYvo3Bm0L33m5uBy ub0BN1jrDneVqsel4mfX7TLQXZXCxlddH8c091xizdnIsqkfFLGcA1lH63OtMg5WAQddWG3Vlmc+ fKh2DruCDc+1KGC7R2xXrY466O0EQQ65M1Nr2B+mXe23fd3edomPDMimiv0MAxdeRPVwSu/Z0dKD BTuGmQvoDVt+iZttUVQG6YtMjgjyjxEyiIyrcra/qQZ9+4GgP6CQ//fmdmeaQdcDRdTl1idzRKpU DXMOqe7xxzCV1uRs8GKx+bsBLMi4oMrOsjHfUHvI8h467/IkNF3ntci9opV2rRkWG8F8cm6nAD4C UvYLo6awJHZixK9N5P22OUiX/lp6KNC1+Y3ylWuPsPKh01cSLymie02fxL+rumEEcuZbYA5OSuL3 Na0XbIdk1rEb2YRZQaxWWoC2HJOwyjFmL6qAL+3okQL+LOob047nTy+xyfMsZgyAB8IfBYEWwB2n VtgqMPUA+1B/GXUvSEKdiWwLHzFFV5EPtNVeA/hslDQ8pRuc2XnSqTxy/EgRWzn9k/4/GO4/O7BP DidLeuEQt+nUFLOhlB+JiFGu7w37VUlWEeCAZOUo5gO2uhB3upSvDd8/lVBAvNpZIayFyMPAUbMj Gv64O9dIwX6mZLgmWFroewAPSk7emw8PcxlcQAZbfn7xR395NxbbNJUvxGYKeLhvKfc5X8IS0PLU 04Y87HPmigIJstHEcNxy9Sud41gA+mo+LUw/+bwu1Y55cRAHN/SJxdtd/Z1uY208cy9UaXvZWiuV p+TdFW7fKaojiATDdk1xJFRLE1OCwgONa9zqsJaDeZVCl1+WZb6nYaWu1+/2fsrXtvDTnpahm4d+ 4hcOc7zxzPJusti8uux8ApUO37O501z+VYNH+fKNKJPOduBuBKWF5Y7HHpxhkC7JkFecOItzGBEe Ay1rPDYqiYnPI6kH0VlD3cv1nUhXoXLCywG1P/61l1TP8eWmldRfJkOfwRGcHR1+k3TtO/O6s9JB pM1kjCinLqJ2Uquv0FlDgglQVPNxxfNrNOalCVvnpiXi6Xolau7PCiSXXNqcACfmHgFhbGg12u2o Wf/ofCDdZCoXycd9rt7L4N7QqStBj/mixhSysmuiapjsYPTRvNjBHHDoSXuszAVE4PBbfsZLCK1e U/BfFHw6gktCBHsazhY+K+4v+4r9Gpga2PNCWjq6rK6DH/OpgbtUssYazybOyG195amtBfFC6zDJ 8IhL7EniaXU+4c1W1AW9zWotZK5CuhJuP6hWNw5EJC0TFMOkSsb/Hxcvwlu58/7gDovyUCv4zDvS syc7dKoHh3SsgzNI3EZg7JIzd0E4trLlO4Ucxho/6w/lY9bIwzH7jMm/EKOszwUpfOgTxWH9mT5c tvGywMWmhY6j+Yl9UZYIPqmycv6nBPpCNEJbDmVaf7WZpoQqdr6COYUa/DO6W4cJC4WcIuuo6NJW lQ3MjYd2tnVFhKc9v+9fwJqMSdLk3uTtVhF2+W/aUC9tiXth/MwSR5fF4zvZ5wIoDm5sck05E0YD SaA508Mt/awxbmUOEfu8XOyFB4ZUR8thJZcXwsXeb6i5xkRYufTNK8qgZnsLEOekzED59TzvANhd qAfd9xYq64DwZS1FVWAYvXHST+rmfgo2judeYWiKb3YEKi6vvv6URc2IxZjj3uyZHCgxZ3E8BzrL wnrDN2rDsG7I9xSNy2VYCXI7AyLsGHiBI5DsotM5Fs92E2mDtiypJThiRyVRwStyziv6mcqC/UKc FeH6XyFwMMfSLwmagCsj7aTUtjljuloJkjWa/4NC1elnmIlNpfb9xWUVWckTZpQQwrzjkPdUtMrx b3mNQHrKWWG+sUwsg8r3sCdDxAUkoIzxUL0jqwSEuAa4FNZwzx1p2p4VPZUGGTQY9Bo2UasSONCT 8CSEdTQwFETGKppJoGz+a/KqzTgNm6T7Sp3oEWuo6pLQJoRAE7qlMvd28SpplCYoafBza8s22zFA w50HXiGCFqI4GJve2axa2PzenLmC3ZqZiHeHEMIcXmued93jeuJQVOOArde/2ugfxP1mbDadoT36 Q+uAw6RSJyYYsLnoqaw6D3RDOcpIOj/XXj7Wl7RlUjYN/nHXuG7vQUnBjX3TFQcWUN1PVImbTPeB /neyo/4N1hpLmBVsGjTpFKcWhQjrN0PqevxuJSvk0kdo/3oCKAwJBHScKBXX8qjQjji7+Zo4p3Yf 5OM7ni3ego2H4XLCJuP7Lp1kxNJLb2gi9e6w8naKFs0m4b0KNBExxl+3A144Q68t4ZlTvmWpGXVR +vEgEcqBnV+c8M42MIvoGuRKMj+oUst2yIbr2ijVbaB7siMYQi/1BfmCXOgKK+8lORXeUplTeacc MG8lsGV7wyT/gyqEEB1v73ywGgrgZ6RKiCTNT4QEdPsgDYvs/pooun7axF8/hfq0CtEz0A8EiE+5 wigRT1P7v47+NaZDf2rKQMNrPMbg+B3DP5Z5oLg8Ym66ybLVkhcEFYDK4iepNTm8ojyrb35CMa/E AWo1PVxp347fnifjIBnEzE5O6kLqr1RGZkLaKUYrP6g55pFudV7RlJx6nwqdp8M/ruq7o45/0Lhv 0hZghwEVSUcD3T2z3JMk3AidWyMrEV0YuVsObNs+wR4uoyxEQBSHXc5jNCyfFfDSCfpWdgcd9C3v bBewxgtpj3MFxn1g8KafmNUD83FP5LVH087KEn2gJ6cE1vObHcwu0isZtCOGunPE2w1cruGFEPks Ed1hf9Sv5+87+alZ4MdiFJXeoqeNFm3hZMDtP3I74ADMNKHExtPf3O7sh1V9WCpTry38RdOPZW7C Es1isjD7q8HoeJ0aJhBP3nIq0eBF74Sb9CKMGSt8N6x+cvRAtc0yFDmFvSe3p1kPw4mwDuUoDCDC y1AfkssJeq6z+pqCyoUALtETANdtmBBEhAw6qZKDEr0v21kL02nU7x2gyFjlE3rz8WVB/7E1NBVX 2x4aBP/T4dXSi2sgilsr04PmD1PCuYvtIm7G+sZJ7MPf1zpoRYwuv6zToBJaYqrjmMRhbQAGCht+ UFNzwCQeMEqwbo9OlD/gSzs/lVCfYYwYdgRZ17b+xB7HPFhdVKoUA64CJbzON0wpWyHjA73jmu7C Px/ATMiWdPufBIewjtp5oPd30YIg7v4xymr7C2IEjDqXqCOPOr3tiB8PB8orYqA57fx/8Y6OBJI3 JaxHevzkzQnhaE/fBQsmteXv4BoJPu+/OJGshK04nqHP88zMWvzSLDxPIla6REOxtwsn0H8ErIRt WfXiWpTm5GwVvZ9SoL6mouL1fafqDnqW5m4eN3GbVxD4yauu3GTTCb8LtnO5qSXW5TiQ5jhq1+la JbLj7xQ5eClp204uFapqN6VLVgkk8dU2Beo8ZNjTsfqXaQActGhXIzg1wST3ubkW9OcsbzI7WJ0c CdCmPkIzGtegx+5ITLPsKUOxBPWkGrECKslswfYix4e77Qttk10CrLpKipeth1ahxPcHKJzl4HbA yfR+2pij4pFmirxCjcD9Z472WZ5pz5Z3MUyXKsLZvl8miGVN7DBJeejd+9tgL1Dxd+KDcm91XoMC xzii6OLy+rdRTmOw0bRevz6RW5v/m2mgEh7Xxm/+8gRfRNgpHsHIaKu5mB+2NEMTVes4FezI0fjm 4NnjFXU6uEVE07tIGc7XFxKTRWdKcIj79cic55pw4tO0lKQDkP7A9+OUCRuCzw4IYwcZkDon98n9 XvW3ik+C+Tri9WtBlboANPPJ+1NVV5H8xdQeDnx9oh8cwQXHIvXy1bBFLYbAII5BmZZSj/pxX2Kg 2JcJy8csiffpAbUziRcJrnp730YGMFBVr5rNoMoixnNBWrr5Ucp80N35BKT3oP3DpeNe9O7r5AKy Gb0vxrWNl/N6p0dzzoyQfNIwSf5alKF8h/ypT+d/V+puls6H8Nubd6miohTPwDGVhTgEx/2JU0a6 gQwM8OoGFEU/YvNUimuIVJ8OOBnvED/2PuPnByRPTpSqUV8EODOAJKWVKYbtDWsJef7PbHhSS8yF KsXoSkCuxDf0hy9JwBDo3k5flhx9nKqE+TJCnKa/3TgBzsLqeCJ2NiudC5kksEz1gKrViUOUMsg6 9BRqjz2gSQZ8MEo59R1+MJYROs9zqEyxZocsNsmArByDLh5qTafvcJOfxnhaxsPlq4UiuetcMBd2 YnytAuWo1Uf/eNOIB29FxNkem7HIigthP3orVAtM6chTf42UpLRxTcwyO4ORMJKZ2dJSP4xct9GL HiOSmyy3Wt+K0PWGUBoYQ/A7LJheI49jUtFjMpApGsMAPEFhbFXCcNsaWWBGAlNh6PjfsmUlx2Nd OmSxDHKZweZxo/KWFG6Hxl8bGmWM5xtkrn+S3VmRIiP+nD6AtN4DuiFT8VPjIy7meCo5pO8a6tty cbjvi2l7Ke9tYYPOSKzmxeq+Pz85k7/eKmAUsYx6zEdhTk6vMJBjEnsD2OlTGXdVXbDcLTpiPqoU v5FLnF1NH43NCKCh63jlxxRv5D4TUHiFEKWSn6iFUnFt7VaUZOlPcgSA/mOrsxHj6tUImmYpRPZF R+tfKfLyN2GFav1vgITkj4im8HGXCSbRb77zs1SKMjzrR3naloXUDJTYKRQj3ut85ivh53b5Fbwy PgIssiDS4xg1O7TgGdoAjCon969aArrVrQP33ntvEGKi5ZbzBi4s+YWtHut2+RLlOFS8PzK+LA8z QYWT8xYHoTUR+c5hZ/rwg9wLeWfN7XDeoFbVkRiaDKf+Ktl6pTVOMH8ha0nDlqWRm/8TEyFJKrOW bMMCnR3ngZUJ0a7nLMLQg9m4IOZgyB7Jl7iuF2VNwrO9AU1fHiXVCbEJrNDgBgUb/GjzDIxMbetK RWoExjh/UTlZd6jtEOH1dA8JhxQ/uwoGEhcqZVsElEibRCNdFdJ/88wUKbuDdEy3awo61No3Y+G8 Wtpb12KHpZv+TUFQTy63YFPYLrUPSbM+DIvP+jhoSIS96/fHpO4yuerCPN6dozvlXuMFa4QlIWS2 uXvaWCU3kgzR9pt28F6gFUs7/XA35vZ1JBOCXT5KllC0DeiReuKyi0XFOGbdKxEgUK0FLG8NYVbd 4IgmKUYN1VsyRguOBU1WBWN6Velon1ms1AEnHn8EtFcdGs+/Z59mM/2cSDO96WQKbB2LN0XM+Egb /voMopDMRgqPtJzWeqIUDIwv8vmzUC233ZJLq5FdQ8kzHKtL1CpwaYE43nc9A9Y0gU0Bti/Hhhj0 Wy3o74JiXxZdE9HbQZJ8DefvfLVn2wxv9d01JwzNLlJ9NNOgJOx0PNThm4fVJUJ/1JsEU1BwKSYT dPPUAUpvA78avZl9h713NlAuo+3aj1hfomu5S8ZoprRs1aaxteCHXlCeDb03T0C7mU7vOiVyOLeB QxX//g0V9mkcfQTzFEgU1iG0Xn3Wyv2UwWroBX1po22ihBDDG4d+S7ylHPPnpbFMEpTDMo5IgIjZ KLlX01qIV9K839qX5LQkUirH3dYx4M1Qe5Gd0d9s9vS9XvaK9Aumlsy8Ow0rsKgxV9S+ZhJxwenc kDIb3+Q+0nUDRzCMCvsI5tUmhY/VY3LJpZ1RTsifOPUsK0lbPY72W73YGP2yl1sMwW7zwZ/t8YJz nVrc7EMtwT0ukvYct+oK9WJ3lIffJwOd4e35PIViVk72JsdqAxx97Ow9e6XrETKhh+mYNB2u5sKV Bgfj4Ojr0r8z4xVyOLLMi2TV+3CC5cHQmlQfleCEXMHSMiPap4/IS0Z0MWKa0K6lvyJbE2DzS2Mm YM1u8xRx8yFSuNms79CARqyqFGw7dXAQiRASy57OlsTAKyv2PsJrH2CsqpSgl8PSIzCgK/wqRcL3 CZUfN4Z1CO8ZKmjCegWhG192+dtelZbMzP+MwehOwhmkQviltbm2jMaInI1u9zcHgDtENS1r9K/5 xR0itt5YjMRFrKib1PYxUajO4CSoTzBBZQ8CjuNKmmeiyBlROkreP4RBmhFim7qI/k9NMfBiS+4m WPD0tBjpzFs38FXHy4ibvYgBwTIvOs9Xe10MxWNYmTJJwAg+dhD7ZI0G3pjYMWPy7U4JVXlR7xHk cGMlHkMive5hxGDKblsAm7+I+wdtllHx/LEALc+gnLyfhvK0yQlQyN2Ut2JWNYOWmI7bnboMp+dS 0EngbSi8yfiVVSzt7krCTyL6VInJcCV2RS2T5dI4BgiHLAlxvPEvX5oPmWE72QrzgVTUfmiiyrFr 1DgvhMMSzC+R7J6LRj/G2qVWieCvqxB+6S4MNloCtIMN5OCUy743U0LT/0YB4Zjqsi2lpvgeIolg zroDLqP1U3gtiA8GRB4eZNk12cFOLW9CT4be19GbTFjKrpMw5qb0DYbGl/0y1g9dbonAfDg8bbz2 bEqz8sBbKdKuVJ8XJZpFJ/Ix29UIJh8QhBWi0EQJVWJRYXj6v1Z6UWUafYlL9C/e6Ox3zWxzSNVy V/4SWBHg+KE51EcJ1rmXWlJslGIu8UetN5+6E+uoqVfi74m8hQU9RX4Dw2vHYIr9hu0aJ1I6x/5C nlfLiJ5mcsiHMOiVn2SPSVe3XWwgk8VCGuzBiSHl0Cku6+PcrEluBlT7aunjC/M7VjMmZlhVH/NC Ios5Pfc3N274f5nRhjJHJYAuzAPn/1SEzl0a4n8dmSJrRYJZaGeGxX/lfQHUgTxfbJINfHWbpWRT jO4IpP1rsqKXN7s/Z2IfL+zbCZlN2Pc4B4k6eRfOdqNmAJJF4UXMIaazRHz6XxATQaDMwAxtvlvP Mj6tot5O0FNnQ5GDtYANqGIVUq+cY9iB4TIYl6hTWiJZ3iy47Oa4HqnZY+5zVeOoJwTZJe+/ZYzI Wr4n/5ZoE3KyI9tR9tGmZi9ujeaMTv8++h3JhfBLgeFJqP6UkPdPLUnKw+R3gTxMoaXB43EMJIVN XvL5bzbS+k5x/JqgoViBtZEBbuJ/sI5/wJeRj6k2D+IFjhx9e1MXG8MZYw7NVljXfSL/AxJz3hlU hW8N33hmlnQsSr5uDTuqgZCvn2vJ4K8MPj0CJn3yBi0/mypZVxImjaD+NrS83LMsZEonxaAZk2ep EQkTEGLMlGv5KBoIkm9Ko3rNDF3SAdLgpgjJmMU/55IRVg4kMAk2AB66h15c12v57Ztq91E9GEBO 8/enqrxPKoRSS8RKLWnutiUazzDqA8t2BGOnUyNMhIR9SSOb4+vySQCFsiO3y5iTSb6cjysSqx6X 7Ig0U9CdLyphRsl6/2xNziHp7On61QCTSPv3/cK/+3X2XR4QEkEp9WyQXzoJj8Sxs+vm+JIbdwZ/ 6jfUqmou2pul2h1MDxdGgwmRuZsfv4yioDCWNgwMFlwO88bVJIuM83o1/5StCkBin/u0xlRV3vBA rlS2eog4fWQHr3YbTiZ6RYjHaoFtjL2JEMcbk/0VGv4yTAlwhwPUCc96jMJz/l9yroCjnWfmfscn zVj9chT9zeeglClnB3SL3RdhxEJKj/HFhEnizuRwV11XlGX6XGXH6ejpKw0h/vy3Ni9NJqziRIka O+u+5FO0iaFRLm/g7yyBJH73LrUUIt/xKkM7v4hPbXCbusPMgmtQo0Vaboe/THXmMeMllTuU6blX mHQjV8iyiQjZbtHBqQMCakRrBcmSuLBPpepaIrKDtV1WHj/I7WfSxKU4U8EqprkHf5171rSsajj4 ZbsOjUSbekVpCgBrCZoUcT/Xf9DvQcDc4amiVFDedOuUnloORnxIili+nguxC+t9op6iz2tQZO9Y LrmXUEKvgBoNJP8fcK2+NeHbuQEW8FBUJXZMIJqlFg4vxhiurtlLDhwoagy+G1TAgr5Nm4002n6z jOvIcL8V1ZGINeDhFtGj+qi8y7L39o6i9kl6A/Qx8AkhU7ftvoXyAxsbs33yV3DsTzEuu24/mpXV lo50NTXWTLGswflNtZXuXsJMgR/A41r8j6ilCclWLmxTWWeHvqbyGzMd7H1V8XKZxOzMnnI5XKVj Vfna5FrJsaiEDaqi9Ej9a8nM8LoX20D4vfyLX8A5m/KbRhj9SMXnPoE1+VzGihSK2E4YLrw7Nv36 ox5DZ/kgFdJ7jgFuAcXHxYT21NW3BVTlJkLw8ONLb1MM6hYCO2Lz/mjHecnlcZPe6cSG+nFyu7kh Emecn4TjGuGONL+HumXAQREoiCXn7k1N4j918y14ZrQiM7XIgrHCwPvZJLUknbB19CfatKzd/Km4 JQ5GpyGnFbfNSR155lg/rRFA1JMF/J1hZZkORSfhnCPwCGzYP7iYRWv+j4TYsyofa1Jl5lfQEeWn wnqjmhNC7ZLdCcuaaHeEBu3BSkzkuxEoDG6amJOdkjlyU0IQ/NI6az2xqBVEp9jRz3bksvu4EtW1 VLyZsd6MBAUj46VayyBa3MpoeTwYXuP78X4Z+/2bw1kUmKWn9bXKz0IhcFG3wg6ndeX676A/5UkZ G6rs8tZOdiGjzyE2bJTEnlykpUUvP+HUz6x+Jcom5P4o0gtjjKaWoBWjAqx2jO3HhrptFDt4GXcZ cIw8e0uH1LswQaAfFgRRYtEn50gJANF1MvGTZolDEQqNFYjmKVw9YfcgsMzqMCCtCsIywHK4Hfh0 XhMMVlTEg+eKz6yw0Ce5NDRYhjEAjazj4F48TIc+gOX7RhXySDSPpe+1K+dWU5C7HFSHvhcBoOMw Z9bM+QrX9z6YVtH3MIqGA3AVVfXftXaKojBr1oInV1wTWHL+Xz8xXokGNc7MtcBFrUi6vcmDtPM0 8Q6FL28lr0XWud5hIPYHBFTBNCA9zbLqDjXjRAKLk2nQrV6IAxcF4CC7Xj7NbwXuRqHMNUGcl3+V 08reDcRgHAFKuv+OdIoesbhmLaHefgsTy1fjRFXXCTCy6uh7+EW3Ypf1JxOPZ37NJR4veRxqLEg9 YnpEdWhhuADB79O/5HxSp9fRF0X7SsvfYv/jDxjQypOaFkr9yibmWrgsaW8nczpYuyYrClQdl+4P 1oDPEyS2N8kcW99YWo/Z34OZrQ/f6PT6M5OrOVmobo8RixgxZ/Ebw3Uo15DPi+dfc+2TcGk6CPgD iihvYHr4AhDYTtvLE/BDt9EzBATt5nWxXH7ArM4DA3GekDHIN4zFItAk6dI7x/mKq0xZvYjwO4fV H3yzcu7n7GOaI8o2JG709345woOpXqut6VWoETkU+yGvZlLaM/JyBiy+dykOyLHw1fRq+WFDt3Rs BclVcZA051/wUXx7JpMbrovDQiT79ZSsRiNk86UBuuwo9iRUrP4xq60X6fMPAsqTv1Qeq/l84XRH SnE5dk7PqfAB/icVIMwSnqpWkpGy4bOcPVjo8J0txu3XsfcXwDu9U4XKxmn70NyQftw1Jd1CZeQV ISV/vqYMlqKCL7jnIXfJD6ezEW6MNN4zZTMRkb0BoAmOqvL1uQupsb3s+hlhrLQQodRctuTkWRiW RkY4fE+qCKH1ZOuJCObpXZdjL6pHMLmajSzcxTK/Pz0TEn9qlJLOPqYgTb8j3xmjLknW9C0TpGyj 8QiszMpWit2grKlKAPOEbjaGQOsn/A7YovhchxQxJhe1+maeI9M8ZnP8k026D5tw5j3gy5AT41aC XLgIiPjBzKERihlGwqUW0OXcmaxIVXL9Bha/0PBEZHoewQcSIiCquepM/lwb0avy5cboyiv14pT5 xsQ96m+o7/G2ib5U1r2OZFd4+c/8IFJmyknJi7HHtGyRniwVtaREse84LNLqjVpIFaMv+pbcDGLy X+3wwDaA4ViCkuMOTyNqjKzfdsEtjdHiaKYEfRKFbs8oMVkWp2dBB9DV+KQLhLse2pwf9xMWQAom LYTqkrAgHp/EcszDjyI166srp9TXY7gKOe6YJI62kdD70Rn2ZOFu8w/n+D6VbeiGqoVUDzQB4xgM Iyrnzx3FOJsAyPoZPDkc+siAOhrZIPEfNnhVWNTYWpVFgMaLU42YCzmEhJJKERJnGh2LB0OQcFaM T5Kjvl+EfjmZ2aj2PzlycKcJCg81Ib+ax3ugE+TyY7qUh+dH2sOi3J2kRg100PtU+YmaQvkz3VcT 1aytk4ibL1k15DUomh8rSHw5IxH35W1MExHrfkzP1FkNgMpe1X/OTs4BQM76okb2Z3Ul2KKN+DFv InVopRP5+0Iqc+kZ0Bp9Jk+XwyOyuEpw1vGwcK4uawdL5eLd+dQszmfJBsypAz32XZxaAZxqlnID sHWkclEwx6IbOruJt90BwLaI7sfClWwQnKbOCjSh0Wde6nCmRFY7COuCYpKhAm3UCdJ6UdhAnyxS PYmfl+4b95WxxJpFa9N53IX+WBUXCkqGyW/NmoGK/mymiAEVawzRp7URD7ozeCem59/nFtTlifrD PoHjJFy9fdABsdf/IkReJvjTIH6tcSRE7PXZ6qayEq4iJjQGzAl0/UEBmOlxv1QGjhJWekHI1+VV 9tPryz+A1+2NRjWVkaI6kbajbkUtPzU32fGl9FRiSHlfuDIdlKJ6srxqAgOLXc508ZAT2pdMn34D DVfyRsPTg+RXXxe1uuCB7q9V3wdMbLKmaKvq77kjyLpw1uSkSrAjLEcVDFsOyw/LtsUTCHp6zhQD vBz3+X7xEBetp834/JUKo9pWfdExjp+kCSMw2sztyVV8duh5MQqDPE0iurcw9pWPrFJV/l8KyEgS OUBXv8HhquAmvWZ/jd3Q8/moH4S6XSbDKAiyXKNsFPLq8EeM7zD8n3hWUJnL6kTtc03Vug7UF0hr 8grMDrTgBCH8jX/F3ihpWIObNm9DTPjIqIV0YrUvWQH7yV4r01hjBMpR+EiqS5MN67TyKJB42JV+ 54F6FbIwCFsz4792BDV1Tz5WFMMuSIvV5Z66ZICyyqRYKJ+6dL18ussagH3NxfGJBhQhq2p2ZK75 pbzgwJQK0itaZRw6XvlZNPH4psII1LMLXtMDXQWpJIavJgW/6vzVGUrtNJIefysm4UK5p6THFhH8 c+rkPHueMv+68gs/l9vy+4Hn4n5LHPehVcQsbvgSK0yYaCwHaZY0mmwXr2LdelrTfBtZXiIFZGUM vGygPkp0uPFjwM/iHSUymONtuHqRLaNMJ+8rGDYTfaL5pBqnONDBvNqxayeXRbIAyBkHyIuxaW2X o1JzVh/SFBBwFdPnE3vOO1bpFsmGDpM6OspcvXoXjTizmGVrSOYOE7z/70JK9uteX7vc30UMRIzd uVwGi5KoaV+k2Hn1U8N71TT3O++Sxjm7EriQr9NyKfPa1e/y1Nv7bwy5LWQtD9wZ5ZqQuTVPWGx5 d7alpmQLulKECVe7yjB7LkypCCEu8n5UisX1sgigk4z+Dl9mAH2TpY4SFhDdrLLaT1Cvbnh5ljCM PQDgmBnk/j7HuvP4U9UVnDhUwAr/hpfzAGGcmsPAhgnC9UAuN8An0gmzoj3VoSpPwc4gzjARhdPc WZBuyMOnxw7VX9GQu293hGbt8TCJaPTOKVpEBz+06Wy/UfCDrpOZgrvcddzinQTtQgl5yMJRPtvF VfqECqtsEcDUIOFDroOD28csqcjPf236M178doyBeVJ2Y/ccRYvcZhGT1nTrtEyjP1chKhD4c4gp zHD59N7LbVy8sPqfUzd4C1WSL44Uhm4deEUe6BYESlS6iOyiS3eDFLn+azOiL/x3GeIJWgiwT3fF ylKQmusoI2wSysIlQoutmU8jLgWbvkFAvSlBc8ef/7R2J20ED8y1kmwRKDyufwchLYZZH4yexHpp He3/G8JuQx4atz1dPab9tuh/cQVHHwrr6kxHnLNgVZPPrcUOnm0klH3TLUgi0FTEF+g5XbA9jH2K zZlfDvUUhE9Tvrm5zNs5kIIfrqBpRURmmrGx2jUwTQlccEWloDIJwH7bnVVS6pBz4lhWuY79sXKx V4T8zjUBmv53T5DNkLJqSMFxRROV4dY9xxMc29xgydnym9yQOJyt64xS/o4xTMOid50YRyTLG0hI QwY6kITat4soN/VEekhcqzXFBy8ELnaMbO0JONl3BEiLaeGx1mXx0WEGdKMcUcIz3w1Eff6hFTde fcgol9gEb/dvtd9HpaC1H+rneP/+CFCPwXeLxvb14x5uRzLQwMee9oF/vnroUVl8dtRHw2QwQeWU Bp/wydAUy6B+qGT8oVO1c5M7w2yuYP54izsUE6RrDL4jAjHWyon/YSNHoaTEZf7RLYHvCI8E1SNX yZF7noL+8RZMjceLOk+Gh06fHXlN9ztDhavUyy03lLQkJK7QXKfeKBYBu0Nv6gbjg6MiQtjOeinN GCVpWSyR68DRuGzfwQeXZeg8p30f3yOYoRcV4ol+N90WCmXWRuchtaWhwbB5gEyT4yPRIJGwivM8 dQ/UiOrwuwca0wsuWtvkrWulEQeAMwdr9L/N66OIoeoQ6k6TYgDsbJsa2BKL5ikc+JUdmFuGk0Sj zOFS0V7gdsdD1JFQJqT+gkdEDz1b7l1OUu0u6ppQWIYbS+PrWRW0JRxj9qRbB4SMp76oU357GRSB if2moOGuXan9Ij9H9NGjrrCr3ul+jAdnMPQ+N59GZ2VQbH9+MFxZZCuq/BcLqvlzmQT8FexO64YL EimlOqy57G5lYoKtZnAfN5t2uiMuiIfD3wBQ3FMMwZDrBrLITuaty6GVeGvY4JigUtZ9um3fdOWQ k0xMhlGGzCbjRfzXsQyux2au4tGesqnT77mqBcJAA4aTjGR7maNmlmYeGQOCsoipF2QI/vmIEjQZ KLn3uGiedj7mVTRADY1zFQ5ruipyu+4LH0be1SO4593vI68oCFLnKKWQ9+JHPowuzGoHJUjGI6dY JhOxpiUrHQBIeYhzsakMq+pSYZ/AgfUW7EYTWBBZbeo9eE3W7vik0lHDhJ8Oo/ZbcQmWJ248V7oz ROfnvFa9OPOVd0YC+w8Dxt3YFgzxXaIrZGXk7W8CbGRaFWNYgFwR2ylOjMDmGdjbamnso0Vb8h+U 8UbSCqovZ+yFXKJQMnf/6Cm/v/Cwv4bW7DiUfE50prBtdmIIzf/vSev/6cW7qSAuIm2gl+zcjCn/ oUFWIyqjWyKUfOrB1lOYVn1zYVCzDknXU5S1CKXpcMhjPorKfsX/e+cYDlhVN65/wx6peYN4/HYJ kbEbLmY8PaOYQr67sPqWB53hWokQ8kKqB3N7Qr/B7Zd592ZvIh62Bc78un8jL+EbPfp/+7t7MzCl tgNIDQFMc57dfFsSlt9cpZYoeoeGJ7iprEYwCfeaQ64JMATR1YZPg7cGTp6sIGVypSgKV0NZTjrM r3/cyBfoXt9mpNuziTH5U/Dx5o6Ay/0Otc50Kc5TR4BEN7vhPYTaG8hmAllHzvnOsRPnz9h+TDNz hlhmvhKtkNk3cgvJc0dQ8KGJe9qlatkQQaWyNLdbVjV3O7+jFIiJOLDjkEgK7eGnHYEhSuGxrRfC yw5zEVhPfq4tFGBqa1ZYTxM0cUoFsxA1Ck/+duDKLD4HAcYJZ0vD3wIQsSRk+I7LvPDJ5Rr4pKnK Ud0zHk+Vkv/5XYPwrKes63C4OIyRPPqc/GyoomFxtk2d6X1SJ6rlGWWqVlqHaY89WsQzR1HfFqev VMDKRYBSrnM0nWywt05goVjK0OTflSnxzmWkLhj9wQCQVNyTBL0AMHXd+yQBWl+dhGYT2JEcGnxY LeB/rpuGK4LEjhy4aPvzWPx0Mj0RNJ33CPV+YgALiQcT87Qgspl2s0GFWB+F6OwErGu3SAbv94s1 nOgWAgxwizKBQhL2gynuxTaRA1CwTYZBvejWSymxkO95Rhco/Afm9RPF7FEMNJ83LdiKC6eOwcdD n5Q+TIjYPCBkYw0EenWjQbhlXfwybZo/GHfjTgyqd6wRlGRv0iDtffqTQyJZYDy6YrFjOrI8jwzT N2QNQxNn17uIKNlmEboYQkWu6xQulp0d9SydE1nTW8dkBFM4zZZNHPaKaV04OHHhdV8lN32idKoD M/VzE84c5PZsrUrD31F72Mn9lJ3Uq4OCC33e61b0IITLcVzJZ/onc//nggyxpbYxfmax50rsNCj7 4vKhh2BgfAJ5yW9dpOl8WbogLlDeT2Rwq4xMtR8bI9gyUt74nnrXuO9nISI0lgKbM9H/0z5D+Y4M WoeQGvTnCL8mCj5OYYVoIHQtzNA5C+a6Q7x9RrLIFtLcjW+gh3jtY1yVZ1SzZhlbEjhAzGg3A5IS 3JetrCjPoSFTR4apKMqh79dsaB1ME2POt7FQeX1Wun00gHN9yh25WwGGaYRYVnJDxqly62TLEnod x+hkkI1V1utYDOlOBM/gbLjzCF411RIGwZJPApxTKheSnl3SApuzWgAytpSE2Lrm3F6u7ZgPvX4R T7U+riabgbv64FxDBzHVNybKvV+B5+WA46ZGxM8xk1mvYRYaGMHIEjTN2hYC8YdMwZkPlQRJtvBj vIiynm6LEFbE7GKN3cH1m2S9q1u0zNWDIKIal+NupG3bdvVjUsPEZPTrN1/jX90NGTdrvfIOm7BG MG1uh46YPr+VFCc4WOW7AR6Wi7bL4vTeNnLr+Vt4n1wEiMk1d58Tg0KvUt0xNEIWFM3C7Ldh5wfK YUGlefk0rVcJClcbBw79qrlI4GkASd/OpKj5xp3x/fNlbBDFO5VzUVlGQuuHTT/IM3bT1H4cdbjP REljmEnludPGJIm8ThzS9OpknWJOy8Ul5SELhieCkRh8rNkPb8NSYwR1FaPSQ2rjclRw6MvG/Nao E319tFsckPiytKTg/bqTGLWNF9ahOv/dZ30i1OlqDljLwYT64PazKFpjrf4KFswRuofeeENEaQpZ EUMEnZyMjSmTmmmchAZify5CymE4pg/5on8jvFcjqOjgB2EmT5jenaO6ueXIX/LiJgLB41cPbLFf c/sD0muH1t7+IsT36jdQkwLGqtudGB8pvnYKo96hgr4HYZYUfYOAxSVD6gSBYOwrfoQKKw9vdahn raC8pc2MMyAVDwy/T26C/H3hOXw5GCcgszTz7L1JnWhdp773S6aKBe3tVqF2Aw+RCVXILW5Fil83 YwbDpXCOJ2x18kfyQHJqYTZLw6ECYzTA6haqIh6GHLLScEXP/AqU5Tbg80GlpGGwkU+937sSqs48 kuJw7/iyFkIiT8jXbgqyVV/E7qDGg71+GwiA20TFZ1fdk1jmyd0g/9Pk/WuZpIUG3gK7c91yIfWQ MP/6iCo9JYVHfY0GnDj+ArzGARvvttYVpJ4rDZPthjB1R+wuIly+Dhd3RGZMzbhnsqFu62IoG3gj /l9aC433p3mdT65SESj4PnbnFKnKMR1PVgoQyI+YoUxvR6XAY6XiWeJ4X3rS+A06JGPkSIGnviNX +rkac4iP7LDJWBBEwSEqsc2zoiHJjwp2h4B25mDD2geawhAWwLqVZztKYnD1sVTFMfgNBkN9UoqL NtXw4hdHB5mxrkBSQp43gxYiZqWTHH9Rbyd0OAVygunjwbt+wOKLAI7ydR3HSujiisiYBfgiwgGW pb16GxJtf+4syb6A8HRT6M3W1re4mvuKVmiFFcpX6KAzZcAnK1bHN6vrc/uqmhMPASRYd70S4OqX SmbqB3BwRQCd8rPhIkcc3bDpCSjWq0BYqIp3fwmDZVqPCoDr0m/Zxox6LIaqF1Y6NPc9CpzX+9Ya 7GgNrria7IkqTJy0xrRHjIx+GgZ3w5Bu07Yiuowm0dC1B5BdhsoSVxtFhfN/DQeCaqAcpw+JE/GA yUwhAxplXgboz9+ksUntdnUW1bUT45Aiwn5n5GwxlLMPxg9t06/75l84Fhb2Iv0JVyPTyGHCok+b wUek0kckHKZ8IyMckY8zxfXPOnQZMOCmT6X6BKEaOBcUEscqmKOIFSglkG1sDi3XwwP7rES1sCkr lkL5AcvP19M2RbW2Axk5tTObE2cIvz+rdN6YDiKBZc29FTm+PpOHBRW5fVQRI/Ydko4LUCqki4x8 iVFFxCtnRaJyokrOEABe8Av2LyduWQFU3fIPCww6nR5TTL1iWh3Byp/CKXDGcX7RUPecmo7u0x4G JwVdKG6dIYZyOuNwVlB/8FI9uj40J/MWO1GVTQUUGZlFQABFhOxOdOmuKSP5uMoDKTLZfQGNDkyG kcUyKGd+B4ujLHJWEBfoHg6P2Rx6jKVq4yCHd3mku+P1fVGdzXV2t2Gpp7+BESVuScHLqFSaBygD SvRIo/wIBVYLYn8RidZMDvKmfzMAe95m82HlUMzBJKR+/fEzyg9Tws+nyy4do0cv4RZyUUxjuofZ kBn8+axZ2bH+kBVILpnpZu1Ix1imYnmObvROgAVb3dNRIQqsjvFGsdGMaHFW8oJIeGeng+iKLhL2 eM1XYXE/vVYRWokWx5OOh5snF3qpgXUXNfy3k5feXDOnHBt7hxqN0spJRPew+Cc43ThGuSmq6BAR FRtNIEkFejPW8T6+GIEsttWjrzrAPkze67Oa2Sra/h+ltOBUGjjv527Bd2pWZIPbhnysEs0DqKfd ybI0yvrSopgH5fMnXDfrqOVrk6lr9gJKMLFdZC7MeM2V7AGCzd/U6nXDWX+I0i1xag4+hSnw+0Og LAswPBzpGQdFn0bLsCucxvF10EvwqoeVLBn1q4w1KcQwIC7WArkmGYBpwS8ONF0ieGyjzc+CMrUX LU/NCqjNFkSvjnOt2pSGnRJg0Q7x6ItUn5RwanDUa9Wrbnyn74U1Q3pZ/2sxQe/VrCkgxcbDv5Hl 8M0j8QtteAUnn2uJyRv49kfkS/jEoUB1AoA/yzELXaV3Ewp698wkGM0cIWll2ihRkmY674UMqBn2 xC/L0WpdS2bw221z+P056WZfSnVV/6b6tTXViRErxHN+RGFNG5RxChVL1MP5NtfMiRtbCWHp6B7n ueP7G32gUaP1WtqoGAwr7F/zZl1x/DH4SeeItYfYH2Pu5kFsYJ/FfOFvWAqxT0iqp4cTnYe69+AF JUs7VdBTAZiEKvgWqDPj2W5Vy7fayHA9plNja3rg5XlZn59O8+ymQYnPzszIlz8zPx2tpnEZSOyy hEhSc2RANTwc+r5d2r9LCSaHEJ1HSe6V2jpH3qIF/BhvPceZd2mgpOlmT4vh1AIxnMtzKOVFhjyJ 0L1wFsK/Vya5DUH1UPyKjNvi2QZ7VZea8EssZvZ8Fy9kl5FMjCCTvR9jfcMQdrDww/sNmvUnbErK CfmpeuXCGDtdU/wSrvUkYGY8XcesqNgdnhOCQjLTDguQ/wC+V4uNpNd6bYoItL4+u4wzU8gdoIyF x6v476UMqHeAogKLoTimcnVxMlb/dUSZxWP4gJIweL/sEBfLOb/+EwwxYMvXpDV1tbf/SeFLX2T8 jiEHTvJ+NMG7e7ScdYBHhQHz9bRrEMunttzofewe1idpNOVj7GbYsj06aZGiCQQtB6bDH4Eh7rC6 4n6dGuuNSqnPlJV+lqtzL5kibbpgiRsEhKiLThRNMbFWm3IBM4XNv0+tqLvUohMxDzwEMsEJBRBz hGZazvB4dOpEXlfF3vaURutLatdY+A5nIa0ud7gG/l5Ohn/tz5oCmCMC7u+P+0wHBbS5j6RiaIcs hvnD7iTJ+hPHLUR+isZJV8iplI6H838reKLS64fm3me7sIH8/GFLpy1HbaIyGtdGEG5uNTZcni3/ ae3iC5rv/X3J4qtlYMe3wPUb1Ruzqp4saoif8GPy+/v4/NPKUbleHfZdoO0omFBZJPjJglutjcUN dbnoqgY3sjS/K79OMzFQQ3mV61fxe7nDKsmjx4SS2zEsd7jfEIFV7zGsd3dPOGYX+TpmkP0G+N87 XKwhJfDCTbXg9Oz+doxAV+24uh0N/EQX59e5vsExY3Vv7jVtDaZi31vHj08oVq5Ja2MQ0LvlipIp OwmeT6vJAP6aV+mas3V7GRnmKpTKS9wjrfGTmQuU8Onle2a4f2y8WCtEVlAHKCo9EQt0yF5UaVFQ rVpB039X6cVN8c/crmAEs5R1ERjIpLVk3AuQNKHZdZ4/vwdxU3onub4E87R/ZC+aWjtq8U8wSp5X CJBWX2u85ZurAVd04K58YT8V8iCyLhKs8FaeR1JeFp8ZTqzoQUSwvJvrsWqxkNbNv98TZGjy7B8T HDshJh2NsTyzRwYcxq4tv7Oysll4ciE0CEYCvOC2TIHzobQsGhd5I8WL9z+HxQb8KscfqkTvnf+g 7AA1KnG3FTqiOXtgJSjFTqvrfuKmimhDCR56sbgqTgi6XGE8r3xdMapAC3aOAxHrR4dkcMFNFy5p EvibjjgdEf+SyT9zCxBhzUsYsiIIOqmNIVmIONGgElWbB4a60D1HkAYXHZtIYNDa0Pnp4NQbQoHk KM6+Way5JSAXucCNZBzc+UJqzlyiiC6W3uexGyh0C5+UGFfRGXbaBa5vZwBMOsEg6pjosiKgeBMw FMHcPIBjnf3x5IcN+ZYqICFM1PveElq09Vr+Q45WK7IvHfnqdvXA6dt6cl33p2Hx4z4na6YKdZs4 JzqKZFmp6eZgAobW4MlRNlIPNwk0WsmGExJRqqE6BlUVT/qTDoDm1mWQj82fSHI+r1ugaHUSuo95 f2kybtsRYL4ZaqMdHAwndblIEhAX7qXxmKDFcW7/lz5HuIKC5p56luCQwPfsbWX6XqbpM9RktZ4+ hzVt7/iyJC8Nn1Q7fQiII9AyAy0nOBWsVgL6MdrIkLXnonoqTh14NmShfxiQ+mSPOPu2bx18kGov V9kH9IIb+yyESFP3ODloHlJTto/YM9RCOdlRM3y9gxMom6vM+Rnt/SvvaKG6IijZ/1kmd1it5eQZ pzObwV1u9WhgEZEjlYDO/no6o1fN0Ot9v9QjOrSaqY9uxtEgYDqgApFLOR42VWjSVDQ/ulH2p5Ze WCuZlmDMmiZmk/tCirrIzm1IxuQ2/oV+KlVIva2JkWfFywIHYHd1FiVcZQbhl27s8LytQrgWKiHS CxoIcfaeOvq+++GGgqHA3t99g/EHsLRcMRZ64VD9rxa5ARQG7Gx/6aqj4grGZU6Yxszht0aNVXfB 5ul8Pkr0GRaXyC4GhTnvxwibhtISboLVky01wiMZAN7UYqbirpXlDMiM83QZWI9HeFMUV9DnaJ/S 7y5m4h05Y4/yTefGWw62aF5dWEwd+WUr2HfT/g0aurj8RRM53qG5il2uKUmtDx9L9utULsTkucKU cuFqpb04fB1UKcX0CBZFdaYA46qRczb6Jh4Lsl5qlcipNpgIdflE2HvI7Wmmj88UvamENWs89Jga LOUsbXpuUyurbDHuz9qmhXraUl6OZOWUTBL8D2909640po7AAIxLWI00F7P/0rbmfipl0phwrE0o o9x60qqj1oAakI0jDlPSPPkPMMpqVYjoohvQli9Fl6+5Vc8GB/940IKU5Gs8NzLcaiTo6CZ5/d3e r1S4k5KQriAJWGKsAcGGIntHpC56RwnsmjIKgs1YNImqOZyYFkDvRhw1mpxjLlKIk6O/3syI2cOX M6nNJod3IxslZ55oPybLnR6tgIDlWHF0diLJWA7H6XU5qpT4nTWrghiXCKXjwvc+Mljadq6DYIl7 FLzffBDeKnc/ZjWdEcSX18lbbL1ii2R6r5wCFL43ZaBheCx4QBgLzwqYfj+vdsUGoeFnv3OHUJne UioM3e9zNbp/A7oEdpq38ZdCuaWEyb4SZrTbBX/vn14MnW8ln43Mn9+AF8b+o0/3Yuon1xpkNA4N 8m/c5Y6bzRIxM0xUVhET6A0Y18OxhZblCxPXHqoGp2bjCOOgaYOYbGF/mBmCDmxNKy1KTauCF++0 uxs3zNBHqHxXk+Von8zK1cNQDBny1WD9Sb0A0rA1quoVQAo06GXOmseqUQE51oJ6XI/QjgN7fY0h wkObfmREmiWr3LIlP+5x5YHojyZcGruhzCZPcuMhsr4RETjUcxPBPbbQEiyQYZfKc64GXQJg3hXc +xFj7u/JOb/ReQZZMzO1HvS+sERkCPKUQ3bR0J/0pi9jC0UPexbXjLaPvrmbf0T37k0lFPqnTnC/ PMVAGiYwXTiU4A5a2z/2QUXOt+JulfR0OFCmVkU1oQIaKr7mvp3Nz1ivk0YLzw9iKp1qNRYHrypg nh8eXXqoBTFdqtfspX2244Gtyl/2RG8vdhlRM+foUtMl/clo0S9swA5Ou4jR5xeInUldW9stsSpJ kc+6IvMQ/ggk4vibTmx2TjeYaW/mNJS03pHqxA8lE5owPLuhBD/uIE+O24RBfi4QFWMKzymoeg8U seCJRiqbkJ/wVxOEUguJOCIYII56GabX4tARv0FOef90Y1rJTW7l1O8lzVT8woEvApg94W0eHRsS atdtheFwt+m7Bqqia5cr4A3Zy3JOJwyRzx/Tjd2pWe1pDiblZstu6QajlK7z+p9m5oBz2EXHtCJk sTZTKNuzv8Dz8i3uEBeDd0EaXOb4tdqt5DMumB9sFXRiXbImq78NkfSb4fRzfNDg9m0+KOm8slI1 AGPJrQ7TETesxk5yR/w04CHGf6PIe9a1P8C6umIK0ZgNrmpE8Q1apxLrQBzP2K4xfkFwKxw/HLQQ Xe84LduoD3efCRRrhJdTb2uQDg3S+HbdxINeKNHmAp80m7rQ87feqhzDRj5xYGfpuvDwMYiR6acS QGCxbWDX6Rem/RafSSE5jFjrK1DBOzD1EtEGov9cNUFl3qyOuUnJ7QC0HOzBzj5ugNrmWePsQgxs Whf13gUotkrlYXTZx3oUdP1ACa0odnQW8Ta3Oh2RmArGand9EiR03dgW4B7Eg0IWq+MNMYcBMRfS /i/rYOZUoyMg6pP/pZG95NTbMwS3HGf6J+7sun8BKhSiLpoCK0E5Q8H7XAG7FMOKQwZsmEhv6ORs 8M1wlCHDWdFLDb1BeLhHXEukYJJPofzaY2Cpy7q+sim5s+Xs1OC1AHk42aU1IURh7YLUdjtzY8el qq6Nyuv3BD1UfAuo7sGMmT/YggyZXFhRNXD3L/A4ysSRjIzBt6kd0NZugTwv8OX2DiuKaixWCoiQ 1EfcEG8FC1YIx8P1tBBGx8ld3LW7ad14w46N4bhXV8f04lbSLJ3OGZp47KhweXg81oyFIzL72GlX jCPlG1HYdlN4AchEBg8JKNjcw31w3xRHAklrewsvKrBXvjov5SAFxcaR1KvAxAVLNm9/7HOoroff HzvwqdDCz1Flg+PSWX4u8Y8g6l0XCP+Ph5zseNZuEyKQ2mK3UM6AHEHdpo4jy7pPxN+js5+0oh2b 1xPzh+V/DHg9AjfFV0Ig0Ew2/6aYREHJpqaG1+QxWM4z+1sS+kSdXVzxdDzSWp91+QuY1O5eoEl9 vrL5a+7NvUox/kNl1X1PJZz78/SUuKhZiSigui+HULpJMJ2FQ6+HHv7J4LXmjUd0HxnSC7hu+Kmh oIfVW/Ill01T0Lol54lFSzlZ0Kulpywpg7CbHv60dXst7XD1CYrtoTMc9Ho9G1ABAMcV3zzbMvkG /uXXZcTGfGeiS5+yVLbwJr/yFdM2wfQVaFNuZZHv1vTeFIDTe0CaqC01QjKrhKBE6Kg135d8tPsA TZq13brrGZlS1Cx75xW5hzCfKJojz0q7Lv6ExEDEKMc6lfUWbJ6goNK9hJRR3G0kVY6l5p5e6Utj oXctAHmcPabHNTBkwwLOjol0lmx9kpr6IgiejYh3DQZqrvy8v3hu7H5I4yO/xxQGQWuM6DZODNGO 6u+qBoVeVpjLL7lS7bjf83pKD8djGFjEXeD1L6+6LpRWESvtZmGdpJKTFweLvKfMp6Z2vNNpGh7g 6Lv1SQLzPYwE4fa7sMPMymZQXKlvQGlL6YVcnX80S+BuGiIq4E75qkW0w0PTqgCRv3BSceBOSowJ OmJ6/DZBrcmhwil2thIV+Ep9RcC0ilWYr5p1E64DRZcPsbtZIxSWz0fJHdmcp6p338MdJlGtwI9/ ZTYdfzfmivWsQ/rbPegzM92kBk8PeYTWKMM8fyYONIQYLTVeAwt7lPFX5CgzfR9luiQYAYFw0MNo zbXqnsS5Syb9xhv1RxE1X8F/3gsmBZPaKTzn1P7jTJgfe5OCj3KAFwAuCc14iS/tBbZJTI45ls4v cVEnmCdM+gXodGgIqb3lwiT5T5YAbDd+pgOXHl4trTZvkJbPdmMW7/MZPJ4jEQ4ARdBpA+mEQnTg RzbQW1PN1IgBYFqKS+G78fbd8KUNJpv+uuchrguCnHLUFQ2MGDfGUe4yJzXFwFabDoHnEKXKrdPd JfyKcXqN/3QUQa8Ma/Ie4FmUfocQxURN81A+HxAhZ7f1wD+grLPhb+g4Vro/JUOLRwyj+uUFaJDz xzzZ/oOpSZgppnMA9/cZ0AhYIalE3QaJDwEO7DCKCInrvdKuwmO49CsRgkFkBX8Gwwahm26mxlJK 7CBha91K/WXphxXP6BHLVxSZi6EfjTNRPKpfbvYWiQKYmMOFG2kHihNVsmk6DWJEFHsDw+f5r1aA XbSvXvBbULFk6pvl1Vm7S5EnV78t+0u08ilCLooOKJ3agKvF+jQmkMIODQG2DRrD0u3fXD7LNeOm DbH0qEaQiPgZ/PPVOkXqs/Yq27om32mE7grftC5l2knZJuku0ZF65BCVEZq8geOzpR9CCVdOq3Tr BxXV3RBmdAqO7c/ifhFrcxs7Gqp+p1Lvj7mhCGLuftyMmEe2wzw36ZEqrUu7CBhE3LAZzuLUF/1+ QS3qlTSFbko4AJOvzwtoi6oB/TrI7xzNsbkMZvMMkxAuBBabbr3ug3lMaxyNuWyi/92/vesoEmZH bHjCqqysExRpe5NCHWrSMst6VHmh3ZMXm2FsFrx+H3fFJ31rhvKyyeaGSv0HPZmhIMAXL3tTs8o1 fT8zsiQP9iKtIbUSvvosomnOqW+XOzDhThSrU/VN47Ku/0uxenpPFOuPi4yB8jpQ1AdMT30WE4hZ IoLMtV9IxO9gotjp4MUfLbvuXej7XclW6ys9M7wmI18+ZXo4ofHeebCf4ZgAd6SB7zeKOrD3A9Ty g+vqN5p3yAJ/HUZEHgippE69stzf5H0QdCNRPl2iyTklrtXVBbIXlQ/PDh+mSq06py5VIRtUeKKG OgULZOHfO4FFxROng2S1l8vAiqPLUtZtN5dVl/B3iMFbSrbwJ2WJaF/1/58GXJc3j7Uk7a4mZtna qDXyexASSJce3u7b/v7SaZhJtDsJkQ/C/VdqARNgFX1CC1ov10/vmedfSMTeAOSqD+XOBVlcjwMA GT5FpHXOzNRZQFbpHCJTCYDRoKGstdriGHqV1QJ9gLA2XkD83lcoaVk6a1hMk1t1Sd6svL6IN/M4 gsdVRUI52+WOk4j+6twTIPgHe75c3jfnT/ZOxr+R9xuRumJgN+/9d5B4dwaCpoCXU8XsR0hJc5Hh dfR/OpOyR7von2qfqf5bKeQyGcThIOowLtC1lW4mnpQC8XvFrpHHr0sKs2wuX+5Z/XD656gsfofW GUNJREaJMgdbUZ9RntrinfCWy28DRuesPadQhwXyUxyyPe2gjaODaTufUjATUKcmGRqyhfULP4vp p8DLABzRcwO6QKI0FgfdqMaeMh2g1VrH9dm/LmlovwVva87kqp85rhRbR23+kgqmYGnjcfXACaRi 0L71E8h7qb/ckUHP0jVomARsl1Py80mQlfleakbqWy7fC1xZasLyGwoStbEAMOs1Y8kcA2AlMLXK 1BckuLVedxiIMnfBWsNu4KlxV5ZCEu2GNhtLXuemv6P/82ks85PKnPOIZPzKKEic++gkPEGhC6lA W/gFpS4zM1ItKibuWnJCcJ6IXTjJXP0tEtiMEFw1D/2k1AAq47Jr5IgDTBTNUXTnl1N1j7KEy0SO W5+PXny/RzlFJOzg9nnCF98dX5v+ueuQyT6B6GIOaLljBpxO9+JiLmMO2k2y5bIYU03NBqYNqh5X gSjPUVOEKVPEvUu/WJVevS8YcjKs/1QdIqkDLthb1ugoUI+fi54fbmmBkCd3vyGitEdn+n5BF1q2 WJ/I/Cbl9id/YlsA/LqmwzVQfWDwRbEPL8kYqdeh6/5Fc0YGfBkCpXIM2w/iIgcj1aljIEn2ni6x tfJ/fElRXq7+t0Oux4CzwMMn3zbbCQM0VQkGr5HTIxYNFZJhdoF7jiab64UvdXm14Fg4/tLqEcrn B4OC1vMLfMB72PnB1UmcZ1rGgPiqsmozOUuJYdHLbjPu8Xhk7xxnNi8142cwlRbypeEurYloI/6H gPMXTTRWRkURkp/8QRzwFHLMBQ8zoJQFVI59s/AEBz1kuvL68XZd9ClUw0NHqlzJp5itf0baxVI/ dBAekyCqpbVeR66iz+DBbLeIKMaJjDcUDxc0mURLtnUgvh/iWSJERp0eaiRETbrzH0gq/SBp7lOJ 3m7b9wJtAI4LcjOdmwponi86J/to95CjftO05bPPeSIYdPjdVy/55FfupjREEsulTsCcWr1b3P5G ZnkDH1UU9HDWWmClIyNxT7ttD9JYFflfHPPDxpUCzYfnijrskLMeprp847OoBOuz3ugfZxfGYkDG tF/TZwqKrIvuGT43kdghgK1905W5lJqYVHaBkn/FIvXjTIiuBSQ9n0EH3bKR9kpJT9d90c3hJ+SY M88yvkFYPUr5BJWDIARZFXp4fVkryVaNMd9t41kEqV1C3cB/od45za/vJllpSMf6ktkKIfUjcl7r ACLwdSZw1A2tyk7lguLOmvfeglvx6W9PP27skl6iG8vAto2VTF+7A+kjUyPnHvhM2JBp0HhYg3p6 j0QIVofozKs8plAjGyUeRor41UzhO017+iYbN2OdyO2OQ3C6a4L3kIWZ7NR0FwE2fMmreKj9vv/W Uhs4q9buTNvUzNY+QxMm/zo3f7ksJbN0VckFbsliy1RvSbh3aT2ZAtMDYbXgf4Wpf+FCWXIuRtvX JlrR9y5HBFA3Uqm/3RuQuMAP7Wzv5lXeXH+XwIkeqbzrtLgWuhrK1IRf+tjEXp/PL6Eu7nw92Uiz sgZiDNaRVVAc62FdH0HcbRzTgJYZ5uowl1ZvIGprWFPE0VYhSfow/nRWHK51odg2MvS+1yCnousP Fw5hmimeA+RzDACokQj3aZy1iIajl9RqC/2TvBmKG/G4Bp3n+D0eBhwGfCpx8e6J95ApVm3cz3KX woomLApgfj6KFvztv1HOoRl2jVuO0x0iGvytdzzMYIpoGvmSMKIf/iwSTdkQ3PmF09krT7CJyL8i cpn4r7sFCXCKegu7fZ6Z+frY+kGdxTCAQqwydZ/IPOr33+sBC7Ym1c+2pC4rU+U969yoG1yEmHF8 E3qZfhPtkXn4KIw7GfxDJA4uQHcOE5b53ITZUnF1y8QStCRMxNKgztc+E9DVahQFKheY2T8rgzxC mr/RN8Rv4Csi9VpTcrEyEyTkn49DcW4MlEUc8R0D5nnx30P5s7zgWvck3GFvkbaR8aAbSYDSGU8M XOli3Ik69dclrcoob6jaMYWy7hZgqhMUkn1pE8xv74FZIF1l07mU8zZbQu9xYRhKiPAmfeAazpyu 41Rk5gQPEpIpZKNNN2FYHbkrTsrTPtIQIqKw70yT4xUDiOX4S8Y503GOfp8DYDxuokww/Q8C3i1o hLBrlmCkngs+HWebLofkWKZZANDYJBFDiZV/pZnvCW/9o0DBz38WXygtmISw7loeDUSC0TjROnlf PdqdqYDJj3HCzAGJfUEbJowizl/EwF6eyKJVDrhnii7oG1ohtR4GSlmDPj3/7LPmvbhkWClZRmDc KuWxyaGskvRL/dXwhXwx2chU1arudTieV2//KIaJtaVHFgj/S/DEn/UCGbr04Vrg2pQ7jrT/x2I2 dmxR8TLPIRcGMXAP3MZJ30RK8PQV5QMrNljuPdqj0ewPj+q+sYQjr3Vzy8fWDtSdbRtjjmse0Ix9 TRafyCbY2sFdnk/NXHEcYxrpIh5ajrt2v1PAr6DUtTHmx+mbVU+vW4uIyO1LH/SQ2OjQBEeWeCi+ zC7LBJ4Dm/oNrek0Cta+r1Xa1uECrIlPa4KlM1x9mqOsJWjU000YT6qf6Q8kJMA+Pb/SYpNQHvJV VSv7yMhEACH125TQ1sQ1lEOe+lfPDuPMDnnoOOMdAgV36B+lDD+SZmR0n1VqQSj0Z7vYybNvPqYb Lenm13mX4IOVNgB/P2QzEgHgWSY5kqzHjJy6AGusXo/prvkWg5GNbtj+g4TyJ2V1aYcSBfdB49uZ nBQLsqxzaIM7fwytN6agp4LbyCOUjI6XJhcXhR7NU1hj2Xed5oTdI2nVu4SD+BgFUZmZ4w8rIsgp 0EbdEExB/gl1IdK72gl+vLfCAobw8zVX4Rup84qPjqnhlhEGCorEUmFEuwFjhRFHZZ4DzqF6bcX5 RPQY/fewR/Z4Y6ho+M2ZrNcdjVCnAkjcn5ygMuU1UaseOt0YF5BMtPgx+f5ospVYm+IQMoayRvL4 KArbhOejqdU/o6gaRBBVxhCBYrOsPPpn10tDJJmffp3Gm4KYO6XQ4VyEOzxl54pVRfA3vpiyskL8 iBmYQnC10hM83SXeP8e/wGzy/rny8/G6bErma6DZ22YJ3OINpvBha6Vqul0JP7hlFQH9OK4/CQvo 50q0vCW3upDHnVd29vTHlrdLfewjNWyyh0wSLIa2Q252sQ6WqSiZeuykzlXHbAUjCCWcIiZnRFQS RSODWAKPs6TGbBr0sNRDQsw/ce/6jkDUJsfOxYwNgWPrK9xV4/WZ/rU54WWo9+4vCJ2D5vnuCUD2 0O0sTq19YJAnOsMKW0+pV1otlPaVm2vLeqtYEKD9i1FMEDrphoQSv8hZODNKaiJiIvz+gf3Ycv2p ddCbKSxhQsjalN84SbGoBT8jdVMeuIHkVxZBlRIlelfkjLTY04wCIJkWGQs3EfG9jIzbXmvzKMSd /9P6S7aWi1hiY+igcNY9LwqG3ynN0xghotI1ubgSmC3ckoqcFifAqaTXoX7K+i0YhzGGL9baZR1x /fY5ONCisvM4CpeOa5QI81uPpa4AdVzKVL6wC/mcRkPpgvCkWj/11zQNfceAezXMKvi3T83eNmQL s/iqoL+zaYZTdopnYTb1ysFQXXb5ZDpACmHdA85l8UrYBWXZVyNXGcx4rQW8G3gif2RIB7fLqs7l x7/K1WGbLHVLIoA7ABlIzpWBv7jQHB3e1NTxKYd+cSpr1kJrv6Aj8QzdjLUI/IT6fHzx/4eWtNdI hOhJoYMwpUkFKpYPtgXy+5xBoBDgCeHW5s2kEFZIJWNW+VrkaL30H2aYRiMX1peULR2XbxCg/t88 OFtPd5NPcDjBsVW5QQjhHGOzNjw7dDRv0iorJGIc3w5Breb+zWOGnyfAdroapypdQRBI6ZQDzIZj ge6c9C8klBo4md6wiI0pUufb8QSjoMgg/OmsyD8dW1jptLs0FO3zkZapuplSokszgJVPwIwHGUWH Nh69p0r5iBmh8NG3AV+CsTXF3HkypFav4/9Mth6SrEoPFMS2hM2Klp/m3IP6dovfjLVzNx/uRZrL 9ZTADpRzKXuQnGhWiktkSH1vKW+oHuL5968O3KUO0fedqsjMKkChrfcTywSBPBKEmxQiphYd9joT kxz7YgUmfo9BKKnPcLG0/X2oYhH55i8jj9EmayaAVtblu9YNYYgQ7Ovpnvjn4wVy8Tr+p34ph4SY 3MzuNVoNEIN0ll49E1UQp982YxqJ/AtPI3cn5sLEpEo0X0k75XwCgeWN4/ONctyIGY+dbhkVoz3+ cywNA8en8oIb25FvMCUyGlDl/5/X8CyRYYYytbu/W1eNuDUfzTAxjE509+xZWMM2Vm0x8nxyyziy 20SA7MA8caUHTuB/Ny55dqdGokU7pDkFFBjepud3gyyw3Q4jjpVhtDRYLhKXgfcdvZ8UgbK1/y4h HC5daq2KXaDdsFuiJQlVzDEOLpws5Q6zwWkFDaPh02ENTTP0HpS84L1QSTTqpc5XRn9pyeGy/c17 arMUbXNPUK9M4T3ou+GwdT/0iqUGvR2FnMJxyM/lxMrgo2n9dmiIaZWA5KdEZ3K7InFsCBMtJ7mU r15pJSh926eI7g/AVVPJwS99G1sNkd8FlOej9N1wBS0I4hxLQ9r+ozPTn4SiNkmpCNCXpSoeyvUs pGb9DEw9WKdNGX5f4oDARjdL/c6dFm2bAGkwgJqAzicCirVw6uSpZ7kevx2gaNREXI0AhVFvqiLj qZFglM7mhEaUFGX2L2x2MNJBFoqMqhB0Yxk010Al6OfRFtDIuIGP3/NKDl2Xcq1vJ2UGTzTYb5Sz +aIlqtxKRHcUIwCjmP7aNgH0iTy7THTPxC2CGT4AW5NQ7kB0813QjLZm503UWg5KmV2fGBjeameO aW7TaO9QVowKs2XEoLxUYYZ5EMFZzqJJpoAWgfDh3c6KIz/XcENVTdKJBsBNalTXlqeFdcoq+iO9 yIc5AJptw2acx61R3fdEcgFumXSU4ujUA5ck9dNnnpqg/wwpCTI8K/HV8Kw86qfUcCZ2RMtb9sla YeiCqo5KXlUA29Jk4L8kbSsOI24Wc9Ap9ifK+NdOebZxFtoUkUCtzXSvyI66/rHE3HJxMhkrihE7 zARrhO0Z11oaRO2sx8KzrRq9AwozhNcEPoNI7hnoBxFZAZDzFMuB3o0hGX9M8DGHd6n8jCyV2E5k hL+vdK2ZYNWHjWW0wWLUToO1iVmbFMTHshmqKWiKo/QJH13MSGddoKwVgJuuISDDgNaxBjE74cYe PzZaExxPvdPRHim0X/hFCXKTdVewRFehV+4z0yNttmAkrelNhGQMyCbm2iakEo857fnKyzeReI/2 jC4Fz5ISvX8qOAZKASfFO2V3RteKbJn1l8Xy3O7O/pFKllycXCCrdrfYDgFG9V4+DLVNtFQvGfhk iEVGXZHv4nHifl4rsm1S9tc7kthWqCBQBYVsOlRjeCXrGVWmSUx1Afv2F06V6MzOvyWtSjbgCUs6 m5HtBgqxr9HbueDwho5bT0jQC0OUj/wzaxvxJkMOLlxx4JqnRHs6EgesM+V/CGMJ8LVufivQg7Bx ycCmM6jO9YoT8kAiVcyICTBHj3qzUdPqStORwfacru3iego/I8yRyh8gp1LJJiAqmTtVQfAePylI slWw8HCKz4Ropf2tcT8x9tIWikVsBSJmhqIl/CNO5dc68Q3BD2eBuI6JMgTiX18trlCEVPWcTuDt OtvFxnQoPzz2njMzJ6ZBLdxhb4i7aL7bnXdPF3XvJJz0FWHyyNsbPLawMiXdI7tu5Zxsetl928Us vh9z0pc/1RQASuQWcWiFlTC7nJIfiyCMVPZ8XV8MrHQbho7LtbL9MGdWoXO2LbNw3r3xmNc75PHj 2z05TvgDU9LFTCNfyFfufrRZaTFiURPi6Um29F+E3RXPWzMGa5TUqIDIDSfN8Deij2n3orI6+n7x 2jOgwPVlS/CT9TaOGASq5zNlOaAn/8zM3i8jKRCv7Og/MziVPlbnuwoZvnCOutXDCGpsug1/Jla5 VgafyYW75plQdFyhTlGL0Ot1Qxt4MucA0X0Kva/JksKOuNx97bnbU94VjWAhqg54f/gTllVhuGHp SsdBoveosrq+NIGGGJSXK2wYUXv/SdeuSZNRprMQZsYWksg8Iz+bpgVABELXDvTNuZCVJp0h1g3A 2afY9z6hknwDPkwqgyLRUO9Spbz4+HMmonicsGM7coDZxOcl5TV0CNYAFC1uAI3gOS0WNzcVSnLp wlgCSX1J+CUDiM92drgXfiNjjpMShoaj51U074taeHRywCLX75n+CBexoXoP2rSxXQ3USLUIhMAE NYBTH43kmq7VlN1gfMdZRinrEs+wCQ040POFgk4Ql7ZySGZ14iG1tc5Yln4eAZj9n0YbHrG3zfFI JYm6EqobDptRWq+DThsMWT5K+CB8uVn+HtJR8oMDP+t0uNwT+3QvWKr8yVkgPQ4dfMzSEV9kUfAK cAs2Xl/zrAKwEdmBYzImHGjvXUhaYPuaT3b8M0C4R2uuYKkHEcMR+qUeqEx7SD50SBtUQQa38yJs Rmd625m2ZoWi+LJkt80XI4oAX7K7KJAwEjiNo0+zTWYEWt9ZrICV7EN1ja20d10YECUA6CLTGYP3 94M1Xx2RjqPKQpQlvT0fg/b3Br/Ckh2c4lLpmQG93kdzGbuSOpEeHMVSQ9XlvKkCb2/7s0X1VpsK pIbKoVmq5GwwadzlQ5t5L8M7WktvP4OCHdK1zxPDqK7I304QxIFWuyPD9rgx0WFX0tUT6J4gmzDq ftdti8/jwIIdQJa5wZ0J1ecgIWHXSZnqRLawXcyilpn0ueCjCUDu81XYqqkG9NxRedj6lN2tgRxm Cfh3DSlaqCDC16FAFyQN+e372HwYbR+koVGkC4qrhsa+AumJUOX39LzZBMkUR9AhAvvrF2IEzw9y WD7twK/HMF7CM7iQRB56iOYAq4hBGQs+zJZgh5azhqodP7lXwvOgijRDJ+2brXOes6ZFYTTqSsa6 /BIVYe9FAsdxha+M6Wwfo1CLpqatzbIF1pr8lgxJKpsWIR5oiPzuF5G6gcr9YiIMQXKNWyY2eXxa jIYdhUIRsoGSo5rIcLIWmI2dZBzNZDtgsuZBqf1Eqs9tXRAhJnJFcj9rCpq25RmNjUvbQYrO1Coc WqPN1ehUJLyT90vp9IKHDVPvJwlM5H6uWB1fQySOcy0dqE0/grYMlmM8h/BVexLPOzwhlZVqcBfr QUVDE1RGe+aSbeLyhAOem9Rfq3RvUHAzxIxayNqvXa9tvlpYajyUXbaWbxsGaoXxIjIyfw4oWqWn eJDOYI1otyBfmrOHOluRX+vRkXkgXgflU8Pvg7JwfdHTa66gyE3MMdHNv+eu+idcOnN4De6Vfzfh mzI5NYvpOo+YinMhl+OMw/04pZoPF6g0ku2QPTtW+nADJIaRVCBZhegvKDLUcoWLjc5rR2vvsyna zG2/tJBQ7xkewVRUICPwBU6AI1v05lnzyaRyQ3g9ChlcTxZpGWRwzzwSMtv2LFTY4wPKbWfX8/Ir Er/lsNxxqaeRGqgYT3+MiKK860/Q6PMVXAjWAXJZ46rSLM/Szlna6PBSLG9yLVsGamMtyz87kgnb aplg3VKAk8obVCP8kHSBa1hb3FIcPpit1Jik8iSQ1Sn+s/o6CRQriQwnCwi0+kOgDzfaxP5Zs1br 4CHbRMXnnPk0s6YNTVhnzwEJEURsw2gkfhqui575vGnVk9yKtOPSTQMIV+OH2lniVGT6E5s9UWe3 ZXAFcnZlcwQJjdlsu1VSwADFtoz8JQ5iGLUZdJjwXIcqYXoB564FsWo1oN9DH2cAd7i7K9u2Ewbz cpo6UAf50Ekk0ZePSE76RT7nyff7vE2FXoMxZPvVub+l2Z5xzmbNdtwy5uLUQIkhZ15/iUU3Ixr9 bnHxLkJnJUvZNbuvN2Qp7iPlPe3zuj6lGsTPsOICmk8pYLj0P9glrF7HmMjfp6EcHlrH2zOEXXFQ VqLW9G33lqrYCjIXPH3620ZR+cl025QD1okzZsBzlyv0z5hzvO9kpMBHfbcV8u0ytXb2LLDDVla2 2NSEQRWkcPFU9TIcjKNymGxIXRault9S4Gh2uACE0BIoX+ukQZrutiy3MRMhgHm/XDEu47u8J7gj MuBFmVj1p7eeDjWyiCFFnVfaqbQAhAaPHJCV8EZKRh5F3kRnIRdVZvsYPp/kMDxx81Nb0KhyfuQQ pHOVYV/Zx64Z8zEJEVxwqGjQC8ihys8jb23wUzkOBii7c6KyJlaxSQ3mNbRHc0k6x2Dj1w/Xm5Jf 3crnNLLA0GEG2q1CKiWiVRcJl9+zAsOpM3KVyTaB35pVz4GR0FA5dy2LS/4QEKMXWsAXZlVfI7aX BL+J3fJr3fBS5xGWpuRwGJq+jfA28wz14Cmhyzvju4PUDG4KRBpBGq4/nIj+C+waqmop0LVm32M2 zVfrYindnagSfp9vM6OwSnxhepsbaorKX+Ys2w8vT1SYINjkpxb6xBDlHKs5qCaP1NMUB0BinYzd QVEIG2Io74CQxbRZC8ZjHBuSRBy0lS9od9W5U6SIsHJJfM+lRNKkt34mCDV8Yi/4yZCd/ujtWQWy v+OPDIcbifj8AZUjZbr1oQcz6810i5zfoZ2IHZGPIVHPu2hFhNXvD+lKiw+a7VRCYUOVnpaDdkij c0EfoeSzHmfFvWobXhzQkINfX3jheIIxUyxiaodhBdJE7JLRBKj1kt0aZKf8GYZfgvz+gdwpvEHZ D5rTmPS0chrhOd0fXfM/JNhCsPcSA8Eimp5aLoJKXDDHZIedLGgv5goWAZ3zhfoEVkNgL63t8B/L U6PEI2NEQTw9Ig1E0La/CtmnaOLx45rMtrzdUmM3A97cP+UZWLUnwcSwABt3RadP6vOy3+aYDEyv +TYFS+ZTt2WVn4s3TAE0lMWhlPR21b/nn2KXTF1WM7BCRMDqAmt0zfroU1tgp1QSPIqm2kfdHJOQ AjKjnv2eqXKlVh9ZZz7mLCTojpEIFiye3M+UJalADdT3zlTV4ZUrogCVI2Eu09RGxd5F+IqBXYFg GmQ5zEsqUnx/OjsvhFlPy0uQkT+WuKyF0lxOIJ5Qws2vnm4bIJQv1hShyI2XNfMpLrE2HdxluzjO OaV4lpd4VdQXrwghpjTrImdj/BUGYnL7Gon26Ulv83HsZQRZadSrOuLrNAt/ezKsfF/m95RN1WNa jEw9HhBcGcscH1f5+2zC6COVumuSeL3udUaEyqd27zUWhHb1u2fcXcv+RSDTFZA7RLpUOUV4EV9v 9VWqw1K1IGsNndZExATbQg0HS7IVuFJOYzUkN7ux8sjnIEgCf7cvB2QW350x3Ywuiw1acI4KUJmG b480i2kptmbFzSDRG34vxxQR9sl4isUyToCeuO5EH2XYxesRg+7YL2NCUR5M2e4PnZ1tdNslExR4 6VaaSsDXNJ6IV1vnRdwrx1OrWoiKjACetD363PobJ2ErPp9wDdzA8jPCS9utzr4Vcq8BUsS3/0LL DsXsRSnOPI0NDtl4opcknMTUDYp2bP8nYDSHUE8V8THG1z6gOvN9Qqt8CpWYqEVMX6ASrCPUb70m XH3pHg9mEtAJRVUfm3Ud1ZyNnSZTDd0HTz/tT3EzV9TYO46ea4ZJLwwQdvoMaLwSdrBD0U0kziXU JDSE7gZ9X5d/XWd+4wNBnW/ou6UfIdps4m+SYjNmXmhlXxovcFu6cxuiMeWOh7Vncq2jLQOGGjvL 1bPR44oiWVBxUqPmN5dUwBsvSDgOA+mk/AcrbZaEdQ9hVMUUViwaA7v6MYeb5otyABSMWNEErvzo xOOUPHT4tM2+81Jzsf4Zl7eFEIAE007MFmZ8l10GBOgi3ahyZzCySISe95FARCiSG56/OmJBgwyg A1YC6i8yNDyzLIff7LNh8ItCS0nqq6xvDBr9+Sp0PWpIo2U14+fWesb/2Lo67TixwtI/4L4QOIT2 Y5/DiO7KxjHPK6lF/H3h1rja+H8/AoPVqgQ+95RDtNNr1l1ZAhyI4s5pzlgkRT5LR+Eph5tYfIcI 0NwC+Iz9gRsZ8INRiImR/lfwvUJuPJAQl8XGB8wyu0tptcGqF40Y88U0JZKKv6hnUeX74ZuX5IGd qLEACoRWlRVEz9Ic6g7F9KNtO1FDHEWwj5Xt1BLDvbvKaLA/Q7Tp0Vs/4sY0CPm0P8ho++qM7ljg 0A+RS+tCckUs59mlXAWmZpm1ZS2X0gTWyCOQ2cz/u895eBWxWOfbihc8B84LbmLoKN00mwsFzTIa UJEsyV4AW0l1Wm1UAb447rHBdxAY1p6lpj/kUoMi3rGpasZQuM6wAYuFuSqg27yJ/WxAUhY8dJYs BmV8KPa4aAIr415F1IsU/MCCbPPuQ278/Pv4NXzN2mCwyIrlOQGhkIUEjyLyKrlVaJyP5fQtssLX JKs3cewR1ey0hMJ/UCG3iQ9h68y+P0emgq6qdML0VuaFoUIWIzun7Wt+X3KaIYfWM89q2K5iaYWJ /PqPX5hZVrHunb6gqSoLcY0niG8RWO+xZbImsMUqePc1tvjsYNoOwRmEBaTHmTn71NLH/rH2h+pz 1/1EGAFG2bWymuLErNgsE29qDgQmV6hf/px/SugI0v1Hov7Ly+wUA7X+zu7zPwlQN/yPSQhctN0A vaRLOckdrUX6ZgfQ1MDTyYa9jwkNLuceIWXw1yOAqqjw8Ivf+qq8QKGo1NNvyggQ1bMBuC6rSRLr T+LuuQ0cBifBN6ea4cza0iP/nixiujUulNChM0q+0waLVEQpt1wK3wGEiXCms6GBzyojh2XWkDzK xz4XwR3kw7aCR0Ui/haX4hv78DMf8syRPGTPgX2w/DFXLEp27O8cxLa/kYxiW2zubH1+bgZtVG7c irg65wtvmDlN54Vxfe6mbUjwOsOW1eHasgkf0mXDgJNRYixjQ5/74dTlWx9F+ILiI7Xe4DBRIgWg MAF7Wn8QUZnZScWCGoJos+sQiePLwG9vQi5x1EmXO1IIh5JsdseubjSgMCryCTBUta8CeNXZ3g9D y83mpH6gwamE2NLGzwEDRnqf+O9ZdhGa5j1IY/W15KaqWAOYWWsdSAtaoZvlq8wSn/pXIpAjwJJT gG4UHzikjVXiZ8vdQNfLmp7MJiB2ceFUQP0D2BHZUM2LSBS1emjet19hjZjiMkgnq5Elvcuoy0Xs YQaTNE1mxVylJeAd98IcImeMTFC5FkrqebWAhusiO8GG0ZnZpCHAUvMBdd8ZcgqhsPsG+HsNZZa4 ReA7RS3YC1LA0GYPDXZ/TpVFkQA6SYGZXo+RS9X300LVqIGWJK7nj28y3s669vO2KnjTskGK4y/V mAy58Ma3QnfyJ5SOU7LX6v+GdoUTV2FYbp25FNmZtNSww3MG2PmVbkrCvsGdmaxJNKjF8Euw2Wbv mL1zqbShJ1aKOh55KfFafqiLRkQOpeXFmzu6Wtq+OS/ZqSeniLhMvVQCYQwcGkeayvpKYZ0NqQ3u fOBpoVf/kq0Z8PRe2F7A8Af8grKm+mmExluufbejBAAWWr16sGlWjKhkTjb1AdpL3hvkEhzuo4iq jjGRrffsHTtOMtHvksNUquea0UOIcz6Z6OsdAMIq2IW7Oiu2T/42+VIvQ2kCCJKTq48GzKqPpofr A4jR+FQ4BzJD2qHkej6fV2VgT3KMTKyqj+lCgHiG7AnfS72lmXxwfsoszPAfnk6SHpkMyxty8PxA FtVouwdBoxnJD6lzPn92nE3NPbceQLV+8lC5yYNNRCDCVZYy6fgk3gMdNRdU0vhR9FcZV1lyOh+J /6xQtxh0U+uLmgECvOHc7OMQyHG4T+Mc5oLLo+xpkpzO27Jd4EDuWRbXipDkB74K/xj0DbE67hJT UC8Nbj6/BDGfMmB4cfEmYYUMf9k7/o6hfIXyWbF/gR2lUzNVpEGImsZBu1QGZjrKNo/ycaPGYGd5 KklQM3/RO6K5qXTTaInDcSasNQEDpVMg9FBDetOPixV2u+7p88ETZhX2MinUlb7vZwaUpR5ZtQa8 rg+Z7meth9eZCI8tUgyHxKJqSF9xUTQdrrp2vj8kcWoYse0wwc9mfEH7CsqMwMP3jn9HHPK02vCr TtSoEEyoP0pbrdc+wuCe51ily6Fsy4KEsvUCfA9RQlefSIjHVMiOHGugyP55I6pkEYEpY2fCmIiY nPkfSaQqPQTgdU9SqHpyoXfNfaw87TPMQcgf0tLXiSxfyGyW2kNJfkj9LCxTj7wGnHu6bTRZ3wlV vOgVAq09xBzlpxP9mXRHBAh5udljGpVelBpmA8AdRTe07ygT2bs6oll5lyhxmz88pOCpbvb1IEqQ 5VkI1dCko5qOH91R7YZ4ZN/hCalO4E5HJ+yhSOUmyYP6zOxlrdNHoQh4caVEWlO13o1EdVNQTqd7 +vFIWGklLVzYMfk8O0fG1923OZHHzbuh/bfOvrKeKqOv/s+6GxdonPf+RPJn6LDXZWo8IPxmGZky ku1Ly85DVAbhC5HDt0XYai+V5STL+3Q/mj7i0kky9ls7smwuu2vaxef3LO1+OXXZj6OEawyMed8i Aboyx4DaR8Qlcolrfvwh8sG8JC96wtXYKO0KUvVHnldnGdTS8+epd05nRwhWrCIq4ZoC7HTup3Fc uD1ty1vHzyJaCf7RMJp/zOtHrnV9fZ6mDr1N2ihKxRUQmMiKzkYGmxPq9wRYLHeODfaMDLYX1Ig9 becxn3NiH3fIp1m8rtbsgjex7Jb3uM6dQufmPk7gQ1ejqqoWWVz9he24f+SstDCQHTKlUGDZb5JD FBDtDFHIod6817BRnMqTrtZq0qxp4njFzi5iCiVkdBMSlwx0AWeeYnJ25AyebIQlNvzo1HGuBeRl CSffuIUD3zXex4JrqWRA9aLeftNwYqB5FApPpmIQetNe8XubM2pGZHcc/FAyoSVPf60atl2+vwm3 6YwHys6VjfcmcWr16OvJAlIbDi3Gzbje0xhzJKkUCHRnla/r/vXCI+xVi4w9GspD6ZN4hiii12Ei gJSsMxMWgUcW28GvoT8jRC8GbN3LQ9gVkOYyfpaEYkHt3TAn6I+qtF8cTqHd4iOA/kEGNtw9yGxY UJUYgl/sBqwdOZ43h8961Eo1g3NF5/IF/Ca6HdLklisNvYRoCM8zOzDyGGoqONm/CpWOBBjExi+x DeOLpc6cIawsNPzMUaGVGEnaX7ovaCTaTuU6HZRu5sAJPgE/iPwm7ZKSXXufdaPpWgdbl/ume7j+ HFnWjrW6AsAnydfXixxLDK8u94nVbxWFY6E+825sQdhsYtFZG+bhUxZbnewXziPfPDwbc+Zrwxlm yM8MPiWWjEQQw/1tdmG1VGy7rlzDE0uQV19W6Ue7WN1bYCbnSUFASpop8qBWs5qI0t3VDgjYj1e/ txs4rpNDEL5hKNpfbLy+gWtcpJ/qT0h9XIzNrIp+Vabgh7AeZtJA75iBpT+xnXhElZRbT8D6EyTj 1Re3IOFdGM6lNZjARGFyZ9y8mT7bMrAXzh01sOjp/uBvu/8nJY8gK/mMDi5bNGA/lzc1WiqnQpw7 duZ+wAo3quur4P7smYnWr9NbIyYAdtUt/4ao9vIt7EioYk+CQrYe9ea/jFaZ5fz3+S95Z6WXvZ5N dfWK+347rkBo7eBGRbxA8D0Z4S8ezzEbYf8IvTLujo0R8rlWqPtxFxt7om1Ah+r5xUKwf/LEs4fX IEXvUVa3zd3oq9rCP3E/OTTjPZ60I0vwIFOfs4nu9BbeXfmzmlG7LpOT62p9qXqR4pnMnfN8x7ln BQBAWaydbK2hd6nWfyGZVOUp4pQ70Ec0ohlPL7d7Oh3BPXKRYm8T6Z0KdbZhyrSGHsIxkxXjembg bLstQaju8avtPFwQnpA5kRShei5PAiKRTAysrQ7fcdzTZZOp/f4vUkDvRnPBV39qvmn20z51IxQh zk0jqgGlhUKZoLXhUnuLZl+VJOw9tOGrCCC57q3gWUph6r2vzL/poUdN3ncPug8D5OgNy7CqswY3 XjbB/j6+YDTp2v9u/tk/7JfbF8C+x7R6w52EbEJZ9ty2Zkpm9iZo4/V0lSfV4SJMjk7wQb9Y/wy7 jP2Gr/bsbAuKvGn/qG7qehCdwHTZeFO/d7LIIGuMn/3gytlHzf2tpxp4HmonM2/oL7Igiu6YoiH2 tdarlsgF2BSqLYGRDvIiIJWOSVG49S/46vlRRySrqpbrOD7Z3YZDBIsVMeBVzv+VQZfaNCNvb8lO E/5gud//9KoYq2vaXCaBKEjzwhzhj4fqnDvim64rPwATYi8jU4oibv2oUIcUSKS3tfszXnzRl1z/ sQO7/PfnYgmTQ9zAWVw2+X3bgK1aD621O4J7N+hfH8BX50h9yW6LTj1TANjudpuAtut8pM/dx7Mz cYIJa2tRDSPY9uM5UUeg1g+wSaJoNeJVQGndQwTf0MGNl/Y9JgPPNdQtSzYK0XMXrhO4jBQCrRIF 3KxGCX7gdwHiA2JWCHeh3qgpMsF9ozsI836TU45Ap9Z0aeFSN7Tgm3IhdtaBECJAcFlMT63ACHFV fiUTLz5AnxPGXQA/c43FAPEGYOkkEL//RDsGpOtLG78oL6gMFcXhiCjiuWYhb7yEah1u8L+dvneJ i4y/wBWoyF/tFantIjEK5owybo20/x9paXyv4804BSB1DwVGTiD2bbmQAFCX+Q/zPppeocFdWAN7 QAcEk3uDibfHRNDjv6nT9ZjVSjtJy96vStp9monejoQVT5t4ltejwlnQQr7HNzk39gvctSseKphB TlRsSrKJsp+XyDcsYlxn5IQO+SLv+1n7YVUv6cejqWkf+MLxFhvJ8JdDdOLrG3xu6KKVXeWvylUP tRK/FF6SmjeOLqPl01ITU2mdbORi7HrdIU6hxcko6pmVFxELwkDTAMiNXhHdPRdMFIVCR8ZTEK6E 7RAX+R2OEWaJ6fGr4aDG9KcZiGsKLtrA4rc5Dz0UiICzxcEK2sznDAU066jDhaXWQwx+HpejQp71 Ln125jtZRI5B2SissQwgO/Cyady2QJKyPM24rtcc1kDl1U1KS1JtSdzlzCrirWu64g5gIZHdo+MM vs6L20YYSVyQizHri/Vo0IKPtuPqzgItUjkbGEpXfYdVPS3qSIAdpK2V+dlnsP/BAaJf+fajvoOc 2VquaNoPOKf7OKmei0HwKc9d0yUfv45fUzOaNcD+hL/gfAmMfiRCxniO6jQXI4flVf2ZHQo3F7y+ D7dHEiIrBcg3x9jICDCnPjhXeFtfMLLqzvjKkuI0mc50BQI/Yt2GOy4t9YBE3cYJDh2m5R+JVt5e 4I71LPHWW6+I0xSndlyc+0aXxc+jOOJHNYfj/KEVSHig9z8OjtLneBfy+PUV2iR61QGE/mVNW6xI AtdSEfYqfbavQsBK1aBipTUf32B5eRJEG456QArc5VAN89M0iCKmmacXY1oymYfxmdLuslnva5dG 3X6YKwcqEjzyahdWPQLyWLCXbD3dja/20B2NM7vcBymrl6Y+5eB3Pocz+EfkJ/WQNEOPMOBb2e6p NUUfYsMWXWqQVGE/20T6gqHZZFTiR1jgyQBV1DoOCw1RvMmMHlp448J3Zdbg5p1Aa0aIfWtksHiP E636Zy/IJBo5VHeBEHQHoCQYZ3CU/pdtZvTY5An2836bxSfGeBMlpSWkTXpW48TO1hVxUPquYYGE JAUVOpVlL/mUWSfTerkPWcrTlOIBroI9BWyr5RrexgSS1cHf6/mdJi6DLwuajVd7Qnma1vyxlZMI zw/wA+cyHDeak87P0LVyhSceWSgx2YxHujUeuicKM0bno18RimlyuLWgLc/Wi2h3Q5nldlAQQnya IE+nXzDmvSNuMmmhlsbiS+zreLCufu9sA6wcfSYWwdKICHf7pk4Yh7OytietwTz52nfKX3h1x5I3 o7oQLOD7vccXpg1EXmsYYc67YyxJbT8U4rwxAGrv2t3qanINT7WKJEUP+Z9VXnZzqxtk10bkIgqA LsUV02OEKeaWNVtO4lc/WjjHVMtBsa6Fe9WZn0yCHwehl+76mnQ0Arrdx0kw39SOhrkIpRXZYTQq R7NO4BKanDrQqc9r6thyegCXKojDdhOv//FsLv85Bt6hD+ucgxM0QCHBdOAfDKZBgXoFTbmzQZ79 lDx8OdL4mN1rAYCuEzDS0YX0r3fGTFEKRB/4Svw4qQHtL5MQirLAuAOm3qG8n5mVaAaOlrmQ3dRI ZPrag5577syMyW0djwW0q0NEK3snFeYLT/cCv12vXTrW4c6ZW2MD79oDn1XL2KFQbGLkLg4CkIXN yR0aBJSBL44eNznbcCSnZ/SnFqnzfiH1rS1F/vu6oKXF5TjEYrhnXXI+TCybOrzMB2F/7eeiLndL nezkVoegDTJVUHyoxzMLBpTRtO678LIeSLC3fmtrhMH8uWM0dvoThzRFqqNKdwmT03zjXEhGfww/ Ax03cD/tTqX6VcSLJf3mLn40/2leOIBdq8aDJX2E8Dj2RxVnR9w//A4LM83OiBwoB+R7gGCPfGEB OEdY0csWXn2W5YPML/rX7VOSJN04m2Luf/ZpZR9OZLC+MPi2WTwd8i0vMZV8mqzyCNmS/7INwdHO NEXB/D96aGJIrTlrW/6IQxKxGygsQDW+Ak4/YY2i/MhV6+vVyxdfrx04hor59zHOFl1j6mgoycIY YkKVJ09h+gV9yupoek+SOTAwgGrTd5rBM2H4n02BIn9SP419qa7cXOQBc8R85VY2M4yTTL6haWNW LQNBywOAb963IZ/EPY6lnN0UOABIqtp57MSkTZNr8hnNJSodipo5Di+W+2mh6B3BJVdpMOnVrC39 fRxMxu8XEnPkLGqADb8aRahRnY9NUQvbxlBOvRcyGFB06wNRW0XZXx/0ILWT1pjuiiuc9QkqDbDs tkjA5k2A/Q4EigWzJNftXN9vQ/eQCTLQ6BGWmc2wMFk9EqEU5xwyRxivJW1uWoyGpum6ZFWMQCOf fYKd8zraDF06h1JJWJ2enQh1JyOm+M/+6p1u4H9XKzuakIAMFeh6MFhWCXCkX1HY6a5PKTKbXt2o Wc7QddDzRS16JKK+Pwy+gZuF0PIX78Me62Heof0CmrL66eb/2i9PWABiU0qOcqN8PmPBNKvGAP0S zyIdtuvBGPDHn+Iw4sJbXpeR7FtQ00k3z2SPNvvhP+FxhXCbGWWa9d4OTLShLeIqmmlV4TmwsLSt yxwUKmICP/fq4Ob1KqThpQ3CeDsQrjmBB4bnkiDQU+FhVhp9/EvP3RFAGu0PxCnE4Xz/0wQBv8b9 VsENAgDqzClOF4cO/qLc+TMGlL+UQkIuPi15T0exFXb/RQEvcWFJwutqJ45ZQwUva58i0fkSbUZq 8R+aQpwfSbfkS+eZtwTh5PNngGC8amyWsYZPbIDetZyoaxjgE34UlRE02RqLJqLRkCZUMGKUO2CO PDJ5QOUab9PogYdhYC+NEn2DHGor/bHKnQ5m1P4+0cHRcf4TEQefLkT8AEUcgZRLQTuHgaloljA4 2DymPasRsQDE/t+r5IVG1b9cqG3zROuSrok1VdrSJf5Gox9AcQh7iTSeBQIWrbACCgyPz3sniELg xwTcV2mPoGyUwTNQ8CivnJJpgjf2dg6Rs3zEJhKkkqae4ZWOFCt9lfSK+5+k1gYpWa12usvnvZRV M09hv+gf/Y/KBxdCAv3UVQSpwOGjhho4CnvC6dXPr9Q81y74zZiqXGzhHRiV5N0+u8OIhPTc5SWb mM4/lFGSGLO2SgBquTk5QFIc1YmYCKc+MgLAXgW7Nofymeq/5F9O7LrSU1xzVutOzOIqP9dVqX6p XNrvyeHscIfnqg9AiRiIlRcqpMXDCPJFxJiWWfW/1XPkA9UeThGwWCdp8i/w5Y649OmSo8w6u1hX Yu3qldIeNhQfSxYh1IyZIOGgwGd1RIx0UL7YtrbJ0KddrZM5VMbrPMv96/NU4Adkmixxp5d8d1y0 Hy6/Bz06qspDZR0SJvqZ61VrYqKpSlRIYLD1kHzKayPGXms0Ge1+r9ipD2cL+bCwr5PAeIFGDx3U 9WLHKnCDzT9vljTnT6JXGMpx7dLZzsp/DAE9EhYqFMO3hDZ5LjQ0PZM0bzssQmR5riDUPNu9VnsF Uu/zBamKtehztk1Sp8FO058Wmj8zCKn/yFNIKxU0pUnXB9KZDP3z9zHk04yyzYUWntCQytm0feIT EM3cIV3saaUYys2MFbXobuRpPlZSCnX3ldbAvWSwNksMlPpGTsnHQZebJvbLPLiwcDhPe9jxtYZ1 wy+BgbALpyKNeUvPRmQaUk1OY9Rl2FNx/8CENGV7Ytc34kDg9C/FCaC82Ytw72c3o55OxgIputby 0pMf7FDXSjurI8PELuvCvdOHtMKz8EOdiWk5G9w+1aByu96QfFqcBEfpLjX1G/o9AYNP3V9oA2vl 7GHCETORp4FisRn4USsftifva5kqE6a7h/66Jqll+yBQG4Qb5eYKhb4E2dBPrXOfQ4YmkHrtlYb8 e10zYPIOcRSeZLnRlA0xG4v7L+bF73e0ujEqQtCrMVmMOIqKsAb6n/dPpBr++3vqJ4vxaP6LxS++ b/6I8llNgX2Uzrt7CWmtsstGt8prvmlMYnTUEfkIt7qE5V4pO17DC6Cyje1DFhOdNvZ44RGiL1HM Vj4fEjsf+GDlSjf9kCnxc4tVKUp4mPd0cKcE8cd3hEoebgdEckTK/sPA0IavrKOXsnP2Pzqv4R8h m/LbEIH0r5jySxBsZpH4e7jPOfSxVdxkM/kZqJ8OGmIAjE87kFrM5cV6Oo85x77R7iXa+knvuZ7A v+/cYMSOCnSdA4OPqYgStk1+pjkXztgLG+9Q4UhU/kSRbU3KgZbm6eFlVex0hU6O5QmMvZwGDFTC junCdKPlvkVQZYo2k3DVcf5zOX7pQ2LBsdJuCRj/qOd0HWeZ5Qn2eBCPtBIxNqxhUynZmET+wPc+ I40p8bvV4q65MLouF2x/eulA7C21QR50zaMdgsWq/qSNehQsiMWHoisQqq9i196IaxuI3t4XR7vt xcfibBwCCS7H/FhRcdCLHo1cj7DNZt24iZqKtxK6V/YYLpjojwGnT8zc6/pdyrUaQI6zo6da+Swj t105ih/ZtN6J4+P2iT2aZzn05GjPLQeCDmWkgV6+4xknt4zBH3VTt2ChXJ1GXMnINsbe0eVsaiJ+ 9heD8L7zXsMzvD69tCOh0qOcHFVyJP2OUJRWtWUskiCt7kNX6jCPD/YknKtaEDyAb+DOEHZx9SSO X8fou8wKJ3HXy6+wlpcCIdq+OGoAqxYJ3Gx02fy3CqO0WoaRwahnA3HIniqURq5DpNZriXw0unFD tXJl8Xqq+0UriWO6vWd5ZdVnDfRdjL2+A4qdaKSg6D+X+2o8UMyBdMSc01v1ypRhpAkFASgthZnc vaaJsYa9B4OHk+cjww1UX80zQFrC9qNaymEtJHgURgzsUUBz54dTjlrUcJlfJpq4flJf0yx2/d3O eq4cB0RNx1p6PO1hZ+EQXqfXXmSGyvH8bm9hYXxHGLCN6J65nNTrgELXFsuKqnpXFLiFcZM9Lu8f tN+kdozrjF7DEtg7MhqbILZ9UL/yferxHlI4mRrkXLhK5RwyDgh1JhIPqoS2EgK/iF7q+CO+uwyd 1NEAlHMhQelD4+SDp73cxgQ0fp86KrTknZYRNWg/BFcErztm6nxW8awFUirlUAh+8Cm0f5NTQvOF 2/SOCJNbpu0vbXQsWWVF6GtfilOQH2RTSaixWY0KYGGgSLISEvCyD9zsSEIl6yaXB98Xo78DTOvm asFOrrVqR15yuwDw9agV7HpL+TP9nrmpdlwFRq0eXNhYz+A7CyBzhdKCKrz+3vQfBBa7uGGzSrgB uo16PPLdHg1ZAoucsoIrSAZoP+o943HU9BG5CIJ1/0A4H5h4BmiFH6aYjHUdjIsxbY/ttFnUDj7i 0GumnGwEmP+GP+Nuk2m9+ZG1rYoOdXU9T+uN6ydUF7PocgY/kjO3KpC0u7vdKEyw710lIprRNmBL 27rFkTm8eHgODvXektfbpu2xe8nCIys7mLhGBxJonKnimNDUzSiAPnnTasqoYFZ82E8/av4hToU8 XhfwWLcxXqnt3K6DRr1tSJiyfLgxyYKHNvvMYNNK2REDvKLUNtSEUs39TvJf4b9arFkJhnItdjWS 5Q8itwBdZxLxLmsh2ovC693aDDvQdS1bJAgS32A6MBstj39eEpet1BVYAnPpu0Rbj5Ik2lZJhGE0 KCosHk8JUqS8bKr5ULTFyXogoQnxKdmQZbcBaaBts8qnaZAmjiYKgsAZkT/w2Wli7AImiPuj4/4R jZNOPcSw4wq4N62wTcoU1K9YA4oBFl80YtwLT4sLUvIDXt1/gpg+zNSCfvBCbfOhYBWrGE9zc26d nG/JqVxtxFhfa3jOAEMydkrNSm1XMji4VO/uceHJzWdGtWA8I8oE9McaqxPpTVrMjytYxHfH60Qt kuMTgklOMMw7wVJpvGp2TfBiidoZxRuyjB4TyJkQcw6iHNt2x/JOJyEMrakrigwdIENc0YV/8jkW O6tFsZYXgIa3Hj6S1eQSzzkgegZKUfV0lPhuFXsyAaPzv1lDAwWw4aj4+fAKdbo8SuZTtvB7kgr5 JRV+CQLf5p2fh7DzB2LFiW5nAeMgOidAr9FS/hbrkKRT/JAJiJX4EtNfqcBb3vPyedbY783Z1a0h OotFY8u2FyXlrW9U7lvb1T+ye1NOe+YivAqkY6DfOM3PGNOgIMxGxVuMzHPmzt9NojEuqwdI6OIA RHbkPGsCGnvgTo/OTj3O3sUZUFGUcqqn6SZj7XzWY1CDdUIYICy9aTOMTJnRjuNZT7o03e77MY6r /ZXSLlJkAs+hs4SEAeH9yBDwVVWBNxxtDkZaWlAMwmvVHi/WTLsdqGZHM2NGlByoDTbln5L3kNG6 Q3+A8479R+7ypVkPrl2VaQJ6d1K0Vjl+j++8b++Mmet7iYxotKzWXQruBLtprM4VjoeCsRDGDl4c s9eeT+4yJAaETtJxlhHKKxgmj1C5EvHDrAmNku3z4hQNFWS1xsdMDamzzPvktqdOpQ6FRolIGMJO DyUOrdyVYVKUEhUXaIpDo1k9vZWoQsi4vWGkHiZNq22O0qdC4xsv4l0Wzr969+OkzTMocACAIaKg WRh9l+w7WYrGl6iRLqq0ZsB7deDOpLl4oNo86ExmxUlZlojAETdr+S2Ry2HThB7l9zHRajTLUP1E zLDUPvYLBAabEBT+XCzw7mGJ9i7hn6hiHerOyttTEQpsMFSMUhiW4wRRiRctax3IajaNlv5yq9nJ 9nOGjrhzP+7WnSFAVk0GfWDMmAlK8jDLYqAMvFQHzdJSygJaLqvIv1a5MaNoUgFPVkvQhTu2jby8 qKtGXsd0Pa6kXEq5gBXr0a2cRszc2ptk1A6CF4Uh/jbwob3PokiZghtpaZwOqH+GQpW772RDy5Nt mOerSez1lRFYnOA+sUUswgnydy49jimyCN3Uq9FfovqCfq5bWKapuFaQz4/d7VibDuE+zgqoLFZO uZz6QuyieQONgh8Kr+Q7BVjOvmdHWyi+fGdb7BCKQ4rQ2smaKf+vPN+3AG/BVV14rSAatRmnr2nI o+rD0dZl1MeQnmMnIRv6ul/UtpYgD2xGzqOdfGlWx1e22me5LNZ/gU9dk0iaSxHG7MWphgmH7WGl zuBNxY5AyoAN0Ppx03jpAwdVFoWffaUZ7sBMRICfTqh6WcYPfln510Bhfda2OMziK714A50iRmX1 pyBW0jUICyy6uSNXvWJxMrR0pV1bGLD1slTguyz68o9ob3ObKnWeMDoMV/YCPr3071gYGpvrzHcw JA4BntFhc9roIB1pVpPF5+rz5RtDLZNpohk2ZEbd3yWqzZQOnnHofxDpWkP+9nWUbZPCZGwQ+7dh 1SL3iVYLgUivZL4IQMOHQEDTskR973YYldrfq6CMNfIGvd1xolwgko+WhvtEYZVRyRmOmov6qzAG CSAN+GJPEEVtiYJ7d8NDmy8fpEzePqpqGpa0i0hbGxYwxuzklBZ1yTFxt7Ml69AwGbOOMSElXDjv 2RdJBcK0XfoJHV6GrlU7Q+rG6e6000DyHtKJP40KwlZhwnY/xLb/HD4s8aFYEZJ0F+gjAKy9wcSa VhoHvboLnWa/t/JufLbhPMwslMNFClIKEy0K7LJwaDAzb7Ty4ISGMAbCF9tybI+433dC4N04Ylbr xSCF7g39IijW0lWn35N6uRm/bEw6DPc0LOOpILL6JeICtzDN7AOncgbbSEXjjnW5b3ubYgu27Q7x t01ZJBl3QbjAQRHGTvGanU3DzvtF+5WB0pmEYSTzuTjghSm3hHfm4touH0dU+lgCITzDdtUAqLAk PaKdQ85HbmHZYQ9CiC1OaOEgMrookRvr/vVwiBRL2vRI7EDU3z1eJCqIwuu5GUtz6N9aR6+qT5ny 8TFBcGhO/xr0kJJr7e3Teh2Ahd6dOgdZZFvunDuLyNQ7d069492U+4lgCRAEsTZ8YTXJCqoPR66O nSdXcYLMCJ4jWUNoFQKLCq+1mrn46kXs8KS6bm4RvADMesXSFqifQ/uyob4kTgqbvGPuopD/Hpk4 e8LO/+NB4p9a8f3/miN/GRd7FL11j8jo2RmSJOC/D325ApBbUPDulVpoM+NtUzEthBljh6/A9XjS SiTWAZdVjffj+rVnPmTZ5JUGDuuDHz0lBaNLJi2jcCH5wNvvT4Reo7/07jKzzhL0fsuAxpF++WE3 fDI5R204iBqZZOcaUpf5IJlGTB2i/6oVmQ2uSI9ENXuZ2LNwVHFQ2kkQ0q+vhMUgjWcmxYu8/jOJ ds/dgPLtfVquzZSohJoHgSjiGvRSQLz9Nyfaj0uj3jlPoG6N+KsRUmuYuUrM9SCQ1kjR0INHn4hE iRTFWRuf9aKzbskMIh6WepCVK9bwSDyiAeXGRmVT2BwG0Lp5GwOfOOpjIn5RfPXGcmnEJCGhzO6X mmrMnAtTX5WldizqC9Y7NE8BbfmIBHGIKklv6Ax3uoEeDJ4ofYlCJa5TjGvFDR1fXnLP/0OAYEw2 pDUJ2UwGY+nWdQW5lZyV4tfmYugUR/VeNaKv3waFoN5s6qwyoorSBkKTHh2P5/npFYEN83XcT+tE /j6ot6RBn1Vgtwceraxi5Rff+ueVlwFU+04K2FZa7QuaufE9qyeF70F2+MVD5tEsYrRh240GGBPf y4py5vc6xiqE/6N7osYPv7MhS/FADAboFHpPv0u5BuFCeGESG8A32PfoJ8JTUQCELWew3fUN7xWi 7R+axAjzE3Z6BlO3scbB1zZdV6jSp8KPYsKvNXjQMbYR3C8dj5GTryO1FItpOFf1id+CarKtoTq6 S5eFG9qBxtA2FKaeXfVszIDFPkqgwCRZxc8W5exUy1opLq+SeQyTTaSgFo+e0HHFEDcvFLXhBinm Oa81I4NSL3eB+JJQ6KOfA9bx/jeYEZZ7C8Jg9zDJngmxpz7gJzul0P2JBv/xn7SVuCQLTO1mXlAj UqtgZxgXKzslYCPpj0SUlYZYiXA7a7UqDxckw5vGYGOCUQeyzNAfOObZcjgY+qQVtCyO3kwm9nLb EwxIQx8bq6oO2HlFBnUr0pbY7uGG0VSntnLB4FMEsCtzlaF0NkqZk+rZ99s9Ezm844HhwQ/aC84e T5WhHJpmcXPDQiGJHJWuUspQRVu9FcCJfvUgLmnZJIz89/rESHd0lEomgwAKFtcEtMNaPckiXjwI NFOxHGdBr5DlqPOhjK1KRbQJh8ObzqYsSMPdTZm16ulm8cYe+HF/8XorpnlPwsaWcoHVRycWR1Rf 24zEnbAOXTzlA6og8/kAYPp3Yyny3D98/Bhwhm3hM3LAKsIEcLiK5zlmAF503ouH1BlgrCVrHCMS ZW95Uu1t2CtcHGMVDvOvEWQS84SnVjzlaq9UyNgbe0RvzqU1CHWn4m2zX0qIkRuNIMf3zL9eM2Ze zXCWMguI+7+6oU/aYNZmRX5ojuhDCUKrNz4FmdqSw9THaa3KBN7duiljnrSQbzHQEulcScQU69wQ RWZC7jhNNwmzhJOaJSi1nUm4cT3/MRMAaGLDG6aGD419cu+7gm+OXhdxzDH7SaN+qrBd2HVdRHyr tOFEUTXxCADQG+joVR7Xl+jHoaoNQMX/i0joF86KBKRmNVqQUSNnDKX9govYdQcIXE0eQLJI+CMs Ms9qK2Qn17n2Ray53n1IsCGvPX9ZqL87TYxqSQrIVljUfhRQ0z7qeEJbcx1aaXqUL/TFKHBr8i7b q4BID05LQUNjrIpcUkN5G/66nNb+EDOwZuyY+VJ1+xr3od9xcjR+y3A627AgPZBjAOWT6GVCyqpX nbGYOyFcAfiNJu6NuH3fRMbnkvWguzIvWsgJ8bFdDiZ+toLvSRuFhvQuO95P7NDBVffXK6gIQCIV 3aOGRjxJiWEeAzrey4Ktojp/cGqG7JR8UyXxYEFHoMa3ANb4KjTUAoJW+IPydvds2E1pxaAft2kg 5ypuLJMqLD/8OvSgdL3EM4Tu7xtQBY/oFYSmUCbFQ7E5PX2DHQtDIKPMVH2shMT7pR4j/jgMsuoO WydB+9REle45FpHzSiNApaPoE08rsUulNI3toJRVnoxkM/Cqwc1Pp9k0W58pRWdu1feuZNS+LsYf 0Z2ZWbEzDEQ6A3VE88JzQyffkE56zUeHL83q/9YTJZcqdSHxxUUGU6i9E0w7fYM+yREGYsW73G3O Y8KooLQspTpYnk7vqXjuzGxKCSvY+uSuGKS+BhnDGqvNP/vaeJMsLX6Vn39aVv4+T4JV7CMiLCre To77QFuJGbxx+d2yExnkk1vk12qsMiMrGX/BpYlRvWMvtRUdKuN8R/C/Ze+z7qDt7bovJlAsMXLw AG3D5wZYD1dSfVKV3CjOIGIa3e3rY1TXGBJ/GkugJCtjStTE+UKYUAa8qeK8o/AAYakQpSycaRbK 6unTacDhihgF1ixwqvHl+XtxwGfaJPcz+5b/z0w4HDl/gUe3JlidQaSwRC2EGaBCtnMfeEHleRfz ImGBBYqgsTkyqckexh7vYsvqcgP2s+pM1ZybEDc9X/iOGIcyi1RG/QrXFcrmQsmwQqFK5eCO+OjB h9y9Ys6+1aC+6y8wjpN2tpbAkAhHIWKlthYGPaDY8mfjNhwvJMQFxAn7VRZi3BHzHpm4XITmTtXv JQCamEYxN31vZSjd318PQyt6BVc1HvMEiWLwZ/s0gb7fycE/aHyu1GYKJAKVbpQMk8210t2oZHuy 8BWBJSpCar+adxskUOoPi5RbpPhsppPU/eo++ffKpF4r1M5bPOy29KEysnSGU6Q6V0jQg85rtyU0 ZypYRF4T+ZLdgPDLcLvOPlCiTnLZKX9m7IPAE7eHolOng+RMD/JtnmA5T9GHikG4mRzte/Hi4nWR TS1Ctyr+6ASY2BELJSmfy2SynBuKB8Ig6EGO1g/dklam9HJu8XfEHOtWZQDvoQ2JVAQZUhCesf1A u/CDJ4wTZLKr7Wqxw/7ANBXuG9LplBu2GrVpC/7AfsW8clTtlGUEAEX0ECri8Yc01FxfUPbi5HJu UHz1no8E0+TNsyVZjKU95tAYOVowDbMnVlebirl+/wX4hfOivOGFtSOIBxrcQJd+9UTZm1hkwyA3 iRxvW3WAAQmgcOjcVGBHDyBLP3kN2v1v/ZxYYQ9jjwbVNolyHqbOVrlprB/CfOipZIVY2bW9UYqX mOt07MwlFbDwZZtQOmnX8f0KyBvkAjmuBorkGQ/5jC7Sxw8MosO//pS/2Fz9BG/gbanY9nKeNRDJ vBb6Au5IkXtX4Qc1J2hrMXO3HfaNYyXEZqRc5nKFpG+QhuTUgHWJkfnowDcR9m62R9qGy+yp4+o3 hJsK7p5S3AySq2/UIrrQTR7sqdYEpTXwE/zqJzKsRAOIHS/Btbgzc5+3+HRZ0Jb5TzWYIHsQj4N2 fS7rPsx4QpuE4UBV25gsaUovhYZVb4L4Pnypt7IV0hfTJAXD5Q0/sr6QFV9BGXxvS32X3LRKukHS oIxPqlATQI7PRIhD51n80BnpsD2avj/id7F4J0Uw8NYMlg5Lz5jFZOIHrQD+W7t9yBHR4MgD+3AX geXOxQz1BPRfxy2pKPlk4yIsWTZxzuD7PdEh3soY8B3wi6r2xuq95zn3konGuwZrUSMO+T3WGPx/ /Sgak2DcKfks26/YXVjlTJdiL3rF1xuZZ4zsr9ajzsztKPdy9UlZe2CcacsUtUTpujaDQIBNlcVP oQxS5yFx7FymdL7VBgICyRNZkMIGC/V+RRndT+GMgWHYaLGdbTmeJV4/xL76H1j63ISQhff3JS3/ vQe7EPud/58cQoWxkD1jck5NqCBU0+svQXsUqE6+pX42T6Frw/bBBuaLRScgI5XM3oZG1vPSPjhr 9uIPjMxkq6NIYJBKJnKshyjDaB6qzlSc7AerL+zAh0iDPKHUd/LOg4kBZeX6pV4t6emCy66NXT0W Ci0NK7nXqnOp8dlkVf/pKoDA90ANOZzD4s2OHiCFzj9u5DTJT/u+UrvHDkz6bN9t/UAeZXfa/MSf F9rUK8dcQqnS+oF7ZL8IesDWVDK5loW7JZM+VFAQkUmdg5h0nRuPR+My067dAd+/M/9pPfzrPI1z 3hcPM5PewLZvbFh3J6Dt3Sc9FtwVlz0aIhIKcQIeqGHRyd29UYcE7trw0duUBpyoBMeHG2MEbrEI DUIiuaXXjlHr5507R4EU0nz5OSYbVRQ8cqt9yWNLYI6BbYT1cXUGII32yfghmVbLL1fP1BlyD48k /tRlANJArQk9Qbv6ZS1P15AYvtelxrYCbqh6K0YwsxINOEtZarfP0kvuHP5bljrv+YOrEq3TI1SW cBjldudCOzc8KReA9TwxT/2bNpu6mqKxThBdzOvqI72DntYB8ixXTv49AKLV6c6sPLE0bu9BipAE 7pwWkzprwI3sNNTYr+7FxhNyN3vX6NbQT0P5TdERacFYPHzphjs77fdT4s3wTg4UwsaZk3+L5hmP al9jzimNv4IThUuW40xLKI2B2/lHa9Z3BfQ4v3dEDhlS+L7Z6xPquIPjXJOE2YpmAuC+56l9GRYc /w7Z+gVPAPB8C5poeGoN8JwSv0buMpoeNjepJb3OmxRPgys7LNII3WthN66A21vp4eVAoUVCv1jI JwoTu5Y5dNxHLjf+iCQa3F+du2l/kwVgAsV6bmvtuJKiyAjVSJhH2e3CDk81VOm57TIpYsYqSZhz BCmnqpcKEfrz7YXUSjYRSUGnSY1MUK6eR2t3PJll2vS60CbeELBkInh+iKSttkIbJEVi2sYOqkTZ /PsbbgCvJ/z9B2o/bCOV3p/ifK5nS2/gdO6mSEkj+gsqBVUlneNWhlZyeSpxvWOh2ov2IlHCDljh 77UXGinHa7RdP81HhqevXKojE3kZOIcOfa9Fe6zSkAXJ4/uF8WN+dIvgUxumdQWGOmbDa0vi/oFh kNOFa57Qz8qzglxVoE1gJftS/z1hvI5dnVqPKKAcZrNjSIoVeDWKNab9hxBFfr+slKjO9L9qHRM6 I8WYpPEQYJAOkEucMZ3zqZb4UeFFkzRFowb3bb5toIVPOA5x4sonBLGCyFqKTbOOwB2F75j6pRy+ UJm2K8nzQJ6GWSbskkkAoUGN3ZC4jNveogX88fmGFGpk9yneghG4Kvmjp5kjtQymS/GqpQ8XIDI8 FTuG5HViT1S1b+EQKP3ubFb2yhSFUHN3Lzw2Rzj69IbfMMjk4GLdztqq7LaDJpO9HPDgnVmXJWwi MvTi4RHIS+KiuLmQZedF48rNnZ3mk8MhZ/QFZzDQGMUjXxlg4TO00nh/j25TnZER3aW5zYTN25D+ MFlF+PR8880M7MHkRq5HAhNxQl51SgTVypSDg2b5YwRfc6JPC2WajtmstVv+21SC7EL2Ysd8jnWt H9T3jg09Oh9XW9ajr31DGhdiOh/dHgi1i/1mrI4yTJPBYvwvPH7iWKAzYbhihCLDBkutltRTrZfl esEbn01ZcbdKfwwDiW7mnfqa1gr2+HVmQMR7TSfTM/iUh+jc8Pp6e+nN+tcCwBbVc8EfQOwMIAKx iE+czsFBAYTjjG2gbB+nwxXm+HxuONbsZfNvgxsvtBLAX3Y9LASqZmHCYidg/nezQmjC0V+B3DSD GRF0D5h3BtqgCuDdlW+nuopjcE2hHpYV+j7+k9KPPE8UbpXfUQ8UFKqpCPOXLEUXJgYY6es8L6+k 2VkW6+qwkGMeO0uelcHZHw7phIzJvoWCWY8x1A6c+lV3DUH0sDdpfq6oPIkD5QPLymRbnrj7awg3 8KAffJyvdXuQ5AoqYP2fvei5sJbPwM4MM9pa5VQDANl0WpN4N+neOJSS+jg5W0eet1FEO49Ho3vz 7+agb91oz8T+i9ODeEjgJKNxIsE5jggNHbQB95d3rujhCKA65/pUX8VlhnDSHb67BbfGwHnw7pvH 6vlhEJvL6vSv5yrTGDNO8EjxcRwkKX8Q+D9sUEMUGqSzpkU8hLkTyEGJvTKnPFUDNQxIdzcxet+F Hc5TpDvPQOyJ9Wmilf8AmiA8UctGDVFFWQoLFylRv5roJnAWk6gLzJE6ONWB4LHrj00p3i4xnDD8 HpP/RI95iO34D5KXnlrzSKMD8WBRhS13jAUHeXkqlGOj2Cvy3Vjx+YdUS8t6gOG78DX88oQUNoGi 3yfEoApQk/Qtpuy8xvxdWzkZCqYDLxtv4khlWvg086xM2ihGfGgerX2kQuGcuyEg4LEBocBdRv2m cqLPRaGpYIZlQVUnRS/M0K+zSMRTaN/Qz8tcsYB8OFAa7ezYCBabMGrHgWT07ng7/UBhH1jYkA6n U8j7oO8CYv9kzcT3xM5zET4wG/35nSSneZjKcG8mAMRT0Dz6ryXkJSL3BaMARVl9bstPRlFCfIgK ddOA2HBBe24ioM31b+RYRfCDWosfYpVxxqFQ59w4Bq+Ecg1l44B0JXMU3GZDaUhJ1skIl89l1JZe SlwExO1hmOJ3u2wos5LbwavRGCBPEeWe5Aaw2de9ZOW7UKRB0ig5/bZWErrRmHK8uBJi+jH1YJ6j vRqtMIH/9KfHlzSOJJfH3na/G15HwZTFjpA+5AkQKLJPbtjB+EG3fwEu2oZLROobpZg95+NjA5uX 2WV1QgofOU0Zq9/RcPgtEavKUbS2dQLYwFEXEUtfMckHp1zv7utrVtsuTNF4x+Whs+jLDpKBGTV0 sIkmtt+KSBw3/Gg40Ie+8ifWmnKmg9Atfz4fEYGbIaOZerKYen71G7kIg1277SLMacW0zXUtXCe+ o5SZvwLiKkKxwBpAQ+bPlp9+IRNwH9rHmYkAIdT3PTV0PVldwe8/WPN2ZMD+rt5L1PEVXOLPTRLN WfG1PJN9is78aFZFBikGKvBEiSz5j8fpDEO0t3xRb4IiweTWpZFACYNh8CLw/lo8nbFmpNad3B/C swZcLBx7nu20qm1K84uoOAUaEV+JClBd2R4fcI5iITpycFg5BKK3jbS27bOf5vfMgA4fsMwyGJnG 5ttyxf6L5ficVzJfIx3mEtXgDCRUl96MRgDAsMXrGpI8zbCEcc5twldjshd2hImS2Ch4uivh9iYO ejXW7SDfVQTSuJzqECHLYZaMgOUV5B2uaHptP4yPo1i4+vaWrgakJqS1F9VxJTW91Okd8yXt3RP3 E3jirqbz5/yF8DvZV/b2+x9iPDGeTDS7pOSsHM7txrY2ftiD9kxU0Dkg/k4r2lw8uzqjiZWy1bDM cxmOzqHXXVBDmJK+kgz7KeHRWi/RW4lcSRol20mPkDLSKL9SAuyocdzDGWbxfCtiPq4K50efAu6x 2cWAwhFtnDF3xpzZ8PECc3OfvY8qdeDcspxAqhrHeQUxDJ+n0rQ0cS6gc9pDwhUWau2Rh682WYQs 3UAJIbW0ilV17FVs3ssuWaZP9way2qpdwofaM/f/e+HkdJytFANT1Q9i3Z8vTxcWksMccFzwpufl N1zJSCfa4Sx46syiFY8xeI3Wqr2i59VEMk9NjbOQQooqHO9aONBsczf+/bFmtFHslDMj2Tugfy8I OenqHMgLatuNImIZPUV57x3kiNXa2E7B7OQRQ5861QEg/YjdNArZJYKBTpO44lMMyeUbA4J4+DiE 2n1pgHLJNJt1v81hKAmHOJUe6slKx3fDoSMnAIjsyBemMjuTDmjPVSNNzKH7uQr29Wm/CKxjOb11 TtTZ9YyhXlv3hmyKjw+/lFi3iQKE9BD0mdAxWZVxDpwjuKuA2VGQncl7eBrlgXmmt6FM0k3rRysA jUx0fNz5/Gwz9tGg99E5mxuztm7xg6ZxXbjHPAiEwOVF0PX0uTqYTs7TiKUkj5832Necnt7fAkWq yb9jNACEAXZVHkgYhSYqxLGaFPSseL/SxKtHW+Ov6wKFbDSKs/RzqHXwIie+HmKwIRkzR99V9G1M nvXRQ2VrfSQCatUhu2tROvDWBPqV2pISzkEcD5KiSPUpVjSzW2RKx+Z5snN9iPF4a/z6SQBHUBHX VHo5mZs5+6+z38M8xxDwQY6zaIhMNlwahGte3mvzRhzx6XvkoirZb/o16ck8IM9wMLFg7WC2zqHN dmB0UgY3arRyavUt+aflb/aCzUpz/mOzXCbq9eacur8MZl12ZABEb9tGUQqJlVctMXEw3JkN3Op1 3Rinfh164UYaR9zFCBU9SL7wa6JCR58Exc26mP7X3m/yoNa3nJLkAcoDwFK1TBJvA1pc37hG+pVB 7g1nj60aTfxX2Ghe8sQn11NP1FHFGKoC/lUDKnRGKm3xPcHz1MXqtJNT+cHc+19AoPTtf3SKoidx 6ojkpn4FlSo1rsh6RAAfPYqukNp8tuk2Taf09FiG9Nqjhxlt1S+0qgFy9rPYV3FwmesP4/vqrHLZ 6UJg6r4MWtVvQ7pJI4x5OjeZ0ccDLJPg470V1yTM7Xw1KHqWjN5xwCnapY8COk4ibweLo5Wgy+O1 SBG30ufiSC7gnxCkXx9mKt7CT3Mvr1NdLhqGKoRFx7R8LE+nBGtX6Z+0gSDxLH7IKfclZMAox9Ux CYVM03z/4rREFnSupl8h3lSW6rambjjayjIExvgGz44dX512/hVHlw6pWkArSWj1pNmMqj9fwtaM xM0569G+JK+/W6qEiLKyvJKcNKPfpgu1wqTLGtFZp5aVTJziZEEOVg7okrgP+FlSuByVooBRkB9m ISHW6KylTsiUh4S8d9jbxXMybNeCsBsXiMsybi/lGHHfGpCPh5CoQfD1bcrrdBppK+bwKGqNrEPr Fj9t82yA+fOA4Ens4U8e33gG/oo76ljHxZC+E55Jpr/036CuRAuLK5j5A5wkBKHTW9qExvoLxKVp 7420I05zDMK4d4SfEhovBRM1A+3p5iDQDQ1+0j9rvuaNwISQ6ohuwyOczyKXB+0bQqhMnZEWz2RP /TUbaAmMy3LUSeEpSWQKTpCtaJ/eCgl81gDGX0mgxVNxWpG9AQfVkY+S0ZUtVeB+6yw+KSZXuY7n Epy9ZkIHitb5STeCfoyWfipQR8pPsr+3SYXjQ7mZJ2tLI5iz71XlI5ZP3rKCz3fQlmBGzJ+nlIxm RBMjZKVMCU7oeIIKS6pOgxMHeHZ+fh2tgM0PlTNI6uH/ds1BGLRghcFMH9NslT/2DSBZ9SPfsIgt KBoNqWj2BBqs5HzbHaU7svS8lXlhkfofNFScS8beVfw9X5brNkwbUkMY+LddQSEmwGeAK6P4bTGd I3dwphX02E/MXbSMl69QPsSb0L0y/URlc9f68GYogTjm+f2SDZj25seyIkTvdxuRufoweWBR0e26 MZYi7nLGQlH8gZHhzf6/dOqhrD+KYuAcDIRlYmlEX44dWrVKYj2xAWYPIo8FFVDW+/QvXxoRMNvE f2gv/uQ84ljtYreG571wfiwQZGswgC41Qx88YK9iErbOXFU2tJu5g5cKR/TI+Vkod4g8ES6RqAcY XTirmTYMsMszIQPXRJlJ6eb6FbYZO3IkCgLZVx0X0eELBPwcpLlZRfEx3BGQGgx2V9SMfH5FrPlF Jqh+c8fTFXa9VSug7L/VUGavgMIJSFGozCZWdlgci5/npkVh/oFebQfAGHapROq5XEVYyT4u/tyN 9LE8dNCxLnYblLDke/Ox2OyiLWq90fJ7AeqLto//6B36YMuRV0Sz8TAil+3fzzcFxBnbJ6a1zKHz tMIQRNW+vHEsnsSdGwk9/g5MRDEvN4VBuw+Uevg5vUzFj8q4X+APg5i39JnOfFRvKnID5/ikRvh3 83/KgaoIL0AA4ICVgH3lJqXnZAMsnsVIOpVbY10XagfiPEme59J4xszA/DZi/VAubmm2R2xLaDQK P2RDHSTY7JNxB7IktUFHD0AqxbTkgRIh07iyvzxMnvsr6w17nAg2Qd6NwAudpPLj1nSIVSWAiDZ1 eO2TUbZBjBiA1eR9GXC0Dp27rTI7bgM5puSdfKyTRrNnYgX3/B6o0ere1svHLbAEDqCvppw0GQdr ibHOHMrYQJl1tbu1dGLAldDnF2iOmVRRr4A4fTxaoLTQaVXM61nWURDYPWansEwY8/xnFu1Q2Jfz SoWfe5Rd9WIPPgNbikV1MfkDP5nRcufpndPGohpjbc2PF0ZlIWxQmiJt7PoIr9vee+0l1/fEDIiW coZfGhWsVFt61VHmzR5DkSHh6BcYqFrAWcMae5plGhrokxYLqfsdslt4WBBjbKZmp5iIeq5oTkcj UqSQ/1qWSigsl+zBsMV440dximXZ/eRZzjflrr416dvTPHE06bwh6xM162CNkn7oRrcAjcMEKbti JcA6+hizPEgeRYuVZ6k5jB9IayZkUT4bpUTYi76kC0cCk/az2ExiE5P4BybugrLtz3ub1Kr405WD mTXfkkcZ4dmS4GRv2I9M0j9A+eCnwEBNrY270I492axEtw6UfGbqStEDL/OcSZvwtZocYjXTUaKT bYjP2MbCr/RX4j9GteKMQS8oZFOWOZsKVMiHxtYZwVtLxDSEpRD84bveAAyevErS1ZeLtLKPYO1H jz53nIS0RMg5hQln7ZUqEQwPvNbMBuFWvoae2dL0BiMuATjjpAeKDXB5ibonPIWK3+9zrJLCmlew qGbYcZeRqIGkzdpL7dZfmF5nG1R9FI6chn9bTJNuhQpQ/fr+Zv29WWiF6LxaMv0Xjncj0SWqUju/ YKjVIVHzVJFqZmEUtn4YfVskqFn/S02vodM/JoF8Wsp/xdHIHBBujgJCskLEPmR70Ht22IsDigjY HgISIMYs+eaJE9c5UXuquxtVvV3DaP5w78qg8A4/hS4tbcEoHZeYxBvxCSLtPSpFBYJ5jieuvG1Z XrZ8nGanwdiOJuU6doLuipEcbg+5hM2O23di3zeC4ce9DBboMQhiOmfWStAD9lWLQY8C1oGVA8Eg IAvldYTpAYp36LSkSZBirlYbkD2MlKeqmeWghR2gw54eR/OSGTOv/iHCbe9DGxVXkw7KCZ4QPoPM S/Jo54sz8gdZ9bPEkI2uZrI66fIPrhwDvioiJWT6GjiZVFWsK/O1uYdpErChZ/0Eisadu8GNArmN QBOTfcUrBkVneY+51HX0N2tvBYIM83/rtv1Vlu0BwjQZ8MoyoN3jabyDg0MEA3JNXekXYnJ/WkFb wuGUXvIEY9Pbt0Z7pHi9juqkSc7wzPcPgTzKmMaWoOkA4YIgtzXPvKKk96Q8cezYMXjR2x6Rweqo i0kY+EwNOFMtChTIBs2codVTFS6YGslbjyfxjYyAOoX8cxWaVY7iUxe1ThQ2FcLK733okM5vk4IC pq1JuAXXlZh4AP/MSV4nnWIUoqsy1BAi7KRg6sgKMqSdk/YOSUJzqqufmFLs1JU2KjF00Le1AHKB k7CqkTwYXIfzjz/oD2ICedB7bRkpbnibv48Tb3SbTw7ViyFdlgTVifhU+kyo5kL5/P0YkukEcaEp EKoiVx5Gnf6rBNJZZkhJvcrVK7fZaGTNy5GCzVuj9rWMaTpQjle97ivOm09JYleUvGfa5+MH4Y/z wcUy6RVR7jGppGFJwPZSoJoY40VLuwhCxDzLAM36KHjo1374ZaifCj3oUxdBV8duD0oewRc3ve2k +au0A+07ADK6OL63XgoXD+2UZq6Zx6OQWPJhINw/IJIw0akuGgHnmDUoCsYdAoGvW8NvXzEovQ2I c+Lb7oaCgY9UnUnQYiZpVHh0qMGdYxd1UbmFCQUYSU65w9EGu+1/iCCK+8jGZPOS1F8paTcm2BDM AVOgrciGyA7EuIi0qh/WA5jyQelBEgVKL8bifkD3kt4Cf9fgWfnG4VzAn+qBC5H1KqSAbRf5qYFW wSOq+Or4OE0q+j0l/4bXxoRCX0AGOnBicqLWEBbUtPNFMZ84XZvqY+LChYDge9K+q11nEyiohi/L QxFOG5hHJivLJOHxY1XDakoVVG3O9R7rSy1Fjxw3V1AvCANmsn+7stSxQOW3Riu2Hn9E0m2f4XkB IklZLtxyJHn7b3EQOU2H4//Vu+r40VdGhuLyY4hTESquvR4sX5W3/UYcvStw1qxXkl3L7s+aINuM rSpWRRbcGuyBSBWbIf4kAtklE4e+GfhtZSFFsfQGPSFZT/oOW2zLQH46vGwGMmcm96Bn5euxw/OP 9cC4d/mPU6rO49o9L44RZGbZQfDU9tZRHEY50R15uAh71upKT3l/biBgWcrxXiOfPxMQ1jVoSitb 3eHK0+XBhns7zBkH8VieAJ/pXr4PMn0Bkjrr8namPaHdHjowqALkNJTxUTdDJHOrZTjeeCh8n+5P LyWJAQ1M9AQo+1whKJYZxSM5a2v7eHQKtRcji7ylzMxucu+l0DcyZPYHRYAD6Y4MNOuqRs6ThIlO d7oOyNr7pk6c282sU5ZqEXZa8bjPGmfCySqbPUs0PHgipX+b7Q+XCPtzFDgP9zC6MkUS8+F6VOK5 bcCymaN3mQ1+GN1FCV/Vh7vZgb/OAfnAB29Zci6pF+HtdamCzwJUjz6HtARjrNjb22UcrdLWn3Bi BdswLLWBCYwXAUWOXB8B8Y93lHuNOlEtU/wjpEKw/B5Qy12Jn/WkEe4R4xWvBvWwO1XzG5jmeRb2 KlsxbOGPg6mygnxGDv347kDbJxMlhmCsJRfsafxHGe8yARiLAQJ/od7XGIhC5AJFFrRJb1LbgJ14 +0Fyp/D5Jkag6xv68c1j4KLm5Rx8Vto5NK9bJR4J3WQR2+Z7E4fR/Su3jYawbPYj8xmgphefD0e1 ZNTXE6xAlhOaCGDmYoUc7bfnCeIGg2rybyvgihroks79+rg6+uCGU/sqORKxmK3FHPkx9Pvmv2ft OAGChnHozQ1VDtjP3fpw1lY1r+7pM3bQZs33/xc3+dEFtZXizE5wbKvGxpdLvdu1nyDi4Wv1VdFb X1vOVRVtoJr+HMriABTCtJqPYLCoox8lT5mqwC7nvyRPlI+9HKpi7JGc3teBQh17DmpASGt//FR+ KxPovYUd62cRH2Pt4Qvm7TxNLPB9L9ARotFnC9MLxxnjHisx8lTLWyxDMjpU3OEpMNXsmEvfBE2l 5vbE8ndgnA7iqk0CjGYcdKGppLma4fS1UODv7ew6RzuQAR2V9J10uEIFpiGFWHK3zyL8+Mi49q3d +5qiva8mJtcOvcZnSc1NJHpOT+RfOJWQdqDA5t4JKUwaVKVKpHtDYeLYCL8fPplmqwTM/zVmD4iX +FXEsVFC7j+5Qng3GVWe7LLpx1pZ9uhyfnf3SvtbTj7L/Vp7L2j+aHGT/cwzdEmT3uhL03CtaN+s H+0TQ8EgxeAW+wciKmUrqoH0Ee5gntsrNF9bUVRp6aZ3kpGoEk4SqYHaY9/0Iy47X0GIQ0ol/faZ JN5A8NS/SY62ExlDzYtqv+TXoYFxZvjBIL+wQnM+VzVPZXDHsFZ9+FsQnKwGg0mtx/oFIfryVDly FTUZbBhrIhJswZLj67kx8A09IC6/lvyHLwjMPpDSZHn9ap81yw2YnFHKMIaEvN2sGMm+VYycyBcV uGGsznuSjH0GGdvz/+y3Fu0DSya4eXItlWYoiMBJq8wNzQGlDVjWwmsbekRlZFYNtB0G4qyjT1Wo QBMCYV8ua/HkHFsk9E7huolJPF6wy7D5ciaw9XnNDdTF9IMOvkd+OPAztvHlHfhITPSg6c9zcRwT qWzKF5sj7f21gLRJlpCXpK1TbtHgI3jE93OXChatbSHZRslkRaxWD7h39qMdEfHhKIF33jPH6G+7 WSDTfP+xwdmf9x/VqiZe6gaiZHOknf3TQjb9BatgGxCWOO/UsTDAz3VvCduCbPsR+9p+US8Kigd7 uetpwFxTSkfLoV3DKtShjpsMJyOJkgNs8pkgZvif6vgw4vnvH7BlL9kWnszfnnRjPGosz81WWdjV UR3v4efr6PC79UjS+ek1ZgEvn6lBHz+vmDQTZueWJXHF70Wul1MZu54cXB4dPzp7srncN44u23g9 KXd/lfNfD3lzvpCKWFL+P6Pe+hwPrXwbMP2hgnntyFHBJLkWwAidT9rikyivdt9Xsq/u2kRM4Qtp aUxmvmxInnVbI/AkVSKEYD9xhYzxFge8Wn06+YWtQhstVFkUVdHgSYhtIIxnVeky4oA7V6BnK6dn trf0Uon6F/xHPVDnluDIJQgsWOKoDx+59wgFBOzz6cjjZiSj4Jr/+L1A/aEloD3ezhtGwtnoMu5n kx/Bnsgv+Glc71EHie3dqMzh+HLdf+yis6RONHJR0TR373g8jC4VVLbFbpS7ArZ/3xnta4E8gr70 ZxlcNWYK4aKR+hFYE+wpgUvjpJPx82X+mH2hBfPHTJ8BYihoIjq2L9g2dwAfzd0Ajc7rfFK3E/LS nIUaCnUGX3rO4neDEiwBP2BKeL/GFiLd4aOtvXtsnBGvjpxXg5Riul6hFTXy7HnNeKYguSwGcAzr wn/1CWYrR7fzkxPwDHGRsfHOHK0FcjE7v+us4K28nzfkKvXjiCHeVuJrtUc8YAJQoUR8jyC6zDa8 e0E8eL8c+dgRalAZNq6BajE4gsLp5sBVGVzMfin9uhksNKVEIpUHObkJoukObjByf0dTlpo80utE 54PSrCv0pJhMls9YLblQVvVEe1igQojH1CE1C7m2CP2JlG+r51PfWiU2xsQhYMFKs4ezSmwvqOjG kKtPxQfBhxxShVdxDBOzOAowljfj//23iN3yue4WTcQYts1gZvc805j2nn3wGBzv6+OOP1vr3GdZ IvYB/Z/s3J0/BlDaMK0EA66Kf04cytHH6gHlw5uaqkx8Fo+yh/czrv12x1I3MAPmMgnbx91oUTIm +VJiNUji0xhUw7CLs4f48rfr/rPaB7rvA3vzkhVKLU4PYYvyAUkANuW8PZAJb6oKtOxamOfFCqJV nDbAXmncxsoIIDd/ORV2TvglcHW1MHGDYhqpQXHzP9zAR5YxlYY+HjyxJmrD3mb8ph5/bKAA5RhX wKTeZexDK2aXFOw/JH59G7RroVcOPgEPgwvv/7wZOnRo9Cthv2cQERA2o9rDs8nCRElOq8ZThX6A ly3vwQtGMkduYNbgcec5mjQfS77TJrUVAZjUFPQmhjRfmlQy/cbMUzwkp9g60fDdrecHPkZkTXFd J5KGnVJENL5MPHX9YFV97vP3yl8Z25WFoWVOgXoFmE10a+ImQWINIBwpdt+z44Owu6Ivkub5hxr/ rFqqQ+o+LS2H0fvsLgBRwz2S4/N+ma+9MMvs3oNLYxxAtJUG2k6iw53HsUUFp3sTSCF71hOrkTfN xLdOR7/uXxp2i+S6yfdHFokNk30jy4dDwJywHbigokk4WbpTeKoiGHv/PvEruX79tSAzk33HwrAU gl0UvnFAcVQOxdGJmqaTDeiuau+PEbSjtLUoWcwm0/YVBUABJEjBPN3cW1JuPd0nh/iCU9ynySBq JAc1OlFxgMUKc4PKDpM5qY7NyjJg7bubhHt6r4spmsp4i0ZR/zKgT641o1uzeoIbnTS7D1u7WYAU qMPQFZEGh35qts+wxAiOfaBNPJz65rApl3TFdmsWX0GnXnZSSWY0JCCcOQ9pQuT1JfdENukTG2s9 S4NG3r14ZQJlLtbpf9PrhyIXboKWwqeYCCmJfC+/CcfIhBvq+xUQsSysL2OIVPkRQkFBDQ+1XFs5 OmvaUmcYsC9GrBoIAnS5eeZcYPx4RDM6o2uESRtaRdxbvP4J9hNLXe/yxpoLjOfSHmj+JbbJ3w7K DPXgXpKEoYFxWGqw5y7KBBliFF6t6C6Cs6xICrixvjyE/SiehHpZSkl+EmUIwSD9D1ezkwPJQjzb CCot/01jCPKQJkNHfq29pwdBgsnLsk9J2+LyozbP08pjN2ILCIHOKcddJYJEBwUqw/HzTIA8n1eZ eH1NzlkYrtA++KZG+d+k1k69HMmVvALT4hDtlVmcXfBbbXRj5NngSCH9/37DQjecNFYD4IhM5B7c QCfyoC3y7PN5n/Mef7BY+9et//5V/F8cJ/liYAszYniFewwb9guDuoWNJFpiVBArAADUo4f/NIA1 1xPJMT1b/LHzfFSiT40lQykNM3yJX0GaLzM+PRk0fNarxpgE2hTkhLvHsJK1kvByG0knsu1XNkzi 0D6JLySWv2WREdHZ+epWNrBjyP28z8cIT7ZRgac1Kyj9PpOiU9h6uaFt8liKjRGPFnHzwnR9vGc9 Skpk7NE+zOq4RNRTtlGRj47Ahd55Gclf7sMdSMD3/IEbLS+N4xiJn5nJTnNFSEO7hkzJAVxr3oah 8uSnmawlYKnyiBOlducP9A95bJmOmJ5Dz93HX9DT8sTOVndzs5lZ6yxvnvzKDypy7FyQm0GhD1/0 zGI8+nJPOMZlmesfXkkTlfvIJfRzC7ZLcjyboHpeq1sIqCtAe4yLawL+2hkJSHYeaGOF0YHZyHRR TO+vFUmgkM8WxD+wvmq/FvqIuR+TKiQlyt//583JsF1IdiiEcwC7p9rp+D6/HFQHN6VtVDedIKcG kws1kpkmMuBDxjaZ+Yp6zbmTRfDkgnnLiNa9u2T9/dokevp36rmQU0NSCHaM1Zr2L7lOe7eF6sLA ui66S4l0kXMC+dk4ycUsIkcMjWcTZ2DPw0gt7pwCOmrI/XR8XCKUE+sKW4GCMei9Qsa3IBwHOJzQ jgJ2EzvVzrKOy2oo/FA5D/SEHGLT+Kjwot40ORncaMhCoY4Clmj2CXjOi8DRsBacW3MKKupJJH5u vCvE74WsebOc302iANxZBAGHCp6JobPfH1h5GLIGNTElQsyPgkcv8i4n5bLnWh4p+nKiNWH8jOy4 2KgssCtkCGF6iq7UsOFcr4OZwe/i/A16IUl3EUthFulNVr/94co9AVde1JCAdLoaJqJaHA74Gy7/ 1B8+UpFx+QzXZrS6E15UeyKKblznSnhSfNWJvBrcACdiqvOjuqAxFt+puDBaXeWheALTBn4reRHe ElmtXj/SbvC4gtekXsIsLgfWhhPgHfQk8ET+ovjSUQcOszt692fKqe5fsTphOXwfF9o+cyj48BFB bQs4/hFP34aNtodVPvBkb6eCdf8zLndnWOKbYjoNzpC8Ladn9DToufBrkIF/iO/8PNuv9OwKhLPm kdtfkqJuyEfw1kSNDKlLyInTNLW2ePY0gMUjmLbJ4PPrg4X/Oayr51qvmIR9OSh15lnrfs2MoS5J UbAl2gKPxeUQn5sPZhaYF9FJ9OfaBu7tvNI3AoDlY2YIR2RwjV/PEP6zpEEP72OP7PMQPBHR2CL/ 7tura21xc41DVx1kahbztrDduUeIId336X16Dt4c7PTVXfm45PhzHMn49Qv0F8q8sFi/jo9A0rOS YJOdUB0Is/rpFuXVhqfnzIaJMON4OB4No+94jLMzygsJBJXEZ97DVVnEhDQdzmIivMyfyd+TywKu EWOhZYjbD8NQgcBEw6Y/iAyba+DPfjjxIVfArFeCeW9czumcM4VIVuAHNH8aY46Guq5ybuaP4Y2L Fts/toXFIDfgQ3JyjiXKuiXgQG3T1JXx9Dm32q4kj2b67Tuzx8xUocm3EaAI8UK88QEZN/qez6Ed 3nuy5WMm7JcOzFudt6Dfa7qHi1X4dZUFePQIuquLpGsinyLxitz4hIkduBWjh7RRqJ2K+6XDv6LX GP55uh2Qz/RZYdxdlXfCnX4uIytpRtunhfr1b1vnB4VMqxo/J8NWUBOjRHr52eE4LmAybuzB3NLe 3Ec3j+6dT92ar3AxgpnFf/XAH736L3y1hf5YM2jPMuI3wVKpMRMeJpliFfNEFH/e5d6y8mF9kNRC BXhpStYzOe/QG4QDJIzCd+x/cbVSoj0YItH1dIHbq1Vz76t5peSQzyw2C6FxD8QvMeMtMsgpX5BY /Ah75Ch+Mb1kz7gGxd9fPc063qgs6329fD2roo4KfOLduJLB58MOCdOoWHQYkHUm3fFDc+CsZDmy a3Rhana9RgpUQ0ZKNzvggSHIddw4uHScfYW7GOUa6eT6HRpce1a+4nBJQMUfz4FtmdnFqBjpSjRp wHYbuahXA3xL6dEoUTqOT8nOpqWB2vM/77gEp58MoHAolf2Sfj70ct6zKClxVITpgefYIE5wS11X viULTAqC+qkAAxBWAMvx7ESJ06TPkK0yOFKdqhLhC3/A/Qm3vU61ZwfFvnVog4g3/Oz2XsmTmLvC 1WewYLWlO7YNg+r7WOjcTLK4Gh+bcg+y7vAr3YatXfh4zbTYrGs9opnDQtR3xJYgq5iUdbi+ApTy 90MH8NZuh34chWjs4nHtpcbrACR+xJjBf8G2wdxwlhTwJ/5RoRcZc8pVsw1PQEyPZ4des9BeLSKp dVuyyc5Vh3XLxbE6xldEYlvMHgvyFOSb5W0fxPJbs+ZaDg7oSmJk2NGPIv3KbQfDs6Cej119dLPN OynQdxJbHnMMuZQOAKJ9wtJb9IG3hPPfMRscQ/mF3rGq0Q5ZXL+gRQEg+WVrCNE+UsSGDcbWqlD1 FxzIZn6VfrjDuFsX/Oy6ux3oV0NKp16C7Kee7pztE2/5hWxStriiG3xXpqtUy8k4L0NJubM/fIre LdKnJKT8cSAI//XBSYxhFjFcmkfmxWfFTX4z7Ii/AMuOqTpaYBOkDfha2e+Jpuca1rKeb0LvlbAZ fncyyAV27iHbAtF2xH1E7vDjhDLVxTVgRQ1gzMUnpOECoQ7/vIqRyQEuauLMu7J6gHg6uHFQkVkw zbCoJZfvGW0ydrAYvPIqrhpcwGA39b/d/lgtzb5LWnDDLdjvOyczuRxFmpUjAskE98RxLX+qdceI ntD8U8joPX+hdoo4OzFHR5RDvwIsxn7GxkNS2gzO1GW4PvkNvju7wn6otWXAcCzINriVB1LqT5CZ 3jo6nHpv+3TgXjSGinEOyQXujGhlhcFpVVqfRbuO9EKGcCtST3ZwOWUyAOPkVcREjSBSDPqMDPui QkLnwRRhsgyjTwGnWOIrrEBc2fgQ4BBnhyfNat7V/XL0nXPnwyLE56C/QwQCMMp6AuPqkOw4Ur2P erpGCJS29alCAcMr46auqioaSocgRWKBZYeKCik3PYl6Qnz9slcKMnrrjQV2Zg7P3tyYs7kEJ2Xq TbRcHam3FzbRs11AAsY/PP3O0GxPtvT7Wv2wrFZsPZ4syLZudRXezTrNuMgKfvc4OmZYQ1/WGdFx 62pEElt9Gp1mnAeoOfcC3r++D1VffICB1hNads3oQgU8IjIquA1k5qsBZMtQapCBcDOw0Tg4T/fQ vmjfhqA+JTt6Nh/8MlPsZMO6bAlquaFCkSljMgM4FW1n9Pz97SmYc4SZYQPdGMvHmW9SEFNl4RnN StZR/WaF2KqNqq57H/cLz+KQEc2vFjrEzj0BRbQvH8IeOIihInIhFRVEc0bDjv4mlA9B8aigqpVw VeK2UHO6+8OfIPpQRozHpK+PfA/IFjOV5n3BKcvaAz6gRw2jtUaAmNWankNYonaPu7gBoorgKQFs xCfbvBGoC12wN0waXiFT1LOxudnSJCAp9wO9fSs6ZrKHlAo/iQwpaQ54rqsY8TpU5qQGeUXwxKgS i8cTvWyD47XAFG9EvHGjuUqQu2a+40HiSUm+C5r1QfiarUDJlMdRw1jIDun5tfdePMZvzVBU2zD+ IyIAcn96N8EQhmL8FIKHbyZ9hMPAi+QfNTTgXnWr6yCU2WxDKKk2h29O97ez1bZvJ4AjGFh09lke EkJ4si69oAAx3xTr/oQcBUDR8puefN3bvBapCIAo97mQ7eS8pVYCVy9brB24lAb/Jux2SKk1FkJl LroMEKFOBfBc50ZkViesGcSb6KiOJH4RFtQbqOAOkctdiidzb9XCBeSpIcQdguTcMgsm6X66PJcJ 9dDjHEbf41IL6GM5wDvdIZ6GGH+iDOESFJ247Di4lA2FQOUl/3VuT6E6K2dJ5BjxOiE/oY/qPcDv ZiqdLnqnfHy4EJHtKWFmxROqBc4RQW8jzJMLftdcuMPvnF9hKSgY/z5TVLNPrGFXOhF8dR/UV52T TYvHEQLH0mZwvNFFDi9QHUovYDK09THErXqjLDNpEbW7AKEdS4W3E4hIWlZtdgH3K8LmIGfoAADQ IZtSL3J3mVIYYWDBk+7nzJD5m7vTOukHo6fMfadN9y0AqIj+MG5DrBCxiqLgiEo1fx9FLHzw6Jvz WhH4vzdLlZfxX0vDCD5mf5SY2/xXAfoRInrK41lXsRGRlZM1+qAu2SESGNT61YzotJCguZ26rvTP Ex/k26BUCtkK5s+E0ufc77/TovQxXWGdjUWvkVuA2ETARg9XnVjHdgc9jATT50MfegZuvOrTZxcJ nV1HSLGokMCEAEQaMiDjeIApWcq5vec/wwyodB1zl4EzhXIuf5Xn7MhOjyJJqXDjLJAeGQ7ZWD6W kYp+GIZAf/vYHXVof1jrxqK+pBrVITD82ead3r7SX1DPSJVQhZ3tHAxaYnipCa+w2JFbkN2Fm225 hacgTNqDCMbw1r1UGwWjHW1OGEb0rt2oMxcPQ9hyYMN8kIMsSsdDbQsMxW5BlRJiu6Lj4EtMhFcK CKHHHMS1PFXxzwQKqlsAR9KyvFnyJGGZztwHgqDznXXEOlsLICy9XVhhiXVoBNRwrCFSQXkLpTlE /51AzqdhKVIE6cz+DI/fzn2h/phA0se5TCg02XGTUEZXFbhi2Y6qNTYwX3Hq8CS7Dp6krGFAH9+R 9Sg11HNlxW78yKTZS46B7MhhyVRoDe9zIy9jnKsaCe/SMvFLtR+qDnRneaWCsLcPmC/qWbIRYiP7 5lpuAKe0uk4RFL1ytCwAGyQRNpIOtLqL8sfMtfU+9tjDmt2FDYDT8e8hke249Lz4Sq+I2W6I8+fo KdxNlOsUoA8pq+Na1p8G/dVzKabG96xvLyZA+qJCsT13C7fyke8Xh8miUlbk5H7HhGwq/iTgBOlx dSr04tOJYk1DVgj2A/9Ca/6WZ9WDF9nhSmIXaIgovef2neakL/0ZnurshDOcmhG97JlF+MtbvLTT 2QcLqOOHNtXihBonqcj5QTc/hCjsSXqZtD1jY5dq++Omb25N+b4pTXo6/Rqa05uHiJvaq5T4kv/0 rA24nbdftKDoUHK3YtviH1EdwLqMRiauBwqku2dwMi/OBNhdHprrtBiwsMiDNtHBbFfR6A5ebZca 81YFSR4vr3VUHzU3VtLjQhKMcRvU43w4yKRjB/pR5vDiLkHFAnaXcCiCg4aEtAuI0LUopXQWbXC8 //xcEORsPWqJKDuEuN0TAn72JtncUZa05nzQdQ4vm0kGN3YVjRn3e7iVdEHQ3f4jf+sL3W3unScL CcFUgcLso1uLJ6kglJt4F/k1f2KzZvHziJ7gFw0qo0EzD5th5guvMf/RfCZ4Yhfbe0MFoMkEwpKU Ohm2dFYnsvDbHYcwykTlPMDTRr4JBSsGPXoLVMyUXbLoreBcZmALoS/PY0S0VCjuM9vyo4kqEIxM Gl779sUO6LokXbjZZskIqMUgn35fOOxneX7CGfMrKG9MuQI0LE1+a3AeN8tmZBKKezPb/eOLaPoC LDwqJDjRHydCBOyMT3STAcht7QeOIbC2wKr4qkXoSL+z/wUVfcHW9iCax2wVPZxgTyVI8QIX9YPr FMy6rt3yN1ChTVv7q0lNRVMoLY/25OqximDJKlWKX7s1P4FtPhrR8KX+SaGY+D8yEuFJ5SYWae8D fqi6SY3IwUoGNzkshamhK1qNeG5viq7+JkJWuxi2K0mAIRk7Vo6qwuzZQMrSmBceOcuUKqMDnptl n9kRfEbICmbMc9JBxVm73E2yiOzy3STejYst877I5AxmToCBrDzYArl1X1jmY5k44BDNKkq3F8x0 AtGweQAn9MbiWZbQDZ1EwCX4cKr/rqL6Jy8SGIvMUgIgO7YAG569sJmO9M8SbSm3B99zWM7agRxb Z/YUixqswV/N0vyJfNVAbpmi7A0wD/4PQCm0VcpYlGHDGlxfXi/TXzBgHuAvFx3GZZ1oR8u+PiqY PoBKELGMWqMuQ2/+Ta0ukAUOpOiXrZ4w1RFxytqQfS8Dwu3ZnIBmrSZbwbMjZ4irEFsVCnJ4jsou AuyTJVNurqLCj1h9pz0MHVADxqqXB4724VAc4jutoUuehN/kww3W9h4G31O93BNef9FwpeRC3zGc qRVJv/ps0PveFoJuAdqJVLjRSTIAUSOv09TNeFaLlE9uQh5HBDjsouKNYk1p0s7ZQKPHjmntYRR7 1RDIgo5kqZ116vMZruiLc/h81Lf8AdZoanRc2EVrQkS+QFSo2nnaXsTs3BfAK4zRtNOu3EuQbj2M i+cjW9rdlZamzA9Rn4Z+wj4SbGydlRgQBPLR+YvCxEaov7SjHsG+w30TBgwpvIC9a2ZkublKe781 GtOMMmk+5NLjeMK66fZGyjqw9R/4L5PlzSydujCfjBnQB/n5WHEsY2Y/9KPyUbgqlt6a18yIfSZw 7HSW3bLYJpZ3uOhUGLlF1NQX0eIvHyoI/Wxf2fRxOzA/PsvX2uFe/zQjPH4KYZaYDRLnP7zgMGmm 5jFDcMwjDCipTTYdMO1wix7mVTeonbF0ZLYnCc21begWazhU+aQyu//cipL3RlWz3L1Pmo8H9E3+ ckqWdjUhMUmRrdcW+9/pa9f9uRq+CNcoq0iXU6RkzcebJVeqj1n6IqZt9CMpRA4XT+6CF7Z7ENT2 F7cumzO6m17RZIAfqsuBfj22bYsR5si4jfxYSONje0MUCnzwMpgBOjnsaDeeHUzZMKX7kdVdJzor UbcVprSHYkkEiP+ZF445sKoGt3W91ipfdoXIhKEHkrIeyhNWHuKhnCpZ2qXmEnNwhFDd9LzIVPCy oagn6JR9avvNjkO6E5rQ3H+Bd+c9gzug53OK2MiNMhnjXa5GMAPQsvPu3eTN23DxXaDUco0K9mAq OlwMYxr6TRzv4c29IasGFjFb1SjiR1A/HmjQBCWjdC5cxjaCUeW4+AO51fU32iYw4+fs56UStadG OTTg60ZAZQFNNrGJBLhQ3zHOwNAWRiIAeeTxyvPZ9dyZZYoq64TV2r5mwfhExJzIqi1L+Fp0LFx+ mFYxx6rfx1M75QFNnkC5xCA/oAGQFisyv4pbh/Fm5ci5vsz1AFGsK7TCzZ0CpuAAiIxHAgyFhLqa JnoZtZWEwWZdVaH1fK2o83x3TZ9qRJOIRplaSg6nsK8rOxAIyhbWOxnCPmJf9N9EuefR+c9ZJ7HY 5v/GL13HKPbq3hIvMFYd5DfnmLsYKBCBEMYsEKTtLXRHlGIvOlcm4hmTyzPWFwoDkQhw/p9BdS4u J3CKvc/dtIbeniojo/0jgoxfa/YJcQARXMpEgnJDitrUoCfUUN9rW/tzc5i0z597UNiYqnSQo6M+ VkS4OP3w12V85YvOncEZL4yl33YRdVMYDLiQFG1xsPCJIIa7Qpi2/UbRpp41K0aqLIPlGDkWpwn6 4rM+qKm/g+3PEf6pt1fIf3KKcZHdt811FDQNPccdI+rRtaJLYUiMrK8NUL1KClKYOZo7Utmnq+9N rF5pfgq2nelvmd6+KATc+iJw/ICT2TMD0ZrbthlqvTW0PxzuhglLO2Uc6bgwPmu5kashkmuMZvGh mO9eRuE4o0gFZznqn0uGmo3RkXdINjNZXz4KFPf6r0OXNs+iB9w0xJq2cUDUZfhBQmOVfDKwrKBl Zy3wNak8RSTMKzc1v0+9g6nfa1M7NZZ7f7DSx5DkJUWPwu2B/6ho/Cd9by3S3owAYQCKXD8isCMu OtJZxoWktD3qJOtX16/sIt1WhcCF+V6fWQeOjKHtC9v2VpH831at58bWWD7CtZp67IaWz5f1ys0g sw2JZ7ZzRXu8tyKww44KHG3+ZpzOwnNJfE+buwJnfHplCEgHQF6iE+s6kgcJFfv5Bugbg+vHU7OG bvtiVEUI2wBg0tCYVwTL39eEP7f4Jh+eSMsNTuVqASwAh+3oE8ENo4NoOUYauRqNydu/J7YqUkVg i/r48twYkXpJlzH7kZXq9L0J/0V4TFuYPwTUC2qL3ZQxvJDHZ2eW9DOVE71lzkxy02ryDwsZ3u61 0K2gP/OE6zBVPStp9RRx2vHZLFL9drIqXGmfWIKUldi7v38SU0a4BoMauGdUB8x0NoxuaX371tTb r7fysAFHstkJoBQREHxvPvcM6arr89ym4emLvlBlFunh43YmeSlMvZO+iVZ1r1XBZ8bJkDC/hqgx 69xe64kH0b+Fk5Um2/EyFBL3LtFuApg79PAKy5NxV6EdBzuule2E23m12h8BQKscgjQtdmdlxBDg fQn/WvL8pI8PFCs1YPzd6lOKkDfqhZ8PFWGAwpgybFYvs2poXjIfWZMqe3BnZ6u/OE8vU63Nhd5B drVJJIYHxciSLIXbEWXhquUbKKcE2iDlSjkaOLienf1xOPwAPuhVNykI1f+GPkZ73OBuI6Xd2J8Q kp98BX2XjJG6nXBkR+qynCqNJsqui01tbqaGinhJgFCj6QTwF7/myOVinz5jOFkt72BLGMRN9w/N gDyen/K5Hx8F418rv5AH6xGYruWjQSH1031Lh4g2k5moomSUvnaE+B9Ll4ARGU/oWm2VnSCYzPda cC0qZONQB9fiELEYr80Bn+lM0Nk5xrPKb847tACDWa7QTrxZvwG3tjNqRWsJsXE4CX84NsyFMtwK 8m8i9b226dmFogdYB85oz6lDwAPd55MWsPAS/JmLwLm7O0a0eOzY7qwwU3s3P3Gb0LtXuvjt6Cku EbT/0HIzfMeucINg9m2BOBGc33tT+t/aVtqJA2nOl8oNzTGjOfoVaqxzOufLaIY2aha3qMjjlsep z9ZdygtF5JHZGM9T8bXpEDc9OljphqcPcXZUc1Af6K0REDbin6IqitTviOE9T6sbl18ZSyGnRjeQ DGzYC5X52w8VG0VUN51ZsqWSP0v9wKNtRnI/CJepVw8ILE4DsF6BLYpaB29XzwxGTZzka35nJqyd +K/sAfMgOUVEwvXqjIyChgVLYo4qsMo21BSXVPOj8GztzdshtVyIjNLNYLQHVcbDw+H2KLat0lKL gjZJiAbFW6+IeDYmK+/u4fSOGLbvV1r6GVpd5yOXo3cMI8tbl9AFaLtYBzIRKhApTtvC77/ED7na J66/56XZQhqLHIefD1wDCswkcvUWUYsvgY1juCEtMFdN5lyZ0qMgo6Peaj8xGxFRZC9hEaXjBjUD EXkXsGvooZkS16fCuwGlKYLjd28+ByadyBf2BUKqB5N69X3UjNsDOlJFqb8gdnOdFrWVS2fIZk87 7vDb96P8HKEf/jqBwe/UeAL+7ID11wwxpdvF3pwj5oBHUuQdQxziHV7lr/7DmSVwI2QCZ+n1c0Qm M/vgzOcFxtKirET+YRfLgE7338jP7Z/3f5KC8i7KoxbwtRxV8Q/djeuWZKY49fnqSTvkmPOJ6H2+ 0irWdqRU7s1w1IlEPcW3HOiRpy4gTgixAk0xvnrHh2z++WvSzMHp6gFdJJIfONavrHUx3VifLkQl GYwp8icRgFZoIdF3vroRzZug7p7hqpYiLKHnAD2ukQltNj1sZc2r5OwQ/QXxibFsFuZXcIBew+4J pMQu2IZ4T0eT1iCUucUtMezskHlVpR/Xj8HA2qyzU7oiyxNjVd6ETT8HvAbNZJOsq91xPM/OzLRg HrzoRSowixE++fQo2bjulVJOGJqRf/5k9xayygKjLlZVQIUung9+tzprk2ewgLWUwCxmhVBjuEm0 PuaDOpt9/CQQvqCtqy3tt/Km4zg7fYg0k/t+1mSSCjNYHXHhbLpH7w+ijvu1sMtsJ+an77At4Ys5 QEj/0EXoilHu/mkRavOqP8ZXJyKCmEN03izP0WEC/NEXCsAcP55601wB2vkIAYnYvhZ6ytbPvQmj b7wIRiw535iX8mCo5Zw5TSs2XAFq6PecOImzBdJKv4Ti5T2ssQNfaelMFFk8vT84HxagkE4ZOh/V 0sxKSai4AwlamRPEkAH2JKDkkhFgOqfTsrvqY/mdeyTjWBA1Zulz5Ktq9uSdLbu25ZnKkBFgDWyX rfxXAgECuJ4L1k2M85hTOYHDffvJXaD2xNF4iEaKYFMNteX6uqCNHejdLf4pHuzB7FcorCrL17TK PlC4IX/TAd/spRfXPC/tz29oLeY91o9jm9NJ2S44GsRgS5ktNXoDZ6S2Bp4MW93UR8iAdia0E43/ wtDqrhZGM03ows1DzX2DuJjdPwvgzmF+fmSO3KO8YXaT1zbGG/94wuEYY2BH8KVtkcaczXxIpKur tNU3znhSaacNA6Kky6r7u79VJdCFPyW9RMaRl7DaSsXbqPnUJiP1MCfNWHHQy0CcofWYIp7r6k1V UTVjwnS9E7/zHfGRNGj7mJPH8Wky/gw/zjeUOVwmT2W7B3GlqKe1Is6gmxJ1Cw1PintJoOXs6/Mo 2SJ5HtV1g8QAFy4ErNKmBRepVQmUPRONl3aKnz+jHWrFktjziEFP9nsUaqaknGhxR5/H9rA8hzS7 8fRDkMLVqOl9xvJ4Hhw7UThF610VpERi3mptwrUnAcIFMVTXvMMRe9wuS/XHhyMOs/Z7fpfxEcfa 5Cu/Iit9JNTZKhFl5LCiUttdrGFSpUGzVXqCU7yn5Xw2wOwemV8vXbu14bB4T2Ekj5L1rmj3lxpF jqrCni2BuKuz2MYCnUlz17/eLZlYadVs9KG3g/Uz48fcx2batRz7dSZV6QKh6ix3eFtjld8I1WqA a7FNp0bfA0Yz50EM74RXePJiAtuyhag0A55yxaCYJR/JSoGjGfD3f5csFcOePwUyYpTQVFVxCI8x gAIV0jf+PX6lR4iSAAh/7EDH5f+mbeHmE3E0zndSEb00Fd+0UzD48VW5eKk1dJ2VEtpIT1bjWbEW esxTldkdwgwLBJi5RWqpzA3w6FhTdoSHXmM6t5ov3hvX5F+T59kt653dDIEOJ9ix4BXRIlOlF39R UgTpVsYNlsz1rDAI4UauTewSw3/HyBtu+ov0DOrLFf7LYuZ+mmBHfLvv4eoVH4XT+zncA4vFprhI TnD5CnVg3+yeJzVSHoHnyuD8GwVKdheyXPv6hVcSmC4L3DAesgDsRmwMCdvMfwwtPO48h5v1qL7s 6tKlYwNmU2xQndywW83EPDrpPjTXmGX5WXPSVq8UHRwGk1rLR8fRenBZ8Ai4tkQmgE7lNZDJB09c bq6Hw/WFsIQ7E3Uw/oRJmOCTL3VhdeVc6oCjlSp0jQIFCfYYR8G89ZkwafCD4Kb2W2DDPegvDMCj 88ZL3HlA5ac+B5q7PrsadljFWyPDqQZtVw3A9gKVvaAVDvR6khcgj9sRV8IEd+Wi4R8+dGniOTSX w25oWAd9GdfcG4+eprAFJ2e3/SvGRZM5EQlRNZXNzNotgOLoFKAsSNg7HqGJRwABzIsIggGOrjaU mVfZ3auSSw2WAwmqoUV9+kLAEP3fHOHqGeJc3aOAINdsOU0jbE+b3P1f4aEVGDeJGllQ3ePmzXLd FDLqVMe4yvW6DjUYCAxEgxuVI8yQiJS4Y42a9I63QYbYuV6M5uNaC48+GS50hFbmsOk2UXCLl2iF fbIjSSffq+DhsdnfcWMRb0oV5Zmx9M/ViW+vwgRKbHIkGKjjoIoH0YCh2qosPD3S+ncNb0PpcNWA O4GCDxPD0CJNaI/eLLrsoHxXX3IjZ1FghwxStDvalxrXU13JoOqWo4SHjRC/3U8FlzltYsXIjB5U D8GTK8+XTtmBcx8kT3nRANzQ6aY+bLK4IPTgVOQf+SC4jUWbyRFTFi0ic88aec2cExPv7FCdKmp/ 6shx5MLnUKe28zgLuA6BT3OrUOt7DP5WrEWtJflzg7rI+TXuzk8uVCu/acNvBhCsK/pWHH1tWkxp QAyGL1glS8OOPakFk4yTwK50tgrMzIcnkOoFJoeCS7JjX83lQF1FeVZo2V4HdPzNgUDwn++nOuhv ASjPmskCy8P/msFxttp2QreUs19THlnP4FVl6KwlRkl8GgMOnSWb7POHutOuYtMqSY6IIevjFpke 7cjz3GkhDJVRt+OfyGb/Vuklc1HKmMTWDVVVcZzm1PAxzUHrucl4RJoZaxq0F0xSUTJ9c4P2DpCI jDvlnfBngodba2L6Z36CfiHG774aKaL0BVi001kmLfWjNcVKREQBPNH8OXawmWhIjEht4Bowbp// lCkomco2Qx4G3Z7gOAuo7BRZnlLKoSfEJLii3C+/s93FOr5xqaYqX/0EEPyCdDodvVY1QKU1f3qy qbeimfNhMvC7AO5KxFTjpOohSJKAjn0JzW/xkhma4dKtB4/bP22GX7GAifags/c/5FAIipV0SIrS +0J5it2hOTvvyxKb3SAJtlCe7kdL1eMOAIpxiRXu0zxtp48DiAS46DJwAGqUOCc7D6MjU75C9Exm +jfSRbVA3u7LHl2CUIlsbJA0Gn3JaFs3e8HNyBfFbkB4iy7rh/GoiMoTve6IZ2U8Gkabe/qblYGP t+6DCD7Jz+6Nrv7HTnefRyZZwj3Ts8lzV2g5LvuM6UGTwOUEH0S/CAKzqFXomLax8hPssGCHYPBF GMhi1wxMBsLd/rESbH2wB7uIqjVOEauaLP0zP1n8r9A//7pxYHFkgkO99PzG6OloQLjd2PWpCYbz qfCNMeRgMoi0+7rYc6ZtMEK0vdpOhCCifWKCwSMvoHM2lFexeS3gD/+4MSodq5jkM9QkCyfiglwL JB2A8J14jq+IQAXtPeGBYTv//COvUcuwm+OprTh5qpW6PXWBRIGDSnlNUe6U0hR5nbybQT/Hs+sZ QnEIbWKdSVsGBUf0d5GgPzKclCACOxENpPetuNEGKp+uoEHqtB809bNuUkQyryDcNFeX/Rz1HJbP XcJRVtm/zmlIUZ37OsH3d0NBfbPvCyshIDHsl+1FOGDIiTueVEJlh+jQ534Ub+XiRWKFX6RebA0a Zy8+U4pJEub3XJovSPA9mKz9ChBAZG9VCA6U5dWwN/QKxBcG3krfD42s9vkPrJaEv3CjVTqNdwIw FEnkUaJt5um9trudpK66R50rEgKFgAumbj9E2ox+QHqw9rqsTtWDEGGnvSKcgeQ2/aoDQCR5GlVo Yq/TJBTCN9w/F2s0foKQPw/L5mQYRUNGzBZVrpakOWlubkmgNoGup4mpwXf+ixhmARjK7sNY0MO0 gwOsTOBsyCA/4R35U+kjuQMwOljWTVZJyBlHWyWVWLv6noELtr1UY63hhD6j6fAo6lNQXR6DVr81 VKc8e5ZASgdAAb6YtZwsFruIV1Si9BWZgRJlkyy6JzoriGC/EQC6RJ2f9o/BjsMK3CS1+/svsADM ilcwngraVZ6nsOK6nxcB9Ongasbdh5hzC3JBVW2F4W+SmZm4mVMcsl6y0k3ngSBrpyn1+YoY/8vC PFawfp/NE9qp6era8CnFNTIiE2HOzcuo+aNlIHPTrA02J7AHqCuPs47K27WTnG2up/ZdCIX/Sc62 vIMwJ5gVQJO+VOE7NJeFOSngDv2IFSZhxXCW5s+eTOV9tgcLYYHNUOFKLjSDTLRuOWl9NbcXeHKm MvUlMXeFJZd+a0zCZgRYAawU2UbWj0tGVm/dt1C6zbB3QfFLUyAzpVRmzV3o9voA7Yzx1bMIBymy J1dP3Nh1yV2FeD+33OpPR2pm4cLG16RN+m/mzPICry5I7sEvDNcsMNjzeQ6IvkX/UJuQTSIFMfNt weKRvSAYmOhnWQMQ8iM43B//JzF3No9a0zXMkx3NBLXB/0mBM9Y+udeTwrTlW7tOhVS/N/6FLiXe ivRxAMmkjOuZwO6bKdgw0oopI2/CSzXXVt4rOFctHvHgCAgCe+f/nvO9jrirSzLQI6pbqtOS/SlW NbRmbxGmIrdhgsBIsTopL1aFLzLPiUxINPLEZQd/Q14sbnkFbywfC+Kcw+tbLNQCrLYrZUKERXQX /gF9ySCsiNN9Bw/dKod5NIYPGwNveomZJuyCIHg9uKwW+zrZ2SSQ6jhtyBE2paqLRazwwQtG5Opx 2v82i9ln0jgeskYZJHIkvcCkR/rqNUZ1guv4DGO9eEpm0JsZ+yTPXHbEzgTGPnDZnmFLdCxoWTEA +4x8rd7rAiwJ0AbTbUxZmoezV1qhmhXzuaZfe1KYPDQUxGS8tbCH8jvjVxP3GLF0ZYdcJpIm9R7H NU3AqeUNIpBAGM6Xgy/nogfKs4S3f05hea9xA2QhBvxjDvMKDXQ8V5T75DTfZNpetJrzXIWr735c 4y8v+e4rZU6z3K/ks9V9kikyZzThktSEKrqfSEAShK8njRvFLOv9G9MCPCT9atr88AZ23uQti/+O OgNaEVpWMdgzzjxM5m/wB53j/rH5Q8fG5AmMYn3LMraAOa/kwNx4f2a70wH3hJPqkecKT5i3vPNW B8JmV4UZ/k7daskK/mBPPoY0GRYht6FWREurfSY5abRh0L1dKYVOGdm6OU963dJK+t+ZWiK9nmMw 05YaS7rrkUbbnqLnAt0SltJmQe6HjBDT/H/bkm/y8ea7Ba9/lX8NS5R8U16sD3g02UHCkdjXf018 guxHLzQ2l0e69AHkisJyiTL5OlzKth1G+gzdtuYKY+fFPXeoLd8DGEYXPK5x9904C0NA0O5jUT+z 4V7/w4moMhfBC7omLZzkOIw0IqFHqumVkUK7zlgIhaLtYkxsKyKdsWBiOKomMACZrWFE5xjLDSuH uXIqi69Zo+NQ3cYINRDYBDWOjeQbVZ29y9w6GnZTdsXjXKOwbx0uEywG5gqZvBlPqAc3oqkFbfvW J7hKrJbeePIuUKGhTHHVb7nO9FhMCGh/DzwTbG/9gMn33/hItQaFQB7aqi576QbHto/wHGEP3HVV MlLXrxi2gITPKXf9M6L9HYHzJvpKJR4KAO+G3Eu+F3lq52ArHO2qYZNSbh6FKckPA0JgUKxWeZbo Q/3j+B83m2tyDGj10EIM51IfFjRV7ovhNwkJ/DgG7sO3DLB62y3NC9ZFsz7KcO9ZfNNiiJ8zqWTE zxx3vP6fcuUQt/dVdlr+kS69qdTtNhObgYTvCPj1Nlt9LcE7QcrwFrUIv2cmUCxaZLRy9uYBzFxG mCZqFIAtvxtauAkOBL5KzoxXO8fiv9UcZbxuDZ4E/nrKh9fdt+J3Xag/DAC0GJRiQRAZU0TcJDvL DveriN1/E9Ta7GArIYyeIurY7AmyQ6GyY4gEXWcOr0+EKhFtSYQTF6KczGDDZrB2VAVisIMnj+N4 zs7YMQglFcEErZJLngkjksspsRSxBSKgu9UJ8zBu0kvUE6zSG1t6OtdA9MKsRxWxyG8g+uMAcP0r DYLUNpt864p95mGJL9agkD5YBMaP9uPVavqQzbXm+UROI9VQTNk+KOve/VN9WXCw5bEKLLnZzN+O hj5AF/TI4sgT1EHhefQaN4rL8f7NZieuC9Nh+U/NSL+f5kwRPXI2+TdPWcMDyyH3+xvIdhAyV1lD LEsjF6fsTQ4qAdleweF9vxuOHb2NcAQqXhTYm5YZ2V+d3Zp1RLLdKV4yxPMBkRhx6mTufLnWE9H2 VMdjL3ELC4wD8ZVvOY8n0dULQvLToIF7cUOy/EqyIrlYUMAl8BLIOjS1Trfamrx4oALQVOFIpXA4 /BqDZISfuYuZMlBUkFjIs8lGzTS2AVX77oIJ4+SVoyURRCzuZco06GKAjeo2Jk/UtAQmYqLtmMuB n+cIcVXfiKxYkC/726cGUJ91hdP/rC5MwGALDdnnFq0bK+lMEZ2q/SVCO6h/z1Q1i1h97QKet3KV Zq7uKprpB+lxlYhN0JhkrQCP9qBsEaVYeSylaXzYQZ3aMtt9Ci3RAy3NxxIR0gLANM+cU/pgHFp/ UQa93H6ik+hTRO6AtBIk90kjTyjC/v+x03t49BtQrga4mMPCbpSunyIpqYtGchQ1Kd9XHNeOrJMe lLm4Y8IfIZXhpzLceWm6AGkpxrnILPJcdDfLqqr/nn65MJ8QUdKqO54qgNU7sEiQV0NKDSVj6/gc 8vZG/uD79bJYP0mE6S83Fy8HO09gquO2evXZ8d5NZd84kP/GM4JnV2Ua1+95GZ0IIitWUbI4TwOZ b/7HqdcMMZo2X854RM8MlX7cQ8Hyowcvqq6YhNUwvpDdTUYi2/rOQqnWaHdqNZ3WN8691DjY+IeW qrDfnY1SPjLnvvbseTQnb+38r+Zg2rFB7QbfS0B1/Nf5YHcvty5tATlDHFcX9aFjeJHSa3g9ABMN wzzYF4p9EabsDlR5I+HJ7UK6ItIrzNu3q0hEPKmWeo6G4KHmHmx+uRqV+siVJnXXL1uzP18qMOKc lXRczQklXcuUxpr5nYv1f73MFPZe8gW1/eJfO3BDZN33C0CeQSteDxUHXUJCozo0DZCtbEfAPR55 icfMA2mEMAw2mdtbXy6Qss7rm2xF1DKffUvtbkiChoLneJ0jxEt40GIl3MPTiHvhbjBwIoWkBwWN tV7g6wYDUzpqmig3jORbEKwqMbFX0A21yqoXzhdOQQiP08COwbRg3eLaaBgqEFVnaaT5DbM3Ybkg 08NWBHqnLZUTQEXG5V5/yNq3XwRGsi+oATL8Sr8skc7sz95NSJ5hp06ZiEfhPAE8rdsrzUCYJZUn UZmoK2/uQhkHrqI6M0dJnZzC4eYKePJNoMWbcuIMmGSJqVB9W18DM5aoYohsUWM4rq8sSUHu8scJ 8ENNYsIBPGVWyk/KsCnttcq68Pn29lx3S6U7m6ZjYij09Qzr2jakKDfk8E4nghbhLD8ibiNa2hUe yNacndOVGV4/EkZUXieuCr7afiNHg/5KqJAuySzCRsOTFHS4b7w/h6YxowYOxZE+mCzEHUIJVE64 yb7eF79UV6W5Be9UlrCZnO8FbmAJFy6XcOkJuyY6rX8ujUOzN8kLYte8gahjnqVoEQE5yqX7Rhex cXMYBMveXjRqprFoiovszIEM8YYITW68KDyzJ72A0gZuAaIi5dKBaOh+H7H/3Q8PAWzJCc1zrYh3 WeyYVOUSIKkrGVWHe4CknsyZDuX5oWXON8YxPpu4dxf3DOu9//kCUISYpw6RdCgG8AjRdOtpbIuA OaszBMUV51zF3COQYGMYVO89q28icNv9DdTjG9FZROyIhXcjn9qG5Y13TxPDGKCcPGwtKv4gGiLJ bz5GahU8D/tHAx+/JAtkUYeg9Z5tf7j1YSFZiXKF/0ziAafAIxv+kX8r+5VPok3tGnDO8OO+gjVp kaMuEtB+TP5B1t8NyIlUXrE9NDvmvajFQMQpbvrtZqCQZ9MxsT8/EyDmniekDmWLk02diSzX09/s MQFCA9MxD8wEIj8hF8qVpDXTGAwIrk2sDC1WdrjiMYgtPkikzY0pROwM2RcNbHwslac6rDMgYp+y kZr37hPLFFMwcPC2IJ04ne5x0WhNXIGl6i14pZiRUAVYiMcAP0UKVZzBmw7LKpNuRWI2rNDNT3dd 1XuiOOqXRJVb0k0R6LzgUhIFPEkEo+XoBAUZDLRxmx0d/eFhxsbVMjpNrmh4Ge3Mx+ZhnB1zpVA8 BqJwsfT/byda83uhQF7PQArSmHe/CGfi5EAcYss2T7Ka0o3308Z0TfmiTSOJIsuK1cvfr0u1N0yE RszSX3s+5FQlKWYN4N5Fl+zWwi1ZFyeQdLabH7aH8NtJ+Rf2OKAM0ABC8jWJXqREHEVWo1Rrcap8 FzNciqX/T9q0QA3xKQh8u3sjha5QdTcMDXx1aXpEDfQEiqxFT4tzzB1utVnQxZa5pHv9a3nQEl95 1+wZ9u5j3Kz/Wq//Ej6KUkZ3pV+LptFTR13smkd6xvIsNaF2dNgNfZ+s39iKmScnl1d+8gbH+QDl 8xhz+HcfcjwfmDgEjGvl/GJ1TSEejy5qT+7NuRBTxZvQfy+M4hLkWhrinzh1FoTJIG1uRZlqGa5X cN7ncx0zt5a7jLR4F2bjb7MKyJE889mcoSIC+aHiAlEpjLjrUgQkA6zYQ5UMuWiL6A70PPhIu0Iq 72fVwNsHiRETncqDS85AYSjQ9WKOUp01qTxQaQyil+z7VRtGxDZW6Tp4AzjUYL4wGC5DPbcWdtwD cIEFPKJ6XDkDutqC4TOQnC6nJal8w0Dh8413Hy1szOggpbaU68J/ts26J3dGfTH7YGsRnWy598yV E5KJOklbXbVn2waqxZHq3FIJcF2RRbDvzLyunqVfGVI48eIg2SjBTzV8lBuFCv7pViB63itAWCs2 VP/KrQc6V11rDrhLJ2nJGUGYzVBnh60iJq3uMNMhsSZKB6oDLjyXtPRVY9kiS/KTou9QMMUlw3Tk VXZdp2QT/ocJizbDRE7KqbJtIXsbYx9kHb+ONkvlmohdcgl5tgjPU0qDAa0eZejFfe4yBDTGGj/a DZdMzl4Avm/ARNYi1skTMDMJzjgR20Vtio+Z/foweCcqMVfy2QZoYP2/kSGFtmDQel6iCexD1y7p xNAS9bejeiVKTFMAlEYPkL0uF4KOdh1i5IxImVuBTz5fHSfieWXglgeys+VK6tb1YV/MnZd8Nrs/ Rs47ZUfQ6Q/tFhsc5ZRsbJKUOX9p/0HxW6ZJY8VKZscjPANpxChP30b4u891AEuCDCu4vjNu8swu q9COe8iAdEzl3zngFFHOpDRvFBd1/QeBjU3FdA6YZStWQWN7GwwtshIo2Qs1NZU/VK6e5JLBFpY4 KbGSqD0DKvwoDq1/c4Bozn49/+U5eljMeBvF8+UsYrn6pboTwcvvDJTCCO11iSlWDuudzYPUuGFp MYyRm283uRG97QizmZcEiLXGyqObcJfceE1YfpWkCZZkoZGjwvhFXRBd0RBbjFiQzHm9L9AIG4rm ko/lzg8BRWnt9wf+c0ltU7/SyMCxpUhiTBymwNndSCfQ4eJr07OrL+Ay8Q+7UaCx+2EnXXGk7Ls2 xrPV+b0x5woI5m2/9QVEQB1QShUwVarCDIqXS4gBhR6X8SeiHRLKnx253swtYKypIFMCWyfMFBb0 RvBkGLZKXGYhukIrEe7bd6l+VIUBRPpNx0oGl+EPz8D4VmjXIzbO0vrVnHAztKm5SvkiAxa1aFDv 9bCX/6Gxq9Ln8JI9G8DHnJFKtWmW2521GI7vW3lB92OGIXpyr+Os4u7j8WZcPPHS12FrTGAZmZAY +wFgScCXBSakKTKFWD7SHqdt7yE2cIqBoUEnyzWeECw7ozipD8HHXHWo5soN+KcgoGoSxQajFGu1 Fzat5qiMyZe05FmosyATHhUsKJztVtcx5YnnTknSr9fnfLHBJLM5RCMjng62Gh+p+b2IEAI3CJ0Q uNQNgIkuJ0Hu2ICa5KJH4IJ09GRp6kMe361gDtw88PzR6ukZDqmZSsuJG1FNClt+EIX8/QbtigbQ mrwFEu5Rzz0nLx9kC/ufaaTPQ8/RSJsaX3bFj0OhFzIVxIWBtQYSPuM/ty/DFele8fX7ajeww3NZ 3fGeFFSBegTfHWGHD+z9DI3UWPcCB3WYrBWC5T13dkxY2UoYSPzF8S9Rs7Yfrwsl/52f4MA44RO7 Tuw7uD+kh8Z6cr+SZfdPGSIJ9zZch9uUp6fpJ3oU9s2tTUzGKQz0rrjSUHfeQjyemNmbnSBnPvI9 MaLlbffnlDk5heJYLMAbfLiZZR7vtdFgdAaFMtw//NKFdZVQrl9glbTwvsZ6li4Z5xromkYetNyx 1tkyuJNvQTaSqyfLbC9940mVAqkKdx3AlnG2yQm/DdWQBTChK4fB4zotJRoyfqCcWskVTE1lbHrg HXNdYVChxjzgiOXhWQ0/PtMBRHPvMvNWz7FobFGu+9BfbVqqg/5ORKr5IcNbhzztA99sVxXzDziV VSH4pI3Kg3zODZCMaWDY1cfqVpVSuf9kKnuFnLsWOaZn4Ludd662D8nL+rqZDRuoRWw4n3qwOfMK 2S4jTdlhuMmZPajp8KYhT+QiyQ+7Ha//r4jUZ3h9bfSLhVVshW4yKzLLLhp3DBuGiEYwaOXrrZVK Sd72H7oGV3DUSh1WNkll+Tz7FEBcoPNE38zXO3emZgKLOUA0cpi6O9HPbNChiAmnTQ36kLVW1+zy titWkSLjpLxuOCunxCiLBgGiXCdHuCPkB4DfT/T0IXLwdFMrn9nWK8aZDQ910Gmrh7kUnw5Sr0jk Cn41R5M8olLSUDmkbXVXSVpOMQn3XW/Fu/HKU0oFNIs1lCccibKMVt7IVD+tUrggRm8CGBew3lgV NQqM5FlUlx2VBkpaBNZyxWmb/Qshf+5Szh/0wdYzsbLK0LXm3LH/WaJOp9RndpGjkLpIK3WC8LPt jc7U3G12CMvdZ0Yp6yF1X2nMO4O5ISVBRLNEbwfY4tatsFO4V/IOWbwmUj1EceJdaodrV3586+ee tOwfqdX42y/amULMdNFTb6uHqSAAGpplg6K5UHfeNYvdRpUHwyhz3Unrfb0lV5KqRMf6zvDfGbQl q3aPkFNG0t9yiEwJBk2mn3nQrghnlcPM2hcfc5rB85B8/hleMZW6tZFJ+FOMLuJbhz6MXzUvv9rc YbGUkn2KPKW5AOGk7m8Lp6FqNrfQ4yqexq+ywkqqBFKLnJM3V4dvn58GKK1PjF6fePS0sYt+gQgh f8MEbIQnS18TjqF5CFXCm6a2lGvGTL1nrrM8Un2XJeMq6AiV42N8ozHT7uBFd9OpE7+/dVg4NgpE eliLOKOelE87uYPqLAjdch4p2d3koV+fnBwJ8jVY7tihBHTOoGUDE1jk5Lz2kXTrLz1h7hcXzDk0 2ZA+Tjxqfmt2Z8effoIJ3nzIxhtCiWnyACgX710AcZP7DTAvsMmgLah+Ac2yeaolQVvhRrkhLLZL jHfGhPQYIK6c7sFwoYXVVLUBq1xUitg9objkeWVynGNZmyMh50z2T4MeapIS8jcMFdOxxXylgHob 01AiBWzh99DcMaZpo3sMmQZ0oZ1xnJ0HhtDlc8Q5yIXfmKUtrl74szX2wAC6fcu6MVdgkrm76ZI0 S50UKgJ84grGYpJc/abAWt25o8uZtWdWW0DZj3rcpc/rouPWGHMC9+mPqAUu219GjptpypwMtKlF K8U92G0usl7dgIs+NfJjh1kEqF2/0/VZVTkJh5bnXqfylqwqgJ90dGXopQxJmu7GBrNgRAX5bVCF ST9zHiwvf7fhIuTVtuzxNSo0wAy1Ybfn2KrXt8wQ6EbhD2YccnoO20X62xi7cr8LQvk7bO8hwPrk u9M7xlGoEs8mBmCdV3EI9CMENl2hNuUxp24mp4mtPcMCnV546O1FZQ46OuocNzQ8klBqS+OVOvo7 QkTzIhN+0hz20HjsPFaHVtKYitOjKbMoar/oqE0pHXPzp552kV+PrxN4cmoj5CtMYssa8OuFyEVd GtMbnZfktvNDzvYknTjsAy0Cu+HFa/sGhQTQmTEboAdrTbmdaWQJUkUbEi5ZVuev+Jvp2WfJCBV7 JBrpH3/OLWocUqdQR9DmmCHL5cV3bsxSu0wJgm079NOPmOWF7brmtTwvYnZlVrvxKeI9WK2yXqcn CVjdyo+esmuYqybFkdgPkAcvsaBQN+j3o7q2nTERBmVGSA1V8Gpqqgf4Yfp8vD/VmXZR4B3hts7z OfDMOhp79hTGe+5y0elExY8iPy7l0UXGx9elkW72JQVVIp9Dcitu1HtT3tP+9RuEgwhbDQeW5GwJ hK0/e97vndrJOXfn9o8nW+0aUSTRE/5/m41SMX/t0RWJL3qXWni2Cc6D1aRcNlFlhk1Hw1Tj+nub adRY3MdgPn6BeiTKddBK3he1NuKuZkByxDIezT4RmIxGPRPQWrLAhzgFpWpv2VV0iLOtsYEHQilT 2wuBqLwn2lurNO8hrJTWJ9pB+2/K1yQouDE0h4Ik8nCM7eHHLORL73mpxqmSsYH/hdkQW6Nvs2io R9oFC978BQZ9kgQZfhsdBsQ5tyfNbnx0lHHILgEOXa/EbBWPJ36c3gCCAXbYezrruImx9gmN6gm6 u+diSIYoRQ5HeqkMX/MUAMTUvRc+lcWVqGdbM+t/eZRvw9ro7e2AdMF4PHFzMCOCFVsEAemadVk1 4Sl8u+bKoXcGrIqkzp7iXftI0hNmz9fshmTZeSeZxy7AxYcR2zS0ltnLn5MM40g5bzextI7szYQx bsCLE22WBQA7DQ6kkeGs+pP5RxI+/1WbGh/UmmnPxmirU2CMnbUtfsHViVr9VHrLAyPg/tsZDAxt blgv9YGPb+8mW6B9azOZoQ5+2zNFwlqjwiPpWW3EzPqrUVHXIf41iRRy+xGTvUogaYYaQxFknjGs i8S2cL3RBXbqa+Wv6ucrj/EoV6FlcgpWonwUnLYKnBy0jqP5xFb6B9eHXvCe8YY7y/728Q/8amTc 7D+b62wmCCB7jXAiIbmtWnWPZzs0c+XjYsyCZ4VsxGZyDHO3E7nLvx8KEyOQx9LerrTukwfrkG/f cWOpKv6KxYUyMoH1vecl/DfxQNvxU+4MQxXsAoYQMW1DR00gFXhhkiaDgPocLY9ipdGS+MrX2cCk FrM5Jo9hmExQGmLNBDa5FMW+rKVfiUMoYcKZ3hOciCyXlOxW89gmif0oFB0DVrAoPGlmBDSHoaXb xDUG4ysvYot4nv6nE4bEaFEMsrtMgKEp/T6FLgN4mVOpnkAcHy5EIj8/42DIIIGhk/8vo/I2vN42 +268U3hHMW8qyIQCvcTHAHnSLZxbRGuiUtJ+UEx3AJhU+ifejohcoc0w+Ul/bxEUbzww7JUSlFZH h4yYYfWWLgrKS91EdscTJREjpx0BxvbZExMufTyD8Sc/8qDA6pUiC3ydX6PW+MdwpXzOmq1SxbK2 VooD50foh96PwVRN1V9Bu6x9aLqI+f4Dn+ylvAc9+uPYR7dPlN9z/nhu36YQeg+L6hMk9H7dXMZ+ kyVf9JzRLBmm6rHZwFOkGmQQ6hF8G+b1M4ChWzHSwYc89CttiFOjo+lzqu/NLqSadA+xhh9+zj9q vv1LCCon5QORzJ6+EIc3TMeXvCwEvjsjjetp8E/CLaKIF37j/rxs9639Rf7eW8W8cwYeWQ8Ohy8z BtT2UMRKz0YxVArQ78QExhmNc8WdHmXmM0JNWezGS/sob7xU3PMZ6WlfJKLg7VGC41o07eHQ9bwN 3xEqwB16AG2AWMISinfUSgp4HJjsgs+3UHFefzUSsbp1sczqYEeW1NQ9fZCviE85z2Ejr+DBqabU G5Nv6zFhBM1sJlX57pVyJsUQv4mOpQpP1CaDlD9KN78/qp0iUDsbo5ItKtf1BbJzzN1gYXKLXCUs 6SNX0Y3PO2jIj+B6SaVVyn4wIwWU26m+yLebAl5O1sakWe0khxT7/S+HrIUPfgFxUatS6/Wo59bq zWrrB9DSZsjLc/iS2n7UARcKDkS+aisQ7yRe4q7JBBQaZ/9iPYh9uw+F4r6QMJD/bjnbcZ6V3rFA btejv+dVp/5HwliZAu2b6gG7FF/5/RkezfUiQFBNZKu45ytLnavj4GvMnLfspmYhJxle/4ycOQXs y1DaWJlRAYV2zPdvX/asqexIjz/t/bHyjl6BX7nIhxWq4roGNyRqMj6yxFwo7RPhBm50caKB2i/s DwNCI2R6cIzdO/+/qrx+GLux1QxQgKDj9713aLS3v7XAFklZ+zk3JBy2D3dICUmDLb+4ZqcBxTFL UHZB+OJBPCRBbz0rvkNejEL7ldJCcxuxQv7EoKyo9811bNIRUVV6nbqgYEAcPs5q/4xAZ3haXgI9 FqtNVleCnQmjDH2OV+CPcL5Mgaj4JqugH2H+UvsubXYf1MOvhKmeecZ/s3YyjQQtN939xx3Qlhhm LIDSfGNAAtqkCmkjA9HvRJH8xiHtgnakCQPX1FDCdtI8wO4DX3ppcffsQg4XCJqNh4EJZ34AlWPb VhhTZgaL0KV5eqcm9Y4kY8uwbfqzPyq/2N+QrXUpCjeve8a83hQgQRzMRhelNO3mrLr/zUE/NqVE PlOA85jyrwOphGLxIic3iVl9QqJH910xyev7RBfxsUtYITH2z/fUP6ZrhWU7Qsno2Cu6oDj1bSdE ZsUsPFT6+/YxqbeZ0gSyyK9x8wsRKGPXxGZvKyqf8IVMJL2JExB9n2x6I6ALV3Wc4mUBTfmbSrN7 TzLfzmZOBtTPlZ/t57v6VTuU4JkkNUMgORCcsup0EOVbUk+h8Mhobp5+KYBiQ9lsdGCIA9oxT9eF r3k3a2Bb2/2NgV5xM2Kxh7l0YY75xRgLM+Uc9KHWI5ECdGyOmKKpqWkgc0wLiP3Pg0Kb+w9z28ro drRfk+VaSlQ5jc2Pd6cpu5qlSfB/XVHt9LsOyGYLHKdB9jnrjLnRU9975RdfPTMjC05KNXG7p29A NsDFy5nmNj9KtuLLcvPa80XSjigcigW7iMFgQ86/psIaqfK4vk+SolBZCXcXgUdS7pnacsbYA9EX IdUOI+uXhIL4pK0mxLPzl1DAw7D5Gfr14Ryo0s27VevsKcSgAcbayCba/0KIPRX2wQ3T5mfla39a XhCLw1rOHtRCr+y/Ei8tBEzNTC3az4whDu1myjYoHZ9UG2MCL8y2FTlZ+5iYfuYjcRPMzXBeBkoR vOXypozvkUGN28aa+0fr9d4P6LPj2UY8cF0A4L9hjrN68C8WNWX6Ju8MJPthpBsgJrZiOnZyDxDE gc8QOLRc33DfJIcOkvcNwV2TxtEtyyC5fPVpmHfs595pgtKKR8GZawEPVi4sBJ3yzTYsXYJqIyal 9AZBYXSY1YvADQLPiukthc5haQcyzvpfzXnq1baPvm6Zx7X2JAZovA/UCrafqxYg5csAcnoknWQL cYMbMxRPYDBiW+oUyrdnmHDF3XFFIjZKZnFaRaJlHhyBMeZqmXxnnazk3HO7XUY8ABbtOUTcTYMU pcpJ2Qh/C1dPHysKh2lVfzoQnSCm3iQXk03VU9uLqeiFayqGJa2uH/BwFEkJLgl/h23HFA1959CH JH8/YRgJ7alcgjKaPVIpo+kipdVijP4QbUs70iOYv4SXdBjP8uZFVJM47HghWurqmHbRlF+h2id5 7bGcZUxt5sLXDSkD8iZgu52//waWE1H2SdjTjPviqFaCt5SPoKftiTlJSw4gH/rr2hVaWLtH53DE kFjWv1HdlmbMdW7Jn8BqNkE9TboIqjcx4nxcweeRo3+Op6rCvXn/Twruv4fCtqJEolvwuE305jEn 2C8EdwYzKxtvr5ccev3QedKxbniPkhnZELBu4Sc8KXwU/Xq2dJG10OgSRgJI3gFg0ZZBF2DKaSFx yaEG6zZ/PZJzfWAibUXhGP2oh9ORAn2s7pRxHKBECEVFCOtnrNPbLpY7iMubIoj0yJMQifGVOiou fZT7SxOFwJpp6Ewoh5Wf/s8jcYHOwTbjBMLeH87XCGuUNefWDAVA7AYjtZpbdy6rj5O0abt6CN1b bfADpTSqeLdZhbAyLUACUXBBzn7SB1JHOHi5bxQc1ySDl3irkwbJ0A1XXw+X4Xr7tLXt3LCJA33q 6ig+mTBsQrqnhmJuzFLuRuPG+hChjMH8ZLwlIicEdhuNANHn41azjQFWC/BtY7yAZOvIW3H+sIJ3 k0gM21fp/1nF8bPYwAB18DuJ68On8Nw3aIOkMfR+ofsAs2xWjfrR1pB+YJ3KTq6SmWayuDUb8irG qpb3NXNpD+jKzlW6TiJwwt249+2fjqUoVH36UfhjZRFOdxIzZlgxRwiF9YUux623K1m/ShR26SKl UA8ly8ckpoBG4JwBrkCD9dQmY8bBy57FvXTfB/mA/jh1HK8xFFhWlnsEOTYxkefrbbAflUUaGXUd TOLxgO94d/AbD7sgudxBSfwduhbkKPqJVWtdzT3z0OEjmao4fHjZIwrizQidxlbWpV8uODEidLrV i3JkGi8s44/7glNMUtXatEn5VkNlRWI5ZC/PbIi1j4AEwkCnfE0YBGp5DpKT3kneAS78I03wzWgo TWp4X/IQzfVdzLBYZo7yi0T3Z0UsCEz+rfpVQvzJs01QzwjDTHN1Yp0Ow6fmiWimzXGdDLW8H0Uz ehbTTur9xfnBEto/ewwqax5v0ZPEtOTZ1oLbpmXmYqMx+r8Tw3F90W3RIlkIPs/a8wrRcfPkrGrA 5+ml2NLY7LukN6NTf/HzJtC8nUF3UzhMprj+BvMvQ+Sr7oTxx3J/y+nNRy90aUwcvp8IIJYNxJqK tGnMAJglTVv2sRubLZ3iFaCB4Qmd+bZq2WQpkEN6bwdN+KVxwQdCaIyQVjXXcIGBR/2Mu3Z8eHSc Al0KaDj3WTmC5ViVNVKk5XgS7MTR8nwk96ielFHf14IetqYVMw8UmEqQ9fj5KI3nCtZn5VWiuHCy U86fh3ywspQ5lvyUcy6HcuWiR0by9NB8hpZDbDN55cQPeb2W+LD+AgKOKePrXf6RmhulAyNakUDc jqSWaeSH0o2JqZLU06ox3WQD8dolPiynN67AuHTwUaSV+w46oo5vb/BeWiSWwzVxk2UPg0qvH7zg miI5j3xcU5t4PT9nz5upF8KDUccOsdJyN6HHsFNODms6WdRANIx9EMlVGBFGqXsZXJ09w78xtQ7O akHgHjuPH9FIS28V/as+Pt7r+nYVz8+uU5aDjDJ3fpRlLb3yhAZOH6o4r1zwGP5QlasbvshSH/ja hq9xGmsiZy1ris26txAB5FKQvZvA/iV11FfudDmM9G2z6NKEVxypZ4HbZg58LLu9VU6N/+sEeCO3 WqtdtWVaLDtrVH1q4gdLN+waZla3MlquqF7lNvgS2eJ5PrbyYCLtXPfVNpo2h/R0zAu6G9r8/Has 7pgxiu8dvlI7kbXIwqsS/n01XGyEfoTv6CRhtGwoL35lH59n9J5G4FTa0HM1hreywA1SCJwAdfi6 9ZvZpxOKD8Bc/U2432RSRdvJ1GStlzqRyiSzYJ6wXcNitxCs5jJYzoTjElOuTY9Sm6mYmepnI3O0 9lM+ZSvqh0EkjRAW6gf8M80VHa8xvlGA0DfH7NC3FmAlV/iRUGSR0PMJ84IF04aTihM7fT9tCVtW LUn+niQqzda8RMIwcuWrwW8uzuzBZnPDjgVjyQhCotMFQLNIEC8lsJzmAbAYpI2cezDRhZPJByN5 xFbms4jDmdXVo7QEztiinVJrVgJaYunLAmTKP1t4C2L5yzzmdQ7dphBlCUdtKf0tlK+uQgKfOgYA HCX+U71INrTZXoBCvGOT3bQL2lgDjH5xXPcn4bKRVA2z4/SKp6ZCXgDcvZQB+FiRZHIFLzmgi12G qCGXoYcsK4/NWVrvOWGuLwIXpwkjiLj17BE/SZXK6YO9P1CKBYN8u/Bnb3+1FNoyiLDKK/CKQl/8 wlr8jUIcH9YoIO79CSREkhqZvVmVk3QvGdkA27ox1Nq+U3A0i1u/FJuJlyhaiPLeHWZSEquTs/rI bMdoLaJ2hpIyMPEi/cuYKmYgVNwR7miS0J7TPqlhZnK0j017ZeWJ2z8FSq9zPPW2VjT9Lq8xMW2M as4mPgf0aI+d1Hc5/8l2hjMNNIN89uTCuzFyOFKpfUrMIBDT+Hwzs30ooJ7+/ypQwVgzlNMFJSoK gSXpBqagRhaQxpPU71zLMAu12zBNEfa9hZSyeNBk2TJsI+iU8fD1CKVU1+4j1l4YXiKyGXikRTqd URqZUYuDMakUnb5w+4QnKyX5TP+GX1bLedFamvwAcICWw3OASwq7rxXBD0a77RSmV64zRK/Fqc44 0C+Tpu1ouvC0Abag7ijMxtmUUQYbjJkmw1gg75445yVgDLn1mOY8AocKYXGP6yQQF5K+V6aHYoy3 kcfCDHoM3rhHZUs6nUSzx6Ijr/1yBydcXqu2N5o7k7llEO6e1AZ6V0hMnYMGRV4OuCP89ZxH7Fob 9WQu+rPTDhs9Zu67PCOI6FpTh1WIqc9n0xIheHsSIj2qjDS16WEDObDgrPIfjqrkIgiFIg8ds1X9 fcth2ElvjslZBQNn16Sjr2yVR8M0nq2uaDigjDflJXYUXpsE2jiEJemHPb21fj8P5CfImlRJjroy 3OYY75VzsxeJ8dStRgqZdXNflaY9UAGk2OAK9OpmXhfajPfwkShBKBT2naFaBobooVVH9Nafk9RW g3ouT8VCNMxcHcSfwXNz20IMz5vXZ+sDVN/fwZreKnm45PG5P8+azLJNJIjhFnAqTHIRgE5p4ZsJ Sno65Eb1jOrqdLj6VGwM4/hOc7XhwG7XGBdOx0WKIcgpGbiRBfdZMaVN+fl6KN3PusX1mcC/RR8i B5KQUHaDwQ5gPdY2e0uyLoU2w5CyLjvks2LpH2vdGGuhk5XgR3WRyaSefLSa++ljxWxuxCz1yceG aKqGlh4/bB8Suwk+n97Z2TP/Rp/I3DcxYdkv89DUeE+69Gwl1AxbAZDHWkS41hJw6fhBXoj2KMor pEdvZy4ixZYSld63pTqmmuKIv7sLzod6uleirBPuX/xF4nEpRrV6Q3fYdTDWnBeJszj97HafbGXs xl9gRvTtjJt09H73eBqeQD5UoCg2bEYaGcAXfGM0y3PwugubmwXMxFUKPkfU35axdR+Li+UQCa70 E8N2AFrDDV92tRFO5Y6ere8wgc0bEEY2VQ1xnzWomQ03wZ+0VG8DQIh3TawKLFfD+41j5MXiIj5z GKY9O23uCKu7k6G4fZiabvG3GcSRFJSu9sdFSKZ27cVr/fj/YrYcJhhKkA2iX5cLaQCDkcDxjxpH iwkwkGLX+d9Cqx77ATPkidDSSXxkbZmJgd27Yz8/oIHhrVOooMiDcxvTzUpbIM9fRcws4NUreYP+ WihPb70ukL0eN9GrYUvvKi51iju/4zqKkgvMoIAWLhzwbhdNQlea/O+M/aRgvW7kkJpRSi3z+lNa mCq62ftVZPwh3CD0xMelwmplOmc6TlrbR6QlQQcMr2K8usaoRlvOG7/SsQGlR1WeA0FpXMuw4Qmw dazvThv0n9JOQaJ71G5FknZ21ix+YRtjujhPZejmF40QBuA+uGLS/2TFXVgTXEtQ1cWUCqfI2xWr caXnY8VncgmbM/loZhB1EbZwAajGuVLW1zXvCb6T2fcA0vXhZl/YnfMDRMpYxBlj/s+fXb3IWAQg 3So8TNdYWK95r9BNuuG2DNji/ZGPK2mCgFIh/hPcfHJOIuyCnXjEDI/ym7Y+7YJ2dK50IwUvS9m7 lOcLwRP8dMQN4XLldPWTCA4gkR0ZtRBEj30YozKFJuvJ9pNQcGYex8b+rTcNP8Mu/XxYPRIwKJo2 WXDHiX5pFgqjmdtwg9xblQu8HuOC/1ooVqles0c15uAuNd0V0XcoRg7Mz1SNZ6YB1QjE01tyyiQn ka9GRzs5EwopVgRBSTYlU5G8HpkmatuETCTAUPhhOlEPlCavisDQkDu9j3oIvYuvKwax8e0ThIrk N1z8WkkI5CM3r6hDux6wPpH5A23ONP8RXMiQT4NG3l1yOLsCCHC6oi9NZNjUvv3LHuLBoLPlMbBD k3b58WXzFhIiDtbMIdyTdGG9rmCAOWNpVV/hkraEngtZeGjHKV7uXJyih9B8GOrKFobu65sqd9dc 5upqNDxxJRXxynTG4xQjBzL9OGemhnj8VufEn5hoSvBGMBOw5GHQCFGb2xww2JnmRV+2Jz6u0Din mpMxLRznzrVzvKvAlUPXrthikrf6g8/yHGiXVllDynZ7udjSU1/gdD6wklzfY6Pi+c3HCXjnWbbh eraupDwrFT9syWGiEGrDz5PHpR4WiebJhYS76v9omIuNOe3Z7ukC3csun++ERx7MaVq4we3ayGLg GsVSUzMU/uajDCkR013SNuy71nLtqxz1vkUriu4u5G5VgxcSZJ5v9ps9leGQtXql1vETcyCyXYyQ Pan4g3zNC2CrxizzgxgY31JLf6Y2VNV7QxUDK3+m/DbiXJBy2haaIzxOn4DtezaKBfTyiZ8uCR4d BvTIPY2hJJqCMWur/t4gIy3pd24hIKpTrccU8zauCe3nCafIbbCUJpI97Qwhl4NvQaEIqgzZ12aI nY3yYHWzoKG6ueT9ck9EdblnAupaEbxw8a/19IaX7W7aSbiNvRT0SIjeiaFvWafTxuP8L5bSnI3V 6IavolfbKWZS6/8G57PYhilKxYK/3kWG+e3eFn10F163ZgUsDSHHxkrY4vNin+5ChCy+aW1+EkP6 krDQhqwXjzzDdO19oVpaO7HSOa3EPm2OSaZcjGG0txVM6KZ3uGxSWBSHcByPgBKIM8CpXhJwQle2 Qaxuavpv4QqOKXjGlux3moiIA/1T9rFt98nvfd2oiHAh2ASczDs6+CztO5L6McSwG6/6fOpIIRO/ JeRS1bpLSdYb8+XjR6uXpmfrkPNzdTuNxMbR26Wu0K63Tvrnl1s1oHRSq6DLRAuIlAyc6Sv2f/Nu 8DG+00CruHUiZjKGtukxEFnCsB4qZUy4NhpuEFqFczRRmwn21Ci4q9X66SkC7bWds6h6XFDk13tf eObuqMNeDitxUw9EsG7Fw33pzW0xLcp8q7t4ppDtTm+jxRirAc2VTfZA3d999zICHp12Bwdw9XtD 8G30mavXGsUu+nSbJ27WU4HxFUGBf3MLLkFRM0v8rnq/OnNOPkweaRVeNgSluDqLhvtyBoeg24H4 V9rClDVG1saBBB27xvRJAUJ2E+z/n8hwRXylVOMp76D6JAQkaPd1x5jFyv486MF4iZlZxkTpvsXe +3LoA4t/5VRpRC3+6dUmEk7Esg9W76PzWUcn7QG68FBU5uZB7P92Zux4Zo0BMtDH21yjUnd80fSg oxsY7CE8na2Ww7AIuGoatW6//i7fm+yNjcH06dWhjACWk95/8++gQNyRp88k+lhb6hvFYOUF+Cp/ sdJN9JRVZfgVsqvAQzjUN1+QJUb0f1E5LGGVl2sbVnGd1zEhR1Oo16LCdGu3dcP8rJvmeOP0F0Lk K9a0vY+FKsTqTTtJSoTq0AjP6D/iBtV2xM9+s28foi47CBxT+AwMGMZ3TjRZ+ThZbJsZ9OHtYEr+ 8M4Ku5OQCTSPCTV3tLtvqjRawvBI2mvYkmt9Q04KlO22DDw/QCvGcxatpdyNE9r/Yi1AptW8HyFn u50Pvinl+SycFudBqhgxro3BsNCRO63hEUgCr0ApGc7yUIVqI4zUj+55plNM5x6buvI/2T7GsAC8 wA0UFExX9bWLPEikRZnrYcj/kZqWHfWwWHBerVedQlR1NXPIlCQecEmVkDNDX90O6+dVN5G1hVC1 7Nr1YewnQlhjbec5xq9gQIbKaRjWFWUJBqmlL3vikPzV2U+e7vZ3ThnhZKrutiT/yRbe425Dkn7Z n34RFdafqXyzO/apn5khI8vIsK6V7Ri5u9daK2pntJ+FVhL0yGwFPeLfKqloXaolIzXe4sUlNaoT Qe3Kwyht4/TY+bnjXl//ldWYsIid6rLY0CNJK7Sq8PKJy93qlNGaSy/Weqdgx5eAopT/xrAKCw1j i5otD7ZkBPvubQOt+l+DO2HJQDY0nHYiC48+Iy7pNW+gyAiKQI2QlCzXrFzYAJLsnm9KuojzSWBw uAZ3qUC+fmSn2ryUATl+D9t88g0tV2aPBzURwX0gY1qZh2geybjEwvgCU9HwQrSUaGPFfvw8mTNP hEvJshYpf9+KETruMee9+Q+2JyQ4Fogc+xr0S3J7korF5jN0BSAnVO3svrYcAI04yS4rC0jGflf5 ab1nYmVLtPSlNEq6TKALLLI1NxcTxObKjTma2Ob6IB+9Z5mTFmWmCnb3V2fcq+4YNlzXVYzGmI+Y L9iGirPMym4eVzvlNRfCl7fuvxJqrWG/wk75oPc6ldNNCI49spxw6bkqdm4aLB/ophd5bkrX3ykY YISl/LEtstwI9dFrCM3+Q6JQSfb8ynCS5C+0e//9KM7KgC7h6EOffVRfh0tFvgmZyimT+VH13FWk nQ8abs5owXyHASPfsG63WVHvMlfpy6YBRTXiwLpqJLg3tFv1QLnA4t1uxs3cS18NdhwTYnjlD0Mv YjLpOGDI9EevBkGkwHjt8s/xg/0LpvNN0CHExp6WpACEn+TYbyKluEVk3QrQ/WnyZkAM8VswErGG JXiGU0bDgmSUgH2zZHTBHO/54L4AIKAuq5IklKDLmQqwGF0X2cUr9AORcGTw1nKhIi/c6lYUXPiD TxC2Mxk/NWoXIsiaFYBhIjiclaozsNWPtG1F6FQMTO1UwUBb+JjbS5KGkvHoxpq7jAT3ZlpMwR6Y U7Uho17pmdC6WQzToWAhB3qTo039quJ11rsQjPf3VFY0VGYXZ/fRul/Do7t/9yf/ssBL8kYhh76N DXtI6+ECnFeIJ92Aj3Me7Gw6dFNfpXFmU9LmnRHdTpqA80hsRaUQzhPMfGzRbtQ3JOKzrcjPKBNC 0mklAHIPOzNOBevVTKWTvty8o4OG5P1KmZqGIe9C3IpseHnFNR+l6X2GPOoGiFxJOF0tXCX5kRiO Hq2rjyoQs+ywK5CefSbsIV5bzP+/PnshIKbKk3+dUa1xOgEO9++BJTSuWvA4qvZSN4IaQaCrlvrK HJU13VYW8Exj7IrlTNHYeNcZvDkBY+uER/EQjT0aq010RjqyjDmc7eHFJ6addJjl1SMXmKpZBIuP wrL1LlWJmB+A+qJ/qDK0Jx9uQ2uUAxrvkNRJ27rLm0U9eWN+u+kSCqbh+I8xrlmB+cZ4y2SWf07I W8MbbTWC+3QxAeHYCb8Hd3fwPdB+4NJ/0sitAPVjbdWjOp7nzcAfYdGeEJ+5T51cYVVDewX+mHHM VvaVO/cE8+Kr1kZuLJmwsRKpThGfrrrFCwK4CuPh80T23wBWXxR256VA4MDpiNRMKSkVOAyQMCu7 8lFxKi7/PnZH0OQ0XxM6tlao58fgx8BB1l5gfYkZQuS08OhZWYnWYOY/t6HQXmZkeJbf8XioszIT f+6FFfLIJryoxiBM5EJIm90cXZDIuBQUISfopW0ea4gfjXzEIP9NNZFRAWAGX8HFzj5LhC1g9RRs Epp3fTVFYBcIGmbVuksUsqiHOkfRjA/ov7B8ntUCtpGtxjc3upLsedcQHeKBn7+9a5ZRU8LEB5yZ MrCOLExP4r2qar+N9UFcfnBKkn1fnlE2xYUUlSxi2Kg31Ar4M8WRdokAYtoqos1tjemXa3ZXJ+Zy DZIvQ75uXOyYEnb2HSIcb7ihwFG/K6fVG9em4igjk46ugbduuhRidirEBHDNxYvT3mcEH/Vr+JDu w00i3Z9iYO7LFXZ7Qtl+Mgu2LzPWf6I+wn1jFIBvA5eJn9TV8n9feHoZXpKe0ZcGXAxaOAUKvmsO BwQsiQ9lLA0lCA+FuOXi1JLCFkPUZyWwwdaSI7smmbGoQwxX/YdFfMOZFwM6FvXeHpq0Jb7NanBN 346Uly4p7w9HLYaj4iQZf+WysPcBU1o+dkUTZsXsqFknMwdY+oO8VlPBnB/8v1Qrs8buPmaGSCT1 kyBwewVXa9bOz5lmOsAiC209vsnlXwF0zu2nLA07KbBdoUfpMLZ/iJ+30ZPjbUVSTdoS6wCQaY4l cowBgfkOWWh0HOtjDHLsZSSXrrJsMtfJWXzHDxBIuM6NLUqM9JuLfkeLKySx4FuXwF7TcmF3NGCM fnp2liXU/OKCoz9NfHAy+tXIR79l32peCa/7PJWui6T2ZMlsinC8UwXxzv8q2rCMOJl98tjywRKE 95o2Ibb9eSKULJ3kz0Q6DJIl6vrDjK9LtwGNj/aQD4wCAl2oAYjIM1uR5PT9vm2hcvwGiXT1Wr/T +8N1E5Ufz1NZt0/k8alBRYx+7XW4OrNG4ro9+W2gHAAs/iKf9a3GKl7NcNCYTQgM5UIU0SoBt2E2 Taz19rCdYrjpAYSccW/rSHMPwA02fUd4Oewn4LnJYQ4+sZj7VSmvSQIVF5FA5TxDStxMbQ7D0Npw NNCZ6H56QFLm8KeGeeMSAurKozrTfgljMdUP+3Ci7FNzzSI7fVjKwVKugQnBPTwiHWf77OXlBgFF 8mv6k7iFcIG4yUBvlcVC29258HR8NcAEmVUaYkQYBhck/yiwGWhcZaDdw71v7vTTBE4ekhkE5wnq YcmkBkwpHTpp/HOgQGQm8oFqq3w7qf5mIXoRK/OAFycApFwtx9pZqWtbDX2CR6LHvhLWE1TJfqqB x6x6yWIahzN5hp48rhds1iHZ+n7+SrK/Gf1TbiWxjJqZ7yvuzzZdn/Dsrih2NMa+yV5tLJGY2xOn /Po/GdFHFfaClAIWXpOwNHo3ManCZl+EYJHoe0hYXMB8GoPQ7NmSAr4iZl17YoDyaWkLxPp1m0WE YMQoqvh37ljWrUrMposavEkJtIe5K/1Ql+F+DlhFnnWLCDToVlWzB1IuDE0pKJkd9wAYo2FSlTvo UeEG82GKz2OM/iy+p8PmXlw9uvab3x+ArdOJue+O1dtSvZDYpOsCw9vYyZJ9FwMn85Yx9gSOOHzX unEOxhpKW7UAWGvPTyaJl9M5FjRNcHBkI4Azw2CIuEC0lRtUf2o2yD0fsScHKzW4Rx4g5PAKX6Gp EhJegB+b3GfxcSVsZtm+GO3H4iioeik/Edr1W+cYNuXtLHL32T6wY55kdb0y5qYnA6Slvy5XMZJ/ g7bWcV9oWCj3VumKOcfNrWvWg3CPHjeA4SwuRnhJH+dhQg5Xq894+2Abu+0nGWTKf3pO+UR5TFET t+WTvXF/qBAAA9pRkPbRzSaXjS+xnIkuwH/EqsWDtkr/jrlxHdFZvSPMGskRANEPOawb1bqsj6d4 8IaU7zvqv2POLjzrWDFN0GSOAK2NurYVClK7IXBjftsDilsaeodlqnCLsgKEUu6P6QZMURvjbvda YXNSanC48/eAP96zYDwhWehY5p+m0utBVarQ9ME1S+W0mDxgvckVBNg5MZCz2fPdZiEjk3bNTIKI OYt8nJpTIDwGje7rwyQF3gkGSK8guPJzzl7LsJns8/yM5RqQa8rVYyQ9SBgUEQfzujNm0i53EaNU WWCoKc/WgcfxVD4eU6hO8l6S0oTh7r6YZNObykboZwYOaxJPVKIb0g6uQCHx3e3TWmwIBMFb1qNE BZKo9U9AhECz2C1qx2ZG1QniSRn2+uvY1KLToilmI5EuMYhEPWNgYSSqlfwbBNxBMki9RnWkLVCC nqMitTa1rhWvqkmN1vQuYavwF9hFoGrdEqyYZgoqgnye4tSbO2+CrieONVD+ePXkTUhue6DBAR07 Vd87iX9+iRkeje7nKQm68ekp5jpoiw2tHxZ1tWPCKTfOHRYO3Bd1LQsj4UJWKljK/L0Bhnd3YQnH PUOUKT8Kg1p+orIuGtycm8nv3GWeFqh+OmSmLdN+/+QyrLKG055B8UdNHVS4acaBq644mSe0Nxe+ ekfPzyglWlS3RQk5O1P8KjaSrIpGKzobuLzxc88tz82n9CAXQB0Hw478nwD5UXOl/ZsTSnL7Grah xPncsfPGyXiqIQ4ifFUVfEaoGTxWOeJcK0TbkTDMNHZqNfku6DfDMjsyb29Oy/+IxU7fBq7GMG7z /eOmLaY9axKZ/BXhZMRUydsw+prdRaxQ9SHVpgIoBuEhzX64A+oDlFoZs/at4x/2eOMA0Q3RmxIc B0GKDCe5G37ZvaNdopK2nFg11LonKB8n0CogP3a6ElW+AclW3c+3emw/NSs4KZj+Rq8QRY/fOc1t FDcLVMteL9mc9J9l3So/swCYvnIeTWcbLh9IBBq7X1YrhmHiu0dSjqaVTnrrPdodcBgbDUmjWQVe MYbko2c9d66YvHdp5nzQK6COPa996DZbc94x3gaWuzx8MTAewpj67adUzNyKEJeTFbNSK+uGveuH WUASPDJdC1EqRNL9hJpgvCBiKxHIulOiGSIg3QAL3yug/c8noRkudsqRPDtGLAIqE4Ga3/ylyXb6 qel68+GaQHn1Qqy7VzVNAOapRQ7SnuYGPwYdp/Ns2vhnd1MPgJJgZCtrppRWn1qCIQo5rG3Pazoe FinhQHMxaUUwdIHM3FPyHDudOALhLYm3QuvZRS5y/EGr1GdYVAy1GsBJ2+RtISPD3YBQPXbHSjNp uD5OSmbjdBM3gLI4FQaTIPKza++1dxH/e5qTeieibqMPsT+0DRwHcv7sURIZ22BHLfoc0D5+e9VF MedI4aEURX/7OhENXi/hGlWfsqEYgt4CiYsJtSuZKLuL60vyeC4SVovPGLyIJKpb6UJGFdV9Tk2J gdGFUnvamd3+daQe13Po/dZFjAEVEDeJJeErgcjpbqXExbY9DmODkmLh4Ct4BfmRpwEINvMGUo/m cCxrNbyZso1P2ODn1VS6+sCC9DCybjcZcdELQCVFp2sAaJAAugMObuqeP9IGqMKHYNopH8QPULQJ v/b0EDAjYDG/9z/Tg4pQqyeLAKcI55Gdm3H73f+/ke1pjd7BQnynAhx+2+igMw37CTkcxhTSCkDD Gm2l/9SdwDgRHzuMEQ57PgpHLEYaGHBnrKdeKrNhp4UPvyLyRbkRHHWiV0A5RJj2bbXxwT1vTgyY T9+bzmGIL7wsXbK3fNStoL/EgrlKUqXii+BSmRm/pcvjQS68s+/vR10e9ujs2pZEBAUcdgFp1Np6 3jqF9TfD/xyuG3W7pHcvVE7mVmmqBw+aJvFTHwzM3BchWTfiyyHLKWF0quMXVo0AHG5IZr8sIEYY Uch++YW7b/NXnGBYt6+f8ckA1cLdC9McqffjRQeIapEgZpbUsqYB6QBhubWqD+hB7dtFHdo+1HFu O3LXa2AtHuExIsAAVV6wckl2bfvm6wrNgFiTF4tgWgAbnVqYOiGgGUNp23wuouYO4hvsC6ip7/9a 7lRzrKHuqgSDhibzyWD57fsQnFZwb43XFcdTY0NDF3PaBAEsrHvOkIIlqVUwz5tThIc4AeW0BNmZ UsijESxfis8PPC/onpIbUVTy/knA03HC8At0RgMSEdVWVSPbLxyLH7xndmiaMb6Pr09xSaLctHeU oqbZB6kmiUV2Mo4E5ILz836Y4PoePhUI54qg4m8M2YO96Q9up/M9zRnFY8BwA0yRiW5i+xRejUOF xKq+tHaM5jum8kWfbQqOCKPBRT9rZZx6f7lHAmMWKg2yplxLqnreNh8OSqBWoEjTSGXIiU1XiyAT y394MLg9J+WtAH9ibJJYyzdmcwtfu10VhIULrjM1ZrwMpn729+nDloDry7TxWQolzrpTmyKkjU6q TGfClA+I6Q2c1780ZMgXIvsS/bFIqesZcmNho9DQb7T3n/+048xN8LSVhpndfEf6Ie8YMx0doXyi EPvo6am19Xk3HBIPZSQUpLJhJRkA2sStsvEbB2LARxjTvCQ+EcWBDX2AhugwQUtV9CGPNHO1EoCu YL1IeJt3YScy22chVgYI/lotOeObandYg8GLmdsmLJ/fLkC7rQ4/dsGKUSLIiJeAEicIwWuiEbuV zy6IvPiSAftZAIoUmDQZ1UWpRvIiACw9XqV0sCZF2pNr1usOAfavwy9YxnNQEAMGxQQoRsz4F4fY +MyFLO9ty+kcUGZFVKbNnh9RUrPzv5hl4haq3byq6xaIShf8sHFL3YLXRIO/X4lQF2CCLpBQ7PkX u3kSUNOG6OKFKsSkvtm9hHBfRUX37WxHpip7x1nhc8JzT3f4+6w8NL/osW9wjC7yGbULucbfqvIH O/z6f1t9vQsRf/77WVCe9qIhwWgkr5vIHToxG64aQAm3uFsKewMrPDKYe7oHHzLAtf9vHXZkTkuW hu5th4aDZXxWh/98qkwHjnWoyqJpffX8xqE9aW3Qq3VR9KjGtUdCe/kkQ2q2XQu1133Hwhboqx+q 8pEJ0++CwKrgcBP+lG4QfstSJ11GvAvItccXpf1X212TBa309vRmX2hWbxEk8MvSCr4UeeJL3DPQ iGZg+HZ91TdqcBu6526ik+piEZHS71WHHU04LSeA37YWm3ZlrKnZHvphCrYwpIw9MAdm+JyhuqNr yJDjaGEpPTVZJrqL+OulodH9lvMSpV/H0duwCykBRvZtO0g7w9Km6PrEBrY/K27NuzCe7mXnB1kn 1OfIUj/vKMERiK4S7eyjHfdVOPLEQsNL6lzYQYK++NZF53TbsKNe5RYZKTbyh24xlvgjyWdXtMP4 3c0/Yljx+qNRzHgI4BZ/vYfe2OISV+Q6e3rFOOyGolGTOeKBIudfSPqbM/z1nTyosnR7cHbmliYv pcGXNaiau2VPKz6/K5AeWHu358OZ6hDiFY7LCiHn+HU31axIB+LGESuBwz14oTPAkr5w8ZR4KjFi Gi+AzpdZrx79+Si1jVANgaRG+nmXXTw/e0nU7dO3uOULwLFcjJX/jZs9APXpl7M6qIqADdfX8owX +1hNdlT01rEGE317iLwBbSvy63n8biyJiDwnnR4ykjGIIrZmW+8ouG2GV+7kHRc+0PFrfoW59QO2 xmtSyEuBKw+fTIXP4SNLTmtwMf+rOoVa4N/vPCBQPjRGk3F3CyAO6FDS2ThrSYE/+8h0JzIZANyz VEGTT9sy9QJOPclF3djR0obm+urZXYpMeoq1XMQaWAJnj5L771OgJWjNVv8nQJGfZywUgViUlASs +wnUWJ4KHbBE0XvWQ9gei6UwG/OCdwVJSpfjuVUEF5SeIfFVHxwu/LgyjprpJ9X3W25Ykp+v5YNZ SvESRDK1X7Ji4j/XdRqG8jZYNQxFc4roN4j2vbbH3mjIpko3MfPpfeamiEBatN0+VPNbDkPcwhKV SXqd+izcXA05bZd4rj8iYSIqGXZtMQf12QN7k9hAYiWexIzTPEqTICs/4XJZTIm76hlbYEZ3JjO4 0i3Iotk+S169hqwvRkaVgwyBpH2xDw5PW85M6f5stdrQXK7ROhGtucel1eGLy8aL0Y1iLeKpF8C4 kL9pnDpI4dnRccKOSjBxr4MkMdqRwzHBvLo59zLr5F3ggRLYWbbdfUnP4J2/qSw1WXp9YHdVPI/I hWuL/bFAdjhVpM0b8LrpCyXozk+mgE3w6dgZWBI5KZJOGjFx7ZpSTuxs6/l0i2j7Gz4V6gFD/DOZ NBdWk20juaUA+RHzLVpJk/F0akCKnBSAnC0KXUq47EbnUKpbtB60CBY8ja51poLbVUnPkqoF8tk/ VCjv2zm3P8/MThuaoky7wko9/ESteXmk34Mh0cfiStefZ25S9CLnh520rGsM8YBwGOjByLYMTH+C MbsUWOD2XLLuqJNzu5TWSScUqUg/PYkHXCYFJllSf2v7vC41WPcw+1jre1okP4wwMeILzCJ4UCsz RxRftplJVlzqk4sUnttjaWvK8VuFu7/QwAeFPM6H26ky87FMnSF39Kvwy2ZS7RVDuiU1/RR2IKCl c3ld2RmbKl40aZLz/EREXYfD7xrJChAMAHDDa8uL5ujIkOwBkn4Ijg6loWfwFYtqHgNyslkLlo1N TOEDlXrOXxGZzoGfZ2hd8t2znmX1QXWu1VEkNTwXq2ow69LfjTTnai0a7ddjG1+oOacjO1Mgji1F DHTP1iMnYsdrvzKguww25R+YcX27/gK+ejmZon3lfD22UCsNfAfnRtIWeFfQds/AFFFUGuBTGQyu zgKgjFuFXcbSbe/bg/fLeZGvc3IHP2vk05SQLBc4UI7M8sSU+nMm8mFQPJHQdlE/YTKr5CZJ/jFg OQ/TXhNNkbJ4oT3sPXwXoFndVKLnI8WCP/y9DPR82JUgXna6PjUO7H9SZoKKpSUFoY/hTilOKNei apQitBuYrkoXw4kjsZcKseZUG3m0SZK7wo97ExLe1a+INyoZiDyVGK6Oz5BGNyqoi4CIHAViYUoF 4SztQi3/P9jO5NwNXaiKjVyL9y+OdFitTF5H8qwkdWpUNN2CvelgIDbDx/sUOCfFnGfk/N4lbnJB s7eSpkS/kdMOANWzqcyRPgfQUiIhO0AOprHQLnMcZNN8fvmPEKQQNifEp304r+BXtXGjfF6aqwWR j31imJds1Z0ZZtoXlQZSC7D7Clukr8Ps0beXpru5LcNyM21y61aEKcSOcoYl+OcPEnDatuFxJmXy ztwkI0XiSB2b1qqijAhbwz0Tx076cI2NU/2sJESToAEAI7TkPgokJtzHSyNo53pqSjuROFaL0eYL Pqxb2OOPdMfcif8cFC1y2xI2WYklLdbeNlI9F+yoNXHM32TgRgtHp8I0tMvX86tTzA05Zo+i9UzA kHH5ScG1yUK+gseoudZScVDGi6pD3YyC9WWvpcOl5bwJebosLbXna0C201ROUUxQcnyvWgXpyV6Q 2MFge0R67zWAAfCQ+p621K/idRa4LCc+hhpUGxSri75pYxccJtshdl17ThgvIQxbsdfj8imSb0U5 Iq3qTs5GnPAqEClYsEh4eicVQoXTliEOFIRSJKShHGMYcbeNe5Fvv9RwA+anUWChCKWmFZSjcpsR 2OofhkYmIcLFCc5r/2hh88RbhNrxP6uz4j7yaTIGSGQGu6huf4TDOipZPs8PvEKLiyetkOw3vsPD 6FuC6MoWzFnn4hhWa/Rg8+hLLfv14QQyptO2mU6YAQSh4nDIwcvUQg/CL3vU0AVlc+fxDHWtwXaA 0R1g0MFA64DdOdCcvgbiRZjJgkS92nrdAURf8HwRr1gbyXhVYWlGaattodL1deVn2onC71dVIirn W6I/Uyy+t2Ui3dF80nB4+UVrKOjcW4KShQtqmCZow1tJxJaCS0EmbCeiXv5mQ5yaAP0CxrauKmDs z5Sf3yZo9y6JTt6JXTvcEl0UD69cosagUJxza64jvho8M/Jm3/5vdDaNFIy82IiEqMTfjbKLUCBC BB906ikydCU9NQVGc98Vr1nYsalBKCqQdZi//Fpgy66uAeYqINSGVMPhfCN/cDBUd0x+VzZmwXqa l6cYe/Bc+jjxmF9kvnEfOdqQw/GFAgjUkK6azYe2UWsM2pjSpVYuf2w1g1vjh+OhjcvCDsnNnXpe UGg/n406vSimZ5pOQ8UcfYiJUe5MQSTFVmMuaCS3CShYNZWWHyeIqew0J64brwwlRVAx8yk0L4Ni ZH2DX7x+2gTx2R8VidO3zD12On1lhGoVAznIiuJmFjXAYLNPw/cRRrSJl+Z/09ZbDsumd684Ujs+ mxEI1DMEFLpRbCAGP17JMD9h0ZP47UceugDxnmS7gjcZizDWobEKam6Xb2wFq2yp9pca9ofVKbe/ dldRu7DnbGlCQPIK4LlXHIQg9t2WJ7NgUadqn4Q+Ud+FZGlYE2bAbvxGDYYDv1De9gLlOnYrYk8U Q2r7dlFeIDr7ZWys8YaxZqQ/PNg4SNn8Fl5GwY+k9gqi+yKwGo8xdvKL8VpBbCTGAcKHYO2ci85J UAB99sxeKMpLla5labUsDrhXJe6BW8Ute21MZBZHzDyPlEtg9PDyCHyIDnR+wsEHHd0j3e+NvvTK XN2F2YdsusKSSDHxVYIppGpYl1FkrjT10oju0SPR7Am+le2zUxvtVeHK3ChgcP+r6K6pRiuyhTWK uk3kUlDjfE+xP5Ns3PMZtKL5gj3N0z+0O3aZtX+fzkSPLU/3jHcv53CQJCMSiFNGSFmr/slHG6Tm cfJVyJ16ttDO+xnMxmaaJP14aJNoVZUUwjyOYYnP9IQg47xsM0ThH8Bf5MvQbif6xlrjbnCGm0Da 4MPy71XLoDha2hC9s7tU5Otv+7mDv6aS1FDQp8y6IU9prJoUZ5G3PpzBfNytPWPdI3Ix7Zp/uChu B5TTF6DTmMD4qY3hd0B5RLA0s1JZuDLpjEtoqeYt+D+/r2Q4y45R1IHmHhuvNHNJMB8vmIJgB9GG 54ml387tof6vqtvm3U/L04qpz7GyBCdncibySpPSRc0SU0dlMYLKg7v1mEYg2CHWX6Ap3Hc4HjCH Tigb2rafp/g6ChkRuujOGcXtD4hOdsiDZ9IOivF7KLrXL1PAyRAicfBAw49wVWRlfcBFsLrGxS+s 7Xubld1dp8EFn7YIzQ6uPIvkVZu3L/oPetxi22v2NJ3giED0uv/M/AOT+8lTDw+2KAcUnVUTaq/7 GER4qLSulG2oQzpvLrRfBoqE+CDELEl2W2TxOOm8Y81Fy0faFOMMFSoQ8qBYDBkKSnuEKWkqoNm7 ALKwCXKjJfWN8EBmlVsVC0DUPNsRdtMeUCWfvXU0hsVZ70FoKkgItp2vCeJnE3JZEkWG8iFUynrg Q8upmsGoVn8XewvPA6ndsGeLYExZjtAeGmKbQFiCq8dbBis3KzynUHIAL6Rd6jT05QSe1MdBzkel GXDgKPbserfaxmhBWONPdfbHQ7csmKBW7Qz2Yg2pM9Cc+IX/t9DdYlAeNbkzmPt5HvO+w2vyoyuU L/jK1nkpqhWCbNmd4pYlPW4k5gVYdZvfMce5e/U8Jf/bPevsWEnis519xSIN302NgC/H5CLGx4uy 9skYC2U+DjctCYLcv3Vyfcnh2vyKK5QMlyHhLss3fYa/pflADGd2zjFkS/N8Cd1V+6biwndOGdH+ BHapnz8K+XJdCp7Tqv8e/2DVWLfG6dv4RoWyVOxEkrim004rTc06q6R6/Rg2qxAiAO52+FGUfGm7 fJ/YV1zfimULjTp8Iy7JGbrwvOqDzoqSWksvkPKVA1Mgpp5s2zOsFLyrRdaeadkNyRlen64xbLo1 yYoOWXRusjviifOshUWLKdon93kwc7UxY6BL/yS0/Pm2yUCJsb4C+KT8e3sN01ocUVNJ/7GxW1NI Z9AC+Pn590lOCxqNxGXBvDNSnVPnybf92oRVasP0L8C+bmZ7X9MdUk+tHRu5W4ZgNxu4LoIq70tn eH4dzk01996LNYd8eZCg0MIf4zK+BHmsTl0KJHCwnPGImd1WNlyZueba505RI+BM0tPhhlASppKF gJvnYUBwXpX1mEb2wTTizU+KlA2bvVkSNDlS+/UqqVLiV+I9gAD+eLMuj8yiAhCNLi7Pqp0VXJG5 p9ZvI16TsQTXQHMJzqwlxVNNfXwFo7Gum1bs+8lo1px3eSIq6NIxGzOiMXuAQDv8nBNxRFnY8bCA QY4ZJ5hp+GI8ibgZsSgOk/h9sprlhHG1JvlXzkVqVCklkOfCvOV1OXbwytvLH71m3qKe2dyD884A GBMXX7sFK4DIB18jBG0rq+uJI6L8gsqB5xT+Jh06Og2x9bk6LR3TaUhZYVTZPElTysqtO3DBpHXX 2RRB0aqhVvp5p/Ap07PAZQO50D3L1zxQB/TJCYBbRX6pal9qXJL9aNxnY0Qq+JL5EDJ9sJT5CU1x cAJFDsL6edmGybQnb8YoRRQyjFVe6ZdUxdThCkDuf6LG9KAWVaXgTnyq9tMH5zj2HnybxXvUV+rC C3HR88Dyz7ZRQAh5XNbvfxxkzGJPnipxY/EkSLWM5mTagt0QYqOZn2yeTNOPe0B/Fqd4/Mp0OWde c2FkrLPIGKsYHPgv5tClW+qr/Ta2xLemSq/v+5TardPqaGD+l/o4rNXPxnC+d/oawvTfazDbD0lQ pz2fVYF6YgpseZbfrawabN31NIBr5GvOpGbzzF+4wJMbkOad56onJuEh/h4lKZBE8dMwuLXEUOnc JB18SOfZWF9hMpIH1885+GO2Q5PRg9ShxaD2hSF2Q3TCpQosUKrK7C0rgvHHR4+jDpKJPLTMnY11 tkH7ODXoExhn5d9V+chTuUlBf8rYMTJuxr39Akh3Lrv14wlL5UIaOG4I/ePD0cI3jO1fSsx7bVEx DRfmodIl37FWXK+x1RUp3do0XsfHHPzY4fKVI3F4SII3f6HC6MwWl2n0R3l0uL0s490a3rO/WjmN Du1zHbgEly6QvSMKVJPefPi3KszUV6OiCvyslfYHQIGP8815VXBfun6kGvBsZ9JCxavzSiKQU1MY xHwNOh/HC5kYsU5Z4BqCEUc1ylGmtAvNzZF5ZvsgTMMUOfXnSDo3bzJ/yq00Fnnzg6Ff48WG2zVz PT3lmkc059KvlQjpZbmrwe/a1KlYDhypySQBL7uYE6oD6RpdET7D7KQvlgdG5FgOFJUDHG1s24w/ UD6X+4XqZoVID9c0YVJJnPOalVXC2H7pvQM91jBgXG8l67Xx3Eqf3xv2tT+8E8ITm1Pyd7OksRjR ugUBGltGTXVpSfryVgU9WYKdojg1xhAIpIkmXy3gwackwIuK/oT8BdcgHGjxLIIwVTAKkesdRuTO JCyvg/5P4q+iDBBQ+BM2nUAZpuECPaLx2Z8d/66uXCSfwtp/W3igBfBWCiPoLToteLdzEbiMg9KC l3CLqo4JfTSDPv+/9yAaBlOERs4UST9lU707wW8e2+SsBLOOLVRmByAr+IkirxBFXXy6Le9JvTMT Qz9ek5SOmg3J/ixZGqD2feNfVvxuQfcn5DrISx1bk3hJL+pYxXUlRteggmvaR4dY/I2PMdd75maG VkZFMFGUvAY/fGYcCmEPbW8I/hlUCceyKtxAZdj91tvCP8ED2yTmdlwCAXDu9y2aofVn/O6gON2K 883bZBg9ZHOxPXHILkg48fQp9NSCjxNJCc7+r8Ho1BlM5KLDohm6RIbNDdgr34s4aJryOFuwF/IU xaeJ6iPzsiVZlWp7ps9RPJOL1P5T2fXE3il4cfp0vzzYUKhR3NLUWMaRzuw49ulSIprnY2YtzrJA lFJVCQjDPTqjmtZdD+INdX4btU+zs3V1tIvND64G/HXwPkoOYjX6dTUuJOdFqR1iNHaGXIwIyjtJ 8L/2wxya8NH2J+awJY8MiprLSnJMXos0KQElultVRP7pJAkp1iGIIYsw4wo6/pC1z9bdaZfS1yCt JlVsMT8cbM8JX2PNHvY0w1RNJkzT01Z2n+rxxAKMWvSbWf6uT5W0AKmDNem26SGsjToGDj/8mza6 U3fCNlQspGMDFBJFF4SOFuaSexb0uy/Gf9BwXOdOCCE1w2b+0oFQPfqxJ+7MrtLlY6w4gDQJllA7 VAGBPpjN/33rVfmRkfB8Nzza+vbCEC/llabc1b0H/eudjtPTBD8rz1iQ4UAtyE3SZEH5zJVF31J2 zIsTcwbtWSRFQK9znC93M4CZNaYGLz3VzP1faen4jqfm35nwRsPl5bO7hrv8mBLeTNBwiVco+8DG w9a2oS6RpVOF+7I4WO1vUYJHenaVqH1sPfPa6yJq6VyvOMDsHUFzBBy+tj237thOUfSxKSnNA/tt 0Q1t5UWvb+fz/UzuvGoeFDCz7Q9xTsNWlpK+IduuIMrVQmZptH5AvscswuQLtH5qyJMMXko32UsA HKshdzTeZHpBkXkHkppiiromqpH0UZKUK79yHrX+AQXIdNpwZKs+q80iV+eg9isQUEUDUa6f5kXO PkdrT7fef7mBVy1IPZhdQ5zS+AbZ3s8g8nmlou5YrQF7xU7LJs1eqCd2jmoAeUTYUWDKP+696SOX CqK6ZeLQC4nWRM3QZiQBVnzooZsPD4H+KUHaICyYqHfw6bP89SgKEak9sFeNNJQNoyjRcLKwOgaK iZZY9nedGenAxUmHffUIlqF+l7naSO8mlHQ4ik8QaeSHhoJlThR0oky2R4BwS5SW0ECjBVKJMBAC aljivXLanvwQQ/ySIs6JvnHAge/Y4qvRcylcG+cb+QnNJRXZXFvUMZCni76dH5uKfVMciJApwxBw Pee2ObEhVpK8c4L7S0W79Uf4GbrqzxeomBbbyYAKVg10j/Q81rNHtA0f23rPZ8/5C57dLHM1+7i7 BcMkirvtI5DxRt08KJ8/o6vaIb8UIghDq8fgFHgRCH3fGKLEIIhdpt1hDTU97VOAvA21frDT3xec kMxId+mNy5WiDm9lpXncEyBhvg0G6ZVhe35t82ImsnHwkV+ZYHWZjd0YWLCwcmxoGJloVDd76m3X 2nHcH+uAT8SMeeTVhbzrP5FWpMbBOq0sR3kr5twtkyz/JKIxw0FaGwA3bFHTWQy7iwcyckXi/c1u Vw+KXpozjYvJI+17BZav5IZ0GmxCSdyoD2LvssEN0ioFUJfWmesFhLiJ1/yoPB8UfFp5Mbbux2JM xzs96Ywi/EzwvSqQ2nRtCSd3J3KxYufHA09ddK/gETw958kGWOe6xylk2nkJ34o4CT1HEGyVCzm3 BT/VJ41CDl9Mf8LShQu9lY7gIT9DIbv3504IOmZQbtu6nkg0sEw62c4RS36BtjW0LaOKqfXLC2NB AK+iBZUk5vW7QmEbahYU2NvXiywsGdPqyhpT0Ukg11oTxKDDfU2NvFLHrocImpuOOhoOfGIBz8rE gwUVM7sX1BkZH/rj+1GCrqxHvS04NirZ4swhqvM3oByBI68SsF0TypiNQ+kx5E7+3nvRfIJ3ler1 1gBaRHWWWS3E8fYdhUEl/DHlXRj4g3CqG1zQvOpHPgD5GcoftpPHSxYS+nt2z2fCRYGhbZuXZREH HjT58RsJR0xZa8/Az2I4L2SmNroENxmCLenAS5n5tkxT41zoouqNNzmk1NMxF/2bDmjrWMBXebMk u5wzPcRB1FUiIWd4k6gwDBZfQd9GrXaPCkBccnJPJFpxSMyc/YO1J/GfYwi1dsxQtutQMcbg5Ffw oN6A0PfGXtzAeNo2MDGr4xKQPm09OqLWnGY3AJ79IU9WvkCn9hSKaEk9sAZoBTeSHJzj7s1BWl9B q08d7FvSLlGQ/l+yPKL2VoXvq6lx6rZfw7kBTQAlESAsCtHF/srnD/hF+4szfh15UIltsBI8t9+i tA7ha5z81wi+LocvHEECczMwbaUMnYQ6Y4DpMdB9QL8sft1MLXYVdElSL+EWV5zXwbAw04Cw200v J3216wmO46Z/RNzxMwxRwnvMUcOWAIlDKDnSjMaJOOPPxirDKeoKoWX8rMD8N26QFqJnjMRwku5D HfoYE7HQ4nryO6+HMKafdBHY3R2PZV0lh5UpFkwUu2JRyve7KRCyiJj1EWmSPKkc6llogG0Q0JFh cpsFAZ/Xieha1+dodInYmgjM8/aRV/J/0Avj/ZpzY3MIg/79kSugyA77sxbjugMW8VI6GzDHIL4B YhyMeWnIE9OLB8O0h90Auq1YE1kLJ5ZgF15hn1HdKMTxKaFd0r99qYx7rOq70h+HRHXPW/SBQ7/k 196cnV5lAzbw49V3sna1T0RbRh/yD9UWtgAmc7X/9Yd8TGHCzZ1N81q4/eFcSN8KsTVLNtuEsdj4 ejBJdYvFTsMtmh5T5do6rPi1mjk0K22t2gHA+ZXwEq/pTjC6POVyPpXyWqlWJQl6otD6KLq7eari 7n31C7es6rMrBrqL8xLknK50lH+3iJeSFUm84MWJsGeX29lah+wGK/dgCiQILQTOZf/QwFeLF60s 7ytMWnqOgQr9xSMewfpzGqK3Nvk8qo+QdOLIGtpf1usxvnbDMdj7ETjYIPPVdmR56h3Bd9HBqZO2 +F6XSN3VicEbQ059l/SvbbVRgafRrG05D3PI5XpX4tTNs7Ga2GEErCXhQauwO0u6caZk7r06mu2L IH4Qf912qXUQtyKi3G0NYPtiEAuKR2Leex8EyVmz4pDNa49oJ90NmfGgdB/TTgCUgau9vebRt5G8 S8EIFDolHc70hCNM0bCI0MMHdnyPbLJcpw7aEajxcqi6I0LZT/ldmwgtkbJGmJQY00B9duApM22a fXR/KuUKORKXEdYwlPN3lOw1rkPckiwZBg4VBZzVR6P0JAfMvCvcbpAFSBMZmLsA4Xo2mIHFeDZc N01J6tnsc58FqbH53Ly9VB669Atmj+LSO6W2uVWSioaC9+fIsiVfFWPK2xOvLdBJzCxE4KBEcnlI cCImzfol9tajjWjDnBXiZIdWA2xLl/mytjFTdnU4lQ2uUzrk5jRjYYW6fZT1Q19BSrOHDHaf47wd T+UpWSCwUFUZGXr+ZjWC0TLam6UK9iB0JNbpRdgbB7k9GEF6fyRa7VBggEzAh/V7OwONSg1ZbIdx LCEStD7lZbPAYPVio4wfnSZph2C0G+/Hgcc0hauRAirZoLWJ8+4o/txvKxSJ7c0HFtcC+iDezbIE wg3uP1Fy1GtscQmqr0TR/W05U23g5jJAdUqtLslUNopN+dkATn0WML+M1g3fgXyAgUMB/OQGsLGf R7h+JZWNrWlqBJnqevcyqGyIh+8aOEXdVbEgKRrv62p+mjUGRfxXp/HVP6/T3hqDrhRmhx4jXAll U+elovJfeADzUT3C1Ve53L6caPcIHtPemtv46iCNzKmV0i/AnwS797tlsUEyUt6TJSnJ1FklYXPW X8ULxQKlozZfPriWZmfNy/kIH18QDSw3yRiil/+vIhkwAeCzFgUSMnwdDBNA8uWVaNsGHsC9DC/i kzZodzbv3oJcwKN9BUbPDjEXcZzB5JEsMBQqHeXrsmBsuryBfVcXTXVu5UTXleC1mTWDX5wZ7BGX 807puPYqCs+XK9OGpC+vAa85/EFV4+/NnqcTO6iEl0M/jTyv8UlRMfAGYgCp/tiU3q0JN8QIv/YQ DvXroRD78IGTuyiZsvUgR7IkVCRC1Uvyfqu5ZHw4iRJaYGPEjBAKnmou6xyunxRe1ysklMk7xsZU 3AtGgv/99Yb4/yk/gQBcchjbXDyDXgyQ7zCMHBbeCj6ZhFQUUsrsY4HgJEOHerIANl523mezHX91 DiI25BZjJfLsiEldOmMrIxGOCRQBNzKKnoL537fO2QSxBz6WVZ1lN3tdeUzFkembrODYuyVkoc+o 0qME5o67GOFOPSxkVdtfV4NdLU2QtH5DLWPdxlKIQhMNGoCWy5bbqyr6/RzV/qAGLfK9xVtS4wKL ng5lqs1mcrtghVTnE8Am7qF8XLMkaqSBNleSEVPStOF4zlW1UDHHE7FZiWMHB4acLHsi8cVRaPkM EZM31Q89ii1bqRUNZdh8gcun2vyiLUHIucwnkYXu+l8DTJnQjEz2CK/pV6kwWF/ZzFU2/4ebKsq/ rNcKpHL/HZmCtFlPTO46ppVK0uOuzmg/GrW8O558+ShVNq8IbLFpK6/kM5blQbo/Balv+Jb+I3nv GBm7FxZoP31thbojXQWH2ICP+WU9XD60gEjrqFCaNPemXYJUtHayUtAcDPdITulxMG+1l+lMVDgb OSCcHSlIhlY752SU/W6D7AR6oE9a1yl69uaXwOX9Z+C90YeGpEOd1owsHLMpkr0Pik8QPVC2w4Jf 1iajLdN2uo2Hc1UIAfT900PePGpjtlKCqB6vAqkNCN8komBwQ3eaio8cd9jdhUmf+Ah/8nvy1T/g Y7qfv5vyZ73JT9R0+n5iNDedmYEupAyKOTMe4WNRzoI+HtVDOVVI9P5ZkIx/HNdXH9V2yvd6mov7 s4dNS12vIgv8yEyaiJf4h3Xu5yePWXacO3sOz1oAfd94rRxQpzefbhEdOHgzeBxA7273MSboGuib RqdmTr6MMEoVWxC4mG+BwuD2OuN7so+DOyJnOC6QBLKyHA5jqMgZYhhYk6DMi0VwV2OqDBE0hNme 9dCduQ1tFjboriSxI1qmQ88dy7rTq/uwvwZHotOKsyYZcnzkNCDm4xDSiHzic6q8UTKEfWeRTRcp YM0s/xRZXNvXXGG7ebrIbsPSD0KusQlNFPRXoPL23tGViytXCu/oGI6QT5/rcp2jZRZTk5uHsWMw HwbEhOAervFvmJLnU1dkpx5uJO5kIFppg/8FmNGawdKH3/M1MllPiSjRWXk5HK7Rcwn2uaXNwWx9 EeRw/55Zb9BBhCUeF+bA98kN6f75yN7On1hD6bSLwZ1sIlMeqFsDqb/B5dkRojmKrN6KFPQHq8Za vD6BhTmKWaJvb19JRQAaNPVh0PkvzwVwfPYOdaEGGukpnuU9OgRT2jwLCN4zb6prqDYP7Y0axhj6 2P91W6pnfAetHsI2LTaDNW/xDEce9CKGOuXfpnOnbuaGrgic5tUuANNq5YzoAWmggyBL6OXhWow0 WQhOaKH2asr4ytQXqvje0emxlVwRSyT92HuhRuVa7OFd7p1/EY0kV0zQENDSpQ4SUcS5rP/Olzc4 ioFY0Sawz74GlJ/Gfaj2D9B6t9NgwVYvHLxiSrsDeZv0gOGCAprSTPD9k2NE7dkd/eX5rIO0gWAJ sOdORGuv/9NP2l1PelwMtasW+6WbtCswOOZPXig+8pxV48EjmGMlYt9VkGDycv9+ryzLrhMo/MUv tHorAKL+pbVey/kFGhgcOFZz3gVsabVVaE+HPOgDlfSk83h/7lpZgfSdgY9Ge0uV+FhFtfLP6Y68 kFDZ2D1RGJ5C4mWig0ksrAz0v2zTY92o61L9zj7XfwkPbviLkuFmJ0Lbq7nvRCyQqDSUpXQCzFgf h4hTk7eFpT/DaSL9C7RA0IZMdGEMD3mlxiiDRRrKdy+UZbIXLhOqItur42iRzWA6RSrAj9uMPTpN qkQ/APd8JeBRFJCc6ruFGdhkUZ4LnJmvdytqWVwsMhlsVom6noNUB9Rh3HsFyTAWlPDl1PRusHSs 16YREABHEfEsZLiHixEaMdYUa6bAi0zd1TVIFV1a2/EFPUat4ou5ZEppEHZm2m/rvFD+NFdi79Zb hpxY1MIjh1p55D80lPPGDPvs5a9icv/XllI9UhAwyA3SLriz6+RkjFaFOSU12QWNHnfbwkbrsj75 wFOoYWFiYu/Krn55QX9maNMZRXM5Mys7X22BfmAAg9mNEQlbECmjVEQjGIPR3gaaHT8ZontKws7H p3eXI3pJB/xWYPIgxoUnQFP1Mb9oGIIU2nWCpKBgEiceymR5NKFNh+dEFdXsX8rYLDM4t/4qXFzd 7foECoCk3lqbOp9XSDen19uJiDX0u0P0FhMkisQWHLZmtbjuWxeFyaWhJISpsxNGCJaSoo2yyd/8 pa5cBUnnCZa3uoVQY1QTzLedOQMeAwfNFeYg18cqzxO1GbhMM1O0xBxksK4lKL8xMcUCssanhHfD jxQHSoKdxnARdUNBaa4dYMTw3feaF94UuyChuSv2lWyD61gpz100efrbjVyseSHaCZfGRZvJRfnU uKX+UDtfpWjsTvqKIb27VRzeo75FUTesw0DmMk3ZWIPNW0sk0EmVdvchy7LDaDmoCMBfha6VhvD+ VGbVBGGUw2oIK7m3uYq8OYSYhqhT+RRYSRwq7uPb/9AcAeifH4q+FD/wzVRDVsdSLU87BFtKN+AJ X6pHdx4aONIkHXdYmx4cP2+Bzm8XUDgEc5mjlGzvzZle88LpwX5NDtjzTF7jgHiQwFVm9xDoaIy5 h14BsfCHYNm/tdpVfNjMZfGIfhrjpY6zkpX7n8TzqBDWc6lf22Nrk/AMTJ10RFZbYJ92FoSdkGxW r9yM0MG4VYduLnPIPm8Om2IAnHmpqG043DLAnAuXzowvPqcNqt2R/jq6hWPqh+VsZTfEAdc+aGYm WeOsrglQLouJNRlXKz37pG2MKn5JBDWVh63ALrNPmten9/kx9x22O/TAdbZCZVzC94a+A9Kf5DgN 0ql0dPVXHRkNyKu/X7xuQN6xsA01rqz+pr1IIXuawg/JyZhsbn1LFWPxu9mSL7pBWMJBwKorooAy MIglzsUd1qGhZt43b+xgrAcLGSMED1WG1vGTdwN5mXE1gcInAaGK0GvhNzRRcfkQJMcCm9RopVOF VihLFeHBBl9c06SueKKJMcxtruMi5T2yJazLY8X7mjVd4rVmr+5T1Pe3FSkxFM5f0Ch6iAniO4Wd hnkyyy0Pt++4LWFrn+8FaGkQu3EHFdqRFKHwbo3W6UcxBUFsn7JAsRi9FYIYKR6knhKd8TmA/ISW raUlXmRcXjMkfFf6z+UyaVN+5XbLqfPiimlUe2m1msuCDoE+IPtNvxm6okpYYOqzXLpxMDPnyCZB WlIh3chyIWuupQ5zhptymsmqb5pZyVicKtC376wcaJRrJXtwNvCbTVpVGZne29E0mEsGHaKtIxjV 9dsMXc/NVbzmy9dTidgsFRL/wObGCGH6/cEjBEwAlwZXeMQcGXMYLVI1y5bhiEbix6BFnYoIw4xf v5CRCb3E+CTTF3r2K3v6/CwAUkXhZ+dPds6lz+ZFby5PSqsr5YzOB3GcoFXJcWlMt3dgBCKeZ0rf I2ShJ3xvXGyTB0++GLeKMXhBEXthFNP/VQXZb9uT/HKFozHZSl8jPApjFjNXlVkacGoh+yteGg04 bTzGd67FgSIaST7DqmrB0jYPWXswChw+mS87lRxH6e+CF4dHiwA1zZot1XVRKy/MO0PhBZ/j4+k8 NHcVrWzAgO4YNLCW15/Bh8sI/oV+8NxaPTt0Sri78MuVxYQCxC0dMr6atzs6jLe7BUZDhWyouDdc 3fKcFe83P8R0LOFJGOB7fnZUr/tpW+3Q+Ezcb9CHjVdqsUdjEt8inXeBGC8NQ0Y7Y2tuMxZ1CZRv cv3/yZV6i4/S1YpTAkPmohjbVoSft7dkA88soA68Lv/RMD7ktqsyyAAxgLaHJWskglMCGoiQK8D0 4Sd9/qEHclbOaABbz1eb6crPOs5zUkoVTONjuffJuGGmQ2esxAgKgWjBWUWU4+zEe6/U61tzzuqv +s9PZDgFvxSKPEUSaCJeHRweEA9m6cvgzAPZy8Hvl+9fLcn6emrnM0xdC4QIvO0Y+ULermlsyWRr FXFpUvsmaRCYVXgs1khniY8Knl3F3l5dtuW3d+ZHzyEGMQ9Z7GovEijlnWNfuM9Nk2k6u1Mp/qFg qhHtBw6YTDFied1Uz2tffvVPX8Pv0rHx2DtHwFjhOTfM4V1WLwK8LLnniA6Xg75m1kRdhT9lM+Oh HO8BLQeNcJ+TbnhSrhoIbAC8A9UEFUd+AB3j3bPXlMtYJGPg8bh1DsBHaK+jHvnV2eO9ke/Hg7F0 XWp7TafXZy0i2gYphkYL7ffpOQf3xhJrQOQebWLyFrQ3jzarW9wZDYnPhP1YLE1+7b3jC9JyCPft YCO+R+QM5ClXYYIVJkcZfv+hbod8j+sl13aMNRNtac56kzkVMaE1Q6ImOLrn8wKbUHQvk9fHYvSF W5mAA79FVwOzjeewTUYkNLy4Tsqw60B79ZXwZIgsDSfFj+MeE/bUhDHdYJljGzV0XgA1ncgNzAAL DulNEtQuQPxx+8A2qR8dj0FkKl0fL0Lm3VqqYlyIVasj9JRyvVRxumsthsQecfd71VtlLHDIHUBE I8IsMpff+jUAVxPfLkxP9sE+j6ptce6aOVKa/z7AcCtG/13yD7kIEHWRFg57VtLL3jya5hj8dfbW nU0LY97V3o/XXmtdseD51svYDNaNRQGK6Ruuls/F7OJdhYrYDxYvAz21bupOQQ0YsbdTLhNLwVnZ 5fn3mh+Pefh2SzZvo+ZkALGqCnamOLXlVFNGBC9leSRfqZoc1rRU4T5nsvVacM8Hsu3QvHpqnaIO Wfhns3cIzRP8eKG6wpqvNNs6FvPE/FXWwZrBsrv3CbGtYjcg7+pNc0BJIfF8P8O445GpU7WbuG/A PoSlAFQnx5l/kWd+6jsrp2eP1FaDM/9QcHx0FlsN4CsxdJ8yHkrP855/i2FmchyUZ4VKZv0Ylmmw uV6THH9Rs6TN59QP5H1FQpA9S3486/SCoyq+csKIVSqAWbRvNggMDzr+a4QNs4UvTLFouoZNaOar Bk6cW4u1mSGQ55f3WeA6Pb7Sy88eh0FAmCdfovVUTHimHQl9IshBZhTgiPFdyvM+sKL/dK/w/RK3 WkH1yfQJ6lLNlIwstbVjCfn5415/mP1okp+5wrjCGfLceXBUajPq3AMRjCgWKPusBkmS3t2fCAk3 LKXTAKk3XVVitXev+aKv7s7iuoe4Y9jPbPXSZC2BmSDwc/VwmsDS4DBkxXlekHQF35PmlFxa8Jfy 3GXz+D7yaekl+uzYkWlWd17q9ebEbDOimCT0YejXLcG+oHyD7O08XcbBd/VFaSeXJOrd8PWpDYpQ 37hyTfUio4DXQLuN1oB1DtqJ2h3yOpqHNQJaC761flXrmU/dVORcQ4xz9qXununyuIqHiTFtfFg8 7pD2s/mupKwnX4jVvOGoZZJ0eNLCgWtjP4oBW1Gt8E+oSFPK2nBuChb7R6ibuLnGUZy68lotx9vB mgY+w4UwF1AlNTdu7GFe+hQtZSWaQpMlBSrojPbvZWU1ZxjntpdtnVYRomQwpyn6fnaJgIxT3Q3e egP/xcoSOlcZ+6WHSgdPHv1T3D1DNCvzU4EOvGGII8kwl+vJcMKo4ltOsefW5AqBCwnNGZDl3zev 2G9ITPJ9R4O3EvLa+ntbpLrYQjPZTwV8g0AyraVaj43TZQgn4LxH36yS4JcGLkzi0yA3Czr2bbMJ 0DcexXJVw6L8DrimctPcuwmnN+JkaBx5WRYIXsj20YXfqkL5BjS9wQ+tdHsDrCneJvYL8gmXJPwU VlN6hsg5ip7jxtO2kaac4dx25BjrowWcltQFbarni6sZ5Xrc16LUgNnnqRTVxAd31CWj2YFxYWmN 6baI9vOv1K3qBErHKSqngZgH55DxWUOSjzLHqwkCCYezBqm2S/Zjo/2no4qU1xd6nvY3o1lH38z4 +AUvqKAeKX3RAzxtjJT9IuzcioM70p9oGk3eSH9zE2MK6eFrs5yJ1ixfHV50Xbgmbqe9ghpyqLDf PIFn9m96tL3bRH4/oH9Hao7oE95gwh1laQcXr5vJ616ZQAuO6sGH95gL8xDqByWdbJjFHnjSVfiQ dV6dBg1CddQ8VhEgChPI4WwnkU082C2RscrvcmdHV9v+CXMLCsp8JAnGiy1mbmcu0sgBUF6sZ2nW 1kuaIlzkV5xE+EpwWIyGAbAXCR6lJAKapsV3ejJbyNfZvhiFUn1E9eoOSk35iuhSxighkY2yY7IF p+FQKYNctYc+qKOjVHhEBSnSUyCTBKMk2GF0YsDEXjaU2B9zMrZVNnp8/jEtX9W5rhaPVumC4zLX 7rX7PnuIgKsXjL1E1QT9OclLqOacAqUPYWujBnSGwRXhlm6b7qX77jh5TwG4e/aDOgEjSe96EOmJ QE3sIDYKoENcAo78VGnNzlb7Gd0nOi/eIK7MSn4peRIinpRB2qug5KPXd9dePTFz3cHEeAAVMF3A Yl+/6Yi6ji2MBG3QRYtAYXCsOxTuOtNQu3yHJpC2gS3N0qk+wcsd+hWs5jDYIWu2oYT7Zr6J47bc ROnOt6Kg5XVeu26s1S9KKDZR2KNUMyvhWwaiWumLaq+6B12Xg0Y7PQIfAELwOp9d3lU246PO8bcc iyot1llWAOPHTs54RmtGjgK6J44Gs5ExvfQ4gWVMjwwKp+SmeCtRkIe8eVZTGmFCgzeutCnU/ZG3 aH30xMSRELl8owu2YWAVAhIB1jF0VgR7AcakErq9ICVFeIcbPtcYEeAdAZ0vt+kvw9s2V/HGtJ6v D5t/dsHAzbUy98I7UEHlUFqUVWTmJMc1zG00dmf6i3a8aNo+4yi864gewvwVd4MV6aAsbjANxwqV V6Jc+Rll5v90BwefZWRtodUWL31wc0pFWjAzmhrQcxylt8SaETVyvhFsq7+5WUzZuoThEezAT6EA tWtdLIguPpJzbX0/2HTBCZqrnQY8MVz1U5+qHRvcMMTKJXu6pkC2AaKieyxRJdmH9mTbewj7LMQc 9PErS7YhT2GprzP0CF39imS+RKa+GaCyjacVxBGzM9XGVN1YsCtwoY/Np1AIrrSHu5oY1K2cPZ4r /8l5C3Tqpgam/bu9/Eru4L0UxAJlNG9nXuaIvTG01fcc4mqcgDJpphXI+l0pPYn70WJyTFemG7Gm kjx559jIc72fj5J5FMNQ1sZIjl1urmVhG+W7E7odTQPZWZXi0b6nL1IUPsYo5p3nFADGkl/oudER wH6opGFjKhoIcvw1Vk+7rzmeXlRugym8G1OaWiY1v/QfArWjixS64IDIrtr8M0SP1b63VlsrNoGl Tx1lODXaSB8TsqE2onip0crslvUKsfxiIGXhD4KviXhpe+AZ4ZDymEmP2d2yUvIpP2DSIMWaRabs 6L4L4ODUz+RZOUEJqgfofd+ILovzTxRozC+sLEkV9nMFMPsX7g6GzFPR1nNZwv3M8f3FMw3DQ6tv WBue2Xz/WYzG7X9rEUrcu52FxpffwlPuKLqOHQPScVqv+wRdKmGB5vGDojcDf4myxAyHZNh070A4 PaTYG+oZC/4cLAYqqnRwSHlaKPsuFYwr50u+tKP1BuME6Z0PdbCBTU2mmU4v46TjW21Y6/w60wq5 h9QQTbYpsrbGnb6XO9POezS1qKk7EoUj77qqmmLtzsxGLpOD9BKvh8lWwUir2LtijxlgQMDuLwYB S5Fsz0/vrUg4i4sVEkfgDmjxIlHYk3wC20FGVBlBiseVZ/b3/byaNNcPTOMAl5EJvFUgf8gsD2Kw ty1Uc1F6SGw9KWZXwAnN6TXmvBftLrHB98Fk/khHGVn9GxY6Z1mKpyWBgAuARpDRLQLMsKg28y4s Hzb6Yqh+ZGxEvlI7BT4FiA0a6lQWNSshMFG7yb6bhrI/w6jXsx9G0gEvjBRExQUuIXIn2fiQ6e0W e0XbBkHqRMCTjXKC5lC5wccxuR98CGdb3puZ33FygkDdI6By7Xew8Z8zfjMM0aAZdXtASNz0eC5h v5J2T1RqfrQU9It+Yoq3qUIgqk7u1dywqtfRxJjuQme1NHqLosDaLLWHZBJXMkNUrCWLhoOw5twj BYVC5K7JECROjx/WBMjl9giCuEuycJwIKx/CsXu0lXCt2BB50qNwmo/1HQwwB4dizjJPyxmVmUbF wS97VApM5g2EZ8u6zh2BrYvKPBN5m/KaPexN8903k2NQm2WRLcLQq2hthP7xTDjtCPYrYFsj/Nvw 5eGUgJLQE09MGNm7X/VV7TcIFmN/KbdsKAyl5EikYe4fMSWGZ/DBJ2E3gFfSD8DuBUDhnrdGCt05 w3B04H+OUg/cvvY2zk1Rpvf0buN2YwYbTfCSk+mV/D4gWcVgyJ7ZWbAUSBZdcXrkQuuiwgNmbcMw flPngn/A1DlAOd5DCftJfNduk8R2EezaOBBHFR+j4BgDYuSQvLxjAB7iAJu77DfY/3y49dr03PxA St7lRaFwx8l3qY/SN4Be3VEZIUtUXjUGTgc2xRQvV7/lGid8j0oI9e/8pNHtMHIsBLRe3AdT9U47 ZvUA7ACguxzqoz6LGt5p/Sek4UVrYJP7d5IRVe7Q29L5/6t324WWciEB7Ww47KQb4s6y73F1o5lH cj+FYOXxVfPvqPDugMiBLWbbtQEvuo3Q9S8nZg7VwTi7eDGLvFLps5O75ImyCPvj363+oahVnQOX YKoxPmyefoIZW6jRN//SSIzYHra75F8cKik+aHIRAhCu2EsIANr45uG2DFeTy/L0Vxa2V2VewCix fS6uDKjyoV0yMExRYfBUpSKLjv7y2YPqkckt6427Ffb/aVjjsSqjTA89gLn55NjJoK9JfdtpAu0f O61gT4PTIT43QYT8/4Nzx3ezmuOmXBx+ouT4eeXJLSQ1jxScyzzuNvb6wIEpz/igtArdqps0GSV9 34waOMmwzTJmC7u7pYxaRB/F9AKTlkuJl4+k+K0nVMkdpZx/18TEsqcE36CreTNGfn+RmGMufvcv +VQi4WOLBbfMn/dFotgJTja8qGPXY8v0i8wgto2Lh9Z2qv1ugSxosT2FQSezF9f21EYZ6IEE5aJZ 9koXaO1WiMF8kQkoXLQBJ8F03gvsfA2GYoRx7T4sfKIzICDRD8cUeCpSAZwkBak4yqXDyUn3JEnA xO4KmTpaWpxabMLnyCeSRD0hg26qntC0qsvjKoQfcehkd+8wdf1nieVilTcvHTWx9giG1h4GSFMu ONx4Eb3epaISgHtxlXQOvgPSnLrGhfwiIWYuIwWYAwWVxSCgPpjcB0xF8l3wZGGnQ9nVWcaQLpfp 7tD8VStcYohAqG4J7jGohvv/Vbday9201L2mV7ss6ExhfTorlKcPhRiVvOo9wk9s5CxGID7aBIcf s1wvKWmzRpnhk5/8iurMdSwOvqotQHXCTxH/zPi9z87W3fI/xswVKOXUSNvaXMn+eUJtITuNNpOj +zIt3yNwmcDqgzW7U5/rqu/phiZ6bVLVmCd6bEPym/4HMzJNK7XLVBrnP1i3wQbE/Qk4wt128bX2 8fvFBKX8OEyvUdl6oB7KL21B4EnJ+MygZa1BzwjQW6so3xB7nGBABMwJya+frhkzq8jbKxHKbehY BH4e8LOTk92Qr9hNnfg8r9WdGMYlofKIPyOIbR4wPrvLxI0/F+6v64L5HbcqHj+HcTdUCbxpzm8E XKAIk2KEzTIAwGYFzVJ/FQ5sHOcfc6WENHRd5xG8C0FgLXzbWg9QVJ1zgPwpx3Nd+pTGHoqbcUdI DfB0ZH1YYbNE9WmvHRPpQfk/tPK65AsekGa5YaGat6T+IQ2GO4ZWSVUXbHJZ3njcked8PEnY3Ru2 OuL0jeYovN2Cg+/TwixGEV7Yy+p8RE8hua7rD4QtUiMMrBYw7GBQVWOpml1w1bPm+GLc0IMpLUs4 0XCue3QJIxcTc3gfNfq/YwB/avrb31mRPzZR2w4eXGXzdOanok7uuXePa0CF1tryo8cvBCePudEZ 01mHBRH18c3kkl+69vl3rQldiyJJos9YLHcu6h8ElDl+/4tIOrKAsD+rIye3NvzlVV7Ze9TJhX8e 9H9HXu64uzClhHVa/8bKlBx052XPgesINJPs6Te8sFJaa9hpTpUmm4oc0ECh665uk6V8UGYWS1W9 SKSGqhN392ygTXYJHRwQZlPaE8ljS2dzY/qSuPKJyteWDdepTu4CI7srMuXGOZdpRB8ENpk3KP04 mMa0rPvYVzkQYynPNAlhEBHGZrKQ19naOaRpC/nMEUZQ8hglpj7i1r95dXvajYjGztlGX37zJnCO Qk9rgqK/CKDQNngjB0V4RVWnQ8k2JXau4utIzwd2UPQNlWsDh7D2ItFMVxdPwYfnxBuho8sLZlDK VENd13mdb+7mpH+bstyz+g0Fj5CsQ/5V6vXp9CZDY71QcceHtD6MUNThDQZ+JSVtBGhdBCtX4HTM HTDNCiF4wI91NUtCZb7ewVzLCIiqUf2ukUSt61K4AKu7n39hugupIqQhCY5UG2QkYe2XTCRaroFv yZ5vG8PAJ7yX/s4hpIOHaV4NAlk74MEs81dxrgBKlhA8gnYIOrRtqUjFVnHqjO8WXUq2CgwiUlVK WFFnyLZlg0KHh5ckggKHjVIpmdqNyeJOPyf31iQh4miRQ67Ynhca0wzZ/b1ILoU1TNI9S8pAHus8 SPXe00QpHu+t+42BGjSNB3qheSbzJNtoV3WcLvxLw0hu7GUtnvBdEXv/7mFWKWdCMhBT1MgUV2OM tVp8R993UM10iNdPJHHdONXkh8JGmcOZjx800CtAnW1Ya7Ut4WaLskwf2QLFKPS2NLpoBh6L7F45 bE5beublFGtUse/YlWur5WsUBqJ/FQ7Nd/UcSd+IrJGUgFogE/RFGdiGipnGjl72KBm6WfW5xvLO +9QQ6T1HNJljwwVo4miVhNmmAC/Hm/ASiI3ZQ+SKjHUk/uBRjIRNo+1DL8HWGj1Zryk03KZoJLU+ x8mT5Iq9nKGK/yda/e2TolgFPiBS0NgdvtYroFEm7YM94HFNhN/W19pqT1Fu2ieJH5lH7m/+/4MT GSHkeMR5uyopLmCSKcif6AEHjD2Zi6p4xAm9cRhoElKtJ2Ug4MYvR39IVW4FD0kyBYj999peKmK9 1jAX75F+SgwGRArxmuiT4Jsq49qhcD6bP5mFvOS3Ues/GH0lKwUVKy3D0L1xdyvs6BXaDJrNVkyd lf3QXgSCwOBJ2SmS5ZXY7APoUpB9xNqwKAiJwt97iFV4UkSK+8pNFu6uGI+3vHiEYDSLhmXIfvgK ofyuD8glylTS8Moe1ygvhrSJNA1Mqam23AHRxSCG1zlYV0XYQe/3GtShGybctTKy0Jz5CZ80QhYi eHBGXnf6bE55v+vs+8mEO7R5jLV194XhalplK/Jtg1/ohaZ+URsinP1mHCHwos+ZfCz0CGw6VV6D s3fUv3IT4rAq9q+8QfcoHDShXv4WgEJwLYm62SCzkcbjYhPAP/fbl9nfgvoz4qUTzRkbifRnOAw8 FPES8re2FPdvzlqtR1QcnV6GhkiSirH4dizf34PHjGFPtB4wyhrs97nZvfmLqbwg3DVKIPZkoZhx 4VqjqOTGbp3N21l7rTQUeWaycO3TvE6jh4HTUV1U41vLEPz9ebJ/UTA6ml51NhB1190XjaqKdRnm 8G2k97e3a6V2GDmK+d/mZrTtwQKzOMFy9gp42Y0z/Q38pnQHVKDOny2TR3YxhbjKLEv3bxFG+gyC rcOmr3fSkpyyVm9sGnYrePaBFVndB/6EaVR9NU6jBd1nsnWJVCOoVRCnRFH8Ww+b4FLV//BH1cE5 dHndss4xYRyuXc+IvlDBEOZGTEJqgGYxH8eGTfY2Js54uoEOrhE+NNULsYbp3eUJb9mdB1VNtQt3 5YxTL0yE59xfXTVS84XFo5WTHCSYtd76ylwmNtPLhSuyslqXGt1VyOvnOZi9MfwA0i795v5rCWfp Jt/Sf3vUKx5c5T469E7tmGt7hvORNbc2fntDdISSR7vYJG7xN6ATSukOoVAQfSk61VaNii2etdTF CgI59tBs5f323ilqHxqYVOdiqRx4tVbuWbFkwfHJw+wmJ20N007Own/5ptPyt0NJ1/QJg6/WR1ft WF4u2WJ1z7S5pqPCkRnw0ikh3opTMHdmT9EaqFjwnc3MDt2j5pK74+H5dr6F/YBdjatjSEJUcgIr PVIwLbZn5teqoLI60b2tWmdvwKBmW+Q2URUXHzdXnoVQJP8SFS2+/n9TJJJBaW7o6uD4wVDk7IuX /S7tCFI+qvfOvgAvKbxthVCtzaD+3G9h1UaTJKlCbLUfqYqPnujsnqaK2wBFJxcO74fv+RtxiauN 2t1529XCIDBKn8ghsFeejUiNFtsYTG87xEwavkKAervYqBGnPGweZoSZqITLzv3YJO+MY/UK58/N mllnYwM0xd9jyyttKSfuOTgcEd7DBPIC7iVfVisuQqfBU8Xt3KWPe8u1yIwbdPo/068SXbfuPv31 N8wzRF//EUpP8n7HMooSNvVWJr61gS6JUW7mEOwzoajr7VNMRKcwRHVijSxEk9ItDksyuWc7iOs4 dOfbF1FOoWtY17zHFFbrocVLkSp+XrAZO1++QN+03Kqi8ZBgCSvio/BQpMLCCgD+tJMKdcBM7YMi fe8WXm8lxP6AAXPll/RY9JGDJCn2XN51UmX1mF+F0mfBJHo2kzw2GS230emW8l31dOa1zN8qvO3S Tb+lCJTCnpg3fenjkRPdZ4tGGEuCnfxMLWVUu4Zph3N+Kl0GEkKR72kH40XL7Ix7+u1QILU8mAYG WGma6/Wd6x8mQYqY9vz46n1KjCit+3DRmtHFd1HByX9DoBOVp4i9DvdFvaOHXZa8MhA6YBCfH1Z+ YiQN/0xl7HqW502WIuy0AnDLNvKgEaypHSkcZQBCk1J57JgCdlqajtLsEGa9Nqzj/IDtTDu4N3pb bXi+/j6TOCaGJy6wZ43uZnD/x5dorDr59t7s88dXrX3jUp2Pn3mLphQVCII7BL7fUFILBS7fB6/g uVBZ3sj08rSqzeL4/ncdxsBqyN/v2ztyRkQO10BFywr6vLWI3M4Q5OF3qhyQlipSkwvIcQ7Y7bH0 U0SD0ACcsBzq5kVXjPUZ3pKlSaTNupYTCKzvP1n6bl0v1DORFhjqCEIk2LcOOfs0iQy7aUC7Hb4F 73XhD85QmdvqYzPV4AudpbidYfzddDkJmTP7qJAwk+G2Q4KfaeWZXFL3TxMQxL2dcy+a0yiF/QvU k+Nv03aLztAxVokiFDoJAWnIEpnAFdoJ56BKKcX9XbB+60CdgF8qOpHoNsWlaciWTXpVej+iZssH D/tWLPpaT9ex/npnXCrYQzTxbXeoUbV8dX0/qpIS0DV8R/fHUAkgCk+MqYFL0aXg3Ty1NlMZ5Urp 4PWNNEJMTWvzgUdWtixjmSvl+vtXhrtL0iKA8oQvKOEBljp0wnirqvxzPQ0a26f4UrYvN15PRBNC xq4bmj40LVq8ozGfAg7IeB4k2VxqXDLB02ss4wGWJd3Pj5K8GSQ+z6rOuXS5ce6QaWxv039JqEf1 T+I/DHyXKetdMvzP6qFV0iI9qB8X2S92jrtHERWHqHsG0OVxsdq+AjOgMAXDpX7fPLmW3eG7XAIG NHUIimQLiowE+Ne40uc55JjS3A0lhLxtp76KHfJfAtlB+dMrBHX12s4QiYkC4gXyJZmgR2xlovFm +J0l5MGxiFcZMxbyjQX3KSPiTZxpid0ABzJ9byb2S43Qias6UmZLX48UvHGkP/rXNt3KQUYmdwKd t5LkJYeWiBnv1CW0qPU84WAxjuDkoGgTAQX8/ULp6toudrcdnGiAyteVFvB0mcGKjQtJsadbbqGl RU8CE4IevWi1Ji/j2nebBZxu2q6FZoSQ6frV8Y+dq3skfFYcyvKtN9WS7bWRJ1uUp9bgF5ZZs1ux wFFvTvknghgLD+Dtgl0KkvaNbUY3bZ9q0mBddJSSIMiJWFoyQQwPB74b6GUFzyi8+LTzETLWRjeF VeBxo+nXJUNpaUGKYviIt3MvIlhrfzml8J8DySmWMLj2fEhofodAazGN/QkSZkh56v1VvN3km01v N51VtTZkVUWBe8CKC8qCumDiNAowbRwlnx5TOuBSDcSL6F8H9FOLnfPNv4x3mhnitH6gmlfgWMYC FO23enMJ9otn1sd2Nebw//mB0riPoexjOXVLFm+cJWuSDD70hyBOLGc21cNRh1wPtbv8FKUeW9LO +bPqL3CEBqBPgXGNM79asfG+sV8HzVgofz5foeDVvW2hzb0viDfwIiPoPXBjgDSl8J343iOF5CWr EnwShqWAWp6h6WGbzp0TFqyQNgTKjcbh4HI0B3Wk5XxlHd8Vik+MFGKRqXCTgrwlK0CIBge0prWk k/qarMQXRUiX520nazHJW+y559U8xwa4qog8eN4Tg3XyycXb3XaTz4YohWbxfr410gVNOw1VMy5j //KN8lFKDSKLJs0mUol1DAjlv8BIcyZIdNWM4qnXxMBxmGPVoeD7J3iYV1arQ2Tc9ydZpFD6Yo5i ZQpOtFX9jLE0FRxiSAn7h+/1mhIN+O6pPqzaMBKnr/huBTZUcBLaZ28Kfa1/nAz0Dr8MrmINWKpG ely5a46QqTVtAwYY2eB7T0yE8y4Ojye/rTeVlFyV6dcm1P4YlPCpASQGtrGfIitigYDZDRsNx8Wg 6eUce3hRuoAZczgyowysdxLJEvi+u/GMjyMDfvDh+8MwvbRKQKVepAvRQW4FBg4aSGLkHYw6bGCR ihQZWNy6Vrsj5/zpP82dEnGUTrdpL9beZj0Dyx3CZPGM7Hf+oEkMBsAbaNJ3JFupTm2Doal447cZ XJt3iWq4HpcBVdSRicxcl5VYtkNs1rCX7uKhuqof6EEF+62EPzpYj5JidL6wcDrMmQ5cfuQ84+pC t+i85gBE3s+JqzJK7+SfhnPL5aw/W/qWgSLpzojEfAxsTvzVJWadPzoitE+IMh3a4M6nFy0ZNGg3 E9vQoN5dzZv9HzHe4evSkDFqucl1YhZUYzUSrAxEvJtYpQvH+wl1jP/xdpF2irc+n9tOxhjtBTi1 VkNnfe37KOBQwGnHgPcBxYfmhJViYaQcCetRMSrKrpB87L9UkapiMNVYUZ9y3aP0cd/I0JtcQkW9 UVB77FvuBT41qlelazfBX3CBDeiFP/aLfyukgSmZ6CBFzfK6LPmRDp0lWtyAEKEtlh9FplS66dYB yjYv+BWfI3NB+aIeJFYmtqNJ2ZVjPbfsLtM81qplQZHLd9nnLyPkMbrPp9yOVXR9IiICCuqIT9rb ImrSRtO4l7V+CF1MIhmH9VG4FNBH/FK98NiWh7RUQxLlnohMelt3s8jSq3HNeawRXCyW5LTVhrVe vUxLerKTDUwAcEVe+YgTINKmSiU31fvh1MZKI/4bdOdcs2wpEIR7V/I37cowhmAQOicqt7Iv4PbF Aq2+1YRxNcS4mK45fDCg0jfrNyObdI8xUh36kbMehQ14jZ8W8vXOTJLTyCNt3NeGO8q1WSXUQRvZ 5kw6n0OoTkZICDDn8xYc6OS8YNvTN15jV7E5Ngcpb+grAAqk87mUH1Lplpt7jxz8sjnvQQuiqQD/ aHlV2V0LnefjFpLgdp8Z5KBgG/U6cHhFj2S9zmoPLfk+6aga0aKzjz+JNcqABtDi44KT0vRJ122e ZgJT1pC7oBCUtic/WwCnHf1CqzwIbBt6bZjjzPDK2q7Ed5lcaj3yvA2KGCXnR+abxGFT7PmgNH+F U6DJ3S6ySajaRwMxG+l4WpHj3V2LKgTMN47NFk+6fcUz+6uQT36YQVjTFyDCX0kDmT5J74yTIF5i MnXoUgYw86YfgNSMzLPo6Foru0d5ZOtUKdhZyxpWfxmG47eWbhjXrLchRXEf3x2bIDOeurgENL5U 33qWE0VGYxoQAWkQhDncqt3ZLrwuPHPNhOpZS6huzTtJIr8GwhMCULofLo+RmebdgNRPTQXMLSU9 GEELihMAwrXX1ptUGB/63oJHhDQ6Qa6RtJFrFEftTFqxGSCuXI36ff/7rKaY7lBC++6Vw8GhT447 +IKu6QG8cSsDNlXT0/dyFHIncBXlByLfl0Cn+MGwDNRORpaU+Imi5TYq7Kas+gzJPx96siMX7nP5 yiaaCGJMP9Z0GJhrVrMxwrKTn7ghYL/5mYjZK498brKina6kCjVdk4zCeb9g46DT25JBfh7fMKcx RpNkgnb0nA1IHxIqXLwxmlrb1zhoWG/CR2/liwNSbbOF28KT5qSRSHi+pHr/ND6J7PpphEf1JVxF qVTbIzLCQC+E5Im4nMF2+eGTwATa/hIuOEU0pcHOadxb0CH4N6ltI/Xz3NdnK+vVGP3TYb6WrTSy +w6V5FSRlEvWddLM7UpSZyhGkfv3dMjWto2+Gtf3YF5ylHyyblqLyNab12pFqtiOEnThM1NP3dGo +FkRWgQTfrXzOA9FtlUby4BCnPfsSQZ54KvkGa8rt3LGdVUxjCM+l0R+767VmKc1MW8Te0e8jJ9A pLfP14XqdfcgBIGoGfQEYBqzbYW5cAyp/PHjqnyfjYwCx0YIwKGra33M8X/7++mAD2YhYPQO3RIt JNXZvZgit1k7VRfkLC8nXkal3IDe55EXf6rz8tNeR9xOK/scKlZ2usFC38C66hcuS8spSasAt2Fz WWytPr3DGRYjOr5rACTM/FXyGs2S/zlMN/O74GrhQ0kIp6CI3RjWQu0kVeotvezdmzNZPy2jHe5/ QMQDjN5y/cVZYrdkKtQhceZoC3j89D1NEpx9M/POAkk8dLBLlxxtbeTDyLM2Ol7X4KUIOB6tNX4w kZ2WjOiv9IkwDqliAWgXY4GE/zihvu6rRTHnPoVmrsKriWASzZ7S5k7KWaA9nQj5wtgZ6RFQGLPH 21BI70R9IvxkC+ArDaABvH1H7mcXc66xDMkhcLWw5nzuImZ75fElRR4vknU68rbjpC7hF+xrZIZP khp3SVxAvYZLcXXtS81nq5jTG/O3xeDLMOgusNCdtpR4v/6MP0Kc5WyrDTvG/6ijEeTuIliZVWZM +kggSewWIvNK7f0C4Zjl/A2pIQSu8IVvfP2pgQp4zRY6Xd8Xj1dtR82226aMWZIIGPfs3hCPrOnd sw5GhK25AJqkS/ussmDAoBV0/TSgFVL83/xXYdi0yn9GnFCB2uc9prVO9yFFtfbjl8InNRRXba7O OqawImSdL6gcApzs/XAVrEy7wdO1nT0d0fqTgYOrNOuxaj228HFg5jlCN2SG3O2hxXr5TRDRGinO kn9H+5anoTzDT+mB48ZWXnt5Mu+3/19QqeIL2uF45KwB42r7xMLVlAxIwPPJGMi69tdrscPk3GEj PjOjhcvGgvMO/Z5AnVjKpfJAN3S4456WdZJECfFSZopagMxDtTJwwjsNCprhm9IDfY+HJyOU9S8v 9H3ymZ5h0u5VuIuyUxpfeah27mFsZWgES2i4976axvQTDyD4a+QUgVkEK1CN9XkAWWDsyIFv7LEQ pWKS1HzYlWiyajFv6ZjiPLPPDhGtWS/24NHOAdmJVbiqWw1fr3/f2iBziIU9+U0xq06j/UIHg4ut KkPjrdhrMS/cDkO2zCtxAEkV/LfXGeQJC6sDevEYYZJ+mzTmqn88xPfBgoTOp+2+lIzEvIGWG7YO YPNzOxWZt8NuPp/J9AHY7h//VVXxFjl09VaOTXj2NP1qX8Fpews/jzufAvVczJiYSts18M3ZdkBS lFXss51t7wtCbjNDA8ckHErfspZX0nR1Unea4z4GNhl28ULIQETLjP+VTr2bF7w98pIu5t2ScOt0 g4Kfxq9crJWUUZHIxUP4iqUOgsh5ycK8w67+uuumsjPqtqKvI2W6z+vkW3Dqsy/cMUUygUTWfHmq YJJ9fPwtMte0tZKPdIQvOryNPSD8xDBPkD33c8+M8J+QMGXEbM1oTTu8U+coEyEPf/7/vPX1tPfa iTpJjbppD9OBCFBz7wOa5n100BQxqVU8LGjXslKqzGp37VZ8C3FYBDM+E0IpBjHVUs+bSIdYhu93 +VnfaiknFNJizimymtjrOjePDbxusRDMds5zW4TmIcr0cwd8B/5iLhfP5MgCnhZWSV37U7rqLuqC dS9PAm2fUO8FTXNdDtmgHm7kCeAjh7qpPSnydbXEXJUWcHBS5SpV//5Zu0THJmhvCL0yD8AAbDFd rwMgMbtznerxfrmcmyb3Bj2VnLRd3ztMNMkSaoGtEAK1KxGicwr5VhayXwyipg+pCZ2J1Kp6eFVI NJeV+5Gw2piV8FSAjY719QdVLTymZyd/0TvoOMRo9BQq4aSUd/61pFGQb20EOhBtz9GfXWbG7uf2 GZjJLRbJ+85IouxRX2ZllR/QL3R8FXQJdAR95llOYnRusJF72EDM88bZ9Tthd5K0o1JZlDOwsIG1 YaRA6AsSX4ZmuyieE4mxN7AmuJ5J1vMpwY+FgN315upXWql7zO3wNlVtpzPO0ExGZ5MhLVSVfZZX iCCn4ChiCmCJzwWw7YagJiJXk/ekzbKtU3p8N6lqOYdrwdGhBRTZonJMquzXGPIyfpqsIpm5DWDy QzhVFuKt1WgpfK05ZjwVell2+hTLr4P0KC+im1zpKi5G3d4IfptMUPf0PQHjE00C2HFLsjaJdBp7 IYdKx68QOGbu9gL4T79163U7LCAmNPXzdMguNfk4hLf6c2BnASjDu1Coj4OXaPUXvzkgdw3kHvxZ EYz0YtctNNMCO13a46z13Nf3qFhhpEuJnxigKPW389bFHU0QE/J6Aze9jf1MFsNBh2K7uhc5WnO/ FjvEsKxzEM+qfSk76gmzBl2WQiHgIsJMGWs3a1mg8nWbjs15oH+U/pPH+zr65s+QFeB3cCHPRcpL g/GjfLpf3Gbq0lDaGbb/PWz6HK3RTU9GGBc2pEO6QWFazAIDwS0JLbY7f7Ye6fM8fZ5WkPW+7V7k +/1j++ZVHMtySoGkQjJVggnAEx/Ndmhu1UDLswOOKLegrUJLHki1I84dZAS02izX29xQUGWyhVQH tS8iE8XotjJnkLencnFCQnutoeCvrBbkPUjniEbniNRHXYPmM3XHoatNKWTHMWCNBQkw3gAVHndf EaimueDwTOLtCqwLvvaH6EIkKn+1c4cQO5yH2WJ4BQITzysy1Cv5JjYq/eNWgN2gb96fviSOBnAY 7jok70CH0n3hTRrpsnTqC7UpTFXcfDdWE1Wr9Q7/AWGic4t1FgWHKbbNR1pdVxjuLDdadDtW9VRp MhJox/m224DxoJdtW9V/xXNajC3ZQAu3MP8pzAtos62t/ybjg08XfQBt6i2Jx1WGamMh3rJw73P9 wNOD56WGDxYh2kmlNNtusE1OpBdvUJkWKLCHN/ksg3ynpbULpwJPCv+SdN9s9lO0wljKHZzUAY3L BDOu1rjM0kci6os4ImS9m3ALuj5AS3q/IAIYoaPsUd2/jawxolIRfJvtdvuLFrabwpBhUlSjcrt+ YqKPA9jHOhX2vGME6e6+rzmqK+MU+X663XwFPnwIPr7hKNbuYEEtfe8UOeduNIUEcHSUI2iUeikG MMKEVYE9mBDzHSiPcq9fCx6ECYed2+7Y7cymOgYYb3LeaFXfFM+n0SumiYpkukopxbB/gSGr16L9 K+6FRvqsnujr2SnaPKs1Qohd8kS+MWKMrrGHEW/Bn0xhS8GWgf43NhoxicEI+fnyQvYMO0oUiaI9 cXX+oal06gsAzlEmq4/uMB0s96wDNrntopJe/Fi3R4BU9155sED4Jq8Cey3g3sNdHTawU4D+D/GU VSoaZLrs3hBylNWmzvcCvCP8yvn3PVWz6goeS8+ciPqEYZEJfJ8ldbijwun/HTBjvW0Fg5t204SS 9OWlmUk+mvIDzRp1c3ZFYuM33DMxQZmzj4dO4I6cZIub+gb4jj0L7hANPJsqKJ8Q7I5Elhm7jJR5 W6Xm4CHomIlmqjAkPmdV99Mdefm9NKOugMfOVzUwZkARGohUyD2b3dpMajzgtd5dkRGg3YbxdjjR nu/Uj9jSPtqf5MXBVCGqOX2sf5PLBNE5leKyu3opcVaMPIFqUh9MaYVxFNSVXUv6/tdWbV2P5Q0S Cw31PL+Dz3hxIQEwLw5w36HFLTmDEjrrvBUPdiyttoHRvO2GLu5mCS1bpjdGOedhvKoG5wwpIlLe s/u9dIiVp3yEJhkWr9Sy/+kDZkKFYo9xdvOlKojgHIO5ebDd5K4Xjm0+xbrdU74dPDXIm8993BVV 2XISPLCZMf/uu9Ei5EnMrrN9+UuTgbChKcahyulgz4XZxgD2+7MGOakLGI2ZPP7JCoy07Mmbf89m v2qBF0nQ3j32VrzqUo3lsfDBDwKQnCzYkhmyc5RWZ0aVCbkMj5XmzzXDl23GuMOXFYVIUXk+qPje 4gSoqt08f1rLeNgaouEukCYYJEJwb5zzAPDszMxiIuyZrsvyzz355+D1x4Qk8VJfyETU1faH3HpN Zo+369y+lvwbC60/97N0QcwsO1IW76oFPIY1eBQZ+nFsZTe1RfHxBqiKj9ZhPyLFkfKWhhVTYM/5 od1tNEkX39HyRfqImvgrK27jHBseVFKPCiNHFpySRyySgnu8VRIX8KRlauCgEtLT86RYUgAUZl5Z EH6ZXSLUGVXmoPyc5ANSVl3L16T/LABHMpx5R8kExwQQ8zCW5Oxu310VhNR9yejGOF+EDeQz4Irv d4wGXZ+LsjDk/EIRTPjNx7V7yS4TT+AMAuHlTvziu31Qs10ybBM+GgUxZw6/aY8oHB/MJqPAA6oV ZE5SdApzIS2aBsTBjT2qtZZuiCUmSatacAWS9Fb5OGf1cLu/a7WtsGKhA9FcWxQT1PkfAlX8kR1M SMqpk0EEzVg7EHpZoIGjbM3fCXebSI8ReltZgn9akHRd0TgPiKitO6YVR0aFuh/HyAN+d7+2OrZq M4qq3XoCWAifAnF7nc4oaxhpVx+05EnXQD23BoyiYTEe7bpMowdXzthERxSyJ2T6+HeaWnFh3ScJ cSJNfzdVMtpn1m9gnr+HoBXA4G/dywPSYW7K374nvXX8rdlP+LqEGt/HA2jiTIoMRA9QeAjsM9r5 ZnnU3xlPyy7zutzTV/w0pBOPWAoqdZdkDFx+6iDDWFWBrkawGWGo8M9shUoObPMbrfQFHxZ/jTHm n8M9y5VnkcBc9sLcotmAMJDfP3hyOFPyeQLBXAdp8w0xhU57trXxpOqdiOI3vXMe3yorO7EG1sTA zxnobr2T1PZnyJstTA1ZItLd5lMDRKKRuVpZQILAIkNAop8DBTWNCTtxTbamOQCh42hesMxUaYXL hAFlznYkPxzmAJPKM3m7TkfAE5hb20FPqzuiPiGtHMxQZaQIxvb7T/Mo8ClZ+H+gxO80XP17YNJc P8HZ09m8uMwYi+OiUvYOKPXXR2HRo0PlgCMNE21vwbIgrHcjH9ZNFsnFXLVEuqL5eY6W0Rk5+Zyf 4FEGB4agl/yeSGT7l86ctLcQo7fywDeTxluD3fCvTWWbAooAVa+xOYWqL1rCU6hDHaNG967RDJSb j+Eyg9vqbEo9ObViANJS8GibkCRG8MlfT4faVh9VjpQE4uKMYOzEJBwsNk2wkvGV6riyRcgqTy2A IZAMLQsBmqtBpd9VBHn5y8VAul4deFHjjqebFcujX5bGOQsViLDPPYrhB/ceB2zlM9akj3IVhfHB N6BYDCTaMZNz7j6/BptPJZArhHk5OltqakFOiM+ohiparXvBCrlIEvr91wTPOXFeOxxgvEpJ1rJD FH008LMd7X3+GvJpNN9D2qaoco98NSsijJxWwhAheF0NiWTPGWwCwHNQdJRVU44X35JpgFSn8f6Q Sn8WM9lr+YZh2p/dLV3QvGJfTr3Wg21rb/1OI5iOJgP8Ys1iTRg1x7/zbXOY9w/wSL66itzEGCkt w/Swvzxm9WdjDZrjC/QSJU5AyW/PWbJ6mSCE2bMEgV7Zs5buAtMDS4U1Bfe3cgfxdS/a3G260YBS mm8G17gaBNz40pzOAt1TWneSTiLUeqB3P4Kpy9q3hwprPjChOw7Nj6YcAIV91pZ2m0xTToMHrW7Y jFHh2uKX5/V08LsyHRJiaU/m342tAgKw1mELJNvxZvUBYylh1jg28GSP5KpF29otrkkntMnU9w8F Ibjl15QZ9Yg083IWphj1Ib9SMU5Hutgok5yWSUMphtFX1/Dl1Vg/CZcwZrXl5tKFK9JFQqn3cXh4 0kqI4ls8I6ibV5C0m4QkeCZmlTifw2+lbeCZPi4Y4ZEL4SursqqdUaF7aDBDc5nIdl3z4xXuI13X qRq4u25mW+zFRIDeaEsr7pwsCZyP7oKzjSmsMh9nZw3iri2np6X+LKX9MXx81+8QIWvqC3PV97un UlxJFrOhIIff+JsDakOVQmAVQBlQ0HKlY1Ye/DPAW7pWU5KkzU91zOMzyXXJxDvNmrPTWMSk0wrj rjENxGCPYtIalZZdXjgmn/iSKzJtts4tVYLZ1QUS2OzI0VtpBsgBzGqPQiHKipyBzMoksQ+Wuxjx aQMXZMM3bRqgCm80gc81kMnszlMgTJJ17cgJu7krVKJdP7nviN971iIY48ugaIuwdgc4uczohs0m N2cuzTrgaHE9nGg5ZtczAAX6x9xJeqwnkBAR1x+J7kyWIqWWlQiez5YY5M1NwpfkY/7YsUBCM4L+ 6+FhRNrtdxW8j6fkpopUhO53Jxvlaf07aYQnJjRzZADaqYmyQMN2xxSV3GSl168Z8ZkmlUY7PvWZ Ysy3JMf2r7v99DICWMdMqqLcyYhTOIGlBknGrmQU3hRADK8q8gxhdz+q3BS7rx+vspc8R/EaQnUc yzGW8oUauWjdqAYn3cY6R1oMHIEbQS9ZNNnh/02KCvo4UWXHJ54NUKt5AxnHJ7Tj8mUZkAYWHkGk P9elurTzb3+4nHrCAwtpzsCIH4nZbiMqpKrxfQraw2rbo5qiqRvJ4pLNLz3zyVSJJsLInQY1z1o4 c3b+uTTlmEfDOJvCqamEuQ746TagRv50/SHsmG0vgvf5Fu6cDabs/rSSf89oJnYkp8PtjZpm6qk3 mnUZONtq0dC9n5e/4qxs1oyLWyY0VDiq9G6LQJwhWnbwwSN2jEgdm3utuEyO0zacCoeG9OFtVR77 qxIhzmimUcYv8AZg02fM/yFMZSNOY6bUTvjq6/B8QZ+Dkk6ppX0PGqes94KRvFs+tlJZ+W3+SFVD 25U1H4WxdNb+RWUTwAJjISP1Cjnxh+rCGUMSTyN3gNp/cmBf8g0RWyVi0y1soBd87FF/NmNInarK 4G7vbGMkeA9kXan/PHChabkj8Wr6FtOyFld2W7ollVExlm1Z9OowGxCC7/uA5422ah3sHFrc0Whi WdFNquTw+VlVPl8Bh60Tqx/Nuxyoa4Zz+rZt3CKe94R7bTGycPDSS2DgyTbbEqmm9lKAK3oIwpr8 Aj4buEiP2C0VTKEM/7lrUBEZdi3EdNA/wFwl4r/q0ucpD/P2OaFZ5Sf6gtTMJB8j/tNtlnfUevU+ 8DM8AX+ACwU54g7Zs8M1/DiE0qbgosOHlj8m2nPUTKl+m3Oxlg6pDbJAYNrCTkgeMp4HXsm3ezNE lwV+unXgHHkntHzgBPSXkSot6yGw8+JAU1hrnnqSUDtJGFYzeYgI52BvLVAwcmq5F9uJ6OmpQHYQ 2oHi23W7aTNmXIRaSj8FQ3mqsegsXCNH5cSriVOx7x1+EskrfIDRwBtWD2h6w4R5kMdTfraLj8cZ PrEmT/Z6mh9T0e6VSFzSHxe6ugmN3qSfykAIdupmlweAv9ucqwb24sdZuW+sZz6iBye9anCAUVq5 /hpewY8iy4BfzhNhPL5vNLhalIvvlvwnqLVKnpbcMXtrV3Q7cz0heUlwsBzhF8dUd475tboiusvp t9dZ9dSo7RK+fCp/ZFrcjxa2T/e4k12JfUO6k297vlBjibbRN/l0X4JSuqjNO8hgI97LZwVLlfmm SZ0AWEAwqhVsb+qL470RqfBstZwmoRkrY1LGTh85WFdTxt9wKiunG9CuIfF/I2cgAwsU9NnTXryu ZjE7gxl1QmCG1ov9SqxeQNh/DpUwSd9eUoNu0pz9UL5Ubd3Zo3G2SVrIw2a/KSLYUyQynNRRuugK 19wFDm5XNz33NKueYlJe17j8vu8/iJ2eKU3QDNV0cn90a0gQ+eKVf3/IPDehlxUe5jgojdgqNC/2 mjRj+MEq6k+Ypfv+065jHwfRNFOdULGeDCQWxgiCdgHDMDMkf2p8wzDtt6D3zPAhALXtsC/BqRx1 kqak8oPd1I476cOkYpYUyLxupcx7gWpujBqhsoFoLNdXC9i4D4oSAD5ErMb/JfTLWxpUcIuo9eaw IpnHDI2wMlXGoautKT6UPFpQW3CZFjTiOAnVsXHmQITd+HRQ77MTkIxx+m69oVo/P60g7FgHjb7b twqgU6IX7hrd/eBPQoyOn23SMQ8Jai/T4pzMe853rXGrcSgC69z9bA4yj1QsQfPDBvlHdlcBZpCC q/Xi2EezpQabdKyarZMidLa6SmKbZXlOYauvjyMkJSd4eUrcqS7rQe7H8Qgy150ogf4kqk1CLqBB iib09PuY9G7u+sxCJ1UVlji2DnIceBtEIByEBystd6xUEbUYXuzVAM0axz9Ra9usOVVgiXhznD/T +rc6E11z/Li6ciUbcqvQVAYFMKQ7gvSrAQ81rYRiHyqxhrzBaMmRgUmM38TSs/emIa3Edg+HEKSD r2aCNylgbRynxHclRNiEXxU/3z16tWcukYcJScoz7SuffTdQZnwEw3MHOZfz2+1D4Rt1cszvgYW2 jDt9iaPBniA7y0h9v1+AjQC8mT4aPxI4XMmHsOQeM8ky2WBwzBUgTonTslnBDlkJ0+9lJRfFsRKu j7A/o2HlgNCvBZ9KiFIS6eTIJopeXmKqS8VBN0k/U4XgAVCXhVdsVpaMEd/xYGoBuW/6VWzq6TMO qoxDtrNqUmUv2fubvJ4HOnYtq2hLPIzAeenil7VGi8umSPvvkytUOeGCtr+SL9/GATN5SDJQaTV3 7wSCZki68UAjwQsIrmivmMXvH1X5X/MgVWs2Owec/L+56gEcCyKC8up8PbZAs2UOX10IlaV6rDoa YXGhbRkM08Rp7m9Eb0uHXlVa6A1efAvudMzv1NM9NOwvtKxjHqcmu+YylbiY68XXLc8T1VeCmslv mTsve6eVlC29kNK63eBMNderRSxkTHO22OFG540zfiRCNMPBpU52IhraQolU8/NlgOb0ZGorvu7B YeYbwR7/yE0z1JzjNbut5z3QCh/VU6pxJT4+H9a7VVqz5QqzrAOMj1advUCtxKLg8XDKTL4bgr96 rSKgufaxVrUa96ND9gLagI3YelkiklAU2C751cM1s3Q6sthKmsoaPtv+oiUrJFOGBKO9iAWoP2/+ ibuP7nkw0VsRaKLEv5RVRS/1p1wKSHeZ/5ZLlNvwKVkre8gKv5zlCxGBOcyAIw7SJfeyuuSxSIo7 OTI0PJwLuZkU0mZWIOxHulZ459HtVB39TUOGbpPhToFqgqGthTxBq6yn0KcVdJyk5fX3pSE84AAL UYCVl0QsGyH2W/1ooG4KuEak3BYJ/KPVqzwakiI7TSNDeE+nyQy+35zFbvRgyroKsKRuh0ulTaL6 XHyPZ7nE51JldNqquD1M4BWsbWHqWAdFqvq4z3NoPrZBpXbcbjLPCPkPu1HsSSsDuLs/tDWS0sg6 Ltv75GqaGl5HyPQ8SzV+HQv4IwjO28j5xRImzjkGi8tkptuGvVbWWp479smcKMtjADh9B/85xxwy bHozt5anK3euICWP76fVnUV06f02HF1ILTQSgnjOfsyfrpc+zlMGl+M2cZecsuPeGQVttMIomYhW z2SljhBuJXOGGVfFu0qlx2zscdlFxLoGRHc0GRR6jh02C2VJR4rz8vFC570pN5O23D/UcMAu0V1Z rXghg3vFF6JlA7YWHaofb8vRH70yuztDTya1Y2tIAkshaVZxgzXnqdsZ5YH+2DJ+XDVD+0xQ4UA9 ysOSAjfUhxk4Edy+DRO9rCQaCqGebJKiz16i2cwSvkqflKB1Ke2QVlBDOFUldXY49LPN+nz+wB5l A4XQCF8P81NANakg3Obuk1+XlHBNEpqPLfJZaFy0qYv0N2NQ75hiPvzxPCLN+doAFwp4qSDaKBQs VHZvFzYDg1QCymZZdR/2Xcf+Fi5tbc4/XdC9qVmYDoIypTPSlFCFOQrlW/v6m98/Yz6NUDRtkZrP ry/+qT9mg6KxIRB/oGvFQzmUe6SqOrSVV4l2jO8fz4ohS1AdssW2q/EM2e5fO7/yK8sr23CNoELb N/sqcfl+hKbmpS1DLC1u/u54aY/8zn5y0a1Y0tIyfpXKWGgHBL/6cvXwbI3chq2IFYm5aYz17FDj QjP9uA7aGxU6cQlqEEZjcsctbBzP8Nhpcqe6yHHo6E3eZES3M24feHNM9QMDVDNHpCBar3ZUFJjL Hfszj6Bc1GbIwA6o6HZh5V3egiK3690Vfml6SaySkj9ZXZ+9Ja028ToCO5nWiPds7u+nb7fDrQXD WMHPMVCm1LKm8t/GE4hgO+/vJ3Ox152WdmLa02Cwu6Nh5Y8C6feTHbKCf+TO/Thu8FTP7CANHjJX r+tyI4xxX0l6kuhBrCDCDwyHg1/asJEOGgczEuAxMtL59oejQPnRQMOKAIYcgiDG6FPEdunxTUMO LIquQCmZC5WsrnprUarjqIVI9neyCydB4cKXFiYd5JBh5cONPCBwZoUrzWEq/qGahCoBuRmRekhh g/sDt3b88VA+rup3Lzya8QGkupfXSo8tChmSPOT+dSqbtAJxiqhbf53ZlyZXPXlWWKdHVriDIe1w BHIVuuOksMPCaSGozLx2I/VhxDUFvtIe2PJd22gN+GVHGmSHuwOX82KrPy7gyirqRO1fzhvdGk10 aJJCFUDLm377+0BjhIDR8CO52tWZdbLPDrLWL+tW9FN0MTG1gcx2rxjy4hIe83s4CqIgjpsehUeC LkAqdHKU+BtqLE4nW1a3MhSi/0bpzIHm28l4KBONpZOHZ+K2Rl17mebY9XL7KecixyzO3nETY2Ae d6YxjzlzqZ28zVebO7X+Usr5rbL8NC1eEwuaUMTAgivnnPNW/TaGOxsRBos5bDijZKXZK1nFlOTH J3EuDdzo0KOPsQrJ/kS1rUOoq5/frehhdU4pwHIlS7QBDtV7NEOH+6smv41c4avLbMiolt4XJq5Q Ues2S/VvNudftfVTId+sWcpHuUm71fD6QMavPKfPK7MqxA8H/oZzjmmeu/cJbUGDT9VEsguuIsya DMSqIxGm/nRqcITkyoZvyeF9x6QFEnKnYq8L9yWv6RlizLWGUOmZyWwK2++3crNAsBW1l1Ar++MH NbhG3OtipOCymON4Yx673hNzbTieV5WwSPyJU7WF/KR9fe/axkjwMjKapPbS76N9qQFYdKfs3yAd oYOdHwQSQWlIvTrAAAQaeQyELn+Me3/q62b/z1CuvQhGs6ws43RFGvTWhDzuED0AAqIwW4LtNOQh laGuR0wpv+xNNxfCWbD6HZw1/I4poNPzEFkOd1jOixuxfNIx8CET4MeQvYVTA24Do3v7oZ+VDnXM 9SPPJg/9mqbT1D8LfwjxJXNo62Z+ctdVwfRLlwKVZIMkYHJplR6Z0MzvlneAN3XrhhFNsaXmX91E y6Ja4CdVKWGUWgXCB+Gd3tPnJD4BZSheZJ4wEVMPay+JDk7K1e3Wng4C0WCFe2wTKESSEb/rQr06 dnXohx+vEAnFcNGi1YDESVtmCLvMMk2Epl7nQ0j4px+QTknDnudeZAjFuNrVm5YRC5tWYhUBKSCW c+enbcaizCRP4X/LuBtAemTku6ZX9iFYUpZK5e5ClkfSxs/7ATNb0pJqc/qPTzK6znAgzxqSO58b YvSNJPwlWZ+upCkWyxZimwV6EhUcqiBpNEG01QtDUdM0UbP4YWVgmftf7g/1ClyKmvA7dWsckyQF LCr+4kfPhJFOWGzNxyFD5AuHk/5z3RZM0fnPPk8uunLCorfZcJZ5AEKxXqlwBnIipIJBrxxLpIp1 ULQS1MIeawVictUewgtd4nEHIAhi1IErjZ1/adC2Xavxe3qNe7YIFOfHjdUWdX2bMZ+PTGjBuf4B ARWN6pZU/UA3hN99U+Rv3UmF/bDLFz+5OVtAo39qfOwemS5HtykMlXt/YAQbrfIFoDhaDLegFHfQ nVQGbwMOA01XN5Dy3tLDwXZA3088+/2z/GHdj0SikZCISyq+cbIbiPNS4ZE1nt3QkZIL8eHpkGWJ I4Jzh642X6weVvO6ijcTXAkzqY9il4hT/Hfj47ZBNmlBhXKfeurGdD/DzxZCME+fAABAuFYgSS0i hkGWy+sWZ8DBtS9imr1TBG5xxz9QVLIMh/QTmKAmDrmW/hqV30dBufwNWr6YHLr9XrmFkCGtCs+R 5PYXU5LZewDv84/BAL3yAaXtA19Lx9y8BVZ2r4+uuV6J2niIYaPZ8nj46/He3WPyayu2VCrVIg5m GGw3E0DSqAOWDFg5tf/VYdRpVpQcrIq6winRKdZi7RKY3YFbXhK6JYsr2uURZimRTel79y0OhCRC KUjQYxdy9hAaHX08pMUqMoTYaaHVuQNpou1jQsp+q7hKwxSWncfePTDqcoAEk5h7qinAgJqnkl60 djc4v0mAgf0hhxDtokeySbBORtdl8CSLd7CRA6hp83KmSIgyvCvPDeA1Y4+PLthIoev+fT9p7MC7 pud6c//qk6kYQPTKdxiozbxy9QyrohXGTar5gjp7Ao1Qf6IbLEwPUA+pCwKy1i4F3vaCAXjzFLFb gGEUCIP5mK2HWOygQhHm/AJa6zDigUgvpK+1CiSjZoqnKGIqawCthuVLqf6i64f5SQ0LUoV3HIp0 fwvwWoBHXSsgz4Xg7xXV6XU/7usuQwqPgb2U5ca4thM5wgOHmxbT9AySXFTccZyEzquUgmpVOqIZ zkrtgKaR8+fstM+jAEi3Q3yd3JBhrWS13U62GT7CRmsTQVCgmqd6IkzW1XycCNbwM650Q28TGcH/ jjj/n9aC5OVnLtWuz35UWdKiDN/MECQmxcZ+CrYsU6uHk1wqindf4swYOMBLrbmM/ctgWFC1TORn OGgkiEvXRXV1KMVF4rjijh2x0+BvaRsI5Lwad92BVP8Id9M/pkNX7csvSDx8OSA03kaPIw1/hjrV 3De/5busR1mCoyBGIVCnMR9owlxeAoMoLtjTBdeW29Sbf65UmmNaCFTFkQyCcOHG4Sp7zvRJeZQw rAsWX6at/gfR+ZJFAGptdthCJPLiE6ojxuPtuVnoRcB5Ptd5Mlncbei6osOOhY8cDsGRa1jnH1tM +FlkTPfwBJQ8x9Cr5iIrMlX6qLfbDHSfyCd+OcNUnNMAXry97uAAIrYiYqJJXylhh062d2qeLvkL /5YsVDWozDi0WA4d7ORqBan2cItFzlYrTUVDYlZGOKuZ66lbrwbSdCntArjeO70YLaSs6JbOPazv 9bf+GQwjz+V3cGe9NO/Lzk/250np8F1knV3TMjfuqSamdC/8A3dAV6x7wx63+udbRdidl/GI4XQg +VADVKXf6XcWQRO/zebKizh1XJMEBD/rzdXMj0LPDI+oZHZz4ucY+QATdjYfr3c35qX6OktJ2Y5H lZ7RUzCgo2AQFtPhXGFpIuJm+p7bmMvA+aJufYmBoYjhC3onUn7jlmxuzlzzEaoODjVl6X2QvykM c6D2qk/9DKKXuyMQ+XMVx/OTlzZqZqAmMHHohQldgqV1EFKvlATx07oJjqDt/x/phBxVEe/ZH1DY bhEwQxZgOlfljfPXtAFxfeXqdyy1Ksm/afz69nnBuictB2JJQBm+m42bdHs/DcixvIGeuPFKhEwn mRwJitcuOXjbpM6AVqXPKPuY5ZTGHC6cpgDe0v4LosFLbXwQIGhCLZth4JIkkPw9Dnm9R9INFQeX E6ZwORG90l3lGX/+LZuI2BISGdny2Xaq3RbttWHxA7lxDrRrjQILYWgLCI6tuNo4XDnx5R47nB0C y2bta+ct7whiZ41q0jji4qWa7BmcFeq5ekfA7pEy+KtZ6OI3clemb1qTg2QDY+5gQxJVPPwNXk2Z 0twz9ZQZusHC/wJeJCnAVGt9oMyM8oGKehizYJcGcKQF6pX9vg7ovhpzpnNd6TD5HgZyKHyGwj6T 4/NVIPd1zkFgioxdVr0NLLQOJRVIwP3r4hCwu8Bk6TINcVE+sVSqafJ7cvegHemd8HxmBi24jC22 fwEMbixMaM+2J3B3qkwWnGxfJIL8KsSiUNQkj9OjHyoOq49wnsSJ6+d+7KPNRmkIfZAB0KQW7lBb 5IwO80azsnv4tIp41dK07p3ZEaRRy4eiGNjrqa6jL20JqfyFLkI8jsdl+e39nRK/hpIVmUUPNfRZ fTSTKjajJ5++avcnwd0empo7b92KJIToKrgU5wEtkfEzLwRuXMm2ce3Of8fbYmJh/AW3JuxUhlzn e2wcVX3UpSA2Nq8VNZq6UGo2YkpznVq7wpKC05AQdjLyfimj4cCAdx+rfjn8j5ECNMmEvIXhBB03 v5F7nKeRvfx0vcwivWcP0XzFlTEeMdKCPs+dP35SOx0Zs2Hz8gay7KhcFHVkHNJUblzDGb1tzqPS TQ+1T/HwRRNnW6Ja2s+Ztj/+7m8xCoyjQB3WsXowwT228CAz8ksOU54Zev7gB+yOIq63XteInEVH JJ6wow7MOj4OpesNkCmc0rqfzvQHPL3Jc+EpmOab/3EcoKdlErKoDEXPqzpUD1kg0u8/pqkRgBFz NUuK9WPAvaSQxVXG8RcZGBxS3N3BYELs0Q17aoQpbxt1WcpYuq4LIcTImJcrcVDhoCjbvUEQLCDh kISkXg+jxqq9VB0RRAkaYVKjj3YiZqfYV07SBIy24SaZg64TsI08Zd9AA7ebpRXENiOnSFdyf/6Y oSMffsoPRDe5K0XBepBm+n2xtLq3QKqHkcgepZkkw2WpR4iBv6g+TE6CQxQOEZw4sDx5YS+epFJr BMr9D5ODXEQYwWgvrx8Kye0ViWTmk8F5udMonuLxIwaxatqIzzDnSQAIKD503LnbeOdsxPTbJHbM QDdH+i1k5X1/C8kZvu1kQeASi7HcN65pcaqXSM2aiOZ4AJAVJyZclz4OKbZ93WkHyjvur+pkg4Ie ae9fMqGSmavO6pllwwO1Dl1hG5bYn1pJfpUq2Xm2q9enV/+KPgqiKwFS3AcYHpFiF1o2bAIsFuRn XDjm2q4Y/G/jZdX7XjrBDW0dWMi/2i+aMwHRLRKG4+fskruakTOIxmRCFnz59F/Fa4kZGnvqToGY 2NSz3bxq1dhyTNr9trV95FnhKiMrfUJt9ow3RE8RupDWMGn0aUqZ4gKMmnFPmIJ3/25s5XQL3iFJ bBc/GXACu2cLpt84FC3TKbXLr1M5nFu2RiBFKVW1YAZY70WF7ulqhHizCrP3MBmy4ItABaT+DOcn WjEQNQC1cPvs2TzoGR4eHrT+RioBBJS1soRuOkkV7P6f0MLNAdXJuikPvCWfB8PprZ9iUoi7rLbN Z++DNDz5k7eM+Wn8UcPnwozREGAZmjg7gATBoX5XBM50BZJ+VC+NqL0wEtdLMOFgUpwOpAX3UL8C fYokjKKE1mmlNDw+v4QyZ+cjMDB0alcEPkFVvCzRiRXxvzrhAlPec/N3+6n+Ep4yYZoIlLB9dAMh qO6VXk6hgt8y6QtzB+86Oqo/y7zW152wj8vcU309MHuYpZE774aeTycoIfkOF48Ir6zDEly6tOJ5 zq+OWlMdrp18QW5L4TgzmhyDRlrra8snAKQtYQhbTJOz+9d9EkxxVVOc0ogBK0Ou8c/pWT64SNNq 36Z1aBIZgRqxxTss+P0/dG5BqE/DfTdlh0HRkNX87BfYEKdSu4T4v2FxSnM/qA42ExCtM+QVRFuO 8l4OclxNZUz0g+HZguW9TvXqn/EVVp3X0JVbRWgQeJVmbaFeCKocnBjNtEWnDW2E/gnMsZogkDD3 Va4tEw6voFyY+07MbEqNAyx3WkSfBfU8u0XTQJOb2qZPYGjYZzEqFHPeOZ1TvtlqxWWTK2SIZ3fb vUbc2jGZkHuLOVBSUKtO/bnb+v4l9dESYFh5TC1vgwRE2zITafyJHr9njUsMeEMpuB9RJusjAEGM HYDRjpIO/SgIFZZiRf6QDQeQBmanY333by5MT3G7AlgcB4w/P6gW3YMQgZTtfnaZIEsZPTh7aqql jPrl5b1o4KiO5+UgqMeYPm7/Xf4OtMPhgh1uFtHQrEHZ23jBqETsgoFrTZWS7XT7CpsmAGIMkjS8 13WeDJGgLskkLPQr45OY+1+q1r6MsZ0x7ReZz7+FKQkQ/atbLnefJWS5az/bYYBrDhU3ya+D8Z9Y aploJskPlN5EREMoOoRu8YHHOfZUgzar712XexzDI/hmYB04BnUyohaPamqnsFYk0mVKQFi5IWpm 9G9kdcWoLxrFdzfF/utKJ3oKdSGbfYJjFOUh9oRvPFrqO2sv46p7Knq7qxx7caSm9kkpblmzCau8 1osGrRy3zBhwsZqvfTZcmMmOa33+RBYyZKDmblqdsyy0GY1HNcCicI/nTMQiHsVh4LOSRGIvkivi /WSzAppiQr+WAqts1xVLpGlF2yLMMGAt2Ap3ICfSM11wOEeAvEHvGVD9mRKRDH52QNNm178XMFMp o2oqsoi7iNOVaoVimuEI/mP/7LkCsGrgEfWOjvsZjLLrk48RR81CjFousPIPa7i8YC4jlms/6i2l UjukhvqdwK7XjBvShi3JEMu8kORRaO/7NxmrH/GRFxYGPliuDyBLN24/EDTU4VbJjyGIk3gcVawN w28kkLxyprv8Ee+yZ4iCVdvjH2SxpZZdEg8v7XrNrrYiyjWppwJwQT5Z0+DIQNRg6ufYLqceHMG3 8FtIKJSmrqQpICEYTpotfpv1D3xD21K9pVZe2WG8gEHenLGtyaASJXP4ay4AfuKpK92JaYA2ht7n oWuViA0SrDpbA7fFzqoE/DLLvS5X9T0VnFP3Tz+UksfdwJimdU7hQpPagSMxuWsyK4ulA+3z8ldg ouTfQvRrrkuDnnDuK1vv6qnzlvMqjWd0F028XWUO/cLxNtbrsFjcriaifxmVWNob6K6ckvOGujr9 wK5F1M5syvw1mVtOrqKoAFfnd2kGAgynj81pdG3Cu5/dDe8HneetZOoS+NV7lJiJNryA468kWM4S 0pdhyM2qt26k8FlIWS97hqlqtiaWcmJASo7ZO1eIK57kE4oCyoPiBxfVxURVOYY+dACjM5Yg5j1K YlqFAq6FnbfWrk3qLyqE+wmlj9GUXeO3YKohHYu5CO0qvMGT4cnaezYp+6pCYFEnLPFIinc/qwvm Sdeo7Im1PMobk5IAjvodTKVdr+34VBCCg8yna5Uo7ddPCS9pKV3smsW1fTYPH3ihiUqjN4iclKRt B0Em1Lh6R0j6MWogjxMI6gC5LzchRrA38qpp3xw+t6YD7lZ7gqf971snC3e7VOHMQkP+8vqeKQ5+ oTi2ScU6CGqy4ciFQou3547jj6E7343GXYeN6XmAnRC0paA+BDoz+yqe1uTjuwxTrZ2NxCkaox0X B86S7Ob4CvzIUKOGJru+CgZXBs7E3p4dCQycgbqdvaKalS36hPti+ZIzpf6L3GkVqHhHcQpHlNL2 0sfl3WgK0xfCdcYMLNpNAa677uTs3ygctJmk0OD17nhcD9AXp13XKlkB6DNARi/kOaZTM8q5i6s7 6L/ByiHIzNa6YUBMkw2pNrm+LNRkuOasU65Jny2UErtvXDQVdN5feJA1UvOSJC9aW69w3FSpCzJ+ R+01lJGBEvfF2gRAlSWrb4oODaijxqK3K5Ryd0q5wkkHsr7YOAz2ERlUtZrd5/RvzmGKKLPpSNhN 13GPq9khsXpbBIdi288oaLHMYtTRPD4Ah5C19syINngoDFeiWURfmFRgPL0CVD1S7DWlwtNxxEFw MnawqdJnWWNOlfRdQaQ/ZSYohjeW6uNZ4ZsSnCTrlTNfAUEfuQpy3d00seOXygleTM5SjYH0g/Bm qJ7JQhdtOhz5K2ElPDybzEbTWWsPtP0kQ/e6gGKTSQuC54o7frMKRhtYgE1e17DR9VODBRsJ/4em RKdNkANyS/HIqp/h5hVDhaq48J5tIgNnBFVLd7hrnV/+xwOlCs7/uaMkWHMs9jthtGQKaMBCfsG1 nayzdhRjjz7oDe4wJcioKdqu7/2SmhXn3HkCd0qyFOQlGsMxRy1RYCzbT5tK1JTMhim+RGJimO7i ib/Ibwkq40O4q+hr6/poCoIXIlnEFBQKsKvkrjFmDlMAc9408L08fPWImcZpqe61j8v4HOiCzQ8j ZmB+upT2XBVeY9YDxGGlEfLD3hHaU4UT+McOZZ5+u34/8JwafhLJmZtsxEwpRsI0lsKg4cUCv/NN 4QOyJc9bBEDJLvlnJwEupHsKCl1F2KYD63qnlhcVJwjV7jTzB1XGB+9jLyfFJ/hhp508Jha09+0j 3ZDyYC55P+p4bldNdpbVbrFbtsBSjgmHlWXFDyX2Jw/922iHGrz21i1BwLCE1ig9Heg6f8sVvovA t/aeznEys/NLAGQQj2KCBHYx+96b6i62SahZ3o7QrHtz/a+H80sFDtu8sc9h6LVQdKn7NGrPjPsG 19D7NfgfubucaSa1jyELUFtDdSD7NruQuMwGtfzlQlQ0n3I7QRlzsGfzA3fyZ2tvMVctzSrA9nBh WfK8Xvb0eUoUyE0Ij5i55ZVTcMNnN/eonADpxaEy6Pj1E1hgGW9R5j+qWyTVJcfxB4x4G6SLaD6K BE4hhpnsgpY7Jl2dZ6L4TR9bkwzaUR1Eii687HitZU08AseerQOb8JYwsCSpveKgiZwJkW7pn8/C 1/cSwo4tpzYPT8UG8cc/8YiZWApbu+O9aHJ/bXQq1lJ/aptytpZndov4jay1i/aCaIXZAeozpV8T BLA4VD7hFBZmuVMHxsLl14bklMltJ/RuUQ6kKcXOV/EE+MCLW3Ol6TVo5C+TDZ/dYslD32y4Lm4Y YwaPlzWltMyJXOfSrFJmwc5PYR7th/RypTmZbw8G6twUYQ5QiioDxAh6El/mhGiOWafyy5WSZ3f9 H6FwClGnOdPrgi1O+CMYxBLm4muTNHqGsifUT83KjX6aS5p3PcHIzFSULKgNMXxJrvlUnbOde5BF qqYeQWh4CzCwkEqqqeb+VZdCvZj1NiPfkmhUuF690rpeuRauSL71yzU37csaN6SJwZYzLdFKrpkS e0J40M9ruCdqmW8OMQ0TpArM3avGOTI3lkpAX+wvLyDbF4NIsUS1isN8lG0ennDuDHgTTb6dayZi 2/GSK1PhI+l7Rbd97niY+tUNhTZf3rg0J9TZeRWehxqaOFmYkKq8X0D9jhR6aOy13uYy3OWeQtN9 dde+H+C8MNVlKwVUQFqUOFb1X1nWJmjmGX7+flHYGzoGCQLQTAxkdMTeFwdSsjq0IBs7sj5h/G41 U0Zl1tv9qU4Ht+57OJCXI0i/e5xocTfPc9VRaXzyz7jo8mfyjCjTv96cnK+1gzeS7/kCQ9L/Mwin i+j5c2ku4esyjCfCbSkv1c+jm+ajeOdDdn44Uery3K4aIjQEIaG1bER7/alsw6z9kMcMeAB1oofo eBApVO1E6g9AuhCHOPlHwEG9IfZDAACUJVpU6k8Ti401l8+6qpHSGMmsF4uyVKhFLpIXOXYgl/B4 lIL5Wd+7EjEtAAkESzmM0y6lofAKxalSGsu0mIpcLeDvc3h1LPoMfi1/2pqF0SPtQkbeNyY/z/0I wopbCC68YQVq7IoEk6zbPM7f8psQ85JqfcZY/VspYJ3U9/SYROA4nQ1wd/agb1O+MkCr0Z1buE6i kS48oap5GesIRUJPjJmY+KhZ5hLnlPhp8BlsfowzSn0firdt82ug8z5INPqq6OyLGGYHYnN0H5sD bkHmCpzm7nPUd/TP0mqd4d5jBA2kMiwtMh7/qh0KqKDa7w2WGpX+MayDMXuHFQB2HlPpG2Q6c1/G MxDdSb2NmK3hlPZO5xBvpSA7Ueyycogh4Rgp5lG5tRLnrCMMqoVYSGZOqyaJKvJsgTKD7RME0/hJ KrqAZWhTH1E3cP/1phfQykINMHUUME61K4TNexv9A0IzqBQuKNRXRG05oLr4zyCYbYR7YQUAjaUj 2RK3ybNz4YvJ2viImn1tpDOrf4YnVIBRa2oxp7QHtpt0cljxYTopYcxckDgeOwUi6OyNvzRFivIL M3xZqeeM9EywSrKX244+quHJ7s7SwDJzmNzLFVOZp8JGPJls6vJ32aiwZensuwo/QwLFJp9F8TtU QOq9Ww2HCnmFVoXASgkWIT2S5YGRV7z63YjcrjRQYks3ZrL1ldFo0PEieM6CzJxivDH/s4qL2vaL e4oqNP3X8cQrnLVEyx3dmiiDD0Z9UT2dSDF9GjFgEMHccIL9bSEQluPzi1j44KswrtwOBsRoumdg 4TLv2Hd3JdWwJSUpuvA82zBTuhkXfazJ+7BWhvQTVnFFD/gpNPtLlj8pH+rOS6DRQOYbnSb9axyz RQdFe65q8YKGzVmHnXEa84fHWr9rBnSzjgMI06zRLe+74zebO06bYaXm10NGT3J6phBRNGftrwoR suOitsaboS34OaWX3I1uzdpejjufA7O9djOoQ1nYzHssHUECOQs2YB4KK2NrGW8Oh0Vsm9DaNSw+ BgqaDERRuXt2GUiSaR6m0dVaEeZb/hIAHIlHINDrl2L3A1/kXhctPurbvounwp5bzT1VUOcBWqiD EyYFYs8N6pzxVHVsOf2110pdG818rlQPAKjVfz/ZiVGhfPdbEGRplYqqsL8jms7h9rVwxGAMKysa z3gNqgzJ38dfQyBKAoML0PcdbJ7HyZd56H5uhQi5dncA9LFntWe0KiQis7RNBAgsyR4bC+Xspoay 796V15lJCa/XkiYXjgG/nO7nTL/26srVdwc4xJPb8+NDCSY/xcand0cP6EYsbbsh+i6hkSvOaQa0 E5yn8xV+Liseszwogcg9iNnkvdlCKn58rPR2ZXP0QMpUeMjmOi0FK6IzN0WxFMRMmo3USvxhWVEZ 7Xx55d+AQDYY3M53lXCjoDvlgBhEY+E+fcF4Muo4FeffAGybUlMNYkLFb66OxiQvjLn4zB6DUn0R wmhrSb2bFvfzHZo6w4E3UQEOGAC0AOd6P3ZdOK5U16y231PDiMuFX8Evd14LlT0mCGticJCA/VZE ntUidPKGh8rmx3RSO2L34rCL1cy9W5INHkB26G9X5h9BlOw7dHB4IaqjcXeF2HX41fCgR/kG7Jk8 KA4T4T2q2hRdu4pl8j5H5KD3hJs2UNbH0/EdYyYKtbatWnWD1Sj3r2Uwd2J4RaBxZOAsxs9enfLc C3KtScPwLjnN1B1neM8xwjR50YXbG/ZDx1AnZ3x6k+YN71jV4xFCIYd3NOo1EMELasKqZ0hZJp7O la3f04MdiGrba6vEtzhx2XEMZS5xOZDesw9EEwaz6X84mwD+PiGd/BSryG0M+BO+hmPAoKDVec5K TejYy/LdeFFVbNCMzQitNOY+LHROPwDRASRpIEVekpsNxQY6ZStJYgwkUpdmZYkWAg4dbQM1xIkZ 3sJmtrAl/oHqxIi1KBw175YCLWkpWW9JRl3QPL/p15+4N64APJurI/nsV3Z6qY5kI9djqOe45i/I NICcLs5FlkPkyTJRJs0SOyOGJCeX7XPCu2lMmn2cd0fGCENKlN5UkyC0TBUV5OftxDPjDfmdNEUn wAfcvbEcxkfKd2XbhRhpsX0AcZnUAozgrdU2RaGECnQ2RK4IIUdc+S+h9tajminkjaEmy4nL2Fhs 4XJ07G1bemqQ/pzmU3bcqGXaioIaOR+Wnu2LZLzxGKtkMtjIVzZMAjV4q+hWVVe8PllWR1cSIZSP H/UYrfH9k2ceHDMJYQmSE0rpw7R2zxJ9yJh1gNfim0sKQ4HLTZSe51UUW7MHMCafW3mqPDSNSD2c REjLvvVAFQzknUsBm5ayE20fu++87mUc54b55IMcxpusnTveixOyc2LHnnb+zjQX7Z+ekbpzElR9 8zgtQVbuz8pTNotNAbrkO6am+x9IvvJMwPr7UuhGgs3F/VJIinkH1XdwTX8eBDTA2nMYxtJ8u/Y6 yKBIACVBEb8BzAcdj9ZB59S7IrKl3vjZbR2VP7nkDLQP/0/pT+3Uui964vjQP5RXlpqlSkBXCGpw 6eptzSfPdhBJdLnBoq3Gd1nwop6Ab5wHRSH8Gx6d82qRHycHGB5nQYczmSVlK5LX5f6lFhSCXGqn oUpussndX+dHParjjQAY4/eLHzVEqkWfB+2m/eKK6qNsRfl1/85S/y9aBvBiA5Lhw5WHYiRuo0pv 8ES5G4cJiuMDeRzAbo5sJR+j0GioK4WqYB7KpMWJ3kfCjanB1pBDztV+HhjCe99ovjl7ZlL0yeWz 98+h4MthHcCCpUWnhqiVVAL0SmxXmkaYYeFuH5CcjgjiLDmrPJvzZKVsHLzDnxJ0YgxKsTChnQEu q9q4u/Kc71DyHE1aUo/W8zKlunDYqTQQ2EDunHI+cV9i3re2/6mIcojY5TrMLZkWQRTC05yV07o8 fcuokF50j8q4Uur62MgVBn9D1XbL4fb7UM4gp2an+ttk19H9Alie1TT9uJnmfpOECNv+pGX9DZed qBwY7tcyZG79uY2ehIGa8MSdRzDdIlUKcd5+GyquoiO8z1N+P81IQ+wM+0Avxtz72GDFgBAsnnff RRgr3t8ffUBybvlWBgr+s99jHpuL4rRmffPeQmp17UX0u8fQNtJbVImRFjB4mUf7CxPofLZ1cfr7 5fdqw0nMGRMQd23w1YLPO7pixlAztQdN5pKvXJa6OZ8b+MsBS5wNG6UQsiaoHkh4p57BnRJE3JMp guTijzcsvRH/uGzLscS1GRVx36cuBxIpZgwgwKOKtYX04Ql+cEwdCuilwC3Y4gpGkc63wXRF1oAd Y/GFh1hypG27uP8/24Bo4sm3u41yL681tcyBkEmb0ptwr9DGgWx1wdkjeIzO6phO+WL3eXDs37cP br92ocIgV9voaZuV2tV8630WqRPwuGPXg5kNdFvqFnxz3ai052YRTjz1awCgokntddJI0KSXvV0w Ow+UdetNjM4XqrR3jyQ2HikQ/UpdTm+zBF/P895vMJd6iqkk1716AuuMu+kgxSEGsIr/4p/dd339 3uQZ++c2jHtp5qwFYA/uCrl5W8nd8Fv7B8444JZvyEVULsPFZ3PjkJXN0Q/1VhwdEwLjuGJoyqzy udjHZhqihVjc7hSfmy1Q0r8KzXR3kHTg7ku5vMa53NENNRccTcWtMVf11O2+N0ZKDYo9g2jVz/DB CGXlysAZP33V+0o7KD53mW/QIqkfPiZCCPmdtdxgwoMQzerD8wp5TZtgUJ7LJKEVWM5tWVFsO7Jx q7bXMR3ckHg9A4I9qlD/kWUIkLoetbSQfooEx20XcYtIo6jGOv+QGsAPxnW7bT0xd2u1d/ubbSIk eWVA/HAA7RxG/7pu485DQD/CUI6sMlR4Nd1nqxo7FRhV518fs8FWQapzslpjCrrrGnyYlfbaFC31 EDu+N9VnlNzeZ//Zf4di1Jo5bdu/P4XHMK4KzQZxFI8g6Dk1fSqznpJHJMnhzS9hVdyWqIg2H0hW yDbd8lw8SckLl1RjcX9mqdcqz7O3dK5Tttk3hHN46haLAokhsEOzINpEhZ2s18OpqgJ3XvVYpmpt RnQtyhsFYuaRX73fc5RcSD+twFqlrB42yG6gabpre2/WfYOgUzMDkX7UlE+LnqCqMIark+1+pXmM ohcLvw7WaAWVLBiRAx6fD7FOzwRlwUgnHcF7jQz4thtF38vZgcXzOwy9wcrqMC3/5AUUjVvQpfQ5 aRCjDPrx8XBbWXjHEgl79x4Vmp/FT19SYXRewflU3+dnNgJcFIIEmyyNmiWA31OeXTJH6mfpoceY gUgS8YCj0XqeWg2p1R9n/XVTaDg4QlOfVAAX3XkfM1MZyDC0U6/bZ0lewJmle1Ktoqfn3dc3d97X jnDny/Ad2skAK+9NQrWzVj0Z/HEyIkMbcpRpwgptZp1IQGDmU6/lYuG1PZwXZ28OlTIF5pbKq+IQ 2XQgc7uloiGtL4LpgPrWf3AoXe2f9nBhQS+hQNb3ANvW8fcob8MasQ1KnPEaKDbIGT8RfeCUHF/p L4KHuJlJegddIOMViWNVMbTVuVSFDPCAAtejmM8Ei1PAftna8Og0UYFB4oQby5rF/oYKFna9sTbU jmgpQ0O7Xok9MqHvTVjLGJyfThtmk0q9MWv44QeJ4h8AK1R9k9BRtJ6BnxYI3LRxau0sRQwaFdRW 7DpeA48hskI/n9vUwWxOi7clqkmosJykghmfpxyYsc/qQRjJY4xOgn4e75dTyr5A8j6jJeizbhoY gw096J2czo4xdKydeqpF1B0Df2xfV12pRNvYvwAKor07pMjo5tSEDgWBogpVNFloy1mle7deJpkT ZDYSPYX6WiZBIkYDuCmljBZ7HDWPp8IIJFjY67idQfFLjhUyVZenYv9hypEj/pogW1qOpk7eu4A7 thpE1SC9uB8S7hzgqvrCIeq2bzAxId1Y5TwDQoPXd/n3CLWEte5ZyR5pK1LCmGm01RowmupZXyDf BTxR/is2zRLE/GPWOk1ycbk5uohYi2rUfJkmpdQEdw8wRr+rnOdAGXx5ZHtENcZbZkS3HWsbQSP1 9Pcox7zgekYy674AyySj1aFxmE0/HgleyWQlH5MeCCm7E0FL1Dc1IzmuOU0G4UW3daBoa1Fab8R+ E3oPJ7Xc2AQ1O469FHeoLqBuAwUDMojmUASWZNm0yQDsa/F+YwvyHfHQztqxTPwxUujYakdwYQJd n1zMXCxV1ywUwMyG0Xhjc91LybtYa8Oulj2Wul39EAdK0sPPTAHRQvkFHlUHDhWzLiWKcVH99U/J Mtvw3LquqvNkuQa46f8RjUneTvtHmwADC41Mz7bgbI12yFdfF4OyTMfJoYmuHMnKMyozsmDoy6V8 JjCDy5XcE/3Uw6yhobC74s3bYVORh/72sSfthfCsZOHh+dNRUi6HqhJcQPtULPXOD0QyWmuZr8F8 FTY5/hWlZE0WMTyZ/ig+jZjmZ/KeTXVdGdNkWflEyndz0aF8FwpqyTM1pfipC4Uhvs4fMpb5vZjm g+9M0zQb8pik6mYbOEtcwrSEk9ZWQFGj0hB5cGzZILGGNGS4zADfAd3cC9piL/DmSUmB9lP59oW6 MRcHaYwo6VzXJbh0vCq199KVCEqrLHXHutjhWza23soRs2MraIKuSiziChQePG1476ZUx3oygCjI S7vFPO58N84e3BraFN6s8jF31u/vGzdnZiydtBZrO2jKtdr3bj3KdCdu4uWo3rQFx2e6nxeU9jmS qT3MhUPsh70Yc3KXyWr9eWYMg/Iqh3UEhjoSJWkkNHLuHKvd8ktlXTj6/BzH4v4Ucd4nU41heWn6 XnHUYjpsWx9cKhZMPgN2cVBn7Z6xfBvCZy3aOptf2mUGHbmPJEHaSmJ1AHEEiQhmBi4ahIErJDWd AJYSguxxWHtkWXo8AjISljIfB55EuwycLdZO1tbJlmPVttVQGFE/q3TZp1tRbuu5ctwDoTDTi69c KkE4uxTXFnEfXnsyVVwxPdXqmbTi3GrqVBitAqXIyWsxe2yjf8XpyGLnaNM/UhxpkRmMzmS9DoOw a6Z79oVhNaHogBvZdVGE4iQ1EKIrSyAgtUtm++rks23NFvBpbpkLI6ZPCEzU6lswVp+7bSotxXG4 uuz3G+PwlfXCCPHuYfatQtMRGLoIRj1dXGZ91o8sj6psqaMRgZPkOrX+pwbCxLQyV7lkUhG1wZvz AkcN1VwUwNArIHsSP/VZbHVQU5fgm0PbcUZrfOdJa32cn08HTRscU2i/IUC4ddYZwlLb/jpI6cjU tGKCFBO3j876881FUgwekrM4cFQIqo84VprlHT+NKqsP1FTl+zC+bmdtqccwF+uZpdVnA+lHpUBm Mo9xGTBHFcCKthW3ArLB1JihUIy1ZXLGF63kETzOssXbqde/JchwF1Y/V9R0TdHAzuezSrQ5qCj0 KprDFdQ1hQryUB+hyf7bTFpd324ED0Olgd6Lkw/D2jdNG1AAVR92GSnqg/gbAGQ2v2af/r6OOsit poYyyvkuCP9PM03t1UuAdp4Z6BoHSpKI4lqDj1EF2D40GSIKP1Q0nFMKa/mWhxxlBSjXbYgcvP4U JENkAp95C3bGQj8trIK77MKFsq2uQcb1SoNVN9jgNfyIP8kc9tafaRumZ14npbAxCeCLkMvlkLON Lll2+2t7Nae8Ds1yPXc9trzWEwgdetobLYyNl980huoH26EORs4wk2lT/l2MXaxmY3rwdL3JLBq5 dTDDKVq/XANnBx9+BQiuuF0iBeebXCOYE9b5EtW061GERR0aNZfdVvQGh9ZKxrTkdBjszee0dkUc XPSdUplCppgCsQFCX1oDgiQ7HUZ6oE0W6C95/W7Pu5N8kLr4KwvWUNffVQNmY3ShF9cSBBGfszXZ Gluzj6MeSOTctRndVnC54El2kLLHYWl00Hq4Lely/q+jIbsJGAAbWFTlmO7js3nOFK98TiLJgpBg ZQ3FuvkGI+y8t6SF2YWzMWSZImlRkb0Luz6rccQO9lAsJaernFf/tciHE85bAu+S9BTWgXPJCBvc 04ZaSk6r5XZaAi3nCQRTBEbEquBVOUK794Ar0CaaD076PfeDD1oCCvwapt0NMeJ+zVAAP+ZP0iQ6 9J/0zkKVzAxg3MlywgW0lVDYwsDb1C6F9zgdeRtZ+DAo12x4JMxWc1v2aQg2VQA8P5gUiIMPMepw EIiVX4suDcl4nfIUZ3STtPdzypxg+5WcSg6/J3rpPgcuhKqqjd7+q7Hac9ZOp+rkPhy5BDnYPVHd 3BqVMccib/kO3EPMdEWq5SxErzYP4hY28fQdFYmfV0Sq7F5IgtcPnsd7qTamL7JwL12sl9XVsCHY o9p1QYotHB75OjZzhcFBzS1xo4s6iwmwBwUjK25A77w8kRnN4P1dcaTk9hlQ3oamV/x+TzmDM+S8 0R27nbdywnwddJSPhJApZ82tkJ2zXhO87L5icEND179oGZ7hEJha+Ty1uOLOBx+USEzPL7767J4O B9j7V2ot5iCT2z6/qYL04e+UcfFZTIdTRrdbWwF7CnwFg7IfN0X4dv5woY0gNWSw0Nmkm+KrJIF9 Idf4wlWDU2hDfO78CItpJ5LhX0TSYWriixtr5IZR+oFH9lm+6178xNeSa3hlp050r5u84mMH8HNn qvECTJD72rYR/wLS2DN7cvNS3eFjMcibGNDrxeqy/dfKRAarMsPexcCFW2IHiQiHbcEezpGQ86FB DQ8H2E8bJ8pRPXi4PBZY4xwDtiwxbv/j62p8TEzjtFFb9/qAAegY7ETVRfpibcw0LLPM9NETG+r1 dPOwwVo7aqiUMNK4rHI3ijxFAQaEDi30FBg2y5/iEXz+wxuPZKhhwbnG1ibOf5AtkvMs1LUQYxD2 gA4omUGmwLTIpsK9HXJlHYwTy8ruuJUBVbEZP+XxK9o59pcFAC49uK0kSTO4e03IP/Sb6Y3qLdoV zANyzQWquEXWk3/wVFM/mhdmrdqhc+RBI7xA+44GVPLHrDyjW1y6uU9k2bp+dI4yRJqfo5j2lZG8 gMNkbv7BIIYdhF+YVFhpaA3Zyxw6s5kkc6ZpTLN4wZV0fGjI/wY73fw4tV7F+Dk6uwXAOfmZkiw9 gD0rCw6X6hAJ8Lei4fHdRrXuT+cKw5Jy4pApXilIKtpr7vkwKWyQREehb3J2D0iovjBc1bN+fU2A tuO6KJ8HX/0xYDAzYAB5vVS40SuQ+aIOOO5KDMttpO4LjoHysJ4ibXLFIUPJPIfPTL53la1Dzxoi KNDuHOttx3Nm0MUL6HwZ1D/SEg+jRaUc3CvIFkrh+b/KDlTkZNMHFOViIMGl0tZ6zgiokY029Urp 6C+seeAaBmLwZAL+pmR88NRkkwqDqy1hOy1t666A8VugpoUkRc/DT8BEvFr+wax/KLJPZ8Uczo1j Q+EQ9dbXFfSV3+h11k6fCryweLyZnqRYafMKVX9yrJvdA+IFQG9CZVWT43ceKPZ2lEBuj34pU6l+ ZKkrCwIuwtbrdf8jLER3uYesXpFh5Awglk+AMA0trY2CVyK50MLio99jsQrzRj+S3Hy4x+I4YFtj YrXToOvKF1vRVr06pzp+J4f2UXzLmteVELGXjOF7kmLD/aK9vWSNHgOL1iysfq7t3RtnGmtliaYu DAZXL5fCLbdyuUv96OivEMrAOCmSTRCIs15zpNs6QVLgfJGlqSyyuOpkbC/wyM5FeGrZFGMRnnhF 3oDYsJRMiLQlXenGoC3dsXoeAkjAgbNpH+q1xnkuh7NgVe0UxFlqh6ZofjxfrMei1l0JDve6HLKF 3J/a2CZ6zCH8vG+DbnCLcHapwkAH6fHxt7MfMOe0jFsEhfz8ZXyF6ceiyVpd4nQEiVwJaM9107g6 02iqh/zqV3a9KmYW7L1L8P/yarCByuyj0VKt3DuhYdWfykcfLGwuB804SgGq6gJPgpUm4XsrgLQK BmT18ks3BksQYZFn3+aImz+UYmg6KOp4wJ/CMW7lE+iCynqhH+LlMYF2j2IGsabH7b8ioLJN/97Q lPZTLvNFnMO3tZSsTZV9WB59N7K9rgjLrkB3nnpNAZojRiyEI9dr5jjLO6jJNEAiGp4Vg7C9BuX5 tv/6p2m7PGnim772LBdzRgm73cxXA+8MqKr3goOOu0xCyI1D9TB0pVzVBEXOfL37WDjYjB8/y/6J X9UeM33aJrsXikDHw80HGDpGFlJoLFJEp3FFRR/Efn5lZxxrpR/J9blp+UvDgNpjWerpsljilHV9 xhPu9HDZq9kwESpgt9be6qhuQ8q7JCHMb9CkByTUAPBtC9HmtmJ4rtS+EZlGVaUzhWChCR9OSjYP k7oZpy8uqcpdIftmfwBZ43d2VoaLhftiinnxciyGYOEzZhiD2Uvos0JyOyDcVQlCG8VCyO/InZYE DqzycTwg/BqZCoi0AP7H7Xitva3RtCbe88XvRb56p0g9ZP54ketqYpThqHBxxY4mlVAJR0K8dYZs ikgK2tW27panqTYh8ix+d9lvFzhfYanuL4fnCdraj/9cKFETxYWtEwlV6EoNf26rq9XdS1ByXBEe JTH778WWxuzSBUeWocBZOtm9iR7VGXKoLrHAPLt9WK9G/h0I6osuNXR1/ctuXf5V1CSsK+EjTwcQ fN17YTuLNeI1JYL0CuZ932YrWqmKgAPUN0FK8mZRepVncM3kHKTPnKsvf0qOIt7VeZV2pWNzDYba pyOBePefDEcI0sXY2j+C+8mjb7UN4hQcZTktMhzodR+zCQXBzSSrvqRCz2haSi5Y2QiE5PnGgzf0 Au28H7A0wLh0OXQk1heS36bwuTAxe1NqFEKk0afBmZE1j1i1Ojg/nhBPOCf8xMzlvT8gtWvty5xH y0jxHoVjAeHIVW6+4OS8AWGlyeGxYgWsQeFti2ZGJz8gMTqN0QOsk2R2AZiXF420lOjqblHQcTHL kESAYfA4zsWlGC/6s5RB8LCDywSgIfsfI5yW+RDFX6UAsMWZL+A0wOh+5kVGQ9D/LlzFNf9dS2fC M4NjWl4uYzobWLCWO4qmew+7h4owrKzKClRT6/8kP1TPlXt/oA8S+4WMby5vR/qrW5Dg+ustIyzb INRUq6bo51u2qjSBvHfYKvg+dOfimhBppQ1EvTjvTISZ2C6ZJ+a44ff1VcQo/Jf8+/yOqy9B4nOC UCwEDx3Ym3Ct4OuWBqvQzldTsKjgs+tmwrM3IYXSWTVPLCVrjyB1r9iqvZCvu/0UeAWKNJEKFMJr KNZCzEyre60SnfC6fIXZGtZNVFkRjuCSJvL4qHop1xjYniHcxPBz5dPWkDNAa/6L7XDhikVnXLb7 heET+E5HYgTNsn2Mz9qnXu25oM+UFbz4hKDRy6MqRz5L4NLOCLllFNsmlzlmTLruhoADovSKbrCm +2LIyRCMT+fT0Jj+2e+3cqnEEjZ4zbW4UL3BuKep0KwsIW7i9XmmPgYJpSWs5GI2G4LfRKJ2UY0S B5uR2Y4Kye9YM0xOyTIVrwR+a7Qg11x63tdiuiK3llZbCmTIyatY6Lz1HM8W1N9nbklavetl7iH/ vduRtZ4bkCQ6jywZRhyEJBUFOpb1SCUCK0gDcnVvPUL0cAwrEpD7ZTXHI6Yix6kXg5yd+ztplVaq 28nqrc5uGJpZzccvrBYc8qOZ54bKb4wtpFXCocO4k7FFShIJs7AfSEVC7vq8koAN21ol5d52uxa8 Jh1ixW7m8GKun+cS8NL9090dRn9FIslH9gvXJ74m0tQTVC4xB8+HyyI2rOXU2nGl1FjuuLivhZk1 H50JOAxwYk0LFJEkxz5rBMSWSMBAacOGWt50cXVSf8iLf+XFXoafuJgJLYO6mixpa2fFtrbEBl/R F3uUqfsgjWP/O5tRtvSAIgpXQY99ga1SbbtfOPl+0/17GVknJW3TjstvMiLdsaUQAgqAPlMG5JMc qBv+/kdm2AoNrnqZVZX2upxEspFMBItEFkZEiC4pfXAMHQZJRYKpV/Ez3SORTzWW/QqziMBtf5kN gvFrN53jUnvXs2R3Mq15xWi3rlNmEpRSbbLYQDZRwceKZSi/LwPVl6mkup9O2P7DePHaVxi+lSlO enXdjuftsGEwCCcgS0Y/tYAphto6hq6YlZBiZ7iMOUD7OWe/9hkmqqo9nc6tV+lByDWyuxkMi8as L1S2cRVnStV7LAhl0B283y3t3Rluz5mFALtJJ0rsnmC4aCDdCiHr9fLrm8+WvoJXv6ULNlVHtszD 1VX8+w2hzwoMQJsJK3ZGJnL30A2o+DXGDt0pOqXA7akPGMgKna5JMEMkXtoE8/jPwHYxH187sRo5 5P5eKUMlR3JK23dDDR7AydQSRqmf05QezFKPgnLsx0oICvLwrheubA9GtyMvyvYO2EEupEDdtLIB RdHrT2i377Fz3mcJBgODMzX9HKHDYsYXdKTuVZM7B4EnP7CIutfIeD6zjRfY8Hm04kuWcmxA4MHV nDAYwiEWgwQdk8LyQjBxmrCUp5xvBvrFxhqjpEKMQg4LjlaQUzPn5v/Bst0AOVlRf51k/xisnHxM Oya0NDkgoLcPlkJ7MRnwcpTA2730qXvgdxXQHLgxc0DYSPFx8oIuGLwc2Q08746hYRl0S9YInFX4 FXz7SmdE06bFPuQ7bhYoDi4I0eU4SrRFcb7wu9pHqON8OC8myYPLJ2qou+76O5ExQet9Cp7p65y+ X40x5lGUDwla1J/aFivLSYabXVHBPs39CLiuPuQo84WWItK0GVwBz+KJy6OTSxEsanm96v9YwqY4 3JucfTZI28buGyHyPh6JA/PCHDZ8Kxfnof89WGmqE2kTRkixvjb9CUL6GeD5f4MCvXWjbZuzYJeM hBtlVkPH+cRDYpmGY5quj9OSAjdH3JDepxxRAWIClNXnCEWCJzCCTFa3+TEmK6gq6LyfMLCx875m akkXNyO4NQzMAy4UEme4+JyDvo9Y0Rce3AaAvp5KkE7Y/GAOWChH8O6gCef4U0pjx75c9CHwFfQp q0pUiIK1Cth+WcQWP/4mU1cZa0WzkD8NZ+hI/j5k7OBqr2G6yc7vjs3LzR7XUdIt0E6H5KDOiwTG pVMu9goT+uldtXf2VGIjeziGZpDi7VT2k/JG0cWRlRpoPntjOVSYUmKGfE2wN/Ceg3pxSiqvs/hy Zhdw510WyTQ6WcpDTzxTE17GfjpOFCtobIZ1NTh9XbbTiBuw3WBEHhj0AifHXumRPvGux4Lm/zj3 0WJqNj2fUDac0wCr+h2ar23Htz5SpJjEUYgRVaOIWY9Bf7/kROuBdn0QF8qvijPjinS0Vn4eTkOn AOhGTvesEtyYBy3K4FJL+YpjcqIhWTd6Ogo/uK0HA0daPw3x1Znp3JJM5tzazNrvVABKEkvCIebf 2VGeDV0gv7mI/rhTQLPCbfgxg/2F+Ch1Zw5H24SDAlTR0S99hVIsl19eMoop6Y/4CsIl/Km+MVPe hLbsGtQ+V5OUqUGmFFTJxMR6jeVkUIkM+/PSC2TkeUDQXZfnm6W9jCrNHHR2/gbVW3POMrbezyps QFa44NdKWaEjSKWrhgHcGATfJaQNBHtn591T8f5Ivju6RlK+K/3gyVJ3YLRFQXc73BLWWc5vXo2Z jktsRQSBRR6WgDvsXl617WhCL3nfyPQwY/+Lz8LD5UR7Ap/dclGT4zdDYIsdPnmiX5kxfO0eFAd0 ssP8w1t/ef0bqiUNqb1tavEzO10pogIbfdIaTiszorre/cBLTSWtVmWdPhGy4GX253rYPKnVTvNu IOnDMMEUZV78GexlYQ9U5jK5do3eTARnRM3l2vPL4o4NO5oiond6E5iTNkV+jdsXM2Nry1z6Hb/X 9CtpP8LMwc8Y0a/3HGDE7P8lOVqZRdKOvvLyRCshh5E2VVDUxmpUU6vBtAilKvq6Mwj0ZTv73mga 4lJZKZfHcWmWIgKqDzF/dJfziof3mYViNVVsKLy7frbCOvhol6qtllVPM4gMQMOsatcbbL1xD+4f WOzW9V3sMeLnio8fKk980CDTIAP/ETsWZh845cHTKUDBIEBxmQ7ECrloqQ/29JLNDOiuhdAADQro CyVJcAT7BF9hscPTr7QF5xBQxkp7cDAwaWVDuWyTohqnjFr6tc0u+qYcDOdw8Ixx9m81Qc/7m/4x iYR75iFcLZzjQYtMZr0r3JXgyQJ+aFfV6Ul5JxsD0Auf/feJR6vg5BgiyfhTTSEA+qN7ggwUNJ2J bxEDVkPSmYCziEogjRedAaIngj7W4lvKTFpC5FyAdYNe3NfeHY+zkeKxxcjWO2wtya0WgtkshSVb UCjf3/VJfahNsqR6dbepgHSVvAei5F02otS/LtyU9ZAIe3VJpjpvlQQxo9sMFybe9ZgsjT4nb3DQ tY+a3oo8WXvisAz5ENbqkOxfvrL45G0eW1wn62Wqs/FiIyetROzu6SMPIyGyG0iCPfLqxOvDJuRB vpX4yMdaqO/qgfERD3PlflLPg3mO3XTgtg3DEHXSjT9ErY5GFrwyju/2d8s0gC7zjqPYRMXX0i5O TiIRd6pQSP+T9JOapYl+mC0KnxZs4V4Ow/0/bcHhWoza8aKZguCuippIcOT2gBLucPQaomSvc/Tf fcA6fOlEmCKyl1AQwwdqMKm+vSGfhILISmxx1fZwMOg5xj0MQ9y0FfiKzQHeBwRvRbSogUXD4td0 ck+1Eg1g6Y5pnjMG+ICL480eDk6vwygEqXSEmwKiju4BhN5DnjWwy70l9QotyQk4GDYJ2LZ0iX4M JE9QhW3Uv+iN0hocc74dTNOhY8E8GRLlsb+GcvqoSx6qdaKZ9tsiVwppZabYXW5gpDHJieQyA3tM Zxd8Cc0Zl/0t6mvjT4h9aQe0xmR7DWpGCd7OkYZIheVbZ/gfzDLalDvPsjCV+E2r3T//tm0rMGDB PHZ/11Bq5zG4sZ2SejaB7zgbUWcoottPRJyLlvhNLtGYfwxmVJRnUr7Y8kVZ/KqK1nCHxD1h6Qx6 s+3XeOzUVdRmycBn2LMV+kYS48SLgbRny/npteNqcCMBolwTw6MSaXXvT4BKUZm9jHmTC5MApBT/ U6QSfjhzKxC1eSqCC9LT9puJHz8xnO6YT5r+uxXarJmr1I/el6TVkhp62rspw5UQ7KKVBiSt56zg DmR5NFqASy1+ZSrVp0MIGqfjG0CC6GMw38/cByXCzdbCo2353JJhIyn9SLt1vEeQwJ7g2t6KsMeb fEkbvcdFy6vemX50FC31bBGnoVUzflXuorftADin5BEGARMz4h72IDP7D157141vTTyrGsC7zNFQ LYA2roQA3WjiLOHPsEmoWuor9RoNmNi2xsRI85ugHQCApth6c4s+AWMeG8A1Jm0kdgzgZEop1Yqx TBgE+Pi5W0msUp1OV8ZAKpddG2O7H01D82ft0ag3/IfYMQuWCk0PYPa85X0MhKc+xewshsTRrjV/ 1wyXGgklB+gotVqmV8CZlrGFx/RzGOQMGJ9wQIKE6gcBFSA5DovYeBMrkkGDtSiGdFGTtYZg4RYo 1197AbB0QWWvbY24YigCfqjK7Fy4FjnghNINI6aP9BQtpFBYhEwycCCZqMWbesuFmAV/tTSB322T 2A3t6zsvU0mOBtkvIfXLOgoz1ltbl03lggAGqGuZiQjdmEzIkivZvwQvzVYY7QjSehuFrC11cJoj 9rjzXHLbDI2LBOd67+FlWaxyornIFH4V3Ef3AOvY8p0QOi3L/c1U8jhbpmmPJzfqlkWJoX62NVzP tS5Ic8tVS+dfok5cLHUHrlS2+5/hEKtbt9MKp2fvfH4YCIOaEgiG8ktHFxJkDuyybFCz1Dgr3fXR NEtIxvgsvlF1uH9LIXxPulMlJ6/N/fUqfcM5tkU4J3tWkNKjhoo+UdZO1H8quLNkSzTZWaduJq68 FAa3sidg6+KauGOS79KVRzdiwexsvDFDtotR3bne1uYQNJu22I0N3WmFy53X4f50y4RTCxb/f5Ky xiP6NApHu0FCKgi1rpJqLH4iTsfQwSao8bUUclfVb8HLJ5ZD5Uh/lEnRdcKfSZTe8ERikqE5lbPf tsNV750Lmxpd2GyNzKXaKh96aWld/qA1pnrExWxqrs6lSn7R7izBMZkFPiEAMc80yC+XicPsxVLb HMeDpVJt7d26/qmCCy5A8WfkvCyR1a/WkXxW/1f2/JEJQteKmiOZnfZ4GTKb0CjwiP1Iucnas3zI 8gvQj5oEiexnkUtfKntmIYdHrcbyZjxox+Ee3GslX7Zgd5h8/QYxoh2NAP0h8xooKPzlBwN1JdSl N0bZ30rSRwW/TblVPtdYdKDnlDTurbL97Qpx72H3cuiKBNr+4JmsvcO3VVEewEOLHp72vPEpAuYu QiKjBqvgFFSk8jONr1E1wQ4i0uRWHGluwtx0jW4Ha/EPjDOFv2VGdS559TTeLvM2/Kbu/VbWbYYJ CO6pExCPfQ61Qwj8DhNy+x+iXaQLxt4aORR7cGhh9ovZ+zwpL/QtRpy13tl7OWgHogtf0wg0nG1K e/ii98tbyzSlAwqyIg1rQJB+mxnNGTOIZh7U0fnw57PMYK6H+LWR9mpcOnnia4oHkM8UTdpHGyDP 1TQKVGaPPx8z1kp/7mneFdQemb2n7Z7j8NqNBWwEwwCcIFLnOJ34e5keCblxhe5AV9eZwhVaYDil +d7Vf/CLlBJmJ/vlXp9WpGwg1TSuBxz6hECKIhy3oePnme1s132c/gZqtLuw29fePR1JNVbHNzd+ G1gqockttXVZ14nNh1M8R9W/E/T4sWGtnuhCsLrQWI0JiCMJBW7piQ+zLKigOHvE8jVr9Ad1l5aj 05H/+MaVMoIw3eQUr7N3ee9E8kblBonwDKfzNrSH2S21MZTZci70ie+aSngVZ04tXgqt51YIB/Lt 8w0gQvIBXqRC+1xZjqtqYsxx6jMEZOQMsKNIoyM4RCJOWA6E+a/Ms4O4AWV7LnZKyji4fnOmlMc1 Edb3tEJffY89VeCw697+MW0szyjP0DBXVLB7Mxqc6ll8V2EFFfpsgxeScDTKEsbmtOr3ul+jdsi3 krLrY0XZ19u3dQ2/8UUOs4FhszBTH2Zk5ALAQHjfPR7U6D3+w7YtOLG3PcxE5nnKK/tr+uLpZgjt 7Yctm1gS2/oLTP81gRloUM5vC17iDu7lhJsiTlgTc6VxISxHnBAWcVJsw4RFtaN3kpRrXowLRXms Y98+dp/1cqo21qlQOTkwSlyv0dQPxCh5nHSU0bUGYcXTk/YrR6vg1/HN60Vhdk89SpN5UvJzm87H 5MtHnO1rJV2ZYOigWHAShpQwik4BYQNe7LN+8zD9U7xzXyPmshkcLYu3uyqLQx/+Qc3jms8wjUag AddU1Bwtc3gGPzPqVUA6J14eT06jvHpP/DHIR+o62CRiJZQoJFWp7CrYT3wniPBTn2JxwSOiVcjH 2beCZAx4aMAgcb9BEyze4YNrY580G24pUmXBWgd2lTqURyWAdsJMEThQetLXrhfC4Is9UIWRdFF1 rnhW9YlGurwGXGd5VyrOrXDbhRxQHlSXk4hpusaCKkLs4KZik9TcXNh8/456xlpdxGEHtxBrw7e9 lQggOMFbhHtA91+20szmeDz28SGnTzRdurKc9jgWbPCGoUQMFVs2o7wRTRUMfStrOQ9o0k/ACQ5Z gIUVLaJP0+cMFDODwUll77Ze9wwijqSEsOQzBDOx16kh1w0Km/2CVC+r0tNqKZk1o/1MTseXj7a6 oahXO3tKTPcgoa8kpdwLec9pyUUx6TBDyAjTcSUgLqGXcddFqkAL+d6SHs0ZCbb54eqU0liQCU/9 cDu9gPuX+ia32zOjW4C0xCkJaQi//qsV5H3gzpeNrdfUOliu0eguoFRrIdpbrj/GGqkl3myvwIyQ OyTB1BXcV3M1tVqiaERFshY0jXDIyn5HNg8GEmMmg4yLfJ/Us0/Z8h/jb3hcyhUt9lotVhN8LQst T2+P4EnNPRgfUWIAhqm0kCGm3t9FxffS3GFZo83/uMuQimBAQPjRrHyVUlne60xHNekAPf9Jnboo b59aGHMfleT23APqUDdrKvQkFqdVelahczekgBnxz6c6XchMyfDSpJLCVkzvwc25CV2Uqh0DJCy7 PKSqdW5+rMmu/mW9IP+kbraBOKkVmo7M1u9ln8gQCw7MJbECnEbYXcMdXUbIkDKqxAC2MZC9NapU byKfeeJ72Gh/bwL2HLrgIQqaNPOCUqRSh8c2BGqB/Yyn/DJz4gsYvi/2Rmm9m4ODcaYNRmtYq/IS IcNHCxAfcscZDqcnr3ZSO7+AI71bX2fWIHkjnn8bYA63dWKlyDk3/euRv9//IP5atn15qSNy7zOw 6rlEbCKdnSHC3HgNGVRFzMceLc5VbR9c0PPnk5c+7/cTLTHrwzA9YjKfO+03iCUy2aaejUNtjFz2 k6cCNrKKBPkyCPsTWUY4HCdZMMVrCrdRl1ziiYE4mmuIkmPYCHagNX8UV48RSbHiRXl+Hr2BFAiQ LEOtLN19bZVejpJYrtVMlSkvRrj0f0Ay8sUt5VyN5lhxlP6xkTTfDbMhcrg6gF86aDzpiuRcCTNt 723azBsYt6tCS9sbydwpvMi1aW7z+VYAZ3suMoP13DzNg2GNHpDxlK/qqU9+ucTltH29EONXA/tN a46YhN4pg6+RN00aGPdnDmoF05zwAKP97Gf+2laJeutd3aZcS4/mrED+iZztriDqbG+f/azpVmoX wvGnVoi0g/+d2ZzzY2utxlx7cAgGwn292X6VIZPxQeRvkidIRzzm1QPuP1Eb09UA2t2/0Mh2nLDl ps5dA4x7W2xpBI8kXguiIk5FMQPC5fhO79sl4F4+wPxG9BeLBMHHWy+2cP5cPlkAwRRLdxNLLfTh gaKDD51u2E7GACbjceT/A7d0GOc9sSCu4feuJHH7DRTmE4n4o8IOZqJlJ6Zln5JmRDcn+6FmPEWX ikNTkpYC6FqDbOJVqNikPQqn8IR1gTDmdSbyM9JWL2CKdIMFmOuY2Ai0uM3KFd2UlK0ZRiRqCv/R 2n7HXNbdFXYfzE+eGQfPARv9woAkf7PgoXwjcFzDiaI5qYJoRWmr3WW2oTk+fylhShSwP49xuXDD bQZ9DoHzxDwNYtfNvd/jtCGvAdZV+rkIbImBvJAKRED6Huqs8dgOTs5mMCS7cWphKSoj1qEd3yYJ HknruBLMRvugeOlTHuNM/z2BIB+cb3rQTppU+f8zgf3j6qLlu1XNvIcLvF/b19Bymy4N4rh1y6mO LFoYqHNhKlroO+Cq/xPyKTRopBnUlm+32EN1EbeFjTDiSz6wQ8FV1S/xRphjpBfzhnFqEYw1GOpU FWMO4nnBotSgHInwI+UPA213Bf7y/WgbpnCcVQBrpqDJuv9Ph2tpEsjfiNI3cLQJof1TW5HQPjtm p8Z5S16ea9hd4c966Obr54kn9Nu55Gi9jFDgRFv8VeGWCPF8Jkz0A6/aMu1cTZmdOYqMfqtmSFUN yw3SHUCHwJGQaFts5AA9hpOzSJumQoSwoQZ0rmDrn+6mj0Lqd8KLf5KdOuZhGfDpNahrHmZaO5uu E6ZM2ubtEgMjc143FIghXlIQ8e7TDQXGq+354PEReJB4/f/3U4BXyRatggVLu42Q7/4jc/MUufYE gNM0pGjqviUuZNJwha7zJT4OscFqOmA2420uVyyiJxLEd0ZNoZz2vtYZw6o196Yy3JHgrhFi+saq mMFPb8QN9BdaTRYxuG+1o5yzASuzZpsucRI6E5na7YgcYihPfjVTvz+8CDVXweTnMbOTh0DYfn93 cmECnd4Wd6BgVzUIhH1EedNbVua5qlLPvnayH8G9uHhjMEhhZ6VPcQEIzAjOUPdlM5EfSFd61Ezs J+38Cy5bblA6oL3pHybD4gLive5a7voZorPNc9Fi217BmkAXEy39hL8hTiV73jS57QAuoC+hALsu 5hemWjFpJQKGmwlSVnA5IduU51GIFmdf1VYuFuLWBJsp2WkX4Iw+vAP3L2MPPFbm4qibn6kWfAHn Y9JxG6r16vmzCtIpuD7+RiHm2t6Y7fp/sjEYezCEIy+QzmGCpBxy3LUe8evVYM+kgDDhonTTNDtQ oIRYjbCf6Jep65QC9SjOk4YSB+1B17ua3Wyen/SWk4dFLdveVQ2Vte6CenGE+fsnzUzAaySCCdLI JmGmCFF0C9uCXTMwkvjGIKxbQhNygRBdTZhUqXAYAdH+/t8qWG/CQkvV5MPNGSjwGCnZT2nHlbNq yLUcfu4EsqjaPY3S1JqQKHtzao2st66a9zJM28arm+/s5IGO37rXVOR0+jt8eQx+qobm/HGjYstv xcKFcH41b+JiPLNTakhabv1QtfBUHpa9nhv0dO6Qn4mPZLz7M9nfQ6oLVi7dtmfvcaCRgrC9rPAm 37RnmOne6en+sNElJnOahWUHxzxqGkLUIfOW9f/PkK0r9IKeSVQ6moMtoSAU7tHZKNqLXSU/rtoI nkLWhQXdlGjrQX0qIyNltlq2ksdehFHZVc6uABam5ggl1z7HZRysSrLen1IEM6T3uUJZebFN9foU hppWx8Ti7YOgj1eQm102D+F6F9AQyHwKq/8F4PXJVuPVT8WjHkgYDQqNTfqQiWz5mv9COcHxrcZb 7s1RiGoBI6bLTuyHZCUcDi9NEDOrun6kNhFMhO/GRKp2vI/2wtX4g7lDMgJmbeZ7ahn6e6vmToWr Lug8Z5R16Azv92XBfsSGGtuRMmncSmOWnAw8ioe7NsrrMQcA5zljVVkVD6b4nrsG/KpFa5qsMy1P DvCB25kgzVcZ/eHNEZ2LTDvaWbosN8mDZ/sFcSLrMHdiZ5U5jj9byKdskBkYUNc/CdPSWXvHzK1C vJZ4Jz0MTo2M5wDx3bxDotbpmrst4rOd6D1qOZtz+UNF97eSJBhKxDwu6p62Qqj1NV2/bAUrFajQ +42buVtPOySemfPI4bB/BuYWuu6BrW5cxCYOim75SUlmi3vYtnwYN1+ZVV4AolSIbfi3QlzfJph3 8btNrkVTrSuEX0ugSyF/ZV0INhp8KBwZgMbWuvkQlAYaDNBpD47k5t6hkEmYGDGbgic0GH9fzxu5 SzgHMXpPReGgiU0KRkU4KUeH4eu9hEF5JrXepjNQhkdNofMRvC/wp0Vo1HbhZIDNRhszpIn2VRtT HOOOaBIO1DgDsObcekUfTUoqCjjtDgSdZTLYGtgN9eABRXuwktgPnRtd+rNU4IwDihCpPErx6LwM ZTtePOhSt/Sk+aL6x9GvV8G4IgDgjEsvCuGyIfrKhHUMXpcmFuz0HsPxxUXQzWG/4FzwvtI9/d7y ZFKsSdLabHMoN4Q7LeMeXig+N7Q7iD+cJVEvXpn1Y2pK0x24NQ8uCzabBhiPywoYtX44WcJ3EvjC 8aZ/P4J+JOtPd4hpPUBO2dGscE8OqQktFmu8QVwXM8KZr8Duy4htkOkpjUACamtnUg8wphN1sHpe uqWF4aeQ15T0CFfVtSO+enrN4Xt9gePdDMjzAFTJoX2cgQryWD5J6XcLbzOPzpVosnHooYj/PAok PYvq4p3dDcWwFlAMOKO+H8bgVV0jkQNzBP1sVBi+JqAT586tZPNoc4czoFjKKkGnz0jIY5OQ0k0Y m9QMefKIkdg0GGmXzjnXyhKkSf+30nqkoWAjA/wqtT0ctFkZQdvrpeSVM2vOqPSue57WX3UizmEj s+f0hSFnZp59DjFCjxs34t1qQuz5dkPjD8lv3gCi+sywBDWGFeiZX+kCoBi/oDUwASQrVrXR3snO KH0kRyKmUXQPn98qPw4U/aakLwkP0NS5jnfOl8dTvnhh0EszlHyEOV1fRVPPXtiGlX91GNw1L1AU Ex7PnpBRClTsKml1lZ34zvJHnE6DYafp6/s9uejymexkGch1kiGiRvn6d2rKEJRoD2ABWWkgWUsl 2enWNjG4FwvGcc1Ss3qXqD+VlRrBnLG+1hjLxecCFm/xUFFIbQmmQ5X5hZvA3/IBrUdaJen6fXxV BpEobVYHCQHe7qCbUPir9zrwHyr9NPv9BrRBUYbUuowBoB4T2cp6j2o+WKex0dZzNrh86a+GUvdn MbUUVzgq/oQTmRdF4on2AEJBhNIM0Y554IMFP1Z4eHR3Rs0xUj9Xr6kRNV2jmlPtN/6WXFbw2YHk SjrfcR9JUAOCX7/UhMASFXg82USCCS8kAIu9cUNAwNzdTfx6XdjuYh7AglI2Ye81ayhoz5b87sNK Ju5rbcvHRHxRBecoUf0rbukldaRIMw0O21j5OYg6fyUHEzltD9Am8XNPeQe/sqy06VdiRHC1DAC6 YzYYknVky6c8WzwsmzVPCqJDbQqq0p5mh16umGH+4vsjc4fzSpakyO3ZyIWDWT6ELJYEPH1Jweo4 lOOOJ/6liZnAgLUM4Auv5Kg0xhTSFNESFPZ8HFGMNb7+xjT2mX7yKdOspyhJO40OjiyAQuRgm9ND T6idki/cRSiw5iV8G4SbC0UwQosu6wcnPDQlS1L5DeqX+eVnFTAaIhJGMQh3t2BGPKbMdAnWJ57l 5D99MWpluvUDrGT4y7MlHu5B3GbEnwP2X663/5sDlyZsFHOJLOj7l1mSg3aRsiIcUlUP19H4QTW1 02gbVfV2Xvv32G8HJEoYTEaCgOfwBQVZqRdMnaDMNAjYELmOtZyIilLG1HqnpSNaWarcqI5J6ryp sBdjetgvw+kj/7LX0zw0z1T8MJUeiaiXOWNyg09FzMtz1pynRvBZIDTcSNbINwB91/dsBvMGiqSA 8mk5Lgz6/TlwJ2//ELw7FgQHH8vL/M3w8HqP2mNBPYm66edNeGijimZsD+V8kUkz5OfxFrr+1i10 DzSrEPvFoiLfNPQGkkcUAU7Y4L42HqSyKrxNVGfte4yekvieWdWG/hWuudJRbj6Q/SEZVBKs4htu LnNiKPo9SolN7XYdmOj5eiCBn7rK8EGZMsvzy6ESm6rO75r2o6/e3cFTFgJXzg1QMAuLm/xst+s6 HZBQwDR+6vF5zhoXy8qcsSuBEDdh1dpzyIfTV29/FuCGokXxiC5PMZMO0upOyTfT747jT2zPu0ME YJMXQlx2Bw8n2rxGgREx+uw+jxZkuG0ehXzUggX8RSmYksX1xYShpHxdGB91VRC2zf03fXfArHb1 R4TLOQQnrJ+wEHan9+vKrIs40FN+TFAODnPuwBSeBHctW7JJ2JAz56oyvRGQmVYp9o7stzgh7FCs LvR+tiIeFkqkgnkRIIP2un9figmrwVWlLgxuoSdm3DKIYf830lN0lm/lE2m1umahHa/GnxVBPsBp Qo9K6Ff7yMeOovjJekOXNKEEV/T2gQMwqlDBVl5umUx5mp4rN367/A5hbkFXqCokQUawkp5HFD/t gViwGFEUZ0pYUL3NiepJuyY77ds2wT3QYqC+2iQtYuNbDbvJsHQ58gp1UDa7z09q+aYux/dm5ajf fnaoWHoa7IiOKHj8tzFfRjSl8CBWomY2RjMkjY8k2jCXNV79RW+yrlBf5zwGE36giUophbilUH9J WPW3XXO1/f45sIE3rF1Nm+HHweaqqng+CLPUEp55vfr3/OZ0tv3NLHZ5TtLIEZQAXmglliyqskBN 7Ibzwn9sPPeaHtr4KkDRV5FCKenx6RJasNjE1ODg/dFbHzqABhyQxEnA9H953Cfn4RYskLnP+Cs8 +V73f3TbgjB2732+TW0epRbVdVsWk+Py8tU5QK2kMcCQDfiGnjbDjRrcwNIZnL3O1uu+quZ12ntd sFk3cNHrRWmGJ8UZEFE+c0NemvuNiK/bTcrrpV9xgFqRtirVJopBM3pWONkpEY+uUp3dadPK3PLH eYMwC5eDpGLGJTB+YdNMuuHoQ5oHcvrNPFk9LhvSCHjD8YojbFzpuwxKXku27YwWnKu+rEsT8EBP 6F1nTm5cz8rsMnbzO3faqbQbD/DBq1Chj/8/ABwlsUc9MNrsmSDzdoyvrK5DxJhNyhfkigcrUb/n oJb0YCt0pY3wonl60+cg0G45NHc3G2GbkdZUQsJvnOeSesOHNhx7UzQNrBruF0gcs26FcG+VFYl+ x08eQ4yjwGJZr6jIR12V2y4F0w47/rr7Dt5DvIzrDX/6AqSVnorh1S84VxSwGmEWo9BB7GkMLIba UrOtK3cvKDq2SSKQKliNtSlkE1n+0e9vxYUo15NCYmG9/q9Nk62xB6vz68HhSWB6KjHoKrDDoI/p BTzbBC/ZB4Pbh321/uYcqiIJCzp5DAx8iSaMAEWXUeBLjvxVNSTHkya7Gt9/P5L2GXLNwcn2cqVS dk/SK0SRtuSdy3Gd5UVqn0ANdv/w3PGZKu8EbuiZCcw3XnM0/BjEMRyA70lj4HqPYL8S+FjFzn9t 0fPEQnyzi3tr2qOOrX7H2owWA0dtoe+p/yPY+wahQ9vX+CRRNq+oAAfJjag0o2OajG2ZnWuFxLiL anGQ7MQ28PHll+mjlJKURMeuRNfhhEtdaiiAikJR7sg7dkG+Bpx7U8XL5gAWmQQFLq1PMqCttqyd MAQdHq9NJkrUJvLAmfDAxij9ZfVtM0GIqG2+v0wtd1W8ny6V8HDsNH7albPkue45ZqlrVr93US26 1ike6ItXCmbm62NRKougqkdLcuHTgbGm7gZUh0+W3FEeKfU1JB8tb9RXtihaKb+dkxF79YzGwicc vOUF+BDoFFr+428xgpg0lmiOrYe5V1iBMqEdMS9c3hQCFmGCYxuplKTHSTqfrjwJu4+FDrrncCk1 N0pnErcS9MDMrqLaesDEcIxNeVDUl6FGllpcG8+LlQjnVTuzAqx4XyfoY6+PugkAwuNtQ3pkP73l UnqnjHm+M2Jwda3luamW7iXLOGXMmdCUC8Dw6eWS9pCpkgc2lmI+2LrSfAw8Lz21z5T5pt2BYc7i ZQbGK7Tw+QeNNBJv8SwveOll1taJzx0WptykXLeOluLbHk1zq+t7lACaeW4vwsIPoRUbbHBqdDeZ /72bwwl8YzS3w5Eg+ftxGO3Tq4XM+ZyRAzQP5MfKh3gQvv9211eh8gED/HIfjSGn0Cfxx0sbLudd CWhxZIjqm4W2QLT4svR6ZvBSz+3NKSD01Ki9bzv6t33Abu+wu6YZr/A/Hx1kT9H/YeSksUWrCa4G MJ3LFa2qgwwe9+azKuRgNivYY0wK9s61NAoLDUzKlND9v+UkqZVroYEtk29rn0nK6Bz1hnDRn1nW 0ht0wvNimmCadG/JtsMBpsSJHtjHADBWccixPr9lrD6+RQ24lsY3XubqzNEgR6q1ivfDb9wuiUNo mEBsTCHVXXviOkYGzxMWeFwC+M3XpN8EHmHR8x5wdJ/bQyCIpslB/2Dt1tZQqgHTUNCsJHKrlHmj p1NSw7uMD/TOVKxmfY0CwRb4rdQe5ITDHowzovfXJTvcydMhV4ss0Q+jkAmsQJ5LGxdwVqljPgqt FwjGyXN15NNgf9utiGW9CvCvxggGSV1Tby2wF7y9wWhY64B1u7UcQTn1dvSfw2TQ7Sr6xt6oVmGJ fN3+dQPBjY5FwFeY/PTl4z/IYLqFCljZ0hvkMTm2wx1NuEnO8N50v96Hb3G3ucBYK247s3/QJwj4 GeM4GPW+7amf0Wqxv4FDGuxue61ka4xGqPSfV+4iBQPzKO97DJe52qkZgvf+TjebizKznGV8XSCh 85WAM672FgPJAS6VISpj51albNramKmaT6NmG1bR6AnpuUSRiUbb8zie0Vzg608vRVA58mHpGqH5 uqOkWg0DIqZBfMp6d3SBr7G6IUFOrLspcBMroFxyDYgaEla5wcYZ2pqFMQvJ/s0inVtzE6i+qHko xErrJY0UHyVBeMLtrP4KUHDwZFXq8prNHEaANVMwN8hb9Z9A1R7kSyokpmRoUMOkAGCh3KXzpZhw +AUDagGhsITj97pyP1ouBGlFkAPPBOWeMSAlJ8lZlDgeva06H7yWs0Idx/dvYHvzE4Aes6f3cC8V q+/Y3Lj8To0apuuH78eF/XXJhmiY7sgDxfziNKn5Rqx2uq+a4G58O9H5Jb83hB4BPEf1EojeoH+k gCA+TikTMz0T3GyaCgxibk9iqHt+uWaasr8WY+Psw9+M0yx/uW8YMXJcuBhMDyjuTgn2zBs6ES4I BWsD94NI40YmkBsqhZPQgEH4MntfwKEpgKW7hmkvuvbBK1/R4/Q7nIasLHyxzKqC0srIr/Oxv5SE yNRNLr168qDqwvaBkTi9udraVY8yhVvNjI3EgSbLCWn0oD/RG0z3Lm0XmADqwoC4Eon3cfuAwFd0 5cfQiiVvctWo/jv43IxG+fuY+sPo+OEmm/mDH20AicV/RqQpGSEhuy91+C3+A1Kqg4EWNiR9cspj db17ck2TydAjGc/cGp0O1UM6pgpit+Q7QnkeEyGduXX4DLXQjhEBBr8ndHWWdsS5MsDlPvcNwaYK LJbD7ew5g25arzEoESoeUsHddwVXp70wdtqPfS9u2Ur+6kIf1kzw6GyB3DvZSX4awY5gOiYy2gYA hEcpuVn3wfbR7BOYPv8KfyCx1h4+DXbEV9AbBzs+AP6N0kiT8g5E8ZOLJktJrTXt+hKfY81T8zGB Hido+eLEpk3TDMbs3da+HtfK/uKSmX8PRnWeDob/0YOirpGTuXOG9wW/HVF9nTjGF99Ck721Kif9 VHdX1+BguNBM+DDWmcLXIElZ5ZzfXqrPSbI1C/j6vED3j9/E9NpJ3KDjHr+w5J5nPqemXMl09278 FnQrEe+9SVGt96xTZajS4xP7yc0uY0O423YARUkpGe+1TQIJgncEZ4k7a6x3arjmnsVSV57nv0Qb 3TlCGR8ewkdULZDE96FpZRxcJrW9XpEGH9+HFtWhU+3yvB9vPG43gqc/0quymIFHETQ7dF7o7Fn4 yn3AZBK+pi5Oc/G873HfpNQRuRHPR7GSz2L/aprLQyz2lfyQJPUsMJHGINzrxajurAtv3bL11JVR FzVotHau47e50bWtoCx4ewKT4TpxEOT7B2Qk6/C+XyUIM1xl+hAEMs9oMsnhNJ+TKeaVZLg7MRwM RrYcmw8JnE/giqCCJga2WGou891DH1i6csAZGHIo2ityHFK4RgoVsnvo65LjQZIvJDYu/msbAbTN V8gd9bgLxeLocDke619EKaSdv9xiCrhX1SDbJ2sRGnjnOLyiTHAvGA60aPxkK9w2eSSvS0oS9+B5 Loeoui6be8FbYdiJtqVq6r6S8qntDK0vFuGTUFc0ovPXMrc0VD/bY295tudfylTkSV97CVjemndi tBmZxwqbMgsSYjn8uYJOLEnaViy/GM1IaAC+E7XvENBUe5mq8NpejkjVV6SKlM//rI8RXm7ltcYA LhRhJpB/XDv83zOcpzFPGm7KSKJR6uyKvrWrc2W4FyRs6y8725FGp5kKFQdTjmtuoFiXo9QhtBYc pT6cH1eOiGyETCiSN+GyRE6VsDzIPJdPZv8SfTB3eVLZLtcyYBG4pIR52Z0oJbA3KDj+cHlHMnF3 iVGDqxkmihXE3zawMSx/EwtsUPnyrSU920Zp/h1GfwXzzzaW03KRX0cIRE4hW8DW1FamKDNfW89c cQ/eRiuWqiXYlaSIJ3lvIdLup0pVza8CkMLc3uQvUdo0S01ikqkKUvPaidwPIyHsvZkcM1l1v2j5 CwHzSj6DB1WK2oTakQKxksbSHwKIZS5ee1AxPweH2uMEHGK0J+8s8p46AxqAGsokEI73evKuHj3l 3iTcz7INulxLfJ2VDWV0mbkoIfou5Db+xq22L4iwkjBqP265q/VxaHSCRvIC5Bk9HkQ4+mT9Saha qfzSBy8Whm9SqZ/fwim1+k4YUt/YoCBi3bGdgC1BpZPRRUHNfsxQbTki8woUvNfSUOXHtcQFefw3 w6NO6s6dEurCqhMnED3kAVICXlYlPqehTayGgbxbj21QVjJATqi+OyTQCApX7aS4m9ZdWnhowENg WtftWeBqvj8zLsNcLUeFiqlFJolpekrK25ZYZvuABYAiXjAXhlc/aVJV2G2+s18aTDoYHZLM4Nny o228dHcN2/4cWoscd523vvNpq2/bGr+2Abao9Lh46s2fxiSX+/Rex2hublvUx1pPI4b3kYyc3R+G PgRWLh/NiauWGt8+FSGoBWRs4sPkLcygRPv0JDIBHYO0NbvHCvRlWrnrApjnjHUiOc+aDADcuYpf ijBD5h5Gig0VU7qLeOn9YSPk+RTBw0mDmGWwmX8/l3uhMnAScn0oWcCSOT6BQVhQRL6IQEuuRVR2 HOG3rKckD6DgqX9yO6bIzeMeib/LS9yIDh/LJm1E30CZsxIQ3EKF5hMQ/+zvltd9VnCY5gRSKskl sCa8CdKe6dqpIFWIIXfzN5merCduEEXYSZIS01H22kCoXeoqNo+8cTkH8aJk8vAHVE5+jjDm3mEc GsQ5nW2ZYnDuREhsHcz3sfbL7GdSJh7/zfv1lI8spXpdebDCHx4VuHm2OK41DV2bv3ovry96M2ZS XBHuKwTFwhUQ0ZJBB8/NgC8Y/PjA/yRhgUpBDeiUc+cMUT0FJF8d6dpeTLd3+vhLw/3Cb3+r0sxU sNKBF3+hRI//D6ueIHGqfftwEBNWzm5dreraygpVBvJZzzvqvfCRJBmA3e643RslrVLX1+3R4DsF 59QhUezMc8a1N9iic6lIkQ8U27vmU0rEdftb0urdWkKdPv8xJ5xWyLBcEA3PTRFu9lM9u0I4ZIBC re0fvHR1rye8UOl5RU5VmZ91vYEs5GgnlMoUJP2OG3IE+h6y71CO5CGxGjAO6Rtk/EqW55oCIzos dac2CgfiU/E7LrYBWn2lwqE9UYhaquncE+rYwNLJoF1r1IVhlU2nvJAC/uv72NQHhxgUUPkShUVT SBz3kte0lJ2wJKgdHqaf9KiuUUl91uH1HCjVbFrQwB1P7NmiDtQU3a3Umws20Wv09csyrLh0cvwa e0eMOICpJugHdBirkos0x8xghHV7xouVBQDB4islChQGY6ee1yhM9ccDaspPUTQuLRcDGGFKgmo4 zIRhvFngFdorlYWL/TzOGTam3X1YczU5hkq4SpFQEKmCmJ+2DnvggZd12/NQDZQuSVl8QExtIPvw ettfUzIHkv6x2YaQrWuz0au7pGrM5RdMqacqDnlPbYTAeP9zELuMyte52TISgO8NdnXYUk3LlFB+ RqHsRT8nbYRRmGTttRdFylL+p7U4IFV/5uT7QfjJpzvJVqJ0tHKytvnb90/HyN7LX0w2/sy9gE93 A0z6hoBSAYDafYH001/bNnSSTuAUK2DZO1iHY8gL1GJGCUF3yRoCkwicp0+R6VAKhNEb2UdVyB4r RWndUYJnFVnoCdWdTO05W1/mN1KheyBtw3wh8mfnaser8Bv+Xsn3gGVHbRTWxLZhS7+ZRb2sqS2H CCSwY+xZVY/CChWOwWN9eMOKdqAjC/UKM4dO4uZBlwnRjjoMDaa6Ie2eTFS2C3mTWigFAg4V8PYH 8c2WwKp26XHA3S7mxNgzZKXpCb0yndinTiXE83o3QyA3ZPVXS6EnVKuN+ZskAlS7OfEwWqpylaef lfAYOLJJn0Vb/qOsuqmHI1MLI1x8LIYlAY3EFaQJImY4MpbdZFibkFugr87wgJEMyz5cvK9btSpI RSQCp1uD7LNMK27nrnbfeZ8T7pO7D+HY2ttR6iT+5HXL2VEEqyrB6nUFtxk3nq5cC+Aumst3e6J7 mW/GDEYoj6g3CrW2h2ahe4bjVTzzkqwHUh6kwI7xmOoiOW9WXHJbBDWriaH5+1AMYRQPjT3ad0kH n99HkztvGdSR9cI5imYYYuZoBmN1F8xz4N4Xz9O7oEQ+p371Y9QYr43e5UF1DOCgigLg90RnIWPC 62tFMaOJlts0XujTXRMPD51KshfDbO7MFK1L0Gd7zQYYas8I2rorKn3SbEyV4Qg5Xzk962XhEGSw W+MDCVwknUSY3D74VwcNaUpzVU3RsYbuJ+iXOGR2n2wcomlretsG1wyMU9K4pIRBLerfJ5PyTfHI PW4G6popMGx6skXC5pug+5llVUI7q/ywCFHvss3csuEiRZeQw5eERkZHru1BP3qBFZ3jEWnxcLVp erize7IgXYlygIZFjtm0T7HsUeasqrTxPfNE2BHgn+t2t7OVKbSFmAgrYldMWKgx1nOSoicL8gIS 5SmUPmJ9LzSg43u7C4pRPgt1H/jgYNrza/Irv6acVG/Mn8WJIo3Fimg0/QDFOtZqnrsq0lobHYHn 7+9ET0jw1J2TE5DJhthBcw1+3hu6wHwsWoeGL7uLbHai9pm8b86em6UXgPheCXUPNoUcyll9pu3P ewShgrBy7BAo4bCrkQqVt+j8ukUwqsFUu5vjX9xhSa8KNzIhsiz7BFs/v2WknFloVxFX7FFMeXZm C6bOy7i0KVt6BmIY00QYQ5tnW72fkGXWBDWq14YDRjrgL9EJVrefCCEqSHRbycm1eD0qAOQrGIQq 1l7PdiTj4tCuftTLF47fpX4SKg3u72/7iDHA6nVQKQzMgwBqieVeBbMFwC+oErh/lbqniJ4FbmH0 BEiylqd6VhmB+9KR72V420eyaRR4MkxpbjPhkKmOyczgTOWBvbXX4MMNNrYz96IwkachccgQZD2q hbcseiSK4ARlzg7cwiqjPrk7jz85WA3dDqd4gb9jhJxDAVc2IlETCbuxFtLRSSxOK9HCh2EXJOoy nzyNJBY8PkImT65XaRSNqtDk/p5aDjkw8s6Upbz7BVWf/l5mzQdRegB4aLMY8un+7+REkJuAxNG4 GXAEpvFJhVA0Hr2C8b4f3kFWeCuQ7La08PBSbcAaiHVBYWOF5P/rOfXPEgHQ82DNifRBL5vFk3IN pzPm2lMXylzS3su1sV3YsPkVBB70MQXOskw7pNTsQKKBlkECZZ6cbJaEX7YbLUiufiTydxVQ14Dt Bqy7OQzSLyVxHeGFU4bMeW+DhdYm2sfJeKxWBYHu+fE0SJ8JwDH77oir/8KJ2sIzeCoMoIbFp6Iz zBGAGBL2IUfwsXT9cgUzSvuUQLhouvRW8SEOqTyTV8+0GDQkI7mHaDgdE67N62H5nhET8FO4gLWH +vhm0cXitJn9HfzVrsD22+rlZYN/cu7yPumSxeVB3ucr/cpW25JHgQDD7PD1iLppHJT9ph8YtUT1 sCVq+NbZ8ceN1fRo3nwvO3kJoCuNpzO4iqoW3605kUVYkRRPp589g6hgTGN/rbPjm5HV/m0LrMss vOsGmPMCc7ug0WW8kifJOsn/svr6NkYu1exDXcOWQfZkhgtFPiEqUjz2KwhWe6bZZvWUYSHQwZzl +Xt6f0yM8keKVLX2t1f9P02rL0CIgLJtzkdnskJ6Yk6wQccRX3gLSweYw77R0+nmu42y92YQ4/y/ CHC74ceOQL8Jy65hX5vuGbVDrNZnIWUHQylDlX55XPU41+5iaysrgbsMld2CZFch3/JgXwzNvhTk XPlwdFd8suNDciaM2IOpmMYeLsUb2NjPkFRj3fhqxehVIok2T3zMntwGDHrSzMkW/zY/ybgbgdrr ZNkqsoYpifAZqdv0a27busO2Epo94LOitULjY8HIsu+tc/dj6anaOI43GdISr5i2JK98+z0eLbad IaucpldJ1QXWPiuwl3hIGKd5+oy1xTgpOinqbYqZ34YUirTKLY1mwveX8EQnW/ZfUGSRWW376Tjf Y97WpI60t8rlXE0ckwtktzP8RE9MWnrPf4Ixz5Ov8xlMEL9LUoDU5n/MoiQuRYJHLzn972s/S3fu 1dHeb8Q3dLxn5yWovnx4psE2l5vxqWeAByMDKJiBF+2IDCkarkajfR4ioukPM5zPEj71bzkn6Sg1 WIMSHhCnZSV3fCFY73rz1PBpVIFhWqOAc/ht9GWYNtP0PyY98+ScEke2XWkCt9GcCyXUaltLaac7 1jrLPmVl6s5ydOY1XF99+T4Kyh7+GvZdn3el3ARflKNzX/YWxFedSuQeh4zZQd5JDeJOe70OgnJW vZ0b2nBZT4PTE02ppTiYerq8f2+CmnCB5lcjj/WSALJDjLzblVGPtGSfZaX4LDi19GS7A6g+R3M/ ly6vfjGeXFINUPRcZe0XdGRuOiG+4cpWGdDS8YgtM/Xsik/61Cp8H76qhToIJ8pXVFrgoGyEloU3 N9E0Q9ZQex3hwxA7T2SLPFJNugPij6YynKsqGZJp/mD6SbXH8/UTr7DlWYmxVejd1fcgvH3un2Er Ytsq6sHzDE6watRSITFwgzeNKrjH0qgHZxpXXWNvdrpxlCr1BTL/voNebZiYxOPb8Esd0xYI2cJo BkzxVVnO1A1p8zBna1+ZFEqJMCqQgngWPtMNpw2/4/hZiTtUos6Ogmk1IS3wtI6eswLN5TOh4rHn W0Afcljg/SCzqPaCVae4GPTsQ73r+AcrSUSexZq3Y1RRHaKVBU35mH/2JA/lHEyKND23LVYoBCU1 A+Mwq/KTH0ZUuzaahHH5FuqwkNhNpEoGk3o5K8k+IDpWitR8NeSi13zmK4lzTLT2GayURDv6xBnf 2g/bOVo+GvhauwpxpU1gEd+TssNBDEqrxS+jNNFUCX6q4uD87k9xb5Ct8UMo3jVZFgII0Pu8jBkg ZKzW8CMfVU1C5F7EzUzDh6FkCMUkPeMAGEz/o69FHuNahoGhL0AUF/xOF9z9iPu3UNOQ0qK8qE+u 8haJgu0knb6oBsz0OMVDtxgTYbyZ2LhAkSgLWtQvY8lSeUjqmz4IDtbx37bn8Oc9ZdImoNphBOmm VvUm/1b6Fg9YyuyWYzwUIY0yMzXsYBKysi5GDOLjKRIQrpRa/bmiANQQ8g37e6INyARa6qCBowdq vTgzT1TeKV7AXx49SGvQv83PXqP3a1GXG7lVLASqtwWVeTB9AdG2SUp1SbY0C4WonhX+WttWhl6g Ok1rdP7cI5aAX8SX/Af5kXDIT2jWWWO8cId29zYsva8oLbnnG0ftjujMDLxsW+1fHZTeWNsPFITR 1hfrTeHpqFMQzcQ3cJ3MhtMN4dx/k9MAT1jM4Wp/RBbrrq1OiCBo4HWrNpJ8uuu1tT++tvdQuinS UVnNNokm+fIeE1D9QDgJO86oYBjlbSbxyejpaKN2wd6NImAW2rhS+pb8ikH9iB356RBCGtJU1cFk ojzzxwPatrdB+QR97zVLVCgLKYavcQOJqmm2cIpAVbM9EYxe6t3hUZfNZLDZD05T+pEBwZ5wTew8 HpCDYO7SNUuiIwQddjxMzzhGPk4P8NHIiEbshTkUriilN/EyEhskOW24yYOPeY/o6gn0ijnjYJI4 CrGJIS76MiBfp7W+M431ZJIKYK5b0HpGj4MrJF25UFuAuc65vxv804Kxv0aRaQFsM/g3P4DXnpxd WcckqxIeAVu/foOQYbgXf8j24eBpvLGsso0elgLAhS56ccHKkKbDlPnGS6qA3R9B9WIqkxtghKU5 Z44K5jA7DjZLENF/qdc4jmzBqHZbUvc12VWqFusU0Z/3WWQxjmEaYcC0sjvWlrsPGErMSRFFTujr cf1iV0hAM3rkVlnobC4bU3Iw+tcu7MN2H6mmO27rFItkDYiYIr3bIsBTEmc2CS3Qgvsj8TtUgS4l aVhkWwCL4Cq+z11oQY0y1hIIKqXDmuz5BtGEqXHCb/Q2b7tQr7PNBkVxQDFaYRw0ngOlmXHdVzCu r7bBOo0O0p9PkOIhpBeCCrtLPqJctgYe3S4D8WNxPs+/aPrAPSMYhnwD/KB4lH4rd3biER31emm9 kxQtSQ/LhxDvR3Ba/CCZKyLcA1baTowRAXsMqt0WmegZoeRKFeSTyuk5VUwvYhhVzEEGdAzzDMqr Ifag03Amfx92jJ1SqV4FCKz6KijKu38y5yMcxs6/ULSHpUxs6pYRXBDNrKDofpVqduzGBxt7RFsM Tw7FT3MjZPlpCDntm+x4HyJB9LR2ToFJbbMHnclWpG8dFG5rfR3WuDYGaRb7yMCQejHDjaZeWu9J seeM8mw+stFVbUl0C1SCXPZnuJLh7TFUkWdEQpyuj6GCLL/xcSUfEXatdQ6/4Xj/Twbts0lMKeXK dvZO9e5oKDhrhkw3Oqas4tOyS9VrVK0/qSH2wpTPAcdGtzLPLiR68Rvvn1F2T7BnKS7gHYWN5BtG py9PJcm9K04z0kkovS5kbrBb1o6CaeEhzrKQA9HB9TCNlJnhj2vjQ3pRy05KHFumSu2UiPq63iIZ wChGO3eGnPUnnT6Cm8w+IFSJIjKABVXFxlHocHYcT76dNOHGVbknrV+bn/uM6opERVnFzfio5776 gk6RDl5F9YCzb3L5db2y7x+6jHiKK+YxTRLBm/RKjz9RYDhq1R6VONwkhUxZAnCkFTIMppXkoAnI TUxiqBRYz//MDQQbbE/j2rzlYUPNG/y9nFDM4Pkk3qVtpk160522jvgOrDk79IOS1LXCBg1bZtn3 Dvos1JmDYSFhve0qz3WTec2uSkItSY3nnhEHfpOrzqKtZhfNw2nGKrUSHsWEEGYl9LygIi4ZA+fz 8fgs17oJBrS1cN6MGucbOI0APDPiDTWjY6eGbj44jWWbpF8EJWv2A50XkyN3hBMX2egCn+ZC2mfc hem2Lx/+pEi6eMZJx4fuSLa8mmTrqhkGBlWq4WGbco7thLSBeLLf9VV5/lk5P/Uc29y1FnIViQyE 64YXQVOaHpFBkYou5UNrPXtAfRgRfXm4JLcNzYonvFD1XNVtKvjpI7MQecimhw7A6wER33IFR3i1 wf5J3S5IHLN2TvTwKh2TUEghSobZLYlzquQNWah+dPFXSdY5t/8KubqvpWEStAbP1bh6E9JDIm3e QzNkZtfnzYFcJK5GXceYQwVOmKkvxglM54wNEp/xBow28dxCnRD357OS15NMw4snutREC/OkvX4D 7R8COIKPKXc7JU47GrlE3Ex48UwJ+fS0QafX/kueaTeqrGN3YeIkvcgi/w8JIadUwaZCy4X76a5u Fej3SYnXSVjbjqsZIr2ZREZzLR8wT+ETEo6qc55luqjQM/HO/X7bbEBLNmb0iUX+hodcNuvdjgfw qMiX5/XSQKtZNOnNpSztPQz/3gprqfLQN6NVIP9cIgzAbpitjyi2WRVLr+VJobG0SBQTLpBlvZS/ CJ+lJbRDHakKxP39VdSNwvh1YtkEvyBPNsWJtP1RQmy23CLX01WFc5znuXDvJbCwWwiwUJANk90c E4DeiDz8hECTdXeoypQ4+mH2f+FVnFYwHR2O9QFj4Kr4TnbTCregQSUsq1lG7oRLrRfd5iz8RLjD Syai+n0ePzHEwwMXRz1yFNuq+kgdhov5Ty0r9WsQarX7KtriVFRngLunuAv1e1RAcWSlMXoJj8Dw RTJ/LVCZ8kqoYdwI6XljMpSA9c9GOqtI37t0i4D9pt9DSzibz6IYdC3mQTDpPCS1NiQO7bYz8gTl HU4e1IODZn2DswTmifBrqO395fKqstjzjjw/1GUqQDc2Vr6WRUkbmU1bXXXxI8CoLpfbTYVzQGy7 nAN8IlC16sTapIPE8f7dZXxZnpDgR0Ef871pyffFiyVIEi9EnmBWCH5/oEC5YHL/hViebwhJVqJG l1RyAqjAOlz0zGv5ww7rO2ar6VCnKETYHpVBgF2w/doOgBPZhZZah41CNbyDsguwgs/JIEplF0Re Ciy9zU8q7kxULbHYT1+VykKR+H9UoP5Yw3wmFtGifOk3uyXtAq0flT/cKEJ6oSVq8kWaspbxX2RF imaXp3kJJcOrWQ9b/RX/zMq6eN+QwJluTTqQP2Eu61/o+8lyc3AxAHwSwW8YYDrP4jakiUWpzeQ4 EbK/Vz1iaOp0t9p8tlN4dd5+bhhCLGrmhcl9vQbx+oRUlm9FCZIAPCRtYObC5Gj8E5tLGC+zuoWa W9jNdYiTDVv6pRdcmijx1yD8fuxHGBsoDguIQ5SVR3OLaqOg3YI6vPpJ6zXNjEpN+NRMWOe2zKZd M7rwd9mC2mOUUkEoOlw3y8VUUhYhHkHwa9uCx7b0MWzVE7/9sdJlKDvWr9/Xlso93P3RKuUfZG+0 tnsLifdmjgpZlz2RQO4x2aeX8+oac947hAYaFFBFWhGT4qGkr/wy+ixtc9SQAT3Gl30lonbXA7yW k87gXdNAx2NTYou2NR87MFzPWVpFVdG5OuwsSHOievVj7l3fcIpHkvbcmv9dup3bdHch4nbuvohE xQi7/b/NkKIUuFw4iS/boVmvykr2lSZSw3ODowB5IDkHoed/AhdDb2PnXhn+NzuiciNTmc9cj5FK XU4t7c0DD6pNZTP57n+q2LnTOuemWdJg6tJy0OPxAsXaFd29mkkaTzrlNBkNhKPW1UTLt/J14uzF peRmdQFPB9UETEuDAhQDFuJ48VzEcoLMmCx5VlYxLivrkENu9Usa1gfx3WYHDA67H2DkRos84mGt xsoqk21xm8WvfEkjgvJ0fLT80QXSFa/zJMDv3h7lbMlZIXb+oEAc5cAE63wCBRDTDMyA0WbcFz64 QTQ61THD1Cg3SMVNc+PgQzslcumo46oMHvhH+mtU8eOEimtRHZa6K8fAOmpU+jV1m2SAqnLpKx8F aKK3iPeQ2FHSYiodubinij7qtqPsMsg+r3IiDSgwL2kdewi5EfMSzviVl9tZGGwjVEIhLVJaaTFT jzfUkbjxKzpicra/i6jlo1sfSEnDnWVh0H9Ny/rgZlZtK1vXfXzLTQNSpH1FWIYyzDHbAlbGSMLh qmJG/cPoEIHHRTw0IBH0PyjCmXTjxSemQBO9q9h/o2iqqEeBu9a7vDBj+RzbaZ74VHqpW1jDKOlt JpWSGu6hkbGuL2J2C03F8d8GJi4sLQjIInWfjxmlIxxDm8O0VeWIVhW0v6xmOBjw+Pr9uIDiCWR/ 1IWMWJdbu9mtssvON0nD50KLj/anXaWAENpM+k6YVJXOCW5tm1tSDs5GCVH2czRV7dW33HhVaMVh LCSi3/BalKvlmQe+HyV1qsX4U1KnOoe6FAW/WhS3XT421yiGXJwUaI5uNYH8fSrw+1Nb+vYm5Dtd BhopprGibLTqmyThR67DOpUhG/za54bFMvL2rtHrv8MmiEx0LwDcKDzgV1rWwMtOtbJUWZLIP1N+ fkFLVBBbBawLc6NzELYVbwvD454REUTfacld0tY/BgeWUlzN3AV9r5KbbmPzE4SvgFUhz20rwIwr YqQ1FFKOhq46gdZFRl9qt4C/vhLvlL95bwfyday9FnPqSH7EDFdEPE24TiIxr3U/jPlF1JVR4s5c DszAiW9nrqIpEvZQ3dFCIL6QKoDhi2tP7Bzls9p1jgNw/LoLifV2+/cFmOeOJzjoHNsLHuXpG/uR Zke88IRzpoYHb/KwcUvUXd2XhMoBlsbbjWvdFeW9TzdZy4e6VitUGoylV2w0BCjxbHSH/6lqZcp7 dvXhegS2ILEYj885cWrD22b6XYowLRNIFxJantCzR3IXB1M5QgmNAnVkLqKiRI2m6TfO+4NNBN7y n8B3FemSrK4E8rm8cLDVJagwBLJRgBwZ9RcKZ8NCooIrmm+rJ0RX+54pFQJwKrr4aRQ4ej8hYE8o oOYZB36tQfunIsAS4vFeq8TzCu8AEG8VyvVxuzSOft+CVST6j9suulo1bPqkU4WH4NKyt34L/4up m46LRI9ICjff2HaiAirDJB4EPd0MygR3tdF/p81LFaaHKclPLwqF2B1JGEchnBDDf0sGFYMJ2ap+ h82trZne+XPWrV9JW7yT0JH0ueGlIys18jyVrQUbKfB9pENKmFD3t0OJshATBoBnDUNgpaXSrSWK g9zImmPnPZpfCJWGbatwQLbA0Yxm1yJGyq2LVfjU5HDY1uM5wdU9pglUc6x/mo/T+ZuIDMkc4YtK 9NYyo6R9CI3/CZoHLpOjNUloWe20Z9IT2z8zJZBc0aJxhX+SIjt+6X8Jjr7XxAiqXLD2e6GBazjR /0ffFLeLEpR8ghnrdhMWpI16dmcCaKkDKNCohWFbfMIoj9FGPbdJmD4z2GEUnWRw2kne+9fHWha3 H6+JmuAZ98nt7eTGcUvYg0V3ErEK4cpe95AcEfi4Ps+vnEYq4yWN0mFzC4d4wbnYORDSaeA5t7ud UNBjn+60SP0XQIllRhI2j1ELvXv/ILVYUb+EAOrZH3eTBqAr8IxUtBrc+IITVFzrFaV/0DG9yN4K ioMXt93r7WuSLAM2ckCaVX5JXgfhgSpL7Um9T1TyGRAMk8CouB8QuLbGjRTTE6okWVtVTKwN7sZV tJA+RoosjeRZ7ci1U9dMk+2CDx3YPY19Itqk1hrjGLqoxjmt3yMm6S0r5bGkQax7jGYFksustKtn nRV8xMk2wjXNhvntw3jR2sO33KJ92mBFQT6I+hG2SqxaecpK1xdH6LjDeBZoniJJR+E8Pf24OjWa moDLFQBeMC2efbC3ANuWmuakGE/G/mWibRV9WgN/OoO2n5xHMkBuxLpaRhJaNvmFZGdSrGLXwkin TgUBQJZ4p33zGqfHmhnE6cwyTynR4PtmOATPg76YjQ9du7jwyp3APGUVh770akXKFpobhA6uPWHl 7nRyKIm96aX70nER+CZHVRpR3MK+rM+IczK63nGhURJJqT5WI9whaSER7GywtesUV/uzyWZo9LLe Hc3nFIrZBBJQG4rtqy1IZeL5AX45HaFOmZkThOuBf8XD0m+7xFDU/djYv0jtGWA4LsgpP/R/23Ko FB0ZY+LberVBLcmBf7kf3vc81UCV1K1kKo1U1faSYP6CIzsHjzT0Dh1vUE+EXZsxyZqYMXMpCq+2 oE2vNT6bj6ZpZuznqc5v+d8UDKtalSSVIRIV0SNKxeLLH0x8uT+4CRQEmanA6/U8vmjce5957htv CAYgT1AS7KwPtY1epAIfK8+s7lM9EmPB7zBuD44MsRfc44p3kA1U6Pt2N6VlQKQnghjHiYA3LqRZ x8zTlEOENqhlJRPgu7sRavLBdGZJYheHcyOFsl0rEaeffJzj5KU+Ekpjqglq/WG8Sp9TcOicywWb K+tEpE4c4zTt+50fqM9N+m4e0kkmuPMxdOYkXc/A8WRCw2dd8qGC9GIVDkO/32HnRb0LplQyeIaI BQEpbZ+fpAS8o3s1nmL2yyvj1wncHxbVWBCo873p06XvDbk9vD9C36sHM+MpPPoC1FayyvUEP1So 2GQS14wLOHv9vAE2KtBjKm3qP7vPR31zZJT6ubXKtr0XmMEH4hkISghApiCvLWv5HED10VqXjbYP J58D3peSr2iU6uDlyz0MQu20pDXL01zoXsl+pxR+D6ly49FIpT1NRlxeF+YUptL2nWFObE26fwz6 wbmm8crRV6ZD96gvGJfUMqXr3tAwkYqlfUEwZBwyPP6sL7ewxE3a5DLelUhMeRYnJ/uEQ5hgPs8I JSt2dyDaXBWkEVdXj276FyOQCOw/MmexXwBgxdQ64YPzH+5OP8GOJeE+lFvZ+MDJywtXmVSR089A hJ6nvxGHZn0sFd4eTq+RCOaBA/B/xUKuCESGUv02CHT3G8FzB4jZctFWNVGOHLlRhIQo3k7uwLoN 404yedjMC0F3lZeLH7Tf0DiL/bjoHZNJjP5r3UyhQQdSbv4j23GKEyrHKpSM3ILuv824YTsMIhAE 2OndMpEDFVnyAaTTdUYcmRNhEDREcR/qij6mztxKfhQjai0u7eHQppfEv7t1IAvqSKYPc2cK0Efb ctuGQDIIEmh7zfHCyBDgceHyc3UI8nB1EhL75xcZy2ot1E4HfM/+RO+hJj8qnue7gB6UjhR7c6Ps w/2EFPZH8L8QAx/CevSv7hAI3Kv2r/av46OkcWELz7oz65ie6I3NSOCrQUoTiPSuWgOwLcJ5VsuR iwGT1S/4CN9LeJrTF4YjM42g190Dk6fElShM2tU5tLns52Eqes+7grn3M6WtlSotBfZuNyFfsnaM GFY/+1dfiL8bxpaBTkZa8zKVTGB770Of2HR5q9S9VR7n4ZDoBsFomew4qW+CnNYyC1Ka/sG+sLPj /cGL869uNcJc7QjV5pJYkwwU2ParVVDeWRAwYxlUYY0Ax3bKl+7I6DAPSzM2ZPmSz74JIQ2enw70 gv9uavYcB1tc6sWd0WKegWTfTZ5GmZXlR2Td9FVdyMhYwn7qg6CpztOkjyoJUcGxaYXvB7CoNqMC rylsHgGMTlgb/oAPpr30B/FJJS7eNX3M3hrrQfPxjw+DSP/MzpVc035TBXNY66/B+MlrRDUaBb0C 0D9Ar8ZqpmHtFx2mRNQusdyyGKPyMFUgbArikhB8cTZ1hVACJEzRC1xI1rldtgz4VK8HqZ5AdW51 VS9QIJ2HTRby7QZ5eCf4SBRqjGteC5XXRS9vioLKAbmqZyMifstB3GIxjJ+ILYDaKipSR9AtpHnV 7rWHqUkDw6DTCJnOWktespy2ZiAA8xzh53V1W3H6X4NQtMKtoJzaylI2kn0TWriO4RtdIs2W5qEd xVXL5mo3yd+n5a1cqwsNZumkOYjyIBG6qbuYRzu61KwHwWd78F1eBMr1Z15wJUiY1dhx0HgvH1x8 kOyIQeNUkFBmzsST/+Vu9+cMGigtaoshPUP5xXgr57naAONWN0EfQ3yjjJCoc81YGL/f7VL+cZ3W Cr3S9lcx7k1KYI+XfDSmYiepm5L8JjnOu08/3VjiktkLA9l47NREg48BksyXBRb/ZxkoQ27QYkc+ jlBq4dNW+oqdHgWyPnw9aFI+gU39Fxlbr83wmtaLWgnquYtALIYwAxoX9jf1Yz0hrbXB9alJNhfs drdQjlN8ombMJBeOLuc6bO03yVOAuoIcee1YwjPr8IvwIrhkohOJ74MzT2eStbAI/PRRcY5mTLxI P1Coc709SsfFkninwaM+Xl98UbOWT41bZ2/v8dG540fVj8Zy4uKeY2b0Qx9xMo+Yea0iK0vye2Iw 7bjfIICJh16Vt+vBbmaGdusjoIx9y4VUxaAP79yRR4b2brfximPFL6LrNF8Rwqs6IthAIL2uVS0Z +sI+pZi/Y4ifsgdVj4RNZPkauqE8jrLJokND/cei7sf4gMD504uDqVu21oat4xGSatZMjECdUCxE 9brRCfJMrvfYIuGEuTuu0Wlk1W6dYo9p4aa94nXCthcxr5GJp2F8taMSc+mCELPoIKy2GdA91oxl z7rVGVmlSSbFqX9PMAMNmmuQALAIJrnLHpPYVbVpZiuht0ZZcExevj/gC/v0TOrS56lfIgggzfBt WCUiwxedmmhdKS5Ct3jwNWDCZxaWv6Zs4LI7ewod/PMLy/F/mVIWw/YZoVANilghrGXbh7gfcBF8 B7C1Xq6pDevv8zSzQytiGubBxelcghqINFMZXDvn9Lx9Hmk3AL5aP1PKxAVeVUX/aQxulgJvTLih b4G2x29NxGXAonwdCDp4g/3gxUwDJmWGct35oveW27Q6wECxuIGAKK61iJoU9m4uZXUnUlcANi7y wU/wbaJd12Mmi2l5tZ1inuJAiecxNgYG34CNd37D4cCddMWE8c+JzsOYmWDFqJXI4q1zZKhD0bVP VgHlUeHq/k2WCK4CjkdxEq+S90YENJhGRXHOFP5V7FyNaovyrb4iuWO8XXq1zsi8gIt/T7VyY4VE OBCuwWpLY8k5WuNB7xVFwdvhQqFVNjHaF2nLYy72Txjo7gx1WGMeqmDJHQ5VJZqhgB7fEt/bn8dp zYSH+iOIdujO4kgMqy5uI6vmbT6Et4CM59HvQK2J6J0QZQ8yoN+7U9wvAF37fh3BrRh81wq74jc5 SrHUt3tG2HTT8ieVqxbPCXB5alwuJYvyA09kZ40G06Thcylc0clyPN9Yte0I5TQQC0xwPQqV0PxS ZYnO81UMPY7VgCdPKoQ7rcZDbGuBTgB7l24BlpX/6nGfVlSibS5Z4hK0ca/t7Dp0XXMttN8zp+hl i6mbdrKJgcNDy0923GvkRxV6wzTenHhTuNfrHqFqqZS3JHEA35+zruI2t9CQj2Fk1z8Yl3l6rnXB U+Y42fm7Wxq9ZMaaCeMADUyiUFfJ/D5UY6aDtcwVJmpnP5ppS9VLv0drg9I/hP09aeWuIcRN9wdI imIqghiOPzm3mvJDMA5uJIivlrv/6ACh7lzr13K1NQeo6+9Hf4DDb/5xQ0LsxQuc95iFriHEVPDc cFuOEhiOQ9EXQsTM09CwhidXdyluTwfP1AXuRTVk/d+OEdmz6O7Vfw7cxDs3iz86nQe3xIFf7fkl 4MqKU74S2asjvTDPnyMbMC9sL42pf7myY1LlWPNHWQvBKwlOiuRPuI0UUQy0pnwHotopHlB6VJk1 DnahF1Wt9jZ8T8Rh/uq4kvC61DSxolJdLnFbBywtslxok5Dp49xeOfoj32X1sL6na7gzv9HWgtkn oHwPti/pe3q3UPTNryKLO1v9b3alALpub+pi2iqOywhrOk51tYqSyLjEj72jyhaocx5rIrkGIbmU GtsGPpY/Jmjs9AdYt81JOtPQNTEJYs1UcinXWHg7tersZnJGFpqT13J1tyb8MU2XRQ8TIdxtrvG9 Zd71zjkZOfnfWwUfwb41elUvymTcn9+S67eGRjHhE4jTtQzqbeZB0bRMhb3WwCzkAsqihBRktMxv ruCxIQE0EpMm9R2nKeV/xLAS1hdrwWAEuB3vzGy4stNhhezZWa+C5y1CaCTk0aP2F3xBtV/O/nA/ 0FznVuGI/3GT4pkPVhMtothIDbCIEmZTpJoyK5huK6YuZ1X9/kVQm6KuVFk1kErwiU7sIkH0JJW7 37AgDhKEGhyc1e7gtB7mErOEBnQh9k/16o/Q6N5ZQdJY7h6KOzA8HvfWrMyY/+Txd1w7To1cqEfU yZ+uHNsaTOiBFQpwaZQwtLBf5dyYXZT5LqMaYos0pO6xvAtVk2UM5ROouzOwnK4yr2izKN8L8jUi ID3F3IUCwpR+tjxmAAkeL8OEQDKQj2XFFw38ehSqGWNhOMEYNsNtsUAiAhEBQ79NKie1qERYqXQu 1bbxFk/zAUoU7qsSNDvhKK0mWlqPi2I4EF+bbwQXlFYy9zi8b6OOC2K6zmv2N4Vxt2p21RjGPEGi 3eUiR788krYCqrAIjWhtTbKVXmeYmI58UaAVwoIzHXpXHkPpxNw41IJ+0Tz2W33YUBH8BlGrhM/M JWysJwoDpS2cO3cImg65eWfHo6z7Ew+hy+ZJKAc15eA8ijICEEqOeTc8nodxNZH1yxqazXs7Fpg4 HTAowTwsZBJ8Q52QYqzL9WL/89d9idgNFxVF7tfKSgdh74oZpP412CsHrKrbteNnIxSi1+PxHADs jqesUU4Qz7SlLvAuw+xyev5/m2Tnpod8fEOw24MwkHrQHYd8Xy1YIP77QVfLlB2q7ypMeEhR2jc7 CuD1Gq6656/WYVVXv6vl9maoJFhw4EkHlZhxzCJwIreZBwJ1YEnFORhXkP8n9x73aOCNVDEuaNf7 Rg8mXJM99ZUAyCSDe1Yf3OWAQzDxe+6npUfo/+4Tl5NVJCXLJH6XeqfOuGuCtUuwwXk4CtZp6fv9 lRgZhXuQkD52k9ulVOIm5dhVLIYXigycyu28fVgaY9hHav4TaWG5MxNLKE4McPIGk7L8L771HedA ZObLGBKXl4jSZz4QgdVp2kgqhuCUvJziU3HS5/QPIynvMVGcGDEPumOyjuUzXZt50gbpIqjX+Gr2 zXrigF9xRsLZT1hEmz2ITTRoJwl5tkqFMxJZyWbfaOFUS6XkRNtOYiKrwp+NZi8Te0nbEuqvJ7Te IYVcxPF+6SbBZaH9u6TWG8+9W29T3JBrLKD6umqaIvZH+CYZIHt5rR5BDh8G38IR/2pC0S1HUrrx 3NOyEhAL/cZWHqYoCgk9oTAf8XAczr7hXRWDrrQ0wGBh8cJQCitzoxzeihIWSLkliMqnK6j/nQdM d9aM1Tc5kc51JW7zRZ1ETGrc9jMCcSWPgFxo1e86ZVPfLU6c88dJecefHsERi2RWWnTIJbQLVEtF L1kwWxn2RqeTvDnm4XXDDP9rf3xfJVqvVuUFbCFufGWFJ3pycryGDQ0WoUfxSk7jakuhirS77Awg /ka140K2ZNFVTnMHhNheEpojJ0lMWJg2TJwpeiqmKhjXaX4YzqV1P1ax0uG6O1HDPA3tntpVqT1H qpz5y+yIAfnuxgVt1hoBw5KmHBR3K1lzsAQY/K1quCt5SAbe8CHU6DQCMncL8vhnTMWA+koHIPMn Kkbx0Yj9pQVo4Sjc+e0/Kn82KGUrw+A8NLAMjakGYIKguZdG7nLAxTt6HgO+YyKu8lo0tTB8qGqz jPHFZpn+6ma/+97VkjWd+QgwnEZuDXl7ercXXufMsnQkuwtU/mniZRYPVpuN6qenUCg5069lPqJI xc++D987JrLr1JezRMWH5kTsG2wU0heDM//EF/9z8f0mrHMRGyMa9tXci6g4xP5mHsjLKonEG74A FKdGgP/SwShlmxixLC4yrSkMK+zw2zWWn+wu9mS1vVv9JOq0KGH/c8dqjfr6++VHxwz9CXoYxXmE oUYBPmlBsc6FBLIW9byuDo/hQm6+Iywa47WrNH+SkXHRuEPBNKVtsGB4VH+PhFYsitl2UfwtBp95 3v383d4xg1bXW1p8X67cVCHzFYwSZH9+4rRBsaXPoLXGKJFyn5cxv1PqBtZ1pCuU5sleWCrg4F4G w7Im0RV7C0Py8MFpTC/y8U20zCDGf3jl3rIF+EOFetxI5EUMpdyyUaK9vq6ylzs5FvN1d618EDjA jve9ZNGna2WYR6T3A99zMZFqZUDX9fIMY9aS81k63q2PLT5mvpwpSFNNDFLMBxeYqTQhtesHmNfv 0sNkdftk4XG9qcWSTFUzcQWUvcz55GijLS7yyqTfda27vlk6O62+DLMFWs2kSyqiWeealLwY18Ts 98gvEzSv842EZGZuT1bjQVQ0TJgcC44jsEQLtWDR/XMkYu5ZyZuTc0pCxm7t32irAXIJFuXtofWV Ver0qGBWIDj+WdZRZQLeBMYYfAMIHrTnCPZ5EqvvcdC8pBJUFCtcU4T5LhQh/cSLTjmvMcsI1zXR PGFSH1OG00gr3aiLwzVKSj518vw8xiFEntfTsr6SwZvZZXkWE3phAwbxCw3mqVsdR5iEPRYbua3e eZ8BESFb/p+KEFBRqiAaivBnv7Op8a1R09AWakJLGC9XqARsIJ71ZNbaa+tqSYCx24Ok1mytYaQg gdL6rwGRmImFQQ9QiEzQ5RlEoM/ogBQtlYIPjdPiy5+J3c19V0Ny+iAZnuVEzWXrj4Cb8t6xoFma 3cZ9GWiOKw1TyDuSHWojeIGvhH8AJVwWKfyt7hmNy2waVFYJ62ENMsqwce7apSuUCmZVsr7PZu/9 4Vcl+AawI/cXOL9q9l8WAeD9SXhw6Reqsvd44+wtF366ZgIXPO1kaOgzQEK9sePfEY9nVtHTdzmo asbbaVgVCI5aXjUbeP2y6Y5KEaXcKkcZFk4V2m1HA+6bw098Rs1uNkqen4G7uzb6GwrGIgA6jZp+ GUzvG29Gp+gbIs5UGlx9CKjH1Q79VX0qaSS1aRIbgyiAR8vK7B2uFihzfh3HpRp4FadmwqIfxzpE wnRC3ycOb5yZgw47YfeZtydUMVzkGwtcLBmn8n09AlfTmeTGyYa5WltYfV34RlC8tBucN4Vfe1P0 zmcf87g4oEqvVnOdRCJubJOoEBwa/KAmy6nZLwuFfKfOM0OVlsrfGU2llP8ORn2mcjLt2vDUJlio MN7zB2ApXIohfsJHjvOkeOqyAp+dBg0+jy8EaMdF89EIylBw2YYk1g1b0ZgsKOTJ0YssbbBCgQq8 gxhewPk/eo9ReibUKfjed2GlItZTxCRLBEA+ghjSU8lUh4IZJLK+NYAVWgiUjbbi533poBL6rpws PBeMFfdXJndSiKLvndUZJZInTbos/xBB1KGBXRs3xCpuUyFgsRg0GBvfBf3dMWOUyqXwnrIhSlJY WMWaS3+QUvngZ/vuk4xHPWJD7rVWmF/S34+r8bzhfbDJmfbUQFDgMSZRn9f58mxbZwEndUhslOTl G2CqxSTGmLMaPTeQg/V0m2FTbosyP+vVtdVw0iAL44y+D8bv9AwSzlUu2V7PBu9Dh7Gw3a45ZZ24 tjmY3k2oV+ZxSkYJvu/BVFQNuX5MrkVCWo7GHx7go/8Ff2scA8qHzLugPruh0oVBGTzJNl6bQbgf mvmPQ40jUPsdW3tqPPeQjzQNrs6bHF+s2zy5vpCTg8GhJansJZQqs7nz+AdRQHrqmHoNydw9iWhs Q+c61DuDFUG/VAgOaOq1qbd6Pwj7TgSD9ymeKOZgtDJU+5eJ7EBhYDF/7IVuldFxcLLbjktXorcg iWtgqcvhoG6kc2dByGLJDT/9yzFYwy2ItocksLno+52Zjyd2aK295Csf034FFVVPhsVsk/5Tkn9I WafPKJE9+Ebj96tV4hF16QQsWkMKlJA0XiCsDt0EXY1jwWk4FQXFBJuvbis3jy7eYIyrtsv9eq0L 7fIAlOfPhTrjuJqr1zTM9TluKXBYctoseSbJva7tSHWPtFOYZXZbwyv7PGuJdQ/hr2rmbQNqjTRp C54C+eC6ccavmj56KhxKXDXacE/Ky/w/f62sFgTPQg6xNMzgzTEXVVMK+4EaEV1yqVSBIUxFt5F1 8E36pPGX5Rmy5yGpswjiVpDkZ/iyuM1Mmp9912wrBe1hKTIsOQDnbiKEGsUMCUhhUzT5fOJmou4u HkqvyhTYH3Gdo0H+jYh6w5qKjgj+ZPUCRpcUsk/6Jas64KWLHjh78H9iS434FF0dNRK2V6G2JCy6 qY9eNu03zbul3fo4Zmy9xNm/9rlaNKgQyiT+wuwz7L/CHgWJNY6rwyr+SkeQodFlSSeC++4qrNDx Luk8tNXHbKT0RtPocpRHF+7iRQWZc07NvP4lJRsuO5d8zwxV5biUoBrJ5Cb41eqBZ3XH5hlkIHv/ kp1GAjQt2CC7CdMTjYF5NWYFSwH6M9q8cnfDOFFOlAFUz2ndn7i2DmKrSwrZtRl8UL39iHbYBiZW RNYUt75qRdhv1DKqRs0/5+MFL6XFa/eRWZA6u3Ec/emlJ2RTC1AQZksrC8VcHsLs1tdZbNqo/dTr r14En5qMmMgJovGgzK3PWRmP7HGxoMddSHbuxzODH1IaAsjEKIW6nCaPpethmrfGNNF15eJVINpF dw+BiD/GYyxkMznk+OHnCgp+9LBueT4jQuEbluTvXIO7k234KMXJot3Oaoe38b6Ne4wQEA/elE8f kFZnlafZQXMbml7svZCi2JcAchertri9FkxPxChz9n50fO0rDZZy8rPw7ci0UubQxwr6hyiC18se TqaZ2CiCXE4oVhHS5S537xHqMPFQGpterKM8/bmOZ/vFXVvV9gyncIsdSxm5jrchH0DtzQMy8wOH Ttq6K72ZbnOGbXJd2O7Iq/axihNTa2t9R4QYMA0ouwMjjq9W0Ds0qoKlFng1VSX5n3sdJrLJRNe7 H75piPkgg4NxtsOa+/aACST/LOeqffPD10H3u66U/h7mvbcrOwNWReR1eKWQ6XjS2JO98p5zaab9 ZlQYNXS6iS85LGAOFqvnUpO2JUuGDWeoEiR0HIf+ufeoN4Hmd5uTreatdU/wQ44mj1eYmyBI96U/ rA0UyzRTjBeZ+v8I2Nnf+9xNeM4itoeEYijligrp+mnyYPG9jjf/dKzTJxDi4CJ0SmYTNS3Cl6jc Sr4gPPjG8mFgRiWrO8eN8ZJAaRYKVrp2W8DGppx3/jTVHN/rhmzKHvBnwoevSlNozvg77YjgIxdr GxBKQg7kCvxBOj8ha1HpcEYjc6hUr/ROn69vTR9eB2eeLon/A7iZMlQiB3myG1K0Dtx+RG1iWA0Q hHh+djHcVhLRaCtw9tMx1jaMc9j5uadCw6V8KiDAliF0NXj9dpfTMI6kujZEtfSkcki870zNyQGS ej//W+UCmxzjL3BySRkRgqvGihZGI+J3bfBeRZJEt3zKW5t+WFDTN9RaYlUjc7QjkMtszxQySaWj BBCFnqVeOtC5oRMM8HWhoRqgytBx141xiktVvQ9H8ToTVQvgXgF+1MI2fggwZpY3rsoQlwZz8R6z thF0PAjZ0t0pCse0eN40LVN8Sjd7HjiPFRiAKwqqTUSX+nKuy1YHhHwotRJz9pc9loofeQESF0M2 0XTHqDIl3Sbz8zEhNLpZiM5T8ig1T1LCycMnQOjOFaTipCq6z5UoRjSBmAql/loJUCokS6YrqTUO 8kVOerEcfuScVe72ZrnJTpLCWamDif18vCRqkPqSvua1IjgYg+fDGPH0TJMaHro6zA6KjQWXBlKm iHg7mRB4KTG9gBWaqx2JhTTZY0r/XYqfa7bYcYCE1KFWJEJ7TaGNmXOrwql7habCyJ2Gugln0F0d iiXeSDZcLJu2L1hZaZWU+rOIvgs/7gSM5blzqGo2RHs6r2pgN3InRDBsGIyFGuwoihkz8Cztq3n3 d/UDs/mMsnzhdtVj5C8dWYPsXnspScwD9RecNn25RUbXuv6KyIi0/Ayp3uYv8m/B5ssvDKd1y4js iSpdLlhFo6D8xGLPc4qA6DVTgGa0x3ig9eXvHAFXpgRmHOMLCCrGE5520NS4Nk+taKkD8Lq54FIl oRoIhb8aLqKFzWu3DXqZ5rBsDX+UWovxZRxZmesPtHcg8O2obQMNuIc8H01yDAYdLPzAK1olfnv0 MbzTG94c1ZVLio+tQTikheX6kFacb7ZTf6BzHWrx8oFp/fR7AGK4vpc4+AfGQFnZfC88W+1QmS0F wzGhZOlQ+shiyVfqrq0RY/4XWuJ0B8ySep1zwlM94WcOjFQWadGUWpkSOwQojjnrj/NWOlZ/v2cj Q+zvV2PC/OjB6UfkE5yolre6aVinbYD6K4slTYsdt/ZSLhZaJ5R/tmNFNMfRa7A2AgxRH8fqNLAu 9guqczG3n13FQCI8KTDQHwDdBkE5cjQf54ilmipOMA+3SPioBToKObWjAXFpQl92tXVpfTtT0v1l dYZmG6+QVNIqdcnw28XKYlGB5OTqV0TO63MCcj/xrA+gLzlDJOemnIQeT0MhN8aoqSRfb4ZWB+T6 ekyQoOLJ8OaDkP+qpnYcvrkHB+APZnOstTh2IkQULAF9iCFMoTqvLGjO+R1iUyHpakSBXsLzGtiR rytQJkNr54o0mBEA6PIW5TjLWw/t2iFavJFnEQwjMcMNg+oxHOVLx4bquPa55Q2qkVri29m+eNWo 0QgM0EeHB1URQlycQrdzoJRmObD6SOgHM598gtwGYTRrcoQPeeaOKeDChhk4w36N5RyePiLb/2sq ji4MQpbm709WH6K9cf4TEcvyTQwFDZKYWYvgmDXieZVR9MN7X8qq5rzaulmMY+R0GMdHEG0WOAKu b8yohzdA7XjExGqxAjsTqs+x19QQjkxZQsdK60MfS5kkF9ulL0zrJIr2oLuP/rjUvjVqr5OThHUa VH667EieI4G9oazd8odCeLgI6cPSApwzj/4/HNgb5KHHFIixKktjN2X7edjM+0HyEahJFAvxGEZA PlmbVt77RbqF9uqkrZrMeeko/LM5MlG0jvxdG8ukVghDk1UoEPsaNPSp7l52+TA7XLWy0JPWkB8k q3T2cuWde0qH1GX3NjAiT4gYHI0SgVH2p4yZmfYb+Xutalr/PXm/stA9x3z/ZfDbGcFhKU5COCu6 CwtSArnILRUvqq0VY47v1+WZWZPOnGn5hlowh8g99L1+tskq+v8r+RVs02an9nQNd3Cn1k0o0JM8 r1VTJ8idQEjE2FxBjNuT12YezS2oza/3ZhTTep3KBrrPI5WXfBmMjMRMP40o57mGph1hzhb7sorS 7VW9lGHElw/tAMp6iJ5ZCgMnXhSW37NjvmvqJVoWuQ/S764NIi7XP3jCnItNbylI9Uw2JPJ5GbQT e0ZLlM+yc8HcNtA25oeZpu6ASh0aVGr1TYRJf1raQsmqRSpc1lecTvRFf/gBxkX3sxlSFDg+09NH CwN9VSHnORCR1S2NCesi221lMS+znOJB03jYe5KH05Up9Ezs7Th3J/z5jTs7WIDNnfnugfOa5a8U vGllf8AfUAsdjz5A2h7bewVjPva2jjPy8bvvTLbSzF+oiEDMBLP2eeAmt4TrfAXfuc6Veu/9PhLE 3KR+mR632DKQO9atqNAsiZUHXDY1aJyNdep7ooQQUpWWmKg/f3oGmJLYGucNC1R71H5cRn91ItyP P8O1gKjja6vYaNx6KH6WFN2gCgvIHi0tVsL5UR4ua4utbIk3BpIzrNKQBsEInoF67ncHYCLVhH7L 2ohfKJ45jo329Lew3u/mKCMfIeIjSeXBddZ9P1yjR1j0DN4YJ1Q+OXoMj9aWISRst0dl990csdEm TCJrLeIaW098JUZctgueo+bhYbHLPk4/WXZ34tb5zKaAkNM37+uZVrJCpVpqmG0A6HGlQxzyNi7J CUUbl7BH1N/rer7e1zt3CaXzDV4VltPs4jhMx+cwL8duh6lPafqzzfgc+zGBSiiEZOdoOunkm6Pb YNPMG/VdkvyKKm5x8e6EDmKPLUGmMou+pPmT7yoFR+Swmt394ZswjnWTfSF+EcRkBIFJ1Io4G6vI wGlLyLLqYZiz/cUa0fiqkE38B4J3rMFhBm4AIyU7ee1WyPvNzJ72CTP9lc7NAWoHKnaMgNMcya6N jVU82U0H+2CktSstRh/41hpJUaYS4YalnOovMY6gy9VgsTsCRAIX/34LmbMxgfAMq2qSdXx7USnV zRHlcbmPH/1/31J6j/O3fvt0t8IA7wqd3OACi+HHGAnvdpRc8HNDx9sBc/AIgepZzX0BD5i2OTN+ tXfr47yrXvNPqjYeg/3JUZOrLV8lbFUpVbvQSLk2mUOJOKSFGHwSoIDbkv5ue8a5rrVOeLQqlp/1 +flM4515MctQ19OYdtNWtBa4pW0mGtF9R2pqyGHVss5Crcl+KF46tK9SAkvKX/o0QyXJ62spbuQS p3HJgHUEyVX+g6upVq6SAD+Nqw2o6kMvjHZjdz6OiaBPM76T/PqVFdsySthBhzYGaLRqEig1asAz M4C/dVLW7ko5E091x6Rt/5dtX1hgUp+c6Kzi7y1Dvtk9e2+tC11Acr+OSNR0omdcFF5h7nzwC9qp t8Tnxzxy9tuX/JJJBn1HOpN+ASJOOxltdwYBHIEbJQ5MARqbT2nctEHurnOVGI8shVw8e8RkLn0M vacAq2LCWADnmZY4cz2+HPmvc6mkkOpkyyKDdcwpdDkCzdfk2InD8no+1VgFZZlZjPZm+D39paIj jhKn8dIEQblhaIsUdJFmpAWRNzL6T/NHU5X5t7VHRo0Xy0Z9/582Z0jKOAgBr0WxirW3YUmJbPy6 nLWocPn6ZC+6qmGbJ1FKX2h3xvjS6wPmr997Q17RTHdktbsV/r9vb8LzWqS2oqaF1Y+dfvCnbStt eUbypFotq32vqRbEiXYorgSDT1gT2L3HgUyJc3xEek+O/SVyY+VJK1BcxNbGhMHuWIq411kQV0UA DpA4vSpNFO8DbDvhkjMbgX/tuZnwVOd5I5a5+kjnygkA/pwBCnKzOu2/+wsWw0iF3yMHZ3yVy+XC 5IyvmVk6ff68eIFEEvf7M5UC4WQbXDFq7ME/MGUSmPoDCkdsYmjFGo0nldDfob61dMXHgm922y6R SWuxvRImz2N0ahEtwWtqqBqYI7C4SBejHRUC7HkIiJHyOtfr/noi9aV0yu/Z8zc9/zTk9MpYAfQv 7gvqGPbmrV0VEegLQvrhagppvWEO3qeL6jUIeFRKW26TEpI5Xp9irg++NxMxuVzOK9i+J2ZuhRK+ XvQftURbjU4ZrIdcHJ7/TDU7uj6xqjbSCV6Ysn1a9fRfn7y517hwP6ocryOXdP+o8OtJWvgZLmrs b0Cv+qwWVqPIN3+IAGvxpZ1VlbiP4uwUVOXOv9pt/kJr5DURkssimLeu1aHzWTRsTZzCVj6M9c+y 5ktTKj9XB8z5fEeK2b9Yv2K/91MGAG39ymTpOIA836gbh0rNdcYanIYnf7E+Hy7sbRvsD6lZMtaF vzT2GTBvM+anqloXRABak6M/xwiS6B/Oq5R161J2EtBBWGOsufaULhoyyNWIZTQbg2LXv1r/hGTL u5c8A41LO/WTsXuEdCOxrKgvmdHo8yl4JhkjTkUgRfdaA0VGfwvP3uuKGPW2zePCivWOBbrCuXhb hPolh/IHpU9j/65YoVLZLfQ2raIFAdxeYuI/iCOhOxhpgsGEvP8xdPOtlQykgiNqhWbMcETQ8TCQ SnJOhlGJ+OVhjJdKjKg2E1TJtOMbRKWfUcse7x/tXdsfkw30nTZPGeH2lVflc87DX+xMqKH8RXVF rMn8IH3ZiIII6Sq6SnRIH8nUebuKqW4BOsIuY9ZZTF1zLQowIqAHGa/AELlZVjQfsQOSG5ZDOOZs n2+mVwtQ0UAFsKks0xivbIpTMDTdIVXCl55cAjYVVYwx3MKm5ozOqxKkD/X+mvqwMyJ8inQiQFww BdUBqY1/ooMiTB3uT1l3cVKfybxR3fVoHKbmsNDU8WlPrW/T2lqLro9C8szg44mV1E202rhIYLLA kJ6Y22qM64aoLj1ICmlq4KiDZYSaACC3s/iABt4Rz7+J0wfL0J3riBuE86zJXJ8xl9jRcKEJljF4 9Bxt90Jk6yNCFV1C6zPDHr6ADt2YpQBh/pGmtr04/tzXjr+IPrt8HnpE7I+xaya4PPZBt4MQ3NBt aHDt40Og07Z2NObKvVrZ7R3J0sbssA6SSB3PgSluKf673tX2gs5IDfkqF9NHU0p/TO0Ydaeo2eEA iJbt1oLYU/PyMMouomhSerjrPoHZP2TU5bsET9s31ZN2Uq38SlERy7woREpI9K5BDZC0iKpaOXXV K/Tyx50mblyWt+aqM0CJGs+Z7e1l2Vkay03OaoguYQ4Nv9amkgu7cNro5mFGY0z9Na8fMwZoWclZ R6bIeo9umB6v9ddMQ6G0Sk5W2CKcbzw07YPCQdkN26I0hbwGdtbrjuZi5cCrvsXQ+Qv9ljfmDxsz NEIdeRa4FGH2bsEYTl/HclQhZxi2dzVB8omxAv6CTBSor3gc7WotVgCP7lz7I/YSWCCEPn3/p6tR 5bwA3WZDG5AEvDw/0FF3zEax2EzNLUCSqTkp5BIH4Jd9CM7dVUEpD7F5Hdxev/+k3dHvCK67ZUJx 8ukaN2QPxY/P7s7JSqNV4xa195+4ELYhMcDvyqgHp4H6A+MpP3YRQ8N8/NhJh2JdPnLE8Oh9rv9b /ghCDOstM0wvMTXUCpaMj6LcWz3g2DFA+bFs/WHnjGtkte3+4qWwzOc473B2oo8gj9j2DiiVB3RL UTrM/kBGYW3SVGaVn4CfBkHDiTj9vTMDrh1Muu3UZ5XXFt5oL7++a+9bVrqk6lkItvvBr7vHbhDk AADayid9EvUM7/DeXQ4jPD6O+CwNuMkJYs95Jg1VU4JrR3ej857g8jCTo+CeWWaNLI/2YfRvQycz 9ZjZO1AnPoU/TlTnlrz3UdK6Z+UOotPe8zaA1WZYT1OW4WjcbmaWXudI5ADbZqNCQLgdbvYNWHsY xPeTdOi116KvUvPIYPqhtn9X74SwbjlKJyAbooy6hikYiEcj6Mizt2vClkJBcI6WKPQ9UVyCUdCf eRCT1YVLq6ziWqxlSoWSzaWTLY7ZWbGSf9Sl1ms1BpG6XXnySQBtcFvfbynsCS0nZOsnNqsknd1a twaGLbIevQDwQ+6idKNW16FbQ/XOX4NIFusMBUN3HdE5GrCQJIYqE7F9dAwfITo8fKCIfOIE76YC IVbCrutjEGeERxbPJdgQrs5yKWKyOKs7mOPwatAT9LuvKe0qag9oMlhzZe3gp/RsddSq2zBJwwOk /iGCRe0yC7IG7ZWLt1/7MsfCL5TWzaLZdwRyw6jpMIZ/5zhSfRxTPYvktgkq2T7LjLwuFtQr+oLh CwWw+bBJCett+aSSfZiH/ERGuAKzCCKLIkaoUbMYv89LSv8Yj69Vxn6kQRfd8EGTOujnhRJ+/JKS IlxaSAjudmO/ywXy+jEQQ4PMP///Vyrgol8MOE3TARsTfM7/Mn7OkVbfpOQYhFZjdhGIVs9jhbsr fzW/jnFua9ghq49QsqLnXx8seCXa2+Z6hDK2l8pgpFkkvHp5mV/EdBAFgnZ6rdHamCfXt7GJBZTA zJbBlwLAyDe7jtZqOvilEGsmiCtnJc3pQLQaaI3XNFP9AK+5rqE9t7kJysP2d87tAITF+qMJ6wDi 3Yxp7j/C6PE4ZWEQpvZknb49adQGrYYoEqA1b6fs7osoykrCWB/KjjHXQGf6p9kXq7JMFjJ/doyG sXG9ltB4+YPHQabvehSAWrSzv16kvQyS0pGVwqA63lhaSt9weABi4L0LbtY3Br5yquaD5nh0qjT9 5ufxvAPcEktmHtNUUjTJkKeeRtCF7kYj/2pwiyVTpQm+rSVm4D2RewmBZYxUvPH5EuGu3ltqwbfU bwkh/gMdweLwq0UXjxew2r9NIHZPfTGgR/+LLkcBQg86QR7GCAzMbPLyQz4co/wuiOCQgdftetrs DW8pw0DoRsofsleLzbjdzHkTplI+QSSjNjboT51MkTHIy2qDwQi5tawTcbSyOuj+hlJ+KiGkBM3+ 4110eEL9wS18YfvAFx9DKUGfZWiWzV/XoLtNLIW/OGmOhg0Ldw7mX5Ge9kOcVAwJdzBmXE51MCIT knZYKUauJNMoU0ZhnRuvB+Kr2WuExjy415bSMAFIah8sqajGyMjk/3BXORo4a218vKk/kUfRiADw IjO9cj3eCVveaZzLc+njvprPPOLcB5O7Pf0Vgh3Q5H/1v8AIE8u+BF9dJ1Whr+TLuFa5cFHMov86 vZhXQAtC1FmyH8BLopaD747cHd80FcrWR2hwTvrcpIHjdQtIFfuGacPneJfLDadHEksHNm4IAIkS Paky6EWhYu77U/sgSvPYjIes6TSaxy6foQi6/7W8oAu+bPZ02e5eoNv+GrUZepOKDeCpkwnjukyX dDYmv0amiEe6YLWYnEOr+h0rQzJV0wMfLbXz8q/6RSoHO9Cu4Se6pAQkIg5IstOJDCCPKQI2Aflz M7okeCe5E0FoDA/rfGjuzCuukxp2PrDewp5TbOj7fuLltxGDdEwtUgFlUELUQz78nyUDsNqzWp5C AmscB4nUYosxQtEqEnmLFXjP++ac1AxY1nJg3moUsBFEz3c9olgWv95Hv8s0i0iKCM78nNm60G2R fFB6umACFz4zbrU6LupJYI5GBEeGPvEHNpr590zwLvyKvqUJJLWsRu8sz81ZUJb3T7iQ6HO9W1gK g/py5mR9JUmV5zhTgfdBTji7WTzHW197LABGPbJsJsG2bvTxvhOkQlv0A+yZxgOni3Si8XkuLar6 4YBpDkEjShfLUfINzYpLjnj2BGBwakMcaflqn9IxqgXqgMs06mBW56tVctOWbjxwgTFUcKRF7qZ2 ew1Dd6hKJFAaCs8j/opFemXLOQHOBOe5jpOTiYiBDQU1+iwAjfHcTz3I7Av+g5h0SWBVH+c4ad3B oIHWQzmiIVWQUfy42/fgBKQkbNbejuX/ic3PTw/Nux3I2kjPZ49tKdoBSjesrdrmr/WUlZo4wwVS ooeCsOn7/joSjN6Yae2SCGk29TqjjpwUwMgS4oh7fD+skG3SFzikOMwSj2EqYagU6KNFKsIewHUn 1VWQ9MLcsJtFCJe7dPbV3yz0+600OrzQtmDQlHq25IEFjG5BfoV6Fq8/WcgucfSf3fzZvkNEOlw9 /9/Oyhd0v1pbMwN6aqAmIOAdR8GSW/b3T4y9v4GDTL5Fs4UlfD/QqLkHVs0Jkw38HMkvwkg2WLci 2KddyjxozJ/DJqay1he2hxkSCDDaxgSGFTRjL0MkCl34e/3PiOvrW63vYspXrRdEFlmhyF4BTI+s SaE8OriWhJDoF+F5+5StPtuP0I6XfxuDPfaU7DyWo610fF6WkHivQQN0muQGTLqrXz2s03e3M3kI OF77IfBT5jzZzUmB0X456TVEQ++RQ4OM9390yPUkWFsH6+4f72Tbn7RPeB2wWlS/9vAOH5NRIV9I ej1bi4QWvNdZHYcdh4APbfgkDdTdsGsJV4k60Omm3vfhBYhOzbPM0/DejdAgQkL5S2C+fvwJ7iIm 1bmiC1PNHPQu+eIYXLQQdXF18eZIfE5ZM5DQognA7QA/ughso+y8bOy9iODPx1t2oofwxv+U/ciZ iy5BAiTDkUqoeL0Kyc28jcchiiDV9GMoYo+nqtkbgsIBdGSnxL/3as3S6SpcsMi+8qKKBMhm/KPY 2OAR4R1Vi/Q4n1KzSAQgnEXAsQ5dr/QIstRSq4WFA0TKnLUwHnlxuXHQvvXk0zwNFt6xmQEja2Pb SVVyNNqLPmtOOGkCcwExh2TGNia5aYFlN5UB/Al6tRwQLEMy2hiMIpgXCQDWjoV/cFMTDL4x595a hVCm2wGyQJHpQ63Y83febTDu146qqkbSAS5GKTt8ngtPc9N5P2YVLSVw3I/Ugod/ZwYpHIEGrJPH DGCCiIxq0RFPnxRxywgvMCPwHFR0RPECMIWTJ5WpUQGzLkdWV9d0c/cmln+3oAMktrCAVg1btdzs H/2MDyAFazYLQ9a91R9qBVQnfStBUSmrqM/vcl7QkoZyupfoO/jmL0r/dNKjgaUeEDgHHxPx98sr nE4wVg5Hf0dV83kNdh/JwgR9AOzN/FbHizZoRjMyOCMjPcJw0vBUDXxoEQZTCp4e2YBAxe/jCakD NOf+3ozQ2czYZBBpVJK31HP5FjXxxMi2gU125KU+I6cLJ8TrE9k2czmrvQLyqxblakFgvrg4A9K4 9tgpnww2JgvavNnn5U274DDW9aQmBlQqMblgeaOxSuY37JCjvWPRwmdqoPf5zZDcpVNoCh4dazYU YzZmdv30MrBEOOtegLvxInkREGgbuPAAsnJ6o5QCyTRpndYHLLTo4SC/eFHK4pDlbFVFMj5Nz/i6 7gZdb2s62fPjd2XLhAmINhwarstAWTfDdwfMjQNHiOpJHW7k8e1riuwoE4zUi1zvHno6y6lAfp42 CoUtnUmFU/A4BFxAMeP4ne6FybG3ahYl4Wj7G5xfF0i+YAqJX5uQL/GRKknXIsPactwrFRqr9azI jZXsuasTLOgen99iDnSUZYLqSMJboy2zpJaKwJjrlXlrNJxFk7MTZM4afVNJWyiEKzSq4oxsTxaQ K/KNXqM3koMdRkujYqxKdr4OD7IrGkRjtMf0thwZBt2736suXN2IZfxjPBWOkm6I3zMvJCp9kSF0 tngSAuBgTYD2I4ddjWMF1x8VPVCVNK7NjFn81xIPq2UCL3Oavs9urFvu34wjPKag2/WXdxIlssTv qeH4V7+wGDmEWZLPjtPhxepTiJ0XQNu1Te4VwQSkKV+99P3MDpan48dAKsCCF3ZexQSH6suepDUS pniVfMXxrqQ3vrmVSHLHW/ae+yAGw2qJjucBs7cbEV9tWSTxS6xigS+6+9BJEacN3Ww1JAqJ7bPB kmxsbkNGTdXGAMKLUxx5lCKgM0pXYaI/PxozNYhjU2zaLuilRjHOT69tGnkELrrJKUizN2dHN3sB QgWscXIukOAwiKBFUk3P1wTm96S1NadMNgk0a/6EjCLWDG8Q5TPW1N/u9q2S5emdyyP0DdXO8EBy iNYlkgc07/V+Svs7K2Zyl8Bk/rsoHsD52VX9eCRuy5nX7ArQn91FbqunZgofIrtkCTgfaxSbtuOE Td3Mgslt62FHgpuTJK0Mt4ZRMz0MN/QRqeYDMzGBhvO18ZROzK6ibeGN/oKdXn50MCy+jQPP0bwY 9pRDAxBn7eJJZhN6onnzaj/TDCiETKnsEJBHIp2vnN4jk6415i2kxufFSL7r3rsn4lwWXzGPeHdF lEb73hzSxb+slQAGAypw438V/cyaG0PUGSccmCri7Z8KDxtVACPckfGQfzBv0IjyocH8eT/JGFLD YbbelWVjth8OxAVfB0yYHFJ72JWTy+7laIQeT0QQn5K9M3ZtYzioUbxxt/g05o6GKS+V0dET3lbK 3pQCd46B5bCRr6ACbY+zy9e0wxFybFWZF9zFl5uvnZ+m+PkgahvUODzqQQHuIkmQP3SvKygRw4xQ uhnriNguM2Rr7DMm1xlXqlS+zFCCSccUBqQ38GqR6IJJYGR8A6qMEiw+IMV3dgfjawkOwESMFtqp krTJXXN0beIYi7MjAobaD13vHL3nDjDNK74m0vnG2HkgZBjKteS+r1frJGDNtk3xlGnr8w2be2Rr qIc4hb6zZWOuqu784urMsWfTpH+/OXvN87K9RfIADsh9/rfI2qineYiCRdLQbARc7lenC6wdgPuW PEv9UD/IKlzjpJ5UbBkTucPLQOvKlBWW9CvNmVv6cWs+xw1qctkrx0DhNlZu1qUl3tQqMDHIOL8e s7Z+D0eH4oXUMw9wiJ9nCf5kwaMUeoLkDUDHCYu3NoVxjl/AvGoHELwWsD95yl3Ma7TsrrLAzerp 9atKvZyJTrapGYRf6tPRlKMGSfKm4b9tZ/0+EyuDQkf/6mTJCY2xOLRfb/6tR5u7TfJLjsTpluNV 4ye8Jpr8GnTfIo3rr9B/2Buh5c9x6xRanDBAKebDRpPhf0dYa2C2AfwPJdYYi7OoyBN9bCHlZb+3 G0PPFg0+Xbg7hOuiaADTfvbBUeJUQJSgVJC/riTeIZ+pT+K8oeLtbM1a5GMtDejFQo9rt/2dK6XE 1bes1/X2bVg9IlRwrHDYlt6eY/MPtsDIg5gMDL0moHkq+58rbsSDsRj7w4+HUiKi0XEWx5D/yzIB 3W+sgOyDUAnxUSpcdMlbdfyG15QZS/qd66jKEhTHnDKKYIN4xqhhW0HuNqCGJswj3YveoTZ/Xi61 bfTEhK5jWJvzXzyjk3gPH/3TimkYmy7J1O8AwSzFzE/i7YDeN9YVKD6mR5tCO5WzOdHILc/IjV8m obL3sa+FoBMfz6q38EiBJspxd1jKu1tvYPKteLEBSkcXU9NdT0JBePZ213ytdka0H5N41hD9Lz5K UlmaHdP2sbg46d7LVlyJnnip1qRsXCJwXPrazXz5oNyycMzysE7oXrv6z8CAALULGYcr7zxUXsAq OYOzcCl2Q+RhJPWeFjMcA+ikOHomLcKjYWt4oJyGe8NgVIQwdvI93uc7rgSook4JioHnvXfauPWT 8zhcaeUHuj7RW40S7T4fmBLhweeUMEj5NvwuMiWrdMQXNmYXwNwWeISp9QFh/FgG3PlMhE2yMlnl PkgFC206931o/WfWAc8riiIxu/6KSo0VE0Z4VjQwwRIrIsiTHNT3Rr671I1nqXNpj+gCNOvKGZDk iu84kjE9PPZyMUpx7Vgt/buU/wP+g4+FksEPiNrDDvmVPhrZw1XVaCcdiB3xKlVV9ZiessIcxsWZ 1yGs5ZyTOwkLwIxVNTjehmsHYjXnULczI9MVvknPvVa9mKBe60efjLOHa/mTc5xKDzkuRI0P/l9i n6lrm+5AsOoo78bSzJX2qjArbzgIWdIaq7zjIyegH/eSw1/wj5PHeug/ueVqYctUHAL1HoGwmyFZ 2YlvK66lKLepy8aW620lrq29M8u6FFfU6tfVkaz68e334zoTsSigHCzZjAV4/zM1ZajWE4KKh/sU Y+Pid5OaIYna1e/4GxJHfrOHxIUYWhrz08Pa4McehJWJb7625iwZO7JixiT7wAXZgUHLj595DXJr PLT+eqH8sCxjp6i5qhTiwRjJqvjOZMxwXzWsEz33FH8oyNDzIiXfxzRb7mtwZVHBP55YQMJFtHZW 92e8hCyvjktbbXsY76fcA1J7beBzJ87w7uBt2dmbXnIpu3WzrZGXDDmZBg3E15at4aR5s5lA/exc 2AzIm5mSnz/gornVFDIHYvdEuYPfOD/VjrlMEfLEv/Sl5IwjUX2uhpjcyvaPPTbD+6DSXLPceEEb MHY0dlsyIFUaSTDn4hLjFiFZPNQJJWCXmClOpuHJhMoHtrC9ttQ1p8uYDmzNwcep2vXkRtTglrtS 65zQBa/eqyPVtGUlPxTrSXDPu5G9jTYLIg2C83fz6/iNJMQzQ5QHF75Rt/Vb59tIFQaEMh+sgkTx UhR6EG3EJzH5WA06K/z2uUCX2q57ERxmjdBKS++z1xIVfuCSjuyXO5PeUIF1wtc7lkYNIZfsnjsL jy9nlpfNUycgTC1l+Z+alOY4UfyNFcmjdc8SIaHYzA9veAmBuZSeEkNLuqwMvPnH/Nj0pRKk5u/d TDgneibXEiitdayqUFjbHMSRDMD/DL9N8iGlnv0M09fzORmlE+r0SR58sQMdlO6un/yRMYtOLx7H ZRMnZoj/jMgzHuhHAUFTctlROJDe15NpE5UjTYjxcGSSaNf/0868aX/UJnvdawKP2iCl7TI70Kxw NNXichBw7Y4k1LlFZOhffLH6HKkW7CmBGucpK7g7+QQ8GFRmApwPamcGscfltoQehuNfl4IE2WiM yEKgX7Rfw4PIxGecR4SQH7Wgd+sE3BPy6HIsb0P9EVLZ4oLuVX4fapFCOvwzS7zKvdVX8CtMCFHi gSoWWQE8kZ+GxY62axwKIGt0jmI9ReMVX1T7ygMJmpNG8iP1FRMBzq8BEA8gLANlrPw9y8WIYi99 frEdk/rtMHAW64KDVr6izuBB3me9ZeampztuVnQKZOAOxyWqu5s32FzjxFlCzfYj5KxJ3JD3bWkn 6AzhvuuIpgSgqkz9Xpf2wAOQl1eLIyJa9uhFpojaDlBuflLIWgSmHEv28eMrXoKfIiiAyuK3yUyd 11aKNBlghihSHvHpbKeVOGpJIe2navtqWABa/Du8B/4lcIxgVlmbdFZlo0NtuTFBn7VenFC7YR6P dFjMpXPSx7lTAp6YF7jWPePWMY4wC+ixdln0rxzKeRSJ4CVTkFsMZKN8RzDY7W76NVpqqPsaY8MF YQccygz9tAMN3yrr3wcP1CGA+ljtArtqsM1iJmkHuZP3obKr6NDTTB4v1DC8Qdfp2yNjYrfxr0d1 jmFYzR1eLweDygH/Dh8/eIsbDsY8AhA4+DzSTEKSypTQMzfc/a2v6efINCDDU2aVCPqDpyBVWXwX iNiWbnMy9uo5oy8x1bZfqhHZXMUShTgQx5fB30S5Qb884967SwR8WUeAdO+3I0o9ylHuxIu5b+bp FEx4QAqPQg3X6pGWv8hePKzFl0C6BRFBZsb7ordMRfJeKp4NzRoe82I6ISTexQJmp+3V8/RUTC2p qec3gOuxhQe1KC198Tbczq4RZto2tm9KDEswdRmXHpDl2op4VBoQt7Uu7kIBfi3JPjZF7Lo1Rsul Yc1HI3SLFzE+JaB0GXntsUCO8KQ4qfDakJJPZy311X0E4gyoZKpO2YMFNWgsxqj28rRJgKlI3JwW SNf4jkcr77x7sSln2ZMG6av+jfrnr4Bc/JPNFFUgIJFX/sZv5IcUez2T//NDSssykmLyeBT1/VcB Ks8hcd8kppB0J5rotn6O+ZLjRA4Y6mXUwiEgBkIuWiwAOSqH1/AvFuWCgnofPX6cGiEZKg7+5VWK Zxk+0r5fORUJiWjxucwgwM9tXZlqQeGKXhG4LWLqwyntSoemVc77j3fNjwdGYzKh5pOwvERicxMx 1rKOPW5XJAHbI4CAJJaDU5FR7tmd0zEFd9hUjVduA9C3QW2cXRIZ1G6xKNqW7TMXTzgoEE8PYUJl oP8zJHmEYqIn2URMmdOOBgq6qovwAvbvLtkBCNbDxblImy4Tn0PSsOXC9LV29kd7KRNqkGnXK4jU 6xlJRJ5EpqNQbMxKd5AOGzAELeOyu+xUndmu2sBMxawWyMkHkwtYniZghAXmrXsya4pQ+Ne3BiT1 jxlW+t0Loiqp4uYSscJ5bCtvOe8xcrlb21GJitfYvhfG/16CUE0ANGRImwOrwkSsrob0k1hFwkz4 iEhTtaLjcDj0ByuXk1rqZkxQk6+tD299ungNQT/dZZSo1pk9AQONPlaUw5/e81vUJOjoMUBOdv2d P4CogjlkzpEv6OFMONGMH7Itu4/k1CuvsRQ4SUrFWq0ID5oEkhDqNqeX/H8FEABmKyiKxUR5pcQf ARBCxSPPezblV9/vZaklJBtitoIc8KessZ1GPYxDptSbCVFw3kbfAl0/qj4sLAWUMbifWuCWBPtS gZODqsadMYSRDKCKMJgCjS0LdI7nRYiK5A2URcQ/o5f7qu+WLjr6miVx6FrIrKxJeVBH9chXDCTA cXGviH8gu2V+5UNLnqnx4CFVAYaiNepRfLVRsWgsgWBgJvBCmWnOeeLlQJP43B/JZc8xcUArE1XV ks525ued9P3icgC3JoJ4qGKaUMYfVRBOof31ySm/grGQzNMlO1XYolUkZk8OIMZBh5HMbgeqdULE vyLnDXOq9c0kJf0VBsjzKo6IoH2KWFRx5NkKtvHMrl7RAPcUsxOSKUoqdKgwbWuOe9bzYNP6hiVD DIT8V8RNX+lNzNjOunaxGh+h8x2j33v07mj4Iyt8X4kXb1JnBU6tE+xoMiY8AsgAYbW8vKCKGxr1 JP3wsjcYTude0UwozQpIWfetqKJzYM3tZhZQJsS1NTK6TQsnfuTfvmbhuyCPTP3IyulKHFAZbjcS IkFwD9KYkXRkKtmTkTxXm0IPhoh5/7xZ6Zla4l+jmTKX1vpPAPjTMRggwFxJad/Pe5dQ80Lre1ju Ndc4Z17eAmx1GsAiHVtYNfrh0CULI0WX1okawfWvqstPVPkWEcQdWv43YwfGevcrNn1d8CexQVhk Wv9DEb+4ToXYW2iYh96CCcokXKhCJ5UYEZ3kvDj35zz1UEiQ2BpX0/mpt8xoPctE1TxkrOzAXffV NvMCuw1zBIA772y0eMUlP9pLlWyyQA5JFQg05GO1cF77tPBYh96NUKA/jQqyKB/eIbZ8vsQNf+sj c96fnVCaPZXpc9mHVzD1sjxzdx4CgY4i4v2hjv/GPHI69vLWaUA7C8G5K5ht1jzkzksqE2I0FAMv OlzyGAPk2Ba7wmcHaImLCzU3yQGImL9aVVAhHs+VNU6UfvcmcuI26BCJ34T/Q7U6/63BUjxfNHuS NrgOY3uuMC/I67DeT61nEB7hm7Z8nVoIP/FYlqZsZHuHSpLy2PS/fdGuPEoOlS6EEdMCSFgYPQio DOuhtUlg48+r5msGVQgSX6xPcPUQ+kZRh2s5WGIfuTFGQRUbQ2WnzlV+Rz6+QHCDCnHMmiwndUmP xG22ECEJYC2tP9V/owFplqnJx8Ga2Kg7H+doniIwcFsLJVyhqp9Mjt70Stz+ImT3WHLusU4BaAJx rfLCGzult+peEQ89B4iQxvqebSMny+NcvhnU4BZJnb3Qf42nmOw4kNvYEFeoASpAGzpi5cFf5mVO MNXfCfsuwZDge5bPpNZ0x0ph4fDUdbwlGsThqqaTizTPEpVgRnEipw5BImNv9iLQ1i9Ea2gVpMv/ flteBvVFmPX/jBstc3CZWYw6FleiOw+gZ6/UARQlO6sgBfTvd0yazIahM100reidfOXk8mF9yt0R qDevJY0dvAn+tsoslWFY1x8/dGxc/ty+Q+o1cCsclBX32uIL+kl0UBTWCUgcBqh9ObwvDyGJWja7 Pe0cJVbaGz0rLPeQqcAaQELtKCzCTfsI8sFSm51UiwXiRZKW2Xq1B5Wjof/aF2qAgOqa0IsT4xBJ G96JnDhB1nmM/Z8QRstUD4WBIUwwmmDTR+nRzlzbcUHgXqum3k4wWXrRKj0lofL8970oFnQXlisp Sf3vDqrMFQNYHw6++ulHiBspih05pdRaI8EVJZU8ZXtNsI1w11NIG8uFg4iruzsUWMOLqZvb7XD3 D8t3xH21IFlmnR1esUdwjPCpIfga+IpArc5n1PVlqedYeg9tix+G4C6++uISKlnkMFtzPZfMbdyG ghZsNWm0QhjsfXDt9bNJVuz1h9KUVoj8/XP3lkiceIorLc9OM6uRX+TeXu1QabSzeW7RAmfFJiJt Zpdo94D483GeIluu6WWtohHb6Pifz5QluahvGhjTkIMgu9c415Amfv6fgpny4lL7wb4dDJT1s1qU wX+1ZovAP/VXnkWGW5I4ZI0ftQSOqu/JwJ4gmYbiDb9lSf2uKlNtwTVbXzi6S7iQlq9OpNNQLa5i d7cHQ+fnXWY3lkIgAtB3i2ytXgIQGGLbRKZBd5cYzwDHEoxnMZrk6VNUGGUOmWlBmvYdHLSZ68aB 3E/Ny23iUBR8DjjZpiVaBU94EJJWpLJaLHfiFrEIkmlsJfNqso0weAgV+1da1vG7CAGAkhfgOPnv kztr9S2SggZ5IyGlzkgrba+2CiES3NIk9Q+j9oio5QMOuinZIxQ5G0Z5zom2AbbCzm1HKSALStXL 3S5Xbf/lnvbsQ3zmgHYCiXjw/D7RPekgCPhM/SjMFcwUB2mzGK7e23TJTr7eQNxBVvMM0aF8QUP7 mUtdlATHrp08y3cFoFZ1QT96C/zMhNE9WTX5uIA9hYqy4ZdjIjpnbWVLQ5dIrl6+rnDLWgZrKlNX /QpHo282MU3B5q3+NoGLmjyRv1SnvIcTGnBQZ3OAXVPLSaIwZgUCQJeCvQBiRExHw5HAsLwXRP9e Jug/v2dIyXjG7z7r1mWfRNPtyCNxGXZpfazur6pwfdfRvsYni7Q07N3PQuRFo7A4dC29S0KCrOta HyLF9UZMbS4RQUGEFHymw3L+TO7DmWYxe7QsbewgjgV5KHnaxdXkYFw761IAkCHURiuOnQduxXrf JYu5ooCKbE7B3RZ0CU09Gj+jlfnZvIEZlC9O+5SBUCQ8wYSMQz9ev9WY7Y2jaz7pl3AnHUfnKGU1 pWvq786itvJob3xP/WdHLgBfPyYvm4W8M9lu97O6woifa8TChHx/RfHd3Vac/mAlY07A7CfZlQBV PnppoDmonVwnQu5m/qyT/XjLRH7q0+95N9Fdq+QZQOqziFlO3wsBw5gTbWq/hPOeLzb6tMYiTNG6 pCi/+ei+3iHr865BI8J/PlfUUAD3mQhd4rvgtLFkBphBHoF4oHN7JRfXmLhHiFdu0gs46E87Ax/9 nSq8eeMnrnLR+leKJMAZh8s/e9VlMbWBdbU6ss5Goy0a+crlDlsF0tunJbPdsqSQ3/+m9qiEfkQ8 +Zln/HeZaxucXoH6A4TBurQGRqtzonIMF0Y1PRyu/GDVKIcg+falsSj5uHU1SxwHBsBGUtZiN3bs Q/YRlZiopbbflWoHyNegdFGbP5Q4rELvER0jgK6V1WIud/P+O3v794aSudyHg8FtRne/Bw3JHisB Ra8ugmXwruE7v0z3pg0JtCkZj7DR9MlHq6rx6OCp9aWKd9A39KePe2q6sTIbwQShnwhbrs6IXHBn hP5K2DFXqfBi+mwbPSmNsCZmyi/b/u+KrcUK9j0fua97VYZGWQ5tXy1QkZWI6iGmGdDUdDor5mph 5U88LjOHCPSjxIZLbDXUK8vBXzK3jWds2fscvnPdedpzbxwbB5eELxUcWURcXssJmm9mO8H4t1us jtkRKPkIdz6BKJGKGVGQWRLz3L6DzqGoo5eKrQq4IPcB1vJf7wGvaZneUaDA7nCvt4KUDVXmdgF9 +mljvNJ63u1sG4WAfdxwINGsNDVRo2lGa3VB01a/xA1JqB5v/Rvb3J3SarYNWdSUttsJm05UXgrc LMLqC39RuE30UI0UDARqgx2q1calv2o5NIbA7eiYwRl1L1RvY91OONaqfAidZRL3Rck5+n8ChL5X q2zAl1nnbZAyYoNoNWc9TycYYNfPKOyQjobdt9JGWdg+aitiGWAYk5sDmJ7a/fqNIx0p8hAaSZTC 5Iehx8eC+3cohwb/ibmgsJkpNAiqW6b+e8Nmydu4aWEE3SbD7TF+o2kAuWwsNUuRzg72EU3NY6hw CV8M3Ytwd1TscqVpJNV82liDirATeGWg23dYfkZ9f6odp87+5wErD9ODy8enZ25198Y6WINSW3Pa TCR1Ggn9OueodOcy5h8vOlspggFFQAqRTjHhU06jYTdE3alLaUJoBJzcHCcd5n7sK6WZnozr1RWx 0WCnbqQHU7KN3eH6oBTL0abTpyYb6Xw9w+XUbsMQXcgxJiuLWw7pk3HzugUIhc58AZV6T1DbQZZ7 Nh1Yu2DyyumcIEM0a1XHOvd1+qTy8trn8KOh53SaUcW+MGQ7/ah5GpA/huE5Y5YXkhYuMw+72e1b IVl/MNdlD9J2+XVwq3vvF1Z9Oc7iPFmzYp0vZ5H+ijXlou2cgtE1KJ77wV5pF/27y9El/9alPPZE /UbdPF+NCoIzzPOr42hJy5cDjxrE6ySiQLnPUGwpFlBy30J7QVlcgMYC1Li/ACHBc71omfIeySoF 4PGJtCtw7uyWaJLd/Aa/SPXo9iTDQUbVTmS4ipF+7EYuuNozLZBEsP3wSpqVhcWzO0g9y6Q06QHq TPwj0tHmEVu9T0GpDGTChUe6JokI48TnaSaif4xzv0sb3O3noRD4sabRO9KjocNxCGFDYpS7aC7u DFzuz6/Kwf1ad1qQpGrWXVfbUZW/8wdt+s4wohbV+3CBEA8LLrRTYFaMmxyNgsHy8VUn1x1wpC08 gKG9Zwdjq2NLh9Wuvu+AeEgIYTtF4X0dqdPFsvjtlNuwnQhrjb6oJ+bK9VXQyPkdp7Yrtwkk2aqb GClJKulAUirOAD52vPVVoeSXxiK018WouM2MPRJJYgvGuq8jVT4sGO0Zelmg7M5S/o3kdCMNpkB8 SNAisH91XKiH/1zA3A7ay0fYKvNwPZr9pw2w9tEy9DOI2FdTy+t8/UJklWjqehU/YelIAoWLOjcm lj65dldOQw3SZHBQIEc5JkNNFSb+4UJ3f0pMzAr2aN/PqSZ1qCFia2g20z0cAUS6snnI4/7Kk6wX S8tqXhsXB351IDEMF27FhmgtTdn+utFEC1ZJ+Qf2g/JAf+0ZTz7bQAmnblsRi8LE3AEnUxuNiJW5 uHzIdtX87WSTQpsE/4D3TMkmdUY77+IcH4KXbFHVlwpGzw9pNeUaFkgrY3ULPSqTJNumYIFwEIKI tDEMj5/SXnLaVJI1+WlzEQMV3YuMfpMC04m6/SK/NsoHA+hKZz0XPW5m49ikQVMCC6eZhgXrWprx SCZe2VOKjvGcnNfYxmiuhlgrvOBJZMinai3DFkl/NKQgVoNJjP/cmq+Aji3qEzLTRnzxCBNx5s3F hBtnwAdseZifglWuWj4RSAa1x+thq9HNCtSc4cJB8XL1x1FBTGuKPtMVmJc1xeWdlmMrOyF5uYEt jAmxqy57u3H9Xv+ztH5WyhldY8ylc7mlJntaJt6LqLfO1KBYXVKYvBj45K8rrpBbozJwc+gfY/kV R14k/6/FGO2PC6TxlMz7MIHFR+8N98Cc9995NH9u0DxNzy5GwZYYyZtryeLK447Y/OoTIz+okMV/ YQ+a1F0zLvzd/EWCQeszG5uCOHztVN05cs519dD5c2hPz7nQoxk6YL/XTlL6aCUM+hEDHbTLlB14 MlPOBM+KOuA55YYua1MddHdr6MO0DghlYnHSZOh9AeaRK0rYghgvUgcepZ6RTh1Zbn9FlhCgI8pD 3Gv2jMZSlj6O6ACUkG2MLRNuDuDiTQDrS/Xv/0qlFuwwdChYEmEIw9oECgylcKd/qqsaz3LnUs6Z ocqHddPwpvb5pk6o3lJ6fjG0buHCvy/mjALqQJZei47f4OVPXs9KyrtAqKZ2MHNW8b+Eun6i321A hWMX7FDHD2ufvwNHVxMjrOSRw+iUPs2otSKbeXUrvbIPq5JgmX2p/CvknordLmlO2bjCIdIblFyU a2BEqTvvl7XF2gr6cswhLS8TnW4ezLPiLUHB1WyXYgFT3C8oISrINXfiQTbeicevPw68y8fRpgL1 6ONEbeWtt9J6qKVA+TPLYV0aU7CWVV/DUavmlPoBS2Nj+fSZxbHz91OJzDR26Qt/SS1ZytfEgEAD BxFO9l2oi518/KOmSorgydq/tApnZyTiKgd0AjuRIQvCQAstpNH+FmSO7Wm6bomPlmhvS0+ezvlH /4RQwFmeMObF71P0QdFa0Pl7nuFSveoXC2umDdlEvw5F1J8i0JYNRrApYYLwUB/Xbg0PR6S2Hu3/ gwleu81nviAKhUaOWb70lghdCY/EX/Ks+ZFhWkTVAHhGc1uJ8gYTtAoEXeHmBlu82YUO7xJMNGFR 28mTXl/WXKHdoBoWwKFxclLuL3G96sQ7uQaThb8loXwxa95lhcG7dVS6fe+1DdxnNm3tqjYd+rAG cvOy6bVaF9y2KhCfvMf7pqN8j9AFBQw1rcM1k1czx7JYUXpyzKbnPx4nrNbPzlTHpmXwetvfHpO1 WPcNfW0veow24ho+VigAMydYiv8nTlnjdb1q+xJg55YLTc6n3D/FEG1Omb6kXi6DkImGCYqA+gfw 32zTetdQ4ClAZY2xVH9pxXfbZ0Md9fjoGkKeVHBFBxCsK3iZCJwtRtRo/6Te2GPepivkRC+N6fIk wynCLicEkKBzvIgKcJzc+dYThnMc8YKLkcyyfq9p7TXOSY1vUMAyGDXtqzHry6zS/JyIaNFuvUus WSqSefFG+QaioDjBbp1+gJfBX7zYSGA/RYdNnYnY0oWrLBynYBWeqjlIgfeQOGhvXxG2nj5j4MGC Ls7849gvD1q6Z09/8/SjkwCzCEc1LnKrXvY2GbluaoLxoKXIt0ORrHm58CUwfknxuXYzctQkrbWt b+g5ibM14Y7Qo7hGwQeV/FuuZjET4X51iWrexX9QhB0UHlwP4MlzAZS+cuggFIuls/wqOz7qrud7 hM/NZhas/FsgCgWZ2djyLiVkw0PX+EfGlrXeSPDgQW9GaoGR/E4I3Nxb39xIlUQP/nqEArOQ2SFP YqOURlZyen3Ug2smdQHnzhVmSODk6G6k92c8krsZI86M4bnyYVksuKLRK03XJ7XbXE/eYl+ovXmz IPDiEqnCC7lV0lmC3DaUJK1Ms3ZwXNLpzXWtZxyO3OjGW0/QiNM7q4Wi0ucL49RvRFeNspb6Jg4M L9ZfHgT1TOgp6QyGXQN+lQDUyzkavU5eVsybqCgB2xnODLjMU4WMmCBXmvDpozycffXKf7I5WaZh VYKTTpTqXgd6cUAOi8tD/vKCK73yOyavk76Es1hAe0j0CC60J2OmAk8xoRn2xO4xiuBWkrS6lND2 2Dko6e73cBBqdRQ/svIc4y6NyIP6kfE+kI0+1Tp5pkdDj6nsyA+Y/uPxB7wihWhHWwI4wiHiOWS7 JcQztTS1K+ulQ7d4grvVJ3IPxr+y3mEd6paLjD3VRcEf6+sCkGt/3tGkLwL5q7YQUS6Dc/joi31v e2MuzIGkgTd+7DuLJ3WIvudimMMzLKRcQ4u7aeZPMZdBtBaBn4gTt4MOujZJMvt60Qp3q0qBAWFW epsg/njniZ4aWl+veZevMa6HT4cG+cG6g2dGl/YzKRf0B4DmNmnnfBBVyWykq9qM9oUW/0iq8ddW Cy2PjVpD7L2b1oooC+jgcsk02kUN7UuyQ/n1I9NWL3jqfYp/5eJKJx4LAHJAmQ8PNIULc74xGOYq IsSYFErXcsxPey69sgWB+qptEbF/6r7ZE/d7fCQXkNDvo8KbvD2+dVuUz/rCzoQNgE9D0gfcvoD0 C8b+8H0qB7WNDRreU/g5NtzgYjr20i64f4Q7FJUgMg/Q32j2YzKhg8eD0lzfexJ1T7McGpYWnt7+ j/hTRjlBgGrYvHEsWyA85/9/STWCz/T5utni8wucizRImOyKcmawVMFV+R0P5MOlgS11hIjkdAMP zvl7IPjsAnBhSAnMyreJzcvB9lIzevGG10Lad4C8WEEoZFw8FlB7EyK5H4IGplNmwnbsjjZkPehH 4zgMEHS1C/eU17bLNcTsDlLZC16IjJTWe9ZbUo/7xUuqBQQ9NW1q15EVf5SOt6BtOuOD0u2rtA9P bOhdxdqjwAUFxbuUvz3FiabSYLAlzSpZZ2eloVky13XytCNG5d5R8IQVlXLgSZ2W+GDS4Xh363TQ Uh+NR+Sn/a0yvCC/TzmdmZimJVcFtg1AdNulKFNG4/bbNrCSbWWqGhI6JZYaAvhVfsteNdM4ZZgZ b89yHKhC0LcmNpq53TAIjJYD+MMJ/MYEad1VmEq83JhxzqzO8Bg28U8fCmatoQJrUDFxlMsa+Ev2 eqiyvvJR1lyKSAuX7iWgdnHSj9bUxziGoqqFsoiepVynTr+6cBWrM6+MNbsNRW1SQfer2tvOwW26 aowze5yRsfwnOZmTI7zzswa/C2ndqCdQECAhmFpXn11DoK/xjF6+UyYuMbTK926Rxra9INN9bFR5 fT0k/PQV9C9CyfhF/HBS6IH3qpNhW2WFIBNwGOZ2DUpa6OEf1vPziRkZU39++XHvdnGiu9ySqqSD /a5MOzXGUYwKPmprGgHuRTLZ3giKNgAaFzwIlpYtspEXszd43cySkQFH92cHdAdtbkyzbyc4Qm57 RXof2gvWw+gP+WQIwiwODNIOkX0AcMXF9UjgGJLOrAwi1HJyn9q28dyrjU4ugpMLK95jNve4zsIv TB50d/QtPh16BXjupVh/bGmmva8Yi3I2RAa8kWyg4UQAWeAQ+a3Oe9lSdq3l3MC+ltSUoUhc5MLV 0uf7KsS53IUI3pceWE9KVTA1rUVg8nAOb5UwSmDBfXBaYm0Pg/v532hVvcZJKtt9WF7nxLVU98hS q0FJrXrdEffw57ejcvI9SmIJBE39BUG7UHJGchnoBDByQoNh6pVGxa9+1s3v4H4o551hmj+0Po5u TmwvUJuOUoIbazJ8keuuvq17cMQsIX5CbV+ARBmvhAOgQbSOkidNNq9TuyOoLgC5NmtzU8w4YbcG KYjNhzU2JqHbK7pMrkVHeajmZXmQ49mTd2PaGNijqvske+jjHMCjW9oL8v3Snett+ccHk8kDzWud Cwwn+JWB/AraTYDGxjaH55A4e9t0neiUQGwaNv/oXFA6DrsyUudgAJZpxtrImUKA1k0r8rajBMkQ d24ljZbxXGLCz1wjVJ1/e4jctwoiX/AVrvbbkphjwVeoPjp00eYszKebu6RDjDhStRqtuk8LkbYV ex5HfNi+HD2SJexaJuaztaryGwikzeFKqn2LjgQPz5pXcBBnB0Qg2lnRGhiqeDff6D0UdUPI6X7D QDOSRNQyg0NrZEezfhKGActzY/0YVHm1B7eriIyocJgVHHPWGl+8i7ylsJ0EnWxVuv7AE2RAfoc3 wJIV47KvB5wL3MqFi7+0lMu6ZIg5AfO18ku4yePJ9KchCs5TNh32d91BxTzjxEWdFZSza3IjN1se 1yu9uMO/Fq+XCHjX+zOaXlzg2/ixyQvaUf5jUYLfk+zXIv9mE0desGOT7OTpsxSQGVQfSPBOkoT4 1k5pdnTNrsqe2yFjzJ75mnO4pHOpsvb4S7ehxGa/nYrKagvi9tFhT7RGTQZ/hGrL6E7bw/GrlIUG L1ykca1lvm/jwtygtc/kQ1RcgcNLlrd8okv4+gT3GO6JJtAOenizX/DQHgOd8W/EDQ60jAWHzpnl z5yPkXU3ZsQotVpnjDE+68BqWPypbTyqcprw3b7hdfiNF1Fl5o1oxkmXAHxKwFblj32rASpEJ23N nGs8C9fL6Pa00GqwP1p0sygRzBKjBVEDxbuLyTWxUh/VL4iWetEMkGm0FhlgsIvvbg89xFJE53Fh oeW9Tk0VrEtSqaO5G8Qi0X8A9u+GIx5aV6MBxhRjphj8Z1YOkQIpgdkinMvDf51siZtuEaLNDaa8 t70SrhYF7VaMVg8g7tZuKvzKHSsEMSqStiJh4XHOEe2zlsnQLfiTGQcNO28RurpqKcUduYDQWYGz iP4PWn0RXyQfl2oo3A+56v+apDYqEuepw3R8PHnOvxHKK2ko9KHYorCocf+DllM8EjLyGm28V9Mk S9tnEva6IHiMufTQccTnSg/1nUnujJ6oLE0dnK3PNVy2WrF73abQzS9hVQhH6Wn0vJQj6PHnFL0v IoOzNa1sO/VmX3LxNGS17i1A5xg6CXj8Bggh+oWx89FiwtbLxxzWWTcZbUKgqWtkKl3BOOtT7aKY 9SrHJYWNUxLqDmQmXiCDa34lWZj60TKA5HduugN3ET6+hWFMefm4OjZzLSWZMZWFXJWbdJPG3tk1 xw3fQnBbHAbyl8OowkrRvyUXmB5vH6W1gQORa2uM8JkW92SQkoGAxZrubweY+SyWxJH4wfMiRhhH ZjQzZLNqMytNk2n5OF1OMhSkUyKFQee12FIh4y9uyxS5XfvV/OX0IKPSOzyFKBBFVaZjYG0xAeN3 Az5tVQccZQRAMscf91YNuVSzbxsd6e8wMupSTJobjueeiamZHgf7JFAwbiGmLYhfgcaGSn/cOaJx 9Q4EErdMcxCgyw84iYW2ky5WDwFGwllZBSFMzsGtmnZNTidQL1SZOBpUgkUo5DpbKEYOEXvWivdp 7LMNdnekwl35jyOM2winDHtg8/h//yhelyFVM4DYjevBWfE3EChpYHjyn0GeynmUEcWMG6jY0ySu 2eogFyKiQ+lNS5o4HPOjTnDyzLjKqEFZEQWLkfSQLilf2YIkZt6jukMpJ0JAGuZUBzHWHhkhkdEY 5dhS1apbsKuDLTEv9Ej3mH9rhYf7YOkiIux/a8qafE/NMKUKum93Xd/qJzFB6VHqDe1bsctsj+kX MwvTjq1KmgV3Ik74KxHtO9cCs0DxVRLgV1sAcsdquRdFUfUz5NdKQIOeWKb1mDDtW/nKZ5aBF16A jc0g47Y8cDrKgDIKJpUFUd7G57nz/Re/yqSbKiROYM0fBbN54z7u2W1KEdoVoqru4u39rnSAz3Uq lYqlqH7V7queuObRZhwwiA8DAOTAevvykw7h/p5PxGiJGFp0udWb3ZkZb12eS6sgF4QOn4OIouS3 rSQjpocZqSj/uswVV3b2tFiz+79DfE58mh/B2abSDWEEgmkxt3y2PSgiZ2zw8tt/hEAZF+RH0BSj /M2wkJC7lLJgleNwqphxTVEbAoKPGxfXULOZ6BRECW0FKXjf8zsVZ4QvXo8YxB0F0VQdPNeXWqyq 0Vb665P2y+i46+dT7UHj2dT3+Oa/AgTckvTo03jUQAOK6dYRcE/3AruYJEW1HzW7DoFKz6/1YNCS fw9X8+kG2hiagEhJXpG8i5GWFcgmJ1ml9TqauCaw0ZAQ1pY+thHPAcvUHlF0A3gDJQYeJwdJ1B6Z OKobNNM2z7Uuft8VZajVBhOp/7NSuG91Qnhtsord53fWruNhIBiI+vknptYOynsOhn5XYkOfKvCO aTa0JOfLVj9SkdFyI32kcvExZ1mqWkEgj3ApTERofL+eiGhGoOFyjvQ3zTHCeCdHaMTYWMGBgcvZ VBMW+PFQSROw0Skhjls92vV3Dg1CK8IKOOHpPvA8sGM07f/g9/STXjhiE96Ns4VM9Gy3BvwB7tZf xpWXQIgiSRxq6gXCEHT9po0f8QK6vUYVI7Mqy+5O5n4+QGJrZtLm4K/I7ZG+CMK0ztFrQVPvGmN+ M04ENJm9grigc7GCb43mNorvbmaHcX5AN+gFTsZobPBhlDQ1RrYij43uZ+HsmQAHUSWbdt+X7bU6 go6SHkFo5QRm8W27EQrE74ZBimkb8ZRVHHsstlUTmVR4Y5fakakEHMhO53QOz2PPSMdWv2lKYK+V vSjoXTSwMNV0vZvJ3Mpi3qyBAgMgs+9OqL4VEM1q0UhCs+uLlrTZ82X9Mff1K9zMfxY1ZgieTCIP WRGPCxop5y3qbELY7a4dfP7L6ngYwJFlckBcZqNaELaisN8uJo4i4XHzdA69oj+VIuZWMJ8Y2MgB 3vZB4EiYZl2jV31BBtpN4OjJLcKxZITXPAgx84X2iecJ2/ovAylJP/RbJr92zCgMzaSDPsiaagsX B47nSYFHmhuRGkQ1xjzyictKGgiwIapxK1AU6tlas82pb0U1xH63rlkxVAivFV4NB7i4BWNnvMAM wlQBr2Z0ka/xzkUogBNDGqcoack3+cx+Er34M/TdqeAdMSiF/d+DZF5ttWs1nhETaBeRfpRfzUUK KTa2g/gmabSevy4AVQ32TWzhIYaHnJ3BV2OfsFBygO9niw/kgPtH/gqeqHCtgm/CG63aM2aABh40 +YTIW9yZoXwnLOWfglbwnfKeqZEEO5kvtpc0KlKbGjboWhW+BK47F8VovDmp4dCFnngEnhOYhMcG eiaxeNRiVPN5M3GjNT907Rs7oLA/G/2BViqu6v3KgRndEFCs00/lKi3/m8L4jJHUlxjzlPQLDMFU C+dCMSviqav2RXAPuxPiPMg8x8Tqk2RwtUbiAsd781lW13BLSgQnwAujgC732Ra0Dk+0gpZgJ8BH C172pnxa3aSgwxrrSOeyenqbIXZssuVoWBpSo8vGINc3MdlCBaw4KnlE0ApY96QnClncg7x3qZA4 gkOUqRtZNGI2a/xCMqtpPPzvVLOLK2tOMGFyyaqPyy0IqiHNZ8PE2G3o72pbiH5d+if6qtUPACoW ++RMf19btg2YkSpq5YpsO5tK8Wa9m0yGAeinauRxI1DuvJJAUnZfXzKIz4nxDtSd6KnFJL6UdPBA KFnZoHkpvoQ3lS0yLFz2MrFOJdsQNf0ZsnRWaw+/yCBkR8jyxld/WIiaTDv1SH1/I+hDQ2sJbEy6 f7iQAisUc/lVnFfZNxAewNzRBp2qz0B/qqETB2CvzVoTkG5VRGutgY+y6D0MYgjr0BrcIQoTXf5O iS7rBf9XbVnM/+JIjypOp2GnUDdZeXLS1c1+koqOME/7bjhkfdg+twdqJeqGKYbDqq8LemOM131f 8d+CX203bmUHj1dvocz3ufLYnUYx4FDcPdRWfIHqB1qZUQSOwUQ2lIz35hTYs7m0c5WgpW4G+f0T 0rR9KkIp4YJduJmJ5VS2mIqAZbW8Xhm5DcQidFqrjiwJFM3msTP8XuPwaquZed9wXC0Vho2So4R1 sZECNStyl/dVBcqng7xfOmjFu98VRkxxPTAibVDmrDiweRWb/woPPMrQigHv25wxOPfuZx0PDNM4 m9/XCPNsk5ih61+EHOz2SGTkHSmAzBJCRRU2O9jSBOznrcSjrh1nOxOlMScmIsb0gY5cb2dBDjr2 yai73z9UEukbYDhyycDEiDHY+qm/EZtOPjh05/QHOiYsNM98nef4Xg5lwuQNerzdd4CHS6bhz1DK ExZGdIfqKmk1I4/emUMEl4yIP+3o2qON+Ved6I6ZLZPm2noS/hXsopRYpwPVhuWfJ3AztweJD7Uq 3sywijOGFwNVzOxsT8KUleueWc62pha3z9F2DQVikc2hpw3qc04IeHcZY55RZJCBP7pbC01jFKC5 2hNzoas5t9bKJOieSu/coI8sBX2qBUN9U8FTZJVLIE4P1BunFkooNEtVz20nl5WmZfnFa7MYmIUx F9hBJEF31Oayq0CNY4yufdS3HyxvWcewCSwyDH4jmXwtA/6+E/SzcQPmSe6xQHjUBkhPOc5CTReu dL47EhfSEPjzpZKFdvuAGqm+XchTWEzUTRQgfxYN46I8s2mZic+MG//IsJXydm9CQH2GjdOjC3ag Ol+FbpOmfj2sBwih1cEYD44gQLBItQBXPgfNBW9dmlb270gVq1De+KuB6VGOY25UL2Cda28KYXyM 16SH4P/viKwnyAdzByamAfQC12gN3etj0/tsavXhN0PR6ZxMuuaA/BUaMBjkcgp/2l75XoiXRFSL oFUi9OHEMDDKKMRgEmxlD2pSy6Z/I7yJk/EaW9PKSo47U2mb7AhIAZV8CNI5+XdEjwYSVk/bpzwB caD1b7LphWGpsF3dC7pOul3QEmnlK9ExmsoeYXWKTDnqAjOvBF0RKl7qzxCD5cmF6QRi235H6yrY nAZFCABBQARqAcw8vCbtJPupkl4MPgzMoyEvgKCAxKORcNgM2w6NEcUase+6j7XkeyMNHtFRwh8d dWTG3i4tw/w4C/RfDgIGAXN/rCCUZsgFxvvUcCYQ1P+6H2m+L5cVrW5SWns8GOC5ER6Fifh6I+JV +51rPM7t5d5GWDF23IKMDYyMjQTLhIGDHlFhQM/OCdC86VEIFKMNpQtB/WrTn1dSJlGSSN7Qiz9u ltY/Ern8UKcBYZFb/BQOVPsOvi4DzjKb6QMd+Vwh1CdID1yaTmMWmFE90DRAyYVzDWvo/tcqbE+z lnkPUsQsasoBBAs7Mk9tYZd7qcI0DILGvd3UHvpxCJU1RxkN8aK0mZUg3BDR3YRWCABHPVppRusP eR5ekUPtIygptSLpVw0xdLPvndJAHxc18hlipsHzOFpx0eu2RmXOlGIpasI12AlYtrPcphheBDHz FbhsTyOK2gFu2daU4L2mKEWEHcOlJ72N/VaxnRl3jUWACd2KIp1a+wFBd7Mf8VFHUGt5dLMteLU2 eI6zk6S8X1vCS9PnCXwdgVzoRXR/xmnnvT6BxouricNCuT7wQI4xMR8r5qT07/pW1p9s0i8T/fTp VzzH4zBU5meJFvz+ERaNDZzFshSvrjo+8PkSvGnHpZ5SfojKO+mXshb52pgxhuSZp0O/fq+rspMO L+7APZMg7C9m28OgN+qDnINFGzDEGmmKcsbvbb7RAZxIh9k+W+W6WFqcyKBViMhUcsj3jb5cVJbv WUzRytw9LGctwa3mu2f1HVtxjN0/kifLjtIasxnySMCNAfVfe7JqxdRbrKQ1fZuh+OcfmjwIiHgm qTSxguN43E3Pj2gprSg4d7hNXJ4C5avIiopOs6QVbzOo6zTXpCa+fLyklLvHvlEEQyUdHg1f95He wnQCX3ADd3mwe1/PUSgrDhCLtanoX/u6o55PSUpedGAVODaJB4i89k70M7rHPj3iqSJTb2pqkins qtN4ujmhIlCT2zHl7tRuaDpjNGrfmj1+1LrI2G/zvjvLEMwq7jEEuNUmFGBErDOX6jLbspgz9pq/ tfK5egFddHmo0E6W4UK4CXXPPPll5Djs1joAoLwlI1h4rlD0oHc4zzgmwCKTMHgahhYj/FI7bU2L BnpE7AjW+uybe2V9nXW0akx1YbPvKMbvdBPLvDYTb+9prjeCgIGaluzdPpBIxP+OjIxwRF5PAulR 1OdEmJhx3Q8vAb0dsiU/NaipIrCK1/pyISMLKzIRr3Q8RNS5+7yYax7xL0757aJnxaVmgbr/a0vA 3uCnde4ULBGVNXERcrDllqzYaLYSE9bjVxFTRgP2uzIuYTAgDI1LmXmyxyFMhtUx2OUFMmIYuru9 Whq/TL3o6h7i8sDajQGQRkZDOqsRJsuWbNqM3fWLnrmip2uymXbhgs0Wetiu7u3ldfZ7PvFnm3JZ FqJAWGVQCml6u9VWgMHGXPdgnjeyXUiGptgQtDZaF8eD75zJTWRCiFgnNjGgC/T29hmOB3vJbvw4 q3b7tbD/pcLJw5sTWagcriFKAILKwfk6ugCX8P8mjjrshJ/1SWc23axnvCdAKw2A6+Pmu0cUDUft rRNk8izFMSAvuRQAxX3n9TXqIx8gwDFV1HDLetNGj+bpVQqScb6LMwEUHwYSBGlUjohKM8AxdXil kGN1T/JOuFqgLSuoB7wKA7gnlXQ6f8mQLfoGxgZJ7vsQy0MZI5gOJ/e/oC5TOkniZ5+Vm17Fe6XD 6Q6lVHY53Xz4wVfBV1n/vKJhGXEKg1jTz14S7ls61T1pzmHEenQoFbtK7l7FEWAQSCRAi1pLjKlj iNaSgzz/TKl+/55XFUHuh6UKHs12QuNpIhlgw7mFaUOe9i/PSVfueX80H9617su3J5xfKlbh2NFb jZevy/zOWquB7ijOyTOD/MYqPAAmdsUv33UZCdBDDkP1unjnigG+kgYDXFjWgYqWgkf8jRv1nb+8 l7MMMdgBVonarB3VdxKt+fr9odRw1qag2gMmeTJQ2mJM20V4xZkyyj6U26i+FEbi/S03yE8GE2oL 7D30rbfFcyiHNrZdAyTUuxJ+6TvL5/xcvBImtiSZ8fhLwCXPf3hBnO3MzuMoVynkT+X0tuT69KXg BYtNXG6pXmX/M+AM0AB6EhqvizTY/L9ZB8F8UXMfsTh/9sbFzHFrWvyt5ViuIWTMCVNitlliqFQD sYtotuFK/Y43t8QC0rEKphh2qbIeSaOnn++Eh8oN9Rrl3Q4bBVTAJpunWNYrQj8s3RJbrK4JqmDx 56G8x0SfaA+SnJRDkNL+dLSWR5bjp8NIw7JcDTHzUQSYK2NNOvOV3GWRVziq4URqne7BXVzbl/fE hpNDLGQUffgSWRfhlLQzhaUV//MtaB0KjZbx2EvEkxLubwH7g5LcAzWMqfI8eMPpJKEHOF4URBE+ AEhJ10G9QUNkAa4NJ1wP2LUHhp3HKi49QkOptlQ+SZzOANgMymlkccJmF5l1n05OibhQbkEYKOiX fVanvKSyElYVukz3Q5uedf/hr0cQX4UqMOeELYqzoPRbTdck4UfRUKuIpzcApy/XcwBH5N/Amdvi 7CGCa6PBtuGccasGPWlwwPoy8JIufjEYJJ5Z9l0u5UIwFsNSO4V7aCWv07yQMKmIy0PRQvsM3kA7 FaARrMcSqD1laFE5H0tPO3qHadPYW6f7gGjBnjVoRZjqTEnxaDn5IEjHvF9oYlN2XgBsdCSMkL3I NVYrMWMyi+KccruGG82HIn8/31sPn5bsirDm6PQI8fNdKXv5Y26kv0KTZcgF5MgW8Z/kPFGL1IGi 309OqN4LFuvZJzZymg8/YrCQwzzQeiSu6oe4uwob8dInQpr5jaAw5dIgp+J8EkS+UZRxA4/rcCbn M9STLlK8/OFk/o3g/Dh8sOlUMMXVrDNZAPcPN7XRvdjs9SPds9u6sTDGxs4kD684G/C66HdVxKBc 34d81WPWKy0UeJOnNqsn4XZKKzIZYQrId4Ch/L1GD7bi9hi+Oi20cIcex0cvuT56qn61Uf1WZ78s n7MLSGlcO4W23jwGFWtcUsMt3o3AqX3qWAdt+OWPk3EnxwzD89f6VX3KxsfYf5U8twgAcy2Po5h/ JwaB330i7E/rMAlIXhO1bkPLya/BiwxL9db1Ebjl2Eh+mjaMJlpZ6RAIyp4GQh6cQ8h0njEPTOpm drW6drVSGucuBVhimG+cuU15fJ1uGN4m8/vlQP2L9sd9b5AaliSHHURw/+vest0282jHRWgr52EO BpTwqa60gXroqQIEMsRQpaOZcvM0y8DaH7vM9Afxd4r+atl7uFYBmxpbgyL6uyixZOTR6L2QujZM 8ch/PSqwybIQQftFgscmE1R3kYb4cLF+LswyZZk14ae5K7A3VxAX+Za0/tXyRIUYb7XEIvJGEWK5 +7M88BAF3QktmHzY09C+Jj9DPfPWVDqW/UQEiZyZrRG/7Ptg055MBveE/DcTQJrFPN0JFymiSXCr nNbfHdOJh030Js82CKOBcFn1YOn2L09sSZrPHMTpm90XB7QY4RPRPSm/gUFXviAeAP2O0ZcQGswo u7hZTIsv9ncK5ILiSEAYXSzT89rU7AvcjMNyj1cbr7bGxyhXH7VPn1IA+UDtXffhI+leCMtOK/4S +74U46OhMFKn08+T3QnTeWAEzpRsKZZeIvBnxaCYkNVvSozOmLV5/2rar86EQMdrveW8GohpgnHY tnnXBZsG/j9Rkjts59iOPmpT6t+5R71xQEqwJHswYW1lTaFQWl8ytDdsj2hmCoMvi2OgiXOuaank VjjrNNG2ExWWG7EtGHgeMvlgwQ+zAQNvGmkpZGE/O3DmZkxY3nIm7YbvMHtTES0H9oOC8gu6/ONB 6Oy8Iic4cmBaEQK2hKRAzeoOCphAif1VMqlfBw4DIyQE46xDmtzgbobm4KVzUOZRJ03u86I0GxTy q8WpOjy2/5Nbb/clFISzS6au9ytJyTUz5fNaVuKA6MRAJeemnLsfHsy3NiB3U98TcLq76VLOsbLT fMh5nlcT0NXVH8nY1rC3AOpnSY2Wb7BodSDiXZUfdkbs7Y9gDr98XBc5jp+4zoj7TNF0R9cJi458 ywr+XndehtrFXJ/VfeYNSjm3TSHUqsGbtlPeqqugEWq3nVUX4oE3pTf0Cjj7bI+A3KyZg3CNaVaD MPbKyHXrFQODBS0Z4cueqTJdWbi365iIq088axJQLl+bz2CsM+vWqEKqt7jq0QsIDzhFTlMT1wbo Fu68o/Cj1dKhtES/xO7894DJxnl1kkjMpIm7W+ytltKgL1zlUtDVhkz4nUI/NHjxIZhwFM06WeBY KvZxUMjs/5pbtHFnQUHq+Q1YZDnMuUctjyrS+egGmOJwgzbKA+NddremHjaN4bKTbJYj6iBBHjGF 2rX81wy3u+C8r4Av1PORhYQtuHZgEEpRTUnk6VbUI4aSBN1rYB/OuNSe5SwzDcLYOgu6eoZwkAOA 6fJCW9ij3ZS/GsShY2eaB4LV2xdcDqMNR/yPVr+Wh5+rYp1xYPYZNyUFC5zyfFrKUqSC9IcCG9Sd OQpMcz63YShl7MfEQE2R5uX9UOo1ckt7jJSM8F2SYwEqh7OVBn3fl+uDTimWDBMnHO8Pkj970rSf qcNMUwsx5iY9McsIAJ6Sj2R4wogQFU9v8JynbwJGmNKUX1GgJgQOPBUDP2m9cC5LqJY5v56oZ75c YreV4KnSCpG/ze7b8/Cud3kddBraxe++T2+AHoD7uOlyfsFp0e2GPJustCzfVH2GBz0EG9W1SJ8O uxyet4uOUKBIScDtV3oMwme4l+p7FHOOFbKL2bC9ZoFFGPDccWEgQO8bCWPhMn+B2KVDGmMdMDH2 2fDWThRYYxmQkpsPKpM9CEVzO4lDfqpPd2fcDXTsNCIF39pJNhH2s0G33qWUCxtOGpQ8xO4Mlm3R TA0Zz2XrRVBqDuB+SRgz11LshR1TQULWhZlLj/+ptP0i43xR1Y9qml/T1NZadhUErDuAi7dI9oN+ AtC3Z3jVacq7j6An9k9IAnd0ciowiEQr+6M8l0fMR2G+cCK/XK0XvBOsbr7SRxf+TLgP4jau2rjI QLXQGzi5gO6vj/VjFzuTtT4/tNgzI3jqrV4q0rMAnaOyGLeerhrC+eW7HAJqLGyweEAFJhiWY+Bp BOb9o2pUwgdvZeAgqNQU4z/X6x9O9Kgx/z8c2zoadvF8nUWys3tIc1KGjVN8bsyU2AxDCJKTJXAo yj+5KeGNJDlZcZRQ/m2sxFSwpHok9XkvXATPRJEuu2ANMZpvmr1lTfZOWzDSVatw2KdWqd8lt5VW xuhpCzWCKtSYZIlNqjuobldOqc+pAwOY89W0sAye0NBcDjvl1eD6QgDmXnAGFQ0LOMWCKojxPy/Z hanrQGw7Butr6ZH7zWvR8jqJ20xO289HB7uZJRWzYeYQEPsPIOhbRv+L2VA1iX0O4RPro/qr96xP y82gBFRFRANaA0iHpUMzMgln6/3pntB8o8sHCP6NlD96I51COHrrqgYgoXPKebwi5ekZAEom6oXS d2aD2VK/euG8idXqJ7cyvBCJJdlscFvh6EPkze0xZ9I6UIqdOMFxAYsijvJCtrsUEjF0sw/PpmsU Q7AFaFV8zLluS/6leXp1hRVP6boCDgFAI5MrrFha60citT4xT2yxl834A5o3SayJm1UhAD7Kl6dc V/iF00cDxkRdK7D3392d7qanpz9B4KlQGe5J1rrJwWSU4+SVUTuqI/B7ujrSDN290aOqQ9T1ocVS i6nmSbvgo9RfQBxXwyLt8MarwIETOJ7typVngmOxNKq50lx3vdCzF/O6zkJ6mrWzskrjr27lqkDi z/7cDYRDOZitSBoDHGTlCW+YAqo1Q+ab2AKhmBFwUPBy1HE1InK3tUUabSM4x0JSYSidLPlwnb/q tPa6Z7KZ/CVMLnDgAgCZtROHfFw3o5q1yfJi5PXj2Wau6YyJlhtQ6BVohd1owvEwMBl+ukEbo/HC EaC9XqWM5lm7lbyWT5HvHy/DYb2V23/YHo4Z2A8aSy12c9NliYk+ESa8DYEbFgjigwhwiqkzk9ep 9hjMjsbujF0j87hmYuEHs4MZzSLGDvHfqD7oGosnxRhKICgNMR/ykufQ8iyqkh9Rbp7urXodgEd5 fZf3ri2JeM73YhMzorCxY+hbrXCfljoF3WocSATe+GQWpHdxY2KT5259phPJ96LsYXv50xrpjQD2 BHgwN/GioU4/rL16AQ7bD+m2oau7uAauDf+HkvPWK7s4kSuU+R91M7wc2uXAUMCtsrXw3pUFWpU3 5m+7qD49Z+KBo0eq6TgUg6ITf32F7z1zSRiVPwyyt8yZrl9hwZEZiCfdPtWw1KX6via/unpEL5k= `protect end_protected

mit

925754b4d7806b0da5374954af1bb996

0.955203

1.808808

false

Yarr/Yarr-fw

rtl/spartan6/gn4124-core/spartan6/serdes_n_to_1_s2_diff.vhd

2

11,029

------------------------------------------------------------------------------ -- Copyright (c) 2009 Xilinx, Inc. -- This design is confidential and proprietary of Xilinx, All Rights Reserved. ------------------------------------------------------------------------------ -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: 1.0 -- \ \ Filename: serdes_n_to_1_s2_diff.vhd -- / / Date Last Modified: November 5 2009 -- /___/ /\ Date Created: August 1 2008 -- \ \ / \ -- \___\/\___\ -- --Device: Spartan 6 --Purpose: D-bit generic n:1 transmitter module -- Takes in n bits of data and serialises this to 1 bit -- data is transmitted LSB first -- Parallel input word -- DS, DS-1 ..... 1, 0 -- Serial output words -- Line0 : 0, ...... DS-(S+1) -- Line1 : 1, ...... DS-(S+2) -- Line(D-1) : . . -- Line0(D) : D-1, ...... DS -- Data inversion can be accomplished via the TX_SWAP_MASK -- parameter if required -- --Reference: -- --Revision History: -- Rev 1.0 - First created (nicks) ------------------------------------------------------------------------------ -- -- Disclaimer: -- -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to you -- by Xilinx, and to the maximum extent permitted by applicable law: -- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, -- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR -- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract -- or tort, including negligence, or under any other theory of liability) for any loss or damage -- of any kind or nature related to, arising under or in connection with these materials, -- including for any direct, or any indirect, special, incidental, or consequential loss -- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered -- as a result of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- Critical Applications: -- -- Xilinx products are not designed or intended to be fail-safe, or for use in any application -- requiring fail-safe performance, such as life-support or safety devices or systems, -- Class III medical devices, nuclear facilities, applications related to the deployment of airbags, -- or any other applications that could lead to death, personal injury, or severe property or -- environmental damage (individually and collectively, "Critical Applications"). Customer assumes -- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only -- to applicable laws and regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity serdes_n_to_1_s2_diff is generic ( S : integer := 2; -- Parameter to set the serdes factor 1..8 D : integer := 16) ; -- Set the number of inputs and outputs port ( txioclk : in std_logic; -- IO Clock network txserdesstrobe : in std_logic; -- Parallel data capture strobe reset : in std_logic; -- Reset gclk : in std_logic; -- Global clock datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output dataout_p : out std_logic_vector(D-1 downto 0); -- output dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output end serdes_n_to_1_s2_diff; architecture arch_serdes_n_to_1_s2_diff of serdes_n_to_1_s2_diff is signal cascade_di : std_logic_vector(D-1 downto 0); signal cascade_do : std_logic_vector(D-1 downto 0); signal cascade_ti : std_logic_vector(D-1 downto 0); signal cascade_to : std_logic_vector(D-1 downto 0); signal mdataina : std_logic_vector(D*8 downto 0); signal mdatainb : std_logic_vector(D*4 downto 0); signal tx_data_out : std_logic_vector(D-1 downto 0); constant TX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0'); -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing. begin loop0 : for i in 0 to (D - 1) generate io_clk_out : obufds port map ( O => dataout_p(i), OB => dataout_n(i), I => tx_data_out(i)); loop1 : if (S > 4) generate -- Two oserdes are needed loop2 : for j in 0 to (S - 1) generate -- re-arrange data bits for transmission and invert lines as given by the mask -- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2 -- This can be avoided by doing the inversion (if necessary) in the user logic mdataina((8*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i); end generate; oserdes_m : OSERDES2 generic map ( DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL DATA_RATE_OQ => "SDR", -- <SDR>, DDR DATA_RATE_OT => "SDR", -- <SDR>, DDR SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE OUTPUT_MODE => "DIFFERENTIAL") port map ( OQ => tx_data_out(i), OCE => '1', CLK0 => txioclk, CLK1 => '0', IOCE => txserdesstrobe, RST => reset, CLKDIV => gclk, D4 => mdataina((8*i)+7), D3 => mdataina((8*i)+6), D2 => mdataina((8*i)+5), D1 => mdataina((8*i)+4), TQ => open, T1 => '0', T2 => '0', T3 => '0', T4 => '0', TRAIN => '0', TCE => '1', SHIFTIN1 => '1', -- Dummy input in Master SHIFTIN2 => '1', -- Dummy input in Master SHIFTIN3 => cascade_do(i), -- Cascade output D data from slave SHIFTIN4 => cascade_to(i), -- Cascade output T data from slave SHIFTOUT1 => cascade_di(i), -- Cascade input D data to slave SHIFTOUT2 => cascade_ti(i), -- Cascade input T data to slave SHIFTOUT3 => open, -- Dummy output in Master SHIFTOUT4 => open) ; -- Dummy output in Master oserdes_s : OSERDES2 generic map( DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL DATA_RATE_OQ => "SDR", -- <SDR>, DDR DATA_RATE_OT => "SDR", -- <SDR>, DDR SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE OUTPUT_MODE => "DIFFERENTIAL") port map ( OQ => open, OCE => '1', CLK0 => txioclk, CLK1 => '0', IOCE => txserdesstrobe, RST => reset, CLKDIV => gclk, D4 => mdataina((8*i)+3), D3 => mdataina((8*i)+2), D2 => mdataina((8*i)+1), D1 => mdataina((8*i)+0), TQ => open, T1 => '0', T2 => '0', T3 => '0', T4 => '0', TRAIN => '0', TCE => '1', SHIFTIN1 => cascade_di(i), -- Cascade input D from Master SHIFTIN2 => cascade_ti(i), -- Cascade input T from Master SHIFTIN3 => '1', -- Dummy input in Slave SHIFTIN4 => '1', -- Dummy input in Slave SHIFTOUT1 => open, -- Dummy output in Slave SHIFTOUT2 => open, -- Dummy output in Slave SHIFTOUT3 => cascade_do(i), -- Cascade output D data to Master SHIFTOUT4 => cascade_to(i)) ; -- Cascade output T data to Master end generate; loop3 : if (S < 5) generate -- Only one oserdes needed loop4 : for j in 0 to (S - 1) generate -- re-arrange data bits for transmission and invert lines as given by the mask -- NOTE If pin inversion is required (non-zero SWAP MASK) then inverters will occur in fabric, as there are no inverters in the ISERDES2 -- This can be avoided by doing the inversion (if necessary) in the user logic mdatainb((4*i)+j) <= datain((i)+(D*j)) xor TX_SWAP_MASK(i); end generate; oserdes_m : OSERDES2 generic map ( DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL DATA_RATE_OQ => "SDR", -- <SDR>, DDR DATA_RATE_OT => "SDR") -- <SDR>, DDR -- SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE -- OUTPUT_MODE => "DIFFERENTIAL") port map ( OQ => tx_data_out(i), OCE => '1', CLK0 => txioclk, CLK1 => '0', IOCE => txserdesstrobe, RST => reset, CLKDIV => gclk, D4 => mdatainb((4*i)+3), D3 => mdatainb((4*i)+2), D2 => mdatainb((4*i)+1), D1 => mdatainb((4*i)+0), TQ => open, T1 => '0', T2 => '0', T3 => '0', T4 => '0', TRAIN => '0', TCE => '1', SHIFTIN1 => '1', -- No cascades needed SHIFTIN2 => '1', -- No cascades needed SHIFTIN3 => '1', -- No cascades needed SHIFTIN4 => '1', -- No cascades needed SHIFTOUT1 => open, -- No cascades needed SHIFTOUT2 => open, -- No cascades needed SHIFTOUT3 => open, -- No cascades needed SHIFTOUT4 => open) ; -- No cascades needed end generate; end generate; end arch_serdes_n_to_1_s2_diff;

gpl-3.0

997e2b73fec334613bedbf469f5ccdcb

0.501677

4.129165

false

cwilkens/ecen4024-microphone-array

microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/buff.vhd

2

15,490

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RAdCEmtmW3yuIMLzvz5lbCamyqg5eINaQFbMjHs+ixucClDNKHKZzetFoWPXqsSyg1jlYZEAc1yh WPQsgz5p2Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eMzZL9YvBSQiI/IJUlxzCjmET3lsc5Qww5knUMp8yVXv+14AYBTJ8VbvxEupk6a7amfSSl5osBgI oMIKR+nnRX4x7MaI99LPUTJ1acCkJJ58tVzvFXPc2BTfBYmbIOFrwB8ARMQGFHsbN/BfeGGOqVYq daxMyeEYTXuqp8UqwRM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block NyxVJqhB1xiGWHp8z67hmvLSGB7TG0isuFrjbH3Dt6g9lUWGR50FJRltA+X5J8MN+heFHzCrbe9o jWMAYY7JNTj15N7aCrOuAX2FRdOC67pxVjAwaNlAAmt1mKyaLVKXb2O9d7H292PbKLmrgh6OjA3n LZPZJfAYljNm1Uzd/NTEHg5j95pauHX+yML++twIW7hK37YpmyTr0CTfferVJ3B/NADkGho3jFEy 2CU6lRVVwHFusDsMrUFRFdQL5thVgOdn3bdwSpXCweBiZPOS/yMVscInL0mNEaGkGRuDvbxxvk46 ggPPV2ptT+x6zmcq3Ga34TKQSQF4sm6iPCBAPg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block sOBRhV6YD4wF2l9Bs97TjXCjdwn/NsNgrNcMi+HMOuk3u1dGY3s9G1VjbZiPbgO52yAfxofelLJy 9vU8n1w/Bb47yIl01KyFtMK7AWE7nicbcZceNkaT+EUd+QzDHe2ScDgBXwHFNa7mTyepSfLDZ/HU Y/XUQl9PxiqXQp47W70= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block fkD9+1OUmvbMGamswqYcf2bvNrIxKAtKBH0Nd9npDGvA0JiUOo3roa/1TAi9aumWgCzYFpe2nnAV beK9UvAnLu+wpXeNZ6POTh8zH4+lAZwhMV3O83Q94TFkF+RgM7pUcaQ8KaacbkfQzMZsktX/jKRm N57bRawyg2QKWXbIhhvIQ/drXMo6w4uKxq/QqmWRIcNAVw1vYTtYKp2U2bxhtEmbihowbI3jp/qD h4/Xza6Y+9/m9S8ZNhx7lvgr0+Dq25cVIvc8qWOShak70IUujuAe9yJtnpyXaJ5A7FIgB1Q0k6dX x13rabSRDtMIwXXbr+RJ6N1T4GHt7X7U+BdkVw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9728) `protect data_block EpRbq4oeZ+2IEePxifxZHobCEYasYGHTUDoSGiFUqhyab0NE+9k6zj7pV+NeBFhIYuz1LDNPwgcd k8g/LvyeireePCX70Xl1Q7wCGRmUcQ6TvvDimvFi1jjiKRTcKiUBF2rD9adYPh/n+j5Acu7xFhNo LqVWDfjyICbmmfMr9EmMkHizVoARyik+Dm3lzLe3BFFd3v7LWYUWF6IXCbIYhPaNAwiH48ihZAGz X9bwjRSIL5PV14EO1UVsGf9fViDg+tmsPXj50w02vdn8LAx0l0Qm2JaWqIR/Oz1W7RhX95tmgKij lLuw3pDZ/EMqcj/4oId+NpwDs0E+Xosh/O9H6t585RC3u/72Z3ZdC9AOnmI6P+PqYIe2BgRXahl1 xN27wDoa5uZSx5tFoSs+ZkDJ1TsW+GvKRsd1YM6+7HZMbvPY1sqNUGAEuhabo1f8IOR+ky8vGBKr rah216j9Ug/aSP5uo9EGCuRuC2faprpPHPidAgtp+zjVmqvf2nYoXrVYfhJ/6xcApFQF9cKr2V7J n+K0VRN3MT9vuSXBFXed7tQKE8HyFXu2v7x+RXmYBBv0swmgksT/C5A5UmjtzFkwRURYU3QUaYSh A/lzmiFCR89J5UpAbZzkONY0CDd2phefxWLK92uCPQF1ZMF9M5fQl40uBlPkHBtkjetXdpwqvJzs DowwDJ2hdH4xQgm/G5VnLS46wol1sz6ACKnKhuwJqDMVi/etZnEKAfqWXFLA877FgZfcGt/3nliS PYQR5/hUuAAZgSPszH64L+sp/7yPEneJHUKl09coEmMCjz0vf0ErfK/fKwhWkfyTafFqW/PKsZ0k /yNo4mQwY2EpfbgN+JSBXimLI31nVKY3HrqVkGVXY5YMnxUClPs5UWi4bHrmes1O0YDkxIgIR8+k YJoLPgsm9D5gNLuYFBkQghLYjTbpdw9lrfUWtUZtz4SF/wh2Y2w24H59rvBHv78vL0BiM1QVbZ6Y ffkMRcMpHojizVSYX4qEfZYRGae1n5Wz9opklZ5lB7vzpQiADHZN3sBL8iplyJWCEeFi6Zu84f3u rHUZ7AxVI80JjqiF0y8zszEwGnC1J1Cc7qFXxGqeQ+7fGO5gBRx0nutaFqTiXao3KdRHyc9rBsf+ fKsWqYdVkGuzdMW1JvPtprAEk7Ykij9pIApoptP8nE5cNQ+kUJziZNGkUG3Z2pPmrJhDGLkxBPAv N8OlIZoVCtKvrXYcXiKiD0Uz279+qH9dM4eQTBzDK0QFoCR+1/ah9EQKi/V1V1QECLzwvTareMmR l+KDtwNt3Zaq85RaS5DxILrHW0hmCHmnJD56WAHGJwoZecPr2RD8NI4l/QT0+kedRIA7RmCUOz/z ousCUxtgaMf494G4vQdfk0vF+HylQdF5TasgEEck5uZ9MbGiGvKBXS6vabjYrT7lLTNimap70KXy KJr8F4heNadVrhKQ7K9x3vlDtQ627JD+rFgmcuw3QmXz9yFztFpdbPuEgvboXhRBOc9YH09D2C1O ocfk7KBSnT2TSGKVjQbO5WCaTSCeHzmVDj0xfZNQ2XXTlq00hXWi1kkjjYZ0YzeXVwH/STFUoGKm scOl9klIx3qUdbAChp2TPOA+KAQfRebI34t5RYetlUZl3023tAbx9DssImy/L3uAztZoLb21syns +JOG4g3IsVnvU1IowesxDUF5WMvGAdYTJ4ljN3jnpiiiPrhS80/h8WgZ6tlEB7u7d3OEOvf3CfxQ +xV4WDakcECN6ZC0ZwhC/b1b/TSF41Mh5HseSdMhTY5Iw2wmbPf8SY0xFsNnSdYoWaqmkzHzQt4D L3kS6EFQBBPWpvPRtoSX+PVxrYdkJytPutxE3HV0w8nDiF8KsJgeX3Dvjb/ow4Ler6oK8zDil7Xa +DSgRqUFTinNlSl6GvRDbK+RnsFchoUWf0WP2j/Qg2iV60FH/RDus+SgsW5kXX0lDnDIHw37TZxq F7UEvcBAUeZ6ZhgUITM/GPRc/heLMoYp5Jae2D1VUXgSzauYgpLk/5tzshq716+3KnDK/bD4JtF5 AYciAAPZoQyiujRt3Y7nIZHes/AcnxCXxj9tFhQy6YhKJsq6SqvkoHGNG6qNsUy9J+UbW6p+Ykwl mBv0Lzp8IetURboLAWWu5oP4SiR/kpeQuHNbRY9LOEfQNuiL49owxaJMet48lBkwVQ23zwQ95u7x 5TNgAq6PCDRvUi8EkPLLZtaUJuICm2woiVheq2biL2b0bR/eUbHmLi6oJDQcSSpkAWh9wGxQGkqK ECOI0XA8C64QwOHgMrziAh9LOxA7O0H7sQ7WMQAoi93eus0GdWn6KojqzwKFG+QT2sBZBcE/Tpop 259dwp/BLqb9N0QGOVRMnHiL+amtd1+dmSsA0nEAYHG+YOOfvhHf0vprBl1TuHdkWu8Tuu1R7S9p DlGVWLEZeTOAz4AJ2PiI/YQ8zudRRiig5n9Dkls2FLXfCajYd5KswNTqIOFQHgCO9wkj7NTTf1XE 79u/DXCdX9NGjbI4A1zkhMFBfV9G4FB/S/QGLcWhut88gACYm9xU1B4+FavbZmiLERud6r+kpwdF 5lMkyc8wBgNFd/M53IuUXo/ilero73vDrTJHHPGpVfYtEY9xUmnIKD+W85R2BLbBSK0hDGMBsw0b l+kLb0uTXXAB4t9jAZjE7fIksDvIB5MWKHNNdeaQriEHo5dX2NyOPqJA3vvdplxNxWwwM5RH++tk ioztz2fJrjrZoe5/p4y6pvRbsFR9k5tf3UCC6y1qAkp/4FUPB5h5ZcvcmwWugdECbyqn1PtNhGVr p/pXm7DVilWwptNjx6Fu5L/RpfZUM6jK7RkAfUhhIHkoTpcgGSSCNGE25uUAbeeJzV+Adf5R+6K6 mtqdUHY/pyV5XNQHXTKq/TX4KtNG9LAZLNPeePgz6L5xv2JURbBZN2CR3C6DJXnncbZ4KgPKs74a LIiU8yFTYRjTz7hq6OlmeXrirKOuF9LIbNEBQP8YeOrYlBwiV6etXz6UrgaYgkaaNumc8DXmcSX1 wApCc3doyiJcWpqQtKAL0WkYdscgh/x5BwuW3e7IEMHXqg4reSClYRMBY6inSV1ySDEv2/wqVwqM g/tYVzvv6a+XzxwSK54fFzuf5Z5MyfjOAkDI9wNLkU3gxg+8+4kDH8kg5/B5nZfzi+nl+VcLVv9R mh7Cn3uT9Q4y08g8nO+wPytG2or7OpZBui7pBjAsFpLSe3Tkb+3ezdYfjLf8ABxIGYoXJeMsXZcY 6YOuEMDE4r3UyeDzoIYssc3SVO633LV6LxeVSDtsbtgFDQ6tkw2bvZH3igyKuzB/XqFKUmGxIxOk hShm1Xqw8I9BYpKvEZWqg2kXtDtNYQ4rTehJeg2AaH62lKNfXZZUeCPfcZnH//KBnXKZAcIUHWNH IWvzHzMoUnDAc1fpITLYS/voSyzqALGnCScAAlD2OGwx/XxlarSd/RDHMbEHEU4J6lZLpt0xIvLT YiPrSoyK1Xe5rCoMpZRNltjGKstuXFSLWUluymyhlcVJY547AmRD86kI0B6NDVMnHKFLouGA/qKa KJlQGw1CqM75xAbqQe1+5t6KH5lu3ZSCN0mo470VL0MtNCpdhm1gwH1uHEuQLv1qZwSMIwFTXgr+ /orj4BthWosucMe2oo7g3hoDdrJ6fWbQ8XW2ATtgzofUG/nhlRWObSWiQh3GTccO3MYlJheY6IsP 4O0NjHwzEfetp7OCn5S0e8Pwrf6vVNH5E2dfMi2cNy3iqN6faGicWYlZnayghWKk8fwUDnnXpNH+ FHTCW8zuSq6spQ6e5sFlV9W7lkGP0SRPHOub7SHvDJDy+ousS3mywtbhxynINMXTN9BoKA0if6DX hdtkmFaUQofRqQHhy0uPhcoG1iPMM8sA+WwppJRJX4gWx0UwXHZwwaR5GGRNBB8NDtqNojQSTnuK u5d30b/CykPRhO/eTncCns6qYjRSpAxVhDsTCEEAxWOtHEpTdOprP8XE3Nt0OtLrZeyoDgtkQmV2 Rr0gDDG5FS8qYJ81Z+FfayAufMMjJvYGmKmI/Qbvn7ID4PcEIHlvP9w9M2kzzlsJkuiSEnq2TIBr 32DU4L13wTai1b9ZBDAFk/zLwgx11q00lfbcNHd0aQbqTSF1YdbZjiQNzF2Yu3TmIrksi4WyqnV7 vtP8rAIZzomjS9wsLxX3/6BWD0ntfJFt3PzHdzUDaY0yRlZJ0zo7GHVf27wFizm9FioLHmC4Gj8R AVAqi6bci9hpi1ovSytNgUvqnvxQBFs6VWa3UaAApoxHP0H5RyK0FNaoBo9hH1Aaqips9MTCaW4s OE8aJA/bmeUdua0ertIGFmcwZJPoBjiVCXntnvU5nHnwfp4gaDN+pT6U76bVXplPcDicS7VdnZaw iujva29NYAHk21ShCHuX2mDVTcIE8FJxfjDMIvrea9a2ic9GYLsWzLo+kH8XEPAkBn4Ufhjlnfx6 mKIsdW1qazhHu/hPlF+XOL/KEHRHTBciQDrdYhDl8aKFSopxr+JollziZUcooSGam7WtdAnCLTjx WT20y0nepZD2OLeE8Nqnq/NaGwVWqH1yPXXirVxGhON1sSkpGsz2QCnl0IkTe2c7THpH6N/5vFxr oggJFmqYzwB/RFfPXPni0fjPBnodV6J0XnR5lUItOd0ez2pRVGc1y80YocvbpNGhKLhiYKJdcOOJ Rk620MFdZHynWcsGitg7TNMSrCMNyzFIZ8SP2CdTESk6VpsPnKaE2p4RWfBWwATn/1gQLGc8KAmZ oD7MFNc1S2C+/PZw3ZQ3V7soDSb1v4DhTGqBMihkamDqFRaaG/p414nVgLdagLpT2fUkfFvZs5rP 6e9IRjBbRgQxJGrKgvYZAZIzEfnBIRJ4cpSTdCdq6MXcCe0j4Qc7yJW40IEjOGuAatdbk5nDSz32 8PBZen2YIRiH/s89xkibpcK5bftO2WWK0l5fBaqMcsKqDVIOG4DtINHx+cuJuxfShKqETVBgQm2V uhe6l9lAt1NcnW9rtOuU9kuTAe7xdnejdH6FJfcSUa3SiANzmLmqBied7veoQ/xESAjTbK3ckz4K tr623VBDHwxVQXfgrT1bFJMBJ73f6dIuQGE4Se+Vic4qTD1kPbODp57CZQwU0bkbFim37e/M2ji1 /kKoSwEZmjbbJELd3uEGYVA1Xh+UDaiDFSnD3aO8Jw4EMBJWA96KG5et2Lg8pbNoBzjEmet+IgUZ N9PaV8GKVjYMBYh1Dbx/Gjgax/LW1I8mmGdUrKe7/RvVyGBEB5Itk1gdl+4y0yzYCYjp9kYLi0DO Iv/pkd0BsbqYYrUYn4WDG6Jul9I+NgS0xC+ebo2HN8geI/Qi6ZdsD7jHZjTnDZW4Fbwmm2FfHYSt RhBL0VII1O3U3DMU1VDqAaKvQdU9Uo//RQy3nnmxToIxUe4bkK29za3Pl0ytbzxTiYboeG2yZvak MwGhQ3beJf2ppyzv7lh89BWwQmqB8jXE1cfSQO8wUqHFatIMawv7HJZ+P4tsYp/oP6cBeXqrWWb5 f6mMAhbS+gas/Lg0OuKSi+BrsXevQeK4HdT2Zl/iHakQoFUO1BrvKcRzeAXEgm7DPrubM6HKK3tT 2OyHiwcYUFtyS/8mTHMrcXKuM3aJDyfZYmnd29+u3I3w6mi1Ptn8pI0T/SIm1U8u8ImUCTpZyn/4 a/lZDRWU57Wugv+v6i6ExPe8ucQcak/h1IFOepZnwM++DXOZ0jr3NvTf4aLluWxssA5itoM8CuN2 4iDx6sOt2CW79ex/tf+SxS39w8mIozwgaXHJnD7PNL8eiUTXo6t1Lf3hiov6m5YTnlfPJf3/utCI 84wBql+1hoS+0nXtX8xm13KGDXk3Aob+5DwNR6VaXaKhx4Rmtj58vOKJhTsSw8qYzmcr/zpgae6B YVhJOwTW/hlCGA0R3lNChLVUMb8kjseGV7NawlwszwYoR3YcaO7PwgV1LpPK3PQCVsdprjt/JBjN XmFWUsbn/7lWvJ5GB5rJXbFAo9dcQeEPVW0o0CVwTgIRs5j2Nifh7eJcx/rNGzGNRwPQ7dliakI4 QhRGXbuM7Abo37g/S8y1Y/rnsM1hHl6rSKBbhxvm5GPk4+p1+leLqoCs+fCeZlQ6RHnUmYXF8x6D pCGPZb2RFYcQobUPqdcNkAnRcTpgPHb+XUHW6e9PuUOrcBkiJH2vmUj5NB2l6V7xVV8wca4lW7nG 7hEsxUbwSkSwkWhcHar+nZHGdYfgW6gBeRnaky4HukqW+ZWTG1Af2KiML8U09SQadSA9Ho/3cbC1 vFZ6bCQY/MBaubkLFgG/20fqCWArXJzL/VC+vl6UcAtqYO0B0jVKmlthk/C7R58Et3fYb+8XjJW9 MA+kjynG0qQLs1qBFrcAYu3e7nFWJVUzE9bveTvaol6Pqy2alIeZPcetahKchwUa7obnGp8no/L0 EuehbZ/CAmeQgKpOTVJo5e8qhPPuKk4WfQvhy/11ySSpBN6NHQHEbCJxBc6st7tcvtf5paQaH8WI tdPI9d6xsREqUJVs2LVVn3O4vzmVhQWYh6Nr6A2tId2mfqqg/V9hKZpq0qxiBw8ydQuisv7mj6ND BnJ1Or79DwNW2vquTOqePgP56aO0im2XgQeVsIWmSHVYBYo/WwJd2Krp0Y+f9YvYkFpVgiyfN0ml pn82Q78t1c4Kt1HHj22QbtrUKEAjmszTaO5wy5wSpJ+Zo2yp3h6GoOzmAVeyOWl6PrXb5unlBKdM nUFqGcR4Hfd+3DOjwRjAqzDzCjuRObGe+O+7fJAYgaawpL9wHrp9Ql4/jDFLj1vdCF5D7KXtST/7 /KwqfYdVx2TpOaBgSGdSKYXbmhL9vMNanU/7XmcrA1ajhibdm0Oozjva6eVks9yTZagZXKRUJWDP uQIEh+y1wzFbqlbyAuBM/0It8rl1/g93YhZbHY4MXJAb3VnQ6AsnVFDhmYo7pD/wv1OdbQGXOALB ySsO3KQLhe07A0wQDqGIHLlu8WLzyyAOJHBUi1SZBEN0JgYrvmJDhkPpmfkHstOJgmBjHe7nMAM6 jC0ZduWT0PHVOF7j557zN+xkBb1dmU/98k2138a/hjol6KHd2czNZhfSOI9lMmhCMPLFcV/tRiY6 OJLm2euseWf06PcCeprfTDPqYUOqPQG/NrJDZSznaCGUkN6r1p/d+FuFPjml+guoFsvCq0dKpOTS 7IrVD66IOu75tiagyRT1aWUT/fjbFajqyru/s+E1/n+T59NtgaadLgO0TGWKPQ3ck1TVS0Ei2JZ9 naW3fwIXsryNaynnh7vSNlkdzwUqSp1dzA7+UDI8qblxvfUPmLWRS/qTfp8bioxvJR0CKzx+1Jt5 /131yKXP4Cob2/UrqVr66pDel6lGkiKN4wh9A9Z2bTxhuMQZ+K7Qpt3bHa+hbCu1AmA1o8p9vZxw M0kdHUl2chlMZ4Xo1nduvxaFXpTIVPYSrEhxz6n8SdfbnghuHcnuQGhjazOUj2dzFSUXvw66emuy K88p9yh+vhrHoDdus3noHg+9h9onwjMDY/I69EkIuYOG+evFlkpswcIiRYbCob0pTWIekmf4Seww V92cH3xulC3RwgqH6eWFi7hYhBB8R5/lRUPiqhLS1ReqN0iGUrV3pENhwoBK5X1pDYSfL9XVphsH i/9yxcRQZKBx8VHRRltbS1CZoH+2mhiTu0rNO+lQ4eBUlUaGXJVI/L+hmYmAbTg+DnyYJmgSU5l5 lDRbFc8zcrJn9qcGbh9NCZ05mPaD9KTaWlSvqtCveB6LKcpwknGtdjKMqCI6SclqPw0ilKmoF3ww q/+PyuUL5cBpjp/ShKO575bzxOSeFtLXkjFyOlEm+5/MTlb2GhtAkWnxJW/hoD/W2P8YQtlEWfka c/cOZtS8IlkFknh6vhAcWTYwz2a0DslGkI3uQKfqF64h+faLOO8FEakTAGCF49gGNAdKMSpz0Hs5 s5ugCCyjwfgNViWeOcoXT+JwPm5spPEpqBSApZPeFqVWr3av+BYOJ0Zpy2GHCoZtMFYjMc/oAtV5 Y5t1FhR4trv8vqw8kGj/Qzg03HO4X5iJwjbqDVxpj9D3zKt7M5G+f0x3a2dqCgAR5cVwzp9LGXW2 KaIlwOuwrqDRY/FvK5nrFWzvfhtYQ7tXdg542UdAADYotJD2GRshQUJ2xy9Kmh4HIlPq2guksB8g b7jxrbkhcHLKxjXbsRXAnYZ0wTkghRU9QYyECp/nS9wR3z9UcUzqEX3/BDJ5LnOUgVEL+AaFR0DC ig1Kc1E+Ah+NkQoksKwCeQZ9+1o9FFnOEhZ4o0jM1QDlkOUZ9sUHF9ISDg5LO7zyjXM9Cbji6K+F QS5+evOY6Jqpj2nD4ZWM0ex6yP1vbbIekoJLIw7gvKWTUN8cOiF5QRx7gqjekiJ2D1Nln+sAmjKK YIad/hfKZZr2BwjSTciOHxEE/FZFkuS5rEgT1SUihD0cRSJ+mioEuKmc8JNpJUFdOARsdmZqNpR7 qa9F2HcUl0JaPdQmo6VQ6bnl/u95E2t9+NQ2ZamKUTCTH2ksgcbLHx8W6923vZFWdm2dXWokyS8s afcC7hcrXZ732r+pQVBfv+8nu2TeuM6hNr514Nbt8qt7jJpWXBJTAEMxCtwGfqlgAJgnO+a0xIUg qr6z55nzqUSpA1e+beEhkbaYUIf68PTbhRrFpF2t3WkKBDgGn1CB6UkS02EDVKElBbxRTSG/9cLL xVTgFz1zg2sJ0Q4uEThd7hkZNNzZtRLby1WKhAmXz7qT//2B1yztyOPEC8Uk60NutjTX43SwtFoe 3JDQd9ZwNEFSn4KmomOmX6vCVRZ7ZranNQW09LGXLCl4QWD9N6O2tukMUieRBvXCrkdOZ0HJeQs/ WpkHJlh0bKCtzWOKPj8B9oslh98fGiqThSQzZPROcq3EoE9QBmx9y+ISgJ+15gAfTfpKAb+BL7d+ A6mCszpqeB3xOeDguRXikb0aMNg8tJLWgPjmEQnjK+7ojvRwecz2ljK5qRAuVQKnczkUDvaIJs9A wUPzmkuw9pj9jFMNWFCCduJa78fA//hQSZDMOUB58dmNxKSJvDqe6CcRtm5XJIyIzatsXno6IeBP tEwBzVI3j34rie+9LrLcGWJk4Vdr+R8dKXuZAM3KW5C3wI5w/oKeue0cDAxTkrY3ss64LTjKjhvD IDFx0ZoCLippHtD+jeXfgJ9V4GU1ZaguFmXxXvmbAwJDYNtkHn9n2PhMx/hzcDihCmUCrqvirB21 MMQX16aS/qWZkDrqqAm7HXrPtd6FX/X3hEEMiq9CDVyKdqLYIp7rQanMqZg7CpW3+BHTaXbWCQ9Y +nCkOl6rexsO8x2N7rzyWa/pOpHLODxXHSCsuMOf8/6bBtkdTpM7mWDqQqud5wL2pKmt5LjhLvC7 asB+LSipLaYeUFEuZFwICRML8R5MsTUvL0KaWRZPNqXgiNalG/rm/iaLB/arjczkgM7kDbf6yY5j Ewi+jhjDeMJTg69m4c+MypDLpONp83FwWkwChWuiWpxRdnDtadr4IXSvRcfHdVEP5fvCu1/1Q6Nr 84ld1fns1BsQFdvNKXqaFE0fs8sDlHas5O5N+hV/flSb49UvVmcYACFrToA9Wus4YGkHXiz31VHe yyIP6yryswb4eByrdYVa+FzIFP3Nmu18HA9ceORuFPd9M/2VYk3gDYSQmulstG/ud77mPxEEHaLE wYr6g0LB8WS4jG/ZMSTtNGVq2i6+WTfBqE0kFrhQEkbnbKhR2FJRxLtOAxaY3UwNNxU6sC1iF/qv oHfh5fQjJMY9fhLakOlvH1sp90jrWXcBorE05+X3dk78K4FDhGVYMa1J0PCqdUoMcG6WNHidSgTN 1ZRXk3nBUp4AV57bK62g/5JAlsiiIGbYctiwqos2oOUnEOUgzmqIrgEMNXuIWdBFIVJLHNV/qoRR QmduF7O4IoJ4RpxuILIqqjE+uZKc8pvJCIRKtYyLF2EpkjijH8aRRbK19CgEF6qlOQAssG2GLvsy ValOSssOJZ3b0GSFvX9L0l78lplcGpvFAurCJakaTD1q+nljqgATx6kt4q6N2ywaNb8W8ARSxdXE dLBBCyM0LEMqpvdsdICCHULWbAKes8wvu4jRmxzt+oHWi49CQnIzu249AjaH+CbD5OtGnIhD8iyB 4TuHD4NutmmC+AyUo0aliHajozFAN8TW7b6Eq/S3arXMYiDIlqjmsrgmm0/ZE9lNy0vgUzZQCR1h 93M2sHYfjmS/roAz/Xtj064DvfcuN44FA0/KUPxQZBSa69MSh7lmNhUzI9GyMwwik/EfsWH+ThPk XxOpnfHEzYJxwXKbJHVkBq/ek3rLXnRloCXcHGHPr1Ko52+huSMSev/E/H5vdLKiANE4m/pKDG71 GSYt2uXaVfMhpmvQQMA1XkLYtutxzw/Bfl2118IkIeJ8jR4DvtlNnb9SG0aktd6z//4qSzRaMQOS 3YaaboWAi3u3AZBmvWPzEOYujQu2MTi+iH2ghX81/x6ntx1Nvq0kKmoH1T/awiLbV2/FuaumrMEk vrM6j5Yc5y8oV14MG4L+LBUJ5oNP6Rc0Mx4BiHuegAfXBSzJZcoEUNc+EauofJQfcnegbLVn51ov PB4sSTsIvbhD+KDB+cgzsuwlo3pynHCKtG/v6YEveDG9udXFfG5Ox3ZpAekOo2F5IkwN5J9rJOVw tHsSBufXVHkV8ywzihRnMgE8B5y1IkwsCr3faHyuQB0yF/lnVUSK9YKacolqhDJz9iOo6+70dcEn xqSOLNOG1lxJdpRcx2UqgQpS9yvwrGsVbIA2EKljmSCFvCkBihUmL2GcQ/EH3NMc/Jq5HoaUbVhQ BaYNyNFTxQh46dPg7iDpOWxSfB4uT8i53HFYY52GCP6Cae8fPTyxd1Zwe6fApouFxJxhrpe/oOYe K7HNiAm94NGJZVCSrby60ePLxl4dR+IwKQFRYBs6t/rqSEg8Uk/7b/nV7ktJkl6Bm5k6SkxhlLNp wSAI2IQnZsZ9UMEcUMP0hOBlkhxZy7O4WT/ZlLo/a7PFwTXqBNOOiK7ya2AoyWJSgXjjOF0dW6Gc EnCBGMPzubSCc/p3XKnsBmjz8FCF0AZiB7IPRucc9jKRSBgxnqYkbutVH7L1jgW/MALcjnBpRRqe sqQRSv39GdT6xtXFxqy4uY4BrXjVnTlcxSz89uBKcjEx/cNXhn/IlaQKYt0JwVnwj2DObgsdgnqA ZqLBBMlAYj1VHwnbMCP4hZYC5zGpqMgOagRTQTxXwdGVfaUzVF9Ef5eaXUpvIukTJ8G2sZJy+JUL R1/uINLnr067jsr88Vih8ZU981X4iU1ldx8ZiulLDPcbWzZvNjL1w4tOsorA0c/foSeFlxa0aFNY mIW99yk6234dxjhlKmTzaikMjzwQ8vDzxJy+iwFEKv/MjBepXIikZVXs94mfCEZcSKcE+AB3ckw7 qeFUupQPCv4bkj7KW7aqke0HyiZacGusFYhF79AqL61AgLEww86142TJZBlPWecxfVa7J2OTdWag YYZJ/ahLc7NBe538HjJvO5CHYnCDUHs8/ji9XfUTQBX0Qg7LXo3Eb5pJ3eSG9Oho7HB0mO25FCgL jupl1RQm4q5dEjmTN4j+SRXC8BNNTcr6gDzikvSRDVJA67W9xRf/4TwuZxxx0l7Mh6ccY+BbNpe9 gcLIkejcGrD/cXk3CGUg2DyuH3rFIsmQ3mwRLuJFerEhteGOvmKyAu/iabMbMSEOTYqDY82Np8Vg AtmM5tO9LGVqD0WgwEqvlsmSemSSWjNRH1CJMi/iZ3KnXBQk3RUvs12zXvG0Dx2Q70auOMm5afsM F/BBuS7qnWE3IjvihnBt0PG9WHej2lYEFNkJIHs+da7lvWAGjaRU70s4KstywyZgpVuLp6CnjorJ cQ8leqsMoaRi+aKtG0IHJKnmHVMRQwugwrKuSFrWxEBgYcqPpAPfY2sH3QHhlI2D1be4/fr79g6x zmXc3Jvm5lALTcXmj/BPwYk4b510dQYzrexsxgDTeK4Yh/6RYPtWE0G1QASyGmftq3W6cyg3HTfl IgO9bmiGpr64WYQAL7+QVZtAv1WN4sDL42Zukc+l91npRyL3k7ixkNrR5vxcmS2RkxEEr0UfjBNY 5gwsebb2vYBMlctr0MS82+JL48Nhmc7DXYuXyApTF1+81JRLKQ9vpnjESc368hKhBAJy+CR8sif0 gY0rLLAUnFda79PsKX2/zbPJmjLC8q+YL+GQuJ0oAOsvpiotEmbHzLqLe37jQDh5q80pErY3gOkb 0OGSqeU0IK51r7dpNEREheWz2bUanwofC5qn4YOXf8/JU2CKiPIED+omJzppGeyi0KWQVWwG6Lbp zZo8mYiwenAhy1MWmfC1Jku/shWQ1Rh+0viyVNOHhmo/mUYyYbAQqFY9isM7PfoUYkfYo5Opnxsd csjc4hYehHK2eV7G19P/vXAmCdZC++mzDJnmHnasEWmBu2a+DKc7cJDKEspiBIWb3kDzTaxSzHc3 h7X0yvjU6DleI2UVSPArTUYGLNg/v35uwQuUKlW08lZcgIffZYIAxW1njnTgTml4+sy3Ygpd0POx 9XjMHAo1nEMFc3CnyhO8F++xIXD+BuQhvJHNOQ0PVk3+XV/Y5iElUnLZ4xxfGDAikkhIhgOUYekv VKb2iEVdLGQko7gU7kRyl+Ni340laPD0KzVIGBB3/ltegjxNF3QryWAAMZ3fuv/l2EamNUdT+Sxx iCj9EVWun97yIdo4QO9LTWXIUFDwGNP4mbsA48rAkRMPIEwvirBkNgp6cqEn9sd8X372XyOThtJL XkMuW7Hipzv5xRYNCm7l9+2ILGGTjTLskYgMUmsPDM8mmzbK8ZXYRfpkEtMCsDpYrZM9taDDVyPM Y9AZjHVHg49yMmYKvDDNETwaCke41eWNSzRhTk3Hcwo/qPgwoyI= `protect end_protected

mit

3af215ff25fc55be7d520547f3a4fae2

0.934538

1.862003

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_queue.vhd

1

37,514

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; --use axi_sg_v4_1.axi_sg_afifo_autord.all; library proc_common_v4_0; use proc_common_v4_0.sync_fifo_fg; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_queue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Stream Data width C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_INCLUDE_MM2S : integer range 0 to 1 := 0; C_INCLUDE_S2MM : integer range 0 to 1 := 0; C_ENABLE_CDMA : integer range 0 to 1 := 0; C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; C_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_primary_aclk : in std_logic ; m_axi_sg_aresetn : in std_logic ; -- p_reset_n : in std_logic ; ch2_sg_idle : in std_logic ; -- Channel Control -- desc1_flush : in std_logic ; -- ch1_cntrl_strm_stop : in std_logic ; desc2_flush : in std_logic ; -- ftch1_active : in std_logic ; -- ftch2_active : in std_logic ; -- ftch1_queue_empty : out std_logic ; -- ftch2_queue_empty : out std_logic ; -- ftch1_queue_full : out std_logic ; -- ftch2_queue_full : out std_logic ; -- ftch1_pause : out std_logic ; -- ftch2_pause : out std_logic ; -- -- writing_nxtdesc_in : in std_logic ; -- writing1_curdesc_out : out std_logic ; -- writing2_curdesc_out : out std_logic ; -- -- -- DataMover Command -- ftch_cmnd_wr : in std_logic ; -- ftch_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- MM2S Stream In from DataMover -- m_axis_mm2s_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_mm2s_tlast : in std_logic ; -- m_axis_mm2s_tvalid : in std_logic ; -- sof_ftch_desc : in std_logic ; m_axis1_mm2s_tready : out std_logic ; -- m_axis2_mm2s_tready : out std_logic ; -- -- data_concat : in std_logic_vector -- (95 downto 0) ; -- data_concat_mcdma : in std_logic_vector -- (63 downto 0) ; -- data_concat_tlast : in std_logic ; -- next_bd : in std_logic_vector (31 downto 0); data_concat_valid : in std_logic ; -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ftch_aclk : in std_logic ; -- m_axis_ftch1_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ftch1_tvalid : out std_logic ; -- m_axis_ftch1_tready : in std_logic ; -- m_axis_ftch1_tlast : out std_logic ; -- m_axis_ftch1_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ftch1_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ftch1_tvalid_new : out std_logic ; -- m_axis_ftch1_desc_available : out std_logic ; m_axis_ftch2_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ftch2_tvalid : out std_logic ; -- m_axis_ftch2_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ftch2_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ftch2_tvalid_new : out std_logic ; -- m_axis_ftch2_desc_available : out std_logic ; m_axis_ftch2_tready : in std_logic ; -- m_axis_ftch2_tlast : out std_logic ; -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (31 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- (3 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic := '0'; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_ftch_queue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_queue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; -- Number of words deep fifo needs to be -- 6 is subtracted as BD address are always 16 word aligned constant FIFO_WIDTH : integer := (128*C_ENABLE_CDMA + 97*(1-C_ENABLE_CDMA) -6); constant C_SG_WORDS_TO_FETCH1 : integer := C_SG_WORDS_TO_FETCH + 2*C_ENABLE_MULTI_CHANNEL; --constant FETCH_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE -- * C_SG_WORDS_TO_FETCH1)); constant FETCH_QUEUE_DEPTH : integer := 16; -- Select between BRAM or Logic Memory Type constant MEMORY_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE * C_SG_WORDS_TO_FETCH1 > 16); constant FETCH_QUEUE_CNT_WIDTH : integer := clog2(FETCH_QUEUE_DEPTH+1); constant DCNT_LO_INDEX : integer := max2(1,clog2(C_SG_WORDS_TO_FETCH1)) - 1; constant DCNT_HI_INDEX : integer := FETCH_QUEUE_CNT_WIDTH-1; -- CR616461 constant C_SG2_WORDS_TO_FETCH1 : integer := C_SG2_WORDS_TO_FETCH; constant FETCH2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE * C_SG2_WORDS_TO_FETCH1)); -- Select between BRAM or Logic Memory Type constant MEMORY2_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE * C_SG2_WORDS_TO_FETCH1 > 16); constant FETCH2_QUEUE_CNT_WIDTH : integer := clog2(FETCH2_QUEUE_DEPTH+1); constant DCNT2_LO_INDEX : integer := max2(1,clog2(C_SG2_WORDS_TO_FETCH1)) - 1; constant DCNT2_HI_INDEX : integer := FETCH2_QUEUE_CNT_WIDTH-1; -- CR616461 -- Width of fifo rd and wr counts - only used for proper fifo operation constant DESC2QUEUE_VECT_WIDTH : integer := 4; --constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461 constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461 --constant DCNT_HI_INDEX : integer := (DCNT_LO_INDEX + DESC2QUEUE_VECT_WIDTH) - 1; -- CR616461 constant ZERO_COUNT : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0'); constant ZERO_COUNT1 : std_logic_vector(FETCH2_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Internal signals signal curdesc_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_tvalid : std_logic := '0'; signal ftch_tvalid : std_logic := '0'; signal ftch_tvalid_new : std_logic := '0'; signal ftch_tdata : std_logic_vector (31 downto 0) := (others => '0'); signal ftch_tdata_new, reg1, reg2 : std_logic_vector (FIFO_WIDTH-1 downto 0) := (others => '0'); attribute mark_debug of ftch_tdata_new : signal is "true"; signal ftch_tlast : std_logic := '0'; signal ftch_tlast_new : std_logic := '0'; signal ftch_tready : std_logic := '0'; signal ftch_tready_ch1 : std_logic := '0'; signal ftch_tready_ch2 : std_logic := '0'; -- Misc Signals signal writing_curdesc : std_logic := '0'; signal writing_nxtdesc : std_logic := '0'; signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0'); signal writing_lsb : std_logic := '0'; signal writing_msb : std_logic := '0'; -- FIFO signals signal queue_rden2 : std_logic := '0'; signal queue_rden2_new : std_logic := '0'; signal queue_wren2 : std_logic := '0'; signal queue_wren2_new : std_logic := '0'; signal queue_empty2 : std_logic := '0'; signal queue_empty2_new : std_logic := '0'; signal queue_rden : std_logic := '0'; signal queue_rden_new : std_logic := '0'; signal queue_wren : std_logic := '0'; signal queue_wren_new : std_logic := '0'; signal queue_empty : std_logic := '0'; signal queue_empty_new : std_logic := '0'; signal queue_dout_valid : std_logic := '0'; signal queue_dout2_valid : std_logic := '0'; attribute mark_debug of queue_dout_valid : signal is "true"; attribute mark_debug of queue_dout2_valid : signal is "true"; signal queue_full_new : std_logic := '0'; signal queue_full2_new : std_logic := '0'; signal queue_full, queue_full2 : std_logic := '0'; signal queue_din_new : std_logic_vector (127 downto 0) := (others => '0'); signal queue_dout_new : std_logic_vector (96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0'); signal queue_dout_mcdma_new : std_logic_vector (63 downto 0) := (others => '0'); signal queue_dout2_new : std_logic_vector (96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0'); attribute mark_debug of queue_dout_new : signal is "true"; attribute mark_debug of queue_dout2_new : signal is "true"; signal queue_dout2_mcdma_new : std_logic_vector (63 downto 0) := (others => '0'); signal queue_din : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0'); signal queue_dout : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0'); signal queue_dout2 : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0'); signal queue_sinit : std_logic := '0'; signal queue_sinit2 : std_logic := '0'; signal queue_dcount_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0'); signal queue_dcount2_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0'); signal ftch_no_room : std_logic; signal ftch_active : std_logic := '0'; attribute mark_debug of ftch_active : signal is "true"; signal ftch_tvalid_mult : std_logic := '0'; signal ftch_tdata_mult : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ftch_tlast_mult : std_logic := '0'; signal counter : std_logic_vector (3 downto 0) := (others => '0'); signal wr_cntl : std_logic := '0'; signal sof_ftch_desc_del : std_logic; signal sof_ftch_desc_del1 : std_logic; signal sof_ftch_desc_pulse : std_logic; signal current_bd : std_logic_vector (31 downto 0) := (others => '0'); signal xfer_in_progress : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin SOF_DEL_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sof_ftch_desc_del <= '0'; else sof_ftch_desc_del <= sof_ftch_desc; end if; end if; end process SOF_DEL_PROCESS; SOF_DEL1_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then sof_ftch_desc_del1 <= '0'; elsif (m_axis_mm2s_tvalid = '1') then sof_ftch_desc_del1 <= sof_ftch_desc; end if; end if; end process SOF_DEL1_PROCESS; sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1); ftch_active <= ftch1_active or ftch2_active; --------------------------------------------------------------------------- -- Write current descriptor to FIFO or out channel port --------------------------------------------------------------------------- CMDDATA_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then current_bd <= (others => '0'); elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then current_bd <= next_bd; elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST + DATAMOVER_CMD_ADDRLSB_BIT downto DATAMOVER_CMD_ADDRLSB_BIT); end if; end if; end process CMDDATA_PROCESS; GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate begin ftch_tvalid_mult <= m_axis_mm2s_tvalid; ftch_tdata_mult <= m_axis_mm2s_tdata; ftch_tlast_mult <= m_axis_mm2s_tlast; wr_cntl <= m_axis_mm2s_tvalid; end generate GEN_MULT_CHANNEL; GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate begin ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid; ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata; ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast; m_axis_ftch1_tdata_mcdma_new <= (others => '0'); m_axis_ftch2_tdata_mcdma_new <= (others => '0'); COUNTER_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then counter <= (others => '0'); elsif (m_axis_mm2s_tvalid = '1') then counter <= std_logic_vector(unsigned(counter) + 1); end if; end if; end process COUNTER_PROCESS; end generate GEN_NOMULT_CHANNEL; --------------------------------------------------------------------------- -- TVALID MUX -- MUX tvalid out channel port --------------------------------------------------------------------------- CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate begin ftch_tdata_new (95 downto 0) <= data_concat;-- when (ftch_active = '1') else (others =>'0'); -- BD is always 16 word aligned ftch_tdata_new (121 downto 96) <= current_bd (31 downto 6); end generate CDMA_FIELDS; DMA_FIELDS : if C_ENABLE_CDMA = 0 generate begin ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0'); -- BD is always 16 word aligned ftch_tdata_new (90 downto 65) <= current_bd (31 downto 6); end generate DMA_FIELDS; ftch_tvalid_new <= data_concat_valid and ftch_active; ftch_tlast_new <= data_concat_tlast and ftch_active; GEN_MM2S : if C_INCLUDE_MM2S = 1 generate begin process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit = '1' or queue_rden_new = '1') then queue_empty_new <= '1'; queue_full_new <= '0'; elsif (queue_wren_new = '1') then queue_empty_new <= '0'; queue_full_new <= '1'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit = '1') then reg1 <= (others => '0'); elsif (queue_wren_new = '1') then reg1 <= ftch_tdata_new; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit = '1') then queue_dout_new <= (others => '0'); elsif (queue_rden_new = '1') then queue_dout_new <= reg1; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit = '1' or queue_dout_valid = '1') then queue_dout_valid <= '0'; elsif (queue_rden_new = '1') then queue_dout_valid <= '1'; end if; end if; end process; MCDMA_MM2S : if C_ENABLE_MULTI_CHANNEL = 1 generate begin -- Generate Synchronous FIFO I_CH1_FTCH_MCDMA_FIFO_NEW : entity proc_common_v4_0.sync_fifo_fg generic map ( C_FAMILY => C_FAMILY , C_MEMORY_TYPE => 0, --MEMORY_TYPE , C_WRITE_DATA_WIDTH => 64, C_WRITE_DEPTH => FETCH_QUEUE_DEPTH , C_READ_DATA_WIDTH => 64, C_READ_DEPTH => FETCH_QUEUE_DEPTH , C_PORTS_DIFFER => 0, C_HAS_DCOUNT => 0, C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH, C_HAS_ALMOST_FULL => 0, C_HAS_RD_ACK => 0, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_PRELOAD_REGS => 0,-- 1 = first word fall through C_PRELOAD_LATENCY => 1 -- 0 = first word fall through ) port map ( Clk => m_axi_sg_aclk , Sinit => queue_sinit , Din => data_concat_mcdma, --ftch_tdata_new, --queue_din , Wr_en => queue_wren_new , Rd_en => queue_rden_new , Dout => queue_dout_mcdma_new , Full => open, --queue_full_new , Empty => open, --queue_empty_new , Almost_full => open , Data_count => open, --queue_dcount_new , Rd_ack => open, --queue_dout_valid, --open , Rd_err => open , Wr_ack => open , Wr_err => open ); m_axis_ftch1_tdata_mcdma_new <= queue_dout_mcdma_new; end generate MCDMA_MM2S; CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 generate begin I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1.axi_sg_cntrl_strm generic map( C_PRMRY_IS_ACLK_ASYNC => C_ASYNC , C_PRMY_CMDFIFO_DEPTH => FETCH_QUEUE_DEPTH , C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_FAMILY => C_FAMILY ) port map( -- Secondary clock / reset m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Primary clock / reset axi_prmry_aclk => m_axi_primary_aclk , p_reset_n => p_reset_n , -- MM2S Error mm2s_stop => ch1_cntrl_strm_stop , -- Control Stream input cntrlstrm_fifo_wren => queue_wren , cntrlstrm_fifo_full => queue_full , cntrlstrm_fifo_din => queue_din , -- Memory Map to Stream Control Stream Interface m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); end generate CONTROL_STREAM; end generate GEN_MM2S; GEN_S2MM : if C_INCLUDE_S2MM = 1 generate begin process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit2 = '1' or queue_rden2_new = '1') then queue_empty2_new <= '1'; queue_full2_new <= '0'; elsif (queue_wren2_new = '1') then queue_empty2_new <= '0'; queue_full2_new <= '1'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit2 = '1') then reg2 <= (others => '0'); elsif (queue_wren2_new = '1') then reg2 <= ftch_tdata_new; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit2 = '1') then queue_dout2_new <= (others => '0'); elsif (queue_rden2_new = '1') then queue_dout2_new <= reg2; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (queue_sinit2 = '1' or queue_dout2_valid = '1') then queue_dout2_valid <= '0'; elsif (queue_rden2_new = '1') then queue_dout2_valid <= '1'; end if; end if; end process; MCDMA_S2MM : if C_ENABLE_MULTI_CHANNEL = 1 generate begin -- Generate Synchronous FIFO I_CH2_FTCH_MCDMA_FIFO_NEW : entity proc_common_v4_0.sync_fifo_fg generic map ( C_FAMILY => C_FAMILY , C_MEMORY_TYPE => 0, --MEMORY_TYPE , C_WRITE_DATA_WIDTH => 64, C_WRITE_DEPTH => FETCH_QUEUE_DEPTH , C_READ_DATA_WIDTH => 64, C_READ_DEPTH => FETCH_QUEUE_DEPTH , C_PORTS_DIFFER => 0, C_HAS_DCOUNT => 0, C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH, C_HAS_ALMOST_FULL => 0, C_HAS_RD_ACK => 0, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_PRELOAD_REGS => 0,-- 1 = first word fall through C_PRELOAD_LATENCY => 1 -- 0 = first word fall through ) port map ( Clk => m_axi_sg_aclk , Sinit => queue_sinit2 , Din => data_concat_mcdma, --ftch_tdata_new, --queue_din , Wr_en => queue_wren2_new , Rd_en => queue_rden2_new , Dout => queue_dout2_new , Full => open, --queue_full2_new , Empty => open, --queue_empty2_new , Almost_full => open , Data_count => queue_dcount2_new , Rd_ack => open, --queue_dout2_valid , Rd_err => open , Wr_ack => open , Wr_err => open ); m_axis_ftch2_tdata_mcdma_new <= queue_dcount2_new; end generate MCDMA_S2MM; end generate GEN_S2MM; ----------------------------------------------------------------------- -- Internal Side ----------------------------------------------------------------------- -- Drive tready with fifo not full ftch_tready <= ftch_tready_ch1 or ftch_tready_ch2; -- Following is the APP data that goes into APP FIFO queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast; queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata; GEN_CH1_CTRL : if C_INCLUDE_MM2S =1 generate begin --queue_full_new <= '1' when (queue_dcount_new = "00100") else '0'; queue_sinit <= desc1_flush or not m_axi_sg_aresetn; ftch_tready_ch1 <= (not queue_full and ftch1_active); m_axis1_mm2s_tready <= ftch_tready_ch1; -- Wr_en to APP FIFO. Data is written only when BD with SOF is fetched. queue_wren <= not queue_full and sof_ftch_desc and m_axis_mm2s_tvalid and ftch1_active; -- Wr_en of BD FIFO queue_wren_new <= not queue_full_new and ftch_tvalid_new and ftch1_active; ftch1_queue_empty <= queue_empty_new; ftch1_queue_full <= queue_full_new; ftch1_pause <= queue_full_new; -- RD_en of APP FIFO based on empty and tready -- RD_EN of BD FIFO based on empty and tready queue_rden_new <= not queue_empty_new and m_axis_ftch1_tready; -- drive valid if fifo is not empty m_axis_ftch1_tvalid <= '0'; m_axis_ftch1_tvalid_new <= queue_dout_valid; --not queue_empty_new and (not ch2_sg_idle); -- below signal triggers the fetch of BD in MM2S Mngr m_axis_ftch1_desc_available <= not queue_empty_new and (not ch2_sg_idle); -- Pass data out to port channel with MSB driving tlast m_axis_ftch1_tlast <= '0'; m_axis_ftch1_tdata <= (others => '0'); m_axis_ftch1_tdata_new <= queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0); writing1_curdesc_out <= writing_curdesc and ftch1_active; NOCONTROL_STREAM_ASST : if C_SG_WORDS_TO_FETCH = 8 generate begin m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= (others => '0'); m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; end generate NOCONTROL_STREAM_ASST; end generate GEN_CH1_CTRL; GEN_NO_CH1_CTRL : if C_INCLUDE_MM2S =0 generate begin m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= "0000"; m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; ftch_tready_ch1 <= '0'; m_axis1_mm2s_tready <= '0'; -- Write to fifo if it is not full and data is valid queue_wren <= '0'; ftch1_queue_empty <= '0'; ftch1_queue_full <= '0'; ftch1_pause <= '0'; queue_rden <= '0'; -- drive valid if fifo is not empty m_axis_ftch1_tvalid <= '0'; -- Pass data out to port channel with MSB driving tlast m_axis_ftch1_tlast <= '0'; m_axis_ftch1_tdata <= (others => '0'); writing1_curdesc_out <= '0'; m_axis_ftch1_tdata_new <= (others => '0'); m_axis_ftch1_tvalid_new <= '0'; m_axis_ftch1_desc_available <= '0'; end generate GEN_NO_CH1_CTRL; GEN_CH2_CTRL : if C_INCLUDE_S2MM =1 generate begin queue_sinit2 <= desc2_flush or not m_axi_sg_aresetn; ftch_tready_ch2 <= (not queue_full2_new and ftch2_active); m_axis2_mm2s_tready <= ftch_tready_ch2; queue_wren2 <= '0'; -- Wr_en for S2MM BD FIFO queue_wren2_new <= not queue_full2_new and ftch_tvalid_new and ftch2_active; --queue_full2_new <= '1' when (queue_dcount2_new = "00100") else '0'; -- Pass fifo status back to fetch sm for channel IDLE determination ftch2_queue_empty <= queue_empty2_new; ftch2_queue_full <= queue_full2_new; ftch2_pause <= queue_full2_new; queue_rden2 <= '0'; -- Rd_en for S2MM BD FIFO queue_rden2_new <= not queue_empty2_new and m_axis_ftch2_tready; m_axis_ftch2_tvalid <= '0'; m_axis_ftch2_tvalid_new <= queue_dout2_valid; -- not queue_empty2_new and (not ch2_sg_idle); m_axis_ftch2_desc_available <= not queue_empty2_new and (not ch2_sg_idle); -- Pass data out to port channel with MSB driving tlast m_axis_ftch2_tlast <= '0'; m_axis_ftch2_tdata <= (others => '0'); m_axis_ftch2_tdata_new <= queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0); writing2_curdesc_out <= writing_curdesc and ftch2_active; end generate GEN_CH2_CTRL; GEN_NO_CH2_CTRL : if C_INCLUDE_S2MM =0 generate begin ftch_tready_ch2 <= '0'; m_axis2_mm2s_tready <= '0'; queue_wren2 <= '0'; -- Pass fifo status back to fetch sm for channel IDLE determination --ftch_queue_empty <= queue_empty; CR 621600 ftch2_queue_empty <= '0'; ftch2_queue_full <= '0'; ftch2_pause <= '0'; queue_rden2 <= '0'; m_axis_ftch2_tvalid <= '0'; -- Pass data out to port channel with MSB driving tlast m_axis_ftch2_tlast <= '0'; m_axis_ftch2_tdata <= (others => '0'); m_axis_ftch2_tdata_new <= (others => '0'); m_axis_ftch2_tvalid_new <= '0'; writing2_curdesc_out <= '0'; m_axis_ftch2_desc_available <= '0'; end generate GEN_NO_CH2_CTRL; -- If writing curdesc out then flag for proper mux selection writing_curdesc <= curdesc_tvalid; -- Map intnal signal to port -- Map port to internal signal writing_nxtdesc <= writing_nxtdesc_in; end implementation;

bsd-2-clause

ac50c123bd76e09bcb82bee493ad84eb

0.470731

3.78738

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_addr_cntl.vhd

1

42,473

---------------------------------------------------------------------------- -- axi_datamover_addr_cntl.vhd ---------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_addr_cntl.vhd -- -- Description: -- This file implements the axi_datamover Master Address Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_addr_cntl.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- -- DET 9/1/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Fixed Lint reported excesive line length for line 196. -- ^^^^^^ -- -- DET 9/1/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Fixed a Lint reported issue with the vector widths of the addr2axi_aprot -- assignment to the constant APROT_VALUE. The code was ok but Spyglass -- was not interpreting the vector MS Index correctly, I changed the HDL -- anyway. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; Use axi_datamover_v5_1.axi_datamover_fifo; ------------------------------------------------------------------------------- entity axi_datamover_addr_cntl is generic ( C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4; -- sets the depth of the Command Queue FIFO C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the address bus width C_ADDR_ID : Integer range 0 to 255 := 0; -- Sets the value to be on the AxID output C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the AxID output C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Command Tag field width C_FAMILY : String := "virtex7" -- Specifies the target FPGA family ); port ( -- Clock input --------------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------ -- AXI Address Channel I/O -------------------------------------------- addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- addr2axi_alen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- addr2axi_asize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- addr2axi_aburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_acache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_auser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel BURST output -- -- addr2axi_aprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- addr2axi_avalid : out std_logic; -- -- AXI Address Channel VALID output -- -- axi2addr_aready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------- -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- Command Calculation Interface ----------------------------------------- mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : In std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- Sized to support 256 data beat bursts -- -- mstr2addr_size : In std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : In std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : In std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_user : In std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cmd_cmplt : In std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2addr_cmd_valid : in std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : out std_logic; -- -- Indication to the Command Calculator that the -- -- command is being accepted -- -------------------------------------------------------------------------- -- Halted Indication to Reset Module ------------------------------ addr2rst_stop_cmplt : out std_logic; -- -- Output flag indicating the address controller has stopped -- -- posting commands to the Address Channel due to a stop -- -- request vai the data2addr_stop_req input port -- ------------------------------------------------------------------ -- Address Generation Control --------------------------------------- allow_addr_req : in std_logic; -- -- Input used to enable/stall the posting of address requests. -- -- 0 = stall address request generation. -- -- 1 = Enable Address request geneartion -- -- addr_req_posted : out std_logic; -- -- Indication from the Address Channel Controller to external -- -- User logic that an address has been posted to the -- -- AXI Address Channel. -- --------------------------------------------------------------------- -- Data Channel Interface --------------------------------------------- addr2data_addr_posted : Out std_logic; -- -- Indication from the Address Channel Controller to the -- -- Data Controller that an address has been posted to the -- -- AXI Address Channel. -- -- data2addr_data_rdy : In std_logic; -- -- Indication that the Data Channel is ready to send the first -- -- databeat of the next command on the write data channel. -- -- This is used for the "wait for data" feature which keeps the -- -- address controller from issuing a transfer requset until the -- -- corresponding data is ready. This is expected to be held in -- -- the asserted state until the addr2data_addr_posted signal is -- -- asserted. -- -- data2addr_stop_req : In std_logic; -- -- Indication that the Data Channel has encountered an error -- -- or a soft shutdown request and needs the Address Controller -- -- to stop posting commands to the AXI Address channel -- ----------------------------------------------------------------------- -- Status Module Interface --------------------------------------- addr2stat_calc_error : out std_logic; -- -- Indication to the Status Module that the Addr Cntl FIFO -- -- is loaded with a Calc error -- -- addr2stat_cmd_fifo_empty : out std_logic -- -- Indication to the Status Module that the Addr Cntl FIFO -- -- is empty -- ------------------------------------------------------------------ ); end entity axi_datamover_addr_cntl; architecture implementation of axi_datamover_addr_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant Declarations -------------------------------------------- Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0'); --'0' & -- bit 2, Normal Access --'0' & -- bit 1, Nonsecure Access --'0'; -- bit 0, Data Access Constant LEN_WIDTH : integer := 8; Constant SIZE_WIDTH : integer := 3; Constant BURST_WIDTH : integer := 2; Constant CMD_CMPLT_WIDTH : integer := 1; Constant CALC_ERROR_WIDTH : integer := 1; Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width C_ADDR_WIDTH + -- Cmd Address field width LEN_WIDTH + -- Cmd Len field width SIZE_WIDTH + -- Cmd Size field width BURST_WIDTH + -- Cmd Burst field width CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width CALC_ERROR_WIDTH + -- Cmd Calc Error flag 8; -- Cmd Cache, user fields Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM; -- Signal Declarations -------------------------------------------- signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0'); signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0'); signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0'); signal sig_axi_avalid : std_logic := '0'; signal sig_axi_aready : std_logic := '0'; signal sig_addr_posted : std_logic := '0'; signal sig_calc_error : std_logic := '0'; signal sig_cmd_fifo_empty : std_logic := '0'; Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0'); Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_fifo_next_cmd_cmplt : std_logic := '0'; signal sig_fifo_calc_error : std_logic := '0'; signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_fifo_rd_cmd_ready : std_logic := '0'; signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0'); signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0'); signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0'); signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0'); signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0'); signal sig_next_cmd_cmplt_reg : std_logic := '0'; signal sig_addr_valid_reg : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_pop_addr_reg : std_logic := '0'; signal sig_push_addr_reg : std_logic := '0'; signal sig_addr_reg_empty : std_logic := '0'; signal sig_addr_reg_full : std_logic := '0'; signal sig_posted_to_axi : std_logic := '0'; -- obsoleted signal sig_set_wfd_flop : std_logic := '0'; -- obsoleted signal sig_clr_wfd_flop : std_logic := '0'; -- obsoleted signal sig_wait_for_data : std_logic := '0'; -- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0'; signal sig_allow_addr_req : std_logic := '0'; signal sig_posted_to_axi_2 : std_logic := '0'; signal new_cmd_in : std_logic; signal first_addr_valid : std_logic; signal first_addr_valid_del : std_logic; signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0); signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0); signal addr2axi_cache_int : std_logic_vector (7 downto 0); signal addr2axi_cache_int1 : std_logic_vector (7 downto 0); signal last_one : std_logic; signal latch : std_logic; signal first_one : std_logic; signal latch_n : std_logic; signal latch_n_del : std_logic; signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0); -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no"; begin --(architecture implementation) -- AXI I/O Port assignments addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH)); addr2axi_aaddr <= sig_axi_addr ; addr2axi_alen <= sig_axi_alen ; addr2axi_asize <= sig_axi_asize ; addr2axi_aburst <= sig_axi_aburst; addr2axi_acache <= sig_axi_acache; addr2axi_auser <= sig_axi_auser; addr2axi_aprot <= APROT_VALUE ; addr2axi_avalid <= sig_axi_avalid; sig_axi_aready <= axi2addr_aready; -- Command Calculator Handshake output sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ; addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; -- Data Channel Controller synchro pulse output addr2data_addr_posted <= sig_addr_posted; -- Status Module Interface outputs addr2stat_calc_error <= sig_calc_error ; addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and sig_cmd_fifo_empty; -- Flag Indicating the Address Controller has completed a Stop addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case sig_addr_reg_empty) or (data2addr_stop_req and -- shutdown after error trap sig_calc_error); -- Assign the address posting control and status sig_allow_addr_req <= allow_addr_req ; addr_req_posted <= sig_posted_to_axi_2 ; -- Internal logic ------------------------------ ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_FIFO -- -- If Generate Description: -- Implements the case where the cmd qualifier depth is -- greater than 1. -- ------------------------------------------------------------ GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate begin -- Format the input FIFO data word sig_aq_fifo_data_in <= mstr2addr_cache & mstr2addr_user & mstr2addr_calc_error & mstr2addr_cmd_cmplt & mstr2addr_burst & mstr2addr_size & mstr2addr_len & mstr2addr_addr & mstr2addr_tag ; -- Rip fields from FIFO output data word sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 7) downto (C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 4) ); sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH + 3) downto (C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH) ); sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH + CALC_ERROR_WIDTH)-1); sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH + CMD_CMPLT_WIDTH)-1); sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH + BURST_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH) ; sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH + SIZE_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH) ; sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH + LEN_WIDTH)-1 downto C_ADDR_WIDTH + C_TAG_WIDTH) ; sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH + C_TAG_WIDTH)-1 downto C_TAG_WIDTH) ; sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_ADDR_QUAL_FIFO -- -- Description: -- Instance for the Address/Qualifier FIFO -- ------------------------------------------------------------ I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => ADDR_QUAL_WIDTH , C_DEPTH => C_ADDR_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_aq_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_fifo_rd_cmd_ready , fifo_rd_tdata => sig_aq_fifo_data_out , fifo_rd_empty => sig_cmd_fifo_empty ); end generate GEN_ADDR_FIFO; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_ADDR_FIFO -- -- If Generate Description: -- Implements the case where no additional FIFOing is needed -- on the input command address/qualifiers. -- ------------------------------------------------------------ GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate begin -- Bypass FIFO sig_fifo_next_tag <= mstr2addr_tag ; sig_fifo_next_addr <= mstr2addr_addr ; sig_fifo_next_len <= mstr2addr_len ; sig_fifo_next_size <= mstr2addr_size ; sig_fifo_next_burst <= mstr2addr_burst ; sig_fifo_next_cache <= mstr2addr_cache ; sig_fifo_next_user <= mstr2addr_user ; sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ; sig_fifo_calc_error <= mstr2addr_calc_error ; sig_cmd_fifo_empty <= sig_addr_reg_empty ; sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ; sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ; end generate GEN_NO_ADDR_FIFO; -- Output Register Logic ------------------------------------------- sig_axi_addr <= sig_next_addr_reg ; sig_axi_alen <= sig_next_len_reg ; sig_axi_asize <= sig_next_size_reg ; sig_axi_aburst <= sig_next_burst_reg ; sig_axi_acache <= sig_next_cache_reg ; sig_axi_auser <= sig_next_user_reg ; sig_axi_avalid <= sig_addr_valid_reg ; sig_calc_error <= sig_calc_error_reg ; sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and sig_allow_addr_req and -- obsoleted not(sig_wait_for_data) and not(data2addr_stop_req); sig_addr_posted <= sig_posted_to_axi ; -- Internal signals sig_push_addr_reg <= sig_addr_reg_empty and sig_fifo_rd_cmd_valid and sig_allow_addr_req and -- obsoleted not(sig_wait_for_data) and not(data2addr_stop_req); sig_pop_addr_reg <= not(sig_calc_error_reg) and sig_axi_aready and sig_addr_reg_full; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_FIFO_REG -- -- Process Description: -- This process implements a register for the Address -- Control FIFO that operates like a 1 deep Sync FIFO. -- ------------------------------------------------------------- IMP_ADDR_FIFO_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_addr_reg = '1') then sig_next_tag_reg <= (others => '0') ; sig_next_addr_reg <= (others => '0') ; sig_next_len_reg <= (others => '0') ; sig_next_size_reg <= (others => '0') ; sig_next_burst_reg <= (others => '0') ; sig_next_cache_reg <= (others => '0') ; sig_next_user_reg <= (others => '0') ; sig_next_cmd_cmplt_reg <= '0' ; sig_addr_valid_reg <= '0' ; sig_calc_error_reg <= '0' ; sig_addr_reg_empty <= '1' ; sig_addr_reg_full <= '0' ; elsif (sig_push_addr_reg = '1') then sig_next_tag_reg <= sig_fifo_next_tag ; sig_next_addr_reg <= sig_fifo_next_addr ; sig_next_len_reg <= sig_fifo_next_len ; sig_next_size_reg <= sig_fifo_next_size ; sig_next_burst_reg <= sig_fifo_next_burst ; sig_next_cache_reg <= sig_fifo_next_cache ; sig_next_user_reg <= sig_fifo_next_user ; sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ; sig_addr_valid_reg <= not(sig_fifo_calc_error); sig_calc_error_reg <= sig_fifo_calc_error ; sig_addr_reg_empty <= '0' ; sig_addr_reg_full <= '1' ; else null; -- don't change state end if; end if; end process IMP_ADDR_FIFO_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_POSTED_FLAG -- -- Process Description: -- This implements a FLOP that creates a 1 clock wide pulse -- indicating a new address/qualifier set has been posted to -- the AXI Addres Channel outputs. This is used to synchronize -- the Data Channel Controller. -- ------------------------------------------------------------- IMP_POSTED_FLAG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_posted_to_axi <= '0'; sig_posted_to_axi_2 <= '0'; elsif (sig_push_addr_reg = '1') then sig_posted_to_axi <= '1'; sig_posted_to_axi_2 <= '1'; else sig_posted_to_axi <= '0'; sig_posted_to_axi_2 <= '0'; end if; end if; end process IMP_POSTED_FLAG; -- PROC_CMD_DETECT : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- first_addr_valid_del <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- first_addr_valid_del <= first_addr_valid; -- end if; -- end process PROC_CMD_DETECT; -- -- PROC_ADDR_DET : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- first_addr_valid <= '0'; -- first_addr_int <= (others => '0'); -- last_addr_int <= (others => '0'); -- elsif (primary_aclk'event and primary_aclk = '1') then -- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then -- first_addr_valid <= '1'; -- first_addr_int <= mstr2addr_addr; -- last_addr_int <= last_addr_int; -- elsif (mstr2addr_cmd_cmplt = '1') then -- first_addr_valid <= '0'; -- first_addr_int <= first_addr_int; -- last_addr_int <= mstr2addr_addr; -- end if; -- end if; -- end process PROC_ADDR_DET; -- -- latch <= first_addr_valid and (not first_addr_valid_del); -- latch_n <= (not first_addr_valid) and first_addr_valid_del; -- -- PROC_CACHE1 : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- mstr2addr_cache_info_int <= (others => '0'); -- latch_n_del <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- if (latch_n = '1') then -- mstr2addr_cache_info_int <= mstr2addr_cache_info; -- end if; -- latch_n_del <= latch_n; -- end if; -- end process PROC_CACHE1; -- -- -- PROC_CACHE : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- addr2axi_cache_int1 <= (others => '0'); -- first_one <= '0'; -- elsif (primary_aclk'event and primary_aclk = '1') then -- first_one <= '0'; ---- if (latch = '1' and first_one = '0') then -- first one -- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then -- addr2axi_cache_int1 <= mstr2addr_cache_info; ---- first_one <= '1'; ---- elsif (latch_n_del = '1') then ---- addr2axi_cache_int <= mstr2addr_cache_info_int; -- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then -- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4); -- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then -- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4); -- end if; -- end if; -- end process PROC_CACHE; -- -- -- PROC_CACHE2 : process (primary_aclk) -- begin -- if (mmap_reset = '1') then -- addr2axi_cache_int <= (others => '0'); -- elsif (primary_aclk'event and primary_aclk = '1') then -- addr2axi_cache_int <= addr2axi_cache_int1; -- end if; -- end process PROC_CACHE2; -- --addr2axi_cache <= addr2axi_cache_int (3 downto 0); --addr2axi_user <= addr2axi_cache_int (7 downto 4); -- end implementation;

bsd-2-clause

b164ccf0bc924253a8da524d5c9cbfa9

0.395216

4.962959

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/architecture/rule_601_test_input.vhd

1

8,216

entity FIFO is generic ( G_WIDTH : natural := 16 ); port ( I_INPUT : in std_logic; O_OUTPUT : out std_logic; IO_INOUT : inout std_logic ); end entity; architecture rtl of fifo is function func1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) return integer is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; procedure proc1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) is variable w_data : std_logic_vector(g_width - 1 downto 0); variable w_read : std_logic_vector(i_input'range); variable w_read : std_logic_vector(o_output'left downto 0); variable w_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; signal w_data : std_logic_vector(G_WIDTH - 1 downto 0); constant w_read : std_logic_vector(I_INPUT'range); shared variable w_read : std_logic_vector(O_OUTPUT'left downto 0); signal w_read : std_logic_vector(31 downto IO_INOUT'right); begin output <= large_data(g_width - 1 downto 0); process (I_INPUT, O_OUTPUT, IO_INOUT) is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end process; a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input => I_INPUT, o_output => O_OUTPUT, io_inout => IO_INOUT ); U_RAM : RAM generic map ( g_width => g_width ) port map ( I_INPUT, O_OUTPUT, IO_INOUT ); end architecture rtl; -- Violations Below architecture rtl of fifo is function func1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) return integer is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; procedure proc1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) is variable w_data : std_logic_vector(g_width - 1 downto 0); variable w_read : std_logic_vector(i_input'range); variable w_read : std_logic_vector(o_output'left downto 0); variable w_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(i_input'range); signal w_read : std_logic_vector(o_output'left downto 0); signal w_read : std_logic_vector(31 downto io_inout'right); begin output <= large_data(g_width - 1 downto 0); process (i_input, o_output, io_inout) is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end process; a <= i_input; b <= o_output; c <= io_inout; U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input => i_input, o_output => o_output, io_inout => io_inout ); U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input, o_output, io_inout ); end architecture rtl; -- Change entities entity NEW_FIFO is generic ( g_width : natural := 16 ); port ( i_input : in std_logic; o_output : out std_logic; io_inout : inout std_logic ); end entity; architecture rtl of new_fifo is function func1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) return integer is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; procedure proc1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) is variable w_data : std_logic_vector(G_WIDTH - 1 downto 0); variable w_read : std_logic_vector(I_INPUT'range); variable w_read : std_logic_vector(O_OUTPUT'left downto 0); variable w_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(i_input'range); signal w_read : std_logic_vector(o_output'left downto 0); signal w_read : std_logic_vector(31 downto io_inout'right); begin output <= large_data(g_width - 1 downto 0); process (i_input, o_output, io_inout) is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end process; a <= i_input; b <= o_output; c <= io_inout; U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT => i_input, O_OUTPUT => o_output, IO_INOUT => io_inout ); U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( i_input, o_output, io_inout ); end architecture rtl; -- Violations architecture rtl of new_fifo is function func1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) return integer is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; procedure proc1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) is variable w_data : std_logic_vector(G_WIDTH - 1 downto 0); variable w_read : std_logic_vector(I_INPUT'range); variable w_read : std_logic_vector(O_OUTPUT'left downto 0); variable w_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(I_INPUT'range); signal w_read : std_logic_vector(O_OUTPUT'left downto 0); signal w_read : std_logic_vector(31 downto IO_INOUT'right); begin output <= large_data(G_WIDTH - 1 downto 0); process (I_INPUT, O_OUTPUT, IO_INOUT) is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end process; a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT => I_INPUT, O_OUTPUT => O_OUTPUT, IO_INOUT => IO_INOUT ); U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT, O_OUTPUT, IO_INOUT ); end architecture rtl;

gpl-3.0

e88599457b2386a01d1af5739d32ba5d

0.607595

3.127522

false

siavooshpayandehazad/TTU_CPU_Project

pico_CPU_pipelined/GPIO.vhd

1

634

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.all; use work.pico_cpu.all; entity GPIO is generic (BitWidth: integer); port ( IO_sel: in std_logic; IO: inout std_logic_vector (BitWidth-1 downto 0); WrtData: in std_logic_vector (BitWidth-1 downto 0); RdData: out std_logic_vector (BitWidth-1 downto 0) ); end GPIO; architecture behavioral of GPIO is begin process(IO_sel, IO, WrtData)begin if IO_sel = '0' then IO <= (others => 'Z'); RdData <= IO; else IO <= WrtData; end if; end process; end behavioral;

gpl-2.0

ac0e3b83f638f36311b8aa883be40b13

0.59306

3.336842

false

rjarzmik/mips_processor

EX/ALU.vhd

1

8,032

------------------------------------------------------------------------------- -- Title : Arithmetic and Logic Unit -- Project : ------------------------------------------------------------------------------- -- File : ALU.vhd.vhd -- Author : Robert Jarzmik (Intel) <[email protected]> -- Company : -- Created : 2016-11-16 -- Last update: 2016-12-09 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Integer Computing Unit ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-16 1.0 rjarzmik Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cpu_defs.all; use work.instruction_defs.all; ------------------------------------------------------------------------------- entity ALU is generic ( ADDR_WIDTH : integer := 32; DATA_WIDTH : integer := 32; NB_REGISTERS : positive := 32 ); port ( clk : in std_logic; rst : in std_logic; stall_req : in std_logic; -- stall current instruction kill_req : in std_logic; -- kill current instruction alu_op : in alu_op_type; i_reg1 : in register_port_type; i_reg2 : in register_port_type; i_divide_0 : in std_logic; -- if set, a division attempt will be a X/0 -- Carry-over signals i_jump_target : in std_logic_vector(ADDR_WIDTH - 1 downto 0); i_jump_op : in jump_type; i_mem_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); i_mem_op : in memory_op_type; i_instr_tag : in instr_tag_t; o_reg1 : out register_port_type; o_reg2 : out register_port_type; o_jump_target : out std_logic_vector(ADDR_WIDTH - 1 downto 0); o_is_jump : out std_logic; o_mem_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); o_mem_op : out memory_op_type; o_instr_tag : out instr_tag_t; -- Debug signal i_dbg_ex_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0); o_dbg_ex_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0) ); end entity ALU; ------------------------------------------------------------------------------- architecture rtl of ALU is signal ra : unsigned(DATA_WIDTH - 1 downto 0); signal rb : unsigned(DATA_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- signal q : unsigned(DATA_WIDTH * 2 - 1 downto 0) := (others => '0'); signal cond_zero : std_logic; signal cond_carry : std_logic; signal jump_op : jump_type; signal is_jump : std_logic; signal adder_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal substracter_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal multiplier_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal divider_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal log_and_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal log_or_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal log_nor_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal log_xor_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); signal slt_q : unsigned(DATA_WIDTH * 2 - 1 downto 0); begin -- architecture rtl ----------------------------------------------------------------------------- -- Component instantiations ----------------------------------------------------------------------------- adder : entity work.ALU_Adder generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => adder_q); substracter : entity work.ALU_Substracter generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => substracter_q); multiplier : entity work.ALU_Multiplier generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => multiplier_q); divider : entity work.ALU_Divider generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, i_div_by_0 => i_divide_0, o_q => divider_q); do_log_and : entity work.ALU_Log_And generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => log_and_q); do_log_or : entity work.ALU_Log_or generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => log_or_q); do_log_nor : entity work.ALU_Log_nor generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => log_nor_q); do_log_xor : entity work.ALU_Log_xor generic map ( DATA_WIDTH => DATA_WIDTH) port map ( i_ra => ra, i_rb => rb, o_q => log_xor_q); do_slt : entity work.ALU_Set_Lower_Than generic map ( DATA_WIDTH => DATA_WIDTH) port map ( rst => rst, i_ra => ra, i_rb => rb, o_q => slt_q); with alu_op select q <= adder_q when add, substracter_q when substract, multiplier_q when multiply, divider_q when divide, log_and_q when log_and, log_or_q when log_or, log_nor_q when log_nor, log_xor_q when log_xor, slt_q when slt, adder_q when all_zero; process(rst, clk, kill_req, stall_req) begin if rst = '1' and rising_edge(clk) then o_reg1.we <= '0'; o_reg2.we <= '0'; o_is_jump <= '0'; o_mem_op <= none; o_instr_tag <= INSTR_TAG_NONE; elsif kill_req = '1' and rising_edge(clk) then o_reg1.we <= '0'; o_reg2.we <= '0'; o_is_jump <= '0'; o_mem_op <= none; o_instr_tag <= INSTR_TAG_NONE; elsif stall_req = '0' and rising_edge(clk) then o_reg1.we <= i_reg1.we; o_reg1.idx <= i_reg1.idx; o_reg2.we <= i_reg2.we; o_reg2.idx <= i_reg2.idx; o_jump_target <= i_jump_target; o_mem_data <= i_mem_data; o_mem_op <= i_mem_op; o_is_jump <= is_jump; o_reg1.data <= std_logic_vector(q(DATA_WIDTH -1 downto 0)); o_reg2.data <= std_logic_vector(q(DATA_WIDTH * 2 -1 downto DATA_WIDTH)); o_instr_tag <= i_instr_tag; end if; end process; debug : process(rst, clk, stall_req, kill_req) begin if rst = '1' then o_dbg_ex_pc <= (others => 'X'); elsif rising_edge(clk) and kill_req = '1' then o_dbg_ex_pc <= (others => 'X'); elsif rising_edge(clk) and stall_req = '1' then elsif rising_edge(clk) then o_dbg_ex_pc <= i_dbg_ex_pc; end if; end process debug; ra <= (others => '0') when rst = '1' else unsigned(i_reg1.data); rb <= (others => '0') when rst = '1' else unsigned(i_reg2.data); cond_zero <= '0' when rst = '1' else '1' when unsigned(q) = to_unsigned(0, q'length) else '0'; cond_carry <= q(DATA_WIDTH); jump_op <= i_jump_op; is_jump <= '1' when (jump_op = always) or (jump_op = zero and cond_zero = '1') or (jump_op = non_zero and cond_zero = '0') or (jump_op = lesser_or_zero and (cond_carry = '1' or cond_zero = '1')) or (jump_op = lesser and cond_carry = '1') or (jump_op = greater and cond_carry = '0') or (jump_op = greater_or_zero and (cond_carry = '0' or cond_zero = '1')) else '0'; end architecture rtl; -------------------------------------------------------------------------------

gpl-3.0

503b2e44f3fd07181ec33eab1fd4017a

0.47261

3.414966

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/dc_ss_fwft.vhd

2

9,156

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block rHJ+29MZ/51RW+8RxBIyMfaHxYDaaOjBE/eEB1G4Z7n+Y4SNCiLpsD4QV/UHYQVcratvHGJL/Iwh 5tcSX5ro0Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block IjfEfFJ+wSDFntr7e0yFi3zx5F9j8KL+3YLAnStzZfksF7IvXdzwub4fw8+A0UUlBFtDZA0dAWXl 1H0D5rU8tXsQvjlffxb6ttDSltxnckWc9DlXznVYuqaKqt4fkad2vvLjTswpzKhBRGNQogydJlay MVR0AnHjZyiozQlGUqM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Pr9hkyoA4bxBXOYxo81Aj0Cg1VdKc6RcLD5oJK4SjzoAY4EIJwx4DGyAj5fGmZVGGTKasiDv0b03 ktw1A+pr7SIG2+AiG9v2eZvIulAxY4v/HtsPTMVvxB5kGu+4J3xJwkG3IihcHVPsJxESw545tZ3M uQXYyZe4ZI++yNHF7w1V5Bwzaz9e5bPGI08iMS9EkqToVc8OKHXsA/bVpDWJCI3WwgPbInr26//B U20XskKobVxeSRmOdW7CChVZY6yur6EeICkYylCAb49UfiwF8HxZCO82OamUBDapXEXOVP8Ys9Je 6ygeBUm8WWNyXi/5L3i5UNPlWKQIG/cZzv1Bfw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block l2mvE1B53x+qmvvu7ioq8n2bk022Ko8YUnyvuyQWqPcB/lKbsK2BZqB/8oPaIoKnxfcPAfCxwj32 bEpyeiYS6dD58IvtGelNx3jKosWLxCq2UIj8E0r7E6m0iAngMZQ54c34WDCjZ/I7IXSyR6Dl6J7c M1mGM+PBkAetpGJRO4Y= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Gw11EzgCL46WMHUhQRKXx64bVvw4eVlOWxvvByQtkAM74dcurr6NTsYIW/IBvMoJERiE1RyLXWSy 3byDXGIr2+aD+3orWbiqMaNUbmdYQc1v53ls74GUo87b1S/ut+8xQ1K8jKf3yj/zQ97QPhPNQqRX SPmZjGfn5ZHYyzL3QBdeDdj4hNBOH6DSF4Qx1X8dtButL4EXXCizSXYZHXOHiI5K0oS+JLJDrwGm 7YSKzx1zmldF4hgIMDRlE46c/CqrsTWjeh2LfaL6Vpida6m8sSSnHtUGIB7YhCz60WNYKxXgR2gB TqQoSKOBsxwc8N/7NtZzr68DXeo1PNV+vGl7eA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040) `protect data_block g3pFOXw4WP1M7lhfy0lFLTk0YiBQwFW/yjglnWbFB7KBwwX90+LwjAhUk9N/JSUK19A2kCZgMUwO XqwXyS8p4eA9yRlsHWY6r9CfCbO6af6+I1iLx10fwTYJAZZwkswTN80c2ZCM+unOxbspizke0Tc+ GCj9D48fVu9qKqhlQuKE5ppU37Aj1GQ1qiemqPe166r3/94TpiCGhUHh4WNS8/R6qwZK5r/zE0af 5dzyfp5tv8AzseZ9MMcqhZNUaJfK0V8qaYyql+EDay4RX+4S+jAlTcxRLnwV94X/UYHgLlgevzHy D5CHRb8XTTFFfLPXbHyG/8+YOjLA5jRpz4DKUkwLSUhamruvNgBM1zIwTwF1/9DpGGubMRuIKEkr ktZmqntEVHpeqE+OEy6RkWVoNeZbZs52CB6ZIAfZ0xZ8XI05K+pHbMtKGmOkpkf0SmuMB//PI6NW 5X+PkYaCyWjr52dc9GXaYaDGSBpIm7kqBO2QYWCTORLAtouiPpm5i3xsZHRP/Eyl82lbjuKvMiDu bclSwRfCGhEg5AfcFvHk8Li/Yu7DGut6UOZszl9QyGQLSZ/fdkotHsJRy5OgnfKU6UJLOd67PVru 8yCJ6rytD1OP1wLCMVVBo+LDAYURUsnIflpqMCHyzTiTXWymhXbWR6wch0eaTGkKprkyxhjlyIwg NmRGxWwYiuTbgk6HLNLm+PcBGwy9NJiqY+gvXPRaDlsDrliIB68YIZxUm3MMbnm/lQU5WmOBd37W oJI6gHB+NKd4tY6kcGypEWPOsmC/YFcjcdPusnsNTQ79G0RyZH03Disrtov8bT5OTv7G5IJT3a7g HBsw6kP2JZCbtZ0OVG6/Re0783iGXEaeNd2/m9JN1Hp3otjWh1a+k/C0dD4fzE/h4IMELqu4FAcQ Xqks8n4kUoCfsbj+wioakZneX6RcdnxeMnjpxpbnf4SiZUrqtIaJN54UomH47LHqwAe2qozkqQ20 deSsoLQKtXvXV8f1ZZnjrXyN06Dip2ASJ7J8vJ/a0zktUFfQBUvdDUn4Dxg383MKa0l591JaHMN4 DxKJYsv+ZqO2Rhtc/jCRtmiouGtDdr3EkkhkBSHcGHxgQFc2XqtAnr2x4QXr3yRWtvoAdKV0Logk BKucXK9kpfX4WvOa19+5pyeY4Q9XNJEDrYfle00xhlIuSV2nuN4xdAHSIWaFPNE0g0/EAPdd6R/3 gJ5RfL0YzLmbVtt5cRgUPkH8XdSSvIrFJ2MMycMxtdUjxpexRySUh6aUTa4CvW8SCr9Ox2G9L1Hi zudLL7mpQ5/hZfY4+iOGdzo06LCzWn1Gfzh4olNguBgxGZLLmmncovs3jwR0mYtohrPCAEm7WTd4 /JTBVXbBSqsWn4H/7h30gwLoigS2Otznopwn3hHgivWidpere3TSxUiIhBw9u78ulxfpiq5tvjim J+gywzlF2e+xX8X7VQEblCj0BTew7CLxlX07BZLARBqpUA9Ji+4rAEftjcr4hfDi86waGvfha8ZP M3/lPBo7qmyV3sLfy8ajVAsObhar3285Ax8tPYz/GEKpXYM++BORcbrl8hlOKx/xCNJ174vgxHx4 nGeiFV4MbzLCNsbB0dWd8qG1HxE9vExqAmvDT60XenHMeoqJvEhP5DkR6G6AEzIdKP04LznQvXTV uxkOcSiOKH8prgIGhsH+qHvSrgvk3KPih36SMbo4K5s7MIJ0SZzF6HiKJ0pmmfAnBH+GWyLdFYLH BK8OPVOzOMpS0UdA+Cygja16y5c9mnyjIjP+M4AF3plb6szTXgzcYb/LdhLMsTEzd0IXBwGmTS5C B1llOHHYsEArhlrGHk+RQ7OwpbuJkQGGL6//J4Op7zH86raQEwD4/hTs1k2zPotRBl75IM5xDhKk WNtimDjaHX19cf3u3nGviGdqsW5FZDj96kkEuaYKuD2BRTKrQFChZodl65PCvwInAkPemaWn5FX2 9fnau7Y6BwoEERf3hL9Cs2+ZvXacYgZkv6l3sXVALN6SbGHhTUg2AHNXOl7xAGj9VYOE3/BS4bzC irZDYKVYrUzn+EZ3XHJx1t5gAkQlXEkdbwfGk6eoS+yzS87oual1fndexLq78ba406pHKaeWeaVb RCG/TTCKed35swx8W0Av0I7IQ7rPh5TPovW22WP2FKz9PypWWFymWGRBOnjHGYNSUTzkrP8hOpUc oLN6l0z/V9DJ8Gv5DFORVIIyaP14E53QUq40gHWZ69R99uGoEUJlw6B8c7kzgo/tc+E68CSrr/U9 V0IIQeLwon/a5ye9xIxkRPJsTSasLvywZAdjlQd6C3lc3eHkcuuYblZMQhfKreKTOcMQ9Fbj9LXi r798EuKPDiAzOuht3jqpEXuPOzPdG817c2PNxEvyitn7kM/xMgx9rC0wMWzNcVBngQKwHp/iqT3M MrDBiez9u9RCbQmgxN74MYwWJEFUlmxspNV5ElOVLCf/u0ZvHVhl+au2Uj72S+4/tYvexQRktTiQ oC5mxtU1KRTAA4VVBHLmlkMffXxiHqcapPeyeHhKvughSxAWIf4zSJWS60xk8XaPu1AR+42wYLd0 wd3MdiWdE/uFTIdFWlCR5QcBEqULQmzcJ2KEUKKqcTnVJi+HrSaaVxJPOV/iFI9ghjOWQubdfZd0 JUhxHmMRwS6bb8x0HKEJkwdGlwUmmZ7GNOKpoVFrOINB7zOfYdAvR3mxfTfdoYQLASYRUy5cRvaa lRU0QoBqbFEYZDkhJC0o0eEKERSApQRYJMzqbPcp3IFlBzm1FAa9zuC7dDN0BMpd9ZXSEO4NN9SP EaSPGIsZqOIhCew4b04h1zc55Qnq8hQ+sYUZqFGVzBQFkUAaqQVzlvVnLN8WhbDr2Zo1MoC0NsMc OKNp6OLwBQ3NBeo04RiGlaVp5BIrEMVmcWLaDcU6KNKRV9CcSBnwOngFe5+jkyUqKqyhMStKbEOk tuNjL/sfyRv9zZTdW3b1dqSdmPzG/025Hdp7xf33RSy7E0FTQxh7Xu/RQldo1xFKPdQ0U02UUIns UyzpYUbM998v0kEinvGciBFzwQg/vk3V9J4OzD1vKFqS7XFYxfexZxmfhIw7u93817xjal3VBkYC k6C1N/vJXj8FAz0LHO8ClIoijiosNXAQ3sek36HbzS0wSPmDp7Uxo05N29gOW+7ZPWZ3Q0NQ5Q32 412fQrjQ30zYS4VqBeSqjjthXhGaz3WC8SkS5jKpQ/KFzs8HrCTvkgxfFx2XN+OZQ/JTvpHBaus7 Ogzp3p/4VvnnFlpA0PuGMJ0R8s4x/vXf+31fT49JkJLdQ2kJPyDIltE1E1eS9/lERpWkrrjWmRRp EP31ua/CTZbaPhtkn5+1bQrEuMxUyL8EZ4zBGjaiEbYVCbaiL+eAukCuf/i+yQ54yMIyLrOr3Ph8 t8cNwwnCAaRLRlxNcJq/psPwG/Ps3HDkeJozz+re4m039d2bJBmm4a2RYGxpWtvDnb4smguO3UkS nvWA0LmHmZzH8V3yR27uR0ZgP8qbw6iPKF3lfA+SGelIRh75EzY0sz4CeYN7USNx4eJw29ViDry0 +rWHM1l0OVKtqXA2TvN5+c6a4KuSnKKBlocFoUuYEJoL9SN12+LBDpnz/vWQDwcgGCUzMPWGMUr5 7gNq4gwHSaM8rpcLA8BZW8x44U5+CD3l2QYR+vhRP4fTu3hVtCBbxXOzwotN7/CqGS7uBS+tbo2B aY2X9ZEBzfHM4Vftu9RmoUxKVkDZF/tVdgdQMS6Y5KacXj0eDdIdfIJRzXVEZr2EGv9j+NYZsv/C d3Du76UAngOFFI/IDyap7G6XJEWa/V5C18wisGZ4UJ+ic5tH0lakP9zOHzRxfBkAVPWpKvu+H+dS 1P5Yi8F1SY4Rzsnh/QG7k53dsk/pXwc18mNF3CVDb+gAIq66e9Fk8bKmTTe8qoXbwBq6Sdy5dBcI kkvCuYEUerS6m10avfTm3HgUKZV3lgESV7auVKs7UXuys7vze8WvL8zVYvrJm9hCkU3vo3VSy7Po dOQ0lYWIiTU6cYlCLbknvxGA9/mHoFBV5VFNVlL3L3yNr8LdPwHU1QkBy5d6wj61X7tE6Yo8XbGA +HnYvLQtcuqcZEOVRGbOfxtFZXB0AMJqmsDyXtPC2a1pUWt44ZlRhIyObqhXo+lgtO9wfYkJEeqA JjWnpIM+Ca3ItX0sw7pbLL+I1PQBIo67EyojhCkc0cCABbbYGXcwLC7IRDnU2BOdmWTn72UmliO+ vmJ17UnrZU8hUIBidl+1Ex9VqL/+4NX7wIvHO9rd4+bgDhjCwdeTCjVV+Et96+qC/UMOMF+NMf6l qVkPgdYTopKA9zJqN8q3GCJe59Fte4ty/Msm4aw/JjdX2XXqftGqIu/DiPsoErsleHWp4CRfjV6n z4Go4Tf2wz6o1+ZOLD9mp5PBF7o7vM710GIVvRUpLPh8ov8VxNy0nHjTGbNqbQ0cDO5ns2ozyqEQ KjlO+xrLgq3bpQT5BzUleDeU0DKIWkL7jwbdecRrvo4pk7vcx5VLPtTQ8hZCosFs7N9ftrctUDYi wPDUbXMr5uU7Ek130Q5Y8YYfgKi9VrnGn8LuU8L+n3OQ1XG+48OcRfpE4O+Ay2vFTQdir7v2c7/q IDgy0tpKjTCnhrt0PAlYfzX4NMWTp9lE4tH4jL0wHh0gdrHWsjr/puLMm9Oxoa8oTLScUUjU61gg V0tpPYRZnP4q9GqBfJt5Ch+OpQE1fZtptuGGL7o0TYHJs3CnYiqE9m3fZQlUlBH4R9H3d7oNP+5j KB93+d6qO4mpY7/cjhBqkCWaGfL7P7mOg7ao7nqTonEpnleXwnW7JMrrlIsE1xqE03e/SaruAlKP /Y8R9iPgkqHHNEkkPBRfRkPmxBkjWYx491zh/Gp52y5xCLr3xFP2tZBeSOFAbjDbf0ZGkEsaGBhG Ci3M1Qcaz79JL3rceaWiFuHhQ1iBF23nQC6UeH5lI7dK8RYGRAxyzvV6W/4VoZvic97eAuJ1kPDy DECYXS3Hb7Gx99XMeVcJ0y6vXBgMbstx/4kiRQmbybTReCPIEACue9hU26uX3/uw3ReB/rbBW4Fw VB0TaQNc+5XX19kDoQ8DWxWl16UQwY4a/2kz4ZRmeWdY6PS/WP74RPQzqUAg0q97SzVWvvm/Cyp/ VFEhL6MmUNsRfHoig/8lM9XNDndmQ9FlThbO/VdovrfpbQwBTE2JYIAKy89jaoJeMaHMerE8FYr+ zeD4ouwrZWQxTO+DIvRnA3I/yE1Pr0lpMcVDELF65mTRVpHzPPp5ya6E8Xdw6VQOYhY5DgD6uR5z 0eYg1W02mftCb9wlxhncwdEE7t4g5uJqWTF7Gf9Yp/PFYWNC4bGb3H6oJoi491MYLrQY9fKBSIWT kOIPFEGBk6VGb4H1uJ7BnxYiJTXf8HYGfFmTxnDIyflDM83hYMp7mkgiyTJLDsBzoS9tvqNV6YQx RL8WhHrkS5clNgn3fcULm9JLzYhLvN14sC/xUQCICI0cXzbCMgrmEm5bgOkwznEb5QJ2Ua1wRQWl PfRB6gtKGW5HdAak4+5LieE5ST1eJU6+8Cygc8QAbtUSSJEGow7aUSh9ajtQ6dbSYCG1P/KXaRux uzwhh361B5rfDf9EwFTLjI4YZMAEiEBtACmsckcJ808krr2bfQdev+S8HMKUKNXC+XzGjE9jAA1d QHbjkHquQdb5v2BWY9k/E02BpsCoO/juggdIWWC46MUDHhqOBRnP5ri1T0B7ykD/80bAMvaCLDON IxoB066ZjjDMMeRjCdznV7u36RLiIc+pJTz13+hYFx9YOIWpjaQmNac3mDqVpKMiIjbvWwXD4VlB lp8Ia4dLtLOmRwLJYF7osAtv5BuLbZy20/jxYX6EnHQmqgPKiaySOapGl6z/aCO827uWm5oxHAvL 8d2BZ0xL6Eo8C2IOvVChMnseDTvzyyi28YXjVnx1l9DwUT/FtGeItpeuUsDf1HYctrcuvCp0Ehg1 WkBJ4HlsquaYRFAfAHS/KZ86lOpwwgjXIkRRTM81a+eIYC1Gl0agURIxWsbH1RO1LIRgRVWjKUD2 8QkTYiew2iWtCL2qwrCIWL4IeVp/650F5JxD8QhjNqLQy5v447a9Tlgh4qSL4jZwdKaLTYplbKly eeuHtopNIqqm0lNGgLZ+YQQcGgAegfH69U2S/i3hb35A8FiwdiKTjSw13R1KnZ+gLSCMUkuChmhK R7j+J+a++nWWlSMhz4xD01N1+MjW4RrAUKKvSikhsqBKadfK6b4i10glDyrL+Hf3d6BMzbtPjolI kswGkCDEJcYtWPyXbKwHYka+9/Ntuc2al4U78fjjdpUhlXcPHXAM3EtEafgHpxHM8Jvfiglnc3vS 4Hr/DLBjDpvxGiS5WR+Z0YLYn/4dagGorR2IUCziNOTvkkZpNKxyk+LBsp1x4tHMSXdy4UsgpTnW TnSMayh+eCy7NDWdkqtTNAPG/tFAev5Kt4e9PjyuuUpfMMPc7M8LaETrqQLN11pM8sYJnVaX8iiI pD5beLGbJlLrCAsj38A0e/JNcH0PmNsAY/lpQUOWjZgG+zFVoS6VaBVeNsNvjpbuONGzcioW2mt3 bLLI789xDIBwtOFtxdrNSs26/GNhIStnummenp06/kWxezj7XvGQEHJ9Wee3nwBl/iJew6KxkU2b vUIybHyy34lpcNNHf22T731L+emeLwX6 `protect end_protected

bsd-2-clause

0f20eda2c4d6a4fe5ee677da71f6dea9

0.921363

1.902348

false

Yarr/Yarr-fw

rtl/common/ctrl_regs.vhd

1

4,691

-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: Generic control register block -- # Mar 2020 -- #################################### library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.board_pkg.all; use work.version_pkg.all; entity ctrl_regs is port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- Register Outputs R/W ctrl_reg_0_o : out std_logic_vector(31 downto 0); ctrl_reg_1_o : out std_logic_vector(31 downto 0); ctrl_reg_2_o : out std_logic_vector(31 downto 0); ctrl_reg_3_o : out std_logic_vector(31 downto 0); ctrl_reg_4_o : out std_logic_vector(31 downto 0); ctrl_reg_5_o : out std_logic_vector(31 downto 0); -- Static registers RO static_reg_0_o : out std_logic_vector(31 downto 0); static_reg_1_o : out std_logic_vector(31 downto 0); static_reg_2_o : out std_logic_vector(31 downto 0); static_reg_3_o : out std_logic_vector(31 downto 0) ); end ctrl_regs; architecture behavioral of ctrl_regs is signal ctrl_reg_0 : std_logic_vector(31 downto 0); signal ctrl_reg_1 : std_logic_vector(31 downto 0); signal ctrl_reg_2 : std_logic_vector(31 downto 0); signal ctrl_reg_3 : std_logic_vector(31 downto 0); signal ctrl_reg_4 : std_logic_vector(31 downto 0); signal ctrl_reg_5 : std_logic_vector(31 downto 0); constant static_reg_0 : std_logic_vector(31 downto 0) := c_FW_VERSION; constant static_reg_1 : std_logic_vector(31 downto 0) := c_FW_IDENT; constant static_reg_2 : std_logic_vector(31 downto 0) := x"00000000"; constant static_reg_3 : std_logic_vector(31 downto 0) := x"00000000"; begin static_reg_0_o <= static_reg_0; static_reg_1_o <= static_reg_1; static_reg_2_o <= static_reg_2; static_reg_3_o <= static_reg_3; wb_stall_o <= '0'; wb_proc: process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; ctrl_reg_0_o <= (others => '0'); ctrl_reg_1_o <= (others => '0'); ctrl_reg_2_o <= (others => '0'); ctrl_reg_3_o <= (others => '0'); ctrl_reg_4_o <= (others => '0'); ctrl_reg_5_o <= (others => '0'); elsif rising_edge(wb_clk_i) then wb_ack_o <= '0'; ctrl_reg_0_o <= ctrl_reg_0; ctrl_reg_1_o <= ctrl_reg_1; ctrl_reg_2_o <= ctrl_reg_2; ctrl_reg_3_o <= ctrl_reg_3; ctrl_reg_4_o <= ctrl_reg_4; ctrl_reg_5_o <= ctrl_reg_5; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '1') then case (wb_adr_i(3 downto 0)) is when x"0" => ctrl_reg_0 <= wb_dat_i; wb_ack_o <= '1'; when x"1" => ctrl_reg_1 <= wb_dat_i; wb_ack_o <= '1'; when x"2" => ctrl_reg_2 <= wb_dat_i; wb_ack_o <= '1'; when x"3" => ctrl_reg_3 <= wb_dat_i; wb_ack_o <= '1'; when x"4" => ctrl_reg_4 <= wb_dat_i; wb_ack_o <= '1'; when x"5" => ctrl_reg_5 <= wb_dat_i; wb_ack_o <= '1'; when others => wb_ack_o <= '1'; end case; else case (wb_adr_i(3 downto 0)) is when x"0" => wb_dat_o <= ctrl_reg_0; wb_ack_o <= '1'; when x"1" => wb_dat_o <= ctrl_reg_1; wb_ack_o <= '1'; when x"2" => wb_dat_o <= ctrl_reg_2; wb_ack_o <= '1'; when x"3" => wb_dat_o <= ctrl_reg_3; wb_ack_o <= '1'; when x"4" => wb_dat_o <= ctrl_reg_4; wb_ack_o <= '1'; when x"5" => wb_dat_o <= ctrl_reg_5; wb_ack_o <= '1'; when x"6" => wb_dat_o <= static_reg_0; wb_ack_o <= '1'; when x"7" => wb_dat_o <= static_reg_1; wb_ack_o <= '1'; when x"8" => wb_dat_o <= static_reg_2; wb_ack_o <= '1'; when x"9" => wb_dat_o <= static_reg_3; wb_ack_o <= '1'; when others => wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end case; end if; end if; end if; end process wb_proc; end behavioral;

gpl-3.0

089f51d60852cfa2a369ebd2ad92d409

0.495843

2.702189

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_pf_sshft.vhd

2

20,160

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block F9G6dpNubZOdcFjJsPg4yGA/lxMn90z+RAo6UnWnrcihwIxe5JWhi9q8L+/4/oREa75Ngvk7DQVE g6seKWp+JQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Hb6FKCBzWQ4rBnYqb+vORxcIRgAfgPQbSN8Lj4sDZnZBaq8G4IMUME3iyIwZHkyV5R3ZUWNIHIu8 ksP2467Ea/TPnHKYBC/F3fuB9s6dVI0r9GzKDYvaX0DxXKppmjgeyySUYcUVoHxg0gIoMsV1inqP TgEoCyv2Sr4TUsG57mg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block dja7spovDKtAWBakQxz/0HG5ecXk+zKMJA+UKr9YFT19EqOhAPEWiV0tXQWh49QbUjFyCZjkAOeM k34qRJ9x3w/sWyFssAGNHH9WoWerts4MDiFELf8NjsYwP2rALzgiv+0xY2dVCdow0InUA394Sazd oIw9KqGCd76ynjgRALS4j1rp68O9orO9MPT8ykPXge2efg1i653lnA/5B/m7zpbcHB33yT60fuRY 3JY7odS1n0K1GM79/8QACNu4kcVQcWeexjB/ORpZeVAGmOCmERaUKwsPA1Mr77N6im6ErLeCj/Kj OeQYszXN9eQhUYtGG2MNZzU/Z3sAYQK2Y+3Dxw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 092wbQAUa+agI2J3y2F6rmVudzHXyIDhH7KN0gCknwG7HRiIQIwXopzJgIiccVKXNeFivr5Bpj9U HEZ9UA9IfNCPs4KbBUl4qczOUByImW9Fg/k0nvBDORYj0Avxl0N8j9OVZTsBddkdhEOAk/fV3D5i 2DWzzFcBB27esjY+SsQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block m56rCjBT0e8mkwtg+YvzZgfnsjkP7faUa77D0Senvq56+SYRcybQPdbj4QVKjz5fbXy8y0qINc+I Yd1z4Y3/YGMBlgL8uBe1Nb2Yea49J/Q6TB/EKhBTTahZpbrnOcHnA56SUw6H7mremtAYwq7RaY7c 0FqIfo4BnIagEv+zdsrOomp3r2Hl3kLHBCOebFCY2DtxEUrk+oQ/tXhBhUTOUTP4JwcvKI2gkhkL 8hBEWM6wHOjk9vJmHClvvaPKPhZxguxiUad0uEFsxPlYzJqp6DcckvqSQYglJX2oB4OmOJ5mMfRy dOniK41V1CMNVIi43Z/wgYyPJQbdahdxsejGeg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13184) `protect data_block u/GmWeDZqKz5KQvAKaqE9N9QKxvEfj0yIqhMgVXrpfXnTe/NvoYCsNw/hr9FKKZ3ipdB2jBJLy2o fKhOrGog+cqwT8quchYiayixd6pmzpmqo3Wl4tPou/gpfwU+auo5qza5U+1k0HzLRH7vI4WIEe6a kiCygVSQq86ij0YwyYV53aiNqFCodKUxnjAaCjQOwKa30L5oh/OG/q3/md0qLf3BqOLGCIFzSS3D uK/HKYfUgMjd04YAJtBbU7pnf+hNvYQTDZj1zo+2OcDAqaOxEBEmMW7lmIfFodkXx7cG6020t9su fJZSazJx7rD37rNxmsLGLIoCM0WB+siZv8E7+KMtRedfvFhML/RxgC+G5Z79paA84UOQVF5q4zqb 9PB5uNQmOD0w3pfodMP17o0WWZ/ulwI3KTMXipYUll+yAVobBuYY5ekoFQgSeJnVKOAPawdmpr+p K2b+mIZFrR3drXHKR6rJAHU5pNSKjGujx8NYMj2TagfZhKLTtVIBSsZE1FD8QpeNTk2OHznrtOJ1 458O69tUm6+Kz7l4zqOf7B/7jD+7saC15G+bGGowG+l5bOgI8HR+H9eHIrbIHS34dbG4X3O+fXHi 9+NB1Ofgs5/OuJmXHGaxAr6iQ5gA6+Rg4G2L1sYnWy4ZH7jsjS3c8dzTa0ytNG3K2mqr5HaxrANI RzrVt5Yn+T2kLmXmt/ctwlJZic5j2hI0wayHJTXSpi4e8lnXgDfpDqZSIt2f7gSr1BJYYQMPrgPm rx2GFaz0YezHEixsv/PeJK1LFwFF7t3TIKIRcMNNXoWbxDQCEh5fc71WAKmDd0lfzQh7NoxOyAbZ Xpa/gWaCb/VtDXnMnAcFg3odyLi5JZNpvyCV1i6TiSOuACWX9lvR6VLzjiZXXfqXASX8M1lnt2p8 2yGmRjL2aQE+KjOgNRbE/J6P8/yafr7MW2F9XeKVmvZqWNCJDGvrorZRj5/Z+RjHSXP6AQ2srGBr m6rnZfQkWXoVLM1j0D1cPvTTwOsqR6rcuzrZ/foM0guDaCpIDy8nGA+6XX9cRYYxf3Cd2Ftf6/MF b+D8Cragh+rvpsvj4EZoA8/zPsngDu2Zz2b2kTNZiurzwsCkoWI4D43l+LoU/9YsthGgYTIvSnw6 DWN8x4sWLaWLkp72nLIvWn5B+3wvWsV9pLURjF+XN8Bfuz4vG+Q07zOhnOmk6OyZJugvb1dSWSeN SxgbYZS+Q/Awrc82tKbnBoqmSToChfWRvN3zcaHABD5mTxiEYFpg45DrWGJsSIOHn1kAFmkGNPgQ kRLHpDLjn3A5xPrfOovzxJY6NO0b4/e1TXjvw0jfkwWAHCPw8d/YysSuO9EIDPV1y86w8qODBK7H UXkHuNPgT9lUxu+vXZ02Proj9RqamfYQXNFkCAotP163TtOvrBH5JX4MkjnVcWllmfcE3UvyzsqP 2MTFKyKkDj8L230KdKZtuv+bdFsBqNYFZ507bzhRmdtTW1IRl+nry4LmLIbT2mWsVOAZYPWx8qDR hITlz+f8JdqufltR8NBzTtp0y76HNshbUl1vWc3edIRYwkGSBDz2kjJw4lP8u3VcKOv70V6rL8cC TI6XfiP/pVvFAb5a4U7pRCGZ5A0G3F5ojqudJNOHW+PDwZbL27f5PJ0nCndMryE+53yGRP2gfLl6 OlGWl9fajHfHJbbsGzGkXpq3GaXYsVJcoYZr1ZXZ9D5z1SCamXLHAYs3ky6GZLDP3Z2Tn6S2qQgk Mtu/B/X4WAfDgU1bm0Wo4VbDjYY0/QxqUgwi30aYLyfkxlZ6xIc4/4UD+efq5EoWvPiIFD8fHO0z Oiy0XgHgTO9dvaXMh5+jlkjiKL3L/Pbnpfajr1OeaMYSa9jJ4bZaWEs0Ol2rc6Yo469vxGZLhJAG br1crS9xU8hJxwiesQHOhftctW6Yp9hLWu3NMnz3FVvYX/Z6XNGU0rI2N22jApsnGszNeFHZrvB0 a2PAsfOZd6oDn12dvktpvM1B/cHLz9rkmfZJtE312izxmETkUTjen9lw2IPWBLaznUCt7QFy5Xfd FH5RN2OZMPBwXhDsoncnXv3SOx2keHSokxsocQmmbEQInvGOLaiaE7yW+NPJTWVK1esDIixlHxr6 MTVPfnGI7vI7S6Q1iYjloEUw8783n1xC46R1RlBCk2X5M5g7M1SlZepTOWQqkbPOCDulm1MuGJcf dv+M9ef+ReqK20JOYSZfxmgWN/Cc0PjIgj+yjeGx4vnI3edxBixr8qoobEjxfUWvJf3aRfhfKpWQ sySgPjY3w/+24QnD4qEjxChKreGi3jyyLeuoJXShlAA3Jq4BoWLe2JlRepu4m16Ya26rmQ71Hgv0 O3NTssQzTrRFyxTmu28eF5QxJgudwJcLcErbkDuxdiLgR5p/u7cRumpC1+d+Ry4eNZ1mlJK0PTr4 zuH86v2a/ogCNQm5pA7hcNORHNA6p5kJoKYlYb+V1oHMKbOrPvhIKKLversoEp8Zs0y5Ul/e4k9/ f/APwpDvaKSGNNCDqznJMk88BpMzuME/S+UwE21W1AIwY+2N8u6tyuCsE0kaXIuY9Ho4ZUgVdLi3 Sn8s3KybUX4ciou5N4qXEc4SeYFI11yzyqpXAfkjxPCwUkOdONI9fX6lBucI9mFKSr54vFTCwm+B KOJgJPGw09v0hwqlXWPegP1LtfrLY8mvyT38ZkH44HQUxJhSO5vaWLdA+6wthgmRvaVA6KNtMObq cxY4q52whnIeMrxpjf5uZeW87TCgo/11J7yqaUFqg45cFLEDuz3+ZbpeTN0xJmwUF55CHO4Apo/u 7N+a+NCm1YXM+/IicaeoA1q5KVgoALuoeAcCYhmtrm56CeCkSLbzt9X81bkSwJF92nBJD1cacMtA Pt4Co6Ad04eBLpSMCrSLEB939JqhmWzcNZugEXLKAAWNav5aPN8SbyTQ/mwczftNp1nnqzWDMIhh fsL0eB4CRUug+lUmBFup+Lbpjk9VnRJGlqaleGb5qqG+u/rhMBZ1qM2NLxI8+VEkZuSZ+B6AkMPv Ibt+Fg+PXZOT97Rg4+mky9tXxYamSoO/I3rgxA/e5b5sb6mXJzTqF/Nr6N+7AAtXw8es4aIsj0Eg q0u65u+FAcJhCZkZKghooPFS44iwEQxCnBT/gNSBMRHuKSHQhLIBcdxoqS97Ur9lI+MzsORQLkUU hjN7nLxjnMzbnt2VsFClmsR1+Hkk5sFQJ9a3uGONalTqzblVWY5Co+Owp7Du4V0JZd4FYoWoTVxY uf7n7dqogsMLXSNztusG/y+2w7pHL2GDqvJKFTLJYjU5cKD+rn1UJQ4SObxCzE81crma90nBKVi6 aeDduOa/1ggcoYyns9MVXxnGHXCqbbtZKIZ3Qwmu0rCFsTKH2h/kcLaLXE5yJTXIoogV7g5r5Nuu CKnR6kL2ZrzQOBnGfvFIKxTGJaeYsvrAqRUDWxB/HwaOjdmps27t7zoAw8q3k/l3faoCNA9fbTpU yDgBfoC1Ovtym6JK0DCkvJotPORZxR91RZceL5ZW1giyjHImwJzkGcXStXp2w8ViXNgGM+x5Ggpo nS3SvpA2hrv494KlcxjwrPLIDWsc/oog4G+UA/iAx9HpjkfMb3yOlsRrgDdSFEykKJqu/0fpVKRK G8BXMVWbuinThYwwT3FOvkAuM/AaEjSt3E+P1xISXLussy992ezlemR7z1yQeWEwmpOYuODA+wyV HQK6ZrX6V4xrlzOTRBujSci8mpIBmUwbsxXVENHHUXtqV2ZJZy63aftKeSbpMDP/+Om5CNkcyG+N KhF5rAtmgJImJ/6+9FpMTmYkOMlcgxFOTx03Pm7moJSrXgqrgsQy9SBQ6qC56lYKceW+D2BHtoZs kuDA1+ib5jNz3FmGhrakJQrFbUeu9dP4/PocIrjpdsqpu8LCj9W3bmu0l1XC7yriRhO5awSeFZno ijDAh+8yXsd0TiyW+wfnCaGVC4PRgtfuAZuTuldamfp+wD3yqL+M0ci/rwmvbsjai10U12ErlyA6 oJ9lAQ9UBsfIhOYHPhq5mQyRfruxn97/s3abIz/259dl+/4r4z++28FtfreXCKDj8DSfrs6wD6Ak iDXBuHcvDLqYdSzRaIqb052nb1yVScO+2m71LJ2yjm973qysP0Q47hdLG1qBTD5eM2r64MxOLKsq GXuKROO/m5u/FYY2fxqsMxrA3coX+N603N3MLse1p/CXONaboT+Y2bE1ZHPXOt/vXJd0fyrnuYNL pRICV2wWAhPtbfa5h5w+hMZW4ImRw2ZLXQnWB2Thh9kJqkFxYNL5nP7NtesIyLmCOvUXmmuDxE04 viUvwsLdpJKHGYbVBxQVjVzxkegkTA+joIjDK/6jBc93byL0CDmcmE2f+FI3A1jfxcy0bpGqy3v+ PBppXYREYz3Tps9TZL7I2JJbp0Hy+//yPD8K5DRfhXpQuoAH/CMyK9nGeQ/6gzNyZRsccAqlMU2l jmlMt6GyXcbMOiF9BTXpzhuzHo/VTACxfS6u2t0BsPSbtr4a3gpbivJLOroGhS9RtVwpe19KLgYU Q1o6Rx/2zNWa8woUqNJNsAs8DBLLPHRtTJwTH+lBc/f4Rm0GRNziPwJ93R6bB7Qji1WUvtR6uw7+ +wHjE9i4NnIdMM+CZG37V7hTTbRH4uxmaa9zCKi2xFmzRQG/RxSjCsY9bejcBwln5WZW+8gtrXfc pita5wSEyElkdRaARY5OLlBrfSaaA7/V6MpoGbSNHZ9FkfM7BR7c7Drye8Ig6N+ZWUtE4L5OD4mI NK5XvzoKecE8gg/v/PehZLYDDUKXUu0uX0E7Qq886TA0qxOhPJWSK/aWX/RLfDr5XHreko64hLd3 SQiqPLO1AhJ5b/uXQHc8qRIaSAWsjZgdS+juAb9YxGwCETZNe166G8MtaQCGzqWdXcKz8ZPZuy5N 9cEkuo255LuKjdG+9iJA+DYzRq4pwq2HQJ+9vO8qvt7INWr7jgRubagMvOGCH9zWBT7Fqk76HzQC 7QgKdypbNl3xTC2x0pptnWJFiYEGV5JvHyusovIrBknWuD3MNCsmJnepiRlrcdbt2rs6b+4dU2lm E0mHWfhbY7j2QChhTyg0PZkVjsJXz4clTLTgtnufJ7AmEubabyGEsV63kDO6n/Vh1ZF5LBhAAgPP tzkOlGau+3lIVhHWcbet2CKA0lknla48W78EjM8kZCNffCvpPk7T20NzaJ8xp5OVHn662j5r9ErS 3mp4mqTHqHY7k/QJwQBQM9+QKWX4uWBS8cxvDc7wdtQdhrD48FfMrHOoM998YhpG0MvH2341dPT6 LHwmF3ez62JtVl1wsqauX1Ob3PqafFKOf/J+Wg6y98o7w2ZsLaeNXOnHtmq+YZBmq3Db1J49OXMF VF+wIRxpZ9zQncsRsTMsCPJFL9PgR3zYueitWv3jq5eAGqiCA7qPPAB9MxB16NfRy7pf67JrS5K9 TnCSJDYhLe7NKM7RPyq7hm4lxnnefqexp7LbNpVgMKO2XJkxU5hJv8wvPyF5+qefQQYJzYXdRX9t DDcDowpqtSWbruwGcEqcWZ3uFwJpFYGI0OmsSpl9XOWktA5T5Cf5Gjsdbt7iu5B+vE6AoRRsW0ro XnLjvnz9rvRVNlUSp0zbSNZaepxYmnyaovc8ZRfrhxLIsN+SA8uvY6hI7Qyze2asO3wxAYbNls2y +X8TJnLFT31azHexDc8r4n14wZX0jxmZn9RIe6EYKg2TmZODTMspAjrMsXrby4drXLNrSF22sD9W VzNeeywXkHFa3EPA2llcAeJjwxVw3KgyU6ErcSDTZTw8eroa0ErIXZ0emyey+1OQfnntmcqexf8l yzMTMPsxI0GeH25FzNEx4RWx/xZCAZJWfjiCnz5us1egrD/JOzoKsWwQU9kq8ii66OPGQyH5o5lr taH/Q7AUyWICoTMSfy7/7BNSXCzzdnrNJ8UmpQH3RnjNydvinEgdcnR9ctq7rwNg42G+WULJGgNv 9q56Hy+otdJ1sGGIMTE+cDbSBCo9lqTnDPwStk3zhkUaEAbyEuDf3eeP5oG5kqBTl10bsPALfBRA 7czuLGVOEcB0knEgBj/prGYfzyEsxhMmt6FLDACajtw1WReK/OBeE3sIipdIgrSIZFTMczMAD/Qp MjlezmWc65gmWP4Gi/Ofnp0uYIsR5VrhgO+hMhkEg5420Qm5DHIdfw+cxASythoZLJrMpgwnmpPh G3k0F29Kg7XeHK+8Ln/hHS0wN+fVYUEtqOzTMwCWZDo5/4Q9IZ+y0chCC2wWKa1cSUo3GUcz0K2t BDZQe8ZW4WYKKpXoeNT4763wGdGrfikVOVkRKAPlY06Qw0yXVXTB2hbsvzu0SitLLNdcp7gaASAN KGeaD7Fq1QgsoBwVoLeQdIRZX1nFwEKAv9PYnQ1MBHMwslOuhSgh7C/3X5kVWuBQ8D3i+XRIPA5c 4nsU0TlZFI10Ew04dOzE6bdJwERPFtDOt9t72q3/z86gTM2UvcqXO1TPliqVEP3dNlTptCYIjcSF cVcWxpCPVBTfYm4LqsZal+BuRCV8LaBPbYSIbEMzcIBGaFY3hB3yDQMbPfiOY0u6zpQOe05QZBkl IA4psfmjgSchg45Wpb+G/oQpFh0nwdXIykD5oKxbl5TuiADLJ445OLg0k9Cp89vdZefIzBf3Yd09 0CidL743JqsDjSli+7tAwoHZxMnzXzMC7qV/9/lTCYztXwz2sHvJc8pdO7Mms5vcv7rpSg8W73uh 3L73D1UUqjlkRGjX9SgFBz8Q/RGAXgUs5DbonOjM46JZgzrA/V9pxpoQtU7dSJ/gqTTDFxWUzqTz 9O70lUKbWWZ9WW9qkcYV0NrG0rwA4LbedS1TAlHehsj1agzi26ioe6mHcFqXB93EcytRvqmRaJYu shbEIcnc9Qf36CwiHJK0Dyy9Tl3zy8LPmozOR0zwsZFVUI44SWnj+u0JEi7pi7SQa5q4c8j4IRns 70Npu3zBags2y6SEqaJpXgshOuXujaHU+GYZIydKf7qzLaPcPMLM5vy0ShKQRHcRrzl12IuxgeDS MC34mVzQHNNCMJCmF+uJyrnnwqjDzbivvlquCIWjC/Qwyc355SZiveU8syqmz7ccZNeJsV8tgAt4 UiAywgoy6JBJnZ8SRF1cDVHExWrqcpE/5m4aU6lTsWWGK7zUEFYzmqmmkiNCjJEgDT1youaeXhX6 +X7j3zf8GbvoPvNLHRAOLhJf0eLp/QPeJhz66/QJ5rVEOg3N6ssbN6gexK62x1euxEOSiq+Ewhzb myywpgNBDeSspBLQhUahz/EKBG9GHoCWyStkMiEnIN/b4xKfE0Ryszm+tF6Bt09h7DU54yGUXYV8 +AKEU40Db6fnzoaWKpCcmEPI7KkOoDrfq/MzfwHF7jLGVhGC1nGBLyyEAeayztJE/vnRW78kgVFe pHsPVEThLTqdODZ5vgwlBWEoqRA9emwApJYJ5s4v2Zjf5+ggB9aVZEecoSbXlSrGoLh7ef8zqXo8 z9f26uPFJVRIyZtVr1uWWxQA1i53ah8n6orjyn0fZ3JbABmDKKGzMXBcZQqiQJH0hojxed8RwhXG FQ9PrBaJp4o1OBOW1Yafw1FE4xwWrH+vPdd+eJEl2xsuRXVm6hDTQ4wth+P8Bi864KQsDrs6YlrR 3tIKgyQtGyifXqGYH+7mKiorrj25qKixWMvEYVK05rUIjnSOjpkyeiLrrtYgy1U4ACog+qgFXVk/ ZSZ/uLSIL4zwS4bKwfR+KSVJ76h4nAfvCcEVuxeADR373X98io5CjMUrSs45pI6kwlQVZaTj7kZe Bma6xtDQ73cgRMoQ2PgJ9Rw7pqNA9kUa6AmIMkUo01yN94LJw/f2I6fxxl+vjbsX0jv3sdPQwWAD vmEl4DGRpaPs7izAbkSk/453f54A7vmI1pccff/sx+mGirGpeEQyx9XZf2mOJxI9hrg4zsrDgSZ7 UPxziiAvM+5PxuvH7Pag8OsizGAKnMODzQVyUnbiwGRDJ0KeBYZDO0UWvcu9XVd1o7Pstyer0IFs 3b95z1Qr2gLD90mIPDm0174wmz/fLHD7adFkJrzIbShVMlJjgXpCHd6WKUtO/ySkIMJJ7u2SNNR1 JifadZ0UDCIsIjuhL6GWKwmNqQEiHSe+1nU8NGQibPacskYLgS2vf1fwioMCWU6a8aIeAM84oMrj kZlpGC0JFXyTbOx405SX3YLGzELXU1VpRgLLPLTWLfnTwziNgSQAa1fSrh6Li786qYM7iv+B7f0J dQ1HXgeBnlKYjAtQB5MNpnVf0qrig7a1wFKI+aReHPVBHTXnIlzVo3VYzXqtp9FNwKsN/H8k7GWc x4+UfkL92h/2ip4m6jDJWUlcytO+HECr4xqzI0hTBa1ReAyjP/BTWcPgDLXFPIDl0fWW38b9rXOR c4KObHJG/Zj85SLfpO9aZDOCVVdCiCcPvNFkW79O/pdFk7ee0s8ijySdFPWdRycJKUZRmx36HFax NYqOULENvIF8+UW3ESdmUv7CmCieP/VKBgRTX0YOyd+YMClCcLFRhBjqmM5FMeQDPvxql/s8+h40 Dt1uZlD1pQMvNwjSM+P02b3AopoRIX1EQ6tpCEdPqopvxJTSHHqHo26iP6jO064ohbows8y3T3he FarT+kHbitzikAEhiz1zSSsjSUWsY6vlwa3MPMLwPRN64gDVFJLrbI9fLrNy2o2q0sPg52kURns9 AGYOPZevIqCOV3q1x3UbLsoH0S7RsETPJgjMZDvf0W8gmdiuOdBk04AkiW4YwVjdFMfuklVGBriv h0zcaLSBew7wUaDaKdMuDOo6vGnBauGQF4Bpa7KWx4EX+JvDjyALFT+W6Lc6WbAbEPxL+lNIUZC3 U0ADQOG4FeJEUzX7v0UfufomH9skn14NpGRlcYJHyIDzEsyB3qaxPJHTmtPWlBEUftW3zDdz8dBn 7TadTdpDVRnhHVbnz1gL0bO7+VaPLF5hiUTs6lm0NgU+cBkPk/l3taAX35DWiRw9mbjcFLYFCZup 0K3J8BwQgNnLtF0tNaMl6BFtsycLe9G8qMRbqBE0wzrM8JYjA+gNJSgz7PFF2K+rnUdPiQyOgD1m Gp400QXkul+rD9yJ7/6pwJksJEw0xqoKeb/X564yShplrMbFwp6KkPVcYbUwGJMJ6PchSCuFOBO2 cZNWJuE0ZoTBRKgN5pVfsyBYsZOvSnD4LSVyPCDkF0A+ELW/Z/SH6IGCX6EDoV8YYlcbuTM4xk/q FG6WlzKBNvYjexv7JpArDy6qiNk5Unidkl684OzqvGg3JHVA+GU6kAY+V8W5vtx9TdZFn95+N9GZ aI4fmbOfialgrGPuTd22Z7m7v5Zjqy3tnUYPvj08KZS+vKV8xE6b+LPH8KRWvF4TrFCQLU759uXP 6rqime0AoHHYmcfoYFXX2JNcLBae2lKTjurzXiTqIeQIG9TLQsw6tfVwnlC3v+FdYXm+LUVdJL8h 5cC/sueK5ECxFjoQE4WK+VXNSlrTjyPeCZ+/kZ8WBsxO9/yPS8anHnS+QoTl8kj/Q9AMBLZ25Qi2 4zE7pBWQHQIxKEj2jh7yfi/i/5oYhQk6xm/DICSIngmJzJTRV1YJJevrcUQDyjY70bvAaVI7vUtP g8iNBY8+KCzOwDEidNYwA+Fe3E3qSwV56hzOlm/8yQezksArvk2yoO3vBwb0xD2972HW/87vy6YS He6UicsSvg1s90Mk0NN7vpyOQAIQZ3Z8Yz091w6K4Z0R5d95rtXqLqeLExudWJtDng0j2kje4ok6 0c7dGERw2vJJ3tVKtwycuR80erRgjiiAnwXalhO6tzNMs0TZhJOONO5Tx66d6a+aAgSsGLV1/bzm Lmwk4fwiFOImKXizY8hHI9n87YYEbj0OCmL8pKYI51nzN8Tw5A38d4D1CDrw70cuICxX5I3LezW0 j1vtyEysHQcR1DE2SrOqKiOO9IWT26ANYak48AuB56XwpiJU0USW84PSG9KVg8/sEMX2YKejT+tp 1Hs9EqIUKxApmkIezBxYFd9ZarfevpOBNbv4TwiwRaGwAyNSjoZMvIGgUgFpyy+yR3cSX0UMcL4g o6xWKT/vvagMLObWX2iU4gbHtkh0PpXT5rdsNyiTRMXIbfVcLluCwjS2V1ALVOjOudH2QJDe6VL5 NWuC+Mt9Eo6hFIiSkyb7FBbOYzKYVIfAsSCoJqlSrKP7o7rDM+5DO+1f21LEUG2BBMJzajUBNspT 2N5p0vRiD8B2rCc0IpCLEAJhaQekU6MmRp6dTnf8BYowb34Mqw0SY8IuQYn/4o9yaJZHBWH3baQZ w3SeJaay/MvwKxHkNF8bONDk7fGtmgeF7hyq0Abb8U1MH6RUbCiqtCM1UEu0vNWIb1V9IAGoAYQ3 o5o4kgT+Qw2xooxN2z1m/IFrLo6qm8gKo4D5a77Zx1c5mxo9RldYheXnHdOJ8qZbgY3du/FK4HQX h6/aD/9hMmOklQW52AbKPmFmRgPF8c+RPZLsHy8fr65d9kJi4j0sj353IHZMod/x1j9jxBUukxbz V3kmFQjRxlDIlcOqY6wJAfgrUpK54S+0Hubfa6ZXMicjy5WPMVuZAaqyVa8YJaDcjU3d/rn8Y96W JF/MAKx34bdvGy4In/C1iHQOILhNWNw3r2hC8oUmU/c4qzCUgmfRK/W2THkPB2WpSGbKbmAS1luH Yz5cZYyTEmqwGx2e36GyCpmF/6igrTEFM9rxnQzknm2X3y0/WLLamIJFy0ceF4nk0y0BHSDMLMrm 1bOm+9itwPzkgkc+fPZFacpHnMdGecko9O/tiK16M1kezTCJbdSpJLC72CPqhhVLMQROpk0EobDY hSYeSz2k7johAEsAoG8Le4t/aQ6PV4cxUL/MJflDleCuJYx/Wyu9o0UqvJqUG4moOiHsQcYc35qm 0OMWvW0WL4sTNRWfbyFwG5h/84pzANgCwiBEw/lgtzzA8p8P/Wo6gBgC4iPafe2fwa3FKi8W9Bgv w12oIuBvLDFsapyZ0UU9+hqACCkbooJFKgr1C6q+UhTpSRIPMc6eWZ50rO/8Rd4PQzFqTQtKfC7E UiAyaOIok3EGaV6sLt/tXoiqjee0cVP29SPhebloiWtHhPrPgsvJhj+G3hBZLqqjD5ctH0O0Wtx7 09rtRZfGu5LZ08XMh8BxENnD64by1xrak42lCXJtPZaQk4WvKGfpSmwUKABh0jvcyDQcRH/hLAmn R5hCVU2uDmwzuOsnJSK8U89cUUJ2kURpv9u/UCzHtBwcR1wIx3V0sDgxhAJomZX0Y0xkYO6Uzd9k 7gfU4Eci68wXe1QkaxXBFTuD7dXu61FR6Bid+YYHi5qk6BiHpKfosyz3kVzZFMKK5rOdFCikL19N cFLoVBgwg+YaVUf3CWtDSnDpVdZuWh4WqXlsNiJoGmP4CWbhaXwmvF046FABLLv3jRWhTlsfeDf4 9SJ4FeFCSYwQk3KaaDBLAWVGFw/Q0g0LweEw2qn1KXKSiHWYrWNOzOcVl2fNHIU9uDquh34uDJnS 8GYslg1tr98NcpalIPfgpg6zw/69IKOXBrx8HVqkN6lNa0RvYdTquEY3oLEGxs4xZPU6oWM/Egqd VDvZ0Wg9vPCdeXyHeg+WFEw+hZd04w0+wLWKdDOF09IhfMkAYG28/IoaRFFLJ3YPpNwjFMAH0st5 8f4jCfb3cLBqyCoyELAbo/eD5GJ8cZJZwEU7jz6A0BFwugn0k2701xQYz+Rma2HMKE0moUAu4O7m poXyFjqI6x8YtWu22NRt13uI6H5r4SlexMIaveuv04p7/uofdVDcmdXDbdFDISldaK+jxgxvlmpL BZVQJhoMLS5o7DY8M1lPjzVXwGicN9nHJkz/DOrlxzz60s2oNT1CfSWeaFHhct4F1Wtx8E7hdazB Hmg6LaDhTahGIkypeYZHvkQbB8QuwQvj4KHIJxxqxhlui6LJcKYRT0uOlYNrQn7Nc/0vjLicplp0 Buej9Nw5ubfxeO6XZ3eS7BjtdqbpsuGmYeV3cD2DiAvSsMCQhYctAaCF28rYWUpi1wUpICYN6m/Z 8iRWwIROMVk5m8/8Yv7wHsCPnEmEb4IwFdIFa/QFZDpsIS+WSk8eq6aNTsq+cnM30nOiX3ITBgj2 VAZ+GlwNHzUieDbb6GkIlUPnwPjevbbm2cgR+msW4mNXVrSdoMQT5jx/adjc5798Gelxk81laNO1 QF+CVebCEcbe9giWseWidBkrCLK3qqdhrAVJ8lYW6fc/lY+O3IjNRVxbFaBXComBK59rDC6S/3WT direBeqqGJc3ZtvlMvBqzJj5uAOGksnxuJnBGrOpE+IbiUwo0p3fq6hPUgQ17VBAYC1mLwpP+Hce kdaifkuHtJ8St8dgjtAiMvAmZv6RRByKf5mv+Hp0/tz8G5hZ8hCOsyCiDoTZWPcmvTBxz49q+zEb tYpY1LdJSA1w2nkVbUm8/ecf4GQYUYqzpdEp2VtFxwMyaqHZcXiQxxI8JKdOCU3YeuBeQyzwkYXf FQR4l19XOIXQLEv1xpgJPwvba+o6YYJd/Cka38/BL2dQWOIV4vRWZWT8hiiCGw8gStoJz0sICz8t kO5ZUlIrpCecdW5ocufG6ak7ne+BG9jYQ0nfbRpO4eaT9UKCMqQzML2rtrKmWm+/6dh4B5jBB6zV 4mblsKtkq4XP9imaaFxTLdkqXl8v+4Z9O1FpuHrHfbXFn/nrFKnQuqunQLmEgCYB4xdX2VEJPrdw yGQ0Jn1qEZNqhxh7dsJFdm5rWAPB0fX545CCxwDW59lmwoOWYv07CIRmtAqFiO26r+4dMXVoz02L dSrdti06Rn1kvbQaoZNaqWMpzewm6BLHB9L8Wr4pBtO1GG+3xMGT3u0MjfFTfhYWzMkUOEAtgk7s 35CNBquFX3vScharPSUYpzyO8rsv1muQGdjJoPRhup7cG2zJV1BMyf1cmCBNTKE70Y6HTaNPsrLb S9J38gU1d9nqq2tmii3prcBOn6Rvf++9fZVKV9UwUxKSKiU7U1UCLnuNm+gwBzICzjltmlu/kqTg 8T8sTtMZZdAXrSgsd9O2YZGDDtLdacuFs7pzlJ+kUT6QPn6IcC3+xUQagB0XiltdZyXA7wnvfO4u ICRybXJvJKaGSruTxhsSe3DSBQh6WmK3EwmO8RcLRMmQOJLbLR8+LUVgyjg+OlhNXzwwnqwcRCov 4phqnWok0vtXeh8PT4NGUbpceEbWuuJdsZPUUV5RjawNP53lVHOSwG14195ckFWMEC/zsG2fMAEc hLCwPqSPzht18zWLKCaasfoDkmBF67nPQ6HNUmg8I8aXYmcKSNVuwYzBrLA3NTMbo1mz7xOSu7QD wQ1XCD+m12aigD3Zg4zrgxf31mzWgwfuR/LKsYlT/2ukiQm1I2+XV6fC3ypZR2MNBHpPBeLUVSuB OzpkDC2Vv1E+UdQ79ggtAvemyochjwgW+6VdXTelAmrx2vAUaIfNXzaJTJt4JVSMgZ8+I/0Ho2Hz 3TKUH/DU6Hmtbw5GD+COYazRDVu+YcAEHzlmkQJcWh2PDMkMdSTsb7ui96aV1lo54SLWy6hs3E1p a3LJDwSfoSSK0YU8lUk/PBMkDVKoT9QUvbEB1Fav19gMxgCQLOB0p3ArExGBKQb3xQxcRF2k3zKr gECa7Ja6OmTcFwLugVb4KvUv2z4IMeNc/ZtFAjajtVZWLXOI4ELG4SQyfGqWPsWcu6PM8U+Q84NL +nowp+ALrtk7+DXD4A97S3+C2v9xVoJdUNWR84qs6hYYsIygJBShSHTZDypdCrNAY9RfHgC8gDQg dw7WvApC2+ykqlEYI8xvrkHkQ5aRg6zSq/4GmgWZIRWhTkNgJ/CtRDumvfL8tAG66Z7zSGJNqf0S sgT8bzuKHIzjeOnQJ0nDl/lefs0XUcYxr9ZycVFjgLOEngsMtViHMrzZgxXR9AiTqM9yxZ0q9Lc2 IFwvrowCHWPPptqAltmfwi++6j1IiYqUnpGzX/QKnh5L9JGCDZaUHbFwovX8OglYI8iRm2oJIV8+ w53Oj4+xiSyVNVK6+1uK7LFB6s/59AktF1QxxMxddZurI+a+bEpNX9W7sfndst2iyMJzwcbUWT/u Hi6C6oPiRNXm3hYqGWGnWyfARdxeRnE5J9m9m2fwg7QxPvrTnAk0CDGTCmIZTs2GekrQ2WuOlf1/ L1OmvW0TD9Si5Qn/TX6oB905YaCkVJzcTS54pnf3AeqBuVEVBe8FvlJJwEv8hKLX8HJ2xRbEXjRo 4Ng7Upr2bJPG/SXtpwCbHO7iPqr5OwyHZtUgt+Fw/0DUIPjC2DKNkmiUOOzwsF0YHNpOqFwScuKr N2LU6eXWPejgNO4yIF2w8fF2CugjKoDeIGySQXcwK9FsM5hxZ8yVyMNIk98Jhrhlprg39pxh8Lxf QUE4AJ9/3ZUwxBHlMVMHfw+pw2ya0ntIauzyrhEnffD4uEV3vhuONnZEG8XXfe08SVw4aQs4b13h NFHbUJItj3CTFyfMVG/9mym8w590l76Feyz6x8qEWBolZsCqmKaT9T0rvnjdijCUvbqkgsI8tP68 JPwv54+Zjp1OIVKHT5dW0KS29fjoiUMP3n75sWUtWzBcmbEY1ATU2XOB3wvv935saUZeWbUDUI93 7AMd6bHBS74qVP9rSLzGSWOESw6HJb+FEbcx8/0juAgBIPFffozdfkDrydYq6EK9S0+lgrCzu0Vi KuxQ226jIl9bC22pRddn6Y+v8EH2sbjB4ioYkWtwtSaZBSQ5w8wbc7SOZ4fcftSaFVyf9H2/HVq8 YmiRcHo1sBW7KTr9fFMlqOmdpPfBjvB5cBvaNKxcUSR7iXzYmYSyulvSYylthBNITTdmD/O+wREK N2rZt0Mu9cuo0ZE8EQFxdeqm3ghDLj7so7x4xdHSJ0nUn3CuO7h9ebHUeOymm+UHUCIS1Y//+2p6 ylFrt4HP9wCnHHvRUKFiwfTDd3yLsXH9UVoyxBPR/aKFw8RLpFZeLXvzTLlu7NtJJK88AldP8mF6 PUIW85stpJ94cBljEstOglYMwSLHGYveX/GyaHM/7UO/Pcy3sVb08ELqUnyzJVaA3LmmRQCpsYXP HzdVlP5xMHco0gHDdAQbkfch6/MoRk5n3a4m19JfE8uyAcNeD97QLMu4HpFcDaqhvAC/w5A6xl2D Hn2uwNzTz0E/MVBjo+4I5v2QJFzVFSkefKtJiz1NUHEKwEDu6fxUfCpybQUMQivpg9hPPIw/XX/B zxA9Z5hdtdehspw2ovO+6kXJwdJd/6urOKeGpiINz0/QFiTGv5XHoP7QlD4ankSxzChjMeUgNY6p u2UiLgg3f3DYWUX14Sj4ejfOhWsCxbNSVPGZcNI+NIMo4YyRZaUs4hakUm7IkSzhal38/zXpxGrb /jZ8DrSKL0EONe//sZhOut424R5TKSAXLrulMCApE7x3gN8wRT8NhLHGF3i7tUQkalHtPglzFd8y HGys55Bt5bpBBJfP/RAUnvL2ZYKwEzWcpPOdgnDL0ZXDMFaZd5z9LfmiLkPETN1Ql/xfJlpB7wm9 9Z1EqsIBvwhB25jG9T7DFXLhlrJTrD134ExoArwGua5AQiJFyhySH1O1u6ZbpJfgw9p1iv5Qjk6Z RYoqnne9kFhHyP7/Aorx0lHkwvHBFpYY0/cpny3fkZr9U5OCV5k38kx46NNTfgijyfjesJPESVJv dH2dBCNBUoGQSg0ngy0rg2B7+esGfspDQ0LHsSQ+v0i+MNXNrgmYxI1QhYYAOS7aL8+/9LlbgQ29 hsZfhJR2umHysypKqfZyhC8vG39jOwr7Q8vHrgPkieiY5Nja+13vXnmppSM03L1L3rlC1uWSnGN1 vqpiFap5vyFZWnhrLOeBCilR2bjVGXDHaY9pmvTV00hoT2AKg+2jtV/9e15VlZrl+/dmy5EBDtWm 1npbajuwivjsScKngya0FxeLL1XOUtctE9o8LrRhezuplysQJehlVLTTZBZxaY580e1n7Jmduhw9 snIP8ZWgyRUCBsk/76xnDZf0clV10dsQb2r92FK/ldmLx2nhexD0iteekRsVXDDm5hHwzrp4Ksij 8tFwwB36t6luKRwlKmnknSOazLy/c+pN5I6DZFZrv/dmDd1OaWBgB8ZNOdCP2VznxqEoXCCvLGzL FqLcaj7MF9viWIZ9EHDKexGG901D2X0LHYPKA3gwpOKk7oymNdCuUNfrQXUE8Z10Hnvq4urOwyJX 3uX3qdGPSieEtZ0Pbi3WCYh4jbP/4/I9KVRO2ndQlF49c7PEa1XPDbUlPWbIQaDFAsgZB8xY45L7 +agevoIBb6pGanLs7+Sn6uVbCpgv32DsC/wFw7KL76Yyt+nf0IWiCz89GsYlztQlK3tWRGDp5bGX 0Rv+9kfueBk/dGPqSLjnnIGYgmHUscUAusY/OGBkf1vLcFqNjH8bjw+pICbt2At5RiTkXIScU95j cLoSIpdULJ5mNZB+YXEm3AaXsVutJgkmfyBR204ID1xpkiofyP0aux/UMsy2xc0SPHo2EjKVZxof sacGGf8OYmnOdLxPTyijBkHwdDeMRTxzo9gpVEjU8t1lUyscd2OBMdMuIvZnFtvooTzeuyDW9/ya 7JsOxnr9Fw1FfjY1JoNXyl+XFCY3OOAd+n1I/Q5nWIm1oPj2m6B/c9cQhEt4lL096dPwZ5aN9cBw urVfSvUl2ZFiTwi1K69ky0QS82Tjw3kqmMKcDZJ2wLbGVPD8BQkUMqjMV5X6Kx+9n8uh/Yw/BwDj IZV/y9zSWKXlzu+s535bxmjRLpgEG1YWRPb+gpn14/vmQ4Q/t/bM8a600UkZ8kNwtSxIWNwEzRnR lKyoTSi4iO8qkg1k5hLvkJSkR+h992dwUfzblZkcWh/pV2Wvpo9KVEG1gduuzVrGzDIHJmbXUX8R E0qGCYh2BrHgruvxCgbREFuHr9R76ZJAivvUAZBrdigWJxEjewWo4vv0U1FAr8mANRc0t/9s+k1k CArhDoqyifDhtQx43qoCT0lnDxYjti3fg0THMPw/urnuyIhsNuELpu8yejALvAbi+s2J2AW7y+xg BDk4qiheuKdcuk9F2XMbaOaLmv7RNvH5lnSzg4A6xckF/bV/F/OSjvh589/t6gyxYbMno9ovwcT0 cj4CttFGkk3hHTKLsKFG8/mG/I8UatvKWAraOx0FWvjsNXNFoCvwVK7kD+usJu6wXevfdEQOBWlk gbE/pw86mvoMkkLP8sJU2NB5yl2xYQI5V9KVWVm77r9rUfpWrFRlnXm99lbZNmR3J8lG81sf5Rtj ruik0oUQUQXhyS8jP2PUCH7scv0UYOunZAArgRpu5snHZ9Mns3umECqKDuBQdTX/NHW2kpY7i/2d Y2I41ZhP/9as5ojauoFxhR82J5beKS4JxmYaU5uDKQFRWi8ltdQLtg9Ion3Gi4S7sXOkOmMGod2y yfdpM3OqS9ikaAKDMbNXxP2a/VxAo+/UKOr6503oSExYoHFOa5j8nMNJV2aBiuXVbO42YmLelTNv AnYQzN7vAoGMGo6rznuw+Xw= `protect end_protected

bsd-2-clause

248f247d3b878d148bc1e9b03f527a5e

0.940526

1.844634

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_status_flags_as.vhd

2

20,484

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block j3zaIMoArA6XWIHFomLzKtuq+Rb2F+tSmSFNGOdieWSUzjbLz+u6uPRcJXllL3MZUcvj/uKaOaj9 u0SOi73LHg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block g7IZF/95wRkFGSInsPOZyO5sMJ+VrRPeMk1Blgwfu4W37IyfwU0wC36/2/yub4KiFF/mdlx0TSKw EP08DLOpASSW8nblpF3eaw5WYMK2tUbVB83MbVhLDWJels5RU8ZtvQfpnN0wg00PGoyqKcQg7dn/ S7LnJCwhTtwOdibkn5s= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block xmiZu2CEeySwoJ3exH5beHvjFkdMUHC19GZhVMYdsBJyF38vUIt0PBnEtKgKuBh5L+hXPBv2Bcn1 45xYL3IW0hXv958NMBfrydbbKdc2V5H+Ip2BMijbMmj4f0PSSHCW3t0h2wzGdS0vSoSjMFn3SO/c rikEVE2WW4wfYs7cMlqZ/goswvusBIMezls8gbIbmNnpIDHO0aO/G/ocW8F3kp6/KXOfPXb2820V XypCJJs3iOV3sTAND1i1KRya1mele0sf2kv12wl7H1TvodOCeTJifnRqXa/55LwWMyY4NidqG0PF KngAInxyZiv0msQB1uX2uSZkkKVIEXcihXizdQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Oah7MQQWFuso1UfVI6+06ZBzaeEbWnOVzKjCf90BmtDRoim1EcmTxmf6hL8yEVrH9aAwxN9vmIuP F62f8Bpc87xfwvhNIlkJ8s4A3iSTXSE/1VZCnHsWySS6x4MoRD+OzKSLhjeKseLd4u8saYd27BJf pEKEznWpli0c+mVIZHQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Sw7LWGzZeGjtXHY0gWzJ1mNcwX4GVGKCG+T+cIhzI1JlvGataZiKJyIuPKjVEIdeL9nYSKlx5wsJ i2DKKxZbU/fxwcsOz/E3bwzmqQvxJi9hcQKnr8RsUuvalRtHMEAxzbxzTybENpYFBMHSozYUbdKw DlTn8aZGPWxK0551Cgh8ArsXmMslGjui+tBH40wHVxyj5AgeeWlOTKlmTWBsOgrv/NZs4d6sWOqP TTbQdeJfbAc58yTmfXvyOzWwnI4yyRyXzgDKdoIl2Dpm1rxTn5wb/KBu/pGkHNK6uCI2CWEsmPF4 LN0B3nuSzZt7dZQ8UrbH2+hv43qyDw3cqqQsJA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13424) `protect data_block zlDtPbjsW8z3LlFkU6lypKe10hRjpTnxsOYfxmOk8oqaX8MMtzWBLLgZuHe8ICCaPrTFOoiPWaOL vffcQ6GzaS8XqSNfx/AKWlF+JwOkx8ATXtLHIWMY6q46/WRfu7cLIMB0Ew/MSn26K3Hd2pcGsSdj sMRl7zyGG3+oeSwx9uM4OFmvpC0/OvBCqPFER+41dApe87hRk6atBP2b0a4WqojqQvQ54CtoDukZ gJGCIhxJX3PsMuBMX7ilefaNjtFvU2HLHj7xbu8qyHfeic6AJLY5sx3H3mnLU13UvjsvGJkTOiCF GDln/3CGDiWUrYIpqA/S4lz2feWzGmBldSO74Ox0LZMdLzgMVD/7Tu+ggVffLQHmxxX/RhU+RupA vhNK/qemVkG6dZqXqw7GOadvBIlEHx7GDh577LyURs2HOzx6CzGBILmSxaB+IgaUGbHdqMEkCvKb CBuZjSOsWQLa3uoEQajTiieftTeQl/Ciu9j6OciKeX5fnoIfr2ZqFE3J0tLdUzDZkMh/GEewVkib 7z9lwOYjX0sF1HBOjO+j1JZ/NsL1cdP3q8xm3jyyf3wLkCvx523rhozFHiDHsugKf8bCLoFhJa6M ow/QvT2MR+wTIts+4MyfdCNx6hXgFJ4KiY0fDivwQWgsMowGuthmDXj/lfQ20jwY8TkZIoljnCSd 53myxYOqzi+aSYvoiC0wY42VPpwTOF3lKnsgeTSbFZmc8AF8YGl1aVXS5wXkjNVxZ0yQAQBDqi/m hfno0lpDlIwYqn5MYq18wEszXHzZjzsKiNdV7ssKmLM6eydUNgOvY6o1ViTIAuYKDui2Ws8+hNQ5 ebZ27gYyRouu6b/rGUCJPoF5EW+9CPTLkKJPbruXlHY3j/tEtXa40xd2HQpnB+xb5H3Uf7195wtT xrF0Dvv0Jp/P+VqrNR4ELn2V8cJdLNgFaJsHMA+IwbkLYNRlxbga+XqM2h1XrJbk3F84EMRnFOQm LKi0wBPW7Az3msw9w9I7ZYVR7dztlhm5R+JS190gCMPlae/KTOGk/UPVsPwubi+af92SIZgkt0Lm MWy7Kspn6b81PDI4eFAhnv39A42EPcuyGAQCqo1Sgbx3kOFZrnkU6zrqP8hmecYioE+SwGi8yaja 1+87vbFbLjSJI0j/O9Ch2W+QVt03/NnVjG0SB5PnCYiafmbu3DKhtH2w7DTH6zYdfy5O4Tat14St H28KKwNyep3YtMEmSBmkxUAYvUkAQHRytf2ASxR85DkQA+ilL+ps9RHoHgDHfVzW7snXVCj7kj+P 1WziNjJORZWc9SBUVRn3ppdIfGKS3eHxjyCBSpVvdpgRqC7lvgv7G0ocdbwhbiGuBWwgi7ROJwud +VhnNbmxiOmIx8PthXL4ABbpva+xlFgAviq0+ACq8Wb/Smqox7gXJQbHCo/IJWnBLctM5RE7jrn3 2jwtEOc7XhjfhYnbCPlGLNq8PAt6zXWFM91zjnqDvU778O489MU4X1e8/Lk8zJQ84reiIHsW+9pl EQgckHPKvKY+jbxIPreE8oDbvr1vZQ69yxvwwaGkXx3xXt/rrL74n2CfuNv3BFhqHwlfnihre33G eVxLcMIzOiYRyIlXN7WfjF0I0lWZbJUBTCP3IkkM1w6rDyhKWZWQnWZg0syeMbNO2hXeZycjZ4Fx yxasL0RkBRuQutfRPMLcl6nPdFMiIdMMuTAvwzOnFakLK+Jq6n49JIg7I68wX2iBOtO7AmTjZQAO 3sKYoA2mnMZI4fuJM7lQsLMxt+YJQ5YWTe11GkkSUEvaeDtc3jvLLzcnA+5Qy66Dva1pVpGN/Za6 pzfEkI8wXd2TpF4w0edc/R0ExYT8gNAYLa3h6KLwYo/QWODMUbSt60VqedowvhyVfLH1dHGFM31j 5XtNPjcTbFFIuaSIJD+xxBuyWNUFG3lOj8gYak3oPtmziwFbqPsnpsuG8UF1ND8e+7ECcyBunLrT NUM6gqZzj/biwosHT4zGjrynk7lMliey3T38p8QgBGXmD0qfGDv8gymEVk5r/fwmFOCNWLFqlz4Y W0Tu+5JP2Y6N+jVBiHdWuHuXnbeGWLeItdGQFDqnub8SgyNSrVY1IheMexavqGiFXXyWF87NldfB NB4g2MvmQ9KE5gtO2XSbweKXC51HSaAwtnZF0Ieo10eErekGjJ/chsURl3glRkcy6k+VvHTSLLqX IOmrNUJYJ5tGPeVwfc1Tfz45FOR97y5BUrRUgkP9ffoUcKkfOqPhnpZgjQlvD2yxczB4aj+25Un8 b0CbNZhxFLzHwG3nKJwuYs1PlRq+/QEdD7qhNPZ/fwoFuyjUsX4vIURNZF5JKAh9MBK46KfmrnOJ obOX4JK7buhW/GMRRIJQV3wEzKYrFBmEneqeFc+8XTMc88YuIm+on2TpJdqrhT9E6RTu39m0GJtc /zdnbisOSFolzsEf+2Y6K6x4knAGrhQeJGF+aPxgcpM6EmmD+hwif4XipC1Yk1YXzg8joe8OTjYx f4WIoWVGmXHEPVDzordm+zEt2SMpY4y4TUjZqAAVU3WaJDKprvDwJ1l8Nm75HxjLC9PmAv9BoOTG 8y0mOEocMZ1Q1H5w4PRZScOJ4KgtANRJujqieniti91xinmzS95fVMMvZlXJXEeOaXXyTor/wOIY H1cJWg3Tq4YmH7Tma8SxAj8DmzfkcWnzOgLPbhcRM/WcROpaOsixnJ4pZEU4J4I1lVkXlkMpoVdk OtC7sowCXAcj0d2kf3BoQH1yx2Wnr/9Z01J0x+s6iK5kcpiOnwnm93OjW8EsaJBYCEY+tdJulnxt Yt5XJ8HhaY8PgI2gYopTVUYKQHh3RUkl0rYv3zG4rL9GS/ddU4gbXe5c+CGRRXSMxRHjyy7B6Rjj cbgWY4wwtMeL7yAbE06wjuO0W1iGKjWJ2l8Zm+fDeMA9t1C/J/3bTJ9++4qN//Br/+709LSC4r3n ldVexwy3X5NP+n/NskBnue4Vhtn+zdVX4hSnC+ZbR/6Rca9nwt7lCc4JFqWtyqqwojXxkyD7fj/C 1MsrGxtDJQIxGTEP6DYXeKC9g9W6A8aJpigsZhk1R4nMSAV3nlwpXIhVYTea8QUN1TvrIfGPzc6s 2qHmvjGm0rDeIaeMDxPsR9YBQXJLwVwsFRp4QJjQHUNn7zHsDdqLmxQDemz1iJXLqk7CGz9TVPpc b71fQaCyHZmacbHvo8sD2+iL11RfStZO1+/mrZ0N+3bGW/VkhaSfgmVGApBxOVWA28lhe0Jmf4FH 6eLEE64NV1pMbZp20Va5LWpYWFqOOkGJyfJ7Rr+UlYO2zK2isWaDt9iQVP2UrNui5f6jdDpSw9xc 3FYBNL+k4b3TzBf2Dfzb1wJxgGuCZW1pENt9IqNmapLchDbe20vNEpXIf14fUXzTXU29tVKl2jN9 7kQddrMEMgKvkL0YzJg50Bf+aUYpvXEMS2LooSm9fwny4czA4cYWfbOLCZebp3eNSQ41hwNK35qN dCklPO2IVtXXrgT22ayTJhYuKAUg3wGT/5F4rxMdnv/OxOYJiGVJh+fqAjYLx1lywboF9u+yWlHr Pt1MVKVi+b2DIKSui6L91YGLN3GCbHD46a2hZ/rpxNU8D6h71hXMqioLwLregVgyEMEsd/IueQNk NZrkL2+F2OnQWCQKeP1uYhFsQemL8kx843NYLxNoM+aW9W26CFbpud16seYbjAScEgJRM2hAA05e Hwer9oLfgnYfWeApyC0PgC3wJhbg7hkUO+Z8opC/R1juUJowLk8GNeDuW0DIr6ZQvxuK8Bg98buG FuHAIxJbaWQZYB07KMAaKXoqMPBwMcjkjeBw+dPOEeB+Jz2OQ5eCDdp9WHHB3PBb+54QDr6Yn8bA Yc4WqIj7KUCU6c2NLVy7iN6nrFtmOud75EKX4cURvae8ZooGhKGRVRu11FlSZX0+EPn6/dw0P4YN jddj6++MC6oT1dTb5I+kJDkqW/UFIs4O6Y/s/AJ0h+aOle90MK01OgWnZU6pJ820hxcN/Omr4Ffo kqoUGj1y3it2h3vfOoqzQwM8P4W6SyHuKOoZMEgPlVUOkNszJo+xR7lj2Owm26qOv/TZwO2YqwfD esTpKElrnIulsqn7xkGKhuGT9vJXhYxoaP4gLBntBRueE6/yEd7IJtFKEOQS24mA0n412HtKni/1 b8yrnOhPO4+iQqtnvjt4u1Q1zJbnc4kTivftRJE3xeqJE/o9KFj1q48dgQhCGLmSqP6ZuifVEDrU zB3nUzZiBfBW4qvFFe1pE8QZ3lzU5RXQ8N+jH+GZ0+UHV4mAc3o606Jjodw7NgeE63WpaBbrXMuc xUdhWfMcTxGTRifzRY4huQMtKMajEuNPGa50bhfyX30g6Aj8lyza5IGBc67RGyrJWgtrorHQz/z4 VhJCd1ZL76QMK1GcfDUYKgXC1Ab6tdaPkaZC1KPUS7evSKdVJz3PiIh99iP7p1EmShIt3C3DuC46 Ps7JnlAmhHq0JcuvjKmhBHwBn47jxWafG2hnk79Bl5SbGdwoS75S1XSe7nf01m7KuzlbtKPj8ugP GYo9t9wkXGYK4FGt3SdK8tESOErxzb9v0m2HpsbnStMGzlIPG+WODajGEsg0wytRhNfCIBgB1xx3 58/PDeLuwhEXeMWRqLDZfg/TXC29htVqRADADlvsDoIXjQ8eotu2L2DzoOqEGa5CiE7CnwhzTtm0 7dB2lgfBIpQIsmship18PJcM8pW3rKuwKxEt2GyCznNBV9W/HsiqjmokAV2mUOFra1V90rvCeTrU ZRUCubxxEoc/ZlzYRmwP8szm23gPyWrxkpJwIq3PAxMGQxpmEkBV1Buz5l+LxiPuYibviD8LPrKe og2zEoqUgzCglRc9PVbds/DOFnWluRKAlnmV5LTB7riA7ayptZn8e+DNuwAmOzzOZMifiOX/iK81 7eFrZZoFK08O5lmQLXLK9pPf8jLgdmsrDPDnFwTpJGMy+hIbsMhSeW3BxaL3y80RYvNoerNC6Ojw K/5C7+wZzv1/ngd5slJT7vJfQT75TJT1GZtcA0COtZbLOnKFnfOwugkdwcyWOrlDdjzNdbUk4yZa 8myPwiFZiM6sVOlCdtXj9cr6Vk+HtZdgKR8Q3NopybzGffvi9txKXg44QSSjMXY5pqf5CKuvn8lB rvpS6Bvdu0bMn6/ucTWvpnSRpYpO97XuTjlzXWsxk9mpFSb0jdCt8TzS2CB0fMdEX8Dtpnv5HNAZ CuLKnb2S3fny4wL+L9vbFS+863Z04WWZwfE8FdNJNj0vc9LBkmqlSt39GwB3dbBzvc7mRg2/DPcZ KNwhXxEdJXCNcRrP0+ffOhXAiI1/nR2FZCPDEVCX+Iy9CqJr+JsoQvmHfcS0M4goycTJk59t/2US lLcPdDtb9zEveggi9W2x5z73qKVlit5GtZ41ZgJD3/XxFNk6JdncWm6jQv9Ingp2bMbBbqsnjh9z 8zjDrVAOsXzSwxr7el54/CK5+dd3Qhm9HjE0Upca4WhJ3oxH3YOihJro+voHAd8b0rpW3ub3C+sr CZyXKvJfQwWN+3QoOo2FcyMq1G7C1Fxu7Bva/xskU8b5pUnU0Rs28MZ5h+BHPeDgcGh52r5ny0Id k9fy/d1SGCvU/FrlUhGfKh5Ur8TQPqHxnR4HqHPbfFvWHCt5UsH0HpIodzEmSVPApdjjFmBgcn+k OixYXbgFKrHSXFuwcA4X+vz9Y6Z2b9ZxxwSlJTjpkT4hed7/6CgIf4acYi0ubcJsNdq9FAAmfu7H h2mW//uCjX5gK3S9lPOjd8ksJOa+RarpbJDfIo8hBX1DksNmP99W9u8jz4Hkx8+M3bbO0wt4lJVd RKiuszmQhLKi4AOQHV0rP4KCGNJAE9GwJ0WfTincGDD34hmr4KIAF0BrlvFOV60aUCKAU78XXKwt yE9YZdf7gkToU2cXStilQkyAs6LSso0/4Kp7z1/CoVPY3Kh2FvfbgpijfH50nQp2leuhGhe0AAYA oGcuztBaJ3jTqTvNM1St3e1a2W2B3XClT+ipTY2UN4xutwngsaIR4U6YvWCd2o6ANj2jJqxob5Xs /6Tx++S9stq0P6wYqTRxCgd2/fLtKVNDkV0YuJh1Xqn6JNfQZsnOoW3ug4V7VHo+mxO96IFQ8VLf cz+9HjjYr0ySR19C8CVCeAGLojION2dAW7oGOQW4oa8zzMDeBjZcn05oGrSjfl/qNgMAcoCXQv+M Jv/4oAJWKKeCf2pnVh1xL9BDXX8u3XQHL+kzeUS6c5J+lp4oRjE3ypB4+IjjYyTRMh/x47DtJqJr l2nCW5q+GEbFSO5On40hXNpFtxXT4+il3QMfci7UjaI2/VB2kFQ+fx75sOKbM2AhwVnaloR/kfjW 8LK6zIvepMFjjbqX2kblWU7mC3sK8Le8/QPlkaeXoh+mi7FQq5/Og22XxQD4QUX++9sY2Lo2uxr0 dKvdcJDIZAJfThg96O/KP/FcQWlnZNvmvwjfszOKjD+S6Qj29GQCP6yotuF4zUIIc8MogwiuHPVC tWISumhcVQDLNlOVfpfS0XLv3qa+v2oYPM04mxitEZZC7Zgnk5kJro5pG8aa2Z32Hd3olAPBOioz JWDc/rmtu9UJulFj6Q1I+IBDSusDEwCtxqKZkTMMFQDGfiN1QkeQs4lXzCoJnqTcnKFWJ2z5Fmev cs1gcp2vSk3E5vdr/+RvO5Yj7lyiJvgLvBQ9YG4qBvsiOkDXA5xFQMCIfG79wuvoowU4neIKHh7Q BTUg068oSdkenJ0urfyA0x3XwDiyFsJYGtcwtSU5qN2nco4BuwYTlAmHQaZ5z877AUyesvVlds3/ 8HEWzauCjGKKo6bIjg4Roh2pmdK/bHEdcVD3xHhJW9XTmPFuQGGXk2gNr8WJIpSSzGeb6xpzi79w QPEZehbUvA54qHXEFU8A2s+dlMvcPYelDwdcZ/fToWXTPiHAFBYtknym2Zs1dNIpQsNTXTyaTUQM MTqnXCCg/U4bn53Yd/zI8+GkGbWNX12qS2/fzEjNB/QU207pgl8xz66FRoXcR327l2PBKJWQX832 Odlez9Up9BchnquBruYXQ2tdK6abznc3e7YqJSlMnYcwsExuEN3uMQyIvwlnGMf9qyRzLe/5hXH8 q6aiSNrHe4C3VaeSPOk+BOyF+XMBJPedY5LysBeM47RZ93q19FpakNN7Gr6gGnw8zDG18X87zWMp 8rxDSyW2GTiDRQVC+xJaTw1Q12joVoN6Wqn5Hewp5KqeX+Ad3TRxR0b1bSgSF7Aq8H13XJwOaC0e btP2/D61ibfzmbEB49JWLZYWkd/QUNLRuQGQd0CLzH9EWCjdhmGbOTmpDFv4JjUCvoeEgzgVv/nO w/xc7n6wDSQCwfFN8n6TODCWNiMiYoWcAeCfur2P5bvFg03at81RyY65/JlQBCvDElm125toRlnr GAa+sKKssDhmRbMXXUia6GHS4INigS8vZBfRAJODB/7owJWBxpyOs+U+6JjY07c5ZRlEz3O/Om0C 7xcXluYEpfJUuRmf/F5NcoSO4L/Y9hF63uuBpbwLr/MeUocu/IcvdYq6bCEe6Ie+k/kvB/Q6uC3+ 7ATMcJ2de/6djZuwj5zUFshthmFQqGiX3aVSBE0G+SVCJusVHf5uF46TA+XuZnMubVkBfdujeTnk UtY72ckUebLTpVRuuGisYknZr5rNw8HkVNNJHUDw2VIMyueVHVZ5yhtzl2ktfmO9lMK7xQ+nM9Sy W+QuHgT6RRNwP6+6BULSLKCVIoNoTLO4JYK3cq8llFfVSOz8KOrdMm4RlQAEQULZCeaT+xiukOB5 8CSOllx7109BSwN1QLYgTl+vf4KIEhfwzP/z9RqZfQa+g0uSC1tQNkxG5rtXUiZXtxUqarEagC6u vKcj+NCeuBgCfuZ47kvNA4YQpdOkLpTpLhKgjZGIRo3Qx1Z8aJkIjOExxwWMiIep4rZAXtAdbVdH wh8Lr3FABZ9/0OIyDii+WtsjGUu3yDWuWC1G4mvVDJaLd+lb1dy5tcC6R2tNwj2rNztKhPeCQ2Hz /Vbkw+rskDeeqcKsyhSZ+snm3g/scVQn8iU2VnNbvdM86Tn12qhHvMJOepoQg2jPB4cE40JYnjQW wjNCcwJR1QDc37vyIxs3JbQRtHkjW+PfEgzYTVXlEtlWEpprXaXd9PoFJDS4zbfzSwVDZOHGiRjD vlob03ArCf/C1lnTowSiNIm5449yy0eP1ByM4+EDxxf03580KvVKU6ETOrgLpesmLQjq/Ecy0zlL iGs1uOnBGKF2BWrQsIP5EmprOLJFK3AH668BkE8yBsMHaSSGGGYwObH7STpiMsKDlxCWbob3QFAN wNvwiPMQbnrfUl1cWHExq68/nYr48kdz0dXNEkK+SyvMa7cTtlG65T4tBhQ0EXOEEXU2D3G6FfMv QSyDNMs0kyFLOjr8xuRpX8Re/Nm8NMPaLJvf/GObkNnTlKDWgpba/9KUD1650hDWYTH0Aj3ygFoG dPVgafeB6QAtrPvXkv3ympd8x89GBsFg08U7O339My365RJggEKwCIFUBrN4N8jnHBMqk3TV5vjQ QP1lfJn6GFaQpBM7EyAqdj0l5+rsLtcOcC4HrQO6soUYxQ1GBOLI1DChrllxgTDzI+VnAv4TChaU PwuyyZpeUd19gQIrQC2YnP9+b4rWaRzftqq/vCjytAyPF/rjPFDwhIKjpd/cmyp0S8FkkAOYSN1f 7wMucqt/mf4ISWMLwpS8bBVXJmZ5lHnxSiz2QlLgisTF/3nTx2rN9wWvcYNb+l2U81d1HUkLfAEk kqQmt/Yagmq9DSRabpyR1zjoWtQnZoaf1XYX7cbElO+EQtfid7m78FHoE2smIQTWwjhKXwitHtYX tRYX58UkI7DUpI2tEe/rGjlQnSQW+4o3zviqn5Wq9liaHoO/Y9nmAqmD5Dx8O9tWSL5WnxKCO5k6 iLadYB8dO1UMUN9B5GgtW5av0YbVkaEFOH3hqrjh/8gjWcrCHmxRkKJCK+a5pOvkHTtQe2ACkIlJ l7rjAhXXPMZPGgnSjGv5YtWi7W8L7fkX+mtt6evo/Q5ZUXLNcJTbu68gcGf05vgbkiBOXmsC5U3Z zJCyRrkQnv3Q1QByH54miet1kvnEW5m07yguw9h5/t96sp9x8M2e877Q4OuE+AChrxhv3+KfWrYT fUMKnD5nRTErCKXKtfrVq9pdfXtPQkcQPzMNc3VvmsUbuNySZ4gjKdlQEfCANpPirn7S/WcKKUoS 7llsrZ/ePj96oxeR2ShARDzkw1wRHvCllT/5K1Buuk1tdSxOSGQpkfqr6jonluj4rtj4BPHBlbIi cn5jdhF79kutb+XX08mmcVsRtvFKb3RJj17MRliiaUq9/lL5YqIfqEpcn6aSvwAI/6tUb1ZfKgJ3 Rw1UQl4xY9HD/OkQV511kewZnvT+kmJpG42E4cBm19mPjRRvaopaZ7+mMeRZbm4GR96DV2XsOJXF TAH5MI+u4Vcw1xNNwmHMixYXOpexlgo4dS5nfJ75aCjt48RDEIZiCu5+9iS7HZ612QEcVrUoazO5 hD0fERTjraMJMVClka5LxBIT9g6/6RclcRvhr4qwuAXVomkoXsmxEDeVvvVKra/yXL2yWVqSs3N/ wqYmz2x4nWP65ss8Xh/aD+HMv9sNpuqNUmHsUaBTjf826K33GG9Vo3ZsZ+w5UGQxG7360wFc4Jz5 lVco2zanMzl17Ca+jC9yV+AbBQiKSQ8trwDO+7zJDs7jh+ptMtVUutWF2ZswuRboTqTcopcoprLa kJCTP3Tzt42CKYCWMboUCEh93qZrOzRlEHEfEEq1v/0+30p5TW4dmsVk7y6JmhrTjiNiU3tyqWFJ WEIbYnBpWpCETZMfqaH9q9bsTcF30RhICGAiuRHVvpjXTsmekJQYjh6gG79D4raGjVQpCkm9kYq+ ell3P7F8zxY3PSSmxCzijJSDeHauhOJuvP8bTwItG33I3Z3L+KLaSG8r311yKbCDXVbE77qVsegL M9SqjpYVbUeJIMqKmypVaHL1SBED43ziC0gSP6UhfJfxqle0FUkxrYvzf516pdo1HjIQ/4aNeEgz A0asPDI/eg4f/2OJCi6ACg/wCDBSWW2x9nNtOq7PgtXMxCHUjvp5HZ1a4u5Ab8+6lgAKde81BPLm bNV5hvePK/BKfcPVjNhDh5BQhb+6eAJgzkjlxudf5Xa74X+mbdpmTe3OYKtlkxITxEnqgqbTce7b Lk9711BZOHVviU8owJu3oXJdxmjh3wl1J4s/dBHhJsVKZX+DKMEonJ1oZUhtNCywqzGnQa89jRnV QpuMj9CFoGvVpLdc7ztBgtwsP2bnj95aBUlvLLV0KoO3glM1Egt4ZG8r1bKQlgWIRpEUywpXre7f 36NWkp548cFGlO16Sx0fWzy/c4Q1pBafXL4dr12Iaik0uGAef+yYlT/zOzbtXH/YISXre/DuI3Xy Ulb8BVF9lvGQw5e8RQLMNIyk3LcJ2bYiPejTHGOoZA25JTsoxSdfvdHOLnTuHiSjGqQiUkbPzXqt VRbvOl/OkBOF3tDhWFZi25oJTDmsFBKTlYrq9mzF1MlK6XHoDNd0OZ/tRrqSZZ7RfkO3MA5VsyJc MjQtWk05pgJrvkxej8r9Etfl/2+5NR9rhknvQsLDEob8cyXZzEr2rQFIYj3ecnHpKPjoTyRnVAjL wfcVC1jdLFv9AFu015R2ySRLclotU0VQb55ATp/TpCHNqdOFmJTgrpWbRPFNrEfgrqD1qq6U75HD P6xyF71qH+MZsrEVqts5WeM52U2FBdja6xNMprahK3ZwBowbpWTKJBJPqzAv2DZ99PmO4X1BcjVS xympC06Tcu9fVMMO+/3CT9HcoWnWRMjEt1EyOtaDctzjk5Ed8CsY+f3Z/1vbJynEieDX1W50iPIi an6STtinrlaAAWkYLdV8BpzTA/EVV0JcNMN8EE//sFYZxjmdEC3S4S4b71VHzB5BImjb7aECrXCT ZBVZHnifSidIBJwrj2aH4qzt8kFg4bW4FAe42iqkmP1sHaJpfEz/D2dHKrrpPuO+WQtW2CMuNjTn pDRLZ3525Td9L3TPqJiw7M3tpTg50nK7svh64lithh5lG+y4pxKVLf/xcfgsTtpsnUPqvZAHBpmM mJPMlaZ4fycEriWScoSGyoozwrmnm64JdB/99by8qkD9WUGBLc8Sa/BsjbQmUNx6whY4zkkRdmjE a+4yNgAAChsZwmYgMPVg2UoiKmiFGgwCIFLRGofF8f/912ufKFP40scM+eOVwa0PijwRZ+rYIFsA TwH+mmLbIC/PCtZQC8vvbSwIJTDKP0KZ/QKxBrwqXK9tyz+AxJwEI+x6SMeREtq2ah21JyscgtBp iW5II4vn5H04/9MwazMRemERCESORkxNmhcIkuFGTsFIAIUr3ZOfoAwflHPf/YDNt6fBDBUeBDjV 62/0LrA898FrGbMinAw6uNWtNSqCT63gshPEhzZfLhcmbhLzOOd7WQWg3V3kIK6QYnzuY6HtHhnZ 65K3rA2pR3mwJXlt4TAG0mcMKoY38lPuoyTBO710RG+E4QfCHf1XbBEEq9Lr6xT6N7gWPMNRc2OH yZH6iVK1Wa8fXanMBiiqsXt1rvequdWSzZ9C3VGYGIExPayiwzVUYsHYgDPThCI8ja1M6UhCi7xy mbusUFiPPrtFjhyxOuteL3tLb1SVvN0/FGf4zGx0pjKmIuxybgyCKJ2+Kl1IUXQ2G51wiGuPnMcZ hIXu/9xQhltXJ9gsotJPVuIHvNctZbyyqdeK+TeoOXHZwSSLpjwJHmExS/AxzXUvIRkE0WVO7mg5 NSIvlTZZoNlEHCmAYpzcY25GBw6bCE28UzK4187aOTvTmFZVlUnX4AXeIs1CoGJhopKBq7dXRaGj lZEi8TCw5Kcl8lg+GnvE//3Pc18Tu9y0LaIndPjV00UKd2hEuFGbOebO0CHsuF/AwqLGvoBo7xr9 4r9gRtJp7DTIjOJrzdIH3Vu2B01k/Kocf/BOX/Xt7/tF4PspMz5CLK1uJIJuM1zWnBWP4DcRX2OD qXoe9SFT/CKfFILmjlBmhRAa1335GZDGnrs9jYFJaYDdW/MZ7s6ZOrryQaEhY3yA8qMjmUYIqQoW 3b8KCkeVq9viYZGJ6UBP/Yuo0vjGoidg8tw1S5+onAkBY4vfTb7mRB9xstIpg56q9UMtdmLj+eEh VmoXfNL+wpzmaiAX6geQPRCjCcqDWS2OSVMYDOkP5PAIJLtL3ObFGUnj5ejfmkxcguegmXjC93hp C3IGdW1ole9BwMVSfAaJSYgcarExuohfGiAxcH+frFlv51TySrWif9LXb6dW/+uaq1yIZpFT75GF VlSEKvLHl6XVKiuUCCg9/fT+4NTC7nsw8ptzmdj7dZ1hfFFOni0MpVgo+qgK2/dlB5O+P3ByU+gj EZOlngOFLD+z1ojltz8vwTiHJIPhs/TFMAqqyhXYrE6xDeTT++oCcxxHJ2CdTjXmtHMW8fWFK6YZ R8/myw9lH5dtjwQFN/cqFaOTZRzH5kJe6qA6mJnNKslZuyAWVKJD8HTJIdPg9g5ldvEsDaJM+XIl cLLap7C7NGlP4cg0fBC2cB3+cjCAVgA334zZIb/DhhAcq5qVG2vgn7w2GhVF8B/99l6savTNCzAr q5s5SRNfurNynmuu6oar7cNzGsDIIq5yLHQfCboiQRLPpb8AX6cxRCFKPLb23Qr6HHVkbVLEgdD2 F4kzD8ADdKL3hlrr0QcnHEzZ8eq/DRVtT1hGMJ5lJjH2SHgcbJ0NPI+kVjWpU7hPSb+6MFJDrKqm Z+WL/2p5jNIpwSnOFUggvxuO/ZH+oHe5lxtpCYxuIsel/grLGDgQ7LuDcZ5yHMATfxo8gCOA+63w BiO/TFzf9SmUHpKTxoawHo/ARGYUiuaq4grO8DW8CDpgSakv1Kel7ohp5Dg/HmgB81XJXRlPXZ7E lHrCW+PSgaoC9OUuI7EKT6JunJZB3yDXE556vQHm/NVLlHGFBeHFa7Qi0YrcO911QMHjKzQQkjXl xoTCeJA4l3g2rVVgjGBhln6JfNoCYuylqb6iFZpt2UpadKSPBPv9uCTuFt0RrfSE7C4O9vHZltpw OFgXuOv4fpAmjATkL5opmJoxHbDbsf/fK3h9YO/X6ZW26nJdtdcatLr0HlEzxW9A2znR8ihQBVD/ sFaoxXc32DC8gTHC8N3eh7ARyuWYxX2eqUbeQLgtE3vMJeMjreTJSkk1NCMUnAU0JhAiYNBsMnVv XOXqfmBaHhGfLqxTnHeyyb0yPT1GVjvW2GZv2JVD2ghL17237S5kiS7eLiaHyRQZOIDYagWSC/cu udZfDO+FRGEUMSQPWyhJxeuLl3PJRhYK3A+AC9R0699ffjSLGMl0AcOZU8v4/Ry1hh1D88Fms0Dg FXQcONeREa3gDjN+ft3SqkSEwtTm5Mes8kQcOcCr7NfHB7+IsefiUDe3Ls4B6VkpTIQBzXHR6XA8 odudeLkKACd+9LA8Ma3aiSnBTthfNHI+LHKdccQ1U0cxffQmgEfQ7tWxVURfoas+KWHzImvSIBpR KEUu4DsHuGEOsHYkN+7WSANkYqbL4mFIoW80RFJM8LTHjR6wNIHkQzp4bMhP5od9HzXfrIlUlw++ c69q8gsp/Etf0NUpXJUECzkQVy++QWZ2pHyG+ajXhYLDRgA+0wkV9CfVZ8uv0LJ3AqR5vsoVO7ds NJcCjkFdP05Is616Ws5M8V/7okPdGO4oBmrlKJ+4fMZDCC6ZuPneSa2Tf4KB8vejYO24A3iWwvRz iHoQPWAE6Kvwb6tBECnJ4kwT6GwbNNHHlTOCOseXAv2gB3lzT76sEFiKg4fVKcGmOdGlvt/XWxO9 DE3RAhJM7fjqdA1B3ivexhBCjKOQ+paQbE2ExheJ+K/c+Qo3YK20U2BaKf7H096yPz72EdZFdLCS h2w8bBUKmNguHP8jRniAFmm+5GV2EnN1qhbIZ5iYgEGV1cv3JiKvgT9QbU8TLx9RQQynOc2oewIB MOf6FYV0BhYymqC38WlQRv59sxRBT5QOXrx86qDQQLCwJJayeMspZqQdJkr7SG9fPzsonolxubH0 1zCEP7csIiUd7unPdNoRuPmplwqPZxZ60Hmg4aeMQyTrfvZDdcNjW0xaMGtZc1JxtEvJ47p99YOk Wx+RaBC624QRuyRiRmkv19Swc/Duc+Rs09fgw1dKhiboXPIIBSxDRsE23KkZCPRTFJMPViEPLhBM yz15vtNhkLs8V2mAmt8MFAT1r/7PfrQwT0VcouweOtm867s5H5g5F39BNaYOKkgB3uoy/wtDXvNU TBFdWLeleJ2dXKwZu/aNLEQv2ZtWc+r/gL2HdzelOJJzXrjGW0hkWoSlU//x6uYR1LXHvB5QALb1 kBMhZ7FfKaq6wMP/hhCSMzwJfbXR9aSfeO1SczFhfvFcXVZn2wnisVP+CJeRN7qWqxuDAq1oqC+k B861BbfK4v1qSuEaHh4TkVdtQGLfoRjPj/wcqKI2HKFHh8U89ZAcZLpWb4dtWtaauV6IKtEq7IpD yEY5qlctEBf1FZbcRS23F3vQM/Le55cXCry0FZmZF8sQ0tAp7DB+qyZAYBO36j20PWo2icZcDhmI a2w5wVQ6FTvnqWT+C9POFfBhZyYWjrxiLHQHom1lGj8ljr+ANawC6nr0EHwTGBDL4IlRA6ZhXlz0 vCClUphi5CV4iC4UDzhCsd9FaJL+Njwt4CwDU0ginliUenyu6lKj+avH8hrYY0KqrEUVVQUubh0m ccSWA4aXcbWmr4RrSiCv20HCuvkJoJw79Z//oNu8tc9cU4TYarJqvWmYloZS0/zu2vhI9o0UALF5 0J/jxuh8LHiWVDXUb0PEjg+knxuve+TXJ/sT0N4hGtEF/3MvhAMhlZe8ZA7QpapbXWGklrWSgJ7Z 0NXp+QUG6Ijdb0F/W+f/sWgG2NZ9Ur19HU3WvVVn/cT2TozHZlThfgJCqjyENKTxAcc0kfmh1XBr 4KR6xWPp+OWegf7B7CsMsAdknE7vS+mgvMmwDNteaq/2JNLBGeR6O4iOY5WBpm6nivZkLknalJUP fjLcb8fUp7fN+9jmofDrkSPOad4NDq5pnRPheIeAK+VaflM7F3GNKVZzGMWtroJ0EdO8eUaSvVxr ookPBLHAimvUrr0SHRW/WZA1O8Dt6gKLFfBVl6NwLMY09MzF+Y4DsEMX5LGhwOtEnNzv/n4orA1w AxNLzCHAKO4/5rHZOgGpHPZ5LueU8G8dyvx1couoQbxOh9Tv7JNqvFq62rdX1z4O5z/V0PxEugii ef5d4TKUzEoSZHyuvXRuh3FFFQexb4X3H+2zEDdFE2Aofc+7Sx99E2ZEagwEQkL5G9fUEeuXnG6T QNDgyqdBdTmAE+tdrx7FIozTrrkLSv7Vd0/oSo06QgK/N4rs0lJuxqOXm3NWNqONF+74eiLYrn4l dVaZhln2brWfKvz2sU+nCP/jEQCfcpb2nOdl0MDB9ITjS4V+eRVuJzXPu6Q/U9vUxcM9gMXYwjJN /iVLzAJBB951O1ibNx7jxs5Gfm1eQdi28hgiz75yCp61JHjKjBnvUFbc08vsap6sDOqcg/j8zm6Y 7YpIhNmiQBLcn6cLWK99QF+ysMLYwKl/Fp0vcoJCSq3y/yE9lvF4zUByWmtIlMfV51uqG8NvWSFA 3R6wxZYH74GSVWtsBlQJCjt8xY0nXSTHGiBrvwRk8VGwTao8zI3gs32gsVn3/0tgG8kOUNqKuZnY JwW+t4p7u1+zmeJqnWQG2nSf6/CJ87Rq6VeX7SRRHIrLfXjZUxEBiAlt7B4rK/uQTkcMWgzj50/K zO2LV4M2nXPInXzFOx9oSRsUwdLqSCr+lB0U8yiuMPnUgqdkDJkaLNUpYVu+0QeqDJS3AkPMgGkw ggF+NX6fiTKyseHzXpCfqWFloABOg3hRl0Q/F9imK2w4p3ZBb8bm54mmlH0o0lNncTJMletVwV5M wOnLtu5z/qA0Anu9BvlUzu0ZFiPhqGXCg6TbdYRXw2WTxIpbI2dKXLuQvRE/gnvGAoISYTZlhEAF nEmD1KAb8zrzC13zvSSEHkIIelT2Q2KOLgHygkENJuexSPNd9CeqG2iSY8rNxf8kxQQIxKicPrsC 8dG5xN0OR9qYGRyWXKxwaf8Knj51I0T0YQZgHTyukhUzT7e9g5hGYj7mbNUa9Ov3SdbvNlDch9t/ 5usIGVvsYMTTjgpqZYDae+7eTZTQEgibyxgtKJ3p6TwCYi9LFKUm0oh6nSjGpCUcYkWJy2bH2WIp eZ4BdcTfKnc1+bNECExXCFIX30TJiCQ8A/F2kBojI3dw/1cYOWbQOKocwl+TmFahzD/rRzEXrZzb iCXfAO2rjcFvoHjOEZk1CThwMUP9yAg/d9CrAs7WFQe+7uDU36KIIIy4kdYSGfoI4zKqOVMJ+O76 bDz/oDYSZrHEcHPGkSszfnO7V+0ias36+LUaRRPopmt6Afa7q8mir33q35F1ttj3JQivGOjwwku7 h4upkWKOZP+nrjDR11c71bLjpLN4hS8gvOx1+UGk9jWo5NoV+3kaeSS7gjqqJgQtmwRdbpYivDC2 BubTzhnZIjl3A1ccUY8oOMCxr7fvAvt1ScdlXfmiG/9MUaBbwME4aRr95LXxBcRU9xXKhhYGt8xX 8i/An4O5e4RpLsh3gd6P/piAyPFGS22id2uVTiQAKL9WBrZE3ClM6kLmg+uhOOigDEvgL1HG8eEe u9ZcpoOBsolTHectGdDZaAeiZ5K3ATAs7+knvwuA6I78FtVhWbzHqghZZcHW8nSJR5mf0QQ0D7ps jEIpiazYNn8rFdMKmWrw5miA2hhfbWnWmQTYxZLVZWNPE9lbW7GDZ+DlfToNuuX6v8WWVCbkDeY/ LL7w1MFlhOe0FBbAVGFNuupUv8ETOVj4mbnWtNe/QyZ05q/J5+gjsZ9Rf7bgb0DisdVBENfu634R gC3aVnOkPuLWza3Lb+tTxyqci70L5oE2yGjbZ+RXw1K0uj450obAcDF4jjpRVwbRUM1bnfJxII01 zBB70yueSOnLK+Wst+1BgET3A9ZAIkfss15fmnEtadcN/xZOr0FZa2WcCgsyKh4tqJSNDwZxiXtH K+ee784H+VDal9pNMJOR8PcTDYH7QWD/cKlMw6YZpHetyyQLWyDY04ICmmzeIkWZolRCfoOSQlfA WfWWxwZgJxm7QjydmAzj6UzLAM34ChHk+WUtic3fw65wjtGJFdtqrLqr+muXaU6ZCgSLgiPVHSia TKoQqhY0fSbJ/ovEei/+5yq3959wfItKoBlL2Zo2+eRhWKZWkpe7hd83Wb2PysWr1z34HHf8GTU/ gHrOz8lgp8dHTGAfY7oMISzn0ZEnOTqprgdQHzMf0xDoeX15uP2xk5zN128Nn/f3hNqZJlbzsa1B wy7T84qbjxPS1tggItYCgtS3RqIGAo8uo7kfQ7N3BCdB/Fzj8Rybd9sOWCmS58lU7yUNn/L/Dn/w RT45sElD3glwmqKgTfdNYYIviy4aVcXztOlXKStMwGiz0s7sYQvcz34EqbuRvjSrUoY188/cxuo9 ASOrMDu949T7Ni5RLwuF/zor3Z4AolEYqli0q7d8o2nnsa2SF2mz6o/2oTKa36YIA/mlrF8v+fNc iBLOY8P+2P2hlNMddzq0rK5jf1MnGcpm5a1xmgnWWe5qjRIwrXUKCYcCMweCjXcKui4vJ7W4Y7da wnEAXMUpZ6JgJmdSw4SKV6De/xs62U/eSdQUkw69uVIZZWfWxfMjmR31wGBiVryRnqeomm7X2wvj lGB+tbrZQo667aBA6nUvF8ZxNfAwXaHDseHj5Vc= `protect end_protected

bsd-2-clause

eae873e5ca78c767734d43876af5e819

0.940148

1.86049

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/if_statement/rule_029_test_input.fixed_upper.vhd

1

566

architecture RTL of FIFO is begin process begin if a = '1' THEN b <= '0'; elsif c = '1' THEN b <= '1'; else if x = '1' THEN z <= '0'; elsif x = '0' THEN z <= '1'; else z <= 'Z'; end if; end if; -- Violations below if a = '1' THEN b <= '0'; elsif c = '1' THEN b <= '1'; else if x = '1' THEN z <= '0'; elsif x = '0' THEN z <= '1'; else z <= 'Z'; end if; end if; end process; end architecture RTL;

gpl-3.0

0fa4c892245fb80eea3fe4a3f9705490

0.379859

3.19774

false

kjellhar/axi_mmc

src/vhdl/mmc_crc7.vhd

1

1,758

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/01/2014 10:27:20 AM -- Design Name: -- Module Name: mmc_crc7 - rtl -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mmc_crc7 is Port ( clk : in std_logic; clk_en : in std_logic; reset : in std_logic; enable : in std_logic; serial_in : in std_logic; crc7_out : out std_logic_vector (6 downto 0) ); end mmc_crc7; architecture rtl of mmc_crc7 is signal crc_reg : std_logic_vector (6 downto 0) := (others => '0'); begin crc7_out <= crc_reg; process begin wait until rising_edge(clk); if reset='1' then crc_reg <= (others => '0'); elsif enable='1' and clk_en='1' then crc_reg(0) <= crc_reg(6) xor serial_in; crc_reg(1) <= crc_reg(0); crc_reg(2) <= crc_reg(1); crc_reg(3) <= crc_reg(2) xor crc_reg(6) xor serial_in; crc_reg(4) <= crc_reg(3); crc_reg(5) <= crc_reg(4); crc_reg(6) <= crc_reg(5); end if; end process; end rtl;

mit

c0197e90bda6ba9fd2552d104b2b7d91

0.510808

3.624742

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/architecture/rule_601_test_input.fixed.vhd

1

8,219

entity FIFO is generic ( G_WIDTH : natural := 16 ); port ( I_INPUT : in std_logic; O_OUTPUT : out std_logic; IO_INOUT : inout std_logic ); end entity; architecture rtl of fifo is function func1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) return integer is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; procedure proc1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) is variable w_data : std_logic_vector(g_width - 1 downto 0); variable w_read : std_logic_vector(i_input'range); variable w_read : std_logic_vector(o_output'left downto 0); variable w_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; signal w_data : std_logic_vector(G_WIDTH - 1 downto 0); constant w_read : std_logic_vector(I_INPUT'range); shared variable w_read : std_logic_vector(O_OUTPUT'left downto 0); signal w_read : std_logic_vector(31 downto IO_INOUT'right); begin output <= large_data(g_width - 1 downto 0); process (I_INPUT, O_OUTPUT, IO_INOUT) is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end process; a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input => I_INPUT, o_output => O_OUTPUT, io_inout => IO_INOUT ); U_RAM : RAM generic map ( g_width => g_width ) port map ( I_INPUT, O_OUTPUT, IO_INOUT ); end architecture rtl; -- Violations Below architecture rtl of fifo is function func1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) return integer is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; procedure proc1 ( i_input : std_logic; o_output : std_logic; io_inout : std_logic ) is variable w_data : std_logic_vector(g_width - 1 downto 0); variable w_read : std_logic_vector(i_input'range); variable w_read : std_logic_vector(o_output'left downto 0); variable w_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(I_INPUT'range); signal w_read : std_logic_vector(O_OUTPUT'left downto 0); signal w_read : std_logic_vector(31 downto IO_INOUT'right); begin output <= large_data(g_width - 1 downto 0); process (I_INPUT, O_OUTPUT, IO_INOUT) is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end process; a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; U_RAM : RAM generic map ( g_width => g_width ) port map ( i_input => I_INPUT, o_output => O_OUTPUT, io_inout => IO_INOUT ); U_RAM : RAM generic map ( g_width => g_width ) port map ( I_INPUT, O_OUTPUT, IO_INOUT ); end architecture rtl; -- Change entities entity NEW_FIFO is generic ( g_width : natural := 16 ); port ( i_input : in std_logic; o_output : out std_logic; io_inout : inout std_logic ); end entity; architecture rtl of new_fifo is function func1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) return integer is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; procedure proc1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) is variable w_data : std_logic_vector(G_WIDTH - 1 downto 0); variable w_read : std_logic_vector(I_INPUT'range); variable w_read : std_logic_vector(O_OUTPUT'left downto 0); variable w_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(i_input'range); signal w_read : std_logic_vector(o_output'left downto 0); signal w_read : std_logic_vector(31 downto io_inout'right); begin output <= large_data(g_width - 1 downto 0); process (i_input, o_output, io_inout) is variable v_data : std_logic_vector(g_width - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end process; a <= i_input; b <= o_output; c <= io_inout; U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT => i_input, O_OUTPUT => o_output, IO_INOUT => io_inout ); U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( i_input, o_output, io_inout ); end architecture rtl; -- Violations architecture rtl of new_fifo is function func1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) return integer is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(I_INPUT'range); variable v_read : std_logic_vector(O_OUTPUT'left downto 0); variable v_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; procedure proc1 ( I_INPUT : std_logic; O_OUTPUT : std_logic; IO_INOUT : std_logic ) is variable w_data : std_logic_vector(G_WIDTH - 1 downto 0); variable w_read : std_logic_vector(I_INPUT'range); variable w_read : std_logic_vector(O_OUTPUT'left downto 0); variable w_read : std_logic_vector(31 downto IO_INOUT'right); begin a <= I_INPUT; b <= O_OUTPUT; c <= IO_INOUT; end function; signal w_data : std_logic_vector(g_width - 1 downto 0); signal w_read : std_logic_vector(i_input'range); signal w_read : std_logic_vector(o_output'left downto 0); signal w_read : std_logic_vector(31 downto io_inout'right); begin output <= large_data(G_WIDTH - 1 downto 0); process (i_input, o_output, io_inout) is variable v_data : std_logic_vector(G_WIDTH - 1 downto 0); variable v_read : std_logic_vector(i_input'range); variable v_read : std_logic_vector(o_output'left downto 0); variable v_read : std_logic_vector(31 downto io_inout'right); begin a <= i_input; b <= o_output; c <= io_inout; end process; a <= i_input; b <= o_output; c <= io_inout; U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( I_INPUT => i_input, O_OUTPUT => o_output, IO_INOUT => io_inout ); U_RAM : RAM generic map ( G_WIDTH => G_WIDTH ) port map ( i_input, o_output, io_inout ); end architecture rtl;

gpl-3.0

c697f04a83d4745f18374b388491bf80

0.607373

3.128664

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux4_1_x_n.vhd

1

5,771

------------------------------------------------------------------------------- -- axi_datamover_dre_mux4_1_x_n.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_dre_mux4_1_x_n.vhd -- -- Description: -- -- This VHDL file provides a 4 to 1 by N bits wide mux for the AXI Data Realignment -- Engine (DRE). -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_dre_mux4_1_x_n.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.STD_LOGIC_UNSIGNED.all; use ieee.std_logic_arith.all; ------------------------------------------------------------------------------- -- Start 4 to 1 xN Mux ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- Entity axi_datamover_dre_mux4_1_x_n is generic ( C_WIDTH : Integer := 8 -- Sets the bit width of the 4x Mux slice ); port ( Sel : In std_logic_vector(1 downto 0); -- Mux select control I0 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 0 input I1 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 1 input I2 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 2 input I3 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 3 input Y : Out std_logic_vector(C_WIDTH-1 downto 0) -- Mux output value ); end entity axi_datamover_dre_mux4_1_x_n; -- Architecture implementation of axi_datamover_dre_mux4_1_x_n is begin ------------------------------------------------------------- -- Combinational Process -- -- Label: SELECT4_1 -- -- Process Description: -- This process implements an 4 to 1 mux. -- ------------------------------------------------------------- SELECT4_1 : process (Sel, I0, I1, I2, I3) begin case Sel is when "00" => Y <= I0; when "01" => Y <= I1; when "10" => Y <= I2; when "11" => Y <= I3; when others => Y <= I0; end case; end process SELECT4_1; end implementation; -- axi_datamover_dre_mux4_1_x_n ------------------------------------------------------------------------------- -- End 4 to 1 xN Mux -------------------------------------------------------------------------------

bsd-2-clause

2f25b0ac2d709c4431e0d49e0adc70a5

0.476521

4.853659

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/fifo_generator_v11_0_synth.vhd

2

227,980

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gL0CqO1ypyB9Iajc4H0PZWSiVuR9rN+e/dExZ5CzCiWOIMm1dkeBw4ExExKRzJIKHBnvfMPGx0gY NJfwOBv1Ww== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BmI7qCK4aPeD4rx20+AiTUTtIjC99eXYSOn9Yfn8p33JFaxMkAy5+CgYjbYDX34rK6U5iySkhAtI ccUkx6ZMkz8hNY6EgkjvxtnTtQxMaKQtILNv/DO/0dRPcEzl1G51tso++2d0+SBysiWQ/6GLLEAC minyDmKCKUfWkdQ2IdU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block li1siM5dimL8mdnKqtBlzL9QPSSf5uTaDmhGwdSa7wPFoD99doQI5kl7srjBgKvOZgXSsiucBxMP XAH1KSDdbE8pj79NttwuKGCxe1K75x7NyQDGLBfjbFsAnPc7hvBNoBKC3yfGWu0FlO+BXoQq9+mJ TZKheapqnfam/gV2tLL97UOWHGQlK5k4C8fEeMgXcxiHkUhA8got9xa3R6kRomre8jrbq4zSxdoj g8xZhvm6+wW2aZzizle7kOJU5jZTMTlERAAk6ZIwBk8hCncQKMjBSN4TJZ167CeV08XzJEIRrCKc gNl55Unx1zpzEn2SQBMTsRFZI6jPGJRVsEKhSQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Mp5AzZVFDo6GkMs+iJ6/0sDABOkxTJ+bTm11GYBNdjWmBEqZqprmdJBXI/6KNBP5n+4FV0B1J7JI MFj/cXbaRs2gkdC2Wxm2bp49nV95vZ1+dGRbfgA6lqN6xhHzd5MzNRBsZqn6AhZAPK2w2viFYdFl ytMryyHBmkDLU2obtQ4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mi/KOQkUb+Rz4/CkC0aVvOFVjkUQNWC4X0FbQYlv3nkKpZjsfHrt7+q8iLIdrGwtDs+qUs6QEOqE Bp2ZO9OL6Kv7K7lu6vausGK85Mj+MVhYnV5seqPWUOjjJioEyQWscstRXbtQ5b/uIjm2BWX2PF+v WyLUCDS8pbDb1/uL+PloLxbep9jn7tZ/7wOQ4hIFkFBvDdj4x9HppDm7+Q6LvEp6hA4Ox9S2N2Ko Dczf6s0+iAQfrfVnp+zCnNz/eH2qE/+Ad2W31T4EO+5+Z6chQSqIxer9iEbUt8lcYll0jOpqk5sW 7wL1uOnv6W/oIqpv9CCquOS8RjshPZSYcOuMQw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 167024) `protect data_block 5CAqsBX/bCuAvz/pLA8+ITOTP+PzFNqI00yoi2MBSJsfxHqrooSP3PMAs2elQr+nss6NZ8kXfGPN bhkFbqD3pP7HJz00aaiOMR35UZj69qWdZH2Yl3utu8p5aKfASw384HVf5Sn5Xjkbxgu7IDjNuGaK coAI20plgvxnsD/7djzePO5eZQFCm8+BjyxKmU4ACqXEJaFZh2DKHjsJCfN/js01Z2+/uIKsmdD2 UFcZ7EcSbV8ZBhgxEUIoNwAUow7OcwydJUqHH6/Ah66Rl1Lm3+0ejnr2Kcwub6EVgYDXvWyI1Lsr WMwLLKwVlOVXsYqQWSvBfCH0AtNylXk55Zp/1V8IHXYP/90B3OOGaHiEc9QeDqd1H5+vp6WI9JS0 tgoa+N+OSOvfUBZanc1QT2eKnNy67Lq6Ve2PshxHkJZbVhCaBe+qrdl9ZHYUHNxLGXatyHpyStPg FWGTLJe3HBanuaBQiejGVTB9lko2qee8g6nrlgU7QOUFosELTnEjia4CHusNzSBwii0IZw0jx8eD c48Agl2/oiN2B9ekeVWdI5V3ZdykIl/1Dd60rfmBpxLTyr+BidPj5Mad96QddEfUpJdCXV9CkmQi R9rbNPCF9bnAgoYteRfk+BA2T+ueNZesfA800KHP+fw3zCAgrLmbZen4FRf1usHVtaljRLS1IZbh Hv8B/el+cghQnO/HmOFyvYD7PrSpUnHbSgmk75vdolOgRbnJlDztmx4iu5KD1EZeW5cVYXBMUcwx ehWWBPgg4Yc30fAGP3EQ3dolWu49MKJZngf4FoxGPcZ8KQ/GHceU8NcbWN+e4maflR/RdCWHrwhm BQ1Gyr2+513U5EOkDl5IOJB87LFOXakvKnHAh6uU0UDrjdGjQWLUSjNqhXIgX0UFomK4omhWSkwI cu7wABedz8IEFtDrrnW9M5CKVwRoP6PsjopknWj2J0/5yqgtXxd835RUdNdjHW6IR7Ruid2sYPeZ 0bsmEb4n+G4cWeiANa/MkeGcVlsPaBHv9PfBUbuFFazh1qtzc0ZV4xB5xLs/BHaJrWtuRMpza/0q 2u8Dg9UuaFyrjzj8nJnXXhtYxrNc4u8xyGwLX82cWsQKwUfJdt5p461T4KleQtJiYyuzXmjhBABO NcC+XhBo8Coo4H6hkYPjQtdLl1dXlKUAVvOYK2q6huw0uGJyC/oipDpeJg8TnoM1AInhmxyWvjD8 OHdZyAFrS1S8/mJD1iJ7Mk3Fae227eXOwdz/tYziRNd9FJKnXzPWF6jXCsQq5eerYYl8oy0wPrWj LKeIPWRn0LS3+EdfUMxRWiiaQrpOMfyhz+aP+AuLhxB409iYT7FKLcawJP8FjpeWUxF2wLrZjhLn DpeBhGLUrVHh2xmu82Wxnc7gJ4rkqTxpf2kQ6iFkH3KzYtpvu1iRP/vP+FcngJLQjQpv6k+lCDIr nB7GSUlguo5WjzVX582T8tYeDOd9SHFxo04T5C7NdBn7E96Tnyx0NLcTncnKBRY/PoKqFRP2NA+F B9luWTAFkIiYhLpuEEyaPT1gYQhJMLiOJdAv6bq9+LzEjC67tV41H4al+YqAKR2odcaJOBM/KaZl hrEbni+kxzrflIJZB/W9N3GB51NE2l4WOTbSOSZ/JmEtw0fa4ixnjPD1PC4CqOxYsxfpPZqBSaWq o5kBjgdftoKduMs2fWsH5cJhhm947Q0OHFtrkrCCVY+i2sEG+pLaYg4MSSDZyTtRD827fUgEadbJ iyTHMYeN1sX69znIJ3enlzGj1ebgl2P6mNq8O2vXbbP1HmC0phaEjKlmwKtiaOjbLZAhBVuqKDgH uAGv9hv3OCZgDWbkMfixdIwn0+I7J0LfKTxPQJuCnnRcvu2MpJpB4z/7QaVjJJmqtm0F1vmeeLYh BdvKPf6th396otGuBuUFAubBXfvoUrBUITmzP11ZvJGSAmM4rtUjuvGqpI81jmJccuOcz6SY/gEn Z0IQ+otIquSYNzTJBy4hUQafxWwrrB1/sruSKHJOhrAAzdsl5Wzmb7GBo4qaEodxKatECKK5fq6Y elhrJiC0RktRT69ucpsbIUKQj+FixuSf2iO5IDW81tLQI/55vkc6n/uU4t7Hvurj9uCij12K29YL /MeODom3tkxVYH+GR7PRhLA3WSqupmYdeMhbqFn3CpoF17xgF4Yha9zBple3g42818BjyFbz+arO /LWzbIOBcqcolrGun766JOR3rxYl0jB5O6+SD6V6ZrJP9I0QmGVZuwxviItK9+5R450Q2LUJTXyO Y7QfKh7tgVXk/DLJyVH+7YIbF+lGTEL7dE+kCYGiL9uIp0+fvnjZyGCLxAOQOp7aIhpkCxCduRjU cCe0YOS0ribdob4hE7VnecfFjhnm7rDA9szY/j1espwg5QWpIR2icTHFSK6I+jCU/AZtIfGH69eD pPyyL+4TQ9xNOu6UyIvRNj/tbK9A2gFH8KuY2xJLQgfSoQKll6L9HfoKFPTd+2Irym3ShS1WdJSI ELpOOVXzR9imAoEvJpyPRHTF4S+ePH1PvVexCQPQObmN0NeXdLqOhslO+Uv45NQDzT9zLhfahg+G KUorBL+S1BI8ob1RQ7A4gjH4KoUFMsQeMNF4DIBI9x/lNgZhSeTpWQePaIzW8XiZFHBUnTe4QHqk SAAV+2x+pS4rGsrkn6QrvxhwLBCkgQEaMqmDCOI0klNiYQMt2icYwn45lqVO9nv2S3hXGDuSFcl2 qhH9I4FCdqodadKjlncjeH5oa9hhb+DS7Hul9mkdQbYdabtA6KIUwSLpLh3qBkAvYquUKfUs9RuW li0Dl8xDnZNbSRyf61IALLw62ycg27Lf0txZx/AW252K2VXUnxMnvDIZrhURBurBii3XMmrDYht9 Qrmtxn/6bcRUPdSH4Lg6du9LcmN5S2EPnajNu97A1RiqXtmbjyl9b2STNEixOEVuRvGo4dWdsEIA d/cy55ajrPNZ7Y7waAf9x8+LcGrxR7LQQlZNxqFOmOCE43XJDPIL4FPxxhyQJ2gV9T5N24sILblS 45TlyHS4CnFyNBQ8nIHAchov09uBgYpYfqfRFMw1a8eToFA/LQyfJxHZo2o2zC7pz2JyuwXEMS+T mBtaEKpKIiZvTorRzzJPPLKEp7P+PmS2DUrDfK/eCCOoP9NauYmMwVLHnQe3qeZgR1g0TRw0+qDX zs9/ENQU3r1RvjyNU7llzeNHLi84FIeQ4Ril6VLhA/owdlkYK9EP1DG6WOd6LC8eiftAjVL45sTH FEX+Tjz4MA28PPgVa2SHrFbMHf5YXne/x7d5A+LVkHhaCkknngxUZWDieWTLRxIqwD2U7C2Nm3u3 lQR686QkLbpa1fK6aDSoWHGwzURQV3bTZDxbopyNEfxN8SdNMAduqKonAsK90X60nVvqD379QlhX 3LbPSg44esKrpjc7ObfrmqIrI8nTGNXxQXD/FY5PBsQsQktss4ovRTY2iPbdUmjwDhZvqd/IGkIa xJluBITHt9UiEHHC1VgoyTdJA7LeIqgkXfJtSvguM5jG9L/4wU0Y4fwHZxLqLhXAL6DbZbnKV7e9 oQRW8+ngyDm67A7hf7SA8ps/cnA1XmrmYslrbTHZlDbqOy2Qk4x/uTE9tUlPYgTIEtZK1XO86TJX VJZ3+SWrhtvVdB8i5ggiU7zCLf+O/1stm7Jwvn9aLX/0Eo4DUcT42tpXd8yZPII5kcF6HVPtZhbn 5InPn35pZo1Qndgic9Cw8HTC6n4hjRpPfJYEAsJCItH5gpZK1hCbRSGwSEn686DAzyUah+IK3UdM 4GGZ/1nkSO+ZCajBRURppaw7WBJ27/utMvbzORJIpHe1nIELTESiNrS5YJ2TdGHsoPwWdt8exNbt Ex9PHC5VoQImsh7XhZMWvlYpKq3NZJnuss1Nbim/MFoFswDpiuG9SIefHwWu4sJxeFt087m8szk1 zq/1EBUc2RGM1qd5Pt7rfOM3MRFdpoDsOtR4bmLV0bER8RUANnC04I7FEcLr4MfcxE9UDS4Yr82x MK5MiheMDmLklf9glvRcJrQXshZ05O5svK+vAZoK7grm0f19mvF0LYUjbrk1YEafQi/tE4wzuRTf SSMtoU5lrvng/4Lj9wIy1VA7YM2s8bnKOzAV9SBimynm8jMnqnYu2WOjH2iZGhwnP0oxoMo1MFN1 uVWu+ioDHa8ZaaO/ecd+LToelWqYaDTl1nZsC7V/1r0qd3ktqCCjxrCRULU2SeyKYZTt15cS49MX Fm11Vp3ypSgeGnWs+9MlAjjt8RXnN03Q17CW/EHXDw1ooHv8Xi0hOIOvKDawAYsUHWUj+yjhJiXq eOtkE4bbZCCD0kNIq9eAwFgC5Ojdjo869vbnoGygMVGx1e410VPwNiQFdosdxgkpzalfz+VCpZO8 PiSOtsYVJqWW1wLYlkDCNqsJpsgYskJ+Vxf+Nnhw4gNNCIFSmSMgBkx1xxyB74VyWgfPxWlgLDT+ XlzlfRi+MOrjY+qFNxNasWzw4LPzyST0td5u4vQBUb/ddviA5EMzSBd46nvpp4m5q6qPasxIKYpD cd2rLM/SP/u6GmBdk1qF3SCXybUT06boaaQ/CdqIJPwApd9klNnCpz7zsiMNWms2JKmKQo3fGPB2 3j9fnXRxr4T8GQ3zl1KbktWl9wAivFAaxna8Zk2euHstDep094attKc/ANFeebICwJRIaUATJyxV vZiwgGO52S925FoWIoVjDiCnLgUqWarPrrhrmLDCgfslNIn3v9F48MEeBMIgWT+Ozn+8/RPcZ8us XrF9pCF7jkLQtZL5VqrqajiNOzwoFPUKGho+fCM71NneNbIn9DgaSgvBJHQm2FjvCduJpSYQGTvP WqMItryJXDNBvLkac9Y6i+mIgiOD4lwpM4GMfw4+6XRzOh20+9W4efj8P57LCWa1tdESwzbq+twS pGG9IXfbO2moM7+i53vBn7rRTkxiLgRePNUGOgwFkUHp72A3+QJY9HyNVTFbvOWo8+GVxzDhedYb 7bREXrM4t++GJa07p+kvuX3pfmgs/V98tTgjPWREhcLY94pi8kfO18ys+VUV6p+3mpk7gcWISIIf GGtW0ve6C2mKaKw764VvuRQw73ZAzDiQxnhBGmlrj9a9SUhgX9yJ8x3NCD7NoVbQEqI+ngxr00Ct h2holPjJ3Ow2hpSMi4aLsc7AEBq9BSN3LcGTuWdKZAJibjiufNlzTLW9+VkUFdGWsw0Kbfhic6W9 tT8oFal0cVmSLdg2ia0MFVaC8UEtox3N3Mw2480WDxC5arBBRdiUAtqz11T0uG3FNk5y2a8rQHtB VnyIOlLotF84tfZcbs5mwzO1QXP//WZUvPw//3f+pCvamZsQjxfYtrjWQaau4mI4G5HGJ3nzw72J ciwMOb2WuTowtJavfTFMzi8gklq/2Q/u1X7P+K+Ccx0yOKhzTPDcBJPcsn8zLkWQUknTNJRIGMEy YQ9lps8beV/A7c+KqWYaKpKxzgCcFFvdtvLnoIepFDvkVPZgBoP8VItkvaUHqJviwyPcdoPg3Fws gUiFEFduDuy3AB9YUJfSPMzmtXF+UGDFubsjm7cqqAzT42Px71A6GM9A3FZRKCBsLel2E/UwKcDq UiJEsOCA9NYtNkI9ApEBrADmcWOKrQFU7OxDyl98sN1tbsn/6QlNJTzvpcIpp3X9Nvs9kczIpZfN Fe6dVCONBQNm/OHLWJ1fnqs1myyd0KgntopWojRYK/sgdL1Z4J1LtHlewF2biKBJWQ+K8gIjfIos hGXOHOCR0N99ECi0XFnCKugonGo/M6hJ3rAq0fkCs5Ent6A656w32E9QXfiYZ61ePZ2bDz8j0uhr WKx7Bh2v1YfCW29FaiRz9wvP9k0kqAGzLlWVL8b1Zr4Mdf3AEIn4iCQvIhHdrc6PclFGyE1fsiFA 4cFQ5ssl+jHKZt/yy2Ax8Dh/DnqzrOocBetfuAPALsTLn/4LnadvBrZ6mLGq88gaLpxE7FG9EBnh Azw2GBYyJklMp1ZDZwBTXZ6gDWdHsyax9aLfz126cQh+sk/EaivDSSeEz5Ui1FJ4pGnh0zxqBExW +1zja/nqMD+e8hO/thri2Vp9e+RUAcrQ8XZRSM8EGkG8HV3lmc7L2i/9jqiONHvF/ztLEq0chBOQ 7lXjeqrK3tW3B4VwOINB9M0cbO74wEmpJmvXckR2ahsAAxNdCXRS9oJi1Oqja2XIzVwJkh0I8e+M kOvUyUjiGcRE9lWVkptKj32JobUMO0kdqL7FDu3KWjUZbiPXQ/uCUipJpUdsVV14Y16g/qmUadST c/IDmY/ey3DWH8GpwDMECD2z8hUZxDjkwi2BrPqWuTcew8CGcqAEcOMtWLSxtq83Iou/g+f2JBho jvIkG0z0QGAKrbbwcWCbRZJdEU+r4FjdYwZbGkMC0rkKZT1ChAc/cmC4wfMajSxZPGjR2ybRifOl QNOl3eprUhTzTnYiY8ac52jums87u1SpPIXXQs1WIy4uBGm7RdvWlZNnz7Mz/QFW/GFH2OKLkc1x 1m7Esx2abMURA02YOjA7q4vd7eF9EZrbDzAo0FuMrtsLMZea2kAbkSw+OpP9jkzoAbiGyY3m/wca fEvudpoq1IwczpYu4obwB51dgVHMg8CzBVL+jiAo2764WXNyl8l+1KsKfQtjEd4NF2WyCqxB0i5D bFESVfbiCcckrl1JgbUD2jbZ0gKRRImupLjnEfujnM98FDRn0KudaNo5BK/9GQljXcgybo/qVusb 3GL9uGJ5imslARKSFmTIZfg+gfl/mn69d1px+XDwynKUY/kcck3CJmUK3LtfuC7h9NQ9O/wRjABi K+SQf/XhZghGMKhWp/KaeR6nCnwIhVdilSZdJlCTPorE+7x5IlaLgoHQP3IfoweApvNQ2WKLpiaR RPkbjADlDY6QqO5rZ0cS+yT1OGpCOatowsNaoxo1UQ4s5oN7IeAwsVjtNodmfFyy+OqKpsER2jty GbEQMPUf4upoMF6/7vfG/VfSGGUvKWKQ6zR1xpq44LcFsr1PZ8+Sbt4BM4fHYnLlSr3fvqLHddWR mVp4slWgE12kx25jfRFbHKJj1d/MhPXH9GrpBxEySvZij3vTzsykWXHy6gfEwLnI+Ehm6hrIxAji XfIaGHv84IzxhEuCc1Sjj0bjCxTJVg45vaNk7EWRuf/fiE5T+QsO3iPm2bbbscsc4ynPJHhajqS8 wZw8poLEg2T3/IKCMRMWpNFnf5Gev2OaNO+jMQzdJ795VbS+XwPC1gd3k+22aDrPDvY3UtxgFo47 CgEOU2Hy5eGZzq/aRQfwGHcy2JqbBP5vrBgh+YsZNUhpeCnkgDX7/2MOP1Iz9kDS7O7pP1daJrYO D79EcWU0zElEOVkEFwBJR9Fe/VLRKcVjxVmiDFwh2y0db6jaArMev8b5EifAWoPlsbsXQNByoe/I 3qRcpRvQ63XdMYu4An5ChMADl8HRx5jxTAOdB8KEFe6CV3Slp5JapyFbCR3giH06KRuLr1X+EvqB bMNTKys80DQXJATwvhzwv58aYzj5SgAZZNJLXwwf7H8ZibTiVE31n3Ngxxr4e8s1vO8RWqF9lY8w THmq9k+X50erGwDpfOfVlzbhUprHzLKYmlymJRkUgM/iiCa734IYcmmZLz7AknSZRvTCI4iqSTUR RDodd6FqIAZxgkaZ3FLnrSeJaDqs/Jj37F3eCLKmO2Yk8uxiWGiELZIi6e2H0scB9nlKHSqCF07U 04NgiDxYYPUTWz5OaurI9giGpo6NXEBtPms12kkmlhEgfnFGEDNNqysmtOQUS8fEpsoGwys9mbFB +6DuxSEFqMHhKdSPybq5XBaIjwVxK+4ZmS7ZtHSrL5OImm0Ykkq64J7/O0nl502YJFnX9nEo+Kdt zn51u29V1kH4b9Sg5Ok+XLhkJ2M0W3f83/Jvjw7VhHQ2Gm74t29Kj9xlG17d15UbHjDdDdAn3RKA TRApFEzr3zFvVeBNz3nASp3klnHVZ2/mnR3iIaWRy4bVIwzKqEOj6lfruNCWeGLZvhbU7VDR9ABs ZWx/e3T/eLrORCCWxLgm+zL6yKllN9TSwuZWr2krZ4wjPgfSIWq81mnULRxB7dDnXxIN4Ei4Avvh 5WgVmfwEG0L2kDqfkQy0gRMk4iTeA1BfHrenRkaIUspaxbUCJtxBFPUQgAUURo21AsWFqrQwWmbJ 7hzaiJHn5GB7bnVvWfIeRToI8isXJ+nmEFrmFeInfVXykpOo1tZC04C1ituDnf5mJhp4RX8Vl/k8 nJTXvEIEOW4ThmpfJ/xMZBKBlzDxveS/MCSztv7YNY598uGya5o9GNTA97IAQCBQoK91+/W2s+MV SHlJm9t2OTMNqmFo980/SLXeG/zAk/7sVOwljZsbIBwgvL4ZrsOLoTi9OUu/SR+V4DaDFRMoITbm xi0zfmroSxPDNs9BGsEBmSP5Zcptp49xSD2iWI+oNy+y3F8Sc2z/X3rvuGxvCQBXHc9v3hCcRwFH kB8G9U1h2Bdu+yshBvtIHbxoDBMmxGQvfgeEOPW0nufv3qDQHH9fsYnYCuur4fTNVIYzAR28qzdu eSJGqvZ+MFIVTfYuePSzWTx3rEnvcC7JnNcxoQga7csWyT1yxi14+Hriw3vOqiGmoSufctaFpm6c RfzkI67osKUwonl+PqpbzfLOXaSfJ5AA6yieC0Mz8uKxLcUJrmEZpYhi5WDMX/WPwBg2NeJBeLA3 Qhg0/ccCqpzzWBnAMIgC+VQy+cg3dutRpTIPcQVP0TelzyDV4HbfQT1DzlwGRqkSW+OoGdzyVviw 36ZVDPkNGY94tHQAHsBLoL9PfDJShnBfwPO55KjNraov3sMFswOGtGHzcXxnfIVeUN2QGPr9e9K/ QPebr1KZlvP11l3YJ5pG3pjKXYa9KojGDdoZLLVHKsuwzEBbseT7gfBLQukup56e+XfFwOPjEdMj qBdqazQcVPPW+p9eunmwquXRdHJot+wFy5Afdnfl5E8FGsn9qfXWPHzKnczxyBrEgZj97+CEO8bU 7JB4of3zZ2yO7EqSmigYl0iM2TyetoOR78PUudFmyYcYyAgCfAhO+mhPEWa9F7JZePxuusRFHD+v lDvcvBvCCNKNg7fNogY8FdSPws2pyciF2NZAJniKcN2JAhVHKioVPItZmUy6tfLsDexuhB6QXSn1 xPBYLvU7uZ5qUtejmzlTTR6ZH1hx/D1Uofu13kUhXIHbQgN9gGOrKkq5bQZy4O/mt7oo0jryNyVE aEAn52lAv3IvkI8jbPMUTBJ5zCVEMgmXlRg5A0U1KvaxqXLUS3wIfjLlmKx1xgPf5Qv38hOfGhn/ 9A33Ix2NxAVo+H7bo+JjW52x3StZoHtCmjucPXASeBI2zFMGhUPNA0/hvbBKvpYDnZVCy6M0ooGa Bc2z8hxlPYB94FCiWdwPrkhv1T025MLkIaX7+ESN6/I3AWbnq/KfvI+G/ZSjbliOKpTDLky/nk/K HYrZ93NVexcZ9MFL+DEOO2PnkNfAYCdoLVQdOufWdnuQKGGLFRpnOBnl8JagLN31TZXFA0PltVoS 0EMVZexiMnSvo9VLLThMtXHRlrqEQD9u0HYjTrCPxnMAbKIGvJX4YM74w5NBhiO7kMw/dCaMaE64 Nws4AlySGWuABDju8M4c9Y3R5+r2MNvnDfy2ScQuSvz/TV5tRdQX2nuRVnZsNPGbdIC1cHAgIMmG 3xDea9fYDOHV/LPCmTKmqABc48kCAUpCaER/mDKROX/ZW8lcRaXH/DT1BI+vKim/fbGqetFHBXsv kEJv0lVYTta52ZwWVeWH2/d7yGq9fYSmvHZoYhOz6/K9YUfkY5gnbFImyB6BJiE3FxIPWbq50Dmg 9Igyc5Sex2tf7GEaWnbfWGP2olzKtbGTXLULGBXVY57nGEM0lA7u0cZQxgWBtjGinoJ2QUoydqlm VKP7C5nC7CIkMV2zGz5EKcNNHnoCk0T8B2fFge+xlWiuZS9pZF/OobrxK/zLiI/Aqk8yGqhjVCn9 32InB8ZLBqZzZ3cK2yCxH7cpNwoO/AxeiHhOtp0nYbNNThngUuL8+gnqJ6EfiUw4r9ADj5o6kLlp DT/YFGFo5mtchmzLYGoiB30JrV5zUJOCjNknTOzWEn7UESoXn5tpcrVamgpTEyG34YUuYYao8BM7 ScTKA/p77xMlnVPiMEVhSi2NG8F5mYz9gXbC0kvD3Lv4y8ne9vH48/F1P8UifpCX8GPcehuC9eYH 2bdjSpl+aOSzLGDier6diz/75WpQngmwypKw0JKu1qq/jEjSyh1UvOCdNZuRFs2cl3l5qlCddLPk PK9WTCHynreuksIjIdanjjg7NTbZ29emcv9DSESBB4ZnhuZAZjNLU/gv4O0osFTeI2E1FF7neZaq /kvp/7agheCFtGMTofakoFXmSJRPoIQxdI0tvT4In5xSl2aSekFa5EzXpxH4EKeA44VbrcN7pSp4 8QpsOOqSwbZmTEd0+6hPHta0RUole5pDdv7AlUlXV3Gdl2kjjeSwfURk9GsV+NT07xVSKWZvF/tj E7j+PFci8/HPT7YNOnIGm2UskqjTazBmd5PUTuyRzgDUjoqz2ShgAyYEypSMhtITKiMRusqUndCH yGJBnwEyVO0lng+0HENsUHnS7fGKDBy5cE5fDclcYuYQ9AWEkf7VgO1sUwYmj7MKSeY6XzA+MiSB B2xSAA6ttrfi6VnSzsqJpXyIAiin7ChFbCq51IHDA627l8DARmkQwrnxrx0sCrTz0VvL25rQvWtT 5L2cfZXcJM2dq2RM96PrB3dInCpjVm8I/n9uHFqEq8NLG/zH4rWs2d5Fv3/2Czzi3mqTtjHD/Y2+ M3HpxVhsjGduzby7YngPYxF9U804jLPM513nEAc6iFBA1iaw5bXefqNsb3xu7ORBtCplRo3jllhL CX5fE08qT4Jwaa6PrA1ORtPmusXXKnScwwWHbhoyynCmHp6i3aR+8994iwa6qK4yZxD8ISDHdL1S 9rOdnzjg1pphdjiJzvrxku34ExPYncs98Eju1KkePtRyVZ2hICzb1Of8i12h+H09puQuMKBQ6dp6 it1LBjvphQ+r+AF5yGtx54Tn8fWR4pgNaAmqeuXieiICn0vuSG6Ygq8/2V8gHA0w7VZ+p2ZAtQdc 4Ro5CQzO/6uUm7khRiI2XRpSghgFwxk9OtzY5uIPflaGLFN74cgndMXuVvDnzF7Txf9Ry5iUhU8K xgWCdntg1nfaecMngeEuETMD3//HsaW3w1ohsKKgJDxU8ZM4JAvImj3r/QF1JZU60eJ3cK0bVmKd yRkMSM5rELER4Qfm1J0+VVFa95JD+JY4+YRcwQoctDJJYoZx4IUv6yYdq22k2RHZZ019E/YlWWVa 6DtUNbrzVDKycy4kGWDD1sJXOUWTb5F2JV21+p1xl+syAxxllLdhKcGfB+We+ym8Z3CoXE9pYxsz jZxFuRn30994FGBg89Ie19lBQM+Zyv5WYxEBe4um0eKuumUNy9mQwZaa5IavzW1oH9CVajEhWoPD rle9RmGHtOhi9BbK2P+/JDHOmhlfMD01If5HzRwxhFJqSb74QE0zJoOVb/avCEIcO0/0y4KF4wFr TULKSt4NE7CNGtCYmtv8BeHpOaEg7x6ZGNtRNUVSyHMpQt9BTEVup3ATR/5v/7lk4reqhaYQYXl3 NIUXldPeYrlVSQb6nd4l2rlmJfqwFBgWFD9etgzPhKpl/+fSxmkrbXGFg/L9WGMFWYWiF1gc0Jfc Ta63EhqLAiITWtuOKoYanvTif5bjde0O4Mv0YMOY9T/ghyeEG7WsUUc6dIfThsJIeSH9iKEW+Jun G7XcXs+yJ5/J6Njs5Ocip7kZl/pUTdWRehh5xn9wrKTvni5SWPTujzriYX7dJ/0fz0Ffg/c/G8xH rtk+njnAXhSi7HPQJg7Tnt5Iy1kVip/z3IlRxQRIto/Y/2rwcNyH4TWNSrTxouVZOSVW70n4VjZS lg+1hpw1E5CGz5PHxlKgy2lR1RjhWw/etLC6E59DFeG/AZ9TzpSSGPyKyJoZvlqzOosaQ+ndNIuC LNQy6TtkBcDoVLzv2Ui4BGcQWh5aBxNp2eOKZRIxzmcUTtwXJt2Gt0nZ/VKlzdVP/sxKe4DOd5L3 v/DlmXIKXPc9v9bDH3vd3EnaCYxlYvyW1tuG7E45M6zdSMxnM+ckSAHXhjZxQiYbJs0NCeFlQu8a ju+BvrZIqBpv0eerMBfS2ZaMBVETuHubueC+pTy4OrKTyXVGLJgRXcda9V+58L/P8yo6d99CB1SV f/mtHS9FSHY6NL8X9afbSr9mDnx9u4ZL27/zRJe1wDJU7DGnD8U2jAAJRvAs20mEoHkjdkh838Uk SIGGoWmk+YEv81OYofApWRYL8mGzlgTHzaXfnmHOa3EvPtpm7oLoM5YVj7hO/yb7oQ5JmLyE3nT0 iG8rHMo2xqS3mLirwJAA2GiDqJWEa5SFFV+Fjt1FXn5B/KCJwm1XCysCOBcM1JaOtu8q0xdWWIjd WGui05iODPURxlSIG9/KzUy4W6KTbT/mm3jrd/CDifAkKFfiKN5mjAIHIDWHANelozogYh2eKhsz Yv0y6wihUUgrUqsnwbfWrAONyR/fUX9MlOpiI3/Afsa5pafLv2jYDcjs0MHDlWSGIdamyISBXeoF x+LOcNXIemnbzTLQaH0cWhTaxgxTBJ/GRidIQolumyRF0dibS698zUMfz6lWY1fIOwPW08lXbJ2r YJYQQ/XT1LFbUM4npk1B4eUsjgfDWO0PrAHuHr7ZUfrEU8uRQDz04pDVQi2VCAIk9/g7cqCXPuN5 lvMeXWfGWZ33swe+/Y/Qqwk2+ACE2pbZY+/zvfLm3LdpDHYb13s2JrV1GUcITlRrAy+uPnC1NsQB aIfajVDXmMvJKfwCruGs6zsxq30vDykkHsiht4UEkdBlO99dreLuu93MpZ73omwxoCQlyrlST2NP wMORb+f+fgMPpWtx/dZRbn1hHciGRpgTeRXTrDEYOHmgb0sUGZ1tjv5LfxVEQf4r+6evL5xq/VIf eXBXqQ5RDYiJk2EgfQYawPVcFal9L4i0VfOtpcEdXYXH1fuwMEdL5gEHbQ6X8/G4lBhhEh353Sdn Eh9BUFMWTuOUP/HRUYKxd4IvH+NPbrRS83lsQ7JQDw50uVhiqFjFFk9DwE8vAIFPuMsIvYPB1Dcp o9DE8m5zBF8QjDnwK37xkTPPSrJyfe2pbiQ98bfW6RDI8hG1HNpJSqFOrIATgoh8kcAYTy6jUCd4 GEWlwgSCnf6/LUGj0JlGceQCj7MGIP1OHIxfPPXKjI3qvw88u/Mzzq3uP+j7ZT7Dk79tAiJJ3sKW CTH1BOkmzbYUFLYXS7hyU+ve0NRXB+mF2+1mbOYsXomBuuJj2eFWBfb8ZsDk1ddrvopSKkQBrD6/ QbXtmAQjn5Kqr89Tqlb/L3eKk8N8KNymeGHas9UtaShE5IuJ/kdZSFz+9av0dHyP363stlNju8xw Uvli0VfXFKzMAnx2E0vAFXlZdAP5y+98J94c13ltnhNlqQliGSYrV5OyHR+FmiovKWL42/Im5WQh AI3X/52bMJ5P3IEDxtMYWB6eN6ejsoR3raNkHrQl+itY73edzCizM0myarwvNXDEPHBi3lFCHbvM hSaK28TW+bvcRaNhJuj/3hxJzBWTpukbxfo+jTGRd+BliF8bHDH36y6uWxzCBlAm0iRzdhLcGCN/ CsuC8td5w/91nu9EOspUh5Op9tqZHFYvZ1KQY9wCaD4WnBWR7icd0yyDuTpor3WVqJnNPj35vXIV aOxOpavCF4HnaV5c8UyDwfuKKEuAkf9HbLzgTToYNNqfmez4IpNbnR3QXcL5fvwUnV0exMpXHXxA aS07bNOPvVg0hew0B3d/7mRQEc94vcMMN3LCJ2K2jps4QqtUmgz6ys4y18xXTKt62hlRdAYWxkmg 9eKkeSkNhtz9P3iBdSy06qjexscl94ZZYOvbBWpaHQHtcDYura7HLjv3qLRF68UST4Fh94dg/ZIh CftqII5uhqfHqDw3R0iODqU5/0AceJIQrPfjQcWAI/M8t4nyvuKzhgURU5LOBvRRAAGQ7cnaRp4B XLCBiNX9n971u5ehBCKRd5j7jgXaGczNs5VQA54p/g9OGEzJLO4OApI/oucEyW5VuC5HvCp7IbKq 2y6Fsaaq2BvLd4ROuVxy5bYMTVUrIvczyM1j6g98Gh1EFBrWzGDoosRM8wFy2MVR8/QKVANugCIx XyS9pMG66DDrFC/IhBd3pxAdAaYdR1mgbwFTORPYJRDwrCMNzzi7wyV1cMPoB3fqCVrdJHeHQNG9 D1IQPBgyZfUe2uth0f8k+TCNly2+JEnHbUQh6mN4mNTS/e0044OJk5MUDIii3475FrrimfG4+U1i N6Hx6J1sx1JhMNBoTu9XCTv/tt/onbpl810PIe3BebhwRJdh1CJmQvSFVtaY6lIZ5568p3rYKCCr MhUx7IYmOYftorM3bZC83u9p8H2q2ljb8rqzreJeElU3Bmtbiu2NaYRWTzJ1tNKFEyuta3lnCVW9 awkdjj9XrMCtEggU8Gi465g87l2SSuDMkN/9r8hiN+MUfKu7V1HJDP9gWYDUYz9cHfpUkB1mlNul vUav/Qgi96Rmt1dlWafpSRs3++FRomn0I1+8R3oVayI5cD/QzaPwKnn68bTehp2ijia1eeuSnQEw gHmyjYke//DJD58qBr0O6kPmd3q2htOlnObe25AMnWLTBzEpcTsTYW+gAmM8EBGkmH4FljQhdajL +viQWsS6GQ9K6VrXbZcGXtWVj3NZT7RMPr61V1gZleq20GOYLvuZBmJxnaT0GXEcxBk/xAb54xbZ 30Kt6xsAekD83LPg6dKNZk0HDYgf6UPCh4Ix8t3DTo/22fkQcBwRpeqD9+ML8UhnR89AxzUZO/+i TjFDLMF/gGcFd5ddz6Sw4D4iE9hVFnwApnTJa6BQHSmX5WqhSWBaAUFiDnnmU59yBkGp7Y0tJidO VhhF6FqZeqvm+qgvABrNsEDXjBZkOA6O1/ncjSnhaslRk4V2kxc021uSJVEZQPX/NEAHiG3g2Keh +6SuTTpBhP11lRS1B19fbWf474rAXSr9+eV68t+0uBdPEQ0dbYe9qsW7rYi7srzkOizCKJZmwLpf vrVg+vf5JDgtzxPxFzKHaDuJd1i6itstQlnsw/3wXmBAntUxO/VRH1cttYiN2eLLqDyoTUAjeF87 JMLhkGP3NrwUguQnNEuGfPEieQanmqSLnlzMQe2NNue4aEzEPej4JmSycoQ2BhgJ72hyv+ICf71I Mv4xGRSuOkTsTGo/45hUe26bFpcUEM7AqamWiFo6zhH2/IGPirzIOZgCiSYn/FZLePD3CLv8QwhZ MITeMQkTHkeynqHxpPsQ7ikdQ8L2mVzFcOGsBkaMWJd5GlKk0GafHFKqtt1hA8MSWLhL4vOegDdS fSYiv4Fe5sT4oKla8C0Bp2gh/95WrBP78MbzTAp5yn14BUgrvG+IMtRjcsxQOUVukwCdAULIKjJr jD3GTlZSIZ7ZUxBEyubovxX5tGBJZD+7TO89E70zGQhUZ7yQEUJg5ivOEKgRQGCyh0W0ZHAfsUau 4loe1jcb19texwlF25bZL+ZpRE0mI3boHppRWdDJYdfht/FrLrhyJXPfV+ZFef9vWno3N0us1vEc U0KHwfqkJM24XU+daRY9Wpl7r+Wpd8R6tDwP4aVjFslVbLBBs/E41Ojth6UuFbXtC+mNuEhaiUZB dtVQ+PK6dZyDkzb2bPR0CAo9/0D5CNFTyc9xvwh7rrm3gvD3NHo0ihklddBsdsILdeVfyuZlT2H0 qn9+iyWdZK1OO1MdOhnRg0AXcwdzwwYwUXQgcr3VsY3Jk/c0q53pCEkatUSdfDmrcWhlW7nqSi3f n/YdGCkp65xqy22GaBJlczrleL/YNnCVpQkh9qy/FRO2sD+MFiClKfCA3p2d9nPjaUFwxFqog7bE 7tLQPLh6PkC+jFd+YcUk/XPUObmv684zJKewXySEb1lghgxU80rnx0fPsWNTrN8z6FUEmn0dK9E6 UlMGVdKdFP8NqGuD/FvEXLh9jvXuZazDJb/O0o1rqYJbzQgzochaHdG1HxZGdSS6rl/2NuVwIupu fVwB0jqy8H6Qo8bYILNoiz5XPVxwKO3qogWseizlO/M9AzLfMbnroPp5Eo4aZ+AIvSRzF6FfCpU5 si1j4UFN3NTSQKvbNgq1dmqDnwe3zJz+ALJoYfARgoRH/mooZkZJ47ZabHca1oVySkhFzalnJbmh LecDGNuh/Fz6+ni2EjgRJFeq0cIdXS8aeTK3i/qcK1qW3WxSvypFjIfQijIZj6pKFmT20hl5l2P3 iQSz5+uHOitF4fHZPBARPgIcnvPjSGt6XqQzOxM4c+Sh3foAtGufrGf1JLQMgXOjdQlRF1+CDuOs 6Frpw6LAmVWkxGGUuh0/jjY9uWXriB33swt8j1w/L18ZfQmeqCDPi4+w0W7kQSjWRDvFfP0Tm8p6 WHvKPTP5loeQiaQcysZ8BJBQwcOv5mhhql3XHpkp3JQFJGMoQbKjg/8rxwwXMlBGpylH4Uago/rm J7S6ytRoHbMpcKtaCOy8Ih7pp8zBiYfTmXd4rH0kjpIJot0WVzunvfODZ5OY/svj7xkbDDqcOUgf 8+HsUNCOKWjNHxZJR0Z1/xIQxFQLd1mcRICktR64w70gkae3X8FLzqoPmf4xFySgc387uHDIfHUk F3fMbri6j5W3R6lLILoDbyGFO0HEwOxYVF2kaWJ8OgXAfsBqus2BqDCchw5H4jxh8jTGbN4+h32d 4u1jNFefwAkb9Dy7OW42DYCl8Gq5gqFZ/ytxy2qUK/dUEI0fBQO2GGPYE+NNicHi89tqJsNcLZkE tDYKMYKHdb12kCIU5YMAijkiQjjIKIP3GoAh3w0vU9+SaKHjEicP+e9S28EXpQNxYqMkTTssjOnt g/jd9CBSW3W8/w9PN/yt29+nzU0mwK7k+G5hU1z/tu88jwVJOx7fQh2mP+Hx19OLCKUJgi+eSaqG 5Dlv+ZJ/3YUIvD6MZ97SDy9UceNRgt17WXVAsK5mQheVNENU2SAO5IMCDyUNVV16HV2L9uEInyR6 KunmyoY2iAXUl+qjYiw0fMyFIXfTV5fU6all5WrXp6YWAjxQIcJlkoNEvx7BjuJfr8NYPrR67tLP 2MIhtnMzkh16oDABwAUnAfKrfzrMaTVS0yeXYDlmaaTc+GAF+VlKoCWq4B4ubb5akIA0vHqrYn+P X6qtBkk6HQqY4Vy18aKugFZDkRDrRaeP3RsfO0F2CfWvwpEFNv/aD0zaxqHs4d2nwL8DxTl0/T5V MH8jjQvXHUl/Hv+RU9WEczPAkqhVNWZt3fCCNDIjxmkT3GtXmyR+XcCvz7l8Z3kQYqQb3LwSHDOY 1ub3WM5aFuWi4x9crTRE/2zUdObjLoyDE8XcQOb2TIQZJJzWZtAHRt325UePoeT/KyCv9yobDFVj sRYLIDtIxws6+g2ZumMGC03/n7mOoW/HGx5URvtWw5NYdPOTMmJIS7BYtD7RlXQWTx8c85adEqEa xY8U/lOqtgv1az6Yr4AghBVRkTVQJ/uxzM+xveghtfuzfbrKBNS1OKzYopSvHbQ0ItVbzyL/kIx1 7PsDenIl5bcZqcneSBxdJM2jZNFzJsDVJH2AeHvvUkWKFFM/hSEfTHtwRHwbQfnSG4xwttvq12dL jwdRmVyhlClWa9miTmDhioEauvQaD/silmqhTQsnG+3Aato4huV3i5lYZXVgRlgiKSsf3l9/BhDk iLt8S6eq0bGQ5XkY7P116ztUe4bS7Df1oN5cMWrjbKboTm3bodqf7JSBlmgBB89tTdHQdNb+J7Cb VqyV4cPghhbWe+xZk9/5+bO862RgQw6J6v6raE3nBhVopapG2z+77Vzf5n+ucPMgJ+NxG0R3NhvS KAeby9XI6idMj+l6l8J5IIpyzVP5dUFUd3sjk9XNY5nEaKg6CehvZH/FLzbGBIJgkeRIZCuVLzUc zhGnu6koWj0F/lSQ1k+dWZ4UPZa61DL1GH/pabQ3xejDjsY83kiuzV+pNzc9GqXiwlVnlF70Ifwm nZwu+5aTzPsvM0afKqfERxbndfu/yfJmdRMr6eF6DTnIOXpx73BcIowUzDrL5zt8N0KgBPgp4R2y 5H8cSOM1cZem44k5FMTLPIG+u16uzZ6HmnABCrHevHz+A7seKzcUjI6TBdlwyraRWGMSSR882iUL WqqZAMelSWfsF56f828gM2dhpUhs5YQBnzbeuT8OXNZHLI+8PSOUSLqzHMhoI+mvligBQhIV2Qoh kiFRf8YZSlqX27RWEJtR6RDZhiLgnXM26/FWxdwraXEsD6hBaitk9bgsnIqS17Zw0nC8bK6LXSF5 lzRaZos8erIdH5o9fGmN1NRzoilgBCcXLHwllvkoYruIBGWgOcraXxyjByYfbsCo9LYh5UXNGAMz wl8aGprKqc7JNV8u1y4/Z2VkyJK1/R6mhyOkw4Go3Dp3nDGtD1A37hWDWydBT2kinS7Q5yIIk60M rJ8k7Cv803sQT0HYzoyu9HKtI+okKl3FFPQl5ug3190Z2Y5whDBDFtWRRrfHbp9cW54XuUhW5oPQ 7fLVDhapu32ZNYC+YD0lCWcpSPrqFKYdX4gTEpiVkGU6QX30jHs7QbnmOa78z9lFdVjGot6Ll9zN MfoLlUFdD6xeD1JB9KBdFYvAomKPVQ5gY8zzFgTFywoEVjv/zEkTDFo5zScTZLbFNrZbd2YKcJNe DDp1m15HPt+uW9dwnpsWOOWa1Z2W5OyRz3wOnHL2tHlZm2UdFOAZhgYT7d4xOiOgSDQos1vay7aL 1f+pf17Y8svNSOufDiNcCOc8dYaNQI4vwkykzsoS+Kz59OavhaXoARMQ1hEPnVHRzqVxWKNcxSiO BEkc9IaF5yLmxgCKOpn81Mdmy/Cnh3NNDm9klFoAUXBfw+lW0++XHXEBuQxE1/4W3a1xBsEU2Ns9 xlU6LmMPW0bGLi+QcTlNlOit4qW74KhXI6uCN3VQxBAhvLSl+fkPRQRCjTlhX5tSbQ0LhFwL3ajM 5soO5wqGJ7Hi02IKCb+6x9P2oLyOUmExKmSNFafxNQZ7Y8rjCeP4/1VR4/FqCb9DpVKGQzBZPgPn JjFdExYZhZk2u6V4rF46d+LQd5w3TMZJs24eKsI6EiI7mETdKnGfwNw+YPyQXpkzFxvQEDmJXTH1 lS6vh2J928bsrsd5faCIZ/9DaajgQJD879/4WyH5mkwEiKoG0YjSvcnF4O73/arY3xVVRLhFmV8+ fGyKHmTVQd5zPm+m5bOVWMEBzogUJLjmHrXhGndXzs7TfRHEXEzU7kTFfdFfMgp4OwSnjtlnEzQO AYJuq4RuoKoYMvZImagpjX9JTif7nTXYauymInHe7xqWOBYw0uWALSNr0K1+vZZpPQXPDto7StMo NNYSp+soJFAkMIpZGp9sQHyT+Gq2+9RjE4ohpBeaJ7Bq1dgerqS+ZSGRFQWs4wRU3Vrnx6ESVLTU Ate/rPcMPh7DzRLBUQ9tT/nmGhLxUQNb+mRwbhIxnP2ew0sluJiZfakyd+W1dCmcxwQxwUjRwIoW 2EUq6eCxv9cdESbLXsNFfskflJbUV/QkRufj1eQnJSvZeNdzLEMR3HxihHDoITaB62zGlVa4dQ9O oGlr/Crkn5tmQ0z9OwNGagV2H/EK3wVsgpSsOJhhH0g7Gx47a3eT2j4ZaFnFAp4Q16KDZ8bPCEED qoc4cKWXLxVvat0Yjhldk+USS3jAbEgipNzO2Kidq3eoeI+D++A+lh3HXm8nMmXFWy0wBNvJXRGd GzxZSYxMs7GipYB6UgJcsaB935ImqwJHY4XufNEeoZ14MXYEpY63gO/4njm4AnVWQkb+6WpJ0JBN Nw50rmnudYHqmrswIoN/LXFYkApo6UdqF+IBQPURYP9rROjjmd5Ih8tzURxjYiu8EcI3/+il1HqD 4cbGkD3r/dk1toyMcR0DZ3MhJ5iYd3xxITeVcivcufWq8xvKloSJK5g1Sy74T0xCMSyDk+a+WkoQ jP44zdXCXwIJoE3F+ZyVWA0jkn3OzjtprpYRZ1KD16Pr590pV3Uj5w6S9L/JzCA4RLyrIp1vo2rv 12uFNGSWkHpJImMqVFWgjzl3OZ1CrggyzMwkcjT+oFSy7gTDuJdysfxwpeSBMlHO7SQ1pj4VlpRx wRVng09VcMKSTcF7uPbWOxMJu8/LhFSjkLODJtyWan+1ulvLZigyXT1FiJZTcBCWsngsWYOXZOO0 7E7mIotdkcYuiDYeC2rIqBHyYlfpepRxl39dsgQYXwQVFQAkRgbVUV/eSCawswYSBOBJVx92fS3T b2zxs5DvsqW5suCxnUHlXmpChenUIf7xzXbi1dqfYvqke2SG70NIhIIIWiHBu4UPeNOYUu7t9F9Z i0E+twrZ7XpGvfxZR3wFFWMfJ6c/IMC4hNbtXm/clfYSDx/B48YdID40pA6O3wYPH5pL/uvUDS+/ c1h9sMyo6Ndd/JQ4XkRO2hm3bUYbIOU7TsXL4l0+XTuQeBf0E/jnM//PBNiWjEjNEP+TvtfU/Ml/ Fjkvlvei6gzi2cnItl6UZLZ5mg04v5s7ujAfmqamm7J/yFTHNwd3Kvmt1xPKZuwe0c51uAYnIQ+2 6R9WTzV13tArP8XEmkH6VHhedbF59VYngLe6WWlFTZf87hUulepi5PtgDwfZm+K0gvNpspIXlUYc oSs+4f9sdnkqDwqeGDRaknkZaiiVfjemS7jIIchd36HWFYwaQylv4k1FEh3uOeRSZvxk3wvipLjd AP+VcAibjH/BP+rE01wLfJ+04lgPQiBgFOrdihKFciGMqRPqElmqHvg67ev6A/2VUm6bHw9Hio6T u1V093d2wzyy3nNVMdGHCwUlgiSKxjehCW7+Bn8lRlH6L0uXo7UCz7tio6Zflk6B4OU1EuFPz51F /eRDWl+3v4pfEZkzf86IZcaBDJqZ7Iru2fMLPQ61xY3AXhCG3fE12quGbi6257687OdwnQCpPQx8 vzOSvIrXIzycfb8qyO/izWC8glciyId0Uhz7bIovn7LQFvrUCuTruxXh/S0GvAv5Krc3tpFY2x59 teCXWT2bCQuBf5djsy4FByv2yK+7SyYR+69+XpUuVGTUHBUanqmLEQL6WvhXal7xpuzoR7VD6tB6 Ce85+5xizMGTKU0F/95jgomJjN5JYxDHn9PA6rBD4btXiOcGDLU/DP4wubHhQ+r5PUuLq6wq+Fn1 OdERtLTapl2ic9Fk8HEL8gCHRyD79a/MBKvckd89J1O9aHkAqhqnfxnvxG8+F6P+aS4K6BcWfLOl MMwEbwvZRwwaj8AqETqu9UN/lJXlrnAcyAM5UZd9JKe2fQ6ppT3v9KH1exwqktmwXS3j22xW0+73 8e+MNIqExNBZjE0q1ulnBKIzzi1iYE/MZoYIA8N+sXG2mOgzeFQGeJJDW7sjLZ0+PKxhU59g1Ve4 +CjKrWZGU+mVYB9CcUJnW9DOReyCNyGyEKkaIv6dhcpWduNQUSb0cV6Y8CLcfBynPmgubquZPeZn kk6rt33+No0o0Pceo6BOXJF9UmDneT0ftJRCkXES0P2RGP6oci2YqgdKxY+bb9HTEGixEpubnguv 1Q4G7TbfusW5mVGpeEl8/RVQMLL9mO9wpU9YmYJVUcKXRH9fQ2ynfmT1R/KZF/0UhG2HCZ9g549r ulaKW6s69IoXu/entjilizdjOo2wPx+vTgDCivO/auHZehPig0xTfPbhRNs2O67Mgf+Vn0bhu1VG sF251MxSCFxKoKVZQc+r1wkeOsNHfUD4cvOuVhtPhzXJnHaBJbFeJispPRwJQOD+22Si3YbzyJjZ xT0y8Wv/lX/NXDLmBh5mAcuy+/JC26JCjRO0iLLgk9o6SfR48GIZbJGifLvTs3QmnSpDV+7HAM+v vBwkZvbKSXWvkxQJRh/ghq1zBRwQfK98YNGaU9xnpb1hKp35xVcB6b691YZL3xPlZwsWJHu7JfXB sCr0WUZ4HOXAQ0DjX2PTFDxMve/9r6Nw7Xstx4EaoPdEm5gHeIW+C8RlVsHWXEMGopAGvk6SjI9G Qvp/fYp90wPj0oRFrb+zNDf7NG9kQZXOCIt2BqLv7irKPGo0V9Kurn4v2a/fqw9DGfWVmoNkr1/L HaGDijgPK4ul4QH2/mZF9wjN1UaapasQKMebkpGdlTPrEhjBYKUY7ubNP1Rs1fFCAFESSz8ObscR ezt2v+VmC+RXeHkNnzUxm0bTn3owg2nGmd9kJLyXQZDvn8uE7oRNDA2i/V9KPFdj69nQpR/SZUBI pzNDC/RW9Wfoy4pv52CGyk8ZoerDtTFnhz6PhdF00w7QumWUlj34d3/HpPKxTqc4xZcQBdknDAx+ gFvA3QItKSnuhO3Pd+dR5QjpwxOtCWNRpF6qtByq4g9/MYcgpuZBTuuGsydYW82Ii3Mr3rUepOJt qxsukqa5PoW4ooO+qn39I8cEzJYbK6Ju/wnfeyXOIOmyZQp7b+L3wHwYTRutBYKMhSz6g2uyB65e vBjEjK+znoNclv02VucKmNaY48pZ6tRAjqsk9o8ENTA/1VJOEJVZwq8nztGkt9cuUsE5pjWevPKG 7/lAa92DEXvjRIlUqGNE+YktexCAx4pE6e6AsWE5SwzVDRYpdWWCJu0R5k7RW8tvpL8cC/QIdmB/ ZprCLGZWff9QwIGSsLfb9bg/HG7isn8z4Y0IsbIEdefEunWkCi4KH9Ap7fLNT9EpGG31JJJ5oLVD UGHggmQqxKLq37NbSHxUaURTtPGHkaDh+RRvcDNlijbb369GE8lBymGoyTVIQ1kUJiVZ5AgKaidC 7DXrQ9c+7dUVpKpsQ7cCXJQ0ZU01e9ynzZaWf50a2bqD+oQyw3MomvWdaI2F97lK8CRkoUDUtj/t QcxGeXb7k9bXV2yz08Dr5k+6bzVGrIy0yjWI/GAGqTsAvi92A9EP//gMJlDyjYsi4m3mcYdAH+Jd 3xeLM42TSkrTB06VYH8t396BBHZ18u80mqdVMTanmMjiuJMUVeTAkZU3wvtfQmWth/lx655fkHA0 95w4yLJHDfYmiJM8JTJZLqwYO/hUL2ZTdz4A6WAhiVB9H/k81lJMJ0EtB/iWVJCwUy1rDBgwiVBs tGRxwTICm0rKRO7R/M1lOFPg5gKNMcy59vJqZTo7BK3gDItD3nWybqhNA9TZ0x1DxNJcwaD9eNEY OGFVcu8S3DhQ/dvNTdz584GtfjuHZttdudheLgI5tqKFB2G9Boyv90wXvz+crIyNDRoJeagM4J1I BNYda1zW9lxlqvtEYyf9Fs+45AkCyjjpSG6c+SG+1fpOEJi6keTeu99zdJ26fjtI73h+Rdup7iUQ Csf2PBEdx/i5PruLEsaOQIRxM/roQSJBpLAaOLeP/CfLY+wwuUJz/uGGauYFMWLItFN/jp9WKBgi snaVKQM3hWcdrJ39HvTbLGQOjh/oCWMSKSLRXAdjUQq1xImPPCKFfe5pBTw6sUvB0xVjFYWcACuU uwnw+bjxutai1yQtf+BrFIO9qgCxxOWqQUt7YKQV3EBdqV7HmgR5wkjCgvFEa52vnrJfRYriWU67 HdEhVQBHTs3IHXCx+QEGj9dH6p8NkgY1gU9hgsRBGRDNFnSkUYIE3DAFG9zRM9tTfotevRxF2nKa YpAboyZVzj+erxwtanwaQ4iiwxMoeHeDJwJIej8EqxyBHZxRKBoExf0DAhwkN6ke8yZEVuZ70+jn QNwcA4PW9UTHoOusU3fenUElw/WK5HvOneDwvpTIUlgMk44V/JH50Uw4myOzkzind/TfEJaTMYW3 impcxhQ1x4o2jWFrjvIhxhdai9PuNK+xJMtqb0fD7rxJ0ZHDUz723P52yXleEJna9NUFEblUdkF9 lldOj5qDtRJDU2bHGTT9oXvXF/ChqTuXl+K/CTuYLy+ud9GxEhv5bvLUSaP9NHQfOZ5qa4aqYhb7 XnNZZevcIqVi6Z6g0f2TU88ZFAjWqZGhXtg8BdYN2Z2dA6AjHFgjUXCBvoRrI627X1B6U//Gkogs Zw1LJUlo9PdyFApqkpDfJ54lTKkyUBxWmjufwJSczK+35gyF6iRcggsmWJGwlJ7X9ErI8SkK3UlV IWWyUbp9+j+dBrTKMmtG1lE9bq77yTwD0lUxyslx/sBCpHX5QL7DJJtZj8hu2ul+dWRCQ5xpmec+ 06WDRlSSWoQ+NTsldqP6QF5sojlMgW/X1zg1aInh3rMQ6jaBwRXZkxnsTqyeS2/oD6UPjY/Tb2V5 tGHltIUzpD77PeXBachjiSsIOe0SOtC1k/H7hl8eYajw1V3LIOWbVqoErXhftrgngLnYviiHPYeU 02G8GBqoh1Ae/xmMgH0qDOYBI88zr061vGU12RcF/V82xBHLmsPM74zsi+RH3da4NAehjOC8CJZR 9T2jV4TnkHO2L1kAw95dlKO6Us+GqTAhOFoSthC6DmK8K2ePQDVWywaBQgBb8nKPpYLx+7aed9C/ zHLHwelbAenH1KkjpvzK7aQ3XPCsvW5CjtqEFlWKBmZ7KvRydYMhz8JuX+5GqrzRClir6TEevA7o eg1OQMJGeXE2jw16JWJcpet6QZB2SyGXVCt63LC6zGH6BGYmcCKW8mx82yxtxtrRNGb0m1o1FW4K Ks9T1Kg7ZAk3u7uIjksaHAJeK13nmHz+NK5lfvT5JjmE3SquNt2TGaof1Evz5tLzKgztK8j8+JE3 cia5L1JVayj+Mwpc5MIWGGKjvMW/dzSVQ8RHY4fcMrKnAhdFM1wkIOXOJcqyD6cetoO8EOVrZkFW Wg4hUcSARr+R3WKCNRZrF3ncAQMWhJhPiqqymjtErtr2o7xtSaP/Wdko3lX9pcxVMa6ZwjV0WJVi /+yeu28lTPzkbtSpZuMc5JaIcZ3Wd5JiWjfsSIFaVgEbE3u9sRl2slzanuB6OVWQddNN3LauyqbU KLsKkv6eNTRxKN6n4je+tawF+i62rLK3PcztF8JVDZBdjDJdudIDloBvKCjNTtSrNQbmQLj6OL7m elmL011NOjf3NydnVKZbjYaGQvFm9KvwLQoT2UjPDsoFD4vV0aDIaNDSK0lEU/GIjfi++eCcAawS PTrV0tl6YPJ2oL29UKRnaaB0wpc9B+f+axF3Au/cwzxlqP42sxDLn0l7GfQqnJM1pErRVTcqOCoZ eId0Y7Dn6aE6cult96bIpreenYusQnRH5VVvaAHw+THRAd9+qaK/sd9F8vM6nEySMK40VESp/bF7 aHPgR545e/jXGrXONG1K8TvBu27VxWhY5cJUAfXWfEfKIQy4Um/z+EtTTudW7qNOmun94PiNA4ac A/Ts+FqJaW12eRL+fejxF9kFlby3B6CfSG5LMQzC9tfZja5qWm1uLkMqMzUbYiKvxk+9Hm1zNb+D yW4rlBUULvr66SRWX/1OQwuZs2gUo8PL/OAjoZSD0DzvXq3TB//5AbpAxM8kQ8Z9hl7MXiDtySx3 pJasOOvMeKZzu3SwLGGlYRwUiG4uyJxJ5H+kdpEvDrsUl2p9ZwhvfMDxKrTYrKoylXXp+n7neXMt bFRor/Pr1SnlVroHHa5dYzTlbzx0QgqXi9UxYqZEeadYe2gYM9tL5133N1m5jW3+7a/Yvd+Oad3h P2tHAHRTxVlY+7fCu1Wq7F2dnGIpwaHbrrIJPqPjz/V7ckyHGFA/C8otISzEhfyhuEfYb4g2/grb qvpjuXZCQiRJ2o2wGsl1WjtEe53AaYM4B5oihiRdV/y39WVu3283PNhq8dprlJwGwpGuuzCxyk33 of23fJybjqbSANdrIEtjQi0Z+yHGZhaHLzgrwp+Mq2E8wu4+28QOQ0+fMo+Puhrrnea1AoNKcne9 O0ZSVUKGuRRgDpqyT0KpatS+vGdll2b1WMHIluzI4oyDPkU1Wd0f16W51kgwyA6BfH6j3ru1vo74 2OXm8BfBvjEz0Os0QQdftzKbqtG1/0C5HhIhfcqcpyDh9/wr7Okd0t3LwQBS8iBO/sYG4zqt8V8y SWA4vISDpoD1u6sFiEHyteHkrafkzr3jJ93VUGm8XeBp3tIknllB1KClsolFXjKpWKhzuJXljfbr w2zBFp9LzpwNayEQfHgN1FJbaTm2FJjkvfnmr4hPAhitxizCPgJgH8/UXTADz6H6P2PDXL47jz4O oBua0UDQYjaSQL+2KMPCqSAOw4BRkIE+zdp+qEuzEBaSMwU2Y3mcf6SxEdqPW8kOS3mK8RtM0ASl E48AAAbCZOQVSxPm5erzZOfZ81YnKjGRgPzkGuhTAmgscF68pl2vsKqKN7vg50pkC0MZfqZp/F+c P/glne6OPfvi7LBwvvBMUMDCN/qHQyltYL5BDnB/uuUQ4/0DJlqzWMmQHGJ5C3uUSXyxIf/CWTtG p1BEEbRz0xFuSIWzb/n139nV/MFzIWzIun4n0Qxh+7tRYMhaHVhMe+d1V7QVlXqQ71/c50bPV94A r9tR4Mbl93Ko45CvnjA4BKr5blDzSLmPA36h6MRqvVftElCVXw85dvXNxYatv4hsmEt/0z89niIW MjgWI3EOGPRb/e8t+Uyo6snzFaJQ32ucPL2b6cQqFdnJquWLGwKHfGiNLNSAxuY99NslGfahxvWm w/NgUg0qeaJ1iKf4RHEU5D4Szb0dLYK5y9O1z45QsJ5FxRkvzcc+XQ+c26PuXBcaKC/J0Rqrsxj9 yjBOoiZRdvAqzTWt0BnR+zcC9ksmlIs+5QVIe/3hPCahygoW9XJY9a07tbDi7zbJuVPr7Da5k3wM 1K2ZZ0wmbUHiHeggXTDbPQZ+bAIsMKwLhmz6V2qRj6ra+KGPieyPcwR7/c3QOrQrI2UoESCtZWGP W+7fM3QwG6czef4T1EkKbR0WjJBO0ixreSYb/+3S5J0IkESWops4wOtJt6nJOSSFdyfrfRUGD1dc pQ6Zeg2k+1EDUicNNOQv/75mKbJ5OGetihKJoHuejU9cw75ZiQLtUEHEfRU0vrEHRg9a8TBwM6Gg hOtNqWkEl0D3cm2sc2oYVlweLUTDuJUVu30R1zMut/Lpm/X8s84nkyvMhys7YP/y73YROL71YIy3 qvdWW3OWRtk66iuJ575vFqyOWnzDc5StBwaaz0Nn7IwS5oTQZnxCuDF+oCFiX+qJ0SBfhdpcwvEW tvhZgnFIDPPexKrShe6lsGAQcc0voR1cni8P4dd8hKqhIXKDfwCipDxMCVVlTeDCAB9aW/auTjbK apX/+vx7Ny7dB21fmgOSoV/Syqu1b+5hMrgWZWXJ02ntoxWc1DJZ5QlYldQtvxYPxuQakEdgarFS bsF0sbHy/c26WSqz1+evVBq7JC8/0ECCtW5snXxKWZcKmZOpH+WkLRx426ZbMoy/AHJuNwyFLqtR LrvdA/g7qVwc05BFZ87a7DhZbZ/GHJuH8IBgyYWDbgpyAaqoayZJo/guTNDBpFq4C1doIhYYAdgw aRnZiHWVzHAUOX9OdJCkYBrRRWr34adv51mU7yFnF3VbA6Hk4jFLHxkDpIPjSwW+7cbm0+Itw+eg exn/e/Z9VirSgGWZqgFWmoev/X06rSft/ZE9Dr6e83/7OsuN9j2iv6+JjIyOAKXjtH3ZH8LtSpLa AZqxCjgLhW5QcMvwjciFigFm16FP6J/3am5dlQkKa1NefkwA4qxWWRJa5njSLp3Uum6SvfsLUaJL 0D01bf+qWdb6aN/sx1sLHL6Ui3Z+gxyGeZwLlfecJPoKITtdzXtZnXf7TbCP6v2Ufqui5O2z9Uq2 WqScpD3pyyaTlgQkptwWYQzjn6ZUjHG/JQqWkR06Rxojoh1zSWjboCKdyKRPIYYgMS+iAxFOjuh7 KikZQtYnQjNm+JHT51mB8S4XqRxZQqQlKRev6MUIJYkdR/2n8vXxLZICVyEoVCMZk1A8GXVL4U4K VLRObw0AsIiWVEVIG7GN6QpUtUiBGYKQ2YyJJ5Q9gEC5XLO1wrz7LiLTfRrwuoPCtEqwbfWxMqD6 iY0P8S2+WZaI+uNJYH7RcSpZB+urpzSrbT+/5a3rOaqS2tsBEMLJ1UUMsKgoAlbXM1h2N25cfEXe ufUPSnpoKLNIOcnvMvjmCZ+98gmfeXIxYxBkZd5CTNk9POZmmew9rTk/IITg9rUBuHxyAr3P1bbp iEzlhQNv7NYEJGf7nLNr/ixnSxMwCO6KV2IZHi+fcL6lVIr2pPMJpUaeBz8ohQMv4qj2HC5Nwz+q gK+5HM2vMtRA4/lYUiTWqw4e4zPUPnEVxDmHXqn718WKecoYsMJL0Y3fePMHZ4wpPvx2pmuSdlfx JnOfX8Bx80qtIRfomKq6JN5yiYf11H1fAJVtAHYu4hTcM0p5WVYhkptNOQWX5TwUFcRkAtVA6V5x rlGvL9bauB7iX6Hgw+1hTCuR+yV6fOHCAdoGDMn4OPNHR1c+aQ/ZTeKRLc3kl05wfuGgdHaAEwrR oDQG6DNtekOAHGIKUNPZ7xH3g72iYSNXjmlTwBdA/SXFwAkrhrveRTyWkCP1KhcxVlSodK1ujl5+ TqLFVUugBzLQWa+Z7AMASyU18BC8sGzFPjVTqULBn8gebKqfXyPWnmBInM5ci71SONPloeoszjLS pB00/oQH8WdYPmL1wU+ykMFpv80fIqB4lZfKcPQLpdTZ44SB3ZfOOAaatMZjGYDkDll5g8sZXpC7 2z4k2S00FxQAN7eTrPuLeC+Jp4CWIm12BCb8I8C2iPNa0ouBjAmRnn/GOAuWuoUbzJWOUoLHnhQT VdR10kAwEcpaZeER5flZfsiAxQsTPhIKOdJm/fkKLlJ4fTCaIpMxRJ8ONUeJkGZajErdbQXmWQsh e3aaUpXAEzyrBdJirVZFmEJpbb9mD/qQovHRXAAHl69JpgfqH3UB0zcWavqxXwu1EGMFIuOKbzPW uA38xeLG/HmRf2Vo/TKuaybfPXWkGaqaty0yGNPWcJ1GI5VPIIvjBOtTxwsO3h2ia7hL/IEHDLdx hso3Zx6wAKqIRhFZWr+mpl8pcPpZ5O4Saeye9JERoAODrQqKtW8qGSjDumpP8TTqLz8qUOuz93eR 4YPHQt5/28K99YPKYyQVdMNWotrxzQcAmKLKCWeglO3ZEl0SCa4FVBU3jkzV6DKhK8mOM80S96kC /oDQdJrDG/Fa0qOwP8gkVmiwLJmnDNnu1Jck/QTk4kqcbX7HhIdzh5NV/y9jaTckCgiDzbkJUFic UTVHHW5MsmP859gws0AD2mla58GF/gu8kolpXpIdyUlv9pntiH5UcTUrasopdHgfUrGzOIgyIw83 Mh3CdHgusvnFdHz5N+BuxzNHlX8nVq84xKouao/jlisqW38FopuiWneknj8RU2bBPQaNk+G7PACY SNikRmkIWTLBz8bYwaK4nafZ7rw4oSP52R4+f/Rxo5Xk7bIcNODhr3+lJROO0b9UIWW2MZCNjLNK D2pJnfy9bYJNCEyL4yvPd9XcX0sVzNb7Z7IQo+JNtXkW4Ww4KsUi3UxnjUtWtPtdyfXbk18KnnV6 s7csB07L0RvqbRNqOpTv4Xo0nvX3N4I4XOEF53lxdEGdppv8rowGtmGP4S4q5Q9UK2+rzD/nnAuS Qm+ciqpVFS4EPj/WZzWUGJM+DtwyUX0hd+vZu6VRLUWmaFry9xzKUN01WcYBv84dOBmUEC+IRDYr rS8D/ZUOGnAfkrlKZQtIPacQ0Q+yUoOzCTtDpqlGdGVQtlP1ET8yN1BdDsftW98Con+JGNUNG/DW IcOkT2h74VHAd15WtDk28qogca0e86MEMyeQ+pw3N2WUQbA7h68/gIDAyFuVtfE7wOTMtbyz/QAL jQHMEbYJG2ev8eUCiDpwNk4TmFPbzwpFz8GSTV+f2Q7FbUJl7Xrhq6JumCVGOl1sob7TaBiQPbPt 0duDsnpJ2jlP1yPsoOFkCcVMypmfBAAU9oHPMY52P7Q1BlqhlH65ubcZVFI3C94dDE4BJUjH0W0P mkVuDGWi31sQ9aFdFAf/AZnndQ7E5GHlJNlNTtAv704N6FFX+8c0+5KDNvJZVVfiDYyNDTC5vsST by7SfNpQcL7jIBIgZOZBt/3vNVhq2QyDtVf88TBwRmVyghjWXF90V5m7HBeIwZBdyY+SUEYo8Vah 28wpOysFmEf+O4/kotGHZ6szrev6E70SqcIqtOu40/qt7OttHW81ZC7/Iyo/L2Ne8HvV2Rnixg75 fvV6D0F7fNpTzaWPNdgUcYyBiex7PhDnviw7Da0CRn8v1BM0Tj/OStrjVS4ITShpta8FsZr3EGAO QHLnW2+O+/T0baRe5MOl4gWBVZip1d/+SW7069bebsVIBT3K2j93G7AKB5g4O20mWdQu1X4pTAqQ gkMmc7Desls9Si9BnSqfJevWp3WlD9HHnytqhavvQClgTMtQZaapztMZ+FbMHDGNyb5meVzor7pO 6iK+R4oOuMilt9uTngKbBGlpeWCcHofbLr7PV1nVh7+l6bpXjlAUF8qPN2MddJBdUiZ/tE316T1/ OBjx7+4tjVsWChFsIQRAhdPDzJ4QpCHHll1UPRB2/9G7KYpaNiGBoJJoplQkPbNdFkWSmmnlEv4K PcgC9SP+OhVJIczxmxWlcHud8d/TN4l8LnishMvBrn/rFkDbwRSn9fiqpWJUx2mYUsm8vcYHSnz9 wo42+7DKo4FnuiLW7HMAGzC81WM7vFn3aBj8PHZZm93iFD0X6MFIvFpDj0HwmauC/xXskaX5yK5R 9A8yiG5PhefatHm00BkEz6WlMeCFnUSNUe/AOTd+/AFUFUPlFNpQHMfXCnARuSdDTzyju2UClf+l mDKcG8G3W8lo91kF+2eaEqIn7G3aUZ7ovABCEeak3Rta8DRdH5xQE2ZAzDbIXXo1yv/BliEMoZaA hF/+0RrA4UZxAWYPDlnbRChescFVjj3/utYHk7bbAnE7NjI3vw1QF/iTS6L7RMVb28EVf1Ql62bG 7SEnWDa6v8lDHicmOc+owwrdjc//P6PFnmeINbsy15hLrNLTr6Tni3Gxtn19zJ5Ze/g3CN8dknS6 rLx051j190K1ilptryuTSGSsyZYlMuLxbHFfY6ugGQ0lGOOZK9oChsbi2vQovEwdq1Y4VwX18jsT 7IH5URxqNObH4HLLgWYw+E8WKOzJDCKwQMkC5sSQ6sDz9WLKcrCD7C/6wQJ+U87EOi4y0lQ4QJF+ PYZfKr/zrPNEY3DJN98mUMtBonwbdgAQqTBnErWRlAy8PGfqGcLs21NAbJt7AlZVMrynBs+B4s0H fNoWDfUJVjwzFeLxvKA0i3FO1FhyAp5b9eLI25FOwAhQ2EOzniwPwhMQau5DysLncBKROxqRwgTw 5d108OHbiL0RGspPKHsTaGp+hk6jW8N2iA1gEopQSSiv9pmzCV0uGSD8TQ3GpPLXx/a4ASOFcvi2 nsZ5KK01ZzxRTJoJkYuutu6k2OC/8gYmnUP+wwu+fHYC49LDj9dEh6HG+wBMm7A26a3LO8NSel18 e/egUSYy+PjAzp1b4wWsFWonRoH4DZ/E0ZtFZGArDpuf2kR0J8T3G6YjYV1T1HPC+1kkUUoPsVYg dMoqpHYyZJvGeIGkFLMNx5/lxSjivGMo3mkbApEyOBU3+18cGDtQAOi52aeTSZYmzxklco1DbJZ2 PDOPAXH54gOvfL/DDNx4OWumSSwejtwLMAw8bk73ZuSa+EgkpZIOP0jfLFQHyP3pCCTKroqIPMc2 EUGo/HZrIPGwyNpYZXRy4DWNa7zY89+04DVJET0S2/MqK1maeJtuECa+n/NhO6vZMAT9jls3T+6o 672hIBNDAn8STLCXBRUdiE+j58OG6BSyBXFkaHBzaxug5N3oYQopSqFVRctwz2J5S5JYvAr59mMH 4fiMKHQ+1RKRXClPhI0rUcPi/rY2Fkr7C56cfNXDBWTjOffagd6nGfTYu4foxPAw2391aAkuvFFH g5n6tHuDUzz2vin/43L+7rZx4n6zJrsnXmGBLD/papbI5RPJkS1CwF95L4HRLwruOaM7VhOhtyxJ SuMj82HVuZ7RmcVgLaaKznZ6R+JIrYRXYTI1Jp2f7bACSm7QGw6GrqLpLHk9XMmuqUy4LSw/u2oq 7N8wgTUUlt9AFIAQZFo0GxA17+4H8EAQb7dhbiyBVs9JuHv2eZRBnP3ZykE8e3I1rjpOPUvga9gl TwEHLrPTCa59rcztHc2LhKWontlcXh267Sky5XSJ4Z4gnwmyoAV5H8ttscGGOLiLIPzVf3ar8/C2 buLvMNvC97Bd3OgodeA4Y4EsFIa/wXVc7MfeIt97JdITjQhADwMfL5SF+ygFB5bAX5SneLENUSYS VuwUpdq2+dCtDAYDOntQ7ER3qpWM3BNj+uEDxc4J7YazXSW1O9kOMnbY1otRb9HPf6nHJm9asubL BuEbHm2+MfE8NUmZLrIu0DidIyMBXXD+j4irTEeP7ggpQ02ZKlPbwJw1yywU6uDXmrE48+jO0Whn O+vM4gUn1uOGArv5uuXHze9VYxRqc1TmgfD5YLiK1Q5ii9vmfKyXcvnhakEUGTX1gxL0WuHk6Fmp mAZbVz7ijkkq/Wo9WTfZp61DBAk18AhrgabS3BCHC/WKmTcY4f91spOgF2e9Rxuls18WfZavn6yq 3guX7aDdocVw8UD91mFc7OF1RH/TbIaXFugJtPsxdCgWgra24oZoGTz6R6sHsojmavCBcH4rWMsI OBMr3OOfPtMGg8uZ2KViXgeFpzG14AzQG4lEZu0dDFEN76IWwcuFaUDrAlu59LuaA+Xl7UlviV+O iwlneA7Ic21uOXBNUzLYMJ/VzZ+KrKsqAuFxsaIn/28tNMrUPBcKtvB9I3127/4iW53yjc1UKfc1 ULj5K2sgrIOZ6iLEjF2z4Vjevy0ROc1S0WXaSyeTRBaxzSeA2dwg1RJwleN+pAv3M/FGnD32ciDQ 51wXRxu54V2vRR/DpHQoS38XFcAptLPUvYUtLWZp/GgVVA7Vc3kfG/3LjOl1o19qYrKe/AhOaclu ogdv6j+kJHsT7Rd+YS2XwMzKVxVIAJXy+VS2FjPCCr+cRYQo7/iSI+/Al+pX1+G4eChnnMxBC+Qp JbXs7yHvCw2D2twYd4/7DA97P/JaM+R55IHb1jHm/MFPrfZW5seBiN2xRDV1TpjGxTFo2xMuMNlx L6VsXw+h3U6mLA4liZZJCCPIa1MmqjjrWbtM6e+EyWyDAcl60hBy+qOx+0jKGt9n6H6gVXhFgz2k WANlvU4osNTcKvtTVHO4naeEk0qOFucuBvBMBBICeQIrpfDzh7TPhR/zYtdqk/cO+4Eo4gKliwxT qo9czfCMD138ZZg1qzONcmIubbF6vni61eP2o0BZABRqdLVCWBMItP4D7UCxD6UZGRoB1hV/Px68 HmwVwnHadIl57XU3hxzqJbL8nFTOBXAJssME13hXmRT68mrdeX8XBSsw2AMZpJhZjD1yIacq0bdz peHwBImUm3C1mYszi43nrNA9dSuieWqOx4MToT8zZEqqQ+3RhE8yN2qz+LG9j9gf4Yi32erDU2ai p5nqDxtb3o7q7nf/Cd8qTTolNkSBRWzb0jRaHqCBStQFPPBPfRclbvF8spAYLcHxoQumLkToHvpP C5+Gz7M1y3az+g0/BQ9b5Gh26vIFvmE+/RpVIJqZeAKT8zYPpjKhumrVDopHNvYrX45BZgK/TE19 EnK/9Gdhjl/xlRsuljKdDUfgzp9XqTCK/v5Oalia7AD7iRmZYxyr9VEzmqwIyHDyRrFKucTz8UON wRUoDss5FTJxMxgNtuOtPcOGFIAbfNTqLlKcFV6zpE//ns+MtpryfTF4dv7KyCAsSXMf0LdmPLnZ 2dG6hWceCRT031LTaqGnTVmMYqMoN3rsOD+hlgs5HREyiEuv+067J6cC5JPi0e9stNEhrJVezAIZ 932SPzdB+XHv4axW0YKNmgNj8TDg3zZ+Af9HT707ngdn61W+AYC8S7Zd7m9iIGAiTVw3+fV5PPpA tEb2E+UTr2+wBHEZejYplq7QvIanGlaiEyozKxlmpxnGP/8O7othb/31bWMaihbdMiCd+bw6qczl XjH+ij7RZzIciYyTm7rLrseDchKQOcPv5VKWUqX3s/O48qJGwy+Xt5ntm3fwtZEyXhBLJzD6LG+c EW7VYGquPIUWKu/9dkzp+dlI9704QRYi0oBuffVxFLuywPXyOQrnAN3gSssp1Q/rnaIlUBw5uJYY Id+J64DQ8vNX9nGpkbjQeX7V39krLIsOK8b6YebZBWy5ZJUe1QC+Zj1kiV9q5u5S9ubAaMy+LM/m Acz0BPxojdK6+u6bXA1ClAjwyNHjayNY5aksPa7Czu+DUZZZ16YfxN3a+Dx8QOhf/4m8k+4HHoHO 5Z9N2bUQZv0jZB4c12TqW0pxL/RLJPumlj7KeCuNUTOhPapcw/nSr88XtFmduwXx5ITIh2BA+dTp W7dBLbXKj75/XwcWevLoiVk1FQwZAI6xj0jENIGVqWs/MzVuTkMClGtzcDAaPaUwIg01PI1LLHPE BgPVojHQKNdsMsfYkw5Oniqx6wcteG77KqmRDnFHhFeCXQfqYmEwT04GS7oudc161DTanNOm4ad4 lGPOv7moQhRavRzDoBv9oLWcJbJYTKSqxhOerbGp2LiaRTrsmYLfFSmjfkiFhMLbMYXYygGFo4zB cyCyk7QQkFhHxCocLiBzR7YHZJXYt0atGvvnHfio12nqLyL9fGH4C93HS+Xb65p8SEZLUvmHv1gL FiLQduk7AQnECcFNMUhKbwtED225Q58qvE5Y7ao/wf2fJDD0FVMcsXnCFH1099BQA8hXM4NlviT3 Ye1ZIqQTIQrSOCwHx/+bP2Ln/71wbTqsN7APjo0Kl4NlB5abIhv1pA8pI40Nw2rc3KlCHCpCaoEe lT//nUEfCqKlmMHH0OQ8arA74x7jighvLIR6XwDnwigV7AB2jWU21Thp2MHbiJFUTjyKTiU0hnXW NksYO7EepFXKfpNu3kUSE+TQX5RzDbCOmkRqo2AyUWMink71cLYrwMv0Y6WEWGio6mDOgmZCfGcH xL32/hJOqu8Wom7yFwNZPiSzUFDKfaiHLtcIMkKOxhBHWhXbHezoYQ7ELbxjNcjI15yAqJYWf4SH GWioLT3sLEH+dAeWsmdI0d90wDWv9PnGY354dxFzgDpDX33vtYP2dXdtfKIOMeiFnKg96s6miO4U oZulqZ7eZ40qKkQ9AnxGwwm4YfY1qZAqclPGWow3FxerRpFxcanjCbDY5rA/Ls4NCaEw2eCmGC3s JMtQiBcBVVzTbadEafJv0ZN9uMevtXgSpOJFM1qymTTPfIDXpCmdGjEtUTVtOHu/8/4pNIvWUdOb 76rOByfF/N82sYMltaCpCd0IMSjloPIb3jwjYwtlYaYEzEu0Xoap0cLf3Q195+0a0+FQeKGcw8ER L2/AqUsdRDlX+pDe3EaYguQGOWgYorJPzfooy3IORmxBeR+dN9lrOt+fUzJg0ic3ev+qh/ICPZ8x qcWcrnKSaZU/oYHJRlSj3uQDOn9Oz2IWWk1yqD49/XfNgAHcyPSoxhVVJ3eXnuD+tdcQPzal/5ab Gd0HnHXM6yI6dI3ZkGjdtn1WPs/DQAznVbzEiCRPR9iHOKrK1Rur2AD75gERRW7PZ0z6g4hNRL9q 26wK+UPEBVOgwxaVddZC3cncq8uHNhpdhcn71Tl7OHoT6dK8zFh3dKXd0uqNOaOSGp9hMHFYPBvQ 7AcJXC5zVRMuuHv4KxLev9ViG78DHsHP2HLxKIcJrcMmAVH98IxhBT0R0ccvK9mRtrmU+dzcU2UN VhN9WZ5tLxsTsVMNcMeMGpu+0Q3DsiViR6kaVjC7HX5fNWdOn1k99CX6NMSLDStrct7+QEYBSesi q50XNC3CUDD2zfTWgRcWPywS5uN27Wr2cRxIqGmLLgH7N71t+qDSDRE006hKOp4hWXZvtzmHUC+v MuFtO7FGHMpMHCRrLAmJaliWUSGGVhnr/xsR8spSQ/+5QcFsjewX6HdbcVRaJCubgbTwN4FoKBYO lnpXv7RrQlzhyXdDznBajDzdVl/cAWjaUYHTKJyex+MrqW7O40Jyy2ToxLzph8h9Eo7Ngnf2yZMD eh3NpVCYckh4UpOOpqwU9iSpCJbbqr8E4iadc2MppMtG1t8OlsSsx7BZc/1fv+tsZEY9cktbvxWf o2o6VQou6orrFK4C15r4YelyZAEgQ9OQfHLy4dsATBHaHRHV/44BJ5GGTEsLdure3aKffFgeawl1 /t6WRYMoLdSRrrh0GfmKOaQUE2D5uoPLncwbSzIIJZYnjSksiWyhQDnBE1SSu4JDHhOeNB69m9yZ ywESWsb4F7lugrdQAUd4BzsiF1n12dbDlx+fZ00F819iT6aKRf4JwJiH1wftMFNJrmHjHz1VbTsx dve+0LRYxbfwbVWo1usUmXwd4l9RSRto9K5Qqo/SfBjk34cNNc1t1WpuRrqZ7tW48L4N3WzOFGkI lvsIroyLwyz2y/46kKDO0cLuTodLTpjOVMzxRTR99ypVLpCVc0xieqPToYJI8Ld+i/A65xGGjiX0 8W3lvg28QRxFbNQtzZtRYQriAtO/QBUAYOdkkp+kq5F9c/EcP71zQUG2BOskdMosr7hL0D/Umr2I 9N1sr1bn+/XvfvkMkslVvthEPPgsx4Sgrb5lcH5wWOxJgbYAnlQR3w/eTdnbBls5F/CW35EcCGqW vSQ6LvFPe4hlIs/rfV1LlDQ4+NrOd+nQZ2uTwK3uCM0/OODnHJlWFTgH2Ft/JsQFpUCCS6mQTgvt rcLE+zDEoGeeFLZzesD5VoPZS85YK/OjiKvtj66Uh1h/aVGanLu2mRMEPN6R/9v53oGJ2gcY7HY4 sMbvFz4ZGmB4YLAZ0hod5u29jtBOCXOzMGoYxsP2LQVgfaec+ZmeWlYBmUPFGHmr6rGG+x3kShYz tlih7BJJ7OEy0fpUnhLxxgzO3N7ez4KcIMw1SZ9fTt851uauVIFBMbePraBCF2TYd1aibGqnQZos lTITOsBlD6oyVUDPFeQ17qD2u13+GEXY2dpfhXGsQOayyp9mfz/CHKU8F07W08RXGC+OXoQB2Xh9 HThF3eVtTgzrY+82QvlHLFv/19UCVCMA8M2zSh6VrICXfhpUIhDoL5+0IlxGD8jXRgJ7XA4lNDS1 ofXMHsRuio2QTd3wrbS27K0P3aLptn1dKyBLSWOGH9Liklfv7cystXBKQusOUAIuWeSP13QjHcfU oFvPLgoWfWpKkaFO8eYn4atEd3WYD5h+RSL2POYK2GnGMMXxG6WnqwAR+botVcw+jYyxtik6/d9t AJLjM+jpS5xYovVJJM8QZSrkeP5N1rOkIMiuo7fBbGZ5J7bBfmZr/spNTYFCDIZWOpl6D9BLSg8b s7mwL2ytSPX2N4q4gifSfUuVC99tvd7kFEMZY7ammgD2iSyszp/NneFKewE/npw4dzEi+U2J0KJY 7Bpm9bEMiFZSM7GtmHpUPEuF0eV7blU0QL9EB3HWSxFFE+zotfpdaD2EEBU/lXBYCv71bIyLPfuj pd6kqd67vd6WtWxWahMp/ZroOjnHDDv+vfVa66FUZ3RTUw8bbMX7aBtdsqhIT6RUzJ6+yv3KnLb4 afupsXHwVedUnUB+fL7F9Kv6yPKTVUvKG88bIW1iW6/NQO00aaHwmM7km9YGMGcvBWVa3NjK5plA zs4ihY+8RlkkWgM2Wop8oajAO42IeS1MMU3SRiiDARgKs2AMiks/wpUg/g7MwMEqfJYRBnYB81ft FueHxWjzbi3euEdwZh3aSP6PkQbk5fyLYmimszk6lpc+4+3MW8aO/iZXI2zPhUNnkZFa87mFfbep L1DJQbBhHYpSwqDE3/r2qmh1tCOW4nOEAupALK8bgefDgk5zc+ekzlJb359x9eKC3aqU3AFJtRNq gR4INnUE3Lejv1uvyY2jNg2ro1a60ZugkQ7L5TKMCBNHRq1ddD2ltnVMQDrlR9DZkH1sfzQ8Cnie 2gnqyENhaBca9osJDn7Rex/q8rknW7Ys7NsGE/wpWwJpjf/ZJhGj0+2AtVsElZmzph0cVbYSvhCi 9FP1LVwjFrZHCT4XBl1Yq5Z+Q+5hw3fWhCMciF1v+KCNdMuD0dY11BojfEoHeHyVzLGD42B34UPS 68yneUn1nc3DdxBGu89kFMFdX5WUyhkqTeYVTBzkFZ7Bxf9s+kpRhuHT2oCtEAQQY3Ok/2SmIHfY poouVxv4FtQQbCH7wOvB9BvX6adHtOmD1V9chmHTOM8lKFmbGPq02HIrMF0mp6Aj/3HAm/coNnb3 rF0yxQDfyRlz8YRA0n/81REA9qq6WtqfvDPs2K4PvQvH+5w/V4wIqPkbZfCZe8716tGYUQ3h55ul DSCsqL7Z1fMrsu96H3b2ssB6MV47Vlv0eJW5Ebj0K37gEPFuosffI61+iK4AQTV2oeb68iBliVB6 +j1nsJ+jr2aXRs8/ZTsBw5+6WaDH4K4ygCad/gRNtgXeMVARgisyXmBMlXP7sFbRgeyTIPYzFbmD e07q/x7g0xNtVZXc5T7DcSclLLuST1RaEoYBKLcKidxM56sitaGgbQRcWihpXxo2Dz1TCZsIK7AS I/qubY3hStAhepkFf/sGvtXQ3pLFeqJOSs4Jrx5YioOcLJdhQdojPI/UTzJv9fO9/bL1ndNRueY4 9VLhzwcitCvHphzE9WD9zX2iH6FnHuhLKfskwq4HVUXKpgsQRpGbX4k8GZb2zGGHW/cWwZfcynXH I6gsoowFQPjMOOpPEyZyMiWobj3vqKLTG/krltkPedjIKx5xwpG9Enbv/3iajNGGhYsGUwv/766W 8YuwkbT7R6s9GD5EQhnoJPtxaCQu4H1/SeUsmPJJGPrM/pTZ7nHLYBzBw0I6kYTIWJAnKn6A1mzi k7jK0Pr2Dgor1+RJow6Ekzoawp1D85EM0ua6kZdGw/nnIMGdRMHPxPwmfGkl7dT9Zb+sz9fF4ojV g1tp7S2FS848IlA7WBRk7f0Qwzbw1hwHnYOIUnaKCDXzrL/koNgvL9s2UjGtzTraGJ9dCqQKxC9X qrNIerBuby6uzBd9pSkXQ088dvdnIhzVDYyKx4cu4sEID6yN346JYz9xRSZS5ZdCJzvl7GRkwNA3 khGn7KfL+6TLJ9jzOpBsAF2VJ0BMnir23X5pJcIs47YNoTJhqPNRLX4+viTbLSNvtS6FQEmPMhA+ Hxx0WSnJptHGn8TfKPEjQrAR9IxRTM5sk3VpVC2yh0SrQbir/b5nNRcbwfjDHwWG02XGsOD2bsvZ zeAhksaGMk6hfaDhwKdkeLl7/9kCFxmnH0ru23nqrth0NiIysMQy+GZ7YmwFJdVsfb2ObeGQ6bBg Jwn3gMXPZRlwm+gd10VEmiyHyUk+2XsV9Z37bjnNCaberg9RqvjsD7YV/VA9qJxRjy1z05/fPWPq /MgofdmUEvhAxiryN0WbOh1rEZJzi41yX7K2DIM+Oh1oxXnUV5dSbyzxbeaPdkAUq6+0K3P3PTKA YIUpAPkNCKhuy0iPjPUvnxYos4i/f++2Z5hGfqlS0BsxAxcxriXy4IqMrjFeQ34BEiqTYX8z+t28 /xR44yUWOFA0icmKMNVUwsot8VTNc2y2ZQbvOGc4qYuV4bZDLrshOO0Y4lQdjrR67aI364MdsLMN 1PH16vvYySymOKqnya4oXMPEtyLgNJmhwsoXV09JGoHlFBcDaAxhFV79pPOKn3jo4ljDUzU6PccK f1JDHsf2D+7AeuVIxT/XlhAAXM0aO8kTB7VeQaFeMpCDu9DaustPARgS7hA+BYPeZtIBlfWCres2 T4oIuKzhL6AsyfL8y0KtH2BIsvZqobQC4v3fMhk0CBdcKLjtOidXLh6WIdFwbDgLgpks/eVz8WZU tzyXr1jDwdZGTYphajRhrgF55Qz235NMEJDhyGaXaIjF1gF3oyQXPIsGnhKrMAEM6xrInpPxUb04 0+mqg26Jcl4wt1Nw3L1fm100c0h+u724vFnXJZXRHfNt9xpPHxa1B2oOTEcawdBYvrY23092J1xe oFjjdeUdNNkYTQYIo0UegJ1biyu5/GsRdMROtDH93I7Fam4CIkjGJn5FPDmTAecvkBqVoG1pRIIM Iltf2Vg0yYsKkWjxAfaiBpuM/bFl73o1Agzu8UxPR6XnxeDR4lxHvTPfRIRoOgAyI/mSp5Uwxg1O R0CZDx4BugpbWuyCkN+JARMNAFiMlNomiKHQXGrbX3tYKAHDLw96lBikUaFZ8SAu3R9Hu9uynIJs k4DffBxj1zfRkIYw80Yv2No9V9ET2xP/tuG/ublGYReEeyxUMEAXm1PcE6c6sHcnPSUc61IA35uO XjBzOP7t5oEt7LWyROFk99N3WMoJYhPGXqrfvTxS+Rw+NxBhmfPTCi2uFUyCkl6yy7iU+63QbNE+ vZnrvqICxgOf0tvL1O3/efLxnkyQBitOh30mN2fXXEYI+qajakTLpT135FtOQhHfNnUdMrLNG0dN OYcRLzUc+SzM0Qwx5ONgRs3YyIH0zteReZI4fUjh9SpbHMIz1mhGGG1708JszKE3V2AeNelvRLZf vgPbS+EYNL4se5jMiH+0cJSCuo9uJX1I4T9t5U5R6lJbQelSLYulrFQrNkhiOZPMe7YxTp15D6tc YYUFxmrWc6/5XHoiZhKbwZ+Ut7CkiKuS6HvGWVnQLJKiT1jqDBl8CgNnAg2ez35v/resYwyLZhhA 8vvIqu3ySgLluLdtruIwfqNWZwIlxLey8RfckgYcrcOd7uDHporNdhfyDD0YEUffP3lLHj/3Yxy1 +5UKd825IkezVM6IEhQRxcCbhA8aydxFsOATkB4rzELPHXaqF2939YT8IMDcDcIsgHzC0M8rtMxg W/ixXIALVQ1brS8dJa6YyEARgbbtgJRZXOKy7yKPrGI3MkI8yZorjncb/GMvCyEjQRVuph+kie6v Twrfdj76xg2g/C4UJmM2a9NXNFlZtL4H9fNrKxdGPRz2HSyrATvtRJL0iZJNoz02YQigTHuQEQoj ClAGo2ahnCjZnP/5t3aW2l9V2QMrjLvybvw3SKaPwmFZtVOB7CZHPjgbcLWVLhu+UOEUtoJHd52C 8iJ14NMtk2MtJtq+58Sxi9WXCJesfr1eZ75RWHRpanMDn9DW4OtzKHJNv5fpqwhivOFrrVHwiv8u RLsNoHPzlOXZ27ptpqvuz8u8sTNOxY24ZF7fk73yA0CE4TLq63lEugepfZ75ORVq2Op7K6jAVqQm w3n+hQsXVPgsWJv0fut71qXQmxkSQTv8qreuQda9yFx6gFALM1107PUqFKpEypDY1bsFCbC/GXUK Qeo6tQc9gAYCyqqlsrkbHKTAcqtvfiXi+3A4nkcNYMlRcVP8gLOF0WA2dE2p+x2tPKXtbqN29qb1 QlRE/S0w9AoGI7sj8DfSVaR+W+evT0hSp+KlgfbH+c4b5qC+Y2upGHlp7QUQ0JObp8/H06VmYh8w jesSIYHjj8ePydtVSWprtrgC2DAID5ZHZ+x6HY+kNYr7ZCrqjcImcDb9YFYVzFt40ZfTZ+Z3lwMP jceh6c4041W4bCnR4lqPkVR/K5d7osCXHHeUhTFYwmFH0HtSJHZAIk2a8xqPqTe4o8xvSqMStP60 7EYZNvZlTPN+gZvbxFe3MlFNI/N9JP427qzXCw6JkrbDPTqYW8GnFJaB1P/SrNkAoEbx/U1742Fg pYhWVZr6U5REhwtzpuX7CVJloYKJ/zTNwvNu6PZZb0uMn0vD+iI7VmcUqmxRVnbiKxrRFTS7Q28a cgV9nqNOU21zMTL2T6TC2mVq+XYHUaih2TDWmXTUjLPLLidxGEt/vpQDal8sxFsvAvcm6Ln/jcO2 yIXn8fvnXvn15W/N5XEXets3dhbjkA+bEGCb+i5/lufU2RLPAFpfe9Jnw2teWEuqHW2t8K4UErGT TXv/hIdVF0W7fr1h8THdBpYKjylYj+5pMKtRqCO4NX7CJDe4+gxgAw7xaqNYfdYFLh0nUo9Db2rW fIF6P8NmQpdziHEmD+Og8yNmHqbH5EsXGvnXZvNzbhZa0HxffFD6uMmhmZc69FZIc5dqc3LBx/R9 BTiP0X9f8H5bb16D4xuaSWnoSJnVMSkR/c1TF29xOSKqVc/zMDrzWbek37w5yqaKR47uSqECon2o yHciZM2/L9IYtVBPk3Ws+fRXKFdNBecavHzDl7Q9h1j4rfmpyNIG8Fa+qxT8LZZZIc63J0w7tLzN oSQK76ft9+sdwK5ShJVptgzkhOuOrBEW+t+xf/UW3AZKDmLxZOam2+FCI7sPzmYuxLKkqnlTbsQY od6jbhsQuFqKYopvA8Nv2e1lNFTmgZXhdkKtLo06fwq36AGaoFa3b3aodhIWFEQK1eY0JtLopZRP ztbT83h7DKmVAmvwz4XlA67+4CVLE2W0fuiN62/oKa2eS+R947Kt8u2IkzJ8bbvcxmUi07nSekXn 0xh8TYbTirdOV5qw8LDLd+FK0EbZYLCX3YbU6WwlB4yaiLABipzTqZMgik7bFL/H60yTLDk7c5eG X79233DT+jrO50K3uF9Pk+s30z+aWc5x+AgI6UZfSYJRIrllYEtcvf+UouGf76Aof5UsXoM9KjJ0 vWCD7MbifGSv4DGEqc0GotAgTeDZQ+ZFEVPLzPGagrbs27ejbn95spPBG79BL77ebVVkpzFWNgER QvS7QfFpTSX1SK/hYmwVwyDiEux9Awt1Aq+dWRR9az8tr51vMhu6faZOQnyhNTl8r4YhSz4wSifE mFDUjLzO7DKKozFrO74s1ruduk+D3m90pWlECxl6AV6OBV1MYzV3Rc6m9wB6+N2PZtQrZ6vQgwWw aKrU3lQDkYUpkp8bTe0jlf/DZuwQTNmAtEZ5Vyz7FX76QwBu+jBhiMFfUAacdYIrygBT7lKWPAz0 UZH2uO5vFlBfXfP3CDjd6EYw84HwPUWqqJjeFdf5DQKzV78I8ipHtMsEZ+NNO1KtPOtVjwFHB6go NYheTqOLKx4QY8yP9XKgTXMyoUB8PcX7CRx0A5yo5B0YFMKfn+SjSnvuVptzIAwcTpkgMQmeSP0v XJ6fxloYnNfxwRR2N64MVqJXl35W4wn3HesgDAi2eNOTgzu4fuUj3UijovO4cGCean3QwH9THXZJ ZT+ilacqUeU/cRuO+Rw3BgDOCRXY5FdYoLhkeSKF6DIwYIRVg4Uv/9WPtFt+Hfypp1zQB3turAl7 lmaa+MlchJUESnyjVX1A9jIuaxktoqfVYeuFOwanW+By8VNqrl3Cir4ZWPRPfzcS4ySv9zo62Nf+ 6NNmKpUXL+gmUqPWS2Iqnr4CGuPNDjHCYxhzTAaXKC+C8BEEI8LTyi9xYBVC5xMuzKyeA1/6LNYU orofJuA3IfkTdzDZoK6L0IyUCLrUzKpVJ/Kf+tK1RMvcLWJU16blp3AjnOflwd8qfkWpg7B+zRur E56b6Ua5MxHyCqwDvnq+6MQaDp8dQnescGXcTepQoteCE0b0wDN5ptxe34LFJbdRUuE71b80w3kr C1kRxFCgwq3MfZI9XTd+mqHlknZfch/rdnOsz1cjLy9A1Ow8N1vS7pkRtcmH1QDZnTyTs8Ip1UTd qWxdfT3brcSJdiSXonSsG3sX/3tVCxCxwceOesktK1kWCR5MyRb7hKsi8TjKPAYT1wkfRpB/lC5Y u4iFsFhW6aTOaZROrTEGF7ZTT2SV+52rHcNE4yFJaLPTmye+SfANE4akz3nCBWLvzL/YirgH//MG atqPEwL6TXJRTM/ZFfd+ceV2xIjvWFinrStHaVp/Wt2/bWq+PFvGAgRgCO9gg0tqdd1jlQnCgC4z 64sE9g5NqbERyt9Xe4TXV1VxtsuBDW6rjl94I6zUp7O+J3j1qhPf68PQjWCMUdpN9LKocLCdNWjD FFQyBnSZvNRHb3PtglZNj8ofRejjGXhcKQdFDj66OQ3nolhAG6sTeJ3Urbh0QpbNdBWsToq1+nX1 oXbgBSAUzBeADo1R1mk9QsmCilll7z0c15qK3rl8ekL9aq4rHITPam1jCQvem69vMvPDrcWjZbE8 FDJYX/8VknavhJkYGZ9BqY/a610CFF6fwvMr+VHyyqQQwGFhXatqffskGQcXq5g+slrd5fqeIGpW ZPOhd0CAmXm7GELZIzb3GP/R41cIf5UFNNj9MmySsorHtalCFQNjwqsI27ciE8QzBR8YgrJ9LRjm 7SJZ0socn+397+XiS8EHWvYJz/9iVdDueiGzuRlfv19tUC904NViWxQSM+964ah7YHFF4PbcTf8g ZhVZTj4XEm9vTK6+ZlBxj6AXhXdkPQFyoP4K2Cb/zGl1t2Rh2JUJ+eMEn8TlDPtsEQ/rfARDBd5B P5j/LbD4nstpu5HWE1d+c+EL7MQnsNuJP4PaaTrDQ4TcXZZuSYepH1OCpAG8Jfx/XFvKingFyzPg /vr0qG1grU2+qiAfHlBLfr9q/ob2eHCFXBe5QNsLxxGnAhHnCBl/albsenNhTArehBVdxPpLoQTn 6ZOt895HRD9FOG7x4U9ip/DaocPpdT5RyY6dlvjyY0Owv3hX3dsEOf9IWX8UJjI5yL7+8e2dswAn biszEB7yewLJXISF4RThIyXGQhpdXhTT9GvwPOTTVGaupQoqQEmphPvzwxKilaQV24QJV9lyP30p Ueh97k48gDNjikI6CppzLYTSoCaf+TVAzycrGjFjJI6tzca+MhN1LcMh2WtQNrPdCw/7Rs49SwVi J9XTkLafT82M3vnQJh0+FJeo/41Eozzgq2Mzu7vOeneIpfDK3/nbrIuORiGwuEOZChnsNZ+85rH5 APDskx/0+lDEHZabIyfxrpqqq40gbOeh9oqDwdZul6yI5DRNh1i/AegdrAYQs/YrIBK9pEwctTwP Y2tbppx901i8vEy9klwmnt03vZBO/pa3/YnJhM5/onSlAYMkxCWXl5I0SLjW99Xe7ZgO+elzRfVB w674WQ/LFScdhgCpoDRUqSCL062RrbHGPx33VMR5g+rUXGqvkQLIyHTHSb1Gu+AvDnjZfgtISCiU fq4wHn3fVLIhPYxrCjs9gcLuJrb6aMvAYyatMPj9MeqmjPopAf1+E3O4i0YUG9C3xW025s98mZ0N r/SGNRcG75B396kvGHVsnrsZdWHLhAYpdDS9k0OuugO42jwcHDXYW5VcaYJd3HYxffzSs6PR6ihV x5wsCwjkiPHhSJTSZzFIo8MuC9YnswnQw36ENAHjvZplzO1pzD76szQFimWyL4+RIS8PMlauulBX 58AB0T9kCBPl37kPv44xOPv1TuyDUi0r00Ew/onBEDv9XUeLLYpnCK0lm50Ds49geiNyELTnY8Vn c6gY1Yn0tDoJNNLYhvK1SYJ3aXCUsYCrx6Hl05Acu+N06H1NstickuNCr/hcZIoXU6XC/iC8UwyY RC3VAGKKDuFQD43IrZG2TQ7O4T4Up9LBEJPLk6dDvai6BEI6UMHpYggYpi+XkludjcPYFU7GtNyi EzW+DQHq4P0+oxkG41MVMVChqLBpnolC+2RXwmUwJCgAvpi4xfSIa8650xfN9LbggSVcldCTfomu rspRxrdvSnWFJqQG+nl/lZiY0GOnlXO01YC5+DtrDYlwtqihLncBz2Yem0Lwp/J+QivFws/nsuex BNGKr22ZlN1RZZk4l6vDJQxppz2gybRiPh/3JfTlPwgG0LCDKsUcZk0B7XrtgvuU3Kw74tgLKHpy CWHhUIzqx+zrcuKLo+OBTVpX2UAIMqSgbLJrGoTjsbh+8u4b2X0VFkMxJf4WIMiIGe82kScWeywz e7zbbdWjPQWWDGlxVQPO7UA/kVwXVeb1oG4aYvzhAcx7vppNJUHuKPFRu4FHsYLKy287fqtFLb8c 039JEPrBMojfFTopQgqXUgmA5cqsJO9bX9VODicjnUMtziNdRolaiBrKpA+644KIS8OW1EP7maUT e7Whyn5tKkjcI/uYmaNh/cYOSLUNAkfyRX2YBQVBPiV/voaZdjuJxvnu8bf4wm27cM0IX07++hit gdr7lKNpY0TpVDnIbhaWMaKeoH/TLZEZCx3iJ8Du8XSMI+kgE22+k9bmcnR1/lOVbVUZ4FBPFwri wqIZA+GiERbCq8QvN61Nn5ux1UYRXfR1t+HOr+wmUVT4cDESsIC+9vDoHG/bYl1gXs13AHiSVeFs ikGgnHmttxncxY75R1cJ7lwttg46LCAU+phLs03bd4LwhVAIOiPrdYbEPywKLOxRhM9Wr57+s5dQ 4aaWL0WS9W7v5l52npfPosLyAeDBEpVGYzR0WGOzcFcOOA4odCQGtAL8owUh/uRnxiYiDnNChtel sa68mXkiu8OE9dPdx8Izmrp5pdr2DoV1q73T2qS4qjkSAA1zE9yoaN49lKCoxoREcjPXgy2vjlBP cLxt2ogQTXlbYDgx8Qn/iUDwAtu1sEYFGIGxMnC3fqr3LoVgDifD5V6QWoqB6J9vnMegyGthJ6cL 1y/ryMEzQkhgBwD4bw8fri3b8tZ1wpNoRk9ytdX6XkNURSX3Ix8b3tABWVBNr2aosvH6EnJVxj+q qkzG4ewrXv8L0bIaRV2wpZEdONU1swKqL8tpyK/0yRlPOAVydRIeKwO6zOfeQ8s/TFEeRxJgi5Nf RSQJyjnqHEafskvjFc6424pGATGqlGyht3N1WBZ53z8+K/8noEpTNkbVcIZ2v9FZxTl66e2OK/qf vkb+0piLoHOLOLGKPxK/chJ1KXgQ2TiXJgXRcYwsR1VNYhNocsSz9G+0rSpI8iHWCJNJ7wTEhMoE kr+LTmUgdSS7v5YnMC/zVGHQkD6vsYc1tmt3rH8nkD1Mr9b63cQLCKdNC0peJPu5IdzCGN8xt1pR oqFhSOfBSe4nPwMTkjxKFZ75yfO3dJI6XXM+PIEE1lMw4KIIbijRbDj/Y/l1ZXBrXiz5uL6TBeYl whEuuHOuSq8Pi/5muZA00AXEE/x9XbhYjKNin2rhnSCJyMLtfe/Yq8q8Tad4u1Cr+QiL+HgXTo3X HAlAhKBqDCB4/Miw3061jMjeutNyckZOt37QlaITJVXpL/q77SpvVRz9+qKy+yhCbwS2QZmAlykq q75d2GZPGY/7J3tch1rw6rCLajoIalwym/7OpMl7Q1TGD69T/zs/OqRiu+H+pEgU95EjQXvSzcRb nWGglzY2X8X3lZWLpkoM5nIBlFxh8QoLhuWa8wfYmGO9/eVgXLL3KUU+Dxk0SCmHLu21fEruizGs M81iodMaXW+MpZNVOT4oI2LhcIQqHzaJ4HmOndIwdRghLK49ufqtWFsJ16og2NAweoZSKJGWEYZC +q8sfstdUfbvHq1PiR0h1K9qFN2RxHJDHQ4iMYz3hmSNLvvrwo8ShhyJyxzTGwp3W81TUpADi7iA cxoj57Idgw6CK3LM6VucX7Tme/ifEFeqpEU9bEl2SYHQDJO+a+qC9K/fZd08906wp1tMpbunsexy c1NWAW8tXonuPlus4xHSXyS1gjHWqKoPVqWRNVEA37ot2IFCsrbnLMuF93jnTmxUYTqaCs5ElY1Q IETiVlS/NJVK5xQ/iCNxH5MjRo6uXOoNQRBPBOtcqgvgRjFkaCPjxU+OO1kqrnvSR+EtK/QGspKm UzT1ndFzU/+Rt6t0/x5Nb0TY9tlqICHC35TDxH7mOC8zwgTvvv439Ubba6Dyc99OwPLB53o0BxHo eyoYmh7eXACkBbpMzCtlgwTmoPTvvOaSEXQsAOoLaBU3muqRJwh3p82/wiM5WSgkTv/HwbZX9I8W wlU7TAP4t7Tl/Sfkqgb9NwsggD9Wv4xMuniumIw7ZXxrA6GEHi49gePoMS5q6febzVMW1F/6LZZj ToVHLg4PqpoQWU9h/vZ5PzUhtL8vixrmcdfTkdN7qEXuBQLf6XccUZaBk9dlKr+RaTfhE1SXO6Cq XIR9icKzYXe3NOZEbLxBVENecRzmmNeQzXnR722sADxKbb+P8aRs7+C4Zd5vUpBbheosgXpuon5+ ERUCMX+SqGyt3BezarGcHFt1Fu3KMta0Sf0K/fDeXB3UpnofPzbYYluIIpIBfdj2S+1XOPXqRWPr a9kYZa1Q93G/2zxTeuMDZb+TG7T82Pa36yIGwtq2kd1b3EweqHumxJDr8J74wDEU6kn/aBwfo0kF JFPqUZPOF5uCIwdBiIV4nmBTObxdf6IzBVnY4y0nG4XmI7cIlAGhhAoLb4807+qJvF7+a28rebji Wn4FNK4qL41WYU9WjIOWsVxyXGfxtD4RrLyAL4UkCgv9rGj8RAOLRp692QzSENhVRKNyCcHFDj5e LbBsQGiSIoV90L1HgTzvcg4H/RwFu2VB5/bDxoyGHj0TEZxfuymvvkSm7cQ+MvOa3y17dcZ4g1+A PrekTOBPJq9YIO3kG/MH9MSadpBDvHJYx3z6WyptBM5N6TDC6qdetefywgyw9KJIHlj9eaaT1hZm 0L/V6SN4synLfbG432Q58OMgu+5rfsmsnleSNbYbReDhmOqG3rMv4DAzCFtkAyxMo8Wrkg/4bJoB HrtmnqN4FIlwXjzJ++oXy4G6kvMeCzOZaFRMHnL0EOuI58RRHJp5wn93IzkXWHY1FkIo3ZKn4ULf 474t3goeuaOg2kIzsySgQsjnb2gj/XMDm+EMu3rqRQGwUxYh+phqIBttswnX5kys7s28MMNrOKsc DKrOEXWnNKT4NuhIfTkBNbXGEE2MuWwtOprxWodM8Tdx2IfdMQAyznx10K3uawghZ22QwkiZyURE ScDt8K48Cc8+z5w8KeBCkaItqz/71ZBlBSmvuGyTPzc+ls8COumZ/btiELMN88Tw6rYf9u8IKkhP LHV+I7CZgn2aFto12xrWGWrRqWv2goIHM4pUUldIttkwHJGFeyFxUpDxb4rHakCfhVMHXmAa6NJ/ FqRRAyx+0YIdLZhpbGdU4osD6/fG1sUYzz06oMDfulFK3rVu/EeOfomM5jDgKOg27SPQbzepM1hK f1SMPYywN/nLut/nmPGwqO7gkV7TUyOBifKT3gzGc7JbqaoSmQbEApZPrtYa4vqPwQ1UU3wSy/5u yXIocMrz2SSyyuYE6ErQosNPniXrYCqiWM1LbhTH7y/CJ9rjuP0nw/6FU3q+bCkOluSZUoKm+XXG 5LQjxq9fFjCM1u8P7jvaaThLLh8nrgqtVCndCIgwZI+du/mosV+jccEFVhSDgbHD86gh7qSR6lbg bDOdIdMcxR6/u5BbqovvTZeOh2+Oc2pfFkE6gkA1/s08Avs+uXZylYTJlVlAGAqJdmuIVDzfLwF8 quTZwpqtA6GHoWBOxh1ID5llvKAiFUTzN6NQMwKH+iRgM8HrsgSG7uim+aBilCxGwaXff6HrMoTm doHqb/nGJMh/zUhq1miEX54Kna69cpWdbG9/kUu09mkbCFjnmIZRRUETBK5DrEQwJWWKUncK6CKD JCD0aBPkR+XGcFD1f98PhzDw9na7OOyEqRP96omBPA+XQxXRLjGjxxZzrXX2z3BBT9zhWtGf1C48 JZuZb0J8mmuf3h22B8XbVnLQDCuWyIijopdl4YaRxN5KZnXMBVU/4UITG5SxAOtWRx96zsRHxk8w xvgcfVFSHmqEeGj/TwPLvWJS3Y6L1GycJXCQ9ynVdn7Xu2JpiZUqsFteNT5pvL3jebseRIEElVM6 k4DaN7noH6Rya+7WnrVFOysAAe0L50WMPMJ5Fuja4AzM2NLDGVME+eu6UuJTVppOe+bLQDBQLyrZ Nvml5+r1nKdVrHS0EFG07pLkQW8a/Ca9z3j7pV/I1aErXe69I5oZwcnVXcJ5rIt3X4/ORd0ImlWj +aFvSt4qbIh5lgYIyMCIDbVDUwjc0fxON65GkBCHkwaT2bVMjvXqoW6NYBWg3602U8elIQocnN08 UQjpE4Q7kkKMY9fUgUAY9YB+qEdP9Im9h96IdKMURorSE1NhqhJbkTL267G1IMEsYhC+TlTP+jmG zvYr/B7iGCgfiOA9YCCB7+eMdmyV5NaC2BnT3YjJMAedv6R0Br7Szmh6zvClFV0wT+mZlPJrSuVL +eB2QDOx9hsSH/+JQfmwCVuDDpZy9tMQ87Lcss/rH+mTga6CiTkV/gJJE2paVquOGeD4gkp46Qzq M5g2idp2G5NvFiBo6AZZdXbo33MPN9xmNWMjyYGHeznlaHKmwN8EVMNmDnkZ46KKPuilzRUlb3TX jhpoSO3C+aJodXfGHJ93PTg4y7zN9rj1qa8DqfYfoDMgt1kRw8u2LllRhDXb64fbrKUZ5siGZ6+2 NLqYGcwBGTk2BTa0kNmEN8gHwZZdp3y/RFkIGMgFCm/lizFBGb9RtP+ref8Vuep/O02B0jVkDegh DkIuiKWhv8YbViGUVIIGgjzT4T7UdqOK3nmbKuyZ590RMrp2HqNxLavqCFXeuIGWVl2CbN3FuBfI awRIbEZ8+9GHDVv/3vqJUSdHZQ4/Vve2UorNrVsyPknYQ0J49wh20BZJ3cNC6mDsl4jqZi63ouag 8BGccLOHuNNAxI5Hv+p7bqm5aQfeFYST2sDFDgxZDO0i5FIdg6y8b/1unpZelFqx9R+e0Wj6lecw E2wCySozyESTcs+zIrZgwTFHfIXR5IzzVaQCJPBxPTPW/xygU8DzBMY4NJQNU4NAMVa8PEgfHMsX qOD3bvx2n7EtG2LuqqlZ/URMM7XRcdyktqPsWE+uHjliTQ3d0IFPX/wpbtfohgq7Q4zhHAxuNXhd AG37/uxclbkgBpHZQJuru2NE743t3QI5iGEdsKzXDlUi9wvd60CzR3uTfqpeCevIMxEpkQQuseZX CATAJtwR1Muvszex8HAwiuHD7qsWWVNFByCoIlB+OqvAz747BDK03Tq4Osiwa2bNqDlvbD15D1N/ dj/SJsjc5uylrWMUGuvOILkBEjVEe6g199KG4+oTXJwI58gvH2wquMc61ZDH7zp1s/2XGv0hZGeu LOvVjm5zTNq+ghe+dz4x2IV7KWxgP4rl7VN+lJpmno6UUt9didHmx6l6hJnQZsDiT6Pfqr/Ni8qw YoJLVN638kVWRCeuCTFZ+ptRZyZh8mTYbT+wUd/BjF3dv3wDh2SR+XXaaJmfEuILKFGvVCdtHW9b KIwEXPO07FR4LiE+CR1hIzUYKi9LvQ50ZrN38+9Hm8Wp+ZCu6jgBUs/tYCMkPSqkmkk4TJHlOCC5 1IqwgG6MXwbDbYLS361Xa0WcAbOxbMzyrBs2aHKkWMtSd5n8hvPSPx6dF66g4GxiEfPtT/Pt1y37 KexbzQt8L3f6TtGdtI/KpFosbHvoATBqFQxdQH6QMh3LgeQqWJJCnpAbl2D40ExY1mUMDOuZig5v oeJbmWvYLTRNa3WQQIXT1YxKWM50emFIPnB0VzeBwupN5Ctd/hoWJ9LqyrmvWDplB4mA68kyleW8 TXUhwjP8KmUmghkR//0HPSHpbQnYTqxiOfkqNlhME8hGUkZGfLjyO4O+MAomxkfgz8A0y3HbYBbd 30shATWCAqdTrj2JVPWivpGrFDIAouy/z3LfOzDGMgHZycAzCFZJwR75BVkCvaUTf+uUiPUvMxTc m6Z+DhvKgH4WD1qoEsk0jp8rwcczxsgEiKdBT3UCbqDNeH7jMAQXSAF0aND7GreFN6tLIw/ZeLpo AO9OXJdRmNspojGkHT6JozLG9Ds3lk+IEMJrWpNJRWZdOPkf3+IH7cIrkLrJZRFQippNskblSLTW AM74KJm64PjrQUdVB/8+2wlJo5sIcQwjlxWdC9i8CpGtqPGNFeGIRae90Se0eIb7EwaDsReHB6v0 FxLeO1fcQS1eoteqMU8juYjjsK4j1n61lq2nHrDUKl/6m0jImhv+EOci86RJWq+KxkrqvfngAKXP ulvys/k41oRlE1k7Omkz6U/rl55sYBMm/geIy29Nm5bPixiqActH/wIEb2vP6usT3IJCtcPzJmFp AFOoucyesTz9uFucpeGBid9Y1+YFz2c2GDLzO7I50OofuAIOctDxDodAFQjaj1lfgOH+ChGch+eU ON9SYRGSYM3OjellrUEpGoamayuh6cTaHOWMmWySPfBYF8028RwsQwxpRuuLqgVsrE4Zl+NIj5Jc zQQU7Sq1DedrO+79JM6gvoXZLGgMKPTHp7c54bUXlxAbXildZVU9XpuHKqiT/wYgH90ifRTuR915 NpPiBgKJ/hwAmo3KXkbLhwvVVqRyi8BTUgXiYNlgmxzZc9o0/2F1nmpZt5/+g4RmqpdeT99FXir+ fNX0ShVBwSvp7FVHIrEyTKyL/TXQ7XRspnWakSv2BPX39UfO8kZ2n8x5bgwzIqmQPlGRzI8pUub6 J3ZD+VbZ3zti+zWIwkIPVRc+bRiRXLkc0h9jv0O8D+0am83TuxBvTuVCxC39mTY4vgukLm6u8YrM bzsyzxIXwNtw1cFOWG87e25L2NHfotXImyCi/d1Vt9xLZWi3m87UohXreFpN9McDSnjXpHC2iEnn 18bjDQL/CjmFEJPw/IglQFoKTRCBvyFmiuf+oTld6protBcnFHwz7C3JL33X2x4hWaK2JsBLilB6 zbBES/XI0K1G2sYdSrdc7WXv1CKdKd6xTRg3p33Lur2ZQcW9CUsn40YBDeCHTdCY+zYp3xpRxTlr gj2BUVrjWTsStZrzikrErJxXmVXOs8Hxuj/Yg8iBuSuCTblnglNWv6uHcVeOXd8cksTQWnGvGl9d y8IqaO9JJcJFL3qpOg6TuVJSow4wAHkT7yoUtF/wGB5eOCZf9en4UsqJqOpFhYNpX86sKbjMBKCN r9Www6YfvifzBmIaBcolWKVJrFLxoVSeivEz+aHrqMCVRUa4CCSH+amT/DjFV1QOOrzik5JxwxET bkXmGxY64m+HWJ32+ENWClO+pC+/gW9gMHHP068drHIA1XLoJ4S0QWqgkZj/FWZERm7/b6340LL+ w6tDevehpSHnjzfq8jDAZ0VSF/NhSWwq9qr5UdMXTH1eY6RzpEM5QJOyoKIjb6qmVBR/0V+tkKcv 38sWCJQDPd7LEjelIgz2a8y6XLP/+g5gdd1gUiF/Re2ltumMNyVOBTZjHRlHjyuxopUZ8j2ra9/0 dtCWrBU0e7qSr+zhziCtydCN9FzKBamlWtIHKw5RRq+OmIaVImjT+WpLbMOGnL2FZffDBLr9ykyf 8smWfRTOoQHb6iAsaUHFXPCRm1plUTMdG2pwg/HZdLnM7uWfTOu9Ixa1kHKBOvuvdGMVeX2dnJSF 5GbnZS4cmQYUrYzNSkbf+yTxeXw4KnTEUFm7myicFTi6LYR2DlY5RqXkj3/7ipAuMIAYadWCXL6M 153IjlMSqdZffn9Mrn36JXamUDIKPin9ewDXGwNo6gLj9NbVSt9FXKWBXIcwuxrEl++gkZE+ddds /yCFgGGtZrSBspGKmFQnKjTtPyEOHhs56skyPmki8kFgRv6gO6cFbF0SYKtZxKOVo1002Pth4tZY KGfEJ1Zw9yqmfhwKOvSD6C6rqf9i4TF+0xZNxmja1Z7hoy1UPxDoNoMcsIL4LJJ/8jxjzdJAsrhq pRXUs1YBAHarZFqBAXw7XVyYHBnnRWajn55v0QhUJR8c73n1aPeY8xZReVaGZbXKoUFnDDGCR4Wp 229ePI+C4wYuEtBPQa/4ZsoXHh8QmnXC8eNZYgodWy68+JAQ5XdykzJA4I5Q4nVunLOq9/zNXlQb fbaaeJnG8kLZVvDXkP/tpXrS2/iEG+LWTRtIqq8UOzq1RYCiq9J5VPngDy8Fn7kzt7ILqVlIZGtt K3r9fiwOU7gBUz4DCxHQtc90H+wJciyi4Kib63JhWLV30Y0etLKfMbPqpBiyk9eA/yuO2V9dqCfm ikjDKYrvYBgdaXyJ+XOHpnVfOeh6djxyHVfjyPr43hmdw3yCWRdXZNS5u9hwGs5CdvrSV42u+HpV xSH1q+dxto+ey/v/zRRRZn6WUn/RBQKGyiRYlM8Vj+WR/SbSmVCXWh4n2ALpvSYQv1u7hLUKv3Qs Z4OUcgzGrmq3pgAp8/iGJNrNh8EErRssgE1J3IZxIaS2HkUNsfq19MqKlanPUUnkGkkaOXyqOJMc VKPVa9OfRiyOQcIdBaNuQs/M1uAZeSXAxqlYq/4bQYvBqgRIkx0QCwF49cSb29o+u/iJIycVzq1w /vcEhp8ty51ChOAYzGrvt4NVIMMAF7E9XQF33t57yuZr/cQkGR1rkomUWzcdFimH6Zg7hth4lyX6 KwjDLP4ZEElTfMYFthR9J25X6AJtkVhQn5u7zql4Qt1VvjkmGxPNSbafWa6/XiQI3nrIbt/qx2hW Sto+BXgXYc9faSWmbGd1BIOJ//tFXinYGryMC+wCGTa7LxndwNPOCgtJ1H/MkwhjWbq81tVmEVr0 r30fnrm9ZOR6pNjfxdJYNyfeUl08ckzuHkxys51v0WxewuPfB9Hft/X8Lt9eRPnGxJq+Qsniqlh6 KyL8oTRX6PPOW2c88gGD0L+h1EMsN7EZKyfjWVfbJ0soCDmlYdDSIAdp6lFrP8ZXeTB363Kr1GyJ XQzH7TZTHxG5r5yys27mDdSU+l8jY2wvjUoq8hDyQx8xALdF7FHNmW6xjLMBl1XDlvgU5nymnXpa H5TYcel1JFBjcsgEfx/UjeQcv5w3XXD3CnNtc2A7P/ejC6pMQvdj4xIhuzBuSXzub2b1KKH7xhWU 7gtb/J1+BiRC7n/wnTfYX+Y1nEqHOweHqEorm3Tularroow+jEzKLKShspzOyIinLjMB3WM4nQYc kKITz8MxYV4kuKxMlKBd73mIPmnmTxZGbUQyF/MtbOxq8qf6Sc09ndqKkF24X5qndTp2x4VEZbXc RsCAOUzyd0HthbK4FD1FnBKdEvNI6EAlFm2Eu5/GdoH0buY+9NGq1F+KUVi0hKszntEuU4d9Iayk NrVmKeH0x1esTLdSDF/a9AywffZoNurBvx42zWkt+5V9CCHe++EakO8pNdvahuKd3HqtnWKfN9zn lCZrxmf1/yq9JK1+pAwzsqFDzTkNanUFnnM/b19Hk9qrwINYeqZOGce65efJBWHx1wqsJG8DF5/c +qyO5XQ1nOKGaHuGAE+7hL6rMewhke0ugwGCWibHHjPwyYf3tXBc/cI/7zUHENA6DxEC9+Spn0xh pjiNrjzj14IYhLhakOqW7ak1nBOiYF9CuB4WiaBe+0jSdHKSzqSaXHKlBLEv8JaUcw4Qm0mz017u /TwVtrSFNH+QVWvn7p9/XGO+3NqDI9aCuwqGNiyTUX+M0n2aUKCwBl0Z7GFDVU4UHjrs6I4aOZ8s 9BehaoJ/LdL3YlHgRgc+Nt+F94T+8BBj+cV09n6YG8YLR51oI48UG9QhzeuxdsBJf2fY3OhfWs/V +UR+K89Ho8lEs2n4KQMeCoYVIBMWy9kWY8SkaXYYssnhxrxrNAvlN2n1Lmyj5QEuXUA3FHi+AjIO KD5ASZuTcSRrQ97lbIqED/n19zzSclt9zJ8TiaxfwU0jAvn6jrmvhcbjgj0pKRD8Xl4HEjMAhWvQ V7tD+D9/yx5nP4W4Yj9FTUG4b2S7Ibimm3nAJ5dp038Z/tbb2YTE3/SizqrVDQvqWdDCYGke1EWT FfuqCNPphCJavAV1acxiZi9tZWh5XLbmvkEK586W98cGVA3YHThAFPfE7G1O31LJpak3E6wDJx45 cpQgkkKDydtLzPHDI+5MURuIEgy8kX/MGAIS0DGflqZeSliVFiZMtr6Bbv1HL6jKNmgOxYHye09m miirpYt1TJWy8l96TLmRvFkpgEsGqfQNO2EccSzYqGM0OFxKMt1SuG9UG+ZFJwH2/e32qGH1wtP3 qggMr4pKN4tLg6mKDvb4ThQbwVanjnlJLDmUKgU602MTyqhEchFY97M3iiZ/7Ty3m6eV2+osaV99 EHORKuKKlctvrx9Adt0BXhOMsKHV8m9x5zUHzMFOTQbWmuTQPIyeFy9Glwm175sjGUdE08jJUHf1 78JEQ4rHzhPXPO/ICXfpMX/2rXMHKMoFhHEE0PqDhgSQNqaPwdL59thuH/Q6Q2ufZRneUYHhfZla TDNReqau5Kcyilw3MxpAG6RUgFZIMhb0CuGTkjkprJ2PG13aX9nnr2KO3HcRPsbzviyr/TCFnVqv ZlkWUifPTcDZvfDR8tm3hgk+dMLjEw8b8nEOKdSqR2is6NeIqXgnLg3kUtbDUjP2RJq4JKwPBDYd FG83vXhInyG+jEex2fROk3Hla6f+gUU3ZPZJ1GaKWPsdf8udbTTMDvV+E7UddrYRHmWutC1yC4RX 189lAyH7uHfAY6Tq6FKPgW3RjsTOyYyJe0x7vKx0VevY+ZTJwV0r0o/Y/Zt+qD2c2HUDnx5ISc9F 9RRKlKuNfr0gCDM/MY9aj7WCyNdqDbWaUbndc2Mr5kWK4rDLunzHO3KBLOFcGcom97oPR9Di/gPv i8HqdJtEwXEPNhWgnO2GUXpvNdCOHA/gdjJohudERYoSCKJoQGx8+DdKZ58Sdl4cxw4KYbfQiNOw FxkPjUw3JRkwhN8lzT/Vqi0vvqjO3XN4u//b+9KRNm6qhk8QbpkgkOPM5ZcSSSrAuYQrIMJngpeO WB+UZM9otXpTRlMaM+BSMfmBxkSPCRR5ZRGU/mcJEgr8iB6tUcuMxVEX7VQr/ei4DrormZWvn5/1 Q/uh8nCkP4+pMTNP4aPPP0JAAJpMdA6sn5Krt+2/Hv3QyL8UTHbJsGUW+sNXzQVrVVLrzgIfyOYm LCKQCgIFxMuLb4Pwv6lxd3aK5yNuXvH0guhIbgB+wz39CPhou+3atKRvg1TS3yEG+3wk+IbR/Ivb 4lxfY4Dk4gqoFPuko4mY1l5gUceWIcG+mQftcLarvyTYhHvWqWF6TdK6ey+cRlKyiMP39JU1F7j/ +E6Iw1Sa/fzvzanAvfzztf/1/VzNG54f8TF2pBkQS40CwL+ZFXzGkON6DdWGHB47QjMxc3GLNiS9 j+FPETv6F2SNZe69jh5pg29lBwfK2H+PbWz/dZGv6eVDReEkd+/gMuoamW+uVdVVfQP1zXv0R7eX He/so5vHYpkEnlxkja56Cn5UF8mSENlPRlKc9Hg8tF/nRiWwBRYErTi4cfgS6YH30VkmyfX/yM7Q Wpbdk5964k576eVhWYwGo0FKvJMp6JTlDFSMoVHq2KyRz/aTm9+YQhcabuTw9zuUB6k244qCaiK8 8O1r52XP4NoH/0vW1elwbaCy4Qvk2T2wEvpRO/1xFbyyGsE7LvIdQZI3u3lKnQ5rawNhWTNRr8Ep RSyLXeCpxrKTZjDBb1Rrr0QjaYLPvRRJIFNHkl4vxE232+mYxFJxxdSlTlIviMShQvPhBQ7fQYc4 uS6XORJQJS2ELTdzd68gjNTFlRHHyN+2iyOHCD1HdUgBoVePiAs+DjyFx3JyKBxW6ynTuHCTt9WQ 0OLbMr0ZE9jTU0TLkvBXcIuSzT6eVogRRep5Z/JxTNBrOxK4lYJ8cn158WXwZVBFDsm7hKg6Xj0N ZgBbGuvS6Aj4O52Tpn8Nngg3GQyEnZKDyvkg18SyUVdDfMuv7P2Xzlq9xJHktMk6xZb34rRwU2Fa HTz9FbWE66S6hV8MbuEi5yEg+5xKcWZA85acGspCCeEP1MU8rxPaskMvgkGyr5YrD95SV90an9Xb KSDQr97CytW3AFI6FXxwNJP5TGlRbMg6jtLah3OWXH8jIKuMfSFOcdg+bf+ASmJQYtdKsOJNhQqi N6BlTWfM2ffTqGZuonSrLv5fyLRR8G5AOdcPNdD7HmALHhQDLNUUpfl5E2f0dcxbIOWCkbC7ljQO DLjP9xLyg/jliyz9mu/d5VxLwJIhB/nyLVHYZOT9ROIp6IorINlcJWFLDVn8Hc94fiwvr5erkjEq P+LkpvqbQqBUuheTBdMwLRBRSykGJJkcFsNO/RCok5I5CJYe4PoVWiez82K0EPjdLkc2HFhBmPTq IgEs4pVskCiVzYUV521QNt87ofZjXGCR3+L8JtxGIsai5cRKgDaoXUtvMbCpCO34jSVEOoRUPTaN 7/eHJdrLe7cIsEfTYTV9DU8q6Qv4ospMKkmQaDZ3XFClK2EdwsThut3b0WDHD/H5Zbb4RyDoXGrJ 465SUOIVqajOuoSelcxLa1sfQgPjoSlZ+p039txt9xCWgsjGQopdgWPj4vixKfXDhdOezpO3X1rQ shRNVApO8rsZ3oq4JG/uo0XJ4CEhrguD/nZHNJu6BUTpC5Ki6RhsfnPf8dUzDKBXBeQAAgaY9zMS O6jAS1Spsj5i9KGRNcw2ZX8rKzm45Y0joqN4TwNBBa0fRwtuuHsk3SK+tSoEByXSUlIT/b1d+6Jg llfJh3UpkGezI4KucvEjaxI6k13+RJeB5TiIhr3AOJjtiqZUAGB+19FEvAsRqdRTXfRfLMCnr32/ JdfqrATTuNoCwWlZYB9tYW+EQtaM1jRCiQ8F+jJNk8CryjnqcYExgRtgSKNwYWc4XMpS7zro8KzM AXRrLW6NNgnQdsLjhL54i4eWepLc7rKxxXIQQUzOl0uXuwXm53+cPJbcG4NcFr1nPJLjBcpPDMRP /spo/KuEqFh37RSNSQinoKQVFoLQalFhd4KROTC8Mk3GN2UNXUohaVFBzKh4R7LRHGnvDEbz/pRX EBJ3Zbx9iaYkGuhHoufTTesOZiXqQCk3Zm+BQrDeFfMmkFJ7QbiZnEB+bBRXYE3JIE76UFWP8rKg R2BMIfsymx9LqLgHvbeQD8FrPMePai2av0Mtp8F1VVFQmbd60hREMjleTB+HmDRUHNOFC1MZkrVc NLKURw4wNw62TUWszqZc1dIqG1MHvSVu4u+9QKdZHzRQKT/U1WBRdbgfUc3w+yCmqBFYsRhH85oz KyIZB8dpBp6oRZensc+AoObnhWtZBTxHQF4rA+1WpAQEBV15NJTleGxelaqCNrILEN/hkFbcL7GQ botnW8kMy0ePAfPJOWVzGMbNIjd9fouKWrbIH7cQyU9ior50LWi+Cr/+DfWUukbKZYGbTYtk8sX1 hndCZYrON2JASaY7pEXdzqA3FFE8xkNJM0AEtD/u6/9pm+fDyciNuvZlt+j/sh0HANEdCI+zrp4j whB6Jk+i4IouV6ICoP+TYJd4g9HbIsIFOUy7Z4H2TPy4T8imCjvFdu3yuF3HaYexE5TXkRZehyfE OQfEg9AMhmEu4UoDjtgJJkSBnVpljMEdUbD+FSKs8CeWdjyACqXvNSTzqZshEoO0t4pyseONfHep 60qmFQZwNmIlxBgu3jvgRKkMmm3QiwRipgGiuXDFmOpaubt7BaXSUqV97FHoVbFyMSZzssgkGefp yvnFmmMLFOHrehsVM5jC0ggSHTg//9sEwZnqLTWWvo+FnzdcFFRlGPzKfVDaWzD27LAChX8fujC4 p19hgkJPakti7L2gTnnvPWoQfVwY/lZf83ceDMpOuOSvwU0E/gGOqIIdYHA/HTkKgEqa1fHsxIMI y1832FzvDPGJ4eDHi620XGPh6khE3mXt8TusHfuor5OWy1v4xPZ58dXV+nO3lKgG1GeDW4uYRvsg XVjAQctZ4BdAhwwlkKea2Xr0LcyvBhojkXI4ox5DEyTdxZmiDCSW8zqW1u7JFpuI8jh+ncuvWX9l 2CHr0HHvezZQbfm+K3/bjljk1TL19sS0qyDGvaN4KW6d5BWoRuHAxTjN2q0LsNYbTQi3KmvnRLpa yldJ8Uv+pxMwLRJM0/kYHT8tVzJSOLHYgF3C5SbkNJ142eTdDwxdNrGWGNz3jNpPm8/sgjoDfSo+ 7czB5ujRcIin/STeqPGkyHMT/ZqNB3m1nQs/Ypf+B3vDLqDTujEhW8Sr1beTXCbsxjKOXAnXQ0XR 0NppCu8d00xvNkFBpUDFcnymylNARvqjR9SCO14pF/uPjPa5xlwN+FlY0kNLfcvkRJCzsglKDlwv P4pDnMKCYKuFx7yWdhQwn/8OtpQKiGmuZIE9Os7s8oPEZJ2EbZYCPiFEWDacsJvqGX+stjPyUeyu KyRmEHA/xbC2pkoDdfTdp2O9E0sXPaeHY4FyROAQwcD9pN0NSz84tfY9Hm+Xg+RCr8IMIynPZbs4 kOktpHWguwfz6UTLxD5G6O8jV05IT3uBu3aF5KqtXQ1dddCzXJByK7K+xawEpIl5p4fd7IQ/v0h0 SmpY7IQTTz6+bkVHrOrGrDQn9J/zZkhhW+Kd34Acz3TJ7rZVAZkKmK2wvFglpi9cIzkl6D8mrXvl M6fTfqeoh9zmak1e+g6JkZpzpuRGfKErLUFL6o0WjFjzCOAwAEy/mpUic+raKQbjr2Ww7Nti20AL eeICr2sW+YB3FZKJwRTEuF4u9eIRhp8sffAS1LK3sWmoOAKXtWk23lS9+G5W/4JWtW5hlPAxA8Y8 QhMvb8khXAk+sjM27uSYV+6SUhvOuQGOl9pI1n4wx2ne2UDS9n35zHminelE+EcEZ9tb2zN2hIOG prAwXay0JbYuXkniHWtH/eFuZpC5Skv2duDOF1q/pDgWhxvASRsQ93WGin5iXRSgvaabBO7yzY3S CCiALPZEp+0PVhqNBHPVeazO1wsFWWMplwau1JoZdv1ezJWx9C6+aE/oNn9SmglMiWp5TsNcFMyd g/gADtOdociuocpNBbWMbatk4eepn8CEIBs43hVZoBd20Ukb7/AX4+paLpuM/aJzVcXosA05dxeB pdvCpSDztSXIG5yFfyszk8eGu4zXAIr/A693zoDJMKBKD2vJYbYYIcH2kOSoMW5xlkfCwDqXtY4j e6hfFqxq34f7Ms42tDae3l+sjvntI57tvt+Mi+g1pkKpWydETCLOdmC3E4RMqhM5xRA7tKp5AdBg F/4bOfhkvWqgXbl93siBS7+4XZJAfuJp90v7FJzEFptEXK3jQvuLD2ghQbscT23trnMOUt289WwT BkFpUcd3cNkEJNG6MqZcQ8i2Zf9JibJhnM6L4kLEG5YJv+hojekrVB8OpntEdJ1AaP6lUeg6rr52 HoBMLx9ldllV2o+dzLvF2dzjapbjw5r1ICOtW6+orCc1B9NPuTKigjkBpUiSpmvytJ1WaE76uy0I Z/Z4QMSd3W4p4puMoA1/Fqz2qxKnBEjJom2gaGNY0yzFC+5rO9sPwS3ewKTfKO8Ny/gpujT9LSI4 zJcaXI8b1puSbbQKOVojzzhG9mXcPR21XDGAmpcLRbTk6BLtHX+gq54qUe5yb0jnYauNM948R6aS it+AS4zOVHvqoU0Bpg1Q5BzMYcRDmCYRv/sUxtFcMd2Q9CIM68QCKw+3KYgMN2E4ycPm/gSe2P7b 0kk8aonI2cEQVZ1OVMP6ffN/C1KRv4yqL4X1L4CApjbaIeYhfRH4G5lmfM03I8mAErQTs9ghPshN e6EAnrkYzCk0wsXtivYCnRKmHXh+jhSL8SjJO/p5AHwDWiPLoSAiDUPd34UFaJYTzMesnAEFi8n9 VY/BgYYT/VNvp+nXcqWvQdEFcZHjVjjVGlmdjKNoy/GMlXrYb3sM6BlL/wSvgkzYCLO2ZT7QVH3m bDvUuMIGrLTrYlLKvOLTt3rTPG8f5YLYA1/+xNB4/nycqwm0sAZT80Ww70kZbJQkbhoBVS+RRxLA 7I5hoDu0uB3xTvPJhTwHHhEPYy5+PL0e1thEDrNl76wU4Bxp/Bb6WjMAedZ/UJgQPz0Grc0p0TQ1 LXqzJne5FqmCqNOydH4bSWghAS97vt1C7gpOjKWBkl07YFdaETjlV5JgFzJG04var4OyRHXdmtzi BrjwJv8YuTSDhdjXkPqnLkli/UCkYgPFTfo4xTAD/Qmnfxs8+abO0h6QjNCzZVMIltgQrPwcLkeW 6HIdbPp+RaMm4UpjyNpBcxzx5wjBCvGWEXGiZzuhyKuukl8i8PHokMgGgLuzfHn+Q0nH4zXS/axx U9IU36V4cXoVvZnVlnw/Q7OXfgQoxUIzOggBfRGFIWMxC0JN1lIrjZu3/eTRop16A+/BgTLRPt8l SULZ+HkHn2qOogIhiwPgaMIRzCa84UkuiQ5iNnCrnBQaQfG3CxyG8POiG+DqvaUqvHWtfLupRZrm 8q8ebe99c72M4fsg525t7/KIiMXIQSMPqxiLjBGx7Tz7G0zK+IH2BnGZJCSWKdnXi8hC8mlRldBt 0Dj77S+lc6TXvPJYtLZFv999k4767nlRUgfGXmM7QuXIEW3KZ/CCcdVLJx2GWbC2KR8xal+Z7vOU w0iiVWKvm+sd+lw+WdF5sqVtWgxVrXqiCOE0bCYiaSRiU1fFRXkixs2pYfS8XFiBwxeIFrZARtmE ADEsAkaq0iGEx4cOyVNQ6JN57CurSNN9mNfY++GhTgfwtjG3GG92op2TxUUtqmWzCHzFKaq1nSms ohoqs6sCBjukqnsOg0h+qaEKh+p4z9ptmPY73WdYEfOah2awYWLW5xoN1A5WlYl86Q1Dsclq9xe/ S9D9U0P30WAAY8wpi4iXU4Rrnf2eZpf9iGwOHrrBt8V1d8Qw8b9M+O+mlCb3huuN/wB5a0vUgvwx eDvAtw6UwEt8Ypt8cbp6DhRoc2Ej9m6jxT08DkAtEbKmnUXQwu5MS5J396z9u4t7uCu3hGy2mpq8 TtaH5cxuXkmedPJVEhWuXK7CzK8JcEoevYN0rYRH+MLiXoQaFR6tVTbgeA1gE4qg61EQ9mKUnBlG hzAa7P/RInHmshicLb4jNVo3ytOuu/gulvHO76hTz7xEzCk/kOZnhrAU19rSx9LsnAWZCxw6H+rt 6/SMy3jx3PpnZy6D3wjOfaKedJl8PeT9/oRRkNWElruOxCUkQVrilP1CtjqtX3HafdXUirLhSjrB Uq/5oHNrps1rAh6e3e9RsH6jw5lmj19RQJMJ121IYnA1OUhRR0fcYx25TtJsOrDykp+z5KMJQnPl 6mfuKwM4b3qf3rwyNQRYMmWceJYxeun57SikWUgXmQL3T88zEltD9jePWe09m7Vy0M/G5mf9Ly2o X1UC/Y28O3n/bBFDoCdtEnbxsXDDnbcYAUh9kmFhGEEtzFAIh61Op+tBQj+tATt2S7NzkZghWJLy ak1OnyX273PcmuMp9OyUM/DYtF3VJNznjcQ5WcC+sbFpsk/+LSkyu2Tz2QR5qI7vPXrgMK27u9V3 hVKNGW1f/IlXuEkoCByUSw5+qFlM+HhZHkQJBgYE74hPwK4mRl5YWbZNU3HXhVY6Ww42S/UqE9Qf rjzkOTtzWkzLleRqY2tL+IprFpRoanupsLl1jCmn+5P19wMPadtYirl57/dUZUfwTHiVevkoRrsE TcCl1uH1V0diLSD6nNlFPRUurqGYkmZlMFunDOLQFHLmeFMgYSAoAwoBFQmKz5WWuHOW0uNTFwnk 6e0JxHp4XNkwnFPf8JxZrr2hW9olLhv7zC2fd3vjTu/61nk+fyXIAHNnqaX8Aor8m3CqO4N19q/v ZXuHGh4cO9aOBYh//WSmNuRB4AaaHtt+DPBriLN8SZtd3UftU8N9cer1/+o6ZMF2P/XusNdaTAoL vBhm5Pytbh9+kEYYzud0UWveEgblekdT6ml9UWOySNKg4v/hkj+chnxhPU7jNIWa3GMF5/ey5hdG Pqh5AfQvpX2SkGGsS9Sh/37o/YI+g8WeDmPtBlTXTcfe+zviZfQWMDj4B447jTUh+lfmq31THudp eOIDY4N7W7UdrZ/jGUAE9nrQP1HeO8qxuF1QYsdbXITaOpmbl4xpmP/5er9MD8MNKWEnmqniBren Zyp9M3y4f+9SVjsGw/BwyrIzCVI+v+jir6N1Wu9um6l1RQNg8D7lbNrxnQCTG104ML8RJg5K4gpr U05M3FlQF9iYmdpzUuu1gKbCrQVgwvOu1DBwiBFLSLk0JIP6nv6CAGxaMIh5/hG7u8R5Ai5waJar umHBGQMknDLKMqj3xPkmv6MJWteei1ZkoEiIw0cnBRoxF4CF/oMAG9Vjp7YCexdGpuZS2CwlyI1K 1SCeW5LyEisEgT14xu7UwuScNO5Zykf5+RnY9zUjkjH+V3ggpFQf0LUyVSnaI4FjMYcU3AVZoMeB dTjjnBTCqzR4RBJ1DPjwAmOZZ34lqqOhDcXaAlBj0lquQK6SjkzTipCocufhzKQn7mvhvFv7T5UY xr3bK5SE2zgELIZrUF25sW6SGo2WJ9uZTEuI/XK40BQzRakn9Fyy9RJSy5SMRQqZVuoKWYb83PP5 XvTQpkjOhQF9vnnyDraorJuCpch/+KvrjWqZcgUOLk0AP6YdsP7VmpQ4L58AlvL6Yc4YjFGSteZS r7G7EeQeuop4mP8M7l3V0ngmJbxVUFYncKb+DmNTZ2ml7Oed44eF2M1Qc79D/6qMXiIwsMlIFraF Os8RqRTeHSo+n2iB1cYhhrG+T8gapFlIWNhd3Kn+Diutm8OnCs4nihLNaLCCmhtNbLbFbUofIwDd UJ7SZVa2SbC4CYcZHyVx6ZWklZtLjnpIiTIINmj6jxm86YlMAkdPR7bZqh7w9vNr5nUbjdCzTOe3 qzQTB5AoQoXUWmm6E1GH09oQfodoW3ddxMtBnGNmZ4+xsLrcHk96MyHbPoJl4sPvMzmJxrcFu9r9 RkD4ODQuTbIuAVy014QzruFKtjdlgWXire2d095glx1GbaCY+uHmsk+QqI49Z1FnrQ+Z/O15ucWG eM8oWPSsHgv3HrUQVAZpDh5TAP/EwU44Xu3dh+srtzINcV2z8VZAkxqNzaWCpF3wK7bMHpr7nILR T3ZDsKeiDSvMMPK6RJf+GSTdfZdcKUCBS2PRj0TJ0DabitHMd0OzZTeqvYfYMVzEql8Q+/D0036G nxIbI+DXI4yE5RmugbZ2KUiXjMCRdsP/bSyPXTfE0/M6NGc1WazpdeE7FaI78FHpQEFhi4At9FOi vbzE+AewOHTGVhnXGxNhPzrShK1gN9k3YirUCQb83oyKzk5ZP+iSv6v4COwvth74KEA4BV1rkfAx o/ggqQmsaKF2+TjvKt7SuC+WgiXyJBAsYChwqa4WoJ78Sd10bW94Pc48tklclimbNfoWWfnsKlMH fNyBMry9jY2r77jGEVLaMDJZelcVVw2Klt4xNI5imDX9XQvDtm8HdPME6NrD6sSDLPCM15tAwLrA 3We/k0UbSpN+0Bf7Vzf9Rqo0PxdxyHFY4cAyFlSgRvS2z2wGICtYSIDeHUcb5Krnvz0e0NoWSMjd 4RetQvXKKFinPky7VJC3GP5JRIBpkUnifG6ReZrwZbQc569C4eUvIEcQQU7apW2TX05JfXN+onQB Dwz0+gIe///0wCs9J8r3leFCkk1sw5tLyJ7uJkCRz8KUgjtTIzmKdBS//1dM1be/G3dUk4+64yk9 kWSvvMVDnaoIaZnMb8ndHrIxonw1HCGKa2LyXIUbpXwgZ2fyzgH7HmHRxdWPG5omYAjD+PdF3JJ7 tlSY0PsBALt8pwQjqqVsGw/+QmSgPd3/NcspPgOUaPrhQ9BspEv4odS2QuvuXAuVqJhK/ACMxD2Q gUN08dWMd4QwgFSVa+4VL4qctaltCkk9yrxaz7BLATEbvI9UJc8dnPgbj6gFI/5IkkqzOg6ohdoi shvu6hc+TZnkPagLWcv5EAxJh2MjhrZt7o5/SqfD5Y7+PZR4YG9rwhFOGAwJ1QCZSld0uJA5BShN SxzgYYAJye4CCHMLhcG59UbMYL4RPmAxjt9YKVrzJxVskuWnhT9wEUeIulpdtkYyL043doHQ/+gQ FdIfCZGWyCHjQ4RD4yrMrgyDVlmjpV52ERu99v+jrgwtX3PKoadeD8qHhHpgsstrqrbq6d6QGqud DyJhYoi4TyaVJD+GnCnuolonR2kquKfmxFxLIaQH1u+28SJGcjHB1jnnW1Jf1KRl7wM/tT4oqdUN GRhUiFodO+g7GoT/D8zcC6BmKifAn+7L6nJrhwEaBhRk53cZRFrajpBk+U+riM8N8JGs3c0JkunT ao6lh6ld4dsv471zZQSMUkC+oui/oyAOaVVqxc6YfVDbqZZkT8ymbti4xq5wofqo4miemJ2xJZVf NlFOBDJAY1RsR3ZtP+Na+CON9ck55uKy/l4RhuhZvC7UzMf5oSAieXofQZAHKs6t/xqlRxg6/jgM u2PDAfqrji3btDLXru5kbwlo1+DCF6T6qdoMB6tmKCHmwtrDAK4WEqQWCrnUCyb3dnWN9M/4GSNF UcPzFkJmC8jIm4BiUYT8Ds2wzqRn3mQ/ihyofTE8Ugx4CQRcnDuHr8T0r6U1wiWx3t/nPyIsLne1 tSCsnAAaPBceCLbjYkAAC9MQzE5TYXtXCpvXb+SWfho2c+yk5Gk8kqBxpGR1ACAsvxTLmysl9sbZ pbAJFYnFdkkJEynY6jUBtVE9SJbz9C8KBuDv6xEVIqhYIgxtFu9+4YoLHLfm0aaidLdF9kOUMZdu mGQsZjYfSxBp7xlgJKMo9r6JHNPl1nIhACTTeZ3rNWLsKCMkbvNvoN389OgMKfXkuWQSaQuwME3v +lRQBmckZC6DOFomeskMWe+g8zqc5fhEIi+KmEdJl+o/OpA2XQzmGQb4g47I8osQAycfiTJbmcJz lsI6hs87NgNU7BToPTAD9DJJsl0A7WvKQLgomN0vQhl5wTHL8mcorX2bgWiyQuUyEfI5pfGtCfvh ze+P5ZRgLXHYmwe9FRSO5dohih7QxfZt9wdHe7zxjVlg/+u5fcVB8WbVFt1aEff7QSyVmEgjEuWn 5S8hJVOBLpTO8z0kKgBMzf9eL3W1vsrifU76dBW19kuHessTidvrkXp5VHbSo3iX7K1xQ/t+Z3DJ DrVjrsgreEENcOJ8KM0ybDWrWUmCSZXU7/LRC+myUFfThwc4NMsTfwuCHrVcGW+GwYsHw+UT7qS/ rULiIGfvs903Jufjh8WFx8x7MyAaApl3FKHYgLyV2DYKpVSxPKo6TOZHSPFNstw+XskYDfaVXj8R YDvjzSQA7wNGRQHQ73j4w9dj+0buJlOLh0mlCN1wJmLvGPaM0vAeGMcblj2d3m6V3tE1ExzTesMf XrgWHhTkDkuPcnYvbjiSBZ0iMhH5AxuHupMJ1Wd2n2EccYIZSgawwmrajsg2FNR8dahSH7eSFdkC N/9KHFMaV8R8JbnmgYizZkZd/zNLoEoFkN2dr0y/ktOrKyKh7yzEIV2e0il0lCOBceS9rrfSNfpZ 7BILe9xqOAAy6HGuy0bvwWP+S6201YDIRLO4aYnBmzdZs1RZljqsXthRh1SOzWXlHjNtiTNOLd6A Ut4I2Z+pgHXE51qUa2kr8edXMBcXnnalTruQ9t+pIcLqgaWKQJ/jB4ODSIbuW4NRpfIu7fE/GhYA TUBIwzvaR7IntD7F3hq/w4E44fF6C0dl8/VctCLa/ydh8lzJbTvxSj6Z9A1rX5HiSDRliHD9OgdO zKB6SGFv/v28iOpWFen8MDcWJRR+FJxV3sC1t40NHc48v8XWzSX9y5KfcrfJh9U8+M+37J8Yc7Dd bt/6com2+2qzWFah+TbqDqVMlt6Oq1iJYzk0fYFuOr8Fv01I6FvdtV2rMF41d0MQ0cWD6s78gDxJ TyD3qb7sYZuoQzlnJGZfN+pHln2M9Uyz7QZaHJIYFyBe0NepS7EtIKkWtE+B0MK2b2Dg/6H1jgnS Gf4ECUOnDa5k3ooeH/EJZvpBbbH6HIDgxN6cw/J+on05YEPoqz0rrUnITzUJOhtcU/1vguLhvFCp d34ucFB7dYvMXLfY7vGaKLloViKbiPi5i9fwtQ9PZOzaHPZqHQzeCceo0BHP6ERNCgg2z9DB+xlW orBMXLS1CYNuxkSHT2e1E5eOhDp9AaxR1MEnuEpbmrebXs5piSSNFZf/3FoRP9kX0jplnAASVjbY IRKIsr1PQtpfvKtr+idqTZ043+tE9UqfKErDXJW6C5F1H7tS4zmiBPW7/OeqdhsHPrtlIzhzT8vs d6vQHL6YgqOkvny7zEIskVTrblDdnnW5+f133888cC84KDYXRZ2X5xDclK8IIKM+36yjcFIdv+BL O6IGcu5qDWR7e8MLMUC+a+KczHYzZ22GOEWJHlRVR0q0exoBBFi7AKVAIE9/5eulPrfliuQ6o3zy vHsGCM9dz5KG9xWk3IPGNYPB9WdHdR1PGmeNGWdBa3D7C1qaHAn1L+IxxMF/nkDXO1uG+xsBVcJ4 Sc3z2Dc2Rtsb2j2yivCnSKtFUydurNbIg4EZzVIeZLuj2/hNIDTuccib13mMh+ARoqqYSRAU5As4 QUtXcP7ZusC5+UlFJrabSh2Gu0L3K2LMVOyrP0s/FXaBhwlCVOew80F4hL9aGFcGPFA1I53HipaA xv2Ngk/E0hog5hjo7iyBJTpKlrmHiXMwmuM0J5CK1cSMbTPasFnX2Zhm2hI4Dp99EZBE+MexpaBL EDClgSsFpBspDAFeAPe7XSGhhv1fPKIctorO1Q1qddxpRU/SV4t7vcLrxwKF4dPmpXdMTpVTLBj6 JlgigVfDWo7lObQ8UJb5ogMjXZHBDdZRYk6XcVlpB+fRgObdOxEYhG3VEOiO212AOh/yG77nn8+2 +W5EQw5QQzGK84CC5H3jXe15qdho7sWCxxQVGfiWK3r3RP5RuxsbCESNgTupcLhUEavhRr2bd/KW TtcWLfrgmtVzMhoWkplhhJ8tR3EgbzB61sUAAunUpmG9c9lWOkDlr9bu7xCA+nnwvKtSnkrvHVCi YDK6crmu7cn4S0NAeTcxVcRe9hClb9capAUPCbl6jggQgm2EGR0hr496ke449lkqq7wNghHqAj8e 6ofnz/XGRoHInJjf2UyHV3GHUESSuL3yaI94FuUNYnFX4s0wOdenna2F5q7r1jsU427IyZQ1i5Qq MV7akjAzX8hHQ4IWIBc7C72CgwTYImo/5a7jUsJ6pH8adKTpKy6R/RUYQEc9txXhSNc03hHvtnnI s91WmLvsODakD6hVrV0tpdwwJwcT7bNaAOzyS9OkN6iSPOgYtDd1Tw7jniFtcNlSzibWl4QmwMWn S/TBgTWlcVEJCLwgxN/GRMMzWZD4B5foeEzf9sBYHkG2pHz/F7RSMFkZ874QSgc/MtUSmdcGNdzQ tjiA3sO5uSjom86UqpJ/5Qccu51tUtr6DojKC/ASCrYoB8lZY/jhOskzx9JsJlprToyPIXelNav+ BKtPJMuUl8c5pdO5f/L37LrY5faFcSnSrn7THFh3yCTvAoiVEXUrjyBCGGbUIRP/qEeKpPCvckPY ixgGZWZDy7MivftZH2QMM17HQnaapDel79CWl6GvmX+sFjBjrQR5BALC3lbdDzADHRaBndIAzzzY WUi5/4TY5Ize3ZJUH3QO1fZEAQVGBgYHOyS4y3o2a8OfOS36xwqfnFm3cVBekFmO4h+VCXUVakd6 AxccVa5wrFIC14cZ5fd8SXQ+KCXw9UItHHZYeO7pV8AfKOsBzQ6gF36ciLjFsfCosymXSquG2nIx leEx1cYSANKuuhnRgpU5/4YAfSZvHocnZvCJ2NrthlgRZc+f2EFrXB5dlZR5h7AyApg3cCz39Iz7 QwX3wvC7XD1w68w/fFjL9zf+S+1EsKSVDTNGEzyC7sqlfnKkkNHlRpSwJUhoa5pWziqPtBNRsvKC Y8g5EoMhcPqgkcEmxnyu0zXvkxBYWO9YSIeCN4OH7QGnLo27zkODtEKDWPg95UdCTt67jSozgbvx Dgl5vTDc8xjwZeke8YimQ4bQDSCBlmoVcdfZ7pQ3yO+ycheMEhFUJSMJdLLr0DI7/Ns6brre6ekz KdiYKWUkAdOrkmZR0JwT/AxP5phR+X8mk2c/czLAlmfMX1is+NEwmwPJjyFGEdXgbzaN9A/rBV0i qqzjEQ7ZlphU4P5yqVYZAhT20ZiLVcom1Sf8vYLmrDTMxcHFyzr+NTmn3I5EbRyjUPtYfPWoom5N PKLqv4lEa+oAC9MQ7xRXTEt3Loa9WIS6cHb1X95KjFKYnBR6obzQfDNr6jjQgjxnb3m4gubpRU4K zLTnih8l2v9WQh0ohs66AzVYjILqUSihs8lji+VP1UjIIwZpAMRf3EuutveKebZnK8PN9RVi16Go vCx43nO70waRO280yS9xN6jA1fwO+8q0+Z+Dey4sZyv213aU2jCwYFRy9mjw7svj77xOYuGgWycZ /JB5KVAvzJCOpHHmQ9EvCDEtjBA9rPuCkLrSammIlveavmYXQbNxbYYo7Ykl2yoyBM29zaBq1+D7 DNRrab5TfSqtlM7vHf4d0BCPWpWWkndkBU4D1oK+AFjTzA5pBxzBGU81BvPq3zfd//iwVB8heTXc dgIXHOhGuANUwdd0fXt1k+zIub8sZ1083KparBmFzPLI0MTjod24wg5UNmCzg07piHQjrTNnolOf wvTAeVZTKnjeZgr4BI+guoLipheVHnh95Od1xeWqPjSTjK63A4/X6sdv9ZtwoMMA98Pg57v8H69R Kl3BhIREXI8gsBl9vMc10enXWy2oc+dRYpq/46u+5jIJaQlnqJX3ioCz8rmFSAmJZTaY2eRYv+sI fxRb2UbbtLElzo/7TPPDaSDJiPqjD5ws+V8OfZHaBkburnTO+UdHXAGnGQ9vB54jvV1sSf80cYHT kJFpAWD0EGDyfI66njkhUU197m2mYsMFngj+snYDMK9If+PM8+g+fEaLpcNRGEv+V9cc13IMIRk5 9PFaidKkKcd8y5DICd+AT5OAORLVzH1wCIum+eHnNTCr9zosk8jr27qd79aEByh+bXn22qGiFOuK BJAm/dshxo6/q5DERUICh4GM9iAdzzGjP0owzfo/bZp/q5XU7bkvZYnWIBL/AxaM+MdplEYlarNa tPkuZjQfn2wwOSha/2bY871Yoy5OpoPNyUTUnTG3dq7Aq+KmAWdH5ZLC5mnsn4ynObCjp/6dM/3x 7nllPN+KRcettZ4Ghrs66LbUbqUfH+4AdjMmq6pIIGcmVwseyqxflB8eW7ADktnDg9jCtGGsveuR 5X43O63+FDe8dBlLH46E+qZmwwI6sfZ6dKT00wfnUqYBudScqCa04abJfeO+vua9oC9QREVb45+P JhbvrQCekzQcrJjUtBcal9RJZaPgRZD+6OE36LCrCp+6HbrMK4+LLf77J3oE/BDk5OaAAScqMN+M uADoUbRo2UhYVPJH/ow7DKZA3DJlqCb3TewpGxX87YYDPcYz9b1SZXTcWyHsXNraCWLdZVQxHJG/ PlG5B6DShITvkSFMk+1tfX9TQ+Tgf13dGeVmprpJ74tO3A3+FzvBu+vpibEYFRkf+DKahJP0ZYPs fWRaEPHcxVTasIDVBVjhX8A6Jn7PXsFhY8UMOiWrfFDyNVC3JwsbNE40yUe1NNhuzfxwwuEiH19v 29ZNYBKGDoxE1O4Hpc3IWJe6NZO+7MDgOVaXvCP62zM4dH8dmMQnfymnYljqz4RY1ZQAssMyL70B xpEMAxoROLQQvx0L7N2BioRAesfhdEU99NTFCptuqtFvPZfkyl4HCZP6M5Xh8ZOeXXaxkFkPlUCd fR/2AuH3SSZPNwMTkAyVKNefpdFXuRcxhtg8sOZWy1qkTTOWfBdvdb6Rwf1P266Dbh3FG/QWwW8T yplX8Yl8cj70hULRqHd7tGEZFot74Lwnn/GiX4OU8SgSv8nZ5DGFz4IDv25i7fq10mnaoZnjjKzM u0rNscXs7dTYOsItQmiMgm7kzuwOeDw8AWfCzMCEB/FRtyVOD/TMrH4q2M9hmpk8JQnRGBPAyret P1OOhtDl7kyBY6RNUqKQCNr3DGgc+nvnBLH8E2XgRt2W7utYwtlo4IHtRXtWx6Jv/2OPBhDjuWKg M+oNDMQe3xrkW/i72r9MJrnupq6u0BmbK0Qit2PwAhmWP71FCTkrYnY7FfhjiPZOQxhe/29AplHu qy0EKBRPMf/EfCQ/GslyQaa3g+i9nh86ni9Ka+352ySRIUeYlCoPI6irNANALH4i1dXkH7SRZlJW q7IWcGTV09pVtRtjDQyuYPdFYfIVohjBaVqSynNZh+SJRISXdD8LAzesVsoAN0jpP8bog+DHbzy6 S8SxA76mCEhjj9QghNGMAtx26+atrkrSG3UzNggXILGruxitYtDp9oyOMbFmf6ab1Uc++K6HI4S7 pgqIh3+DXXqu4McEb0g7UNPwinJzCCgU0nNukwwOaIBoRx8uTl+DqASost+G6f+LqimL8/6TMS1V mHdfPtD0dK4WPTqr5nsVJTeJGgLjNP96dHC6SFYzBN9/SJ2Katn5LN+gKigEofb8bOuaz5NiKX9O WaF+vst5xUwxCvrn0abVRLx6r0rncZNzxkEmD6mu6Go0JPP4jJuo4cl9VFobb7fXMvIhENCjDfGX ReGK0fnmFMKc1Gfex5XFQ79sDaYBJ3N8UIEGf0upKqRgTKtIIrbydGZb244uzz3Bop1AJfvOe6vX hyhxkypTzRY+28p0FOZzzI8S3DVj3L4xjQRvngaWo8/dtmrEw84uwwKNbQKejBDf7oWg3hh+mfIo a6maepJw6Auk5dxKgt+2k+M80cQetF6qCbqcZJhKT7ZkmrNATI4S60qIjraaV4tTNRnsu5lOMvjW gnnAIdD/2ZACqK5WL3RSGaeaEIAVXtA4f/Lf+NAxJ7NWBKR86v7lY1E2aJW8kpBkIteH8pLOCSob EXAOqsylDPhMoLkDDPHuZWrc/TvQv18AsKgq8rn3nAtod0o3MflULxoajQzLMKuIsYqd/0ZyL5GX j1MyWAvMcKXVSHlUaEuzMl/HjilKz0CRw1Jy+FwFtPLj0/fiJfSywPvNP9ncbQAuPOgwiZQvmAkF 1K9w1ZjRqQvGB02OIaTP8QHVnSfRRY216yJgTxZKXO9sKSmSynjkZmVhsP/WaCF9/E/kqNUrpoXU pRtCkIF64klXXlOkGZnJcz0ppARtkb3q61qPgbUGSwVMPeETw/F2hK3a3NxqldB97NIzLFnzwnw+ OQzvnfmZ4wsdLU666TXaDIj2dw+lSyaP4t6JSMfajONchex2K8ul9XOWvQIwer8kSXVHDspk67Ek Jcd2zmNveIfGbmV+ZvkUqXjr+doz5Qv2BGm+RiiTEstSSWCOptrkSwhmZiPhxCQPhesvinVqMyJB t8df36q9GkseIm0fHma/QisHO6OraBFm+6S1+4GoCywU1m4LBgUjeEuSvM7zstBU4Pl2l7gfU8w/ 6wb8iyZAiFKQjCKFGYuxxgwOw6Qi71c4qj9YFgxyiWMt7ipRRj2qgq/eLGD/bsTQOcgbTniFgpgd w7pWpckmz5SYolD7UbHHlGB7fpPY9XSQ5G+1dgZYF5fPRbkWF52nHB/wVWaVmDvTcXssB1GfwKjl dMagGiqRf+Nkqg7NS/U8UX1/rFfTDtu3fiSxl3O+POCio1kS+1ZhBftTznjs6JQnh4t5r6mIuZfk D9q6HjyBkMW6+fuY13Fd4JDp7BPulApyHnHX99njifFsGqWY2BDZWsLfWRBqTohv6GqqO7MJZtIt Td8ToLk2eOIWWgqg6k5Z5eViH/Q3ECodchspVd1zRAY5+/8UbB0+zBkqyZv3A90MvXXIZj6v09RM FIUQIGbPAoc9ra4RyWR/rnyHq0rWwUFptn/NQf1V+iZ9tTICF/DFZsuct+/lm6A1kh+e6rHHs2sp fzpCVaa/2gByOWvpcahIy2BDQb6navxA6Aqs9EVHA1o5n2CZvLwg6u1ZyBzM1s/Nhgg2EnUqC102 3Icewu4dBMrf+ivxY7sZGCtZtWww3Rloj3wqTPHCqtbbh1Adv9FW9+HjZPAZh1yCDv9FVda01cDU c3Pycgqmm1hWxeUCimBGSFJRgCc6CSM5V9QTfXs441F6oc5I8qxqE2EwzlLa+zrY12iaxpMDPUbE q7v62VnhMcFy9UHaZ1RBTR8lGMzr7Bccmjogvnmw3IvnY3vWjTqcyy2l88aOmV/6vv35BpJlEC6I cS6+rOO/M18JZU0uDFoS+Sz0pvyubhgAJOUiQ2eFWTkXozMiWKF/SDpJB7cz39HNsWz27CGvWyfi UtUwcO898SGDqKhbpSOuTCth0yd/FILxbwBel+kh2o6ZJCiA5svvi8K4kX+gdorz6yBONZhfUQeP BYx1c9uEPvLHoPBrkejZ/XgP+bJiuo7KKFs+8oi9f8M9ilillKEzoaMWxpp+cnaKrzvQjQvU+Afb h7Hso+vtOoSGhc3OFQdkVScN407xgrcBVuJyuV2pWUL0MUlKqvy8aqnn8puqphUzachKM2gqO+z8 gKUuZmmjXrYYve8rsGhuFZWLPYgitV9Lv2jclitmDaO+IFoEJlDjMiTf6DCAo8/8bGgmKc3sNLLR XXQ+DjH3wg1n/wnorBCvgeTe2aoxYcxUovNjF/frvLQ65QFMPf/p5+kFpLtiMz40yD/URrK/2wI3 RfVxzkkexrPXVR0e/YsjnQrQyjoBHYlUZ5sn0md6IdwK6EtJUZHRQEENt6FwUpY0kMVFdKzHBt8F wn2QxqWPXGbBCaU3G4COTp3rJd6Gtuifw5rxfF8RkbzRF6ASlE06oDbJAtK7G33loirJZxoxdrat ewVLZpl8JdNiV5JWzj4wy8XYb2QPjX5sX8b1gvIh2jSKeIezh3VWVr2FEvAXr2DlVLSC5rg1AEFK lGdo972fnyph61p2noKJS660PreZhrHYqf+ZjkU1YTO/gPGe+NEhdYQUOztin8axu47e8Ke29njO 7jGZ05ndScAYzL9S04xH0f+OFCNKv3UbHWIv6B2usHu9zy5CQbnixIch+D84SAdvJ2SDWBv+QKgh IMIQhcnXVy2mXBw+sMZObR/JV4VBO06D5zjNZNRzbWmIHdHRpRFxgve5M4+aotsHDBrbYLkoXdjf Beg/R6drDosAXxIA5OwRnUTltV9d+XJvTmL6PEKoz+oiLMIzI6MP9ehXM0wSoO0ZYVJ5TQ3FVsU0 6OnlEHZRljqo7KgrqpkUdCtsscqBw0MVLFOg6Iv/ZS+CNDm5YovvY8gaTRILWkoqEWqijouqJoiq haAIqFKGmQlY901vFb0hyUW91hM1cDnVAH3DwwhNsTiQqKyXgqXpt4Y5NLbzSFmFcLm/w8dMt0xO +Wf0FUSC2+x3Lpfz/t9TCbqtNFpYvl/0SPLPBzObPZmp7NM6M6r0scF3Sq9piIvZdtlv3qFpwFK2 fDJGy1WcYs8f0MXkGTOeTB5zDmN7py09xm3urt6TsR8V2XE1awpwLkLTSSaKrwholuJGRRzaHZDG v8Xgjy9uXiN4VXWyxJnDEJu8CgE5UN53zX0fALMMjdz98nFta034VZzhfSItPHkqm76huywO8TFm 31DpGYgCPnhcquFGQx+kRGyUbp+CxEI8rvXenNG0nF0rkY3Wwk3LOU8v+Jwg6YqAoLvVH25UcEft Ky3cQSKdYq14HKY7tlx0ERWZrmht4aY5+urxO2iUNNlzsjT20Ghc4UvDB5BbrmvdDHzIInATtaEr rz6II2ip8PKsU/2hRUdLU39wx46QlG9ILk6O+iF13Qy8whO1UEtcesvtAv4yTpN8fc3Gtrrgm7ek cTws3TV3H7TIW6Dp5Rnrc4Dx2ZzYDfeW/fcJQMHKKn7oCs3oC64YjjX1T511V3mlVsVLkzFR/lVj i5gcHO8QVAyPq1SH+tMDr0/wRbSx6l91ltt0shs+uZrpOSchZ2h213TkiXy4SDm76ZGxc/4uz5se pD7gRT4uLe5nh9+vSOkGMB+y6rGyr4wTGiMXF4eKhX+HDzrBEWyuq3P2zxzmHBLXjK3keEJiN7ZE 9Sl7MFoUrC199TH4IQpA/O5hrx70jVo3ImKoqTILuyjeSIaezZaf5Mey8BryYizjgqTnJOt/kMIl u4YeUpDE32YcWKFnDsNfaBJrnccdjrfFj29a0Y4FqVDGicw7M7w4YtnWjJv0G2bSAlsNCWvtRfaA eyS2anm3tmVnTb/SuMJQuUG61Pmrl2qHhHnV9ZDnyc+QVoxO6GBJ764EQBOPliGMEak8LLKtfS5c WqWh82hToApIBzKEa8gNJBAEztYly2JN8KaOW7DNC+s+bP5YnIgppkBpxxRzgyzvM3N557XW3T/Q cQhjA6lsrzbkcowyIt5RTgGVuyhwMYQ1TpVukTxLhJaXSdJkSoCkH+bR2Pm4ND9AmeQrScCS1swL gpZ6mdn3yLVXruex+asdrWyKB4r48CB11R/+llj94oTdidnNdxNQw518RpXsikNHjTKjfiw6Q+4l mC8eoGtSGc87N5aQwTPiqYUAW1gieK/pb/o9nx5VZPDfPvWCTcGTu26t6O2Jjstku3IXJM16QHUb VXImE2YQPkpzH8gm1XrCaGq1q2I51NTzKr28CPCa/X+tJ31mX7/QE+XPep56KM+gIZgWrTvzxQDj n/gk97bi2b/HmfIRBZzfgdCHKvZwsjXC44DjMUHxREs0CJdUvcyk+cuopFsB8uzkBFO3uhtV7/m0 2FieMAJdkviojiIt6Wf5uLu3iQ4jptj8zSuyg2e0DKTG42wtoJ1YdeRXE/f4sqIm81lDt8bpSMDN 3mP3Osi/vn8KWCTtMHRsUrVpCeEWd1PWi9aHhGQyQuFjRIt9FTEQ8HI4gW6cLhRyqVqavLCpB+pm sNGYTLtm1J5ERf8wh3pGS0/xQaPbMtTUw60AOxvrVF126xyMGhvA7xus6xbVz1It8AldyJCy3zeg hhtrfkQjpPs9t60iQxrXdMIEoR8XKC+5Ll9xWix2IbLdWN5bNustfM5R52/F8di7EbuBtRrIpLC6 slig8tQFlaKOzlF1E8rFOyoBVvCHAPCR5EOCraXTw88fmkLAJG/uA5+IvrWzAvyHFjknXKFqvQ1d p+F8I774vRAYrZrdhXdXuVlwcsBj1ryB79VCgRLag8WNB23voytwIP+ksVr2kj/KFnIyGtqMbJtF 1nuqSfsNVn77VAllJK8LFjewvQZR5CKkkjm38AmiVnBBoGnT5SHJ5lTxCTBT1PwUwU0fAQ7Uz4WX 17vAJaY6RIHQhD5MsQfml+SRTiLrJqU9wU6hlft0DBEUNFw/F1aP1vnIOPmx+P/IRAJQtmhsmqxV kiQ3hM8I8UjNglBDixBu9G2D1QubX6WNn2dsTFONgGvDUk4tCpQgK40CpxF8nLLa1Umc9zM4dQsi AN8A7KPbw1LdXOzJ5OqBAuCHm4d7z4aDOquNEuYMOwC3nQYs9CY4N5cPsCUpkepyvkKRym9fGyhO y9mIfntQxsGP8LQd7wqnA73OGiLNLZtw1zR0+HfsNP9DOWdtcCanHYuGsJPhDdU73M4CGqQfWUhF dKDKrtgPNKKIHJlXamy5gu5ZYg4uLFX3b7pidtnd+d77QOmWedKGQn64fxhowMsc6PiX70FJp9wP jnBRBinFXKLQZAXRW+Q9I+CkOyHAcB5K6acmlAKqtJKpu7VPyFiUp8HhR3zuTIoF1MGQ2nG9A9qK 6i371EIVNzx6R7IgOTm0h/iKRFWZrO29/kc/LgBARQYZVedQHwGF4IxoDLAUA8XQhaEQ/jzJLNOO 08wOdZXbW6m/BtL1BTt4ZeBtgzbwTVsOcZ8rdl4aNv6sHPK7HPCXzE/AI3/m+etWuDhQX4KYhzQy xojWPrxzJnfE1JqzqjFAwVLxFzrjsVkPT+grb+zBucxlv+sWFW04eIA/cG+qBA4947jUiAtX0D9U lzpZQZ+0jL5vUlMeGCjliXWflu8ruAfmnmxjqDME/+wKmCU1Qy3i68FSXVjgwlVqWVejhOMAN4I2 ua+yl95AXtr0LxrOAG0dWdLO0p/25xO56a/KOT3Pv5Jrxyp27WaMpxPjVNy+yRMcC52qCaVQS1G+ 2ofuCLP4tSONSTpUVa7DE3pbne3CCM2pKYwvWZ1djLu7ekUeUL29aamgxOLkGo4cTPLuHa2C+k4m 48pB7uuX5lYIXLMseviz0b8ogpOIKFgajcQIlqvbDHDx2AwEZvBoOa7qacrVhAxEeRU1QFJbeTlS 95+VXAY+y99uplDePFpB2XMoOMfZtf4o47QMwP6jjVDRrUzJ0cj3gLS37WhGT3woGUeBRxflN78H Rp/DKpbY+CiOLSKGfJJMVVgrTFEQUrbtjuF9d/Ut0cSWg2YZK+qOHmfGKN0eNgocoi2UidpBrqu8 KhvNVcGJMotrKLomwGOda/qkgttREF10BoPWcnwcSjfEwmFVDQKcaZYbxqk2YNDx+NXjlLDP6vpN ZOhnrwTQU2PowvBBz9We82L4l3wVdwnyXIFsvIPA2eky+25hCOPuVsZn2lEo3h4nvy8AC/N8a+Sk o0BhclXuo8wrowSmK9sOJwlvWuoYqzISKn77j/vKSer8YO/2sA5g/ZG9MD20WM8uZPG3uPT+Ra7N zJzCx1HBLkyDhCylICJrYVQdN03UAUf1URGd8xJR6Ho6fd9eNA6C8Ri+6JSHElNWa7mhrTYdbsNE 6M9g34P4mdzm1g4hJtk78HV28JinfBUCj6/vQlRDKpj4zpC8LIZu1TXo0H0zMEt/53mB0i4Q3laf PsmaSFACO+BrXKeRe6GMpzPZpbV1Q0t5yjhTj1p76cLiCU0ldmilnQeG9IkmbnOnvBN46HtTiPCu BnhP9B2BYHyP/vsc/OSxsZfDhF2cQQpQ4AaujvfFsyunfFmSw8zdaUrYrIQMEH+qw6t4ScG/7rTh 8lV/RqPVprKxB5OLRNzqaLfuWQXdm7O3MfJrl/PUopZemDiZrCRkQob+4/5rt5lbq/FvEC2H5rJH H8qeqgTp8cbUQv+JR3lNG06c2Fl5S+MgKbk/5uGuvhcjQSVn08QjAVIJ6wrgpvbB4i7N+Ig+gxWs C+FBbpM4zkTpnEOLtQG9NUIV2Vy0YjLiCERDqQFYq2hTxbhcx+Sh6uEtfFawyxjhswIuI60qlX6m xmT3yI/sFkXU9LFH+WWfdNkuWQjRc14oVWpKUqciYx0U6Za0jlS3hULn7Y1vzNPEuiJ2atUfSQnJ ZENtKBLUF4iVWypAo6HYTIDjVZVIZ/rgN+P4NmUQwu0JBdI5Nst7vrsyhxymlT6qguuTEtR5T9J9 FOOnERmyrvVADY8oqppptsqIihsvjnlRBPnpv4cJhs6dy7RRtxE+6uOvISTulP+oSbC4rJvps2fI GEZ48+7andG9gkTFSj3kxJwzXFJyL4tPD1SDAMvs1St3d8fluegVagZFKkpMgwjIjU6O/+wUB7VV gYoCvUey2S7oj1pSP9Ibywm6lC7dKtX/AKI02v7ktoi6YulYNx3jFs2qGoXf72OYGbKoSYjN5iHz 5SJB4IW0WTCpeqODcB5LZBCKwdmaVWjNfBd/SgwMvzth+cJuv91fiNJWvAlIEV5WoVHR/KYUyF2M 4GV+cLI32Pey0hW8EyDYZmCGXP0vbWjvutC7OfDRKZx5oxargZ7CAQTHfQVgHM6jFPb958BnEI4E cmkByNsUXqYHjNyCt9qPfw6mUdQRv1rJhwqKORBvs2xCIx0nyuv/uZCokAjU0vGJm2M2tWamTwRX BCAv//zz8nxnXSwAf9k0yVEjjr0olC+ENkpJWFTfill2BZN51J7Eol1nF7i0Qws3P+TSDBY+TsiZ o1C+qNpxE2FwcGEUTbnNQjM5BzZqIfj31Xo312OSZhUuxIuj6dpo1xGq1q8eAIIca2v1KU4OsdWM pYYsuE/f1GMWBOvhazunSHVRxzuV14JcXFEgAyCfAhdDLDVOrvJ2RzoK3WDruT3ZHfjoKumbiuhG 8hq3u3+TXwCwHaxuTgrIzvVKu44y5rH6hKIxcwEinkx7y0/80hPw9tEqC+eL+SVjnqn53elbDG9L hXBNMJ/FkqWGxt488vpv92eYwQlI8hslNMlwdqKed8twxwRRtQyC891mxs+LdtO0l5ImhG/hWe7p Z7tfbAkzCQdwqd/XAqnX+4TqgwUSf3KSRorzTX8wURKjqL997Kf8N8eufE3IBvjSvVV3P9nQXYuH 8UY3u9nfuBBQDn+lsy5B9AW1rVvy0bzw3t+xXgIZfLTbfl1TsT1rkwYXGeA2qWNj59NaKNoFbuLc vM/Szy0vlluqffKcJkhs8pWN1ywpo+8iVkQgAt8sxIK5GLqkCgtQUpuSVdSXoC/EoVutEsCgyOWJ GZvDo2uWLxrkl7gYoeCAj4KqA1OGeC31zTkPrtyiwgwtLxfaIZIQ/kgqKNQB5P741VkyWJ9p8mty Fh7KXRkrngqDnT7tJgOrpHO9iXpnwCRF45qunapFGQNx3gZuCC5fRkXAqpVbzNkEHZruqqtKuXjA 8vMpUSUET6sd3+VsA4zkKmGpyzWZtIeOGRedpbdobuxsavD+DGfVswt32sBKR9QblBwablV9oiWH aMyasqDBYZ5txh8oiEvAhAwlNBp8lOskEGDvBnFFFkaCAKpfItQ+8eQTdjjV6cxdJmqsF+j+N3kp uBLk5AMPbPecsmaY9LKcoulKpViFf6gE4NHjtDBzCmCGAlkFDlCezYYWJ2WxtLoT2Y/WYf7mnN8B hUA1Sx5IZjT5l+tipcP3jttwte8tNjohfq3eefjq8IlLrxPbSsoI/pl2exU0f/VgxA0FF3hI9IuV JHEHffR7aSycylQA9tvMN2HBxRgOpVV3nJdf8r5/zuOnKvtzVkjh/+TZUMPrSeD69ATPl6kW0jRp 3SPd24ADxXHCawnZgLSGeM4PZo4JHmpB0+Y0ijMZN2J0HxkJfH8+dnh8Lrh/oYpR0PLbNd9+59gu I3BURFTuEjSlDtaw4z///kl516A9of4d6eaViS6pTXjh3xd13yq2xP2j2ML3FQ79efskadLWeqfj wGS6IwvbmIGBwfgsgOLkEwCoWCth3fEEX8S6CmShrBftFq9iwQhUarHEi+2BmprCkdf/nP0V4mam 0XRQSGJC1FIjHOtobf2MQqNvhmFl2Hjc4Qjky7CovBM9N8BkTVMeOd821z98wIer/vr5Wwr8UViS lzuYkLHYOVK5wW6PqoSR+xttvRksKU5UBY39T+21kML+T7MuHDexKQZvyUEVZP5RyMYNElx0HrHH cpc2bqUj8eD8Fl+gtsjZ5qYV8ifFauujgfk/IWilAG8jmSOfCJUA7oHrJApcbYklKE/V5dgz1Yez zf9evCcW+AYTcWVFzOiKfcI3GCcNMB2KqX3G5hDD6il9eHvncdfhcj2We5mFZUx9TqgN5SDmAgFM dbHbjCpNE+RLLlDkMYo85G4WKVda7ea0PIE4Ewa4tCdzbwRf7BGhRefeG30tSTDPrTB6nXZmNYMh C4lDoXSeBWPA9MyprviSBpq+WH/7pbxKreBWopdKF/vCyQ+3t46VvWUN1ZIbEzj8nnrjm6oy0jEx isGxmb3hnBpE4vOHi3nQBr4uPiCVqXcsl7W/ppb+KGMVuCKhpkWwRj98tOAYdU59GvAKnEVo/HaQ 0FMvboPad2Ttb7GS2HZEgqFb4qd6pnR9+M4HLgU3iALeDK2lyVQ94kp64899i8hDI3zUoKxHgwFH iWnaHxXo5cy9snAwfS0krnNTVZSfneukcI3hSunOoHEEjcdKDlQtfSQlyXEiR2A9NJaTsaRFq9Hn HlX8vWOWySNeboCfmjN7hhgs/IXSJkGoRaYloWpxCilU2cfac8w1BZ8RhUsWizbfaL8VA+nR06I2 cTElvKSJgl0hnMnyj1nLExWmGglL31U2IeY82gk/+1YzcHGDMjllDq2zIKuGtw26aOYnMndI4MMt mxzXcjVIDJ+QjL00qrr5J8hQFt6/iaTXL1w1LqteKCQY50cF33I+s4NiHavJlnYQiG1BkicMB+TA GiEUcYqaZa7whCNF01DS2v3gep7AnGJFxODHHiIsMXFdErLUMGe9V24P1N/YvMuTCxtX20xIvfs3 H/ykuLwkFO3SanOJrXTbGT/XO2dtrWeGzjoHbzFI+AhmM9TayQEBNyAnnW6QDelWYje93yqpZHZ9 c6TNawTtO9H1eU2T8pqw3W0j9p6XPWxH6sCy/SiVdSFdIOtEIocUo/UitDTwAbGB+XvvuA1IAsRC R3h3kU2r1/MdE5LVx02d3DgvOCsjWrx4jxyal30fULqS0LkI5UhcWsvhQXtkACgMJJ9BYGtVFGAf TKFNKVBTdXklq1XxjkC4RvnEfglHE9UamQUiSSKJdFUydUzKY7Qb+VNVZdRZVnN5Os2Rmdjcr77W 55pIzBpjgkUvdLcjjIkReSvaneHD3UhfPVDv1Zl96VdVabse+d8JaNAJKzVT91OBC78c83xu/JSC 2AcS1jQphoha6x9U8I9KHa4p6lizg8qXgg8kunc4+VTrkual6jES1WhJceby4SAh1g0FZT2cKfTv L0m+8Uu+5LXwKsPocNqkq/+mRI1INDqnVfwLZFWkIHfa7fBoteK3neZoRcF5E00MyvGwO77aB5lI mKU9pHFQnvglX+lTEgRc4LgL4nd3KDcnfc+xaLiuLq5XsHoQqCpz1I2SPJSawYv75Ov3cUEpmUy5 B+AHLBWy8LxKtj0xQMV9epe/Dc6ROHikiYBL8GJF0G3BUY2aXwbvq9G5deyPP2LuICSb+4et+2PT ycfDEFiRFvUBOSTuk4KDNZhL+pvvjdm3adQ9Y7mYkB01qqEefasQpsHWspO/wdfoRdBjNuPn52ci pka2lSutmvpoobiP5+puurLdbCWIxQHQMJ0rM0tv+AqZH8/FsQoDSYlBcGGrfJz2W0XegTcb0Eda dpyA2sWbUT4T5lzJAbxfzHnivMG+CDx9AW89QOIa8O87MLiPUTBioEQ6PlJwRGVrJPhaVL0Mcj1U YGAj5LOReQxELs+WAQ1W9HIpKzY3OF5tUFQa5B0ICd9W32jhzZLtrXoY4Eg7CAdbZXqxHz4GYCE3 PIy3Rwfuns1fc55B99qSbaJNX9cqWWvf3fj+59bEPY01ORhACnqVvkBLZDj1CcGMG6frumsN4XJU Kii++Cs9xNJAjWYidntSGFhVnJL3yfG+Ot1gBNwjClapkuCVxJqEgGst+Z9piAZ4o/OSG40/m84j Xfoo+Mj/OdyBQ0Qek6FN4yKNGirwhHMpxYBAAPO9bSQvrUPD24B35WJ30jbUf0c0ua48vE+7qIPu 6/wxT39GIJGuYN0Q4FKQiJBuEJrg+Pys957ap0eN4IB6FQuyoQK66sjrozQA7YbTW6L8FMv1kZIB vdBXa7XVw1qYOUIu+8n7PKfAvf8sDSZatq9BqEl/9SogcHSOctwbqHOhIhCzs1oU+59Wvhx8JNcE 4JKkWrxxRZm8RXAzv+99a+HOk57TUVPf1vcrrDO0Lde2u3AZHDNNJTvDAOmCuJnOQN/oCjYikwKN ZzVy3CnIXw9K2CfN5uDsvXzOayMXlre7GlXMvu90jGrG3PyCs08RD3fr+MAUCwHHtWVtEwoJ/NSJ TPn2Xm9IC6aRoqHb26tBd359jteo21Q7Hr/dMj19pxdp4hLArzuFurD0sovTR7k3YwVdswepWr9k c2CPvB7oLhqfTUCjt5fi0yVMKQGLPgbUZYil9O/O48QBSczW4kOlODLaFMwoqarJAmW03ki5ReIj crVKmd7Gv+7PvDY/wej7+sAR7nfEtBsnxY7iLOA2rtQ7kicSLaJ2minhBIdNfTLiEPU2utCF+xip DDqP6wcBnkCO3qzoTYSizRR7/ES7DLis3QydhktF9quh/UNSNU6q5l19QXZssrnb743yx7RBbbef NbNcnoB8/mOkXXDjzQzBXfagX0PpVLK4oG7CwNn5WWsPDnJGhV1/cQsF3bxDp39ZKSxtIMzJv7At +NBktInLB1gAaGfuGy0BCOhrrNx5JNT5/Mvvd6QSMTeyEM6Ev+cfYbKt8ImiItN7aKYLQqaxrtAa yhNUJmRx4OXPO2mOVD8FBngSr7ZeWWTGE2NjEQpdb6Nth5BjC+FSR5X2ze96dEiahSaD5dGHGrPC YsJTg5zC3UDV/eY5xnolJPOdWrm9JC5dwp4n6xEGM5tvSQZA3ewgns1gUa8uM/Dt9FzWrTEx2E7f vJaOmS5QbPh7dlO86kk7Ytm2xYtcliRhGvsY4iE4h9m/ORhmwlud1sI2E1etm1iF/h4nngkm+FRo F5W9CSJ3W2aA0s0RwTEMJdtlEs5KSE4zKpEGKzy6A9bbRXtjScBU1N0PzVpcdzDKTOduVOoN3aYE /I5Yogj2Jo5L9uXYev+N6SekKgdznDgvcwidz1ksvh9PuZ6L+SgFXT5u7chNgo6Rlc7F1loqvaH6 qt1vaC//Bw2rcFli+mZlFealynntcIyexdYPGNJ6FJ5ngr9gQjWn4td6DU9qK2wYWHJ3RsuJjloh BZNUAJu8z+rwxZs8C1APIQ93MwFcFboxJeR2KAQxZOzx02emtFeLzObSA8z+sH0QMwO82N7PeVIk Xs8r2XUK/Nqc/BkLIXEEJh6VVP1yJcJjWf4uWccVNPs4OMPLzm8GEhiX/As1f1DamWUcmkGo6Mqv SsqAwb89Zb4AZpt8hra1425SGpjwTp4KE0troPz4xkS1kdYCFnpxNB/SNe48PZTlgUu/pENs7GYX GgOAlQJUZ+NrOX3E+LczQfY7JfhxhB1lvrk7HskEaQndaedhyTn97xqjp2l/lXoMhvmAiDKWIDNx 7bTSmW/iUvpR74YQGLJqx1CwxEhq9IBbSMMtBw2eQpdimzyfeFYF//MIoFuuXXoiVCazeAtwHaUc 7nl5+wtXOy0GwCI1o0XN4wP7uyxNKn4H62IwMo80EP1XFT3m7Ut7rQkZpwyX9jqEqzbybbBVN9PH 6/V+SFyvllo18uyHXQ6u0zWrBaIWe1LWoMOq/h9qZrdRQO0b5kx3uIYRggmFGfm2m05lbHfTW/3H 1SVWBAya/45uTEju9ly0TSqCX2ywuLPuP9KFhXvidNTGbStE3aUgymf6xsq9W8LQtu0tiC6OKkrH Ei9aei8vYGXWmdY646ImKlijeGc2YDEJuVvdyfxB5//WLzsFRr2LHgY7OlHc4TkCRnT3OlGPUnuM Bjo5MvYZuL84JBdmVwymfHEj7rOWMC0Zfz1s+S0iH4xkXPO04iNS0zkrsv5aVGEPyhgg/90wZCCF /2FkRnp1kWrYBe484WcNTEMM6wDQQA2zMlI2ytfNeR5U7tWx3nO7z99GisViEsoXkDpQY3cyDI7L byUYuTzVMY3zamIbmnSVlMXb9CFC6kDu03Z8wTRafFfBqWg3RzLq0NVkxl+Raf0sZxthQXVjfgdn qKSI+Pb2W0gQSd1uqTT6joBpVYiueX7KrR/ePnmxPD4JLfSXzCpIyPZaBzqIsW31cVVHFe6mpbHI 3t/wBK8de7UagB3XsUlUcqHPp5b1yrs27c4+6SSiDQOctHHTFJLboHhgu4OsRkKcgHo/MuoI3av3 G/xIwEX6pZUo0AftGzE3qRAbK1vqveNG/YCJwet0xatGsKcFBQHu95XhVITTDS0NWa9vjXXcS6Ze ycMAWj2T/jlmmDhF1SfakpuOfcm2NYDYDaH0EAU1eXrh2E0FnxyXoX3vyKoI0msL6GWHHSGOiQK8 hcUgu9xY81wKaws0YvANn896UJLPukSG9E3NbqVQ5Tfcg2QQrVM4iIlE5YJygTuXUGqedA3ZwM+p yo/Ej9pgU4ITBduIQEtY4S2MN3hW4tnZzzgT3/B22UXHhPQQNZ9jLpB+sk5zdCmjWo3Hmg7nGbn7 k58YVQIs0IEeUvWDMwYNUNdtTgXQ3iVRGOHre99eZHEAWqf7GvN7Mj73VRgWcQ17pxbQmBdF2CL1 V2upwef7yCvrT4oqWTSmhMyeMCgRaEQI+wBYxBcGi5rr7Jw5XGsInvm8GqOAYBejnV19kgXPjBWv ++WkIr2PGUr89FC+TRX/0yEJd0STxmlm4VrvRSeuFWJvks1HEpkIksq84dGpfn1E4UZ7F2iMDrBr W639npmzq5smovoc8SOuVIHs1ns+/TDQb/y3aJR2qZz8QA3kIq2Y2zUNoKwmnDuk935e/Zk/4wUY 4IwAO7Tjp3y3G4+kyrYA2Nv7eJ+24IKNp2rHkcwLfwnIwuKMlPgrdzDfY91dCEOTNLU6xBKnsenm d8se29pwXtf2OOrksxYA4jbXHmQaCXaMhjcO7e3ubgAcodyv8jvzVGwPGPn2+VK0UoS+dGUrnTUo 24lzcboXUsTLjpd0Xsrj/H7fQVbLvCs4siFNYoYquPOUGuwoWQaoXqOV0bP4Un8g/Pzkau0tbkCO CMZuyg/jpz86ekdxsMR6zmY0nzrezaaOCn1JxxmYPUH/VLxWCJpGC0h8RDKelxrK/KqtpeRQvmt/ ra5DXpjkzKCl+KlBMqFbA2fZmkhptCvfqb0PvIm50qFBlnhWXh6I9zZH/+mixaiANq4+D3NIGkQL LHnfnP4QslIsHwapoFSEXYWTsI2498Ic//4iwUdV6IaTjjgJ0N1yaGY1AE9gUcxFqZMYNxo05I2n KDq4MS/ASBwD1z9vio3kHUXqbRTbGyhuwupoCsfWKU8fMFIjk79qNeeNmC1PZdLXqixKaZAj1FlH TLfRnwIvyDu3M5hKSxQXWmNVEYkbY1RdibMVottE8ICiR3af6BpGVbqKrFeFF+e6Sg5QY8e2TcIa hB7dSjH9AHfhIXECkOORIdsKR4AmcYLbxKMF9wQ4XuBmsA0RKcfNMJq/h0q/fJMprKGN31QVYKXd yn/pzI4aj8zf2O1xUnMMZh0dZHnoC8u0L2A8juzKw8gIzC5wLWDO1+OVrjR8X4bftQLyqkm04vw6 z9FkK973RT9NyICQIGfnLhT+nscwAxfrdYbfiuTjGY4BwnanIZUpGW5/u3zUYi/ntWMr13OfZhxT /maJKt/EPh+NjoSrxjBNR+4iJ48PSpgAob0DZFiOZyZTMLff+ucvqZBPI77FHTdgF1soqu6606B8 NvTYqzfzls4z2X+f5K/N1nLic+993FIF1Wfv8uQKsXySriJJv7lFfkvwfHl4d6QdJviwjqjdBjF0 XnAjUEnaMYT1EOIBh5JY5K5ZtDK0FAlKMM9VhmjzeqCihcZos0Yfd1i+2ltzrKl06DZ3kr6RdcPm igQMLUEt3mRteXtb+u9r2RGg0kDK/WuOU23C8iMOyRc2bIeUbbR04Av2vVtn3pPs2nRaOe2LFmfi rt77hZfXJkwZrrymSDoMWvid7zgpBtdWcsQmjWnF1YYOXRwQnT5KPAxnR5TT2VEi7/Hb4zbxZEqt FiZzhdjtZs918bIV1b3wQnB2jNLR/0ZyJvQKRuemV1+KnAgoLINKK5m6V/0+vFX8G99vvhvRSUWA wbZ4+veEXM5/crkPp78xgIt4u+IU7qinjr6Jd3Ngaq7RUMr623WG6C4NoQ3uAdhkozTOW7E8dJpe WwU7zPoMQq0nzfBqUXVH407r0JrC++eD8bCorPbmmoZYO6uNT1CX5PEWdxJIzbulRFnwr5pL4Opw vzJCZjmC3aPnkgolWvMy1xVT5t8ewhLP/Hgx93tGYbdsFbsgT+Hln49QoH/HHGz6wTc9xkpkWAUu UQrtxfE8A4tH3YXWfmlmLUiOgn93w16XlhBj2J8AIff3Nw9Ga1UAqX77T3wdr4ZKQ6gvJtQUEfnM 7b9tL32MYBlbrYJzbKYVGtJveAECr6ebKXxVD8IN8mtLafG/I4/hIgOg1V4H1LGmVcbNcZIgtZg7 Pj6jVk85YrQUMO34k2avmLgYLfG+dFAsnbmpYPFvvmNPUwext0DZ1aGuur6Qt4l4VsMuvrbR+SYJ lmAgNAO+a6ZgNLx75g95y3tQKDcoLusHmDwlEReegt4w4LT4kk7s+j0/Ykpn4LASL5hiJsIutUu6 0XNdNLMrI1OQBHcu4UAO/qYmIjTg7JscerqJ15Tmyoj1Co+7IlN/Y6ZtixrGfQNh5lo6ScDOodV9 aUJDYl0ntZ8XVwjCkuIo10qneJbD9Rga/S1Rtcz+iZbaZ7XD6WvWrOa/Kree7BdIhD4LkpjVwFEv CWkBxqzf8F36ABQ6FFg0Blub4lKP51e4FZFok/ztzV76GGVnenJVK9OeznlAcw5b2s9es37ZcyGY 0hiT355dGnSIzShBAylVfgUsVerm5j51fkqBu0Uiw/o0OyK9ETPWNlWw5bEapkw1GNUScrUy9QVn vVggt8+JnOxL5EHQTvc6aD8DQu1+zoJL55LxTRAZ0ksL4Sw3w0m7hftGVOzMYe1bb4csM/+J8Y8G KkgfxKlnbZSoKuymWCIu1Hl0a00DQ+0NZkhMxibQbmlH984xZ9zYbHQsXfdDp2arovygg4J8fbp1 xmZeeChsoE/TGvrVQxIdllRdAUozqW1TDwLiVgVkNaAVx24BNYDduujOBg3A3CRctldTk1uDepar UZRY+6jSWNJwFTZJUI+2LtyLoVjsDdI9ba4tDsykAbBcqRPDQdxadLeHml4TWLMlFiP02KS29Rew hrTMPkwNVggMuOcQ7jzkkBLROioQyqo8w3/vf15hc/nC7qY6QlLQz2dDJrYR1d+2JbpxTHjP6ECC 27h2oj91V2vNs85o0osuuk1YBOPmLSFUGMKzoNVL3SQCpEjiAg4fnuG4Xu1IwgKpNO26mh1BOAQm zFrsQ3rtdaWJPWKmcOIF8vc8CyN5sKguwvmrTsBjwp+acC7gvNIqiL9Ns3S04HCGP5GR+lnLSwLB HQih+vPKDnBy3GcYNCoBJA/fR/9LeyqVejhW6wyB7WFqA+m4PjQiHii9ZgkelkzjXBQ3hzArFZvR ej+VE/cEi1spX/wzPNOKMLhyuEdkR1eoemvdai1vyqqXAtksoxe1tKqMsafrTgVm7SaWHBlUAVRg ZVUCRy2Pq+Hum7IXeGKqvNE31EOU5frrvdRU1vL6xK1TlJ45b/7yLBWhj1AdbZAujWAdzOiMuKsT N0aqkUb9wwx9I9qs8SG/v0z/SwiPBDFQTKUxEd7zaMi2SDLHVQ7ibvA1tKEqwHEhiu0ZFat8xBEd ufsjXH9eD1X9OGeex7SmvzK8uG9jhLR93gpG9zbNyNiEA+AqJOl9A96h831IOVwO24IUUZ3c0PPz KnAw1/Sh/FGP+Nxpm4X4LkwIUrz+D9q+SboMx+unxlRYcGzgu0NMiC6/pKwMRUnZAk+SCP09f5bx K47wXVWwgYAr/Zsa4zNNLdgWgpITiiqBpFu8iFQcrDJXi+KD69zL3kLxEYhDn8Bkd1d0W/PSS+HS NJ7n+5ADdFpM6TLk0uXrd87qnEjFgPLVDb5anbzRzY8zQRR1oCLffNLUipeIBTs9L+e0SFvQ8nqE xHUKA+oVJ/sZVGUv5vX1pjooDRae22GRnGIPmCCus30wKHYsgZ1xNQyg+An2oKPEzuaQwwRkR6a6 xY6bmwZ1QhX6Q0eZSAmKbOW++vNWyfG643+Z3ERJ5xfRNxqH3WoLRBPkgimMc64XkpSoEQNrRzt0 kt3eqZhmDpKGnhrxnecWNGH87aQ6MT+X0ukE6dno2SRzc7EAW+Q6Jjtbdd38ERewsE2WmEQy/GrF 5oD+7BK5b5nmsW83JBvSIDC91qGv5zqcz+hijuXcNPrPoE7/T8wcHRcZwpbPbEdhawySyeY1vUVS e+7oNI5PbID1QtGm61zc5HDJlUy3+JwgZT5yzbw6MoIKqKwDYi2qeNMJLKz4aghck30z2+7+cDhT a5CJOf7F8pejyBtMx7A8oENTbS1eBVQsfUNgodabnymxCzNKX4lgwR+CUEqD0FCeLvAc6Ch9EmdU yNQ5DDkgfg8eXVLMe5+Jz9kZ0QNZgB56O73XQN1dMSlwy5aLVScLRpSdXEZ0QnnQBkXIJ7xNzJIW y5gvKGh3c4oSCzgdi/5dKWrAzHeQYEiZobmEFo4VklCrLog1M4mfHhrQ57WudApm/EL7GGzPemSm HQhCQhSm93aUmSY1vu5u40/k1FCHLtUO5QFwO5SyaO6MoCV2nq1JZvsN+4kxLtfi1tDiS49qweaB /50rD3yAp0NiH8rWGjUe4ktrUrOoKZrr6iXzi4+21S+nLjd0A8DfvVBAuPTMneTUsKois1t+Bgrf nsqKJMbvupDftWAafcBVSGy+b2nsrm/OQJUwfbNudRTwGMsWLp5H+0MJz0OwnTPW7mgf8a7NWxZP AVlIVNjhxk5uQrE1tPmKzNYUvEkuypXnBdD8FZuLytwYxVDuPpvusCrrIYnJjF8r7KaDBq1aOC4r snMqMXOPOTMV5KledrJH7Hjv5X+n9I3qoDcZbGeq/Ar2uqpitaZFoXHGUJHphD+3vTlZllsf9Ic8 rFU/n0FmHwonDUkFl9SrO04HZFB3PYFYhTzNnQcAry52IuL/Q/BjrilD1cXzUDs4D6A/lKLMT9qO +DsVXjGDRx1QuOvD1FHKbpXLfWScbqYUVJNn3FDJqalq+/0M8Y7yp/CdrmnixgjxCFyEuodnOWew /AWTpy90nEZJw44fH0F+m7zIj11xh6t3yxGeRonjDq47VTpMbrSwQtl6XPm62X2aeMe/g+L6nXYo RMnkV2rS7vEcwAGFNbOYa365C6rB1Ng/qfAsC1xbeDNmK6KvFTAnFrenuD+yBpmLBDuRf/4tVRq5 8Qc6RLjLSVsoZZv4INfD8RGy0Rtsq7GVs06LJDp2VhruxqC5Z5yMfbnXNytLHCupczesc5OeqFqP e6XihzRIAXFaU5xAFmWT0Pud0l3DsWchJm9P6znuaKZbrKk+TGKcxBSsICQizIYK+ttj5GJMSXBS pPr1GAnO/hb0R3qBSiWU291KSk+48pd034KQ3LrIfdviwAg27tyjLR5gyDuvYjNZlwAGsh1ySX+y adqWZ/jshBgXrXW7bsuI0BT3n1sGjaHtz6wkxVtYUmCNewvmR483lKHs/C6BSwKu2TSJRbkivT4p nOzrNbtGK2vxdg+zBCNWsnPMO7KWB0IhkkXukNbhWkxsBfVA0l1Hd9aTIFBX0XzExBl+HerW4zws WR5X/AjCr8TJjedqY/7wqiujW+Q1R89vlCv2R4COsC81AZIy4Mq76FGBIWFVgp0YrZLVytWP7JxY b2bGqlSAk/pnX0rI/bHINd5/3uHFbykEJjS0C9aPw5xMO4z+uLig9wiSsBgwBGicX3HVoS3odKZg Y1nRsBDLF/umENjg72Rx/EI28SQM8G81dk+nw07PuRjV/TjPgWnvLwDm1XZfaqwwSYCH2EOuuFTP TvYtJ15H8RFhtxgRQCn2CxZLHT9Smh3He6XAtExAuC+Bg//2Mom5z5mlzcZRqi+qkdXTjiems0LY rqzz2HpfJEdTRL3n3cGcGbXon5DayvB/jWkQQLjfRZtnqVnwhamV2I8d048QVoIokWS603Moq8OZ N+bevmT17h9pBq0dc0ghJOcZVDCfoWiWnSw1vmQKzrODfWVa6LiNIMVrN8r3XyAAqN45pCPwYMfI JylOF6LQXzuoFqaghTbsEGREzsORwUhEasMjl6BKB908RM51JkHUDiekOi5+IBKIfM/1MQILh4ok VPgH9F9uj4wnbJtOg9Ty3jPHDryWDF0qGjzIly7Q77IsTfXEG1Q6zrewE0J5g35A2UGqyjruhwHt DaZeZAp4EhTkLh7FCh01xHjI2xqKRx6UXuGBt1smsgAykxTlXlpujpH1KBt1i5JoNBtVk1jrl4ln hDlAF6g96wRbw7NAUcmF48PzKrnPdy1PyxOrA98sxL61GfYjG2SyM9v4wiYuHgbNCOOAY/Y3IwSl p0EtBGHE3F9MovBoQ2Hxkgud53+frox9S+bx4cgzNJl2KLjZjLwgmy4lEYBROe8WzX0c673e5k5C nNUmQRY7pMljqN5nsNf7Qzjrf9MpRXJaTh+BJBqrqeV6ezTbbvWNL7FfXn5wSgC+XkessUWXA9Or ENpd4G2DIJUvbTmU4cNR5ktmR/0Enj3/VwWjUXbWnhkwTewpg6tvVYtzn6b2Zh+DrnQAP9pWnzj0 v9WI49TlSH6I9+XzQ9cugGzevViox3DjMijF7gUPbL35Bjleh0vBHiAiOalKDXV2+Uf5KurrSoay Vnt4ihw6j15x2OY9TZHR9RCXsNsI+0JjATOIC9QskQcOOloS4eNIFNqkc+e5QA5Ke0/n+/CgaGZy l/aQNnj/v5Jfd9toEOPAo7Co70CVg2U+FASjR3+HMybNv3ILL1t1ci7O3CeOBTfO27mOWLLn1AKu pkIvT9A+XWh99yaQgGM3sI3eRLjfLy5Jspb2MVbLn66/ZaYV5NuBNiraazmfQ2p+7dcp2ixgCBE9 LM3N0HvQc5pogBnugmjhVHwHp17CVxZuwjOPzgDS8Tk6w/7jgkQiHqGN4VMYDJf3GI+iu4z8cAOS 8zHvqEdiXagUitw/4LkMKrrDzE6NAOGpIW8qlJLy6XzYaZtqfrvpU7u0bk7yYHI4z46dCRyOau5B 1ndofI+xQ8ZvT+qnXY7xcgdCIti7mOEYuYdDaCpnQSIQgIB9LmmGzqK4C+pbawod4kvXJ+sNFoQu mYTDuwmeVRUUAS8kJbqa2m0bY9U8TO7K8Ee3P+X+M9Ig0f3QLNU11/g3eCdiDV+EAVj3FPLkAdwB MiNKaivWpIzWytdwP7neKUkXn4xhpUgHmwLyUf2n2t1DQq/wa3rTtqR2SJsxtcJYfhAxwSFimMey g7Ku6CpIq/NdIvG1iKiW8Fbo71pO8YK3okZz+zAKHVpM3D1X4b49eYyd9RfPYqOlxLPvXsuKiWKl yy3RArVlIi1y4SAngp1PGJb0mzLv5cUTJ2iJ77CxDHN4TBexaN7ttdXuJyQ/5O6l2D2UMXCNdHjO qheWeRCNEvrkagw2Y6oPzpdBnJlyWU7cgq6EMbzzMu5WOnWe725YmzKI1xgG3mfVO9JnjbyNr3ay ZmVOuitaL+Zo9LmvvvvT0rSAk8278o3MgDkIsxJrwawfjF9E7Z7ypea95RSiN5ARW6qWALkK4c2Z EC15EXa2ggWyeJC2UcQgkt7jM1dJphVRhuaKa7ZA14DT4vUlyH44IPa+M0vUedlNLeCe3GMumt2U SvkalL6SLLU8l3FVgB9b1Kk2slCuH32fQKcX40N19xpcRx3SnA3IvlVp2autDMUoqDC6/chMiHIq BxkVDGqzDkasf+vjHUdoViWm1xo7Uren/X/TZPPZoMke391cOaYJiye9nFz+0Qo86U54qPdrg7CQ JzEb8JKTpr4QIXQZh2bYkT93xN+nnG8AVfG02JEb77CFynogJAbRlklc9nCt+FrQFhLxa+KsZcdI iPQCWmtWciXyC7CgtkTYyvevmLSzb7y/jZtJGTIryntvnzman7wK4xiqqQ7IEvxQ/ZjuEk5WaR1i /qzo3+zxQfjU5acHPJm5Ce3A7IjBdTgX7pdaNO3yUxQmKXS6NFIazKvIuuBJJkbLEiY8jlCDbOct DyRhhVR9q3koMhAnmIko1t5eacEOKYz1nW65L91v3hxpiqcuEUe51Bj25/6DZuRipQv8uVX3GqWx pdHuYDwEL+p7eKfM6fWfLxVA9bfl3pZL/xu0JrGpjgY6h4lIwBrC8SVl1b4Ei1SSZcFhIFUAclU4 bD+6RqkDy8OBLQYUHdgsKuEsIa0ilenhRBqykOLw0FCPBW8E2xISlxrQ6gWLldIarsc+ale/A3YI 7eK/vntBlbIt4murfyOtIKCkVUaDMubaCUkuZ7PLMiPzRU7JVDe6ZMJNHH+sbx3Ro3fXX0bE9SUl U6B0LfkfPblK9GmhNoO0ouS+cLZyI/2vk1baxKF/vDFx94tIPcoSWFsH1PsWh+F5V1C0U75I+r4b Rey7NoZ+QnZ8b2pPiUhdMMi27dxThBui631aLXBANjCvaJi7/CTaO8iiy90xDR+SpqmNC5EqrM1Y OY11oSV1vtYNXOKmhibce7ve9qRrI1lxIYTepaeJ3w9rH4OzpSHYviHltPT09sw3yQgeUMnZZUZo Jlkq3qPO5OmlHLsGn4pdHMLKCIkWuYv5+r2W7Ye7NUj0YkSMHjsF9GQdR8XHUGyGLUTJREJcU1Vg 15yd/djYs47ZBzO3DDOnkTouY8HVR/I3E9q0TSGABLPRQnL8FLU+dCruiYF8Fovv0sq2qha9UBmu xb2K7+T63kd1BwiT/OwcOeaM53cTFCitTb4R5e6m0aEboUkH7ThV0MZCkqS1TWKuZVXlBIWFcRBL WZnuaoM9JMR4QQyW+vqTrKjFfoB9cil7dFtteFlzM2q37w+TOH/sfmrf0r82Qei6SQl0FBk8szPd nxhhCLrUTumdoRFSXnr7Kdy8N5CntRtoJ+RUZLtgzOiVsnkA34U4HlnHWhQXjqKBljOnPbB9gZvg RVb8y7fdhRHZ99osvJ2E6nouW2nLmSGfV2AU2SHbvvu8jDNtjxZhi/zXoAqNIx5TWwkDtuOiF+2P AY0//S0/+bJSApFjd2L2VARHMfTOBOYB1pRGlP6CEFV260yNNDxxQ+6NVg18/NHmUptxefd6eHB7 ydci+ZefFP/5XkorokULfZlftsyFMyWDjMDtcbRXPVyjk0p9uRz1NE0f6D/VHU3dIPAiCjlGOc4E 04FqhM/QHOZLCXRVUbEaJOKsn+iVD0gFc+lFz5JSRo8rsU26IMHT5PwrYO/9uisdy0mtXHQ60abx fJjjRvn4jz/XB8cmgz4xtt28xA/mi/I/25DemIOn6S1L49wvdFzJepcD4uU5wSAXaMM4fMFMi6Iv mlSklZuPyeMck7fsN4wYPimFhyNXG/9SsypqjiU3/WlTgL3ixnHKaRVx4uI0EFrEYV1/BHbVMRT/ 60jQ9vETTWY3klVkw07VmYrXbomXTMTENWVxQObvLDojA7lpCO5L6inO0dmDIF47QaJClWsTHet4 2+nTbd8PmxMlha2ae2npDdX1fz3fIjd/6mxTv+0cDRRrdQq3AVYuX+GxxxgpVvfBtzA44y69/5ES WAfI12tYaM6EbrSPWGDhEkrGw0SkYmWpSTIGVmlGDIAmAszy1RCjs+PnklhX2+ZTfS220JHRFR1J TIRo/91r27sTnyf8D21U1gX3ftloPo+k0AT9hELCfi1J600eJDEHOsI4D1v2ykXWJ0w4QyMQ0572 LJM+h5gr9Mfwwe7LB6Xg69+Fs0gcVqb98IWdgXcYPsPdO3RRzyN4vDrTM65wMuE3QQ2AyatIQf+C UmF7bxmSY5hRUWJC47xt7n3LRzrZhh8LzpxOWA8wPsDARFMIqIdyqWet1SpJUiJrVBjiOMeCpkA1 9yZhjZo8oMIRoRMaBHzcJhHNPd7uKltqeeNoRGfwZGt0/CDZaKKp2qPGAR72b6drQ6yaremocPkD +9iEoacc2QHMUclu8hxqJhyp1/Dl4hNx4c45b8es7KxXb3kP+WBYwredRq1pmR+R/SKVvtH6+IFz qsYXojy4WTH8mhM0F8sir7al6qgLVXExMEMQXrc3z6OcdXV7GRZSAKf4dyt2FzpYyI5dMHOmuUac BKtbFrJ2fHann2e58u0Cw5Wfxh89kc+nEDm9dBEJLV4k7I2pq0AOAFqNM+C3rmQMSR04PANDwsb/ l2jZvBtwb2lXH++N0ey4Cl1VIlGTBYWdL61G54uA4FFZJ/bbPIbSmbCesph0E6gLycYNIP5DdgX9 QLMeHY6+rbQb89y3mXIh4zK98UFoWqEI0r6Qm0FX5rXj1GdBHgJxWjaTB8pRLp57f07hQTU2Jm/N uQVsfVjp4BUtryjK8dnr00QjWQ8j3DVfukIOHL0c1CdTI1gFZRCA9yEZkjRz8bbQJWRQpvvUETnS UsEwT20mdYASTqPhq4fE7hIpdi/hXCoPB1NRNz+lNC+ioMEpi3lCcXEvvIRcfx3lUL+1uZbJCo5d sDGWqpArWWfK6DBPy9JwAIIUkzu5mHFupUM0F+2c8lgV4HvxVavOJIjBeQNEnTff44FVNkj3BcCK 2V/Li6O+xjFZGLUjXBe36KdT+UMd5i+9pILGpSOB+MqN1TwlapZy6HGxeieJq5l0ZSB2BdbhdmPt VMYLbw+Zo8GR3LByLRdJ7wgb3N3hqY4ibpzPZPZsoBpLWiek+AWsscT/d0fsikB6eYc2JqfBB7a+ /HTm1t4RNZAub6SmW4k7/a3lzTscNU9/5nzEZxMfQB4wSUgibkqBhTBVmzcquYLjlJSqsQXAZ1Hm Hm9ZlRs7r4T/afYTgwDmmi4vQH+q9VXNZ3hZezhBIqoznY0KUGkROLyUNQY1kEZItgP0orGx7gfv x1ZmORJGbyViyndK1f0EGWA5ZT9BpfE2FbY7ibXGGFc0jdgPKkrFOAGXnraC4j8FUjJjq/vaIpGr E8v4WurTQIIQDYxcDcMHsxxNSo1XuvSURzCorXhLgjMTEXyxCdZjBFUItff/x0IQ8fWm2a4Pp1jf MNgkTOVN9pJZfZeozoPZKICSxfaXMsBEA6fgxs+dqtM9QYlN2PqoHgkwQns9RSXH9CzFYC6nPD18 wZ4HTXXrzZHTgR83LHjDVaJo6FHnHwVHQeFXCQGqRsqcLZudpNuLxHUu2tak1aC4LllChR8xCrCk rtRcFLnbqtiFQiaEMBgj9t1fDWtZOiIkzQYLoCY0w4zeIeHuKP0Nr83XScnW7gLeGxBbo3d8QjLH I5m/GPo38n2cNfU9/XVgHjNPhUAdrMJA5AGQCFiqwwF+bX0koHnrHmE3zs1/dOV+57JA1TWss4mX ZY2ZyrIHxxTu9O/IGSJmMRz+SlEbPL1Gi5PZKjRjZtpvjvPQHVvjfYvhpoxzpVS70k9MCB2V37cF R4enQctcC1G0/BHSb3z5/tuozCA8cLzJaPqMC6owu2eeWaNe5QREYGH0u7Yv1ikP4gg3iW1bPJc8 GBZnQjRXAezX0P2kdYXgN0eNuvry6nTno9sLctnuM308ZelyHJu2nMdcR/undnWwJB6GEQJXkm6K b8fGtXnpCB07E5h2VwylMnZhbbCBPszKoE1qONR2trlxOmtjSzLPeGkfaypbo/zs+vcwdCS0TI0+ lUgvjnseu/cgCqvVhLEPAVfBvrDO0HO905OC3eHBN3PcuuCQRmL5I+6RUm4zInQz3i2HABm9ib75 Ep5tCuN5WVqD6Hu1tqbN3XwwlE9Sr9HpwjjraZ4HJaYTInSt8sqFBMGJlROtvvJksLXqyk1Me8uG K6rcmYd3GYW+ORsNSCLzeKfgPkF0xYOgLWA8SmTBZhtcjEB0sBBrvGF5g77GRxkkQLgSXnR0R3Ia McBOglUwtmJv/BJXQJYBf6Z8emO80R8tKJJ3JnjojioGlRmjVF45q7ry7+V6Pwn4Neg2AlwT7M0m Pf4zT7lRBZ45fnxHuAm5aC+p269tY/S/AtzooLxZFyfyT4drh9H/JGLA2qfOy0bZ1tTlzWncz8KC OVkGqNRwvGi8mGgsviUyTV+VHTkylCLRNGI9uThMpmMqvcnccZUSF0urELz4Fu+aZbfzWE1baAYy dbwN+XOW0WOfMzOECTzFu8YqYLbZ11qk3dFphSZPwf4i2YNqPX7myrxtMdW4PjXogOZJNpH7hcW+ +6ahV9i4YzGuZm5QZ5/Y0PlrqLc6f9VV0Y1TzOAGA+CIl5YQHsDCu9iKZdgDggQqHyOs2lRNPb2u GpcoF+olUZ8RBwI04KfsDbXww7+KgE+H0hQm3MTehPkY6cWOjjiPquJ6anWpr1MKcLCcYrxwn43l ctEAW0Du9own2nUC+tvOKUl+1HXBMIujg9LN5WEo6pSJypGMf/FFkUNezRtUqrOlVVv76szvmkw1 kvrP0EOumbxhH0x6zAqHJXgjtfY7BJ02m8IV3M/+hBNGUzX0+XunHe2F/+/Z186EAUWRHg7VE6tb gTv7fhTk/72nCjYv3O+xPyM3SAtAWyNhtJVzTg5DkS2sF5wJ0Ap4ooubOFE5Z9g9ifZk+eYkRjXk a2iuh/fFjAMFmxQ4RFap5Imsd1sCjUhNLH0773/KYwttPorp5AeAc6x8pfXzMAP3+JpT+vUAEPk/ yIG/JD4ylYLc7TU84Yr+GhCZQc6qEuufx+CdO3ig7bmHmBI2Prol/fojoj3+Gp4HNtXfQTa/vQLx IeIJeM9CfWX4y5640Zl6sTdD3dVMhlBupL+OYVU2z/YQcAsStmk1ve5Qm9prqRc/K1G8gdu0b9P7 SHUD0QXmDu4EUuKq/+LcN0QEVEAZpwvcNvzTDySecCf+5UpjB8Rj8FLZsfalYiDZr4/cneZkQkiZ R1VuU7Ra6+TRWFjSG7T45+uxsiokVnBYzvYe8NoMn9cTINC+X0LUyGvflETH0n72pCI1JCRwyPv6 w8iOQzPhNSS44eeBY2GhDnh1AtaW0o+kHH6NS2N9lHhrpsIwLlUh85VZEOmWuHiZPU3jKQDcfcHl So4c4+w0CYSlcOLeTtWWB4yazW7dM3s548TxxruaSYVI8OaAcXaaVbGOfLXmz4uMR+AJkE/lxTLV jnlJkUwyGfjVzGbHDTQ7LfB7VGdzamsCxciyl8igEOmPvU2ZiYyI8rhhLlzixUjqBWPPBFPnBAGI Gbdk2kZ69SliJDrFE/+tgy3vRDldsqRenIsjNBO3L+S16TSvddXJkUiM42EQbgl2aDG600bmCHNm ueC0oQICw0qRnBhIy2zwQqTX33NQP6qzZdZUxBrvSc4JmT01514vYpm2BVXTlF/bUKjfMgvZlh+J VlPWysyBlpn1u5rhK3gPm0uh8qYiAVUUdJQO2wG+xEkEWKnRU7RBMvwk1boQdcvL/pQzv0qBw3Wk h87BkbZyvWoktsx2diY2tA0w3ZuWv4DM08L0qCQkrYr3g9Lhe5kBf9QAv3Sg06RgYt3ZOQWNCiMj LzBKG7+k0bbRZ8QI1no6AzgMj9AkzVbi22z2JGuJiqfeq2BHXjVu9ndd/uafcjyWjoUexPaEsQBW +L/bS822p1Wsbfqvo6Kpf9JkyDM7GTZCvdUDF4CKeSP5usd8PV7Wye3EdFrMPc2bEyaS94PDJ9Nr ir+b0rVvlpHHn2oMuLlm2fkVMvUVa4m4BVKbrqbXhvuAjd/kp6MR84nKeXDNk8sN2wVzw+cZcUiv KY4y++0pPGqV/3lk7wUWramQJr7fQuXrRvtB5HGc6PhzQIwHNbvp/+9thl6wQ8TH1wCRplrSGCqg VUeo++Jf01tldYGWsCnaTGvn0k7GNw76hE2Lx5WC07scRxjKexcdI1w2Xb/tG7WPPT/4Do/n27jI GpTyOOQgq9xUZHAi+BtyeDCl1euIOKVC71yLX+As6qnIk0s1FZTm3xeyoLDibLXJ96Dq+/x+JUKb W6ys6JDDfBZ6LIqaKP0UznNZZY5M2b79J/6W3vNfZghIlKrAbbBJJju2+8JpOICnluaJhAsscTVC YI4SfYGLuQLzU74214GPwfclYPTFZaep1dU3MjcilzNcQZc4kFq8Vjp/uPBAe7m+zW6wDI6uiIHc PqK1pIxjNRdpNSTbZyoSxV+SPTMVk9QBYD6D28Fi5Lc1UTAkVNPqOxn421HXiIPjn6mR/tKVy21m xAhFdU9EHz2CnUchAz411pX8amXHO9iDziRsemgXmg4CwbKPb4XVE92VU8VM0vIdhXkMJMC7Sg+x ST3YsxJjgc04Pqq8F6rbYlTwUazNspfO/zF45Lg6Bx+n1HxcUss2cxZ/Cv2+m90FkZEDqILNV/y0 IJ/5t1uYV8RE1wBdbKY/qvIUO5MZ/oBdV6acBjExXXSjDfAyYby639HYefK5OoOVk9mq5atwBl4q odS4y2AdH84VTHZa9jt6ThWmKELDqIXvkORhP7l1zCt2vC5bCh4Lg565FwxEsu+BAYbz7rGKf0qW C/IdwAIEc8iJsGUtv8YmE6Ddnf4lLOOI12CtJGLknO3/FahCRw+2FqffG40gm6RH3qpcrmnRx++Z zKC7i2T4i0Yf/6uKDtpHN0HgfHIgrwqaPGiJNa60iMpgZRrAeI06jzNLJ+052ZNwYwzaeIfukrJZ Eu/uIhLJYI0cFNGbq6SoietaKQYischNpFXI+9vEiUZ1uUtOVC3x0m3o6Af+KAPZgAzv5Cpg00cq gNq2Ewg/uKsy6OpiRt1pvd5I46OoaAt43cKof05ILzquq2BlfMkERw4YLPqEmRTFnqW+1zt/5wgV OS+HCIB80fVr6blX7dR09TBpu7wpGjN/TEOrRkkyVsnfTy/bBkqQkaQQf/LIvlftOPr6uWjMmyoK 0VaWXSdH8OoBWyaOC4WxvH9lTq9EaWoB9dt8q37VCcUh1z+vDYbboY27niIVa95IwcSh2LAQ+5OW 39U4FQVND9PA3zXbQQL28r03pZ7CSrF7N8O3tkMzgC/D5t+b6tmxr/ay1iU+LQoQBALR1Ybxqc/r ANpMvTz7RhAoolu0Vd9AoBbZpwLNks4ZI96dM1lwctU0c4nAP8dDgKeVBKkopUSIE8bRCJn9yb/0 j0I6Qomm2GrjNXpSNO9/7QLtgIepK3LYWVHFwj7FbRAjxu70V3n6mGI9QkHDHaOOQnAJm5bcdrKD xcpKGSq6Qb/AFmfIpj1uivh3xNJFh5/OxFAUWmiy7+Ru/57DIQ+N6nd8UlfybuT/e8TM7T/O30ie BoovgQJMQyWhjJuDRRcwf3vEHtFf2TG5u2Y0i/s1QBiVB6KQexI4xyDd3PPIwD3PpIgmyyQF3Pxh HalICmef3ax8PvIoS91p2p+J5KaYHxMlIiDsnNxCW+GHimtRceUqxmseY/PGtw0q1unKX9px87x+ EYqHoYkUoGc3VB88dJQ4nvEtQK4x3qiEZ1xQP7kom+z5q9R93GoE778lg25+dtSkXhxgINIFwIVM suXN64UDDoMNWiLdG9UPTUXirdRLTQfYb0E8t79gYvTo4qhiEj+MrW4z2xI4VRBx/m52NH+CbDIR 1oBACyVlXMkvEh9Cy2Yn3T1Co7Vupvu/JvsMaVLDCudvU427f5hrutirkwcLEvp5vRZleFHV9e5j ABQwYq6Exe+PqnmVKFAq+Q1aeU1Wrd6IuSiSXh5vA2G3wl7t3Xusc2kvFDYq/k4P3T+6xolfXfUr PtVMa/WSVPuyeNOxBnU5F6FtuNF4C4zUbZ3bUqqzgwiFGnckf9gE7W4JntBRYGCzQYT4CSRJdi+w 1g8nCmNINEJOxGPApJWkzNvD/QnPyjLON7QLezG46frcrlvJwid5nqM69fMcBrzc9yqPSuU7SAJf 4gRIjPBfmRak28B8o574hcSFUb/6Igb17C20+4v1/5v1OuV5nES5FQmrRf32MrRqPORYe6K8C0ud QXFv6oIv2Niozd2/VrvC1XfBNcbOcWWOVB7rlsiGRZMG/Dl42xmnR4xBce7shXG6xnQviyKGdlCn WSSdcx+owKPEoswBEanrZ9TUvrSS3SQVgLigMA2bzOA3d4lqSzzUtoYg7JwTqR5uGv1X2F9WHoe+ IaCVOEyuiQHtQpP5x7Y2fLFW/2S0U3kcmD+r/5+VpI8LVZM+AcVpBg62aQG608oKWQ4dskEZfg8H 6OnCQOTSHXHjIAZXe9MRpTct0/l8GWa86BLm2Hof5qCR9lI4YE8ynh+Xl+YfJLMmKxYsKjHzpUUC orAhk2GHX7QhY8Yd30mt/Z4CGF3kiG1XQClP5OF15m/V98Pui9rtkOt3/d4YBPE68AGtKxpF4kWZ Ti9DWX71272YZ+SqlHqfofUB08HbDMElHKZG9QriULJeKpNbiAeCOrHD+vDVLXskiQATg8mrlePu b2dY449YZNwSrp6++9LX1/dbYIptuDhUWzmPIjTfVtrmvmsmIczE5oOHEaOfQGzR4U108Yjw8Cpg 1S1RTD3T5/VPPFOZgSXhgaQ4vTGdTrt/pmZkkhlp8mMsTX7JhdjewK5jEakCcv1qJ+x1rFMq+SGz eIczpdy2DODcqow/0KwctP9Oro8S1pc8EPRVYMkHK9ZHCzuVqHXIi+uESEwujmyEJ/LYPFG94Wok K80zi41Ji5GtFyu7oqkN0FiFtKgNk73/hkU7vF1KzcgSTcgODHs1nFW9pe7VG7lZzltYaKahMUHC XgEHWq5qbEcXftuMHcB56JUJP5pq4YOW3Q9iR2/kSWRF7pUaXrGL2B0xuYB96rGBNbjogmo/XKMw 5NSeG4iME0PlOej7vmAYj2ypesaKVgmt2KUVchmeM1TLtBhaupUWLV5BzYGXS8X2FzZslBGEGB+2 ac0vHY94Ruw3TeSqjz9/g90fTMMszjtX8cW/ee02COnhHCp6b2DjXbOGjAJfW/+U2Ci4FnposHe7 VGqgXT6C4YU3L22pc467hWpW6jyXr5/Zac1yT/imoKfGaqTxwp4kfRlMpE4Uga2ECUP2BxMxDiAf 0MWgqIA11MwYiprgPhCBESGibVarCKAA9yJcF+K/KU+Ody9tydiXn0Ys4nHJcZ28P/NNTzEtEpNO vl3c5qoxdR95xS2eYbDLV3XC/gwvHPa6RR2pzA0i5dBd0Fe2g4Mk2QLgWfXuZdhygH4rXY/fKZwy inODaHI40LP6t/bbpLKsM5BfplN4wDC2B1E28PiP2VENMBiAO7s+U/pV67RY6z+RbFhJ4qdm8F5f KgX30q66iSGEKxeyaTPbJ+DJ9W/LeYXqjKTBOrsgG4rQll6eO7ZGWG6Tnv7A4Gnt0sVj9QNpKUM4 ypPvuCJS+N5oMnOimU7yVHxyqwWqNjaaXl+6NtnXXYXJcMrZTzahBIml9NatqNoV96OpPEG+ambO pfq63/5kGVJJq7+3pDv0MQQVesHFG8BnrsExlzItBscGJr90ROOh/j2gVdgj8Lb5RGk3oDriOHJp a+HdtLpftgELBOrpyHLiTyo/mKgrG0S/a1e2pMhadWpgW0LcNxd8yl3WqDpmdNgHxJ9W+KgzC4oR o2PGjmW8Uw637fVikGHknoiuvdn+s68+zfBIztbpb2xr5kbS73zhQV1knHixT5in1t6fnhJ4mwpQ Kjo08L0mvRQu73ha/1RTPSpBbNlf8S38q4KqV+LYcqA+rJnjBgXzPeSKRug04TaHb1BaskoIF/+a hUg0NckWpywEY1uhpmr4HiL1tYek7QPMgz2nQiky7nreEzen/P0ZG8fhCQnAiE7QidFZA4f5Hn7x /e52rLoByEF9mIYiRgy4Qic2fqAbbJ/2oOwygEgf70eg4AKP3zIEb2Dh/dVj5B+rb5Ir8c1vIXsg JDJp7XHtthZXMVuXVgtI7eOA4PsGpqCui/rn5toOMstSPHAv3Sps2/TLfST4VcxPW8YeNqynG1oB /p0oTqZJoSh3Hoj8GdXqwqiWm0Iu2p+JnNHOkCEf6c8jFfRkq8BUyRAFQoU1wjT2yj7mwpOB6ZBE KTPi8aKrQwrI4J9uJhGVzQ4RfK13QyBvSatEF0RP1avcykHnCjJ2+/9ujZ1mAFYjFTLnPf5hUGjS qPginKpEPrSuwTB0djnTZvMRpKf0rbjws13SrDiXFbwL5Teg4fJoL+RkNfdX7IC1UW90oqPcx4ud 4i1PDsyOS7ArHzhel6U/nHFDu6fiLGfa3Sw0/wwGJTp0xRdFKlrjs6LOvcOjCQTc6f4kPd4Zg68h V8C7QJRGDi+t7r7AGGyfTiFIyYwtUoQjEZ6fvqNs6Qzztjb72zko8RuJZnj/w9FctjJjPWObkVA8 WfZ70/nNDr+ic9cFWmvFZ6e6U0TWeVmkVRrk7iZ3pCzSTGmAOtZdDTsyBphiGz1WdkX9Bl5IrZYg 3nw91weCm1UtOTe8y8deDRrRckFDfsqlpenKTPun8mYqgsLb6TK9r/xsksBciAkPkhbXAYfIEytZ cQRZhveYxHR4HcPLwmdOKC61ZgJjYpwFPC1y77dyfwuBBcyYGeZZawL3xbZbagoSoZftBTxXVYOH 2lRIEdoL9r/zfDMXe9pTu/28UUELrPDxmV8gsCg1T4ATg2xo5DNLyE6JMaRemIdzzBIVutgJv0Qh 1OJR2+1lASwMx7YtcAqdINQur9xIvKCr390Bg7KCcJo5KRZeD3Y9hUjNnt5TZAFdVe2FTFUtvaZh 5/wzJ0bFlGA1F4HEBuvmbjrUDKO4IbGryaC2wphzrZ4U00ttG2/kLFexiNfS2fKao4kc842ylvSI 38lhbiwjaB35zvZ6EjafGtC/q7lq/HPJVtacsKoXdSFu+cz3/M9Rhbcr3er0ztDEH9zPpXNU0hRs EkZej2RG5zJIlfWFWb7eOydEHMBQXs5O1febvB8evxDOD2FTSCoKDkOfKAz8+e2hb3O0LABAxzf1 xDOjp465REvmt/TM5n8ZQ07JWfWkYKGuLe1tkuVls5RA1vvgSK0AO4f2pB6ja2z8E3M1EQSzPy6K Rj4JnOU7f+V3Vsxd/YICTDClD1/u5svVtUcZ//nHQTDExLMf3jQ0OyD+B7k6ETg5C6HEkRUfkNp9 B3YjlvjX+RzSmCMc9Oqurw1uJ3e2YBXgNL8BwsRI4uW5Mb8qh3rI3tvWvL8mEr3Vn3iItcxNH4J5 ecCsNvey1YPxIH/FbQ4QasJdgO4HfxnhNW/M1+YHAcJbkDAZvfGlC6BeBV7PFImOJ8d97mU3ASbh OJLnVuIDfWCwsR1qw05Y5GLWAyFPFJVqhvBbc0+xEoYpu41qK93+NWIHCLibNCjuQzHszVfKQthm 0Gbnjm0pO9tE0AkFj2cJzud3/KMU9S3Z6frF4maXYlWhFWDikmvOndH66vSqUsFNbr6djjo3V5X5 5lIJJndOYQMPbRbMbWihl4iq8tSvXM49Dyndm1Xk3Ool5Tvyq8s+ma1f27PJkwEm3g/KYQy8+Xjh JbhVV+I+/Alp20jDswffep829GgKtT7xs7pOiAMBaUkpOfecO+DreqMCRQwSTl6TpU5pV8OaN6mA b+XVHORvN634HmoBEzBe/ugv2QNvpJzehktR3QmVXvZ51eatefRW3mF8kGY06xpzy101Wtz6s/3r yz17HHo+XGlYU0s1Z6ESrIJNicYX+XtQ+KH+Zotl0pWg4Hf0TlDKakRoQ8RuL0DAVQHvXefFqX79 ui9e4sXJ/uZoyHpBAqtjDm3tHExgY4uXluI9xi252ccjIRO7xABzvpTzEOJbSmH0UPB0l+ccQyt4 qkyZvzeSIObaOHhYlEunaE5DNSrXRMOXebE/pyu3RFa5b74/u+SPkgL3Z5Vmgyh9voKz4jD4mVWz +HSqhHQxlXISpEZvFuyIznm+0p849OK5BkA0qWuxkLFhE/ELVQm1bqs+hKpu9ofkOH63y3f/nwbt ajMldAGN9oSatW8LRoLklfCUEP77TK12fw83R9k+iH6sJD3NPIXnEHYaR3mUIo0Faw93vCFcC/UG GjcvXPHAGsxEjhly9TlAxTJgD/MB6YBVeU6zNEnAHmoiRFrRqxeiengiYPC8WO3Gvs+RbE3o+lx6 Ojz7nYaIxWc/+NE2XhbyLw7XkjPHD8iYfSpe2ZFee4++yDfdxI44k5DtfzZ9fTYvV2BJB8h8fDMc VVw51lT86sWCp3rnKhGGetSG3FoGoH+F25vmW9nx0uWCoT6KQZNjNd4kCrCrLdH0237OXdMpSVSM 2hHN7LwOG2f8GkdusPNHpaXBpjN9q4p4j9DnugCXHt9EsiLIpG/YLGwYugA0WNIHHkkX+XDUEpo5 gOZ/Zo5o4utIChqtmHmG0wq4dD8jfVg5sY9p4bXBDe8MwadrPIElnNJuiHcenWoRiCciWqOy2Yr8 NV6DZX4bPPkXQzD30Q7OpXU5etS/UZRFJj69+eZUaJN2PnnPe47vjdj/UcVap935VHu1xM8LX12c uWJvkCiVCXJwtqEBtaWJPx9stj/PXafdbp+ayKyR+va+97funrFbc4fXtwuKl+4j74OU1AReWwuZ cWLEJ9Yk4DjyCfdj3ncrcnCcqlmgZLx91cNsmknXm4yi0P2NV2Yz0oXwGf3yhT1Ga6TJudLJ3mde Fh5FcmilHTyz5j1XsPy2ZrCLS60V/X6zbsAEdfvhQIo5SDlve0VUHP449ZRKkVEtgYwMWFp++igT 2cP4E+tIppnveIDvcpsdgi8K2bNAXe3dNcaCfTc4B7wyDaC6qklzYOodAV0nv1qI0FqeOsiVj/jL keXTKWDl+yHka3ZSzFnssjE1zhEp5aMuVla+0PqUuh06k718LJbArlyWx7/7D+G9trV2Ag3qJ+QR cZ2O9V9vrSxlCLt1MAZMJzOjwCSnqUJqAdnhyEunUyD85bAjkT7sntUYvT3nj63B1o8eGjzG9p9U HfBqwwFmuOfdj44pL1ZlpF5DTfjVM7zqllZTfF+x7U7JLWkoAR8DIczSOHMl09CTcgqZqIb2HnoG bvLUPz4df2c+lVrEVS/yRZMZWY2R1uLuC61qfruKvfPCoT7cMGM9Ig8+3q9eqA+R//c4E1huWO+k cW2X5sGi3c3Ogwwpo1o+16kNYzQ8ixc3pRj84FlMym46avIbxA3FTrPKWl9summJu0ml6Bwv09G2 jnmWeHwGVHTr+ZsVOnbP6TBF7XbHme+kRoOCNfgDPpQz3nulbZugIc3C9flfIe2F+cj1pofw9jTV ot6OF2m3Gu7uFDnBMj5Wo8osKoykyCF11JFCqrGp/0y7iQVl8osd/bqI1fPJd3ug9fd2pWwI540y FITmLBFdQO3DDeTgHKVvecBGtU/yrEzeRUrQECKTJoS5badkPwyfCuxXIjDT8g+pG0wdRyh6c2dJ 68huE7zchKal9gN2xvwk+9LMTaRytzmslBCGjF3XpjI4zdviLGwthkiohk28ngPql8AD2NVYsyYz etNYzhb9gJQuyM6iONtVhFxrsutA1D8R98YS1NASSCtz0SY2xl0Er4Lznr5Pek28akmiMn4SIiuM 2CTPpsWXQfZnvUIy6Xjgpl8gSoBfryUjboD06NRn6uloPHnObMWfWQpBY4yuUvBnjRLVv+20QzBZ 3WC1kVYfgn6PAe8tacJoq6ogB/e4Y+QgXRhV4YyfxdSwBu0Z4pONsPasMem+xXu6nhE7wxLWuAML M/c2up+TR9dMPsqBCtCRNhm1uu2eDSoe9NCwmoXvv4r5JE8/xi1SEdIJCSo3tDUIc+8RGXPgaknj UMn4stRN5LxmHsukDa0TOHwHqr/3HhBEsmiNjv9zWCtVsAiTqsjR5llqn67NxHJHaOia42PLCRMC N6dmton9Xa/ZFhyyXgMZfoQZbgyQ1Fpc3Mgp+nmgQ5/m8dMwKn9dC2TuClgCvH6+7tlczkdFW/eJ HINHmQqXBEaC8FXvKsba6Cri2yOnuVgvLI7dBd6EACQiVMYce7Nf/M00KOdQqE2pQltC+6/5WB35 TQbGVmwXGWYkR8uDPlNa33szZe2uytsgnlvwQ9kLVJTXtKTpPNRTjZs5F9SXFlF3YV1UJtSoSydt LrrJxMaGmmrkeFFe4NboKj7mxf3JiP9wXOl4IieLBN5HZ1j5akHKlFdakUWJJV3NpwcFPV2kC3ng dfRWcPiNxzKVorqGXn4BHizj/dPWQuLLL9twekJQMAlxzQZeTPv6naUvdjSh2x++Ivkb5xww1EIA Y+367qnJ9OGCP2kthdv0dTaaNyttzyTc3jV9F4WjEFqjBANS7ur0NmgxxpeanYsPJc/A/NF8504G eiiEZDeSAmiKfWzZ3lJj07KQXu/k0tRKYAOzJHJVhviutOBYx1nczJotq3EvfPEWspOvIdairjVA YeSfMJ1PWfBMYQ2WvpfuU48no5W2cUnOqrNdAjIq/IY0KwO4hsY/PP++IQK+7NuB3Z7VOT7dhovo uVAB7rpZmftCl43EcenUErDnEp+ALYZV6LfMNEtkqW92Jxq1AuGqjujRmbjdhsOGLZBhZdgJwSbl ilxVwLcEJ98/hqUPwt7iZffiM8qKSoV5CQGXkAQQKE9+OK0/Jq3s4bj53spH+a0MKR/O2TnFLgGO ghm1I9kedlm/KRdwCTAKUfL99w250s2gyDiED76o63bcQjgC/oYX52O/Y6dCDUQA8hclSqVzH6Il slqOPDw7a4k96jmilPKl9SFVKbHCAqGMjR+APEQqXn3dNRcCQ4ti3q6txi6aKZNhVayHL8Ht+0AQ 2BnvsFVWgSNU4UWU9/4Ow+1b50xrQ1g0vuAZchrvBApB2p3b05Ee6B1uHQS0H816aIO1gWTqjjql WV2qLP2Aun1Uyu+MsyaknwOFd/XOuINhdWfOQ27Rhn6t8l9ImO09g+wUDHKEgndcZN+0Y+pKY3Yq o+8hYqi/De8DMXnINLlJAUUs1HYo15yonnhEGG5wsZm4Il2RZpnyDDgwqvon9SHFRS6X6NRU5qkV a6iINN2NNAEegxdFUXiFyYS3TVX9KVyIg2SiqVhHl/x1VMxlQDs8h1jY8BkOdECZGe6BtIh7qOPT HQPrQFegAnuotsyLLw9p5qrq/OIKy8OOYycrig7Apt+jAhhtBEwl1dgPEp4CrWYnInCGwhu8aGLs /nS10lrFb0OIPcExTxwECGTLNC3EPgj7iMe4/8IEcJaZY/djvkmLWpVM7rzq7TWm4mdbzJU5KOnk nCRccF2qUVZNIdiUg0Sy8y6aCMcHzjObpxBRsuQrKmKD522K+ouwArez9wWojAQprt1RipUcOWeY qqwu2GG50I2A9NOUZklXuapjMy6oK2pIaEc2juk4LAxkk8Yk2i0mOVgJZP7NN7xKURdnBzMqAh2r sRs4aG7r7WCPyMAE6HtW518KTNnh41RfsviM/3mKDnpEfzlHSGDHz1EJ3GJjdmNPjLJxVfh7srrL XnDgnp8882b7Qra0ORIY3CotIXn5FgHrFk4fyXbUToKaEYqXj2bFwOdqPWQfKPfvGTr6i8cNzSqy i3LrkGZAPhtI/HqA2Ar4cIs3iB5YAI4PStBXS0xFYdOt/+am26S8jioujmqfQAkiCTULzI91ofXO 6Eeag62cXZE0ckB+NWGWVNKEMwNez5YdNvzJuBNIaQWaNK6VGx+o1pc0QH5VcP7j9uHeXkYDBV7H Ueg02NodAAfYT748GtpRKJvacINnco6FXpgXMlEK7/EfEDGtbNmkBTp0bnzb7jgwDFuFsJwSbFo3 rXHlJ7iXDKNOzYwpAYtk1p1RADHOOhNQBaFwR16v0c3n6Soi1A5x55Dwh04AfezIQF5lvbNIQ8q2 lPAfuRXew8/U/D56UoVrejt9hqmM2RJ9WjY/aD2B0PA2M9JBr9I90zgtxwxYkRPXGqQw7ZVt2PJr mz/VBocfc+SWQrmM0Vtyixh7fT1x2lfKoFVWSMCwAyg0K8hk6MlMtpSc3dicOJ7d2H7UMrvt6xOi B6b/1+PSTfVvzmOYEJTDUARkDsU7IpauX2PGyrl8PGca7JL4mxU6gj0KWUhkOyFxzesMQMZvBkcM 1iV70EctwEEjlnkzD1BgYMv/UEfuLGb3DCvRtWnPbJ4JQfcOJ9jALSGZX6HeJIjan0wvpMRqfm4j gEmTuBBqj43DSSd7D66kXj8JN9fMu6DRAAvrwihyxHvmAos6Ih5B4xrbhB02fHIySyb7qTG+N6B2 Qd5TNLHhPhaw17J6TfZEfZN6+t8doSOHKyX5zZQUlorT14H37pIrEas2m5HE5klPatb82q3q9LFc 5bNbUA83oUNcsgfRRVtuVt/0b6KyAYDLv0Y8OVQLLlneD9IfSgwc61lXetslHmzuvT8vxUIuJEei hl6yMiD7v0UMbgv3tAfg+Df3+SXHMMWAXCmmUni7mML0U65eM16pRf5/0f0WH3GrBRp6cCKVrdFA WG9LWJljXCgx4wU7PFG8K+V8A1su1P30FTiTUoc9irNI+UYYEjczCsl2hkV9rugEmvwjpgTiOYHn 3G5d/cPm3i6kxl7/HGoZ49yEE5VKV3pNCZsaEPZSgU7HBkD9LVgi1wG/0Fl2HacX0uzdy2RalF9N 2YMFV76pF8KzRnBGR21mksSvQFYA1E+CHqyMhbqs4g9L9sGf6dNhT6w5Kry3WK7o9nFIWZkrvFVd Q84JjZappujKp47wZKsvpSEiCVJCKshgGIDnJdJA0rZ9VPVykUmbZcfv0owaufYXZ+i47aCZNVmq E6mO0uk60wwRy+EqfN1bcmGbPBPcUZIqsA1BvzaLaL5HSzHI9nDQzYMmEc+U4PYXjCiezYPvDSUz aFeTMq1YFRf6TyZZoc8Zvg/1baeKZNqUMHPDM2g28aVfeLv0MQnM1Lm/B9kCFrzn4hwzhGnLpx81 5dU84Pa/oPaeYTeP4M1dThB7UxFnpOw2JQXA29iMOrMLze3HOw1MwZGSGNnB0UYZFk5jiYELTTb3 hams1WKS6BZqRdivLfJZkLOkQp3r6spY+2qllRO9QRHVMawsertoBGueSchgp6hPLHs0JKJ92iF8 gd2ogcV6lgyPmigAo3KgKc+hjFocyEn0F9LUJozs1Ob44v9KMAgziCQ0jlyfbpoU13M8DPM0/Nlm vptAi2sVXhYKgYAm36IVl497hS6rK6I1Kwsc3zJq+VLzzNeOInOHLjmj66Du1/5NdHo+sS56GcpM rt2Gtx7hX2J7xWtVOBFIjoEME2E4PpssYeXikdG+DknxoDE/jo52f4iSbtmSJnC+sf0j6fsAa/60 I/U01rpvi/MNPrZ/jzprEW4SzaxIBmVXgmPL1+pru6Yiqu1SKdWw8Q1+53sdMXyHE5cckIoQHqpH 4snldpEOghM6r9kOcyC5NYcF4mpIWKvxxtR3/tYoi5W5EOWbgxy38CdMS6/bHP/TM0NWp00WHqe0 63BVp7ixzuMdxf+UFCksmraJkIW8jiKsx26dfDkiP/SSI6fPKnN6iwbXH6AtV6HNctxdXB5VZv4B 4wD/eUmUBXgE+kYHtrhTkhCnvLSfnlLRrFFY9Am2aCrEFtc4p6AxEgRgvcV25tZi/13A7Em0zT1G G6yQ3vB8eCgLqgdwiEAQ7IC7GTV86IhTDTCd6oIDbqvERo8Hbd5WvvslHlp8tfMBUnd/1/ZQCBB4 YCh8mRRzroK3D2WDY4V3ZbvPIOxzRzlZYANSMvZMhaH+jruHPTw9oGoikJX5+T2fKZ+H1PKb0+Zl wwN02TgtbD+8w1+tBZuROmBbPV4RTr1aLWm0Qr3lTk/61NDKCY0lbrUPfV3J6dVjWin/6DrSBH84 MbjwGtD4ISnhIEoZOIQCxvm4Zo1P/yBPgHm+r6Id7zxBEX4isBxR8rMqv+kbxz4xnDyXsW1/zQmD ECe4LsL5LtSNllf/iIixiR5U8NGpQo2hVH1evfqtDMTZi0yAXwHuD/1rcpslilsY1lraeQeMvyqT SoxgUystryenagV8y7R/T0C0IUArLjDc7ptA6Kwqr77jspBxqju39ATy78QVJl9pt2y/3LjqdFI7 WkrK2cUgjYy35qFxrvaLEiZY5T657Ts2SvAaLGhN2yjQNrwtr7QnHRc3FEDgXGjFQSFZ3NpQHTvU bn+v2KuoTFnXNVaxVntz/7KcxcbrvTSGJGsPr5bQhtbWN8SjJGE+Ta+r5P3IxJ7aPvfyYj9c40x0 41gAFMlLRG60K+xpd3UNb7pTrJec4tzWonWPup+VnX9EZgDZ3N5Z2V2PHVFChivxr9rsPWp8BVeO HWA5a4ayr5V/rDOpKCpX7aUBc/e1iz6ed2rIpuAQwOgC0BPpYDnHXqjnDLtlQdrwqWIe0Y613mYN qpd52ulDdtlt4xZQ1mX/+DASZu4VCq4ZgtFtAoDgpX13n1gnY+Q8x8lcDp506Jo49Z1aerkfNAsg +LEueBPjtlYBjDwgFsMQV0vh6//VK2OVoKAifQpY3Ii0IO/XnNtsKdVBK5nE6H/8xXojvffGp865 VEDygrln6QtejLOza1TjSk9nAq3+0YO9V+kq881MsI/74GtAWZ3X/v7i80XHekyMQ/0FquRdR4Ri 997lLusPsiHrIzxvqqCGjVvuvUUi4faGlo3tWqmqxYxvdidbAKDlkwKpn6liNMXP17/C6V4HyK9l uR5Eq4xMWPu4zlJGKC5DUPw6DbfvOG4gyMqagz3Si4LgMFCmQw92vwLP5unctWkB/Pvj2YavRyUv EGUq53fwjK8YrT25BzPhAKi5j9O3oPrV/Fp8vRQaPYrLIkwTX8259oMMLgDprypZ4WHf6yo8ODgi ivB+qBHQz+R4B3jWyj2tTNVcXWWT43lDvrQGsoaMyueAVY06QWr/qJTsnBCbmCFNqRBz7DbJpUk0 OCEECz92sUfLmwIbY/BCLKUGZiqOu5G8LbpUMIO5JnE9FcA/XeFH0P1v242GIJ9YmPSp3+DWaHF5 8VmT3APPRUVU+5KYsEeLAhnF7Kqlwo7n8Qs1bV2uwfftI1tTDxayLDbMhUhTlH1Wyg5rL2kvj1PZ xktFEY0nmVG5YeQX/RAB5OEVY7Z82A6zLDC5a8Pxi3Ts2FPJhSdJAhYQAjbz37yL0a+EoKKqxUFV r+8CddZzs87oNQv/bo4DX/oELR4gUjk0IdIEQGapEIhDJrXi79F44ZID02eY9+ZPd+fBv+SedQ32 5fYoKBi79c2aHSXbLsnJyN4rz/1FkZNbefl4aelbGHxQxUE/EcOu58u4yzlbZmni5qT20QHt3VfB DvKS94GuGLTwa3DYrhJ00ketJmyD9lN43Aeb1WKpOSWNOF04cYRKhWTVaW5fgyaHd8BmkqfFuUp3 tBnnggb/5fyTldbVeXL3V9litw7HBbN8YSZdI5nUG2xe5xlYiNzAvnsZpClmQ4wdPMe1GbiNP5mQ kZomvAOBcFtkC2ZdOELhvOsJmzDnAM8h5SwHnRnR1Am1SBCSF+IXU2fdN1lIzRjfi8Q8Quf64IG+ uiiE4XVScY3BndjzGLSKiw9s3zkzxpgQk3YShVHfomj7u+dMfd+lMVDH4n9sQmrh4Z5c/r+4BSu8 75UiTwfTN1/h9AgJvEsiiHw0f5Q5v2vvqfUIbna05t/QTMyEAc/AfD4aKB6L++HP0qBCI/bbGmI8 vGQzkVNjPlhq3/WPRgWjgHmEOfSNvVRYOreBvHvFkyYzM6w943EkA64gs8UoX6WnYs4ByIa1KEi1 Nepr6B1zQohiy87g9vjgzec94mEW0gLkLY+mnsXp7Qif8/dwoADKdXkmopDtvkCnOm/2Lwqm2S7H rjt34CctCTIMSq+Jrnq0/a+PMj99PKpNzG8P606oOPuEX8P4ebekOl5SwgWiOpGkv7okWmU2XC78 e0gv+cbnmLSOtYpF9D8UDibtLbfd6g4aawowksIUyTuNrqfFb8LgneJwZMVsnwEFVCNxxIOfP0/O cxzHCgQM7LIupqvxX6msAT4HhXYWLjrUEQDQIIItxTEVBf7IzMRr8/nCOujXAks3+lqjA8mcJOFM E0ZeZ1vjXbCVMZblg+vtM/I4zKfDqVM8/JA7JpfHngtPsHeuO3pITPJiFFJ5IBBmr15bQXswzq4w MjZIMNW40i58xuXDeSpeCUND+mQZ5rhbuvgfHBUONq72bKdDfcAl0uxqqkeFhSp4Na7tw8s/VGmG bBI9SHM5aQPsIQ4IuZuQx1S8SO5Kml6wj6mo3q7ycFpp2WdawDFzYfGm5H8tMDCuhMeHQkBrHS+j pMDJda9ZpcNVMAHGjwONBgYO6C0laQqcpi2MqpTBKL1sCyy1UJ31AKPzmCzxHRJ56dcyTO1/nstx sn6P6dwu6yfy+lt06DneOTc6LyTq1/7PZLLF089fVWOf0WBc+AGliQmGyUsARfENZe41Uzz5v6Zd mhPsCwGqq5xCxSq6DOk8cimvkQjtKl2yh2uD0wmxEIPZKAE/F5EHjU39iqtcxHoAnFAGspln0OOm AISgLOFCAgSq/ABM9JkQI34IV6/PShPzRDn3HZjin6wnclD1eG4V8Hx98/COHdPS+o/NA55gMCH/ boRgg9kueBlZRCL3MI0lpaeh2yxLGZHW5FZ0SbnbIxam8yW0dWaDEX+D57EcYQTueXWUDSt+Tr2e wUS2ah9YsQAFtHTbESb/IdbHimUSQ/AVpB1bx2EiApxL8d7O2tIEXkhKQsGdaKt14jfHawSm/gem Hu0GYyfHnPxHcdMPABxGPEf6dHGBa6dO5FaJqEVbsNpmH4qyGq5Am7P6zqWJ+kmxC6Sku2RJL+9K k7HpbDNyzbeGLNEBPKzHI2Gx2TSQyouIxwmtqAN7i1uQNX5O4ni9hNkMy0r2OEyY2XmJOwOoPuVs jdoYhzGRaizaPi8u2VmY8SBp5NDLGXrLzklLjrEgZ4DlnHwZgaL+VI5t9KHDA7kStld67CqeNFHV /1y0+Fe8DQxeLsum0MlcPl5tc/KS2aXHvc5+G7EEVr5ZElP1EQGTamsDxrBfzSLOWXSP6xxzVdgL 24MO2SrhZTFFZJckHANdpVYuflODy4WpjY1u5DEd82S0NXoOcjY5kt9Y0o9Fmc9KqrH9NjiZTlu4 Tdjdhumhc3x6/rf5RRfY1XHTb5aDX47Rr3C+ai9ALbDGnAzKx1uj8jVf02iuDsiMitu0EpMB0BND CAg2arauuJj2yOAaas+6YC7JL+YueLOKKhmoeh8+CcLalPq2ndRQVFnIrfD7qJP1DEdQqa72Zrdd vbz/D6V4Zc+3lkpnzo6n54CUhbbiWuTPlvK12T2Vuhe2ABN2FygWFEJpdnxh9FJVvG8udzkwNQZ3 yy2wmccq21k90dk6wdKgHvcGge+bS/2LI63zlYrfQKyd5JxnvHsMcgJToPemyE2/dsQsHHEM4YxK W3BlPdiqREzBodPf8rCaJ3JfmT+nAEih7PZ3OGCs2Wvcdq9pnnjaGNfGObdaDk5/RKnkqJ5StH3E z3pao5st5xMVMxv8wCcAOnNlYzayrRZ6NYuWIQ+9ocVwJraF4gXzs92T+DdVh34a/GY2fBw+SX7q wSlCsfQnTMHgA4wZr+OQrmSKrme1rREcKZ0zac8hAb9moSg85YvSpll9U+CiowFxyCah3Vf4tAFR sJeAK/Mp5e2Lxev7pQsyKeQY6I0YMxMGmULn0vuU5BR7j43XNi30Y4jsAQka3V4bH/4udbQGsHCx xourReGisCBYJPIdml+TYWFVbIPoEgcna9r+73wmv/ddu40DGp7pQqCLIbqlnJfpzlCctFKfgBuc hA4HqzFumy8h5Ke/jTHlWSGhzTJJGRp87Uo84xq9vZFLae8JD26FucLdxr4ocSvfZqKHNhKl3M+V iwfS0kYiSfoOool7NtjWwgu1Hko93PRUxyIlOLoLJYt+JD+Fnqr2XT8PDChalI1QlJ8PCdM10kGK 3o/8c9FMvsmeyohBGzVknJSDUUruo+ZPiooZtfwz6liHYIxg2ox5WCpvCi0jkVND7dy4HBr8iohD PbGJBALV1CbHRUsq9z/ZHJFwFaetm81OrGebeqLH7f0XvCUgT4DeVw2GCEHYjVfONPDWWU7tK6cs NsVsCDg2QQanuKwB4PaD8HObosmjOYD+FL3+PMgujAQqAtN2eI9dl24MaQRxu3Ya8dRdzqIrYapN 0KDcY+1Cu+P8VL5UX2d7bTaKPCTL9NkiqLFotxBG/7vX/QAPGA0OnWCbdcS7BpI3QOcKRpYiMBX6 7foE2OBIszqyyk6T0Oy0QIHWC6I3fJuJnBAfwgkypCBSp2vt23YDpJ01R9tkzMbuDjN7KWy7LS/r X6N342GFcF9caUOnJzqdLbBLlLmN9bNSD7GJ2t/DvX92REYEzBG5otLIPEFw81sHeZ4QZxDBj/Fv xg4NZAD3L3bjDYX3Ucr+biXy2IrrxrqhZeI4J19LhcNoEQ4tI+OpUtaG27Tg5DtBpGCZmHlyFjHO unQDLXw2+riWjpVdWWMwTIJIhYk+uY9KryHdLVPA4AD2SahNd8MqBtNoLvHpov9zJytRX2r/3p5n ZhAUHygpcppYG+kcWyPXpq4uzYgBrGaPQ4L3etRbAXd+e+4wxxjHBo1pwPKKbS7ESc+iX1RHWU9F dS53fEzV/fUxaGPMPb8aieeWhJFgWDMOH1eSkaWhGAas97cq3sY1IuQiQLS5/7bdnPl1/Z80xlVA 1zV62YgVUzZuiFgS8sjPwGYF8w/ZONy0/WJLx7vBXne830k2S3poI4lzffdzMXCQ4eeeR48x3/hC LZbak0MKx9Idi3b9gaLKJZAwZs1aW18NloO7xWZHu9d9wetvv/1nfySu2bOr/RyngVXO5gE+Ie5f UtNCBkJGYKkU7WodNYhs83yRkyrmXnXAY9P5QL+e9ljOxZkSuHxloDSB7z/eatSIK48Hm7bStpWY DFIJPaYKO3YNbAjrSYbe1Ucywe5jEFv7d6GqoSl+aodOPZ/OD6Cgpvd6Vg7+VcWMX8ufhKpjHOUa 3oLCczaldX/AP6o+Xz3P9TJGLQgW5X99azu/WnKq2RimCKoz0ax7NRqw1a+M4KBh37cPZ+/RDNFK 8rbLNjy6VFEFBDmPx7GpOHXACl2HVTjlwAYASi+ScLKypNesNrdV9OxeAwsq8lSQL9nKc05MXAS/ HZQq2Zrek4hxQQS2fP1R5RJONslyhGraCaq8y4wKoxI20/+7VVjmgCflwmv5TN+WSsShYRRElEKd BmMZ3cu9LAKzra/KB9U30SmlD9ZjQ5gYKQxqF4tTp4tyHVejgZXF26YfthxipwAZtI4vBOJi2oKp hBPm3BxlhoysccB73BGiX25ql3yfD34QCH6rSgzq9B4Id+ackiPJb/EFRUBbN5dxfxi8TyoIHuLp 4CxeG6aQmptX0lSKgJIbWvLctdtB/bWcSBHAAIxv9Qst3mP3A2RWDqWtDamCfETSGwyWlVNl/bn7 gddxDGdV5o5YalQ6WtBHoktjHfxdAjZSsqfNAujKONzpgh5zbP9NjhU2iHSTEOcJOPt2BndVUc1D TRY1zuNveqrKGxO6xbyg8ZgpzfxHCw+7zGiPSZQN4ZbkX5VMapaAqLTpEW7mUndsa9lXo5+KB9Iy mktbyH5IArRoX85Wgi2VWbOHzV3UpnXtqWlI8rQvjKRJUtdXBJ3tpRyU0YyrRWhoPAY3adeEzuON pBWUkqCduNQ+ZZ4ZG2xrskGPBfELQI3/iOFrmbYRurGJdERlpQH2X8XzwrvbYE4MNin+xmuM8L4n IlXbdJ1cwwFWwAAoHKgEZOfFIdyyN3OSyRMBeY1XeINxgpyhAaex8VAwixkUvOc/oGk/h02u8U0Z gyqrLm9u8X/Cugp+iBi/Y7ZxY/a1+XgNx1HVwVMmkEag8v0S2FLmECD9JkPHhwdgiZiB3kcVAI7X YTt0+2NXdJoddt12ekEfxxvWm2BMRWya0sf1aWok3JA78SVZ8BNzO2f8n2+ssqVlrYQgxF98gkGg Agv51rmTAdykaFgcuyLyzUaXpZHWLJoj0dIKiGHNsGL1CqLIk2fuO/82H4tlvwv1uks3g2JiWnig X7+N1tNPpPrZMQd4JLfDhIoH5I4r3pa5a2odV+t9OLGifdS7Zq7EoX0b714N4WhivCHfS1LW64/6 VAaST7Z6Yat+6D5u25B1c+ro2Rw9O+l00Ls6m1wtOh0xZQHtTsO4FcVMLoJw5kI2nhwCL/jBTgY0 1861wrUmSr2NAgGwl5Gd7gdQFgo8E/zKbOOJiRVkFzNlEORVNPQDuwBU6NjCv1as3U71Un09lFrL 8OBySGvxRnYBrrPeNw5qZWRLIdHDmSI4qLHwY6Pp7Iicze4G6bp0jt1CFzH/fjgTq2bH/YHDlVao z/9cmQBDwKNybAzqK76heZxqENHPSKvk++uLv4AhmOCRoWvI0PLDhgpioOD/OXS5gmfnTpT2Em/n yc0jN2gW/Q20ClUO8KoXPn7ZK9imMV6FoH8RUfczlrysjxKJ7OnDOVx4Z+TKd0ys4f/HIwNUB+g/ Pi1nxvAjAhsguR7V3e1+TbnxeZS0RP4OcLNCSTYkVN//kLmBa82gD5H5ecdtNCKyk49IL+AvKKRc /eGRHWrmDN/sRO9mN2cpdyGfkqTFg4bTDNJbdG6alnJRHvP0zEt2ifdPrSQSkndTYUv6X9n7QIfU lowzHEulzq6kpkZ0yhS1hcS/CMuR4RtkbBdX262tcc9Pv3ijqhmFONM7+S4CCY30dmiSKsyfyjeN GXj1WFV37EZ3csvt0MRHpHIqMRukQFdNixrhmpGQ2mIHPUeRnVqbJh0TM1YFBeZF4+O8wTShfTYU rTUgRJMW0pwvW3u3jndEBum7lXwnOBI8RTJorkpjjELWzKcd6GO0xrYsUKVTOc5WszFvaLyQAWQ/ sKcqZ1fMWRkzdvoMzkEI+WRvDQoi4YnzH1v3gggC/AkhJrRdrqAYlwQ75tnMLiM7VuSHCRiOsTYM AKMB9+0kjkbNBfi3iUsivPTTQuEJxtLxYXmehoTKWo2mKWTMA5Xn7oDrCJnoN90iqePUqx3oclkG Kad4cEOzmvYM43KvAZVT2cZui4gH0URkSRqfVtJrlEsrze8CaCTnGcQiH8fj5rG9PZ9mhvJKMRNu cND2NeoHMOBJl26CxdhgEaHwdZZLu3lsJp59Rt7QAIje8gprUtFYee162yPompWn1up2zdGwu0WB 7dGazjRASfLjjMM3ATB6SK84c2atrV6/3DLEevjMGtCQ431A0AEWjEY029vzPYlQ7UpMBlU49pe3 O9VPyzemUfqJLLn3HVjns3wdIowA2j3TlsH6kRYbh6TVUBZq1+Y1N9AD0bp1fv4LhdA4CQMp9WuC XgrMf+I3EGhxlmUUj4Gg4HSS0+4Eek9WvuZcyOWUVjdt/JaXA3FOGI0Dnffav6oPC/yUZpWvpoW5 kmxy/vWl0yqDcxRR8TUw+xRrtm31zfiK1xEQG9a57ezJ9Ohtx2FDDXnHpfFB+peD2MqpU/NdgJ8Z WDnjSZdlvwrzs68VZsEcpDHhIclqv3SXv12LKqUzuYiN9qJRKZAP5Amm2dYDsaDwQJZxM8ZkB7uK vjxYG31Oh5xg7ZMUrp6KQ3vV59M5PuRcjMGYj0m8YlydEmeb1NmGXwXk5EKynZntQwpVhM1/oeAQ 15TjIqjvbdxS1Ag+CmVnYVZ2p63kZboOQmYyQZazBH/DJDiRstHhwB7Rq2aLpO4dPy12MhRnIJrR qX67Q772ynJFAl6QZFiSp2y7Xsj5uTsXe8KUlDrrnxyzjnv0OV1BRKalLTtRICeBOMQVqQYpt0oo IPJ2rfVStRQBqRd4KZZQwRGUPvay5+9sTP40CK5pNfH2byMglRMVObUbbo02y5azyqx6Ah6ONl0K qtkM7TYyMYpeJ82AhT8qFevoAI+u88lFWumfzEmqRqEEE9L6YAtkPGKprrAI0VNU+HJ7tOV0DWu3 umHKPt6UL6+KvaTw5xLJ9hjgUIt0GLwtoM6YW1IYhtXqkmutxQtf4hGYO/6NLBrjBZgp60Nx0jUB joTnIO8sFs5BZvN9M6RQCzUhka0bViWpAAxeUkJ41I5QEDkfY4y/NA9v1kDcEGdaoNY/VVaX5qC9 kepUpCg/U0lUStJ1rhIThXfBIciTZ7Mt4fJivDJmlnX2Y8f+BM3rS5T6dcf8194Xup/mFQAQZJOw YVYNe+ntvociNySHHgfEaikUYKYj5Adk+rzua1mZENezH5483xqY+NvnNdNRssuxsuCLDR84WLpV UTXZ9uDjr18bfjtSLncKQTvz3uGxC8TTF6gqZ42BHRBuGf2AMb1No6IG55OvYh/dhWNvwZHAcQKn tW8ceY/C9jS1cwCrBhk+wkquSiNME7QpNbOpwH08q0/JljY7fM9CXeHUx3viJI2ytdye/QteSRgL oRc4tT0eX2Uv9CbnIjMf4ZaNFUEn4NVmz8QrVN6KVN9qDIDfNKU0L8js+YZIuZYBoxW05cPNr/1X 1/SJxjPM00J3ywNm5BrofGpji63NUtC4caZ+Xz3ATZUZAM53zmbRG1wZvW7YLaDc3ruTBKmcXUTo 8/IThMn+7bOctt7pkcwYGXSfcNgDVksKlZ2sIXdbVJ60kfvBOHaet4kJ2BbMmT/2bC4IosL1e/qE 6h4uc9/tDLK3+Tm9afYQovj6y/V3zHSAAinXdDijcuHuF9RWpngysdmUrHkVfKMM23f+mHGIfZFO 1pUkvgyulrGNaT51ieSQilDGQ0A08/5mb140unCYmwI3TsqJMK/Mdm209Lk8Nc0aj02tj4OnyOIG 2JQyVCIUFjAVDSOMzhNaDFi2I3D0hE0/Qf4PXvBIyolbV0+cQ24Tcm6V01gYgjnLFAgqKNgmSwgf BbgCtgGMvP+lug6QFD0N452EllVJeyhZc9li0diFlSJ8BW0IKFdb5ks1h9Hu0AFcdRuLVi9MErYS mUQL4+/+Qoo7WwqMMGDEDzTb6q3ZtbjERVjjMZWNUv2RXoc9AuRtrTjLXmLNAD6NCg+pnE2hYTGa RDWMnwU4z8agy1ki9y/LGQhXsfTE1x+SOiv3Ho2y1aYID0a5FOVtjfILh5VLKMXZcNYGq54qiPNm EZNUuMvecZ59nrLqFZGVy5T13VPb18XRMOkao2+y5i29/cMYdC4nNllEIcBTwlbTopSaKhps01SJ jgSKHgVFvlGQ0EJqjyx8hPxj5C0Pb5aLbf3cqevJ0hyYBstrwfozTqAa6UJMlwR8WOh4nxSnFycg 1WGYQTZ7W9Rr2/ZIYxFeGGU46VQs360QlXOdayIiHw1K6HZ04amUJ32G7cQxy4cYHPiClMRPgh4j /VQBPaOvCA9vXDATFom8DIxP8pPG4AwIg/Dg9lVuajWiLSZZtoM+RVJHonncze/nUPZWr1UUpV1H iPX4xc+irRR24lP+EPCuVSBB9ShxbiU6xAVRPY1TvJSXn8QSwje2EnHtb9Q8SWTTEZaWzRYtPJT3 5PGd6aQd7l0xbhpxApi0AMscPm7mNoldOk/wKSVjyeWCWMO6DKQHZJ+A9waTJS/r0uw7IZkwvKkz e0k2uUEg/BK0s7vqkYIZLozg23vkuVepDSGqCdLyG8/1c3dzfhvOmZLErif/lLdD84Jo1KzCjlNS sU9+JLoo/bevHhtKHIJvRG7Rkyn758y7Ozn9/QnS7LEPjziJO1eL7t5Zu/BiFm8gNB9QEExjo0Jk sUyuCMFJwF/DPvqV7BiKBAY0f+0Cr7+01Ee8lglNsZp/sEn7jUc5OETQp47o3/6PgHW6XHJROm7A cbHuGFRtkUwzl72fAv3ejUY+UkztIVu0852nl8UPtv2YCjh99duOxgXUPzlguipE+39euQHT3LkA +NXpD+/8Mw/ot9Fu9ViDxRadt3rrH5ZrnQPnU7/tvGata6E0FosJg1lyfQ3CySVFT+PbdZ2mP+te 2ga+NjG34NSmmUUBHvetu8eK/IEv1z3BtLTWgQOke7m+uuUkVLPgNd4LIEwk4Z3tdQG+OmgqzAZG i1mcHjl4hUefvgTnFr+uRLgPstZojQ7uFFHi9r1m84F/IeozoXkOqPTzVx7NeexeEaNkMcpLcrTl vzA2F7Q3yHMouJSFhulHOVRp4aHy8DlV084sl3jfTp+Wltn2/9HV8E3UgXm3ZA0d6NfDDAa2Ed3m BfzEQjSpaSti28TuhDqWBNAmwsFoIv+A2lvJcFSYVJw1S/UPWixjUp4HRUkyo3BUjVebIQqRai3J fjeL/oZ4qVQf9baF41jB5Jb11xgmubbaBHnbxu6UpVqLYRGN50ixS55r/2EN1NgCp1riQ/eFvJOQ qE7Wh/ySDypjYN4xOgYt/JIKb9e8sGIUKpViHBKr7HWTSNno7P/JR8yX5RpUolI9WLnnFcqrsGb8 MGG43OSwKA2yrFizgYVHlSo+Xhauzx/s1OZG8Cc1pPBHxvpE3k6xDaIkU2LVsZ6Wa7tnbRoOiKKF jakakKZs912/oPk29U+moK9phVCVl9VLgnjF+v2kStiHkjlERxKdNqD/WImhLN2b1rORpwz4czWg EPjCrYvMc9qL5OCJRPCxUoO6lvkdc6cOL+9lPJRQmk4Is/Mni/Wm5Yv8oExoeUbeotL+UNomIZLX pIfWPJcMERxDb6dxGeofCZXq9lkh1P/rLn5HdNaHNQWZVgPNdPxrsHpwz+NV3Wudnzh9xl36oM68 jxAh4ACkiJhHGi3dDCfTXVHQrdB/loJFdH04TmwWSPOioTuulKqTxPzSTZ0fJaPx4pnfpdqhQ3LA W9CJ5priNskYVBf9W0zAvTOB9TDMAceQTmpR3Sku+wIUbW1MKqJTOhQQFlcwpUb1Emb1UhLlEQYU Fouebq+qGSHgKgd2XRVtfNlVApqy/+dTFLNDfpPvk3SlLdgK7HEo10k5yiEFl+1P6WvTpCN9isZX vf93FUAwwgF7+0K4FZg1ydb+23vlLrBeTe35VAVIWh/dXVqnNGHbRu7414GnNs+kptjoFrV7UC9D LevRQ9s2VcAc5CkNJnSFxPVEjDagV0EYL/MkbN0/wVU21uqD+bNXxz9cKSgz2DA/uJExM14LrxWk 4dRJVHpGbnc6ya0NjxtcDPfYsVxy0SgLPOx0cUo3ULOJGomadsNXd0+W1bc/LROF/r9oJiA93y4D HegHCpH0vKHNQ0RpXUrkVA3uDE66Iec6rvGUQS9vBkCZKpzJGwLEI3z7PVyix2Lgy/4dk+mLbUnG CdSsXl+Xjv80VuOlpfcHlykyHRCGTolzDljgNEcAPsKL1G0QgBS1QVAngLQj/I5EFkyfcMlOcKsF knxbpukGH8VEcZOzsctz/Grasl2UzDHMAhtu9RtJdJdX+BsaMH4f5/rBlW1xPdz/FfPc8HQd/0RT 64JGrYZDCy1alsczzglZkAgzo1zMTGUPatj9gKSi6W6tmlDljBFNgZOvCUT8yO9gHR8/9X/NpfD4 8abzQ/Gv0G4G/QlUmXexzLy2TUJq2nmcb9WOp4XqrfsBSGJ0KYV7JQzmyBtieBIm7Y51WNsfRrG7 CCKopcPwdxk7PtN0IEJfv5knL2ktjN6VVeCr+AeL+BU9YCRC70egu/DiCLaianeRdEqv23hDstQH rWuaCbIZjy0RiCE8VI/pjYUXFBQVfkwlJJ5sjWL3d+c/1FUHfnXoL3ON23LLUb2WyfaoOK2CIotk IAskkU/OrHxv4wg7bi7jgCgh8yIJ8x5dxVlDmFtxBmSU14KKTrKrN3I3b1KhkiTO/JjpiieHBMj+ fdEmnA+Hm0MdftjWCN8NYw7RWiae1cGRPmAdEifvTJFS6Ivyygo85sPOMlYOLVpkHXNeVmoUt1tR YO1TonOYzePSfeJ5NHZUe7YAMyN7ZZZ/aASKxmkdHOF7hL4yPCGrQMtjkDwAcLysZ3F21+Wro7cu YuzVGECK/1PmN9QtTuOlDOafZSf0w6NUZkSOz5hlFJoejAfTIYWXQNJMWeka1DrYjn85A2FmN7K6 lbE3OAbCG/Mvgw+IIvkS53Ns1v7J5PjHpwDnP2kJ2Wglc+fPRgdEAy8QNoIa9j1BI0QQa4Irnm1v q5bQQGhwDOZA5A4tSOonEm3w1abppKqMByyydXb9WLvxc03PPfnYHGpwa669sh/BNBp5lrIpziwC n8B0NqXt9EHT54aIsm2Xebt2oOUAaHZhrrptpyuaXZ1b47zuvg96a20YJSoHOA3X+3dMNTjLrXrH FPYK4+l+Z6/USHRc8n5K8l1iCCRZDTmSoweZlWv8tcQfQT1Ll2jUgywBapl+kXavqhNRkjB3+hSQ SUv6FY09xo5ar6A+EVx0TpDYRJelio0DfzDQmpE7eiSbAIW4610HXzikRShKi8uKv8ymb5GVvr8A YpM5QI3EhPgvwW70MbsgnFl5FMrVMXc7iixGg+V4NaBYxBVTu1NKEhNRC4g8ssoA77/ae1NMbmvp 2VnZMhJORF9KrImwNUX2tsVxgt+hJ0sShZvBaipXR6iMmYWp4qRUsV7hG7FeIHFO2MqRdwGpGqzU lsG0/tjHzCIAFSUqJ9ghDfgLGG60jH1rRYNOBD53zYZGdzDgeDrz4EnqQyuTIegKkSPS2nP8CxtU u8Xq6rmOkvs59x/h8EhBlcDKVObYLA+D7Y5y6O2vR53FWmS+kGUWeF0ftuDg7+sx8HNlEBn338p1 CITx+lSozlP/n2VPQt6jxRMISc0sEqA+abk5e1TpjtrsHTIyn7TOFt71TTF6Fpf2mTvPLULKgYmD L5B9Vi50DKhpsahbAs9mm7O4xCG7px2Js9qfX8fdLki3Oahj13wxAoXF0yzMBY46dQc41XUks188 4uPcfME/32UJTu1aguPsfgN4eb5SiboqAowSDcIkL56FUc7J5IfGjFLYENyImD+P/8TJcF5983+6 3BbFz4K1PS5xkrIuWCP3c3FiasNdNeStH1FblRzF/xFM6EAnNB0bIfCj2Z77oSI0y1AkJ/JKoNzS ij3Yid93tyIjFAnLFB23R2h3ZgOWuVtWywAFSIYI7Ku+cigysPz7Zq2GnGOT80/NPdV+OotoBxEO 0WWBqpBl3PJT9wO0OAhNNzjLcXX5UJhH0i2GtaK5NRSNzqk+by+UyPYMrLCQYdHW//NnLcfTfcD/ 7kExeWcI9LI7o5O1K69MS5ErxqGmPRpkmEwSafBfre/Dl9NZ31m/4NQXoLC2ea8QeLbUzWpC2VNj 9ps+o+peosKzJgl+t2GecrG1tHZY3QAQ9hW5RhFLtzA9hMSHc27pMgzW94P5vfwpua+aBZae/p8Z ogIEIGs8GXbHN6+6FxRqTQp+1euGANcaB5xOu2lEnp+nS47My/Y6UaTyFN+tl6VXVikpVlQKd+kW 89ptOq2rv8sbCUvkMnoCeM+YNnwsyg6hgVw+bIWkVzpzqBN1jPGRmE0lGqufEy50F6jEbp36d/TS WFXU0cOOBp0ZLExiAd4sbROP23NVymbqtYWsLB/LhBX8hQ3u8ImOWNuEB1Z6jGpgzVMvvps9V8e2 oTWcm+9/cZt6gqgfQxUUe0E2CS48NwcIM5BO4E9P5AyVkAGcPgRaoium/HqraPYLPFwX0cgRliKM EWIuLMsM0jvZvuv2wvJEyCvHKR6kNKE6wDClhksHx5ZOB8mlWFUwGA0OycQUeIGFfTfzBIt62Eub kodeOukX73fvFYOBrazcgxY5upRoEPOwm5D52HzgoTGUWjXYAn99O3hB5eZkB0O8MuDu0YwFuCFo JSqDP3SkhhZ+VCAXc1Zt7J2e5fXAouG1EVJaNl97ewRw590LoFzg+VpINkTKSpY1BCXGBfSHVo0W wOBa+xfiU/ocjFINA7Du+SoxVISr19bFp8DjNVOVZ3Moxls1gnABlJPw+q/jr9B6IBFFoRN48Dpe 573bW1gKwfT/FRLwR6xsoaC3kkmT50s02vgkbWsPwDjSlo03jVxD20J/T42tRgTbwYybCwNn3XyZ SOl+UYh9fPHJvOW8AAyXSwvplb1kCVdL0KZxZGqPzAQG+ldd5AFlsJAg4Jtj2eOy5qYywSVx5Qdm 0gubTyOKGVBAfzZrSfV9vAiMseombahlnwhZfM9UqZ7fxl9vTWelSbHRT8yNPV7NyYSj/o1sh0XZ tK2d/wQLQioe+B11AfIltoIW0MABuVCdusJuSTIosle4/3241knWyjuyoe3XtxQiSjL6U2SvMGgW 9jeNFnh53js8hNYhM362ipf0FUYSo7FqtYdCbl6sbFV8ahh8j/HA+6jcXhtWD6iZ5CDAp1n9Q25Q ZqP1l8TK7zgHm3aZhFVbvX3OFVFdKxRHJbXKj/65ksCz+eBKHWJDwiH6qVCHUKR4d5GWUCP5PJWm +aRC/a7NInwCxIWzPJeZGEu7SS61y/hxFdHa11+pHu4yMJpOJzabYgE3R9m16V+AKviGPJ5ix76w +QZaPHxk+ZQEysC/iGermgvf2Wmy5pvx1gHx+dl/SciHYl9eqTQM2N900qooyBZQcv58IEFOARFr p6nFgAYFK1fB05Xygc3MqGkbD1pJFZVG1aLZyzIdFe4WMYvX2gnRPh3Q7mRD5UtDOOfKnWzKmKcq ZJY0oavuZrX5FQtZi/eLR8Gg4tDuVPkY9PcN+RZ/gfe6EV5kS9N1boTlKK496RfL2hswqHZcqcMT qxL5AtmtiBMD0IVb2IV8/nTbPIV3N4b8JURnxurbkVeYvjDVPFJgB+Q/VIJCEg6RzfOVHNqdEnus jwRMvfvogdXBlDqMTMnuyWDJigbc4RRJeLhNiNKlCBrmydhsDaDb2SECVb8S+hnY037UOFDesL/O yBuZtYR1WwMIg6lYQpHx0aqGSigFeq25oxbNuOafEe1ElM7bjxLO1vqxThwP1O2Bjwc+eZb0l1yt 3JKWLo9MPjcdhaElJIw7FTSVBVsty4mo+qpYGmUq9Imot+ZdxIy+bdOUq94fKd6WidW7/DikDu5a dqubKHm7YoJRhe1gOx/jIYlE0ByCPzeiK5epzsNmBs6bo1mC0ApZLDgO7b0nn1McgvyOVbH1sc6e uAghBmJqLqBFT0dLipf4k7b9PhO/9DtvTqhoWKkpWzWtKrUQwtWjdDuErdYVrUP5Y1+brMG5T58e 9hiJ364uPFj7nzyl2xjCGQOFk8nUSFR7S9BWg7kwRD19mj5wBqdJtW5R8c9OlhrLipSyJQsPVGxD Vwkzf7Hf0WDY7gbkC6rL80kC4r7p25t95AnAZ8pWvxLXgx5AWAB37jUepdpUX5z1honf2OI3GqY6 fmxJ5nk+3jwRvhBPl/yeUUO8yqfbKIi4DREp60AbFNKQAEFVckH2IWMMCWLKsXylPViSpAyrn+z2 uPu2eYw1zlS/ESzHpHt9Nayv/i/WNZZXRBRyYGXOVjC0kovX7VYWjIbq4sgOjKsoq85Xb/OnhW4d DK4SaiL+PuW35ME5Tt1P1rM/YcElbdPZMne+qsbil5s1TLnHVRwK0V70pfcBjkD7vrkXow/+i2yF HvTnd3iGGpwcuZ3Ca+l8b33M001LMySDsLYMhhAo1oaONKcNtcZpLeKtH8zAJAAEaaU+Rt2j77cf UXTyD+ea1DejSlMhBbBSC4418vcRMj4NVp4dGStzxq4uM7m1Vvy6EC7rcNShoBbFh8QrEMQjkngA o4opAMONXoUshxtueMKu3/CSMMqefTd7fmpBcKb9lykLkrS/1EN/xAQyQkOZMOA45VjpGTxeeBFi 0HWykwF09YZ97mOjmZ6nh2NoN8O8062rkyChacTWOYkdiw3gNRnma42UqO13MJvVi9W3KrMWLzCf 4Q3YgkjGiwqmRA63hClrKYXTSZV0ZEfNZKpUgcG47X5D3uKptH6wKYmdWZdcpeIBX7j3vXNF8s35 AiPBFY3ul5BxmFKSoRyhyNDJVTCF4rUDSdFKqCqBLkcFXShGbOwQzZpCaAWO/HDsSWSU/eglSa+o 0J69MMu4zSPVnWm8l61UTzVhnpNmISDUEO7TF7fkm1dPUN9bxGUla0LcfUptsP56IdRVZz9wBIZq c2uZgixCnNQNtfImbl7osUboOurtP+TobbygexfvI+x4TVL1InH1FHtoW559JRM45Yv1C69FVtul ccMezmawoJw4C0xjr6xO/PMFDSuQJptL5A24DOewFM16exTuoCJ/XCZiLe0KhUbAAhLmNPILseGY g74MrD79tFaxTi8ut0V4oZUfjPh3GfmlEX8Gk25A7hmHE8XQCHbgZEpFUBlFhFARdpH0F6MKEoGs +6CxTgtymu20S3kQbVF5fE00zW5/Pjlr4QouOmv9Dz5tAgICaB+HKUrSVKtxHeuj4MJLujnVt8+b TL4GvrLbL+M5BlJW/wqpcWkPpphN2hQgiGERmR1G0wJlyisJIUS3rsOXJQsCc3ox858nxCT4iFja Q7FI0a1wn04j6NeJlxqBOItsJmUnkYA3xhLooh0DVna93uSRw158XXK5tshLopNkV5q+BB2LkuxX LU4XZzQixdj5n8U3K6syEu715xKC/Z1yQMp9nwscfu4czW/S2Iq+cIMryzLA/2ByiOOMPN0YqGrd e6X0lgLuQSRgk+kICeyxG7xKDmTXNrB7LzcAXZN7NXm7z1d24xomlexR8DPMA/trZncaZkPUHBP6 uGkzZWwmGDxOp9amAgNBHzXLoyUHpxZcTJHVZR+yPnyr1RpJjEkVGTuWbrmRbVD9WRWG5+BX4z3y HK+lRVUm3P5yzvPotwIvp0mRDE63BxHnbEsAauax5or+VUv6WtJN4ZiEsMI+9lx6DZc47QIe5j0t ++kX721K/07pZCskAGdOhqO301wguWJL8q3cDC9caqfISMVHTJMOHQ+GY40buSWO5zTVDP3vF+k+ 8BnrxAkfEhWNldZzFOz6mQFEUxmpCTwWik4FfUS4Z7nMUvcri6gTBNibolaF2SC9MXgaIPBhE2Sb c1JkgE19fSIu0N0v5UFfLa/zigQaA05zGfWLlFBricPQuG1R3BfCvyjD2/675MClkvIj8R0HewuH P3PgxpxBCioLW2Zj0bN4+1HbU3dAyj7XjyTs09188IP2Uf1ocpY6SOnQJfrz/RGbV6OGVwm/Q24E ZnqpTtJXyeS/wJw3esxFFaNbhNzslkmEvSkSfO9obeng0hxw9f2JZKqmczcS5zimN9hd6bB6cyL/ AMQYXZpMue2vXDqA93M+JVBfkuMPC0o98ufHPV0iNZ9hMjVmEZ/+QMaBQ74ys2Li1tT8gLNPVEEg UGGubDbaJT4C4b/14j68jD7UkyjA4yAZBHOeR+D6hpcJUxqVNXsGTUMlHShhinuyTSIhGIUUZ5nz V/cl8zqa+ZeqwYIl4fIKztIgJK1DvryOPseHjofpYEarP6qauq+vCTa/am100dze+18Tnjp5pFA3 J47y+5CTSi5/tdAFkwt/fGE2ThUl49nfp9QCDZ3kqlSuAdA1K0wZIWWY7yhbH1YvL5VqhEU2brCA 4EU1fLSSQDDmkrI/O9qTEi6VLwfo3tsKDS9ZWCDB/IX4yakRTRkoJVuZxShYu5Mb52HifW5AjGjA Rwi/b+5a4FaD9+/blExBuTdGxv+Isc/aUzCZpm30wWrGPUbD5xghs597VsLZ6z3U6MwSMkTFokXB qw8LTjL4ETUQNfXbNU6dmcHA7hvRj0BogG+zGNhzojgt4kay1RkILo5lLLMRaM9J1mLkOekdMHcj 7+ekEzpNwV2MeK65Z0RCN1YkPD6NjmiF60UeHd3NPo9a2kLvf19w+/OxpM3RW0tnRsPlkfDeDObv AcFrwap4G2KFV8UKx5CUybQsyUyXvtygGANUDEkufUBspbE0jZMoIpN9N2yVh+g1xEeUFosV/6kY 1qeqrPQKDenxfb7H2dF9npuW9cWIvBbN4YAOoDRM8ekDILVO6VKdaWlHRqXipfItmEt9j7nweGzf VtweeZYZoOUE2BljkHLJeknNjS7Oh1yMKcETGeIMlgqaFD5wH8nSjtSgNp5oxf6UUfgUTCVbevUh GnWFiOaguvlC2bMOJdj2l1pz0ecDkPosB3FzdnbxGVFp+B5k3qSQ7Chw2eoSm0JD63phiG8TTQ43 fes9/m5ntgZv1f+is8FXqrLLXJe3TQ06WVFXlixV5vIem7/iqQOwfH0hN3bH+hJSTtZYKVDh37EK t46cVnG4PBFZPQR66LFyOIZCnNHtIsbuhtaNnUbn33FUw/r5HIS7p8SiHZ3SmdIEL6V6SMlKXdlh fnoH6wkKItbpWBJGH8CVvJtfvb29sCaHQ0vxr31y+UZKo/AjbwbC/3iqQfqYEdMhdxf1a1eocZmv SHPDvEgeUqeFs90fmWwck6CSEAm06BNb4wA2nS+HKPXL1SPEcWbKyxUpmas2W2h/LBwmBtSYRrb/ Ca2UUGgV+QOJL1aDOEMS7fHHA0oMKGEv80H8y0MZYbw5q5D6o6ssAlx2fAwc7Cxk77oSvevtX2Gp 2pHWQsfq63vnb6Z6KAJ8KkBb9TRDTVd98NiQsOK4mlcpw32B0uRiaSPuet9ROOahxTQG6qYB0r18 1CcvRag3fZqYLbLoKEAHrZtJ9QtRPeIymJR2mDIXCQCXbuECe+C3vPx6OYovyBQBc724E4EetCud HxgUHeuOZOwIHdZoBdn8YLVdzkzWTvqQZN2e1zA52HqsketC8vnX1IQgxlWfnaBHSCcOW5eJ5twn uQtOutBr5fQbWztST6HKtcO8VKeS0v+RV/SZdDSRjEPetID3JWNfNn1boJKOXxIADPxRI0JCgQiP 6v/4jlBsopiKrT62Um0RtJyMhR6cDFUXLw8oBZXteiHhmenHpA50ggll4XL0LumGyu2iztTBDIha b08xGg4M9K7LonP4bIleRBRirVpVY6VmdK561O3Lnmf86THsPS5IW6YRz00nmBw2nMrrrdUOyDLy 2GfklnPOydGtBLu+dGjSqn3XZNVn5ydH5dkk02Y1pkc/aqMCmko6FzHGaJJW1oYN4iOsRKPmoHLH ThlbTiJ493O9NC11rHGdfkvvpTgXBzB/aNz1pcqPPgbt/ajaZvPFgMiaD+/rlG+omec183SZEmWP 46I/K7IxXCMI7Ijn+9TtkWPIZZoH7Uut4wL6GqAi5FDB+AOhJldDwVv6WmkvpONFaUZKSQb6IIJw dUHKUACDo3JEHQPi5CD9HI4XlFKkHblToF+6J8dw+tEF/dPIdL4QZPgGc23LcEun1fvuhEjbbeNQ yQQ1D8SZ4cfmAvmP+X0CHW6B4tKC9NzP1bFz53tQClgcBYajXIVZHzQO8EieazAzfk0Q6Nd20ByB mR6Su9b5EBToEW5uByuw/2H0N11Hn8wHg6x0e/vY7EgEVYAgNNkmnYDeXInjZEuko4JLEKX8pa4r SGgTFXkN3YBupUetiuACy2W79I2hZrWSqJIjqyo2NL4V6DbxR0I8eWrq21D4JG3Hwx8ZYQ/7ZqeG Ddu1Cw/vRXtks7KmwHLZHMV28c25LdJOTEFmOUPiTaSDfWR3PZBwHV/UbnLmnRIqzv+XkjctcZCN Xo5cyqcQ3HQq9X6++CIbo4IWElHTuRoTk/UgLhL96XCs8Qf8deNDme8jVRdADDihmqmvGjSn6Xeb UBbm28RcCMatqoRhKNOpAc+CfaHa/0nKpjJkq2oVs2p8IjqMDubUCqi0OPJcl7ckhXZepth2QPoW Jnm4SKrVV+s4oLHbjtXzgtdxW5ARv6CZ1ZAJ5pNYhv2Q1SCHqaLUNxZITxc2llimdFAeIZpXVsxP Ib7XyMuc/UnBWalBKTvuBGaur0u37QQjcqhyiXhJCaITpmxIqN2NFY7vj9rQLEmx2UCPweSVcDiy MXLiCL3F9sxu5uoO1rBOIv8y5SfDXJJKzxobU3cvIPBEgtatmTR4nxV23HJXBg2crPm6Kz8af0Xb snq1fqJUMXe/fVx6c5CzExLfY2HeK8LiebEprz8XC7gIitEYc29rE7t/mEl7H6NKZB4GPtWfKPNo s9+oKIbstdlbVsKjzf0s16bfrHREQlKWR2Ex1Oj+P2LpmBWLMZZHxenxkuwZd8y7tDLEzv59clXI oroy0WgCGfQjwvgaS61Wht0uZ2JOpkbPmFZ7ROJPkvfDBFmaRwzBtzL3psBqA2TbzLF1agRDVDci MrWYdfYdYC3++uGjKccA8KXEaIxbVe6OuLVFG0kSTOHZj+4ewFpplj30pLQgHoRgW+is1geNY9DZ zm7PuiAJOLnGzaMyyt15ZoQIuMFyjkrG4+4gSwL1bMeTOXgCNqXnqYEpQ0avdxCDl65XMbHiDHDC nJlJ5bYc1A8t3lUcEInfGd2XQvuxIGRIfLEi9ied0WGr+e84Ih9GbsLATpnIf5T0vZhbwtS93iIA 1B5xsrP3bN9TVtWjmuuBJr6GeogxaWYFeiflDTfx5Vg40Tuh0B9f5FYhBBV1VFKPYb9w8c0gWlWW dJJ8qpg2c3lb4YBoDXyKy57iPmjPbGdN2WttR8u0NFNLHdrI86TcAm3gHjc6JjLiW5DiO3rAwR8+ z/ek3s2bUpBQBEbmSwIAoFZo4xxcWeWCOlbOamwPFzQVVJytQXXW5gRcugNIpG43ijKpud4jDEZ0 BIpg+3E6U2DojgKe0UWp/2OPeJDlt+odjb+6DQp9OkhuDBDxkmpxxx+uM1Az0sq6NHaT6P7ANsai /zTpDSOJuvhWlwxvMQH7Se6AcZ21hjQm8EMSL1qt5daWUFu3vCSCqpj1b5uQ/3Yc8vmjYrvGCLlh AuX1XUvWju0sw+WD+42yhTM5V42xP0Zv5cgtBlwO8vjboFwoL4xcA6At3M8abVOuh2cpppaFmoep Q3XoZKKgdMpVYzl9bcpsPsakF48IYreZ38BZqWL0Dj0vB8Bl+5ZDz7yViQdgiz09O1j4IbNSF76h M4+1TfpRLidftm6ZlAGiLjJtOjDZKep36CV865PJ5UNtNO9oBCRTwxteWSf6jBaAswGiUdedJpQN LbP2XEWmxYF+qRgvhFumbHkBM13OoK6x43FbpWnFvfqDIbGyc3d+gBOfrP2bL/gG0jDKv3uQkf90 JJ4T8DbRX8P4cKsF49hW7nNaRhnGcCvg23fFrHxuRDTEP7H1iGqiBYxJYcWtOwMJfJYbqGl0eoaO rx1ZZKIXEWPlyDp2QxTEQFs47hhOOVkpUsMJSVBTWUaAunr19GRbyreGIxlHPHqcy3Nuq0P3PbSx mgS+hQUX3jztLh76cfkKCfI9+YcE4uOOZ76o22DN5hcvyUuV17kfVwsUe6iOCHslkEtLLuNTeec1 ejTc6BKY76pjGA+NwUzdcnhSMr51ZPcAeB91rHZN70JicxwJdiBDkqsX2mDk95kDwGcSsZM6W1l2 A0QgwtsILFYUFEk9DgEcn8LWscMqKOZhQKd4z8Njh20dLJEPB9m5chYO90xIbX2Rc4A+uRpUiG0N dbAFQpjzRfDe0/82I692YbRElwSu8A5Jr0oSIp7Gs/zdK8gsC8WILZhaOWE0DHYfjaoPLSBmuHs/ AHNq9aCQEjkThhDbCdaBJxEjCnSuxp9fihwvDdUKntaWvNFU8PHjiYIxljq1hnTyzG+6uUSvO2cN 7t2W77KcWjk1gwGZ5T2207kLSR/of0CFhD64JB3Wz6XbWl7UQg9neohNQNrYfkmjl3Ki4JOLYu3+ Chwadgb9lWjhCKY47rwAEf+GohwqJFjA5e4ZjyiJiQoDVZplIcz3OC8xpscwnIlEN6HH3aQa8IWQ W9+tKT2uQZbyfNt8tnbl3mVdkB8lvmxTzpLhUlBhS992CAoE1PguRBO7b43l32OtGWcvgWpxY6Zs vUvdqcg8soyRQh3Q6xy0hQvd8T60ANtEentLJLMKnvfu7p/7gTH0r/xZN+YWaJKB1Ua4LkvvL3je EGIyIMRC4eRQfNWig9TYXpi7jp9SFps1+8OZ44BD3H3PaL0dT0dJhy76yt8zRt9BDbQMgCghztwb DxCgM+WmzDB2YxrEbHIxYuhnV2zVrG4rn++0OgFMx/j//+Tggip5hNldfdceLXZuzuJkz1GuERC2 BHMEbAJQtYHYqXQYsD2hnkuX1RSmgUK4/Np9A/vuXj6xSX1lJeFmyU8kjjOMr9GzaYoZgoCF9keo YtnPbZe0NgolMY0ZQGeioNtGuiKC5u48zQedlNRwoc2Kx++EZ04Nbb5zWP61EPbIsRU8cDfv5ZED iykAVVgGeWElKb6SlOV7fdNVUnmXFbABRWsAktKEagYQv85rQXu+wXuNjUmAHMHzIsjhm7/b25JF mRL94XTMBjmBayiMUQjhcAjYde4YUvKkAvmTR3ijmbIkKW7ZxOqT/WhxIo9Fwkn64znk4O07nq+s v8RuKOAhHzThkFLSSHd6c337fQPJUbeK3NfQ0LkHdzLxRzwn+TSV7tWfqNhLP2teUar1oXjcND6m 2IpJWkEfD5VGc6ur/gvyWYkI0iN9Vc/jwskQSuiudomdumDa05vzNaNcnE8PrX9dih1fF4fuvs0M AR5sIdk1pykVY59Uu7kxrAu82YOgPIP0ra3XiWy29JFVfh3/UqGcP1HUNHmn+RxFVhsb0DC1brbJ L7lpvyOe8Vh4PPiNZuj2EyqTqaGMVyeSf3W7DcLXzibIzy+bo/UWBgJHqqLp1OkHIo5N6GLj/J3k JPR8TlHSMoGm0JAJLBs10ry60lA+b6CUrkYjvi++zhJyl8fOfXaIh/DCybpDZ2e6R80PTwAgPvrJ fFGYwP5mwLvldEtCyn6XYs+JNSSNb37gRtD8Yi7/2CWqPzNm6fl6uyK3NmSJtB9qIDc7yc1g7nuL 8YrSPK7zKgZRoKRFD3gY4VDi/Qa8G1wJtjfDJ61r5W2QMHklWW4xavYMf6YNhKir2SL+lxUryQ68 DQG6DKDntI5qImHK2zzaBwycpFXPLYcR1F0/iTtce3Bm7CfrFQEOu0tUsDt1nQpxMK/IzDiC7q7s 73My+GNGeUmmWleVLPjbrv/ILnh2cUsq76xkMWY7rSz6zgnI06HjebX/4w0KLo5tq6aPlxD8hApP KTAX8I/p+QQi+BX/F5twSNKqWAuidX/7ncVnCxHhvNRSCZaOOIqthR3M5/IPskxPJfgLFLeBHbZl GdmVN00/6DHUdkEai0NeclmcskjhQ4OmAUd2mXtxzR2Pb9CtnHqIWFH+GdPnapX9AYRp8bKLnzbn voDgYo/PybwanH1r6bf4ALL3VcqIpIjpzajIG7d6xOr1VdNoFtoUqWzVB4Yu4/1PPoCLnwGJL50c NZM2orcapCB/N1eo96d6K4qQtLgr7jiZZh3W7XLSDqx5eYZz2zmyaqkxfS0wu6Upq74CJLpRs6VV HNFO3Zn9gp2kUfYDlnWNcFp5vYIrUB4w41Nt9gSsN/vOzgRVLLPp2u44kfCZZ1wSJ9sSgcdk09Gj Xoiqgd8vdaq9siX1EcSAbZuPXN+82FjOy2HK5UgRMGI7GtCWK1v4ZXBUtMl5FAE5xvolT2oOW+OO E7weFZdJ805EDJqY4fOg2iBKP3d3P83CqHUEsNE4WMAX+xnZj7kXZPrkwSYLE3u8LORp7vzkH1Jt DuklFsVFk6UmPLTJSk2bLwUUOtzAf9tuHEBVYiJcKiea1wxx0vUQU/vwU2y60y4t31HiJuC4HWPp YyHaJyqwExtxyTs3fjnimeFskllG+tFqoCd1KYdVVF5hNYBtUS63D45ZVOzncuMQBqYS5q8zBDGs /GXnNSKmj5gT8qtzRgR8sE7DYHE7v43Y5+YA7qbhoekPpy0jK9eI/+oQ0WPO0N7NMzdvfztQ/Mou oc7iB0nbFbwDBpkpIcGAEBpbXf1eIG0MfEjtCtZ3CQtAlJbWOEXujWRTzNsLE5FkpsZAz1f7nIBK Vy+zNu6re2+ARKRmsRYcIniaZmzcKEw1AmQo1wy6ZcXzsFB3vRJ1OXBU0FidjlaETxoF6OKRA6aS 0JZACreFEDMNcdJsiT1982jQCzokEGgqzXL0+VTyLoS9kSUWESvPY47IzAdVFYIa3m0RDxefUZJk /7vI7acluDAclEdiulYmUSeZ3PZ3i21a4l/BcvNTs3aCPBQkHEOaVCFITw9AQR6SY2ouB+NhZ5Nl JG89GOt1Upn/lz/67e1l5GUyclMY7h0mNVdf1AKGJjYRpEegI5vefrgW+sQ549xYwWGvbsnlGAXM 0iKIqDTsNFNx0mailfR2znmJnudAgc5maERZfZVLjFPKBZIqodLd60l9qz5cxqqANLS0fcI8diUz dR92ObI1B21NYfigYPNqyDxd4Ik1VXRNpWA2GtcnT19L69XAsBLE9YwCf1UfmZF7Vuikd9Yxj0qe njY3vVIBR3ekgGuKeYC2GpA4j7YYtwN8ZURCw4BkWp9/OfPl59k6UPnq+zitwvEHjSKFArZksbnk PSCJgE+ArgxriPKOBqzcTMIAbsE833O8o1ISUH8BMs8TcIgvxEHtc0MYpq9itiyO6jMj8P9Vhbjf +XM3f2K813oxNbeXbIrGb8PIvyTSrlTUKvmTO9m8qjd2S8KKzGPSeZwUwWxBX8n/hfCvIh0Sfj4m 7T2l9qVN9wZFgXAgH7kIBzaeydKNFTT3A4+n7s8KrBhXpAvXAPAFNUk5jgLrFGGSikvkBKWRWMmg L2+TaM+sWqQJ0cBjPeYViqJ/pOnnHPEGn3P2O+svIfWJZPD7GNmfcFOSZLYzQp1RdVdux6bgdIcc wDdV6ZONlKCG16HTOv8ldzXhDqRAoXD1ZYYwhKF/pVQSU8Oq3fHYPgXJ3uR9r82HqZHGGK1379Uk kFtyD88MSibkkFyAqa7X47vGS/zzc3sJ825DJbDkxNYgFXAsM9kSQf/jD9NEYILW1ZjdNc3s4K12 2ncbo9fiFVfJ6VtYEGpzLdKMSlYa0YEQZipq6bJ9WyugolQpLgeEKkGQQN+xNNidjnj6YDEUgQen lPqJFUy7TiRrpKhGK1NXSImgcPvwlsaWP2hpxq3n0tnf0Cua+SKpfYjZiNOKJHWTfOFoPi6JfCqB 9mJ9BQurcdIx0UnzRAaDBt3KeVrY2OY5JoF2RcQRnvCULfD+cz/p98N2brjkCMho/FFW6uBdJDLt rJsW6qvaKNU5t83ydA+a4uPpuQbUEv2jVjkITaoCFP/nLETu5P6cFZMYjTY8TyN8XvPPCvqveNdJ nYl+Ts88BamEtFsNq1O6qATN5nMvh8ooRRPLUnw3sNLndIiLWH5cYxHZtrWdP01C5U+euyopEUf/ MKwgGqrtfYiZAVWTD20wMrrG+GMwfxtkNeXgH+3j3fSNBKodvzKmimxrB2Jo/PHlGMQrpo5uwb4G DdERhrBSErkrII000Lg2bE+cqDUcSRzADpC7uwqGrtYMB+sGiYGd/qg8NIsZ2e6Z9zIUzn5xSH76 FPwHhCclYpcjQAJVenbBH1UnoOgn4G1fVxldVDKVwRhpW1sDwj/SWUCwYmLO2thK68jv7S2BpLfy XX9p7outTbyqFsKew1hh9TMAsK8uogQEGnOsQli4EGjakYkZFOmEh2gVdGE/UcImfKmQURZzP4Pb C/UFFV9n9L9Qsod8RMK7637orPKDD8i6g2SmvQXmegvnF+TdZOv3iWjtheUVO3Tfxw7OjhYZA+W6 nobsxcOoO9grL1rX7X8Y2wRP48F12UdQZW4rV83FPo94eQNnroIkEholQTSvv0DtYfJbztOXC8ac n3CceQYLYzb4BzY7v5lsh8bTrWmOPN/RjFP8EhMjgr96RvKthR825Apg3vD/HHxE3+nwiyq1YHuV KiUKKI/m1aGMp2LwO6p7E3CXi4tfL2zlTiicD18q04Vg25TobBWHgvpBubiVeISiNK+4GqCBMw7S plwYXLFptjfcO7GsKQr037Mz8Ufaw8lmnPHPO1z0TEhV8U566Um1QSF/Ox7ooxvXQwYZ4+c0W1vk vWcA6Sy2MFvtn+QbJfYmZ0nTu4ywJed4BB5rzYGQVUJFOB0O2g6qvnlbw5VePtxXG4FEoSlTOePz R3W2c3fsTwZLx/ADu5QfKIToM1mLVmokXfnZzY9JewITs6sgoptNuwY+AtvH7qFmimVDCJVn8p+z 5C/Tc5A7S/2cNP+04C9edqNDYD0bI5la/F1BZThem58WnfUuM/9m/FIQu1rIXu/4mpNWwAKRdrnD SGSZC1m8PoxYkUSXogQwaEc3M4MNJR2PcTGyJFETD+vA8b8ScgnV6irXO6NC7cYbeOis79GXt6Jp Lo2DYgfwAhC8BOhgpY96nuUB0xfJeL6yprX3yMxxUEZ6XZ5YJQ4vdClFXXPyhLvyA3/+4iIvqeI/ YNZfXyKp+ZNFBNcxet1pG6ylj5zqCTb0lLWoD3F1hnhopu8XvJ9nQInIpEGA5vc/gXgVbhSMrRTn KZclWu3ZoZ2LcK9HLBLvj8Vjb1+rWXtUlSYwIZiMG3VTL1eXCHJzZKZgxhguErehO9n3yikw5ZpC 9PmR5jmAJStyCfy900dvOBNy1lzjWC5JbQtAIN//VjOzrHSw9t+dmpL7kn8Guime5304iLCdHNWW EkMkuiyielEBpyloLjwqiZn5LGLB7eG3rlFe440A5bpkwCdDjJ6U46+hShMwWqO43Ra5jy2Q6nNf rhTNRaEaPUPZ0WICqurDGzvb9TsZ92YqPM3NLdYabdGo9st6WTwqFXydrDekfArbjreOK19PAp15 gx87WFc6ohoUDkTgxRlbWvGYbVuLtoJBgrrnG34GJwZZ/f4Qd1XbbGoc0rEOeYfaYOZ3E5WEqy9+ naHCW7oekRa9IaoHci9wDSg5pulVxN9YD0qZt218pr6UqgAk6beVJjBCs178SzsSVrFfppJB4kG6 t6zPY0MQ5uQQOWfvUUIICLOFDVNnJ3DrYDwXgDe9piVopPc7RvxBbP65nja9Z2VU56dF2IwG0zLD i0zE+JjwfY6FPXU7sGJQbLklWjoJTMnYjdW8AvXlPGNC/1yNbEdEb+vFnrMrO557FoEqcRhSYNvQ 2UYPwwFJ66Za7kYFQ87225T9At13rf4G8NKhraPOdEIK8cAKl4fXPgWunNGtTDb/3ZhT7bCWKXBp cYR+yQAXmCY6CA339Q132iSQLMIf+/3VtpuEOYWy723iz4Co3aDVf3kN6OWZJ+G1tOirbnXaOV4O 0JItt8yhsXNt8iENFt/6sgJKk/MUUmDqjWHTxW+DsXrEwngualifglWN1dbFthiUg7AZqD+UeUyb r80bz5GVNmGwyww1wccsjPJP5V+o7tWKJJg8xtX5FsHfLx+GT+hDozefpyd5JVWhYis4f46/NNi2 wYixMz62bSKPzukgJ0NU4k6aq+4Y3EBVPwKgHErwGEKUPsvXXWMFwIsCiVLVJM/L1+W7RFhVRi1V aqsyfGN5nCsYmOo29RvY25ZVL49kZ4KcPwnrdDSNNF3G4GCiSX9RVcJdtTxU19On0/TZng3jct+J ZrcX6mkHfUBW2tCelvsGuVr7CBNpOL3hhueiDNaikDFQLT/bcoUl2XbcoZYUQUgATH7BFCqvmKoy at4INHO570q401YUa6UZlM4/VEWhk7U/u5kyeVCLpBJ08btykv/rS/Na6gVJMUnjmpRcZ1CMCbs4 0Iu7wedI3VEvJh6WDeqXbhPVbHjW8eaWbN0MCAa7XPPGYnTkpcFl4Hx+/57QbSDIi+w8G+4yE6qM UVFV2JrFpIGQ7uDbLY+zSxmWmdpWtZYN+pYB2kWQI+xoOJKC5/iyii/KN7I7zD7totGuL0wQMF0i Z9GgvlJ4pnkhc8njw/CZwy6LQoQ/C2bXR2y3hvIcDtWEISGBLPSnXYWvwCPxIabcXzSdC6tXvBo0 L0lJy8ml/ZLjE/Zv1CZyQOUgVUODNh4yuCsp+KvIX4P4Y3wjv+8O36jYl0egn011Zm1AoqL6hIeM 9eRL0QYDe/dMA7DRQBLb9sSEeK6QMSdzs/fbzbBFJ6JepKoUUN3DttFezqC2x668AyCMwSYQTLVB BtFrxh19V/OoF7SAS+6uTx3AeESOSKGdffaWxUazrQCZdDkrmzhVCQoRQUfwAQA9F1Xr+wuQV8jN nLx4PryC/8bboUYzvMFfR4xFCL74xqahzFTbfxDidD0uWIG3xQqikpb71inqO1Ty09Dh+X+UUizZ sEbjx+zAioVptV/Ial13CeDC+xsCGQicnffo6grb3KAJ604p3rBCshyeoC9m0jsawAW4JGtymZSI P/NvyWiAE04xz5fkcZ2v0smU/wwC+gbdRIu4WK5Xf9nGhv2kbAFQcS/Ll9uslSZPKGcOMaFErPBA TMrfqOoivGxpTiHTDiyN9AcxP190QPkajlDiY+A/Cljb4qigzFhMmqs2rQerjRIFVAFlQcJNsigx a+t7FdIPGkcAw5P99q/M5SRYbJuBgZRFqseu1UB4DFfGELjnZ/awUwVUxqHjY2iS4k6pX+2mftXs ZhohZpnc4dwujE1YvxIvwa1tVMl7I4LtkCLQ2fOPjrN0PvOH+pArMHxp/+qnrcJepiK6MJWmqfVZ LP76fQSRZOW8209MYznaw9/zN8vF+76C2kXEpUpBSOHltdk4HIqNrKAealrtIeFSHRwyK47BrWBo pX/2fEy2zMMaU5kSqsxbRBzQ9ATmb/0E0AnT9AOuywprD7Kq8zfY882C6aFpSBpa+eyq93qsdbBE zXiuG6eDgeLj6HNa+tGanLTxzj+4/rcpi1JAiicKOJkF2peQeGH1Yw1V2dDdf9IHAhYPsizzCanV 5kHRB1hT3xbBrQAh4IPKJpqkNQXVqBEhjH3SFPEXFOC5/j1cttnX0DD6/X991MZq1F280CsmdvIM Fh4gKawZMjjA5bC/Zb4zBUmYDVB8zxSt/PCrM+dMvQfXtSgHUIHGi/gLg77CDqQlqPyyaMM1Ha2v /O3Z7ZDa3NvuQggdeZExz9hQg2o+lloXlM3b5Xs4DDqQNULzLR6S+iK2l+aJdD7/2mfoLZIgULHh WjAJS0NnotwrLvgCeJyDcYfqozaS1pd8K85OEBaq1dCWGNQDLuVxLOsQG90CKjlt8zfU/KHUDGL1 VNecZ7isVBJQQ9qkAJFlnqZXva+UJ2FTZaA1P01vAcYqZZb4wlGt/8tNIR8SWSTntEn33aOMHdr/ 3BUqLCQAbE8I/8BX4J27IVw+4ai762zY8XIJuWSrFW7jjyDC0HxIUmELAhtcGY1PRWn6QaK+K8TR YOAPM7wd5phgt89a/zNOp9vacT//hIbWz/aOsfnc3ee0fJF8RXZV2hvPATwQ3xS2zaKSneIgreVn MgCO61VYLZfKxLAE2SHHCp5n1c4FQp1auzm/OnvISPGhUlQljTAl9Nm2ngQoTgoqpibfdePgWoMn LC9Gk+nkxKbNthuD8q6HrqWkevSyYOqOgcl0AXxSyPiMQVlMhHLAwyhhtIlCBLaZU1fYOZhJaQeI v0JAzV4YNisX/DlwBrxvZn5OE8CkYl4BrSyg0lnPmkHlJ8NON9duSmaU2cUd8YJE12qT13nZ31sp wjLcEx55ZSmnhzcPIxPWVddRHYqOXLYkh3mxZ9fOnJtLHSbYJYS3HSLmUOJYUEIIzUY3ZRy86Ra9 S/2/iUM4hylLYYPJ+J63A8KZWIld94wrOJH1mzdBNNkt4gwEJDjbB7PWg0O8DmRyQHYK6iVe0Myh +T87COtti/JhKcWL9d5gBzYk1vH6VXgVD5cul4aYlzkju6saueCkBMGbNFg2F3xxyqYX3Y56PpU+ B+t41cePnvOe8aWMu25Nu3a2aJmftx2IWyUfAVoSKZJ7kc4ObIgfOVZmZ35E+gcnQZfS7y1wRf7f Y/IB41iQoFgGzB3uGMpWDQHZjuVhhoERFcKRP/GE5wf4VC9uUE2DV/lVzbE0Vwkpdcs0ujYA1rbU y5CZqWAwI98wSxwqCoI9Aq3R1pwuq4++IV3ZiLe+jWWVnx6HsAhdwivsM61z0f3bRRhnjOfHWvSV WDAOaKvQj3cDTCuc8+plhm1YVeXMO02f9nzByScMseYBuefbYJIGY+jqnJx5bwSOag9hNYBE3hH1 Tw3iAJpFk+MhZbpSglZ8pPbA0T/NcHZbaD7oawBZ9DpbLbpnG4EKYMU6Ducg4/ATkYhmFay3O4IG q4Rgt1UB6HkdLHBuzf9VYFwpG7NBqZmCzKsxnb7dwIfc8vDQjLfEj0QAkRTsL3PHz9FRDLRV8pe3 C67hFNCtJYKwo2jfvPhMdEAMmdRRgsL0beTFQI8/lE7REz/hSrNH8xy+M2YHM4W283TRntrc5Yk7 vYzaO1U4vFqm1qISu5DA6uWFknWaKro+B+EA8jpNYpZ4cV8sGpsnFePvzrS1m03cDcg0Ym74w27e /twa91wKPh6jcEsm/herTr5qF4a8tBYNAm09VmOh0rkGLL5uS9LbthmBorh11ZDb02YHZBW230Et 3VJ0A7U8RBEYzArzdLIaoyLZa6ZzFDyz8wPKH5+ioNnhYpRLaCuNd+xA7w9dVqUfbqa/od0X0SG4 gwOjkGK99tihnkWfphYZbRdXtzhFTrsHXMZHbSVvRxVTBKn33wOMcomXYKw93sVD13WbwOexXpeb HtXky3gWkUpFOgcmYjsw57C1O64y64LtUQ2rFRKlA+ZqqXLQUphbJG8rJhdvMb3FNW/vn4XDIf1a U2wQvz1qklTz5U5NNR6tnF6olsRWv7zUmxSoBG+gkBxG2Z/zWyP1rqXnM7No5MPpaikAcZX1n25M HNACLBuXtAEuaxgEsjLUzg5O/Mxcu8s/Klm6fsxn1S9oiSYglrw1VFSmwo20JQ6SmHLGTPgzs4IP 2tkEnsoAzi56KLnSdPooe12VqlHfzKdIp8qzDLDQjSUxmGN9Ah9qZQ8rlL0neus1KuGwQj0JGlpA orA7KIxLJHP/iE/FTQ6DhKQaWAuxaSJY445kGqQBfOrotN7oRGuZK5VAiBDtfGqRPQrKBpdZTHjm n4Pn25PC8Z7TAbe/s52HqV8YSh/9lv+25THx2stnzFOMvKjuV7ljMQTvzoThxzGpvMw6oG13Ol7+ vrCQfHHUyhH/vgFm2b8Hja9JGKolQGbGCR1SvFTHW4UYQ1WGe2m94AxcLQi16DNrxP0ZvY2JqZp4 e1bQqSQsLU+/z0Pxr3c8aCLfRCKX6LquXLQHx55yTLctCiosbZwxFImP0WNRqopu1P8cUCDVlkpO LUkupUoEGajaZUC32b3AfUCajwXvfxbTHLBcEVxUC0en97NRB98dtbre9qiMkGdK3ouotpgfO3MP fZZO5UTCTZngMA/9qTNB2fJ+5qY3uN/nBKPlV5Pkz5LWAwgpdDoH7cEhhMCWOKlClG9HNcnBcft3 fPUg54aXhPBjztRAbLH+DoMkonE/9Zs52wUWg9psYjt4OV9VFQLlSdmP474Mt0tmFJ0wcjaYx+pO RVddMmL+rnoe6YmYxyVuJC13FiYyk3VoZT8zOTs92KQVD7ZKuhfvvE47wdnIa/jJ12F20ljCy6Pa TJ4pBIXMq74xTJoOfJ+QNDaG+E30oRSrcykJ9PfpjgLBchuD71nocf7FeFRojngiUIm6U5bbDwde AxJRpcxRDHVwNU9vK7WZV/kK8fRDGrcqsBnskZXqCrvzSgGmEYVBFPnYWRzfAfBhYh5OEjgEkzeU LoTDNNWF3YiRA1+0J/Q7l0WDFFQrR3hQjbHgkn+g2Y8tZeqecUD1SC5YKLSeu6cF9YY3LwwaCmui xcmF+Rg/ERezeP5erubW+xBA0G3MNqionsF/rwqV2ZsIbv5mGypz756PSwnXSLDWxahi5YJQIcQR D9uCioexl9P8JhE5ib0gLx/8/kAPU+yF5UKzv4NKOgUnJaNKwtz05nRLC1OUJjV8cs07bES9NiCQ aa4KoETNCCAI++pv0wBYdcp0kRHDDvhz5AfSa6McvPuz03vWVTBONOBic6Kd2q9i3xTBr7V/9zNY dRiOd417l7sdMcgIz+Ey7423CWWPGUNQ3nEhY2xR+s+tQFZb2oIHjaL+zCbnjtZPfTt1zPWX0YdZ YTAUqQRwLRjvWbVumjLx7pjvkavdU1p+03TLdK/GwbnWfhG3EJi9Hu2mvMfKeZzpKCDurXdJ8vDB XervxiUbGAlnF29oxfsyAcvFnJP4a1PCoXPKFXxPIVZNZmw0AdG8XQX6NCQQ6efdnFYVHoQKQZt0 z8diMrhgZkxsTfaLshAB2CDaolm9KKp2pRWJ69vPsiU108aKxe1Igc/e+VsYsUv9iBLGvHhzW+Du LwsyD1hrYz51qG6ALVDqhS2PWa0CjlTXyjSXf2j4QfiUa9rkay0TYTLybVLIt7/FtbguayGF9CZj fZD3hVKHXdf0cr9XHep2gy2CdaPnATk6bzQPnXlTcyBMbMhX5rjhQujtKJJ8Q+XBwrcYFvPoLkcO B3/k/bORZ2NBwsXj28s7fWH0DCjOnSyyKoz8bB3eVAVoH/kVO7kC+AxQ2DWIVvsbGjH01aZe0Vkl LjNZ23ui7IcGoxXSMqmfd8+1WdczlqSv7XZzdFjRFghYZWJOxoNQfoZor8ucFEWJ3hNujCjajrMX 6tRQHk6ZxQ8hJjumOh3ZiVa4RSewrdSkgLYp6WpAPeuxD3DyNRD5VKxe4P0VtbNz6NlMugPU0oCB f/oFvhPxpC7NNlyfaFh0BuDzcHJS+qf7cjswVn3jMRL/z/pIltLLTb/2SzThS1x0Zli8+azUQCJK 64ijVQuHwS2AWYEGVmXSW2KVVR5t9wIu54dmhOP+q8RqZZg32GqwmjIBDoSHn3z5Z2lDGY3cso9M FkeoehzhBjWBRhFUCsgqdxHdMtHtA5Dfx6JytNOv+0QWd+iWWQQpbUQGo/etkXJZKy+NDZ86BBMH SQlNsOQF+0VjAAqv9fkjWK37ZjGgCNZE8bWsAW983imsRnTKFjYaILiu1qxV5BVNDI8cxo/mlv3J xpIDa6teuct4Iqvbu1gJZhFVCUETtcLorcoskywPB9utKYHLd76MsZsQkrQ09BD94wmWLMgUsEHJ G4XX4s7V5gv3p6H673dABXLW+TzKg/FZmTAGlkAX15+rA4/mlx0UjDxXtlVadRe1mJlFV1ELt0Fh mv4lVL2gdo6xWZy5LASa/thJtha7JhVm5n+FBXTwuU6Gj5oGL5Y1qMjb+qxWqZmnt1TKRUSXsoya swtwHY88jU7iBNg5MoWqxGpUQugNJpL7A28xStkWoVlXR2AO7lW3NlWUWTUG0xf9W9KrYOu2DPdj jFKDMwQ6pp0tHXMfsXYWp3dwxb/zTb3pl2Ha7x34Bkmv+O8+wMxaIw0Sr0RvdKRTjRoX8rcvi1kt P2xQvAcTCN8O1EL9V+O5lpEConnu4J4dzLI2uaVhC1kdOl0TV/9GaQE/KItV1XBi8BplP9z4F5gG eZ9InqWJZmBWj7poA0+2wHIfeP6jygRlSed7Jkoodl5BmqhJNUK8KvYR5F0rWCCB/iKI4dqjzptC j2y3jJHyaNbAhKvBZzrTLEgjSFrwMrCZeWCJMYK0+jCiUnQJcQhcoOBj3U9135BECUU5LLICRn64 DZdu3MAJszO+HIbsElj3C4tUba57/ggM780GP5yWnx0w+je1d4htRWbur7IifR+tsRyyTN2a0KHL soAbDNzz0QKQZ8cWld8cJEZK0zSDkDhcI3FO8LRoHPRnfhCuDtgt4Pcfe+6e7jsyFDQCmM9tYDK9 DiQxtL9oD/Id2MOi+LeDjQ7ifX7NA3+m73Uj1KsWWwP3YRJ0o/cJBh53/OpAB/8+AbBnzuGKD+lL O2FO1xO43Y9t4is64rUzWsileiIHIMKr/k1KrbkquU2Yi8/tRZ82YnFGJnDO2bgeBEkre3qSLhXv /aduExGTp0o05YFuXcx06LeeaMibfPphr/9uXu6u2dPKCvtKo+TkXe+WTrxsCnLrZ1Cuoia3RkWk WTrqJhptsCxONtdTO4uDu+5ioPcUXEzcPt9oDwCYgMXOnDDTW5fIcEwHwEUQvJg2SSo9eLw0nUN6 NjwkAjJgzulejjpDZmjiXv9k5DsAr06p7wpN+WxyBomabqrUOv5AGtl/OetEs6LDolEyvt/QsuaH jXrTmlOUxyxlQfktL17iWbmSif4fXFyq+ne49Nnw0ShUT63UfG2+GTPNTn8OEes1FUwlLWZgk/6P ias59szQkiCssDf/OrQyHc3f1RTw0vRBwOFUA8A/4qIBQq+O/ViXefoNC/8R3cI+JjtiqWWRJDVf UsBH49K8SK50oEpQUMrQW3Bbw/ZLRQHwW4p1KFp/Mdp8fGatnTY6HEkFIFQKuPBG/2Blvne9+/FK fpcdFZB2FT13UZU+O9gLTjDcmPEmyqP+jKN9DNO1siP+JFou1XXp+uKYoX8pWAlBaX0Ij/TLmyVl gJwjogiQu2a1/37bk5ehtMFPWTmsHuTRGWReZ2HpJZe79AS2uTOWwoP1KlPdBrA/u1vrQHWfhkLB u+/hhT5kgIXA8NzS+djK601ETeqXzEVL6LXgv7lLyyv9TfY7G0b9957slJ4ot83uPW3DkimicbkV MBnQMixFXd4t+VsFJgiprE+/YLwsD5I5Mu84Gij13EjzghySu/B+jjQHg8Pe2QJSrJUIHWbTATsA UuQ4byKa7G6UpJsoXFGii7to53NIqaA5I8aN/3+CQh4jWmXXZCLNguaIQAi0FE1pYUp63V9Ewdg3 otiSPAhtnryfI10sUqzDI1xvvo2s6OtIMCnMfkepgg3AALKQiFcmlpTHajLYkF48u7R11kV+x4c2 /GMskZ/xvxeeqiloTkUxZtAc2X/c9kJWN14TPXgbuAPNo7klS4ZpI5wgZydrJygEjqc1CxZrzv2z nGYL0G3GUcJQXUFVh3tkf5AYfP9Pd8IvB7iFonwSj8EIDQdIj2E5y+TQXsKpdMfApm1LqX6AdwUk AUy25YwwbSBFimtSpvM/RF6/Q4fZCyro81wCsaylFMR5X+CeRy64xou8rajf45CYHqpcF/Wwnpdn zX+oBhYDQF9VclND95Un4KmtHDF+QFK4DWGGzpRG1+Z55q6WkpcxmF9/Z1Yh9ryQRxGt1QsJ54CE Sp2qQQu0B1yDb9gJnqEz8SXlQypYqNb8ojWv90vNVwvMgRgN4na3DL06BDEZiV6J1x+8q/4Kniil 0Bmvfn1H+YJ8n+S5dw/MfAKHUtoL4cMMO+YDrtj67+VjtqVT1YRUuGHEGRnFNqBhkp4r2H58y/6l Kpt+t1IifUlrFljHGSgZ+wfHoOPasiGvQ1XxIXWqJcjgr6YCXvjUamS+Py3/TZdG5SUd1RB2DkkV YBmAKYOIftw7M5Le8F7nbPscIVtSK3s/72oq9UgHQzFj5yW2PSaO/d4/tNgaU34wWNq7bdkcq37y 18nQpIVVkwroWfD4q5Yd9gOShmxeewBO3lez5j0UzUfB+v41eFHJPAIr2GrqeMJsEXd13KrUhbGz 2yBReMaM9bP1PXAMPWWBFEvKlpzo4De8belWtZx4/dWXq49dvj9TSJgn+uuIsKoSGgfaj+TiQlyH cA5mQzJBrhMqyMu5fPX/fRpR1wYG9tMO/fNx2ZPNKh9pCNgTPKrPoO2nYt4FOH0RCeaIZstX8fdL KzMC9Y5lX+Qvmor1Iz5uLPpceCA/4R/RnhYtDPCvILWRUlKRnM4eK9CzJctqtAdRw4RRlodBWEyK TcUpOZ/lYh7eTlrIfFH9MMPJ4/hzrh0zSrYaT6+ObuFVi/mgbjs+rAcEbOKHZGxNgfye7olv/EdZ 6JND+Pd6il9e9/diVUnKhUPpxRKiCfslP97HH7uPlHMuv8FLWbNGDSO64F3rtKgNnuIVT3iW2oli UM4ymY9oVbjggRCJAP6B7fjRoQWGo5ZVQx83hJyf5hmyZJODAjyScr9t9G1bVEI8CFG3tQN8shOk +kufrZLjAyc20Hx1sCvXw+SwTthZBDXog7TZ3P+JkNrL7npUzLUYpNFDu8lwkt6PgnCbVrF2OPlv 8Mn0HObOCPoE2USEdV10krQAim8lyxFS5YXE+3PHN39PHpLJOT19YrFeswA/StHttpUDCjZQQkd7 uXmkQHxQurq4kdLskA0OeUrKUYzSX8aloVNp2i8dx+A9E5COjWDaRq7mLQvwzM3uAPoQlOTcOuUv Dg/itiLpELmslH3Y3L5QhW09KaPyJ6iU6CeyCB7s+GqDHuZOb79KnjjMGsmvPzGJWA/MgI3bh7Pj EtcwD3/U5ee8n1qfZiztB+UeohUrCTRW2AqdaTxL0Zjb6nGxYYsDTEj/3LdYnyi9glzPTJtseXg8 R6FasEaj1f0lkBeuK2cw/N90pRpHCP+ue2cC/UzN8CbQ9l5VRfKAeeJ4C+HuL0QDv7M9mx823aGy YlNUddzhYB6IxsyievHvCDdpADys6WgCYDigtDTn9friHMYBjsjcDnDpyzv26JoMfkmUYLz/snJl EF52OYKmNkqgbAnbldbl72dMDRna9vcvcZE1tLhQgTNwnDBstkY/nrLk0ZaJ/mOcY5PJ0wlLG2RW yMnBs+xsal5jvRvie2Qh+Kkmmh6A9eFsHhpnXe/7ETWEr5WT8154BxftkX6UgROrPq4SCf0kbfR0 +DWqM1k4F6EqVFq+PfXDgy/5p21ui9YKHZw/YzgmlORya/OFiAS5x53GvqOhGv6wrBmPXy6rZk59 yG1E3XLt27yf2LY1kWouZlMR1wn7fwga1hjyF0rjpNioGo1Pln4W6lfRwIz7CMx6Raq3fuXAcRqs Toq6wa7oZ9IsBefTEJos59dv9FbRYJ+fOdgtub3XYL5Hr9Tg/dDvffkGKAXGBXQR/krrquWPt5E5 4Q/6L5Xeo2M6eeztPlKgAfvs56fLrtXA6iFlaQhefEKopt9XHS/zYoZe9zpVrlEclQiNY7yoIJv1 53LAEXFwniqYQDm/4rxBVcfvMYCn/bH1UTI3LVcJ7M08QaurlNYq+5nK1SVlX9l+hkbBRcYzXlSA sCRdoPyxUxL7NS5YqL8UGiGp1UtCBvg897b+E8LxTcxf6H0mCTfCboL6uogXrDcSuh69v0lMImLS sv4C8sdfZYgl6XhqqQtgnhnzu3SpzUCcJ9XgGbL0tSJ4ivxv/iE80YdMiXtrzdeGrAil78eHar+A VM3aUT2xgChqpuCxvH6oSf1v0bWuX1Dwo8EXL9sNlT2o6lJFUWkPbkv4Yh66Y6lTpO2BA09p24jr nrD77/nymElbpgJgYSHZ2w3o2CiGt6JX06PSYfSqcwNVxUKNYbC9fQCyZHDmsH4Yf7ZY60QGTFpH uz75x6gMraGQUCz0u49kYIG3K2JtT7lgMRE3KOYewf4j6cBEFUKV06J6wCbpwV0Kx6LvUNScSpj5 roqCCm7FTDAUujOImx2+Jsi+YeAxhpQPl9xQEakemoRh3LSkQ4yJYFlgeu5No/3BEDbF70WVuZGr cYTdadl4CWLVxVUpKoJwYZCJsWOtKF10xp/BnsRIiQiLUrz/nEOqGiMzVrZ165TK/OypYjhXJ5W/ xV7jDQtNHxu10V9qtsj+CJwd148dpabd83S5NZIQ/eSj99HSaktwrkwYUJFBnWWqxzPjUVBcAemY YTSxbL7ZahiQn51WjjiI5hyRrOJdSE8G9+Q+5MNgkWBVCVysql/blcLuiDDgdKoxd48rmsA147DA LYCJd48bo1UYf/IXwsOYQGq0+k3ny8DIPZp36HKyRIaQEJpF8g2yQ4+Vme/ivGEcVdRcL5Qk2JTb wX07UfSrmCnxofioLp7ET3OOfa1R0WS33TaIIPUk9G9LLeCsKorFV3uLaFRFHZqLBJcy7WWZdXfQ 9rM3TNtqsLR77i7vp1cqr+4SDzYWdXkyIX2EM+0IF3aAQT2GhTrNE/Pg5FRfoHapLOdSANIOyZBO h4beKmPIzfh+FA2mCL+N2xJFxVU0XycjCcxrqJ87gGSNU7OMjYXq3ZWFEe3z+4lSu1ffAsVoLIkC cOMM8jzBLbgmkIdxw7rAT5ssbwQLw77L/xzN76VCWU88q1i6HlwuGT903HKDycro9d0n/VmOuJ7E HVIYrF/7k5EI1c5db083jBvCn0ps8r9okjj+155Zq7YM60fZpvEP69siuOSceMR46AbHTdiecjrq vtE1TAydH+4buUu2XDrP+emPGsX65i9lj40ppQMLNFjSe2hRD3nHZmdX1tFClpkjgR8H453HRVKv 4RDre5XYNTDPkazka8lhR1z6HxZsJlI+A0wIw6PozKet4dkKYglTg1LANCJxq8tWZafQeDCvGnVm k/RLCeV4QSKsJxi5Nl+XnBl0C0qB1rKiDne6nrLGGWv8sDAnUkJrJXPYBbK/gQYRPUTeuQtiGr88 2zc5tk+hFlh1sNu5gqXPJt2E9XPrMsuL5k2QZ0L65To9OTMc/mAUQafQEGCC6AT7VRqh1tMuzCG1 bh5JBxDXXlxUCrNyoIzSo6nb31TGaqMxW31QfACYlGuplHHfFpCIVt/taI96IidFRJfSeBtl4qba dwUxerlO6CB2Pz6arwrSOigTUV8JUT2aRh1m60JMTpyWq5mLqrSgPUTc06hu3ILU2ECRbYBSW1YT QHCM+mdcmbmmUc4C0vkyxZN+OvL7/olcBd1sHEjV5Iz20QUpksTEjQu1Tmv/enzRNruQyLo6BPM0 c6iIteDhppalfnlQopbXdgBVd+e557SBA3XKCvYG/HKJDZhbW3bfUp1/DqDYPMRh7Jr+5tyPNmoN AK+jG9wPhNuGhX6qBW8aoJycaoTXjzj2iBlL7uT7THh9l+H5dSu9QcQnZUgLUDjQTz3au9JkyJCq Yspo5vD75P7dH/TKk6PueRh09Aymc+/2JtN0GAw+0H2wGlJij1a8Evz15EvOfmzBZ/0RJw6aD462 JuoW8i3c+RGimtlyrNI72s+dc3+pF/rmmJLI65wzhDG+XcEGTGRHCmDfrtHXTD33okpRORX9LrZf ZMEBqITTvG8WX03idMhG7Zqq3RlEdVmy7POEJ1Cu4lsOePcfOmhpOhDsS1fHN9LxhSiAWr+tjmtO qjByPqxsLMXUYWOxVkpYoLGXG32LIi6kMcLXlg06yGmIk/WwTv9l3ZRiOc1iBw6WyiINPDOdRchc 8/b/9zFfeJ8knR6Eb5qrNSXyjmiTu/AIeiMEfd4fJ8R+xSCapwUEUpozGmwZ5dDka15Vm+0BX379 9EbrgEjMVCxbtfdYcrMA6agnreDs8bYHG3fgg5IyvdHx/tiJ4+sH4Z4bSpDtp6eZ0IT4+fORH/Xj NGLXoPicKMj3S3yKEe0dlvGiMXq7VExMNtq5BXTNI+s2fPRUJo8wCWP/vL/mlgo9SGh/6EYryEuQ o+hhBm6EjrayYyzloBlxxJXLli2zt7HXXpNoSHDLrloqilO0aqCbFJqLs1UHFRUrH8JKpd8Tq4xZ vAl17tedYhn05RzXSIinKgAU0Bwxaq2Tz6wBD5PWg8ehsJW0JNxMcvM6UfeFof4Fh+h0RPZ7Lbzf PijbW67nQC6phOSsZW/Q4Rkp0XULudGOJhlsIgr9L7W3H3qg3vxEuNoPyABBGW/LkK4YLiPfIaKu i5mknih4ZYJvTbKub71kKg3xbF/FFGr/W39Hqua+beS85FAzWGJ7f3QrQfuOB83Sl0f2ealyX6WP 1VBZcuMr6pacUIDWLnLeRoausKbGiGcBO9T4UcXnp82HITPe5yle/hdXsSHi5MI9X3I1ygNhhbm5 VylFJ3V4C0nmm+0b7MowS2FP/c7sSZlfpHFis/PR8N/aoP0hGTbcHppZsmZSJJ3i5YNNHJQyHjMz toBFK7MGC4twOovV4ynhrjl/ICrfGDYeVW6di+1wYX74R+868VayLj4CWyvJ+NWmxfEFb9UUUW4a qBfbdhvF1m4rJ6ExbHmEyjd5nSIdK566ghiVKRvmLjGnRQWxcMekNoj2v70IcXIlYx8RPyYk09Ea 8Mp8Es8Gxq8RMLJE79UVmDXOnO1iqV0yIQ6NZDMzfHI7o5rjLnVLYyIhx7O5i2D5FVTBUS92QpQP zisO0d1n5H3Ap6zic4JxrkXpb32hWkHVCso8zROWarT3NdMzZo7NoWYEF5fvCp3RqVU6/ioCqa0f 0vnfZ8m/07l3mH7zy+b4qU38wU1ec0gBYBrwj2jqnKhv4zlpjUtk2TuuTKm0oHB/Yf+7S/T2tZsx Y63ElBqTrZ4ZiWD1U1MZHSdg6xRfYkL/vozU1qOkOWHeEDw6V1oCZAPvREHINzPiQpJ5QYfr+wyd JxjxkfACwWb6TbymZArR707BzMGK2CblO5iR4xUOGvHoWrOPkX+7o9AJpZDgFTGdTfT4K5eBAhDG 5KFSHDqfysl+QXhooK+o795a0EIrKdxwcUng+tpmKvCkcb0TNigBkomDF+Q2EKn9BR7ZjLKXWGmt fGEsJlwcIu3VUSlj+m41XzX+x2auP3z7iciBBn649fVculF4kshR8GHXA4lBLeZLN4J3okWb5Mb6 80upCur9VxFInmd3YUvRixZzdDsBfBI/EtLfUp2eeNflsRYcscy0BQ9ZtEFDp459BnjiqjVwkPUR 1krlI8XVsf/TrhmfrcOVuB67XVNpABW0f35HUBcTUcBxvYD8aimhyuhmfKV2apDUozPW1uDLf6UF cCUD49F5Ps4I5YULZhbYKFn8hSXRAQ7r3PV8tgMuRgaBIuhXIlrH4va9/7uZ+XWj5HEuWZrxiroh qBa4YKhygh9WqkedOr4ipjZLiStlrqClhp8UnUno6cWjTobL4wpBCpE513tyObcofuv7wEzD/OkJ hJqdwHXTqrv0t7bTn+orAku5DH55FTUDLYw1b2fbxSa/dyT20M/1zFmfNT3bchMfbVqmJaW+kUt6 nGwms2Y2JmA/LZ8mLLXQ9UO0YMX0/qIbUA1WieQDkFi5b8Ot31djO/rhV2MUYtsVRUkxMtfOH+oF p7tpG4LI+2ZXISDGx3h6EvE9o+wmMVdnAfuCyC7bReCv0hhI7GEpdAOzcpdgkXXuN5G/4P9787cS H15EVRU3ssVA1hHKHvAORaLK/gIMrxhFImjZ5EkBOcdgzFJN4ZmKc7p3bYDM4F5wK2r3WoptkzmW EF8uuG88B1Hyj3ESlq3jRcsWj6e/h/+b/Arw11jTidHRsEQenSyAZst4C5ibZJgc0IvWAcCOhifn WEIL3vntkROHXV9ktHlUmuRmHe4riS/DNjaQDGEYCIgN3x2ZsTaY0Rv2PkQ6Sdm+cky40oexrRCf WwP6xnqNtDme2ySrr0dR9YWRe3kQxsC9prtZU502mYPgtxxRLRe+ZRo1ASkHdYR14/8zwWZiM40b rv6hcHu09UizCnFU/0fEZ4FcjYppJWxuPH1uNDtEiUBsqxVoFrQk7AHpXauL+/TxolhvnNJ2R5RQ 2ZnIZKPiG8C7vJA9gS1vt5AQH5xjrD1cJl/YnPdchHoOlUUi6ZHtx/aqGHrYMW9E7pBHZTOXIh1B gmILbgtvjFq4PO5BhdK77l3vqWObwioIZorp+qQzC4I7Zre6Cqpa2sMId4z7n5+G14VA7WdvzUDH CLHcVoBI2mhhMHdXYGEr1DZKhjvQ+WrFp1nhJzOvc7RPpDXt2oaYUjst1/lHjPguX0+BjBLriRHn VVvSGlFx7CJoJB4N4YTUDVzbO60eTMCmj1PRkqpe315nh1ky6l46fD2PJySLC9y8KO+bZ5Cb7VWk VKZlVdZHIjlxC4JGk957sRDZZEPlUzvvfr0o5INoRXPi4uWCLXIzmfa6DICIsO3w8fIJ0uXuYVab 5NFM3sg900c1LgP7GpmQcSzNJvYYWVgmmTC8+KpZ9qKBWEUUlwBvHWe6PgyixHR/HGVfffSbdGZE pNYt8HvVkcSFTVLVBmcKLT3NwyB8Aqk0tXswpZ45302+6CrqD6I/Yr92B+U55b1M6wRNCDjh/ncw qsyOTSSidaEfR+50zXDdIiLkz+0yaSxa0Up2G4MiO6nRONMw+n9/HOw5tHormxJq1AGFycOAm5Df 3/YUXDDFVZ/CUSJJ6IHyTvnkDW3ytCAA0R5uN1gou3jvfV+2nr7LfcwVnQ/UCHoLlKbJeqKlj/rC A0uiG1y4nGS5Uju5Pe2hxKTVqCTYk8OfSk/lKthBq327P0bHWS6hjBuBqRwHoGU6COSwoCuYEsQe 1XFAduPr4zvE2KX7Z5MbLskw9GIHrzQPgJWhS0wWzbYi3LtVBvI46t4c+GKpPb2+DQ+ZOWUvlBtu 4nB52dVmZGo4QHpo6BHdAV+D3meeIpbFwT69Pc6Q0UNCV8rWomWUti3vsgNKhiXOx/gyNkdxwx2Y 6pGcNkfLIoz5h1M1zct+kbAeMehr+Y3SPY0Q+BgRyVlIq5QovJwUd7P2Dz10o7j12J6lslBw0O3v xiK7hL0THXf3LXzdGZ9vpRtdyaNuD/4gC17AO9frfzqMU6wJz/Y9QWi4D1RsAdDOGRalboWprcAo j/R4yhLZcPuxwXC4/6fSefOt7mtOPvLWXQd8bTJzvH87+DbK4JkG2bCLS982E5kcoe327rVaf65d UOtyAyZoSoXHrCEYujEnRZRQ4MSO4P31LpqqOx6VqgPpvdomEldQ2e/Zq00b+3cCoHenDOpxC3ce umxEs9hTZMOj5YbJKVZfjhUK3S8aiyFc1DEqdTTgln67Bs1Vi8TlZD5+zfexYt1Phuds0+9I4whG 5cgeXgLXl7HfkI4N7k2ZftMerR1pjFYOsPyKQcrXcvz5sQjrYBCQmj7J0rFolcgNmBHznADVd9j3 eplZR9Lqmi2gnRMoybHOnEkjO4XoUVO8k/ztIrSE/kN2b1xMOY/EGBwIErujRP39hVxxny5+qZ1j fSHzYsetPyW6XjkRNc03T8pVUYcN917dNXgnGENp/9IbCCSXnsYSAYzSP9mb4d8hEPh83FKvy9r3 biev1iZctk8Lv4D+8kn2MFgC1VVhnh4tMF1qF/MFKyybnSRTMPWYy3te73leJzXRp6D/h1NYXP2O jlO6jz4eU9HdkFqgt/9StKva7PS8hEIuOpArjBCVqx7z4faHpUqemIUhb6icUzHmJ/I6f9A3Nvmy vOQrfWAU1Gh9YoQOU3OsnBgtEtfj7CBdNXHYzntF2VXPewbczXax4lx55t50uahZcZHhNH6JNUM9 cLdPIzrwusLsrhXJ3OKdFGqVzqlPgWdnr4QDOLpqm5jT3dxa4E52dAh8Cw5we9DZrfBF566TND2t qNh20Gs2en2dwnBlYlMh4zpCnnTux3per9E4aJhAE4BRhB+ISPhYXH3gAmPqxQ69dAGwEP59txhE bS1hZneobU68nc7cftVlC2dssrYQ2Z8Xt2AOnU4Xaiqv4lJHvcKk9/5dXqMStYBGu+r+CIzZ4OnA z5CLOuIsFT6W98Ob5QXwwQ9qPRD/7Zz4NwgdxnJamAaIS4gZk9U1n0IorD3s1K1NUmda7v2GGUPs Nvw+qqWAgxMJ0OSdbHNrsoreKrxeTMYs4wca6Dfo81E9N5Y5Q2Mhi2yvq7h/Q4ZCK55qlnLlX64r +6Otl5q4Bi5BauWrc0fails4A63dUfDrvnlMbWGMOkXZa6asnWjfpOpG3BOikMPKeUz0xDOzJ796 19cfZFnDLsI07iS93tjg2chvFPhno/glOdKXtw+9UMUxmYb2hjQK87cC7B6Yxux7DmXJgCiBdNE0 HmmPl6yFxiph0vb3HOCvbtka0XtC5hGmrlk9idvgTjmK8sp4lFmyiMqLGG7jyY091PyRPz0ciBL2 3mJyQhbJhoSSTVsQIK1fqEYbsrcP34BVhLxmtUCT4sApw7PB1D6J4M2yaATJz4e6rkIiHHEHgJSd VQcwmNt1kTRN9BTAuFAIDtws0G+iaJ8As6FNiEI2DKK/Vb6bvi1RiGRuWwbpx+bGvgT2+UurtUNc QSk7KsSM944ytKx2ww6OnfRtg2JsJ9wF4bSReNIN9m/wSk4f72d6YmZzjlkyQFOVtKRo7GH0OLkq MXDU3ncObjGFpBTeeMppIq/z9b29B39bWmnFUYkY2AD63mXii4CY1h8Se8z4h7u2WohAwKIlrI9B b+/yMEETJ/PpuetcSSF849r+vd04tPgyQUWcS5Gmq7hqGBYy3LUMFOdwHSbxlCrSFJE26m/rOmTR KcDigqN+VmSubQR8QtCq0PtaTfCICOeHclsArWmKSsDKBLKvIaazbIZJWzbLWxD6MRsjNlcDrehr GAyNPVSoJB0AeBsi691uwadoNSh/bYOHJeknc4rmx1yDx8KwTtqn9/ENggMiMQXxiRvhdYnUHLo8 ZEaBismdUA8Gf3YqhYqpZWBOmYCQqvehBx4FUFxOJapdXwt5LsDkiYD1oGpgTn5Qv4hLvrY6WGWi ZdqjIFTQNgoLkpKCvubRBOsQc59+ghhqSfgIK05Kull+SRmYMQ39TZXQAWXJBQstx5287GSX77To x0fd8qvgAftbKYE6y/oEbA1OotCB/MaUOUctusQqbgmWZbCviyFL58n3Z+PRRdBeFRsdpKWZwgYw MRpkdNaavF2rQPpYA3LbTIDrM8Ip3OgK0JUJZUxcwi/oDyqfzBbzOnQbajFd/ARen8QM+xUYacEW zR95hKYSiefTaPQtdqmB0dYwbqwLtryynuF96yXsLrJbPlVOAyzYnfwaseMr95opWammqHP7ZUAp rEl1OgUql8PbgBSZk597mHdmLGRm6W85Dw+g11zuIRfGPbsT+186G2qibi0B4zK9D/12zNF5o071 iXRG7OSMNXBOnMkjxe8yPhdCV0NtENRgkxbgTnaiwozK+Ph+i36Lh5pq2r859f/ndeaHvUgJpi+B Vdeww3hDhqaLqGNKTTFPVhyDuvqsuquOJwqh+oCA08DCm+VPM5AbVOsCdN67m4ABhh/Y/xDQOdfj yQ3gPWEg70IJSz3sL+labepVVPTa5In6HShvJ5PsFz+32/QbBW/PL0eCr1UeudFvq/piBs13jzoI o8Yg0awQu0Izw3ovLpZl0po88VswmtQjBbOWaL8PyjkaEmyifZrYXbrsThP/hv59GJAj6wvT58DQ QCzpIMczDQFHMIgdOaxM4KusShodYQPCHIF8O7GqHpDMukVDvOLqrR6zr+wbmWJHU4n5IR7MsaDT WyB5NZcocaMd+yxbttXx4mLLNHqvMEIwX7dRVpLBKJnA1Q09sBE8aXjosto/UYY7GV7NVPD8vWyB DDL8dRGByXvNyE5PdwNQIPA9W15nluTrSc8z5o8AmGayBqInhHUP6M2lDEWgZO3byqa6tx3NH54v lDaKNoFOC2Pl67NsoAt5dpm+LtcsdwtUi4mzrNPcE5VRYOA56zRl1GqSS2nq/nX+AJvmNIMaG+NM ONM2Rwd30HYt9LY1MKONG4hVXaZYW7nZIkRLns+0ry6gwdrvd8CR7DsTnlhNXVaIEcr21fhYg4k6 yFpWWYqZLvDxICas1EB5tRPb4XHPhkW1+5OR3SeqB3H0MPwrB+/H49UQ46LQaJdLo6e8qmF9H9gS o7GI/Z8e9J3fd+3EtXjw7PeL237O5tz8J7rZUeM0CnyY1lY1DF5b6GRQv2YWOPsHQxKIERRowG13 AA9eg8eDajcBZL2KkYSs8M8IdA1QH/rAoOyhUiy6RSGxDmecEk8UOsUu838148GTlNTHE/c11sY8 4MUpJVneOm0u0k29tD3iggR6MnSik8T8LkgcV9l0xYNq4+I/qYBxYV58TNwFCSPqouFftnfzWZ62 taZ3F4Id2DFRB1nhJobzKpV4tv5K96k62rrGchJ05yXX1llY/IQMD2JR1gZOPDww2j9NzuTPW0jB 5CLyrhQNc/J6NIdxQi3n7KTMRPu7dmg8Ool46r73htrVeob/n02pKwmYZf1AQiUvwhieSx8+Ti7D RJqnDOgqo6G/zUQBMchUHJyazDuZ/gKTJXcggGb/jXsbYEw64xVwBGXrI6PyWbjQVxDe9nZULzks 0xa7qmgCLuHTdPBSXQqDQbLef4KVc5+Ic6ZbFexmdUr6sUcajgOCO2dsXn+NZ4P1wyIdvX+gL/Gl b9bt1pHzWhqZIL3sCobilr2a//4o6QIm8PxS5c9FdY3J9+zoT/gu7nZGfvlCw4FEHXTAFbnmsu6c tZBk5/IUCXcaXs07JUuUceUafDBuCcgVUN9ksUt0KZLq1gbxbKAbQXS0Z+SBIoncQpvtqRkrabSs 7pf3UV5FxzXU/rKQbPQuXYDruH/1QrZ0/ij0IDZw78WfEbHJQOg6z6P+XPSUjTOi7cIWQF8gXcyD pKkPqE9/X+YWaaXbdtGY7PDIX5Yfq38PbnmGcc5CviAhV4kQbNPBX/Wq5u4k6vwYR9Djw00/zfl8 9Kb+eLQgpeT4RuUhzo+l4jtdTfJ5h382LtmDfrJ6fGTPjp+HdSk/socAbFlc01wB1SDuXapTLQDu j9ZEF4FNZjkyq2DRoGHtG4dzCUtOvPghYBLQJXMvQ3hPz9ToC95aZBtLuJ9ozSlb9tL6tUEdQzBN BA4IiJJpjMZPmr4WRX2nntcopfEmkSByoUm7St+zt2+dzrZk+z/gRZWLGHZf612KFtBQLY8Dq/y3 Wrp+YsaZc8GRnpOqZWk8d34yS7dWs2bfvJj1kJ7oUVQ/jbkXSsy2NanSYo6rps2NpiU2HeD6+uEX SNYNIB3BxZoh6S7ZIqsKzhFXrIMoUgn0T+/pLR4neY0wV1Xhe2dbQRSLuPnwgbSwYcCEbCyh68Pf g1rHLn7nQFGtw/3fKn+X8+6FxDQNdKbesRjWOMY7JqjzDgF3X7M6HRmjyoTv4qJuXgo5BH7/b4kB CswcGr+EjkhRlBTAlR5GSc5KMewaQhWtLyQ9gmu7oeaeWX4zt6LFLMOOpyC8tU7zzR5ZMeOoGKcx q75lYUu6jTIRY4lY6bMZ9KvewoGM3KKuJsarLcDnCtucuRTGJr8/D32x7xJwiPUjRRGWP1+ubUD+ agnGlc3jQ3iORD5DZ97l2N3y+6gtWvo/LBk9YQieMYzFpy68/Ks833C1PEocQEGADGDM1aIx9snK 9QjWdLe2e55+T8SG/6XaP/n9jbAB1ZJmT8xh4K+7PsXqMiesKFa9LsIq6GCzoylucYoauhEdLey5 0GATHieolNHFWq1PS91c6ihLBJ3b99SQykRSZTtoHVzo6mozJh9QJGt1h0tE/ZS8WLu1sR/n39x1 OBDvo+HVVCjaGpDHCYx9KE2wEmZigY2RxNTLxNsOvb+R9tMyQEfbkX86+Bbe0ZmiIQFytgOO3bBt 4tR+Lay+eVuRYzxuXtc2mKcYRxAc18OZlabTNORTDKBYuE6Ra41/ZjOpBV96RV7vc7qJ0YmIwnl6 NeyTohcuAiyHZ45TUqVQ957hcZORPW2tUChdiVcSTpPCpN5r2T0wmooTO+lVG5apTTjk9J2V4vbm NuEkV+AXd23K+HJ5BiCb+G9VAZUnZv785K4cTibPjXS8RnPIuJoWgpZnHlOGwOkkAxq/sDcRW+YU vRzpNE7nKNaDFov0naYYxSGy92RskIYwRxI03epe27MjxEJX/8uJxU13vKRuNk4Pt4qlbTvU5fB0 eE/X1WP57wjkDPQemBl2eIK0TWlz2dXaz5K7M5gFLzCM9XR1Me7a+JNyFOWSM/I+O1ytdizRhR8I M05Ed0UgudW+L4EULIZgq51HKxzvLITDFysFUEbx0Ku8AqjHqJOoCeWtVzZV9/TDZmKf4Kts1n+A 6gC5L9dHBl1Dmx6tCn6Jx0K2gSntBsE2oACXiygoIFQIRXFgR5qorBqt70Hf5wHCpE4UcxzQdg2G oBV082ELO9lo3Oo097dLdcJ/s+Di8iGRJ/KWkkwx3c8R1/RqQV62t1XYcfbDDxZPC7exw5HfMbjY ffj27zRlRTIxp2ez3ov4T2WpcegJYKv6iSDuKFZFuzpE8c9FI4hwdw4wGaEWHDWHyI2WyT8RLRsp +E6QmQn4ELkEGO0SN+xv1TeAbM/TNuJZo/zZrbDNW/2kcl7gg+VzqTNB5dssUm6AS9psIyxEbhaw hqndZeCHWj1e6+9xUWIvk2ltwiaoqxjKhwDSgBSAVCjSU78jDACWHB/5B3wAE+xdHDDde1ySEEIg Ht+czCb8fLk2LP+qgVzsjOd5VzQMMBrHIjIpxA0XsJ6PQGJa6QGU7AN9DKSIqhB0VBKMrcBU+yCq eQ8ewAL0lZ/dokui5WeG2PtNDlanwwFL8MY3QCTR4Lzg6VcwdV6rSALUjxklbX/7ZI3GaGLYml9O JiEDu9LnKLAVGEcqwomkfC8RWoySEMoP8mRpUtqzkrf4wFVrd8tCoX3rLt8d+xk+TF2c0XaJuQYy VKnvZeBz3NPfU1mo55XbjybG79EtCR58FFln1xo8xP0DxIiIuZKJvPHD8VUbd2I3vQfEAYyqEwdt Dc9pqmDr3VZ5QN1ZgqM/U7RAIZOO7NAUF7AElCWfZvbSFwq+kApzUxZnKJQtlz/kzPDwGBQ0ipnZ /jNscC5Qqgo/GYU4Eru7DkTsD9iabX4NRMtMxKCVE7tUdHBv4K5psXB7ZvbEKuxKK6PB5NN4hzTp g6Mf3TDDCI/RvtWp9fctUCaplao6CO0rruCmhhvNRnpVmRFbg8in9iGXJzJ80GuTs2oVrvB9hqkU MCzHMf7b5LhWbPbP/HEKpA1VeRJ17qSYsFiTBwsL4/WPcPzTTAVJ9D97Oc3YSfMq1/wCMLMCFxmZ JbjslhQUvBJXGAulivit7buuV4qrStvkhqVgrB/3MsSETzjGSxHAsJQlr/76UHxHkwySCqx9NFOC ts2BmJjcxpDOip6I2VNm0kwikkSYKVUiizXyNiWlCq2vCaE0cJyH2VcH9HlDYlPBJHLj0j1iINCf J3y+jd3EMoLxDvG/hmXj+Aossz0zpcn8M+hvpOT8RhunS3JGhncwcHI3WXGHOCBob4Pish8RaMqU xf+p1PEOwrHG719zCusEA/CxcQKM2pSWR2I71MWLuMO6BFLCx5ZmkYoqcI60cbD9ONgcyHox7Mat 6ByNEj13tcYUcTNYSoMHKoaNyxLQqd5oD7CEbWIdZAEj2JuC4qJ5t+5rcIaTJN9NOdGh5LZcwO1c JJzh82EFhpzev0GJ1BD1f8ELZjUJr9yStn2D0bYIUAS7yLQzWs+LWv/PlMVvRcTO1ebvHXL/Xc1k iQ+zsZ9o1S0JFy/133xzucDqbu6WT8s7bbWwm1+Usk8OLsfbidOFSLqiRBCgLxIwBHxOBxgAERtT nwzr67NFsaxdXAjGK82KnLp61tdTaI/AmNeIKO8qBxxMeAZCgLEtn2sb8AftncVDyrfAGTFIL8Hx OnjxqvCxkboFXvDGb6y6m7ofs3uQ9QIJQAVbukTTI1QxY2N2skvjm1u3Xbj3VQdT1xwHRWnZp30O kA6BHqn+7byCmvf9ODp49+fo8ikjfMsodLde+jpAaHnvGJ6JV685pv6igALXtpYnXoue+VJRJ0// 0nj6JpLwYw0RFZFSWn27mRoEtefa59GpADNGUbfNDpmQMUKWpmRpBIKydq6LAG250rrkQ4gi5kTP UUM+YVcc3aex5ELzeXwHwlmOUlS6OfU5ucjC3ivsmPD4P4+PiG+3nnvwCUvFanZm8yFSiuzDNilv 1vpB2kagfl6jYYHTpS+KF7GST5c0mzstt9QwFdHJ5oP3wQEkpA+iiQbIgw/C5AzALkU1LvNXitHU qGxfMmvNge+r3LNGQvrsiyxocvfpE7AoRBaLOTJnyjb9cdcLliYfeLU3OY6w1x18oYTNN+qPns4i zmgAxH8G7nnk4KplQVrejbDPdP7VA5onQ0N9fsBZKzwVBAH6hRYZmtp7NgjrMZDEW36MAn/txV1D Xoqquegd8ZvSffgo4kUjY9Ocg/7TnJYSS+ql7qVnHM7j7rfYvGc28uCBLaBMiaSC6g1glvUmSwuU YHgGGyU0o0pJLnBuw+vDkh3CrjHedZD7gz2OaFXghiO+QF/gZFWS7oMeAdZFYpfpwDCp+p+EylBo P6unYIrjL6XK/68BB3BTWA5ET0ZgFdB6h5ZGh9IUYP5GGtcbsiD7SGBRo20niNx9UmCWvi3ywAxD OWwZB/5jZqpSnFDrQeBhKm9TRFlECJhLqfPOvXnS6Z9TDlCo1yuBmxVp40Dtz8A5B0YLSYXPqyjV QtKtLGWgdwDLV3o5vmcIewrlJ8AcQJ4D82IWRqNvBWJiqeEtLAeLsGExFtqvQkV+TxWyTV5/BS9H Tbfq6Bhqk2gX+MbLJiXTtQDGBUuJ9OHgIke0dhXABhzS32h/jvUVSXfuakB27BtDmUxC7ui99QjU eIcq3c2v+18GQBqTIrd319KQP+L1V1C0I+Kb702x3ypERlUQ/Mka5i4wvNoaeYYUgijAqu2s639e AeENSMucvY/AbUc6E0btajIZflQWmYr78uWqC4/xVJriDC9qpcNxR4LvITzQotUAjjJEl8l5eeiI AP4QSw5i72D7sF2v3VyQBR1NWVC1zPJ+rNfLKD+UitA6JdQ2GWCB4kb5Ru29KgJBN14Rd4pxP2ed t2wto9zYY6AW8Tgc7F9trxXZbsoRct0e36eo0ytgAooBtbmlVrXS8Z7RdH3ejUDn5vTf1c/RAatA +AKjTzOK5S4855EIMeR9CIUoMZ5RGAoB5A2TqdfQYF0ezgVxyvOaWk5il1ql4oyHK2DPyJ2x32IC VmADDowa8n+Csejgfsf1w6EM/+BYfWdWtQslfjwLINfugGmA9ocfr8V4lJMbUiPKmzT1AqZoc0B5 BzHLaLN2GFQRdK8i4qMjp/XMPIkvSAvTfeePOXOMvM/5wardNyfKXIgy8W06L6Qg0z9PqrpRAXjR oqpVY63JEBX+M04i5ArQ5cZgD7uFqULxQwQNsY06vyUE+wI15k3iqscVtZ6LKiRH9RmNorKsEB9l u1ArG9f10bsHKfyzIR53prkqQVpNQmNkSdqR4yKZY+wbL6BAxizbcu2auae5pV3I5vDN0oaxSKfY z33zond6qg/0BHJe6IASO8lBTxeDBycioEIQD+DZlN8qA2YhXFOJTGFBWbbsWV10xH6h7Z7kuxkW bZYDcfDPLETnZHUznAtdfEJ8IEK0AkZ+e2fNaNRrxRjbRIeC3IQ/IUXl2Sf++UBdyPhsUD4Y7umG mPS8AHTisBR8N1bt2mW0IOv3/qHoxxemwVR3Iu8HEvHlZuVpBUoSDdCDIivIcXWB8x1ht1X/s7Bo wofbwLRedfDpFlHh0fd6jx3ealaXfpYPwFS+ZdHY+d1ZG1JUIuuBgWxsGx5gBtOObKtILL4IT5IR HkhSbL/RnfqNeSK1jjQ8cvN32yUY7uuEh9SgCAI0+od0Uz/en9knkU5O41esG1GYbNjkYo3x4lyw CDd+EIY34LzWvrWQaagID5YcP9TVeEmg7GHtgqgrj8SiHkCMqmEqHQjcyaHgi0LZKZ7ukmvh6bvE 6YCcED4MlPS7tDMJUb7+RCLo7p++aJogoioQZJkgAfHqCpypzbVEFWutGs4368kGXzMfgk2wGSYO ncz0es+2l8ERF0iVrUOl2QZhxSlaXKIAsxj8X0CfyoZTQObD1Z+LTcAE26dzan2k4WlosMg3zVqP rHlX4ZbRTwXLcw9f9Z32an8ct+RpMtgCmby1uPFAfiABWjZwG6fqoZisGOaLEHn8JliyUDfDJENb q3q2mztEKzQcXcLIgWZ1w4mD5QjwletuDUZeRfeFpHGGwQybiG/Hoqj8bdSX8+Y9jRWgegv4XqCm cwUMDkRAnR6epQHhmp7Xc+Vlq1fPhTta8dZHPV0QU9Or/uH6WrD/6CvTBF8IZ2648NUV8PO8yfSB 51imoCmGXQpov78iMeupZUsoNQMLNXEc8jysvdtl0/PlWj1zZccAFkrtkZPfFhCez1IL6AYG1uBs Y7gplXI27quwOpIFLJz7fJ+Ym6M9wxScszFLJtxQhStXM9PEGf1xpDdvbDOfHIbXkQ3Zg4MTF9bc Ue67P2r5aqlWdLgyp218Xt/SWQZz9LAQahPig1QHjw8uMiWcia8JQ+tONvOpbxrIpjcw0dDykXtK 2P9gryBFFkMr/iV6HuQLJ2A6X4wtXFL/NWxW2XryjgRnaH60TbT79Nk6A/lypAZrClfcYaA5K6Ts LMIAiEB4MR3J2XfTzPzcil8tPsfMo+kFHE+c4zZIJ5fmqa80JEPC2kmnLhXLwP3J14CKRQbo3FEn r+40xO5+GHkDRjJJ0gGLI0DkpjNaq6xGgUccijnQC3E2NhFA/YBWB621WD4tm551gvQ4tvSOnAEn 4NacLNlWO+UwLa0CxXU/eWdWUQdqzCs7tgN7mNKNQ17C0hafJaSDd6Z8MVkaPQbndtZTjxDsqfvP 5qc5GPoi5hstcLk/zrbNEC/+RqXMsZbsXQDT5XM0dJssypC6nfJmsTcCbPFac0AbCBL6F37oQVgB cHlMUl/r8ICHrDkHy+cEj+/u+Md52NIJu2tXTu5jXiZAdkSg6id7/4L9u8tiC6ah5RAo7EK7i3CY lh9N0xHs+tIoIJK59CjTMA+wNDVLB0a4bLPjnhGQUn73Bs0qN3YZkkiI86yKTfeRW7eQHBIHEvXQ 83lINvWVqFv3XbdEuPfDgzzMkRbNp6FnlumrvdBWptmN/fJUKr4SB2CCZzFjiU2MZetml/fRBCt/ UojEJ169BACKtv3V04t+IjPgEMxCVt/TlD3PRqIHyuksghobE0u6ZPRwVfUYzkfGMPK0+jnayzxF 9w6KGPqfEW7OQBXahaSiMo4QIQD54navsL9tAQ421jxMqsUBoafJc+Irj5S9Db+lEMD8p4jLWQiw PVMnhw7Ve2wjkXhbZTMBDvn8EuFNZ/Rcq+i7xrO6R+QtX/ZNLYLw8HdBJnTIVa6n++f1gbJ47lLV B31tBUpVVGwGnBfKGI6NBoDPvyg18HB4cP7x3AI7EHQfgo0Aha8y2EK6KnuBZY8uKq3cAa5B4bqL Rue8kAZBWLr7fVXM5hpCXrCPSFIDsUzsfjLtXOLKMM6a4W6C8JXR25e75oblfd7YaBGIBwurwu2+ QO5Pim4lZjtaexl5xpNTDzxnHSw1dO1DA/CXGFLZNeupVuuW+Hngpjnosykf2CNmGaxCsQecLf15 cUN0g0gQ3FCUcESHhZT98BOlDhIj9yP79a3tCN6R1l9z2n3lz47nIBBhNTinpj40W+lLDgQLyZvd Hs/xQS5lKO50GaVjwCeAbyW4QwiY7kNYiS+q5Jue4k8cAaAGrKmw/4tAQhl2GMYZLEr7v2f3I1VY d0pkQ1sLVzWvTiOJf3EUjEuwyOTqyCLTlTrUXm2nQDSk4shtirNZUlFvGkTyoFv3Kv6RJCj9ld8A th+45qL9iIy2dB+arD62Hh39xDtc8STbd7F+f7+aQXD5hSZi5rpqimzL2mcm6I44U10E3qv14LwE qGpTltbhLrFBm0QZOLRCoR+RGN8uvqnwbAeTDA6pVgVNlPeWJ/I17EYqicS6/FaTWcy3Y5USpHRN OvLfkVc6IgMBKCSpNh3XWw8UQ2CyLZ80R+sPm+oWXuKOTG0oHpnH4BN8X3zq8nrAZPZQ4y+q08P+ 4a1eT4WRWOXAHBFUnoFTUGhRh5HFo+6VFCtB8W2lK32diuwk7G8kMqzHkT0+HAVBiSQwRJffPuPe 38Fu4e58MWUhr1ubGEc046P+QPm1W1jptbSJ4OrPcObKbFGoypCuCBXVTVP5iGZ3aaxWpv2j3949 zyZ2LPNWr0E8titiPyJP0lvSuf/A4h2BUV2ArQdAT435AZxEivZqRDlRaoU8MG4eKArt/nwPq4Bp 3GrRTZ5zT5nsyxkLma+JJcnKqwAgItI3YIsOaWH2WSYSWukH+hX1G8tOVEmzHP4mSqcBMpwlgeSk tIwz6HOorMaJm5rkB1Au+5q+ZIuX0buOPYGTxWwOguxQT5XaFzeawJ6nbVgOGlk/6ZLZV2m1yB0t hVqAdHgxR98luuFx4BRMJQEpV/i3TldSIeo2eDn1wtbbNkRbyxCrI51NaMEe1nCLrQKE6o3qoDax O4ilJR0CU1UwjZ3i3fytYnl6angN93Mzji/ODLMQV2bl+r/AEg5y/KwdQrUROEg0XIl1Bje7xKJE 1tTChw/h+HU/mu22Xwy3/JVe0it5BotWmBSjtWDgLCL7e+7raUeDW3SijRQvuW88pt1yaUcW9k/X lAMvTEIdaHZpW76Ol3ejiXLjFZbhuHJY8ucG3zGTa9rZmEMEt916vq/kOWzPHSgHKdszi1aLYkW8 eLREA/CFmR5WVephqgK2umsjKl3bJK8StN7xyfmovPNI2af0T2c20/n8FBktDswvhVGKBsyPgNtL 182wKCi20/LkHvdrMtCEGjzvQDGsGyxpgM2ErtObg83+WDqr35hUIRgLFbgM+Ovbngh2nc5pxGk6 rW1FyZ9uhUSpeAQ7nP7UySremBKdip4QwoVBOk9HdIXpF19SByJiAOLPI2j2ppCx/+qLYYSuhNV7 wx/9aCJqZnZ+2aHiyoIAqI5oQ9vEuKx6Pyo4LppavHqaaaXs7YyGvsDQf87rVHOg78qlKBCt2SJb 0Bd0hHz0iheouQ9JgEk71Fu5UYMSi9E9t6HtOOVkku2ZiTffXP5fXiHrJWz5SbKyxGUPU4gbiRM7 QfTuBVt3SxRb8brqotakmLMs7D+JdYIVhpt9SViYP7Dy1i2wbYs80S8Isg8Evb7lVWYNDIzVdk1I xn4eVcbSQo3j+KJ3G5fyM65SZE+huEeKyR8Mz1u1hoX+XLet4uJH215UI2c7SPYNC/vkThC5DZOQ kzoR0jxfEyso8iy0Wn7okJTF0zXdAUEoTGS3ByqaMKxd/39cajvh6+L5sRL3eDZjjyVAaK2bpOj/ AlMlOSs5bxs46rZAjDDpVWFBPuKz0+UmDrk/+9RKSkq5ORur6VtB92LNSBRMiHNnsDtYHBanzZQ+ LpFX2YDSu0VL/fn+CVq81uaYcB9jIChNqmH86s8COKUwnXMfdmRDIKpGf5CeM7/P16ZHZlOf4tCm r4qBnJq4Ugx45DLEn5Z45Gl8/vIwRNGICXV5YnYDzXu1s5iuTpmDbY4DJchCICorwr+zd75kVfUy v96aENsGmgHCe1zgqBo2hsom93LxK5d0QU5lQ2AoxKjVnLeqRt8XUO7HWJO5lJg3u5wvlD6NYn8k mTwQtos8JCRwX2lY9MrbNuOdDeXU/YeFmQNfg1u+tUb7J0h8v7m33ZIknv21haDALOZUcuxQNb0Z VZxo/GFUIsmJ3sQyOAbkiROAS2KhweLgFFTwzurA/pr/9Z0udxVFqD/Yzqbo+CAKcHPdPJB1ihFu IPS76omAFi1OMA1DeDt1MEGyo8zFOJrqx0kvg2tu2OML0bdqu96OT1OSojDZEJQzuqrDyUW3INO1 hhj7mqLH8njjDm7dYePJUihFv77Hj8woq9Arw/OHrIFhh1V1hU9oqqSfWXVJTMPKvYc53Q/T08Js 9dBQ6L/3Pce3AWLurK1Eq57IKtc77zTN9jxtOxKo8Qwy70xQW7GI7lmVt6yzSOIKFSYVAPaxe6Cc 9a/dwNPFmJ5ufvQhpJvZU1nOJTJjhBuc/7stuCZOCuCIqMnI8gSQBPLk8nlnSgbhswuo7XawHceg IwYdXhDHBHcpauksoW2bJIZGGAOqToBNTD/20xop7eaWdFWJZr+g/mBNlOOExF2wXMf8fcbqqebw bnX08gRClWYTARyNntpWI2HPHWyvFZVGpuFV/XH3IJ9kj2ImgKtb/Q0U6qdvUPCmS87UZKElADlO NDPidnYaCef2YF2PsXBWu03xFJSBq8jsFzZfyv/rrOBy54/MZPJzodjHfvrv8Hsfx3BBGoPRWf/x vAxBozXdYhglo1kEQ/K6z085Y0Oo49p/jbvSltv5fIkq76VTQ1eRNu6cAGSm/+4HRwBK/5/zGmoo yNTVzedkq7ycka6p+vw5vQSB5oaQRFxsyDJ4GD+0K8iN6Z9MZ3TjXLdBk3owmM8dluSDF+R7Q3Dp S6+l7UucrnXy0mWkNFGVlfWNHIdzEabwWiSllb07j0xfv+zQxiyfkKcLAh8hW/HQatb9bRsUyKj9 oTEIp+qTz4OehYZePyHyyDaayXam/hAH8HJDkwgce0+ibVQ2TFN1txoccwYHKdluz4FBwIParnMi zSU83mwbFt8FxHsWYOh1KbPeTJjIlHzy2rcCM6Ze3gUiyeeBJwLjZI/YGtvvTgpZtMlmvj/KHdGY RY8nUpDCsskQHkyz4Y5c5io6VJeJTWFHK89STf1UddZUEExbmTmYApOG9p1FZSvL4ldg8lxkUCXq SFsAIvXgyMgIjtMvXE+kmhaPYtpdppWpwbmxDMtOHod4l2iKIc38/Yqcq0/WHdBhewP7g131Tf4e pP15ghLs6Kg4Yrt2hThxzXMBF4e5fSMOl9SwcvYhiMcGUrkWQd5JjPdO+PRonCIG69qdlNGHq+Q2 zVjOgG9pg6BE+hbybiHBMcyGPa4h7/27ZP7f5C9yqGm+uSz+v9KDggcvX7bpyR3f/hgEzq1sJ0dA F4kVx5Xsiout0G40XB96U3vgFKFyxtITGap2/6p2ftQdUxrW4T1ikG0WtZ907TLCfExnGv8LJIUs vSszs/UDeSL9sLvwlqP2eA34KBV0owZlvRoyGDoIVrCySBUO+1/U4E7AxXR+bt3La/gRs6wyoRhC 016nMozRLfTu9viejdDYLQ+OS3XJHqa9RHdZfiE0Rx6gZ6YDE1Anb4MZxyDkb348OE2ooJVoplOM QKl7LCpAnpLVewpUcBIiNopOwTJUeaLKMyl/NGbyYErwsqnBCdGCgAbL83aHoTesGBNwKO2GO0kS Q56p1yw7JzthxAzb3gpOCPVCBNXVPpiMtpYQwjT1F0OCAEIBtxE1Vrk0/Tib0jLDHbSS2TK9jHu+ wskCefuhWvuSi/PTCFSbKcDFdMUZcIPtkbes41U65og05v4dYaRM3Kl+6S2JxQvqsZPGqSdiIjo1 wlHdKQnCFgOtpnBOkPYuSzbMH1zQsw/CkrQAH5waZjWeZml+4WlQXdjasCkKcKsSzX7Rdz5GQ0CS ztXmfDPZq3zK0QVzUxKuQx9MWx3dkg9tjTGKSJN+HcluXnbIffGN08vAQ8P20KfqNhuiQ5brB0OP 0oRYVVFG7ETFr4aDm/LKm+Szm0ZJtcNcmrVpaAQYn2r8kt/q3qetivI+ZDYL1A/PmD9MpcVox9bd ndY77ioWeBiMXPJD97tkAEfTLrHsuwD1DKs/1FzOymI7ibc5I/8qsWMR1/dAgT7fKI8rjBt3yRAa IgW3qcvuwn+gj+KpiZBfupsRMUJFsFM10YZX2yLEF7viEam617eD9puE9KQBDLso1QUm/QGKgGEa giTAYUVdrkiQyqa/MxOLFR9pVA1B7TmPzPkmufLPWUCC5ALSvdurxtVmrhZ9UzXXtVzjyH6Xb/PG bKFK7dNKREv+drr6OuN1tPBxnCw5M/yAjTKI9YFu4yfUtDBG8CollAvMcM0UAvR8zgXbCcTRGERc eycRzS0f5dwGXyrccTJCkPDZpun+X1waPWN8jjznnr6RXiExoq/pVw9h2cCafXhBMg4gKoWp/2QP 21jJhUEtPd9JBKjvBSdciJV5n5bJmwq+zugXqr7pFgKB4l7IKYn8yq1lIOIYKjcBls+ILNIkoTim Qduo/HoRQo1Jl3BtlCA8nzAa9przyyOGJBUAUAC0dY3cCWYwWEra9apygTP7ClhaHrDIqrm2QyPL FFqTuS4xne1u6MRVGlT3hqrZS0y+6J8WOf0360WQJZoyagS59rK2lhBf6lFWfFqJti9MeF882vLy ySVm7M6q0Hd2o/4WA1leUREfzKBMZeLJt5HnJUME5VXKjlKcuHTQ8cZXcR9WspQpyA5Yi/LBQida baiPAQL/lepuP0EgYsJHoyy7wmF246nS4xOpwIbIBg7VntoL02UDdEGhtPzFZBON3b+WImUmLgE4 05wOk10zK4oe+9QugF2jaydUfJz93ruFGiG0K2FKD5nH97F5ctRTIQ+4ndFT6OPX870g7MQtwgvG 4DruL1Ya1iMGA2FqY0PdvmarSGeqGuoEbl/ztYrlta0sNsu6ZSzqXYOb5MWGUbSe1PjQBiYFrY1K h4FAa9ymFbQA+KtyJ82Rbj94jDKDrnw6KwwcYz87apyZhfGEf8zjO6TANn+tGHngQmmXUxqjjbRj T9SSxnZQbFOmxyvbdl8T9wF0MJeLEmhVgUH6akedEUAuuUXggV7/RwalwHQYRj9E/TQR81ti/VLa i6wiiAv4FfO/5BUKytfpsLvsvWdFTBwZ0DO+7nTVDu1o3cpvXjjqRLTambzr3yXQYjPzk12wSacF d0+0Lk71V8j+WU0XMQOMaJNTBD2my3FGggjn/PoRx/IpdDNHyS3bGEZU/4NEMiC+ef3Bw9uXWtK4 iWyb4uuoAO9jh0d+vq5HDSOKCCUH2p2Ce1Uw/xMW714ahXBLwiBFlG/cZKV9iT+aU2Gl7A4f/RA+ qmdRMvXq1HYbEbSNoK/U81ws4Fh2wqGFkUAtzdqbpFT1x9+6lIOQ5GjusTCyfE7+r6xwnvOUcECf 2zOFp/aaCvNjwEqjuks4M5L2lZblsd0SlQcdYx8WZ1o/d0ugfrlJr9zXb3HpKZNhsBGcBcCajyPx DtjbmdRi0IhjHSLFgAf6X71Wwqpy7CKCekND/p98KuJkI/qvrsbgs+zeB/rz45TjPaXFsbqgce0l Y9fDa+40l4OVd7OZK8IBlDlVV+VYf6xeHD0o6f8b8Kdl/CKmWhX/CgvVMlK8j2AUcf9PkGJ4czak fr6NVBNg88BYMHb8XKXjSWuH1qO4TdP3SwMWDRtgecAXROEm/G/6DwcT9wX009fFczUnCjUauyGJ J0BLED/KZL5XFIjsU+I8lS6Bb2lmcZMhD+PevTwmLoDl646fu3rUOxwUlKqpCKnITZsKjDlym8hS 7PMM0KDMqU9RMsKPXa1vK4dTDWprZ2VD4OW8LS4WwzkfwaIokH4/gzX3HIPjsPtpJvI1NO2NRZz4 cNuuW+9sx03Ovd38ddH62Q9ENY7GyqEWTNSAr7vtqiFSMp7UhKRQa0iNKAECEcOEwLxnRdFCEFNO vxDP1hF2JctwvQSYMhJOiti/xLO4OrkoUEG66EvV/nQxgZs9+cj/r32M1STQLyrBG1IOTHnRWNc6 4/tibhQwEgSxuVE/z7VAqWbDqvP3wEYQ2lqPWLuemPU9BdwtzTdSKrZwOtXDRfnNg1jjaiiFxpDo Y7MY7ZBj9namPODM+gDxjVaF6Xk7SPpuV/y/9fcjElzO8miEgzt+z/EdWaHGM7RChYLqWpNSnwQL FGjUS1OAQ7YkzXzeyY0TrOpn4bydYwUHfq/i/zakyEhIqn/TcuTYf+BOMEiDntcitjskLumJqIeq SGOWdbzYMhliUiBMpeingG9JaKyRb3j1ySvFcN4dOTVidmVdxFk9PJhYUuX0g7RJWz8ECIiU9LC3 /TSQdg28KcPUdybK1npRsdYYd2bV6MTTXTz4WqICZF/MuPPXfp/kZS9mAh1PHF12xnyCvguBplag vq2FXVEBJ4ChbhdUwLP5PE/oSF/6dzk2um7WaUBlyeV2Afe9NAVRnYHr2znQnm9Ja++1djOyPO9Z qwFxGdINJGEqA0AxQgrH0ASvNaLEuN2Tu7akyH0A1HOJGscoZtHPKcmbalxdkFjAL07c+ROG08Ci gCp4caUU00axAnvzw9/MugwGqXSrptbLU26l/rwpx2jYVkRSf6fpMgcj0286IX+RBfLz+Si4BrKY 945A82XM4HnkuHmbhxNSIuNHPtrS75u+o8p6RPUwQWX7h7qSFh4VQjcTOSjyvLnF6BTf95R5OYVV o95mtHZhuRppDI0nslXZjVTT0Xoquh3pu112eEHmQ8g8+K4vNprcpKbWk6M8PcjKps4PGFBqNFtr hqsdTjHYqqYKWDtlMlQxxmGpfVEFiPtlsT3rOCgBrGyfY+cT/MkOqtb0vNsREATtt+wl2CCu84fP qAQhx941Tmv5D7avYwXXEXAQa7Ew2Q8T2+pCUAxvyESqxpZOui91/v5q/UQLI3ktf7xgl2zL/Ui8 QwKWXW+WS6M8B1Y8aH08YCP9PAOwzVhv/Bnr+6/0mkSFwlSObtIPlGr3Y+biaMcy/K/Picxggg8O YmUdFjagU9YP4hOapBAV0t/hR12Sh4qPz/RUEFwumRD9vvdXhV2azT9Z2qrfzBZb0g7iaQm+D3Zr gR8B5Pytp6a8p+674oN6RCon3/rFqMHJwPPy0fadUI2icH9X0ai2xjUPL4A02/HTvrmzzZtxLftW wKXWz5c7LtE4TlSkrtfgIYzp/x9cg/kVe1PRfiYqeKC/3WKv0vFNyFhca+QNsGPg7w8WM+NHQMNc YqUmZ/6m+Rb0SWjoUTv29KujbUe7dt7D71UEr/4v9ABRU2UM4me2kUfpPhrM1JGFiNyYeB9Bbl3K JOHfaNCfopazsMf4eNwvJYKOrGnE3F8ckmkUuQD+01gDtzC9G7EziyJn0d0B9iIRj6KKEj4kOJKE K14dAhy+ypbFZ/RxvlvqGwtC1+4F/m+K1HN12mRrzNl8lPJbugdGUGXwlRRd7dXqIKZ6ZUQSa6wq YEgXJvnju52x33CUzQz2bbLUSrpeNrupXHNuDx3UFQIi3NKNTdtuCncEZ7AqD+a01RiONGHT2eON ta4DPsj65Z7vh7qjV2S7169N4mJaEHmhQAcsrBe39FWyGWrC0Tx7h1bs/Of/RhHVk5uPT1Y0/clY wm++oZynpd4sosExxw7c5K1tuvMiM+4B4CA9WBYOGh2gsC8wxY+0VlJ56VZlawoIY+53Npv9EjY0 HQ+4uykWE8YWMOstDExXMZUPjGClwIYxaoRmImVSuPuFFIETMaJ7Sf1O5XlwvFhk6QplxKpSaqYW p1BdWunbqVL/XDM5T4pLcPW/HQHd8/C2noFeqm+OoNoik3/b4x4nKv8o3FijE1FSxZYoDN+fEl6M Kpavq8/0rCXYPDUmAGserNvvysvrPXjcsnZDRbDwssHziWDlkUaLk66NVeuGL5pHoteSVZ4DuL23 YujZAARedarX/38gc8l1SpHMtR6Ajs5lna+nJWpEnhw4PYzoGL4VPPuy5TRdWKPGH34iTyO9gmig CLHUxzb6TIdkhPBm8AwVX7dQ61Nlawptxa4At+5XlgyoMAcgGiPP2jEdLDyZfHNZ70dNJWIl8Au5 QJGY/8OpiVkCmxYBHBAC/Bg+SNEASX2H2n8v5fTRyXfIRoqb6IMkfENNl4PNPj4T/jZdwjJIsjeR WObSagqZ0Z8PUhDvlbEnCTjkR09nS76QmT0/scPN7Q3Ia+R/9x9WUGC2nC0fkf4fDKPVEjgpH4SV cuFk1jWoq1exIyY7QIq5VAy2wvIp1uhGGeKde73782B624lTGhWCUX7G4nTV9DqZ06PIUY1CRCZW WsvzFIhJvdQPrz+NdVpuK/TNsQL4gDqHmeVwrtZAjIdubGXs35tP0tyamteH2MlFLU/m2XGeaHiH UobuIwaOSmXJAK8aNvuC/F4ztYRulpQNbWI1gqisg0iPMZ4nL8db7zmJt8cnI/KP31gEtjBrT4Y6 Gj5Vqg9RtbH9kfQEYOfbEZ4tyFV1YKeqdQR1AL4RiKlqk+fonQiM7PJYtBjp6qBosti1Aq5qsgVB HsEqjUbd01W22TUbU6wVFPid0Iw+OAHao3qpAS6AuDA49QaVhU7Bb16yunp79VEI3JSU+0a0iIAX lo67gTTGvfv/2AEUG8S+qYgW/EBY1UOs4Fh/jwP4aNeeXg9+Of2UBahOGmyA94uAcqxhIvjx2U8j Yve3y2DTqpl+gPIMQm2KfILj+7+oqyM7jgZGxzU02DkOZvrWIaBC0Ml8tsJvQwhVW+O66gEVeA6+ 9OQExcYgbt/IIfvGk84f8vnmMFVv04ynThdtpYWuXgWlfY+QDz31BoixURk2jkTdnHMYaX1RdW2m rH0KjPJCBc9vs5Erqch7UA/Hr67p8lTGjMPFoS3mGGB9PPJqh19hnOWxDqesPBKG+erzwLnDEyN1 JM/Fsl5DCavDNo0gYPDA7f2B/mBCcrStXW0hWM8HQdDI4tMZLe6lqjNtedZzVBCie63hzQV5wK68 M5wt8TNnzvLcAP9pyTAIX3ECy3fDKszwfM50v7Xu2+zOBqiQZingL/KxhKpcWf0BgmBHHhmfGe8H vqsZkw1hnSrw4zKUk0QG7yIyD9ujqO/kJovk3+E3vt70+e7wDv9rxdQCzjmsSIS+ge6PETliV5qy ECgMpqgeV2ph69lyZnBpKGqLP6LBVLlrZpZSFIBmclciNiCPMHJz8q8C9PGbXW7+dYwPewBz6MlJ UDap/5Xb4hXe4EBXDoSCkn0eBZ49Ux+4+R2BrW8epLpruHDe4BQCom3mUcKROi5Pi7lrkmUDClkS I+475DFf8sQgkd7dEuJesyZchaU9l5xG1Ov6m19Yjbb5/TIE1C8MFS4kyB3E+BTsBovbmR1k7b+v TPmkuTY/zXsHs+oHXk07EvLrFkkAlhi2SOkGelP1NXqVIsAPlMwe3kgi4i5DpUcqCmgzuuod8Tmp migNk++5LQ9+pMwNR0lulUl9+TCh8/aUNBCeaggK4h3lI2RPICip2fkcpJ3UkoJ2lJt99Tc1Bn3A ZbyGosf/hCFIQAJiYYvxq9HxknC+HtNFEjfV2Dygz115aYebxvX08dCVcaMDT6372PswOppAyeuZ XfVsUfWiMAjaVE6uC/uHXMw3nlU3zpkxq5qckS+Mz13Udpmnu4R7qX9N5IMUcixrQyyA67zQaP2p fso1+Vyo9vio3naPCseMsUqDeiFhx8DYsWk/Ks4rSu+V79u/j3yJIVtC3pQdGXiR8FvlEaJ4IUSC WJue5OOAkT2TgVNKJkDJEXJNHJhe6nEFZpF1J6nqzhChSNv5kpbj1V5uAzTRtfWEWcU3yIBYqeGP /ss+2lAF0HxFfVPQRJJNtQeRwXjlVx684xpLYlwSUSfjvoY89O1z9xaXW6g0pnXBVP5sgNz90n9O 3DI9By9siJEoKo3ZAlV6wH9UI2m0BgPlvLwvowTDd9uZXcQmwKm763kMRWi6iwA4NcoxQBPrQWGu UHYeMOYkhWoDL1aSUTI4NbIbSrRFBAifbDeFMTa8O0fvq2kQ/3drWCg44dA/B6Y5JRb3H2qUmT49 2lDvyd4vv4YHQnNjaWjQ4aZN+F+fKJaDLJBUaMUHYrtWi1cN4+iZ6PAx+mCDnsptY3pvmwU1c+qM XLjXPTCpbDWz1nvPy0efelwRQxkztPvbY/Mnxlkg0Ls4jmuwpkaxAs6a8C4yX28kRWkIW6R1Dow6 QGSp8ZANMoKscgzeRY9IRlMvTpMKHmHtGwYz8fzk5BQqBV6r+Rj3WQwzoCJj6m9cqdSLzxT+gBfZ yxQ/HcbBgtHKVItLFgmlPIAoLuc/VCxk7BOQMvQRUCbcHkqLXS0bH6I5LrVbYQM6cusNTCivTEA8 1MoVRoVVmsCt7iSdFAA89QXIRQ7qdllzDL3X6DIA1tann/uDlcVioigHF3kyKlKMrS8PCaOkiFM9 THrJFlqS7ipZcXZS5usyAXUv9RPDPjqCprSXQK0bRa7Blogfw/0/rNUEmx95ZQlEuc5xsJi4AsOI 0W3Xz0y42T0bMGwkmilohfRvsboVuCNcR26NXbc/E4iF0zOVlbH+GJgx+ki70Mya/fUvxh7VDUKs VrJeiGoUJx4yPrTeuv0iI7UzY30PZLklPiyFBL1903dwNrRbcPuxJU4s+gp5e21YxVEMrl6bcgdP njqJASYZjIEKNeSoVwBSY4XBu018Sy1KdhwXfYS+Ct0lSBk56FZ1J36mDHfUqowEmAeGX/FNgTrN 8ZfdMhpoIBLDKEZzFN0M8GNFTaVE8fyPMassHmRPyl+HuE/hLHbHuGqK7GKIyDaEesnfdWR2LjGb OGfpA+vndwgl2pPW4vs/DnlcEVEGC2194MdvL8e2N47TVAioJA0u7ODTm3DmokHK7jaZTlWW0ooz WQn9v/TCrtV0YGYWYnXJHEhWfddraQIN2/E8KtflORlbPLOp3n/2qZ76N1S6hZlbqHb5XvxIq4EF 4RcxBqcZKvHdDRch0jhUrx1iH5QByrFYcpgtc8o3PfQgSoDS4kQxh9c6r7EZVFK1gxFc6ma2BqUS 5GRMSNtQk3wjpmJHqucQaoCewvupm5ItvcOcaZNgFIsrQuNUSRVm5gSL/uQEcV8BrQJIONdTRSnS u9hIs8b5lAr0t67a/JDsKMAwer/NM4ALV6jsRyz+Pf4zgUz7bZtYWWlKN8y5Pg8A235Fegw/dM/M VoMATeIqmitl5mby5sSjehMP5vnYuiFQAlrKDl5HPyW7xLSVKY26RIB7G9wvryTPCu19borjgMVe SM3yR+iYHL+bIMUM/2CnqKuS5h5j15E6uLsPE1TMSDnYSvDwCnGIl/HciEimU5GAr8DRJ3D5eJf6 V4n3V/++NAXVfAkERcOhy9/x0+D1qwQMcfo4H3/5o54zrdGqB5JqCO0FIdSM44saCYTwyNDX+E0x rlKLyr5v1wYaZnDIl6b/xX+jUiaLsGoqZrAJOuIP1glBGcRf5r0y9HqiTu3g5FYyV/L8EdP+nPwW 3j0a7zi7ou5uKPrfjg/mLPlJEXnaQQKcq1Z0FoR7SNLyBm5X5NlIfSDd01NC6LKfrXznXspV8/6j AJ62963tA+LRp9jd2CBQei1y8axxRJXck5XrHnGYGl/3cQK5icLZI6aNugedJkWl/QgDMM/9ChKB 7VHUIIAEJNVOFqO6vBSC8JUGQkogI7N7Nfum9VMSvn5GJH0vTFQAJIwHlGPiiY834O9lNx/LAM2Z 5TrUovfxVguCcKIH3Mzp15J4rTLEtKJIKWkRoTvXPtvZ9fQcB7VhTpvSZCH0PNSqe/3ytqG0jEd7 95hXDzngyGzk31A180FK5SG08/oWgODSVEcQ/WGWENuBFdkWVeYVo2HmlkN792jCOvsrGoroq5is GkzXDfR7y18W8hrTdG90FCU0lScY9Kv5YMWiSpWqnJR4TqHPeYZKdxhQbkHiXfxWrKnLmw4nS+5k WFVV1Pz58xSaEq+3b5uHNbN9E803JXlfre43NIKTaLP1dDxNwVgz6r1ewI5IhQXDKvM4wQ7xZrFf doG9D3YPb9jLrpcqR1deQyttzffxT/KyQDBrWdS22QDXQD6BYuo2PJTZx1T/J2vzha7LgTaJMtrP cLpiMeYqHEGvCP2plzF2DJqR5ugcyPUQ9JeUUwq2ma8nme4FqBfO20euwF+EKjt3WhooHPHSQ4+0 CkBHphrFR+rU6DqYzADsGNOPp27IWykWnzWkRoqMu1hEfEYN9Cw/9ezUGCjGNbUE7daIHgVtn+kr ggDfUdpSNUR8GVWYQ6UwII6gG03tnrGAqliu8qsGJHGorXMiyf6Bjqb0U1KDrcYBPUllrHBDSShq bvxeUhMcrPjH09ph6hyUzc6tpajs4KqW8gkqYozXNIct7GSH246bAFc/BxGIm/kmAtsRl3GiMmAo cwZHoV3VuW+SjApOzdZK/A++prwPgf+RcFdAZoaD2gsXfFz8JXzAUyWzl+/ZhHYzzdKozLnukSHQ yJhkt2Z8RnMhEJQ8bQ34gJ9040R0dGAUIA8I4kSh2Cq7xcE9uRdV4md80b70+H0oTWdKjbEijCfp 3VIRljPKhCbI2lO/byalwacLYbQORibPFHh6Gan2WHIxOWHstRPxGKPvGC3X+oVMdN6aJjZpVzZz 8rARvaUf6RkyTkG0OclMq6eTLH1UZ2xYsKHrAK3oUrU9YNLRSNvkpSrdnxK3Al5+EI2mHLrVyWE+ WdVE1v1rvm+cBPunCHuD0/ai/7SSoGDq7iLY+Gy3uL7nvHLHMVwclScng97o7Mb5+5u78J8wjgHz Sorh0NNGMJZDeUmORomx3Q7ZCTb+tja3V3zX7eLHAU8gFjLaaBkQu3le2xEjjo2IQF/tEjKSmz6G TtK0M5o/djAHyScCIQ3Mrn9kQe5KA2lZOjJdWSDElSjpLzYZVM+HWncNukpeJBp+8qNsaG5PHob3 GHmfFfCp/UUh8rVX8cVyURqZLYfSM9LKsVLdTKDkr130qtbUTqxDu1Vt2q4dy+7Q7KyCoEw7BH07 y1SIrdk/ibQrapoJLelhd488WJ+lE9Fvwg0ROh6R6WYTu5/wDQQccrkMsZ3ftEz/+UqnEeklafWb 9lf8vpctUMApOQxTUoaCxzBtQLHEyVs+SbcZQysmAUlktAhOLuL4q4KDdTOJSYYbuVviaxx/U4+v 2ghNEUm7bEuMCykX2Kk+0iCHMNU5GSd19U/ceknbNtvsHFo5xOKDTa16BrLEOmptYkNYg2xTjP4t miPO3x12M5W3/+i/+/kOqgKWJgqUYvzA8HDzopkSXeMIbSIU4E4BPBGZBgzSTGKfx2ElCt4NQwrv 6CDiPsXrg7td5iQ75NhyGc/ojPw/FCg9iHkM2oLm6Q9LMM+e09xtim5WrvgPQEyg61VapkQUPkSZ JEUtQH6FWSlPPKYMPP5/mfRexige7ZhfdHagafCCrz4w/RXCPP6DlxNlZZNaY4K9Et1/hl3NWMpP huElzMFSDn4ShQLgoWK5LHu/DmoFGoY4G0mRUuBhoN8o7s7DNY5/Wjoqpfe3dU7qCdfrhB/oGLYM xwmnDf1+xPRsq3BMk0FtUeR8db4lb36fDO9HV4FkYGQieM5vm8tdY4tvwMVv9uuJfMiEPHJRBBb8 7+lIkt+db6Gu72iBiI14Vj2L+87pDDw9KeG41u4tWggqlZlyyctkQjsdefp5UYUkfAvnCZGS1jq9 jntpv9+WFmxkwLtUIxgjf8e+zEe8Nhc1jOumkSdoFpVv/qcUpvjyX9AToikjrgVYjWUNvV5aoT2j 7v4JgMgD4jFz3m2BLHtaHQOgTie7XqCL7KppftqMLVZsITXg3bK6Z+fbXufKuptWfbXdI7L0kaRR yVWeEgjVX4H1cVNoAukcnWHmLz25O0zSp1ZZUZs1pkFW4p1XOG95lclzq8XxFP991PlEyOXmFqYq oqIk24hKiCEReeA7gPcvBM1/07EtAIct3UgkoMKtf41mTCC9mJPkDI+auS7cDMf8Cz/CUmlzuy1x qB3b5twrzJOnjNW4rDFoNlhoInwP4JZJ4almR9iZy45DGUWOVJXinIM+0ngIId4s2ezlE7gwYGQy HfrmfPnB9yjAuzEKafue6HdkrEqAt3I+9WvLx77hydsDRJxDUc/Z9Y1VFIzP1Z03174Jfyz0+8Hc kB4ziyk+0w0Tiwx/a+L279ERBphXmi0tkJj5bsV670A3670iy9bSht3WSow23E9EHlTEAqDbBJ/t Pd80ZXVzIoRvG4HesAeSZEhg1WgDnHPHBax9sgNs3KW3GjgSrtLeTxpNqjM70JgCYzMtY0Yf+N+O XIns/ZFi5DBJBbvzpPgksoEX3Nxw/BRkhI23yDMp6J4X1EnAOd65eLvIB6sSVX30cNwi/mntt1ie hc5DR1KmX2LAtEa930XKI5rh4q8ajdP9/jG7xxnADfGqVWURaNEOFwe/3FmRZGYGfoJ54jk3CyR4 UsvZ/fGZdDIISLEhyZrmtwNLESJZoaNpx7LFGfBeGMENnZZAVlNvyWqUPuz75Tkcjtw3IbKZPvwt cfXa4j/XMUpQsvpHIof+W7KvTwz6ub3pZ1jkfq579CkoTujSVMI31/DMk8in2ddbDztEXuqOh2OS 7+klSssRiOD0rCaLhP2A6+/Fl5q3ueTOlgkddm1KsBiutjn1dtxVnaAWUUY2c8hhiC++BXP3p0kv x4LKGnlWfZF/i6GUbdfN865vxNxtG+aHhhbzuZ60QyL9Vk+G2+l+RgVw2nkRWlGc3mEfrDrZS2+Y 2cNhqbyuFx7mAHufMdoOdZVAQhMsvLR7Az3zHAjLMPzXYqslffUD+782hOtgF8ihEsX6n2FJJxgf oximGJ1Ljx866lnYAXOUifFPgLgKdkEs/uN8aQe/2nCkQYIfOenmq4ttXHkeX1a73loI/2qPB9aK D2JpN1TPqwfClJUjd2qfjub+YnE3yGdAJiha4sFxXg2eJxTXfH5RbN9JdBozJUWkRkZJiAukl1/S 9YKJWQi8ctRu/XUbt0SfrgmCh9mWl0XiI4l+m6pdJibWagK7l8g9hK4D3A7XJdyTGDeBR8KTMCbk oDOlsAbtIZpI7sySYX5f6I3hhcpqKji7WlczxoS0Z0Z63YuOiqq+c9WfqRqRAu1iGaZ5cRndQMWi YeutHd4GeoA79ij1aJfMUYqRSUYj3PnYORRpRP9k3rU21MSMWYJgVIkzrYozVgKC+Bk0gyvkfc79 Hd0FeC1qmOxz5dlPa8j5GySF9QhcwKdipCoazfE3rts/xM0oII0oUpOC83hEckrLyUaUL0A1Gk0N OKOtKgPFyKNszRS5v+/WfCFJP6ZnX7uJkKD4NcQC2Pho4m6XBvUbcx0KZMh2kE+6kgJmqBno+S7H IIMI/6NCGIgulKG+UJm/S1rXugUoZsB6DtJMJK0TjfI22tFQbBFCRbP9MoKggCSwCxzMNB0cx01d PUuVq5WaF8fxpeiCch+LC6iqaarToCU+o51WJbDEa4E1ndW60YCIgtcFpFZMk4ioNm5K4TjFBk0t fpFM08UFY1FagB0gf8YryXEWKIOHhtVb8NWUd1VjXoVDrE5ayh3uT8wyBtvCErClnsa0taPx+XN6 eCvwM8ly9KS/iMmquYkX+0c9YwzwLqagVqGOYYgI9ljOoKxhvwJ43sAmi4t8v8nanaVV+XbxexEG qsg8c83rxOCRBSLfsgVPiH1DOQJTqjJD5fZCqnzG3J7u0QxpBXgBxmqkzj4YD48AptUn8vtsGiKU E+6RfiPyM5gULK7JA5DsWX8KoUrJJr6aOw1lwEk7tzcBz7utaZgi0od6L9Zp7fiv4cu/qBV4bpnW //F1VjQEP3jZv/wZ1bYyKsV42skzA4jmsGqHDBnDWYRWXv8SvoKd2FmW2UVkROUC/FpdIVP3NNYb MODSBdhf6dVfylsMEQDdh11T7mM5C/9+RbmZ7Vz5a8mhXw80YJevaLSQK4usLT6VlDS7tTqiLcyv FQo1PPtElGk2XNlpXqYeTqF/NLIcXlkx7FqiCF//qcWI6rIIUJLmS+FOaY2ucQ/OaeRZFKqop2G+ okm5XX6UfjnifxFVGCTqwScKEGCymme3qdX2yp2sXDU93UTn0EC6BdEUFs8jJ625kt1tzyYmDfmc dILOpnVEcP73KREVii35oqDL9sBk4JNBjNR7lDD8RTe8HjJM6/32kqOfSuhOHTTjJbeLHOVuTBss ZCvL8hPXR19Shn/uA79nbf1ZF92/Fac+/KeBWg6Buf5nHHaXELzwGwlI1bY9hGp6w4yyD2DgDXyo ebZOBojcsdzpyxxucHUQZNNqhwlWD2ww8rtK6aZ0OL7M9owXOwXvKa+uElqmBlCxe6EsKRaYVp/Y e5baWtg89yct5JpHgwQYK3X5PHNKTkQcGeWDzKGEkCZfsb6R9E7SjltvYgkGXr3B1P8jcdcZbSPw /MGEYfW5jnM5bRV0POVvz9F8HMISne9lOT5aCBz6iFFyGLSFVghgxqGs9j9zsrPBI0RKlhWEdCSh tIWbQi+tWGBZR7e+zjkcpf34Bi0Gq6jFeCVJc2+0+0cwQrMI3fXXIuM7eVavxJtvWwxiWARcx3fE m8Y48QA4jwpJH9ra2MObAvymPcEI441xAUZ7wwwqwabRrauBwzaeuWuInxaX6HMXwMukx88SPFQg ipZwKjv/SaRVjyntPdsjs12dTTlyQ+u+8htcsynTbpD7sfpgqdKhUK1H7dCWeeNKg2jWhNXiF8+4 bFY2EZP54lWlPO/N8zlf+LKczmFkp9uLULAFCC0OkHaLvRLCWKzbkn/ffvfCfhYOgyl45crNTfso UpWzsBpcm8evKEa+dcU0WX026KNkrA/5FmkZWYfn4qmOfsVes2so9taOWjlbQoSTNstsy/t4QelP bnoRTl9tKIggMnZb9/747ibKQaJHAKpYKRiD0d5BOW239zoCt/8/lmp9smp/U8naBvyx1kXfQPhS SZCiWvfbM5stx0t4qpCygt4RYsspyN7ehuEC+LuW8ZzhamJwmtTKuRNn5ahmf6me3ciAytn2GCu/ BJm6Y+1e/70HZez8gWwtyQPOoHoSnoVsuymmlBvKCcEARqnYMMEfr1NsZ5hglfalVdQ9Nhdln1Yc wLlKEFVQGMBr9aBzp5mh9wz9aw/LtASFjfglpYd4gou+UO3/K0AhFyuDZhTafmGLpbRCp18G+9hJ gZFC+2DxKm2zUrmweCPnRwRPm3rrbFLiAlFdg5BlNxFO10GI2WFpWFzTVJG2l2Uc5eI7OW1e4r5f dyYLLeaDQ0NKZqMBJQBZdUyVi48dB5FtsBAOgIv+84bTDidsDcPxZxpIKQQTJvAjbXJmFRm1W7Vn uRD13uR3zLzFf+o9jYonO4QzoB3IJxFqI6l3M5buG//KBrtuisMejCimBkevyvfFiVkVu5DcGyUk d1X1bbHYAkFpe43ac0rlrTSizf6tq7DNCVNH8PU3g/kJvPQdT0ZF0zNztP9NvB1IsdfGsLea0xDr d64IpRC6Zb6lObnvdnhj20xGbey1vawTj551rxiBv4G/y1zLtOzeY134Yv7KhprIVCrfVOAnfr/o zEKzG+MX+vgSmFJPPEdxMKrI0uAiplomhnYrHTKiFozRCCJfO5AQ9B9L0MBKDMWkaKYcQdmFVs48 oVLjtklnSiZH2sxNkyRwEANgiurvTs/S+89/GoqzHQBkGTsxMAF97zLIMO8xtL6L/snYI9OxGeBq BmY/qgmJ3JNip7QlaZ1gieRyb6pYuqhiFJ3viDJsewsfWLxQjX81WNwThJUq4oYty6B0rZHwH07w FDwEB5nOvURresWVpYWOy6nEXETaVtRDk8aSQNS+te2K4leaw9WdG+uhigFRKLNxubsAr03r8+LA aMZvlOjNQrtWb5gXfBV+yRu7sWdbZ+uiAOihMepHzX+8BIPCOzEiu1UMXZbHPUOjwdwfXl9Pvc00 EjsKmS5MqPgko04IW0cMzxgmjKe0qDt7rkCR8cc5o1a4JoGtv4i8qb4dS1ZczZCiHGKg3shCK7af UvulxhYRVFwm9wtrxV+LwWWB06OF0e+ChGXm55gkAMGAb1W5MUYpvy6tcEn0KF/zhUg4Lge0q2HR xGBNJBkOCtKhx2A6WooYFm1L5riHlvRBGAcWXdZDaWOVJXfsInRjRx4+6mqdIfsTH2quR0zTsjBa V7d08d5AwnW+IZevLs4RK29sIcan74Q/wY6CmIdKh63UZwTbmRCz/LvgSZM486RXoe40KFQH2ZqD 0VS5vcs5+Q5O5fE08OC0Jtegelip434uFZH7SlBSGN4sd0OR+BgAGYqJ5vU63VoWvuAMC356ygLD fDRXMO3JAtxTy2YQVWMB2JLvZTWSZcpdksP27RkW4r8GIzH2jZlFBjr8oDgRG6UZGoOvPYT9G46p jAVLrrULxhaylfCorqRkd1lQOI1jAbVjBCp2ZSzIhaW7NdfFyv30hti2RbXUeupTl42OVjL0t5kF rlBFqx9M/lP0xNEX/ajGQ6XmsoMU2gXY+4KIbbw318HXktSE5YOlC/dBOmhEEfskz0iZRuz9szT+ xvT9Ji7u6p85s8UYMTfOKJFbpzshMcLP4CEE0IBT7uj4Ds6b2uSFUt9pxA7lGkGZP7m0D0SEJCwd h6/TZeOyld4YpVa6kq3I9abGM3Y1a/977ulLNRwKKswYuTqAV8ROhDxM8ICaf8aw6o9mDfa93kbp /c6EAhgyD/2RG93IZB5gQjOT3CbvTPlCIznJoKDJqMRDPI40nlaWB7bZ99zzkpxFxMjFKyirdw/I Cc3Xpl32k684UnEMabfzUaQxHF9JoIXU3RcQ/UZqSQVu2cdSetAnGYxA2+/06O9cnIxsigbtqP35 0gwDs3tZbTlpvnxvjVz5BAnsygbIXLyixAWa+ZRHMsSuiY92hYU6oORx9NbTGk4vz5ccZUsBBkBA 8XEB25wK6e7z9TdcmsChzl+yaHE4n7plbrZZGhAtaz2z2sasUlgJEKQk0L3eGtVdsuU3EzTzsI0X u7xroCAA5iMC1x3eVWzIGLSGn7QodyMiaG9tQxhBwpGgxQzreNsmpIj91l1xglIyz1SdI3y1XAQb FieHYMP51hbuooZBRTSFwkeeo0Wjn2SrJIPrqB5OyPr9c75bykD/7n7wkPAcmebh7EJ09I6ND9pY hUNNEkz4nowCAXvZ1dpT3f6Tl2n4UHaGvoaLs/Y0HBsS5gWvKXiW24OwyioFjc2/xlsqhYfP9h08 fBgltqam/j+H6KTzp3RjWlWlv+z2nzoz8Htd8rFvqVxTpS5dYKXhblk+Mu9TAHWGRMvWLdooRKtd 7bhhwiAghsWrP+vClmahi2/hh4du+mSMT5SyOHI1i8xrSNbAS6BL0PCPWiEx6exCV+FWjSbxFGZN GRgrNTnMRAbhV3hNdEOHc7CPn49ghElYBLBtgM+fvY0mxZlFRvokub0HXFHk/jglZ6gmke0PW1HO 1QKwm7ZapYOGlXAnUMih1NUO3DtH/j1sR9IkZF3RbolNtd8IAquhHxleasNQrcY1H1VFHC4lcaes X0YXruvzCjBEF2NkVsiL6tDOvjwu8R8SFaCXBFmabZ8UBCrrHe2J9GkVStyBP7EcPEOJ5YYWp4ps B2ZNhC5G6vDrbTjxiV9BdSd7gs+/P2FWrFsMRitTL6O6VYUgVtn43kOhPTGLcNjlINxo6yVGZmEs CXfjDpi9YQwemp5HyHUnmbcrAchsXvHSwMk7JRoUMmdBQ1p6ZJXK985+qNqrAYwWBnVy/y6HQwXz SDDn4B2dbQ8ANzHl4TUS6iK/NTWIHGuZ6hcmaAjNudtCuT61RyJls8jf3PLFHAQYeE/K3cnMJDO3 j9E4wNnK4zv7YY736kitJ4ogLEmmSB+unVGR0VfZBAsL2TiSoYZX+XV5B98l9A2c0UvslS0xoROK GIGbdrI/A42xBepoIwqa6cN40XpQLOg1auZQqfyCwmFKY6lwWhyDnMlBwH1iepCkfa9L9x+a76ze SM0keyZgM2mmsC5iZ+1atO0NeW18q2mlXoWuTPK2IoJHbIrG0UeE76gdhNNX7/fiH6D2s1hDQtDa GHpVZHt/+l+TQpgI5q3UAGl5FVgrgxWNXemlFSzfJ/0l6tahiQ5270X4KaXAoZ86n8icMTMQ8HtQ 4/wm7M+wtkrwiC4kDtBxltQFWewsOatLBlRhwPx36frJa+6bMjD0ww3OgaGcpNBnPqvRxZMU3v1U RiHjMvPvdxcrq8ZDiMu6ZiNJVJrc8F6y+BslrAJkKR5+80G9h+GhvmsmuC3MWeHXnru2cP/gS1jc kD0jsdL83ha+6zBEnllpRhakyfjSg/vaEZx/hFiDcNSVIueUpb1mql28dgc9D5ODekacMdc5g3EK WOE3//AcdiITmzKsTKpRVsp7vsQ9pc12QqhuJ2pkh0HN40G3qIJm8/cH2BneL1U9tSV5hlXgPYzo RkcQQ67gDct9oiviH0nX7slYKMey7rssz2IFD89IEKnj7jekueLarPiH8N6NzdeIKN7HLJOWTTyk ddp9F4WtzRqtkRRK+7JHOfWIxiG6WooHKwEwBzReE/QtiNF8O+SFQZi/rByeZQ02Cg5+fvfkfEa4 6IR0ArY7XtUDDeX9v7QE8c0ctForzHzeZBeIlqQDLgHBJqXZ9HR+1QEH5qN2yPN6E6SpKuZKIbDq 5FRALDeoPDncYaFp+vk67AqiPBRKiowOUFOK/dgHfLzDH93YGRj42d4hcw++xLEwdVY1b9uwVhLV NYGYeyT4wxCYiFev0TIERE5KD4Ke7NRzIe4j+hpqY7looNYMA+nNCfYHDnFyYb3NOYI/WJsw1/bR /iB1Tx4BNQbwiLSGQmDCsRo3j0e07y+Zq1zzNmujqaNV1rFXYDrFFroljJwNajYH0ziHwMGfrhOq GUCDvXh5VOeebqvAgkX5gHtujO1Sxfk4UMgmHesQflDNUyJYe6dPwpcOE9LVLUyFJEDEO+NPu1D6 SmdB3hr3U7CBD69pIMNJ3Bzvs3Hb/VIbyFwyY0ii+B3BYLY85P+eLk8xiBVHGomG6KA8SX+pxUG+ 0Qfin75HqnpLgpH5srICSjG7PGBpqi4G8QiPP5DrooFxx1QAffXU9EQV8iWHWRBV/HLhpNzAR2Y9 4pP+icYEk0wAL9vttOdSg0VpandYd2JADjYVUWdBDPOh00cgmGdCZI17PukaRKRIL3wPdmrgoo7T AAQ5URARYHR3uZqTKI5TBAs2KszLo5eg3VaSpRlV2e5QXPnriDLlp1bBktwiakv+68NsHH7CfO2J krNMGdFQhbs4eLmr3l9cP6f0TH+Y0mlMIog3dUAx8C613LV6z4XKLpxwMlK6dQl0mzfzf9TI3YMj j7Vri8mUPBybOAjKoIwvg02vJg40o4oj8ZJ7SObjHFGmx4noEaScL6Cqn3VwIc9A3fX/HjC2htSy cBfDopk2O5PP7rXa0VupmP2oIqP+To6KizOcm6Qog6sh6PDA9nhirgZp1GW388ctxzyBao7/+pS5 UMKVVMCja9jX4CPUmAVrm3dCKEbpkTjt9lHOZrPU4zBpcF+1mqGLIw9JBM1e0CR1OJY5DYKuoorO 94R4FldLpkyiMi2jI4cUYW4Y7ruqtRR3GqFrD7yE6FHgFTmd75I9w7fh0XibF7OdgLBVb1dBpkTg CgmLP7QHXhvHwpB6sCQVqHe18rK6OuoK/Pd/ToP5XKJ+mDAYL0GarQonyIVg8LFlZkg1gn1BY6QY 1eHjiWO6Mh1HGjywmf7mf1RoPz239dAGuat7KnXKhc3PVABFlLjkQpvAxAfqzVg2bTtchn4R1vhY 520JgotaNU7oVpF+1mELw1HiWty4NAvrAZsaTm/OOIe6CnemUPmi0KPR+umPzznx1pumV2gBbBJh +SIw3sT8fjCtidF43rtx1sPHhp/D7boXBsYcYaeLNLLBmXIvVwU8A4aZCKNtFlmupK4iJP3NZJZp h7HL6ubqpHmeANKjo4CrfnnS35FeQbOqNeUaMxwWLH16akVzF3DpVqZ2A6z/BA9OOojkSz3kWAfu 8ZJA4P27wB51d84Rbc763YYBlGFflIVw16tmuLo341oGViwfrT6r4c1HsvJkm6SOlryohKh4wJeC Z/6ivmqE6XJS+yT/Zj/w07egQMWJwgPE6NBBzicdGiXQsQtI6oBQhR+EBnuugTKPN20Gue9eKw5Y uUOMqCnx/uwV6IhhTG8O5nhzxhWBvsamsFnZDNdp/YhcOuKJahdS8/Z7OHrKSbafLdRBRvsyEpXM iwgFtW4U96hIKB/x1GY4a/581VIc6grqqTnfRRMxOddNaU8E5ed23I9Oqwxf8HrYT69J2DcuR4UC 8wOqhTL4ZBcGoOYtm7hmsKlSmdvUU94PXWNhDNr0hUMKmVTJ964GUsjA0bqcEaCj8Ckb1kPBmInD JM+6NZ84omcfM7Mtcd93RnhKpNBcHvA0HRQQIhK39WNDqxKZSrmkHHM3jJ/I7n/3EGqOg4+Bjm6Q S2+8CkSE1zZ0size4Dfg6PdVpTvZKIkFaNJ577KaPcz7YR9+fV+P+vyApXXr8BZbzt4D20FIOyku gRpoQVRMfAVkI66FEXxOn8y5+loRtI/Q4ClBSZULGbog1R5pL7ujQaUYLP6Jp9y3SoacQ4lEToXu pooOnj0ve7pbUifUWCgVCd3xPEeJBJUV33TbNJ0g/rnOtQm0nL3Y7Up79jYCSpVIzvxIRFiVsKyw +42/gR3otU4FCQBh2kUFJATj2z//i9x8AaEs/JqfXBDh/rOH1lslX/sNgWbXmLnEsT1L2M/s+qVh WZzJAg2qu/BdmcO/QsvwxGsbLLfaOVlf3TkRMlQfsduX+tvnozFbGxS2w+LfMPQe3FkFk65fRp2r TUCLUYZh/6Y7cqS6BA/E3NATW9CRH4V0spWb8EXQ4s9tPBFQYAkM3eyoeuo2HkkAQkKLqhythdsJ 9yy45QYsUa9vdu/wBZJ7z001bliXbf5k74Fw7MUrVBzh9G/BkwfOPH3FWS4yA7qBX0mj9KX+baq+ zHRV0ZvSAjZ4X4BU4lS77sVkKQKn1HW7AJxuJLcwP8ksLKMDv4u1liJWT8vVqMjU9X6E2rw8JRYx jnyx7wOwe1EJ/rUq1sJDbbpeorgqTmTA3/miNf43w09A0M/MW/gDr6ZS4+DFLwvSGM9Ij9JIkj4s ytPJSrgJJ5geMPOFJix+Z2ySN1mO17IafFQW7iKG7xwn88bsD5w1abEbGe1sIep6ZM9168xa538E Gh2YOYahD74ScpAnaCJbwgRVmODJqeMklv+Aj0JZpyL1SewmvQ8xftQw1xckb/uswkpTIqDnC5+2 tPE2vYumjTxulS6hbxvqpM1DpSRrjAe1P7oz7p+DIDOd9fAdQBfAgi/GwoGZXddnpBG73R/Wm2V1 m302DLdPw+r1C7/R3tY1v0cwGrFPjgkdNqR38CMlExv8tYN6eaOpF/5aMP5f7j7iSjMEkmvRs4zh sW84nEf75xY3oCsqGcj56vSpM2sclIrF0Dfg8CBYZYlS1LCoELXGLf+aIoXbosPgq59aBtwexVQZ p4VWusRlJ3TxrKtiVl40bjINafan3UpBWO0yriT1o3cMyRdxE+3LJT3rXWek6Vd1PcCtwlV8wSzW cq6NNwDcrEuwOyRlT20i55Mr77bWmyoJwe5uQbD8erFTnVj2dwRdRvkKabyh6GUekaz767y1wWr+ RVhS16i1eI44AVUGiBYHu0vDCRiyMGo0UDI8KM1vfyMbDZBXDFXQiFgdOzt8qKBXvsgyj2yhHoN7 A0x/f8YoG6F7cyUzFgyGdRNmofmRvSriOcENRFNcgZYqBqy0v0a29zIDMmb8yqyxub36f/oRir8x eBvnQJWdcU7i66H31ums8/C35Uwc65KOyX/20Gf67u3m38AmKgjUGsoNxnL2UWpShVAUpqKIP1GL njJ/vJDetioPp/9Ci+SSCsNdI7xCWpcYygtoVtqMeeeWVPGlViCUXumFi6sT+tU7gJDWMFE7qPo2 9lAmFyuVbahJagPl2mS4zSDUUspiGe5qfQJQPCoqFoSPkJv2p+Rg4qQTSGnrX3oody8FoA1EyLIc yNAeZ1Z3MtlSgG8QBny1iI10jIdO+L/8Go9lTmP+Njeaxmj51tWTXLsZl9NGxmG9DTJpkP5hzW2k ESjmxMTtIhEo7begBFAQIMZoR3te28iTVZ0/KxLffnM7iRkrAKgfEJy1xhQbCH/Fp3xNSioMrHUs U8x6ZmBVKanbREv42a23Cf9t4NUYcscC1yfO2lazvjGUcbEhG2iMTZ1X/FdFmfsjaLCMok4LdAKT DmSFRhLjuQk+t7pcDNWGPdJRNB7lVcPlILz2vAqUjdmiK2J5JKBYqd+CL67L55tDh3bW/4KZq/io h6Nz1h4KZS3iblogK2r2czMcE/T4OxCY64wEyRF50cOZbAyjXdqjQCeHxJCTmeRkfjeub0et61DG OcdrN666zTYNtpov/Wn/gRgynBSaYEwxhpmlo/VPRqwwFqbZyZvtKHrRWXndQxzKXGA0H25/g+/5 iy5qi/m2F5cZoPPO/ksETgw1Fsp1kf1yDRRTWfw1TM7s7lr/8MLiDaILVfsyfaQR6/mRpmxo9Jjx gelrBClOB2XCcrvt1xpdTcdFotVl7JkQhxUjy85yXyXvOl9j5HQKUveLDXKXNa51goS5AZQZgqdZ 4H+Of2/AcGOWQGqlwi7D1PoTKJLimHho2HvVGdkkeA4s5zG2DjBb9FN3qdOmTlvPSiMdzKlWwkXr Xqh4gRwFJE+9/apKZmNu4AViqenBnnq+zgJ7O8Vja4f2hZILyA1/DWunGL+OIu02qzaZgD6yw7NN Zi7e8/n5bMuVjOhmDffPc6eKsbZsTvzOFJ6l4cYqJnrem0JDZlpVtB9tSqrr88CZfVt1Qo+2hQSa Mza3k4VHjvYRpxRsWbRD3bR7Etet8EeWG18b7aUgP4TMKFuW7a3QqorA3tkIebSzUEt8TO27uBq2 3hyhgLaCP98AgtM30ZBngNf1Ee6MTwgmOlIQtxJFP1iDF7TOKzg3jAbiTYlljBHUEv81vUF7neZF YCp1vTt9QLneRMe8XqaWCLljTKHdlotT++ph08UaneOOmIiuuafXpkInF2JMqBxBUMVuACdNdGfl qIMRIvDouymKqooFqWOFQf1f6dL8OtccNizRfzkTBKy8i9h88dJmjYoV9yt7Bskdk/KW7pdSMjGG vcxOsOaWK45wcGjtiWiF5w0ZuihzitUm0YadeYrIODvP/F6g/GNDmnJPjtPxVGxg37OJx0XiG//G fVtCjxwTWrdN03f/wnbY8OSSjL745WvQ7kJIPT4DGiPTaXXb2DT7h90RT9EJ7MT7smCubUh5BVvb SntCj2pm2ajAsPXAUdYq8eIgORE+dEm/zjKO0hfueEDTPQtAE7WAEScMIu5rL7lTgYCuEkMGcAIT V4sqzFoqoCdl5ybVa+wr+Ms07EwayzmUHZCqQQF9SKKc4N7c8P8nFui/l5rTsxzQBiOSWmptc9tV 3giu6Z33nhUEZ3ts415SiADhrJNg+SY7QZYx+XfJ9hONJLlHkSyqa+SucYJb32n6ftuwpxPHCq+D 3KfVn/amuo+yIITRn0teW5B1eIeTzF+tPvuU5u0vxbMXP21CWATT2OTjrUdbuq21A66cp0hHXZbE b0e4LccefKRmUY25XIVk7azf1gawEFEZuqZuRvF59bayAvSkEY0M6O/6YjEv2zveTytT2mFUEEog BpUxIr9JaEAU5zY5f0FgCfi5QOrr0zedQURqKQvfc+soPHCtoaS4G0uEhOKWdGpo+Mne8WMNWJEd wfprqtnPGmcEINC6wvOs0TgUzsW+FBT7QGtXBaXOV4wvxRmPhQldPvvRNZflLVwOhSZWLO8FpQ52 PwgKz5x92HgOMMYqUrGOyu4UHFH0Lvmv71YXe40u8LN34sRLwG/vYJPsidp4WwY3DgoaGtdx6gUt vgeRQVuxkhKMEJyD8EHYZ0gGgsaoUZTKgaF4iOHJF3meaufv9fAIH1J0xk+Cy3Yn9qwqllbgsioE n16dU7IL5XXMqe+AkuVJe/lrQIzMaURGp1+iBle6SdvbjXgs34HxswO/e6c/2OGS4+QQ9OlFh2JX Lm2J5gavpYASpFMJgirT0aurYHd0dZ7BrLPgeMU+9kMD1eIYAmm5CrxcSwjBQgCP9REyqItoaG2P OGH3SnCq8tobflgzBm8GjpNmhjUPpLHYL722vMR/t+tjixpy1qtTlIM00wIJh/GhWz6QSvy/0oqL CjjhcE4iS7f60Oyy9D8PGTHlmmC81A5fkitU5bhkiLV1WTgNzF9cLy0F9Wv3PguMmClwA/AbmO0m p9WjpkVZqX3piDlrW+ToizToUmia5m7Ft2668A5esPUCGQS51EOEQ3LHQztlt7AXXVpc/wfXLZoL yY0JTsyxAqxiuvlX1au5trCT+wVjz1YLzqGsV00gCnRyhoMvCaXZ+MbyRDcF4B9s/yRRe18tDifC qYPFr8J6m+MzZIZPLSglSIsKM8bpEPfG+WMyhM+XdTIIgjh3wCzCmr73rFiyLpk6ylqGHuwYErsu NdBlYQfPMjayzSbarxDnuYM6gAkPgk1mubuovs8P2YmkOU3U5Goo/NFnDhpIn6B83lw79NRly8lf 5PHypV0yBlNkIdJbrB8hj1pWsNi6yJdETWBzkybWYMwJPMQWhLO8pYAAAAMx/YHDAQzNwjWfec3t a6SrN64jEBZ+PVxIRv36Vmlaw2lcMrMpQWrXSLv15/N2ntrc1b2AbJUWMrNITpzF2UBQeUE/Tlax Msy5A1JBOfkZBeNDKI4eJRZ0BmDwR+SnuBUusLuuwZdScy1/v1IjijcLIBtppMSGlYtchExyHcsa GiQMIWbwJywHiWgnhcPzpCm3YyLiRvchr9TLPvTeRmGXh5uuJD4Yqb6l1CcrPcuTrLZy4VONQ1Kf nXUW8dUBbF4Pq0FERaT7tGintNevUPIuR1FDC+CfjIxWLbDg4wUD0s5tLpMNp8fmWx9JcuKeFdjt 3r+y9q3z2aAowwxnDrPU5LFHeHa0GDrfBfij6bwdUm3hEHyAbVaxPpsvzF/2GxSLuCosWF2qcVEv eMCDVZlL7eMMv3ooicsk+hjuIX7Yp3NnvB+XwXSLaaHpm1mxaXoX8bSVZ6edoLvChrC+M8cQkXEZ Gof2q9qlzoSeJS++N0cwSos5sAm7b46ecSyuFKcZ9kLeIm1xxXiVSwco5hy/B/k5harjKVyjdgXH zq31vBZwCh+OMbgXZMGd4W4Ttyw0d2vbOMZUFQpEgJ/aDIE+x4/u2LVQTX74MLV5Jwdd1yDJ7dWV x5UcUM1aDBji5IqMUjNU+VdoJcSCVanvAea0ZxTAz7ABDKwVROJ1/wY0q1x5Seleuk0Zo8Jygn9E C5rMAmLIRn9hyy16o+Q5l/p+Zu15hjtZIF5SqOC3/5H4ZL6duGvVp2PP4G91X1+JHGlPeoW4sNdF 0UD/3//jX5JLjckvGK5hTZQZ4BcjI6prxufUJBS0SIX9ngzA99fzIknaoJYYN0b3h2WSreW2G97v yzaP7k2gfcCfrLvoNzUx47rMXkeEA2YrCPE8Xm3VjSWHy/KdchHW2nAkhPgW04kVownDzRF0vFMd tZDPAygM7YumZzPDQ8fAyXlwkhe4BHGKJz5Tnunf9y5oIbYBGeM3xc5ZcOg7Z6Y4v7e+8N/Bcj1j YR4ZUp7hjwi60flQW99wCxgDE5yRw8ceQQZtDFH+jqU8Hyaq1+eUxWpOJ4tTAZYal3EW0uBllkV0 Dn9H+POef+KqvDWhyYhZMwN0BvLq9PdKzAxDmzCvr4eGjp5sEKhjByTSMlb0k+Ap9iILNZgwfNIh OWLSFtBPJ4taNGtrH+qEVxrtgXIoaiTLVSoSQwM7AQMVJBHjMph4ETJJt8475Qv/8OBrcglVGHyY 9SKS+LyoCyY0uk1S2r0ppH01S1tZ+r5+QHD+WZE2n88/r62rkze+V1ml74HrrdJoAawARBKUJL8w DDLtAYxQ5+GfuwisHbY8nbQ30QFuh10QFPcAf66BVqsQT411Gb4QR4YOwNo8oBpkigoegSwEgeJE HZw5jYCW8kkjSz7RJgEbHUVywf3UxvnedagM1un2uN+BJzp3yxzn3FdhKX+dqv80DCLlblx++Fk3 c21MWCWLTL5XyYIxjJ+2f0ELCEh9H4bdbrwc8CK6xKQH46EOMWNnRUjixqtObZ2dNmQaywFcyigM 3tBAluV4LXiCFw71c7UPKOr2wTe0YX8bmKn566ujSM3e+frEWHdnHEEQuZi2Y7haUvEHQvJTxAi1 I8BuzrXNUwFLblLGw69SgDZmfZY1DxEVdyNdEzT7pidYJVPsAYpPqDvrG8nXH4ETvB3JvrXbMrjC 1KcU2horlj2XP+o96hRtO0ufo792mmi/mmMZjdrxtbm3RQvnIbM9gvwKBD41l0c7Wh8TsTKoVDBV D1+uaMBp7EuPPtXIyYeA7xTwGgAk2v8BS1va4hrYEMD90mmbTCBH4lgo6aeCsoU1DCiwXihW1nY5 hqPv11jGjmvoaDQGSdq/dIJddpulpnQBKlYUpyOTraOVn5AHQqaS9VLTXInE+DLnYNjPgKh+h0X+ NKhuwIyD7EXaAHaOLUf8XaQqqKr2Y7z6hQ2ijWsHEN2PWaj6W+ANiGQTgBQW9+CGx3gZhjkaF8Wt 3xpPqkltYKi2YhPVVQNFLyoayuuMKpG7UDS2to8eN5Hct6n2hoGZ231FOG9k4iTXYVQ2KYegvwaw jhakZcHhpOSna0JUvaIN9pjWoLinbiTSh8bHiMFKhEQCEDCFJxJg9Yc7R0xEri+FJWpluQNE04Tb vPX4JSg725DCipUZfP+sZOk+DcyKQK/5QXwbkwsPRiv1dve5JxQuOjxHfX6zBX4tsEJI32NAXBbV Z7WgRnVsNoTZv6C+XcZueh53WIkiIM05jVrIJOaDppajZa6lL8J8Ve+YUAMbaRwy2N5eMk4VDIJW XwSOIoFcI9TET3XFePQYEnI6+dkPLLf42HBcNAm60WbMkBcmThOQxrc3oLVvTAneueTOQdh5tqco nYNxW4ig3uJhwHR88kNDcDvpZLEyNRMt3oKCfzCoyY2QYbmJrlBD/9xKkH+LR16M4sca3U1TQVDo 1AXZi4tx65umvXng001Yu7XLvdGeAGMwvNYQb/0DLKrRDkAlqHk7kLhgwKXUw50jUdHsV1EaCUhL XyuthZJJvBMNODz2WKNDmtCZf5cZlB3d1fTql/BZpxXpwqN5YiXRuylaAFVYCRt42xG2nUqAHQrR 4KTi1D9eBibi1YLRFF0AUO1Xr7kftWPqL9OHnFmJ8wI65WlmSUAh6DyANsNu2UzsqA4XNfdtXB1E rsm/z0pO0amOA6bF3tPFdhTgoawFntYrCRU53q8rKd00itox37SaZ1MAyL+PGDwE7B2fL2Kpnk4Y pK21I8nZ5pj3WsIUqcVK5f2Zf1VvwcKBYxXZ4v9WYlvlU5FO6L2JvUTG18/BPZG5SB5sy7iDNKxo 8WA0N9HoB85dOTop/G6Uz229fzB6qyZJi9mYuh4r6MEbcn0pk7/KcLBkXbPYEIizRo5XwcaEfvGv tk/NonEut8qa12dvu/b6HTIOBvKTLmrl/6kSpn8qwCpeY7IlGvAKY0q9Ec/6i4NjMq/S4x31PovP xvUSWx2ACHscnoTQFWMWcH4+eKxR3c1Ut5NApZWhAPgg0/4ixgI5wtvchz7kzTPx9w8A6yDfRfKI 5JFSFNBqMO37G5yrZ4ERt/RDCILg1FaONQrXGGkt0aw5rnBBC3LcBHwJHR+1zMI6HCFKPIQkSLp3 nk3+EF7ViACD0WOxF9ssKbvyBOZBZoOBUmEhtpCFcKFBckMLZBa6ZUDycRqLUXYKqeGPo0CeSXgn hn017cjsC1p7rgjzpx2ln9XtWfyJZ9JBdrbXiywdZi3y1abKW4y/7UJr1DWhHeAL5YWM2iuvZ9/l 8WLUSzxibKq95tVNfD7+4DyFA7vF4EW6At5qfsGisTOy0ddtTOQLhK81o9etIrv/dvKNXv/G4b1j BhCIUmLSy7rM7Mf5Vvg8MGlDBjLH71UXgyzoBqoM7G5lzbE8lNTtjFY535vYh8onn3uz1P8J8cPM xSo9CknHVxzwbnd6an71JTpyzdC+eG3fTHs9UvQImkX36citra/xtrb6UcddyTIj3KcRfHqSVKF8 se5gOYUxBrK4IiYk9UHMs5EsCvOHHI04E3KD7bFcj4i9crjmgze+/zcAdy2FgKzRLx0yt2qGVZET X/0zs3IoAGLU4E4+my21OKRgEwLc6x6C65C3kEOzxKDXXzStCQWbLzTCbVpxH3hxEjNKWtwYDSmZ w4CTeY/u6kJ6hoXkZckB5whJYJVli7QqBPUOAu3iCohrS0a2Jwd81eEXrqf7qED74LRdrf8UUHgd C6ouWKzNlJ/Y7a/HfJQ0f4TZrjWmWcYCs4tluAIm/78g3TEATjvOmLnDSgzr+25zbGHZNV0tlktl BvyGe5EyoPlrahrDVHyVbFoXnXOwv9zGyX7FBRxJONOxKttIx3AiI2SAZ0Ww+P2JQm25mSpx69i6 czZ2z5/gQWwV1xe3z1h+OEsykhg0YZI1bVVQxK7ENkVETuYCF8xIGOERGxw1Dq8YOo1a/XYxqM8z XczJcONJoFH7gsxoW9xziinkzgEJAx99vzLRlH11A4mx0r2OEBtqR+/Y+e8wnKLA/9Y3uYV0dTQU 4pCkOLpA6Qah2MuUvWKHQxPZCsE0dHX8cJQYHy4dGofEwkxq2fwXxrayyjyrNQJl6PP79MpiIsPm 6B4lp44Zzn05S97cCbB0wkvYmPs4OKAF4aRaxcZWoYxjduMb+c/36rIWjDHSDfYsyEtHGjXYkZYW bIKmZ68abjwOcbkoN1133Ujk+Z047nk31gsxr+zC+t34DAbBFfasxSbVfgQwU2wCuqg07rQ3VbT4 FdM+2YN7iTjGcundAjplQkKdHcQayfz3LFXCqkr4lDsqVKd3KCrbqRIBumyJmFC3ckOBTL7jHnYp Iig+6WOXGEBMO+lopkq2utK1y+iCqcwMK6MjEv0VgvAvksINb0VYPUhhdXC0eNxRlXyTjh7Vk5By Ie6Ft4FvTvnw+Le2jUKL1H2Lu4M75HfSZeaQCevRkPlbxZhQ8Sozvf8Eoyxqn+R9WryxsppLYxJv n4qfb3oFe6p6AHwHXtZXjk8q7/7SdPyUvole4l1nK7oj9a8NopUxZqt+hCU6ZqIKvu3tTuRKqK4g BddsdvqH/LTXldhXmCTEjNDE5btnLf83qNp+OROoZG6h+f9UeGXBQaCecLARiDUx1VX7/d5jT5Pi +AO/ZC6aWAjr3zBeXgAZz1fn1p1/gOzGTU994oiFVehkGdRrUACAm/+YLT3CBUqTBlVRg96a0vOt /MAVG8oIPNcBowiIBoXwayI7zcMVc38HCuxblzZqVuoutx15RPnBsGsSLjKfw4GHbE8NO/uw7ikO rV0ITEhq7WnKnmGsfoFGpTFMBEFku6Sw1mvY3x4BBWP80aEwt4l9p+SoP+HGpYABYEWid2n0b1sA QssIHdqOg/CiAKTB1Lb4BxdHzYU804uebC/ZFGQYbegdjTnb/+ay8NnsoKyZ/q5daGrjJs+oeewA eXxccqLAcW/nar9H3dm50OzoqqPEhYFf2DsVdcU2jZn3DdrqEk0+eh0ZxkgT1409GVkA6LESPV7/ DyyP0ORNu2iwiqCYkU3wQ40m5zbav8Lt6/PKjr6iYydP5JWw0aVbfFoPOsou0CvnbZs+SXM2BRJj abxfufouqGZa53AVnSlUe4NkuHNACwQJfB9FsFgcV2vfa4I5cq9SI+VO5V1FVEsemHPBKwqCPg5M 1ZwCrOQEXdavBIs0RJ0jxISiik0Gk9MLA7+idPo4McIr6rtxVpffylMnXpOgYu6Ct7gzRQ0FNXxN 8D6nJK80Uio/pmpYuQpoAsGuXaom04auu4recnvVFjsQpLnI1ZF/ovd6OdfAeJy6SX1Dw/1X5qdt 5CPYOP8o3F+V5mXcHsTnsTh8GbB8jc7h5N4CmvqeMZ3rZokaZ8Ulp8buEk4VIJOta5V2Tmvb1DYX 2Su5KcF4hA9e2LWBhfboFZv4qAtaaltdYpkHVtJFBWlSr52N1J4orGsSFq5HKSZ+FN1Rpsra86M6 QgNBLY+DhzIgk5aLErAeUokTGfibFCBPf7RbOxrvdm8KNWb+J+699L7vq7/dCmnf7zhp46T6qH8B 6NhTHYS9DFxicQSk4Alp+fOI2hLHWWRPs84VUmRQvQ5Yp0mmUwlK9mXr7NYAYlaOvW7a2GdzQeVs IigMbf/UKZ3FYq8fePtVuefMIAW5ldh7DnQl5V8pQkvDJbL7lKDTO2uJ8h2L9VrU7iljj7Ro0zNb u+QXGTTlSVTTWxl+y9JDKFfyeO8gEXxDb/LAxzUSTgSd0UqJoMzojVHKwbPBeBBjQXhY9z0GcMNd 4OkMqmRR65fN7aHxBAU9LdJq7TgnSn9ABgcHbS41FLfLtEFsK/GK68/ivKxeXV8rcytxLv/A2dYJ 616YXALzxeMWqkOo4hz15W37/jCt6FPHbfZxe2AcoC3LCTo1TNrxK3pe7hQ//CaLK8lmmzWSiouW JFIRsN9bvd0v3JeWEM6Zqn3SPkuolwxkNWiNYVD/zKeKUc+B3E5Rc4rDFZDz4P4my0oqH24Plbmt aaEcpnZFXu+iU+JImtnGErx2rWre3qluWYxWGnj34+RdHVG+LZJOP8f7vAvwWS7DSvfJ6UKEl69O 7dKP+j0XOgoP+rLX34nllQgW7+QQO+MlOPYgKHZsyhaXpkoyElJeYa503NaSdsdUjeIjOG80SpBk WB/K52xrOHf76BVN4fCstqXJ6+FnWt74zWXCDWgqT4Xa8Stj/QWLGucEjBXivcM16804kUZ/56z2 V5yIxsPfzDfyMjCCzhfCY0ND/uMKSSvTrtoLrzSP3m0lDbNLIBoK87qDb/khfQq1LfVLVGQ9jMid 8cDBC0q7FqxfW2SZamo9sru3pAL9twPyXFFbDhVVGlC5dfDlr5VC8ypigZG25P0PRU0yuIDk5yBo 9gC5jMhdOD5LPYwc7IYaImBk26qnAA3El2BLLi88AB9c29rCErgSVhvX94x2S4tMEpwFbD2wXFia bk2OmMKDko7peP7yPp/TfxI/2w+UP6PUbIZ+gCbQ4rypqICEk39F3XO9VUE7mZk2l6p1QzAYTpWj XfYtCgVVieuktKZQZha/2feHoxFxIaUalMBKk9LJujtEjUduBeWDtnm9oV4FG6pehF3wxH3paxM5 JwaMM0NogoPsAvaMBYdC5AMiBVkq/fSzVUY4T8csNxIBWQECIXIb6T/0yf+g065aLtGV7QDIms1w rrqoz4ihgFx1yP4qEiV5NrrB/ksREwPrhaZDfB7iRP6hpa9gAHXFIn6/YYcsLs1iWrTDHWiymw2w enogw3ZNWkAbxKa+eOe8qbusbhXIPg/0teRhJHcG+yxGT3Qj2VrJ5XBlr61BGVTO9fiNd5Ezgppp QGvQPQQU5oYtYn7yVIbdryRAAhMrXiaZBZS7xuDw08O/BLoAVCCRt7+8296gK7hSWbkIqlU8TanY hXujgEh3nOxShw9uuxllwenD0DeTFWVkvBSU4iIqh5v9nCQLo547rqVk8DPCdgLmg/01iOD672tR WTf+fP+6Ge/ZMoZqKJCLhjYGhHKY7+8bOQH1O1D9A65cJlUS16t/pdNJoH8wzoEiFqKSFl4x96kn CR0VZ5hporpllWH0y64ruSnB0pOVyNRGS/ivPf7liZsVrlfDp2AS7auCdxsnaFgPQczL8fgqVSsz SK5u3/q/BA18V+xzxwMoJOwL6E68K88L1YRtmckq0hEhzbn/+VIrztpDqC9lVu+s/VTHdapveFpR PMh9K6HpdRonw4Lian3UIKgVMZRqk0eJN9bO/1gBDpNp4pzl11b5LWYQmKOWX66cY0y9JpkDRFrr 8ZpQWTeCKG8puHKylNsCX2mFkMSnQLJHvCwfXU6b2avPEfxoC2dXIxVGgDwP9B4du8jDP8ZjhnyK xQ2txFJvtb8r07YCimGR2GPZUkKFg5L8rYQE9L6xTjP9u7lGIOq7lgyN48SwKYCnRvOc6Eok44cP O3d5NA7iSSI73rJ6vhAkM4wiLvv3O47G6yJuzetGnsvcNwpsFgKxZ7/e5DfhjkzBfBp/3S5pS8ti R9U98TvFofHQhaAGo8MHi2a07sE0/zB1LbOX5Eer1b5MOl4umNwGm+9dKnGkObwFt4sh8Gz0L6kb 6Ojguz+llwbsI5vEk8FGLkmXm1XpxV5kRSY1ezd0wz6TXBB/8NeslQHbxYVJ7A+YdQsmhfpoUgxw 1dlYk/TV9plhhpWguLJW6es34MRCNa3ypHNO9kdOrDL3vMFIVrblQJmtvyNy4DSbwI8qfqVjqxDB 12haETCoHOZ1A3kE894YuTMQuRrhRLsFoJmU3ziuY66sbjHQWiOZZ4Lr6HiRhhDybE7rBb+c66lP 9m7Uiu8nZVXH2G0o50vzfZwgCW5KF7oO50eJMOADdCp0kNwZP9L0bUBnA0irxHGSCtijNlt9QeWj Oc9xhz/+EXjPTantZM5q4jqKUwR/RTw+p2ctZ58wXYpPKubJLKQBfqmsiMHw/5eEqI0nooQAZ3nH UoJ0iTQdIYbxARCxx96hVy9B9N+Nildb3aYmLwKPghtmViwUELkFybig9VyWfKbkS8PF2UITl6eK PS060/BETAvnh5JjEKGDaaPdpCqWIz+iVzTUy1jFPRHLiM2KHD3xWWAsRGq9pQ0k9DLWmAPpNJTS 7ISOfS8WOH74e/IjUdBE7dl+FVo+7gUO7hYJZAXfG0hZwkrs+L0Z9NjSVdqp1UUBpwQXmcOvyENQ kWVJD3nR1Oa+fjS+Vg17HxwhX+3Ve/BsTu6BCi1+9u/y1AYsgBDbL01f6dL8OBv53l5N4Q2AmZ5X CsDcd8ObrZ1bZA/2O746NpUOusWwG+L39aZEm0Rn9jxKKEfLN030fG9h/hESt+dIdciwPXcdsnoS ABh8fyVAQnOIXWWEqNKbRfLRsREcx8IXoAXr/woXOEcIh2jvavEwCzXZXl6d7CQxT3sc5OHzAdTm XJxqavBUseKoxQwx4Jtl+kaBSFtBb2yDKLVs6oSphGgsGt+HkyeePnGccaAz8KippqrS0+ns3bRK ZdTo6KO1hgu5qU2f0wnY/CEJ7rvqQghBZLxA7uz36SV+N+gfmkFRGuE8DS6C6rtU2Zdpgr8zTLjJ K5MBTbn1KnquLzsjc5T5s8JG5OregJ4k0rD8FiVfBMcmKcw2PgUIdFvQIUgNm5PSAI9hIZJX6SCr jH7BbSNE3WpGkzvAU0+hR1ap3phUNTVLB1+lfWmaeeM67r1yMKEcjk6ujzvEznfpnD5XGe1YLZFh X+yXRJBAz6KGdUtgAS1H+ERK54OJtbiJtCF3PTYxyNIML0QKWbZuP8GQYFOBLCzkLQXiWXqop3Qw hI8MtTK1Xwc2ltszePZMiJBac1D2Zqa4laA0PeK4JUuvzVcVksPfE9Q0PGyp4+PHLSvE/2nkwL7q x8IBi+xg/ZsQ4n6MA63mvFHHF/hTHzVvfArnfoS7gaNCYLEZXEOMkXdTWi7ZxGfSmz3ERb03sR87 cjgtw1AbEgLfPXP+bUSp5XE7X9uR6xdaR0eeMOyb/OtEjqCA8/2OEMxHBop/szWZjdyR4ezYuNT9 aTxcoEXjjNE4O8uc4JP77cLyC4OnJ60/ThS5OeCwJHIiiNVkScmMb1b2TuOftiW+AeYOsnYlCRwc OEPvN+RcxAjG1638n/VB13Os0Z5d20r2RSDC4+1Wu8PoeUHthBG2YrTptw78jDKIKo9weRTBN420 GiRxtSJX/wHw9hJS7cD5AXyksjSk1ONzypiqlRuH9Rj5g3P+vbxOmgC/pGS3QLeY2BZfPKH9t0Cp /vjCvKpX/iTClu/il+NyLUwyCztsyw3cn3ZEz8Aer7G9YlNgOgxARZzXLypt62wPnmuHxhihujGt gb3US/c2Ifghuqs8hbUmpGBa8RK6yqIdRyOOwHTSqS64qf4dPo9ySu+PY3lHAwxZFbne4PTXv3V0 WLfT+WURBYE4qj2gX4OYemhk8vJbhCfiEvlXW+yXxClOgmyLWAyq2aZKapmVp7g/WcVeHX6rYps5 1yDv5ZqQEd3H2hEP7xmTcbg/ashtcNX2JkULXl+gebeuZyV9SDtO+e54DwE2wG+MhZ7sHd9YG0bJ tMWrYVvT8SRPzu3b4PmYA5nnNzmvItcvatfZpFTppAWSODdtI26LX+LN4PbBB96CFYEyDCcH5Dmk U5+Uqk7+cAsKXJmNTexv3XxLSxoN8YnhZfxGPrPR6MKvyc8B107LbnMc5uxcg23rAyQ9CIyhZ131 db2JMKFuuns6rNwPvuvqWMH9VjpYBR4o9wnAjcMfJ3DzevTMyPqFiDVQBDuRjI3+Q0z5JQcwpHGw V5S7fyn3k5QKTNwibu0li/CP7E+VuCaJ+vPetenZuMCvH11wEjgSyqnZMnMt1eiMKPxvyGRHnFlK /6mKKGLmsl+kBKpqSOPPSsNdAopmK2txyzSky+J3WYkmXgBEGCJh0GPq1exs9loyHspA+Id9NQOa BA2lKVMt17y7NcH4HId5jou2UFCBYGvH8GUaO5qInatIf89HaiQTqd4dCVye+ckSgYHjN5A1bzz2 Le3r20Y//RtCMBIsMeJChif7p10/FOuohc2USUoO3zZ9eiLIR2+KWsc7Eac35CkVpvQ2vHGaf4SY kPCWH6TO8yWpSd7364QtPHCZ/dwJ9DrpMeTytS9VYWyYTJYXKeMKvbCP1hwHFY4tGlIbPpNjhxCf Ppjuw4SILIf+uWMjxmIAu/vv+EBR9h6z6wA3a/Bb2HmLVhTC7uoRSucWKjG8Tvlc0sxZLZ9GSbMh 4LzD0LM85TMo9TxzUbp3s10jjDC1OihmhZoq93BRxg/dfkKrP1lP6exzFzm+WR1+/eCEaXinlVsW spKgjkI0ej+azZh2FQx0JPFSO05MVOyNxua78AwZTpgUVropf6EgBIPgmUB+hscAU8z2XPxQLP/s jiVRDA3WsueItx+b3IMWrXQXFd8X+Mebq/hIvjD5QtlYshdPkgrNb9WQz/4mEnvnZhXd0gLndpp4 2ocLRo4TWYC0crnyhwyf7n6Z1JhV/wDRinZjlXEZssG/lqLtjZ3yDYFk5a9gMscM8y2yajnWKpZv 0LZxp0MYZ3pqeNUXg5NQ91LdTFd36YLE544UXBpGozG6NT9sx3yvCBOftZUh18jfRSaC0qF69xDn W/GV8Me5ZWz2csjn19ZyOV/a3X9ZoD0lR9Ji4tpQvjk6/8QWyVwAFv5wtPmXQAN3hGrguphVaLc6 j2hqn1QaYb/WQTQ4stMGt4Bnt4/e+RMbANk/FvM11zSqIOsCJDa3mdbY43cVNIe8X6BMZaDu4ht8 pqiMJnBQWko3GFY9ZhMFn+hWRR5IiBhy7/WPL8FoupU+8itmOmbJzJr+XztZ3dKQpjpBqGT9+O8M gQvD7V7zFVd0VvZ9NyD09xqPK4wpYkEZ6fk1PbjMgkUzQ728WI0JUN6h1AwcxUCGWG6Ki/g9k3yw wkGG5hITgbizjnoA/pQ0oAwxLeY7k+JeGlHkBmgsKzuZoFvVhtFAdaYMnKRK7kp1UBSoydlHymLi ZX4QeBf+GCBo2lnrxc9zRVNcj8NskZbnaFRMPI3n7n/IdwymKP744ixOL6pApdQC3yO61/TwNzz8 n+cnXDevqQ37f0yRnkHLxQ3Xu5qgFAYfScXlSkTi0Rmnb+49ztKee7W3ngwB6p1tCFbTpXQxAxXU vnpGVKNeYu6hiTcyqpYKAbBsroEk/5Yl+4/C2EOe5qRCwM+kuPJUzX9VdMitH7+pYKWV3Jb7KfpU E95zRH78I3Zs8I8taWjfvGhpjsb+z8iKH1nn6d3XbrjBThfzpSbcMh0Xm2TH4qBGMot2tlc4hTz7 oMMdsaGd4WBLKhx9wD8NmrcvtGL/lBUeuYc+DxJaUwLLthTGD/85pNTZx+X4um3aQofuJ4COQi+0 DRsEamJV9hvae1TWm6ylH5z7i3xu9dTdG/5Gj7kNuBx/z5ICP8QGxj08WvtLOiKR4gW+4NCybGAU 4FS0uFZ1tZ52qR2/197u//sUFQND+QzoovUTjQV3igLDKD9YnHFVxzr5PUhDxQOb4Dv+cqqU/BMk rWVd3HPapCstyrhwaVpGazpZZDB8beewHx92AVB1qZ3bNb9CXYWqz9H2Fj2OXJqXdERhIPL+SkP5 aux70IXJO+oa06pCw/x7bJprRldp9ZUSxNWRhDeHe/wyE4PpZ39FxSwHB/mkOvXhz+kzTfU1J0x9 wxSvxPtoi8DophG2rrvbsfqmUjED1IddOMAaafspB/4iEPQnGKk19/Mljzp8MxskkMlsTXTCosUy 87QThuapSEbWd4ET90Um3bu/Qv1FdV1cpkD5ZKTGtoc0/MZ9ZB+pK+eP0RH6qQcsydoeYcsRa96R YOVe0Qwzd0snE832CGQJs8skGSuryFxQScdpdgQwYHcQKKgVY+XzB8BL8R4hxo0PPk3wM1kapJTc qMeiBdT18f85bGvWa7bNL48rHp6jO9kkEWP/8SsDofEXWfXVDiXGkyRtCzhabcQ21Bkp1uogMusS y8pkUvZBsTAfjj9qVz1LJBBhaxshB6vejMDoZ+euaXGqsgnSZPdmNFAXJtICpjoJgnTVcpZn9fGP jaMtdouH4blxEb/m5rQxghqD7XJOiIC1h1SRhX1AkbpzxKrzT/VKs/opkiAxnA0+sO9sEWADqnO/ 5tD73HbB4K9m0vL0i2anpeCE+lFklbda7pWjA/ZLqYAM60cbMLVFXolIJoGYH4kPgTb+9Hzf3w1m lpkg5jX1yAB/lJMHl8A+B7ylcRYqGBxsFSLb4Gg51LXB5CqIUFmlUQyfVbbyVVNMTi+tmeovF5HR GeU2RvPoXbsF7T0AVx+7QhoGPGDW+JDeHyhJuwidvvReHqGNSHvp7TX27gUlr/jfVXxveGPqf7zC mDZPaeHyvULsIuz56QzL19yryE3VIbKC0WetQPMwU/Hvi6aHaYTz0GL3/Op1Tv4qe/wOl6Ne1feM Y7Z+qa+pvNSx/UKRBvAy2NHXMvT7r6CJZEOdlBi0xVYa6t3h9ekI0N5hf9DMeNjzle1bJS7JV4qp 7yLZh7L6ElRN2HqJMzp/nTtAlES/x+vokk7LKHe3kMwlpKwbFWMn/gBRiWnpzDHk0IeidS2YYBK3 iPQr0qoj0v2jm3EGBOV/ljCwnqFuhzJg0kH9sBEpjTrRGs5JWl/TuoAHGza5Nv64Y1fyOw9bvbxc wB1KRRXVQ5S9tWv6+broTp8ZSIq2nGtuYnYiimqoQWt3psrduHSxpRHiZe6hogkURYxGkWSK/Wdf DkdV/4OZEcc4nHtp0ZPEEDXrJvUtn0sZkMTELNocWRUp1Rye3QMv71ZuRQ1Gmdgd4DIrh8KVqaPI qcKqcH7d+jtWFGZqfN5I2YlAWTVtzFAFEkJzzkv7GEifIKLPVB/d5L7nIZSjV11g5ZfGnqTi/OY2 1EJ8Fhx+9wZ8LRXfGPHe5AepBGAtWHqlaVDNWt8qxLbQYEL3NIhEMuZp5PtncGUfPhtr6mHtyIcT O8fgGxL7jAglqYzy2uIAYF48u2QiCDhfbvJ37CutmYL2ByNDspiZNpmZECDm4031Bfq/cO66a36C 0kT+oRiV+kmYvF7gsMqOUYxmfyhqYIprnWe/3YdsXUEU8qessYz8iEqVCApfmgkc/vpXBF+pRAQw dFHiq8eVuU2CklGKzaGHogce2Yy3LQHOs5cjADZFLYSNn2vJshzdsGyFGzA8B8MPHoi9Ydhvco7p NamDFyBYsP2S2J55bWl9KjpfDrBRF0xoNrFRmDh7dZJu8qdU5IIsQru6pP4um5lXw0sO5rwYFq9M hUmm+rCenOcNdOnAzMwnFP62ZzGYK+AORBIGerWFEsMYaJ7FW5VscWVjPE24vx8H0+gwvahq4IXk evzlQPlBujF5ShxrjuodHvQPcypdvLTKDuTA9z0mFYgRx3a/MrW1IZqY36JES8zkQwbGPW3ND1ak FelNggBFV7ISQCeiE78kMYmHjTrF9/MoT2BDmAYZyq+ZHzMLis4OE0WVHA/uiGDtyg4e6ZgBo2Ja /grwT5UU++rWXUF9IfT0UT4w2jkGFf/HKcAujgRP3gRVF+ri1ZCUzAd1hr6HyzneerJifkYVSl8k VJ21Vv5y5HYoNjA+p0dlnSVyYOYjc8VHfm8N7rfkJ7zUSRLKxri+msGaBp79vjScRrdAvEvlVCkU 04L9I4I0AK7gHhOsJSYlwBThnKJ2ywXMemTx4ahJBRUtlMTNEdbe8SBac1WLhMXwMRzDZwkNT/k7 0QdYsc5JR5LJGaeQU8JF3MUHwNh0IYxur/qedN6VTkyKOR0yZMo38hf3bXIuuqFtCpUn04gK++sX DGrM6C0t29urYdOKHi7DdbIrhA9nws7a5cMEOlzkC3sV0QuFC6Hq9Dvex6hp0D8AGuw1W0Z/Vsya Ojrlw05viG912+NtRo8Qy9fP4x6J4duslZnNuIxBP9yeMxHi8z9p2GJA6HVTTmUkHEMh0iW2f0KK i8va9Z7qUYDzYDE8jzknlVETws1J204cEZUZKGOkQSrCBhTo87qb70FsZl29GQUjhNBdVS3/OgXs u4QMBAhsNNFECfwY7hD8FNE4C1lgXtv7JNzGIFBYv2JP7iA3DC4bywjWPXcn9JJph+LDmkMI+X59 862q8Qsuv7Zr/eq7DQeJZUbof0K7D5L5/tlffVIf5gnBvZbPy0O06t3nZB7ksl7viyc0pOU5eZ7U WKwk+v3N8iAmaTIF3M+uJc0dFsio5aOGdEFZxP94sENnyllWU8dGZhLcxm++smvgmgh9bfK0i5gP fF8q5kP5Wogyl3/Pd0XJRJtqoPMnGPWH+tii0i7+zZ0biCUNYMgAoIGbw33JZtxYCHJn/hPTMHe0 St2nP+Y5R/7ZiTXF55VKlmjtxk9s/fmxCRRJw8fVE9musgbwDwwsdpEiogY7BrQHwOPTmkSuHBOq lSwAvUtfSGzhnjh/ICLMNNmZK51pNP1H9hXlmG2fEAwPdtFcWpWtfyHpNBThV0D9aIPD11tbmJC8 UCC9f9m/+fxam/IhuCDp6dS6cNHZWShu2JIkaAnaq9CgKTHvUnmAu82wrb/1u1ysPQqpU+D6CY+W WCXV8Peb/EBe0hG5FsuiOnJoQKAQ36GUBJi0XuNeLEfdIh2MbJIZH//eRua12nZS9LPmT2EKBXE8 iz7TuQwvysU3BaA6GMiRlLb4s//gklHPHyVoIzGzJGwTERh2EwVz8uim6PWkFS8gDd5TRhx6q2ur BbxpuHuePXJ3GMVWIHDt4PDBHYo9BUrIsM1dTrKIKLMNpZnZ+vLCMSIRtzuJD2DjzYDf+Kd80Nvy rr12vADGL9ZQ7Vu21FVQ+uGxslo0EAnCCa0f6oaMks/7f9TgjQzm2kOHocb06fVtOFlja8LqCWv7 qNJYQ1sFkYI4IGS6ueZuJxcRKG0VIDnx2vblcmF+fnf9TVASO+qK/y6tCVa4XkwsMyZb52/rKe3K MLGG9Y1IbJ1+f5B4tytVh/TclVuN/vtOQFx/0jUAFf58ozbLhXAafbKKhWPcfEJ2IMjdDKA/EKle IEf6o6FIQmNj+Fhz0Nn2kZDAq6ForyG0mFT6Cd2Iro0CR5iq1wfaln+RHwnK9ymsGFbNxdpsvTYu MSAoHn48ev/dWjwVkEilNBrzYsSH2my1x9+YnLMiDaysvWJYlO563pw7tCR+3b23jcKOFY3SLTkY e9sJiCtXrtbufXYTPqpyUzNcgdwlYxuu3Mlea6KEjXhxcX6KJ+fVxIEpftcg8xDldrL9sA+zdZym wrKcwl5Grtiy1Ah6BR4B3xSl2uOB6pwPGFMR0f+a0/W4ZY1yMsoE6nfzJpRXFV5hf6Uab17aC9qc AUd7xR1DsmMeymX5oN6rqPLUYU/thAZbvAlE+FT/MHY2lANgxffl3xFnpdXgwmfFQ4nwnBaVdqSv G16MqCHfnmnJ11ttklkjTcMAbyjfooMpsPP4YZ8cYfOckGoaGRdq/r1CZrKhMUahjvGRWplZLAPm Z8r5gZemcdMMdEemwHfiAsiEo8+Hn1nXNLmdGv8wjL8XVxksatLRXeamiBq+ftJjZgiiP+BGh47Y tcD9a5qFe1/BYVgh7d7rKCDHpmc3kA3RZ117jgqgAm8dE2w2iaaRKBjKkcV1+Ga2kOC8DvudaEC2 2KsHQQgmWZK9xKvRZwss/uL2ePIgyJc4XYYlPq3uwu2TitqrmOV77CX/Ge+3aACleuuMm61td6pp zr4TV+QOUQWkhWEEhImG48WrQn+41StjC+x9FVcIjt0WSYxw0CMhGAAG86dHGoDb7OivTMIl9XRj /T0cUGjd95JyW08xKpPTZPLiQVfJfAYogxCr90cFWZzRJfJHjuaCGkbEh8J567xvRiML4Fh+Jbm/ SV7R9hl3KbUB0ULXPdGJJKnPsQUjThGXnNgVq+GEncZX5OpDP/o0kg0wlFva7VLipRcaKYNHypYN bWBzLBGz2HXT1ILndG+/S/tjN482mnvpzhUNnJ4dhf9sN9V/d5oj6wXU3U7kqZgeiY2S/rdv88Ui avSHGD6lrb2ROUo1LMASl5VBpJo/COIlTwDFhkdnlfjctpgPIFL/NeprK7rWdMhhOwz9cPjkHZA9 +ZcHJPudSJoZSuNUuSjAEKSHsoj5WGWY/GFpey+drhKiUR64gD6+Z0GYA65+COD3lmxPWpH2lpna DQCQfvjAQTY2n1WyvAFAAlrBs1LMvQQeeOIunadv8a7/6Y/RKzWKPMtVYzaS2JdchIiTpmgdgLUL KVQuog1eqUmAX7hhLfCe05sS9qGROgSi0hUW7pgXzU8UcoSPBvG+m2uXnF92lNdO91Z7e9QcRpBQ JSICNViRbrsjcMI2FjGN5xcvH+cUEHKHvCrZGUS/3DdykkpGPu8FloFJ0vT6d/nJC/3pi9LSB4xc hbFM3bxtiLSlP/veE3TJooEJeKIKepnlH2L7LHnnEn36TxnH58HrTT2VS8rG8yU8wxiTankrTgdd /f7y9I+3p4K5TQ0XrmroqWPCpF/Og8KdQd2WGwZq2R2VJb3jNNhSYXlkUL0/SbqXgAgVBnrOo8nM sVKV5t4y0c++1uLAkw4m97bB7hlArhMyOB3cT/pkxEC8NO66GwasWGrRVxAWhRzRWZ2UrrzR/79k b3N3MnJOdYwNIC/ioeHig5qs+QKL2kZS4mlPUT2064T1CLZq0zE3rIEVjfQZfmIh6evh5S0cx/sm UKkLT5/Qj7eEnKSh1hVd62dRhJSzejVcBexj30mGPdzNwogo/2KUTEEBwFf1XD7eTRUQDJFUA1qX vIF4n8RFPQ057ZLM92zF5lt5cHwJLWOyOgTlMefqXSiBeGIg9OezmfK+qusEA1KzO5UazMijbqlk B21FdQBHPnC1pinO2fupqFbLOchWyrK2OIdonTBLAwYi0WYt1jIQPVfqrwHplj9gjuTMYXO1OMlH MHA7BGR3pLXWKDJcChj2961/emRO81pp0yXDlq5OSrqh1PRRxBIfLZ1lMX7306It4p4qQq954vqP xrmcaK7RFSqQy4YdHuLKk5YEf5i+1cmAM+oyt+NKeVjRTZ0NSIENMXKdq7dM+8gDPuXjBfKLnmDy 1YZMCkt9bp+KNeHllllqJVgxMEnwdLB59jGaTvOKoSUqrl7kRzChvUwiVmLwXn3Vecmb8LjsLRIl MD2sdl0ywAC5lNgkYKdCPsDq2k3VwQMa2TSWzf2zcdsKTUi7oSnuFfA4YTqY+tUq7p7iAE3w5vcT yaLd3auY7iN1BQ4vuFPXVi1aeolEBg8sPBPi4d1IFbyB1HU4bA5iBhP9hK1ZglfvvEh/1GZZGVEg 4V6K66H2Z5a2gkslxG2DePkJGaeQa+RqjZBdBUduQHmoO7nbFiJ7x8o4h7AXbfQEm5O79BZZb8Um 9BowGO4NldiMUYAahqrr+QbV2dybNovZeO5qVowNcUcCGxH7No6A8syyA7nXICAn3ZKy+iGicPdR b02OBoqqJCvrC13PLV3J+VY/5RQR916PXaUzsAYk9NbcQsEhhN2aB4zs2UQBwyILUD2L3StcL1fG 89MK3tqPZptJ1HKhGLSCSFeGMKpToSTg+V0IxzOSpebOeR6D/eHkvPi2q5/KXBnjS1Mn0eNLSLXq Z8eBXl2hg+vQCPaq7VIzWyqqoKanUi0NvRWDSXTAipLdte3DrP2d9cRMlrgDgstnbWEUQP7XlaEc lnxzSWMC+5EUqZN/ETrYuetCJxtvYfooNSf3ju8icqFiHQO42yQesd0AgKNXylw3c1uMgGj8EGZl IrBgG1P5sDk0xZE4K39Dk0QC4KLw4VBk1F/snr5qfy0E4ZmBCELBGSg9CIT/lGWV/HkiZPuITqkR bnlF8vXOlx1QXm0xlEvJQkC5xeNh7RrfC1jn5RnDJNezO8G18C2F0rr9ciHg8OIfLwjztYOnvuth DS24A1vlJlV4ZSrkO0B1PRsgLPs2JFJo3N28yjyWylPesxFHo9mPem8jYWLmxYX4wwRrniaDW3fB aQSI8X0c7V0Hjqs8nVAcvrkpfkacx9S4N9MfsgCzsm3z+2a2XHRU7NmvBiAP4QPQYca0pMxR789R fPhLZfyq0f1gRpivR77WLpDi/WfvDSkRnlVrHnughnZ57j7iF3Ikoo6JE0qD8/lPjt2S6fCM7HMi /y/zweh5v8KgmgNz7q1WUYLWXg7Tf8UjU1vyQU6ZDR8vwpjuAnOehCGH9siOAG8dG8nK07g1uX1o 5D3ENMlYhQF4RwpzGSqLQ8vT3OXQZcuSF3RTyjYjHIk6bYIvWtFQ0I3e6ED4dtD91CmeMzXLubt5 vViOk7QLJIntICUbKTok+NYaguesdd+mddb++tTDHoq6fIVGruZiSyGLwTuTLpqk7aWIhDQN4V5r pIE3GBId7yatJREC4NQlfz94OmeMmx6wxLuOIVtPrgemovGt4QQKHG8yFzWi/wIXOBAWadHceDRM RMmSElcW4Y/20iFej/rZd50ob2ar+RvU6horaC7hej31Ja2IcdbOkc7leReFJ3uAoLnZtt/H01Ep TQk0nsmus6DlMrteCWUKzv9FeTOJ0wEvc8zhoW71KZEEkVZ/FphRCzcgrdwc6XNSIkyOoe4k09A0 Thqc9KvW7ugX2szfwG9FyvuwdcIRT5ZUf7uZqtYAHykjFqANHFBPS5Kd4vt/QoCIO4KHEwa51Fbd IED9DNSXYeP1jH6ZGu0TyxYJuKBB1c93IGAoDopwk9eWRT9Jkx9cfoW/zCDzx+jx6XZBNXcICnxk OW1M0t8GpSR62LPV9YgyckEoEOb70ztIJoSPZGffr9K7698I4rE7h2QQaj6UWI+15yDrk58+bFCq dQZxaJUNNJBFBfD0mXXSbh6QMXWiVidhdS8mq52NUer4kQ9epI+nm1X0bnbnVWQlUIEY9cP90l4h legFwQFpfdEWPAw3LBHmfP0bLtdLaCfl6O8dtHhmFW0HERGN+kAAGWSMypHYLPunOQyGwAStygoY e4/OxVrggCnewT9gnXnWTNKTK/0q9IisoU/UxcRInWOv1KL0HzloNtjhh/USlnKo9fPjQE07ZUsc bD6GDoetyv7et+wlYbJbLcIVsjYEC+YacCZ3GB39JMsdBbF7NM/1SOWJfGSOvQn+Tfq2K/NgpecP bImfehML9EYv7DL7Wpo4ZsN5dkqCI/OjaGydbdlKQH+VtcaokyZ9rVmunUkzIFz6he33bctDrCPV DxW9WdLYt+sSuixTiYn3YzwA8Vpo5JqbEqOw93o3u9eyolcLzOKN4L+6YWMy4Ky1KfLM1ItsQN6K 2Jdy63tsW7zz5lZ6P6iM19E6OgMBpM6RpEJeAlj9f+Bg1Q8ogCl3Ii5FVUmGoQZm0e+oj174wXo0 tcHCzdBgr8GljEpf4gYxlGe4XYX0kbAn9tlm7hI5nreFqJPyYR/PZZEX9NQpZQOXwj6Xj/8Dlt9B 7Eh3Oa0kl4zTqfsDAxeoGKFZKmH19fnYqM3jilennh7op0PSX/wTscI130fmpF6ypH6HCwaFYapo Au65ABDXHHYIbkliVP8wz9QrDSayQKTwKJ3wyKR6ZwBuB16Aau2B6Dv/f5L11luUaOevHYHnMSq1 q/xSuLB19GH8opOVoH2VkF82I6z43+Jhzk12Z1IwqgLtUnMRQTIgYyAVPLeqSgyZHhUi/QwwnQOe alr1eGyvJYq6ghBsGHXG0+Djc9WbMB0wrPc4ZUS21BnU/Sw89hVjBXPBKHpn50Fs5Fd5DQYOKi4/ lchKaw0xlPPJPqVfXzBcBlqwQ4ZFU/sKfI6qXhEBJjCiyBOlcVydsuNneI2T0r7UjN+5CFOcp61Z H7+kLe1Es7ZFbOMiYrqIrpLj9HYiePySZSbvc16UasDXZO/L6Dsw80oxJ5b9ZX+q9xp+HcVMAusi DUo/1PSbt/ZTSUMIiWsVyuksDAq4n1+jE9e44d1QWeAXJaK4G34Kn3qAtJvJ3fpiSdhDAIXICMuD U6pdJUwhg/sFFu5ZLe1xe2fLMoJBZncFE1BGsq3uTakI04Lsbpmg5yA91mnIvfmj1A54HMXZ61K1 QJNHN1c/o3jSGyO/Zdxo3efRaQJNEmX7cRy8N1j/hEdoJu0p+60iFabSG28RPQwNHNtRtNO6YFdF RvZBy+MuMUPdDXXhrgz9kiRB52k3zJQCOG120/caZMRqzhaxMY5XNHTkZByLYFYNcu3bZqbgaSrO 8sf5hJpXd/rzzytAuY3eb4cNocMkrvEt+Ul5wFvzKVmxqrupSukMmBpxc80+QuTH7543g9mIRxfO TSYBMMvfpZgddCYFwlDs8FS9kf0QE0xHg2AS4G5gNzaTCczu0K6o7bNgBBSuLoknsnmAbm4vY9CA bwgstLN4t0dbar4y76HqwbISAjapsS0KG8Z9x7Iy6PMMODN5Rzbsyb3PaCau/2vDj/Rys0YdPQVX QBM0rJIYfMnFw8xPF0JpRs0z220sANa4acQPYwpcnascOokHB/fT1jGKL79JCUwN0wblhuWhHF0f 1Lr561UIVncpMkdHKgBIBu4V9JP5km1yjtcTJsmvtKIMojl8P2ZVjU/lh+mBKQSJ5Ug3kg8gXu6U 0Uju+glYpuvOxcETnyVG5TzGOzc7k0j08fep7pjjYbOaZqI5a/zUT/7Rw3xDrV7gCviYCq2hNTOI Hzu4qAJHzoGOho/aaGVqVTNElcThQDL0ffMHC3KT56TiMRIWsBKRqXu/kqKYBWC8sYCziUn3IeIO 16gxB7BUQDmAkHPrb/vNO1wMdFqYJZtDHvtI4Nz7Ha/On3aWCGFaKE60/qIKqcsBAeJmquKxLljI xFIiu1ZohxalFdpA9dD72UL4oufBIyAqlqEHn2yHlP75DP79urT4lTBiMFskpuCBVjoHYoLv7phl kUblzybTk/2X9SCh1u3Tguw3NaAeTOEpOmz5DjG72b0zmpSgbgmD1qPE8yuGlmgmFO4pch6+0COM PlWjPGj6DxxRhZ+Rr0hvGWoF6ns4ZHPqR+KsXLDIapnfYAphQ9T0+GkscrQTlBNRQJTCWCNQ1Ts0 Ihfa+jCVn+Qc+3k8uI7okqpOVQe3mcs48+8rIZXwaaS/JDfrYLhX9ueNnN+9A8n6UzwjBoIaJhSX VLLuo1MY8Vyo+zqmHsy9CFbZKLx1Fps6tppMvEq0cDkcqYVf+ocIcQKyrvBfHUNFHiHN8hB01+IH HaBEf/IMUo5qaI+AnQApNycB1D/DOdKvagn7/PYtD1Iql0KW8MryNwhhwx5bXFfb7zeew7HZGyiJ Qty4O+U2TqO+VZ+G+LXy4gZ+Ekw/eKC0kaWXndBOHfSUAu3MrBiI0X1Hhhk4xA6y/CBbFj6BrB/q VRCvSfGm3ZIilXTTZystj9RPOmtfzNfKFNl3R1L6TiwQFVl/MSJ4cfrP6LEPatsDuiwTRpelq+bU Pd8+YSZL8wS3DYy+HhoQxFPBCMxzMdxcASfhOyT1/gRKKDTZy0lQ32fK+vr/cVaWsQrz65b20P2v CjhV1W11R31DtJifYDwPVlYGZx24snXZ50jXV20B1MEmsnT9BT4+/CvG+P9/qN5kJ+Ud0y15A/EF rpPUzaOWvmsNxrTxVKHWwJV3zeUDKbivouKHSWTY+kQY3Bd4SlQ9jqhVRB+TknSKJWfmVYmRIRu1 BHIR0NiS+lJu13FdGbR/5SjEMxorvZlftGM4ndMbnRJchcXX9k0s5bQSYpHP/JjOfx2ZGDoGaWmu bNv1FatJayzojyIX9xfxZCUvmPRdPSlurKC0bEi5dIslRN4UCtmLNy54Ri2y9YWCMzqiSRsC/KQo 3rP5xZOx4a2MN5zTAj3vSlhEA0r4ssW9O91o0iRfnSJlurPAKAxoUeCZ0hMrL/aIpCf5yiySimjw DA9PFr889EDzY5XITw5u8MPN4y6K66laqLP7rw6VXiGUPmPhfaY8zXfncs2RfivDtTlPNDqiPGQh kWtsekdYT+KzMJHXci2EOcRMiCIs4V4ThUrmKIQik8fecJF+Vbb2HrCk66VtSh0TQd+zx8rQq9o0 1VyUE5axViNdK5voXhmZupeDYxDbImz7dZlla2qtN4WOgF/jCO/lH9cqWOgSkQ6fzxJMUyHktTIT eaIlf2nVRGKOo/ZWnUdYzWJgjQF7XzFbFAi76+bai+p420om268/S8LC/rLdyGMr1TXyaq9rcbL0 pvcY+maLzC5S0/4PbDIum9TjdBOhkrT3sLnN2/AOhnWq/oQeKM2F/smEVLwwXGkEQ9wo/xgb9sFb Hqo60F70gyk5dQPxVR4FT+pFfK91UoMgN1ij6kI40+fi5TwMHxhVqhccWTq0/QFdoGc0Av3CV4SX dSCvdbS64wqYsXdfAAn3+K7YBzzYYJZ6F2u6s0T1kOXFi5OGyt0i/Y/w4w4dLhpok9Ji6EU2kmXt WcWOIm0YjaqyMLIIE07Oi6ZSFOxVhel6hekNVp+L/rMNlCazfIY99x2iASOEejVPtCes8156I3sE 9UD00ieYm3qPhqdRA5ow0nibSIBTn4CBa3WWBGThnKZJqyX5KpZKVBrvPc/4KWUfix6h9jUHtXD8 Vc+Z/kGvuC1fOv1PI0BS8n2zyw9khQ3o+L0ul3Kz2c2Y9WWKstc16X6KA/KngHZbHfr4bj4/ZH5l z6k4+8SSmMhHXp9k97iITS6zf7CRnm3w9/1TnwYXvhCYXLUwAgk3K1ZswvYP0QTByshVflqdSOKl rKs/4FJRJtsX8eGmTad4XxB+6qx87jhmHfu9ng2PWgKkoKomU4uU6dLVKsYd/Kmp/Pb7ojpd5Gi8 9ArMIG0wn3UTTy5E21iQJb2wi3PlikRK2x0a4QfP5i9eyWSD88ASjmkbKbCoV5sSAXRJOetM1xeF rtfDkW/AKgNEQGaMf05rf5k7jSdSXctxKYSQK81m98WIrssEg/QeeOsIeAG4+N04lqtlE32wHirT xK8Ba24siz6H3ImgYgq7CwXYNBgmt40EQz0V8NR7M29nykeMbv6GTqNBVndVZQFyuYhazu6WLHUe DddOaBlXyiNstOXSjV2xia3Et2yZ4mCQOCShbtRHKQtoObLbTyOX/Xnlbrpb86U3iNXX7mLDwjsB ODlAxCY4Gb7hrHLoYy/qEHyrS/u8VBscZoyvZJR1rwBB6k60V2XkBjUjK91td2ALFZgJtXW/wyVS DTwadtsyo51lvqU72fDOXtmXfa6Z0mAwo0JefZGQ2dTDoO0LAvfmfhunbx8GLZGLBxV/g4axPwyQ VfXnlNOuLHlR8jbCwBYm4204BO2XvyKp0sW+8HWpvO0E7BX10aCK2WS5MtN/4vWO+LOQrNU5ZwKn OCuVWAbqgmIDn61syLE0Bb4p/7Z6B5c1SMwXTDoNW3uqWxDVZD3Tyr9F5xN1vhMA8XMiMME2nD1w tmCY/biYLE841TR+TNnGVykVpDIuhSfJPh9saDYfkARGgASgSKcvgY77gxD4yxodCGKzPrDf5fGr VVruHa+3E8zjge/rLHVGLCXMF4K5CRfumGD9F9DI2wf+mEgC68eBJgbcOnq0cSCaKJZH5pSV2trz N7Uqm4VX+KdfN+rFjag9U4K//7XSgq+jCz5VTRFHxxDAXTC/iIlgcX6keQKyzFPhZ7zkT7vfh6Bn w7tHHqDskU5oh+GmlQ4bU281OrOa68KTY2FMoztmYLY9msHhYZ7tF7XHN/2pU72xs5ezevkgDxAE U/KuaUpfQGNV3bwOWkH/nPyrKOpolG4WeLJ7PIziEpB0nur7XojFD37X7092u2dsKxDgtVQSQWrn CV/o1gUJJLbf2u7GCSqTyex6NgmA5qJiCbo7Q8rScE6lyt4EFBQm/S8t5IgdlUp6yDBeA1u+X3Q5 Q76UXPHfbvurOXfYMc5MBhaFAXmrS+UUXf7EMyhVjSyJ8KoduIC8fZtFPCRU3aoA/Ydo+hP040yr O7VLDx0ZCf9b3MKjjRuIB+eoNAomeH970V4LWGMZDGaBHLjzSXvv1oZvednDWXytNOgGmsJj3nna Vm7Doz/tZILHe30S3oLaQr6G4NzxOPnguocVZyw//j+QSZjl3h7iO3HgU0Mk6SMgZvAb1r0H6stX 143Vha3nuxpOUALSOLGgwyirIFJs+/FzhbMJxAnnBTUHYEwgdm99M9MYHLDWuaP5xxfUSgX0B8fW XaxMtaS4px+laos13Nc7pPjBvPnFF1Z3Tkv2/5iPSlW9lctZQIc8zsg5GJEyomtFdo2IwDJZ62pO VDYfK6n0oi00jHUzKVFpl2kACCsfQWTKEKKsNyFA27bgHQqjPneuBNsZxwxwQGO3angsn8fiESFK OUIE+EGZSOzQkZFAh0ursrB8wRyT0VeqkoKf6XbJvR5ewanxovYn3EvqxaP5B8OBNXd7IamzWAx/ 5J9p+am+5sehYGSn+EFA1NxgwDAajZmYcJ3LUk8fawkwXCSCgrC4oTnsxOm1eIISkJop2+qiHROz OzgniXRKGMSx1ZSKqtCZq3xEhNRJyZ0stuf2acbObeFc1avjlofHGCY15ubVzTEoY5fWzTqUixfg 7bOHXI5buPHehVQvgH8cA/puwnnS1nrEh+inNHOElBHqNQ+ePVvBHpdSTOfIkBR/UqrrjFcuvg36 In28lXcSlpCM4weNB64MljzVFKG4bCHxEIs2Eh1w1YJbMHQJxvrc6okgtoFQRCHfEMh07WFfQuff d0ozSg2QVmVYpq7KjePxuY/4tBbdxW9tddn/xfsJcrr7Si1JpdReOOj/IgHUpH2bEoQhwPqqhs8/ 7keU95k3fVdaUHri7RT8Yq6y3A9h0tCfYM+bLxW6nlGNMmXlnsDUAVvhLPdraX/i0mJpTNu65G/M 8kI7jfcP+z6vFCMahjkGRYcqD7yQG/BxpRfZIkPITvaQsElQ799qDEloofXxOWHnpk0STlbGFxAe g/OZcarXp1j4T/X+xCIUjrgQuICzGIJd+K981j8IaEk/WiQ2tsf48XFLZcRQAXHd88qb5pgbjR9V qfAVFU5NXFWTPBcOM/EtnDWCvwZNTCaJewlhurMSYJwRUKBVY933LdOwPZRHmkLlUGfNTFaiWTJP 2VTymv+aP/Mf40aipa9LVGQICIRO8prC87BcpVbZl8U+Uf7X22TeoNhPFV/+261Tvbotu+aH7PI/ J7cL0tinLzBXj4scBOsIgfmw4mq2Fad/rwqWpSm/j7fR1Q6OWUSimx/jrM4JtYo9BhYfNmlIfGL1 Vuo3vH4AWZ45pLqhkVOsyr58SkAkhQ7VbDEF+DWshluA0JwhuGLWIm4u84HiP8EP6Yc+tXYLXXoN QLp/i9EUUK+je0tImyiATLRSN12PBGvmI73/6Joc86krXTFY8XuTH3kI1FcEqZqm8ddT491dnPG2 fRT8rsJdeqiTt4gRI2Q6uRJWQwCFwzi5vr2uTL+ylTwdbsnkmcosDgA+/pW8ymFdLhEyu0L54wmH twaxDKwZ1oFKoyiuew9pBIo0WWFMx4FGS5rrPOjU10YItFD3iF+qZNFrDeJ9nuh8IfWRc0z41rJR 8rX040Pr+D/rGX7advX347iS6EXwn8OqeXvHwW8gGEenZpYd12Y3ZT+JT716rKAsU0Wc+OJUhLUf 3VS+ZGvBh/emjmXNUZDgpT/7nSOigPDywrzYf78EjIKlepy8RTE/btfOEXLU15/2etIKHkFoserh fLsnyLSmBboBXMA5b/pM1xgIilRYW1mgeVVQC/tCrHr8daXFavMF/R5/KXhbhZ9R5wCPtwAhaRGy 4wzZEAp9c9Z/OYLHC1rajhNzzdcnNSEOScVSoQRO2kYLUca4Rc0yVS/KeHZZumwX3YQj+IpEFHgp m8siyf1eMIKstxkF5RRLUDfO3X+/iXvro1vMDlTY8xi3m4Jw6iK5f2NIPZEyg2tlriSvy14i+8Ew 7SN3UHC59AchpNSDGkqheyntfrWv+TOkr8fAWzjRyMz3xSm4y7sEVCnZvJhXV4+yyi1jMNTPKDVZ 8EpbPp9Hx6e1poRlGzNhRNWCM8X+Mceeol69CRCDJXQqMUBArMPjt2ozn7tixDjiEDIdMRXwHboW mTSA3r1DavTfSEdjd/1j2EqfFyKlaqa0RJuBAF0GTXrQlEcPZgAMynYdXHtG3QCzBQ2Xb4UweqcN gJNArvzyBtwr+Etl/8lSPAqCiYx82ESP66oNfRbuAZVYr4rRKkX6WwrZdKtQraTR+2RSr8fxCHEw kK1Cmt7EJcMtp5PuVW+A/AdxOoTIr/Lu9MU6yOAKP85+aw/SnKLKSMEn80DWs4fqddk8t3fB/F5N Kt2RM/gVu2gtnHPGh6vl8lg7AbDUe27nmwvNXSUlg3VZapKif4VRyxqoHA9YwGUeLlmq+nUGCCaI 5fMkIBOoLBzn2QoE700GVoQe9CRFn70uxlQCxowdWfguAX9TXtf4CkKE/6e8HCLuVU3ypIvcniP1 2bgNHMxTnWqLnLVO6T3yVfVJiQ7RrskZZvTcnUSZQj4WVGQow8eiFMTYdBj/oR2tkyNmumVNpxQ1 gW+QfnAvAK2iDcdJEcKAhIv0jX4p6useZpaRCurBpwMDciiTtB+XRGDMv+lOYlL4kgQGR55aYD4F 5JqD64sZgn7ZjibPY/Gcj81ZNKCtV7/jbXWGf6GlAsYl1rSAEtipOKkfmLStkgCwPMYPDb0L9Qdw 3xxeops10j2xJq3TcNV616YEuXZ3eZVS/26OJOFPTI4gFdnsm1d8GOqXhbLbVC4J1viEugilZ6/w TPaX1L18YCSgBkdGMXaeTJSYWziikDcbhpytsBuH40a/sBlUGfoHeWN4Qap+DdQSiJfE9F2muAQ/ z0YEuIqHKJpG8dwv/Sbw0eBDMniT3YxxtFrK6pFL9SIeiozIW6qp+BmL/uSN60j/saXfIjSoYPdU c9QgQuotO9slJQ7RZNTGzazOlgqXtL36YsnoqMq04ggSvDrD7FTA635PwPGF2t3LYw5NT7+o8fJD Xvg7uV4/IqflMc24giOl1Aky+5pFsZzhFbSAPl5LY7GEsqKnhsdPuBXkMZ799P3EtGCmh9PDN+H7 ry2tusUl45vY15wB3t1g4W8iV2NRgeyWclKGSH/tNeDYZtPQZ0RgZdmWTpUscaaOdOGcB12bxBH4 UVusHliuLfELroWGXXnJieq7ogkbQBEJ7UL6p1r3tpBrevxiIbcRctRG22mYciqBJohbiky/ebKR 4MwA9tzxO0GGjbq8ex4c8hL5OULX4X9zPZl172JjKyaWfd68ZKY8Wh6zuouIOzPtSOdvCzYDOief 6HCQwlGaCZbqfkBUfKW7i7EySSIpYiTaEOpy/3TIQ/dNFHDYc3UWS5EiYgr8uUDOvhnVJxiJ/KFu J7+O+3M8AR9JRhIhuyXCuwfkFfv6q5PEJLNpj0p0W7S0JLvbn47F7B9TOU57bZYzUB1oTcT6hC5Z MkY/BNxiW/wiqRE9bg9yawCRtHekjEzjiCMBF+OWjeO+VESyojFXT/vzBJOOPuLsbJT/0qO+hsuj P0QugT5NlizTNOiarT25Jw9m6s35A5CyGV6h4tjG//AyZ5h9KDzo0mzOsT6Kr3LG1dPpB0jpIAh6 pkxKH0i7TOGoc1tPp4g+NP9KcycN7je44rRTfrCEDS9cxWSkUYKwhTOwAg7bEPPS/z+1lgp/yN9E IiPw6kzcBVUI7ibfG6RbR1r5v7TG9eeKmSLOLI5uI5bpaNtzamrTCOQUkuw3FgAPgU9cI87UdthX wX/D3Lo6Qzuxx17+XD2mEodkeDUnX1VB12AwQiD3FkxGpV40A49TARrVX2QiAiKkkAwJGs6RY/QE xw21Vi7/DzqlLrDaZBRxJDYRUZkf51h09YE/eK6wvF4v8hEdq1uRGbgtbWOuuQfgfUDTIO0kNxPo N/VdbHtCmTA+R9SJUCKJF4hvW/P2LqGrWRlNOUJHGF/4TFwTad2K1M4n9/byadmLui5R7wXBmqNO xEcGMyHxngHOhkTSO5Rm3Q6/06Zwqa/i8B16bP32UG63HG8q7ToboeiMmFt56okJaIaD8sNmNG25 RXRlDq8UD35EbOnqV85V1VeOecCtegZ/5dCm0uqWC8OqG7fChAX8BWOg2kCFyE+u2dUFB1Ff7UUb sNSQpTS0r/kxZGrPAIo6E8mp+gOAoOCa4Qg045m3G8/xb8Hcap8JWtTXnkm3/4E2aB9HpjkO88QD SFO60T/+qLRHF6lQL2YPmuAcEQpNPZz5nT9guJAuKJuISAtsVrj1WYcnZHb4ZSgVZ1sXPBCKELJ+ cttJ8ud97zA42RwhcSmuKIzn8S9jEqfa630X/LkVz9x0CsUO3ATnroLJIXkC555tTKt6T2w907uM 4jUDAkzGHhP0ZJBp56vo0I0C2XxOaTjVYMhUsedaBF6XIkOUWx0/KDt9f8++941XJyxZQyDS6b1I 2tEwmZdDd+KKFLy1w1K8lTg8eCN0HKKlprcxIU9XesJ7QjpmRtwnJoh7Jr0cls+duNzeNZC2lZp6 lprgGxlU8yBsBUMj9gNP7t2nl4PjujA+rnMu4g07yUHgcQcGXI1FCNc/MPISF5Q2in7PCimzwmxO Dn0bIPmcW1tSh0KtzI7cvVVVbCzRKJUxMtOauY5jLuDqNfnsLz1VU7082lTCOLw/ulyQOiEhZWbN bt7/tOtVhjkRKZaKk9VMqWtGrgfDJCVTw/8Ea7ntQNQLTFzzO3HjaQ3TsRmPmFsScq/iS3KnEVpj NzeViqfj1lDqW7oJMJVBDB3626XhMC9NPtZ0qktLLniOK08PX9nxtau2yigGOz5zWWVhs3lpnr5x UtWL6Er49WbdQ9RJQIFw2AaOQgZpPTSq4xUiaDUW+P1JhGr9FR+yMOJisyRzp4sBeoty7LsIccI1 u9mRFrTLu8HLen/5Q4N80FAsAd4sM3A/Cu+4d57kswWZH1yoAlmPwH2n3MW5I1a1WRNDpDsZzdUL h7aAPg4EstxJv370DxJLqGPt3JlJWjAFzq/DVQ6Jyv7u7cABmPJ4Ul9VEJk+DjuEwPFpOIfErjyo 2J1G/EFxQseLwAe0JIwbAU8B2IGl4MJh0hZoc0wp+vZSdS/U1AGelLuHMiUNMcnUH4eqkvteWZbj M0BEIq6AhHPVDbcZsQ78YN0S+UiwM0jYFQcfxmvrZcKlyQ3OJIeTWYuMOZQjL5z1BbnMFb8WOS4u JHdt+MR2QTLb9f3WcqU0quWqlD3ycgZx3evMMjThsLTs2vWb59hf6mIz1eImOkfh+AuGA8u39var Mqoo7OUgoFHL6TKfsiGJWtS6T2XbKYzJt01h861Plo9qyUHcC8BwukgJ3bueckPbBzwRDxaMlJii dQ+jewRw0dI3Vmzf6e8c8StYq7a7d8beb3g2Rhkaq1+vAAQ78SK9VCsS819L0PcLX/QbAzuPoBwZ sM81USz3b7t8yVq7xeCZIrZjyvXK59kkfcG8TSeddQnimS01dqZNY+mdTDD2nr1mo1K8eWA+P+b3 PCKEsfLu6ENGkxlZf0LPU4YR69EML7EotVTsz7bQOv7E+CN6SuULmBkpDxxRbxQc0bZaNwuQcyqL APt1DB0cbg/ksNhE+cKebUrpEjWe79I+6Yv+PuTjLzseVjVV8JdwNd4PiUZ5y1UsuJ8Qs+GkXx45 HXfvzZlmpGHB4Hq9RGkzkRkUF/Yu9aZjPQEnyue5V1QtKMjMYKOZy7yA2XNfDeSVHWcQt7Fd4ooj HidFg+iwZ5VRweoNn3orG2sRVTPhw7caYShJr00on3E/YTyDm9HggVzoEzvMKCIvCvmtYu44HO4W STlMCqGWt3p+Y9GR6dLUiOKNbYqSpJONon+9mE/ooipNxvOR416CE+P+u+Zb89Q8zKhrvZb6+UWS MjTFgfYskMOhlD1yPfWD63zCha4ZyiqQj21j5QKnTyWH+DBvqWGqzdQjOm7FDVGrIlAMTrroiiXU lrJe9aQteKkNgNpH+twd8T75cQXswH/92GhzAS11iTsbOs2flx07zpInSPN63XZ/ut1GFGPJMHFh 4t1gsc3A5mKtLH5bNMkZv7GBoCrd5nJXRdUBUTIo7sv7/FULN46AVnkqtgIwhh03nec5TzpEAHYE oSOsUC1p/w6KYbxCRvbjQeWsYO2vceuawYxtovkiRVeCiNf80MISVcKcjzVU73T3CjVX510WDSI9 +mkKJB34c6yOga2guW9lL+uEO+7qU6boXi8o326wC+vJbld4HehGwvJQJ6RXlz2r7V8hSEa8QuZE Ozslg/INt97O9nmhJmqezdzUT83C2QstH/WOzDOiaxsiBJ0MsR/tdE4v0ykZTjTAXv4cGlXhSAUB 973oKHVQr1RcOC6v3fAF8Yk2nZCA59NIqAH9lwrYddXnnD78r5NKIyKpKi8mFF0kiBxiWyhpCSD2 R/xK5r4o0fc/GfLlRHs/ulAL+Mym1PmG8xd4oct7wPNDd9r9c711m2gRz84FadxGT+VigWBY6oYW YFROMojC8P93GkYZdipVgcDYsGayDePJ3USwMASZFJDBTt0BhF4EKsQiG/Ty9S6YTGk3+SqUMc4F 5oVoldnqmQejPHNSHZ9GZDiA5Gq04PcMJ36D5ZUKZLVou+9jt0+kndpSX/rnOBeJKUFgUEV7LLj7 c2akGV9vKWL27hgiKuo/cser3S/kgtkpO9i+U9LLJXmZ1bFrPGDIIaafsug4L3x/Itis7R3siwge XO4MCVco5hq4zBkAbQrII3wRAve1XePsA57mBI0n6v3CiH0s+rl4uuA2xGyp8EbWziDqhmr1VeI/ 22PoI/yPYLOkPqMGu/aS93QxpOvADUkhxqadJ83Mt5uV4AX5gzGWKIycUhpF6esZaSUByZR2EYrg hNIo6vs7dPUYctWzj5s0HDHz4x4mSnf5BP97trXV3zskgISZGXL8rQV1Ryhe/m3cOsJfPGB0ssdc 0sFYwpru+04WBSdGQMBRsuCAJmDM0B8HxwoINPz75tWfYDVM62OhIhGi/kLHC4qWDTSTYLDjyiYe TO16rqFvVIyF1bW/CHNapo/AHs9+2CCPo/kBrAA2J3kPKqbMtAWnr0dGvegyfV14tm1osL/7FgAf xwmmdJg7vDRHcvu/n3W98hX+gKrTYZm6rORjZSxvLETmOY48YLXgqRx+0gebecn+HRyKkkvzJQqZ hnU3ap5Fr6GysCy+4b2W/I6fAITtIuD+/x3caxLRHf2IFBF3bp9YzX7nmwH0vlP5T3R4Rd+IqjL/ fllaFNeIig0oROZ7GKEOnkYSZ8jnAgMon1n2mxOCbfJE4kmLEgmzjR4CseEAgWC8N+uExLtCty6Q R4Uu1CSg9cvVMwQN4Lw6ACoG6U4pu4+3QOX+HprYE/h4eeYRf5MUfUCxaNqSkZ31bDPLJVNPsNLd GKZsEez24ZHeXV01K/1PZDB+T/4A0X/TX2LOvEelDmxRU1M1pL8Mx4ULa8+cUTsetKzsMXbWJH2Q S0XjQghEjtStnzjnE3RjRRGNlsjyYKUAxWmZdMKr43KGSWA+vEGGerKvV1F6EMQHQCR8zWyhGyWe NCEtZRCbmu5HES1IfhU= `protect end_protected

bsd-2-clause

a5bc65d2ebf2bf31e13db337e1b14f4c

0.954474

1.812371

false

Yarr/Yarr-fw

syn/spec/top_yarr_spec.vhd

1

52,161

-------------------------------------------- -- Project: YARR -- Author: Timon Heim ([email protected]) -- Description: Top module for YARR on SPEC -- Dependencies: - -------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.gn4124_core_pkg.all; use work.board_pkg.all; use work.common_pkg.all; library UNISIM; use UNISIM.vcomponents.all; entity yarr is port ( -- On board 20MHz oscillator clk20_vcxo_i : in std_logic; -- DAC interface (20MHz and 25MHz VCXO) pll25dac_sync_n : out std_logic; -- 25MHz VCXO pll20dac_sync_n : out std_logic; -- 20MHz VCXO plldac_din : out std_logic; plldac_sclk : out std_logic; -- From GN4124 Local bus L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers) L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers) clk_125m_pllref_n_i : in std_logic; clk_125m_pllref_p_i : in std_logic; L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N) -- General Purpose Interface GPIO : out std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8 -- GPIO[1] -> GN4124 GPIO9 -- PCIe to Local [Inbound Data] - RX P2L_RDY : out std_logic; -- Rx Buffer Full Flag P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock- P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+ P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data P2L_DFRAME : in std_logic; -- Receive Frame P2L_VALID : in std_logic; -- Receive Data Valid -- Inbound Buffer Request/Status P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready RX_ERROR : out std_logic; -- Receive Error -- Local to Parallel [Outbound Data] - TX L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data L2P_DFRAME : out std_logic; -- Transmit Data Frame L2P_VALID : out std_logic; -- Transmit Data Valid L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock- L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+ L2P_EDB : out std_logic; -- Packet termination and discard -- Outbound Buffer Status L2P_RDY : in std_logic; -- Tx Buffer Full Flag L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready TX_ERROR : in std_logic; -- Transmit Error VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready -- Font panel LEDs led_red_o : out std_logic; led_green_o : out std_logic; -- Auxiliary pins AUX_LEDS_O : out std_logic_vector(3 downto 0); AUX_BUTTONS_I : in std_logic_vector(1 downto 0); -- PCB version pcb_ver_i : in std_logic_vector(3 downto 0); -- DDR3 DDR3_CAS_N : out std_logic; DDR3_CK_P : out std_logic; DDR3_CK_N : out std_logic; DDR3_CKE : out std_logic; DDR3_LDM : out std_logic; DDR3_LDQS_N : inout std_logic; DDR3_LDQS_P : inout std_logic; DDR3_ODT : out std_logic; DDR3_RAS_N : out std_logic; DDR3_RESET_N : out std_logic; DDR3_UDM : out std_logic; DDR3_UDQS_N : inout std_logic; DDR3_UDQS_P : inout std_logic; DDR3_WE_N : out std_logic; DDR3_RZQ : inout std_logic; DDR3_ZIO : inout std_logic; DDR3_A : out std_logic_vector(13 downto 0); DDR3_BA : out std_logic_vector(2 downto 0); DDR3_DQ : inout std_logic_vector(15 downto 0); --------------------------------------------------------- -- FMC --------------------------------------------------------- -- Trigger input ext_trig_p : in std_logic_vector(3 downto 0); ext_trig_n : in std_logic_vector(3 downto 0); -- LVDS buffer --pwdn_l : out std_logic_vector(2 downto 0); -- GPIO --io : inout std_logic_vector(2 downto 0); -- FE-I4 fe_clk_p : out std_logic_vector(c_TX_CHANNELS-1 downto 0); fe_clk_n : out std_logic_vector(c_TX_CHANNELS-1 downto 0); fe_cmd_p : out std_logic_vector(c_TX_CHANNELS-1 downto 0); fe_cmd_n : out std_logic_vector(c_TX_CHANNELS-1 downto 0); fe_data_p : in std_logic_vector(c_RX_CHANNELS-1 downto 0); fe_data_n : in std_logic_vector(c_RX_CHANNELS-1 downto 0); -- I2c --sda : inout std_logic; --scl : inout std_logic; -- SPI scl_o : out std_logic; sda_o : out std_logic; sdi_i : in std_logic; latch_o : out std_logic ); end yarr; architecture rtl of yarr is ------------------------------------------------------------------------------ -- Components declaration ------------------------------------------------------------------------------ component gn4124_core port ( --------------------------------------------------------- -- Control and status rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124 status_o : out std_logic_vector(31 downto 0); -- Core status output --------------------------------------------------------- -- P2L Direction -- -- Source Sync DDR related signals p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+ p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock- p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data p2l_dframe_i : in std_logic; -- Receive Frame p2l_valid_i : in std_logic; -- Receive Data Valid -- P2L Control p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready rx_error_o : out std_logic; -- Receive Error --------------------------------------------------------- -- L2P Direction -- -- Source Sync DDR related signals l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data l2p_dframe_o : out std_logic; -- Transmit Data Frame l2p_valid_o : out std_logic; -- Transmit Data Valid l2p_edb_o : out std_logic; -- Packet termination and discard -- L2P Control l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready tx_error_i : in std_logic; -- Transmit Error vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready --------------------------------------------------------- -- Interrupt interface dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO --------------------------------------------------------- -- DMA registers wishbone interface (slave classic) dma_reg_clk_i : in std_logic; dma_reg_adr_i : in std_logic_vector(31 downto 0); dma_reg_dat_i : in std_logic_vector(31 downto 0); dma_reg_sel_i : in std_logic_vector(3 downto 0); dma_reg_stb_i : in std_logic; dma_reg_we_i : in std_logic; dma_reg_cyc_i : in std_logic; dma_reg_dat_o : out std_logic_vector(31 downto 0); dma_reg_ack_o : out std_logic; dma_reg_stall_o : out std_logic; --------------------------------------------------------- -- CSR wishbone interface (master pipelined) csr_clk_i : in std_logic; csr_adr_o : out std_logic_vector(31 downto 0); csr_dat_o : out std_logic_vector(31 downto 0); csr_sel_o : out std_logic_vector(3 downto 0); csr_stb_o : out std_logic; csr_we_o : out std_logic; csr_cyc_o : out std_logic; csr_dat_i : in std_logic_vector(31 downto 0); csr_ack_i : in std_logic; csr_stall_i : in std_logic; csr_err_i : in std_logic; csr_rty_i : in std_logic; csr_int_i : in std_logic; --------------------------------------------------------- -- DMA interface (Pipelined wishbone master) dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(31 downto 0); dma_sel_o : out std_logic_vector(3 downto 0); dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_cyc_o : out std_logic; dma_dat_i : in std_logic_vector(31 downto 0); dma_ack_i : in std_logic; dma_stall_i : in std_logic; dma_err_i : in std_logic; dma_rty_i : in std_logic; dma_int_i : in std_logic ); end component; -- gn4124_core component wb_addr_decoder generic ( g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address) g_WB_SLAVES_NB : integer := 2 ); port ( --------------------------------------------------------- -- GN4124 core clock and reset clk_i : in std_logic; rst_n_i : in std_logic; --------------------------------------------------------- -- wishbone master interface wbm_adr_i : in std_logic_vector(31 downto 0); -- Address wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select wbm_stb_i : in std_logic; -- Strobe wbm_we_i : in std_logic; -- Write wbm_cyc_i : in std_logic; -- Cycle wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in wbm_ack_o : out std_logic; -- Acknowledge wbm_stall_o : out std_logic; -- Stall --------------------------------------------------------- -- wishbone slaves interface wb_adr_o : out std_logic_vector(31 downto 0); -- Address wb_dat_o : out std_logic_vector(31 downto 0); -- Data out wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select wb_stb_o : out std_logic; -- Strobe wb_we_o : out std_logic; -- Write wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall ); end component wb_addr_decoder; component wb_tx_core generic ( g_NUM_TX : integer range 1 to 32 := c_TX_CHANNELS ); port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- TX tx_clk_i : in std_logic; tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0); trig_pulse_o : out std_logic; -- TRIGGER ext_trig_i : in std_logic ); end component; component wb_rx_core generic ( g_NUM_RX : integer range 1 to 32 := c_RX_CHANNELS ); port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- RX IN rx_clk_i : in std_logic; rx_serdes_clk_i : in std_logic; rx_clk_locked_i : in std_logic; rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0); trig_tag_i : in std_logic_vector(31 downto 0); -- RX OUT (sync to sys_clk) rx_valid_o : out std_logic; rx_data_o : out std_logic_vector(31 downto 0); busy_o : out std_logic; debug_o : out std_logic_vector(31 downto 0) ); end component; component wb_rx_bridge is port ( -- Sys Connect sys_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- Wishbone DMA Master Interface dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(31 downto 0); dma_dat_i : in std_logic_vector(31 downto 0); dma_cyc_o : out std_logic; dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_ack_i : in std_logic; dma_stall_i : in std_logic; -- Rx Interface rx_data_i : in std_logic_vector(31 downto 0); rx_valid_i : in std_logic; -- Status in trig_pulse_i : in std_logic; -- Status out irq_o : out std_logic; busy_o : out std_logic ); end component; component i2c_master_wb_top port ( wb_clk_i : in std_logic; wb_rst_i : in std_logic; arst_i : in std_logic; wb_adr_i : in std_logic_vector(2 downto 0); wb_dat_i : in std_logic_vector(7 downto 0); wb_dat_o : out std_logic_vector(7 downto 0); wb_we_i : in std_logic; wb_stb_i : in std_logic; wb_cyc_i : in std_logic; wb_ack_o : out std_logic; wb_inta_o: out std_logic; scl : inout std_logic; sda : inout std_logic ); end component; component wb_trigger_logic port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; -- To/From outside world ext_trig_i : in std_logic_vector(3 downto 0); ext_trig_o : out std_logic; ext_busy_i : in std_logic; ext_busy_o : out std_logic; -- Eudet TLU eudet_clk_o : out std_logic; eudet_busy_o : out std_logic; eudet_trig_i : in std_logic; eudet_rst_i : in std_logic; -- To/From inside world clk_i : in std_logic; trig_tag : out std_logic_vector(31 downto 0); debug_o : out std_logic_vector(31 downto 0) ); end component; component ddr3_ctrl generic( --! Bank and port size selection g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B"; --! Core's clock period in ps g_MEMCLK_PERIOD : integer := 3000; --! If TRUE, uses Xilinx calibration core (Input term, DQS centering) g_CALIB_SOFT_IP : string := "TRUE"; --! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN) g_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN"; --! Simulation mode g_SIMULATION : string := "FALSE"; --! DDR3 data port width g_NUM_DQ_PINS : integer := 16; --! DDR3 address port width g_MEM_ADDR_WIDTH : integer := 14; --! DDR3 bank address width g_MEM_BANKADDR_WIDTH : integer := 3; --! Wishbone port 0 data mask size (8-bit granularity) g_P0_MASK_SIZE : integer := 4; --! Wishbone port 0 data width g_P0_DATA_PORT_SIZE : integer := 32; --! Port 0 byte address width g_P0_BYTE_ADDR_WIDTH : integer := 30; --! Wishbone port 1 data mask size (8-bit granularity) g_P1_MASK_SIZE : integer := 4; --! Wishbone port 1 data width g_P1_DATA_PORT_SIZE : integer := 32; --! Port 1 byte address width g_P1_BYTE_ADDR_WIDTH : integer := 30 ); port( ---------------------------------------------------------------------------- -- Clock, control and status ---------------------------------------------------------------------------- --! Clock input clk_i : in std_logic; --! Reset input (active low) rst_n_i : in std_logic; --! Status output status_o : out std_logic_vector(31 downto 0); ---------------------------------------------------------------------------- -- DDR3 interface ---------------------------------------------------------------------------- --! DDR3 data bus ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0); --! DDR3 address bus ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0); --! DDR3 bank address ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0); --! DDR3 row address strobe ddr3_ras_n_o : out std_logic; --! DDR3 column address strobe ddr3_cas_n_o : out std_logic; --! DDR3 write enable ddr3_we_n_o : out std_logic; --! DDR3 on-die termination ddr3_odt_o : out std_logic; --! DDR3 reset ddr3_rst_n_o : out std_logic; --! DDR3 clock enable ddr3_cke_o : out std_logic; --! DDR3 lower byte data mask ddr3_dm_o : out std_logic; --! DDR3 upper byte data mask ddr3_udm_o : out std_logic; --! DDR3 lower byte data strobe (pos) ddr3_dqs_p_b : inout std_logic; --! DDR3 lower byte data strobe (neg) ddr3_dqs_n_b : inout std_logic; --! DDR3 upper byte data strobe (pos) ddr3_udqs_p_b : inout std_logic; --! DDR3 upper byte data strobe (pos) ddr3_udqs_n_b : inout std_logic; --! DDR3 clock (pos) ddr3_clk_p_o : out std_logic; --! DDR3 clock (neg) ddr3_clk_n_o : out std_logic; --! MCB internal termination calibration resistor ddr3_rzq_b : inout std_logic; --! MCB internal termination calibration ddr3_zio_b : inout std_logic; ---------------------------------------------------------------------------- -- Wishbone bus - Port 0 ---------------------------------------------------------------------------- --! Wishbone bus clock wb0_clk_i : in std_logic; --! Wishbone bus byte select wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0); --! Wishbone bus cycle select wb0_cyc_i : in std_logic; --! Wishbone bus cycle strobe wb0_stb_i : in std_logic; --! Wishbone bus write enable wb0_we_i : in std_logic; --! Wishbone bus address wb0_addr_i : in std_logic_vector(31 downto 0); --! Wishbone bus data input wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus data output wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus acknowledge wb0_ack_o : out std_logic; --! Wishbone bus stall (for pipelined mode) wb0_stall_o : out std_logic; ---------------------------------------------------------------------------- -- Status - Port 0 ---------------------------------------------------------------------------- --! Command FIFO empty p0_cmd_empty_o : out std_logic; --! Command FIFO full p0_cmd_full_o : out std_logic; --! Read FIFO full p0_rd_full_o : out std_logic; --! Read FIFO empty p0_rd_empty_o : out std_logic; --! Read FIFO count p0_rd_count_o : out std_logic_vector(6 downto 0); --! Read FIFO overflow p0_rd_overflow_o : out std_logic; --! Read FIFO error (pointers unsynchronized, reset required) p0_rd_error_o : out std_logic; --! Write FIFO full p0_wr_full_o : out std_logic; --! Write FIFO empty p0_wr_empty_o : out std_logic; --! Write FIFO count p0_wr_count_o : out std_logic_vector(6 downto 0); --! Write FIFO underrun p0_wr_underrun_o : out std_logic; --! Write FIFO error (pointers unsynchronized, reset required) p0_wr_error_o : out std_logic; ---------------------------------------------------------------------------- -- Wishbone bus - Port 1 ---------------------------------------------------------------------------- --! Wishbone bus clock wb1_clk_i : in std_logic; --! Wishbone bus byte select wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0); --! Wishbone bus cycle select wb1_cyc_i : in std_logic; --! Wishbone bus cycle strobe wb1_stb_i : in std_logic; --! Wishbone bus write enable wb1_we_i : in std_logic; --! Wishbone bus address wb1_addr_i : in std_logic_vector(31 downto 0); --! Wishbone bus data input wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus data output wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus acknowledge wb1_ack_o : out std_logic; --! Wishbone bus stall (for pipelined mode) wb1_stall_o : out std_logic; ---------------------------------------------------------------------------- -- Status - Port 1 ---------------------------------------------------------------------------- --! Command FIFO empty p1_cmd_empty_o : out std_logic; --! Command FIFO full p1_cmd_full_o : out std_logic; --! Read FIFO full p1_rd_full_o : out std_logic; --! Read FIFO empty p1_rd_empty_o : out std_logic; --! Read FIFO count p1_rd_count_o : out std_logic_vector(6 downto 0); --! Read FIFO overflow p1_rd_overflow_o : out std_logic; --! Read FIFO error (pointers unsynchronized, reset required) p1_rd_error_o : out std_logic; --! Write FIFO full p1_wr_full_o : out std_logic; --! Write FIFO empty p1_wr_empty_o : out std_logic; --! Write FIFO count p1_wr_count_o : out std_logic_vector(6 downto 0); --! Write FIFO underrun p1_wr_underrun_o : out std_logic; --! Write FIFO error (pointers unsynchronized, reset required) p1_wr_error_o : out std_logic ); end component ddr3_ctrl; component clk_gen port (-- Clock in ports CLK_40_IN : in std_logic; CLKFB_IN : in std_logic; -- Clock out ports CLK_640 : out std_logic; CLK_160 : out std_logic; CLK_80 : out std_logic; CLK_40 : out std_logic; CLK_40_90 : out std_logic; CLKFB_OUT : out std_logic; -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end component; component ila PORT ( CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); CLK : IN STD_LOGIC; TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); end component; component ila_icon PORT ( CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)); end component; ------------------------------------------------------------------------------ -- Constants declaration ------------------------------------------------------------------------------ constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address constant c_CSR_WB_SLAVES_NB : integer := 16; -- upper 4 bits used for addressing slave ------------------------------------------------------------------------------ -- Signals declaration ------------------------------------------------------------------------------ -- System clock signal sys_clk : std_logic; -- IO clocks signal CLK_40 : std_logic; signal CLK_40_90 : std_logic; signal CLK_80 : std_logic; signal CLK_125 : std_logic; signal CLK_160 : std_logic; signal CLK_640 : std_logic; signal CLK_40_buf : std_logic; signal CLK_40_90_buf : std_logic; signal CLK_80_buf : std_logic; signal CLK_160_buf : std_logic; signal CLK_640_buf : std_logic; signal ioclk_fb : std_logic; -- System clock generation signal sys_clk_in : std_logic; signal sys_clk_40_buf : std_logic; signal sys_clk_200_buf : std_logic; signal sys_clk_40 : std_logic; signal sys_clk_200 : std_logic; signal sys_clk_fb : std_logic; signal sys_clk_pll_locked : std_logic; -- DDR3 clock signal ddr_clk : std_logic; signal ddr_clk_buf : std_logic; signal locked : std_logic; signal locked_v : std_logic_vector(1 downto 0); signal rst_n : std_logic; -- LCLK from GN4124 used as system clock signal l_clk : std_logic; -- P2L colck PLL status signal p2l_pll_locked : std_logic; -- CSR wishbone bus (master) signal wbm_adr : std_logic_vector(31 downto 0); signal wbm_dat_i : std_logic_vector(31 downto 0); signal wbm_dat_o : std_logic_vector(31 downto 0); signal wbm_sel : std_logic_vector(3 downto 0); signal wbm_cyc : std_logic; signal wbm_stb : std_logic; signal wbm_we : std_logic; signal wbm_ack : std_logic; signal wbm_stall : std_logic; -- CSR wishbone bus (slaves) signal wb_adr : std_logic_vector(31 downto 0); signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0) := (others => '0'); signal wb_dat_o : std_logic_vector(31 downto 0); signal wb_sel : std_logic_vector(3 downto 0); signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0'); signal wb_stb : std_logic; signal wb_we : std_logic; signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0'); signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0'); -- DMA wishbone bus signal dma_adr : std_logic_vector(31 downto 0); signal dma_dat_i : std_logic_vector(31 downto 0); signal dma_dat_o : std_logic_vector(31 downto 0); signal dma_sel : std_logic_vector(3 downto 0); signal dma_cyc : std_logic; signal dma_stb : std_logic; signal dma_we : std_logic; signal dma_ack : std_logic; signal dma_stall : std_logic; signal ram_we : std_logic; -- DMAbus RX bridge signal rx_dma_adr : std_logic_vector(31 downto 0); signal rx_dma_dat_o : std_logic_vector(31 downto 0); signal rx_dma_dat_i : std_logic_vector(31 downto 0); signal rx_dma_cyc : std_logic; signal rx_dma_stb : std_logic; signal rx_dma_we : std_logic; signal rx_dma_ack : std_logic; signal rx_dma_stall : std_logic; -- Interrupts stuff signal irq_sources : std_logic_vector(1 downto 0); signal irq_to_gn4124 : std_logic; signal irq_out : std_logic; -- CSR whisbone slaves for test signal dummy_stat_reg_1 : std_logic_vector(31 downto 0); signal dummy_stat_reg_2 : std_logic_vector(31 downto 0); signal dummy_stat_reg_3 : std_logic_vector(31 downto 0); signal dummy_stat_reg_switch : std_logic_vector(31 downto 0); signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0); signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0); signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0); signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0); -- I2C signal scl_t : std_logic; signal sda_t : std_logic; -- SPI signal scl_s : std_logic; signal sda_s : std_logic; signal latch_s : std_logic; signal sdi_s : std_logic; -- FOR TESTS signal debug : std_logic_vector(31 downto 0); signal clk_div_cnt : unsigned(3 downto 0); signal clk_div : std_logic; -- LED signal led_cnt : unsigned(24 downto 0); signal led_en : std_logic; signal led_k2000 : unsigned(2 downto 0); signal led_pps : std_logic; signal leds : std_logic_vector(3 downto 0); -- ILA signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0); signal TRIG0 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG2 : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG0_t : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG1_t : STD_LOGIC_VECTOR(31 DOWNTO 0); signal TRIG2_t : STD_LOGIC_VECTOR(31 DOWNTO 0); signal debug_dma : std_logic_vector(31 downto 0); signal debug_trig : std_logic_vector(31 downto 0); signal ddr_status : std_logic_vector(31 downto 0); signal gn4124_core_Status : std_logic_vector(31 downto 0); signal tx_data_o : std_logic_vector(0 downto 0); signal trig_pulse : std_logic; signal int_trig_t : std_logic; signal trig_tag_t : std_logic_vector(31 downto 0); signal fe_cmd_o : std_logic_vector(c_TX_CHANNELS-1 downto 0); signal fe_cmd_enc : std_logic_vector(c_TX_CHANNELS-1 downto 0); signal fe_cmd_del : std_logic_vector(c_TX_CHANNELS-1 downto 0); signal fe_clk_o : std_logic_vector(c_TX_CHANNELS-1 downto 0); signal fe_data_i : std_logic_vector(c_RX_CHANNELS-1 downto 0); signal rx_data : std_logic_vector(31 downto 0); signal rx_valid : std_logic; signal rx_busy : std_logic; signal ext_trig_i : std_logic_vector(3 downto 0); begin -- Activate LVDS buffer --pwdn_l <= (others => '1'); -- Differential buffers tx_loop: for I in 0 to c_TX_CHANNELS-1 generate begin tx_buf : OBUFDS generic map ( IOSTANDARD => "LVDS_25") port map ( O => fe_cmd_p(I), -- Diff_p output (connect directly to top-level port) OB => fe_cmd_n(I), -- Diff_n output (connect directly to top-level port) I => fe_cmd_enc(I) -- Buffer input ); ODDR2_manchester : ODDR2 generic map( DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" INIT => '0', -- Sets initial state of the Q output to '0' or '1' SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset port map ( Q => fe_cmd_enc(I), -- 1-bit output data C0 => clk_40, -- 1-bit clock input C1 => not clk_40, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => fe_cmd_o(I), -- 1-bit data input (associated with C0) D1 => not fe_cmd_o(I), -- 1-bit data input (associated with C1) R => not rst_n, -- 1-bit reset input S => '0' -- 1-bit set input ); clk_buf : OBUFDS generic map ( IOSTANDARD => "LVDS_25") port map ( O => fe_clk_p(I), -- Diff_p output (connect directly to top-level port) OB => fe_clk_n(I), -- Diff_n output (connect directly to top-level port) I => fe_clk_o(I) -- Buffer input ); ODDR2_inst : ODDR2 generic map( DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" INIT => '0', -- Sets initial state of the Q output to '0' or '1' SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset port map ( Q => fe_clk_o(I), -- 1-bit output data C0 => clk_40_90, -- 1-bit clock input C1 => not clk_40_90, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D0 => '1', -- 1-bit data input (associated with C0) D1 => '0', -- 1-bit data input (associated with C1) R => not rst_n, -- 1-bit reset input S => '0' -- 1-bit set input ); end generate; rx_loop: for I in 0 to c_RX_CHANNELS-1 generate begin rx_buf : IBUFDS generic map ( DIFF_TERM => TRUE, -- Differential Termination IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "LVDS_25") port map ( O => fe_data_i(I), -- Buffer output I => fe_data_p(I), -- Diff_p buffer input (connect directly to top-level port) IB => fe_data_n(I) -- Diff_n buffer input (connect directly to top-level port) ); end generate; ------------------------------------------------------------------------------ -- Local clock from gennum LCLK ------------------------------------------------------------------------------ IBUFGDS_gn_clk : IBUFGDS generic map ( DIFF_TERM => TRUE, -- Differential Termination IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "DIFF_SSTL18_I" ) port map ( O => l_clk, -- Clock buffer output I => L_CLKp, -- Diff_p clock buffer input (connect directly to top-level port) IB => L_CLKn -- Diff_n clock buffer input (connect directly to top-level port) ); IBUFGDS_pll_clk : IBUFGDS generic map ( DIFF_TERM => TRUE, -- Differential Termination IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "LVDS_25" ) port map ( O => CLK_125, -- Clock buffer output I => clk_125m_pllref_p_i, -- Diff_p clock buffer input (connect directly to top-level port) IB => clk_125m_pllref_n_i -- Diff_n clock buffer input (connect directly to top-level port) ); ------------------------------------------------------------------------------ -- GN4124 interface ------------------------------------------------------------------------------ cmp_gn4124_core : gn4124_core port map ( --------------------------------------------------------- -- Control and status rst_n_a_i => rst_n, status_o => gn4124_core_status, --------------------------------------------------------- -- P2L Direction -- -- Source Sync DDR related signals p2l_clk_p_i => P2L_CLKp, p2l_clk_n_i => P2L_CLKn, p2l_data_i => P2L_DATA, p2l_dframe_i => P2L_DFRAME, p2l_valid_i => P2L_VALID, -- P2L Control p2l_rdy_o => P2L_RDY, p_wr_req_i => P_WR_REQ, p_wr_rdy_o => P_WR_RDY, rx_error_o => RX_ERROR, --------------------------------------------------------- -- L2P Direction -- -- Source Sync DDR related signals l2p_clk_p_o => L2P_CLKp, l2p_clk_n_o => L2P_CLKn, l2p_data_o => L2P_DATA, l2p_dframe_o => L2P_DFRAME, l2p_valid_o => L2P_VALID, l2p_edb_o => L2P_EDB, -- L2P Control l2p_rdy_i => L2P_RDY, l_wr_rdy_i => L_WR_RDY, p_rd_d_rdy_i => P_RD_D_RDY, tx_error_i => TX_ERROR, vc_rdy_i => VC_RDY, --------------------------------------------------------- -- Interrupt interface dma_irq_o => irq_sources, irq_p_i => irq_to_gn4124, irq_p_o => irq_out, --------------------------------------------------------- -- DMA registers wishbone interface (slave classic) dma_reg_clk_i => sys_clk, dma_reg_adr_i => wb_adr, dma_reg_dat_i => wb_dat_o, dma_reg_sel_i => wb_sel, dma_reg_stb_i => wb_stb, dma_reg_we_i => wb_we, dma_reg_cyc_i => wb_cyc(0), dma_reg_dat_o => wb_dat_i(31 downto 0), dma_reg_ack_o => wb_ack(0), dma_reg_stall_o => wb_stall(0), --------------------------------------------------------- -- CSR wishbone interface (master pipelined) csr_clk_i => sys_clk, csr_adr_o => wbm_adr, csr_dat_o => wbm_dat_o, csr_sel_o => wbm_sel, csr_stb_o => wbm_stb, csr_we_o => wbm_we, csr_cyc_o => wbm_cyc, csr_dat_i => wbm_dat_i, csr_ack_i => wbm_ack, csr_stall_i => wbm_stall, csr_err_i => '0', csr_rty_i => '0', csr_int_i => '0', --------------------------------------------------------- -- DMA wishbone interface (master pipelined) dma_clk_i => sys_clk, dma_adr_o => dma_adr, dma_dat_o => dma_dat_o, dma_sel_o => dma_sel, dma_stb_o => dma_stb, dma_we_o => dma_we, dma_cyc_o => dma_cyc, dma_dat_i => dma_dat_i, dma_ack_i => dma_ack, dma_stall_i => dma_stall, dma_err_i => '0', dma_rty_i => '0', dma_int_i => '0' ); GPIO(0) <= irq_out; GPIO(1) <= '0'; ------------------------------------------------------------------------------ -- CSR wishbone address decoder ------------------------------------------------------------------------------ cmp_csr_wb_addr_decoder : wb_addr_decoder generic map ( g_WINDOW_SIZE => c_BAR0_APERTURE, g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB ) port map ( --------------------------------------------------------- -- GN4124 core clock and reset clk_i => sys_clk, rst_n_i => rst_n, --------------------------------------------------------- -- wishbone master interface wbm_adr_i => wbm_adr, wbm_dat_i => wbm_dat_o, wbm_sel_i => wbm_sel, wbm_stb_i => wbm_stb, wbm_we_i => wbm_we, wbm_cyc_i => wbm_cyc, wbm_dat_o => wbm_dat_i, wbm_ack_o => wbm_ack, wbm_stall_o => wbm_stall, --------------------------------------------------------- -- wishbone slaves interface wb_adr_o => wb_adr, wb_dat_o => wb_dat_o, wb_sel_o => wb_sel, wb_stb_o => wb_stb, wb_we_o => wb_we, wb_cyc_o => wb_cyc, wb_dat_i => wb_dat_i, wb_ack_i => wb_ack, wb_stall_i => wb_stall ); ------------------------------------------------------------------------------ -- CSR wishbone bus slaves ------------------------------------------------------------------------------ -- cmp_dummy_stat_regs : dummy_stat_regs_wb_slave -- port map( -- rst_n_i => rst_n, -- wb_clk_i => sys_clk, -- wb_addr_i => wb_adr(1 downto 0), -- wb_data_i => wb_dat_o, -- wb_data_o => wb_dat_i(63 downto 32), -- wb_cyc_i => wb_cyc(1), -- wb_sel_i => wb_sel, -- wb_stb_i => wb_stb, -- wb_we_i => wb_we, -- wb_ack_o => wb_ack(1), -- dummy_stat_reg_1_i => dummy_stat_reg_1, -- dummy_stat_reg_2_i => dummy_stat_reg_2, -- dummy_stat_reg_3_i => dummy_stat_reg_3, -- dummy_stat_reg_switch_i => dummy_stat_reg_switch -- ); -- OBUF_tx : OBUF -- generic map ( -- DRIVE => 12, -- IOSTANDARD => "DEFAULT", -- SLEW => "FAST") -- port map ( -- O => ext_trig, -- Buffer output (connect directly to top-level port) -- I => fe_data_i(0) -- Buffer input -- ); cmp_wb_tx_core : wb_tx_core port map ( -- Sys connect wb_clk_i => sys_clk, rst_n_i => rst_n, -- Wishbone slave interface wb_adr_i => wb_adr, wb_dat_i => wb_dat_o, wb_dat_o => wb_dat_i(63 downto 32), wb_cyc_i => wb_cyc(1), wb_stb_i => wb_stb, wb_we_i => wb_we, wb_ack_o => wb_ack(1), wb_stall_o => wb_stall(1), -- TX tx_clk_i => CLK_40, tx_data_o => fe_cmd_o, trig_pulse_o => trig_pulse, -- Trig ext_trig_i => int_trig_t ); cmp_wb_rx_core: wb_rx_core PORT MAP( wb_clk_i => sys_clk, rst_n_i => rst_n, wb_adr_i => wb_adr, wb_dat_i => wb_dat_o, wb_dat_o => wb_dat_i(95 downto 64), wb_cyc_i => wb_cyc(2), wb_stb_i => wb_stb, wb_we_i => wb_we, wb_ack_o => wb_ack(2), wb_stall_o => wb_stall(2), rx_clk_i => CLK_160, rx_serdes_clk_i => CLK_640_buf, rx_clk_locked_i => locked, rx_data_i => not fe_data_i, rx_valid_o => rx_valid, rx_data_o => rx_data, trig_tag_i => trig_tag_t, busy_o => open, debug_o => debug ); cmp_wb_rx_bridge : wb_rx_bridge port map ( -- Sys Connect sys_clk_i => sys_clk, rst_n_i => rst_n, -- Wishbone slave interface wb_adr_i => wb_adr, wb_dat_i => wb_dat_o, wb_dat_o => wb_dat_i(127 downto 96), wb_cyc_i => wb_cyc(3), wb_stb_i => wb_stb, wb_we_i => wb_we, wb_ack_o => wb_ack(3), wb_stall_o => wb_stall(3), -- Wishbone DMA Master Interface dma_clk_i => sys_clk, dma_adr_o => rx_dma_adr, dma_dat_o => rx_dma_dat_o, dma_dat_i => rx_dma_dat_i, dma_cyc_o => rx_dma_cyc, dma_stb_o => rx_dma_stb, dma_we_o => rx_dma_we, dma_ack_i => rx_dma_ack, dma_stall_i => rx_dma_stall, -- Rx Interface (sync to sys_clk) rx_data_i => rx_data, rx_valid_i => rx_valid, -- Status in trig_pulse_i => trig_pulse, -- Status out irq_o => open, busy_o => rx_busy ); wb_dat_i(159 downto 136) <= (others => '0'); wb_dat_i(135 downto 128) <= (others => '0'); -- cmp_i2c_master : i2c_master_wb_top -- port map ( -- wb_clk_i => sys_clk, -- wb_rst_i => not rst_n, -- arst_i => rst_n, -- wb_adr_i => wb_adr(2 downto 0), -- wb_dat_i => wb_dat_o(7 downto 0), -- wb_dat_o => wb_dat_i(135 downto 128), -- wb_we_i => wb_we, -- wb_stb_i => wb_stb, -- wb_cyc_i => wb_cyc(4), -- wb_ack_o => wb_ack(4), -- wb_inta_o => open, -- scl => open, -- sda => open -- ); -- HitOr ext_trig_buf_0 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(0), I => ext_trig_p(0), IB => ext_trig_n(0)); ext_trig_buf_1 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(1), I => ext_trig_p(1), IB => ext_trig_n(1)); ext_trig_buf_2 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(2), I => ext_trig_p(2), IB => ext_trig_n(2)); ext_trig_buf_3 : IBUFDS generic map (DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => ext_trig_i(3), I => ext_trig_p(3), IB => ext_trig_n(3)); cmp_wb_trigger_logic: wb_trigger_logic PORT MAP( wb_clk_i => sys_clk, rst_n_i => rst_n, wb_adr_i => wb_adr(31 downto 0), wb_dat_i => wb_dat_o(31 downto 0), wb_dat_o => wb_dat_i(191 downto 160), wb_cyc_i => wb_cyc(5), wb_stb_i => wb_stb, wb_we_i => wb_we, wb_ack_o => wb_ack(5), ext_trig_i => ext_trig_i, ext_trig_o => int_trig_t, ext_busy_i => '0', ext_busy_o => open, eudet_clk_o => open, eudet_busy_o => open, eudet_trig_i => '0', eudet_rst_i => '0', clk_i => CLK_40, trig_tag => trig_tag_t, debug_o => debug_trig ); scl_o <= scl_s; sda_o <= sda_s; sdi_s <= sdi_i; latch_o <= latch_s; -- cmp_wb_spi: wb_spi port map ( -- wb_clk_i => sys_clk, -- rst_n_i => rst_n, -- wb_adr_i => wb_adr(31 downto 0), -- wb_dat_i => wb_dat_o(31 downto 0), -- wb_dat_o => wb_dat_i(223 downto 192), -- wb_cyc_i => wb_cyc(6), -- wb_stb_i => wb_stb, -- wb_we_i => wb_we, -- wb_ack_o => wb_ack(6), -- scl_o => scl_s, -- sda_o => sda_s, -- sdi_i => sdi_s, -- latch_o => latch_s -- ); --wb_stall(1) <= '0' when wb_cyc(1) = '0' else not(wb_ack(1)); -- wb_stall(2) <= '0' when wb_cyc(2) = '0' else not(wb_ack(2)); -- dummy_stat_reg_1 <= X"DEADBABE"; -- dummy_stat_reg_2 <= X"BEEFFACE"; -- dummy_stat_reg_3 <= X"12345678"; -- dummy_stat_reg_switch <= X"0000000" & "000" & p2l_pll_locked; led_red_o <= dummy_ctrl_reg_led(0); led_green_o <= dummy_ctrl_reg_led(1); -- TRIG0(31 downto 0) <= (others => '0'); TRIG1(31 downto 0) <= (others => '0'); TRIG2(31 downto 0) <= (others => '0'); -- TRIG0(12 downto 0) <= (others => '0'); --TRIG1(31 downto 0) <= rx_dma_dat_o; --TRIG1(31 downto 0) <= dma_dat_i; -- TRIG1(31 downto 0) <= gn4124_core_status; -- TRIG2(31 downto 0) <= ddr_status; -- TRIG0(13) <= rx_dma_cyc; -- TRIG0(14) <= rx_dma_stb; -- TRIG0(15) <= rx_dma_we; -- TRIG0(16) <= rx_dma_ack; -- TRIG0(17) <= rx_dma_stall; -- TRIG0(18) <= dma_cyc; -- TRIG0(19) <= dma_stb; -- TRIG0(20) <= dma_we; -- TRIG0(21) <= dma_ack; -- TRIG0(22) <= dma_stall; -- TRIG0(23) <= irq_out; -- TRIG0(24) <= rx_busy; -- TRIG0(31 downto 25) <= (others => '0'); TRIG0(0) <= int_trig_t; TRIG0(4 downto 1) <= ext_trig_i; TRIG0(31 downto 5) <= (others => '0'); -- TRIG1 <= rx_data; -- TRIG2 <= debug; -- TRIG0(0) <= scl; -- TRIG0(1) <= sda; -- TRIG0(2) <= wb_stb; -- TRIG0(3) <= wb_ack(4); -- TRIG0(31 downto 4) <= (others => '0'); -- TRIG1 <= wb_adr; -- TRIG2 <= wb_dat_o; -- ila_i : ila -- port map ( -- CONTROL => CONTROL, -- CLK => CLK_40, ---- CLK => sys_clk, -- TRIG0 => TRIG0, -- TRIG1 => TRIG1, -- TRIG2 => TRIG2); ---- -- ila_icon_i : ila_icon -- port map ( -- CONTROL0 => CONTROL); ------------------------------------------------------------------------------ -- Interrupt stuff ------------------------------------------------------------------------------ -- just forward irq pulses for test irq_to_gn4124 <= irq_sources(1) or irq_sources(0); ------------------------------------------------------------------------------ -- FOR TEST ------------------------------------------------------------------------------ p_led_cnt : process (L_RST_N, sys_clk) begin if L_RST_N = '0' then led_cnt <= (others => '1'); led_en <= '1'; elsif rising_edge(sys_clk) then led_cnt <= led_cnt - 1; led_en <= led_cnt(23); end if; end process p_led_cnt; led_pps <= led_cnt(23) and not(led_en); p_led_k2000 : process (sys_clk, L_RST_N) begin if L_RST_N = '0' then led_k2000 <= (others => '0'); leds <= "0001"; elsif rising_edge(sys_clk) then if led_pps = '1' then if led_k2000(2) = '0' then if leds /= "1000" then leds <= leds(2 downto 0) & '0'; end if; else if leds /= "0001" then leds <= '0' & leds(3 downto 1); end if; end if; led_k2000 <= led_k2000 + 1; end if; end if; end process p_led_k2000; AUX_LEDS_O <= not(leds); --AUX_LEDS_O(0) <= led_en; --AUX_LEDS_O(1) <= not(led_en); --AUX_LEDS_O(2) <= '1'; --AUX_LEDS_O(3) <= '0'; rst_n <= (L_RST_N and sys_clk_pll_locked and locked); cmp_clk_gen : clk_gen port map ( -- Clock in ports CLK_40_IN => sys_clk_40, CLKFB_IN => ioclk_fb, -- Clock out ports CLK_640 => CLK_640_buf, CLK_160 => CLK_160_buf, CLK_80 => CLK_80_buf, CLK_40 => CLK_40_buf, CLK_40_90 => CLK_40_90_buf, CLKFB_OUT => ioclk_fb, -- Status and control signals RESET => not L_RST_N, LOCKED => locked ); -- BUFPLL_640 : BUFPLL -- generic map ( -- DIVIDE => 4, -- DIVCLK divider (1-8) -- ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) -- ) -- port map ( -- IOCLK => CLK_640, -- 1-bit output: Output I/O clock -- LOCK => open, -- 1-bit output: Synchronized LOCK output -- SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2) -- GCLK => CLK_160, -- 1-bit input: BUFG clock input -- LOCKED => locked, -- 1-bit input: LOCKED input from PLL -- PLLIN => clk_640_buf -- 1-bit input: Clock input from PLL -- ); -- cmp_ioclk_640_buf : BUFG -- port map ( -- O => CLK_640, -- I => CLK_640_buf); cmp_ioclk_160_buf : BUFG port map ( O => CLK_160, I => CLK_160_buf); cmp_ioclk_80_buf : BUFG port map ( O => CLK_80, I => CLK_80_buf); cmp_ioclk_40_buf : BUFG port map ( O => CLK_40, I => CLK_40_buf); cmp_ioclk_40_90_buf : BUFG port map ( O => CLK_40_90, I => CLK_40_90_buf); ------------------------------------------------------------------------------ -- Clocks distribution from 20MHz TCXO -- 40.000 MHz IO driver clock -- 200.000 MHz fast system clock -- 333.333 MHz DDR3 clock ------------------------------------------------------------------------------ sys_clk <= l_clk; -- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a -- write sequence arrives to the DAC. -- To avoid spurious writes, the DAC interface outputs are fixed to safe values. pll25dac_sync_n <= '1'; pll20dac_sync_n <= '1'; plldac_din <= '0'; plldac_sclk <= '0'; cmp_sys_clk_buf : IBUFG port map ( I => clk20_vcxo_i, O => sys_clk_in); cmp_sys_clk_pll : PLL_BASE generic map ( BANDWIDTH => "OPTIMIZED", CLK_FEEDBACK => "CLKFBOUT", COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 50, CLKFBOUT_PHASE => 0.000, CLKOUT0_DIVIDE => 25, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.000, CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT2_DIVIDE => 3, CLKOUT2_PHASE => 0.000, CLKOUT2_DUTY_CYCLE => 0.500, CLKIN_PERIOD => 50.0, REF_JITTER => 0.016) port map ( CLKFBOUT => sys_clk_fb, CLKOUT0 => sys_clk_40_buf, CLKOUT1 => sys_clk_200_buf, CLKOUT2 => ddr_clk_buf, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, LOCKED => sys_clk_pll_locked, RST => '0', CLKFBIN => sys_clk_fb, CLKIN => sys_clk_in); cmp_clk_125_buf : BUFG port map ( O => sys_clk_40, I => sys_clk_40_buf); cmp_clk_200_buf : BUFG port map ( O => sys_clk_200, I => sys_clk_200_buf); cmp_ddr_clk_buf : BUFG port map ( O => ddr_clk, I => ddr_clk_buf); cmp_ddr3_ctrl: ddr3_ctrl PORT MAP( clk_i => ddr_clk, rst_n_i => rst_n, status_o => ddr_status, ddr3_dq_b => DDR3_DQ, ddr3_a_o => DDR3_A, ddr3_ba_o => DDR3_BA, ddr3_ras_n_o => DDR3_RAS_N, ddr3_cas_n_o => DDR3_CAS_N, ddr3_we_n_o => DDR3_WE_N, ddr3_odt_o => DDR3_ODT, ddr3_rst_n_o => DDR3_RESET_N, ddr3_cke_o => DDR3_CKE, ddr3_dm_o => DDR3_LDM, ddr3_udm_o => DDR3_UDM, ddr3_dqs_p_b => DDR3_LDQS_P, ddr3_dqs_n_b => DDR3_LDQS_N, ddr3_udqs_p_b => DDR3_UDQS_P, ddr3_udqs_n_b => DDR3_UDQS_N, ddr3_clk_p_o => DDR3_CK_P, ddr3_clk_n_o => DDR3_CK_N, ddr3_rzq_b => DDR3_RZQ, ddr3_zio_b => DDR3_ZIO, wb0_clk_i => sys_clk, wb0_sel_i => dma_sel, wb0_cyc_i => dma_cyc, wb0_stb_i => dma_stb, wb0_we_i => dma_we, wb0_addr_i => dma_adr, wb0_data_i => dma_dat_o, wb0_data_o => dma_dat_i, wb0_ack_o => dma_ack, wb0_stall_o => dma_stall, p0_cmd_empty_o => open, p0_cmd_full_o => open, p0_rd_full_o => open, p0_rd_empty_o => open, p0_rd_count_o => open, p0_rd_overflow_o => open, p0_rd_error_o => open, p0_wr_full_o => open, p0_wr_empty_o => open, p0_wr_count_o => open, p0_wr_underrun_o => open, p0_wr_error_o => open, wb1_clk_i => sys_clk, wb1_sel_i => "1111", wb1_cyc_i => rx_dma_cyc, wb1_stb_i => rx_dma_stb, wb1_we_i => rx_dma_we, wb1_addr_i => rx_dma_adr, wb1_data_i => rx_dma_dat_o, wb1_data_o => rx_dma_dat_i, wb1_ack_o => rx_dma_ack, wb1_stall_o => rx_dma_stall, p1_cmd_empty_o => open, p1_cmd_full_o => open, p1_rd_full_o => open, p1_rd_empty_o => open, p1_rd_count_o => open, p1_rd_overflow_o => open, p1_rd_error_o => open, p1_wr_full_o => open, p1_wr_empty_o => open, p1_wr_count_o => open, p1_wr_underrun_o => open, p1_wr_error_o => open ); end rtl;

gpl-3.0

da8c79ff3bcf097e084fa7a24e9d0ada

0.516363

3.034204

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/xor18.vhd

1

8,446

------------------------------------------------------------------------------- -- xor18.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: xor18.vhd -- -- Description: Basic 18-bit input XOR function. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add default on C_USE_LUT6 parameter. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity XOR18 is generic ( C_USE_LUT6 : boolean := FALSE ); port ( InA : in std_logic_vector(0 to 17); res : out std_logic); end entity XOR18; architecture IMP of XOR18 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; begin -- architecture IMP Using_LUT6: if (C_USE_LUT6) generate signal xor6_1 : std_logic; signal xor6_2 : std_logic; signal xor6_3 : std_logic; signal xor18_c1 : std_logic; signal xor18_c2 : std_logic; begin -- generate Using_LUT6 XOR6_1_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_1, I0 => InA(17), I1 => InA(16), I2 => InA(15), I3 => InA(14), I4 => InA(13), I5 => InA(12)); XOR_1st_MUXCY : MUXCY_L port map ( DI => '1', CI => '0', S => xor6_1, LO => xor18_c1); XOR6_2_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_2, I0 => InA(11), I1 => InA(10), I2 => InA(9), I3 => InA(8), I4 => InA(7), I5 => InA(6)); XOR_2nd_MUXCY : MUXCY_L port map ( DI => xor6_1, CI => xor18_c1, S => xor6_2, LO => xor18_c2); XOR6_3_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => xor6_3, I0 => InA(5), I1 => InA(4), I2 => InA(3), I3 => InA(2), I4 => InA(1), I5 => InA(0)); XOR18_XORCY : XORCY port map ( LI => xor6_3, CI => xor18_c2, O => res); end generate Using_LUT6; Not_Using_LUT6: if (not C_USE_LUT6) generate begin -- generate Not_Using_LUT6 res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0); end generate Not_Using_LUT6; end architecture IMP;

bsd-2-clause

c17072acb9421830fc3ad935d452f40e

0.467203

4.144259

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/input_blk.vhd

2

28,006

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block SAh83CYn+CrtyHs0wyLF3VZv7cA1BH4CvBkoLi0+D5t++bHzQKzTaWdgRcQakBSVQfoCVQ57Dtcu /gfHTdwkyg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block T8mCWsTo81Bff4GR3bCqwHvlpS5llu0XD0bVs8KMe1b8xOVbAQ0tlBpPX+11PLa6S4Tx52HdCMid Ji4wsQAC0dlhvOCdo4vfSKwt2GCvbuSZRJuPlKEU9A/Jp7oXmp5U8qURf/uF8dZsM5rKIKAc3kLw TlxqVAsBXLlaKjJnqnU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block wmClIagxRVsaBkVFxQR8giGUjYRKy4pvBXPzDRK1c/MNyglPhyuQLTfRqM+MKzsZtJmI0/l4Jrhd pNGPM1aKVRbogyam+Z2c1W89AwhrDmK33fdxLDRxhlWU6IvTA9VJJ/G9TDuUWcZVNb6DTwluEs2N DkeqvaUTAwPJfnkFi1adjsfcAfp37ObxlIwiRn0cdVbSEaCu5zI89JE/Mod7sWEDKUXI3JNeYVZ4 MDhA//wl1sRLmOCHrR1kt1zebehHC7yamnc90ypwaek4BCme2p+7KZKI/x1kkr4tdcSNrQBRbhqu mWfoCod/aFHIygKeq7wmAg6IaVLn5XIdtIFEnQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OQDS5QzbdigqBbuTfyjXAHip3WhAej0wpUsGwXP4uTxQcjoiYdPPVW88nLKTBI8rwViYTb1vSM31 Amk84oATYU5rt7aKJNK5NzkyeZg2UJRCBWXipqQWWKzmOOUEi0DRNpDkJypYg2OUxfer/O3iF1yC ZkQatpBquyhsjRWeP10= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Xxex9T7KxI7m/X0Yh6PnC4byFdfdmi06z/WDE7fgqH/SJtIm1IQLBkP+wmsZn8Mq5Oz128ru1Rbp yMwjjLB52n+0J5ZAtaBT7Z2PPwdorbQ06n30Gyhtdo4YBNOIDMCXx6NjP8WMZaKyqrmgOaq6UIkQ lTdXjpXcdUyzHhJbj81gldXMApAc2PhhPO3SbFMTlgzLZl4rs24dXvVQrpRlS0ka+Y5e0SQCInh6 HujQDR5JuGdZYjf158i2Xvod2ds25NWN4fRyKciir7b+6su4DT1uYBGkl1MZ7JiEfaIe0ibAxp7i 261sdm9rzvRuiY1swfKdBZXfXj+RIJw5PrEu3Q== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18992) `protect data_block TLP/NXUyqvkYSgNXANUCkc+DjXpO4zDUJ0QmBRzzZo5I4eDcWHvP0yUoSjoCc4RvfWWK897ULGRc bPA/bSIJ031kSOnENR0Ka7A5ujtTt+EdNZytuQkJdHdIPQ1+7mjXC3HjX4xyR+mWIQ2NDqku40Xm 4Di8vJ+i2ap+OysgOP83RBTYDiRm0BSL3w0JAK6aDcS45IRAIIbxrXAz1hWydy5Jn/dA7XFOElKr PqEOGGsLj8pPfUHlJ6b4ygytRTafqToSCqhUaagpAz2+V2oo1XCn5vplmBFO8SuxCwXdHtVGCo2o 40RGsAvQqon8IDZ6xDtVxj1K9nPLAGwntFMKSPOR309MtoSh9VQPAiwiXJSG1hXtVL5mWCbk9jE7 52RKOI1jL/6d6XFNHNNtCIfLR6CK+pRp6vO8biHpV96Xuz93aOSWtnei9LANfHCT91960vrfCqfU L7Gi6cDo7+HlYq/5Pk/JSnrSf6OrYAj9S8stD91lgloCGKuBwwuM1+GYv8V8cZB5ionejRRdRegw NhIbJ6Z6hqkHJSoQCIEhWt1tU+Y2Z1e643bdXe7t87xfEYdh0Dlu/W4xduzZE8huPatzy3Q+zCkf CoNiBxzayuM+8fWI/Mz375+dPAbE4eyiH/tpWWP139FmFeW6EGqEgqF71jPIpRuNLcQa7UnWREpT a43wYj/BQtPThOFRAejk+2ZOSSYHi4Qa04CoXZSwGjwPawDJdojAQtSR99hLGlhmxqsZgK0yNbVH zVbjM1soCHh7bvQ7bX00Ghy2ONzWp1+MSxbZoh2O4FQco8GqCOND7FsNcwuz4O9d82K7Rcb7KUrs reT6TGPfO43ka5nWEnSupKtnr+Oaa0h//HijVdKYwhy00hRy87hLJLcVxAze8mBB/qOmP8feBAtG KWq1cHzaf+o85KBbVxMDWPgiT6BrF83KF1tTLCDLtUG7xqyDYHZqhwoXYTinOZguI7RrhK+R0R+c ucdRcfykN+3EYd5cv2E2FRpWnfNoGmM/GIK6Jsk3wUU+mlE4Aw7rCghsyBdENibluDkul7fEpvbp 0i0qyih0HDiLx/GsBTsGLCwnVeE6Y46m/D/w5mTmFSc0QvCZYmCvhyKb/omgP2lVoGYRwJaEnc6P mfs7BZWXAIDzv6Tu/vifZO5achgo0nxyCPNB4aTMvRGi2vB3csoZwMFI7hMpKyt3lMC1n83wtHMl G1fe9ohuuiNC4kUibj3dofTiRyp3PVjPiapfbqBAv1FNgb4uYXJAKJPQcC8ZrLasL2zCufeOX4tQ Xe/a9c3s4xKtdu4ymo53lCHKKf3sNpaJNu3WTiXfIPGquwuVhAJUvkR/DqNJz0R4rK6RUmbmruFQ g41lU5S0FnTnX3AEVt9x3II/jBT5uVHy+O7aFMWMnbhorf93CkXsC3MKW6FE3OZvrv2Tyv9FBA6u J8XBNq1h7BmQHv3zGgHtQ3W4F68WbmysfwEMmv7NG5M648FbjW993Ko7kbYrUwsxSJ4oGKLPe/ir ShoAn92AEt0kTbi2c6R0oKpFkWkvb9m6Dz8B4/YMeMP5hqgIiSD45Ug6yOgs/aTyd5Utmpyrp62H nqghC8Wly7zG9b8+VtST/XyJlwa3zmIhCqbemxRmXOczAgBIp0SJbacnyHJH57RZ6ZzCMGzITB3/ ZeIqXVDWEhr8S5uvmhhMZK7PX4nfGGCv5eV2zHQPotoTL52UcR46UeEtoVJSxhimewYARCI3s90d Br4zP15lkGkf38vGFu92y9UlzPo7ehV4dVU0nO0ZNeThcDEwQnNSa+RVoZ59OcmXiPcEVqWcERwl Bdc4HPkhifcIHOLZbINLOkq8aT5B18SZdbqidkCg0HGErOeLqLo7FVFZEY35b2Kq3yhfaMjQNmZy Cgtc0O537SRFEPR8RvWWXve18FWJR8ikuXYOZ6jf59aN+yQGaxAMZ71SX/4dItQ+RY9fhj1U8iTf EMZNIZ+ilS2CHpM/cSWCgtpNsmE+QNLfMKwImqhCC4nosqzeH3mvKFi5NCeCxpGo7cRsHja3kQYV yZIS6GjE4yVnAgRhxfYDUPEmnOO9ye8DG0SlVqrS1zC7rPLuGN8g/hRum8xUkcIFNTCsbdqpOalT 712ke6dXuk1uGPWfXJYuVQZDzHsyGW9lzfF6osONhD0zBWCLz0QvB9cVF2zqqWDIyEC6rX4PN4eg vWcBOKHHM0mrGdQKmuhD8mPQdryThpPFLX3hmHyrY+b2T/iW7+r3X+PtevmGBhAnCmU89hRFIkzg R/Rg6b9lpeag6I7bmdq1Cn9FffqEEH4+FitTN6P+RqsEXzCgbvEmGzYtuZf2vC7TDhcrKVLel+HC 3BgzalTdEA+D0Ch3DNmz/YSWyNy7H8cOv6BkV4kFKr4E2zMtS88JHnWi+I8XcS292u9GXuSDs+CD z6SoLmg2j1mYymkDJ/450GgqjNLj4ZhEA/jrCfuSQC6TF1ClqHKzyRPV711ZTTQ8f0nxrS9cQ3Pa ysqbKB2g3YaMXo40VuC5d0LojRxrRFJiVf1oNB+1ajLGOToPzhbJjhSCng6jROVv7hzJSQ6ppDzy m3PQw+PDTsYl5bDy977o70mIzYImuNmw+ZXyargTR55kO7CicROrr1KqHifXQ4UB3sSdewnhaf9/ ljFd7faXKTBPkXtgNe5jW5C63PBXOBvf+S+pMF2ebs3oejYMN+XRIejgRCwrUraStot0a2oN5MWO RNMNr3PC1IlL8VqQWSt1eZZdQx2vFzqjTwvwzksDObytqn4PWKrkSVqZxohiLUNePbcd6/+96iUr LsvwpaaKN4TiYh+yUZVE/86NPuATJyjQKZyoUopauULVMhjGQTjfGq/GV1xkLS3FxzDqkm8fsUHV oh9EyEgqarqXIn6IXIEW+XcOfRrFi4jQ0memTBxAd8ByFa4Yps2d6ofbLOiY8pw1bVNG7ECmO93o 3iIR6iMA0JTiJ8zCh/4lEExKq4v6lWXt/lTlJgIWS7lZXTJA0OMFd3XdZ25cp0LaMWmDphv5NKjt 0XF7xxc+Jrm0gy0QEqup6jN8Y0wvX02bNvhXZVXknJlmGZ2aU5B7vrRBin++sQQJw7bjo476luIQ PbBg54DLG81/iAaMG+mT1Ujc8UMCp2I1kNs7YCAPJ7Vw5/BLOWtoj9PWY8NqJlX61CKuueuxPA/v vJ+ty/uPaJeNi8BoNH2tbVxNe/CckNNewISpVKEB2MoM43cQ8R2of88vfdBG2q37TWridHZ20Wti EkFApL7lucFH/Pb2nkOQIuIKGFFFUYLyO46xr7IeYAzvIRnvlM+InSpVbYgkPZ5nI26xZCektPFy fvTEU/rQFU+Y/dzLON7wGJdsBp1ag4/B9L/UPxlt7wsZmdwH9sv8gCKaaQDdeCscXryqDWDKIsmH lS4HEgm4/uj4ai1OTbj8cKKoCX/4Fd1NT1TGGWGprhXQzmmNWULBInTrby76342tCFDXT0rIVnNY cYD2M7xcNlcqxbippKZSBsa/UR1mjrSPfQu3mZH0CoPhQbZTQNDQUXCpRqA2zji3V5he+wYWSjRz Go2UhK88QkMibIwbSwWDAD1+TaP2pnehbNFguMZ9feBK4iNGQZQWSsT9YUjNPvQBrcHrLelvDKkY tylbFSHOkfMCOJwWy1PyjcuyxI4yfufJQ31Z1OHEklGcvpPly44BtIX5Jomq3YJ5wgeIzf2ZLmq7 9ShUtEiLuJhwJ0va1l5BsztmFv6qDAp0DPc40lyw0FQ+MFRC1EPTqsHS/sVCH6k59osV54CVWiWU fdLbnR5FsbZRiMqNo3sK/nikkKsA/pSmoY6yhfD5vJLSf4M3LjnyOSUaQsSjvSFbHYzZ7mYvPJbA FYmmqdVRko+XVmZNpwrEtX6iKZwmLB/xobLTOVyXapIUj3ACZWQFHexhiUG/13+GV1HJABLhNqDH Z3UNc4jUayx59HZOgttVZ2xTit6rbcbyh2M9Too8in0QfEtD1+z0ODv7wB8CC32M7KiLNsMJ3DaW NHFlOw5bLPS4o2G9Sf4xZ/gSJ5om2bZg5qw0NetWXt03xDssx3oiPxW/0fd+PWI3hfHE7ZtRf2WL Yv5glGL5GBSkZ9UW7Y8VcginvV8u/btGPF16lwc1wMwBg4rLvGG0CB/G1qVjUVWXr2rzefI+5pnA ohhz6hv8o3oAOPgJhAaRfwlyvR9yFXCmWFXDJcejm2LdnqogorvwBsZruXGTmvMIDvb6HQP3Pxe0 S1ILuhfR5uWB6AIxHoudcK+zcfOoNoUPlkrXU1x5Q8NcPf0ENtVHn4Eo3y3muE81IEMNClJbfkn7 tsBJwDFtkdo2kgnZvll0kpznO1vPOnPAtpfaDUzIv2T8eYALJrWZQywWd390J95aw0UmMzul7lBg bjXy2YTReZCxUqEsyLiQAxWK/oSeUh/h3Bhhh6xL+BfdcZ7VOm2WguMXacwZci2z4nE78XdWEB7D 4MUu9U3pjgFqVLxVhKKVIkFrqVG34s2ccuZQr2aWwV7sx5vDHz4MJfVJr6V11qFsiV6+fju+PSrB fAJiPParhU7NRmbTD/V3jJ2WXds17UikIqujVLUa5sbUnBYS45wmQrZJapLYcdzoSj889br9D1IA uFg8USiCKm+/Tvw0W1TyCsHhgejnPoqnT5zuaSiXZ7DwxzcEdBEzohJbtKUVnY1Wa2c3n9xyPHaB A5zfv+xoDh4Lqb6Xn5+RmIDbjzm3I6MXXu5vErbKieZrrQlFDL0A00oBOTTdcCvmBVe5QRBmmahx m+0JPO6LDYrRlRwIX2F2K802V5ohikFCmgzxlc7sr8yaImzaUR72wtUiwfgOlNHJzKF+LlmOy5s/ IhCAyvTSu8Hf9Tqy5tNKHi26++5UolG6a0U0KyXEuTKMEuVN3kRZP3f8TSY369GVwbqcQcW93z3o 1nYzC0USZdyOov7ViugWNEdS4x70wwt93GkQNEd2gqHrKGhMK4M2tqqVCgoHRkvi4D0YzUM8c/mk yqXBPf4tZTCsuKBxbnRawwHbt0a1CWxZr7GoQ9O87f9oGiuwBbWSdyRh35/PcQ6GhGgZMKWBNcE9 aSrsUo1QJ+J4uYQZlQBXJWeqKKgtUR/WdBvPHG6QpYtzNHB6GqUoxJYC7iIG6hdijUvNUa0AuoRW lC8bD/0IKUJYROoSPSWm+wdFZGvdrncPovFHHo5P6hEbI/KO4tsvg2Ub0LsEpzS2+x+ZFXlsb7FB +e41E9BJfgVXWKiuJbOh6Wtww19gOWv9pweU/AVEqm/V5nMMy6X1GZWtLX71tH9GGEr/LmHUBAsR ABFPe2pSXX3R+w2+EHmW1YZK5OTq0M6yWBoNdcsDwBqrA/3eNTeCCR1yzbUIcQnJ89IUw/fELisn 7Loolgjl8trXf5Vm/JcWEL+ZMsm8Rqk9nX2wwMwDwPd6uSHUiyqhAJFP8UsDxekYh9iL2FQJqt9f 3r0oX96C/YyKrSpy0R/CsN9dSasfkkJiprHtLlj2gChHmMt+Ki4JOAfQSq79pJwgCik+zcy2zjhV eUtxkuHJuUDquJvVYE8cfR250H6WhfNoYQqUf8v4JqGNTm98sEcOoMEnVI10i8TrdZg9ZXm0QySP KfUqocrWvfH9tqAJH1P/yqiZuG8AXSTz9kBbTUKacrjBAtAAkJ3yPCv4b9NQ+SxGXmq5noTNSGeP ADsCV7C0wNhK6kB5lJAo+07DBgXcRV9E2IZyysQ317LboGicU6jZZa4oRnzYsFWxzCC992TJ9pj/ FZZSBSlh6cZXfrJPBI+t07D1G4M+9CmQ7xYDfAhr97wUyTvcOOu7VI12ibLY9CRstLHhRyroYIvC zVOuPMdqeAue2AXELr7CDzpHjbrlBtqUjmJ4YYzMpyEge34J9THivJLuXzJyU0xOQA/rCHmr/Uv/ VtXXWc4LJcs1DncMIPgTUcpn1vHeVFKLUaNxKcqG2UYXsmW/6HHUw4QlWoIcchE3kWPTkb0335Fp xp2CdMbNkNnijCdWF4dUcCcwL+R/ub5TsEjhTqbNWKf3te6WfHTbGQyGkuqKpCa4/RbOU3aRgLyl vtnIVeUtbfxwLPI15p3mVOKAjOFRYFQtuUrxDLX7xz4M+NRvZ9kobuBWEIrqjPURLaNMc46JT3qe K7FZXNCH+1Eqb7rSfPBBUSq0/GjPNybaVyRtJ46MYmdlUJteLLbNSUnkrWG2DVGwcgNUBSE0BV9k RtmUCOVk2fe/VkkFlygbKslthm1eEHkhyIy9Y6kRFRdQS+VbaGT2xarxvW9BQAO9UPgSmlR60gXn YLV0TfqnEIznX0rngNxkINVY9IqRcePYINtpOzA6gbIF7ESKV6e0ierC905a/34JMGUQJ8samM1F E4+s2Kxng0BCZEgHErhTq6EDHLSMGYdpKoU+N05tD06xocfCdDiZRY/u2LX+Srvgm8E1eJSXwNO3 vYDarFBkTzLMrfEDPfpBYQsOhbZd4GnZAXDvrOuik1XSo83iZwsYEcN1YUSVFO+FsbVafL8iiAqQ PHJ9M8j61mCmS1PDbvh7lxCmDkzOaeOw45GR/fmp9pPnmZzA+AFQ9HLMusYL8N95X+qGQdFWIB79 ZKRawQruzcHBW2PhZ574J0nwFvNIkd8rCxPSsmKe5zda1fp/DsbXr+YMHV6OyQ7jUubYHrtR3mMy Ypn9X9GlGSy5Vfh8b3S3ZyvpZfBtST7NkW5nU3av4UCFEHqpyYdiRnmX3+LXWx2hE61p6NmgxLju bQgppiPCB4D8lBxwg1s7qjNFVo4/ejn3HkZnkHG8oMMamnuZtMbx8xtYj1y37ol6aP1LTyIQkcv5 G3jyO5RKoj5qHrruZq6NyFDWQvpFQ9NlpLR4KE/G4IraNVBfUgR0Bul3LW5FFo0Qip5dCWttXhYW Xjm+RQnyZpZl/6fLK1MQfnf1oJtFVqTBTYZ2weZvpp+cTJgLJDkhxIzpEpfZSFH8j3VAdFlTQH/r MOBsNA975nmpskzF9TyVBjNIBaphfLSKJwpgk+xYUHc0yKw44c1IeULA4TqIUfzFyzrMly2ns+ib GkCMjbxsjOLuHlb2JNsR1w+SxTjRYn4BOGwyM+Bar8jXYriHCO10Ir5MI13GEfPmJTtMsmQ/G+qg 0Pv5j+kMSbC0/oIvXPhepX9Sf8PDGhbDJRGVv/emcuQfV8LKyFvxlvwX+TjpZhuArlaKOtE9XLuy Yj1e1tSvCXelPq9Sz1pixpPde6oF4nSJidVk6zTgLC+rbtbEF5IsZt/NW1RUg9o2fLl9C3C93vES erMO7dkI3uw1RVK2oQJg12/9ZkM50O35/FS3aNM3TDTVnQJQY/yLPMK3CgLmbVPDecucEX61F9sm EaGcgI/9c6V2sXQu5RolVIfziNYmepfXfGsa7PbPMTR5kJvjNK9ZlZWIrMU890ZnUv7c5wHHls9B ueHl7UMQdyd97x7vUClu0lWCl++nzIOoj9jPrpcIB6pb+XItMQC4NFomT1YQc6rtS6P+yw8eWui1 flyVimLomn/omGL61+nQjten7j+yWG/0hp1vZwuf31Iw4XVzf63AmUrLp6iBvXq/EQ13eoO9/RDr pEoFTvWT+bWvJauxv6aQQ8EPDraTnvpRjROLLBTMQoVRm4ggVc6tPda7fhVaHEOAaNQsyGDjDdkE oNRHbagYlOmAEnx3TbE4/97Sr1rpeMcZ/w5p8tJgx3EgSwOGHpN+bjExhhkCJ5jHdI3jrJYvWcmP b5AlhJldvL+KO+zJfs0VCtfQtMTQ3DyUdRZ/73tTbqhinO8vGK5W6BbHPPBd09kKUE6GWvIZnNR2 DrDu7y6WaX6jXZ3zfde5ifgolXm61lDoz3pQd9dvqCaY8EeG9JwOWIa9mgX5BZAyIDt8TzQp2LCP KwqfttoWw527tONR2fGsPdtk2FMJ+ypHdR1UGUv/43I+n5HvFLAQD/Dk/j17F0cReT5w7HetHcxm Dt7bSTjdGVMLeUFfDe6PElDQKo76EQbrx8N+5ARBKklGVNHCGfIXhqfo4UUy2jSlw1ZvoQKJpqZp aGhJuVmQq1OjjZMP2gdUwE4EnK8d8dJ2XUAUpUiEIPaJXqjLGztGlENO+wSjWicX5xF/Owsc+djS sxn4nKS9nmTynOfvgJVthRYFJ48P6ZpZgQfat8m1NLPZ0Pehu18c95l222TXuaYnkarXUQ1hFGKl OO55p4eZU6BQ7f9/KiQ2JJsJv5fDmkcjBL5AJ5QwO1Bosrc8+FV2YXUbwluNh5rs8QYGFS42U2qk dfuMeXi+NrJv20TLenXsL01wMg/yVbu/vMgH+gvYW+K2cFc2IDUq310E2XDwl2goj94oRysZU7fx si5xC48dm07l3CmnUfG/bLxaBNQobR5mdJ7ROWFBq3/TfJrRbKmOCbuYM3O+7ljKUkAn43c9mEm8 AT0aRop3IZG46NqSrUPHpADyuqIBxbl6Zv/we7z+ZTq7niJWNdEopPsJNTPQnceA2NQ4l7K0nMj8 Wzf/G/a4WDUORUq7FfOKrhg6o0Cy0/uvZJzFKv8/5QA/1PYT4zVxj22Fm5onu3q50zOEkm5xg5S7 q1D2WDZ/9kVssMM8/IAi5Ptd/QE+bYx/bb/gbG+oh6DpeW86AXN/63znbz/u9eREOgNoU0Lmw4E+ xrZaPD30KoRr6BheTrx54nzi86Knt8I4NxszFlUtapEz8ROKFBJoc6rN1Zu+/Ak743CDm0WT0GkZ ATYRHtd98Dkr+AiKgUrd3tbl4b44gx8SmjCE0y3ypTTUcdPgbrUL05kBjblA146snfeXQnqpASaW dwO5ASX05S/2BTXeib0LQ0zqBSs3/4hpb7DUePlfbeucX5lueEnsE04Na5etJJqSvletmVuw1IHQ Zuh5dWo8k2OWDzCnOTTx3t7+s/k/thFpRVzs6R5XDAp2an1ILO9j2nppK3cODKhHCxh1NBxSYB/r J3dRqX5PUq9eW9XsyjglaDajIMpdQcV68eEW1p3UY2t6fCv+8nYIqhDE/3EuE8fRiUSOXD1MXgtC vboIbPER54zgNAoW+b5dcbLB5kxhAXtDYSejUGf+YBpXeaOkNzT1WXvMT0PyG3keZVeKanKdYHYc I/BkH0uQ2pX+rJFxVPYceS/9jThE5Wd39Ji7xb2RBPYXPnclmUNRTldt7nXcWGmi5PvDE3B8BvH8 VsrhmDnjsGHcGFl7hqM4S+JLfmFMQGictCM6vD8SMMMj9IVkqgP+sTYbIdsj5QRL/Y0YEpOvOLWz tDJrO8nVECy9+ep5N6/PEOQ7bit2hhhaVHHjKu38Yebko9M2375owuZdfJ/XkIjDtqNyY+vZzEur VQBoH7h8EMGUDQUC5kPJQjBxPO6mMZn+Y1QGUr00bzIsmgy9QKhSAzieCaUtysO1ALd0bTOJMk9O w2OD5Ry4hr7d5bijqAejkcnlH9n/VDeNfJYmdtLmBHHjXU6jV35CAyYtpzpLvx4c01b0ORJNlAVU 5FQHvzeL0DV6Gsvdf3Ax3bwBmq+mL6RsMwwqvvGfZhYHVQE1qaFVkBFiqLjdRvevNmotH6a+VrB4 E8hvH3NUVhPiafaEL4CfyVAoP2iXnCSsIFvtfeZ5U0TxA+5PxHvpETsrGP9Cashv1W3CGCUaRZhs CHp0CLhraRoaNTUGVqh/IZDRAhKdwj3oRiWXsmMPKjJQ11Q0wTpgO1dPd+9/JUrA2vBDcQLHyvvW fWSUKSPkyBmnA0/CuFA1WHa4wxwArLXcWlkXYlAsrjBEp5mbqr1Fd11oewWpR0SUcsPXVq/UDOj4 FwgL03rfzUK5bDhvDSHT+684lKEMrxAnwG+Jc3zMkREHvO2KurBpxeYFY6YI2tUOjc1zhK0C0avX hJSUq0Z52aiSBN0yRIKg7TdabzsTmn1h0YzMxsKixKNYyQ9yZfFMSINYITZzG0HznV2Pcb6gI7Bc AEhbkRmmAZnvdajKsdK0y6q0XUaURQgyJfLhCwaV+e/p4mod7haw+MEQ1H+3723euqLyUch/+hNT l42zYGsqYnu70dS4l+6jxxlaQXbLKfQukRUNk+Eh8BEjc9CaHKX72iFy9+V8SBjX7kqboHkem1TJ QR/KQIRN0Qpw5crUf4xF6YE6dVz1U+/1gGI99S5gaaLKQ+j+ndlH4WT2D67cjhDU+Ar7qyXcOuA6 PpRNAWACIy6e64aLt1ZYbcrh7xtonlYQeG0/JyaYHlqRttLOQb9MPydh+4osuG3P7UImf5RBi922 PfSLty3H8/4lCvNfCPg5tjMmsQMMrLiK40nQ76y/cmgXF6W37UUDaUMjUOO56EfAuBePZpi3+c27 7LdDhN1dcUUVPcHSyzobJ/+eEPj0PTYD2J0/fsZkj7ZloFI0SHXZfjCXDh6K79Lrpe0Fz6QkCiDw fYIgzhXFrLJx+oRdYRsiGqPWL0aKJpTvof5RrZNCNrO8gCx5pOY51mz+pjY2z3u7sRSg5RKTBNrv mWkb8LjNinHrqDC9fKWRFwSLTu94RiXvJNXRJ/uEjOXdNNj9ep7yhgiqARSaxQ8hZh/zmfJrgxSf t1HSYBZiiGQvGGHW6SB4/mWzzSlHTU8d6KMCwD3jObh48ohrbshdmFQtSRmRuAX4t2ZM3qkfDUoj YOCe3ilQxqXbk6uTRll4xI71mnHzOdtnd8X4T69AF+ScIGlk5zcUEQhyY/TGG6h6TNlIW/oJoX5Q pz2G2msb1wfXAvFmGeuyxYEbewEF7+RFzA8qQb9j4sKwOTpvo03APziL/JHrlFkabzmJJ+Oa3ViJ NqDcAnjg9pUMzQLZq+GUImAi0rSlxnRrklU+UTJbyW85hYFAmam6JJk1sJApBqVB0fto+mv3dntf v2NjQNISU17k5cjCL7hf1VvDql0qbDf5pq6KUyqdS+fiX7EW/i87NAiue/LV70Qbw1UXLJUUomjs on0dC9F26KvM3k5F3721C8GwI17CNa5L3r9NcHPuP3OV74807HwLYjhhbGRHyVSX4ijMRn5Ms8wt iSRs1MZ0wB/PWBBnDxaX3noo9LpzG+kJTAYY8boICvP4OYMR2I3stuxDjK/OipvelH5pxt3cB0zl /oZhvON/1JVx9VBJPqedGP/EY0WXK+i7a/dpJQ0KCZCFbERTXgF5aczRR8k3awLlVSI7ScgNzFHx ZL6fECsZUnkKtHtOcFpiJegcKb3k38QdgoMIqmGScNisIsQKIfBgdEF1dMdiPjzZMrrmRnrxgkpf a5YOcdWkucTJBVSaydiUFvBL9MDOUwEqZqPsvFTRnHRtGftPiebf03elU7c0VUGpQKNtHBO2JRd9 Oocqn2bSLbAeYuwvgYZT4mxJAlFlEj3699siAmrr4Fm/lqaeYEBF1jY8zT+amexG9nNITC4TBxvb yfRzpdpR2DM2cHWke7Nip4RXtwaoeeKYBfCiMqtcpiMGz+AFS65V2ojelpqb8Kqd1bVSyZ6V6mAD 5+Y6G41ovgwf9FpPPxtDqeoT5w6daaf8+k5Qs7vxWP0mutj/vtJ5eUhZuarqFFsGdd/N17I73lbz KZIAhNmy1vyacwUxlQeWUS0mAJvYPhAm30w41pzK/CcizpjRA7thvH1boEwGws1fLd1FFLmk2Z2L C2BoA/537JRT8p30LNAjzGkDGbRvG+ei4KnZuP3eM2pLWCAWH4tOHR+Z6RxVbJt79sXmdPekh6ro RAfFRSUGSxBSpXvV9oW1vNCiwfWBlOIFh18evZt/xgyP3iZQdlB/nNNZq4qWdJvYC/P+TrbKxxFo et2+GFeM6prMhNu/xITV/mQjrw3G/Tk7dGJxCRuhd4JbPo6ax5TgvgmCEcMkyK/bont/+jBlAX9y dn+c0GK5e5aKq6uFtg+GaxdJvxLLsNHdkf8zIko6wElkYTyyv3mZauLZKIxsWsGgnzN71Mp/Lxjc 1CbPaHizwmUDluiCAoQtoWMzneRcChzgJLnooODGlGuiNkle5bF4qrRoapht54L25WqkELkLpQVg YbQNBKimGk+ImxJ2C5WwQa/znLB6ZYfK683eh/EbwaCTq2LeEMKEKABTOlYrkV1x2Vsjy0+tRDpz eB09i3hy/3yWTp0ykoos2lP6k9mA1qgkEbHKDRyd5T2zEhU/wM3iaGNVYVIEo687ogUhjHkiJXUE gNzmD+I5e+Tr1UVqom30A9XdwT24MSmMlK2L6TG81d6L6PWaVNWkCmuGbhhmfLKjb96j93EMNKQ9 UD7wW25kJuGjYoaD5/SvLMegcOMbOAz0DahS1Ep7SHWaPAibv1hyDfrEzktElDZkg+/LkNxq2Gfo +GeYWwu1rVPESyxX3gD9jUkRmoKET1lYzROcZPbaTk9pLWC5+6pEcO7uJnaFZ4T1ZoQhIWLr5T4G rTpLJVg/aAryzx6U6j7gvrMqwX0KvikcP7N2FMIST6gaE3dLQWt1faSUunWbztVpysnuYdRUXmLJ hOt4DAXFZK3vyVUJZKk0X4kCyRI5yhx+po88CgzMdVulJr0o7vnQBQO1mwWUt5GYapxfSJKlBTVS RmMia0jvQjQcmGTG5VZwAsVIrDf6R5BeGjfOv5CBMwi/soU2uZs7BiZEdPfTZXx+tpP55V0ITs0U eKTVy2MajaOOictn+FG622ELblsXC+vpleqFp5FKsVjRrokh8WFGrab4+xwcnr06JDsZyDCqezCB GQS5dio/NqtmQKzmeaRPRonpDH0ebRBXzAxZEHCTR2S2IAQThfphRqHJMssJHC7i5LJFm/JQJ5wG HQho8Hb+kNtagpkaN9hie2ZJ5eZIg6jzSFRZsQbbfdKGpn3MTA9QsK9cE/AE4zsquAyEMvtG+PwV ju2AZJeZm76vQJ4TeRe3EwFiXIPxI72peFgX/KO/dDzW74nA10ave2Jp1NYOCqKlnPCE3u4QmNaH OpnhTDyApv/eML/N5t3b0r5B8ScLeineM3NOl2rWNW9+Zs+FU8VdrL/3oToQCqgl5RcQAns4hblN ZF9UC7XrjdeLwSTKGbFnc20s8xvIuNd7esC6OCztglWB+/6NxgLep9NHL0T0kgr2GKF5oM2WZcvO uLyFL+Bi7DVg6qffCbGu00Eg1cSHmL8N+oj5YRfO1Z34XMUeJnmdMR5G1SWDeUMYejueXg7WLcDp fZfJ0qVCq96sF07C5HyKGK1vCy9qLKG9g/XENUJ7afQ7FXHgMX0ALpCuWEb7nFUtgQNgsjV6fd3H 988kYXBEEnqWhjvMA4XpxMGvXG2qAGKyp5/rONDk6nL6ftWekbYk2b6jajIsYOlKyW2SY6eiETYb zwm/kU3YnTktT0AqaET6YRmKP+7usX8vMgn545qqnFx2JFO8vZstK+dBlmYjEYw+58bsS632BS7Z V+dHWJPwrUaLT0leZP0pdPda7ErzFaEPWkyN4B+cbnveyR7HbRnwm9Pvxe4KLT1tv5pwdptzwzfT JXA/oj3ZGJGjvtbpkpD9600qQYCKqhwWKaNAqK5dko8WNcVY5oKuuaWEiqYGxUqsVFkXvdtILQZd guWIxWINmMslPxtBrfAkyEuMEeoy9m6i8RwKKxGXWOAl+ueItW0++KypicZ8N1T0iIokuLtCIK0M RFNRIcU5ODroYj3fHOloznTPDksbcvpU7hBcKI/ljmIZH5raRYsiHjhubjgzL9hu9rW++c347PuP Eb+oAGfIULqiTq3pgwFPa7kutPkMo6bMyrJIhkci9ZSJ/ABn82O5wj1dv97CRtycV3CjMRweSfwp xtqSNlv4NbYSPEyKg/nD4iF9PQcrPlGQdOkkS0CGwCKhklMObFoAOcOqDlHSpcrvxq8oV+oZHfo7 +6Gg7eq/QYeGSBKzkC9LTfo6yIdBLffkp7b1IO0eu37YBSeJn6D+REd5E2eKZ32fhCLT3+IJen2z didvY9MRnhQPfGxV/RGwz1W5q+XMdZiGN0toA9vD+aLoDYb0fDKBtgWXr0JPgoZ2tDkFyhvrtt2Z rW7rM8cfd+NLkOGDRmsoysa7/YgYPUu2cBOfK6msh1oEOufcST7uOr9zzw7hLvBFEV3dMY96Dd0w WPK6MWl10YH67O4wDHruKsAK0w1OlHqDRBCfMIvg57r/Wd7Y/jB52Y0kfGiX4GEgnZah8MuYBnFd ubKM+E1On0dsvV5EZkhc9UEnGZLg9r6fQ6Mow+Ie+e0ZkT6QUevn0B1P8V8VloF9TxB6BIImNZxJ kujSRi1ku+j8/oVpZ1m1TAPWiXSyTdAyH+YdGnkjhLZvrKQZrBL4Z1197COualvxgSoZBwYn2WbT ms+TscWiRoTNkaP8Jl7vSO1Zebnc7LU2TQwPlka0tRcy2foh8CtraRE6wX6A/tqogWQpb+btQtQy i3bVZdTv1bF8StGdEQtU8g6iG/ZtztTcVdfqFV/KJNRCe5jPg8aAvRXVfrsm9RFGK6BFp5Og/66P l9xkTzPm3+4+vQiUfkRQ72QQd69wetgwr0moVryb7/dmcogP5p/+TXViSzd0CftQ627MjJsxrS6l n7de7579PvSBNfAcK40m+b0NIsAIskjclt3cmbT44wQTs6d4d3pVdLRmINoqnIpzfc56Z6236J7H aHpBUqi8R9rlP1FzTBmkboxu0Cf05PTYmfjl1mQw9WeDob9dqiyH/9tMXvEJ1HzprTm0FOnAvIWP G8Xbi4NFNqPQkSfZVh4/NX5+dISX2IMCXjhvImCrGlyD+BOe91O1s+eHNfbBCNiaqNDzc7jRJ1Kt 2fIUlCayH6E/msVeknAuHc10pft++HUyudpd3vlUDDlFX+tmeUHGwF2LXXKOakU9oFboB2kgyMdq c+Duch5pcajpCehi3OujVkEXeJ0W2/2/cpV8BrcfC1SmV5dsGm21RDo90Y4rIxv61UIF9vw7BReg 6aEnf6KVVd+K8oPU4SFaC1SE9totav3VqBbCWqka8fw/Jh4SNAshJBN0RnEYTDDmblbkz0zA2KeZ Zf8HVM+dFxWVgZmV/qnHmlHfxzYLZMXlylR88rDXmRBpqyfJV19hzx88PG+BFSxUW8e1a9uRQmSH vSoTRFF7FKodhPIdm9lzOX85yZaBlU6ITQnhnzCqGCIQFrKpcyx9ck5S/EKXAX/XfoZQJnDLTAao z45JiKpZoXv5uDG6E/VP6OzZMD8rwss7wwJc0QAgYCIkA0yjh4SmfzE3F1JC6qNpnbHMFnXRLRVZ VaKZmD0BuZab4XTTlaiI416MiPMLDsq18FScwINFOp24r0qCIZ64FHncaIOgve2xtSiQOaes7LGk IL7ho2H/E40NxPWKjmtL7YJ/Tf2XBSLMUw71uKCMnRLkX+gYWs+xys0tE7jW6rvVe/HDDwzvo0bC AKrcl0nlujnI0uxLnX8rR1bJkk2C7rNt1ytSNFNw9d+AInx/doUsbez0KV+QGG57+Sae99UAGnz5 fk7RGNRFts/qkWpOy2Vkl/+ikkeOt5i/n5TWc/WpTEhup6UDiuceNYIXmA8y8KfCYAbH7/l7SeO6 AeyI8KYfxpQP5WXxFER8Q50EOvgcjV/zz601SP7J5EBZeEDyrkZNJBE9iABbn6a2bYPlnJH6CVM4 3826KrSF90z2QGrk77xEXbIrU0bCAZW1R26zvJTqAjMzRApod7waAybDf8OdOrt/6NG8sVBUCgA3 2MHP9EXNR7jV+zMlZyii9FzRbGrgfa1Qdz5acRU1V7cTdoYJqe9JaRpyOICMerImY57Uga9ez44n DL2bwB6G1kg3X9faLr1+dtrK//nNQxXOoCNEgCY+mpLn3Kns1jtFPCkQycxy7q7aa3G3ioG2Gw26 MhazwgQfw0bgqscc1ChTu4ZhgTO28qSuygBfDf4qVM6mLcgOA2EvSML1A1C9xqQDph8HkU+qSN5X ASfXdwC6fXzG5NWvkZhVtS37FqaGgypNwqzwtLeqXtAai5I/ZzUWS1Jxjcl4jCaCFVbQ4vLekTfg T4Sg6O7ip/x+uTtjp7XAuRyl3qcq9a0t87mQpRlRhowoAeWFPHjnJLYGCnWc50g/kCzEVMUbPjQh nb919dqRx0XO0+wYMqpWYtky+qryd1af+6SlIUL5BwzhOP+WfHKhHrAjr/CbiOWjs0SZRpCZvqQn cAGHBNY4MsOE3z8OwAWQpKbiuXcL63ZUhb2tpEHjH/xh5A+D95nkgBI+W4phT5zkH/tUFTo8vAH0 Yr3V9rLcQibaq4ColEWDvwOmAOPUiAGVwn6buwxFYuVMNJ1pjxNEfDThkzXh+4DLsqIPBkt7JhRj 4Kp0Gua+YEerg3x4Xu+A84uF/sK+Mb/GcDCMdWY5GchNlFlBJ4/N1jvLaK+EubtoSOx/Ok8F0X+U P+EgWIV/tPp/fpaAgR1ItFKvENDifPuigmzQom69K0D8Srk9Dhi4lVwImBwxZZ621wRlDTaoKZZR nwLXvJwy/sn45jP6AQOInVW0W5T8ichsDimQVdq47rFK3xhLLyBfpOFpmnNZ9YsQqHMLWhoGF7zw 7D8TqbYpL9/Qo6t2c00NhshHO7o2JQisjy+cyMVhGujLWv6inqiayJ/YQhhD+2mc/D7QaCdMByO0 FlnVTzuRLIMoAhZ7fNAL50HJTu/0diejZdN0JPd1LZzCB1Lrllc/VoFxmGwMPpCS/1c0lLgMKrCM IN2SU6lcg+KS7fpKSDhVJgnkVXJwOiaeIS3JVbSpAoFcKqRRnUHNIcjB7rtMupMRdf6FsF/X+RO3 VAzIjHj8ierPqNWgODbi4ROL15pcS4oHkvSdWwpE0fbHuBKot7tfe2BUTjL5vjbGxQsTmikuig2h /3ucKsytlldzqAP46KkHKtFagJR3PAdid7528wl1GHc9cW+spFd01hwRoHnIdIAfxDQE1RsHn1TF xLgA7L5/i3T4YVQ2sWrJuAAwJj9A+w7QBrll62+a1QLseLoXcDhlbIleQ6f9YT6/nMHAkKWAuVgO eT3R1MUqHj3mtIfesVYjMfgWv0KgDfEld3xdTa7K0HN2fctqn3ClqFnmyLz9/ioufl9UZvl9wYfW h9VAm7wMybTgg3xRCHLwz1Aef+Vcoq65XCAd7dmHTJVPRW4awlrG34c7NE7O2QrMo1fK8tM0PyOc Ks/YvRNUqhsiEf1AEiCTLgS6fyY1m04E7k2HxlJoUAgAov8EMR53gGWWglXlwcwnpt6oIbFAG/Am ZitNcKBsHQBESX4ai9ZuAl1gxIRZpjDs4PBr+7ZyriAfASIUMTfL0us6cxJKbbRk1WimS92IxLFE qmTD4vZA2PF7k1ihJbF0wkWR7GSX+MY6sp52foHzbatbVyF+y5f431jWiO/ZW/MAiiX1dkvHISov c7awrhIuyIJQygBxA3Zn4ZLz/5JDvhZfODGbJCCzvWM5MB4hz+UoP/Kmn12AKt5nFy3HJPmtlm/c 0iMEf0g26gQJgW+PlgeA1tBnlLMokzR5e2YtNCG9FlLCYVcUuO/P+YBYpUwQD3NCagrG0zPgIWJj YrcI1auJfp5kK7HblncbtkLPtsMiepuVaFRA9yOQon5IbxTSurRg68DEz8xjp7G5p8JJAFvgBPXR IrGZ4sNv6FEoXWx/2UpkJkX9GL7dci6d5sA4orugFJqMg9QXpEg+My+CBQsS3wL21TpxiF3e6djq LMdEGACRg17hUPamIaLWZLO9GAQiQpfbZpECXeO7ucf+po/b/U5KtAxtbz+itwo77p7neU3BcDMw hrkFeoo08rA4qFInLBtvoctfxo5eRv9Icqo7mE+UeuuNj+rw7f1bPgmcR9ZojYDh4EiUWtRQYJoO Zz0iZxaQhDomffL0kzzHzOCsLM4sZreRFGbbjfHd/6EUjbOMU/6zOzRQEzsOQ6B3ipONVfzGv7L3 VzdL07McKo9qCjQe3HNCqDdfs17GWrjzuNnNuVDgk7XuB3OKncZeIb6U6u7xWdvWy0g6xE9wnEp9 kWzVArwT89jFqqLvB14v6cZvq1KTZYTSjfOuv/t1WmeaYoOpl5F6xUkxGVw1x9iz39bpVNsHtPRf iqZJqaiYjGTWpuj1tGvVk3qSh4d1f5oPFV/dzglmyA/QbXS387la/lUYXROyfeo7Vu4h28kvUgKf 688tRgMRCU3TkwTkdNO0cSGb5lny1IL4tZODyn342aJvm01c6u0ckPFClVyxLBBx37TjOGtxw1gq vjl82yMHo19GhAzVZe+18jQnFc6CPGtfmDRkMrPteu8wTMVRgAbNNpcLI9zhkYEhyfYROoz5loA1 QxF8fHKO5thd1a0wzruIetWW4bobxBEmrx7avhQSSTbEO3oN+EdAFQaCNNYPS9ytGoVb03lzXDtQ 0HA4XXZuzn5ahxkSA8QG9GgoimvJsjoZkmh5PngdEwvGFYXkOdkDmDRABS4Ve5Tko1rnJg6K3tsE MeaitKFeGmgei9R81zF6UJCIi414gy5in3sFsi8crQeqvMpP6KDiKrK9okHDSK61OHmSV+kAjJ1k g33T5VSJDYCQ9BuNt7iGwjWc6OlA6zXZxWpJQe962QmkKIYNv1F0XXaKdzjzJcB8JChKE7sNH7iM WYi044ulId8tx20FMG7LJkyxlPRzrLY7fYssITsT5c/FThtNdonlgaVxxilptD69y38NGi6zNhtM rEiJzC9waImH+mqgVewnSdvPl6TD8YthuhcScv/d+p/i6c85pU6wNZbLNOMJUo+mFbZ+pHplmXDM wHkc9+vR7DS2oQ+UKx5Diwhbog8CeyL0IBG2CVynDrXZj/9PoMWk3Ja/5EbY0CfrbdenxKdTUkAg 0FDU/A/GMCA24Y6Kt2gwe6goqwQs4OfvAXLparjFWUb+MaOTRyncCjo9biwAhJQVkACz7Lhda6Mn njJksvVN39/ZAUaSEMvoP8KPpEB6Lg7c9RI3HPnfRbDXCK6sYwvLMLxMNqqbFUJPhEq+uevAOc+M fUNtxG/E403oczyWj7Ifaz52UCmVi7UFSM7SbdYLH2mpxQE/l/sPEvzl/g+/9rZHa41ASIV9sLYk OtAf65zUuHGADoiP3ThqEnKVkXkrXIP4flZRMTb/pMMiDvGSkvV8+NGseahlJglnqphRk2SUOUJJ qzEEHQhwpFl3be8UdXAQlCpjlY6rrlIogw2AnbtsRth3roONH6g2wkKmJgzszwKN9t2WP52d5LEm 48/BtGBozthujQezOsbOuIOSXuhWVGylvtrH3owkhSpY9Ek+kxkNOHMJXNkUrHu0uRagvoa80sUL rVPrVy0tA2NRS1qLs4hemep9+ytpeHamjRcFKWM9FLNQrxha+2gnfqibd78WwLvBkjUM3wKWJZTy U1TFYmgdpk50B3wNJbvE16FIMLpEteEgOjWjMnSnh5REM14u0w9ikunqdc+vUT33kKipmKxGBiJ/ Q1mtoB+CExxUCuihCTQGlJSZWa6HY60nrWR6P8yYW/IuXHwnGBvA/7QRZ6jZf1834iPJzRNwwnQ8 G5P9XWZ5YD+8g8Aq1vlagAcUVSobuaVMoUmPzS9Zl5LL6hC+OkLDL+JvRB9n6DDjOhq5MsGoo96b /N67fPhM7K3NGrMb4IJ9iRdxDmOztlKakDu+ugXqwpUethLRqFYAeJPWWrKdy5pv2NY6DWiCGRHM qLD1z7NrewCn2k7acNwZ0hZG3cS+p9RMEkLORQ/lsGCw7xX4Ywn/MmHF60FpInCn7Z7gFRZ9BStZ QBPoJpJjeQmB2awD0vb+qn0VFe1vmItitubigOpmppuD1incTbldPoABeb4ovFYJ03Cjg4dsauVM 3lxuTX2wPmq8FM2QOrM8NHavzSSDnVWTlkmUL8HvRzWMF5UqkEMTx/LrEUZiuqQJe/p4ZQnkaZmy YJZAiJvpmyOJaQA3xMAtlhyCJtSp3+QKr7VTXJNES0v/+tqRRwxW6SUwSUjb4M6KP8ZizLaadZzd amhww89PytxLOwKptLIYAsOOGoliQ4d7vZssN2F/IeWrWweSINS1VK37f+6gT5hD9VYINrlHlvJY 10suqScD5dCHDoHj++zQawrwZ8HhMfHMa80gYBgOx3z39oG6KLGubV9DtVm95QLHtlqx9rHg+e5X RdlsRE0AhJPxC7L/0Y/F8jdDCISTLajIeFNx9cpoplDNKlaaYrbGhl5yMnNjmZ+JRW3rIHc2ZpkE Jwo3KjgipyNeJmTh+rANw9j9t4aEFlaUxF9IOYch5A5ajRqE72lTgMNNvrh3d8vQmD64BA5eVP/z nf9YjQkFQShQMrWUjeyt79A8MKmkXIEXEw78hpAbD1fQXNFU1VXb1+9dqOfq6GN8rOZFvFFrHI4M qapxLLXLMtFrliWm69nl7lsrRN1qkcwRFXCQ2l83eMWIuUP0xDADIczpQGBanoaXGmzZKf/pj5Dw 0CVNvNFU7JVqlZW+P/ASDeMpX/FMOqUmIaMUCCf+guIziUvK3/DGvaR797+Op77i94OczCVqru7W kD0PVfFMo/9bJVW0iKC9iUyhOeDCSqV3zaUzXZNkIekHUUQlkAYuKHD9GFq550DXpfbH/Jt/BeEj wsJqg6t6b7MzvJzAfgevtyCIn8XASB22HMUgljQh/mH6iSrSWQnDWA5Yffxd/ix40GjiaWeuAywY EeDtfosj1bADiGwoot7M8TPFIEhLypeJlGxd8p3X4OHmnd2vPhZ2aQ1YWGGzJ/3DC6USP8hAyjrb g1FIWX32vrrxe7hDEsUoJSX1nzRiMN1WaHWDA8qU09Bj/oHEbGXsmamFfkCcCybebbB1U81Zr/sW mDMj9rRAUAJfHBjdRd6E5+gKH15MIQlDppUo5oZiVgHXCH2U+SLL36iRNNchhkulGu7vy66IOKI7 Fe+O7EMvnvGMEbePTdEr986XMS5V1Gj9qE3MV8qfletzT8hrZyf5+9XZ+NaNFQsuPbR4XbDj4Jqu MJ2mcz26QflfNqMcAVxzNTNYF6VujpQyLVqmaIRbcAUHlZJdDohXry1TBb3UvqU2fpuZ3hTKvbug FkfzUQSv8M6Ky80BBtJBBvjFssM3CvF040zHFZn705GZ9G32W0HMe5Xzugwd3Yb5LWSYrixKMFeH vVQHi0IGo5nORIRGJ58EKWQ9qFySCzlMb9Wjqqslg5QdDO29apz19mbGnFu+yqUPm21KN5hX8xoj tbVR9eT9ZIgQjxPZ/K2iZ0P8y4SJnAbsn9cmtCQctSuN3AnO+oecRLv/he22FjxK7E5S6XAuyh5h 0y+x2w4mKBkxFK2sGsiBRgs3ECuhk6qxiL6w421DFn00AlJDLDCTzqZwhO6emOkg47ZstAUXIdQK gcU/oFUGCKzWQF9ZwNGfV3GpHb8w0M4PuSsQS213r9GV/TSSQbMqCGDyI/icaXXZrdd+aC8ELasy CieGvdKQQKy/fs0w8eZXBM8W5BVENFpo8425jntGibTgHbkvJ5iK/pzsKJ1oNXyaNbYiWsg2+hE3 qKVTwZpnpdWD2FA7cDCJvq85K/8d6pQGsHezRItHchtQon0RSIuTEgP1CeFzQRGMh84asu95SMqp ntUvB4r/yxxIdiJJ8IiupL6OlIvmfWjNPGSU2QcrpvMYosDupvQoj054QVcriw/XcgodX+CXNt/U JPbbjzdcqbZr3K6TKkk8e+l6pk/KU5omAixDlRNVBTynAt6zgYrPi0S45bgpgpi7wFYDNZoiebSE P0JtBsQD/h7uLeIGiXwgnBA5D1UrJGoXf5n7FqvurjxEEJYjzk6+i8CQ1cq9IqlLi4ltWJvjF0Ot 6lNS1XNpubzJnYJW5hZ8OtA4f9Wm5xUhCLvHSdHwOC3TH5xOoYhpYeYl5AAqA2MjqJWTUTw09ljz O11ydRcKqBWmV0s+bfGXyydYA8AYbxosWade4ko22ceznlnDuUuomxUtPhER+O/IVZbszWb+F3N2 VxpZmOXBfKPlgaggsIU0AXCMrqurAKaxaMbktnLoIgjlStQGqPumbcQdtnCX7iWx7rQyVkkXOG2B 2tUgEXEZT25w+xHky2nYKbCUpSyfoNYYOUeaFKgmsDXIXgDy1I4Wg5FsgcOqB5AJ0JXBPwpEHQZ4 Z4JZrFKDAs7O/ck6smeWZtLckFa8ai3BPcOowWLEn+P6nKryVeUNwj9x21Fzb1mgphj0RBkX/a1f toAAY1JT2ohWfzXBVeLZkYBybalLeK/jVOF8lnJiGJlub6SaTxXNGlLXFxnHOJ1jLyJi0DHQLdxS ZqSPwFuvRjyesJ0PvkLqsnkpO8Qu8Bv9pPlXJsBR0rW9CKF3JnErqOpdZh0gLzoZ7uGwA5J1vbS8 4DMMhhhQAuHkj4E4NQt437gpDj0ZMh0zBdMdDhI3KTeh1xaeqOQJiicp5TKEoYwL3ycFpVkLfc6a y/2iuFSt6gHPDaxowHiGmJlPcjr8jNl2W7sd8pv3xiuTJwHDHVft70gFTT2HVDT2ECRDoI6WaLPL /IqJZatOw2697JzlqOL0DBK5R6z/y6MXOu2apMyHpQ0z+HTd/00y+9F2PwF3hW4/FlAcFV8NWpL+ I9H2gwbrAyAehvP6+z14vDsbkngc0uraMhzZzttXFi1rrCxxD9vNvKDxHh0KR/ANgIfQZGNqghHG xcIjr+ovf8f3nrhAKse+LDPTH5qnTi92raRAK484DtImTluGBH1Oyn4Qz7S6DW6A8NwtE4K9tW27 CxHXaEa7mpTtTCm0fP3qXhFIhSTXg71+L96KH3jh4uLGhAu2ZjL0ez0eSyC1whpRr2nnoqcBTev2 5pmibWmXkO3kK4ksCgOWZ4oDJisYoVQJmOh3SIsk3KzFZSHOEPx94gjuH+MbuZ+lOGugJxzZEsZE c7nX98A1clW0dOohqZt10+6oJTiOU6b9TuI85MbmR19Hslcfr/nL5F7dVUw4DvNTV2SoGnFpT/It bI7whChTIWPXMzJsOi8AcFZUhtpghctt6RvCOyCVX5lmU4fPVTIn6OIoNaq/G9jH2ysg+lWXcWr2 Q909n9SyK/N6bkp5MUcEyQB9daSKW3yoMrpqg09jBkhXJjRSZK8nJSR5gJiScCPAqZzvWEx33l2R Y7za5k9OFpywtwSc4uiT00+xLe383MxxGBTZ3JUOqiFgf0QDPXtyp+3pjbFyPckd8x3sMbXlE2hL /tU2J41PZplWtbxl/Ctu69sQyPg85HKnnKpIMFdruSrIxv5zyYChQwMicq38t1bExhN2CVG2BOET BHXpAN0fXb+/r7ui3SHNtZFtNC2dSH9D0hYC5LbpAe6MRQLhhshqu6zBYvmw9sSI0jbgIzrHhg6t LM6sI2/T83+oON8zaZSc+PwPfer2eZlLyK/1+2GHb6SJp8bL2f339JyDt8pNCVXA/HUZGhXS2x6o dcMGKu7LfnT9BejrfAszg4uWWQaNz0TjKdfdZlJuvCublANi0ll86M+IoAe8Oxy4YEOp0bPrqUs3 YZoWxo9d7943CDskUh7Nnw4k6hHPi5gIgtJZzdQP/SK9s9ODgmhDKLFghxzbKnCJYYW+Wru2SDqc kQ5iCDH9nzFzepAliYrrJ6Yr7DuDEQabJ4RkUJqoombSpKcsxKbj08IvcoSBxHYiehZylPQHDJyx GOki5iCkJGiu1B2jtZuh04EJYBPUAyfewQeCuXMUNfKOZvq7HzgOLdiafWHGs7M+Vpuk765vBhO2 Nz4lFizXYPSdeTfTgS+JJUUP1E8j3zejWS6ZtqtVufIrGYvFoxi3DXkBtv9wySbo9l8srgNA7j8l BHd1XdXXR4Xyk5thD1wZSaL18DNHgApMKdFpe3xeG3P+8I2CLdLkWPrvRpqaW/IXXuwdOfOPqAiZ Psz89rheCB9QC7C9WolXvopg/cR1Ze0CPny6xd1YZ6w5kisVjDO9caIuOEH4v2zrdEcgDzUjM1Ns cRLyGm+UhEtdve9PMGYMRgOok/rw3yH4wFAEqHSOUFaI4yfOegMBSOMi4qH/NqZTkHMc5gARVuTc Ml0R4q97spRM8VYG2gN2hcZkIM7Hn3RVWpw+IxkqFQSIGcYcpUHc9lIHXuhADa4hrOCSq1vtI+Lr yhdBSEROBLJrQukSVR9V5WS1hgG21jHKwbUS4UWKOpa01ngcMboCVLM1A38Q/MrIhzpQn33MCX9R D5Q+e0fI3TMCI+bGaJTWmYzLHafzLxXQaggL9VypzFbwhwdHiTG8BqerCStZQx5crXW2QR/ac9FK LHfWuHN8+vXRAAXl0Pl1aIZZxebahZetKLYfzjVM0UNtMPhf4aqaD+WwbtBmy+8DYOzeZfffewH/ 0S8GhR+k4AvSIMH+kNjpQfybcMUH8lJPitHWIEAtxH1a4gTB53qfqNP+rgSlmce1SPKuF3TDEvBO GhU3YGiv4mc7VFOMVZjhUPz0cz+isFcOenVx8vnjqWilFsYEtqunZnI0aEGEQN1ZcjaZMA5ULVRA CnDwjOy9BCxmaupN3h6MwQQTu//MNCv6Egs/eONEPmHSqNKRQrYt1U9spxWgjcj4GtdXZhgPtOZ+ RrnyCwy5qUoF22EBYgo+g2xAM7NFPavnA7iVhyi6o2F0EuiDqFYYvkk/qGmz+SNkCPoYtpTUUEeA hSwdJfdgqy8IYA8MM/PNS30sldD7tzm0Nv+Q/Rp4PGmijatNn+3Udpjt5wGSjgiNRyjeRmh+RIcf tAAn5NKX/q1TDTRntcxhhy/RZ1MJQiUjypmr4Xrn0HqGUR7jL7tZchg2HJLuhbdK2TTOeUyh1B15 3Ph+A5xbkx+7vX3pHDacmlMWDIGODXYtWRm00Ifr6ubwv0vu2HtD716/GYHXqvzKzmu33bqZk26k UWBOhlpli6bMValgqvFJvW0E/Kn5oGEhJnEQO22o1DyXgFiD5m6KhZP3EJ/h0+uscQvSP/I7zzFu 0TviDCZiNBXxTU+CD8Vp3iyuPYZf0EwiPvkc1860PcoELUWfMtXLlL//e6B1WLQRImlI5IqINoq/ BURNl4rd1BM5X0whVCDxYwDhr4ssWqZVBCTxh2DGAp0JPYPuXk0nxg31X9ltVizgcm3aThxW0J2k 5iLtU7Os8XCYABJUGaHU0GzAuuFIbf5lS0uNRbUg/S7CI+3u2pm2i2NZN10NVdarsJ5zxPgpsyu2 5Ag+CD6yPBZMXWYCOW0uESpwctwemaNwN9/6KIvjFwRwyZIV1qr8R/spZKJaRviNuAZdJJXhynvZ 5IFlbHHaCCJX5uJXBYtNzebQ6irgAQt0EJNGbkQIZp++HrZQ2QXlNEahISwsQLXqA4Bx4O8W2dTX c6eLbR1nNnI1fKP9HhiCCle+XcVoQxd4/84v4SRXeGJ2rF0bSQ9R7Z3Gd6ALUq69h91n/0j/WRhR xGxW1pKg8GDZSGo= `protect end_protected

bsd-2-clause

3bc8a28404fa76f3c6bd5c0143b881a9

0.945369

1.850658

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/case/rule_018_test_input.fixed_lower.vhd

5

589

architecture ARCH of ENTITY is begin PROC_1 : process (a, b, c) is begin case boolean_1 is when STATE_1 => a <= b; b <= c; c <= d; end case; end process PROC_1; PROC_2 : process (a, b, c) is begin case boolean_1 is when STATE_1=> a <= b; b <= c; c <= d; end case; end process PROC_2; PROC_3 : process (a, b, c) is begin case boolean_1 is when STATE_1=> a <= b; b <= c; c <= d; end case; end process PROC_3; end architecture ARCH;

gpl-3.0

5b433484b6d9a8701c28658472894623

0.4618

3.308989

false

cwilkens/ecen4024-microphone-array

microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/cic_compiler_v4_0_viv_comp.vhd

1

11,904

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Z84vKbp3QwH6lKW+3V3OSSO5FD4zz8y0EqVaeZDjU+UBq3V7ktjxQjRP1cxvCJPWGV0MOHb3Jy+L BxCu1X3nwA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block E6lvFfL82aiG+DYyiUODR7/OvOZcSTnHbCmkxWqEKJE6eNZGxQ4HerEOlrasLpNDqKfvbbJ/ZaHy Ao5sFLbF3sMAbrzb2i/u6yj7FZCsiRw9rad7LAMHw77L/0qfaiN6mLNTGml5KMHZ3+GOQDVyRg5E s/BgpSviUSG/H+tF3cU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qzxtR1NGFsXt01AFjrWirtwQO0+2TpbvVBi2mglgH/PYzLR0deBprPoclDlQkPTVmwxtSDwlB1sB mhiQb75wcU5JGZbAmYDSu1AGtxTS1blja6HL0NqBicN4sdwsIY2NIQkDZm6XaQw7Z39ppWnWfh/G RcPMnjRRR3dKbuIFwPZt9Q39Jscet0YHPyLwzel+Y9DptvednrH2YqV1yeEs6IvdgW6ZDN08OrRl 6ShcIjc2ONLNE134F4OR2iZ9N79/rR950eXEIc1nk4kA/RrvAnm7y+9JhZjAABYF5zPx5+MzL33U m2lGGX5FYwBok4Z7JhRzPb7NlXoSLeQvPsVbHw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jLBBuI+29JyW7WPnGUEhExWCvDxR069cCqeQhmUvzzAq17K4sQN5CaZsLSNz90P43frw4EOUEkfK oeUDdYQMoJ4/oIhBU8NC4h8yB2UpB5+EucFlPo14ZqMfPMs3dkVJ11i2NgXTm34Oepn8qQyHZyG1 kxBhn60pCvxeyn5cGO0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block d5h5mKTIkW8Gy6BCJRqEbhRsdezlBIM3ZTR9MOAj3ovBxBWzkq76pvQVO5FpTvtuRmqe4Pvnmu9O AskFM/I/EWiC5LcEcL6/PlnmydaNUVHAVrGlWTZ5h6JPN2C3qWfsxlmCKVGUjgexwZpOwluOAphd LAxL/48MwWTtGpRADed6w4gT0DHhANwhEwP6SYc9+KwztZD18Olh4n+alFO0a7zYSN60YO5SnMS6 6UZjwGTtqXLldqQeoYo3+NZkBkzX7pCDLjFTJa72VNyShZ6Llcoe8X6cEJ+uSSzPy8e/wdRYkR4v HnjnA4NpMClrVb47dkR9hAdZ+gjf/OtVrZo42g== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7072) `protect data_block 9ZNnLnu5UeM0Tx6PFkDSJwlhYzqGwReXAR6qc/GfYCfrfu5hZyeianCtFJjQTDbv7ByVLXoj/EFk 27lzuRHdn6hIoDeJ3P9VjLoKJKfTBVoB3aqAuj6tNyrC0kjf+ufOtCKccbvq3gnpB24It5P9M4R0 TzoRv4ZTpnDn3j/EMeP5C140rfCU1pGr95fsxEo4SqJr0Ag4/lY985yhIy7jNWl9rnlXXB441zyr t854BiZr50VGFEFvl1snoDyu+Pz54IhfqTQgTNi8k7FIo7rxi1VHRVIk50gz77wx3XlIuISj02P4 lRP5B6jXns2wj+HmUOo2GFCrUZv3WBUfOTsIOStKz8xLjKli3VWyQooDHGA1AJ4CoY7N6hGIE0Wg l6HpvXPSWAo0DwDXEONhmoZKWbgcylXwP1VLDr+WR4MQWxEOFJa43hPzFLrVlKijAr70+gkgLYS/ 6dQtAHHdG1DWLsnahC3Arskig+ZoYSWzvlGRnUwcnCga4B2TWc1MDyz9HeNYNe/BxzKc6F5Crqn9 hV+8xAK2VVo98HLjTmKAHyRH7bORrbaqpv3J5yY1g4zx4JjAYXfy0nd3/RMM1to957HuTzFCz2VX H9MUA9wzwqtbcKQmF+OraollFGEwLtHm3Fye+bNqiu4MGUTKkzFKtAJ0AWpgO7x5XfmZtjzMQD5S E4q5meM7Og/2xUJjh2hvI5fW6vZWbYKYP5O2rqgXAQVh6fNcoZIBuKiLEQ/+aqJoqjxHmuflbOrB 8lZQfPYGN3rSbiAEw6hueaf8udgbxjd7e8Opu1pCW1gRhH6XKdA3r8E/RUBjqKpW9tqDvXBomus7 5uanQvujcp+TEoLV9N2376FrzA8YmA9+L//QM4UBvMWEqfG7Gke8hUnxQbJG65gTXTOZw7B02QPY 4cadsbs5XYJo3V2mPl5Ueb7bgx7UIobzMWAm5QIuKg7Qv24D5ArNRTjlIdriX4TejIkDsDvf+asc QnyL+vkDYDNVh8i/AyxaJzEQ1PrRHK5OIo1rvZJ1oF5zhTs+dpxu5+auOs26r07SwvO/k5yk6V6e ZKORiZzesHd5DXro2aqV9qKgE88WbrUDl8h6BJbt0elKQPIbcXRZVLisipMUclNVf0qLDdiiT/ab JJW2NzuvAJ+NW8EEvdFZtMyvlefk+mQ6y/AUnrI08vGOinMIBWgIHC0gUIjQM11cmN1JFOXE4pEn 6j5S4ys3ShDNModqeU1u/4qhJgjeGjHrSC8ZUSDqNWktoRs8OAb1zX/6AKHS0g7q0ahhpmAOaPFb cxY9Ar1dTifhjyJm4jhd0LWTgfzSwLzaAtK+Q+l0T+2NmZ34zAoPO3Qe4YE0/WpkHqvCVbYUI4Es GEjlbpvlNhJZm9U6PC//zVNU5f3ZbUuVaZ9cC8ZjXocGc1yyef24tcJxtYurKrBmL0jLqcLex72Y ZNw1C7DAm6O8z4z6SLKvGIMD0kOxJnLaeKYM9e35OADDIGxAALmZixbFKJcEvZkqyDZ+QhUBg6f5 Yabb+bmBFy8s2NgVxprZyirRRWXsPkH2RxipsIpRk1ndGoy5WGy4LMgEM3FvoYCdf1YxnRElgEqj 73G0/Q9KOYt/laTsgqwdyO3AbTKvFB8l9arAaJwPHWYuzUH4IjFbzMC9gPryUShQMCOUFSZPRR53 DMbpuCvd6MvIsrsGnFmF2B4rls6kds80iETr0pMAh1uzRWNBRDt1FswpN9xIRbEXj7EVnTou+ssa iW/2V7pF7JG+be1arlwgtIVicd/vAZmNipBwec7jUheUfuK50B5U6sV7tdkU/eUkqWRcS0hEBVFt UNtGXNo7f0r3lYTyFcgsyjtmX4GS6KT77ZzkVGX0m15+dLfUEObMxdd/6WAAq/ZNksKcQciNxgXQ umDOUEkURAk652dcLmnOj+/BXaflb0w07p+HoM+ld1Mw3Xshk42M4QyRWrjOTUuvq5rhPlXMwpiF Y2XWVZ6UTdQMkO18REav1q0/r9sspdMEGyPXfninL75kU01rxiVbCw7xmJdl4+Skhx14P8WKspYC tHO8YgPv7eTuf2kOBWWOSQaVMF9tn8Xrh3f/3Zza2nxt0Y6qB5RxZwfVgDQ/p11stVf1z4ZrjIGh DjBjrK4ec+VpiOn8ePZDBqZGUf4NAxdpoHTM4yaMVgryTkGAgn0Oq1TJmwjtu/M1KJlnUTp288LB OJB4TC8PCqEuSIGqTZcCWsfU1q7y6q2Msj5vSMt0Gbd3adKUNU0yCDMrBTkaT2hxDkHMSDY4NA/R wpfNIn1wh80rK2KUfEXPbz2GL26p0xXpVbzm2Qqil9PQTCnF3GXy0B3p8GPKf1eZ5Y2tsKaCXpCe 8fetTkdK8aM8NnUHVuHYs4H53bL151Ec/XPth/4W8WL7DTH/WOorME2PGAp4Tg4fokW4wbheb2nq LXMPsLn22QqcUYz5S63kVBCm5k43/n3G8zgf+QS60MrzWPkJwn6VtSsTtP6pDdOv0G6eCKtPM9Q8 VfW7+qM9XZjQb6Xpqe1lVW6ZtNYalhCSZgLOg+5Lw83T01IVzfEJgLZ1TuTT4iE/Kj/i7gFB8GqD hkgSfch1fR4N1Q0FwOdrRY9D4WAY7ad3KFlAlaJTONcYbOQA4jjRXwAzKvGMJfy7bF5EjY4FvpEb r4sGAKzw4h2Yke2H4hE/s3sIIRMDU/v9333pvIDxw3KhUncqUP4tYt1G9TEZGNyP+zrAgZRm7c6P 4M62pKnUetJMdjFb6gpxJxfuuSLVawTzsGmwqFoOhfX0QR1desFLye+wr0sN+fMI9b4BBjZwYCyz BwibXy7BIZCwT81JLJ4ehtulgPnNdOgm0H6XCHypzB98XalqkpIE61+ROEMBnCNRGknBQf3+cUOa QP22iSpqok56XZuHCjlOg5yn2H7iBWRllj+y284vJBQBrqp0n1g02XwFIEkCbukItk72pS+Avv63 SZaRYzhnAZ/3elAfnXovHN7XOWLi/s5IrX5HOO0hULyxaVH0ADE2dw4bKbgUdDNMo69HRvX8DRzc 2cJinjoJHv8jxf6/IJOT0FMo6Ck/zs6d0Z7/O5YaJRKzbff69AMujcF4BWKCG1zDcH91FdJbtYdU 8DCDpEeyHGKpLI6log2qijNt0iIcteJwRio4ZfJ+sYnP7KZMAnxi/wNFGndbUcfvjhbHzwVBj0a3 Yi/6rGh0JLp93A+xLh6vi01tWQCX6OORyJ3GRFMG+n4VcKnpi2p3GAdFjGrDWcUdQo3KWxM6VIAx zVfdCLR4V1xoyVX1u5Pl2g/5UaDkN/skP9Kok+9IMe23fTuYi0nbWuEQJlNrE0W4vK1nrf1kAZpn DpRZ36Dgz3ZNVaiV43FXGC4M3JRcEtIHY0r4+509EcGU+2aVihguNHNsV4n85qAUr3FGyhqI+LSp kGsDQHfhFLZuA0g8w9Rj+Vu7Mie9V6XrB4dnEqhD75QW6jv6TJdffFuMahem8Hw2mTuZR/EGpwx2 IR85zEzQpkiJMSuibudcfH85tVV8lq6lfoMxV1qTiW8bFN2eoK021uLCtqLnP+roH8uGhvVnIKFA ma43XxlEwLGQpYL1/mWzNEIL6RXyKoL9IIeK4i+gv+uPtl/zURlWoVWu1vMCqvVtgjFLfpVlosf7 JjpoBK10owOTQVdUMM47zshy7dW1XxsiISal3SfXFYPeo2xxUHZD0DxiHiwlyKAHxXZQRjq/2NlT QXxcvlTF1ct1pR7SFw6JZFIrukt0+NmvN6BCbbi03ln2m6V8UOrThp7OXZiZKUmwlPG2W+66ZRPm 0K+P5dj4keNn3ZeE77AY1JSssooRxLVmYPZCxgz/h75NvetfNG8T647/s63N2Z12KQqcVIUO1OWJ bf2B1drvHTdEh0R2TcuTEM2ZL3S72xJDEjHdLXuUKLJvNIy1Nxz654x4Zj4yfK/m3ysm1XqPYztu auP+pUrNm4aLzwgVWIz0f7/46KoBYuBsCVr+7N0cRPlSSt11dw+5opS7edpQJPz1cn9d3c5Hlt8m DmXs7txaecJF+OFPLAaikIyxZAtQE4ODQXxRH7q2uT2qAwrwRO4qziN6PBqAugaezeht6KRXkBnB rQp8/0hM0a/LxOGVumLvQKPQAw8zfcN3PdSE9z2uZjj1r2uT9jVqZeXGuGvrmW8D5SZbUJxoXZJx sYDIjmYbAIH387YpJ0kh0QmwL7lY4FweXv7kG/LOso1Uau4gKl1IWSdds6/3++YThyaNVPWoubyS 3JpXPAWehdaTLaVVRQ50GABV0gzKT7kvWo8M6UZ14/ikO3V4U4P4iEEG1P9rPodz7XWu8IXt87tv NgY6dvzamay11Wl4AsWoRyknSG6M3S3IGM2B5dTgqXksh611RIhZvqylpmSfqCTCoWINg1Q+e7MP ECYQtkWt0mSEwFyWhx1w0tfIYSQ/GUVsIWQrcDrAI78HHT816Q72MNcUiUu6pdFyVmj6npyb1oBG pBxAW3Htsa/KvFyrPyyALYElvPFKj2CMPH8x/bDFKIGWS4WH426fux1+lCeIA3H8wfH/9wBV9Jzp e09g+ukbwSmCdB2h+Lb6byJ/auf7Zq41pekAT3pvpz7E43JdiLx7WWWMBaQcvrBC3b4Fp/KYrWse h7f38dmUUnCsWpDp/PdsD64gbLRLcEFzyBBPESknOj94lTdCiXH8VBQ+gAz77czbuZQqmcp8L5HO 0bisviOiTfaRLwdJpFfv9MQt1NK2gqWwz1fCAJ0Q5t/ZJx43OJe6RRK4STwoQo1uYI/PcXVw2vMW 7aUvmpKBMubfDDgaN+u88n5nCzrM1XkrUO54dfyROeLQnBdGcVmQsRT8Gp0U3YykLdd3OmwRr6fo T+l/IwzsHrRcjd+g9RvJ/woXVP8cf4njX252jwEGll0z1IHUE8gPY9ud3GEbafzaUNsbMxm64Htt sPQC5cNHZzhBnTkKJThWDBEuyKK/hO61euPGzts3QugwDpcwWQ1RSVSpcrtSnkCPC9QWzUS3Qs1x o5KR8ddpR8m+cbLzrzsXkElLsQ6FJoTZ+oyGyjXKiTHJQ4eQ0+ly3AZ4kZ7/j+56epugThLwr5AH KlWu+/wKDZqWS5he9jk+tOHXiH3hpY24kemWeZGXTBv9uXTSNSc8FFPxRLi8MUq6I4jvs2/hoedV IzqHM3/JLo6J4PTsGmOqExnG1RtUqWa6l1Ac4YZxEZtxKA4sDuRN5I8bDDlokIOPus9edD8o8qIq WosYUYMac4X/eS4ec7UtbQkqAlEEuSrPG2a88gupXNkrwYz8a4cWWNlp0mwOg3kkOufYGdvTEI5T T+CCxOjiIL6/9N+S/ccGLpfNaQYZ3sFKlvs4k07WFp1nSeRhjZeQSamHI3fvNt0adK6WQYN6ACcI YqsHwc11pT5hgvf3IcZ1wbmn6WB/sNQwRWPnML23OsY2WNmdI9FFBDg6y3zI18u5pWt1DkGvH0mv ckdhVAVF4AJdkx820TupXxt3TyChFHMJ1hbxwk/xqT8bbYY/awKVKJwLyQfqrOlxM9vCchPbDoPO ARlM4lUc2E4EjcYljRV3CtGPgDVP/KD8HAdfFGVm3yJX/cavTjhfcVEYLmABVod3wypMN6blpt0Y FOHN14f1fCybAfmZO55PnCKWOKEw3b01J3TldQhilgbCZMnlI25SAAb2zVc+Dqc1kMUtxRmXU+Z0 0qwHTICzujra/vlkvLXobW82byCXRSXUN3GShbO4zCGgTaS0uR3t4oJUgBJpmOKgUmi5DAryt3u0 WAitLHL7557MzUaoQTPhlmkXMNfxPDbsxI6pgTxSdhG/Q8wc+E9lwT9btX+Amez4kExP8PxEQlqs ME808iBnKwVplgxP9zNeYEEoVnhhmC8nQmQc6kWlzuLVFYFMj38rUYSysTysD8sohkfSTeJJvJo3 x+Hq2eSENpmwxbw35GEhUJKXv/Hmz5QOGFczlXC8D3lYFVyz7Q5t+o/A5nEm/heFho2EXCRiR2lb Y5W6YbVJxXylGdFJN3QtByyLhpcY5Nq/EFshreH0onH+mAakh6Z6Kj81b0/zhWEnRvl2PoVmSsAc kceAiboY4Df6yVxteJG2NTXCiReHnaEWgvnZcqI1sa5nQSi+IgRuUlvtNjz/MxRirFAAml8kyx9r NbposrtzolmRuyMwdYZ/fS3k750QtpFhf1U9xXDGATxlHxkglvrXoTBUFZS7s6XAps1rOvnUUx5l p2WP0Le5yoVaIjCnbSq+w5wLGG/WTEj7Z8Uco32PVGHbvazkWNejyXEX9UoGm82rdfUNzTXPQxHl neoALJKMkJtwtbUDHAJOh/SolyqTPiO5wZaNoDPDiPfwy8p033kBi3D64ZpeGnXAvqkgAN1D5QN6 PynNP6Fj4KSC7h9PS6uIeJ5z0dEKAL+yQ7L3Ddj7UgvsShs0jAlJ6AP6h7sSFK8i478VfBhZwBim 2RBaGRijrV/UPSXDWG6koIhNcC1eBcxtIrqsJbrpWVOCUirtuCYT111xAlpvBZc3Vh/1+s2WNXic WAoKDAOZpM2YL9qypethZsV0QT1Nbg+NtO8NuGF7Cos1JnKDYB83MMaTJOVJUtvuaYaq8tltfRoj oo79YgZfCchTWsg+eSvpWFBvXhr6OFpmImLV5caplo3CuP66c7k5IQa/0mTIkDQ3cU7QFYMleE3h JNIJ6vU4eK0Kftclx/e/kMUaf6DokXZ4Nsn/o8uHKPfIM9LZWSqRPRv9Z67v0PGrVr+Hp8RRt3oL KEwkuuhrdR0m9PnzPIDbkB8Y4nuVZejdUTa2rHANZDYzm/xXpxM3T/WJEAvqCCeRIoqChA+blakU AVbG4Wpb1uF3PQdFa5ZwbfK+Fj6fSqapaEQQU+RxqGPAj4YpDADTeyD+c7hSQH6AEhq2Aw3pJqQp Sv90n49qs5UaU5PMetrAoIg1YNHYzXAkdhPS9kRLmLXB/HIgtlcGB/pyicGk7qfFu6lX3VswzcHQ JqLWWghdyo6pFyECPCi+E27/d8bM3uv1tmvABnI6KwJGL40SAYai72nbyPgVXzrDNBqc6WAfA/V9 zV3rhBEJ7HiCsXzZFlF/8TKHhwWevbsgD/QywlHUuYZ8E6kJ9UrQYSjeO2TRXc0ldUM3P34g9USv f5j4rHHbcsv3msNs+91CT6Nbrfy/QNSB/6lo7b+Un3uyTGtkeYWkkQRIB3dkIo+LDTbSw34MFWKQ /0zWTeZMYRrGhPiUkStxZoMfi81YtlqGrxRMAKjT40KVeywGtyzlFZJgJanzcvN+h8I5cZsePpsY hawvuvkXg5zjUUfCx/sjBsjYmvNw5GjJKF2ANQ9r5i93QgQS5MFeJJuG33F2RUVIMztia0HmCGH2 SPt7Gmp2BfwBoaDyF0X5RrAudKkJYh+c0fT4nLUJ0fhaIUc3B6kdKI7Ws56jUgM5VvZHvex060iN Q+tvqPZgv/dfbw/XfwWITT/Zds7rPGPspkg8RT+BWRfcf7OP21X9LcKQrmWvUPEDC0Ck9SZ16sML I+8QswhP5KZvpkilJfZ4W+SfIc5i6ULA24h1N9qpBmnKx99VcXt95lNnPdXBwuxPNXHwH/USJcsk N4sVatwhwbNT/WivqUXo9MHNCDJYFPXBjyyP52+jc5QEGUQBFpadF0aOkeAxaDRHQIy7/igPWc/x 1NLxZBZ5ncrzev6H2RUZ3aT5Z35qbLrkqmH/FRFCUl5b9+cF5X01u7MfvZdpnt71tNQfrf3FqzIe GYEZ/hfdcIJ2lHiEVD761LvZeI9rZ4VsJZh5OhwO1Y9QDfqOSrh+uRliN2ePZ0CCsE+yg8QOFM7Q 46d8kVeRqKBAZxCPD65mEhU/pbZBM6awUEwgdzfsnnKaE57EMMHGA5/P/Hyt1OftPWfh0IzJ+S9m 7jRQkYWhd0de7ekxRidM1qacWskfijJ51eSWaDVnssJkQ67BLPMddZgB5ul8fPukkOY+h8L+kWbV UPaNOoHU6cUVm/SLWBlbDrQ/k64+enc1ImyNEpcBpMnIyRqWww+Bsx85W8QJokz3XeWAgDMuauQ0 MOkI6NZwOKPxw4N3o8Ev08dKaSxsNPft57LGhTh0kAm1bdkibwG6G8OHO6cWvV8UZUSJ2zwzY25o rgUZicPuxX8D8tXDCZR7jMQCJnt1O3JPWcs0CihOvkc79xAjiil6VD01rps3NyDm/p4UHmDhSSwL WKWv4CW/g9E2PMcr5rMPS4iGxzNy5IA9AFFgFDTDJ3YT48d4+KuXp5t/oyiGfwbpjmWv3Gykuk+a oFXfKWbeua83mvP4IVpIbNzJXCZNa1E6kpAaTGM18sZ8XnkWDPSaZAj5UPHh8wfSe+q1EiHmuB03 QXEtITBkL2T//caiYnjGlHtxLTRx/2Dwyoyef+NKcSjvrJBXNxqrHv7vShgiP4kro46b4wTV7VwR FdrbKK268A0yuXJAUdKxRyApXn8bE8qCqtz2nxxfhZv8Jzic1JwzEvaN6sA/eizeYQCgKrIoVBAh Rx1ru9dHdgHDI+MvT1TUbzQE7kcFklCEP3pbVEijjUQw2NRL7m/DSvDijTTqnJtfZIvtXU8MhwiY z24tsnf9118xFNOhQ1hyWZjrGNc/O1rYjqixu1dqAPgazYPQxsWQ32bx7AqGrgr3Qi3zDLadIMdP ImDlKU30DHHaXHAfj4vXG+RlA9VlqrNiue4BZNg+pqyJsl9zn2GsPxr7wbrGjqp3InJplJIfFiPR BeHs+Q1qc7yyfhqceMkeF1vB2j4MGcqJNqEY5SZVmsPG0EDHWOjjy4Y2at2rlioLy1b3uIqIZzve 0xNljReM8EmCj2FMiH/UqK+c5dyCseYmSNVv2vtbiv4MRJBAtlRgMnkispwIaKWyNIvop4LNXBwz oFnFjgP83hlbKre8H1d/pceoMt1ysn5UtmS8VzjmNyBg2TkJ0Tk4sMTcDXsSd8h7xf7UXrLZVfi7 1py5wt1KK29wfUz9FNtRuImAs1XomaSHnyElRzQMlEU3F/v7ckSkzqEvVJCnY7eOLzxB8/jxGhtu iRrSgiRUMLz/nhIzu9tatZCB45f3BlpJdbQBsSOxaevfDmfP72Vgh/8iV4Sj5QYKfuyfMqi7M43Z ftmXEbd8NxYpKFIFtCYLvWgR+RhvRLFMzpl93qzpZLo5y0Y0haDOh3XEdAsqh2PBXU1Tc/m2wX+s JHbtvNUu7/AsjLFsdsJKJqA8pJZygD/IhzspTRNuwTEIfjNrshtre/jr0vmD2Ue/8FKYpk9QJd0Z r2uF/u9QXNsovadV05JUgr3BUVyvNYUHbRxq2jKauWN/x5pCEOnW8ID+TuN4owkW36bbaKBDfuyS MeyaRRwIguQ1E+BGZp5I3kt/DCCBMKjiRfWZ67Lf1+9zCr6AgOJDB2j20mBOdHA67O2EIrnY3Pd5 XcgX7A== `protect end_protected

mit

19bb0b07b4fca4f084b8989be862d4c2

0.930696

1.877603

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_status_cntl.vhd

1

58,183

------------------------------------------------------------------------------- -- axi_datamover_wr_status_cntl.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_wr_status_cntl.vhd -- -- Description: -- This file implements the DataMover Master Write Status Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_wr_status_cntl.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 7/11/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- -- Per CR616212 -- - Changed logic to force a coesc register push when a TLAST error is -- reported by the Write Data Controller. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_fifo; ------------------------------------------------------------------------------- entity axi_datamover_wr_status_cntl is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if the Indeterminate BTT Module is enabled -- for use (outside of this module) C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1; -- Sets the width of the data2wsc_bytes_rcvd port used for -- relaying the actual number of bytes received when Idet BTT is -- enabled (C_ENABLE_INDET_BTT = 1) C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8; -- Specifies the depth of the internal status queue fifo C_STS_WIDTH : Integer range 8 to 32 := 8; -- sets the width of the Status ports C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the Status reply C_FAMILY : String := "virtex7" -- Specifies the target FPGA device family ); port ( -- Clock and Reset inputs ------------------------------------------ -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------------- -- Soft Shutdown Control interface -------------------------------- -- rst2wsc_stop_request : in std_logic; -- -- Active high soft stop request to modules -- -- wsc2rst_stop_cmplt : Out std_logic; -- -- Active high indication that the Write status Controller -- -- has completed any pending transfers committed by the -- -- Address Controller after a stop has been requested by -- -- the Reset module. -- -- addr2wsc_addr_posted : In std_logic ; -- -- Indication from the Address Channel Controller to the -- -- write Status Controller that an address has been posted -- -- to the AXI Address Channel -- -------------------------------------------------------------------- -- Write Response Channel Interface ------------------------------- -- s2mm_bresp : In std_logic_vector(1 downto 0); -- -- The Write response value -- -- s2mm_bvalid : In std_logic ; -- -- Indication from the Write Response Channel that a new -- -- write status input is valid -- -- s2mm_bready : out std_logic ; -- -- Indication to the Write Response Channel that the -- -- Status module is ready for a new status input -- -------------------------------------------------------------------- -- Command Calculator Interface ------------------------------------- -- calc2wsc_calc_error : in std_logic ; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- --------------------------------------------------------------------- -- Address Controller Status ---------------------------------------- -- addr2wsc_calc_error : In std_logic ; -- -- Indication from the Address Channel Controller that it -- -- has encountered a calculation error from the command -- -- Calculator -- -- addr2wsc_fifo_empty : In std_logic ; -- -- Indication from the Address Controller FIFO that it -- -- is empty (no commands pending) -- --------------------------------------------------------------------- -- Data Controller Status --------------------------------------------------------- -- data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The command tag -- -- data2wsc_calc_error : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- has encountered a Calculation error in the command pipe -- -- data2wsc_last_error : In std_logic ; -- -- Indication from the Write Data Channel Controller that a -- -- premature TLAST assertion was encountered on the incoming -- -- Stream Channel -- -- data2wsc_cmd_cmplt : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- corresponding status is the final status for a parent -- -- command fetched from the command FIFO -- -- data2wsc_valid : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- has a new tag/error status to transfer -- -- wsc2data_ready : out std_logic ; -- -- Indication to the Data Channel Controller FIFO that the -- -- Status module is ready for a new tag/error status input -- -- -- data2wsc_eop : In std_logic; -- -- Input from the Write Data Controller indicating that the -- -- associated command status also corresponds to a End of Packet -- -- marker for the input Stream. This is only used when Store and -- -- Forward is enabled in the S2MM. -- -- data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); -- -- Input from the Write Data Controller indicating the actual -- -- number of bytes received from the Stream input for the -- -- corresponding command status. This is only used when Store and -- -- Forward is enabled in the S2MM. -- ------------------------------------------------------------------------------------ -- Command/Status Interface -------------------------------------------------------- -- wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); -- -- Read Status value collected during a Read Data transfer -- -- Output to the Command/Status Module -- -- stat2wsc_status_ready : In std_logic; -- -- Input from the Command/Status Module indicating that the -- -- Status Reg/FIFO is Full and cannot accept more staus writes -- -- wsc2stat_status_valid : Out std_logic ; -- -- Control Signal to Write the Status value to the Status -- -- Reg/FIFO -- ------------------------------------------------------------------------------------ -- Address and Data Controller Pipe halt -------------------------------- -- wsc2mstr_halt_pipe : Out std_logic -- -- Indication to Halt the Data and Address Command pipeline due -- -- to the Status pipe getting full at some point -- ------------------------------------------------------------------------- ); end entity axi_datamover_wr_status_cntl; architecture implementation of axi_datamover_wr_status_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_cnt_width -- -- Function Description: -- Sets a count width based on a fifo depth. A depth of 4 or less -- is a special case which requires a minimum count width of 3 bits. -- ------------------------------------------------------------------- function funct_set_cnt_width (fifo_depth : integer) return integer is Variable temp_cnt_width : Integer := 4; begin if (fifo_depth <= 4) then temp_cnt_width := 3; elsif (fifo_depth <= 8) then temp_cnt_width := 4; elsif (fifo_depth <= 16) then temp_cnt_width := 5; elsif (fifo_depth <= 32) then temp_cnt_width := 6; else -- fifo depth <= 64 temp_cnt_width := 7; end if; Return (temp_cnt_width); end function funct_set_cnt_width; -- Constant Declarations -------------------------------------------- Constant OKAY : std_logic_vector(1 downto 0) := "00"; Constant EXOKAY : std_logic_vector(1 downto 0) := "01"; Constant SLVERR : std_logic_vector(1 downto 0) := "10"; Constant DECERR : std_logic_vector(1 downto 0) := "11"; Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000"; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant STAT_REG_TAG_WIDTH : integer := 4; Constant SYNC_FIFO_SELECT : integer := 0; Constant SRL_FIFO_TYPE : integer := 2; Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH; Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH); Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0'); Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH); Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH); Constant WRESP_WIDTH : integer := 2; Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH; Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH; Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH); Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '1'); -- Signal Declarations -------------------------------------------- signal sig_valid_status_rdy : std_logic := '0'; signal sig_decerr : std_logic := '0'; signal sig_slverr : std_logic := '0'; signal sig_coelsc_okay_reg : std_logic := '0'; signal sig_coelsc_interr_reg : std_logic := '0'; signal sig_coelsc_decerr_reg : std_logic := '0'; signal sig_coelsc_slverr_reg : std_logic := '0'; signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_pop_coelsc_reg : std_logic := '0'; signal sig_push_coelsc_reg : std_logic := '0'; signal sig_coelsc_reg_empty : std_logic := '0'; signal sig_coelsc_reg_full : std_logic := '0'; signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data_err_reg : std_logic := '0'; signal sig_data_last_err_reg : std_logic := '0'; signal sig_data_cmd_cmplt_reg : std_logic := '0'; signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0'); signal sig_push_status : std_logic := '0'; Signal sig_status_push_ok : std_logic := '0'; signal sig_status_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_s2mm_bready : std_logic := '0'; signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_wresp_sfifo_wr_valid : std_logic := '0'; signal sig_wresp_sfifo_wr_ready : std_logic := '0'; signal sig_wresp_sfifo_wr_full : std_logic := '0'; signal sig_wresp_sfifo_rd_valid : std_logic := '0'; signal sig_wresp_sfifo_rd_ready : std_logic := '0'; signal sig_wresp_sfifo_rd_empty : std_logic := '0'; signal sig_halt_reg : std_logic := '0'; signal sig_halt_reg_dly1 : std_logic := '0'; signal sig_halt_reg_dly2 : std_logic := '0'; signal sig_halt_reg_dly3 : std_logic := '0'; signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_posted_cntr_eq_0 : std_logic := '0'; signal sig_addr_posted_cntr_eq_1 : std_logic := '0'; signal sig_addr_posted_cntr_max : std_logic := '0'; signal sig_decr_addr_posted_cntr : std_logic := '0'; signal sig_incr_addr_posted_cntr : std_logic := '0'; signal sig_no_posted_cmds : std_logic := '0'; signal sig_addr_posted : std_logic := '0'; signal sig_all_cmds_done : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_wr_valid : std_logic := '0'; signal sig_dcntl_sfifo_wr_ready : std_logic := '0'; signal sig_dcntl_sfifo_wr_full : std_logic := '0'; signal sig_dcntl_sfifo_rd_valid : std_logic := '0'; signal sig_dcntl_sfifo_rd_ready : std_logic := '0'; signal sig_dcntl_sfifo_rd_empty : std_logic := '0'; signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_statcnt : std_logic := '0'; signal sig_decr_statcnt : std_logic := '0'; signal sig_statcnt_eq_max : std_logic := '0'; signal sig_statcnt_eq_0 : std_logic := '0'; signal sig_statcnt_gt_eq_thres : std_logic := '0'; signal sig_wdc_status_going_full : std_logic := '0'; begin --(architecture implementation) -- Assign the ready output to the AXI Write Response Channel s2mm_bready <= sig_s2mm_bready or sig_halt_reg; -- force bready if a Halt is requested -- Assign the ready output to the Data Controller status interface wsc2data_ready <= sig_wsc2data_ready; -- Assign the status valid output control to the Status FIFO wsc2stat_status_valid <= sig_status_valid ; -- Formulate the status output value to the Status FIFO wsc2stat_status <= sig_wsc2stat_status; -- Formulate the status write request signal sig_status_valid <= sig_push_status; -- Indicate the desire to push a coelesced status word -- to the Status FIFO sig_push_status <= sig_coelsc_reg_full; -- Detect that a push of a new status word is completing sig_status_push_ok <= sig_status_valid and stat2wsc_status_ready; sig_pop_coelsc_reg <= sig_status_push_ok; -- Signal a halt to the execution pipe if new status -- is valid but the Status FIFO is not accepting it or -- the WDC Status FIFO is going full wsc2mstr_halt_pipe <= (sig_status_valid and not(stat2wsc_status_ready)) or sig_wdc_status_going_full; -- Monitor the Status capture registers to detect a -- qualified Status set and push to the coelescing register -- when available to do so sig_push_coelsc_reg <= sig_valid_status_rdy and sig_coelsc_reg_empty; -- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and -- pre CR616212 sig_dcntl_sfifo_rd_valid) or -- pre CR616212 (sig_data_err_reg and -- pre CR616212 sig_dcntl_sfifo_rd_valid); sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and sig_dcntl_sfifo_rd_valid) or (sig_data_err_reg and sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212 (sig_data_last_err_reg and -- Added for CR616212 sig_dcntl_sfifo_rd_valid); -- Added for CR616212 -- Decode the AXI MMap Read Respose sig_decerr <= '1' When sig_bresp_reg = DECERR Else '0'; sig_slverr <= '1' When sig_bresp_reg = SLVERR Else '0'; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_LE_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is less than or equal to the available number -- of bits in the Status word. -- ------------------------------------------------------------ GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_small; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_SMALL_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg) begin -- Set default value lsig_temp_tag_small <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg; end process POPULATE_SMALL_TAG; end generate GEN_TAG_LE_STAT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_GT_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is greater than the available number of -- bits in the Status word. The upper bits of the TAG are -- clipped off (discarded). -- ------------------------------------------------------------ GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_big; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_BIG_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg) begin -- Set default value lsig_temp_tag_big <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0); end process POPULATE_SMALL_TAG; end generate GEN_TAG_GT_STAT; ------------------------------------------------------------------------- -- Write Response Channel input FIFO and logic -- BRESP is the only fifo data sig_wresp_sfifo_in <= s2mm_bresp; -- The fifo output is already in the right format sig_bresp_reg <= sig_wresp_sfifo_out; -- Write Side assignments sig_wresp_sfifo_wr_valid <= s2mm_bvalid; sig_s2mm_bready <= sig_wresp_sfifo_wr_ready; -- read Side ready assignment sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_WRESP_STATUS_FIFO -- -- Description: -- Instance for the AXI Write Response FIFO -- ------------------------------------------------------------ I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => WRESP_SFIFO_WIDTH , C_DEPTH => WRESP_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_wresp_sfifo_wr_valid , fifo_wr_tready => sig_wresp_sfifo_wr_ready , fifo_wr_tdata => sig_wresp_sfifo_in , fifo_wr_full => sig_wresp_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_wresp_sfifo_rd_valid , fifo_rd_tready => sig_wresp_sfifo_rd_ready , fifo_rd_tdata => sig_wresp_sfifo_out , fifo_rd_empty => sig_wresp_sfifo_rd_empty ); -------- Write Data Controller Status FIFO Going Full Logic ------------- sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and sig_dcntl_sfifo_wr_ready; sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and sig_dcntl_sfifo_rd_ready; sig_statcnt_eq_max <= '1' when (sig_wdc_statcnt = DCNTL_STATCNT_MAX) Else '0'; sig_statcnt_eq_0 <= '1' when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO) Else '0'; sig_statcnt_gt_eq_thres <= '1' when (sig_wdc_statcnt >= DCNTL_HALT_THRES) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WDC_GOING_FULL_FLOP -- -- Process Description: -- Implements a flop for the WDC Status FIFO going full flag. -- ------------------------------------------------------------- IMP_WDC_GOING_FULL_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wdc_status_going_full <= '0'; else sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres; end if; end if; end process IMP_WDC_GOING_FULL_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DCNTL_FIFO_CNTR -- -- Process Description: -- Implements a simple counter keeping track of the number -- of entries in the WDC Status FIFO. If the Status FIFO gets -- too full, the S2MM Data Pipe has to be halted. -- ------------------------------------------------------------- IMP_DCNTL_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wdc_statcnt <= (others => '0'); elsif (sig_incr_statcnt = '1' and sig_decr_statcnt = '0' and sig_statcnt_eq_max = '0') then sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE; elsif (sig_incr_statcnt = '0' and sig_decr_statcnt = '1' and sig_statcnt_eq_0 = '0') then sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE; else null; -- Hold current count value end if; end if; end process IMP_DCNTL_FIFO_CNTR; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Implements the logic needed when Indeterminate BTT is -- not enabled in the S2MM function. -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate -- Local Constants Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3; Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0; Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1; Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2; Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1; -- local signals signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); begin sig_wsc2stat_status <= sig_coelsc_okay_reg & sig_coelsc_slverr_reg & sig_coelsc_decerr_reg & sig_coelsc_interr_reg & sig_tag2status; ----------------------------------------------------------------------------- -- Data Controller Status FIFO and Logic -- Concatonate Input bits to build Dcntl fifo data word sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2 data2wsc_calc_error & -- bit 2 data2wsc_last_error & -- bit 1 data2wsc_cmd_cmplt ; -- bit 0 -- Rip the DCntl fifo outputs back to constituant pieces sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto DCNTL_SFIFO_TAG_INDEX); sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ; sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX); sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX); -- Data Control Valid/Ready assignments sig_dcntl_sfifo_wr_valid <= data2wsc_valid ; sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready; -- read side ready assignment sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_DATA_CNTL_STATUS_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO -- ------------------------------------------------------------ I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => DCNTL_SFIFO_WIDTH , C_DEPTH => DCNTL_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid , fifo_wr_tready => sig_dcntl_sfifo_wr_ready , fifo_wr_tdata => sig_dcntl_sfifo_in , fifo_wr_full => sig_dcntl_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid , fifo_rd_tready => sig_dcntl_sfifo_rd_ready , fifo_rd_tdata => sig_dcntl_sfifo_out , fifo_rd_empty => sig_dcntl_sfifo_rd_empty ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: STATUS_COELESC_REG -- -- Process Description: -- Implement error status coelescing register. -- Once a bit is set it will remain set until the overall -- status is written to the Status FIFO. -- Tag bits are just registered at each valid dbeat. -- ------------------------------------------------------------- STATUS_COELESC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_coelsc_reg = '1') then sig_coelsc_tag_reg <= (others => '0'); sig_coelsc_interr_reg <= '0'; sig_coelsc_decerr_reg <= '0'; sig_coelsc_slverr_reg <= '0'; sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY" sig_coelsc_reg_full <= '0'; sig_coelsc_reg_empty <= '1'; Elsif (sig_push_coelsc_reg = '1') Then sig_coelsc_tag_reg <= sig_data_tag_reg; sig_coelsc_interr_reg <= sig_data_err_reg or sig_data_last_err_reg or sig_coelsc_interr_reg; sig_coelsc_decerr_reg <= not(sig_data_err_reg) and (sig_decerr or sig_coelsc_decerr_reg); sig_coelsc_slverr_reg <= not(sig_data_err_reg) and (sig_slverr or sig_coelsc_slverr_reg); sig_coelsc_okay_reg <= not(sig_decerr or sig_coelsc_decerr_reg or sig_slverr or sig_coelsc_slverr_reg or sig_data_err_reg or sig_data_last_err_reg or sig_coelsc_interr_reg ); sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg; sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg); else null; -- hold current state end if; end if; end process STATUS_COELESC_REG; end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT -- -- If Generate Description: -- Implements the logic needed when Indeterminate BTT is -- enabled in the S2MM function. Primary difference is the -- addition to the reported status of the End of Packet -- marker (EOP) and the received byte count for the parent -- command. -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate -- Local Constants Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH + C_SF_BYTES_RCVD_WIDTH + 3; Constant SF_SFIFO_LS_TAG_INDEX : integer := 0; Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1); Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1; Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1; Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1; Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+ (C_SF_BYTES_RCVD_WIDTH-1); Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1; Constant BYTES_RCVD_FIELD_WIDTH : integer := 23; -- local signals signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_data_eop : std_logic := '0'; signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_coelsc_eop : std_logic := '0'; signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0'); begin sig_wsc2stat_status <= sig_coelsc_eop & sig_coelsc_bytes_rcvd_pad & sig_coelsc_okay_reg & sig_coelsc_slverr_reg & sig_coelsc_decerr_reg & sig_coelsc_interr_reg & sig_tag2status; ----------------------------------------------------------------------------- -- Data Controller Status FIFO and Logic -- Concatonate Input bits to build Dcntl fifo input data word sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7 data2wsc_cmd_cmplt & -- bit 6 data2wsc_calc_error & -- bit 4 data2wsc_tag; -- bits 0 to 3 -- Rip the DCntl fifo outputs back to constituant pieces sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX); sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto SF_SFIFO_LS_BYTES_RCVD_INDEX); sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX); sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX); sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto SF_SFIFO_LS_TAG_INDEX) ; -- Data Control Valid/Ready assignments sig_dcntl_sfifo_wr_valid <= data2wsc_valid ; sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready; -- read side ready assignment sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_SF_DATA_CNTL_STATUS_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO when Store and -- Forward is included. -- ------------------------------------------------------------ I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => SF_DCNTL_SFIFO_WIDTH , C_DEPTH => DCNTL_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid , fifo_wr_tready => sig_dcntl_sfifo_wr_ready , fifo_wr_tdata => sig_dcntl_sfifo_in , fifo_wr_full => sig_dcntl_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid , fifo_rd_tready => sig_dcntl_sfifo_rd_ready , fifo_rd_tdata => sig_dcntl_sfifo_out , fifo_rd_empty => sig_dcntl_sfifo_rd_empty ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SF_STATUS_COELESC_REG -- -- Process Description: -- Implement error status coelescing register. -- Once a bit is set it will remain set until the overall -- status is written to the Status FIFO. -- Tag bits are just registered at each valid dbeat. -- ------------------------------------------------------------- SF_STATUS_COELESC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_coelsc_reg = '1') then sig_coelsc_tag_reg <= (others => '0'); sig_coelsc_interr_reg <= '0'; sig_coelsc_decerr_reg <= '0'; sig_coelsc_slverr_reg <= '0'; sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY" sig_coelsc_bytes_rcvd <= (others => '0'); sig_coelsc_eop <= '0'; sig_coelsc_reg_full <= '0'; sig_coelsc_reg_empty <= '1'; Elsif (sig_push_coelsc_reg = '1') Then sig_coelsc_tag_reg <= sig_data_tag_reg; sig_coelsc_interr_reg <= sig_data_err_reg or sig_coelsc_interr_reg; sig_coelsc_decerr_reg <= not(sig_data_err_reg) and (sig_decerr or sig_coelsc_decerr_reg); sig_coelsc_slverr_reg <= not(sig_data_err_reg) and (sig_slverr or sig_coelsc_slverr_reg); sig_coelsc_okay_reg <= not(sig_decerr or sig_coelsc_decerr_reg or sig_slverr or sig_coelsc_slverr_reg or sig_data_err_reg or sig_coelsc_interr_reg ); sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd; sig_coelsc_eop <= sig_data_eop; sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg; sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg); else null; -- hold current state end if; end if; end process SF_STATUS_COELESC_REG; ------------------------------------------------------------ -- If Generate -- -- Label: SF_GEN_PAD_BYTES_RCVD -- -- If Generate Description: -- Pad the bytes received value with zeros to fill in the -- status field width. -- -- ------------------------------------------------------------ SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate begin sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto C_SF_BYTES_RCVD_WIDTH) <= (others => '0'); sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd; end generate SF_GEN_PAD_BYTES_RCVD; ------------------------------------------------------------ -- If Generate -- -- Label: SF_GEN_NO_PAD_BYTES_RCVD -- -- If Generate Description: -- No padding required for the bytes received value. -- -- ------------------------------------------------------------ SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate begin sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required end generate SF_GEN_NO_PAD_BYTES_RCVD; end generate GEN_ENABLE_INDET_BTT; ------- Soft Shutdown Logic ------------------------------- -- Address Posted Counter Logic ---------------------t----------------- -- Supports soft shutdown by tracking when all commited Write -- transfers to the AXI Bus have had corresponding Write Status -- Reponses Received. sig_addr_posted <= addr2wsc_addr_posted ; sig_incr_addr_posted_cntr <= sig_addr_posted ; sig_decr_addr_posted_cntr <= sig_s2mm_bready and s2mm_bvalid ; sig_addr_posted_cntr_eq_0 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ZERO) Else '0'; sig_addr_posted_cntr_eq_1 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ONE) Else '0'; sig_addr_posted_cntr_max <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_POSTED_FIFO_CNTR -- -- Process Description: -- This process implements a counter for the tracking -- if an Address has been posted on the AXI address channel. -- The counter is used to track flushing operations where all -- transfers committed on the AXI Address Channel have to -- be completed before a halt can occur. ------------------------------------------------------------- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_addr_posted_cntr <= ADDR_POSTED_ZERO; elsif (sig_incr_addr_posted_cntr = '1' and sig_decr_addr_posted_cntr = '0' and sig_addr_posted_cntr_max = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ; elsif (sig_incr_addr_posted_cntr = '0' and sig_decr_addr_posted_cntr = '1' and sig_addr_posted_cntr_eq_0 = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ; else null; -- don't change state end if; end if; end process IMP_ADDR_POSTED_FIFO_CNTR; wsc2rst_stop_cmplt <= sig_all_cmds_done; sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and not(addr2wsc_calc_error)) or (sig_addr_posted_cntr_eq_1 and addr2wsc_calc_error); sig_all_cmds_done <= sig_no_posted_cmds and sig_halt_reg_dly3; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG -- -- Process Description: -- Implements the flop for capturing the Halt request from -- the Reset module. -- ------------------------------------------------------------- IMP_HALT_REQ_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg <= '0'; elsif (rst2wsc_stop_request = '1') then sig_halt_reg <= '1'; else null; -- Hold current State end if; end if; end process IMP_HALT_REQ_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG_DLY -- -- Process Description: -- Implements the flops for delaying the halt request by 3 -- clocks to allow the Address Controller to halt before the -- Data Contoller can safely indicate it has exhausted all -- transfers committed to the AXI Address Channel by the Address -- Controller. -- ------------------------------------------------------------- IMP_HALT_REQ_REG_DLY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg_dly1 <= '0'; sig_halt_reg_dly2 <= '0'; sig_halt_reg_dly3 <= '0'; else sig_halt_reg_dly1 <= sig_halt_reg; sig_halt_reg_dly2 <= sig_halt_reg_dly1; sig_halt_reg_dly3 <= sig_halt_reg_dly2; end if; end if; end process IMP_HALT_REQ_REG_DLY; end implementation;

bsd-2-clause

49b7c5af5e777a1b9e30b32a37cdc8f7

0.411564

5.10646

false

cwilkens/ecen4024-microphone-array

microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/cic_compiler_v4_0.vhd

1

14,842

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block hNU1Fw8N5flzF7Dghvh6XU+XL4livwFhgUKirojOUYwyKIKeUh7nyLwO0FOegpo/MFH7aElslmiH WCSdhyjBDw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CXbqVSsRUpRk0hgCZEc+6DFcI860KQJ9aXS/R/aWZ44LeB7n/KNhjI0UvOcvG4qKgedNZ18erSkv 4NcXxTL51ZANLRW4vV5G63kqA33/oTvqZ29mRbUlE01gRDQzOR00+nqjWzfeKHex/3Cd0Kje2bas bOdiv+p4vxl6MQaFL6E= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ICxJUWvywkTB2IX+xrIyFqh8q5LbfBkmhGNlHsAFyOjP8AutiwPkvKMJPcbsaEIMkoxqclzys7Dh VksOjN+EZIcGgVAo96+B0dj/e4nBqTDSXWKnrRlZ+BdwlfBvpIiohPy6hN9lxsVVfHBGAWd1uYBq muudxpLZJ20aVw0jmgVJPWtYzOCt4b4bD5XF21wn5V/98y48G9iJ6nsnADHiz6HVCRbqD8A8AXjJ engogkxMp+5sqFmnE6DPcE69qg/lum5Hu8+Br/xleC+NZo58DezDChri/UJrviiXT1lZisxtTQ0k 3yxPD76y72VYT1jciKyc0UD4GlLzZ3RpE41GQg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 1okb0g9l27Ks0+k2riB5pSTUvnU2Cmc7tZSLR0VauQIiKfZYRt569YCYIpKCZMOI6dcOmrhZ/2mA k4Hin6HCBoTVr+rdfv0hH1txb2ata4EMDg/cqSAj72EyNYbkuVaTHDyFUlXDq8vHoES3VnPTbo+0 SuOpbgXutkKZOPemao8= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block RS+gKMWH/ErKVYRpmPl5v/MXxJm4H8IkrCOWuAET1H/zTcAOZoEFCLKY/SRSHPv9xRMOIOCzlWlk +Nkd22GRGnDjJyDpbjBi2A1o3lGHsesDzKSMedwMs7h/wy752JwVKXzamhtVYwElE8b7IQ8tqkAq 136dFy9NCwW4iqecOxR4xI3u2ECR6BTJFLXYi/scLdXXAhUQb8KkOwBtohMzOTmXRDAAQl7TWKbw rmADAtlFXG4uWvoJYEU8C48xsE8i+WItDtK/Myk09JrAld5mIhGqacTd6jjmdBN7b+cs2aZ7szaw t/pi4HPhfg0RSAklB9kxNy0t1EV56cQb7tAubA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9248) `protect data_block 8Lff6nfhbdeB/jQQjslYvQMcIi/OoiaCgZGTr3lLta6wK48AwIAxrUUCHkaZjO+3mPLRc+aco8O8 X2pdZ+YbwiBuWYDtAIMsp9EbtZO2vXCNxMnDs998gQaoEvO8hT1FzwLdQlmdRXq/W1r6s3wvgm7A MljRzrYTFukTeDWNetmQPvvEckwOKZhfjm6eJZxZQ3vBT7rTMRJrJNYnUqP6Boc5R90uBlDiuOaG JYLc1LNCrxS6Cio92dZhBJwgIImzAHQY6PMY9Pk+m4xH1+w+tBtpsN/m0NeomEwUB2UQHKBh4sKr xBjGnOyPW5ATNrrRuz6xPEAFWsV1eQy2JNRZ/eaiC/oxI4bvdZfiKO63qCv+WVVwLV1TOZ7oK8Ru EZ3y2CKNaWJQhapbfP8Y3XK6pW3ipAbOvIXylkMk4zLQzCC5EwQfhBVmaKdRiWyWL6kKc5eGOuE6 GEuzrVjBG7QLxhlCYxHlKJDpM06OsGi9VF68889frlHn9pMdcNTwJrzsrOkz61jeh3DdwaCIJz8p I3C3HsRb27AdlKgk+ZGodRHpp3Rp4zH4QvnSL68t+H7dcFK2RK+6KTOgdvIP4GTIx3DY10zRfx4j qDJDn0OI8PxHCowE/R6rTCbesllxA2rLHTltwSvogXGaY91Hg5Y83bsDCLHHHTt1ngNbUhgDcDRc uJLr5JO1FvqdO7lR08uptHO6r75rSRZOHuwloa3ezjrGcXeRhJ4iXG/gVpWynl19hHpwgDT7o36G PXTEBQTBkBkB5DtfgNx15AOrTFLT/pNdLZth3qBH8Ox4XcLWGNOcdhPlACbbBgsGzqLFWmhVEkQi 9rjqlw1zQqBiioqtMfAPyIlLnhDTsJmE26Z+BmHufxJROqcz9BLzPa6G9sRyFSa5BontJkgtFPeJ 3ZSJ6fjqYRhjQjoNin3b5raNew9EKfWFGMR29ZHJUrURZDJnzOhnMFB8k8axC3S13nRx9Ea1gnHv zshBKZRyyjl+otZQhfzMG0NZxW8eHIC83S17ItLxgdyynZnicabnt9oXlWZaYMXGYn4e3/IjRXor SimFaS/yc0aq9QbCrLXuNHZ/5pU0qc0F+Ei5uzVXxFySUXbARnbKyv5hTbrArvFapZOaMmwjbtrz 8RLSCVL9Qnfou5izTdOa4hKav7NesICNainTWqdpodCKWtkxT8bQ53OxeduLCJKuNIoSrMIGReBa GhPg9c7EbBT6JyRt+f6xq+wUpRfglM1MWhjSjQxbp9Dv+CURSXVmwjkbHx5+EZEzvU6UQM49uI6V pORDj0YtG0x/kRqnL4EIImoiq3DeF9BbksMqnvUZmCTqkB5NXQJeQfPU32pclSNO8F8fuMImIG3k tWtpyZP4mSdexDHj2bJ4oDYWk6Z0FpWn0eyFTU89ximBQ2c9DtRghrhkUZ0KxqauLaVenY6UBIJ4 dW/JAgkFxrlnihbKWOaGiH1nfIC4+dgN6MyBJaVaqxH5FQlPGcNR0cee21Uv793VWPL0oHbZuokH 4fYpVUaReDeqP8j5KBQBEhDYIT4EUMTVVbj7CopUEYhgj50ZIUUJXMXE0D49cPmobnJ3HoCf/0Al Y1yhTnV0Jhjro4ieC9FfHXMIegyxTWpa5nSGMJP3rpkFCzBGOBq8IiIBYS8sj0ji5/5JkZP9tVzu ZMJDGviMe+30FaFyHh8oB11s8c/lPW1HrupMRpdzR/4d+NjuN+pVkEonTc6N99QWGdmbok+NOfTv Ks9uYumKyMnE11XUSX/pMSvnFwboJ8caH9uQPnaWu2XXrwQiXyvU7KaaJE2KSmXQ2Yt28J3zmoLV EIJhYP0urrQACRbgVYaRz62zyDqE+gkh+v1g+hYM7d9vAHRUDIp81K/TvjCpeaofgoq3dSrS3g0q 1Ue06C5dWE5c8roP9eRCbJpDuSyrJrhbSVhXoSRWI5FYKLwFJRY8bfldTPpefcq/kmbQ56otvAot 9HDyb0mdRHvDCzZppzFbNDDsYN6pQCIp3+KP/qEEo3EHAEt6LcUQDy5UbfQJKrAs2o6Pg54lwIoL AvPXyq66Y2y/g/zaor7Kms+1LyRDIKaI31YISs2ZTh1TBMiHRCVBMjVMFL4fkB7PRzrFfGNahAJS Vpi5/h7owA67h/MoGEWQP5m6lFg1gzbLF7Um+CzaMAU4OU60kL48my3YxPtP90voe5NqKtyh4aBD g1HkZLlp9cjRM7qOPQzrXgphzNGd+5I8aa83WjUjrHAauxOdnpCRfevLTyYwjnsHtEcZX3vnu+zz Qlzn+HFwsqBgwBGoCnYOwMtecvTXR9ml+DJ6gYinZVOPHABxhAnt6NslCiVfeq5qcdLa8w+IXKU1 kK9N9ivr7UzerjQobYswj2ZsSf4M9oPHqw/pm0Fj2rAleqUheXVVNv7nIDuRQGApN3QT4WijpUaW FNXoY0AnclfXw09a2XVk6ICgURcXgkzfc+WNY4rYvkllM4A7tIy0KDVrxvL1lsjoybQkjx9+hH3U Uk+9MO5GOwduvMshY0wVuQMln+7ZETTnNbcykmiGZrzuaevXc+7azfWbxV2utDv8LesCoY3BZOj5 BKcEmOuYNLS6iiNrs+YRVZO/q8RkVeS3MCkQuvFFGAkASYECM+NpV0MceH08YtGnbsX1s3L50lvp 7VQBRr7T3R1HnnBmvyw2VU9QZ+eGaUJ8gEU3nPH24Nxl+rwQl63Rc+9QH7LSRN5s2SSpwtj7KUPx 1bqxVrsQYJvsgUpPDY3VPWCz6lsMwDUw6kK/PFrPYpfI4pGZwRSG6HFFYSTPxmIY/igBA+JH6nOv 2ZMuPpouutNWNfoU+CnccuJ15mWsSAD4BTbrRVhgUxW8IT6jNAKUzE2MGGbqs2PwoSPcsx8lmy03 OGNhii3zws+GtTdPrMl1KgPW2mMCqsQl5G2mrYEVB8G7IwnDEjXg2clLYsxQYHAMsnbkhPv6ybFb 9x63mNgrTEIfrn+78dz7FPuofc9KhkkF06rrH96B1bs5SoK59WYMdkh8t+FrLVRGLNmwCAMBkxQP iRGb8RTIENpfNNUZpuqX3yRM843xDhOGf9oMU6BO/VUS80xDpt3HxJlTIoLiVHKTCbd/o493jPvZ AbcsC4dQ6JrEVbZu1dqgPFEApanejqt7Ic4sbIlDmeOVtFO7kwdB3JnY+htkNDvfslNiKxvYZZuD ggPltzJpqlG4gKt1AhQXHXDnwrO9tZ4+IBJi+a1i2GpmCWjE4EeZLsU7UCWb8cfBvo70kfGPhKsn iTNrOU7BUCQpwGqfqE2TgYrgZc1+FurOoaErY7mrWy0iGLaOZYCLQ1wsxTdqgreTQYWTB2eceI5g qbN0AQuyF6XU10PLIhpTg0AElVT6pKl+vodzVH953IdQOo7c1TNwMjhNhOg9ECnsXvxgaTw1+MlC qXqbaA9F5aqgPiTowjU9tiCtKfaWNliw0LdXGiKlnROXSBzX7j5LW0LjJzWfDOR3HSY3jzwxDZBb wfmNA80DaN8qCZ9iWOm1hzyXdhlIkxmyZF0fHpBpgvKcCN/1OrUGLDUazzWvm/9nXk8JElMzsvIL oZ0JJpWMNqLeBRwHAeMblfIhx701OeWTNmXKUM6RlMDYxcjrE7lfHZ3ZH5PrNgDw9UqEqYhc1THU KHfCOEkLzo9DmlYfVoPgsRIfylNeC+BMbyR4yb/ZlKv3pLx2q5EFB99ZqCboGdstL5irlQgnW+5/ z8KUtPWFn1X9igOpLvJuBI8khYtDzm4GLBQEH+tL/D8Yzqm6R8cPtZXNTJqr5Qox2gVA6s+O5J5I xGB5c6rVwIUI1EIg9M3x3jMQ94W7pJN1/kXM6gSOOMTlQTrt6ADez6yyL33QaKauQC0CGrS1iv0t +clzq8TcgmnEnWbQVRbpAfEebcNrJPWJnLUUbsdRk03p79Yo2+dqCHqUG/mt331Nr+gWBbNcSflh yfflTiDFrNpIPNg7GEdK/IN5v8k1HMj/Atssmi2fMexc/mQc5gWRxNWVLshC8xoaaCIBXX1NL/hj be+l2MH/sAUc4hUqPLgHr8lf+B6SrjH0hIH/VPXv1IqNsxILP+IJm5otFrXBTyJ6Eul8Gr9vbHEH hPBTgPpZAja/3gWEkFw9ypMGaC3g6q58p0/f/fFR2uaVqa+m/XRfVybd/Hf9uc4E6Qe9WADERUNe Zm5d+IhuduRjlnPySjPzExzMJTfDoTDqw1daOhs00d0dy8TvIR/l4Y61wOwheKA9AKNyoc4CFs3y eZOH5P2Fr9fzC34B+L14czRD4RR+5kOx+Vs/NrhY5UR0Ha0Li73EHeFPa8xQuN7OPdWPuUd+k78M 15swYouKz6VI4FqEeRzhSE6nu4KIOPDUheZ/AIp3E7mZvLCvYfRoavWIKTCKaStQXESe6XUqibt6 6GszHom93Bhs+zeAwUK1ZP+ScV77DzLYIJ0PT1+wIhD5c6M4WUwZR7ulLNuUywEX8PcWYwNARl6J gGVkWAxx45W/dMkxbT8nrbIeTVi0tEggPmPcTD+j7pnyfqMb7Iqd/2dXey6a6uqLX+Edl0h4FdP1 jCVSmJxk81uUWYPeFVzh9iN6UKWn4ISuNx0f0mEqKDoxIkT0JkiJXwsGGFuYACWTkKY6sPgxiHjK Sl84O3Atfipfcp5gCPG9PjxPuuPrl5aTbLLA9oLIwTZg47CzqqjJTzhWyiLPgpKFXjw44ItK5d6C 6FNyjDlRi2/EYpikPhjdg2u/1BBBWJ4KvpRmLZ3xLyNtRtJ1P4/+nqyy46/P63fzPDYQOAavTbvV 0FPoEaRhxvuRTwHB/rQRc7wv1+UUjx/0SWVyHZxhRjpd/23W7zqcYnttPE7Y6T3t0T3MflUjivTv HeS38N9um7P2TIoVMxROuNFtzW3xKT82JmQog5lmEo+eDA9y7B6atZg0vt35JAED+e2N0hw/FmW5 7kr6n+STX+Oi5uWb3Tf65+UPtmyBxFCmK48E0XhbA2HGUQZLvnsORMcZD3k4i0odJVaU/QCF2XVd SRpIJv3G3AFX4uin5KStXUErb8tOe1SQ6CySDgJD9Fp/B/E4Cdo9JWC20tgYRdDptnyON9pAcDje GJ6KWWl77h6+y1wVcjAfy94EpANY8boZNPrNPZXOf7QS7ZPwdY3yA3xP1/tPaZ7zwpKRPPUzKGHl LV/GlfWilUJPdYFhziSKQEbr2c37a8EQqk52ofCUmuXDQK1nCUUrMSYr/Khm0ctsA5V3JEMIQDDv SILWpbSxdWWEmD9PiWoqAsnkMg9bIkpeEa73B7XUD04+kSZmVJ4V5wC5Xmr4CYcivdOaijmGBBK9 pgFaXm7yziinqIXlF7KPy07NpIsui193rTc9QOWwIWXD6lpFJs8GmuObD59AXvRV9Q+ve+BtlNj5 D3p5CWhrhLtYhWb0FPC8ETaX9WGAdP/VBXhLRxXSh8wpODiwRxID5xCT+69JJErHt6H6UnunyuQr QMMg3Xmb5YzlSZFaqqjWfxl+h8xL/wriCaLqSt7/EWPDBjpGq5y0dX3bdq3+m7Bt9JLbqp+APbdk JXVUMFoQIbJjg7aHggffgN8a+sXVkBBmAe24Kg2Aei6tOpq8kILhAqxQlgFD1+wxXTO5cUIR2rz+ sK6PPuz68gJPvNneDzIoueSmVriY3Wf4VFilvu7eF4vVAW/c+xHGexXGoOAKUD96dXKQ3u32Vg2D 0RE3HESdUy8bU9yKF9k+hSL31046kBWmFzPLZoBud9BX5xJJMcdvi7EyQSueYcclRVNqsQ9x5pKk c/LD3D1hjobG+aifrVz/VRLQ2/WZ78wmWHiV86N04892BgIHqhUzVJJQGGVQVMcjX1fFCoEAdFZT fA2jeNdQ33p/b3py4/XI/mct5axOq8wc5LUWPnMrUwhbfOzZDFi249F2tzzRgqUK8kXVzjoaeGmP fth/Di6ZY2PHmUqZBhLSX3EV/GxuAVBI3+uBmnwHElTZhZ5SQdKXozDFP6UgQtnaK0yw0e5BBipz UZ5s4bTDmmaAEezBMRFnosWFp8F08y60MfbmnqNxJgR8SnIbgkYe7BXCnGcbVd/pTxuhzYxSL2Yi 5loM66obFecjMZchRYaDdELyfVXqk8IPbiFKXINQnXfCxg9en76yAJ0SNplG+eO24dMCUVu6/aj0 b+ukCtHPwtOk4BXmBNzXRk12BXXOBbszslXRGJzq4NZTjcksdeZo70ltpkWu35Q5ze5AvI3QKyaa EAmYYf9Igknu4G8qJn6wzYkQ3ZGsMjJp0gsLGwJbANEPt5zHrg0rPKGy8NLNJJrQLEo9hoxZUUKv VKD5WNjdwlgVi4zFGZ30xj46qxxOMPnKyIb73K/PCCnyFr3lBdMNvCL58G6kGG7pg5qiqSO3hw+j qpyO66S7NHu+usw4b/89seUDmdyzz7k19abep4CwwcO5aF5KTCaWFluWFK6+VGXGxoMA0W7HXfDa 6xIGRp8yj+nKTYtQuOX5ZSta9ct54vwOwFKX0kOCP4h2I3HSeb/jPx4r2pAwzqWm/BTfIw0CtUPX DTqi9mlZ0gvblQKm/ARwcAx+6UCwubn2BihvuLLZ9B+i+Y1sz9l0Gud2aInu5/ipWh1MxtQLDprR CucDNEVNqz4Ph8HKD49u/Q+t4kNMSCj4nCGdBzzQzKLMRsTaEc9TlmnNWu6cJkUTGjCb3HofPsd6 wRpLI5tO22Mt2lgl7+d2jcyAMctiyjCsyjvsIOEMGfrVfRsoBcE3BadfHrA2edkosRLGlEXLgX2z YHHsZXHpBXEQpWJQr/G3EDJTEqqSO1vwllp28hbWmRiLCGosYFeYx7USobrGQvTc7zu6M0P0sOP2 3J/5FlD8SRIgBtK6qxRzJj/+/Hea0nrAJXWTteo13wv29/bEbrlhcA6Xjr2rWBKRvDDGFhRPWaNe 2fAAK25iPdKkLPc9oe2a66kEyBGiuyEig1/DgpkfLHVDkQRkr8Ooerzi60TBWHhCwoLTU2TV7O2Q M2ZUoEawkMzjTe/tK7Wh96zlcHoqsb8gjaNeV7wTGqPSJD0wVYnLqJ7+uu1sXFt0PsVNhmrn4yaL XOnw3H1LnHVC8WVo5rkYOHzaJSLhVWyP2SQao4sLp8pqG3+qG4QhsAu/aqQIMNSjtdGpecZFLkqX VknhvffKoz+DIksPWf4Tq9n9TwQjRP3ddq8mDvAfRCiwsTRCy1eFglQw4xQmN6I9i4FlUYfKdzeK /dzrKTJq0AjtvKDTQqdw03ksYQp2HEURYVPzQn21B9lxLQyUR+7mefZqZewG68WgFdXRUdjhZ+5b g972czfPc9KKTCdTJrOSlQmp0fCUUsvCOCuOJrNEI0er0eVSkC9GfgMs9OO1ra/hl0WVlHZfFTLt kXhmejlMjPEx5m7n4m1/Wcf5gRPficCT2X3fdBBWGBBtz9z4qmUMsCdK0KCypCpGA0Ej3C8+zCNr tdHoTwOAwWHQrsr8xjaOv/uySuyaB5A9YDQwvP9OV8cSNQgUCitAwlnCb15VwujqWdz6jujo9Vus SlStCVNXN/q6v3tL9eQFAnP5IAHLDaAzImhKynbiRTr9IOoGBJKYaxTMCC+dZdz+K/UykysxIb+/ UelCBz57pxMUvR1NEVPeo5HNGVgsWRZRhqx76xPef8RApICE0dpn/Hlh0oBKLim2Pr0uW0AwX8lq r3Bv9wtI0scj90454cpxcwAA4+t8GjPTb4AiLi/9xaFzlGr2cOMr9GIkU460JTDidn55Mv+rm//F /Rt6Z3Eaj/TuMMjCNQmNGkfA9GwbsWVZe/LI+ijzIPac7/EIHXrP9VsASmfsBjF44I8GTmIYgeV0 jdpjWn04yrJJvpCi1dpgYJm8gKCaAJg3opUJKTUmDmW7zcszqBIgTIx81y6hcQQNKBQvod5sEP70 04KK7jJZdOP6zprBpQNfpFwpdtv9vFAywb2sl0mI+HLvVCDc5SG47wjpjgG4nn/NG4Eesyyp964V 7GiFbawLzMEMlQyCvO35kQjRWGsU6stO5bLTPBnBhv3cW4z1hHHx0XPBQvduHjhkyLrpErvPpXuz eZXhK+DBsGgMJkas9OaBBgIQ8/fvjYtbV+BWoALk5TmDTmA2uFJuZjdvgrPfaU20GUzRGKmrKGbG 6OTCx0JbuYzQKrmc7/HIsmbMIbz725EcwypP5cX/avjT8pexnBXjNHYgWO3S6/wp8UZY0mCi8SsZ rXWFaktd17YYG/LXCu9+Cz23m3IR94IRU37js/xhWKOaJLOsb5Pbz7hOwbChLvCtJGMNC6pUO0g/ 6zQmk2ygt3gw3D1o7xMNIVXW6n0uMpBC1bzwYnUYw83ESSp8CeuiJaml3LwrYKefR2JBxbM076KG ZEHWtDogw2fTB6BjkEjUFcJgSrtq7v1M1ZRorrAcTEFfs1oBNCUBmxtrKf4kh0Xb5jXtic8hyBxy KCai2mzYRDR6lxtRNw904t16NaaMi0yHFJKZO274ELViQRGjTnjmOLtwaR2Mv9ERb+eQ5tjEfumi JiMnpSXhEkjlrBGqN7Vtsg3zLEyBUt5/kZ2reFWtEw6iSJaWbPMqUl2IHLmb7lyHXIko3skU2iwk mAl70zgkJNv/a4RcZoUvq2OY9qAZtevVzlq6YLtRbGr4deH4gtYhSlCgIutX0F0gcwvD0aKUaZn1 cQZJch+Eyr/WYV5wUUTlR8YuclYd8p5obqhVgPPzPvIncvzMNpYsKoZRlwNqrkO3s/HsoztMmBzH IdR2MipYEPOclOk/eMDfnGL2/xapw67/bWWDOu4hv++frJuAnLKjJhc0Hznx2IL3WUOvl1YjHLG1 fc9HWLnwLjN7FEFmriKTePDyO9qVTavZqvQyCKDQEXyhUojsQzGJ8REGiJVjtBbsYMhyW09A4qLC lwHCguzOp8YrAcuJlmJmBmujXhBqICXoz8Rr0ukiysjhWINR5Suekthna4/fKRujSrmLwQ6QkBAi wCcmNJondvSGtdDhOoYvYXd2w4DYl+vQiwqX9x5b9HkK1XnRf25EAnzg1sJvcWBC3RG+PEQk8B83 fOGLJOSFzTVXNP0nz3eSxUg7QDhWMPMvOZ1qnScZf204vh2kSnwXb5NOFT+G28UkfBPW7j1JA7pA O2F/nOUIgLMHvQX2A2j2UPQrWDhEFQPcHOItCNPpBxhQ/cqKrvLorY2iYpEci7VH2GqGu2x/2B12 H/FJ1Xq6F8nksIzrKyHgbAAPCfLGjOtxF6mJCT2MM85DyIL8mAIbRqhQsPM0zxeJ9cW3yCCoAAld dGmAK7uZEPDGcav38eW9G4+8oWTL29AAdnyXnL05OMMqSo3I7QbKtttf/G7i6RgGMPAsTaDuYWyq C1ARLc2wJw55+PsQ28Hqur6kdqvhypIKPXFFy1Cu3tp1VpeXRxO7zq/LNsa2KAN20f20JdqtYPzW c7KNo8V8SXQWZEvsFv90VrNshGOGxzeYXQcXA5ZLIVa9L0i58LiGaUFrYBDMEduevl4Q8AqBXHlB iUiUxPWoCfGSGeE7XYmKjDOC2h0y9wvJqV1w1qQU6VA/JiHTEhvK47dmRYcGFC0ZiMDIbiWczixU v+iLS18FD8vrLK89GzkAoY1baFRg7hzdF6oi0NzQLw3JHgP+BKxhmfjPmxggKGotN452Ev+TiLGk 2elkKOhfdCSZqGmw7slLGJW0x87Y2RnDXEbtvzDE+d8sPa62Nah8OMCfOkYYz3d85p1yAQKPGenj AN9/ZZUd5aMBl8DL+SKe7p/XoGMrbnF2SlgX0BvpDSWknx3OlZJDRJQehbc8WKPMBuHpER9nzU2v ZSewtmZPl8NjJhnLwm+DQXdHNQtoF3+WJQKfWSSJTxDrBgbvd1hDma2LeSwlUf5B8qr623MKvFWX gbDy598O3R5RXIjktth8LRv4Z/osFsjYhXKrFDJfdkhFMEgZ5l1V5BwHBDSokIgOAdGN8N/5Qlkv MCNUO2SdZ+z/WIevW3aalSgXKiqns8ZiKOE0gQfTXj+HdoB/ZFTjssgrKXwOcoA/y/p9DHLWjc1z JQyy/pOQL6x9YoZfQaf7lynHhztdQlQAui7uNu/Bdw1qSQSJZUnC1GVCZvZRXrmXU0D0cVGk9P5E ToPKjwEfvOFOIMzlCNYY9/tOImas7g2lRXafAPa3AZSFO+VZmObtQpP7GvuoVkSyAutTbWCWKLTH 8szDT/3kumiM5SErDKiUBhEO0Yg+ahw94qHWMuniLgErhAXuMP3rMd9yz62rAEBBKU70aSD94YY9 DgDw23wAaL//HMjJuffm7RrIIW4tF+dT+WllxQLJU/HMb9STgIEirxeZO9QFr5KKcnrRYKl1yze9 csLa/H3gSY58yM2k9rC13ZjTTy9r1BEF/MEP6aTBxgSMkl7fjDcTmeP58sMad8/a4eLEg6QjY3Wi 3TSgF/ernqh2p/pMzIivCWuC90YoWINon4IH+VR2vp+wiXJ4E2zKOkwUyh2pnERF4bgTLwAORxPc LebgqXSKSiUJGHjIoD3tJRobve2Yjn9CHV3KA+bR2NKZHC/TZ4BnzW50H4PvHOjDHC83LgZWkOD8 95ELh9sqMP+ejfaXox2kbMptD1oj4SjlwLiwafe6U5cQoqeXOQgKsbthmoPDxmGx+O9qsdw3OjCM CLtw4HW26bOHPfbd7J1Oe3BBXriYyFUM+yIoiQuhZ4FEPHbEXb5a+uxe4dAXHEAwTzzse43izXsa WB3BraDFhu0MAIpHsCIt7tFQo01UumVuJ7iAYHxe8WFEUrBtzVhAipP23R/ih4Zt7FMAZ2enrH6o V2LRbXftDP6khEFzOxxxEBfpEz62XjvLqv8tFaP3xZTrOo8S4kZkVPhMfl+H1MVtEEh8uRjaXWRd BeTGZC8yO5DmnNJY7cQdnJpHm9r+fc/WDzerLrRoIdvoaFtr2+ePAfV6vw4gsxzx7Rq0NTeVtYP+ 0sMvMwzI/CBe7bOF1WKSW84RxbgP9w+ykNAlJ+C4knnICPUaZVAqEoPxPCodrRG4GaTqLMovdIxw H1xIOQBtc0noLF4fzG0Q+JQ1S38YS0nJxJnv6x9BdqfEu/FZvDATRHAZZ5yEidtr3WQQemNAlcrM W5YXJ3T+BoUVfV3VUVfx6GamPjClp73VADQjKXqBw4r43l5BsK6hidUcqsXs8w86BxHla2ejLY2F jEwhc7B5xyd9bdOLUNUCLAcxkW4CXCf8Z1q0ULtphsk+4ku/PGMRv5zgvQsPlN5PzqsRG0mw7xyV 5PeOKIIKYI61qlbj25PuTc3eef9jhMYndd80r3X3ZYxBlyYXeE5wZje0owUk5ibKdX+xVfNSaGLR mMNZK2OTRFUjYKK2p2PUEURwzq1sMGe/dBY2YJxEJVmDmReiFujrzyG2AKziGIQvblouXVCIKaqU a8I5xPosV0B5KxyPn7nO3U4m8a4Bnrsd1KJEuCgP6MmIyL3ayMo73r2+2HXHQIMeLqKxeaxhfx5d NaHIsPRhebDE2fG96XkU/82Ftn+zQs0saA/3I/rwzvgnOn3v33VhSJ6x71EIQX3B2ZGvKQoE47Dw +JR+sMpIqoGXoR/qAXUXGofFxvM4um2foOt996es4+/hGDBflawGUHS3oJpTnBn9RjdQnUvhjxUi hgSa17/HAY05mSeTxp2s/gAeqHuH6Yj1osTw6ZHPjpB4uVheiptnZeN+m3p84qhBBFGogvC9JM0s WKN0oG6UpcVXbaykxebvSuKO9QSyFNLKw1drA6qK1E2zGVP1u491FDnf9x48kBmBzyrpV9b4z+ol 44C8QtqxNDS/7EoKyFG70LS/Umxyh+U4U38WxJWcyiZMahTQ0OAnyLba8mfw1v5T0PEI2AQZG8RA Uren/IVS66rETSjj6ykVtcfCCTD0oAiIjL3Mrw+ehi2kiW+hWqw8OVuzuUxymOuGlhIkR/n+KGJY 2SLjzWKmq9+LQsATR47KQWoB4M1oXW4Br+jXmjZEvds5z66hWUHyunW09bahf7INEmhSQffgQpYt bo9VFr2v0i4Y7KZ7B8q48EXtcmoLpY6rrgHUDQAhYDG7dVBfxorAz00kV5icTa9UcAoEw/qyatwH 5Jal83kwczDPXrq0rRteFwh2UJNwQ6u0Fkhn0aIDcwpCo1efPUAH2BOYOwpY+I87aCxUUA7wxpwu 2Y/19NQ1kwY9hv/MamTDoyZWJuBSpspqjqfakEl+SzzKcrJ+6yUPD99nVogmvO2r0MFF0drWmbhh M7l6C28wta9j0HY3EoBFw8Mkwsp1mX1CpTlhOos5ye90J9SNjRYpOrzQK+1C5DwimRob8/K9A4hi 8wdEA6aRGHuSH3vlDpc= `protect end_protected

mit

6893f32e97b894fe1d24571eab361386

0.936397

1.884698

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set.vhd

1

31,018

------------------------------------------------------------------------------- -- axi_datamover_stbs_set.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_stbs_set.vhd -- -- Description: -- This file implements a module to count the number of strobe bits that -- are asserted active high on the input strobe bus. This module does not -- support sparse strobe assertions. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_stbs_set.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 6/20/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added 512 and 1024 data width support -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_stbs_set is generic ( C_STROBE_WIDTH : Integer range 1 to 128 := 8 -- Specifies the width (in bits) of the input strobe bus. ); port ( -- Input Strobe bus ---------------------------------------------------- -- tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); -- ------------------------------------------------------------------------ -- Asserted Strobes count output --------------------------------------- -- num_stbs_asserted : Out std_logic_vector(7 downto 0) -- -- Indicates the number of asserted tstrb_in bits -- ------------------------------------------------------------------------ ); end entity axi_datamover_stbs_set; architecture implementation of axi_datamover_stbs_set is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function ------------------------------------------------------------------- -- Function -- -- Function Name: funct_8bit_stbs_set -- -- Function Description: -- Implements an 8-bit lookup table for calculating the number -- of asserted bits within an 8-bit strobe vector. -- -- Note that this function assumes that asserted strobes are -- contiguous with each other (no sparse strobe assertions). -- ------------------------------------------------------------------- function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed Variable lvar_num_set : Integer range 0 to 8 := 0; begin case strb_8 is ------- 1 bit -------------------------- when "00000001" | "00000010" | "00000100" | "00001000" | "00010000" | "00100000" | "01000000" | "10000000" => lvar_num_set := 1; ------- 2 bit -------------------------- when "00000011" | "00000110" | "00001100" | "00011000" | "00110000" | "01100000" | "11000000" => lvar_num_set := 2; ------- 3 bit -------------------------- when "00000111" | "00001110" | "00011100" | "00111000" | "01110000" | "11100000" => lvar_num_set := 3; ------- 4 bit -------------------------- when "00001111" | "00011110" | "00111100" | "01111000" | "11110000" => lvar_num_set := 4; ------- 5 bit -------------------------- when "00011111" | "00111110" | "01111100" | "11111000" => lvar_num_set := 5; ------- 6 bit -------------------------- when "00111111" | "01111110" | "11111100" => lvar_num_set := 6; ------- 7 bit -------------------------- when "01111111" | "11111110" => lvar_num_set := 7; ------- 8 bit -------------------------- when "11111111" => lvar_num_set := 8; ------- all zeros or sparse strobes ------ When others => lvar_num_set := 0; end case; Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH)); end function funct_8bit_stbs_set; -- Constants Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED; -- Signals signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0'); begin --(architecture implementation) num_stbs_asserted <= sig_stbs_asserted; sig_strb_input <= tstrb_in ; ------------------------------------------------------------------------- ---------------- Asserted TSTRB calculation logic --------------------- ------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_1_STRB -- -- If Generate Description: -- 1-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate begin ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_1BIT_STRB -- -- Process Description: -- -- ------------------------------------------------------------- IMP_1BIT_STRB : process (sig_strb_input) begin -- Concatonate the strobe to the ls bit of -- the asserted value sig_stbs_asserted <= "0000000" & sig_strb_input(0); end process IMP_1BIT_STRB; end generate GEN_1_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_2_STRB -- -- If Generate Description: -- 2-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate signal lsig_num_set : integer range 0 to 2 := 0; signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0'); begin lsig_strb_vect <= sig_strb_input; ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_2BIT_STRB -- -- Process Description: -- Calculates the number of strobes set fo the 2-bit -- strobe case -- ------------------------------------------------------------- IMP_2BIT_STRB : process (lsig_strb_vect) begin case lsig_strb_vect is when "01" | "10" => lsig_num_set <= 1; when "11" => lsig_num_set <= 2; when others => lsig_num_set <= 0; end case; end process IMP_2BIT_STRB; sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set, BITS_FOR_STBS_ASSERTED)); end generate GEN_2_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_4_STRB -- -- If Generate Description: -- 4-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0'); begin lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector -- for the function call sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect), BITS_FOR_STBS_ASSERTED)); end generate GEN_4_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_8_STRB -- -- If Generate Description: -- 8-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0'); begin lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector -- for the function call sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect), BITS_FOR_STBS_ASSERTED)); end generate GEN_8_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_16_STRB -- -- If Generate Description: -- 16-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate Constant RESULT_BIT_WIDTH : integer := 8; signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0'); begin lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector -- for the function call lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector -- for the function call lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ; lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ; lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH); sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total); end generate GEN_16_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_32_STRB -- -- If Generate Description: -- 32-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate Constant RESULT_BIT_WIDTH : integer := 8; signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0'); begin lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector -- for the function call lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector -- for the function call lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector -- for the function call lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector -- for the function call lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ; lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ; lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ; lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ; lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH); sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total); end generate GEN_32_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_64_STRB -- -- If Generate Description: -- 64-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate Constant RESULT_BIT_WIDTH : integer := 8; signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0'); begin lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector -- for the function call lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector -- for the function call lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector -- for the function call lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector -- for the function call lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector -- for the function call lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector -- for the function call lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector -- for the function call lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector -- for the function call lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ; lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ; lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ; lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ; lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ; lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ; lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ; lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ; lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH); sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total); end generate GEN_64_STRB; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_128_STRB -- -- If Generate Description: -- 128-bit strobe bus width case -- -- ------------------------------------------------------------ GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate Constant RESULT_BIT_WIDTH : integer := 8; signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0'); signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0'); signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0'); begin lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector -- for the function call lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector -- for the function call lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector -- for the function call lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector -- for the function call lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector -- for the function call lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector -- for the function call lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector -- for the function call lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector -- for the function call lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector -- for the function call lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector -- for the function call lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector -- for the function call lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector -- for the function call lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector -- for the function call lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector -- for the function call lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector -- for the function call lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector -- for the function call lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ; lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ; lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ; lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ; lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ; lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ; lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ; lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ; lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ; lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ; lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ; lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ; lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ; lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ; lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ; lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ; lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) + RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH); sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total); end generate GEN_128_STRB; end implementation;

bsd-2-clause

a62f262c9a70673cb1e231f99dafce7e

0.441518

4.467521

false

Jorge9314/ElectronicaDigital

Impresora2D/TB_Reception_8bits.vhd

1

3,946

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY TB_Reception_8bits IS END TB_Reception_8bits; ARCHITECTURE behavior OF TB_Reception_8bits IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Reception_8bits PORT( Divisor_Frecuencia : IN std_logic; Entrada : IN std_logic; Mensaje : OUT std_logic_vector(7 downto 0); Confirmado : OUT std_logic ); END COMPONENT; --Inputs signal Divisor_Frecuencia : std_logic := '0'; signal Entrada : std_logic := '0'; --Outputs signal Mensaje : std_logic_vector(7 downto 0); signal Confirmado : std_logic; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name constant Divisor_Frecuencia_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Reception_8bits PORT MAP ( Divisor_Frecuencia => Divisor_Frecuencia, Entrada => Entrada, Mensaje => Mensaje, Confirmado => Confirmado ); -- Clock process definitions Divisor_Frecuencia_process :process begin Divisor_Frecuencia <= '0'; wait for Divisor_Frecuencia_period/2; Divisor_Frecuencia <= '1'; wait for Divisor_Frecuencia_period/2; end process; -- Stimulus process stim_proc: process begin -- IDLE -- Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; -- BIT DE INICIO -- Entrada <= '0'; wait for 20 ns; -- BIT Numero 1 -- Entrada <= '1'; wait for 20 ns; -- 2 Entrada <= '1'; wait for 20 ns; -- 3 Entrada <= '1'; wait for 20 ns; -- 4 Entrada <= '1'; wait for 20 ns; -- 5 Entrada <= '1'; wait for 20 ns; -- 6 Entrada <= '1'; wait for 20 ns; -- 7 Entrada <= '1'; wait for 20 ns; -- 8 Entrada <= '1'; wait for 20 ns; -- BIT DE PARIDAD -- Entrada <= '0'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- IDLE -- Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; -- BIT DE INICIO -- Entrada <= '0'; wait for 20 ns; -- BIT Numero 1 -- Entrada <= '0'; wait for 20 ns; -- 2 Entrada <= '1'; wait for 20 ns; -- 3 Entrada <= '0'; wait for 20 ns; -- 4 Entrada <= '1'; wait for 20 ns; -- 5 Entrada <= '0'; wait for 20 ns; -- 6 Entrada <= '1'; wait for 20 ns; -- 7 Entrada <= '0'; wait for 20 ns; -- 8 Entrada <= '1'; wait for 20 ns; -- BIT DE PARIDAD -- Entrada <= '0'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- IDLE -- Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait for 20 ns; -- BIT DE INICIO -- Entrada <= '0'; wait for 20 ns; -- BIT Numero 1 -- Entrada <= '1'; wait for 20 ns; -- 2 Entrada <= '1'; wait for 20 ns; -- 3 Entrada <= '1'; wait for 20 ns; -- 4 Entrada <= '1'; wait for 20 ns; -- 5 Entrada <= '1'; wait for 20 ns; -- 6 Entrada <= '1'; wait for 20 ns; -- 7 Entrada <= '1'; wait for 20 ns; -- 8 Entrada <= '1'; wait for 20 ns; -- BIT DE PARIDAD -- Entrada <= '1'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; -- BIT DE FINALIZACION -- Entrada <= '1'; wait for 20 ns; Entrada <= '1'; wait; end process; END;

gpl-3.0

2d1d646577e6823ba86404ef107aee49

0.502281

3.366894

false

spzSource/MPFSM.RegFile.Sort

MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/Controller.vhd

1

8,076

library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use commands.all; -- -- Holds interaction among ROM, RAM and datapath. -- entity Controller is port( clk : in std_logic; rst : in std_logic; start : in std_logic; stop : out std_logic; rom_enabled : out std_logic; rom_address : out std_logic_vector(7 downto 0); rom_data_output : in std_logic_vector(27 downto 0); ram_read_write : out std_logic; ram_write_data_port : out std_logic_vector(7 downto 0); ram_write_address : out std_logic_vector(7 downto 0); ram_read_data_port_1 : in std_logic_vector(7 downto 0); ram_read_data_port_2 : in std_logic_vector(7 downto 0); ram_read_address_1 : out std_logic_vector(7 downto 0); ram_read_address_2 : out std_logic_vector(7 downto 0); datapath_enabled : out std_logic; datapath_operation_code : out std_logic_vector(3 downto 0); datapath_operand_1 : out std_logic_vector(7 downto 0); datapath_operand_2 : out std_logic_vector(7 downto 0); datapath_result : in std_logic_vector(7 downto 0); datapath_zero_flag : in std_logic; datapath_significant_bit_flag : in std_logic ); end entity Controller; architecture Controller_Behavioural of Controller is type states is ( IDLE, FETCH, DECODE, READ, WRITE, ADD, SUB, HALT, JUMP_IF_ZERO, JUMP_IF_NOT_SIGN_BIT_SET, LOAD_FROM_INDEX_TO, LOAD_FROM_INDEX_TO_READ_ADDR, LOAD_ACCEPT_WRITE, LOAD_TO_INDEX_FROM, LOAD_TO_INDEX_FROM_READ_ADDR ); signal next_state : states; signal current_state : states; signal instruction : std_logic_vector(27 downto 0); signal instruction_counter : std_logic_vector(7 downto 0); signal operation : std_logic_vector(3 downto 0); signal operand_address_1 : std_logic_vector(7 downto 0); signal operand_address_2 : std_logic_vector(7 downto 0); signal result_address : std_logic_vector(7 downto 0); signal data_1 : std_logic_vector(7 downto 0); signal data_2 : std_logic_vector(7 downto 0); signal data_w : std_logic_vector(7 downto 0); constant DEFAULT_COUNTER_VALUE : std_logic_vector(7 downto 0) := (instruction_counter'range => '0'); constant DEFAULT_INSTRUCTION_VALUE : std_logic_vector(27 downto 0) := (instruction'range => '0'); constant DEFAULT_OPERATION_VALUE : std_logic_vector(3 downto 0) := (operation'range => '0'); constant DEFAULT_ADDRESS_VALUE : std_logic_vector(7 downto 0) := (operand_address_1'range => '0'); begin FSM : process(clk, rst, next_state) begin if (rst = '1') then current_state <= IDLE; elsif rising_edge(clk) then current_state <= next_state; end if; end process; FSM_COMB : process(current_state, start, operation) begin case current_state is when IDLE => if (start = '1') then next_state <= FETCH; else next_state <= IDLE; end if; when FETCH => next_state <= DECODE; when DECODE => if (operation = HALT_OP) then next_state <= HALT; elsif (operation = JZ_OP) then next_state <= JUMP_IF_ZERO; elsif (operation = JNSB_OP) then next_state <= JUMP_IF_NOT_SIGN_BIT_SET; else next_state <= READ; end if; when READ => if (operation = ADD_OP) then next_state <= ADD; elsif (operation = SUB_OP) then next_state <= SUB; elsif (operation = LOAD_FROM_INEDEX_TO_ADDR_OP) then next_state <= LOAD_FROM_INDEX_TO; elsif (operation = LOAD_FROM_ADDR_TO_INDEX_OP) then next_state <= LOAD_TO_INDEX_FROM; else next_state <= IDLE; end if; when LOAD_FROM_INDEX_TO => next_state <= LOAD_FROM_INDEX_TO_READ_ADDR; when LOAD_TO_INDEX_FROM => next_state <= LOAD_TO_INDEX_FROM_READ_ADDR; when LOAD_FROM_INDEX_TO_READ_ADDR | LOAD_TO_INDEX_FROM_READ_ADDR => next_state <= LOAD_ACCEPT_WRITE; when ADD | SUB | LOAD_ACCEPT_WRITE => next_state <= WRITE; when WRITE | JUMP_IF_ZERO | JUMP_IF_NOT_SIGN_BIT_SET => next_state <= FETCH; when HALT => next_state <= HALT; when others => next_state <= IDLE; end case; end process; -- -- multiplexer to handle stop signal; -- STOP_PROCESS : process(current_state) begin if (current_state = HALT) then stop <= '1'; else stop <= '0'; end if; end process; -- -- synchronous instruction counter -- INSTR_COUNTER : process(clk, rst, current_state) begin if (rst = '1') then instruction_counter <= DEFAULT_COUNTER_VALUE; elsif falling_edge(clk) then if (current_state = DECODE) then instruction_counter <= instruction_counter + 1; elsif (current_state = JUMP_IF_ZERO and datapath_zero_flag = '1') then instruction_counter <= operand_address_1; elsif (current_state = JUMP_IF_NOT_SIGN_BIT_SET and datapath_significant_bit_flag = '0') then instruction_counter <= operand_address_1; end if; end if; end process; rom_address <= instruction_counter; ROM_READ_SET : process(next_state, current_state) begin if (next_state = FETCH or current_state = FETCH) then rom_enabled <= '1'; else rom_enabled <= '0'; end if; end process; -- -- reads instructions from the ROM -- ROM_READ : process(rst, current_state, rom_data_output) begin if (rst = '1') then instruction <= DEFAULT_INSTRUCTION_VALUE; elsif (current_state = FETCH) then instruction <= rom_data_output; end if; end process; -- -- determines the states of registers (address and instruction), -- based on current state of FSM -- REGS_CONTROL : process(rst, next_state, instruction) begin if (rst = '1') then operation <= DEFAULT_OPERATION_VALUE; operand_address_1 <= DEFAULT_ADDRESS_VALUE; operand_address_2 <= DEFAULT_ADDRESS_VALUE; result_address <= DEFAULT_ADDRESS_VALUE; elsif (next_state = DECODE) then operation <= instruction(27 downto 24); operand_address_1 <= instruction(23 downto 16); operand_address_2 <= instruction(15 downto 8); result_address <= instruction(7 downto 0); elsif (next_state = LOAD_FROM_INDEX_TO) then operand_address_1 <= data_1; elsif (next_state = LOAD_TO_INDEX_FROM) then operand_address_2 <= data_2; elsif (next_state = LOAD_TO_INDEX_FROM_READ_ADDR) then result_address <= operand_address_2; end if; end process; RAM_ADDR_SET : process(operand_address_1, operand_address_2, result_address) begin if (current_state /= JUMP_IF_NOT_SIGN_BIT_SET and current_state /= JUMP_IF_ZERO) then ram_read_address_1 <= operand_address_1; ram_read_address_2 <= operand_address_2; ram_write_address <= result_address; end if; end process; RAM_MODE_SET : process(current_state) begin if (current_state = WRITE) then ram_read_write <= '0'; else ram_read_write <= '1'; end if; end process; RAM_DATA_OUT : process(current_state) begin if (current_state = READ) then data_1 <= ram_read_data_port_1; data_2 <= ram_read_data_port_2; elsif (current_state = LOAD_FROM_INDEX_TO_READ_ADDR) then data_1 <= ram_read_data_port_1; end if; end process; ram_write_data_port <= datapath_result; datapath_operand_1 <= data_1; datapath_operand_2 <= data_2; datapath_operation_code <= operation; DATAPATH_SET : process(current_state) begin if (current_state = ADD or current_state = SUB or current_state = LOAD_ACCEPT_WRITE) then datapath_enabled <= '1'; else datapath_enabled <= '0'; end if; end process; end architecture Controller_Behavioural;

mit

aa1921cf7377b2f1df66af087b6d5b0f

0.61788

3.167059

false

Yarr/Yarr-fw

rtl/kintex7/rx-core/gearbox32to66.vhd

1

2,153

-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: RX channel -- # Aurora style rx code -- #################################### library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity gearbox32to66 is port ( -- Sys connect rst_i : in std_logic; clk_i : in std_logic; -- Input data32_i : in std_logic_vector(31 downto 0); data32_valid_i : in std_logic; slip_i : in std_logic; -- Outoput data66_o : out std_logic_vector(65 downto 0); data66_valid_o : out std_logic ); end gearbox32to66; architecture rtl of gearbox32to66 is signal gearbox_cnt : unsigned(7 downto 0); signal shift_cnt : std_logic; signal buffer128 : std_logic_vector(127 downto 0); signal slip_cnt : std_logic; begin shift_proc: process(clk_i, rst_i) begin if (rst_i = '1') then buffer128 <= (others => '0'); gearbox_cnt <= (others => '0'); data66_valid_o <= '0'; data66_o <= (others => '0'); shift_cnt <= '0'; slip_cnt <= '0'; elsif rising_edge(clk_i) then data66_valid_o <= '0'; if (data32_valid_i = '1') then shift_cnt <= not shift_cnt; buffer128(127 downto 0) <= buffer128(95 downto 0) & data32_i; data66_o <= buffer128(128-(to_integer(gearbox_cnt(4 downto 0))*2)-1 downto 62-(to_integer(gearbox_cnt(4 downto 0))*2)); if (shift_cnt = '1') then if (slip_i = '1') then gearbox_cnt <= gearbox_cnt; data66_valid_o <= '1'; elsif (gearbox_cnt = 32) then gearbox_cnt <= (others => '0'); data66_valid_o <= '0'; else gearbox_cnt <= gearbox_cnt + 1; data66_valid_o <= '1'; end if; end if; end if; end if; end process shift_proc; end rtl;

gpl-3.0

d8754e737856a86a4574addde67fc6d6

0.471435

3.71848

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/instantiation/rule_031_test_input.vhd

1

545

architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : component INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : COMPONENT INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;

gpl-3.0

440c69315cb811f4185a4c8823bf5a72

0.486239

2.809278

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_queue.vhd

1

53,845

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_queue.vhd -- Description: This entity is the descriptor fetch queue interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library proc_common_v4_0; use proc_common_v4_0.sync_fifo_fg; use proc_common_v4_0.srl_fifo_f; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_queue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_INCLUDE_MM2S : integer range 0 to 1 := 0; C_INCLUDE_S2MM : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- s_axis_updt_aclk : in std_logic ; -- -- --********************************-- -- --** Control and Status **-- -- --********************************-- -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- updt2_active : in std_logic ; -- updt2_queue_empty : out std_logic ; -- updt2_ioc : out std_logic ; -- updt2_ioc_irq_set : in std_logic ; -- -- dma2_interr : out std_logic ; -- dma2_slverr : out std_logic ; -- dma2_decerr : out std_logic ; -- dma2_interr_set : in std_logic ; -- dma2_slverr_set : in std_logic ; -- dma2_decerr_set : in std_logic ; -- -- --********************************-- -- --** Update Interfaces In **-- -- --********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- s_axis2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis2_updtptr_tvalid : in std_logic ; -- s_axis2_updtptr_tready : out std_logic ; -- s_axis2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis2_updtsts_tvalid : in std_logic ; -- s_axis2_updtsts_tready : out std_logic ; -- s_axis2_updtsts_tlast : in std_logic ; -- -- --********************************-- -- --** Update Interfaces Out **-- -- --********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_queue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_queue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs -- Number of words deep fifo needs to be. Depth required to store 2 word -- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2 --constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2); constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2)); -- Width of fifo rd and wr counts - only used for proper fifo operation constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1); -- Select between BRAM or LOGIC memory type constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16); -- Number of words deep fifo needs to be. Depth required to store all update -- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * C_SG_WORDS_TO_UPDATE)); constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * C_SG2_WORDS_TO_UPDATE)); -- Select between BRAM or LOGIC memory type constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16); -- Select between BRAM or LOGIC memory type constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16); -- Width of fifo rd and wr counts - only used for proper fifo operation constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_lsb_sm : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal write_curdesc_lsb1 : std_logic := '0'; signal write_curdesc_msb1 : std_logic := '0'; signal rden_del : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_d2 : std_logic := '0'; signal updt_active_re1 : std_logic := '0'; signal updt_active_re2 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; -- State Machine Signal signal writing_status : std_logic := '0'; signal dataq_rden : std_logic := '0'; signal stsq_rden : std_logic := '0'; -- Pointer Queue FIFO Signals signal ptr_queue_rden : std_logic := '0'; signal ptr_queue_wren : std_logic := '0'; signal ptr_queue_empty : std_logic := '0'; signal ptr_queue_full : std_logic := '0'; signal ptr_queue_din : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ptr_queue_dout : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ptr_queue_dout_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); -- Status Queue FIFO Signals signal sts_queue_wren : std_logic := '0'; signal sts_queue_rden : std_logic := '0'; signal sts_queue_din : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts_queue_dout : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0'); signal sts_queue_full : std_logic := '0'; signal sts_queue_empty : std_logic := '0'; signal ptr2_queue_rden : std_logic := '0'; signal ptr2_queue_wren : std_logic := '0'; signal ptr2_queue_empty : std_logic := '0'; signal ptr2_queue_full : std_logic := '0'; signal ptr2_queue_din : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ptr2_queue_dout : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); -- Status Queue FIFO Signals signal sts2_queue_wren : std_logic := '0'; signal sts2_queue_rden : std_logic := '0'; signal sts2_queue_din : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts2_queue_dout : std_logic_vector (C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal sts2_queue_full : std_logic := '0'; signal sts2_queue_empty : std_logic := '0'; signal sts2_queue_empty_del : std_logic := '0'; signal sts2_dout_valid : std_logic := '0'; signal sts_dout_valid : std_logic := '0'; signal sts2_dout_valid_del : std_logic := '0'; signal valid_new : std_logic := '0'; signal valid_latch : std_logic := '0'; signal valid1_new : std_logic := '0'; signal valid1_latch : std_logic := '0'; signal empty_low : std_logic := '0'; -- Misc Support Signals signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; signal writing_status_re_ch1 : std_logic := '0'; signal writing_status_re_ch2 : std_logic := '0'; signal sinit : std_logic := '0'; signal updt_tvalid : std_logic := '0'; signal updt_tlast : std_logic := '0'; signal updt2_tvalid : std_logic := '0'; signal updt2_tlast : std_logic := '0'; attribute mark_debug of updt_tvalid : signal is "true"; attribute mark_debug of updt2_tvalid : signal is "true"; attribute mark_debug of updt_tlast : signal is "true"; attribute mark_debug of updt2_tlast : signal is "true"; signal status_d1, status_d2 : std_logic := '0'; signal updt_tvalid_int : std_logic := '0'; signal updt_tlast_int : std_logic := '0'; signal ptr_queue_empty_int : std_logic := '0'; signal updt_active_int : std_logic := '0'; signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0'); attribute mark_debug of follower_reg_mm2s : signal is "true"; signal follower_full_mm2s :std_logic := '0'; signal follower_empty_mm2s : std_logic := '0'; signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0'); attribute mark_debug of follower_reg_s2mm : signal is "true"; signal follower_full_s2mm :std_logic := '0'; signal follower_empty_s2mm : std_logic := '0'; signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0); signal follower_full :std_logic := '0'; signal follower_empty : std_logic := '0'; signal sts_rden : std_logic := '0'; signal sts2_rden : std_logic := '0'; signal follower_tlast : std_logic := '0'; signal follower_reg_image : std_logic := '0'; signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1' else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ; m_axis_updt_tvalid <= updt_tvalid when updt_active = '1' else updt2_tvalid; m_axis_updt_tlast <= updt_tlast when updt_active = '1' else updt2_tlast; m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0'; m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0'; -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- channel 1 updt_active_re <= updt_active_re1 or updt_active_re2; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active_re, ptr_queue_empty_int, m_axis_updt_tready, updt_tvalid_int, updt_tlast_int) begin write_curdesc_lsb_sm <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; dataq_rden <= '0'; stsq_rden <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if(updt_active_re = '1')then pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor pointer -- Reads one word from data queue fifo --------------------------------------------------------------- when READ_CURDESC_LSB => -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(ptr_queue_empty_int = '0')then write_curdesc_lsb_sm <= '1'; dataq_rden <= '1'; -- pntr_ns <= READ_CURDESC_MSB; pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB; else -- coverage off pntr_ns <= READ_CURDESC_LSB; -- coverage on end if; --------------------------------------------------------------- -- Get upper current descriptor -- Reads one word from data queue fifo --------------------------------------------------------------- -- when READ_CURDESC_MSB => -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. -- if(ptr_queue_empty_int = '0')then -- dataq_rden <= '1'; -- write_curdesc_msb <= '1'; -- pntr_ns <= WRITE_STATUS; -- else -- -- coverage off -- pntr_ns <= READ_CURDESC_MSB; -- -- coverage on -- end if; --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => -- De-MUX appropriage tvalid/tlast signals writing_status <= '1'; -- Enable reading of Status Queue if datamover can -- accept data stsq_rden <= m_axis_updt_tready; -- Hold in the status state until tlast is pulled -- from status fifo if(updt_tvalid_int = '1' and m_axis_updt_tready = '1' and updt_tlast_int = '1')then -- if(follower_full = '1' and m_axis_updt_tready = '1' -- and follower_tlast = '1')then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; -- coverage off when others => pntr_ns <= IDLE; -- coverage on end case; end process CURDESC_PNTR_STATE; updt_tvalid_int <= updt_tvalid or updt2_tvalid; updt_tlast_int <= updt_tlast or updt2_tlast; ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else ptr2_queue_empty when updt2_active = '1' else '1'; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate begin MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate updt_tvalid <= follower_full_mm2s and updt_active; updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active; sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active; VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then -- follower_reg_mm2s <= (others => '0'); follower_full_mm2s <= '0'; follower_empty_mm2s <= '1'; else if (sts_rden = '1') then -- follower_reg_mm2s <= sts_queue_dout; follower_full_mm2s <= '1'; follower_empty_mm2s <= '0'; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE; VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then follower_reg_mm2s <= (others => '0'); else if (sts_rden = '1') then follower_reg_mm2s <= sts_queue_dout; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE1; REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active; end if; end if; end process REG_ACTIVE; updt_active_re1 <= updt_active and not updt_active_d1; -- I_UPDT_DATA_FIFO : entity proc_common_v4_0.srl_fifo_f -- generic map ( -- C_DWIDTH => 32 , -- C_DEPTH => 8 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => ptr_queue_wren , -- Data_In => ptr_queue_din , -- FIFO_Read => ptr_queue_rden , -- Data_Out => ptr_queue_dout , -- FIFO_Empty => ptr_queue_empty , -- FIFO_Full => ptr_queue_full, -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then ptr_queue_dout <= (others => '0'); elsif (ptr_queue_wren = '1') then ptr_queue_dout <= ptr_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or ptr_queue_rden = '1') then ptr_queue_empty <= '1'; ptr_queue_full <= '0'; elsif (ptr_queue_wren = '1') then ptr_queue_empty <= '0'; ptr_queue_full <= '1'; end if; end if; end process; -- Channel Pointer Queue (Generate Synchronous FIFO) -- I_UPDT_STS_FIFO : entity proc_common_v4_0.srl_fifo_f -- generic map ( -- C_DWIDTH => 34 , -- C_DEPTH => 4 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => sts_queue_wren , -- Data_In => sts_queue_din , -- FIFO_Read => sts_rden, --sts_queue_rden , -- Data_Out => sts_queue_dout , -- FIFO_Empty => sts_queue_empty , -- FIFO_Full => sts_queue_full , -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then sts_queue_dout <= (others => '0'); elsif (sts_queue_wren = '1') then sts_queue_dout <= sts_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or sts_rden = '1') then sts_queue_empty <= '1'; sts_queue_full <= '0'; elsif (sts_queue_wren = '1') then sts_queue_empty <= '0'; sts_queue_full <= '1'; end if; end if; end process; -- Channel Status Queue (Generate Synchronous FIFO) --***************************************** --** Channel Data Port Side of Queues --***************************************** -- Pointer Queue Update - Descriptor Pointer (32bits) -- i.e. 2 current descriptor pointers and any app fields ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- Data Queue Write Enable - based on tvalid and queue not full ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid and not ptr_queue_full; -- Data Queue NOT Full -- Drive channel port with ready if room in data queue s_axis_updtptr_tready <= not ptr_queue_full; --***************************************** --** Channel Status Port Side of Queues --***************************************** -- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits) -- Note: Type field is stripped off sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- Status Queue Write Enable - based on tvalid and queue not full sts_queue_wren <= s_axis_updtsts_tvalid and not sts_queue_full; -- Drive channel port with ready if room in status queue s_axis_updtsts_tready <= not sts_queue_full; --************************************* --** SG Engine Side of Queues --************************************* -- Indicate NOT empty if both status queue and data queue are not empty -- updt_queue_empty <= ptr_queue_empty -- or (sts_queue_empty and follower_empty and updt_active); updt_queue_empty <= ptr_queue_empty or follower_empty_mm2s; -- and updt_active); -- Data queue read enable ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable and ptr_queue_empty = '0' -- Data Queue NOT empty and updt_active = '1' else '0'; -- Status queue read enable sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status and sts_queue_empty = '0' -- Status fifo NOT empty and updt_active = '1' else '0'; ----------------------------------------------------------------------- -- TVALID - status queue not empty and writing status ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- TLAST - status queue not empty, writing status, and last asserted ----------------------------------------------------------------------- -- Drive last as long as tvalid is asserted and last from fifo -- is asserted end generate MM2S_CHANNEL; NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate begin updt_active_re1 <= '0'; updt_queue_empty <= '0'; s_axis_updtptr_tready <= '0'; s_axis_updtsts_tready <= '0'; sts_queue_dout <= (others => '0'); sts_queue_full <= '0'; sts_queue_empty <= '0'; ptr_queue_dout <= (others => '0'); ptr_queue_empty <= '0'; ptr_queue_full <= '0'; end generate NO_MM2S_CHANNEL; S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate begin updt2_tvalid <= follower_full_s2mm and updt2_active; updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active; sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active; VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then -- follower_reg_s2mm <= (others => '0'); follower_full_s2mm <= '0'; follower_empty_s2mm <= '1'; else if (sts2_rden = '1') then -- follower_reg_s2mm <= sts2_queue_dout; follower_full_s2mm <= '1'; follower_empty_s2mm <= '0'; end if; end if; end if; end process VALID_REG_S2MM_ACTIVE; VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then follower_reg_s2mm <= (others => '0'); else if (sts2_rden = '1') then follower_reg_s2mm <= sts2_queue_dout; end if; end if; end if; end process VALID_REG_S2MM_ACTIVE1; REG2_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_active_d2 <= '0'; else updt_active_d2 <= updt2_active; end if; end if; end process REG2_ACTIVE; updt_active_re2 <= updt2_active and not updt_active_d2; -- I_UPDT2_DATA_FIFO : entity proc_common_v4_0.srl_fifo_f -- generic map ( -- C_DWIDTH => 32 , -- C_DEPTH => 8 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => ptr2_queue_wren , -- Data_In => ptr2_queue_din , -- FIFO_Read => ptr2_queue_rden , -- Data_Out => ptr2_queue_dout , -- FIFO_Empty => ptr2_queue_empty , -- FIFO_Full => ptr2_queue_full, -- Addr => open -- ); process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then ptr2_queue_dout <= (others => '0'); elsif (ptr2_queue_wren = '1') then ptr2_queue_dout <= ptr2_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or ptr2_queue_rden = '1') then ptr2_queue_empty <= '1'; ptr2_queue_full <= '0'; elsif (ptr2_queue_wren = '1') then ptr2_queue_empty <= '0'; ptr2_queue_full <= '1'; end if; end if; end process; APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate begin I_UPDT2_STS_FIFO : entity proc_common_v4_0.srl_fifo_f generic map ( C_DWIDTH => 34 , C_DEPTH => 12 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => sinit , FIFO_Write => sts2_queue_wren , Data_In => sts2_queue_din , FIFO_Read => sts2_rden, Data_Out => sts2_queue_dout , FIFO_Empty => sts2_queue_empty , FIFO_Full => sts2_queue_full , Addr => open ); end generate APP_UPDATE; NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate begin process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1') then sts2_queue_dout <= (others => '0'); elsif (sts2_queue_wren = '1') then sts2_queue_dout <= sts2_queue_din; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (sinit = '1' or sts2_rden = '1') then sts2_queue_empty <= '1'; sts2_queue_full <= '0'; elsif (sts2_queue_wren = '1') then sts2_queue_empty <= '0'; sts2_queue_full <= '1'; end if; end if; end process; end generate NO_APP_UPDATE; -- Pointer Queue Update - Descriptor Pointer (32bits) -- i.e. 2 current descriptor pointers and any app fields ptr2_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- Data Queue Write Enable - based on tvalid and queue not full ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid and not ptr2_queue_full; -- Data Queue NOT Full -- Drive channel port with ready if room in data queue s_axis2_updtptr_tready <= not ptr2_queue_full; --***************************************** --** Channel Status Port Side of Queues --***************************************** -- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits) -- Note: Type field is stripped off sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- Status Queue Write Enable - based on tvalid and queue not full sts2_queue_wren <= s_axis2_updtsts_tvalid and not sts2_queue_full; -- Drive channel port with ready if room in status queue s_axis2_updtsts_tready <= not sts2_queue_full; --************************************* --** SG Engine Side of Queues --************************************* -- Indicate NOT empty if both status queue and data queue are not empty updt2_queue_empty <= ptr2_queue_empty or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active); -- Data queue read enable ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable and ptr2_queue_empty = '0' -- Data Queue NOT empty and updt2_active = '1' else '0'; -- Status queue read enable sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status and sts2_queue_empty = '0' -- Status fifo NOT empty and updt2_active = '1' else '0'; end generate S2MM_CHANNEL; NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate begin updt_active_re2 <= '0'; updt2_queue_empty <= '0'; s_axis2_updtptr_tready <= '0'; s_axis2_updtsts_tready <= '0'; sts2_queue_dout <= (others => '0'); sts2_queue_full <= '0'; sts2_queue_empty <= '0'; ptr2_queue_dout <= (others => '0'); ptr2_queue_empty <= '0'; ptr2_queue_full <= '0'; end generate NO_S2MM_CHANNEL; end generate GEN_Q_FOR_SYNC; -- FIFO Reset is active high sinit <= not m_axi_sg_aresetn; -- LSB_PROC : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' )then -- write_curdesc_lsb <= '0'; -- -- Capture lower pointer from FIFO or channel port -- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then write_curdesc_lsb <= write_curdesc_lsb_sm; -- end if; -- end if; -- end process LSB_PROC; --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else ptr_queue_dout; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- updt_active_int <= updt_active or updt2_active; REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1' and updt_active_int = '1')then updt_curdesc(63 downto 32) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then --elsif(write_curdesc_msb = '1' and updt_active_int = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; writing_status_re_ch1 <= writing_status_re and updt_active; writing_status_re_ch2 <= writing_status_re and updt2_active; ----------------------------------------------------------------------- -- Caputure IOC begin set ----------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re_ch1 = '1')then -- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active; updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re_ch1 = '1')then --dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active; dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re_ch1 = '1')then -- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active; dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re_ch1 = '1')then -- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active; dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; ----------------------------------------------------------------------- -- Caputure IOC begin set ----------------------------------------------------------------------- REG_IOC2_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then updt2_ioc <= '0'; elsif(writing_status_re_ch2 = '1')then -- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active; updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC2_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then dma2_interr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active; dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT2_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then dma2_slverr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active; dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV2_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then dma2_decerr <= '0'; elsif(writing_status_re_ch2 = '1')then -- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active; dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC2_ERROR; end implementation;

bsd-2-clause

fb0861b80792293beb48c1a83d196805

0.434079

4.280547

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sts_strm.vhd

1

38,384

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sts_strm.vhd.vhd -- Description: This entity is the AXI Status Stream Interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sts_strm is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32; -- Slave AXI Status Stream Data Width C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_ENABLE_SKID : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- s2mm_rxlength_valid : out std_logic ; -- s2mm_rxlength_clr : in std_logic ; -- s2mm_rxlength : out std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- stsstrm_fifo_rden : in std_logic ; -- stsstrm_fifo_empty : out std_logic ; -- stsstrm_fifo_dout : out std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); -- -- -- Stream to Memory Map Status Stream Interface -- s_axis_s2mm_sts_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_sts_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_sts_tvalid : in std_logic ; -- s_axis_s2mm_sts_tready : out std_logic ; -- s_axis_s2mm_sts_tlast : in std_logic -- ); end axi_dma_s2mm_sts_strm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sts_strm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Status Stream FIFO Depth constant STSSTRM_FIFO_DEPTH : integer := 16; -- Status Stream FIFO Data Count Width (Unsused) constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal fifo_full : std_logic := '0'; signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); signal fifo_wren : std_logic := '0'; signal fifo_sinit : std_logic := '0'; signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_cdc_from : std_logic := '0'; signal rxlength_valid_trdy : std_logic := '0'; --signal sts_tvalid_re : std_logic := '0';-- CR565502 --signal sts_tvalid_d1 : std_logic := '0';-- CR565502 signal sts_tvalid : std_logic := '0'; signal sts_tready : std_logic := '0'; signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sts_tlast : std_logic := '0'; signal m_tvalid : std_logic := '0'; signal m_tready : std_logic := '0'; signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_tlast : std_logic := '0'; signal tag_stripped : std_logic := '0'; signal mask_tag_write : std_logic := '0'; --signal mask_tag_hold : std_logic := '0';-- CR565502 signal skid_rst : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Primary Clock is synchronous to Secondary Clock therfore -- instantiate a sync fifo. GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate signal s2mm_stop_d1 : std_logic := '0'; signal s2mm_stop_re : std_logic := '0'; signal sts_rden : std_logic := '0'; signal follower_empty : std_logic := '0'; signal fifo_empty : std_logic := '0'; signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); begin -- Generate Synchronous FIFO -- I_STSSTRM_FIFO : entity proc_common_v4_0.sync_fifo_fg -- generic map ( -- C_FAMILY => C_FAMILY , -- C_MEMORY_TYPE => USE_LOGIC_FIFOS, -- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH , -- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_READ_DEPTH => STSSTRM_FIFO_DEPTH , -- C_PORTS_DIFFER => 0, -- C_HAS_DCOUNT => 1, --req for proper fifo operation -- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH, -- C_HAS_ALMOST_FULL => 0, -- C_HAS_RD_ACK => 0, -- C_HAS_RD_ERR => 0, -- C_HAS_WR_ACK => 0, -- C_HAS_WR_ERR => 0, -- C_RD_ACK_LOW => 0, -- C_RD_ERR_LOW => 0, -- C_WR_ACK_LOW => 0, -- C_WR_ERR_LOW => 0, -- C_PRELOAD_REGS => 1,-- 1 = first word fall through -- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through -- -- C_USE_EMBEDDED_REG => 1 -- 0 ; -- ) -- port map ( -- -- Clk => m_axi_sg_aclk , -- Sinit => fifo_sinit , -- Din => fifo_din , -- Wr_en => fifo_wren , -- Rd_en => stsstrm_fifo_rden , -- Dout => stsstrm_fifo_dout , -- Full => fifo_full , -- Empty => stsstrm_fifo_empty , -- Almost_full => open , -- Data_count => open , -- Rd_ack => open , -- Rd_err => open , -- Wr_ack => open , -- Wr_err => open -- -- ); I_UPDT_STS_FIFO : entity proc_common_v4_0.srl_fifo_f generic map ( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, C_DEPTH => 16 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => fifo_sinit , FIFO_Write => fifo_wren , Data_In => fifo_din , FIFO_Read => sts_rden, --sts_queue_rden , Data_Out => fifo_out, --sts_queue_dout , FIFO_Empty => fifo_empty, --sts_queue_empty , FIFO_Full => fifo_full , Addr => open ); sts_rden <= (not fifo_empty) and follower_empty; stsstrm_fifo_empty <= follower_empty; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then follower_empty <= '1'; elsif (sts_rden = '1') then follower_empty <= '0'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1') then stsstrm_fifo_dout <= (others => '0'); elsif (sts_rden = '1') then stsstrm_fifo_dout <= fifo_out; end if; end if; end process; fifo_sinit <= not m_axi_sg_aresetn; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write; sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif((sts_tvalid_re = '1' and tag_stripped = '0') -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; end if; end if; end process REG_RXLENGTH; s2mm_rxlength_valid <= rxlength_valid_cdc_from; s2mm_rxlength <= rxlength_cdc_from; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- register stop to create re pulse REG_STOP : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then s2mm_stop_d1 <= '0'; else s2mm_stop_d1 <= s2mm_stop; end if; end if; end process REG_STOP; s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1; skid_rst <= not m_axi_sg_aresetn; ENABLE_SKID : if C_ENABLE_SKID = 1 generate begin --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => m_axi_sg_aclk , ARST => skid_rst , skid_stop => s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate ENABLE_SKID; DISABLE_SKID : if C_ENABLE_SKID = 0 generate begin sts_tvalid <= s_axis_s2mm_sts_tvalid; s_axis_s2mm_sts_tready <= sts_tready; sts_tdata <= s_axis_s2mm_sts_tdata; sts_tkeep <= s_axis_s2mm_sts_tkeep; sts_tlast <= s_axis_s2mm_sts_tlast; end generate DISABLE_SKID; end generate GEN_SYNC_FIFO; -- Primary Clock is asynchronous to Secondary Clock therfore -- instantiate an async fifo. GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate ATTRIBUTE async_reg : STRING; signal s2mm_stop_reg : std_logic := '0'; -- CR605883 signal p_s2mm_stop_d1_cdc_tig : std_logic := '0'; signal p_s2mm_stop_d2 : std_logic := '0'; signal p_s2mm_stop_d3 : std_logic := '0'; signal p_s2mm_stop_re : std_logic := '0'; --ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true"; begin -- Generate Asynchronous FIFO I_STSSTRM_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord generic map( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 , -- C_DEPTH => STSSTRM_FIFO_DEPTH , -- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH , C_DEPTH => 15 , C_CNT_WIDTH => 4 , C_USE_BLKMEM => USE_LOGIC_FIFOS , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => fifo_sinit , AFIFO_Wr_clk => axi_prmry_aclk , AFIFO_Wr_en => fifo_wren , AFIFO_Din => fifo_din , AFIFO_Rd_clk => m_axi_sg_aclk , AFIFO_Rd_en => stsstrm_fifo_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => stsstrm_fifo_dout , AFIFO_Full => fifo_full , AFIFO_Empty => stsstrm_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); fifo_sinit <= not p_reset_n; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid -- valid data and not fifo_full -- fifo has room and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length and not mask_tag_write; -- not masking off tag word sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- -- elsif(sts_tvalid_re = '1' -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate signal rxlength_clr_d1_cdc_tig : std_logic := '0'; signal rxlength_clr_d2 : std_logic := '0'; signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_d1_cdc_to : std_logic := '0'; signal rxlength_valid_d2_cdc_from : std_logic := '0'; signal rxlength_valid_d3 : std_logic := '0'; signal rxlength_valid_d4 : std_logic := '0'; signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0'; ATTRIBUTE async_reg : STRING; --ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true"; begin -- Double register from secondary clock domain to primary S2P_CLK_CROSS : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_rxlength_clr, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_clr_d2, scndry_vect_out => open ); -- S2P_CLK_CROSS : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0')then -- rxlength_clr_d1_cdc_tig <= '0'; -- rxlength_clr_d2 <= '0'; -- else -- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr; -- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig; -- end if; -- end if; -- end process S2P_CLK_CROSS; -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes TRDY_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0' or rxlength_clr_d2 = '1')then rxlength_valid_trdy <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_valid_trdy <= '1'; end if; end if; end process TRDY_RXLENGTH; REG_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; elsif (rxlength_valid_d2_back = '1') then rxlength_valid_cdc_from <= '0'; end if; end if; end process REG_RXLENGTH; SYNC_RXLENGTH : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_d2_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_back, scndry_vect_out => open ); -- SYNC_RXLENGTH : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then -- -- rxlength_valid_d1_back_cdc_to <= '0'; -- rxlength_valid_d2_back <= '0'; -- else -- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from; -- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to; -- -- end if; -- end if; -- end process SYNC_RXLENGTH; -- Double register from primary clock domain to secondary P2S_CLK_CROSS : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_cdc_from, scndry_vect_out => open ); P2S_CLK_CROSS2 : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => rxlength_cdc_from, scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => rxlength_d2 ); P2S_CLK_CROSS1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then -- rxlength_d1_cdc_to <= (others => '0'); -- rxlength_d2 <= (others => '0'); -- rxlength_valid_d1_cdc_to <= '0'; -- rxlength_valid_d2_cdc_from <= '0'; rxlength_valid_d3 <= '0'; else -- rxlength_d1_cdc_to <= rxlength_cdc_from; -- rxlength_d2 <= rxlength_d1_cdc_to; -- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from; -- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to; rxlength_valid_d3 <= rxlength_valid_d2_cdc_from; end if; end if; end process P2S_CLK_CROSS1; process (m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_valid_d4 <= '0'; elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then rxlength_valid_d4 <= '1'; end if; end if; end process; s2mm_rxlength <= rxlength_d2; -- s2mm_rxlength_valid <= rxlength_valid_d2; s2mm_rxlength_valid <= rxlength_valid_d4; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- CR605883 -- Register stop to provide pure FF output for synchronizer REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_stop_reg <= '0'; else s2mm_stop_reg <= s2mm_stop; end if; end if; end process REG_STOP; -- double register s2mm error into primary clock domain REG_ERR2PRMRY : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_stop_reg, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => p_s2mm_stop_d2, scndry_vect_out => open ); REG_ERR2PRMRY1 : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then -- p_s2mm_stop_d1_cdc_tig <= '0'; -- p_s2mm_stop_d2 <= '0'; p_s2mm_stop_d3 <= '0'; else --p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883 -- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg; -- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig; p_s2mm_stop_d3 <= p_s2mm_stop_d2; end if; end if; end process REG_ERR2PRMRY1; p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3; skid_rst <= not p_reset_n; --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => axi_prmry_aclk , ARST => skid_rst , skid_stop => p_s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate GEN_ASYNC_FIFO; end implementation;

bsd-2-clause

30086459e8a880da5bd4391d6b4a4bb6

0.447035

4.017164

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_v8_0.vhd

2

19,382

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block aCVHNLRL8soMwgirb4igYdy+w/d8MsAkGS3ESRMsTr07DnKVy3RTnJ9RtYLA3I+MFSh681EbheGN wOr9xTxo0A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YjKX7hHDAbMBc5ZteypfutOS5A5c7hVUrYY6mAWpruKdPwT/ntU77uwBhl7ztC9b3c1NBILLEc0J gsIfTEXoisdQQgLcohRsNQCnpSTvaSYmrN0bK5pNGe8DfSB5DqW2RcqlVXa9LlZYu7uc9FiTA41V s5HCQJEnh3DQy8T69Uc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tIQpokMnxX0wpy7fRnd/O1KwmW5fUadWhs/fWcCyduFMy+bJWWMADfVSuYd7YlnybyCzRyFNBiS3 SelCP1dTXOz7RUqRvBmLTUj7lt7j8p8ZwjUfLA35leKw8lFAup4iKpOR8P2MqmcPaSsHKRddXKRs nmQZB6b/RPUVYEmctonzrMwzgpugn+0WszmI/iqshfLwuegkWo2rdcfYcHEiX8Bm34zlRSjMTg55 NHZBq3cJxKEM/1Vb4I7O98CB+W+5E+RZmURDyZOkC20AR5a7jN5MMwgSxsOIH25aXazBbJS/RaIg alPkkcH/HmQviV25uIFcSRFm0r2b84uS5liNZA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Ij2w24zZEehSJgByNgalrX9zQ/FmZgkUvva63ww5wYDd7xg7Z2tNw/jR3Uq3T8DDG8+EuGauv6OZ wzZjF8PP/sXDW8XwQiz+PpGp0gJjzHoHcFwcQDqkm4k1WgMCxjjeOeYQzZZMMqhcjCsa95NNz9+r qYBVJFxDHVw7IcB/s5E= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XQe9uXZHQ8tuqq/muDjCfWPpeZbVoAuLjnw9oD51W9b8XgYuPumUg6XDfkoWoUvgDhUj0nX+JohN AEVeYKieJr6Ybdjt4lEQgvwBv9jovxOo72D67DEgxx4Xu1nEUvg+yBbWrm32WCnWTrRU231EIX8q Gu9olP8WEYAX3Fi4p6XewkVc0Moa0lqEpXmHuOPRygzvnVAIiM31MMSaMIt4JiCDs7f/qbqzrftZ s+erAHXMB1oGtybnkTUmhVPG4PeqBE3jcx6mWqKlR9Dl42XhbpfqIfIR6HGPuFcuJ1p03eA0p0ZV qhN1M4rdey0jf2i6KA1schp0TrfeUfKEGbhDAg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608) `protect data_block BsHbM8W7kNfkoYsutF02xo3+pujCXiH0Ip/JIvnJqewlPhPQ+exF8cWK/SsSuN6zmRBH9MyyR4pX ghsiKvu43f6uXljfjBJ3Z+c51Nk8WJmzg8BgKNC9AleJcIQZwAyryM7KVM8P4IiU1LwjMxXnuduN yK46XJ/88Uk7hFTr8spku0H0FpxhO+QcyHjYECJJhGrPvZCCLr8bOZC8KkWWs02QUXWsZr76x32Y vVzdRlQpb/CjfyMtaXMs5WngCcKHDlXYBwPYUggLXhEAYhTa0RAHnXv35HsxW8YcZk5YXpozbKGr cKcsrbMR6Md8NZR90KsvuANqDa2eY7SRVifIjzNdEu15+1AGIDn9AyzcY86B4dzCAjjWRpc3cvLB EEk7jc5vJ1MwD2aqz49g0lf7W0y6qepan2ucUqWCLpUoWOQOJITt2Hqp7UHheO68JjvbXa/IfeZD RYgSclUAocjzkN0cWPTiZtg5SbyYSefoSZttuNyPHwBJBvorlbArezdGimsasUa44YN443V4fmEw 4vvEWE8drnXgxgnsQSu/Kuy0ExjsL+Dfu+P82D4nW9kCTIMalU84UpLXgtxe5SayklU9xHam8xeG +WAW4/knwPYqVaG+YPBfD7oB+ZdXsO9edBORs7PiF5SlF/r7z8I8ksrnmJ7ghQSf/pgQag2MnxVR Pgv1qkC/EypiRURCs3ym/H/m6vrBm5NA6fhsfvay8AUL/oQHSVItnlp7xcDiErnj8+8J3H10CBOE TTS2SMDXZmSVfjU0+VUqmmXK25K0zRkkmXOsVv3zB7buxkw4WEPQIb3XW5399tE9r0NUoGJaeugO 7pGfzVnQ1L/gM/pwLvNFg5iOGVPbfmyEMCBIym9kpVHd7a7K7urNCa2H2gK0MW0UGiJMGeL2J1mu eyqLumPz8M3GzvjSiUvuaZpc6ak54Icz1NWcL3cW0sj6x71ib31/5eHIMg+oweHkTvPe00DILK70 4+BJju+wM5QJOzo+1HJZj2IoEe2SCkQKBrbA8P7Pg8T66oBW1x0sfSDOx4kd970VcDwQiwCrolra +7cqXODlfCIH7ebcVsV9d3UsG1iHmtmTJsAIRt3HI6Cn1qv2dgtv7MC6rSW3tz5IYqcDLPKRD7I5 zuNooC+jB2iUCRn3jWr/PoQmE3bY+bqBmIILfHaxvrG9AUvxqSk5EakAJqQ+oPGuUuodHeZDkfqH 89tfWMh8gGUwFsgXH0IDrhldCcW6t054OJ04c+oJGhgWwopkhzGXDRc3NJ9G69FrFx1Hq2+foE7j yijR5FwLlKg7UOWFpz7q38pQBHmYjhjmrG/M8d60jtuO8dK5x0z5NSNLekL+HmRIkXCeDCgP89w/ emXgvlYWiPsI3AlM8d/x8avyrhB/TLod90D744ouTNiTwfA3FTb8O98yJnysMIhr8vlqO4PiOpkx PUdnTvSSgHLmHjwTzrMr9gJExT8M8zhAw3N58Q+3Fp+n1S/L001wcwjSEErp3XxWjJS5Q7nxYShP 9+PZRBOBAFYXtATvvM9WDl90VGLcqRgU0pU72y1tEOubpSea4ulq9qQbvTEoW1VoxaSads4xdTGg cnTiwDHQ4SjlK6zCC0g1uAIe7xJdx44LdCxoEXmGu2lnXq1DzBz29WgJoC67wXK5V/lsypZrxJb8 5bW9BJTjlh87Gc8KW46qtId9jXuE5kWDParniX76p33qFKRLqm4caAyKxRblFihGtOZVZY4hccp6 Pg74UviBTeDL+UheOEHFZeyrm85nWop/0GW4XAHGch/BNjcf1xU5k6ciQS/X7fibBKX46BgbTlK6 wvFSSlgyfaJPWEvjRKhUyDizGDrGxOHTJFmZw0axJ4JCmv1vnMHZK5HP07zbMoEn5JM7qmY/r4Ub RvZxLj8RiST0oV0/9kCj5O+uAKFAhrkNo5hYpVxNooG4bgqHD4fK/Di1VTvE+SFa2kJAZvvA1K81 rUslxEcUyb+G8YAcnFE3PHZX1UlsCtDUVms9IBaFApm7OlycMb3ruNDy+wkbKkEtPuxuVR7gvn5I bUHDnFh7jQEd6G0hQrVgfnBtSRROx1kPW94xudln65x5onkHeyAGtJdBfc+jRvsZZ9FcdaJLKsUK ylBX+Pu5D9YTNLc4WMwjP2JkJ2U8/MWsG4nmU2rUrRHmDFLJQeZVxcCb70v77xJH2yuX65g2z3m+ KsOfecoX5Bz3RhsV8mCpHmPzRG7oHpvAQb6G3pqOZRhXYJ9LkcRiJtV1dxlCzXAsduYr2RKpQWa6 Hpp7O7qpnTsnGkjTCMWmEeobkFQLB1yI4vB9n5QXQZpoFGHWO/+PZo1beXVESshlktt6Lu2HQTfs uP1nxmwdleev5iG2VqHjJe+xc+e57/Wb/7SBoj0fNErwDOf0R1G8/z+8yDm4r7jz2dzyxfHefzos awYTpYUshypnQdeMOONODUHVhjG4blUcQHAoi6Qc8ORZf0X+TOWRLHClQOMnZUJUrY+9sBBehyTl Ajlz+IEzWJLtTbp+VwRKfS4avzrboBhoImn58v1cxe8mfG3UM3BVyEujn1P6vc+uGRzoUxleaTxT VVg9OCrGQFpukmw8HDc/y0kscuT61NYNYFJzxFmkE7DTwLkt9QZfLaVksJBjh8nt0VjAvXfJ9x24 2TEEnyhFtRhF1HR6RxrdZP7kUVbXGoH0RQhQhFRVpfLiPWKIAIolYu2h4R7DzCwXXSM5uEpvbWME kJ4Dm9KXP0g/Pq3Fo4IWJxMYI7rbLttVOVR0oaRN+9muUELa3LhVe/qm4OHB2t/TeaaYZB0uPPNL TdsSAXm88SzXnDQei7JgSikG97BjBXhJWCzuu1DH7aiOcLBXgprVTFn+WkoYP64wgAkgrLpo/VC1 iTmEzS9dg4gkmb2h++xNhIfDz8J5Yypz6b/VixYaUO3aUSKLlT+Lfz/TLI2mgPtbyuW83pDQwx5+ 3C7C3znRzlRntA/qjb4JVyl01KwtnmE8S9A7t6VryU0OFp36vXI1ed2MzYfLh09BMyTj5KKsA2Pz Ub09lzAnLb710lUzVmHLuwShxgvhDRZqIVd3x1veajUYvf+kBYoOwISaVmb/bqV9knqOi+hW+PnE MO0pWgDcJ6HWA6RQjD61b3ZgIA4YCl42frS9eUeeyEU9Z96OqE5tgK7BbXRpsVu78RklNZdZP96l GNCoY5FJcRYTfVzESBoRTwccDOAYJ07Jo6rQqayHivV84/S0u2DmG7xo/dzPRMqVGKwpSgT1kvJA sO2IeILrPwl2I1bk/td4CX81k5NiyrETXnbDQsH6hiZ4bsfCQs37Snl3pI9mcZzUq990CU8w/NZn O0Ls3bbrtZfKHB5LQSgXF1L4kci89/WKz8EqBeWkEJ/arohzGqyKOn58fpGSEtUz1QxIJSkn0n/R 4sVgcbu5tuCulOOjEEg2Yn+mwVIaQHouTbs+ivwSNVkIjOaHnyKvloUJ/Ob4UQTqIf6s7Mw0Xvt2 TJHsWzpDT7tmefonp4XPghL/sNgGhLpMb22fKeYpktmVEOYb1zVrUXxXXY43s/253XqASCR75esM WLIO2Y71tRfsIUkBZbj4hlRvhUWUdfZKt3FugPVq0dQWypgcjryx/hEBA7MWaw4omo3q7UHzVyDP /pHkCKuQIzz0Vp/zfgCLKL1NmwY/cN83Jse+Uo9A2KFmO4iHUgLns16YFs3jx1mWksFGmg35xEYI 0SfsCboYzeqOqE6O3kTwFXoy8FkOrWaksbeF9KaKoz9dWc+mjzNRnkwRb3+cvukEOMEGkhSlqp18 CZVGDOxmB8Q8Dm+k9Ahq06KHgCVIIKH354bNdNJBAt1MdkOY0Hd+iEDARDpKNCcV/Y9LrQbzOF5z 8B9Wm/67opOT3TtyH7G/gkDjvGcwDqycm2xHqYZBVDjjTMPCatSwQoWs/QzIVoOzculL8nrxuE5O Ke5Cnw58w69aTGsxFGWnn60eMcCCB5e93dcpnwsuJmiYiC+SUORG+Vsfnmpm78yqm1QNJhz4Hw6O HcWmx4Vh292Z6iNeq3bBdnXxJYc84WuKLot8wVWmDn3m6xHrOwcfkB7fZI6ts5NaChMxpvMIRcfv Xk8fMQuqTrsRvqFxACbdLnY6T56lgJPviXtv6fZK4mUKmf++atYyY08QUHNRv5Z8XrKhqb2hrTh4 qAGsOKZocT5qYPff49cHE6Bnh0luLkl8YVC1XHwWTL3wEVGeTvJFR8OvoP6gM92671ba+oXFlEa5 tSq44Dyw+S2RCW5EDKsirpz+NtD2GcRHHakjpbYv3eSJTTEmd94SzZVMXe2rCCZhEnIchD8bwrfN QXuNmT3Ed/SkxKEzbzUgcRdfo1vxYq0475k9soH7WMb9FX5Ya9jTCOVEXjEKU25XEx6xRIPtTCn6 3sVhIq3oPkwAMat/Dbt/TGtKFMmh8rmX94gohlgJE5Au43+UhfL5Z3dHby+QTj75tvndi4Wh0iyy Wyvxisrde608k6am9MXd7YRFOeHGJhnmGv9VUXFYA1W48m4cOlnIiqlyaAF9PvROCVPYMEVeXGEM BYcFblU2Utcdq5wrU39xCr7l12oLczpL5XqVEiwU+vt8LCnUZGBmHEVSM3tRNyOWOfaDQF+MkuP8 tPkekvqom8TbV/Vd+JFsG26DHWhQ9udhD9KYo4rbFuXnz/naS6MkMu3n8kue3Nu0WRRIDQkYGfpJ D4Fq5YX+A0X8Dr2vWIDASa36jPA4GNR7AQsgJnLoRYBZqmhn6Dwcfd+k3uY8ZWS0WMBLy0Kj/ob7 fPxpjwnvWL8eIwz2PfmPtDRf4u/oBy62DGZzF00cEgdbb+fb98I0IQw5eUP7AaBk+wMXd+DhyBLi yWJOoz/slRUUSy7HOGJ9q61vW3AWntnoP1CCMuW8RNx84dokG1AuhK3c2nyqB5TlUZ5Xrl52G6Pv 7FwuZP1VYs+uMAnfv2HJHoARGf/LoR2H/AVPXCw3ZtRFhQCW55F4o4iVioipi5lkYzZSIfJE6JxD 9GnRIwSmGdqIMogOZlMJdFk4jqXNVyb09x4VkJBXORZgr9R6kimPLqWKeWARTOD8F41c5VxvyrI5 tyaJsEIVfjdzcFGpunedHdADeM1dYq+r4DnZJlq50yIzat696LvLc18sQX23CV980Fq7I/WGO4nh dyJDrlxXqfwQTzvMgX8ZiX89iV8t5DiX+IHkBuxDvFvd8YHMX6yt/GThrykFpqYkzTQ/AsQ2zFQp vltaBmAZq7tkfOvpy38NpZz6BNkEhJFxWIisDNg1WxXXTHLEENivFTsanPz1ki4Bkub0vT52U+37 XBn1vHAYz7AzFoeFMfc1B8jHdbxrukjBDKD7ko7xHxPtchMnXuIMZGA7V3yEFTEPLLz2pUwOOHY5 ZyMDgWjLuJA5rB0jqHimiskIW8rSYt6B2zjEEQTXej8uzn7kNzM2U0CSj57onMgcKKLtz6ZBxmNs /MknSFAZpjbmfK0nBint5W4toVfcRr4dGFx+L0U0yQLijk4mFHF0T2hnnqDDTcxqdQ9kUcSnoeEH DzOdWzxwQPByyPNe4Mc6Rb13MwMHqAq8nWvK+OZxWgNmnC6HOqkX0lMWXtqMsAUuzEIZxuo28is2 8ZHiAnyOEGxqKLTr0LG0Gf7RO5upJwKUM2sPPfu2a2LI4lWcbQHq6UtAXgMSMVZBnJFlw4C+ef6X 6fpIVvUZaNM9uRFPm5JXhXX42nKMGr7VF6U6joGsGQhjZ5DDZ5fSUJ/hgUUADvKXWN8Eb7q4zroq +rAiUnj1VDDVXs+7J+P1WMKpoCS+ROAGwceJi/6jWSx0fakQZkqWtfOi/rEtb2MkOPrOx6Eu4xWU r0qk3FMnxkkIOn7lG4m4WU6GEoJ8hdAKceUQ/SmfRMsyXfUlqj1dnq33SKYFUDKrl/XLw9KgIQQa xsj4IVNivVXfKQpuDqN/FKm/k4WutaNrPsMIFd5SsTFC5Qb8h/YfU8ognjpi5Xwl8a1TZ3Yzg4li 7HoHAu+z9LMm5BtVJgItpfkgtbyZcmog8pVstGJCyGfU9eNM35IWb4pY0K2Dj8craq8RZU8GG20F Rbpse0ZznHbra5Byewgd1G4LbHwxNAXVgUrrrvGmKZ+2VHiGqglqNakmjBM3nI9zbutniBC07fjC UlwcEI/Bb8LA1DR8owz4R5pF010rmjsbQrDzNXWVOGhTghM5MIcd1bIbQckNmTY1tkMzhR3NaoqL P5ilfBNk4L08uvezqIE2tq8Omg2R8c4ROZ+nq+4I8ep30ZMngt6ZcCHxXcw18AhL3gIhLsJUkCR+ zM0wL/uXAInli/FLTOO6v2/JlQRYLvI3SpR4YdpEUOb7lMegZX0THASbGj5v2QKJ2PBl1fMkSEbc M3MvRfB7C29mfjT1AWfvfT7sg6FV95VYEhpa1lgT0jdKdZcobBFSH92pecDHszrhh3VWZbQy4CGs b2CxBnlJt9rPGoh+wr3vRzPYHb1WCrwsWZr0+ClZdZXVSBSCM8lBgig25DSP6f2Fe4IXd06U/pKA +lQcrf9o0Dm3WUKTQJ+6y6sY+0Frem1GIAa/Jdm3su0H3YGIMXMUeF4OsYIGXpu390q78vJ+xg6o ADBSc14Z1rwF7Bsy1EFPMyEBBIt7jxsjanQf9M3RBDJsy94/gTmjWyWYHBbpvX8h/a52EI50woan 9lxMjO9qY/Tfu4uRTbWf0Ed/GeweEs+YByU+fZBJRDJOa4rY+OYpHWZl2g4vksqrvI+3lazu4b27 LLYNgXILPAHltWluorRl2e74sExwiUuIVgUqZueOkw+ojyBtyxhPt2/7LKspuM38tOvk4FQiGyW2 jBfVJTQoD2jvc4Gmfn7MSjnT00ndxlullT8sdEuUQ1oIbKcauEN15lS4DFRu+RF+9VUn3l3r+vHD buFSzjd63pQ89hhlUQmZ+Ch/woRFJvGM/k9twlKyidWVFmmx4OB4I7+fV2kG7vptUncbMz7mxDkD WhutcU68kGL1csB8avWQjRKH4CT5eOffy1YDbF8Qpn8S1MV0fRDOXdR6rk+75Hscyl842gZkZR/u g5j0oU4hFmaukk8Jq7BspBTZGIEOB2UupSiNEwzdyuPCShwzud8tJGsNJty7elmLgiQnsJuMXdy8 ybZFPB2nwRWFLWXzJCUl2QdNP7NH0YCSYnFYhHw62jqJeq08DJ4FUS3cu7hxLTIvNpAxtG6yyLV6 b7TeCyguugz3jxw4aVsXc+fDoEbWqoxM1NX51NcUPIhegd13Ig2h/3obl4IndyCN5IRpKyWp4pEz VCJxlByIZal5D99sdLprItQEQlL0AEpoe320lpYKI/t4bjPPIemh9FQQWHJdj4eLHpejPKfSqgBx j1amX6Q8jDoTCpJXxpEm8xlXaesrhFPNPD9ZE2lo6P8ggmXZFtyz4uvvA6deUOYhhrURoPkuAJR3 JREGCyALfJVHyH+3ZE+N330udQgZOt5G4xhmlgkmBBvYjDPRC1YMH29KJlc2kSK7ale4kSMas4kW AeZHprUuwJFLzXurbZG5XkzVUH7oEj5/F1eg3HVa0l0aJNGCjL8SF6CnBRt0t6Ot7mn4L/ehrxgD xn93kVtso+M1uBi55l0acafLkF+UDP4GnYAVqc4X8BAB9u+qd9DrevNjHTK7M/IXp4iPSySLzuz1 riQjbFqI9prvI0FVMmi+W3VjEPIzHlb5LGyZ2GyrndVFT7yxUxMac7nCUsFP5M5VFgDVw8jWMBBl 59FbKh46D6t7ZG7IZaiWTYOivE8kHgJNc7kp1OHrhA5DNpDJUS1LvjKLzV/Tm8DpCPzH+4N00yXm qbhf3hNDfibZ1Ob//e6TOLLkEtKqe9dpYgj9OEZapXzEcl/twyXk8Mv8B+JuqpsLjSKQLfpuECaY aGi5emB/6uMfVpZTPoU7jG8GvyhuEwwk7NhJDOvOwqV0ARb+tX4ps1NfP4asJ0RzOJ/B/18nEea1 Elprwp5oZg1O/5dvi8VP7H2aF7k9i5g7XfYomnZTXiVoc0UyaecnMGwf6VVs+FrVzYYa3uLosmdL 8MNZaw1V4WAfuRShq20Q+j+kFu7unYChElz5EXif1BBKf1IUFEmDN/4ZNvxYDtjoWBxUB40loFQZ LpRgPCfsg6770FQkQiZdjuptWLMw/oFOXSLfQyeujhZI9wO0Zin+y4EZ3A6VGLZmlXwEDGQ+4z5I f+j/tvWKBSIOETQLkSv4OogLp5kFQoK3NUdx5zhjfk05AKr2GuoDh9pcIzNl145Q+G5111g4n6Ye qnRgKDJ/ke55999uVa+/GlcmeWy6oZ/VP6SxkeGq6DPY2YRcn1RE1LoALGhyv19T0sIGHYFcO02t yJ7vonThKeJ9PZKP7f4xKXY9BKyH2NyzV0ls7RkIDGh1RAUQZwHNDWKOliWyFBHXX0LmIJTGjU8r m3NkSicGYMQmrrqHn1vQWn2hQjgF+4n3lQldjcbr4hS+d9+bkZHCxdpj1X60D7ZkMjCJP6yMB1mH Jn32//b2UmSXzZ/tv1bLlahPa4tQN+UqR5l/C2UkR6qH4RDvGnz/w7EGYwjWWa8aoh9Kz77+c1iL n3JDB8NVBcOzgm9axkFbqLET2URLUbThDgabcu5vhmVjTYC7c4QWIga9Xw8kKDSS0sL+dAdt9TVK g84tXyZamMsb5JqSDNPsrut4Z7rtAXt0+qKADB7rA1Tc0WQtq4npGqzClqkH8mzL69taBVBBwE9r P96IHRdsGOo5EUQ11wmUEL8wnAWgJRZu77duUgyWFdp19HksWh3g4lPe+YxRbsiaoyFO1zDwLRXc IjB1D4XusH4Zr2tDyjbsReG19VLwsHXJRJ2ba+VIdzltAH9FV7YY+5kPBHYQcslS7bEgi4p2c0s0 6ZPHOGIE/niDWcYRREIxCf/f3hjNpDOXMirWNG72CyQbVbTarO7g7hNIuyrpHJ0vqLAepUHWE9w+ rew0/ZUXCO8WgdqSasVnuobQWUGyncKqWja0AW9fMZNoav8HpbOtyzPZSjLFjLap5pe6zR+bNbPr p8MGm2SBZ6BQB5Sb6H6vYqEj+PQwdiwd3JDrAcPeVIISkc7doQsSjMzbfNFbqeRBnu4+RCDxiXid tC20SXUuHZeXiBYyU6KX6hyGfr/dtOeywZBFow9Gk9/T7vzM9AsuAnLfqyjCT7nuuXGALFB94ZT6 BbxuY6mFq00bbSMEJhSY6VeJMgTXPaOyDZjVUFVAkDWZMMCTOtpWc8BzrTArtuLL3KHVGM09guTi xlP5uTJtQRDygfd5+EwnxRHtXEks0elr1S9/LaJvatHT1uKtNBtjnq+UJEhK6m2V15IyFGc1Vh9W UW+MbMc9hS8QnLWFZn62/g/wGUHdtUmKm+oaukEAF6hqMUAYNhjEvdrS8yjuDFwgf8pEDFcoYYdV x9K7OBIVo5WDiT+sCsmy/s/ghH6GGyMn5DbYX2zzwIx54lvPfOTfQMmaDo1qQoW1h+ckMn2WpRUm ZTSXt3HBafQOOtBcHS6lclApZcnDECSBKvIoqa1gUWcpVqnRvmYyTAhDZxPlSi4X2T5g4srkLCt0 hAx7lFrA6K2MYNhnTHgpEtojGdYV0t5ew/0LVu1wvakSzw+ANR7+Dn535iGihZdUzH57R2BCnRLK 3gqvGo/ko/MIY6n5c8RbYmhY/vSBUVo2n7nWmpExX4gKIJ4sNt30Xtx0T3pfYMKZ3Sq7+wkB2EZ8 AjfGxvVvIS6twfJeSa3yxKMdO0/LcOgVBtx8uI/ArIF4zEC3/ztjriAIna1PR8kqRa7VxgzuOpKI OVHD6DbfFx8lbCkAuOZgUY7LAFy5FWK501WSudaHCBpxhTLUIJ7SghgAOnhr401EfiRVKuOxJFq6 L7jE3uznhIGwzRDMgcsELdCGFaep+KSVEGLf67UcR2Cf7qvA4XclrlzEWXaDxJqbWHjYpHVnSZt+ j3UjcxWdJj8x9KYHtNdTSBQJHmr4EyMQu/k7slfugHVKrccMs55iW/P7Xd85dV9O6t7WRSGm3jfu Zl8XINbQFj2D6zC9HdRPZ2K2A/KR0rPciMarQp4IamroUpcwNShwlaSz7mvpsTjcPDO5qsudDUKv XyqvJg6KWPNmnpNFqLyl6Zc5oLI0xbmQnkC1N23UsJhseg+gnsR+pIUjFWK22MEqCcb552vmPdMF BUpCs7xbgpAB3iUZo8mOU1MlxwZEprS+VzBZmM2vAG+DuZwAksUMVkTF2q//WiLEXIW/A8dYspE/ mvxTMdAuwCn45ldbovfAoRSFZNzz75t8VjHmLKDgyRtLaGQn0bRh9Xs6I11Kwal0d45Mwria9lEG ZRYAvoBm0jbkISirh7STt3sclu4MyZbW19F+a0M1ihluBWeUowm1CD2X5vUf9zQiZYb7PmVW4xPw U28OhJTtymU5R43sqf080mW6RxmIfITHRp70G9q3fLs4ktmwCdDXzmokA03dE3F+bAx1G/La4TqE 5uTETRR0nPysjwW6HV0o/XQprfWmUe+6zNt5bvHt1FGc6ZpciXovjwOyrOm2cre3koxlb/oHlc2X gEV+wTBzvAvK0zJwBbusREiUlZ0GSEaZi/ARA8tK6lDqCHroop9D+oEihQNsX3xD303Jy2vDXZrW YfU3t1rzHNKrJm2mCXSAF7qhnvKwz1SBX2FIeJQz2LL/znspf0Rh4Fg8nUtFIBYSU8yK4S43I9/M hcHUewsPjl3dUOwjWwskEPut7tEahww2Q3URfC3fZQ9HWe4bVVdYBdzUOeJQDJII/CbAuLckTRmd ws40Xmj3EYzMYaaLma+I0O/FyW/fcl22TNZI0PXul7qpY/So9DdwAGBNJhE1pzRUr3tck+UlGChe 85WKZM5ekcLkbeJ+9yOHx+Iqtrfrz8Ql166B2MapIyzAXEvbEShnllPVH08i9UXGGmUefT6cs6qP V+rdewM7t5izmyH13WYX2+rrLBUMHZsbQFmVnaetZw2IIDmHUQ5Oo22SoAAwHgsdP//lt1qwtMEB x77mi3jhZGSxmkw5fOx7qzh8q9200FyVVJumopobLtgyflQexBtDrUXm6d9RBy2kZTIqOwH0d5FE jFc9oVlMrYZaYoEYvlx5ZYxJPBrEfPHXf8P2JfF6uZFgNq86pT3rLO6dVzF6O/Tj6yzggGuxDm8G L8KGOzILRyCNcDoTuOKFjB72o6axmpgXEI5d0uZgZCr7iKwQaqs0iV5bHoPrz9nVW4OXYfys7m1i 1LP7D/DOgpvePh5PAlQoHMZFT2yiXu1+y7mVBRKNMACtXi1pz7a5Ub4NoVyCsURKzSyMrwaUQtyz 2kDXfR23JnMoBjxdCOFiLoSZ1VC9oDHiZOXwbYdLSnLkIbGPNyBt/9Df+2vpmim56p7nS6zRbKQo cBSNNnEmY310JQo8yNsIknUwTKgXwkl23Dwa3KEoRfwCC+T75Pp0/rMELsXBYmtdHwycI55s5o2i ojh/b9DRKN/RBN62PuIYMr2O1kCbhlz5tVjbH47vOiqhdXecLi/abJWgUt9wSxm6HOsWCu7ZncbY 4Gy9KdDPkm1kiNRWrERlCCyWFyBmCmJ9fKX2qn+pDza4Dwsbe3ZOxuAJApNuRngVJaZgiR8Tw8rt w1fkjhHB+UF28r9R8nSJjFr6HWpozEI8/0r+3O4pU5icpNfDv2DMDBsLDGB2VKrAxpnUOyAwFjFO YSKMi9NUtZ7k9Hz781vVfWxJQeomtbSZY706wQmuGJOpA4tv6hNKnEQGgWR2WCXfDvwaDmjpnngm 37vcPS40rwHVzqfSCRacLEeV+jRedQmR+G9ecz0JFRc2quUa0GmVdTlldbFwrp8FABPU3rKe8JNt QwnqU5a6dPkh3wV+aGtg43odBCTLSBfeWY0B+buStnaVTjw/CM/ZQoWKO4mCXUxu7zqf8sKfFhJh c1FjBRS7pE9orApP8zizMOjrZpfNX635dEeYQ+DnxBOBPaHqbEJw/XuPBVTxBLgK8AKIHdT9mVA+ uRXfGg0ju97Ay+0LY+z611ZAzOjTZ8Fp/ajl1V8OAOim2pJnl9+2gbg/sTAZfbuH64uJZXqRhfZS I8WBGR/gPci2eTMvZlwKfK60SxX247sqtnYq/N9ixmcwmyj34ppQ7uTirzH/o9JRzbNvtRSxVuIS QpCbQuGF4Q2wxh3OnFtlfIfEHRyF/89K9Wyo0L8KwiA6aPd13SCe1PQU0Oa5CUB2e27MZzkWY+pT qCh2zqNpYEJulHxEnYG2NGJdRvHl4Yj482H4mCKXVYdole4PFgqYDhDghywJ0HoT49wubbGPEpcM LCskdNrCf8uDEEWUa7vLTzUYMrPu3FJIyJe7wwtwRVEqBXH/8ESpKQuJmC19TMvHHWGE5VsN6wmA DHGP3w5O7XWvbAx/7O66qB6xGB2p6h+b0C33LCPpjJJvGP2z4t+zYhPsCSpKWYN23YzaYnYmR6Tm FnNko3oeikK6gPRodIAGS4nZ0N8C50Cd3HtHasRy0z+73sB7JE2MZB4GXnh6D4uvKBr1KoUzudwt yD0H97gUCMMXbGnzZELjc0hv6kOffkbTAaFwzTS91334FvICYoKj3r6qx79JfoWRqxsVVD62xZ11 jShiuG4UxLGj7TocqL8TXGSsy4GSq0k348N+FAeS6iYWVl+fdPAQikkAlQNDN44I1eEgnsIpCFpI xLih+4Uoqa3ZKY3FTX7UY1Z6b3vDm0eEoUOQZIrAfSRXls1dr+PTy5XxKWSii7arO8TTO+hIa9NQ jTMwhY2wzUmFgUSE6oAW8s69r5JQfFE5imVTn23f/pMfMlTgIKKOhlVHKa1pMRxXGjejoR7JWssS v/UzW2bSpocae26pUrZ1YomzOM4nYQePSfXDUqCuexoXZtnTh9S54uJouSOMc3mpMElZv2bAofxm XlO04ytxQsEKQp+F4efq9E7YuYA3w77f3e9kaYJrXhg23obqZmlbnQyNVt8R2TIsD3pxjhHJkuNM qAexF1XZQWXxaM43dAHfv6vIk2U3jy0f55Ns0JYk8/gBotK/dcikffQq8SDqaR15FDgfvJE6OkEd MW46AVpFJ9KJ9mxFSR7XR0y7QUfrKYSlvTgyJohvEDfEfwSEEZBuiF/De83fBg7xskQqWOiz4bFs pbRiW6xSby6rTujjRP1cD+tLnU99weBl5vulvlexahsTEAC7IbunwTho+GpROwN2rr4ulucK5CNL U+K3cnWd/EGq9gHtY7psJatJbbYpeHMtHTrdBad0sP9vFumdL5FtxeS+YULI3XVJ0kQ6rE8hGxf3 oNtWenVlh192lFLsqm50dR/E6yNVbQbzFNb6mqxqE66K/0/BXT+p5oDYzsBBDrgTxajP83QUTV9L MUt4RetbbSR6wOp6np2sAEtT3CRK21dll14wAG7ljegHQG+kA5y1HExuCcf2LvLqXMAw1q99+sRq e4S6jS2ypwilDFJGnBrbZO/ZPAr16zWE1AAcFz9D0EggaxChbmwZo8LfiPPXK37eQhboE6SxOYdH VMGL+iDFchUAsTCJsiNAjUkxtaq8qVsS8Omxe+RR4nCY6FGV552E1iMULBAcCusvwS0GeNLD8zbx nWmoi+D0dw7J5JkI35bmoEkzhRG9+OI15Y5pGHREu4OHxS9EaVQmq0IPDUUdkw+yU0TCjrbnvAvT Sx/08Ql3JYuMyIn3XAcbghEcNFDsFa1QphhNCm42xQivxRhkPF1d+xsm3ut51PT9QtNBiLhWCmxZ /dV6cEhMx1x2w4ZMFRq/0YdYEy7XeUq4XhYsOrspfHiBrRFiUxZN2wqlTr4/rP5esY8Nxx83qj3x bHTSTgLm/YAJpVPbRULCi9mdSQVCZw2j1ueQtSkfnUc4ng39ee5SMTwf4o0Zi1cCC+pLqVX7+RAV n4GHk7ngZQGj8Vfos5+7hL2quhJv33YK/T8BXIdOwCKqyydaOQMchQDV7MAE+do/X7i3gbpr6CbY 85qnTec0xpMHNTG2U73iqGXT4vI4QzpMKysdCKdHYbdJsswuuKscxid24tgVQol4ZRqDlRnFhLj1 fiMr0OMy1c/pTjJzm9iLigbaFWAy9jCumUNJhiZ0mpd+hGTLTDVRwpZB92xpfWJvYanUqy+yPbUV r2QL4YZ4xQaiNbvWub42onfXYpVK4EaUw8rZoMWYjVISKFIEW2UEofoO4J1OLr94b1NFho80Kzt3 6f58g4WkYydb8sFiBl8tM1/jAMclLwYn6/wavdhYQp8azxGLQgfHYkTQGpAOdONd2YuKm4LWV4jN TvcXuHHCiJvHZtz9+W0qWz6zEEwxDA5M+RVlwabk5qtMcSxh+7IzDMIn7uQFCgdd5+gb2vyMu0tZ knH6LFNBfhnXoG3DDCu8wBaoG63fkMFEbF9bpojfYLHXX2jSG2E6mOL+V6Pd8yPV9JrUOC6U9bha Txm5ymcA/gy1e1LOrDiFB9ZdZi7Zz7WxNs9mu2NWdLYmeXvPpKQsl8b2tAghd52BwKtvIH6gwcT0 N37jub7a8rsW4wvyexrrem/AkeWkxC3d3k05JxiMRTGbb7g7rdOS/+zV1z3gR/trbhMioQhf+sY8 7oDQz6f5sbKTBjdF3O64mAIPRU6egaVqZGoTpJziLabDojBjAaL82t8wW+ewQOJ7H6FjQiIfFPAB pkuxBQPNCRo0S6iZ/9mOYzdsdad4RYGA7DRXORvhsBTR48hadUuA5vLljb/Eat03zJdhw93b6fQC uVp8qOA42orYZZA3NSH4LjPUm/0ZLWpUYndojnj5Sm93aDdrJPk1MbMij9j5hpE1s6jaRpARWLcu FUgA+udne03fD6AH8oUfRWbH5jYx5PGjMXHLgWmGrTNd8CqzMpZ4PwX7NkVd4v94qhL4x8SFiCG7 T4xd4WxCDAW3iDNY1Tx53ivY9Zons2W38BVHkzCv72UTlsyBuGjnmIXRCbVUW3fq8DsHdivXBb3F gijXEexxUnAX+OZ5nb3fz0PTH+Qx/diwqi1Rdr88EajJMhFT/IH5FG9Dx5c8IhNs+Qe6pFTtTLh5 AHFZPl557IG/hPGl0g761dlBXEH2WAdLTKj7aINyFB9FiDKdV9CFTFkC2r+8OOtkJw+NF/QJxgz2 O4H2jKTl0ElRsiAnpElLU1wFPUnxmv1GGY252nNJu/HkJ859CvVugrotS8BFk3CEMsnnS5L8NJBW l4cdKwzcINgeUXUCJiGiiS/NQQe0lxyZfQ5SgbY1/ilTexseZqXMXAhmOkp2ro1eY2L0oCYaFh6a RhgBBpx7dZ7+qSZrjLHHeGD4cUi0LiH5wG577A0JT1DB6bUPpdf5AlfFcTC/KzKrtiSnIs4empm4 ZZgwpy4yTUVcHquo2/nRSDhCrU3+xM1YeLvVQA4hOt0nylbWmNPe6wulpWB6hL2cTgKxfvRnLoDh pwd2mRvgL52gNYhZrucp/3LqgUmboJdYwW3iKO9W/2dIr0bu/7r2PTafpGU6g8wqdWsudCuuE/lF tIbKo+yw2r4WBRHMd6csngzMj+p5jYu+CprnQJQ/fYedPb2lHzvmG2qnk1DzwU1MB9/0+2VLHqGB 5XqdmbBz27kHZwNquKk0r3SKAAq3MZI0UscpOUBgRRjDrmHYtRU69hBg9p8wI+2UXXUx3VGI1D9F TZNv68FzZJjCSnaOU50zCTMNijAEv5NkNZa4kW8MyeuwRS1DFXI+g9mAHVpAWb7KLSOyDND0Nd+S qPhBaLO7oO/3/bwEivodAUW6nsLhs92OCztWW+SApMeoFFYZg94i9aYTUVrShufAiRHQhs2QZ4ok D5ogrsRKU6a5/svWV/fqVon2n7GOQA36+adwVT6ZiPHCFVPZ90d6/zlOwM8dC0khrwGEx0x5zKhw g47yxo7tzNbpdmu96bEGMKHajhcVHMpk/QYnXNvBrFgQQW1TPMUKhpjhp5GZ0EVBV2+g9bE9hDUo s8JZpWYGWv8sh6bQuajPpg5xGmzWnyAalOJqUAdXiFLxYIbP+Im5q5qGMhjAuCMc9HuXlZaOTAwo H7NYhVT3+JOOjgwouwfFSU+P87Q6pAKtcL0NVws9tGVXqwwflNwqhMbioP7jnJpzqhMuoxjtZq/S G/lxFuEUxbD9PpVMcqE6yVqes562Zc1K5RR4b1hhK78+pizoU77PEI3R7nLzRfJRQ8U5dX60gZbn QFG95xhE3Ssrh2eP8lD564/fhwooJOAx+NYY37fyoQlS/mvC1/e5dzKzoZzTmENWOZcFgxCMm+8Y rjb3tvYd666ok0vwgE/2EcClmLjO9OF6GwGC2XGTUKNTg+RjcgYMwXixm/eAiKY5iz1iANMyh2i6 ULD53iM8nPxZWFiDF15f4saOm3QAlSQuw9oJ4gypi+BlPtod1Zkdlx2+Wtfe3nezA20fU5kfTehl d2rhWckJtbHkPxMJS67O3UnTW68PNf0safzbR75Sals51pYOHgkZTYNi0LTaGVAFDueHTL3ALkGI qLxNOLgFGnF+2KsCBd7JV2I4UsfbwfwHOcg358QOoxgRFZQMM4d0ZZ179HwMnFGD2RRsBVcNXtek MMENZLPDXnEZlZ2an8COQ50a2yHw4SqtkwSl1Eoe2i1wUcISAiJzm+zdKQui+iyw4DJQ3eblEZbo OfrHzZhGIsy0wfjhicO3iZJpVolCZhwkIOwLooDE9Z+RoQVfl9+7z4l2b9WQ+Te/caiuLGwDgQox pN9eCFST6+KSexelLHqP4jPT+xBuc1hJSuoLXny3PwuLH4WdXnZodTbKyVMCvRpePazkUzq42cfH B14HqxypeG2ymkU= `protect end_protected

bsd-2-clause

d9a013b73cd003072454e9cb662380f0

0.942266

1.857759

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/styles/code_examples/spi_slave.vhd

1

34,119

---------------------------------------------------------------------------------- -- Author: Jonny Doin, [email protected] -- -- Create Date: 15:36:20 05/15/2011 -- Module Name: SPI_SLAVE - RTL -- Project Name: SPI INTERFACE -- Target Devices: Spartan-6 -- Tool versions: ISE 13.1 -- Description: -- -- This block is the SPI slave interface, implemented in one single entity. -- All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard. -- The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'. -- Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line. -- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two -- clock domains. -- -- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o. -- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch -- signaling ('PREFETCH'). -- -- PARALLEL WRITE INTERFACE -- The parallel interface has a input port 'di_i' and an output port 'do_o'. -- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. -- When the core needs input data, a look ahead data request strobe , 'di_req_o' is pulsed 'PREFETCH' 'spi_sck_i' -- cycles in advance to synchronize a user pipelined memory or fifo to present the next input data at 'di_i' -- in time to have continuous clock at the spi bus, to allow back-to-back continuous load. -- The data request strobe on 'di_req_o' is 2 'clk_i' clock cycles long. -- The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid -- race conditions at the register transfer. -- The user circuit places data at the 'di_i' port and strobes the 'wren_i' line for one rising edge of 'clk_i'. -- For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one -- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer. -- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time. -- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle, -- if continuous transmission is intended. -- When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'. -- -- PARALLEL WRITE PIPELINED SEQUENCE -- ================================= -- __ __ __ __ __ __ __ -- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock -- ___________ -- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'clk_i' -- ______________ ___________________________... -- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'clk_i' rising edge -- ________ -- wren_i __________________________/ \______... -- 'wren_i' enables latch on rising edge of 'clk_i' -- -- -- PARALLEL READ INTERFACE -- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete -- word is received, the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'. -- The signal 'do_valid_o' is strobed 3 'clk_i' clocks after, to directly drive a synchronous memory or fifo write enable. -- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'. -- When the interface is idle, data at the 'do_o' port holds the last word received. -- -- PARALLEL READ PIPELINED SEQUENCE -- ================================ -- ______ ______ ______ ______ -- clk_spi_i ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- spi base clock -- __ __ __ __ __ __ __ __ __ -- clk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock -- _________________ _____________________________________... -- 1) received data is transferred to 'do_buffer_reg' -- do_o __old_data_______X__________new_data___________________... -- after last bit received, at next shift clock. -- ____________ -- do_valid_o ________________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'clk_i' cycles -- -- on the 3rd 'clk_i' rising edge. -- -- -- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. -- ------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- -- -- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave -- -- Author(s): Jonny Doin, [email protected], [email protected] -- -- Copyright (C) 2011 Jonny Doin -- ----------------------------- -- -- This source file may be used and distributed without restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains the original copyright notice and the associated -- disclaimer. -- -- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser -- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or -- (at your option) any later version. -- -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more -- details. -- -- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download -- it from http://www.gnu.org/licenses/lgpl.txt -- ------------------------------ REVISION HISTORY ----------------------------------------------------------------------- -- -- 2011/05/15 v0.10.0050 [JD] created the slave logic, with 2 clock domains, from SPI_MASTER module. -- 2011/05/15 v0.15.0055 [JD] fixed logic for starting state when CPHA='1'. -- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries. -- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core. -- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets. -- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches. -- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce -- synthesis LUT overhead in Spartan-6 architecture. -- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic. -- 2011/06/12 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. -- 2011/06/17 v0.97.0079 [JD] implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset. -- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock. -- 2011/07/29 v2.00.0110 [JD] FIX: CPHA bugs: -- - redesigned core clocking to address all CPOL and CPHA configurations. -- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite -- clock phases from SHIFT_EDGE. -- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions -- for each state, to avoid reported inference problems in some synthesis engines. -- Streamlined port names and indentation blocks. -- 2011/08/01 v2.01.0115 [JD] Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core. -- Simulated in iSim with the master core for continuous transmission mode. -- 2011/08/02 v2.02.0120 [JD] Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit. -- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes. -- 2011/08/04 v2.02.0121 [JD] Changed minor comment bugs in the combinatorial fsm logic. -- 2011/08/08 v2.02.0122 [JD] FIX: continuous transfer mode bug. When wren_i is not strobed prior to state 1 (last bit), the -- sequencer goes to state 0, and then to state 'N' again. This produces a wrong bit-shift for received -- data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and -- sequencing from state 1 to N as long as the master clock is present. If the user does not write new -- data, the last data word is repeated. -- 2011/08/08 v2.02.0123 [JD] ISSUE: continuous transfer mode bug, for ignored 'di_req' cycles. Instead of repeating the last data word, -- the slave will send (others => '0') instead. -- 2011/08/28 v2.02.0126 [JD] ISSUE: the miso_o MUX that preloads tx_bit when slave is desselected will glitch for CPHA='1'. -- FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update. -- ----------------------------------------------------------------------------------------------------------------------- -- TODO -- ==== -- ----------------------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity spi_slave is Generic ( N : positive := 32; -- 32bit serial word length is default CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase. PREFETCH : positive := 3); -- prefetch lookahead cycles Port ( clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers) spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core) spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output di_req_o : out std_logic; -- preload lookahead data request line di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i) wren_i : in std_logic := 'X'; -- user data write enable wr_ack_o : out std_logic; -- write acknowledge do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge. do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i) --- debug ports: can be removed for the application circuit --- do_transfer_o : out std_logic; -- debug: internal transfer driver wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher rx_bit_next_o : out std_logic; -- debug: internal rx bit state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register ); end spi_slave; --================================================================================================================ -- SYNTHESIS CONSIDERATIONS -- ======================== -- There are several output ports that are used to simulate and verify the core operation. -- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing -- circuitry. -- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the -- synthesis tool will remove the receive logic from the generated circuitry. -- Alternatively, you can remove these ports and related circuitry once the core is verified and -- integrated to your circuit. --================================================================================================================ architecture rtl of spi_slave is -- constants to control FlipFlop synthesis constant SHIFT_EDGE : std_logic := (CPOL xnor CPHA); -- MOSI data is captured and shifted at this SCK edge constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); -- MISO data is updated at this SCK edge ------------------------------------------------------------------------------------------ -- GLOBAL RESET: -- all signals are initialized to zero at GSR (global set/reset) by giving explicit -- initialization values at declaration. This is needed for all Xilinx FPGAs, and -- especially for the Spartan-6 and newer CLB architectures, where a local reset can -- reduce the usability of the slice registers, due to the need to share the control -- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice. -- By using GSR for the initialization, and reducing RESET local init to the really -- essential, the model achieves better LUT/FF packing and CLB usability. ------------------------------------------------------------------------------------------ -- internal state signals for register and combinatorial stages signal state_next : natural range N downto 0 := 0; -- state 0 is idle state signal state_reg : natural range N downto 0 := 0; -- state 0 is idle state -- shifter signals for register and combinatorial stages signal sh_next : std_logic_vector (N-1 downto 0); signal sh_reg : std_logic_vector (N-1 downto 0); -- mosi and miso connections signal rx_bit_next : std_logic; -- sample of MOSI input signal tx_bit_next : std_logic; signal tx_bit_reg : std_logic; -- drives MISO during sequential logic signal preload_miso : std_logic; -- controls the MISO MUX -- buffered di_i data signals for register and combinatorial stages signal di_reg : std_logic_vector (N-1 downto 0); -- internal wren_i stretcher for fsm combinatorial stage signal wren : std_logic; signal wr_ack_next : std_logic := '0'; signal wr_ack_reg : std_logic := '0'; -- buffered do_o data signals for register and combinatorial stages signal do_buffer_next : std_logic_vector (N-1 downto 0); signal do_buffer_reg : std_logic_vector (N-1 downto 0); -- internal signal to flag transfer to do_buffer_reg signal do_transfer_next : std_logic := '0'; signal do_transfer_reg : std_logic := '0'; -- internal input data request signal signal di_req_next : std_logic := '0'; signal di_req_reg : std_logic := '0'; -- cross-clock do_valid_o logic signal do_valid_next : std_logic := '0'; signal do_valid_A : std_logic := '0'; signal do_valid_B : std_logic := '0'; signal do_valid_C : std_logic := '0'; signal do_valid_D : std_logic := '0'; signal do_valid_o_reg : std_logic := '0'; -- cross-clock di_req_o logic signal di_req_o_next : std_logic := '0'; signal di_req_o_A : std_logic := '0'; signal di_req_o_B : std_logic := '0'; signal di_req_o_C : std_logic := '0'; signal di_req_o_D : std_logic := '0'; signal di_req_o_reg : std_logic := '0'; begin --============================================================================================= -- GENERICS CONSTRAINTS CHECKING --============================================================================================= -- minimum word width is 8 bits assert N >= 8 report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum" severity FAILURE; -- maximum prefetch lookahead check assert PREFETCH <= N-5 report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum" severity FAILURE; --============================================================================================= -- GENERATE BLOCKS --============================================================================================= --============================================================================================= -- DATA INPUTS --============================================================================================= -- connect rx bit input rx_bit_proc : rx_bit_next <= spi_mosi_i; --============================================================================================= -- CROSS-CLOCK PIPELINE TRANSFER LOGIC --============================================================================================= -- do_valid_o and di_req_o strobe output logic -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a -- fixed-length delayed pulse for the output flags, at the parallel clock domain out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg, do_valid_A, do_valid_B, do_valid_D, di_req_o_A, di_req_o_B, di_req_o_D) is begin if clk_i'event and clk_i = '1' then -- clock at parallel port clock -- do_transfer_reg -> do_valid_o_reg do_valid_A <= do_transfer_reg; -- the input signal must be at least 2 clocks long do_valid_B <= do_valid_A; -- feed it to a ripple chain of FFDs do_valid_C <= do_valid_B; do_valid_D <= do_valid_C; do_valid_o_reg <= do_valid_next; -- registered output pulse -- di_req_reg -> di_req_o_reg di_req_o_A <= di_req_reg; -- the input signal must be at least 2 clocks long di_req_o_B <= di_req_o_A; -- feed it to a ripple chain of FFDs di_req_o_C <= di_req_o_B; di_req_o_D <= di_req_o_C; di_req_o_reg <= di_req_o_next; -- registered output pulse end if; -- generate a 2-clocks pulse at the 3rd clock cycle do_valid_next <= do_valid_A and do_valid_B and not do_valid_D; di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D; end process out_transfer_proc; -- parallel load input registers: data register and write enable in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is begin -- registered data input, input register with clock enable if clk_i'event and clk_i = '1' then if wren_i = '1' then di_reg <= di_i; -- parallel data input buffer register end if; end if; -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset) if clk_i'event and clk_i = '1' then if wren_i = '1' then -- wren_i is the sync preset for wren wren <= '1'; elsif wr_ack_reg = '1' then -- wr_ack is the sync reset for wren wren <= '0'; end if; end if; end process in_transfer_proc; --============================================================================================= -- REGISTER TRANSFER PROCESSES --============================================================================================= -- fsm state and data registers change on spi SHIFT_EDGE core_reg_proc : process (spi_sck_i, spi_ssel_i) is begin -- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1) -- state fsm register (fdr) if spi_ssel_i = '1' then -- async clr state_reg <= 0; -- state falls back to idle when slave not selected elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on SHIFT edge, update state register state_reg <= state_next; -- core fsm changes state with spi SHIFT clock end if; -- FFD registers clocked on SHIFT edge -- rtl core registers (fd) if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then -- on fsm state change, update all core registers sh_reg <= sh_next; -- core shift register do_buffer_reg <= do_buffer_next; -- registered data output do_transfer_reg <= do_transfer_next; -- cross-clock transfer flag di_req_reg <= di_req_next; -- input data request wr_ack_reg <= wr_ack_next; -- wren ack for data load synchronization end if; -- FFD registers clocked on CHANGE edge and cleared on idle (spi_ssel_i = 1) -- miso MUX preload control register (fdp) if spi_ssel_i = '1' then -- async preset preload_miso <= '1'; -- miso MUX sees top bit of parallel input when slave not selected elsif spi_sck_i'event and spi_sck_i = CHANGE_EDGE then -- on CHANGE edge, change to tx_reg output preload_miso <= spi_ssel_i; -- miso MUX sees tx_bit_reg when it is driven by SCK end if; -- FFD registers clocked on CHANGE edge -- tx_bit register (fd) if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then tx_bit_reg <= tx_bit_next; -- update MISO driver from the MSb end if; end process core_reg_proc; --============================================================================================= -- COMBINATORIAL LOGIC PROCESSES --============================================================================================= -- state and datapath combinatorial logic core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg, do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is begin -- all output signals are assigned to (avoid latches) sh_next <= sh_reg; -- shift register tx_bit_next <= tx_bit_reg; -- MISO driver do_buffer_next <= do_buffer_reg; -- output data buffer do_transfer_next <= do_transfer_reg; -- output data flag wr_ack_next <= wr_ack_reg; -- write enable acknowledge di_req_next <= di_req_reg; -- data input request state_next <= state_reg; -- fsm control state case state_reg is when (N) => -- deassert 'di_rdy' and stretch do_valid wr_ack_next <= '0'; -- acknowledge data in transfer di_req_next <= '0'; -- prefetch data request: deassert when shifting data tx_bit_next <= sh_reg(N-1); -- output next MSbit sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb state_next <= state_reg - 1; -- update next state at each sck pulse when (N-1) downto (PREFETCH+3) => -- remove 'do_transfer' and shift bits do_transfer_next <= '0'; -- reset 'do_valid' transfer signal di_req_next <= '0'; -- prefetch data request: deassert when shifting data wr_ack_next <= '0'; -- remove data load ack for all but the load stages tx_bit_next <= sh_reg(N-1); -- output next MSbit sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb state_next <= state_reg - 1; -- update next state at each sck pulse when (PREFETCH+2) downto 3 => -- raise prefetch 'di_req_o' signal di_req_next <= '1'; -- request data in advance to allow for pipeline delays wr_ack_next <= '0'; -- remove data load ack for all but the load stages tx_bit_next <= sh_reg(N-1); -- output next MSbit sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb state_next <= state_reg - 1; -- update next state at each sck pulse when 2 => -- transfer received data to do_buffer_reg on next cycle di_req_next <= '1'; -- request data in advance to allow for pipeline delays wr_ack_next <= '0'; -- remove data load ack for all but the load stages tx_bit_next <= sh_reg(N-1); -- output next MSbit sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0); -- shift inner bits sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb do_transfer_next <= '1'; -- signal transfer to do_buffer on next cycle do_buffer_next <= sh_next; -- get next data directly into rx buffer state_next <= state_reg - 1; -- update next state at each sck pulse when 1 => -- transfer rx data to do_buffer and restart if new data is written sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb di_req_next <= '0'; -- prefetch data request: deassert when shifting data state_next <= N; -- next state is top bit of new data if wren = '1' then -- load tx register if valid data present at di_reg wr_ack_next <= '1'; -- acknowledge data in transfer sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data else wr_ack_next <= '0'; -- no data reload for continuous transfer mode sh_next(N-1 downto 1) <= (others => '0'); -- clear transmit shift register tx_bit_next <= '0'; -- send ZERO end if; when 0 => -- idle state: start and end of transmission sh_next(0) <= rx_bit_next; -- shift in rx bit into LSb sh_next(N-1 downto 1) <= di_reg(N-2 downto 0); -- shift inner bits tx_bit_next <= di_reg(N-1); -- first output bit comes from the MSb of parallel data wr_ack_next <= '1'; -- acknowledge data in transfer di_req_next <= '0'; -- prefetch data request: deassert when shifting data do_transfer_next <= '0'; -- clear signal transfer to do_buffer state_next <= N; -- next state is top bit of new data when others => state_next <= 0; -- safe state end case; end process core_combi_proc; --============================================================================================= -- OUTPUT LOGIC PROCESSES --============================================================================================= -- data output processes do_o_proc : do_o <= do_buffer_reg; -- do_o always available do_valid_o_proc: do_valid_o <= do_valid_o_reg; -- copy registered do_valid_o to output di_req_o_proc: di_req_o <= di_req_o_reg; -- copy registered di_req_o to output wr_ack_o_proc: wr_ack_o <= wr_ack_reg; -- copy registered wr_ack_o to output ----------------------------------------------------------------------------------------------- -- MISO driver process: preload top bit of parallel data to MOSI at reset ----------------------------------------------------------------------------------------------- -- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit -- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic. spi_miso_o_proc: process (preload_miso, tx_bit_reg, di_reg) is begin if preload_miso = '1' then spi_miso_o <= di_reg(N-1); -- copy top bit of parallel data at reset else spi_miso_o <= tx_bit_reg; -- copy top bit of shifter at sequential operation end if; end process spi_miso_o_proc; --============================================================================================= -- DEBUG LOGIC PROCESSES --============================================================================================= -- these signals are useful for verification, and can be deleted after debug. do_transfer_proc: do_transfer_o <= do_transfer_reg; state_debug_proc: state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug rx_bit_next_proc: rx_bit_next_o <= rx_bit_next; wren_o_proc: wren_o <= wren; sh_reg_debug_proc: sh_reg_dbg_o <= sh_reg; -- export sh_reg to debug end architecture rtl;

gpl-3.0

cb3a9545fa1daa9c283638a582f93725

0.472552

4.738092

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/instantiation/rule_027_test_input.fixed_upper.vhd

1

565

architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : ENTITY fifo_dsn.1clk_fifo port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : ENTITY fifo_dsn.1clk_fifo port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;

gpl-3.0

eac4bf39ad58fbe7561a75bdee997f37

0.493805

2.742718

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_sf.vhd

1

50,791

------------------------------------------------------------------------------- -- axi_datamover_wr_sf.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_wr_sf.vhd -- -- Description: -- This file implements the AXI DataMover Write (S2MM) Store and Forward module. -- The design utilizes the AXI DataMover's new address pipelining -- control function. This module buffers write data and provides status and -- control features such that the DataMover Write Master is only allowed -- to post AXI WRite Requests if the associated write data needed to complete -- the Write Data transfer is present in the Data FIFO. In addition, the Write -- side logic is such that Write transfer requests can be pipelined to the -- AXI4 bus based on the Data FIFO contents but ahead of the actual Write Data -- transfers. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/21/2011 Initial Version for 13.3 -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; use proc_common_v4_0.proc_common_pkg.clog2; use proc_common_v4_0.srl_fifo_f; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_sfifo_autord; ------------------------------------------------------------------------------- entity axi_datamover_wr_sf is generic ( C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4; -- This parameter indicates the depth of the DataMover -- write address pipelining queues for the Main data transport -- channels. The effective address pipelining on the AXI4 -- Write Address Channel will be the value assigned plus 2. C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512; -- Sets the desired depth of the internal Data FIFO. -- C_MAX_BURST_LEN : Integer range 16 to 256 := 16; -- -- Indicates the max burst length being used by the external -- -- AXI4 Master for each AXI4 transfer request. -- C_DRE_IS_USED : Integer range 0 to 1 := 0; -- -- Indicates if the external Master is utilizing a DRE on -- -- the stream input to this module. C_MMAP_DWIDTH : Integer range 32 to 1024 := 64; -- Sets the AXI4 Memory Mapped Bus Data Width C_STREAM_DWIDTH : Integer range 8 to 1024 := 16; -- Sets the Stream Data Width for the Input and Output -- Data streams. C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2; -- Sets the bit width of the starting address offset port -- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH) C_FAMILY : String := "virtex7" -- Indicates the target FPGA Family. ); port ( -- Clock and Reset inputs ----------------------------------------------- -- aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- reset : in std_logic; -- -- Reset used for the internal syncronization logic -- ------------------------------------------------------------------------- -- Slave Stream Input ------------------------------------------------------------ -- sf2sin_tready : Out Std_logic; -- -- DRE Stream READY input -- -- sin2sf_tvalid : In std_logic; -- -- DRE Stream VALID Output -- -- sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- DRE Stream DATA input -- -- sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- DRE Stream STRB input -- -- sin2sf_tlast : In std_logic; -- -- DRE Xfer LAST input -- -- sin2sf_error : In std_logic; -- -- Stream Underrun/Overrun error input -- ----------------------------------------------------------------------------------- -- Starting Address Offset Input ------------------------------------------------- -- sin2sf_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); -- -- Used by Packing logic to set the initial data slice position for the -- -- packing operation. Packing is only needed if the MMap and Stream Data -- -- widths do not match. -- ----------------------------------------------------------------------------------- -- DataMover Write Side Address Pipelining Control Interface ---------------------- -- ok_to_post_wr_addr : Out Std_logic; -- -- Indicates that the internal FIFO has enough data -- -- physically present to supply one more max length -- -- burst transfer or a completion burst -- -- (tlast asserted) -- -- wr_addr_posted : In std_logic; -- -- Indication that a write address has been posted to AXI4 -- -- -- wr_xfer_cmplt : In Std_logic; -- -- Indicates that the Datamover has completed a Write Data -- -- transfer on the AXI4 -- -- -- wr_ld_nxt_len : in std_logic; -- -- Active high pulse indicating a new transfer LEN qualifier -- -- has been queued to the DataMover Write Data Controller -- -- wr_len : in std_logic_vector(7 downto 0); -- -- The actual LEN qualifier value that has been queued to the -- -- DataMover Write Data Controller -- ----------------------------------------------------------------------------------- -- Write Side Stream Out to DataMover S2MM ---------------------------------------- -- sout2sf_tready : In std_logic; -- -- Write READY input from the Stream Master -- -- sf2sout_tvalid : Out std_logic; -- -- Write VALID output to the Stream Master -- -- sf2sout_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); -- -- Write DATA output to the Stream Master -- -- sf2sout_tkeep : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); -- -- Write DATA output to the Stream Master -- -- sf2sout_tlast : Out std_logic; -- -- Write LAST output to the Stream Master -- -- sf2sout_error : Out std_logic -- -- Stream Underrun/Overrun error input -- ----------------------------------------------------------------------------------- ); end entity axi_datamover_wr_sf; architecture implementation of axi_datamover_wr_sf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Functions --------------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_pwr2_depth -- -- Function Description: -- Rounds up to the next power of 2 depth value in an input -- range of 1 to 8192 -- ------------------------------------------------------------------- function funct_get_pwr2_depth (min_depth : integer) return integer is Variable var_temp_depth : Integer := 16; begin if (min_depth = 1) then var_temp_depth := 1; elsif (min_depth = 2) then var_temp_depth := 2; elsif (min_depth <= 4) then var_temp_depth := 4; elsif (min_depth <= 8) then var_temp_depth := 8; elsif (min_depth <= 16) then var_temp_depth := 16; elsif (min_depth <= 32) then var_temp_depth := 32; elsif (min_depth <= 64) then var_temp_depth := 64; elsif (min_depth <= 128) then var_temp_depth := 128; elsif (min_depth <= 256) then var_temp_depth := 256; elsif (min_depth <= 512) then var_temp_depth := 512; elsif (min_depth <= 1024) then var_temp_depth := 1024; elsif (min_depth <= 2048) then var_temp_depth := 2048; elsif (min_depth <= 4096) then var_temp_depth := 4096; else -- assume 8192 depth var_temp_depth := 8192; end if; Return (var_temp_depth); end function funct_get_pwr2_depth; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_fifo_cnt_width -- -- Function Description: -- simple function to set the width of the data fifo read -- and write count outputs. ------------------------------------------------------------------- function funct_get_fifo_cnt_width (fifo_depth : integer) return integer is Variable temp_width : integer := 8; begin if (fifo_depth = 1) then temp_width := 1; elsif (fifo_depth = 2) then temp_width := 2; elsif (fifo_depth <= 4) then temp_width := 3; elsif (fifo_depth <= 8) then temp_width := 4; elsif (fifo_depth <= 16) then temp_width := 5; elsif (fifo_depth <= 32) then temp_width := 6; elsif (fifo_depth <= 64) then temp_width := 7; elsif (fifo_depth <= 128) then temp_width := 8; elsif (fifo_depth <= 256) then temp_width := 9; elsif (fifo_depth <= 512) then temp_width := 10; elsif (fifo_depth <= 1024) then temp_width := 11; elsif (fifo_depth <= 2048) then temp_width := 12; elsif (fifo_depth <= 4096) then temp_width := 13; else -- assume 8192 depth temp_width := 14; end if; Return (temp_width); end function funct_get_fifo_cnt_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_cntr_width -- -- Function Description: -- This function calculates the needed counter bit width from the -- number of count sates needed (input). -- ------------------------------------------------------------------- function funct_get_cntr_width (num_cnt_values : integer) return integer is Variable temp_cnt_width : Integer := 0; begin if (num_cnt_values <= 2) then temp_cnt_width := 1; elsif (num_cnt_values <= 4) then temp_cnt_width := 2; elsif (num_cnt_values <= 8) then temp_cnt_width := 3; elsif (num_cnt_values <= 16) then temp_cnt_width := 4; elsif (num_cnt_values <= 32) then temp_cnt_width := 5; elsif (num_cnt_values <= 64) then temp_cnt_width := 6; elsif (num_cnt_values <= 128) then temp_cnt_width := 7; else temp_cnt_width := 8; end if; Return (temp_cnt_width); end function funct_get_cntr_width; -- Constants --------------------------------------------------------------------------- Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant BLK_MEM_FIFO : integer := 1; Constant SRL_FIFO : integer := 0; Constant NOT_NEEDED : integer := 0; Constant WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits Constant TLAST_WIDTH : integer := 1; -- bits Constant EOP_ERR_WIDTH : integer := 1; -- bits Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH; Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH); -- Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN); Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH + --WSTB_WIDTH + TLAST_WIDTH + EOP_ERR_WIDTH; Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1; Constant DATA_OUT_LSB_INDEX : integer := 0; -- Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1; -- Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1; -- Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1; Constant TLAST_OUT_INDEX : integer := DATA_OUT_MSB_INDEX+1; Constant EOP_ERR_OUT_INDEX : integer := TLAST_OUT_INDEX+1; Constant WR_LEN_FIFO_DWIDTH : integer := 8; Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2); Constant LEN_CNTR_WIDTH : integer := 8; Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, LEN_CNTR_WIDTH); Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, LEN_CNTR_WIDTH); Constant WR_XFER_CNTR_WIDTH : integer := 8; Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH); Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH); Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH); Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH); -- Signals --------------------------------------------------------------------------- signal sig_good_sin_strm_dbeat : std_logic := '0'; signal sig_strm_sin_ready : std_logic := '0'; signal sig_sout2sf_tready : std_logic := '0'; signal sig_sf2sout_tvalid : std_logic := '0'; signal sig_sf2sout_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2sout_tlast : std_logic := '0'; signal sig_push_data_fifo : std_logic := '0'; signal sig_pop_data_fifo : std_logic := '0'; signal sig_data_fifo_full : std_logic := '0'; signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_dvalid : std_logic := '0'; signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_wr_addr_posted : std_logic := '0'; signal sig_wr_xfer_cmplt : std_logic := '0'; signal sig_wr_ld_nxt_len : std_logic := '0'; signal sig_push_len_fifo : std_logic := '0'; signal sig_pop_len_fifo : std_logic := '0'; signal sig_len_fifo_full : std_logic := '0'; signal sig_len_fifo_empty : std_logic := '0'; signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0'); signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0'); signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0'); signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_sub_len_uncom_wrcnt : std_logic := '0'; signal sig_incr_uncom_wrcnt : std_logic := '0'; signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_enough_dbeats_rcvd : std_logic := '0'; signal sig_sf2sout_eop_err_out : std_logic := '0'; signal sig_good_fifo_write : std_logic := '0'; begin --(architecture implementation) -- Write Side (S2MM) Control Flags port connections ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ; sig_wr_addr_posted <= wr_addr_posted ; sig_wr_xfer_cmplt <= wr_xfer_cmplt ; sig_wr_ld_nxt_len <= wr_ld_nxt_len ; sig_len_fifo_data_in <= wr_len ; -- Output Stream Port connections sig_sout2sf_tready <= sout2sf_tready ; sf2sout_tvalid <= sig_sf2sout_tvalid ; sf2sout_tdata <= sig_sf2sout_tdata ; sf2sout_tkeep <= sig_sf2sout_tkeep ; sf2sout_tlast <= sig_sf2sout_tlast and sig_sf2sout_tvalid ; sf2sout_error <= sig_sf2sout_eop_err_out ; -- Input Stream port connections sf2sin_tready <= sig_strm_sin_ready; sig_good_sin_strm_dbeat <= sin2sf_tvalid and sig_strm_sin_ready; ---------------------------------------------------------------- -- Packing Logic ------------------------------------------ ---------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_PACKING -- -- If Generate Description: -- Omits any packing logic in the Store and Forward module. -- The Stream and MMap data widths are the same. -- ------------------------------------------------------------ OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate begin sig_good_fifo_write <= sig_good_sin_strm_dbeat; sig_strm_sin_ready <= not(sig_data_fifo_full); sig_push_data_fifo <= sig_good_sin_strm_dbeat; -- Concatonate the Stream inputs into the single FIFO data in value sig_data_fifo_data_in <= sin2sf_error & sin2sf_tlast & -- sin2sf_tkeep & sin2sf_tdata; end generate OMIT_PACKING; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_PACKING -- -- If Generate Description: -- Includes packing logic in the Store and Forward module. -- The MMap Data bus is wider than the Stream width. -- ------------------------------------------------------------ INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH; Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH; Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH + EOP_ERR_WIDTH; Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO); Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, OFFSET_CNTR_WIDTH); Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH); -- Types ----------------------------------------------------------------------------- type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(DATA_SLICE_WIDTH-1 downto 0); type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0); -- local signals signal lsig_data_slice_reg : lsig_data_slice_type; signal lsig_flag_slice_reg : lsig_flag_slice_type; signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0'); signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0'); signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_ld_offset : std_logic := '0'; signal lsig_incr_offset : std_logic := '0'; signal lsig_offset_cntr_eq_max : std_logic := '0'; signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal lsig_tlast_or : std_logic := '0'; signal lsig_eop_err_or : std_logic := '0'; signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0'); signal lsig_partial_eop_err_or : std_logic_vector(MMAP2STRM_WIDTH_RATO downto 0) := (others => '0'); signal lsig_packer_full : std_logic := '0'; signal lsig_packer_empty : std_logic := '0'; signal lsig_set_packer_full : std_logic := '0'; signal lsig_good_push2fifo : std_logic := '0'; signal lsig_first_dbeat : std_logic := '0'; begin -- Assign the flag indicating that a fifo write is going -- to occur at the next rising clock edge. sig_good_fifo_write <= lsig_good_push2fifo; -- Generate the stream ready sig_strm_sin_ready <= not(lsig_packer_full) or lsig_good_push2fifo ; -- Format the FIFO input data sig_data_fifo_data_in <= lsig_eop_err_or & -- MS Bit lsig_tlast_or & lsig_combined_data ; -- LS Bits -- Generate a write to the Data FIFO input sig_push_data_fifo <= lsig_packer_full; -- Generate a flag indicating a write to the DataFIFO -- is going to complete lsig_good_push2fifo <= lsig_packer_full and not(sig_data_fifo_full); -- Generate the control that loads the starting address -- offset for the next input packet lsig_ld_offset <= lsig_first_dbeat and sig_good_sin_strm_dbeat; -- Generate the control for incrementing the offset counter lsig_incr_offset <= sig_good_sin_strm_dbeat; -- Generate a flag indicating the packer input register -- array is full or has loaded the last data beat of -- the input paket lsig_set_packer_full <= sig_good_sin_strm_dbeat and (sin2sf_tlast or lsig_offset_cntr_eq_max); -- Check to see if the offset counter has reached its max -- value lsig_offset_cntr_eq_max <= '1' --when (lsig_0ffset_cntr = OFFSET_CNT_MAX) when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX) Else '0'; -- Mux between the input start offset and the offset counter -- output to use for the packer slice load control. lsig_0ffset_to_to_use <= UNSIGNED(sin2sf_strt_addr_offset) when (lsig_first_dbeat = '1') Else lsig_0ffset_cntr; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_LD_MARKER -- -- Process Description: -- Implements the flop indicating the first databeat of -- an input data packet. -- ------------------------------------------------------------- IMP_OFFSET_LD_MARKER : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_first_dbeat <= '1'; elsif (sig_good_sin_strm_dbeat = '1' and sin2sf_tlast = '0') then lsig_first_dbeat <= '0'; Elsif (sig_good_sin_strm_dbeat = '1' and sin2sf_tlast = '1') Then lsig_first_dbeat <= '1'; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_LD_MARKER; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_CNTR -- -- Process Description: -- Implements the address offset counter that is used to -- steer the data loads into the packer register slices. -- Note that the counter has to be loaded with the starting -- offset plus one to sync up with the data input. ------------------------------------------------------------- IMP_OFFSET_CNTR : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_0ffset_cntr <= (others => '0'); Elsif (lsig_ld_offset = '1') Then lsig_0ffset_cntr <= UNSIGNED(sin2sf_strt_addr_offset) + OFFSET_CNT_ONE; elsif (lsig_incr_offset = '1') then lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PACK_REG_FULL -- -- Process Description: -- Implements the Packer Register full/empty flags -- ------------------------------------------------------------- IMP_PACK_REG_FULL : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_packer_full <= '0'; lsig_packer_empty <= '1'; Elsif (lsig_set_packer_full = '1' and lsig_packer_full = '0') Then lsig_packer_full <= '1'; lsig_packer_empty <= '0'; elsif (lsig_set_packer_full = '0' and lsig_good_push2fifo = '1') then lsig_packer_full <= '0'; lsig_packer_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PACK_REG_FULL; ------------------------------------------------------------ -- For Generate -- -- Label: DO_REG_SLICES -- -- For Generate Description: -- -- Implements the Packng Register Slices -- -- ------------------------------------------------------------ DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate begin -- generate the register load enable for each slice segment based -- on the address offset count value lsig_segment_ld(slice_index) <= '1' when (sig_good_sin_strm_dbeat = '1' and TO_INTEGER(lsig_0ffset_to_to_use) = slice_index) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DATA_SLICE -- -- Process Description: -- Implement a data register slice for the packer. -- ------------------------------------------------------------- IMP_DATA_SLICE : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_data_slice_reg(slice_index) <= (others => '0'); elsif (lsig_segment_ld(slice_index) = '1') then lsig_data_slice_reg(slice_index) <= sin2sf_tdata; -- optional clear of slice reg elsif (lsig_segment_ld(slice_index) = '0' and lsig_good_push2fifo = '1') then lsig_data_slice_reg(slice_index) <= (others => '0'); else null; -- Hold Current State end if; end if; end process IMP_DATA_SLICE; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FLAG_SLICE -- -- Process Description: -- Implement a flag register slice for the packer. -- ------------------------------------------------------------- IMP_FLAG_SLICE : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_flag_slice_reg(slice_index) <= (others => '0'); elsif (lsig_segment_ld(slice_index) = '1') then lsig_flag_slice_reg(slice_index) <= sin2sf_tlast & -- bit 1 sin2sf_error; -- bit 0 elsif (lsig_segment_ld(slice_index) = '0' and lsig_good_push2fifo = '1') then lsig_flag_slice_reg(slice_index) <= (others => '0'); else null; -- Hold Current State end if; end if; end process IMP_FLAG_SLICE; end generate DO_REG_SLICES; -- Do the OR functions of the Flags ------------------------------------- lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ; lsig_eop_err_or <= lsig_partial_eop_err_or(MMAP2STRM_WIDTH_RATO-1); lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1); lsig_partial_eop_err_or(0) <= lsig_flag_slice_reg(0)(0); ------------------------------------------------------------ -- For Generate -- -- Label: DO_FLAG_OR -- -- For Generate Description: -- Implement the OR of the TLAST and EOP Error flags. -- -- -- ------------------------------------------------------------ DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate begin lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or --lsig_partial_tlast_or(slice_index); lsig_flag_slice_reg(slice_index)(1); lsig_partial_eop_err_or(slice_index) <= lsig_partial_eop_err_or(slice_index-1) or --lsig_partial_eop_err_or(slice_index); lsig_flag_slice_reg(slice_index)(0); end generate DO_FLAG_OR; ------------------------------------------------------------ -- For Generate -- -- Label: DO_DATA_COMBINER -- -- For Generate Description: -- Combines the Data Slice register outputs into a single -- vector for input to the Data FIFO. -- -- ------------------------------------------------------------ DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate begin lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto (slice_index-1)*DATA_SLICE_WIDTH) <= lsig_data_slice_reg(slice_index-1); end generate DO_DATA_COMBINER; end generate INCLUDE_PACKING; ---------------------------------------------------------------- -- Data FIFO Logic ------------------------------------------ ---------------------------------------------------------------- -- FIFO Input attachments -- sig_push_data_fifo <= sig_good_sin_strm_dbeat; -- -- Concatonate the Stream inputs into the single FIFO data in value -- sig_data_fifo_data_in <= sin2sf_error & -- sin2sf_tlast & -- sin2sf_tkeep & -- sin2sf_tdata; -- FIFO Output to output stream attachments sig_sf2sout_tvalid <= sig_data_fifo_dvalid ; sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto DATA_OUT_LSB_INDEX); -- sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto -- TSTRB_OUT_LSB_INDEX); -- When this Store and Forward is enabled, the Write Data Controller ignores the -- TKEEP input so this is not sent through the FIFO. sig_sf2sout_tkeep <= (others => '1'); sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ; sig_sf2sout_eop_err_out <= sig_data_fifo_data_out(EOP_ERR_OUT_INDEX) ; -- FIFO Rd/WR Controls sig_pop_data_fifo <= sig_sout2sf_tready and sig_data_fifo_dvalid; ------------------------------------------------------------ -- Instance: I_DATA_FIFO -- -- Description: -- Implements the Store and Forward data FIFO (synchronous) -- ------------------------------------------------------------ I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord generic map ( C_DWIDTH => DATA_FIFO_WIDTH , C_DEPTH => DATA_FIFO_DEPTH , C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH , C_NEED_ALMOST_EMPTY => NOT_NEEDED , C_NEED_ALMOST_FULL => NOT_NEEDED , C_USE_BLKMEM => BLK_MEM_FIFO , C_FAMILY => C_FAMILY ) port map ( -- Inputs SFIFO_Sinit => reset , SFIFO_Clk => aclk , SFIFO_Wr_en => sig_push_data_fifo , SFIFO_Din => sig_data_fifo_data_in , SFIFO_Rd_en => sig_pop_data_fifo , SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs SFIFO_DValid => sig_data_fifo_dvalid , SFIFO_Dout => sig_data_fifo_data_out , SFIFO_Full => sig_data_fifo_full , SFIFO_Empty => open , SFIFO_Almost_full => open , SFIFO_Almost_empty => open , SFIFO_Rd_count => open , SFIFO_Rd_count_minus1 => open , SFIFO_Wr_count => open , SFIFO_Rd_ack => open ); -------------------------------------------------------------------- -- Write Side Control Logic -------------------------------------------------------------------- -- Convert the LEN fifo data output to unsigned sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out); -- Resize the unsigned LEN output to the Data FIFO writecount width sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH); -- The actual number of databeats needed for the queued write transfer -- is the current LEN fifo output plus 1. sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1; -- Compare the uncommited receved data beat count to that needed -- for the next queued write request. sig_enough_dbeats_rcvd <= '1' When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt) else '0'; -- Increment the uncommited databeat counter on a good input -- stream databeat (Read Side of SF) -- sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat; sig_incr_uncom_wrcnt <= sig_good_fifo_write; -- Subtract the current number of databeats needed from the -- uncommited databeat counter when the associated transfer -- address/qualifiers have been posted to the AXI Write -- Address Channel sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_UNCOM_DBEAT_CNTR -- -- Process Description: -- Implements the counter that keeps track of the received read -- data beat count that has not been commited to a transfer on -- the write side with a Write Address posting. -- ------------------------------------------------------------- IMP_UNCOM_DBEAT_CNTR : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then sig_uncom_wrcnt <= UNCOM_WRCNT_0; elsif (sig_incr_uncom_wrcnt = '1' and sig_sub_len_uncom_wrcnt = '1') then sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len; elsif (sig_incr_uncom_wrcnt = '1' and sig_sub_len_uncom_wrcnt = '0') then sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1; elsif (sig_incr_uncom_wrcnt = '0' and sig_sub_len_uncom_wrcnt = '1') then sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed; else null; -- hold current value end if; end if; end process IMP_UNCOM_DBEAT_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_ADDR_POST_FLAG -- -- Process Description: -- Implements the flag indicating that the pending write -- transfer's data beat count has been received on the input -- side of the Data FIFO. This means the Write side can post -- the associated write address to the AXI4 bus and the -- associated write data transfer can complete without CDMA -- throttling the Write Data Channel. -- -- The flag is cleared immediately after an address is posted -- to prohibit a second unauthorized posting while the control -- logic stabilizes to the next LEN FIFO value --. ------------------------------------------------------------- IMP_WR_ADDR_POST_FLAG : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1' or sig_wr_addr_posted = '1') then sig_ok_to_post_wr_addr <= '0'; else sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and sig_enough_dbeats_rcvd; end if; end if; end process IMP_WR_ADDR_POST_FLAG; ------------------------------------------------------------- -- LEN FIFO logic -- The LEN FIFO stores the xfer lengths needed for each queued -- write transfer in the DataMover S2MM Write Data Controller. sig_push_len_fifo <= sig_wr_ld_nxt_len and not(sig_len_fifo_full); sig_pop_len_fifo <= wr_addr_posted and not(sig_len_fifo_empty); ------------------------------------------------------------ -- Instance: I_WR_LEN_FIFO -- -- Description: -- Implement the LEN FIFO using SRL FIFO elements -- ------------------------------------------------------------ I_WR_LEN_FIFO : entity proc_common_v4_0.srl_fifo_f generic map ( C_DWIDTH => WR_LEN_FIFO_DWIDTH , C_DEPTH => WR_LEN_FIFO_DEPTH , C_FAMILY => C_FAMILY ) port map ( Clk => aclk , Reset => reset , FIFO_Write => sig_push_len_fifo , Data_In => sig_len_fifo_data_in , FIFO_Read => sig_pop_len_fifo , Data_Out => sig_len_fifo_data_out , FIFO_Empty => sig_len_fifo_empty , FIFO_Full => sig_len_fifo_full , Addr => open ); end implementation;

bsd-2-clause

9c96fdb7e61a300e197902c81c09e91f

0.418106

5.006999

false

NicoLedwith/Dr.AluOpysel

Works/prog_rom.vhd

2

19,877

----------------------------------------------------------------------------- -- Definition of a single port ROM for RATASM defined by prog_rom.psm -- -- Generated by RATASM Assembler -- -- Standard IEEE libraries -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; ----------------------------------------------------------------------------- entity prog_rom is port ( ADDRESS : in std_logic_vector(9 downto 0); INSTRUCTION : out std_logic_vector(17 downto 0); CLK : in std_logic); end prog_rom; architecture low_level_definition of prog_rom is ----------------------------------------------------------------------------- -- Attributes to define ROM contents during implementation synthesis. -- The information is repeated in the generic map for functional simulation. ----------------------------------------------------------------------------- attribute INIT_00 : string; attribute INIT_01 : string; attribute INIT_02 : string; attribute INIT_03 : string; attribute INIT_04 : string; attribute INIT_05 : string; attribute INIT_06 : string; attribute INIT_07 : string; attribute INIT_08 : string; attribute INIT_09 : string; attribute INIT_0A : string; attribute INIT_0B : string; attribute INIT_0C : string; attribute INIT_0D : string; attribute INIT_0E : string; attribute INIT_0F : string; attribute INIT_10 : string; attribute INIT_11 : string; attribute INIT_12 : string; attribute INIT_13 : string; attribute INIT_14 : string; attribute INIT_15 : string; attribute INIT_16 : string; attribute INIT_17 : string; attribute INIT_18 : string; attribute INIT_19 : string; attribute INIT_1A : string; attribute INIT_1B : string; attribute INIT_1C : string; attribute INIT_1D : string; attribute INIT_1E : string; attribute INIT_1F : string; attribute INIT_20 : string; attribute INIT_21 : string; attribute INIT_22 : string; attribute INIT_23 : string; attribute INIT_24 : string; attribute INIT_25 : string; attribute INIT_26 : string; attribute INIT_27 : string; attribute INIT_28 : string; attribute INIT_29 : string; attribute INIT_2A : string; attribute INIT_2B : string; attribute INIT_2C : string; attribute INIT_2D : string; attribute INIT_2E : string; attribute INIT_2F : string; attribute INIT_30 : string; attribute INIT_31 : string; attribute INIT_32 : string; attribute INIT_33 : string; attribute INIT_34 : string; attribute INIT_35 : string; attribute INIT_36 : string; attribute INIT_37 : string; attribute INIT_38 : string; attribute INIT_39 : string; attribute INIT_3A : string; attribute INIT_3B : string; attribute INIT_3C : string; attribute INIT_3D : string; attribute INIT_3E : string; attribute INIT_3F : string; attribute INITP_00 : string; attribute INITP_01 : string; attribute INITP_02 : string; attribute INITP_03 : string; attribute INITP_04 : string; attribute INITP_05 : string; attribute INITP_06 : string; attribute INITP_07 : string; ---------------------------------------------------------------------- -- Attributes to define ROM contents during implementation synthesis. ---------------------------------------------------------------------- attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_01 of ram_1024_x_18 : label is "86C181F181098179A000872169276712680066C087D1663F68124D3967118781"; attribute INIT_02 of ram_1024_x_18 : label is "6712800287D166C0880148918002815187D166004899A178D301D201478980E8"; attribute INIT_03 of ram_1024_x_18 : label is "822B0D11800287D1680187D166C0680087D15341682687D16600524151396827"; attribute INIT_04 of ram_1024_x_18 : label is "823086C1842186C1831186C1828186C18781A0018002822882324D9082324D98"; attribute INIT_05 of ram_1024_x_18 : label is "690C671468088721690C670F68088721690C670A680887516914670A68086607"; attribute INIT_06 of ram_1024_x_18 : label is "670A681A87D167CA681987516911670D681D87516914670A6818660780028721"; attribute INIT_07 of ram_1024_x_18 : label is "87D16713681B87D16714681A87D16714681987D1670C681C87D1670B681B87D1"; attribute INIT_08 of ram_1024_x_18 : label is "87D1670B681087516914670A681587516914670A680F6607800287D16712681C"; attribute INIT_09 of ram_1024_x_18 : label is "681387D16710681387D1670F681287D1670E681287D1670D681187D1670C6811"; attribute INIT_0A of ram_1024_x_18 : label is "477187D1663F68124769CD014E69800287D16713681487D16712681487D16711"; attribute INIT_0B of ram_1024_x_18 : label is "670C800287D166006812477187D1663F681247698D014E69800287D166006812"; attribute INIT_0C of ram_1024_x_18 : label is "85A186C18109854986C181098549800287D1660068126713800287D166006812"; attribute INIT_0D of ram_1024_x_18 : label is "3C0086EBDB017B1FDC017CFFDD017DFFA00386C18109862185A186C1810985F9"; attribute INIT_0E of ram_1024_x_18 : label is "8002875B4748870187D189018002872B4848880187D18901800286CB3D0086DB"; attribute INIT_0F of ram_1024_x_18 : label is "A8110401041F053F45414439800287930D1E8D0187216927680047696D006600"; attribute INIT_10 of ram_1024_x_18 : label is "000000000000000000000000000080024692449045912580A829040180002540"; attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3F of ram_1024_x_18 : label is "8648000000000000000000000000000000000000000000000000000000000000"; attribute INITP_00 of ram_1024_x_18 : label is "3CF3CF3CF3CFCFF4FCFCFCFF0000140034CF0CC3D38430A0004FF3CC00000000"; attribute INITP_01 of ram_1024_x_18 : label is "1A04E3CF422422488BBB400000013F4FD3C3C84F0F213CF3CF3CF3CF3CFCFF4F"; attribute INITP_02 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000000000000000000001FE16"; attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; begin ---------------------------------------------------------------------- --Instantiate the Xilinx primitive for a block RAM --INIT values repeated to define contents for functional simulation ---------------------------------------------------------------------- ram_1024_x_18: RAMB16_S18 --synthesitranslate_off --INIT values repeated to define contents for functional simulation generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"86C181F181098179A000872169276712680066C087D1663F68124D3967118781", INIT_02 => X"6712800287D166C0880148918002815187D166004899A178D301D201478980E8", INIT_03 => X"822B0D11800287D1680187D166C0680087D15341682687D16600524151396827", INIT_04 => X"823086C1842186C1831186C1828186C18781A0018002822882324D9082324D98", INIT_05 => X"690C671468088721690C670F68088721690C670A680887516914670A68086607", INIT_06 => X"670A681A87D167CA681987516911670D681D87516914670A6818660780028721", INIT_07 => X"87D16713681B87D16714681A87D16714681987D1670C681C87D1670B681B87D1", INIT_08 => X"87D1670B681087516914670A681587516914670A680F6607800287D16712681C", INIT_09 => X"681387D16710681387D1670F681287D1670E681287D1670D681187D1670C6811", INIT_0A => X"477187D1663F68124769CD014E69800287D16713681487D16712681487D16711", INIT_0B => X"670C800287D166006812477187D1663F681247698D014E69800287D166006812", INIT_0C => X"85A186C18109854986C181098549800287D1660068126713800287D166006812", INIT_0D => X"3C0086EBDB017B1FDC017CFFDD017DFFA00386C18109862185A186C1810985F9", INIT_0E => X"8002875B4748870187D189018002872B4848880187D18901800286CB3D0086DB", INIT_0F => X"A8110401041F053F45414439800287930D1E8D0187216927680047696D006600", INIT_10 => X"000000000000000000000000000080024692449045912580A829040180002540", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"8648000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"3CF3CF3CF3CFCFF4FCFCFCFF0000140034CF0CC3D38430A0004FF3CC00000000", INITP_01 => X"1A04E3CF422422488BBB400000013F4FD3C3C84F0F213CF3CF3CF3CF3CFCFF4F", INITP_02 => X"000000000000000000000000000000000000000000000000000000000001FE16", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") --synthesis translate_on port map( DI => "0000000000000000", DIP => "00", EN => '1', WE => '0', SSR => '0', CLK => clk, ADDR => address, DO => INSTRUCTION(15 downto 0), DOP => INSTRUCTION(17 downto 16)); -- end low_level_definition; -- ---------------------------------------------------------------------- -- END OF FILE prog_rom.vhd ----------------------------------------------------------------------

mit

798ba7c7b4943cb9ec43507215a7ebb6

0.735725

5.044924

false

Yarr/Yarr-fw

rtl/spartan6/rx-core/wb_rx_core.vhd

1

9,504

-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: RX core -- # Outputs are synchronous to wb_clk_i -- #################################### -- # Adress Map: -- # Adr[3:0]: -- # 0x0 : RX Enable Mask library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity wb_rx_core is generic ( g_NUM_RX : integer range 1 to 32 := 1 ); port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- RX IN rx_clk_i : in std_logic; rx_serdes_clk_i : in std_logic; rx_clk_locked_i : in std_logic; rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0); trig_tag_i : in std_logic_vector(31 downto 0); -- RX OUT (sync to sys_clk) rx_valid_o : out std_logic; rx_data_o : out std_logic_vector(31 downto 0); busy_o : out std_logic; debug_o : out std_logic_vector(31 downto 0) ); end wb_rx_core; architecture behavioral of wb_rx_core is function log2_ceil(val : integer) return natural is variable result : natural; begin for i in 0 to g_NUM_RX-1 loop if (val <= (2 ** i)) then result := i; exit; end if; end loop; return result; end function; constant c_ALL_ZEROS : std_logic_vector(g_NUM_RX-1 downto 0) := (others => '0'); component rr_arbiter generic ( g_CHANNELS : integer := g_NUM_RX ); port ( -- sys connect clk_i : in std_logic; rst_i : in std_logic; -- requests req_i : in std_logic_vector(g_CHANNELS-1 downto 0); -- grants gnt_o : out std_logic_vector(g_CHANNELS-1 downto 0) ); end component rr_arbiter; component fei4_rx_channel port ( -- Sys connect rst_n_i : in std_logic; clk_160_i : in std_logic; clk_640_i : in std_logic; enable_i : in std_logic; -- Input rx_data_i : in std_logic; trig_tag_i : in std_logic_vector(31 downto 0); -- Output rx_data_o : out std_logic_vector(25 downto 0); rx_valid_o : out std_logic; rx_stat_o : out std_logic_vector(7 downto 0); rx_data_raw_o : out std_logic_vector(7 downto 0) ); end component; COMPONENT rx_channel_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; type rx_data_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(25 downto 0); type rx_data_fifo_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(31 downto 0); type rx_stat_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(7 downto 0); signal rx_data : rx_data_array; signal rx_valid : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_stat : rx_stat_array; signal rx_data_raw : rx_stat_array; signal rx_fifo_dout :rx_data_fifo_array; signal rx_fifo_din : rx_data_fifo_array; signal rx_fifo_full : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_empty : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_rden : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_rden_t : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_wren : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_enable : std_logic_vector(31 downto 0); signal rx_serdes_clk : std_logic_vector(3 downto 0); signal channel : integer range 0 to g_NUM_RX-1; signal debug : std_logic_vector(31 downto 0); begin debug_o <= debug; debug(7 downto 0) <= rx_stat(0); debug(15 downto 8) <= rx_data_raw(0); debug(16) <= rx_valid(0); wb_proc: process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; rx_enable <= (others => '0'); wb_stall_o <= '0'; elsif rising_edge(wb_clk_i) then wb_ack_o <= '0'; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '1') then if (wb_adr_i(3 downto 0) = x"0") then -- Set enable mask wb_ack_o <= '1'; rx_enable <= wb_dat_i; else wb_ack_o <= '1'; end if; else if (wb_adr_i(3 downto 0) = x"0") then -- Read enable mask wb_dat_o <= rx_enable; wb_ack_o <= '1'; else wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end if; end if; end if; end if; end process wb_proc; -- Arbiter cmp_rr_arbiter : rr_arbiter port map ( clk_i => wb_clk_i, rst_i => not rst_n_i, req_i => not rx_fifo_empty, gnt_o => rx_fifo_rden_t ); --rx_valid_o <= '0' when (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) else '1'; --rx_data_o <= x"DEADBEEF" when (unsigned(rx_fifo_rden) = 0) else rx_fifo_dout(log2_ceil(to_integer(unsigned(rx_fifo_rden)))); reg_proc : process(wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then rx_fifo_rden <= (others => '0'); rx_valid_o <= '0'; channel <= 0; elsif rising_edge(wb_clk_i) then rx_fifo_rden <= rx_fifo_rden_t; channel <= log2_ceil(to_integer(unsigned(rx_fifo_rden_t))); if (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) then rx_valid_o <= '0'; rx_data_o <= x"DEADBEEF"; else rx_valid_o <= '1'; rx_data_o <= rx_fifo_dout(channel); end if; end if; end process reg_proc; -- cmp_ioclk_640_buf_0 : BUFG -- port map ( -- O => rx_serdes_clk(0), -- I => rx_serdes_clk_i); -- -- cmp_ioclk_640_buf_1 : BUFG -- port map ( -- O => rx_serdes_clk(1), -- I => rx_serdes_clk_i); BUFPLL_640_A : BUFPLL generic map ( DIVIDE => 4, -- DIVCLK divider (1-8) ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) ) port map ( IOCLK => rx_serdes_clk(0), -- 1-bit output: Output I/O clock LOCK => open, -- 1-bit output: Synchronized LOCK output SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2) GCLK => rx_clk_i, -- 1-bit input: BUFG clock input LOCKED => rx_clk_locked_i, -- 1-bit input: LOCKED input from PLL PLLIN => rx_serdes_clk_i -- 1-bit input: Clock input from PLL ); BUFPLL_640_B : BUFPLL generic map ( DIVIDE => 4, -- DIVCLK divider (1-8) ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) ) port map ( IOCLK => rx_serdes_clk(1), -- 1-bit output: Output I/O clock LOCK => open, -- 1-bit output: Synchronized LOCK output SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2) GCLK => rx_clk_i, -- 1-bit input: BUFG clock input LOCKED => rx_clk_locked_i, -- 1-bit input: LOCKED input from PLL PLLIN => rx_serdes_clk_i -- 1-bit input: Clock input from PLL ); -- Generate Rx Channels busy_o <= '0' when (rx_fifo_full = c_ALL_ZEROS) else '1'; rx_channels: for I in 0 to g_NUM_RX-1 generate begin bank2_1: if I<4 generate begin cmp_fei4_rx_channel: fei4_rx_channel PORT MAP( rst_n_i => rst_n_i, clk_160_i => rx_clk_i, clk_640_i => rx_serdes_clk(0), enable_i => rx_enable(I), rx_data_i => rx_data_i(I), trig_tag_i => trig_tag_i, rx_data_o => rx_data(I), rx_valid_o => rx_valid(I), rx_stat_o => rx_stat(I), rx_data_raw_o => rx_data_raw(I) ); end generate bank2_1; bank2_2: if (I>3 and I<15) generate begin cmp_fei4_rx_channel: fei4_rx_channel PORT MAP( rst_n_i => rst_n_i, clk_160_i => rx_clk_i, clk_640_i => rx_serdes_clk(0), enable_i => rx_enable(I), rx_data_i => not rx_data_i(I), trig_tag_i => trig_tag_i, rx_data_o => rx_data(I), rx_valid_o => rx_valid(I), rx_stat_o => rx_stat(I), rx_data_raw_o => rx_data_raw(I) ); end generate bank2_2; bank0: if I>=15 generate begin cmp_fei4_rx_channel: fei4_rx_channel PORT MAP( rst_n_i => rst_n_i, clk_160_i => rx_clk_i, clk_640_i => rx_serdes_clk(1), enable_i => rx_enable(I), rx_data_i => not rx_data_i(I), trig_tag_i => trig_tag_i, rx_data_o => rx_data(I), rx_valid_o => rx_valid(I), rx_stat_o => rx_stat(I), rx_data_raw_o => rx_data_raw(I) ); end generate bank0; rx_fifo_din(I) <= STD_LOGIC_VECTOR(TO_UNSIGNED(I,6)) & rx_data(I); rx_fifo_wren(I) <= rx_valid(I) and rx_enable(I); cmp_rx_channel_fifo : rx_channel_fifo PORT MAP ( rst => not rst_n_i, wr_clk => rx_clk_i, rd_clk => wb_clk_i, din => rx_fifo_din(I), wr_en => rx_fifo_wren(I), rd_en => rx_fifo_rden(I), dout => rx_fifo_dout(I), full => rx_fifo_full(I), empty => rx_fifo_empty(I) ); end generate; end behavioral;

gpl-3.0

e2a34a0d68078197c3e5db8faf61fe9c

0.559975

2.72087

false

siavooshpayandehazad/TTU_CPU_Project

pico_CPU/PicoCPU.vhd

1

1,867

library IEEE; use IEEE.std_logic_1164.all; USE ieee.std_logic_unsigned.ALL; use work.pico_cpu.all; entity PicoCPU is port( rst: in std_logic; clk: in std_logic; FlagOut: out std_logic_vector ( 3 downto 0); output: out std_logic_vector ( CPU_Bitwidth-1 downto 0) ); end PicoCPU; architecture RTL of PicoCPU is --------------------------------------------- -- Signals --------------------------------------------- signal Instr: std_logic_vector (CPU_Instwidth-1 downto 0):= (others=>'0'); signal InstrAdd , Mem_Rd_Address, Mem_Wrt_Address, DPUData, MEMDATA, DPU_Result: std_logic_vector (CPU_Bitwidth-1 downto 0) := (others=>'0'); signal MemRW: std_logic := '0'; signal DPUFlags: std_logic_vector (3 downto 0):= (others=>'0'); signal DPUCommand : std_logic_vector (10 downto 0):= (others=>'0'); signal Reg_in_sel: std_logic_vector (7 downto 0):= (others=>'0'); signal Reg_out_sel: std_logic_vector (2 downto 0):= (others=>'0'); begin --------------------------------------------- -- component instantiation --------------------------------------------- ControlUnit_comp: ControlUnit generic map (BitWidth => CPU_Bitwidth, InstructionWidth => CPU_Instwidth) port map (rst, clk, Instr ,InstrAdd , Mem_Rd_Address, Mem_Wrt_Address , MemRW, DPUFlags, DPUData,DPUCommand,Reg_in_sel,Reg_out_sel,DPU_Result); --instruction memory InstMem_comp: InstMem generic map (BitWidth => CPU_Bitwidth, InstructionWidth => CPU_Instwidth) port map (InstrAdd,Instr); --datapath unit DPU_comp: DPU generic map (BitWidth => CPU_Bitwidth) port map (MEMDATA, DPUData, clk,DPUCommand,Reg_in_sel,Reg_out_sel,rst,DPUFlags,DPU_Result); --memory Mem_comp: Mem generic map (BitWidth => CPU_Bitwidth) port map (Mem_Rd_Address, DPU_Result, Mem_Wrt_Address, clk,MemRW , rst , MEMDATA); FlagOut <= DPUFlags; output <= DPU_Result; end RTL;

gpl-2.0

87d1e72f53579bc390cf4820e6d19c26

0.631494

3.406934

false

niketancm/tsea26

lab2-3/rtl/pc_fsm.vhd

1

6,039

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity pc_fsm is port ( clk_i, reset_i: in std_logic; jump_decision_i: in std_logic; lc_pfc_loop_flag_i: in std_logic; lc_pfc_loope_i: in std_logic_vector(15 downto 0); ctrl_i: in std_logic_vector(5 downto 0); interrupt: in std_logic; pc_addr_bus_i: in std_logic_vector(15 downto 0); pfc_pc_add_opa_sel_o: out std_logic; pfc_lc_loopn_sel_o: out std_logic; pfc_pc_sel_o: out std_logic_vector(2 downto 0); pfc_inst_nop_o: out std_logic); end pc_fsm; architecture pc_fsm_rtl of pc_fsm is signal ctrl_c1 : std_logic_vector(5 downto 0); signal ctrl_c2 : std_logic_vector(5 downto 0); signal ctrl_c3 : std_logic_vector(5 downto 0); signal s0_state_sel : std_logic_vector (2 downto 0); signal jump_case_sel : std_logic_vector (1 downto 0); signal ctrl_i_PFC_JUMP : std_logic; signal ctrl_c2_PFC_RET : std_logic; signal ctrl_i_PFC_DELAY_SLOT : std_logic_vector (1 downto 0); type StateType is (s0,s1,s3,s4,s5,s6,s7,s8,s9,s10,s13); signal next_state : StateType; signal state : StateType; begin ctrl_i_PFC_DELAY_SLOT <= ctrl_i(4 downto 3); ctrl_i_PFC_JUMP <= ctrl_i(2); ctrl_c2_PFC_RET <= ctrl_c2(1); -- register generation logic process (clk_i) begin if clk_i'event and clk_i = '1' then if ( reset_i = '0' ) then state <= s0 ; else ctrl_c1 <= ctrl_i ; ctrl_c2 <= ctrl_c1 ; ctrl_c3 <= ctrl_c2 ; state <= next_state ; end if; end if; end process; -- next state logic s0_state_sel <= ctrl_i_PFC_JUMP & ctrl_i_PFC_DELAY_SLOT; process (s0_state_sel, state, ctrl_i) begin next_state <= s0 ; case state is when s0 => case s0_state_sel is when "100" => next_state <= s4; -- What is the next state? when "101" => next_state <= s5; -- What is the next state? when "110" => next_state <= s3; -- What is the next state? when "111" => next_state <= s1; when others => next_state <= s0; end case; when s1 => next_state <= s7 ; when s3 => next_state <= s6 ; when s4 => next_state <= s8 ; when s5 => next_state <= s8 ; when s6 => next_state <= s10 ; when s7 => next_state <= s9 ; when s8 => next_state <= s10 ; when s9 => if (ctrl_c2_PFC_RET = '1') then next_state <= s13; else next_state <= s0 ; -- What is the next state? end if; when s10 => if (ctrl_c2_PFC_RET = '1') then next_state <= s13; else next_state <= s0 ; -- What is the next state? end if; when s13 => next_state <= s0 ; when others => next_state <= s0; end case; end process; jump_case_sel <= ctrl_c2_PFC_RET & jump_decision_i; process (state, jump_case_sel, s0_state_sel) begin pfc_pc_add_opa_sel_o <= '0'; --Default value pfc_pc_sel_o<= "001"; --Default value pfc_inst_nop_o<='0'; --Default value pfc_lc_loopn_sel_o<='0'; --Default value case state is when s0 => if s0_state_sel = "100" then pfc_pc_sel_o<= "000"; end if; when s1 => -- Empty when s3 => -- Empty when s4 => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='1'; when s5 => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='0'; when s6 => case jump_case_sel is when "10" | "11" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='0'; when "01" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "011"; pfc_inst_nop_o<='0'; when "00" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='0'; when others => --Empty end case; when s7 => case jump_case_sel is when "10" | "11" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='0'; when "01" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "011"; pfc_inst_nop_o<='0'; when "00" => -- Empty when others => --Empty end case; when s8 => case jump_case_sel is when "10" | "11"=> pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='1'; when "01" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "011"; pfc_inst_nop_o<='1'; when "00" => pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "000"; pfc_inst_nop_o<='1'; when others => --Empty end case; when s9 => if ctrl_c3(1) = '1' then pfc_pc_sel_o<= "110"; else pfc_pc_sel_o<= "001"; end if; when s10 => if ctrl_c3(1) = '1' then pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "110"; pfc_inst_nop_o<='1'; else pfc_pc_add_opa_sel_o <= '0'; pfc_pc_sel_o<= "001"; pfc_inst_nop_o<='1'; --nop for the jum calls end if; when s13 => pfc_pc_sel_o<= "001"; pfc_inst_nop_o<='1'; when others => end case; end process; -- case: default end pc_fsm_rtl;

gpl-2.0

07585076911592881a8731c6aa955760

0.451565

3.057722

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_scatter.vhd

1

69,756

------------------------------------------------------------------------------- -- axi_datamover_s2mm_scatter.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_scatter.vhd -- -- Description: -- This file implements the S2MM Scatter support module. Scatter requires -- the input Stream to be stopped and disected at command boundaries. The -- Scatter module splits the input stream data at the command boundaries -- and force feeds the S2MM DRE with data and source alignment. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_s2mm_scatter.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 6/20/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added 512 and 1024 data width support -- ^^^^^^ -- -- DET 6/29/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Incorporated the Indeterminate BTT mode overflow absorption -- changes needed by AXI VDMA. -- ^^^^^^ -- -- DET 7/18/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- -- Per CR617164 -- - Added TSTRB fifo empty qualifier to the overflow absorption logic -- in the IBTT mode case. Also added additional qualification to the -- sig_gated_fifo_freeze_out signal in the IBTT mode IfGen. -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_strb_gen2; use axi_datamover_v5_1.axi_datamover_mssai_skid_buf; use axi_datamover_v5_1.axi_datamover_fifo; use axi_datamover_v5_1.axi_datamover_slice; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_scatter is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates if the IBTT Indeterminate BTT is enabled -- (external to this module) C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the S2MM DRE alignment control ports C_BTT_USED : Integer range 8 to 23 := 16; -- Sets the width of the BTT input port C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the input and output data streams C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_FAMILY : String := "virtex7" -- Specifies the target FPGA device family ); port ( -- Clock and Reset inputs -------------------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ---------------------------------------------------------------------------- -- DRE Realign Controller I/O ---------------------------------------------- -- scatter2drc_cmd_ready : Out std_logic; -- -- Indicates the Scatter Engine is ready to accept a new command -- -- drc2scatter_push_cmd : In std_logic; -- -- Indicates a new command is being read from the command que -- -- drc2scatter_btt : In std_logic_vector(C_BTT_USED-1 downto 0); -- -- Indicates the new command's BTT value -- -- drc2scatter_eof : In std_logic; -- -- Indicates that the input command is also the last of a packet -- -- This input is ignored when C_ENABLE_INDET_BTT = 1 -- ---------------------------------------------------------------------------- -- DRE Source Alignment --------------------------------------------------------- -- scatter2drc_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- Indicates the next source alignment to the DRE control -- -------------------------------------------------------------------------------- -- AXI Slave Stream In ---------------------------------------------------------- -- s2mm_strm_tready : Out Std_logic; -- -- AXI Stream READY input -- -- s2mm_strm_tvalid : In std_logic; -- -- AXI Stream VALID Output -- -- s2mm_strm_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- AXI Stream data output -- -- s2mm_strm_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- AXI Stream STRB output -- -- s2mm_strm_tlast : In std_logic; -- -- AXI Stream LAST output -- -------------------------------------------------------------------------------- -- Stream Out to S2MM DRE ------------------------------------------------------- -- drc2scatter_tready : In Std_logic; -- -- S2MM DRE Stream READY input -- -- scatter2drc_tvalid : Out std_logic; -- -- S2MM DRE VALID Output -- -- scatter2drc_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- S2MM DRE data output -- -- scatter2drc_tstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- S2MM DRE STRB output -- -- scatter2drc_tlast : Out std_logic; -- -- S2MM DRE LAST output -- -- scatter2drc_flush : Out std_logic; -- -- S2MM DRE LAST output -- -- scatter2drc_eop : Out std_logic; -- -- S2MM DRE End of Packet marker -- -------------------------------------------------------------------------------- -- Premature TLAST assertion error flag --------------------------------------- -- scatter2drc_tlast_error : Out std_logic -- -- When asserted, this indicates the scatter Engine detected -- -- a Early/Late TLAST assertion on the incoming data stream -- -- relative to the commands given to the DataMover Cmd FIFO. -- ------------------------------------------------------------------------------- ); end entity axi_datamover_s2mm_scatter; architecture implementation of axi_datamover_s2mm_scatter is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declaration ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_index -- -- Function Description: -- This function calculates the bus bit index corresponding -- to the MSB of the Slice lane index input and the Slice width. -- ------------------------------------------------------------------- function get_start_index (lane_index : integer; lane_width : integer) return integer is Variable bit_index_start : Integer := 0; begin bit_index_start := lane_index*lane_width; return(bit_index_start); end function get_start_index; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_index -- -- Function Description: -- This function calculates the bus bit index corresponding -- to the LSB of the Slice lane index input and the Slice width. -- ------------------------------------------------------------------- function get_end_index (lane_index : integer; lane_width : integer) return integer is Variable bit_index_end : Integer := 0; begin bit_index_end := (lane_index*lane_width) + (lane_width-1); return(bit_index_end); end function get_end_index; ------------------------------------------------------------------- -- Function -- -- Function Name: func_num_offset_bits -- -- Function Description: -- This function calculates the number of bits needed for specifying -- a byte lane offset for the input transfer data width. -- ------------------------------------------------------------------- function func_num_offset_bits (stream_dwidth_value : integer) return integer is Variable num_offset_bits_needed : Integer range 1 to 7 := 1; begin case stream_dwidth_value is when 8 => -- 1 byte lanes num_offset_bits_needed := 1; when 16 => -- 2 byte lanes num_offset_bits_needed := 1; when 32 => -- 4 byte lanes num_offset_bits_needed := 2; when 64 => -- 8 byte lanes num_offset_bits_needed := 3; when 128 => -- 16 byte lanes num_offset_bits_needed := 4; when 256 => -- 32 byte lanes num_offset_bits_needed := 5; when 512 => -- 64 byte lanes num_offset_bits_needed := 6; when others => -- 1024 bits with 128 byte lanes num_offset_bits_needed := 7; end case; Return (num_offset_bits_needed); end function func_num_offset_bits; function func_fifo_prim (stream_dwidth_value : integer) return integer is Variable prim_needed : Integer range 0 to 2 := 1; begin case stream_dwidth_value is when 8 => -- 1 byte lanes prim_needed := 2; when 16 => -- 2 byte lanes prim_needed := 2; when 32 => -- 4 byte lanes prim_needed := 2; when 64 => -- 8 byte lanes prim_needed := 2; when 128 => -- 16 byte lanes prim_needed := 0; when others => -- 256 bits and above prim_needed := 0; end case; Return (prim_needed); end function func_fifo_prim; -- Constant Declarations ------------------------------------------------- Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '0'; Constant BYTE_WIDTH : integer := 8; -- bits Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH; Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES; Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1; Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1; Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0'); Constant CMD_BTT_WIDTH : Integer := C_BTT_USED; Constant BTT_OF_ZERO : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); Constant MAX_BTT_INCR : integer := C_STREAM_DWIDTH/8; Constant NUM_OFFSET_BITS : integer := func_num_offset_bits(C_STREAM_DWIDTH); -- Minimum Number of bits needed to represent the byte lane position within the Stream Data Constant NUM_INCR_BITS : integer := NUM_OFFSET_BITS+1; -- Minimum Number of bits needed to represent the maximum per dbeat increment value Constant OFFSET_ONE : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(1 , NUM_OFFSET_BITS); Constant OFFSET_MAX : unsigned(NUM_OFFSET_BITS-1 downto 0) := TO_UNSIGNED(STRM_STRB_WIDTH - 1 , NUM_OFFSET_BITS); Constant INCR_MAX : unsigned(NUM_INCR_BITS-1 downto 0) := TO_UNSIGNED(MAX_BTT_INCR , NUM_INCR_BITS); Constant MSSAI_INDEX_WIDTH : integer := NUM_OFFSET_BITS; Constant TSTRB_FIFO_DEPTH : integer := 16; Constant TSTRB_FIFO_DWIDTH : integer := 1 + -- TLAST Bit 1 + -- EOF Bit 1 + -- Freeze Bit MSSAI_INDEX_WIDTH + -- MSSAI Value STRM_STRB_WIDTH*C_ENABLE_S2MM_TKEEP ; -- Strobe Value Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM : integer := func_fifo_prim(C_STREAM_DWIDTH); Constant FIFO_TLAST_INDEX : integer := TSTRB_FIFO_DWIDTH-1; Constant FIFO_EOF_INDEX : integer := FIFO_TLAST_INDEX-1; Constant FIFO_FREEZE_INDEX : integer := FIFO_EOF_INDEX-1; Constant FIFO_MSSAI_MS_INDEX : integer := FIFO_FREEZE_INDEX-1; Constant FIFO_MSSAI_LS_INDEX : integer := FIFO_MSSAI_MS_INDEX - (MSSAI_INDEX_WIDTH-1); Constant FIFO_TSTRB_MS_INDEX : integer := FIFO_MSSAI_LS_INDEX-1; Constant FIFO_TSTRB_LS_INDEX : integer := 0; -- Types ------------------------------------------------------------------ type byte_lane_type is array(STRM_NUM_BYTE_LANES-1 downto 0) of std_logic_vector(SLICE_WIDTH-1 downto 0); -- Signal Declarations --------------------------------------------------- signal sig_good_strm_dbeat : std_logic := '0'; signal sig_strm_tready : std_logic := '0'; signal sig_strm_tvalid : std_logic := '0'; signal sig_strm_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_strm_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0'); signal sig_strm_tlast : std_logic := '0'; signal sig_drc2scatter_tready : std_logic := '0'; signal sig_scatter2drc_tvalid : std_logic := '0'; signal sig_scatter2drc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_scatter2drc_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0'); signal sig_scatter2drc_tlast : std_logic := '0'; signal sig_scatter2drc_flush : std_logic := '0'; signal sig_valid_dre_output_dbeat : std_logic := '0'; signal sig_ld_cmd : std_logic := '0'; signal sig_cmd_full : std_logic := '0'; signal sig_cmd_empty : std_logic := '0'; signal sig_drc2scatter_push_cmd : std_logic := '0'; signal sig_drc2scatter_btt : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_drc2scatter_eof : std_logic := '0'; signal sig_btt_offset_slice : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_curr_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_next_strt_offset : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_next_dre_src_align : std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_dbeat_offset : std_logic_vector(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_cmd_sof : std_logic := '0'; signal sig_curr_eof_reg : std_logic := '0'; signal sig_btt_cntr : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_cntr_dup : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_ld_btt_cntr : std_logic := '0'; signal sig_decr_btt_cntr : std_logic := '0'; signal sig_btt_cntr_decr_value : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_stb_gen_slice : std_logic_vector(NUM_INCR_BITS-1 downto 0) := (others => '0'); signal sig_btt_eq_0 : std_logic := '0'; signal sig_btt_lteq_max_first_incr : std_logic := '0'; signal sig_btt_gteq_max_incr : std_logic := '0'; signal sig_max_first_increment : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_cntr_prv : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_eq_0_pre_reg : std_logic := '0'; signal sig_set_tlast_error : std_logic := '0'; signal sig_tlast_error_over : std_logic := '0'; signal sig_tlast_error_under : std_logic := '0'; signal sig_tlast_error_exact : std_logic := '0'; signal sig_tlast_error_reg : std_logic := '0'; signal sig_stbgen_tstrb : std_logic_vector(STRM_NUM_BYTE_LANES-1 downto 0) := (others => '0'); signal sig_tlast_error_out : std_logic := '0'; signal sig_freeze_it : std_logic := '0'; signal sig_tstrb_fifo_data_in : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0); signal sig_tstrb_fifo_data_out : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0); signal slice_insert_data : std_logic_vector(TSTRB_FIFO_DWIDTH-1 downto 0); signal slice_insert_ready : std_logic := '0'; signal slice_insert_valid : std_logic := '0'; signal sig_tstrb_fifo_rdy : std_logic := '0'; signal sig_tstrb_fifo_valid : std_logic := '0'; signal sig_valid_fifo_ld : std_logic := '0'; signal sig_fifo_tlast_out : std_logic := '0'; signal sig_fifo_eof_out : std_logic := '0'; signal sig_fifo_freeze_out : std_logic := '0'; signal sig_fifo_tstrb_out : std_logic_vector(STRM_STRB_WIDTH-1 downto 0); signal sig_tstrb_valid : std_logic := '0'; signal sig_get_tstrb : std_logic := '0'; signal sig_tstrb_fifo_empty : std_logic := '0'; signal sig_clr_fifo_ld_regs : std_logic := '0'; signal ld_btt_cntr_reg1 : std_logic := '0'; signal ld_btt_cntr_reg2 : std_logic := '0'; signal ld_btt_cntr_reg3 : std_logic := '0'; signal sig_btt_eq_0_reg : std_logic := '0'; signal sig_tlast_ld_beat : std_logic := '0'; signal sig_eof_ld_dbeat : std_logic := '0'; signal sig_strb_error : std_logic := '0'; signal sig_mssa_index : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_tstrb_fifo_mssai_in : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0); signal sig_tstrb_fifo_mssai_out : std_logic_vector(MSSAI_INDEX_WIDTH-1 downto 0); signal sig_fifo_mssai : unsigned(NUM_OFFSET_BITS-1 downto 0) := (others => '0'); signal sig_clr_tstrb_fifo : std_logic := '0'; signal sig_eop_sent : std_logic := '0'; signal sig_eop_sent_reg : std_logic := '0'; signal sig_scatter2drc_eop : std_logic := '0'; signal sig_set_packet_done : std_logic := '0'; signal sig_tlast_sent : std_logic := '0'; signal sig_gated_fifo_freeze_out : std_logic := '0'; signal sig_cmd_side_ready : std_logic := '0'; signal sig_eop_halt_xfer : std_logic := '0'; signal sig_err_underflow_reg : std_logic := '0'; signal sig_assert_valid_out : std_logic := '0'; -- Attribute KEEP : string; -- declaration -- Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration -- Attribute KEEP of sig_btt_cntr_dup : signal is "TRUE"; -- definition -- Attribute EQUIVALENT_REGISTER_REMOVAL of sig_btt_cntr_dup : signal is "no"; begin --(architecture implementation) -- Output stream assignments (to DRE) ----------------- sig_drc2scatter_tready <= drc2scatter_tready ; scatter2drc_tvalid <= sig_scatter2drc_tvalid ; scatter2drc_tdata <= sig_scatter2drc_tdata ; scatter2drc_tstrb <= sig_scatter2drc_tstrb ; scatter2drc_tlast <= sig_scatter2drc_tlast ; scatter2drc_flush <= sig_scatter2drc_flush ; scatter2drc_eop <= sig_scatter2drc_eop ; -- DRC Control ---------------------------------------- scatter2drc_cmd_ready <= sig_cmd_empty; sig_drc2scatter_push_cmd <= drc2scatter_push_cmd ; sig_drc2scatter_btt <= drc2scatter_btt ; sig_drc2scatter_eof <= drc2scatter_eof ; -- Next source alignment control to the S2Mm DRE ------ scatter2drc_src_align <= sig_next_dre_src_align; -- TLAST error flag output ---------------------------- scatter2drc_tlast_error <= sig_tlast_error_out; -- Data to DRE output --------------------------------- sig_scatter2drc_tdata <= sig_strm_tdata ; sig_scatter2drc_tvalid <= sig_assert_valid_out and -- Asserting the valid output sig_cmd_side_ready; -- and the tstrb fifo has an entry pending -- Create flag indicating a qualified output stream data beat to the DRE sig_valid_dre_output_dbeat <= sig_drc2scatter_tready and sig_scatter2drc_tvalid; -- Databeat DRE FLUSH output -------------------------- sig_scatter2drc_flush <= '0'; sig_ld_cmd <= sig_drc2scatter_push_cmd and not(sig_cmd_full); sig_next_dre_src_align <= STD_LOGIC_VECTOR(RESIZE(sig_next_strt_offset, C_DRE_ALIGN_WIDTH)); sig_good_strm_dbeat <= sig_strm_tready and sig_assert_valid_out ; -- Set the valid out flag sig_assert_valid_out <= (sig_strm_tvalid or -- there is valid data in the Skid buffer output register sig_err_underflow_reg); -- or an underflow error has been detected and needs to flush --- Input Stream Skid Buffer with Special Functions ------------------------------ ------------------------------------------------------------ -- Instance: I_MSSAI_SKID_BUF -- -- Description: -- Instance for the MSSAI Skid Buffer needed for Fmax -- closure when the Scatter Module is included in the DataMover -- S2MM. -- ------------------------------------------------------------ I_MSSAI_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_mssai_skid_buf generic map ( C_WDATA_WIDTH => C_STREAM_DWIDTH , C_INDEX_WIDTH => MSSAI_INDEX_WIDTH ) port map ( -- System Ports aclk => primary_aclk , arst => mmap_reset , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_tvalid , s_ready => s2mm_strm_tready , s_data => s2mm_strm_tdata , s_strb => s2mm_strm_tstrb , s_last => s2mm_strm_tlast , -- Master Side (Stream Data Output m_valid => sig_strm_tvalid , m_ready => sig_strm_tready , m_data => sig_strm_tdata , m_strb => sig_strm_tstrb , m_last => sig_strm_tlast , m_mssa_index => sig_mssa_index , m_strb_error => sig_strb_error ); ------------------------------------------------------------- -- packet Done Logic ------------------------------------------------------------- sig_set_packet_done <= sig_eop_sent_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_FLAG_REG -- -- Process Description: -- Implement the Scatter transfer command full/empty tracking -- flops -- ------------------------------------------------------------- IMP_CMD_FLAG_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_tlast_sent = '1') then sig_cmd_full <= '0'; sig_cmd_empty <= '1'; elsif (sig_ld_cmd = '1') then sig_cmd_full <= '1'; sig_cmd_empty <= '0'; else null; -- hold current state end if; end if; end process IMP_CMD_FLAG_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CURR_OFFSET_REG -- -- Process Description: -- Implements the register holding the current starting -- byte position offset of the first byte of the current -- command. This implementation assumes that only the first -- databeat can be unaligned from Byte position 0. -- ------------------------------------------------------------- IMP_CURR_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_set_packet_done = '1' or sig_valid_fifo_ld = '1') then sig_curr_strt_offset <= (others => '0'); elsif (sig_ld_cmd = '1') then sig_curr_strt_offset <= sig_next_strt_offset; else null; -- Hold current state end if; end if; end process IMP_CURR_OFFSET_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_NEXT_OFFSET_REG -- -- Process Description: -- Implements the register holding the predicted byte position -- offset of the first byte of the next command. If the current -- command has EOF set, then the next command's first data input -- byte offset must be at byte lane 0 in the input stream. -- ------------------------------------------------------------- IMP_NEXT_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_set_packet_done = '1' or STRM_NUM_BYTE_LANES = 1) then sig_next_strt_offset <= (others => '0'); elsif (sig_ld_cmd = '1') then sig_next_strt_offset <= sig_next_strt_offset + sig_btt_offset_slice; else null; -- Hold current state end if; end if; end process IMP_NEXT_OFFSET_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIFO_MSSAI_REG -- -- Process Description: -- Implements the register holding the predicted byte position -- offset of the last valid byte defined by the current command. -- ------------------------------------------------------------- IMP_FIFO_MSSAI_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_set_packet_done = '1' or STRM_NUM_BYTE_LANES = 1 ) then sig_fifo_mssai <= (others => '0'); elsif (ld_btt_cntr_reg1 = '1' and ld_btt_cntr_reg2 = '0') then sig_fifo_mssai <= sig_next_strt_offset - OFFSET_ONE; else null; -- Hold current state end if; end if; end process IMP_FIFO_MSSAI_REG; -- Strobe Generation Logic ------------------------------------------------ sig_curr_dbeat_offset <= STD_LOGIC_VECTOR(sig_curr_strt_offset); ------------------------------------------------------------ -- Instance: I_SCATTER_STROBE_GEN -- -- Description: -- Strobe generator instance. Generates strobe bits for -- a designated starting byte lane and the number of bytes -- to be transfered (for that data beat). -- ------------------------------------------------------------ I_SCATTER_STROBE_GEN : entity axi_datamover_v5_1.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 0 , -- 0 = Offset/Length mode C_STRB_WIDTH => STRM_NUM_BYTE_LANES , C_OFFSET_WIDTH => NUM_OFFSET_BITS , C_NUM_BYTES_WIDTH => NUM_INCR_BITS ) port map ( start_addr_offset => sig_curr_dbeat_offset , end_addr_offset => sig_curr_dbeat_offset , -- not used in op mode 0 num_valid_bytes => sig_btt_stb_gen_slice , -- not used in op mode 1 strb_out => sig_stbgen_tstrb ); -- BTT Counter stuff ------------------------------------------------------ sig_btt_stb_gen_slice <= STD_LOGIC_VECTOR(INCR_MAX) when (sig_btt_gteq_max_incr = '1') else '0' & STD_LOGIC_VECTOR(sig_btt_cntr(NUM_OFFSET_BITS-1 downto 0)); sig_btt_offset_slice <= UNSIGNED(sig_drc2scatter_btt(NUM_OFFSET_BITS-1 downto 0)); sig_btt_lteq_max_first_incr <= '1' when (sig_btt_cntr <= RESIZE(sig_max_first_increment, CMD_BTT_WIDTH)) -- more timing improv Else '0'; -- more timing improv -- more timing improv ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MAX_FIRST_INCR_REG -- -- Process Description: -- Implements the Max first increment register value. -- ------------------------------------------------------------- IMP_MAX_FIRST_INCR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_max_first_increment <= (others => '0'); Elsif (sig_ld_cmd = '1') Then sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS) - RESIZE(sig_next_strt_offset,NUM_INCR_BITS), CMD_BTT_WIDTH); Elsif (sig_valid_fifo_ld = '1') Then sig_max_first_increment <= RESIZE(TO_UNSIGNED(MAX_BTT_INCR,NUM_INCR_BITS), CMD_BTT_WIDTH); else null; -- hold current value end if; end if; end process IMP_MAX_FIRST_INCR_REG; sig_btt_cntr_decr_value <= sig_btt_cntr When (sig_btt_lteq_max_first_incr = '1') Else sig_max_first_increment; sig_ld_btt_cntr <= sig_ld_cmd ; sig_decr_btt_cntr <= not(sig_btt_eq_0) and sig_valid_fifo_ld; -- New intermediate value for reduced Timing path sig_btt_cntr_prv <= UNSIGNED(sig_drc2scatter_btt) when (sig_ld_btt_cntr = '1') -- Else sig_btt_cntr_dup-sig_btt_cntr_decr_value; Else sig_btt_cntr-sig_btt_cntr_decr_value; sig_btt_eq_0_pre_reg <= '1' when (sig_btt_cntr_prv = BTT_OF_ZERO) Else '0'; -- sig_btt_eq_0 <= '1' -- when (sig_btt_cntr = BTT_OF_ZERO) -- Else '0'; sig_btt_gteq_max_incr <= '1' when (sig_btt_cntr >= TO_UNSIGNED(MAX_BTT_INCR, CMD_BTT_WIDTH)) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_CNTR_REG -- -- Process Description: -- Implements the registered portion of the BTT Counter. The -- BTT Counter has been recoded this way to minimize long -- timing paths in the btt -> strobgen-> EOP Demux path. -- ------------------------------------------------------------- IMP_BTT_CNTR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_eop_sent = '1') then sig_btt_cntr <= (others => '0'); -- sig_btt_cntr_dup <= (others => '0'); sig_btt_eq_0 <= '1'; elsif (sig_ld_btt_cntr = '1' or sig_decr_btt_cntr = '1') then sig_btt_cntr <= sig_btt_cntr_prv; -- sig_btt_cntr_dup <= sig_btt_cntr_prv; sig_btt_eq_0 <= sig_btt_eq_0_pre_reg; else Null; -- Hold current state end if; end if; end process IMP_BTT_CNTR_REG; -- IMP_BTT_CNTR_REG : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- if (mmap_reset = '1' or -- sig_eop_sent = '1') then -- sig_btt_cntr <= (others => '0'); ---- sig_btt_eq_0 <= '1'; -- elsif (sig_ld_btt_cntr = '1') then -- sig_btt_cntr <= UNSIGNED(sig_drc2scatter_btt); --sig_btt_cntr_prv; ---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg; -- elsif (sig_decr_btt_cntr = '1') then -- sig_btt_cntr <= sig_btt_cntr-sig_btt_cntr_decr_value; --sig_btt_cntr_prv; ---- sig_btt_eq_0 <= sig_btt_eq_0_pre_reg; -- else -- Null; -- Hold current state -- end if; -- end if; -- end process IMP_BTT_CNTR_REG; ------------------------------------------------------------------------ -- DRE TVALID Gating logic ------------------------------------------------------------------------ sig_cmd_side_ready <= not(sig_tstrb_fifo_empty) and not(sig_eop_halt_xfer); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOP_HALT_FLOP -- -- Process Description: -- Implements a flag that is set when an end of packet is sent -- to the DRE and cleared after the TSTRB FIFO has been reset. -- This flag inhibits the TVALID sent to the DRE. ------------------------------------------------------------- IMP_EOP_HALT_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_eop_sent = '1') then sig_eop_halt_xfer <= '1'; Elsif (sig_valid_fifo_ld = '1') Then sig_eop_halt_xfer <= '0'; else null; -- hold current state end if; end if; end process IMP_EOP_HALT_FLOP; ------------------------------------------------------------------------ -- TSTRB FIFO Logic ------------------------------------------------------------------------ sig_tlast_ld_beat <= sig_btt_lteq_max_first_incr; sig_eof_ld_dbeat <= sig_curr_eof_reg and sig_tlast_ld_beat; -- Set the MSSAI offset value to the maximum for non-tlast dbeat -- case, otherwise use the calculated value for the TLSAT case. sig_tstrb_fifo_mssai_in <= STD_LOGIC_VECTOR(sig_fifo_mssai) when (sig_tlast_ld_beat = '1') else STD_LOGIC_VECTOR(OFFSET_MAX); GEN_S2MM_TKEEP_ENABLE3 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Merge the various pieces to go through the TSTRB FIFO into a single vector sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet sig_eof_ld_dbeat & -- the end of the whole packet sig_freeze_it & -- A sub-packet boundary sig_tstrb_fifo_mssai_in & -- the index of EOF byte position sig_stbgen_tstrb; -- The calculated strobes end generate GEN_S2MM_TKEEP_ENABLE3; GEN_S2MM_TKEEP_DISABLE3 : if C_ENABLE_S2MM_TKEEP = 0 generate begin -- Merge the various pieces to go through the TSTRB FIFO into a single vector sig_tstrb_fifo_data_in <= sig_tlast_ld_beat & -- the last beat of this sub-packet sig_eof_ld_dbeat & -- the end of the whole packet sig_freeze_it & -- A sub-packet boundary sig_tstrb_fifo_mssai_in; --& -- the index of EOF byte position --sig_stbgen_tstrb; -- The calculated strobes end generate GEN_S2MM_TKEEP_DISABLE3; -- FIFO Load control sig_valid_fifo_ld <= sig_tstrb_fifo_valid and sig_tstrb_fifo_rdy; GEN_S2MM_TKEEP_ENABLE4 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- Rip the various pieces from the FIFO output sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ; sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ; sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX); sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX); sig_fifo_tstrb_out <= sig_tstrb_fifo_data_out(FIFO_TSTRB_MS_INDEX downto FIFO_TSTRB_LS_INDEX); end generate GEN_S2MM_TKEEP_ENABLE4; GEN_S2MM_TKEEP_DISABLE4 : if C_ENABLE_S2MM_TKEEP = 0 generate begin -- Rip the various pieces from the FIFO output sig_fifo_tlast_out <= sig_tstrb_fifo_data_out(FIFO_TLAST_INDEX) ; sig_fifo_eof_out <= sig_tstrb_fifo_data_out(FIFO_EOF_INDEX) ; sig_fifo_freeze_out <= sig_tstrb_fifo_data_out(FIFO_FREEZE_INDEX); sig_tstrb_fifo_mssai_out <= sig_tstrb_fifo_data_out(FIFO_MSSAI_MS_INDEX downto FIFO_MSSAI_LS_INDEX); sig_fifo_tstrb_out <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE4; -- FIFO Read Control sig_get_tstrb <= sig_valid_dre_output_dbeat ; sig_tstrb_fifo_valid <= ld_btt_cntr_reg2 or (ld_btt_cntr_reg3 and not(sig_btt_eq_0)); sig_clr_fifo_ld_regs <= (sig_tlast_ld_beat and sig_valid_fifo_ld) or sig_eop_sent; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIFO_LD_1 -- -- Process Description: -- Implements the fifo loading control flop stage 1 -- ------------------------------------------------------------- IMP_FIFO_LD_1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_clr_fifo_ld_regs = '1') then ld_btt_cntr_reg1 <= '0'; Elsif (sig_ld_btt_cntr = '1') Then ld_btt_cntr_reg1 <= '1'; else null; -- hold current state end if; end if; end process IMP_FIFO_LD_1; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIFO_LD_2 -- -- Process Description: -- Implements special fifo loading control flops -- ------------------------------------------------------------- IMP_FIFO_LD_2 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_clr_fifo_ld_regs = '1') then ld_btt_cntr_reg2 <= '0'; ld_btt_cntr_reg3 <= '0'; Elsif (sig_tstrb_fifo_rdy = '1') Then ld_btt_cntr_reg2 <= ld_btt_cntr_reg1; ld_btt_cntr_reg3 <= ld_btt_cntr_reg2 or ld_btt_cntr_reg3; -- once set, keep it set until cleared else null; -- Hold current state end if; end if; end process IMP_FIFO_LD_2; HIGHER_DATAWIDTH : if TSTRB_FIFO_DWIDTH > 40 generate begin SLICE_INSERTION : entity axi_datamover_v5_1.axi_datamover_slice generic map ( C_DATA_WIDTH => TSTRB_FIFO_DWIDTH ) port map ( ACLK => primary_aclk, ARESET => mmap_reset, -- Slave side S_PAYLOAD_DATA => sig_tstrb_fifo_data_in, S_VALID => sig_tstrb_fifo_valid, S_READY => sig_tstrb_fifo_rdy, -- Master side M_PAYLOAD_DATA => slice_insert_data, M_VALID => slice_insert_valid, M_READY => slice_insert_ready ); ------------------------------------------------------------ -- Instance: I_TSTRB_FIFO -- -- Description: -- Instance for the TSTRB FIFO -- ------------------------------------------------------------ I_TSTRB_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => TSTRB_FIFO_DWIDTH , C_DEPTH => TSTRB_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => sig_clr_tstrb_fifo , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => slice_insert_valid, --sig_tstrb_fifo_valid , fifo_wr_tready => slice_insert_ready, --sig_tstrb_fifo_rdy , fifo_wr_tdata => slice_insert_data, --sig_tstrb_fifo_data_in, fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_tstrb_valid , fifo_rd_tready => sig_get_tstrb , fifo_rd_tdata => sig_tstrb_fifo_data_out , fifo_rd_empty => sig_tstrb_fifo_empty ); end generate HIGHER_DATAWIDTH; LOWER_DATAWIDTH : if TSTRB_FIFO_DWIDTH <= 40 generate begin ------------------------------------------------------------ -- Instance: I_TSTRB_FIFO -- -- Description: -- Instance for the TSTRB FIFO -- ------------------------------------------------------------ I_TSTRB_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => TSTRB_FIFO_DWIDTH , C_DEPTH => TSTRB_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => sig_clr_tstrb_fifo , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_tstrb_fifo_valid , fifo_wr_tready => sig_tstrb_fifo_rdy , fifo_wr_tdata => sig_tstrb_fifo_data_in, fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_tstrb_valid , fifo_rd_tready => sig_get_tstrb , fifo_rd_tdata => sig_tstrb_fifo_data_out , fifo_rd_empty => sig_tstrb_fifo_empty ); end generate LOWER_DATAWIDTH; ------------------------------------------------------------ -- TSTRB FIFO Clear Logic ------------------------------------------------------------ -- Special TSTRB FIFO Clear Logic to clean out any residue -- once EOP has been sent out to DRE. This is primarily -- needed in Indeterminate BTT mode but is also included in -- the non-Indeterminate BTT mode for a more robust design. sig_clr_tstrb_fifo <= mmap_reset or sig_set_packet_done; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOP_SENT_REG -- -- Process Description: -- Register the EOP being sent out to the DRE stage. This -- is used to clear the TSTRB FIFO of any residue. -- ------------------------------------------------------------- IMP_EOP_SENT_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_eop_sent_reg = '1') then sig_eop_sent_reg <= '0'; else sig_eop_sent_reg <= sig_eop_sent; end if; end if; end process IMP_EOP_SENT_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOF_REG -- -- Process Description: -- Implement a sample and hold flop for the command EOF -- The Commanded EOF is used when C_ENABLE_INDET_BTT = 0. ------------------------------------------------------------- IMP_EOF_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_set_packet_done = '1') then sig_curr_eof_reg <= '0'; elsif (sig_ld_cmd = '1') then sig_curr_eof_reg <= sig_drc2scatter_eof; else null; -- hold current state end if; end if; end process IMP_EOF_REG; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Implements the Scatter Freeze Register Controls plus -- other logic needed when Indeterminate BTT Mode is not enabled. -- -- -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate signal lsig_eop_matches_ms_strb : std_logic := '0'; begin sig_eop_sent <= sig_scatter2drc_eop and sig_valid_dre_output_dbeat; sig_tlast_sent <= sig_scatter2drc_tlast and sig_valid_dre_output_dbeat; sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set sig_valid_fifo_ld and -- tstrb fifo being loaded not(sig_curr_eof_reg); -- Current input cmd does not have eof set -- Assign the TREADY out to the Stream In sig_strm_tready <= '0' when (sig_gated_fifo_freeze_out = '1' or sig_cmd_side_ready = '0') Else sig_drc2scatter_tready; -- Without Indeterminate BTT, FIFO Freeze does not -- need to be gated. sig_gated_fifo_freeze_out <= sig_fifo_freeze_out; -- Strobe outputs are always generated from the input command -- with Indeterminate BTT omitted. Stream input Strobes are not -- sent to output. sig_scatter2drc_tstrb <= sig_fifo_tstrb_out; -- The EOF marker is generated from the input command -- with Indeterminate BTT omitted. Stream input TLAST is monitored -- but not sent to output to DRE. sig_scatter2drc_eop <= sig_fifo_eof_out and sig_scatter2drc_tvalid; -- TLast output marker always generated from the input command sig_scatter2drc_tlast <= sig_fifo_tlast_out and sig_scatter2drc_tvalid; --- TLAST Error Detection ------------------------------------------------- sig_tlast_error_out <= sig_set_tlast_error or sig_tlast_error_reg; -- Compare the Most significant Asserted TSTRB from the TSTRB FIFO -- with that from the Input Skid Buffer lsig_eop_matches_ms_strb <= '1' when (sig_tstrb_fifo_mssai_out = sig_mssa_index) Else '0'; -- Detect the case when the calculated end of packet -- marker preceeds the received end of packet marker -- and a freeze condition is not enabled sig_tlast_error_over <= '1' when (sig_valid_dre_output_dbeat = '1' and sig_fifo_freeze_out = '0' and sig_fifo_eof_out = '1' and sig_strm_tlast = '0') Else '0'; -- Detect the case when the received end of packet marker preceeds -- the calculated end of packet -- and a freeze condition is not enabled sig_tlast_error_under <= '1' when (sig_valid_dre_output_dbeat = '1' and sig_fifo_freeze_out = '0' and sig_fifo_eof_out = '0' and sig_strm_tlast = '1') Else '0'; -- Detect the case when the received end of packet marker occurs -- in the same beat as the calculated end of packet but the most -- significant received strobe that is asserted does not match -- the most significant calcualted strobe that is asserted. -- Also, a freeze condition is not enabled sig_tlast_error_exact <= '1' When (sig_valid_dre_output_dbeat = '1' and sig_fifo_freeze_out = '0' and sig_fifo_eof_out = '1' and sig_strm_tlast = '1' and lsig_eop_matches_ms_strb = '0') Else '0'; -- Combine all of the possible error conditions sig_set_tlast_error <= sig_tlast_error_over or sig_tlast_error_under or sig_tlast_error_exact; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERROR_REG -- -- Process Description: -- -- ------------------------------------------------------------- IMP_TLAST_ERROR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_tlast_error_reg <= '0'; elsif (sig_set_tlast_error = '1') then sig_tlast_error_reg <= '1'; else Null; -- Hold current State end if; end if; end process IMP_TLAST_ERROR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERROR_UNDER_REG -- -- Process Description: -- Sample and Hold flop for the case when an underrun is -- detected. This flag is used to force a a tvalid output. -- ------------------------------------------------------------- IMP_TLAST_ERROR_UNDER_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_err_underflow_reg <= '0'; elsif (sig_tlast_error_under = '1') then sig_err_underflow_reg <= '1'; else Null; -- Hold current State end if; end if; end process IMP_TLAST_ERROR_UNDER_REG; end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INDET_BTT -- -- If Generate Description: -- Implements the Scatter Freeze Register and Controls plus -- other logic needed to support the Indeterminate BTT Mode -- of Operation. -- -- ------------------------------------------------------------ GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate -- local signals -- signal lsig_valid_eop_dbeat : std_logic := '0'; signal lsig_strm_eop_asserted : std_logic := '0'; signal lsig_absorb2tlast : std_logic := '0'; signal lsig_set_absorb2tlast : std_logic := '0'; signal lsig_clr_absorb2tlast : std_logic := '0'; begin -- Detect an end of packet condition. This is an EOP sent to the DRE or -- an overflow data absorption condition sig_eop_sent <= (sig_scatter2drc_eop and sig_valid_dre_output_dbeat) or (lsig_set_absorb2tlast and not(lsig_absorb2tlast)); sig_tlast_sent <= (sig_scatter2drc_tlast and -- sig_valid_dre_output_dbeat and -- Normal Tlast Sent condition not(lsig_set_absorb2tlast)) or -- (lsig_absorb2tlast and lsig_clr_absorb2tlast); -- Overflow absorbion condition -- TStrb FIFO Input Stream Freeze control sig_freeze_it <= not(sig_stbgen_tstrb(STRM_NUM_BYTE_LANES-1)) and -- ms strobe not set -- not(sig_curr_eof_reg) and -- tstrb fifo being loaded sig_valid_fifo_ld ; -- Current input cmd has eof set -- Stream EOP assertion is caused when the stream input TLAST -- is asserted and the most significant strobe bit asserted in -- the input stream data beat is less than or equal to the most -- significant calculated asserted strobe bit for the data beat. lsig_strm_eop_asserted <= '1' when (sig_mssa_index <= sig_tstrb_fifo_mssai_out) and (sig_strm_tlast = '1' and sig_strm_tvalid = '1') else '0'; -- Must not freeze the Stream input skid buffer if an EOF -- condition exists on the Stream input (skid buf output) sig_gated_fifo_freeze_out <= sig_fifo_freeze_out and not(lsig_strm_eop_asserted) and sig_strm_tvalid; -- CR617164 -- Databeat DRE EOP output --------------------------- sig_scatter2drc_eop <= (--sig_fifo_eof_out or lsig_strm_eop_asserted) and sig_scatter2drc_tvalid; -- Databeat DRE Last output --------------------------- sig_scatter2drc_tlast <= (sig_fifo_tlast_out or lsig_strm_eop_asserted) and sig_scatter2drc_tvalid; -- Formulate the output TSTRB vector. It is an AND of the command -- generated TSTRB and the actual TSTRB received from the Stream input. sig_scatter2drc_tstrb <= sig_fifo_tstrb_out and sig_strm_tstrb; sig_tlast_error_over <= '0'; -- no tlast error in Indeterminate BTT sig_tlast_error_under <= '0'; -- no tlast error in Indeterminate BTT sig_tlast_error_exact <= '0'; -- no tlast error in Indeterminate BTT sig_set_tlast_error <= '0'; -- no tlast error in Indeterminate BTT sig_tlast_error_reg <= '0'; -- no tlast error in Indeterminate BTT sig_tlast_error_out <= '0'; -- no tlast error in Indeterminate BTT ------------------------------------------------ -- Data absorption to TLAST logic -- This is used for the Stream Input overflow case. In this case, the -- input stream data is absorbed (thrown away) until the TLAST databeat -- is received (also thrown away). However, data is only absorbed if -- the EOP bit from the TSTRB FIFO is encountered before the TLST from -- the Stream input. -- In addition, the scatter2drc_eop assertion is suppressed from the output -- to the DRE. -- Assign the TREADY out to the Stream In with Overflow data absorption -- case added. sig_strm_tready <= '0' when (lsig_absorb2tlast = '0' and (sig_gated_fifo_freeze_out = '1' or -- Normal case sig_cmd_side_ready = '0')) Else '1' When (lsig_absorb2tlast = '1') -- Absorb overflow case Else sig_drc2scatter_tready; -- Check for the condition for absorbing overflow data. The start of new input -- packet cannot reside in the same databeat as the end of the previous -- packet. Thus anytime an EOF is encountered from the TSTRB FIFO output, the -- entire databeat needs to be discarded after transfer to the DRE of the -- appropriate data. lsig_set_absorb2tlast <= '1' when (sig_fifo_eof_out = '1' and sig_tstrb_fifo_empty = '0' and -- CR617164 (sig_strm_tlast = '0' and sig_strm_tvalid = '1')) Else '1' When (sig_gated_fifo_freeze_out = '1' and sig_fifo_eof_out = '1' and sig_tstrb_fifo_empty = '0') -- CR617164 else '0'; lsig_clr_absorb2tlast <= '1' when lsig_absorb2tlast = '1' and (sig_strm_tlast = '1' and sig_strm_tvalid = '1') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ABSORB_FLOP -- -- Process Description: -- Implements the flag for indicating a overflow absorption -- case is active. -- ------------------------------------------------------------- IMP_ABSORB_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or lsig_clr_absorb2tlast = '1') then lsig_absorb2tlast <= '0'; elsif (lsig_set_absorb2tlast = '1') then lsig_absorb2tlast <= '1'; else null; -- Hold Current State end if; end if; end process IMP_ABSORB_FLOP; end generate GEN_INDET_BTT; end implementation;

bsd-2-clause

aeeaa636f85fc733a5a074c21b3d140b

0.436894

4.745629

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/conditional_expressions/rule_501_test_input.fixed_upper.vhd

1

400

architecture rtl of fifo is begin process begin var1 := '0' when rd_en = '1' ELSE '1'; var2 := '0' when rd_en = '1' ELSE '1'; wr_en_a <= force '0' when rd_en = '1' ELSE '1'; wr_en_b <= force '0' when rd_en = '1' ELSE '1'; end process; concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;

gpl-3.0

b7d3933e2e88188facae9010116e2d68

0.54

2.564103

false

wklimann/PCM3168

PCM3168/PCM3168_tb.vhd

1

2,352

-------------------------------------------------------------------------------- -- Engineer: Klimann Wendelin -- -- Create Date: 09:00:40 11/Okt/2013 -- Design Name: parallel_to_i2s -- Description: -- -- VHDL Test Bench for module: pcm3168 -- -- version: 00.01 -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY pcm3168_tb_vhd IS END pcm3168_tb_vhd; ARCHITECTURE behavior OF pcm3168_tb_vhd IS constant width : integer := 24; constant clk_divider : integer := 4; -- Component Declaration for the Unit Under Test (UUT) COMPONENT pcm3168 generic( width : integer := width; clk_divider : integer := clk_divider ); PORT( CLK : in std_logic; RESET : in std_logic; DIN_1 : in std_logic; DOUT_1 : out std_logic ); END COMPONENT; --Inputs SIGNAL CLK : std_logic := '0'; SIGNAL RESET : std_logic := '0'; SIGNAL DIN_1 : std_logic := '0'; --Outputs SIGNAL DOUT_1 : std_logic := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: pcm3168 PORT MAP( CLK => CLK, RESET => RESET, DOUT_1 => DOUT_1, DIN_1 => DIN_1 ); -- creates a reset signal at the start of the sequence p_reset : process begin RESET <= '0'; wait for 160 ns; RESET <= '1'; -- Reset finished wait; end process p_reset; -- generates the clock signal p_clk : process begin CLK <= '0'; wait for 10 ns; CLK <= '1'; wait for 10 ns; end process p_clk; -- provides the parallel input signal p_din : process variable i : POSITIVE :=1; variable first : POSITIVE :=2; begin if (first = 2) then first := 1; DIN_1 <= '0'; wait for 320 ns; end if; i := 1; while (i <= width) loop i := i + 1; DIN_1 <= '1'; wait for 80 ns; end loop; i := 1; while (i <= width) loop i := i + 1; DIN_1 <= '0'; wait for 80 ns; i := i + 1; DIN_1 <= '1'; wait for 80 ns; end loop; i := 1; while (i <= width) loop i := i + 2; DIN_1 <= '0'; wait for 160 ns; i := i + 2; DIN_1 <= '1'; wait for 160 ns; end loop; i := 1; while (i <= width) loop i := i + 1; DIN_1 <= '0'; wait for 80 ns; end loop; end process p_din; END;

gpl-2.0

e52b1f223b0edff2c1379b47bd1d0165

0.52466

2.854369

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/if_statement/rule_029_test_input.vhd

1

566

architecture RTL of FIFO is begin process begin if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; else if x = '1' then z <= '0'; elsif x = '0' then z <= '1'; else z <= 'Z'; end if; end if; -- Violations below if a = '1' THEN b <= '0'; elsif c = '1' THEN b <= '1'; else if x = '1' THEN z <= '0'; elsif x = '0' THEN z <= '1'; else z <= 'Z'; end if; end if; end process; end architecture RTL;

gpl-3.0

d23b068df86e27a43fb3a1dbe0c83344

0.379859

3.19774

false

rjarzmik/mips_processor

IF/Fetch_tb.vhd

1

4,914

------------------------------------------------------------------------------- -- Title : Testbench for design "Fetch" -- Project : ------------------------------------------------------------------------------- -- File : Fetch_tb.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-11 -- Last update: 2016-12-03 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-11 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity Fetch_tb is end entity Fetch_tb; ------------------------------------------------------------------------------- architecture rtl of Fetch_tb is -- component generics constant ADDR_WIDTH : integer := 16; constant DATA_WIDTH : integer := 16; constant MEMORY_LATENCY : integer := 3; -- component ports -- clock signal Clk : std_logic := '1'; -- reset signal Rst : std_logic := '1'; signal instruction : std_logic_vector(DATA_WIDTH - 1 downto 0); signal pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(0, ADDR_WIDTH)); signal next_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(4, ADDR_WIDTH)); signal next_next_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(4, ADDR_WIDTH)); signal stall_req : std_logic := '0'; signal stall_pc : std_logic := '0'; signal jump_pc : std_logic; signal jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0); -- L2 connections signal o_L2c_req : std_logic; signal o_L2c_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal i_L2c_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_L2c_valid : std_logic; -- Debug signals signal dbg_if_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); begin -- architecture rtl -- component instantiation dut : entity work.Fetch(rtl3) generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH) port map ( clk => Clk, rst => Rst, stall_req => '0', kill_req => '0', i_pc => pc, i_next_pc => next_pc, i_next_next_pc => next_next_pc, o_instruction => instruction, o_do_stall_pc => stall_pc, o_L2c_req => o_L2c_req, o_L2c_addr => o_L2c_addr, i_L2c_read_data => i_L2c_read_data, i_L2c_valid => i_L2c_valid, o_dbg_if_fetching_pc => dbg_if_pc); Simulated_Memory_1 : entity work.Simulated_Memory generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, MEMORY_LATENCY => MEMORY_LATENCY) port map ( clk => Clk, rst => Rst, i_memory_req => o_L2c_req, i_memory_we => '0', i_memory_addr => o_L2c_addr, i_memory_write_data => (others => 'X'), o_memory_read_data => i_L2c_read_data, o_memory_valid => i_L2c_valid); PC_Register_1 : entity work.PC_Register generic map ( ADDR_WIDTH => ADDR_WIDTH, STEP => 4) port map ( clk => Clk, rst => Rst, stall_pc => stall_pc, jump_pc => jump_pc, jump_target => jump_target, o_current_pc => pc, o_next_pc => next_pc, o_next_next_pc => next_next_pc); -- reset Rst <= '0' after 12 ps; -- clock generation Clk <= not Clk after 5 ps; -- waveform generation WaveGen_Proc : process variable nb_clks : integer := 0; begin -- insert signal assignments here wait until Clk = '1'; nb_clks := nb_clks + 1; if unsigned(pc) = to_unsigned(16 + 4, ADDR_WIDTH) then jump_pc <= '1'; jump_target <= std_logic_vector(to_unsigned(8, ADDR_WIDTH)); else jump_pc <= '0'; jump_target <= (others => 'X'); end if; end process WaveGen_Proc; end architecture rtl; ------------------------------------------------------------------------------- configuration Fetch_tb_test_cfg of Fetch_tb is for rtl end for; end Fetch_tb_test_cfg; -------------------------------------------------------------------------------

gpl-3.0

f6dfb479b01cdbca9cd8fc3d0c0be4e9

0.455026

3.84507

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover.vhd

1

74,527

------------------------------------------------------------------------------- -- axi_datamover.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover.vhd -- -- Description: -- Top level VHDL wrapper for the AXI DataMover -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover.vhd -- | -- |- axi_datamover_mm2s_omit_wrap.vhd -- |- axi_datamover_mm2s_full_wrap.vhd -- |- axi_datamover_mm2s_basic_wrap.vhd -- | -- |- axi_datamover_s2mm_omit_wrap.vhd -- |- axi_datamover_s2mm_full_wrap.vhd -- |- axi_datamover_s2mm_basic_wrap.vhd -- -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 6/2/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Updated Burst limit and min BTT used calculations to account for -- the inclusion of upsizer/downsizer logic in the datapath. -- ^^^^^^ -- -- DET 6/20/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added 512 and 1024 data width support -- ^^^^^^ -- -- DET 9/1/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Fixed Lint reported excesive line length for lines 404 and 530. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library proc_common_v4_0; use proc_common_v4_0.family_support; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap ; use axi_datamover_v5_1.axi_datamover_mm2s_full_wrap ; use axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap; use axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap ; use axi_datamover_v5_1.axi_datamover_s2mm_full_wrap ; use axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap; ------------------------------------------------------------------------------- entity axi_datamover is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 2; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Basic MM2S functionality C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0; -- Specifies the constant value to output on -- the ARID output port C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit MM2S Store and Forward -- 1 = Include MM2S Store and Forward C_INCLUDE_S2MM : Integer range 0 to 4 := 2; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Basic S2MM functionality C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1; -- Specifies the constant value to output on -- the ARID output port C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) Store and Forward function -- 0 = Omit S2MM Store and Forward -- 1 = Include S2MM Store and Forward C_ENABLE_CACHE_USER : integer range 0 to 1 := 0; C_ENABLE_SKID_BUF : string := "11111"; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0; C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input ---------------------------------- m_axi_mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- m_axi_mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------- -- MM2S Halt request input control -------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------- -- Error discrete output ------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- -------------------------------------------------- -- Memory Map to Stream Command FIFO and Status FIFO I/O --------- m_axis_mm2s_cmdsts_aclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- m_axis_mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ------------------------------------------------- s_axis_mm2s_cmd_tvalid : in std_logic; -- s_axis_mm2s_cmd_tready : out std_logic; -- s_axis_mm2s_cmd_tdata : in std_logic_vector(((8*C_ENABLE_CACHE_USER)+C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); -- ---------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------------ m_axis_mm2s_sts_tvalid : out std_logic; -- m_axis_mm2s_sts_tready : in std_logic; -- m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); -- m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); -- m_axis_mm2s_sts_tlast : out std_logic; -- -------------------------------------------------------------------- -- Address Posting contols ----------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- -------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------------------- m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- m_axi_mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- m_axi_mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); -- -- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); -- -- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); -- -- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------ m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); -- m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); -- m_axi_mm2s_rlast : In std_logic; -- m_axi_mm2s_rvalid : In std_logic; -- m_axi_mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------------- m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_tlast : Out std_logic; -- m_axis_mm2s_tvalid : Out std_logic; -- m_axis_mm2s_tready : In std_logic; -- ---------------------------------------------------------------------------------------------- -- Testing Support I/O -------------------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) ; -- ------------------------------------------------------------------------------- -- S2MM Primary Clock input --------------------------------- m_axi_s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- S2MM Primary Reset input -- m_axi_s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- S2MM Halt request input control ------------------ s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : out std_logic; -- -- Active high soft shutdown complete status -- ----------------------------------------------------- -- S2MM Error discrete output ------------------ s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------ -- Memory Map to Stream Command FIFO and Status FIFO I/O ----------------- m_axis_s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- m_axis_s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- -------------------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) -------------------------------------------------- s_axis_s2mm_cmd_tvalid : in std_logic; -- s_axis_s2mm_cmd_tready : out std_logic; -- s_axis_s2mm_cmd_tdata : in std_logic_vector(((8*C_ENABLE_CACHE_USER)+C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); -- ----------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ----------------------------------------------------------- m_axis_s2mm_sts_tvalid : out std_logic; -- m_axis_s2mm_sts_tready : in std_logic; -- m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); -- m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); -- m_axis_s2mm_sts_tlast : out std_logic; -- ------------------------------------------------------------------------------------------------------- -- Address posting controls ----------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- --------------------------------------------------------------------- -- S2MM AXI Address Channel I/O ---------------------------------------------------- m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- m_axi_s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- m_axi_s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); -- -- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); -- -- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); -- -- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O -------------------------------------------------- m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); -- m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); -- m_axi_s2mm_wlast : Out std_logic; -- m_axi_s2mm_wvalid : Out std_logic; -- m_axi_s2mm_wready : In std_logic; -- ------------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ------------------------- m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); -- m_axi_s2mm_bvalid : In std_logic; -- m_axi_s2mm_bready : Out std_logic; -- ---------------------------------------------------------------------- -- S2MM AXI Slave Stream Channel I/O ------------------------------------------------------- s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_tlast : In std_logic; -- s_axis_s2mm_tvalid : In std_logic; -- s_axis_s2mm_tready : Out std_logic; -- --------------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------------ ); end entity axi_datamover; architecture implementation of axi_datamover is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ------------------------------------------------------------------- -- Function -- -- Function Name: funct_clip_brst_len -- -- Function Description: -- This function is used to limit the parameterized max burst -- databeats when the tranfer data width is 256 bits or greater. -- This is required to keep from crossing the 4K byte xfer -- boundary required by AXI. This process is further complicated -- by the inclusion/omission of upsizers or downsizers in the -- data path. -- ------------------------------------------------------------------- function funct_clip_brst_len (param_burst_beats : integer; mmap_transfer_bit_width : integer; stream_transfer_bit_width : integer; down_up_sizers_enabled : integer) return integer is constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0); Variable fvar_max_burst_dbeats : Integer; begin if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc If (mmap_transfer_bit_width <= 128) Then -- allowed fvar_max_burst_dbeats := param_burst_beats; Elsif (mmap_transfer_bit_width <= 256) Then If (param_burst_beats <= 128) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 128; End if; Elsif (mmap_transfer_bit_width <= 512) Then If (param_burst_beats <= 64) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 64; End if; Else -- 1024 bit mmap width case If (param_burst_beats <= 32) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 32; End if; End if; else -- use stream dwidth for calc If (stream_transfer_bit_width <= 128) Then -- allowed fvar_max_burst_dbeats := param_burst_beats; Elsif (stream_transfer_bit_width <= 256) Then If (param_burst_beats <= 128) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 128; End if; Elsif (stream_transfer_bit_width <= 512) Then If (param_burst_beats <= 64) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 64; End if; Else -- 1024 bit stream width case If (param_burst_beats <= 32) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 32; End if; End if; end if; Return (fvar_max_burst_dbeats); end function funct_clip_brst_len; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_fix_depth_16 -- -- Function Description: -- This function is used to fix the Command and Status FIFO depths to -- 16 entries when Async clocking mode is enabled. This is required -- due to the way the async_fifo_fg.vhd design in proc_common is -- implemented. ------------------------------------------------------------------- function funct_fix_depth_16 (async_clocking_mode : integer; requested_depth : integer) return integer is Variable fvar_depth_2_use : Integer; begin If (async_clocking_mode = 1) Then -- async mode so fix at 16 fvar_depth_2_use := 16; Elsif (requested_depth > 16) Then -- limit at 16 fvar_depth_2_use := 16; Else -- use requested depth fvar_depth_2_use := requested_depth; End if; Return (fvar_depth_2_use); end function funct_fix_depth_16; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_min_btt_width -- -- Function Description: -- This function calculates the minimum required value -- for the used width of the command BTT field. -- ------------------------------------------------------------------- function funct_get_min_btt_width (max_burst_beats : integer; bytes_per_beat : integer ) return integer is Variable var_min_btt_needed : Integer; Variable var_max_bytes_per_burst : Integer; begin var_max_bytes_per_burst := max_burst_beats*bytes_per_beat; if (var_max_bytes_per_burst <= 16) then var_min_btt_needed := 5; elsif (var_max_bytes_per_burst <= 32) then var_min_btt_needed := 6; elsif (var_max_bytes_per_burst <= 64) then var_min_btt_needed := 7; elsif (var_max_bytes_per_burst <= 128) then var_min_btt_needed := 8; elsif (var_max_bytes_per_burst <= 256) then var_min_btt_needed := 9; elsif (var_max_bytes_per_burst <= 512) then var_min_btt_needed := 10; elsif (var_max_bytes_per_burst <= 1024) then var_min_btt_needed := 11; elsif (var_max_bytes_per_burst <= 2048) then var_min_btt_needed := 12; elsif (var_max_bytes_per_burst <= 4096) then var_min_btt_needed := 13; else -- 8K byte range var_min_btt_needed := 14; end if; Return (var_min_btt_needed); end function funct_get_min_btt_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_xfer_bytes_per_dbeat -- -- Function Description: -- Calculates the nuber of bytes that will transfered per databeat -- on the AXI4 MMap Bus. -- ------------------------------------------------------------------- function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer; stream_transfer_bit_width : integer; down_up_sizers_enabled : integer) return integer is Variable temp_bytes_per_dbeat : Integer := 4; begin if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth temp_bytes_per_dbeat := mmap_transfer_bit_width/8; else -- No down/up sizers so use Stream data width temp_bytes_per_dbeat := stream_transfer_bit_width/8; end if; Return (temp_bytes_per_dbeat); end function funct_get_xfer_bytes_per_dbeat; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_fix_btt_used -- -- Function Description: -- THis function makes sure the BTT width used is at least the -- minimum needed. -- ------------------------------------------------------------------- function funct_fix_btt_used (requested_btt_width : integer; min_btt_width : integer) return integer is Variable var_corrected_btt_width : Integer; begin If (requested_btt_width < min_btt_width) Then var_corrected_btt_width := min_btt_width; else var_corrected_btt_width := requested_btt_width; End if; Return (var_corrected_btt_width); end function funct_fix_btt_used; ------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------- Constant MM2S_TAG_WIDTH : integer := 4; Constant S2MM_TAG_WIDTH : integer := 4; Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF; Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT; Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE, C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH, MM2S_DOWNSIZER_ENABLED); Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE, C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH, S2MM_UPSIZER_ENABLED); Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC, C_MM2S_STSCMD_FIFO_DEPTH); Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC, C_S2MM_STSCMD_FIFO_DEPTH); Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH, MM2S_DOWNSIZER_ENABLED); Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS, MM2S_BYTES_PER_BEAT); Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED, MM2S_MIN_BTT_NEEDED); Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH, S2MM_UPSIZER_ENABLED); Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS, S2MM_BYTES_PER_BEAT); Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED, S2MM_MIN_BTT_NEEDED); -- Signals signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0'); signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0'); begin --(architecture implementation) ------------------------------------------------------------- -- Conversion to tkeep for external stream connnections ------------------------------------------------------------- -- MM2S Status Stream Output m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ; GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate begin -- MM2S Stream Output m_axis_mm2s_tkeep <= sig_mm2s_tstrb ; end generate GEN_MM2S_TKEEP_ENABLE1; GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate begin m_axis_mm2s_tkeep <= (others => '1'); end generate GEN_MM2S_TKEEP_DISABLE1; GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- S2MM Stream Input sig_s2mm_tstrb <= s_axis_s2mm_tkeep ; end generate GEN_S2MM_TKEEP_ENABLE1; GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate begin sig_s2mm_tstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE1; -- S2MM Status Stream Output m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_OMIT -- -- If Generate Description: -- Instantiate the MM2S OMIT Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_OMIT_WRAPPER -- -- Description: -- Read omit Wrapper Instance -- ------------------------------------------------------------ I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_omit_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_OMIT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_FULL -- -- If Generate Description: -- Instantiate the MM2S Full Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_FULL_WRAPPER -- -- Description: -- Read Full Wrapper Instance -- ------------------------------------------------------------ I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_full_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_BASIC -- -- If Generate Description: -- Instantiate the MM2S Basic Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_BASIC_WRAPPER -- -- Description: -- Read Basic Wrapper Instance -- ------------------------------------------------------------ I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_mm2s_basic_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_BASIC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_OMIT -- -- If Generate Description: -- Instantiate the S2MM OMIT Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_OMIT_WRAPPER -- -- Description: -- Write Omit Wrapper Instance -- ------------------------------------------------------------ I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_omit_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_OMIT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_FULL -- -- If Generate Description: -- Instantiate the S2MM FULL Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_FULL_WRAPPER -- -- Description: -- Write Full Wrapper Instance -- ------------------------------------------------------------ I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_full_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED , C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_BASIC -- -- If Generate Description: -- Instantiate the S2MM Basic Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_BASIC_WRAPPER -- -- Description: -- Write Basic Wrapper Instance -- ------------------------------------------------------------ I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1.axi_datamover_s2mm_basic_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_BASIC; end implementation;

bsd-2-clause

554ee9f7e9f5cadc24d288bc28227b99

0.400768

4.190677

false

okaxaki/vm2413

EnvelopeGenerator.vhd

2

6,777

-- -- EnvelopeGenerator.vhd -- The envelope generator module of VM2413 -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use WORK.VM2413.ALL; entity EnvelopeGenerator is port (clk : in std_logic; reset : in std_logic; clkena : in std_logic; slot : in SLOT_TYPE; stage : in STAGE_TYPE; rhythm : in std_logic; am : in AM_TYPE; tl : in DB_TYPE; ar : in AR_TYPE; dr : in DR_TYPE; sl : in SL_TYPE; rr : in RR_TYPE; rks : in RKS_TYPE; key : in std_logic; egout : out DB_TYPE); end EnvelopeGenerator; architecture RTL of EnvelopeGenerator is component EnvelopeMemory port ( clk : in std_logic; reset : in std_logic; waddr : in SLOT_TYPE; wr : in std_logic; wdata : in EGDATA_TYPE; raddr : in SLOT_TYPE; rdata : out EGDATA_TYPE ); end component; component AttackTable port ( clk : in std_logic; addr : in integer range 0 to 2 ** (DB_TYPE'high+1) - 1; data : out DB_TYPE ); end component; signal rslot : SLOT_TYPE; signal memin, memout : EGDATA_TYPE; signal memwr : std_logic; signal aridx : integer range 0 to 2 ** (DB_TYPE'high+1) - 1; signal ardata : DB_TYPE; begin ARTBL : AttackTable port map ( clk, aridx, ardata ); EGMEM : EnvelopeMemory port map ( clk, reset, slot, memwr, memin, rslot, memout ); process(clk, reset) variable lastkey : std_logic_vector(MAXSLOT-1 downto 0); variable rm : std_logic_vector(4 downto 0); variable egtmp : std_logic_vector(DB_TYPE'high + 2 downto 0); variable ntable : std_logic_vector(17 downto 0); variable amphase : std_logic_vector(19 downto 0); variable rslot_buf : SLOT_TYPE; variable egphase : EGPHASE_TYPE; variable egstate : EGSTATE_TYPE; variable dphase : EGPHASE_TYPE; begin if(reset = '1') then rm := (others=>'0'); lastkey := (others=>'0'); ntable := (others=>'1'); amphase(amphase'high downto amphase'high-4) := "00001"; amphase(amphase'high-5 downto 0) := (others=>'0'); memwr <= '0'; egstate := Finish; egphase := (others=>'0'); rslot_buf := 0; elsif(clk'event and clk='1') then if clkena ='1' then -- White noise generator for I in 17 downto 1 loop ntable(I) := ntable(I-1); end loop; ntable(0) := ntable(17) xor ntable(14); -- Amplitude oscillator ( -4.8dB to 0dB , 3.7Hz ) amphase := amphase + '1'; if amphase(amphase'high downto amphase'high-4) = "11111" then amphase(amphase'high downto amphase'high-4) := "00001"; end if; if stage = 0 then egstate := memout.state; egphase := memout.phase; aridx <= CONV_INTEGER( egphase( egphase'high-1 downto egphase'high-7 ) ); elsif stage = 1 then -- Wait for AttackTable elsif stage = 2 then case egstate is when Attack => rm := '0'&ar; egtmp := ("00"&tl) + ("00"&ardata); when Decay => rm := '0'&dr; egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7)); when Release=> rm := '0'&rr; egtmp := ("00"&tl) + ("00"&egphase(egphase'high-1 downto egphase'high-7)); when Finish => egtmp(egtmp'high downto egtmp'high -1) := "00"; egtmp(egtmp'high-2 downto 0) := (others=>'1'); end case; -- SD and HH if ntable(0)='1' and slot/2 = 7 and rhythm = '1' then egtmp := egtmp + "010000000"; end if; -- Amplitude LFO if am ='1' then if (amphase(amphase'high) = '0') then egtmp := egtmp + ("00000"&(amphase(amphase'high-1 downto amphase'high-4)-'1')); else egtmp := egtmp + ("00000"&("1111"-amphase(amphase'high-1 downto amphase'high-4))); end if; end if; -- Generate output if egtmp(egtmp'high downto egtmp'high-1) = "00" then egout <= egtmp(egout'range); else egout <= (others=>'1'); end if; if rm /= "00000" then rm := rm + rks(3 downto 2); if rm(rm'high)='1' then rm(3 downto 0):="1111"; end if; case egstate is when Attack => dphase(dphase'high downto 5) := (others=>'0'); dphase(5 downto 0) := "110" * ('1'&rks(1 downto 0)); dphase := SHL( dphase, rm(3 downto 0) ); egphase := egphase - dphase(egphase'range); when Decay | Release => dphase(dphase'high downto 3) := (others=>'0'); dphase(2 downto 0) := '1'&rks(1 downto 0); dphase := SHL(dphase, rm(3 downto 0) - '1'); egphase := egphase + dphase(egphase'range); when Finish => null; end case; end if; case egstate is when Attack => if egphase(egphase'high) = '1' then egphase := (others=>'0'); egstate := Decay; end if; when Decay => if egphase(egphase'high downto egphase'high-4) >= '0'&sl then egstate := Release; end if; when Release => if( egphase(egphase'high downto egphase'high-4) >= "01111" ) then egstate:= Finish; end if; when Finish => egphase := (others => '1'); end case; if lastkey(slot) = '0' and key = '1' then egphase(egphase'high):= '0'; egphase(egphase'high-1 downto 0) := (others =>'1'); egstate:= Attack; elsif lastkey(slot) = '1' and key = '0' and egstate /= Finish then egstate:= Release; end if; lastkey(slot) := key; -- update phase and state memory memin <= ( state => egstate, phase => egphase ); memwr <='1'; -- read phase of next slot (prefetch) if slot = 17 then rslot_buf := 0; else rslot_buf := slot + 1; end if; rslot <= rslot_buf; elsif stage = 3 then -- wait for phase memory memwr <='0'; end if; end if; end if; end process; end RTL;

mit

f24a27e4c463bae6fc3032d2dc13d0a6

0.491368

3.835314

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/shft_ram.vhd

2

17,157

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block omNAiYCkVgSpwWQRAVcNRmuVjDasJ7fqBecood6uQTvzwoer3VBmMrl/sKgXm7PV8OHd6KFUTW4j 83emWzmDUg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block IaH7PVbW+RwPNo0qPm77xsP1bwSgN5Pcmrj58RwcvtTJDNH3F9E+ML4deTpljXJX6IrcaUdM2fNM ImiRygT+gNJqQohHgw4LjniGngO6OqAzjoHFaty+7DxViwIxpXBk7b2Q1GhKRKAEsQ7lddj/6x/d 4CGtJastysBrrJIcFbQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Ge471IctsRp49yURxoMNLow/OTPMRjr6NPV2erpJ9mo80k07ietT/lb8QskCLaX8Q5gAwn00BfR4 D2wUNUvm3L/neIgvU2m1uMe2f55wNoZSu/qopn2UhnDs2QtIwG8zI75BYOcuRxM/NvnKbQKe77R5 o+y6K8keGMD1r935nsUtzvNSzgGueB3icYvB38NAtJvMzo6Ad+gaDzNZZAdAHj1f8QQNuewkrFIU 5nWhoM6J80xziaERJ3HbNlRMU1HGqSkW3uhlRZnMMDbCuIsSPo/IAXGYsGD1+0KjTMczr2LEMZkK fZKFt7TWo5DpozLWa2nIMYcUWkshdXxhjDkTtQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fY/cdQmFQ+zAfd/CHO9RZSw4dau4s8GrEQbRh5HbEGxAQvIHnFVvGRkVLHfHgtH9ZMBycKcc0871 CofFMdbWe0fsr1hyYI+8gRnD7Wj8KUs+N0Qhv4VZAruvhj6Bbf+rWDnKXPzVwS3zEoCTCkt0BDZD aHjASTSOAq7owypnPfU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block BArrUpKvws2Un7xsPVYAW6wuAm0/EOtH2Gl/W0jc7gYlPv2wxUO97GKivsBofywjFoGtB3haW7or t2P33PhXIHrNFG8oKURg4tEPCT738HDZxwwdtQ8GUQIh592wuBm74VTPGDqhfQnfJvEFKrDpB6Lh dt0W+Sh728R1BmkO860vI0oBTFZob3BcKK3Y0oqwJsUanjWVmczXn+2agzrUSgEI+DZOSezq5lRZ JuGFUxRPpb7O86+d71NQf6KW3JhysnoaawZ0/APwkxqA9Cs3es0fkOAmDSfc7/+ZPX+BePycquBF X54xG6uM8J7fqk1enX6UXADv+m7sB5G1Vn9xWQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960) `protect data_block V7jnI5Kn6xyQkIOmBVDJEC60punMuYgTWL1S9XCO02XfS22iHL7vDVg6zN7iWSP4Dl6a7lU2vNBw urPyFcDOwKMXKkVCx3ZgXbnagYWErZvUznXVN1ZHOtMuZsMJTk4OcOIyHtec0G1C1xBuX1yj1OfA KnOU1T3pWuVxdkcL1ykQjcvn8N5OGWDtPKcKyvXm25DeO/3KfPULXPhpuoAMaVYoDE1pnhUop5BQ hwLOubJ8d81oGCpxpRxiyC25gqkyh6YwT8mUyK5snipwSY3it2fWueiFASt1rl/NILMxKrh6fopx xnNJS7eG7QTTcJv+/PlfkjNJ/lkb9LwINN2bopeaA1LokYr36vlfCClNQ+ouEkSpgnAYKGjvUtBk zDUN9o6jadAsLwm16udP/IMyJ4tR87NXvJ1DRIUJuJQMFSciT5XP2OTYWp2ibPlwHWlWooqe4/ZQ h6HJn3yvDDk1H9LiPbH/Amqw6vUyKr2VsaBEiAgtw6rH8dZPv1fpA79KNhfrOpqixWZ3dU3iG9P+ 5NoHcD86fR3ST2oUPIWXA7j5lPcqvHTlk4ZswP2nHPjZYgq5/UkrjdHaXhbHjMB1NarPx6mRs7jq 223fByGtaAgDUsHQWJJtD7A2Uucd/DrTiKb/3rlhutnJpl+rRyfHgiIV0NUGocGFsS+23zjVOVtY GTSsERt1279CMwwHfw3+fZE7q4fYPf2xphL/SiD2K82EJfXwYxJ1fs/i6XiUee3J7RpC2VTf5sQG k104UVw+FjDeaV8l8PC4DuQkulSzN231o36tbxjybqdNU5bFwGynQFptJrwejMCtG0DIBonkpUFX 2QZwBPsqu5ule5EoS3Xm6r3v31ZdVegpqnDya/PsBgVfeMao/b07aomZIxCpmDkRNVgvRV1Qfya6 wjZqLryulkwIJV0680LrxCUuZaOHCMMTO1QoxJfWqv77r7nQ6zPToNzyTM/LnPmKDTVexGRqmnDN RLHgpCQw7E5ATv8UAN/ALtgVIjqMvaG9xjyJ+d/HlvPg5ccAvPuUMtaxf6aLpSRn1rP3z2OqhX9Q 2RDVeyo0XqRalXIS5AWLQLpsAcZBItRzQgNoI2p44btiINIkesPJp3+YA55CdGnT6TVaosO4/qUh rsvSeMzFnxhCgN+RNy5LPjIyAP22aON92R1hDx3VfBEw3/5ITdJC5MhJo5YrnQuUHJBiriR5wayg 1TsZzKw9i2QlciU5pNQS5tAWqP9Aw0yXKSjOmKASEZ4wT5w6cu0+lTZ35PyEjKRgwOK0Vv7km7wp 1xoU/8zRobsVFkfGH5kXfiuRK5kKYiREijgf9U8xXdPT1siqrYNov3TQMj4Rj5NvrH7/mUoCQupM CLuzgQxSuiKkoa6RxXvvr6/rcwHpKfdWoTEQoRGvalIr23qIELYuqkKDei7ZuljKpnYNRLkbqhHK AOHxcre89bJMuI2SbZ2k4Xx5MwudykrifXYodr0TySnQojzChadovLrqigEEj4FGhiYquxpHKPKL rO/A1XzpPBKybj1PV7NVnVkKlFOA+wGD3Rxk20F4rr2koix+nPTDrqjAy2zesnrZFEe9xBnIPPnH nSyNDfZJSXBSENA+AMja1/jOYnTHblI38l+oG4+l6ZHvz+ZzyTLIOG/1Yb+Nl5WPqBtA9tsFt/7u fqkrZnKVxbYNeiaCNPDy56IHcsr9s77aklfNx1tYzHE/eXqJ6RDGpfIoMKtEVaf85aJ6xoj1ymqs pRoeZakH//Ec0Qa8Nhmwn4MNNSxVIZQE4iIUPLeFN7WKkk7Y0bpsF07S+OSvS6Jfvx2cdaVUvB1d ihuWqSOEwwSbUVEbSVZiRl+IjNhzOB36BBKdrFpKOCh2OvyVFG9vNAuxjFNbuR5fPcndn2VKpVBA ST/fyoo2mQAUc5iLp3lJrjKsEYlieIqr9GMzG1ghy6S2Kw+eOiWeVi6HfVSuvykCZrnOX0CxCypB pt0UiuUo9nin1EGl5FnX6hvKzaZmdUZPcXHhDY2GQLe6jHNjTiZ3a6ZDWIHyQnlYHmVdCUCUaMS6 Wc6V5F4LKpYxwSEoYyi53XCm6cK5SwxCnf309relrTF2kjkg54FE6Vvc8b4+lU7My90yYDTGdI7B S+gRaTo8sOv0TWMvLhFl+TF7il/N2y3d+iyFpf6pIukalhqUnGnB20mpDAiTR3BJ7cybAYNsjZJp 7RRjvCOUND6N/PYJp+e3E3dzqbdfNHHVVpcFihqgz955CV5mr2CDUjnecRxgPtjS5iidhjWxYOI3 f31FPAm1TDb/fOG17rSB5DxcmlBfJIIO0w5V9TLSqdxQzwsW210cfiL7NmJbUl7M2M5cN5/4D9cv hfjLJbvobAAzRTa6G8rHMNW96ZDtbZt0c6i555GYMEKcOBv34omkyliPHLxt5u4fukfI3CGD9Arc pHSYQXeyouR7rG4hCgj8wq8mgqR3ie33XuXWO3vqvdAJk+36eyH9Py+1vaMtviuuAzQgV/X2hTQS cqif/m3hDXCj9Gxy95ym/ZhklZvLCovlTG6zzqgixRuy2g1E0KpI9Et+A2aZWUzHz/bKy6TIJCUn JwA75hZ4eGgfoeteNBoHdchHn0zpN0y6/T6wUug+3m7v3Z5fdvvIjvfhzzDDEkYZy51rOG7sX66s /ksKivJnqp9GemHzJToyUHOR8q34QOAc0Qglis6pyvwGmu4vJGwXrFOqLPZfn4T0YVHnC6T/jI2k AZsM9Rn4T646CY3EA19FWdshP5LobdLTKZOWQGd2nJbBGMffYSwvk0EDDcxO0S4yGOySmfLN3Gdg 61L93VO1zNjKi+bXbflYf8AGYod51gswBJ4AP6e02xmgqjx77wyXGCBd+7Q+BgrpM5SNodpFEP0f NZ8FxCjJk82DKdnH//6clMHeTurNlkp2/x+hsNjiPl8dLMMCTSm1CQD/BCNl05aAS973aD1GFL/4 WPCrmWpff1lV5dTmUWKHGMVu/N3UiqwBbmNM/FLTsGBxOujN16byzWRnrAc3BIa01ooAgLxmN9Gr CTvgYyU45UajraicPb0Kwjor0xOn+rYvpsGMCh3SJq+E/Vu15+QlyuGnnSb/mH2bxChVj+VZSOEg dLC8KtRsn2U0JYEd3j6u8gTxgSYFbAsCaNlzlc8oX0yByvPIcGb/8cjvLCNR3itriBH0TjecT+YU AbGOLY0lPhCHojQ2AevSknwoEgAD0L9UTPNCsm6yrKDB+J1kfWzgf+22pK14zaPzEzKIyEE+oAtg 900RTGlw0ekOwV4ZCGHUbrXL+k7gVy+qN3BgZC9I87t1IZp6hQcDBkMNRrNXr5TDypFc+NHM/f6r 6zJ6kFX7/sCfC/rGCKsEoodW4gO2NoQFeW9tDlIuLgbsMhwI4y5VoHXhpxWrg37hn8CHErfNZmyT VxIKKe6Db8igN74ksk+ErtBUzPxwLnxrWCw2YYiLjqdh0SkqpcPDjIY19bO7gRlt5L9TSLmjFchc ItxNBD/UGsXSDs9+aoGTqCz1MoeJbCxFhZo24TkehLgBG69nwDdp5fEXiuN6NoF72QJRZPYyGeHr bz2yQhJ7jEzdqAQKGLzdtoAUpEO7roCocO6XC36h5up0C5Soslyi+ve1xBbZNcio+NO5KOLtdfo+ 0sHQmLWlxMa/+B94kbpGY59PxNtpZqvHqGKiKIDU1BjOs5NOKlAvNo1hrAQm+FuDgodgPgTJRJND bB6V+oP8QrkE1S157Rj8Ip7qR6V0FLe1sU2nOVO6bw7eZo5k9m9bYY9dA2yzuwPYH4a5tsxzFNFO qZefMNpe1p/QRttHLomcAWfd5siIN75aBd2bXiopGcWO6WUiEv3Fi4HX3wD8Dx2H3SjwoP1LCWK4 xlSyLYocmVemo3Rq9Xw5IC3Riur2bv5d9YRYanScOcqHU4iuFHKnTB035puX3Br2uHOx/U0ILQ/H p6K/6r3EmFrCbHCMFm4L5WAJhFWPEJcfBZVNWOBLp6zX1VKKq27SxA4B7Zc9UnTZfTzu7Uhe9qym OsWIYcdcqatmi9+mZay0nxxujuniBcfpZqv5rDJBfaPm8vVMQI5XxQCsfHdgqOX6Ngs+iAj/x8Tv 1ZP71iK2yBkBAEI2XynnaRNdCCKsRjE+hK7plK6Q/K9Z9aakXdahZuSoD8HsYBV3GZrAqd1e6uiY d+SVUHnslxMVVVsBiZudgoRw44rhVK3qHjx9fag18CjCqIj3bIH7in+44U6CEvjDOHZtIB2+9ZOu ePEDghK/ljkSj6bHsbLmJ5s1DbjyhrkMkKLQ4fNjqKVTWfyBlSlYRQXfGk5ydr7ChCIsr+fsUZTt qBywK3K+P2aW9ACvfiXEsF/ZTEr+BDoCoftLMpVDcyVoyAgVIwi388djPURVrrkngaQ7oVGJqsbV OJjqxRajvad6vqLjNqIcXqMrk0uB3oaXl1Hlq5aOoDpGK29Q6f8uTiRZLkYqY0f3Zm8xMwOGk4NE a9M4PhF/M8iRM9nDk83D2K9vpxTiiA4S5Y8MJRSOkEXzky3SWutXhLsErnuCwnEPURyvoMRoL8CG XbVnxAqN7q9ZTghR58VKrD4/MXBYwkamZqmEmkm+4OpmIT9Oqz0BeQ+irXd3aEw5hZM4NEizIQ2C 3me9EeeD3SZm/axLzY/yJoNJ1IBCYgCXuChjS3oJQwS/4t1Rc/29oDUCSkOoMCyNR8/PjrVzSxy3 PlhpE/9BwnIr42ev+hFbJWJgQrxBIzosOmf/5zugAhbJ2KVuHk5Ddb7ujpO5yRR7FVsrtzMmeQli DFfIGcAvxP7Pi/niWx/HOlUum+MslY+IonKjkf3IdNQuHwP1Qi01/8giEGCX+VfmFZ5VOaFp7njF qEnQCUbzZcfnyJjQ7IxyBocHk/mOE1HM0wQi8X6WJ4MwhougwUVc8MyvBfGvKuZLaknvSXdpSMm/ PawH52khC6FraGOj/C5NcqLJrIlNR0X5p5lSNUaUkNW8H/eo+F5E3SHPbl1HcfNATv7KBlTBJd/f G+badCilzOiCpterkNEvrRA5eE1630sZeuYp41XUavhNpQ3yIi1tKT2eHOrOaZ8Z8gdDe06PeCEj JlWQ+Tg+4QZXBixET+TFwR3i56KVAgYDVfGZmDv/rF5lW3e1DaczgQ77WkhVMUD8+tycf/bOtj3j ljPd8V3gG4Xlt2Q5XboDK583Jk22Ian49lnDUCtnAPDM6l05qxrJjJdaWZKMlz+BMJlFBS/7tkDS yPVDcTvwWOWJ+phg3YbEQiFonJ9WldsTsp5Jqx1cinWWwkFGQZH0kay2nx15fPd70jmj7VDJWGn4 k61Atnqx3HnkouQU2B+zGzml+BlzownJWUkTbYSIw7qeYg7I/pa0hwV7wBV6qh7Q7A6ESRsz44Pv 5jecX+jNPphNNx6BIzhvWs5lnJsoEpGQEidw8qQ7sdehmCVOMutfLW4cxHHsBD3lVhfpH1hIuOPS JuEHHfpAAzEkqKk/XSq9cJLWvmGHiaByaugFECwvgtbGclRE71rvbFyXeZD5/oEi9znBc7CnkP6r azQzVYtITUIT8s8flXl2ki/gDJnQFq/kSJRIZkK2tkBM/41vkr4bloCiTWB03Hs953gF2LEJd0og h5pLovTW3+HB7Fil38xvqF7+O5SPaShjg30Z8Y4CF2sz7vfVR+qW4aUvKezl9aWj/2Q2kfbIh0FT ybEaXohCmdZEgL3PjXoRMQ/l0gX2pHQnY0yHLoEPQCs2bBFGsvrx5JhItPlWUUNPd97AA2hLryaE B8jyFE7mPRey0ixE0+A43VPJgqPU4WBlaYAS1TSzI0X6XId8ctnUdqgn5MD8JgIFvIC/odp+KrsW oYt8OsES8D9ni/OiIZRZ9tC1+uCQsEQmo7KYSNkKKsXLvZ6HwdQsayl25WtK11ARCK0hJ42o8J3U TIQ+bri9GfQ4qUjkzIAKMn8v6PU8nYpaDVyAhVESdPrgkYDSAY3A5+5ko4RhBF/0yaD0LXsoJ/rD swXZUGk/tJ6hec4kbRVJTOkUsJOGzdKb9vhJoROG2iXzlCRhtsqBOdDpioZwlGcyFppFs3AsmX5e zznFenhjDyk29+41yPJjgrXkkTrduiG83a6YB3uhUx142QuVYOX47lbF+6tsl/mGJkWZVZPyrDM2 SFPuHvMjAqhfj9YEVuUjmOHNhDlyHmwfzCYRU1tgz/MeBF0BOBcU2qv14ZMPAMhjNdslxxx2R3Au 5ZXHS//ECV6nH36lXOT6ovVpYmAlet38nNkf/nwIfM61FpPVg+9ZuGampOYhGlB4Xjnevf5tvgVQ kkkJJe7diN2GSc5KZL0oi/w3DIpuctQCpL7XjwNMt5VMRzm2DZrddkLye3M//G38YzbemUkRK18z HxXskARWphAsZhl34ym4Kf4A6REa7hc+jMytxlu/A/kPykBy+WXy63UUJ1+fTW6I9JdO/3q9/jbq Ketwo5U1uNXIV8dpL49Y0vnkJHJLcq/Yg/gquOBoK/P+sCqhmbeYVsTGxdur+qxMbkb7ep9eaVLP 8pQDfjApevJLOznmxf0csR8i5HIdiMYRmJb6RFXhSj3daP7lNiBIGqXr8hGiewEC2GR0TA4Mi9zQ 8md8ez9jIOAHadPAih5I/IXqbflghjCBpCV65+908/veZI/LyYgyzexs0id7oT2BmBsbVJdlSUjz 90uHd6r4Qcb/1X+WXo8zmMm/JONxeR0WF4EPZdcDr0EdnSy36BHPe1+N1PPrLAU0Zx3OiNVhHemq PL/+En98K5X2QRvjpH0QCi/KgS623lnP/O/BUxu4TPxWaPs4E2LkYu0b98klKdBGBfyRbhZCvG5M fo9qdrueZZWFnjz19707l/M7+0URJBmBUhwDECoTDjWK5oU+fe8ULMy5w6yknn358HBVAmCOYll4 wf5O2M1tMegJlRQrevR10kYo7pVnvnSZVkn/qBHnhsNAa2oCnlJgwt8FwFrmjBb2YRg40pBcV/2m x2k6Akw3vYAGldfkKUCPDYTjaVMQ3dSzzn8EpR0kQCEjUhkuCs2dxttKHI3w+2iV3REsXl+X0q8P x8YNiAoL85QTdzDtX7fprww1rrOtjmnUypz2MG8WSNRVg9ymfXOF8Yqb59gmVcYkT1faBBHUCBhI RyGY5GCjS33YcnG1dA+bczsp5r/01it/G6gT/mOJ4SzYzJXe56+rORttFA9UfbVMf9Ysg5V9G9bl JA8lGajqoHGi2w/rp/AGPxFAeqZYRPrzLZq/GVCnQ3L+Gauoii4p73gNVCjm1Ndw19XIqMOs0hTi h1TB/flka0bRBLYPePCbuMVTND2OVj24tPCvhcQdkXeu9Vxml6aMEml2/bGRCJDegwpCA6AcI6OO QJMAqZumdxGSaUORNj0sPtVNjWlB20EwoovgL1Ams1Hp72PRBen2fwHw3KdApeZLWfvW0EBVXMxs Au53gnh+IvHOuWTJN/PBGFKZU5lPmI5eG0Z6kgjQCgiiWGLX4pwOF11E29LMdqmPsgt2ZFnqVoV+ +OIf3MMYrpm2bIIu2sO1FsGbSUNUNFr4jyzQqYU1fliEB/p8EbXcLoOlQYblZsnK/nDZkc6BNUrl jQXUX8xJoTd/fCSpWxIcYzmCXtEx2atibiYO14xdCb7Qvr5NrFtbV3NbOousK/WOdLqk5zmmvLk9 pDMxhbNqrZvBGSBPvs8vvsnHvIXk97h5awRiRBdszMyxxwuZQ9xVHCkF32ylvnQU5Dxs+b0/hQ4H MbEjSIkB5GQ+Xk7yi4E7RD/tdQYz96a8sYcGGe6qNfakH7f7aNe9vLAHOCbGa2d3AS7bJPCvts1a fe/tkWpW1rMcKcXiS4Y1ST7m4QpAPxQgyE+wk7MJMXoJ8d1B35IsKCA4/Oxf2dSWjdCsLzfGMo6N Jp0jThnD9lEVd0RD/fC0bf2dln+u+jhnr28ZQtbwuvTnWjHVHehfAuVEqalbBF1uJ+Ykh8c54naW QTGkBO6zs2cCQLia0V9MV43qXeQraS5hDyyC1in71eXi01rvrh6kW64v6gcMyYoNFuLB7o7/D/C/ 65nI66jCK+joOTte0D2IUpL8cgJPlh8RrcQennHecYm8/HqSD4TUJtjLcgnz13WlplV6ruhftVWq FCIHQpjicO+NyVIMikcoDT9WrYftL3Rq1/4PZCZN8dRxXT088lA+Xx+r3VRq+mjrG9WBZsbg1y1J iFXjk7vMvtpI2Vu1NytrMc1BciYoKByoDPmHJ/5yXBOHOWoT6HCfWFrmO3lTduoakhq0bRwX2fDw IRQlkd5ylMAq6vuwqU4QEzxKtxinP0VEBGHWYLTU+2daVVO5723DhBYgRavy+PLtyYIISRF0C6Ad oGVsSrPpCNSYhZbzd3DY9/+G7KneYaIhqYn+YWkLHk8bEyR2UD3JX0CaKZriJdjvt1DYRpePA2q7 YpmQednFht8hbpJnlWD7Pw75/kRQHckFCByNw16glAWIvjhFJ4Dgnyi7H8Nfdw3c/AGB2toWu/T4 8PwMyhuIh8/hjtWmgqMurz4nZFfyiuWrXYvYg/ywyiRLQ3M5Nzi0xZ97uxYT3e7niQq0y9nBA23Z 04NEpDj0i1pRrVjjosJI9twoV/+LrDLy6ySml1qv9ZMtL+FwvF2Y9G6YrDhUfz46lk5Arkxly4Ew wg574qk6HoN0HC5prBdkttFy0dNwjePzUz2lRlPynE4CyQ3FTUR4fF6oVtp+jz1Yxb5SO+t1Uwr7 0DWkMLCqdF6ZAJCYFFzwoZM545GtblNW5x4ktXN69UrMng4JK7jiKcHdzYcmkBBpQQR3Fd+zL8ze 5PNX79uFochONHtMX4Hosz4KeHJDcgmbzKqltDbm4ka9tl2+zuLHS7lJAnDrUUFoVSSe4lm0ErBK nRTQVeT8PNZUvgFHk+yxi5h8pF2Z1rXvZMMn3HVkbJ49yXhACWEzH3tYXlLIfCVp3uqobEN5PSMA SvmTpKrJmPSxvcqthi2XAlSzJgJemXIjjqaBeSYkZG7DnD0UxVgqqkYUzuxCcEsVV6XpPmEjf96u cWZFilIpXS4/zTHyRMIoEdaT1KdgPmNeO4rIwRqnotvR9h6n16rQ5zHCEu/fn9+ny56Dco1uBng9 x23xmSWQ4oNIpk1hmxSNtVDNe3MRuU/MM9wYT1yq2jJA6hTy2ztPmCxdIEFjHpk8oHxPQTVwYI6T CiNq6mbgtT73j8OHEQYSziD8+c2xTzN7JMGIIg7G5EYRdrKDK4UwmeHz7cgUn0BZ8/z5/fVYeQUp EC+/7RotMJeklkzKZhjRk7rjF+7V7yePmgrcLU/Cc7L3jesKUCQN4Sw1GvO15oaa+Rg4VAzJwkwu vBZEOBnvQX5Dsd/QMOZvgqlknW+1Nsc5o4LWnfVfVt3GbKPGtQxkG+yVK1uL71AwY3bxgchwBoel qo+Rd64I9hd+N3W5RPXmvJZ0l11izG+vTcXeGVP/NHQIh01N1w5Tp/cgcXRJMGd4jWyirx02EEQw 2YVOU3Fw+P2cEbGqjeVisvGBn4jd+mTvSKGg8fB9PNLJvc4Y7DDM8InkzjRKgnYmTOWOhJV83lyt yn0In87cp3scIma3fD1jMmh6BYfYKGR/ZLoJOKK0Kj9YSU5h2UnzstnxkdJRcimvYiQaO8QaCj8K j+xDw7vBMash7jkZf0nC/ejz1JAyLLEnw6XtE4XxaVDEGKCPCi4wdcPuqhnhCqKZy/aHFVUPeUni xQs2uT6Gx5DQ9rh12KrWzKdfofZMiNRsF8lPirH2MJs3F7kH6MOIyayZ2AF8TGyKNsHnmx3gM9R3 9lEDCNjw/ON+gTPzeEjEE3qfXiDKU9dVADK2hghHuBbBCZtG4XCKymG8cnNM0jgrBTEPf5MOhnMC 4/4co5EuVoVugTFzGSFIf0biVcH9AzodyFKT8A/rnvSMq8EqI/baysCbktFtdk7KlvZ7//AIE08p vy9944vajPW5vpba++kv00fibHzDRYQWAAP/Jr8hSN+cjBxOQVI6MovKJ+fHRCkXvWxA2RC89Lzl n7FYjHYolHa2V8Eb1kVU9gh69occiVJ2ItiffdKsa0fGqV+HD9t9uZ8UzWErK/T0IHSYwODR52Ff DkuuZ78DbVREL7ywrwszQhz9PE9SO9eKT/e3FpDFex9DQvPKydPR4FWzQg7Ry0nVm68iTdTmq9rY AUltVsfZkkkyXIWL3llyJs/dpj7kkWOJhwbhr4q0+j19kbP7TQXZwb1zKAeKFpGxfOWuQUfbTK05 zwOmGvK94GqJzg4HlyFLzJgwYHU0uWvwG/rUbw92XJ70s7M1Bzm0bR7pJic6EOE3qiFNleRnPyv8 jZkxi/eAvtxGdDLKOKm+d6M9UeH9VXIG1OEOmVNBP/6EZZNvFNAft7zWNN9Lb1/+2zrNY2CX5y+P YIY7XbIyX1Yh2meRbtZXAVCbXb7pulRlBOW8KwQgE8SoeHkr7AXHnnqk+WWHkRC24ZlR0kytUStx LyivKkt0aNR+gNFvPSv4UaufF1TMBxroEXBhUbKBGrMCeFjnVUkles18O5lkqiANoLMD/CMG6hEv oEDndtPpq0X4oPUy8HzqJVHxcq30YHpzREkySJa8mcFa8ueUXYlIea+WUso2s3Np4YCLQkTbNxY3 qypO7rZhwVCr+oQbFnsSqX/TaTyJuv4HtOgxg1g8AdCbSReQctAEQX9/4a3+VfoWzdTk7HY6geGQ gHnHu30yiees2DAbaE0lxUsRvYMvDJQKWENOFF9mjhyTBZKlMlIadMZRnR8eucCCQCDD+StDA2oY HoITGf3xxz7ZfoNxzlUQue9bbuylgs4vH8JD6evovgodDM4lKbFNVKP04JwwdKUsvXnTwKXPOjs3 73torfqfBwxWYriuFVFVv+IASJo55uI+IT9zjnUTw22qACrGQF0QoTJWznE8p0joclWyINSXLfAR 0E0lzROI5mUjxfQ8DuMuzfYlzmvuC9IYNDh1egX5JB8tgxh7uZ8VOB9K5Pf6VSlk1R5A1bP7FD0O Kw1negyE9jZFqz5zfRd5mQCiT/lSpqfq2ORDkSZjfgTcsCm7MOYLOWJK98k1ixAXyCWIJ7TD0ul5 h32MaQ7Z4gmGwRyqtxCEHkuV4SvLQOlx7U42q+Yw/WYNEmvIsEP0fWBTiGya+9Ik960argvIoZrs 7Wsmn4Hu2zsNuRZKEo9sMZtMypTPz6AS/qMkDhgA7dyOL8zQ8HFKjdUAYbDVR0GTkpY5i2xUa2yf KUHnyxG/5O19+PW49V4bo8ChS5bL40+CqQftPzAm9ave6ZYF6g52gN2jYi4aW1qqRDxc8Mwf/Znt df5q7O6QVa9hQPJ7wEO3KG+iQsgwl2OpCz2tVPeY1UvY+yLCaz4cOTHcay075waCjFhvR2fzgRzs Z6VlNJRvM9GMX6hpgv1ZzNsdahMRog1Pd6wzMvb+6JA94rykXvdSy0CIUWVsjTkfClSlpP40KBDZ 0BVvESURJGz1vAm5m6byw4ct2fw/fZu9jOUjWYdBH+l3VMR1R9Kb8CtPKBYFkiyqRTPCGiOIB6Ah 1bRJ+FIVu83+vMdbsxKRHeGDIgBYH96tZbhml+fS8zqXYx5KRsLAx8ng2tkYXcRJ721Kgma6nsEn GDwKh9CQdCDQIyfTv29p/NGWIpw+z1zpSROkMq2G956YCkOLp69TYHng8HNs1un1R8lAvpzVwoiH aDxEM1o0AgQeXgErB0iaCHKLuZBclvROra0x/3t1GhOJeP6GUHZPdxgSpoeuhHUeGrRpfMQRlfn+ pIN5PgYfwyCANand1eovWzqJDy13jLS2/aMMzrHZ9bYv/Uv1YzSffNIFdk5l4AUyCAAddsBYU4bC cCgOseP7vAkGnz3ztz/LIC5okfqiNX1lodnhJpE5/OgQcei7oiOq1SdPvf1YLkE7T1b29W+1vd/O OsLvdpcJzDSJxozbXNkIxASmMJu+T/yp7RzuN0imJPzSW80cotvRIObj16OQjiBQKes7XTlm4bT0 TTNQJwrW3uhyrvaRP9tc6a+0COSTjVGsN7PW89GDAKnNWDvy0KvD18NLuoOUamjWvdUP7dQP0l/u sCXQsmU/XlkqYXZkcaHxRQPhBzHQFZw5poC/ojnxjXpLOzq2V2qTdnpkE67AexPyoZRrpJyCfiV1 3j8LxIXA2pUUUMQM2e2WuZ1r735yDmRHR0mS9dCCKCZAB7vxB9TUuEOgk5CnIiWr2UIG2sowwvE1 DgLMpyjp2U2PyThAHCm6+XyWW5vqABbqZjAxSiPPMSibyN5aEndnH0l840fNWvKaDLzCM8ZZe0Lh Yeix2co0MBFJat/pAPXCDKnTvtSOvMF/cEw+EEvOH+PMqWtLEPO/oaSeb5sIotgQI5On/B2vYSBw Ov9uijXFHm25uVVmUJc2WHUg32+51YCLCoIJrvJJJYNtkb5vZCm+cWCyVJ7Xm/rEio5T8bjjvr4l tSe2AfB8V99R12Ul84K159p5edDKegwfoP9uC3H9H5jFdtvkUReaBkHcN3Yeptwbimng+AC6khHl j7K84WgB2MfjV3rNu4deoVam5haVB7/8Q/ALU7XzdDb71vvqZaisE112S79vQrFl73lyigHN+cc9 2onQN5E3iCt3vjFXcROlLO7K2InJtOsf32N7e409+o50X0cDxUz5OXvVeBTZFHiF3lPCGeHAtRAM 6YWCiz1FwILMum4AedRSaLHmZCp7hTQhMHqm03hHlKxzizyL5WWq3Lc0j7qEwMtFvnCiUm1JubiT 8vAdYQ8LVDDBJj/3RBTdBCx1PMWzFsmwcglfAqMXPcB6rdcD6wWwPlQx0JdM0p6BhGE87FcjoOuB 0BhP5pOi3GCrld5ZNLed5EZck+fwUS+iJ/bQw37b1SU6TY0z40Eje1E13/8p4/gN9ZmxT9CGxkU7 Uo7lMjPRjMSDXp2q3NNyyPUydSCnv2Y1L7wKhguhj0oZcR4WqXw9u0lWWUvJrK5t6S3GkWnTNm+0 sXmXkJ4G0uDM3kh0koPeX0ZggGWOEL8DKQ2B12OzqjZzBBd6LjX0v0ApVRGJFl23tgz/bjgvORAy 5wBNE/18CyG7bwVxR1KCJ/ue1pur14rP7SfClbNMKPqIfLk31WMR6h6vQUCICET5K5YzepTHpvsd 7v537jIYISUUJCLTiJq4g6jbrDdq2m8oGbABvu52XSXZpC3mfl8XWkQkOjGy9/FyBmE2D7KQPtbu jJ/Xft7lwi51CbHTYKQHwd4RKUqloZxn47l+GRFcj+H7KFRZFCgZf5pnKZMvgtYYh3OS/OsIDmQK IwXNtq/2wutdTETAiXS4/yA6S5WPRPFJC7LQz/ieKM+YmINc4oh9DX+Y5bM7GxLgwhiJ/wQkDm4j YJXttsCcUmjcMBBw1er2L2Bu+BuzeAi871ZH7r1noK9JQvqeJVEIGByif+mjLUyRhSOFiYzLBi7D umbVmYiYyl44pMOhnfRjDBZdri7zFpBjJncSGxNLpwDZaBSTNWTgdnGFB9yxdDyuHg5y+fRSDIav Fsrsnk5pO26DhcUkr7lu+9giQLgleJ1SXgoKv/KFIFLT5ZnKnILl5Vstwjjgp6VrcaMCBxqZK+27 q9McNGGZCMvhqLwxJ3BBYKPFbkm42KPDfsLQz3c5RVbgJwkqulWkS/+xUQ/PUEQFXXtegMV0HzW7 g8bOOW9xJQOv4IK9DzOVENQx8uMApgAZPzVXDwKIRlEG/oVou6P7b0qrQMM47Bsn4crlVgKAX27A 2lB04xNxRYIM2C4C0A2eQsQ7UHIcoV5buOvZI7/CL+hgxVsXGnJ9vkhYhMpYZ2EZE4ek4GFjrOGm EjYjFdevwLzrWcROkVWtykqzW+IBA8X7U4YsGZnMIZLnsydA+vPGE1IOaQokFLRHs+OHWkNaqoN5 jlnBt6WJzQMWE6UEzhglbQvsOOSUb6MCEPPREpXBHUNYUOzdnNZ+47VLdBw3UVWVvs0wllCGfRMn 97xIGvV678P3bV/6IBeecJ0a45x5kIa9XsHQnp/MLPe1x2OxM5hcw5HVuGAuauoDIIoqpNAV0WZF X/g03voJkoaeDXmgCzn3J1Mbdp6HsFnjNh5vkDgKXNDMgkPprn19wiu74+bRHKaBVKQfecg3zBU7 fsuoHuy3fQU5qbZMXqbQH/YoLOPuMoYCA6B0DEqS0x+Mdo7JXUkUYiI0gH/qU9nbnpFhtCrKnrTU /MUYOeMhRp+olyXOwj5QoPjRwm9MBVXUf9lVEnaYaQlwacEIu+3jCstxNYux/afuOB13C1gHhklo mvF+VY+JzS7hNBXewXqP93wqQ3mthqzbaJLFxHJbkfyFXdz9RPXlHKTyT6m55OzbNKWtzRUhamM+ 5RjvqzCUSbWHKhqPipBsN6x2dnB53fRBb9e6T6gj1VIZGEH3c59u6YZDRJYtYDuZvXDmAO/ueW1l CpCK3ytCLyovTceTPCKozhZM6bHF/wkR+kH5JvciRyGF8OX7qHw8yyovN0kq6L8QEseP1nHOvtZU xANLGDAOEmMsgO25h37hcmEN/rccrKueBIrIrNlCJ4njswBL1yBVXJ7VXHJh2mIrtRZydW2fygNB VFVAya9C6m1mc1KwWQkGUw== `protect end_protected

bsd-2-clause

77d65ea15c36bd598f9a038385e2acab

0.938218

1.876928

false

siavooshpayandehazad/TTU_CPU_Project

pico_CPU_pipelined/FullAdder.vhd

2

728

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FullAdderSub is Port ( C_in : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; Add_Sub: in STD_LOGIC; C_out : out STD_LOGIC; Sum : out STD_LOGIC); end FullAdderSub; architecture Behavioral of FullAdderSub is --------------------------------------------- -- Signals --------------------------------------------- signal NewB : std_logic := '0'; --------------------------------------------- begin NewB <= b xor Add_Sub; --this line is for changing from add to subtract. its add when Add_Sub = 0 otherwise its sub Sum <= a xor NewB xor C_in; C_out <= (a and NewB) or ((a xor NewB) and C_in); end Behavioral;

gpl-2.0

27b3c82e325e959f316a4ef934c2b3b1

0.498626

3.772021

false

cwilkens/ecen4024-microphone-array

microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/components.vhd

2

77,934

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block NCnPn9EMfeeGkNOZHewsk2qZjbTkxCAiyhgG7pHWLqc2/977+UKlUqmmzmiUQIt3UMbuuZNtFyNy wNAW6QoPkw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fu6Zvf3+vM3aj30F1X+kRlfGyKq+lu36azwkAmQ/sAgaosjIVnGuNPUqezfuzTUsmFODFsE3ticq UZD59nfmPkza5fxdJXTk8JHVsdZzYh/7Z+niwN039ic1DiU6DrJjV7OU6aSS/+FS+xgIBqumAVZu fmnOhHvUNy5Vqf7e/Tc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ou/4ZMNrjfjESNRf3k5gNrbFQ6ZZS06x09izPEG+Gb+4vjMlkQgfTrxxDViYYIuIkGJvNZkhOq8c cOjDPX3Os/3aon/vqyPkgGNOGoRU9d2wLMUi01z2uHKAbnX2w7cmTrGWDDOxkqGhpc58/JwwWas5 ZVcGa2yCq6rK4knf6BuRloi5w4Yv2RL+WRJk1Blv7BlxtW2er4THGlE2ndARB9RaukSWfM900Pze Sgonqy+HCkwzVO+7zwMo6H17zjhc6ovcjozMnvzvlGM5ih/H3/n3uDC0hv+yEAJ/tZrRky4/j7HZ DgwUPKPnCA2KtARPPQAbkEzdc4TO7A57PEBdUA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4T4giQRoEvLDG82I3rVBwAuv3zlXlryL2P8ddyUrgGgIqBIFJq41WJCeE8Zy7Kasxw+AexW2ZYvu US4V/jYluC0CifBp4JV4GSeM4A1VlmbGhKV7aqSjjXdlTUFCmoozW0bXKlA3XugyA3k/u0GWRZ9m phOZ5YXCgLPQB+SmxCc= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hxCvbq3L1ht6tJPA8Gl/HytlQsz6C8Tl2nQ7RXP2Rfzzc0ZB7CiJ1A7jshFp+Ub+fQkd3A535skn NqOz0IP4XzdNaaX6x4Xw7WF3elmtbjpck3LDefChLY3V7W5P6STG7D0fN4EoU2Wl3B6+/Qks19rW sU+gtK3inD0okvDoku80j3sywxOCgJBkKaaP+yiYTqvH1/DkTSLyUaMsOnwfbIH8mLn+BxQ91plM fZddw8yJbLCPBGvJoguOjdsntL+sBpErBZ0iFExFZ0KL6FCf4lw1n9pMkI9Sy530wMUO8jG2sw1U IUN9voJbajwjfjBaeIb3Q9zk+P4Y9KzOP8tSlw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55952) `protect data_block 2UwaJ1mZXkd2cQop4Rg6tMFNqoJQIeYa1cfyafVUZ3Q5XPyy+HyAnKtfvFr8CnwgZaUgLQbPnDIe 7yepapMkvEcK5iKDv3kn5eNhNszGFfyRZ8Xy/B2QqIgdM+VKZdwPKIVqVgitpp2YZ2ktDsU4xdNi RKC7DeiQPbScpu9M0Lpega6oD8J5dOymjtjxFcBikkdl4ffMdFCSCDPf+a0JvOtTMTBnJhhdxTfL 0qMLhdX6+y34MBlvhN5iVv1GFzBx6dpIy9fjGsz0DXX+Lf74CP84jbHQn0t/H/oI18WtVhUYkvIs LwWMqeKSUU9/Yg/J8xsF8PYQI2LoUFCGj3on2IbA6zaExc9k8kSdH7VYu8wI/cA/7Oo1CCU2R2hn urtwWSSNNdXbmWXfLGefzqiJNzPRLYdGiXzf4dWFj5uLQQ9sgq4oEtD+wiIKLDF7ZhLIgdvDNdl8 lfetlQfWdnM0VGOO3jMvE42pUOKUeRLLAPquKQeYgr9eP7YrxuVgIvoiejRjaFwjn4GgsvZzeaF0 vwJpVSQnkIB6rzBBvkTKT7cXdz3GKDkkeCGCOqLYd0w6fCmN/Kjvi31in1t0KJNX2lVAYCiNMWhw /4cX/cZUQ/S5Tz6tqApca+IaGZO/Jq7iDl+E3qHWq0zL31LP8yvxmFB4DYruv9u9lMWFguOiZpBX OG2Rh/EZa7zkqNHGjqdszSJ8oByhj3s5gxBr146fxcCrxrkM8AmIZY6juoVNbaQZ69wF5wT22xWB dKDwUV3WQffUo9cy32nk1FfUIQ/Tohq3PRj0bI4j9JGxE8+sPHfnEHTo1KLOjLrC2fGff4K273Bg 693+aenFRjPOKy99+Uq1fFnANvGTfgRFpod5D2VsO7NAPTpeGZb8BB0Lx7t+6LFtC1e+W1OBDetd 6dv93nNjtw4naPMsu7Uu3BUEZ9uv6O+QXu9gpHmhTOH07ydbv8+fPlIdo7zazq8HpyR5v3MVjv8O 7pNp3hJGNVDGKUrNj0o5wsnTlxiWMjyL6lU8XoFGlrx3iJb6do3XOzr4ngPjRCl/ROAm8ZgiZNiC fDT+EjfPTOC3zTJJ55wuzpQgixwF4x6X2Za8lziQ2A6+fhaq7PqXRRqyT9EvSy9vnu0+Cj+301RE RhVg/xi1N81LDf01RZr9Y6NNpmkYjAUXwFihMAW9LqVghLzfupGviE+pxtYxCE2/PhYlISkoQANo jE9g5nkhtOCYGOUI+dXDP5I5CDRtpFuiNLPANJyAcF4i3fbzGsNAes/49dno8BNvRCdhLW+U1SZd HHKNu61vLdZmBNe2ALwU4KDjsBo3EO3eGHl+7iAakJ5A5V3zPAkiuvez2O77rxUnRRCVEcPlsQWm oXOv9btADiS6s/YYGvidEdjduSZyOFBDZg2X9J+xVkGX+LgAl4RwXOKHtrcESnktjPNdNAJt051x OlzDeC5xLX8X+KOZHBX73nb5QxoulXLgfwtCB/c5he5TshHSHYUtPSNlJWhMvb2b7DDpbNRJXE50 IWdM1pGHzuXTYXjGsUqLM19FKOfLV+S5hlWuSEj2aMRK52JVXqJbwAAqAgNQBMYu+nzO9M54jddX Kdq6w5vUL7FSelDlRf6EnxtVPypKfjGKBxsJh/5mzMiOC/KfYeYtHreHsbGJ1fJ/V7+uEHMKc7Fb ijCKqZQO+St14mLJOIU3DHGSLn+nyeUdXoV4XOqS8M3aE/NTNEhZyNWZLgOs+wfQQ96E2BCbjSyU mscbjUOGR5crmAx6scIWR4dIAF3PK2y1mv0wbDsDMG9GYi11Shc2eyo/Pj2f2FAtxIRapCYQS3Nj r2uio4hJO5KYeh26FAWWAmiGJs2kcFhAXoSIlfV9iCcb5Q3igENN0sMvZpMebY6bJrRHVxlMxPdu rgzjahUNs9e6BMSulqTxnFJSqPIH1E3vqYgPmhQGxkURQ3W2vNTMj4wDiN3CZ/lurQiHWVbg9QGq DdGafdutC+00rrqaUt3fqs3KT0KAUhbbj4OdhwY3G3Y2kgOw9uh9SrlMEiLHphXXpwuTPELPc+LM ipCdaV0e6Lg3xC7rNTP1/DjnPo2smgmlkoVejHq8NhVvvWdfiC2gr31p2WkUoi3ncPh+a8DCyiQl udBTT4nYoyP7+jm3cbxDmxPIqMaiAaYzayQnh8S4LeyHgIximWwp/ilp1BhQyKYu7EbKt8j9CPMs BPeMbHhn+DQCV9XK5fav1GvCpw1vSI9UlFwHqpQh0kfrp1Buv6xM+N3qCy1UE4od1JP4+UUiq+aB nrngL2Ypz8KpCmKF2IhiOxt6on9sCnaZxcthTAziyWc100IWgWOyp3aOiXFgKE/36ewixXv05TpG ePnvLhRpnWS0LDDPzeOr+vZ1iaOp/UEVqJJK+73yErj2zO3IBUTKCimFhnq3RAs5PDERqrlmtyp+ jdweV0pwFF9HBGDOxFw+xYYf6fR80KBM1qhS9quWKJULAK/OEfd0d0M0R7khl3gPJJNelr0j9h4M 2gKsIICH3LfCJgPSQYjPS3WlGrpqx7vB94En/ir2gLfJs2QPZen/81bYHtqB2eJMOEIGDTCMKI0O NQYpWCXpEkcFX4FqOsC1y8tz7qDsf2jaawhyKAXoqrQ750phd/9XhzcBxRSpd6UA2KhNZ3yuYQTP EDopjYR3j7hs1O9sb15MkntZazLws5xlANcuItHXifbg6XRR/XehF7U8Ero5Ga5MbLHOGyQq8DlV CEnsSk9aSPVTCiC72oW5ODBj0h0aFfA9U2nI1GBvPv01M6hZdz3GJN7pw4k9kbCn/SyHhfEw+SaD iEfJ7YxC8kycKZY3DBXlqDkwel6z2Lny8rR8NBq+fdHrSc6vtnL/vTFEftq5Kz/jAjs05oWeJiU7 ++HgZJgRC0B5cTkVeHaefTaPWJTFr/ql1QTVIXgVk093bXcdvyWCuH1xYyHCuskfLC5c3TpS/2G+ 1yrXpgUtHB7FP+vXFLa8EyqirX6tY8S3EpuWvORkezre0MsKN5ls2RE9pzzAwTl/AtDPdVO0PwXG zl9/eZ61lUbvFqoPAcg89v6C+SuVkDSuveqXhkYfBCaNoUJ+g6RqIDZRcLWSa+449VXBzpxjpYzv LXd0rmIvlXborZexdz4kFpkrNZnqmkCwjmqfLaZze6bAbaMUOb9tQuvB8FQoNjqdHPoOi/pRO0Ev gBq9YStjnr+xI87Rpqz4MUoBSnxZUYnJBQIeE1+G0ZnGQcrBduQZXIzaXy6bUhXaMRBRaTQp7ZUl zpnaligqlDxcU29jo5eCOPWLsLrPwsJAyjtQcQzJGgo3YZ2lovAHDE9F+IHSITU4LicfFOD+1wgZ 7P+PdJiiOhplqgWLAgBtb0AssMDadjNejWpwAI0XcHCirQJndXnao3t1AanZTHw5itLRXHGPxce/ +n8t5mfDt70lj7BZp2wyK+OLjutju+eV/vlUTYe+3YC9ZpGmEZOPLeWlGIuHpvZiHAQs4LFo2Ta0 BYmauWN1cInCM1LUO/UboyHKpSIDe7QTgrPkPc7b9m/m8hUNI2Y+2oahRlxK7uiX4Wk1q/05WftU hf0uazQ6DnM/pttnwcXLJwR81k9BFYXZbunaMCxtBzdTg7wKJikZ+yZNPkDFsTyIvmgPpzvDP1AP I5rPvrxRnEi+C4K0ag+TJo9X7qDcFf4Kr+wnUp3H/HNM9twTGhIx9BQ2Ji2Oz0FwS37R1CZsPPYh RY+7CnHy15HncMPY7HrSc7RXhP5YTRx1DOsmIEAACz3fudN1UGnRcX20SI+VZXxjo+OrVJv97hJz J7higyUWK6MhNxOUzb/Ae7UxtKnyfw9l7uucJsECBYSGTVoULEmncGaxpsLcwuOVtlzCXhOoTvWj kXz5T93qHTsxlGe0mTrLaw3toqqmJqgDb0K9VyBYgB7nkqPu5JBakxiIyZhiY2eiM4xdnZSfbQL8 236jselF5YAtgqDdB82oBsoLbqC0EbZI8TbPAQOG7LQgdwSPM5La8czZDGOx2Foc5RV3+u+UGcf5 +VFTwNB6m5N4AtttlOn9XyyBX6AadDg4uIreVG0PCueXNwp3ZFAKbgVYw2FUsJ+PuaGF5rSWseGQ h+6tfbHBuJcwEfM2UBbUWhdYqk71VtpvNSbsamVCI2BMiYyI39t3K8FopqIjB2JSE28gEOqNkjPH FRfoTCQXykDmcL4cKwlhzYnrH73NjQL/MJ72Fs0Vi5K3VnDyhOV/ip4xWN7ZAdeCeV9I9YqP2Ska C1DDVe0sEQenbfHX0aCOasRlw7YYGxI/p9NVPknUupyaM0xIj+lerpUCM3LgKVhTjuozVMRpyO5o b8NFRr+lsDkcYI9EpYoEcx3wYcJZbu1IcD84vg4FUfWXbBxUKE8DcDluZqTiKKZdM+u19jhjNlWz GOfvafMsd7PbTmTpD9dpiV9p0yMb4HKVTX0+o7Mj68Y3mhk7osYbgRaFfhBlVeoXjCabAGlWeL9+ KXW5C8yM/PBQXHrfumr+7RDKfPOgVtPx8ANsxckzwxq7zMMHFnCw625o8TM/TQ9VUoZgBReeTC4H x5Jb1jWp2AXG84gJ+fIu+d1UHjiZEyfdyDB8Usv3aS4jPBT7c2NEgdDvK11fzUB3Qt5hBL24//rr O1B8nEKS1o1L3jLrJooY1Kn+aLVdQlDGnkTCjQofmPpOEs8E4ebfAH3cPb6kkgcwGSM0R3/Z6gij nDNiwCht0bfB7M0jNr/XgOzTJSICa/Z5h8vPxLSngEGDBDCHYSqIdsJgxbfmlmNXrKDOvskh8xnV DVE9IG/RxqNVEFWOIMhBmV/iWTssXpOYbobSBhX6vdmeCpOo9IBeEDNfe4KvEPaAMpvW+FYJDOY9 zLryyY7bCIBFALazK4EVLLeU1TLmaXlDYQym6ga2g5oqLP+p/h8dFKxBhmHWCj+ybAUjsM44G4ji f1uXNEK4mBeE3XEFxMQlSq/yAzyF1J7HxcIs46jhl29YkraQaHJ+uE0U7ahGmZZ60hco4smg++t9 BsSoYn1tOU4mf9TNENT3FGkLzFxHWQoEKqF6SCogBoRmaBzW6+LSy4OG00qbbzkoaX6kFnTxJMX3 s3UveT3Ow+IakjVH7z4I5+M/wFF2yHG6P1XJbTHpEK/rsR69FOVZVdcqwwaMXDi6mj2H8wxKLeLA NPuod6kKojaMvyhdqmWHXx68yC3UYNdsEgtZnhvU2hmlkY/uw/mOoLk8TW9y25syrDLBhwMIOp0A fslDOOdKjowVjydtiEzowSUyVzohxDTi6tJb143azzmuiauG1uhVjAKReM+erMVpTeti/CDxM/tI YDeWE6Z7NAJ5itpeYzf29I3uPkvIwEzjUyNUy0nH+L00bSYYYhnJEumNMwCrlOlxvEBnkWcjXq6k LyWWh38JIxBNCRXXTc8p0lmhhdkOizj42+xLe08ns1J2p5cpzoVQpEKdrvik0OJ8f3SDTeEffat4 vXU9d6kAZls3E9tAs0JN0b+Nu8/q1Aio9Az5zinyUwBUrTQv5wboibv0pDGPjnupVmy05J5JEv0K nSZTamgbyfFBJ3h2IRACIKWXFRmwtC+NJgumkzoMVs3qitJwzOWm99W/lIjUy9/L9gxUzU4GZdqR qmbEsnECoRGxdvw1U2lFE+fUyQelNdffGapvfxlpTCpmzc/rtu8rHZxSpAxWqfCbsLcYF5x3wyyR taMdSh0PUttYp+du+N+mo+KQieC7r5599iho5miaO2JxCtbl+QFPje0XKmXJDMMdkCILxKVeoHvs EdCbAAPSfynHR0/NH/WsbrrRrZfPYi/eWSnPhWK+2q0L8ENJHiI1SWx121eha2+Txz32wFbFX2Qk QfWNnBsWgSGDXuUNu7Ht1dte2hLbT89g+q+8rhrEB0fX6YLHiWE841lzH6q7hTXcumiu1qi/F0zZ QKBURVZMhfGhL3Plnf3RLcn9HBwxz9wExpqCVAXQDRRKMEukJb0HpjtBTBVXGNd7BM/wUqzigLrz icJHgvxSdEI6FVzCmVXN1i0s2U8fPyr7pA4KUeEzlRvreF6wuhthi5moT6yLoz7vFR9stXZBNS/A Te95VoolM9XydHBKFGGgzeeaL6yPFMk0I1qkkm/mZwcvZEBWzXGnPp8DWWwuhuMY3//Gg3J4ePHw bRkAOaD8Dxc/CLeFMq06y9Q2JMAbQ+F3EE+Sx/RB4APvdMjC3vs4HWGcn82YU7LquXAvSYXwefNA jhL3yJJEzjkHZfnzaQEB6cCWygLicJaYHSWdVqO+FtdVerjF+uKLHJLdFpj+d05me71Pq08ZmLcg 0lXH0vKQt4cokgtt7qm/IwYr1elxTm/7fVGSiJJ2VH/XydXgA5zB3ggNzd6gSsKG8ge+dLbmn58g bXOrdh/y1uI4f0Kag9+VTe1YTevsXkaa4CJZ6EpQw74Z5HHjMCTLByjMHS280ovYsDFH3qvCCQXk apYf/ziSRzgQeunyfTur3hA70QoOCQ9+XqNExcHhVULBr2gbcx07Vqe/rv+XevNPuBtO085uKbJQ Dagb96M1GPvvetOBEp5sozkEoUux5x2u//smmpe0sf2OEI76lq1mJzvQNl4HZXaELxWJuOJXgpAc zN1JVo31oicJQfouquZlIQevBa3ES/pzgumNXC7Dbk6SYg2psSHPEf3bONJf/yEQYwBa2jUC790q R+b08C8xKZM5v+IsdAxX786wW/TJSlvmXAh0ax1TcnavTcqmpANYOGNys+eeAK1vs16uGe/dlhvI oFvJqadcN0KqRx6OXr5eesNlHoRstJeN+QVjhU+Vj0G5wPs5WIiN5XrDpbm2iS7wN2LpLL0r/FYT vyPaxn1wNmlYilmwduzEY2Ar0t+uwx+tZbFHrxbZ1LwxbRNHJIJ23MH1KNaGkX97baFfkr+qk+oy O13WvdgcqiJcOkywNifMcDYWc/qr/OXkcVunz5Jy/9g/v5AwmkAzPepLh6MpoYf9aHzZiviFfOBl fFeLBXGv/+PvZRxcYGPFZPzC+9rdwXtxaC05gvhmUxT1TbfU9b0JjsTqODKEBcHrwENH3cY/NV7N iw1iyfBJmEd/KLTnjyMYYYvOsv+qSppKDqhcGh2De22q9sezH1213imYRyc64ugynugn35qlj/9+ 9wlfoKsPagtwkXj8sKi/KKnqzLQtNSYmMG/SHx0AhmN26Xj895lfgQQlfpr8XFMReEbtspLxj2SM dHCMh7ITxiksP1uDbSDFOp9fRpGsR/h7sd11bIh3gt4pbUspgSzdQogp4hI/O5SngGtfvZ45ugW8 Dr8KaNX/7T/zWZs+lyzwUgtACV8wak/ZlGRE6yYZQ4toG8Piraskad2XhjziVA2vNZiNqcUa41pw DjlaMmXv4slaXHZb8ZC2rL/KyuT0xACYrJHhB6TtDTAN27KGHN9Re1Vc3Z+xCxPoI9T4coJxUfsR lHUfhR/tjKgs8ThkGVuzRNvYiedj+59J8m8/b1u5d5svlZMgMmymZ2bvCVKmBiWzBdLVqICySPcy eLMuBkOqnQWZVlCt4qN5B4ClNeVqRPZKag7c4SnvyNjCHUHp6hTZ99v/bLu5XeRAQwlIpo5+xKZa 925A9KKC2KYGJT/UHqlwOPcOuvPy+RnWeKpO3+rfcK2rTPN5CIMOk9smUh3vfpcLbSBqu7KZgKij CgfgL3+R3wiTaay0zUIuGVs9BOtGeeoSlW7Sft1xSgQdOpvH7m06ymc004FiH/R9PCNjzEVHo9AA PGZW0OpzclpBhxpQ9ODkOI33hoSA4+zHwMDJVOky/EZYNxP3VFShX1j570D4JzjVu3HYrK3ZFPZ5 KnOOMg3Hga3NaRPScxTO/WtBsTFuoI+h1PX9b5xweephZ/dszLznvq8vX6Qrrv20fNx3i+QLkmei YMvmhPhvL1pu/T8fD5b/hDENZz3GL+XxUYwrhOeVR8sJGmCwYp69H1MFFwAcpsPtaP5999Tuuz8D cZtRBIaOeg4lMzezAw8iim2zaTdcHkTEP5UGFmC7ge9fpRrZJJTf41hWZAAvvwy4tcDw0k3x6Zlm DE5baGhK9iGryt48pXlWnGxl9aqANEnKowSLrZ/s/YB8UecW5zbOaxN3iMhPLaG7maXf4np2kIsi GX2okJC3r0/Qqr+g8ChrN6yzNwd7OYB9smBu1HavUPSG4Ngh5qZKBRdqgEUil5bc8SxkKDfhIcOE aPM/A5PPKYSwYgmRKaEr6F/e+KYb9WP6663KRjZ2NgME5ocAuu1VFMF10expV2BRQV9Axu/5ibg+ saPIci2i7FYlwyBtcr1ERUZFcLQTI/Be5dkpaC1uSwnrTYhA6YCKtfmNGM1WrpcvjAWiTVD6uEy8 whg3qy+yORphmHFnGlqS9Fw1ZHMKF4GGo3lvFvX6T6qkQKCl9qVJcE3EtUt+5tFZDWNU440qMnIU pOlnwCefWxuxi8zXG2nRiizuyux2gYScAwphMbpYH53qvOROTbHg4UXjIllcAnFIz1G1sSOExCZ5 c7i8WiTyN79kzZNp6rFSfjW6Vw5wSezNEhsWIci8siRP95AYb17RhbqVOLjqk8wIjGJY8VRTG1z5 qE74JViHMzXhGKNeLPp6YUVBvLw+g3gkP90TBNFYSCKweU+J3+qJnDdoMVLPIEL7LgCG0AbD9uzj RQCGas0UtYOmvflUnWknb3BuNdoweuOBwktxD7XlXm1xhUsw41TWTmK2zoDR0dJcwFmFaen+1zUG NUnnU5z3t/kg84JiAhjVt6Ezz9RnMs9/mBVBWK3gLnpB8IesEvPnRqnD07KsYwcWFwyxupf/K6Qo +MsV8fh1FGwpS2jALKdUFxnRshAtkrmQhjdwOBOsaPwi53kx1hdu1ao/FBdFfOtbbmdDPWLsqnGo sH8cYemgsI8jR7+6OYdyJlhxcbGsbniY2sMA/WLRXpbJzrD1smQxZ4MM6dCeeGEmKaVVY46q8ZDm VlITni0LJ4PBlDfW1lQdDYDkgdr4rLI16QUCHQmdKYwIfe8Of/7z0lJbtyyoC7QMikytLYcKsDj4 snugSFH2ky0XX5FopfFD5ubSwVeNpGza1PUQbI5lmodFTqQXvKc09SgOLqBdpmytNpHBJFxbwNc0 YgmtMtXsgf1g/GKQe3rSY2kOZflk2woHXYW1yswiinxzABYRuzUF2JuGUgpkrYC4Sox5yxxVpD/y SafzMXUbfZXoIMulgEQmUXQ6xyREqfGA2YIvQHtQrQMUyYND4lGVYFrttp/fieEHXA3Sebu8xJ3O jZMfL/JzihlrsFagGuL1KJvReri9bpi5dq5hANxtI/4a+BYVHaKshkXOUFlurfopFAjfDksjH2MR uLDY6WghX3pRuSZ7u7B2gvkOTItxWOeT//AdF08uw+Hq9dpOPe7rszv71c3gajxEXz4B9vmt5Rj8 qxgak+Xl7F+xcNMjooXHJgOrrWiUty+fqs+bMFwjKhltiFeFXCn4BWKe7A6qTbkhVf4IMFTo/Ach D3Bzsbs8NlXPGys3Nbvdx5tFDkwHt2upeBhF0qqb3N9tY353EaH04OGew3147R7w+pS0rfEbaY3s YAIKM0tfOGz701i0ozTXD5nlyy4McLotnvKHk0VGaVn8I4WlNivBuBGEl/B9BcPzHX+A+uVd8KPV lRV4AiHZMXM6Ei+7kQVNPC+zPGQjkfSiVo5SEnpvGSBDELpZRqqjFIoVsbCfXtUhTYsN/PlRl4B0 XZXdYOiJxCEW49sYnnGR8/sw60QCuZeqrhaxN4sFrqwsTfeQtsszCs+v9JCMqlPdBv8Sc9ArkD7x TN/A7FDYe4yfzOUAVEkHzjTZ0esIfAP7TypdFcQWklzZegNxaiGt5ytyx0fhOw9gSaKxZ0xRLBoB mx/Z/4phKcyZxUihk1cVhJMiEwC/TifmHI/2guqrYRWstWYHAfgavNxSgc7lN1oNgIQCK2h3ASiI GXUUjKVp6fauNz7n0E+d9ODl5KLHe2HFbfmIf5xxOSrf1Zly2Hw1uRwpc3nvPEIE7+p4ogbUJA3+ RDsV6K3p2ZYrKfM2MNgf2rTof6bHD1BK/6MCbjVmZ8FP/oZCfcLLZq9jLc7xVsmPMMk94zZJ806a VUQ38uXdr7B4ZkmvsGYCqaDk2An5sWTotAFAqL0VEp3TZQnR+JRAgLwwajuj1SU1e+GN1l+ADDg8 bC3HrCgDv3bYdIryFU0S+MR9axKALnF6J4Bc/eQmps34Qf6Fuvo25vAbcyFYN+PWDPu6xhuGcDdU 7w1O3ypU6O3ogbmOTYbFu9afGY9q2mc9m58GjMAj6GYswjydJP0g9QUqMyzPx5OI4XZdp+OwQIoL ZN7Pex5s/O9sgsaH2q5JS5kc8K9RAc8N7r2z7hT1N2651eoBtB98yGkIpzmfcmtdaok9Lh98pso6 wHSB01HwOE1WTKvGBh0gDN/4JphtpTDQfsXWlz9iAPfIoSAypB5LMVDgk33P5vXmaC6UtFFJjysp RPVJJj37FM4Dz0OGVRWxMPrxuleIXUushxd5LSEGBIz8NsTIqxkbpLEJyhEP6Qk4DIoevZF9SWP/ qT4uCtJl0EfkzzqYd2nPu/LXsS2Gh29pBJa2388Gx2PRahzMZQuUE9GThTkFg3U1FGUnSzDSqVLQ r4v10Yx1Qi4Q1xzMDg4DB9XIvvfw932VCtvmfCvZ9wMGWZMwqcLSKPbmFZyxc6PtXK8ZrIxDrp+P 91BRSjrwtLeTm1UizCQVx47IO7da/acMoexD3mG8ftuF7Y1D1Iv2ZvOOWOQvXG4JSKJoT/wQ72Wo LL6Uxj2vrhpIn30Kf/cStxwU3732Xv33BTTNKUeGz+nYnLZnePvMPXGniiHU7w2B90IKfNnXfngQ eT8Jh7XAUfq8kbdgnrxCzjLmGBYNIDBAolJMhIKX5kv0SOK+0CSfATkkT41iWFpbXkgLzUrC+XTZ vuvERYEFeXthZsJfEKGnQyF2P5ypn99cElf2c29RzBx+/rI0eUtrzpH1hxe7O6gjN/LDg/C/vRqE viPCNci9iRRZgIGpvtXUdpfV31Mhj8yVj+F87tv55YEReicbYHRXOT+QpT0VrLct6c3gbJ26xnmS aJaxL3zCX+4bQH76IDeQ8ekrw3rPQ8iJz6s8UowjQgkGAUo9r5RvSfTwCBzKbdaTO1ZzfuGa5rN0 Hhe3zHJEsW29vxuaEK1sYAWxxno8JySDc+wY/VUbwtOfoNIxcY+xPA7SVWylOWzQ318noQODhz74 a/Pg3eUxOGXEDPI40CSkddjWTmBTrbAV5vw+MgFhUTS9jABvBjrunqVf2cPSiC6RVgyFl8+rhB0D RUYpyC0HGMJQIn1I3i6ZtxXOdtrAv6bP4HmoL8jsE2AKCcQadq5Km4G7ocIt9NaaQ4lE23eNDas1 8CV25GHjxN1D6HQD+GljiVPZoi6DRi3x5Q7nnEDgYPtc9734B0OdZIL77nh8eJnC5J+BO/BpAbu0 ftxtqLUZwvCOuhkO3g6RCmu20YXdVmS3OzunXf9peud6LWNGVqWb8iwOa/mfusYNafMzL5J8USVj Z0PK4Xjn1nAZi3DupK2RjNSNnzxHdIMH2JRRPrW1207UdWqzrSTAW8Jn75mQ6oCSl3uGSOr7WZbk 4LnDz3d/M9Agg0jqgoGVsEpc7ihqwqDjriwJRkUOWjT3ETYcYEWI2LdfaIL0iOfPWLeHjIpAaJmg alBD1+sM5sZWYdch0hYzLXC4AN/g/S9+GBvjNbXt+E8XsLc9EjXaPPkbz3vLGEMs7pDfLT5cZ0zy EFH0jxUWNvVTrTD9uAJLdMV5tVExo+tccshQGSErOtWvmtAHiUuWXqFeZV8r2V6gAUuOj/bhjrQf LP50YbecXhQSKTbSYK9/HFwkga8daKocZW3dbVr0z+7Ku4vdsNhv0x8QygSDw4Mgw1sY2f4ArQlS 0DlPsVfZmw/bT006Lxm3SPtOFxwW49NjNJOsoGkCGpohIEWNVr+p61ZiYQA7UgcTxMq0RwJ7hKsV Zt1Ui19mej8m2mNhtlI4w/IqKg37wB65crdyIMdojea567GfFqTVoFt6hKf7dn/bpWIp6kFVJJMg GALAv5FbyOzult62C1Ri8epqUPaVzLwTKrqcqdIZBt037jxY3H/oz3vny4K7kKhxL/gtZy+vK/z7 xECcBVzHItTV4Jtjk3islsao6FiDJoHrHJr76+uk2XYDVAgHLLYvraWa4tiHrCvo7E7WFoDjTEFI 2VrzYHcQgQp7RIEdgILs1eNHEB6QMctbObAyJ/xxeoyy3Ng9MwV07WStISuYA75YITQuUgzKrhgs GvSyBzisbs209Z+gdnjI6WjycMuzwy4HR6rmV1jBW//H519dM/hbSNbw7jmnKAN4IHJMAtpS5K1c 9XAYAohcgWswQy7Cksh1x0uxeUGE/sUXsnJ43dSllswfmeT6lUoB7brkCOVBEcRT3xBHHuD+PCzD wqylqpCO6ON4fW4jCnc7NXY9Jw99EOlbNWO+pxZm0yBpkLDCQRsMezINjnvARML9+flzFIxbFFhp YtpgntXx6TIdISlRdy5TK9kyeeJM0Kdqy7BgKzYECd3BKFO5X55wb+ZL3+/vE8EbW350JW4g4Bp9 w/sAlqsmKmeztuBZZc+8xr1LsYDV73Cvk/Ovp/c3ANxG4yUjWQagfsNhlFH2Clwf4nUXw2xzZXQ2 iMN1DV4sHksA/f3FhnAlMeZYce24IBvvXM700ThflB3Ff5zLE5DbUD+oURKAGGYCY5QYvEC/gveI /td6J2UShqZkKhFgCLg7MmWKYURj5VPHrG1j5ceXbLLp+DmmgDMKTJqUMrrxQIpPuz0buxwSRDTq hTXFx1euYfxOvQZDEGWzi7zup/RaCo9iIluWnzuBqGcbiDWu4QSqVWBjbUoZe2A+jyiZtHWpQy9x w4LxNBud7pJbXevKVyoo2+lhaSv0GfrQLLxXhDhUeor+Ux9g/zbT6lZkyaKEsqRgcxD7XwEaNON3 kmujLEgFU1PRvfLU/tcp/rLlPPo3kFHJqPyCaIRGXvhS7APNyw3x652V+gMKghnTZnOLOTBSYHSU bECcJFPIZBZ0MqUFiESRiChAmybi20Kd6vYvc8esh606PPN6wlLJZCU8GvlDMODjYW/H8vPKTIr+ 8Q/Pha2GYBY8yMr8F5aMkHlA43pEw6I32FCqbI/QQJ2NZFl8h9hcihSCVLux3wRTZK44B5dNaAaK GtbcSMGcQdlaFUPvtInBh7xMurPmLE+8jBRCPvzBsNg5mHYFmq94WWs99IJ7BLspCjrZD8etbzYV tJ3hvS3e96hwJuwdeiGfgge5slxKX+LUAmnOPAhi2ESB0a7aU2ATfsmY74H5meyWxg8TFoB4SNmE XCNxvqwSy2uXewhk2umDHeyII8tUI/VO6jU8vwXPEvPh7wY5jOlGU5hn+dKjbduNCWcfdb2TOUzG LjdWCnBvyuvRgTnuMzp1Ndrq1lwiC3w8bqG3/08uxyNn+QGOks4CSd/aPSDqDTuPrc8D5eA+Jo2R QeXXqKulrciLyWcN+ryiijw/xK4DwgHRGLDMF4q7YP5asdKztRSM7b8WkuAwbBaGhYpkSCpvo9Hl Ex//EivAe9NkFfnQ8qTT/STPJ62USasyXl3TqLqSpVg5FsIKmIJw2yh8rVY8+XyiiuPXQWSmnVcU ZNHOSUezR4ipRbDcqNwRh1GnxxtTqjSrnL/ChjFOvnWvoPZt8ooER3ploCE9lQZ0qFOedcQp+lOR SDEDXoUdNF2wE58h1sEUliCYDNhXruucYOoiZBtjNFuyV+hJmj9STSQzBLVxXCRg4dzWnZgnEPQr s/oZK44jEcEWf0hklu1XE5QDdjR/RkyW73tjxO/hguo2V0lgM8i6T1nBex+l5kFhFeMmAgGYjX/D jb4PNMR9LKsG5kSdvX4pimlJ/DBrSOR1qfxYx7npHoKKp8KtGgfBaTYOGu8dghpm7KusnLuTmgbC pogVm42JEHMxuu3uLTKN28bGkgadJZcUIGaf2o9YSyg9nAGFHA/b6XxVbcHgcTSGbbxILykNoyzX 2M8gxMcp2Kqi+O+WR8hVhslgFS6PzS+iU6wUpf3iW+LLCXVcV4PAAK4Bzrc/M5vUlrK46vZA9zZb iiUJeQKvqzKSb3CoqH3es1H+KxUT5anpMdhpa2JpnoN1riKv55sKdKJFvCc+RnsGQZ3/+gGU2zC+ VlJstqKVTRZWyoT13W4OFaJ1KQAhicleSSltI8HgaFpDe5SAZKncjaqkA56ARVuwTxgespT2ckEB eQzvMYKuS8WrQrwxBsnaBx58BR/99anzPVshwb4sMhUHptAcMdJtqRLQ+zh/2saVMP+jV9ocbjSP LVcB0jGXc10hVrtT4N9NFYKQy+lZCqiATs94WZlE62uGQry5Xa2PSk90i4KEpVKdyTSlYFl1+zxu 1tNadHOC/T5HJt1ok48hfpQgrEoCsi6OccLaFBZGxa2IrJutU37yxcNx22T5IewWENTuPA85Ghf1 BmeGzz7Q6b9UuvBCcs3/LTWvkO0EmiT30j5MJU090NXWOLxHpAVHRKRR+R5WUYVN+zNQSRYsDvn5 5oi+O+WJ22InybZK/wliwgcJYeTTEepPfx3KlL+1o3XWxOxXwIJKleZlsUAfclA9VLi0+vuEvjYH i2hQV5lu0yz0GpszUIVrqpdGNi9+e6y7cnA7xA+Jj7bRE3lx/hgMzUlo6KdYQaFZnO/y5W3TSubX bUBMILvJf7a0cqTDm2HmZiTNs8lMI5MEVMvei4Y/zskwtO1SqZLAs3Lgj7OCHNixY49GIppcc/My iurCKorUPj6AbYhfWPafitvPuqyeDJZP9rnaK0QS1nR94jSXCLjWSHraGBujnYifpKYKkln7el04 S5G+c7L2Flvbi2+GMWEFsm40xemThksdvJt/N60zh3f4IpJd88sE0Oeb0FFi0sXUXQR11kODsQqn 6rOil4BvOBYj3EEurXdUOGGeiRZ+P0FcrS0sPMc5W3mz6uQ7XUewbJPZ4TRrhh3p1nB04AQEFwCR 0BdDcCMQRDE06CRMhwhbgCx2ZuN8Bi3jcWL/MWxNS0L6KyQ20TwgL9ALyLcz5HHuhmuUmBzilEKu OAsPsQS8CRhhe13BJFJnpsrEQPYMddk1CMORkIaCeljsplpF5s+R5qp9hyEXe9X9e0fRzqsyueZA C+fuGQzfsCWIFn0bvwOyHRCcLoIKqkm+f8puAcvhY0LSZBzPKMFA80KLGD1DK4wFCVYvHJLXNWzn j6FZ/PXJHbWKTc0J48JtQcftrQonlUyzvu1w0dTH1+eMsKPixUqgRwzQd/k5QOsugtAj4X9BefRT yP3UN+4xWp9Egm/vAlpnDbUhg2KNcwrZdhM9S3v2a7rshn+S03GlnZMYPzKuIp6crisrIW83YsQQ 3+S5n5EpWEPXPeij2accV6EYCPs3Xxu5jv+JlUfB/gfoOW7YpUg8V0XOt0auPs3bFU3FsHurorKs 1gENXkhfKXqZkiD0TJRhjyoAaAUYYoI8wtur3KiZYElESQpS3P1hH4rL+uHMAD9YI91Eqb6vz3/6 x8EGEzaGonwwYxysETH6UUHgAlV3E4O8CJdPJ2VcFXUpZUUOEg2DdHODkCvlmulTqsy1KLfX8WE0 zZjq1qeh0dkdf4v2v1gNExBfOa4NQSgGnC5FEcDzUwwZN7DEd6RkBXaUgbTf0o9IWGCR3NKKtNFO Xv0ecfm88TWcW+t7jT4Ds9d8DVLQsUQ0jz6zjsNjYtgoQpYJILviCGl/bGWMC7EJmrL/1lpHsiIV RQRX31FI4rCi/3Ia3Aiz5jGYMiJiQFHlzoh7HDun++JXftikU+WZFAMXddeevXssK2d54abXnvyk P0/eAtEMyPQrx79zxfzL8Zet7QQq/W6na8cHZBI/ABZ05FQsTmoLtxshsY/7klOZEnjI/vG5Cg9W q9ME93T1jXNQV3+7YgLh9aB8Fju5aB0XTKmyuyVtuhygKaKNpDj55/uxaQSwqPbWIGsv44vEO3tG XmS3DSnawFB6DLYwg8cYkM+Y9VkiLytpUaCCONYARx19+s3G60f7VRsdFxl+LPi04LN3v4wCjLs3 w6YCUeLQH2DlUfvxC9V6leveGR0lrKDsmIW1DAwOf3YMACdcnbBAA8UyeJhxbmatqZkDLTLfG/P1 dcxfvLrWsxH5eSSK6a5q7AhlQbmWUcJSpNBcMNaq+Q3kanh1FBvLhz1vVShhv4fICGB5iH/AecFZ L3Pt2XUOwkWmKWQhLcv1PxYLElVN4YwQhaxr9/Sz9Fi1zQRJtGxWyyushUod2i7dnx9P3F2GKL7E 65p7ylGYmsQ3tWXbd6Z3oNLVPwIbFfMX6Y1oOJ8fiWSVIAnrm1LW3x884YLLyZphR/zz9zwrhSCU BFseIORvsrS0L923v2/jYz716NzG/PrTry1Rz2LAV8iJ6mqET+kQRWOE9RdIkzA6gjl3trCxVPnd Z1CbIa/G6ncJuQ8BjPCCJNbF13sDxqDejm4J5d8UqvLYExpKDRxZUVg93Lfx3tYigU78Pj6aovjU j7n4mDQ8ebNrLrssjXGOnN+yw1GS+TYBbuW4H2fRvgAFuIcxVVs97Ehlbf0rjyEbM/HBbiRlv3+e d4P+Rsp5jiBzPCkJv226wF6r1rg1n4CcSZVhnySMVhD1Ygj8tdyTpnXmC5qfsmmEvRDtGRLrnEJW Vf+dBrVhCR0finHmrvNMuN+TYifp9XP3Vy0vy9f3vd7J1cfxnd/zqOmzhi3GhBhIfTb/YWJELQO1 we//M2EB0UtfKN1DEA3USHjd81U91OPgxzKI0xTmU5CJv0nevk4x+JAUomDHgNONo28mThgleqp+ EVRe5mD6t7Ql2yk/vfJ7z67R3NYAIcQzzOXMrnAGwBBQu21twQGSIyKTnccZ38grVnDj9//mqnog 1eVFLLRKMwg0I6t/4FGD6Qr6v0ylCxd5MckwXHr83XJ6/0WEdEQCZd9+IeyXKieMFYbYs0LV8AE+ DaN/0SWDgfdb2Q706XlAwfP0g+jskSKc97mqyMU8p3XsXuoVkMLrUoAhrx400ir2dqqiDS7YCKB9 2wQIkkYyJjyn0s+/f5Kv3OJyXwSohh4ZOF6WGglGowag3UkUvleXVcuc3DwrpWJpdedSrEC+j3yT VgKjVPs+O9dz99Dval5XaM4m2Lld22SBsUDaKS+YrWL66DSLO8DgVUAJJhA5wlluPYX9F/XEGju2 iW7iC4XPiDWFBF/ZLIRZXxi49aBHSMvrwvfClC/9mGRSJmsTA3DdQmXRX90Va0crRXrNbrmxaXA8 OuUYSHT47MKFj6P2UvU1YGkxdAVXt524ARhZLMFN1ishHjU/tY74pgkYFWKSwJfeimWWAHd3+WSI 2FGUFrpbdaDLpGOUP6t+xTYP0for01fRHqhXK3bMWxLcVkPZOFLX6QqlJEXIVHwHecpKO+Yxwjwf iiW7HzFnmSP1nJFWKw/FcbYX71y2s6tRtX1m50hX5UqXEbtSZQ5gSpMt8Tekds0fJ7dGdG24ZSwB s66SWa/xU/ZpF/0lOY62+jczdjsrMUPumPjLn5IgnIr940gFpbwxtu52X1QBw7PP1rprFrf8X1Am PfAaLF4APHU2tZUpN5Tb31Z64LgiGxO0R47yIbW72PMehL4Xk0zhS54Ny0PS/UHpFPeFqIYj/fvt DNiE9gOxigZmntHovpXnok5hwQWEBv8eYVgigCtdCE3HWozEPVx3nnRXcVcUQxDiq4uzAqILJugn EykE72lgpq3td3zgqH2heUUUm9Jr3Q8ihN1WMfAkYxnYjXUfcVoarRQCofzzd+0QXr7a2U8F3Jt8 +3fQ1xa4KOWd7HL++MAMtp31WcLOl7ZAuUHLu8hd1qAzsRu7jxYNSkpG1MoH03Tm1pVauwP8fbbS fUCBo3xiM68t4F3qlR3V3JbzDkVzEvqKkxF90rkfVPSAVvCv2TbAi3o/QrTEzR4hedn8fhyOzwLi haBriKuRNHrtdp5ZsTApLRDU1FEL1coAaYwP9mErm/s47V5Ava1ubJKBok5VIQxnGsOQ2rWbo/Wq EZGGLfDb2ZhyYYEOIxKtMLrY1E2UHTgsZPWkLAU8g/i2gzjGi7+cucEBsHZjg3Dkt4wRAkyT2u3D qM3JUf6fBsSUHp794T9H3lXUyyEzyyUGdzUsygcXFI9VKqNqng6yqeTd6UOKM3mwbKh2NYIjO3kl jIhSXIdM9ig4KLS1HKzNIXww6LUsswUuiKsXQTMwiPQwHnannRimLftLKvP1OY2W78i9x9UhuPk9 KcX+t2Vp/FKlcu86zV6c0xCsZAZP8+/HZA1PtwfnOdaFboeRFqadm5RVEJ/JkFuG++MDJCroxgzu rrxq7P0v4IhLu+Ps9cbk2vacKcvEq96DUi5ia3ytj7UI3lZGr8bQFV7AuRet81yvmPEnHpj6SKrN FIdqyAeXz/7VBMe/lf+afe/yy927Yj20wtf+4ygnVIb7v3qh8xsEZZjK0J+eQONwUEsCKq0CweKh YnHsLPZhr4qSOlOZjLVcdlSJ2A71xvFNPuL3ZB6GYHGMIrxXBngBnSO33fUeGQsrQwRCNAeQXH0E nASWE1jAufywy/0kHqN10lNFiIh1DLdNeVSbkq8ZaxfrqB0zUuuTbPZr3B2OZW02jwZU5a0MUMoz Bd4qs6yhMmz0cVRLNG6oLx/eX/5t8mHnrYeRbsfjzAzyc+yzwTUeryiVjt0JyJOhMKJ1oa1IZ4cP D5GcurdEnaRBtDvonbZz4Fw2EQ7Ni+P8kIB5y2Npz826RlHSOzDSizmEFlls582Mr6GNfAEt2SbR Zt7wmhZtu6DdF1/Lx/ore7HBiZMjl1jhWREAhqjLLwD2DxswZ4zOwso+cVkJaJmshIkZyhnoRivO WavEpbIoj9x0qSWqjiM0zyPPwO51MEugHewZfzRzL3b+XLlKS78E1a7GYZRPW/testwo+FA6In5z gzE0uf/78OzIXX5froEms9ObRpmMP3UGdAomSlxJKRQZt2BAH0ZjOghQ4YUogNoT5olWsaKf5zGJ NDlWDtPF+TpCVhN129XtBXZD7+SahrNfHWQhXyELV5uU4tbkvdz9stzqXPhkgJBZL+IXBVPbEP8/ hClfFzD07CsN+kf4h8nlRg4P53AUv8sZCW3s8tQLzQwqQc5dpYCSxaxHJSeU6WCZKOTRJ4zIy3eI vD3iegjHGls0gbhDoB6TUdeCMKLs+Qkqkf0wx9KbuuR0PHRabR4THLJ/rNSRdza1Q3le83fIZdhQ +YWYcHnjJZ/xtoor3MpmPgiAo84Rstwp0TYUsOzjVRwGyjUbcD079p2Qyfp1mWspn/+pyu0Iaie/ 2K4zqAmBUToqvHVd6NLIPgIg3TMVL3nm512zM6WTaEQQ6G2yr8wXxqyhlY2t0VjnRlUGhQsksp70 TVaPTPPneNdVtUp2IPQau1TKttHgind8mhLG2nQzzNT8hh74RHFxx/KDgUR694tXoac7nXrQ1oM3 6Lt9Nl9bs3Vn8cPp7qU/LvCbMCb8vxQXe/42/8wpvR+Tn12WM63CmmyHzHIbIShOhNbZlWw5zbwi FT+h+ftE7qPFNzh1Y0zEA1Z18JmwDsqcVIOfI4ww6Vn9wj2ExuzZBkBFZy8xoIS9LcWyMSsxHnQu WA8hc25AXPc/gBoQwM7OhqWaj3OM//DNpnhoh3pgnmq+n5eKI67uz4UySqEABqi6Ywd0kloqHpFf ou266enzNpCHsolYHxgaayhL4BPWp5s/qSaHv4edqB+5yF/7/RuMkZ1JL5Qj4NoyMfWdtO7aHnpn ZFESKtra1nu4E4VH4iFgwm9Q0IL2NeMsHjgWeb8cxU3CvrCgo4yQWBFACuHh+tkFI6v+Imhxfl5w a9rQlGvVEG59p3g97zORix4UIDZD7nwvoKs7nil7v4eLLyDlMZgvpV4FasL9kxLumuuQFodjFxIE kCCBxaMq/L2S1Z3B04iTbe2MP7ySwcsWCiW0l5tZZvRdWj2ExJboMELNztnXH1+7Z2C2Lxf3J0MT h7Prlb+odjA0DNfanzAeGap2GP1rYnw0y3U/R7y3sTNf3JgHA1zGAk4bODFxkHxVchfktgjxzOU4 BgYoVV1QdHYnMmmvjIelnHyildoZQxeFSUzvLQf0I8zHDAig6a2AB2ylG0B/TpkounnmMJjnJbnb N+vGWDb+DLFEB+hxILam4rYSXPfqqOWQHlrLjbFAMxF+ws9uTDuok2atYgF4gHSWzicYZqeugySF E7uUT5ngrtcJdlsSs6OCphVh44kdJCGPzmdgQSwYZWloc4P+Cajp2tswmCm2nhXhaPdPNKc5rBQ6 L3aEZHeJ4wLx9QeiW3KghRGXN21bpwGD8uLiNIvBg86HX4ZZRFJ4IIof/hCKdubsgSoPNxJWWvkc DwkRASeq8hKmIUkL6OOKTw1sM/Ije3n7V+0X2kNB4PTV3HWLXTKxS9TemsGhVo990rZsa/lvoYnP Jg14CFPJL986FAdI0Jm5S768QsoyohxBaNn3YjNWUi8TXDpK+Ge8DtYNJvjqtd7eVVJlVNJmn8xv qw0rGDdVZKzeSTGEpwGpYEL7myOD04iJJFh6jg5FhHia7hhFY0k1k3vyhZl/sX57HW3mFc+/CEwS zTsbgrDj8OoeP3647DaO2GeA54GLGcSQwbeX7pAtUoQahiTGPZPh1uCHbA3+1gAvG/qsVRTYeSyC 7GuCYnpYrQP9naDNRqEXfI1vhz4uaB1Cc93iG32NcF7ymRmnRP04kSlfwgpozepalQgbD1Vf4hjy Bdq1W6MSxb/VXaQ3+GkzuyZge+XWnKXy+LwV8KrSohGaOR92srXO9HLl0CuTlcEEfnp335ai2b9Z 1TFZgGPmsZ/J51855mswXSMVJwvWV+0UWYxYUoMcuiqrP4CiPMomnfGhOHkctrvWdVBa3E7mmmZy hLpnk3s1nr7KhN5ilVXHWzupfduX9ReSAqMRK04lCh6c1Cat+G0SYVtXwPV+aySU3OptDB2KkrrW vxCjFg7sFBtwvBBIec0pnVq+gf7BXhZABlcnr/VrYRQ7e+3DobUlFN3AcoUo25WVarADFLOttEFT HSEuWkwzktDPurzkGjkKm+wjufM3TOC9hnK1AIimuxQWs0GAMhV59ud9aPLSOnXioOHObgreVxxI CEzUahTERN6MQo8vRbvX7QNyH8pyUZbcyZ9jSpfVdwvDNJR2YBQx2chmjMVdl90k4uitXiQDoaEO KCu1HYrrhy2WszQlDCK9RB9VSI3H/dIjo7OfJ/hYuNoBi81S+ZFakQn681kvxVFxZ7sUhhGymXOt elyg2filfg7zBxebyw4sXFxHy5XAZ5W7saGRrS0s1phbasXwN+rNiJahVs8wuKTzRW86nWixswUc MvVRToN4dwFdIr9E0MhSNnWtAC/DI9sEHJj2sXLzedg6WiFKIk8/xHrQUxAoOZ/6Tx3ttjcXCC4t 5UKqcTGXK+yru6xFROUTNm/5+cUW63aHPXicg+Y3B+cEFrTbMgd8s/BfsZjeYeXm0eiGtfNlPRxF 8QTtP6EHqtCHrajPxOrMfU+lWtyDGqnp1mLtOXl8bxYLlHrSyUswYBrRwyDfCuuMCY/1Tsesi4rh SU+vVXKw0u7gOJT7fGCSNT3WnFEPLNDVApKjGHgXuhphXGycn16Oeh+SRwBses6gKxGRmowPtFBT KcYWwTCPDBApfldG4Q++lVDfB77LJF4gWRRr8k7adACRvVAwBLN8/TNUbgcBreF4b2mdlN1oPeew TsJlWLPIeiNXluTrQHo16iKw1w5/2tv/9AFmYATVbFiUMfCxPj9vABMKm1wr3u1BGkMJ1fenSL9e MMV+ko0pMNYZvvMi8FewvMai/miVTd2YD2Y8kyJwZKQ6iIfGQmLtE5G+tchcTvHFdGwOFReXuq/1 yte865N3Q9cBQbhGFIpYp+Sdfqe58fvvw6TMdL1kkOBbRS43+SrFDXpADekgBUROVrA/Qx+mU29x x60EVipSn+cuZO99cbEt4/L5MmTdLUrf4M0olmZj2U2pNzQG+9H4PF7sja+SzJ+swXL0uyuiy/9Z kMRxg+YZGEuPLOl+ROGxjE55xuGcbrZ1YvJ1Oc85y4cEKg/WTrEb7yiKOxD2HoqhtEmkXRIBlKIL sbA8if1jmR+sUvvPFcM+S7aJa3MspkU93/ptkS7o5rIPZHwuBrg4sxpMo6uJqOrmJM6vSVmr2cqT kajwU1PiDflQUifPMw4AdBxBjO1V9/pih0azoAsJlZMNzBVb4iSvXgRXKjvbEG7Z4xEB4NoF9X1C xzBarZvPFu5XCdRj7kea4oBW2j21jxHvPe8Xl/3XnYUnMPzH+/UKCh1RjK4IqcrhJOutgF9JWRbt I8b4ulZhI3lDXrXI+tt+gDhct1oGaFdqDmqR2rpPVPBGkjahAHAnwktENeIYTFpcjGPUWoayByFo jaVr0IuLEsPQ0V3yxDLA+gQoNrZSrL8a9sMpb8wU2cqj6PoiC0VmVY1SFrXy8hiifxwPcBfqe9QA T7iRWh3lJLXE0/k8uWTHLj3AsZ1USH7YvkJpryUzKTDIbICcLrzrtpOWNIL19p2YbQMIdXBCubqv OLV3d8BG/2NecZc8Vpy//FmibXuG/ADE7vR8COSXIc7IJlWXkj+n2Ygl5n8kD0pMAFk14+Kmhz5v isxVhgF39sngVMgkBZhm97ltiFP435HX1QjKmIAuHsk/hbcql4ekzULdi8m13IguWrZCeesAo85o 88wJBGYj3uYoWBOMeT3SuWV2i1SlAgTYA7hUhCyGfxtmFdywyCJEB5C6rhkHPzneIiKxRpXqAH1b Fcm0zVMgIsXvEzTwlSwicUvCCtu3uTmnHg9//sayHcd+4ymOfy7/7u90h6bGH9Ea7qjHZQoZHp8h PeKMo4fk6bNrGWF32zwAtk/qNQgjk0VFVWkzDvTKRz1J/Ivrjnxb8L9Mf0Ae4wiqIt0Lj9Js0vgT g2hdmF5g44rkS0bnONiQtPkUucP8Jz7/D5yqwT++Jm7gKzSenVTR3bTVFCpXyqD1OWvsy4Ks3aCX ajNn0uORG8KN/ocj2lo2E2ZMvD+z+XYk+qD1PYdE5Bt2wny3txO0IHdKoaG7vkpU3rKRYl7Pg4Lj xwG2qzsQ2FDYB1QI38/spVDr5Jxf6Ck+BIsNpYFe1t4vrkSAeazRBKL7OJD2KW8EveLZKZ6uCD8D XMyEyFLkRcAc6pWRJp+w//bh/pgfSeM3FJ9jZ9jHEzqDj6p7q+XxrsX2rcwwuhKV3g1Bg8jv5bBH gTC70cW3eWVGk+NAOvQirX8i7l8TlrF/fnggucsiLJlTQ6Gn9sBvmbuMO8Gctfv9hy8Zqz3DQkth db3NgPOIr9hB6SFDgkqGcXStZsOBRugOblJjN/OgTFiFulm83qrBzF5hIEmtmM5bZ5wTSu/PjSoC xXeHzF6Cns34EZkD3e0gAqKDqGco3UkezQQVzAgfqFK1vZdGtRWqCNP5ryxabUk5RWaiPsre7k68 cDzQPU+gUCPLgmnFkOWdGWVasOeXFxH6imZw6MXNuy3xXaZlPLITrT1O86CtJ8U+fJQi5KxQgaj+ vJLoqwc3768qFZAeO772+bIZP7Arby53Gp7f0OELCwry5m4+YNAv5uQ9T6ILYEkPfV/CAn5XWL0j A8CxXFQTX34l0gR3MRlo3E2Bv2I86Vs2H92RSMSC19xiflENzT732amo3aRf/MqltAM8MNPrdGlq F/ZMOqv6K1Qejplc5ROmrq+bP/q46S7W2SSBoFwc9fZtzbbm1Nztf25fnQUIO5xSKZrJhW6KiJL0 RcyvzHR32JIMI9ROnCnv3r+4pZkqfTmsB5aq16KNLO5e38kQwcaegJ5903jNHfnuTcvQ4Y0r5hcI n3358XND+27DiSKGCZ0ZX+Wc/MSt3+LqZmLGo24qPNrxuWzuVxz4wrL0D8jRPp4EvJuof+TCaSvb 79WaodWFxZqnPS3Czlppp+kYF+0AbRRDTJplNZW9hMV3KuC3JhOdpTfkfDSH3HE3OGzjXGHd7BiT Rp07OyerJB0SYFfilv8f9SaBBf46iDi0WkYuH+0z0Q6UfFKtJt7p6slh7N8i8I/lha58y1Y9vQtb 2e+QJlcT053hVHVRSwbFVrPh+j4JbFORyVSIdDR2QlonVZM7fP8QmQ94H265iMBX6WgiYksEzCkS jAUPsTtFim5j+shjtB5Nk6hX9eB49gOpCLae5E+Xq4BIDfNKbtOj4zsZuoRkKBf+oDLSYO1yO1pA xcM3QXVDbBgkp6P8pqgZz6V4MuCMWgiCVQK+UWdQpoWvgSHkK4qG9MTD9+E2RnsGKm6puJpAf8aA oqE+HKZpWPCFBWK+pvLsXLPUYWz9Tdwl8sMq88/jPMNqfQ6SADiaoct5gnMDWmJwVLPPY5DU01J3 8gEVN/6y4ytCB4nHs/yT7smRVVLS78gYzS0U2KsobMNmTBYECruqhcOAko1YxHo2fW+vjUuiFm0R h6mjiBt7KqzAawx+lW5M9l6uay1lN7EUFTeFXdoSV5VAaE0gcZpuk7MyKh+lRzranjOsoJiJ1bL8 qLz5O9d3ricfqOULsz3wEdIAk6H33nxSzPhK3s8XuU+xu8WYxT6stTK5wLinGr2YIFX7djvZhvjX yMEAdxUAQz8eaToGg2ks6SXwScV9cMn1MhsM4mcU5aSJxTNr4Sr9Z+yJgn90ELAbmxsKqsv3bgXt txzClW2xQIYCtVesHfUZzZIRJDBS1WnxGy/N2KGKjC5u1oE1F6BRuPzvu+atSUWMqKVTtNQKjP2U EKARUxS8tLwnHY7leIhSrqUYJ4xDp9h3FTBo8twPpIlPvJ05E/TLYSY7cdJ1sm27j1CNG3KoSzVT F5DuK7EYUMOHSkdpnhkdX9vsFu2XzS076dBv7c/DNJnjxpH9pUtgAxSmTP/nxovPhuvgI5dOJ7zq Y8x75vSxDvX0cJLiQBKShIF7cNRb37vMYykBpLfvY2Ye2cqMuTP1XW3onZctJQf7ju3J8I4rfd61 fxMSvkazdEh06zJl+P7VAqEed1R8/v9TQ+ojUryIgIKcw43xcHusfiNRuekUzj8o44YcaV+gUxoV 55bCaGgzOCH2LiK0AQCPHBIjYgH8M+6c3bFYrnp8QK2EzrPvikHiHBJtnWVU4uklD5ORAY5uWhIs 6mo/vl+YIm6cB7+Vcxq+ZNWgRxuXSk78cHz939iJQqhNmIKkOAQjNleMZcXcXSqN7JTUposLmG9Z lQq/g2Kr635wd81Bhwr6AxiU2etnw3wFwagEODCRej7vVzsTDS63U1/BO2Pj0Z1zzy5GBB14k/U9 GbIFezPMEH4u7utN1hZvPZc4OBUe/QellP4xfi7xYcVr37yWhw3x/o7XRDa6Q544x/8f0dFDujvs bbtxjWFNxdlmpsU8Hfr2pqlENO0Ub1wwNmRDT737E4EXeQjll3+tyxauAGd/xprJA4QKbWvLTtwr dBLbjt0+Dz4/D4JiFfeS0sasCFixggKwFs0t+Kt+vA4/uObyK3L7/FIK8v8LQ04pdiL22vjbRq6v 8ld/q5qmO8KCy/MVTt5I4LKlS8gGStgHQmUwnyvA+9dyGLXHw6BgPavm5YyDeiDJ8M4FiDOKv5lN bCYFX/OGTww+zj6W2s2xuHfu87at/NeDUh30ukhpVqqnj9sYvW7d61On+9nPv2ndXSkFFVZ0/aDi SAdB7n75KBBYuhyzdFkeAzOYvBThNp3Ah8NmLv+0XMwH3rb3EpKTido06pWaayyRxaeACHWFALs1 y76rv/AHB5Fz/wMdRLiZmYJ11aFdE8yHYoxB20ieyql59gXgVthHD9LaNSSnLIj0vDZ2veory1A4 LL9x0KMmHfmOjGyCTJS3wqdW01uwNw09V2+0VBFruKCVPET149iSPccdjwSioZiWOMgEa4UNo7sf P3RGxVUzzE/IJOadtkM8sKUl/ZXbsUuXf+CoejPWkGOYUJyNckA+2MwXfZJH6HlvxoBTnnHuZ1Lu 5G4hAWzWeluSa1Fgg8hpKZhBh9zUQ4bRWf1NnKIFGTzlrwThiI5LaLAtxNt3FksYjw0W+93dy5Fr xJ/bd0OpWeQBdl6/WmXeSjZhUxTYhxHBOWaSF3LOjfRfHNRbb7fR7/hE833D7wZn4XZoNlVlYUyQ vAY1K+zRL6TnZrax/Ol9raGGozPCFd/CoxqSavGxsunL4T8lHV+9e8bO5jYMfRR9MeKYsiKFS35e K+C4HygMtyg4C55FVx6qE0qsEgVs4NXASsBtd3lsgNdqu7YshVHjPNEswFdor3RKmzFLojdBG+yN DHF0Gi1owYd2XNMbppmChnkKL8gea5ErKAxy6LnCQLPhO7gcSo8YRuSzlPbospWpYbcvK7/jBpon VHhSeEpwieUUrDgL7vW/3XSEG5t9rvg+wyCuT8uX/iI9Jg0jqLeYNMtTnMWXlB6nkHgGmsLh4e+n 3Nj5bM2B36vlkpE54lr0jLJfMz1cIUHgxppX0vWOVTZT73CNLccX1q75iu+ZeRQHt02MZHEl4icd lhJ5UgpHUo8TShm1sRMJkZ3dC//tJq7U/8GVLYnae3WwollaX5rHUI6E04bMOIjWwSm/qrWygWVH A2IPjOD4MNfmSYeIey0MQ4+FbXtMXKo67YyJRDiZA8DuE1jSDuFXztYGe2CApDdK/rZI9PhWHNX0 6TgZeXIN4ycO7LQI1C/rGi+JGpG1zOBwMi5pB/JJAqxR2+i2LOtUhHswUwcXTRx7+9yudYZ86136 2cAUOSH6nL/wCcAZmMsAJLt1D62DvKEvkV/f5VEELO7bl+hlmcqae19wYXRzS087lTtbtJREF7kX JC0CR61nRo9xaktnPLrEat6xm4CE5dC/gniIfvpzZKAtetaSlG44U8tvpufZDafHvI+SuQmWDpey IflD9dxpq1/DKOPUT1dlZKLEUX2US7JZNk1YQiVLjM3fQ94ZgvC79Vv1oluEVkKjcIAUA5Z6Rnav OHZl4TcaqlcoBawuimrfFSwqE8Jmd1Uf536MlqXPgbBIoWsAomP1lxF5nYmTa0+AIPqBfw632ekb Xmnw7LeuwsYGQ+wd8WBZIHFPA9P1qqa7IAZZnfXnuKYXoNorRHB4V8Wr+4ltEjUckqKmrd+iELuX FUvt4L1XnHhyfbeIUej22ySI9avY+AsXPzhqagvQDcMkTR4o8Umc0A8xcXkx17OLreq1pG3t1rWd rjbfu4iuSi/ZF+Wtl4nyuJcUCAGchwErl+XpF2g/9gu9WNgNLhHn6iFwACeRarusV1OM2hs0Hoog S/V9z8Qvt/YM5aPv4frcfEYNA9XoIoGsOcP1ORgg3bfqouaPLsoEnV7NtODZiwhhLKXFpNW0e1FZ 31JBujYMq6t2Syyv3smDZ7YgO3z2hm5+9rCtaXBUdH6P/rhlQcoqbZQknh7XXbehcHQc9LVmwQDj iGzvcVONG2qU+pxjwqYYvHdNVOM27WnfgWmmoXttuRaraVYpEaJGI5iketUAkOISnKLXv0WOfUwE e7CBuNWjsfofC3oFCVLSBhXONq8lhuSVBrDFu++2d7pNWj2F00XnFrwO4zKP4EkB5rNkW5SV7vO3 FMY1M/niS56CFcmWbGovObn1xEXAJ0gVnld4HOhvOz2mKZpe6z3z9eUwaUYFVzZEWCWc6CWmKiMr aLrqa0cbYt7Kn+iZvO8O9zM9h1YF+kzw0hTSWbTxEJ+Cqq4aW93Xe34I6ai2fhqAGVonWiDtm2WR ExR0+uK14HrcAGRW62qfwiHkRavFW5B0I9RYsGk9R6vI2gthtJy7DF0r0f8YQbeORMIIGmDfz0gk C/h9lvKLLfNgFnw4PhFma8mrAxyjK27wJ/HoBmwN7kYM5JRNHeaxeGEO7lDxzCWlGmlAom8hEXBk nzg1/3wv/W4ThIMxoXHpITJ7grzsH/CoEhYZ8RXSLSEZxVx8Rb8EK3D7bXtRq4S7IgeKkL8vTgTk pmJeeaIjiFqXoDLzl62XMcD9P9HW8XHkca9riHkHPjonTMqb/G5B3mPoXuF0+jpzegwvRo1sJUxe NPJ28zLo1k+8CxYVhL/WauQ3iBWVCSFmnxi1T1O1K0aZ50sSGm7yLDUlO366BUKNfeJBGB4ab/WV QtIcJVLnPIYwjppFTwMX26K1DuahKonKj0dqFO9WNS8TmZHeOaILTqYRe33Tag4pkGVZuAlt0cc2 PpvfkNT1YZ+jTd4Ye7l27BuO5Y9QmFaBufFKmZ+LE5A4z0iDvNNJEakYKyxiqFmXdW99eY9ZXnjS kEiSEOJ1uFC1URFnvdQOcIKH65a6uefELW0FLMsH92/HI/Vo0QBTVwDrilKlwNcz6DwHBxH92uNd d+LBS7F37kP4QUPKXprAIhtcONcN5Ls42++lbzQGQrIpd8iY+G9YANE65lfYxETCmO53XOD77iw7 iXZJN3ufOdXR5VDfa78+mEtaa6O3i6OYRGy2zWhCHdY5rag/Nmik7QQI0uRaXr+g4PMMXrMD/2aK N/EP9g7zkzTvasHkgubTvuA7maiZp7KhqKEd1MXwnW2vLwfm3FPpye+w8jdZtC/eUBLwydhp3Zv4 O+WNOtaFZ79YIE+FvfiKvZDl6v2+J+rQO3LAac/cmLpN2niogm8Khfq8seTuDL4ozTosAqUaUqga RYElEfYTKvnFeYhuNbcXu0RbO/itmEAj6lolYQv+XPgMCweL9kE2aFrxSuWyMwSeYfcmSeK6nBmc pRB/ZFpwiluNA5axZRuxNE96Mh7UJalSaU+fuuLrDqKrSXCyuSapqM3z5Lg1GS+BDSEYewjc/kH6 lGnlFr5X3GrRjbqYSswXQUZsVEuLye3s1wGjiEcaBBK/wZ9QegqTAESIR0dCIAnCdGzZXdkg0FwY T4V0GQZ+xCj5LhRyGFxFhiEOm0uj0vQqJ0QvEyZBBOUP6N3qEoaA/j+15oPWZ8HOLJ+cIEcmTdlL D+WOQApQCq5XqJ0uQ2sV/zc/NCbLs380fpG0KaMYVyjUQK2uu5L12Thc0433m5KXBLJL2oFLspan f0e6O3Vkn9gw/jFSo25XXmwU8qjhXggbY/9PYJ/NWLegYDK+VKVpubEBULvDjQqMtnLr4RyH7DOO 7Z6HuduXeouLepngvLpyB5EwHsLDZNMLMdHYTUjh/+/Lw1Q2pwYPwRavNyTE2SyKYorM9WHLt+h+ yiH7fe2z7Lm9SNMzvcBcD2B2IFAWvl8Ei2KVE1qEGyvAGJ5VrVngjKY49peixvQ//ZM92kjoTDhm kruVcEyZTqR/Z/SAP6hgKZy8UQPfgy781SF9/HnRl13MdXo6v0pzT4vz4VBCGqPw28AcwZzBAVKU FSNLBpFiRlb2L86GsdF3C3GFDZ4W+Z2H74oRVopnRFPit4ZjgIO97fK8kU7xay/FKguAqIzDn3Lb z4/srYg0U0mphyQGNi6gKU+qmNJaJWc9gEGGRcpnvqy0/KfAjMD5lRQqME/cnMjds29RuZfTF6IV 8YsqDAIk5IM/Xm2anS0qvJShrrNvxUqFyiiOB8LF1qqB46L4p/E/DjzX74rbKcr/5gi8S8FuQXvm jGK+X0pj4b9NBBBKKlaEkK0zROkenizLne4WarSnWsLb1533Dr9yzvUiA55M2FNgBJbGaMvqLWvL I5IYUrhSVy2BJNMbXCArKdWMRXtqc2c/XEIw4UV2UPUpmqQyVYjnMkL1RLE1EF5grDpeS0Y4OsmF P7PklQBb4IsDwnIW0minG7TngyaAsGF2JPakvFxXVSo8fUCn9bpCq6IFvumAkq3mg4uEAYbY+usO YtNQYHWcrz7bwekSeROZILGzSOBRBbeti52TVwV1bDJekpu7iJ6jwTveiRW3KtobbACc1tlW/kfU 3eaoLm/VmC2qoh1EFoiFR2TWI4Q9FENmFmP/15RLh56oauBEAjJGCFs1EV0eSLEKKVkjev58MOmn wwbustFOVqI99qCVT1P/8bPSXDzIse+GGkxOTZZobTxlkpG6M5jJuswkluPj9lj498G9qU45f21d IbHNHj8I3/H+hAwN3tNq9T9NvlAVA5CkXmvzOrmwP6xSxtbo5IGdNccyl4RBGktsr1V+5bnYYg0c XKoTBa8rmhUyENg0hgVZfSK1/jQkLx3aOpk5bxSyxnAp+M0B8n39+zOt+aCwM9uTiqWZv4Ps0Qik enWcumrPqbDAOx1qqRFw3M8yzstrnqWSOH/xagni6aCFAPnQloIevCEtbGAt1wq+FHz3bjB2yQXR 9YoTM0ZjvUxXXmZuZzxjKqeBoYSW24IL/2r8iBSAGYtD8/DBCQU+/r27RRa/ht27+zHM7xQMb7zb c2g7lolMMGyel3o8Kk11ufK1P97tQzlfFDldKMXlCMGhsaC2uHxPAx3/o72TStcWpAoqC1s0LVl1 IiuBtfEHSrjTaUVnruFDFXEgU2PFkRys29onr2KuNWwc+w3o/68pMQaU+UD+R1D+LT1BhWOzowTg goVQbfdQpFaouKEKT5EyW2NvSYsUqvTJRX0SkqX8EAPQHmQ4RQGIEBTzeiPz9fUg7+YIScQCc0pK u/8nB7ogP4sTRK1qb9mv+fi8Nc4Le3Mv8mY/pH+AaOu5+Wz068jhAxBF4GGf+EJnpfMsBFb7srLM R1FSQzFKAM70Hwshah9l6RK5YQ4ySCjoEAwoNMZB53/N+C0srk9QhU7FXR0pak01Q+UBULIE80CR Igih3TT0Cigi65IgPrbE5J9IimeC5LjoNkPzjsxVET4CYTe9sOmnn5BYvYadmFbMO5s2qQlBVkla 4DNp0HINncwMW/QxPpoVnyl1XeV8foMh2HTQUDaVt/szLAndTLERQ6t9qaUtpRanFsbcZrugRjNv cZ//uV50582/nvmcTK0dYHIdVKWccwerrSVKqVYL6FygB6RGtFG+JNiGxxKK32TUcPXOiODDpRVR PCTgUWFGJcaKiukMhLNcyyvcI6U1AX/kwfLhBLN+vu0/KkqkzxX1KJv/TDEW4ftCDvmsABb6jgn+ 2Z6vmVy5ZBGS1bWDjyvjIgJXcr+plBG3E3kHhiUaPhLKMKZ7RLZpv/Ece612UaSuxif77r3xkh0A KeJznfPbChD6RGU/kL3NTg5nSMykjdPTS/qfzWX91+5x6nBZ9XMca0kCTwmdhEryRoCRKeRT3MoV RQKvAs+cO0k084Nzf80FYFZa6KKYapcuCqdb0ktNSByu85tYd75YPMYir/z2Va9ZKZhhFY4w5fWO la+fz+42/vrvzkc3vYar+VGZKlQWESc9BfgBSfL4Bh/B1UWHncs1iVoXEEu4ps/+IAdC5+7qMNLX E87S8TunWr/788dtA5Gf1hhVxLRcuhw5fL+YtMkGBmbdjfjlgZ85cANIy7Z6hzLU42gtwtt/vSB4 rda6B7EXuVZrelHkDcSsGmXi0TP5AK0AfTCm8j20H8qwdhe5gg4kXlqaeVylWQOv7mmRkDpu4HSp YLMDxc28lE8GaJifi0noQO/YVvvIpOQ8FzrTMRmiWfFbw0EdF0ckKlx6SyqrShv32XZ7BRv7950c 2s9izfO9eUdcKOnUD2BzYGozgi5q/BMepPERQnb13eQ/7ZsKhkjVAcTcw09QWMqps1UevyaOW37Q rlu3e6+4DDJvqdZjDHp+mbwnWdbOPdZSnBvPE6apMAKzgVXd4D1BlGUN68g5RIWcbr5p92E3TfMx wdiW5HuoDGSt/Jk/ic4/QuHrxjA8CJEvg8o+0bq3IKBQrqPJC1AipQhiDITxc3em3hr1O+lkHK7V 0PkTcadoWa9t4dNjoJavwzRd9QxJ49kIaQvzuaK46V5Tvc0HQmBxoUQxTAqSykR80eMzE+OddpAH wtn0qxdAugseUNq3KaZ3t7DVoP9s6VLngU3cqE7aRIgOWkRuHxEizvCVyc4DlEkUimbPXcehz2wV ngNzuEc3pop+PF7X3pIw++LyHjo/bzJLeZYFYFS8jurrmMCBwLH+c+7J5yJPK4JjanZ8GQGzNBzo dcMJmaOIastM1jD7uTfE6MRYzplUh/yMiDVUdfQB2zgpbgF5PuIpRiUxJ8smBzG1XU7kkYncyDX4 8uVpWlhqlCt30IdxHM8T5Uaz5hzY+3JKiZXhs0HWgQTU3ovJiwhGu+fJU0fAy2WI6kX3VXy9BIUa Ab3dbqZphsj8N455E8RMKY6vEanvaimzB7P5KKQwlOfPnolHeSiZRrJrYPibEhNDSlUml+V1lpx8 ecATEKFejxMkumzIBjE7Q6IY0vjf/VhZKLyGkcBkrHc++E/Em9UIyGesSO5PpccEm3BOzFEAtXwO 2lB2OCpc9ajhebNULv8uUM5LfL/jtolxwXzMhMiv+AqfxF2q8lRsf1gWnJspLJYoIlOhhqQ0Ucl8 LV90KHKiU4VaQeUZRtDzAWcqMFtb8nP92nhRpMUdXH9qoG5mO1r1DJWbuqsagDarMt/j+IsTBBbS zqDojrSu1Qk3NK68hnLl6SULrLkpTAOVjOkAkMZvvLgUu7GKxg0o1nh3+K/F027xyHUyR60xPCDD mH9OSPCyXxvpvJfv6NSNx+zEuocdEWCq++P3KAwS3jsWuOzmO+qPKumpNYOpGEVD136rQcg5W06w kipClS4Qsjjg/foORfgHi5fWZ1WM59j1doFt/eMoa99ec5P8RGfx10r8J7n78j2VKXcnta5TM52m 7XZlUwA/Y06QUo5cwsvII3oF+rzc9B9XOb40pGwRjkP3J9bwbNXjHvdaFsYYP/3rUD1uOCKGsIgs hxFP5UALR2miW3qQmJzignCeh00vSnA2foSogH1bVt+dUIavJbjAEnkB75ifCKEnWITCoSl6j2rm Oe+DRHUKT0VALs5Lwc3CPNX9m1W0oM232eKBvTi7mUiS2PK3C2NDFLW/Rho+ibJY7Z9tbHwpwcVW deApaS7ah5T2UkY/k0ToNZBU/dL52kalaTY4sRRE3Rw2vJk42jhLGqmaBht3FWg5qBCThSFIIXCI zMa3ekXyyApFp0WRqaCFg4SWrcm5ijS0Gk9GJvFg51muQ6Cm7i7wLLpkN8bFktZQSL8PNm4P8yrX X3xBGvCYlSWRr5Bt3xwiAfCduAXyX2ppACGArN20d1s4gwRZRmcuTR9g2D9jz4nJFAbTs4M85T4A qcDeD5XXuBNOnc68xipXVDtw4ENwBWKl96U6OhsjJ1F4xrl7Q4HhatIRrwzjP1Azxg6v68J5lA7s eDCkgO/rAoqpjoOdg/liAQK97nCLK1TC0guAQ9TnVSowG0GjT2nVzIgYvYmMUPR131DpIm7i5hQx 21WM2DSyoqq9k8i46KorWaXp4uAO1PcslwYZwOZmCHX9dvKDTb3NsdllrffpoP7heScv2lZa0uVK F4IQ6jyiho6bz4JiDQOTrE++C5HDHHHkDX3YX03xwnomBM/D7Y9Yeaepj8Xqc1dIFjmTBk49ynBt BuzNsHkkxbBWF+mBcEgNN7WYfllgC5KtMP3aHidKBd6P8xHNAD8q92nrjQ/vcoJksMea3OfCKPFJ mPa/kXF80NFMlKBW8TyiCE0UUWfOALxGcrV2e6DtLMqMCL/7PdOAtPZl6txx52hiZEMsqvZnelKc VrsXpNdj4nXBa5+YuHVqZTuuvMX2cJ14egjwUe06UAoxby6xcrFLWD9uPIg405Ws2ykV7BurbUuK Yd/lxfRcJPrrO0mQrosyUtXf4zPY1bU3KnoQmj5nXCfyp2lehBbFJnsDoVPGiNhXVZrG7ZlrIa0r jEZdssFV+qROU+qAaDRbawqXlJcKmiVFpCsANFXqXmqAXRt21cXwxKZziwx+F+kWz2T1+u7RmEZW L9Lx1NRD1G9AhrK/L3320v6lAkd8qRHNEnjVBzg9LM2qhzmYbrG1o/MQkv00/1UdyOpfsSlvyaft gdvRZBorGHe84bPSNBMr4maPtj28YRIZvy7RZfy7JcGMMYc6k8Kwp73ViAal5hc8lbPG+9MEI7Ck YfnyS1hZU8mIC4dX0nMC+tjowI+osD/mA+0rBsrZ04erdDA7si9F2u0yZZ2fXp3sZBHMfc+z6jOa Gzl3IUHBmcSUDSScxmIZ/6v9mgB5WKVbjifEJ0e517niDmwcHHzGlnd4s7meVtzZfiNqsmeGqmy/ tZmcHA/T/bOrzwTkylh/lOKd/3W66WDx1P9KCZJAEOjZP4KxwgsWjPQw0q20oKrtzITVkOxB/i4c 20J1NR/PtQ3vnp6lyRogRGp1AItqgdgvJetlfWoXT+owUaTxuw8x/RcRAhDPayDpxXU2rLHf8bSn BYmRdlHO7OH3ErUE4Wx3XzbJAuHBLRTIGjkoRsLl2nBwOz0KfpIN4XFrr7TvlNj9No9icFRLUQTB 6fbYDgwpzVE/f8IDfdVWBJpgAbUQ4Uq3WJCm0mV7BLLIGymtNKVFg0PHxyHgS0EUTBeDR7LdyD+C qPZRcEWoWNkThvdLfvjwyT82/e89oIuU7V7QELPTqYsTdggMaaKGTxRm1gPx7vLoQdlZnrpdcTQX ZCURv6IJAstHVKeg3yIZ1wpkzikV9zlB6iUa7nC8LyjzPeCUo82Bg+Kd+vQQuWjJZB48EauxslgI t0lemz/NXQ8scfp/7n/pb0ygnr4Zs5+R63WUBzPE0EdRGx2uhkcCBxUK67DQIrEu+nx2lV1GveMR TwZ2i036lOP2ckFYs0/scQg4f0QkFRDVNMh2j1moxkYuGrXA0pddrAHYCasK3hoDjLp3ey1MWGG9 PEYbuY1QDTtwjyUMrFddcom2act+tljd4P2ixxuYSPHgH0RdXiBIoGsVkPIpvvf4Iqz8yy8T9Tct pmMLXNlnYGP1PB/If6RjJimz7NS9w5gAXPglZE2JPCtY7cvrMBQrY2imqqb+vQSu8RPQt/oDR+ps dQ5yrvE0zVe8a3FeY0JA55tt0xUZEzHBoHk7Z+Dv53Zp6edZkW7efiYTI+8LQ7YmOXFEnObUWcDa BMf6iZVYqGwoEGL4WnngbgPLQHdX49LkPwdy1Qg9cMymhNT47VWiB4TvIGT20EjVmoVJvU6wQZT6 /cgf2KDWJ84gqtlcD7dwpWZM5NIGcpKkgj9MmuBGIoK4PXondLP/N3jcppiwk7sIwrxGBBpcnl7M jCQZz5h91JfV4da5KkVJ7hh6NeiLQE4OYDSGpQQ7JV14jqjYN+tV53q3vJLWSpZa0daYalbzdI7k ubWDBiHvvj9MlVcK+vBP/uFZHGn4rNLiQt/JcGF6WQvtuXo2iwa14xbdb92lKZVjXQwlUX0oe9c7 gK6DmM3O05meu+dhYxV4EP4Qqme741PLMHK4b9qPwX4OfOxU5u4J2mrQN6efVBL5r/64ZFQTvm0T SquMZPYaBJUy4oy62al7Qfl1d1c2RJJ8HefjWTpnCxmnYtnTdtZgv0KoizTzGxA9TUEuRvhjeO3N 7Qurv8Ysl16I27CSvHOOakJDUDdcG4MrYEDSy/cBkFnbnx2Cpa11W7PWxH28c84bReog0VPB4AnZ RcDm0tQKYk6piToghlywhNXDpnNDhyNrHoD92y76dBtkGT/NjPFJGt9CQHImzbFt1Mj33cNQhfcn pDIfp38cJ7bZK8pV1l5ODNPRVcKrivxNekAEDNcDtkRxf825pn4YgF0VrY0PfNvnLB+xpldrGCYc n3A2zYP0vaCyqtIyKINcE56B2jw5Kkww45U+67wdAqQvX044q92gE3Sz8g1wkffm+ua8RHVMjAYy sTmve3NXJY6dyLqa3AYQNVm+jMAvpJvf5IuHY1WVln1e+L4fnhLqhJh24so/LC9lrw5MpptqZC/B Q0moe01O9hRoNLGjyclzxvQZxV02+3H8YGZhNXNk1wgUC0LeAJnwC6GVoVFOJhCEq60KmLKv9gRW n8iA//2h+qx8RHZGGKNu9IHrHmJG/cJMErtT3qWg/WJjA3hn9rTmdwR0AWiAuYnxFLmBb0JI/RYL kLVZvGfGz+N8kcW5ngF/GiCUJ7ahX/X6l6XlIUJMrmMx9J/QZUtEmE7iliTR5V6GrX8LITBrPcaO O+dgfmQQ6H/PSOLnv1an3b+9Hb5MTJCXl1OvDXRcENmqnp7/L9Gvh/jVGr+9nuMBLWX9wKAxKLv0 r42PZ56AjeKIO0aW7kp4ATAz1XxQXybb0PAkGk+pLPVtnEDaeOPJUTl7ZLN0aOPoFgsGX8/4eSqC THz+GPSyHnRLYEo0wh67MEch1Wn+2iG8hIzquXyZipe8nCv908bdAc+vc/aifjtYbnRT6McnrKE6 4Dz/eTIgRQ86PXszxjNlUx5koFbopP7d1aVhWf1hE0XzWp/kTRNDyD2aTK2ebXEOgl2NwNi4o2RJ JCuxhz4tN5XyWfQ2YAnYW/LuNMNry7MuL+pCO3k+j9WZdML6wxtyLoWg0CpddaAfTRhhrqqFmb+T XKdEoObZZXefJvLpkTCKzP9jokU2PbjWLTaQHBiDbJ/zJ8tNPKrmqF+i6W6x7KwtVZqfC/Tg+Q8g HXXTsswmAdhI8Sn3uZLHKexTk8W5XJ4od5x50uISFYwTg0QMrU6j82rd1PPio9QUnBh4DLM3HjY8 4OBB78uXC0ba0Q623lF3u25kGon/umHWNDTW5tCwMSJT81LK+c3wAHy4m7zZsABsIHg7JtzdNmGx rJBL3LbuVl5tlNMFZKF2mdmvsbzADMJOKsi9zd6JdxJsIpq9hYXlrZ8v6qe7YrwQxadxhV18jhYW oHTmRAPYxtCzVTrMrGKBagNi6ofsmDaQvyZcjtNSZUdfGd4IFjrNOErIh2nwDABW+ULGH/8HYL5f FC7Z/PYbqwk+C/4hhix2K4cOjfT9oNRq+jEDpZu371RUhI042Iv1emoFDQV4/Xt0uryPfCkEIj9R V2TC6EDkp7hC7amtUmy2PudYlrvQn1Ci+MFhk58lh8XEAxC9VnKZfrM3uTvXkxVCfojAfyIUipoW zM/uoLiYLGBpdJZXZa4jd9VvbL6eG1Pf+ess7IdxF8yJTv9trXocVUF4CcR+Z8MPOFIr07QU2hKl BXYj7uiVwEGdFqSrAqCoSGI3uXQO63EbradQnzgwrP7VSbBb6UkERKUTn7kDVoGT575v7WD51Z3w d3zsZ5tUkauL3TdaeH53HJ/OdjCR/B467mxq8EVlk/A2NXEICX5QI1Gzs8Ut8TGk1l7B0CV1JxN6 IRkCkWsd5Jbp7lMYpoCx+ZrBdkZiLHDVL3FJ3guZm+7c5tl/Mn09FYD/lei3c5Udv2BQs5rJhqlS Dy0BilE/see0To9X7sXLKfpgCxtUjC8hlwK4+RJRtp7oM7Ts3rAdh8jx6MUdcqGAs6kKmP0PF3CP ir2vIbluoFmbNgs0OFc8H3OOooA7ggvORpluA9yB07yp+31DSSN6HDqxPGhNrrGZ9HUsYlhaKuCm GOBND9rXFWOMxr/4Y9r65bXJU7gmq+oOeZxUC5vHGbPqUZBW+tWuuKOREw/gwf4ojgjyGBtc8469 wUZ/spvZP6zkSsaWI4fF0Yg9U20xeU2yz++MdLwbi+90QyKJ07GJ2jK4gixypU77MZ35Nn8IjNnD woTOe+KL11XIjZ+/0eZNKN+VCCY8OJ2nTjByy/i4n9NqIzDRs9KSN3mV503zeYjNe1WE3tWoflhJ Z3RLlUSq2L7rLwtZc6M8FhBTGWpHEpnD4DPKtY1b2yRxIL+7JjjGyGFNo/yslkRdhB+2phVIWzpK jldxsUEvuj0evhoWOItwmNQxxdDMdBxES067ObRna7p8rvZtXXkqfZnxXcrgWGMtrOekIJyH+30P S5dIsq3fjWvNCePuZXf9O96cYDU+MbwemRIQb+HDSVo44/gtkzJx+hb5Eu/6x9C49nfDL25tm/cu Um/HF+cij5a7SNu10FRBXhG73N5V91UOWPXmGsxk3VZg5wV9THxOlHW7PISLBSnyp9MQEJXUNSNW 1x3ZgI230dSteGVVIXIJWJoCCECwUpuWOgi8ZFidjhyNFuUs62q5OfLj4EzmsSHeD9lrEpZK6b71 1pCbXfJFwyxa7/ZPDXrwERRQ2LBzltS1XPw0GexZQeF3q8niOQuppg8A1xa4X6mbmwmd1RTzlRr+ XFVBnBZJU4KKVd276/aXPYp6BOPU8bpJ8zpOr8JNl/V0pt+Inxcum7Hv8d0oaZBEPSkWtZGQqw5k XE9LHgXczqMLtgAx7UJRNc6HsQF9w31oJ1bssT8A10UnAxdMJtRyTGwL5twhj/Ovk/Z/0gRa4PFZ 21OVy5hontG6W+PXydDPAn+3T5rxEMez4Nj2wV6cG41BAHU1DBghlHrevX0Y4f0uq/djnbSqrcTc 8DUvf/TkpzWcavZbzaNuI9YNWjncETdyA6QrFzOaZZpLklp4iBaAzP5dDJVHDwX1Y/D7i48uUfsg 4hpkIJ3ZGZRNwcUKR/JLjnwN5pRAzfsoxfXUlbKPY9cBSy7nZxCxTnfN3rQ0aitt2nHup0GPV1Qz MIlwcwaSeHgn2EB4l0a6AIO/xe7GTUDffx/ild9nvaPbi2WNiCjB6AgiSXssbvme9dlwJ5+3ibmf HuemdTbrYgZSa1NCSUwDYO+eV01mvsA8K79q9UxBLiZpI+8bbdNwNSXRNzU14uECI0Q860lMOCbf dwz5dKEn6uIaCryQe4SKJOJG4RH2Lyc0zeWE3hwnIR3wmPPtFMJB5ysSw+Ju/How6iQx1lZPp+Kd OQwNTwdVtBf+80bc2UPzcCLZvTp2+GRXmtmCJNDgz4Rih79KhnOVnVIMjHkyyKdfpuLWhQnp9ZAi j9OAcd2mne/hmPvYt0w/y4+02Y+sEDQ8Lo+/+lRH0U6Vn9kPIJV5Xl88ob4hFUYz76CB7BmPpw/R 6cuaE85SV7v2u8pyG3JCh87fsT8+ldkGbuUtzHg17ws8hOd8Nj9uWpkIkQA23uYvaCFcGJVwpCCD bxxGKwJYNotpySxmhFq863rWFy7D9mPkrnoSVU3tqEG6d8lxRKI3uCwzA4ZgKrHWxWUc78ue0xMD HRpS7Mwu2rClkb5icNSBF1nTs53zkx2fPTiBQu1rkqRwFAaHaOkdK4tfemsdPAOQm17AylhDFdIA i+5H/XUT6/yXZdSr6E3bRdO+5p6FsaQBDszTtie7kS+PyZ4cTgp2oBt6yHADavz1HjKiJbcTf2Nd SHESkDB02RwBk2WSVtsLUY8xOKDVOhTfFDWnuYXLvamqQXqsRNLxq0kDUIE63rNItdFmPsDk+bSN lgy8dNJ2ghVlVK79MEvFiT/iq5LCiQ9KXtwLtbXUEdjOzpHAxMix2kxzVvqNREeYBPXaQYpdrR3B ZXCrD0jCcjM8RUXiYYRVXFS1vBK/hvMDONjVnFEkvyTALVLWYsa0gmiGn6/MYFjoAxNODr7tR3Nc E7PNzv4On1O6K3PxYGkqtawbYc9CSqepLLsv7mbkgS1oM7ZvVQKwSTvmWHQ/8Ij1Pzcaf+01p/eu 84SZlCIhgbEI+oVMmgxVrcl1BBhbb3iXAJTQKf2jQhvdgS55mkBqqTtpc1B2eS+GfWdyBcvbhoRT DP4o2asTCgNPzm3WZ0OjuEAcSu3OhwFRi04VESjh0T8iqIbv0HZXjLlNbnIJDXhHH2ubYYIIseRO 6LqqzPKl4c50pAZhi1imK8yvVBZbymBZ06EmvoKJuSheywkD6LNdCBdkIG2mh3aP+4QruO6GnSpO 5AQ1SK4xI/CilvehEB+STdnRMgKx9YLiJL7t8V0jGcuZFvg8ndUrR7uTXgMHmJoe0lvqdHrwUVTM pcA09XrSOLCJ46dgox/u0DQX+Vke47IBekqBNeRP8uXxl4DhNXeFNM9BKOoS+dcvQvQXTDN0lKHG tFOzgiKxREA+ZTfPE5Qj3lxJbvub6xOuMEM5baaxRxVVUS7cYxi9mJiV2AG27exN691cbRwd96Rn FolwQKnjJ5TVO02BwRNmY7LLWVHUASmFaBpokzWRcwvexzrlFVIpl6u5RmxslYWQ0jN3p8fiN52m KrLYuosb2JK7IbGULEmS/OXBogMrkF/snz2qH9bwRW38qkwL8DVvw1pb99ARFewZPRtVZE9x+nYg VyKmCrBmHA5Qd5lzg4vLe2V//XPbQu5GOu0NkUC0nULk2cBaLcwjSoHNYAfMds3Cn9lyr4vTF1pE 9b7D4dmUdZHgKiRbrLzCPVG/rmoMnXZtz+sMQlHuxNUKuze5/oD0skYkgmTOUZdYneo9z+C1oqMe J2JV1SGTNRmXPHL5mxrgUtjdwREC5gklfmqoGn1Fi3TQTvb/N/wZeA8vftml8ih0p+E8F/naYCy7 Z6VJRTDsmLaUuYVhx7h3aJWDyHZ7DHkC5/9NW769cWGtZuyyAxrB/es4upGxsKYtFyLZEzf+atN+ oGdx7kmY9oMz7FEB7vXoowRq2HS3vNCuS+HbAOifWXUtFWyg6kniDezohZh+J0bzL7/MnopnRWN+ FpR5L/CKL64m2M9VvwjIScVswzO0f/ywNUsSPXQhEJpm1xPq7f1jjuwAJeBexqFv8tso1yT5EsNI r885fWmmOF2xzrI42hGgN68oLKz1uleR8vyV17QnsqXBS7qX9aMISlkry6bHwMixS5Tx92cq7Jw7 x6rwJxuF5mXPRnBktrEnf3Co4ma8GENR3+lBYemEMrsv29GbMshQgd5kyw99r/DOpwjsdDm55B+6 bbUHs2zL08PalQVIsTASlvJAb00e6KHikh7U3Df1ak9GO6qHIsYGF9/5H77b6bETlQkDJk9yB7W7 rzP211HZnEdcM581JV6zEvPcJka7GVFSaI8EcyNTV+ZtANlu3mJ/9mb9bPYLxFjsPPsVQDaE6dtq 53PkNRJdwaQPwKomJJB8GfqXD08k663WGZ6/qhlkRJeDmHv34q/GbW3ETU42/jLCAFGi72KNKdWu cUSPOK5BRz3SGudQKjAIb1h2gtRPMCtu5y6hVBFyHYoS8e40Ah6SH2shevSXQPGx9v4KGpuZSpRq oRfz4SA4m1eVPM8LcuQtYZ8STmftYNGdYS7PpBW9uxGjtnNYDWRffN/T4Jz2VndpeZ6RPY6Wll8r CPMbRCKkX3Y0eq9OOC1RLBP8sMQyhAC2B6FZARU3S9OUe205Fjsb46o7gywmHjTKrKT8ikKzd0iI +LQrW5f/eINeA9jx0qzlzpIO78ti49HcVsr+kSsfDLOf63VDKfd6M3KXmznS+cwx5CTzVZHooWNx +Jc5KHfhhz4mRUj7mX/DA1/JXG1L4mjhA5SFXX84Oj3JPK//aEXJj9StB4cOO5WewPp4Iq6CmyRs KQcx/Q/qjho59T/DF96HYb+1NR1bdnihLFKOnijJ9FtEaTDZ09rRwOTcwVjlbg9eC0v4vf9XOzDM wUBG1XpTHdZNnv6iz2Sl0w1mmL0TDBIOmM0aPA698nxCwUJA5cTU6qe40lS0uAXSXE+FglXy2FPQ /xjBom7j2wQXfxolFWokP5Enq6IEh+XmtiGvdIcu2QJsEptt8RYMyaxuKdIB2TUVh58ylZDb8We1 fv8gEmFkLFhvKhD6y8MMgKsaL7fm0hXXIJag6QbW/aeNZtbdu1ZYvtme9t880mf009jSXdglMZKP dXa1iSjE7APdM2zybefPm2mkjuZqW+7PDpW4TmVRh3mdwibYCw8X64n1+lcys6dyXDkXhPsvZ1G7 tQPtPWAZrkzhc3h8Q/DuquRZMQZIWDkoM0VHTyFwGVcBC9i5KORDzisg07CdwwIAx+ctOSv+ArjS xMG42VNz9/d8HUJpu0WIP4xSIMPbOLSd23HzY1AKwpcNbjw0XHECH+si3SCVvmMIGPTsUlliZXq2 ZkojktVTmLuraxCyLx99I0jmD/DjFFvY7tjvOUpEQeMq/yH8m+jniu1w1oVHMYLOaITFeKVfmDjm uv/dwqVgqsJ4FkgszR5ydmAJBIhlN/O1Mjrq+o5X4iCA5Ys+20RMEKnJddg51lGiVoBesoPR3Ufm Ygolbyifir8umrPHytyPyq4plxe9RRQTi3YH/qLr7d6IFfkHdhprHhWr8DPBeGHcyE8wwdzFrnoI jOr+omj8VkGGsGutA6643O43TPywVl6jyClcXPliJMspCQN+8ow7p9uJ5gQ1C3pYwvjSQk7NGsxM KzRdabRnLK5mt83LcKI4buypbkXkHmm2b91Kf+stdCHWcjJQXstHiTcWnwp+RivJEOp+wh3FZikZ 3rti9iCr0j2j47/Cxhg6rPhMQswgNv649l9Q3h0kfKIASPUjJJMnE3IyS/tjqryYSxKfbkh6KoUl TzLQ8v2bF/FpA+YLcNLzCZV5I0fCyePz+5JwTXMSTnXa+Y9u3yVPdSitUSFOamBqmI35fBqKOrKU fAVPAXJIumtpfzzNJD5qRBP03Sp7saAT+UVZTSxPOKZfRLKJHC1/4m3DXksXjT6x/5aMsMHaW9RF 0ej5iQhkswvXlvWRr1Yvn8qGC5j90C57iM9//YONo/9yjn2mi2lMALod2Fd2C7QA6pagbFfylzAp 2DHllTCXfNTqTqpBPBqBQFMaM8sZtQ+7sd6E9yw1jQYSGYnLEykX1N3jtGnNbs8MWF68RidJR5Fi z+OIalpY33Eo29jvqIvOcCnbIJoHbYZeZSeP5MM3OGGfD3+RO6+NVsFObnS9TgMaVH1ZZod9SeGS 7Q1mVwOBuAsTnfZNiiJI0R0Ho6NomqNhsxsaup9RhDUC0M8Ss0dv5nmfZmQ1HDU8J+zslrVnNG44 vx47zv2UjoGyOvclghKWqBv4UcnkpSpfiy1a9NkEBT+lUZffBAOlUXdbaTxYAdE7sCsjQsb3Hn7D 4p9h7S/otu9c1UisOsGs8Y9gSP9NtieqFORX7KMGvn00nDOyHmdB6pIMxMyX44CgKX5c8pSkfBfR vCtlUyC+FJkyPKh9lsG+DWLql2VWJr3Nnvdoo19ZkSNMlox6WVdmNQwCRq8y5LVMR8C5vlY6TF7d xHUuNZ0ekpY/KdT4/t2kqJ6IZmuWmACR8c2fcGTzGb5E7l1kPhRVxwJpJkDTFaolVEON+tRSm1Ve LP6wKcgM3+5hV9k6SUckoV3wFArNPKPLsLXZG7qmQMxVRUBkKcNW2rqjod8Es5f/g/igGrKHLvHI /sJXod+FMBWyG/M+Y8GTvLvnkXyh8FQo1UFb3YGkng8lACvIel87C8+SKPF6hhamRLlMLXzT0NDN E8Y72/VcmuKBYFBO7z9bGBks8wxhH6Li05d4lm6u430vHhIxjs/EoMuYk8EoHzjV06WNGIJjbMdC SzkDX8ZJSVTvh28C+aItK7WF6WRYxC5FC0nz9n7uK8/yqc3uySy2jVCcFQQjvODj61ceY+HpvNvZ /nUG5GSbPnJ3/gEAkCDbTe7qvbtEHZRsGmAPDqtyivYcKoOM29xtUs7BciTvtSDWZuxme36UpsBg M4nT4thOEwt8U4hjDsbAhHYPS8lDRXYSXaaph0bb6eowhq9dl+uTBpR8XVjmbIqUljZ8K1fHb4Cm SsXR2eKB0Nw9rhvpSgH0i4FjXycvJu8DLbQw5yvzo/AdRLm6bXN6mGDs4LUArzQCV4vxXPgO0NJh +cVBuHRS6mz306jRKmr5cD3kCCutbEb1ZO0sEPHAkHsVlRlGaJ+KjtaZcrhxSvNySk/8TaOomS94 xOcKXu/jrYT39lL9QFpvXuHDnihKR8IBeR0zuQOfXT7PVUeTUxwqZtfrn9xRYOa03sfpjV6FgFqe qRRBd669z4KS+HT+0QIk9hwLOuBAlT0SEKiw60zdzBZAIW99TAWxwF1WQxTDedHxqKM14vvDXzpZ o09d0DPKmVg5ehM1WPrg7yTg3qNZMl5CIr8/NrSlljWhJcO+RfmH9jsi739Yzra6ew2VML2e7lBB 7HmVqBiaYILe9kwoKaARpl4P6dmI0VyKASZRvacQiJ6LsDydEeuBKevcOVkp8MW+pHoi+iW35gYp zXQpMh5fXmw2LlEwF8TXrxVODhKN5AItOpPHqRFy/7eFQ20pZgBEymFjwCOvHIOM+jf79CujFPti z9EXb1barx2XXAZ0Yi+kwbtWFRSBpVfRjeQn7+V6qKDn1n3BX6APJ5zgm1dbKw4x/WKuVq7C3cs8 TFbkqqLaJsMxsAbDZeS6mLq03EIdYCNyjeNR20WXispjksm94wfHi81XkowEcd854UnriOMKaIdC iPg5bjA5GKGh3QS3OTokJ7+eisaoZPIEApS9JjyYlIVU5A5dCu+57qm7iFdWhTzAg1X4hXnmHMn9 Wk2c74kloXqBN9KiP9bSWJm3xZpiwhINAArQ9j5fo9NjNvCNBS612mli5SB8vuUSSFLNoSkX3wOv l73VN2FebbzKQa+bh8b8hz/svc3LRpYg5W6PxUz7JQuHAh2r17P2optlaTSlAsIbV+5W56it9V59 9zpS8m+Dn9h6gj/R3Z0+FE4w9/y1BIMA3YL1BLo+lmf5HuItzf1nmDgXoLVO0xPHsQpEH7jlOPZd 0oO3Z6y/wmutCi/MHsrDr5L3jOFmM7uRt+FlbWtJdGOOhpWCeWw8br8cFjuVMYNE5GJuZ95oDH4Y OUj/gRQwdTsAV+QREhjFjYKRaPlMLqXVvfVsIAsClviroKIo/0BZSQ0ZULOGUSvP1UtMdjTDWGeU 6mBu7iPF+HarNp+Nz3+7w353QhMce4t4eNr+V2EgYLeBxWJ7gBWnw1V3BshynpzBkLbd0TAw4gfg /52HPXF2uu4MxG2rO1qGZ8zX/5NQ5UPx/2YP5B3F2e9f6TF43WAOPxwi7QvKXaUD707CNvaEu2cI JPLM4jJw5RJ4XSKalRgVu/LR7mHVNCrmFnZhKEIyjbZy7Moc3ZTI8EBWKE4sFZj+lDdWJdJU0aac piDnOYEMy31roWQrkv2zqQ6L/zsNnIoCp6JOSkdH4LDyD55C6Rsj7Yab9RPfKU2SnK0baytDC+YV 9hbn+W8napA3wmP7S9HIHEzzke2ruIZi6A+y0LulN88w1pLZ+Avyjs/N6DY/Lmnj+sunM+Evr80u mLUgSECFm9/GNA3x5WTIELG73wJKY0wC9LtiudhPX5s9ND/+nTrFFHn+3JsJSpXm0spJ7mpMmNnC YHLoBNJ3MmoNyJ+kf5TzClzhtl0VxJnn6dtPFNtBjzefzndnHEqIIpZ9WvehCJCBe9ZHRHm9oQi9 KhEbltbwLIYq+jccap1WaY9B9tcJOppV4+NeuJmnXyM3GHDWhk7+r7sVR+AK3+pEoP4xxb2d3bVf xWQvP38aP6eLnkMhuVLOS7lJWpSxyDuBG8jjD/n83Mg/hE/n+U9akABBOkq1i6TvB43zboiBhE1B tgPvO5gLxzinLfz/zXCaxzx7haJDZl0pJylZ2G11K2W3ZBIuxGPh0VkOs8WQcLnVtB+PGoZoch57 rI+JEdKZEV9emy6JssT5AoVeoFEzMBzwxdGoLfFKK98WkszUcxaK/hZ+LuDdUeuW4WiLpknMmSqn fihRXYps83IM+9S/X0K+exTqwDVG/lmWgQoZhGvDfaMLHBhxMZMEJbuLY7s3ladGScwQ02/8dzlV 6ftvQK5zjTQqCuLZM8my/d3EtVBJuTTfG2O0o3OCT5XGZXiP6a4MtQSvtyYQx6DEZgMFxGA3UySh tkxOSPm6E1AIZ+cfdVWhNr3ySMU6J62n8oEs4lmpRbO94V6yFNoMSf3xZpHbQR5EvsL61e1utH8T OJfaaqPqkKMs+Rq8pl3RbR3xk3iPY6Uh3xFoHuzxbPv/zSl/V7iANJzrgANTSgeGLBH5Yi+w5yd+ 2+s7idE7fo+HyYJQUI7X6LfZh2Wu0Yv7kipfsXkEOFYhLqQCwCHoJRcIqzoWGoC1Is0wlIgTjtkG l3k4bPIuwi/DuyS3rCHcW58u/YlTYZg/C5YJIQ+40xmZAbm0qgxTbttyQai170LNhtdW8m0Hw3Af hZGejODeH4pORXp3Ih/iH7tq+f7daRiS8iKo+yCoUzcYdkJJg8jVdq5CRIOZabJF5ppVgSuZtuHj MgZ/UifPrUzeDAIkAEM/9c/ONCXbytF0FrjKqhTeex0cR6lzXAxlRURjD/VCk75cF1kFkKhPFNia IDBDwM+XnkxO6xbLmw9QNuZFj/pXR8hvBN5KV0Nlra4xB9ywAL3Ni9UQjYJ/PL/hq3J6u66v+0Nn MeddxbxlcAxImllGwQMdSw7XYqaEjFr6FSxAxRgskOpfBP6My5hSkzfHktT/t9c1aV7g2QPdnWtT n4X04tKVVNfbZBs6V9hLqFsN2caiPK4i14452fXeTPeHjVDiYEzVVLhV8MlTVbmklaIP+2gtCwC+ +ra0be868QRxgvz9NIaPhoacGiop6GUk5pqQeW5nIe2058FPmGnbKBQAmmA21Aw3/+wW+fD9c5/j N7jfTW4+eAAHzpyw0HxaKOb8+3pMSLd30Q3bzZ1N740YnoLvSUotSbcMdPkLWih+yOY9ZUh3bboM k4LZl1+JTVXDcIaRp5+H+HHl5d4v879tgVRSFTPVgLRSTkykjf35HYa0OdIN+hPkzm4v8f560g4s KGoU8PL8Qkl0cRZDj6TblPIi0E+p/mc1xXeiylVVDW5TMcmhNOz6oVT2MOr3zDoN1m3DjIi0DuOx BCNgpZt/iMbMvP0A5tVi6v4uPlMapDsEkSKnLNh9NXcAAFgNDTH4xV3aptXqmBHFtbjoojObkvDO e130xe2ZUEsidZPlmCKb+LXoIJY5eR7caGpGrnU6uXkNXwzeNDEzV5GOjkwHbm3x0XuA5syIqh2J 1IZjXn8sX0t0DiDyA+s4iDJZR6w+MqBBKeOk0S2RlX4qgAIgseSH6A7J7nD7KfK6OEUeu9wqqpmV 51XnKZdX6XiwH3XeVamG2AVQH+nmNDs0UqC7Qw9cwMYkoZ4LFgo8cOMWxQqY6c76ZLqqP716PpNu poU/mzl8v1HviseXuw+ofrhdJAbnO9ZXK9z2rCQh+C0m61Q0niSqUZgynx+gfwnnwalpAxEjff31 X0CvTW680kpCn435wdwbeT5pCPks8070XteofzlFCSK1apb9DkXSit7Dvr4TfuNOe1Mzq3kinjor MGpbr4pxvK3qVlbWNnMOkideJX64v/whiFQ9aUJPzkAwQBF8kp+1XtdOZ7kFp6SDnLvaZe0z+jTP CgMBk5Utp9XiQ0mxBtTbdTfwTRy+c451Wvi0MULkefljrV1SYvKtaBzl9mci/o2qyK3HhKdrjWYa uKFdFGtL72cNWxFSrET+GSfyj4bV5ohbeknY82J7n1A/s9q09goHzE1cU2+U5JrG7UMfNQ8av0Pr vvKJO+gD5BZfcDn5y3AMcDAK8Zh1oa/W2ZFZ2lcC9n1ex4SnCQSbnOk0hTnhdvhUbihJ6Nd8Gn8S seMrr+lFF28sKBvQfSKJpjF+YKa2xpkC8FGVjnR96XlzoAjPC13BmK844NNQWRFAzsBrqW15dW4C K2pW528bP17nuL4CL/98YZEQUShEW71x66E/5I6oFLWXyHBG/pHVxFHvZ/4yy5W5qi37Xfr9D5SH tYJBDVv/1WPdXdZ5FqMTUzSDgpr2EjxTONaKHnLvgNhME7HufgO03xF39i9r+LewnCQaVR5FogBl PhgehXviaBNW7nJGA1pQDD1xTUBhpilUviU7o1LzazRGrQtiLbIyMK8YZTHQq92fmTSxVdc4rfF0 VNZqaT146+A7/rcFlf6odvfXQxINtjTGMe25Ypw94HYL1bbGllC0FFyG/1uh5E7YsCReOK/pcL7Z PA3qsC5yTpDQspvkOBAYekIiq1oyCgXcKoq9R6cXGyd2dcnMF/nF/txbeCQ+zYRttMT8CTZPV7jj zNsRMwmOL4bfEXQ4aQUTV1gjfOjMFrTDuFkLWEIbIUPQK+fEJqH/YD7Jyv2nAQa7O11M6X29nrgs FhiHh5UEefRiN6foAIM2tydaPClfpAGDEVg7oVE4wADP7eUASTtchRrG8g4GW5RGrG2Qhvwjz3ZF vssW4ogeKbrBu0pz7HSyr4PSJdqSTEAZ2SObBSmkfrO5gOVr1BlNKFvXBIQSOA+mCm2tr5NaJfjL hXxb8kb2pxgzqaAnuxPylcp2W+kQIYguCYC/gPRLMx4Na2w+GJLdwlCXUTnS4kC4OYnlH4U9ybJ5 iAcU384WxE7csqOuMyioAgAWaTqE3Gxybg78ysqcKHp8KrlDBTW4O5hUR/PyFNY058eN0aHnJ8Ur TmJXniNXPDaH2lmFOyuxDkiFkA+Pp+Kz0aqMMbOjp6Vii2zlp0JcHCdv4q2/BuBC43KIMUuAyPO1 Vxr9KExjk/K6KloIoXMcgF3KfuI7OUg45lXYfe6yvq5fGHW/02x0R0uVG5F0kGb6mzHCNU1PDrBD A4bx4u1qP6GwmSny2k75LFc/H0wVhAXFNYrEiwCvDLcu8q7FQk12+OG8vFGeZn9lzoATETWAyGwy LjdqjPpSEeI/na24xYuYOgmIn6WBK16LuLeexulYktv/ZYeCpI/ETB0YcZetYtHxaO1/wc+mK106 i32lHzv8GSm1nai5Ow0ECcT+AwmUfZ9qFw743loXWqMb6i4m7Xjcx7EGskCus2CeJp7pcA0bHKKf ZYebeiqquLcPZGvVc4YcRK+y+1JjkNNPBHkUi564wvsvwZeL5XhoCoOFBB+hGXONWKb3kMQwufN9 YUsUKZ/PiMugK1+7zt4atUwXWtfshoAnHkS/BNdyb83DpPc6AMXMKqt8zNeGaVWnNlr5vcpIplQI EcZAYthwi5o8PHrP9PV2aYzijMtq0P8XZR017/TojC4+rCdaQ+rSQ1QTRTwdPpm744/5YtNlXCcA Ifpa9hxSYuSifiHWSEuq6Oz6x1v8msKOnift8C4fy38wVVkwBPuNBEgMpDU2gc+iB9ysEGdqjn2y DoFzo1IriTMJICF20v1KH6ETzXX1qaNE8G29TehEXUKK8Qt1Y1gY9iDbNg9etDyz2zsZ+hWoZlPS +Pm58tOUe/Im6Eimo+dEbtAJiGC5wFMovt0bSRZVxsONWZnrI7VOeAHZ+lwlVgrjK6eRAVDhzpd+ fw0offVnZfPRqYRo9pJTT+DQHm15uMGTxw1QD2l5AZYCa2BZk2a26C5hazDy+SAQdcg3VUDs5POh PLjWyXkajzxPx3soM9CqJzEgtK6h4Nmy7GAPxzkKo1WZWomxQgqjwq7C3mKpFwJgOLXCmHrYgzYO Ws59/eXdRYV/iIZNr/d6TRMzROLuSXvm7hhfL6LfQl8gTOylV0Fh+CfH91r2ACfUDjsyBT2U79mn AOyB26klLMzucbQCgoYNFlhGObibDZmILBfbAA/42+g0RpzYL7wdAmnskDqDVE7BBaj41wYoqPYN wS5DdR7pUgCGhYpV6NzkSb9x0yJT/9Qd6Do12qLCOOauBLGDhb+Fwif6UE3YdRipHph4+mVYabHP 1Oqleh96EWGkMLonBqCWeSUVse/FQglquB0qsezew7ldVoKc4VFBLC6HTr8N4RY31QKZIrUV9CB8 /q3BXvWJwIO6HPDg+aENVsEMR+yvGGB7Nfz5W9awHQwXIMSrgMjGckbubyfhZbiJmTfwB2ZxCQ4c 6+rlqvlASyQZpBhnu6Vv7VHldjQ1U11amRQ/Y7fCV99r4RDB7UA8Spx7gzPuP2O1gYolMpy+M70k AwAx6OggrDy2K72r5E6aIbfBseJ3LlvLcQvxnnKbMPmI8Umu6FV4TzLQ6iMZFboYPH/5Wmb887TT 3ql/pWiKiAMRnHO1yD04IIo0eC0vqNUw2A0p3sdl/gDFg2wXnnrtZXgVfDgzK+9eHwwlIsctfMpm ayTDoggCM0ITbXwFoQba3gO3pq+Wli6tTRtBiUDlAob2vwc95Qkz+N5RJgTEmT9Oj8Xk4mlHC2R8 qZbA+gK0IE9Tu9zr4kiW5S9upmJAgngq1CAVi+A0ksC0zVmEKcVdtQQrbPfAcMybgy9JYCE0Azfd kDISNqQmCa6HNMOfcXg4T+H640xVC3/NIK+ITM+KlDRCUY5XzcOTn84+vpp6c+4M/PmeEDb6h4VW lrMt2zIwMmHymgyYz4peIPCcx7SAQxIyNpXljwEHwB5a4PV1Ya07XoMGMhvvZ66rRZQdFHe5pTnk wUVE7guz4TsxfJKsGbaqQvpnxtElJejwWtQIQW2Qn1qgOUvt3snMTxqZgvw8wUxC4nRTSw1USKv7 I+kaesKyRZxdhPWecanRW+f7cT2oZzP1SuZHiLnf6FJ564BndiaS0yquDHt8rIE43c7FjuqXxzqj mWrTlPJmp3lrbsfXiuy3kr0d5XQbdannIuoICpGZTsnOHu83wiSL7LJwlvjhcKaMdJ4YNjpG4uQm aDP/TiDMO6XPuqT81oVrB5A6R2f6YdmGTnN+3cZD7qCbv1K9o8gg6ToiUv+dhPd9/+SKfctdaH91 4v9Xb9wX+uzs7I1Qf6y8Aw0roSxUC6LeuF6l4DOKJTsrMIwWwfRM4d6+bhIFtWyWt2VXwkBG+uNQ hqFkms35fihbifLztmY5OuVqHlXJHui/mOwOj3AtBzH49Rau/aQZuGH7yl9ARqecgMEiW2qmkbkE ROx+j5cilk1HdJEsMzNGOBn2VyQZxtB2R6qbSP3xPAPkUrjXbsMQRDhqMFQbT4yTyu6l9tOkMOjw VPMTTxRbsEN9maaNkRmvKZ16zmp+PEyApq8vKawpEFTIT5F6uDb62F1TSxVea35MDh1ijVsc+PLL n8nSLVLkWrW8Hlhta/UmkfVz0S7Pip3/VQz9cHFVCQ1hHTUdeFC5aXOyy/J2x4AOB4gMwqKT8Ymp u1sC6dKNSrOA2kTNgB6k04GRB75fR8E3FRWI1djdiSRlhhAuJpXrKHTmRieI0/nsHh067dVVU5vA n0eV4YaJchhyQ8VUJw1h50m2vvyQhtloqpLUnXvEcvF5U+NF2vCZeHvVkG+jXIQaIiNK1GNykv4t 06z0gj2UNQhOHKpQzR6KdI5+Ep6+6EAudj8K31h/1MKeqCCz9l7EKcxNwMa34dZulKvwbLE2h9Qq ZQcx3XEdGtcyvk7taHBUKhqNiHLW/mrzkL5cEmm3zT/OrEfPuT/J0vLin6T8rES5OamEJrPSJmte ItljPxc5YNUEidUHAUwAdYyTKqdDdqwHa6uEtzklzdaTLTu3twKT7lhUrWxMqRlAq24TfsBuvm3e c1R+U5uYK/LN4UTIgihjvPE5FxgR9EYmVcTrf0a+FNZWo+dFiRUs5hppASJcz5mU2akwmsrAyslk K3tIi0jA5gvk6Ze9YYNDlHlPgAaFqBA9JtZAzBPUXaRHDuHiH2zWC4SAg0NLI8kEZ3zmICm9AyKs EIvSfikHlSpBoPzb2yQoqtAGZQK/WdQJA2byryaJ3epQWdftuM9lS25w9xX/VWMmGz3mvpHnPkkQ KYjLsBrKfcYsSW7zzmQvA+Hv+jlJRyGCZClnelZHraflH4Y4bnZLNpXHkdgVpdzxnJ40x5lHnM26 0sWVuU0Z1O1LrubKorxM1shbK70Rk6gMV2NGdyQetrT+O+ZPg9IPD3o26E2SQkUssmbkNdVwVekd 7wxvOP9tXAiqD/MXoOrqeWuGveF1NNgnh9JrXPkcAIPnSdU/IzXTIckHftJPa/8gSt7qW1awo6yX 4w7XXFgbRATuAKBh9iSPr9uxfGr1/S4G8WX/MkJ0lH1iQGDT8l46i+j3kA7/w5jXJL3t4aZgHuD+ 1mNTbjuNmKbU7NKmp3cwnkC5Vuk1DoGVUOQWrWjFYm9sFtqP4RDmr/GWz2A3j6Ft8/4dBjVvtiJ/ GzsXp5rmrxdHly/JJGBrtVuIVUfOh69UOud8IHneBd6M2Z2t281SWx4lCkeceEK+CO8HW44fpWaR JUetOVadPFbAi6TpwZ9gr8MF12ZUn/3uH4EZgItWHZxHdgrvUxFIL0T9gnSrhCcDP2Lm4CVMNS6Z bg04uAssFIFPRZ8qc8cnzUOdwaIp7cAsGTcLYXJw77Udww32hic9gwF5H0F9ld/Db3pEbbvwA5kf AZk5hsl6keYGsmvTTWYPHcBslucrf/C+zimiBn4ML9ydDaqpvhNscUniRNo/DeiaUTRZUhrnez1k 8jNRSTYop3rkOkJ6utY2y0uLEtJAVfUMFsqPZfKWqkxbPHolWi4GofZw8y81s3FcFZKuOLQuQAe7 HTdDzpboj9E1rIImrS4hjcMsAMRJAeyWxxiI2Ed3ZDuJJwWQXZp7uLxVxS4bTTrG1zNuJnEvHUkw fCNnXVieT3abi0/r3GlqjnEeeo8O6IQ9ZVDCi8oD5UyG+XFkrqdprG5AH0o9FTUPIW3fCzsche52 kfscEzYphXuIMkfdgDbDiBHCqjzTesQbuK9w6vUMVSmalZCOBkHhrwirF7pMh+CRO+DcgYhI4zb3 pr7FeS5Ip6iEWy/iVCKELiDJ++wJUXrGK9IKzm9W8qzuavWyiG8fPmQwXXRcIGSQrIDTL+cCTp8+ ml4lwjaoR5y7nB+FEkt9uCqB7V61L3W6Y8VhQyi+l/7w5TBdLWx0dmquZxfAWmUGrWPOeGcjlfse zppyiBN3jHH5i2ah71+sNLeTgshgU4ZDyapyc+cOT7/U1DKjQMBAcjfIcjDXrLz/GYtrigOh2b8c VUalPUr53VoR/3GirXNapVmDnHWZugMgBNGdnCnWvCLZLx/rN04hcs34xflbZvUGYLjj4UWO7ppv giWlbB+3vJY37qNmOf2374TPZKr7lt280rT8ue4sTnPYdMo2D7xz44jo08zjozIq78ivixeNjUXp siFh7DI6qkVIJC+DTRv1JfBXKLHREaIMpZ2YS55i4yH5YHib1x4bHTp4QmCuAr94xXlPUgt+fpVN 7bryj0t63PgjFgDAFUGc0lhAJxx4OG7LUdW2haYo0gXWFSpUcrtOLT2SShzXSHb8x8zxIiF0Pi9F J/aPrwmaBoTSgJ/517CNDuDAQ9DO07ADSbR1BiBYAub6eHmqSA+vJPjepTGq7kQ7G434gk19uGz7 jdjCQVvCXm0NMdhMAhEzazwxiXecsaxdcn/QKODTndDrBHxf172AeFq+RM4WtohP3rLyjABZ3lRw N+TtXeFUkT6ntoZB+0grcFexkEZp88MV2XR5xydNe5KmIHXn12KDcJ6XVTdBYMaJfsq0fhgSXkRq YIsow+HGm4FkuWJ6r4CZ5TsZlOVTVejBAsuqZKeSpx/XmwWVc4jEdrqZz0VgpN6SJaGjGCyEPxDz ZNwv46RnVEuPvxc0Q17OR8YwuxHyqJPRHosuU4LTZjBtx8TsZEjEOHoh8rD0nJCEBJdQ8Rzn9JHT a9+nh6RQ/cn2SE2DvOHXDd1CD/u2X2Z8oS05zgiDNdEyvhGOEigW2REYRgFfHIPODXtbHf9XIla0 I7H9PISFcXmxl//GgF0cLjHGhGEikgYo+WMaSpgBjSFBTJNq6jr6lTQlk4XcYEEHvehdNVSk5ljs Ib8Zl0zVXoNod3KPpWJM3h1y/lfMgUvQmrz2S0N0+swK5iFpsoFu4o0UpyskRW5XNkS2YpBbm7nL T0nWce78KcOy2hAP+HZPeQPuMyA/PBTxpU8XFNf+3G01EX/BqvfOfnXXFGGT7agmkAIxKMVbcnBG OwQU6lBOctQu241CE6PSnix+k8gv0ceHYLN4DgiKJDzXAKQSm7m8Cor5td00nbfAdqHFrkyHq8CZ eE6bBull80qgVlLCA9apMizVFdnCbTcWKINPuJJbvnQZIaXZcsgsdwXajTzvGe/l9Cz8aGK68dsR rZ06F5GxLJLurm7DD9216q5at10HgesSK5yK3DAsYu6bQlQUgyRA99mArMcoJnHf4P8jAq2ZMHhZ QJu4JP3fS+UWvzulu+KOXfMV7NDMHoWtoeJMf275eXppAF47VPKbPEmKnsEdxfw0Jmrb4IopNciD Ao93Mddwcnil6VUYdmQqnQMC/ALBNuVvwBk9UJFWS4jDBVt47vjwCRH9GHt+bBP+WEJCJOCM0ey0 LGcELfEW9IhdKi36SLQPTsk8RRgbDYSVdfx7DCqDXkdWV1YTLFf7xFKK8SWDSYJetNB2f4PI4g2D iUlEajaC9xCH/851HxCWQZxEf1LUuZaWkpxGPTsoAyOMGip4BLUdgs0mLBaVPZnQqdA0XBkctIQ6 YZSW1epv9D9hpc5tK0HvkbcODj+yJHDrFFnmvz3ufV+Z14YPVVUFiKl0sbEsqsprKkpSceyVl7fz MoR+dk/tUbtI2tMuEsp/XnHG2RbQz+DcT3Y/VQOz0fJs/hBLbuBrugJuxYQ1ww89RD2LFA3ZwLal fs3GlQWH958kfrrasBYRorGVKDJxrnv2iCGIeHO5rP3sWIyFFDTKHkbNGklrNw90RcGODb3ER3Ck r/UCzFArXK3RJMawm2ugAFCVqNfhRg6Ito8P5d+JpZ8TPGjU7y0CTubcVdSsaMn4+Nu4lJvSxGcP +OPAEShmzo7MdUFvBuVrTM/k58VsgKmqmfh4qxxWS6Jjf7sPeK3KQMV+teEcIRqrfxj1oMiu5vJx yOwS04pzbhltQYuqFknh2NWFxdt2sla20ZgJc42tgrOFYz4+VfNJ5YZySctJMXLgjm0UxQdmldkY veEg1HByoOUAnAJHhg7MHAaicrFLCg3Pm9A0SS3UA+soNiJv9/oXLveiE84HUYlzhBO0LxG/WakR B+gIS1d+8a4Ngrd78XclIpXPBeVqfrBobs5oa79irGZtJcPszLv0DvqgHiONY2Ui3OSuimGNECwu 4lPDj9Fj0F7/pDClYVkC8pUnqZgi4qOVbElJytNwtSvIWlJMwNemJzUGgK67rjyzHd93ppM/5vEi dMXn6oimIfYCY3jBI2hc5qT439Z9dkgXqoabcOTzR/4QbLnEo6v9v0yYVa9wQwBJB/HiiRK9/J3K NtHPsBSob03MjQgualQxSR6RPQsoGMfJdByOEwJouPtoMoaArKOhIJ0GruL/OmCkvbmVEKBNcHwE fivBHxF6xDu4Tsi6uhietl9Hq5H6VbGceAr+FSsx/th+bfKVdaRHxwI4y0EQB3hyAitadAOkfBQp 1WvVbrob9Ru5g7qGuP8k4ljgL0zP53FHBBcMBiXYRjtFczqPuK9/d5ffNadkaod+U3K//2JM2fkO qs74cdGM+IP9916om5+gbMbklIz+vkEiWje7C1YPbTUJUogSfidTCU4w7X2HyFL5rFoM5tZnsTLd aPFjNNkKHylMmpDEg4gjKiuKmgsrB3rNMzHWgmXGi8sISySqKVr2ERIoCMM0fwynAhcxKdVmsTTP S+c0yYbDMqaK79itV/fpAnt5cSjJxGiJ7UjsynFFclbdTxFVhx6oKiFWY4Pqqu0xi7HOiG8yT9PZ lF8CPwMq37ZVO2XECMS1XAL8rfaiIGYYgs5lrGE2O9SCXgl+6kfUFHfeNei13dFuZtqy+aBSgzf5 FrMZ6ufAxq+MHHpa+pZFe2sGX1ezol25sdtx2fvEIQwcgPxOeV+rk4cfw4DGM7XCtx3618T5dnG0 mCs4eb3uo6kNYnsTiT43Yui1eC2otgKCgYEHlAe/+qit9GtJeZ4MuDbp/SN9FrCBC11XUXnQKsbI t4jia9HVWBEudf8LDbWDuiYdfoRad80vrlLRxyhCpWguiwSb1psZFuY+0uwADLF0q8Kk+lZRE+jr hMuTap/gVegsNmIyX/kM8r7APPnIGeUxtcDZ1NuwG0Snp0cAz5faq8hgFnz7llA4bKeho3ya6kAg TQuheNI+e+gFI5NHlIS4BD5XJ28nTBe3YMt1eg5NH4Rl2PJlqmJ0wWiJEx1SQCD8dIM9eCM/+G9J 4l34s65Ag2h3wanDfyyG+LA1F6tC/CtapHRob/TnvvIE+sXD2cvxsaKWb+PPQ+rAfka2my/2XKdu da0eq1XY7Rxw26ltDJ41erOqlsIbSZ7tGGt98IH7NAuZkvgzTfoHHOzuuH+CI2m1VSvDGBgMKd9A zczUkm/jab6uZKGgIwiEl8m73mq6b6yP4ym4Xu4CtlvsiAJoTnrViQbXH9CR6wffoi70Z60RzpAY tULLJFcSGwEgoyFHcq1SecXd3OoGXKDApzaEiTScRt01EH3g9V4NxopkfRxxn4sG9br/QOf6OVvL SbX/oYhE/V3qWfjtcHMGj3wbo0ykvw7sD5TtBrYRVF0KTVdFDBINZ/KIaIZGirT94jxV+OdmWlip SlWc1+FP7eMlO34EmqXqn35Sn5kG9A0UJUkazdRjs/t9xSOt/mJToKQ1QHwKxYzMvs8Mxp8oUegx mEGlk52LcVqyhDsWqQw/LqJLws2Pkbv8cCYitU+EpfOtQB5NSjxbavISkFoLUbPwDLv6wHJPxkPf UM40Etsms5yAEk+KKOY1vTBfJ6JceZQFoqmCd4l4rJWpzCYS22ZhNduhkeTIra9b2wioSbnscPIc gzmhjoqk1tBl243+Nu7cvmyMW4eGjwPX88EtmLzJx/P7Kw6iwEVmKPGb4UhwGgM039ZXWx1qkCSG oF+RHid618neFyhj2oJwjLIJ9hKlOc4ufpT8RuTBlWgzmvS1GuRg9IstpXblCAOHBGDne2K9e354 UBuf1LOpnCoiBWcORqKVanDKtknnziX0p2zAGFKazUFlOOllSlBGYV9/+p1IRDqwcfmN7/+mAu8d cJEkUb5dDBeoFObmfUsj+hjDarRRlb2lqpMCt+ed9Es2Dj7Jnc51yVRulAlda41oaYVQ/4K98nNW P7XmI31G3rwkmkG88qp7OsRb6t+ZcKmW9emPbSrBaiv8UDePMqdsC16m51DTnnti0OidoFOycJjT N2gB2f1/XJgzQVkNBfqLDhzY9R2Otw1R7WDnwWVz0YZOzlEhi7coulvbjbZ0pEEkF2XEht6gnt9+ lMzLqyh48rJfyVs5SU63epKCwIcn4WYXj/p9Vn7hJEvPej2bJffstlXwtkpptwJKHsdtOlD7+GVH qJvzyfSH/llcvJtetxWgKDi46FSMtsRXC4r/G45ln5slmP7kdSnYVAJv0PzKAcGNQqRvm1yd5WYZ t+Hj2YSopMt+qJjgaxRGCA/G9ecfclXLrZxAl+sCxTKoBlCtwWzYbt8B7XGD+HyNvTysQ+tuVTCA DRrx1jHJIgDHFvC0rDqmc4uctQ7Y7gIGOJ5iFU0QHxpJ9HcrMKeksIQwWnPq/zcTTvb1ZApl4pXh tcN9TjM3vKJoB+Wfqvcaj3/Om0w8Ud2mC93YdDBw4Gud5+jYyNfcXZWo+VT58QxF3hWNOu818Y3n IIy9HJzr9/gs1dW/lc6t8ff1f0srjsLDi3LLNBnqnpO2BTXSjhPB2LkWTiCeD9kl3ooPj8H7npRs oLnrYs8zMxyyC2w0OsRQaXjD9zBD5pHF70rPTE3IJMFkqPO47T9vzSEheEfVSbm0xMI7ldZ1N/2B RfC4yrsE6k8OQiUWGyYsmZQPbDCnxvITYPLRvfRqUI2Wp2H0LuhF0ZI/2vRAV6KC1GM4ONZMOJOl cAKrj/FslmoYEXoA+hQThxW7Sdb6ZLsszbIACRypLFQlAgQVb7MV24p1KoQeq64NB0jpf1Hw3b9o ZnGYPr5/d1f3LhPayYu3P5xUd5PC0XdebgPGwcSbj4QAKfTwybT4F73FQunYRaLnpRkE9ktKKFQY 7j1d76hTVopkjaCkoQV1B3DQqIT4jsyTVjA1QYz9LsIdOb71P54trub35kEOqcg627uSVsBb0pHp PEFdhS/j3w8mNjSdEkfhG0dVyqOJ2N1IlaaAmDMShe64hXp1i8jxpH+acNOs6wfJKVXDgORAnH0l fj/NVnE8oV5k8/tbf5JVUOJNdX9zqgfxgd0Wjvs3aIy9z3cBBk9RW0ROGZo4e1b3ApcdnZDxIPB+ ORqxWwsnGcjWgSRmxmyGLCtzE/x2Be3yyl6pbVyIUDo+7rDEJ8kRuIjzKX/22Z1A1n6dQiFqM3lj xiVsKjW558MbwQXVqpMZEaNdlMGuUpPMZUJsP3bFPb4uuxj0oS/6CrZMFjGP2wzrDmxkXOZNw4Aa JSGRsy17JZs/BEivdUbmAYQp3oeqgpLtx2CpLNRFReO9mGwk9/OsrEIU4jTtanafLuwbzGx8ABCF wQbZOL40C1h2j2ek7BY8E1r7287ypFGZyLAUQwum8yV9INdXh8peaSLau1zTXjjp2WvHbvCWsR5A 3qqZ66NhND6LZzYPnpvLitAfo5jF6d5rRRvrW21xSFQrFDD5cGkoPF6BVVf0qVXy18QG57D+9TOd HDcUUh4ASvFsNwCzPquqzWx1LRcFJXD/TIQLsLth0mIX5XLp/N9pAKnJhew+imDbBFZxeUyj8ElB xVb+fe5GvGdFRC/OMdJBYZrAqVAp7E93G/EBsdO6BgfeiEyXNzvfGSZJ3XJP33ObwyfJNkZeuA6z RUnviWWV5X5eHaIjrgjuhM8g1YJOCF+OG610oDlYDnKK4A0AJTaJ9gs4wpVI+FUYH/uuzts/zvdT zIMU+6JdzQscW9iYS+IOCI02I49K1EZYfjYDxl6PYlgmDkVkV0D13/ItCMz2UFr+SG+nEQ35CXuo yNeQ7dvJXN99lluha/YM26EY5J1ubfa/SSNCvCOPqV8o2xRb49E7menc9fQy7VBAHgcQzjuya7+x F3G6E9yT9F2Z5EMyAr7dx8iDoYm7c5QHDsXMnh31iTcbqJW9nnmd3/A641a5XERCAy46ODHJbTuJ 9CySMQtL5oXPL2bN9JliWIvHgaBDFI1ROWSXG9k42TCA/rAxp5B3fUz3TT/D+jJesmdiVj9QI9Bh yqETBTPh6XC5eEEHWm3Oh25bDZaB51xyH32bbtEaMcPb7Irwc7kPSrieOksZtads9qncIzF0isNN EbaMl1wROCfVfLL/JpDkJxZ8KRPc6UPNth+BdFH/lTSD0VEr19Ed82Z9v6ksAFV3iCoV15U1KePX wMLDwP/1sTtWcCHBnO65YDTTV0TFCme8+ZmHmo6uVFfE4f5l/OS0zkmvnwcaErR0ReiFFoEK6jj8 qN+Ev4BN9vsmNVK7Cdc9novs9NI7EcquD2XRVNpzx17MQUwLRuy7S/xTS1El0K485P0koWInEmrR S0FF1FF0JhT2umcCwrmdZ2L0G1061qwDqsOHPAeM8G5jZ5Y+/jmt6zvvVpxTyUqkSiYdkhK/wmLt jzu27xPlNXwiwhqwMJd4kSdR3A9lI6MKezV5pzVdLQZdKyxvp73fK0AiWVSEwKLR9RQMjjSX1IIP 6tBhbZ6qMqMyeUdFF3CT4U1mZhFfzEUEQ5lDPtJnKPa4Bwq14ZJ0P1ok/X0Q5FKEHb6z0iDMTIRz /mvkBWRdexxmEOXDg/Zlx0L8p/OKxCc8Gy4soD877ZwW/tnkqsn6EL0+NzYs6TlZuYxF/mP52piV r1pu55Eyfc+pq9hwrDLHMCeG022ecc0EuMOtarRD4U+XuRcI/p0skn4oopgLBgDvy6U97Ka3/TDq RyZN+uNzeAb26p5eNPyZnmRo+mLU4EQ/72zymgS1N/oAhgX9QAeFkGxCWPc6NAUMhosobSehmJYD W7JOw8TKua3l/n+ZQGsn2T/LGPo9THDaAeYRVFNqyV26cg9aAa1sj0Zd0NXWJPXDEWT6Ia9ELdOh S6tbmd15tRJXqx38WxwWJvy2+6bLDluqQ8hqYkLgzvnpQHpZEpfxYaK2hDk4mYGteKvpl65NARiv gHg3OwmMEz7dWNQYkTag8eNgHQptmMGjQG00oqIgehWaQoTZ2mLFlA3HLieRowVwsulMMHyFgN8v BxTJWTp2tkU7//mYYwVtY8AXf+fXh46eVmlWQ0pX5mPB9jR659hK4aFAKrccet9/Akim1Q5h/eFp e4SM0wv7JI1oPBJ/XGtOVXxijbAEFJjU7NWqGHgBFPb4fQZsw1EUIZzekQmwx8M8I0r96c+2rT0N h2YBYvFNnUCCQVsqw95m3OGBFs8jRXi2hflz1j1GagW7xUYFtGxQ0k7KrwsmV5NAMhUsZEWWX/4x 9+3FJN9BRYxDp7lRMDp3mBGkAIZWGRxiQPpVo7g2G/jaVIgPZ2Gp/s1l2dWBYlpraI7gs5EpgimP oKzLLceW/y6bR29mmvv8yBRA7pylA2UtXvWZJdPl9FzfRGylT8aE7dG8MpGzBIP3g34ISPLa7ejp TrYY5SWtlGgyysJqGGq7XfeE2D2kBtI33V2f4WczJs6FHud/eAUr/8D8wWTcZq8pTfAgpa3TiJxI cQk6e3bxbZs44IdnmEoq7Wa+sCBVFkEdReEnWMhXlux0yH7y1pQiR1do7p0XWmI/4c1XWUS9/Xja FSu+mFDrc102+8PChX24LRG7ps/KAEckey5U24EDe56u4hEOopVfwDJbatgNoh/7WLi7qmB1ycig /LeZy190ggbomVEdHjphet6fToKpWKoKpjs4tF6xMpJTpuIwnYySqyo87aNRhSsAmERrhJJgMO9w v1G6MbZ9OzFYJEcCcToixFperLKvaz5AbPnHpMBAytJqvzm+5x58YIsMH15TBjQjNpBNnFGg6PQj mU39bHvR9JwchsHMazs72VbWswwxzb84i8T+/uziMlMoyCvVTETRxsXLWXVieruFx2QEB6b0cuoQ rQaXugU7Ph5nR9Ib1HY30Lzy7DH8anhCHYYc4X1PQGloI5gZ6P4BNC/rA99m61pCNfagJtf/8+AO acKirgIStV39IGpCYeoUu9VvtL0X1waLonudUwZwEICkwsfF1YNogRt0GVE/FL+NgqaU8jMtkz3+ UKJCtTgei3wpKii7/3cwdP58XjlADlOFZ3S9PmHBVxsfM9liDRHxq21UUbaUIt2nMbOjgecMGoXU awuAMRcblpadzp5S7SGt6Ny4BgJIA0tGUGycrkOObYpYVSxw/nulNELkpoJS4jHbe5UlZ/Vj2W6r 4uds+HPvARfqFohzf3qAlLEiX+/PNfkS524EENyM9Is4XLcmKwlH3dgfI2eaYtwJA3dxzoIDOGhd 3/LtZVYhGorruftP10cMHrpssh1+FVCzrbmhHVjn06ZqGbjof5rQ8Ec29P1ZhaMllh2ZG6g6aIOJ pGmMXqtP/4MEEsR12pPcKGV1ihKmLGAmmNQMuqVOw2+a/UtDWflTRf//W39UgIXHo8BCYm0eA9G4 eaSO1e+tnA/9NJMBxZaePFn82N8ZkvLJXT7sgiSbYzrTjGODkgXGO8vNPpFC5UJExiGZG5ogcX+n R79WqLEgOA6z/NZgJ+ox+oBgxFGn6iLeFNknZGyK1UtJvBikPc1luWLQ1HEkteMK7mvVNg5F3SRR YkOSzDNLRBbZ3jkydYAMDkVMY5BwZ7u+vdj+mjGj/H+hli5u8DdcrEFOHdkMPFw9VoCTF7q1EVZ9 4wtWlTxXYM6gqLdMuZy+TIP1UFw1BGF8ho3CGUaXz4mZPghnzQX5ANE9czS6NBWTUHYZhE8DTVXu PhwomYg2qhegaMa8pwblfmJLEPWe4HCdNj2sndIVfoilUWtpQ2xX8raUTq2Fywcy9/tJMZqBixKV uF1F230fJADVesvNQXGBaaKA5YkoiJBDEEutfWMg2jw+CNIue0rDHrXpUFyaINq7c1tAzlxNak2R embtNi/t/zv6oMxT+YHuKc5QGWGd2vmibsPgryb8pRRvLcoGShDrvuH/XrCnpQTClLL1gbItoXq0 3/fLC7BzNmPSPmi/Czt964xFuxUmg4PJ++QafAr4JcsZqPwjwcIqjQWr8t8TVrwiH7MkjsEWr7nq 3e9ob2cPnnTblS3HrKMtkayeO7BA4X6aY3gPAKUnxQfBfgrSCBfjo/wHmm3Lyd+3PgHaK7akKqQ6 uMBXCQj7xQSLZMlUvzdTJKRMTPiKvcz2sMuLSU6Agf4IPoNvZ9uuFK6Ip5QdcIiSspAkR0ptHze7 p9HE2HKs9SF5nnC52XXRsdLuJO1gfmeUrEUVqonZ/Au9EuK1gqxlHhKo1IW3y64+KoWF9zyf+Dup KZ3yAg39uUJEyMTVGqHAzHn71slR69UaPPL0vlDPlBdT22wP0po8SD00N703Mou5b+k26GtvgzTE lvfWxgnQf31pSlV5v7xlkD3EPU45q7PJo5ahchCogPV9JEuU0xKNmkkSOfy38RBq32SbvnptBC/h TLwj9LbvG8nbT58OJJ653FfG15Ztsg+QlBokSPMjBRIc9BDyB3S0chEaD9grOHkQJtt28wXRLl0/ zGaA4+vu7yu5e7d6kOXT6Pyl3cbXLE5/X81kqCX4soEPP0bRCjT2CbORjOkNslKo0xCJTv77GC5F mr8U+YVqGwUyOwDgt031hHJ3S+CqeeTQNd4/EwMzUub1HJxSTCJ2CZ8XHeSrn30q9fUsKdIfhAEv U1FX+u3nrLM+ZBJ4JPNmoyLrUu1FVat/vIOD5rpPCuaTg+2bBQXLT1bAtdGcFuAd5fat5pzuU1Hy nt4ZMaxfW9V8uWdGdZNFOXvvYDefcq30fx0SRHQyiQaiDtsc25u58aah78P1M7ANIl10uw2fQ0XC gA/f28GEqs07FiaJpZHIThDLtLDL0txakRFP7DHkP+9DmF1tlJwVrAwK+pF6Rd7a1n/rMtmNjpJI bPguKo3DRooPskzlNSYgwiZwytd0QzfnQck+jYpQUH3cZ4PqOPmGU7dsVT82EqJZLyCBzDb2R7km +uOW+QOcaPosaBRPw8dCRGdnJiXsp11qNvx29Byj+wnNAtk49njL+7Nk/DWBUuECYXUAsCDjJcZx YSCBt6WOIi+umkOfc8qCNv4SJicZgU3SvAZUQqZNnE7Hxpyrb/+Sz2sbqrfeLhBM0v1mfYDv+/WJ 1yyzZb1H8E6GX+nTPN6iwLKCg5QtE0sfznBkrxh7F/B1SjxMwmYUPCPX8LsX16/XSxTS3dIZAQrS dU4BwZ330dDycXjkeXh6I+rJrGXqV+wj+r84yyXfftX2xDB7/JwEzNmDN25b0/+X4VIIVVyAeA/K Zi8LTHw2DYZbsIvGPk+iCz9wDgkey2di4fmvqlcrIq6d9QOx0nXahI9X3XjKEl7soMbohGrV2u5x 1xPeSosfTiRbiE3zz6cNCWdr4GRGPeWXb0RL3qfBKyFOX/uo4pzg0yvaoyCxr4y2yA3KGh/hlzJV lJTBmpVmGmO8Y6WfRtCoBsAqQakPXKyBtrnNQV2cOglzVMi6lrC+hCF0oy4xjWEDoUGkI8YTq653 84uSHz1q5oXonRxyVY7B5UUyW22AJxZX7pNmLyKloRy+K9CVQLs6jVM1VE3ogzkrnwJL5y1aF7o3 pDYROStp4R4jiaXZmeGO4deeawfpvLwYpyBrJRBLn4BjQNx8nT2k5uQmurcTEHkHrN/NR4tr3duW eKLDh3yLa2XoLW0+QgJqUtJV4DIofgabTxWHVjpSzDcCcMUYkqDDNqIsoT3mIUMt+gBuCy0I2piS EuuPDAtf5vEQ5UtEWzjZVWx5e7xiZRnKWNWWQ9q47VMuTPa+9/YdOzmNl1CgzU4xGBMh8iFRISno iFY6+lwjnhmmvaiLKmtAgrBl797w8KRir006ehCio/dw/tPQkyF0pVd765myCqw6TaaS0HOBWnzO dlUookn2vL5HCpebV3mPGMCF/FExDlqyuverVI5/Ikb+9VbOp065NW2z0TGJ6g0gvVs6otQFRNlG cUBsj1j8vF/xXAKG1a5gwx7n907z0mTlMk+/05ZGHUkvSFyK/eXt/ScgwOtb1IV9fAFGtyKDRThi iIeHbeKKRVxl8kOOMQu5Tc4i/1inSxsgow3uKbQQew7Ya4IFhZ6DNbX0ryGN2CFBOKxUpOYaX1M2 63fCXRv8KoAHnbLh9ljK8zxL/83NS3wgjCVpbwHVwAyl3/9lloQlZ269RJl5QfBt4A6AA8GMrHBJ 0YAii8EXTUIqHP9U6wURtxYTRgDhFb3HqL9aKTr0y5+oCVt60dYsdx4ByXOinKEI/QhwM9G4TDer 7pio2YsUMMgqJmmXxBQylnM1RfeoRSdyOnJuc9P7CUzCkKne0ktZypTe5XTu3dgPZA0HJvWNzLCo wvnIlqhCH+PF4R/nzptirgHLGzcM3VXOGRuySY+01kbg06HUsKBffei6nJE1vfpE2x75h/A8KrRw teMXukrbPBMqvkPv6ZMFkVZgBLtNcPm1w5+b+qScP4MYYFIsKcDP7dVcDPCMVW/VNbR009jsLd1i zUn5S09s2J5cJ0tdFG1an4Gjbs1tpQjp5EG/MPBvE2/rliXKnenK+e1nt5v4BS/SlNxBqmqHkEM0 WuXJk1cmgPmsWjwLZQHdpMrO2ptejRmsDlbxJPse0zILYJrONjD4OTS2c8C81NASCMYgXslf9d9V L1gwsVB5KyZt3AdnvTn55f5PE2ho3ypyWniOzSQpAlLYwUTF8yuv9Z5ie1TNqhbJ6xLA0vcIWR1p fAllsPpwh0kIA4T8cK/p2zEsUkBHhl3/MLmgLO/2rSlyXKrxHLIb94y5fRkHcnf+Je6brluBwdpy rez4qmbleqqrZox57ng6zZZRVWOTO6lgKfAcdvQqKMr6adIElss7Wrv5ruCG/Cbs2cQNQIQVQ9Cx yNuI5A7kaJYpaUcHt7pep5XuUizgrdu+sUorbLevlzbSc3zLAno662fl9S/mD+VzqrdrZfrW4RqD E6YW8NP1I/f3U1XPhBRXmocE3tsfci0Cr0BD/s9v2i8cFJCxntR7kmnnGk4eg7Z5KGDBwAPA/y6W qTdew0rQCTsnFOzyUASj82ltJeAeb0Tbv5J88F8Gztk9gkdqJGTHOvezQKnybYCiAK42EtXX8vnQ lx+iaW/U5zIpegfV5d14pIColdm9vNSp6t++0DyhRkdLmE6RGJ1CCg5ZkvFQqcuOcjf6czQyl1Vw n+GZ3u3yK7wwxCpMvLFVwtlKebzKfwcIwO8Mn8oc9xwI2zR4gk5vH9JL8qGGlCFOS05LFuJSYgRU fmbgQUlVNAklH/5cXwoXK0jb5myyyC3ObkSJI/BC6YVjL6M9hHTuQY94rLsMwfSrC6AzkArcVDFI +UOjr6oTatGIwOT5lNeGQIh3wsnRIeVZDeMGwPOaIiq2+G3zo0N4nmjdA9OUUNNGW5kYtYqtxJ86 zrt/pyVEQA6j/4t7wKHTRTGRLcIjLfjacuGJuGj49axDKZWS59nkGxQNkNkO2D3ok9N/evlwX4uz +VrpTvxEBka+lauEcHj/ljzWPM3me0mAsXaF4qzUuMSiazE21s1ekxBS2+0FjVt8yv1Hq0Zofj8O ZysDFucwvelv2elyhQnngrTEOMRjn4DVuAh/OV+2P521ba3dNMJBlTMvX6aGq5wPVtt4X/lcPBMz gtOZkeDkqTzpPh54NK3Kb4qww/SuHPthkfsKjVHovPPHEe0KFIcxvxyVQNIIsAFJsXPx2spJXW5S 93F3k5mNHZ7UaHcnIIq9uS5oUij57Lma2sObPbRi7JpYpHXaHgOybC/g6EAg4qlH8g/2dgdiVIHz lO1gVvyGYqbfPaGNa+3KoUuii3bjwiAxipatZh3vF7V2G9kg57QDmY6Oc2VMVkHZCcO+419tj3DE q1kDY4AKIxz5B2jPmSumAWJ7H9QhNK8lptw8W+SsDgKeViH96XApw/in3kmgEg9Jb0iT7/5YpUA9 5efgb0skhfvLNFu3JZbWrAJBUyzEk4ypfKndKRzhjTGMtPd4s4Ori09XCLhRKsNfj27bWf7BCNoM EygdgMOQL4dmZOQPFPThGnYotL0F5XoByRghMoZwH21/QLPOzVhZbt7pkmt+6COoxPJjdZLxIcRA Rz3gTaLnnPS1MhVB4zM+pARP0hWk55YDrPfd2pNko8T8WCvKGl0f8Kl/omRFxJkDYokif9SDhMrT 4f1ryHtoNHNajtwIQXRVKvT1b6NAlw3/1eZBrqLPyQ7qKkTTD+mT6KUBHq57HAkq8Tt4jg69qyVz 4GE/ret5bIwEIaBYw8cQYcurzqhcccKv9P28DMIYYkJ3/Snv9EKXlay0hLGBpmBbwJapEA+DMCE1 LyXHP+4wKd4kCt+J95DxmtTrEhxPKWSAbhc+r6/LWYMZKxTWH17ZVyB6SyJMZl4i9UFCYx/zwqHN 9AEp9RfyY6ZxX4vnbcLF0ONUrCm4D8LB3IDUeJPcTIfUYZCLc/r5MZK52K4Pmbjam0Ny3b0TkdRl FR9Ky4YhpDTEgIEI5ybZBYi2H6Ux3isq5gvBXN3zaA93WU2/ZP6ytecATH/nUFKXFga/hWk145Fm D0q/gvieLiXA//UBqbvW5FOEIC/tqlQdM59atLVbUl94n/9Mi8qTNaPgdp+JNbm7iCBqsT5Pp4Ud XP8Pfpp5Ljw6c5y0oRgmQiPfmCcT8s8RjKXA8f6L8A/p9bnspqAIond9Am+7XhvRYuhagipc0XvX qPro7VWD8W7eRif6CrxfGYFBJ36YC7+jVT3dhbqrd8uIIF0WhQ+dvTCC7yoRwY3rgP+IPCsus0Dv hckoeW4B5Zi906iyaA3n+TZIo/Nx1EkvPAfqCnlLHoVDAyuuM0zZxq4PM/8mZNebe6CG+uF/SpZV ubMFQ1Wk0rsvLZXNr5Sozsgm5kAHQoA/670/SJLFt3lXrLhnoNr2agbPMxUJFkRJ0KdwNLbhh8Xn IBjcbqzYHkaUYuV6oSqVS2v44vqODyYtXHOaWCTCFurt0hod0cqkxqbnKLJf3DxBI9YHrIJzn9VP BGmoAIPLAIJVW+p/KgsmC+ESr4xRwAZkIDTn17Jw+JRuLk1B4MKZhGwEIimmjercLjdN1pE4vSud LGG5GhGw4FwEWVNElxZv427TWyzbmpN/3kmqA1J4PFDLF4ermBMXvClZ1rrwrH0TKR0fuXcFyKOx Z/JPCxFDSsok9zdm0AUasxYwUvHpQA0BX+Yq0BLG3NgmOmhnCEGi2xRFaRsP12jpJxCRFf0fG+KH k4VYMbNCetn31Rdx26slXq4NzWl0IjO6I9uiYndG7Ikmi86c3+2wT2wS8rWT38SXGLX7sY4TSXeR 2JbOh9wdt/myM4wi0LzaDL82Pc5ZGou/BZxWRSi98UZnscH4SGZH5wnrBwJFCM3L4tUYwCLanGKn ALMKv6XZannoPmbs3yJs1+NXhRmrUWDeUQPlRTSuq1qQ8WJ9XMIh7b58D3YaOtdkHseQorjl2esN 3eAJPwY0jaZZ4nO4lQBL3q8WLcQtU+UYwnH6jWrE+PxjrgYRp/rxIyFS3yUj2JC1thwMGe72QY8v +OADQHHQqkf8/+FXS5ozJiPol+rxtJJy960mT5IY7yB0ZSk0NAkIyEYSeQASmr+coVZS5RfrDmr/ T48FORRVh6MgBQGWDaj7Mkr/ApLou+3sasfZii5gA5OCm1BBjFqYcsqfGSSo0N1X+U85Ld9/qAkI a3A/lmvLwMSY/SVKy/G69t4JF63C41WNBUR0iP1FN+KRwR+rBIWZD9gqSE/0FmDmqOh8qWXoeM6W LpZzICOQDDFLhFoiQuKKJBciqUflwluQ8I9DGl2Fvxg/WMGIvjX1cV3pxsIHwsFrbNRU8MwOUk3o KM9f9OqqQzRFDbwzkhWwWssheEVBCrtovhlwEekwjSMmeDEtLkiIhtRvt4pvlcsyaTPJDRNKzL/M soxvgNEqdwSEicK4YXzUBqkRykFhISfsDnhwMXpuOvDsIsXk2WEUDhL4NYsINBEDLcH0INfgJuuQ rifozBDoWKK3Rs7I5RTYQXF5aHFpGngOuCjF6kEJ6WCc7B3Vt5I14giFLKT2DV+azN5tGAVr7ogh fY0rAF5OoAnQLZrfEy18AwBmNeDEZ53n8oPChiT1ZWwecL9dj411syybXFAQt/pcy2j+GsZD06GP 8OYZW2wcs0Zk3+ykHfwEs/BPOz2robMgEhb4Ap9FETbfDCrH38S1kUI7GUm+RIOEQSSQcjLbylC8 0eF9CvOxrtb8DV8O/AYG4SjLV30Dc8qblyk8AyfLaJXj8OaBg2wjIHG5B0uIrZUUCWiHCp6Z+YtU LbVPFDQUxEUnQYD6+DoucwzPuN04IIcOZ6U2zQ2mq/OUGzS5mf3CMxszdwlOrONjnN82ZP+QmbTd mE3CRd2ndToDOo5o6XfX8ev+8GuO2EigBKWk3MakLQOFJLRPgcBHU8Df/nqdHLC9nOsvTePonod7 vl+lH+K7vEUGUQrs7zpZIXWjEUZ+9y2VAm/DKyS1kRcvO9MUhEEgLv4RON2aoe2v/EFBPPI1Qv5A Ai3S56fZL1Z4ATQFp4V8yTerO1n9CZ9qKAxCrSjfmjm8CqFtu8Ti68slWtrj3HmHG0gEhqzbrNKM wHYl3c2Lyd8KES9EIC9FEeZLcf4yv/hdUhnBFiCTBIftY3qvom5QC/PpnyWsKPHZ0eXrS5HNJguk 6BrACQkXkmvaQyiyGAKI7j05tlBpGtxmjlfJUdQm8qHZs/ynFTItN9tAH8TDXBNUPgzMTM7uBT1s AcqQxTuCUDMHdt7P8gsjrpass1WLdU79fwhlgtJTk0Akeep9DCU2EawXuix60anS7/b7Y5L0Eyex MsFuf0VQ1eQjrFVTFvaPbvJVDRIh6HL7wekWe8ShPA5or/cYlxR9ssTXgRdXYYF7Rj+K3Zma2vXc njic6LJ/4BRzrAiVUCCxsDOuOaV+uvtKOHc1cZDlh9x807gR6MQQq8sP93tPDYtgmOMiJZlHZEo6 0jhu9lJbNRRMaDkmbgntAgCO68QNChnFHB8XzH7VW7N6i4kr4vAFquK+1R1dPbRSVyTGuyxDnOdS bM0NK07S9pBKaqqTPSQn+qsy/YfMjVCEJ13TlkrCB+OGDuU+SaHV2/feG3liKKnvHtHAq9t+MTu5 VeACQeOaTkBdyo7656oV3sDhESf/icHJRH8KXWumGQroGicz0sJgd1n9TJfu7OIEwL/b/4PWOxRo ICp3ukMOyr87zi2qIMK5oY20i9xkJfZ++DlJwZNuzlcZmp659D8tB/LZ37VMhShl9KxnRXo0Pm/7 0y/5C5fXiCiRBCFcm+al+5OBEc17R+G/BmZaQ/KnODgiJWfQbaBBgX+49OK9VT8SQ/zgJHoLy9M4 EHUaIskYmorBFyE4pdKOl6DhZ65hwpItF7y5D6JPHJ9d7zzIOGrLGGOzE/VRmcfs6EAvUugUfKfE 3LPme1ExLbPcHZag+Qr4ephl2UXjJZK2k/oUNnzSakZ57nk4uLppGRYlFP5iI/MvdW5tFHW00w6k ot9lu5vPVkwWs4+iDmKylS4QRBOAcb8MoKPSZ+84M02lzTmZqsyDu3OHUIup/2NA1fH8uSKPGUqV 62uzLdJY9qoi23B1KDNWPjWHWFSLcsmompgOXvm/WkE9p1SjGUHilI/+b3CID9aXzxIAaCBfctA6 PFFb5WDY1MfYfOxOMQPMwPMSQR4EvCxgC3TaMvkoO8b2k95OZ2vYCLflEFUPfJLsQm0JW1aZxlhs zHKL7VX0FocDTnn0zu3oRoQ5nRSA7i9JQtTbZHWmcQni9sJ2v+4Uqr/DObbEq949+zx3xFcaEPRQ HtpGuZ7CO9nrVfefC/QhkKtjATSN1pfxFOPmaCf83aFRYpWKU+HT1UMjHbqW4ud7DrQHEPiBbghX DgHn64ToLnAHaLyajtlvE9dEZNKPlQzaF8tOsmNjXWjOkAaUOLamjbsPA14h4Xty/FGlveeK7wZ5 3BCoO39g3XAQli0+L7iXwYAIwB9LEx6495kzzmQ5E+48Q4TCSZ+g/WylD9S+i5ZRHKib+NhMeDh0 TgrGabZ7tpZYY82SHw6Rm08zrqY34Opkyji+kBsX8swkgltaRWRKw+QxcZvRU3K7KNz+HVJORefL 7SPwjwR0QzEFuTsnUoZRREAKx5MXl8SnfuME9ypNwIcye55idvdLRWn1HsD0MF9Xh6d5/CEnCXeY /uW6gsrN1iqKVpX+rTL2T0JQcKj+TyZ8jD8olITn/vU8GpXd/gltcjEGirMXUyAhuU1l0TtN02nm 6REK1SUbCPX7yqJqLWoQj8OGjmrWSzGNjN74JCeXv4AfXU8VQyGXG4YW+xainEflP/0qY/3bNw1+ 1v/VtSNSLAETZwtnetnYBGosz3Nh6W7u9qiYBvmNKixmmdRNdWATPlXnd8Ml1dEbUSTMv0A9eCU7 mDLoXn/K6ttF/M1RkK0VGIu/9+afj3Z6gQ3xm1F989AVj+cIQZIa7aBQI84oc81b/BqB9hyKTvco 1bwtEZ2KA3H3EY7xH4l2dh953ETkCGZb8Z2cJSuBEaVuD+vQW1fhRFQLj7L7taQA2pjFjeB0VH8g dutWwIlujE2k6wnTESV18iUh00+radmn/8iQ2F4I5N0QJ8jcCo/UwIUsjLkWCCTKIfBFD5CucTpg Pm1f4JmWCSeR1hWVL/X1U02D5zNBiE8ySshY0SxLYPzf34chmDl1d+fTsCOEgPwbvEulMNZb4Rci QPrAzC6NxWM9A21S3edgBniS3qSir/tP0hnPrcqEQOpqvie1HDB9C2Gv7XCu0eTF8Ff3rsaDKuKt JV4Xwo7vLucr5qFh701uVpdxhUFNeRATaxrljAAIV9wuqQ5lIx9fdaLirHNGA869wg5lcTd/rT0W DLNkk+zpcCQFUnz7CinCv+OTzbY5QCTSl2EwAOoqMtuy5VrTsmwpxNrDmvy3bxkQwSRVs9o7DAEr coRLxqkmgYo5Haropd9kWr/1tj4eWUsz0JAZlq2ft1hTyNFtg8kxQ+6hyOYLZL/G5tyRdyHZYssf OKq+5Du/4CgXvRGCfkeBYeC+jhRWioM0SGkAJpFVqpHZb8mGxh9hrama8rwpNfRwVPPJ1zzK6r4r 41JJl4mtSMK94WezK36ZFTgxY/d3gBpf/k2scR+fKVyTnmdf8oAHJxwaGtJ9z700QZQaNU15VkzM pyypqkUte8RfmKGSlsm+cXvOAr4lFKFKzRuNCUX9AKhZxyrMAUcunfQX3KUIFG5lcaZ6z/e8BA2U 5s5TBhebAP7gN7IHAOwJBr60UaU2k+FMWoQMyXN5qLaYMD7EugRPIuPp6ZNNHEwUOc306XL6aQQy ltLctDobQmCeMnDlol7c+h2hSMPRfdjrpSH1zw/PeRW1/LQBbwxDHfS7/2RXAfca3WE6y4xokn6O h/AFYaxHYawL8Z1gU90Ne0Jy4v4pk9eoCOYgrkFX/etmEKJQxoFcJtpXSTbaL6K7NN8OnXJwc2CZ UWISiW2eaGpXoNNvEiE1/fgjtESgJHbJoYw5W3sobOp85pMw3aOJg69/wpP0VMSDGcoMdztFzRuX UVAXMDl3ie8zDeSkG/iIgY2t7OGl6OC3DPt+CIDnWdK9jZG6C3dcUiQ50k+myN1Zf7KcVoP3vrGi vzcFuu26xMxQV3IrRnOVNHMflS2TQZhzpmvODAiDPiZyj5Rmbqn7aWGDh43LguwQK7IPKjrBMjY6 oLzs0KSfYOgwMnBDRtrRIdevHJbMMqWRt6R8AoTJK5gxdMZEG6nOnoPvdZD2YW6wjHGZ3IAhujsB RgNp5Pcyg0Wugv7EQz+WK/v3jY6+TC7QTO6N3HKqmkBUMZgIlVJI2qglQgm3yCqmifMzmHf8MU0g Miwv8bC1vh4vNtqV8crOWmjfN7jwGHwlgELqJXil7lhjdMh5CNa4mD/tDNBDuIynIGyE8iT+EPYl Crsw9rpEvhB7guxvWE5ZoVBNd5HnOlQftkUGxAwet2u4OqHT+fzFEWx6C/dwdzkWru553w7QVk+8 t8xmO3yQ6DpITH/b0jeaKM3PyaXP/0KHvHIQOdNiuNy9goyN6gL3U2cc/5j+F7PVV/SPv+O6YSk7 8xe1h1W8Foi2s3Nc7vCH0H84oEkZ/85x+H+KAvam1Zx14H205Hybxmq3RKYkyvtfmH0QjgbxrMzC LkLlRBrxefMg3ie8WsNi42si6zopkMMELsJDEUSjRW6TDEsXNl/bS6bDhvUFe0zSeW5w7BtvueK8 R7uDdtqSCrcWuPlhVnpCYW/EG/cut68TmgnTdVaotjZLJv6DQe6uXKX2Fvgr8uQXaj2Sc7ebvRAd FCVZouH1KURd4a/0KJVkNnMf8VqYUV6aT0LHzHwYWL0RCCVOxyZy/+699DxoG+VTm9Ltzq78PtSW aFpvlmZyq4d+a5DXyn3Hzp6RfTGpT2y0DKzWEIhfq69wc4VNNh7PUBz0qRjRnk1GRH8z9G5rU/kh WuMoHa6U2e8GujvqjAtMMWA9CtsZjXKlLmbpr2SEQgFB/DBqyCUA9PpyiCwm5Awp2fO1ZPEACvGI xvedH7jFNQepZRGXOChlRhzRlx2HVLVyp5s7GDBdsBK8RQsOvQdn/NvbAGHy3GWFsT2IvIvtEHmU I/3aHs89+hOiE2Ru8MDWqEtlN9dSzcjavaM4Z+tvytDvZnJpzMYLNrDm3Ekw6iDEs7892C2ZULBB G0ccl+dHE0iwMKbIv7axGJjYnDSSEaezaLU0ZtTRFH39alzK8pHcfp+hCesA+JSyNhR8dkoqNPEy 8y4KWKgTDCrwAUdKrQOA3S0/PZc9ynD3OKF022jlL15Uvsk+AUfN6K3qYt/ljUtghAuDNB3j3OsA McafVo5QY7zb50BjXEZ6+DMitNYzX7xzAaVvv3mlOaGXYgSQSMTd4mPFtkdLjMEMrmA6u2DJMOn6 VPrMdjq4O4IiPputFLEEjbq7zJg6Ko6fkdZdcJqjB1Vn3+srHcnFo9OoMjipJ0jLOSrqhh8tIQZ8 dH5ye2xtUV+jKcnrru0vDVufrXU6GG7VhCdg6reWsOyv6XMP8ga/UHRNfGj6k5jJK/qm4HTArXOK QrQYrq51pB1kGym2Db8sH28iIrxp9URdUD5FpjEYlxpFpCm75ki8q3HGGHMu8xdoXgoZbycETndd U+KcDT0ac3PSh51e+gQMGB+wvvSHPOQhZH8va8PoT3P0MZ3T6+SR6jGAiS+9iOMpdk3a2pPZhZIS 54WkU6DgWxWGTfuRfpNd4LjJBRnGdlAFy0yG5zY9d3Y8h+w9d/3TjWir9mH3m21ZwELfaeLoaajg TEvZslarivxfvYMoNQZdY2caxC9j/RKwqUVSN6CTg1u0ao+pnIqIarJcWxhX+U5H6dH3rMYlPl5e a3AyqAN5lZxadAfabmKZ1YcYpEwojyzzM3z6ZZlCTxxWnstyjmdIJkxQ0VuYdw/eeVY//ThntbkZ /yUaNhL+H3M0V49vHf9F8qf6U+O/sHsRrFe2KQcFiqXgf7FiY4OlUPZcOPRuo7DkLG1VCBUCd6sH Elqi3B7ronFIjAwLyuoT2DiFVEgDITdNQEMNbfefnI0zTtLXuO2NFZnwC1RDQSJRJbd/tS27d7zh YYBPFaw8OMa3ZXH6GjewiNXHJpuYOgtFBeHPylcGHpYK5aEl3MPvTzauy4qSbqjc+da53w/vhLjd d9TZAINlDt6ZtklY3LF6z949sQlxf1aqq5yTx9nuNSMJBzQB03DK1PHDERRbbZIVjrvWGSxN9Wgx eNMXQ9QeSmCPaayRoHW2MTjXk7G+Mwh6OEJ2VmXMUo5peyzmQDhSK6RcrIo4yxs66RUHOU8jr92r z+rbDIqfYY15HNQo3pl6eVRhQXlbXgB65x3qrrctql2ZeByswFm/2ZB+hbMmPLdpLEIwLwYZr30H vMAz52aDfVW1HfYd4w0tZAZzFffpaVPTezpP28jk0ANxpMwK0CBgJVoVAQBQdjsFXsgi5k7mVYpf o9abQNjg82puHEYgpK44cRZJHlKUgYr8FJaaVTJ4264GP29YOYjK7hBODyKljovt/0Rn1yBe5I5I UL4H+O1PNACEyhp8Fxa/DFnTlykNHVTEFIrv4BjpHVCiQuvBjVqtlc3BDXm//c1hmtjni/a3Xhxm w+SVx+RNwa9Kk1P7y1y/gwhRHFskYsJBtXRiSuYDcS7Ow9laqcdAytPjfYyxXvC/NDrqsJYGNUVQ 823hdkXvQzuIuCFGSZ3nOgk8Tn0fs1xAocO0v2QlAikGLpx1xRc4g+RtcLkhp2LIkP664z0+9IgY IB6lEdDMnjYfdattj1T/ArR59FaEj/nyusuMTY3egk1VKDDPVTWEPwpyi2h1RvFPSv23Bi7fm0dG Y7hBzOUTuzE8+xjNUDW5kuQ2w9/Waqss4o26p6bvo60c0ENfidBOpMBJqBZCYHJmxlHNiseVrJpv C/dFPnUdRGUbmrdPlba/+Ez4gikk2Hn4/dE6o0L0ZeWCgiEACLji6mlnNtmPci9zCl7D6LU8pcof J9A/dQPFKsN/kTIiseEooDgQh7EnWzz6kDoNZa8c/fmiUxIhHSISCoRwCSRmqLE7Q4oRoyZ2CO3R omVwHsqU8dxSIupMGkXbkK5B5aS9VqWZy7iemvFUaZZrKNn1UZEjOL0ITBnNbI3UO7TVTsW7cOpn TPiLDn1ViKF8tXACtkx3uvblRcj3OumEosj4gPLr4FVGDJCMq87ol2Qd0u5P81niwFnl9KOMN6jY AGz33GgcRe5RJOgc5g6IcM+EZMSwSHDLlx4NEJFiCXJtlMOdRzMj3mK8WVktlrEeg6+ZxJ5qcU+h K9PlXH6cjatLb00ltBctPzRHFQifzdi7y0DEU8jizCn8da0= `protect end_protected

mit

af4ae16fb33be0fdace808a6599a3885

0.9521

1.81974

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/builtin_top_v6.vhd

2

52,905

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Tm+pO9cWjnP6SGHGIUORi+Qy3ZPKJPc5Do/wldGLv+79HykTzAUPZjf0NDSnxG/NwyDyNf1sRy4e 53mlcC7Kkg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block nAe+7S9bIXjryeeLTMUBL+JHgnMEq0jcRlFgKILMIylhACCBGZsF46L9wUs0Wvv7QjDckMnV5HQT Sy4NgPjocveCUApkXfjDURz7dNJWr1XF7aBVWWJuZIG3ziDDcBpQm7VMFPSpmvz4KLmzeCmOqVfE 9ciHLBKHk7X0AHDS67I= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block JLesE8QBzw0zGuRtqT4qUSTc36KQV/9psE0Rh3RGZoKfFjeZtwU+SPmg7MX7kYJvN6KPv9LiAYuz w6HvlBzLXNBLCpykgbFCQ0MNBUyv9uoWSrUAXq6u2FpEUSjMdR9658e2LpdGAgv5vcby/zuTZmS2 OayDLc0pNuPfa9CwE/dgGThMEkeBWllWFZC4XNk7Ei94cVR3PBIZTgJEst+k8dvafZAePcYSflZR pJgku8OFiKG5ZyBPQQ5KWNteu/40MZKu58bjSLEsZbJaFe858QNBv+e/jhh7+4jL8y5rOqdFvsFc wILgn/xQ7LZjnt71MT+0FVdl77P8BD0Bg4p3EA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P8LDT9HXJ0k/lbQ3U6q0+/gfU7N7EG0VXNxAcHSRxItrj2iyedJlFdeK6kiE8O0p0OPEiDcPwJHc LFXsevGlBGQZN9RT8LepodPQWFyAA2zMqyQ7Jp4DgNUvDHPIdx++myw9cSGa+daXyarBv+dJg0L1 FGYoDF9VRBHxOrJnTEk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cWHAJ41oL59SLCBUSOY4SAYDh7gWLG+fAi4FllcNcSaPYRM4Y0W930vlcWo+455Vjokd3MJVqRol nk5JPY0divTkOcp0AJzvkI0ytTeHFfykU0m9CqEhPHszQE6Py3SnieX2mrtujfLK+j/hXb7a1RJs YumlE/Y0fe4jFKG063TPSwqnPbvMXimQCETOWTij0tGSzfghJNbYdk1vERfwdjjYTzZhvq8WTuur STYGKOoIxxoBhuTqITTBga2RT5vxryR5d4qLN3ocoF8Ay/s+BMXqMVEqCJe9PPJd9gVlKP6M96I/ C1AiSDaDoFdrhcG2aOR3Vvlx20/P9McsOkvx0w== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424) `protect data_block KXAbWy6Y3kLMWJ9C5pGqRplWc+sj6rl25TzXO1OcO6pA/wq4AVJcewFSFA4o2sL96+CGCcEdgMrN QCjXi7dmSeA4wfkG0XTtbvy+2S+Z2JEscOiHPdEmfzfAyphmFPhkiNYB1GftKcUOjI8wkPgvaeMp xKJVv3xOzvrgz3roNDnFhV08fZLV1PoqVGBhmfYA5HzXBfUkFmkITAzvnzB8gG+Id8L+MwOzaGra j/dqD6nBcfxBKxJIyLm26mhBvbo34VpvvTaSDbh0zei/OG2emm+joHpzkQ9eXlcbwRSFymRCjuH4 3S/fA/eur1fwKLVk9RuvpxHyBO4OpL3gsTvkAQS5MIiwBluWBojNRguRUlr6g4Ba8kLd90hUnupF oRKbpoGb5jSyr9sk5QYRCGoNY9rMI8wKKG+I7YsC7vktemp9X0/DlCm5Ck+S9N1/TWUBdrvepiO3 urcE0rm7JzZmoaM3U6iFWYpiVJ1vqhAYSTL2r0nZR5g45kYDTf3bC0zgTG8HucGh1wBKjke8AS66 BRIvrp/SfSnqRrT5c+gD3tat9AZD6WTbnznqCHFhhcSa6GNlslhWZNQQnETUT4UjrgemEHcZ+f8Q LZa8/fchMUirzlTfxs23O8dWADfXaVQasD49oqYtYbvU6ybhYQw5DsoVHVCrXZbnTvealiQ0kVj6 eFv3bYdlNU5Y4RebEDFi5qFreuOxrxxfraNKx1BNy4aqlualRq4RIxf0Eb+HpBk/pGzpvqPJUP3q 39limBXM56jUd//51HnnvpzafjJue/nwY1Tm5tRXpKuDaNzzFb0U0ZBiUiZlucbcEeJDiYX/Ekrm DlAkkzEIjaG5tPRtk9thaC+7noiX6D4Q+b//m0EI69MjTfDdPbHJr4wvndT9yCOSLezlR0nC0r/O iIhW9DJOZCja6Hbp+eLTzZ7DAkMj//3zmyV2BOAVoEpGQdYpRloEj/jwzrVjYLM/i/jTU8eO+ZNr HBt/sPKZ071kBc05TaxiHdmRFhgLyTWnBlnAM6VqtuFkrij3+iWDf2eN9w0p+NC9ESSc3BEpqTRh /g5b/tps4pFF5P4bnDjWX4FC+X73VToIIB3gkSqQqY6xZdAm9T5R9Fy7JrIBKu5AhPbcfueKmEJj ifVHxPfZddb3U242hpplBLMZ/Hz/4l/pFZRFZ45+JEjC5eVE896mAUdNLJ1Blu/eIfyx4+75SCss nCP2JlbAhTmJKlGy2Rxut+rdKh8V/rzTFDfKcZnpFVr6CxGSNaX+mp9BTxeq3bQ27C6Oty0EMdTt HrEjmJLJxjxAEn4Uaxjaso49BWiIb+HW5iHZsl6Y5q/o5h1ccig8vL1DxoQIojF3xT8vUqWy0GzM 2ZMAbf9+O2Id1k3KSYYC/EqJTJcO0XMxvCbtb+Hm7T89CX9wok9SfvvgtIbDiG+Tvrih4BR76HH9 kAKrBU6HqLBkVUH17JS83ckxsZb8ASbFLpyxk2UHpb0xK+DJtsnV/LMvtScr0uHjrLOnSxADWZxa PsMf5bxtwk+gm/9AmPEqZRsuUggzceMxE2MZdOs+jOjjtX82JXtHupqHCO9hEh/xyo8t9LrRyh4j MyWmAPP/OUEwmc1vLTBdE8c1lO1ViXqSn6EiSFpHw11yrku13kkn7ikE5LwxndYXjfKCxlj5HV3X IQCWSz/3t407xeJknkSYXe5lv61IN7lnUZX0IpaD7geRTg3HFMVf8hoZU5gmDQDkgTqpqU2x0aZJ 1S4FAfrJ0/qpYmOAjP8QLD8Kwqso+y1dwhlsappl6yenXJiW9hesJ+H0VzukCizOJSW80hCHBtMs EyugfAdm/vcT6Eh1ac787dG2h5PSqDWaFbKJ63VAdSFgVUYVHZfXQ7p5BQp0HG1bsqVKu/yGp/mm B/ndRIB1YanTG0q5F+2rZ/0LRe6BoZCBAn32dW4LgtKW/PY4/tnU6dQoDzRyB2mLxaSnhy4I1e5v ugPGJUlS6DY1utt102lHjcVWb8t5q3eeK5IDIgzGTZU/a1qgLvJZ+XoWms+EmyZgNaFWmzAlx153 OgjUatydCxNXRFm6mm7ifKL/JujhTXEQPIBwidPVwYVuP6GKWCS7kmmE9RGWYX5vTrQQbgeMwqdW nDC4dI2ZTMIStw7GlcXSyQrJ+aH22Q8tyL6mNmSPqm6LeBpWbfjgQgCiuCDbunMk+mchDuaJmVI2 DEZjKfOZG7p0k0fW+mf5qtHd+F3xxjQz/iXYygGXUO929JXUDYc/fbKNu+Om03RlGIc2e1SQYRvr TB50Q9i6TxRqA9vtJjTkEhXKpHQKmcMgabgBzh3tV/h52oVWLhqDRxvWzKI68x8O10E1cfF43+HP qztiWNWjQKhYc2yVTD4J9n+p/f0epftCHyHqAZ3Ly129mGdvwSDnP7Mjbc/tCdWCU5onpfRCgYZg V1O5w4LT/b47tIx5x0QwOaItI+M1E6d/F6zn7fADmpmTScDbI9Qs49r9DjvB28EbLDixZ8HuK2EB QldBWQSmwX1HkkPkaHda4vgZnTobLJJq2D4+2P239dOBsMD3r2uxBwhblsHmgFr5aLNoSfclGkyS k+R3yP+S7BW5dqfFEhofKb3miujwKa/9Y0/nS8qG2J0CnMlpg61xsoA5VUHCFVh+ZUo3084h6WED 0vhowrDJN1CCXzxIxpcXq4TCVs7VUh5Gbz+4CmI08yFBs8TIb67a45AqFUS5G8FVOxOmlrh8vmV1 cSB1Dz2T+vepoJVfxDU5gvrQ5sA3baVkVbqD8a9TEvV2efGIzM9RZ8oi3ij1PMpNiKY2At8x47rq fPg/AfPb1dCGU3zmcAxw7bz6eWIz/yJ/TMUmTBlRsdKfpEZPrRNe7fDquIWqHoZIH+3rjeZ5vlQu 3TUL9eAXuRuKl0mFq4I+3kmEX7aXZpvYvjQbpaVYcxe9u7QwLndgyThMIozAL8o9Q19b4xJtD9Ke 9V2yb0Qen0XZjap1ExksYASafRPu5Wowx7DdSltjkf+VCoHv01KflhtcmCxswSVGFhyGPXfBEj87 Qo5qQ6kK8Be7C5j/oSPpEFMXiX90eyZ6qJOZ+Q/kQabXLmDHTuzK00tBlqExoTFIkad7Tq15Ooat 2uQC0Uh03tYW0gJPLkJAFAm7HomJrueEPTo+VrK+WI4Xeg6G0k0Mr0lam8Qj4+nhit85JUy0hfkl /oo76PRwgvf0o2ZvIwnvsCk6Uyx0tAfXibEN/CTZm/DoTpR+B34owwlGnahCh741RhKxeom0WxpF HA4McY8CpSxM56FmOgf6e+6Yi9MARmxEcLUwvFzNj5P7w4ttWXdlf4riBfma8kHQI25BIfRbUwGq SnCytLxY8qbotZzNByVICzoTD/XJE35DdIbUtmhlIadnpl+WuyZ5q35Lupa/KV6pdSekngAyQDV2 2vIF9yzoPYuPneiNXeOmjZo/bn/QPMXe9dEH+0W3oQCrElIiXKs42EteqrKj+oUwN0zbFIkKLWFz 9XzulCFn+XzNyD6c5BsVp7BKl37AzZF5FjqaDfzPMXAjkvqr4Or+XCSy807dojeqVpavHTr+YwsN Qouj69mD2W7iJWGNvDDjLs7xEDT4uMaDoPqC+PhLUtrMGjn6CpQceN/wpQNc8CJPzmAVwM+RxJAV UCVB3OJsi+Sxd8lkeuK8wRYGHAuCxj94Kv8t0EaXXp5x0B01XZSnBjWlxIJNiEqIUvfEC5R3XV1F /xMa1IG5NdilAZhaiEQzwjOmIFR1IBFBW8UKRav5a/z63UkIBk8nN9uEwhedepNE9PtKBofCIWTp mGLYt88Aj16NY/nks4EID/UOvCJ1rZ968IlGnSb5odcVx1/TkIaiAiCrJb/P6PtWgdgUCYIpFM7k kRnd7Zn6EeX/blfgk/vD2HWYLDSjTpHYh8Cef9+MVBk4vqLSAZc6Ha7SGuAM/lU4fVykeN+Gy4SQ XgUE9FVSluupFcnNKOgzXDhae0Fbcb5rfeHSdcYJzKi2EpPAZswQwJTbzw8upsFIJzHnlnr4FIPh K+FIAxu3eWUXVoKkfwYAqEaDpu4QsJHAOwrgnUZv0DD6mrZqRQ+jfAYSGTyv4981JHndwVX+g1iC 4I02jJMt3rIJXYGAp3G4dUeoVUSzLRo9yDssfOhF2RVnSFXV0YR2sBMEh69vzOSLpLSSeABOdTjQ 7lnz3IRLgbIGcJSBgoQvkXvq4aXaGhhX0KIzchYpfy9AVV9jz1ro7w3CSR7i9iHhV4ANfvaEYZ22 wznwafHI20b50VZnvGRAC5TrLzHYHJtbCUb3r+UpxYdTuOxmEW93mSRsgq0bmAgrRr0Gio1Gf/t7 /H2DxieVrABznKP7HdrcYlJK0pUUGTqr1JY1VDSId9w+QHM1ef2MNv8Ts2ZZLdltxmMrnI/LLPP5 q8EmMECYy084EGl6jMwwFbaBL1dzDEg+5xbMJT3BJ7XQIA6FXVIih7WYFViEpAABo/2zgHN1wVp2 2yX7UaXIBuut/okrvtc7CAY6RZ9TlGdrwX8G/Zi/mFg1vnrY1Rym3BDIiBohtUYogJsKXhkp/fVf 5tCYP7PICqHHAIof7kJ5J+6Bc1UeY88a98QGbPaKkrOWEREHpNJ1g1mGRgeHV1dQCym1TnZKPSjE R9DaOaiWQXKyIiulTW8vhzRPICichr8uizGqLDJj7hHtoHPFnjJKzdyfR0VM3ieVY1fvgniZrvAy pWTPhTlEhfjfdydoudAwYbgqULSfuwFemLEReL7jd6/v6hSFdNKIHshx/GRF19CKKoI4sEKcoHOA WAHhWx0L4RhoMqUtqOarK6JCMVGrTvr86KE4EbIo4xM6Ssd6SyCOkpy5sb9Na92OXdU7k4zapyQw CpWQRsnHeeKpqI/lS/IhgqKUJHeL3aBqa1f6AD6O6iSeX77/34sqUAoXQsZq4Q5igroeLHJH/4cc bfnHOQO/wZOGmcqxPWN37DlpYQSzmecha7R5xRUUve55EQR0OVJSAi8EOjAeaEVbBQL7/lvNtdPm 0G0VDyXULP00DOznTyXa8ygR3QY6KEnIrBiNbkE3Aie4pdUqjnPoOzAuDEkoIdANiI4UZM1UgHDl TjHZk7ZUX6SjG8mls4GROUaI339tOkdPgkVKFqsvTL7UHMpbDBuGFtEX/ZSf6OPqgmS2/1bNlDpE DBXNzFlt/lE7eBqBMW1Qafm9iUfubFnufgwqEe+jYbpfzIEU0hCnoVZcoYcoYQOBk0wvVsl79pEh EwW97X8YF621XF0lhgMvlotFwvSyqcCHgQL73xJRHTakJZqVmI5R2eUq8Xc48YcW6Y60BJj6GZWG 7JcW15CWFkQXJr9e533VrndIo+LwA7sjd0+b1aKES5YjYDeTW6Hf4VJXx+XOSBi82S7y+bHJXKes gdWySYME1cnMX/W9AdBnmrMNLUs7FH0kTpAFoBRcOczz/HeL4ajVPAiAgNPmaKWpGOBRV42QeQL1 Xz8ge2b73FYCwvY1G0+rCSStJ0UajKTBO1UnjPXpuuG3ZB0RggtLg3yoQ05zx6U5EFLAAx9EEwXv pIEET8iVoX2uuc/P0FGacsLNU+uRHGDXagtDZO9ICgIm4wk3v16Xc6k9p7HZb2rGVUtAYogbTH63 LHhFhPhS+uLBDSPprhTfrAS+k29nYZgpG1IWFBFZH4hNguvXpg21dqW1BcvDbF1SDOQrR7qL+y1d uiyi3ytR+U8ckkYh+oIZn6x32zxLqw/AWgKmr1Wd+OFFDTz8zgIDoVSLJzwPS4zuQLaC0o7MXvjA kBO0o+S1uIIhGPdhBSGFWtUlayyTpw6DrFJYEJk0xZWNKm9iZY56xIZW7v0mkxksn11PRTzZCq2W 7+Th6wdmQcvEnIq+C0Bk6wBSJgeq9KHEGBG7RQhUH23yZRaT7FmYC4xAaAsRWvfEsXfvdwcMJc0P UK+PDuXysZWY+WM+6aBAT+4+fEr6r/n6ZdgInfmCWyI/OFkoiyl8q4PzMHUlP6BvdL8ge4/ix21S QQL7XhYdUpQ/GYdeYi34RF6C+GYJlUkhp0In6sZlVFptBPlztoLKt/Iyux+4RZ67BImA1hjlSXUs 6EbfkytLW9uyaZxlUNrC87CNPYrWmXU5S+mv6rzAKLyY5ONuDYbi4WLUGqTiiQR7wmWbOepxTK2G eCHFw97JpbsmJ8M5IuS/BzHx4AL5UjCmqc1UrQ7aEEy2rzvK8EXRwDQdancmOdD2yuSK/LYGkfRk jZD8FgSF1YPx5J+Yg6Fsw7ym0Dv73pdMtxTS1Lp8z9q0zFN35GGI69YJvc7D1/cYh5KI6F95v5cV H9DoHTU+MbG0K/t+zkSlpd7hBgM1Vl2v4HjHHhqtW6/uMi8BW2dI1ZjPUVnviy+CxP5DABTKl9sh r9HThUhTD++YSNzSnJWm6iEipfX7BHLfLvDr9xP/mkZlV3FN4pUsSRgGyekU88PccI1LnPmLwT6N YDmqCcniUD8kP5SYsiOJ97kJC80eNLLo4iMZHkIBwdti2dKi8EC9EoBW3/jN6CH/LCyc3SZNFvbN eQ7HRbxOzKy0f/V9us/2h4IffxGzJq5SCUZy55ItDIK7HnlxomquApVVKmFMoFFsklKSGv1rdf7s KnjgNMleD3oeunA6F757S+5Pav1nzrHkba+AHxheLu4hRDV+gyFyYGWqtzFb/95SL8UxCPZZRfmp aNbXErNEIKG53zapo8naSkK+sn+urzVAGGXQezyEXxRtT+fqHohnnPGbeDfk0s5DFjgnibgFUmCi 82TcQ+kfmSNUnRnpijeZCeCRXXT9fFsZFkvfFnL9BaTY5B1Ji0sLDyx5SotV+sbQWu8jelkWexVe QLL6zmXOC/68yzTuD6UW8ygeBhkdpq8cauL2jmc1VlDFMzauynQ7TBUBHT4ULKhkkMa/W8G9Hj1Y ADVIIfFFuVwBIq/EnxMt0DOfOLWPI3+gWsrsS64zyiP5I1bDym1I0k1LNLlENJl9sp0er8Kljfun zAGrQ9b6oLreX3o/Rpe/tkH8tUCzEaxsFf2LHjjXsJ18aciPBIkB3HgEEO45r8PN/vDy67BaOCgb IbGabCI6lLkxaPxnehRjCfs6Z6wb9QQ9+Gnf5JhlYV16szrRJwhV/La5Hy0285ajEbn7+bNVT+Ua Sgs1JFBhAPh57P9dKKLxb/sLIsChPLJmLQSd6P3pNPqw+VsM201XBySPRSOgxOStlXYOgU3IgONq sCLuxoS+Ew5J0OSr6I8JBey818acv2UoYXGRbG3Z8hrFSEedDexD/nsAdITm6gAzByVjkQ1IsqyF jAb1JJp+Hp5Bwfo1U+sTseNOKRMFUIV9l0X1WZ9wkd5ZY3vYSIAZCrk2L8AI+UmgF0qH+o7HKT3g CszvqzKJ9JjcY1BrUqE1h+PFzp/rFyv7K+rXSdLb4Iv8ipvL81MtH7c2Kr/njUqVQsihevng+COx 4/pCah8MMMWFPPMjqIDQf10k64pUMJ208gjNN7O+j/jaxHfS+QXYy7sZFlNEW9WRv98WbsqOSdb1 lkuyRDSp+jt0XJPukZ9V5L9nt3o9RglyYf9stBB0xSJpmby3U2ScMj5t3hBkPqHXK/HtK4823ZCb OBKG59ABRKKxbneASEMWowRPSXUcdpDrhAXZ+rJ1K5zT+rBvPurRCD+cl+EYcjmUC73n6j6Z99rM Ao7l1bZyq5SLoppDPB0HGmI2g8yMZO7qyAlqjTN0E/rg7Zk/n2yrpTrGQfSh6q47FXyr274vgGxA Se9EXWAUGxAiLDh2XCmq+l1aVihxej2hJLZrey8FKZS7khvZZ55ci7P/c3CRqHXrquwainrVpkoi u8TJ30FQWNBJxabr55Q4qpWmwfSk6DG21GVlpfupjlBIWe1RKGT5WdKICt1P6MqwSH+6/RIHk75T c3RxE8zXeM6XuHx1y2Gp2/wWG1wSi4UlcZTqlgXP1KoU2WMHsyE4rA7geSynsZb3TZrVyvLjWC9t CS0AL48lKC9jgWkkUsc8dGNfrguso6Pyh4NzbTjd2cPMgAeRNryPMNJwdNvL691B8QwZSEU28vCq jFNolxvd+3uNFUWPeC0B5GtvAzVE7M2UFKlYM0gGgZ6oVYRDML3MDuHPLJDwmjsBWWDgKaqDfidq KDaF6+P7dgD3BMJP93hXTTxleDg3YpWMv+cIAPClk5gIhWAQPM3kBMClkDrylppd4GCPTbpGicBJ UYnV+pv4PeW0ZhbYSQWCDzedRKd+ZXVIrbNBfctFW3bSP3sgxFexotwR+2ZE+bUV3u0jsWjiHPbC PyV4M9BGEKtc1ckfOtpR0S1TsdKs798spsXEzNRxLlrGKztjQz6I+eOuQBliPyJOfrLidsPdqI+K hx0fvOF+gTFrlLmWIi5Q0SVMTRMyVgtBIdm8toz3dxRoMMLH2bLT+JLbwJcDivXTHM5ZNX8i8Pd9 hbzDBqiJ0d/Y//S1BufOZO8kAm2A9SUZ1H/qxdVxzd7alz3FO3ZN1mAB7pTE7BOItMC09iFQPwkH jWWvOsngSvIceLfPRT66+6UB2PtEmK0jhHjoKmW3wmxCSp0Y0aJ6FGQpBPUjesRQzCUI/5ESFKDj 5DWCeOLqEfmCHJvVyjUzNQ1f2S+pcb0Tih7Q8uIaUQoZJfEJdbeb94cGb0MJ19/Ln7AxBJRve3Hw sWyFEjvGU0A6jzACBiYorgzOWuFQuvuZSwV+jdj/OKOGWm87lp7l7CLyb2TVuLpKkXQiE+xNwI5b 9X9VEXS0MkOzTubZ55o6TSeSraBpiUTyK7nD9MHZqHDbmYOUN6ivDFKURTmMXBNNnnGuzzxff5JY ddWMx3ABTInW68VMnXz9XSn+FrrlpM19kxip3BKa2Pk7nG2xJqcngJdIJYiCJbcj6yWJKJWRSDp2 sv971+lDk/P6FivTZ8fyaDELtv3lPji1yyVclrs1hRzpbCG+iuK/D2piWFkCvyCEbkc7JfNBYvh+ P2FYtrQBpV6fXZ6pANJA7cNRuDs5Gf/3y3DsL0Ct4dhD3YieBFcjfHvdO5G8pxgUgbqNHEIpinbw S5tM7Rw+QK37SkmWE2hfUUTCUhGd4pfIZ37vySFbNqYy276/1BZil3w/W6EbAgZvldSSigioE7Ux 7YU0N6861P3fUDk3UFI07G8RNP35WwVTDLFHqs6wIN4nIGgJaOnoxpuRT2/aIOBvTpxBsuHX6Ev0 JwGN1XfQ9pppEK8EgmesEL1PkH9nr8GdzsesJ7yYMpKk1qqCZ0kX4l2klzIJ7w/gTw/GQpuFrud4 n0evw/TqOpc898G89NjUdgVOTrCDEzoROT4UIbaSuS6ilbc9/8K/BuomPRrpKjw5ZxZ+OMF5VCHO 9DFyhOyZ6Bkk9yL7htmwnfgxJeHl9VA3UmyqyWITCbgFmSxSfnBoNvH0TC38QQr9GDJP4ChaD/Gi YYbYKL+KxXLixnd4S39yoQheguca9dY3pctYbR046mx9XWuQsD/EeInlir9/m5ANnsLF98ebeZu+ sOWx+M3d1svE8WNYfGHgpb9sLdJpCcaIOLPZWNeFNZpzvIbuPr9mi+mSI8zud1OSqJI0qnDWfwaP zkx9BNE855qJdo5d5xJ81dM9kTFAhVFZ33rKx/D8ltHV+IXP6KIrm+XwqoUcDoyKtGxlqXtUVdbb 0LrCkojiQKtdgdBqlFB7wc9AP4C4ANOXnwSoeUmpwNVrsGiNEIRooUhRb/wrb+w5TYPSCjNa9PrL aMmsmaWZUS/5E+Rfk6eMsErG6chAmqv53g4UvsoJXRVxcXGXgLN+nfU9m2jm2XE7G6ijO4eUDIhN ho6aH+eZmNyJzPNQBKn+UBT9rq44sAuZvP4aT27Y9DWMF/eygdOv37pEE81byeJnH2/ijhCLXgAY u/8yiOWEbJFHsZC8dRwOReKNOdqjLjdx2Keyx//ilbRYZTQ+IMeVhA7OOROtzu2aXvfn35BBJi9/ fwZrzvALtivRvDEFvWbCLkXb4pr6FQvZkkV13dA51JDfALFix6GgIs6NLPcFbO3DExZZfI3AnN56 7GxEGnmLCMqr0q7R4PWvfoikuEne2EYrqnwWtPAN6+KUjuq1e6Be8ricHIe+aNDQuz6+OZVkfNen n1FI85xAO+kzw0WUeHUbrSGOIbp//pEMguAwDltfTW1v681kuvdP4u0eFIbponzczK5OjKuVlK+a Mm8df546vINJkK0hbLi/oirk1gH2+gsog75ADHAOtWdrOHK3nE6mPG/coT8FQqUZOqPDP7/EloNd E2SV0E0G6GMBGALcjAwC6MrXfNlX1iwIj/wTD6dhxDJWgX8Q7tLeLbkr8v47LYB3TZVgdyhFlPyq LNZiNK3l9WBt0y06TDU4b3mos5hsvVjLJCJlnM2Hn9AKb9BDOYN5Xp3Ny1HUI/kxWKcie/eoz/4E 5I+bb4sg3k+6/DbeOrVfo4aoOdwU2vnyehRDGLNolIsCIbIrgucy9bvxeIB5G3s/JittzcxCdmQ2 TIYZ/Z7BCFobyEdkeAfDx7XsEC1TkZb1UtSafFhiFFbHDMjO9pI6a2kbd+E321kVCWfo+/dqTCZ2 0pXgeAtBxz5zZNbyUIQDALPxL6wErOeQj+2zVRzv29LVtJZnEgIELRj69q4DkLtaaNvL5y2pcUMT eqjQMszpYmPAKRx53Xk/wHuxiIhdSrBc30UcL4dDQ+JKmn3XkI1nQxO/2fvpaIZ3QzBDVYiUahJR mmwbj+Y6Qgj9jXGJl4e7fm9Joo9je31X2ZpiL5Qavg3YgiAq/NXwJ1dyJMMOR0e/9m9HkE6nph3u PflgSX1Qrolk4Q1Y3VVNuhL0AITITNWbnn14xlJRGUkEQBetzasUdSqiu/Unr1lBvugUXkgLwxyi A1aT1TB7GKXuGnneJIYAi7gnPPtk3PA3twbCpNln//W4f0g5FBcwTFz3yOFKOwjYH/J468ruygxj p+Pzj3c6jse0Jb/IaKO7hcmmv49vynJDyfXGzx6ylmIK0CfwazqsG5SX6DiLONIa3yaTzGVPhQoq zKUFOLrLd2TE+ssH3xw1Mkt6vwvu6y33DWRljOfmDDmvOsInWae0ZY8RjD43InuTgI5jFwGOXr9K OfxypqgWph/4NJYIFP6HI/z/MbdI6KjYQXT28d7Neixhv3MxyRkBrEUJ3jq0GXbF5pNFOv8dAu8K ZW4E9DJpsOhM5afB3z0DubH8r8lCGfIRx6/A4DgvcAZkQV8vQb3XPP1TntacpZ25r1uGczn7o0gF baXHJKYftCO6llOpnY9oS0EIIfYuuOz1KdZYweh/qbYzVBN8i4DTmRnrCUck2WO+iFOQPVEtO88s Ds/LnR28f24iD6kD/AxDIv8tpB2wnGwKKfFuuVF6iSRgEdECmzayd+IC263OsHyEobpoJE9SKDbm OI5g1c79VxFJvqvm9SXjyVy6+WoCADt3ZIHr+jchOxWaIm6AlDKu+k9Hfp9eBVF3Z87pLCLcOPAW IlDeBtauvSebjtSV7mzC/faEv7eqyHyc8DVfT6NMyqmXqLfrSWeFLdFhDD57Xo5D2nN+Ovw/dqyi Cdl5h+Ngprf/X6OMe/al4wxYF/vC8UwyCydZvKo1LnEw31nK+xgfvYq92cQBrmrPGm69lmdD7DGq 441jticSeqcGMKClGH/VaAu/5ENHHaTPQNxKIWjhvwpMCMVgDUc8PAgoEd9Qi1TH/8WA0JG7T44j vx6ZJOIw5M+RZpyFM3rG7zj2Ij9f34feCujTGkmfnlHSvIrDTT77kZDCJDIfB0tOvEVl0rvjDGGE tVaqew/IGXxvXoxGBe4/y0llVsz4Rgdi7qS59u222/TzfR8c2VjUPPZGj0XPD9a7l+HmI6S1+wtW DEwwYUJKUfia5zK19egBLjcWC4XM3kTZKoocjCibmXvAwjtZwRSkBGqLMegqI8pyZRCmNNbNmrYG 3qkh/gaYQFONeenXXrZESQqhvERqkdo7jecSEouE1jINMYaT4vKWqVkvryMpO+515l7pMrMP5euF 0ARcCaBlqhhBt5FQWGYWf0BS5Q/gRpSeOnj7RDjI3DTLZtreiaAtlpJ6YVqqv06maDgPNqN1r7wT 8qOnErNXoUoWf/Hxv1KfVE0d2FNnOzq803bvTJUK6zoFSa5NO/lHk85VSEnLyCF82EGvGY8YXYPT hYWnaK/hsPg5b7ONnEhA6vudKalfHWfJe/Ad+3q78u9Of3PDT6P7d/Wb1NomA72FhearTTHVJZwg 1UWAhz45cr34FG6pkP6BaGm9udn+wAlXP+OgIKx+/T7MY4zy0n8Cfp331MwfhpjYAG7zUF8QKcfj 25bPjW+j9EhdsY2B5gp3XFibOD6a2G6xY3r720sfn+l5BOfP1G0HtOsVtSkpZ676zOJz1Tz51fxl HhHToJBMuKHTKeuwjpjZGecXsU0GC+VpaNsauCEq2BGWn5EjyFy8s9x6rVMxN6Sh/zaiXZFvaXvq Ub6S9lS+KmZ660IYMYJlnHlvWrwIzkKPBV5+qNfaBJwy0NYTZIgMKeYGGJAVbOJCMA6LCYEqXS7h Hr//qWKVAxH41bWs0g1zwyHX/W9zsyUngUWgIypeAcwPCBSJ0Av1y7yswo18z21L3kL2oQXUhSJ2 clRo3bIz3VSvd0wHJ1j2lD5AIJ+CVWhHnz4RnGidt/LIZgi1P53l87Rri72G5ZNqr4x8hUJ+/P5+ V9SXbtrbtaXFiX1QAwiclRBc3J8H5Wp7kIUz39LnFu23XpjXPgqREbunQ73S9nEhQUquJ1IvnldV QowStR6/rlEAMLHIUENSzLotHpgO2SaJY1enKVz9wBqgMJ6IbWm0ciiTH9Hy/Mhta8lBCfqEmzal acLOkRnqkx/JBxFkXonmuEQxf+DI0O/dm8OfJIzAcguqnbyJdufTEJyuJCK2Mm/R/h/lOiJ/5XRR DxzWMaC4iyLkCH0UBpsGxzawZzzDPJOsSR+YHxKDPizMVg32XPdXKSYt+pdw8v5SXEFmSNjA2TGX F6DNTmYJNq32785z/umQTCzqohmJp6wgnSo+F8tUI4co/2P1YoqeAujVZuSpukNBaaQ5WOp/oY2U EYDHzOYpWkGMssAW7O8NeyLqBicO+rbbZVEQr6OZpiEcbtRPizaALTWn1Ado93x1WrUPB3L0rzwD f9hSGHx0t1gUFPVG9XPAqKta7O0rmR/KCwIZhtr276Nh66L+zw7AQ5+uGN7XcAYQZpEMI/csT34Q Vs0stlxn/kMOzr8f9nnxIKGI2xvncIzkVGrsC0fftNvnMUqr+iMhxbMPenV9vxSesu8C29B1ywT6 mGwMqX/OtFxbdqcCoWtqM9fmL0DEXd38xbpqjX2Lu/Jw436cEoIgymNqtnbqM85+0GQ0YYYTa6qx n4Fff3/voZ4t5Zlq4tcssaNWrzldr/s9gdpN2oU1gK9Lvshu9I2fh1QRN0IG/mefE/nQ3mXWW3NX MBgH3jHpveR0eTsMFqgR2XMJr0vYuo+m+f6b0wq9JEGb22d69rBJ2WrWe8sjNAm2Sg3asOhPJBh6 79kX1BTH1ghZYYKO+cuajIGhfw8tmuSyH+ZbYEdoqjAcx/5CNq1dlX6phJHnhf9EnIClX9DUXcLE 51u4wNgpSzhNQfHLjPJb3fg8Kw1FXJ7RLYK4vBP43VbjHmlPpwqQxOft6OqFEAAzP3UzMPIkKDBd x6HZ24DJLNgfz1Y0b8uJU/vKEhFOGEQWFvS+2c3BxOYK9r9/7La3GlEHQfnLYIbNcy4XwxPn3ED5 u3ZEZnvUvTmFfV1CCOCXlYQuNm76Nws2032B0sdBnXkrCv+9vLfR/RALarQ0xjGRs1MtTgY7j6o5 kAB4WldUJLHauJ6hDHU4EVrmvHyoju8WeZ2GcbxDhPiTsqLMLd6fHcmCwhc8DiivrUT8QQ5op578 fhrotSUTNmG6P1ua1VMQa41/uxhc6+1nBq5M2g+Hy7Koar9ARgjGthvYwx6bchQ5YMJEE6oUBqyr h12H+wa4xuRwc3zAiVDUMSkQDf5FU1DrfzRXi5NKWgrYsuP/fQFeJAQPeBtcBay5N5VZ04Lz0Rhd xmYlxshwPCRHSkIhFAd5QgYrts+f+JMnLMWlvo0DQ+VpV7m9S6XMxU6zaICj+1oEs5bS8kY4o061 /cANT2JMgYWUsIZGDktC43mcyNxU6jPGaBG9qtODiTwY28ZugK0Up9HmVh8gZMJ4za81W3SpXqza pCiodoFMhVNFj81bGYQYwtSFQuRKsLK4D5MBeDWHO+Fb+r4dV/LNL4V4TLTfQmK1pRt+7BeN5yox miMy7FXX3269FODDvpHspzYTsncyMM8p3/O+dqvPII6XjDrHemBPNR4l1hjRD7Zgkfo7F6r3il6c 5MDoiNQUndaGQB4mLAgHKYpuabWg+0okzjj7d2JMQXlRo3smL27xtxh5nX809je7iU8gU8B0zvga RX/6y2j5CtmExE/xHE5FmZrhBlYtOk2DkiBSIS1KLxbrEl089PX5/Kz4TPHzjFbRGX5zxvopF3A8 c8PhuRGti8q+JkFPg5mtltHOWlCToHccnlivNTTwktk0ox+xmqOJhAkBy/tjO+6vkDj7+ooukVSL IRHxUep5rLO9tjRIj8kv1fLYPKIAJ+7hLsP2/BGH/1co/okMXSDO3L0DJzDRHucN1NqffAavK6JG 80SDwsZU9PhMlfayDBBu9qf59vaIw8f90nZX5XYdL9W8h/Kkp7shS8aBE1N/nHhEdxUrfENozxnS OUbwMsIeafkaLvqEbYpJ9jE4WyfFSnnR1R7zQxrfmF2gksujzPAHQB+jTqWtLD6YccbRcF6UgL0T wfYhW5ZdE47xbwFBKuqzoWu68rEZQFb60VVzJWErsDezW2CZLqtrb3qzmkES9vVea9Q1uWIAKHIJ ZCQVW2IucJhpm1geCevk1l+x92vLsfHSgDLCqMZiK6DibVBXs+w8NDyat8JjymVNV/SGjKhzGctG wNeLabegqc0g7NmZiSgimsG0samVcXSvGB+gR2jGVDeVapA/5HkE1RS49U5BgGQgzZmrp9OzXMeb LDGb7M87ZBRsXmfATmEhOExabSWcSZLvPskPTVg0ARTnqs+cYMUDIJVIM5qOxrqOp/c74yE2EaFO 5UCS266A6Nhw+FYB42YFoTYtnOeXmtjv6HfTeEnmxp8kHo2BcIJhriwoBdMvPKc1vGILPLtfLPNr AY5roVGBhv3LdScZiBT3Xg7llDXuuUZjLV6nxqJ7JzmV+IiWJuL1QTsIJron4487HDP7nzjoZ6Ll 4geIktTHRSutZu7KX+6686OgxT3HvifMEENInGEcTE2pcnwwFLMY5JLkAKlCCoNk+JCkFW60TEvU AlbYgTkx5kfCuAAJgAR+rSgphOLuzTQIme24fd1w45SkLopNRyUoVMiP5JIh6SLm90fxqSAb4GCI pwhp5dziNLfqsRHeP1eIBkj69Dmq/mChhsJB5cU8rZPIcNw5QDrcu4VRxP9jCuLoWtatS/JETkuN AGCHBCDmOvx7ULCPcSJT7PMw67PkD6zfMhFgMzMh4VAOGS38SjRIRufiinx1KlN0D4Pq2mYiBPvZ joHuL+p1W3vKBqgSG13iY4GvvxxWgqQIqiZZxkUo+w59IyHHRv7Dv9sxrAfe+g1hbLRsQ6hRIm8X UWs3+H8ZfM5guUBUGIGqpveyHWkVbGl5kEmelbYcoS845wgrcJkZS5udqSzPQ9ThJjvz4WENIdlF 0GwbKGymsH9k6yfR6re23ZovtL9Yopg26SXVFQySmm3Ojqmpt7lNo84dSbBkoEjnHS3p3eA7foss DIeSpRA6mKY+yHVS51qNbY/+1N6IB57gBq8ki2YHsFaP2a4BiEKqKmcZXzGvKpB5tMVyiOYy2RXW s+Up/trNrpAdcdqxrfrctzevEtL8A9k0LlMpfFl26BDmkMkcaV785NP1IQLKiGYE/2T5bhSkN+12 G2AicTTpFrT/bEEkLbuf5Swss0GdT+w2ilzo7xTxjVJWnjAFDT9YI9OGC0qqEG+f0QDjYdlfUg48 pQXPcRigsftF9tYx+3ehhyZjEagS9Kx+NwCG0jGI+1ei9ib3wqs2tqsPjH6iELLaidLVyXCpIzwo 18g/3vnWFYU78PET2OJwA5j4EBM5hKcpe91wAfNX4QVIJR5Oecjp1MSCdaNCHzsBI8YiMFTvtG45 69rFOe4QIEjwulUArGI8SMAEDin7Qnm/dYz560iwWrXgjlLwkl7W5W8Ibz3t8+0IVKIi0tRB+I+5 vX1wM9bgbN8A7nm+VFYdAhTmSY2U5FXnZZjBRn/xJU1tKZFnKnIMq3kXPddfwhWNCvUItHuJJy80 Ojly/SVrn1RjSJpGB7hCtje/u8rVaA1lkOMIUwHTKTJWqkuBh+mZLkWwj/hUK7maWxsHF+qWiUBb n9obJ1LnCbk9aReYEDMvsyvMmv6AGCnOkmZeCmOgMIlVeG94fBskc6jmXeJKKvKYZucV5o39+uNX uys/Pk1IEy5NmHjdTZMq2tfbD1lB5YP/D2yPSC7wvRFnYKOdSeBCr64RaC85WYqlLh5V7pANh8Jv dghmooI7r+ztxF2sReFenZfH7N6iSsJl2EeCojnC0f8qRQ9yK9H3eKoTAMKpaQO7QcPbUE+p09Bt QKjfAE9JdB36IsqtcaAfMmwKyoF5sy0/E75yevs3pM8XffyTFnYmSBP53ogcl7Ll5mbpTHO+ZbQB i6MO1+xuHO1+2ibaPQHpH29kUOadrN5N+J8XdgQrrXQAh+Y4UZ2LRlHn24rbxYP9N1aIAxGgBqMx Qj8l0IyPg7T4dxwWOGGuSPR+7OBh33rVyZbF8cMCfuhQY0b0M+T+XtSz/jZrkdi7ym9zXGWpWrWO T56OkVVJZjAOHNNipXN3/KYetH/iH10MR8RCJJoVofNxgyuQmwwtu6CGaR7F/CWZ4A9PWej/63/6 49Sv6zqQO1m9aHiw6+tvqSxsnpenJt0E7Red9MfXibFPSRIj5sHq94PxhL29ZLBy60R35m7BNU7s 0GnRfzwLm+EPrsV0MnfKJUUZXTtxTDUW+aMiOR7ZQCHXc9VsGsXdwvenzxUv4b8PVwE4xex5CvG1 4ZwL09GdDVyO49tXtmhNMULa/4uiwg1T/++LCRrvybFtYGDDABahy/3pNHwfvjR8hyKveMcOxbJv RvGkcW2RNzG9et1lbpkYLkLuS2lbMYE/W+2ZGNExhG8193HMFdfxUrMb9ZolGYM99qs6kCRNPZN7 tm2t3Ly0dB3ubuCIU6WayYL3yE46oOSaIOoQuejrrrvM47GIRCezvkFU9vaXzSgrMVHCXy/cHhga 61hgKTpJG4/sNbgPNtqCqKKmFa3Gu+74Em00WOttS3oFqxmfrWKAmp/Vw9A587PIQybUnvNXU9PZ 6qBncoOxHGqi31U/gMRBGKiWLaeEp/cgdbFThMIYSlfHXq2ZUV2YjHHt1paJbs4jPZI5/eNFB8o1 tyuvLSLE+rnmbI+QfAhI0YJaoE8dQHLV/zyETg8IZyA8guCZTv7IxVkKxeTeZCYU9MAB6JMm/4ik ZhXjPHXOLoy7PyXXdDgJK9QhrpVkSF4jIq4zDNx+okVBw8ZtGPytsUBW9tFBXzXn2bBl9jS8dEi9 xM6bxy1FWR7hAFlUyLivTGgXoketsTGQXwW3z+9779pUo2M3iXtwWXqB1OVFfN9fJSql3eu2GaUe MMzTLPyOCir4FQEYNdmzfU1SzTvv/ZzVPFduVTtzyQQKCnmgEKLuuuVEl2gDKeWiS8z51UyUZcsi Ur2PGpKjIDYW+5jCh9Yyol47qq/PoGZNZIWcqh7ms4qrSOKJS6Wu3qNA1bNkQA9JJ/I+8ZRlVM62 ralO6mxpX0xqhycyarhRjazJBjAOCLKVziOt7cJnQFYUWvINzRocqgbkKAKnfZshTBb9pxnTK+H9 wCjv8Q1HTZ6J5RbNkilEawQW3nfK94cJ4sJVVLEjm3M1F1cviZcekHToRPJ7OPLyGaZEx5Aa2fJJ YhARyVHM2lmXr2BEyVMoxMpN3jBCdY/ja6bynRAqDJCxbFp+xLppmXo31yxYhmsq8iZOvQWxjcuv uXs+1AWN3/0WyUnhD6c1dOGyu57PNbextdCZMFlFcTCNIhlsN7rj6oUxZzRW1yURSdt3Vt34Ojey WJsl4Ys/a82c+euxt2760gfOAYaifKN89b/UZ39jcr8hOl6hQc5QRsJF3+RV5nzcCnyJ78xEKbEX TpiY3UNaa5DDJnki1eLHQhhYX76crJ5pFSLA0/T18xslFflnxmkK+stFj++VBCuUhglDq8XMXZ5+ B7BLH+tVzDW++Xe+tkgoQ3CFWAkDfSTr3KKLnQdHzPyC3kvoW4bBNmeIReNvbvvhtcs/q+XDMXA4 zuyrD4pMAz1C1jbztAx8OM58E9UAGjVeCFadgDkUAtg8Hi3CRbHDqA42GcqHwlYopJwSkScWrckA AtuJWbpnFbVXXL/DkjJISMYWY2Qv4h3t9EzBvLUB49CXI0MJMQNkxigqcR2cvmbvnN1fVRHIXgwG NlCbcVQ6w2UzbCg3Zmtb9XOV1WOcIpHBh+3LatQLce5ALI2QcaQR0iOA/Xg+MpVzVZBsWrqDn1OA nBWSwGPih3uXUaxydbPHp0dGCuBqaWOE4PXAV9SbrwSifyUpak6T4B9Nq8/Dxcup9UuAzd0CnPX/ aNXr80iLx9g0Qpe0em8KwecjXU3A0Nov16pm7owMO5c3Gv8Pm0MSD6e9p4TOkj5pU8eLNca8M1oD IYFwhOXAOhrXZSO+7dapCMrIuMnWwFA0i9hRQVMrPcnPgosC/0ri9lQ+tVSUctQ+s8eQJNNaa52n kU3HqgPcU9TVo+ifvkUkA6AAHPNCZ8T8va6O/xPx8Tf9vhViYrfs/+ZVdwd327UcThN6y0LSPkZx hrs2Gh+HlkNNQglUmDfEnNMEKiNabJ3mJMoGQZHOf++MYn1ftF5Xj03xTsQ1pzbNpZVnztK6ZFEQ eZajlO8mqkDwGYS2Qfe54vWHws7jg2QHDL903tk9Zfcx9f0nYvWC6olFqM9/+4jeE4PyQ/XHIaTM CmlILmjYgK/9l9Lxej16IRq+E2VC4KH6Q98fTAK84HpWDtMua9hL2o7fQP0A5on76uQ0P5H7Hhn8 7OtQPpp8y6wnBN9RmV4eFv3fHI3lCJFuSDCD29d1hWGa6M51zi1bxK27lIMXitQakCx3yVzYtHHt GTBxn/V8/jjTETVfDNj2PagV4XjGt9ZQIH6Uz7A1baWzJ0Q07KodWYEWRZa9idLmaB5N8IYLxwNX Em/eubsuxFp4sYAvzPXs2Isgkw74MVG7iIVtV9yD+AnMYJKZ2+SoydYuA4hJxwUmzeV4mIcsdm1z shvMKt5euucN5ZBinl7krieAIkcaCClTIMrYQHUQhIyPKWulH8DsMEl3K84jqBtfWxUfqkLVFLE2 KVN5ctBUIDZ/Vi9yc5snb9Y5t7CANzAQ1xBUh+4cIWH03bjHvQLBKg8IVjUnz1HWfj9Ds09pP66e Ad7CFPldm13L7Nyp/mEslEJqShUDciMmHzj9F4vVOJNGv2hZCPamWFpY8Mc/h+5+8vc/d6mx8ii4 OvDlt+BQZZjVXcc2nJrpez50Z+9X4VUqsg1B1W5YKXqQAjOVgvl6+0cV/HMFjeZUkZOoSVFMixWx rLswZvk0b4yTbg9s8PDLnrXEChiJ6RzoyU4SeEB3jdS56cui0Nh3NsqnsYxpTWxQ4nyMoYFSN9Hf tsnvRlIFZT8xNZSsaZ5E6B6l5kwHZOAWC7vVa5t2oTDlURzqwUM/q5IAIYqSlqFU/HddlxPxhsr2 SJtzumaHGYnIIT39z3Gz1t87zcAescB3vucOtZcLr+4OCRG4R0DF5Tkwlg9anuCFpaynoeJWq6kd D22qDQuv1+yvukVKjrI8lhJdQubnEofqz1Ub8YeKRuUtHdanuwzAxsiCbJk0PDeWnptHCencjB+/ 25s3n4iyKZsPCltCdGr3YjoVGrMPdhz6G9oDwAqMpWZGmjJaQloANmRJJZIy9OXhiVSe4yRYO7so nRNehgBzUg1Jc6sB1YsWmXbli2bNLNEjYg9QjW2q1QeOrb6ZmnUZiSLQ7YvyjokS7UNwaXnlCY1w SHz16TEdV8mVmDMvzxRgIc61HnwW6EGQ9k7JYVsgMAlws2WEJFYF/sg5J23/UQzbIqk+orhEpBUr TnW3ws/rIUZRF1CMdEdY68MbBdpxVn4dba5uC0wR8D/ZaCzbKHco6p46s5tlWvVTD26QBAMv7Vn/ ns48G9jdp/C2bAvrW3OsEVDWSTESCMhdlkO9yQEi0K/UwGE1LGZH5H/vL61yPUlAahoyfWqKYOsY EcAO29ZR4U9KmPsrzzhi8h2j9ItiDnMH3GDO/xrgQevv3QqYtdk5mFXr4pGcK2EQBPTVwYp74WaC xQqyBfRYdEgTRfSEbGmSqxP/C8GXqMDj2PJxuGIffDLcb16FNhJIHmGuYQuYg/7jDlVUCCZP+F5G i1xJPLBnl9i+yQOtI3tmLM9Vm8+t2eTvskXb6lub+HWLqS+ZO0hFPVcFkffVH4OlvUTXbz048C8i Pi9ET5I5Vep/UC1D0Z35uO7PzweBdWIDUjYMee0zXDA0/FUvfuSs7XdFidAYNXtxoH9gp0vuq7h1 GVrIkumERhZzLkYZZkyYdu/1ko0WGt7GwuPlpcJciLcQwhcZT8ky2bq//v9lbOqBEjZeD1h/19et 3dYJ2b1ofc60Wgf0KwoA+MQopfD67IiFFXoKGWAJLfJAz8vEc6umbvrkU0c06jimRwPOOh11/xG+ T/ALxDAwgb1/qz7IEtlisPpLPT7N2HO5jqRNO8sry+0u0B23ur1sysEKWriXDGLvvHASTW83h/Q4 RAFs5eoIxvGF0IUG4AS4yI47Kjvflguc1c1tFBTm/lHntgUIvUiWjL5m/xcyX/Hm3OG4t4Z/DCfE oCpVQqXxWU8CsAzy8by+ofVVEroc6+Uu2m5KpXeqKYxUlo3lyo15d4CONtxYxY9o69YJev/KHhsi QDprPNuSJhf+c0wfAqOfIHUsVYSWxzOI5a/c9/sSObdil8AHXoYZZiqkdYhB4wFlmC+LAIGr2m2M EDzDzlfQGqum/0cpN79UrEUsv5O/hM5unZmFGMRVx+6z3QRK2FwQwnT/vkhucbuW/R3dRC6TS8lK gCaPCoxMArZY6gv6ylSaj0dnJ2Fbr37ybDB25rnhgcT+auKz6blcuY1kJ4CjKplRfsh5F9K5zFOo nkLciY7BAQbLSoFstzN6EYJsPyvQ2xNClYmuqlM+61NbSyIICTL0Kt5cVRuhO1ystrhindPocnsl FF7ESrUnW1MqM/whIghGLpaJpgHPpPAFOqB3Tn9vkSXQS+AIfCVg5vlqDIIxGH09ZQakfhO7iCwq uOXw5Rw/nbMxfob5sJoN+q/34kiAS32awLIpsbT8/2Ot3hEyLKLWeLk+LEg9cSeO+JjjSR19dBwW T18r6JZdaOPLfb9preITyOBQaIAWK+MI8BmPfExumb0Ddy0hs/bm9GLkUT9ZzgpOvJ7sgeJRLBhl B7ad7UTKwcVeHJ16wZS8u7Osh39ZXrvtoO6xRZpdbafnHOJLfQhdN0n2AuWBWSDBtc5YNOquBRhR hdSs3nhiloP/YVC1xgnDZsAk/p3vRXkfpTTjXjfU61BwPArov/qi+MH3GqZX/OmYY9+UPIT9dzv7 GmiBn5Y61NG1Xq8i83Z5L5JWrGHTRAYJx79iPhUq+x1QoVkpGtHmgg6cBNmfgy0nr8IUs3eK5lAf oOfW3VL/d4Apq83tK5v7pzA4Zm50iKPiwg98fEeeiBglm22kWWBaDg1+O+2CdseF9nywFxgJAAKc pZ1gz7K1BAImAA0Mfgbpy4PC1euTm5b1VZnaSFNhYNNTQ78C8aB0OBASpSsKthnRahMHcTJbqxhk MyfEowT+yZegG3FVKoSDhsJ/PWWHCgbaVpBmSNBkWnRcb0YCeSMdkSipAZWBqYEv5ViUeuk1dYKk oaetskfE5Fry1IUYVHI781rR//zWMp5RAVAJE38U/8FhR0mCTUKAp8tEhJEOPf9Ca2cY0qSD4bmO wPkJ9QhJ+Uu+pdAVOnal0aOVBsosooQWuB8ZZnV1A9A0XGVQUAxsJ+JJHTj+mNqs3QvJydwK7fRD 529Bm7gT3562fGiKk/NdSMQNWgBdvQ0Q/rVDXocRY2+9XkLDUqikP/NksWMiarbeJlB9BVPGlI4z h5PE3TRBZUscH5gWDaWfW9yZX95jXstPS741wcmz49OIqiSSRjbzjuLaT5uvcKa2XrRkjCRD6rYw lkUtA11AepiIpRA6rsSQf/2alHqYe9HOS8CzOvCItjW5nGAJtnXgXIxSWRlf3NdGZPFLjVQ8Qv3C TO6A5wCvXxEBk4fuwcdarbHP5UWTs8ijk1gtTAeUTwiZNUz8woDgv5YJYrPBYFug0umy+XRa8ppP 7ZOaT8k8MtueJVOX0I+K68qPR6XZt55HKog/pooonqyP0DUQq2Qy6n1cCOHtMl8thYKbPGdCFEmK mT/8h+LKSSwQtq4EhXfjt9p7kpjpeDm0bK+/3/JWh/IRHxhaW6x5gbhjfHwCvt69XE+SZV5gUxn/ QDwoedm8dXZBcuwSGb+gRJEsSUhPKGI6oJJPV0Nkf/a/hhz6m4h4gYyuf9DCFmFJ6a6adgAkRp6P tdw6IXx6sCX/zmgJUegLkYCYj0wGN6g8hWcz6jGbrmiTe4R/emguNUXsmUItPZcO3E2PJYxRMgPi isVCmaTEl5f7yaRF13b71XVubYnFh9M1MTyf9qY9eTr5smgQhnPOYPrGj7NZ9+uxe2shLpYkPD6B 9AoqXoGfnHqC0Msj9Yt485/5CrvXLQAkx0mbyArx6HXEBLYf06jFLrTFLu9z0rk4RvlQ0gjlNTn6 kWmWv+yX50Bb5XdMgZ8RnFka8LbglWkiOVGeD6CIAPC4wPV+962cscPY5OBNdPjg2VWuHXkhlSSE 1b9OMPm3QUe0QlUcAIy++nxu59Tt/HgYaIv73jihN3KfvRYrbBKzgwzwqS95DREieu4x8ioddHSV aCXltDTR5R/DL5I9ZHBXYOvL+4cthaOU5BkDhzk3tL0+DRDrM7Y2LZUy3uA1Th9pzDfiOMz0H5rC mpUYqdcfBXNyFqlY6KtfzDzHRwfkZbG/siDPU6ZNpBQ4ECqZpq1y29tWHoreawpB9nT02zMtErIj Op5McnWHpBuZBhVdVYU43I/g/3Kbg8j4hduat2Oc9VEYs1d2NByGWtK7DcYlFvC8cPa7vmcwOrOf HZ6t4sBAwIkKabXOGfnaZWsLEmyVjZxh30/w7T5+ZV0r43bXfTLFR9QJoGl9MkJT71PZvZZN45el UiNvv5Q/y/2sZ8kgKwwTwvAPTd6PHZDmSwrIpn56MySpJIXVTZ73pgSCKRM/e+610iDVDWbkFXMV LsPdKxEQbCt0Mq2R8tdXVXlBviqYtiWtdY533MuPFCsRAjFxxRuCC0Bi8lJN9ckQ3epqosB73t4i v/Y5mCjGiC9dBuB81Sg2kNmcpK1teHlGfUhTh9VEPQwyM/gC5ZnSpEiYX7GcA54FpSqas9Nwpwaj dxRttYUjBuae6GRxRSFY1BBw4j4NXhK3bJMS2wwxBncdiuzw76YFsrGk9XOlfsx5bqEgtVhByEDA IhuXQrNshD9VSivPtJLBDbHXLoqIdDz+2F84A+EoQ2fvUY1dz7pOK3pe4xaRpjltx5KWyaJ5wlWL 44g3ubXDNoJsV/fzD1CORxXZFDtdtEY2VAdNq6ExVa51/phyQwaDLBjjQcxZdTYMeg+n25bhcbhM /TRCnPpgEt1QnC4pw65Eax0H3jIixZxfbFw7ytZMeIjWbAeoNFQ7joQYBbgLBZnpTsDEM/afDrJz TIb9O47edwphkZs7WOc2lCMGWnFPupBGnjN/flxhLoNAkEWZlArKBE5HjFplgeNcxpJSL4FkphVN naaTO+u7VSy0m/Jaz2vxNvCaxC87E0VIO+WAzP4RIbeOY9TUWSaZjZ1pCMsjx2JcEyDEb6hQi9l9 Stk8jzTsOXqVUO6yFjnz85bQqD1gakH8DxFDW3fdlgHyCTEZV3L+9E3hgQP2mf7AsomUz2p6nPDJ JPTK9Koh14kLmPcUnOPhBcL4P/OHFVqUvrU4F92LGlTFO/SrcfsRKbTtBWndezzdYdsCvIed8dkl TIls3AlMJGBackmAx/KA3D64wPFMGYAn486dccIMh9/Y8USPOVB0wHxReADjjEGbTgGpstJ6PYdP 9iLQWkz/+DXrIlJeFVY0dZh/yArrymQCgbkNlFBPd8qYMoBmzvLU8y4F4LMDnxW9Wh8DW/sIgiNx HBOHOh2mU4WXPiAo2/NmPRlS+LLcFT91hjYtowayPs1n7AlLtiNdoeKlj207IpK4/UvBOHGiqvZv VFqx68MYFGli2O4X6n7pRL6bgLPz41HIzG8Bctwk5pX8gHdDbiqGVrcJT1ddmMApuOkhninjwjxM Q93V+efuaHBM9fM1cPudAOxQdriaZxG9hBCN+uYzQYZqW+NshJYhXeFAU/I6U3lJKBDgc1tshPNd +VpRU97JZe/3oj/ege/UjU0Ukt/nRfKijySwo5YyJIh1QFVZZPf5iSKhMxeRewkjmlxE+lt4aUtJ D9tXrD1vTxojaal8r845VSGPd3io39z8otrgWJoPusyD5xp1u8kM3BZOYEeFJc5Y9/UyA69iAEH/ H2JsWmrKnXWSmqygW+cpVzVvwOuM5awjjV+cvViuiLvzwAW2tR0w6sML0ugJZ/t2UWNXfRyzFCgv sglwFDsSTHucik/yO5m3CiR86BJCSFxgYn8sBLnxirpzgAYqtS1hthP9BaQR8CJQ0kDuLWAxJmGf oXWU8y0sfOpvJSArIxRgJb2zoEh+EDKsuJlom/CkCmTeiCD6yZf0PNgRowJn2lZYVq+WyTkMLS5k F58cO0yO1kkq3hfwtOB2wtm+uUA/pZFkOYur8GKXNsSV289yfWwX/oqZLDkLshPXlANmdZkYLVaW ck/4i3ASXVWUf57kRGAyavS3l860S5akEOkpRPdcKX2HMYQCt4UlLJ51Mrz1papmqp1dtQYO5Crq ytBL2RBCXQ053r4CVa/fq7O9mJDiB8bMTgEWU5/g2p74sn6eqsHCF+fxVFTkthdBF+i9X4KmEMWV DYDQalpb1xdwIB5Fms2n4Eeo7mTimhBg1Y9kOXrbRHSfhMug/1ZkXsl/Pc559+mozIkwD4ku0z+y rZWYFlTVghD/hhvYOdkM/j24Yn1RnrvWs/8QY17egC5zUjuvhJXtFGulihIpFdzcDtY9QtLrWuEZ 7mOpi47XVfya1LRdERJobHPxX+S9Da9yX3/GFHpknaHYqcvZ/ZNYwIXt2BZQpOZtMyuDxbImmNSc m2rURo3wH8RL4qILgc7neUORf/d714nmehaInWOrqB584kEt4chebIJaOHyDQHvrUnkiWjL2pL7R j7QowIP9N/FIj6D3Il1l3dD207cR3Nr8XYq/9ZMTqjkYBbSsljkJzInaL2bm5oYM8MOHL9YZ+Nme 7qEmeuKjHmvNsDRiig8bIuvZPNq5WegvfhXDouaZR6jH3ldt/aWiPTLzHDynvr2nj0KftqiFsAGc fu3eN4d/d5Ki992Qmho2U5Ub9ZtfGg/y7v1qMzTTHylmS6n7kDBdos/Wg4abu5dmMeRcvMGBCNo1 7LNbBiVWC5KWNTEcbbsR0hkiSk+6FLpSkhX7vFkKjI/PYq/blwrfDYkcREYUvpXiqCjtp29ua6OE Ivstn/UsP50YlY3Pq2VrXjNHhOjEUPnlHd9ls8k/pXiJgfd/gL2VHDxCD7GRzb9lGagaLT7e8jOs XkQjq+qKnPcil659YNkfUNY7Fsls2uT2uu1z8/mfjreDfSpQAVUqo7o6avXLx2O+arCP9cbt72Zm fxM49D6fXEjWogP3KVe0Esor5PNYrWrbUxeHKS3vDmx6ZO3ZG42HSWNfMVY9q9qSJw6OoSZ80Hip WLn4OY92DRTMQswHUxvxBBf8gtxleECL0l7DTUoE1dyJ3vshhHTwx7rWp2MoSDIGFkbmSzjcIVV6 70uhFB4uAInx2YV97F6C/1rwo0ADvE72m+aejJr/BjP0MKVyiddWGYacMmcVj/HtlVTi50XKnLOV Deww5H97FDTyeSXx4Rqe3UqYHypMYJDbXJ9oOC73Px3yEsGjcewBHBW9bcs5ALBPehuxXW5QLs/b CCyS0w56zKP88eRrVCPr6sd85Q2038kDWdrATKDk7cxNvS8PcQvflx+u6xEybHSBSpRvGFp+T0KD EGRiZMyvD/SLYTIoRuBJJIyePr5cBOuu2Wg6KCMPpmT4XFRZwXnKbKfFDr12Rx7MYfznvNMvZj2I OpClCs0gm3OX5bSLX50J/zwbetXR4A+gYGuUKB9qSYrXKVKYMzGqBZVK+69gKEqgx4uQBWVkNtji PN2ErBkeVDeeFkFrJKW4MysAz2sMwwX7KMqGy0T+njl834bLxoq0teJ+GysMsYzXXthyG/51CvxB 0m/xwE16/6NT2NjXlVjhY10UyZDghSMVKxXzV6DWOziDbss+OYIemWzh7+l5nhl8sPyd0Xyxis5M pvNgCwpMAtzZE82vY15tzS193k8Vmu4OPN/Cv9iQqNLNW0N2VB4GyqOsxLri4Aq8wUHO55cDATFa 7M/End/jXSnIrhrB5Wk5Er4pwqZCHT4nJTIaGhBYh/C/WFekUh3xeo0pww5ufGS1OysB9Qz/G95v mLkp3sY5qggmrHqPRQAIkf/tgw6UUnJf0fdHpdFUv2jNecMDxdcEDFnY31Elo0vV8M9/FfOOe/7l VpLM7Q/hyzSxdkjQtvUCw+5Rv3z0nlA9DTQpE8vhFj04iFRN1+NTCxf9Z+Luz1oViHcFFi+I9XhY anwlBWskm5kGjuoRKQ2d8X4dHS3lvLHsWXjbfsQA0/9KaiZx0LduNw8D/PGaf2meckQgmc42hqlN WXXEqCX+zPS2IYHbP5lOzqRMXJ/zWPsfujgqLmjhBLk0nF7Q0/uTTrTmVFyVlpolSVRPKyN8OzBK ay8yJtNsECCSKtDQA1PKdkjDrvn5PDZR9zKvAq0LtQTvRQnfqx+9v9UJsMu6C2eCkY5ppt7LPau4 UOf+GulZ0AAUUX0SWEYr/SWiuqFqsx4SkzFsPsJSWlc0HPzs3AhYcWMqaLKOQbHoUjbNBbZ1ARVF Skh6/k5HXNNzCQt9NYO/j9v8t8EumMDykqEA8mK7Y2v1DaWuI1M2iTX1MfbF98Eu+C0BJNxHHkrb rxLkihLXIxo9bdtBJWB2oI7AU9ILwIyiTM+ykbfwmkvMzEONqdJAPofNPnKDlOXruvVw8uqmv01j e4MBalAIPnuwTsrLZcv1uXNzVp2wrUlj9sMyPGUTgLY/2err0pYNmxLg41aSpripTiDAupMyXVlF bNQgHMGaXnb1KeiAd6L+ucS5vDz8XuSt15TzXrth0ftHVOvAnX+FWrjnmtx0BoQtFN3VCIXvk+5w V3rkPJJjDmcfmNnslVCQj6VqHbRvth/EeTu6keyqnF0veaMT1GNTDZbPom2XsGYYmJA32I4xKZyr 8dVI4dslHctuulB95q/Q3IK7MHwjqCKQGkMGThQzvQIylWvtWPyQ8WkXXCot4e4Z/+WAEFQaRWFo vdS3eG4Dtx0xF4tNZ9weidBDy2w1uO0uiHYHPYzeyXcxTjRW0cEKbppSF0y59KCRXIRFYE5iXjK3 ImhUgFVomM72By7YdUKb/N2ss5dnGqQH/kwa/X7NkiQSGOCM1mNMw1ldA9LjWK5FHubjj8mqOgSs 7ZA9u0Ov5qLKHq7teIBNkd5cT/taCmECuO+4bXItqV4V9QaKHRYXg/2gH6R62ImAg1hZHplw3Vpj pMTeaSNOJW33ozqUNRNXKK2aKhOHCyCAKLl/O3uxknSzo/jYqL62VEzYS4TZ+WPLc9TKoUuGSgkK CRanye4McT8oQjBKx6f9mTGJ9rMMfZcq52Nwwqr6msLvekjprbWqgvl8vyTgqCMUAtfvGrrZAGWf p9bpTS7UBbjPr+dgrz2b0kY7aamK6nvi6+3rkbs4sAHwQG3WQEojF7RkXbw3l2ITTngjfkHSqfne +RmaQpdSRx+TX0XVt25b8eFn+FbNMvAIVfO7/RqeZ5BhbgMyqg28TS7dohoqwVNxiKOAdY+9jANP pWBoX8CXlsWnE8+k69ANIkX7HgLCqnnUZ2jHgwyh+6jHDTVqgpiFmsFW7I+EPqzLFHJBO1SHsj6e 9H81EB8qRopNXswCquprm1AnOxM5F52TqZcjM7vKxnlycQ3JcXsG/V4Fvclx/+iWVDHHRj1Hc5Hg 4F/S7vVNTS+oRhxnG3ac09KPlQU87lzRqVH8H8A7TXG3Hnjo3zkVC4NF6TKZEdb2qkhvxpH9Saic cQCMenP7LPMwyIx6MHnSSQy8DFEE7TEXTJknd9x4KTBOLM5JdeXPxt0+OTD7CLjVCaBl39FWZ2h9 174NLoAjFzovdXMjb0UL/X90Ea0lv4FC1fphID9Tf6cjeAdfW3x+88lRvjxoX+swFZkKIMMdTF91 wIt1r5+f8ZYEJyQbgyRKVbOpcSDglyO9N8cLeDQEM3J2e0tDhCkoM70Dfp+xOZnq7FUm81ANkmQf uIDkbC+ViiTP7sYpOdA62RIl0JTC8zs5LnBWuMBPAWsWg9ytOdmPe+EWS+FTWraCieXE0jV5QUIA u63BZ6E8j833K6JC29SoiBYuubdS7n5kZHC03YQuZKbi8Te/NnkWb0Zqvc7tsZo8YIwLGHON1Z4L Gcxnp3jvbzBRgTypL3QP4emYbBcV0Ny5ZaEEpheZE97cWvNS0ot98JDg1sMGphFlpLWy3HSTzYFJ G6emHbw5roxH2JdzWzbPDXFIzAuvozd5l+PuirtH3kcq1Eo8CCK5UDa07pdlt5X+X6xG1kflUY/V m3TO/VlXWutwKXxNI2kW54/Ue0Y70heQHw6KHHfThavfF6cVLAgtNujT1LxaN1I6jYXstla1bIP3 CGj54CO4PQkbDs26CqcJNh2NsKu557ajSrNmRDmSSvX3m+m8OnsP19Olf4ieZU+aa/ox0icU4YCV uhjdd+I0FcKQ+50nF8Db3ZSs6hQ8fENYDZMZobNIWUrGANHDbwmLu6+I8CYKTZJgOy/bYHo0aap6 Dp1J1QIqraThxSrdFDJROQRLBrbyH2IOjiRGqK7oKtsihtWLj6n2+w0vQIzeIgz2GU60OWI64i5M nwjXycK8B8Okw7fdsWUYOc1d8Y1aOX45jaIcFgA7dmmEUene2s1xv7fJ4IhtDW3H7FrvqmGYpNbK zHcD0iGCL4zsuaAgMBsxeJRbUlln8VwHqZo31bd4IjjUPEBdu97I0cDZ3LR4GFXwdf96EKk2h+/Q uIy0FQl/3CISpXHgCdr6up+z6jTdFD7iY3/5H20yWTXkOzBpy94veoaOrxCX0EGKj+BpyEC9C8QM HAXiEUELHVSoyIMWwlaaMdfF4VVLYwZyHnO79Hso66yvNZogDRSz/B7I+Qp8ovGcY2BPLlxqMG2O EGWq+F7ebK7eVkFTdBeWP9FjnnqX88DVo+A7d5yQjoz+vTeS6YmtZXKaUaLj8kJMgkdMJB2mB8Pu fKfCASjog8nQTx9+lxHtClAlb5G16mEmxrvXogQgW6/qbhRKpL0O2gIdB70RgE1zeM9DUiB/OOmN YmXXwVCDOUGetbZxm2zlTqzV1DsN4+L5/CGlEyj2HWCkaZED/WlM4dP9O1NbsvxFTXleLEMaSmV3 FT57YcSncjsirUuQUvxzilnzVDXqmJ3kiyr3kdCfoCK58JvVxp2ryk7Zc7ISQbg2m1ogvHs/3tJf BrHRsGQAdPaaOozkXywDxhGXA5c13gGeIFwxdMSBlrqCDRkcW2IPM+Epv905mi2pOr62nNWhrV82 7iMCHINDkAhkRASWocTEc3S4c0tOQQlgJ/fWRnLMVBQTY7UkDlEWx+hoXnDpxkVLRkgo55DqGOBW OLKhnH1YMV+MPgRhBzfE6XOIUCQ8pGIM4pruGu8uwulxiM8a2wA2+fX6QU88Lx3mOpCmxOzulacr 0u5AuWtIu0+y/CccrzfFCUrXrSVIFu68ONWqIFwyZzVHB64f8dDN+iVrYSGOHwSx2P5pOdYx7QFp LsAcqWZSDOf5GRJYCbzLcRw2yBQjYzv8kRB2VTGFKMzRWejBwfS4pOSGsKNrgfdRUBZ8SJ9jdvhy nDMIybwo++p6CpEt4hCvF3Nxep9J11bhynbqTtb9vpJDfTaBK1yGGD9awu5GnasxYMpOFMINZuIa H+ZiJS/mq2GIfgGmWEfv9ksgnn0PQbUvG1Z/b+S0UuIvVcoeVwaQgjvcaKUC413sATCXvTxTN2V0 qantkbnJ2Rn8A2suGdKyscNp0uEEWgGotCT4ypmiJEVVobEpV7liIA+wSlWky6RvCsALXUUZiakf zOOx+2nWR4XvnZd8PS3hTakwwyM7Qb24F5TnCA1ol2ms4ox1cnOL70GJ6Qg1M6WSQ/bGzhnJUjy9 oXdefyf4yy3yFIg5Grga+JpI1IbWXV+K0GHnbHUFlmPgbm7YfrVYUpoa6NvNQ754x1zaVWkzQvrt SzAn0ZAfIFZPtVKpYOHA9ARSf9eAEoCbJOJE2mk32ktqjNNHKbMhvACebIu7vxzaMSMEaXXVytRL 6McfLFrrJ+V9NYye1jFeDtuitkL+70Qh2EGRYTvM68zzS+Es+TSlQ0RdcgAWNrSuUTut3PG1Gdoe BCY62dwRDnuO/dJXyDfqN7OnhrUn2vsfvkMWWjbkWKmX1Eksenq5vN8Yw/UHv0qlpEJnpLM4dody qUwZf5tmi7yp4fMc5EZK+QQAzkqRHUzfbKqkaHTGffL6e+zB7o0w1l6I4oUqkljF36zuIVG35o2x mrvJTmJDb04m/gsKjdhH/rhBHyCvQfPCoe6RKauSl2y1ljs//GbXT4LkzKw4NUL1gkxsexnRVw8F w8iayfht3ZgeFRWK1Z6cSeHhBKvBPc0NGSBNt1Z6/RGHmx08HM/vrs+rgexuFJHAzObLpPlslrXg qUEuOcqGJ17BXZBnzbnXwUqGJWs+bACiblVUNDQXZGNhZmM33yvYmhn4aMEqPqeNd4rHtrTSD9g9 msEaQGdD4wBP5LhNqm04aXstI53iGiUP/Djv0V2QMbznnvKVUfo29SMd8Wwv99Eq552WV8p63woT V31S/YdEuO5vGI2X/E4xtdztUD/DjGNq8TbpglAuGb7dvnQDdibYAUOWewoSLXOjD4iR8Ry1zOwM Qt2IDQZT51Qzg1UFpjQHhjCqfVP9G027R3IRECLxd+DVLw7z5bmPmx2irUqqqpPgvJJ+2GwtyJfY U8QuFnb/AOYuLtUR0o/yTjdqmR6aMCFmOm91GCg5WM6dc5KW1pOLjf1UIL188ghqcMwzxHymCoQs EsNKWB31oIB5A649p4SJLzrhdtfJ3LdDe8cn1vpL5pAU8QNMpGoDMslNYdKbqp9ENoUd7eQkRN/3 qNfgB1r4IQ0iF5mP+VXf5EqopxZZ9dBgk8FnVpdx+C/e5b4sD/TXZ5zhJa4KQT0WbU/wW6snROYO ihHaT9h7zduyfaQpY6Pz2AGqvckShUrRGq2qdnIgoKHSptoyE8FvDdd6RAKB3ATirW4FnMMxgJHb jdUi0VK6U3j7bQPo8+0MJwWlWAPP06cnmoTzkG9YRG+wmCWBUjktDzP7A/d/7w0dCACgJZL0mVsr Sb1RHrYjUTL6/DvrFyBLwFI7hOwRe/GGO09r7hgoN8/VH5nSKZBw8KBdcCnhU3bKYdhPmoLK7wUO charaiyrR02PNNBzpd5zkyv+4lVs8Vdzh8Q+XYW4ujiXrSZ0/hn00X3PnZMzOJmvD3TkUzTSBNhv tYNgWUhAja69GcpOA7DyTgPregV40YzidRhltVe7n7x/H2xCXKHVjjvIBg8/22lO2+4k1/9r6Xpm TOygpBWGatkRNprJx4I6kMl+o2srkgRttfqU/NpnMpLgLbXzLPqKdYYinjMEmCI9pMZs3YKmjA7D lCSqXqIniv4pfP/6DZuN6ResOw8DvhtFDpVPhStDdjCDDtWQA2MEdAkwSPj6q+tt90CiFo0zLXor eh5iymR1zzbU2VaA1OJIA3KsISaTnESD/eqnFULh2ei3uNWgFnRK4j8MoJuUEzzlqA9cO18ZejJQ kngusxsduIO5HYxN55oJThBHpdtLQmdsm1cFD9zYUULpntuI5due63haPVxQplp1mglBa8tZ4OQw Na54B/y0VEDo+Fa7haU2taet52WYKW2NxgChcE2NrICt5yurUR0sim/yw6Va6a6BjzJCP3X9K+DX UuQb8hTmx6nr/Lir6WKAHsdC9Xgk7dqKeEX4+Ok7Th8BdPVLFCoXKSvdceZAo6W1SPskGK4hcqgd 0qaQhD6qzMvXaBWWhjT8boSHPxQLh3GHMab/cgGFChsLZenW4U0cmRqjRqbMyMAS8+5N7O5FZT6z U8LsphDtNf4cseXvW7KZSxL/Cj7zfnCARUr22VU8d5TlZWXez0g1jggzw5evLfyCiEsAL7E/+qXE Jx4ygebaKUzsndg5IBw90S/5mZq/++FZjDrjYKJXH/IdzlBvSzA6yVmAy9p1HFHyRSNY7L9cMSdb ORNS/3ZDNpz+inD6ArMVc9qlFExYfBqhHNufui/IqNl7jANAYX9QaTRNorEuYDtyAn6voQcYFiS2 dy7hovTzCAV3SuUyQErc4voCAQJ01pNt1LJhmm6lfxxKKTbnka4FTuHO7IM2HO+R5RbLtJXaHFfW 4hW9+qRpEmQ1DNT+mTH7NW0OMPoyQAFlxq8boMyKOB/sL0++6noyelI3NuWEguwkyXz+IQn/UkWh XOatYLzNCd3Y8NxUlHu2uZWdc/VzuUVKAIJJX5FqD6RdTlgnzeq9hda6hZ5Q5Y1DJN4TegjNQNne l1RUAUmeqqKXLOcwJ/lyFCXhQw/tD+RJxT5wVNsrbsyTrGIcLTBMTGehv2wDYsza6+cbjhN7xpIx R32nIgx+slF6zN6cp2we8F0uhqF4HnP6/BXYXnqgy9MVsBm4hHz/P1SD3JGlitGHcFYkOi5QZsqP +meuEuhVBp8X4u+UXVNugLATDJsYyyQEuhkhabg99t3Fokq4uJn8zhDCPL2pDkSBkvQN93Zu2rg4 t3rK4HpiFYuAa6hNkWK2ru+HkGck22s4Fn4ialYvY8A5ZBb/RPF4rOkfgcgZy7mKKF9qhYhuYzhw KrzJ6G4GuUhuXGZr97PHbNlz9h2+BHO3VWkGmhNxuLc2JGQAa/QtTDCmLA2ijPaneHJpsPW/Cg29 Tan2OsOgDYkJavcGoPOekC+ni6H3C5RbJ6WJdjAkSctpR/8A9sc+0fV1LGnByRu6USjgyZsoMbFb /kNMdbwNM6SLMBLethXqSG5aICM9AodfnM2pp8lKbex94AmggLNL14qNo/oWS448S294p4FSr2Vs HFYr9Dm8XRgty8YIf8Bqjha7kW61rCobaM3N+PjxK2ItJj3e3XWQRfeVUGOx9jpcca3v/w4s6fLf s7oTEsq2Ub09QWXuHo3jEjcvfJYFyLuhr9vkZycbM6z8psmfAHtMNyLtPbm59xa5OYK9uBIcK+yq 9oXx9RkkOOjW/BVWU0KmvNbog1i7WFIbVf4i0dKOHzbstsKfWmyqEdKodHDgRDTNffBsjx1bwJ/I WcvLapR5jJJekCEpAiUNsdP0yaO2b+eVh1KBiU0l/KQ9aeUwY6kAyxpVLsJRJcc9pGWt0s/lFvu1 poIR3yomIFTaiZ7esZHVgYKF+hp+StuMkeGwpb56a1EgpMuAcADeeZWZZH3ezA2fXtzKATffa+JG iM5LYwDVP1AU9un02WhyNDyL/yUwX1p4kf6WDRbWCO6tl19/BvJGan3HemDXD3RSyW8QVfUwSJ2o omoFgxQjpNjk9IHriSXISV2TpSDs9Z7uk7GeCa6Tkon/kACt6ycn3m4uw7KxR90osS3swxpZcP41 E8U5KWGqluHFuH8ztARgKB01hpZsKdoON3QlxKyNn5v4rzSpexaJdMJrCeGWt2La0/LQzy+DS/MS DyrP2Ulxd9xMEjRg7seXaJ/if158EtqcsOL6U+q48FTwl+7mqV4hmFNg4ejU7l09CV+DtgQgdmSc zv1WBOBapSnbLvDcumzGR6+Q29oEdTWgxRbD9MMalpisMPj+4/RHLGuOdztHk2Fs4sbKre31cDOJ cHCt4+HweLFo4qhWSNLFxoHucFqM85uLwEs7Hn3wG/jb4l5y/qOzXeOBlko681XtSD3pSg7mPsGe 1os5G0XN2Aw9V9K6SnrSGhVrbpXZPH699KwUxkSB0/vD7dBEgsHM5j9YWUK4lUdcHji48XA/tQiS RcE0Va+i65QnPlNKX3l+KaJ/jHBWeoIhAo3jzfNdsEAMUVK9bipNu4loVMnWM26UcnocDnsOnWVC lhspUqeTyp/xraWoPBcLRU5PFbQSQ32O90JX0+ms+Cu9PCXWSNcwkZ4bQNlOGwikYJvxxEU5EwSM 8EHuXVpqDGZkZnFTBX1AaVW9kb/7NLU/ug/h/rRVlfK+KjnCM0A30IaXTCQ+zMoRg66K+TJwktKS O1e3yCt9u7Ej6kXlTIftg2ciJ4Ig2VO219WbBcUwsjic4SFC//tQKVYfsQCE4d2T9BTxNxACGK4c XMsYMiedE2iIfc5EKckBdkm7icF5vzGQ8qePahF2Zwp3JRnNMRCvTYLe++1spQYzDaBYklS5gnqu +Lwa/Er4UVgGIvkeef1eeoaQ+4dwHVibKJdTZ7waOWooFtdR9Ljn92AXm3nIwHaMXWGijSjJWSwn it7yJZThEbxabSgurABCrDh/UfYBnOpw2U65pv2FPzr9EFfQDO7CzxAHlC7nNmbxDweN6ckyNOAN 6SjiJF+rGCHtVsfxLNXZtcjX2pwgdZoICrh1Y3o/eKuHk38U+KNPoFu1YghVHKTdYycOX/5HWA6e UP8EAy9TxPgLG7KIdLTn7B1cnDbyUiQ+IGYqXY3LPV4S3lhVZJUZuwcFbwcaMd0FQmTxoqpuJNwe u1Px6e/Y4EFWwWZeO5r0ZIfgP2qNGZRu0m9XnVHyHq8iDErvXrTGgtJm3YeZ4ehZyuKKJQHLkuCF idO/kgQi7vMv00E351MS0ye4zFUx+HWNgjm4HqQ92HrkuTK8ou6tdqA7vLu0XTRQ/242WelB2w5W pTEZuXKC09/C6PNyRyVcQSwIVwZRdFaGWGrUTb+P5RkWNPV9Op4CGA6BAmh1OybRy2/Wq5uCCl8i bO5rTHHJlReEnwQrQUzKIQ7DmCZ2rH4WkKNBilAaskUSbVErQDlOs/gR3gFtoVkV8A4YA4LPLsWB cHVm5BvfaHpzQR2VElVLa5mIIahBu1eFTbzpdlSv6i51vzDUOQHrYmjj09NKiMiQx4fxTVe2Zenq bjxv7Js1zrh6qRDWRJLrpuCU+rPTp7n9/2VY4BwoVHlygj1wp/rlidAaCl7sE/AE/Upu6ajoO0Uu PjRNnm9mAGxRKSdf3GLIQMc74YEEXLBV4OPLrDBSE9Y5kfidW0GKBG5uME0jEMtDWEwNgYQZZHix VyD2xRT0w53ivaFfkRpqZCCUHfEWtQ385VSgoPQmE3ZlN9uTIASD04ijed5KHNpZDtXaSOvGydjy 6rmJvJ+c0cjPyi4x2qyoLuDTAa9PCzSNZze6q6MCQ4k4MY0//7FcS373vK2Al9fsyeazaE6Jg2a0 DdUZt69qJopdrO6nKNBkikQuAB/z2t5z9/NHM1CA4J5XFvMjiphC3aGVkVCxDTmAzI+GxWCiMGl4 RNv0g2N/G7l2//DqfCJQU1sb2DKbEBI/NGwMeDOKhzzVtIG1y7fexzgRCw2biXK7GWBKYXcRb6DU pDITdJb1d3Ch02u6Q5RWPieTU+cfPJEF2/0sawl2LXbTybgNEpbZ+43yzMblsykwD7J9czIMOSzo 6W7NhkpUcP6avGidZD2EfLOSZM9SJsCTSqU111BLIFUBPVERX1RiIArcs8dFnGhm3cPT4SI6KS9z ZWUTh38y1rlj1aUBczY92LuPCCSN79lVnUVT9gZx0cndAsd3U3Suh7qCMSNGeEYpzbbTRmBkiLBD 8xugIv792VDHPa7hpfUCh2epA1C6Bf2BuUEcGE43Y0ZbSjS+Urr7+nlL7XhliOtiplljd7uzmCkn hDl7+bEf91xX+NUc2auZ7k6nog1w/Cf8zHfKCoQzFwM+Y/dxOSW21N7WTxeL7PFA7FWdYuG5uoo+ NRToAlyTtz+uHBkvOr2gHKiVZpSR7Y5yi4zOCsD7evQNAl+suzwFs+cHWkY2ez3nyM/Ki8+dUJ6y JSZ7/3bQltgpmr1erduWKyMooqheb97sLq6rIssxxZhec0Ku0zoFZa+wsVtM/3QxR41J/FRZY0HU Mdn3saHxem6KXw5ylyIYcqId8EnRFwpdM/Ygzoa8/RCVq/9L0MixOvLj/FLCEwUSlYLFm5M6Ht/2 wkITx7mAeHJ31a+BwG8YbjH8Pwnp0G4WQOoQ7o6wz/H2pQpIOIHSy6d6AeBsDgvDP6BPyhfd8tbD F8LpIRGuHqNCcqCFk8RMYchlLhVUxf5HnJxQ0DUUYIe02ra58GXfzOJI/4Sog56J6HKVrZVzT6ZF VP/9CmL0bGHYz5cXJAeYJfln6PpC2P3HaR7W/I6ciXUsJrOoiutECS6gLARrD0Iv1tzknEm24rMu 8/Rt9gy0bw9TL6j7GCPmGtaXuUjVwAaPtxE5sdrUX9L9pWZvTF9Px0s3lpqQ5K3NZmLdij1nQzbh GLh5ozlmTAgNqSxbA5UW3QADWK4gP2/ZcY1PeKztDe3TMaGt1Yttn53f83Ypwytqury9RMVgLf0K 7ziLsYdLaGD7QQWMpK7bhZ+OIqIVjG/xU6BiH7V6vJViHDIRP6Jei3WfQcVtafra+l2V3VuF9bgL Ng2r6Pnde6Vl8hOl062K2J1lIavdL1rzJvh0o0e2AJH6Fcfkj1JiNrpUHGKS0v2gsWqMzlVxGyoO 1GGbgRfL/GnptLAzq4e8kUAd742YfGq7dWO+MA6FsOUXWRmXz72gvU9LGZEjmZhmtEzrStYdKKW0 TviAR2aSbeQvLSlKtG4/AFGvcYTQMcN8SogZk6ThOaRl4LEz+04fDVru533PKkY+usxsTxjH4P5V YupmVyJAsYRyfEJhWrtTUQD8wutZSlD1zXSyZseNn0ihSad4NfMkyxAdrkR6uGNgbFL2/Qpk8YLC wmIhUO4ZObN+DU2CFESK5LgcglGA8VDEESDKt7n0Y9yFpFhbQCkIS4sIubbfwHWX/IuvBbSsfZxY KB4maCC1u5T0qYw9AOpB0ZG79pC2wZ1NVOrewEPJV8u6DMYyGv/fbh7BNV5rb+p4s2bOlhUMJVRz YsndC2js4oUtzJDmZIO2POAhp2ddPRGJaa7knwPY/fW0GChmR21Zf17hQUTLpOC+3Y58RZmHrrZP vbd/v35eV266XidkWTRpj17SmFo3wJ9+AS+fZFSTr3X2g5tAOOIaNXMwAn9NmuH5Ecfj5KH1k8nD PZtI6MvOdCBU2qcQrfv5PQUcb0TzzhOsQluQDOQLttU9BWNDMqlGLYkq6zJpS3vSI+3HQ8M2XH/q z/xsUAWBrSMPSOJ/V7hpk2IEcEWqWFC5a+6mGmQXO3oynvfOEr5kFYyGEFReBAQ5SRq7M2tD3hIJ 6W63jsIAKofAgDgn0aCC2ZS6HfGWYyOKsjM8joqTQW1IYGz3BU6n4Mc5Dx6FiNOAz2TUijBTw7Og hac8xyz/SXZ0zJTbI1Z01RcUF3nWhS3MF0DQUL92nEV/8i9QpnoWY+amw151BFpZMGAtPumIHPKV 5Nv/gMW5pg7R78jZH3+IeQqWe+9MXktBai2DQ2P7WidoUle4sIqsWgw4oTDR8OAANKCyEcX6ai2o OBC20E1h58pUeeGnr72saB1Tt2jpwmLRBDBPDLnOTwWwRn4QccLZvgoHiH8yDY6Tv+YbqQYfpfKQ lCyfy7nqhWZhptycVvri+SKnBsnUrX5spJihrSYQ2h752lmVhXKKSg8fn788xNumz5PbHLmu14RT Q+NZ60542edB1e8GWj0orz4k2QRA4BYokIop5IlS32BRfqF6bQGiBPD+u3TCTmvAoSu2URza+iRj RCDokiXxjnCvUHZn57lUwZ2KgM+8SYVyASwwTUqqUnx7DCM5jLX9TetX2xbmmfcDoKOAGzHW9Cv9 tocC0mDifTHgfvatZY27YfT2ADqNWM1cL3njltPyPZR4CxAnPEQvu4Dbwgh3b42j9OqyORztWy8K Y/TlCNsH06JCHt5jo51d6X8rh9GW3XOQ1S0uU4bfJkMDZCwghOzCAvSMyKONydKKYv1J3kcXT/wv juK0DHy/H30pV5VPF1WP+QvrMQA8RIPQj6OF3DrKjjJ55n37OCc3Uu/dNp78qp3C4N52aOFO0a3t /cd1Na/HQK3JEgYc1Y5zlUGX7goaS0FaRioRjl2NKMAh1ww0rNUU9u96GLkwSMAZPkq8EukhZF0i NlDvL9yXksN3UHem/MOE3YhGAWNei0ianTQVxCgujtvDbNOTakMPZqBtMyZ7+32G1knPSKpBrYUX DvG4+e1qtyjyZPQBw74EatxsDfNkMQlHFYrVYqJo0vHBA1G/zG1cbcaBRWiser4VpjMGdvs74Q48 VaQH/N84QDsaSHSNsh1uJ8kH5mji+NwfojCFWJtlKQG2hr0IGcD5hJ0PkAmznvODeSmrM1aTtpLt /gUqT9PqGs6xVLYSgmTU33bR4EF0a7gDOa2mZMBGjmFTnLnbDAX1eDk4z2ORUIptU+lJGi5dluAg mTek7zLlmWoKHuxUFGxWOT0UuEw+jPQGh2I3XI8TEXSvunG6qqe2+iswae823rNvtDH+uuI2P0PZ t0E5WVg24uCowq9UnWPx5aAFB87dnuKCRQqXbb348XM2Fmiei9/hA+Evwzv+ebxTY5FHQd64aD9I tBvzEwzoCYO9i8A9IHJCBiBPoyexNXHyYHYM8opJYa9fBfm39D2rItKGCy2qUcUi28R5h4fmsVH3 JP5Nb8Rt7yZxlvkg9dj7O8CAXdV3a+Zm1kW4+F1sgi7vPI8MAEY5GWHt2EAWMKpDrbuN6i5qLA2a 0OH1bgrd30AL9xFg4M2iWuuRwMAH9HPUc56F8fPFkdNiVj3Csd+39lz2ubPx46fzoPQcEPbcTTLK S5yIGo2rvVDceFPmtHwjKQam1b/Sejue4S3Yg7V9FohYO+FmEAwoV5Od2jhTVtVNd7wJgKPDq+Zr 9Bou4PKKGlLJiCzyuXAnYT3g3KMWT397tJ05+ZG3ayuQHU2wlzvbvs8jOusDXrn4E5vc8yOLdXdr BHJRfeykzKTgqRqjwTwp622vfuJ/QB6fYTeuVYkNycDcP9/81Ca+NSFtF4HIfN1JGJRUKs4yOuWp Pv0ovqKpwYt0vlc/aMXfqT7xKqq7rbu5RA00u6xJFxrhhSqjNamtpkmJ7wMbThZBzybhNKgiEElm 8pbC6SJQCbpgIOo53RMwb6rsOvSHHyI67UC5jSzelfwssnwG+8JkZLlww1IWn1QQENnhQhNTXrFe bZdHZQVWnLAYLl3lAO2ghaqPWXI1thpgkaJkTT+I9wvmtX0TcG2E8+MdAhBnGpd+ZhMthUaGJwyY nGhp807lgz8Ij4MGPe9q81jLZn1rkul5JsGcF6EX7kUtbLN6LzVi8c8TN9M/ndsczcO/DTWK9jjH GQJHTYU0NZd67axFyq1i93OwvBiIEqeEETuWW6SK82QN0Se0ei4BKl0/Ku14JpIfRPgfq9jtfG9w BHotXCoSwTvjnBlgz7NosLmPMFLYuup5OZY5WRvvdaEHpZTQ0ooYbReXMi0Onw4KqT9wHykeKvIN ixYYPM5OEBQuQdBkATiU8+i+oT58bIuYU1LBsjogunfcL17uL0BDvphhM9Vczpe04l6KmVlFKTIb AJ4pcGblP46HNcw16n62i2p6H5a6btF6UQDHx3kGOBzPwCM1d98AVzDOy63BkDV7ask0W6CPJkyd dG/74u6Vr7hMzzlzAtTVUecB+Y9gafD5zDHUEgRIsKF/p57OqEKaFHqzxZFnl2RaSt5pQ7NgjpM+ iWaHw0fkKUu8ZFuAZwmkIsHgcJwqvhZ/X0JEwQWvcpMt0fnv9eCJFDxzqtjkxAYoNEayIjZ+84BE L6KhzNbBUKyZHGcJU7AvpAyXQGOH8UwtKytftq9k/qSiNYvQlEgY7oHvq8mM5yVjICwnFUCtQRzC 7OZ5mPaPZflleRqIW7k8KAjGzPZVUL2NFQP44/i0TC9h09XcTWURU+Wl70HJkwcvkVEM/JomHNUU ZUE+OUKjGhyWUsxy3x9kwZT1hG0pbm1mmeflFZNusUPzsQPWvc5l3jrIQ+2izE6GWaQOuT9jD52I Jj4pergtl9oul/fdavYaMvaITrdjHk6PRd6uqtwwk5TG79KTVaBSqqPIv5bugj2FGp3nK+TZIUmf 6fbqhJoxJYfdOZpy2gM7tFsGS22HoPuWXsYDL55Aszje0Uk/TY6JnL30HmlRjiXn0d24/JVj8ixM WQHpMbqvZnf2x0RFCG4qqHI2j4cRU27JLYEFmjxn0nWfOEDQtdcn50uR0vEjWpK8O8KWXGxbBlwl KwpUyc4Xq+D/SwNM0kYL9rmiEJCR7e8YG0e5ZUs30kpOZLkZjmULGE8djvkVWYUwgjyM2tzTsKFq SZ/fLHQx3q4poxpIP+XCm//LMhp0+7KCk46QitAkYoT9wrHBoiCVDfT4xvnbclxVqMPkYopbBNRH jzB9CyLseaNV69XAqpJvZgYx1h51lIsglDie19Io2+5bJso/2qNkbOji3Flx8q7swiHVi8cxucOD 2VI8RwyuLIHqPSSmG+X/yl6yoY4gnjzoN+Jfspy95jpbPsQIG2QH7MjPd+7WI5/J+Se0ziP7gvwh rWQh8Pi2fcYDsu/7EU9BaKIdjhDgpF/9hAXitj1eUaQpzuP6CsB8PeyRgy9SQKzheVf58jYjO6Mv CISkEom5fj4AAjcnVX3J8FHwuz+Zu44AqM1cqE0TRpLjW0cEdWpM64yGR1i7IqjHM1WAH5Ncg3Ow 1hW+TuEsfZdTxl2oS4LFK/JSgZGtE2eWDAv8xIyH7LXSTPCi4u1fc519fILZkp91FJA05MwnELNF Guju9yHSCiz81miogNM7UB/S+KxY5mqZiP2rCz3sEorrEKdoZC6HKNCXH9esSK5yxsPJS3LBdxqR YbBESxjq/Sc0GRZ1nm+fyKl0eJoPf/Bxhsv+fvh9HCVcNTK/nvCZezB4usRQ3xJJey9VDXP5qfOb MuBRQvJVKOGZbZZE9nN8V1LXf0R98RWhAnBipBr94Pbf8hrxx5UZUeAWci8K9CXlszgq6713Q/4P YqP48qMNflfKQ1mQ5/iCUPU7AQvpV3p5VeVE9LtnpTqJHDRkw32E1IDcomMFZdtxwpeEt8d2Eo/j 36vnFqrpr4Lz+GyStA+7AUIdMOfkCScqzwkju6iPp6HBnyUkHUlKDGSh4LMQSegM97z4UbHJKK1K o23vCN1LIlrxlJQ0SRDCDy/GBIJBpmTQ1xJ5Ounl+n1Q2WVs2+oJwUDTjBzE90aNo8/z+MD2um2A n1Uvgqw6bOuCrfeFoRxYVk+SIH2oJWO4sXsGHd5LejrZDbc/HsdpAPbxfWKpSn9/o9TJriWgEhfI Zwcj7320Ifm3agYAIk/dHM4GdvZL1P0xSgbJMxkF1A5OriTjKzr62HFS2DKQ5da+FAiGFhJSx7sj XPxhYZww8xhgruCSUW36qtExGWO6UnDxw4MJ/j5wtBuG3l943bc+oTSp+bq8IYAETdVelUEiMO9h MxkTF4vJ/72PmfOcXT3eaqguyoC6BGOz93lzJcQu5z0G/exFBOUwQOBJW6SCAEnjAoV7JRfN4gZs 5LY1KpDmKXc3EOZT419jmHudOsJGrfpH+Y5CLJMhQ9u0ZqMfOr5tSFWuNBYutKAgsUg2ne18fNT6 /hzNJ2oqU0g8uVrWyUvCCLCCNkUwO4EU2Pye5NM5J0g1TjfY9wWU5iUSRxlHESi1foBw8JvuUpgU Cj6KeC6/5VQIPbbH+e03VW+bFxJYCTfvGbh3kRvx10g65xVgIEz6IUm9Cv8IRiDxF9f94HvHlCNS zMHqIQWb4V0f6wY0JDaVIC3pI+oT3dIudp+5yeV/Np2NQUESAucQfdpJg8OyIoppdfkkE08dxq6L PWvkIoyLjESxpgDj7m68UNiUnV0AxVtcgi588p6W3bHovz2uX2rBMNnJcpC1BXF9N73xDxdYvyjd 5JN1LunDS+fnLKWPpMAixM3QOOh2nkUg7ofI7IycCUXGfjbJ59FsjjYqxk3xlhfoKHTIiAMrKg+i dVJgtPjSCD0Y8tP7d3HM31IcRtO0gXTGIK2ql/gSyaupc+eoaDq6XkqVA7b2gqiWsbZVSDxh+sws bh/2gT3UR9tOLf047/azXCmxZOEabkuuXd0Y5HP4Xp7sXSEvcBOSO4x2UJgAXJtOOTlc1hz1fY9+ DxHTxyXHf7afhTcUkznftF2AIe04BE2iFUWPvQ6sbwav2mTSJSYHsieFzMwJ1dBy6F8XHGBt0X05 EFhFD6wf+VblDCo7hdpnTorSZ6uXAuhETC5jAyBVMjAmk5q70ch0iYNB9ObiVL+Z0rEvKByNslrO HOZkFzmc3fB+xq1XV8qANpXAuwPthQiVSr7kWsX9Xv0qBARcgt8En+hBXOexcqkTCpb4SN+zbsQd /18sSiTt5Zu5cu3hJJa9CkcEtaMg2hUI4xUYX0umWWeB5W0i8NUVqUYIoOoomZltpcyPgXUW7VQi 18tdnRPTWTEyCtbrUGui+zVmUdqZOTXyZfgatR1UdxA+t2g1z+JF87X/COmUX6x/jKuGLCoZEKwC yvT5tbCV3cdI8XF0jXW636T/ZyAmjs2Stmzm9zn8Vf2HDVRRqV+hwNFBHdOrY1VUN9FfPtEzB+b9 hWc2UXR4oZA1Osp0UNuzGfO/aXGt9KVfQOIrlfKVAKU8P7VnVm5Mbzs2fye71bETisWfzpgEzauc YIKEUWpjNtmnGDsSxBlt9VVG6IMBo1LGZ+PWbZNbpMjfxcFAlFjE01EAZuKgYb0Brn+mWzPY5RT9 f8WxNrcCMCRN5OmBNfMaIGcof2e4xps0yHsNQvVI6Lj0i9ptNF5DfUgSjlFhERi0q/idEZt5Xfuf Gyo2mBbkiZA4ve6+JzTSIhBTC982ytqKqjm4OXSJq+7rpyj64kgVEI9bxxB2M6avhQil3OuRPHBH Sz4JC9jC6AhRbC0Jei9CUaATr56wx0J+nYT9FJmY0pU7Smv3FGmvDuFyiDSSs/vN35GVjEUcd0qS xvvWMh5XeoK+8ip/0EOMs2y6wC8tIXYHNL8ipmZfU3ChFoxHtXsRYUlvI/GDCMi2UOJn2cDuZ1Rx enyoxiLjE+V+VVydEoxOUSQv2WyEwfQbTEAjp/2wB+VU9WscNm0LwoNnWzpUf8p+rUcS89HL9Fqy r90WhDmAdg0OlRReIo/yyTA2awmiB/A5qMmwrEj6jW/+Qdr6FkiwerJtUd6ZS6YfgnUmWjcAh0Q2 wVJUqYgtuFyCcqWAMktQiiZyLkbBp03f+k61GJ/NKotlJBqssoN5EC3YiheQRZiuFwZEFn+F+BAH lgSQL+30bbsf/qOuXHKquRVk8L7sPucgHZHJMjLXZUSIPYwv5zwFFv6PHkBdkNicXw5QQVTt2c8D BUferjogCHYhhYslTkMALKrr17vFFcbdOHPJ2fr5sbJ59lme9XCt7yK06qUNo/oRIId7FVL6PCe+ qgO1E+oipN6JdVy8S0W83IlP9G6svWmontD/h5kuFeaTdgYW+pgg8i8ByFC6qEFXegDllwryWd2E dImhmGn4pAE040lnmB3C94G5UFu5KYJYZvSEXvmC+Oue1yJfg8kEJWbVktYh8RL9goQIVGEoUO7Q 01D9UqKKrkkSyJp1er6CZucRqwQGCTeTCdNY2/0xVjT8fQv1odd/IBxVpVK1J+2viZespqJhS/R9 4zWNrqv/L5a1sWd1P9K6l5h8ngnDtxf0E7fj6rJa8zEloVemYOlTHguYsPhxWr53mDq49ZbLRILC YJuiMLYQUAeDmHtfIchxyjc6W+A+nAbsyOWqiFY6x+Y8UuuAQ5TMxaDxaAnZpWHqKxQwMM/gLC2J arqAX4vgM4GtymnWd7Lnj0jwE3uSvpUbt0AeGBAvdw/50J6bN47G3tjcJEDzjTLB+/SGBJiYP59V Gv8V2r4hakR1qBwNP79yWVWLD9mC/6vic/DVPgJg06e8ZrH/AQ9zht6ZGAIK7oS/wh0mzOBUBkhI aMs01Lo7eKhVxRzknpxDXeytnl+LK/lOSCRK7+tnCMaHdrHBRAXURIzLdEA3qCmfW+Rb0itbQMdW X3J9zfkixVOsyoYS2E6luPX9YcxyYuzpwTtEnF4ILRLfA2otlS0l0lQ4SGaYlBZr31RB6yY923FL F0WxerAOqsR9PkNtu+KmoyPdJs0f2zpHOQ8DI0dLiSDtcCIHxep/rsewFCZEyr0pDfercZAjhL9j dyvJoRXEFOi5oc17em5I6Pi5jb/ItvEK3cUa8mt/6agM6brsup97gXiJ1NrX+hjYx03FZbVh4hS7 sbbXc/67IuYdgq5qmAUMYP4KwzVUDbdmM8DgiO5YVxfLI2z3k3yHnGydLUlp/W0Lw4EoGmHzE2Fd bgP5bW9m8aOUW4Ia+l5L5kgHYF6bznURQelA5poZqEtQL9o5EvgJdu240vQMmdfMutweYHihg/Ft nsn3gLDZ/6knQPARo758AjqGwahLuVLR/Mm80kH6/2JLbj8FsjbD5T86ZISruBuHofB1EntqdqPD 39cGKswKwSFwFSk5oEOxSS0MQh3DXfYsbI8FmRggpm+u109J5OleGmPVeGCqOPW3KgMQZeeugCdm selcS7fCh9JYfVaQy25dkuVrnUdWAGPXSweDuYHnxcfC6XB/lEuJnZmpIWnQoFXWkGEKTN0UvBd0 P5fPjtALLEG45SJeG6NHD5b8KVvlxtpPuTu+3XcQsbqoJMkaqghhESSMM8qtJuyER4zXjh7TShv9 UX7y3fmbLGP1PqPOXwylccanvPhnM6l6pim16U8+i4F0Jj0yD1uWRaPwy+zsppBPnafoocLh3oYG /QV7QQhsWArd2Rsse0Bc8gKnzuXdSpCExXl6L+f28iVYCMuW8/hiXZJan0YVhYQ9t9IBnEA6fYOo Lr+EnHHoBzkAkXpLfkRsUFjRwuem4TRdWaHdr1zgmA9V+N6QVBqXTqZSRD8aN/rBnJYv33BNb7nS J5ZBhzhs4sj45p9sZ7tfetZmyQrg8GCeuMeIrjoRnsBfmrdVpq8I0w/rBHLrvzX+Pc/MPk9MFtxA ym4PdKeLSPK1s9yRM1B6OugOjkjoh/hJ3GMmdtoCkAWMGSSd7x1PZN3cFylUyUDKQXOoCcSUGJKG t8deaRJcUgzI1nqMxtZ9kh8YBTlFnSwxJXNt+n1FmelGvlxQygnC8DqiJ7BXSESu38wqmoo+3rZf WNWsS04RuV325SinYy/k+tlgoQpNumjnLXF/hfqn8B/eSB96Cot4YpVNwoYzGIlapE+zqnCtGuB6 nfZWw1MjjhLZbFXUHC5PZqXHPC5kVUsADaJoukpJ6x6DpKKPDCB+NtkpVdd3ZlOjnOR2Fa2rvLNe tGU1qCf4/V0PM1nF7gIoWo+9gjo/ytENFyA2Ws7sLX2fHDur7Kp9xXWFRqF3Vvs11HrHidqSC00/ YRyEDD6dyf2Y2uHnQLi7P8p7CUQX8KrmVmhdbAdKEA5VnA6wLWSfE2KZX/FGudUVk3Wt9RUOzzgL wXom08jurTSEtyoolXnhfYwXSUmgxjz4h+YFHlfeqN5k1cEy35XQAUpAtJpKtXDhGP/k0leD9Q58 tRPmYsUGJ78lwXOq5R5p8nhFNnHAdr7oMSD7GRZeS4/1gYlQH4AIp7XhakIPbKTRduu+hM6cDzCB QpVgRUGrnfrXnsvDGgGF5av0CYb9Y7HLdRUGZpzUoRYlCUP7vTPuHENJaJW+S1KZBTOCCzd0/S5w g9ECLvi1TgSY1smyd5aGOvmpw4EGXJlEtRQVyhu00taBLXDAblKSJeLgdmJkhv3N9MYaUZWvtJEo 0il+7LzCVyn+cu7lyFeG0rFR3npH0lBJ42VS2qJ2RcseeSy+/jVyHdCUGeLKagd2vWNG42MYsnob Ekjom4Au4gl45hZnuk9fAR+gnebzYwHcFj+O5ITEQukmkBTC3kQgLnNd+9CAli8uu+zyJ2igP4Fx 7sbRuSmoWEl2S5Ov6MYdN99i9oc0MyIT7HZT+WrZONFu3A8wFNSOsQS0RAnqro3sbUQr6FeppNvh eywIkBo6A2pUFUfAExI6NY0mI/3WmQVwNYKM+i+bvH+80g7RWr5bMeG29qi+Nm0/yxm4ZiE3H6BV /ZP2KyvfCCapI3U4Bfv0OtNPK6KHBWwVnREtXE0qqAL0un9lWdoLEk/mamemK8qWDFrdULKLxxlf 3436Up3Psy1qNmupF47dZ5WTOBxGXua1mYwpvU41qB40NQ7CAEtA3Dap7n/agaTDRRt3xe87RaAF 0zQwNZ6bDUk0ZcN/rGIrNSEeuq7lpE7smriwjcydRsvRJgj+VNW336wXdz5J/gsU8mKTvs4pJSkS GdOnU9bGzJrgb7M41zS1pFYTdHUI21YW5P1qQap6vdfE5TAOqeKB8Fw3J+r52p9CQTGhXNFoUBP7 o8dXLxkgphalqempcNiITuQeuBn+rvqIwXL5eY6RNqcFHNB16B0ONGlcusr6rza0sfIok3nuaGFo YmYhlZnDQxcylzIhlNid/wiUCdqxwHTVTcinRpYHmSFizr+oCXCpznHgD5P6Ak/xr0tbP9KSktDf WPsoawS0oEVVQUo5ZRf2SmjuJgL5VqQj2Bchi8NSC7PUa0gJQGNL4qV7sygeN1j2EHFFs96kRppB hJlKGdrTXQ5eJ9vfpePTaGzMliAiFwQv81wQMZfWPA3+lsFTFNz+PpFoPMbYsUZe9x9lYtsDTfpQ ml6c+032EGss+LYcQPvLcMv4Ix3h5nwXE237c12PsZHt6nrqh3+TMQAqkPhplmyblQRSicbap2uC aRWQ9QAs3JAyoGim/2RNCNQGWAfyup6U5qmYoFA968nHKPO1/vXvF9cTShbnvuIE0SOzkUaVrLnc ig0oSj+fYlFOLAGJjdjfIhfaJgiSJBhvmZ8By1ZknBj97b3BxLPR83HF8UGRg/O4SYh7TX+dnVcJ ao7kJcgeAqm/r+BftahJGUNH+Qnyg4pyGu0kT9Lp+ADnPwpgPFAt6GKb9U0QmhkUDRiS+qD1lgJK fw3DACUvDJMVvVeH7IB4jfsj9DZf2ed7NJZnUM8PFtikSIUmOpDE/w/VtCBGZ+etZUtTi/0KVDHe B9BfYpFjShqFuWZVFlxK2JNETDiC8c9OdWBUIlPx9o+kj2Nw0mplGsa65ASGyZtIkB9XPSODVjii i1QeQGfXY8TG9xyc0ixPhpEmcTBPyLstdloZJZvX5Bxlwr6TRkU29xGekUMAJkDV2i3drQxHIzbt QpuNDgdM5p2KGhrJXqvBUQ6zC13JTmBPf9pzgfaM8WTbQvG5lJSU92zC41giQ9aAwVCjF2Gal6Sf 7xDRo4TyvwxisHxfE8CkuPvkzOAoOsdmdJMCT1/IYK/HjjfIGjt/89KZ8T7vow5RkPJd+RTg/LWV XCY+shCAaNTgdZ4eT2jS7QsCC81HIRiFSXngY1VK5UlTIiUYRkMDc7s9C+YXU/Y6ty//pLOhMa1C guq0168iLp1CRexo1R043inOXeDcJyc0NnyQA1YIfJBwlRooXOofnCe9f+LzPPcU74PPur3seiPB AnnQ/PeaZLo3vujRDZgimgqeXEs3batgV8mr2OfwQ3NgVoKI5WaIHpgDK4RffZGW/n7EMbhBrBHr qH2QKYVhN6cfgRPWd/nNAmHUnrgrzokzrOmUqvFVriKFNbBqDDUJYZBpnVgh5MBQQtbMLr5DvU02 09L4N1iaVfjclL1IeXRlREMrwWCn4RyDtnpdcxWdraVj/zODEHsA9jLkgDNtb8IyG2OOZ6nlHwys KLBrLImUnRbLmeNZ7eN51GO2MiOcOhh2QMn/SbyzPGCXRgxoA/oRPhR8z9Jx3ucslv0tUwXqlryS 18K0g20yko60NvH/wcPwF9jGhX1eF+kvICWUf4wjZWAqcJkFIcSMhoLeybVTsc2GWY6a+lOKUeoW pO43CwxBy/+LlHlE0iNCfrvybxHhRGxR5R7fhRIIOZt7AoqnyYmfAsFNKdddOCYNviuFXqtmW+0Q EFYMWJrbBTGrnbkY/mE+ZcWksqHI5s8RtM5CIX9brkKiTjRvo/6dJj1YOqgjKRvbb4VBFfm2gLh0 9NfqPFcUAQhynxrDah2cT5RRfGnkpbiugVX2MKN+XsUU3N1+Mpv7LjChSEVVxVUv00442zf40t46 YW97pmRkt2hVuMVv31/NVGF7bJ9DUEHo7Ywcq489k66mLy+C4l8/37jw+fXx1fMOW423HLlOqAsm INwvhEi5i/gyj1FAckTRrVjGuYdPeEG6kojPj1JXgEKPWyxkJVg3Yk89t/P9IoT4xND1LSGYSIks 5GZ1QEC3RZhNSU4IwwO2rlOdextKaApK9sHb2yB2GBjLRcK744EOPM0aXZZ1bsN8sOS0m1MamSrK kk7LZDUZADbyJCI4bxQ3Kyo5Y3dT2XpYC0eOx0UzFHBjnMxEIDSlAOrMpsoR64fKdYOgTvvb0jTc p+4uGySvXcQeeLbygZ7ZPR5WSSkB1MBOTKD//ftGda6dLd7OhjFAu/VWqy032pljsubfUm2co83k ZxOloZovn4dJ7TFDJMifV9p84fvN/L0DyKlqglZS9codOIT+zeCcxJCTsxbHBO6GIXAEVzpok/Ng xRchvYOO9fyXhg1EDzJNjo30l7bMAcUkLh8wRd7U4RFmWvarY3E+J6PjzJR9Q4vYNRlA7yBXgZPl q/FmB+Nii/Zwj/NJW7Ks/21TkxDXvml5lnr2GJynq9DxvOmkqovmxTDAYj7yUYX3NaTqqXLdOMCH DC4Ok3d6b4ZsmPC+ie+ZF+7TeE1uYRPdRTZ1wwvtCZTZDYmzoJVmJkIknpmqOa1Uuxz8EwnQ//tv rdc6ihiBRhNAXqrmygniVlnGcQzM59rcVXaJ+ZeSh5Vx6gJLuuRI0nk4InEjY+hNU//XWjmpgCsE VVC9JzcnQ5Bi7G1hXR2bpH62lHrttZWEKCJKHMsDgI3R4o3mowSmBCzPQxZ4Q05+BW4o38HlHyis Qg7CRWGip7DOexA2ynsoJHzbLglKRBwr0Bf8O82thpsIj74c9+zpaupkvjOrWeJN9UsgqHrQPheI IWm8ZqgUR7VTCeZLbwx4QhC6On926mFrvdT5fwEsiRDWcj6ao7sS6lIUz3rAKapwCgPyCEZUTeKc aVBkEXIn1fIW1zvsxMTk49AzTQxVPzEERu0/16nfasgugmIch8tvQRqD/OqzJY2w5Lu/Texqdjn9 nvtfS82kvrRwn7kEW8xc3viZt8vPLU0kxN+G+zFXhIOq21+1Sg4KZyP6bl1LcUAqFvLSIbLrBCK7 FJoMI6a7PjUmB+QtJvQXssbjDZf667xmnmJOp83EOA0= `protect end_protected

bsd-2-clause

fd47621c4d17c2a1bc0f54a5b8ff6b44

0.950024

1.825695

false

rjarzmik/mips_processor

Caches/memory_tagmem_internal.vhd

1

4,755

------------------------------------------------------------------------------- -- Title : Tags memory with arrays implementation -- Project : MIPS processor implementation, compatible MIPS-1 ------------------------------------------------------------------------------- -- File : memory_tagmem_internal.vhd -- Author : Robert Jarzmik (Intel) <[email protected]> -- Company : -- Created : 2016-12-15 -- Last update: 2016-12-30 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-15 1.0 rjarzmik Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cache_defs.tag_entry_t; use work.cache_defs.TAG_ENTRY_EMPTY; ------------------------------------------------------------------------------- entity memory_tagmem_internal is generic ( ADDR_WIDTH : integer := 7; DEBUG_IDX : natural := 0; DEBUG : boolean := false ); port ( clock : in std_logic; raddr : in std_logic_vector (ADDR_WIDTH - 1 downto 0); waddr : in std_logic_vector (ADDR_WIDTH - 1 downto 0); data : in tag_entry_t; rren : in std_logic; wren : in std_logic; q : out tag_entry_t := TAG_ENTRY_EMPTY ); end entity memory_tagmem_internal; architecture infer of memory_tagmem_internal is constant blen : natural := ((TAG_ENTRY_EMPTY.tag'length + TAG_ENTRY_EMPTY.valids'length + TAG_ENTRY_EMPTY.dirtys'length + TAG_ENTRY_EMPTY.ctxt'length + 7) / 8) * 8; type mem_block_t is array(0 to 2**ADDR_WIDTH - 1) of std_logic_vector (blen - 1 downto 0); constant MEMORY_RESET : mem_block_t := (others => (others => '0')); signal memory : mem_block_t := MEMORY_RESET; signal raddr_reg : std_logic_vector (ADDR_WIDTH - 1 downto 0) := (others => '0'); signal rdata : tag_entry_t; signal bypass_waddr : std_logic_vector (ADDR_WIDTH - 1 downto 0); signal bypass_wren : std_logic; signal bypass_wdata : tag_entry_t; function to_tag_entry_t(slv : std_logic_vector(blen - 1 downto 0)) return tag_entry_t is variable o : tag_entry_t; variable i : natural := 0; begin o.tag := slv(i + o.tag'length - 1 downto i); i := i + o.tag'length; o.valids := slv(i + o.valids'length - 1 downto i); i := i + o.valids'length; o.dirtys := slv(i + o.dirtys'length - 1 downto i); i := i + o.dirtys'length; o.ctxt := slv(i + o.ctxt'length - 1 downto i); return o; end function to_tag_entry_t; function to_std_logic_vector(te : tag_entry_t) return std_logic_vector is variable slv : std_logic_vector(blen - 1 downto 0); variable i : natural := 0; begin slv(i + te.tag'length - 1 downto i) := te.tag; i := i + te.tag'length; slv(i + te.valids'length - 1 downto i) := te.valids; i := i + te.valids'length; slv(i + te.dirtys'length - 1 downto i) := te.dirtys; i := i + te.dirtys'length; slv(i + te.ctxt'length - 1 downto i) := te.ctxt; return slv; end function to_std_logic_vector; begin -- architecture str process(clock, memory, raddr_reg, waddr, wren, data, rdata, bypass_waddr, bypass_wren, bypass_wdata) begin if rising_edge(clock) then if rren = '1' then raddr_reg <= raddr; end if; bypass_wren <= wren; bypass_waddr <= waddr; bypass_wdata <= data; if wren = '1' then memory(to_integer(unsigned(waddr))) <= to_std_logic_vector(data); -- pragma translate_off if DEBUG then report "Tmem(" & integer'image(DEBUG_IDX) & "): [0x" & to_hstring(waddr) & "] <= (" & "tag=" & to_hstring(data.tag) & " ctxt=" & to_hstring(data.ctxt) & " valids=" & to_bstring(data.valids) & " dirtys=" & to_bstring(data.dirtys) & ")"; end if; -- pragma translate_on end if; end if; rdata <= to_tag_entry_t(memory(to_integer(unsigned(raddr_reg)))); if raddr_reg = bypass_waddr and bypass_wren = '1' then q <= bypass_wdata; else q <= rdata; end if; end process; end architecture infer;

gpl-3.0

e70fbe8e5f84512a7714a21620219d3e

0.498212

3.674652

false

cwilkens/ecen4024-microphone-array

microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cascaded_integrator_comb_funcsim.vhdl

1

528,561

-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014 -- Date : Fri Sep 26 21:45:05 2014 -- Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cascaded_integrator_comb_funcsim.vhdl -- Design : cascaded_integrator_comb -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a100tcsg324-1 -- -------------------------------------------------------------------------------- `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 201664) `protect data_block 01Q5om3T0jCWxQJMbPhryVrOuGifBYcZDUP8T0QtHy75UmU3O5m8uX51FqSh5mZRqJB2aCiEihLs PWSaAvVnF0gG0owiHlIuHCWeL/iBQqlxCFK0vq2u+ArJEahDPzCfJnMZgKGrIuYD59aAJyL569fD zB+20DmFuR0Rg6Hni4Q2Rldua42fLHgsmoVciKe1Iq2y/RMoPT/U8OHdGvw6Wkb/M/9LHvjZQRU8 Hr6Qz30q9LjEMGVK3CDmLbbbKh4HUTZih/Tu9WrZWeAVaSpvBx807QEAzINcoEIjxMSP6UCgS6bk Y5inGMlhwxdRugO1Fq5KpvbyKAWyPob16zzQmTNrVhR1+yRu7zxnmBbDKKOj2Iz0LwhrQt/XDp4a 7QHmXGvpB8+nLEa71RAxntZSlUvtRVztEb19C6xxCyUg9p/bLZrTngw0dY8yYiP27iszi3VadSB9 l8iM8Qm6DKjN2hNSNBv4E3YHBU0v9eRZvteKFq+luMRODAzIJ5tlGfiwe5I6xitxtq3gZ42g4Ybw 1d7jUc+UV6TAqutkIQB9r5VwWwb9rndOl7ccnNCqHpoAIsuVpAMNCRkRZ9hyzavs2wu8luzaWlHE XIHJSflpY8h9RE4kpCpQPAUY6iuNmUupZDam8I5pcrmHVDI2FgqyzTzDzSPk9J43JnGzDh8FSo7T TXqs4IkJqUMmHohvGz5rpD9rR2X2VuRgEcoEVNjfG+iu52ny9Flco/aporshH5vubaO7MhiepExQ axqe/zg3D2Sp022cbhP+p7fjYiLlY4B/ZIyyXTNmk5L9b/ZfSEOV4UzoaRYbbXM0x5cp3FVrFO+y MR3YRLzkKytWW//1WKYU1NtHBd9WVE8ROewwsn2g5sxK7IouOZimrBfKamAhMxgeCQoLZP1IEtw4 7o5DP6pTt2UD6qNJ25yXT8UnOSf++ngwSkz8p9eGs5bi8D3jB7LOCQb7BT6qm4u5iT1FXbe7rSma reba8XLrwAl8Gyv+EE1e84j74byCFjN+aNBYsmZlz/i8h33b57BZ+0zkidWAsnqZllXTKSh6LKVG 9CPGUWEQBG9MShItZFdKUbi9ZgFwcptdarZeSLQAN/7vSe86OZ3AfAPEQoJTQrnNCEg28Blb2q9c laLpdBr4Ng1IcQM97Gp7qI0NqS7cZnhaTqZPmVWBytEWM41LImKv7QlYzGZDTYF9XdRgk4idddCH aAGEBsjFMN7BdxPuwRH7ESvSHi56d+NsCkF62MIon5lMuXKbrpqt3OLdi2Ln4E6LZvKJCNZH9ewz 70AErybauLTlzM5Em1YC9Wa32pCx5HXeLLT3kpeiHj+d0UtITrgCkgkuFiRoYZ5Ix0XMl4bRl7g3 PHbnKtVp35UM/3n6hJY0WKs7vlI5kzPOT3r0/KFt12NVcGDJwbMyCC3KPfFLCOWloiMcmUz0nw4A KTsV2roiw3rY0skJ/oCKUBV2K/37yoU9Ai5gdPysnIvWG6Qa0PTpI/ai9n6gbG4anTXNB97udMVK TnFPywA8tVTKkI44b4J+JOsZ7CYVH4uLUHDgSgyTdNxsAytfRn7IqHq/5iIQ8mpgxj/g29zGAk+C MuoGyYXOk1JJsjfELHYTv69lUM+kBzru4nVbD5eExnTVhD/wboXJR1Mp46QVdsv3ZrqG0WYzd2ON v2p+e5ebK8OuvfTIZxjv36FnqMvlaESXhKGQZ1DU6mKk7HwGQO1qev2c1WO5I/0N1+NXNlSdWndF 77srgcweLTOdnfVaBlGOOmEOn2ePCDVSTGQchtInyhhHfqXACFP0NWODNXL0froqo24W/p5fvdUY wtqjuUPwY32E9O3Vw86RWiOGyVYqqz8iR5I1IH+HyT8Y6Fnok9mbka3419JRNnRpdT/pKuY7czdr SEGPSpQMBuiKGYddK32pb+b2YE0zrLSh4b2kVLOFonNLt91ADBTyGCgGk6N+7s1uidgsaqYJuw88 +xuQL/6BWDouIU9WSB/G6Q3dsAKVtSG61QG4g8+Q+Is9X2fyVpFPdtwWARDGsvBQffsFe4nkIAAM 1bKH0NkI/kbSx9Ig0Lw0KYv2ao6Jtt/mB8HuYam0+0NlLEbTYpayfv+6ngJEgUWhonY/iSFwae74 V7EMLjex8Gy85vtMGbpNr8PQp4+wv+BveVaP+El8WOlxuqNDSxDAufIpFgNzEUQQX019qT3tLpLK 334WMzc4lYdSKttXmAe0pQccavQAqtI3yr/G02MmUgqDycpSMg//e/29GhkDRhnE+A4dPx9WNC+A prV2fwlRCC7QP0iD0U2XiWYrugyMEa/21JS6US0g3Vil5EJgXo5CzoL5gE754hUZnLSbnADBTmKY TXaTGpGlnAiCA+zpQzuzAvhep2DsFE7dgDh3VoLUmr6H2fq12pm1GKkoGKw1E+4bIJyF7KSgfFhW Ha5BIteqJCOkPLrNENpNuZ9iayjrUseAjnQ+9L5tZlz3rO5D7pwNvVBELpDPnsypj5j7Npbqx4RO 9LL01vFA0TjYr/WA8enzr6XJ+oa43mqWMPE0k7brB+c8aEcTmJdiN9/ReB2Ek63XrmREeEmiCT9z JUe1LHSJF0Z2S//vUAM3j5ToG4xREAey8tdSH5+ES94vRrU9ftMxKMe+lQHAljjW0oGEbZpvpB29 lnfkArfUAGx2DCIf2euHIKm9gMsL5CPrdK3clGifYXyTJmIS47Xs95kGQr/lgs9WJ+8JAWRPPuhO /UvjGXvt9aMMGfkBhFWi70rqP1Nc/2O0Q7bfb905O27Dhq+X5nsAJOvxTc16RDDvz2rQD38gkS76 UW0dB9Gmh8+EyRCq9sDKpnH1R0sWOmmA/FB7N3Lfcf+9IcBcRHjQ6xtJo8iKIc4zE8Som7kMxSOF 5LfCgsjfVH0ZwEW/n99aMMhnvHlGmekZQyffZJ9mHz6dy+3GZsYFpuUE9sp7+0EvZoeDhgLcOPDB bZVMoNulDAfHaYlm2o93hOExXBBZJF9+DGLBCMj0meCI/0A73k/CjWLCUwxE8pUIQcOrtWTPuHJQ cTnzoOIAxR1NIyq0CRJJdHDN3A/hnKAcOqeRwbS+0VduOqydj2QFYvoh7nMUeQxECdlNvSDwJXgq fm4TO61JkQOOflsh9dyH9ErAAto9uX9wd1YF+N4z5vUJNvyRaQYn9SsL9i5ZvvErQ7OcFWZD5Udh 2hFW+EUG0e2K7FDGDO2qKLPCpoH2RFRaXhfhdn0BntqGexUa+1+ZYLXX3PvAgF8jguNI4rcpdEKM FPbRb5Bf75JNVRHYrWS9n1K8pUbd07xumhGGH7NFR342a6mPI2sclgC8tQufwut+tUsMJqMVhwTY hxuwyNNACu9O73zBJjqdW+SJFJVc/ndYjmxdiaUh3sfCevqxC2rCC4DbEBUvmbtmbI1BpEIk4OOd /GJ3dkN7cokTbxjJsdgDDRyDzsSVTFkR1qRrpzBJAeaj6AYpUkilwbVzwm1WTrPw7arQFX8VyYkK acmLqtnqGhJhXh8EDzbMajaqQp6M6geLG/juqoknNdXjaZ4Tj3C9rrZQoE5YZQMSScPqxM2eTbLj qIEEkfruSVP+DtpD7AK4YiAaN2IfnVapCQKCVyTtoVGQAHBlCPcK2JO8Y+8kEAkbSOp4/DxAxZUt BtoVZih7T6zwhuJ6dZU3RwOeBetPmWUHE+YCmNBPjp22xHyK8KFJHPwd+YBSd3v7g13bkxGpVbbh lK9uDeXh4c7QPs72n0oVUiWrXczBAxhfF7ljXg2cksU+HSw4Iiw2MbQMgJGHmhsgbBoV9GCjPnh1 NmXEacOkm987h8D1g06j5IMpk0Oidv0JPo8EVe+Z19zB+bDg3paOKBZXCghf0/B/z+2mSXxuGpGB ixCyGWfkAOcb8YcB+bptmfwh3BSDYA50X/RP6aDk4FI8J9De0A0u+Jw/mB0ZQnbGK8UdlpXCjmYT l8TFmH8jQEMtOJBXBv1XdnW2S0RCwdyNPeGtASLD0KuEsJOdfvTtgnjK6eMURAE/tixx2JHqSwPx BYO+G1dNyAcnXsxzAM+irCLXVKYjUS9TdYTQjeZvMJ1FNLbA0KATS35wkT0BlFHjppIvE+kviD0f 7R3sbxTlg8zPyQg7w2CvrxFh1iBOyVlCzv3egy8U5PK18ZwqTlgEfdG8NPKbbuNY/ty5S1hGOCum QlL7ZuQku8LkOutv8JRPz+rpJqeRFCZ9GVWyAiGQzQzo1/3VxQpJdhxGx6jrJKKbAptezduE2rGP JAsbst5aemQhN8sretRtBvOLML6RK1D8txZLzoRYwIfMZ7QwLiSZTpDqi5L1a66rQblG27C2Ib3q 3TclYqAyY2Vhy1Ve/+5dtZb7NQq+kQ6B5h+0xlvCmiBla+qGXL5nKOV7qQWOBpL10drjKIDxxbR5 En/hRZZcRmbJzipN1KRTlHbpcDHEcrAgXFSGKNu0qAmUf6SYRTwr0fXFk0vWFBvG3V1+3QjYhy08 bQwRae1Nk/207+Sl5AYy3L/z9ngxxFhVzt+DlDA5ia+M0xRkSy3/w7DRRwo3AojzVXI4Z510Dpwl J0qwymTOIP0wlPVB7uSdsheBmqyt5XEzymsKAPx0VSxNy+6GeTjjLDfzmJqe02OEqw+GxYzpSeED FjgyomaCq2WZobgUdqPsUqIFswNCIck8rzhSFwRLT5bVaYUa7qasoblRcIbce0kFsS4lONtz9fAr 84zqF3ynPB2jEHx3rHJUZ0BPLt237zU9qthhz5+W6jEEYZrMfhWcXA0Rq6rAslHJE8L4OeYb9vjC D3ib20+h3q+TKfrGgDHdeMKEjnJvPawU+8Ly9mSyT6AdrQYETgZjrUd73697LdvxQv7GXhga6LI6 Vb48yjSG9EnV0E1RIZtazJstl4ePmvC3LttrDo8Uy2OCm8UVzkQu6V9r6/jmEB4d76VJzTTfrzHL ks0UhQeZJA90iVcne7Ctxdt3L4tl9f8TG5AzxH+IQqxHy+Ardfiprf4lPWed6QphulUONVE4KUKk VmHO6lke3gd4Tw9swSRVd67YMdY1HXDnYdGLUmvoapRFyKtuxrfWFJ9/3Ep/1zsvcq8qKeTSKkmu o/NhuAwVPssz/Q/spT2Je2iNDJ3sLfwFb4XO4wDvWyyRD3MFbgeeVpp8PaCeeSTa42+VFn8iTYJk XyxRSss1SJOdb3QtKqyPNlAd3bp6V+YudaSDijqNKkRqXfOFxC3zoyozui2IkbWGDW3eT/P0Y1Hr CWoXmBjR9YSosE/HvZeIjIi4N9XLFkqfifdIkmapLYfSvRF6+2/EoMRcvLoG0J3iK2/ZDutw20gJ q4aP/NXGAKijShWJ8dcLcCbODcfI400w7cjvvGmNl4vveaH6NKqOL0LXgfW/xPONe/sJmMnSSvDL orIJyJoeu0htjAKupKlvnykiXWIS68+FgXv0MXZ0QrAcJaDLrjQZz9a+k0RipWRNDIxAyq0FFQOl Hg1anBZvUhxaqeLcf8HcYcCBHxGltPvrrUKu9fLZTKGTYzeKwrcBC9n1bwZCvVb8Y71J4G5uwRYT M/FFXlizu9legMxZRS80H2NADo3B4RUJ+TttD0umbTpEYzdeo9DKMdhUFtgvENEWFMg19AOBkv8y /SWfX0sp3wBVjpVPQ4IiJ1betE4/w2ueDeIYxjklWnK1hKA6sIkTNuN36WgCoatzlAcm1j8O35IY PnB0gxWXc3gLLtuP8FalFxJ+focYSqiXm7zWaArvbdrX1vYSTqadupx/ITk2kJkljjTHP2Jld2PN v7weO7Nk+oaqW+3/Gt+JCrO6ZYvQtPdaheQYD6FWeKtL4bkTbAicjJP9pcWTY3qEVq3VBmLDMaZA 5tydXngFgRKrTEAvMaIz8WFCExj2wLz0InDl9XHur7NbUDXuU0NIUpkB3vzceSD05LHrCEyJkNgU pTIWIjPozH+MtlbXTJHLNWoUmqYHciqAHefX4QnHXNbv7CkklM/li6LJRab07C6jKIXpfFUYFg5T /o8aZX4jf5+6aD/DZ2F2pXkdJpSes9txGiy9v4ulOrxhY5EoB/ZlN7pMCcOpD7n5gupTDzfRttF2 YD58GsaSgYHlWt0q4lJnMisF2IHdQ7Fet0i1pdnpRBjBgEgiCTwme5RNRwtEWXhpu2JDRKGbFgOt edb0Om6SNjpk0DZeXMSYR6s+OzIr55Xak5kaZcDHJJ05LEDS1lNXdoIrBN6slZzZ/cSWePe7BBIT Vus4/iMJ6Nfw6ULMsZaYQ+yIP12ZeuJ1CmqRnsdtX3dwVOdGVS7otzlYOJU7U0IATmVjfkZTwxMg 2nbOYXTrYCl6aF+PUsDsNOpqR6MyZZE0Xrik+nVt8t+U3Qm4KdKRy/t7iyFuqXbg2uEIeU8XEhdv xsE39lDMZLulJLPRyafkIiKYKvC9bVxkMvU3zGOVUQ5kvtCPYMY8HbpL31nGKgwUbJ+SPIPQ0c2A nr89IpDFbzQO9rWz45mXuWT6i6AvMoeDQIBLe4MRvQS4y+Sl3DsAZ7Of3Ucl/xaIWGcCFw/2oErG EQEqln2uww16qbsCj7oBgLVF24V/dUj6eRj5NIOPP9UTT1BtYXQsb+lD4qjSakWoVseIGcTbBDeN 5GPE9tbbcYT6vYyhbHUM3hRSps+RQlJmZGr3QDhYrn55A+an5KXZypyZNH1+PCfBrFIbQekl6gRA qx2a37k6XQMgTsZc+ORD7dCe+n5OiSDmASMvkYlTgJMnHsZJTEG5w2t8lpH1VRWJ6F+TP+mdtzQo CH7lnknDM11G2f4vbp54aBqEIjzKYRefoImFBW54v/35VCXqtu1o7od0rw+oPOSd7ivt2PH5Nelf V200GZiuDNHml4lfSRPmkCgREEAakRkfH8DdvClQ+4nnMVYOSZxQwvl2++hVqPwcIeO7ZtfnQEOm ZMzBAS7qTGx2Fjtnjvgk9qkO+4scEFVzICeQvrwDJXN16q1B0iBWY2aE3wNADr5yuW0Iqsqtikue fyiKKILtbasJs+8hkpz/ob9b/gjcoNeX6OzORda7mf9L0Oeo6SnR8Kux/0IRf1G3hxtNj6OZdg3o r0D70dWb3kWCTgFQpMaSMFcHKIdMqx3orJG1ii1iIen0d2S3TVtFD8AQtfmPVgEwA/vTt9CdmV9g 6fiemkGO7mlggySWoheWqJ4m5C7senE0kbOhxrMw2n4vPHAHWliHgQFW8T8AylyRuWi5HsyR7ZPr HlMYvg1fBKqAYefnCCiTbnUCD6rnYLpC/HBKob4VzHKHT+p47lordrkbEGcRxGGLosZf4Flq/dFk hjpMzegVxbJ9NMXJRPO8ws9mWYPiR/zwx32UamQQqgrBSu3e6F3mf1M4owx6kXmDoIS0GWVpspuN z1RiQzm23XcDCS06kKYlf0YuijEJLpavmuHB2GhjDMex6WRy4D64vaNg61mtUHLmQ+I+N89ot/BF c9iecZo+kWav7YuzA/FigA+Cv6IIz4SYbnRc9HiUDDYHsxnpyQCJJ/GnNscNETtXCF7KyD6fO/UY eB4jNn6qlXmQJwc//tbmFu19mzP99JEYPKqniT6XSGnG4sP/OlOhRkgHKcWQLUEE37Qb7MYMHfXy fjQ/+ILl3UzNkVHfM17IeuclyMPTmOb8cT/e5qJR01Vs+v4ROg92kjzYiHZps1/oZ80AXalRlTva Re0MihMDo6QNWsNUyxY2l538/ERlgvoDTQzEfHf1/mqe+i/k1gi1xo1V9/+PCyXwpEqCOUbjH67r T9BKETQ9nsgvVi8+K54tcmAtGXh/Tv09HAgZ21bDQcpdBMJ3e0tf0EcvyMEnlJsBBJF1ZA7ns6HZ VmppUrW2PpTqMy4qqmqQ/5K6N+7TR6OpEEm3nXwpDxyrYWTQk2HjTgMAMBF34U8WCpze0OC35rkf jHxINKRyg/U2Rx1gGVI+jycHCeNhjWktFPLfQ09XcgFahJSlg7UDOmlOmgZj2NGeSK4rRHD5Ss7R DlZamtp0zP/Cdgd1IcgDHsFy/uP4swCpwlSstiJ4YB4PT3L69mc30zZiMcEHs2cjin2M9YZM5E3F p3BZh3iS4NBN86NAE1KUGY2Q7nD08DnpjXYHNZBWlIEiwvf8IRbX/fH+3KpI2MMTFfsecLRXMujs WD/Y8kyPI5GpOIHn/7Vz3AOEsYRVkKyuYx8ODfv5brBZTLDyauoHNP4sDJlCQN6rz7Y4qp4lv5pk pMs3ICTvk10BfidmO1jeeS+lEsZBZ0U523TVHkexlUCd7wJim0PAXES8uXacsNfeZNZ6o/gULbdE J41E8z3UlWckIS5aOzRQ1YJQ1wHpCYUSVMFdMJcM9l7BTGCMDvzTugTEu0SKBF9KFa9sVEjcT9k0 SkxajR3cbLDTH/H06+vyg3+gOrmWMQkUPa4AXhnPlfAD2tXSjGPWEXbmZKEiXTdZpaHs++W1O5RC pe6L1LEnWaSSC+33ndtuGL62YmqMrzTvgtDYLEieMx+Fg74Uc2GJ9l3PVhc//Ye11vHY8zlewPia aEGFRnbvAy5/X3Px5+2bTFWIKAh4w4hZj5Q2XSpIJeEzEMvGOLV2MrXv/lMaLTAdNNfC5RZ/ld/f DbBM4J5DQ+alRZEwsD/ZqfrJtD2sN00dBmCXh/WLJiqh6jpzG8yDL+4hWCdizar3SdsmC2LLnJyw CrkoNdCc7kTxEaBsA4MjfRB4jJKOgmQvBhsqQCXU3qllvkIxoZ4TEn75Cz3oJRdEEyjwdaeG86AA GG3Mg1axcGW4ks0QYXMDvcFtoAv1QtK4dBmg9ZYFCyntB/VoPggwJwrg17zfsBrXs+A+CuJgP0TN Rk6k3CE1N8A+uu91mkemLph3hwNj3mpZAmPdLodTjf9jQ8cvxj9jju4t56G4iooUjZntonwbvVKn 5ojxyaPGKsFETlsAaxowH2907MhbOrroMVk98nQ5PQLqZ+dh1+7vXVRfYFJB+GY2j0YmX0ICzz+2 VGQ8CoeLe+EzJ/A9HOY+b1y2YnHoneFyTtsvedd9vo1Sz6zXzd4EYmIHn7isWrYfXXV34Gag+aW2 h3Th3CV11iYBK8zKrhUDT6YKd/CkaVgrZEk4YKOSFvSGu8NmTkABNjxH5hTGgdB6I8mRdhe4diYA 4De86q0OtvMgWOSpCwC5ucFYF/LRx2AKrhHVOurgn79a85p93KXyaSxnOiCPH/wdP/3EB2GVmkrK ndiMGOLdRyJqCtFflQ50Jo8D83StYGduMr4BwZac4dAytw3K0i19VZ9+9YBaGquu3DuY/IcHWgTh hPw1jnO2a9cHDFJTTFCxievekzbuQXEoMClwjuA2+x8LLArfQ8TLDlCynF9XzuZTfbEL2Svhn/Yt lFu732PQ6U86RIHzHR1K+dI6qNMWXx+75aNu85wDq4h0zD9cNwVul5rGOIC4QLQA7f+wK/Gmv6KS 8QIHia7m0R+iKijGnnPxuj6ybDeptT++ru/X793gWiLFWlwfCQtISxkj9OPB0dO6YAdhWOEzbgbt KUp3SqY/44pqcivZSIsBALGN+9dQx9CnaWpE4zwnzD3QJvXkSbgJklPzTL5gZuLdtTY/07A37TcB 4IzhsnkAHh5E+Vo2zjG3+FjCcsw6LIepXL5dovGMzEQJLXxiiWr1P3B2sLe61NFTwU8xnLXh9nrl FPP7AyzVKY68TY5lnzlhgV63Oudcil1JW7jmT0VWqyFKMI/DdLhgzVl42H/kfSvijR37KlJ2/oSp KPmKw7tDwbWZrBKiCijiv3gptXOztaKstQVORZTQCqEpSxKxpijZQBp3bXjmNw+XUSsevD6iAlIg vT5VvukHL3k3eRltmEqWUw37Jpo0H0r1MVq1BUTfZLyRXPPZvs9owag2uHLHfwPVxwaL5S8nsbUk 8Z6pXV53YZkL1sFuRod/8wqkQ7qeofx+ZfVocMBpmBMJv7KfMd7PjZ3K6JzjhuTkRykH8Q4r9VkG 4dAQFw6xaPB3RhhtkgCxp3je3Ey5sBaBTsV88EV8/KBeQfcZVsFiNd7rRPrw9ceZvmmYLPzH7aKq M1ZPDriepfzNMEfXN+lz2ozcnTLj+TtiutQq/+HerCEcPmJsJa+eGkdi5yKhAt3eZIOEjyWdkZIR J5H+IUNeoRVFioB2KRNDODVMrYyoBZHfFUzjynsUTvA7HvNkr7/km1UO8pEt9OjVpIgLHpN44anc CGBcGtz4dT0CqM84ZtZfTNOSaKv8LRAf7dbBFh2b9uFhbht5EJmt4DSLSUKM6g9fKvJkm6QgFsLv urWaTy4R6Y85JLC+dpEovHk2woTTZUS4hayIJLcK6+3RTGFWgDqCTj+rMarUODhmjv/NUrnC1sce Hf/WjmNddS0taUQhKfR/rD600WUDBBCKET3cCqNe9UX/0qvj48p3w8NOURJGcQEW7oQI6S7FRXhf vQhOQpOsx09R14DDXgPiuM7e2li0s9iLlyovW9WLohdrRvS3XQ1RVb/N1RhSVcyCjJMmn64FM7+M dj8og9RwI5Xo4KRCOJM4Ybszci/+EhNz8uGjCQlPGoqQnDHjGVksKD8yRJBy1yqmJMX4DwPHVmBs A9+yyOsFp2MX4Wp2aCJSgxAaMrUtBdDpqne2egTD9CDjDcwpQ3hEojr7zWZduUlhH3YznqNZi49n oGeuxv1GuGF1GN9ikrcV9+ZKClcDQCk9tGjhbDOqMpd+0G8+lP2+wEF56rxZducjQysLurntwiq2 7X+qG1+n5ZKOpLsQeluTBVzhEvsVGlapsuxNgObfObhpYM0XN9DqmzW6wMy0wJoNAKlgdFeKxhqo +0SEKjAaxOGocLNR4b9vFHhwnpDsdUN1t/jIwi211DZc6QLlgbsNpSiHKlMSUEpAfzRrl6EZN3zI ylJTZjmDXkwdO9f8eIxqzKWfau2p/f/JqW9FuoXmpBK9PS7D64xgI6/1+zVBbUARZr/csy+uMwBs EogmNfotFz/hvgfudSDUlp7IPc3gpYcN97dnrWSyMW1tmUBuM7DOVJmOae5R/sVXqtjZBZr/Xigc Y5wP/7oRCA38Yi+pfTCjd3iOiVOGMMpR1Y4Dt3DCqZh6hjBN0xIgMk+szZ72GSGdSGuEx9rm8Y0+ DH6dLcJknAXWwgMOZmSAxyXFkTHWH0wARyoqYbgJCNIMBqOSJy9WW1PSNUJAE58Lfry2HuvnMJUk 3Vv0MR7arb9s+mr1wvs//foeW/IPfQV9aEOAVdcQJVk+qUM+P75aq35CRVQ81XKL/9P3PbBCOCX1 rfaX3Qpl3bQJ6lxIkhNfT2lGBt1raeejJULEIJFFEyoXRMrEboaVgTVxcw3EyW1NT0sLXoShvKCF pYMWv14390D63vHkcsIX5F3lGEst8H7N+Nud7CdOhCrCjie0kCrT0kJgw/IRZIu8/PRNfMc3rvJT 48Z9nLf12C6JyWf6+GtmfsbDdHWRC+IiWzG+lvINA/aJDg5QuYSTX70dANQaZAAixpbp2vGJHFzD ogPjCqMZ3k8iALzPcymm11b/jhH3OGEMN/fVHxx4HfXJRfq0AEOBlxzGyhA75Vyd+gGBik29qItT N1wYFBigk/FNGB5pzKgDXx1eNt+Q4gp7SoOQPtyXPbZBauUmYwG8sumW2xtSV7mNegLWpKJ6kNmH n5NgH1LTnnuFJgsumJP7CJobagHzyhdrvQVSKHZvE00/53gBhkKbme/8TWuF3cOTRj/bfwZmycm2 zWYNKcns/7zRNDvxK8OEFvCK73lZ/CDAEo3ErECnY5jXpqdSIDyneBvErQCZLQvC2bQGhPgdBas5 FjXC4jyMudRInIg0QmUlLo22xt7w0X+Y7QtfSIce/bD9zYwSIArU8G9easrEfdAWPdh2IrVPtHfo dIGLqHC7Z+MUyapnqu3M3d7ltKDQfBVqW+P+cKT3utjxYzZyfMjgMz3GWMvu5uXeGzwl0hKwuAqD Dt+8uWLFINb6cEsOr0+WA2HAOWIIOuJCFeoiyPzFhR2tpfOSC3iwzG0tgXQYD8w01VucAd6p2fJ5 WAW95LKY22xp23oJXhNLZSdeo/APWw41AJcn0UNmFewza/y3Hn1AhA5EYq8Yci7w6L2TrspeBNdC szJw4eFQzCHyNayZyzgbzzq0Atx4qQaDWK1k9LLKuP6NVX0VjDOGBibKekn5suvJX3zNOCdfK2EN e6jBaV6t2SnKQBg8YDPvUh2OF/ojTz9tREbRaH5hpwpWLu7++XAayQVBo3v2NpASZaoKpARgRsLh HHAwkPvSWo+xushxx2HPHsHxlFmHf72Bw5W5776TuWD7AHzv03edXyHFPClx9PNPriRTzRFCYW2H ASvSjOKEDrCk33ilntM9fSWoWa3jqXuY5cDNyn6L30YDce5t+MhaH5tIrFrwm6GZ0FgSlUsTzOLg 3RruOTwSS2Oa0LC8giKDjWD3wmZ2/hexCXNnmzPi+OUcHHl0rj2CSKEkOXtX6yUSlOtA/0Z1OQn3 qO9DVm9SRXZQstJt8wk6I2fdxDDlc0/DhA5yqT3XCLoXgnJFA/NWM7AEGxrfsFTIcvULiiJnOa3W 14qsW/rguCbOxQVGDnsMLOiZKOIo66R4pDltDoXfO64k4zJSWioaUrg30VY/vApzruOsw5ZIWPvL cxWK8PPpbQfmYupW+i1vSO8HEMuP1AgV7M4lh9T47WF0JVtLtruRqK4tebyr4aUULCNX75UQRepp rmEgMATHl2MBOFg5mx1RlTLTFIJvYG6qTw87VID/sAy1fcER/mO2NnPbOtRdfPgigPvJDTul8C+Y GOjIhZ6pCPxdMzqRTPvuWIbos9+l7N3TpwgN/FPkZQd95go1ORF+jifjcP5UPBCFKmu65/mLBkyy td9KdqcK3k5mSg4ghb7X6VawYfPiI6F9ceEctLWf5dU1atNuXFkbG8VN1rrV82vahRSZF5W8JXA7 9dadazHU33Y55ZIfi/djC/q2vGEFhL9dy46gKPF2LKyNCIGRAtdXSR8+5IVo9xCWZI03g7MxQ/p5 6oup1oeo0Jk0uR1D0lX60lWocR1xZpUJndJ2Nh8L3TLePVnLzd/gDBTmK9o0HPw2Yo/Ali+9qDwA kYoXyK4wUHQixA62c5rc+R3fuUEcqsQXHVvlPK+UusvZi3pwkF8ozUrDpFI6Fy2WkpirsGFBUXwJ UlMtJD1K3M8J6t1HxkD/dPPPBXbPOmGBl9sVvrXGeqeO3sFA/A0egqW7jexgafsVrlLoNrpxWDWb 5ThpnCD90nK6GwhSKSkBZXTkG431rZT3Ufg9HepsqK8hUfhOhgXgJRhUsClRQgZO6v5jeLmuHbrm nnUn8dXxSl3h0q7UuHRma/VvpJQQDmGHQiUIM2eIOaN7cTmBQfY0OcQtL/l4VAvkAX3XuhweUZCl gU0tQDZV5H1RkcBVZoAmxHKk2tnbBJNogTdDBvDaniMUYe2YK5aWqSi06tWJmLFlSe78mnDnDnIA KL8OO7MXjBEY1y47vE/yRvCcbMH92JBaYz7gG4QQD3r8GkMjJvan9wqeJc3SzGhZSanGDOXb3vQg juvdf9bM8xydA9GLI4KToZqXvBQPYPQKjK1FyH5kwes0fLPqFZiVej1v3n9Fly4s3qZB/+5HQVLs 36L8sMnE358PGjhzQ4NA8CqCKRYcUb8RMUe8KQK1XEQbr6EaOEavxD5Enl8pnAyCjWFaPye3DA0W YiwXJuVIQQGwK6edeQGlfeDG6x3QzuHG+HVvVNAFY2EsCX1UGgXPhxP3wGlardUc9f4JYXEEH3ui Nf61dnBco6dd+DOEB3NYsxzG9p2jIFfJ466Y32rfNhunF5dTw6J9DzKhMNLbuZXA1hMcGtDg0Ofx azuz9iyj7XU0tK1+v6o5Z3s17MYJ/u2HA6yiWrbYz4dLM/Zih9abrd6bly+0hPs8+Il8x81EFfn2 cFETgobdMg0gGP2r6zb54WRfIAFsrIVhmBekKntIZN+yM+udLFdReKbr4X5wY4j8SD2iz5aZ7Mvf Y6P/aTLJyBQ6w4WkyjaQWbjGY8+/T4RXaCBzGhI8fRP9r2WfhfSb+jekd3ni/pMMuyAkXwVt3RJJ H8YkwVQiO8aMyERfShgNDEimbtUhLKcJ+tVOeWC8aqSUI1DOxEKT7q7TYXhcY9cqILOvPjeSkfUI vrUuQOX361fRrx7zluREGmuRjRohBGKsXPdPy5BSdF8jHYl1ZmkwzR0jtXqTKL54bEU3QKoJAlBT gcaal+EXDb/ABThQ9ZjGarl1Uc3+9nIWJYr+oeyLh9Din7eoZ+vUxVy5fH0NWwbptI0tbmFlFo11 pdDpy41RHQjm3V5b5GLDdcPfXraxC7O0F0BvQVk/7OzaggDEaCYJKouwxmcFED8vWVbUfo2gQZ6/ Yr52+WZxODbZnG0Y05cPNjPGmjc50MIZtGFyGQFB5LD5SIKcTzHpqahTfTl88OFw2AV6DLV8mLEz mCoE3bCuGmsMVGpYmKkYQoDj+uHrVKYhY3gvlKYBkqXByNYJiz1z1XhUPyBlQB45sVVIuQHxyoFF MY0D8OWByGKYAOWCRXLzyqFRYSy0ALKvSaSBgCI449eWz0blYZJJwyV2g7A1REwIKCGHBmqhQTDy PVN7uVAYZ37K4roi1rtKx5fjpFmnf98Q2wPdHIYdvmKt5gJAYyzDDadhgA1HJtsMksHTsUEmmVs/ 0K1slgiNlEK5aecQgdMb6ekgkuU6Th04XnddUu6jZ0NMQMWpGA1BVwJA0CxKnaIrPAHD2OPdgY5/ WRI7b35Fq2nUn252nxyhiSdd3ZsYn8pjpCY8AagrowclhK3XK7L0O3AnkXKPbHGUAlemEBwU6jii Uv30nnAEvkN5BENA3A9JdaulLFGX4N+59K6eaWzWZa7NuvIkFWGyxY0mKkcaeEzy5AG/esKiaWNC ecDev7nQxqk/nAAeXHiPylraEIwWxAzG7TZ8WCSeizJVHp5sj+lh1SoDKyocVvq1JdJVXIj4qLSb G+xP0igP9MT3G7sQlkC3OcwSt8XIR5dFW108vfUHpGg/NWIFOA69G0zlf0JVznxc4Y6wvHPVnfmI yRXZrME932IOudWnRW5GEzSGwugPuCxQYREtd3qzqcoMjYvCsE0xHRkVyGOhP0zqdqszAhTn6FwN x1QqoQyGYPiRX7hOWmTg6pdFpZzhe7y0CgwlyefqPczo8DL8gnkyls29hN1Hl7GFDv/PIhAQDh45 3oniyM6HW5Dj1CvAHoosQ6itYXLaJK9sfhLsbTJ0DfdUD9gq2+fSNButlyTr2InkhxnhDcrbgWtq 1iRkHU5PQQ0C1OqGcXKLm3PUIQK4M/o3XS12xjG/AXFQgmIMU/1EbHH+rRZ3yRGsYT+u6DDcEyYn ZxTdwPuq53B/c96K2NsVTTrqjNAedHr5VDhC/R9OzE6TiCPveh+2z4bpnXH5q0k77yReFVTarvJY +lgug0KPy0nelo8MpS6kxsiudiFbY99Ytn9eDlgT9w0dHwt1pqZyRfM+Sh8mG/Azd7iVBi/slBTA PZubgvjGKB5U5J+qPGR5/MirWBTMN8KEaP+Ow3vETJS/ctBHWhhzEV3FfT/nSzZH5dCDw5D0tadt VJ0sam9s/UV3pVcSoBvcxUnyF4rLxC+AToWYnWjaxGczXVr192TBjI16XyZGKHpimd15MTiRzgIu O7qO6RyYljcEvyo3lgwgOLdQ+2S458fccaNJfxdW4Em7WlC+7PDr/jdzAhKb8w5svW4kkI3b+MH1 ZNv/x0t9CU1+hMFlPocSMt0dFxduIHVlem21zopfMgYP8ZpDbMg7xh5BmHvUEkZaCusHu/lTf2Oy Bbb2MtYOTka35JsT9KG20l7QBsG5T4j0MhsdJKyozys0WnTgRmdu+b5pj4gv0zMkaaf2kObmlfZR x1P3aBCmMzBFlktQxZJNwOd+rvwZC+8syipNfrOr2DH14fqHLV2kGKW+Og892INWgKfm780LLQOx KmDZj3fYTWt9tHMRK401BhA2YFnP0+r9BVfrCJccijlclkvE2flp2rSsqe8ZfpNioG9LPeWRCpGY jI6W9yzwlN1nGaB8hAo4oTRPc5ke9MS2OAGxJ87dJ1ZGVUQXT4jAVHrBPZts0xofNJKB1nQ6IUZ2 Dg8O3cPY9iuptG1bfaKsiY0IZQdFkgAp/opnt1tqIVgITPzCZJ5AsdbsDUhJnc5w/13QPX+u6SI5 +cJ4eakBj9/+lW7Xm8/CvxqTqyx5TNZvdC5kgWh9is9WMrKwSwF5yA30FKnFJDNxDKRhVDunC6L8 q6M/vJEEb/5HFZa5jm/e5jBtMpgZG7n2jPyPyvx9G6qp+k55F0kXNL1l367hyrhokpBFaR2O/glL POWMNJemKHL+/H3w3oU58pR2exvz2GexZt75Bk/xBI7Z9lZEygew2KO2xUuh6W+vrg5zzLhZnNiz 2rkgUp5DuyCREuu8mZt07mN63i9V2BZacVcYbAcY1TNrV2ACiOREBDANZ+qp/1f/0tTh9oh1McRq 2d9lIChAQmFWbM8T5wuwelXcm3Rxgp4+NkDwySNIR0rn5nUq5mwO79atx1iZO8kwEKAWOVhB75qL Z+K2phRCZapqKXhgNsNWMpW45HPbIJLpmOdV5LEymv+R0ZfCMACUerKd35U+Ue1tVtK8KAGczbWv UGG+92TFFLmmOBpFnxZH0NgFPIzOKQ4WsiKwlTFQ6t2H5g/FoF75hqJEexRtJTZdyp95iWNdV71K P/ktZX02a/ld9HZ+bj2aR+YFnVoJtS+POcTDdie53bwAj/fi8GBZwI5PCv7AfQXel8g7WHVFehBc zfFhRW88N653PaPboYkWV4o2fqzkygwyquOWTuFcoHllvJkPcakpCubXTjZ3nJ8k9cNQlB1c5gPZ 4YgEckNyk6mcPiG+pdASIwtdVAbxLWn7ny6tlxau82ZNgykFScW1JNTRxFM9m+xBZyFKQXLMXnvK 6ZPKhhjYaBbbLWrzzzJHQ5/J6/y25y43D7BDCQq2kiSXXHJSQDA0TEr2RC/eRjhPH4U80iQPbxtB e/cZf41ztepAndgKmUkknB5OIp2SFf0K2+lUyOyrJ552Zq1mrfxhLuBGxFzSih9L8AL4hI44mBx3 Nu5x/zD0DcIpIYxzYsd02M6vMU6S5TJ5cHq8+pMzuB9iKSmzmHparvSOzSPEhvK5/OTASbCazoB1 ZNaW9u70Ebj361k+CnjfFGRMHJx6hW65Ex/96d9WCWocBkCATMCmj5vT0ghV1D2LvQvt5xql8jyE cNeOLVcKrMuFPs0FjViBTswc2QsY/rBIZhsc8CDmSCWDFCF3WskDa6m7AzqvnnDPF+XYx6Y5XD4Y VOPobE1H7kHxfo8+Gh51sgJw1SQ/HMDgfvmCmhZOFRB1f7h8Yidkj50Yv0memTDDnbY6MC05AlLW qZIrhdOUvDZZXSKeuIi/NQ1auw+0JpxfMRrvNcYOZUugrcLF80L1IClxITubQLpTG6r1WJGVFvo2 h90REZ67WcXuzEyy5xiBTNKKdTZQextGVknNLyHrrUoDEBUqeqUKADgpyV0wevethEfPdIs0CRbn QWf1kvSqn4G1esJLxUf/7g+Pxn8LYNDb8iHmJNRjnbjEbWLW4sU8l+NDhymSmFRx2SPPSIxzBHEe QPIqL/6ZtAYPBNuncv25c5bsZl7VLWuLAnt7UIlX2GYjuO36HOiVSCye1sQ38/T2msxv5ie6vrnE 0LIhc5DhgSPSxvWWFHMydGWMeRk0lMsPI2XkLwVkPMM7wCfWI+DK4fpnKvilYh6OoyrKJ6ia9MdJ 4AbouNkdzQ7VzMqarX9OLIhghWYYk3X2kMYNtRjlZRFgpEa8ZSBgC/QBE5hHBhWyHN6JXfxvNMhw VH9xV3RITh1Q3DLTs0NYTdvp2BI3NOGanYOVL3AH78CpCFDBEqUWWcQHURVbVd9GKYGPCgQnjEiT BQPb2XGALd1bBnQJ3r4F14DF3rWbdWc86Auc+cxCkaqB9QJWCa9RAjQdSLHwMlXhNyCMqhs4za9M U4IgZH01p48LWcqDcwR31lktksggzsqo9XVboPXmmbqVytTmum+J3RSD2z8dMs8r55P2Yx6NrlTE BpbtGwaAxmGWNdb4s1YfllWyC2O8Tbbgtq2QVtERcFWoPJ++jv21wr8iu+m5REEP+62JtUUadldK G1cRYEWxWuVPp29w73pxMKTLo0A3t/bng49qqE0zcttX8klMhEyiSX3S+6tf36FR2zkrZlkCOY7l NaHFlwDsMq+q1p17K3WaX1DIqBKAlUe89ogxnX73W4V7Jr0VHzGDdFVffzl0m+4ia6ayNIiwn+9q c3yrsnd4WRjQsBTgQ4SIwQkXxau9aqB4Y80e6EP0y3QIy+gqM2Zx+rXBSb/VfbEAMRkfzJXU8cK/ XpdjgwnSC96h0lzD7pdtTaa7pYxHJrv0E06quMZhZFqLCG7SBOFuxPjd9t9hYoYu/qI4JhquuG4A vlVuSECxfSF0U9rJ+/eJNcDfXyOFbjsl+vAW1bIa1wI1lx3053Ti51GRFf95iUNn9PLHGNdxilWO RCoJgYPJS0VRq7967l/2gN2kR6e3U6ZnRLwbS5LdCJE6V8OalWDrADDBgpAvXSg3dyIhQA68aHK1 Op6hPWN5NDTOQQVxISEx8z5IzvmRMzuJWo0PZU6BpBJ+K39FQhDQJjBkrXAi+o0+E5tQMAunWFCA gsBi4lkS7n8OpXgaGwZ/Mosgkndq9Gpd0AkX0Jktu4wbEkja9XxquyPWvXa1uPyC2AxEOjqOkc0W Iu9XjYU6pj4Lj0JmkcXWQtNbNnarqfTrU2n3jV7RYR9tsvUwttDI09KOh+P3zYUbL0hd8Wb4QcEg IynO/jqRnsUIBSHX2fwIrBhgykFmM+ZCGRXaECRG8KhVvzGogzNmDQJsdX6/5KmkQ3UytVGgc6cC PKFfSCQ2po9HgDyAxDwvNsqZSxUrtBun9nReDyu/6K32iONg2AGW//hBFgNP7tIuEFgmzpFsU73h E1j96uKvI/QQyg/UAsvdGPR8naVdojQrtwil6g6ujLsvXQnovCgWuum0uMwX3JX88XF53H9G0EUm LfrWv0ETIdx2WyIFj3Wza5TsANHm0QYPf63z0Eh+qrYz3it/zg3e3nb7/V6A4H+enOW+w7bh3nZe 5kKUcn66cK997FmGCRZxy+9OOrn54BNeg8kABdcuS68gasYi+7RFOhAZsiC8bdzQrwRS7Mdbie6k Yq6bkZaI8yVVqby+EsNv/IMZhCREnM0YPLi3F3beGizg+2LHtw56d9C71RrTT3BhBVTvIftWto+h hTJz5jtJp0Ps3xibiDPYOBaWcg9/BSAjRFlMdztaZYcQzoVIAPdbnB/TagHUQTJh0O277HTN4wnk HljowITHoyQFme4vAEsRNMtG0UxDD/jmYciWsvqmLZwArNlutPLd5M2cp0/36QAQE7I+BZ+7bEOl dmbhKqYBRmU6SRt6NHaw8js2QwdW8ThbA0qt5XLw+2QJqEb6ME8OBqzucPvzQKleO2fE1D+jvoRY P2R0y406KJO7laVsBR1UBjKmZgO4CCQED8BKcBr/T6mwk2IoWySdTn2wK3E62kZpuJ33GTR7jw3L px3RdeEDRDw35HdVgAx/UCmnAfpEwh0EDCfRKOIGnL0L2w06wQU77dBOoFeV0jO4lqT3v1MkvRnu JqcgvU53iOtMJ/vOKyB9/Is33VxN3468frN0JizfaLB6gJ9l179gMQMHcMVmWznUtxhvQZPklfxp qnm/qcgB5cBRq/rG9ORV537G6maEC7O5rXpq2+x9JVQv8wHEF3JEQ6GKdL4LmMjo/75V0EwMFmi4 CK2+hEIWdUpC21BfdvjyDgZfdizWrNH02B+0vE9M9smdm5dCG98ybQET8FTK1Lo76gR1qfGS0wAp fVMMmWt0VND9ZMzrwVRljxqpYAKlXAQfY0R/xA6tCxiV6t1LQnUGLyFwGBTHG86e4p9tEOUQ1281 l5fgALlv5r7ao8Nkg9fhwGWkZBPmY1zIlqaiZokkWTstIeXi93XxTxvs8ARekb2VzGlM+pCELWTE uDzjT3+C1kNJha9SWZDhVjNrLWaxX6esR+AgMT+oPdqsyjg0tG8C9JP7bjXqMIZbh96i56dnLA6E VCUAcZoMQ5RRMq2+SLN4VDd/G9kV2zvcC+FiT7sdcRzpPmaPCtVDb5krS6H5L1tdXuuDz0hiQJjO J28KWXh1m1cyzoedSvjZjs9JFGc6JIeGVXECOaFLddmfHk1p3cpam48i7b8M6e96qXS+8BLENXfm /qOg7d+JJsXLCQ8Af1ZXpcmz263pVdN0UqF4REEZVeBGLe4rkN9WPuNedO364kMpv9KiwBke1X6v 659Xy6u7EDnARQ600/ItP7zGi+EhlUa7wizxtn3wYdnN2NK15jKZQffORYo3v7GqcNHnwd/Jqr2o LWo3kmwytUwBPbomnlDf/swAVOaHP0769LTsR+HzRkUnMsxYbQZLXs3FSpJRIHDI4RrAwSWQArbY JSx0Oc7U6oOKHw5x0BcK9lK79UUrdzpW5lKEQNbCGwywsJc05JFI6Db22zx3BWr01wXvU9rCSkvM VS5bd1mMTqyQMmOLkfZv+zZAjmGDFIiO2zLqYSxWxKcLYWaXgHgdEko/ujyGwDwo5HTTbq3nNheY FnaYH95s05z/7lEtJg5BQwGqBMc3znw9EWtT8EsTKvh29EQJJ4+MWDeFHkP7lCsC2r9Gw0kvk8yY jucoagwHK4cZZui9vTZDPcO4ZzPL2jaxvYrydDmmK8s8v8HP958/bjuUfiii5QEWToWEYjt/KXvg w2mLQhk4LaDojLuEqeuQvugm7DtorHsNwFNE4wMeZ5HTsxR8Wcl1fbz2Nt+O4o0XmrTwQZlhmBrP S+2NidfLqCx3PccBtE7CgFtAlftB95L/meDShXKAQYPbltZPev71nI5USeT9OE7Ml5jP1s2VispT gUwQ0m6NRcG9xo2fcp5r7Mn+YfrH9Hnq/wIdilfaJTICUfIl6h1x5MmNKuF1Y9gm1ArYlx+Zw68Y vbQ2dhCcPvCAIJobN2aDNVMXBUy3Fe0BQSznCysthvYin+YU6LNIFYZeXXYy9L3Qj71o1LzdlHik lRRU9LT0qsHp2Ftclf8db80Wks/je105O2/uRjVGR0oz+qkg6bJJqKoX8cBaqV/Z1GZ/UExZnYhP 0vVt52BAa+1np/WdIc/oYhukoxy/i0F4G2u2ro1QiRnLjrcE7RVMWkJurK3MjZnwcQjqJHpkZnQT cwUEgRSjLZPQ9EKYkA/5seM6m2lwYW94H71PH9DMDrdAnCvuZ4CnTeS8QHfYWfQcouscNm3wtJNe 79C8xKahRP5lXQnN/i5teikNz3Xjki9skCpxe/T2FLSqsgxDNImzXaLOIZ7YbydezeJkeketpmcS 1jRwOyjSacjdp2JlgvNicvl8US1erJWS/+0veYG6PDOvRmSF8nRKqRNlkrnyI3JD2/GmewbzV4v4 t0HKIdk1VOGvWBjdxXzbt396vnE75gKDwQpd8nnt/YmeT+KCANpXDyvun4nU2LwMe0X0przTBM3I v9J1VlZZVNmD3wm1RS4kj/+T9gMGMQuQVnr8T+fhuvx6T0FKayCsIfZlKIAtBh1hTJJUCsM9N8yg sdJKtYC2ZangqSUdy+D/D8D5yEvJ/kjVcIxw1gxABYzDpBw9Pn7Xfvva67NyefE1urHm8++QoEC9 OuJ98lzacv6pUg5ESbQ0n8HVZ+9zyVwc8IDnicW7CH4XUMvoqOAr8OXkZdZftJm6n81BmarnnnNM d1LkOcRwytPMw4QxhBMPBoKWZr3PMN8QOl6hpTGkfYM8HCX1qONbWIJZQ44/5AshnrzH5q/1TXAX 6AjJQa5Z3BeMG5BqzSjCLZM3d4hO+wxVXFLbwE6ZfNqtYmEhWiyveF7aSdQURRgkfJsJhvK2xiiN VLoEWrW8S15gMmf7yXfi1LNwMe7Yn5nbQGhC5ov8yxdIJdln8PF5yXeeRm8i3xvVYJWbgPThkv7q WKQ7gBRKOws8LoKXQh02d4+wG+0JkOOaeXZooTgvbbmHUgvZZWM+jF7YDLCTHXqNyRp+dMG8/bmz wjArAeBBiFQDYnyZ4d6kPfunJO1KnJYllG1JxVhs0zvpmQVD4Fh5JUHuyRsbV6/ZHLARhlYYk2zB z1aW9XhZA3mww83z9NfnHJ9TPlC7l/GfPvtdWOjp2FKViu51FXhcM8EPKiHlMvGOB3zK5NJvY7cz n59fG9jbTB23NoN8dbaOOauvviRdZhGUifoyByPz3yrYqSbpqOs2PLSOLdKh8UcrbHuFoaeWQPX0 yXMltuUpb/YiEeaYdKLe6amr1+dzYOMFAObbnXsQSjwQme1c6XD3JsUTmPfpVnqCzmFPchxtuS8F aB6Eom9MI1MNzOQGbaW36vNyXXKnU05wCKM3L/Maet+SOJuS856qxCqh5uzbf9yo+iUpnCOfxbvr FgoI3tUiOcHuSeN4qnBqZyAFkuw6urRvhAq+ZZsTLstTaDl7txw1x/jCOuU0zOZEZbE1x9fHve+5 eG+q5UO7oHUoKAfHOYAiD+9JgTSxGoc5ITAqexe5Yf84Ba1IePYunbkUWc7rg80wdhSYLKfA2mMi kYoeUcENgXC8dgiKNTPgrdOd8cWVNGPv3DIXTeK39lTWCUSaQBJg9YfQMHvK5Lrj+8dU7ATMhoIE hnlLyUVJWG9fJ/bHvE95QgmmDPJ64k44UnnzIsNcu4U4iAdEq3Q4aoXKYDNdF4wA2EfOO0JhdYlm wWRg0842Cqqup3xOKb4gQUcxOou1cD1gSOHg9k6awoVLGEjuFuSyhh8dT88+0bzdWzY4bPdACdzm jfP7lhU3M2AhVX+4oa8etmNPLU3GhvRscdnyOORH8UURdJ/d7bzLPfxNs8dY87yB5Lm1+InFO/eD cZVtpT/BB9U7+7VqyUQHaZ2G1i9TKREjrdywJVXUj2Z29U/0FdAz5bxg2Gw7vz9LOIoi76YUIO2F JnKuqalKNIbWeqwMFgTGN6XSj1rgW/Png72HgPLIuFPTEQYjr6ZXcra06WIBBN7Wm9IkL5C3LsgJ rxHqds9R80qht7sahxwmdgvXO2Y+nqMDsM/5n91Ss8Aa2Bat/WwX8PjoBtO6wJNluLwjU+zPWjUj 4wOKacyW8Hm/CqhUILlrH1eRSFMKD1rr2Cu54OkhPva2LSC4i/v8xjFHJ/+iM64nlknNpQ/KJlzj erT8eLjoZRNk/sRRdE6eo8U9PxweROA4vrian6q5LXK0AShsjlgPg1g8sAd2t7+7jJmuviksJ775 icvgB9j9v2YT4IkX2wpIfp27UJL0bkG7PQeoDwrU8wPYFJoMXB1Kk5Mm4SmQGOHwFCSYcCuJyTwY pF9rHQHzaMSb3SijM90YK5n629V9KM2JBEMvwQjvgX2khwZ6pib5xJM4QJkfDSqFG6Q9Wj0WdPs3 4DZqfsWH9ibiwyGvIXD+ODLQ6U5zV8GWP+WyDfwYItxu6/Biwco67nEQj0ay3CklbyzhzuECz2pa Umz2ZEbhtKpiVEsjAjK1njPXjwC8gYhmaXuHTZCDKPnJSy0HJhQVaxqUKqniDMTxssLwl39s2AzQ V3oiQMolR7XrXkL5bcKHTEZmj4Vb2a9p6wNryGNJWB32vJh52inlixkHdYrZklrzJWJdt+O4gaLb HpCgUA4I9dpnJrrRMa7h26VsSmQe1A+BpSI7YyW5tCtgwCAT4p9aJ7Itj/8o+1kWFatugGTAASSw xymyEVBxBp/GmiqaaZ9w1CINnsohvFfOzzTwJXdYhvs/y5/FUMMTmmWiBEP+ZLVTxV+KZ20xQkaM nnMn0WMB8KfhiIZNt/8JsR/dz6yQV+M7VZluhCp/ojWpeoe0egWC1o4M7yhHG67nNges8KO0PpO/ hZJi3nbIl6rRsKNs+LLtl0+CRy+4o7aGIki03oP8OQAlGz6bq4wJuW4gnY5ccvMVx7CVOzQCb9tg GsvNCmrOaeDUA8MEHnpdCzncZA5eco1m2VvoYkkJj9BZXrVoqeWV5Wa+3TrJtNilkgrE0CT6b33t erG/+hjB3M82Jpb21QwbL77F+8F7bxzlTeVZbPrCHIskJhbclz8LsYvCIo1A1tRCRoGbs/4cl/GJ EllCEc5TDh6mpqfkX5Hd6tH6mbJDm0SJzpOCigk9z+Uv6ThFKpECAyCgmJONNnFi0G6VxYdrWnIC b8uA8QakC4dMcrT/2oRXLfSEpa4MdUw2VcYYItGl1agoDR/2NwMAIWHnDscNB4+3hoJXpHrUEidG xBr34uXBUp4aQInVeBT8jFYzw9G6zvlxPvxUzjhPqlL1YCMRiBJ/ntw0selS/dRWYF75WbdIa1VE HYYCKztGgUvW6PUWiL9JGopF1llQu2OjsuH3QuH3FwDdP1IfkO+zHdsAWdntVQqbLVEM5D50bxyp Ns2+WnDwP8WSAOOZsWHEF5AjMPSrFYZdjPYbL958hlgduHOgsdcYgD3PA55/Vu5FWVzDIYc4fgho fbVzRXaKS/eSr1DRQENwG4FYXOidd4vrpX1gmxX1aRN2MEOS//RSqX8V40LvLm/6QZhZkz73fCOM SJzMUegen77rKr3AruT3/uF+v2faqQhX6nReRFe0aDVNgMjhxaBS2m6c8Xc4tuCctOcTc90XWm0X VJnAMCvdEUO2IDWPIR/GgMwlpEt5rANJoli2qrjwe1xJ5qn/sSvZtOvMVZxPbEsTf9L2rSb/np0x l2jwO+o8svFTmdMxR6bVGhYTXv1x8D0bLINw7lDGm9TKKkIfzqJTsy5NPHwh45+XwWerJXtA8mi7 RLN98orS36LH42ArVPEpxc6XcdGeJg4B27Efi/3MxZPiOu66socPMCO5RjZrE9F6UI5Ry0ipu8+l LXEK2Xdj6uDK5/I9x6OBgAf3nO2EjOcOSmDbhJ+w4MTnmEB49DxZsK4h/Z53QQ70NPk7R9QhzNnl mb7ZvtcNAeqv0bQz7jYo2nw0VRrKwdnx8hGtC+qIkxjD0igBXBAIVpkNAX3vjdBllyVHS93b65nR 4ZVUgpSuz5m+el2Kp9BPjRGi/eT48anWNO8IKmMSvBLdjRJAe3I3eRaJyhJi2gCNnDDs953WWMHq 3MtrCQNPfLE0NFHCdLPdyk/fE8uWdXloj5znUviv9sv5j2b+XTBqYPp5o+rKFnCOSx31c9QqTRSN nz37K+eIYPhJpqtR9QuO4u7CplEq1JPNh0WokTq2LCBUs9TMW2FARt0tPzQxY89IyG3FCVM92++j fZIYkpeX4A+z8Wkem3Gy8bNC+ABSfEc1C/0pytyIbvilFP4thcIixuiXIl0j+bcciv/mW5uayUZE qY0BPvoi8B4qTEYBgwfezdpOqlJ4M1boLay6lvx33xE9gkKPMIlHHxNBE0N7JJ6ULR/st/ivEHmM FMJThzCPPIeQMMo1jqEjKX9C5INkZu96GO7dVKyWpUm32dRpNu1mJd7p5AeEIM5k9qsNkbGHRnn3 ydUidzBjU7GpUamcZ3aMWBNry7xYdKiYgEG7n84PI0XYSGAFWwgMO9uDItX2NAJ+wtw6Rtnwy4q5 jKgFlVL5k9QgCYij9XVrHgxEapHYfuETutwlTSElas4ILQoFXsk7qMjAj07Qjs5mWOmTmevX2wG6 9qpb5jr5sHxp85BJ/XZnM13rFYvb6DS0Fx79EXKd/vXkPwgrmT0t8XW0HjrZsmM5UBwN0csrGEDV fqWVowReFqXTzAAa391toUg2yKaF0bVbdVAgrDs6YKEHLir17ZGr1uEdmsyBSqLpIWAqhDlgjl2x p/5XWlF5Hk0XJRY+uwM6rCt1YVQKnh0iQ22YyyXJ4jAx2sGAlB65TRM4sn63xtunN6jvhbPJYyvl hLnCoWazVaFzOWmA3k8HXy1uK5ypWytne2fwux0PMX8DIsqyCidkL8xbV/4e09P8+RY/yqYXGlCE He66DwO4ssER0L7hDkwLREQtFzLqWwQfuHjV2mc7RKMfa3qADWS1KCi3qRRmPN4ugY8cIiSZRbs3 0auSguwc8QWLrF6/RaxHIw+TN6T9JjDLJ/kqhgo9TYbbBZGYOt46u6GwjYAJVTKf1otNEXvrhTfl mKGV8IQobeM4NSAJJVdNFkeYAl9OpdXL+lZniM0RwonD5I8AaDovDXEv0Cl55ko2LukOV9UF2K1z kj38wWeDPbqDyj4uzd1JJrVntuBW5rivg8XSGg5tp5NluDSetYLAWAuumYevW2qzsIH6MCIsZeJP grAb8zj32U5a/F8CvjtUg6LdqvyIbi7L5tulyMQhQ38zFOj8h8w4YYVdXH0EFv2g26lFP/SxToi0 I3BS9cvWyZtHA05kTE/xEj9v9fW+EmBZ0jovNFFhpdGZNxNSUSmjC3dLhZQ/+yRL5gQoxRM+nSUi qwWYn2D6MQKQrP6y3jnzzc0bXz7loIi6DGb8jMSWHBDl2BGyat6OYq2zj2nDZO0yaHWUgeTI8KQ5 afHaA887WSfvZDQtRtSg+DDjgKFC1LSZC2f81/z659030mUD/FlAeRFEot4d386npVoFJ+XC3ZOB NrfiygylxaWFaE/qiaq2RTbxNxl6o2PScJO+KcKvVaUtwTV6LgzUWFRPC5Jx2mGaqVNXSZp4/J25 7tUDWcs1oRgnYe2Epj33Gk3owIX9nXhwYQRIXS4K6dwkqn9Q3xrHeOZRd7Ga+58hZDnSmUwYFMd+ FP8jf+X24xT7azGBCj24IZzPh5T4ta9PoAz2cVRbtUgCJYbkufP96hTQ+pK5l5FqwMhzG7LqTvRY P9U4L3vG1Kye6yzYHGhpRkeudW9yKeeCS+F115UT2h8KkuLIhOe0XgOvTOwE1vtRMB9RBYzvD0jG cnxHZYs4BqiF8WvG0LSPSm8YylLq6uN4KUxYU9aNk8ZF14f2HIvfwN8r4K67VF//SJeq5snf8X26 2nJaUFaOY+xwGoT++kuR4Qnq5YVwhExGI3/DDNgRDtCrExJrtC/Xvo24Twrv+VbOabR9wyUiQjmX anW1PVrIVG9TFst/IGlMZCkfuQEhk7DauDmikLLZuZErrXh7ee7agJ1LPhTrqLBQLKRCAzcKFbse G15USTPJgNimy8SpL4sTD+NpHC1zrpRY77bpTLprlOEuDiqe2BuYtgCVAsabVh51Aj104FOywsRK uGja7LHIZewoC1wDSupVlVeN5s7cuah2EebA9DmCdHX1uvvUXsp6WfKOI4gn2ZjzJaz87JddfNwr VbSxJ9Hx5oN1OvXGtfYoRNDttlcoJJDOxlA/n323s10gIi6QSYgmkhISyXy9HuKLqduEtNN3b+6G bZtsqXR9GC4NqQMgojwubICG0wyZoOSxyda0yg2HkgiXtAq1TKOXcQytsj3PMOQnEr0G9nFj56CT J3T6gC9Ewqemvn8If18HB/SGCMHvZtGXZtRTvDM65kbURBdrpRS7dIPB/b/DDpCHm+0Vr0VOwsqX NcQgxufZSSxef5HGsHBhyBSzX+bdPHp3NONSTaPF9zyi4CasCFaJW2oPwIlFVDxadjDn0tNEGFah 637lWZpCbWg9NWOD5k4zPPD/E8+7U+rPbidsFyH7epwBtgVqVegj4K/uX3eZ44Yx9cGfh/Oi4gxW DFaioFh7RFgPjwpoQ51UAGjyXoGDYacPlWd444Fi/crkbHPVoDfKf3GZWaq2KrbzK4kEbZ4yqEOu tLsE7v3KvpHnlLsdBMEy7kUjGCk/NzSc305m4Ps3ab8pJrrgeGdpM8tS2tNkT5nHuqDrhB/mWjqC ZUIVG94f9ivnWo1lSupQyjuzrx84p0y/s+y9/Y2hkbwP8uoV0DOWd3iLo8DmcXe4xTEZcBruxxwx fLqVmGRYPzKkG8K3zNJH+aorDIgcfmQ2b2u5EnxLl9LeJ0Rx+/iYTQZxlWAIQCP4xTeM5NHRncYN Qkh55nSAQDP2bPXTxUh99CbE4bF084U5zWHOR0/BaxtV8L/7ddOrkfEuj//vHcu4JkNwc5bHhgLF q4n2MJU7SOOa+ZnAjVO/ekXYkH7aGxuZVfNuqNlxVTeSR1eRkkD2ijTXXkD44p0bQ8naRciKGI1X IFYJ7JC9oBNjEWxISXJSxzG/c22WdjPL4oCZXa4t2bB9Fi05eiBN+11MS/yPUq5/1xcjPX7DPEB7 V/jv9/Aqb1bhO29EZWkaSoN9Yg7koDzKZh+PL1d2DXm2MQqj9Tl2LzZkUFR/507EbBrDDEszoPbz GF+1itJO9x1xM5opU+uvwrc5tv318ObyaO/pl3cvBQvnNYy06n3/VA0W7oYPn5Q1rqbSEoC1P/x8 xNYCxtJG41O6jYhIhZ2Q0/FKOgbIVGwtxWl4G7GPi99nH+Jk3o96r2vBfZHAQxpu6mEkpiMMWIqZ aqkiwQREB8L7qOhxh9fYAM7xrHlD7dSHLPvn0VYOY3B45AqvFyDKuq7yJGgsUP1UmZXNDxpxwSSL RARXs+vBHgefZYOxYeMLdLedbW5gGcT/fiBBJw9BRiBBJawkfPTlimF508hJDcdTA5rzoL0A6Wl2 HNTE2G2VaCEwMqAoHGige41Y1FRsTknJJPZzTS8fbz5DH7FjPxydwArBSV+LtANV6tqt34tjI7vi sbyz9jlvc9sHNKsrYx5EuzRkfFzWHL50WNudO/JTDLUeWfZ9oD57u8vLC+8icT9EGx6iwm5BumuZ 1Sz3wsGWoMfp1khCbxeIDLBK7ZG0oS3XtBYBEMsbMvyuiDVekF2uWvsGY48w+vjEimQCBmftscGC Nb8BYmHPWf8a5PhE7rN97USQ+UZETqYhaqxypadqZ1LCE5uoFayXjDvY3sRP/6J3IGqwayPyy5NR X2hWVjqUfVXYThacBN6fK8K6Opma+rSpKfWK2HYLaCZ1gpEaWhDDLnfeEdpSPlq3K5QIBELe7r5Y krkT82lEWZDbpikNhOBqu0GV1GMKF42uVkOBQOELk/7MaXVItH0xdh3rL8XL9FKsJwil25Gcpe5x NQ6Eev2BEadJa/k3NIcIiJbqpcAMqwwntgyyskZNFGBBEFd2ZZcQVdB7UJoH85FlGHKGjtfYPy2D 3vMU/4DE3p0wDzGTzJa4hRizKAOCA9qpF7S+FzSx4cF0YMfwDIsB/ntNxH8fP1McgJ0oyyUDv8mF FbMfB/5mRRdoe+N+K9mm+pchxcVE+lRrKsWKHvuSNuBaHjHRQimXnx0ExUu9fVdVYUg0qt2dDzUH 2dEggq290TM0GGoNnz0DXgZHvD0NZloXaJfnfmnjOwqI7NLyAn8ObppiJDSqx91kQ68A0LgxqmUP Q6o0MTsuffjl++EbnZC9ZlhhCNngvZjt0IRhk6jDsWsEQGA+q9+BsGb9smO9AkL4NPuOXVm64oFB Oy/bIP/+2/YG+dhTW+ExFIMKHCb8ZEMofor0G08DzwXNuCsWL1OpbAz7tAWESKAnVTi7/kApyA2m eMj1Z44a6UjxEYnqZOlfxi6qt/cmddh5N0NVJmv/CPvJU/iv6XiQ1xPmsaHfEpwZzIYl2pwhj/Vk OmxfgI+bpMl8Thf2ZorWUt3uNy7UyMsKW/bmqu2GF/rqFGgBFUhwdOkAmW4nxUGcO4QGZpE4w5aM dajGt+fEki8GgfKwDHj7raQi71s5m1r5LZMBXEkbdQBKgVpbhiqMTbf127ETDHGlbAxYpgIbVNT7 Ah1A5cOuOX99VDUXVBap6NJVa0XXNBPdstRd5VtgMyVqVvFBoIZyLdEO5up8HkMVpAGPpJcp+41A rMbpjULe9wIo8Z2fBB76Ms32j6iiPpgPG/5S8Nh3Dk3IVPS99y3O1emwHCXovgrF6AJtfH/wT2T8 a3S/SE3LkQSg6q8/qEvDZp8/hP3vShfYhqxYbu+2+ThoshFlep5Bb73ucID3fChuL3cZNYPGNiAa kD3xhfLGRETQ2rEfbhCFjx8FO4Xub9WBRvWDyzEL0pm0SZF0ZMbagpJcaXCxnqxsCnkAJeUHzV5G FodlN4vze1g7YQH6CewuUxlmJ0Bbodo2EiBeeYoQzqBv00HvQpebTOuCmMua+7FHfsW2ot8lXViy KKVVGJ4FPPYcgjd5e6+bRNi5FoJfKuLNoElTUdRUtQ9sOCKDH6o3l6Mmr2Qoe5TrMfyU3eoXwJ18 wdT3maqV7BLQQHPNmSwaOHMU+HMBSr7uDcpu92z0tRPOz9FMNrL74OdKOfv+r1w0Aq/LBRmVHvN6 DsFjOrjyGKER7wT3GI7lz4VBV0PDBtuXYsb85AMbmcBiL03SpPLzT8D5I1v+/71ucw41Xav0wFwq hN7KihvY7U+4f79s+e7nfhFYZIxphxcB9lbEW9ndht/rMZZbBExoEe3B/aCTEfc9UH6N70odxELZ 8TgpxZg/VriOU2aCb6EZuJY6yoHMhcr7k5O3B4Ac5KKthRdTxjT8ahzSoZOcwMGp3YPE46vaV+PR KyoR1/6z6Jf9ZPZK/0wgOZq8oW/BYqV+5up6VfkK+K2dVf1zfRsqigQ5AauDhxoJ9qwKaNPuJZL9 FI39wMbZhRzaF4+Tr+gRYWzRwV16TYbdF0U+itI/pdtaYDV2gcvTI2nu4lhnKlLZmH/6507c7H+y J1QqALETaqrTHNdPLanBNdtc9OW5ky/+y7pczbzUpiDI/lAyQnT0CDwUESDzKyJAq1qJVIPTfHse qADH+b86XUsqE2IUcYXygPTRu8yUPi00eQ3R5MwJTfcv5IOltDRFaSUcJeYr4uzDD7VwBGeQfVOM DyqhDmhBDzVWmOL4aCORvB9uY2/BO1K8b3O991+ZlymrUSx2RSiLwPaiStp8KsG1yFHXZ+faKxe6 VuaL/oFCQdc/NCIruvmgVFBGPtAT//XbA4um77M7x57hmb8jv+dYI0IEMQJMd4dG+Q/sCY0rj9Na miA8GyN2k2vLcNgXdbCDPd5MJiotSmwQzC4J/5nX8p/S/f6ARRRB+x01dsnZ8MaZ0Cmjw+XGmWmH G6CxC9vEflEq1GSSgDNVQyEw/dBWEZkn+FW1+Ct1RaOzAIIm4orBueg6smDdkmXg47XL0iTHB5E4 djcfhIvG5yrEFQuF737AFrt0uDEgwtU56AuECRcl7IgTixFw9hZr9ooAXq4EgZHF8Ku0RxJRZP+H NqzObXUN3X+Q4AZ4gyCorpLf3dlWV5D6CdxL44hsJaiHaWtavKM3Mruz6uuptOmlUo0HYu5vEyXQ BkTNSFpIk0ozU85Y5YvdaQGwV1e0ioDC0vNHyvrQannhgo7HNq4mFHUQnqmqb/+4kD4Hezd6DDAs bw+XdEy7YD4S2D5mN1h9+WMhHwPUUSzWhtgiSNBFcITa41jtuJB7+mSGGaWgt4tf40+6paYr37Fi ALTABB0bMiYIAFx+cN2lYT2RDJ4PxRsMXKWf3TZVdOowS9fFbQ1l8Cpr4j+8Khg6E/EwNTGcnlb5 c6oPvzvOqraNv9G4tQW03GYjPJUVjbH4WQYIh5DSSeaHY7FRRNHvzoKiZrKaUZvqEbVPMoK7v+/4 wNwyDQRsKMvOUApRu5VAgYtwiXYxY2ffIG1qmUgqvNgqM9YwzkLWVYbOvFyhKXJleX3/35aUhGI9 AtL+DpJa6w6AeOXQBuBIc7UwwCwSNqdmef4xsIb7kHQKVEuJNlFeyuDRn8TJunIHxXqnxJO1oE7x 33xiV3yG3Wh+oXTqzr6H+rXq3Lo82MfuOVEqnUs/suYclNl5p46+rrmDESFHrSa2Nbdix5N/8fwl uG8uwXbs3jcppmHbX7XcZGfbJZsH2841DiOJJw8T+f5mdfVNTsrjY6ybnnY2sDZEeeVr3AyEPCWK 5jQPB/Ll36uX/Ee6NLRodnYGH42go3/Aii77WUKKzI0pqLM5h1wDM+iDt88MzHb5MyQ0EN7Lk3SF j+xB0QDyZDl1gM5YCcoIACXK3A+tZiu448zXIkk/nS73Gs9AkIYI5sV6LAnBWp2FWnXqFhviXQtb uSCKmoKzKixhKr1rT6PalKD+6FFpDq5pcuwxdVDVyn10C7XL6iF1Dh1uJpriq0maZVOZKz7/PIMq GfE9H4JEN2ri+FFZGliyQkK2QQDGAmZcKTunpQdCjaIhavQ7eU8qv02mvXYO3PBQcn/5HUd2BBJi G0MB2qr6e6IWFlb33BwDJpMU0rMiJ0z1hpfGqR51TaF3jdC3xaikSJRyDTXOqB71IXxokm+WN1Fm 8nV+Yc7JPxgc4+KC4ZJRjDq4yPrdBJkbd994tC3//IJvwqLmz4WxcP2VBrB+ltEqgs8+8M3fMgtb TFS7qR46RGYeS9nIL+UBUHGaoMDZuyIQQ3FqhV1X9Y0tQrB5YVul9Xo5HGwbHcYfIbqNhKLNmQK0 5TayWhLHzsYtD/ATtXzxbILvetk+ijUSPuniN7RS7UPtpaUiz5t0dwyh9l47C7mcdlK9GCDl06D2 LgdOu4cUH6R7fA+H0cy/dWUpSh2REojqzWnNgdiiJg9A4FRrwy1uHSKnqsLzCwV3qk9AL98xzG2X qDh63mCnmA3svjUd0NRa83NYKKKR9egl/WiF39v9D5yYD7pKHajNwABgP4T4jIOcX66fp1yhB2X8 pcL7qqYa2UslB4lwZC2kuMiy+Vr6Gd+nRqc0RaqPbyrz4VXxG7IWI2F0Y1uwQfpcCBHyYRVVufOi 7Z4+YJuMovyT0cpJ7Nh7BfpxpRxU/jwG+pujq9yQsF0qZevWuXiYeV7ZdjNpXBiMTQ1LX85GLjmp QgFK0ztNnEj2pPBhkK/rjY7jdQeeN5tvcwfi7JCnBJ6SzVmy6BKLbQn4XXHAd+I9brSjXsGqNwJn QUq86yamAJJiHmsPh2avLZRHaIzhbt6TXRULqq1PJAmP1NP2t1r6g8dXQxSHKrRVjmTP/J39AVyw PA4PgnGi7Qgbg1j1Jc8Fn9nA93EolYLINjwbvubcTM5WsJdP7bP7cuutkF/zOV2purpbdl95HhMn BZrFzWdRt76r+NCUGvf4iGdfcEf/h2Cvm81/u6avGLphQuThzW8vvmroZPEfw6mjRcuSejUX3Lw6 74HI3Ny79Tc2VL/dJ17DRGyarQQt7EvwEGJfFH7tvyF0FDDHHQVygs0Ul+PEijvAkhj3Pfs9ZyhB AW074WvB2idVix6QObKjLPnMeXiyLhxcNcQauDisvpQNh5MCJZ9zm4c0xsnb0WdT6OMaqWP5Xnst ALYUmdCZljv+kI+vdgeCVhGsdEQtmEXS+bRlPE8h6PTNnr2KOAT8s6wAwUhzgI6vvnWL3A1H6Rqe 6u+i5MlkNxHP008qrJfR+ZWFJy2Z9wfs8s0S9WNpEjVXopG6UVGMgA4fJuRvs/8o3IRjGvGPU2Bd NTe/PQpq5QWza6cPpRPRMgRJ6PA93NuMbwsMt7oThQt1a7jc+h1wEdsMjupTJurqJ2Zdr/S6lmgR v971YTpICOSJvZ9L/PTzfFKQ8BjD9cn03ZdIYeWp8AEB/Qv68pKF6qhnOVBIErDqXcb89+0We/7D /dSRNbK8Qw8Cw76cQ9B2xSo9MiiCXA5Cvu/HwICNupHfhAkB+98OvhOrhy1F90c5eLwYAw8Hbf/R mvoavMY71MYNHNLeMKB39vny0gNw+U+FTmwuid30xpJy5ox44XvWycOSHCjeVVNfOAYa2/R4mzah Tw90dxTQa0Suyi1pbKYAnTtmYkpvg7QzhZzVAZF6KAuHiVYYw6bjuQdNorWODYwqhh1/8fPSM1o6 TD1YqBqvhCJCzRIIsDSs4FbHXwoJeZocW0pTYaQotGmLbWZHrDMRfyEnUD+dXmnEAkf+acaraNa6 DvZqzS52pwyem5rfZR6q1n8NxklPjSbb7KOiCmW+0Hw7djd5oW8fhMJdihxKpbQdXp8gN0eGI0VN 6u+4h9wtqArctFQ158NbedbXGjzTMdFSi1SM+i64J9NzQsWYIqwppxV/1pixLYfnt2sHUegHOS6j cctHfly5D72HC1YmWjPXs07QxpCfdEHZu+EfU3jym8XMXgYvGfeoRE7OO29u6xVzUAxu3yfxuTRu sSalRMjTTEoiDymAbOHmCV/bMsURVhrid5PPRMdcgqEoVN06B3vcf2VnkC8GZhQXMBbNnoi2StcE yfa00YimSxQdASHCcsqbRDMHIAP72QoSoLeH6xIO6q6McKX1Yo3ea9k/b1LKRpfuBHkwCoIVk2l3 2I6WDeiE86MbGwCpxKrD0fKCIrdQrX81aet2KIuF3K7YkgvIlHLpHO5BFvj94JkrkGHgK3jE1Ivb ennQZj/iJ84nn7pbrpFpz5Ou66eWxz7LQ5zPUPPMxs5vHPP+YPrWy3YVzoaolzLT7W5x+iDU9w6c kdxV1iHEuckdnRE7y+DsmVgfk40fS7cgDYpXt3FQYX4bVP5UystqCExcs7TQD6iD/Ct1iHFx2NQb 51iBtJYZfliosMqPaa3VfxCLe3QxIulSOar+IUeA0uI6kHSWhP9JjRFyVeEt0P17ZIGR8NObHp4L CGMWIh0WfV9rATji8PuJXVNaor3NWmgb2hjXNXB2BpTVTiu9G5Vz8d808FYsHv7fl/mU9+B+xzfn ldKY/Vybh1u6ZJRcJgK8nhAanjySwlYtEz45nUVZOGai/SAAyzPV3nbKwvYuVQvzgaLGYMO0pPbF 5Ss2Ib3EVuuu0gQC0NRmUIisI4cWjo4cwBhkfGjGV7C9nC3ALxx22AWacfRcZx+vAiGvTHBP9sah VuHSaU3ar15ABbhRATb6rmN3567hKHuyQFIh5w9wQ8zRs/FZBP8MTu+2uL3bCR7w55qCvXACmPcI 1gP5ilN5zKvTHXOGiiXmFg+rJhlxPhfRpohjNs3D2umg0MMKYvFCAx2D04YjXcMmB1k1Qg5IilbB i4nfdMHZyGRW/5iOfxP0b48/BoFH5FtHxP7l1a2TbIDerQLIKy2iQdPYSRQyiaGuMqbfbvB1qMzD rc7iqzosIGTJRTKZoSXpvisNwnw7LQMAGiD+ggPP196FjsKRi903QnIMCcJuusL7vmk2s+y48VCB 6YSPhPww3MjBjWMHapxLuWM4Hn7yGpG7xzRkWS9AJdEyLiBgKfnkCo9S9hr23qwQQRwYTXwZOYKB 24r0Swlqf+k/C4xepzIF4W973z1QKe8OBOHYP2RHBmHzPIdujZYeBALtwfUwYt+8uQV362pPc50E ipNov70XQDMEqb3nOCwBxzJFziLRh/1lhvnM3yx2J0tp1JLJwj7jsexMAT3+EHp4REg+x7B6VGTd sXVFlhCd8gUVhvkBuc4OF8LdsHcAF43AGhgu6AJxko2oUrAKFJXddCOJeuLHqISr3UnX2+mZLQR+ VmfjsTK1kposj7wZAr6k23itBYzQibGQn/DfFWSxSuv9+jzMkhGGuec0Pi+ZB4tQ7gyZ6bivx3m3 laR3EOOpEsflFektZsmwbgDEx2FS3hhTTx3wX1k9x1ltxuqTK8C9MZxpl9NlKA3enEOikTQ0JCh4 242+8CoNiI3+Gl7BzpJ7LE5pHmGVKz3oq6vHN9p7xS62/Dn+bboC1VI9bvNw/1EHUeemcz8GalFd k5TnLRcyktraKrxPnRzG+4UzVujIsw9RyH03/0C2SETjrq46aMOtYoiCaV5kkl22wmF/oAah2gnQ DEDWQeINBR/9AWEkuuZl40bhk78g3uW1LeYAnJ2F81IKbam/YTvdpwZFOSfy6cwE+ry7fsvCKh3O WjEuQ4Nm/EVkfJLaQ2ERpc396+7oPxJd2+CayprS8CRHs8aGTbYUo8lWOfrmbcH4w5E/Uie2/Di+ sUiCXqsXD3hDCqLSMnpscXwUZL5xthVd9GF47H0brUzY+eoe2Nh2ebD4gBRfizEd/NN1VUrV9Ai/ ksTM+qxTkIylAU5DN1WlEsbZqdF7hswJQirdnAbcllBsclugFP2AAmredgd83+6G53G7A6m6RUxS S1pStgu+uKUI0HXtx7l7EPtgGmnooCjjieksHfnH+J0nvxT+CQft9HFyjaRn9PevmVO5/rZNfgtf IJhXF3OtTMUVlCKo6xzMEVqbn2DBFl6Re6bhE621z72IDHAT5thrknUUNbgbkMWNt77yH0z1nrag HLFGkQamqSW1LcUbhBU7aujbz4TCER5ap+5HPqXPj2Ky1Pzgu4coU0n+qxR8AMtgtlDptZTdxLFI wfi+wmPBMpBjKzIlWue1/VJxdBsV69fdrW4WmejzmpttWIdeWbWK0+R9zaNkmcnuU2rjVBwaSxHO OBlxrCZP2Kuej4Dd5VM+9OG/Yu9JVOkPzP4f5LKaayNR72hrYA0dztqXpMXC/9jtHnJJOMhYAL/6 mXHrELQcfQgYebAivCJ/oWTsnD03lomzzgMff7YrTcZJZPb9GCf4aSbpbTwGao4SCZptYdjl18DG 8mBBaFxHnxaRkrj3F85hdpjl/+l44dlR6wnUZMXc3kLoUbahMHT/tExm9a5fjeQREdW0Slnhp0Um IpQCLBKIdFOI6eMD+4usRG94YNKSRntMaR7SaJ70j87D0WNEw51P+Wwid7yD2gs1xQEid4CmviYq PAyvzkOdO30S8PcIGYt2mFwfsFWMM+SUbinR+Ap8TpHDD6Gs1ajbYDmxC1tSER+qG4PkUurr5ICd X6vTIbOd8btfaCxU/PeoQVXUMnrpmfjgynlQuXhynsj4pfz4SG0of9aoSeyzszA4nFEqJavyV6R+ tPnM+LNmH6011oB+0Qxsesl508kp0ptr8cyVJca1yMA3D9BYHGDGqckaVnzQcD+7zSRpwcdE5coV neimt+LSZRpDFQchxHdzOBmI+OYiNOZVJOllNo/KfXd727+4bznjFGXKXrMbSdCm8GajNAP1kdER 4AQRH7oNJRTWTRGI+KxCfoDO04lEGptb6rgUGe3/11MZeOMx5Bx+hKXFK4SQ/ajY7j1d5Ne3Uz6z qQ+PEJTNm3H2QALU2zpcQmg0dQMKIkvUBZ4mXDhawpb1MnfT9apACdlTZflXY/B9rOPhndIur7hh DuKfzmtgI8qEOhUb1nGIrR/LT4eMWNcyZpwG0xO8WT/1lsC8yJv/kS7RxpjFgcquBVTtJwzs+pbB uZu4EIak4OhtRZYEZjWwOQ1Z8PkGNg5tR/qfbOaWFEo7LQpYs/OtGS/rNXPNcJzP2B9WcYH5k4ib IQb6Fe6Rp2jddbHY125Vg1WyEqNVh1xWkcVFZ9YSwXVQI+cgtYTeu0CpELd9hYxk1miig0KLj3JO Jt+QdtJWCxoGCRG7msi1/kj10P6RxqfLPX9a9N59xMjSI0tJd6ZGOT4TPj39TLoY+rZjagxgc2rX ro5aNEP4+dNbaR2qVZ8HZiq/YukQM22C6h6JACo/JaE+UyAx0gvwpZk8RonviwugzGOaYtRiN7zS 3uch25Tv4SuxJmu0PcmpaihKXZ5JRefe4sJqxbrJu4dCwjmxu+qfJ4JR2ao0Lb4XLSeBgE5Tp4rz Bo3beVeY3kGd6/rb6lFhsXTOLujblFGhBBo93SEAEEZ10xO+sdnljQVbk/HVcR2ICGQiK1MtrDFR RgQbsV04I7UaOupdWivHGEhp9peYJ93esib0pYjfuDw3G1SglbRTCEqZ/suIklTAmonNH3BCvQpK uAIZhJRuzf2M0bkgbGzm7gYqqppyZPL0dTCz/awb93FPwOLhOVqOU6YmcZTfUXZYlIXk4dJc5f/Q M05sDS6C03gPofD5+8aaN9Hk0rXAufj3szoeXlaWdNIJ8LhJnDSc5MNRJYNv66ij/KDNjRlkpp64 Dq0em3abAFPLmRpk8OzmO0MPYzbYICjJ8czlLhuvpEIsLevutNe4kZ0cXD+OqbZ/E1J5aGTcRmz3 +1LA+xQnuEOsxkLvJdLRNq2VJkEBSVE6EzOTIvdDWlavtYkYpdmeHp/wjkN53q/xT8UeCnIJaIPx PqdMKQhbQmSHva9L8J582kvSf8eqxKoxTvhYpuI2Zdkx4f3eTRanrjTNp/yXEv719JtJ5gIyJPNb xcbvg3yigiUboMRMXRPQzbZ4lLKdUaV2whIXTjsWqm+zEL16Kudy0A6NnG/upVMo2QGKH703H+Gc Vwtm2vaVC9VqbMwi6pqcxTsF+FZ/4nyLB5RTAl5NRP/TSYQzOXD1uo2Dg/3UJXLMD9I3w98VpNl4 EZ0dDU/E//cxDB0PEowozV15H/0kCrq9WKE1g6RiMpbVCXQNQ0qxvZmHhyW6e+NEo6neYQp8r6Ls DBOgXL3btYyhn5TWEowiIamnTonT4JiHuStZf6F6zyRy+qmqVrW9858hzrCTDSS3snD+g4iJ/ade pab7jV1wa6etdIheuEsOlXg7kCADP9BdZvwKz8txmrFrXfZ88MLZkk+1yehmN4wUQ6yq7M0zLc1T TtQ5V12JJR6bziRWtUf0VmedeKDUBVfXSeyyt+GbUPSUoVEfMP4ythDPsi7KJ+dIlcW1XBEt793m aPaIxM30MGXgFl1ljb9z6eQlXog8B0UU5fENqmGIvO3qvTcKDoyA60L7p7fa9ff7WgipvzDZwL1Z kP77WY7AGx4lGsRJZ8HfkOU12p3ToXnbm3XkR/dRqrfwbFv5pU01srJnRBhumo3uzrLYnkJgJbiB HxFVHcnZfUvUtFYUEGDwKfwWhAVyPnW9a5YNiBcTIqhLxyPriuJXTTlC7PDF10l61CLmERzD2sgt V+V276eGoeau8H8nRbOvxCrk1HBAKEkeds2QH+cijLLQTMW8gg698rtbwYMvHFBfoONHpOdeKOnK 1au033FxPHNuxHkuQdoHP3guzEY7V3UVctUegAulxgGn7CV7gz/KQYTYvAbZxIRhQkW11R9u+1Rp aZ75fx4J6X1OOuhqmwWnQpg9b/0YMUSJ0OSsYbS+BT3Ifj0WrK3zK8cZDnfTwyS7tstXLuBzsdRp 6WNBwsvMy4fgDOlFk96gQ9QC4JnAuP0kufGw7RtMFwRTZvqSX2geOORzfIdgabMjcvVl+LTcU3Zh v/RFMc2qDR5Nvntc1fU1hCid5+XMypXVo5TIonuWPZAX2xkjPfNZ4IO/9MUhntpLrmqUEVd2C4Ep pYqVov5N6A0kMW2ZkVUo1NkhOM9Nmdgy3o5LDReyCBzFmMqsJmU24oyIKs0OCKxpHoKRuDbYumxn eqDWDFtry6Zy/WIwpj1ubhSxX3mOUKjrdyNFEZ2fUQgZ+MlKueIFs8Fm2fctiH9BaVOUlhFAh2Lu ugtUscUyy9DiaVptjgNd0fCj4Jj47v7KD2HJ+oDiPoJG4B2t96voZFUiqhTd/fI6GFOL9Ts4JAc2 xnQVXY8KTBH/LCPUoDbxqZYAhsY+vljxI9uy5qXPfoFaI9LgvaNF2lA17Agda3R9Io/gntxObF5a ISi76eMfYbQEovBY0KiyuzNSNUCwf//bStwlSeNQVdxicXXFjaTFnt5D/C51sxjJ8C6oT51hVqBg oeqnorBC3jXdp2YLdwNW0YuW+S6UHTeMZsC/2a69OgWFhIMNK5K2pXQiBQy7I3IDINOkBUAsu4A+ 8H58WdkfJl4jNdbA+JdPbbwBIYuX8F+HI+5SzEbDQwC2uJ8qNsnL5sQ7erPDfVPG6kG6iVRH6Mjl M2ZpDX3+j98lmWUzj6nipYHATM2OlNbhzgRa9rbpfROb4NQXX4Zv6vz6QVt2cLSgC0ifF8J79lwO /hj31gN17jw8csbyAyhWDO8hS7r/iP4oPT+GaJVAZcUGP6kSSz9mojrS5h8I1AjSRefhhp/DSwLa OrYiEUHKBlkYXc0vO3K61lNAp9FSkVIqXV1CIHZKl57BGe/FR/gSSMD5hdv58+1W9T+3Z0fU9QH4 7Vo5WYX9MOnSwE8zXDMVsLc0q4uvK4au8HW+INTGPbWQNTzVOkM7cEggXWJl/zHTEDU3t8OTahJQ eDwn8it0R5hgwRdB0Ue/oXCHL7Kv6MDXqzPIiqA1byRs6kO0wvLb2nXuua50Z+mwqfoDcipMkUGZ bqbLMIqL97zfhFbLHOwcX3PigWytaI55VOC9RCTls7Ux9mqLyNGfmlBU2vTzsFnTXOHgh0PvBFxM bSSEPvhQ+O13tjoIX1f3t7IzlYPnC51NZQm8rqOF5L5/SUjqA6Rvqaxjsay9idFjOwOASg8itUPl 2vHPu/lVLngLMcqqjCT2zWVJ/0VeKwJWUYhv9S89nfrt63Z53DQhfrtxx2MVIOeHfWDUHLScQgJL VVfRxPbVpxNgQesA5qXjSQfh/ewQ17WFhiqPOQnSc0mzhZpxhgSVkkqBoSIT2zEDugLOp5RLcSaW Ya9YAwK1C81+/M29xzmwk/LQI2HzwMkLlIsoJAezXQpuVtJSXVmlDnEtNTd8LMwZ91hBf2kdjgsj vt/pJHBxbsLMq4hmFbQHFUtmdQM9H0YPgKQsMvI3GsbcXzz3XdUCNpShhOyruf5ispCPYs/swX/V wL4clSAcOiQ0dkrgOvRySK7j5XwS6px0Gmfya7fQXudKGkhI3zwUdNDRdM2D6/izkKRl83cEx3/1 W4ZVyBHRyd1/UT0zSNw3FR2zSSrV4DO5m75fG6ZyWYyNi9AlPDKFTrr+DVDKWuXnqwrOkbF3iAwd N9AOwD5erhNrd8arj3ADfvd0IcKHUk+RlQuK14OyHz7XiHX2GuW9Czoq4TdMQorFsyVJASNWqaVK Lj49R830dnbnlBz/cOx/9m1N7B3Wzrf9Cl/PE5CcSooGisA9wzbVEE5ULKlxD9cO6Md13YbbEEuU H56jgKXd17BRpHYUIfzwGZh1JguJj8MGwTPSzo7d7M5CXl61oGM4mX8zvOWYeTJXqhNUvKbMM0du cMoFLh6zu7x7iN0uT5MLc8iDKvOmmFwr1qGqguZXWX4bf2y83TVWz8DjdxCSCPQCRceK+TNXtq8R AYfiXL0uwT1+vJmQj9fg7YRb1IYU8J/BfE8wDjnHcWnQJ+P3pybNkzPsLqBsb0gHYFEDhbTLdwgx KBTWSISS7cNvgEQ8QAEZdDJF945BjBuE1tVxqh5X+HGEHeOcw/nV/68lEm04M9vNaniFKGrSzDET O3XFrIH51exqoe58gyijJvqPBk6bCVnJfm4NSh1hO6gOn1wti0c/u7e9TLUyBcQc8+PMt2P2ocUA NDq8ZlaxXYucah6EpPzf/+g7d0rADsZqE+NofPqNZINE3TayPjs+UrzdatCMWOouc/6+bO48POfS 7ApPIgdtSN5uIm8qxfWcvVxWCmFgvLr/lnemG8jwSE7IK6XQUwAN+W/60JiY4fJFU2u6GjHrHyUP CRYrFf12JfjI1v3DnvTafFrqLvds/150Eoo+agpstXqJYdB1DPQw2YY7KfwvquxW1ftyZtxmuIVv UtKUJZMs1LcNJFeVBc+M80P+O5Vd9HkK8gy3Z4hweEX+GYpgIsAagxyVD53hwuUgV7uQFjWmhNa7 fYb4Y50QZLw73AubdpiX8p9lhl8VrMiB09MM2ryaX06J6wEFn7oX5zwFKfXJNyHDwMhVCrwbx6Md cq9pVRuP7dXIPcVnCIvXA1XYgaIBZA/CUaP3LwA+yJ5JW5Mmk6696y/szwfNH453dNymKVpqjtaJ tlOooprOqOHL2zbvTJOt+CVt+9GaybyXPolyCKrApJeyiYYmrOvX4AVX9pu4VI/xTCSBNEPZbLaS JpVvTS/c6ZqjR4rR7kWTJrmDVealXAjcVWR5Oj6odyu67n4C90EXMWlxZJGC3/ZEnjg4UnWy2lxH w1f9OTbSK+J7x8mS2jkGghw2lAUFeJ/I8HOlyf10OK3lw0YEhKVWgXRAP4eLf52JoU4UNHzrhCVG 2p39Wd8Q8im/+c5uTGQGgF+KXJzgxbsrRsR8/G6SRpj0dZXH5c4aKnvDjaC84I7MLvx2sEJQobaf si95E6b00FrgK3cXgI29tFHpNx470T0fYLmQyca28WNVUj9RZCmDRYp7Mu1G3wxayzGOTEVy8Rxj Nl07OtaS+gjzGeEJM5+1P5qlJo8/jaR8v7Z4DMW9f/QD03H9Ae6BZqjjRovv1JT6RrYnrUYEXt0G SmRuafKxmW3S863wfh9bHEqy+T9WALaf3Z8i2TsGS6aR2hdKEIH2pCEJcvqgYiCxn/2A21O7f4Rz 3IYOZ2Q64g5lI+PYuc3oyVT2CJZQpKtPLNiQE3cggUuomejfFiV2OAQF06OmHJopsfvAY7yzmFVY Vtl31leOY4HfwAIE1a9MrSka3bPEPZi9MPXmt5DjfV6+rbzDHe3IjJc1fkEleeD/MTNcCWKQtEIE l9BlVeChacLrEe1r7Hbcz9FSId7v7D7QjhwEjzZWyuPn47qN0g3wxdrmDI6JMZQtXmm48svxGLys 2/lj4/lWfi11G1v6QlFQNeoz3v8Is9KUXA5+vEcTYkTVZfO62k8lqyd0YkjshVfdpgutaq+60Jan IbNOhZ4n9u2e7q5MmroTA5FpL4oieZXUIVMHA04Wkg5VWDsvpInlwNj6xJ42PLzg9M7dS717Tu8r IMcSchkmcocY3fk89B4NzuyIK+8VzlqRcvi21JppK3CRjGkxeUH5DpVDIMMNyL3c4furv17N0PO7 jJn++fwMynWLyAy0pXJBEPUB1p/FPQ9rvEC+nJyKeOUndvvQN2i4ed+DlEfUxzC37eODpSWl7jL+ huLiI0jiD9KUXMfK8Fvn1J6gYjrYl/6xlFQxZ5t40kOSawd+tmY81pqZL56XiGeUDbA7DkQiGkNQ bpxJDQEwc/YVIjI6V7jdot55MRyuH03IeIt+ZqFHmjk8cIdlqzmsLkNS47YFa3bG0SS+QGWDwAYB hZgH0b7NnhRzK/zz76Rfo75oogPRuQdm0wZEkXIUQYnMSqsp/y4ZKoZugO81Lvx7nGnTbXQ/UWnm A0Fq/m3SExJog5cfUP+0YNXLJjzcOShzi93KkpRlc+tHgdmn2MztMbGO9/9d3kzaDITS9fv8CZ43 GiO18pYIpzG/OQdUe8nezLDhT0+4YOqJh0P/qUuJA7U1c40kDvzjtAOIEiLUNoKGpy1rlsQNk0ZZ kqsMKXYS13k7iA5FlffNi6j29O/kIjOvlQwD9AwCI4Ld5pbZ1KRaAQwTiIKJuzmAnVq/noua8s5N YF3ku4ZPP7Kwi4BsbPfAV65QKxnINGrg5zCGU3WzqoTX19k1OKHDY3oiFVEiLxvbRq2cIDJMAV10 baLVBbA2M2AdGeGScH/Nbb1G4sxL5kNeKyqF0xFhFEnwXn+rCTi2J4isKfxIZMRWj4Bt6wvPqWiI HhJd322G6Lpyh0cmangnc3IUZhcoQjDj6R0qRGL5B0T5csnzM21pJcxGb4j93bskmZ0ezPU3Xt5x aweki4KSz/2NaoTcOvKQydjVr7QqSvXrvpdpvvvcDHKSR/ejn58ajPhG0Sz4882oR3mA1NFK8+WA iXhP8utqTy5zFXoXn54tGYDNwYKMLdQuA9wbMParopuBd9N6rBLPLYM0VJGHH6HCnjk3a0UvsHTu JZXqmSpgPJtAAN74JoG11vtjZeRk6xmxaSW6C9nAKFqUaPK3TsPN/Sr4bi//zgu58OrL078D7gsH F70aOzCMgQF6fJX9rrGGR2qqtSN6BTYItw2rC2jQnd2Lkvp8/FF8HIQdepD1B7T39R74Jbodi+dm RTuhaEpp2IQOZqV9hVumEYqUQn6wHLxq1AlW2jxT5u2ZcaSsWI9wy4ccnC8of5Le5Nye5HE6FsyB CDBxh5sdhf+RVr1M1X7d7BYXDYNg7xOuGckkZT/3I/moETaYEnqbhESMpcXZY2042nwvzm9JBxtZ 46+cjdur4GfL0QHYM0/JrAP71K7Jq+5STw7sEy9zbC7U48qByKZ1c4ZKNXX3CbSnHBqjVJWLr9ip NQy7tlQKINq+Q5GLwKrDT+6FZSGtD13IF+6BiDunhOMtYMD4vbHYU49WtJfWeytTK3jAgxYUkMMq yY0OXBBtHK8upzerzvck+jQu9bqBeFp6rJeb/HQPFmKOwvdJvtdwsDr1A3JZ+2DXo4yL34OXVH2o mHe9po2OqcxnhMTUMBu229b2LHZzHA12FXDYrwoTfzD4UYLtMmtI5NC10rpl2Dch0rhRL0ccQRTn 6P9k8PIMJkZxsOT0L9a3Q+UxMFaJB87oVF9c+eTBVF+QH/D8kunZ9OFze2uH1z/mjWqvaOmj0Ur7 8KAgydfr6MelT2KAEnb+aOce4ndVhoVE71+5fdvjruE2SbXq3Zsy4qcKBg3WGLxm3tjfwwnok/NV OxztQOauipAViCcoDKVY3Xwe12ipv3nsZzCN9f8uRewVosOwI+Gv6lS90AMqI2NHFgN0DFHMnePE E7yEZ3jydb00Xx1cOLKtGjaY5VGr/46bXaRBz3p1iM+nihkhKzPbT8JiTsJbR+ksSJKbECzSnM+/ LOaVptASsLHuY5F8Q6WKt9GUPPsa0NWSgiFJ5Iv5O6qAsdHFIr7uPEtUsbHoduYkT0phv/OivJMI WY5ay/CrnwjI0qXxOkeSyQlJd2Uu3ls7GVJP2DT0TztoAIxLsv3OxxI6i3HS2G1RV+1M8Mt/Nza0 Vqpry+92slfMXNmJIEwyN3lomNAqEDH/G1Qo2gH8KbxY8C6jmXJ8E94MLOz64wGQWv+lSsFoor9B 4LvQx3VnEiofcFQbvvOVK4Spzd/kibKLMOzozWhUbfZwC+F+BgM8AzR7+QXT/pNqEQre9zTg7tTD hHK0Wl9OXNDSiVwZWDjFKUv6NPtluMD2s3y1oNMXD4ppPXm1VjOAFEgqbl9BVPzJBtgLi4/iHDWx a9RkoK3O7agmXBgX/APc+n1AKogCJn5I+faAY/BQpOE3ci7iB6rNLIakYRAUy03MobCcAcAGy1aR 8hmO9p/JusLh3tQpwmuHtEJXbUmmKw+UQ49hw8mPvFEJVde2tBF7KxiX1PD9N448yi4I7BEUvd6X uNt+xM1ItRCn3mANeNRAIljMtZk6iayPhk77FQih9Vt6EVATba2AqT5oyaJ3hLo09u/a3j5pOiNY o9t0b7LsEAbwWf+cNEvFjrBdX3Vz1tCmw3JoWT8QPDFgSQcoL+m9qSMsL1A4YXH/0NbsHIgnj/9Z 8ekvZyzJ8FOUrwr0VHe3FW6HFwP905u8Modz96BIn9UPeYTKxxukLVa9xt11ju1aC2VlsNkPlS7m 4lJbJl+SCIHFm2G3wr5/tMJF+yGP3jUyDRooTVhBGuRkOdvPJu+V+nrv/c5oNosFQsBCQJNHj2NI mC2A9BeHIFAZeR13oWs9YayRS7vSsKqMvcxR7EcryGUyQFCPKYjQC+ur9qwuCYRZclnd5yKkQmFq T8olSIp7oqyAzsNFkvRwxR2OTEmyAzQbELk7GWfy7TdyPMlfKjkyOTC2EJQB9FHrAZRemTh6lIvz 8eINerbimkOj1pehJl7VW9Xc+Gg8YAsFukDAmflJtNf6mX+2laHg8SNrHUbl4ySqMTxcZT+tTu8o N2lAoCqwVfTzClGjQ4iLL+i+qVwFINsYpkTjG9ovfGQVQC3Z0KgPOQTRpVxnnnxLBbIeNeyDunkd 8UI42rsG2+NzOoQz7D7iOuEp83Lyeyd4e1Jo9x8W91VJmaJqZ7pQB/57xI0jaA05PcWveUZUc7U4 hIWAJDxB0WB8qMnWEKo1DM0G2ncLLUvtGfXtrw45jGU5rOg+VgGrp+b5aJbNyFYFfshfp59rK9x5 Ja0ttoWl0wOC8K7YkhEVQl8sYEtPVJPKoBkTvBYIHi9calf6yErHr+R81NchVMumFyjfCdmsvgWw K+km/Q6zgxUgkb8P40W0oI55kaja12lXJUpIMcEeSlfylwJades5JdzqsHILAJeDVTX4RVqW+8rY 44tnE5rtwcXNL8h8pw5H5r4ZvkbjUNgkNEAtgYPxDlX5uhIBJ9OE1QqaObtNIEwlgmcOkXWJXbbI TafjTKlwl70tpdGz1gKw0QPukvbOaBLWXgip3h+U6LTeLoQcr6BcK3VMCm/bMFaiec19wvOucPhx UEz7IpN51YIHYEdtVc0oCBxUE0Uuifyuyyndlor9LmevOCiK1MYyGfjIfgdmQOXERJ2zv1yGRC/P scoP0KA2QEg4pcmbjdKJ1004CzeOE0cj8MKuNGLSufvfcAmyoxNIu4GG3eAWE05lepR9AlgPiXTo 705kwNGay6Aa7OfuyT4m9uUORt7F3lQUpJ9WLYWSX1eglBjM4zZykzroI0eXI2Cf9mEFQO3j/ZA5 u/5OjOTdjJ6/0yErcnQcZfAsY0ZjQBIQIbvv8Ff5KPT97YLfEkFB0US8U+tyrtUcX0aYvMTkb4SL ednOHu/9mHimgYjk3cbYdsPPmIHxhT52j1/hitiMF1DeDnwXInGGi68lrBB1jf7UoTqepPbx6rBg HJgh7oE9uSIdcsItlqa3D+IiUFAbU14knA8nJtw9r2KRyH05CDUQaY/coZ9sLOtTGHYOJapFgdNO y1DNWiFlQtdrBjN0zPVBOw57sKLJLWIMRiHh9MNgoG+U+C27qmr3g4wGog6uyDIaqFMeF8pVw6bg XnwXx6YgPOrxWBVFQfBp9VQ6MZnuoSkTYD9WCsfoaC2cNKz87Tdg5r6IQ+RWg2PF1Pr6o3Iqfsr+ H336LB2KDQSccgqCE43dOk2KfF3NmBxgvYh4DK/fwy5BNfOmF/78xAiqjJCQE6+ebGNq40T2VDMz TO+LZEcMO6vLvAsQTBcQtjNMc4G3HSvNVEc1mWZFmMNC0H1NKFhFQfX7MAdAiSog11mxnSJhVwwH S1xRSvDXESyCFAsqz09AWk8U+/jmDuvB9akr1CbhAUOINV/jA0qEqhcNp1lBKIcHyumY0oE7ebqk ryN9/HfDuVIB5YKPMu7gVxamPoxPZgjf9NH7cxHwVEXT85sMmVnbpRT6OfinjQNo+UlHbkFZCGvq Ka4RbahI093NrsciAB8AycIQzt0LBkwBqVXd3iiK7NChr2HP4mMRmTaSg+ScNcZwhKUMor54Ztmy mCrk/QrROzozWXv9t3yd9pnTscxghx37usGteSSecdI4TjTn8beo+VkREvurw77UHGhkZE9t+LyW GICr73TF5En2EscSMzSL83vzO+p9HmsCLgfDOkznq0ktplbFSFamHiJYNYCwTcIdKXdGwujOBa0u m5aH+TLmROtKAkRJgZMeP5m5EJOsZojYgnNOyhCqvHu+ajkgaZfwDKLGnPSk/aYrVei039rxqWo5 +QdvYkJB3gGp4I9FzQFsR8zW9auH46KYqffUnZ9+ShWIn6eEMYlenpNglOgkOrAkp1aB5GBBr6EC eMIhTWiWIl+D81mV9f9/Hj9ChHXaTvKD185qjnWzJufulmWkL4fLter7z61SzUXKfrntbRdlAgwB iVAAnuPZKJSkt5t42sJz9PWKKwkLK2vwzWNqK22WuVAvCZoDVyNdXxRJH83dA6JZUxK856XoWx3D nr5lWGXOUq5g8i+fjilQlPLgcwWG2tXWyKV1l7YoxJNDHbyRqZkyvFsgtfqmt6riasoOvxSfUMF5 jML18oP10eERMne16RDvwVtza6+rkEqF9yOOOT7/bthMTRn+q06lYVgcXyqib6OqeC54giQ75PGN r9XhsjDRPt82HIFqYq6uZvXe3D2IuZoC3Fgp+muGayKzCOejp6JeKpo4MFNQOv/sOqpqp/Caf906 FeHf+Od6s73QomZQSaj/UP209pJoHJzk1sc6aS9SWeqrucZPhVl+KNm0KxE6GFFSAbvC6eGsmgnx d7UxuGuPRRjO2qQSfwj3+OonQKttTYYgizY21Nd+BVxUxC2N/MspZ/aMaRckh4I9ODQ5vG9cW0rl MxPKhtfmRsVZxBN1Yndph4uXo8IA6yMfBjqINHqc4OCgmOCh9+JpEgCSI9FifD2Acx+hClMZGOFD nRAuD3PEv4NZoBScH06uvyd8QOSEtKlpiDWbZCCeKFVhIShu1gcFHxfA8pO+Wr/8Wd12eJ9RpIkR cF4aT2KbokO8LrHvQijyy99XA3fLyV4AD4+pcK5xKd19XEf+bTEGk+S/fWOc5CvRZy+8zJossrxD LGWDPadaXykioFKcP9M5gqFVQQBWY4EisIOk3JQG7orWM8OlvBxGQap/L80ldidetkYyQpRUaqu/ gNoDQRTy54FnJsGI+zs41dN3KQAniy5qn/g0AGWfV3GI3FL+RqrXpsTc49JKKKQSip+nYB/IRCsZ ZPhC2zi+jf+ZiFlFAxjFI5TMmLrefh+M8PhC4PVj/y/4roOkeE2TJ724X9PDJ4VKx6Us3IiWfSvh bAHPbdPWzcnYl92powiqyj2N343WDt39bquVDudbYJN5+fHkHuPXOS3Z8ARt0SYMirvnolYyohgp r6YLdN5jZS3QPnnoQiWMrYE/hIv+8d1m6ziRBulcqxcZEQqcj5lzxx3i/7JxThVVsQZqsZqZwuW6 QuXWmJP6stkz5i+73NBfyZ7ybxLX3iYWH59RpRKNHSMFE5F6GtI5Az8v0wbPLYrBSTyb6zDHrpUI JcAaMIX8TgLlPVKk4N9ADrL7C6sEqjhVw2G8U6e7/edIsYm8aw0sXmo8ur1LPTJwvArhZkynMDfH 6c/+mWqCiCSsfJ9Z/wprlyQ8pXvt7vXSnBfaSGXha1Eiq44R/H0Sez9kM0t5cRczVijmQGkwE9ux 01F2Wd5vKMlYR2O/Y+R9EbDUgoOzVUq+F2/BeDLtQTadAMH8lwFAPsZceFAapOwcnY4e0wInTCPq yCEGuzRGZhaNZijyv091THCP8msVN99YHEHvxK7Rzf2sE8nVbcVpOv9vLwUciRFCfaW1wMy+FBn4 /HHX1wOrakajd5XDT7ozcLZYhWqh6WhJ9Blzw2iLPz3VQraAcgb37ZMoqzhPUJx8h4i6/5HCc3T+ L4M6udT9oBHOvNb0lMXeWAxMGHsXYc06Z3OQl0H7DAFEGeEn+4CjzrT6MQhQ5o6YzSXFMb/Yt5ZG IXBV8mMKNxlxoRk64rdIS2YkXnIyYnuOwMELu720EyF4PeWVSqToBlApqJc2UtMpKwiZw97sRXOS /WdxpHOrsUxp/8zgDirIX4WCwIa0NuEHwWZDPrQ9+u3EUR3PP+SZs6VOrWcg/FZt64QRzdV5v3X2 U6MSZtJx3rEYlIF8Sq+A3P5zrZurYP5+nxymkaTc3f3UmSiTqpGXqlCOoLDDJ4XLg42BZtvzkgcC s2yzQwCv4cJ+4zSmMYyUowTVVgazZ6P6Hzvane2CvCJ40CX7uBb5ZZ3ZIYlhVC3ht9E6j9yecgtL UAJ7tHY7Js9IT+44A71LJxU02MFiqoqfRqUpw+YlP1ki+ooZB38AXpHNYZpskoxyfv9i0buDGQTJ tkzRFfXZX6dHXjcfta+htRV19q7xbHDC+kUAFA7FQYYF38pgQvoN5csapWksJhx8J8r0D8rY0rkj ssYZqBLnoTwXWqI/mmb+YcpU4fMHW5QeGmo7VAm1t08Ackb73VW0k8IOaHss7LyiX5e9HLqIkuXO QRg4MXnU3C0LxcnuDFQ8qIKMi+ozyRKzjO8hcIX0dcmKfBT4B29ZsqNW94Nj75Sh+1Y7dWuu+oiL x7duYzfrEwKCIoFkaMi5EW53U7DmluRnEQfvTPm6NtcftobBgNL3fyCrlhzEnhnktHZbi3FiY3sX WR4wnVmz/PWYt/ClS8Ii47D9hV4vJcmWMkn6FLsq3cUMEfjWKzfnk7p06ZX8jAxYoAiaqIPjOZRH Ms+YV4omJ4bjXRhf2UbYEga1N2wfc3BAUaRsIXZL8BFzciLkoyoKzgeXJEteOhWjnnB3H0aN5qey hbts97vmT7bPpmrJYVXxXOrLSwfNnH64DWe5aKchur45GFMnmzXwyTN+Tjrw6gogK4xOdpqlrQ7h cF0Xat6q/pTXiXKDC2YA706N2oKWhFSqt9r2Am3XVZlM0CN89N4Vvtc12VGnjBGgnT10vsyW+b8n ZES85zJSftkOoYaFD6TEdLDfus1K6mG6y0LcxngVYAyKLdrwXrhLskFohtXcXPBCgGFK+/WzMwmH 3k0gdDejWqGk/L+5CZfm+PuVLbfzW9nnFK8oFtn15whPBjX3PR2xTGq8Ij33/H5u11LXIlFaRxAv KZLOIaAbyDzOb+EDfPhtDSDW8YESW93ZKHo5kPdsOLO17lSnx2rm+RqN0u1zGXGFLIF0tpi2BoVW cq1axY3vRhNAjfF9VMVaa14A3qROxn0iI4if5lXjFyPZBp3Pm/Ufl6xUGxBURaWdPMkUK6bd+3VK 7WaMKE/bN13Z8elvJcXjVsaFGJE1cUPSuixVBZfBey6k03JoeDIg/15FpuCVb/91/oDoKa9zLViq sTX6fUSrBn6J2EEyIP0UtlcrZfPd5v9L1B2GRW6sn6PX2rVDCRzHTnfloE5ImSDux1DmxV25AsCJ RgfPBtQXSWs8WEMXM7o/uZzr6G8hItle8KHNja4sXGU2nFTx1cuFipCgszpEp+CLH4yAhb7758AW wQJ65AQJ+bJ404n9sJ+dEpZwXmhpYKOTLxdyC2FDQL1VEay3ftBorkPsvZ9u4Yd3mVCkHrp9FDdK RsjbHiYvrSGzR3nwCaClJ1dkbUYPg6zmWvQXg6jZo5fxrH6aWY4mdtTMji2L/pg5nxwjyiLrYRHB BqXyCmad9a6MkEKX9QnaswZ1BsZSgK9p8FMQt1sMn3ZY4+BFOr/BnOYojeeAE+A/xppu87Uia4GE 6Z2jGfC7UYz2Jq3gCtxvlReDWY1EKXTCfaAv06rPnk4xoVP+BiVcbGa+UXiDeyLhe9J/xvfvJ9h5 YB735jnm6IGJhX8sOQtLzk4sVVEJ9i1CKvoRKNFMRkt5MuQ4OSntvL/LxUQlms5FPHdUc9txiXWx 8f6hIRVniVQ2fjre57A/K1OYf/RxeD7UzPTEfVyDkMYFXTj1KlmgUG/SIL1fycJ6BtjQ3B7qgoEz gOJHFn40FOMooaPOwhM4DpLVlyImvjmPDKTNQltPUjQ/mBgA3/VD2kSKNOPiX1OKhEYzpHpcndxS C00lD3JeHACpTMK567TZkZzA+nqkFVgDyy9B8JykdDpFiJMhLIyKAxkNlOZVrS7AZ5g2Ns9dNnqz NN3P1NyV7hWbvALGF0hGF7tTJWQDKrpnuqNi40Z85wclhnoeAR46o1L6n+f5R1GreYlgPV2EHcml CyzSqf47M3Fi4zLpuiz07Ts0kYCQ3l7YF6M3V6YfmtBvg1BlOcNgac9coPAvzsfbVyWZv1q/REtA c1PTFX1za+3RTkW/92bA1sKoMoHGI6gfz1chf7B2tUoPFywIYlKXf6xaw5m7jahydGDiUYeh5wKb Fl55JCctk8p73xjnz9PzRezPQjJdTVOO4Syg5rwJwBb26x8AFipbFDYO+AFKmqFbtmYPq1V2NkG/ N3Vq472tD2gI5JoNwLj2rSdr7WzsfnplmKhtYq14jrDAZLxg3iRpZfBUG4DZf4yQnZ/XNB6k3TSN olL+gmKJuSJfjgCc1VyFv74XaP9PKHCG4gyhN6h3hpUkLUMozWqY4IDU3DXMPxcgsXvh3gojf3nU fOMz/ho8NXmHfKUYb9EVMXckD2pmwfvJXOaKlxWlUQN4ixtn3yFttDiqQId/15QvpkntJCaVRrNy ruPvg6yBMr0DlbfrTSZIW0eTSEz9VYhsLYZtnvYEimXjfzSA/77O2y8q2gLjL6Fd04UdTlqN3pm5 WU+miuKJDWRBIyTomdcSWau6l31k5dv6vjY8VyoDemUSFhUAih7899rVf0exakeOMvgdQBIq15O2 UWCH86RUsPMNLdegc/TLUyBsiyEAW/j6AlTnEoF+P+7XpsRGPEFfhoEZRwFSyT95N8mHBqYpxW0K Mtn3NqwKdBkBWLca0Icgycwb1Hg2oSz8W1GTrOox/lghcDf9PtybiPbq5mmeI6doLv+a+ilQowY+ r8EIbjp6JZKJm3gPsFYphm7DJ/LGxqmYYPsq7OObrVqeRr3hhv2fJ909COQGg4TzvDc+4EGTr864 4nrddBLFA6Zp6aEwr9r6F4fLWpvIZrqw6JlmxInlNYTi1FOQ69TLURaq/4sTZEvLsufnwy/G8QZH r48pVLEuKy5UgmBUVolKAAEZwn91s+EmY28qzwwrs5DSpxTsoyPB6DA2hIf1v2RXmws/vk728Qky F3ru7Jnan4VjDXP1Q+NACJpLkKstZTjUWMhQgPLCZwmi1JQUAJl3p9KzrC8pEm/rAD1CPUwkLqFU KmQ35mazc/xvBGckj3xrUGPclfQYQ0c/iDIFkSVcu43QKFd7X4q/rL5HmEo2jhOb5cChzZJ0/CPF dnnaOoLGz1pgShB5QnXlqXkhyc7Lxhdl7ZX/vQ6NKiQQavbkLT2lsRwKGvMDSJizVfeVPvWYPkUy 7xgV+rikiTFmYQjB26skVQmkkA1WNzQBqyd7ifmnMf9uMDTrhL+sW4sRzIvr+gDkqzxEM3f+t6Hw mb1yIJPRk1JRrlhIaoiC2Wcx9Vv52Fe1C1nvE6z48l0cLHLJrocwA+muivJel+zLQhdQW8uP4U37 GkdGFF6viAd2wQum4SvIBLEvPF8cYcL0sruTc3Y4w5F0rOwCHuv/1NmQ6UjOAIOwmNW4S75ymkk1 Z1q6Ws4+7E7nsYRHqMcQlchzTsF2IS5muP4/JfKZrbN+eIsD/Aqkjxqe1ajVPIQhZeZSVbaTILHl IqdoKN+XWSvTZT+WUnXckYHiAeEY56IJ9HIaPM46jtl5pySEOSpt0is3CDVtSWmfJcACQsUgs3T+ 4WglXlliNh3L2PL4ErXrXGE6xqVD1gPNIAP1fnZk7nISQlzIbJG3ZVhN5GH63ucihN3x/y/0nEt2 /wLiyemZHbvMp01IO0NrV7oWXXrng6FSXs3WC1qjic3zitaQxnqNoRrLqbQyzXWIJXru91nNDVep ABdM666UL3WuOZvoWC1abhm7cTsLJfWztdUzrSQ8dSePE1JYuyE2WyVdvKOd6+dQjOYUSbWoUeuv 6lVNFw4dlE1t/8vyFa/GUg3kQs2s2SNklWvgqMkYtvisxEKZeSE4sc7T4hTDNgB5FNdNffpkogET DKwJTF+rS4m7heJCzuSFisdKrML829iF30CBmtnodAhGf4dL4nQszka/+MBFgx8hZ/8JfQFuglow xfc9VpeaEWRwsaOpV1jAOGDo22VwM2xkx5qr5sOhLpYMky5c6MM7oXWy4FFkXGKueQYuS3tRARUD Mq33AQ5tcfBiVdot6urvyyAm7UdYsUX12nf0MrSNWtmvV2/7tsiEslpXoc8kHgK1k//DYphuahJW Wh5Ke+A/W+9e3tG3kQzKmf6jaIuVz2p3hVV9nsyD+AKL2SPGnoh/avrAf3XjXbpzmZpOXwnokApy VH0YhQ59XTx8yy4763Z7OCEQT2nIFTERoBuzb6W8eAgUFuqZwy5F0vwx3svu4JFCqZTb0Y1IlRtO b+lbOqxsv8BK0LqZ6rGDDNOcI5VVQ9R3HNewXz2Y+EZo9ePEzbqOWyvsOku1hV6QKR+b1Fmznkmc HDOHn3xjQEAonZ6/JCcqpoXY35Msi92pe1cBWM4Nj7ZkVfIhYEEkCY0gRBN9KtIRCgFmB+A2cdDX unmS94v77ueDSXgwrh1jtVwREbmQBkhNN9gUUoh96NzRWfNnlN8dNLWvtgHiH3J2LRKq/+qKeugW TpS1jk0a3Auv8pwPs2esucBu2J7tP7lABvH13n96ZcNFLxKtKZaTdtia8BcP+lXkFgfUTDmWPxHK bF7A9CXBsaPthI44Gf1RPfHyvA1oVGFyFTcBJcsmZ8r7Rzj57kt8h86bEEGkekAOYmh5af/kmrwf x+V87cVtlKppC1QSBJ/YAaVZekbJ97xOuZ+jEoGjepyVV+i6GRC9d3jQAWZ/wLCTlVRKdicqM8GC hB2RY3O4250MmIBSVhCS/a1MFSVWOdoXcUrUIumnA6s1bilmZNsjiyFqeypBu822wR8vqlEZ3eUW /2U81lSGQaI9seiC8f6OpTbF2dUY9OvnCyqO6oes2BjgoQpT1RZgLxpPKt3wI7MTbHK6mEgPEBdJ s+Zgxl4cJyWjmflLEg1az/kJ/dbl6JQllZRRxEGDKHvjK1LizcvqRM+X7+wViYd72BYYUAOegVs9 rx2e9z9b6zhXoY3g2b/EFqCfEsRTAu0ZCgd3hpOBAQKaSxCGjtvDEZTaDM0jZlrFlmt18SpLg023 KLrmUecW82VZXBhgUv07kKyWEvXE/hMp8CbcOMGVAZThAnCSnEQk6gF4M67ma/C5YQffxCpg5fpr sFbuIjGq5Kh662wM2hK1erxnZC+MY/teEVuDss1xuxoJArUyvSESQrRNEzP/y1xQi3ODqkmkRuwO a/+yimSAzUWvqvpX4hFqCB9gfYFqQjXopRhpGZPZ1p0ybJZmcIF0Pr8bWkDJIc8u3aQUALpAWa94 1RUjRDTNi0+C8CJ++BoqR5mUQJZXyJ3OXjrmslpXoceXDI0DgjIUrZkzVkDKqNAyPUtzoIDd8Kri izkvhOKTY+uf3EPGM0K5gMdY4byZMFf2Nloe1/zvsOPTyov7Jt7uAHvGY/xVSQLrXFmnFPsHT53w AEvKiApHtafN5jahEXwaP2Pj2l2dKyLbeMPpCAOuZLcszrY9M3iJxzQK5zVO+ipBJIN4F+WpmMXe xmulYyNE7tfn0XfJjepNLCDToOuCaaX4UiT8FnHbJmDrsUA2ZXiU9QYrk130+MryNhT+Ax5AqPFY Ib46vWHP1aDR5t/mULTkB9kmY/OdZMEOxWBNgnxtMSM2RG26RZFbRog3fv6tGB/wWSZ+vs6puw1w YxDG5d8bSYRoouMBklyg4cSIOSX0mlu0prxp+KMuRdcZszgsea12HuiXQjHTL2bITPhRbBQEQqYh G7CAKYH05rT31wCZnZ35r2YTMitVd81gDQIQpgs48H2w4/B7Kfy5vH2diWWgviynoB+lVD1BNqoF 0z66FhstnNcF/S7TL/jsfPIzQymGc3/FX39Nj+LQJoLemfs1K++t7bJvtTKzTsRJyUsaGkh7o1et HPPTtP20JglFJphpDEoZO4SbUHKNpE7Elwkcf46jgUfIwtS3Fpp0wAogefOL8vWn5WMx4KeMQLio uC5ZMJkFFWD5QzR3li9GpI5/LENLfUooTn5zNjVviapWa8GQcZH5xSe0NySS77svio36M49jyDM1 8wlhH3Nadr9WARM/CcrcViqx6jjAID4okPEeP2h7vQe7VwsUGF+QxNmaE1KBUHMSVxHTqy7ZHOw8 nrDvIP82paNHah+0E7Z4IuCW1VJKJdIPquJuATh0F8whb6fbBwXVystXlw9XaVAfotY7xqkujgPe sTjG+YyogfSbAs9TO0izi+Me3HcMg/201qyUI0u+KZVmEz6o1xPAKiQBS+R1Cmb7dEbWikStDZiO ok2yEZuuboJRubAx4bOmbFQOcQkv9tCie89+cNlK6siJz8tOpZad8/TZ04bqNiQcCIPcNABoEE4M kjqIsOPltWmGDOjPjXYENi+u1C2yU4Tv98Vg8vYa4d1b5rY1TtA00K+pdMSF+KgfTpFMapTId9xQ kLQ88ABUIKnZi3abSGBqMJx0sOACcPNcuaTXnsyvVeutABgsdbv69SOZAbh20Q2a7eliDKXtrpJm W5VZo4eTjZWNcgd0cb0ZTowwXHbD5fetRCbZAzpLYC+q9SfqgQ01BMmhqFVUC+fklQHX0gqw+yGt UPOMmjrQmFWYewS3jxroS/YebIiE9JzqT6AVv3v7K/pNOjsNvEdRPLAzLKJ4vcxj9oJU9cylENFt gnC/F4jokutWlhVt4y2GeYCaHEvnSCiSrZ3o8Frtn5CGx4x4ZZU81RX0qgDEWlTZmkyRTrXLSQgO n3Q3h7mu1Dmimd26b70e2hOrSU+pJKAxeSzEV+JKjgmskY238Ojg3PciPFHTeJe2FUVe3QSw9q6a Z//7C4JZeRQg3k1DW+q9kpziI5DJ19DoBYBjdQhfkxZi99lTcVXfyKujA/H6f+Jc3iLqvSXh8chb CMZo1hBKCtC7n1L/dRrV0LeIk4ud2LDM0v/M3lKWmD5Iw5jrcLRGYHXK88pNM2N15gxLC2L2gW6q CvJS+UmNccBt1k/cf0RMPxeYnIPHTGRogY6VWhfhskrtzDZOApsHH/Fi0TeWoiqM7gRsnHVTteZD D1wUEmuVYqFauL2113cKwEfsx3WRmqWNANioh0C7kbIAd+NkYDJUsRTE4eJO44TXtWQjk5TZU1ES ONIJXzCZqcDIoX1fV6a8Tp1q76I489ld2wAU+LtcY+gclceMcpi75cNazyZ3s9ub+6BeNPtlegF8 R9e+Dc+lMh4mU8DQY4H9sNTpcOuIRIQa3w1TQzV0eYBywlaJ1UEPGOYeg+lx94ljCzps/48xDx7e 0ETnrjy6yNjZkfvAnNepF+tCNpOwSSBSDWsCXsfPKgDorGdoMf+4p30Ni4n5TrX81+3nRn3iBXnV LC+es6tx6xdEVy1V2IOeIfQdML+zACzpRCOMef1fe6WxaGnlRnP9eRz4pOBdhUtgtz6fBpWNaAtq rv9uSZ5jqJzupRk8lyvX+mzEaxwn1DF4PNU80NCUjj4wvx8aTa1Xuy6xgV2eO4IZDECcjndZs/av xuCv6sY6iq5nSavpBZE+JRGVL+vrptMVPzqMDL2wRiKJWOLWEScJgG3F95Kgn/mL8DQQjfNZgF+A OIhNtvStvz2F4vkWQbWPlYt7UlCtfpT+2k7gQ38vRl4uBm8X3pSpirkG2AWvUh7H+1Wx4Oi4C4YR niiC/4K8RLZRzjz4715ol08ZhSZRwW/KyVbKXbZhx3PjwfiISRE+l2kS7cLtlVJYaJKixQWrQ/vf fulbCsao2WM9cGy3kOtJlt5yJfTHFNx98j6Qp/TIBe/ubGxvhqEC63o/hjATDKEsmEh3OdDuq7gC RkZoMAh+BJcGxDNgzJxNFoC4ngcfTJYTSuJUreOBqrodAd2/I7NdX+eOEbX6xygTbl5RR1rl+GUM sDhTmBXiEUOqPdZBaXJa2rpMTRPJ7biVZDcRUnbIgN9G4PUdAxem2ck9M/OuBJ00gGWgYo9fyR8s 5Iw2YPn+1iuGtVgwVcXvE5n/gsHKxpFagdXqdUFzthwJ7GUIf+to+pU6ddSigvG4ANUIBgFuTBre T++GjuZ/Z/ObhWqTRUbLCVyX3PHKJb1OJ2aMeB/nDsOJ7YIaw5gisQiI/uCu2vo2ish0KrjSnGY1 BetgQDvHRUYhyGSYgBI10o95G3I+4rVlVWfR72/Rmf7wVh+D694r/A1NrsvxEaaSjBtDQ9+E5y+O pyf4Jy47P+4rx7JoIlQtXw2S0XFyx1xhGJYKVoYrf6IoSU+hXbyf/ycglOS1LC5oldNE5C4KwC7y ToBAyj1H5xqcjj5rW4ZeYcz8d0wVbLoHac7JzkcCykvRa6qtFT+LSRup00W/6JIOEiSgoiJo9Kme GfnhzQjX9jWqIz58oeuDmrxza3hE7eQZL7tAEwC+UoPtE6ugYNBrgL5IkpDBfwGkFceOu5stpaQk SHF1N6ig0o+L17PdVCwQzqf+a/lUzxubE/CWx6mzqchA2ZaRa+Sz+IzDxqUrnxhC2ZRn3KyFM6nb JrJflh2nXWiG4q/0NDkSJSkFdu7eQ/2Ow93/oknyLyRjmsBEpMSR3uC45USSJCJZyjyJ1jkhlbPk W7U06/5SlppbOzRK9Q2k2HHP7ZffTrXY3WDKAcBfQZDrsmzZkmNwjBz++2jzNfMW0trDwaKGTIkB qUX3cvJl4uDBMlZoKFBZko2DEe7An90bryOIUQ/kPLt3toli88uhvHgDbFT5xztR45j7dX7S3LPE eetOWTnJVKG0NsUnT4VeIAh2XLE5yWjcNg/wwrcYDnJD1Bk97VH6OONPofP4qEJNQ9c6uv5aTHvs VtkrlYmewLxAz42I2cN/o/v4/ckeivGmQZ7aGbicExKWCKx9Y7dJxamvclIEiXmTsJmV0CIaPSlk HpZOm4wzBTQ7DNfNmvETO12/lDojnklh6GL0yQhjAempr8mu0K1GVSWOdZz2jiCGxmDCLo9PgCL2 OQFg+CUszz5BZTC3/Ll+YxHzo3EqWMR/uc0WMQxfcFrWK9rrGyswGb+8PLzm8dKiMW1py7p7b1vy A1Avq1/7tE9nkAHr2pTPZtc+Qc6PKfmimmmi7zHlqo/TwVJ0vlHdO0aXqR/gnxIJYdsN54LZ1010 uvXP7PE4uLgweSjBlM6jRuC5WJlGAF1wSAcJv+SlzxLv4peBoj1z3enxNQRKcIKLMb4INp1c6nnI Q/VYXUkUf5lF31Dia6U68aMX92vUJ/AthIw8kLS7VZ0IeMeYN0jqIqcecmS57n0mn7XrrarqdX0a YvVlH9fWpa0YWS5q8PINTyvv0mDuI894JChI/on3EPc/23u0Lkxak1Bd1+MA+C/ppsHpUr3Yqvzp EfYme7qSB8sOSqqat3OUrP2TGQ1D2j/0uTUpJnHj7enUSaJIdlBH0PrH9a11+N2v1rOwts3bVSbB FNBKfsrF9NZVrlFj+mq+LzQ0/bODQC1gOoFCyIlKL8WBC/SLYsZ1OPkHqrf2Ty3NRThk3i0s/Gqh n74WlGeYCSl8aFsMWA5QGJS1nakeEqfurPcfbKLQEqoi5ynU4qzWsu9Z7+6HM+r8oBb2B9+K1OO/ yJG4o0GvPcr5KFlm9FI/sWwRp+KcTfL8H1t9SBGwQ+aSEcK4n+Z3S9RfZn48DmANHc7Qaf7igT5B kPFmZgbaSQeFA64TmDrVAPcVsGktmEflhAo/ZwEVMyviGJ45Vjoks0DqBG3yyHK4Yi7RZndajfGx K+IrzGSndjnJ83525uGc5HUE2BZkzsQTWEgqoD61/Hs7bfU+Iv0xs//eVNeAJ1ZdwpuHlj5YTsoH zSYpcPeFw8Mzh187RsupAfDuP74nKsTw4nfA1iwU6FDzBEqG9DFJ52vxprQ7KYqFbeI5EO1oHc50 5ovGDL0Ou3Ge8bNrRQrVvT039nnUzwXPXX7af3NUVjJz7sryjawePeYVY7SPEEkigMeU42tu41L2 0EdhyoCwMtTA5Lnewc5vP2+7nN2hHzmECY4fpiF0nQnBnrXKJT03BoRrDvAYRjY92XNZ0Astgemm vmp7uBrOP9d16Z2utYkb2NSJh63ub7HH54X2btOZ2wzJsvCwSO98ByqYb+ExVIAub7drElLHso7Q m1bhvIp72gVtb1JMHBaZknIxIsot3f6PFIA5lbXZ5F08SPRYtgDFwXYgi4L9yPZVAPmltRj+mz3/ tx69DcVpAtpVWFf1tbeSMTK3TeNLBPEaNlhv4kJ/+H9JkZOS95YzXDmJl7/5SzqgmQULOWi2jZ/z vSqF3SABvegxU16YwC/4AwRhy1MJlxYK93LfQfWHNZ4Ur0ewhK/1oofuwsQebP8Rt1yKxZqwQB5s hb2Izrx6wJAPIGMGkCIxapqMgSdGwYDQtBQ3V1KQICltGjaoEqZad6CJ/P+ScXjWojkCkHcUknQt KUdRWC4Zoz1STY/lTiNsqqACPGLVe77xrrkyPm8bzZI779NegILw8+3xb6MB+ek71obkaQ1PxLoS pIo/JyWCmrQGOpzM0y9A3OjjTlmxMfzIbZweb5U5FwNe7/bixQLFYCJ6P3ZfYlbd3T9ToHVGTzwx HNEy+CAA+Hs4qU45Edoj2AUNCFueor2nffcq0tX2EJa6hu0m2bEodK+XQlQjGrb4rKWfBDCVQoVV VaTd9SmVBowpFHqMyJISvPLYPmvxPKCNjUh2A29vOhS649kmQ/4jpAHxm4QaA75CraB4ugvoADDM aF7UAHFK1s8leef6/nvw/IhwCm80KuK/+lwkFBLmU/U4XBtycOqY2XqAzBSdm/pES1p/YFnSWPkg vKbyT+BymUifsYn9kbjEGrQB9idpHb6GMqoWtSkNmH+dVMVxoDyXq+ovlUuN/Iupi+vpKOFcFull Hm/deQ3SSehaPEMeGCy74SjOwBjfripQlqpddD+l56wkjlNXlmUmAEoExGK2CtUbNSRzbmYePy6W rBeiTvOhqfeluUkHItL6m48pgOxIABBMhT3umsLxGFgDayGdaKkTFtZsJBnT/R3dP2RvBwLGYF2J sClwD5PI+BoVTNlBe2IGeW5iC1QBRHg53uAUDnFUeNBJr0MLpmxGA9PER0YRMedxjngoRTZUZUxO 4rdsSUzYasPpdbj4FZ19nzX8iJpW1IZTBTLEuuoMlFadE339QqrZDbMs/SGbIQe+CZ26FaVw1rF3 XsrV9HjGmpPUcgx/Ki41Vxlrb6bVblJ5BqBgZoU5yDkQmmTxJSAAZvFuoqlN417LZwynVhdUuK0I oaMQNCmW0Wo5ru/YO+Qc0EG1nqH9YbbRAstqx2DzDdNoEiQoFGRH1+yFzafYDIoNyGjz73Y2d/t3 K1x2dLWZYoe7WQD4BVEsbxAUTm0pnGQWVnM0radPuUywbqiVtj7MXq8SXWGX2bEmlC2bauN1y35h RbqXG/EQ4KDnxRRh36xnxp0CFDEUltskD4Ns/pMJpqIZaQ/mcIz6s7OiKLmIznWF3BW6Qj69kE5V zjPKlrPOgOtciWjODcLkFoQHywwv+bzj1yFD268u6ugkXat9O5UZ/vLEKbXy5MI6ga82rciYCGHC YgiK2uo4F2NhWoN5jXKlJR0vIkoEPmVNJ0icrldhueb43V0k4JdyqU8O6TULoaMCwWt/KtyXa1a8 7Dc6MhylL7+9sCm6Bz7uGAr9WSgqQZVPB7alguvFCeqBi9t3cXMeNZiXH5u7zkyvEi9fRQi5ijzJ Iyhn/+NbMAF7fL8jV6fbsBXO/ehEZnpW02Ct9QuXULLHW1D511od7Dib0MLqqKJp59IAaWXKApK/ P9uOfJlIgUav2LdbDfFhC5MGGvODhcCzmumRYYIlU1KMpJQ0oGjP0PWMHfL7sUNi0pMIK3oCrZil riX6D496s1Zf3r2uvoQRrAHya8i//Ry9PjnrzTKvRDsWWbbpEMIqGuKwiJG2fzCnRs6GYBbiADZV wwUIxznYMTfxioXibclcy+dKVAzl941SQiNYOtFSpH1sNkLog/GskP5lR3t0sQQ2T6C2ZtWc4Y9Q zhFCRImpzcuhLsInoH6S8J6OQkKZtP6gCtHNIc45iuJWj0p4hYH0gSnPBL4BCPmKKF4sxBiLXYJ/ vYKVMxD+n0AYPL41aanmJjKfkEgnwpMJf9Fzsg1UlcwveUYMOzu2m/BI1Kus5zh/FRSVCHtAKpBE Ilv8A5MNotPvp+tanvTJPcBn8Nhuf7mCPaMg5n5AseyXZPJiThhmyFty0aEbtEVf2d/+dwbrWvJS oLgfgGueO+6LWGrbVSE28VlzHsiD73Dd64RMT/X7p11JitOrBV0c1urV1Bh8ewwF+HERY/nvi24g KdbuuauUAXhpWL1nWYFmQipkmrv/cGQxQqQYJw0mCfEAMwUFIMdaoxbr0dFbIq7d8nyg440rzvkt qF5J+GI6H4lzu312pW9YS27G+If/AxdajalxYP64VSNHwFvYtIKGb2FUHqflruyA/URrB/tht6sN kbxeJHEJgSrE8CfK7Q9q3J0kAijMNmxMCd/4VOFav22eRFtvR0E59S5K8TsrQiYiWuKSPM4tC1a2 eFMWfXE61itEgZmaB1lDjBWOQMW/iNLqclXzFxHpljFOfl3U5krOioFxwsYJAwgygaSzYXNTD7wO 0c9djsaJGUrf3STDXmhP65gmlov47CZTbx+fyhJgX0l7ORDfy8aNLs4g/5v//5HmKcvyo6FNqzy0 JJrdRbNXcgx2DT0+So0KidF3VcI8WLIn2aK+c6kzIfIVgYXW6JlW1AMHSgMLnQsZAk+1s235paSM ppqY23fKrmcOvlDZ8p1IlH9FjkJ/p79SO4ith3gFegNUTp0o08ZaiYh9m5Z7wOl++m9rcwn0f+tJ GaYAqHJAAZLBsWQXsyD4lhu3iu6RmLP6ilQO15GhoaF615laZcIQqGEBEQBEJDi/OdTyhD+fLgTF eu83qwnvE9QT52LH8dDbIYFkAjrWxlsGC2F2x0zuQI2BQyjHNjSsLpYIqIXnuHIggkSvGIHJWe8Y vRB72AMp7/IvMzEeMAa5SmrjQDk+TEQz260bM+kwbMrRHNaLHb42vgN0P6rm0YPOkXAehCxsj1Jo opRyexFmcfQzNVb1If7cwa+3lavjMACtdWHeD5/WneyQv5kfb6lUWBnpFNpSSDAHLn8N3AKau/k/ bKUGI5pto4jzjr2tzBsFssFDe7qSQ9S+2IpMYpJ99IIxMkyeXurZIxn6UzCkW4hQLNBRz25DD17d 3QwpkOYVihsqVjkKm4fhoHI+qMr7hZ5OCIm3z6MwrJ7XPI8aXliNxZJqkGjj/Ao9vbKSPM70lKMl 2vy1uYz73rGR/X/LOq0gZPGqw7QFPLqNV1R4tl3RNv2ZjWayNuJPQ85omHdIQFdHIbSTBVRLB46R 4VeYc6cWXdt6OPNdvL2inW9djfX63mtO9j/zn0r6z+QC81hIfwaXzfoyfLvuX8xzvGKd3ut9Vlvu AN1raXgMzIzjvsTwU7IUApKrgnv1K/jNj02yWHxJCunwq4jYbo9Cpi6kLTCyX/JJRBnAUW1jILsJ klcKbZsavLXtFd9FGKF5+vMQaX9kLBsH+F22mpsKv4ygj1mXOwm/eeCYMtYQGx8gzfycfeNtAiUL QrdY+uD/Qt3vgGfF+iMD4MXcumQatWSCjecccxrQ+ZYHqWkNcaWQfKYIpQjSrIK9y+4zPxaUzxmc JYIAQosgvM0Sw6Sh2l/rtx4vqR/WQhXZe3J6VdXbCwoiyYZfOlSNmTusLxd45e51Pfb0WmlzpOFN hUk3yqDqJHvQlhDsb/68Po/FkJJaZSfuoNkevFs9L+7WWNCua9rD25XLsyNCxk4A+VsrWXHt3Kbm J9mY4lgO+TVXBSIjqW/CAuMKWpgq7093TAoXRrN/gNvO/MdgDUmw72m7lrKJubgx35Rg4BvrClo7 Hjmx5zJLbMufLRNID9jKcvHpoa8cG89HHU046nc7sgNCT64xx79F6U/v8VNLhDnxofOXgDXPcbCH fsiO5JX7LtZ2+deje9V8kvcmrR3tCKnocVfOgdKKmEMK01yp1LqeDB3hEEPKZ2n2sYqFPWz3NmNg lyt3p8CtyQfJjBqMTawHFXzlLi5TtZydYoqnMXfDEDaIdGnd25h0PyvQXe7lBb85etVerRT5AN88 IIGr7QlYhl1nZsxJRaEl+dm+Md9k1oHs3jlmOTLIKJ7Viyuc0rgBhetPqubFwzEHSrRguepcL9SN 0gqIv44izGS4+1Pa78cRfExeN6XkimhD6G8/0urRd5sR2cG2zkjnhtdWoU01C6sL1fW/mdvxZFEN NWkmA99NPETawdKCkq+a5rYjw8Tld7g0Z0Fz+kzdQDLkyfKrbuW7Vvqkq8gTSO4E+UJd0H/mFj9E gdNS/glU5pIveaRiXo0r2qvHVxzIG193jduct9GJPbDxAxC3d9Xiy9+x8pNhxcNWESLv48Je2a33 z+MUqPrLVy1Bqb8bkLi9w/72QP9W3zxiRrnXKo7hUnI9gaViT2AHIBURx65pga/phX8le6VAO99n V6ZThH4chyxhFSMZutZSzPM8GQO+hwTIQmFJyeFb+tiu9Y+owYJrF1I3i0sMolUArz+mwqii+p72 d6MYrtBrQJU3AjvegyEmU93nSHPv7br2CvKle83fnaZem04z8SAw0QzRwNqV/GsxHrU2zBwrFWjT syYL56G4VVxCRBYM4KjJtEhW90YeJNZUGN3U+eB+VtIsbWKgcQBOoQy9d3pRHen3XDAmlB0l66Ob C5JJKeThZpKu7XvWJPD/KBQBLC3E6ApT0aSY1rGpr9CIi+BUMZJB0WWqajf8BVZTJi1fiGEMOhKJ i3H0krEj3LmJJ5mpOjwVxa4/LmnFGDfMfJjfzwiXX/c7eXAoAiY6/4nFrcCOSlYh20Yhr5KEv9fh /Z6O++9vytw+wxHFsg9+R3po+3DjuWZ8t3lvAduaYjnCMu0USV7iqzgZ/0Jvnu1JeTWA7I7ArW7K XVaw3j08JD7vfivIybwxHSDklKklOWhFh4Ynen0J+CpEp9KnKVkUpJpPnzpWkgYaSa8LmDWOAaNw ZS8GLlch29RHPk8haO++uby2WIFolY/PxyFdaW+40mKqfKsRhkJ4LxeTAQUo8/O3uxpkRjhoiXUr rLagVpPsfXBdn6mUXxMuLPCFzRlXjpLcXHUhfMEn6KQwCBqnhRvz1dzz9yjU525OD58MFyFyG0C4 jyyux+xoNEzF37BzLsV26SL9mpx0nf/X1ZuzkWUPTppc3e17pdVlP4nb1XenKVLD+wuBpvi7rz3f TRaihBVZmTAV87+P1nW2wKDEzWaGNaHj5Y7fCrQALGa+Fc7gDWkkkGZBGSAzXXCX8TmMaQLkzD+k y7F9rks0AVmLwE6n2FaGdbKIMD9LmtigR9RwgQCMyh6c6WvD1AiE12AI0CgkdNb+OPS1wCOPPOSd LqSpkO/NS+9ICLBY06nvcde9cUplcbVcysVU/nQvIUt8QXeiVQzNyZfOdvNlh0zYRKZenBb6nD2s y/45PL0eCLyIMgcjU73K8OVW13nWQgNYxPakUiuRDKS7BbXAan/cFBRFq4/5GfPPN5QtxLiJrKw2 RvqhdQUmVe5/y2LXarnxi21CIhlGXVRNd+O4bgnrV/Ug6t2PyUBjAu8a3zcnFPphiRFj7wYEbQ2/ /Iil55T8EYBzMK4b6xgJqH6+wnF1mjSCyU4m1f1OTENDQ4nwOeVKeUS5fRA3IHfukRTSWFGFjaY3 nP6YYJgW7qvCgLs9PWWEdv0v4LeiIW9WSTRiBKYfgWrJwyD6T+shXd5Dn0pJZ7WS/3jj9emtUtVA IMvIjt2ex7FnNQ//z2Y2017qL6Zky/lcq8RpRd1vBxsKQ++sTtk0gzGrXusTEKjOtjNlz+Q9c2Xh ksPi3OfBu/b0IodAkInkRq8VuVeI0AAPGIN8Kp2F22oHJOtA1SM6DMOzmRBrqvS73IyYEEGW53Zk gBtpSfGZqIxsd6MiAR4Jh8GwdetIIazk8sPyyNgPvX2LDBmd9GW2GWRAO0mMCvkGw4OKmGuOjsYZ T6TCHUIO/F8vZA4W8McuQE8c9XZYY5uq2qn8fb7E5ufUB71m7cqRuCXrOQpM8kiEXpRivZ3E0BqU 6ZGWdmInn+yEL/chgYPgoS/zCtwhfk6Z8oSETexlxAaFajKW7aaarI+An9QemjlI2unKaAuf9R9Q jzu3QETfQu1qJgedL61HGS5ALBUyAw5J1h5GQstVssY4P2WufgpVtCflSIaBrtRSPL8r8Anh31dx WOBoq4xAMMJxXBqwoFwpGT5UKlwPs3F7j/OxMJ4tA9UhTl6aotCw53m0Mn3nu6hmNq7RWWnN8nvl A70wn9l/YJkeo26P+bHostjbZsPvnavo4jJSRY8WDUnT87gPS6T6N6W+mvDWLZ21QotF4ZJKpuSu ukNuPEl6GCob21V9M0M/5zvfrEPrTBIhU50Wpv5/RmPPR+X51olCBV2pR6kHCANduFwLqtzMLG5C YyzR13NWreDnCWFvOlnGVbHK/4qQzHg++W/3csSfHziqud1xl9jFsUdV+pa4GRk+FFUrZfFC0DEK 1rXNFSlaYZLU/4zPDQx4G9GTXEGf0yAXcWcizi2XAxQYDK8bVQtFoQoLXHOXvPBSEt/64f2IYNms 4GViOCc8R6ICy+pyoQcFX7EAtlVB7vXHXacx8hA2XeP/F0X8fFgBCIS6mAj+4GVzNuwzKLhFpaUp jLpbkHQ78Xu5fHZzsI9wxhh1C1sL/ylYnUp5P58RMlNRa0GXCFuh6rekL8uKRtGRQWv67b4do3Fk n8WPB1HAohje9l8yEcotE2dEYZlYpIK3lkDhG/P5gbbF0Gpi5zjD7kiYhgOxdL6JnvvROOzzi1eV pQEHPqjw3YzIDyjOx6M+QRtx6g8f47OhDZCZLmQDmsduMbawTW7y8yO07ky0NjGoc9nnxo8wJYd+ +oqPOeQBgsBjSnw+dbky0XOnQO86pa8Xs18OCYjwQlYBgaRP+H1P2vHlMWmGSYOvhduxnQgKf7q5 JKpivWVg/YdJOizVAqJW0bFg4kqWV2MBUAUYnlST4HUjz84q25SbNZsYWp+OFv91TvFXTsmmgbjZ 96E3NYCn86iVaaFQcup+s2PKmzYuLZdIT4nDtDocYJcUGTjIbVovfn5MAG9RO3Av3cKfbqHpxf9P +XEsv3RhdfVIW+JdjCCCPsefjQelBCWO72MGqanvs8ANAvE+iKDufzFBXya8e2c1rZaMznx9eM9h gIgwPS+rVO0O6OuIIwnmt3vloigs9ILvX6bvKxTA70P4PnGhEYQ/NBgk1JzCevwZNNesXW++RLf2 KbTPdvgcGPwfaUX1pdmfzdS6dqLpsgB+nQo9xLHHEnL9NLssmHbVnASNYuGJBT7z95og1fXZwvhv d59D6Wne5BMRcFPHnAlzkCf4wTdcNsmiM+kwmFQ2oANHk9cuyw/1D03NLxQsQX1sUQS/+2W8shKu MGur2Wgqssn6Roa2iemoRZD67xNL7EDmNs7YLKP06jnsw53Y3kz6i0nt6NkTD/qIWyPmyZS8caEg sd/QBIrVaoHiimrNkiImBABibeAV8WzKiTNyT3VyBJ2EI7sk3U7Py9LvzDVb3/e5Mf6AOgFaD12B o9PAwVi18Qy4o87UB77VTD455FdYVo0kbv9M4cEbv4l5MlJxCFtyHK9+ZbySyovekHk6UAQ/tnvV Ezpq9FJou9XSHolGgUzcV0kawvqzuXtYzNUQ7uXJYrSy8CxulloiR3Q2wQLbmlAhoPA68XzOWCUS 6svFaMRHQ6HmUpF/mm0iRY+bLH3/tuQiYJawQsArzlzrHG0P1RNM5dC4I6aLF06BKmaIoz6ZtnTS /S8XtqIsB0EoJi0CMfEVSIe/XD8RLbyBvhfY5boQ4ccxl9xEcYowH7ZvoXxNYamsxAXsQukVyuvc yCYCZftek1PqGYy9pb9cfwypUGCAK7DZIZDV3jAvaXOAonxSZH4rUqJjJhpUEhL0OWhIWe1phtpE Bog9sLFqNK226EPiNO9BjfNInqiUw+n0Y+CD1zWaZmGZWE0ncjcr8sMYQm2HkRY/IdM2ffG3WUG6 o13cjqD5dbRDvGa04qYe8j+j/VxC2ulW2J5ECwgwpY3z2jgVrhSte4XtHMyn6hIk+YqnQCOlM1Hs 6EI8Ko1rQPzAyssmBnhhY4NdzbpHiOndf7WbjMgdAAcE97fdEsafVfShUtc+qhOg7pbtgt2p7oCg LQxDWzd5a9GlUi0g4iwNhFBDfAMtKGhZ6mkpt4zVthB+ZKwPZ65v2BeVH4GMMwiJgvTY608yDpb7 M6FCZIFowU0ext38Gah5iZw5sNwo45Zrnd6a6w/bbIH54CndUeDRs2jqH0u5ClkEi/86XXYy6gmI +Blehhzlqy8lPCWXNA7vDLHj0YrH8qO3Jra80fXlEeN9J8NIhkDVpiYdIOR1nAhiyEJ28HFHtb36 CY3rb9NnSlVkRsDh3TpWONUqDWT56BS9I6DixWIIHD8ASyhWKiQ5VSshyYjGm1XVWwZsdIF/ObjS mjrdXOYZ1R/zIqe+VhJdOWIb+i16RaOPtyEhfzXupGyamM96vSBE0aDE0HLIr+pD6abUxDOja9hD 7/yC/0soG0GO+kcjUd03dg85AH7ScUXhtt0fbcb8FPwuQmMqwe8gfyrIVyvk4wJrncgFN4QUUdec OSn4zQmHPNUfslPEvEWGqN1MlNEn02XVe5CQ7BozjCJFaJhIfoCwng6XyjWNRDZbkON5UV+iLVxl aZ5BDSttkhY5S6p1nDUBbfBvfmi7O0HX41NsLmlY2AOwJgddyppep9unUKiAAON7OoXM4KJJ6Abj 6S3GWQVrrngi97gEcalFB8otDxWzyKD/nH0rjskXJ0WeE6swhH+WrwGscKBoOrsH9j1siE4MWPXL dIEqLtxSjxO3KZj0RyDIzp7Vo32FkcBEk/dTBuxbhkNF5/sUJP+KpzRl26EVAz0ews1fBobqIuME 3UDgKet8U+h6Tk5G2ZLlvDhPbEgkd4ZtdyBCJ5Icqfb2dC+mZKqheaeQNNp8eA/AY2PytdCfvwSh 5GYvBMmWpt03UAoZIDAsAc+9h7rLFx62cMQj6IlopDZlsTleqsrK3giAVSSUE2gNQWPJAwLBcyGd X/rCk7npvbjejgTqMHb6+Q/8jcUuREBBj+f+4uLHtB5+wWmYHhIfR094Wsh5+chahlNBUsgBdMOG omHdMsv0lfsiwjTk2cj9J2UDNgFBKBJLyKE8bMqZh4Hd28ntQtRc7nVMs6ntKazmmWn6IGqiEU1n JKgDFW78pd+9Pjcne4udA50jpqxh7sjYYnOdGucpe9etOcDUJe85MmaOYSbB6rloKc9fhLs4c4A8 eFlSz6cp5jSMjI7CyTicx0NMMwGuZNbikRGhI+L93yGlvCq/mBU4I4PrJUBYcmQy8ShHRryvQXxw g5vqyMa+6ycw1fQ5UkzJp8c4Beg3zs69HL7X1cB4yAXI/QPCAuH5elmzqx95knNuxtuTXkarL5vE aHA5FZzkgB0FYxZkm8T6qHsMvX6JlP5HH2JQPUTPniGx73JffLPG7R6O9vCYtkDRM5WCK+5iyZA0 6MjTYr04d2VWTaWNNV/Ws27o+y0Q1edX44gZYKRAmqoWNHQH5c/t7NfWR3tT+pdTbEaHGsIliOxr Cw+374QsS8RrZ6tWolL+5AYOZ14t1mQ2QRzwEtsxzGjVGRtmLOGm3PsSeso9dFymcfkJCx4t1Jjm JIXU5tcSR6MbON4mXVWGGlam6uv+4Swfej0DXF+5PeNQYFFpQKiYpL3xXK3ZHnbgdtERWI62rE3Y XK042KcaGeCI8hfzObcB/LCT+eTlxJtUK7n1n+Xx9X14DcgJZHWm+fVFuVE2iNBJBAZurSTABYJS V1Ceqf2bbmHr96iSl13JJgyVumMGqtEkEV33aq8ShQeEPFmf3GPwdG7roeTj+2g++L6g38MNaYW7 AcrMI0aL5/nRv5/c00WD6yNkNHJjTU5QSu6HRXkN2CR8gwCoRXYkG7+2/ImX6DvL0ETKhA47SVD2 mTlHyGqSchuqiixGu6HkEVAPxK/poiFd+yFeFzHJP3gR3Kud8CSVNxwbv7i9vlY1ULOrh0j+ZJ3I 84FTjBClmMkxgpcuFoPImUQidLsw6XoZv+u4UcQ0JqB3mgvyCts1h2sQ1SuJb8CKGIYFTZssAYQU gcRYn5qJbv5m2oZJjIFbt1/zRTWtFTAgQ2/D6sfiI4CLa2sv406fBoLN7wP+lzMn/tEgd4iYxdvX y16enQuzD21CtzoU+4J4oqelNz3HpbPj83DH7NYj7ilgJGpGNl65xYp3fggD7GHdWpm+1N0adU2y dox288J0s4XzJ+nzK/N2Qm8hckJ3Ol5sOsByaZQdwr6xWsk56BVLOSGoceHqzE9F1BwYKUbVgdOX 7X/fPz94iuFexjcpBRIO6rWFPUGp8WDnJ1fj0plZZTDVoW9ely/5INQsxcNr8MRqj8Jzt2fuzuRW qNamPU6oeKdKtqch3icG2mA+4UR5ujJ3TWnqd4X+s0mglJq6Ybl5U1qneJQTVFfCafy6DaOEgc6x 2g5jmA7qTTgLcaoBZVgw4BhGMtaLFijs8i1wi2/m5qIX1PJEpZdypwAW9JheLFtQl7EYmY3hBWuh CpgaH+2ZtDC4+91/JnJ3ZgDDm90yvVxHPL0L/HKS/hhocVltAJeU3jocMLnPD87NUBv/+QJltmvU +Q4NSuYFk8mR7HmbSrcwzzCtx3JbFbADcTaATqRGEbWjvPT+I8rApF5PEoEWNse6HR01k1dGX8DJ PBPQ4srcoU4C7unCLnus118oe59+xUu1923dQiL1MS6LRKbvt1DZLVThWhDZOvaFLFeDUKJfVPrP UL/W30ks2Lu5//vot8WBGycic/zZJDz3wvmUf+kyelBa8lTLIX+SLaFiUJvpZJD47X8lXuRJdkIi K848Ot6TdYJbBGe1/7Fogh56hVxBbxi7xKpIkv8pXS9eekfP2DfcQykJGEhLFYeyWrNF4/BtWNtk IONO80MBE+3I/metflLZlbcTAZHJV0TTLCgtM7hnQX/l30BOSfc49u+5BHjBzJ32P6Qw3mlqmYPb cHpFjlegx9AXvPq/MwZnyV2oDZQr5cNaPKCX4zNabjA5FartNIDjtIbgqA0Vkjg84omfV53dVBoO QJWkVV2/h+x1Oy97OWcNsK0Lk41oJy7n2lKpLpF+u0dkJi1iulGDSc+RiIIKM1JhotX8lpp/C0ei h1kgCuMLg1xg7/DzE2U6Chy3O5X9xfs6jGyYtehdxFdD+6jC5QPyGG79xXt15jski37XPdiPYQGv x6FLvrdcBvu1MXLn2rttdef3l6YHWzfu71y0DiHCouyxEDmfXEneD0rP5XeVulglpDKaHO1KbRD2 WsxPdLs9rovXfFQjjXMpU4Py8DkmFeXXJH2bihMmdd+4QnckV74Bg2UgD6Z4CrTJi19nTKtlcs6a jgUtk3rSYGSZr39IJUqxC1mvopA+zFDo1j85jWeQvYHCqqSTS8x/o+GmfESURMLFNjyhVOXAFCPB 0U9UeqyKZXjNozsIJ237q81ibxXBGUOXNfQ+KOqsWvTFpPRTnZ/x20yf4zrhqdN34ihjb/rMZBoG c8jS9GVb/4TnmaJJAZJmIoyLAdqZPmxT0h7fGfYeMVbuQLm+vQMKOYmPwSDgUnjRJ8wN+kofWoC1 ewTahu7cr4Eak9/sUd54bwbzW7FdJEEHBSxO0iEJUXlm0Px+EDJokc+SkJixcedG+fUjskvMX+z8 D+TlgqdArOKzPuwzMaW80FpdS6BRMviOiXdPrv75VGoTY/vWAqMMP/l4FaMekxhXaJ/lCjG7DYiQ LBQ7T14KjpqjvPkcnb7x/cqQ7Q3QqCuZi7MDdRDZ5tVIJB6/RgBP/BECOhmxJjxTP3n1k1WhjhLD NmD5uXdNOJGJ6re0HrkdoyrtW92dJ7vXnjwQEpcJgQY9env9JqfLFvvboSKofvj5h6PkPYSbpO/+ iRpJU+v8X86FVU7XGWE8CojVPBGpTPc4YOKu37Rr1lcT7geHQZnOSg5rIcmxROLRl5fu5U0jPqCl zx1OvHq9AgUQKJZgs8LuiByWfWT8VdMoUx+TMrGFDWXtg4yhf5tk4YuOUiXcyDqrEG4TNATL0Xju wIa2lmpE5uqVkwm3Z9hvjuhMWr49LJ5q4djKVaOdI/a0ene/TfZuViYcPruhC/3j4hFIglhccZnG dfIIHww5wC+h6u9k9cYBS/LWb5LMcDzHniLyv8BR5nKKhpA/XMDnXV1KQGBXrN3jhux8CcdabAga c2nHmNAogcWsF3WoLuVwXrUPxaKWj8fffOnayWEc3srnBnyLHRHSxqPRxr7nsBXvC63r0RzG9hrX 0wofIq2QBPimTb1OZQvGtNm50X8eDHjmVuGNI7d6T9ie7CYmTr14+pnz6FfF/iZfJRkPEUJERLVL l5SRdpW9GZWPOsNGH1q6sL3UIRQYXs1/gaHwpt+TfIMNw4x/2ZitlhVTVrYWkbUtQkP5R3PdPNFA PbTs2+h4jLRo5Y+9teIL8dLADWhn7Q6x89wu02zSCqM59phPs+FJwQAU44ZhBJ1gIlp5OseVuFHX 9cZhOiMZRsMX+/AgmBIzT8I//eRzi2AXlT0kp23FLHJV++B9hmIIBtgauAXc8XSdfNZJBa4bvr9K LyZyukkH9miLfoIsxFoabkhvu1jI5skATADDlKhhG5BFVPFHmc7mAnw5mQtWGFznpUZ+PcBC6/P1 Ed8CPmbgVAl+UrGPcnnsQCBkz6xdqa3CuEUK2SDf22UbkKm2BgV00K3TcA2BuShGMOo33TxmKPyV o2FkgV41RfsLF3ajNRBwASj0Btl3q6frp66f5frkGGQQDqaXaPj+aM7yNR+tDQaEfij1oog8Arbl yULmPFh+2WQmfXct4+MXPp6S+2wgZ6ZkfSoO7ucY6tX7uhOprVqXTG9RnnRWa5c9fbtBa2KzgXyH 55HnCK06GbISXfZoglDGUnn13pxIE9m18lS+6RMQ4wMBwEL0Igdn3bEQeW4C7GfFg7MXSvYEDh/C wIqqBry7oGvuxUyZS4nEqYO6IWhhya6CGzgiUn2VAcD/ec8rWrIzJQN7pC9uNZ9KjKyLN5weKwVp lDd1Ywopk78uC4rs65oqaUpjoh188sRqYIFI6Z7VEyn7u4iixrazNj7HihjoZEYuPjGGVKSa8d0u 2F39zooadtz7mBeIa8D5xbK211E/nTFDFDqbgA2mmvUMFmB8nusC5evAJHb7q459frldiO9hUOm1 xvKTGaI3+vMXl5JQOZO2zjWCv2382N1eOyTzmZoJ6DxCbMufRXTq+/fgP++xeEBXjpnZYWM+470G vH8iG4KlSyrjg6DlUZfSE142OyYiHtgXeFpsBbMyXfIKKYWYt1mB5FkBryVxDE+SBlf+7RSr3bqq XAB+BRuGcVWCWjKUrEJLn9D3RibRMiRX/H8ff3AOUawPZWtZj5r+bdTJU+aJ9mUfNtO1Rilz2FbU V7/p/CaYzc/GSFzEIFzvwzCPfSZh2KHta+OQ63a7290xuF6HQv+tO0K0AdOtAsGulkeO1LgtULqP 8RWQ146z13SPU7Y7m+E048guOOeXKiR0UrXg+eQyOw8ygEh1RVF8mwM5bYlNrhZVxTj/MmAUuUTf w2mXX6JfLxwGq96I96gd8GLx7z7Ky0j7MmW+GHj/Sfd1G1h48Bkof6oYfQPb0jl9ft9a0J6ykelD pHOuBMQgZkisbY6E3fGqQPSyzRcXKlaDsmLsQpQQniN3q61+d+Kz2ThrAEtmJcAuQWLtLyBOeMZS 489L8v6Q6GyQhvBp8Gubki3h1US4Hsr+rxTs7j4ETSKYA+WVU6/CbCN6Qk2pzZxbUchS4hol70PR MFb8ILXc3AlHYgdD4B6SgW9y01uSEepHXGe64ezLwrzu/AubiDxihuyklWGkOMa41iHZCh6r+m/7 wRrIMCrwQ9eFA7jychf7+2inA2rHBdiGNuA9ofAdhJ+v9ocDdGdKtrNvXAJ1tXbuszR+Qc7YHAe4 mcYFfD7hZ4HudX7IAFKKbVm3dTRVpXoj97jISByfsVbun3+bLluwZzjbu65GPkN8jX9KnXVQPH5z RfY29E0LS1Dnx8qsAWQ/P5xKTIFphEucQ2LGXurOgWt/TCqL26bJ76Rv9mWegjVeBSBZ2USmGCQH H4NBd4ZOdSinJy8tQ2yDlc2WSPDzP+BFHUuqhnDUsYMPxGpKpobDGExMQlG1jjm7eBEB79HkVbtC KpQJU2TB99JshEkOYfYLvtLbHONk+d1rHGgmPwXGC7JuBKi9O+uI7KRtNK98nHryhW4lyuukn1Oa L+lOBPKpJaiw7AoF7jz9baqcSASzp6tmjNTrZZRT5isp3voynvrV+7EmmF5Idl9zegqnUh+ZHKwN zeDxcFV+NKSjS8STHizpzMwLlfbkl8B9QKeD06tXxF1fhtVgPUS0NIsW5fS49GB2v1IrJtK27OWJ VF4mO9AIxs6Ai+uoReiWi0QmTvCf9d05ITT/yc2gGWDj+NT1H2oExz30zrb3Rs2Fcb3D1ou4U6cm BqX20C2vfsVa9NkWXibm+YCchljsYmvt8UVFLBGrPgvo8GgL8ZTeRRM+Sw+/oTHUEcgYGrDmKTeS hsHLHCzpvyhWrpF5nNGsgqGpZ+OLE44hd4FOS9rCe0fXA3/VMiRLMRMxIpAqhw0ofYLVG7jUe82k s6gnzJ8m0nUwosHsZ5jHyQ9hGo3A/YJCyFjbDxuYWjDOdegey7sEcZSD8aFEDgt3sqtra83l+j6i 72TCT2Hcuni2frlruqxwOxOo7rEaegZuUlzsigVWDmRwIzEDnfNC5K20QWimi5eEjj4gw9K5IF2P M0zh5yS+QBPxu8MrGcjbXIJDpxc30lvEbXxEslXMPxfqv90xh9pMD3msejyNFCX9GKiAu71HErih H+pYcqzt0gf31OJjH5NYCglB0y99zFOcGhxGAzUuvqJjlXderrCz5of2XpJXPBmBJtcsRFlfkil/ D+RGyyyWChCoPdi81Uq3qUF1A5R6B6Gt7A88bn2JCfb3r8zD48EW02itxjFJ78slvAyvxx0o3z00 LsBihmZ+AZgr9D5jA+VkadqLdsFgVppjbGils65tGR5gDTtv7kMHH1fAGsrauqr1y5wJSuS5C/AO dly/InDzNBB/+Kc/e1EcNFpm2/zzh0ad9XJN9f0CuZmE1z79FpO9v7G20JosHl23v/jp1rvAgDE9 cHrC9z24/Rv7dQTW15dbRMcFvWweXBCsJ+6ad0UzJPVwLlYyAjm3M2BrxkCe0YjgAwYK8d6phF1o 2URxaRoC9ZH5Bk1uiehugRtS1F3jLHmVhtP6LrApxWO+mMR6nA1IBh7tAgnz3yTXrUIWNawFfZmq QH2mW5hOcdgB3TT0LvoYuIhqB87i8csw9m3I5fhkSdNu+s3BNc/kV6U3mjIHbV743uUvw0VtlX29 eZqKWdppzXcAc07LoOlDzMBDPKY3Dd/HamT4A67AoM2clKv8K2GCChgfeq5TnFT1oFLOuqTpoyjf RBjri8u2FxvByf7Msp55sM6jzYCm24tmRMFdYHnmR1xeV80QIFqngwywcxrgESB19pApd7hYvBF1 s6XgGLwDpe3VIzl8DsT8JN5IPtwRxmD0XXrK7iIuF2adrJiUEwWNKaRGNcGGsMajNj9NxPtrd/7O sH/knUcvgyVfJZN30QC1HUhotDvVOPD3Ht8puFuPp47jafteKES2ha7D4ZIudkmYqqq2QLuW7BpB cwDwbKp8RK057j9JMcwDiSXRvYR+2k9TPg8kPRbTiJHqh9Ne8JaW98jaAAP4n78Rd4jk6N0cZSm3 X/Latt7mptXAdt1tQsWaK+5rk4bz4hkYv/5SAwWczivhAlSd0tYCKD9b97caxALa07ah5b7TY0kq wl+CvXW7fv9w0vttox3lFzSnt3EaMhPu61XCKOR1bmcAMPu3mPfHE3WZgTXIxfIRkid4YW276/p/ mzFrpdVl5Sbd+8S+Hwp7j6YH7tYZFoNdqBNaQDl6EzWB3z70gi3iiwZw2Ee8HPbKhEgsmwHEP9yk uakFK+BCLr1QyznZWt+56/7bTbLz77X43BWgM/OKVtxsOT/S1nzF+zNrbqo9wuqIW5hHbmq8+YEq voArmNMkOhiYOT677NiVNrX0C7okTemNctarSLgP4jzicv0FTztPTXDXTIL9tY7XX/rPubQcUZdY DEeWerTM9TOCNEdytbIjVKp0zQja4lt+cS99vcI26l24e7cVH1v5RNrvm3A/lL7++h0+2vIjlyh0 UxzFrlcOfJab+kLI1BzLi7RW/FPyj9Ky1xgPhpAYK8o6c8tj04HPh0ZagXlDYv9wE8vFRMrlRLB7 Pczck65N74PizfnHj4tBTizMOu46y8mBnr9Au4nf3rzD36T+eTpZFvwG1Jb3Vy3JAoytYwzK/sC3 wRb0r40Di8OllomQtIeNKv6+o004nKViFODGlRYVPqB/vGhAtKo6qA1it1houhq9pzSVV05p/WUV 07IC3EQGsgu+ERsZjqwqvtpm/cmUZtxix2F7RQiW+RZhKqZ7JIpqfqdwCq5t12ZaBCaqucUC/Dfy Tx3kxJPJAUs9jccVZ9YvtbKdNY4c4iDJYdt94Nvmh3v60eXdinFfCU05YVGXMVvAdTV5ylueVXGS 5FeWsglimgcK9YfJy6oqk95tqgAw1EazyCPcd37F0Sq+7QSJBuK9ev3lV1Fpa8hd3rdpnzYAWU5j wGTMHwJA7rFFwJPtDINGsfttloHNplMWPJjHsbBM2CA7cly0jj7C3yYyOCIJPPLOZmqZk0W84sQY bUEZ/tQi2bYHgzKZNnYR84EW0POjIywfoe1+Q53xKlCm4pfXnhJr+EcHY/CTegHy64eGbf4V39c5 v9NXDvBKUw3evYhsbQRDMZTzLLrSDShKx345KPNGr0LPZHuoae5zxTKe4N0GimnpItCifH2kbgVv Er0u8kikb/LEMphRvmNSGSWHCdzPrTDMrjaKuB+qxxPV20WTJ8HVr6reB2OhugWKm2eIa53abdfo PcL0bqQTF50k3dOCkV3tqv7tjxN4xegPEIB6LquGR/CLxmB5vtvjnHeXtWMxXWT96ezjLtfn1G3W qKbCGCZDUcpgpbQcEDO4h/Nl3QheELFjIo9TjI4N39ooA726nlh6BV21zoy5sA/qt1y6t3phXyoi tqiLxTTeUclcNfrJvO56laDIVYc6fZhGxwBFVHqz3lxxDKE3sygsaHz17zDSa0vw7xZUVlo4n3nT xftWptXr1gqAnNSsJD9Z32QfSzXqk4IwZLrd9n660Sb5TzPiyFxgOS+4SIet1o47jWDhn5UWTH2P z19feaP32VOff8r3q3zFdg/vS5IjdE53IDAF0nUMvjvYEICGX3WxdWBm5643c6tdEGz4etChpcQN 902FBlxtkI5twhi9tIYUdpGR3tuQUNKkWqUrfCVoJuvX05EyWBJyOCqU+6D9oNWxpTD/hkg49zIH kEXvLe9VIH2ms4RB9IIeLIluF0z7fGsJFOD9h2S7sXCP9GDzX3Z+WSQIejXPNORSTnMDOC+NnQ49 kBGt9R+e5WMY1B6ZBBiOAI9h1SSqNNk1ooh5mlXhCIZvSiIrBcncML3KK3jMmTBiMpDtxHt6yX8S medBp7HkvjOnZAaK0ty86pVE5zSUhwsgMLlFicy9bDEQU0BNgVS+SsA+DNeXIRcZb7yPxGD664FM ++71a/nBpMEsQuDsvQA52DYppes29cage8rCIaDkSGFjos5cEddrUvX2LcvNFMrp+R9BnVpTMlH/ MwuHzZUCGx3nWLdrBl/gr8vNk7RkmMJgBxXrIg9BAu0ZcwijXHk78zOYuTIclIq4dTQv+nqRFVQY VLdIZy8LOgPF7/8WhkhUIPTKnMtiXVzhTqzjldM/wxOAM8/vNsPjxhhxUQAycvM/6BTqQt2/yz5d aw5CoVl24j9adpXnGlXwJFwik4t/y3NcEOfLhHjMJK5GsMZY2FdXSdXsFnbJ5J4HTnLdL8gJlvjO 8VszMng24Nb8Dy3CwZIgTqxSWPCBOAAjuCtsyIXbiKzH6yCb8UfANY5Btjivl3Wun0NvfgFj1RTq gh8VlbUrGngFWi0dboPkGvB7l4pMHVOlnNeuVYBKUhumVUeyNAVVSS5G8TRnVVHnD+b7/aJkLCkJ n51bHdIb3KRUuahp8SC1hmjzZqWMe+2qHusGdqCnRWsiO17peRmGuV3I/R2f2VjeluTD6JsN1gio uDZ9hu4+i/M/SywFeUD5zxOXHsZfhS9Io0sRLDs63Em6846Y/EidT6y/TI6F9Eihiy0BM9MF7Mt3 scczHOt5IsHX+2KCS9fVGzWiQpjrq51WhvHXRy1OCQASOJQ1OjmKl7+NC7HH2lZlLzMJcseOlMXu gMtpdqQ1HKIkDYbXvnI6S0cKC2fDXjlQNdUtLt6L/2f8W2l5cYBJ5KKYzFViDdBgEcFSQyJ/uCX/ 9nXNdBM4sISnwLShvqUEA5EIW+0RVM81jRwG/MmXNjo33ZVvG5aAzY2F8nwg2obZtCr4UPD9nEWW NLRpCGVDZHn0YnAXOPhClxoLcKaxtEwBUUq89+QGp3k1iEMElbQKaqfsoy+iMhPTIzx2nafh5FCi 9iMcVJP7jQ3C26QlKihkEMH4SRREV5SD7RYakIkp6G23XNTHu5WsWRnW9bWJpsjgOQcFe6fwulTF 0I1Mgft+d9nP0FQIBORnRTav8Lt+DFckioomAsAMj1v6j0FfqMyY6pWRBHky9NMoT/oxTTX/vJhc eHG8IMGvLXh4YbNoF5zKM4JLCHL+ABsqSifnXx50ycdeme5G2o81BOrjdvJCNmEuUsypOpiiMr4T wFJUWzAWoekunbSsA3lNjF5hiQ1nLzT6dgdRpbiWaL9kq2aSMj6U7MuY5hcJ0s4abrHSDGGaNKkW Q2rH8THEgJnfll3SSgIlyrybMtJ+b65SgNFGQf9SkT4w9IFRmrBo50o63PLhk3qrjfHc99QeNaPG BFGt7Xt4WlXIFcklv0+0e/4Qf5+k1uoC8uZ0jww7woWfNg3UEykuppYYUYaNONNOeVdEOfQ40hGW UL3fxKERSzfQ6+/yWez60qmrpgmy2bWTcIuTVmU5ALt147kmKBdX7xC71fuKni10CPQUToDtrc5U Lg7pFITn60rj4RefXkUppx2r7YtD7fGvUVPZ8m+vQgdWBOroN3VeiB2hHo0wlCleqTnESbi7h40R fHn3saqlARdg2vVXaNK8gSuGIHMCSQFUe80bdA+q/OMX3IseqixGLew7rLxG86jj3X+VFwH4fg/2 Kj5JyCi/zNb6avZ8yhQmkg9uYtjog1HDHPbwsZWMIWkfvvEsUgPEs4bWwVk7egui/5uFbdc1QE/w kS4LgZ7N3lB9oi+nCcB4TniSztwPpZNHGcYw1f0JJM0FqwgeBtCK06VKRZWfnGmaZmWM+cDIfMXh Lsdtymu+tkqXWHx4jLFHEwWyyVeHD+z325AM4aCKQaIkfO4Yk9ZLUxIWwGDYGsFFwNFd43qIdcmZ a4RV1k4jkZGXAeXunzAf2j61VrrgCA3MMdU7OD6MtOivJuC34w85YvEUL3PCJPtMGkIYtfGUA6NX 2xYUFyz9fVi9Peepvyhn/w9E+tCV2vnzU7M8RH+OCMhwoTOMWTiZ34SHwbUiH5xMqBzr/DQb0dO7 CJdUA3/Pv6sbv6XGGV/Qn5vaOBMUoRizm3k7zjx1bcbyUPM6FyCzBgTmfQtuLiykhus39N8pnl2f Y8hQoVswQbCB3V3AIO2yiNBG3vHNj/hKattZQyA7XIEVdXgvIz8c4kNZbzy52WZ5gkrhp7EKuTqe hC4Qb9mOKY+s44GutzipATKyxM6Yvj0ELO0JH5yItSSnMReyH/mgTafKYYtk13JXleyUFKRAOMT+ NC/GoB6XoBh2yIHeQMH+HhankurNBYQ0kw9LyD5baQ7ijzv6Vyoa4iNo+5wHgRQ/zy+XQK0az0tG hxkEvEjajfm+vsorw2EoZbuubur0cuoHrgwUiWA8UOpGCGL49DKWpCnH4FPM0Tlc9wkC1MtIqngF wbUt02FiMdW6ilhK6rZa6I4rOGAOp5L+NXrcB5hwZSCbZu6ltz/RpRqfWTuRZLDIUOQ1NKUi/KtU 885K2SxdloNx1uCld4h1taoEH5OzpykSnNq5L46WZRGzSDJouA2mq0o8MNrmgvg23MBBXEJMNP8z OpV9PW7PI0Hg12jKya9NKig0ETGuqzUBbCworuaaJRnHPCCI13jC2mfRuIrP0krzXhwSNv9b3CCm zFtnOli50V/WnWzuOxsNFIR4tMBmpitYDn/nH5byTIyRl0XoFXaIHY8pXwkWQNPU5et04chx6xWO VVzkKjqSVg+OYqHoG6LB5dgtV7SVi9cCOJMmP1/kaUh0Hdgg8Xy8xLOYy+eqaDGvHBn0sb7wlcuE Q1kbKM51MKiiHmJ6LNXfUJqGSVe26JIN7Q3kjHfN9+J4Ivcn2X8pPWJ/HjCj0eKBTS2FAn6zzo0G rzSPqwlgSJFRZgOP9N+2S6DTNCl6wilJM+mnBXBvt32UtDQv2syc/+6UfqJAN0e+9lryNU94fZOp fXq1qZ4zMA3Q7BHkwj0Ju2mlBIWOpOQoeLm6R7M7mPDa4TCeFnSLz6/RA+xDkhZjJlrVHaicvGD4 bLUAmqcKZkLRuPxv72CsaL8exZd0mFldvtf8Y65wMjSIdPZXaC/P3OugLdo3UlYsp/GVtkyh3V3y B5BRHXqDawp/78O6WgKlp5UDeZ3S3SNocVBASqagWlNdCcZXFt8QBkho+nlqjsbu4UZ3WPer8Zju cU0ruTG3a+4hw1+87pJBTo+Wu07sSgJn2byCCZ9o2RpRBQrDD3cFx8ZcXU4Jx2fNGaB/5lBXe/lq ieYZ8os2rwulEY++IQw/Y3xf47mEWrpGN/jc8vvQA1FGnBQiIgq00Rbwa6q7fLqWwCh1GnD8dNi+ Wd4CCx2FT+bNFcrJ5R4mDoKUnQMFVNWi/Ab9icd20uzCtR4PkJABfOM3z4su4vdaTAcGFtr1CpBE FdeP4HNsookj5qGIsFZcKqWoh5eYu/dmI9zhX3CndHXU3/xKCGuK4ADCLVOdZ2cF76ZQ/gcEy9jU f5dw0J5s1sYUjM93rWxtKl8H6FNypWE8OW9Q/ap0zTU+bKqHRV9mx9hTrn7AtfuOIutic0DejzlT IfR/UMY4FlE5LfVNKsg4S5IUySbfpIenXLjf/47ipiZ5hM0vRqJWZThM7yjv6Yc825VG+ZG0FoYb sOde3b8c2e6yV+5/pxK2h/9dcBURoX5vyVd7ratqZJinAJR7nwWrPymzlIi/EeIhw/VIkjiOwiu2 G1p+XySanIEPgWLuF4H5q3jvVCNpCs9GPmE0LlGNpB6O5JLbmX1CsqSlfX16MenbOysOOJZQvrwn eJAi/w22wbDvUl9dJlx/i0iLezxp3kraKexTclpnQHNuikv1vPejDAxaMf3fPpJjtF91EyI2Vg7n Jo8UC11NG06gBl2BMMLjp91qN6JmklFSiszXZVHTJxQFJoYELBdBm0p2AkEqerdDT9NdwQyKCICs q41mSOWjYVOVvoV26jYy+qzzbn5aLkKI6WvZANxW/rL7h8XQdoAf8ZH1tdifpeyAOARp17CBi8se MZzSPvizGfiuiPiThkjMXvatfzA8XR3p0JXwINBQFpiZaA3cgxE163yW2WVOQrF6LBFOml0xC9Ny pzFAZxCVZom642gRRtCj0bOOSJrao+OmeM8EaFULj76kCGGxgPsdlzuA8PBJMz8AMHyByxTcyU2C vqS4BPQr/hNfaMJh3IArKe2sZBCOSwlNamhwTiOt5Eb3xE6UST2rRsPZwsNVOwxnPM2k1RTh2ArZ ne2HZttRpvLia0nzEryI9G/ypiRpyuoQQPgcsfzE1FQ8QMnZegdL1hPKj4ah97cBR8pp0N7IkQgz nR8K/HtNg99hEqBGvfwdOmv6uWw+IxTCPhL/kn7yc+0BtCrC3kz9eGpav03D+WNyyVXnXy6g6tmS iMpiS+LKixG0ZvJ+ltNBs2BEqM9vxq4ieMOVCq9+TKkcB8F/zEs47Mz+Rgiy/uW0F4Hli6tux04c abv1+LHcCcRxCb4k5jsoi9icHyLbe3hHnMvqswfgZ4ZZlUcF7dadb7+SZvfKzlulRGaDmRO40WMg tqrMXHyhDzx6nnqjV5Wl9mDx6ZycBgatgS2NV4XRlNADmNJZzDSy8/dGjRe5yjnFlvBbqVGUvkGw BbgZRLIvBJh/jU9baSi07gLJeItPgbZdx31zC4UXPiowUJu9PLpaRBfWrOgirT7lMJE1QJdyFVNr C7dyZ96eIb+cCfeh+2SW8PHFl5+qaWtBYCkVc1kjwW0ZXBs5UlDloRRbZVIdBWlR12PZcaA1r9RN CHS3cZ8QqY/I1nqQoBvVJmZAIrR2ivDwi+kutVy7ibJCh1IUB6wVlCpUQsI4TI/kbUR8zOmpx7lc dnKEEBpG87Ur1yImfx9mno7YqaAbQxK6Qc1zHGP/seTfb6B1QX9wCseuJkyRsbvFTlX+7wUUEqOC PGCRh5OWqy6+6QwmweckLc59tzv+z5+kpLBpf+Qy+MXvsFD1ERwCpGbFtG094NYJH5R7qwiC02mQ OvLVuQTuWEK6wNfvQheo9Zh7m7iQ5K9rVMuknVvZtqoSclxmzTmyLuMCsBewCdRDoOhW6tWvZYin C9bV4aVLuEQpPaV2LtWOD+eUSYXGjlJh7bQiYdh3G4xXTImCLXUOUZNdGMty0ZSTg6MJEDPjMYCd u8egHbwe6X74wXOuppb96f7j2xXwqrs6LaXVQ4OGnqurKylP3rpz/njv1KpPRyqltFutKG+rsooC mzFG9Je3qJp8xEa+YlR383WGSnnk94QPp70xjItuQvJLLrSXgUYihJXug4o/MvBXbzFFG86/0bD5 8AjBheUheVVA2xQw9LCduHKKzqQ+2B5uK6RBP5Kawivf40EG7NH6MbaQpIExSW9hsrlB3E9MEbLq IItbb5sMgXGxQgG6MfScfsgU47WMyfPB6WGU3F1OWI6FiX0cbwlehCnwjPzZGh3aESMlUvSKYztF +yr4SLcIkL5TMf5V6+dBsy6QVXq6V+9qh8xJWStXSLNzbC6lQkrtiXtTbyezTlm1+7t6PQSIRoXg bquLHyehPGrKz76UU/exyck2ljZpsVM0Z+Q1bKKNcDswQbdQ3tWDo1kNgy3fxVIkBYW/QFG9Ta+H VKRhznZMf2dGzD+EbBLWOa+0uGfGGugFpdPG1IJnzeLjmI+n7fhb/0wT5/YfZ1ZvK9c6d1emaBp9 hNiMw95X8x6RAukJt1yrJkOPi0BEqiA2oTfZmWkPWmltwOi9wDgozGmwF3n66tbSb7++BMtQXR0z GkfsmObttqt0xpCVgS60w9SrN117kOlzDJmYGqMrL3aurNxQtfjZoHW7F2PtWwwPcAmq+aqmpePV /CrOakzaL1+OC8UDCsHNGzerVV+Jy3ix6H9sMPDU67ej0KZBO1fBmyvt718L0VpATOz7hGAPnB1I VvMXjYdobLlVU6XWQKajG3f85qtdu+S0fY8LNkZDw50BbLWxX5GO72nclh48MeOGf/Xlvh527xyn 2LEoIEiSMRSuAvcd1aio6QputLvfWX/CmC0xEJmDbu62+JLQJyCirb4xyxkjFeQ8I+YgVtaJ0pSs a86lGqnwuoMEXs16J5JSfgbCEaMef7MSinx0X7LEWwnD6mBkoNTEBtXz/4TB+KpdamApsFTkTR7Y QXNnxVze5ewkR7u0rQBwvDVmfP/LWlkTu/TGI+zmDNV64/4fi2/zY79oVRL+OB8YfY/khAe8QlpZ 6YTqWcCG8X7Eq6zzpw3tLu80PIbkctSP1sxU17VIKSr5ALKzm/JF4L6zE1RQ9D6wlin6sQxdizqm RgkJhbhssXATlJrZOQLwpciKc4LRBzqwA7pAAJWeTG5lSToZDxKuJcNoYXKxlHvRr/FyiuCWyv3B 95SKb/zETXqUGz2awrqfuu2WIKq0VNhvdgnZCcqge4xhm1r7NSBEJdDY29/GLZH5s8k4WgmNBM+U fS12iyTUz7BSJ3zZ6/s/nnyoNLG9ePspfgZCFGii+IaUwDKCXLvYvu+VSellXeYKYQszImbz1n84 6HKP8GFDBjVlW1FuxVHUpsI6xxrNKPDnA7rSct1rdPWogg/KW203zzj1fVWbLWoaPwTci5gWIQB2 4JsiM/Yb3QzHkkY27t0EXElKRVjb92KiqOcVhdcE5ejBOT5b7XLhCkrY3o1uJLsmJxscjAShxHlF Oo8uofu3WF5wSiws02f4THNqCVmzxi7bUaCh/KImSLKPuyc/TblsHxGO17ktFFSzs12OxeOfzvOB QTEXvDfMQUJYLrrnmKWv713mOfbeI4xUynmEQYvqBkh+jrtd+KykpgufU0Q8iprYP5u0w8vsY8Hn idv+WVnc0pNPAIEhaWnLScXz/a6/fxTAzYxvD99CKcdXzQhFlKu6fpGxdj8g4p3gJUOWSSvFYTdg Kc5L0ac4RkNzxoke/3kp/Y3z1Cb5EMt6A1YGBXOhpIYpgdqhwag1mejz1SdhbaxxrxbmjlVEUwt2 wwLnqli6MS0j/wS4LkVNG36fN5FI3w78YAWB/M1FFFVLOUFP7s91EEP23ZeX2JyZsTfJpgCdS1Uu 7J2mvh2DFMO4vxwCmXyq0wGqnodFtwuc/9vzQrWCVTi3Y5Q1cQB1mciVq/86BXDg6Bgm6f+sp1pl Pq6gPJzaOsY07M82oAPS+Q18eJvOdJ2TLZgujMPC/69J8yu/yXRQeJ3zgC7AzRQ1E5sBr9u0VCEo hCpSa3i/AVpFGiWMgEF5zlF1bphdpTLivZSmnsLI3IYSYaguP3/zl8UhPb4NImYRBgqI6sV9BDDp woh+4Zed5h8f3Cn9wsGfmb4kfChCxTuPWSzX8Vp58NNcZ0r8vdBEcaewNT1QCdM67Q5mdnrX/7Zk yG9QkzwEehxdFZzGxUTNGjZEgThYAOLvFrzrwEm76uDb/SOduXpZGyiXQh6jJk/n4ExNqQUpE5lw 6LZ1/nhAsGsatUEB+Ye5J7U7oqpJisOshLwz+cuCGZOB0ccy5wNQtmdJkK3BWnhk4DFCn0mfN0YB w/2ngQ1nwAJokqDpACN5mF5Ks34fSeEcDEpBquN36rAm6PTp+dia9B032qYNH9K33It39yWJLydn CqR7ulJm39E1Vh6ros8E5kPHTcu7PdDmtdMahGTSalDtxRjWheCne2b80QIErTgxvq+P6GB7Az3k HhHSO8oDNdbzQD37VPvQhMIvxjtyxSzJdjUMtkF8YedNn/O7oByDATQWFdPfsRNv5NXG7PDgV6Mj sttSaamDV+8xVJ6bZTytxjJoL8gR9GK9T4HpmaA6blX/12hRY2rC00gkb9u2NAG1zvUQoi3Mv0i+ LnyZ7wy2SLKvB9bbXvaixCMCpHFNOdSP/G4PJwDnx1RHg+E9up8YjkN1wsWiqVpHMTevrbuUqMxs uGvYzKoxn+CZkNFAClvl3sFEcdtBWGnTA9kVqMcJAhT41ThzN7UltTOfkTBlgqQK5hiyVrObeY1G o3u7TnZgjFe2VoQQreYbvPhclFDmtpzu4GrIQqnxEUHuQ1E4TseFq2o2zzM2aVjQaOJtSxX0h0Zr GQJxqQlqQBAzHd5UwlHqHrDHVx3TRpVkxzLIvxWrrir7Q4SFhlOzCoQKqVpu0ytbSjU1Q3IEnj1J kmTJJt8OrpMXn1JmTJYK5ZQcCKjwCdICtSyc0g0ZJE/ruG+DQSIHG+7Rx9eJEl7VCS7GUjrqs/0u y+cCj+gWfsVBHyyB0biHQePANLfvuKnOQ6YBD0M1NpHhz3Y4U1a05xvjAOPS3pm3B+YnMvlsBwco 26X4/1odiGj9Jp/Y7XgvqOim08XZiytnQq2IYt2K4popQXl3UrBMLZq3c6VoCefV4M/c7q71p+Dq 8iLp0s36wSi6H+ZZWQ13vanq6qrSd23AW0rNofC9kHNVmSIOXssWeKsjYG0QJHicHXWCcy7JrRGz c/TVN8Z8hba/bztNGZ0/IOHLLjhLZVCFNtrZ3OdYk2L+zJtKaJyTy/qLynW3B2EibjBnoZgWsEFb kxyhtJZseXgU+RctdHFv+/CRB5qDtaYc4A04tkPYz1zuvjsG+dOWmgzoAF4wP2Ov3Lp1CzEJYieN NoP8uZMnVgBnz8HF3MMnWg6yuTI5hbt6ONsUXIgilTi5qmgZlmwy3qulhJaS70iBvbz82dSwtlh8 6CEDt6wbMa32oauriOcPUZahi4ifogFLlkaZW9L2wRSS0FfIM61cFFmFlYbxWRP/zUKWdhQ6RnIB +/s20etyeSNNx7nNkhgVnjR/niKZ+T2H9oUz/FNgbjRsTlCkkt+VJ0SsDfm34/WGyzKD88f1EVFi 4rdCej/ldOUntmUqqYp3C6UAgaC8gKzqTyU3hKxOziqabWDPXXM8mBTAanloQoElBwntp0ZjLfus A6gzelWAXk4+5rj3y+mpLtw9JNGGbnByhwoJQxyXOJUAlc47AvwZUVuxyYqlBGm9abBEZdu3GsnF /AsD8I8Qclom3CNxbf7dsSKlGws7INAkk9hVaIN9WyjjZ/+73MIBTbSHCtOGoI8TQwTmQ59DGUqt Wb+k4PEXE91hBFHznUNdiixjRgkjis4xvSueDfL5NKVcvzoHP2euA8ytRz6jfLHCPI5it+hBNP/g 3odTQiE4H/mhHmeX6gP5SuFeMFPSvLcd88vkwiKdsSE3bDrLFlPOLYKSE9MiStD/crWVULtTrZsF gNYPbkoli+8gx1jkECdkmPmrvg38hiFW7n8GJEREanHHqlI1OHvI/2RZ/5cyldd/2ZMyyo+w+9Vh 6bxJlonxwQ3/e+3TgX0/8dNrxEaCYvjBA0jKwOOgepHqkrZ8t8V5DWAhAUy9iKj4XnwvyKdAEYtT bgh+h9xhddjmY8lQ/aoZQzlkyWr6gPOIY6ZZ9F8jIORzZp1MVnlDiJi59uXUE3FM3/YrMV1d+T1h bQ0dmxnUbajJCiawaV1mfbr6JEtx/1GlAJv5liJJle4vxNj7OW4ddFzDUzBCclkeGViJoWMB+VHT 3AlAvc5jWq8snFQMzOou1PG0p6ma3j4Q4HO57Kzu8iWSrMc/MOXBLZx518/YfRkyJvNq4oqkPNWA xJ4506zqRHL+ZWPJNYXBJBpclX7brkXTI4qSz/br7jz9fNwuekvI+SIvnnhM+62IJSzFB6QA+LpP Ctm/IonumBHKEE/ASw0iqyUdQTEP3nafjkngNyd73+qbpi/JRnxOg1Jz+cYgKPRlr5vv0ZbxoPdA +rH58R5DbMy87HxCBA35e+FlsStHUd0MfqfWNLF9kifkY/JLaTTFH6OUayc3qcKRRG2+/F1GTvwH AbywjtUd0JeBU654P6/dXYjJRPIlLil6M+3EyeEH+2RrBtISp/84kOflLCZ10defFiWumE+h8tV/ JbgNtZCsZPmdqD/0EcI/N0ryV3LYrzCL//R7t/0TTeevNBQ1bJap6Am9TPIzjTv0V7BLHVlAt0hI /yz8lKB0Rj6U3sN/h7oIyXgOX3qbeZtTCV/Dte8BKKtz5YgITuX1I+W2i4sMyflPwYOPFSwmC8l7 II0H/a3SWUzb7qmi7DRueSTuYVl1Vwz5a/n7cBnsks4tvygwh/vBVsf/3klXJ3869sQF2bty7dUJ 9MWr1tWy2udQCV49C/IbSLvWZLHKI54sM0UaPYHBeyb5iEJnn3bYFKSpR4YPWQNTCWtrKV+cefyT MCJ/+83XfcCX63y0rguLYsPR38K63JxoqGqlamZytXkUnyijBp5HZVfh6NZi7y47rc+LLjz9kYWs YW+AFIxoPvzCoG7MxmQ1rStnAZ44750wTUKt1NGzy5tknXljbKBTeB0nFRGvb0898QFUEmnWK9P6 0gzvJRgSyzg5La6b3d5Oc4AEuvZ3VQSc0zmRuew47a57Gwa2EdvgSwI7NAPmD9l7br5Zhtdwvnbi hjPloKCVNJpRJygHABuHz7iJKuo5ikDO+kM0fKmc/6MkEQ0npTggJHw51SBeJl1gvhjTBQ86ptjr G6wZ58QUb+ccHk2+RG3cm86lP+R4UhwidMQb4J3dfQhO7/3gur5hNig9rs7aPANSHPULQYfin/TN WBb9gfI0v7OoBVFlonDgFA/aZybfTHL+1B9/rnB+koqJQ7ly5EYTViDejKWJ2iV6gPULDeGOmNu4 MP/+HrY/NWPEfx+piHpjb5Xsf3lHQvzOs3mZ+M093j3eOq60ptOtFzQTeZoGO5MElabC2Lk8VC4i UOuKT1xO17tmuqhUIIRyHNI2SdVgonhos5A7B9gNDtJDYjIUcydjXKBm6MdURMEwhVtuFGOCEkVw CPTXhNaw0gwfVIeeYavYJ/rzR5uiijGSUcbHtH0xHanT2OLsjF/sXRlGXMEqKjjuTtudEwkeRHjJ TiPKS/0FwDgC0VAEm5OqPZAkLsLwzL/BV7t+OfTDQj41Lndrri05b48q07XnkPMkRsMWeAHpEQhY oHt2TJx/oTE9Azw5LdYIyIBVyL3KPfgij6joyf9XIyQMdSAV27dWn2Tp6PEP+QtRW5Lc9tbNTZVC +6Yno3xx07yiRyfQYHmR/O/yYUxjIQq6nFTGVCJwhEdrv46NpH4/jMXsGDlZebOQehUrCpuStRTy 9GExw7u4VpIlXX51zzSXDs1INMtDEUEd/9rtqBnrc5KYqWUeI5nh5LGiXXEMaipHdZCnLL68LdbH 06gqeZI4zU9b4Nw8b0kG0A4F4IF5YiHed30AJfHxh3JsCe948Rs769N4lrsnnkpOrKLLpngrZCwO 68HigMiUtx6hFnlYr2UZsF33gnrr8AdjCDwFD8POEajENwrhFkBdVzuq8vOxYBYK8glPwkYYCm/+ JU7XxJctS6D0xNvpT7peVSSkM6/3B+YFXkW2oddY+N6iu0pZq7GLi5nMhKgoYhAZlVGDvAompvSc qtxhW9TjnxlzgOpvPFseXZPfAath/92mQOKtLg5J6Xwuujofa2+rS7ue/hSSiQMihixsWUS7y+1h EIrSbKQ+oKsM1Irg+fPBFFSE/wOIVUPs0ndubvephwm6KuTDiWNoWcgx8kOX9pk5Rdn22AnmAIZu hKsrBb0yQr1gXXoOT3tmF8zmIpgcOq8F9ZNzCqiGRDQpudqgkkG6PmNcJYiA0bbVhsWhJMZK8WK/ XDIC6ry9F8Id8QfHyPt0pl/fiEePtUcPF7IsBpJmHz3ERd/1FQcN6N7HTNW0ImxRqsG+p/nmG26M HbRVmC6I8E3C0dxgF3z+xLpBUIWKCKDV/k8Q8CnKrE4a6Lb6GoX+e3Om/zpy7fsqDZhH6GYZnty0 fIGdYmwkZCdjpzv+nXrZ5Xk6Dg3NAX5Gu/yprBKLTmDtso0LfEUTTujDfOYeO33DDFNq2+4jpxGu ApkPpdS1Xrkia6bU4o4rrqhMHzQ0FhDhRKgiZY3p6Hk8jehXqgPDxfk3eBHnDSIOOXD3qK/SKAWV HUzT6ubSd1l617u76DoDgd/pG2miz1ekqpsfCaXC78ZJH6/yrm59NvRVu7FbkKyi3aglK3k6Jgbz 4iE2rZ0yfu5qr71y85J4vI9F38PlhYtFARJYNznZMAmR6WGuDzcrBbrGyQ77fNpq1GziYWlxHiCG RpodgJwKFm0CMAy4uRuZ/Z1yFI7z97eTsRJOsm0/iWa02Vq6peY6OpDJUPb3D+P2VBBPwx5Xpyo8 VGTFH9RXx9UzH1uNEk4qkjBzyYkr8M29G503AT2kKtzVxADeuqehDaBfThkdsWmN9JZDmflSCW6S fMAGqP/AWLIdMk63J0KffU8WnbdPAYFgObrXPAw3kMstEWVFkRA1IcjBe8ZZMF3r0kql+9d1MV9Z pa2yzWcI76hij6S3A4Q8f2Cdi5MHK7BTalCr/awarbOFGsnqo4doNr3UK1iwgMtC+xA3Za55Czft pNV2nmr4Uxfm3PRLGEnZqgWlDMD6LVjn3TgZkt06Izp+VEq1XVMgcKWMPe/udgJAvyP8sYKibAJw 73tRWUbS8hVlKdkz7yIW/Hl44fA5He3EmfcMNEZzn9gxvSiUmbsygrwJoSi9JVfx4gnAKZyROSku NcIjj2pjrYcvTOq+xoy81KNtdSlXNMcjRAD2PDuN6RqEnXbGpr6V9QDS0Z6m4J1M4hSYquoXOG2v P5BScjT/wlyYxxY8lEWFi5PoJhbfbpEfEYdIVKPpMcPEEp4RGyBEhQbSHehOAMte+81j7Ys7j3DH mH0+cZn8ysnXN5PFpp2kM/048Lu2qyCgx+R68qaRNsB7AohlSTCHaKtl0vpsehf2oT0cHzMg3ueg NJJ4d2PsXMqbHkWqLrtZBgphvGLLEIHXNtVosV1a09XjaM/k2lS41wX0ALwVSmgwDGbWBXz69l5/ si9pq9xiagvtEGvyVh9jimJCznZRzmuHLH9IVImOOIWrKXOQ+Z1a5Wgq7yhC9/hmXuIIFdxkoudT ovkedypxdKSnwINx2jHrdXpPpvDR6FUdaRfgyGrSb6NgcL0owWesdNuP6H4jBK+fFMyF5yQkAqw9 3G8b7ioovnMPZPXTOvxsoMujx395Cy8yM9vCp/rxMnkD5c6mCrZpK1zSEMR5RFuH9ruaGfXrghvr 2mTZUu4zDaIGV6VLAEcjGcKrWGr1JPyE94MwUqkehhSNJj6dT9hvC7RCFC/AYwiSZkqvAlFLbc5Y O3F/RX12emJEzpfcCKtj+rERuLg+y9QaEOkhI+2dqxodwYZWokK+ZBHODWw5CCxNKsgRlVLUgqI7 KpPs67HYKXA8sC3uMbb5b4xkxg0Tj16mdtcGTktmWVNsDfwJuZkmORGXNRsLOCnTtM5XYqNY7zsH +tJcU5pgrdPygZtblEbqkQY3uIfTyRiHyMsNtVZZETIm+Orx52Ls8/zk48wP9iqE1EnwuHXA40t+ 9z83XgxHAZzhZxAckTxK4k+Qrd2O/uNx2dW0yYE/n423CBR/o3y/hrWArtIK5J3GuRLbdW2Z7IrK M4k4A2snY6sB6fiWNX4Cth+VSSOxScRKzV9bjLJHgndQrLIhYUyi8HJcZ3jWLllGhCfgFws27z2b CzHCu4jmmH5b5Dz76UWfpEWeuPd8VdOP9vtlYZNxvg8CDQrfIb9rQOOuzSPluVkqNCClOCm21EhF iBfjaqCy0W3S2vVxCieGwrvk5gNHnwV2iWssbO5AK/M/D/uEG17fXPTm1nW+qcZbGxt+/Upkz/YY iRGNKTQUm9JAZdy1fpQ1Nh8QkgjiFZMO7G3w61xDDvcFsKeYt5wiTH1Zkm9091rgntiwV/y/Yk5r icBWNg48QjVor7BF7Q4TZy6XfhSwxa+9PWbtmP9gu4kpKTMWoA1WnwcrimcWhPyJ36G+5DE7mffO 8OTzqiVsHA5xSrmKL6mwWO6Y1lcijOJWv/RaOyoDmzJrwckOtK6lq9GGQNvcR4R5nQzsb4ys174g 6VuaB1PN+A4uRElIXPah2P0xUs4N7dFffr4snNFf0+tIn+0aUVPbm7F7MWGCE4MRQx6B8bQpf+DV hrJCE67Wsx+D1gazIXifyhtUQTBQjRTNsIzRXHXkqF9sZwaJ2dMdSsVRYRU5QL5oKNtlRR1skdaY flITyaju8VXQ9ygbOI18NiSF/MN746NpGoIV5Z9/z9WbjX0vLCetKfVfDDyHFOd9PeHQLyRtJTMR 1xNV40u1D20w+tKeG9eP4ndjkJ4wQ0LUkDvrF2uUAL1r5wh6vqFHbT8DWz/jAYBZd1ErqaLkubkV mpP14rCo1B75oRnXpL5hSPByWu5TnUiP6qMtsiSvtX4AY92L/afgOPRn2/6dtNs6iKt7ZSGJdq2M Y6CtDYUol8q3FLuw/GS97u41JENIWbY+fTzWGXO3d2/NBKiPD5lMw72DcEdl4GCwA/gr+aTY7xB2 YN2rVU8+L6XVfDcAoqORjVbDwC71xyzyyvd5mfOT88i7HotV3RHl13TCtazqpv8BYjz1cNrcXvsP j/6Eg0ixoZbvSKpUQ2OB3oK8MbbbUxtXFErGC/V3IkUtD97Lt9hf96Q0crKdUt83en46mKCMArcl KY7mmqgsDOTqVw/KIVJk73Iee+vVQSqeYrEUjKhPspuTwCmJM/75ZiODiYZciRiBSH74oZRms9eb hCULNhx3wj3Nc/uI6cYaz96/J/xiM+FD5pIgiSagPZZAFbGf0ixWBk2VylqUgk2ZCvIC4Vwi6dZT quEeg61kiMLxBjmJ9Vbz1MhAkKp61VJFiwyUJ33MFqRA4WhHgdqjWoYDGxuXFnN3SBydjgvduaEd ih715QUnsw5y9/FHTqA5Ak57/dBVIcZioBcSvR7KiMfhsRKjcSqGRChqNcyIEg2V2M4g2scPCTrs sF2GqJ/alyf4haQV0IPjeMuQn5uvolyEIBESM5xqXmf7pG7a7JexWdbeNTTVtokLbYOaaIysn29a szSOiC5VUzAeNRhcP3reyra6rjq0NhuhkT6tosTORNj1x9Ib+4yeuQlMk8jI685R4Pr7FswgmLsu ExgJ+0iE59a55JObBoBNDRI8hiEn+nz/iY60w1Ct3yOOd2DCC5BGZhCDhIFtczVzgPJWtY8T0Ney 8UJ48ZfGL9niavrWptyKvBF6CJCaDGwFr/mvca8nKWtiUftKBuxiNu2Wumx3d0DeMFpUYEYjCWJM mYyVEdX1FlI8MshcL08oxt14i8y5TgOJAnZw8JIvqVRvyZF/aHSQdvnjiuC2AbbL2BUsPOhmi9MM G8mHZaxgYY47ME5mOhdl6O9+bAi72ZgZntIVrxTVZrfVtIeBMKm+GQecsIVRHaCptbt+PTvatZPv EduUl9ED1n5XHDb+BTqHxoG8UHJuYiLyBZEDDQ+8m5b7nUjRzgR31FiN0lL9mUc6kGfTOim9FFBo lrPQjrdWlFqn1BHT4i48SsLVtqfxSfbjxy19z/N4X4GzGinljNe75bY9S7l1dAH/SDxx7qf89+qx gsc7+aVwADg/G2Z733J/2cqoi7sPBbHvzSI+9MES7yRp9hEONwgA5hXn19LLh8HWE+i5IIvBgNDQ risFxvIrqvS7yzTJmuGuySYiOpBabI4DWbca8NytL+/7NtEY7O+/7lf/YrMTyDUl/uu5h6fcuMj3 LWzlVBF33ZSlXtG0VVJ513bFbWOnInE3vp4JX6oMgwBDoShmcTPCRx5k6wl2M1UCrt8JnlTQnRyN DsSg0YTxmo1SvntcR3M/8Boi0LBodQeVBS5mghxPPXStq5ZP2NybfvgAqCy9M2yMssGigiHd2Fwt V5gxGYyIPhBMyhkCoqSZ4UZeRIvO+lnhCBRLNBWAM8AmygYmu7c3Co8T+h/5VHlO+Z3kgqLC1lBp eyIYbQeVPiL2M3f/b7+z8BfjlOBvT03/4C4v8qxQXMtkPZ9hgP4ZrGXjFR2x1zwMWVlHCgXxcnmq HAXINDIoPOg2A8Xip7f8+fuiykqBLdYYIRQFxuXu4F6nMvHEbtjahdoY9ZrZ2MXKZyEmp33/oIxb pJ1/QwwGTZNw/j7DhTq4+WeoWCysnNV6ZKVEMe8JpVrbP0IRBV5wnyZTPbZrg9AAUS4qs4DHXXk7 SZPCcnwkW6S7u6LS3FD+EW36k0OdJth2jLmgPpG1YQHKWr+eyVF+nuiBSPHuDEVvBTilxbU8U9WP OQKqFJ+XoXYjZiNe7L996J0237ys+1bn5SQM5ogVR0U2rQKMNlTFr5wvv0qJD6DlaN9bJwak+rDC GHdk2HovsJlEbULPOyrasxp/yyD8nnY+DhkODeY1FczlITxZaEVhFdDUCin/EBFSEUmmlPo4CStL mZGIG6lNGgLmj1xJuo57NQtVd/kKb4PHosqABiemV8DTkCD5a+gSggXrIA4qOaZJ1FK9HSHrpXbS /00R9ZQknh2V8yI+HmBT/NiTyrLwkrAaqpoJVPoiPBSCWxtuNcqwmnjTVDy5wXajL0fYfckz0fSg SiWWr3NQ2JFvvEcr9gJt5jzOzodoHf98zoNhsoWlQ+0N8uCllxW6yRfOCdVvRoYEQCsKeZTWLSW5 237YRKjgh2X1CQNZ5SHdXRyxPMfmfvIUsJ/O5uKkYfZp+eM/wkhnrvTTaaaDXrz1tDPXmSNl+lgb 1H8SDF8t4JtB+AWrc1XVW5erVIsMpElP5UqGYyKTwWTx7Tx3KdfdCpVdOlNj1/l6pfSDrCtkPS81 FCn9eOK5bw1HSiywTarg2B6w2dQSeU3hop7Kz2ox2YltmFz0/C4PtN3mYx/sawwvoZ8IXTiLKyp7 ZFoWVe+Lp0tMzck5EF4MYzY2lZmRV4s/snU9KorBhW9m/4ohrOVRR1OxDB8iARBzsBMTSCbsOWER GVu12aNgppJpD5IoO/50QlYooNL0YAGjliM+ZorTv+6pJpX4iWypbr8H/BDK5RnfRGtDcTRAC4oc NRqf2B03tO2LEPJM9nmObKpxFWbys6OOOackkkkIV4T7n5wvfK9xjuy9Md8NtkADZC2+J1GbPikg +divRD6X6N9yQCm2AHa1UMUWIHvwYZHDoQ4lG+FIDMqnNUZZt/gWPz7iZTFgjteLkt2iCT/w62g0 VfrL211VL1iXJvZyhc4ubSnSo0WqSH+1QNOFd8+o8JR2gyNxSUoEEaI9OKxyn7ZdDZmql9kne73C tTLSkbDG/zlPPIFuOvL2c3yYLK5lqHzvQbY1NygxxomWQeKOjlscELTgxdcDUxSvJPo7v/4LlmA8 vxuPdj8cF2RaIwRZ4QtFwXjv7jQUD3b3Z0myvcve71LupqfwW1J+pVkStt+oPKj5tiNeRrgtMzsP RK8p9strOXsGOfVm+xWCiRr+HEF3xeHCoH2do8BLCOjsPgB9LplCJJle8yhCW7Y+MCsrWiIQl7LX NOx4XeIvw/3Sa4iJbrIyto89cGPde/qdx0FV1YhKj5jmIhAJHuwmUnKnBhx2ICcGnX9kO+qxYHoo MQMdyU9ZpUMYff1I8+VyOI/YWEi+De0Hc4wJMe0hf/h2tK+EXL/rVUfpyn0+nhUkt0dXhj5Hl3YB Zv4koSfazRzcTcXf1KGXr+1Kp2zFHNu8ZOkLaHMkxFO8u9GYUijE7aE0jZ0JI0Lc/yDyZYG7oMZy rrEGK/D6/Umg2ZdLh0gRFz9dTAs/Ki8ETQYYsy17iP9rzL9a2NCFLl7IL1rPw6evAcNYItQzanxl HJCfrv8OVY43M1N69WOPAjKArRQLP9ZeWmZrCN8uHAbnp7Kr04EPAN9M3XMofzHanz9s0NBq/MeN z3shRxlZ33KRnAXuB4OGehE1kPBMOmyXnuztAJwAPEK1R7sXzRz1krw2KjhNWemLlbxNXsLESEjY J09+dWHfv/xjoUl6i6SIkfvg9hnJmDHoFtQsdsEYG4BHtSa3+5VPrSHjl4A9WJOxAwnB7/oQLJM8 7kDFWEtNhZ8+y7xyq/HP2A57CVBBHhWTZ6xWwq76558++hD4c/8J3Y9XlrG3jJF677SsvOc4Eoef KgIbmp3bfKDgit0WAhyL+KAr2PHwuNocLEClCDw2mbkUD94fXOaYC98n24mYK9CFpWN/19PU3Hc1 WPMRjQCx58beHkyXfoT5aKRu3LsHZ+/l12aZsn7rRFxfKcqrpQd41uZCTRmdyG25jrEloJWIdQGe t9lYFM7jO+3d20Tg3MBSLc7bmoMgDSjf7ST0pmbrHJpTGSR3Ir945L2RZ6pb3ZCdncurkNUe1LKn 7R/XR0G9kEqhQlJbEa/qPCyV0p2Uf2L9xHOoKawQvGDXy0fdjHDTlIi2PAPRqZ8PvQywEg+0t+sC 6VQceDEGaToVeSmRss3/FAQ9WuhxLjp5s7vt+Lwv3iIqho818UKIxs50nTdmg9pAsRv2Zxhgliij l/2plOpTocWuYebreYvAM12hcsr9QJvLfPZ1v1rEskHfA1kATu9cOLcq0Ke1AUDceqnWww8y0DFa xH9ruYacoOAPrMTe/OLCc9WvcrOLhjs4hWPEHs0Eyoe0G3QbpjRQzNKCeCvwq3V3bK7ZGVcTr3Hc YF6oyPeadqY3sk/DBKON01OvQZeF6HhNM9CIDt/HF0SovDoPjIvpwj9+WyOL2235EINetJbo5qEY 6EEaSCspBeA1F2npJBdKbZEo+fVpP/7vHGqVEAMRWkY+kR7qU9AQ31ZK+KxbQFOZ1EQqY5/zbrnP kFB1Jenaxu5TpWU0368z+sCfqHbLssxDs+UrziuyhfqKKcPfur32fu8jikAklPplKGwyy8VJ/xyp JkUj5R6WFaOb6EDwXyIjNArPWLnNS+J1M+L+t5x2nBdSXQqux20dCC+n+KNqNxTZfha1kcT9K+2f BENLIup8KF9ZvBTu2Luf0FyB37iWZ9JqgQgMqj3XQK5X5jTQSRAV4iCRUOUEL15ckMpNM2SkSaNS tbYOhV00E5z9Wncd008GLS6FDG+a6Z6dqXU4InKeEey9s3NjIJTyXzrBV0wKJe+luBc52C0m5HoO Zg5bs/Zm1Q6SBRpt38B48NZC0mGppF50NqhIVps8a7pI1lxGMbiVtewq/XMz/aXSZdu/eJywxlPC YtMwSPDKcIQaDnFpR+n5olIMrf8b4ZUjHBQU1Kd61vcThtCtPiexgZCjA/n+XefGDfZQrxsx1f4B SfYe/BtmxJft4f4v7rqAgipMsKUvIYkFZiORBdGnvAlCZs29+fe3ywAZ2fpzFJwruIk58rddQqGb UC7KrEFhlEhFCvWvJvjKxj/lNsvL6t3EwKahncJEmLx4YKZuyIxUPskNNfN0z/jEVLJ9gkIq911J 8o5IgbKWyIzFhxWZfq6bAYFNGeetTb1n1pKZzhpuKQo277yoAQNZzeczdt8ustXCxOOvyRPcfMYp Q/0bFoPwZGVVfrQN2tHwnmUkF0qZnLUa09ngrTCcui9bQDPwvjQgc8GTQQeT/43e44TY9QEzpmfG ElsZmAncdBk9K7amcGHnwvLvy9bGjJzSpTUA/UCHzbmKgm6KW4DVcdDa9FyrX2TRItbzJv0IzeAf 2Ug05Lyd5aXItoGgQEjxUtnsGCsrJRAjZqrhuGx9icLzcjpHB81ZAz9JxbYlKcUz+A54VmT2Znev Nu7pLA3J5dod7QppuHCPACZiSXgYi0+eoS+He/g/z3pu1EzJez/xYwA7F71j9eisXxSTrlTrMmK+ LoTK5YP8+Em+ABsda6UWu8/6vmgOsSPPiLk3kF6yz091jpjROIxeJwTPd1tEJp4XXX00HoVF2Ofl RSQaqsnnnb5kK/MqmHrvdqOI/JRe9QROVZnbUtqYFetZ274BPkRWT/wQeFji1jxHhA7nHY5Z2dla uU8F3NrzSGpVqWyiC46ve2GKQbB0gu1h6sKQqavTcG4g5TDzQsQhCGHAcLD8Y6osPzjPJ6iWxhYZ FUeIIdhYPFxs7UPlzI8ePFo3I+ZtlN5vQdyJrc4+eMNz+qhswcU0PYEI2ZijVD7LGjBGy3jruV/e cAuprBA8xc0FmUbt+5lVAEc3WS+a7yr9puV3VXubzkjWW+nrJgQFCXlcQm8Wi1JOac8SdZR1nLMB G2o+s+i/rkWS0FnG1WU+tVybmgpwS6hO5CRbCPTx2abgPcSPVo5x9QZnlR2JNurE8AxqH7vmC1Mu G3y7CidxEId9QX1I5QtOMw8XweBm8TtEhunU7Bh75H2gx/QqrwYguHRx1crEo5GQw09Y10Q26P9h nm05QcoHo249EffJLYnS6K4gXuwjSIfRsafeQLL1fc/qqF6OcCJ3ORIFX49VjzEH+chjLMOKhsTi IcpT3LQuGO7pXuek18NXfxrHuSDmFYe+WXen/WW6KxuMrd2EUOCosMruwwEK9QFzorf8N5xeFRF/ Hrc1Ft+QsJq6Ew/WpESpqlG0BpNHbs+BNpU+0QwktpJ7g87aC8/ebYCo5TZlFwYUJCfBgo4W+oui z3lDCk1yUAFAOl66yGxMaDcneDIuZN2yIODTvCpOzMgQ1tfzUTw70qsHokJuc2ks9knxCGPH1ikg fk++GuGTSvhXnSmBIayFRNfhEFiQ0g2hE+gMClXqDi+dV+73EZKWtyD8gQ2JFx+r8x6GtIWW0imZ uPttBrmjfhLLCen04DwVjpiekW0Dqsce6ZIx2+QQCDNx3Z5J+o3glbdJHWth/MKheP341qpCFhhm urh1hx4MWQdz18875pCoJ91+U+bRfeu8S3ctVZ7xB2qOl7tbAis2UimU5LLws9MpmVuTnMrwUnqG RBXKgQ4zry6eM51/nBg8tuzzlJBoyUTWUkfieOrxOfGEw84TXku+6J05e0Wi2N5BHwAUryFL094+ gtnDs+kkmXHkhzKu518Jei1zJMZRcfvLrMcs7s4ptt5HUf1V6x+FfnAH5THxYyhE+zjS7QyS3RYg i0rW+CIrx5z84AziyRKQiwnKVinAT7Xb+vbP2vl2Dt1RRMMqIhSm9iwSjxZA57bPcMcjtq/9BDVY DGzlaoA3gLL7T2ZQVSZN1HKzskD/zenZ4vNBGQs5lVwnLODQ+LqjOdw5Tge1Ar6fgdmiTlsLIzQ1 wJLHxMT2tZM4KvtAT3/O84Zam+Bx74x9UBw54Xk2wd3y703Hoimq6lhN5ZXy6VLoXvqr/OWyTnUR 0bsYsAjv9XpvjoeHK5wUpDMqkBa7L3vk9cSCSjdjVFdOSWY7C0yAXEVdgxE2F99Qpr+qYGCc31gv 7iwrV3z/sqvAazAru6weX9RJj2AB2WGbgrITcnpJ/6uPs9nQ9DSr/qEFXchiZuDiZgzGm4Veqmlv 3oZXDd/93EdCoT2PC5kp+T0SfLb5qYpZWLrrkGsiSBWB6nlea+z/gLdWDaxPpa/xhmJOlJYyjzEs TzcmFycUGscKYM8hBOqBTy+p6SUHP+BmrcfbD30pJ3Beu4cbDTo78mgbnsVDTMj4+KIO4zb3Js8L JZl9WjsNvMkGmQIHZNdX+1sIwVdlbco9p0lEf968iME/elbsLAi/0VqzV6Ha55QxiOisFieEqGcV 3wAeimRHLTSUqxFBDjPuuTH+clAO8qyvuKZEOpxX+OrviBQd08UkWj058c6LNodaPVVtKIlkUUBv J/i5Ivj88mdkXN1IuQSnYYoOUWUfmacVppWnwr8XPACjmaAOy2JFXFBRqsXLeaxKVd1dsyrIDYnQ a+6KRZI14IDxWTRF5zq5kSeb3MS7U5tU0bBiCihiq5QrIwzMe88Jc+tNs38hHMnCpVyPU+DFVicN hI7/Q35AlVfQBPF6rwUv3rP5uq8HLpIhIlmnGnL2sc9uZ/FtTYmFQbF8ODV7RX2R1FzyHxuxGsWm 5dyMZ8r+ck6c+8YvQlQUe3XaSgUl4q3/QvCLlyxLjnsjNaIp3873IgKk9YGsqJb8G4P0ptgzZfkC c/nZi7bKiYKnPac6kA9qH+JntbND3fjhe/cgzybTB4mBae2f7loiRJVnml7oCfN4S+LLtBosJRuZ 9hMaSto3a0WVOi4M7mzbprxf8/MysGtVI4rtAsI1X0xBXTNk6PdIYHHG7EdWEv1Asjq12ZL2Axyq gZV5chaDis4jc08RH2eiPJiqIecId2r0depepG3KiHGSth1NPqXbW4/sYhPRJY8AsfVSp43TfJue o4dZRPOxVY6p81mzkTOxXs5Zc1mtNjBYoXhCrB8w2haX6ZgFFbe6XIuYOstb1U9RfE0lp5696yDi VfjxYXuJs9uHU/xJoj1v8WMs7kdn3/T8xXeFWP+c+x+auvTBTMkkfGDDJ5TzWYDUGVxrVUeI6SVL FriXaBmopotOyo307De3oqCyk+gmI49YjrooAJwO4AaHeTsRf331ZfovHEvtw/lPXxhx2gBaZp8J 4HzbVIG04TMFd1gv5UKPHITUaqFZRZjP3Ad+FR9YBHp+24r14ohnn5pDMePIxYAswY4N8xYUPzvu GSylN8PFznBt/dMCT/Q+7gSjB+4GIelMAAtp3TCAT3tId1f8jaeSo+8fTlrsqqMAPzX2hVvqJScp N2IExrKCIXMvF7G13KeFYAcOzboEhbAB5rNpw5tg5d7zgR1qGe+jpvhnhSih6a9xDMobmDBXRI7F +exFOx+ZzidoJtE5uzv8GdI3SpJ8J1WBxbkeQOLx9XzT7UIPmIT0lFgK2h3i4jMQWwzfe0BOjCPB KMAExbIpoMIWWZT7wMDa8wrK3t+kSJ/8at8YXEl7ifsiqruor5PFsiMwN1Q2B8nLOyH5921HDvmA N5T2c1brpDrTCzRmTYGPc/LhXqk0d9DcVLK9pmZhoN+tplMiY/jifEuT7rg7uQXaWkF/0dwnwTsh VIgRbbve0p8iyY48GNGWPU+Xnek2UdckQKxpRchQ3bgKt6UdLSaTQPjQpGil2G6LxyQyCsPaaukN THuhrrtQc114SS9KTgkvrFkvWSYb+E5MyiQC2XK7PMIA0ktPjeity7T3FtPH7JUlr4S0LBQ4jOB1 2AuVtkFDrP5pQZLbVIqXNNMiOstTrxxjEJvOMmEERUIfFeoRnyjN8BRxVLGYe/tUdfGB48UKDNQs 44ECxElGnEnzsHzlV7D5taBI3un28obDHjfcngTRTlQHsD/UIY4YJkuEW1i341QKEPlA8gYlpQ5U 0POmv/vlogOSN/I24xvpR+6679EbH23YzNRbgUNVfcFjZpxzPzXR4BgLdLNVTfbVXt9YMY9jIbK8 h/Nx0xy7nd8sXGt3LfTPy7Tz3SSkY0lYjebZ0Aki3yhseF16w9lFdQklvxCthLjD5CosKNsAQ6Nf uPFt6jeF2DIPjomdXX8r+RzFX1ZAyPS+lNRGYY4Sce684rPAkxWlBoyic0LgDPPia/za2xiv+oqC L3CTUzr3K3qNmJlVKZBVht6tbHAXhok6bfozGWYs9GEqUFYabAud63d/DJ0NEn3fXocOcg5rqOxc lWFoKa8AMFWl5GxcKGXjhkZgTr/Ky94FsYDPAERT216j9gz53FBqLvOzo5Ahagkb9++Kk2+H/xxJ HEpkO6oRrcUCkn8jOVhvFn/VENnV+vQoMNviLbXhLgY75m2xFYElNkqS9yjwPADBK/x+o6de5mNk M1Oyenwc3HTY8vEwYnarbVpTayRVWVt3yiYpBX+/IVYNzGBSS1c9xJmnZDDLVJrYfjJXbyThPo4K sPwWVWhY/wO0dxVBBWkyThLj9n933WeDRByYSAho9EC3xIt9drQ0sfl38xrjfvXXGimyWcHN83X9 tkM0rENkNqaJvB+mUAdQ3P6k1w3z3pmgPPnCPolaoAynPETAF8+YqizAgcJJlAxsxk8X33aownbY NF0rZzQOs3KEGuA9p3FYJiFHDsmDg3rQ9HElrkr7xAoUvjHH4jLd+/b3eksvP0j413w50jcTPbW7 LEC+j+53IriMicItmLqN9Ir8nMa3xxCdNHr+mbSBiDdzK6fXgQIm1MOkKmc5NZX042tOPf/h+dtr JnezgdqMFoz4Qnd0Q2kSYZWh/vPACf1IvvCj49PdA/YXunFLn6Z+itKXC4bu2WPnjmmVkYsW6Sc/ h4NPDFAqPbpl/YLt5JpOp2PJthfP9k3s6jO377zr+2W0s3dPlN+i0txvPFyGcEwfcbmpZZ5fCfBs 7Hm2rgQP4sQZWvLXe0vCmWpSQx4/TsBwcmpVnaX7qd0zOtX6CT0+VILJcknPbABkc0tb+wdDYnh1 RqdDhyn3CKrdNprALPJl0pXKKhiKdbksOGhkPIToiqroshZJTrYKu60t/Vyc5vT0FEjn9yw/USX/ PS5zLKb870pyJ3o5EJDt9mLf+gsEzQr5rbfR2NF53QWlvCLVVfLUnNmx6ZGPwM7/DbKhRTFXqK69 WxnojnhjXeTmUtx+6W3irMamsNeYe0fbSyQLUzwhou3IAOujuI9GxgQGJWFGTxzNcVf+6+mYEXTC 5JFueaEOSwjt/hEVLU2AHpYQuVyPVO3XlrwbZeCYfYJqkRLr2UzsZo1UhP1WLztOghYmIKuNZ9DJ R2MX/v0muivC7TQwk870qy6gaaJZ7gf88vrmcNpo1daGf+nEQsQb020A7G4rpj1PNeWUTsNwqb1P C7vXWKMPm2UYrSbpsiHpCopEg+YyErQsqukPLXY0Odgla6hzCykX3Mj3AGH180t7+1NhgwTphO8o uiVvt36iAdk78h0lxIxdsjQBSUC5o9CMxKY8KMwFN9fMy7mGjMl7YGCa5/r14EmnhPBuIf8BJMBN uKvthJD0ck1OetQ7VqXcZtavjPtbDxQzrKRO/mPmgD1T3nm8WJVa9hymX3mLiJdK4WWSNkDHMNEs 0f6pi7lbHJBSRbwU/qkYRRLH+HeOsD/wb8S6mMgVQTPZVIxozCJcXmwNNOItKl9xw3G3R+xkhRj/ oNAaNL6ZGtrNi+igxRAB/AUN23RL7O0sK+2U2Gv0Fxsi6Jn/mbwnh7zOtWOvQZIlVDCaz0bJS8X8 I4uAO+87aovYgB+mXAD0BCRqzQ32/yoHGtjQRNGzlKjh/Al+FnUL0Woehw+LzK9JEnEZzEwCueDc aEo1GjuyWM598jFsin54MHmXAEByGybfMgcVAIR/0Y6cvTjLwKCEmJVPGI58qff9ud4rco9qRq4g 5djgSs6sqV6glyTaYD2fkDOf5k1ZEPp4U1Ch82RHGAOUo0S+rsPtTmhWnIwrXa1A2tnwiwpo90vt gqW3UEh3YPhVZrcyW8UV2ALHpnv1inZnZh/e0s4ZZ6HAkWHxaxKgoePCga5ENfMUah4T9VHHiocx Lq2xevaEWJOW7plWo1IN1Wf5i6sJ2+IKIFwuk5iKnk4e24XALqcWlmzAJM0unjWrNdNZSQCNMwhJ 9JWiVN6I9HCdxF1wcoWkQCZcxVPjdMrtvu/A+CcREA9T0+IsJTFsLxcKA5C6b3sc1ZLmGkpsv1Wh kZt770Wc1W1A2ThMpnZQr+Bya71aAC0XVx8ioCD0BRN8lqSX46zBk8xM44OR2T7W4BrnMbCRwkqm pqWuJv+3mp15CYND0Px/bUxNBdGwWkuVlj79oo+yra1BYxdtLziBQ57P79ULYUigGKmLL+K27h5V djxEzzH1N1hz8nFcIDLya8/I/NzSjOZJc0osAk8z3ZOPQD5rt9BB2ol2L+/HMuSyclhcc6SAlR0+ fhHPUOD+mzJxA+Z8jlnCsPo78sjjknSqosqyBXefD42MuJ6nExMcqvbxOHYAgRgGLZKykpXwTl4h aIddHtK5VqcjnjEIK2EG2iYI18775lX6ClLKKYjcYC9m3K0FOrhfQm+0G2X0QHravl8npJ0uYFd1 b7/lF53T0Bzvgya19BS856r57odZ6cK/CqpsXma9QExMUzW+ZXpwFFJPIa09pJC4Y3QuobAaDfX/ UwCyRiT4VgkXLKR3bGZ5XW74UWIWShT/mKx/5KqnAlHb4inewqwg8SxZanDL4qos8cbfx+euTBLs 7Fuvo6lGhYNbzKkKuMVOAgOhiQkMrnnS4sdEuGcb+4Df6B0eORdBhCr5rsUkY5PjsgQfwZOgikNa rBrmEjX2NQrihYJcZtDegMZVWg6XX9p/kmCZ87RP7ygeOS61ymYGoZwVw3DNIyfIYM/bi0Dst1Am QRIjFlwCLx7xFFdRI7/mu+xLpa8jf+Kdkx2bRroGQHzOBXxidyd4AQ6jV2NaSJ+yifwfkhsXC3XT nWiuBr+Oggw2ucFZivlO9ClJS+mylEWV9eWQqG3XlM29pje4Q6cnRoEa8l89/bAhOsv4xz91GoVB T+XMN/AH5TddVPGl1h7b8NR0KKknbsFhlr+tWZadNQ5GcYCZzvzhSJZvByGP+CZDl5YUfZJrM1Uo 5JAtvMxJkbbZyin51DKsuO2QGrhexDMv1Pezsx1mSGq3wvPOOEQGnQVgsUh+Now3LwECFI5gLeoj pBY5CJQ4C+v8ppnfldlyespXhLhyjxHD53r71ejmKlZqFB1UQbMPvjvMJl+Ea75jgPE6uvL8yR14 1WsTry32mBRNleDg/ZSUq5Sr/Tf3tuNNl0gNSqJsj3W5S8u/9y9cCkW1chUqJbZac38csMG4qevt bEAitdiC+Fy8psJgAKbt8FasnYmW34HRgeZuJ4S45Ii5ld4JIyC/xsrhP/lBlasZJwa/5OyS0WnZ D8ZLXmyc2FuOWBFffOjD/kb9G3uYPcTZmkA2I3mDAv50bk8XCp/7mB49nGJ/ySzW4HLqW6Jp06sW +M4RwQlQMFzDChparZPWyzqkCm7CZJfxZUEABUSH/O5P6Ga9pgIPZoA5xQOJUHeu/HFUEC+yg5Wv uh3TmYOkEp15zPgjNkTdFmIBLanTSr/3qgaEEp+VioQP+cCbINio0FMNtZaPf2NSg+mMPvR5oZeS IF0QiZSy7en2PCm1MQWkonEi206rzpZHbeG047bd3tVztd57u6wEmQ/orhnGYlx6UG6CpbxAdjkp 9cLSEzMglNyjS7x+8bQ23nBKgGouZA8/4pxsiq2eG7u6J2fVhIG/4qxaFubkqebmZKmHOlVUwXrj 1MPwA9P1odnGV47DHzjSrc/lIJPbrhZzVi5WBj21/R9fAAF7kwgdhhaAHHg/BNXFSqDUQK2x7cfG XnGxNp9eeNgjZNgx0QsEV3lu/I3fLMvxTpNIXyeLOq4kmkQCA4zYVcIzT+bg6/KyH2qEDcM9svPG Kdu0GTeTHWAdL0Ok1tPramYawwNz8K+lsEUwN0xwKNljOYUhPaZgwVpenRtikFlln6OTN1gKoMbw r0TUodRhv9+RDMOfvCeoBupQfWmQvpQXgg9aVnU68AdlVoeDktsfvpklboWc1ytLWPCHVRiuVTtM ZFd6FkGvQKl/lELgfxsNgH+bc1mIggQrVnm8hjif7vjWwVXw/uzpNxmUsfyOSfHbt3wV3aPBKT1l +zs8Pe5EU3MuaaAOFOh8Lr7jwxHp31q3MCKmxpXXOVce0UciaXP+Ih/U4ZIP3sAbipGJeP4MKHAN 3LMnRLwgZMhMnVrnpSLcv4l3HOgOhRT1wVoFEGmyzEN0xSbRERfqAvpm4m78uydaFKPhwclI4tV5 ay4xU3LdHlFsBWw2nEZ7DbqLw2T9Pq2Uv+YguoSqf4rY6coxbAqiKtCgevvCMIj6UrSc3l7RNfhp L21DxW/yL/WqOgT40TRHml1JUtXHPz0zb/Ov+h0rKN99euVGfFfkDeX03NXaeB2XCwdlrbpIPWfA ZbMNMTCeh0HockndjIGSYRXmfAwFfF9YGcaHIwWQgBL8Y5G1C6j54KDVpM41z4i7LBqJ41vuO+oV VGY0IhlVdyOrkpxfLuJvzNrP3r9lPSQA8oXnHz3WGOKWHgTbKsqVrHAbY63JiyWnR6lfsytQyNtN ypZxzmpMkf5M6ZU4H55N8rxFkzjH5S4puWk30L9acG4rnNj+bWqqMe8WvRVJVqmARaoIFGE0+vUh pGowxjzOuYl1yK6Be3Pxa1RQEm0pxSEZBkZKU/W1yb06mJ6R/mMENl2wabUhWNiv3unTargTBDVc hP1eNfV0Cw40GJnIdAMBx6brCZLBJdDQuXRxkNi5glG3syVRTtUQ+xeH7X16yYEGkeCqRpWuiCIn VMHJab0koGZpSHUyK5f45knCkF3HpYMKtfblS9Ly2R9rQ9GJEbE4n7ZN7Zyy0S35GA3C/XE9mfnz zBtJPIIe0UzBYLaxKPi3kTk2M0Cks/9IE7jqI9vSKIBr+ZLBGPiJ8sC1PCrMxQT2E3Durg00kCa/ vb1HKrgXD1g3fcPyy17OwUd5t+eUFrcVsOfMrqhTqgPoTn+5Wxr4tuM9UdKLqQtkOH7zOpv9zXqq bbQe6QUC6ntJGgvYkqAR55Sx/G8BgMfZZHSGo67jSmKv9ZhwFQAKxbYybg3/gbX24NQ9aP3RMzR8 kvuiy+XF6oFYjVwPxnarEDuedMntiyhZtGhC0+duLulP3eUq184KDJys0jXxGsRDIYQ5h3qhX0Io BW5NWx+QBnbDs3xLY+NwQSN/JQHfEU9PtsGAzyZ1up+TI1+Tr8LQFCw1HsC9M+4+zeZ7vJ8k0wSf gocvtuGwtbqfC7wNgbR8/R2GyPehg51zUR6GDyHlBop6IOjhGUwL0YGnl/K4CiV94omGmR93Vu+E aOVtyrHAvc8b4Qsx012BIf4u4O+sraTtywIbWScNP/vv7VUOV4gCAAZieAcVlo+lxoeZj1DM/oBr mKELAYC5BOziD2L/bkVrQfEn5jysaMcoHk+V4O+5ZDBan5AvG4rqmv2jHea/hZ9LM6vxfrevtcml eGxtR0ARvYO/F7XZaA8wfRxx5jGynqVm7R+67+eRDIncxJImAcFNeTlgIr1NC/8ZAg58iU+fdDRu T8S2x+AqQuhf8JwGqspEPJVmx9grNvDIHeQJ/7o1RiHKIG9b4CxGznWbjIVyvxpK9Zhemj4PfJXb O3XVCIMkr53IC0qIaAhr+mhHtdXZuGSLrBsMIlirsbWZRRp75TfRgykr1dx5fkBMcz21WM1Pc2Jh hqdBjAFopAx6hzF6n+wZ7YtHk9TxEyk7JPbuF/v3yFo5uyHTsxXGrJbammsO7wB2wPSsSRFFtXgO k7O4M1M6G4hipdA7+EdC1Jvt88cGZRbQ79pxEpZbgtKOvEmfGokUFbkIvWEAIwz8RBjh7Zxwh/pa 9TK+9rF+TMNmlMmuE2PDqGOQAgY54+oxGx7DjFgJw6W4sz4J1IS/2adM+6Wi+cyhHEF3gmXyrFen JvH9CMrGD4DjnnWF0joAdmZlX5whjDbVWZA7703o/l8oIaxqtLsuwx0mBrRgxdR63UZbhHDUxmz9 sJxP6uD+r+lSsb3ArdYhO7yTQ0a7V+f2032aq3MFKWClRUOYMrsZRe+nIaN67HMDS1k6QO0GG7lk t8Eg9M8UrLlPW5cS2gH2pdIDkT/SPQAHJgwfcj9znlrJ9coUo1kPxM4ORkifMXLqjVq0dytKY6d+ xjM4hYN7+ovyjVlBmJFLIeMW3X3jddsUs6AacXh0UhPErSD2lQmfIgTTMrpo8ihO4M3Tyb2NKXnR +fx3vSxtiyk40YiTaFMYlO212ZJ4cfijdyphD1z12U8rVOyUmMcHJdEMcv0WziGwScSJwlDF3l3B XDd9oVJCD7aAXk7kC17MUtpYHan8vYv3olNQlW/lDquqxx7s+0+SgYT+mno7Zpc0PLfyizsAxn+f 2o4Q5TEwSDk7CIrNCw/a5R7xcVCPP+SCX6bmD3/Xg38krBDkQiTexFDMwxvizKu8I5euftuaOFhD 8X//Wm7lXGnZ2TceJsXaXzupzIyAX9LVZwF0A1AwRsWrOGCngBam2BbDMx/q7owKWgN+ytOwUxZA 5v2vjWT2AEuFEEYxdcvqaMb/qX8bWhZDmzuVagRdgg1xQEwIUjFdi8N0FypDRxGBqMuylC7fmgGX /Df1eVQ/1yT4anjcrPEGs1xESi2X6aObqsNe26ZizJUpm9+5SRM0uSTCeQpC73CJ/IwKQdg8/Fx7 iC9VXifGl3oNxSQ8snfCplDuVl3WQBkW38bhvFe8c1L3vhlQslEKi4VCB9vjf3umtsZ+YfJp4D6G /OAJQfdGu9x+2ao9vyZ8TKHr1GdioBSOurqGiCLcclYasQoCcURSH5rhZBwE3rOd8S2eZmRYaJ18 NFTRDY487rWM8mkNVe+9ppUR+Emom7kS+FvL/oQDff1nhPsBjB/vx2sjihlf0ni0qOnDFOpBIR8P gYi+Q8kuhWylkZUiSKuUFYvEu344BIMaUZagNJEbr1oX8Vexhqr6r3CC3fX92qYZo6pmapCaIshM XxINa0Qlp3AYsIpNe8eawGixc/HdbnXg5yF0ZWtUj6NxYKbfB6Hl0rP24hBbOwEfFIWcnbd843oq m8InrDUadWsAsTGfuSqxqtFeiJ0w337uXGXN6wOM/ZSmUYDrx2OKK3ZbKg62rk5yn0rI+Jth4pER +qpVyOjg6oXNJY3nTovzcsvFjssG9OEgKBM6NxsqUTDBOEvMNgYlFSg/Y0zb6fF+cqA2qD5W0AQ6 hUWOt16u1OynqMT8KX4S2E4AKpJVetgqiIxJ2dQVrQ3HGTjZ/N15mpj4cXnLPpdSvf9+/1Hv1r2d UqhZ6t5wY7YCJKsn3T6jH1KQ21sOVRT9gazpV+rQJZLYEt0viUl57uvc/tLkoi3gH8RgxtYqGtRw XLWSzdxxfnbInNvUgcmMMU5OoT1uAL+j1L+vgPqDIk7NtLTzmNP54suXKfVGA8v6UOA6i0WQD2nY VgguhUrBKx/wcHIIpZBiq3lMhtdFdU23UVohkiFgMirQ4Ptd4kyJS3Wi/cElPODp//zR4kT2oj3L 0xMBe5bWziGvO+IAnVMH+36G3GKOg8vwKITFxAbYXuxcfjv00dYY9yZyUoNoPMGwAXfq/dMx+A4s pp1yj01p4IGGWsl6LUyh4yH5g+ZkGrZ1VBCR/waI0uCEUuWj6oOKI2SixXxQpe6d9XRx0ZjFJ6vO n9hIqEpD+AkyBCyUsdYYL0JnG7CT3P3HAsEZMwE0XogCAcMz58lHcgGHyzkGq5EIxiSTIimo7Ouk 5YDCYfjhUKhtyj/yvyFZ0OMg/aTm1USw6ToCzMQDg4i6A0DBAK4U9mU122RHYlCCOBBEF1qizOwl cqNxzHjjl5cdKCQYgqRjpvBN39UjnfuKAdxhNatr9fxv3Dz/Nh/s2+3sgYDZbp/XCCCUdVKfP2fn 1oQGyTkESTzheDn5Q/OOCbso57dpg1USm9EmOA3j++vvsJ5d9kcX8NKsZhkJC4wn4zKww0cnvePU JKIODe3tFUnCXy5mVbeLkjVoZI7hSH34ng0jZho67EIaR+FBLNKvD5/7uPNXiIgL6X3dhqQSSQU9 CcAZ9PQ8fK0BkouI3Dm/oqIGh9ymCAYeXP9qkYBHp5N1sgIXQtEwW/Es3AV0+U1Bf0pimCXqxyAK akXDh0UK0jo0EOw+LetZePPL86TpSdAqwvcB/DxKavrbBV54nP/SHrhWKV0lxdXrx5bfH6t+4fB3 NXZkWPeOWWfUJPQS6PUkXuaL1FCggptQ4zC4gTK5fqyJ8MwJhxnl/yn8jf4VJTtGC0GKQf6qXtWf DOIN4IqRdTR2Zu2o+j/HnPQgeCiwi/O1ejyo4Macv6tRsDJ3Br9IIg9ePWxObeUyQoM5ZIejooho AN5xdEYE1nOn3wl8luyQ0gwT+I+LdmPc3BycI/Hs7WIey4WebwxCf2YRr8o0hNKmBq0FPAd0z3EB E4yKhIiEV4q3VGsvSYmvJ+EMbYl5fhGNXPK6pixaavwHWaxxDij3uudHSh3C6f1CYks6HVXF9IhI +0X6gz4ndxl8OHDojIP3pykyEgOZbhe5qY6Ajx0llA+JGjog/R0Q/Z8de5ZzMXZhYV8S/iLF0p+Y 5qjPTExVbuSSkyF6g7GIJsIW/s58qJ3IOKObDV9v2LMOKr6Ccd8DkXFpdlvwllaULl3HJVQOGU3E AYPFWHSLW5YOmEaJHz/3RjIVEknMiqDPLM0mxh4vBJaR7Ny9kHm3Z/6+eqUpxEFbEbXwQL6E+25d B5Ytf6xHLmXmWd12+auGo8tl+L0cSGfXCVX7cpcdq3JppKVM4G8cxSkh+niBeAmPnb7Ya9Y/cw7d VWC6HK3uYXUkZpZAx5LOmlQpzf7JtVy1m+obO9Pz29iUbhY1oO+aIycPHjGJjDkKtSxfEsUHdlpp 3kkQF9g3UiifUZcdxYTD0b6tH0bNwPbHWYGyrtLo8HFIiyztVPNjsChAgbvxqOJIwBQr340+OFt2 cfAl3CL2nR/vRqtNs7fjCvLTXWyBWUdiuMrA5Mr7G8HsjagsddThTtfbH04WYFrjUeOFJxAn5xJS edU5rKROOWeT4q14Hr8PIgBYRbkwRQ9m5+8Y/3knjwn4wGoX2VX6rdYUoy1xI7jJ2ZR2hZ7Gt9uT rNkz1fmLAnbBevdq47+EMLVG/agiDc5TbZZ6p1MUcWleAvtzAQEjkkp4lfGkV32XJPmIOrlLtFrU oQ6KaEISvU5d1PrR2B2UqvxmSVgdUNTNDfQQ3YSHa297/vQMJtV7DVO8RHI7Cdl4orxMZVMwuyCM jJbc/IHHuMRduKXfBB0kbgj+ILIDivOR8EsGzW/K7/4ii8T7Fdc+lv7GR/Jw/bM7GHQ+1/I5dIzf cH/EgJMD6/qjK7j9Yldcou6FOIKkYByncJmAKoncc6diGnOw+uKCQF80QJB+1Hb8t6n8CevCpOWG 82yOIoI/+09TidZV8V1yVufzXXuWYK8iRSYSQ9pp2T/DOhV9kHxoJWxZG7bkWa7vKubN6TQIRGzm 6fyZzf4jtr2kzWCvKGm6SDSEeO8umK4onS0h7MFBfiMjHsdrvzi6rsulqZFisX+QMsscWNFGO8v+ q6IQoQS4To4hZMXWkbYPgmwR9JeWZ4c6WXI/60ZggPhQ65Q5HfztH6dozexe0ZXJYEUAnWmYNlzw snJkn1mVyU86IKmPMyB18I8Ojm5xdBEF+i3oD+v+jbx4a1w4juzUfx7kjy7PkRUxTMBTET67QDJI AojK88sPYEfc+TlYb7vj3WbLcnvSGe8ryOiAwh2e439f5U3LYYMrIx9i41aNm5CrM04BYj8i0LcV 1y94jBkbZax4vZRDo3syk9/jSs4EcKtT4wCiJtMGy5VBu3jV5tTHycMH8dpQvvRng9vMT3Xrs8oe PkssbCHT3A91OYsXt/FROBwMEAHaVr9iOnb9MihvBbNjkuO10Knycdxso6sBZ10vuZU1LP2/PKjE Q9P5cPqEpyuBT1bbuNmiUgzLJm5LrvFCxelDZy105yicCR9BLjeo6/y9B8Bd/vnc6EU2ePO4yafd +UvQr7DXKAXa2eNT45Zzg7j2RsKK1Nw1nKuhCvW8Cok0RdEUjqLl01nk2y55YHgebA6WdR5fNX+w SLqXjDjc6lZcw4n3eJggwr+1tZDsFlEWKO1IHj9L72bvQXj2/gPYpmYM6bGAESxn088oF5whg+kN 6LjaNZQikYAZXyvrZRK+53nXdcSROSekHb8DIQnqzh6MafAskPoZblPsb2rJQSOl7p/PHrsBre4I IWv1cj4jv7IHGsN6ZI0AjeorDoGTyo2LGY7Z5qkYk5CzUc2aIOkubTBS5S2z81kUvy0Q7erI/Var XiFGFMBqm6el6ePCSY5/KJ1R9Q3rE/JNlZBSASOPiFZbeYPPII8E5KqtcCO8hab5nsiJDQf/gnMc B99wrZX3csa2SN12qHfeaoOB7/cDOZdqCRZHUa6kd6XwmoO7MbEAx/OOTyxnOYIzXU9pRWUdIkwt g5Q/NBKwCCmD4hLQpDIUu9BaIhD69m1+vYHqUqqf9oHQxVf5slx6qbpLMbI5M+8rO7qZFQFAV7QV tlNO0DVdMiqcleyILxc4Z03aS7MY2Z8Meqr4ex6lJfaj+5b/ootLCGvGnIDB2eMBG3hzEEgVnvRE 2zHtMZsBBJGuHt17nx5vdh+jPMbrRvGC+PZwUymTygmR8ocPk4MiB0teT6227Fop9AFpdENVTmy4 vlh80aGjZ3m/PdAgibTbwv4zKeFJk04+CCIsIy10v06muN8cGW4v5n45EZ5SSJDFQl5mklJ5xGk5 RnjZZMpPFpUSw0d40gm1Lm591D7Hj0QB0g2eYJygzai4Qo89BIwit96WThbOpAmiZVNVWSm3O5Qd AmQpbXdQYCyE/VNczx6A9WO8EXvF9Db2YoCH4MkC/TrQGMHtlwxBCLZhV0zp2lvOXfqyxqQyICLg FYEaa0t/7g7q/ZRHOAY9s1s7+XDmYyzGtHH00KErKc/oNrISOSGw76qtkJYN8IuycFhOw3vzOnIV Q9TXReKU/oi2Cvfc0ZEpvuYYU1tKUSxFKaUsrjHzNFJBWjkIbjhuammJlzzAYSnybEFTMR7Gb00a 0aIoheDx6bQRXtqmPhYlzO1oQU5kM1EeYpo2+4sWXQlgLpKm7JvsRcd1rLDrYvS+qaqKMCmjscCw Re20DNyykEHaCTCVPq2v/HdVqVPOfbkuuKhtwA9XZ+k4Has39UHHnfjlMG/7V4cirG3gsmEFPVVW MU+p+/34psocS/TDuJpcrclORFj6MFPsJ3QQtZKF9OgIaGqxxwD6dsSSkmywHD2ZRFi7xZvud0P/ wuTTe0B7JX8Ny5AmmlRlv1lWMxVa//yZomXXKBpA5AmIkgVN+zsjfRQfgUbU6Z51fuEe2Wtzz9hB S7vsG4mVbE/jWmffiPYsxA5C6/gY5UQMbf/te7z/nl7h1bnLSNjh1DR5xN9jIy0Xra07oRxf/Uz2 i39SXXlohHwkO7JNBU9eK0YI6UdqxX2/efqWWIA9xpxrY44ae6oeQ0HpQMbQsIuwiA+ENNBQOLDM SRH5/eJu57PN7P625OSuSKhP3QnOyRtJupIADcahsMPd4nXt77D3x9gcnVwOOXUN1Ub6IKi0/UgF v5vP54aX3w1TC9F+kGGUQEul/43jdRNKzWp/wBpDk4qq1JE3pHxDS7irgZWeAmZhugkXGxIN0tDh HEpLMC5XgIJ5+12gMoxoTub9e/axKBvm8sR5t2VOisQHJ8HSLiYzxEfgEbzxLRq1ucrC5h4fJYh9 eFt/9lqlGxmz4mz6PJiFSHkIfc5gEKSKExMSwlBbOO3wQ+aCbAMupYKgB1HEE4k1ocOMTgo7xg9e KazLoWsUpy3xQhPYi33IKwal4Zzd00AS0OE8jF0gvMrICPD+WY1BGrBP9Jsh53M09gdavZEGfPXN Z34WFRRfj3IFms5FDgz6XInSMytpE2xevninxzeqE2bl4HjTKcv/q1rC2+wDBCzvcyNI1IoWSg8c hjzaSrl99x+XvthbmKg0W4n2FN60VMTx/tATizTuZPGJsE/In4CfHX2faYYrTamyhUk5l4fj7lgQ IFeL2XybxxkpKIGEOBZ+YpxHERqO9g0hq/jXDCDaXP6Y2IEY8RbGVdzv1w6pYxEc8NUoRUlxuuMv njUQvsTLPHGHixN+nBLVKDIqMeLh3rzbtP2BcUPQ+mh8M7zKLFc3BIaOC5ZMJOzwj8lqJZy5uwA9 w8Id1WWEzGjMHaieKMiieIe286uAF6iCqGfj4USPCzlUmvPxhGDBKIDwqBZ3W8Gt0VAqUhShKjdj xCl61sG0kpFrQ4Uy9gj1VNcEXmq7csPQGehM87hsQdc5+iOdKtl3N75Ti+O4kVlfuG+EEI1rvWiz FiuoYWeDNx/KRWOrB/3Maio7Qvhy647zhxveUutyXTK61laSPp/+Eo4N1UrVBswhnkIJvwsEtmfC nBuhofe59j8RKesUTJiUqcfchob6vapYGyv3MfRkitbK+tKV8CbqnkMLHzN9VTNv7jGjPZE9/5zY S2D0WYtA4TJuPVOheWm/V66hNMPF9y+ZaX5H7bcnpXmQpyqRZiH6u7vqGuu1K1gav9BMwhk3wpOU reWiSv2dQcYVOs8GDt11ILAoSKQCEnpIwY361wy/jQ7k+bAvYpCB7vjR9C5ojViTgPUf4tKkjEQ+ 6cg3Banhnrw25wJppNWhH0SdSxEyt2QsKsiDU6Hun27b7F1Tm4GekRZC9xFnwt2UoErAejeEDek8 dHcgaQxB0gGnz0cfmL/J/U0PmZR3AAvP8D/GWQ0XcDMV8ft2ATVrmOX7Ry6HEAni1VgEd/qw43iM 9JaIutj3bPYRSSQDQqZmkfNf5O2TH7aIBt3K+89q2kkCFQASaxj7xCYE/e+K8hKrwYxv9a60/6eT BPkCLbo5e6/2HKU5Vlo9vsrQDiwNEIEClmYxCUB9MKbm9V1pm33ZKPv9CqwrlpPL6GhopOIHJseM blEf0HLekC/zdLUDLlTpD5rApl7jsRohpoI00vKAuqmIos6hfHcG5QrGM9hZ8/jxu7uQ9FWAbWpA awKB2gXFqMciRsb0IX0wUO9VjwjRU8e3ZrCpOWoachhWl4MEF3XvUYgtnsjx2ZZAEzTM+8bDZkOC hgDiwK6+94uMe++FtVHw232Cy5d8KHx68CaExShYiCJVfevQJPPLP8NuHbJikSI3zZPclPszLDri GQkt3ClX5+t7QluuN0ohmfBWU5yA26BVgdFdh9u63j3w+F8D1xyvFU8ahc56pX/R8okd/IWA3qzb 9n62qr3q2tNEtI7Im1dUNeIUkh4jXZ8pQNc3lTHdXDy/d50TLQPHC6iLyiQ01k7vHiqL3nXTTuqt Bv0wuOFFStgxftiO7vf4BpTimIibyx4Fa4EU8qlx08GqXZcOmG7f3mhdglW9Volxy4tDvPK3J1iz qgP7PnBxYaRI454ImNSj1/fmmdIJI7Y6Hj9BjJfg9EDkhuBuJfW7x2YjGNx5cFZ/QvZ27eLryD9y SLaKw8u5aV9F4jQ18H9AqBJAiXhWIzaIH+NxsM7frAox2glxYFQ3NiihdRbpNSCUr8v5nfPWoREZ cqWQPB/PlvC8AQmNbtdQzM6aJaNHJhMIoG0hPk2cmwvDdai3yto5ykf5ZtkV3A6ayXIYInkeR/zp jMzZYE1d+TTY2zK9I+mNhWQ0zfMcTok1sxJ0eJsY65V64raPUFNm2h5vZ7AcIBY1TNdNI1puy2Jp 460/4JXv9ahK0099VKYPYZOb171LsJ9XMciBw7GI5No8/d9xWnnYH8vuxAJhK4SjbueFw+Vw6uzl uJDsNrRx8oS5pIcHz4joNeEwzhZ+q97C3QhWswxc7ZQncx7v/JncX66AgmYN5YysqLSeXu1DmX2R Cm3Y0BcXd/DYA1VL5rVtbD2ADPxfGMK8TJc1NgCWj3exYDy3Zn1XEka2tAejZdUKTaPVQ2pj4nDA OjzRiRiG/gsEZ5Nk+GUi8AD2g+XTgpfp09krPr+mvsFrMYqJenuDh4r1plTrL2coUY2gdNgrs6An 6tTV7WZkqTaK/EaB6/2xDrSwhTSUC98TQxZKhzrqDFUVIH+jJkOASGA4hDtljQjYLZB5WemotTVZ lHpdZ9SY/XH+ECtBezX8Fif3udWIZCJOr3V9CXnVfTsFQDOUMa38jypQcNUxV7gASEgHqWPNdA5I NuV/sXdoX/w3VZ9qu2/Nn4a2KH4KsGZC+r3QYwBXnuAwb+dhU48DZOKDeSqKzz+UCpIdkzUMguKd cBot0BDwyXE62aEBuq8VWnRuJp1I3WWq55qQPvf35YIzyluLKqeZ6xfKUUK2sY2m25ZqjbOKmOdr r4UxdJr8IWQeAVnU63wOnBSCBKi9bTzbMUYScCV0bDWi+0zAt1/gcL8XMd1y98IBTrL+bxbxAqsJ UaIcbYeQRsXoxpupCDwPGbZi2XUA4kxv8RJ9dPFpOU201mvLpcfgGDayui9DecC2tFSRPCu/Zr6A oje4tbKEvavGT+CP+69lNC2TyAZntolOS8e0a6zrA3NFzUbcd+/hBCkKshprkIqbxeXIFbmvyUg1 nZWJMXVK2wcpIMMpfKj6YRg5ieoWUyoPc1ORryGn5SitNAaF9osFGdIm+dkrcAa9035oRM7GXhhU 0PdKHsVmMLE6Qr0fSkMqvzp29yDZwDVVKmpJolP7ugFk1hAmnNHCspM6uedaIROfBT4W4gzd1KaO HjbayywBQSGlCxP7oeDkt5CuI18w7pCo9ORotUyCZ4CtLPX5EoaQk4XmcQe28g23kCVOK8biNbkQ o+JCzFFK7+sa7Slo6QXg3YO5aA6s2iYS9Ppj5FWqU4xwkiDXd/+x/mCoy7bBb6RZtN6WPVYElaWp d7/emDMy6h7HC1HzqjNWkd0TdKjnVfLvW/sw3MkHgo56Srzp1WJktPyhcfT2is9MIeHvUIZzCRBS 4nGylD7YhKSlLgb7BdxBplPrY1sgwqAH0184Ap/kq/r4tPrfjQ83/YqmQ7ie3EKm7r8z8TFQdlgA Tikb1wN1Xc1S7F0Zq1l7Oz3FqqRjcI3AE+vKxID6a4mNZlRJKK0cJOohQzWrdlsxBZO8QtlMWK5P kJC3Fipk0BiI3E7SFs5AUkNVQtr8igOmmfWKaW0fK+RMTvs9fXOMlxyKEXBExzjFGKUuJn33O6py J+P2Wgpraf7gd9Bohpn52HdZgMkSuRnA7/ICWdqZjsjLFbyxNoiykwsFKxyMM3FV9MkpFvPBI/wl 4khrk89cQ97Ne24LGHvbufr5/wwf3sfKfn3e2GWIY6LFjO18f16djyEUWR0ZX88iwM0aMtvGxul9 +8s86oMU5mtdT2KejO5oBoTKLZ2O5WRUmnQIddCd+VAvX2cKx+VTmucwiFFjf559W52EasVAHqCT C0EqCI3YoDozA+BzOnxhtcpM4LkgwHxF3/xi7LL0oyKSlOY9rbUXXi3eH4WeFPgMtEXOKISCcOmh XAIii0M+poDmQysm5Td2lAjIC16Y0CtlDCWcQwkW4n7RnOm05bPErB0Cn/mHkERC9XHWFgN6PAdg cs1OHRdKDACOXX23egCxmdH1aalRBg/tASHUAjDp0w1cQ7V4HM01rmBvXuME9QcgKpzStUxNw1N6 FIetXp+khvs5Ggrh/0vBi9Lpo+Kcri205OC7SAdfWUzso9jUfXKs/RvUw+zhecIWg4f6HIIT31ZH btBm+tEYC7GT+z+xRf5ZNI8TxoNMj6oNb5EURcnIUjE8iRAzj826pkaY5JEUs3PEUF44P/+YTk58 IIUUqlnZpSvIA8Ptqv1RELWEj9f59gQdgWxqPIGRx44xpe0pACgzdd6sMeEp+C9JR+w18qQas0Qf xlp2LaysBaswFGZbxaIiPYg4TSmkmgYr4MYacb7yDtvI8f4a1x/G3EPnJt4FpsMxg6renM0wC/P1 VH1NWo0a5erkAtDQagvgmEO5MaNJEgxjLXALBo8msSKPg4YD5YJ2CkwIcoItdIE5RV7YHOb4/F+p H9Qwlg9PMJQbkLYgmaKkEIY71U9xaF1Ucj10rqLclRpgmvuivApD0Rc1yPjLBqjS1aBbRa5i+nYi BbEmCb8fX4O16UOaKRWZIp+6kOm3iJFy+p9Gj1pAv6qXK+q2e8bJ5J7VEubRRvBf54xuXajLVTBj QSQqwZFT2S+YpZ78d5vCDYsfVsqpIShPQ56V74S1fOFoye5ge1xUQSYy4Xiic9VkRFVqMdwsUZta VsnRuhqLl2iEPyWLWvjoDJX8tstaTy8BNnt3Gv+EDL9bj+pY7Vp8kj1Fc/QHYaUsysPNXCz+TJpn iaVObjkKzNqJOnJNZOfxG5HWr19w+ZLeMc3DJi4da+PIQkXNpHk8hy0L/BiAaFjNvGtkzSGztDw9 HO1KlAgXtzgYisOZztdIjvU6WPK//F1drzlWY6lY/TnnzNrM5glGF3tGYBsOSUEK5pBDdAYry2eI A7zhDbmPoqU3F6NYpPAwzWXv9j2DvEWWKTKfvrz8LTz/HUDuSheinFyoAwpNbFoGrDb22RfHaoHD e9F4Y0Q9+z0zZcQXklVFcGdnALozi53RTCn6CWS8rzK0dHsFwpCxft/cys33UkGr/PvCM3xYAQJS 3e1GZcZImWozgEvDixu/3KffCY38NJ6VSlElaPcBcvRcL6ovi1JRsFxSGwGK62UGBKBsqJ0Om/sf at9UHCMoXpawmNVGG5zvpMGvKpf84x2AwVmwFNqneabTZk9+Z2RJcB5MGxUkPjn/7fXA312lr9qz cE+vksp+1MaJld7m2ouI3WbOszbFt79bQkUGdNZaYcQaEijp8XAhn7qmTvUxKQi/N7K948MjgFmc RPWLA5VazmUbSmXhgzyr6KEA05agrpDQq1VfgzqSEFF0+PmZ4u0euQztRK1VRy+/WbMBj66QnNXo 0KmHEmsoKpt6rpuuFkeJokJtBU8lNWeZrbNyq8tsw+eOHC212T0jWSejoXAXuY0WMKIOGewzbi2b TNdrfXC6YPGd364xSu8DhiKXLtOnVkmqaNuXTzGRiCwIGpgBFfZ3OsQzf2CcdAH1P3bXGH1lsMis KttxKECq+9AGVIiLJJYqmeV6veMjYzx9r+2z7MpUW1jhvgw5x0MbKqOhIB4j721DvJ6H5UOIZZ7x BKjv5cSTCFTl9zodmjboNIpRSLTCFVd3/YYqpkCN67BY4uTK9rdjhb4Xwu8t5xZ2mgWvLAf1A7S6 PXlZZkr23sutW3PURz5GXrnoGKT3kz215iaIGM/Q5Z/Z9kHrrhTgfU7JZCJtUE+4XC72/cBLUsRv 70po2JSkzsyjz0BQixRhr0yY3yaTVhIHuubPEDfxs7UhuxOQE9EPjmzSfJo1/StKztDr8BwkbJBW d9vGMjhdR+/mr6uMhSdJzGmr65E7Fx+odWB69OB1DZrThPDEttr/MFZATENf6NuqTm7t/KdTyKH9 CCsCZBKepsO9dBqD5CfZ8pJCqcW+PnubUyJ8MFLGp5U/p1Uu34VHQN779NMEsxZgsMGvOLFsXkK1 sNfOcTMb71kUsdT9e+QMaJE4psg+hgmEwvtb2UWCXVakebfBQUdMqpTbLp75Wt7qM6fXlFvIxjIZ iG4oTq9uqhuLvKBdI+4ZE2+V7l0FiNpof0CU+1HE4z16+XISQ5LdoIHf7pefVA0AcTgPHwjZuind HxBX3qpvGBXC4eXndNlxDuyyPN45EMj9CacTgA/s/T0Rf2AGk10fh/qJOu8xm0Be0U2lIwEnfY5p r2HbZyUtP6mShFoZBcytcujjrUM4nAAyL+W0i0H4nmhMaHREe6iLG26zWTwyanYQSdhO068EqkDB ieQm+NzdktdQipqhOgXE98AINXR6ftggjUWg6DVQG+fOJihqnar8A5q6kNXN+5+8Q1z1GMLhaorB Ba+0WRjvl8R/S+KwNJ839lolb1UFST5ATkjuSe1eGZRniLoNbu/0OSYSOi7X+ylT32Ei5YGsnRRQ Bg6hLqQnbvgiKObmpQVOPnOwRcD+bgJk9Z8OVJdKSgebDljNmwefY3VPdyZcXha7j4hx2fRzrohK yr5i6IoL04kjx8axSqc8u3bxXWe3+Kr3v+cRONAkcwdYBY5g23Xx5wutjCOaBfXwGzm0F9ZSQhix Ngu3vpS3u9HZXnZXVfC1dKtq3DBzWQ2h2tsbIVs+X4EPpmnZUw1zWKYf28Ox6L8g4u7fLJao+gaA RPu5oLtcx4Z9YFx1a9rRrL3r54wYnqFAtIks6Zwivr553A4GK1n8KXZ5C7frTkbc85KY3cyDhpTC h8EqWnhpjvPHAMO8gGsynmZ9Y2HuKAeoTrbDyvSgf3+uixYz9QU1bf+nb5h/+rAjFgpTK3l9kY5j eXkq64NO3FKSvGNcsOM5wS/KYtIRHEzzdLzbzVc5fhP0iwB4A7k1++hJpChpb7Svt4H+Kw3LKSCj u/nEhyb9sKz1Xq+0eUe34lJGPrlPOXbUKFBnL8s9J4JBRCVwtB3yBeqkNu3Vv2Suke8nR7dfZD2V vRvn857ejXVIit7mXIjOT+wtwTOQSQqRAYpIcUxAXUB3I5fAZkAw4Ozz5jOujWZcjMbfReSQ1e/N PbbMr00YF32MK71rIYdvaEb2LDpVFjUmLBdoHR+v58j8FhLxQdDM81+tcIPOxqmDTrcu+zGz9dg0 v3hCwn4HbyI21kx0ObKAJPUM1ijQWs5QfYEb234LA/q2DWur2Imee5nAJzluVVqRVFj+p7nTZy0z cryUYvn2qU1C8XS5iwpfwSG+fPI42UPuxu214g+DaZvswc/irK4vYfc+LNpGmvb3BzwRXVEzkEae H/HNmIjYZfOcasVpWprO2XYZmqiL2AWT4d85JzJER95P3pJEBtHQIaPFQKlsDGGj59SQawb165bV L34N1XX3YMzlVa0LI2BiN/CuXxNAz7SpwuZCL4+T+w6RWlSH6bS9N1/ZwiRCQ5nOsFxTgr4MVL6U Mibk0QOKqVIwS0a1UtpQVPQa1siJOOkOryTdQrh4m4HIgAfyczHHtKFG3lrzN/WiS+a1JOPqiEi8 NGvgb2XcWQAcaSnJ284z7hD0C6xO5RtAkKj/tGMOWkjzd08qXTC36YNPkw5U+VcLccXNhA13P7/M I3ahgOH/+EYSf/+MucV90kfgTkQoIrXibP+Zd2E2s7+S7gaDVoIHxpHkuzKLt554LgZsdwKyZBdv LPNfG5Dq+FR4vyO4pgO0NKqvtG73WnxONK8FcdVWE7XL457HGV3iNDfPKEOKJoBHytgcmKBfbMIx s47HlsOoCiLycclDLcao2/2JLY1AZVA9ALL3+T3oTuk0JZR6uFn52D9TIWzHqkLF6oKFPml2cvug x8zbtf9BuTdZO6DHpL49YKiqTlEipL5BQXZCy6Y3pApkETwjrSWvbwj7AfKvr6698IsJfCrEoe8T TXK6d5/1zJBL6hlSwC4LOu+tvsX3iuy8A9bflyi+RQJ2OjRoswUT3JUkssp39vhmWolao2ByOJRx gbUcq8XrtPnW/1wCRu5nzjZCS2C7CFMkupiqdmW4FCMNkh3GJxroPViQMqOEBRxb7tkCaL+IQ1qK rComwpOSU9N0eVQK7SDmg1GG3TJuXM834MmUOdrSOJQPc9gTn6tsDawTmOZ/6oA/nD6dCpzsjyLU 5uwkSKGSqApA3eoZY8b+w6z/7ALmTN4b6Mr/nozVdzVN1hNXnnQVA/ZYj1tT9KcwZfvAC5LqCPxn YkM3NYEx8k2iHuhlUlYUjtNC+WTzSmU5uaxcWay3YoSgvu0znqshJR3J8Qubue7wf0S30d41RigD QzJ/c18zVDHHa2w8oKCV2/mKkBmW/dIUGxRVkb6mtBEZ5G+akHyZs5GoJYR1C/Ivk7zKsEDBw7JD Ep6XtfRi3OJWj1JSXd7OXDzl9tNcEpsHpK30v7b/gja6PhoYi6hZWMLBE5xqzIfP0oaus/CtFtXz T1rDfaPoK/hT6klnGnFd4h2hzEYEN+6EUiFD/O/gFbsgyzRVOqjruHLNpDkvEyS/FK1zKqBVEUts wrC2ryYYtW9TGm8PV2o7VFR3f/Q8HyH75gDxBezB9f4dQ8Vo6Cdr2XXeSpjl3VnMnJwChNlh0VQz NyFeGvFt+MHC/GEopP4xh989bwM1IOLjfs1qOXJqsdXNQ2gJZqIYNlgcwk0/ZL7NvtCEh7U9ma6h YaCNBCazLrkZb9qBwc+isbQ21WHBdQCFIdR6L72SdTn47Wzy2dk3btU+J8RUIZlksNkR5Di1VWKP hGTDkjIh4y2QVhzdAGJfarPXIaZUjn+dIv7NMSRNHIFW+DGMOBpYz/lnGPnRK1SixMSA+bdFraWN ZCHvlJoqYY32xbaXCcsHPYqfe0rt/b+XE52IBnxr6vGatwz1kYJ7lgdMuEumLoovIwnEHKgMQvrA NKP42Ro/2EDp1v3MssI4zgsPyHw5tD6eGbpU7X8bEyXMzgl39wzIlsrqGJnoa16ojjTxiA3IZPfL yZu5nDlAN1SNIZUpOc8u/5x9KdWC+a8ddrYXZbRYnxIAVuFNntOIUzJYxVXLyc18hIuBiEbvizx2 5b6hymph/5/y7ks9PF0PUwNjLiLLz/04feltKNx1kSNVJvOi/PioLXu2shh4k5yxbXpe5ecZZIP1 7LHsxRPgBAGgnIJmlDVXVoF8FMBZBsqBV4YG3d1W08rCdS5/+5406ReflYuMZrsvRUYEZF0b9HU4 bnsR34Hy6rvMdoTV50TwKKpdQLLDic7/N0at+8n0sc9wKXAheegvPTonqkit2wT3xQ5nPwSR6CkR YayqBa+X+l7erABg7xf4iDDrI7/wkZTfI6Izb69cTNQtOLRk2J8zGcalB2VIwRYV4hZo2woUYodS 1DzMa6vQ9tN7/3S0Ng85kMgTtmlHWE305EKyGXG0FtTR5MHa2tVLfOVsZnDeWJgi8zvESgB0gGbo YmeECtcQAOUzhwfYvGUHA+05/Ju2W9VwBOquJVPo0eEUoK8CoxHYxw+T6hAk4ylPUM1DIW8oCYAs muzMsF96OlHoIsz5Hq1bvoCFmTg5htCGykuUnx33DY2XdjIsSfHUt55i6BVsHOx0q8/vXJTVuA21 EhlpZMz1VN8KL1FiG5zezZgFjo4o4/pSQ6G6GGoD2Fo8S+h3I/MMN9rwOs0ZjcoL2bf3f6hHS19x tIUJfKRjU7mtkP0djA4HnlkzdCz6eBYtSUistkXcNYK1Y4lMPgX8BwRu4J4o/MRabHh4lh/bj2nS a8ejGoMWBkpnPVl/4Y87oGSC0iNRsJ6yNPa8Lg0gn4GK3UP61O9mvsDJFNHQfRTce9dsmov5ZKZY NbCbCg2zOLjQJBHvV58Or/R+ijygVZdinfRoKGqihkOT/BdYMrksUcNEsIWb7tGwS59Revp5Ghns 7Tgpz1TucGsKHlXy3hUyCxHcLUQ1T0KeAD+d4sD2Uei9iHSxgjv4IFMYixAaUTjSbWDJScoeQ3yC ZzrJ0j5Tg3DWRp2e/bsur5UaAistJTGFyAfOj+/YgGOWMDoxSXvsPOlhwIae3RdY2th0pTtjZ1GD fDocpisYVfb43o6Ekqkn+cGll1tBKFIuWjl5tXby622BMCxKwHBm6uy+yOvwqy136CxLVwoQOsyE 8ActajkSF3ifbcvMi2+Xj0eSJ0adN25Im2sNtluCthfRvqQpLyPiQX4G1I8FfH7dgwl/lRQY44+V mGhYGf+TqQbPFLSsSytMCZRtWE+FEfm3cMlgpPxn5c3r68gPR0m6msxLhwASrJCXJllGXUTQQ9T/ rg7uuOfN/bvmOMoIFnbW1GfK3ITdWA8ScHXUMSQsE3htxCLN4d+hnvAd1w1aMOGG697BbwvXGruQ mBpqHDq7lIYJLXnucK1kEtMjMYINC0jimNoOqS4gB/qUJtg6rdYBSgpQCPWIpOSRATSIzNj+mp1R j+j3NhzdiPWXFsMsnG/aQ7kWCQMQ4zx4bzIgT9pCwKXCBafZ+h7hIThk1QnDrNwgKbHcez+doJiO U/oRYu8pEUeRukQJWWvKGidqu12jYrnJtFs4Vik4W30n07+nL+HvWuOuW2PPv7tyk1S+kE5LPE3x /3i2sk/3G6E32UkxyAr8pBFAar/ypGc1x1A9e/ADbUxVrw6PFp1Xyk1t8fH+QSeeuAYu/gbSXbjj MulZgZ9A+FmBRHRSoxsUIHQM73yWHvDQ2QEFcIrKYHGBbxvqusdzIrW78nARHYOUw3I2HtNcygJS R3gPU0nZRgKcFRNun+45Ka6IyS8ZLxk/ODnCsjyYYVeuROpVSFBaRdhxA5so5Sr7Y5yPNuCs3OEh piGEhUJrm3EZCHeUPnbwW/yznl9nPOyMPuqoWJ/FbqNWhaYWLdTDmbCJpliOEKlzIQWY3v6CA9Q2 MPS67uqRc9pbhCvGTRAdzl0c8vA5ouEkGaC4S03pZ+jxy+KSn09NJN88lUYQmJCbvnR3q8AwLtNV 4avEXzmtZlmVnspnsZhj9ZK4GDT3Se004VPvdWbRU35+zpMoQfoNvv6CtO2mmgotIvRNIi+rFD3C pq17sGytj+ONVumfArvN8DB2vvOxachmy0AspRqU17srxP+fnB1hiUjmwPb6ax/CYlDgyII5F5oa 1WJvZXM8PnxtKCLIcNjS13CCRzdrk0vqu1RGp1oGNJRnGksIhF6T1JGPafeDI8BjNSztwzlTNXFg qFqvCu5jcbT9S92nQEF4kKlPMsy02WQ49U6m/Uxe6CWez5FPZDcpblTwD6tVZeCP1LUVu/Z1tArM zm5VmpWIHCi1njezbdc46qvNzsIN+/f77aIVWyaT+0ICGPZyL5+5qVgiV11D6OVJswIaNtsh2G+c 6Dv4Joy5cMygQefFR4Ix/sDdPx8YPLFecesVjmlzH77KGgYmUvs1iARC6kly1wwHIG2LbtQsxM94 kTRg0KQrMmrUD2zR351LRQ1IuQpdW0Tls7lahK5YOEIJbLpIK7Bdp10ArzDPaioYpGnOlHI9hHPR ax5LejpCz9KDW0sMNsljsnBP7PSlgl/Ph+QvmY/NxddPnzYslzlm+BOUz+iHIGWqpZeOkgzuha2U syb1EQUf7Gt9/A1zLkTsdD8qy1pDvmmUDMV7Bq+SS/F0P8u47FC3/rhN418m+j7L5SK+PeAoV4Jr ADmk78SDOCyCgqu6tNuC+Hq6W2beMFsrRL2VMCA4jmaA6f0MWFf/03U0YxywBQbNFUbsMc5vbHcT BiFoWiGebABbMBOsjO98chUd4lPBZGyS+A3yNZy9vStcZVHP9jbXSKyAf2LckcKDtPYFwZAAzLFa Zli3L3jmCRg9tZxzPbYEa4zHQjNk+sFi/O5WBQB0Wh9i+pDb+WFsJifVnyP48WcWcu4YzbvWI36+ s7/FMPk/ldDnAq9GFE9Ab48/k0VWKwv/q8NDEKtiI1SuBzuRbWtYRRvBazWw1G+Zu9knrcYGL//4 FF8mxFiXs4I8kInUPAeLEF0y9CzgfsGw1Gw0xkcLm6AOzOu9Bgv3xGas51CMKevnQa2TNJR6WRW4 dahFY8WWM6WyJcacXjFKQfwUGD1nGW9DeNkF2yPJ2DljvtGlm+SArtqT2YXj+E4TwinUgLMe7AiB lgp8Fx2YtA1Q1s9fwJeV+UvCgaG6zHA0rCj6JXpdBUa0CEBrkCGfMUlqg/QTWZRmmwVLcmW7VkYk IH06E9W2BzJ1rdhsrL2BEQRj30KoDyFmt8BLiKxuAozuW6yRgoIctBZqfecV3ET+YtXNMKaIT3Z9 lYKDbkDf92qRyKa89/3G3/uy5bt8dbh+vKJOqXtk56YR6f8InMsQ3cuB/mjaAn7H2gCZ5BU0oB/k M2TGV8M+Jt4ZHkUrNeXd2x/EYcZAPJ5nMc8pitDTAmT5iFPVxvZwiXotmopxgcWw8LudjmPHAAZg Vnzf98H3kMpaNLOyvFoxtNeYF92xCezJVcxkOZvpPcpOPdFCRzQxYn9rP4WMKoMN4FP7rgjRZg4x Nm4QS3NN9V1Hnh+ha06MmKjT7X2yChCwBT6IKeYX6b7ledCmEzhOxSgsA72oV1GJZO0m8+h8evtw y6hVMoQjTJAZVMuobECzYbZMw7Lg4jTj8X6q2eKPAhmLI32F6L/8BYuSKUinoTYadZX3k1gdRucL zwKmikU7hAmKPPx5HMiI9sq3bcxZ4AWdmSNmqbn0xw366KI+1W/wFwyv1jJxvblK4mSHUwQj+WO9 jX3rtHd6iXreNmFqUc3gT8YY0zLX1aUDtGKL8QuOs+hy33aWZKw5U6ehHZAZu1G8/eEhYv6JSf8V zgTYKIolpt5IUCM2KZEq5RmOGvagWldY7fEM8nsEJ0Tysi0Qg1lF1PIUnc3FtWXgcREOD3XCgb+Z 57kRz+H4esXTqbsXx2jJjZiv1xbBPhC212awqtswLDBevp+d7kL2n43diOKgZL6XqTevR52p0lnM rSEA5s1M3kWZIO1R3F+CqTjX9fVwNfNUH32hu4DAKHXCJO/QU7kFQ+FYCxOea6oXxHf0PNgCsVAI O4wlL972TXvCpYJxGekY+y6maTYpPApG4KWXBiSTP+o0MD8O6Ba7xWdD/3YvVZSnl5H3XamhjKER FBRJl1gfqfPXq0LV8vycKL1jeSAbnwnlYu3mPuKwbVa2PN8cTaa9DEoSo2210gEEHqw4CusMS1GU QokgqLb1xwjXafov06OHsoqxZwpmx+GKr3EjAbTrJSNJJH6Cs77q4adnjhYXrzVZqup/ji9AvUTg WMD1KftSDWLhl2x083nYxi0aPP3t9Pvw8UJnKxcK9E0nYzQ7jshW+TKMY4H4OK4ZzGhFKCcQpRGF esmtftOmGqo5AmcTY3A5tcyWRulBrvqJkKGXFhJL5hqNarM2CTvtRHWsPLNg2zZV7BayT/0gBO9r cHj4ivPsNlmQKWQIUkJrM9MIWmag+k/MlTVIOw0FoHX6bHOr989quqfhVlSIAPV3aFgDHqY5DJPo ZTvXqgOlplmND7hXv30I/E5BGPujIqBzPTSeAykCtbdPVpPMJlUVZmVjkwBIEovVF80E7p5qPNcW mAg+AFkm6ooMJY1O0QBMyS69kI2Uz10jBiEdGqxbGGJJDw2HBIG/UnZUZm1t/S4Hhu37fEXYKiUo JL/jpKWxe4ML6ehmFJBqe6d8zczkLfr+xDCGN49iFnAGREh6G5qaNTMMJBtEdBgphaW1uY6WGFA4 N+4AyX4b7llvGZ7I3X8rYdfWEVC5e9ywHt+IV1RcXfwDAjvNBWZc3iqYc4vTnEhp1LRZrW07bEO6 sIhDzBGey2/yi4wkrCKsb7IK8gW+TUgkA+kISkUDP7bEoD5Ib9XTupmj3xdCrGKLrbBZPZcwYMwl FY2THiGlQ7qZ1/bLpoRrJf++IdTfjRzxSU4fZgxao3SO6gkwkiZgu/Sdko9PPqZ0qvxeacm99y5k 89sRtOcge2d8+/X265QhW3hNERq+O8efeLyWzIvP4W8mwaiGVzl370qtXy94slyfMOtI15ZNA4F/ VKmvR1ol7QZyS7HFnBccazLfLgbr4eTE0z7Vv+XgHSrgtmqRkTJSbcV1P8+Ym5F93faDMnpS6M+7 36UipZQEm4fOGyVB7WsI4LeQzZvUsErhKW3nCbYl5Bf0UADZolg/L9vMJjHnVkvY3/EvITsGhXMi xBTR0JogvjOyKP+bDcZYPOnZmD/uYeYlLXTJ05mcJ0JNcKMbZunILETbL/db287Haqne/H0BlEfH kpCz43FxBSQvHn7WBybA8/rkNkqR6IfL6abI8v4ArR3DjTByce1JRZ9kfZkHUydoiqw/Q8cEkH6Z vD5G5WMNncO2wj4PgJ8+XBrBTABiuKuQIL6AyuoEE2qH5wi8xrfUEB1su8v7BRAennGuAkZQD9sU 5L4RiQ0Y13V+ZSCRHVDc61q8/y2DcLWPFD0Yf/BvPp4DMvVNwTfxf1giS9URy1rHdkpOmyMUvtGx 3QbVLcFB5VI8YMQG2fAmLKZJQB3OX1FxhSSUNyEanBo5RQQlyTnTWNL0IDCyTlIQ5JPAR+a6Mqui IugLvYdgupbwPQsvPslt5Vye3OrBxlCH0sa0yAOyxZpfV9wVvnicz92Yo2TSsAZ5qmqPBWEOr3EF No/nJQ9zWDl6UXMSGNYBoCvWlLq9lcQ+LMSvXnkVoz66pwK6XRhs1qR9U12lvbZh9A5DhjqNhTJt 1n8Q21uK5ZWaJjFY8BdXB/m3RnREJIUeR0LnNizwncdRb+qjfQOHknYfg82Ju7HMrhittVMwDYmC rDlznnZDakbYRR5ABmu9dfG8bB+EchpmqUQBkrdwtV8Ui14l0PxcHRuHXKiLcBb16Lp2Uoq7tR5e uQ/AJ2qaK3rAIyQay6UBOgh2mDja4IshPXcHjPBOllFRtRFcnO+9y2BqfJCvKqBiujLb/5L00LsK QtR27SXXMxFOzSBmwDluit5Kfuec3zkZUVLKb8DWrhHOx9umO6YR1MvYcf6iPGfDKgFhDrUwLMTi PnMFVQrp2CzsHfBq7cDKuBOLkWiGBtsHgrWrtRF4Z1j2yqxqk6fzoMn5Lz5GS39UQGfhiHw4ayZO MB/BPodqckocrLfCNfo1s+P6aYO4D8ia5N7fsFJ0pI++GZv/3aZsAgsg4c8f11pdrOKnTIyCPCeB WMQTIGog7F2BUFJAX7W0a1Jh2ybzOK+JgtRlVx4cflN0h2lM49nHhy5fDCyukN0mcDcc7rCOW1g3 +68Pwus4gthCNDBAhnD7j59m1LQJfNsaAlCTOo3oTTsr2yB06xNe2bAG+YwGIvEnsNfV6OeFZVib 9EVfiZNV6y4Q3cMa4GSTedHxlbTiLTxKVb6YI/YjI1XgX7DZlfOlpueIg7b6aEmyEPHCYvIpjuub QiuZgkICuzaAB5/2Kucdr+zUVNsnUE2FOIX/SqEpu9trUXzC2n4pESTVmhYcKsfoGTiQuWxHjJ55 28txehsPKMw8ZZC0MoKKmFFkPhPZq6BzP7qltCp1dMDauxBm4qfzOuu6HtZzlhBuoJ0TYsfVqpUv HZsiF2OaEKV2g7JbY3+5PAL+X0jf0DNlw+isJxCdoYXcwoRGXK817eBcxq0wpN46xTbBwEDXXSSw 85/EJIEbR57hWNK8k3nG8e/fackBVxcZexFnljyTF5qffv2GXE6ew9HfF6WqqN1VgWy/F6evvbSN mc5mC3KgoGbrNQQWAIwj2b56cRmshZqomQl6EnrvICO27nt4/EGV86ppBJh1I562e9uEUyj5BoK6 vWfSjc4Ys2pCJF/OmLyh6z3whIGTQXZi1di+lyXcV7MNw9FOU/eTKzCmdrI9G3Ykc/H5si0g31ti fGFUqtaPJLfNNp2uq7bjJWUxdpQTCz2iJD9G6KdUdBoLnAxMcOjn8M159frqc2kIBI8ZVsprYRof sWTzvbnyF/UrVAMoL+tU589eJC1CulRiJdroFXcKG8N8fx4A7M0RQN8nyZi1C3N1bq37t6Pizxpn l4N5sXHWIXJM4CRVkvq5S0qJ19YiZ1d1Yl8oksI0zhrKAajW+rPjjUWSAnpmaavYBuPJzlcaV853 wsHH/iZhIYYNsh1KOXDEDxqdDgIpK7mn3ixASt0t91g9EpxvhVYOAvbGz0bFlNQHU+lrEviip6gi C23AyfCXSNGyo4edP9i5k3yCGxVYKeVVWF7ZipI0Halp8F3HdG7JwPcJh4pR0EGAhuLfQmxZd66E MGz5JPS39iY9d5Mb0VT2IBla3Iwly9g5t8En+1hs8dfCOSsHk7oyKv62oVFUG51CJdwtYsPJ+aTc cfb1zFTtnpKnUl8i6N4eCvFGTYxHz0NkJpl9izG4nBUsboGpF/B1rVYHSb4A16L3LCfKExA9tdNz vH4jc1eGc0ESlII+6nRiF6/irxWjQxacwByR7Gk/RbP9LHdoJ4F+Hn4IJ/2zDIEMtMYZDawdI+Pl 8hQ40Hi8DfbHo448k3rkX7NUeWxIg1DniSvlIgQOFvJD68YxBrJzWXLFnASbRreh3LBWGjERPkvP DkoqaDpC7g9nyTEx9UfZZcepwhDdyVZq4I236+eqNSzLJKVSG70Tu2PYSbJSEOy5wR6V8Q+4eimt WvHGaRKZ9d4QEGEOT2zyj8qJ4AFlOnRbVALZjUAaU6rU+genN2nt1XD5MucJy9VvQVCL47iJM52U mAzroji1ntj2oF3VW+dOtNlHO8SP4UXE5pIL8jn8iV89RbfCdlnIM5pq1XNTRwXhpf1vUYvsy58m EphFhzRB9tdYcvhZkycfVMdbCaWEQOAb6YbXSCtNrCwTpbXTiSENxjjZFVKL4697Ky+vt/wlm6Ah R6siO3fLBrUVnWsXM3Jiag32WXh6l2ZKrlck0JHuR+QbhZoAgjeofGvNchGe+N/Aehc8Clljwtl8 DrdoBWrpTL5Gdwqzu2SRA+bhH1RqdK4x+2xXwqwBZlny2bJQ9S36V6iD9eI+EsPQPqtBJcMsy/L5 2i6kZ4WJp2vPu9IfK7mUhXvm37sL5Hb6grezl7Ebd9LYIutUUw6drQWLY358dfNHU2NjdnSMA7mh DUNAy5CaA4K9ZT+sj5kktEu6d9lMSdd3QxP5VJpFEVmp7g/ypS3LPQftmtJq0Nhdv60lMDYzxOMX XRDhCjO9nAYFhHyFdqg/ofxsnFKRzaDPenWVV88+PD3kx7SuaEFE03yeCdJT9LPIH62ehh8h+uZK easwq3U4PMM4w14bgXv1x/kAe720jAK8Kg/TN3iMtbNRxYDbvRNWAoyRwkYLoImQUubzji+P8LNM 6lZkJRXwjkYR9dGA7IafjA1n0N2+QxdTlyEcU20b2aJwdeTaefKourxd7R2hrYJmI0428RqyuApr uRv5FrLbehg23ESmlLNtqP+DRCIxcTkjOZDRJuJA/jH2Dd7IgCJID32wbLueJetaYjz0u1Dy5y31 kCLtURjT3v5i130ogBZDCAp2stFBplO9C0tVY8LnhQx8NCTc680gZpiVpZFnIuEZ71MBlt7lTGs+ hlctNchJtop6ZlsrUYznfE7zu0U4fCVmdNxNs72VpqeTeDIbRFrAYL6HnPeqWx/dhch6hXf1NdPR OcXcIU/as3z/3Ui253Dk/jUst4bqmN9xd89NYODi0JRrD4kTIorFLXV2hwHqNY7cEo7OjYYEIqTw GZ9drVhYEGidtL8Pz48u0i6ghPobOCjGsFgaGquWOOb73kP1Fb1GkXohr3ubwZMYaVmW23RVoa0Z U+3Les/eB6C8B8g9QR1QEhhNG2HZpJOC2MKJhv18qo8ITNpw/Pv11h1QXpylSyjG9L3Q1HduYneT k1UbmfEXd0IYu1Yd+2tqFqEDsmwp2ct+P7lDHegsaiJf8fo1zSYdgrzXu+fS99ovDN8fQFUiOrDR IMWvSx4LsxeSc+6TAIUaiWjQjTuIYuC+o39mJfkILzej7W7UXhO/gYly9G1VBrwKqmDC6pKFdnPN hyzaKZ1/v8XpPiVH2Hwy1XbuGAHtgWLu0n5qsUtTZT9jfQsS5rd/RiODWepyM1LXBsn87pQpugWA zU/0UypW7J4o22cWP72+EabOfvibE/i33D5ju64PzpnByxbk5t6YX0R7gn+SbeWD3FPHmzEpicm6 chiu7vUsw9aAk9oZ4ONhSr8jirs9miw2pZaXLv57Tt6Yl3IxEQi+R8mEoDYHSlHcKHnWGEbBV1YC YT/NsoCcHZVyly5ivo7LnJtHUhvLKAjxqKaGF0Oka1X1NSymTgatbqsedeqmE2nYVnr8vDv95FPz odKEM7XL3binvZANJsE9LDEyorKRi3ocaxZJeXzPUzQ8lVKKeUXaNa8Ka1fBRRJylVL2rK2vc2mM U3IOME2LnKStdH7UKFG88xyEJ3JWS7S2yoR5cAhX41f48WLEGNrM9J9SEBsiDHJEpxU1os9HBFqP HV9uUN8Qae2xy7CXZOqj7cKFNAKO9OYQZ1I8enMpMhXJxtdjYD2XoJ35hG5FI3GCqOm1Fmb/8Sha 78gfFTxm7H53dyVXvxuAQbVuQ2crXHcd9S9Cz7zUaqUfyJOT4vfKqjKNo4281NkTk8eRm9uTLUXU VgNpqwjmFoLy/wUR1TTH9XjgfXVxSf/IWBS0VSCDZkyNtG7olvKq5ZhIsRpX3DaIy/3KcZpg5Fjp EYegy4uXqg1CLh9ULh4kBo9ltGCrJg/Q2poaJgE+nKGPwz3ushD+fNpsAWkakx1lgU5WFr4Xl9En vdMMB/QTHTDJSDrH4J6KtUOHjgn26HThjBCaHVJ2YpXFIpzzPMYlzfmd5gOz7JXuPLjwhhCBc4sK iVfvcdtQVmtUXpovJ0c0pWrSU3iNr6DqkofUoRxbLgCNLkYrZA0HTAy1OU37tAZq2A2ihxU8oE+I eGKmrerD19Zlv0GZP5/ymg4SLqPPtzZiAbd8aXKggQPatGqdoVBNnopcOrQVDgYS0QJ16YM1QqFw 15dxXup8GE0KsBBBhzK5dpx6ZC1UAQ9trjrSod9KrXcyQS0jvtUYo6x168iVfRy++BuCa4MsjGdM KxRSOyzxgLyVUQFmUJSoINWZyN6jCb2CAnTTzJa2bZKawkKStR2n5zY1MPsC0qsCbJGjFgMEoSR/ J2wdb+h+9OSPT3cu3hnIHr3/9cqNDOHVOA+S2BXN+2FxVgQZYUCLCVBO4oNXxco6SRDiyQAg7T6X XPmybTarXzgWXNOYHUKzA6I/TIbMTzBIJK30qD+W+EKs4rfKfxBbl8Pd/0PSKzwIauznxQersrPM 2ZnBmvLgmpAJ5kJ2GvZtGMlvRVzHydsGJE0k4WeCpDbddd2Tvt4uB/cD0U/mlp3yalX+C6yEXsuq R4H0tf5EMdqzSS5hxB4rGAAVjL/7bL/VekB7eXoYu+J802XnFuhsdaiCoWZGPuKwMtBPvT2Zbk1+ gEsLa6wsDD4ErbVOHy0JeLELRkGWYPmNKK0sVXuO2PrMHje8qjqtCcIxT5zFy6UpMRskIqBDl9LI asBlAxmiBBMUlJh0MW9kDEsZ3gkTBbWtOYurdi0ORS2QOGFBfxqQIKLZWGWN/Y5xoI6cltOVgvOP YAtJdQuJlNnjbI6g3jFcNrl+CqP0bqBJPN12u9fB3Z9yvafCZaoC2RQC6fTJ8CybuaHbacipeQZk jDWk4FSkmIMdMIpixD//AVEW8P1bEPtss6B2UNMaXKEMa5IA8ayB1vWT2qfb2xFVQEcOdM7QUXmp g0XARj0opC288p8mZa+OV/jtPA90goKj0tnzaX5wRIG+ET0VfxQ99M3/4LLELbNXmHXXfY/k60bQ 4Lp/N3aZf625cQJ7qGYzxj0AXByajd/SiPs3zbWe91eghharIaKO70NDrEEXaQtMVjzoW1BL7kbe SQ5iWGG3Rw/cSYhkg05kqrG30As8owfOTu7tyXgPXU+90VU4pUak+fIGkGDzCieNjZu4RJHCFuCM rSzl6qj5+XXPTpEEEdYDB6Htbn8XGGPxlTQ7gZcwl4goC6c5yxH8lU4xv812CqbowCmLr9tffxVd jr+b5c9UPUxq6BgAD34Ba1rZwDKYMPL0Z7WZX8MyS6D0ibXNZ9NG6mkty2wJNQSFYMc2REzsPYyK Xi2e6w5Gv+EDnhqk0MM4cmt/kjU9b+qxIqX38TAMPQXibmCXxUUxM4dxwLB//TmqHEei7uFWyNn4 w6hvWKUE2PR1kz0f0u/8iyM7g6+khZPo0MH67vF5CTE53LE40DSFnkhv9QorYk9qhPqac8RQgajD bH8nBZrg2sisgSZgC1II5a5OavvTgpJOwiRuhuNJMw3PHuHA4wDKQfnCZVowUAy2NlY7Gr5Vp3PN J8TW0hF2IFbhe0vUW15vvZT32LCbu+x/LPBLvb4OPvY/Nc2waGLbB/IlkNWyjfGL3wbkaAPxzJIy AvaFjbPir0UfVfXlV4S46nBRZ+tazPfNqbceT38LIqkwWI3W1Qqlhjt9TaXq6Q5Y/DNUiviViB1O zv2+8N41nz9dpRGeOWouiA7J0OC5/iW7nB0vd/ncPqUzXGDlMl4lo5lMFNMKe29GZ3hqLLaomecM /4eSNZTlHc9DM6/9yCMdXDNSfPQ8zCAw2/W+r8SxI1ULyR4egy8Shim/8yEODAW5NIyHOR1dIq64 Hefhy/Laatd+AmgZDlT2LVrOFz0MzJETpMlnu47wGC5jBC3xe+AfvOzJbUAfyDfZMOKbAryeeAht 5yvHuVr1r75ujswomV/jfuG0iiAnzVKHB3SCFc2nW5skNlalQffgLiooQSx1dm7JkObWq28ORxgC Oh3PTWsFKm9Y3MCHt64z57znqSOUUYKH0Rpc/ZuTjNRZMZ8SNit/ccpopSwDdn1d5Sv2PCOoDnnT OyH10nCQVnhAeuaFerEMrdI1NCHkun1eN5DmzYNxv3lz3fs21gDXk5UTCzWSikBsLGQZAPigD8lH kbuaZP2zIiWrtBbzewkNbWjuF8AeulJNi3BHecuW7gg0+Fl0agOI3Eu0YTDh9UOawiaTDio5N1zw pKpejCiiIkMSAjpJFbUgUfNnTJuKPpsylBDwEV8dg5JqO4YSAUZGIhYKRsMCI703caiIkoxYrsI2 ni5qzCQ9rcc0Nrp1btqITQwPQm9dGinneDfaSIyNifIm2wPiab15OVsRf/d1m8CdMWvuU/ufs46u vBYoLXy5GrP1AMJYHPs3A05PQ7UzQ6PgM+UYZgQBTKBbre4K505MBH92qhA6JOJpTaf5Ur3gGRLl QExHyfRDcxAe8DM673HBvsROBq3O1EcMAb5AkkcQxXAKkC2fMGDsGttoy6jP1oAq3yixbcuWLs1s +dpqFRnHvSKx5pV03yvXKGPwERvRk2TReqHzY8wxASvAtyFr44o8F51rN2rVSiyMA2dktu+jWIt6 S27UBRn4Gu+0zqeU8u0dg0qEYlB+2nNdlLnaUOi8t87aKMii1RipGrcO6LH6kBQQrZuHoZQIxg3E MZCK+lXCTC66DD1xrJxZw8mScepHyCkV3po/yNCoPfiDirR3peoyenM+8nIlzKnSG0UJ7ZtXyzWd 2tjzD5es4aHDvQFLNphxSpdlen8M2i9290WK7RgEkb4Y9k6gKGNtJS2YNE54UXL97F11McRVicn6 IAvKo58f+JW5WspWDG94lKkAmKNjJvTrVKSHw2P/ONZtgCdgrDXVv+bBuRyzY3c+56bOzmKv7ewY cYP8IzHD49qkZ2L7Hy+axrdNRGU8jyq4Bc5EIRrrOqepux49brtKMWWgjBLaP6eN2l94WbHsAC1u IWVT1rXxtcagSY+dG5w43R163io8ZQXMK5NaNk6JPYr+PHiz9KYNKMEA0Gpi/OvG37HB4AkuZXGv 6J5vfC3JvhN3bVTM4aeJuggMXgF2qS/39rswbU93gxawW244KCaCG6VCV1Mejxy+LjNf/vHH7A4u C+fZkjRd7fRR6zJnuAzFy2t8dniY/RqSdAPcmtbyrHJGOOQbCM7V38qOayJgJ39LA3eOBiTl8HmU ABFGaVTqgkVUvjGgZ/s+l4t5Hv7FVoxDjKd8FF5mhxTy6J72wqcXHoEqC5c3rCiU4oupgYHygQh5 d7eGBeRZTdw8GpMkI0b4TTTXD7rNql8523zDy0iesdzLsHzxOPO/nmW1iapm+iitsQIrIAVGbR8n WfyIT03Hv6o3LgIR+eCgjMQBif8joRxOL86dpiIptASrvX10cIZPHFxNH7siyQoIyRDuf2o4Rqsn S6vmOFLDzrasB/+k/meIkclkhf4fAPxweqbAHtcjKwqQoFJGYTW0ib2P1uWNtF6JMjioNOZil1zr h1osjHq0BCRRydW61pBF6nr6LZLCwOXin+FXx1hIVejenXq5En10+ux5xu6pG5ptn0joXZEqU4xu tv8nGgCCSlqhUiSouTOuQp1KJsw6WH/oAu8mGSlxE+zO8TN+y4F4utvxIBb3Hr+Ufi0U7vT1dV2W IXOVawgffrB5eEjcSuMq+nOhoFvkhr7l7SsTWLun6+ejAlq11CBvfjqnRiSE5/7SZr/5wnDRLTt5 DhlpOFsUZMjVrcrCy1EMJ71/5unEjEOxxpAkgWQCjsAsx9VEe6Gdn05CU1x+hhyFL0UzbWQMUO4G iAbkS3CsaP3JUzOrdS+dzfVBSemu+0YONYpKxp5qy4r+E6UrX/uPZR++acZWx2fAyTxlLUpR/Q54 PIe3Kt+SO2kzVE5Q3E8U042HjDAHS2Tqy9DP+w8MlAd49ShKErUWWM7sCc9YATg3wsZXbLWtI7hw g6bkhoM+ScfosuOcVezV7oBdijr5QGLSvmdpHvYd96EpWnqb1/QntOYMbkZRKnT8QKGtAdvOo/tU rpXkHO6vMBa5T21wDUiAmzz9y7MCPjK3DHYG5XvsdTIcjkAnrqC/nJXzUUFvN/uZVmnD+z1jNnL5 HQiBb0G5yC4sOBni7PIcJxsOWKC5uMKR49eX8wQtnIzvDQ5pFZatMt2FuJKRsGzhnvZI63NfYH2B 8KyaxrcMkH55C3pPSk40/GxIDONS/DGoON9dYksLJ3lkrqcMJbjIEr0PHZa4pfZkG3dVL8OD0M3X m8yJ0WH55jyVlKD4QAiOfY3t/72N6qxErieA6c7EKMcW4prdeStUyq0J0JiSShi9g5OjQ8DhPIVP rR5n+NYrLP6BGI+YYhnpGjcQNXxxyaR4p5gmsPFxOb/8xsUyXVyYcAhNb2/ab30+MKNjukHfvOn/ bpWZCaE7AjEUIctX7hbGezjrdp41H7N3sLp7wQKqs7ZId1wHAa6m0u2T1qDqA/d/KpT50mRZLq0k yA/XCvf1Ppa6fNAI82iY5SM8VRnTIdVkIYHH1cY8tzlAVynK20AZGG07DQnY7fJxnswar7Xw9ai8 Ei1DUMJrzzLBfSnkrUxlIfLs9nf8BxFqOLZEc1tcZ67xwERd5tMsAyUixxrLSGIcg+VX77OiEfHw lnzVfhsnmfpqDzzJWieEUHVeEVYeKRNDiT1jHAklAe18haBiVBVsmItLp2k+OBF6kPEtVwpZtVr/ xR9kJN4MHUXcALtr67v+i9SGy2doCcBFscb6+yvMGodsz0636Niy0tNsyJ+6FoABQp/1SKwMXnxo ihcNw/s1Ryzvb+VVGim15V+m3fPa/Sf3XGw9ykWMBMus0p/tBvdbUo9aTsqY255H4STRVjRDfPl5 iy+P1X7cs8sGkjcSeU0GLeqbqsJ3n+bfaKxKejXag6eY7aSKb9KV7wxL9TPsgM8N0qTG/RwhIRgP /NI9ypjuu6SdpLkIfc7meOOPvZ7O6LKsAC/QsvSj0mAHUMM8m/RAh+MxoVKkdWTae4GsH2gnXY96 sWEAktPFvJ9qhbItkeIRoecibwAcQFXS0atsHT9Nk4ZUjg+4Xwgd1WSItC2CMPDJSbz5mH0xazQF HoIZXmCIW/fOVm53eMl7R8PMAzA43k+s34NkjmzqRAt3ICm1SZnPG+hxJFluAtQ0kxvLV53Ji3rY 66HA56eOL1WOh4z+IRF2LWEv8K0DsN+EFpOXHC2vFyOunvwqRZIV3FdI/8P/3H/kR/1QoBI0+e4Y U8E+/FzB68bkGAS8LvFO8pIdbNqmdSb5tlg6S1iWP8BlrQMdSiqb80P01+sg56BRJ4Fuz5uLb3b0 1NxQU3qv30G7wnBYw25HjaDibmo7Y5iJhJk42BoDvif7YY0AyPLC1BvJvV19L8oAwwAkd+Xgv0MC LHzFQzVGdwi4RPfFkPolRcfIwnIzzK8nREG7fT0fgHO3J0ECbb5jZWrBdU+2qQ2YhcBcmws4Omm9 qBSuel5gZjNIA5L2zBNsDKEWjmBuyLIaUP5nv7TWGVS1wP51QlYpuWIqj1uyAIH31gfbRHtzse8F /GG5JzH8HS/+i/tGTcAcxXBorXOqChBz9yJmvPonEDTZ99rvlZqGndjF/0cejreHstjm2cBy8EuF yirb+RapF+G5qANzQ3dsKfK8J1MuYrH+s35JdeT9s0QjVZ+FZPSUp7yoySBDOAuF7PioIgnp4u/s 7FKCEuaY4C1TOvm62vZ9qy+Nvg02vyuMlZ5bZJ3AGsoEuVDStwEFUQndlZXp5nt0G5w49MRDf2Ws w6HULZBUiGfDrMkqLawbUBi/lrTfY1HzU0o03xHFMc+5jQ85GZ0mliKbt8AXBfApcMBw66YUGnuu DH7dcIgcu942GfdjxMPLXPkaa+hUbgbCdfgpn46GEY4ozaecSYAaPvVnxHkdT/6gVD78XAVxPIEc s8edka7U1pQTwx+prvl+IyeLj9q/hZKUN2nbdMmnQVB1l1inxamSD261zL1LRYDgKp5thIV3m3e+ qsrd/2Qy80pYjRv7RGNkCEl6gXiiYxV9kNyd9TApEoVSPBuuMTwy6MIAqKhcG46cv6kymt1x2Ix6 75/MEch1I8Y3RSRqmnCys5rkq85kkGdO+IlzviCgMuM4+hahlP3JzjFbQGLN9EAAJbEAmyPz2Dve rBDFPGbX+7Ne66ekUrwAJY0srWcL94iXEbq6xx5OMoQpxNYuDHpl5xhCI4YvYSLJSszKY1ylPyvr VN7odZyPgEIFD1PpMorcL9wT6o3dWLJh2EhMQ2wa/zEv6ZJnXOGWyM6D/DeyAHdOVGIagGyV6g4u Kipl+w4RtrASsdbQFQmFX9g0pVBcXURlpLqXNy/arP2rIqJHHtTq+i4On4ZusGtG++YMU6ZD4FZa VXSTKEDxlRDYAsxjy1T2ishRir40NV7qpUobJ3jIAyotdS6ay/j1d1/CW0db2QFDkRJL6PDU/hHh LRke6RHJu+uJa7deMP8ipRPHCmATvYZr0sui0am3wjk+furZG1D7uS2Swv/Gzw8IOsYW258rcvhG xN8n3/8TTP4e5rPWUY9BwL4YYh7yS3PkkJh0UYDhP/8xWv9AqOHtqs+Ib6MarGGMUVoxapBdK/Lk twirt5HWP4SkgQCOYH9AbZxKJZDwksymm/gqC0uNrwUSxj/REVA6Fvy4HPTB3Ook5EIX1kt5CYim e4Z7SkcIYQq99tz13K4YxelXsoCWe3UKzX0eNXRbvwCkkIkSNVRUofjmVUlLUMG2CuAID3kS43LE GsqUaLUf6aNu+ZZp5pEAm7q4rdyqWhJxkuyq+e6T1PuJCNbatK8yrBPGvj/NaWo04WCVJFX0pb7H bb9MxYcmXyBsv87U4P5vY4ChdyQwMuxCuey8I3dt5iKg9bTeiT4Bc7ogF8WMR77OXnthhS8hk0uR vsh96ldE/AOoyqdG42byoP73LZzFl/J7rVa8KkUzgxoeFl3GhEhWbUgrXfKQkl/ZDpqb2HmwJx0X IjDmBc4ix9kU3XEDDuuzd2bsqnc+d09sJy55i/zojFyTRbLLtjWZPDmWiPY0pObHMcX5SUo+tR7p OA0DlxDD49YMxnT+WdJaUhJoBh30vIuXTu1zBU95zocSoYzdK+SPEBet2DJKyb14MUrjm56qD1/a xcvnexrDlcK+za2avRyg6T3zRiWVCUn/LQ7Oh17qijpbdu89AtjnsWsFTK6yFzWwyyjwHO73NnUm h+x78oxg4kH72eMa/pik0lkZH11Wa8CNd/PZx1fqeADsK5hJ/piehxokVpF2V9+QEcjGZwcq+Ilu tyq9kDi+t1H5/ZX8dVhckGWR7B64AbEj3YarB75ON7NVczCxRxvA3yA/8AjLMECQYJVKT5lSWJ5K 6DjjKvn5wkm/Omne/C8vs/k84R+9aNB8BDsw2dtBkPIokemcMRBlPT2tBELG0dFsQQRWAQskBBuC PRgU2lH2QT1aKdhGFQpNeNhyH+sWG9RVckFg9XTHIKl1RO0Ma60KYxiuXow3gWgf0OaMqJ0lHY0g A/AVJETotj3uO5eNomjxb5/bEGz/52o/XuhVzNmGVzxkIWCJoRjMTaKqqpY+2gD3mFSnaQdlBfSd NTr38fCcXZvkVlYhLegx609KfB8bhbK5xSh0CruFR2j48gB85zCfYpKGsFZfBI1NMRBk/uVtNRw0 xdnwF+ipAuqWfY4iZ1SvNnsAybB+54QzMkvuW33g6CVw5P+53UmbFKP1fXbPcoU9st6bbXHA5yvL pzf+zkrLqR2GTL1hw2SyDA2b3ozyH9kXSZXzML8itJHIZu/Dben+Cc1UUjqd66Y9cY6G46wodJ7e mAjnCCrh2pyutnXM8Jj7AtBKE29MXwZMMcnsAk8EFs4GcMaDpyPhD1BzC2tiFCPULORs4n7p5Xkx kxJ1dQxer7JxC8FZFTi7PCy9c9fGtjENo9+nU+s1DdNxIxtQp/zvgx8MpmBVQd/2ps1dPbK5f+zk zJkhlPCOPeXtJ+hetYYtZBBZ+D3t78VLGFbWzmu9M8T7FiK8Jk1jKVkBknFFDqcAtYavJAbvh+GL pIzI8MOR5Ul2XTdlTxECwJM+RYfUv9a3GIw7DnRQFTR5+WkWt2SUQvynKOK3yhCfPvafihsFKHhB nEsSzmCclA12bcDWRKJ0gmjqP6IhtZBXaQDVl/6NTNOC6gMbUp1K2mhJspL3cnLY7lIZNgoXgacf DprU4Nwz10zPeXuIrXpvmVPvU2wn4RQrgqRVtc1MiA3UMV4ESMd0gMa6OYzf8dpoqABeJbCWInOc egjh7ZwlblLocSMWACuQXzo7oeL83xEZCHZ+Q494EpLITyahC1mfHEk8EwLdeSiDNQ+jy6V58cgx pSLc/WRDmD2GTaII9uNFFb9j80lqz3t9aUTKvVm4jTmE/O6x9ljKFjB3O1R1LFt8fZgFEMd2oeQz jSAUoPZhRxouNhn3C2dUKcoraRGvSDWvTl/qJv7SNod96OMdkKt6llrEEKns8VBzxeLZsAwy536X 9g5qWtyWZ7jwrdsYSe/GfsQFzg+M+ZWWmQuY0WjJbr+f7AiWA0nLxTwtxM8UUoQchhFE4VvXUPRZ LAE0uuC9bAY4bRBRUoojVAAhEET9Qt3VYGhwyh4pM9byQxNteHYaf0CWzCAUrmsYO73kmKZ4RA5V JSptj1b5JKb1HCXwSFxnVIGMSo7EOw5o0nDwWcpNd5ufaKEAVPsII/51hArKFure02ECm1PZp7C0 Ke5i7PCmrxB33qvHYj4SmmdrQSojZ6NYrUoz5QsPJ7+hGPvwmJbmyPOg95/hB5hL8mnTNvm54EFv 9eUTupRBj0mSun/8q9gRB5rn4GkTyii28sxFLY3vmZyw96IG4Nq9jLGYKEPAuek827i9aDdEK//P xxT03EYhaIEAbuUEk0AoWIsxmXNaGeEC4+jGYoY8ywdD/EdtGAbKKluS54E9WdVOj+VBd2v+pkvt ja454f2BGd6XOJ5GPPLZZfzoZTEijaAArerqc4IdyeUpMUUwwjmAIbaWmgvNZQfXzgDRHr2/1cVj wrxAPDdtVLRAXa6ybpfM8UFx6C3tK+OheJYgh2fqJu0hYFhXyOLdo8EcRMvfY4/E2vCnCmX6S3Tl r8l0AG4waZPv9Z13lqk0Hb/nPKn5eDm1XmXvFFuwaONxdcbf0+fmZ7KNkM/eObvzj4g5tH2FRNiZ XHSZHX0zrRZRtXOicNiRle/nkw86z9XfkW28ZAm9Gz234vg5i2IrZ+8bCMZ464lk3bp1UiEJEeym v1VXNNHbpEG3nf3niJtdVv70L/7lCO/GCofBEW2Rb67xYzaRCO/s51mXijf2QShXrbVyuG5l9fH8 NVSHCGCwZt4n1CWnNhZkEG0F3dutlg6qx/UgPe3PR1RPFpdP8y7x1EIH8eMqMfDXNZ5gfYAn3Zo+ uTDjL6z5FdFF/14UuZVP++LZKloDa8JWzUM3z54yd+OcNyMVWuwz2CW63d4ZuQM7H/asZ8RjcCZ0 H4XziCwas52fZCJ5Ka8uHqFvllg5w09SNtezle83iikCQBQNpQ1ykS1bbZOfYHjIwxQ001Gy14lR TPQlggiuMjmCRowHQE5Np7wc4wlf+u14ZVgeP8Uks6IKqWA/T6Bkd0ni8OWtn+jtVyS05ZtQujz7 FWn1qjy5KGW5OK9JTosdPFWqLumGe4nF2wSukevgbSe3akpLB45Hv+5c4XE6gY4vVVdREK5ffw5N jJWwl2OSWX890cqgO/eI7Kj9yxgpisFnpcGu3fk+gV4e7eClbCAZTdD76FJRpCOQ7GmnxKFSiTNf duwJ0meM4nFXk+Zz+F5rjvIeQhHWBhc11BD2+A1EPfkanhVUm7LvB3XjU0wmlCo9mMPLQGvrg4qs z6misptVZWp/qbqtMU6+u+ansZ9Oj/7PNRNUEzOE1WJ/FqPmPtLgTP7ARpOcrx8QNKgZppcn4byu uUHAq1CdjXG+MFv5l8FTkDol+2pWI60E3zTuRHleR1iaJws+r9tu/YT1mX4Q7lxSygpHsfF4ZkYF 178RTK6U5XhqJL4s/TyBnbFsh5ppxFn/iJqTWXRubdzisLcrEhYr81mjkw16NugVHJK/X/fLfrdy e3ORwo0/YdjSpcMSUOsgPxcZDS7tXyNZPe2YSrOYEL6EYUyBjR4p+EInnctbrABD1RlEthRARaIY 4O0K1YQAMEvKWnoUY2iPg9ngYOCCKlMGUogOHkgM6dJHKCHtheg3gQxr6zxKj5dS4ybvBw8P7ymc 90EBiNjGPXdmRwQwk/99qblU3KLEgpJcq+4o3hAYSjIGDwTMfbiMEezzxzvIRwcw1/eluM440qEm cCjPkkaCTpaMZPHXaxlyt467H6Ijw0hOLmI8LnYx8K2yq2WMuXa0eOFgAlP3Yq1ocWT15Litst33 okNbbwxthsSZjIFuaGADHCi7wQgcyzuZ9tLWnYUF6gM0ytgrpdqpxbUMBXFxiuOtkIKwMyqQc8k0 H5YGoiGpjMpA6NkeOAHF+eiLoSXh8bcdmzcmZ7SNTf2QZIDxJZrwy65F4YzZSQad2PsrBGNf2EDX l/ev6QCNPSorvd2e04ZtH91OuqFoNpY7NSLlY80w23+Kc0xXjb1y9FGTeRbD6zMug5NxMQ2VGPLW vJrbIsgl0/F1t4XfpO5D9D6+gm1D/wTswFk50de53coHi1ra8jwv8ONuG4JdTOmGHMvP8+rfYt0D +Pf0hPjFoRlrXZ1l6m1YQzyndggZ8Irn+5cPUczMv5hhJQSVCZ7Y3ZjSfs3guyiAEbY/8OQoC+xg r6c/m5HuaoDItzTuFY5hu26Sjwr7YKxM3GHbvqxs81U+aJ1HHZK5kGVJYnEP7s+9MU75DgBBMMly WyzkIQCB1vKO5v0YCtv6bwkWeBujl3eocxV9QfDgYr9RncjnbFJ7R/q1EM9MrxXLEw9GUokW1G4x 2UdA2Aem/qg8mvf0URF36qrtsMRce0KOtHrx2qeF2LoEtypj827XZQK77GU4cTRq2PzgYZSkoGu1 5y5G/rwYMI0p7JKEv8PxN0ckLgf1xpQp3UFoUlpuyyNkxhDwiB0QHoYdryPnx/oCEzS02t7TJ6YG o+QTj3JJtI1lFAFaBQr+4RGIPAvjacIGikwxFkueTWqGJbYfWk+ueuy6QkdQDkj9stQ0TWfm5nYz a9QJ80VpsPuMGqQttNsd7Rt/x8S7Rx78GIV4nodJoYEmQY2/SrDKeie01J/dNWzMoCYthIDQ36+0 7Gatg1ey+5MMC4T8lKJeqQ1VhkUOY2q9b3NzDD/N/n/G5ePuun/4FlVvFSxUoMl6prElY5RXG0ri O+pW2iEpOSjt1FTbfZOCB7e9zJPj+CKob2gkqL0r8xPE874PnM65dzdtD/jOqgzXfNq1s4bo5xXu VtSj3hH9XqoZNp3+kF0YpgqEDrAKRTLSGlmCdou+do3Xh/caJ1kzSl1HXPUYzWKuCwirNoM7GIQq JwpNg51gdWOu5s9oEAUi2aLKHf1M1XlldjEmKh2r/5QEg+rUDlPu0Dj4kMGOjXAUp4D4Z/5KoVqK 2xBrMOQ9sEPRVXTOp+00jhB8wlbughKZrTW3822oksFEJThZL+86muOFbsG+TnBGlF3/zM4xkf9z ETKF7FtVcZg/fZryW2utiAxMH479HwFAIRKTWKoKR4MnaYXpQJSziVlVKJqgDvRI1v3k7fj2EyiE Yt2IX2a4sB7Va3GncFKRYutaeP61obYBBHjAmF9S8QCzUM8Ooz1yHrvEONtF0Ibq1jL1hmQ4jWy4 3Nelc1AIFIT4Izg7nGJEnsZWOiX9zItVgJsdEyalTwc44qsXWDBUtG4FfphKt1x8XpaNqSZwn+s3 Hncv/MesYy6wDWjsnIveptIymehDdjMir8EDRacIJ8GXggjGz3xIc7thEubSVznptD6jsI1LrWhL klZR9TxCCOKqhCxcbgX4uFy2g0r/gCfoNWWdwKMkM5Mzq0VIjyam8cOsh1GqGAZp8snLvV8y8jra vNF7dzrQaKD0uA42bVNrGQMNS3OLOu59ZpsuziO78THbgJQpJLs4/vRVkYPEOs9+AXevbKJl3gws +jgUTaRQtSPJKSbZWhPc8Bs3NTZ+e+9HN06wacXsAV3H2qb3fPvo1z6J5c6Fsulp1g50i3y3owfk wnPyUXKdtcHnIdZdkjRNzN9G0ZEOv8kPOHLq1P3BlLgsINq+BuaF2b+1FaaPpJ86BOPxmjF3On5n kU/F+Oaes4j/sCcDKIv1thh51cXIqPVNBbhUMV2dWG3imhDi1TQxA7ZhITBkKiNrGTNiCOHaC3LR pSEnAP4yUvg2BpR9WUG/V465aw/Smxi9yteyyxtTJsb6XceEbxqczK/gTUrDGU01JzDnccAMtj/Z xH6oeq/OoR7Ti8b4WIq/Tmq2j1arAd7enJLFPTKBwxcinuN3KfKD8VOEjT/YiuuCpQ+6zOS/CriK zqmNAsU7fDhOW+8pG6iYpyUsz8ehlNtzDMGRrq9lZphegDOrGlI1V01GiwaXMyC1ADAp4XKuQmy1 9Y6KecM5zyaYegi5BZVDUk8c67LiF+aFHd7q8drpWXrN+0yhvJ1TRU/1Z2ZYWJgiRWL18G5CXxac +2cLbcXndIbozgdlt506ESV+mF/ibsLGzU4mJ6SvZemHCngUELiCKMQpyhEZ1chye2GzCykOIgJ0 FvsPpRJB8D71JWVAdzC/SnCTyTcSs+aeDetPX/MzbvHRA+bYKw9NGSsTZQxOzPbJg2fCBtNOGnv/ G23zs8D7Hyai5F/kWxITskuNMr9szuHzaNxVjp6fWJRdhTiG75aZ7VvFJoq5Bt3Q+BnNo5FUVS80 lFOOwUDHJPj9VieIK9gmKr4H/39Rj3RsT4LPC7+/Xc+/Os1YyHKXxBD1IoGv3zvQb6jvBEphINjf h0PPj+BLl4FBDATwoARjYGC1568lRef6yUoJ/9q0o4Lqle2d1iH7AZHuCfp0Dy1oIbg0IUK6O1iS ZIReS5eXD3nHqAW36GBwZ99sAPilaVZTmCoDywfgDSIRcMdIU67z9LiFkwAV9ztB/tmY4hU45H9m 6hYsMjB5bHM6Hj0oxpu6ahQqyIL/lRi9ryHwGVRD5fDR+cVz0Xh1vGiT3itRuV2GlP51LQydGeJM qTJmHj2uAEzECyRaYv68cHcjF7wzgVojMao1u8q1yCeDsiFXUSks8Wfs/26X0hHx5ui0tiXFhrWQ SJRBclNntqq1KfuzsZ9xnCQ2FGuKfLLD1iHYU584iEnH0BQFLJB4M5Qeyf1459mGD/MEqTJUWMr1 0Bo/Gt4LPVabmu+NLg3zRyO5Zo+Zuzmb295lF/U2C7ZG+nqA1okgkqluIUPcboJG4EmGoXJf9Coz bg/529B4qF3IXJidUf7oficKjqAzID0X6z74zuvQh2rHHJh7yHRZ6D00xrzTTC+HEBneJyg0NGDB 6mN6GRkHFRMThYFLbENJozWTzia+Fo9PsnX4MfkwjSYnZJcHJFoKqbqHpEj3EwUDGvx3DBst54uN wd7p3heFgSf1kSNjHcV4LnpIM5ic8cYFrftdgQCEvzFZbSNOt2tc8AKOdrhYuF5Qo237AgQ/ITJF 34lCLiENNvyXYlhnSocs60LOJodKk+Ip2LVb+G1tQlINQSzoAmj5ZftXQQXGvB3w1cNwwK6vZ3iL 15nV2ZwsXtKEbZY+VkBwzRpCT1TqJFwIOsjTs83ojo8u8rmIzgtXR8Nn3BxDVpZRxLvfUeUx1FMz qEnRe3LcHtvWSD8O+SZnElfZaN71gO8oKrnq2wdxGdPTKIlZOqehICHXLL7RpGQwAa/xPmHFIJrP geHolk4rzuT4/VHJq9h80TpJXdoH8yCCky8Mb6qpX5+NDPhPAK1P2kM8MWPvInG7+vPM90kw3xVZ xNq/ZQKx3zmWMfVev5jhGIZ/miwZe5RFAUsHLc2TJjmBUNGp+OjdouRPzeay3PuaIKKjiHppNUKd gh8/aArnACuDSsHo2r79VqxtCqgILO4UeEfjp7aGRs0NY54LXeOInlGt6dN+gqqg7+gl6INjO0BS nQ5uynoKGdjOhVEs+X7wuJouMtQq1Y7J2lp4q9/JeuKqLQyamagAkcftMdfbHHX+wfpmjG5UDd2c rxVJaldFhDbhmyZpBQkI0dzAes2TSI2tcHZKTxmKr3LPi3LL1kHAanm18vFXG7fw0f28AF4zxsk7 U1qPH0nj4R5sWEdZlIXkTvNwreIhcKDQ/1zorVmC9xm4GGSPg+Aeu9gKJhA9QWDjgygsmlpsarY/ 9NB4QkcZG/nx9Mi/6OoP3qug/KRW4WhiM8tKeMc6RKO2Iyuj6y/w7uUwkeCB/5+9oemP4NlCI4cu 6CcuyeZug5sCFNPsnMAAP/Gw8QhGcDdoMU9hi96fhI1A28OadCbdm4rrT0Uzx4b/2AUd4BKojghX GuEjxVIjIfz5jKBQAp99+8eOFs9YCVDjsKV4pz+Oab3Vvt3gjRysc99bw4dgzfgSql1kDjKmtqU0 urW75cyAZzZKHW8S60oJzVvuqsvUyj5SyrsM/GKD9WvjH0bRyYgi252u5NvMbTYAJmEeIJiXLNhn TKh/rHuzMr6zueEkb5JNACupmVaipSxT43yhp/EhAQ4t0JkO2NN/qbYUM8HNA+M/FU3G5D26h8Rf QPXy8nhhfsvFo7qhT1CBBRLOJtV5pGjvl1BggaQG6XbvciQsPFPDzLHmU3MG5q9/d0hFq9T9fQoE SwgVOZxNdVJkxw3TwizI0/LJMiZNq2Y1FPfXSqAMHbJtRvT/C1CKhECeBuvB+ODxXXFZn3bhldgS Juc7KUrS2UDN1UWwAiqckIj2H7FyOg9vMRxxETM1JTSnZWjvrXZC5Q18TF7CPWQIiVUwze3MZi/q HdC7Qzo1smHXOuDXuFcw9nmYxCpADyR93Lv/DU7L5cKjQRo7Rb79VInoYMGJKnGkwZMGHiabp2Tq WNmLV06YGvlk4b/E3qOASDNnNfYIsmC3X+TC0p7J+1MqoWGKfiQH2VvyQnUMR60MpQhzI6QVb9VB 6O2oN5ZSiB2fJOH7DT7tIXirP4jAF+i/ONcUwZjesNh9QnpGejIy5SV7CR/dgeNxfmRtHpDvSrrE mYi8h7zOKg7b8PwPZN0aSE2n52Dq/kDiha+fKAPN8JSCyzPM9DAUjDttqX0zCAt6CaqQUHgOlrgD 9u3Se8fAG47Vly8JD/BaH0jidlhDNT8Ny82/y7YCidQ5vdwmDp3EioknLj0IRyzILiP+fC5WzHOH 5/GmWKo7L5HWgoiGe3GmWW8WJdV0TINtDXAAC2OZ8KQjr+b3L+3J3XDs2s2ekSVvBcedNyMBa/B9 /jbiAy1EVDyiC7dl9P7t0Hfp39gqzwNgFce+2wE0AEFPLtinusrC+isEbYoTEnkA+swNJjYdahy+ V6LbQ6krZh9+bemxnInraBmMJbV6tKodi9qjcZGpgXbAJMUd1J9wZ7aEUnMsQh7l1zPS21TIJWIh HS/zQ+9mXnzdboxr+Z0D4o0uFF7Ibr7n9Y5gvpaJ5Z4jHg+iGis4SwXEeQDgxA3qQ1reLD9Cg2Pv 3uzZZOoLOzJTlzPf6UKW3tANPpFHKpQR/CJs+ZmQbPg4QcUWJ+RYhuPN0Nn+9pUyyG8hNXb+XfW0 VzH2agwRhaUIRgpmChTkaMoPRKArUGL8gG2IJ4vbrAV7Y1pAjcAO+atIFzJTADeflewFwQy3Z/zX wKthYO8JnsBCqQZYvSNN4+m6eoN2L1fTSC8W5fdMyXIi5jRzB01AxURJ/DcHCMHQ/OJZn2jn7qS8 qdmqSaXi7m+rtSbbrPSsTrNKStbbN5FWHWxxwdkMpbOTseEVMlmOm6JSZlWEV4+U9ekOh23I8rPQ QUYBKeieMV/Yig7qscV3GkwuqAKJfHf8IQGYnyQZEjZyJRp3etKP7UNatzvJTXgUrNt4mMWlZ47/ Ei8fktVy66pQAYAXwGg5twouR/pdj1voabziF8fbZIhah+8N6rTUMZaMsHjTjRgctzG9drE+2gdo NkTqfsX2WjSnDDd5Ofh5eFGrXe1oT8Uk45Kvlkril9t/KYmGE6Bsj6iiWh3ma60oCGBz9sViDLAh tRRyAM8g7eo6U+pt2JGbI6SMtIxwfsO7OaezmD1So/sMiUJdfpjv/q6ZnmScsT1EGIVWL7B5SEWR sZW+Noqr7IQjyZkmZGvOv/VDUJx0JNPs/8WLHxap6rYpeOXQ6Q99GiY7DpJqPZc7GAWOFP8BoOAx RisXaLotD65I9YbZRkErNbk3/WYA+5zhMP4/MBrASnjDVKkQ4GHQR4XMNf87urEtIAJ8gr/r/RD/ SmN7KOVT9g/NS7jHanPSWCE6OyT1UrTRt1C4wjwWHG9Ze1j93BPnaku0njCYLezL3xP6ouS0fmkc 2Eqj8AypnfmAmsDB1egMmoJLONHRjPyvAHfmWmOVz3g6cRF09Nv4u01U72Mh0QWEgDAvsaJjUCWv 0EPYyGENYofdz8dCxfMhulD7yw8y858UWveUTdMXMGJBL0jWUdThEeYiX375xmzPHDNphrgoqXMY zoGbCE9UrteMDC/ZOjkCiXRkw0PYZ/un32xQIAFrrjpk5kljDbHiYBSNUuNkxf8eC9tqxTI7mg5x J6qVIDIDJEXMlLVqx1f0IgRFrSC6bNaW24+PmW1WEsEV1IHOwV5wsvdAn4r50OS3H0B1YrmHhXOL ZrcPRJjcuYLndh/UN9Yow2/B2F9YSrRumkEbNvmMC3jX/pipTpJOxZlH2jDMYG8FC07ShB97wFva qdlWj4UPbOZveuyzkKOGOgQ0V4RdjZ/dO1NG8p/MHrGOaEPfHoxo+nukcSHbIdJkBVuZjTnz0JOW DqpRJgP1GjQAlTC9HxwaxvoZ2LQhFZ0bNPnBsbIIQMCPCG8+rSigEXl52GYtfuOZ+Va+tsQ5sYue RyJVcMnM6uI6nhHOMBK8D47Z89Hr8dYKA+GP4LG+uwWgeCiMQrkuLY+Q8nNOCvjpViBkeF8mgjrB ttnojHdQgU83PWnQb39vBlunqkUQ72fUIwY8t2qPqbwaW7K3za3/oikIxrS9EEjTkhIWKATGSyvy OyZK3XQOoHa5Zj9hv9ev2y6AJHfZTm938mQD2uwAVmT4X7ZT5c+19h6WyVNiU3xdhBhIBbPiZiGi hEYZXmJNqC6EvRIsF7h55TWaQqJwIim18/tfDmqkUaL4vv6rDDloPxitUSZvNa+pYVUcVomIUru9 4acbSlPJGDoh6iRyRzpgE9ZYOezIMDqztBukylugjPiRkCdw+0/FZfFgiWEO8624X/Bif/+G847C MTMjq/ZXWGHTQsZJsClBToj5Q0Hfc0gTgC5VmLOCzgN4GsxdnAfvZRC+2zuyMZvpFfEDIyOxLfbk Pp9MU131NqyjAFq9kgZeupOs+41oO+qYQi6MK8UIBSWl5HCz0Vztg47mJ9EuRvz265ZErJrvS22S WfzaKUxPmYz9mqFs6ImKbAVTzX1p/7woBRNpQlPQt9yEf2hViKQEOnYQqMszL633NCFon29k+Cf9 4RN3zyf/ZuXZdTYpu9cc3nN+VV2doUmtfXIaHPabef8cRwc1A7c+tNn4FB+yXBaw2yJH0gl5eUM5 nFY9hrTu6OI/uEta/WphTFaPJ62ay3aXxZ+A+LJZdy+MaLMgIBBYckAo2UFrWx5SfeNMSKsjw9MJ J+ILrmbe7+RJUSFAwz9uZUz+TkW3deN23EkBm57dZhSKTJYLeUwG3zzBUaKKVTr2ve8nFxTYkYES KPaZvNPSlRJA00gwV6uAEdvnivCqxnK1SUzm8z7xrbxsc3ewwHgnyfNcmJFiiKDU56ZBLLPiv64G oHx2uNO5ozEtYOViQ6QI60ZQLBQCPeOdEExuARkcUneaVlKM1cbEnTNd2WGlY/wlNaBn5wt00Hem /G8gTCTODnYlMB1MOWbT2QCTpvjccYq/40rQW2NbXWh/aqQm+seAlMPqjVgWvR5Lg12mgVa6BLmH QyxNAGsnyEbve9Pj1m+22Gm0a4un+PeGCSuqnaszZYxLw6L99uMZizDmT/yRj2wgMm+qhMuEDPdO JGk/KnhsopAMAUV9qr+flSKv5YGRqbqGpallt+mikvOtV4G/2GWciDuKvPvxJrHd51BbpGkvcOgO m1FpLHK14FA8YrTA8G8rr116+xUiArxsnO3XA6qcCP2KLLC4lXUAIk/JCMI87ImWviUEWmWnAlXH 17SEwXx7iGGstmyYtR4/Noy0/Z8RtL1FvHIkU5RroKjTKnPUWBqkQ0W+OOeMSwim08DckXwFNDe/ PXzF+eZ7yXaBU0jDqxrxkClHzmyHIq7R/HDy2EjIcn7r3emIEB0+s4OHpbUf6h9g6gpL4sJXmp8I 1EYA5WF08scxipYFR75V63Ty1dV3rTWpZ/FiEyuo4+s9vGDDm36ySOX2YotM3S3EOyW88hIlYrCw FwYSRJFVIJboB4T+nIsTH+CQcfPkQc9j5LLdB/DbA1k85/QRGKeI4A0sEw9fdLxJ7GnjzwXpuGYJ jY4ioWBuOom24cvt5OgnFHW2E/yBdmtzNkuwBsmSc65mrpeZdAxAqKSf56V6ElWuntC7zXTUXOiH t+6gnXqyPowSkJozzHg3/rctQwskxKTcc3kflIVbImo2M4rXMhdrxwFRX+O94qfpeFfb5xCy4JIg TuPjVMuRMMXbao40oCYjHBazTA1V/IRE24l1LdPNmiNLGO8BOO4HpPXnbmlRnPWDWT30CwfeJEXZ 2wUgkkXl3PPuy/Olgoo45VPilY5SUzR4t+yimfSGgs+CkvOzOL5WJh/gTja2NdsYnSUr2pYhlMgW OpkxDruBllDR/jdjg5GiA0QvRGwmqo4Dv/zixc0+HmlMi+tax8fttle2KU3h6Uttx8SkVPHxvD2P AopdYx4iO1lcLseFXyOvcbuIPCgJjriIjHsd04h9UpKBZQUp87XBn3r0OXBM3cL7NQ5y0GYfFed5 TXHpAJfzm7htcsUyws1yDQ8pcaX0B3jzaJQckUnSf6Lza2pAwkL2MQU04VdBxbaK8mJQuybUsjCk dK9Q1AEMbginMGeS0H4UDAU0Twhdu/6+oISym3xXJHp3527jwFJMtvUSBdqaqEOn1gJLpcjkCLyU le+RtGKoWtLx8++YdNnPvvpMmOAvTofHM6/SxMLLRTxjkaw57QJoOCBYbdil9SpX707i2QGTi/5w TjS7FGRH7ie4XfLyWkMk0obiGpd4pw2/aY+ulcEK4D1bsAqh9IxPCsIwKB6Jc7y//bGcNRm87btM iA+W+e0S+2PzEUK4TwN76AH5MxiN8EibC9gyLIawZzVQAuzP8CRCINjI6+4C2ma/EOvJFmcGTNnA MZ/36uViDdhcEpUOCkbh/LD2li9s91kZRBMnuyRMeZTkiquq0tCfEbQtTmsEiZvMoxQz7NkXJdXU t/UTQsk2EVf8AuGm/AT5raReE+x15/xrt0Uh2Y0TG65Cg4BXsWGSZ8HYnP2jESmeOATmezHYtK4r y7HLN4mPnHdPPAWrEu8jWt8JyEnZ3Jo+gNS1eoWquyjZNMeW3feio9kDQMJBKS/vwGyOXVGQedNq FpW9jG1dlTzTAX/r1w3qBnGad69auh2CdXhBmGPgGe9AO8y0Uqvaj9YLeE0wxnmFXDRg1fF8Bljt 678Y2S3OzfPvqpKVksFimLU6x2UsxlfjmR8mjhBlt/nv1Vk9ecPsDjB6Kj26/UzkCIqKZM3pQ5fm bj0tmWBAjIfLMX953yDuAMeiLJmTIaiMmw5wzqSQDDgPOgUFISQUNA9Ftke3RqX7F1aND61SPVB/ RprZZ6Xy5pVQpdCS79GT1F1Ik3J13BtHDpQf6wVEN65OCLH2EOjM5crVlAE3bX/YYsYCjzezGXE+ ozcmrUBJs47BQC1OANw/uFkCfHYTEMvOTWmi7DJTnTesB8f9M102yiKTX9Ezb2suSj9TUeDzBHdU RQFn9RP/HiIvEkFTPmd8GPBwXCG5Zgk6lm1wn+my6W/PZHPcmGaQg+QsnOUALIS1DCr7KiKnBZO8 t2u1ZhE1oa2VmL1oQOfcfFCRzzUM3PDqZLaMHU1qtdTmH6wkECR4TafykQm5iBPZwYc3DdvPJxDO CKWhTy+yLoXKAvsTNybnJ3iLQJeLWNDZ3QvejeLj0jqCp74v+mqRMRFL+qpf5fnb58A/Boi4SYbi ak6viv6mX4/833X+mniA+XK0NIFkPKXXgvzXaKcgGnP3uqletzSan4wa9G0+HoYKi/9hxdfBpeUb NfbtF5Iwazi3LiLlYn2OGz7pJkYwGRb4W+FrOVXa/ITJmQ9YmxPuyMX7immjvhXF3FdS5xmyK0Kk OJ1rGn0FUOTftqQQodTZtVAPnWajWHI3U4i2i3sRTBkCBe0GLfTjEEROlSuWh0NQUOIEE0+FxLrB +R5R1joN2WWwG+vCtkRisodVaDXdH8oSyb8rLrsLHZAIlNNA+Wy01xqWh+mYb/yddwlNA5N7NDqe vDYwghqfsmWWfMguStskvHJpO0fl1caIssF0xbxw1J5JgF+cPSjqeNWa60MWu7giVawObTt5yJUB vEwWyUljJTaV9xIkbiMIobtp8fz5cj2KlViIZyBCuwGqOXoU1Qd9mgLNXA68cVCwEiN/HoBsrrLf bwPiJAXfEsafDLItZ6eCqakDU4M8ATJLMJ9cYqvQLHb58NNSgvi3neTmCW95+GiGuaCpUkFjCa0O gG1/rwYwyL4ttF8H1O00zx4mD1dIbJ4COq/GAZk+9Wrm7tWh+zh2ADfmHohWGrKPMVCBvP8RBxpd 24rU458wtMofmWLxVx7g/VP7X3Rww5Cffft2o0MnBPoUa5+sHDehWWGPgY8oCRKaf9Xz5pGhnDq7 wEOmSA+QAEuGjKsoBOFiu6FGjUSYw0cwDrakoVX1SmMyvt6+5exbgCOKaAKoKECy3JFbz/swIxUV LrAQgyPp0P2cZZ7SFD49vCNgHCFydIPA9iXnNgf4zwAbbPBBUhYXE1ZDpEEze6U2Wa+nhIF/0xtl u1OufW8BFFVAHEc2FZKcLtQO4saTFyGYfrCujlh5cYMPCmujAbo14nG+h1o0oHrYTVQPJDmGhrvu tQLiTrIfFsFFo9Q6Fafnmqd9Y9QQNBIiKmyjP00IxtOFevHFs3IS3tZlI3p4jZy/zWOWkRC/lf1+ p2ShE4XphqP16NhndcftB/twwn7HPZrr1zOGs29AroeGWKkXP4R1BDUtPA90DaVokJ+qVGxRyRtp 7ZNrj8AiRbresMfYjV8f/UKKiSsvLIJbxLSzNmTd48WmGytEHzML3d8N8tYpG2rS3JKyqSZi0Cuc RstQddlN07cP4oZCReD9VjJIVLXUHfT187MD9LWUfIE4DJK3AfqFGJmFXdFADMkcVcX9njI2NKLo l6t5Ad3KFQydREu/whYHdwytDnVf4SPWT8f54FY1F6+gZjwdTVyjRliLtkW/B+TMB0nIrBW8iET4 S91SMLzvYphamyDwjfEKrefQkR5+pB1lXpXgPhIYS53gJYsNqc6E+gpFdQBtYGlS46GQ3yMZHEre p81F7Oh2OyrP0kIffCJQHq3p4RA80BiWMnZ8uDW3m+N6z5u1Z3zZ9nJhzUwNKbm936AuEk+86H8r Jqv5sIrk3fJg0BSfDX04n+kZXzT1QCccXs6Q3V6of4uqPBk5vfaQXFbeUOo+VXdYsh01m6fDQ7mw NsgT9PO+0NUgmwle7GF4Z0qulL5/KfOE+hQQ5htzIiOAGYv7tjfDADhZrNiLggkERR3b+/XKcFNz easfEY/wJoobUcKsxDsahYW25dtOtpIYBuFsMtUrE0PzOJTaXdDCPYfbQmoagteU1rCURn5OTKuU HXtCmnkH6mX5Bw/8ZXILkZxLrJFaig8gahjofbTl6Qh1qF9WNLQYtVlzFwdC8ApydQDA1G12RHf0 t/9hde6jAyt6h4npBwy7IT/Z48Ef02VNCpl2JzPZqPX46g/jm81heq5F1mxQwcDuNRXAarpn0cxL IIn6FldPptX+IfQm/z5vvUj2gHCV2Uhfpk+abeJP0esB6ns31qaI4rvL/GiwuaCNBjSicgFId3dq zvIRqtYo+Ustl0A24qwkymIhmfAgnwW7kiUrB4PkeZWFG98gd+jMs2VNoWg8w1Iq7ja86BxY7000 P0/BOW/yvKU23qNnzIK1qJwJ9Hv/gAECqYULvmOzZq8XdaqevJAvVoYbFWWvqU4TtyRjUGPhMPYR Wo3pJrX3+BtRR0TOItT0oLJ6xeIrOf3MlaAO36gkkmXfn+qO9FzoZDdUrpoYqlcnUhENlEPuEM0B P3TuC3OJgwzycxLa4tiN+NK6abE4amNrxREo0rCpoPBwTEbyvdE/xbVt20XO7szo9dWQXXzG6yq5 B9iwC9f7eoEDm1uZfU4E7ssb9bwHDrJPoxenTG2NughdaV2NHzfcpiLnAkFnG2GxXjH2Wp6njAVT 5BWHWFk/RJa2z/OIIG4EQviwyihIhPAvfVzn/ugE7zNmES5SfgRAnJBleTXiBiT5/uIaYf8eP/Re UYe2UQcgrd2HMXC8Pe8k+3fL3Jh/LacJY/aVs733L31O+h+rSw2EYZ5UY2PNuWnZjDu6c3VPHppA 2HhiBX4FuRtMJAqqcZfMIRlTNuD8oK8CSS6t9m7B4lPxKu7FMNCBRrzY6px3bguveCxzQAiDG74Z NKSQ+sTxzT+pPwGOjBw+uDVs6pCJAZDSue0LNqIpWNWGY+hoi0ZPptcqLyxXLe+axRXm+uWYJOSB KXtRpUQ/1qb/PeyDiqfwbrFfhIDAIbrMpDrdH/T5ozLpt55qVRw8RmybdGUPH08T4KbU1zqTfswu cm8aGM84XVO1f2PeCWHbX6Azvy1hEwNgaOWPmsrrdiOYZ1HnvkPSiWKHLsbPO1A0FAyjWVZoss3C 7t+834garca+mTsK2S9ER6ObL5aIbb2ksS4H/wLSy0SQenK9jNIc9run8HHohuhjCOIehnvQ+3QV fmKR55LKrrxaWBJdpZLLYhFbxla+t+Ojl6po6fQD+t98FBeIWwkj+sOpCZyTrFb/fL+DJ2y8DV17 VXOIXnt49UtclW0/EU4A0YvXQIZoYFxzPXcuadvw9yyWpNq1qTbvhilU7h8ar5a1JQO49IrGw9rD a11dmxpJ1nOB6pbrkfi+CwJy1n6DrAka/r6OYhvKSnLtZbL8p0kmutIHJ4/e2pk5LoZhmqK73DJA 4KErxzRF+2PBsWkV6QuGubaZ84URic3QX5g0gEopdRfybL/R2WH9JKIFQPK4qKtBCqkP1XDiB7Se cS/yXR6U05vO3lWfIjZD3H/fgbfxoRhLfbNrVzmncBDyZpQm4w/VIhrhdFPDSEb2vuv4H18yosok 5b1H3n+2i/GF3OmmJvmnoX9ebATsgw78wLkzqyTyOkGjDOB+zhPKLB3ppqPdUs5I9un6813yusZR EE3IjM97Z8/wchofdYaYNF1ZBtTBx7gqKTbs3Hgr6L6ZHPYjcoq18U+O1hWbL6LU2RsEd+auCjLu 0uLyAG7i7KyCaKdlhXxAH+RNmIwonRO5uha7hJZScxHtYR9Eu45OzlVj/Nezu2Vo5/xD8o9gHKwn nCIMewnIzV42gLi0U54r278HD5LgldkJsewB1BxDMcGBJYESbsEZAbkVGvJLrfGN8iQRcdjIRQ3/ tJpXObvdiGjXVO5CCtRs1cTx8QvSenHy+kcIjzrNFO1Z1Ith9VnBxr6boJ48vzRlhhJZfLF4Z/T4 5B3seg4p/X+lvasUcYGcWqBk4md7xCtumT4Zd4MqZQ5kYcNIefJwIQ9bTbwiDOVfPwZHvVSRGEpM Joi8luIQABB1egA6nJWya0o6fByf6bLVaTi49U8aSdZ/+yhLXiA52l7rsPVu6cPzj+p+tFm1SdvU mGPa47kRgjEsnGoMYYT0xCXnXG/ofrkAQwVG3t6pr/MgDQ1Hrx7FHfOdeP373RpbT9pDcXz07Xlj q+Neuexr+l3kWQKSfTTHLNSWtfw6pIVJxDd8sxabeDUbBe3geCJxCI6xu/DYtdN8OAzy6ib75E2r NOvBrpa8yq3S4h2qK5TICMmvRETzf9oE59pP4e6cyKYC618t7acJHfCH4VKuJS4mtMXbddToqolh WetPxwuYm4MTyE6CNee1S6ZwDa3CUoW/IFcp9hxZWM3ZR68u+UglpYnozpIOS+6B4z6aUuvbTKaJ QrWV8DMKf42zn+p5bXvjVzjHVcAcITflGKgX37m1hlGGZ9VO1cqv4nXzGucNSk2v1yVZh/QHxVCu tUqs3CIPrj5Y0RKgOqGYjadkzTLvYzcboUt4DnWiC/G7IU6bo93xZlJLFay9JV3hOopWA2xV3eph pxj66Y++hXrZabgRh9O47CKP55X8Y90dncDaYZMliWCU60vO6mTXa4hGkeVkfGWy2EDU2ngwTZ/A /AX9guFdV30k6X97HXOkUpawIY4txk9NhzCZ1HJ3/IsgdjIoW9KPm/TFcfdINm325fgJ2olJiyqh Ba9vGdhUZlmtutJ3ESEf7BbKVhZ1ZhrpfbQp2DZywGdC2fxgSuZUybGpKvjp2B7kRS2JtVMLqkIb MDyQ498tWRwqpTcJ+YfwVppCtg2Jn+7pe/EhjOZO/Of/Ma4snDZMNZSoU1OLHja1HYWQsNWYJ9// ni7GCDTBnjJjwJNDelFU+tTOjzpH+ZZvAoRaBX6jPm9sqHtQuHUXB0j5xWQ2ltbOK8mStDdHVsas gvoDzIDs6f3N8UW+ivLK1zdHVMb68XXWs9cY3Dxrxjl/v962+RoUo5Rsoy9ZbXnafdy2icVokP7r 3QAl+4NA5pKSbF/5UvV0jrMVRm7cJTYDnSyYhzU7VkaX3vyusxR8uDBCzKezU9pgAneyTudashu2 J5KwaygTGCtmn1BUelPjivOaKo4ATtaipNPYaR5kb8g/MCYxCr+kKOO4XCBLsh6sQKx8iBHCL57E oGSiRzOh9Juy+J1IlVKghYm/6TMgpEdJBhoUJSyfDEfy+yjpfXn8Apuqvxq6Q1co1yA0u0otYBTc DOtmLkv1BIPyo+3wqFdbRc5CiXtz0BNDaSlaPCbUFk9IkumL4mcqBd+WW0ZkJ/lNbpjBLlrofUYJ t6YRGN96G4ZdaieO75ik2SE+c3X5+RMLhJdEBx1IwjJ84Nari0sSB5JI9ZRUVFSlkjvNhyvv9WOA +4xUhtZogUozzRL1Trbk+vLEqO9IZn/dihpH9sMM+oq4hraB26jTe6FyV1v2LVWylh3GoC51Kx2E b5Txg+bEk+WQrALrywT60lEBhnj1tdOmVvlCCdrgw8g7MLZiJ91a6FJ5WbIRujuY6QnDzh802rzO 9XF58osX1Q6SuXIES9YzwhiAmMY585IRL2j63ysXsLcfIGtxWhbpgKJ/MXFUbXm8TffVkWVU2BU+ g3WEoCd4YV3Ui6UwyuQCgGLOTabHmnQSDB4CGqjzmh0mW9kn6UpY8fdhCroI+5qMi+ephw4gsmFF ZxyIMvz0qIUeuld8mRNmcQ+Pt/LiOVb5UO95Ih0N7GNa7+7JwAxkwx8nFlC7p4679pwAyV/n8uB5 wU19SzbSqC5dWU9u/d2gxlvERAI4IKvPCeMXScYE8y9LwDHZkzJ9+aOReC14PIAhdEZICKC3yJ9n 6qZC+zWGzDQg7gZozRNrFzKJxhij9MVi6F+ZxTE40pbdsmPE4X1M2k0yAq9tr4FghgIrv9KHfLv+ t3gfxnYyMVlDr7XE7lmywcrb5LamL9CeP6ZpfOA9NMSLWwzgE/7SmLdZ64D9KjmoI7iOsIKA4aGE QwHQjPlKJFQhdiNMl3SRvsIUeetpDOOGAqBRi6f6t6Ka8SQuOHDgql+4kmqApBRfHHxhUIw27Ezs 9yMKcEUAl7oFCCthdDXwnMkQnAIlyYCCbC7LXQW+aCkoWqVoPYKlT9oLK55zFdVLdFKk+dXJ5gjy dum4YTGmSLSeQxw98E/66A5QOrL+p+Lwu2+CAaXPW8v2ZuqQattHyRJM3JXSzqBnv34b23lhQ7MO cA8PyH5Fb5gaqiOTaLYupBDg0NezV4XXLw+QEMQIo4XNj2pE7QOCBOVSFB+gDTszdyerFMAjscOV yXVVmKXCrurXGWyH6YH0pWyp9QJAc4F6Sq4JYVWWTJH7j/XwbapDKHR44fhVHc6S2Dlvj0y5Rub7 oBtVWOLMsuycMtl0EdchUswzkl2qdHZVVMWYYJZ8NnTt3qltM0o1VQUJUUL5zsIr3NVHWNL+8uWX hnMvI1+MKeNKduTgabxvIJf159EP+6ep+NlKKVec/k1PkuYv8WQaCqAJCBnUdsagfNhT8VePGSqY Tzv5raoFwLMHAxjFodAcvjtGtVL/qZpF8UQFBogkfejPQXI5TQgh9O1MMtSlHcQ8z1wJ4bYV4AxQ VV2D5dVAYgrfgaeLzbNNFJjMVDU/y1Tdx7nelGc9AgppuOlGqnfldgn2c2NIxrc8OXTuwXpg7dlf hr2grNFd46p4nVFfTp0fVUbvspSQL8j1SZL9PyLI4gLBC+YdPKIZ1f33oSUNfVuWSTKv1dsPqyMB ju488Q6wuXN5EqK93X3rzbjYIhI5Cf2fraRu+iFQpGjeJWQm8E8dj128Bf9N5PBMcbvl8oKxmFzL 9IbqxipqukLm1nQjv3eR+jLVYt/2eUoswhzQo3D49oZ3KLlq89Ccu0DPqGdn97lkyxo/Suc3uNN4 aOBqItKHzx2UuB0uEMRkZ2WSLb5Iu4814sfQkU8YKsYj9KTh+3yHWLMhIudcnRPnICMrO25pFSJA 1chvm1sqRsdDlXMgOQEmm0bpx9eTtF3cY3iLLa6ohHOqQNg9kvlx1QGtfUoQZ6x6NRuOb9UtjI/o gGwAPvrfFWkK98Wngs+UbQNGqbRZJgwJfXTGyRLB/3fuCOXQGuzVABcZXP8qJ2X7ymfDDJSaqFyw N3rA9qpLolJAQO09G975q2P3GLpP9KANPaeWt9T2beb0Dw1p7iaqNyEFOgmM2Jwcv2uUx52CejkY uR3mM/ev2e5/szKZffYJrKcBrpwSdhF3eesWKOzRImg+b/lm0OTbmErUD+dY7KHfuQ/CKr1K58f5 agXp0F+hsg1u9uEHkvAm9Y7oRJsgvMs3iJMUj6eMhiwrMUWohrnTpiRHfjgKTWOjBYcNvL9uoOfI fBALVwwjUkjDh36kM3msaroyogC1wd9Yubtv98zSo0CJQrzldHji7wTmFsDGdGbz24RlgswxYStz /eJGbizXuyH6h/lkRsyVKDiIwpDL2bAd343b3UEN8wukQanzf35qVM2/d4nrNva5cfpesSaSrzVC rS8a2MbKiH8MH2YqTKjN3T4OZJnOHzHypOTKCqE5DhArsD8cocZQz0d9ndrIuDyqpwPyO9hzEvJl 8qg69z8NIJSEWBQLDreIenUZNmHj+dsjOQsszzsFYYOYXM48BHmrJtRmFWo0uYrfJrx7VuTHXJT4 SQaKdMy4cJlaVoMkFpQx2uTvg4bafhzcjRstEBSU+GUzYe/vwzOGKbj5V2RfctJu2LK4aEW3x/a/ kI9vtW5KBLhTfxQnTB4AK+qw6iBpGKIIH4199VO6qvHBNl3Cd4eql/N4QTvO8SDc294TZorit+RJ UaE9Q0q57YavTl8diRCyF7+D1MiAdrpZt8oZYktYxe//s/LnQPky7RoKurecW+x5L/nacswpvKF+ hymmpH3R8KzISUALKoJZWzQChvG3BxIrohsNwwvRj0zhSa8f/fEjXgVkPV30eqpAmJD9Od6R2UMm 4PtOl9tIGrgJHD5oUerr7jw8mFmDPlcR1/0bTQG2vNM45xcCwIYXOObXa2hYY0lyouSmqFnujjRY 2HCVQLfRY1C/sOTps3Tf3u31CUN9fwEIeTBHt+JwSRhHFKyDXlmSVWyBSmiD3NzCR2kkxR+LtsX8 f2ANFjqrw7W1BFf5PLZZH+6a5cjro1ZHZ97HC6pfbAXJYNnipHoZbXhEt270Yn0NQ0NA+kU5dp6K Jp0bUnAS0+gBsYq/6r4XLLCFjkxBFfnQFbETJUo4N+/SnRg/4K4CG2lia7D4G/3jYlNgbT6Nld1j elFlfIlxJJXQ1f+kBbWMI6HHNrXhnJYrDkTZ0Az3gd5rXzS55wGz3c1dqoP0rS6DPLMt++cXoPd/ VI944Odn+ZmvrsTsFhYmeYR8yrdtpoEXKHN/Uy+y9bzRoivSj78HhCkpsgN3568lHXzCjkewPP55 FzqUUtjGCYLfQpNM/18S93Kcm8FdZ8yFGqEdL3Wav2ydoyTFY0ITE+ngPPTHLXA8f8ZZc8D60LMw w8iQczIKffJx3Jz9siFJUra55c8sNdSESHAUlsAKD0dP4WiCTO/GWy3b4u54cvg0My72VNfN5DP4 8UQFMB/coExZr/9rSjPTOKvgZU5UswxTO8ZcZ1eBgRtRqr66lvXzy0aEeLo2q4+IKSDWRCxsRxQe jvwy2K4D57/10Frh9CkCWJw0Lz6FBIue1OWIHHUBeWg9B1eVa39bRq/CdmkjUXwms1ysxKc4pux1 1g/zRhzRjxJm8pqVBdT03HuZncmGbjVNwk5GacelJzr6JO4mi86H9tqITXEKSF934MwP+uLBXNRY I8TvDORxNqYywJ+fHdaQ7gA4Yrv2ZB5Zm+Mk7ErXbIA7OXRfgZ1nM+4SvgI6hZMOVIAITgIYJgGE PzDTz0a1hQ0BosBQhWcvXQNUUOFvAfSN3VYmFQmSQIXUtiVj2JDk8Mq5PgVdR/m7lff28PtknZ8E zdTZH6Sj+Acz+xWnltivh/Lr4GmYo6bgOL4Sr7UN2zWnlMIDguWOfdys2T47TLNSYUHFd5rWON9c VKWTC+xZkB/ikNlZkW4d4pA7Us6QkIg//NsMoHkJhCR5uyg2JwhoeUaXJGYQCT7IXPflxzOGZ34P wXOpoLZWZfweXZ8Sm0I/l5ru7jCUwPUK/NZm+g3OnZykzdGUNx9CNNnlaCTgdV0aOxv9z48TJCHC dH5pQ6UJV7ACBwsxHgjgzmgximBqae/4ug0YzcSkoemrCUqpspfYD6bXqNk8znoBQHI+JBPNZ3AU xeCL0FTCvzqv7SnDn4xHdaMPZpm8ztWGYE0S9jpqjtzmvq26P39Kl0JKMSKZLo1srawqI2QupzqO p8SpKKFSSaI43wXEbuUKJVqsZ8EFXMB3jM5h4EOOnz4/tY/k5VqHor9cOE1X/hKJ1+UIpekEWDOA uwFvS3VeVulEj4K3+0t3qnfftA94Ad8zhX6nXS6tv7tnLdyQDBq6zn2qq8pkcmzWdCSH8J+tbzbe 8/JzFknMsSz+lNlwGMm+u+oEGcf51kugVDzVzUfcDF0Ykjt9VrjrLz671iRzggIY9PDZ9guoo5NK mQNOsFU/Alua1PymununjJFUafe1UA9E3fKH9xLBFwY0QWZtoaynSwgTBcJ+FPybESiIv9C+7yRc jQt38aggO4jLqAzLZ9qlv4RJKbuxFk9lXKOeu+O2OAtSZxomGl/GjZ2XHdDEyWgkzNf+VbKxceb9 FK2cNnrUj1MM31EFwjyl8NlIA1/iFzYn0NMuSmZhehDFqIOk+aYXMAAIYMc8C/2FtXFK5rtm7K+r NqvNjLHhxCTY+v6WGMAN53/l84eUrraAva2Q1lqx9B0K4N0N3k8Q3+eO0pN1QzR/cDbigJvWAO5W 1ZLujPFgQ6c9OYG4ev3KIgYyG9voLu+6z+CZl9GmcGj0gPjRFiQGl5PXIhfMmOQvgivd0xJMS9qh V4Izs+k4wRyoN9zF5oPPk1uyk4jruA1X+OScwumpPkBH0Qp/aQ3ZWYlHMfviCerDYUNFO8+ieEcA czTsyDD3qkpW0EDY2CUPuCBUY98JZeNw8vZmx6xM8YVv9JcOtOor35Iaqk5oxvNMwx+daKSNQxQV 9l7KPj4mqPIAijljRyPew+AP0zImrIfGCcjCDrdxD/EJAgB+uhnGX6/f+/EhuzfnQlkIcyM7NsqV jUhNwXXfhmHlS/aRciujN0xUz/izyIEqjrFXgERl7XcYIdLw+M7d41rsucyq/D2EM6/a79Efw3de pdxuZ4kvuWpuBW2JhRm1G9EPiAE3dR1pJA1XIBayl2dJYPGsZyaGvEUBiFVUn2YHSceiu/vdrsvb G3g7qA1CeYxGpngSYhpi/6DDn9bmSUBu8eChD/Rj6zqEibobA5fpyxtfcAc53b22N0MQesyEOAzY MzX7+s384H7Do6wYO546c1HXC0AuZmHKtv9BOwkeN53G4Cqh9veypw1+4cPYzAxcdXt3MQRToEu2 XH8UV2mFw9qnKNRsnpAMuUzUsojZ/P1H2Ct15VyVLVsS6jG91vXASlZN8CSKl0Yept1mAf8/KqfB WHn2PvuGL2IK6h3+2qOc85FQt9XYhrKJB7cizSEBD+nIWEPwNikRBiKwWQqMtfx2d3J4QNJZg/7x 5oCWJ26kIAIDKBLbfWv9Wv4o6lkdUje1sEm2lv3q0zDnlOfaHXDx1y6MyBdpM8HGbFdnonP4OnZ9 /SSvAZuIXB1ti7Hg9dZO7JqoUY9lZQV1iJkpqMMLcHAru0s3+2zvOauB6ox4EeM2OW+a3UV7bahi RQAand3lNURB76L6Ufvk4zMePLdyvqHnDPDvI41GL3GU6+ggHoRYYxlMyEKDpHxS1lSTMhIQuZFb BT57c+1fUvu0+0guAHJii9l3ZE8nDXXeI/9MO+2l5J9uT23JTJbxLkANcyac3NsYjgyRZuNK5clm pB/x4hMgwnN7vn2HsH7QJmtK93rNdyKo42VT4nISK4EWLL/raury5V/e/mU0yCaPcJGhMMqq2zsT G5YRvmJV4EsKR2HUbGhzITk/ltNNMG4ABOT6UMbgEWPbSJ8MLPQmDZ0Yp+v2Wt3x3hoiEtn2EcCy 9ZnLTWb/1QjY5BGeV2alqnLoG7gtIJj75w/9hUxt+nx8lvHCDHYIE+C7K/gqj6jFwBlGrGE54uDZ tVnGGSNVYbMhq1qg1vhNLFqvIGm/XUoWWdinPZqFICaEKHwYmkaPFj2fMU0OAT18aKSW3d+VbegJ /WQeN+HsctH2AYcF7Vrk4Fq/rS5wrD4JmySD2oxMS0IQaNEbwCsEseqJ7VlAu0E3ZG3XXmAk806N RXd2jD/7mSe43C914/+CFab1Gbp+Lc9LT/jcVP31RL9KAhaF9L6+O+DHRrlCvn+o4rKBBKFEynTS L2wPYciOsfNnPmXG1unVL4c7FYnxTUsC0dWcdihsF4Fnp4w+QnnejSCTXUW4ztSpwn1nTmIG9WFG Jd1F+ae44/7ZkR8BLEW2cYMYXBmsimhb9u3jnFINICZR7MWP23vuq4LW/E/XRl8DcL4ERjN2RYly WXsdm47VzkoaeWXqbVyLZXBzm8TdxRWT2e602ezTa1ipZcoMpC7bNOdwSAPTKtsZL7Q7UD4p3qN0 dsCv7ack1rtOsnaT81gaeh5jGF/lk+hZaN5bO7yZA2lEaa3ylPkXrizagedbxuji4A4TWyXBXLwe vlv2abZBSlPLHysdAvWki4yL1peLKw6dQg/soqTAacmZDAoCliBnJDi9Pm5Wkxz6jZ2X9zdvocsq vBrm6rnMNGwjMA0nk7C9bQj79FTJ6paOzm+rSPhP8zeWFNVI99TtbtvKEleEPW6u8PftYFVZyNe8 Z8/YVvpflMClMxIi9TmpNkPsm4D64QATpcLzj4tLGpM1c3tQ3L1hEaBBNjxwZ5PpEgTv0ymD5PIV kpNp8W0CaUfwYzlKlv8+bOvK54RVs+/a6KF9NrDpmckaEHFg1OwUVlYmFjCg6AnEu6F8wNKwM4++ 7tFk8potKmGD0ATe7N7qQnaVZPZgLQM86V32Zdk25F9MywTL+iE/+qaCTNPVZMPeD3bOUSOGIpTg gxReFfGLKjHSKxZLQxoAblAt4zjG74qFW93TD+8YFp6YfIITygaV+HbdraBARGjgU/gCbmo8WGeV ztBorXrTQa0NILG9cM+9oUXZiVar8/ulpAz1K5e/fNGArDax91AfpLsAKx8CHl/jo25ntqtZu7A8 8nvaOUC+TOWjlNjbB/wO8Gx+3hd+v4PpTvU5XizWG3tedJHpgT++PYM2x0TQsqHPc+LYQeZBef0H fGZl3LgeYclW2Um6iueOuq8SQageYAINCUEBwNfco9Cd8qidME1QLQdAmcfLoGfioQjf2DgSCvsI v6a4ZPlVCk+PtrvEXrhttiItdIYtsw9cu1aBS479yRvcAIUd5ZsTrhYwQ+5fG0XhON6BRL/Kh9PT Fl3qbejhwthQ8s/pfbUDYB3lDIs/cP+bZpXgdaM3pHY2gN5oLkDzqq0tVdcTWT7rKpt5AkoaWJD6 QF259nmobM8u4dm3/Sx2ZfPdUeZIaDs0J0xl8//QEJY9IMyPIERsYDLy0bZGm4xAI7+/Zp40w2Hq RllK2mFghfCo7s7xHqW/t5ZaxC38ZhLeKZCdsqjCo0rRduGz4nZXkzMP2ybUuriYjTDnN0gdT/v2 81+gRYpNZliRPjbymxew53zjaKurxSm4xBEu3AIwmGWplyK93+7RsZJQ33D8jPu5ib6KniWZaCRB Jw5GIMCrojHNdvqI0ybIG2XCvgkV8ZoW9qndXdIrwo//fCHimEtzlMVc0b/JfT+rrl7nDa0+WZMH Ym7KPKZHgXsfhk3b68yEBq1nntT9S12MWISmiGVriabL8Sig8H9+qEA1EectpoP+NJxuM0PbgfXW v3QFA9E3qjsJVF/spM5g0jp1CqUqTNqejH0BxhioMcEat6xwDHxK0kxIRY0w2wSXBP4l1TYhYkal o/bZJp652a9yKRJMHFkBxFlr59JUshnGGRcq5pBBD4kKm9OtocOpYcWjAgvctoewcv9Ea4O71Elk KZuuIFK4z3fpfTfv3eMODE8KHXX3yFGtrJo7Owm4WH5yzEVDN3399NaA81s+EJo+9rzLc61tMx19 9yflDyUeBKqc1JRSXLa/NzDTBQMGLliG5kb5p8v6BtWNOcXEDW0GZMStnhyXcGK22CYcz8adFAdk fAxDwyTy7TXLq4eLlE+yQVfSDjTg48MgY1X6eDgUwzhB5b3wWKaxY0ggJWqcN6tDkpIsTSWpoGnC DGosbVFpKd9udw/8KI0udxZflHtfXwa+s7KtNRPfJf1xIXRa4V7S0Z2MHAllBVfbIUV9UFtQ7SiC hYFotn3I9Lv9CvHKlaGYWIrWHnqt+cQvkBeGtMd4+dehbK4z64h7/fQW/Z7q1HgBsTt4rmBaoQz7 yn+vTl1LVWL6oOvCQLYVNtS/mgFVAd5dZmEDpbhohoZtBemxDxrATMszEE1Af/gDwuPSoa6SJLqc 6e1byD/WhjbDdywCffFCyY7+iwr+kgBPMF9vsBP7s8rj7kC5s+dRIfQGBPSS29OKg+vpDy/9Om7G 5JOm4AifT9Dtsc/V4YXZRFwEdDsxtdz5J80eO+GeANEyuO9cGJupHi2u3rKIOgfKC3UjLkn4sDBR YzC7XLT4KnF9lxOojLDDL9VLCALlx/vwas39RKh8190OZyuufmV7MCl9nAlzHZtd+0dH93JALoys 48up/udfJk24NiDULNqlwv6UEf88FFly0FOiOJylyspQb1STKFyi55J+2hfIOvQExyYFWqHpXbwz qK2AwmaSxuJR3UO/RtHQLdRPj3mmzV/aFwF6VXqxK14WUQ+HPEb5kJ/uDHVhozQYBHm1qM3qtWso 3mD5pOLN5lhxd1GcdEEtaDHQBiGjUHki4FwG3TpZvRYrD9A2VtLUhtf8zhuW3U3u3t+BA8x2l7Qd gtOTuqKQ7MQes+phgK+lVJf4IfTmbHjfHzpxA3LWSJ2ENX+Gm7+IVmL7+6SOtELhsvUSK+zErIUM jTu6XSFEpVAZDyviqbm2BdWLkKhfoj15UptSEFZFmlOwRVermxWnbrrnqo6C+hOgZfX109j3O5k8 3ppLJ/0/UcSvJ458z3BHc3w7rNNCazBqR20eAtb18Dg/hj15nmdv7sIWRI4Y6ryIFmlfi9A5MLS/ S6sVq6IY/D8z6m6Aq88ohuRTBgwYIldhZoM2KatrJ9QxMuo81x4+oRZ3A1YeQOrvw6YxScPlEzdq nTgrfebgKaKhLrUA3tzxdwmyh00VxhgCWa55svwqmzb2RlW2Cvkj/Eb2FF6hUdizdkyEvccMlhnC VrV/nAcN670gAosxlfF8tYE/ZBhSWFoaCSQLEPs5gsE4wIvCJbs/IY6GrJO5pc72ONMsl+TXw2zq rtt9WjPytEPdxe75DWqgGaD/WsDnmtd3hVaFK0OF/+39DRuYFtYgl8P4E3lQ6zXM15HSNiEgbmVf +OkQTawUwCt33zhAHTpBpw0olvtyrmnwoZnbWH2sxEPYllH5TbV7R1/lW9FYmzrkLhYeWTkH7vZo xKAoU/PhAggW+l672k+AGLz/BVqi7FwdDKVsfdUSeuNkc8F14tPm3qAZgxTKvEnFali+dNYGlS/X uu63rPKROcIdMsmLg8VJ/aTs6NbOmmJgvKICVBGkRNyqPPA58RacXTbAP+Y3mYg5RJUKujzyWt9O mqYjXTrt2xGO7ZS51SurcclwLsuOgbfGH+tXfwDF51IGSMeOF10bLVzXGqsQqWU4t4ox6neDNYNS 0k+4feB8/rGpIIq4UMEhb3vdSHCQfMrDSElaz3fPwKs6NYsD6n6KIkRSYu6lZl6yWXYgdXbWX8dR lAZ4JtGj0hvnT5075w10MMMZIn9lJPZeRUdLbFLP+duw+pgbdlHjVcaa4lqLK24Vce7OdB+YYis6 b0rTT7cLYo7vLl8J68t1YKdvJz3bH6F+zO6k/aGEphg4FK0rIN9sU6ydkqY9jMuxFNpCbllzY9Vl sgQnxpgx9puESWAzhlgiFGY/TKE9uR+RRILlCtugl3EAnW8vb0T9Smjy8KQaLEV+87E/+c7zP+Vz 64y2K8tdBFa2Mi8j0T3UI6RLb/pobm8cYIprzJjjCVdlp+hm7mbVL07zqlkeGYDJ+quee7R8p3xF wHX4nD1tJSu6N1MfUZiY59cUPDK97plOmD0bGh17rP+g9gdMtFV1mjs0erR+qG3Vw/sLfAnWE+As IerFpsCovaSCT9LzHy4TnPFlUkyV62yOkw51RjTGUPUMfk7S04Zg3qXKv/wWwMlOqGgszV6EXmH+ xU2pgo1kzN6KuzvkhmikMw3lcAoSILMo2PORSlT0W2L6noD3n11A/eUK0BjB/p4OS00vSLcmG4l8 PoZG6dDr6E5XfVf2qJswV7PY+kP3dWlpFCcsS9KOhDYA9S3/imwJMYXJb2TDYt/S/Gu3/kgONYOP jhoDApZsILl8Hpyw7nw4jAK2qYGs7zJuu7q7LCnzufjaKCE6XSMRE5rhW7aqXqL27ystoPe/hqSS vryMtaKgumqrcp7V0YRY4luk3CECL6yCm6xE6+JZ3HXC/m9Af+L7/WoDpd9n5FUyo1BuxAb0a0Cw WpnDx5+PHuK1jSE2MvtRBuW4hLP3RKWmaZ2p9soEeSED3ePHPLbimg1ZsPNnNxYeeSCZ3410/dsK wVadePbu3jAyISKm7SPX4DjC9cg9lUVB5R6udN7B/l8C/r7GUyUiPdaqSU7jxldXvUyXn958rxEG b+BTDz/5NfZs1N2NPVI9XSoqWJ9P+u72UdTSVb9IxE9rfa5jVpIFC4UnBhPE4m8X/x2Bl5vzvd5b xLLgZAovX7dhN9vr7p7oEhyMDv1JjoDuKbDC4jDdFf88CtY2tOWNyrSKnS5mdhzvG6TORjmLTC9s MjUKtBnAhg6619Ay9MSIiLnBiurfpOUSVFKmVtUIRVLNvEuu+3NQpC6YI09rRhks6ty3iwvP9ygx 7AuBTa31DHZgCcT4MY1n2RaJv65UkmxzIROOM/W0HlizfNbZv5XHMs4g7cMUZH3i92mZNA+A7XLX a0O96gW+WlnhkeTXXyHlo2dPU0E98W8tuyzoLq3zG3sn4u1Og+w5hbHZ0ve3CeiMjiHIZ/0rjUbL kkrF8bsyLLbIjPIJkKdTlq9twPFU76QoXODYFDK1xXx3un0sdlFZw4ccf86ONLhpGTHAPrm/ghO+ gEIZq3w04LkcOHkFaRwcVRO/Duc0cFfGVfORLCtrsP/VCEcNK+eHCf/jFTW0Ep88VaVS1+B60N8o MgerAc08hDsmqLEbvRPIVNhQwYeW93TxMME2uKVV5p1UbVVmzjsNDge4dx6IWeTKtaaZIv8uSKay wrfJ1kY6FM+VEH5x9YpPsC0tZtvUflGBC3+u8a1Qz84PUo9a05oBSU1vsN4Z6edA9M3f+w7nk25g zSklwzzj+3YCTwwZ9cneBiwrE63kSBEbRvX+PCmRt/0tLGvgAsdmb9xQDleF1OIVqFiU/PO95bYw 1QM7P9DWd6+Wsj43wS0vjayZqGawkf4anwo1mDNEVMjPWrQB0gBPa8Xj67WdmaqS/dl6l6dzVn3t 877e5tz+gsr+BSkQxgbGU7/oLyT9tPnV7guBQ8XVwgJsVZkBtHD56V3lsibq2Tk5kLDRz9dcdvc6 Xe3NJLjhdUlNAau31nNWfN8L6Go5Z9A6iXurI3BqXGmSH1DlGIKHn5szdCxvST3p5fJ4tYxavQJl 0WosI2cEHu+HN1c7/hF9YOeInjabSmJwUyWxPRQQ93rW18+C681APCKf28wPzn6DtPgifEdoyhfA 8zWRp7x/L5dF1wQIqfhanQbpKQIrAzOdB1Dik1+1BAE4PTcaxgwZyqUUijahaaILauinLfp8Aw6g /BKK0FtwvDr+YpsbttWJHBWJP/IPMoDU3o0Eey17w4oKpXnSMmCVYT52du0QTHba5OOPdXL2YMhT XX2l4ntxkSgxxEdmy0tJUxqFYrjha/6g+2T09wl+JFzxlQIspMrJT4ijSWnjk8horJppk6TUxoVv zjv2gBihkMgmNkARxL4XNmzLo+myrFSX/VwiYR95Nv8d2DuIL4miKGguvGlm8CLhamG7mLRLIETy ozUUFAEJ4VaQM2uihgvaqpYV30nx7c3tq9sVUW7AiD+/2sySdysPM5/kUCTT5Umu5CIqW0nrnBnj BvaFyJemUw9snnSSZdBVzCZZxbvSTFsn+6tigqvpYCouCtgXpCTGC/q72HKAFuZ0AeWchRPXgI+y ZNFagFPV4nKtOr4qFHF7BvqgcNfW5y6eFnjPywl28sPimp0uh3tZLLToxesD9zGMHuTC5XvO7Ih+ ZN0ZtjGveb+zJ9YxjNA2WH2k9QdrNriC4NkW0pT7W/hy2mYL7crMlUCijiz+utR4FXMTsefLM/2r GgBVwucFgTPhZHB+BCvFGEpBmdUR4qoRWhphN5WKh+A7Z3LSLsVxWd1xYUct3tVh0ltiRje6YgbC 1IzGJlQecnxqZZzJ+bDKGgXL9XLeuFwmHPYbCH8C+Gm8evhANWXqYBNmmqlzLnNgew1+QuJL8WT1 o8PJJSKnAmK0VX5rRcrDRbTB4+FD8zTxA+/jAt3eZ3j1Mmr1ZGDgadlPYRLOYcIEPN2ufMnGwA7I mrF5IjLDXIv0fBVgjuAUkLkh4YlqUOte45lMcNsIOr55G+IEdtMT6IiGIEMeJFRXQrawojZ5k4Cj PAemFbyYfZzJsg+SrIhxZYRdJ6tij/4BpgRr6twK+zJ1YtmRraQCnLfNQQI1n9rRFQkowwLXYMv/ YZYdDfwbsERaAkwYX9Zn93g6o0QAYrTx1Ir4gld2C7CSYdxn+UcOHGt3jaZhWaEJbukIQ7IbFBaT uOC+Ojtfs8Ysc036NftHkyci0ahNQZq+JqkdLEqynGzEkDHyhUXIHK3yfs5+jm9VG4JcE7cH79sS XOkZVMYx86vjScyACj2vwBc9bz/MtzY/6j9LB2/IyAygjH+UCVrg5GXsFdVhKj42Of92KNh74Pip EMIOj8zNkaKsVscjjwyBbD5J4fM/YcfNL0nr4iPR0RzKP0V7Q+nWbBp3vulD8AX7106phYqQdAjY a3n+NV4kL3NEbd32YF1JRiw45GpznYUw906T36vYDhKOqi5gFk3f4MOs/4G1zqtF3Sz2TuJj3j9k wxeyKLXq37RB9e+yXREMAMtAMFpHnZZTlIORYiz5KGpse2aCS2jW+vP5TRAhoRkTayeitixAKtun bFchEHJxm34DI9PLxgZdBOK7+4xZIZXc0TLeuOg7JTqi9T+ev3vhCDuGtDmwF2+0bfQ/6P8fNdsB F+NQPuIYaVIsqMp3N71lpk84dW25JC4DHnJWIMWaw3xO3UBHqE8KuaYLOUhWffxIHX0S89XJ4F10 H3jGhBS1s2yIDh18ideVZhoknBZazNJIoc9f5X7ZCIRRaWZSiJ53HpkfxBrR/JuskukmCXvztoIA kgoVAMUMaFr7K5gF+vEYVI22hlybTbg1cmKhJaYJa9qUTFUHiFPoOfIXHaT8M+oEUdGE1pSdwn4t CTu36qIV7gm+jbRji/wt/LE6y+U8ojK22DSqZ4RiVkL9wSHVmm/PwfihC5IhhPn9YkRRL7enE4qi aVUAqqjHVGE7VKzbyGRfK9OfIVFoXG4kilvR8Ake5jOZ7ma4mRh5e3BNyAY4ZyhUK+7/IweL3aZZ NIbSZPiQPiIIl1DUvIS+Igw4ZLP0YhD/HwcPi3HcqTfQRFt7pdDGJ8JRMWI6eZP/La1PiXLcDYQb jEkeuOZmgWCZVZj4+htYfz0YSHMCzC5TGPpHp+oBtujmkuVS0z3c+wobQdV3fjD78y9v2EJMN4Y+ GmqruPXaOt7V+nStSLxKdGcddBdeNB1PXG9Ukay/clKr/JpHvY56bsJ09B6udlesqmmhBvfBtE7f re2XVR8kfLh0yoA7gzqsAgV7PFZtskRrTg4mUNXdbjSM8k0z4Lv1S46TQo67ms3U0dRCiRITA4Ch mE9gm97OkWIfDkQrU58YUPD/OkjEWX6OBTT0YYvIYTSnpB8e2PeGQ1HHlpdKBzGLcKnrPzX7yaQJ HfgifzuuQ0feUVIeX3ws+O3Srcym/y4RRpAlZi8ywxzanY9pFHy8RPfERH2yZJdBVwMqHRhQCkyU vWkBVqHu7AC4npXYJGzwtncLxcJrwZpcCUWplMML7Vh0VPZMCwnZRyo08TnyzJh0c4RbFb+BIVnl bFmqMhf9Z1PUEXEUgz2bUUgXr7ph7NyELT6HSz5i0JAQqM0t+UsTuu0skal3uwVgSJ86ezWHAAv/ TgDCULf13rH7j70a3oXyjK+fa6xEKfLD+QRTq/FvN4xYJdtNH8zhZvSa3DCOJSPZzUli6OVwi71p NeYpqA4l3hhcdswUERjK1B7RKSZQmnB5GWjKpNecdsoUcrZH8qtyUO7XNgXRxd9PZDfX81GDeurM Gq861gbDelGfw6Z0R1wlLqaPZPIkxDrFOSkMH1qNO2azgePM/9xnaNm5V0r4q1fP8h11jLsqiBGi hlq4HuTHoSIQb2Gi+WeS/PsadvnKClaeX+FiUoDq41mlIhr/nNSfM1dURZHbiBtxLIOWAUNQToAp sPkzVWDU+0oll6ZubQMas6ZNrdjbVEkC5kezOLAk2nR2ypa4Scwq8rlT0qYtrpQOV8SHcUaBWYXM LQ9ZVRJGl2W+c9yliCHMXhgFsILRbhfsRvrmzX8erJ772Ws82fwXv2QtJ1Wc1xkxscEOWuqNtCUT rXc35xGBY26THus/eruNgUGJy7s+xRT70s7H7CEmdw4gcqGTz5/oSJ5ZqDhQH4mUD4oAkPAHKNSC eddUxlR2KW06IPNheVSeyun0xn/agsHs1zaUBRyk4Nj+tHMnkH8BzuE4PpCwpoGzMTaEbvtip+bX UmEToGy5FhVPk7WmEyL2OtoAhOlW8vz16rVT7mWpDjhNewVlBF/wmAQbxCByasP9ZW1Ny9ibVF9D BrHSpum8gbQBh+OTq+070pyiS3lmU8xeKNLUBDoDaYDcXQAkekl93M4l//ojBatL7+Z5KB9UEIBu P5OQmUEqxVVi2378cGsPNAiCWiNJinUC/XkJWNWnuXz20UTH369og/ecsKuNK09elS2LCZG/TYtt vCfGFx9lTSEeR5QJN91RWoQ6rP4ddS+eUpPveGHJqKYOeUbJN/9UYiBIHYHD/KsdDbbS+mB+RxNy Erc3bkyxsl492Lymc7jPfoEp9NiUDQ9eDH4XLY8T3w9Ec9G1ln+bOd/8n8JVyNyObQXXdN3t96HQ 8PUrqOFUPqJL5rsfSettc+28ZxfyRgjuEXmNK3JIzWuKl78QPxk1ElaQH+zuAlLwbkvIsERCpkkc lMrgdYAjnC/rv2OcxQ9s2bkimlAq+nZdQfJebBp3bze+T7FfQHkXavHu7YyJpMmFBRCatPsIO7tV /Dn8Nt4uc6mstorvLbdaYPwtGne33Dou3P1yzIHGImupo1LaJ0RNv8NO76ROPdHV2HpHSSbxzT14 horq4iMDQgydgAYpPV+zEbhx5A8cKt8SLr100gfS/Jnv0M1YRYl4d6tYNlQSlOu5XXt68s+AKiOE ddKsKVFZsLNVhgAL8rHXc2XNx7q6oW2D1qYn71MIIivW2Njli3rcTVeqHSXyHuNZQBHuZ0xH1SND 1EzWlrmgxSbRiUt0+VsuVyJ7py4+Qv6cZpRWHlLiOG9A9jwSCQ7hKZeVs/9q900OlmGZuU+xbG2C yn3/Vw1fqtGucs2jIGRzXNFnL0TaejZV9WWRBlni287W/kjnSJdSIKB4eUr+wOcNX3+4uJIuCZqS M5BQw1znNSJtX0jUN6CEF3S5jO7eg8k3jAsCPjC08BajY4lQU6pqiMWFfKd0Z09wgglqGgeZfsB4 /otYNLMDOu1gOSHLWOGhhZfQx4HPWXzZFi1FwNEMgGqm+SfjMjGDiaLdmbgkXre/4rKyEcIPO8Nj RjJ6BbN+JLyc4mzHTdT4QEpH38onbkp2j0f534feudmYYq2c88HHmusFVBBGZM7PXW3a8z/DAUWM jEic7wZtASx9W3nBBJUI6C01A8H0McIpOZ8O0N/kSuszSgh6TDrCbZOzAsQfRGN0MuBNra9LOZUq zRb22cOLod1kyxRAVflOU1RG71URvJhSRlomsbYtpqonUwlxJGA6uexbec+kaCTp8OL2ncreheKr fejddHHE8w+Nd3zPuBjBC/7Fze2U+TBKOLumIvRhMyyEGocvcjAbWz36ng7p2o4jCA+cPXATS04P VALFmr3LqFC47EtwQzJycnsoonlbaA5tva9JMrZeZTXNg5fMDQE/k12cO771sAPkKYPb/t3r5bhJ xvdOnCtql6T1Rca9u1pF8OOnjJV9/IqOREtp9sFzivSJ9SFDJSsDV5Gap07cEwAzpwJ9uYo53UlT JaTZ5sF3OXCp/Ja6AqZ93VzOjefLhesr/E4EhHQEx+iqQ/o8zfCWX5oS6uJlb2X+KRk+MEGK7RbA wHymR4BSF0qLZd6l0RmeNYOw/JrWRXKJ4xa7lLGsnvaR8fCY+UcWl8AEoGPOZwdU0JhnVsnDM3sw Oryt85+dB0gUzu61+Ygb0smFo4PFLWXD8HEnf7aQSfX10ncj8HJrGLs17UKQULO8cW27v+yv3Rrv p283rryQ15mgpPVuKqH9h84QYQ5/2mQweB2qFBXnrV6eJ9x7ZavV6cR67b+osN7Nxos6DKqeAYbP 0dtHTOIIiUxvwDv4U77IN2sgTq9/PcLUN8/sg/CYM9OeYSmeGLNyFqDy8RwjVaMZSSkJZ4UvuNor rbnd0YWOcd1RvIU6WJWh995ojp8kfQy8gbnGaKNoiRQjkwl8TkrK9qC/Tg7RpsqY6VL8LaWrIupE E5F2XqfeUGIDuy9GwmpUzz143OZ8qqgyYlPai5rbFqV8VQdhOpvzkUI5PEpThQG9xe2QTpJpBl7Y wWfPUky3EY0W2OijUqL3uf7FU2j4KT+aSHgCHfLxQffgkwwMFJHJJ5J8nEbhbkdjH7XQejRLB38k OBJKDPVLmnmpxWU+uilNq7nscjik2hHqVzSsf8BQAJfYr+yM6kdMUwK+H3W9ewpcMDnupGrauyq3 S2shUd0qJyeUFZkWd9vZkBZq2V2+byKHHYCiszq+7etcoVNQFcFkKODWdB7l5rzekTOshogP4B0P Mg+Eg6BJDzt0edz4ZHL4ETMLeVFqt/0VJNsLDBOksKnPF4THl+mCoVFPEc9rZHvxl+slmPXIOtux lf3+7bm03NXzAlFTCE17Stpx/ypRBvpXSHF3jS5TxKe5n/K2Qbs8GT96ApNEeq1JanufCMcYdixg 6zGWCnTD3mKFycw/PDEOW0WxGvsFXQj9TNro6JgK5EasOnmAy4P/SRZymqPoVHJfmFzXUfUJ+5bk V+KAxpAQ/RSd34NPQbR+SK6bXivUPMTju66bYs2pN0a5IhsI0y2qdrOONAo/8lGRukRrf2BYRrEK F5nmOFnuVEsCvQRJT1zPadbgrrV8Uv9qUx2FLaM/NFWkL4ThLiiiRjJyRjUubK8FAxvF5ACkf9lh X7Wc5BQA5fYe8HVmg8XNRDu57vBiqDxO8eaVqvuz6fO5VfoDfnex9o9S+NX48D/ZIqjr4MbPnjfg PEC3iVBGyxvYpCzihpwM5o5ojKwrbnrDw8noCqicwOupmxtDKhZQQXtr0nP1D4WR3+vhhhKOzsJk pS4DVwBoI5PCh42OopTFFryRZtf5B2tUjo7vvrgt1GjIoGCIGH4SsmMWw1nBgtbeRudZh8Je7yWU /EUnxRUJpKfk+q+eDWJHYkC02opdPVHRDHFywPJN6AuT/RWjOLiFYortlRhJXKHnbRx43NZMDsOY 7I6q2CjEyR4EgcYQ2T54zAjJ4QbVYxR1ouVhP44lsl+db2Fd3KYSKx+HVqHftLZdUp3KxeAzbtdQ DHQvKU9TDEwhpoQBMJdtcz/elg3JWWoK3wul3NS1ZDO27U+dUP5NWDkSBj5d6OriRnmYdC1E0nse 4JHbAecxXNys7dHXpgG+ddLtQXJhsihh9C0NbGVnf4SJQIlXk20lHkpv3N8qzuJ+Hrdf7l4fBQPr HHCPndHQNsGbG5B6DkIJGhnT23pqkQpwrvACjZojFlyJf321Sejzyq+HccS94usKnsGOfHI4qgsm QsAMi9sw9dA37R8HtADfkSgQQe8FQNBNJALIamsuCivV85quy/U6FFqNjOMirYw+rEsTrJS1lOsD FCrlRgG2/u1in8RWULsQ3SknOXjkGSIhFI3BUL5upFaRd96tjxlSECz0BVxU1CqYXiwjoAe44ymb UbG1FgjzIQdTwZUppTuoadJWmxfjeb2PcpIKqIg/5I5GYRkhXbKFAlnL4QUQChQXT6dXOybleSEC y8P/vUu3DpiFXhhrYx6Vq3D9CW1mrYRmqQnDRj9TbZAaw4SbYjnEViVz8E7B9PNfeZVlOZEyp32t UUbmAyENg8pV9CKTRcI56J/sqgWAAxvg2ozBQrwIjNQzAs3Tn37fQ9gdIwPcJUGkxYo3zMrPmJ6o caLHKmMoMGOIN6hxr3hKqEH3T0ptufPpcWWq6yxAwxHLwsGRyT3tFx8z3e4AvOSg6mzNyYf0NQnr c7qqvpFJVTITUhrb1brUZ5sR+kMpwSjpXJgOia4JrnFadd11K+W/NtTZAsl0ut/bD/FDc7nJ7TKv OU2LwyPpqamqCh8F7L++nQHs0Avijqs+nZ6a2Yd2ul7p8iwFkksC6Hgcb2ZHH0cGM08OHzRbvTxy IVUv1xr4lNnwWofit89IHPZKpi+ZKxO/RECBwdBQwU0fpsu6/QkwRHqexLUUPc76Hxz08fk8z92P tYgQW3T+82Ah3KkJQzJhYLSPTLYzFGHpJF9yCSqOjMle/vARz25X7V3CEuJB3r8bPdzUHgkb0YY/ kxKv6w2oY/ajn5starui00OWNdhErv5AR/RqNUelx5yA3UEJxWgIcBMv4Oa1mHvFG1m3FZuerKrR jeJONZP729Av/Z3ikuWJVTAkPmAuzr6E8I+4tK1m2ujqBltssaKl6BhdymqFrbEJJZYUZ72dZHm6 OHywDGtOLMv6prWlZKNjB4RK7go/D480wM0ijPWivOX0oR40yC2JIJF0I6MvM7vpAYNUnx8Gso4t KA43g3EbPJtjwWvZGeLFzoI0hD4V5cm9L9PModz5BoIwiJ0jwK6ntM5NN4kmZXsQt77ObmearNR8 PCMq2hyM72rLoik22QbB6GIkyLDyaewMkXH42zm0vfEa++e1b4lgoesyYRRWtciWGzYdBDhw//KX 9wv8TMEbXXzQKTecRXnlS2CEACJ33XO+qsDC3H/FbGZYEnmOG1WXyW3O3kzNYrMVpUXohyqEUQCs pufxFTd7vu8JRN3OPRsRIj563GMN2SF/lssf0jslydSN33qSNcEsIDIJIBsqcRDPJBH2VmDpyPR6 QcgRqG2tWzGckFI/Btx6ykHZmyz345gKsV3WKlE4Uon8cfZuZ/Zr5Vpn6V6Y1Zn8z8zTczeML4Uq H4NaGcmFDGyeRfj+nubZDkc+oZZrn2EsrK1NLl1v0Ae5C8YoeFKHIfDT1H5WVw74oPX9p7A2EwHN bXFoDz1HP1+Vqy62X5EWLl2n6O4ouWJ9rdL7V1n0rQeIax3faYpSQIS6U1+HVM1X1pt+clQutfpr DMw2KSAifKV9hmCQDHdIZ27QNpkL9lvlNuhropRoeDN5SWBBa+OvhHKLg1muzuH3GmAb+BIZTZ4a CEzmmfZsO5oXaV2Uh+rIFwuxYf19GbNw6hbW1EN99yd2tDIfhycYRYU5VzDv5pHJELnaXVwsfRXe TXZGzLHwejTfvQuWrDckPMQ8aSj+Fkm8Gu0YfeEfVtJqTaZZ028O4OaWWstntMql7y26nl50wHgL Mr9Gh7qVlwza7NZwbegFyP/aGmbpfaGeixecDxAkhqPY8XXl7r+QBCBactna6kDLFo5NtAiUjBKH zjgRizBJDkQbeT0PMlVZ2a5S2XLJiUGOUtbb61BfcoV4XXCFY7okH1XDL4fuNUaHAIeqc3ShoMCq eZ8O9Rp4lyLbkcB6ytQeE77dAXNMlgkqaNIQEiPhMwggDR4kr1zcY3HSRHMww44bCWajYycT9jmR iobNlOq+4qa5zCXck9pNF8PEnJ3SwkygSptJnPUNpcqQXmDdqoMwWR02cIAzE++LPPf19Bru+Mvy U9UlNYXVuIwAcwqtFQ7w9m2QtGsp/dASB6mAa6by5yCmA929LX8aMTCmU2taPP7hNyq8aBjn4wJK JQuju31shpR/vLKXLy4Ovr/kua/LrldGlmIM/qGoaQC6vp0VtV/zcCKOte+JNEkeB3w+VXx+CK0A 8ozxbZcikP6+gFWv8T4dcZsAe8CmMOA2RwHamafCIUe37kcdgP/JF1528kqw2ehhaJ5N3TPXw6U+ A2c6hj4vdUoeaJ9Z7/MF0QhMx62ONEgX+8pHIV5SQnW4JTbJPkPWMj8qj1nr4BnmIUT+WT+Am8bc a1kc/ZeHgvSJdzblRUD5H9cWRmALDCbvSL6TLoWEr1qUPEYpTD+j4vAw8zsQNb6MJCQyPQVC668k gEa113d0gx6VISdTptwYHuxccwXHBRSS4bQfUtrb0hdtKcET4GouPdfd8hoghSFhipbWcJivp+Lc nstaHfReCFhaxEZhB0sBEU+yQ1aeBq1asBbndo+RHkpQrdR2y/7TLFQ1e0DiQ5RmGb6dJq5OBEzo Uqs3HlQyKl7LllN6WSkF/AMGYyYeQ3D6FFJJ3MJ1zVHnta4I85Dzr3N0sFQfbZFZktM0FLVculZG D1nPtmAK5iRdsrkYe1O0WgbzfG6m4Vlp2HKXQb/NEUgrspJttaezNbGZDX40MA6kLFf3ye9zdjBh YOXWAxgVRAbfBqiwTIKVllvFF33vCmMQ0JN/hwfNErA/ZwCbqMpCYTmH/W+CTdyC529e3NtBFn4Q XVyey1LTL6AMg8o4w9ur2y6hxg3+4x2rzEU455PTeCvQ6Aslf5xmmirNtmFHFh9yFVbwV5DMbtr9 PxxG+FeK/KYZG3ZgH1wT5d0B0HKyfYtw+6OFR6w3udCZwJh71SvcniH1wI3HW47M59aQEDyDNHIm RD/L5iHHiaRgLaHweLTV/ddiqBRjlEOfTkd4YJwVD3Z8vrcBPJoEm850w6WpxjhboG8Hb1ehTxgH 8aF0uB16bHezaiZWBSOqQxOCt1qXYcnnMdir5hEbCiJibitrlRGaXrrWNJ6LCVw8xi4xvewqDPqS FIiBSVbAwShP9xclZb3AQXZEwuG4E9O8O5n5q/cH4GkbQ2zep5IZm/3UvhMs7iBV6oeQA/4oREIs GhmlrZ7nz0MFY3CDyDr/tj1Vj/e26evLE6TKP+pHzvfzLZbRsRUvjh1/BPtgXo/G72Spv0tKgdx6 W3egB6p5nitn8OiFv2KAhqcCAudMiZHHERllWhI2WfFD29Pl6JaQbe9sxbcyQuMjayXhqRFsU42s /vNCKHu9OM65ersK8IAvULOaDJdm6K3y2Z3j9EZ8QKz9Xrzbpz/MffFTs64HI98UC8MBPbYrW8C1 maMZAVp4r3az0sLc8+vOVv45z/8T+iv+YYnzhNa6knIQSxtL3LfbewXrqSB/aBHq3GUILjiEXr9n CYZdEg8g7yR1451t14LJCkfv7gd3jvxtbhwhcQK410wd+wxVmpMYgSL8/dcrWCMAGbbADsQu+ukB SIFEf0wpJT9GothPgmArJiXV7PytX/BGk76kNS5IdAJpC9UfD3gJJsgRHVtYG7XDjiVxkk0ouu6P luuXokHBZFNlor4aPe6t5jk0y/DYm0xSIz0rF2C+Y8B9JXs0YyGFr2H9QLSguSw4Wpboocot13f3 q7M8YhAYDZELkPsXWhgvjcptxFQMNx3qyjc6WhGmcqSNZa2SqyZqqMZXRLOBitlRK4rkf27wL1gX WphtJ5OUNT+Y3muSmlqS2nYIxD/TBdkwsUfPNyVVNI9YV31cEyb8TtNfxd0Dh0ZoCup5STOdBjkP Z8iID5KOm3LMgsW9lxTUM7s7vd+ANDldOit4qhBUCp/5oq77BfVi2oFbHD4yUxNw0UoXXhoaG5g2 w8c9pQkngFUwhiKTR1Zn2rkDN60ij6bCZQfwxFFihGDgZMk1ChF4mzA5b3Va5oG3KO8NrmUEl8ep B9NSh3Pn1AJREdaRcMdhSbtED5eTMx2muz33x1p+5Qnf9FbtFBdu+/5kWanslvtLNVsTqETfRHzM yEkWOuZwXSSQ3Kgi5Vk2eJeeQMGpwctKuPjG3Y43NGnpOAadyHPZAo4dApAfohVZGqLfR2mlvpmN yjPnKzPckKq12g2BIY5xxNM+RnvOG3gLvnLVR6aNu+6/B8TC3NHGlpX/U0LznKr6HmfigJR7+W8R Pcrg7W9ptgkATpioIDPkS/6gSbOVcA/PaX+mzmncShQ86WQ6OaZSazRGTyCL/5YMhXjpPl3CvgnC rOmhWxkRounawfvutqVZ2V7CsBrjMw1P9mNxWoaJNbtXeZGO4/VebN8YKAN/ys5lS1905szJVdmq 15uJNcjdfXP5ibmuqgolh3GaJeSWion0p/tMZHLJJgbdohf7C0s/+hCC3TjwdPe5Sw9UFo7egMP8 kj7QWWL9f+BN87DQtc9MkkXQrWbq5A4xOTz8AOVn7VzAd2/AWQlXPpVlWC0QCWbzlE/rdrN1udpa L9c4uh75gNB4fxqGdKWRw3fiUFv/+f61PHVkGd9tle/3pgxKRFjrkJpMAhzDtXLLdqukOzaWQfeH 5BGYyxuyLO37CWQoz1TLT+14zpx+XUFTPINFPys6llARPRH3J5wyicy06ckWta5LnIYVsekqPL8t RcTY0t569U3mxw97FRsYvbzHfCqGRva1TM0Cy07ylITJysq4YpgAj4QNvsiq3I4af66F87Xf9cCc gfCUXh4SBTxSpuzrrTQS0M0Zg2FXZiNGkrZb6hGVXMgrfD7t4rBs5slKoSQJ8lDAzPPl8uRAGAlQ AUp86HvNxkvze/sVIQwo6YsnuUjI3wDDF7ZN1As9RVIXeuCyjlPxAh6Dn692bLJCAmg1xRAeitBE rA7htkSqDUFWoh9lk4ujuxjXtpd20+P4HSKfc87uACmTS5Val4H2rWQUSuFRiefFyhJf7KDOJYC1 wRTBiaSTCla2Vx3BbBe30guLX7SMyNsIx5/7AlsJOebTTGeH7mWkbiablTew4jJKg3vfVSAyMRfa ++S6JrsJSUIekNLrN//5JmU/+GPOCQ9zPBH8ONm9msrtDXwnmqz5nyxXEWvTTTrIU1HrOkQaSCWz jyjY4ngtX5p+sa/oUf3yT7EVB2XTUBuIS+xZ/u+VjST+IlqwgY460eC/gfDiADU3zyj1gympETp8 ukwjqQ8DAJasNvWGg7yizlUB1MUspuya7kJ5k6S+de8aWwni9W4SC1fYw9JQpBpBmFOrL+slrwIp oTkxo52G2z1NJPTZwesDQaN5OOMvANG9ua5LB7FUQQUexqJrFWiKlLPwZJ3+aRQaQw6GKO3LJNea PGTZgrz2wawEGkKYtC7egMkMQA7OtGZXi1TcoJ2NH/E/epassiu6Hjfw/kIG7WV2oiLgcS6YEw0n 8ayjcB+PcHsOfMjvV0har1jSmHNhYnioR+uE+FcJqTLG8XFRWQ5NZB+/8ygn74lXEShIoxXtQCN+ 3g4Id+8X9VwygRbFn5j9ljPHr5rzxnM/Utuk0yroYvVgcUfWu9PaDf0U9JOSaNmNP5kRuWtPnonq THWyW7Av/61miWqt+pFaYs53pPgDcgz0sR9uee576Xco0KkMEvu5vfCUn8prIyRBDkjF4/h5b/Tp GEP05SlyKwVx6DtMwsm51BzF9fTELkKyZBBMc8SGMg/JlD64kYy4BF1aQYBxHaapB8E+as8WzV7e SolfVnM+BWWUh6D6TO8mQlqgluxGhJU9NR1cFR59i4Ckk1JDTMqNO9ni9q5N6NNtqnnenMBCV/DA p9llUN3JApGiV0i+HfWWHazV+IsrdsONFA9qXfFamjhUINkDgxWjem1yPtkJAoqHxCvh+oyPzxJm qiH7fZ6qGnN6QvRhHzD0+uTfTMAOMDtSVzpjK/djO1M6/54Uew+iKyMr7/2J4OjRxXrXlYjnc8UZ vWUZb3dC7YBEZeHnMtAfLmPmTGiZzogCgFADTUcIY343H+Ybkn3ctnpqWjR6c9IpbgG1fgtw3oBa MtKO5n4eAZqRqogfuNdNJsCE3oHVkeJhmLi94CLiKH+p/oUBUkKrEXOGjYzr1WCGcpN8EWt7Xr8K Dxz17ftsSEAcD9YYuYiyE6txcWlk6SztSGWMXgwGdc33En6OyAEQ2vuacKqoH0xGIhikxYIsms9w g7TMIeX7hjdg7LWoFzIIuGS1iBSolvScbqo3dXdJ0dbZrnEW9muKAO9N2qpOuR8XfIpcKHKIpOQk he6yVmm/i+hE/ty4bsV+SY9vHHEzY+Z6TIRK+EIA134yJdi2f5Npas2hufn2j5XjZ0tRUtPe3FEX k/XA1TgpATKslYVKXZxKmwJJd9jBViw4FE+AKnxJpCIrRQdVqjatoZyz8iewJ5+vh2NDb62JXNHu Axb0ghLHtep4FnNEmjgBuumYkHP3elCDkP0SXbT8Nj6lPmImIssKxqv94rLMS2D7xid3wrVEliAJ q/hZofgjkNLsQQNNsLNTEqa+gYbEE/0Yvp2VRe4lpBtRVKJdvCdIQyaefmPF3GLNzWLFBzy+YziF S3/xm8X05HW5B+3wUxTKZTZqowSCQ7OFDVGY2SaPrpQKmMZXcUQdU75Lue0llh+3WfgN8cZPIsgz fHOOw2tjpyc83fHo8QfHXzOkJy9d49/UsP+O5VET6gWO6n3oZoN4/RYXLrvUUMfyR0DL3iAZlsie gUhQ52aEHV31ZbQ4UExD2zXOGOZ1II3F/UQS48XQ+QGYemiEPFUTa6T8J8B34bt1UxxtxBMa28p+ jxv4RdkqD+lw7TQamofYUhahP3MJjwUNBZQn95mzQ+xrSW5Jf+dMUl1jUPDTeqCyB/YbayxQSwfl 6qTbIy1r+RHobXQIsrfa6TRITzkev6Te2jzlsr/k2iVEb+zjS+imZI6KyGjMHwEYmppxr2zGN1FH kSpnkW0I8zZwAe4clVCgOtnApaVCqWEWIsnRlZGMEokS3ZcIFItUfoUFxrIir1fgYTzyrhatKASu 7lEkPul3YFCL5hcf08Vwbqo5mF8+D/GYssxxADPE9PUuF5iPW8kMLketEtuDHXilgteQ7veBVDC1 8r7orqZeVWlQ7h0nOHY9zgtuPktJes4Ta5qEGlOtuDq69gK4+P1T0SeMm/ZjVQRNg8odDUm/5Etk ejxcuxtelB4qsqJ9ffCiR0HXXxkmCloFaey4pPf84Q1gd/bg+eOhyb6iRVnTWYvScDDuZgJOgiAy 5fqOCwC9wpYy6kpVD+tRqO2WwJsvDHFKgWhFY26LYmg6kCCkSJWONGtCgVCsInqkqKFUAY53UITH YQbirK0ihPn97yEqeO0d3inpXtv9GrfZiX1ITdKMTIGfOit5JkJM4OqPm455FtmvsGcBzOVHcP5D bx0hzCHpBXGg6+pZiaU7QXv4HlgMLTvSDTBlv7D5KuuAnNQ3ujGn+ZQoNWyJKIiwaQVCvUnNHGYB 1G9mrnXjTzmrAfD93Z8gbR4XuoQ8H9JKRse8Qx2eaVN8/ts/qHDRxye92IJNCEe8fdJyDJHwcKvI yvjsGydm+BFxqHCMwFZTHal7CQzpJGnPb57v8isLGQ5jPeBKaWI35nP/ux/PgC9Awt3HWhPVxbTG BuM/V48y4fVHiAGbG9XWblD3oXLE2xH7M/JNZs/WYTWi7weS7FlrSnIyCbxPloTDLA8osWzUxyhQ IV9miEkEKc4p9IbrwkF2Df4a58yY5AsXjrHFRqNf2dLDa3aYlgGUa5M5okwWzWgjj30c08dvk8rR w9Pp3AEQTc2Bg/3pBTWr2OzGyWxsywsvu70sjFtcUE+psqhi4OOcPLzgTZdKpONdRFObxXzJ4p8W sJzUb2H4XPMvhgscCZmARPF63Nw2jAQoNYzdPD8pGtMtcnhbY6ThEDnGKVBd8bGxYCglwYBmyRQz 7WmEkBtYn3QtyFyrOWuY8VJ0f59iQvKpLhZi232hilRCSW85Q9pMO+yTE+dxe640ts/xGz+/gtPw gJ7LXaaHVFi7TI0r4eyOkGPIuaGZ/BrG4U5wY7DfQbw3DvOeEq13BvRYH49NUPqKzWsAKvy1klbY WgFSUe7+YW6f9Xi8scBYlKvgzxTwGPMZgIM786sTtOuT+IONTgFqvPjgg6oVhHraNN9uOqrz0kjh OBCMSbpUA6TVftw5sYUk3DCIJu7OoPbHU5dhBnL2FWPOxKuVTeHOVJ/a/DkkajFsIYGxw6gSB/pd eFV4sIqQTDhJxVaPJ0ojc0cTti1HZSwnq7Svgh9kMAixk+Cq1xeKa3HxO+/QPON0ldlVSIBnlEk1 UBtkJJyM6tq+ofPEDdlG1jyLyyaYg7KMvqYuabz+xsk3c9gVcx83VjH1ZpxZNorclx4rnMOE61HK XlEepir6rao6k1lNEejHH2jmgXkSET1+NbFEZHASSygOIbjc+302mjyG59DQEbdx2XB1g8ZbW5mN wtYmbumng9hEDzc6SA7O1KE/jC86vsv3AS4YN85G4qQMeC06XMnCzbO9kdp8JztLwGcCDaxOsEzN sEstQ0BBaYo4lkJNCw5vOKx8wT8DP8Fyy4HUw3Mqo1dXDBtx+SVMc26QGVxMCVJlJuzVB61I8V0O uYkDIY/NiLD+DrMLiyieNABz2FwjsX9rEGUpffu9m56+wooglxl1z0dQNaOq6PolcdDwMRu/hwe/ s5+Nag5OjqGcWBmfFedyDhGpDFTK3cz3QE4ZQ32z+0Kg9BMfpCmZy6XtIcfqD0rBQ/YmmMGqnsRM oJ6C7rBc0bq7F9qNY/vCqGUk6ncE5o3405A9/EmhcEE+GexJUjEHbo1KrOYGANn828srv2ZBMnzW 1SFNb5ZoAFsnAkksPyCjnwImXjjTra/6YbORY48M+6WSUkCVkqBwcTjA9eYVMdw+yfKUubnIroy5 H1Kp3FSaPB1IFGhPuilUsVIrG57UbzzJS4m2YaVsDk6xpt41l629qGkT/3yoHwjd+SdNoVNqw1sH 6OSGmwmbvpnXFZbmJrVYlKTq8Ta0LarV5HpEFOxt/euouh7Sbg0s+eMKuLRzjcTVlZlLX56yddWs Nd2bmZt2YkNwJQaKlxJskMgIETWnrpbSCv+r3zpf31kQj+aNXoVbNIKOcov7QGNfm+rpfQk3LOYd RWB/mn9JSoHVOGzDTUMnXBgtra7VxIIxPkddsVlIcESaLgf5wu/cKPPq8GsQJ22/IQ95kw3WUFEX O2UoBTjkNZO4b4MWInrVOCuiAiAuoAgzFXWC9PIkaVD+pabjga2OaRh5i4Oc5ML3xwr7sgk/vE3A SNkjwUFwXZldmCLCW9jiqviq+ULJ+nkQBLhYftlvF6WZ2AkNV1EX9jSqFtmLOifHsWxg5z01guOt EGEPY5b0Xd6dbME9gnpsZVaQy/MkmgFTiNEa2WbNU9vasZFN4RwcQb3FfbzktzTJFdFS6YKZqSgv uyGl6AdC7STOV/tQkVPlJsKVssB8pHimLCY76SGeQ98L7LcCEHJF3b/si7CgCYgHF9szhVa5JZRZ PNa4XHjwjzz6DRg8dK1B9UCpz9EfSwqeAxXKPiVZUtYzTYb1Bg3/YMl863Cvi/Im1CCl8QP8D4kw 0hyszlQ9GwUiqs1KJVxPo9HF9bIXa5Df65kEEMsucHHQ1EqDOA6YFXvMHjAa0Itw3ZdZQunw3IGf FMPqjyQUYc9zBxUxOFO28iWd+8CC4Xq+zT20Jqaf9VQokkni0dnnXiqR0w80QVnESRPZucENbDQ8 7HSiBKlMVx6jG5570dH3oR0jw03wq04kxBSE4a0Pw12TCtP/GBXEZc/CX0JJG/+bcwprBxxfC4Z6 DAR8i70FIk0U0ZuGjXZavwQTWfeX00uO5Q2jIm6nVOKoiRLE/+SJ+Wjb75xjUU/L+CxsJPT3TxUg eAzQ0I4OxBC4oJr+AdFWB9WSFgTydsg5dj7Fq8MbNovAgn5vCxWAkaSyt+7U6/GVLX75OzOlpWbK DrkVYRth4a4rO86lT8woDRzsTnBPes9BriX+r/uscVG38r6ogNcCr1OpwEWKLqk9Y34kPwsHlgz5 6DGk4wgLHpu0/EBYRrmzlpUw8zVGtmZiGvOEZTwnBV0NhemBPPnR8mEJTAxcsk0sBM784mEQefRH e86GCV7EDz31hKL653UoNSsiOwa5jXy1vZblajTdyfLuHCke2Z1zaSmh+V75K0LSYFjVCrIxpiZ8 w6mHSlH4qlX33vPTWucT5qCPf91trsSv88ByJO6Q1xCxqqmSjYYPchJZplzUBgwPObvEyB8bZPbt JV61L6DK26MgCP+AXFGsH0tdkT/Wod4EVT7NwfTI62qtNPFUHREKnTsl48/pABxCEEvFbvhz8phx etqRXv4w82ia8cChOYZhr0eplRgz7OgQ7jc/9eMrURz7/g3QgyzRp+jQO6LkB21babkKTN76QGw/ aJtJGXnzYzVYbyJ8ZXgUdbmpnra2f2Qdxs0YPcUwndDZIlwE5vZ15PzwZeYpF5d38dLznnkvF77V RtdmiUvnniEAZPV+01k5/pol2WMULhPsUaj/uhu0ABck2m6ULyhf3+IfKZcYH7EF3OB0Z6hA67Rs yX7GTFrx4TcDIH5a/fEWHr5BatdPGTVGfCwVC7OqqmuxqVnEzge1VoMOvWVDgB9MdTfMCaoXAgIH zCkmh/FO1x8auL6LAjdSRGw0EmqV4Ur2UzL8K10/p+UV3BwU/kbExl6pGHMyYYM90mtwTTt6MYYB 5gzG4+F0R66TlMTBXavGdQ/ltxl+DpODEZtKx97p+KHJXtu8mzQRSJCaxWgo4VsWvqxazzdXt+Hn ExyDvGiiy5k/aag9yEIQGFGWETTBn3rVPQ/s6dnEjfupq82hUHVBOZ+MR/LqiPy8O6KfYwf10S9X /p7il/5TvZJTAutK67Lz8PVALCc21sSBPU/haK+AFQDr1ECFHQ01udZl/uuZySTzKSMvFz8GR7DA 6tNJweSMUmkMevnSZ67GXbP8qtIUWZgewvvL1Es5Mj6D725AFudWHfCvTqO1g4mzFXJ9rRObXYvX HceW845jf19R8bBv6KZjzaP87K/ksfehtD/8Qc2J0uSEw719vJhm86XUHPM53i3t2VWiE7S631Rq eeVNdx5RCmH8/9h8TU+6csvBJJy1wJLUxDtH/jPgXfSfCR9cou7mYPKuFNJXByghJ0ULphnGuEue RciFaSAHvHlnijD5xev6s5+KJ1l7PR6Yu0Gr+ikIMBpZ+8CfeVWsikA7A2LHT7gAvg5doY/COt8B oqDqi6PTq2YnM0/N5eziOILf5Q5F37vOy7kBPXmRy7f2D4gAb35jVSXr0t7I/KoA/Xue9/N0TQef rUh0VfieRGv7C052IxLvVKuDIwxMBJhH61jVBLcEr+5jajMVhnrgoyn2bOkJvZuBj0hSK8r5fd4C rnsu6nSOMnuXkqHoiM5Y+h8xXBd+/O+ZUcrYAJ5VXiw9VVN3m+oHKCLg3RXVOiYmHcTTb/xyLlNg k1Q0QdNiC4jz/2g/fm1lTC2l9SKU5+qBx1IEHSTHX2w62/QWhS5zbfmggDUKMocHMAdXnscxY6/Y zHVroQppSQh+k/yk0GsB7ZTMyqqoWwUSsvob8hmU5/8KSOR8ngpdv947ZVm0gBsllNUcQNmJ6Bw7 R0US1F9yoHssOxMobnRvA3zWVZHrxnHxE/D/qxEfTr4pufGm3HXhQaWrF8oBZrbC9UdKkP9ecg6H fMeicCMF/ExlStRKx4DT3mvsI4oYmEgJvOEeyy71DUTmFHw45l5vuE7QGrpn0R0LvF52iIgaJmRq lo36DIFdUnoPXI3hu1My13FxsPCqGrgoBUKQXRJQbm8WuHO6PuUl84arfaUag6lJFFwsnnjEHAil CtTG38ogdU1/KOuYLafw00NvXAbv3QlRMEnjMDmHrND52ESLLdGFfMJigv3HZOt41XaVsuIA8zMc kKia8Y6kOSz7lnEHwK0AfJPNBbHqYiYPEETrbNl1HpDpon+SkEIPRElClc98PIJtngfuBA9wyp2s aJ7UZou0a7eceZU+ohczjtxsBeN4DEjeKlEcU0Rliqcwr2fFknTclxBhg7i1tEfmkZmALpYxxJeP 42ieUKYMqvL9D6P9cHLh5K41sLdoJ2IyuFvV6B/mXyA/Jx4JjoLB3mpr94fXn8f76K1Gv0nTvDqz eqFyTJmmt059cc30a9CHC41YZRnB3zHQ+SkMCYAb7ZaP/N7z+QThqR0qVwMaerENQvo28vGjkIaS oKT8zdoohZCoHIumAHPdhVc8nC7Nr/ccHcwE4E+cgtplF7z7MBW+zBEMSAStniuw15cFslaG+ARa bBnW5PIR7mAOA9SC++i0D5H+B8/SdXKEeoQaABx+jamVk88SH3Du1NzLDt3nFu9IejlO9KIOP3m3 w2CUZwkSVooo3bGZeE++RyrOulGlA/yqpKTJDXXsRYaws6bq6/Ucc+r2/nhTwVlUgLIkWe6VqsBX 52HuaT1NzEdhsIGzBJVYKVK2TR5+IDopqAZdR3W8CwzDt5/YwALjuxt47V5TOJHxggXC5OxgkIKP gEKUAE/KX66ZjF0u6t94rBLwzLd7mkt406iSyc8qb4C7UsbtZGHvtjmG9FWZh907VxaM2QRiLxNB FooI5LGSUWLiPNRrSQ6M/cBurWVOXmm2XaaGwfYBY8QkGGzdgKvJn2XM7Xf6NeSf0gk8s6WY3upH DjmnbnnIFopGu9q1GXHjG6jCkzH0scMwrSJS1QVp44KYcihfK+/Cz12AjrYGMgYXbBzaAFDzHNKZ U9UdkYsTifaeu6LiQnrijvhHFLcnw+3N7Aio2xMBFVT7Zcb9SE/DiK5aqWP0y0Nf2CfrkznPA6ip gDMAzG+8RvoDXMYtp+uftUKvOAeXh+UVVI4HrcqeOC4fZDIIbsLFNHH5AKJWFWt8Fun8vB4uWag/ vVvPRl6VNgcjyTo+U0A30QCb3+Gkrn/FmepeGgYpOOrXNrQ8MZzV2G7uX+2U5ZTiDMC3UeTPU77M zXziTlTNWuk0M93ZpLCnjECJ66zNrwnlE2H5afWBcMJON8iIHNr21fIks9NSs42MUyFH8soVasIN JfA9p0u2Vapo4hW4EETl26ogLsxSs+dnSXs7HagsGu29dbzZWW52OduPxe/U/CNEkfSErQoeZUOB lUASEuJeVKft2D1vMULu9mtI/p17rKgnMN00hmCDcVKmiQmLk1/e1TXccTx4Zt6SUzDOe/REn5Sa D2a0CkiJ1t7f4JHJ3FutjtlG+BtnpyVfrvwiQgWYRhw+rJ++AeCo5EQpFkm8ptxz7hTpJ9FkRi85 mUsmhUxCR3uq0dHL5b8qlGVB6Rv4+gyapQUfW1QFN5yhoty4X1F43NEHb6Ytt4fO6hdfX3lN9WXE mrZGaa3/wyfWvAtUbTcG2nstgyYhcHzN71V38hj1Q1JdUL3G40PMpb0ti2vOlwPKcc7+W0m1N726 hEHm21zTbSktM/oOiLuPoyXT2IyOQ73TyRam3rHv2QsTMD7qj/6I/kjyJlEuLci8NB13vH5vHCG3 84RDXGi+irYtaKt8hwI6bVgzK9XCniMuiOk7M9nbSBiDjda635rDmAaEEhX+q2kPWNDxoYChwPgR BdLzG94r7BDmJ08vg9uuOCYTrzfipge4307mRhP5bUqZIMl/ZRJX8vyX3jyyfNvoMkPGTVpBeNCD eZWr7rLMP49KNEUESg9gBp8Yz6eY91rOeoll8enNh8zT1stX8Be0SZP6fPVDEPRC4P8GYyDT8mqV m73m4cGv0NRecFgoid+eXnQV3HE1pNR0DgZdnPDXZ0KMFYZ5cFD3jgi9dbA8JGBmSQ2kO0ZQqIq6 EJIusrKITtXRmbR3663cLpq9OqRQYeX4eV22349JzYs+XU88NlYVFD0EV4n9upo6msXTiGPEvduU V+2LycHtiS17vYU1U/sv/L48pcAEJA8m0zFtIXWWASpSrFIdQIgSv1WXYn5ZcedAFNWJPoOoTR0U nP3tqTd8DyH3CB+NRl2DO4BPvdGf5lXfbZLM8WioklaPFUsz2ckf+9/DzT6KaSDCLd2eyngKePwS LehpQWt4RjdSoCAC8r/YiLR15DfwRWIT+q71LN1s9S6z1RDK6EfdXXamEQPiEllmFL/xOCTCqoQG iBnZFcT+YCGl1Rr2T2Gq3Pyy9GBTeqcTEjEwaF4QFL1MuYPECdHgID6d9GWubcqaAvoZMlH7ta6T YJfonOxB8alUajUeYb+i0gtvtrbI231XUxJqJOtMYptOUBL1YLCinarNiUa+DCyZx+e7lKHpVkne B9HECb19Z+VZrtg+ZTG6yFrUZSG1qPWOztYYQYmOIaCuDTX5dv3Uw3nUU2DKyhtxMd0M4Rpen9W3 4+K9jT12r3uRoT7ps08RcqRc0mKJSVJcJV0SeOjwENMitTj1MrpfXWMqFqa6GVZC8VJLBa5v5DXu yS978kTxVjzs2i3gzQzJ1LcHlqW6ckAOxepj+rP+gSZkd5gNBwRb+ttv2ES4xM+znBMHW2M9n1sO +aGeCpv3IrKtFNHDGr1Kt/EZdBi8A2XV3Co1vtkDhW/m+YIGFzqNp22CtXvbTnbPcPAZJGrLOFKH Hx39sAtrH8Rpx0MQwoi28mFYFM+6149Va2E46sQAlvg2rEYqc0KPWHRrgJfCQFAfn0+Uy+MPNiS8 g6Jd4VNgrahHJ1TxnvKNBXL0II5CQGzpblD2GwO4AdSytKbY+NIlEYpMZrci27TC+my/wYonMmdT p+4HvRIeTHQd75a+kpdbnUkeV7rCqjO2ZIhulM/Gakf56c1IHuaWwXD+xIjINa2pZQbvttO1qYK1 USLK9WCtmQAs27MnhDLr3yyNBmAhvQdjuWpSRzDqdjGIKlKk+vhAwyOOmYeJ/xkvltJ0Wvq0Wbvt 5+jFSSdeoOnO98IOAmPuWKTaHmn4gv8Eur4Wqgsc0ZjlU5O2w/JMsCMeupgtGpayIiO6N8Wa97ms VcifwdSFsxYOMbfGhyYNc71dVM7INSloTblkHds0uMFkkHOQzPWH6xpNvr87Uf6fqyoktTe8LbkC rdpum8rY1sx15m3Ws1uaqMpdY2RdESLeQScCc9WLvpjiNJoI28++c35b3Sev/Xbspm2V71vpejeI Orqp3jpT8ndgtwmDhphkmW1AgGJ5UZ8+M0ie/lG5sWoVDgJQ61xSDK3+ObrhoxAbVSdwQR91faQx ZaYkrffBPJb0pGc/ydcPQwNNIEFO7xooaeCi2AVn1C00BVOXS7kVSufi1n6Vajhrgfliptju3T9E uheJrKtrLrAOBIf3vAbcOJD2ByCbfVirdv5TI969xpZ+31nu+5zH+8lg8FYlOeoeTw2B5YvMuBJ1 pt137tUefqbT1aDXtY+qV21cjDEyJuso5lL6eOowrea0h7F9bYXc1e7vM2ENOY9RnXSIX12DXS7A 8SIs7CxkvdIG0k9Gv6smqk34fIsuTsiae6rLJsFQXdlqJNWek9LCB4jXgjMx+rLu3imBK217Wqy6 D2rw43vxZB+swE2+9hnTRU2ApTVn96NdLzxs920z3/RTdMX+yeQ6S9urD2lsoTwhwZ7/SHT70Qc1 DVDhTFK+M+52oki/9t1uKyIOmn/BkE3c4euOoSRTjVSQeR9HyqzYXtsCcR9RHu/qB0pI6TYQdsgg SOG7BUiv/i5YC+GAZfA9PWSRVhLrmbiq4AtlP1iopjDjLyxVDYeISkENikkQL/Ng7220AQkW+Tjf LR/Rs2MsU5dNqygX1LV/83MUQS7cUYT4PNcnAaDp5C/IiDa2w+wbAxBNu4DGpvVXZ5tXC0JqjOna VofvJgcBXJhv4y0SZB3//bf/TH1gfzZ6IRe1Eb+JBr6MP8+MLLbQv9UWHMFmtdZvLABVgzlj+7sB Y2o6p75sXaSxvEtuaS3edEDL4/Q7Mi95AGJu+2iXFuwpH2SPQhNWjPEg21hXjCJtOftX0ZEDSxEl R+pSyKUHVkNf/dFjBQK/K4DizIO51Nppw4dTC/Mndj36pRZx+xEtLsAx9clpHl4POZccq0kAgbRe 83r7WHQdoHPerfZDOjFdQyo7RzWFlmAaT7HuWBFobJ96tWXgCiHonzu36eHpUzcYV0Pbh8afITBy sBO6rIqGXSkBpjLuQxtKI+Edtw2LJhSPHt7Jh9Ecn4oHNoShgPXNHGHEJQn+z5jHu9hWi93VxM0T 4/PiUAUyGrUgqKGKZdGvfj1HiuAaNRLi+T4Ub36bz2+MLs9PYZRo1au+UYAjIsZwAF4fZhmvMORu z9pIgfxaMxiWnLjj8/8Bpt9FlrTSlhThOpbQv5y5Y9RK2bPQGnsfVT9pYqYFMpcCyF6I2qomEx6v LiguClC670cHjCuWGAGrFZgEa4ixnrmBmXj2e2pjHxqgKJC0UvcrSBNiMY3jpd0m3IwoJTsWosNT oRaerEdwgxyjobmM0T0aKZIBGXbnVHrein2Idr8H9IEoinaAx0NbkNB8eqMkw1xkP17B4jmjML7L AoF1v1eG8aE9bNsWwZhZ3YBLEYEXAvcRxBm+IBxmp52ppgtdsKVCqhRIhXfV2bZFetZIcJAbAmnl EQfe+05Joh/JhsiQYrxJFKLk8ok2tTSaePKkcWW+j4ZPCiS4KyxQzzS93C4KitYfK87UY8lE+/P9 CHr/IPWIeXIXYqObQNV9gVDFGTTPAO5aJn7J04fV6CAseDtcvYrbiu28LozRWw0mg4tlnmkUr4og OPpnee5Y5Hq47Q8q4a+pYeWoEl1LRDX9MXZGmiehE5G7UF/kwcQjm35j7joXpSljyF/hBN27Vkci 2iSpFxpqmKzHotnp3e/gcnUjpkPaB759dzPLb+gLyKXAjYQjsPw1k5+xI8UN7epX6pTSCRjqHfyY rWrEye+QDULtVRuIZC11jf3K5lEkMgiGwT11vOMvSfgaH+V9q7YN+rVPs2IKBNbaohTFij8Oy0dm CP4FR0UYdylY1TAJZ0Qh1f68+M/u7idVGjtodO4GL23ncpU2LJTjje2l5Xmra/A29PiDAhXf0Q9L LJAD1YlL0bes8f5DqlnYAZrhQUbaAlSH9If3ZUwU4xmHAaYFmtlmNldooDgVSWrq1dqOUw+N8tK0 TTui9MKwZE0ZFG3/+8W0WtigEs38lvLpcepmSDQCHH42tvugV0dISmy+/vhoFN3iNETeVcHJojFJ hCtl5cnu9NYT0v/rq+7QMA2FtMByJemuNAAPdHqqfAGodSitGYsaIKL9WHEbs1Ax20EfSnRYENea KYDO9m8KOse36MSsK2ejmSoLXPuVUYPzAGkuDXatNiVdAoxWJpTjWUxYHxEvetWFJaS/bFWeAvRL ZO0Roq52vAwxWpkVMNy4oUkKsNSFI+O4if87Z7whTn71OGamxWYnvr3Q5jAceVOIiSxUvk4WMHHw EIntFi0QULAIeZuuq8K+JKUzEeEmcTMDOpj5jzNSM5ogqSG11J6E071R0WddtxfCyfDDRdYxC3lK ZRV2f8nAIVquzc7FVQmbp63N1PHe7RypfzrijkHxQHpgUdp2Yhr6riTH7PErnRLJhnDlinDPj1TC sR73BSnBwU+dm92P1jOYH36G2Z9LwAtlY2GpiBQois5wVLfCgFRPZemEK/DyV5p4jLywzRtrqj82 UNsAy2XiVG9pQNEf+3RxMdo4tfeWZjmkpPrTMU3JE4uss0T0L1URlPiVQsKiwooI0XdBkZjvB3Ln zmmeGkToYmiR+Bb5X3AmOeupbw0Z2sMe7d1Fsx02eNk1GKPla78217mMgBwSHxvivvDzHBKWBwuD v2egIj5Sqonsii8UlyqRYI45Km8UcE07uCE92edKRsUTtmX1Ni+3M/qnYwfUIiPrrZyIz9PXKnmh I0XRZp/MOO+Wzx5SyuCs/4SNkedKGV2HKV+lsygq1fCt+I2+dOVAmPOmxpSxEV6fU/+2AioNE8RS Ae5B44uwjz0QuO63bvrmkc58mVdhZAQw5279ayFKphIXGtFs30zqCfkRmrrsmNb648vk2EAMRXN2 49KUmUtysouxPACMbwJNRumESsQIzS1XjiugVgFPp/C6ThJHrz6GviSHE/7o44pxctR4udaIBOyo rulsGbyxyKN9iqbfRR9+3O6uU5hKEkkP+qLHXztQ5X/8S3Zmf2Lb6uNsJHNfzioZ8Re8aznqdmSC /QP0ID4Ienky7IZDQA6rfXR038pHhB70a70g45qwwo7AyTf88i22VpfgJ+J8FkKAn3hUMYeJPggZ Plelw/fDFY+WJdg7EqehFhYK2Oj2ohPlQferZZIp3EVPTcUI5NPO1TjklA2LMhxqgOHYpnLwPLUx H3K+EwW6lXBMfii8/6X5JdXD1VAoE0OFCxa7kR+TJSs8iAgN1goRHLTBFr8n0ziXNj511adbnnJk gFP+JOIuohw4TR4hLDDVXWbJOw33a7RaaBKA8AOtWYCI8JfYynTEA/EKJHzbCDeQO0p0SwnEeyxB CWTtDP8/wkquWhBEm0Pbvb3rCLy5D9dORQQlqvqnXmEuypkWayWDRgGAazT6kmu6Hp37KTVj5nou rRUBAebzoLKbps8OOS6494dnZgKn7JcdTFeIfx8dsVbdZEc+gPt0OLQPiXMr1RBFPTebJ1UCBo5J zFyZkOiLULD9mI9jlMlNvM6DzXwzYV0Iiv197gF04mLq3BJxCRZzdkJpWk02LpqAk7Iswb3lXfH8 KvPDIN5PAP9QN3muvye8NBNud4yZ5eQF5KE9hXfs/QjB9iQb/VGMqp1S2SG8PCG3kCT5p6Qc+OSK KKtlPwbytW67iW3eO+i5eLzM81KaeXvI+j3wSVizcqAn102MHqloNvE/NaESIjb5jt6JEGKDPiU/ SlE7toe1Fp0Axra0TGcW9HufP8/mNe9ji7B2ByHORWu0N45juScwZKlSgdMr19c/PlhMcY4qUcA3 viFtd8r9n/tPkw8QgriS/wNxomPh0lxdRAhrTKJYMj3wDe/cqJ0G3/RFAIW6ABtxLjZd3cFWB7zw J/zIsw8VVwRgxkBY4Ulyr1e7Zm+qsgUvaSRZhCMjELcEbIZZbPzvAqX5pKIgMmtz1+XqQ0cw7fwA bGu2H0I1NIG1kd+b7ETcOwD1t7RqLo5TaHuAKhUgw5IXaKnXNAV+IsoCSLMGgBrWbbVNM2mFjF6n wOWc4ZKnlX1Q8stHHcwtQ7TypROOmDAjooz59V1AKZusvRSYSMP+jd+ubop7JlfmO1xSgz3vm3Ar 4UC5X+i45UZx4BnWx7RTMtWWF3IR+UfM5aMDIbiSCxuNiLD2w+QNYYYmuqUtr2Oqgh6JI18EFQMz MEb1sX/bErmrssmVj6KbsLARxXZneIFY0T4R6LlHMyq9ERZ8WS4W+zbK3YvH7d/FggeaZUELBA0j xDukYj2waPgC9cBW4nwPaI9x/PyKoXxjJXY1S7/ATyi9McwRsrYGRK64YR2UtnB83BrtPMqhWG5M yFCOsk1FjIt53jhR9nbFSwv2KxySXQFvKzilMA6cYXWvY71OE8/9v0owbqw/m0VN65cNcRrSQBcz 6WBVkZzeCE7GfqoqsbKfdb+hKiT56yCgN0PoR55kkFD/5tDbzAeeQXPx0/S9R/KKFQJZlCZDYwOu DMT2LyLfpgZ0eJds2SchfK4ikj9znB+qRZLujsSBifTrk8e5B3YprajkF1yv59lf7n3rkKOTRudL fjbN5m9geUc3ldibPUvLDXM8+4C9hE7+PKah4/UIAH+x4ds2Sj5uGRSiXltA1hPr9BNAuAS/NSF1 nrGW+eRA37YLt5Q1hp0Dl6bKzM8YypYye3F7IRFBXR655g+Nv0EJxgOcW/8jEalKIpGXjAAIBWVP DO4Yi4LZFWLQo0W1gfmDzcRhD3x3C//3kijJdqf8FJ8Kd9bmW7ZoFkTajlnU2kli496glNB7CeQA O5MgAmMIRUTIiNN8qFxElbwfrZufobxgBPpkqNWJkRir+kVYThC2skVEeB03mMLlnqjsYP+rKnbq aaEDboG1WFRahB9hQNJ9LDRrCXG5fi4PAC76VpL7UKnRMJSd2xt2t6tQHeIi2pqs85Z0HbIATOxb jPxYXsWoomnxIWUJBO7vCXXvV7+oJQkCAOh6N9NilozJ5TNo9bBXVlDn2lQSlZ3QqZ/cZWqeUxC2 rB+6DwtYLsqzFaGshSzUTGnR3hPxANfd9ae/KSnUrXVBgrOVNsIlOjFPSPuv96T7vOMYT9mJS6o5 rH67aB/7TPsnw1b6qc+Gib8E9De6Gaq1u5EOgazc93xViUQO2rlhIcO/3vOmDmKvWZxZIo05fEAN ZpDNTS6y5hL8KmPdPEri6zg7hLZycpMEbQcHcL6Iusr8w+kM4kVOvW2nq91OV7B86fvoeo9oQbUk +ePyHJ1YnsCiyXcT1W00L3UeiHyjqfHM0CM0m5y2MJ1QJvnQPxeB2hTEhM2yKUjLnkfZfl7CnlU8 G4Dt064Jzjv0thvgrga4nDalHFH3WPsF7AcxzZPWu8h89do6UXXxbgZoIDH2L7oFpbH8YCAOwgZG BT/JJQkLt3uXczWqj/8qnr8exNLkKLQb5xf5H8Fieqtv3SMVH/PGYFSo9ToRf96TrmER8rZaPN+g gKPFCLicP4JzhXLLqUJoQL/A5OPAzhLtHc8T+MQWJZ1KApqfGUugRvsIVeweFLUqgTeQ40IrcxmW iJ4J3cLMJricAvUWiRgaoESbcCQ/yzfXIODxpbZP5BeG1c4ZOR8Gx6QwHJ7XoobGdDykk8aZ5C4h G/pweo571kf84sTxxMRJKTP6s9pwcYt4qGEyQqLR4i80NJAzxGq9W7fRPi1PTN4KyAhBi0SGaZL/ OOAYCurYeXUHDnJK8n/rQ9nYfiDvAQEZ2ZqBArqOEa79Rr0GitwXdWMBHLezGJ4FRB88xtwbPaCJ FRdDMilgDUXlUB0yj55zQgfKHJTVVEY08kvy0Q4gTlGsUsc72dSH9pHaTxkKsQpdHncLNgoLSx+n cmVQje5nTnhjB+bIF6W2PcNKUN7+wJMoaqsK+d5eDe5zFemGn7jJoCSOtY3gO6Z47x//bkw3tKK1 Or8Iff5aDTPM095H31aKw2JNeDwvNWv9W3xBXVygi8IM/jOiPEg6a3nL6jtSyEs1HRxlK7ocfZTv nRjIAwY86rNAt2NhdZtT5hABV0cAbGdaqerR7KT7ZQwT/gtguUUJNgAhO56AumERNKoi/Pxe9cNr vRLleU/i1wc0pvB3WmiIxVXvrxhriSTLdKcQYf4VcJihMeOGxtDqE1NvORTug/tc8wVL9L7RQXDO XX4dk8JjGy+TYjd4IIRS8pTFWwlaBM+ZkQy/hzKtcwfdLaJZg2R29C9SICULtpA1b5AIvse3kEPI h1wQQV9YNldTNmCS4oZpXb/L/XAHpSxRJJ+T4XG0DaPIhc0m8mzFhie6La9uK1ato1FvXYgh47A+ QZzI3rEvQLhLt8FJ0QeRP3BOuMGMgrbk8x+hNngKpSVclRYYQNUTXPxJd9tAzI5eD8IVNgL1k7jZ lPehxlX4fR06yuioWNrUr6WcrJ1IV2VaF6fBcGMY7lZLmhAo+Ohas3tSqcFGXetTYba2HjPdkPx6 nyAMe1ZoAtKYYJJW3NWb3nFBxX0uxtPrVyX2n1QhgLxOMsHErP675B8ezzjtVbtaAOirf05X/OpR MRFwDiywg0ixWaZn0zmqsXstbr/QjcnOeMVnhd0N3s/WGwzCBKR/mjy3RwN9e2qbMfgYPYmW7Epi N8T5BGpjxzi/Vl4PWSruPqckdaMaY5Y7cv6sRB1T5yaWls2uMYDPVDugVvpe7d20LL7pan1vvnfN fGOHl9YRWTkpMD+mzeDiZ9EhXUDgONVzQ6B1kOZpg10I6w84hGR+X165EsMM0mbLqpEAhVYpBa0w GzTcrrQpxfiAkrYLZsleJgo4kPX/qpOQETRu9a1ubzh1Su6HZvGL1CO01nTlBMmTMiTDY2ieXOMD Cm5QRhPe8KjA9d/jkIGECioUK/dVDIbKaek2iwr81qXHppZdvG4Z9unBQjHC/LdRp9TuQYoQj+sb h9hsjgY7rw89USVamuRkgf4w/aFq9PgeLibqeh6m+NMY1AO8EPqLLXNA2GYuAZ0bgoSWvqcAzon7 q/oADjN8PodLfCtk7Qcz0TPxeEG1OmakiWCa7aIJ8R9ITfcdKaDsY2dVsczLs8ce3GSHsK9/zCAa gA4KfvpaBuf1TZyDiiQiXWEK7KTRTf+93Aa/3JiF9TXUhwJc75hyz6TFAn73DlwEjv/y07I0nBrK kLOGY9z1Cm7TR0956ek4gK7/dubq+rD28mGHHklKjeUuvrap8nj18rwMJDtAFnlZ8/F8vZp7SxPe TKy4AJfuoWZydSyavWF6M72jwPA8gWqyoayUQeHsOCWIk83TvJRQ2Uv+NoCpmb8KeSd8wysjLS0S W5mzD9C0SmzDuTsmAMFA/GAUYJf7ra9H0VosZ2JLmjghtb2TLgPGspQW1WhfoAMr2WLV9i3ABrYC hEK6dAVxUgROxQjLNiWjGMdWvq4bfk9IaXfYBmXRs0cWzVB4oZS4rleat3aXYPfHn9VwXirRV56d qitq8ufcjoPwlux1MeVvld09EuZyvCMoQF0DBbPIY0AIgAqK2RBAhjbRmjwLitTSVPGuoGORzxPy SE+j/R0aPEGp6Rh+pqmXZ00zBEfc9iSYO9l83/2VGDoYnqTiZ5c4H/1cT1cya8dWVJHAwDb20Zku egYqUsqiCMziehY8V4rkRLDhqd3aDPiycpetftNatLWvXkxC6m89F8/DOwIkhBM8ykCU7pQrsfL2 zi7NyH+ApqSP+AAgcc6661cO7Ph2j8Hx73xLCpDY4Vb0F8CKsPppqGdLIp13QXoUEvvAkVL7vKPx T4IIFLp+PLpvLYpwgnSFDf7Yupukng8UTcCLs/CUThPl9cClXT937iVw8icXS4rHFsRksPmPNMQS X7LDoFoVkAxPw+2LhU4Wl6qzwSWMQtwYfMCnAud1HBkxP1neDJ20L5Nb/FzrISjB14IOna2N/rwI 47J2w9uUXxV7Swf9E8ybwLJEAxNaXqD4GAT0vrwun8HNPs7nP8kge6Z0uYJQy9uomLEnoC1ySKF+ E+rES6oB0cjS2ywnrXKZqn1bWjm5G3WoGDI/nr5BjGRjZCLOT/iVf/97XFk3ffEz/rEBDXnN5PKs /ZdVzlkYEUDfnUp4a5Jw5XvLATBOVmSJQYDdfW5urPZ/JJ4pG9s4lEgbNUfAeb27uwFingZ3Ge+3 or/bXZr8LSE7O9XLYEWoGeTz9L2iXZzKb48aGv1ZuG497RmJXYgy3yS0c3ptzgHp1U8ZLo668s0Z EpugBglteex4PozAUkNGQAzrGwvQ6MJqmKvjY984hNe+xiiAia6cJgZzAwqUNIIfB61JHapm1fay nzzipAHpHEhwi92e8+5PL255esr6XOs7VYk3K76+jKr2Uryh9gnl/HxzpOsK1m4DmDw4yunwbD45 tfIMstrve4Ki/MJcrzA3me39s4fp/hIpCzbtQpTKqPLy2YPnlhQxS+XjwEonssV49D7XxfKA40CF IcRu1heOvJKu/N4IAy5kk2tL1iziMrq55icBaYe1HZ3FxtoKTz/ScZe9+p/l2Ch3B+RqgRldXgBZ 7SDKaJxpgE8HLc1AvJdZBIY+cS81cNQgkSMzjq15yEfr6LIVvOEV54kt366zlbY5PG+7AyJQb26O ql5yJRXTmy7aS5VUmI4cmIrMyWvPepn1SuiA29xMHBKEzIWrLPPn9X5gHsSpi2KcXt48IHzUT3mW R/bIlnjpVzXyn7rojrkAfz5+BpTJdK1QmG3lRwhpht6hy6VowPIIf1duaNYc8mAlo/RXSOSucwM6 T6ry2CIiRH1GGMYu/gtcTyN5p9ivMZaLPW7K9vwsYDSyiyp7oLuWuWQGfwY7ZCSmPKmZ66n3yxf1 ZpVgu+ZF3OvX6yS/a8uVApKd1yMNb+IcJ6fAxL0RzDIzOrv2axSyfZL6YP7JDNRhzMGK74KWEUYB AtD+G17bDp6g57x0vo/zPMvAdCHzW+N7jP8ZuWefx5ULSr66WrLQZOq6eqve7It9edbPmrZi34cx vwzLWaB5/aVuVmlGQV3F4yRdkLIZsLbEXGFEO2NjHhxpPU9aSxeVYH/u1o4skBaOwD5dZ8XkTmSA Qv0S6jl43lTm7DYDzqo1PKUvrMui0Q0RgoDy4F7FzS748BtGvELvJSMl+F3IWDmERl97ybgM0aoh e01qONZ5S9UqKeQrVs4oaLK40RDHOmweDSPqzJ0yjVMpic5medQDEOd3tuNrlfW1pi4AhonCX2MQ rd7uRbThakzCwHuc2jqXAAA9/JNNdn8d2PoD2810Mov0o2GUz3hUpysoa/QyYPpjwT4QF6oQ0KPX komnERRwG+C4D8tifXEZM30tfaYoekN+eifK+3w7nNGiYjHjzds28PiF/ntOpYW+iKssKkTaTIsy TMsW4mSak+Y4PhgeqEKrB+MphIXuat9w5SmwW7A2Z9jC/hW8J8QOf+OY4rHB7X/6ui9iJPATgo6j V+sZ4T+oX88BJARVpnKhBIC0bUrKyErmU3Xc9Li7XK7y8U5DTPJWdAtdrYhJAIKrQQlTN2VQHbz5 8B0hIAP3pxLx1RIVk1q1J6EURHcJafQ07ywMOR1/D7J2Nc+8mCEW3mYADDH5YYnE4crOZkpHSmNv V0U0MQuI+0Fke1vRLhMC5aXgQYyl4VEgJnmTntTtwGCcIba0RdaBrI5qHwL5fKhgbwMoGYfwXcec z43ppTLq0APkquPll6iSu2t7ZSX+ivPwLYIUI9h45u4dOOREeWsosOwEnOlD66/Bm/4UlBgd0KX8 tGOLnYRS12Ced90ghZU0u0bXGV4AtuLF5Rqt7yPpNESagkx0MrFNdvbXLvPh2jJKHA8EKkTp3WC8 BM1ii/d+27x40oUa97viHV8tP1cefFWt7JEytlIt+nONdqgBVXIAmJlrZq5UMd0MeONqJioRAiEa RXSG1Uyc6NMOM94PRSBegIGF4DiJLUeAJBGmSDEzKXkNmtOfsopbUGi20FzzfDnbdanDzxjzs6Ox oyBDGcORVrdm8kve2/IX5o8QvippfFdh2qOJbBt/tttKlKSoWUq0ZsOHayX2z1Ob1d2ZESXOw3/g LDs79rumG9daHyNA2IyIdss0TxQqUfDD1ofCboEt4Gzs6LP2RS3qT2VGaCWYJAJeO84eQWX+c0/8 ZaYo+wsFU7lkre2zww1f1uGPbjtLuIpXW/YTpmESQPbhL4KBf1LRgwAUcwhzCDcYRk+WQe5GRlmL Mn9ImeWRuiWxV3LM3odvFcQ0Q32sU6lTSdlgQtSqh23fC4xLyyC7hDgL0gkQeZotsiUBcjrYbR0t jop4XcvbXSvFrw6Y8omm2QlF8xyoJxY814E0rUBheqNoM/IpzcV5nSTOnypRPULfJY0r2Iis2mAu /6mp8X5nx507ntT25I4FSZip2O21/bUGdJHK6DOm17qaRPnnqV+3IIfVjvPFhnrvnaS2T5EVQJOi 1j8/K2YlwFtBEp15pq+C5kUIjMxoOUlHNXy0RQ6gAoCCSyzcOzNosU37nyYz3PG+lxUEpEFSRBIx guoGFr2QlyoxjJrixOl4M8o+F6A4VUMhLuQeDGCBfg9VwuTDcHfadnofafrKMZEffRcRucMX1DAO C5RyHd6XyQ6Z1msZBybNUQmGEyxdahWbzc14Ruu46Wuh0InMHg46YksB79eXGDjznXeOrIQLfxYb Nw+xhvQSNf+Ne+pBxQDJu7vuUpXwqbmeY8Wn8hbiw6Bn7A6ERkOPfm0/oINyWhbKfkcqj7kCj8or fsX4hPP4hhXC2oqDkQ+gqgKhK5S7RhrRn5/NIy+You19ey444OzP1f9QnZjvz0ckmw9qgHn9oX/U +/AGpcR2u3Ug0t+7h0A25ybJ9xEnYuIlx/6kPnfXNQkt44Ye1k6xX2YKCjRHPAE4qkuIti8yvWxJ MSSkW25UtxzoR7mKt2ISN5sMbqtgVr+JR17DU7TxXeXehSyrLB3nO4pejnIDbsocHtMhAiGQGsrc pja0QrWXsryh1WNqfsCOj8bRCCNZRlKOUtxmdzzkLxJRCh4BmKY1Ue/IUb29Apn7KAj5CQKjpWPC +zR4IjG/0k5rqPnxo3Qr2M76Mfb09BmlKI4OR0AMwiMRbNuPdvgOXxO7zOyZdnZ6kx+5bf60tVX9 sMx6XTLot8qIdmrQga6kxjkQ24duWy62NkecsbiogYdCddxmUaTPOYXAkZBQZR+Tz6/oWSC1orPt ePizqgEtqhyjFU6TCEAAlDKJT1f1pldHhIjOq75nDZh8Ba10ydLte8sg17YRMqNk5Wf0S2DJ1hRc lzNNTciZX6NMbMKTNYa79eU4t8//fFSDgNuVDBz4dDMX8n9BXmHQ21aS+a1spN7UlZ42LoKrGywj X2NX/qq+jzn5o8/aAAmkEh8A2+Fk04aF2i22GUZyrCRmclwjzfDkI1NoJyAR/3SSp1WRNSe9bYcS wLZZr86vmjQ+S5YRvGL3Hv53nZ1LqIfhEfc4Sbkedtrs+E+tRGywF4gJF+Eb2dIqWCqhbCMTAG+V i3vL5ig7TMkubUUzZr4ZqGJLtbQBqf+D0O71gj2mKcaE+CZZgwRD6P9slytwqFGAM6idNvdqKJhD X0eELjDnO7/MTgI8DsVgsKqK5Wc/PsxHGPq+evnBojq88HtzRiahP0vTO4kbu6gJklJ6AjX0MZEX Y+//qG21hp7/RUz+uELs+mOIRJdBvfABAeBi3P+Ej7y3dviZ3KQ0MruNThAwfaBZ17ZpALVC3LU/ sY42ETUp0/R4TBuBa46/asyy9/DxppEszMVnL2im//5dYSp0OF5GSZS4Xs6D0D2KVL6SBdg1Va5f 4RVUyYKoaMD+kaWDcEoxsDEaeWutZWJPnHtVWkFYfxsE/a42UvOH27XjLj4mGwGiz+ow7ld+MJKQ P3hor0w4eUcK4gIKx8+CAA4LSiMniQoJcoQAdeivrhFl6xqfMVotL8SEYNLa+nKK+0oPJshQUz5d 4zCN8zfvsr39VkWr+yP4O78ZJShqkqqLS586pMUfQCvUgh4mr6ct62jmaH8dLkzzFDiAFg3NiKDc zpfiaX5JU1qz2qM43ivZiDyb4JchFWx6jNi3fKlB3iKfdVpZChsDYmyPYN38QmyGrdxtvDxGMv4W R/iN3ydNhC0wg+8O3+Tr7Yj2vMUh7zkuRvHfQJlBrj0q8x+VoMjvJsKKbW3MgbDMJQjCK6dioCVd ljaTAjdTZDxCrDwhswcBYOxevKngNak50x9FKP//00z8RZWXFpt3r6fFkfRFMsoh60kTe+7F2jLH uPJiSdrWaW4OlhayQaYpJvu62Vha/bOmueLLJinhe2wa1VlI+cUbg7AZ6pbdyI0avTz/1EzD8RT6 AZ3TfBPb5hNSiQ7XxIW+eVyUVTNP7UNU8JCf7uHnf4kdMs9I1I4aBibKtklOXva0V0/MfdkSGrhv 2oZMTFJc2/QHn6BNBmmPkOe5A8bZgXFZDiZU7Dld5F21TWB1SDvvRYiSz7Qxbh8lau6zvfMpiCp3 dLNig/gSZgoRLi/n1q3hfuIqatr/uri+dzuFRvGuXmkr1w+0AHqLQOSKwhuGzAP8Fzk3JFjNFrb7 H6v07PfAN10WBGuKoxK6OMppHC2HwZjb7TfR14DVnT4944q5dxgHg2KHaEhCiZQLyUTXP7XOhkIq CsFKSR1WQncQP+xpZbtVRWu3cWTCgZMNzfv23/a6ROfpDhOuzU8bcpQMKd/e2329tnn/p3VZBzxb uoECN+vMKSOtXtWNCvCWWlPmts1QWXmBEepfqyNDq8Iti7hY+TboJd72mc2YZEP+prEEjv6x4VRX VMvYraDCiqXi3X3ggqRr+oVey7ijIZQabc3/YQXquHos3l+EEKu6yuZ2FOyqJOpCjACluSxNaOiE 0uogLBRqFDbuhCGinhcnoTm9MbRza9hyxn2em7yxe9JaujBE6wX2nHK//YwOs+gemPKQNg+mZ88b vPFuoz6mwgcpEmcD1gm8CIje4stxhUK6XMgbo/K0HZNLaA6PQJPFRIppiZrHqieIVC5sIA16kPjF 4R0jtJuz98YH80oO1mhcAJddtolT3nvzIMxj0nBLRKwM5CTzT65y8LfV5IFQ+LuRPCHWLVJsat8t YVWJDFQNG6VHgCoDalcQbTGSZpE8n6+VktmMnwt0HmDxk5turvRtz0OQzcffjkLdc1uFh9Dto5bf omY6eN8L4xRaI9uTD+U8xqDJoHRXpTGI+AjGvtspwZFpmnXSrEOMTCOoIS4RLFzKRB9Basu1/5Ya q1YRb+a19Mz3jPUD/KWPPoaRP+Q2rVX/MaseA1Tmvl+mm0A4M6sISqCie4dMgk0qNenyDwhSXoaY SEWHrWvQ/6OCy5a0zyb0YmreBtglvDa16gccsNAySGbBAgeC/KYJY1n5WwmWU1UoWRMhwbbxn2Wt GEJOZSH2YV24jSOSMWilpNVhwZSkeXCQyxRgqIcZm/zIaAx4UYGMPm9zfdWP6bpVmxGUx92Tfqjy MrnAdas+vLLGNiAbnJFP2HBvVJHvKbTMBHZbF8vnoKuD6yBhh/YF8PFgyQ5xv3qqXPK3mqugGqOm gp/dOvmNWUJXCZRNwKyAL6M3dBItlFglUPVmcpDtW8bNF2ti1yJEqrn97IPxhizdqDcaHR79aKSi 5lIIDoaC1DkOYHltqAn9J1zpclH2SqL4cv/gltoqhFp8NBYb2oq4e1qDc1PV4+LnXCP1+RXNC6kV eHhiK7ZIYl7GrBYbT8gz3N5+dtDJ1EKaRQtxIishldrhC4taLzyhl/Ux5gA2g9tfS6TITkvm6kP9 kK0U23ABVUok/wfWW9u1tvb2Cxe9xDq7OIAweLHC/15VcnCF6iuq8L9HQSykd+Ak3cV6+e3/bsVA aTozahTwo7QC2/+jYT+ZCMeUEJ1yl0p5ZArvKbycWnHrWXsofIA3zLJbKw4t1QhwiNBOyJsRmKtM w/Zcitm4QNOx+DVn1k9UbbAG172lpXXsEewuYu9l0hWpiM303is7HaNklo7+2aijxRifdWJLrQ4l WhO7I4j7/U4UMpG9uDWWC2EbTSIGl0fzpAPBBrDczuHqZkbv4QgrAC8vfJkT5KHUm+K6v7P7+VPm lI/2g6U8SnBTKmPxEfcNWgP/73y52rw7pQTDuQ1sTJdPKxClGD0L86JMtGFL/8rwzmQzgYxAC3gj DGww0HrCGrAHob8Z09AVgPXv3ev/iku0qiZSXlWXTVxX1KSAdee1DwpFbLbJ3zHT3vdIclEM1A90 Ox3f36dlnlvLhHNQ+yZCHbmjK025gJGTRdlW8ytV3m1N4nCm748r1tMapBJ0x8PRGqWpgLJNEIXN p4fYH6ermkWaLNzbirkO9PT6Ks1UubEc+bUI8IR+8fcB4ZF6QYwHDeR6u7eMjbsRURe6+6O+E4lh kOv/Y/FfLrMyQB8tVGdfJWLn4rdibxNaP8BUWjy7NKyAVI5HTqGd8BW88IV6QlmHJgcQpB3V0zPC fjL+P0ZfzFvFP4k2hnytUniPfU0/eZNu6fCBGiupXPKh499DiXv1qo6PafoUVXg6z94Dx2YNHGF7 qp5VyPtArwfBGMngZBE5aAi8cqtOyHNU3hk6Fv1I8+5UU/L+qRhfiNqGc4XbSbquz8mMIggf8yo2 uxmRcGbxvulbYW/6b3iXbjHwe8Nz1mHMzGggIs8dNqfw8Ne6D2gMJAsPwHcz9FWJoR8oO51N1CTS 4DhotD90R7p+CwL097CDNH1Fh+jYi3h8u8S3FTgPL3DQgyjaMvWzyYPcb/9YKrmViWhNzPtjqakz ggcfNbDXuUln8KWDHT6Nlrwf5hogl1U5uR4hzK4/cjtNcFT7BBaRbh4vrD08SMddNxB9r6Y9MbtU 1Uf9XwDdWEylTCaMiHppFJ/YVtTVzsjXU1mNNbCYZmwmqQlsaZjLJoSvh8vI8zo5vTs1SEPgFohS v+RivEDpEVHJ1qy91PHyVsGpv0KifPI3IMtn5BRK0S9DOb60NAf36NwFuapi1H6TAn9OgUotslA+ 4Mpl8ZRkXyjViInz5fqCb9eSIZ2fVcAsm3+iZOAnPnGJc5A90YT8J3qNLl33pzMXccByXJc42DDz R/S4+fPd0QoNG8Yw02u8WGev/56yiz1bPadeFKZWtOqopwh3PFRFCG6w2pop89xpCdaEC42zdW29 yHNgxullW5fe6U/+Vw4/6WVJni+cmUvBPeDBhj7C1dSHzxsmPZqpbhAGmw7CiwIE73PhZ3lyibsr 9dVbvFDI3Xkns8nWfMjHvSCQC6YwlBlbuY0lMA0zOmoh5xqavMp8quygLKEo2P6GlcmfTXBCcIDN nxT/YOEs5BmJm0KMYJyxX7GBeUk7gKDsA6+rsVwKW8gYThuZBhzn/XE9aXlYvnBduL7kpFSnjNzO rcs2rTXmGP3OI3RDjJuyAGg+n1pBGnYC/P80CtxVc4FcxS4BWomFEqoQYhM66SCql0kunVhLNWk5 lII34fSls8cH50DSFvUsByeXR8YKCF+9ZlKgOfcZE2DRfjV+ErCZ54DzxR/NOHyX14OoVh91UKxz 93DIwngi0yPVjndZCJgiTub4Agkl7RFAv8ljyIy90/ZimemVtd/YSADQW6ep2C42dMYbQCNYaffU ueVjTSHPwqkfEat96FE00nv1EZybt2ifK8utqJbBTXZ175FFJg07Xf8ekGfVFKIX3VRKG1XGcv3B v0nHeJQGqJp+wvYPeZhCIihh7fbAzbqK2f6BSCwtmPjcXwgCTlRnIK1XnYJ1isXVa12dBAVbRIVq 3kZGv5efZ6Q27RczoKyjH1DeS6z4PVT+wNB5KtX/znMelwP+/Yk++EYrfxKwfMEOc3aOLuou2u61 hIurCQQqkVUX/io/1VPORvzi47sbYfFSRsytAxC7TZLihJMdcEoEzjJPiriqMbVdeJdHehEUAq0x LJYZ8lDFqUeciT7qCyUFeo8cMYADQnfUUctOlR16FmE5qjB8H12zm7xoWs88USeYcySbDCqLoQpV N9A68yOSGuewuwe1y0Acg1BG+Z4241D9wntg6dtaD48xkAIfsSTjhENHaWGFtd6iIhNGJK7ZL8NW WkBFyBTIaEWM1qI7/tXkLI6fzVxz23atdrNiB36Piwqta05lmuPB4gNE+ht0FM3ud9muF8T4xD+5 PWXcR4+08oovgu+03XQeuaG2o2UU+IWDRtX6Gh0n8emIUJq+DSFy93LkT6yPtM2qeA46NtAY287H tnOCr+5WvInAZQGirVACR/Xgl3nn+KugLZ4LaGD8xVUbXaSuBUckgaFbtSuWvJphGDIoQhlrVMAR KZ98AOmV/dH9M3vzL9HI6fla1MXmsjy2Vdy0fj/0z3tbNIwp2oHUXq0i5BNImAbDnC2JdDRocpN+ 9MvqW7+8fGQgqnZhT9KXlPStEjN6URQJ6tK2NBeUefUYidPFvXKv718o3tnJMt6Qgm9Pl1uCJ9ok 3KbJaJ06KKHdMGLCUR+0uRGSUsXcaPSJSn5uqHM0BLQkL1mbkKKqbCM8IhcK0c2A2aH3csIfq7u1 Q79I+QUEfmxO11BdYRzcq4IPY0h2iKjLVRY4puGIzCjzo9W/gw67uB54qsqqAjE9SuZb2tvR7v84 lmXxedw4i+0hMGcdkCJN8AZ7xkUruXgvAjK32jZoiCofgDR2cN/xWj6s8yY6mof2DltrDtlTTXo8 ECgxMCd3lIOt3E8QPPrvzeGQjxmitxsSY/h5GhZyFTfl22236bB8xgUtGNVTpk5ugfbeZLkEB5sv 793d4AVxXgw48XszGAIKrMb7cVKh+5uGqBF4PeQ5SzECbkohZmF19u6EA54wRBv18hdEgRsHkuzL AUeiYv5Tn58+ygXDXXcihhmbSEj5Xnbdk7rHrWF1nGxQIHFXQFM+NKjcJEs6qLUGeTMYmwDVsv8Q aOXcAfUyiOlxQn4U2o2qgrQUKAmssvyatn+wyyPAurOipEgdQ79NKAz2ncUgjo7W9c50fJ/vis+c /85tB2F7LWVUSl1GbCg/+YIgpeFhIBKEPk5rT2cI7L0O243MbUTh8rikBhFdQW3blZ/T9VEJ0fVy NEHXHWiIgmMDjkd0Scd1H8A/DR8XSZ6pt5spTtEA91m+FKlXJy/ukbFu/n49ZQgOt5IWQsywPoXy Nf8QD9NJXuRI1w/nBKO+ZbEEZzvjb19Mev+qgpO9MxNRNp4SwUHAf/nB37eODO0ljuxiorAn8ycR Eim+WNFJWxZJB1wyh4+N6+tdvp9OwWL7MuycLw0VQhyMBzcystmpPj8b70B210FTkNTDUT8ir/83 5eIgaQ9Hu5C83gWPfBMbzqK7AzvF3/9dSVohpaj/Yplmn0QiSxgw9X9ckNUg3o5w3hHnLTsAZmuf nkyJUTVdkdCN1a1En3G1KDU+Th6bL+/1rtdJBoAQy1/B8EMEeAbZvlyi+ImiV4incXstwFd89XSB Q7tmlwvJ6C3ex1l1pJdRoLB52J8UqqCrZ9xUwCX0zE1sTAee8FITwV/1/0uk9XUa47xhDpxd5s0J g5cF7WcrRLGejMex2zJm9X2fv9sYjXypK7CjyrbECiEBIcxBWYSqWaf0nmxZcbx+eoKC8h+m/Qrx ATnQ+etKnBKI5GDztCnQU9nrNpu1fthfYLB3wYdrVXO+5OJoKqzfncvglc+Afol9TF/4xdaDgTeX K6GuQvBxcgMPH471WRg/mmkEJ4ydr32Oqc3qsDxL4DbR50W40y3+YnUfK7JW6fI0bS5cKTAKP8F3 zqrAmAUvHQ1qAWzLcNYouyM9TwVJSTa1dHJsFhgioPHru7OX65CMrBlvSVY0dAHY0Brb0ZvRL87Z SQf4Ttu1ShYbWKwdFrfjrsXLIrY11u9n2Ot1Tk+yHWaUBzRRpvwG7fqTgMCITleim0YG3udQvVhg UbDqJHSkZD8QLeE911i5krNe6FK/qbscK6GuZM3FHOjR/rPWVwKK6QCwmE7uR+8KYRZmb55WqALI WCISpsHQaC7n9OqRHUg6WfNF6iuTtSjlhl8T1EP0jBcRPcfyfiiAMg6FGZa91XWSl0DTIwC0Zhc6 pn8qNZ9A9QqJSUVDV75RMJCJhhiHDIa5CcTmelypEmGisf3NVkpxBlaowkvSPAqrqRoJpbpz9EJN 5uU2nk/iYmsdyozgGXsyVID17qTcjF1CsOAZOQZZR08sLRXiLXH71Vtx76IzNwkKBRjYddY4/29S 85CqvFNqnmdxYqMM8utQ2sKhTIv3KtOP04gdnoUtrfXQOFDJHxoBZfsZwtZHj591A1tnynGkZi+j oeluRL9R9C2kRe2aGXZpB1TGtgaPhem5dcJfEFT8hcG8gNRlDgl6ndh+PchAbEQguQ69cqZQiq8d 6+MrYl0R7vrkTnM7rUM2JprAexzpqNnXpcs8P6GedkYCTcCG6lwuRlewOEVkCSHN878b7D6hCvKZ 8VnsPCX/yD758Wil3P4YumWZggQqOvCpMn/0PbuehLJQKTHw97CLwG5yG63PUuccjP8RLMvkhbgF GpX+5EThD5WlKcEa0+9Za4Ulb5Zu/iQlyMrdkJb32Ti4b5FshJyIKOMCEqROgBAYiK90Qf6FkxRC sOBlKgC7P+Ci/6NH7wvt6PEOfh3tsrdHXtsaLL4Mnzs7UtkNbziwJ/87kkuaNx6yepMkB0DFeA2e xQqKq24rNHGzhqsrtMQQ5nEPscY4VtFQS6nt0aoxPTnRCtj5yk/eIBpgqiqwyGdjDu1lxP7boKev UbFvfKjiNKQV/p+oL3Dw+Uonh9eYT/V6WWRcriRG6yYaJA8vOBQV3AxJ7XBBFuU6h5IyCkHiMz25 vdJa2b9A6mBy/YyY1hvfxDsuAkTtTbgBswkP4V9tnfBeH2826RBfraGkxVtNVVxy1ipzPg7VMx8G b1yi0GnyMGxeEGNNiZyvrdh5YPLbt2KX7w17nEOt0hFK7zCEwcBT9jFftjPe0AGjqf7B9J2wc1iS KkXurJvlzQxCCAZmDSfIDTrkjOlJw+Rqb0PwtFWWu6pN63/SiJpZSiYsTHfYhmd8EJWnOu4z2w8h 8qLk0CFs4MIMDTfhOVl8PxqlpBmq0Jehpam7w2vkGduAor5OurkIT1bBMUQcLA5GsLOvHJxgkViL sT0+6pvkJBlyIoJ+c9iyalUUqMZXdYi00MqX3HKOb+yPuPCyQxHq4yIAMWkduEECoTFMpA88YEtm iZR5+cf5rGmPY3fXJPgKVtohJhar6olYx4twOYMSBvLh3cNWFlTIGZRfv3/UuDLeL8/P0wYruLcP cyyhVKlWV9i0iojnes9UrtenI9iUvrUg3jpoAyc0yyM/1CPHYYp5NIOnc921sVb9iKkbecoAHuIL Llm9UN7fTyEAX5/dgPp3N317GHpTzKXr/8D5Lsb+CLjsbKOe4otaKjvJ8OgNxQnM06N7GOMFZHfY cU3c5tXnl7oz6gSbA38Fe3Muf6Ob/OX5zX2h/uuSxCzjwaX/Eq6/l0iP7KiH4lCbXMydU4UTfXuK Cr1Ucvyt3MQz80uV0+zcELg1SypmZ9azkZz/voL2rT9NhON3Hcl0gNdZhzRUHX8RKuKFDMgTpwB8 0GPPLLsUam2/3HDxH5G6JAJpXsYFY2tByF8b9DKaV+Oxgnjt69E6wbYnNBuJau8qWWTl3o/FF6aQ 7ZDNaoXSTedTQ5LB9E8CR1WT4Vaa6ix+NY0efNAIzpemDKxHowS0EYiMzYmNUOxtcXhMTBWCDmMp lhLyy+/XtVWuCm7yTlCauAwFiaEGUeyKbXPIjIN+jtUSpTyKUfL4SXqvu13VwNrqrJ/axCAoVYaX 5EIXD6mcwOjNTMfp5ke9olQ5NCdCN0VMaxr/F8dMN+rYpTC9CllT4Xp45IV+Pf35erlWhvAnm32V M8jj+f7yB+wfdbLHpXrkwoOpFccdLo7QtisqFxAKUz1XXZlCHb4RfKNJgZU0YlQkH4ie1kymE2+a vow6RIaInJXxXkjrtGBiJKVwsHJj9AeIwVlcUHfPEtcUQcVtYqbOoK7SLgqCEDKzM0rPt2Gg6p5i iJhifDCAG/HH7tHMv3Z1UuhFbO6kBccrsWdXuup9yUtl5Y46HX9FzzvUEK5vYWsIrTjNYwqVrIbW gyO4DCvM/7BwxQBrqkl5wMDexrgz42uLLn2uR6cQpRCBBaZdxaVEszDdV4SmzQMy+dMafGLELKoS Iq8u6ipooqHQFmTPbb0DHr2iUKqQs2bFqRqrqxN2nvSHhHcnJSWOtsTbNCoD+RCZ1OTNCBa5hndY VfxZA279yETgX2pKYbPs78LYalr81yI4k4cwiamQYzOTYR9iztWkm2rnFAuEtM8IHr4grIGJZ02t xvd4PSGcudDO/6OqawGC0+ebt2Hcl4rk97hJbQtnqfyAEA0QzF8mUiD2pMyJjrZ5IBUpLQbZqz5h 4h1nJqWxGZbMpBbBfuSu2xBvEkelz0SQLu7PauTehBbMlOQHto6BlHxrhFhzNNvTkq0DJFo2OhXt WyBSJgzLjC7oJFeviBb1sOC57y+OTdbG2bL5uXWxCOGPcFkHGjIEAOoO4RQn5KdC+/xu/ZoNLa6B 8DqAR1YqoG4Lg/R3PpZW3PBJs4tmQbyKYnvH13Bs4nxarECFZSfDmQDdrWBAKT7OxpSM6QKSVjj+ +h1dtwjuqrBYVdHvxBSoNMTwWrJgV2lIbM4CuqCohw65DCdtKRf3+slB653EBhi5VHKPEHdP4c9V Hz6fVxZ81CLYY+iJAmo6o8HQP4HfT5L+Mkztksg2pnNCB0hDTCN9mifmPw9Gpm642rUjA6q/MmtB G7jSK/b0mJL7dgY3F542fD4T5rDUl7kAdyZGU2HLfELVYtxCVzmYMN8I+L+87g2HZEEYl1x4R8Jg Sl7VTLryM7OzUweECqinORrIMmuITiZq1lxY51YowFxUasCnVaVIyefHhpz8brwWnz2PhKxfqCXU 3fAMusD8jHHPfrvNIfEEg9vmlghJ8PNiKRApD+9wykN2Jev3AWCipj6fgdWo0tg3LzIFYQ/+vU05 jd+iTNDkIN1l17mqEUOYPlDtJ5OS3Xa/AFYz0GBGPsQi8kVc2NcPVh0ucnNrq068GMCxj3CaGICb Ge8f7u7WsumYxnhlABbugMG11SmR/swvqd0OXEzJUIcGQnoUptUb4SFwjfE6qPSsfE4zaCuaKamV HmMhwjviPAcKkz509G7dYoXJB8yunv35331tj0/a1iR9SAm0SsJa2dfxQJRCZLsX5Sb5Uw30l4Lm xxz1kKWaV/t17GjSJdHA3LAITXgcA3jjg/Lhk2A+AdjZiThProKboXmnc9njia4WOXiDvpCweUj8 kmjelRQyvHuV+gdFAYVi8LuSyfd/GAsfERxYhvEKMwGSF/OHSJvNGA2Avki8k8XDsu4kzPRHR1WK VZhOw2st3FZ1nvnc/X/A7Sy5vF2dZqAB0ee9kZzfI2fBKZ2KdvwVXxrcrPTY8veMNnk7MUnsa0K+ lY7DK5iKqniIV5ppsO5d3gh5XL0wq/pZ+0w5kQxUzTVx1SsTdYV4CQxw6eUamv9QaAyEfEQy9XvE EOsfphPe09STiruLHbt/03I98uqK80HDcuj993x6H0v5e7sro5tE9SpCjgE8NhBlzcy/+bTxvCbO q0xhk6cryL7VncR+NXevS3fMvBeiKGOV1/X0Alm3oLktIYpJ2w7jR+2BKemlpg5D39YagIe75xr1 1/VVbPcOGjUanZLwBEjrzV3CpO3Duyb3KOhNH54HoeNpZPKnNoPf+dKxt0xuSvpZrFd/0XO0PvRq o0NDe7Xysc0PQomQ+mqyNf2gSaAs9fZjtck36KD87nZQFd/YWT6wrz/tknswK32gF0dpSIFakVhx 0BTZy8Xtf7uJ2yP20S7D4EGHnZlVM0Y3bepW3Lpu9dgToN5AO/RDUb6U3n5gqVY/TGsAAbYTkW2Y spGfQS7qZ2QymkcwwEVYqcZMM4nE3X2VFVRl3PiBhNetIFfg/9y7kDyXQOI+9ToZiWOiNrsD33Bk TEXzEO0TzB5sER/0NbEquwoaDUaohEqWn0jjWisGU+CMjYV/+Yvyarb0y19JNZmi7S9m39CFP/mT MT7vQR4ttAsjuTCcMWdG76RCTm7JoUoAtHq2b6EDmFb5Nh8KCEunjOQW3r/jjEl65dKKbkaH6HTc BFVPqzfIbAZB1U/99GiU9+tS7qhw88n28mdzqcCW8LrnPQqn5XoKvFo3iJ+k6a6tJvoKmJ4Mhceh Jg1M5ww72WkD6O7YWCjqc68/QpDajdHL0YzM6/zJ/qQ4o+p/X06b0SEnYccVItiR6qnDBEQMZ8aw F35EWj2Eq7nw0IVElEf8vP0PIp1L/ChxdoUIfIYmrUyc/DLC1WmPGoGkbud5QV+Ad5gh3YUgdL0x 4+2Hv3EFzD5NXpExWJSWhn1EodsayLJvZqkSI5RLBizWt83rUNyGTH6Yd1FTldJ1CHnDdTT7fo/x ZI4G0uIx4wD4bLiB24JPeijibA0mr+zK3ynEoKx9ZSqbka4ZEjQTp+3uuqUgWP78Axkin2QnwGUt cGx7mPv+ql5ZAEubWeUHYYsLA0i4wf+aXf4+0W8+d9eIZyf52E3Y0txvnM8Yrg78N0aEeYyz9ugX reGFRsHz7EBCIaNn+6CejkwJk0BiD1dhfTDE+Bm1nfGERAmCNwAUv7AGibJkrQqyBirGjyEDAR58 Hiuy3ODz282PA0S3q0//GPW9ME+eYLar/8J6uQe3B3Yl76lM7wLndwbIwuGKqT1AebszpFYa5GTa spbIGyk2kJyGv1X4OuM4B8C6VTmKJ8vSMbr5YQKiGjwz11yvR4/ATnWyIXDX4VX7eZkSLORa/2KJ axWDIwJZYh0E/7fn7wZJ0rpaY1QV7Id7aNOqKo6S27d8VsWU4BfdjC7yKb2uYZQRYJ8LDN+ZxcNE tedmUoaOr+K44sZ+snXTJGUjEE6ga9Mj7Q/Eyakou17/ltCsjWlaf2ImcLqI6ylukWRK/H0HhABQ jKUqJGIoJhqESJgmED7+HsOnrNniXmh1sC2TErz4/TA6K7/pW47aXoJe3NLw3XwwXFR1cLOfmbCs 0hh+9Hs8l4AOZOzRAIwdFrLE870nvUOPc4cxeUg0MddXIVe0fi5pKa7to1rgBuQt9EO42rAQhH2R 30Vu7TAynwPCyenfoBFfIaRkXphuiSPdKTMELiUChScv1s352O2vVDHfb+p1TbkBG7pmtSg8W8ng zyDi9rBIja8iuTk08JrwVRcj++Hy+KkvRbCSV2/FeaHrGEl3Ug/rzqckXR7It6hmL7DSUSJMDeBb VPFJVLNPMmjcQOTMVkNtn0OgPlU/K6jPtW/jMySgNPXMLeP19NVW3A0EqKaf4NBCarNbp2D6MihN PYcUSMfRg8EamNkId/FZTs3iKGfs1jXCtW9JNN2vb2W5vXUoTCONaq0bucgVbSEBjWZbzQA7wdcW UMjRGiiEqRIWG+ixVPXZbLSKEinVl7o0YiEs4uZ7WGfjTndQtnVO6jhaOOh4S3wSx9DJCeaDzt2y qxD7PUe63V4vqUs6q/OCMQ6gw3HORRSvTsVIeZocW6rrJTqpIdEr2Lh7LumWbCe62v33pW0WoMQn 7S360fPKr3YPwueWZEcThWKT7r2uZOKFGIeZwzhP6lcLhCY+QyVzphkKnqBNsCS9Z37Qg9UEifjZ x0Fy9lhYTAOB5xYV8FyXrq7n7Wq7nUF/LKCUD5A3XzXX5GcfD+kYwdkXS0d8+EGR++aBfLIyxC4D A6Iadf7XFoW61PiqqFDVfxI/iZ6PlAkSTbLIn3huv8zhi24EhLgJ9DV05MM/dHIguHc/0/jfVsoe ZFyNTGGGSmCgqdqkrLgKlHQ/7HB/Isf0e3I8gDgZgmq5r6yMdDOPdl9XVHOvPiRYXwGg65GtVJMw fzTuMI1rriUAdEy3H+32UZkoXOxrO2kBbyExYZHzjlLw0331Xm7tEoBTcUgluHTYn3khw1NIflHo fjmqF31MXMe7KZ0qMr8MGiYDJ/81TkixYp7Hg2FHUzBj+9cxOy7+ImGCQ8M1m15TNk6XDLS5j1DD Ew3O5FcVuaTXP0poDWNYawuVal2yoM5DD3Zgu5cN6WMRIJIur7k8sE6RkUQ1gkjdLArajGGGt+Sy vlm/dzCo+nWHjMactsLioXnr+eL5GUhpZkxmYw6xmI1ZTsNo+ShPVXhDDKox4vTAbttn0UpmdlwR gWCU/HTG4HzkmUVcDLXRUIyYa2s1Z86txKwbIcowj2abS9nI6BaZZaxwwVylSMgTYdlXKuZj0v+y cuPfQ8JV9k9vMCv34pMPi9YHuZG+lOr2WfBuYzJeRLfWvBs0TyHTZbmEnalye92nvPpK6aiiIvYY D9N+aCFRxLCNh1kJHaeab3sFDbcJxmAvqOuYj5KgHcsrDmePg7d1zKpF9M/YiEiNLP3aIlZHSjP5 Z/ATtmtnFqhFQCJRGv3fuA9sDbpFRTtY6zgreURcG49i9sZ17DIFI1RGDK+JoqtglLwT/BGVw+uh 3HXw743hjDnyKQA5Whx4qqfAK/I9EaPidsN3AWPZVLboNweWgn7SaRMyju0UB0t+nTCYNU0yFc3j 7flruMAZMgYjPXSHdpAxBHj0YT5da/yrr/jaCCZAE5+vbOoN1bPuDjT3RFkXC2g+dCx0XTySgrIE DEMDz6R8sC8jZveeS0o9QPKpLxW8f6xm9UTPmCFMv9My9PsQISIgqd3XHD7dEQe8Knpfk4WCZOZ3 2BBfMkGBwigNsyudeuu7irobf/+ItBvqVFpPXhgVluHZCJEklVecm0LhSAm7vJ3lEx49S8X2LLah ApdHrVqEwUaRbvBp0fxUCMUqz40e43p4Cz98OeIDqLG8cYq7HDTXYAxWseURWSrhIJSYtrg8DE9M BHXHwtSuQ63OdQ9xKETrb/AyfAEI5v5/7DXyFNVjE/85ycH4z20O4ovHrjiQEn3LOclUwTIz6mxv nHgHDK8tEJuY1Onndgtn9HH/buFVPBiFJoc6b8Cr7yqb2Oc/7KibURTAREZhXQ/Yydmk0qvhuGx2 dqiucxYrXtdIBBrXSkysLk1P+7UAcQuiYj3HlIqOqxg7Lh3xTSMWO7UXUWBEK9KgTyUgGNcdNsMX FRKJErDG3I8XORYUXv6Snvr10Ld7HJ0bm3PB0TymBnciWWeLXVS9yd3bfsM13WFqJlSsCP974vdm bdhOlQBXXC+mXGlKNmKXEVVSaJC/rE+EE+cKBodsTooqDQzUhXtSsDhXKyR8oeexhSHaY/CiDBdC LLutbN77Jv8WyhVD5iO/uG8p+JrE213M15Rn+PdqaKkBA+PYBKJRxIqcKnPcBCNEMaflZEgbQcFq InqkZy5J+xyeaT0NvRhgOlcpGtCj3oYh68XNdoalQmXXXTS2Fbs1RyKlAxCObPhPXyHm0r7iHzuC TwXR11kZ8o2Px7/zQ4DlFU7ME6OENHhn69rOuJ3cc8eTmtgfqzQ4G6P0YduMHw75uyUZxEuAZ0A2 E1Kn0qQ8Wbn2FxyBpZj2kgxaOL3vFJL8ei6w0OnfuvXapSV1UH0Ozm4h+Evs3Rdy7tCye8UVTo8W EsFVfbJHLTDSot6wmUnRGcNJh4j3YT2fsUWzB6V+fqrV3mTzs7/zJ55Uq4GQjNr1cPmK1CObMdPX OBK+Dk/7mjQVKCisMkYWL29Sp2vIbSvuyNf3xcm1JBqolMOuwbZprQAr5ct9MiU7nk1MzAnsOGtX 7b6Kzr7ZwGL3fa/TxoRfDguia3EFP2k8VF8QX3q42nT1SnfQ/G/YMqV0uGbfoNcF02OO4vE7ikkl BdqjSxIvZdwwWRjU5ycjdK8vYzuYbd68x+VihaKfacwONtmr+bhbIoId5Zh7I5AbUR46FxFM9Zs8 SuS7pPyanmsgokk1qkvoMz2U/38KhiiKKN6wo8BjWmvzZLn2RKiIyaF8OC71SYQAl9Hz7rYXMrVw ao9c+rWirvjcK39RPhoQ28peYJRu3Z4MzEqMI3USW89F6wUvscn0B6CEiA+KQWW2kX/hxpo+gF1Z hv0a0Gxh0piP6IsNz7OiKc4FG3hEYw/fEJBt8W+soJ5LSdbduorEjIuSnTMfoQ9nrJ89KiwfWWNh UeNYUKDXhquAJMjKp/NIiQ7p54TY44b3BcAuqXROIBnKtw5Xdw9sCqsR+OCK4NKMgjzMDlKOY1uI SCJhm/JJcc7bA+VidxbusBt1Jx7BMBE0YoSf8G0PmcNQIgDdb5on0/6npx90Hr2RlGAsenLjMZSX f9j+qE/2+UJeNT+sUqewRdf7UP3yQWBhPU+dJqlyfvbXH/r9x6CfgXjguOebgkiuE1XGq4tmHT5W 64BKD8ndBzqTwTl4UcUN01PnBrDrV9PkbzEhlQVb7gT0X3EN3tsipHYM+QseGq4jW6kAMtWppXrx n1qQyF0e9oKszb/OpT+C8XLdUzFSNrwNFAGrD9d+xVWeqiGmqgcL+ecjHFsXnszQolAKD2IZ2avo 4S0UsUImG7+25L2wqa7yW1SL87ELYxdvaEIYXBN2e2LfC0fwdjBh2p871ItOy3q5CvQMmF3iWJJo lntf5tRcK7j0UmwcPXrO7RP3tr9TbWAVDgJ8Hh3CiE4nIesJ8Lp8it/cxmpVWcb+vEU7sxTEDi9b bDC64zkggMA3Le05j7h8iCeTs8Zhu1SVQC0TfTpRnE5oE3R4ogMUk4hO/RvUS3eeJCm4FHCJLzfo jfypM/NY6OFqccWxOgpHCrFrMeSObsK7yO7STdGr5iE8RH/PgQlwd56v9qnqnVFB4DsJn/WrtI2V PMLCyP0UXs7XmaON5K4ht95UE17gUyT/MEXz+sS+T+zmk10eyRrF5yUJ0NdEWDKd1fu/5T0DHDk/ WPIKZKxTpufKSN/U6ntEBnzTFKdalTcYUSz3OL4D0/foLx4xl+A/pZMXuELhMNAKFt73tc3b15Po aKeJLRVa4B//Das1saTwnR/HdS24tdfDztJ3eKEKPWhZzQdsmMhIzB0lpJagWY5sF4K4dMtk6xP9 YCKxzKT+yFUv3zjVZXXXBqjm0BMeeNSqlI7hMC/ekqRkYUkPS75SVDoU6tlTQr6iBmOwZZUHthRd hSjGlGCuFRxLRZnSIBxlavOqG1/m27+18zb+lsCRo5QsRV9Q5cbyFdSXPwfl4L+EuTvtQ4cLzUqX 508hCPTbTovlNN+XohIrzrIZWjnMnnTPByb/dHoRxkgAOSfgdMjES54+bQ9TeUYb8FPKybndN9im Srbgmb4pBKM7m8NtTKXUddJ82l4BFuA5pD83ux9CI6htTLzKA4mibvoroHUcGnlq0aAdx/DEPwW0 X43nMYNrqUxV9AG4AYiWOotdYmbOnDE7C8EghSKVXlHSnqxIvpT6Lq5gemK/sC7F4ErI7yNAnxPI 9dHTrDmRFuBOL6A51t38pdda5gjXSiAbIQrKJMAeEWkRyN02PCleKgt8P91EG/sncMVE09Bi+lYC 0xeKLEihef+3bt+WkforaP8Ie/Omc+lOpNz0MBpcXYg37dBG9nYsfnuBY2dq5eyLgSdxiwU5x/Mn brdnvW1uKormMEWMohaj09yf2GJtg2MwBypsrjCqbilZc++bkujw+WSRK4u8U9aLEvNHW+IpFbBr 5XsKxgc/uG9OAEhtMGEINT1ht4aq9vKizOn8mm0oSlNWzmPPMLHly6Dul566ofAl83vya7tXbx1X ZVAv4jhpaPv4UWqAWa4ye41bvJGCmP9Q3TxCQpCNoh4WTmnfoETLTV94lcJq6CsFqeYnol6EZQ6c 2zIHeBVACx2jysKMxpTXvgVHL83HpM/zy4pFkqCWhxgPic0CqWYBO5z8iIVa1+1Xk0qHXfjy7Ryn HBQJZk++eoi3J+qdIPN0Ma8/p5aKq46DFOWobNc6wnpgoHdCr3zPM3C8S5q1s0IVDNH5ouk3ZTgA Wfqv6g4wtWQjyHNTJkWEch+7qIgxUF/cEmI7bKkdBYnQGLghI+PbqwWrt8o7dRiWSxyubkhDU9Tt wEBvFyT2Pfh0S3VSz5dFVPDrPOcW93DukLReA2cwOwCR6O6whaCsb+M30e1YnsJY9A6LhlYzeVVL GkcCtrk0h5nkGyv/4pl9McqqCkZdX9DPX0hlDof3RW96jA60n+xwlS21joZXuNoH7l4MBeC8tCVe BtGvq2DF54Tof+oF6QH0vFNY0J5kSStFBk69zlclqAg+kzL8QrFZqkaM4Tks9qnbmaUwTunzYKm3 6XIeWo50FS9Aa1yJ4Hl637bSu7a7VibQsUZms6DLGyKyXfngdl4cCAXcyeK7XA59kt8TRZmFpRwK GzojakOEaUdC5Iq8CoxyOHR/aAlCUazJ/JULd+RFbCGMkeCk9/lQ0oY7WAc8HJch76DqxfEe81dl GblXDD5vw2DKvUuqImbEeNFulKYfjn9K/TwrqZdo8d/3C2EF7WX4Amvw4Ncu9g7yKLq2RpJNAhqG Hl5Tue0WNQ37XDaGzCYrjuoDm64eCagoklNBGC6chP7Zs9zNHqAOaQybjFgoYjroMYAFiIVR1FvR I5SsF8fEfw6pri133qTgsuhOxV9x8pG/Q07NzCraKbKAG+3XPsdgdpZd7x1GuYrVXzBDZxmBI4JL O1zD3QLyKyTdtldjywDSVFrJGpGLs9/RmU/yCBecSfUyfOfOGrT9ofzNjGZ5QWf7mpDd5RT4ghwv WTg6ybhUXwXsbokdcI4RncPXU77I4Dyc9AkIMOyngDvURUzulR1YElC65RRQj2ecs22TuN8NLCdr BYA/24NDcSNalzjjuxHXB8SWqtJY4MoYqNFgI76+WHVlZ+yE1Au6BuXVC3/syhDuxxIZ6Hc7SmKv Q3Ktj0ztZagfVstmmx8763cZ7I90aVpBZKorJzIQcEbyMcMg5FWHaIeLwnCDptQywJnSSzK8VLEU UOEGkENKEZXY3cm49HRnAw3jhztb8vnpCVIxL7etRM03BseR8huc/IVL4XHW2SAWv/MK8MuTWf3Y FAThTH7Fng5e2uXmQdhT+0r0mCm5udlqqOStWxpFGYk2AH4l1gnWHjluJTfxeZWUPvG44hiMbBaf ngngbSbWrF7IDcOV1tVBL4aZAK/YrejNz0bHLwlTw8IobOQFcbqgXFUqIs6RSHLDpcukw2dRN54D y0XmI8Nv+u6Rj66PsS3cYvSYN+4W77Y8p7r3anpRXcFlG1teXc7yYh1S8Q6Bvxip+hmoMAxyDrtz FffHUf/SgqXP+Q7Js2QP08EBlzjdxxhv7FG0O6qgrsckhj/tm1Z86azKNKKz3c7QoQJzR/e/rCeE XBwH/fD1qVi521QOOmctyX99K/05xwlmRs8x+4vc4XHFR63nvlbZDZTxEQD1aS3/UgR9R2wue3ls dEKShR1fFgQbS/jBxBOjbJOBGiLxZ1FjhPZlsRF4KVluER4TEOh+SO9i/zEB1wPbcXrB9fNzzfXM 2wkMDb6r5XQyvTg7jD2e2hzPDH6XiOwhjD0CCpHq5vM+rQ9RvAQE/kcpG411nvbxZoav8vnLcR8r HG0wNUBt9tp8Lz9fme2PWi7WWvqtt9IVlweR1C0UUCsx0bQCaosno2doE8wXovaop4AHFLkwPkNR yZ30bj/DdNZ/QfuvEqJ8VTabCPh2eXDlaodPHH5m3pbwXeq9ebgajeXOotsNqy3VRqupBtqA3z+1 KMR85Lq+jgo4cio3IuDF2aGbMQXn0UFEJ/HyhqcIUK1usQn7y+ztk0iMp6f8WqPKWdr2hnFmaPYB G9BLKJMrGsMwNzNLah9hMgccoUPXsaMzwhO8QI9SuTCee/HlHQcXnCXJGvUOGJrghhHv+El5ygQS Q0/Dym7ZSvUZz+mITV6xZ/BgOIca16/RSUC4Ujc0pFHcoy7dTXRyWS6Yqb+3ZlKX2XK1J5khDYJQ LOzh2KcFN4DiPeA68ft+289yfGCx3EXKa6CJxK2e2qrZ29A6a+hr8x8znqYZUpEE62GkZu+Zjtu/ /8jzXy7CYBT2r4T+yK7b8DFP5uoSSwbuzF81K+DLcu6nlQAmDsK0JDNJRMfxZSmzxt+lYxDJzgp9 I5D1tLGD/PEQW43SNbjzSyATcV5Ue7z+QtVY+bba9EaC6ZKiDDIEU//Pq+38tPqmsdUU7+s+g0Pd xo+eDjsTAmYmf5J0mDHQjTbrR6+tDQf6AwLWENhOwAo8LBMRrykyg5y5muxo4pIwxNs1g5pS0pjV rw2iPJzaUAfLqOXQ1DRAPg9dppsM1pJ5oe1DFDz2e+VuAVMQLix7zVDjlXAIulkDDeSkNydLIYXT I+6HCOkgiCPMLh1FVgm9dtlNS9DdpSMUrORtcCiGN9iLnQM/46VkvDDeANwHjuZvun54fK5ii2Ae PBkQEJ0UZGK/eg/QcfobHSBhIwfvuoAKE/gmXmAKmujGH8wafh4/jXnQT0tlvEDoUYtDhvJXThPd P367Uq8NONO3IwW8TqitfXyrzDlIDQpbs7lySBJGsp+tbuRilFZgFyZLNJWNuBRvHyFh1j1hN1yC QkKQSv2Rvh+M9tylrSkXDTp2nyfmfMgEnjguMztGmJc2XEw2jZy7rPBR8mpwlJ9Tmee2ZaSENNKd CTZdFbwGk7w+BGOYC05xc9HtDhBJ1DMqmHVlsqWKRxxlOrXN8MoWMX5bMAfz8qYu5NnDDqslS0EO c8EmP3m0Uo8o7tW9D3RKVq+RHSwFz2NkvH6dGWT51sKqg4PjVNOeSaMgB1WdOLSFpSOz0o4q9rrx 8UdpY1q2BJkb52oQ5nV+fq9qsz7+DILIXoRNWxPIIpHwo12pVGSHEKhmIZATGKrzefM8q7wwYi8W iH7Qm7MxHb5YMpNXKSm0HmrRc4gmJi2Dp49PnwemU9C3brW4zZO+FzFNHIAS1rTnp8AH/DiQw1dN /nsmVg7dN27He4Kqqp8ixd7yTqanTXyyAQ4cZGMA7j7bm3vfnFlmdZnhe6VrYdv6FJPvEDv2hGCr k7qCfvOMAMNW12JdT70veINAAS6pkZSSkUqga3VjxiNFDFz0lP0LdqN9p6JNm1dBoWu5L0Tdd4wA 0POU7e200fnkh7nNZwO5MoUvLQ3d/iQ4VR68lDxO3/dO04Hi2oQWLw3Tdsnbf+aK9D/Nbi4o1wvz 10AmBfdK/RCywU3pgW9dRzPFqZH4P5i2Z1cmFxKXzlCpThi7kmkbKcAOknaY4FA5nxBJKsxI0Sl0 krcPz2k98kG/+agpDyeaXnM6wia6ybmnwlMdF/C35mx9j37bRfYqVrFrYgjl1L1FboueELFiVfUQ Dxv5q/EKBliQhnyUBYynaMI0U6i4t/MnL6pvDV3Gocz/lVPpn3C2wNXpBRSfiSt21/fPF2bSTNLH bEsE1VmRFc0Py1aDzxLk7vC3Oqqjp9QqTPfF70FO3RFhpPqlKTrdWaLd3zdMG1Zraj2+jLd4Wyge b5vURwSuJFf8x/k3tBu5AGehNADKt3nRpIvjDXBzpDfQtTldN6BmDLbQq/1aT52MALgq51DT44nE ieUVKPAsO2szsfdnJPKJ6NPAzyvEnIIX46gLdfGnnL8C9br/FtzHzkPBT1d1ps0DJptlznQrirIG nrQSH04iqHNeAuDK+nRVfdXsQxV6k4Kd9hQNa6oJlfOeh0vl9CPcaqQAue9qgjImhUureUNnn5Yk Gpf5EVuq6iZjkyyn3fQx7NmDsQ1/9gf4NKNybbdakhQzPTNM6erDmCWDGEuXxCOMzyoLyqksCe8W eGNfBUnNl6Lr24NyzPqohel5cUAooi1YAJHHE+EuPhhbZQZopXy0iKSE7hSNT4d5yM5y1SIjgyrK RHnAkU+K42S1AWqHym1xDpJz57mkJ1ttII7/nuf8SsWHCf31tEEZUkdgXmkLEO92AI6eo8SicPZP YNO9kVI/OGzHZgQMrf7EKF7TbuC0ZopYqjCy00teoZ6RNv1L+qVFjdflyC3YBVdQjBuweOT0qRXJ 0xwWwyVQGKRYrcmeygAkPgKZxaeAc0+UzDvEcyKPtoGxply4I1Tpk13f5q0MM9K63etfZ4qymocS zX28aL+KBFr7nB7xh7XHDtWQyzg9x0MCdAsMdqLODazULVAW8jy0g2K0qZ5ktfu6cF1Bafo/N+/3 p/hVhhiOfnrT/nwef48ewPdLPa52MfU8btd9HyQn5QdAPKwB6mO8J1OXx5aXVBGM1coIf3Iv4bM/ 3mABacPJakSfU0CPbgxD1gCvg54FgF1hev1DtSe0o72jba2C8Witqu0f7TxfRXFj6s1fDUPGgH5M Q1D0cfXNtnP7kqIKGjrFLUFlAPySfMJMQENqigZF0qzJhgYsI+389+M7/pKTgw0/p31TEx/Z8opq PGWFpEffVGvqH5WZhacCkiafy4XsXDeO3sNmHmzubLJwOMzeojlEAHMfQLGxyPbwf7l3ijSHjxpy mIe/tmzsHK3/kD9pBPwOsqJOOZqdVM8twSzp95h4k0YYlOkV175mrZcYN81gChYFhqInyC3hnc28 HhcO+68VbRdaPx2UCOW2V3HWxMSQbgevWpsTVA133aNUw8w32teVpwBZZhGhWW/GgN/Eq08bzwHm WOdFBX8DAgeCpQx+4tdRB8nHauO9QB22fITULuzwauG3OVH/I6QW2/DtR0w4L0tl5G5NQ166B2WO tWsVa+w4bMPftVuIppcibmCCuGqChZPBu4Vj/K8f18oP0EOMubHybqTDSCZT86PDRR96ugcVXmcz zw+5kag3jIfgpr9ENZ/QgyBa6ApsW1VAd/0r8B+Km0B4hs5HEN3fK+wXvpZYmuwZWwQJq8OkiluW KPL0b/hv2ol+P7xImRwwJ0qFG3Fv2jv5ONFIHVvl0nezDvGnyPjuxSuNqhonALwHjZ6cWA9mHCsz cJ32s6mInaliSCWgWzeSOIft5tHibpbxuYUgfb/yI/h4h9RrPfDz6xdGigv8H8fl+6K6k7k1uezg u5x3b10obl8l3FWjhpsNsk1jWqwsL+1Cq4HohaKTMbM1YDY9PSXZ1o21hyj2xdu+hhGohlRqUqmw 8PVmlqVWpsutg3MK0s2jLoPjoVSZxqinlepuoKTRLb8xDcSa8jWyxh7Mz7Hf4T3LocSml/Tl/hy6 7uilRzXegSEqmmokPSQhv5ki4uEaJOPyhECF/aCfjIyVxt3m7lCQguVUlsYoFDiZhVWQ/jj5iUEP uFjtcS/mRJ9ZjgIZ+DbvF4J1LIQUm1YOKgyDyghx5vwrBvZ6KRiQefkWSGc2jt5dDcAnd/uxkBua 7vjdE9FNFDGNWIZgoYI7EIsxqb5tzD6x/B1pTuNjsHWN+r62B1CwfOWNTWSMGqs2Dw3gLv0B6Wj0 iTPCn4APyUbgN6dW45zUG8Ac+0OEwvF3QpUvJvM0Z/xbN2n9BvxKNGFFoh3Fm9VHcWFj4pHsmzgH 37Up8nBxn34JBU4KpcQkkUpdhmxeC+enMT5a4H0wU5+uZ+bt+KE/kRmh7bfNZzvjcpAtbGgiWsvq k34LOZlYyg1vvs4CDZFm2PG7oax4qwFCJbuweR0gpDu67qs5yrHHK1sI9K1r2XjgVGxERDs+bL7q gZKH4g8oMlk0wKVQ+NtqxA2VkMxCJtzOxREoCgE4qv+msNZ/+B1aFvDwKzp+k3xx/910Z8eScWmb j/DNkzPGUD9evEODa7r8h0v6xwuBT4Vc4YCoZp24TNrOBfEBR0Qg5A48mjmO54i0cN+8Cun9jV8w a+L/lqiWWMK25WcHyomP24URWk7kHCd6JRQzN/mRNYPTauQWON/pYTKFy9nZ3mep09kZVkDEvpYo rkUqH0k+y1TyJKk5RQn7MMl16Ary2z9gb9uR7fQ6j25zZQQ5gctq71OHp5FaLRAAxdEDS7Dem8mD f2mx1z33IZwVseaW39DA1UYfvD1134wC2nUoFY5NWGr8BjCXDWa7lCsdcrt0q+KamWqxAWgapzoc jyi/NyR3h+eUesNMo5nxfnK49GUrUx0NxBNHe97prF5Mpx3rM5qtbLOTlF9YaAVOJoCChYqlkrZM csrNrK56JwbX0XhIgP1WzPY+T+3d8sbH78ybh+Rn5+GQHvj1gyBTHycKJm6tLTq9EaWB6YmX2iVN CyRhslvywtEJJTFnzV7IrpOemLfxMrB71g0oCXjftYaTTYggObXgoOuqRjSV4i40xlBJA/Lb2XFm kNRe0aO97DP+tx0exJ4X8lsXZp/Q4BtUaZkai1hWYp37sFJBYoZE4n13vCEIcOdyoXny6x/h4IV+ 4TWQoQNMEVmaNqA1aWMsiYMLPG/h2vrx/x7+p/mEX39V51aLuF+lI4yhW4bLYYOPI/qnpTF5FR+3 qnV1c+FnCo+4uhHlYuCrMOer+LDteexy3CWimMOpSLPOsFkPh5cXLS3DBEXDtDaTDQTEt96SxCqj R4NTHd3OWVfSKbgBQNDLFCQIjpmmpe3QyrVkmOx0yGQbwt22fKZ+wG7c/BQ0WKq3OuvqXlDYFVyW 9YsX7tUd/yIlBIdto+QifWBaBvpW7wXBOrzmCaLaNlqA+7BFFrLNOFgL629gyu2LKf06cZBDKDqG LgISdX1dzfSDv+iLAZbCwPyvovzUtVEoXEhj3slNUaram8iKKdFq3POOTu/IyHv39I4Rkw42Eid5 fU3afHlZlk/nFBrJZQBIOqERppQ7L2txWeEDHYHnhvpY6COxhi6+KDVnMeM15KHASddaLzGBe/Ez 2br2kLjr7NblxwVtghoyEML7fcge+CkVa4wispp/yTq1iHtUI5HSvSHVbOttqzhDhnOiLOvdOXEf cFp7VIiJetRFa4cbLr8kstF9152IL1ETyEe1Bei3/OiiZW9iKE03tOLMKAW6TC2PLbuVvwflVwNF iY8t6c47RkIYVLNH/PsEveDENqKa23k+qkgm9nr2E86CzUuLi3CrWntltQJKvJzBcCnSU8EfpHbe cw9r0EXtWDqQrmDTX2phtGqL3/xbNxDNLnKYi8zv++hsXF2O769Szjs+XnehKE09faKpdELNTXtG yk8+C3ot9821d029kTnicp2nPU7Lwj5gfr8dSs3zU4XTtQYLSIjuanhxvfWxOnx/R7/z6b/9VsK7 8Fj05NhlDMk2Z8LyqiLlUi92By7qlXeQOi4WezJph+bMu4X2Ptt3gv7Czp8ZxbJVo/4VZLUpK5p4 A6LbDDLfVjCJI/of1VlOaKlqFpzLb5OU83ZkdYilSkvRq+vwD+rsEwOOYFcD135gNS/t93k6+jcA YSCDOTA2loyQy+Gq/mdh8kL0I5XW5bmf5FPWGv2POYYBaKv83RZmPV84xclvpc0HRJm2ZJKKtoub 8Vr61N9HT8YwViA63zlmyq5GoHWoVZI0DCQkz8MrnVBWvRuFe4U4/PbgHD7djuwxBOCAlLoMYULx E0IkgTn+ruwOZwFDWxaa4ATE7sL8XCW3Rj3F0XcilF3weNMA8JYAZqB7aJjf5An0X4SdT2F3q3nd CLTY/1G14+KE6sNR2TkmYGE8oJIMWpIgX940lh3Axpwc5XpaMQxxpSxZ8bMAyJJG7LCq/2BzTGqn PP7boGTcfmiWWF8Rxv1sGs9luSe2rmqU2bv0Nx7wpO9GDu5L89gA7tfBzDKesk5hc8mUdBgw63eT rmvtd7GrIQ7z3wZe4ug9YScFm0z2Df4sVb9Nkkob1wcdt/sXoH8tIE369WW4OK/um0WDgvtXKABo 5ATXFL4Zi3kpBOuFhAm3LABDT79MNP276SAKkr6ug1rcwCViks0w4YbACcd7JSJ2WQWxEMe6CtLH 91tlPrzR5P0v4m25DJsXmBHGVWEUeFacQr95FA5BGmtoTPcwt21n2rm7Mj/cOXT3b7EZDWzgJFN4 gQLoDxHZrgq/I+2J3jEA2i/9kRre+fC3T4YQcfLFpn9B8HNA0NOVLPtDidH2Ba/ElYGV88h5UygU x8Gs6Mk1iD7e0zE7eIiwLtbwoKbaD6pBrGxDKIifyvSuyrOFYDJx+ZRnAhRqNZ60YVfZcFw46wZa zJJhCR4tiKSLEbw99mO1nKjNIFp/JFjEvEXuVjm662WlcyrArzzdFGan7lMwbttGnWdSD9WaC0mP lYrmSjdgh5eK/eFQ9HIHRGRv9A4SwEs5TNekWooBG0cUrJgJ6Og7zcjyrQH/L6te034RA16rSYh1 beLZ/Um9C8LuYyjOcXZUjib4NW4ljrubUfVKePHe4aIKVVKbDKegsJDkCfitBxRk4rAObbUOjSgb unRs3nDGRPGOuyPc2GU86V1JC2Zqm5q5PoAnaapM+5tQwLscXpy60SanT8KNVWZavfuN8BztYdJZ muDYlEYv8bIS68FKp92YuWU2A1aPcbydmV8zAe9aBhTy0fUBcmUTE5+nXjALmzTnNhNM0MvT3bpe B6OlDQVxI9gvzJRGc16GweVUuKVcCykHVcwZ+ijHQOKSsU8rn749orzF7wCP7FlBA2UOfxjz6WYz LZKJU5Jdb/saubtpQvE2pY2OONskYR3BxyqnT57Th8IuuN9JIjTulUYHIAE4RE69QEiqlrjWH65h GF76Q99TMxJycGulnDbuKVyXVRYFaGr1gPyuf0GripSQiMrEr55n4rV4kod+3v+Qp5jK4yBuh4UK 14DNlUXXMBZE8smwgJdrvwdOlIbglMzRbnijKmJsy6sLL10CyvVd7FkibAgZKFlAs4Vl8oEDYguw UAZLIJJ4d1VZoNMAfaUY4hU3HDIJpnRwIJCk0ROPhs5ip57gk/H24up3t1klh3kWhyeXA+hS5b7g JcEj7GnACzDCVgRQerwpfVeI6ghAQruMOGNW4KfJmejCcmRzpG3No9gXWExqzfOKssS9VotFpHh4 bAXzyqCHa1Em1wgrZUFzw99rfwreGaWM3txgxUwNpXuKdl8NKgyY7z9zTgjGel4zmWzehNUFc94T kOgGGE0XfJ9AJbrOmBlUnvAkUUnTST0b3tnEqcV8GUWntnwKUXjG8VtxIy3y70EB8XQllfgqawkg evvPIHsDSIBoZvSjht4c7+E9u1jwOe6EVEIAButM+6fz5BYpj47bi0aGqajo8hpFFnJ2KClkc20B XES5XSREeL7lWvwg/rf804I9ZqxseMFE9USBv21AkxeUj1ZQ1yoD7DfMG/n03Uvlext+BitkfOwb TsTEfK3zVM2tSh+WUxo/smbmPj5VTmT8nWIevamuADiM7wR9zxDptHC9JfzgmdtadOHjuD/GiZml rZMDAgbvG2oin0wxvU+NHz9LCauCbhxwvil5NZlGyhClD95wCn5+ILZqGvReU87zLEEfSH8gYFwd qRDimYxOyg6SmUlH2MXoQgYPpWOUAKCjjiiQr5lM1THJr8VGwdWD1zGKfU+JKBQsE8a59DL/glTd gpwezucXNZ6cK1Fwv+NYLWmiM18Bo2dXeFSoENVpv9fu6qtvW8KlXxd6BcV75pIaxVKaAoZjoemS +oxsu5cZqqlEisCB/BSgcGPqcf0dIVm44RzNQjxeTUq/UYg2gqYLF6KaTFuyBG1BJoNdskNndNgX k0muBcwGF5Ie7zCweDKYLhZtFS+h+gb8AJLEsZny2GcGcPz0x1113fAIJTZ5Ni7nv8O70vgxQE+N Yp433I8vQi55w82WSHSvo9XhEF2I5JNP7kktc4d74OdM7WF6ZP0X0GcZjDppl9dQjEePkJcSy7Df 4183/KuXwmvmInnTpsohtYiTtHKZ+EHLPy00mvG5yFp9vFIJQnblYoeK/t3qgcdwcCWgs96j1z/s ClnWl14mnpi8dJs0KZtSX+zUJn/SPXOAIQX0pMhv9BZbD811sUQOMQdvuUPu2JjEq4zq8F9ik82S B3TSXGxd89JBMdediqMGZeOkhIpzZ3GPdfULDVf15TY0Mz25AlDnv93IFptTjzKZKPvQN4YuMUBA /f3YmxAbewbfePTwVF7lY3/1Xr9mJmtl95C0eHMIPmHWGtAsYxq4UgFQjw6NhBe8g/Ba5i5cwHWy 6td2jycTnzNDpQu82vWEFsP9xECQM1D0jcJRanAOEiwgy+29VHCByZoqNisRFcPxWeCW88hV5ciO XoXHma4FfvMFdngDCZ7X5TmkQ2zQNd/r83nPvZnHDPlos9CL/2EWS75mSd+Fg5gfzq/34+EdWlXr V7AyGRl3KWRPXsuHoxuWeZ2E0Prw3qPq/1ioTRuiLYoO62rXslyrx1AC+9zHyNd1SZzvk3jbJVeH YzYeyjBTvGjw2SZHayY3qJUvq5KotvsGfTRW+1G6wCBUvee4qbI3X/DjdzVXL1vereq9egNkzkZd y+ceVhxstRkmS4Aia0+lBwxGfSbCGkVgIeDOv/L2I2R7Aa2i9H8N7MoSrbvT/84C5sz6vRP9nAcL 7pRZQG5xEFVwxuWH8InnFJSnLcOzzD1LpTtkVoMY5+eOA/pbmQnvg5ZNtUb4wNrjVSX3FQdZ4gpK 5hYDH69nqJA95m6uRrncYqelya2rMqJmL5IqEOI4vKn01sfz1fwAasWhmNoud1rH5k/8vBH4hVdq h6KcAhG642bQwFRBKRkHA4z+lNp5q8txfjSda40lpju8qzrQ0xfmqQ0uFpnU9BSpbqcFoulzhgEU aCJyXvZLa9Btua5p2G461UjHRZG6gWrWoTdNZahRlRjJVWITZpEnriqNvmzRvYWysRc/Uzk5eGN7 +oI8EOr6RaH7XXoFOdKK5j4RJGS0WTNbsWHBZYSU1fV5Oc4yPKRYf4IgpOPRYw6Fjtrhe+AWp9D9 V6uNjp1tn9mL3Ujutcb9CVvDWy47lWrlky+Q0rIBpnGEG909wQlgeVtdw63iMUjz3WlsLLnVXEWf La9WtQ0Q2mdC3Lyoyxosoj7wrnOM1cRzfMIlN+r1FzzCkgczEaWw9hVnbPYPn526QDhz4YEtxqL0 mhdwgbcxmrf3DXqpKLxnbA5JBO6RGjKQ2H8WpyXge/wQV/yHARfLgu6pwM7/N9a5aBkLSn8eIf44 lEpb71NgLwSa3mp49bK8YBNIfijQcQJs/mk9eF63TkwIf6LuOUQIF7qOEzNB3z1QOcUXamYMWiZH OtGGEp7xmYaL3MSE8QhdSKtu8bhYTNtVeZEBFdG+63Asqg6KWDIDjs1jX53MGFUFN5RY2bRhdTYl oxvpORAmYVa82F4joYGti58pMu7SWGQyF5mOA3ucwjDqYZ3mfJgHQuKC4O4/+MOcFv7rLGixYmlz bWy4mmg+76mk6QFeYzEFitIHcGirxLvwdc6rq30A6YkZOzPzlSi43d7JodNVhP191KNl3uylC0jk 8HwzhlWW/2HTmobsvpn5j32QVZ5n9zs+N7iH7KAY9SkurrooM4YDgS/eIBJoXb9JWih4xtTWwTn4 S/6A7SNnOBD2cPpMONsnGg3OkK2+fedbq9YIIlHjLdzd75FBq4bdVMqmj2hBaS87l2IndbdxqQSa FKtmu9TQFPOlRatDoAEJiSMU7yUn/I/91AqQEDphtZ2O6itbMAcF8FFBbBHcEI/e4u1+urcxiMEy cUUdZAaey7VBeEWIYZ8aKxRjh6cyOcM4dBjtG3AoB7M66YeTuGRKd8T9QL+8hosyQkVLNaRputr7 Am1LBvh1unMT9vJhmf7wwVXAh41mkXFPeIWIQKBLu+08yxT3ap4O1FvT9nTlIMKBO7WyfgD7PMJj pIKaTFx26e7P+wdQN58WCtNTvEoeInznt8TI37JVl6Kcd/tX4HrHozT+VTGAqKYVd3qXgBzAJh3s p6+IrOuQ9yttE3PNcRpOtdUEcX96OR5tIp9DsVlHQocW+naH0QNCxxyzssuAaxymR/XPq3UAgGb/ HNB91G76IUQz2oM+7MBaKjj1jLUhVdrazE0frhCLlamO/IqpMDfJRIfg06vIedFGwVLLZg7oTbXB 45eVKInsGNPw2AOI4Dquyg5S8XPxwjhqPuiIGC+BUbH8n2vfVWxHR9eYvNZGbHROd8ViVAweqJoo SO3TovVqQZTAw2cguQ4OoGkRNGsvr2XFfDeiFK6x8axBADixEFFB3XTFwEm163A6e170y6YbfLY7 mhcpqNLCLFwvtfb4q5KqYqJOMcUBIEgch/GwNheh8fYdYC2e1uSvuCzjpe8ARY68ifunm4DcDSMo FAO8hmo09QuHGaGQ0jDgfWzM8ZUME7AdjVrR3b3IrzFZwyy/YfAPO7qntmwdqutnFGSJ6DWtqc7i H6jOOa/cp+/d85cN7bIMpQjttw5zbN1no+p2u0GEnDHDNUZTaKO9rsDjH4kYwqSEMGVSZcy+aPJe F77o06O7MtB2XOAHDzoyn9YmsHvM+qYTL0f6YD+trYyGuFRN0eZnZFaJLUiQYwC+tnC6NXhIeztD jRddU11l7GGQ2Ch0FJbUG/BL2fSfCGpJS7JFxZ2vQsguXT+WVTXQzXt8mDPeSNNEaHOJYH69awgV ey02NYPtYyzM6kP7c/aOCB8Z6jmyxtsJck9CbIMlQSG3C+x5+NSzV7CyHqIY8QazbvFlOvlKEr5/ Guuqh/r0N5DCwEHRQFM5GaB1BwISrLwdj9Z+y474z2H9wQOj767E5fh/+Kx73nj/vKbnvrAxNmpn wdSHdeNIsPxg69VOEmeKm4aFtXAJJgZDKEYRRGsjsykhbr1qa7a4qijmhUKvXVKnDsf93BHJzRAv wIM/u6516KTmVT6Cwj8dpLm4UvCeUT586yojgUax1ArG2eg/27ycvyYZ7xXHCDHDDBjyegSZRpHD kqvr+NH0VJbbSH+M3CGIfw6XvL1A2eHLUDSSZhhfjrmKjsf59g3jZFu9vNAmRRi0i88kfrKitMgE kS/10f0jbgxFL2wP2C0xF1G0EsYbaDGziPuoBGZZf/MfZmiRzZFU88ncF21uoKEgHMCAGfAM2SJh WjuKbtsXw/9L8KNZoEVIftt/jN60lQwOk8exQWxv3VxXjomeCf/3vb6Qrrt0cmxQ9F8N86rF/JkM KPa2XlMmwg5MQGTwM7Z0uGgCncRrvMqy4S6vHaj2ZeRFD0lEBaKx2hOGe1PeBlqzqICjcelAwAD6 ZIbEZ7izw6085CYaQVzn3NFEHiG3Ot+LM7nhxY+0f6+78J3j5RZBATq/J4+ogEPKOw5VqXoSuGn3 MMFNNqau3nCSCyPtS4Z82YPjexs6Uu59kzFF3HDZADJKFaHrDD8BCe7VROVTtU0H0ZP2KKRPQttt Wp+BvmfKZIBgY8lwxvS/pljVk2Az4jLIGQe0pbfZ/5GT6TLx4plp+etiFn2WSy9AS8f/rDO60A8f Nn9+MTxldq6c6TrFe22E4chwWR3fT+1nxvcEBDKADtwI3b2aME3dOshpnICMfG4/dpWcvimNmQQ8 ZEdVeOqkO+hDgIbwlBCOuMHQwh4YiNzHNAdHcRCzJRGW0hHZYD9dharC6MeI5ffL7RRcQE3n2i3v FTkhpSh7DZoIYzUGW6zP0/XwHw+lzLxfZHGHffTuoDBxVKYclhyROf+rgPIvhbIWZR+/inF2l79Q OHlQNCZftheLXrQpX24BL/Xs38uh4clZlkocXF3tRHCWz6UIbNzN5CjVdndknKM/rNCuHcH7CFm3 owFkWXm930RXR4SGXvsqMMxHTNgoKHi1oozl1Q+YIzy9E/enq+J8NGOkJr+d5si5Diql5deAgVG7 c9RDIbVNUSB4CsM1XZJuBq49wu9g09B2z8Z4W7e5UN4IZi9j84w7NtO6zVn/KMIDlj90Rmdj7Dfj I/2c6yTV6xTf32TzlUhNJ7isLExigSV3HlQ3PU5/tvannbO3XPGfMqJwe+nOpauc1woZxnNJ0B4/ 64niCb0i63k3/mfWfjhup9ZLjacdt3DIbbpstGUZcHiu3Y7oH8yYoXo/khDjn3Nxb+jN/1hlbhBq O/1K7ZLJSLuLBZFWPRZbGksmZ8MvY708NvQUROSLdIGz+OZnsztngw2DPyL4kZEwW7s5e83HK9bC D8N4D2sLv1x3MSeWQVXrYHVIO5STr7eqmN6SU/h4VVK17Hs9VNf0DLWZX1k3DwCC5RdZ52gt9YG3 gcJW1E4hfOOtfYaTfIWOBtpV71ZLQiiAPEK8OEWq0wqkR1ExlKfLpkNIi/0n3luvAmYYw8BQNd37 U7KHgCE0WtNkJcgLT6hcIhKS6fJlL9uArgt/trI2zuqsoHX8+soRqtfWuMN5zzUDENsHLSiSeA+D /7K6ho6fC/X1dKkjpAB+KnC4IEOKwU+C4G1u73D0lwZ4pyZKxDX7LGZWJrSF91odlw1HtdLL4i8h pVdlzUG47VGvFNGIaO8tAoDtkng816MjzMb51ti53HB29u2wB7Ajrw2hVH/AdfGaDFrGQklA0GST 9xAJYXiX1jng/3pBelvZggesnaI9p8NjwCOjw0zUAOfpIN7+S3vIZPVFTZyipI6eWedymxHbpbk3 zcrW+kcpUvL5Xm2UE0ChgJRbvG/eJDnBU7x9T3uUSdihGhBco0g/4zEWs1oDLmw1l+Hu5ywNW+xI QK8n2tYtdGAjPBEY6Nx+Zv5WfOTCVMzJfdW48t5K+55bdI2igfgNoRb542jD7EN1ZAx/oBofnE5P KEZU/bON4CR0VDHTGLaaeIjsXl3j/tsAlK5aCcg/FtssN/JO6aya0qcR43ya0r8NlnXPkdFEe1RZ Q/QY/ZWNShOfwp4yj1lx7/de+wM+C0xou1f3/1ZJYxHdskGn7fDfz0H9RaAT4LEJ7AHx/4vAv80J IWkYviho+cKebimt6wv8Kaq/6TsAgZGK/hwjzAVviFYCmT8OkbYWpgjjYZxVFdyHcwlJLNdVTd/w KbiWY0t8dBVGEGTbp2CFNMu9FBaaK3wQhjdgMVI135RcLywiCljR9CbnzyY2kMovhJKdI+8tBV9y WpMzMUuciWILwfDqr+mFc6X6u26VukUT2L07oWPl2DwSsnUIjiyCuvLNIz0xKbOraInVWAXC49xN WxIkQMXBXFn7BfmT9QeU6fjvE+Cg37KPB5ZJ7lzz27sT09UkPS/NK5E/z1Ym5ZZMJ+cy/vPUvUHq Joraei+di+8LEKh9ks0Qty1BJDsD16SR3izJFDwpO8NwD6P94Snc74qIcHqV2as30l4DowzuIQMr aRnoM3Mtwn2hHHWXhbOn0rFLPJIiJ/iZ8c4Z7TMh7ENA1VnUkrirmjItugnqWNZGxLj9pXjKQYET TxgB2kR/3PrZZni+QYrfHfU7bxZiVwssCiRRBJMKShxtBT9h3TmhjBCVr7UbEh9D5AQ3a6aCQzNX zOa6JJSIWz1mj+7wIY9Tp8HLOu29OJBYz5iLsHah8U6AAfXG8jZxBYIUKX2aFHWI811FF4DAP8bp eKkeC5PyTfBNf2aK0be0qV9vVXex1OZFRzfLMZPLj0KjwPS/IeTLuEUqrNRQh/l+aqy79x+/lqG3 NXE8fKwHZytQzVR1OK7VI+2SmuOschBV1wBSBS8yvIPCrQ5WVybkDcuZCIxLwhRe1bAAvJwtEIzb tzI/QKKpwD+R9hQD15inUenF5pyF7zxDFrRX8BKRGXEoZeddo8fQNYBigZIu8GmxqWDJICow8o5L IVoTeI4ZuQEUL7KIbgqR7BxFN7dBVJN4P8BBYwA2yl9kRwBk6nulNo9nzGPAA+Am2F+3Fcncdnwh fH/OwYebPR9SCpxN/NTVEcBCcUOqpZ5zwKCuHYJ4E5x14OjpYlDxjroKEmRWE5KXyjwlUCjTJy+l 4lAWKSoYG3gJHuQmIa91+hemB++FP/p7OmMnL1h5WAhI7iL4I+BCSTJHlkZtUKNVqKLF+uGt2We1 ymcm6VIDwNN7UVBsm7xKIMtQ68DBzF7ZNI4WKp6O9XEjSbRzVDSuZTV+I0QOd/n3GVeWJtzyFvyl a7789x9ICc2RVNtkoDrRBnnb8tksWHIJnF4kKILm4xvSlKXo5JY2Ms382t8U6Jjx4GykVsSeMt2U PGKDF1Rp1df+vu4qakFNzIia7Kp4vEcmP7W64MFkcoenu1vvWNoT/GlEPnL8NpFNKJ2JAAjuoV80 Z6XC481fKW63IBi7m6uuegdAHogvvifsPVwuHdjkivyZXjVSMSkKT4EowsaeJEnFUmS9YJQE6I0Z u4pVdpY8dT1e+gVvVpIBuZps4BYNizQATh5VLiPYJJrccFrWtxk7mehsBt/AIfKK0kR1CilxvtIQ po75O4K1Hp/qlBICycRCldeKsE4jkDbVmI9jPGrTcSI67h89mCXbiz/f0bCfQzzp863azemZEVky yeEJOmlmhNd9rYOiYpHL9WzGTDIU1Sqo8KD7FnSvVsYU8utQYC2cL2yjuJ1B/qlvvPltBRSIRy6N I7vBBxwdSHmszucIQh2HvIzvqrkMhVWWof4oPKS5GjxXjURTz4Nu+FYru2YtL9BPjVyuoE6ouBOQ pV+TEYB6hLK02gHSSONOgWFgzZcDnlAIR+ni1M3BgpyYpjxt6nXrIeZiVhqMKxM5qJt6E7OovATW Gpdw0/HOGxus4mk3Cv7h4L0Zo5dHRwdFm+G9LJrLJQnYzeR8hETmODBR/AvkRTiEetin6Ojp3Gpc zNUewVOnqjOYIKM3bEbL6gJLKuT0dLuCqpeQ1NcxmrMId76ef2cY8B7j/nhvKjde0fxLTQElVGOw zmuz6JJgZd6g1x5PJXSFTKuO5UnhAjZeScvtu46p9FxUa2Tw2XBGwtzp6c72vi8P8TMwYDcliDvN Qhahj/yAr915nAuusNEoLg6s6a9+odahypwEDQRamheBrqmO3t709z0u8pjssNDGh81RD6+gP+sF TXzOoLLx9ZWQJcWVlMbOUW5Gst8HA9SBY851baRhYI2UGyTUHOsSimRxVupDbRMuBy60l0OP36gk WbaL3U0rC+jWq4pQAPFuFOgfHZeNXNtCa8D1tlKoLtYwrOAufUnpVYbZt0H/RTUS88yGDpzspKU0 P5C0OcN0tN6P3mXEsrv6viSpfEjMjgpDKoMNDaBmIZa6X8idB9rNtCSIUDumKDHTkYYfQ3ft+HQ+ TMg1o7kTYEaXkFGmQ5hiwX7Y0VoXUsOsaBjF4QXXIeRaiU+N62kgAhMl2ijU+KiL4ylO0irqu5a7 PwCDpj2NTjZtwCQch8KN/Ub+qGiSGNMmWv4u1RvjVYilwV6ttqbfBKMynbsxfJ2IzvXDeRp2B3+N JMgnusTjebuA58IKCvzFMx+Zffl4sk7ZBCKPzE/j4mps70VS10DISgVzH/I5aEOgyWDLwmDpQVN7 7PBQj2DqG3JsixvNvfPHNUrwYkvBH9nup3kY15rmNaFRcUBCzNAyHgjnUw+KfxtDZyXEujngWB7r lYJFON6IxCEpStKbrv4Q1Yv8pM6U3NNbZAmc+iuzOdws6u4Cb50ssmIi5NtyLbs5fkWkvLDZkU9G u9pMZ4w2jZFJGBHmKEw9OABxS8ia7DzyFu28YclrZqTgo3PVayIJQLGx9OhTG36QrbhxTOSdxdw6 2BrQPS9SZwlnmEf9sHmkwPYJe4fRVEp9rhZjra5rS35IlVbbygy/6YND6jXdzuqKwSP8AyI3rNYq 64kvkvCFB9hv3TB6cPmp/Q9v6PFELULDVyR+Q/5dJtkTBXoE/XMAqF2ADqHpPlCfl6BEpxbfHEHX 6BYnCvzsHg8VSKhUD7cHvLlwXtskdq0IPdijQzkI5B0HViTEbLZ/BtAUAxAFbAeAUdUn2dq1Hms7 3GI5dI/vcXwITWXRc2egu05r3GtThbFBVpqtzreAB5noeqRCTv0hOFJSU0MbI1360StaJpMgxqND XeJonDtfTRhk8I/d0QcRWDKyr65jxTbHyolKgDexqZmA9X5prHlRW/iEAotNab8RQDdb2kOoLV+t HZIVabIFDpnDygTo9EiijSUYstaSmt4W2WWB6Ld51U6aJF0vRL3AsOWxwfvec1F67LYQG8sy1Fy/ CfSEaY157YUIc2AbQTxg0BeVxgey3oNbA1MSYF7V3jCLk3Oyo2aiRwQj9mN5kQNCQ9uch3BF+4ay +CGoCCAYpGaJNdUlwrvBnaztD1Pr66XZ9bPxS28jf9dhm508RgdsL3L2eF/zvZY/qVLGQ7de9+Yh YMB05TGVGwiu01YUN4DBJ9MWq3ytp9VA7wPuyCOHlLlF5e2BJKCm00p2QxVWFQgMOnJmmijit42R VV1KcN83xnT7r+Bz7UhdWvGIE0lvdkuUILn53sIsyZZMspNKy9V2GIRbKSAsJEjEXIzxuUTa/dEl QljB4OePG4eMl/d24a5Q8LyZafS/81jISQ02avCRVTCFsoQ95moHsL4vR+YibmCovjHL15KCwtMi oldkWPMMYAXh/25Vt2HBJae8ejc4B65BbwHoui9pJdP+nLxm50YvwcrCuUj40WqTRB/vIP6dlIzU rU64G0KCoelnJKVvyMBXz9QL5SE571PIFj5KhGzoNGhSChvYyNBGDRYRXWGw3jBKXz0VdVyrTwOG wPwNOqFF34U+TSEG+nZl5KBByV8RlPC1F/W0u60PKyT/AcxHOQR6iXF9FOTH8Fb2oj3RwtrliRUu EFxxW42NUylL1iavjOT/v2yUz2AUC1p+UbVtRYc10WDhqhapNjP5eBExsaZVSetBCM9gpIk+oNi9 axZ6wlxPQuSgYBitARFfrZsRc7Tdl0pmcjTdPc0vupEvQErO+v4EcCDatfnqZGObkCKf87FenNgM +jGak03NJDuAzPHged5w9Njpt/TnlzaJnXKInIdqQyUsd8A50Ev0ZwJn8XN/p+76RBvCQGYBKDNm hXMT2/+rDDrmKHpv90Oc9r8GkWC12RZMmw+e9J6UV56fhBbQOyUJOmT/h822Ds9krWFXHPBRWPv/ 6CAxrSXPYit+Mfi2frZTrqcVPXzYxHzxkii2ZUX0VXUouFRIhEFWkX5CVbJgSyZTxcFihqcF/r9Q rFA+pQccYqroe52wbu9o2bO+GmYw8G8zUpaMbZbWJ4f8Sn7ZSsq6eHO1Lq1FLgDnytUlvacEseO9 8unRuqCnGiZb2AZjrk2ul/KJE+96054K3Tmbke1f+3PELbgjwqP5bOaET8kJLSRVwIUm6Mm3mhvN /+WXtLp7qXa2Fn6GjARHnZIkTm2hovQZizFftaB/tuZaBM7+mbqmcU1WlMJBfDL3QlFpYrlrrY3d mc7yLkNpxWSthkG9jgDzqcYooj3EXBaXFQe//lhBSqssHv4McfunSlncxOuEHhwrPJQxRsF19TW9 hRAYCbBtkIEwm5suWfevIwBNqUMwrwaYRC9EG2ISSWyRNDErpX0bNaaRUzN4bfvIOxRaDcJKA3NH G0q/mUTKfe9sHieNntacsID6fOuDlascmVEAjdJOC2Io2Btp3Pmt5D7WD/Kbm/TWPYd4p2CLAAQk qS/fB+8KrN562fKh6f6BdsVWZp00fzyJ4ZRkk9j40odirMSGlUC1E7KUOkRhttVozsEWsu5Q/tcC U8+HUFhlUuzU4UyM7iz+EhS/2tyxAoFH1ttDyhMeJAuyhVKyYTR0bIp9n1qf1a6s3lLyYxbnG/9P 2ygT6WOgp1ZY1mUNd4xDQ7wJILqK2oyIC5qEZ8ymNx9klccUvNimRY2cIIMicr8nG7qGe6jdoeSt mHGiXYUoc3xi6n1PMhQAxmYG1lmv1ATBzngS9mM991d9SHxCLb1AEKyD/edTMaZI8KL9tWtTvZZj iR8xwAYTYp0h7s6z6qLjCq/zBEEhn+8qLrMVYcgP3qv1xlge9ztA7amZse10kJSB+Sougc5nPKAG 0AhgczuZ7R9mX/HmkxDUhq+xnqN2oR+RkrV3UY4WynrSwWsz+Q+MS5tBjSlfvUBlqXPut6mJZBx7 X3c+/hxSKHYQKeGAc44jXT1cZtWmx77N9AC/PDjoc3avPp8Aj+k46l2Y0aMJlw4HMrJ9VDfJCOjP OwldHkOD9wY16ojqn1cHa8F4QwiVHmHEDK8xDvrwmQkFnlgXImwO4XNgOKU2Jv6hl7F5qVmMGqxU pgXaakZeFeCBM2T7bHX76PunlvvBBFf0lQ9lp53jBp7t3h7EI5ju7irCMMJyHZapE7chxJLqzi2V KEjliuqEIRNE4x3ViqTl+krQgYpDtTTxH6FHdjXhq+5e9spP+kmCw1Y4RyqQ/GyrUvx8G8D6+gHy uqWrnPkqv2btEIP7mdbFWjFvtK7cI3RsFtQ33sVCSfVO6ldAb2XRKVjr02g4VkEhSLj5lP3+sF1t ikGtgFX3/glXgWalnClvwSgVARWBRJOqSu0mQIodP5sa9LF3ATzaptGW4VM84BaxFEbfm9f6Ybvr K7zeDzQ84y8b++WlvmZY12lvCDxSusIsGHipp7dPvBlGrG6BIWvrmX1KIn5wZfdifAJQF8uq/gnw H8YI0zdwpNUvGZ28cvT+cL8b9sGtv60n440WUK0+N+MzUvPtUI6A4Z7wtN3wBOn1Cmq2vfChiSZt ncMoM7e6JGYVXXB32kM0YzmKGnaGM8NlzHu7hJZ1CAjZJTygYAjbdlbHKmmgdKB8PcNqq48+ltZb V8Px9Pm29Rv4MFLTH2eUF03C68rGVmvTZo1MVUDcbCS22HKxDEOZFpZfTkgnk2VFyOZbxTmAkTtr wrY/Cm+JdtcohS7JDuOaV/g4nGvX76khEVm6OZ+7hL/7H6jbG1RvjKKnlp+7YudFZraa4EnbFYzi LHo0LBtlhdG4nRBr9LIJBN/CZQpFv/5j8lxfoYPzmOdpJX1X8oOxjn3rokVR4DKNa7gbPBmgcnSl zbaVt4NeEwH8rfQXexPlt9yLUgzgO9dYeE/Gt2POdaXRebd9KQd+IIzwwzn7vGfy6oi7etr8daAM BPlUwbYr4NSk9KQ+NPyFu5PKxNKrTPgXXsx0IK9Fc+M0YqDSvXsuwlqy++rvWodXtKw9f/goJZnJ RAorLt/tP7a5WlvjrIhPg5qc7WHKxWXs4FGg9dBmEHguDtRG5RqeVR7TkrIQo6s1xceMRPogrjQ6 REFikt2NjYrP16MZL44aoCcnNexb0YiTkas9Bqh4so2I90sqISzSwOKuM/ZT2EMZxOj8RVppdI8K UHJfWiUNxBZCRDPQ8Ks4IjJ8tVLp+hLTP1nwpD/tejCLH05URgCjXf/fuvYFcr1V9bOH9yQMbn+V uhKN+MvXFu/ZLVKwIsGMhMYRCi0i1CStnkBL27WCkdgGCJ/8CCeftuKlABf7LYFXW5hCyZKyd7OL q98WRh53RxJ0Eu8FVxbgWN4rL8Sow5s0RhEdNFnOuxjANpJrX7Co4z3y2sdkHOIBeVjsHfXqj6gU YNJaiN0h1diCtr/6Jr0euwZjfpjO5k62XhDxle13zUFbWEWOtvxcQRDR1666ulRcxMepEfsMBFkQ hGJHiAAO6lpkAkdGs3dt5SkOaGyh0MMBxbdMFQYD5GAB19FWX6SaChbdBnF5gG6VKdfHV66dS2dY MmZwVz+0VLCzgsLgduM1druPhqn/JnLh5U43LZAif5nQeLzMDqc3HtTUdaXLEpZJiZiZ8bKId6hE HsAx5IUDs5Vf+MRhEYLMxgDqo5I9asY2xZlNeNwR10l6M/YNeNWq7mY2FP4D0ElPa1gNcvA4WYsj Miq0TxVUn+bnSkgJklwJub9Bm5EKfmY/YSxCYLvqu4zveUreUDNKmZ6DEJzDwQxS4V3yoNa/9jKd f95S46OlxWv/0rTWhIgF6tUJuW54I9HYHBLS6JcZd4Ia8chEd+q1VcedTcTQDA4wdnPXC0vZzXUP Ysr/26pSnpQHTwo0J2GwR0yr3CQSP/+yBVazZUi441kEatPahEp3bYyvdfONxNkeP5rQ7ISGgeke WzXlC99U6zgUGXDtKjAy9KKzX4ny++EZGvjEDDciNaIpAKzbWOyEYB+rhRoOMOqGRR2T1AAQnhfH PsL3f7LEbHd7AiL9n1i0GAEd4dYp5RpUZ+qhGjVveSiYGxdmLUknu7jGsHeArGVCigGBJYt5w9uQ kRGo3G3X+FU6d5SET3sR1jnzKtmy0e6XxJuCQeXumrbqHOw2LiQlU/yiX6ln+oCtzdQOI6RpyGOJ IKN6kbBEFjluhj3fxHMfUxr3TXdNzySpVnkzPHChVZWhf8rd68xUo3tr4yF5lWQ48KSjhZSWLHf/ WZZVfpQmPHQoqLZ8DjyNjW8oKRmr1OIqx5gh3vMQkOip7oQtePA35ihSm+JgmBl/w/1DqY0wmEEb 5DIi+6OZfQlYGhvyZuT9Ot2DD/Hx/hSFcJCn8+5FZMVBlMdV2RpVGJA3sTjN3xpATTM+j62behTw tlXUrRzgI6vUPXU/FHg9owjD/5zuRA203inU4Iy1eUXTmx4r/lgEQ2wp+Uj04TFinVaeWw15dfWA mHLD4MOEk2coDCzcOPfIub/w2LLoavsYvwHOzlDgzWX4iQrjJZfDkRIlg8MJE7JVIHxGfRVXDNDa 7uD7KD7P7Aav7B8V/B8ZVdr3zmC9qIuSnsVMNFv2gWFOK5LX+EYDzwaTZiIBli7znMuPdVZ3HicV Ufr87Qi9KPOLc906MmsY5uTFeTQ+moIGsXh1QIOuSndaPlBtgskx9t3oidXmnAeYG75j2S9ZuA0v cbRHpDmUQRkWayQgB+UKe7Pnviqvt3gLFUnKH3JqrVMz4h3jvR/K/5UT0oCkh7vaXyg4ww9f7r7R T/pu7ijtWvFwf+SW2dijbxnpKtcO4L7kyNVNzs8HXxGZyrk1vHixNn7qeMToJS/vLDtUbFoZv4gZ evTkOf14EU8g9ICvLc/UAmOBb3MRoW0cqCI283n03215HotZqe4JIBZ4iei04wL1JWkNwxHK76Nw e/11Gyrdk7geoyd6rNaadr24A3CKLiJyx7KeLe9tmBz4HAOMf61wp1AXwDl1PIFnxF5HOOjGpZk6 bknvNbR4K4lZGPagl9Ky9ZB4Dh23YzeWR/74c5neXmdAXVdkL9ZUTQ3LcIfReQVoYJQQVsuAMC3e +r4ve9mexp8oTvpcinPWKNYxveHvSb/sWoqMNvxSJxMmuBmlcUklIP5vV/15a0MoZAkawCdmKynC yWp+JD4AeUg3O7hd5pzgohvzVu5f6i1BxKH0M9IfBpw1JcWMS74CdG7rAUQL5B13KEOQ8JLQ7+mx poes011mdQzuKaQZbBXd2TGExDHe1PEjIZH3Pl7d8SXreleP31GHcE842j9B2NpfXcDgmR0VB0Im M4wgTk765OfCOp9gkgp4ZDZh6CpRFKELF2J7L4MuiQLJLh+TaDrxfKEAz9qSUCYa+7cQFvH4Ea5E UEakWpkyVz89FCHo6tX7yPLBpyUNRpPP5QSMY14QgeqGfQuJ8mfCxtdos7nGTQLYBh0zsMH2jAVE D4G4/1HFh0eEteupfSxVcM/8NSs1/eMxhJEqOXFS99yzPtTYadzTzlg6AHtkTK0L5iferZrUyD9O K0hzX1VrP10R3gSBlYjfYnEz0D13uGSQkTMyp+SqZP2UQKXeLfsayBzNbRoL2vDtPpJ3CUuRw2ab 2Bjl05zXcw1ogn8GgYJ3okm4X9NwQt3Twu4fuD2Cvii9FfOeLVEUbT8Phf6ThFvHYJoKpHSHGdwT yihqvwKwLa81zLt2XZi2KKgyGgwt/Lrwl9+aOfBCDtu1HFdzOfXEiT4zr19bmRnSL2K9xxP8DqJB z195RfOKGlZDim77uBk+oH+TC2ofs0wIxTTfNpRgQ5pAveeQUT6owd45y4z4w6RLnpYI5ea6xqqn ar3q3oONmwB6mnxV/0sM6/hdbvbGm84md5xqYLGJ1w8NeZaiKKcsfosaUjIKfMb4SZ4YTglB+Jnm XX2cCMiW7gRo86pi1bZ1aT+/hhG5NI1BwmMQfGkO8t5cbUznX9VtU1ig5+z6CnG+mZ/uZla76yma sg3kTrv9AIEeKqRc0PTsSGpcO9ESNLc0e4GjALyWl37GFJhEhbDZr0gxuujX4PG9MaGQrfgg3oe2 fQ5WZk8I4kQGAr5ob++qHQUaif+nhpQCiZ0ARToKg5sBAemRd7rvOLS7lLdCQ5VdUCaZPWuOACui q7X5Y36lxiaPU/Lm9/6/YsO71m9v6KoVAv7iSnDNPrCO4CEdKxN3e3veZlol7Z17xFQaCO/dh+uM 35pTzZFgzJTiSB7VZq96YFHGAdzHScrSaoggciv0YlWWofyCw7apG47mxRfVkKUYpzohS42jz1t5 O6Lvsx/WF9hmvioUN4+m1XSOG4vOQ69ETjgO1uEdXU5NrFC+SjDpRn/50SWV/AUJISYGH4vrebJr gJfmFhb6ZmeKO0cY0n5XKoYvq2hUf9wN9xjsC68mIJNVdiQqvnX9RW66rs+hB1ZTULCTU5JGZh1d 9t9fjcsACcQIclOMAeZVjXW132UeENZbRc/KM5ur+4pY5oU8sbMg6560OYyNSeWyqh1TXYVi34aC 3clpET8Qn9IUr1Sf1cZNCtEM6L/sA9hs5ffKCLrtPXdDQ88BmfFQfBehvji+WtUjjwEt8PxEWIsG t/S39xBgBO+jZxg9z7tkTkrpcuOH8rmpqYwPdzrp295243OAzsVo38cPNiYL0G1aytuIV+ULQDd8 3tV2EcRYDgEPVf6r2rdxnq5+U0dXGdUdutYDXdqxAIeSBxvhTI1VVEWHwZmFsvaAhBupYHFVf4bO B08u94vS4g9E+mutdaJaLaPJhl5KcWaXherMuLJk+jdTPRr437C5bCBDe/1cJf/pCLMVjo/xum4z dgaOBbvDioCUd764yf9atSsK3FPwumS1Mh6ith0ITwAGkk8lKhdrA8QM1SwnAtfZ/Txm1dHk6Uv8 5V+0/nEKw/NNQL0p6frqQB4AR1se9rx/JPzZTDjPYBPtMwW8Xe+XFpvR0/kTgPQzx691ZJldXGm3 4+C4LDT4dieXtxCKzq8k+5nBMSin4iGmrwUz9AiyszbbiCS1OKoS2s7j0Qv6AsoaqQbtXvjFchWD e8qJDXkFBHMOOklivHQFYK9Qa3ra80u7svYa6w5YS7Wy2mSrrgo40FJFpF0BdeP6LgIK5CPickvZ MYyy/1MhUFMLvCHAtuRRPXdaQcLMPt2/ebA2/K/xkyb79lcXk8iY+n/WKwIsgymaAhcWv6nn6BTI UVlFmzQoaDLRkno1G4xFimqMb5wio9Ylz2KJVpG5wUZjFXj/BDJfx/qnzuZn2S0UV5H4dh1ZoOGn jCRZWdWy49Z+rgsd++45LxcaI0UbaAArcEI/7glGOWy9WaKmgIAXRKMa7/gbNI7pBpgcV2XVocZY YfhV0a6cB29+RG20OTk6Fv1Naw+dDyqZeXii9hX7P6wOrEq+4Yb8IW2V6oxQge4VGnYgfdn9AjdQ tcDgxLHS+xlZXlAbSd+ejL1hpgz8KfCdFbe5dDax2y+UfSMBd1z8MYDPhOEnb+ISjM7HcO27bdfP kVvJ5iflAoB+wGpcdsWsu4JGZe21OFVcCz+4XGmB75lcoGS8IJ9XpeCYDp4ZvRVlitJIO86O5+Xn vFz+Vq+41P67lwaCBZCNfElOZOR8ILiXx6u6zTNK59eAgGiscSmfA5ZKLomCTH2Qf2gphTvQ8bbG v2jDb/Ek15G37oJjDyDXbpDurNx5OXRbWORjvau6Jqt0ymzFPLcJTOQ2dkK3JeMVFTtGO8u1QRR2 uwNNeY44o6KC2omx1vFqFQsdD9Vh5En717WmRS2017JlmpocWaFWJp/uzGnOCIESpUDOBaeiXgl5 xTesPu/VEnY39PIxEm/fWg8HyxxVla7mMuPROP+MJGqHxiZHVMrre7uIzJknNUYno6sT/2dx5LO+ E2Qguf2gD1ocyg9o6UBBGg8Ji9xfEskAdrxbxMppmc5qbHcUQTn4nRJNHTyfcZjc9BN48Hz9/DVA /h/B4hwtVl5zAjx/EebhcpEMReca5vFO+Y3+4fK0VE97z9zCukkTIwic/sck/fhRejyLmQlSm/Lp esItoSW6CbhCWfpX6jUWwitqJlZO2E1gKLGCNViDEgS2DlaY/ebZ3kbWq3RtQnb5H0DdwFyS50iY 8o6JqCJZqPxNifnxvHAloXuXKbPPSuLqH/P4Wh6E6MI9XjjSVhOd/v278pS8Q8NnawSOxQk20O8S rG+lIRsWdNvrgdHHnvg3ld4UJ+8Y6t8VMkU1oc2+7NnsPF4nXSIwd/RIxvRhwbewXqd/89QapMC4 Jr/iLIAf4FGNdzfYBOIIxFR+XCyobywS8El86PwlrjTqmBT4QgacBqZYo1QL/NJppYL13Fg1Jj0s LVqjrvUYmVRf3LRzd9MwwNE+NCHldJRfyRSuQJrIw0lth6W0JecCsA0Ah50HdMj5Wg+o3OoVzxKI D8AqGiDS24Yt/lyD+wZFMk7tc9lRStgkBhJcDAnaewamHaIE1YCd8057AkFIDM0H9fJdggoDi/e7 j4VM0zMuKq01lI3lCfEt9XJFjzru0g+F3ooMdHOGqGEYS/Zx7vuhS0sxI/w4QmYx920JBM7iI/sM 7NjX3fPJm5LoBCwrJ1LE7d+wxfWAIjmGKq15AosBumDXQdXADccP7o7laCnaZnooOt8ng9PUYKjB LLcJswfMvUnq4xUlNB2QugeQk5wMMUnEZlg3nSM6yvmYJ6gunGbTXegSWEyuDwHZB6G5BtzGGVc/ +lCHmCkoe2ieo4Jl0RP5p1zOXcToc4cqY5OHPbnqFq/Nvu1Ffp+F/YbdfhQc/8r8yablOHybgfgH JuiiIJWbjvbsw+rfIjhUyR6LbudX9ZsE3/hh8MmseslIJI6qxyq73vgAXZaD+fv0nUmHTWaFYwkE 7finrQD9hnohe+FeXiuWyw9FUfi0gVLuY967TyGtmeIsLH4AjDPe4j1BYBSybZ0Z+E+l/UcllILB UcuWl4nCiR+vyYUbIXOcBUVlMhZGNINxk/7esq4JgMxDisBgoFE/1yr1PTypp2BNWg0sJ0wcNsX2 wKnE8xP3piSbNbcw8i47Dz57ukpXhSh9f+i8Ntjoe60KiG0h5gLEKlpBVMjO3T7jCGkKiE5ovjI4 1tkPkSQXobR8ZhJk1YBb35Xat4a3Yd9mYXJid0eMKu6I5ispMxnuNabQnMAZGewJzov3hwHJl0aL ZKdfzMvPqd8E2cqNCzQRjYNPlHb8CTHWTUIapbxAV+tINX73UmzIJgegddXokyg3P6GmTEUbEeVk 0CMcOYWI5I0Muu4PNaoZuY49YEWExRaaPX3LI3qaMJrZqW09Rrc2EUTWwhcB0Ac7HdPOr4tjxls0 61V6CltnlTLJ1MM/15kfphjQQLkbM88ceBgUZbg6SFzA18hI547RYDurrZKX9VOh2Ovo30juJy28 7kL7lXHoKjrckVuIZwhjjzKIFIjEWyOBaevavWbFP1AxGmtTECFlg52PrTRae1JJB3WeH/JWcL46 ApnW9IlcvddzjGrKz3heofRMcfP2b6TEqUdga+mce7R4CGIVeeG1tdNiQ27abmM4hQj/2pl0y4vL omaxUjFaetHfI7Q/dQIMdMjjOAyDqNMF7eOSZEmHpy69JE6ZTLsqeq3r3ObFnNzF3fDC5/glHwB1 WZGfXglzbul3UbpuMbVlm1zz1xgSlrOrZBm17zVtMlnID8VBtp7kIC/kbjLpuASy5d73pac7AMzr O0BHq0ETJrelKvCA8d1VHYBj2rNblqgQRojZOupgmHEyGfxz9vU4kMrsyfs1nDNdOObmXBFHepLe P2OK9roYvgoDoYUwR75fwg5rMcot6L6SgQkGwP+QoRTi4FGbZdGSnwNHA0zmDc0ZsFu9sxQoeZEG vp+Y+rTTCQBp25uv8usroOGAMaaQSgzFVHMA5YBRIoizzAjFs7sTohE4Ws0Ltng/NqRDn4OKtVsO 36oErSJ8Zqa05Xi7gXMqzjuFV191ncpcQW5q4d08aDmMzL/+35ic+6MGK5k/1o6DCDE0Q+rPTOwA b3TWUfSGDhOx0VJf/beaTHR3f8N3CIRmbJ5FvqY2qDU4tsDMQq0CUpsmCJ3rB34PJNExF7CWE0vs vlLX/2JqxlOq7A4HJoOORT3Pc6IWXNBe2qDmkK6+OsbYyvNRlx003l2ItI9X7Kiyg/JiaC2+YFmE ZIncqHzj3vcvyliJbcRDXHvCBZHikCYuFwDI4rR6oHEOpRA4rBWG3M76pxe71IIHVhR1Ijh0h11V IAnEbh+Dmgpz1eM3sUmLFhU4eqnbnVH7hUuVg966R+kNQ/galK0te+ApFOCwBsHd1ugLqt6/4Y5h awsOVSiUlteHFaKgwIB+T3lKak/Ox3NOn0yRztqDpqeTP9+AozgTzNVh05V1aGeFLixKDFoK3Nma gWeMhP5kPre2IKHlWUTrh51R2lN5GUeaPHtAJqvulgHzn78czDuryOi1BGV+q9k+A8nLBqItgAxB 1qrG8p9nxqa4j2OPMbm9LyjmWorujbAIjpe5ODyFZe6kTwYrJ1+6iZWnliTkokt/H3GjQHLF+r9g /eH+FszU+SZKTYRIk1RFvW0n1qdApApXVPfSMyQ42IITT+k5akWQtg15w/B/hTyeB07RnKBu8sis Uwf/3xM9UkxcMNXEr2Zr2WnC4hmeR8VrxpoYEMGsUyzK63B72JNuyZ6HTuFrBVitbeyCwggyQkQv HHOJWMIYqPm1M/OpijpvLuhW2J0brMjVjNKxYQwJGEAKOKSn19Ie7l8YCUglodHOJ9M8S4d9DBkc HkfRwljCzJ6pRKIkGpxROx2NUSeyOlBmrfMrkT8UK5TtBlhvy0OPmN69pgi8TXQvF2pbuL9HQ/2L QL4c7WxuF02s22oM1CMimsHkP7qGYsNUPpCZoQq7Zk36lHI0164gpNnPuYE3JWoz6Cch1snCNMYn +HIq51/5xNhdaGb4rt8n4PTF7pGSDTJGe5OX0jk7YCC20hvzLo9vxr/E7k7egPO2B4jIaRph6Dum WPXaOH0XZDp5E6KcFOHRn46RAR8FEDeBygj2RLrNaLsHrKexHDEWrKthsDcwPFURQsn67+JUkc6c Xhd6dxUE5MMSmrjiPSIBJACEw3UiKoYbI/fP6LEzDgoybQe6T0jJxkWmu2PYIN74sWMxbQ2VJl/J Xn8o8B67yrUwwInlLqzbkDl4MtbBvhQOeUMF/QzHmdSDuVXgHwe88Hf68oOyMzjtQCUpJg3PTyWW rGTp2E31fmIYJnAAk6Av0Eyy75AfJrJurtSzon8IkflYbsg1F2nVivSsnnDo5RMD2BQ2B8xwxR3/ ngd+YWX4QAK7xQoKCBcAtV1rPLOTkFWps79jh0JL59LvXTIvztFxG5YeHovuyet35RFfy1nbHUd+ sWOnZMzdCFuHKD3dpBz1jndvM1lyY/Wi/o4uZ23c+2+kuWy38RdNBwR26JJKVWxHy05UgZwnmSJ4 qOEgupCHboET9hJp8HfGix1n/GVBqsmcwEPfPweejJDV4UR/Ww+3PWBgDN3TxgsQGS3w77FK4+fA kvbLQ3pEYr+97aeqKoJPztqW99RI06sec1OBGfjjscMAjQZO/jBE4xBYIKDiopiT+NUO8jlB0n/q nLt2s610x0ir4ZfpAyNQ8Y3HVVmZskTBzpRol/9ovJN/jAActwTF5WjzwGrcvK4h4+DgPumzRW5J 9sNH5+VRfWOe1a4Xb/PDMGTfLKXappvr6cD7ya/CuvH55DgzFdgAjb9t/gOIy4d5vEagAyfMUPAT UgpDbufq9sWfRlslM+KVtoV4EhPg9ecPoJXEwSAXfPYm4xl6tNEF8ccVq5a7BPYpqmpNnLPBBFwc 8sEdYYYXBfhexnzmFmCxM5Z2V4x1A2yZSeV3NE7bSqOzWYjn2VYqzdrV77SXBLLzAuScZSbC1gHP Ad3cu+j73gYKDoX9OyWF9ZWk3iOWkvEziljiJ0T5B+Z5G2kZAhGhHgiR8qW0T0kJ9f545psAX32g VPa4tKOclHV3aQHztBair8va0RYsghu6QFPx2tLh/SlE5i4IulRgX0tn3l6Z32HbRGlo5IZK2yE/ Efd23J0Kx28gbztqX+VmKTsSNspsl8a9/qaPGVXZrd6gE7KdJG6ZP2pCbFEXcLJ50cm/no1RSIA7 L1rziddej2rWWE7FVzn7108AgTJVauhVUcHayYU65p5iplkLchqkzxEB/lhVGU8jwPybR6cW5Gzz pPFi5sSYNKomTmtsW+BKXsUCUukCvcZdju+L0ZtXCRRg9xbFk+2EmXv0us6F26hXe90x+l4Kv/fb H/JCkxo8r4eiM9EsG+dUQ8h1X/4vClCcjhJhiecZXrsshwbQpKps2QeErrndRTVnmPQam8fqaMxL QGe5Ac9IrU+vXB56SDnOSA24c0o0pqzksaw9wsvKtDCVxvXM8S9Ob7ukJ2h34m/WK9qeMFtreNds Okk6JvTzE/saRAEk1wtoeTO65yMxbKPo/06Ksr4myVM541UEKwbSzaEw+dvtrhaoarIsxXzQLz6U IfAy2fHtaW6LyBz1UY8lDEAoneyaxOhXgitY8e/n3phlN0yaJl4FDkBGTswAPoX7Lb23aT/Z9pBk DKQhCbxfWCNShdk5iV+n5HrxhmPQlUc6/xR4vDaiKsOk6ZeNCZaVYbsDuNVKfaWFWyXxo/s+MimU RiNbc7leBpHDRut0kpeMuAHihUcndP3tjZrfuh5Q4p5CA3OHltJtaJCmti1tBtstNye2VQ1+nHNV 94uA4ME0PqUMOTAniFxhZRwRDmbrPodRu0zaOVuVcrMY0zEyEKr3dNkfb6aeSs+WL3I1FBIxZbYN gjaIl/hyJ4+G7kC1jWF7K6iugGBazRcg5cIF9swbO++JCz88TqumI8F4+Pq9PhaRaJxO4MEFTREs 3DlkkrH8ToBc0dBReSxXuOqe2yk9l6L7+P5Raasb+U82wmyDgbVKsgFUDEmnFrZEqOsRfzRSWclV 3MFpa+SNoBRITFHS442V4b+2aZTrPLi3b0KhfS0xdhI+ptaKnhPxxNE+v9f6Qjbvzvy3DFFkd/jL qEVxCi1NkGPQCIfwf08ij0TiuV6HoCJWIrPQaf9CPW3IED2qduKJJGhndU6vH6HwT0Mjmv7XaO1c HoW6vhzoaWPZahje4fizIhAj4xUE0QV95W8PY3xljfv6XXC2pIeIFJ/dkCIkPjMfkzOuIov1XWfi b+DLEtMaa6+9lJBUsSgh7qHQ7Cdd7CbphkfQfbJGhnhRvZH8zkgwfWxSXA8FyXh0gZk1IqqxzZoP ps+Yy6p20kHPwkmNi35b3pSHYpzSuR4kIL3f0FQLBW/3wRKOv2QII/uA42rwNS6lo+k56NN9F5Pt Q4DsXd30lssivaHf7FiY8k5aJ2sCOigv98R2ZS6TwdAG7vlkYt5nSZGEmwejl2RA1FFNcFktyfUa ixpElVCwMtHzlLFw2Jz5ZQLSyhTwr5SX/25tUxtCL7mVmR3MIA78rlUuDuRhZPgVMp/bqbXLRZs3 9htqm6fkdqqJ29cj+N3x+79Ku7a1UsqDWDQjqscgj3Sf4rxJEy7D0m0N9kNcCvpMH+jAu4nFkyzt 0yMzGW/smYQ3M1GehHK5pb4Ikr7yhh3I+X5rdtDgL2e9XpcfEJKx5zk5XDzo/dk6oW7XYG4FTKII ygTXohqko28jSNbyK+T8X5mUj0AeZA7EjxWKa11NfPUoOGO0xdDqs8uMmBiPQdQfXZ05nY2C5soc OoN/AyMHM60jD/uzLJM2YzBZiobs+IGShXajeaeNA9LD2Mccv0wemP3OBjuJLhXhPfgAtAmdpTXw 1R595rdQtvG+KvdcJigRRnPaxGQLAOfxI+HWmjE5bIdKBalZ0lP1ofHyMTJGux604xx6KaewbFbp cBfqStJA4yqbyqy2jnz77xzH71G9tXopieUkhyvYBqR6gODfJaXXro1hotX+E+0zOupX2By8QnmB duow9GvRb1zJjXSzoYFAcuTbqMd84dknGuM+VR9zPzm9UPEkmlN0FZxByzKTVflfOV0eTwv0CZXV f6fJ7fNstBOVWt8cZZ3mdW8hxsas0ZG27dEaWehdaXAP/ohuKmivx8SQGi+uw3UaB5s5ilBuHDlO +qQOTNwK4owV3bH2S1NxPOvvq81wSCoy4CMdl+RbKEzBz3cbDl132pleyglHw/84+lLLD2Bgj3hi Tclrz9L380IWJfqYQ2Ecq+oIpNCMS8qJlFDkHmKvKqs8Ygk2C7POuC5kaKZ/hiegFipL8yIVfLcO VNLQnmw/HT3RwIJsvQI0i4F3dOD/J1UhgZ62pkMNoQgpTNhRICb9kuXKo9sOGgwxnuO9h/ZBvBzD BQMFtQW4oj4X3y8lFHfuDehtaEGp9ZZTYR3WO9rJ4+xCNKUFQwqcocRtEKHVxawVftl8x8Rg0E7B gYk49h6NMlHsrOBLFzgftI+YU6BUc9aXtpHAHf7jSz9VSsvtqIbUTvSHf/kdVdoN5t+fKXrLTe+o yT2M9T3te/Hn3llIj0+qZxfPsgu+P2kwPCsiGvjYN5hubC8qH35PcBu/7oT558+t8a4//5+yE2AJ tkRyDsLqH05j7Erp5O7WGYW9fTvA1y2onkit8NrbtVQe3NPWGbkhzqmQQTGCTka4LK/q59nwnXif dgytCwAvY/+4ZcxKOWH7YN5gKcknQF57AW2P9j2CD66RAQVwQiDAd0Eoyrpl7mzxFEpYBgUlULgp EBH9F0QCjoWJooCdbTDk/GNf0gfxS63F/Qt525v8z1yQiaDqMrzu5d9dHlgJYNs82VoosvKwladh SNp8zVyPG7a+HC3VhSrrEOVmZec/EpeFx8quYpX9RuH1lNieUY4eva7L7T10zSy8bXuH+hZ5FU64 VEn3fduQbI+tITewEVQ92Ql2QA8k8D8lSLX1yfrek3lwrZTjpysj++GHSbFt8GNuvuXbM6yuKHJ1 B6lTjj4d9a+lwb7S5p1vWJBRa7NWzX39ukK5/yf97pH/+AIHnhW1k5ixVWX7L7FS8qWJa0Nkbzgo 55r6WtmNUFfUz+KLkl8/+VLHvzuRcAPlOOeZfAZtcxrhYi7UyyB1GoXMjW4ZL3eKtNHXYtvNgZmO 1NDKHkNW47W9+Bay+M+3s24wOr/qLwFkWIPI+wQ/ywvcZEJIXJ5iA6G2an2dvdafn68DeUMW7Ptm nXkR+d8k38yF0muiLPiYauHy1jRIdv7anxJAda3Nx5vf7deJ2+liq9ZzB383zZrBjBArzmv9bXLK rCt2bePJ/WKa9JQeDN/wRzuV8YhgpitGGu7YpNA9XyBScvzr8UOE7Qy9C46e1p8QPA11d8qCC4of WPLUws3XuiXClZdpOuDrgtJ8Oyo/iV2wpvJyVouHhj4dp6H+7D3PsD0sRnJkCNNjGkkcovf37H1n 9aRM4gTGXTwTUFhaMyvxJy59m7m1Qy6HbUyp98yvi0SKX2uRHL6l5E6WrEb8r3n/xFKOjHeBAipv 4V728u/D2MnsO3/0n9sRmFSfYZye0quv/Jar2kk0iOEun0dUEYLaqiMcF1/t7Ji8c+YtEir+IBCA eHCFoi8OuOnNrXG68ETAZDxDqTP/5hUJCsANR2BXLVvq/nocpJpfvWGeyGidA+5JGfldndYJhUhH ES4R1d07ojLYN6mvYNvo3GkcMYiwqNtNii7Hh7rSNRgazGfJydCnUtgoSVhe8pqIQTA7FqA5MQKy epzpK366TDZ8en/iGYYl9Y8AZOa8Uc0jZkeF1DIoN8nozhPh2ugR8lWrVLNh3AmkdXEUI0MtwY11 SfYVHghFYj5Ce2d4n8836/q4LQEYo+lGchzfBa9J2XsO/BA4DBU3yEHnWlZEKBnyQpKnKolYMUTB KJX4qWoAlaS8VWTl4IFJlVJm4w2E+g5SaPIv85gFuFW2N+/d/NaNYSpBfwkHbu846Ri3jJIHcrc3 3Y3arE2XeTEpZ8fUBayl683gYnPz63mWsEShkhS2p+VrkopvfrRGO2oscn20U16GMPPYsd7s94al flvU6EBZ9/BSF++UjEpQVF4n51TF2n0/ufFO9BWFWvCQSjPiF7zLGPS91JVk/rHlRCoiXdMPTyjB c5DaZ9/sPnJgXGUkaCK4/EXOcKSdxPoo5tvcT9hZHdRdHFaix2veGUBdiGvkgZaOkjez4gtwZFZV KwsL20fRxjbKXtGNl2U18/BjSH6LHlq+VL6PdEuvfKX4XWI/zrFz1VdY7cmXUtP0w2Zzb3lDaUk1 ZNUtpH7gxlCPNs3QHMpEauOFjNlwSEXIZwcFB5U1lOev4FOyOCb0eS/SYvyR4Mlv/E+hkaw8GbsX boQUduMgiTCXAiSCbkRkN8h6NZ/FoJggsR8qbOVtatvf/5GKI4BaRSyiSGhX1V+KszgGRt3Oqx2M cNEz2n35xP2lNuUDbwpvIBlr7eJ5nlRF7ndaB/bfzHBWuiP5m7fMakRcs5xfDoVISJTlVgUpCgI/ ZHmPWBo+OFtOpq3AXAOAClPXp6fdWqAPzWMmYRAyS4uyKjJqb81gcjAJxEspjq0/v0JAV36IYhGd pRsppfi+NBHk/+jD5It/+HMLY9HuRzj5U7FCLeR/5uvWIvXwtxWihrVEz4m/Lj6uIXSrTxzAin9/ zSULGeoUL5ZJ65hGbvGx3xEMKNR/AXC/jzhIj50nE7R+SpXxjqCQM2kef54nMr1zJWzo4vVIj4t6 jo3zFKmdDplXI8YGhvZTbwoNOp7Vk2YtYVVVNCsvswPiu8KeMaM5ayjLRY9Ekyr+QdSlHwVCM7FJ KU2XST+q9hiJEYRsPmZRA25Y18DPeLj0V00qgB0+E2zlUB4rBcNJOrY5zT7E9bL9oXjNCvTUYVP9 Fuyjbu5CPZhqN3yJw6guS8/1TlDRLIqPyufLf/ZcYhFlY2YSw7jWvCnpDMrAAoPRwopgB+1cK4oG io282ZdG4XYB9fhzeeduNcHnEdtd2sIwRnQZDMvpNPV2u4T6c2qW7amwXCeVjHZ3Z1gs9aIkFvqo fVMOTPKaQ/iq1DLi47tNtL+SGgyFdQiCatN5ozM8vs55QlxN+AUtkUwM3AWS7B1tSAhspW7H1ylE aWryK5A4tg0Q7OXue4omknnrRU6eRb4GFiQ7mWvbBv0eIXMhcfvoje+j7VZkL1XXZ6+Kjygg4wDU JwnSHR3rGeUMAKYeaLhJU2Kteg7wiimdTNDCUg6zIearxoQ3kiawPD2tubI58NDusyTV11bR61Hn 68ZwJXSBlH94kzYBoE9v7T1dtaHU/Q5VafllpoyfxjJgyKq4rFcHufIPOednbrAYGvPLVInouxQx lkpbMxeiVMIDYpEm5rLHB9lyQFKyiMizW//bw/FTyVDx3a0Bq9kR+BMaGQQlrhePqXdCbX/lBPk/ +WXfoq7mQIiZ9AtBWq5+OM0V5EppxrqfHYBtdUdDtwyDGYlBPK0ls7EE7jvFZOOfHOWIcabMpuAB W0VSx5Xibd8FZT8f9p3Hu2AlooJS4TSfBjCrQOMDXydy+xzzkR0Dr82hhYnJM0935zqC3BctPGvJ TSRUO7j2nsUqMy2zDoXAebErgeYyRnUnqy2ayQmo5Ym7icfiai+mS8I9EiPl7BUbEuGPCV7tsg2R ME6+A54aZRtqCGeoQtJO76raBngw6uwiD0RepNmRcusfBp2MkQOSGvux6tZyHOXAfdhreN5oO+gS Ck3JXTbZ9icH+vc1bFPVG6pBzSOhIrR3/tbt5kihg4qDVruLG09yn9t3w8EVxdLooon5XnWXYOsw DO9Ciijps+IQ++KZOucG3GibFEyBe1nGOxROIohV0U17zRu4JNXpfTslBVl9ac567jmfsZwbH4H8 SLA0FMRShOPbK9aGFNEn88YpLJy4jPqecKAQpVLkuGPN4EQcN9KUPp3k8TfQoSYejEJYxCOOzKrq 4WYTCSbyKK6Ekq7VV6z3VZNivQt689VdOGrQc+v3Jd5T/S+ch/6i7wKGYwCNsGirnG/belKB8okO pSOjGWRncdP52GgT+fZMBnbfpucW/fuXLnSVtZV8AiKO976Q/jk0ISzBC53lAf4oTjhajIkEMXNA NOj2z4MbOePELY2RBdYqpaFKmV6RXXzTZ16CEqLfo6jjOitT5xJ1nRBl6CJajozhK2smNt2Y+7Bw fop0nX7uacECjqXuW2yuKXpmTmcEEAi/e9+4A7BX/W0ExkazKykiSeWuG5rX789oVcSwx5mhcGby M6w74owDeJ4SMoObdxfQenUdNbob+lvF+/VeIHMy9CIMhhLTw4F3ZKdR2ru62epfHwvs00P71w9a My0McAja/UePCEnyMpYSMTDsgN60PC2sg5NlPlnmWaOUi6Hl0kIxABmQgiTEDWX6hXjXrdwGMYcu y32wLvZUaPOUv0cVjH/sKONbgPiy9HGpC+soUzHb3QhaNx9wX45HogF9jRa10Es7qvrISjmcI+7c GKDEYIBo/Rvy4+139ZooFKPBFYLehI3tTSLSqiSRFGDQCl5qte+LNYz+R45p5f/4P8wPcON496mu LMX0K4ZLpI4LOsX1DRhO5HV1eKDLDB4yRzggp0QcaV6cYXQynjrC4pD8P7myBwETIOLHIafQ78cJ tT08nmQiSQhOaj02xCCht968+UvOigK6pn1N/EBhg83NQB2B1xlv+B5VtdLHpV5Nd6h2qVRh0fJA LNBekKbpwcZJksiDQTwkKpTP/ffdry2eJSqBfmeGEKYrlvmBT+kvSjFJRuAQHRPA8vyx9B285dVs BR41M22CCYH6MBxbXmH8NJ1H0mxqWyIp5Z/T9Cot6yXDxZJTfQD+4akGQC6GCnQj1hbbFqi/nlc5 VFshrQJvYVAf7fv5iwh58s+zpJYq2T/3J1jvZrl/mHR64AhfnxhK+g3VQaXkoIpTp5kUK56HhyYc gAPLfAeE4UpiTRTISVcM5MYu1f48FQi3O3sRA1ZNRHfnvJrmMKgvFnnMkZ0pVnK2C9XTsFbc6S5k b9uYd8t65FZGkBXCmjWVek8tcoc3Ej7CrfJK/+ZQvShBCD2eFzYB3PrbazPO5QPaU7LlWRsKsRdy U6gHqjbnroxkuX6a3mg73oTIdh6OnfxVaTMqomWnWvlPBynUnKyozcvoa96RnmVCsoDkyPWnoEx9 2Cwg7odP4JF0sYbH9TwSERPNoBVG4Shk6pxae6i8er6Fxh2vBnAxmo1hHSGEx5jLYvFSMblGY/wz axI9Ln747rldLyjQhpdBdpNyjyVMR9MSF3dKDpJpyh4szK0igyO16v8ZCxTcd/GNkQX7p0hf6PMZ fbbCYPgxETISifEqBKNpjBaj73xFt5ueUM93nsxnJ6SkJRVD+BKXlYcq1FsxULOYqpOdsx61+liX +mh/CJntO4NqrDQrJlf6DcD4Oa5p6VNlyhkek0VwBXRS+lznxoIR2+1W1dUXv1okyZjmdJwDeh2t 1XIBf8UBPbD5xgGIgiaNNWZUyyJvUF53m6gnE8wxBGD7uxudbgonh4G9m5QKQqn11LKZS8CJ1BAn 0W3leS8aehQWzN87iLy9edBVHdFwIZpy7TkHRUXLa7HngDOVm81xtQnzDcl7GbY9Q5SWp25UVSNy TBAd5VArGhFYtljQpPLf7KEJwMkbdhjcns+RAK/MzAdL3GUuzW8cjKBwZCOdXHACmWeFRajPnqic 9qLWQfywbAwAI6vOtYBbf6hxufWiuVxvRRNuG1TpEDDtTn6iQM/42UOBhQ+qBZRR2m0yeNjWiOXV W5XxnzQ0iC2cPqxdXIpy6EjNjx7zw85X1g5mWAQE3LPdffG31m579/XD+glqRMZSCDM2OqqGBLaG FZWeX6cLb3mi3y+ZkPtC0NzrXEOetckP1cISRKLCNlJsIs6Bv7+wsMhJtSI4Joasp+Wc1UA0um0L 8/dyrQxM7qJUw3kTlTPOkMjlznxs2RhudcefROAnADclqAT1Z1/p4+9N6MHKja7LueWRslENb1hZ L9do/r3DzzFSqr1AP3pWIWju2Qv3LZDTb9impd/B1ZeeV58iZD1oRve9YT4HTOW7bI8MR7fHO2UY RjouoooajNxxSLX0i+kXyte74FMHOPccn3D5azEMwv69nCm/sDSHnIc+CCKAsYXVFC1OCVOnH6vI oelm2w7Qf76ap2U+6C5jBs8VbAYl/Ef1gL7cdIC7DCRaeKeKaYa80eHGgIVjxv+j8DXVubCS35Je CpobcvvSidc6ceX9yYLRZYgn0NgRw7BRs8+b79tYXRHtcMWjtfnOPi21JFViWSwu6GOsQLmwlNG4 /Nv7RyEZGJOBNhCS487mu0mIFVGKApFcRwDcHP2OGoKjWxMk6q6H6RBUh+o8Y4FKYtCZQ3dhYWxH HNGZVJLPi8Isez6Ahoz+CHf8/Psh+ZfRHxuOBmDmauXqrfX0mVZIDJiynHDB5YejLEFOBiyQ7/2p gkg5fyQwg1pN5jEo7WE8eFQI08gDZQg1i/eZTfoO/DO4OEq1srWQOcgntDt/W5VY2MMsuceQwrTj wbQbmjlJvf3iZjWK1b9EY839/cS02vmr2WTC7Cf81o7EkoAN0LuOz7cATTJAmKbJ6ZDzPhYJfR1T u3jPK/Iq/SZmKoPNjcUoDj6Xwwd9uVoN/q7w7XRgqhKQjc6QiCOq+SPYUeJYTXQ174VijdTf22UP sZ6hNxlw27rNXNedbdaOlcBrrQODbCJEFVFRGUsAGif9oWFy4HijRGhplyyfP1opnIBR0/CzX/VL 6eEGp93lN9EYGr8fT+gf5Ru7r8uEzTITtaNF/XIf4lmgQB0BQwdbd7eXmQ6QhmFUmvp3JQ/ajFGH AIWuwExTlxwDPLtW9h2/DZaqCPii8tpdnh4R10SOAomsusu38TkdLi3UFn38mYHyYymn7VRc/wA+ 19XQ/c0XPU6evaYPUN/E/JsMDcAkbEtG4yW25o1tjSnsjZWlNkK6CobYF70hKsSldTEUJ0wadre6 sV63zXKkQsOx/VdOZZeU+/VV3Oz3jDKm1OF0WMPR9zISCxcQspbL4wXvatDewir2xcuZb/+kurvI V3xeR2h4FeGr+Xe5+AricfHo1ErIES2JvlyqI78iol1fiIULQ7hZl6jlNhjhIqfal70xH1ct23Yb Qss5grHQ1G7HajO1ICVydJC+XbuP05JpwR2VQoODA1cq67RAChlPxlGJOx8sAd0e1LM/czFSPgAS Aq8zEdIH7Gv/lXaD9Z8ySW6UDbLkNszqduqcA6Xf9JFTi//swD18cRL4os/dWvNfonMfFmOXWroI 5dWfM4JCl9o3VXoMHQgUceHaARNuUl7AMjGiocJLOSLsEYXtVSuOCzo8uW4DpVhPKEF2SvwkpScE h6YPgOzK0wotWBl547YmnAZDUqxaXpFo/L++ftqsqQbyF28oaoFRJmqVXvt1znZhe7VvHv52RR+S vhtgIIMXTEAsbzhmSruNd9Sz6AlDBs/CrjVyEvtUb4T9ZlCne6RlYk3oIAngcW9WjMw4WIq2CY8m cu+Spj25czq6Q/SZfa8jDqj25qUVlxLlsedMUZLplHr6rQZGGUUaVTCD/C3SLX9NKbbpLkUJ6Wfu SHWr1Q7C+PasBaiJzZRjot3SQifcw3buwyqp6egxaiBZfzSo43DJdHGITQRaHVYbfqlgLmogJUME 7jEuRkz7qkAHFn8oTjubhIGV+g8SzEXAzBd4dfpPeWVHXyxcGgUaxb79ZpXbh9L5spOLq4ziISU9 BRmb6OdD0G8PGc0aMTsdwxyl84lofsqdqhukIHxE9tNyuqEguDePKjZa7QNgn8J4XZ6e86mH0Oxx KwgPmhMpZgF0cVEW60pSJvsYFhW5y1BnP7/SSiEkn4QW5W3GqNKjBYTtCQQJ0D4oVzQF6OOehb4a C2h9wIF8vssKHTlcAUFptTuUS27qH/IHB1aU72ZVysaQeYD5GQKoX5CrTV2GihpyyxJ5jpmKVir7 6p6DBVlc+Wi5gHP53I2UfxHPjZIxVOCkpN6nx1k6LgYL5u/CUxdkLG0t7UZZH1r9u3QM1N/+66GT 6LfkH2JXc4cjdx0adsZzNWpOoZjk6DURDE9Z77VN4GDXKLO511Yo1tFhn4g2ehcwOb2bGw5zhk/e SUBOdQzuWf/jqHczvsLKM1tY7zrsm2lVnmuKXF1kNO0XY+o8wvrJvQfEzxiBcqoXe7XepAVTgEqj BB38sNhin5o+ckzP3gPwGO60++XM7hpePJwaIf0FdARrTswRPBeMnYjnIOobHRjcIRYPA4mA3G7T 3xTLWZVSDmWrg7lVbft+cTCIH4+qQx1I1LjZy5rmsRirubVzT47x+oTdALlHVAFKjcHgeMQt1f+/ dlN/QfO421xe1/mWwTywM9iy9pJLb2WNLiAtpkxE4rcfC4p/jZNnGq6tB52rX3AHeqFYK6zGtDE7 DuRszpxUTuXz7wjegOVuEhc4zhxro+t7XLJiqbBZvEofgxRekE55fn+aWcV7BHakLKtRpXMy31Bc Lou901PFaVAndnB1axNSFk7nWX/TkO+2ya7LRdSKCaasDZiMk3rZH4z2OvT6UIjJCsjMxCk32w+G nMmHeD1RPPXel4AOpFq/FERb2wjZtaI0TQjH+JLusCAOB0Yb2iUtnX/5Y1ymjlZ85WLXGoK6ZATo r3LLARvlVUU+sx2lRbe9KdB5r8USIhzxd9W0NHY5P0bk7FIPIqvq5stGGBTyHZYzjIIzrsGO0+HL w5P3hCtBrUBNjAVQXHmlWcpaRYJqIF0j6iXBNZ46WIdV0lIT5L3wknknLjoPFCz0hUUKbvVrwFHr 9m3RXBJyWIIqASNtqPE8gtUnXIRZQYFR3L0FTbWjyIgPsI4I8hIxQZS71ziT4u+vEZgo+QBB39Ol UjCAKs0JgcZwM9VjHtabEQzmhoINzsZjfbcQX7jofDU6E9n0JTniD1xwIVogDKOBfpIiXRMBh1fx PrXnAzbHv7WN2DRzt/bbrx5Cptce4TjrhvoojXGpNNl7guZONc2Vq7PlYi+pk0XF/vv8xrwPXILK flaElJNsZ56ldzFxJkHaQhNHLO356HDYB5xpdSf0HvAkT0yTEA+P9YzH5g/0cDzIKQqca9AQS96F w2pzruriVhsC+EYT8aIKurhnve0wd/IyNJ0DP3AJ1EabcNpSy2gx/yYa0Lxm/DfhcJ2v70TwNLaP t3Ufxv7B4CcAc+HHRoQ207YsI7SxW7VMUMtWhHHiNekPhE71bYp6gq1rGzoUAcCS08ktvigSkDHc 12RQoCd/R/nlF973btvhK1VJhQ9GYBeeXcTUB+5JaE+xApF89gBlhh0akX83ZvvSfzE6kJzvC4cG Vr+Ap0IQ6TAoDfDF4CjriyaIq1lj2v8JNGDbJW2b1oDQ6ZQWA+ZXvQtV6Xi8VQZBTd53jZ35gbQm TbU0U/+RHL4zhRVbA1dLuWN3AF2MhYaTID1j3jxYvpmlPIAJ+aHfMbWi0A3z1p5qKDrEf16a23iN kb8bDv3Mg9AZ0vKqRL61JVqEPvRRqNrwA2OY+HdGMxAbIPPODF3NIA2BjTT+rnA/x7MVxqVFvxg7 mD5gIxxYA7SvwFdkQ5XHqdTahEYxcUxJBcNDGWvBC+Qwcq2mlKsUn78igGx4+bFn7gCE/mBT1ea1 2WgcgsSxMHmTaNITfvsZWQ632qTT9/rHhIWH+OVM3r89JFstclrRgvbjK0QSzb2du0FcRGbMAY83 gXa7DYngAje+iCyjD2k8nFX7alH02kfklqFGOjbFUb4xiGENxAHsHWuY+U2t0Znx7mu2suqKx0rE 573YdLbFk+dvj9lRRxnBQ6lZh0972W3FzJ2C5oDPvv+VL8jn+cAnBLXAUDqo37Z0123xveyNrral 9Bg3bQWVN895ppZIz18xMQINQhSaxmCSAeRRX62/erXZ/ZmHVilKkrAowb11/hvvnsZ9q4FU7yZh PZDgZ1SI6FxFrsz+MePhCbtFKgysudB9O97zojoQHdMkOMu2bDyXDY2OZhvkqmkANx5M61NXOE+K l3swW+36y5TI1NCCd3V8JtxQOa08rGPgxzLC1CmTGqHugceK1sRmMqRgG91HfAE2HPp61ZeC4cf5 7x3hUfmc0w6BGh1nN0tCTD86i3u2en1pAqilSP7OVJimU3SyKwrbTGw4MgYlgp3rIBzabNNAGzQ3 IwE2+iANEkDvQH33W1d0LzqLdho8pR4yYP28O6Ax+w2FEJUr9RKFbL1+7z/3qKDG9cbOLDbN9UZR HnqWfs/urApLVNERvqRfrRa8aq1oBRNynDDdbcgl1NWAVj+L3y5SIOIF/HH++z1fL7IjHJBxDHnl lttesCjfBDsH7L345BLzQS6p9XvM8mvqs2mb9ZWyP22Coorveh3OR1au32PY+j7m6J+nIoICJmmZ spDMvKQL2UKqPKcMP7ced+Y0sKr0hheXdhXKbg9mzwVHHbtBIvRugtnauI+cMS6aG61IFqh/Gpei U6oIQfftUI+4APx5iG/SwLXwwKQG1+KeLKBRxxtt+HdOTu2/qt3fYtqJzopeKf9KsRaCzoYQmGr6 uQAUManl8GzefQS/fBnfxvOFy0WKMH6+0ycQkcCdLQS5znXixwK3fq+s5mhM/mVeRfxDSlJImFrf KTOZsRc5gKzmV2duVwbTxkN8qErfKpdUwQGArza2/bXrR4nCXM5H6joWKK+h+YGuhMtHRfPxGlm+ bm2QZpq3Wk1vclchq+D8wwRzbed4Cu7v5K8oKjwZsd5GXYkNky5YaRI5GjtJiWZU47+XLHGUrrg8 gFSe6TNqsHy660QhisvJKvuHlFTdsSWI9H7JStznUo6vqP95r8wyAENLELXAf8LzsKocsoPFSXlZ vW5uBXCtPONwTIizpcVY1vrJGmRgOIXDR9f4pW8/c3phlybZJyYOzfEhYHmw6Qs1+lU1fGSQmGwX xocIU1htSzMouCpg6CBLcLNlEICgYYJWdQMOxszVxG6G7mh6XFbyrpLGjcb02+U91RkJ7F9S0kp6 I6xiPJpcKGwLwXXkvwUMlojuBoNkW/iekpoyqboewBin2dNFtCIizv8AErVQV3rvBbvr74qYVSsI oETpHwepoi+C6Ngu9zRCcDILuRnRwugQ1ysjwJHbVYtTZBOS4IUi8xARQJiqoqRavFLSnOfRJoRn qb3rUdXvsSbgMxqb2H3gL59YvLH/9I49Lso9ZYvJgEcYyVxtMiO8Uwlyq4IWe6XuBTySd3pF75Gq riEj8MTX180unvtKvmnPHFPXuNyiOk1pCfafVZ1p2Dbc6fibzD1JXDHO2jBhGUzXlOaZwt02+LOX lqcZlowqS7iMmafqVobhED+ff1J30SZ1Dh0jOw89yJS9SL968iek54W/cZ5h4fjlfqG/q/UjHcRa 5mOP4lOfemCHC3/RuJ93oD/oJZ/0L/AL6GGRIJDPghVq1HXSbXiu4aAdGkCjwvB3F2C+0Lv2Jdz0 YNJ4KtplcWfdNDnTGFR5wDVuZdIJLOZR7CQx5dI+kCfXLm9cHhSYVjEoZQs0fcKD5QZEZsZfOufl yWjH+28vVAj4w2Qwpbi4dwIVd5sOXaiw+ozem/vz5HrrJNhyEMjGwi7FIqS6V4Gd0cqvfmQ2weY9 2poUl9UVjaK5JfLonpyI0NmBfTfiWipXh9/dxJqSuUikAFJzWIIOfaO5io+AgKbZ20v1DlyX/83q WxWAsJuFl6rLpbTEzOToOqVdeEYUhSjkeh+d+rc3V0gaSec9cl6rvLNZ5DJt7CQiJ6rkbvj2WJ4Y 6Cs/GcpWha5KHeE3lS65dzKb39ZudITtUsyW6Ehw4FMGKp0G5pc8dxOjZBHpqUgooPirC2pBAvfw 9TmLr5iVZSSXJGk7r9PwA8uRmgyl/esuXU73/qRop9MwQ0tTBnbj7n7GDU04mqUgkCtDw6Mg4Qzl swot5fweUUbRKGgYWymLZeUduwXsZECiVItHKex0F9vK3qvgh0MFGPbxybw3hs7NUquS3+sU33f4 7fS2f3qmAyLwG+Z5OPZ/FulDlK3uO+J5dH9+C8xUTiLYrIW1/EbHjeHcD4TAJ0EWOad3v+L2r1TT rgrx2iLEJoRzk4MKzB9SHxrR/vUrQ7k+6zlbOvZ+WdTZDB4v75SfNqhQXPLanPcelXuTQ6GBShvp JxxnKI2VOB+G8lVDkc3BmPixzHzBqtKeqNagWU4rE8XRK347t17fzZZODtmWTAM1i4Nvy3TuifGq HVOTWIDLonlOaZGEEymAUoHIV6/XqmVl4/HVRGoHWdTMnlRYEsdEFAB7iQiKD3rACQXZ18eQVoug F78sY3Qht+eSWHREd8OEypt510IzJYCTkuLJtIN4wl6sDiAm3ulV8frYOQES9UZVXdd1h+brmR4R PI8voz9GQaii37pli0Bvy7Mw33FUkBN9aP2+p806+6B+uY4Ig2ljG8rd2X3mVgcQZZqCsc6dGjY+ UyRYf9GvvOpYIJB88SilGWlmioIaRND9rJ9amlakDGvp4nD3sY/FyHrRCLrHZkk5WTNwZjdLAuGo olUZM3SnA/DLFGSL+v1oJwi9WgK7oCil/z15olcVf+gux42cp0yCiClLV4bi5SR5nYME4EcfCeOs oWkxwG8M0IveO447jL1oexaHCCGtsXwbQ50pdNdFTtLQzXhSN27fGXJY5nqrlx7af5PTFQ/tE/GE nFXWpQuHuog+sh5CYceCsflFmYJhEMT7IEx0/HQtbYMzxDKmql7jpOtUqU73UpYZmlFmzB+L7UOg zz9YZddgP6LHj57sorTbD+AHhkT/QE7GmFyqtjGDNZkO3NBWJLAEjmkP5tmlDPBh6JMoHUt81HsX XZ9Km2hgtIdkh4A11kJFKe9WsSsRjLTTnxTJHHeIC14KvEzv4oL3SVitYrv/yCdUtSqThxUyXzQv WNweNmHcbnXNtMpxEucyhcmAM6QMiIA5ecfkF5uyK6VcCHRCDeOG+/o0UlD3ShoGjnTmJitK594t oiaUFFuDjhPUORahvczjRaoahWQ/5X8SRRoXwvUr+6Pn86KYBk1Dmv+iEAabWpcXLx5xQbcuBZsD nMvr41bhrCAPOCF/+0nb79LG+MmOeB2Y+zOjLH5uuEZpnRB8yliLfTv3Dc1Drde2ncIkkKjw/F3X K47u+TnGcYH/aMVJAekUXgK5vbTtszmwp/uKP8zcDsX3GRSZsQA5uxXhB7I0C8BUdBNev24f6vVM FsHPxnKLH+sySt1C7EmFcvTb3vSllf5xJVB3sf6PnDoP6q62R9qOKUMcwtKn7kawUjDrf1u/ztTV J9/KaoYNaD151elXza79wkbObPkLvfhIq0ApCPwLh0JNGnKF7oVkD5ogz3DGfEq1cUjr7TAogZgU twZeQoRBGCFZWXUpOgM0mkRorV7xv0ADFLOoymJaRGXVq8LUi+Nt4wZbdVDnnj8Y+VusSclzI4Nt Na4JSW54cTtjsD5+Wo5ghp466RBa4I99gaa0HYqvOsuLA4RjeMde1B4L/EMQ8ksZaucHnRuNQdZH 3bpIvJygYOvcbrF2VaqiOWvdqdSuaHPr9E5IrY3E0Cc9leu518VUz8E8DDMfW18CFeT3BIiAoWcw eEcBwspuUPN0lbUcywtIP2Z5+HDngoY3qjofKXTrim//lvJiy+5IwyBIKfl5wqAXDfRFNzZCeQph DXejNO7MaYt/qz6Cqjl6WRsGZqZRNaBQc/zexWR/5KEa9ibErtadi9w7e/Tq+biqoHGxlwBPgg2z ym3NXZuDnwnnlsStNk4/VzCF8+/VVDToz5N+Y6HI5QeW8+FWPmzQ8VxnyCx9ZyWe8S9zXADn0yzt bqky4pYZ8AzwFG1V09EZ2luxmj/+v7tts92FShxmGPhL2y7WzB7ih7hDESFA0ETtsAfemhAedIhw h2vqn4cOE67g5AHdpCkwnWOwEW87jKjDNAwIjPlM9tG2bAZDIvxPprWIaeZYqH0jeBzqvsoqKOV8 ATqLIXItNrXhOFVPiMovxW57HqQcQh3sbVYEpSCnECBketk5zPiURy3I+plfESiL08B3y6l1bnIe Nn+FhKiL6d9aQk3OZUyGU3MULX9d5LW9HhxVN3TuwLBKRN4TVbWniojhB+epgOu/2761y4SEmacf FKxaHXolc8qasZc45z1GNIi7BtyJnc7blTVbY8nfoXkasEYpyo7ZrDFcxVleayKkIgcZhqowi9wp oLOYYFZ9yuMIxv7zFH5M9ztx5Ui30sZra2GdDNFCRyWJcTn5a5gxeVfIqg127hEry3zKeZnQWG74 wr8msL9OpqrpBAHxSQQRXwPQvoRflKknf7wtcX5zQ71+DDv8EIiqS3ArHoaeDEFuD3ZYcKU23m1e si196TTx3hDxHHDbdZ3pUYxBGdk/4aefjRQC+igTeVOmDO6T6Y4JEvn6xxarwz1ubVR2VHy4U0Yd /+3LAe8ZsMmrpNmLs0skJsRJZdBBurTEi4+E9kBJBJTkE5CvesQXn+4Hd6MPZm4O6bll/qsgHt6/ q3ljKBf9Fy0wejABMzCix/LtUlpdK2oH88yvtXVajx6lgy8VI6eHQsAgegq6ptWu+VIeraftzbW7 qie0qPlBLJbWRqj0fp1gqgvcyuF5cMWIrV+1vcqpJ17XsUP38RC+d5cXP1oJO8tFNB9rVOqM4ITa 2Fa+2NKQnqeLGfu+zrntKGtm6QLXGbMeS/bhmex/bqTv1RmeFmW5G92k0jR6agXSBb1Pse33z82p V9nKYB7fAsj6PCiq4dBuzYtqzhA3TQojJ2+b59pvc1rqqr26QH1LP10qf7oIzEpqHRBSTljtI7YQ uvFUl0EfeeNiSnuQenxjeZGORP5BXDUJrNS1Ps9SMvoWK5pWe83fuG6ddZyRjm8+mmYHfpw9Sqqe iv0h+zPnW0M7KrS2vXpMi15ZeZQ3CTyIJr2/V99PvELn61fIGgpoEJSt/JWGLvkWweOZjobXsudV kWdjoKlnZCGfQT93lZaamZVhqECv5YXfrSJ4pnfBO6lWfcKq1kaal1i/h1Jx9ZGgdJs+4NbqiIZb mCNoWGvs0Q7BzE4TdJo33JsuMu7l/b/YC7/nWDtTaMJ/3vLfO7VAO2k7R8hkd+bSEt7nu7PQQBLM adRu/ABuoo/0SwX81xHjFKA8WhX/Nw5r1YTx4TNCqJ3yOQ7wyVayHznVgVucyqVIvNm7bSakQsnP 0E0/oQogBJ7tYwBmYArKNbWQWauuR8XepCLLoQMjntlNhrY449LDzbdJw4K6+VEzCKWZFixKQJnL gt3jCQ1AY6UFjKB4tAFJ8uyBn8OmZ2+c2i/lkonFmz10xi1YRicL8blCisZbWmfV7iMx/nxIKRwD 4/g6D5Hy6PFOVr3cMU6CtTQEooWD5ZoPhYLnjntCW7wS1KT3YfBLx8xSWGTNpjq3ayrFA3On5SP/ MuII2EjI0v4zdzdR80gW0gB+Xn1ctShv43bxD1qE02le9PPjvZFv9p+XdyG9+dQpvXDUOyGbDq+q 6XurmvcSJjQxs54hSA1ZyzFwDzekdejvXTqF/p8Ai8pOz0SyQ0KNKQtnDGF01W9sUHte1RQJ+7Yt +AkVusOAYfCUhTKzEvLr14Hkoe1YV4oYPBfhWBtreaIwTLhc9TXRDSMeJAIub2BOCIngm2z6s9QS s+GIhTCOJqrkP5WItwNIlXa8wh6TqbZZSMgMtI3HzLoa7vw3xsCBkX21sQo/gFdDnRMxhF1Dkd3w W+6RYQhaBAKWigd25cPPtATGe0KNmqs+0x42OnGzCggsiI/ZcjHhVOwUf4orTSaLI2JrrfcnomjP Lt0MqZbj6xauda3Uh2a5fCsHBB6KSvdc8CEof/KRHZUF4M6hrSJuUF/3DiuZHdXGrXtjLRt1oDLp 243UKYvyMxApYESbwAxuRM/jVYX8OFWHIhUcwhb0UrRqn3UQ6lzs31nleDi7fJ4m4/GrzUObxUhm l3WjliGFMsjKE1XMT13ZAiVTPG6aINGHPs41PW5hOM+zyoVPQYqVZyC7oLjBOa4/t1OgZP7Lk/o6 OKEbr+UpZZlWV8h8oQGIUPkVICQdJQfaaSVUP/yLYyb/zqhmQmH3SQdlgI7FWmHXxvBBn/O5Iixq 49VXU5IBpvlMEelOekVNU87xBKR91COd9tfRPN14uJsc8x2MPaQ/CqzyIVmERThyomlXJzWictmy 8cLRt3luRyckFlNbv69vBEnYCgEalFf2BW250ib+Gbw9e6MJJ6f+0AYGLh+frhKe3niDNFy2hqtn 60UXfeBElBKSaKT+T8HfgfsbjEJtMczZ2YzlseTheM9xbpSgNl8SVHdS0IcUqECbntIKPFWWs1TJ ZJeqkhRt1LEXh6MoJMPUs9+B+dUHAGfAVxZ8MviKKLGtMAr9trUKv+U0ykaPN8v5aZ9tUhi7sNYE 01bby//L5f/wNqAgWlVBYnDuCeSYJsb9aPgcDrBkuNImGddCB7JudUslMZZQPqoJ/Wun43rv3Nw9 4ZjMLr7JMPZZmDTztMSV/XcjH6RbTlc0yiHIqNrWf0QuMEcfT7/XP1xwgqLc6YJ/Uu5lLdwg5aVO 1WhfheV325jyl6ElRxdbav5XzTKRleI386HISwookImGO/gJZHJNYA784snn3hU1R9E0SXUGYFBR 8btu61nV079KSECA4FL+z+LTbTfEMes9B0WU3ihb8vw/YhAEs4tkjO6jO9724k6xaZxtTJxDN8me /oBsnn88NJ2MKPyq5B5V/nLd3EwYWEDOJrntB/pmRsk8eHghetkLlnpz6KSmuWBHgVxHH62mxJv7 M3E0dUP9a34HJErqBH0ngcxSOEBnPiZuJiZAiSuJ1g1m4PmaptYJbh8icRaYqY4Ey6VYad5DxGvF jwDSYFTnQwsILtgfvy0ucxWHdrBpfiGZ913BtxlGt7H8yYqQzzmFIAQP2RFVE7gqjuIkU2Vj8D+/ 68L9K7Q3ZbxktBIYkKYUHHv/8E17sp+OGmT7/mv56Q6oSW6GqcbZZtkSp/pAnHMZz+T8zZpP18tH t9Th92KLbxtwDUIs6/pNS1ky7OAGyWHm2OaapgFV/B6Xzu+mSHDgRzeYyhx2LR1S7s3ZGbeOuiaN 0bcNzzvcV00UCEdEFZPqGfsMVh187DyUz/+juJ4eoCdvo2WcRnHgBG/kEmODx9PnBiXDE/rcGlu/ dPOiRerOCrYpnopXQ/GB7keCfx/E5cIjsB/e8STKQsyFB1/fGdrhM/64JcbUR5m58pDEI/vs9/hL NyUx1A3pjVTmWnRjkzD2lKHkja2rt3aUmW7Plr2tw5EweZBxF1Wiv0Gj3cGtFzbf/4v1G0IdHAbK TlX1gtjmKQFk/AjI4XHNexSvjWlxWqkMm4OQ3nWaiunIglX3NrT4FXnYwUUdYkHtBohRrbipmTg7 HbuxBpgBJ2aGp+udI573cParANVPCd/d2DC0ou6IVeCxXKnu26CvHpk5EsUMDoJUmU0nMAXSK1uo CignYh5H1TROmk8uBRp6uo+tUKy+g4b77/KKmSg25P1NeZ+CMo1BQbf9Dr09M/CKK8bb267njLv/ QUWY9viSNGotgdXw7VTrNukaNN4n6UsBB1n0bsMPaJ/XDVCOU7j10BDOgM1106HQVL8Pmh7fljT9 j35FY+hYufI6goKPNMESQHczxnRflj1+/CKwXdyyihFIV0nh/wBsNrp8BvZSdPXWwPVm3whlTogr r3lax54DtSYZa/jv+2c7fhttmoz5OztkfM+jWAIW0XVqEFt1G01AzdHaVqFquOxQHJmLMj8A5p5N s96yhwg8UBl9lLiJ0+LynWzqj81bCnmfG7/Dvucmq3aNiK2+TvRbrNrLOomP+7NvPE3cUNQw6Yhn m4xtCZLGjh9bHIeIhnR48jordNwGj/XQkozL5aV0YElS5hoUZE9BzWCObfBZd8CIV59ZZL48MQQb kAmD8XTVZEwx//7a6Ak2wKTa0qWQeIUTD6iH4tTf0qw/DuETf/YKwzL0Di6UAuKRse8POsRSwK4J 9MHdbP8V7XODCsmpZ8a+bkpLnnpcvOI8unROPEeGU4PvwYSclyZq6VWNmPD93YqjfUqAQi0Xvrl7 W/g+p18cT57x4/2sMGOA8vb9hlKmCKKPJJ7ehMa5i8bSiovxmL8q9DSPWsLv8yapLkvbWhN19ZjU Qs6pXCqOLxpFLeQYKLWMBoi9sk/mC0ZW17NqyunAPhCrevOPSJW26g4RvLL1pg7VrXCX56UgUnZ+ ejfrcgcdcCLq8eArhh5pyeVf97WbKnlxSNRU1ZVNYxKSFdaO0aeJpzEpmR7DjnqV9bXZ9Seo+AdJ HoTk4r2SSHVHkpQ5jrIWgd9aBdsqTYT9C8/SrKxchqmge/GvYM4zwTtq9lYCr9zd+/F1tfUGdrRu be6hwxpmwLFSluAvoLiTkZ2OIIUw3g9EQO8EfBLYIndjkvVJu/gCIVOMXePb9OR86WCgbmU1BmdH hXfCplgptbDl2kfkR/0V6GXyQqhwpTsk1piNS1/07kmi9VuYQOfzF4xjEwsFx7olPpFRyAljUmPK 7yyXG5NLi6XSnslQLuoqLnoFwhjahdD1ISTc+zbadcjkCJVSBKlCNWE8W9+2b+Erlclt/s1w/M0R Fa/6EVjSKnQ+uxdC1N2/BCjPShw9XfsEoS1SMG3pyQP06wX0DCCEHz6CaX4gy35eJYbifPS7cjow fx3h/L1epARh3qx8ywp2pU81no8shrHgdQQmDoHKCZ6Pfp8g58I/Pa8INf4T9sAQYfPlV/yKPr94 dxz1p1GTmYHeQQmZ3P4+ETAcQNOF87YEkj8O2d0hNexMS8d1Ss45CYRqOrURXFI/j9gHvdqDzcuw xqeq+bZJASS9veHQA/kIqYHZ5+FlPn3qPbPQRbyL5ElCtReWuWEQMq4KiHFgZpA5moejs8OUkoWG zREGt4a25jWm+uMqVfIXGe6Wrc91P/JEl5xenyaGT8vcLJETzyAGmSFDNUapHC4+bcZpJlOsu0c1 MHz+LkKIsmLpYElFqEsLQWKKNgRovdZbigW1CZqOsYagnTlA3/cdkxQz4zBIus+OTy3CP9hzZ2OQ aZX2t6RWcHwy+Wm9tomq+ONKPEtCuUjpktFqUTYxJn5Y1jbebsUbMQipSRP0BkhRKtMRpF696gHW 7XDkkVdfvVPnYeNkdZ34gcJCuBEPcrdM8J6E4EWWEdFlGNz34r8YTqeKfRUx3ctHT4/wTeTqs6fn ERi2ww80YKOJTsjOcfMPbLSlOHOM5EHD9yDl9IPeDkzD6lBnvW495hGIccRwq8q0Jk15ZIXb4HGJ TSVK2MPcHa8cfVpyD8oxKXohnmFKCzq0F6avYxnoNzxaqGWm1wcYqj8pCMTqCVd94t68c0zPqlWP uXE/lRV3sER66+iuWMwQXarOdZv5MeZELN1JD9hgL9cpiwpgNpC0xyqysy53WBVZoIadygW1/xMA AhQ+foHl6DA8xK+E5ZOIk86ykepd86SRfA6/pkZ1acPY6gIzjMYb3snCJXepVM3X4y1I0xDpSZMr gR29xTC6nC1FrK9X46Fqgui1aO4XXTN9CUOKEiQZojUAlye9MjLenFMLRsbMqEqrjZzQlMHCLmsG YXO/NS94lFyWZZI9Tp9Gvvd5MmKEvI++VzreY2G67QGqfYdiLA0p1K2rkwtZ5A6tjhxa1zAGz5yS 6o6rvUHa6J+8MedtKvYgnHL063IW3G42defKIvpmEiHX5zxbbsjGjXzD8C+AlCO0Eol1AHo0g3E9 k9axA0cPPck0zhdjSeVTOBZVHeXCGsYnOUMmNqRiM1MKJATobipcTlqmp70Agn6oeTF6ubKMMlr6 DlOe9oouSPjSBF73vqOdBXhEISgkh0U4PGZUJumEECDQYpS/X35Av3PpeZDjnd+aL9c+/2bzI6Hf aV2m2TMLBLwB0ZZBPnr4J9KRM0Hp5rD09XXCcuIz69xrtvf8UEdvbVGYgHWI0WcxUVHAWdKNflOy AcHC8AhD2DvNk6tIm1bIkrwi6tJ8swRKPwwjRZgF+9uAfuNTZfJOf+3YLzRIF6BhKUktzvvTgEpu idGya58GTX4g6yJORFQ3bdazpLe6hysRb04a8/UIhTTQyABUwInnd9KsI0Y7ic5UWY3oQAYgEP4J wvxqFeN999J9m3Bqu/epF+F6b52BQWcKWVt5xboJ5+Jk2/aJFBdDDvd6L+3b9Y7NiEHGDpL21BL3 4xjp6ozJ2In1URPCLwF/ujEzDaRNLTrtAwF83wgrCX3AsQwy7/V3JwmOnpTlpft9xx6AQ2MsaXTZ XZgB7XOIrxDCx27mOWXb9Z2gn7nkYovXDfQ0UgXqk37wS36AwAoRDBrl+JidIJ1wRaxtxAdngInC XURh2pgREFCK6ugu+RTqjFu8pBN8SA7AChqEfKSILluD8zofyaXcjxMKGF+lWMEzoyP7ue85oKM3 SSQXHdDG1Rd0BP7Jael5eWkvpn52SQIpql3cDaFW7Qwq1zQdz81efUYltupIPTII4CPRqKp64Q== `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 23360) `protect data_block nBZ1vLOKKFLxq/wFdE7anpwE7jHXaNkfMzNsf8hTMAqXri92qUV62Nhjw6GTGZ0Ddy9B2yl5tUH2 r91Gqs+eEflEVxhGe9+HEyTCfT1gLr0zp+dTzvfLzvMQfsYorKml4bc15vRcKRVTLsXu9+IyvzLf TX7agGGGn4NhfB5E7u8WZMJsKXIrORfsHABmPUAOGvEeVWE/bFzfFOz4EM4vV+wz1gaZTJvIkcdP CgGqqWULbUMuTUxkfaClj3pu3XNlB06shLqaaP0nQBnKvO40W14J52AEwMLHMBErSufy0fBxuwgG Dipvk+BcYLRhlKZNYomckAG/hPZeJGuxy2Yk6C+qNg5FUMMVB44Evc1k90j73RGwWPlfeEV/r6m4 Kngga0RvshaXMsSxSms0ksYO6aZQyKeK8a2l2OqWH9TzBGxrfjGfpdJYUk+wVUmSP1IkfqL6AePm BQk9jH6g3hQ4wBQbSpexMeKCfritybbTJdI86DWGoX1b7FagGyq3MZlhcWUlF/VJKqZ08fgbV58m 7yiAw2kvxUJxck0cF/ExRiVGjP7eR+yYzWXibkF8jTD75N1bmBdvK//SbfB+K/L6PKmM8s3bceG1 KkVQS9WnobJmYD35ZawlJC8siEd/fuxMxWWiJKCkdJOjHek8J7D89gqr/bFuw0j4+zps6ECpDUP4 mb6Hzaj/AIn8Xae/cNvyRZpfCCT7NjPnpOE0IH9SIYGASgmXS4jWvnEsIDBecB5JA6PUbY+Nzj59 t8HGKRKB/ugcDMEiZpvVN0bii9vdQxskDAm3GkE9HUszF62N4GjV8Sk2D5iyhLcWVAOVV2DtTx3R Jq5zFR11i+zfh22po7VYKkM9anoJuv4nS3L66HNOD6hYVm8IoCsgpXK7C/gM1RnK/eVLsQEw47cH UQgujCeK53k188nokCFsoMmlJpl445mBqaALGlhmvkKqqY/NoaUSUuZH+kaO1Ikt2PFjubNuRRpb nHbfxj+K5FqUuv5ksq4m0FhWel26vPeXFGgNK0Tvtys+XbN/+HG794sLzs+VTYQAhNslTBpw4Xgq ArvcDyYv2QOhlD6ZSd5TDjP+kTrygjoRXR48F51NKY26lBuGR5fWEi77tuqceL+rGs4wAt2nqPW3 zgMBh7mdspwox0uOu0g9oqMfqOHZEgZ7ej2NCLQlwCR0QV+5AhTyFgdZEiqXgxpkBX4G3BZRXe5Y TF83aLB2hzU0RjGFENDu5qBQaQzlw/FYXSRhlxaNwQLzzkKqfhHJ4XQsFfzn6HqQuEtWM+8gfU0/ hGdDCVUd3NnhRC+AOdxqq/d0pacOCmly8JonTyPWsQRc9hpJaVyVeLA/LSkCACLUFFZw9MegoJuf 5g/i9BwHeImI97IvnwEdm+UUS6qHTv6DLTUtqpb+kl+X258fotGVR5BfgBQ5baxfgO6OQ97QTROF 28VFzkZ4FYXOcL5No444Zrj4CU05yU2Px8xbqLHsWa8EBl1OINtFFTUTtjYhMa5kNSjt26RnZgeB oZjxymgf0xD44RhW7HbBVWING0/LMlZ3XdmLiSsoNiPQPXUjYAVPfx1vQQ+aLR88oWmpwhhf++lx TXJl3DCSdV2mKX8VPIUr2j80YBHZ1SX52o5fuNXuif2vRLPFFFvoP/0lT633ULGfLVKjk5YLiCWW zNr9thhBXvymzlK6WzuPhb5uJsZhEWJ6+mR4qxZr1X9qMXfEt3huG4NqW0xudv6GXy7KlKKAuITQ ed6I+hoULN5V0s9+HvWXX353bbQFUAhvI6o18A/LxghtsXyLbqAvJDqZySAoGcWnH0SLAiswkHzd Fc2zo+FYtfOZLrnji3ueuH+WRZ1DWEgJeXU5yrYxKDshg1L75d+R9kX84zCTyb3CTfa+UmWk5ofy EGTx92OMkLr/J5Bnun36V15cQkNp4J0wLS7GPFwEZARynJcfybuB23TE9xSwxVQuB46rLgiyGGMb KU9MGKsEvCtinUBw/CLikf6mdk8rAEGM87hwXN6uraXz6RKXW1rd3g41e5WzxxcKjp6JXq48yzp2 fOjbPEvarLXHIVpOzBgSsRr9GbciaBZ+LcCI0U9QGLcBPkVd+cpZLcKQ6rokKtYeJrSKqZLsMvFz r7S55+kOLo+9OYgZghFtEaIgbGuk5l2VVX7m8moiALUUozK+1pWXyXYaow0Ycv5wjdMmSeVYUuGG eDMF5/J/e9/c7D/bRb6hTw8suacSe09ePPZXEQlKZdBYHiqr2WAC39zRy3jFQ+9cPwf4WzFPIBkK QV9vgjtpzMwP6Zij7GtEZwCeVb5D99XJ4bfztFOcGPMrCrmjSce6itMW9n+prgnzjjDJBDsGbmoe 0LB/VyDLDnufGF1yKXu+o3kE7WM9SPPshd6YjReKm0xdjMwwER3T8TfCn3D8NND/BWSN87594OE+ 9S0yh36+crxMCwtzvN0vHYJVHy1WTXIPf+mOdgvUPLWyNwLKf5XkFKOsf76mP4XaIWNuTIUP6X+O LwwRktqbJYGqf1cCi+fTaIoBs4sq4wDDlJ0pEQ9sxvoy64p0aQnj0rODONDbwOjzZrEhP+Pl/U3o j7KsGw7Vdh7n5UjUJkOjXLg926Xwke7xA3/XYEruZjzR30lHl0BiILU2/RZ6xVJMz2ZdcwqIHxm1 /oJJPc8A9+waGHOBMcPbFFPaS5gGAZb/Tx1ueacMuNMyDc7HPFaqnBHbPYgr49b8eKPFYUEehNAy Ork8qWh27kc1KP8cejMt81ZTATXCsKLf/MxDvQMNog/hvKlpkASAHv/IuFD1zac4xskXei16+EMl m+fhwp5pF1lZp5gp1OR58dLHVkRklElEdGlLdDa8j9annFWS3CVfA9TzSIrY/3QUhZyWWKMf7/Gh N1MstdiGvN7OGbwpuCHafTXB/TJAqNFq24+hx5y/fIVo+2UHT3sAabK5jLjguTQF5Nz7EU0RCEeI q2n6soNt/ViY5bpNmL1v0s5f7jy0yZz/DDiOZmpMxiHf1M7t7OUrU8mG6JVef8V6ySXM2HviV95Y 6+M46uxcihKcvhpluH7JT3LRxsrR4dHlWajTjGbnM9HP/ekfaM4eFSGIvwBLmhJIu16cBgPRsdaW gtZZytAjIccu73OLU/T66/fGTJjdBUJPnaZHIFwJJFj2CTfTUirXFwfdQdXIqoCyt61l/JkXK36u L8kwlS72aGDdK3HDYBDWklH23tUhNN/Q92hEfg+NtsqfhuMuSF/wErjSEnEc4cvugjTC0bgt9atM 7D1/sodF0SMrPY7gltVv0i38iovx+a3pp+QdAxcpEqIZCdrBUXvS/oSPPE7YuR8vdqLHnSSCWLaM hQEGc5GbDDdYlElMjX9C+ShDPWoH1GdvvMt7Sk3riin3zbdmKEtvio6QpClM0Gk/ow1rqIaGOv3G YcE91v3Keik9R8cY3b3Y+M8qV+93E1k6EZMDUbNf8rZKmjbCDHhdAK+xiSRiQkH1xMhHKWmiDm5A le2qHWs+BtRyuvPyEjAVuovIQWbC+WnPVj5HF7XxWmHJcgLRT/bpOxwKq/IUrZ+HkKurc53uSz3V 1JCgUvYbio2eVL1oxeN2kPR5oJezOTb0STwCCHA8iziqMzJDUIC9OsFyesjoIkT/xBsTdFVrXlsm /mLsd1pr4prBYZKpb4ejyQd0bnP+9j3z0TotzmupZ+7/pUVL4NzXVXtcOoBOUnBCoRHAg7DCCr5f j3mgVZgzdxognpY3GiVCCQnzaf6KOt2yu/2d9Y5MqVDv7J7EnFnnYmE2ZeQ3x6FeS8bsaoppS2KU c/IopRnHtYf2BS1BlvNpu3qI/sbNVZz9/p1OuGGa9ImXlkkF9sRittfYG/U0HBrH3phAmR+9Zb7p 4xkvCMC7SN0A0ka6K6rwcevNMI1d80KZMKszogS6ZWrqS7GGwNJ1fEB+vzgO0tId29xdSPcecW3K OGeaj7Tq3OIUKcDwrYAHbxxnFOS7+vnQ7sBk/glAwAEOUgiUZJrivyNA0lXOixXCHTbWhk7bPJGo rEPHnbbPeDBZeTvQUaem6cb5Mp23uoSB06UA8jT0C5FXX9lp8zuaESBeEn1Jogl/bJTUIeiRAt11 aqmgqv79TcOmS2SS/6urbJOyYH3v5f12ve28pXiNMdZbNnn8yH53mvkYEs35wmf8roCj0j4vWwr/ 1tMY64ipU9dgWYgWRmlVLyutBdojkALkQYMDYcxHEnsqrYOzL0itNadxEyKuIJsZsIzh3kZfRndF OdDeHVLsicnYXXWESNiXi+rYTeG8cz+518YwwRIIlel5TNOSPEjuZa6Rvlbh1+hjhdj3IT0B+rVS Pi0fY/R1XHsL2j/fQwbKJNRtn8l0Fc5kOxjZu1yuv7oTab/rEHxxAhVKlZU02SJM+gm6yoOvxDmO TJdZZFffAGKUsQYwt43cuph6v6SiQYHbY+ytwnN3La/EqQHowEwf2Epzq+f4ordo1cWqaM+0jyOk lzdmtcPtXjZOqyTqerNf9CPnROViRvvZeRsti23bWHhCHOr8Aq8KQmR8woIKfReOiDMCGMkrn1Or zIX40S+TLGogVYFOdEPeIpl/nrfSLDPc2q+ttZ/JG7eFGwOAcO5AVcWrefSpntRSm0VG8XJsZ55T te+iqbs1CE/WQIqVfmFzovod7PEFTdgO9jxMn1JlvFSsutEnAKV1uv0zSH248HDsOWT81CIZRK+L Fhb/nVrcCSf0UGCQMPrKtLL3co7Fgt7/DEeUJ0x9vo3kZMZ/I0g5C4YvMIa6FJB2H2OmT4UQuFJ8 MEP/d9lhjB0ZFVOer6VZNbzoWzzUY2EBwb1uci9agS8c9Oc27SoAhlTxaF33mgnV92es1/0+rF73 ehkd+6LyL6K+OqtVQmwKyPtWhXqQqFLrhePwpk/HaUn6ii3ixymSmMGraDLSEWXUioJwBt0asD0K 3K7rlQM5xNAeqneEvQ637Pl6LvrYauYVpeYWrseoVvMQViIoV8cYKHon4ccvsu7OtwCdh7p3+WMr RWcZ9XKOid7JS2rmWUX+jQ/4fatDn7hKH3imuky7YVuRpRqs9lmL2V75SfhMB/pM5pWCZm4/zMI/ QLlh7P/m34Yqmw/Er5h4y4UMNliGn7UJdDYXc9FRkf6x6k1TNjGr1/KP60FzPWjKyeqndlfNzSIN LSTXPthAJ+vAkgTNK0Yy9J70eDT9sC64NHM2ZC/jlV6OpcnUQe/9koW/rt5EfhUZZWKSoAICrz6d 2vu4q30O2kLybyMhqTC3R90uPoekYejbxgeli0dOrGv0QSuHXDsqi9DaN+Ht1jmjidtSfzgSCaFK tzpj76FOoIVpSjccJygTHDWItGlC+RBOwTZ3AiUFORAmvtobvYx7gkMfAEKuEDuN2JfLd2h/Rv1B maLwFFqAsXUcQSRltUpq+mqhQUmw7b+f4x843yXPnyAZJvWy1+fOlaAYcL7/3rt+VMKVnZjBMSUO EjnOuXnuiZCVhLdGYc8Y23MzD/oxy9uSL8qheDkoQg/dXRMATWFv5z0bLDPUgDsxuEnIa486lBZv 9PesL/lRDzyitmc3/Vap8LaFbWvgEpnRkml6In5Hdnkz1GoOoZZjvlpG2x6AFjzVE6Tpumszs5hh lErcjVERh1cMtE6yipR6FAc/UV7JRy1LSqsP0qLEL2A/5Cp5scxbyt7K5TBBJXzcdpsEuMMWQWvV hxbt5U6OFmt+n7cIN0I2z83TiedjU/MilCPNFpAjTS+yFywSkviBm16jTVe9xbVgORx17YXj9t3z 9DbgBa9T0oS8J8nJ1cpDPAmQL/0tnC7zTus//1rKty92JJ7dohuD4S98w21bEVpg2crJbE8aDd1k ns3EW9E4qntxqwtJzwXPsiMX2myg9QnBOadDdz5UTRlyc5HWkaafUEu1ubmbu0y1OvfR87mMaurk 3r0/IpiLGTkMKdnJEOQj6nymcrt08jY2OY5fQA4ufP4ZGeQJ1QWTmt3pNvgYQavgQ6DGqZAu384f JnQ939fJYUpazuqz+DHVP3IB02a45MdbkGetRWGBedquPwf1sU2nzms3CDEkKyuwAnHweFwhgmwL pSx9Rg2Ngi9PNKSGAuHPrJot448qwDmlMmDRIMNAmS3DmPQAQ0lVe78RM+S5k+isNWwq/vld3ROD RLC8t9tLoZd67QFtGoP3hHTAtxADAIYofSjTfG9CvdpOoJxpfdS57/A6JdH0j1crzJk7cE002JAx O/7o09RRVHqdBuXVS7NSHm6e+4+0uezR2L+5pN+EGkSFN+PHWTCGyDznVA7zZoa8lrZtKaCRXMUL AHUrJ2bZvM9dBn3enOMFplUQ5W7vmvdJJCSa0AtnYnSWiYqj24FWTOmw2maSnfvAMufPP2uTC8Nx VRdiCiodYMWpayl6ga+zuP4IGN6olzRpHW2oSfpS54jEV8erG1DZwt+PoV/ocKupxy5+Zswz31xc Nz3lXYjpyeZHdQsG6g4g5SosC4F79w1slu9hrSTA+TCEMX4k41HOVnG3ER7y8GnZ/ZwddXM7YyNL a2q6OZWORFMxH/1KsSHkvoKUd5slHphv+ps9QNYnZHxe0gIA2x0cbu6bJo6n70fLIuTe8Hy7O6HA jJglvQ3SR2qcqhxG8GR/BD7309X87xjUHqkX0tqukofOuUYKrsWs84Ta0qYau3qowMys/id9aDmr ZD960rhKSq6xSTAZqtUr2CEBkABDwMI3p0+8BZJ/7xl0MvOUztdUjNo5S9kITM+6ilkRbqmvrpPx Dq3tYw+d2YIcGeHHF1pGH2YRtY/2ghUdaoRXYvhh0w4hhb0LNP9NtJ/w1OsgnTcRqFbTM+VoHTSi 2pqysrertSq87jnqJS/NDdSV+Mm6BdnyK7KOQxnFHkjqqCcyJZzgDgOxrp4zLpxGRICaJ/4HO8CE JIUQ2ObfMI9MR9VN8jM4oZw6DwYTlTcbXbztSk0QG2rNnEmEpmItVPIy9Qp4q064D8jX5FxDbu6I hSdJGGUscNZKjCaX4AguzNYebcem/zBz/DPnLWzCw8wV58yXLdTXkNg7irn64g+uTKqho493PSOc MpLYWaVzkvnf6KS5s7S2JBZHkIYMBGqk2K/Q+RWZCT8vMiKBUjGAjF5WDQIiYZ+VmeaMgpeU0Mxc /f2q+G1qInajx0/fcAJYZkA9YqYC2sl4YHyUpam7CEpLZesxpI77bBQOkH0C7dV0jPzXigjuXfUb ctLUZIW6hNF5cffBVrr+sLeTS+HAOKY5ETdQzVOYa/ly9Otnm0yXzyCJw1cXzN9wwdQtrHnubyb1 6plvkKm0uYCk436A3Ihsd9a0XvUVYp5SKn2BfNHlhRH3hL+Al7Hy5uaUCykBnICdQ4VJG6Z4hnP9 YE15C1FjUPnboFswz4o90Brwp03fa4bMBKm3/fSq5ck9b92/PWAMBTJiKxyoYxdQEwYvn28HrVA3 yfWtzbC8KAruSG4zBZ69wmI0C76/G9scY0eM6dwdBzAE0wXXi0Wn4hZF1tDmyMUBSaRGqe2Og+Es xk3t0SpnGbJCL1bU++ob0430iFCd+1iP3SZH578VfKQkVBkz/UIL30YE1dhVmOqXyU5xXncllUDs ZL9bE07QrVF6wGlst9xaj2+DjzAySCiRSWjkrv7HhJPIdGnK4464ZCybTzZzFtq7JYCamFwzQTG0 Vip3FMgRJ/ngiBRr16Ch2ZIkujDesWR+l7IQEPgSQIeyBjwKxsuEQ5bs6jEnRoPNDY1dTrIW9uYa eWsHgkYJE09O9QnkmGivjkwTKDNtpkEakA/8Dw5JizXNCdDf03nUNdQPcVpy94zrrwnN+TCPYQJA Ul4FaNUOdEZ8mlqQ4jsYNuEKTQa5w8Ccbgkpc6q2TVV44kkFSp46mXiI+mJcMG27VuqS7yxUxmsf GI8+9d+X7qGlOJH66KSb9FczxSrHpkrV2VcB2z6DISISCGKsbPHQI9gv8kUW79yuR8pWT1N4qM6R c30XOae4N9628jq+9hdvf7tCrav7VdU4KPMUgxx3l+PQ2VOrsENirtaCekWA2quOEN4XMy0q772Q dbyZhiJyCoa+WYgg7bBB7lCohQVHfjeGNwDfy3CAS5I5UWeWoZmXw60prxnMxhUX9CMhH/+p4uIX SIOpT/Gr8hxnPcstK5zpEAbxk8NASHevxAjvTpAZ842dP3qwpqWCl4wNO5VMhtNtefRpMyPZoPIR eSRjXLfDy/wdGiw4pJn/j1QqFUVukVHxiImpSeDwfQISeMdpERhaumV9UlT+xryIDxtc6CW2Rntn EWQZDlNM0TTpI+UTlMe5L/r6SY6MU3+6hAy+2EAhnf8cuargTv6gXMg8TsWgSSZFruWPNFSraRVU FkHe2bBk6pe1NlTz10k4x7qKI6FVHyi01NqU3VsUDczfA8AcKXFvFZ5DzKrPD8WPltHfUfzrO4ca MJPaCD2362ePx23FbDHW+nwC2lN42XsEVAdIZxJLq3dtUEQTMX8OxjUg1nZItXeKc0cG/282qjzY jxs2JRmYkQQpT8UJkVLWZdcK5s8/6uLD5raXfhhC7zRu0gPrs5IZ9X0hAWatqMDyP3NHDwr2Qwjw M84RxbwH20V3w3HiqBzjogQb5aVBiO8wek/oOdexyRRtnKneSk4bULGqRCPcfn116ywy0LsIi10h 9BFv0XpNIEDpNj/jqo371/LSLGWEil4aGyKkh+soVou8FT3TzXFfaK50pZZd9xwwfz03IwcW8n77 Jy1TmWfwlGjk4WF6IRFZ11+XmhVOLQC78SUV19r40dEROTMH2gg3aGp5GnYQPiCcCT0XeuUYGX37 yUvpuEh/ghEJhFiYuVueElqhl7doU3LCIkC7Djs54NPA64GTS7URqVUr53WZjTUqP3F0vUcJNfD0 SeaHL74itpd/evKrNmZhc0P6sYdxJJDo3xmOeqKW5Xl1EqW3pOb2gJ0YRlDHHtAyJS91Pznk50pi qW8t4xcRVt6P7mtE+NyqU0lrjxjTH/BSmB++axqzTMinRssKD90Q7kzmQz6D6vBjJ4vahNfkfQU9 YGSZIb1c3/zsGsSb1YSqMWp41ujT/Q9acCC87YCplR4FYraV5WH/joFcusrkpv7rgRcz3r+CvLrG 9eX8lQuXDiIbJh+1F8+5G/29jzOMiG5Gz3fpmj1z7fSW7V5WM77uNQ2v2he4YvA/9etSIYzWBpUO cwxBRGArT6fvYUXxi+6QQfuB1oT1cbLM1DDqU+FGPTXm0BF5WpPEbUQ+YFdu4d9OMSI28mHlnrTk 7pMzFqE2/wJwYYAwPrNlfJxQleCC+h806Zb1S0sy5lrLt8vmeaXy2JwgJSQHWauqMh82tciz//9Q 3RapQKVM+mcqqscmB2WmuavKoT4ZdRz6cVWOxxq5i2kgsYWq84Syr2Ir7PUhqxVHcJJXkc0205zq OX5Zt9hNzxdWoa7xD3hjh7FwY7oIe0j/6rZXfKdH01ADGHIxdRgfBC5YrcXf1VtZAGJ7IuKfa/2B JmtZaZ49EXUDfqu2t8JjXItGUkMnNi4WEcH+KcSIyrw3nKJncGEvKdeB38gAHwtiDH2sHBhw670n tskkIKoyUNlQiAlV2CDuREgGakGa5uh3U2LUaJtkdMBzW0B/T/Go3ICy4hNl3NVmi8Tu0TG7JdVu s6NnxBftlwZZDbtXHj608DEYbHNdC/puA+pBWBueS5LjUpcGkS6Fze6zyg/Ee6KLvkj4aFnMZlr9 Wb6t2Ijs4SJX1PAGd5Kz3Bcu4WMW8M8diu9uk6vs6uZplCw3evXWjTsuSIwx4PWf9Hf0EzvYpPuX +BQmA44g3An5LKxi5YVUfRFbjPMlBemqtJZtZfCMEq5o6fmkhB/w+xeUJWIzwwx8/a7s0dINRHc1 E7VB87XQgWafJJpHao5gN4Cy5FCfRfbIotEhtZCK/4LcCeTYSImsXyh+XeoyTJ1cGctzb/KgnLim xsu5x/7R6O8C96U4Q381MNbfNmTN7m7F8Z76VTxl/DDqTE5QhKFe3GM1xlNpRZnYIwjnXYtTeP9W 1uVyuiuVhZ7qMpZ1xrYadsSAdSDD7cWpr2/33v1u3eu1KN2e1iNZgLrwyeC8PWuskMdp1PYnPhma 4lMOFwZM9LcxJdJU+8ruAvptMQfdd2ryITypXd79pN7E/JL8ke8jCM9KAFq8pJM2x7N+txF8WMia ZFFjMX/6f64EeQIYiVIwykKti66OSeti9CVf4xbmbWy53L/8Eficab4aLS8v88PvB0SwOisdUjFw lxL8TNEHdGXQ8tKSRB//MMW4E+aKiKd8qGU1TPrWpTBknPPuykRqQsIgV+RKveQ1GYRqAn8/Eplf SAnL02YfVUV6vk78y+ZjmUUcTJ21ONarSbdj03dwfTY17NS8PyhzkpDP2oUeFHr25ToFlym+4zQJ f/9MGvjpMoTc2Rdk1XMchJY6awPKHle5cxPjx0bh7l+iaBXXljnnf/2qn2EIJkn42R7aYDvSXVkp 5C9bX1cIvVtJbCLo9HMwdVVmaSOakVyCWBkzTSCQAELDIJWm4menlehciX06U0XQ2jhT8ckGqoz/ D0EbayWVSCxD1YpMv+KyMS33hlQJELnEFe/d6szsggvdPWu64inKgLOdFuuLdc3XhVTadFmH3tcu guLWu6eGFVjOe9ceX+MXLV2ICRPap3pBEweYunh4/WZh4HhKHqNEpleC0nGMLyRgvCmT17vjVZDS LdOdrag8hHkXxs0W/cc4eUodIMVuavLe4YYouMMA4Z8llOs4/Hd8vupBZXP1UtH27nNX45g+2RrD dX9RYDVSQyoD/nggDhAlKtkj2gjcK2OhaCis6UIg9lgKjXcQw47qLq9A4ztNubLXunoN3FaXBWBl 328eqfuEUWIJGWbhQgEzEsOseEjyeiOcWXcGWVeQ+09vfaQy6gvs3cKnQ0R5Csz+NflBxN8qP29b auIGfacVhpU1Nvcf7yYNe0/A5iRQdoE9qi6fINQXfPL7UFmhwdaEphiyxPABBL+NPQ1r0CP2JY5w 0t0h/QejL+21UNNfLV3WMR2WvXVKUHJzjLLOUMJ6OCWOufJxjdt4dwX+tiBlkKV07BzRQF6rVpkQ T5oDryHKmHC0QP+dIBqylyk2q/ZrVkdQzS90miYTFaUb87+dd97YI0hDyaAeHanRHSnQ6RkuGH0X z1Ngvh0w2UghyCmLTKKD2eXC2ewL/ekRPDmH5u4gsuqzxScNst31G7CqZbJAieba8V2dXZIv+7v2 RG0L6eC6h08bY7voFgogiT571GFjpjhSeEQyNcnb+M2Aq4uqQjMzjF/juhuRoLWd42YVCC/7EXA+ BM9W028m08J+B1Fj/wfccNByeQO03gA2DqdJOItqp9yUVDtPOX1Dsi/EFf6eZtkhQiN8dO4nMKHd fZYPNDYU6Woz/DaWIla80/nhbJ/FYYOnqyuqHIHLdZgaU622aybSfGde9Pl7L7r7cTDzKKd8ATBA fBpj6Y+bHiqh1Pgh8uaSG1SScmNw6ePaOCUpnCyxRhsueS7oYJUY5J3PQpgSmB3I8IMG0vmWTJk5 oPkstguNACMu11nJ44cEcOqklmoXZQ7W3hsI9Hp9Fk3t4KqGEhdjOnnFNum1o+rjNaKoLOkh1xv7 WqJwx1Ts4f9yeKO9lKJrBbjEQs9Z0Slzphl8aVaGe/4JlJBt02oGGUq0D6DCZBsF/wsGuOKcZ7jH ZXKLiJ/tP0a3im3ZkgqlhwWjINZODIAxYkvGCMcgc0b0f0qFf6Uc0T1yyuFh2GYVgXdB051nNguW 2ZdqLJmeVTPdnma08hidDg80BmIxbqPklIRqHtNe3/ZPX4mvN2YAoF4QK+JqBbm/HLjvgk0hmqy+ qq4cM51seB7q6eZmR/wRBhFaI5OGV5cj3goH07+RRI9QIYpgs9hf5Mh9j4XGX8Ui688CPc9E1XdV ITaDXFAQktxt/NxbCQWAzl/ocT+lO5lJsFMnD+y1x8/8trfmrt3dFcAG+eOq9BXv+SbJoW21zMHK 1wlWxs1kWFDPdEjuQv5IQZYVJlsKbPy89xXKZU7W7NhVLrGa9fFPmIRV0xlqGTyB0PauRFoWO/kc QHSBk5K73JAsbHkWxtoTrMoPvPeOrJREuBKldgzeg+yxMv/7JNaU/4S4xGLhrOcbhMYftZIUAmnn XTC71RaxZVidH6nKNX9Q9qbAEy+500rGrgrPvLv2ZRmkHvqrbkfd6nqN5+deC95GTUSurqP78ltz FdTTwVjfEhqVj/WWN2O9Rc/2jX1Q2YlTwft00Y4FUeQJzZklGCDHBrK0SVC+gRMEmygqQwBT/GZy jPdVAGUbNxPrI3dAiS9T2eTaTVVrABqG2f8g9QvjEwcQ30mdXoWDEFR/Q9cdzzrmocFFsj0zJM3K 5piIEYW+T/foVeu7rzyTW4mwVozJUgEOgP+8MzgTj0F4BtUyNZDGlIYOQZAaBotHcvTFWm2D2xBd wfVWbuCqD/qEvE67yNOlBVeU31SwRyrB2wVrVfsKrTjXdKwzW+8q33jOe9WYg5tf9aPJSSgRVG/c 9FyuagCj+KW88L/jDJgg0sc1ANREV1tbnHUsRjeE/bS2doKzACd12/qUmwrmK/J299SdQDh2eyig RhfjixwjwST2C/pfYM9W1DSIau1X3A0N5YEmJHNwGm+ACfAAxbRrlKmhAwd+EQBxCNU5F/goGEeY o2+M2FJsJ3IJpqLy1UfqS1uh3E4ElSMka/giSdRHnQLtC35gHDiveCq3pBSnwuoXnPNE/C/6QcrD p6vlK1izUxlW3FPcq7KotXzlnnIeQGFnB6idVR+DFvus7xu1phniWUfbsEvX/YER/Grwroxv6lxd OnOAoqZtneUzJsQpRo/tin390ToB1HwKzM6V/gYyBUeHp0FzDquY9uST0+xROmKc/jF2ge80iz9n wPCNFLqsiv2Oo4bKrvT5eBR9euJk1pMENHPV2fT0Y9D02dpn9N7BV/lSBZ9smg2uaNL9L9x8lQEP u9crzB8JtTJiot1OGcq+MC6OFh/lv2TMQjUk3xF7QyivoaU5EF2l0xfZVwFwdQYX/tUMv6azqtFq K2xyEHfvRw4xDAWbid4FjY0xaW9TEcm+FOL2hbTWh0CVm+nYorJC4wj+aOWabHeG88bphy1bYQQd gEBEFX9oxkOmdzQUAtFn7aGkJ/Sx2OAoXHWERHMFIia9AM4kbLVQx6LRDdJ0rJEeFJ0QHROXYiFE GPa57Dy0G9hVatsSajAkETnUJ6E9PNCiENdApWiz9g5z5VIlYyvDI4V91Z2zA/YfwgnYWBemgKvY oH7NlFpUMDZRuDE0NpSmyWV86/c138b+l+Iq3ApWyquzjydPeEtr+B6r7ZSjfilRC7H3UqBLziTL XdMsmbi/6VCORwlLgZNGND7GxypEKkF6HC6J/jcbUpovHuOChFcX3DAxxw7paXieuXY/Nn++aTnX UsX/wv/RChk1ID4JQbykBjagj4+cuybQo6Cy+Ngb6iORdJ4RIvWJsLVSD3GE1ub4xJMRwFXuxW8f qn2gtLvAQ/Hxly2tJFoG4ClUFTZjRpQIUYJiKro/dDU10BU8KGHx9QvJkZMexC+d2nc90/YJa3W5 s6wWEPf64raF0LtiokwZ4Q0KCNnrSB0SfaaF/wb/ukzKgl9mUi9XCmt9Kx8BW3fw3UPbC7fBXtgr jm6LlnkGqvjgx4hA/GHxYST72nW25B3EtyfdE/Zp0unsRhh3/mhfv2EuKXM1wO8kmnclMTmg2NjE Vw4XZKPU8j7PshBkDdPgQbHU2oVTCIioyP4TXFfE6LgY+5vRgbiIl0dbNZoQjxmxo4ZAJrPfK9hJ W2koXrd0bhlT24P4SkqsVuAJ3kYoIHi0oFYhfUw51vXg2W+N/zEoc3JblJpo3xUmKuB7SR8iSoNP O8g9b8OcEQ6VuPmmX9GS3EPDS9aucm4EEQWIUvb/GX6dzi0Pnx6WQBdoL4XM2ejO8mnliFoGb5Qk YRpAXwAi4PkL68KxdJ1HH8jSnLzI8mz9giy8wHMqjtIG6+r+eykKol1LimiagxSltvacoE3kaxO3 /furT1GN9Mlyzlt/mum/2GzwV895gYdvLM8/OsgOTpHyyjTH5lMZaVFHlBckHuDj8aSO7AzzbTso +F3dPfENfWsq1e5WFhmYolxETcLrjyAtuI1AIwq7iULpRk1rIoMkKezVpVeh6tSmcMi5oV5CBpJ5 hNHdTRLuxKicOXIhXJG2QsheFk+SfyICdIKxsbih/r7ctOkWiZa4a6C6WnxcAPufaqlu4cLPsp5m ocTk3/+5Ajz016gElhyBYYOUz+MIbdPPfMCgQs3dTrMOmTzPhnZdd5QiDpHkTtJN9m3DMcOXXbou LVJTVASEMLMDt2b9aVhMsLpm2gSv2LjX5+mktBQnmZYLF8tUoqYZzkWwbBygxhYX9pGQH8VLZrrW OR5yXw4v8ZL1LxRwcKhhkHvnLLReA6azJD8PoWQZl3r7Qxv9kY6OGyPRKzhaJz9eB+UPNapSl7WM fwM8sAWCV0AosoJmTjikbgH1vFGdKsOT7drbyQOGazfqmMOJh67D1BVSjKyQy4f7g6HzIsiYaQwC piCtZpxiOrh58UICb0RKs1KmNpfZDfQE1Dbe6GZ5BhOr0MR1MCa1p249OVfvdbKs4c0YYwmoWaB7 zvcp6Wm5bVr0zYk047wCZUIKh1DjemYMLTt959FPC/VjQ3nO0qDT3xrQ52ORL3eOCnIwUwHY/ERY YnvtxAKiungvFfd4/xOFn/xRrEh3Nh8Ng3vtI12CQ9giNnFK8c3cKzUhxhVarA/SalsYZWlJn9QY CLBtt0sKV8FcE2jx/6QwpUU2SNIxyCoOutSSFxc63kydrPnRxbzlbgSTNuD/+1mPS24o7OpONzRt rPEnsPku8XH615RPXNurAXivEg5YierdeAAKdqUkEVmA53HTsOUT5Pe3cBFnQYD/Bin5YOk3sEll EVSCU4q0TQJPYRW0oStOeKdBd9XPbm5FG416zVcVC+d9fPFxX9NbUFUcYMTQTHUoFE+rIuWHjIUF wyHy7aKctmGkvKk0ElQRBsKtthKZP+fgNXXb9RSQJsnFSTjkbbn9LtP/OAqy0LjZOdu4PDQK8iCp 9wfZo+PbSdad5xoV0Ze83dXFkAsTUjrb14KCajPZ/5R5IMylrBBnzclSiozSAQ6UNiXXjBlW8/pw 65haTghLZ283d9VS04MCWE7jIQbg9/HPiL9/i3YzAzXMXplm7UEzNf4XYwIsH0ZvsZGu0i1c4Vld f4AISRWvbtrkM8O5ytxNIAPyDh69eMJnlW84IeT2opdzGT25keebOtKNmeLvwpR0qADGtmKbbdAT vtPilcaJ25c21AAJCmYzsh59WeAzG1Xji8Hlp0l7Tb0H26MShHvD76AeqxDs32CUqmMYsL46vD2f P+JMKXmOXLcxYNqmx+p42da6jNHC9UN8XWeeBCM6LamUIU4+55L1tHIE5Fa6J5Aq7u3rHpEHGzs8 4SuSMjZcwRGWitOLG3b/+Ues3IEhcufGM7OvHDd3+tVg4M4aKihcdMw9X5UVp93l7m9UAA9nXaxW MEybYoGw2l+KuX2NG8DTxTnYK0JAYCTsvjquOT8pdDdHf3KR/m96GKnyqzDf0nUcS+WuhWain9xR XNKKRoY31N4w5XJu2Yv+TIZCPizH+IU9yml3VpRlpwFCu0hU/lEyNDtXRDHaXfeIPAHTIfbTYkwF ZFzKlmyBZt453hs43uP20PgdnqxhS56wa5xBRxT+KUszlLQBRdTMzKOWdvPvXkwwe7W4pQ1sI+vk ItBZopzamsIrvFSMVCGTg+EgBvSFA1c3a0RTIX2btN+pDNPZ9BMh3I9kk+KoK1WKy5/e/SWSfhJa w2zRP/q6rBVx38vI1l/lH+H6WMfq8SD4JYOM3gpxMfT3nVl2+QsgCdKB29KeWA10ymyyt3Bdo/3i QyHY1v3C0xFKUHvM/6wG04WE9MclHPH7Dg8+dYJL+PCB5itwG/dSCiwuPYl5t0CVkhryqmWKXjUJ WRqK5wuSpDryr8pabR8wrZHVpXHQSHC227lkSvvCg5ap+JtUNsQsAZWNY7EXQE5AzCXeD1EKIj1K q3RFHdfXTOojnxeKLe7z5AdR4b6yWhZ3M81HJxYaFfZKfRIeuKWPfFzuZZNeZekeQwLpasYkwCjI /NApZHkRkwQzxLvZ+QI9WElElvc9RS7bwaGyOswC+tgEYR5+UnocojEyM+0N+E41VbUGMdnaJLoN nhFpJuDMcpgMwgfzykOOee4bPAr6O51MPfVttBlySOoqXoEedv2/mWK8d/OCEwpsx1WzTPVZZTUG q2RpNvogS1R+wOwkoDF4lGZZH2gEaSiCDZBJ3GgMlos/TntytYETae6xN/SKRJmHpQSZJ4M0cP8M oBiZpj79ObXNPomfsg+PPu9BFCnUiHVm5sginGcEHWitRbLDzAnRtf0uE49c2yrmwuOfZEzcSNwr Pj02wCIWsxoSEzU7DJlzXmFc8SqRc9J9gxa6w379IF49bOg0cjqf7zfQHNBbUOyT+0bIUA7nfcPo eQ/1sy2IYQz1lFFifCJmVDre/qEMYhyZgpBgCUz6iPHYNzwN3n2Vmr7CQYBZoOHlkdtYFW+8kg/1 p/hxCVr9QJVyLxOFg5xVWw9Ht6qYGTpc0vVe5yWHGFMM2QVH00IJ9dQ4wyP/UU9d+CaElfLryBx0 dOeLBLHUCtmNTmpQMx61z3dTrVXHmcEKAdChLOcVQhxGLFXrKyA5Ho+xR5HFFg8fBdP5TT2FRp/e 7DYOAiZL3n9Ran+3eKoSKIWHmKAuu4NEUznd4dTsQk2v59q2Np/ghQRYOUQXupXcyZvopILfRAwD 9JzqGSZTs2IbBlFuGVfD18Ua2gqfLoJW+svvX/e06wUcEX/OTuk5MfXoXpNONc8ZR4jXA1rTvRjd EMYslCWM6MgTvP/6u77QzYh7hQGNjt5qAuZW9VXlsgGluK71nBz4USO8Se3ewnb8DG82dFht6cYZ 8r9nJ89StgMK3jNRhEEm9RX1VnksYzs1PbEl0saeh3gQHtIJo/Am0jxrCQWUuE9c0j6LN9q+/Gwn hdosFajueRu62h629BKasJcpl2qH+OzH179b2nVrzufqd82W41I1HrMrhrOyPoitg9ajh3p6+q7/ qyoNqQH9yxFFNuVvcNR/oyLUmjMpSUhBsNlddYfkJEOw5N7nvxKv1uu6saNFo/wjnURWcKfu4KLf JhB09OtOGd9XsZvX+CxU0272UQsRYY3267d4pJq5vwM9anMyS8oen5XQ3ajSDdrtsl62eTN9K5KQ 0M5YNcTaA0c7O2vjdmnC+fviscba5K6VWWdbrWEUk3MlnD2mOpfZjoOvGwCQ8pvEOPWpA5e0SyJ6 m9XyRHvOkzUpRTim3H3QIsoBEhxUhDTIdQc6hsTXY3wfv1AI0b9nVN2oATar+rvhaKwUntSCxt7d X0gfyJRKxnNrlignNbwapFb6anNUEH6jcQ0L1CPGVcOJdjy/t7FoTUo+H4rb5DIzRFLQe+tPS5AD pX0q8F3QN6m1Abd6fAWJzV7yTtSwQ/nuxEokJa2EWHJo5nzUOA+Hgz8jjLH+gxsYyk1hiP9ie51j PFRGEc7WGlND5YOtxSMtfHRjQPuM4DNOdvgDjnn/ZvOHskjvfE49apDJjSBdCe6SsHGZyGIUPUVx Ug31RvYnONDEXDsz64D862SsVuG2/OW/9/AVQL013Yet4u7wEqldOct5IHDJf6hER9azi+ATBZNZ MJcMFvxvbJL/ZhvcNpdLKuPAvLVZMhtKkIVcnP1HOi6U5gpGl7r/ekBeaLS1dAq22jE7C37dL/zb h00+FUg/sVlDtaIvEFgaDjxjH7h+hqWXEP/B5gvexn5h+4inFbUXKb+nS+1ofliI+5hsg6LEyP1C k6bb+PP9LWoLIvqkpI8hO1s3l7IGCBPX61j0E4OJfbEYNxsDOamfB+E0btk7Gya7Cq94ev/CzeHg rhZXV/wYgJzfcnm9R0+Xyj3c/SKHenVN3jEZOyr/iUnS1CkubjIJaYJNz6DptyrSV/fUactcLFp9 Xt1qweIi7pVeOhoDAKgms1ZM6TItZJrifACOA8xp6vfXRpkZwdyMQZEJVmuyia3Hld3DibUXTgh1 neMlLiVAFFgaKrnDDeKE7AXlQujUhMcKcnwfHxvmwLQMqR5GrxisONVsnztsISBwe3moFVEfhGAg UfB7RjWstCTaNsZw6dbJRiHtMRWjgCxAFWTQ1DqGw6CkrPj1i/LrZVQOMmQR1eOGoQxqarV0d5EM C1MVME89foBT0YopR6iLgupM87JRgUVig5lBo5VqQWLR9+/yc+mvtiiHSTRblfU+vU2QC0f/U+HG bhlR8CQKEQJGBnK0aGv6JQcvB7U4ZzBKIbx+cNyKJRNlRYiqsX/QxQmRWzTFv07w1hv8hY84xnlj mD676pPYZ/7Zp2I3GrLvSMNyVUzO6s0qBivTOMSch5M+iP2ElCbkRgJi9doNgwV97MoZ2WNf+c5b P+s1CWBB7GObqa17AhCHXcxjmhbzzC7BqwwKG04u1rK2YxWmXiik4ftBwA5+sKirWpPdVxt2DKk6 h9XA4tCzSIjJ8JnarE4jHR3sX4X+vs62fAWAo9Xl01ofkxpVROpzorD4MFRoCc+hQ35IcPm/2E0R RHghTTfnOM5p0hE/4mdh73UDI1bJepnDQCx6B82E34WZAZBcSaHcpAs/e7ClJSgz5xXGjKqtN3T/ jJb1miOooKGGECYClovHR+VnQHMv5ZYwkz1VcOfZXu2YSbTMrrrey+2xAWB6R8/TMJoqm9t3Fb77 iWEdMpAyJx4mh4iwe1UBiied7lf7xdIqym9jAIyBdGGrLgFk58tdW4MxYNEgLWl/FNHMHyW6ivq4 b+NJlIsH5cjut9leUUvTRFXc4rNJzscvTSQxUhvZdGIV3aDcRnYcTLBB4c6N0Gf2hPshxuE21Jdi 7zr5NOWTL8Q1FFX95Pkuq2k4fkwDMHhfsrV+x7pwA0w2FoM4mxrpLYnHSeHc5HVqd2RHfGccth7B JKVFh1QhA1M004WldFu3V/UhbUCPKZ4/ijHJguv9iyMCaI8JqRHZCBhr/eKqsH5JUzQ6b7n1x1/Z /fzkLBzjtJZhGTDYQRE8fADgRpQB6Hn2G4XYZ/MC9bpSYbmNN7vxFxr5msfH4vnXPX2k0Da6Q8ea Bf6eJAP5t6bOOyCs/xHXgfJU/vBGBaZjEgpyQK6LvmGxy4/nGBkiKybAxdU6wTzL8hf38KbFMhGk phnGI90M2WdVTBZ261bE+7KNpBY/MEmR+Xue40UG6o4EJ3ItaRJSj8ydpdecaXPLD28iQw3JgFSe WidMQhrPvfwJRq+MtITbSBxGPJXiQq9Y47oQWpQqcYcUNc8saql6ckY4p1vQTZxG8PcNigj/yzGx JJj3UhaUHfb7dj5wkqF93tL7sriEZ7htClSJBX8tdg42IiKWvVuHiulJjKl4Z3vl5/2awYs+JdWV ZDc1P5lP9ZpUPtHIDNVAbriVNyqfPYkROTtJC3bFs3fEU3x0q+PLzmLiju4RD4eBwcjHjxvMZ4FI VgIPBPzFkq6yFfx2/uqugmC9HWL4LjHgr22JHrR3CkPyNYL3v0yggdgDJZF2po8GC3D2p6yQHilB HfHCteQHvKUT/OgvmncgfYUXy+txf9f43n4CSUuJQCbNZESENSVqVTqiWam7S5M10ve9qA+xpmj1 EHohUOFC5gfygNd/nmZpXd69Kvbv9PSNEqhH4Dn6ARuwM/ZHqO0StCgS+ozM8Ud6P7z9jkhdGM3o VM3jYUCkJVrd4KeHs4BwRt4UWzumFumbZEb4mpc7kpmrHLymTOuBtPxpWJwDeONyy7F7ui9xVU7h kfbO45xNw2owir97dT29CLpnv2aVN7B0cl9uCy2E/l8/BxYwzwbf+vPM5jwjkTz9c2ijE2XJ7D35 o+D2qSowF0D9KtR1r9uVxokNdAqCPhCsnZQGld/xlsKUtIwP/SBmgvvuYYomCEXA1kf3tY4LRKHG 3EDbfO41/huWENtuJOrb1AASsn5Y3mtdLtY6dR9Ql6YCRaD9e6yv17WAc6sYd49iqtKfh6rF30su mu9a+mVlB0+YB728I8e6qYZ3Q65MDyrJ2lFeV9avkvpMdeXENiLoBojNK2xvUlV9DEmQSi4YqXFn y+mjVARnyQFhA+TM+LuFKglmro6Uu/RMRbts8G3cKgbD8HQZuKK7aafm3OPQbg8IFPkAfcW6C1k2 ScBhDlSew3VnE4tulOevfWHUSI9QVmdVZw1ugdURYOxmKU4/cFEk3bhvmSEEOhH8BoClQUlMzZGf 1cobBi9k9uOMLcmV4p9J69x/WFgN00zjCx0Mkk8DleTnVDnRKchB9A1CrlJtYPvPpW9g2G+TwQhc +PjY25xwMx+mMN6EhoMqPwDmpDJAGG+8iZOI9AgWkC9W/VqzbYIbsAr9FOEKIR+lHtAiyOmDie2x /f4uFBss2s6rjZtHwyXRNd6fu0OC7Oa1e4XGU0+YWABnbZnXa/WjhHCs9KdqqTfqAq8sEhaxQYxi 41PKUR2iVGQ4FRGHhDR7PyTJvos/wt2ygvW2dIcxVX5DTP2EKQfnsgHvbi8xhimjHQlhVvPyrNwq jphD18/eN+pZ4PkrNJkQGQncmyAyv9q4MSEa8sWc39AvRYc0AHlvcPqwU58jXWcyc05wD99z0soC jkfrICT6gkhHoAw+iIOFNryi/aLk2Fp3URPeR/ju9Dz2jhitI+STN8BgPv8D0WCEO05HRWtrZd7p RohvMaNpTovchFSJrkLaXzvF3IJPZ6ZHeuPELpm0Nhv/Xg50TWthQYCMYcC8UBIZmZWpYsoe0vDC u0h/VaWDbhwQ7sHyAtCCFEA6FY2F860g48iCLSDyWsX2M8koNCZQj1PBAn+s8MVKWsasj0zB7MQm TRzpYlqUHwoBF1gef3Z351F2JkVyluWs60tKe0EINGjBq/+LwuNTtBt8iLh1w356mGLLFE2auP0a ag0yPGQOOOrHOKhH8oH0BBEBb8GO5EJ/qeykCEjmXkzugxFEl94uORkhYQL8Q/ork8xWdGiNB7pP jnIuuvAJ83uhuXtiNE4LMWVEIl4e7MSfawB0EBNVCCf1HbtIh7dzG0Znd4/jGeb4tinsaQrF8YwN eWRkKOFG32UnzhwN4+txnjWZUQ2iaCCHWspPm7EpSz1/mKWRyNd8OgMU48AUnAuzYn7vAkCB8shV HUN6Z2lz9AHW0ugzgkKvt5NO7Ob7tMXfzSQQRK1GWCbAiwrZ1Ad8Pc0RgT9yyPF7ccsQ1Otv9KQA b/ilmSY4WnbpDN/+qaGvAiscAr1AZk6qR8L3zVSTNKoYnGJQLKumdJFvxQcaL9J/Ejx8DLPXdqQl A0uUNDXnusn6+YxdA8sAgsNpskebS0XIGlWfgjzKWXr4i9YzkEvu8gWvd0f2YRRkLsFBF88JrGq3 0x4Q0tVLQRPOxF/g20Ccw0N/36lXDQ8RujXp2NKA91mgs/XwsZbztUTiI3Lx3/tU7iVGmQfAs6wv tjRGpOuSlb7C7oudVueHy28sNlRqIAyRXIL1jQBfxEn9klSodCCyA0+XjU65em1pFX0JbGTYmhBf MZ56WxsUwGDnF1r/IXWHrXjqRRuM/VEdJoYInpBylcwBrzsKyrO0kkCw4N/cMG1Sllq732unMcpk CAwYoCEZKnR7urwLm3Dz8a07z7WViW4E0MHLdZ7dldXc/c/zQ/K85xdgRlzsstncN9fmw9E73wGf phEaMQhyLwKUOLW/0PSJQBlIxmSXZl0eI2UlyiFdwGSO5BSdYQ9r2etnaNfZKtGvajXpcq3ZSbFp sywWf0XsQR2xsAFUdOZL8t5dEEhmzZ91VTjrXgnQ2GlchdbkUxKAb6mWIQngp4p1N9R2CI3jYt24 J+JYJLS6uS3ha0zFLNhSItkjGhqm9BSOaCoAiOGm8ZMzyJVrNH4JP9ssvtNOSk3isZnK/Sz0IZCe 9YTI8foFyeVHmJrS5oA+VMbiPtYQkgzxYNH808pGi0Z7YcggmbH6IHL8mynLL4fhnAYbNHJbrERC 548s4fiiHILtJWH3qyxHh/0UNkWBUpGpLcqTKHKv/4NEn5KnTOHHMM3FAU9Eo4S2d+WeEHlg0dKj l4KcotQT/ee5r6yCHSLhQsmsIV8lOwXnaamSny2cPBf85pYOJnBNEOZE/YLZYF1MLHlV5Do4lOUU WkWrX4qzaLk5bf+ovUHMB/xoV8XWrwXvi2U64kBpyGcRCB/Gf+PPoT9MsJ4c8LQ00Oa4d+59gaBA 8Uy6eXFYurJ0lynntnmT48x1BDple+fuKPkTHq+4VG+EOJANMd3Lmf1WX+ohrDqYNYEoGCV5ptXE 4kOk1BACU5Qz1n++4qsoSlWVljdLuMbFN7G2tACf0lAH4uD0+zXkTJ2HXeERxhn5cWNt58Q+DvTj qrny74q2Tqcr3JHvV9ZMDsKo2Vi+MInNZc07tQN0VIh9Ls5UsUjCQR7pFeq6dMlKnhfWWok0XxmQ tb1jiNRlf3ClSyYh/wWonruXzOcYnUKdYdL+67qs/m18+A+EVFtH7y0yhGWI0SCfxyuZap28GYeQ stsU3sjF616wdVwLm3D01Fpzj3fK0lOpJEZIQRn71p8SyiEwx6ekji7bCHqZrW6KrLvaTp0K0CQR 7+iWz9l7VSKeBNITTK9QfX0IMWfncFIm+Pp9DuGMhjQ6NjntJ0eLYlVem0xuPasaYC9n+R93iyzb yTMkeHT5oS0jg6BliUDJBScfYu2OYL5XVhVJeoGFmjE1Nt+wwqJdPi71S/yhZ6S+I4fDw7gU/Ewa rOInIRtB1kF8PtakkLs6cdMxmh1rr0m1FQoSbL9VaJUXnoApA5+Vl5HEjKzsnAACbIWyMmXJC06l dGYcuUdAlKDOZkb+VynxLRIXSiRQcWfeDmBF/wGJANzVr8VQHX0otStc3lhtRA82IyCC+oak+znS K0X3OQR2MV+TEn+o/1SNr7BB6MamkQ/DN1wJE6a0IZOU/sqHq3EdNtpw+oc3MwDZs4+DDCPulb8V TgmDkEKkieBO03Po3sE0aBsQUGmytJaRlELRqiJ3kyRF2oo/Klb0d9m4qpbtdk8E8MSU+uT5W48u N+++WoEMYKsrgXRhtuSkn7JK52uuCzO22QanSUexTQcOTEatIksYMvsoG34/rFaiNQblkCJLh2l6 hcPS2yD9aElHmNJwHgX95NQLPE+EWLZZCN67LcOGbhaZ3Pud5z1syptjK6QsBKGOryjvbls/vzvb /e1Iv55Mw6ja0ZoVtOm1S+Q1sQTHCj2V6FfQheLlcr7qFEbqgJmmp5mUeYxE2jBppVnaRBniNEHR u+w8oA0JBD8KlloXRm2JZ3L9jdtmqfoYlnv6xpmEaPbqLIYklxbouNQv7Lw5fiz6DF0OCN3On+oH Ts00FtP1KPicZkwLjJ6Zss/0Fc11jan8aEHJ10Zuy7982HtsSKQ3K1kAOKaOQcEP92w2JDSiCS9y C9FCarJgUII7dyW/Xv6hg9ylw75Mdi+Miersn+lOkTKQMdsVGCe77mpV0GUwZUkDQO2HLJDahbc0 gOVtSOVFwcE6sJ5/oCHwdNCzyKk6see6jI64ZVtl8N7KXACwNq7NM0pA7fQBk9FlUp/oKgKWhxHu OJGeA7EZk+hY+3AQ/hymH+3NDMSv600HqdhO7otpqKs9Y5OuGLjBa5EHnMxMMnNqj8Vr/sHahIDc muP6cjIbY50S+P7x4U8S4M5Yn8zIQnDUFy+CrWlHB9w5wzE/xdlEWgrV026ZkQ5pzgkBAipcsctm uXwEaK0GthCod6Zctxr6brGxRrMG8W9lJLNappg+rMXrjaClFxsfz1QCgikqECo1uN2zkTuDtkyc BIQVi9cvy5W+5NParo6yK0KBktXJWnVFeW6fEEY77WhiSDkpNIx7xL4uuoNDMk47DsMIMP9RC2Sb pYuXoxTFhHx/ik9PAY72hbs0nTD/1hM5SqOikmQVIebceZ8IJkk8QEJPwqFyyRyiG5ltfcKO7iDh MNzr60/Mq7He9bOx7QQ2NCBsUR9YA4MYpeOOy8pc97YOJcvH31VVSPi1M2fghapdcKK30BIWd1Hk GPF8bj0s2BnL95ATZD8ZM0yU8ltBoxrZyt81GXr/Qir0tYf6fuD1ZtjAbY6xfrE69Vcx/U5in66p WVPzRyjCKiq6kHnj1YJSgqYgzegDDJiUj+z8czB+FuyFDkkPDYC7wYFWfhmlZHNQ/p51GBGSfLBa /2BnWT//BepN1CSLI1BCHiQHdcROj4ln6msgJYmBkXtkaBh05zvTlgmy4W2jVq3Vrjds+RBlZwp4 7tGzzhSrKcfpHSzaoKkm2ItHiY/lEKZ/Frut2wzQeJr476TjTWOE5ruCGv92IVpYn/b00mk+ij8a /J8asv21buNAl7bgEPTeGSY8oBV4t32fFE+KnZHCSv2cHDFBHwUtWk72T5O5JpSkh4PSZ/YKXZmJ hQE4tCjkbsGe12SHqQWjwR1KV9DNkMlvAHrkj7nsP236h7pHR/UFciDCpK+uGrFv1WyGhN/JvOMp iCvuMwj2njjCkvtfVLpS6gZAUHRWbm9tp1ZcXFp8yCZoK50dHkFK/RvQlGoWFAu/p6h6MXeH1A+u 26+KygOzNmV15uc70A8cFd5qlVyAp31W+2J5sYFe+X3BFQsnImbtgpI6FGgeU0/r1/mqGukyOYsT cnFU8s7ZyqlqZfHcO1FPGNEkpdVc1M1HheUXAG9V/1ohQRXKckvV2iIA3FWV9zhQSo97gzjAWrVr k3PTV6V7W05uMruND9R0WtCPiqaDdnfTJFEZJ14Tpegjms0TxcEXkUq2wA1S7h2r5AFHjZ+eeRU4 VzS+N8NxuTOKhizWuS98A8Q7NWv5IApeQ4ZUU1+ULQx6JrmFrO/tWye8cRlu60QHEuCmLr5f7KSt E1lz7QJQIamt38Q6PVjUKhPzClgQDQ72HdNRLCvxjKe15TMLbEcbaxCOj2unYolttnk2p8gIbdu3 WmJ/ihqOybkGRNWxGlvpH6yt02qqjr8fLt4mn/z4N+/L9Z+M43O/AasHOz+IqFGQSLukqbTDUs6B MV1AACTUspzAsNjZVJfW/u5smqsv/8SWxMap3px3QngaxHQzblqHd/HdU18CQanpUv0l0js3/EBr pPELLG5A56xtHfscT4lvpO2BOIdPXEu92GPXnIf5aLhccjXTb5iKAiERRlC+pu+T9j8zze+nlPcr F+E8qgNHY2eniJSGckACMfCKvqKXoDXraVw2gQfiYgct0HC0UQMdgkUZBCVW0xe7V7/vabXCVfwi qJd3/qwEfhOkR+TZWGGKCQP86UZnHo/pZbXqQRQrQcLOYQMrZziLfZlOrYUcCjNgu9Iu+xUwWnfV rRniRQ4oUYvx4eZxZLTv6pyvdLvss8K7MMhGsGQckRaXi1UPfrGgGbNpJMsMfS+ZuCdk7vRe0nX1 AAD3hqcaz8BqOztvZAUW54saEh+gVIE1m0bp8Wv9Q7LamAiZ43dmyfhsvTuOPm+PPV1seUX02FX+ jLoU8kwuNDNxvJFvdHbSNvCNMpljaP9UMY/9ZgPh4+U4JU2OiLqt3JrT2q6/lRY9+v7IjwBS24Tc djbVKT0fTu7ke4ucnUreJ713LgN7vPzKQDxlIgmlZctxZXfSpLIMBEaTqpZPUeEFGSzBntrpu+9q 6R2/sC5/TVZl7u4W1h1uIb0f/WkbRO6ybtMDOzQ1qrMAfNP07vUbVHnyDvKk1bfS84T5oucFJB1k TE4nf/69kN01U1ASIHZ08IAnLMCz1X2f8vxw0LVS8hyPUwI8DEj0zpGV3cd67jkOQDlW95Rx+j7Y nmD46NaY99mAQd7Tm8FRJbxXbEtIB6f8TpV1HcEegnKB365R1xqrVohpRrUfjpGZXphPXCpnL8Sz KsEQnvZnECBl87S/AdSKDr8FUW8uDSksDD9UKU1x2SQvRMy62hwmuC36ZYUYgrUlpriWoB7d/2bO MZ2/7C4QflnfR+7zCsYMjWLO75bg3XixKV/CsChvtqmviKwQVX49nw3qdnajZcv1VD1bD8epX7Do Yv0HudGDKHgzNhrp199QczCkESV9YFhgaBWieO1SD6+2QZuj2LTvGtT4oGy3xfRdcpvRjBZfX21L 2evtF8R8cQRHV7jfa53z3weEbYd/Irpm8LbwomTpg2KWbp8mm4/IUyQmtCSrdGFVRNCAkOX+4cYg EIvJ3IClnfv31w5e9ZnNBZIHUKzoqYrZYymbqBiGWDZs64+BHLuenF4M0DG4upLUgufh8qui/0hc /9dBmnsxNSS6AMjOCYFQOBkaw2cu/jJYMhFfVV5z/0qZZ2ZMBguGjHqzygJDAe3xpUqlK/1fP9t0 OB0MBbVO4NQSR2dPgt1ObM9DYGUaG3rQKaGU7vjpFOxUxFgOktFrWW6hLBgeyNbZ3Zfvfqq/gqT8 ElkXvUqWZtnlhMXMZBMHaqXBo5tnFHKp6Hb0/lTuEJkXif9TyOBAtGOpGkCxH6mwPDTvmjdiUJol 9mhWzURK9Y2+QWqBsUzxx3kx3opCNLm+/KI1Yg0RKjvAXGiLMcLAQcuF3aPVYJiz2Rz+XJipvQ8w xL1mj0XD0QygmxYCwp7jsZY4QjclyZHY7NArWMzbKzD47RHXXfXFBZIKoBGpAuR2+ByBKx/aeVIZ uYX9hDfrqblbOEzy5ki03KluUBFE4rmrENu88sBUYiYWK3mOSg9LWBzMql0H1Vc2LqxRnlMiRO8F K5rKpn/rvaKjeGkWtjwAzevT5a6DTwv+G6xdz6ej70/ICAZGZN7QH8cnbAueUV8yZBtGi5yLIK3f f8AGyOOxOunEDEq6fCUPLzavaUdfJK7mkqVSnzuP4brUGZ/iuyhOuH85GY5kh79KPylN3JKw+Lhv FHiOFakRZL4S0i1X7BTWcFk1dJL1krfwr1Fwn2nePyKdQyf6qcnifMmPVdsnqQg3HfqahmLfTz91 zNRmxFMq9bjPkVC7WJkPB+pK4TFlxt/jEWsYvjpR23IjGzh+NMhQvNMmdVfshsaHOnM9HLtf9RYX hn/smYi6HCyTS1YPL+e+xvTjU2ZlbmcgJgIl4ADsIZxSdyag7UwdOS4KqDmpAOrOKOgDxsTu2wC4 olkGS0RoUvnvg281QylItPMPLmCZwQlCURvfXtIvMHUWZxhGkG5XGfMr8o7u5rNkWjmEqr4C8dBh z4k0eF+ERzbHFCasXD3/zJqWnuwKM7IAqFyis4T/KhByu66ghkBkLvQr9lLGZ8x9EcHP1VrYJ068 +4n5dTbLpnpa5viLBxDLtY8hwdn40IcEMaTBbWdL/OJhKWaDUxpmuDmmoXh0H7nzGj3WIzbcbWiP SKN7g1Kur90fCF7fUXr1BHg9yRjDpu0mBGqhZq83kWrkRTeVPlFH/AnUM9FvqAcdGYEYMoqew3q7 H396coc7RIBwXTLPHhw4zj+mWZfLnVT++GWJCVIolzD6UP40CLgZi04Turi1nsHcTlqIJG3D8PYz BR4LBkvV4Zifcyuj4R0q866EHw5TFIgdyafjVjlkCBYrJw6W6WM1qibDiKw07LgcKVgLLtQjjsm5 78z7rIx63vROypWBRXPoVUYzKEzOMrFoBI7j+lF72y+xOe5WXxUAusYuYwMmGauiHqSuwZEFcIdC UBPGMezdm0OFwhkEzt2HztGJry4WuAFANCBPc28IN/oAQGtpCAWwBcVnQi69EbSQ+93dJo3pXDEp rgmb6eEh1OOROKbgJ2Pzyq8UJpv/8Xc5VPbGAF3uZClEItZQymu6pRT2AqrXzKy5mbb1PjFLNGhx Righ1dJeYvothMmlXjSRKOkPp8dJX8cexMpL2wLNMKCUKzRWYQ8+kYRoVODPSk6Cils8AAQb29Dw D8zD6/aY5JtvpuxPtSbyZCZ31RHjHM3aiRAzoON6iSvyCgP3VxOS4ykx0p6dZxm2U0E9GdjxJ3+q ovid9O2fWZZ4hWYb3TrniQifHLt+27IqO/ZTkn5TaoGqHSssb944LuXEtGflmPnyw6U1IxXbPJES oFyAE5+FfQSqKw/vlaVbXq45ESD3gABoDFECHuz8kALAjXrXG0BMW9jizy5k2mvxzAtS//gJTv0k +GseethPGkUqMgHHgFbi9noubgsaHP58v1JLG2Hn17aLf1xIadxmlQtPXOIPYGETWJGv/+lBk5qE Dfvlugg/P4eyNxnRDjWa1l5mj21HTUCEgZXPC3MD+bLcEqw94A+DT7VMEDBlYghJ6St6noBvIm9V Z9fIUO0WhNF7Ohi9Bo/b90v/LPG/vucH+0ZXsbG78gZKpZiaFywC7aqCNfWIUMTg2e/HrwM0G2d6 TF411hANrAEuBUt/crFoSLiKxWXEX6oscD5t1Ua2wOGc8yrD1GwHtSP/kXaKNwBpqK3a8CDw9Mez RyslBscr8DBaww8jqBpdSO6Djl7p2uCiIsUqamk8DJKtoXS1IMYUkDR4ZTy8NbSFneTkvsUrB7qr K2YQvDNC4+oVqaATo6C1LcLxqnmuQPdQUqjV+ydv8rOLji3pH8okqu8crCYMy58Hzqi8UeAnmtjM LqwHZJsdFaga1gkwLTaScAR4tKvfOFRF3+efyngL1kqkqnUO92eUMpImBDsywe5N8JzHNs8EyCGw NMBm4r9Xz2i3LsftIkvByNsN805udI7syGvrqD0nwanhBXQGqo9oKHH2DaW9ltOTpu4OPIRTiABe 64zly939yP8p0Hmfac5D7bsqswjjjmdRTfu0ODmvtZYtQmrVyBepf+/Tf5PLzaq06ZznJfozTOMA qyM2b9u+MkfKhFl0BiBij7Unhup3kptJVbY6BFqPYTNUAJCPKV1NEisBre8QSM2g+Fq6f07eLUCD tAWZ9W67gxBXUd2ObpZ4vOO8KSVDchNLtY8OoqqLeewSd62rawdZ85UT3yvKgJHePW3IBCMo38CN qcFn+m5V3RnzYlS7fq6ykarM4jKZQy21lBcwPEDxT4KR0n42x1HyLl0V696cUzQ7HIfRq8h7xH3P d/0aK9b7Ey6lk51OPRqGveYHgoVbs3s/0BEm7plGotoUr13lu0HE2DaTH0JsbkIK55lvVmtFJHjt Y64dc0OQ7OmWZtspc3CwHV7Aks+SD3qW1RLOx58aJH02zLkoNNoMdMbnYcuXBTr7FR/vHJCYISHX 4l27W2ERJ+1sOE6DMTB5sPntY2kAgTa8CBrP76a+XjTTb/GoXZHteknHDOLY/oyhXNlUznAxZpqb QGP494YBG8zQ004iv3HySR2jTnEipociiSYWtHIm6XU1aswRc3uHvrQml4+13N2kjj5XtrzMgw2V P1v0czcEy2V1ZVl27ZR6Axk7Pvisr0som2k9dN/CM1KUDSthkUhpb0VQeq9vwtFpq7fJ/hJ3FxRf yRHxxcogbyxmsPLRwWOI9+nssZYYU60QaWyZs9hTEHLlwhTr8ovGnFBkKxK9ZVliV0bw/J1igSD5 bXSfwrCIZ++M8zZ0G66Mlb12S6t50mMyvRY8hJl/8NcrC0jseWNJbIj3xsjE5tZHRRWfuceSc0lg ZWYA68HhdFkagsfYQkFIQU2kQhXCdllTm+KxjrHZCduAknorm8QbKvLoQTqNhJGvz8eYq90PLrz8 d543/1ZsgIbJH/ah0I77h5f13sGPyJO/weeTr0osStBxTjQc0LSqAmVHNw4jlyyt3grAa5J9+mRg IwEixYlQT6s9jA3dIY2NFWzOKGEMLgtVtTiyGGSZW9rtplrUVNmic1jilA1sOqFqKBPqi2HjJ9bo QrSCRoYxJ4E3Ex1GqH+tlNzi6+L6Go57F81h3mhN4eOdc1Fli6SKmcsDRg0k6H7eFkjJw2sGXZ01 N27jmB6siG7gAg4mSyg5pOa1cmYTvF47AXq5Qan/+UtCq7Sq8oJEaeHT/wzSy04khLhj993c8Dmm dPEYoYl/2rN35YbJgcWLAomqw1KsxyT78Zu5O0YorzMv9nUNWJ2tcVK2cVCIdV0CsyMdc69Z5KUK SOcLtctYDSQ6XYY2KZmxhKyd8tgtBimmtEuU38vbgECKSRgvu4AnhjxH/mopnTJGLh6NsWbA8r1A cC/J3u3hkrSTA0O+O6XL87e43LD6UfHmzITUX4V/2hF70AQw2C4eEbxTZ8HPO/GtMrQSoy5DT8fD pRhcyGXg+B11ZDthLsSZK/PQ5NRxUkN81W0LQjUSW04uZXA9rK+/R9om4M2o8OJAEu3VUM2u9ROx pdprIozDfJWAQyEpbnRxWYD6xThLrwehxzrOceKO3W22BYmopOUKthr4HWC+Hfc95jdmRORLmGaT kj/12UJssOM5ISyslzFRJVGhJR+ETl0i3761vOvAx+7ky3reIfUvgQVBPnHLrO6gAQw6Du2QqpcO 4xOIxKiXP15OcO4xZatvb+qtACcCm68Wh52noBFNvaqvLa7e4S6iNNYGWr6aUmejSO0tUUprBGQQ Ga+zJAI8kj7QmU/YsFspnAgRwZ+S6jC5kPXi5IDRMPNR3oGEqfEfDM0aHDcmgosrXVLBbOou/KFJ /lTwCagAnmgs0Cn2nOIArgXpYuTQlzneuNWLLkA8qF28W4mE3W+i9yCj6zPe6VGpdg9L01z3cfg2 fOsKL2HHOMY0m90O3tmXH+GNkbs0Eu2GEgxNmm/XCkS5njdlJrbhz7w8OrTX4WfE/n8g9AU4Q5td algMnSIszcQ61Y3gSJt+6eyD5KE6UzA+rDoXBl5xCyrEungaB7qvR1cGoUdaKvlKIhvYVHAgufRJ Uzhgfr4G/sgPMCgVkxGJ/37ejV+K8DnkSDFM+UDra/Z1aQXcklG58p+BYXYdUUEqkLyWdi7X5XIs MfhC1BJE38icifWezZzFW2/jpKI9GV8ulTq7xAywt24TxY9gLlyyXmUsSO8KOHqEPZCrN/kRMBNe 7v00JDYPIjtNAixG+55EZjI+aty5QbnlndTFYE/dTCQsXgslvOVCEt0ANrRvgSzEvtDKM7PVc8tc LHwaktmyElamqYRyW4N9JQTs0TpzndBFpkbk3b9BmbCPHjsmvmr5xf+ZAoLejFw= `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 61984) `protect data_block CZyMVnx/yOPHHnyfAeG1brb8pDDJTPJEhPZLg0vZdzWDV7fCt9A8XspNxEJB4ahodoNkdrz0tS0q YbDBT80PXaO2Hv5ABxjKtPGDKbmygV+wuY+FwaUKL5u4fbK74C8oEhLSW7QppI8pnYBErBi05MV0 yh/eRXzdaieOqKSSrVzSni3AEXU0nponYkydGyuSjzmeqbwMNvQdfGghucEIus9GcLnVC7VKPtT6 cHN2eu3DEj0kbI0CVfgS5hwrqwTATacyG3c3RIBO5InTdYDYN7WYlRj3qs/10UjXKKGmvj5LBeg8 qqtnQkU2/Vx+RTpq0J8Uski6ztI0ep1Ry0T3dQQ3TDLfwVtTPMDawbroR66RWjczLhREv21NbPCL Y0zXBGYurC1GNV7DutMVOPCMtgyg9RgvghFSZzt4Jb65Or4EDBcgdwU7Gj34eM7izvQ6gAr1d24G l4Qk/nriT79xz+JsPC1tkBM6ofaMCkxpiB9aWu2VHoF3ACqBq3IGS3ZqIMRzUW3BaKkBqlNfVbrY DQfFwPYchAn2Ox37pInpCjG8ADShNsmL9gGCo5HKRmhgeWG09deYtmNndwm1uTRa6cLWaVvtUnVU aYbQ+DGWwwfRZFZFPG6T5Ju/rgju2AbOJJ19z42FmRHydP8zbPlYnHrWYUnb7omafxQ8sC/oQvKE 48rBQahUBDfI+vvDrgBkyxmLB9999X1jYAnnl+H6O8bzLSJThQc5NUiN0XLaPOlbpazTtoLqsNBA GIQVghG7By7ovFAh0dM8hlTL4RG7cj4CnGezNBjsoGlgbP04IY+3j+F9oYUgo8zCW3aBeo0jZooC d7Z2Dw9L8xQ1nQxK4ZdqciqTiw6OxqlTge0Q+2ryPNVzxXiQItFNSs/3SeHlngjsCeXviO5kWQKa f+/DPh1Zih/eNvTeU1SR6pDgzSSDFjz+SnMBzzaxQ7otRij9dOakN+Kuk0tcBp985EzQT0fJGfzH eVqF+YbiI/jegMH+QYYGA7yWUYk5ddB/O/KV/TvABQM0HCIa8UT5KjMDjHOFxN6NCXBQz0vohx98 F8TaI2vQwzTu/PSyuv9y6eRmmZRx//NIhyiuaP4N7XlHgtVrdJSi5vJJhgV5vtcU5G1tyJ3UF68k WoEIne7lR/KVe3Ymlmd8++6bW7GNLhvJjH7XkYHuhPowzQBmc8T8QN9pU3UDByn/8MFU6hTQqCAU NiVP0c8GReh/yVXtO1iFRRXjuQvtzDH3310D4UgVoMpcklXXq5fAtYkiCiv53Ju5kmqC0ZnG+Ps3 q6aiRwX1F6CM0Mu1R2hGajrmj5I9kQRpYOZojBDVWElGkF8hcvCoRh4DVTz/3QQrJEwWEGtVviz4 JYCIABgdB61K5RwQWugb4HMviWfhN1CeV2jj4QcsUokmpPQiYulgLfvY4ptgJK7jt28ro73f/rYf FFIBreKwsVUowKjS+BAZCCOBov9eYzYkK/++Z4UeUIi/cLMouxtNMpxZZRft+W0qGcavc/hCqAP9 3xN/RkXqmRNDa3zgPHmk4KcMigCRwn0ZVEb1N4BSvGz/Deksu0xHHuHhSqyIsuRlz9TOAp8b95QH 5yoHfXmE+P8SSH7WKxVFwdHomOPhylKVxmhLd6SNOfVEBEzg+yMBzpU5FED2l2r6IEr9vcncSPzu cCxdUDRKuBAsvqXw/cvsN+SAVaLNLrN/VveLnJylPdY+V4EQP2qXw5lOYVvbakQXlCM5nH4DNhmz q2wJgDaUecMWt5rEWvmP8pqZPjAm7q5WGnjRRbPFrJ4a55ZxHbFZiCPWKcHyiDWva60qY9qpMzRX Mg9KQPSa74U2OqkIE1YGvMYcep80kNjP0pO7yZB7rR+ERewoIWmzkAH5Ta7T/8vU3rLdS4YxXabi bGhynnDafx5GiPGoUIrwhvVOq7eT+rmFrbizXAjGd9+7JRgi4nhBPEVv7XXXHEallB0Rmmm65d1X 2JD1t5K6593IFsvwEZPFVXQODmrZ2ehAxe6c2BDYvE37s3BxkZPn96veSVHMIFQLFRdXEJAZao+w mgDU82bl2YTpBdG/miELK1v0e5l4xwzFfvkNkvjkt171+dyRK5evZiyWRqq7h+0HgkrkLY9o7DVU seE6XZwsv//C/2+P6kn1nE6ExiEoB95H/s6Hy6ScbOjj1wQJM+mvDQdiDH/AwE4CruRA10xc8mxB 1gDYfeYOOKB9xqB4DwQqSUwI1iQrlMGGASSXnppEDeGS1DK9vc19YuzIrkwxZLbTMdlUMKIVqBCj jlJiLz7fvOanM2xU6jyP86o3EIF3SSQRuXcU0bJgB+ClJqdr9ctyHNK8+N1aFX1C2KPa5BYDVh/7 20y7VsRbsjD1fYvA54kFEDBOmBmvM8Fs9ocfOLDxLR1/UqiofVe4NJflpkofRA3MiUnUd0f5HYKb Bx2niYN7TYlhzR/5rLx12oM5BkFhYytT6SgcVnqA5j5NvuS6NBIl9gRBlL0o39dacNcPyXq8PszM yDg1AWzL75WkxP6VH9jfs7Y4se4/nn7tT5T99fvyiT4+8RDb2wFFnZ7Nozcc4LEIoS0i4cGfpKIh S2XO8qCeAHTvLHQpRgwZ7+8eIbnVbibQY+6yg3M+r/qTLabNnJnjsFlG9F4yEPDT41GYab5NrYxh rfqNIChWtlbHkpf0HMmxiDL/MR64N4Q/xfFvpqyVct27ljOema5iGExzvZiMPBIwTaQpxXdc8rQq IoYWdvuzy++848IDJlbj/VFWmKz0SWJn0yAVaisn1TVi/dK2z8Aq/LIsc3hWUMIb4j+ZL8RzuDhY VI5CJFKQMcJtu50w8ANFb7Tj+eqnEXiGxkIe4s3CCq0pW2mytzIeuFPtUk9opo18ucy7AMJlWUT6 jlIrfKaRab/dBLnxxAaYxYoaKK3qDIn6B65yu2ZiJmBxI21fxMinRnIb6a7OIgG52PzIPcxp0IL8 zSHkZvVUC63sc7ddSNSrj/dhoVwDvWp84GsQB8Fo8BjBdqfFYBXIgBqqsQ4ToEGOZY3wan32wi8j QwDgJ8WE5UpQ1kKXfvlSdeFMBEw40STYKbjVR2GFrrvc/XOEaMhlDuomnMQebzDDuwppw7Coo4I9 3xGszSHgJSRVaEV3XaE30a56FB+JWNKI+cnIFPSxVx4khZmMufXXbSkfjNqGDcXoyg7WIjy5OX84 p633sqji48YAlGzGSMt3vJot4gh/LYtIuhbI647Z/aHNio+1XNguLSztIvLYM7YaBWpH1ikhQr1L cgeGHjCmmcIkzJQKl0iEFvaNTJij6WmU6QIPjKA8T8V3G0j+Bgv2Gm0628g3t35zrd9/MGK0S11t JcpZl5UZHIz70+IL+AFuHU2LH94Z2GbV+CeW7GGuy/FctP8gY7nYZz3Wxos5up5/OkV8XyRqs7E9 2ioWySrKaGgCV3WwVWm0ZIMooIivkanZk8r+O+yb+eopMEBIGdDsXGrBottsqgdNpEcNq4B3njuh 0oG7qxMZhrhIKySvPgkFNlM2GV0OcueZHaaKYiEOWXUcbonzWf92c7b78XAmBdOsUDgzvQg384JE FPfHRWGEuNqeEXi9I4c+AFPRRwk/nR71SxGObB+zhkvsi90xLZcXDpnwXw07tDR22qqrzP8T1tY2 a7po3sOvShxloVPIhOoEHbsL/selt9uCnn1myf6o1ABwjLXOf6KNZFbIiBOs+ehQbEhAVlU71Ag2 mW9WUgx1JCiya/c0MX2v4Ilm4MNwp5JXgLVOlyEwHe2+2myDeeKBAmJhT/Oaoqvd3g9aMXXhsgBr YEQ7vuZYQCSqWdhr0XwaLFpOJlIDRftucBQIglSbMD1Cv7R/O0rhd3KiphFW+g+QPLVkqgxcls5c kJATCDSK4g4UdTyuQa/CzlbE4LpUlBwnoJD2y3mk2VwO7wCuvN/wXxh4+vJTzYnDMFLl90jEplnA ReDGhJYHOolR9qQIMUiet1Ojv/1qe3iPnkSJmR5Wj3gvO69r8b4thzU3mPrw9HPLCTTn93507PZk jJ5Fx6jIZ+eSQTysq1n87uZfvfDv86bJ8Tg5aBsVggLezonSYtnvIx0pdz5fB51CDL56KMg+2NuS rRKzCBYJjvE1ZfCFgEof5gCifAArKSLQ65bh1nknGbFDa7s7Hjbtz/RK5Z7nIKXufm3eyS7+ZGaa qqQpFtvlbTrF7GIrq85Solx7K5ZEaBtx58S27XYGTDvd/B24vLNhzyYoGqLi+GlhTJMpN2eS3Ari ZQh9oYMRCvPoG1uNKOIac/xe0zuT87x8101Xj/xisVA0SUUzMLsm2g5mWjfYCf6joV9Z15dL67Fx jRmDXHRUpY5vHqcxH6M5tKO7KB43bwQj1DDfkFrPe6sI0U/XYCtlTuABU61IqMi4YBltoNntNjkk P37P1wdeH1tb/yw/MWgEtGzw5MFIfibVeZubr1OfTWmTXguer1MrELKZrJjogQg+dMOGEFHCf3mm iwLrpryTu+76viYszyvThM7CgCVj2McaAmmWtai9nGO8euC9ap+CCGbjooZrUg3A9zQ1RfCz3THz tfUGfFiBSFDr63sM82MbaSqCWO+pDd1aJsHR4oS0h1zdVKBfRNtjrGGdFbAY1QEoVJkzDhFc29BK iegSprUGzSaWqT4kJhGETPPDqTLtbyNep3fR9fsAfol9M/6wCTwVhlYVXPyhlmdhKkCJm0zsq736 W5FbHBKKSONkk79uLZFMeJP856Tnp9LJpsMUitzRvK+Cu6Jgb9RHwpjCslrUoz5KB0rH9so2axHY 5PlkyVAr3A69kLXrCpggZ7SFKzhOeLh+NQQoqbEBMcHmxKinXwhFuvzUYJcxv1Fr3h1BjN3d9zA5 YNK1u1PD6td6OnzjL75wnBtYRVJtINMUb+P0Kef8Vn16cosuM9hn7xknYp77mmK5oYFUlqTxxkB7 /XoyOp4b5/8g1UOMMoH1nyITXhdk9AIFBr6hAdiWKJfN0Lnu8zSvDX7aDVpxkHo7+MWWBkHnkh+w GVA4NPND/9n5xQGbQWc+uzpEPxqjXT/8FnRHj0PhNON/EhLr4G0Z1oKhyg6N8h+5lJZYbQv2UWqx 1tXJ5v24Uo/86/qOnpZT6pSJQOosCnbnLQUnv2xqFrN4MyACM4sBSfZ2CQQQC268uAX160qkB8q7 ygw4chPmt/R1rUVqaZ+YhAkfXYkVlMHwPkW0dq29L5/7mI39MXYITpDEU1RGQSrkwdocEAzLjDTj lTjXTL4sVm43FaZV5nhYFlEHSIRZd9DWuEqfUsJC7AcnyqyK2CdpBFakMnqLvZTxWGnrdPllh8XA JyMbQVhkm7zGQIWbvQq+zoWG91DUUXxAJLEY5RD0gFIO2mrscKfFAPkSoq80vD+hPEtOGpdk08UQ Dv04pJ5c1QkHiaioe7aEmTDeCTQIZo+liKAtKp4e17PwunLRS0Nok1/TxNHPaqwqYSA0lQU2T/2G 8mQ8fOGe4XnXxJ9FW+EQNjMSja1RL98+dYxwLxygc0u7tTGTgVpOwj2/iJxy0ArADZ7kJrJod7KI xY1VJJt3IWwdZLZaEsFgBKV9HGiCvW+sbqnBpEKUrFAA433mwC7VkfkDct3VUfBnuMXsRoKxGCHu P6bZdtZp7SiyeItrN9mfoRMgb4aeE+S/kpyG5voZnWZiE1L71L2XJerBMNqFuIkhAhEUTTnp905g 26CG/mP4mNbghOAnEj90AMZm9JPg2OVokMZov760EwOLfyC5SIfzbHlsf5E+nrdfG8jUdT9ZsY9W IqWyMc3SU037B02IBUYEV7gu0LZ4kaAmY/CRd+b1dNAzo37KlcOAFH0bRWp+9p4LLbM+BsVs6gv5 8d0GAxO3zHoRr76EfMG4VwutdASB71ue7R4zRmfAQxbCZFCRP5PMJoT+ODcFXfklpBw3v9D6BQpl JUoM7wd60yM7Jpl8zLYuqUlfGyl8Jkppkgzs2aTKNcqSSt5Xdceqg2ZBl0w1P4hF2lEl1rpSvhOZ 9uATt2B8Eeqy6ZD0nCfJ9/P7+l665KCg1Zqo2+zNHuaFXKclCOiV4vWtV8Cj2fMPUIsdFdbT1rqZ hCLJ7E4osmf3IMHZs4USB2chQrn+UfHnsZZjBuaFnlMjeVm5CkqPu6T5RGDO/LtyyPgN7u2pItCc EImxGXLR2gFFg6KFWU6K6wkepi6+Fmo2EdU/yHamC0Mn95j8KDWwBhHYqMP4xI0rsS41aDe4U2xl 04jevcO/ySjnRJ3xeNooE5KT9vUZsUjbzoaRW9GHguYSaGUiT4Op+32piszuRzuIK8jFkNkOag9Q VMXu+Ng1kgzJ9EhtB9yyxpUwPbqUoJEYlfiVSrJH0vrHrzTkpERoN2ntj3xEHz/BjmBOoRasDmts vbPTGoApbbVjvvS+wB8z+d9v1oC9Bdl/RRwjA23RyuIRwa4Z8UBhN8XV4ENjKPr3F4jzKIfA12eH 4C7IZYDlxp2OVxRfpMAAoCMLpRCeuNVMyztivCD74IHtOpsu2d9sftqFOEq5521nrKzbjQnCQ8bv /0q6FIBMsGyh+MKM8ekr4dmVcUV7IDOLeDMVRZ9aZCcViwXm2Xft+Y5Glm45WFoA2VRXxNYg7Y38 bKjIgOSTb1Vj6aLlPP0YdIGcMt0ng2Ydza7+A607ikhtJFn9iDk6mt7Dfcv5R+QpaXyNkNSGwAfX ppepjLkmNUKNRzj9P/O5EcBgHDPCSyF6lIX5LQWH8EZkqYZs5dfDSenvzWlx6TDtQawFoUjzsh8z A+25XLxKzAOBeLdgntesJ+pi6GcEDLp+R4/IyaUOLAgIWtBanB9cMPoNui/cQH9zbBg80afQ4Zp0 Woib5oO1A0sVvwnAHXG8h6x6ExDecqvi1O3WZfqf9LFAABUSD8MYtIIqMKiAelb8M142rNJgXtjU JB13cx2P7yil4HsAVClg9MYGQPTt9jSIFVkdT82HRL8+bL3BQFKj4CDkR1BjX0zaNkJgxHiFnIwZ eOVqb1PePasHdBbezTXP8A+j3O2tNjtqMQJgWzHGbt1DvNalpi7yM13wxeYpP8Kz+0kVQ76OZise Q7aPZ25gVHGLiTIcm/kjXj5sA210WTPrpItlx9WpzxpTgOJY29xfc1KcprPVNy4cPW1GuVvyXNl7 lYGGoe5ot8TilGCsFKwitAVBB9mnN4KFkdR/1N6rJb4+HOuxKtBX7ptf/vsQ3FyD2aLM3l/pnrsB CN9Zgh+NaQE9eCaoeuNE6YKtFw09SHpiJ8iH/1w3GRbMY0Nf/bfxGgzxZLv2Vt4nGEmmSCG6qz9O t3W5dl15gA5JlWDWZ3xVvll16d4Kpb8gsqp6f4MYA54ANf7dnV+jrNFXrf1TFIysBuQX9fg8sqW3 V8ei2T6SML/ViQ4O/BYQJdg1mZq9/BPnElkjIOq2iziI/uGEMLPZDyiv8dGfu48QCSOHkM7PnQh6 EYtPVutx5O1rqv8HYyFac34nA69ahic7qMf4lStIuQT+nSRy0DqImFNplvruweadPlr3qiPzWlVi fycQIvzxVH7fRVB7cYarlg/4VZbM7Z8DTJN4zK+oHe6HAqMkfzqxhSeZA7v558v7avGIXGaTvHCs XVfXwk80DmH1jRc2bYbME5fmBOD98XsN1/u4rITt6ywhictmh+slyBzauHK+d/5kUP14lt+Ho2yr InNjJqeZ68Z9hQkL5aV+VDrXDjUswGJn/qPSJXTiRjFmrjIHWk4BrQoOTw+f5PAi43FeLAdUm0Pi Tk0T7KlPTrtv0izTSb8zsU14WHRz2t1/SElZpxfznRijwDEBHPVUNshZEqZXh+32/VghH2bgvj5E /xyReDhTPUQgaHxURLKVvj1bNVvy5Ni/rJWhufyHF8V69/LWdolwNQQHHmQsKrO7tB/9/HwNbvfh FzHSwZH73JOs80Uu3AdsqXawoyEU9mVsM5QnrMCNB/V/DOHOm4ZJrydP/rP3r5ddQEDeLoGZDeLG Vvl+AmawIrs6CjgqiLS1Kp/RzvZGMg1/cCIK0IYQsegoxZ3ZVl06qZscBnLLg2J6/bQKlo3d35tJ rPK6AePXKakSVIz2Ej18v7p2jkMgLq9G2dIN3vYcFPm6IEQqJwKyfJ4v6uwCoU66o6RNXMttSniZ adC8NWHKVowvWWiGs6F6nIam9TELpqz/oYAZEn3V6j7xfWcx4pyHKnfgkVXIBMJM/TVQEWHpGUke 019FsKtsTNf8KtIVylVJrNoP6MuIW5vtam9RKFSrvyVUO4rPTl6dmWtW4vhGR+HSJaj22BMA0jam qeWIW8w7Uerhma4bLYm2CcZiQTA4XGwAffy95BMndDuNPkiuCQ1ax80ZVAmfwPI2uZa7AzCZheN4 74LI2ajDeuvGLNO0e3yYdoSvUJwS1IJ4EfXQjrhJrjhlYrKo7Y1naKeEvI8t1wyOmcWI66RMC1xY wMLne8EM40LgRF1dWmswDY0aQ2j4HGWuKltpHQdFMb2OSrz+sOZ+SoQxBSYLZ2+NJQtq3A1Wn0HX aPS8ZDtB6PHm2O6+fkacJzsgfN3FByMLnSKiI0nYo2MPnb/o23CdN6HBPx0nw93Foui1WTwok5su S8Eo82tA8JGGAuPacQGOoD1ls/YHGq/hQDmcnAxSKA4JHVT/+HZ6KeyrnQxZg63ax8tK+H1JSJsJ F1iUaSGvOXeOJBhIR826hf5FcHGyNJXq0Xkp42ugus22i2kJsDirPV2Ys/xU/kmrS/Jyt8aPTy2g vzZoSk6+jv99QIYraSJB5UlVRJL9FyIf2B+VnUJkVuX/gtZ+hCHzPPir7uEHL7G4akcC/V6D6vva HyobXDfFPbFDdR/1jBCjoaF6lnJy9RJlp1RNdPyib+1BccmjyKJAFAPC3fQ2vxToju79HUkkgcRd gd1i9Bm8IotOl/2Zn1SK6cS7D6s0VE79X3GYbao9nWJmxwyStjsQkIDEc7jw59K/aHrQBtXIP2s9 ZA995mi9dHYxm8co+Ma6ktYIfYWl41mJStqPYRog63bTCI1o7YIFO6NCiZoswptosRGGPTlh+Usx hkWtNQt3fsa7XKPuwrpe34jle8Mw8KSCqPoAt5n0i99M1LJ0vGci5LjW7keT72ZeFlvGMA4aO2ME gEIz3L4F1S6+od+Q49t1kg6B5jXU0UPrVAnkD0RUrHYzH+AcTL2799fTLFkXfkdaLY0DYH1RLt+a 6679wewe4wTvA+txL8mfvVydeLL4pXjNHymnk3TBWEqfK1+cs0B46BiCeqQ/DDlwZXjWbmH33gH4 wFcWH5Ak5PM/sUwiZRKdzsV3X6x/Qy7K4dHuPeSmshoV5LWJ5p6jExY4vmZFflDTvQHVG/H7GXuX QyVK8H9p25H1AM6eMP/fXorugo++8S6SVUHCBbv8++nrrv4M+p9ZaO7yTtptAauqFavkY/1CoG+/ UlQo53kc12ecwg5cK+HY3DdRheOXNSY93n2StgZdKVApZbdLzIQZApWQtIT2Wd3MLKSCVb7EAnGV 7PxqDNoEaaU5NzBNYgAwtd0W06svRxYX8AdWQq7++dKixqja7QPuTSRU8f9wxabO2bj/W8hd7Nwz gwgocM7fDMUbda8u5xgtqPKsvptWusMOl0huP3HlFIfwH3q1+KlisaZoAkKB615xr8oktJY9mXCo wi4X2qhH8Uq8QEXrfIj3ZUSfA5eX8U5nAFwtSb1GzLf1ESacNjP+pCBHy0j++6vzeQgr4/Wz8UCg ADK9JO+8KB9f0CEAq2jL3yCaBMfWJPhr1DTYSQKPIW/n9dobL3EeBmWraNQIZUWBnq7H/VezkxK9 vZAgVA39ezlPB92VNgsHvrT5MkPxxmEiGYRRPGiStd4W2Wdls7610NaxotrmEy6B9ziPYR6HNcAk GBxOtbpaDMMR3AG53M+o4NgobE30Z21liRnCgjlTUcVCcPdZgJyY4eYwKjzAzbpUppx5p53u1YTk ZCRjzeHL1lCOsHZJ0jfp644NJzG6omrzSQr14rnXqGlmKQGDLMwg8qlRMuGGZBCyzFes8iTtRMD8 BH0/2uhrH9CDP/mIEQfMyRRUcv6BQYtKeutnbVYQC1+x4IvCiiTYH9ylXLW7yITeCS3+s3gTi+Ul TEotS/VQasg4IVQUeJD6jdkpaE4kjZkdGbv3G6lx3McBTPebidbVVoqemj7aW96lGaI+Rk10DjWN V87o+3VHMrTiQ23KtCVPAEi74pBPP5EVnL4IdHNs/ABuCvj45X07FE6CD7hzHEmRZG0u1iZVS7TR ip0j6VizEoaWDABEcqIQIuWcA4RHqz2vNIEVcrercCoQ6EDcFVaXe4nkYzd573N9DkoRiYOVixjv b/tjwgR1guFLR3taCVUmUHfa046D3S1ZgOJlNG69mWM53qIB7NLGhV33BDCmSfKs6ODMPFYWySjT NTpnunYpjJh3UyeObgq9dN5/y0HKEmeWYcwP25RmCSmGSpMXn9rMHUtqZOFITakV/XMAcyEhuo8j 2KNxn2hK7qPDdMN5syHfM9diEpCPODi21apFgn+Pfowa2PALHjKfGpLgzyKX7aiOCfmX2UAZkB7g tlywj5GH/4h75R/hJNHXoTjrOMNONDTVfbbfZGFQqHxByvGowiaAs/CWHRdoYht1Yx0U5rZOjS4q dUplaDEp3P/G6WY+wlviHZCxyAo1duAQx5FC0g675umFEa8onmKArYYIMRx7r6M9Hkzf5R2XMsnJ JEs2pHF7hHgkbe9dRjUj1MkIaFOw8RwYJLcrffCD6uwigb0N+tv1BPGTdxTPgk4UgVfQi3GGUMLS zlbghkEy4UYBMUDx3iwbAReoNipheciy326cVbPWgAGWnMvDFUCVidLARWFtu7D2SYOjYNKIi3cQ QZJQEBdRvJCB3WSKDPgl/kg61OQggWrnfYvPZK9EgFZRVZ36yXOveC9M4lw4ICvgapMYv7QZO5Bh sWToo8Sc/j9LuD5UdMLZvYHOtB3NFtS9WERyFcQFp4XLqflpVHFhnX1F1bdJLFuTvf2xoymtOBYB H4iUhbIg+HNlD0LZ2+BPIqkgEiFeLDAb7yjHjDFyQ341WM5ktH9uD+a+WLW5zyyDlQCv5+sxDoUk ceSQQUhls4SZZwZ4UR3O3h3b04RPAZxOaWWyA2kiez2KEnzU80nKNgQkAenewdp1zhAlEX1ssdBK Q2snzjjEerW+IF5O5CYtYxl+v3OiY69v2BsipF2nlHK/cucHr8VpokbQSADEtOfvtjiNAIoSXiAL VC3mLytHvgNhMk+3lAF+4TChcdXc5qBwU4GFhBX3F8HgHBQOVAgvY+xP0rpnvjEQnomZ/7mdK+fN RidlwyQicgjkbvTG5QoTAIlWDLCNmPSsI7FMQ5AW1ZOeKdzHyITJp1bD8XXSSh+Iu/I1Yx3Y+0L2 2QEkUidXJMpvtX7XRZmBUNqr8U6z+pptI+LeLhC3TfDhRGQqlyZMGKs9prEH7aN3hzc47m+KniHS SRoerBkFkm1vohm56YbUkzulo/M/RIeGqadhxSsaixyYBDKX5KER29b8erHZclmT5jvuQkV2KXyH HzJzfrLDSrlgbldsVv6hSF8th6L24CLxcHaRkIn2AEG8mZ01H9IA3uBe4AgOsH5U/T7jX/0d0/81 3aZJCowhZiyhb/c2I1m4eKyVl40nHmdC7/zJXxzPlntDgoqhqhfsF6FJTfc00h7YCCtB/jz6Si6B zwt9RyEpRddfxGzV7suHtZySQg0pfReLXIDG/EkK8zxl1MIXdZaaWbo3826uBM8+WNvTF9mQdllO 7WpELNEQrFN+GJkmpXgW0kmCjMDO4edRZ3wYZ68EvLahhZ1/gsjjfehG4wbhKpCwqvM4F2rsBHFG Fvurom/Txdeus9whFwWkHxdo9AiBe3PiPzge3givOCA1kWExdDUsPy9wmD+psht7Vw2QaGexM4xI 8VMiCpmWhM96/vofVUn6Wyarxxn6r1v59+9hkpTg6hbxoM+0iiv9LqXO8KN7n3ttuGZ/N/8fyQd9 duXNzir6DrUrVbZR+8pkARGfaGcBlPdY6vsF+QKXk29MJEaGcFluPoeg//1KP/cOM1dv9MCjb5qX hwdLb9zNjSMLcGHHs0VhrV1XQUtvraiZrsF19Kl6FMIjtujLEFzBLuX3vbEhjVqLK7Kq6jHM1Lma K7PFKX0CnFINYr9G6k5mMflCGWJrMRec1KPVT4eBM66gUl+w61cRSJDnPJ8DjRbSY6dVEm3kn7jd T7U+CBtijextfv48C4eZ/aEq65s7s7YxefeA4KWKpCdN6yJwVc7ag4q6bCSpdFBemhYllTRBtNvt Tz3Hl0bCWL98DpeHudT5TOrsGJnSLU/G2oc1fs3T6pWe4BYMtOvfwWPQaoeNOlsSGCtGAbYP80iW POk53V2yZFWNZ3i1b4OBCwszEu+URbu/F9Eyz7TweqjAOyoRnAR8c1rdjgFgzX8e5znnelIA25bl pl2ZGDc0wcvA3NayAqUUc5ptqrqtAZ3woHyT7A7/PEh+MadvbZkBqlsgz72fXMfaPQg2gXpJ5Am0 /dkZGE33Kc3S4Ca+hCQ3o0RHFVGi4g4FLdfpfmur5b+jZgs1v6IHPxcIifYfCZ9mbss6MIq42qyc K+CyUtWm7rhGGrnGNNIVSgLDVl52L4dBHBiqKykJS5M7gM1q6/HYfEniVMb5b3xhIRwTfWlPB9Gr TvcTei6ht2nk3n78HId2WouB1tsNPxHKlsCvup22CYi8IlZ6ZqgibuPZI17hUtmSzs7j0pN3Di2H K13Iijw8hypskSb9B7bzzOrDKmxzJf9tgu/R2oYsWz6KICI7YJJfUaH+RmtREfouj3l2HLCho/N8 UBlkRuusunY8OHwT8TM0Auu0rZ//dGHSlNrx7dgB/Ibd5PCJgpXOLoa116vidEN2gF3l2IaRfctW KM7Yw7rJpxwHv+YE/Hlij1qE/0OtiG7AfnYv0Pb/L+cojR68htb+8vONriLsL4t1noIsK6GNFygB jw220Q5JOwwqAZ/4cQIN6eAmfzrSmLoEWDosE19LRt5vb+7sRLhe+91DVZgXtzQDi/MQl1csafpP ahEyAikY92UWw5jMnMJ2WMAjQ1QYb30yTG4MCQKvtkQ8LI/+n7ZnFuQwwAG+jVgsmkzQ20T1l/wW 9XMk6aVD+hZ2EbSGCF1ZIo73JKoKLFISbTWDrHzMRKg+u39FbyadJkFJg8o204FUb3ZmAEuReeYw aw9iogNsfvAksf/lU7vApt1E2eQ61QeH4TpeiGAr3gExeeSnFoOhRwtcXAyVy1NsBejm7qXqVjLX tC/PvopzPzDfYtkPW534sVUItannOIJ4LgFZ8RnakBt0C2U4hQN/IIW+Cd4QzX2ILvwypGKwUquP u/rxetcfAnqZc5mmGDHAz6e7PGV856/g20956qP6WZKKLQjywTinBfBkuxBiex3O2QmRGRGM4UEF FVdRbrAvAtBtvJGwUs/6K5sOT0tR+qwZpKDl1SlXNhV8AOxeUR05sw4vr5JQt8Ragrjq+Rjm45OM pB/WkiQ6QQYsU7ZH88Tc602pevmrsSGbD1tDrZLrkybX/TJQnGVkANfFUcHY0JPhs+KpLTtd3QSI ZTkxhiEKm1SMQ6GOrbyQOaCMoQbkIMzPw4IQ4dKEoEu+mINT4h1uJBIoVX8PIf0wI9wtmLK3ZXEM B3gs7GNXR0UOT3CffMh2B0sbtrla91MibIOgx1pSBn4+e8Tpn5X0hxfa3xXAmJsQYhFUYDkaiJ85 9bnFOzPoQKT/SdIAkiyjqnoCetcDwo13BVtxCBEUn/QXKHFZH8DXldO5LziePVRJAE7GIplvVIQI GJLSpspIJG+dyXdJJjqtrBZEN/+Pl8iXpsjiYL6BkMbrtQ4NfdAQVXE+c3k/GtkTUiGmgVulijSt SdHE68KCTxDleXaSdA25p9GYjeV/QFpbWqZ4uDo6QGNwwkb2nb2h2YQJ1ueA6G5wof2B2ewLeb9u p5YKUD2jV0ViUHrmXbxuam8DiF9jkLkeUCEGDgwSsGqcsBB+nS0BifA1WzYyRzdHo5ozJgJvFnaS KyfgCq6JxmZBtM+03k5G/brev7vCoge0JefMDpYupppMGBArSzqi72gYmEvvxWBMiT0tAVnZmKfQ 0TNowGmUOD8MOJnLOR8abIdnJikUqxFmNm9IrHyC1RMVg8xU4GX1+tu6tf2duXl5vTe6mcZXYkrR FdZzy7UCd+hbHfjPPHIOiFkLmGzmUXuCqMl1BfFlId6fzvAK+TU3P7MqKhp1A6k/7weel+MXxkfb s+FW7AM/7rcdzTvuEtzYSxEi0fKxFRxOc50C9eSzvSxx748iE3v8ebToaXb4U3mqRoC603RCM1pc n18QtNDsuU31JFq0aa4RVoUPK6wFAWj1nuWbRJyUcWWXhywxRIyyA6QqCanDFVVPyEF3t/wwuldN Rj/aQd2bdtv1tiXsYv0hAhOVr7SwYGF+KGYc9wo80JlAc7Hd9YEX12l19YXmHhO7XB8NJH8rPtU+ 3crXYlPFpTf1J21pzyGxtB65zNVQHpuIdAI8ygrk4K2UjgLnyANs00jmlGNplIAI8lRG7DpnW88P rhoHQZtYrl0pakB4ke0SiHvCnWirFV/2oUxl1va0eN3anafotinCJNQYt+C23dxmQHi6FhkKE4dg Bl6pQ9MzHFB2BcSVjihJi6V+Bzle2E0sXo0Y6QoPh784lIAIa05yVBD2R+R92wgIVaysYKlFP8AM MMpVqP3blQ+7CGOi1/IkjhcT0dq9SH1fz655G63kSXBTYF4I4ZqDAbgmIQ7uCn5h9+K0uKmOna/C kKBZMirBU1HvsHKgE8VEpc0coVMqfu8brjjVN9bxMtxvQfjFoPM2/HzBmrLDFhM21H5HbgedGepR 7dfu3qrKi3hjiHy0dtEtJzQina6oARWlJNW9OaQnh/yv0iKQqumWTV2oB8pP4SHJxvz5o7n3rOF7 yLxPyYYzILGfSiOu5e2mzmUYTr3h9nxsXLtzSFd2Zu1dtWj3RjBDJ0+nbmUtArYHDgleEAqq7zU1 ZgYPc+SdztrcyyQVIOWLpMzPA5c0rOT2JOLZv50z6RNqwNGFvZFa5TaYseZ5tB/H88fKgCmSo53c vNfaPGN6suUBSz3cw752lglvndPYuWZtrC2EW5J6yS5J/T33Ceo4N3vQBP8Ho30rtByZX/eKTkys i47AYwttEm0ehsXvOS0lbfs3QHLlpvrimdmCcqGH8umHb7dL+U+yvoOjjK/k4S41cL/sG+mdwZW2 5Adwyi+FeJI4MFTq1b3Mmc1Umvs2Pb34nonlsDMKV7C1IedLrt5cMVk0HZ3FFuz7sweRJTQTSLJ8 dASiqzI/Kd3KqugBiCO3MeaYxYgCjNj8jjBA4xj6jiFNnQH6O78/mXUmnI6q7rrHtcYN+yOVGGin WdbOjs1fDWKdmEJ/kYFw3zs2t54ibaW3S2qROo/Pi4BaoZwhK5QdgrFByO8oATp44wvZdqRCopjV hqdA9Pj93OalxszBpP9baKTEyoOxydsZARNW32z0OCKtYAzYh0SOGp/mVsYT/IRX/j5EasZ8doBV BSwJxALgqsVM/yZ1Yu43buJm0JyPzG63jSzlN5yQJsUB0UbTv+hWdg0LPWpbccaYZ6QPA9WA7JKV Piac0zCYFNEoUJXSwMK38b4+csy/GximWqfrtApZxoFp6/CtV8VPIkDv9VskpXe7E9vnOBthmFWy 7YD1NaF+d328NAB+Sd4Op0HCxdtz8NcyXFsDD/ooczhxWpGkjrc1/XT1LYwmBRHIVgB3hBXKyO6e PmqHzpBmAm/EJ3/bilgq0hkChVUL/rwiS99l54xJ+Aj1ZgsJqPEtopu2GNRCD9Sc8LfDsZJCITk5 D6S0r9IYTUJBDyZ2Ms7ig7HzQJnsGN1ifA0JTmqt0jw0rZG+B4m7omJViAXmdYPbk8iIRVq/p3Ot RBRTzXG3lATK6IYJEZnk3tjgGTSMOfdtX1X2GEQRDRSQZbSydwFYaV/1hulj3H5rB2HRAdj7yY/+ rcPb+qXdMv3Q5ErMVRprheIWAROqmAaN0nYeTnzTqLk0My5v5DOtNH9ymojBF9WQ4Qrq1RGCfSDZ ffRQyIqCcltdpTXnJnZ1pANg4uKjRtv48XFFnoEdTrkJY2z/Y+jGYe6l1BVQEuioiFyaZXlepuG6 HcCSWQj4oi934+b8RQPSgUwFCH16bquTMsmr7qQ9njqx7xjdXPOgUE6GLz60Tk1eTm5RrtnQVquT 1XuA7VZ9WQEZVi6vwJXcGRvmYLY1hREJuIIhe5j02lc149NJcVoVshagoBjVuufbMipEwbqD3FU6 3bdU/Jexzc2HyQP76q+e0TGbtxwpZWwk41hq9voAK/feaKLgj4vZLVKR7kdtLKRXdaV48sCW1ADn Qv1nEd4/TLRsFedUKCiO5zxN6SP0TBN8ycHKLWeboTnIpcnAfvYnDA+o1ow5La/SBsRBQw6oiAEe neRU/sbuxn3/EsERKA977HsLRRczbvdW58TA7Bk9XOTqXnqyigDTMh7yRHB+HaHdWBdcGTy+R1QM KNymHUk4+lzDZlTDij4GruatLiUN5tB9P+7Ap3x6lP40K1/+4ENu1sK0JAnjnnmtrr4QZnLmA3Nt S420kSCbidOHc/DnOHugn6eptkPDtUpO8Dq0b6e9Fv+ogDp10YCIpEwvfmIatPTM4WLsYqBhf5bV EGtu/3rRAz9QzoFRXjhoXlRjhRhXYNPZXoOglJnZgmSKESl5qnhLVAy6sm7wzdg4nb/C8K1t6iX/ fXihdcD4bmk3tm0hjMkonsxNOdyCCAW9SAydDYtLxjIAFnBCXuOs/qY+/xfrYp+AfNhPD04BR4sC C8N+7jSWqehebElRAxGvfh6xAUq0Ik2uQH61Y+iUsaWZ1aL0zKtkv0J2Fr8C9nEqv8DLVqXEdFzf hCqBWmjZz+S2dbdO3Y5m07PmwQFjDlLotOht6V8qz70GLE6W6X9IPs8ijdtUYPoybIFG3n+uCr5N 3Jl/tWsbxRYYLu3fKBYkVrO4CaDP+raQZaq2WZQCajabxjP+IDBdrW87utLwMpWp37aWIsv+kN5M LG9l+O7Zs7kYVqBRmc9cvvWGQRI142Lc5vaVyLSUtbT5A9jkL5nrbK5whgHEf7gHqinEYxreV6mm o4t3xJbLsOFRm6fv+8vYtzUVhMTaFX2S9obEStM70LtmbezCtqv/+P1gM4JSVBTn1G0PnpthNkoZ Y/PAFCJhtSi224ueP/GK9wzfXmd1iUzzZ8lXREOzi/odVf+uRnXeoGE+KK/lIR4qqF8Bmi0wVTdV 0reZHz3bDH/t8SWOoOpcu2w2pSO/OjYHhRpgUGwRqa92NUsas/QWmK4AbBAN5WTT0IOav7liWZha LqWMLfllb8q2Qi9aVPvn7hL/+eUlqeEPN03ZRfKjiuiJSarLDxlOc8yiPYshXo7CYfASzkrwXlfc l23Br24CRAmfpVWheqso983eDLdtu119Em5c0w1vUkkrnYpAu5M1jIjdid7t+xQKpd2u7tIM+Uo+ yAxw2i8Y3b0eJ7PUP8uezxg23fLCTovafuOp/d683Zhs2qb3slOPPch+XWQxuue7fXJzym0wvejl mXgBWVu8RrNHyRhPN2ht5SH29tl0GTtMahi3FI8F2usPnc5FJhMfh9msweBsOyEjFyeQwIrZzTii G7UNxB+izal6fSqYSH5p7dHwi+BzIqtPt4DPLaYeWPEpWJj5AH4NJt7thunxUCk7ROU5fFn73c9l BW2TM+axMGWDKFiPm7ueI+2ZWmtl1rEy1UDNne9wGRIdoNbrtUIqfCxQrKxhnfO+DlgryphhiMHU UWEg9TGegdcBDlb0nuvyzC7720/NX/8Y8v2gIqAJyFXUbb+WD1J4+xq4xEeIBLZABEJUJYoJS/Hm p7RMB3YVA4oDMWCyDoLbzIxMgxS8Clr1X6zoidqsUhb/zRAs4M7lRVP071Ikvmeblksy5s3rj9J4 xB8haiBPhk9zffIz3nyI8Dt6HpbpwwB1qudbSF1ojHGNlneZroo4vCIs2tILVKi1VX8oqt/Hw/jc B/Z4GBtXsVUkB9ZY0uyrMggzDKXrpsOv5XA0s+rKAfeWEOeUJgLDvy5RUl7eJ9X+jR8LXisMq+F6 1MRc1JvrzKHe9zHarVUJSTSYM07yahX0ab7mlKMoICxJhyScfb05uJstfPRDsfXQFtDn+fi6w/Tw qVqOfTD+Q4jsgUxjwsBnUtQl00KV/IG4rBbEBC7C8Rkg2+XCuJNjK2Uiv7gU3uhjszqOgd3PB9uL cFm+3pO3RoL04lAshpq2nRI/HZO2M2nbWym0eq+t65gFsV6m/qCPO7IwK4DOYZ3fP7GiLJvEVBUT FP1MbvHsPuvicrKJc6OKvTQiHung74CTgqwfPji5FNRLagWM5aEjItI64Mh7GuBxxkm44Mg6tfLw MulHnmRl0MxUGTTZAnNlNBLdSn5KlHnWhzEhv+3/Yj6i9lCOZWIprShAt5MmX5W4AyDHmsCNg+i/ dZFmVjoK/NNA5Vo8SozR7m9AXOwhl95G/TOWnnsyn0LUro/sYfO6p4VOywm9iI43DFHu/lDQ8mlv Qz8ZACsv58mtRAPf7/SSmUKCYCwQntGTef374wS/f0AL1FbRmUlcvj5gTrztpz2M8imxeb1lfgAQ a22C/G4PTUH8Z8cySoXQhSq837TgQ54UOVCf6Zn+logH1hQfSvGZY1NE369uqiZ/wpc3lhtzl2Q0 HSWhhtSz6d9oPOU2S2i1a+3i5qvXtZ1u8BrIYhmeUfR/ST9H0hjI65I4KRsvOfVEKlBFiPyJ8h8p xT9zlfAQxpICaMKQqv1d7HGDthE1Tw+l0svLEJPtmZVENG6TLokP9heCAhwi3rHZsxCymMwi4wRC KvU6xOzzfAHQJivBXE1ZK8ceU124BB68HtFJ3pTRV8MlmHhXJ2YRHaBCuSSchFXrUnuvnzrPreRg nNSF9aPUD1+zyXE2fy114Lva1HhmxmeQoaxDFxUWxYJB7ihNKmTnKNFFZ+5wuhbhKWUbybYDKHJw xnmg45e0+CCHfXActndNyFrH6cBhlq/Bmg8niaoWfBgetx+QWL++Zq4ot1w5bD1I5lE1hdCfR58/ l4pB6Mk79q33I81/WOVmZ24ip4LbKBb4lvl0O+XoVslqf+nB9tow2khBVFUzfgpjSgzgD5uoWwpV E+qSvThDAMv7kIH+QUJbPkPYxFkYhoR48p9VpBasPmrneqHq1m/Y1oYnngGaWDvnvQGuy+7p6isX yX85kNCgW4JjLC1oHzngqYvpix35TXBcZluYce9T3OQKmAvlyLgj/h3J305tcoQPUG58CRT+36zj gIOSIdjlt/deUlc5RqwhG8daAWrxMKl/DlbcTo8XIknXRrgKI8PpLZDT/RVfZ6eGQRScqYO/qR9g o51R7TKsswGh/qoYeP6mU140HbBXHYEK/jxGgMtv+cA4QpEbuHxXREOeaRRXjUQCJbJ8gKgwWkOJ enirXT/F+SV7GNfCKjdJg99bY46Ya19a21fzCa+WjTTjdJGJ1QxSB3PyGE4S4IlaQ3R1K5aqQCoU 3/iA4KFwQQAD5XKEL3L8vOnwDsgkrsohYvAPY4bHCevu6LKfAFgZ36TtCDbvu5xlvpXixDbowr1W jEgqUMkTguXhQ3oqhlCjwwBLnAxoZ6BWef+6IhmAl9UjY/t0dYM5jjLtzf5ulCV5rVX7VDqZWseI z3raLoy+holJ78QFW08cELM6s40JGZKhCpi7utnNgP23r+JavaL1QZlBqIJOJD1Jd+1go16nT3Np 1367BFDA9v+rXCm+tsn5tqgHoYPw/p9xKd61zY4FKbesCl/dn4kwevx1ZKE2oflex5E7Y8uTF6s0 ZAnQFvTGhtWQT7gWU6vzDzk2K6iiYlFlPbfm52QFroPcZFJvHAU0O9xsfNHYWhjcfB6ZNBMn08No fOJxfqClyG8k418ynPUan7mhvvTFin+IAGFSI0LQ5pvX2cOB6wOk5nZkEcc1jdaCniZ6FS+w5mzk gKwLa2wQ13BmwipFp9thDTChNlXiYCZnTpHHfJN1HfUo4+PKP9DVw9u/UJdtR8mOn1MYG3Y8PbUo DZ9lBn2aph4lA5SV5IvgiJsdbBPbX0O724EYhrH/NVu0HTg58aEDOLwJGuiuT6ewm/4WCmj4+4RP ri+TJN855OPho/CJUmqdPKiXcr+4B3VDUqOM3qsdz6pqU9OP9YCDPPD7/Emgd3nmVYSX3626Zjso BSjyFUu9Kd5QFwecvd356eIJM/TyyTidE431QMih2Aj37ZIAiCfV+RZZV9PH6T9ymeBioVS+2un0 Sf5Y9o7VcckED6ll0ds9o7X93fKk0SPdduFJu5rYwa8saRpJ6NjDE6h0ArZRLrs9CeS3psrT1k5P mZ7imUxqFABBnxf9Rfkc2gYC3fLtRgilTSqDLyWmRrbqrIkcHtodI75ecBZih9i+HTLkPHd/dhOk nonAx7RS1fJUkniYjvOlpUTynbPHqHtbtKkFG+y7I/rYzj9Bbn4ViGbfleLtWkOUmWZHKqR13HOs ZhxDh0aH9HKcWRlx3MjTyDnTHs0PHNyZrBEX4xIXkzdIutCzXjF0h+A3kdPMLA4Kc5sKQu58GINb gU7L8JdVXY9uqKR18bjbavD9ElgWHsduTkVTPHJu0T8cq3uttLMzu0WwVSZurAwPjRSw4pGY4hnP MXE2xqmqFDqo9UZJeRjjs5wAo8PngsdZCJjFvqxlSECeFb6W0JZUrod0N9Ct7lMQEdsCf6IJnTZl c6za056c9PYlGyovzUG1WgaQoDNQ4spQr1R7vk6aGO47QdnJXZnsO47s4G8uX+tpkC+ZqpH9B7J8 za4t3Qh/PCX0+aoa4HTTREQXHY92cKrIQecCB9TUmkWnunyRB8Rl6JwBoaYNWZOIsW8gRyo3jiom iVd40e8UB8hlutp3GFNoKyRreGPL/o3x9fgiEU1o+dgjGzaxzlAS/wQ9uizB98wENj94qPoMY5Mp 6WXlnkffV8lrUKxIbqPlhrcp/MDv1a93mUI1uJvhRuJpC+wQIN0RF7k+8nVmFKpXlcqeSL8jjw5q +lO0eknOUrsVxpdvLo68O9dxC+i1iWQxKVJYSQpCdkk0q6/JkU/4G8t8yJ4E29ifPkY4uDUDmPUb JaXOPdmmdzXuFZCtz1HamBTTGPha+L40fy4Mt57WbYW57sSCFFxs+H+8NxhDbPKV3Q5NC/NVmPKx jjgFyBN6vdvqz3LgLR9+SbzRwPLoppyVSHOwnE5JEkmIUtRbL0AI+aT7zlM62tIPQBkTl/ym6w/E WOkn81ibf6a/VUH0tXLZ/QghmSzj0WiJh3F1H5bDn3f6/Gl0v6FxK6/8fqf0thRZU+nKy4BPuG+z R/9OEVkR+tnZkGLI9zMDKpiJJ0VMHmPUDyTA/UmG0YYKIqkMu19gMtZxqawTVoSf+jKsFhXIiS3t Y7xIHsjbCZKjn9eax8vpaQUOoeQal9rKy7ItoEhZgZ2/QJbLjvtMEt1IhozE55E2Ivu+ZSoVLxlg UMuA0UCw2WYBDKgO0EUDY6tUcwqrzC7sSr0yXx0/y16uH0noRKVG9ERfdoP8c1DjiH1LfN9/lYoq PFm0TDp++1QQZWp81IGHxOVW6k+HTp3QrlwbGi2MYkFS4lIDt6OeBGhRtROSfYadolHJ4w3hSK1j G4Z2kKuQo/s/YQHmo4YBliv2968Ujkix5TilRQJ1Sv1YKQeYbprXOqeguKYy02AeZq3nPBPyw5e0 a61VbvduzeScun9jB+hIhWQLcUmX2RaF2FVRjsw/wLAdN637AlmSqNWZLc6cfNQiFiuENQ+NvBWP YyTmZdjuImXwgpZuCiPdgMDVcz+w4xsHSNjimsLyZ3dv/7ah3dU32NAYwT0H/KF7q1f7cVkTnFqD aADMNLh9JHOZHdpXP3ppO1DNelSVD3PX1aMkIZ6kJrAI/arcdo7RPuU19oxddACQkYC+9fDDqxE/ C5CL41sCB8YasR72UY7HydtkHtboaLoOuFjlecLVaA0vP7Sq8oION4uIrhHOYUQfY/JMQCUiht4Q Zaoe5iVxY4eroQ84ORtBiqiRRACA7olSAHeGeLLilOzIWF9jif41qLNntef7OIHq5+omPWCoLrP4 DCy7cNIOkGyv87XAbGbi1axcCUGGD6zePAqZ49HcThCZFPsfVXVVnzeYmIaT5e5cmrN+K8hNjk99 GVoIr9h+yXpLVlEJheKYQ4qAtASwp2HnGV6h2GG3jEQdrpufQDPogiLYDegCm6jTcCCnLDP5aKhw u9+pheWPG9YjdXI6xpZghkyAH8wWjphiCyHskZ028jxR2+pjlB66LgIOHAN9A2xnAk+JME1c9e9O mPar2mBnWotfmnPUs0RFEaukE8Ia5+xwHRCfVaGQxH1Fr/dR00Nd3dCeIZS1SNrFQ2OeWhifINjl RBcC1KWnYIY0JEBeaEcTSfUm7pDHsoEMKAEnwdy6uIT3UgKc8Q9WXBLNTsVoW2bqe+hmZM3t+nH/ eSNx5BpoR+LKy2gHzfoJwLspwFjV+WGtE1e0wpgU7UZwGUfqggKxhC3KlFkI0eJv1D24WGC3p4KR Ud07lnaRHCAb85fvfYm5GK05PAHU2cRikIZcb/4jeN3jiWiD9pPmjkb3CKGFp8RHPbcfzBROPO4z 44sOwObb148vDQyT2L65kvhu9JOonbTwmhTv8xPvp01f83d+7ua+jKGmbYakWA6aEfWWpgrmippO KEEcTQ/joYDIiARUnWhmJDdwQ1DS7ym9eTtc7IWbk/Z7vgVQjNt73Q9xxcy6mRFmx61Qhi4W02Jo kshGqt/p74iDfBDTre/j6FjwfTtq6Q1nyu1ehQRRzXxPAOU+f/81hWzGP8I1iD668n1Wpa1ICuWI F9yfF9czRChlNarXFxoPDsNeI2m7oroiqE4riVdt08jBzsIqAxsX3rYhQHTDHhHGMzzIvSHEYHB+ I6tdoyLbKbqgYqmj6L4CLXAj1kcVQJbT8LqDURT6cqqdDb2RwCExRXJIJ/zqpuk/2Lt7h2/9E8yo DTxshDTxlocQA6bxqAvR86uJz1Hl8rQnG31sR15UeTCt27LQRyX9FFq9z+SM1MNSfQIDf3ou7li4 oA8Up/LRnvVSUPS7dxw3OzRaT7QIL+aSNDFDzzpYrVafSDCQx7A9RvKRBfqr0K7bPMLKd+JhounQ lcj9j7mFDFCjbCwbw3sBwsvwNtcGQbNEKJKx6BuB08VtWtDnE9M/fIlXKDQN4LRdXSBNvpTXta5y aX0gq4u9Fd3nZwVbxhdPat2A7wO8TNYtZwBJNp61PeE0nbxpqKpBx5s4LiSTxSW3YVFsyY1wMPug uX2YBiIMCWArCVoz+cQdIfBWFLCT7NFdkqVNxq+4+PFtBALC6FhdQQfGJyOT1NgsGwDhL7pHKlhC 6fXzzb4p8SmAKDLWhDu8BzVvdwOWkUZRQjznu4Aa5/0LfOQohSLSN/nxeOo8Yga/QZKNAJ4giSFF r2/Dcx2ytpF7Tujdb2DKP7PIgo9pcAPqQrzzLTeSuFqipfkU9mAiBZMRgCs2ByaGiCRvj/bsMxcZ H9gkLA2y+UMPpbavvcooGesaNcJ+EacBcQvyi9xsJvmS964rG7tYZawBszFuP8ZsuRhoU0P+b3Br 4eIvvBheEykTu1147gZU2YqPTVDCOr0JX7WA5gHzSNeo/7ZSMwQgd30N41X95Z4DULcf6Lvg5p96 QvkBCBUCsFt5JSwZf4hAbsb5bIW3X3vTG4XXpfCgiWkWrdpQtAM1JqCOBB6EnQCfnXfCmBxhxShm AOSrkI/TysFV9UQlGCa7nNYVkzhjPzsCouimYapRzD+sD4Lwkgh36bmsdNtsTq1/EMRxlDFdpdgi GLUsEiNFSad3U31rQuG9dRnFb9AaQDNNOIF/zBAzIFfTHezPh3CzrHAeX/53SQ7SVNq457SaEIb0 LBtvmJuHBkpsJr0EwSynzXKdN9kmODPquSPL4xdUb5OS970Xm8JmB4JY4CGP/JwaeTchHrK0+Jd3 RX5Eu7TXm3375LRDPyHvjzJKnE8HddHIC1qFWG8UICOFZp0HmzaYXIOhCP9AprMwpwUb5KiLSpyy b8DKSk9njmWwSafvCOmbnhHHIKQfPeg+IKUeNGcjTW3nQULhM4Qi7ZwjyNafvTE7za8yDI0S5SC4 0zZvBkDVFuwsONO1A3HW0iHo9C2csgg49jMePU0izRH8MEhKoHuyLjL8EjELVwBsqw5YODj69Be/ 1dJb5Kny//yramuhVYDO5F88V2IwtojF64rgWXXPLj2ezbEPCisGZS9rwBmCR8TW5LwAktLKkW5a N3oHmox3t9YfBY8J191Vf3KBW8BS/naYK1uGyodKIMpZlQCbR5C0xp+t/YPqp05xYCrFtqhWJ0h2 YngOPCgB7UzN+xX6Nnw3y8GECjZWdnBU4b+KOWV4k4opWD+TeKaFloR6gSpJ1tgwGMw7n6a9aiFu rMa9Rp0MR4A3nLFhTa7fabgeVXSPnBeuZYR/yORnXC13jzNQGwC2g5F71kNhHaJ5DHRkEYaSIPk9 FMr7bzd3V3a1Xosg5lWLWs6Kc55+vIvsLMVRiejUmHfbEEzmqkw95r2rjpZDYGF+i8/yXGcT8D8n nKeGfcJiztXSjQNUufiHIvkbjFzctfVuIJoWxPEQR0/QkbW4k9HMd4lvDBDsZN+ztsYhJjHNWZZl tFhA/2h59YUPnR+mNFGmgqdazb68mANF+M/HhynHHQ112XzEREY7p7y8K7farTlS5PqpaNBebUUM MAXgGNHK8Wkq9y95ihaA3nLNFoyB9GfQb3W2ESv2zr2Fyq+S1OD7Lz0KttKL0NKJD8V/KgO52Y+0 crYKYPnq6sB0EeHYmEur+yqH+akHPHCTqvnUvctZZcgaXQw2gZsiiyFqOnqHKpoUahaXWC5/Z0GG eiEn2RwCec/IxJzT7ZlYDYLI9QWCdF8Cvl6NuclroqRkCr/IhpaXPkrc/dfpbt+tDo63f5nfddKw /ad2+LJcgiexfu3hlseFSs8u2euQu3jeqL/K2YzgsZQcU21vSmuhmnFx+5ogrNM0XxLbN1j4x4Ms oXRD8rC8rEhSBr3sdds/rgPZNovEnZQVKd3Dtj9POZTs38nALU5NHoz47ugBEOEtr9gXBlNv5Pvm Z04uB44qkG/bvZcuhrETF5fP5n6R4UTQV0msD1jqUfdJApftYuE93K++3TT4CaPDhoKTX84XiZmc eP3U6Rd50cvz2kLFA8BRa0Gd29oc7sJg55ajlxxea2LDeRgIBW0BNtp8tKLFvGZcHkdj68pALGXx 10+NK13a/dSsx8aHQ7rEUheNRXeZB4lHYA/vULTxconPlbRfAFTkSZAqNXVweSqKVr44/BvEl8fW eN2dSpc6CpGCF9WesyIHfxvdpPZDoRTD+17MboCLhUeFqjwok1ifkLU+6S18dOY/VSwrWf7WnHNQ T+3uJzjEuRyDo1WTYTWPCQWdKYeGyhW2o5t1yodAibOq5lFGQCocVkl8jOhqIT+rE/NEBDF4LTNy ao3u9k4r6kV5qhPspO1uZe1X9hxbIDnTtGlGj7UViUu2w6E2Dpeelr+wAHABpyYiWlIB9p6llfzb ZKBxSkWSSdv4/j/lYpQYrSHDa+f4jns7OfVI1nIEQFLMP7BX+5ZnXJXpJqCQONQ3zncDxQ/Y5ooB fde8mJmEpVL0bDdEvsY74oIoB38P+A9dOUyZVZxTx0XqbYb8fMatsnMISh63QWgDqzGsUlPR+bAT slsWjdeyNVlPZRWxrrQgo/oxeZasvMYg1791HfM4uxhhtG5PSAPuQdJ3gcJM4V+8iQrIZDPJ4Xgh VRowr0z3xQmoNihQWJ/Ea0hluEXQ1DMo6NrjFHQeaHaw2fs8O4CdmdE+PbpgqfrQeYn6FbX1fQPh 7/jJV0O5oMcAbHXBkmFTgWOROc2OycEN0W43TcUd8KKc4wG5SCez9MnuDDMVtJsSlVqNAYiXEg0U dFBCbMJDAGFG+1GNZlSJT8uUZVxDnC9jrQmojUkPCITbzs+OEVOMowcEZ8kb03vSIUnqs5J/dxSb 82yTmtB9dkecIjPhVE+aEfkcOY0l14xmNc+89T9OwS3nEGyQa06/2cJP6cZCp1sXqbmEAfVGsIpN NeTmc13axLAyCffAhnjH1NNJEW/cezEZtwB4asPg2qHGm4W+vdjDfhJHXozoErSf5qECaWa3NuA8 5+mhLSLA8iAd213Eldu+6ShwQyiIyOTXqlzZ+FiA/SGD81mwwOqNCaTPYHPSVoaSxmARjjzTgHkW oTl3nhnBgEtMZHbUqB1rDkxPrrX9qDQh1xBgcNGpe8AUMeMAihn8B/6ShVE27vQc0+5F0R9g60tZ 4JlDwYq5mvc0ThLsVaT7Ha3tMO8m/9JldwyKVcrQUS7Yuz+72qNw7NCORVtYLxbfpeu4cWVZrfY/ n/cAjp5rHjBUULKmIwMKxur7da3wa9z4361o8RKVh+L0UbUSjc1kWkkyeJUBCgE8OyFiQRO5SDYy lWVRz6gSBkNZnvfOleUgOrpg+Sd8ZMY6MvdysBSoUNwo9ildkNu8KniFTUA3Xza4elFBAsHvnn4x QbKCpIwxdHtu9if4L/0nhkFcGrgZWBMbvjmYm+mt/QrFD75hvQuTWsL09Rwo4oc6trxrXVWEs+dd 7OTTRCpyW3P/yXuc+RaTauhwGkcUueqUyX3TvuJZ2ZA39+XCjVaCXm9NuH3t+yKeMvXTAkHGZk6B D9PkQAxP+zOyjgOHQ5a3z/RR+cLy5cArgkzUwmrFJMBGO8+WW07OyXY3QBMQ7OM4oVRp+JWHUJL3 SSeKAe2p8/iX0S1K3NtCqclwQurnTrv4HUXTrvTU4rqYP6DCQWVNeGyguFo1BM/0o/ucnxwauwkH j3KOj97/+5st+5HwpheQkMnRokbnu51OwYD+7lbggWgOcjOVroE4/swV/WN/22d+i19R4LquGjxk GzKoLs3s2d5+FDZ5jG+Odq3PVhk05iViwiTvF4ZOl25mh7YNFkdrT04sqQz3AOBs28fyPJrHDJik sM36TF5Vg3qOgaqQl+byP7YpYZaDjAyFxkzEM44XTV9pNBAjeJRqJTvsKcWyUDbHEYS58YlZr0Il 7UuTl8dW5GSyt/X0/BJTDM9PfDAPlY8uMHsmDezXinPzAiwOtPGvWRZL5jjbM84jo+buHA83zH/g MFrq+OEGE/LuJlV+byCeMYYnbUB5dRo1F75VC1BFfj9Ocg8KMLK6fQwLk3KcMQdVNA/B+/PRAdxl 8pZA9wDpHsZAdlUiE9IMXU5IXorac/U1eQMRqij2Ev71zkt3OzVn71D8rOpXZ5wlcdlSKKamqkFa Vfpd02o/FIqoGZkKpK1A60menvNgq3AjWqtkCTIyIhBBnOs1kT81C/h0F+j4D2Svot9h25heKWw3 lkcNzDDoExjvgDLaEECt5pZeio4GdXd+vOJMTGWb6n+4P8YkqVtjFBIx4z7Mlhhp46wLG3rOAVBG YBBy7mtxx1grOyr0ImLpT4PAGKrIRt3m4FJp1j9c7jV7jzC0kRVOKiLq+VKQIzmRSo0WHwHZ0GG4 6gMfZseR26nq0JwnCOHOLrFz/ctu8s/xncheong7AbJibALtc+/j09ZX3wIDa93VILudlFKWoLyB y/4HyPK8POIWv9HyEw4Amkg1hD+D3EjKmT8QomdKP6lT4GqQOrkug7Q5rViZgbREC2Il6xEaAg9H C/msprYoXxfSy17NO3q7cXz8AtHRRdU5oGfAFFmAdCiqjBxyRAvvsuAaAFsUBGnqK6ocHOmD9d2I eBvoJqP7v7xC7M59taVezs9FC0e5rfcPJGAR7l0NHiVX7/Fa3TPtUuH878oM1+jZN+Ud9WpmLbBC Ff0lll9C45p7c13PHQuo6Wg/JAcvvRNSxQuu3D8dFHSJqOI3s8dSZpeGwzJbBWEPKU/rCy+ppTeP tAlNf+FduQB0Y14XcGXjGWHV/de14SbdywryjN7bpQKWOuFJqa75cR74XlLpzkEt73uoSmMblwbl vBF5gQLQVDmggUhAN6Xn/ONmZpCqdV2xhLJFxh52lWYyEdnVJ7yB4x4OANUD9uulnL6SdyRN6XQR 68zIDZG3Uypva6aB33YUj8V4MaUOLMBnPW4AQmmDV1gUCjwJALvuErwvztcTOiZcx8KJm/qZdc7M agGJudLPJ2Bq3/UTIgb7+P/XPo49/Hoxqyo+cz4YRREPCD1RsU/UeXalk9HNaxYk1LNQUJ/85Ce5 OCr/QPkpwh9xvFJIQswDKoTss+8dVhTG8F98M8obHrS/5LDUkLMMHX2yhkG0XY0gT/xnywDEDPkK ULvVVBJQkgFiLI1aZq6lIs+4oilNCv0s9mXkoo2IVWCDFuNbtzo0ced/yLZ9jtX1Oerm3HyrJs2W eLh/Okpqy974gKHsfKlODzoftNa+1oUCFgWNeAssqvO2aYGIbXIJziipD/GkvpsNliQfKUF0VhJe M7Fiy0D+YVNzoz7O7zjXrnCws+xpvx5WS/riyIn2xIGgTItuWrmZ8yD3Agq1MAtlbsw/VE0PN0dc RMlr3TqV3WlAxPFIJolxGpHe5+DVwEsIZ4pJ5gD2WiHs0V72LDnWvUzseSaCNERqUNt5KSICGXYj rt50xpJgdRm2tukV9rxSy6C8vp9D0HSijvG8vbLQ+dDvRQEbK9MUj3QiJi3ptdk0+7G37QRIChlU PZo/+YsnkQnxeyQjXkJcOFZvLaHmhmUY0B49X21jWe8Y7JzbUYN89Ev/0iE1FFb8jLrlxrHBzY8M VTcsHHzSOtKVIdJHTdMudlnOGHvpkCzqgcpjnffqnEL5euSKrDl5bJd9S6jzAlnI7+1oklmvutPr nwGAfg5j/PRFokdIZbGtJeaCOPzXqFyytZUNRd/MdUYB91n9/Wx2+UGPJQ7RQzi1AC31w4yB3GBA 4/rwNLFjpCIjRczWLBM3Iw9alR3frHnOB4RqqGa4nohpnAXtCcyRFG1YKsgNTzelR/HO9XvBgru9 AWcohrMI1g1kSqBEgAPGmTh3qonezPKpIvqCrObxmLLUZFeTlnHKQv5DgfHSq/c78BVHMkj8JWdR PHj3CBiV15Afco9Ac5Ire9O35QWQMxNUuCfLv86wtxTjyyzQqQiX0Oy2fZQYCtndPrwmRf9B0zWx Uzl+fZuP/MT06ziUXCJszkFHJ+J+e8U1U0uvUAzTYAzh08sdnRB574l/p8bUO/7sw/3X9RVt0aUh bkTaRzvU7iVGp207qXPMmx/VunJURfa+3Dm7d+8syiseg4Kw78LXcc/PPfvz5N6c1CcnpntgNWoY g6k58hZphBToiQKyxuWoR/Imxy1mgTrJ9SxUVdKg1z3Rtccq7tisJg99y6/dEMx/lHsLtoziSFri lhvbZKnmTvt++aoeQsk7fxDxowjklNLhBPJdmuW7hnHPtXyroVFXsE7RNVHn/0ay8I0AjqZalL3D 50Q6vx4NvWdXnOIgauGrJJi6+MuhNRjqZ9TiiF7SQ/v4dsrcifqXvzyhioA44eWuKFthBaUiVvM2 OKxvF9lplZcES8G33AJhA5v2pfUEs4cCVHnODK6Os5Exd0mDcqVOYxnS8i8VoOSaHAYsJxDj6s3N xIe961ynwsTbIqvBcZlX8m0otmkY+PqXg3cxsCE2uoKRmrsFWHxiPBb/Vxqau9faYILkkqpZVTXk PQ9EMOTbFLbuITrFjrwgYkXVVu7FNvI2ZDLkv4RAN6wHD3g6ikhkqNrWE4vv2VsE2jQxtVYJEwXI +MKUHXTRQG+Jr9w1joYR0kXhGGoA4WkdvLP8exB+OSh2NhNgbf4rIbY+0OccjBM2KfERxqEncmvE QdR0mKlAaDN5zgy13f+P1Liy088oBdEl7UhFKoAcyo6XFvuMrB5GX5T0vXTMfc+kssIPHyuCy4sr YPpySFyGCFXZcsJft7M+TlsSqjAmS+Wk//40u71Kni+dLtcQ0WYRtzl2AMTyyUt6b9bDGTnLRV0i WuBWFWetC4/UQQEsUrQXmLMCHr6SyV6K8F2WuL6GaTsr5DTG9RhiOYPDubIS7QOTHquWQ6f8wjc3 JyejHcpG+LEfj/ZFOlTck22oxWuYdUWEKB3JtaZywTf+42FXv1ryaTC8aGmH2ESPEeazgGvG5ED4 RsG7o0USvs/v6kYpOHzhaxWMMsB1VnZ6qWSLXLtKFXk3Qaemsn4igRdPgMBT15j7f5lDVC3aFVrx wV/0q9z0zkw7TtPcINJBr9syqCZ9+h1se3LWzXReK7wkyU9lg7IEVdiltFK8qoDmbsGp19AoDkX7 FPOueudRqtvDY1qGKj7nHWUrwcbd4GWWVqXXdRBvSPIZ16WrNbEZOpoWBmBbCQuAtUZzq+S26hBf QEg6VdJ7kxMNwOC7dZaHC5xymgUkvEjL01HfGh5A2nx9m+0hzV1XpBOAJqJ+OEsPmyfHsvbszmxp WqD6s2maU1tUB9KdgSFfxcTlr4jjaIEPOwQRgoGLXFZpqUD3GgO9rellERn9XTyIsaNqcLT3AfO9 w8eseXOPAqexLT+0V07V+d7Yib5ewV9XwE/lcbTx/clqz8r2XppbuioCh6OqKdMBuc7Pf6X/GCAR qGQIWMTECCNuOheWuC6NNN7bYC8VsPki6RZMHZR96mc6ftZQMYwSHY6LGD6pg8fFrCgqUZNkGKQj iP6zLfvkx9mTcrYdHCgd+048f/sEsemYZ37UXE9jYVHfTKvgNU8QFo2rs9jDkfSrbw5ZBTCbVn4Q 931x78H41MlIc7PHPtW/UVLu+fjw9lLmSJj0NiI3rXqjnfde3/ZU6B246AsgGcwgcPxpH1kqpyNi 49EbP2IBwowfPufqLC1tSF/TUE013y+S2ehNwTszWVyhq5QvAAt51GussgAimx9DGxRMVpM6C8Jy 3VRx86gS2FJN9x2zDTC7o4h6A+x4AHw3kfEmWDxjJ1VDMxIBwDZ+vIOMVQcMfiNUCvK3sxtB6goi XV2krqqOiKL7f/x63C8E4CXe9CgJjB/Pgjfp3QK+LwBuXGJGxbuF3bew8e3zU9XWxX9Yu7x0jdtE V92Be8/2oDRFYXTaKWsijvwsalZ12D79S39WP5FbrSBn8aQz3E95P6KeCmOeftYKVhk62BYSBNDu 6qYTBg5d3IEV+3MYkRAeAr3xSpQ5ALxj2KjlAmBt9+Q9hXK3a0Xej51tz3/T5BAM18KjJCZdizzD ObFHAPdwVZWwk8fbsACJENrLOB0WVdxlwCXsWnSZU+j4VE2DnnzaJQct7mf+Gf+bkGMBnH7uYUGq kJjPHyw524DJanv8/HgqLcuHqILuUGGLnXAHqGgZ0CfhknVr1SBurovGgXPG9VMESYsoAmNt9bVP 4VMDk4m8tgHGenbRIQz3S4CooP5dpdX16a0XNgzFUkIys/qrksF76c1iyT2s0T5ZiRiCy/Z+2F4N cDJ3ijsFeU8oywVbedjN/0RrnZbTURmLNZbbLfXFgBTXe51IkjX5nU3ug5ZQK30BQA/jzQfomSXD pg9n0lQOjqmeP+FewGNn2l26OShxzHCWGivD/PLTu/xGyWWU5W+FQhMPKlgRYGMP8cU51Vif0fGq A+zdUJb89QuK9fsdGMgtuorAUon/NiAUtf8h8Ug7D+IVGnQDf7nopB6YHfVhSOT7WVLY7YD2CJwk HezCXwHhr0HFi0sqYjd7OD2xVXXXyAeL+M3Mzm37SnoYvikJUBxN2sYWlpOGdW/qJbkXy3hd02zD /que6qKOSO89Os8TTVT+Ar2izJwPH0VU/ijNX3gZUBUd8HCWyv6uS88OKuvndaBkn914KJXlFaM8 FUX4tpq5XucrIxntvFmqNNlHNJa7qu5DgJZ+MfzvtSzigqj/PRAeTFUMWwQrY13ZvjYFBhA2exl/ GfmxdF2pycVMvHYoOxFHBbMplGsPCo7pM/XHITe0hN+aSAaf/2I1yqJV4qAXcWqz6WmBkeW1utsy 6uYBn3hhCMyRbBd95ax9/9JLAIGnf4evB+1/Kcv+a6wF5A5xG0iE12kZP3Klua0d1VuVL3L+7g+a YpkuEh2dvJisPa+EHWU3T3eS0537w9Awj/PYRZ0RhefW1eGv3MIyJE6q0Z1glLv/WSDon2B/Bz// id8+tJ/hNIG1PXea7oZCq/P1Qut7u+9U0ECQPHYqQ6pU4jU+UNSmtH2qA3FsRrKiM33SftVEFaN5 0CQg79H6kN2XJ14R0yOya255weXpUQ95qPDAobq8CAOq5dA2uLxSeTeb9LuIlEdWw1riRCNVE+GY vLYBd/Yes5/B9gPnA6MMajaNwxlrNAEp60JBzr4p9D94FuSokkKoAFVGf0q4wkgdoAg7mgPrdUOk sxU9o+ayVplxklRl4Ra7qHL8A3Q6lNzrSfA4eZSQc7ayLBZjd2uuLOoeqJpdswAp98yJWBe/6cLO KNwHHmsifwP2pjoV7oj7jEwVTSGfFjgLTpiCmzXeF8KWewO2zwXgqVOZmzpMdjjR5MyROZQfQ3xE jaH64rcs7VpadyRCGBErv487Yp4tIo3a9PF+m0oWbioJ3R/1pj5q1TI8J7Y4pHZdq0aynA3aNxQt 48fT96LY1+89axC45eAt3Bpn6GOIEqttiDRBdH9lTVz2V8JjVcC2Ks3d7lAAdc+FAvhLrmegfEtU 0a6IDC+8Sxe/GJIysh6RkEYBC8D3Gmh8oLDb2CzjRhvMLDeE7au0gdrWfP68nfbz0vcN5Ph2ZgB9 HpMOSpdmIiwly1IxkvbbdCEyf1uDEgC1k2iA5hleJKXv80w04W+Wja5zkglAb0XAivH/qzU3g3bJ QNHRAL2AeTcDSRfEp3fKfAWsTL9zkmEWV/YMcxEZdwJL5s0Eg973m0Mk67yyriOxrKR6URAD9eD+ QP4Pd8sdS/yy1ajQw6WuBBL5agRv7/Bx86Re1GcwuBmTL61vqQhK//UdJoQyiQzxdyjUh6DUBWOW mCCr3hlZuwFciVZxjGU8/8TMNGv0znROFnSLj2KsWH9ph7fVjPo+Y6NUNUk4oVeCwlThjgzvaFXM 2PMfpZ6jSgGpvLwfBYufI3Q0gAPQfzIw7zLfYWbsgKUTFCKxV232LDxN1TtNOTCyMHIyuOaBz90B NxYHmAgLJR6kOUJqvGL/YFxVkJMXbuANvyqVz4VWMipOxmySUdcpFEgz78jpUa/4fJZaqckWq1qb 08pLfZLc+eqXGY9UWSmuVAUVbYP1KwufJYEWcJ2doHQpsx0Gg8OjHcUFVZRghbKd4qngxvdSg0rr iGMjSpDqWIzJ0HKqQibrCuH5szExvlW0Jqc/Zd6tvdFG2fT5SVbLIuMNlfR+CNJXRltq9p/Qdm5H FQrwstHhLSUeIbTI647FWsnpyrl5vT26MP4Z7BE3AAShapsEXmR/FqjYuD8sUNozNZ1J3TcLxw3K PAKECI2u2JRyy24AIuEmZbh4wgn2BwqJOmzhms5VQ3yOoxbjRRUI361vDcCuV5uOt90O927GvhT4 ss8jcRuHVsd//iO2pEMwCJl4PtpfZl5RTGBV1yWU4JPnLRxShyVCz7NG6a0gdTZnVUmb48oqegQa k4JzGdDE1UdaEOTbpESmV5mWZiwa9AMuk2c/GjTwPDkS+4VlS/J4quxnoky0vuJiBfmxdeVYZjM5 hZm0ewN+TBHgCs0YzDIaVw2Yml5uEaJGNIbMxi+iAh+FydwKlWjobfYDnUba7Tj8DpHlGqV6yZ8U GtMW/rar6CDlTl3VL0pMaMlTsZuWeTJREbmJwPd53E8Hr2F0MXcHf4eKl3fheOajXzHNzni3BWfY OmIZW5inBTYIvU4F+y+CvNb8jw4ilckWKQ3RXH3R0VvmCY6RZ4c2mm5BeTV91XhEHiivSHANxhBW as4aelyiQY/5eu7ibgG/mLEQb/5wyDaX3NwQMSkzTbhFZuapD1fWeg9REFK+4TWF0BHwAfE6QWUc v1YBo2pONoag02e8nBaer2MzJR5hme99MXuh6EC8MArVzXQ4xxGbO2uxFIxuON5DMdoXs5dk8dCN 4RgSVCF1EfSRwNNKFXpjvSlkrntaoNXbRsIlfgC40S0a9R/k7vDG/dSVXwrfLxOl/dUyWBWDUFYp UI7uvFxANWyXemDb/XXHl/lns9bx4lTbfg7WeMhd6FSFi3efRMqAl7HSoh890Jb2+jf1caMcSvT0 /Y5KKxqD5PrdD1LfaHs6NrP03ZLalnbPcQqTilwVskcsNvsRuOPO890ZEBsBKS0XSQHCNTn57Wra cbUXO0gqq5VWoA2ldzDWRMb7zvO8x7FRomaljIhqq4hTamnwvTMUruHSZIgkOu+cV3XoV+aGqXq3 EtRzGqOxEc3+h3zDjy5jGiqeM7THKmsh1Lsv3Oge2eL6UeWpb1rcY4W9VlBdlSPxpbFGH+aB4JXy Y+VUEVL/UerxhIP31zeyEe2Ulxe7gtcmO81lXkpg6ZfXBVQ3ClH8dVTKE07rrRToHqil5irmE4mF PNQ450rdPJmNQnwVDR0vk8UyXhIXi7p9Ax4XVg0hEVbDCrfUrEs6LDipBqOvlNRI9AtxG22JzF1x 2lRFar9TSaolJkw1hj/a/vBH+K1nH93Vv+db0vlAWqrHfe5NLhACXfzFQvt83ifWgnC+Wz6aJLPO UmKiQ9JubdcAjD2++JC4WNfX3gA3ikll9HaC+5TCAd/3tGSJcv2DyWeF2APXSXbrKD0VQEBuLAB7 VkfKwSwEW5cz12reUjFFBlRO82nC4Y1rMvaBHZW0S/+a6z7WrfzAI0zbmoWMmrkt0CR1gCehIcAL qu63kgbucMAMwGSlLA2UOQUgHy7hDp2A/+Td0stYAVyzkfoxLBqYP9vwFK9c6X7ygBphZmNUmpE/ V1bjzajqAJxKMoruro0CQ70hdPJh1TAkAq+WOUzrCpLf9Uvjmt+m0Ke6bTpuopiI3BUM+fG/4poj zI7HAMZ+ZuPasmd7+jI6GPVGK79UefzjXWhakpKbqCsy0Bo+uFC5l5+DiO2vFLA6NcLrYoidyWKt Og7xbO+dFOXIxq31PG1i9zlpf0PYrHc5zRavKSf+vK2ARkkSpwwMukUmc9N62CeQKA9cWCz5O+Tm 5QDRvRUPo6KBKvV9Hc3JHTY0r7i1N4mIlpcboEs6B63ieNjiWVgkE5QCg5m3cSlAbOPzbABc8U/2 WoijQ5LcrawDonWaEEztOl1nnl8PCkH3WTbtS8lItrRJKREDUYEThLWFxy/Crwf0YhMbqIsHNtF6 hIqQF9nw6X6p47GA465bHQzoc/ymP0HYcsOdN1xvC5TMlsD/kz4hjA4G0E9IVPeD30OwDRHKG7xx pb+RzJrj7nRxM+0K+YWR6s8DQq1b2O4XK8ZIoTaDoiCSPiA9eTT48/MaaiwD02vz7luDagm/NKjO ZqNutOpObkgTcn2cIJCjAftxftUI3/HHecKCyrhB6QI6zVdw/Ncsvrpa8Um4bG6ywhR0zBuRXzl3 4KoKK/Y1U1YPrNaDHnO8VfQIHkTvgEW1MDWbsJkjaPkrvJa2t2ukuobmUe9MCL61aRH8GAtU/qK8 Os2L3DL3z/HHXA0kGW7j3hqQp7EfvvX1vJsT7rHAMUM0JHgkt8g+oDIT/mnT/mWYakLagstj8bT5 2yU74VuGycoy/6POXFQkqPXi0nvfJXU+TKc+cEbvi4j9F/zzUmOgYoy+5kSd72uXn/qmw1K/uLCx hJvMAgGiqMbbwkt2hMoAzlLLjOm63t3aJUE6NYllHoUedS7EoEKqGvTdy2mjlAI0qeUhnOct/wFB 0AtcOPOz5O++qxgmp4JUJsPfxCI9QbvRLnA29lWUGOVxeKAcYI8oqeuaKNXGx9LKLHRFpQxXY/sO WtLBqK4oAYV83opy0wCXqBNc+XwBq/CtWF2RqoZ8SHHLjvfA8SpSEnvMGu4K+l5Bn/yrDGH3p6BU fiHAchdKSXH/xgwepOloKX6ADhPfci5s7poqBCatIzHRtSHzS3MNVi1+eYOxeCVFKFPr+I3YfxoO n8PkQIZVI5SvS1UBhklAd3tLIPTqe8r0ZlgUlG10i8+7x2ERjCQqDtISGZ1uTOKh70od1qJpmN/Z C+dAAbZSFwwDEAVpor3QMdm0nR2nUAV1DW+HEsF90qH6NSauYXjP2c5BtraloHlDqwkLIi9OqrhY ltjZ/m6y4XORr7Q4H4gMUixpK2LN0MQpr3QWCI1OwnMGxYag1/ysQoMXWN2H8I9/0XeWnwD/R9ni Cw+zdTiNIqdaJwhcttTEDHfn/KSppM178sIP2o/bN5S0SIlkxhA9JVzSERNPyShIxn+sJquGXrlf 2LQh15JMzrCe5I1aS7r+2rOGmYuvx2Guj3ZtIdph22+pITozXBbmLVqJDKe6DpCXWtT23dBuh4lG Mfg+OdNjuxEixpC/JHK2dkVWAcsiuyZ5lf2Ub6FL8P0ppSpJSKqvhVfBBePn+D5u6yURfrY3Rvml 6vtoCYfdU9UkEBAzkBe0/Rd1eo/uxUmhRMbVp5BJC6SkQu+RrZbIo5H7fdWu4PeM9aAIHdPxY2KE cNl5V+i9Lc2z/tUpUKMF0iFCxFJuj5RIzDTnQxG+U5JNYagjvcxIeb34UfwDXhODWABTxSa779oD ferATcmmPYr79hesmxGPKr7qWI5yqkWn/Sxp7LGn4MyZR96Oybmo6T0rpiZxbxHT+SWsWHGt+O1s KwGK3XeM6SPa8OR+vVt9MQ7tIufJRQltDJH3aev0VwNP0Il2BTzXnLA8gfLa50DOPAU32Co5YkVc GgbHxf64+NPwhwokKOS4ney3irX6or1bRKWZ4BuYRRFzhhNSNnZbEYox6GbtgnjrXf+ZMqtYz3P1 tKs7fLc6zub/cISiVN2CbEEXAmLlTGJ5j8P2GTJIVjLa1ZziGn9XiBpDXv9mAxkgBOe0QImVXxV9 ZlA26o2vSjC3N6k0GtiwTPq+ACkRhsJL55bUQq0NzE5+jUwk9Rm8dsKkXnBHIhCYHK6Of6j9OgvJ A3SXaY8QC6c0HyINPNHRar/fmb9sjiVkvxHHmSFmjQq4bNZJFv0Pzar1AdQCPX0CmAzGEBm0EWkS lJXDxR0apPAj1RDfe5P8n6pLwK93aBJqT7TYtiYfImR0Mzqb9PcoSuZ63XISi5ygLxMOZnS6UNB4 UZh7BMvKucyXIelyaA3IQOBp+sMtHA5BnYvj8O7S4lFQg2Kc1zCdeOhJ9PpfImY3+mcVmNAsQyvp ijZJ54dgBYdlOmQbI4trD66vg0GkF8ZU9aazA+LAkMt9RSRvJ8BUKaTbMrin7QtgG2GtGOLUcLvK gHwJagtfctdSLZksD5gTWmoX5tIHTA8hjmPHi3VA+AorlrXUQxxrbf+fPgGdsxLqpkfZJMeoI4fu Ttzh+nsO3xMvJJUF248+KVAoTSc8Q1RGnihdr+gxL8mebvyVsgtc+bo3vvmcCzMO6nDUH/WxZh8I 1ESmKxRWfxbk/tAspNpO5ZljZPqyiUHST1+Xn/Irj7xTDIA0bcc39lBl0mRdQ1pFQYdl2ev+2MQO 4EpTjaguQkZ0dgmHvOaAwDRupBadfDr/BlkId3uo5Wma5NRmA24uGqX/l/5fIU7yX9coChZYAJay jLOiDtxIeTeBp5DKNEHxK3acmB33QGZvo1BF1k6Rv+gDasWoTAk5KLTjoNqy/FQ3/gVutFxxzZ3o N4Y19bCL8QG/Qjfyqj8SBgT/V7Zg8H1G1LsqcV0FmAgFZtK+RHVZNSnRNyoxTdQv3iTTUy920eEI Zwp17A1hIjm6YH593g+95wHy5Ea0mkPvaJN/HcfZgP4X8QU1B2UPNAa52aKgnsJuZ/rE64upbL7T SlXZFGLo5DR2HbachXuDAJRIp07eryPT/yER9HMYRkqyYepPIBJVTQgqg1x874xutWNz+TXZUUSj +jsWMWU0YySXRvoYcJyJZWurxzwssfDe21WsboIIrjAONe2acQgcPFJEFt1NUaLG+KVqBhbKkBzK JtzfDwOxHyjL3DlA+Sv0fuwBg91EkoqqBakLbjNKh7QL5M0a5mW0uKsGtL7IsCz79pXnmo1pUsRP 5rugSEOeifdjsREIdMGEI5CEBw8iXdRZHJzJKuvMCe9tjntPm6tdtPQAfBGGqZp/0YeDFV6kLxtU I0ptJRWf6gzKfwaYgwcuzI4PLvr8W8fsf9K21xtaS/C4Aea9yr3PEw5pVgxVYgkGsrIa98wNTy7K 3LsQFRQmdbFQcZSzSMz/7XUIG3zBACh4mvMa6uAXPe+PAeUwm9oHJKCUUti4mtnsUCpL5QqLXnap DK25YzKf6OlYmLp//toCcrmGPwPQhkZRVoHMkMaWC5SR3CFwlieqF/pgiCQnzP5hEVbATYkWEO/h JQ2f6U5H/91pAwBJhJmY1W8GYam4jqe3tKBaj+x/rAekEL7FBM+LiX3KYtw9AWNMjcrcJ8kbprvX 2nK5wSYqDUGFFhneea56fvelxGxVln0oVDapuJH5FtIBHQ4UB7K6iaQq3itnq3Q10PkQX1OYQx/K igdEK8JiQCiib6FKBdv8huCrHQ0XKZcMesyNHjsGOvT0q+xiW/8Q6oKiT/vdS+E7OopNKHhiH6B3 8F2hcK9pq8SxrD33uDO9V3yBJJQoRkIYHsEiyurHdII6y54AWgYWtOmX+sQM0kMXm28yOGpxngmi wCf0s8vjIw+NkM02lO7/x/IksGk3r2cn+deDs03hWR2B00yudIsMIHquvNYzry9SdGmLV6wfIy64 EgzQmY6dzK4ch65S54xGrHVuj2kRvQVfx65S9ehUZ6efmeSv2RjPXd5PXiCvPIZSG2tSUm8BLAiG dwnXxF+CohXe8twYBTOyWpo/TeUbgZJDS6NYgf9BD1vlV3XkcpxSCF9R5YJO2hWqtCWsI49QtCO0 F7Jpk3A3tqlq9QQFKQmch065ITP4B2bbS0Byol+ntI/49FOxqMin3X3sQ7MYgF5YnVGFVKV28ZK8 i5PMrg25nKkaY9prhkb69n7J+dL8h2Z1rxZd+47+Ny5o39Mar7lvpsqP8BS5R8X838LYzhcoLaaM pcbGBLD92KSGOxci0LhEmG7m2VW6WsTWe9mTGyOMOgXJo2OyXzepRT+fJnnC4kj+lUl/GRsSRJ9Y tmaIs+OsWpMQL4jXlvBQ36URynf21urum587Ehy99J4ff7gQQLI+PtXGvbmYVGmbTmvQGxQ8tvxp KsgdEqHxx3ZyM8k1ps41Y7WedQIXMWuZ89nIdtAGyIW7APHPmTzcXt900R1uPDWQolqEbRQrx6qn wTLkWzF4CFOeHwK+ipbJ7bN4pia/Mf1jT/xd2BuhW8dSwTJ3fs9KTK5nHa1j/mdPDTbMrNzqL2DS 9y/cK+vAJ7ch/Ak4xi0avMqQ4OKkm+5b8/roPoS1ZmFxUIWONX6QUIc6jQA/6I91o9AL2r6S26Xx L5ZDD3QPiKnbmalxT0hH0U5gd1eJ8+CkiXERVoilBC8TjFiEVqIgLyGAaZjzuT+YpV80arKzde6l YrW//za0HUg0cJSdJDuLRQr1b/s/iGRBuX6CcQGKxofSaA/8UVWMa6586k5VFvtZqaQUNyOJwE61 xr4LjMOQI1iBqbl+Ga/alagjcDVbxWMupQOJnMcXdg3Brj7mCvY+5uNVzVxpndRwOBtfHu1vLjYn KHPZdgf0VFtvcjNV8j0+8OeN1r7yXvxyK/dNrD4ZElBu0a+wikaE1hD1Q1oY/cEQrj4fvkGapf3V /zXzKp56fuCKGLClLZzSef35gphAkofwjlDAQRJGHBmLJ1rYqDHggapyT4am3y3UI85UFLFkrYYr t9z+Bcn92ca98LMOb6BPAUfvy6bFu9SyWcZ4quhZlMiA1Yqp8jQuTj9Pm3J8j0bOLRIunOju30Zj /WWK9MYSxUF2+GEKPfns3aG8PjKKLzHTWNWyFCWRQtsPrpV9OJorBPDg4sR4Se1oPiBjnZwIQ4p0 hb5JI9QxqHF+6J2d75w6nSQwZTMn/f/kyEtcDjKUkEstPIGc4RNjcMji5Ehy4ryTZVjr9vHhRMU3 LU2WhR5phrEMbSxNqbepIiaCeVQObG2kXNeqsDDgH115XWiaQD8y1o8TtukeOGAUoE/YGhJCw+uC B0fD8qnmy71MHLfOjlWx3s0TLOxVqcAVmR5HY73uQVcbY0OwyZI/RPdl2ZTvLSk3mSvP5mLDRalY FUY7C0IAEzVBtq8YX0PDFeXcj/gdb8La+Sw3a91DnkrLQN2H03JUO7+V9ecm4+HynPFQ7A264ApN sTDY4TA4i+N0cNaEiVWFkqwxRJX3xQGh+GuFD41eJkUOc/atBqBIOK/MoYDlhM1twjbnQAN0PzH6 g+fQjv6RYEIl2rbw9tOP6eSeGKksTiUrlVU3jmOJJ5C+n3ENN+ztOTOIPxHkv6NLylhyiQUhdvjp AcAOCdYc0IojHmfa1RcIegTcn5i/Mn4aY2OoWt9Pz0ZLAbdmDFCTuVUhA5lKHTXt1RhYKzXPcs6d 6HJyPufONVuX8c/xn9TF8aC5wTBs36fWO8cKHMC/Bgr2s5EbsolifNPSmYDipmldOvwaZoIv2+cc EffKIXW4IYXbeWQt567EA3r0PZvq9DycSoh1Qht7LG6BaYUjLEF9ekQFqRV7E7NFsX14Gxt3PmUj zA452pM/e1C2F0UFeeYT39gB5eOsEA2gyiq06xhuGj8NMEQ9oPX250CrLuaEBOW27QN4XlqVegsX NoHk3LvdneFyn7Rdqu8ugGdNJq/p4BRHJWDQU14o8YEAGHKIjEcC5cdDpTkt1lF7H6RnzIvZopCB Uua967w64t7WpN+N12YXpgeYbjuAL9HTuJyz7oLzVbraFK7jLMk9hCYUT5q9u9fGvh4WnlT77afp dfDWH/IIROVGRlpzkFA5PITzS2H1zkpK9Nc1EUfLxn5BZKAjjf9GXV8GYLMmEgAlEmBxVfYc15pd cj239NGNS0LGD6e/HtjLkSA09VlnzVjbQMfcqpDhQoETt1tQTprl5CZmZIu8O6CPQN6ZaQCIzwwH 16WanWJPxjEjiQ9ZbsFZ5gN7nkqqnU3Fi9HD+JmEHJg0OtPucQGef9Oyrx9Duxysv/M3c1UyMCKS BUBpaCCG+0g3P0CrDuDX87G5mRPE5pDCEMexcb0Xf3PQ2WGms/6n+6YMVIWghOEe8apIaWw6n8mc QH6pUUUJWPp8X5Typ3xm5atN56hIu1NfhRR6wNEHRvMjLNdQpXevHZ6FQwaQKFGWt5PyFmpfpXa7 GLw/y832Z82lbbCydF9haKLU7ow5SSfYknLXMDUERhLMOcs6hfbKC7YMAqpuKa6TrWW3Z4iZyNb1 RBfope0DbeivLk8vdUPBrkrjuHid0Y7FDBaVGwLIHtJ+WJThntQw4Ru90HRje3poZFpHxtbJRYoV 21uBb3Hrr0dBpLiR6xnXm8bFpjXr9Xrwi7VGx+a9RSnp4A4IoGOzdKVijCJlUH2MwZ793w+OVWaF KSdNfPMPLqzrio/Amv/4ReDXCnQNLmjCSrA/m8X+hm4OF6/bRQxhYZ8hwUHmFL1QvtLaKklHXaYt jEdkZlmuy81Jx8IAbyzJLpNXVdtWH07HmvTTp2EKjNi6g6qIFzbSXfZeAUZ4ufdPbe7RERb57Lx7 240rWZ5/KasJ2Ri5kedjN91ImEcII46wxpyFKhhGQusGJcvyrt+nmYC8ZY02Y53cXWVa5o1viCCh NQ8hv1r4UraVuxpZ2yo1L1Hdsop9/SAhQ2cgm5U2akgQfnXx/DLjh380o7eWvYgMfEqsPFDgcDzM FRt7wdMW/xDBaPtVsBScxUYCxYD5emnnsskhV7ViCBqiMaaePA/RYwGvNFjh0+10hg0xaIYC8zAj Mzjs7yr08mXq4LXYCTkLOtIg5d7sQA3taC6nZ0nmSY7KtEh+aUIMWzP9JBu0ss/WnNrNScHs+0tA ulZdIvMyWvt71v5o/xVa6DOg2IXHZ+604jvzBXZYjvld0IRK2qps9noJieHQwlPnpWESaVyOmtXW T/SRaAI2IN2scw669rMn/fv8knSNwMVrXe2KmZDxO+tx5i7zINzux3VrXBEt8YsdmQHTOOVuPodK WvtCo0/issdz/iP2KcXqNEYB3DtmNCkMkTxRVyZhuovwfMqoVfim9jLytTncQtQnHkNoUwIaRGUU MGPFVaxvP9KnqScjy/Z3JKblEDKsq8qdM6luAAW+N2P/T81xshn1n3eI0qaA1CTQV44e94XoqcwQ ovtgMxUPGuUNCdoXpLvxctbHb6kugXRwdejrkLxhOOYFL1MTRFAYMSccJTLJuuHfXgRJL8QL9uaJ TckIcznlZ5+VOYsnxg23YIFv7e5R6O0KpDag/bi+BoO0Jq9gmzFd6DcJ90t8C7VDuc7McZY56OK8 zWa9zER/9ZTU5uJor/OV1erSh/ppeHzMvNv47sOkOPPm+h3bhcETc7U+dC7oPXh2D64RmRXgzz16 rsq3B1giwL5vNjKKFuKAv2QcB/09GpLWCggI+MWV/nx7ZVRBxDADQjkVkHORAiSsSorZ+Xom4s/S dbVEfFHvSAo2c/MA/npEWNpsvklVbVVF8NBIXt0gwzgSa/Jywvu9k4ricnmXKdSryvJR23hr1EJd YYK6gEn/ZWbRZ9XfPd5QY45x3t7pYiUwOrS40kCPNJusRpsiZRJcDqD8ET79wnZMuV6YPvWj4MKa vMmI/A64BAVYs5h73VTLAyBJ4s/byNmMUbo7OUvqrS2Mo3TKZmpN64JDYe1AOdhULgAhqKr+wUe6 e9/9uGqKKBpfFIV4b+pB2Q/QnTxxmD0hG8iwoJmNvdgDYo7UUqLj9P4tkSRA1OxhcF7IDZb2l93C 7UvmaEH76mqN97I9ehAJJ0jUTz5oOLWffit2mSWncj3gmx5rK5xXPfQl5rzhODdYB4WDodOqK/y6 cOrV0rbsoRdWNe1vt6V1CvK+DZPuYq46XMosw2YsiS0qpH4CIHGuH6Cqlf+As/ZG8Ri07QF1CRaX Jh+1Uae9q6KsaaWHLqj4Q+gznbb1vtLaHcOjQzTFrSZ1BLDnWa0xMUYr9OgeixPqttF0s21WJIJQ OF0481cayTlRu6W/aienx8FvaJT/mX3Y36D6JRsHhgPcjfVkppMMqOi0P/B6iq2Cn4JLZoRziz9Y AMqX0PC14Z0qmw7J590nGnLSkE9AVDQe7yVP/m5D4+E3YwJ5vWzA3g57Mc6Y8ll+jlDKpKWOXMXR y1LKmMVdOU0Kx2yOKiNLQX2JE0IRihCAyFns5gWLeZoehYHcikm8m8er0C34IcNGOr6xLBrXFDZd gpKWD6O52snkUhnpedQQxWbSiyV0ydFEvUZfOTT7XIrxE/NL1r8A+uGrUiPS92EBYk/FY3yRBi35 llQxaGxO3M6K/DLmJwHVbD607N7MVS1fNcluu9xhWUJVIV1cY/zjp/wUoH/VZDlxVA0ZVwSZ8Guc +NYdoV2T/QnKxrY3+hmNONZMkps3rqSx4RWyxV/qAxnJFOU9W6B2ul2DCDMO7fMsq1SftNbw5Maw YXiV+fGUUevZ/5FhhvDimWWs8HPUFqBJKJ4QtIxkQHHsaIWDSapf64MKmt2Nr5nRwXqUdUH2Kfs2 f+N7/USMbpRdjvYefWEjUiREcVSoDx0gOMwC1cCPu8LDZ0bZYiChtkrixplSgoiNwbI8MIGssPTj +UKvj22Z8+Bz94+Cy4AauZN7VlT+DKlJ7ca1m/xEaatzEt7vHDaZWHZpjHf0C6ItKfJWdKlsY8BW 5aVH56sk+um/zDEV0IHs1+B688CaqTrKA+zmVheDi0iVtB2x8di3/Wi4hkGDmIufiA8Pgc1dJBcN +E8gsvGme+SxbuQg88UnSuCrLaD2KxUQadmVbvbw8OiYcvlslQ2uhAiFLnZCtOgzg7iFe4veA8e/ X6I+UR55FsiXxZkk/M7MECjo4PZjx5e1CZE9eYXx9/mACQJj7mYiCc3n1VL05pbV94DSgo701oui iHPxwfYJadFQjn1dUsn7LOhtDAN3wn2DbevA8Mcaomf2vYK7ch3hj+giv3A3R/DN68yeDW6Skw7f 8AKLB/xpAMmbpkmGdLnIM58FiDeRLVRZp+0E4ofnbdz4gsxA/wY4pJJelYuTKBPKyCUl22OKsfEl u9vgN4PsC+9CGH0zDWMjsJVUK4a+1q8FWN0ArlRFCA3SGM2Y9x++Rc6vTrRv+MahoBgRgPXKIYOO 0eUVa1Im1LQYY3a6zNviCgiwIfOpoyLdOarL1k3EKvhaZPcDZ9tBtj0rc8duEr5D1CTnENBZCvso FBGpT8NtmghAxxLfRujJppUSf88iz4aTuEg9nRIRAk4AgU66h6CFmWOctmwOjgF8r7b1eaowGlO3 TmiF7X0i1ZFTuIKwiRRd8HfwIm2vckTNfPtpBcv7Jy/IAvzJZeAPJ+l+n8fY26BgVhdxzuok0iXn f6X3C5mx6fcwB4AVOvm8m5LlFXmmsSlsqBjR7O6g2MsbxCHI7Ff6eUCa5xezVJMF9OQs2JgT2ohL ryAcjKF5lB3e+wJ3qLe0A7JwR3eN0M+3m1096J5SnKzAbejldWBjg05WmK6hrIxkqlX8hElZhF8Z mmS8oqjJZhizvMz5R+lnrNrQBGBmROYFqEMV1D6PxElh2hPiUXZ9o7TsDDfNJp/qayEMN1tj2Szg x+AmTD6B/81kQNh7gdz2iTsz08PHXBsnJMYS6bm7Eso4+tmXcJxE6SHIBOWpRIvumLau8LdfViVA U6nDhbehvkig8rUP9ymshHQ+3OuexHPWOUSqvXxQHUWeNwHMMmAwhcrgQ7Sai7waTPpFjyHAtFOg n2YSrvzh83pnzKkXnFywlbquZ1Nij2EkG7KBf70tDxWRXqnJKEULVIGnINbAvK0OgrtLQFwi97vk UnF9+kK2xPJL9jPEYyDMzGk0i30iUV4yNCuwIGUlohVC/7k9tteK6AuJmqM4NTkhE6I5TSfKhgSe yU1eEfOCeF4JJTlPQgtBHNfsr2fPzqnfK0DdZHw8nTMH9ABboJMX1jkBS1j6hSpmAHdU4Fx3X11b P3DtJ5ee4yp/30QXM4zO3A7d9xYjxFu4J79ZtTKFiQFltIBDm8ZkOxlEFIQKx21eepvqFbwL21aq Dt8azFyvSQipWQHClqBbCDvtNd4Dx/ikC8WUlf3s0c6y3AzCh8VSEU7cD5kn27D+7DnOTAXd0/Dw sl6Ven7ujWnoHJz5IuExfNRe3aFlFk6QAynU8pB4k7S1GxXr7Gr+xXU7jqt9vrxJcWaewrwHPtVM MFSKZ9rnL0AzqbiarMubmO4ZUOWGibXEeyAMCQYq+TYpLEOFHkkHDr/A8O31x+2xkBb7M1mLf9fM 7kdDRfDYw6zdkYMYXH+G71ZhRFo1GP9CkPl9owa0tXNIxfvGP7BE4qgQBKrOvZcpiIGlZsmNrsLz cpvS86hCRk94bq4TKDjKPjohSI/QRVb5rCCiw4BTZdGfstva12fCyVJft7ZSSeY/DA7v+D05OFU0 j1YeaDfCVJPk+9aaM1Hd2vdfrAhOYth/z5YbfXeOQ/OzROiZTxSo1UEgcfVnXZVfKwDSz1Iyqz6x 0mCxoEewuj2KLINInCy83Pl2q1B/eVqGSSq/EzfALS3Yb9oKdC/zlO7m/yJPsjXz6SlDEgN6ZZhd eoQ5zrYyL/HzHGmPMWrfaGcpCmtij7LqeObY7oBVgTZcQMDjBXGUVVIiAL/2J44kqVw39zhzDTSl UEsjMInhS6lFHG3CVPctrXD8Kzr7WqdAMH79Yum5bSkURE2wwc6/4OPNSffH6/jWz8mSmCZvvOlF h4tXsG7OPYnz/5ACCP//xrBVoKV5n/rvVcvLIvFkCu8Ux3GhTk2L5t0xIMykQuuSOUII7qAMOEDd bDFwTsMGT2SZWuy4Bf+g0zyIStF4cZ05jG8U3V1G9D3FuUOBfod1QMrKwcZAqDRs/eGj9yIfxIKb f0XUL/4SgwMOinwv+jml5IvpWlm8DF5D5DpVM5HZUssXf5nBBWTQt4F9Wum+1Aw/gx63vdqhGnei sI2Db+bukjNNZD6TJxml7IqPfwXoGPvmME/MLVex1KEUpjLpfiDJSKFFhmXpTeApu011fnaOBf2X WnsnQ2dACOYU4oTp3/PuwKE2WHuThIfm49WlvbIrlQ7VRYxHQOiy910XEeITgxN0NvhbIUVhj7KZ 4f8VwhrsogYVmFLUD0Tfy22VDdfPcl/56YDIJsblQLTb5oyjRZ1UqIvNxJ0QckWmumvqPp2A0xEy f/xyJb1/tgH/hCYWhODr12qyskUSYO9gxlHn0YVAFcI5GBjHEecv7F/sHEb1sN5iguSQdQb4NwyQ IuwHThgu3LmRUWMW007wGpxOfwb0aPDaxbKIyPvA6l/xFFuDkMKHQ0K9JZdWwXQ5B/mcl69/Gpz/ N+n/+DW4/cPXp8/+7h1jdBLU8x4cMNyDWeQQMxllU369AqJTXLv0OcfSht5lSHE1L3Xh2ayPO21v AuOKUt2Y5PFH3aQXnEnInHKWFau4+jvD7KooC3mgja4pKqOYvDfomCqCLgTtfAE5+lMnEgDn4VmU Gex1rR8ErPgx3z6uWg8Pbwt0V1RTCuzpdrHECy4jNlyPRlvNHsYiA5ofeoBht6oTFXsls11Y85jD LlvVyjoMeG+LBf19CG+HNnOwKpDmswC0qiE6XELuGRNT1g11G1F+O1VG1pRlZ6ycO0JSErhWWTqC wBJzu5zEZIknuFgCpw/CINwYWQns/bxXd+KDw4N5n2QyhUBrrpVtDgDP+2IM9TfYVLIEebW1EZ4a tFt10nODkulc30Ypfe+794+F6GG0S6ndvYtW4ouqR25Yqc/gaoqr+tODXDfj3khfBVEkspfrBaCy e+GW+rEp2+lxhXRR0IWkG42GBJZNf/BKFTMdHPkiv3o/buzMHWec0U0kQItkUNBipHhaOXTbcxL+ I48uTDJpl11RsbWp1INYGqJzakCyW36tHSwWzRq6iqZ2kzkTCz0A2TbPrPYmTe7vSEiqifOuKwh6 KYtc1XfHQOcFHWckqXDgjniT3QVx/e+bYHK7RLba3W3bR21tHOvA2ZzJnCdTNvlBoKfaXB07o+hn RsI+N2BA5PvqwCkytTRFbzxo7wMrxDl8EX6CTrKITgRv3p1BZQh/vt5N6EmuEr5mMRyZ5cA2759B tX7MF1JF37vrP6lNqW9Il7ef3NMzhonq60Y1ARqgjJZxpgxtSL2q4AQDZ+O1G6FKIA1znU9WPBvO LKmOjVXxwCuLrVXhbVVwlR4oQchOoSJIVMZismWeX9zkrTabZOvsWKanhOiwQkV0++2GlriV42wL RCvO7cbiIby7exZ0LrHr1a9GHc3OsMY5l0JqLnB/rE94a+X4WBzKqvmBZVumx8Q6bz3F0CwWkWeq TAhLZ3K6Ms6p8M0HiXh1QS3Ir97mVm4VyrgZ2BQf4MFJKwOIjw0cSp5GzBd9RAsHES21anlF8PPF kFhiawM4KPjIRQKS11CxbRlL2IAuK9KghicSnKECshw9qQ7bcnagDQtD4QKClLTKjstNV7pbC6Yv xzSX/Zzw4mlcCQiXva2H2kIjihjOaO2HVLnkIy0zPrJyQ6FjoB5A8hvU1MYpRnPI3/l0m4jUdHLg 4DvTAd99G/f181jybHl4YuW6H1sTwA51D5I5KnmThSaw/7r0kItvHjeD8wLoAnmSTXbOoqmfidBi 9MPbcemizhAF9K2Csio1h8puvG3a78qEoS9sPldxRssJ4yIl292W1H2md3vv6HvYyV7izNYpKRtx 2ubnrNO9TsYTUL9d7O+t23wn8/2VpdgM4uEHPP7aun6bFULxrv1Bps6g/NFafMYIuIHSwtXapn0u PDLCndBQMR7WrISP8NWHSdLIOI9HhH51ehjY2ZHtLr0ImYUmBW4VvtgJVV4sYN5ZDculhLuXvXba axYldqKKp6gCT310q1zTyfe3UcjuBtkYrPMFqwqqLCdtcT00BNBzW7GFS8/078Gv8PjZBA1bLtvu vVvmtSrpeqJ4mcUVJckiYsI0tdLcgTDJ+p0HKXJrdOIfTMeqH0AiaS3JbTwSJJ3eDuUiumn3+7Ft t27PLDBHsDMNg8yM8P2gzray+w9CtZQD5syqh8GysnJd0xEon6JoQeW/oy5X/+1gcZcTxcxqugor uvr7vk797mHHCpvz5J1dNPo1GqJHntNg9lV2D8bY92aPc4vhK/c3T8XxZtlzakEf4zjfaDK4Kxxn U90h5YzqGz2RFh7RzeHjgr+6SPCe2R+WTGOlLc+wf/ttgvvkx7yDRhzUK6ZjugUjLekF+DQzTWkk CUiyo5ZZBLNNSNn7GDpjLG1qH/EH6UdSKE9NIMTdwp0FqCIz+KNY3i8HjqY4NSBDaBuThpWU5tfC wsrjus9LRaQwpHvRU+FfJTdvLjYvNtJLExisujPGHOEJB8eEOMHPJ/tsvjuGd5kfDm6MZWLhaKE5 EntkILPJxtST6ihcWdYpURQPVymZ0Z5nJvFoEhjXIR87rm213JVY+tiFtv1Dj+A8nV+778SEBkb+ SMY+gaBgbv2vkO/JHdhbUntj8hn9+EAqKkavRMtl5LsFqggAezA0SFTwoVtL2bcp1yCWcrTH/DdK eWY2U3Y8ZPiD/c61x/hOdiz8dweBmz8s3Wh/bBCKb++DtplxaQq6Dz2y3UVLwivgi0enm7KeSbdK OHxcM1UKbVlfN3WmIIvAhlXslLyXJijabp3+GAwAsPn3icYuR3Eli9fFXatPil94bqAeXLNvU980 DXgYOSFcWoAMJzW0EdRzIS+guxpyfUqB16sWKhsqHwG9pPluwqchlukbyfNC7nYqeWpi4tHVZPzs PvVJov7jmptNmaN22mCRQ2YQkc7U5Mk3XB8cZ6hEN+S0gPiaV9aTawhuqHcW+p3VHMZKFbnC5E/x F2a7QY7js046ri4xyaZT/+nOfGGhxy//VLK5fNPyNyy9aAERzQXBTKrV2fv8KC+YME/AIcfAqV9Y GEEUUhefMs/Cqy2hXIH204JCj1Pn2lxiIgz0FNbqTc+DOMsV6BtNcZXhRhgJu9CCysgXle34Xzod 4XHDU0tUPeQ0GZ+aengfKVzhz33m5DYxZW4w6OY3327gj+CogZk3owZrbrkYJcQ79Da2bU+WHvef 0quLXYSsby496DIxbdkFG6R7m3sv9DegfyCN8WYPNRkXKfYlssnt9ka+oT39QnIkM0A0YUKcao5D grGirdRsmCDBziez4S0e1K6AKo38rpSWgLiM2NIktFbBAkv5MZT/tFhcCW2rQg4by4tpzKQfemve izQQknQdTcMALudVzI4DR9D4RyirFhMP63iIohX+Eyb7HcTzVEg60qSLl5ULTavpVkFEknhDcvAy lvqm6aT/Lrx5P2v0yWVSs6QgtZoQyhvh+G7RP8qf5stFFdp6Ti+/v5LcCS7ksAap0ZQraOuTqsyX 9djwzhh8RWuz8rKP6iU4sX1tzfErGi6MBb6qz0c8h5ZpJ5ZI9r3FHReQHtzlsu8QjRHMc2p0Ggwk Eml9NWn21IFMfpSyhDU2B2tUahqAUJUgqxo7AtQ0KSzCFoitCph5GvnBITdl6AyLowVHdb0E8/fg 5IbiZUJ50Kw0soVA9bvEP1A4bqukpLxbj6Okw8hBvDw4Y2cyLku7z8M5urZn05c/HqkM3eBI1WOG k/uEUezY4McvitRfErAC0fSu1qVrwrRq9lOxjzO2+ZWt+YoFEIMw8IkgElJvI6qHv7J9sBCwkpvb mXrsywD3t8E0IbI3V4M57TSlX/9ZZKWJpHL8Mg+x2jTYemqxLx253UssNiRxf+c8sTj7JXrCg3yM kdXUMFy8NsCq1NTHZpnC/8yqwMJCzCuFqIW9RnLEBnEdM+/L3uo34G3fLGl5HgGnhuXN3n+XGUVb sdTWQzdJu/D539n6IqhfbPwIO7YourKLB7wely42XkGeF2AV4bcKfTCs/UDH8nFsspHwyH1ZE+p9 VqxUJCKRHwsMnfuzfJ7VCfavDfnCyWp+Ib1uPh3YFVdqeVPk9oGZ/t2YYpuod2957LQqqoWBn4V2 9bkp0a+XX46NWo+qb1xZ9rfYMi85EwwO7s88PhnGhlsz6d4K1Tu/3KMpFlrD54zqesXZZK1iYCvh TXmAJXi+B4Z7tjKFvttLp0ISt8IzMjJrtTJFZefX2yIk5Gxa4jDcXMwlK/VXzRjQKKBTLxte9H4m UHrMhPk7mq3LIXFEtoTrK1wSfddWKhp/rXS3wZk5j2n92rBnrsUYEVEstJQhBeWeoQLfLUCYnfls KgTKmMX1h+mi//E3+Fp1W4bv6O+2FnDkUTf4HUVp6loh/3HCxgtv7XkCbBujvZeDQ2H/erfuPigt MF03z798CfDZ477OkiSJzSH1Ja9Su3rmuLDse7oHCadnr3BnTXBMX9yHDjMHp9Ea/Lyl1BaFxOIN FmMmQrmW1lRRLLODZ5+kMNFSNNxUd0vMg6tfkeRKYeUYZHvDHX7E8a5EQa3MuXaU42jIAGkz1TGw huGMJikI2M5i/wld/RJiVWZIDX11iQBxASxoA5H7CiERFSlpldRasrr/l4x/7eULTQgP36u+UDHv V9lklVdYciABL4rP/J01tIyO8fh73tBG+VdIyuxfP3Ddrk+xkKt8FCWzyf4u6L16N+CnBI0/zRdn R/xts696KiZUa7tjOlCOiMj4ZrDhFKa/r0edCgDMVwxyuNsXJgwdJsiW8RgRC/xK3XF8CeKrkL8k 2QBCAqJF4CzJ/HFkTp1KFCjLKlRy8iOLSar8px3ZE3pePiLpnA3ZqZB1axVX8w9CgOeXyEC59kqp YeSaUaDD60nhoKic7SSgeQBk4p4+TyWsxNxMI5sxHxI/ivM4MzD5NJWtLQl+FvMiiNSxH0ZZGW69 VqoR2ec5V2YqkBPCca3HDR68+yYzUK47yxg0UszW/XoZ1ZAo+MZwXWuZxTakeP41rgGnpR9mb961 4WXwHDuwsEfQZyxUxhpib5C0JZSX4FjDNyMG9b6F3NiDqsnscd082RVXW6w/myYe5GQxT6tOLcMa eJbYRIEAJ+4fvbGLFqxyDNzf0CYEu22WcXPvlHs19Db6oXfDTVKtNeGlRaYfnlJp27+gXCQtVJ19 Qc5PRTraOWiqey1bHScvbdQGiEJ+gRBNBvJNrVOG2DbJearJuySqxRG6Y5yeG4d58qhhzKcGQVMd jjq+9n7o0rh032VTek/i0p2mBQ19SW7e/575rN0aTxO7ZU/YfvrMsS35lDFNUH9FGtC1HfglaadX 5UKMx7XWGZhH1vY4mdTae8RR+Yq36Lq1AFEFf6PNmK8kniCr5DRBKIqy/3Za1YcIHybuTx2yvSnJ NB/fHKg7Me5QuJOxEnAasyuGVlSzZtRmggbn2h+FajunyzpDgKPnpwUOHiOQJZN9lmuC7A8Z3zYU ceAh7GqiRVOvbII2qZYBmkh6RGNsnPQuuZY1RXVeUVwjFPd45o7YfCPDQVOobWcBse+g2tTtrcYy Q5CIIeZDSXGEKZTZPAYv0cUJ5WvRv2FWgJIYtxm9/kbD7tt06mhB59K+LEipIBFnU9AZZuH26zmM 46pvtEuMfE9P7uqwiF+9/se7llkwBldtqay2U32/wwEr5n8k6Yr6oMGm8593b8+6oYq9REKEbcve 04V/WGJMeNfetLhINSf1UxkTy/WcWQ46ufAPxP+zY+akg8C7T/ErCtNEpXsBcncbt4zWZwoi5byh lS7HqFUIWfnNYrpBorXRnaN7VNA8fdC6m0v8K1KtBoeIvUhr8GwaBvGjvOJ4egjFSYYpYHvR5PDa N8maSr+76KzqxlDqA0jH2MvFnQzCND48p6yQRvLBeehOiugW6iekeq794fQsQaghDSfmsH3LuZG9 FBbfRkOcfPaepBCTzEGpXE0+wD+E9D8l4hpPTuZkUkCbIWMliD4VTvOLfDaLu2rrfX/orxglo0+W uo+sRRxTAi2nmgwyD987a+WxnNSrIadT6jdJBVVm2AIfzQkQ+a8WhDR1+iNSOjdWrub6SpNMWyso l/Iv6jOzwdfQh2ah1KAsOF3VWwaRZPQsQd0g8uTFWs43MEZaTl1GLvEIX/cJAIf1W3Lt6Sy/ShjQ PbzA/XUj9WC9zBxXW+xQCT1xqbfssPVYm8FR1GVjOZEBVmMhHyS+6Dl+7bK+Q3OoEr8vbZMAQBOB kBEEoD0Qc4d5VK+lrAIifEt8rjp+rMLUktng7pwf+0ZknXJ1rFh1yNKDBJOL9GkxRHewa1ceyIMe ttS3DqZ21mBGHtLP3Z0IM50rxFGuonC+LujmLaH2i5IKU/fn4qS/01BtvBZeF9aNX9NaTIExFplW vfPt0cEckoaY02H2sGQodySc17CJ8aUDUo1zwJpQ5E6+eHEYKtGaZFf3+x+BqRnaLQzUlUlYEHHw WeIzLA2fJn9oqm0hmA9BnG7TaH7iTMGo1BGPBhgQwLMDbrbVnJxJr1LfY1QbE9uy2uhPpOMF1ZSS h9pXu9/l2HJ2UCI39lHNocme8txXFBlwhgGX5TUqk8IjTqZNrGRc9Ex5OQ98ngw4N7ZeFZK8rnnx 5CUdIa6oEtiG70O1w1NkXv6PB/teqU2zZ4wyXQ2KkQK2mvq/q+aG3QvcO2CA2kVUPMAW88yPi9xv aRshK2DR1/lz4U8R93XLZaQavnAUpLZ4Nfp+wPfDsXdzwwN+ms+Vlij0eByVZZyRYUFLJ6PPaSWv lzSV8HdPwAFjHfBwmSQORaKphtPlAKEjlzB556v90/Iyg20TCO5VjUigjnsBLbCdX/XdFJuMy5ZU 5d6EbqtEgrP8/VXYyXTr8RjiV4SDtfojymfYqUXlcNLrvYmTdpTYSMHP074WAQK2Q9EisgvexzYx v//oBiNZpZZHHmxXx2Y/i55rKR4nhHMS/+xIiGSay8SBmLhhC32a5idg4wtPaPHdAOXrYfEdmjlK MV1VHbJwzNweEOh16aKRl8blLoS69vkJUSkskxGtLRepy1ewZxSdUpzrBGjbM/7M71iKDjwo/kod k4FXcJzVyL2ue2RTRFsAmADF5WX9Mp/OliScJHo/ZPZAEPieUnq2WGDxMzlYEz5vYbBFiM70FWoO 2pcSDx2anjkU3TkcuEJPnYvBQYgMHsBcVqW54BrRl5Ixyj5QGOG6omQIXe0DmTN7XYqEXXN8j9Q3 aGx1m5VrBOOMuWA357Oe1tA1zIPnZfaen2QtbhX3Bg13od2NuKYCiL5gJwQ9bqT/+MQ9B+JVO7tp lLIm+kLr60n8CdB3YJsHbYvVyQF7DZik7nfS48t1u91SSZUXNn64HEzFLvQ/zJvKZKEZhWR9xqCC zDthpFYIhCxjZ4SDBkfzdr/hqxK8lUKYMauPU/sYzwRHkfiro4t6NcpBMaBZin5qj49ip6W870Vu 5C8WPu5lfhxvHZLaB7SWd0AzFwVGVGmTmwgBAIY1aX3AAMEDgErYd469LDIxQH0oLlFBVeh/PqQE qSByvt33y2QQ7Rwzf+Gg+VwRujyElBMZMle4yXXGSjEM4FiWmqtsbHq78Qstg7oLSgdfKtCx6Q3E YvxPaDQRLSkjxgKclw5a3B/dS2tipuZK0NVrc897go8wPdrQGNL0CAgD9YxxGwRHusGwBDjMcU6W Epy5iBKQFpe0RD6W9SZ1SZyFmd00MzX+/Y23gMUrXeF7PenrdDxMDm3gphUj5h6mTyMx0T4RFK15 jV9K0xuFxPMsFiU3ZQ1Cj8cl99hBz7WjknqD/yie8B/x55RBRmpaExZ9pi5cWNqLRWcaz0tPUPrJ tTaCB5EcW45OeaDTuN3diTv/w8vE+j/G3/8xRjoTrLZJ/r9eZV+1YLvU5KsDyyrUcWU2cbjSkLTg PlQ5Qw/EsaNB5sDnlgmWYE8/J/DBi0LMm7CDzCuB7H18seSZLIGDccpZa3M+lNGOj5WjGa6OEERd m7N52AmD+Gs0y+VZ3lMtzlw+Q29+Gba1IRq4msySrK21HSzedZfOm8KiRnK6jwwUEnvZ68Zm+org Le/dYGPbVEiVgdeW78TRtHFg8rxrjVa1hbtIxovukXS9E2A/v68mkAD4XccyaKChYVqo1u0Qkael 2i6ogUOBeMYDQR8n8+uNpH3zCDQR5hcTkIQB4w99iqOFz9JFMTgf4DUI1asHvup11Dp+O82kVPCU 44eXxWvdAdNVkgZeAWlIL7kHN0fOZ24HIW5yjOKYivMGjfRyNXKT0tOQVd7EIOgBemlRGzouiPHv FxTLJi2alh2RmkU2acQgkdi6wnBZUW9LIdTFZe+K3RH8UoNUwUi6ctPx8G7+lcg59lcHhndIy0F5 3t2m5DXPYEQ8yp25kwkvrf4KFbygEnd3ZkldmxU2TxQtcsu6RnYdlxi1L+IvrUpkC9AZ/Auvh8B1 YqMJSDqkf7qGlaS6iuty515qagJ5uBCCWdYtlHU4QCaJpnLH3hZ3fXb3mQHYk5kaZCTVty6PQGUb l+qgS0LvCA68JUMFLc27CAWPpdZdFPBEQ5aNc2z5LNZ8BoPSDCmJBi1IRwyzTRUWNrORAorcTvtb W71NhwbZa6t0BdPNY4MB/3ENZqvbeFl/F2MYViUsz7r6v2fu4fCHcjxSCd3l5+d6ZZAASEiNsqDF q81bVnC3X1nnDjl0l3sm7fJZWMEfSY+TF8O66lV+tPW70G1KOqRXHurBBiAqd6MMikvbfWzRNLXb RFp4yhkmWuVdVUaTDcD3v+c0+RWsXrRC5/R+ehSKLThRrksaqAMrKnLp4tBeWPu76pcoF6eBXBg4 RlFEuSsQgSsBqcTQNCh1MspYlS/b/8+wcVMmOI6T+2a54m8zcMZ5MkgfVJwFnTehWkYhzjUHuXAQ yOluNpCDt/3ErAK8m2ICGCIaP1gpVaU/aKC3QQtkWbTS42yqvq3ZwZ96hpS+nRUdr68LbGYSASkP FBlxxtFJKjpwem2iXcbmU14iwe6Oh7UaNlwGyFKoy5u/dYyxHEhFxOEdfZTFpTvYTauo3jqHg1aQ vFo2yXEom3nsPb9ZxomqFm+WJ60fUEMlQn8SHi8Pu0OfWJZXP9LBKb7pk5tNXzQyXS/ZD3g4E1Mh hBkqDelAjMhNIT3WLEIH8RDAJkfysYtcPGMdzpjwpueTk4CrjTMnSmEafIyjICBzBdYJ8GwNp21a qEYQ0cpXfCN9vXlcr62RhWdI2bwuptlTcI1WjPUXn7Q5xobsSx2sG+XSBKl1JV63wkbQ/qn3Ro/I YVs4m/bG5xUWq0J3//N+Wa/ehJhqyx7XYY4yFukk5HAW6aeIni5NVKxru1N4pqx9UvMcZRRZ1E4/ nqJ5o6uXN92rfp1rp0kj6yKXhh/e3Os5qwu7SWQhzkya1XC+qo8bQcztJ+jQGuGyIasghmuzBKDS F1ZW2dCShjl1F9jKaKFiWJUWNMwnmt7jZN8qPK7NUowDcwEXQzSIQ7jBXJ+7Wk9WQJk2VkYt7CrD CU4is/K7T4nH8TgGwazvjnx/QmDm3+klk5DKPUzH1vf1/DFMzXZGlM0Pya7+NKezymCkwgryUnnr +gV0LAUq5CXYTsabrC7im5XkLTc+fbKvLFsaqFg4K63YgsFUTBl0UeWm9l6QmxTxkSbe9/EwW+3f 2iJes7DvmXYGRbl63q6c0owRndMCAIhIXXn4XRgai/hG1cDZ+uRyclA67JL32i2kfVTZ7XlpAdmK rmJydqUu3b3ittsGZpqAl/FwmcPghEZJbI/oPlXlmJNoZK5IT3YT2S6GvgnTnM9noWSu2PJMOOE4 KEPuhPO66MfKgGfE45QoTVhMKEXfWr8RORXsXvB7IYQiOat2AMd+CnNggQKrXPWWZcDhDZx1vM7l maoe1EclGvkGd9zx2KlqWVAAnjKRMbxZ9JJ3SdbyyJOuTS1cmlJQOWrRQzX/TBivIEJvP92vVtTj WULqqlj9FqmKGXfCgWKGOrdhT27z9WjlHeV7I/GyYdieOgL97zcdgh3/ZWLhtJ9GRuSsdTgkLtbL PxgIT7StOo8XSjP4AZq8u7HPM6eJY4sVTv086kaPWbWUMtOBoo2UM3xxP0iY5WQH1ijlipaYNym8 U30sDY6yqdynFAdkK/AnG6VogQkLHcbacpG3YABF/husfXERKTrpl8X3TuzOhr7r9pOOqkUYacXv gAQ4FV3AkIyMZSh90AUQpq/Vxw5V1E9ItBWM9n6gu/c5DP475HZQ5aSEEeT8RsKOpJp9OJGSKguh kOoi5EdKmPSeuVe5EmZHUUDWmSYKdLYYqjLoJZEbFSI8fNeXcPhu8V79EaZ7lZlqyj42WTzRByZn b3INKLqF87YPvxdSgi8wtlBxQ1BxC1XTRp8PQfVi4ejcyyzY9LZ7NGp5Q/B3oNSWolOpvhM2NzfP x0iw2ooVmk1P78UI1DYpEbq4jbI8r5iFiDPpHmhxTls8YpHfXFhsJWWWJ2yGy2u19XcvZjcfIqP0 DwlXmNFVlGTeKbO7u4QHQuQf2xyfE49zEMSaGFfz5sxaUBR+XjgTHo4jcno0p6kPndbUTEBnwQNT l25AnCKRFoRqXZuCfLSzsNOkVPu+MlwC927euqOWyiGhjyqHY+BhdRM971kMmCjw1WMR0N2I0CHC j17G0vs7zSFNFYKjS+JHXYwiMdgUw4vh2CAoFiKPAEn9tq3+IVEMvsFr6ALxeM0QSqvOOaSQ44rB 19hTIQ/jOum/Vf5nk1uA5ofiUHMiXU4lw8RlmPG8h2KkClJHzwnfeQxgo+G4PfV52hT7R7LXXPZs jUdIuaPTTV8PBh1Jnto0BXqCLlRVd3PaUzJz2YsbpRRI8fui2VLNwLk6Zwi9mtc8ZoLlYS+gSVvF oO88ncajfbCps0Aml2qfuKfYksk9SqfhTQyOLlrw3rqtuz1neOt5Jvz2k6ursASrSzaknE/EcSt1 REpdhkgHMVPA37d55NnwtcIR/MDkSG2Rjg/dAc3phPRAV0GYp6GpCiCiTISghwWyTMGRCIEQiDKv Q9vKUzPb/gd6qFGFox6SsnKr649Ru5Mjr1u3S5YpZlOhcev1hb2J4nluzqDQQ4LL79zdra7//uZZ nCDbjWYAqes9/YUn51rE73vHlX51MQPRGUw0NO/a0bzevEEsQj/P52eEdu91IgaM/OeG7uCXeWtI R96OH2Qa1vtjfFciSs/mI0Fn1HndKzPxxMa99Byrp00eplEZTTM+ryIWTICoQ+oFvA/SVfJQq/bW cXht9c8C/kwuYHCFdTFUUQtRgwYokMcyLx94fMj9cLNmeq5LNwPkIGzeIRcSl20YihTRL08Zbx1O a4LbRLnIKeqXLYXXMVR2EAHOsAKcPvaevrfW1WtZ+yF8rlL6QSXL8bvn1K2F3ejS4TRpsmcXrY/5 NaS2UTaXymcbQ6SjXeOed7RzxlfzLEY/Koyr/fcAiBENaUDWhMn/Xf6AUD39xpnhZvdcuqIIN5NP WW7jF0X71Y8I0e7Tr+krgYUtulYC1O0KbGMczE2MOSgeyuCOfJuXhfeAIqEnaSeUmEGh96WvwQEX 9Jr5Wn94YWfyUE6WTewlrZxAdR/5jz0kWiAofUqsBcbTWVzpQ+GrmZV8gVOJZkR0hjjdLZOYu7OD AD8o3d2aPiVMGXsXtRmMGYAOghOstXY/wrPTF9BKIykcjPjTvulcSPxUMOatx3aLBuc6y07zGYUx yY6WKXaVcJ4kASTK4nyiBDMSDPcw514ltauu6ldDKERd3/1YuxmoAaE3X0X+KsnlspmaYGF1GFSR FK8IPDKcrE1FAdSuV+yG4QUW9hS1BXwEdDg3bvpC9KmsGpkuHt4nfOtuSQTC4DChm/42wOQQ5Wfm wvYs/x+pxAqdepcbQ4z5BIe8rBGpgeIeRn+vrG+9OdEfBcWT/mRpeGW7ZcTUViYmxeEWu1vg/l2z /xtHa/I5WmYGpETGUdnBZQNwPyr/d5VYjNZ7glaU2d9bbHYYfdm4O8iXins+DMWmMOb4i23NZNcm FUC3pfUutG3DZVBXHmqYX3fnWAhCUDvlek++uqIhW3tunNMw0siMvr0tJ4ebkl5vvJWpoKV9qvIj 4A4jqo4/pc1mNFHUEFpzH3Ow3u2eNCQumgLTNQCfh4Zexe65aITlxftGNYB90WvHtTqqta0Iwr0D zCLj4Y7U6NfmSxfsRL2FZBOhQb2vV6ng5/hAcxlP28Y/dsiq44cW+D6ETwj+pa+PJO85pTYmkDt1 wgjmIlUtJRdohxs+LJgNWtez0TfgK6wy+LvZSO2/HogJEgpeif8dj0Qwc9MWnxB+lM15YgO8rwSl VBB2YJDa4PEAvWGDWgcVoLk77VYY3NONpT2ZbSf47AeGL1k8FzFW8c/Av5YwLWrnifXBvcND68ZL bYUXWFXD+/nWI5T2MDEJ8Y5WdfDHd+psNcaIFK9ot+40Y8wK3fqLrT6fs9aU/kuYmsff/fS7xzCR /UF2zs5nTSI2WYT572ZMrv/BHefERIjNvFff2WUL3ZBfWqpiszc0bc2enPvqxbVQhjrXz6aN7J/Q guVhErSS84lpAhiGW/ZdXNNQPqA4jXPi9M9EvvFgBojFodxQeP82qu84IvrWCgQ6KonrAAGm/EQv NXbfbUmK1xwyZgTnt0CBAcwpzy/aAmuNblJMcYdn7Kirm01ia0FqS/xYhPrOZ1p1w9DfAHvF9RAa mU1nHmaxIoNe03yIHyjNOBDZx+qopA3xkW9FoTTCuY+O9GDLa3qK+f5aFPkWKnOXTXrzKqxqZUX7 pyK+LyfQc7iLJks10ZuDBIb+KOu9Dhlv7gBqXtm8iIDPjXHsGpSuoFLE77oufW3va2RASXJMcJEK 3j1Ba28RnlhBbT+6iwpl1Ye9L3ejkpNLdJmUeG1iXAMImLKuBd2ZMZrslNLScgVUTbWfT59gWCZS jH0QOtsFFNftNbddCG9lz8dYBcczVoJpGRRwFACyNlhC89hxSbMgIRPlWbVdUNYXvFYtu47F8pMe XDq5BLqG74bx+mpB+tpg+kk5LStJY9txFtWrHbrXcbACCdtn4gZFB6xo55ZP0Z56qu+MLu8NueyO /yCQH6i+c91DZErCRJeTv5vrAoG+R7d7SurSQKCHLo95gmlFYXcd3EqfLOaf6tZzIcxQPeqjldww cMhfW6iBSN7OCRMuW99w0glTWrGsviTWz3tJzEbO8QWzpHC6fR+prHdf5o6ZI/pPejkX2hGGPLW2 wJTkFQXx4EfXCn0gDtk5jy92IXV5jSxWzRFRXbJSiGOCSv2wWzQarsA2L/3aXeru9nbO4oxtB228 wuMpQUlE8f/bUhyo8O0Bwo3UlzjNUuYc4fo7UWfHZgYr1KsqAfIQTMfmD2foLOt7Z9Z7ENhKeQwU tNkUXQ/U7lXljC/R6/fdM4IQbZ6E8GPTgxIaTZQliZn5m3AiZS/TtKKRF89oZh1YEkNZtYYOFp+2 6PRWqzROQzLlDqlMNtsxMFY3e8edI7DLcx9LVfrjglewRMEx0G7XH6q/eQWkc5nTxDwekd+jc/+c hyUY6uFUhBYajZt5gTleCATcDeVah0ytp4QtWE0OBIoHaJLHtLsZX2E5tgDC5fvWLtnKkvI1fvDM Y9bKE/koy06Dx2bAgv2zh966x4JRvtD8Yehq+jWV6OUlsPpqI2dKvlplE4+eBbCW/KG/37B0W9Wm OP6/pj/63hYeX8xrXjH0qvrdNEYQ8f2Lf7aiOUmV/8XRgnhfwkeW5ca9NOPBq94HQpJ6IAGgiWYr bVp1P03a0HKsI/jnI7OBXX3aGpmfZ9V78mSXalOViheBiRLwb+cM5PPyq/SISpc6I9dlsgZPokC6 EzUjUkOkfmgGrOiqZMc24rpcue01uCqGz3nw7bTGS7QIlVrHlrv7YuLFFQZOHQp/vUyhodDZVbc2 ihWVz07cH1Xa3Sv1nABXtz7WGBa003u766gUNHKKpiz9LNszxBoAKimaVOsnPn9BJRvoIkbx9HtY A75AsmyKD5y1Wvm56LNvYnX+MUdfbhHoK49NJfTwBi47oyiavYzKb4i9nSlujllDznPp3yhMxckZ IOGIthYqYwhb0XukS/q4WvQYI8DcF4Kkt8NE2RCh6YLnAyLJE6ttgZskJHPIU5aFqmd9KAVS2iQX 6tQ6Rdz2ODv/E8oSeWyg4d2MWJQ373+iB6ZcVZu6ri3khk4/ohbXELkYnfPHniodupjEIzl/3Xv9 xvQ8fhCbjW3K2xA+dAa9IuIsFLUj/XZOzFqmo+nGWLu/YcADE/1FEm52zKg5C1yJKyEaDi0YkKA+ RoiRT8ZcEaUU1tc36RTPRFPe44fN/qKnpzrniCqb8fF6zqL4jII8z4YraybBdt+tUgs/XrFKvWZ3 QnHDBhesqnc+pxDIzg6wxGXf/OqNqDp3nE2smcFpuRSsLqq7G7dpXNBLsZnEl/wm6rn+qSy3l7cS KFG2lXbCYhHISg2OEQsARkTcvJh/MvTrW7FvlMGwze7L8clY1bOx6dAsWirf/0viMXr5TFr8e1pE 56aMIOiW4ofxgM9TC5l/U3Wp2nnJTz5UvRHfjJrcZz9FH5t5g+wcz6SyM1+agZdVf264ESASTUe/ 3Y9EOZfVzCOmxygbrZYtNVuvfY5KawEu3F1hhdvtooku5r4E0RwctbdKXznhxyDUTuzy5x7Fb05c 1OwNadJ9qT8bXI1AZ8D0EBDsqbaTq4egDf6mvCd1xeVwK7QLtA4SARhA0pSCIq0CZQFy7cq8wSQ7 ZYDLhsG1Uz/JqsQaLwEIMXfbavRu8jIDtw7316cBtDUIyp21evMlzXK+NEzCYw8s/y+PX0GvhOaC gmla9vULq9riXHb1PoYCZUVW777BeoFAWiVfJfCSYqRRxEtaVpfJKDm90k0o8Eh7/XNcB6DxwlNA nc69AuRUHXAjB8WzZM3/qnSxSY2gLrfB8KenWInBOnjNRwNp+ui13T1bzmr8Iy28x7QaIBjMF2fg Ro1CGpY2r25IW1dqBKCwrS+QIryPNTy71epGB58KBSHc4dB+2TfoRSzLzoxkJllsH3GjHv2DxnUL tbcE4rYK3pm13KKiE8/VX+Vg6DYDa0IhIVqlu5nYk/ITznWuSs6/FW1LnYrR5sRiPkD/5v6Q1vWJ Ohb/ezHfc2w8/NU7+Mb3VkT2S9xNhgYXVi/rY+3zq9GftrUCB/pi9y3o8SuDcWrkNzMlXQq7qySo 7P6qrx/ZlV/+3F+blfuw5aKbnN1a/svU1RxltOlxQAOo45Fxl7CrmzRHogddKWVo+lsQOXiCRYqf ff5N39ooI8G61+kneq6UeFwB/i8UWq1dwfQi0ugjta5rceQSFtH9NCTQVVQacS88m7wLHrBmoSMW 1mMQ1OtPeanDdfNDfDg43wx4gPcmCNZiOIkgAv9CJnsmCSMoWrQflkLuh92OV7p8fSFo0j7iJZTW Pv6O1wx/mvFv6hiQM4pXDP2PW2Pz8ZnQsnPUJx106rL7SD9BCjnW3A2jNXU+JNlEVFGw1H+u8xqw kkHUguAR1cV7DI88FFELOLFKtYWDlg85hnx4zWClLKbMMlGd/csMipiZfYypL6WjH3Rb7aA9QaIN jnVWQ3I6vHqlxb4Sd19lMj8q5/qg0kmy/GU3f5bX9blW8RKCyDEgq7DQWA9l4nAyq3BVVommL+Vn Fi/sOWnpKUJ0VhDhx0TjVUr0NNMHUfYH9i73OIbCyoJk/+OX+42ckFmI8t1ThofmpMK2oJFQuwDU K+E11BPSsXJ3RyDVrpjj2ANqhaH+kUG3yWMiXERsnvr+F9Yh3w4rEhC3ATQfUjfdiAN/yurfdJpx 2dGpMegTN3vKgRzq5EivE1IYLPucjxNGuqIQR0eYvfan6VLB3ly9pZifV9EG84VQX2d0NA1w34u2 usoVd6I94TB8Diu2vl4rhavkb9KBkPWo7KXPyVzF0/iYyq1C+H/Qbn3O9mz+RlABekyGNp2A5CNc 5zQb8O32QMcdfGiPGFnAAK7Z+S5zQ212CbT3yjXI0D4fVB+Cb0dGf2o5cC6PBkCsvojiV9oFxp8Y VLG7U7hs/euygR0nEQzlGKF83iykGrMXhjLR6amWqJ57/6u08qWVxs2g+9ald0E10s09Fjlr8m9c AVP1cq5BlZM8fB272utKsRmjmG2bypDG0bSHynK2PF7ZuuQOj9JhuZeLqTGEu2pxkNVeSOHFHmBc 8OgPzRsmKSFB6GiXTWbmJF8EWB21w4q26DZS/3VgYrpT2J/VMnyHwf/KGiSCrcdnVLZ/WDKi0BMh FFQw7PQKXgOUQGjLlYaEIlavMHKXEPsQoyhfSbnhJuZw+iXX9a4b9SQenKgKKHKwxsmxDqjo7Tnd hCBiSKqLViai8cOK/QVtkUwWBrnDclN0j+3bmt8lRWrBQlQQ/IY56Vanlex0MlAmUYltbcevyuvg b/QwG7qqSzlr2bODPjEytI+Cewf93ixQoX1WJDOrRmFyrScssgGSQcZN2lAiPZv6gUvGOv6GDZQ+ LHiWQVPxsQw/vqX+d7zypVGfPOvmWKp3J08tgch4ZhPC4WZUrKU3lpBGNrJeDCHL31GTkf4OLBVZ czuchGkP45jCO/LxnGz56Tq1PPX/jJWdW5Og9SdyWPcn4IJQ6rjVVNwi/chqcGbY4RDwySEnBvk2 zJ2C5Lc9qXdhfaXSdhqQ8Bhfo9eQjHh5LziyEkeMDA9Mb4YF1ZRX8NNOrguhSjQIbBwr/QLkXqvb sY9oXJ8sRmIbtd2eb/XmlkeuN0QIqW5jupqBgCSmqh8WBDdgeXwguAnOpyL819EuZRnAGN5J2JpY C3UdniGrtI0aGI/UJPUpCMt/tKjLrXJYjQbBnNC4P7xQ+Om3xGIfPOBLZO6NxTjcVczYLUm7QEUZ XeVCedsjKTs/0HYUP6V8Ac+Y0SIrhNdkHcH1dNdS7f88WLK7ir9X/ILgsS2J5kqvFi1SfevboIVU FzRV+oN+L+2qXwsHF7P4sNCFoLc2kK0hsNHE98++gBEoBVJHHWk5HP0IgoxJuWeMy9zkxnb8uKsD FEoelWObSkYh3eOfdrqBawkkxzhIhGL568E0qQ89ryYt19aMSZw90O0Llsvh0n9YKlRd+65HaoBK b5SDLfziEhztfrGA1hU1IDP0At4fE76db096cuouXiKmJ3yQuY54Ph0GrUDs5fhuBQe445JFkp+Z dHex4IZGq5tCUmJnOczK1duQVCKGJ3twIqizQPeGJR6nPzMIn1n/wqtWLzxn4kjywJ5q7t2e6G9+ S6kyU5zIQTN3Ro4JfYfS33bW3+78GIZ4f0GGIwx0F6qVH/MfWHLsvJWACDat90v6M6yEDxx9n+MN 0gOsHtkZbb+Pou9M0DYpY4MoClxrMjdLOqlq/OiHSeuVqucMKlZqVT/F0cMNtL3roUBqQahyB0Yl XJQL2jdxN1FI1Nc1GbfJNr9hF8dWtPbeUzhQ6zQQIVFO+WbOj+X9pzsIXnX2qJoNXdgjvXz46sIo L3NhwM/2TqjDtFk+/benj49c4itKrHhCLnvXVRr7BSftXh1meBaene176rwTcJsYPOhAKyKS9XqW EByEVMLfwW8w0ApOnkrt0PykkyS/2935vO3w5YJyvvzU//64LOUnieGezLuvRGzJ3L4JhvpgvXJu mr06ZYGLO7zQvrsmI3geHPcHxpd5fMvW1QV+WNREXdXwVfwomkNlbJ58PGzkfcCfI+VAmzzx6RT8 ECYs33TENGfXdp/gXg8kcOBXHPrbz35sQG2aciba1k8uq6E0bK6/Ypy04/Lut3FDNP21ttgDbNu2 eksJ8rECmR7FEYLHWA9PIZFkmX1EORsY4PLBIU3qMz+u0QuGiyhdMbbp3xoad1w9aXEWI+V4OYHH d5IQtXlloVVCMDtOlFyDVniNL0EXnmtrNWRh0cIfqUF8iybkSIhuedAtIImH3Lbw7EXmUdKMQmaO /bvdCAZ3238qXUhIC4x3hXMrdEmkuk2qpXLrjFPCCMYk64p1dvkwi6p5JMYfEDEgsZI+ISeyW80f Agz8LRBEWVLp1WYGS84K9RRX6bOJ4LX7ntO0UKqgD+lolUsD5pWstGgKIJMDCkBbKzmVXvT92hwy ZRlNxMwDyLvI9CpOdlfvi+7Aa6hA0/I4TH6S36ld9590KO/N9LhZYwFO/OldvYerNPUdWiovfgYE 4E/i44dEnn5L3P6ZHliXOjPk9keNyjis/hZqYntCuAZvwHGPGSpMj30nFOH/6xyiAMVfJfzZC8LU LwsX/8qFExhqQ1bIBEXHhAw62B7piiQ7oLDPqkcXaNb6FDO1ePzzE5d1/2Gxaz52NRHXXBrGHeLG g5/SHdeQ48cqoHeo6kp6mavTJ7lekqG75eLekrel7RbCKOvfyHeRed9jOwEshdd2bP6O8fBBrYql xqpbUgBa282zAArfwyHbIXHJ5BOF6yQcM7kR2ywqa1N0YPWvrEdlhcavyKsoQOvra7azmQxneGwY EWA1gSgKOemPB78YpSaLBg5bNS/uiBgtrFShb2DHcIUyVrziwCT7y9gM/viq16Mu3DwiffevU8aA kVM6m5Kro12musPAjcADOxuyS7w15vNLQW50rMSn9fGVKaDHTkpuizQY3HH3fA98JF57O+4hOiho oouju59WDvW0kQCjvF3my9Xz5/5bYBGrZxKEAPPH8D0JoyD3AeXHFpmlUT0Jhrm4MbawvX3ycCcA hMD6Lo7l0bC5xvDg1hdPlMYjsA/e9nyyDtXMpzkgSisUmo4J35zsHuVMDWPMC7awPb7qG5b7T8ME J8QI/cnvKwMw3tKPBp03MI43tx3+hoarnMtfxT4I1cQ7RGx6MZilHgLLVdXRrWLVeMXRBDvwkARY FvFLhE0CtRg5GCReNKqIz5O1ey0tZysItludqbK+5JPW38crlc3YOdCiC8oHoOiZX1LojXZkKsMX H/BYhCXAJaU0yKCXKCvdS02/Tlz+g4vjCYqZuPD2Z0u/fRzPqDuao/r2gClflHI/57r40qzvRq97 EQYT64OeKGpOb3kCmubUW/05LATVjRDDlJwQwsTy2mhbZDIA9pxzGnGQkjAxnlxX9sXfPTgRN3op 2JgZDWx1ljf6ygZ0qbfSGPhrTc5Y6aQrWR4Ve/nF5fbWul+ONVfW1Wyy9UUYFvm38oBb1kI0VU2e bqGSnCTul/40BbRU/0d2fMpnfrDYJV+OQzSFNDAy8om/OvYa4d+f8rE1a188N5LeiB7uI4O06SaT QFIyLUI0j9jdpUhkQoLwJugGrOa3YpaOtRHvTnVwDjNbcmxfhgM/a52KpD3jC9k/SCcRlZ84ZQhc 3lai3YG7nf09a7j3BTTp+I1r+n+LLjw7VefMrjphlfx1jNSE2ZHspp1Uq50L3fbvoCxoI4svjpZy bcmn3D8sDZ78+cHsCph+ODoAbPP0wyjCzHu0fhUdpGnG1srFKnEORXsIe3LfoPeF0ptR8bGotR8p QkpU1ZryctbMMgiSPSVbQgAVISbePDKfg9csJAGJDTbILOQdmUh0A4B4e7pUAp6VvIyqxsPqlV+R JaT5FxYzJ79kxvZ70X1P7IodSXcKH2MdHVWVs6qU3fTgYAOgv7f3Gnlb6LdC/m1m1gCdZUw9wNtd yxRy4knPLPZfsBeJ0Pu65ovGVzgn26JlzgJPsX60q9Fjp1w6jZ/3wm4OyrP8vWdrH0BK060mnH8E Zt7B1vCLhtiVkge9g7PsWqlBKmO8Sp5TjMTiLUvWHukOuNoFhfneLUFPpDhevCglJLPvUCdZqXDP kk7IRNIBuNt0fKMDMZTDNf99e8qvxI23AeaU4+iWtt76OOfXirFUZtAG7jfuNMSP0ahn6IT2rRPa lsU8uP7LZMpJavjDlk+gHVrosOxwDA0POP3IDhX4WJNKVHeglvhjTlH3AE4CvgbYXQPIwoeXtXl8 +hv6p/u3noGnLmBFnmk+yrsj4Nzhum9S6UM+2QIHiMKqRiwRlcFv0yyx2nfAY3xyPimlqY/OMALq J816Twsd1sZq3aM2nmeo+NgLLcuI4SXGH+4OxQnhCbkChnjPZGkuSu9z0zELkn6S2AzLgVst9te0 GfA23V9kCkj/nyj/fZJeEV0qYSBeOEUusKlJ8FdiGs/lBbXirroVwWRQZ45nuu5wjo+vX1xNYTIi QweUmlvX19SJCUfz0y1Z62FlEMXpx2N+Ma8B+suSYLb2Xj+C7Q7IheQ/htKcNHpsAihA66iCwT1B sZe4pHn5L0z8Ooeq/PBGijxiuQfeIiX7y9FrN8RLU0qLdl8DE4U2yPFc4+8WZ78kUkrJNEFunTg1 g+XUJYe1mtcaO6QAI2oG/sHDBr+qp5ViSAOuIEfcbLWA9D1GiS+gXfWtg7ZV2dLJtfyHKW8EjDsE FJn0eiVPghC49YdSqQk5Wifr4RAQ3aiBWkqfqQgtuQ31qSUeULGcgksmDD07CXv/kOtS4nkPSmgg jiaeu7qUGWAogE+a/xnupViejxuXJfUetcuq3iJgmUC2RHoRrBn2Lu3wN22/BbSMhHQwP0cMF0hP 3ue2CwiUtGkbRiKrgCONZ7e7n4b02CLuR+6hfTzHatHihmdn3R+RUOUlWsbZq328FhmbT5A156o2 qvlAJEXz0IrhimpE3gypQPBIwV4Ly6KYlB6Rdywein2ulfqHyKQoqhfV5V3AmgLeWqiYyGTGoWqg ro+fuFMFKVjkrY6aj8U74110OeT6alrXH0/5+qZ0ZktH5+MfkEBHtJmCSZnvT96VfkZVlYD/7faj dLaDHxDWMHEb0KCbDKB/fSDVhWgxqOI3plZJv65xr7zATYHVtFUvSbBRPCahqThqFmeALvKT930+ 33W6u4gkZGwRES/rWyuwF8qrbPCCthviCwCchlbH0uopLoKkzzcvwJeWaq0vDZQOeftlc+iF3mkz LDwYdiOmTDXvEqGORY3+yzIJCeRKD1Xhvrf/Luu8djAL1km1r3gt7YzrH5iOEc3KXZVCIJyAlLr0 VgNqqjgd6Y1xMLPtil+Mk5Quv2nJ/MOUyXAoF/9+NfmSxBcBMJY/xIsQVF4zlNpqSmwDHCdNmPnF zN8ZcsQi84N30iI75stBcrGsNlgHVO22Gu2vXWtHEUyHykpryx2c1l8w9rDlL/Pfk4EmsWkQ187s 91KUemL1rFQsAz5N9rewW6bcAM1hcpNs0GePqLztRD9QKnubVkk4fQKNyDO+KPeQ+qnA3zCXY53S VHkh4bCQo3ySoAsLRfjqGwciSg7lOUuCm+upEjAcbDkD5A9nS7tbBzV+evTCMCRN7Jql++7U/Wzk 5lfL2fM1fuLAUJww2q4ueirc/CZYUEj/L0SZeCYnxBdfIYz5TWTGHueMoF2HPCb3VJncrCSTJ1pm VxGkY39NGaWp3NppiCA5/GuXxvxOzp0IygBFssLhsWR9F/KvVtdlZICJ7pVrUE+KKKvjmuORYfkO wtBkaggP8NjQy2Bh42YgvXIxmzGf2nQGDW9mTGweJzS768XYBQa3uqiWBTg2PD0KLEUZl0HbRkMc V8gJfE3F+2cOXUYdahr6Lppj/+jomVTyYLqpil16RjmOWr6OSBQHFDwurmmsCQCyTIyd+z4hoX3/ VXJZkc59BvrT8d4r3PqHndqsuF1hBxeU1Bx8Z/R5yN/dXwy4EwTsa5HMTFZ/MMFappSRpg7QZ1Xq 9hURAGpNiTPh3LRJD3wFgQfpbepvyRnJUTvZMeyoB0aAMqeLQLubqqtZNOR86U6qXPwzDKvrYnX/ YoMmH61K0RdUnl+zS0clM3rU8CW5G94FcYWTjfaT9IVbS/a9wcGPeupcx6n/t5KQ9ao+6Rt2fjPk Gugg8vrYW+JXKn8vhXryliATLUX9LMtRLKACIMW+q3kMAO5kNmJ2cqnf12Q04svOtmk73Ic7rvVV vYthdy+yMCZevP6+xQZ9YOQpq9FMvz5ZdP2YapeZymQXjP+MTh0DtCV73NopkCh3uM7l+LhRn7Z8 dpIn7hQZRDwyvDyvrd7s4nV3M4lIrPrOMApLzcZLp1n5PDYS+eKd+fVA9a+PO419XhDl8lUWfXgR 1SBTBeA3fstwKsIwbp/FJ61fy24MQ7Om6apm17Gwgy1Kkl0YDYZQB+iNSB5b6iUkUngyRo8aiVgq EQxgCHOI9zgKfoxMh958bHwSadiU9WkR8jtXIXiLidYoSctzejZu0H3cIq/3JpPFjPUuuUJmS3sG opt2ZNlNZZ1Plojdkndik+5NeGqYFmhaFOWDi9eiO3zGbnuDL38TGWl1x/fFDwt1qpkuufvURQWe qQNd4zDyvnfV1+mxENGwJhpJtPvRzGcAzqN/VL4KC5sn4rUuNKcOL+oORnjuP503jIywD/xhKtpn /oNcvqZVdPhQhgRow4YvqHGiRWqQhOFe+ogQrKifehlcyuJy6ee45H6bAdDYAx7ZFBB4C+axDt9n dbAisrdINRvlJGw/V9SJYYCwJDToAsq/hpMKpmu/cX/wR6JtDFjjc4pXfvi8bPOHtJ81BK9Kooo5 ZByqkxcICLSpvHxoGdV07voruXTI1dRbUBDI6mfEclDGJMwteEOg2Y7Qm6P3zC7yZXsaqxu0FZ+n 10sv9s8XNN0l7roJ0fnD0PROZ3S4QjEHvx9dd0vl5tZhOm7YxEPYKr9AIzALEzZTWx62m2kXGDqK evIm76kBosM6xe+fVU5H83tvT/XKzQfCpfmE1Q9u74te5pdIwnGjV7s/kvoHshygav5Kp8bZeHSZ 5bpJ66Q9zRHgMRisuFEgMInV5Q55kqznih8I0fiVlv5LANfqKPY6z3qIPQ7N/Q7XrWCX+NwteqLN Ni5N/73un9zyqe0iPoiFP1bIiBcct3RpmrzCOqqLb4YD3O86SIInj3KkDda3u4W6lt3UtaUQmoGZ PypyctoL+X8lhP/qltEzG+Imb6KefQmNKHJ6GS0i06hTu0ySm4n8mqin+kxGcc2Bw075/FFqLHNG SX8Pw1Y4zQUuzqEf39cG2dB0R1Rc/45E5RAXe5SkKaA5N9LiAubrOXAQ7zkVOmwOWt2tvm56oigP N8Nzmp/w7z7fGVMo85AZf2Ey0BnZDKEuctB7vAYCiLNm85J7sf6mCmCzSTLfCzTKXKsFWl9XovJd RE6OXdttKj/Dq3+cDXN/49pWnwKv1Tq+SuSQnAyFkB0bQjcnuqbLHne2s0JjR6fXBc6jyGogY+0r /BHKMF1/IBaWJVDLM9XsSIOPT0sd5sP/+S4o9yHrBNbgo4ZDafjRo5lNPHXs7OPVxrP3VuKoG0H2 ylKUYMhY1MHIJ/RTbxouDNDQo/wbAPLkpb5Iad9A3gDCjpSH2e2q3CCr4c5AHsaKTvP3VzVS53YY IPtLZBFEvWwKFRLTV3D5BTTfbV9LpV7wNXnh38vBiK3Wjcx6QJ4I3IZkumyhSuUprJYar04GIzsX RsYuG6mEZhrrwcz0LdpuobhKF7kklkGcuBvjfpmpHPM6cQ7NpOFvctQ4SpcfLwfyzRWtMtucBdeA dI1P6KxXVqGZYy0CTaOY1ST2LAfLEgyWOg459zQCqo42fFwiPrXCAEoPuA9iGr5jt9JKXjzJ52Gs IR0+dCGlB03qzpZxsBLat70LfVHin8tLQG65VBleA03hujm0pzhVW4scfC3ZObEYUTPd+E62N/Sa CxCS0XljSuYrhKjzJVCRNejRpscXKawueyzz1pzmis86tun8sWHBbNSZz0D2czZJMLFDNBC3EFsF PIJDv8WUXo/AEGwN+SIk4w6xv13AxxAKN0IVp+uM8E5YIX2swihxI4Aymdd606K5g7R7vo34Z2L8 VQFIUZotmMiNMV4ZFWAtdDcWMJc/rtnTOddKickxDVcBRmU2Pyz9OlNZeizEATW58tLxir7kaGkY OfQZOn/x9VsG5TPv1RRBVulaw8vXBv3BYEFMGrmrNnCfDS7csMj2UX10TkM4b4DVzWzXKWEgqVHX YpxQpwoW+a6ZM0Hyw/w6nJ56V7L+EngEvjWkRNTqHu4FKrASuavzqRe0CLJ7csvRI3olUOKkuIVN sqnQLVLmg8qC5zs0mBHjvoQe23qrdNe7V3YWw9a15wyUIvol9UKCAM9CBwS/eooVc0ufRqaq67SH kmtwa8TZHtnyjcRQfdoM/6hvdcSSF9L52b8EjdDYn8S/j+iEhxb8YD1U8jyi1Hjk+5sWn7crE4V8 Ws6rMdO13DHuNliDObp27JGiC9phBLqZTXHhBHWkVtRSevMUXX3PaN7J2ZMIzRNiR0OqdNtKOsPd Em3rfkGkl43I3EKECovEqquyvQ437rdaKsF9BQg9kcyrZdwyw6FMdURzsYgnc3mQCJFrl/E9jpDt BTdPnY+MijidDjJUz8gYLYEJZ3QaJigSDNyJTs8+MdkLAs0pVGsoT+Us0jCsTty5rCyvlI20Vd+F jl7Gq3BedyFbMI2YpQRLW049tgod87xNdcaNohfHU24xduKcOxS/VbmDlidTc+sRrV9Z9ewgvJQI Oka4G/oJD1z93MRJtM6KG4hxW0KwH2nlZZCBNyVcLaN5OegRLMOqBBEj/7CD3tHkZg2HYPe62PCX KZh6uloUCo1Z3YIIdEie6N59WATQqsmBJZGwiri7H067ytc3vGSnionsbcnqY5l9r6lnPIbHqAIt tKLjj0/dIt6YwDUOZkcYLb2AKDXGQlm1WrncxA6jD4nnqUzb8hQxVHgL8Oe5bCSfTxpQWSOyItNU /reiquRhlIy7sil9AVLYsZttDBvEX4UfjkbTvIOLLnVXcpVKkovomeR7gMG4+ByAZ7YHI1SOvzT/ Lh1ACt4ecjX3ALSsU8GVLY0ZaZBOozUUSj09cW/MX6xICfTkYxWI+jJi9z/kLl2Y4fmzvTdhJBFx l70D3BnYTbzYLQkGWn1V1quag11VioCgc0CKL/5HbeMYlMWVRA9OhAEiTxW2ooj5SgSIAun4MfeM S3QKJzGGN5pAuPUm35aPqjXQPJ+56i25DXTMOjG4b0NaBuOd3F2mlzr/C+zr4IluvjR/x353zN2U QEX6vDIL5O3Ixl36YVI6vvqLSZqxVU9Pt+F8IQkwZ6fcTd8Ad6nnsRRYJ2BGYajpev1rXZ2i0/Mk glxjRlRARTFcyZ7VTVl6xT4TjDxVY401qZ5MpPeP92H4bksnZYUwInzvJMtmIl2/NNykh+Wyqar5 GIkwzU1K6NgQIexVsN08fcf3H5JQONngfFlMQqIbKiNYaSbKlrMjQ1+CSujNHE5llpcI7EDhjJmd 3Y9/lK48qqFBymOya+28SBvRkPYGOTb75qAnXdp4iVQILIM55Dn8lXiOg7IlYXI9pZQjddaMWB4t j5JA87Z/vxt4d0wvHa4gLT31kjyYgyJLuOEc/DQWi56y0+WI96Lgv5yUQ54+yhgPTlPQEDBE0tex ghldW380GcgNG9rJlh9QUG/ZXPKAgDwy4B9/90LDOFZJBXcEjm357MbxsYrig7DMUM3K6iROpZfj kKtGQJY0uq9oGqT0ALlaAjTJwsS+NCAQRUInoF3p/POorDX0PhyguuCkVm2u1QQgYnNwjWOT7dEE 7L+1jKvjbacx8Jsn+odSOL4dB0vikzc/sHbdf4+8wYYktZxXcZ4RdEM9Rr4ugDZHYfI6n1JBbYMH vUu6OuXjazlXMQQriRncKgLZh9RJwEKuNH6XoGEWxYzLOGK3QASPW4kpEy4Bw2snMjKWWVXqgiNA 8k0nwTCvSDwwv3a81NWZVMRzhS/UMSAgEjgcOpbSZusBRBv/avBqqwJFz/eUO4S4w+v3mFpE2h5U 0FwwNZ7GMCHPwaA4Siddobmb2rk2sO3OYPZcRzKk9KtU5vndQ3fGiaiVGkW/iTjVCcZF//eq9Bsb p5Q494G3B3Rc0RwcKqugD/Lu/4M8HQXWigFy6cTmnTdj9WNsAWBYFdr+aR3ramiUq2TkFAfukVde tScyHZTKEastaz3DioJzUZpumtpAPS6HJAouo724bgxJmhmllhRxU2XPHi6yHUASKxYSqDBs5bCL XCP1Rq8vRhijbTNL7BO2A1LFLLNjhNWBDhGF40E0AhSRUIvc/7CXC76tlBdk1Le1k9Gx5sL45VvD NmgVBo0uJBTick0J7h8GRO2pCdPJMhwrQKJmtMAJSsNG/UeroYdJAmcdMOyfhLrAi2ryGFedCtrz ym4yPi8OZBCKTC5Y4zTL+Fn/32fQREsICtFnE/cGSasdkawWJeUau8B8r2wxbL95uXJ5U5GIxPbD DiY0oAcrdg4leRtEKfE+DIbdMtVZvSoxrRE6UGZQBlu/ZOdjHQNuIkittrXMVLusUujNoGo+kIbK NonSj7nmuK9zBIKUxMbWXz1Wf4ni8UI4szKcs7/Ws5xBc4DBXntfajpR+gHD4oZDd8+8PXJu85Td /6/kDC6baQ93+MKLkFyXfyHTJcLAGmpUZCm5FRt8X+/mu4DjGZN+Fp1R+NSmPqImH+AXuXOSJUYg mBpVnm93KN550akXPPGB4D5BY5pIsHJ3RAhL6kMHe+SQAqInYIW2T5j7wY/jlWfAvcyOe71ZqHg3 4dAQqmUaWYKqcJaov5aTvu2YK35PB9Jv7oD6h8FcepJ2CrD0MaG00UJaLk31YRVvQKrc8lvo3q37 6HY6sT7ohvxT4j/Itp2Mc0vqiRHKXK38QS01vmPcrJNXhgA5jE6w7f4nf+jGkH65wghhIbbuiTC+ a2VKSvKCValaSIKaVkP2crFOZwgNYobpK38I3OX4gmARvipmT01rCW74M4Zy6EKqWigU+oufIpg/ Ib4XEjtWAHPEWkxT6Z5HqFJ1Lc2A6QnPIdxA5uBSSGbBFMHwvZjV3pHlupWnx7sgBFo+ApqO7EGp enP+2GELc3C/bD0vKRsri6D4qPBfFuVwxi/ikImr/YBNcjuPsKCb3nomswDe4GaDFt4CPhUpVBSf 8RgyG9BcBBsJc5QVEWFTsItvIBNi16RWjOaDV6vBfekVMDORqJK1/dgyILMpRIwEoqZSE2+4LIQ7 1CHtBvgRS6YQqTU78nOdyVDYa/4Ry/865Ph91v46Bppy8ywlTTAJjHw/yzO0aGH7Tjnj2DE+D8+D uatVF5FxlzMouspt7AArz/SZclV/kHoWHPFsje+vAE45i+F+m8EgRNz11XoH+lWDxvsha2wZMVuP f3sc9TmdUg9w+AF3VDv7H8eDWqDdKEMmojpVBkMkI+PIwGj1gRRmSWL7MGBLZh+GY1iNqzflru9i VUHlDRrFB/XyHg0hwAjMWkx6SMmdP5vvfke+BcMubZcdP6LHpC/fYs6Wrcj80PYdrQaNo8vWF56X VHnQNfFXgpUOKzvl4XKq4mxLVLCR/TbOvxDW07SxumX7p+WhfGxn4HMvY2V3ZGU4kmSYNqZkmHjY DkB/dpvVdTIuAJyejQtnXVaGPW6dicZKv5wW/ghGl26Xsb0301O/s23+kJ7ewLIzanlaVIATZJQp f3L+bARxDbHaoVSrnmeN1ZsM2CO5JGqZqf2kqTPgzym0W2WEfeLEcADqDuBmFC4uc1waeUb+MBsm QdBFtE5QggYYtUzhZgzj7u5lbHB+QIB30zzicQyPlXswHrT8s99zIPej9njoNK7GgYIwXzWVfhTj CQos26utfc26ivjYdtO1PZ+13ClASArUKo/IS+UP3WhHxWjbpVSdcWzYZ8oZ4P6NALf5XL9DUHkT BrG3tP4NOwhBeCuPCZV1GMK0P6asDUZxnOFAsPrYuM4NDaXmv0Qzva4ZdJygAJWfAlew75k7I7lA 1zrG3gcS5DZjG4e2pTcs+n3qvioqBpBPutvBrg1qVtB5vuR6C3caztLmUJf2rbsjnf8LToxUYJHk h6aEogG1i+zuOeKz3G9IFK9Xj1aKM8fMoVb2EglSfnstOacX6vmARqcZVv8C2ztb/EBY2mTuGfZc 74KBkLOIwJcHt8IFcrF+VjLtB667NK1oVdu0a7ccQEY/uT8WAhDGHacQ1TGQ1mai8SJ+kJkZaqKa kTCvzjwepqmAs6FmCDDSzsKG52+p0agz4sxoKh+Xx72ra33sNhDzPDPBcflBwvf+ObuIwLupsC2l 8Q5W6xB11NkzkA+VNh48yJjESqKODVRJgLi3C1lp+DFB9v6nMbofs8/8FEoMoFFC6aGluAort8c2 jZgIalC35RxqblJz+PRUW4jYErKM/VTnR/McVtihNOCMASSykekd57p5PvEBV22pQwS6mP6dRaIW OhKy3JP0UmlwaTSg/jfoVdlkoi59bCAJApwWAza1y4jBo4dbWQyiAFRXRyeZN4+dWf9zrtocWspy EjGWllBJcQhqTNTVUI/XebPj/bwO19HczKAUWFlc1adXUiLTBhsZKxnBN6506GeOc5vNX4mzBard 7WP/0rwP6JGdRkFnCiJx/40JcoBqGuwch2XeCssTW/xCkUIuvkYwoD6aODTSmmIOQrVICHXvsrpu cfwcJoKhOtoulaDNc8Nlkxg1gwuanbhPE0BgydcGyjqaP3dgX9ZrKBtO53MfZAKoBj1aqp5yZ48+ UZh5IQo3ri+izgil0qjXcMPHdVuFRVAe+0cf7SKkAMXFBVcrt0qKLgMNf2G/Avf2duHB7eM4TlH5 TZllGjL8KBodTEZ0CHVSs04jIrHbrQ6cuBhYakU+RaO5/ev/WI0megtiVPt44ydJTyssyTSwnLaC TgZUxsfBewPP/lAkTIgMYBHjsvJKzdQ10eST06Zbodz3T87d+tuwnaGzKKJnXSjAWKgJgw5JI4PW M4nph9Bt/PrpSO/3OJEP95XZmQe9Y2C9vlSnwl6qXNlmnGGNpvpVbFMxcCcChQS14B5PVPV5IlQE G2SxHTG1N1JYHoFZcKcPJMWTo5W8A3MgCZc6QCSOOzBvzl426821Fezrn/fNhzCB23wFYidRP9Cq w8jf5QgfWSlUm4bvfhrij22XSeF5u2d0gZTtR5EtriMUCSUhbqzwrgVw1Pegh+bqwXkNVPeh+3u2 5qDpAzUI4LSaiL9Pht/ZWG9aJyCmGhhFK21+VaZyu1HfASwv7uyvfj0uIXMhw1D0eWn9KXxEfx+X pLCkVqt+yf7EAL61xDEeNfyQGcghpIAlnkOyymG3Q8KcqhHUPzkJNhXUIdMKFE4o9o/eCJURvdnq /zo4Ilz8e1OnlM1I+/2ksvP2VaOl3sGr2qpnIwsVWRESW2r11FPojRDe9HRqUqypOXhlzPMTJeLc 6iTe7qh5xXx9eYUegDH5UtkerPeCdlhQRM2v8Px2YzDpw7ga1khcwBSLll4JxVvdirK86x5CHnNu YlTRoJaeXlnrVCVgT6UinokrG2/1gXmr6gQS2y6uzfysPIqxZITLL6dtag7LhBJMqWjdgvr8tX7I DSvdQsWUSv/XHmowjhfsOEh8roHTFKz4YO2xuTVatmFsmHUQQ9pA/HsFUgnzOUgvirYetruLDI6D Fz1ChbVvfEIJepemW7JSpY9RvzgRQklKIGpz/vBf0twhfYvvjZENRa8oSsz03g+GONWI1biYpcuR pFajPGF+MXblM1U988NEzVP0Tgf75gw7EXI7QAHWWejPS3KnIJxVVC+J/nwXRn/R3Nx9TIUrH1Cv nfn4kege7QyDC8PW+7SoUW7+vnaO8zrPpS7Ge3pB6laCWCoYkr5NjtMyFyF7up9ZED0H2+bJXCfD UaGDpN5cXF5lIT8sHq3S4mQ4d+4YZVyetL012sH6DQondNceH3tG/VI+p8XQq0ZIAf64cGOm+ZEQ cimah1GIxeuGaQp4STfJFy/BTJWNe8swA+cJMx/02Gy6x/FLuxCILciPtf47AhXrQ1F/DHC4FanU 1kT6hRCqQwAgFD1TqWzmEfWyv9KSJPynbOqtpDzzt67Gz3DUw5uFqHZqbLvp7eI43PTl7FkW6qgb k4Q7Gc8fUD8yBlWlwPW380MEKQRA6LTXkkDSlsnlsSU8116geo02Pyi3YEVEHAK3EHI+UY6xE9/M 1C9kO+kr7+hd4XenCcLdWsMS5WpeiVg7oIt0LXSuAMIJePuar6VElxWRqySCswJFDQKN2vP4XSAC NAaJcfPcSFfIxgAn+dKe8iebrSOMF9MgbjEWUdFV7usB46w1L94o4Y6EToJB3txOa0xsvOg2zREz XRdb1FgPhTb8WSIoOvpP7G8nzBsBQvqSrA/97KgQdlZv1I+lZqPLaZrVMnHvwZixw5lki2Tr51Nt REhpu7CxhmcR1fDDEVjdT5ZWvsdDH4UyawR9IVyOskTzC3BaHq/LX5WWDpXFBviQ/gCjMxc4XmpR cgOV5KSGnx1LSoczQSwEqVGdZz1Ce448uxsDIPZYzp2KSVqXur9esB8WtuS481xOelGclzuD12ry SFgsIMyN6/6vrm8nGuDIIWEhw3kajOPxwFWrJRB/Okbxk/lq9ZZaomb5SU+sGCWW49Urv+Sz5tr8 Vn/zCu47q+9NOdE9sUU99OpUR69sMwkDepWBdg5vIFBPF6gokVUD8EhgkQ9A3mzVJkuYFhwGM3kI EAJSiAYFpqn/MzdtuwpIE8GyxTIQBzkd7e7+4ITBkfqLTrcvmO91rY+YRfIlzWkLTzFQDlGxMthg O/Kyu9WdqhM7DDAjq9Khuwfayp1wsDSH/Ok7ReOU5zj0XUoE77QsFSSJISCMu41TlaRDbzaLA9O5 g6dK1L751Kc87oXDUOt0SKXWKbwIEInxKL8/RYrrQL2veFYgv6lcCYNblZ/USwo0EF7rdZtazMZV jR+vsa9Osi0m25IwGMBJTQ9R1T/QC0jEe8+nothUCxyaevXSx0xkY+9DkOdXgqYQEfS/6kiJgBne C81of0PaRCFor4T6uc+KxAJ9BvGtZmpeE/pWSEpYYFZiJ2eW8aYVu0kbV9/PMp61+ttFBOhNM7ue rvdZWmQ9mbk3BrLkCH/Slt+OwacVqBTxD/hEwVR4Dw8ZNfWx4fDvBSHrbUO2+D5Q2NhGsrYe8kOD HlJ91coVsUO0Z+jd/TjHvNR1l1AXdIo5FmvQIdBSLrt+PicjNAKzvI/sDrP/+nWqWB7Fg8YDGWPS zb9So2iEHOu62NE/vH/aM7ZnMK3vzpDyxuf7VPr13QvukjKJBig9ej/gvoVA7l1dBdJiqcJOfbUs 9QSeyEJP1RusYpzAyjL2md4stga9RcUheOXoftNsFjIsqPyONKecjqlbtEKEH862ohErU1llLe22 k3A00fMbk6JljM4uosQjrK6AWtSjukspgbvZ97IhiYv9kUvM42GAij2tpR13DTJKlceorTsZJ7ZD KgOtNzLpghGP3CfJ/qFmfuLbYGbPPoTOzXS550olRXFWsbR4ztk+37eS8RrRd8XPpSUMuKpdxyl3 SU9ZsUxZ5C1LYpcTGUt4K2ZFOREamggrnn8v1X1BbALp12Xlzqk8S5U3D85N0YShoLv6E4jeotYU dyT+5SWeD8rTMcA4Sj6bKtWDkIXRsQeMOU5j9tXb10HnGq1CngRoXX/dW7n0pmFtwDP3izdO+w6g JkprQDoMBgHADleB1rITw2RlcIglN6ZfUhyi5gBnDc51Qa8i8Xt6JZyf16d9PG4+ljj1VGIE2xQO s9N+2jCfh69f/UKYG7CkMDNZniTYfxcjBGArXY6jhT4LM8zUrBrZTyBtwEGrEFcdphlgoqY87awC onvNoCgFTGyFy0VTxDL/ffIBSVfXhMiOLmBKXOxJTdy75UD6fepKrdadsjIDt8SUM5lrMoMMXt9/ 2rjJ+VTrgk8189PD9hOl+a0Shj1KbTXvFwkacgiz6ZpZbmotvT1PgdUOHfF5WWsFLTQdPwm/hQtv Oc4nUblUqIJbj0vok2P2N8AKcjc6JICAsg7atVAD88NtmqXYDvwiu8xhFxvdXvOG+VxiwqcFLc+A b1S2U4sRcMpXFQOaOzqdXHcag3xKim2zeN9JqCUNjS1ZXl+lVJN4YdtHOBZ/JbU7CnF0a8Xhh9Fg Ah9mHf4owyHkydnGN6NWTsLpPeb48AE8rtFLBgEtF/WRZ8b0lBYDwdFHXA3eE0/lv+sd9fJGjliQ g3BfRMeLpPYxBsZVKSNkuJcg6E/gd42no6ye5prVM/WfcXfwLud4xidgo1ChZDH0bYS0pNgbdQqP 7GTiW7ap1WPz5gU6hnypEGlSD4cqD0YzV3ZZaEw8w27RIThcQaOtD8eqSTNeXRh+jKiZiu4m+SRq GdL/WlRK6GllGNF+jdTb9GHgLdn7MNVWyL+C/itufbxJ6zY0FP690opKP9P6jQ73nS8HVvbdoMh9 G+k5RmEEhZOPm66gev4Fa896KGGbcvbpEEfAEpTMKGnCPI0T/4ddMs0rK+a991etypIBMiV5HFub 79fyjd3lRfdQoVgx+f8NMcRuzZ07WOsYgAABnUF2TlcU+LX+kjfBsqCjD9n6panw+kyuODGpG7IH dR1gSCfZ1RZAt3tbTU6qR0Kxr4KSSAk4Nqulu4ee+eWOcsi0t0pwnhECrgsvDzagxZWplFsZnhai 7+JJ0GFG6QTMAIU7XfTzG4jWneHUySy/DXa9XGfpDXTMiRs+X3HyDpaoL1LmbR0WCIDodJfn0pzU 3RkejoIXblwji08X0APLWOlAyZTRvjsf/9OK4OGXViwAhexe6i6Gg7Jmjm4/4p4h7VGrAsOo9iXe AEUoNoJiIDyE4IKn+yZ22dgM1izs8aAXNZgA2FX1VupbZ8CZpmGFNNLzTkUFV1tEQVRoSM6E7gMV YGlVOCSApPgIQJihhoKXOWkGNk+nz1rg8yawjHnLX7I3FM6IoZgYX4nLtpMvWSAazAsaFqrK+kdQ 6UCQl1ookDsO1V3umlneM95h8ktHStmALSghYooeT7WuXRvFiRnLYL+Fyalwc81pyDr/kE0DjqLo Yq1NDqbZLRiiS9FfGne7f/r7McMBlwchEPMzingOTXoSteYEEKaI4iqUrxqMNrhIiKEtHLgbG7RM XzJpKPe50feFuLoeRlG1amAp6EFBYlpbv8Qwjjl7TMbnyATHEDYj4XwlXXVRxEG5XJAxpsnB/5Xf j3xhuGlJhWGVy5UQnYXyWf7nbhdXi0D2DT6ZHXoGMaBIrmneH3xhV4WGL1VHqi+JWYL1RHFuCPJZ I6zENIjxs9Q58gTiDyoroNe1ZMzf5OnCCTR0M5h2XNWmkNfBtANi7um+PUj10Ir/p1sTmtDGsxXe OWRs8p0y80qpeE6Q/pIvYwen8dZ86gjKW97evqfUhiO5g78oya1B6EfiA5b4kwlBOkYmo6K4oO4q wKmU5cQ7Kmg9L2lhwqUvVP1WI61/9mPDgZilVkfAZoytAOQaQgFXGP3bTgjqlClGU6twP+RT9XtT Da5XIFueqB9HdiZUrJfzq0nKLDG4kLY0It5BBsqAC5DNddKaeJoxaBhaVwSBmg2d6aNV6H8HK9EV BgjgGJEvGu42sOJyXiFTZyRLMPE95Ts0OpDQSAsW/pGNjbtYs1yPmNCTvaDCSM4piyg4PUd3+DlH 23poXXshdL+3IV56pDBjuPeKONi1ke22JaUcAhZIs+PsYlUJSYtxfOW8F705Cn+i4wVorU+Sn45B Rg0d+hYAOF8XtpPR5JWe9geg9qauD7tfphc9OldoZlrkza5xYoR94WqysGuxW3/TzuAMW96zkToh m4Kx+uLUv6XRXwo7yHhDQFSRqJCifRwxPX7nFqgTMcICuYKSSO6kDVHeA6U9gadvmhpzA6KSg3P9 lePWQI5w1Q+smqpN+laOJlbktk7cRsQ5KpjswPEEuko1GMgrsVZ3uxCFR5iS1Ok83v1N3NPrModx RpJQOZ9CGSGwJ7hZCsGdwlK+uiecKBov3hE60ykDtor+jQcmqP52h+jG+dOmxWtwAIXt0olLUxcC pybGIAEyF+LsZ8ZwReW7BwibY1UKzspZ2vPhIBsEYAd2FjbnxERCPSzmSD7qJxaVSNC8TUyraKYf 9IB8+Ez/Gld8pk9qKBa17EyB7xpQm5J0pMYAzobS/iosHbHYIyFk4KtSBeqmAdhwz/yOzJSLUIfg tdZf4FkUyIRq8LR+5+Jt+asknaze/QeVefne3HfCmiYNlcc5ACpIZ6GoZvlF0Y+zfANIKcGPT64h cMIMvP3hk2RbHewVQueTHakhJO/35bym1fkGtZhtcV/mu0HwhWNMnK0TAtdtb5RUOLpqIJhdwojr eWo6AKVOYhhERRzlJQv0BlHGWEMfsK0vsReP7LTdipUIjSmn1RnXi7+XOhB2Ig1v7XEMdf2iE/h1 +fuYFPARDDS5wSe5JCXYhZImcdb25QLuhWLYPSziX9LGyy1d+itPkY90UXmfrcDy+6C2ZKB+XkUu +nFOXju8P4UtF5zspidslzlhqjhvg1txY4zhzzxyT9DuMXRKueCqlh19DPg3SAtPtFjXQ3bPcYjB fGjoZ0lOrEE4ZZk3LhuM+letzuFXkW7kTTFDpAU2EletkZpyp33nGhsXv3ZbSxymrLoCzdwq6lxy b9lLekJqPej4z3fWr2Vj2flLDQV7mv6FZVgdkpysX6PqA5n4LhJd5aeVKNSwzlhEFUepL1FtRL7J jzl4SwWN3/JYrC7YrC3qZT1ZYsvBsgAKhe8W+m1dtISEwgYJXe4Qzcv72G4sC0PYOjipKuiLzfZA 11iKmZdsyKEE0SeltecFMumJ9ZJ6WYcYkPEkntOwt+lglEn/7JQJHpsdKaRMVh/QTqJ33h66J8qy 1YjQUZ+Xhou4pIZ+IwedwNBlLsNlDzRnw6P0D9K/PE7MNUeWUUPJCdLFkwNU3/IFQFKbx6CjcT7G 7xEyQkr0m1XJf0CE+Lt/Qzi0AP50XKWCgasVnNJ5BKeR62SrvN0Uw+igFueHYsmMUiC/9NGjDVSS HGKLHq6Pwa2gsDTxeD3c0vxjt0hw6GJlM4O9Hw4D+9+q9moM3THCaoxvWMdpFqBkJnF+pf81ilMe gfMYP93XgyzoiniRszcBoujh0P+C1mm1X7XEGKnvjI15xxSt7WkjjBtwujAGNhDyPIM3WEOVgdTB fIJ1t1vx8WWaWreDEWMOu0v90xbUk92wSHd2+He0tuh5c0RcshWVBI6Y2OwZwKMhucHUlMkJdIq6 2n6ERfUI6Dks4fWjihJHbbxzIR7FU90chUd0G6lTdATI0iPgD2I5IKNvdMjaj0exUqRgPrIGKDdJ jcKz0kffmDUWqH96Oqi3MKatTWDqm8rwb+J55cdfCxLOyaE62gtHYSaw4H7BNfO4bl28G2XpULf9 iNyOnegQo7BbxZolHcu3GC1Rvh8k7awi9oeqQPiipLdwV7gtRjrLWuPR4mWWz2L9vEw2EQ6lom9g ZFtXwp87UeuillraueiXeM/N9rhKASuo8/FzVwkIkIQG3h1VoKgTGzICtwz9lYfsplRFoKlzwtyj 2xIWUli9rvuQ6m9gtBoBOuwwty1znNOO8P67+eb9VLGz9KAmbIYY/vJeHy8ew4HVQ66lN/+xMosQ JQtlpoUev3XzqP319y+7ndv3m04S876gG3eIS2Z9Bbw+v+kdZx0tTz/36yKS6VXPMMw1E+xvNXWp JHDdrLzY3+5dUmFax/yKxn5TSLh7arLureQi8urGN/RewWJ2d0tn2YJFI8XlW4/33O1qsXMY97Gg 72tfHMqv657n7Bx9ECP4WOm5AiUw/1ZbfYywJoqzKn4okc5IJveCnhJ639YBbEVIQO4upeVVaigK 6s7EkOtuQGfUcTZ1ScfInFybJ0czvj0IL9TaC7JYigcsgja0z3cVJaDjSkR2U94J74L2r8IO0zSA V+S3uaMAhfm8gT3BxCb6uLGG2k4a6RHLTu9J6nLYLjbgLCjgH3hGCnChW3ay4jqM9F8nrf815LLH 43oLoLfxiUqry/ObsqEjHsG0ILFt8ZNxXyRvvdPEKEJG4xrycA2iJfAAQgHObfD+rwDuDG4KbTVb ftNMBVnVa1QYq+9cNgXJKUEvfz6cqRotOILFiqHukMw4WkYRssE+XJqaUuOhfTlYXdItWXmBJBPe PXazIv1/PRJwPfE/JlVCko1+VOFPfR+jkpu39ajgoBG55ZNYRD5yeYfu/MdOc9dZIOy4uAGqqQKW Lwc4eNhQAaAwMDKcDwTrN86e+2XJPT0xlobjsThVTf/DVyQBgZ28MEWLwC/5plXfaKQs9Mu/WNA5 fzOTI6SPDNDsgWOc5JUQbiNS7Ms/ZC4Q43ezzBCBFvfaIZDtSmKWDmLhZ7CiBVdLbfVy9pp7UUXS /2XT3sd7b8lnrpjfy0kcczEIuKaplNgbNG7cYinTUgjwUGoqNdGB7dWddXTGzTPWyQJ0ST1m2IeI Du6nOnz3O1+1FecGd08XwAZTVqO2H7Y/bNjmzWcZ9Pujiq6PqBTVsveI5vH8OBf/SVXG4Qwk24ZY nFgzRQP//LjBgNhCpnx+La0NZZ7YvZP9rQsBZl090d+VKEmvhcEY8XDyig41U5trN9Eqgk1FTybj WLanEyWSDVEI5QeFibTAXrsDnw4zIVNiild6E1pnj6qOZk7wBUwcEkcVBfy8E+XjixDs2K+o8AkW Vo5Ka7Bwp3SeJxdrqiNHEbKMaU11q+DF6fcVbQhzfRlTetn4bQEJRUQqJzjOINuIEj3Qr/ssPVYl S1GEQXvtQH+MuOH+gA6UyXgh0ZfpVNhggg== `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 26528) `protect data_block EXRvfgPLX105DaxDyVaBjuOyVwr6P/tCMlDVfjC7yI8UuceF5KplFUGU2e6wIsGGSVRUiiA4uYOy jKWMC3EzA3JxoUIsyZlLqfbPE8CnhpMsGQF6MW+1suHWH5rWUwBX6dMiFNROBqXjaiYhLMfh8LOu zMlNIAC1jHuQ9MSv6Rd5So3VdRQ6Dk18p7HfGOnwCtTmwKMcJSpXFcK09/yBub9C9uGUGaRXKFh6 tLGBGFHqQvnv7/OQE10ZC7wzKT/iAmP1mExAcmyKoRYeHERxvqKuDW9KSPad9yXuZtOQau6pdw3N iiHTrwCCcOdKmIrLemXbWsHvJxFyrDnOQYdDOGojoi+b2nMcyuv8jgeJFVddebsC+toQtJmGrERX s6smcfTf6xFhURFij6KFRfz3gcVyiLE0E+vfCD4kVp/kW8StylJ+1wQpWjWz4VAgtYf4wtNpdgFN o/q+9wBT4nfUdxn54G/WAsJdfV2eZXX3A/Xn+/2y+Rj/4asinFoFzSdaDrVHlSjll4Ls8qjrNZGA vb09hUL3oU7Gfvwkg7YVE/b+RBuDail9OBqjX59rFzlsn3H5TuL4RNoa2kwy0ICmD2Y6wl0r3XyA 7UC6+oVUKBZUpUSIl/U/DT0ntLUakeaKRdp/L6nTexQq8Opxl8x6I460zuaMDeFQathIvZLE3hv+ U7qewN1Xdc5y67aUdxG/gGZxIbCJa2bJWgqMOfbBJ7BQPlVglswyqgRDBtc/DBKg/1cabQBknea+ IWIqeyfieJedMFunlxOWdkbIMGjOj2VK9mNehDsVGDfUOdajBIuz92G9fLBgbfnb7Hfb/U0Irnsg AJqcZhgjwJulGHWxR9Wkbz2TRlTY+B9gtNPXQQIB0nn+zZGOqBpNst5vFFXCEqHgdEdgZU2O10hp Vvv09/FU8N+dtFIAuHH+6NzEfLYOjNGx6rXxP9cm6D0QQejZs9WNdJArtgjP8rnaFx/A4/B8bWsb WRmSniOMFEnAZUKitf+C8r0H08UuZUt1oOOHDxl/Y3dCKxgIRea70bPjN1G8kMUki4AZwTaVLLKv U24sfpM5B6WzYiwO6DPlObEauOW3iUmRuWWapsoKLeEX9jyj4+OLvb/z74aNeHOjJnyGaAHuRZ8Y 1pTCTazcMCZZy02oHEUJAwXw9iyG0ike9zAmn3C1A2a5DtK19jFxI+QvcN3YSDZq9T9ocnr5lPgz TUiP65psWJ/xl3SpJTcmP0yreJqDy4mKwbUFjVc172NhkayDHcJ+3HpNcwGVn+nVfUpeE92ceJLM 8JTtDjz/2hroTi5JM0dRmPqkxQFNn10i68aL//HyrP1PL40/GDiDP7C3+MudsIHGgEZaLksKXLL6 TPEKX2mVerg5GANF8Wp0kTR+cgP28TSiradg2CR+GWWH19hl9f+59UF4ucSIB+s08c3bSchfMw61 +qEN3w5ojaqNlEzXWSYhlYYbt/eWKt4g5BQkqqs/EZz3b1IJXh5JJLBNpP1OaNgQZnVW0mSVqtXw gAgpIzD+iXxsuxnHJdRxk+xU18MPOrLcGwYNbACkYg3gTDzkCVYak5yH93fZqDqUYAukL5C4ZfwI ISpZiy//CqNpqnCh0GUep9JR7nQgNG3Vp9MA+2c/Ec6GLW9WLUt3dOTW0LrcNf2TOe3uhHzJEM7A D6Dw6LzYzxm0S8dlmpvsvHNBR6OY3fgzejjBx9nGd/2Qcx1EfotSN4ZkDgLpAPGBivN9AEw4oioY Tmyru9xAxnu3Hc82jgQNRrahUrybZNZUPTku9C+7DQPQxJ8zA2RaqYjpjtQFaWAFfUKY05wkoXcR Dtw8VsAdUlOOjR+KINmr7210hdyLzX6s7VreDG+F0Ypu0gTkXGBh9sjebXNhWc+3VpArHfzHQi45 owv4M+80JREZJ+C904fD0DV5AGhUxpZy0reBk5QrUoxqyIPQiFaNMlD+k1zzhkgH7R2ZQbblYLVB AyeFUVbhh0fcM4AGBIrwp9hcD/BYWBo/SwPsP9dx67zq5F4/pIJvM91kNcQiONgSNXJltD099mGi kjA1j+uk7by2uz78ZvEqEJpRn+qiaXwGcz6K51Pxi4jyVXa/c7WvNIyR6AzpwWkuDccoxSA7nryC 3PXcxZoqJ7u2E9IIoSBZvSz3G3A3m6OBKa8RXoANh+56zxE5Y4J+BnLdIYDPlIsbLRCOfUWYnXXb EQQt3Bn/N1cDKtZAjd9Moqnf00pOg67WrD76O8HGR5bdBwW27NUD5byoerrnPEkPgz7YIbURWN4r 3SfoN3PMfnN7GpSDUJiN+ATZl33w1wW7S85b50wuDhSAhHplvqn8QVQ1S2qsR4ZWBrSLMQcijkL6 6y2nttQn0er542l1Cq8E189eEYgLPWxris6r1BvLYLpbGhu1GWt3gtVWMEJ9TtEQemDzEBlnm7Mr /U2pXHoi/jLjP6aALwbhlUAnyDxnNCI2mQ34GFUAuCMe3gpJxEmicgmRWiH8qiJOISSXuKyM4czE +H9/yEjbkRbj5jmZfkzYGro8nHxMgseC39hMKgxUdnjC+apYbdtAydrRRGLvSoG4M+bO/lfQ5ABb D57dD9VfOV1ZDFTdHKTBESD2yeUePzDbJfcMxmXUzZxULXwxWvdYQ/dZQHXfAVvGmriHQbl5zxah TxFUIrAQUUAS5qUy6xd8qZN62zfL4jo0dbvRQuTJE+i6AOqEFB1kybgHf9oYvZydEEIahr8otZKR Qth4cgenVtE+A9bSEU6VfA3QTqk9TJJbXvB6qB1/kSUc2iYG0SiZM+8uUZdax1tbh1BOZh0HRO2x DyB7NRWsR4jlCUUEMczTyGjhpZ/hec8wEhFjgfGkEfS2HqvFoVR5ib5BNyzazxMGb7xHPNN+UEbZ PaDPY1FZfIqKRugqSqXKoDTe+277BNUUZ+7licQw+1YtEmf54eO5VpyXH4CTuXSWPB/xd8y/kuRb x6OJYbJlyxPOfj486xMp9o5kH35cV1BSKPJFV0f89RBIkRGNM9CvZBCgAhBWDnk6xBFFOLNP/fyX GRDKc6TwZAp4pKq9uLskfQk1gVd9ujSV46QGpri1zsTTvhqzw7EGCm1ZMOpD92uIcfLyL352uR9K 8e95DCMJEL+IItfIbfXwojXwB29wMHgPaIaU/8LJpNIH0ewUE7iUTEKVdQoV+bgqQkdBJ6KRQ27m M8Dblv+07yubnIUD2LukA6ClhkxAgw8geN4TjKmthu33ezhT7hFfRB+V0fGtCjP/Od3zOMEti2gM 7etA8M5JO4aZ6i2WGy7TEmtpTXjsQM6b6/uf2IUSNjl6Y3lp1GKgkvjM4rE6rchnOriaXiz3wMUN FSQKbueO4fGOabKD5LCw96UetrjIXEktD4AKV3e93WGEHvFxVpUTBLtPvEJI+n7i3f5YyY3uNQ+n rAWIyvLHTnDGMvxq6U0DR6fI0g7RLrxX4S3T5IcPkWWrqsMVZH0WWmbwWKwDZXsm7OveHojgyzLp WO3eEngDefIj6l5gQuQMXTckov9GUquDQac3geqLQXlIny3CAPD5uHdTBMLZDzLDPtMqG+2XCLEt VgpzDIveQ0ej0WUBDMczHKT3ZuMNCHchUmKhHcUVQVqdjE+0z1yTCAvG9hRo1KWotLRmvP11L25x XBLCBwJ8vBwzcZ/K9uUlndiwyAoMFikb+7eDCsz5aVDp38dyvWUHzqtjNORR9hHhvdzw9yryVY9V ZW0/Fz+93Monyw3iYcgXTYZZ2yk+Rviu2k5yYaSZ6CqbkrSjU3OVx5qXbeR9k6BDWVJTcG07qMPy uoxP5HmeS9VdPQS0A9TzYnI47wyyqHKqQg95VAJFB9n+XR58YWFmpXm3M9/yhqYFRVAB3MqFXqST esnaR57pSNhUIC7xXjHLCokEB/fF9DaXVOmJJ+Qfp3Y592EWrXCPj1LUTKeblFXOvmaGeI3hSH/B ZGYxISIkjB/+ntY8nopGal8a4p9iy3u7/4zz6JhgTBycRlk82JEUlo3B02oGxj82lADe5R4Asdtx +kVtVPvQ1t3FwoIHSAV6QhdD1UzrdoKNdX5+HtjMLDnt66Q7XHKaXkl/2XYlGxvSP3rivLUov+c+ /eaf/0RM+pUGxb5FhXxdXuyHeOP6B+2kPmqq4AcyJbKXU5bchcGWVNV7yvalg8xUkGUQbUvUYoIP CF5lqxms+I1cWhyM2aHq/H+z67KqYkqzMSpQNzyeMIYf1jAWXeJZX9Qe0Zih93q+PWHvoLKUBZj2 x4UVQDJ3qsPa0Ii2Z+p6Bt2EIQi+8EVa89SjIXbCq/jLcbzEN+EweCufX3+usz2Gyg/compSDVAK ll6QTm/H+B42J+glBLXQ8gCQzd+pHU9ccnekBsPN6jlOyetIlHctBfPlw6Wp9HfbuGBp5ABSPSPt Qwb5NRVBTB8AhhQRv7ijy+uDX6cCvCTuN722XjHBdjUYAxEHJJuUE4HGDm41jLRiJun7I6XToNiK 6V+j2MZvrViOC7YCQ7Ih1kq0s5JmfK93tT7JSH2buIHjkA82LiwwHjZRY6qYygDhMo7vZMvfxsJ+ inbShNGgRrpjo0uR/UXV2/tq2O1fgRaB+saGcrTwqP5mZNy8iu6JmjVTSC1Ncuo4EEDBzbJgdRXP 9uen/dmLwK1TPYlRPwv4qMtOBVdp3pX0haEorgWT3KFtks4vmjSEB+kQCNPoX7cK840tYtuWt4Jo l5kYiO2qqy1tcC1vgwl+lhakZQxKr+HuTOP5M4fuzhMk2pmHY7n/uvR0zd5hpZ5UmcpGMuqr9/GX JQDmrT8KB8jQdL+gKPF4C4mbhqG9iqKR6Q2MBxZSrQbrj59OMfT9yVQ9aUUG3NzwJqFkV+MyiEf3 tcD0f21iD9HY8uV88ETBKbGIgz1QycLEPLMIdXNfkW7Xyl1ZyyuBcb+aNr3ZQZFl8mL64Jt+cBFG sddI6gQ9Xkm+57M+Rr9z8uLRC4mIDSsy/bJ4xqfSy63MZ+SISJywzBOj/t0ag3vPNdsC4cvN9CtK v6VoLo0TmGu4CPlOIJffeLM2V4hv7GtQ60gUb302Zjv8kibzw+vYszBu+Su9xOTEOLPWfoU0bl3k wnpd7Rd3rhMgs5wxiLxfnQ+TQkMv5eWEVK5+1fDc3SKRApqIyJ9pvqnE3m4pS0pdvPEKBnmfYDwL 7uqdy+7F1qUTvaHBhxSNDMsd0e9zozKU+WYomLJWFcRbZ1k5lsjRJpvABoIdAIOWUurf/13YKUsW YMYGQZ/uUcowMOCS9ASXv52evOOGA/moxR2TOkEMlqh3dUgPvEL2ym7yuicFnY74UafG10KrVdrk EyOw0tYltho2+Y3OAbrbbWMEYoT+fHrygNxyTFqH6ryWYWOjOoxWYco+uEr0Xqbl7J880uk4xSR1 KUGhkUsjOlWtBZeO6hLEXlXYW2ZgxYIHOVMQQ3pRf83AgMNIBoTtb4Dk6/Qh15h6vlbXe+lj0p+n ObhqNrRQtC5Big5t4OReiL00X2QA6083hHa7myrpXFnrJR4m3tkxnQ1ZzbXqr68nOMj0iHozzC/S xUyUibVTnggJ4IjvPzuAWlCsDzVv22d7tMSGliRvRyZnzLy8KltQAkdsbCk4jdLxt8jPY58GSJdj toyBJGRKDR/Nh/GCr4TpRF88fN+OykzygAOJrz5Os+3+0s/XqLrhQ1cU0bc1iSeUO0dK6tfVpcCo QgKWOG+WqGmepsbBWqtZKZpPeNm+AoDJ74ndFfJeXVU6oB7B/yJLSkZ41ZhCJL8ZlgzXCnYQJQtk WaImCIzWkcf7nJBU4gOwRatBddgHzIuHKaOnQI9bIuhqcDMSOPZL/o3RIuXl+6FIMB+OdI/Re3QL l1iQg0kfu5tcmztvhZxPl2Eqcid4qm3p4OMllYV6vHsAIK3no0F+KRV6+g574cEkZ9pTbknS6d/p w82PwxjiNgDzsTFZDcQiTbCOjV71jpb67wBIytUTB+WmoRyd8aaBKaOJWUMew8QQCycylLjntfV4 xn19VXIgwvsqHIXRB6TKViQhXJGEl+gpqWGvnUz8AbKJVuLUtMb/ad8ZFRcpTJbEeFsc3NDqxc/1 z5bHH9CXPvrt3MJIerIqzmxOMrAdRSiLOD6GiWuRwd2Bvwj7987G+G6RmC1LdM69qGS+m/IwisWJ ye99m3U5kJe4FZ5hjNsqfWt2h2dBOik9vhMv5MWIxJkDUR3jmQuiyeLinG5Yr4Cc82VrowDPjd+O uscCa/DfoyhXppGEpl2ORxsvyzWv4sxu+o/vr3YdoXSJLfO7Zrmb61WkPtCt6vMKWlEqGlgO6Yd/ 3vz3XvQdGKQCAfqBfaoqLNrLxzYsjOGyke71l7B2KbcZRfA6IjdnWsue5iWWfP8cyZXC5S4tjtOc K9gS7HNj2RCtHAthUKFzfxfjbwtiasbcCM2oagsypPmVva6GIPzugG6P9j27QqshU9H4W8wf+hZR yWpQA0FAz9YeeVCQgNNZKa4UzQK33L4b1EtkmV//6hdSBvsyGebYfC1G0Zm8L0MCs6Mdy1RNSiN8 CO/NyJyVsB66u0QfAIgqHgx2asDrK93yUd2OvX6wMQ731u30e7+v6jXOrujawPXYLhQH4kWm2yLN zPKxIapHCzWnJ9CRGuks6jphZ+0cslZyplglX17PHZjxwQPDKCvtjxTiMvmy4vdbmwBl7cKOdckD W7Ryfc1DVAeIBdUdU+YWi+zjn4ELq3joAQw0/kO6ylLCREdeiVM2gOnlElUFFaFKnsEh+UzStf/N eOZ7EtAnT2Bu5xDW+n32yMAkUAy7XlBIhzLhAzYBnMVYScdQ2oH/wP1TUqEvlrqI5p92FucF8xEG XyUnQN2VELtxbhi2q15yvooGuBBx7pw1Vc5yU+vLADbvFqzmEqZxCkOJb01yct/VFAgHnRDRq+20 gq3Ntzz6ER4luc7e+RdgTKBcPpbXvMCoGk73FAUwNmgrpPZ+4i0uf/svmD0yCM989Y1IONXqi+nj I5retutFAEqVVYYjf9HCQe2SXDnIX+jw4O4l2pLoKnWIGfteky/cBNGcQ/AGVAj7MP3piZ/yHilK P6LRgiEMxcNBe9IZ+AqaTQ8iB9V7SyzZfojSl897NnstlUOWKc7MHspvXvU2ScxcCDU2jEySmIpM h4QCcddSbodWP6MPto2Da7fn+w/3W+g1MnmcXF99h+T/CHpNYK9XjCwXp2etKsZMlvx/oTv+itNj CGqU6v8bB979EOqtCNUcLeFHVoeW3/qH1Rv9VRjbYM++K4vdsfge/f4JAhgc/Vu4/po22Q0T2qe0 XAqejtFvf+ktDPY+6+GozP2LTHtLhmcmg8LIhrBtG+dyGEzJoXI7aCu3GJXX6O2beJz8RNc9iyON vn+oKAqwjf3Vonu6gZFNZLkjHZix3JBYQFqCx2BlEx2C3o+0urSOpd0Pqb02enbOYZ0hcr7Wxj/x xMhudnh2zvoV46MaTUiRY5ZYPwBlSgeIil6p0WdD5smwx4EEYq2ub1/BOLj/eWT3vA5wkzDUNE8P 44VkwqpWBUBbLzOaANKQmajBIphcXZLOgO7bpWyZFb7sbuLe09vLbmLdjO/9SG/o8jwg5VqVYl4K ujGCikAAKDHVSzoooP1rE0XrY4rPu9yO5Ph27DU7AivCbJNglO67BvWRNb73x5TWqlHXbwh9veEb x6cl0hT//G3J1gL+udBT0fiUzRw60MZPIugei2Hfptq6qooes5hpPCsxkiBp01miNzsXOOdp92xL dJWdlCTKWoH6B/9PycT6BE2EZd7nczxOAbqzuk52tOVV5Y3Ew8oclLGvCkdE1Auj7Y1QAsg7rGil m85fNGp1zG+jkRMUAFU8xvoP+2yFw6c2AzfbYjQPFNzurOctlqqiGZQwgMgRT9roH/uQNnXOR0y0 bH0gBE/tYQJYJ1WfaIxZQ90VNg3T28RcPgrFUz9UsRua//QZG6ViQ18ZmCtebBeYxFpXGTOqwYQl Zy5Z7IkolVJxJdFbglRrkLdhh4D5I4vKaegima2PXijnKN+iQ6E/7DK83mtnOyLiOLteMrVSxR82 5M/Fxp4VL3JNmy5FTbDFUr0hKnLmgecw5avSOsEZfv0pKjt7SNcGiUcOBPdhIRMGuJjexlUSwtnA 4/3FdXJy2gjYCw6t2sb8f5Qe5Ymfdtgnu9DJWzFP5BCVxESpxGDYGGZOu6grk9+9DHpB4toYbdAK V+BnH0vkhP5uj5R7L+72gEn5CzedJROQkm34Hs3o9wCO2qvjAM6EGFbh8L096DCtY597bNsMM0OO YpfBrfH+4Q2R6IJoP8AdfLDRPBGDzNmLdIeNlmAJHLpt2dQBSoZ+/N770wYJBnRxcUJ8UQSio92S xk0ByEm0SlY6L1XDBIci7LlcwuC1pPPhMMl7ZfqtwQTChxG2LQ5hDXFEL/e3vhwnL2GXe8iY/JxF uqMlj+Kgs8oc6jdUf++C564dQ2Apyt4RNsNPqlkqFfI8chaQy2VIdKCKy5MkqiqrdovIVfiAod1m RR3UVY/ai88RlP3GHLu1uxIHkUA94D1L96uoCRbHChTiPZbrKerGR90lrIZOEdesOK2FyAa9dI1j Snyzzznfze7UsK1TMB/2XTj1Y+nYcPOSNd97gQ9KD+rCVI8/G3Z2kocW7vLj+Ed1Osm6uzjJqp8K Fo5lhrI1r+2CYIoSMBAHUCGxvkyCQ8SFg/Lw6UuYn6UpWRmlLAiLOdV2yKzckmN4S/pMrnCmBBEt b5JOfyaeo9C4UanOLl47WwzErCWykxri8GNbtI7qBkaCNayT4Fv/Gdl37YcrttieLYAtuxRlmY/Y PEv70uHsjTMKwPRnl1Bxxab44YFdkn1JBdLfQiil98pHy4qBnVUBdtuRG9ztTCmire2qwiE7XMHQ bnGeIroHqz2sVexyE8/gndo0RiZHyah2HgHVI5FN+wjmaYlgolnJ2UcBGErhpQuIN25De0FsOhLE oeF9FdrJpaVNH0yo89RcLdUcXF2PcrkuHrCr5L5/grGKsRwyTI2po/d1vdqx5dtKsoSOQ5tva3Wl 7R6X/KmN8wDDXDeFTxmpAkHnJqiJm6vydZByc3PAFwY0axdsoreyEHGte0jnYXX7q5twdVV1tJ7c D6HZo2gDGMixeCqeGA9Nbqu/DkRZ7eEterWoz11d0L5NVNEkI/E+zQ6m8HoqtDD2s2tMffIukcmq 1Ou+/SWeFbjNvW+awPMJaQbZkRWL20hZ48kT4Acfbw0Cc6fpt0sfvXglszP5bjI0km/pUAMEu1d1 iJA+2W8UIPMxKyOdiFjonL6lzEH0bpbZZyNJvuaCgZLdU29HQ5/d4vzv4ZYHTWSxFeOyvPxcw3Xp MXy7rJHwdwk5YiukoObcPh3saxWWnglIoVa5FxxKnl7X/bOXrpI9Z9ywqA8wT9G6jkWvBCZgdfCJ aodpYQKn9pgmMsb+vqNy32fhjPBegP+78gyUHE99mlY7V1h6kTeWLO1fPz9K7InEB1oIk04qbexb +ZAJzhN7HL8hItmuNVI/Z8t3gOq3v6NxldOeZpoaOTV7aJtIlZKtrqH74lMr3fopuOX8KvLY7i3P e7RVd+bCJpEvAuqbBJzC9B9odDTGprrXkgbRvVZYCO/y7ZCSrB7HvCtW3TSDN8Jxsk1hF09WlvHF o/1KmHlFOPQPGvXfCOv2DKHWYYVhzRzmsyITvoO34IGKwYBsuze2puIuJoejQ7AXIZFYyerdlY7t c+3jm2loiqU7lubQeNBER7qUSKgi3H+7Q/3r2qCV+Cqp6QIaZOO7NTgr/gZhK6XLHCfS00WRWuoK wQutFXaEw2yfYCLPgK8+jYVfRpGAxN14oH0m+BWEdqUh7J1TzFSDoVEBgAnHaM9obYM0MZrkpPr8 6TxjYD20lAdw/jYwcua9NFCe8eVc3NSwRDNCMNxskDWR6pxfoBmBacFjKJ+wOx3FQrhB1XHWjB0a z4oYKgf7MEIr80/CY7e35KJdwQLAwvP73hONwFjurfZfJde9ugS+iLXApm+14/AHs8ta+NxP1DZR HcYB9T+zSnQKX/Y6VfvVbbEvDd2z0DIDhGp94GxVEr8ET5xFgs2QCALzywWLPRLSxnKIABSNJRhQ 0LJuc44C+uPpBIP5Eb8LfN6+yne48P0dEpTPlDxnLLk5YXSeB7mCuG1J6Fwgz33Zzc1cKLKQ1WoK J8trYqQqBO8ewBtbNV27r3suycmPYvzXjXrzuGl2kE+wOwitx2bJK2UvhT3sQvD5DkCFya5uel9H lhegnHwJoLIzotIB6JDG3132z04H4GaFFLkvIWm0SSaRb9OxydzdU6G3kCmsXPEOJRfcncqGJv+c FFFz4emD1OloxFxIPBSK+itjhXHumfGRV+K6OsQi/QegtKaSXbbMLsqR65n4NZ5bMr91llQOVGCk Rahu4y9ymrncYhrL1O7c8T2sUv9nzlRkbMWBL9BhVJvmH9D8k2gbE57e41V7Yimpu978lMlnbPby fJkl27yLTGQkJKNoBExiD1huzvyztbSkEMRhnfdH9u9yTs4zHZ8JE3ZPWhqWn3hONFWvYAupNX7P xAXZV0jx0gJ9RAKZvPCRY3g794CQWEhnbYaKFazEazhmqMhrcASVZv6CQm1lrfUynmoLfw2PYlPl DwCxNcp4hQ+3VALAeI8Y8l5doW+Kh4uPKtGKCKnweDNeNm2n0UPizr+SP6oycCGHD4fkzAIzh7oV mKObMneYRHRHlQ6yaWI+OCPcbLc0GzpG4o7JhNX5UZdKJzksDXmftnyFrlCfskCqhux4m8A671PO Hk6XpztHEc09CrOjXh0vePrtMsqTnwkdDHBzQo/Llb4Y45CnlA7f1WZBitqyRQ4H+dYW0TvzctZw lNCDgBrmqP20p5VXhuQdMDlKcc0FHqYONa5KKiBIIm5AidUMaQbbKnaO2d5GVRW0sJxAg3hq86wU cDbCW1WpQGkYdfWzYEDtmXablyItQAehBwjubRDVPBu/BC2nvzAUSxGb8mORn71Jyo+QwbT8V6hs gY6xbtNO6MXPuBlaWl5tReDMHAMoxx8srVRyxXYdrULDAFL6JrEmk8gqvudYzsMIw0Oal90j8wkK uIAEGDlW+nN0dwmghb3lBvRsEd+qsfg9SP0NrMFCdf8BqajlrueT6rN3xtJXoEb/DFWMHebZmfIn c9DLM+y03EvpDPgDOjTN51XyJC6OZCaFrUh9hDMx4dJEYdOKu9MUFhPZzVFA9BO3YPxmpY/hyuHY mhvt3D6HgGf+d/Tr9lNb/JJLw2HZag0zFeNZu8xTKfRc+Qrlnl3mZ3jL79FWTrzG27ov2no4zbz2 fdc57h6ydq3hsauZSS5pphKmwL4XiPOCFOkpHUnovvxmZzct3pnBSL+j/3Rzimq6h79SAd/PF/Bf QcqHBI/cTtv99MFEf1Am8qemBJzGap6yssTf+v6EjbgwBuAIoRCdckFs8zRLBq3SYxut1DFkAJu1 uUewakcq5apoFYEfwcHm5EPH2P4NbF5mjKqpy+D5WsXaBSUo1HDNk3ZpgrrJQrLU8iK4J8InMaIp B+Fadw0DYGrgVi3KuH+h+7x3tkbR3fVQKh49yJ520WkuDvFz1I3FPbkQDCt1bO7dj8NTLBeiXvgu cXta7+TdR3sW8KAz6NMnqU3Q75M070kfQD+b+LFfWkPjbUox4zAV9L4S1oKP3TWn+yLwJfxCq3RR PJZgQMJ88RldGe2NPo8TJoQQLyaUxFd3ywfmE0VcjqMkAC2jpxj3MsqQ2y2nF7XpeMctNmGsTIJB m0pGg/MW2YIOE31XYO9SDLb51JWSm0QCdLN+qA0dHYM+4RlUlAzGHJVHTIleJzJG4jPdYI8rjY08 nDnUMdfE/0fmhAg42z0eJ73BvNGR7hCp3QzPY5M35iOCOM4E1tX514lh1Tfpx9q65FLhR/WyOGae GbjNgUPmAiveFiQNere4jOwO9cJWyf5J9gIRV2cLI7s5xbgDCEI6cJtGEp2odKntDRTOQTsJ8ezT 9saMSJRJrrJbAbQfIDYFETbJNyFc7znddFsJ6w9v7jxlCiaRyQuoq1S9nGHoZ9pAXmkVqNoVbZ2F G/a+3TOMIiVd6qy3drNVHycEohXDZypoB/TbMUkwzLlVCvq9F4Pq5FCc79HE4CbGC6ViZe1gTViJ yinG3LPCv8A9+XURRc+w9DVTveULEpCWGb4BItMIny947vDeCNG8k46IypshL8tXiO5QuWl8UIYi GnGbBA7iTgtWiWMfQQq/WIZvsihqimoEbgk+xJyB8g+G2Nb6Zi5psCLxQll9kRqytGdlr8+5suna SlVx+s8jKViFVSW5dobNBTVgr+WOEgEJFH1yUhAoXRs4plfGE6dfFI0llxD37Y6V2GlovHdJPznV +tyHJpsH2H/wDK6b4fMfjVQ79ZrDu/sNVe4oB050FY5jETbOMi99mdx9cJh2K7dzmyoqYUfIqsUV B47nNfcSjPprdcpK1aVciOitAf8mNwWHk/jcs1yOSrszHVYymZHDykVuQgWlMJEXMjCtUL7Apr0f rF6vInlgJTch0NvJEvbGeqWx5yolYK+AKgdTpF+Xbj3TauKTME8ye60h7u99r5Ayvig/HSARD/8/ qtP7NGs4eA3FNuK+YXdldEM2exlRU+FiJJdA11L+xbcdtfwM5vvdlC7dFyQ+HWjlzXVbr4x9YAPF VuP6juxcDj7EQWaXJeGPF14WVpMiOvwiu3DfuiT3cIPiMaw+O82uDgwLGB5b3xy7pQn8dLUyJ2yn t8uToXqtJ6OKaJfLJnBdJwXe8Pl+IuUOPLqgtbsQcOsBF3tCn3FRj0R0Tk/5GfD2s6e56fujkr52 qU3nGLAW3cvY52jYPQ5GvpH7S/+K8BEEU/LifIT6liths0YbqpBVykUbtQ8X9EglVjKYZMPLtLBQ tYZdYGNYDY6nfFUGL9aLdhGGTQT9cMYQdovsBsqeF/ZYP/WxoMIL6cXDOwikTJXleY/FcYukAvJr 5ZmYUzMahrxv+AR1h8wUMgMml07UTlPy6LvG4JKP9H0m7NjkGgBILRkWkVk9VpnQKqqYCyrTxaRe VYP4ntgmod2IO/5qMi/02TV5Sbcjd38yiUUuqaNsnk0m9kSIYitHHfftpy4pfBHDfkCMdOnxkg95 6rqs43VPDhXnapKLk2x/ktNjoWkAoWirWlOV4+N1GOk3u4F7m50wLM7oUPN6yzyP03XN5zcFDt92 xRDL7HWZmJx0HDZvVEOGOfA+9EP6TLaNB1ve9M0J/EJxiZ6r6dawcGWCltNdRPPr2qO+NGmfCzjH iqR21ebTOApNlhH/PR1ML9K8pw74d95NZixHO88Y4YYSzr/mh3TJZViSoyp/2v6HmOr/yWiQZ65U 8x/FxajLoE0sg9XCg5pIOtItV+LPH7ABp2g6uLvx/8YZIGYdiXa1ZgpTnIyW4oesYEN06KvwHtyb Kol8oHFtw2AY+WlxfTrC3lwdRIoTNwi+zf5eZyvylbAR2ugrxah1mXVCznOrq1H5MWjPDK5NnVqC z1DU02KAVeE3StejISjhZXnXxyeI66WFK03mdaSUDnHzHf/ECSssI3e5RcvJcypNcAMP/vd9bHQE lO0oWSJOcHU5DBs8kljEChExNTN/7iV4D7XAVFoBw1Nu54EVUXOQmNwsYi8TpsIsbZtTgXpewbtz VYk49W76EsyyS4bGBSLAeH2bs+JwpTWbUOVFhsO/JKb5nDCCYMCbe5zOw/WGTdqAmMuZsAjJTGYD xqd/OWecMAckd/9+CnHRcLU2AETGnAaEBqQILPLAt0tlX2WKirjpg2sfQiNCWnYhW2za+ZLIHOcS s1mVFyvBiECqXhmhdgaTPyUhod4AnsFjX2/tPRrxkI5iG5AscA4X1G+Duye9QmYDsObb8kdPj+Hu VD80hk6H9OHJOfEA7MS9kpHZluhOzv5gj00RnTVK3Eu5nVgvHoIHK3vU1nfL6y9Wesc/gDctQcbI VbSCbXO0veX9f97szRsy5xlUByo9WiPr8Qx/nbAQd4dAV+GfscptsYbiGbGsbpX49W0hfiGKrbEk Mjae/Rzk3C58cR4ta9L/w3RzRYKOhocVzpRApipAQ1ThJzBQMcceAJ7U6psAy46ruJ7JC6/p6RNh nXeTIUwIjTJ1PvvCakxMxHdGver6BzYL4WzyGmv7U7UuVrZKoqRcOrx1uTo4cEVn8+fiBvEScm8k tFDyC8Mcmkj5ZIPOR5TTFVJ6dHf/K8iVUFFOLTcDIcrsaVBxLhKr04D4DPfMnt7mq+WiAPzv54L5 kuU8Acz+bXKcdtcK2TRGIfzsny9zRuBC0ybFBjJ9lfdVU8aJhNVLAepAam7/ZbNpgGe/J78Qvvuh 4VYqjoDcnieE7/Q3IPyYOqtjLFRbb+GmE+I7BdTV5VejvQlz8yzAGmh+Fq2jk9VTIiqDjkHAnawb EdjQVHmnkCel3C8mCiDPeMbyPOxC+u0wIuRX0q5ciHJpL2nQCmhw0Xlj+UeUQAebxgBxL2dnlFPY /hi2NAZiCsyu3qdJPe9iiMxK6MAKqVs+ID46PKZwpI0yoVQzJN5PUaO/9F5E7cARV2kc/puOwZdK L+jYhk0iB/dmoCQkOtvQOJkiU+xymi4mE/WgQTfn6bB0BPst9AOyHsDJumoOoTjcX8i1yj9EwYa1 mF2yNcE0/SvmhsMl8nh622wg9wveReqNelF/cTAcyq0B4mqvvBosFkXvhOVa+/JA9AZ1D8XIjOhH 93yGFkTpNIXrBVpxmn/b9uFitEPL5R1vfwFMWQi596zplFzbrY2gTXP9AF/mfoZTWPYtQGJLYM+b 26+QvV0MKpmz/SIvHa7Inkqp9mtmBkoRIlcAIeS9fsg0doqBCRbr27V6dBivVyA08YppI+5H+6tw zmcnae6DYGrTEkR+dGgnFYgrgYsWEOybfdhZMTeJbYjEr8AY43CsOJMLGwQ2lbZYTOECRxnxlHUy t5D5swCCWer89Rcj+QHL5ITbadLHea5MkDqUCwidYty/1ZCjyZr6FtXG6q5O51R6UCAoS7lbFoMm 3vBsPhYUIcABpCNTYqNpPN51OCx1fLwh1qeraUa3Ak6nDOpD8j3fWtnZqkqzm3+9x5HvAU7O0JMZ UeDaaKPqhFOic45q3bXqDXnaUaZxnuLLH7eZE41nEJKmBGNEsF/OBGtFUa2jD2O+gNS6USdZBSMN GbHIhhkz6DT2LQBy5xp+tU+xbmckhR0OcPrnotH0+rKJQIjoySAiPa6Xkb2LHNqsm6goihJNbwNf H6BQqbQuSH5nEzGH9GsmVA2Tqmi85nPCCZU3kyGantOgB2khxslAQto7VUMIKitEr87nBzwbyAxL +PHsXhz2nmUV4xT6GNdYjJnfZJYUdRLRCjy4EzZTpUbWgxuOJgWRGw6ZmgIi7lesCH6Tc4y1XF3R QUcUo2/QwNNYlPkR/XMXCZgDWesb1tVTQJIDaC9na0KLiKtMxhDbGuGxgi3tkM7L+p0nO85Od9Ru k+qMFujlYziUtZ+l8B/PHOVo+fsWZWzrk+dvdGL062fugU9CYAgAnrd3UJ9Qlyg0sHGMa2jLaRtU MAzGquB19EqeBV1TmP+kBYFSUhw02RodsE5LE3np8ZSSUmpdnwrIeW4EVG0JfWkyDu4oxC9OKfmg dn11H4+4oihxZet4O6afODApxILAer0zd4+rotpN0NUaE+0FvtCVEYtjLWfLFy6H4SDMtXla4gO3 mKESqIDUkbkHJWOjQqvpc7V8FzTKYhG4l/5Vrkwu7PYHYz+LKNoPuMF3IuLKifQyzjvx0BGdYh2/ ZJZ89PK2KjAmcSpOXwYfEUFzfc1BRoWVaN4OdT8QcmiiDjuzNPiHOYYVth3qlBteZftJSC+54xux 2dDtlmwl56bohLRmQa2kTW2hA3K6wGYhqKga7vbeVPDfIwx3NrhLvMIZ8jKGSK+s6F2XlDwr35w6 UGDfNfUFiTMtImSJ+YeVkjkkEfOkTq0viFI2GbV/7f3fP5LbzUoh4EP+6ahmHGa9Y3/Mprx7kXQU 4ax5qvLbWz3sfvUkUZdJUl5NdqOrxDPCmnnaI9p3bK9luDH8jb1LEQV4LkGdCw04R/8it29GWBx3 DkLRdkpUXIffz6BOvDQo4RSXTegPQe9WepmbwulSTx0Fdco3DYgI7HCmHSjqEgBqaVetJOC8NSbK O3gdNHSeYdL0j5+9swtGARAQzkD4BLqbldEsEK83E0elJ/GBRbRoxJ7xM9cobV6wYuSO62y8bTxc w28vlnUhI5Qurmc0rWnQlpqdMmFEWtD572OdzVmv3Gs8I3Js1s6NZ8Hu5GKG9PpawZt/Bu/JwF7G 4gvKH0w5pdcWH1zKXW6qxJD75WiZb05NRaLhDdNmhWXSy1ULpk+RrG2fbEO8BCUEGP6TvSYOGHUu ajfPijindOQmoVBIIQmmkQDmQlKMoRo1HRJn2bzRgjxR1sXsNkFJnY1xw4dUOndzuUTqsMF9TC8U dX2f2G3xWAi/zEWXOgZ21NxmrCZE/8VsRCmcCzRLoMy6ci5jb8CQ+teglP5ewB3/djrevkI2pmvB DXiKwnyUTiwYWHreeTxTgUAnyeifK+SToPDJ1sqBlFfSkRJ+TEYrwNDBMzlDOBzlWZ4N6/TjWRL8 FF77QNmUaF5hpqBIZz/35r/CYnUmTLs1Gojn/LjmnRVi+zr3CVOsvxrgO/wrrD5D1iuDhca1DUIf 91LVYEC4ogzyA3ZCKHdSCrlefjQmw9bPm9UFSwty5k0vPWVyFvmJKYncUQ9niXbJSDgwsuqTDfHg t7GIH6VYVIRgW/bcL45B6j0Nl+7MZuIvqj5tXSjgTcy0WnkPu04sUaH3V1ZQiQw0wNmJS04Qctqg 2oD8gQs/t1VLhiFjk8BxYSQw0TK7ZYTvTDCLceH30a22WVMxjrWnJZ2Yh5LJy89TpSaE8HktFguS BDwoLA3VWdaR+8zHMIQ2mBek3q78D4zT37t8lpTx+gbC9ND4rikpOV6ApF+9E1zeXIXyNE/NAngm MpXPlwOTTobk5nDnS5DUPKabNlsaZ//uvAd8oujCnisJlWrhttAduPNEtS5Sbr4A2rs13+dIvGRl IbKfP5VImbuE/xNBTfPUnQxsaE/XwVfUmxlxXlzA299+t57ngyg/5jlcpOk+qo7uQhcSIPUYABkB 4QLyMPmNJ7DID+vgW+WXmnzzJTCe3zbL7u7WH8Ozzr9DqxTjlifxv+RCL2OoEm5HjHbNI8PwC0Qe snRIe4Jx9kJ2rXNqbZzwDxOpvwfoDFLcVDRdFY0crbP3YU+5ar8tsylNTWp3mXbL+nz3wnXjiSyt /GV5g97+d5DgRpaOMlB0o3XvOj6KGZoWZ4bcAST/TxV0Uv82jz2xZuOAc/mAEcIZt6d/S7HVS/of FTiOwjg0Tpb8XWBZ5PI2DOBdpJAGRWsFBM9xz9S1NFvJlP/UgO0uykx2RByEfB8C7nAlqEQFrL0/ d1ltXfVZG4BP144EImWdwtBRR6JXWYJcoQyNhorOk2jJ3c6wSfMs2F5S/q6oB3UJYQf1WVH2sVe+ 88Lu4J1KWOshwNq6MQP40lmgja93L9MmNx85gN9jKRORElaDJuuCByF3hNMWgUXiZN99i8nAudsq d/RnYBnIkwB7LNcDrxs/TeOq6wtdo60voEWM+WMQO0SkJveLSfAk8sLHDl+uKthbqnvOKScLy6r7 ztIFzYnSGzuncv8wcfh0Y3nzdXtbb3k0Z9gaj7P366EkJRKsmSGjycvdWCxGdpHcyz18U4blFf+6 8P4+SLWibo3PI2RVyQeBV2iXA51Zd6yEMRvFEV++IH8BuJpL2LHw2H70WIZaoN4u7GTl7uH1gBTA KgGOzfmlsySg/usIOIYdx54TV5aqdfF73Gdi4JKj9GOgYQSU7nDqEIAItfEwdecgaxvAKiG0Wxpn MdupAXuKEaoNx9635/CqdkRCpITnc9I1ekG9NPA5qSOSKUidJ4LRf0hDelaF2Xu/ei/ja7SL6eDh oNYHP4Vv3S4KKrg9AX+AabHB8tO8XwRSI1NmugcsDHFX52FupvDEwfffXi2SJkqOUtJg/axFHZij ptEFAkcWZdfAbqTX5Oc7G5fXToupSa5O2uo0MKK94tpVQN/FgWn/13LDDNuvKIvavUe732YvYd+D dNVmRi+vh0mtgq2frhxGGy4/BjQxqVjzBnNEKo+x+BkrkccGu+jNeAszaNBaOzp/vByZDDSxTcUH 3EQ79e1r+5N/j4hQusvCOy9OKH5xtlEo1bef+yy4hVjpQVPs90hdPBW0G9U9MUHjvoclT6faF4a8 Yv1iyxJgqbWFJocvMpM6r0PSu0Bct+RnYAbTgz1VKCZFkbtNx1Z6nTasiCvuIRZhIM9DRpogYypz 9pTbbATgU+9vGE3dwhwkegdTo048smElk2iNOhK95tl9fgPfpkUG1GaNYZzBILJcl/vua83L2clc 5npw9Vd5I9LHh1TRtLAPQTIhK8C5g0OjL7eJfLrtD+BpzRaQ9FXpb3JHvqyQvvYc9k5fFX2RvJOi CpM6s60+sqrGjAeUY+mZX6sEEjqHZrW/CkiF4YrrIG2VgAwOsXYDkRSSS5i0yQlpdhSoLn0IQqY4 UFF4KUYT72411BCG8i76XAGiERXS3LL5eAvK+/4tcktAL7rYibGKPLErPMGKLGBCqFSpEzyv0WNz Ue+H4gCfG/ktguDih41i6xq0JlWIPK9X8oycDo1kbLZcCx9QNM9rP6cyIWdpz9mdLOKSYE/a7FmV maEhENnM7mU7XZ6clB8xxIUhPT6GZcSjz8H95x5xvK8msbTYx54hqUtUCUYgYgh9KA+9IzKcL7Hn Ltllk8qA0AVQAtHye77bIFMFaaEIb0sach6PvwUwR5u/B5193MRZjB+lDprlIPph5/iJ78gJXA8Z frt9sS4TLjwCfqNTi1H81/izcxy+j8r2LDcZYDYPkyHZ4qYgiEAwMT3a0e9nWb5196/5vP+mz762 9f+4NDf+/esAGrrstQXYYaFEbYA41LwpJGXixQEzHKOToT2sql446fCjanp9Q6vP3qyhKIX5cuPd rCEzKs/81JuK3diqokjIKUaSaU58sUVagR5KYmj/vv0M3mHlzVFtmM34Kuh0gBNnskhGq7OAJ9hn i524pj+S7QCXbQ3ervbHhFvFcib34OcsGfVDQf9TQ2t+xUFvlXRF+vjuqvOtKIPFxBhTs5jk4/HH dOUjVP8M8+rN9+d1FkcD1dbcQOWHzTSR9CnhLE0Sl8W/PzU/eX7xVNMxXehgGn20/y5e9ad+c1rd 8DFSW+39auMVM5DF3pHgQ0vZeKVNcJTx8VcFeShMspncJ3ebx0om/VLZ7y/ON6qlwKn99l5OBnmE wVSBzfzNn+fkr6cLG9WQF+NJo65MMsaoS9qwnzt178pR0MhPrS1bKQmh/ldSeIlAVHBS/4+SnOrQ cnwBDCsgHbj7ycKVc4KDPY6Q4Xy+sEikIpNYUNCWt2YEjBDhS4QfQ4hAfc6Akst9VCwpi5FFytK5 qO8rvVk9qsgSEJooHhwqJHLdp9XVTHeIXGF1YazWY1/d/TScQ5EoAOUL5X7D9qKXn9aygkFlAlVK ySO5asQX85smjUtnKykBSKq7TmbVNbbe9jCj3e2fXt6LZLe09TBUFX6rZu4kEDvOaSzylG8Znb7F VXASsgS5CmsiHcyStucByfKyAr4aq5HnJavHJvUkxfX8C8sqrkm9Yjw1vuzlngbXSTmR0mTRi7rV EJNqQ3xbslW4c2wWWiWK3/3mmgaBOhBZ9Rg2caGiMCwO/8o92ealuSVqmz2I5oSxGs/QLA//rKBc ZoI90/UpWwAx23OYxnLdyr7uT6zZPhsauYtON3qo1CT64alkYK0/GXD6AgFPfqT+Lozwy3zcpV7p 4L7VaxibrQGrK2OIi5aHZn9gQEI49NvR+Hl/aD29kOEcwWwRmKpdKfkw0FVWV/z+nlF7xks6dSnR r/1pDymxSQu52/kqQV9h6HAYaeusHKuCTjGjgAMAWIAGppMpD8Jh6PKwnGkZdR/3K0BKsXYB3ZVm xh17tuXpjlbw3uqaGW9ihqgC0aYFnC8Ei99PM8UQMijYsaQhsxy21NkjaULubzgCiPLvzxwPAUlU tXk19yqG8BJttxhxiLNmGRQuVFdf+r9FQe5RN7JtCsZaVOIdaJQLk1WopSxEkSLuyJhLtOixgBuB BfXvYHG+pN3qQ9iGkI2IrcHATqu0RHwfPLBpgWNyG+J3nPf8J5jQYzgmPNNOjy0sdmOD/OtqdsP+ GnXs/17/F9g5YKguHtWc77Ox5Gwef0enIaza0GKKLgXGBCafDuxqO5J6CnjeeE0pLwcLkecZLOdL SNUn1RmcRBZBylczuHnFXHT6yriBdwZA38NqHY4TF9CUmwBCOMqYkRWTX5su2qHFQZ4tu11aHSfG FWVfEhlzdKYKYNA92hdasLFHLHgUO6MmaODsLCrnipqeooXE5L/z+66p1nL85wuAXfsMrOFDw5X9 epGH4xeoVdE1aGpmZryritmDwuGQgBTE4V4gYLsLDqDrFDgIzPDrIZOY5QBgFEADqvYh9u/pJCLZ GQHgFel9YlawfslBDZX0rjWdQRPDBSqG0m7utmvIkwJWgNnugsrg7TD5ftNEDbBZiAnfUCd/t1Us Xaen9QUIxuOxIOcicsNV5t0dKsg0iQjCeqYmyj5272ffsCagviFHl4eKEGsHEMT78SXUiSWU9N2V xfm0U0oudFNvbOuFmxAeMahQWcoE39e1JjM5qVU49wGswsWkt/xwve3mWH7wAXe2xiBDelkju8lo e+3iobHlFBW82x1NY1v6WGHY8ucE4KLBnyeEe5aPwKc26XAPDf+VO+Jxel4j8pm/OwrPE1rA6Dck BwZoLuEjbJE/nlQd8E3lgA7kFJOccr33U0NkeJkfDh7A7inCu01Wskoc8m4exSEWkBQi9I3Eu+xL 1pKFXkaIyqEOERBFsXfp2hCxrYnvTbN7AAM0OKRHCy6hVHA2XEJW7uO5bQSWXa2oPARMPhnqUNxx Fa5aP0Dm+cpXoMtfkLs8xnhaBPGV/Lb/7mGVlOnvNF5/O9lUZ5Mt7g6iw2Yf5dCW+nQ/vpQf5YWJ gmxWDFeCWG3N08pR5ZWUBfMeZgmWZHV8ltNsrfafVRMpu41/bmGn4vB7LVtymGUrvjPT4crptOAG xPXNRxh6wBgjtD5ylpDXbr4U/+igOKkiSDdH4yXNHUwOoyxnj4wLn6Ln1AFKnlYoX0N+KYYI+aq9 1+Pe9tPxzZo19ski7XB2TdgpCGINTB8ZNklqiTXPmY/IJzHC0aZYM/dRAW5Z1o/go3oGMOQgAcIc uveUfJ4+XwQHEkBD6xD2NecLg3K7aIsgxQzn2Tj1XHUMBAyjJGpSOuKLS6kbgZ2Q5McfDRVUUa0W ts9cL61vhB1qB0bZXuCTVo4Z3n05NqXQIxxcakYteNnD1j7WgFAMTdnbae2qD8DcS2lYVxhJloA1 vguz41Rx/3xv6BBgLYI+J3tBfVnxueSyEZyozZ0eNdRUFD6++h8mtjgYqbZZcuQEdVYm4W2WqiYp otB50eIB3lbvb5OzKDDs1bXJVKOv50EkpwUWBqBFRnjIsqCdASG6sy4CdfR7lWlrTTNmvX/u585e 7EaYmtlfWNJCeCnQkpGG/dD3/8Kcp4TssnIBr1+xEN0Yi+wplTkeyQfGXO+9qrK5gKuQXG9wRdrL 48TYiwuFHDATHgSwmoUS0zPrdrNtNG32Up7Y4LYw9nQIAh9i9fjQCibvb/6O71LQyTT3cG9Xc7My uAG3qME8H9PtItwxLcAiBVzmGFc2/ROrzZKQMOCfeyQ2O1l8e0IEjGijtrYffP+NcJrB4sTZMzU2 +vw5Q6bn5g1JXttSrW1MXJPCr+6JabNMN6OXIiiD0DNoHNA3Dau+DoMj3qR/UubS6UthMbFhPA3W J1XIHhV1zweInCFwPU8MSyMzjnKb8tEP3FnDy8rAAuJXE/jeeP5PMxhO1fTEdOyvkA6jJwgmF6en 9Q0YFAHqyEWFc4pfjlsqEIhiMGU6HyysMaYLQE4yGDSVgEqJQrR3307IBDbhU4EfS7oDV9DQIVnQ qJFrd3GJNnfueWOZ4zOQZqDhp4lGmhvMHKv1dWTwGW3vzHicD+5kFHc4mUyBkiFFTi160rGyTxBP EKGanBtGW1HyEuix0CKCo51zjj4n8AOvVbq5aijTrSzEbCkb4vnfiwPRIe9b6Z80H78cVKuyAsel LnYdVuYdfxH6mKvDaJ/XwRxfxfH8mRk0lkoMnHO1YIf0f9Qx2QfEN1y3H5NbuItU1YN+zMcox9qm NyU6TZcxA103NEQ5R0gK9Y8ntyCYqa63tzFzKuvC7ieN5OJmG3PMzTMkljqz+qRX6CzGjTmCrWT8 GyOtoAV5lf52vWYQGj0TguvbQkvBCZGQ6gu2wCbyf6DXG0Z7Y7iRXEm242Ygz3vbsHTuqQBTkMFf X3YJmV3e8BfrSImNOFquDBVjTIhQu8McCuLrKjUNf+rSIlYRaKmoKsAo5aHhkzE1RiAR37Vsljxz cCPhKeeinXb3UPCXDa8bGmHNUMh4Fm+/ysNy6cNyGjCCQkRoGFmOCTqM3YiwkwECp6fDNslFS4+n 6/tnH8WIRb9M/0ETN6o785BxdgMXENZo9OnA+40Fhrbo6FxvTjl7Nd7otxViyD3Xm7R8ur7ZUquy GqPYq3/e3CRK641r2H7h7yeWBSivMpF3KjbI1TIrjElBGEuoOMp4zAYrCRFix2PAf6+dDmT/vUB5 r8ovELlSrDpfsZqXVk3FvMb/9OyBMOAxleOOWjoMVcbl5YhS5Sy0EBZP1iEJKgVSqX8LzjfIlYB2 BqUjYSK814HsnMoUskOKwMpG/qAF840kWhPTKE7XL+iSSum3HEdUb5pH0t/D5Kslz5/lGqN+OCYQ NFaho0lgDwfSk4cdNbutwdX6tQMWmZsPpS1D6+iStn6aK19Qz4Y5CGv1g4YwbtD12kC/0ETpVZnQ weCJewdiJUiy46uOFktNwpzakXZk3RNtW16wfKPCQAqOhtFnEVDIIrSlkZmZwKKv/JC5NEei5Qcu 4zuN+Uc3ASMNGUMrTee/UnerUCTiM3Hc2AIwYH81EdXcwp2LwNb3goYrWbM/ypRn0W2eci4S+qQP 9W7tk26ptgqM/5m/JWQLH6b5dGGwkWnBg+1FvTEqvQ/BnB+VZuNFg2khQr5m5e8RZqpKTIoCGids 5wDV9FhZUqxMeeM41NKNuNpkC6k/OFVmRk4wpKkLrTb6sHFG7JJ+OaePzZ4VH2g89qJRfvRnpj0P +x/hFVmvl5Vi6CDcajBSTBOAe1i1Z3VzODwpa/UkWs/UEGLXQ08SS/3V/CAlPLh4cpaBrmLQQyOs KoaQFZHKivhpxGepPZjUC/Hj+VZwpg+8k253hwmcKCzhkQlI22FSceWnUFjmuNDP2PB9c6X/CKiy QjZw1Ga8rB1TOLsrOmoIyvK3fx0A2F6og8XyalxaBM4tvc8yMGbLRDDlvomQDt0cLsxYDwpMGT40 8W7r+XWq5QN42Oo57294gUp8NxsjkTco5BJn5U/Z23ggwTIS1FZZ7XfxQ2NqlauzjR8iOJnVDo+7 SCgHxIXA4knKxLhuOe6iIUyIMfK+fcRRNZnhcfnoqzFdvjAj0rY6YZjvc0dMh6mzrSynJnDY9DzM Yu8zwcyuaWRd629PbjmXdHlaYFTuIHPdvVkNh0dWFTYRQu3YWTZCnx1WkzjloBHIucITXegeLDco 6SSfyBedJhWI5ak/4JX1FMOdix1GiwW4uUWK2s4CD5BMF6lNQmj4Qa3IrhC5Td12tWvb1bFO23e/ i3vJN2qmUBWFh0/+aYuwHUGa3qf1lEObTWJUd8eeeDQGRadTCImIgM6WuWB80mpwoVgctt9pH0ZU GQ1oxBB61csKQEbcnoTj6OJW7ygcKXo+mHe6w0lZ3VFyQZJIDpo5WCzwSrwE0IiaU6s7hknQ4E8J doWfH9QihRr6yb7SG0uiXlmnQN62j/HY7h8GGHuaN6FUsdKf+mNIxjnbUbcBevDh+5hfhzqE8JUS wPo/UWjIMNICsiBS1w6YYXzD2V1DCF1lLJ/tRXimdl3nQNAH9P0k1OqZHAM1MWqbah91Dg2/NMCp UhzKaBJaVlqDQVOgCxiKdfrfw6lYZj6tEyOms7G52En86wMxyyqJLXS57MoafywJcue0zUOQe88n 8uCN1opnzfUNqOzrtLSxtNQq2RhcXuH+13Nk7FsioSnzGWL2GAdPoErjbx0oCjhFTThZOumDeJpG /VP8vFzDMtH/VHSgX08XWNtgch0rST3e7j5/mqWPlS3tmodxnR6MCHITs//fl52GoJrOxWKvFncj QvGuBTlcbOy4ovUtJvKV7g/iMmYsVrltk+c/h2gdFd1N9u9f30nSBGkBLWdzvToJfX25SqwBA2Lv gP6OCxCowUJxmlnXE7t3YmPdHCCy8wNuvskBWdxlCXDk1GMpFp94NCfS5jUu/Jx3ev5Xdr2bZz2n EaKJmLYboMPDhPnannFNCSwq+x02Pu58JapZaAhs54g18Iu9Arpm3Mok0Elii6bdfxjou+r26Ua1 x9ahXEuAid+L8Mv3SJDAgROGzGzNTh9juXs4DiaT/e2d6CemIdCecFKh/TC82oaFlsDppJ44omfh GSQbDD+3O9EP8+3Ovbc2FoBI81y/X+8QsabeEr/L5BaMPivA7sVvFets3WQQgCbEzAPQ4rCpuXYT uKSp9m76xtRv7gb8cY2wgukWhoeOfYaqw/1txrWJW4BF95RpwU6v8qLma1vNN0ZUUhVwWuSKDCT/ IvVpx4bBhGAH00v6YCQ1DIgQh9hCl6Gckvl9b/O+9FQ3HTPcTQaFH34y4Wk+7Xucox7DsNVWYZtY /IseMLNS4uYOueq+Pasr/lLiXRmwqMTnUE9QWn52cgWR0wIoHRmp8oeCcC7284Q6FaHWWUKNXEzP KvAQolzavLqFcyqzl6l9PA2CVSXBb5knQwZV/ze7Tyb5A3mpYaLUBuxFqNyQnec/4+KLK7/6E/sQ rN9cXTPRkqYQIuqQGt09GXIMURdGoJpEd2nQL2ZeDeYsk0vN2X0H5M8xJH30acBxZ5VQxkftx4Mz wwCkDCPE7KwyV0hLFMz3zQ2ERrZquinkFilqWXWqqjYwpvt2WMzXHGGmjMEFAzVBDcGQjqCKvrkT UpX58uYxXzKRBiB42zlP5jJEHiUYIlSyh+QqM2J5JxAxEWjggwcbd8IO8+oxsaj23YNNhHUAvxaT bWhpQPHeY1atJT3GueaUZ2Z6RCj8ICXwxX7gajvy9DujoIqgmf/27wlDjpkyadGT4AYEcLGNC75H L07zs+D3ZNcgbCa3Piy6VtDBcU48iePgVIt8qNTYkLhDPxwmfuCGEkzUbMw388ao7B1fEU+oYG6g UjRiexDUqRUMRKtOEc2xnNXOEIecvuQIZ4WKE8wLNrhtPYVtTarB42iEdaFvYfUes3vM15TQggSm mdZKoXVPrRokTPoC94x6QgdZB6lkbT6F5MESYtuv87bmLFd8tC1bv2VVryGTNtLVcbEs904eMJ0H Y7oUr/kHlBNKKngF2BoixAyEnnWWM2cle+vxzIK7K/PD4SCpwZxkTbT1uzZ0xs2hTMU0E4o763m9 /+RK4KrNLHS798lMzQS/CDsujYLRZNsoUdfPEORwfH9OSPBgx0EBS+n629w/SXFI5ZB6MHEWCBbv Lq5suE3iCp3Ah7FLz36wnUjZxil8RLexYQXqq2D7KQgwxxAVNcdw7D3gmBczDC6B2dZbdgcoHxTb Y+r4l5k58+yYb83Qx4RKSRq4Ci+Nu9eCj4aJpU0FinjTwZQHitm8pmYN0FyuCHTSVmR4HwNqiR+k W76lYNDuAR6PWW7qb2981nghVVlDC5EFdZ/VUlpAllmjkQ3YqLk7VO1zSmeFRniHWVhBEzE39cjg FG+xKiovhyDJRHiYuOuBq2+jZVLwOxKmJWgRL9IK30XsPjvj1uFdjTbCp6dvDC2eH+qK9N4cp0ZY 3ntSMY68LhwxP0Tw3NDzgC/gyz5FeMlwlzKFCzwoyQsO3oNGuLeemmSjMPqL8KwPmxBR1/MO+nBV S+jq83TctCL8z+9+MzgTQrYIpkRP++h03eI1fxZGrz6ZfljlU/ehMiZYMLGr4GZL4ykJHJaFNxFy UJlRL0p7RQfqsv8hTc8JA7nACL6DbtufvmL1+SFSLc5w0ufnI0Rv+ArslWp1MpERMwtUjdiSfb3b ZE4O9TQAxR3ISuW02GMvxDrdHgk68T8lqosK/k2lUT4sg8XHqV67+0HEPmLyOIpBPgvMdrclcf4w hjv5PLR+PB6egBMbH+CtoP5pH32EWewBTXrR/hbXS01ffrH2JYBk9A0KIZ00ZFvZVitiway1leAf d64p27yG5p2d/ffDQuxs9LC+3lCyNu/k4ez+7Lm90rHq2adIVZeST46zVDVlYlSUzf/GIEvZn17b VHTV2icvM6jze6GN4X4kN1/lu8MZmgeF5cyYAlTXuuGLWF7D9rOLCwNIFbi2l+wYTVe0LEbCHhLE kzDMtoAHQu+jpw+L3xzhVH5rmMbWBrQlhaAUUrfYfmEHkvb6PgcHLjSf04Ozf/FM7ykmgzAMPVD0 QWjiKrTTr7wC52y2XGkM0jeiFvHzWhgg5GAw+IFmxzQcWEBMRPtIfqRdOrErvkmKuTGNTxF9ds+w Obe1bGdPvzappYRpY1AsDWojI+5sitEjlGEPv+M1pm4LROH6aAoDodgaZz9i3hl83pqItQ4c6EW6 QtoccQSTznlfKG8EpkoOP1E9zdPIMMyntVJyFYH3YeSN08BUOJ/ws6WH+lwKnAusrinSmZ+rarga 0Xr7qNpuyhFG6zL2UolVhdxndcfzMQyG5PhK47375WUEXGkffy4B3IBR6Uo27G7f2ju4+TLOun5M TvsdwYaFWNueROxvvYvMTN4mAob+S8Y//xUu8pmVgM89mSB3+TD5DaBfUpJTQcgqJTVwsPiiyWru ZXcP2ADeYwC+UZJ0Dhj9qP1SQFJ/w9FaqBc1nFRTMDqEeUZReTP/amDMqBcY7u08xNwxX4mtKjh0 zOhpNymHJcbfFW9Nzta+HeYKNsBIdQpeHn4ONV2IaDjZhQNDfLARMwFz5FlT/V8aFhaO09JsRTZe tXEF0pj/IF3w2lun6y4IV2APWm59p6Vh0ah8PCwgpcEjMjXl44uvXhMqlJ4yqwwKie/GJD6FCzSt 8W80kWSgkI2ai30j2buRx/AJc//bTi5XLJszLJaYG3H43H3zY7zmYXFW5196Kuhh7dSAolKOwb0s 4KIprk0NSbv5QqGCHwZxu6kTSdAC9zh0mI74A+5bzsKGb6nwyeAypsTmsrsqL6HAnnVn/TCoawmC evnu4mdnrVqpOwPDkNh6nRq1z5sVbfGL24dr3KBc6++lJ/YZsJriaahO0jQN7ne1qB/FDxwUF7MK CBvxxkTBUwweDzZWD88NangnJ7QMe0jHerKiZ0ZSRE/fr6fPeVQI1So2YPDm7fdJWD9iBGe6hrCK 0MloOvH3VOPE8iD0BL9J+GHivvzkBOuaEjdXmD/c+8RUjOdBKpCLeOiWRYwkbRvAh9mmXCkZ2Nix dhXF4TC3EnnOAqR/QCd+/wblJz0eRUCVcHesQn3c6Xn8VqS6efvHxZaDFHIlq0EjxwZnVXu+SA5b vQVWBnkqZf8fgBgsXerSaE/AboW4ASWWPNa1h8lkvgxoiVr96iZ37N6p3ySYfPrWDjnJQkZC/+Ud VCUlKzePB9nlxrwbv5QVbLKN8P4srTPD8qlFRHq9LsPeSBC/7nTtLn3BsthK4UTaajhRJE+L8LK6 wBmyskK0Fh/3IH4XRMnOuczoc0EYm4pJpGvgT03Jp3lRGFKOunY3Jx68V7B09TEc+z0+M/DMhKCa CloG7ej0IOcpPnZe5ggY1rKzI7CFIAJpfeIbKvBfyP3mRnpLeQS/8pe25IJkIH8VXeEEmtUtYB4d SX9TOjUQEB4pg/EcyvBB5ecLyOrKHIdl53Z+7d/r9qXZ2jILlcz1VZTjTv7EG/vSFdwlKYluGh8v VmPV/+1AWGDLkuBoQozdJpa+tV4mERerno2HV907yGYqITQxTbHg6Ur9KYU32TN2vtaDTa+DI4RA ZvXg5e25Drc/QTK0p3y9LJXakLSwzeOtfYYRxRzKzJNgiDBNIMThE22vrfo29pxbCCG+YrbdAR0n CvMSog0BOBiRWEBfyOAC00kp8b1bT9jGk4NpehKY0+rCfMOj3YbmfH2cFJGPbeKrl+F5EiMM42mI WT1xqxkH8UxbOOl5NWzVb2pnl/hiIjLNfWyLrlobj3Dbh6UEBIi7hyvTCMWuUwYOCw7KsRgg5sdb VX3oxX6OTtl+5xc6/ueuow0u3n0onSUZuNaoCzhO2APipqHo9QNhPhzr0Y1mflEsgc8nNsM12gE3 cwIcoK6g2iL+AN21425beDWLx/9OEIa+Sx4ZchhAsfxsL2W2l97YICEIaXme8SQqoo0UY4bdAz50 /T+Cxta2FIJR8KMXcZz9d3dGqSfoanGMs2KcX+j68I3OIufRzbVmcwRNEiAbea0Lmse8ppIK+tzx j71B0tLTK+CHWae7N+xZwvb8DiKahFiw5qOLISRzPr+7+Dpne+hvqveveAM/hSWgU+0k7zvFQ79Z Nhgv7O4gY2CvcXfeNGfMM3YVDkJ3MJM0yLTuHz1sgaeLfDl/MDJTxYKCSufuWwMbLZzpkNLiybX7 7tPExZ6qdavCLfVjRMir3+95gDdZj1GfE4VcVlKQji4u+0XJPJPo4ikE4s2jJPzGCJ6g5B/DS+1e 6GJwIE7M0AeaWlaMbrdm7NSVz53p6XC9LJ9Ivk77K88oMD33SvqS7tchNvubIl51UVO+CeSqzQoD 5MfhKjx+Q/aCKJZbpebbiuFto7DAtxkZlg5CHGGdWEcqOwj9ru/w7ai09F90DWNRqzs8NBS+/3N7 +wqIpgwB23us5Z82GZKFshq613oJoIzH3u0qb7b/V/H7pyWXUjP9MGnAoExe0aW3nzgPIfHlcWug DLPSUE/PitxHh1o9loHeZ5X6Y4B0giEUV0I6UMjzHhA6v5KSNgkxnVv6axngg3aGKx3De48LGJGX ELtML93G5ptrGiaV4l31Bj36Xz3ekPiaJOthcxdUDWNhCfAuGMH3/ERuUz5zd/7aRlQLRBo1bIAG pwbL0/VuMfzKiG186hXRxQ0azUKrxZSAdM1Xs90xgRSM2TA1mYgKpJR22upEtVL2mtKuD6lSttvJ D4jp5SA80BQxtXxi0lEJ1t8/Nvb9H7lBbs1AlXtZe6ZDbE7dl44i7GwndMJQ3ZOHRrjVpvRqPZD4 NjFYzTNe0vihjVi8AP9Wt/ia4K8s5M4VvaTAK2JfRKo8Y9iwxsS9NH+jaTr0RlTyqVHWeRGbNUmD KWlcl8PvpPIcqJHT21KFNTbUecUaaVTWYYK13hqhyeGiqCdvJi3yZG3brBaGKXX2ZGN0r5NgM3+F 0M2RS0ccePP+XiMxlmJvkxKYp+5y0VZQGFVZOlmru3CrP2ExbiFDi6yHvud0PMhVRRwn95MEnVWN Cd0DFtp2+g/L3v95+nS9wZCWwkuJWQxaIORmeeMs7KWRw1ydc1DtDMAY5n4laEipV9OCoyd/v4Vl QoELGAj/htIGIUm3ba6w/EcOM7FGHlmNxDobE02lqRgig4Q/T6c9yvUfCxuQPpAlhiOAbBgNN9qR iHFyC6NuhMqKug5Nx7Gq2/3WW3xeh6ucRJXUZtrlzCEW1x8BwBjhZ4l3cg4BVNTDoc5bPlqCiO7o A2ZHOzGzpyU4wmsveym08s93+H1G/pBN/fLBPUE4WXCNYc1hXGbS+zst+q8QGWOBB1e1M+l+M/ke o7cjfwxplmoFGcu6fyntzvy92Gbn/6LnBncLKDCRunYmpWHPpzQ0AMdqdEbQFhgYrrNkM/d3qvJU CmKRTXvtai/d383z6xOmwpfkaNdntFwPUr1vP4HobGkEUhncDOJFH/K335dRaCT9+QdmYJNT47Kc lciakoGBomBjj7x9N2ikf7d+cKYjgz8Rce/QFo7NBZPJ6QrM66cTs6E0Uy6kaT1bDazvpLz4uSEE RAMZoKvw0pyZByh3QYyg05d45eoKQxwbKExCyYlwzIZuQr3e/aGPfFbjQMWYD5yniS3y7X+ZRsLd X0h2NUCL7Eg7H8nll+/cxir8Rnio6zXxhCOueG7rDPiC2q+QJP2/Z00+kUGohchdXxRPQVjtM33p jAH1L1GSTJKrPp3UrUo5HCxQsSu1C9Ia6FSie/PjDgPmvZVMhn4ieFd/X80AnEZssnNPmqb/qL0u FNAkEgAgY/vbusmSt8lYollMQryI2FUhZHbMr0ZPntaEtZ77iIqcNiYLYxllnoOsIX2qR+3C1JBB MLFb9xIqGceTgTZv2ExVH0vSR1YvqIdgcBwRovlctyILl8gwtdkYlg2jelksgw/YTSdJY3wx1xQo 7Z2iq5qwG0FHY+nsfdDk3jR8BPkkoIjzKKMNG84veiOQCjAbOjxCrgHLJj1fcCocbH52CGcxnaD0 BYqVwH3du/yUHPN2ZBAyGBLBZAPVw24QSgD+r9ciYbRgiOA93GWDphontHRp9F6qVDhsLQv39Vns QIBnnZZKVJB7mKX4jjCCqJBU2ctW/sSZbTlDZDa/qbDslcDV2DujkvUiccdVLDSCO/+osacVzTsb joxmAzdCLdN7J3yj94Hs8JT9c4lyMwFtxbwqreyKJa44XLp7g0K+BSYt5kkJuwgGwZnRl5AnA5xn lE36/eE+EJr9/B8NI6ZyPm767z+s7xN6GT/VPDW2pNDxp/X4CeDEJf5i6f8b5q3ogstviWalAYK2 Wxik5Zxz6lg12ff0ObeD9pa8eauMWTyAWZeUj2yyqgjg6wkOz/WMYqAOSKBGI4Cf22wUzYx2d+Kd jp07vdXKsEI4a9x4B7jDUU6ajz7cGuivnmYOXbvlJ077RKoWwBFJXuZMJy+q6CwR4iFU/h0723W1 /J6LhX2pOcGZUsO9t8lbiMBqhb3lr6a9OjTNPpp5D/zAMORwyjfqQgEfl7BA9NweoxaT5IyRZaZ0 Y5MRAvb8IO85uVcC9dS4/ewngJDzMW8+X3amPaJ6b6RCaEZ8eHaEgjWut4ZrMxEzrVMQM01YO58B IASkWxYPt6Dy7fwzwqzsqUi2MJeKRMwaNLBRRlwHE9YVERA8thzJj4sZh9zJF5snVr9qPZru4Tqc nk39H1FhZOU9Ba0LtmhbU47KWbYA0HPZUkDbEvLafGg6yC0CTbh/7XZBJs+9O/WPJ00MxLSEmaGC xzzt4vvrESg/Bc8Ms3NI9+MlRmOB9hsW0WucjhtSVs0hVMS7Ta0vsvtYx+DgCLBe+RRnOIcJHB9L r5AIMpclRhvGr0rbvKxq8lglScX76A2BKjXl/F8wqD0rg/f/xR7mt4IYie7UZQw6qp5JeZXfzoTX JtYDFQ8tiBeJ89dllHcBSjVuxOBWFfIlJv9cxOkTxQvfqXPJ0Vgu+1YVjya5szMyO+mqlz5rXAtJ WtQh/fc3db8Xu2auA9W6SzFGMFZWrFRxoO16XnMppbxooePaW73lUB0GH4b2jOob3dIyrwz2MiSK vKbk6laxtabVxlH2TQlFgHyGol21mKdzZYHM7bL/yvFaPDkM0Cbu17uj3c8mAMPqPzoIEYk6A0Ja h5rKDw7N1DA6mk2W8uUxnyh86sKatLbBzv6/lG7FDClhdost5bPR8D+pOjOvTtD8UTiLAP9FloCk MHr3v7mmCAUlN9/EQOrb0pZHhRbrO8gVgc7psrMHq2ZdNhHZQXasF9x0qswvUbF4XMPk0YpnAhBD DRil0DtDYjeU490PPw+QKSXw3GCr12MOWKmg39UJHyGyIj5rt54x6Gfo7ar3Qb9t6RlHgB+G0b2x JBoCLZ84Zk+8h2FeQULj6pIbvl61LKm2rukE0qv3u0cyRTUHNNVyuhjFMTtT15fv6ZkPonUdJTfy h/9kr+EbwnEOFkIjOYYMKUWUJz8edfhRihP3/P1Wlry18rBL1/VSELil5z+dnCR234zUmCoDu7rB s3QE2dPQ/WzKfwyuRb6db8VDIPGNeWbdI6RYcSG+Uk5aa8h0bZaowQAz1MglwRN6yHQ9ZwRPZwMP hKkgiAcCprIqjK9bLXIjWlRTvVz2i94mjDaKAvIcGoclfooCvow3oO6gr2QaTVtHnMnlysw0EF1m PL2FyB8ausnjwEz9g2JXIVfpb6tUgiwKZCeLGSK2KQRCMeTSrvA5ce6Ky48cQjDKW/WjUaTZEqaM nmBVYsGWtFkbxcKLbuEfc3GrDzkYlMluWKfWljpX8bRX5sFIIc77gGW3dYYVEdBIo+tZISA4PUnp B8SJ2tMjp7qh4kvhvqRd1Cr/5XOvYfSknJtn9oueBUqHUxdrLz0nGtZ2K4RmJ1xXg+dI2b7k1zHr fzVV5shGPnMhClDnKSz8+V28WhPM+cGhDelbbvM5V2O4+2yLM3nCxa+QoVCUvFttc1/6gNuMJZ2m OT/cepcsOrXX2zc9vVpyM4mk3lfDlEQvdd30eS1Bzau6HwVTuCM6oRZOIzm/usQrSVdxH8OymhIl YavTWQRrqVR+JBkNrVrqbLJ0+HfdlkhVL5lq6gV1Dk+Vc1pKlhaS4Sd9jHYmfuxdlaBnQlz5LWTG TbopGR7HusXG5atOQz80V20qRN0A5Jqds+DnGuBIdKS02JqSOc2VmboL+lcRKjDDSoyIPxEoAmUJ oLYBbiJW/WopLJQYoqc8NVhbEFb+25Px/rc7T+L3uHUbxVaMvdiP2viwHnzuoZXmI7R9w0nS3TlJ U7cFNZdWT3MCe7EfB0BTKA6356DuMVtix2MM42/7cuh6nMOezjBDx6SBCT4zNr0SfOBRJmrcr6rL QX6sVoP5I0MHjk9ov65PrPd0TKizEkv1A4/rxg6pf9vU7GMk1YwdQmzoHgVYnyVA5iQcE+tjuK/g UGwQmX/x9Z7rKv1D59kZNQ/lkemqwyduHnAVinOGsJfLDrptZTpoTWnzQNNhbGbKEGhrjDk6/OZz kkhG1aGSEwt/cCpVee8ertyKmeeWdddrISln67Gn9n2vBNjD402Q3zeS1OkZBkUZYwv6jP2kJRHM o/Qwuz5auz3UJBCpD3ajVOW46UaEXMpcO4O3D6i1LagIqA61+4ja6jlbkLq5z9msWAm79twFVi+n r1RHGVlyrGVmIiWW/m3oLyIkF7pO+9n48TidsZOQ8e+GtwOfxd4C0kYexFJ0B5mzaQ1grs3Xw/Hu GGDd3ecIZ+Jxug97YgYez0YZEQSXj67Uw3QugRQKWdTSKZz+Ce7R5epUfZ7Uul1XdYHwjWJq/RNR VHDB+YVTetkIiYvqXmHj6bErSB0mEXL94iZqI1jr0LZpTnNrlPLLU9L5sdQ1JRWjmIwM0wExOe+l lu0Oeq9q0dd5AfgHg3Us1S6s6kuVYrl1jFL8upFMEZjeY+9/BCeUKpaiqSlct/0zlShRLoq6iBUm B2CALx8lCtl45YdZVyXKwrqlnmuIU1Xc4yeTpRUGhx2yVtRnIvg390Gv3/n8lmSLoZ1KUKFohJkn Mjid81zcQEfF41auVv9++r8X+0+3OSYmTe3QaJ/7XdhPWhid+PPWqmlWFN5Q5Yju0jr3ZYN3cr5m VUkpJuI5ISx6yl+FXimZRdGJz4vjMrYhvRKeGS1kbnUyVecb3dnW1+2AAw9un4eihxezAt45mBWP 2NrTXjQdRwJ/kX50FlhwPZ9QHqqeVwwL+gMUO5a5GafcbFIFkVjTkq0zH0g/RBsFQdz2Z73R/5F6 invbbWU1Y5RgQeJTOB9D1f67syUWwDtld5xuQYD5DdSM/kdJyreC+x1aE75RWH3YS0y/Fm6yqghr AZoWIRiSs84lukirum9K+RctMvcSvBjVn5RG6UbOi7ht/6YnDdIKQ9vLUD6os20PQtYhQLmgyP64 hW/oPGkCodJ0joGN934rYc7OauhGYKW3ZyJHUVuY3pJhPJkzF00RjE/EJDxZYCzjW9HrGDYc+Gta fhaXzsjjMruzbyTyeml88sXYEHfrMSQGNbC3pp/8s5l24BCzkXzR4MClBDtxwj1rgUb8SurknoR8 6xhm8lXZa7cRP8wFHbV9dGkg49GLzVCYk6LEvGABZrNB/BBgeI5HTzNjK9tgcau6a56EjCjB4MRl atBWE1vLAlF6xVFR9ddPfyVoRDJHHQRgCkRSyhlUoDJN7McqF2Ufa85UZAMA9KtsGiRuZWIUMUO8 XVjYmuHlELkdcx5mM2NVZ/ayanxTRmvK9rsyCIdZvi26pB/0swNkX14PQPYRYlwYb6ziXdZYGFiG bNVwy8G/KKaGAYEbMfRSjsQROYjel0O411Zw3aiGSKEztYeur4mEyn2P9ZbQkzSo40UzrDJu6jQK 1ySmfh1xM7BmpnwH0Vv00iqtE5mXkQgjy4zMbDtwKjlnskg9knx2pJNVJjQ1G5SqARUvG8NpY53M HMw4E+Tmmd14AlczAvfbilkn9u+AlXQpu+wAH8SFETZnVYw/LDNIv+dl0hp+L7gqZjPYIpxCV/48 FIX5aiZx2GcFhFD2m++0lFekh6ehLApyfu3aGF1e/czFYI2wzHXbMUgsZ0bRBW2jYBnO61rlRpcd wENXos4HgjwOGnhX24vw/7GEWpUao/ekos5KrVArpDJoh/UgYCBMdmLuI+Cy7XAO36RQPa7bR+GB WPf5F09I2dt9PxWxCSYrKtUYKMA1r0R/pbsFsWoMf0IP+OgsWEZbJJyriuBRlAbg/a/4xGdvNER1 z0JLBOZeAhVL6IHoyfN/Sm9/L+eeJud23ro19ShcsGtVf6Wg/61RBEFEtU+o0CePV2MlpB254z2G JpRtJDeMSfVhqxoYsIFtnTK34fTmEKjF7kUb7Lx+eAmmxNctKw7WUvl/U0uzeMwVVh8fL4EH1VN8 0O1M79uLFprNbtkFdZIooy9QmEeqUtjdoqLNdvlBTQzRhkTRXLZ+sV90Twh53eHsJsL3YVSH6PjC 9PIyZfHsoJh3n9sPhxAnw1cvUFNThhQMcQ7Nm/b1a4lKgX0iJtCEc6QAEU8h7dVO58ekGhC0i6jn 8doTIGkiggBry7VepQ6MLx5MBWpsbTWd4DBUAMlZvdyGJOsqSdpiCjNtcgbCeSf92CO+3RrrUVh9 Z2Avhq5ydhavIa+37rWTDogw3M3fcoYZv8lIqJ8uXKz4DfxC4pJ/ddpkPYtor3BX3GUq0gkN9Bpg uXI1TGy5XgG8rY6u0HrJiJ8Ni8f2qVc= `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 12608) `protect data_block XBRNufbYAgpCrjGiLzjSn3qZB9K7K8KVZDdjW/YXrmm1iB2BWmUw/4Oy3BzBUilWNMDznYPLRkaw oEr6tmVy1YkC6gsIB9hnBgX+QWJcaDqpYqzlJJZl7tP7BfJ+8/g85/10/4mvdIJ91EJwSY910quY ONiF92uPkbtsKvTeo+CptGVM+MO3Muj2rFFt4inhrM6dx/svNhAlIajJwAmce983X6Y9GJWUeMZF 44j4ex1j1rcIQhVk2B+dJeiWGeZH0lglW7alrRohATJw5hzGwjJhE7sQ9iXRcVsS8Lonrv22kFW5 KWfYsdTuXQseKiGgXaBWGv+C3c9qcUiYWAU3y5g1UpkF9nF4Wet32sKxrBR2PZXzWDIvJY/9+Dsp d2fKcduDcybSxqOavrdbsv1fPfpvun4fGqMzuePAk74iDBjxD1u9V2bSPYPrVm/ciDyOR2eNS5yk oqY6jroFWdlrWfBHuj0gVRrZyrsHnngOijqc3f5Wx+muvzpYlXuU4XH5izX3x3knewS422fhZJIb kijwstBX39pO2j8AsI4UIp1QfSo1miwNUFPgkn07it+M2/f9cuuQyLrnRs4igyki4Mrcw70vune4 0pjR0F8ZQ+EWATBtMCxWv3PUi0qssVZV9+rR4lvWj+34VtahpdsCpELnsy5BtNWK9ilz/oRLsWWx eIoa722J0p3d/+ok7iaSWEL3QWbTHPTJOiJXNe2sbJj9bBlgKhHwZbpwFUxkAecVDLyRlU7rGzAY gqv42wbf+WNqMjh/Ab0jnZrGNt3EqeyX3sDYe5QnEPpnvjrOcjEK7mbDDt1Cd7OPWtfdwaSH2gYL P7vsQ4Sylfqn8pFmXltbfUIZ2B7ak4Q/tHi+vxWjrNLT/aoiZBpR+y31Cm4YyAUTTBBUL97fxtuH JgUXYUkcZHkXL1KpAGfU+kEk5sGW+RmU6gRYxR+Csp9UaWNzpP8O/N91j8VgXKPnTolLEbJ2EI8E neXLm2JAXvqwebnURINR3c3RJJ1epxChhcW4+WH6b7qhUAevXI7Wg6u2N0RQAlIvVam/exbnoukr 0NSWjslZ88K4IuxDyB9MWZ/6rfJLPFHOvYh0bPXLYzN+yzlmxSXVg47SLeyPNXHJsdBvW4mE7FFZ SxNoNKRf0cczKydgxwZwxB2gsqv9/QK3tDNt6yw/ohEGbPmeT8EFRfiaAdb2cVBqgo+qSogVmgH1 6JtJDFnqnnf/0rpsRzZXAlQ1Pne+6Xt5G806BV7Xx1TOLG8WArqEq0XJzJgOsjUiNaBtWKCyf7iQ IgtJYQL8PfmQ6ge2Ez/cCDg/r9kc/fp24EamVxmGId/9TT32xAjX+RykGNBpNg2oQcMpUaK0ZsB6 PfqbVTQ9p1dc04IypIDrzZV8FWa78sMfZoXcjFHS/MC66d7LOi6+m5COHkI8Q83bvjX7cB2ib4wN IO+hdPKjcqbV0UBAjuyFBCpQbdRjJf8keknUOBSmW0kPB+oU4DKbKwGnV+jJFdd4tLD4Oq+2lhuN YqCb2zVQZrs6nDPp95R47NfOR5Ar2jnXP6hGSrfmQG70VS+IEbVcv5lz7zwagSzhVXfzatxKr07K q85aaIrOjHd4pjbvJC30Ftqkw+phEhJODEojy621ifeeaDFeiwp+psiUURnoATefqQM7b6k4k6V1 MXnvSQS68tZSwtV3jCclNul0iAHVUCiZgCpVj2iB9uH73OVgtMAa9NgSJk17AML+uUwcERe2vflZ SetjpyvowuWTUe6aNG0GpX52nqMA4WYEOc+GZuClmWCqcVh/BZ9+dMy43iiULxPZNJK7GNiBkJe5 XQGdHK4cUkirMCi3ynkOzCDy3ZUmNQaAWto6i+PKMyPzwlnZ9CAGA3NacRj61VgGDT90Mdn/a0lC D2zMOrD083IEMW3NokdddA4LahOjpbEK8eDLLNtbaH4nQ40yGMMTkvx9jzoKoYObkHRf2JZ8Adh/ 2q42Lo1xtLu00oWDoWJIXW1CmgT5M1SX1vQ3rMAWVPWG2VyTn3DvTZuFLObZnZnPchFj3fuYPCCj IDbSlql3fGG4Dy8xCDN3rvc72DQouRtqY5+cu8TENZYv3mh99MWnio34QFTVIRfN55Tbz2ieDe23 xAlJHtCoxsHEjb7aH0ywX+44IWmlCgWRjbY/60cLzuFPckGH7FHA8M9CBvERMewZCfK2pS0EJ6Gj 8FGneb91BQb8cOggrVFddCewzqhVOE7CXTsaRsfBhNpHlvVPnL4rmdSWp1p3seUBvh9zAmd/2iXz Go4XgrMefmuYifZSkfQAO7TkZmyub7GhoKVWrosha0SQ77+I0AIqD54X75063vpWFTOXjAvPEa/9 WwsZESe5Peb8TFy2v43uGN8gDWAQKa56zwXckynSKSXFn8yYuzlWMyDVHCp1MLrg17bj4rZoDRuO mLukemjOSS28XLHUv8OzMbcy8j5tbjsHs6sp4mwaA5hH8o3iYwWQ3HHwr7qwpOQT6d/m921LUASz 8C5Uxf4zB7ajYcZhwgqYemaa7b159CvMRisqggtw6f+4REpTaNnmei3456M8iQI728MePyY+FURx 9klwacBIhMULNka8HagIBcb0wxeXAQV06BKs8/yU53Tn30KbPlTMQ0MFBAFuGmCI0xDZEwZ3jYLh IWgcCojP9rYtGSI7jQMH5aINVoUE00IVdyd7v/2DJ0UI9fyTll2mZp0wvfzgZ70qvScRXSmvYIJm eeadqr5zZxRvNfZWaLCGuW+QM1dLHYX3FGQENKse1i/8f90dug6Sc6L8x65+ojB/pYGpTqjOxkxF rUYNFtO86peh3yo/3kOpAc953asSV4hOZQwo37xz4OWZrgKwom+9wUkWNhIG9nhBQoX4Pwou/CRk lqHTu0NglIhitZ4pWy7qO60HOaoprsUm/3qtmF0Tk5xvD4XTTvw0ilH1vq0j20Hx0Z4/X+es84Ga uET348O6hoFFAaMHD3tcqJG6PybjnoRlkpZPFYfukWUpgU3J8SdESsSc1ZAaqxG2JSJ/5OqnV1BD 0rU0cJm4P3bPH554Ki1DijDtJYZnvYIyViVL1DezG68/cniN32N0v1bYn8MwmJNbxcoloiQb09sb JMWTamKt0LhrFdpXDyALJyFdnQaAjKO5VwmlpjYUVSzdA4bS95/uar+aDfMXHXRchR0jM+PX6obn YyaTpJrd8qGBn0wiDOt084ELnuCYVWUhiB5fgkAT9b+K+smFs38EcB6QY1fDLdaufL5ghMuUr8gs ATLzyc2SEjVDmrPoId6xhwKm2OezApUO1+wm1wgzjIbtMj3KDiFctcE0yNuz3fvmIc77lrz3KI3M 3IQyNn3+uJ8ew50fvYPTec2pxzjT1GtovV+VQhnXnLyBOWINtmLzAgxqcqd1nVhP1xTr0XBpV69G 9UJD2bVan+Nr9K0OHkoQGtxg4BxtWMbh+JCmVIl3tMNzQN9mX+SRaWPiRfC4oiadYiHk0K1kKiZq CoB2AijR1lGfOAe2OIB12tGvmPyZF63Fs2lQrsBoi0ItNAvHFHTJ4zpNhRzDPmiIo4dsJRrega41 td9pS/hwY8WrBneBuOPMPY9LCv6rGr5kc7xJRuhOZWOiJNWNGdWcWQm05QP/wpE1GtUfuWXsRIWN XImnhGgLnMlO54t2dogGxrsVBj097xlpMNQBYIEG9a5yECTIax/1H63zIzSU5SOUNmvU7EbW0skR 8NVuUlXkMtkuL92bZzSqr3KCnRHqyDAkJAgDGCQyEE6G/C36lP7y7JKS8oWrPAw5U4Ny8rx6xkXJ SNY1N0vxCAfLF2wCFdDlbb00Szbi8Asi9w4OOQXvq0ZA2LazGi5/PvBTTCS8ImNEZTNvbGAjm+G5 +ikZcx177HkT4+GwSAt1tC19eWpgHbbnqLfZFXw5NI7o4uxZ3GLAhUAWbUEcG6OIrt5J24BsTusF WZNNNnwBqXlEL8N1Pw2FBQfOQLQqICkqMXBr/FQbjWudTMis/4/jkjGYOvv7Z1VJdGmgtiUNCFEy FTWS/8zI4c/ON3JzNhB8Lj9rzHf2WF6hXyFpTBZUkOkD4LLaz3ziEpOi3k76c4JK/rT6X2Mc6nAH m4g85oDgg56hq4FQCydAcExfLVhkBqTiL3RRCVKPB8JuXUZOzv6wsMQZgNWqXontlPiX1VwbDTcu K53bymM37Nc2Oe4aIpAcRqUUpVckbDEcq4tmP93k48Am8PCKZN9e7TNmHM5xCGo1q969Qd5JpN6/ SCFkhwbaexd3abPHiykoJ+BkQdvoqDM4PmpQxNG8kNTTfFuTIybR+kpB6uxrBj0pr3InXXOPv4l6 Lzkjec0moNCv3mDBXsU6NjEnyIAZf8IOLrxzoqujsG5TpOcZWCjDbOk3XjFSc6dZykZtk9sqdZrA 8otNiAQZP+cFMS3NDEx1VVVQ1kXqgksam26wI2PjeR+X9kmBtd+pJkqkbQ9879dvCUZSnTRV8ok1 h90Zc/CRadecri0vMcd4eHatbtaa4gUemNdV7qImfL52bqACEmIS1uDGxlBz78G5hQ3P3sY2LG4L rzB9qumMSYZargwKk7fQsq9GZ02/JjzGwlanc/oMHOkL4LsZJ3hgJJKSLeZk8RYu+sbnX4m6CS+H vVwOmlwq4eE/MNdzrGXVi+RQ8W4wDUw3kaojfwU0E/bhAjKwOYMw2SWDJLUKYlpE2TazMUGSL5el GA9mByuzli/d0ab7AFErAjrsD8MKRCLJiYTXPl+sVJmY1i6bAoMBzqbPur1FBWs7aPP7aai+I81N P2XktltDCxVCkOBwUeM8Nce4TgPcpOZ3yMSOJB7hR7Br3IAfzad5y7CIuw0NHecdm+0C52Of+Zeo BESgWxLnkICgB91Pr3hlpiP1FZgv/69KWJyhnsxK4HTbQhUZIjkkqI234imeHglIh394aOzjCBSQ 1DgGkE8ep+dI6VQ8X64yyp8foEd8/uwkrBne7kc6llbQX4IktOAGzAGDt7Kah6F7dtWNsPHPIBon HWKwl+bEvLW1UC9rytTEo9gCdDy/W7hWLconk3l8mRMhNP2fCmGtcB127npQUfSZ5Q6ErDUYHCGC 481qMeNmnp0cLf+rQsPA2lhfjz43SiR4zp2aQDbO2XpqXq7SBWebJGb0Z0p+FR2kv0uXwSreOcHP zjc4mFaQN5YEdZTUfr7ytt0WZalMQmGcKoL40enSpAP01Lw2LyDAfTWoydHyf5KMAa1qFSM2AEV1 /Xt8/BxjML0PK1LFnaOPToZGRnxOXh6Bxfb9bOnWEJ6aCuCzH87giU5vNq1vzCJ4DHM0rV+vgKS0 bLV9sXwAdUoNoa+mDb14+LGV3l8mAg+MImWSwFL6odmTx4iis9OakwDa7j9anyZDLbAS17nfj78O ZNsqzeGPXnpp2Wey9ge/fcritKQrOL/CPnwHBPksvZxo2jKXhgRXRRDpWihct5uCoqIcx1NxhmV+ WT/PUsJOjLyubf5lB030WkdYGGO92wtpF3KibDWbzBTh4DR/5EMiPZHZzrFFArcYBWfjTS0ftU0V z3hHv3hmzupuKhb0RuOx36mxyfLN8Q0FMUD3loi86rx1MVLUDrQsNEC+Wa6h5nzqwWVyWHDGrLAP 989DmtqHY5BmV4SWQqSlwqZgkNr5E5ClbHVGooBlfdKZTPFfpUZXpKVMGoTC71YU7mTE2Wbtf+vB dBcvQY6i0Em//xWwJxqkQDOeDD23X/kJmmQ0nNHKz0oMjsnw2/9llgAhPudUksbRqplFprkZDQUq ytrPa/1SfJN3+daEh4xmZhuGt+lRdliRk4uxPLq3FZDQnfHfMUI9orQBW1Tz9sKLh5IkF3waRfpO 3z7a7KRUOhmLZAp6epBNfX0mo5kfDJl5VvzA5AYNbFeywnkWSDg5TD5f1acMD9h/fGMt8Rrj+5gn yTxYdhTKV+EXqKiEI2Kv4r0sXvtQkRYg7Kr8ypwXqgY46BwoXVSff8DdgeYEKsBFbKhl6mGTLle1 NF4LDdasUNdjtyfpMzRZpQb6FhYxAdUZ8RLACrdMLOsXFsTe8ye5raG8CNCfLezQveWrLk8AOfmk WIQW47rxG8oid9TLUGC4ea2aFx0i9vodtOUag9skLdUdQLpIG/oyz2Ev8PXCcgtl5ppRRhMR4Ewj h9KIa/rqlo6vNvZ5QsQr79QpOKelNku+/S4+ZjWGT4etZEMYzEpLxSmv/1wmvzKjdW6AsYjHsh5y DUd23gAIZfEfpAucUpBSRd7t4U5qE5Hz90XPYd5ubDEKlmZcoaxR21+obCA1fCRWQ84Q2t5YnNbT N6AWa/gOnRnP8LnTH8WGGqAZ5GzBgcc6JYsYSDAK9Qlwh86BKFFBgv70touS7E0SDbvl7w/iR0Ns VjOnsxIkx+QqivC4moDJR6X2BFlJM3HzxSeNH+JAnkmBYlA0kkJuREFUBeoiEunNypyU2ZpPHg9W Skbvh8rgHDCuixCtmh7FXQaCFuBBih6Rwi00qGjNOJ7nSDKvIv4HiJvR6tLmNX+QK3d5/m30KdBW hqAbxWQa/0tjtdryT5kI8pCvhkeS74r74DusHTQWf6TZ5GNWniJxRREJ8tdxpEMwyVdYOsw8Zz+4 e6I0UI/BxhRoGT22HnCjEJWTl17B7qsVkpQHCKfinRYh2GH44ID0AlwciYHrbshAOtUntx6MC8a7 +hVqFfJyv3RP+X9c0o5gOY20iCEevEIC2bBkGhW3YPZTWM1gUMqPBciOnjbsJmPqrxCgngmfvtfQ BvQKVnhqMNzSKu89KczTyytyK4yCnG6lvAcIQckgiitJQt502bFqJ1z4kwKskp2gL1J8U/5r5vuH 5CZqS3OkivbEJb5yBPgh1dOuLARCWlw6JVRvU7EKB/6+ChgxBdm/TV6xIO64m40U0ITvJ4kxNLhB HsV1Y1qoze4nwiy09QrbLHBTwe8Zgwp/TC4vFKrXPA3zzYSM3xEXei3xKDuvFhXyBUVxcZrQY1ql fM/wGuAzu33Xca3T7aPprHfpNzJgI+LUrGVOIlxpnzWoMxS6Z3BAYkxaiBklTJDFpgdvB/vTt8X6 k4fdZrT1EsRx0W+zRKYooxybv55fRL/ugGRjKt0VXIgLZclX+AltA8Hw97HecX6FjimtwBXqM5nq Gmd/DwUwb3jn0HaiQDzu6bKhXBmKdS6gwtatxwMAVn2RlgXSQICyWEFZmEjeouloy41qO3H10mEp lt24eUxCyguA8g5TQLiH4ZMr8NYCUD24Knjm4yz2VUdD20tm1ogieHc2poH1qt35knY+SPamR7D8 wgjs/jG6z+CkoG0cCbjTVKBUUlCcXs4I15Wp1mb7NVYSFAlhb+WusEjDO09rndH5w1ITqsacRkvV +X3RlnMUEG13aFUzFHXiUIFUCMkasHGTxrxdqBHoC0IQGVk0spfJAJpJ8f8cCBfWE88BdtewAI1c dNfzJrqFS5t3Lx/cH502S8EBeYSft7xVlLs4Pj9GhyBlnzRN6RXo90zTfBA1NFaP98jiPiXfcmXL 9wgFVL108t8lh/qmaQNrhF45wgr5SK/2l053aZDhGAXwZxE8AVw+MQRzBuUDvc/NNC2BdF5X6nwG 8tXGmCe0C5IPBH4pc8dVP9s6rb6WytNQGQXQUAfRWimTMWyeoZp0nm7vaLY5lOi7GQzEVSX1z/Q4 tq5mwrkTPRxybAXSQ/3Pl5NCXsCCp69rbPd+sLCIAgfn3sybblWp7OCEWUxdtkcXBdAy9JakR5Jc oX3OYT57DeHfN8bvW1BcIyAiVhDuMi0lMsZeZfsLXurECPQk05lKHR8I05KYbOMrad6QB23WtX3g c6LMB3a+RJeJn8sTlO9yOX+qIXnTObrlrsc4CZvmJC1+CtADuoGZNvbeKsrqekkyzg6RYZKUbdR3 Tj/+CViAjQMkyWnlJG71o8lJyt/aAz2cwXdXU9m1INjqCpKf/rWSpyUNxRu4NXWa4FvFx1ixBQZF B0FUDd0ACFTTpQPQqIBAmphlIkWCJjOaZbJUZvUcqcHQrzoFdv5RlIUff4Fg7PR6ZIQWczHWFB8n P7LwGR0bT7aRLFmtCzEo9doeEFtBP2WwUAnHJPpMbBYH+KagXGkhjIzrnfKj4Qo8NGPSXQwxqZkb eJ3n/lq+iS/nHve6Rh2QhEUcJXMp1AeJlyi+81R9JV9nf5SDMq21zlUdn3qMqGDz1HqVUk186uhq iDt/wkM7zNKUOwEYjQjTRc03WyfAFiL+NlL1LlyLGl04gvumN0Z+sfsD94pyTqSMRBM6yzhjRCa5 oyXr+Mm6OsiZ/LPVkZsKqYmYKbJUHTPLsHnK76oCnrNs2vYMxAxeOj5ls/ZLkurYC1GpvQ2SD17Q k/Yre5AnB7obUzaGhi1ugGhREJTB301bPanugeWv6/WWY5lswXmoRhmUCKuMLkG7+a/te0Nz5eMC nAtEEav8kvOkS8oLbBK2QTjKBCS2xutMbV7pnXhf4Oxn3kujBMF4K9N/ixhZ/CJYDw6M+TqYuLRx 8K6xwlI4Ein1oODwN2eM4D67YLkV6hZVdACUsP83s2o8RM4lCPAzUHay45V2IShNyF8ku0oxCAOk t8rQFKLYvAh7+CoQ/XSfCfO9FsFjQc3X6u/50fnwhB473+550WuYymwswocyj6fOcoXD1fMBjkzS stmlko3T4lvNS4xlQlKJg+jMb72+IA0C/k8kSKNZPU7Y/5DP4ErVMn6Zgvm2ixCJt2FAHsujuZQX G5Mtpu4qRdY6lhliVXDSN22rDGdV+/faCUlMzfksMepyxi6ckgnVcnvJLdnKMdDMj18y3Tud1lIf P+zBE3rWq26hx+7BVimgVgIVFq4fbp/upW9H8SjGV5WAVcE4HVt43r4NK9UGFVBUETpgHTNLj6lZ Jn5iWccsi1lgID4oubVQqcKJJYLEhecDIjOJtL6eeJvmwkSTjN9DeY+E+MizzOtCN9wmfNPyP2NQ GFL0yOVqBjq6r1gM+HnKkyvUMBY0M1X2UGcAHRdfAoSI8qG1Nf4a9oW64tLqnt1gFW/jhQyuERGc w2lKpIUYW++Efz4uD3kegpT3+4HM/M6TbDj2OOhTntKpjcZ/041FLNVCNWsDzPKuUkrki189LRo1 kJBPweHEdpobXOfbxb3GvXExdp76nfNZizrXMF8sVGOqaEM9EYMpNZLIGtVZGtcTFpxQjPXrgSxy XpatC7po4JzS2k/MLG7uArFbTnxGxQH67yGVfHTviOUqaUDbByiZ1DS49Fj/O6IBYeILaJpT6iux NEd944t5ZiF/9NlYS2mmkG0GdjcpxuoW3OxGjwlAdNAaC2sR7lYA6D+kMabqvkHtw7VdIN7CtW1F hAVjENprIW1pnriQhqgtgpOvkS8DFx6bB23nSB2nz9Y9uEJxdw4ETht9dLjXZTFfEntaCGy5v7fm d8Puqi/HFfbSQkSmypxR4x3UvQqDZzu49L8EgRdD+SSn8/4iAexvFKV8uuadB5rDJBkKTb6Etbvr tKvToma5l8yryBircRJdcYw0d8L1ebw+JGgSmApVS/hL4Eh6J71GcaTrv75B8rCfBDO4kn6081AH VudRX/r8mz1TmGR5iwtY6DpzVvZfOQrm6etJIWWLcgL3nTCOSLba5ojUQqAj4tdywt++GSbh3SU/ AR49jUf80ZTN8PA0ySmFeM7UZPNtXJDFsVn0dDgH7aJZKSWgM+fzAH2qOsBuw8urhDebX03kbShN wmC7Pic3MbKU26e9kBgSQPUbmanrCpQf60jzSVP6pP06I489ngDQ12LFZaRMoy8gEmJtE/njTBmS bwBoY14NnttscfQOZRQcvoKX9Og10XwR8Mu3Iq7oB3rlQ+OEkIqHvVKVBKLdvNBFCWN+NUvW1J4Q KARGN9XUREcXrY6sT8Aqq+TNJMfvRbilHybHBkHXU/c+CEpsIdWmx0r5/mJs4QBH6IR/LU/mcHp6 BVJRtq8+/7ZLkizhUEE0zscYRI8qkXZzKyfKBVuZe+jxelGriLOHoR5/XsNS0wh4C8UF09Qs43+N 4paDESDmiGrIj004GosHtUWjXkhHSmtngQZrlaq0Q92PQDyJavUWgte+lmuT5YRqNkxadtEZoAm7 I49DMUeXNUPd7B47zFsJk3rrebrnLVDwW2cHcwIqW9Hkglkb+fX+j/XGOCwjEzTCOzHV02rZFYoI e09rdC4yDupXW0/LdfevCvHXcWhOCCwtY8IZ3ia9XN9r09b/EAGEC9N7RuOICGg1ZaHtqHgH9pzr X/KCXDrPY2NsaEZgXyqcFOxWHF1+W9MDn4UMW7mZ4PfNHQyjujndgrH6sxxVugVEPoEr+miPLqqh mJxLCEHhcUUlL4kN2pswE7Y1q68hd8QEygbNJ7abfkOP9nmAHkPGkGkFzaBWBuk6/JEtQu63k+s3 27BaiAeoBJdv79cpvHnp83xOCgp+c9bYxAKVqsHf6pbFJng1OCPXC5CUvbFM8Tkjnu3ytesX7nAX nCqSiCGCGl76JtYj6QgzdIMPAla5hOafiLPJ5BmMS8jlN3UAzDvr1e4hjiOoy4sxulhIoYQ+d1Fa 2D6FNxHULI4kznKOK1kUZJMJPRNlG9kvEA0v+l3/gVnVIQvybIIBYjrwocROW7yokEFjScE9kcsE q/GPXYhxG/Y0EQ2EHFNclX/gLGycELbmYrTPsnAVe4eKdbpkGrudkxENu4OZeCELpf7RUuf7o1lT DO0cKjDcQyPWk79jy5IztOCMu4marGwR1IEioQb9561TKJjKf6Ee8kKx+VGjaAMu+dDqqNTtvion 9XxR3TEoixY5hxh3OLDGHG4aXL1dhzsc7msATaZNyOHj+XlAfIXuSmhU8HYGLkjL2YFgyqTCHivf fnsWKbdYbwuIlv6xnsmpVjjSWKFjsCjcXJEtEEKt/EZKsZ0TM9WbhzlPjjpKHWpLD39Xv7/lS+RT TDapugWN7gYo9xj1D8CgmAFEX4KzptxAniBMk3Vr5/8vVypQAnEe/tbwFlNkHbccaL7Te6LaavfW KgZMd3tdJUf6hFUBLPwVOpeDEYMFfpviQZc7XnYMNEJUVSWLkBHxOOynLgt9b7AzAhE9h6+KWbLn QkZ7Xxvy3bWDLiz4QXlt8slmdJo3bUpvypUwfhMS4/OeMGptFZ9AtIXYStB+El2dc2DFDEKJSQYl I8ayLkSQHymCzaPeebzOev0p0V70kuMbTkJv3mT9LlIgVzUSp5VKxsle+SHYqGj2UiAJxV9uaajF 0RhSQSJXJTuctKZEFSHKtwp/m5DOjXQtGwMxqn5UZRG9dQHWSO6+dgZHA7F9cNfHI9+4q2LLJJWH C45htygk4Aqms9ypMGp/fW5pmOmXJfpVmXPSCwCnQeRHinMAj3UYUfEPTN0u5OsBlPVhXoySsI74 5QPUcSJ+l2u6S7q87LQdgCFZcI7Rx+34VHd7BE4gJe4GD7ARuL8Cy2qhsFqiwAN83U8EVVnnm7Cd FDXsZeGVMhzJLBjp6Uw6tZHGdcVJUW/1Y/3vTezDQFZmCTNRQ1KTNZnKdyCcSUpzN7Rr3jcu4Aav ow863KuCiR0LDNxklvNL03XmUDPPBudnytGfVBsXRGHFSdLvCTGdho4S/CZZAamni+RlP7383e66 npmdVTx1oF8ZbFtbdU/IsoowJAF5yYthOIqtScpqoWYtmSFEsd3OkaL/WMaurOibzPzcKuuZC5vY XHE1mXXQ0nw2UjetsfKZtXDhayN5j1O+ejLDc9elX3AlYXaNHoZIV1iCO1uKj6eDelMZUUF1kkBb TACOik+FXK6K2Fexn8GCEYzLC79xpAsw+ody3SLvcucq2IbfcnlL85eTFVqf5TgGzsmdED44Ivlp NzkNWH6QZaR877jnqRRMQTeC4+/uvY2f3DAt1/IM8K6tiLL3YhNqS1MYs8U38oXjDp494G31PgLI 22rUEhWyHPMpLgGJSnWrLFQylgacqYZGFbgjBvdOsq33hzegW3Tw7F/A39NtKjTRiBqgxWo9mMV3 L+S+Fwuc5zM8gru4XfmU1Gg355WlGSILMi3u59sQDKxYUs9bTiazWxAZ02Mh0v/VZSGhSaF0dZXm EAOPtnxDHYO+li4QCLoh1arrXChUW0deF7xi++Il5MIAYVZzMv+EA2kyCrc2/jEagE3dZodSkphJ OyaHOXRAQsLt4ge+VDSodIHakp9cpdiUu/k9WjU2PVkII5V/0akWNMKE66lEKW80qs7FcqZ+C/z1 h2HzVnTfJiK0OTXCeywZRMCmjG2JFeGBnBfO0KDBchyMv44hjtu0n9Tnd49vyrB4nRVJygfLIfX+ VNvCKugR1haK7VHG7YP6pcVWSrjkqUrpFrI2LAhjeRnhWKuNFQnZKUzHGFYICls83txpZvJfQO70 EaM8r5IJJLRD1Xv9ThOyjH0BYJkVwFSallHTnHOES34I541YlM8a2JkFPsgrgPdsQ/oCm/V4ATxY bWuIMCgorozdncw9DpzjrmQ1IS8fzLzV9Jy8CUIKKAsLT1Q7Wr9pRgft6cPyM/18mPlGrZkXrgv6 zllzg75KOIWUqPg5wm4myYU+eDFPS7mquZ57mp3LYqUxuE+hTHXFbGdF0PEB9U0OfiRCROubcTAi QIKx9UgaS2/3CNoqlw9a/2XkkJVu13c/jiUhUCkZ/a2/+62F/YkpUHzs1+hMKknoatBidrNPYn+A aZWiPmAp4uNh2f/pXAUNvhvOn2XuPBJjPsfiKcQwgOoJnEY3MLXUA3vXTSP2dBzWv2EvT9b6+jcv eyh4BkdUksxi6jRGnpn2pFXeFHsvQbgGW3hbDaC2OjDHR8hG7BNJDlcEvn5i2toDdPGYDxE0K4Qe kNWzFOzsaobo18SLcp69JnVuWJNXJbpjAyf6PDtfBOeZ3f1X0zTHBbqAufVC2iHLYWx7e21WEAMp jga+uSdEPH93kgQ1VUa2uAFTjv/qDdH+rPq5zu+PwPSqmtrwMuuQ9XAcN660GR8vzoTwnsanuHHs sS1uy5E+7Bx82/9T7YYG19KDsyCOfBpirwXXVY7hPC+shhOVHYCRvwT3qFn1Lp52lNkXz/ZX0nd6 4cnHSxLDtuzB/LVIVc2y2/KAAN1SbUUuwovmBV2DzP6Hgi0p9MhDkS/60YnPYpGiQEmnVBJER9Dw csrVEdShEgdHgnPEwuBPyrLYhOjhqXcJxnXvJJoNhq6GKs3zJdYBHkV1eeONgY3S6brDsps9hHz5 WOYJcIqOoYabRBVGkiSLUFk2QxMvulPqq0MLzsBSV/0KZFvDn0fo4NKck/CMhFCr3SaRVwAnyzIA IWOjM4omaCXFNymHxHoS/MKePdxOXWApNPd/7Qq0I58Ax62yHxiV2n/dt2+QjYi5nV6YB/C/tbb2 wIbNHesCaSpCkOl9fNoMz4n4m7uL1v0URcBXgR0RI3W/eXSSqtS45OXIQHUmBsA8rRnPsQVkbnfc cGdTGoWWqy7rBMHr6AB5jnbKqTNrmLnDBPgWeWzGFO3kua30X6ZGDW6zkB00oMOh3wvAsJFoapow y9Z+SKUosQhnSBDdxK4fiHKcLI9eordHfNNuC6d6bZkQtK8orSY/67+cYZJnXPeEzyTt5AVcz1wI vMbITBMWAhXbFe2opKcwBs81Y0L2pHrs+8l/51Cndtu8CR+3ajyS7sGPVaUh0fjfOt2KLgPT3vyd 6CAwNK4W7Z6R1ZXCCbVbDPOVNscVWzjcOty3A5/XXOH2vt3wsgvIDjSrPN8N+ZpLJWWdGWc2Dd8q AWVXP4IkgK3rcvuUq2BOElU2B1rxPkYEOrRQ0QyjqX90v1TL8sxVXOyuy5QxTTlvzmBIoWvNf7uM a7BOXGdVcEL2uZQ3OJheih91zgIwcvDSI2VPmqP71AYyU4HBNJngdDVJA8+CsT7OVaD8UNrrXd2Q fkpTJKY6D8+NOPDBXTR1XdoChz/XMEldrqtRiYssHQN2MkVpVXd3q2HZswo3KNfiney200/QSyj7 vjK5rcAuRTGwtyOPpu9BgI8o+FdtKobyqQSQoD99Y4nT8xtp6WNio3rvJ4jMyWwzWONnhYyC4Djo 8JP0+5qFpM/1KHFU1iatMYK+85GMc9i2eFmSk269OPW5S1p++wNdeEQuWTDbVfDmBtTEDUd3AUKk ogkuXKNA8Bax2ycNPuhK58zbfuwH1Goo9bNgD96CBPgPyNChqJmTLf6pI1M42Mbvt7tVRfBuRsLb A6M9YUZQvmAG/7gzIF+DmL7wIUy1fMZMcpGrkmjK0XUweyRSzjt4/c89CbAthrXE/8v++MMCK37W z3KTIM3mzpidVZyAThhDykBmIMvd/U1aKNx9K0T/m9SMEPTe4oMoCRUo/RwlrFQf/jNnaMxXKr4B t2o+S1XaRX3yfxzYq+LR0mQ9w04jMhjJqVGtKc0faqDdNHw7o68gB7CYt7giS4G77CoQcRwj1KUN h1qj+ad4FQOwyfs70KAphdRUyQrgyuak+BlUm1txnMU6xeSWE9uV1zvYZjwV20NSu/IT3VdIK4p7 RWC+lkXZE4E9nst0REPFADax9KtCSEzJi2rAgKcHOWDN0FhagZ396D0X6Kup9J1GJtsO1WE2DV0e BpLFr+zSxLBOWTy8rw7sTuWnzHAF+JMPR01qNOIlQ9ttRFbhq5uvjo1Vd4JEB04TqTBlUt14ozum 2DVooAnyxvtdkdRKmgxVBtY+Sr8YciCStC69NzTkGuURAffVVT/Wfpo9vLomO7UjDmc9TEXoklEY ayR+dF44/VZcqsS2eUzvE4/C/gSlVWifDEKOE/lRvOXJykkCxdDL4y6v30zdXep5oOXesAr/RvrM xElAJLayeuvDNWMTGDVr8EnZhl+rj7QK3KX/Iv0wW+2GKzoVIUEo7jAM/M9kl32zSNWvHuwXtsQr vwPRqXga8FcZVlBughr6jRWnVKiYOtsoBOGcnV+gs/hnHeynPwFSkBhEvXj82LQdTSy8qvrTvErr HCoMYR/Ll95DbEPbk5bZNBTV2W0dEu8SF48+zifyUV/0z5oX1DvGYXB9OpUWWgo8j8zuaZgFrpAB cUBGEf9s6LwH9HCylUUjh7BjMjRjOl4EYzTzp1uJ87FJ8L2laulm4r6eAa+NrJYzw3Ehhu+wX9Mc hUCyhJhZt1EYwysibLycNxg7UbucWgac6gaCOL5+Nm5pcyTn9v08gbQxarp7hDznyY4U858az1Ej SoHAkP6NSdWbhDvgirL7NDlbbiGkbHga2aHeZYUm2S22/EMkIIQqhiAaPNX5QgBRcK0yqFDv4LI8 V3Z150ZCXyzAzUji5WRGI3VuGjS7bNTf3ff/lcTUsFy92zfK6++9TI1FFffD1TfzwMah/Xl34Vxd XEGT4u5PBmBTQngAGylsYXgb0rshElADT7XMVFo65kIt2yn7L/BeizXdnxfWH7HbYpS5QdeIrFJx NDPSaHrSVKK37TlulRndsdSjwo0/6BU+G4MjFPx9RRMRGUhRXvSjriP4H2ZLgUApmeBpBI7IzaxO 8U2Gt+C4IZrlOwrWJ0mw7clPAJ4To2533ndbOic/dly2bWxsdvcws89Oho5YFcaBMKULRH+/nL1c 8FCnIQGXeJr8Smf4dykaiyvolMX159ZLqqtZuYG3w9WONT8SVjVHQxBDxhPJtiMycBqwxvVbLzX/ IGVsET6dn6dCMlrR62R2jTe33jXiSLdi01UTdNUWcMelJSB6chsPNVnIYLL0hOH0RN3vVdoj3Kab R+O1Ei8xXBlC/tJo+Ma/ylxbO7zFyb6jRpwLurku2PN8Ff/ziMcJof29I1IfDixLmgC/IzCzwVB5 lLwLClob/1YbCASQnnWf2yP4pJmYQHXxh7fwIddhVqGDAtHwtsZ+NFoI6BvH6I8iw92ElG2S8M/F tm57827y+J4VXTYX8k/Xwj2AsA7wJlmTY+pY3JOPtB7DzWqurYKC5TVW+KA2/5lEQbWXOG9fhLPC lyD3etlC93vv/6sBjwXzb0Nf2hJD7hEAVwO7Olzzt3vGZ6JetczfSTsGI4HQqX03T8J/FbrCIgJk auchMuMocFtX22LCClWrZ+Zl2GzqkJOFOdMFA/qjmLI1Lk2adZWQEC3ceaNNEtjIFT2Q25vVmxj9 ZCy1hYv9aTQMExEMqJZiJ83gch6g6gwuCSutoG9WtUmq+oCjU38mDO9PXvLiEukDztG+fZ0ERhTi gOwpawYZcbVySEej+jGbo8ZCl6/8+pIG8dgX7osx4E9M7JQhVPgrX6QedODFXSMcei8IFFl2pobj TLuG5H9LRmRFa3/Iq/ycNNZ8rm9cp57SB8lTE0CQSUaNdcxdPmI0CG4VpDE1ZDolmWR60jnOmdAw wCfAQLNqjliLpOod5sSEXlheqDY+LdHaa5etM0nTVWwiwdg14kDT8cRomcyJgrV86cZIN810NIm8 U7ZZAQIXsvFz0RUXN79d4Hv4NaBe58rhFHOfd7QYbhxEnSODwsGjP2Qn9C1gDpKLqJkrZtUtQqJc Ax3GqWVhSouARn3kNLVW6GRN7BXmxBvF28HU7eXGKDGZnRs+WZesOzVEApVx+5+h/SSvIqQJUo9x Q947FEeDsOcn9NfgsRcVIWhUyyfDvHF6uf/qXwgIq4ZamCwAzTkDBijHKkDfuiQU4jj3j99ndgnL PZBmlxa+kq3xSkmnHVKJPNVNjXVec/8dfb9mdKpuhGQQlo0bP8d0f9x7xsDFLhpHciyvDx+5jgto 4zPovLEwPkCgTDBamtTeIKSfS+rG5oQB2sdroaTEvQNbDWOHpYq9iX9axALTT/ONQ3LfzqK0sYAg NHVSqLoRRWtKVQE= `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 4992) `protect data_block X256/dZaB+mWsDOJBZUNoEpesdOh9yU8pts9LhNkboUg3+porPYcMfL4zuORiY5Imb+ftmM613oh AkArL6T8TiRJ+tJ6zDzjeSFIzEW8ej255st1KKwEQfc40URYVtyG71PxApdo5r9ToqIXH1Y70iNu CxWxrcZw9WpI6CV36uPw0aRuqpWmiYd0NuvwqIsb+y9n69Cts40TFghcQzwz6QSx8bIIY6QjeEXX FZ1F40vKZa651llX/Ezo9Y5hIGByf1Bkzhq9PrCkPsMOHms07T+rE+wmvkQpW97f1re64Cd1jQxR i9WJ2eAUmvSZKqOijZKDLNHTybEwpkWBILL4GM0zmS3HdUHJt5nn2N/RC+HIJEbtjF2Ayupsr44x HNrmwKqnsSlwQt8/sh+CqNj8ttgHzT2lcZLHzQ9MOG7mdlVamLWctqrRGrGJov/PDoEnL9S+lzTC vJnnQrLENe69kD5+cyp1up4Nd55tXgiqxuSSICIzPkbw/XDqY2kKCO4cgnQzjHvvZPOmN/cM9ZCS cHmmz7ba5UwZVI7CSpWO6xvk/eIRKLUqhEsxNKbNQCaysE3A8v9rCelFeTKjRShb2MjkAUD/dKUn +iv2+XJV6nQGZG0ShLIAE9y3wEnzK/LmadsLnUhSRyLdmxmkpRKvix9HBlr/IL/QF+SWGnBPREKU b9yUjEN1qtitrJt9UD2mSp3D+EpybchfERMUBxi/7IvgnFxsn5OmfvSkd2HlDuz1V5wUvjJS2LNg 4+T/ChKXnU4lOhc2u0eIpimQroDmRrMQ8XRzE84zktWLtdVpnE11sT1AKL3MPbpGqmPWwoDGM+Q9 nCXW4/eKHwymf+u0Wk97IXzWB5cdsEhjhJq20rXz0MZif26ke/oJpUHp9E8xE/ZorrmkVUBzIY2C KpYGKmF6Yw+XyzgQ7Fj+kH9jcj7Y9uf43FNaf+Qt7MC9Zskg6VVE3aXQz1BTWq+j4G5w9yLoMu6Z wWcqBsh7qNnqx2CCPs7O0f255GrhDp9m7sS5CAQgVt9jKX2Zaa4M3ZhVInznrC5hXYLVwxc+m2TA CMMiADFmfyhPLQANpzyv2yAZS0lfonPUwXqksAl3s9c9+fiiCNbnWqum2SbHb32x6OSgKcfN6jON xnF0HM/OFEbreIrJxhFuJ1KFYKv76wjqq+kqq1VCmC8hLoEIWsQM2AFp9xzeVUwHqBjdpkUEGgS1 kLH7ynja03B7eLfagW/GMpPKRp+TpOQ5GIN5myAnyGINoOxDReu6t86bDZyv5X4xaLS8deQeuzFz MXBMnRFaQ68vKCmL57qd4VPuXT+34rvKXHj+6UnNRXQsmkbtmxK28ZR+4rPw+GcLxQXuLMb9WhRg oYW9+VV36UarONSZz5Iu7eRSDhIttt9/D6fYB5SwGWaAXVbUGW8HmthPKMhiJ/IKjctRw5tpm+YO FJWTzV4C5O6VX7YdX/J6WYN/6BaSjjDrbM4mRZQ5YKws7MIl6dhvZ91ihgqr383WxIDA+qdxhFHa 37jukVZu7T6icxxOIwZHSwW3lp25cLo96K+wmRNuHfmiGlBKM6orjX2z+SJUTotwPtSCnJFUcQF+ g+9S8meouyf4165W3S0m9qKpE67N0bFEk3djdEKp2X+kLbHkVuI4szoj0/gEoHvYYSaCVfzT9a2w fsnywzF5mnucfW+Dzc4oJ9U968BNkhddBI5ILkS+g2CRYsbJwsecb/L6rHLt8R61B8BB7+KDylxh xQy8HHd8C0yMDbcCB7qaJ9EdC4H4OHesivf7tc3lNy2yyiEAI9KZ+m1ci4luqIa+3Rv9ED+uhLur DhF7TkNBrJ7MgNAGBLtLOZPtYTGuh0MsN8EKgVwAz/gYQPj9neJQB9DISPtLf3VJ/Qe4UgAtmJ4D 0fIfpx6RlTtQ9z/yTN7QGd5Dtz/KuS74namvQ5+PHinhsBodn4Ep+/gbSngwQGivVgV2iZqwiEx4 PFzwR1vKUe1zZ8let7Cbfzct7IjF579nGm7fyEozME1R/x2c0mh1Xv6iAE86NgqlcWe+Yw2np2ml wS4Dek7cK8SjjUtSNJUcmCpnb4MYSL2Rh4W1vL5uDyCdRB28FD3IsDcu78Qkwvl3y+kpXps4pWIG OdMRK0fPDEN9PCJFBC1TOEGli6bfx/XcCBPrw9d6FAsKjMw3kTQsHc3bMTxSqkC50RNkW5EeTKrC FOuKQxQNv9+2r4m7fz1007WMreXQOE6rwFi7xVsrV/AAaqWDuydQg1PRL42Xo/JDLKjQqEqgFNE3 460TClhwefuqSWxN7UoUiZ1ZtywZkekUsyeQkuSRmj1OqSHwk2vvedE3v73PAkFFZw4eKkMp3XNd 3QymN5lAb+QJrwKCaSTmvMttqmldoOUAyo5n/91fkwRZga5fieTk0XTnV9EDHTsNKJd1RXZpoaOg K7dgWWdQIC6kwHAzSkJEk2uHqzkPRQbSiDt0XHQkbiWXDwyhkbJ7Pa8b0LSqOK3WCmj8w/VJkOcu MshaGHUQDtBpJZW3dM9VAeSdVLwz4bTPZ9HofEUeC4qh4ItZIkJYE8Anm8A+CgYvH/XLx21aRBx+ qTai9ufzbIGSXwClxhxqx5iKXb4tETlY0BkfqPWP2Px6dKhhYFoIdzFixxcTswolgO3WFU9MQkEe zrSLUNwSUd1kezbXfrK/s/HIhVTbzp9N09uMnnlUQfR8E1Nx1Z4LTEkLhD6WadvH91DqvnC/EKwH bWBiv7vdNn0YITwmp5SrOOUd1yrtf9nWTzB8oXQaD307o3hKvZC0JlzMSEIDTEcng0RBKlbkevSz jhcQWzqRcGfKWWG/nei2ThPxJOKb51zGzlDo+1+JwEXGPVY6+MONmcZA4d8Z0p/tn3zbYJLupKnE s2xVZrxvbra/bFjpvIESet7Mw0aTKQEXqeMQ0EnglGkOEG3xgeDIxJr9Da2Pi2PTEjX7CzUJFWQi NNTM3YYzkBXJ7aSuGSk5W3BIOESQhTOZJ1wtdfhXqNBE3L9VWVNa2J5p2rr8Ds/reAr6OmJLqY2Y i2wvimQQlscqtBegOJEwW72EZpdWkjKC9Xl6hGE58jsAWZgpmycEI+o/qNO6lQTF7tUsRwAIoFAe TIEZ+T0zQoBxIQg/DQuintrv2ufEAHqmFWYuvm2O1D/dZogR+SjOXlcc2+KT5kgBlUCAQYEzXYwW Fl2vp0vqMYENcpB20wtHgKHEDVenKsIEezn1o3Hn8C9y0wnwdA1ye4YvaI65RY7fhly7htvf8wxq SAgNS+QUT5hKmypHhv3pIFa8xs/Xf/UqgWxjShPV7XTp1qh6AtTZxWco19fxGk+C/fmM+51OExCp BWWPgwfS5G+es6GtRLaGnyexvoPb9Ua9oi3oEzgJYQo6pbulBdGDMotO2g4sqGlgcAie+WcBagSK UkW6t9ccy9tL6k8kQ6GI8w52BCzwFCCkT06XbahPuGP3u/OVBtnKnV7e45bxmRqWvtDj5vIG0+II 0cS2FxrsVoZEu6XyFIq0eoay+D3XHFVubkyOIh8w+KNTWNJzuLzYTygS68g26rp1vwdZgtpRaH1q VPvOsGq0uGumpGXk1eeG9RpAFq4+xzRpHkWD9RekERy+3W8YpoWo8DKkbDMQtAiAvzPAITNpQmfV 5/blG82osVTQuSiJwvkGH2gs4NCbZ77VgCJ/dfWQA9iADY8QQjJvsfZdn7KztzYv8eMJw9AC11Zl 6M3D453cA5y1D01TtjxdJg0wxtd7mi2ORXWHkGr+jjMbMON2hNW/8KXYLaBvubYDn3FMy/bB1twU mnjeWpX069mA4lE0rK5KV4uzfKy3YtYcR4+XXVdlQUNeRoZGtiPBq626VgS4+fo8+TYBGX11EIEe 3wEqVGfIIb42x8xl9XmLBixhkeATTIkafy7L5kCKC6NH+89S5Z43io/8IYn7YWrNmcsppV6v3skn MAIEaohvDKsgyds4zwbd2mIL5KvgzEEYRp1FrxjlqSp/+POuoVHr1DbtJ6EywAuSEV/A5raz5W/c /+2FmYv0M47H7/l11PXw2DVAv0GRrpbvF8VvvVx0ojcDw5fVB86hzRTloEnhqjow+DkW/Nsm5q6q HR9tSaVqc51E8OdiU+ZYPHHgJv1O1qNVEE5VAu8ZFsf7A9mVqOEeHRUIgTY/qipj+katJS826U+W tlKaw+gVWdU2I3k8l9boVSyYUJJ+dRdbmMThtfpo8wR8TwNiCK+qkcuT8rPScdussrYHUrkuTm/1 MskqmxQJvxw9Kta+lJ2Wg17OIiEpo3mrqmc8GQiAJOOGyaRl+Nu3qYb5czE1Zha0PlOumRfG5JLx 7O7PKTdVm7QxMXwVsJ0+mqQVUO7RHU4avyyXWxYEQjKLvln8mOQv6Qrksv6BWiBjn8X6JbrAguUT PVD/9KyEyUJEuZH1iTB9BTmjoAJt/+ZVfLbE5PG2KIw2C0/gY2GM4Vv3CYAlJbuBlk4aSO/g1Eow l9ljkplNvBN3Rq78iX9Kulkm4Kt7qm8oIAVvFIGOH5SOkeQ2r2gFJ0f8Z//viagWYFd39TQR+Lta QjYFIxwzFZ8WUkL/p4cf9YDbstU6He01zEjdSAZdHtwrLbRRXlsvdBT7bZ4CRLwzwbvA454yUeff YdAJlwFqYe4e7nK/Wt9VTS9WshZ2jyI5CynYzbIvJ/I9yKjqtqmpDyy69cBosVwcGeKuQp1ZBPXk edTZ8jtSCKaLVcEj26M08KibalozhldsZhfLQjgRLBMmuAIhqVmpkP2iP47fAHg7Uol+NeB6XMW0 BdqLhrfAn9wiRPY6QUX0bECRMTMP2GnFJlCTAOELQn89zNEDmVq1+5OBVDM41x7xW8wzPXqlThJK hdJ3d+MqiEVIvzfishjvKY+2FD6Vls/ve+d6R6MLkMneR75dT0pq2Hr+n1uSdEE1bbTPZLTW+dC1 qQus/b80rpU7Hkeyic4oSuGcjCesnRbiQ+XE2qUe8lKjjk8go/Ge+eNwmlOOXnz+5aoej81u2fGz OVe0Py2vjvS+zi7V34VbiFTx1U1+FTCS4hnNNLPH/3EAqDM2fLOPesFzv+XjBFbkV5sIGJIJKT+b 5qREs15JY+cTKdDb4F9EHFXV1z6cf5lI2krJKn2T9KsdClt8F8jSIXAIK1att5Ik7bNqHdntghRK FZqXxLHWOSxVBm2Si3nrsVFTJQa9V5vB4esLFFz7XUvzN52jR/YO+kQjaIaDXzn/FS/2QSoIDzOd nfD9OdYJ2URfuJGRLqo4C/31FVQJ3Vk+V0Kbds4n6RMaMYGchq4MbNLEqcC+3knTx77wmDbjn314 1CJrTdqk34W+RCS85myZqNBTCH/Vbnf4+v+LDUB4D+rwSE1KAQ3OsvZUvebQd2Y3PYajOEfQgeQq ZXJDXiCYD8o6teHV9US0BmNlADUWLY/4SEL6a5KL7ggAE1YPynHihW3MlZ1upU0W35BKtbWlXEu9 ue2otS7Es9YKK9hORPTUyawTPylwhYCVTxm5fopVnFdgwrwD5bRRf7T8xFZ1wjib0ujovLUnCc8M WY/DrFPXHkGlcuTXsTsTnSlj0cxT5AvG7hu9V8U6qFwNyY2eY8PgXc8Ov1HrC4LWxY/l7eEDOJhI VmbZ+7ZIpG0e0ET6cJ1294wBRxmLYxQTYvGc6BfgNLPUoF0KbthkzpEGH7Dh/Y7RYZSd7iZHUSTY nkvYlxDz52A+3ZH9m+icJFCzNlyrZYb+qqM+c+j3W7c8+EenVN1+LIRTHxIEbsNTA3GJRxSt27qD xKR7wU+ICm9JK1EEUXBZlv0DTv4uF+YqTSw5eCnqAL1zNJ1SpNvGdcSUKOzonlHdDDc8L7mZm6yU bdpNC5f+vBLE+LcG26unZqPprPGgBw2YdlWwhz8fMn8yqWmUKgb516kDd7EWImoO8o/+bUkXvkSG 85AaWMoPtXUZWfAxm7M9XaWjIipF9+JDblGjMvUi1/idRy9m6Vz1NH0Z+GcDd5Gzvy00q4o3lLiz 5qQDPaQ8UTE1VHBlSmxzeRgfSdm3WFr/HxHykq/7+4gccY/0C9R0k2qSJlzksag0vR3p1OFcBcr4 EkG8rI5jpOAP1ElXQMYIXnLmA3+x5sZFZWN45V47ytqLaiPtaZa7615SNDUH2iZ1qFgZuOWm502S 46pM+DN8ADhj3L9yZ7s4xtugtihA63jIgXqc43PudL0Wfm3pfSAYVn8ec8noTbg5mpwnuAlVOgDu HL+XkQX+nNXlaC8fpKHytSZqTbwvjm84tWvunMj77fwOLS8AmagqlWscjwDUoT86KKxrsm8ZjCtN /qbS7UQshAJArxKapORXGNXkcD6ee1+YsgDKS37YwY2OYHtF22Zyreno1maN+F1nhID4fkAW1EA8 y5HzeD9cazwMewJDAs0tgT8Cso0qhViEtai/MMuCVn4t5tSq0CAONphnP9C/TUWxDt1CtYu0i92K LmnLDaz+R2sqvYqcMc3cJ0PAMVTu+N80/HSgtZ7MbXzx/cpFnsrxp//JVrFwi0d8/XbQjDZxFhx6 dUdotSfJQzpR213+L4OMrvk1aHI6HEwDBRpEqlMnJvQViwuS18724hDf1BubTVJcw7utt1XO7hqo SnQltZkEOyi9ewATRONvfq+sb94LH6KscnuCGC9eKWWL `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 19200) `protect data_block dok6f1PjRyvRZhS9BapubvvOv+OUZZNhMAqxhvkHYTatOP5iyiiWg832nAYrSfnDIcqLwpZ136zW AWf3grdWnIluMew27IDsPeMh+EXTkn/PePH+eMsznMT4Znn8OGCOujsftVERybUKTeY9wdokdzpD T0B54kMHFcNbk+ElGvM1BTYGuOw/lXjbdqob/QlduClVrOByiVUdQ2ZWotZMs837BdHno9bf6+ZB 3NB8IjwpWA/7ToIYDSbg6zAIuyUuHThgygQy3L3In2lDoBmtBfvylZaFUdx5ETIHffOGvC65i5k0 glfA0MWvEyT01OUZ9MFV704iFkJNT+zpbUO98rU3hSJB0jhiMnmKiL35LqE7XDuuw6RehplilL1m UgIS5CLa5Rzsp5nnmOgAvfuseDTS6b+iF+gCYMoPz2xU18aICEeVHopbdX2Tp9eTVXZ+chv8RCeR 6jAAR1rpJeUCqmBQb0wl63UhvbCyvC5XZCzT+LXX8StpAwv7CiC6WiFd4wocuujkvX2kkdubI4J4 x8pZs0k9/AE9h9xtfW9prjYZQLc5wcqcMNBT+D169HSOtHzBrzjesuxF85jELy4SmJW3xmOR5pD6 MHZZ9GBodb7Qh6ZPDM5irjm1myhYyqn+x+lkwY3NbUPzxfew31gDY8b6Lw+Z5sTwkBd+XGE27dOv Re9e91Q6A4ZpQ4UHiNbuGwfJQcN/Y1wy7d3rl0mkMepQ15xu7D4GfIrFq5iyGAha09V9Znh7Sdwz w5sXyzOPsxX1vXObMJsiAweDg0r0doJtcSh7PwGUHUOvnN6SqBAwXAyc+Ylq1JZbgqp8TXEEmJK4 UNZEidlYETNgU0PqS6T9E2O8ABkeUKj41aXv7jNZmL+6N3yZL6fXqNVR+XocPaT3S/EhiTCn+RDt uVwjirylJ1RUS1pgqHcQ46/mGKaBcLabIvZdNIHXuJTZwnHatJJC4uIIPGsj3bToDjoZxk9RvLG1 ukz2rGaSdxvyYfwfFTzxvePslDOeAVJH5lFJ4uQ7k5pprvSHk1LuiRJKKlwUj/PvtIJXYgv7UuXR +/XqU5zJloWBgWXnioVyG8SFzN7rzBVlliAhXXtqVafRiFLHFJ8Hp3oGYKfzMQjY80ii5A7xCsGe LCZ2WYChahZM81e2MitU9mM3j9C/YA6Jnf4t3rK4NMHCqghvR0EP+I4kFxJy1Ck9eKbUn/TFOl6b pswypTm93akQSlgPjjS6urz/AgLd19slZHmsvMaINH31JG+6OS8HngOzS4d5JgxBtjw6NQ+a6DCX ihngENvXdBLYo+Gn7I/O+vfHYmQDbrq5fJP5fzti2az+B7Ce0l7J33mdTuGdndQoe3wukPNS7siW zxLVI3+1cWzTm8B5OnO5uv+Gk5uaw1+bM/kEI1H19yaqZ9GMW/yGxBF84p5oohnDJzRrMoBxjYVG 3GEyxVlDkwndjf2FoKRBwxEvP9zb7GaQZVBm5iC1A0QPfFFGAom0QZoPNxC7dx8t8NDKIxuj/Al9 cWc+950lu9kp1FO+320kpCXLFa9RTbd2p+k6kx9jkxjkbZM32aeDxtSB9G8fsTM/IODBrr0TgZaj hnsbPndPLWrzXNob53bzqhUw+zInUuzf4W19isQBlwUpPsVZ6f06wzA6POkPqrKSJdC/HZOs1aBk kAK7S9U4WZTs55Zfs9LlG+n0V6OMKlFvvKmGBJDisHp/7UvUUE1GoY3Bimfw+DPyQTWGdmbb6u5O nIbqTt/HS7r8IUvi0VLGgsSprCngKl1aeoY5ngxUJrA3QfZkfv6lscKlP45Fqx1uvXKbR5o3H65T lBrDZodLF1LNw6sBl62FHmNJXngJ2NW1qVkf16j6D5PPrpRHt+8BF5ZhiCAwoW1bhfSNWmXn+1Wj cVrP3BNf1YRNbvKm8UPrQxskRagVboldQUEojszZscTMUhH4pcxkLR9ar9YsZIFFAJX8V5zE+Wnj 8BP2F2tY3qxm9kl0rS3TbMb1YHKyds8rJsRd1GKgUGpVT/oQcOkNADTCofjvWVYA9lX8XHPmX+aF OisQB3z4RW4Ok6sqte5tQ4R/bdWPo9/LYGEiO2fNghV/AB8lujczK206dxcIJDWNp3gKKzClNxNG Fahedr0/kFr9YSPV4ngg4Fef3aZjQ9YJI6MWD9eD8MH4PR42rpU/BTSS3MRqBD8O4UlQeqznbbO4 57x0xCT3yUXsk9zQZBbZtbh4wYD4a4TLDiL7VfF5bC+zUHA+YO4U3wDNns3Sj4/en19p9JGQHyqf +OaOOFrtxVFUkaQpjz6vxWVa7owDQWth5erXjBmIaxLmSFoN7jA/FXg0uUyVuBDeGEGBBInl/NJu /Vlk0peNvaPTgig4A8P/21V3hQr5Sv+2huQdx1aMVnKdbRDk5Bv1aOqzAVz8jAioK0kZuvL/ibQl HncRquZvQGzlXAwwCAK5kW/uLN2jKJAuMJSkpEtiPGbOkd3z9J4NEU12uOPGdh7d4EWxwxmuTs/t 2IL5Gfk7c2BAVuLx1LMceM1XFTETdBUhNtlQxuVyjlm+b54kK/ohDmyLtMaf86/k8UtO78waW7uU fcZyHL9IPukQ9dRJdvRoa1DKKgfgi7s2zSIctJBAWrXBQR09YAzZFQaBOugEYA+rnam9bNjClZPw +KYKY7hv1iazFdom+TBWsI75PssmvtZGHnqYKvsbcoNI01cjJ18Km6N+5xuY2k8qlE7zrQWX8t1c uYne1r1o3PGblsvfSG6IiFd7U1VShwmB/KQddcjOv+bjFAM7NYHxBBuIkOKkJhOhUSJ6S/t9odE+ gmZ9cM+hGGLFfWhtGODqBVUJ989h7zVAhlguIaRMKEt5RrnJQBkyuAYsULEyF+GZCtvCQcF+D20k EsVZH3yDYzkgN5qtJ+FiCwT+2bmvm4LatOwP6EmTGp8nVMfjUFTuUS6ZLAFXT249pXncgsN+9oDa ps0z8ikFCe4zu2pO5lGyI9S5rCUEikM5YTdGgtvG/DfTfKhmarW6nfvBFhpvHuN96Bxn/2pIUEBQ bJlHyx9AvrGG7e5G8eZzgRtO0erkfL8gcKotnPoBYmhDb6hsAi84RTJ5vIRRYv6pKwJWu7dtsIEM q19rUKmOmFJ0w1SuvvX7z4cfuQhKDY64gp1XkrnCTb3X13OUW7Z/PhQ2decruERcCusIbL5+tXsq z7OVLKgEppZV08LdyciTBAXWaI4aiVy+K0RbciuAwM9Tc8TtCbHcg16+RPm3oZGKsxSHkiTeOYkn C/9EbPe1LVkHYzV6h7vIazOSDHg4NagYMMz+Cl+BwG1UHcX1Mew1MtkFbet3E2fdbpWTBz9vhG+k xu/fIsr17gqhxWeQq1FG+Q0SSmGiXXadiHyS3I+Bhc/tLElyHsk9n4zdyDxRzJK/uJO/L4XA7LZY Xck4WiqkTL+aMxlhuo5OY0RTdxjJFrezygdEJ9FqChyVUlMsiOkeuVveJXFfvHTmHs9biLeWbbr7 90bThrEUyNoqLjdIQlrnPD7DDDm22Z0ea4jjd80vjNpQVRAdSu4GfbTcSsgTXAT1JCuoULhV3+Zp nUzmAceq2gsMkU6mzeDpna0bO6mC2+IAy830iJoGPwEptmDj1fXoHgKczR1y9qGHHt5fuGbh9EHz LM6wpzi2rW+uIORjgvxH1EGyEtlNnVFZAgxkfkYM1YPgy2UYDLf9zuc4i2dF+ApzSvAlrxudMKKz kbAawyjAn6k4DYd3OJsQ+Z/vyCkVyuqJRdfCLksAfun0kDXq0q6qQTjt/Yb6oaup44wxQUcIdBGW TCdMCIBJ9croFftF/JvaTqxlUeR6jVcvNjE1gDDBqcORTFMGFsQvrOfYCOAiFzTNcRNmGos1d4me ftFwjx75eiIXLJkTVaO2GIK03m9ov8EF//ex5ahsSno569tvD9SzXCuKXfklB3FqRyuGHc00tir9 GvK8tMr1o4dQ2ulI4xtwj2HWh/iqTMvEFVT4wooMarOFylC8aZE7dFPwh0yDOwgIZtbr25Vbc0IG j3SQIxaScl0dFs4V2EnNEHBCkUOe5HxbNVbEhGvaR3i208PjJt82Xtp/bSqtOmvsASIO/6K/i+7g Ftz2gAOGI8XGSO2LbOQMUd6YjHX1bOnGL+y9nh2umt2xaNb27eyGPL+zannGoK7wqYWj5qJRXH6v JuxpSog+opLqAKJWNdVlQ6d8a7/jlhET2vdjzehr1e75U8y0UcGYP6mEgXoX2yptdx5hYGuwYSjT t3wa6vYTC+mHSPDup8D25C1JYcLQ3EF+WCS9wjWpUP8G04fNGVD6Bk/GKgnd9EpR10EKMMInfbJB xTfRxUf8JB1sdkTOP7kExMb8J28xAyM4Z2Q8TVTRaDTUCc5NM1wPtkySAsYdcHEsPFFNwSqpYTwt CQfkKccRCpAFEWSBPXvQLoqDX2923dnoj997U4tCdGp5zgLwulU+CdL0ajf+My3m69Xn1zDDUMel l9kXlGWspA8+KXW5LGqcuOBg96NXYqfQgyep/nAKn84cQTYY6PQaCHZ7/2B+SaTE4BDfCpXaHMF3 V71BJrQH0UHUkMlpa8saa1bxNAd64ysQzt0tIcnftKg5VCTeeyn+hHd0GpjI2BZtv3GiZcUq8M01 2Ulw/XKtczAos0iJsOZhIKAMYJkakGqx+JPXN5jABSJAfJGYtrv2TIvOe4rC78RUX317PbpG+Ukx dYM8XRuUlFacD1FCO+53EPSpZKKjKlNcuTiJaSuC4BY7zcOdXKsSUze36iE25r9OvVUBMQhf/YY/ Hp9nstXjwcDwcwHGIHcXjwEDxqfkRy1bj/GL/aSL06V/9LHHx5aFQ0QCuLdfdsChmte3M6g4j86P v757e6jFCsA/srQs9W9GkDB6KuoqQfzrFnZkx2lDe+VPR3GDsyaW3qqF3tCH+uK7RWRodXqEaDPY tcsr2lyXDAbkknnCq7X9yKSLkzUTNB0EL8vQ7VVfCGspGAtEuw5wJdj3cv89ei76fi31bbzyGSTA JdTAd7j0A+aBnEHLXeP5oFvyWRZWIiKZs8OoOUrBYhGy2oSSzx3kB8fYGbswetMplaePzvyjgWsB Fa9t9/LfPm9kZy8ruxlZ6twYlwRVMvM+kPzgNatatCoabTXV4h+cDxtXhnRo8r/DJmfvJbA0/CWB j+QCYaw2SAM7XE/LxWedYCPhth6w+8+6tELycMSZcEPyLDsotjLbPSs/czY2I6JGgz0emj7pPX8D QKD4ClF3mJ2oQsebPbpbrqcxx9OlaPDXhWX3j25zVPkv/vakunGLcrbrIzGmeztn1ML3HyAWhchJ BebnyvVaD18EW+pbRw3WpCUyKxfBImaqAeehLWhvI8Q+PAqErk3bjMSFm2GEnyNjr8hjT1TzNmjJ qb3N5mgdSSatC7NgryvtDSUUQeptS7yF1Zl/gDppOupiG0RlVmzYM6dBRFwuOHniGXzIv0Z8xbtU x3pgbnkDVQD4yWIgIWq0i2tWZJQWhsb48K8Ai9D4YBiVAuMVrW7RLtIu073e6vkCxwBWi5HcWeUE pHheof6i04otG6iOYaElps5Fmlu8gCfvLqIIVZ+pWE/SXRblRvm4gsrYt6cw/GB4zvPT4AbRoG1T 8aY7+VHwK2zKwt+FyJuRvR9oRDGgv76NuvOSs+XVeMsf9MhvXUMEcfjpkhR95XhgO/cqu+Yu8Zlg 1cXJttOZalLOfCcurESn9RGbdbqdxLz62nQvkwDQI00CxMJp30z4gQHoSJ3b5jufC5eyfayB96rb JdzL6124AqEsMLAtfS1vF49Z4NwNA7UXLhylP5ujR4cztDRCph+l3/XZhnsTWfeBzcImuYcqJxCH BnGZD5VWpAuCbo9F0aWR4u6olrH7Pk4ml3CYRTgygXwtp7mz8y8lOonem+Mhdrb2zbau3B9znBXq LGVojyZmzmYCXDI9d//ey9B/vrdSDeELbeC2DtqEZkYuE2PhEptvjsN4VRQEovMZRCnN8rtfahCz tUc6sHn321le5kLYJUOBWwyAx0Cp8JxNqtCOMhqaLOsrKeIH9dQJd4IVNAaF13ydQtb9uMhZvFIy i7K+Hcei7IkoE/N9+DvpJfmVBwSLxCHdJi6RxeORlDQvWCirUKp2MCHFZZ8r2w9iDD57fDkhdJm0 4TPFqBa9bwFtKb3yu0JFpyd50elFCpjFakWqWaE7z85SoeG9vk1xTG+4NirGYkcIt9UkDs0L72Pc TfgeegFYTi+SoysC+wuSywUuuGh0aoh7NluXc4p8lziNUcBNclX8fowGDa48iTW2rzVMAd/JicQt MSvqU4/Gbv70vk5teXfFEZr6SpsmljFg0wYPjsQUWkOFQFVMwhDCKc7wpLL0cyK1PxS8QB+k3jYV 1tn8MVelb4uuR+9d2XKj5Osz6HZ8jifelrIWZ6ly/BCAFmE79ptTx9KFunvRpBKshPsiZmD1B9Dr rfruSKTP28BlLMgTPjvTJGn54C3CLA+EeGLFxsWaPexn4uL/UK65D6vSFYr0NB9+Z6uenjJWpY3B nsPnL7APL1slhXO6RR4BWOJ02qNxuL4AwXCLoaCHEboHdNRI8Zb7NjumcfMie1wu+mqYAVSBKYr6 JSC3l7rnU2KhSBHdKPwjY3md2JKJE0DKnUt11ZS+dEZRLx9hDAViMLQJP+11ubQzu7jFaunpvyNs dtIcl+n0BH9z3lzJKHnO2avF1UF+LCzdtBQpki3VLh6micrZuSyVXrud9JqpSGxLFkWHtzPVxNw7 eX/PRMz/4bzeZnQdOB+GMWl1tCRmZgFgg7BzlKsFAAsYJnZFbeDj5pFTBoUJr+6SQcWaJeRkdsru m7891p0n6VaTOX/LPK4/AN+sKiSdxZu2Cui69aSo1imkMAxtGn17xSJB+qevNjv0e7TwoKBOitSR Wy9buF9SBtTYE4FDo5S2Rq/trmOdBya0CAlH1G3YAbe5k02QSmSuv3uyskXGmqM8NBtz9zqCzSze 3z6gPOSDrWwMchDb6ntegaREyQbTOebOZQVwRqLa7j6JimBRrvvvnk2V2M0QHKZg/50c7ovrkJXi pc/e5KoQeLaS0++Y4gT6Q9htukSJujLFPrYPao1XgLBOU6YKIsIdm7GxfJoDk/fcHtUeg6slRQiC KErAnNM7w0V3L9tegm2BQqUMm+p8io7GgnWwnyb3Ah7LKwyZaMPvzdu+8ccctf8iwvoy7xSpA7LG l6T9souriHy21BFg45TjFMmSlrEShBAKhrM+AYjnH0vj1dXk9eJVP0gHj+/Y31LftKmFBHSovgCg rH98Zkb/GbFXmuqR/jkNc8kOJuomoirqM1Drz0G9GSGH6iloxtiaE6VIrbV2nAiCAdpzWlxsg1rm n+/1kB+6BWFv3aG+ggYsq3kjs1L8lM9VjL3LFUvnpT3QuK/jngyvo/kDEEsbosdDkzPhrKy4mxQw QBDiY/aJlZJjkXRAqB7+g5tp1Q15uZvoz+7K+Q6FtQOI6eReEepn/ofb2IgmOwoD6bcv4O5Hn7ub 5+NEyYQIZ9V2RFh7wEWrfe74oK9BBtjbzPkVj3j5GiS6qiFjByHnB6zrA5pQc3QyagvCpD4f8Tlr g+tI/SL6z/BY3ETpcrAwSknmogA9CLgXg6lgtLMLzhFjCDLuSWoAuSaQa7BNCOP3H0+SjK4kyjub 2a743Ayn82u0+MkitrXxHcs3LzeTw4IbjXq98J88FUKUSDbZgc0KMi7p/2ttgzU+/aqQc5JzSSaB HKO0UqN2opGglL6ITM33ymX3X/OmmbJP1tTr/eYlsP+4q0ZDJPJBGHp7gJPnjq9DqkRDZ+hFe+lV lWtM5LRCqN3gqfjWG6laX3CAr3wunRqy/ofXsmhBYI++KHLR4BE3wTf1D+pTeoexLBilrQGPbITk 2/9+SJ8UexpcLfUogS1dzafhDkStiLIEh2DLJqOWNNQpEDetlkiviN84WHxOOuZiCwh6BC94Ys9q pRpNnwr5fxFzq8F7MXv4RSj5tcJtMAvqq3cMzLdEHNST1hjrcciedAGCKSRYt0Ol4ONSDrc9APWC noJ3BvcOaR9l3PdYjT2FQpCqOHUNYLawZbbAcEz719tGdhawAos2chA9Z3PysytJ3WBhBhjzkjlk aSwmXfon1K+/DDOpadNfpJKE7uNWzno3+BuqZqrY7iHi7OF6SKXeIHHF+oqe82hSvWrzhrYZn8V3 zHaRAjNWliK1vvpaoN6k3izTG0/x3RRVyNYHgs/u5Eld9YDwo74SZ4aj9Nj2Qu3Go1D+QaF8Ba8e 2X13dVJ1Uz9GLXdUL0IEAdWaF0Z/+6bjj4fGKxw+j9sZwjMyfXXa/0XLIDVZtjNdyMzZ8Ubovd/8 iLnZ+2nXanrt9j7OA1wRGfBw2cKuG2PDfZhO5uVQwkq/DSMGsiFxhdbXQsFEojDd+LD1aJHBznIE cDt5iaUWPr09S5OjgNcs9RzM1XNi8s4qd4sHtlBpHlnTE3aRXIJSETQEJ2ZrV9gnL3qhCgUECojp BUdtFQ4hAHECiyVXLlsOe6U0BfzEE3dqWBV+0xEiD6H0kAUI3v2COE/3gVscuV3ON1Z0b5bcakeR RejKnDxUs6VxsTxlTNjz3mvk9IMR/jpqhzNMc3s2tspt8Z6FH9Zyeh7x4D/7Vv7PlmHeQdbKvxoj hS/Ee6SRG84vUDAkl9uGNuHHryUfewvJ1zIg8MRjpVNkPHr4haMlq/EJAOAA6MIQDECgt2Q0gLVw m5KiNDMkIs5lbE4XsmO9h2BCGhuhqczs3BAcLtIFeuVdUInFEaTHYhWnm5m3M5ntRaio/yYJIivX Uv28Lws70pFag/gb24CC45xDTAEMUsc1QHNutybTRU8PuScR8Gu5UKLNd3DGFYCiXFK7w+/Uk7pG KQdzaNviAB5cCV5KpEYcpRDa6/Tcr/s3V33RvvpBMJCwV19aHfDT31i18Uf0jwSY/1GSzypIcqtR sp8dWSgT27Wg9ib+Jd+mSv6uPfD5lputWakGyrA4TBg6tJM6yJqJGmJJQvYOaU4ImiqE4eQ6KX7R n3oFvIS+5API7zqUF0AuC980kP7VdrVA9gzVIDMBTfD46bGGFJxUhMoT3vSuEnFnwWUy2dOTzeAO dZzSj77IQS4No23Z8gEUM6CFof9kFWGTqyQDRPY1I1h2qNL8UORs6Ju/F2SIit8M3ym0RGrIng6D kwCK2lCnG1fJgLfiSxI5eAX3F/SIkA3x0IGET5pcEzkRSN1vj4PPczlzKKK8jszxiOR1nM5osw2x 38dgEvrJnUMxgrP7hmSVabbYhISGll5VdOQ74b99as4pEA5enj12uvfP8ISC56aHwOe+lkFeMA99 fh+J7PAT0SHRp6TXhcE/9gsYhnpyJmwn+zjJIs2yQoPWNdhhpKdw1sdmHQIqLFJcFIFG2di0sfc8 cUXGRRCKIqJG5cGzLmhAji6H2tMoaFYT4RLAh0monhWHyddTHxggG+iQxYXyBNWywA6gS834Ww9R +LUoABnK9Wn1apg4Jv00euQ5FhTuGBdfC1jImhxpyUExovTm7AaoPdifJiCwQAswqYvN1ryirzja yFGJDy/DFGa4wukdKmvwon71MkEFyVuLCYe9TWW7HDCHpSqS1FbD5tvFuuqUaWVTvoBfuVALD+My ifnHmA8wlD/2UdsPI1q8UNn0YNczJxsZfApWzvoX6WHhvg4CYOJRS6N5h6noDVIa0Db3+u1E0r7j cUkpBNEce7cgcUSiUZUo3pNJYkw2NNZLwRDAO0vtrzlWWIxgQuCPOtSIglzVXbs0rguhmGsJv2bJ wQhGgzKuf6KUQM3HhEWja0hYBoDhztGc2H9pVgyC8BZyKYQQvtfPl+KUlUWck+QiYaVb/3Gi9OrI 2Bvl68PsBL4XP9pm88NJ/KEAuwJt4EudPSLtbPvBVDm7s9Stv9BT4Tv9SRRXTgA+r1171yctl6d+ 6+02HvdNcO+St3oEyEzuVy7p1cXKyHCNuzbrlmacZjmui4NdWHwLR6aq4dVKNzLcT5exLLQfrJSM u1gmnXJGrXnI0hnoWrRw7tJupqyLCUi1RKLPyco/Vmj9f3hfA/XgSahgYWq96s8jur/vz18HeXhl LZvkZzch8v7WvqNukV3wiV+JT49lQfOHZ508QjIRXhTmNksOh/oTS8YOG7innt1ba+F/ZO0ifXyz qZtdQxzjp8l6x+eZm+H2SqjbRQUddd4oLfDoSrEapXwi3c1fcRiqkBcfxqsN9NDO7SJoxkjBaz1G G6Y0U2KY/MvMopx78dgCzBKMNpdajaujBvBNKDTgLPH8LZaoOTV5Q/YR6J9kvP12U2uxjSUY7o6J cVu4bdm84NosY//2ZL17HYenv9FTk012+xhO6Ix5niAOD6UDVu9ZigjcJA9r9eO9DSR5njzZt99V 9BeUBVDXw5eJHmBsQtlOZFA9oIocKqdf4bM9q373RD0tMnXmX2vzc9bASkj7ywM2ACHLLu94CKyG QLPWLZZ78fVnaz+6k0WhPyPBuTDD8VasBfROtbwRm+bMhVXx2LXxVgcxSm6zk7t1sstd1RlbbQ38 yBQbnYgyyTQIe/GbMITMMzoAurv0ZIQTNGrrK8pkpVVucNvGYJ9Twz8436YhNc8prGPt+xReq3Jp Qte+DQ87uTuohtdH0/AaR7MOj45+qbufFD/D8We+Mr0uwxR6p3Zntjipj2XVLfZ5uPz/IWBWkR79 UcPnFEcNwZqeO67+Kkx4536EusNgzhTwAVQeoARZfhiqgH4ktH/0Pn7K2dMZf6rSoeH71x7qFiY/ MOKWMvbzm98G3Tpvu4nFHnQj/RRTehxHnvsEOOqC0z9JsDyebYjGs3bZdaSjXpkUD4XFnt0USwCi RRKl0PQ5DVgldJf2xlsHns3f/ZRqEDtH3SgPhd5fkZxcTV8gOcbiHv82OMZ1AMg1S0C/X+kdVfJH V4wKx8ItOma3cUFBU9NTPMO4F5IB4jU+yEpo5cExIfL7x1u4Nl8TEn4O63F7fANQum+WN8jTuMxB bsQMU+t32XUNBjfDlDBj7tgWWa2w+XKGlQ8sEDdATGXWVXab1OfX8+bHhzswKArgo5JJBu58yZ45 5BtG3eDVd4hQCoqDh/EcV4f6iXzwQGwlT425nukLnz+kZeH2hZsX2T/Ppz/xlFeEm5lnm5T9Xo04 HjJa38cDzECpDWjQYuu3wCI/J3KedYfyuAAhhbxaz7mBrSC6jYu6a0GCOggOtD8HubB1Nu8Cb0A6 RJCbkK2esLkdiR6O6Ny4awm58DnF+hvlRQLdRfh1fwBq0BtIXl5lqijW4V2bIReWA5pjToipMPWK XqD+f8FNVVHW9WNO+95XgGnK5HLvCsthHcmG04GXkK1PSsIi/EaUBMKRZycxxCOnq4MMahReYuzA vm2nr9IRrkS0w6aZQZI38XCcSSLZEkFqD8iuQweFG2TCLeA6Ph0xkcHqAFT9x1dHns1Hcbex3GYj wMe/V87Sa5Q7zdICCJCd2RJAplu2YwyiwE21slM5X0LAbvk1u9MWqLXP6UyiddUiar56XQXpv5O5 8YFwa1EZUy+2MHKSRsjeHI23PZhRSofNNw4S9S9Bx+R9MYQ1oTXg4P4r07NlWSgA+M1n6WKpTzdg gVjHVvisFEDPa7oHR0kDq5s4gRs7z1Kg5zwkbRTK+bnLsTeq+7YqgHfoOdqFGVg8cIcs23sVqFq6 CGpzDombh1OZ4Ba0GiHWzBfsmCvVXxu2u4Hvyunio37yQIUgei8YaPy//Mcqr5Il7UEK6pAZnc40 KvrSMkmHnDzmqWFLdAZMZu1x2W+V/qukf7pgkVxNgSSnmmvMp73mNigkJU3rZnbiLOBepEWlJyKE T9r56kYZrGL1K9Afrv+hWwe+XixTJL4Nrt1nbnrvkYUz5irRj2HSNob54X4fOl3UKlZ34uqgHCrt q+7r5gcvMDjHFV5Ek0KyGtPlYpnMBFJuTwn+njVvx79h8yRU1UoSIQgxpKCZGDpcWPwU+SMX8LMQ yjSi4uLzQVGohOtyQ+SDLkdoZkTr1aFaWQ0LrKzVKB4PPxqZcoFrErh7QulJnoJIMx8NycO7xn4A cfeEhTOCIsTYb6qrh9Hz3I89f6lBAJIZ23gdCpJDUyuNfXXLYw5r/R3SgIpUvMDFt0YZPDPUAtRk RRBtQkzAxOXZ448iv1in1SykhRz8ey5RggYPiSo7Ys+OmSX9O5DKNgLgatIUIpp+9iPyibQ2C25d a5KDG03iOgouA/46q7yXwziTCgq9WfdxD0/vhwXwGNRVkGqWps7lFGzSt2IjXEgwmmwOxyQ8zVIY gp/uk32swcaOOJ5mFxrLT/HB1bgWb8sf72U+D6mqhAuLdGLwtSjtr6VIHjEv100POCmP7yTwRJNU p5yu3HjplmuYZbnDLkhZni0vwZAqFVyaCJ3RIQk0D2E4cZCVWbgniCHa34/P00hhdhyC0QJoR4hr 3SfQMjTUO996ntN+nv66JMLvpGHzBmEDgselHE//2wYcgNLguJX71uWKS0Rog+RVcOFO+Fa/Bi9C ElDWop70LDkWrLCHXGXKo933gP6lxVkDh8l4hjWOptr74Qhr2rUCwK0UT3qs+Hwz7SCQX/dbVwcn acOnfRgT5mg9vGMhjMzAOM+d4aLEoq9Z6t0a+yZGcZ+EDyUMczvBrrtSTdPi6QkvJCjvpdIF2xRT 9z3Gl/VIEB4eTRQhqDIoA0HdyRjc+3r4RXBZZffJbIhVl2CjTY0b4HiL/sebjk+qkPN5d1b/XcVL z8Kc8jNY85dmx5rwwm68m0X5CgVagnBsQmj44KHrZ8d4RAaHwOZcWzRrhO9qOESISLwOAl8t2QUx tKrR6ecPEZFY1sfwv+WCoNdfgNeGOBD2jpWf/gizOFGgRZ8w+2XHIRCzNbKq6eJQI0ggbMirb9Eg +MEgluP4lMynDHeXZ9LWu8cwRHbNW9zXa6+I+NZ87dKEUDCy5MlKIHA3QDxTpAXXXlkmwfrqQSas AQmxO4absXGmB5rhNYUk3yIcJp8aJk1mNJchjPpPvQwJkIn6uy0gFinfCGgMXptcw+8Ipg46Dfne nrI9eCBPNSye4nZsA+ZffN0DgWt0GYj4RLS8/mkU+L6Drr6KQwrlyd6NjNJ9qLEXJZyRmfxWFGdh S0F90H3CXh6yG+GKly+WeXNr5bhAub0RHMTSrdcxSWpcxUtd10eCB2U+KjmP8wYz0zqCjPmlUOQt q7cwvBNosFOODJuDU/q1M5pO7hbF/QXF6lPGHNNjfuH+dqetSAWeaLa+L5NDThf0IWqS+DEuAjEJ 7o30eOvW2eua6xYES+WnhfStLF/w5wy3FXlle8luMBVK2GfM8aBfTVeg5vVaCw64C8MGBnbcwNrT u/mOWtTt33bkisqAjomouNrwRTdfNavMt6IXXCwMy8Q/tYEhgs5JvlsmqK1sU3Wrt1dsyJVU9gkO 7S7781n2toiU556itkM5rAUSD+JDbuUEUOPCQ021oR/nAIDQgKRmm0x7H2FU7gyHX8oVLssdcmnQ wOJ3mOcjRDv2L22z+Hxw6ijPl3zw8sWddJPt943hWk9LCEZVJIxIxiApWnFCybh59xMraSZd+hFK 2GEYiULAsA9+uErdJP8LcnyTmb3kW4fqN1BLWfrV5Lj6nVOJCdZaf1U2uFUtsqRoAMRkGeb6gQrD GuU2azfT4BKpetEBABzOnAoDtUIdBPJ5Qscan7VLOoZWhXAQBsLaq+Lof8Q1HzIDz9Cdgpvj+Xjg RGM6Z/tDiVgNDkdput01vifq2UrAC6MVaDemS5HuY0PsWWhSLY2UtcsweS1QUwLkr7/xwBYrwdJ6 jartMsEpAL6zIV45DojyIudwbPsXEgKLWCOMG8/hcdG5ZEp+Y80kpEG5x3wyQWvchsY1FmXTZ/O1 mffeYSMydcJ22yhUZ1BSrii99oBfhmEKvkYKyuRNsYPGRH1GAvbBNxajUO0HD3gruzQ6AVnCE5ZS XEsofJGbyfExULZdoPYyfk01Af2Be/XI+67lu6c7WwfPFBOjt8TwvGtA9wNbDCUrfQIuvrAnu14O zCxDci90Jq+UkRDyVztIi3R/QocoMgwsHhKuHV3bRB0R8mCaMZhtCNxb3VnlTKOGL78lNnNqHROj Ipp9va42GSaE1hdZUsBFO9iU7wTT0h+6bIJ+TKh3qRngk1AWouJeSxn5QQqvTSSUhcKYZ9o46oir 9y1A43okbhh9ci+V7kCVfAabktoC3T+5nvhC4gI5vS1DD5DKiv7R65jnrC+1rcXVgBxMeCC/MH7s 2juFHnw2D6yCv45ZV1qlgf3aCeqEvTnwH5+O7dbXuEtz83OPo2hoTuXRlsxOmbSOePaTfMt+3R+A CvbE/vCSFkgqy+eHRZnoS2A+JPzxabMsukh15totem373ODW74loqg8JGa0Q3j6aVCkCcKXT6+xU uNxRcIZXCLeTiHPwAzujUVYG1Ve4bpTZypr6FuQwp8x8Dcz39b8XijlWvlMSIao4y/mFufsmLviI P2o8jmHpkdUy/7NGb3+9daMF+X4oeWn3wzz6WznS9EozvkyEeyC4Ac08i6i7IMfCFh5O5tC4dR59 Ll35YCnf5CXBQ+puGGrwn7g9fZelBrC613dMNGH6Co1SXu1dAyHIRrj+ELkoaAPrANDRnKDP9b13 sKHR36Y+qucf+Ea6OsQV7vuTmmYZXp3sd7VQNGugd9oND6vsQYW2XI78uy/kTvHY1OEwfkjcWwFu CEFN1gpH1Jj5shGqenklsGs/vq57Q3W16hH3PPH/P80NY5ocPoeRG+miRuQ14SrOZe1Gnfr3SDa3 l2mkgi4Fog79TGPgEcBP+A8zrfPBEZr6zU8qDMusxS3qDUxeNjhsKM8biupY075f0JVC5/NKQ1Fz h710GQQR1VI3CghCK79thmV684Qly7iF8PPm2y0kt1rw7e2V8BNT6FT652e1AV0zPdIrJcaB5dWt D12rtcQD8SoJba/i0NGQXjLBw+qUw0w7My317LvKBj0VuZl/iQd5Z8K4uZcjoC4pxz67bh9pAPkd EbA+GUW1cmsoMaPCPJXyv0hiCEZARiu4VI+l0te3YIuSLjlYM8++UtqVAVDdgFTzD7+6LGttfazJ ETh0Iyzw9qATlX3sW7Rvh6dnDDqgT+R51XF0TrQb5YPSCTynBJP/6VHKNUSQ3FgxSE0Q4D5i7Xt5 p4EITTFpNBfI2fD0O1uj0zvnSP8hwdAaMEPwXIr2QVRcAdb4Gsfzlr/k26+76ZE3yP4EKhoOYpp6 TwYCLc45PMvDlP2sh6ljaFtd+vTUplZY6R/y4TuqkPX3nkUKGfU82KKSRENtE2oHv/e87TrVLDuP rS+F3Dh736bFjGnXYee4VzUk42EnyggfLTnrAhXVIJWMt9xp0zAa0BlRJurZP8C01srRHCsMWGNe 3rrKhFAB4Bo/UV+dNFzME5DrkvvlFJntOPY0HkgkTX3fKowq1pe0ZrWzOmR8RGS6LYA+LS31L2u4 ORnAQDupPInn48WvjzvObuKTkd74CidvgHjkeyUO59bkiF9o04nb3GRKZF+VtsShlvelt36cqS1w tuIOqPAqV049UwYTPSKEjhEzHn9KkHep/znG20HcryPrABfXL17OD1AV4l1tRKkzTkOwMIFn11gV SU6kyRx/bfTwD83cT/P88DMukaG+/V5ibZC/hitDZl/hj8q9Y050i+HBXVrEDp4u7yUUJsBC0TU6 CbsNMwoxSuILDrQDJpTeWPpBUcvn3Iuxymt8sAqEGr2QvT5Vjw96qABJY5uE5MoBJVLVZcFOBOSX zV81VdfwHXBKzJX2J8XnJH+pRUcjzg0hYdwnj4dbjanCoGaNcBO2NC20L2uvivtS5vSkSDaWMuEB /kkhLnSF1xNd/8WereVN9mqwNLSMxcGdFZ8mR11bFTa1ZUt3hWcBHFi/hpBSrvn0YEI9d3xzUWWm Jndw6GrkNetZ71OsuqCRJmUtSPx/E5IOio/k6lkVFBaO9tiX3Zh60/VA040e6mZABIkkwGMv7es7 IXpxbOV9UdPhHYybf4tfaH/Bdx52RouGGM5iR+4Z5QkEKNLWl1UwIWd1MgeFjL49RLEKjiOqOgvB joVKGOpYBdY5thIo9T+qgiEchESEsUh0GAI32D6LpUQoTNu98mhqO7ZRDnGXTYSTbiR6/Zz3CKMt LJBDglRvgLIUmTmMEJg+T9e+0e1+RlOlH8Gd5m48pL0BuUPW2CJS0xad5t4cOSKGGRwd/y8vWqVD BmR2W49RPpb44NJypR5WixSXoOilN9w3ATSkeNmv2OW46XmmYpvLdflgi+zAPI2ahQXSii3gPKTX YusKFSO3JOAo02qMo0z5Ec0EjBj5iGQKJYIo/1lQrcnnU3MRLVWjwXWmObX2Owrk61jwJ3R/v1nV YgOECtHyb3rMUm+d8UPBcX+3vNXkECj6TDimag9S9UQXVtP2ECyWXmi8Z885vyKCE0rpSCH6sc11 cN4QG4Re5yXNF3NzELb7R/Ul9TuuL44MbvOq1kJzSBiNR8Qedd6OeEGOlXTyudOhoOIQ0jB+6zTy OFqBYXstR2DoFQ2Gx4hKbJidhzS7AuMu5gHwcFlTKgI1H3SekAuZTov0YfR7trd5nA9XVmT+lCKV X8pRPwaD7fGWY7D0JX9dJIFsfrJKxQaF2jxREXgq8zkqNhv+9EbyASGM5sdrM4WadplPD5V4fuJE FanaZ6/QA6GcicSkeuumnJRTFTWTjSO+1R4Z4MdxWhqvlwburxMGXpBltZoEna+OfLcJLSSjY4fJ kl2Qc2+/o14PrakKehxNd5HVWOlak9gZlFgx2fN2Vr6QKRklOeuc+uCjcJH7n7VDL0fr987meTJf 9mKig59zXKypze+Wub9amVWR7sOJg58YrGJLuT1z8hgd1XvvJpi8Lg9NkjeaP5tFVDoYz0JDKVZ4 +Qjj/RDEZ6HzfSgA5AvxIt/3zUHg72t/pi0/rDZSCVqsUC6zvnXTSrO79VIUktbj9Pt57UmX4SVP t7/6yYHhA7Z/6iGP85UQO2L1XPGwqbRVYuNJazGQ2jJda/jKPR6OljDv+zAhpEqv1u1xJti7PCN8 tqZWAE91c2L/zgfewOPbbezzTZ2wELFeF0WZK6C95PJlFpZFGL669w5Cbu82jgGpXTAP3/CQZwHP C5TCb7AxdKswUc/u2HttJoY8WsraTX/1zDBRn0wyNkRr/50p8blyvA07jabVn2DUgqiz8AltTyPK o01LW+ImHvyuLvKCxWM3mo1Vtyzty90Gb7kk4MsMtVmsDsaBpuAeGCQvpoPfD3R6X6JE2Dq/li3D Tup3t7ewpIfXSHuQop+7nEv6CZBKzngEfQc5NvGgj/Wf6Mk2uPdEPOMXBPMVE6FxZKKjqRZcflRE OwlSbZWWjqBZDXRR+FfxfSS9gQnqRvK4+tYm2v7VWKQBH3aMk088m+xzfj8KPRdO9TnKfHbgSOto aLKCQb47buo2lePTbZr1p4+YgCZs7G5Trs31XkH9Ss9vqbSN+ys6xYtxCDbv10T3EkqcLm2LLqHD p/SwJulO+nHHIgMcGAmb6QqIOcGKl26oFFBvzxJCvf14kbRmpFFN4wkZmSYuR1YbVwb+465NoCMq aOD4imDSrkkz5RA/22rLuNNoLjZsWy+3sTTacB2k51AYwNpw6EZH9+8JS+aMKsQcSITLZE0Ybxf5 ExEgghGwTFpZd0oAtgwb2oypnkkfjLZKp4J8vnTw0QsmvT8c16ShiHoGNHETRYpUcuydPZ2IQhVO YB3O9eNSy+y0+wenjb57khsbxn080syYfk9T8QMy38EovN5RPLoQiyO9Y67m0qDThVHEtu0t5eNX AP0YIgplVfwTxu5bKe/5g0H1V61kXyixQPysYgfk9E61WS+P4ZmdkegwfMZ/bf6jiwD4GlOQcOWb CwiaAGI37XvTdwq/9bIB6SK+l1pDcGX7Kkg7XNJWrVDyVGW1RXdY+lp5/E0qzWT8We3cYawdUqDc SVPtX+PmVCQu9mslMtDiSyTVb9py2c8oQDmzg5Uk0ibSAu0hpxz8pfeu1L1LFhuVn2wtypcbVPbR eHpX7AxSXQ0c7wAKuy3jtXIqXAqAyVg3dFh40vs/Fyosi+4S6Wck76+F/hmkrPsZh+BTAchAIfrN 01jDzYSdDxJJ6XMtKkmnPmiMw8rhoRnfVq9reNmMdR0nogGrCReh2fFUNQexlEg5uacXdOLOH21d VCjhQRQh2R0JlCeixo790kMHph5Xy3ZAxrlCMSRD88fgdukxGc5Y0lp4RY2B7P6zonPQ7DXNyLWa GpwUzNQHGIWfcA5jrKHX0RwLXEZOrFsVNS21mV0eKbhrSQOAEwTnn/99O0tt5OJgir1L7TZvnG+p zCZif+V66I8BH/1TcukISmGf68SjQ0A378XP+flU8ydFVrO3akJdjjo6xy9eSMqg9GntprLqqmHE Ox8NRA6elFPMjhFFssKGoU6b7E9TL6d5AiJP1o6JcglX8tvQoOG7iXwjqwRmDTBVlUaHVkdwxoim xZtGdwH6o9qtRSCt60glJNEMuDEWxGzb04Y3QJTH3BNdrDAfm9sYYMT+/6RB/32dquT0BwnYrr8d GkYUv/PHmPR3hiJHBdQNNwY6dz6oFxHkVhfzhgNTm84hJduKQSDSStFSUL3tr55MxB75ftGW7Ntd qEtEg3qhOaYFCd9pA17kDdc7q2fgeqnVUguJm81slNfDPIycZUlFboGTUvg0PQIWsVvDr8+2+1Pt k3s0YvqqEoIRAv7O/88DOu4Joi+QGfyYOXlyeyvhTfx/U9BykXkQXXmik6w6vSzsfq42u19V2ZBX bnkGt6ql++hQUPiXrSlqFtJyPBZUkIsAbhU7Z/0FyjNeuw2iXaJJZRmyjERRUBF3MDfWmJFfUKPQ jDWzwP3YKQt42rxZfZeuGncd6zH/m4yqqNk0kTfZXBUnTRI7aeyqE8p5vY2SnD3LN4MnJXjo36UE TFMPKyeSgRhY/3m2h8XxKt/IVgc4qvEKS/KN4qnyCQhoq3gznkQ45mZqUqQVVKzv0ntk67JY+JjZ rtVfprRRFMUVfL1L8DrxnzWcBAS2P0fZL3YvPNJlYDg581aW4bghKEB0jXjxM8fj4739pB/mDIGp G7OIlzbeU49NaACAe8M83sZnkCcUtW295jLhlv6HXHxz0TJHRWOT2+AvpjDgTVhFwqi/SbS3sTTJ cLA1DEASlZtADgNJazi+EIB4GVyu7Gtnum70hh3lyBnb4BleOegjrVmAZzE5/7Xftz1M5F3BV/Pa 419xeOuC0Qv/OWuayolXRF0pZIklf2EfMfs7G8Hn30UB1a4NNMJN080In0C70ZzliDog6GUhNWLm vK/h9KiMiSr7bMVuDU0ACx8s/iR6hR45iHYkTisNAiTxfXCGFv669mySVCiwrQj9CHqiuWnXY8Sd smdRsYZ9PZxg++qOFyYOtpO44eONL1KtMUR51LX3VgoO0lGT44YWKYA3TFuFwNIq7u3++YHBHSim VK2UjnCjxp2P2G3GNX1heqfxlb324XtADbaMg5IJ/LZvQXQ84MCuciqPT+XyjajubY4DV6Rv6Xi/ +Ng3S6WgNFCiSU/VK2Go6CxQ5LOPKKV9JmmQlOcCL8sSyXH8/K7S3nvgHJbde0efjpmnRr3VA1Fl N3krwpPhv15mQWSc96MiPXx74P52E6tRse7+pO0YFlh49MvIq/hkAspKAvY/HermSx+zikQIZ+jB BjHfQzAIL23pgo6VMFcbsGSnri74y8eOcGxv5VCUxNusXpR4sOhUM2mPgc9TvTcwxWdNRh5R2LC9 5a6TSq2oK6x3LKNMEFQh6O7QfZklFozfgcz5UAs88zuByphon42sS50XXhklBMPxHM0CLEqJKt0j 2XkOivIrXxuHgfIZ9q9wf6Dd7KR+oNp+uwWJCqRiAsNdyHP4OlG/2EUC8mvgpNjrQ9lzJ3OVQWxR UN72I15ZIYNAxE8RN3hQwgQUXi+iYvCvRTvY+oQ/KI04v6qM+TKfwGk//HhMLpEdR+9DvPuyxN68 yorPiq7Ts/P85M1KucxP7/S8I3ky7bmZFDJggb/EDPD8KwcgpnjIwFDK7LBWTcfoj2TPCi5LZduQ wQbImF3I65A4fnQo0MVwiwayQx2Eb0Zld3uJqG6E8JnKta/ViEbYhuYaUh1V0oZpO4GqAyL1NAUB fmNxOoMvqI1Z9SubF87UTHJzRawCePauBIYphQSbp1TqlfTz/OMPgrR+ayluSCmPtKeyD0p5G07c bOrpmDiEK7Fsj5QGWvHqxGE+iduU9rfoQt8KXJuKYUc5CRZpu0O57ImV2UmlOETSKmL31RWxHXFt A8+MKcTvnDijXWGgQtmE/XSDUlvvuK+LO5HgwKHcPbWhwmdtLPMFdFMXHIn6j9QJFYjSYf2kltcr sbxWNSCVV1xgYhVhQ+TL0uX0m6whautf8sE8bhhpeFpNvy473nh6vdRIG9lwSC/aRgmogLQNMJyy /GPS+UfVVSl6Byk/l3ieGrBiO8Tu/AfDoPzIZI1qbOfnn3Jh3jvl6QqVOSEyffoCowVHaG3rEcou We6qb9t2CNj6WdxnNhmHacha4L8nWdQy8Q9lk1Qav0U0mwvDTjwuo6X4wGt5BbjSmzTMgGIM3Aqm +ONMWOPMBvfBSfRa7fETKKHqps3LlBq5j05yZ1zledkGnwOiF5rrXwNXXxfMcPiyUsgzMFPx7yHw IdBqfaIfNzFV1cR3HbQP5FnBceaaAuQSIJRviFoQYX6d+nmRAdJ654RL5Cvrs2dAqataQbMR7cw9 o9csFc/qr8sdGdO7GDsySSIxlZ6Nrf1HggeAA4I5k+Nc8HzZKSLkFaImeqdZ5saBbGyRY0dJekrs RFAZFKSRkcawW/35E//ONM9dupksPZoDAbhClQuDXjrmhjeGWjUKQ7cEgqIVWjAcOLDoYAnLrnar OU77vl3sruK278KFkgPlozxJ3ZnRm8u0QHfsZjCheXfmFDh/rLL6MkGlt/oZFaY9SnsgT1M60fuK b4jhnou5hu70ln/8Je5vwgF6ZxEjd4fhzHinec1H9uwQObHfXtP2SXpBM94WNWnVRnaf02I8TvBf QQ5OuCpBfA9yhefTq96Whhkh6zfau3SCTkYLlcckJTY4pYThV8h0REQMRk9KvcN1UQa6vKzhr1K/ S6rgrIzXOHhDv830Il445uNNQp0/bOZKJyscTG0BPxujVnvt6qEmKbHv0Htw0DfjFT7NGInIlZTG uFZNgpOEaZPMbxPBvCahI40z1tGRd9lZ5Rhj/iHpi3gKklHQcINafKxeUKw2wZvIdBus6IzDlsSQ myO6Z9EpUSMUca0oZKAF6xcSAfLZ7poHciP5hHlUPeFM/SAz16P2nWM8gUQFY7lgWub0YIOe8o4K lCcL0vog+A7oDO0smSn+j68TOxqRdgr7a1TbFh3g2PVOA4+DrnAQN8wVBVz9BdKpAsoroKJlRPLz rOwNL4tVsc1DpmaimRKoUdOWBZHfZmuKolGG9FKrlwIljakEkTrUdm9R4/DCUKPDuYY4imq081ri 536zuceFufZUxs+hr0PI+Mq929NKBuLJO/UhI6hfQvEHN5vfYLk9TZhR0YlC0rU9jw36j+Q4bVdA dxi+Rs7ZsNbYXLljhqT26NdVKxnysMzGkkhm5dXFdCn4Xe+TbGANZzDK0cLOSrrwW4KZnsF6yOHA GtgrGUfHsUqOPJuTaJbuNP2AnynZBiOkCsR3DyrLcrBygZy4KjXn28t1iYhsgb7pgbGe8lRCN4K3 r8EwAfQeWwa72u0XnJdddmOU3J+oDm77i/HP+uETaxYuCiJ1XTGGGxvjYI/HtDv4Uh3o8/pm0uwP ETYuTGjdvll1lI9MPtDrUBij69jnnG/0BhTC4OCXlOb/0okRaT8nz7/WQqreGFaKWboh4yxmmiL6 2P4Ldn3pvqj1DCZ8H75DEuoTCm62JWp9gpm2HWAy4wgCV4i8KgzojZu2GCcQ/SmcMkxF2FxbEWS+ QSIixHgrH1n5FJpQTMDtcgXbm/Yvhx6rmCDXZUaSBAlcEeWH2tYjvVn6mZQFtdoCHY0t0wazYLAm d+Ws04xUZxZDKr72NqMuJfv5SGU7gtiWjgEskBa24l9mSMb7dmmIchN1BxdUGhQMsBQlikrej/Vq uXLaoM5NT761znLD+Hi6VcZoNVRuFfJNAvGNFZBZ7mC57T9EgzdKtQGozGIZi8EZpL0+YRyGJ8zl aJAI9fKfqkLItxrGUBGUqG6zWlVyEFCqHv5Lq8t//UqFyW4/oV3Cwu/jz3XhRStR5QGJbAXpHNp7 Qgq1RQD8dcWxJdMw3g7BtuEWJMP/aZlFIF78wSIOly38JD9wD5d3jOWoZLoJokQFLbcPiBaVZzvd rHnluMUPAtm6jCmCG6y+6mWULSu+zdfd+S6yMh7ONmax6a/JcK2aGjnpvA0gZZdgpKya3p0iCKnA gY28DJHfesfBA4bVnoonCrQ1rLWQbG/iEj6yAK/sbVKWQ11Kn19TQBtF9F/bI1bhNXjyOBUmpI9B 84ETwOi3NNzLiMq7YAK0Q4v8wk5tpvJRP042QTD4MERv7l5VcShN0kW3GV4JzLMsoFBth+bVJwgL Uizi5gQCEQMFJ3bt2P5Zld+nM8EFvF5R0DlIhZdfgPpLwZesmWl59E9LRuNcwDAeHQJNJzLSxfRj tDHX118zJ7jfwBBoLq1KC2eJWhRnnEjgzymosoSPmgE3iTSzgAoiGgxRb176nNRPrqtUmp6nw3L8 hIkjgEJNWJCHmPk4HZrTRPWO6LRAWE6gRKCEW7PyYsgTcuAnXqjvNcZ/lafahKqYlDWH6D4mywJD Dtg3SlVe9opZ8LMCDtvo3qz5K0W+jEnGwlzAQOOvGedMPjibv9q1HFrU7D8Ay7N9hfQgDBLhWID2 9Moy+fpyxSIoZnxjk72rw9+BWK2lrZuSa+nvDoso/aMI10wmzFzkECb3cHMR07f5XGdixkF/3qYy bqn0nZEzAqqBVddEiXUbaXxuvmj5MoHsnDzWMKaXsNPnYaeD2qFcqKN4R9Tzosj48ZxLgJ7LZhy7 AB6+A7VgSsRLPEA14ZDVZBXkyOYHGw0oFTRaO5dG0+nV514DFZC3f2YFx4IkXSyt7C6ASH6G9Q9L Enx+gwBjGNY22uP2qc6vE6unozuZ1WUuV80VXHiFU1gQ/0veUoxhzgtC6FDIlTGcYbduSEPDqQ+E OsyTi6pSiRBYlRe6g4XWKV/74Bcr7YiCL6RikxAQ1v5UzPf34EPG/5ZsKQxS3IgDxukkZNa0QfS4 CWEuQDmfQ5gjHCGaSQqkjyvCNuWY1RJTXFsy1f+SfqUWHCtMIT5CiXTS+UdCUx+o2FEoz41g72Zc rA9gbc+dsYUDiN6rB60qvFjri5gASUD/XkLQOorjivoS8E1oTrt8nfci8TYbAqpMXJnTlmV2qwcV JsYjnGkIhFIOIz5tf/1q5OkdLUd1Jm1yICxN/LGu79fHu4HHLIkW37rkgtgVq6jSoTYPEjFvGfd1 C08v0oL6pWk5fZI4pL5VOXDXtyhBy10r+sA5S/TQvZR5bCQS34aT871wHz0gxtVy6/NrGiz4hvwF vRgk9rnrqi3JDxtxkPdowVUoK4BeLjxjO8fBs/Tb1wz40v2Ep9VA8jeZpX45yn1vm8BC3ThCCpo+ PVVceIptBu/JwWXWh8R+BJYrHEkJoVYNxQAaVelwPm9ruMRA/BhzgQ+FlRYJowOAVwHSG0uyJ1WN GFZKdIPuMFE5xUnskaurGYdmzZ0rVUp4gljeqoub4VweaB0V7HSGDp6pETVScKEUCHHZlhryPTYP LNqf4fX+q7is8DU30BdTqxL3syOgA5/PeYHT1eVFTKQWrBZ3G+DfQlHaPtPCm79OUOAxAEgRf5C3 /d0+8B+a1R2srSuf2xQIJdkBqeFqOvaoHyQzitvQ5l3sGDg46hHnrZempiCuxowrynodSikK17jL B+kdZXuaIxCt6cIrNg0HsM5YgDciJqdZBmskAlpQAVIONXVmSD3oCz9oMrzGikJ9L9+v0g2IssUF UIRt+JxmQWMqzlz2Xg9Ivh6sPugV0QgysMEBgrpSI02Q/I41Hp9JGvtUC5qT/0HLNC/qi3OTgUeq ZfzIlk2bsMciDZOzNv93qt+ddD6vjOiZJO2FAqW0A7ytPnfHAiyPQ2u5wLCbOlEzT7sgCCyUAAYg aQwUmId+KArvchY7fT2P9xbtUEi3IKO0hFUilxMaavAUK14n2TScGzDBq7RoLpobpE09rvvIMhlv as7RXH8DBuOWiBwkLJNuCpQ2Q1KZd183z1qx0MrOksK7H63FDXibVT9Smy9Upz8w8IvPkDwnikqT OpO+7ZHmc+FKzWIhcAkNAn/SWpf74DmNvq4y+xCX9XYQnt9wn1X/K/ryKlW5NAW0b7LVH8I81HNm pCo96mgwDPxK+H5ZwXoZjnYs7ZweoppBCRKcYFDtf2Q2rxTPZL07Xvefhe+QVY7jZ+45ezj7bzfJ gG7asvESw7tofOtR93/LSP9EJRLVHJGo8wh9qCQZDYUQAiRS996ceJH5XtL0kTsaiUvDPiSQDYmp nvMytnVtuzhZGfeMGPnzA3iSGFVxCzqhQ3YD6TezfMZa29SlA9n7TMS+3qItiobjs3J1Bq/rTDMr OCpTp1bFHr9Nm2goOg9+lDobF8e4y20vzjGYotGbZGjKHlqfIfUZ9HmFPqQS7FPkOJHkAUj8a/Kh Li7t5l814ocYD0XA6hNJFR5i6ZMrdK+/g2ReRzZJmHevQQaiIoRsZQh0zATihlXqbm17nHV3uVmH HlrTeMgjUdJLOKkW7uD57j6VgiHplfH844AHOxQiL+MchRFy74ojSolrUUzuSpM58VbHohvk0+mc noUBGlatjndeaj3er/EeTmcRXvOLVL0NfnGZg41kCGR/43F5yv3JKWI8vr9ZTp64+VMG0yJs2h+X 8BvoSHGh3J4sTNFHUE+TvuyV1bwb9WDnvq5aKxUwCzRIgR8x63xbC6xVgO3HGtH0n6/LczcbIGGX VC1/GFJORg9aZ0KqJvGJYaDlelovsQMFg20uuo31DMxsss4nnJfqPhPH1n0PEp4NhMsFtXEaC7MD 8uGLcjIh0CKkqLUZL+Naso3pTOOTulpF/4QlNHK/yf/PKf+nVeTrjrDZzG5dTp1EbGClmrYSndc8 eDjWa3+aRgpdfkz0/3osEoMwpcLisQsoW6EZb4EoOdhxoyVs/yP57VdmaizOGrQssBDLeAuwzrkA I8NkhBe+3Ede2O3gGeKSXgz4Z5swG3cSCC5oAAymBhVRBBZswts32bDhB/CDWxw1b1Adim+6FvAy cKWHFChdODg4Y01c+Jm0KGDu+IX6Eyd0dtbtoRko5/g6AvHp2yyb225XM0P8pNKm9fKhIhBxhxv+ lN1xdlzS9v4FaKODym0QhBcfN18nYIUN8QgdQjrTr6dWSn01jQjWjBrL/ibpR4vS4oQHzM+EE9Fr Vjoa94Vad9qonL0hmIebAMKeFajARQY05YL/mTghuqtDrdEPq7F+qFmh+eIwK1XP `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block QYvpHWyW7kvuM2o94RSD7enqbNjFSNVx1eFUOGmoTCgYzjFOC+Y3tp4pNCvJ9LtZYHCSnjNJkKhs MA+ilaCFvQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYHkVVElVYL0l7aip5HTeKh1eV/pWXksk+/qW2XbDhFVOnvdgcGoRAskQ6iE4rqsZH2q6c1kSw9 D0uw7NtMEShxLgRt/WCK1/N2Q6PU7+FuVZJBEsBBLPPGu2KLrX1hi9JR/Up9cBy1BHHe6B4yLJkY iinM0L9ch538hsIbHmw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iDLDgpnc5LgmobpF+VkGRB7lqeWjc5Ist/v9sjE4tmOJ6Ul3CzP6ONbwxPRcKzCrYLHqOfO9TNmq Yf1JDcBl0GInMpkSukRMZ0h0FzLOYKMlKWeWfevooEQTo341QIkYIWV6hJ9hMY4kGo+TGPTCCIV2 aU8TCrKqP28aOiYMXrWFDy9sbIgMunb1SZGNlG6bhJJ3EQf6tNc3dl90n7tAC0hj94cFDO7/oNyG vo7ObyLfwUwXJcd98Y9EdCSgQxeQ5aqXi9x8Bgta2ksvR8VVqtFaqhfchjyeJljvgIdIEecQPRcP PQSMG3/VsFjI0dWdu6y3jsAtdPYT7S+BNitIIw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2OCsYTwuu2+JYrjOID9lIUOXaBBorYcdsN4bgxWpcVHk9VTgs/yiujFiI3O3TuTR80GAES9xEUrz +4J8pZbnxzY7k3hJIeytoOm0IrKqwgsXHjNHZ7rScl5BEYiV2xSi/gsVBThnykxUMfRpkTr8utJz f+lo/nrOcVViGXqHrhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Tb2eB4k5v+kC5LdponBUze15sG5kHpIGNJTRZPsCtKybcQDgn1lZYryeruejY9Qu6ggNB06wj/dx HTsP5r8o43MpdWvMWTXYD7bTdozgiOnIbGGjL5A/++xs7NooVLdM5Ig+WtLsUPidFKNN1PJC8063 VoE5HG85ZiTVPSjhtQsORma7Gdm8Zdh8E043xbws1tytVJg5JlUG7eC91nVXzvNAyf59p7yrRrOf hTuYb13KURfogZzYlrliFawQ+TIiseojQ2B/0htHfkjbJCj5KZdds94cMvQ7O4ZvFyw1xeMF6xuK wAajU4wbVs7XwrkP3/5wiyXuoo2mkevlm8aMaw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcgHKhc6gzxosUPGgVQOR2q3eJReaAkLX/QLRPhY9uu5wpVClaNCldVzlsNMU7T86IdDiWlbWavIzqUpXS332CNE4RXaXOiWCSeknqfKvsHWIrpdDzI4WSEZQcEbuPKyN5V4WgjHlqUOrBYpFVlAAgC4SXOX1fl1SfeahsBKkpXWxcylXGRoGRAmzFkCuG8hmad/aB82nPoSevdJgWN3DTS1zzCcmY4LsCfKAFUoy4mDQHg+Ivj2jmlj+dS2QLAQ1BavJ8ZyGLwO9Qw+U4AtpeVfU/ZpVdBe8O9X6h0LGa6jooEwYX+0yr8QQlp6Jow+IvJbaMBVMFV6S2rYJdEYcQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block OqayurkB+LjjXcEnoGHaIOzoXAeg74mVXxgTMpHGxDWIyAwKLbBS7qEZtO9fsEBNoz9wpPstrAj7h+7je2J7YwWEPofGxpmZxdDukkFmqUA1+0b7E7QK4QTSfhbS5QIwqMWiDSRBxioD0XsdHlXwKEVPoafvKiauiHXquAXRI3kZQwEJHWKPelwSuF+QlanL92uZoqPrUb5eqLhW3CJTyhX9ojOHyT08EpPuuTHoLVlG/QR/d2P7KfGTQUYcQHB7e4Zfhx3aOA5tF+8q44/PYugzNqElfv0/kCGvOkEZ8JgCRHfVc1c7rAurXY6BxxEau5R72pdmFvVF+61Goj6WDg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 8096) `protect data_block L6FRAasmfbSpOrRTQqjIWn+0CMvDOBUCOytxE2TNGKhoCXp4/4T/y3kfG9M/XjhHnE01+Rz2m5jF TOgOsW8tDyoYzREJ1OZnR3xFOLOYqEC6Ir/2ct96WEWN8wsXW9SirJO3wpsLhDDKUHKy9ScSfzil 08dbiijOiB6AdM9EUtZ7xZzfajazGdi86ugQK7+qvqQU7DG0/csPAsGxNXwh9XM8eBLVPK3vbetd Ry63gTwGmyIFeenRYEvuzfr0ahPTiaLBWp8sjV7Q2yM0PHB9OLGciYgJOvzfP9/qHz52/zjLtaBa ThPGcXBsNcM/RLVJYkvciZrYMD9tennFnVGB7+H4ONtWcZ5/WdIGigRr0wnMRMtFOvGwWBk5ZW5d HqbzjSDQz4LxDQEZP2iaplpzifszXYSwwdo4zAeWs2MGxsh7TBIBfaKUKe7LKPPireX2Uz6kkxZt ZDrMqCwTKF5fdA/CL24G9fpsg2bc+CTQc6QIBbq629KUXFEs985ooinF23UoU92xxNHKtGwlcYnM eGSQUk3MpXUBN1JLD13ao+/BnrTB1lIGIjwue9YBi8Nyru6VhCfVjF60WMNUO9F4x+SY8C1V30xA qokiiNipJmRmBwkqpDUX8iHTMPq2gFrO3w1gK1W8TZnMZIJXIrAqh8n0wASz93Ob5hQsA4U8wkXd OkxTSlWFDNko3C073c6ceYDOXPK9H10uhvRLao9kj5iFInYVyRmhJ5bPhjhJex5OG12Y/JXcZiTT YeGPkCnJ5/AlVdLgarZFYVc4Gi6z/bje5wgo3HxHZspBqRwQaLNACOK+TSmBJw6uWe7XxazCfoeA 1RlCUi8b44aahWZ37uoBRVltCpJ2cGmEce0mxBX/XxmyWLW32FfT09f/E5cQSiZBhQ1EmaKauF6P K5msfRDBikfQpTrm8ClmW8CqitbD47c6DjlSMgpK5BkbIdX2i6nTSpoQPam/2qDu7JDOy8737/MU 9MRPhwCqD1rCN6N6URP4Umf1tmlqKRmcBt9gFpv6CYgp0uKBV/SFFXHFRcfWDTLkgqxla7b4/+5S SMl0NfAQiIpg5bfJ9dgBclJOSNNgREgHDFEYmw+vGwzNyzF1S7hN3LGukzHryPrrcIHYy+Gx43wq OEXipdudLdXLgYCX1Zv0x2MOZL/1K9BwnRfPfpWyChoNe1CgaYV69jpDhPc5FOoTkwSc1ItldeT7 J5IBm+cx2tLB2P3XM/4T+oZFaBRvDQS2VHR9ej6BunFR+04w+kHGuzUcK/LyTOy0NnPmbS/6VIGQ r5ANHvynwLaQV4qiXR8fTlU4uQc0IzHKj6FI3H8rdWd8Y+4BI7Ig8ziENIEbxbRM3ZoVEj0KJ0BD n8eH2ohRcdyDGvYqOVYJ2Tjd4tJOHAPnNtlvjrh70V/WNyysZFVqc1AZ4QxwNoe+XAZYR20K/44i nkYKdjKp80X1cjXS8iBxjG2GbBZI3LsBTvRyqZsQWYtyHnWluB66FmD5+AEx3HfHU3kPbNX0IJ4C xhC9oitQCsQ9rgyh5Fdl5fmHX0nIcMh/Z5K0a5Cnud7BcnhRaXqkrRdWgFUtaqvDCsuLkYA3/S2N Pb47+CrUKad7v+ochkH2b6p3KFc9MX3+vpqWHqjbbJd3wk/aJrBGDjsHpq3wiAuBZrsrQLCiq5u8 uNgU++mLsdp4o1Sc7c23oACwXnzBkNzrrcQTR9ZpcYYBDG7LK+bopGuA6fPioqm2VZJ9fT5U+BfI f7ziQJ+HNzn+cRjUomEj3Tkfmz/5X7fq/iq5ha4tDbsOQO+0fHcRxvK+GzFITADhpnCM4p/wp3gq xB8VDCIKAJPqAwtRWkX5BtURVxGEfU7GFqMAOUgjE1b8k5MJWlZ9t7XLH7c7krSNwhQqz82xNb0z K3hieXtHuKB6ylr2hFEMI8fVHGZ6j07q2MrVqtU6mv6y2FdHlzMycrkINMQWH5bLyHgJst6c8tm8 gubyJBMOQ4J52jIjaYPeZiuCgV3KBnlwpKy5pOlEwBMHI1OPSmQTuAc6cyv8vNSzP4M4ERS2i43f kVhv7ZAzBsbfB0datQ7R7UDXYzIxZY8/5WIdBh5/gUjJOXmVyrftMtSRMw05ksRE/LL7pW5gcMgJ Od82wSQJ1SYecKQSJT6ko8nMvM45AV3COsESZF1xiOVs4h6MSTKmSxgNcYgeKHi47FdyA9imgb8L ZD6uSA1xUKUqxMbir623NNXPs0dkYQhOFprHC8Ipexp8z+0kkBsdlxEaBCddnnmqBPcx4WmVW1/5 Gw9+0BSLWVDJvccl+hMc9C42d3kP7JwTJJV6vxp3gN2434fIaDo87Ic1urXkYduK/Xo1NouhgXdW x5o+EdOcoK38nH+IZT9nBOo6yV32x17nWNXXHtTTtQkYwZt/KmneME3WpOYxknVro44qprr/Bli7 d11jMwsqY5JGrakEwL/TuJYFCF0UmcHH7HU458pNC/MWCbN+cv5oR7zISMz5bhIqE8Ad8xs9kpX5 rVNfZXZw/wtjw0y3dRHJ6ld1fd/E4hgNVvXLM/FSC+WYASWJ9ZmTpiu38WexUiuFVm2LJOH/eM3d LVkRM4veyTdzJ7DOiy86hfGUWzWZDuVxMg09xZyGZFHAYOSYFKTs3benXHp8hmm81EePaT8tN2Vi czNu/gHaoPO0x54MEo3CHi8DSk4ilLY+0mXesSMHVJQMDo9ngr6f3qls/EqA25akQWW490lTix6J BSM4NL1yQY/QId2XD1HmHhuJXBqEylrKdsHtzcSatLLtMwQCW9a5C0LUawYoPlQH5HNZyjugcg1M 131CkGYd2GRFvI9nRiaHcUX6RN1Vl2aeillyu+hEMIUy2uH0TQJLR741skZ5+ZUAGu8exSX5WBBk EhkKXauu8NeSEEdBT5/xJN3DSUisO3tb259H35acdM5kL8dHNoIu0jWr83e7BzOdkMsrKb2rJ4aK wneX4HcyCDAC6bbh8ybccgmlIl2vWtGbdofSHlwdTg7CuWylc6ece7YKx15nSL9cUxznYbEymj/O MlWWs90WnTrRAmckScD/0nETZyiw6KmFgzuSiPRYOX3BvBBCVVBNzBoVQDwsBSALq/DHMkdJNN6o PyXgp56+H0mTc8bt2VHdKlF+tXkVd6ylI4jmUKIG2TFMemKr5W/xo4NoweSxeDgWZOe6sZFA1Y4G T2qAiSn8VsQqZmuA+NzpDT4VQK/GY4fal5P+TpdGxGu14jzHUoGUCBZQ2OmGGFxmllv+OCms1/bq TYC7harcXidchzVIPuCP4mAriJzSUqiHwd5Ddpf34N9U5gaVDR3raTCFmWfgGTGQmKGE8RszlY2L g100vz98DOtSkEWsRvjHVhvxgIXubhJOE4WzaOg6RKGMZPpDiZybnMQzn7fmJkBLY4f5kBLyK472 VkT/bbW/oxoBq5GDW0KEWc5iazehmdf9kfB4V5UBoYGfhdgmolDJkZWzV6xAZq/jRmI4V2FkvG3R PkwEhNLR91XYdEIVlW1Ws8VmPUZnbN4rmSQJhPJgfjJTQy2ieSgwUPTGqVkKk0+Vf6bN7h59o8KN AKC1VVh+7nIgk/SZSB7+lgST97oja0DsILj85HRiUyABzV3i14TrOXDuU+uuEypPPs+nph+rfteA w4WvZSoi+NpYdMPFXCjYrknIP6aX6/yZ9pz2pJYM3BC4zj0mlorozI1a/I6a3/9qIZhsE3gyLJBc bhJ70anm9twgoAhybhIseTgeuzsGzkmL9CrKTv/W0bt5s3xufHL/2YJ+rHNTcxERvKvJmkyUDY5T US0P8qOsEPER2MDw5e6KFIm3ueTaUH+gOTOSTVBrPAdIxQ+XFIbcGzahSPvTkbLVOVn5B8ZaNSpe +5ccYI0WYudcyGlqb72RL08GQxteG2FN8cYrn0d0Epy6D/y2wt7h/3b3InEzbqRaOkZEqaDuvsKW MnMcUlS3iFVwAl8Yf9NF9GgcxGkBxN5M/AxGNxEfhptucaIPKsrYioOGv1CQ+e1sSrdJHr4XznYn kFO4cALRKQq1DCIgPSGnSa1e1whH6LoAw3UIQOj7HBn285DN5ygNn9NSyAi1bmgElwQ450Qwg8vt hejtpxI2WHzd+jzm2TYWDx6S11xdpMaE//StMNXO4yWuwCMp2aogHrJvO0ItoOVxChCLnEjBOVUh K+q0PFgOoOCKQHkGu6zMdVcNuewO57LucRojWFg3sZoIGFuZY+gTclCPATDP8QwCk/TUOA61A1Qo Kiwbcc0LpCnuVo75E/OewwrJON8+v0rtCDim7/M1Kb9YLtdJhxnWxBgqEna6oyYNJrzfF/eynd7f cYgo+/db7LD90+koIEV96nXXMPPHhxq+fwjkJpaJ9PzgZpte65zUl4mCimV5a05kxE2KOEp8nSNC LEUhlumiSa6kBGeQtfQZl3ebH7P9Nwap7QUatH8OC1LfGHPJzq9A3PkoCypGOFzzvRE+grNRUoMG jQWhoFxOp6rW706APhuZF/FVsPxpCf/RlWDdqQAtP+xEQ+wpK62MN8G/bVKPjCuTx2FGr+zrKNO0 dqPtVaYuK0IRyZgE8k+zcDUIlXQB314QCxiBLiaXKBcl2H4tOOWg5kTdO4BhS9eUtqQPzf570MSA BH2CmBJWkKDJaBOfhunYFABJfr42o7zYAk3Hi+T+arLK2uKcZ8tsYqe449TYWq+j5UeQSN1IZVlr ehdnzf7QSGnh/5qTFWRoXUKYPtm1Vu2vu+qBlTkHUE0OdhzpvfEJ99QS3grAUTGVsHfAMnZvo/0H YEDyGr/JUFAgytnLXhxg4CdHZhozCd4nFFaBzi0Gao0lPEDzGQ0fD+JVFcW25QcNAXqfpupl4GBT sBtm9whVq0/jxAWqeYVUi0005+GqgqjBMPGWJXXh0A+R5PD/rDwbw7ETUkDKLhqrSWv3xkxB4DwT wt/CoDfC9w79MOoDLIOUzaiNcEhGjWF0Wma17c4SMfmYIdhh5KVNnyNjnAQ7qNNjr1UQAj2kjJg8 zg0kIY1API73RMWV31hEu0h7Pwm4dh8Qksx0xTXkOcm9QpDc3h66qLh+buhufUNXM01un56GP+mc fmtdRPac+Yt6M97YF+NWP85KOKJHMtRX52MYk4O22B5EOkpmZB5jWM396TieolJDzaylrKeOqgIq vlGDIi6jh5Jc841OEnff6Lj2mRNr8Dt0gCw3um7B8bmLtXr79rzUtN+P8L6zs6w/airtuCVyP0rf P5C8sZlJOBwhvligShEZ/2XStNG8Zx8L8kY90Lrr3EXsm/+qYs97KaNYU6CyV6/04wzwT/3qbJjs c56ka8iEVzMyGeiW2Ovmf5Tr35cr07zqbq5XP2rntGXDwnFB0JMsV5Gws6Np7Gqhiu1+rZK+QybX BA8+rPJtnvMrpHwV6/9dDEDhfVYI8Qy/aFAbqdvQbq2wi3ezk21LnQdEekiiswbyMXKHtFxRNMXI b7lFW5IMmC6d3Gza5qehe5b2S9dwqKjUNJRfAEbyHKUwWLvqdeb264Ldo3WYp1Uxp0qSIwPF6PcQ +GAekN7xX2uY4TEsVqK+EqC+DDWbwYsyWNEjBhLVnwHmCJR/ib5EPvLgUGasWmK1hA28wUGxjDFh hOAhHojW0ok+HV0daNKUuYzND1M+DlXCbDmGDLt7aiCWbltXJ1wkVIxjdPhvR4RXwcUCK0ZGUrQW w7VicwjzNnPJjB8vmJI1Zo3GNpF9z/1mv1+hcxq4Dfi7OtLqTfcJgIg+Ztch5uQyvBPk9IAELgIe xxbdMoTqgkfrIg/R3rfl2XKKIAhCThg+sMtEjk4wfZTE7jsHaEOTyrgBP1BxRBsJvs/YB9qXTDKP 55xob08nPkUgzHt7H+/VP36gI6iLem8cX5zVUnZzrhBXARa4TMKeKaHCVx2aVP/kzFPIvcIWAkgI tQfgE9f8hi4sfXAqbM4nIJvy+Sa989hXc0tZleiWF1PSC7hDUHfC8Hr0S+nJfY3HQpjYNxgNsvXZ VUAVQNpKIRBghbSxstEqxJozUQRv6wmWlyYVyKJPHlaypvWA6U0bKMxOHKOURVreRP/2btKZTP9V UFZkdmQ3+Y9GG4b+yFj0aaN5gIR3K9dkCieFuS+F+vDB7GXE7AOUDiT1Otr+TRDt9Bvyo8CmKX4o E3z9iPPPxBvTWqCXQQcsmo5fAk3GLDIPh6XIr6qVBlLDUVd26EAmFGeNlx3OOR4EdjHRWCV9IJtc 4aUgjzy1TJnpt1bIYcKTbav1NSaig76OGx2/rJ080zc9FzQ1GACLqdIuz7grQ8/I4TkjXicwOd8O gpDwDNyqC8r6u3emHqItSIiTi+9YBr2wfc6aEs+s5S/kjt8OOSORAEO/5CM3KMTjQhdlrLutNQF8 Gymd29ByadWNCjYz9xlOQD6oxavbcKcI8VwuN9xYL63w74YM8EIidLv0aA+MtBvY3o9x4htbGKcF /VrovJDj2sBQKmdC6ILY6/iy1fpn0jSvIklGsaH5gTjERdIvv5I6ROp1Rz8cRvGISwFRYDvcQGXg AJtwj4e9sRUD2mzMc6ve2DSokr81jgmXxwvUXTfBSE26kNEWTTXwBT6HMIto+ct9tzcCuAPiLLXN l/7oNyICXfoqsyKjW9Zh8203wCAPEHfLt5q36k/ty1CV+AeWaakoNR95fgakDoJCwxsXzJe+4i8h fV+OGG5yJVVgaHhGz+1Q8zcw9O9yEAkU/pxKFg978zz3CTUpHFfphunGj7oIAqWM/yNSN0U+vrhN QnoWy9/2gWsXc0641spIe5UDMDhYls6hesO6TJmvhJNfGLTVvYXroVadfn3vwCBCX1GGQs/7FbJG zWS7NzVeFa+TZB59186F9qJk0LP7sEAz8Vmz8gbuIS+rn5SWOqR2KMBUhBg5WltlySrLVAkWACnl /IV9vMvXcTKmXz9Zoq3W2y79mFWZKv7cOwaAFL6zeHGmLdsEbiImugU2Mh0YfVxXO0pw+m+veSpz EQDRQIngQc6Apzkb7ZxNICRdHC0BxeYURMFSibyAiqw2rzntsrevF60yzL8etRnNR7ULOmD4/7tV lsxXpvoTFnn6I9d+VoZ33V79INsGXRPjMngcIekLKOwcqyXfm46xpqrIJNbId0UR7LTq/q80ZzeK Zla0LdKQDxRciHK3NSp5GVjO2NuCMsSiceCwmoPsWU4Jzi1Xl6j5oUnZJppXf/0AOZ6QtcQEz2Mz sI0z5tON/GQefGQw8TvkCF28gB3FaYSnDsKHP51vNZorDFUGPLAEaSJt7fvciY96zrcbwzRpq8vu hDwBz2dOlOCfrDFb1NvY+PCSqrwg3z6nGlhV2LxZxjqYrC41tksauODqlxqao6WR54YAuAuEsnc3 TeB9dvGwcuIw6ROMnlkYz3FK28u26inggnPIQA9cE1SKT4AdznYG94FYjynp3pyGQvF3Lci/SaP0 NNUu+QLiyXIBy4/VjV7bderDoUHGt1Dv5kC7D7wCr0CazHgrv9Xwh9Lh5RQUcq86djvHtMjU4ENS R+OyremPPwIdvl88ItjD9aRzNnSVII0pK4SlWIDIz6wP/Sfz6fE+l4quO7tWEi9eQ/CYt8iMbyhd OrglJsiPYZzPW77ouRrT1IRPIgITZdOHLJUenOyQVP5qK5Axj6XUbUOf6S6uxclsi/6A9ROoRuPO 6H05G6TTNnN2ZGASSmoSTK8e5UiMh2tQlaD+WZUjWfZXMWqQdyIf0649pSEzrbjrsosMA9AyF170 jhXgwNgfZd14ZoB86T/uTGmtrKOxBPD4wXUnHxjrEW88cR0dn7SQYxS3B/NIdhObqSkVpO+l7JCK 6uvzFbj7Psa7d7JAlNaobr+Lt9iqnCByHvDgT8AjpAH5r8Pxr5vMA9lBTc21LC7DQTcxGaLQFMbQ sRfIiInRzd/NDev6uMP6COcXHnUDa0yC/2pCvd0Dv6s0UcimU4yyh7p7gFQxxbP9DxU/ldiWb9rP CTXe1j7zCxnnI4mvNU0zSawd5X6JfUssHmTgvbo/zmBVP19vrxbrDWzP/Mir1FBXo12alMFoqlOu B+N0Em7eZ698WwqlET84SMUsx1SlyhkxD/c7AiJZuAWXG593kgLYWN7u3UDX5nBTlaMLWQRIYt8i H+cjAGIuT+CTkXWpxXuKV9fOCR0KkZ4zWsL1CcmfdV15R3XA1+sBleThRAzUeMmZsYHzbin1J3P/ +kVkiIYIxuXybPTd0paFqMccO+14AGDvJa1hbZY6b/c5FNUJ7S96vqadiaFv7Y7G4jV/1fUL5Tk8 Yv3PG9mTPvGnu3Dup3/utYE7hyuFR5NL96jPQz6tMTJAPDKlH/DFRrF1SLB7lsbuurN/b2hk6Lbz oZnyawE14wPjWkVrwWw80K4D3bQqKHlQ95K7uX3g0ablomBxR9EkdzMbyxP1UlIkGz7Lhvr0y4dl p9N3xNYzZ5WXltoh1ZdTso1BKOGJFyHMNmwKY4mDKaSFgMi4LkVxu2C9C3soAFDyZyy5xsToBpp8 b+/aqTNqSrbfYVHlbbRPuqWhIGTV5Ia721H2J0fl95aWMfwxa1BmWDYRnH50MwikAgkJIRFoIPRF 3n2VIjG5S7m1TphOiHQ5TjfwOOh9AK/hWQ6xfDqS9/sXOKtqaP6WbWNx27fphMW8HjLaCZpiPAiw lnC/OP5c4qoe39AmjzrP8149rZ97xsUr/VfQa2ONvQsf+SvjRcN8xSA4ifIrJMZAFtp5SwLEwGoD 53LjjNSXCxZc/21T+55IQIbfatMlwbBW7coIYmEHlIOJnlVWGSOzIdEALddMUeN5acR1zbyAbg8P fblj20Tr4YEwJJw1N15Zymtvj+X/LLNbMJdvlFTNIdIDx/MgkeGkJK7k7USCLXMJynswPB+8Jwqv yNli8hT9RZrspVHkEyIljLn3UjBiu4zAUAByn2YocIiWU1o/3vchpzcyISKt0xP2r7iaN8kE9LN+ bIv6LT3tcVEOTy04onJw6tDIuYXTiZWRIgTacdv0Ysvx8ASr3WRbck6XTHjBneiPkLpzKs8TXSqX B3GqpSzo/Kd+fR6/ai22226Riw1Lb3JJbSiQPoWHQq8zm2/P7cXei7mv/x9AdWQxlbqIq0NQoU8d FuICw6t3XOkJLTyST4jQURfFQrX57dFPnsmbHpb+3W8PbtcJ8Zq0yQv0pQXV1q/xLhD5svhasGbP tDnwq8jtw1BL8RDf5TsN+LRqMDs1nkuW8YhNiHOjsIYqmnXfOdeZPN/gnb92CrBTXdrvKSdoZV2S 1VQCh4ETz+JMyt8/LoDx4bd8cqrV9SDi8eiPKsQ9jGOlT18P85iH78hTTR5uGHY6eFxj7FXC/9mL Bb0FC4Xq7LCy9pNoQUEJ/jUxE8Z5eQbfB4G9Ed0OczX1bvOKqoc073Ke+ycKD3TrKqC9zNvMgQ4I DjtGwpeIj3DbcQTpwkptuSokG2VGwNSj5exrPGJ5otK7qC5cisqNCwwikjQ9Pbw82gfctphwvXeX 2DQF2y8mauUAZhNXf1nsMbD9dnPWmbHcb5JMVp3/PAM5lMVftCQfOBDO5mAa7+o+tU9MvCQCfpnx QbD69MTQ8DQGoCR6KLrFu2Hftg0RW+j7coQDDfLYWm1ehg0NKP4+7WlIKYXuIZf8mQYc7VuCGdzJ rHMY+olH8D+u4LlHpRapxdpHaVy9+h2fgHTI8fSMMNqbJX78E5kIzZ2tDUxEVDP4Sjh7tu6gXplg 13ewIyjS6JbGiITsDoElqTC/QxScsujHJ8/q7C642dIS0RCA16q/MSY3bV94m6z50pzOy+1X1AqX aSevtbDnv3Sns1Rhj0IOWia4VR15UwOm94PXrUZx0rU+ByNikm7nTdbmWea0lZ9YpP46TiA8nN0O 1D7ogFYxPq1GUqqL+eO2nMxZyx5B7/M/t4WhB4HQszvXkMRtkzVaxEWptQQpqv9D8B9XhQeWjSeh aJeXcf5Ai0TsZMylx6zqg5d20kphFoOUMfeLNxrHdJWszKSP8Q+HxzrRkANy70NXblNIFXQf0Yv0 dViI//eZRLr3yHuC0hMk/K/3Amc8GHB1UJV0fTAfoCBotZV+zsIctl1so32Ng6KLJewOjoZ4b5gB sCLCKVdi0HOad774bfkyWCZF6USOHL4hIbTJIAsqMeisU9Grx1gyXmRSgwqutPMAe5ZbI2IVOntJ 3AlvKj2lJk4pzEBNP9CcSb7pbZstSw+do/9LpyI1orbHvFrAC/L8714LZf++hkXOzlRsJ2u37dXu iVPqSjDY/wVxhUwtTg9NkTs+FXVPrO2YL6OWPdH4z5anWNQeEQmY6Rpozu4oh9QxlVzMkVCJ/bZA l2zTxvkB1/lIIhCq+Up/v33bUxX9j0DvbpFQvfcbsxvGUAQB3fraGHqdZ5aaobci0Pe/qOwqgqRj qFzykMgABZiWqiCN+IuknS4uI/Qnt+SdiW2E+p1tx3bMzxKWlurJ9LH8lvkfhVy6kN9sgIsUloLU ifwK7s3MWcichaTc7uwvyLBzi2Mu/BZPATxKHeIhfKqC9ATGZ7ZZu1aWd80+OpLvRAPeAC546TTo AUjkxKlgLV2RsIztC1xiaWD26KVnx8Ap6LwjuFCbo+f8wEw8PvL5edH0OWcsFnJ5d/6Z6A0KZkiS UzQx/z+uBr4kPMq7zJP3WY3tKkZLry58lAuOtTOiFGcl2MEsD21+uumgA2smo85SvbA10XuBLRQ0 wBVcJ89eTgYzBH1acQl/i9sIHf0vo+zDE2F0rc3lTf+orwLVVnkF62AzHm/4Ium35gSargwSz+/g kcE= `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ is port ( aclk : in STD_LOGIC; aclken : in STD_LOGIC; aresetn : in STD_LOGIC; s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_config_tvalid : in STD_LOGIC; s_axis_config_tready : out STD_LOGIC; s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_data_tvalid : in STD_LOGIC; s_axis_data_tready : out STD_LOGIC; s_axis_data_tlast : in STD_LOGIC; m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_data_tvalid : out STD_LOGIC; m_axis_data_tready : in STD_LOGIC; m_axis_data_tlast : out STD_LOGIC; event_tlast_unexpected : out STD_LOGIC; event_tlast_missing : out STD_LOGIC; event_halted : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "cic_compiler_v4_0"; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "cascaded_integrator_comb"; attribute C_FILTER_TYPE : integer; attribute C_FILTER_TYPE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_NUM_STAGES : integer; attribute C_NUM_STAGES of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 5; attribute C_DIFF_DELAY : integer; attribute C_DIFF_DELAY of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_RATE : integer; attribute C_RATE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 16; attribute C_INPUT_WIDTH : integer; attribute C_INPUT_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 2; attribute C_OUTPUT_WIDTH : integer; attribute C_OUTPUT_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_USE_DSP : integer; attribute C_USE_DSP of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_HAS_ROUNDING : integer; attribute C_HAS_ROUNDING of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_NUM_CHANNELS : integer; attribute C_NUM_CHANNELS of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_RATE_TYPE : integer; attribute C_RATE_TYPE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_MIN_RATE : integer; attribute C_MIN_RATE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 16; attribute C_MAX_RATE : integer; attribute C_MAX_RATE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 16; attribute C_SAMPLE_FREQ : integer; attribute C_SAMPLE_FREQ of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_CLK_FREQ : integer; attribute C_CLK_FREQ of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_USE_STREAMING_INTERFACE : integer; attribute C_USE_STREAMING_INTERFACE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "artix7"; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "artix7"; attribute C_C1 : integer; attribute C_C1 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C2 : integer; attribute C_C2 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C3 : integer; attribute C_C3 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C4 : integer; attribute C_C4 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C5 : integer; attribute C_C5 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_C6 : integer; attribute C_C6 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_I1 : integer; attribute C_I1 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I2 : integer; attribute C_I2 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I3 : integer; attribute C_I3 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I4 : integer; attribute C_I4 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I5 : integer; attribute C_I5 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 22; attribute C_I6 : integer; attribute C_I6 of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_S_AXIS_CONFIG_TDATA_WIDTH : integer; attribute C_S_AXIS_CONFIG_TDATA_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_S_AXIS_DATA_TDATA_WIDTH : integer; attribute C_S_AXIS_DATA_TDATA_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 8; attribute C_M_AXIS_DATA_TDATA_WIDTH : integer; attribute C_M_AXIS_DATA_TDATA_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 24; attribute C_M_AXIS_DATA_TUSER_WIDTH : integer; attribute C_M_AXIS_DATA_TUSER_WIDTH of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 1; attribute C_HAS_DOUT_TREADY : integer; attribute C_HAS_DOUT_TREADY of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_HAS_ACLKEN : integer; attribute C_HAS_ACLKEN of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute C_HAS_ARESETN : integer; attribute C_HAS_ARESETN of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is 0; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ : entity is "yes"; end \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\; architecture STRUCTURE of \cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ is attribute C_C1 of i_synth : label is 22; attribute C_C2 of i_synth : label is 22; attribute C_C3 of i_synth : label is 22; attribute C_C4 of i_synth : label is 22; attribute C_C5 of i_synth : label is 22; attribute C_C6 of i_synth : label is 0; attribute C_CLK_FREQ of i_synth : label is 1; attribute C_COMPONENT_NAME of i_synth : label is "cascaded_integrator_comb"; attribute C_DIFF_DELAY of i_synth : label is 1; attribute C_FAMILY of i_synth : label is "artix7"; attribute C_FILTER_TYPE of i_synth : label is 1; attribute C_HAS_ACLKEN of i_synth : label is 0; attribute C_HAS_ARESETN of i_synth : label is 0; attribute C_HAS_DOUT_TREADY of i_synth : label is 0; attribute C_HAS_ROUNDING of i_synth : label is 0; attribute C_I1 of i_synth : label is 22; attribute C_I2 of i_synth : label is 22; attribute C_I3 of i_synth : label is 22; attribute C_I4 of i_synth : label is 22; attribute C_I5 of i_synth : label is 22; attribute C_I6 of i_synth : label is 0; attribute C_INPUT_WIDTH of i_synth : label is 2; attribute C_MAX_RATE of i_synth : label is 16; attribute C_MIN_RATE of i_synth : label is 16; attribute C_M_AXIS_DATA_TDATA_WIDTH of i_synth : label is 24; attribute C_M_AXIS_DATA_TUSER_WIDTH of i_synth : label is 1; attribute C_NUM_CHANNELS of i_synth : label is 1; attribute C_NUM_STAGES of i_synth : label is 5; attribute C_OUTPUT_WIDTH of i_synth : label is 22; attribute C_RATE of i_synth : label is 16; attribute C_RATE_TYPE of i_synth : label is 0; attribute C_SAMPLE_FREQ of i_synth : label is 1; attribute C_S_AXIS_CONFIG_TDATA_WIDTH of i_synth : label is 1; attribute C_S_AXIS_DATA_TDATA_WIDTH of i_synth : label is 8; attribute C_USE_DSP of i_synth : label is 1; attribute C_USE_STREAMING_INTERFACE of i_synth : label is 1; attribute C_XDEVICEFAMILY of i_synth : label is "artix7"; attribute downgradeipidentifiedwarnings of i_synth : label is "yes"; attribute secure_extras : string; attribute secure_extras of i_synth : label is "A"; begin i_synth: entity work.\cascaded_integrator_comb_cic_compiler_v4_0_viv__parameterized0\ port map ( aclk => aclk, aclken => aclken, aresetn => aresetn, event_halted => event_halted, event_tlast_missing => event_tlast_missing, event_tlast_unexpected => event_tlast_unexpected, m_axis_data_tdata(23 downto 0) => m_axis_data_tdata(23 downto 0), m_axis_data_tlast => m_axis_data_tlast, m_axis_data_tready => m_axis_data_tready, m_axis_data_tuser(0) => m_axis_data_tuser(0), m_axis_data_tvalid => m_axis_data_tvalid, s_axis_config_tdata(0) => s_axis_config_tdata(0), s_axis_config_tready => s_axis_config_tready, s_axis_config_tvalid => s_axis_config_tvalid, s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0), s_axis_data_tlast => s_axis_data_tlast, s_axis_data_tready => s_axis_data_tready, s_axis_data_tvalid => s_axis_data_tvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity cascaded_integrator_comb is port ( aclk : in STD_LOGIC; s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_data_tvalid : in STD_LOGIC; s_axis_data_tready : out STD_LOGIC; m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axis_data_tvalid : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of cascaded_integrator_comb : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of cascaded_integrator_comb : entity is "yes"; attribute x_core_info : string; attribute x_core_info of cascaded_integrator_comb : entity is "cic_compiler_v4_0,Vivado 2014.2"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of cascaded_integrator_comb : entity is "cascaded_integrator_comb,cic_compiler_v4_0,{}"; attribute core_generation_info : string; attribute core_generation_info of cascaded_integrator_comb : entity is "cascaded_integrator_comb,cic_compiler_v4_0,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cic_compiler,x_ipVersion=4.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,C_COMPONENT_NAME=cascaded_integrator_comb,C_FILTER_TYPE=1,C_NUM_STAGES=5,C_DIFF_DELAY=1,C_RATE=16,C_INPUT_WIDTH=2,C_OUTPUT_WIDTH=22,C_USE_DSP=1,C_HAS_ROUNDING=0,C_NUM_CHANNELS=1,C_RATE_TYPE=0,C_MIN_RATE=16,C_MAX_RATE=16,C_SAMPLE_FREQ=1,C_CLK_FREQ=1,C_USE_STREAMING_INTERFACE=1,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_C1=22,C_C2=22,C_C3=22,C_C4=22,C_C5=22,C_C6=0,C_I1=22,C_I2=22,C_I3=22,C_I4=22,C_I5=22,C_I6=0,C_S_AXIS_CONFIG_TDATA_WIDTH=1,C_S_AXIS_DATA_TDATA_WIDTH=8,C_M_AXIS_DATA_TDATA_WIDTH=24,C_M_AXIS_DATA_TUSER_WIDTH=1,C_HAS_DOUT_TREADY=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0}"; end cascaded_integrator_comb; architecture STRUCTURE of cascaded_integrator_comb is signal NLW_U0_event_halted_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_tlast_missing_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_tlast_unexpected_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_C1 : integer; attribute C_C1 of U0 : label is 22; attribute C_C2 : integer; attribute C_C2 of U0 : label is 22; attribute C_C3 : integer; attribute C_C3 of U0 : label is 22; attribute C_C4 : integer; attribute C_C4 of U0 : label is 22; attribute C_C5 : integer; attribute C_C5 of U0 : label is 22; attribute C_C6 : integer; attribute C_C6 of U0 : label is 0; attribute C_CLK_FREQ : integer; attribute C_CLK_FREQ of U0 : label is 1; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of U0 : label is "cascaded_integrator_comb"; attribute C_DIFF_DELAY : integer; attribute C_DIFF_DELAY of U0 : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "artix7"; attribute C_FILTER_TYPE : integer; attribute C_FILTER_TYPE of U0 : label is 1; attribute C_HAS_ACLKEN : integer; attribute C_HAS_ACLKEN of U0 : label is 0; attribute C_HAS_ARESETN : integer; attribute C_HAS_ARESETN of U0 : label is 0; attribute C_HAS_DOUT_TREADY : integer; attribute C_HAS_DOUT_TREADY of U0 : label is 0; attribute C_HAS_ROUNDING : integer; attribute C_HAS_ROUNDING of U0 : label is 0; attribute C_I1 : integer; attribute C_I1 of U0 : label is 22; attribute C_I2 : integer; attribute C_I2 of U0 : label is 22; attribute C_I3 : integer; attribute C_I3 of U0 : label is 22; attribute C_I4 : integer; attribute C_I4 of U0 : label is 22; attribute C_I5 : integer; attribute C_I5 of U0 : label is 22; attribute C_I6 : integer; attribute C_I6 of U0 : label is 0; attribute C_INPUT_WIDTH : integer; attribute C_INPUT_WIDTH of U0 : label is 2; attribute C_MAX_RATE : integer; attribute C_MAX_RATE of U0 : label is 16; attribute C_MIN_RATE : integer; attribute C_MIN_RATE of U0 : label is 16; attribute C_M_AXIS_DATA_TDATA_WIDTH : integer; attribute C_M_AXIS_DATA_TDATA_WIDTH of U0 : label is 24; attribute C_M_AXIS_DATA_TUSER_WIDTH : integer; attribute C_M_AXIS_DATA_TUSER_WIDTH of U0 : label is 1; attribute C_NUM_CHANNELS : integer; attribute C_NUM_CHANNELS of U0 : label is 1; attribute C_NUM_STAGES : integer; attribute C_NUM_STAGES of U0 : label is 5; attribute C_OUTPUT_WIDTH : integer; attribute C_OUTPUT_WIDTH of U0 : label is 22; attribute C_RATE : integer; attribute C_RATE of U0 : label is 16; attribute C_RATE_TYPE : integer; attribute C_RATE_TYPE of U0 : label is 0; attribute C_SAMPLE_FREQ : integer; attribute C_SAMPLE_FREQ of U0 : label is 1; attribute C_S_AXIS_CONFIG_TDATA_WIDTH : integer; attribute C_S_AXIS_CONFIG_TDATA_WIDTH of U0 : label is 1; attribute C_S_AXIS_DATA_TDATA_WIDTH : integer; attribute C_S_AXIS_DATA_TDATA_WIDTH of U0 : label is 8; attribute C_USE_DSP : integer; attribute C_USE_DSP of U0 : label is 1; attribute C_USE_STREAMING_INTERFACE : integer; attribute C_USE_STREAMING_INTERFACE of U0 : label is 1; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "artix7"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.\cascaded_integrator_comb_cic_compiler_v4_0__parameterized0\ port map ( aclk => aclk, aclken => '1', aresetn => '1', event_halted => NLW_U0_event_halted_UNCONNECTED, event_tlast_missing => NLW_U0_event_tlast_missing_UNCONNECTED, event_tlast_unexpected => NLW_U0_event_tlast_unexpected_UNCONNECTED, m_axis_data_tdata(23 downto 0) => m_axis_data_tdata(23 downto 0), m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED, m_axis_data_tready => '0', m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0), m_axis_data_tvalid => m_axis_data_tvalid, s_axis_config_tdata(0) => '0', s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED, s_axis_config_tvalid => '0', s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0), s_axis_data_tlast => '0', s_axis_data_tready => s_axis_data_tready, s_axis_data_tvalid => s_axis_data_tvalid ); end STRUCTURE;

mit

fff8575e4a9a9fb88808f0733533c0cd

0.942398

1.851644

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_mngr.vhd

1

25,833

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_mngr.vhd -- Description: This entity manages fetching of descriptors. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_mngr is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch for channel 1 C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1 -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control and Status -- ch1_run_stop : in std_logic ; -- ch1_desc_flush : in std_logic ; -- ch1_updt_done : in std_logic ; -- ch1_ftch_idle : out std_logic ; -- ch1_ftch_active : out std_logic ; -- ch1_ftch_interr_set : out std_logic ; -- ch1_ftch_slverr_set : out std_logic ; -- ch1_ftch_decerr_set : out std_logic ; -- ch1_ftch_err_early : out std_logic ; -- ch1_ftch_stale_desc : out std_logic ; -- ch1_tailpntr_enabled : in std_logic ; -- ch1_taildesc_wren : in std_logic ; -- ch1_taildesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_nxtdesc_wren : in std_logic ; -- ch1_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_ftch_queue_empty : in std_logic ; -- ch1_ftch_queue_full : in std_logic ; -- ch1_ftch_pause : in std_logic ; -- -- -- Channel 2 Control and Status -- ch2_run_stop : in std_logic ; -- ch2_updt_done : in std_logic ; -- ch2_desc_flush : in std_logic ; -- ch2_ftch_idle : out std_logic ; -- ch2_ftch_active : out std_logic ; -- ch2_ftch_interr_set : out std_logic ; -- ch2_ftch_slverr_set : out std_logic ; -- ch2_ftch_decerr_set : out std_logic ; -- ch2_ftch_err_early : out std_logic ; -- ch2_ftch_stale_desc : out std_logic ; -- ch2_tailpntr_enabled : in std_logic ; -- ch2_taildesc_wren : in std_logic ; -- ch2_taildesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_nxtdesc_wren : in std_logic ; -- ch2_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_ftch_queue_empty : in std_logic ; -- ch2_ftch_queue_full : in std_logic ; -- ch2_ftch_pause : in std_logic ; -- ch2_eof_detected : in std_logic ; tail_updt : in std_logic ; tail_updt_latch : out std_logic ; ch2_sg_idle : out std_logic ; -- nxtdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- -- Read response for detecting slverr, decerr early -- m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; -- m_axi_sg_rvalid : in std_logic ; -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_ftch_cmd_tvalid : out std_logic ; -- s_axis_ftch_cmd_tready : in std_logic ; -- s_axis_ftch_cmd_tdata : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- User Status Interface Ports (AXI Stream) -- m_axis_ftch_sts_tvalid : in std_logic ; -- m_axis_ftch_sts_tready : out std_logic ; -- m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; -- m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; -- mm2s_err : in std_logic ; -- -- -- ftch_cmnd_wr : out std_logic ; -- ftch_cmnd_data : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- ftch_stale_desc : in std_logic ; -- updt_error : in std_logic ; -- ftch_error : out std_logic ; -- ftch_error_addr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) -- ); end axi_sg_ftch_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal ftch_cmnd_wr_i : std_logic := '0'; signal ftch_cmnd_data_i : std_logic_vector ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); signal ch1_sg_idle : std_logic := '0'; signal ch1_fetch_address : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ch2_sg_idle_int : std_logic := '0'; signal ch2_fetch_address : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ftch_done : std_logic := '0'; signal ftch_error_i : std_logic := '0'; signal ftch_interr : std_logic := '0'; signal ftch_slverr : std_logic := '0'; signal ftch_decerr : std_logic := '0'; signal ftch_error_early : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ftch_cmnd_wr <= ftch_cmnd_wr_i; ftch_cmnd_data <= ftch_cmnd_data_i; ftch_error <= ftch_error_i; ch2_sg_idle <= ch2_sg_idle_int; ------------------------------------------------------------------------------- -- Scatter Gather Fetch State Machine ------------------------------------------------------------------------------- I_FTCH_SG : entity axi_sg_v4_1.axi_sg_ftch_sm generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 , C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH , C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE , C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR , C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , updt_error => updt_error , -- Channel 1 Control and Status ch1_run_stop => ch1_run_stop , ch1_updt_done => ch1_updt_done , ch1_desc_flush => ch1_desc_flush , ch1_sg_idle => ch1_sg_idle , ch1_tailpntr_enabled => ch1_tailpntr_enabled , ch1_ftch_queue_empty => ch1_ftch_queue_empty , ch1_ftch_queue_full => ch1_ftch_queue_full , ch1_fetch_address => ch1_fetch_address , ch1_ftch_active => ch1_ftch_active , ch1_ftch_idle => ch1_ftch_idle , ch1_ftch_interr_set => ch1_ftch_interr_set , ch1_ftch_slverr_set => ch1_ftch_slverr_set , ch1_ftch_decerr_set => ch1_ftch_decerr_set , ch1_ftch_err_early => ch1_ftch_err_early , ch1_ftch_stale_desc => ch1_ftch_stale_desc , ch1_ftch_pause => ch1_ftch_pause , -- Channel 2 Control and Status ch2_run_stop => ch2_run_stop , ch2_updt_done => ch2_updt_done , ch2_desc_flush => ch2_desc_flush , ch2_sg_idle => ch2_sg_idle_int , ch2_tailpntr_enabled => ch2_tailpntr_enabled , ch2_ftch_queue_empty => ch2_ftch_queue_empty , ch2_ftch_queue_full => ch2_ftch_queue_full , ch2_fetch_address => ch2_fetch_address , ch2_ftch_active => ch2_ftch_active , ch2_ftch_idle => ch2_ftch_idle , ch2_ftch_interr_set => ch2_ftch_interr_set , ch2_ftch_slverr_set => ch2_ftch_slverr_set , ch2_ftch_decerr_set => ch2_ftch_decerr_set , ch2_ftch_err_early => ch2_ftch_err_early , ch2_ftch_stale_desc => ch2_ftch_stale_desc , ch2_ftch_pause => ch2_ftch_pause , -- Transfer Request ftch_cmnd_wr => ftch_cmnd_wr_i , ftch_cmnd_data => ftch_cmnd_data_i , -- Transfer Status ftch_done => ftch_done , ftch_error => ftch_error_i , ftch_interr => ftch_interr , ftch_slverr => ftch_slverr , ftch_decerr => ftch_decerr , ftch_stale_desc => ftch_stale_desc , ftch_error_addr => ftch_error_addr , ftch_error_early => ftch_error_early ); ------------------------------------------------------------------------------- -- Scatter Gather Fetch Pointer Manager ------------------------------------------------------------------------------- I_FTCH_PNTR_MNGR : entity axi_sg_v4_1.axi_sg_ftch_pntr generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , nxtdesc => nxtdesc , ------------------------------- -- CHANNEL 1 ------------------------------- ch1_run_stop => ch1_run_stop , ch1_desc_flush => ch1_desc_flush ,--CR568950 -- CURDESC update on run/stop assertion (from ftch_sm) ch1_curdesc => ch1_curdesc , -- TAILDESC update on CPU write (from axi_dma_reg_module) ch1_tailpntr_enabled => ch1_tailpntr_enabled , ch1_taildesc_wren => ch1_taildesc_wren , ch1_taildesc => ch1_taildesc , -- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) ch1_nxtdesc_wren => ch1_nxtdesc_wren , -- Current address of descriptor to fetch ch1_fetch_address => ch1_fetch_address , ch1_sg_idle => ch1_sg_idle , ------------------------------- -- CHANNEL 2 ------------------------------- ch2_run_stop => ch2_run_stop , ch2_desc_flush => ch2_desc_flush ,--CR568950 ch2_eof_detected => ch2_eof_detected , -- CURDESC update on run/stop assertion (from ftch_sm) ch2_curdesc => ch2_curdesc , -- TAILDESC update on CPU write (from axi_dma_reg_module) ch2_tailpntr_enabled => ch2_tailpntr_enabled , ch2_taildesc_wren => ch2_taildesc_wren , ch2_taildesc => ch2_taildesc , tail_updt_latch => tail_updt_latch , tail_updt => tail_updt , ch2_updt_done => ch2_updt_done , -- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) ch2_nxtdesc_wren => ch2_nxtdesc_wren , -- Current address of descriptor to fetch ch2_fetch_address => ch2_fetch_address , ch2_sg_idle => ch2_sg_idle_int ); ------------------------------------------------------------------------------- -- Scatter Gather Fetch Command / Status Interface ------------------------------------------------------------------------------- I_FTCH_CMDSTS_IF : entity axi_sg_v4_1.axi_sg_ftch_cmdsts_if generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Fetch command write interface from fetch sm ftch_cmnd_wr => ftch_cmnd_wr_i , ftch_cmnd_data => ftch_cmnd_data_i , -- Read response for detecting slverr, decerr early m_axi_sg_rresp => m_axi_sg_rresp , m_axi_sg_rvalid => m_axi_sg_rvalid , -- User Command Interface Ports (AXI Stream) s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid , s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready , s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid , m_axis_ftch_sts_tready => m_axis_ftch_sts_tready , m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata , m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep , -- Scatter Gather Fetch Status mm2s_err => mm2s_err , ftch_done => ftch_done , ftch_error => ftch_error_i , ftch_interr => ftch_interr , ftch_slverr => ftch_slverr , ftch_decerr => ftch_decerr , ftch_error_early => ftch_error_early ); end implementation;

bsd-2-clause

3b66ab27886894222a34b63a66df9615

0.358108

5.123562

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/fifo_generator_v11_0_defaults.vhd

2

30,145

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VX2fgfoQjr0QNLgHtDA+gIITmlZjMeot2NAaAq8LF+/WAkN+N3o/LK8V3H4iOAnacmZPDgnWWfzm IUXrGKyjKw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Jmn6FAdhmXuakV1kTd32dofEIXYMcQ9cNEIzCNULYtezAbv2IS7t4diEsuDDZKF0EmcvqgeZSIrG f6CNTPWlu6hk3H3ID/H9g0ADKEboCgjiZTAlsE+veN4r299owuDQOINMnpM4lBq4lqrted2dnbAn 9Yov+e7Asr7nO4ow8Bw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block vIkoPFwMna/K/3APKoT8OkCGwY8aS5wOXk2HwY/L3U0CD2AUrdRklOmxKRAVqmnB1C+l/+IoVP6h uDRnvcM4ByHLceKnY0rjNmxCZcyyAjurVPSudafpvphGND7hRdmk9PXJIgLz4rF8cdyRn3bOCohF q+LlgBJF+4PL62sw65KIEVS/c4G3k6ddZ77kQM/QpfmpZtU/7/DVzvR3aroaA6azvMv/1dfiQ9NI +UFZ6byFvMruf9kjGOStMfAk4V4RK/MwaLkRG0RFL83Df8U5CPD71pTIo6M2m5bnhg8LieS13JvM LyKBHRLrvgwQ5mG6OOUaZ7m3p0FQWL+yDjxxWg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block idChZ52qZGvxILHsTGTJHJCf52mhXVsjDpZGWuPMBhXm0bmHXIL7RtdbAWzdUq2yMP+dXiLXNQr2 eTdPsVFYQG4+I1UDOd3D4o1CmiO3a7DCTnuXfZU0gAD/BXT27uh2KDjHBopm6fE9v4Gsr6Vj5m97 XBa18Xy6PBtXyDBOks8= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block kCVpP0tZR4WjUyX8WXquJ7D1cmQMvhKl7iHiuzOG5Clhm7h4Q5aDg/Kcogvyo4eqnf6OGvgoyVxX uxfXWBMMTWs1QPmbCquCUZcw42hFsR0ywYtZ2U0fe2QUGY8+OKl/8/nHmaL2QZ/aHyxG/oLyh2AG tzhWt+eu8mMfe2pfDalb8haDbCATmLrYIqR1fyxT9+KSOLbcuDMhZt/SxHdCyMHNkMbRw9CoRcxd blmGRpUXewmeS5bEaSCbKAZcgtD4K89QwC4RMgPL/qk9ZUGzwH5taxZTGAQ4DjjA442eWe2pjduc IYE8PP036C7jzixFppaiMZBtTMVMsy74OSGyoQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Tr8hnq5qS15FRuDmaCMTXd3zDwsXudCBEe9DijbS+S1mc9Gv8nyFsS200zS/r4KN6dloZjDXNVRz 9qodpfdWmpWMld7MmCeGKFD4wytFajjYd0d0rVI6Byf00EtiFeoj1ZdLeaGK7LuhFJiUVkUQCsO8 nwuTF1SGydat/QYY9M9sOdZPfEKKYaJvDnKyGk5pyieq18Q5gWe8ykvsBfLyOLdjIVm8boo2u0zs BWeBltnoD3abC2rk6yA7T+D6MAnoEPJmeHqL6xgWJOlthsxGmvndGKssN27I2h1CxKTGnOO74KO+ k4nF5gQfMUrkUvbTdNszVgdqdUt/GPygPnzXJf8/iAnMyLzqQg+YksiTUirgEYYFlGmJmGpOADYv kKLocfol2iYRkqz+sQh2OUHlDX3qCR8ZBZwg/6m4ieZVag0xIIsmtHjTFWlISsjAEFrONVEG0VWk mDDnll2qz7cYa3eWk78aS5/W8Vcfm96G32jVDNOfR9yl7aaowOaazLhNzwTZ4UBH+mb3vlV8AJHa qtnYp0iHCo+7aTNTheS+BwBGvIE57Y56O7k9xCuuJlfnE6cn8AOo3ksXZ5Ihixk90h04k40aT+zn NTMZw3EtcNXqLkqWaZ5vNoI9G0o849iR22eUdONHZfnCiI0oqATauK7v8zpY1KseEybdKyKjoU6I SOFfpwn4rsoEk2SY90Ympe3agVdJxBh2X/wkDE63EDqcVjmiBTnwja94LhHruKw69Nl8QRAJ5s/t uD5UPmoMV7zMl/eNa3uz6fJ9vGKTIqnb4QyoYZeMVoM/Y5dI1naCapbtqO2fx9ydnfPjHGKfH/JQ ZxUoWrHLrOK0pYxa3pf+TVCc/NuEmeL3C46wByMT5ZmKNoXQmFoVFhwi2ivt1nPdwZ2JutYYBgOW 8sbUrY1AoO2gxM31dXKLMge/wIVHeKYHq0161iFY8UKPyA5nDv809VgEp665FJ7fqQ+Jon3g5Mvo 01kWLLCl+djbBnFzGFCJzu0/yQoRQ4SCvNWIObB4MBWnVNBSifZ0KTIQwNuqyLDv0JdQVzb0Ka6g T8WbhwMi2zpjGamSdV6oZLJ/ZksKXNoSD2MFUsdyZgWt1+uiOuUU7iatDPL2EHIQQ10MPuB2tNoV yUod/TbbOcpnwdJxjbwEFVs5pXZSH5L+TOAMCq97ZMTAiVNDTVVcNX3c6xk2Z8XzOTi2n7r8YjKZ lOzw+VgeN1IFPXt1T4eDobUApXffE82nCxXT7/I65oLQFXXOMTUibzwtJo166WVRzNno2kt10+eV iIHUq1w+latHrRPa9Oaxxg+VbObKUH5HKhn+HxL7w+T7+fnp/DdbwE+zX7nk4DqTf5tiIVb1Wxce mbCkH4akB0nwaXrUWngdwMiOlkU7JWzXdW9Z9K14kjykqRDKh9AhyZFnK5vvw6gjlt63IbL39u3C gZU2H0F8eT7dqa7yfnsXVQtSph19TTwKPMjcCqlV9c42vpj1hmU1YdyUZNEa4nXCSkQauFxz1fbO E0P4kLAopwbFu0QiRDxbPqayredSyKGsVHokw4E2ajFtZnNR/Jctb44Z0edNg16nk22W//CpgWSS /oqsntzZSiwi5n+r7UZDOjJvaEVD+CJTOcqmL6IfakmmxPsF9ZLaIwuuN/C5C0Y5aBN6vTGe4XUD i662GefLECBz7uYUtmbgF2aea9kqkfaRM5VLk5QnjbDkTKHkT1lNE4k14vuufEG07yGBMmD6pxzO DYLDxaH3iDG4cHvULLPmGYjf2fqqotxpuxPmqSB08G6znVkkRLiutj2jg3tzFyG0094rj/VgFyQI NsFcnlxg61bVfVOOPsUp3EaVUBaAuTmsKQkp0xri5KHM+ukHb5qi0/HhmvrWenF2FJc0Cd07j3e0 Keg86Mf/88N9KNrCzkbvtPNuulWJ2cspXGouCbsXlQR8V/r/S+MEnlhLf8qDcEgKpF+xWvtcGCNU PdBaxRGObZmy1WZfZiTxB4oXJDB68FJvyAIrMY1036f7a+UReB7mkwn0PsPkCYZekCb+q+I3qHZB MkVPhvLJ5lfVuS0RdDpjFmzRbAGr6H0u0ZDwqoY6hXkTqlNzpWjIRY0Lwb/e5qN0aHC2OXcPL5qL DTL+o+IDA85zlKh4WRITMNixKAscZwyq7JGQzch/93QeRQ1o9UnC8mfYamFZckZ+95HlM1kd+x1F CBLInWjCbMD1Yg1zemmTAn7PRdtvHgvSj2Zsmpzqs8oPidCgoooDL4y6kCET5hW3FeI9DIg0wn8G HQCohP6H7udUD2Zk2n8WrctcbH5/h0t+jBNIAX09nnSbRzDWLadOPnj3Zw5/0bXuz1Ljm+I5yuEU 0v6te5UtsI0jR+kgFBoFPywyNLL7/KXfLt3aGA/omZ88WA68HYRcd1Vv3ilcuPVkYMznhtxKe5b7 7AvXcpTqZkoyB/l1m3Dvc5NZ445EOh+ROryr9EGIzCDrBXygjqP5xiA0IxjOivc76IJFLeIv7qty WA6g3GgadR60Cyn/SPnQ1Nji4WqAT1u4heV6zIo3HIQAu24LJ+Mn2gAfuIjdic2FvSCtn330BISA VhWQIz1Tdb4chILn90vdbjIIDFhT2hWEl6kh9cJIARS7C1wvrlnNWjnujNDZkXB4XxT+8VlyWXol q6k8EGInVAq3oJq5upq4XBc/EIBY1rcNkgOpiTUeY6BzIIGaHsln2jFm3wzgtdBQvSG0kV+FKsXb dVNQM1895eRibrg1bqJ2XfWHJlT+o053Fl/Fok5CpqAnou6aMDphD0ovfjFJWLoNgh1CEaGK5PT4 6GoXZ/U//+/0JtauGZ5+64qs1cPplXTXIMarprWGKhPZutBWKaFWLOlLhb0s8fHZ4BmVzUkNaADG iIDfqzPNgDXSOTV4G2YOLpE+8nEnhj5ycii1cBx/dPWDyfN3u640U1RuuWi6vcZ6igIk6reLKeu1 HjCYJMnPQqcAGA7c1FHqk+4iBXmAv8BqJABtvxNiUjufl44DfbEQrJOWZxFzzyLO9VU1R+AIc911 VGdsaWrRKmgoJBgX0XZaxvu0k8a+w37GUV4Sf/q3zd6s4MI+kFpxOYRz5viqag+5AgXjw3++OeyI uo4GZKj7AAz961kDsv2CKasp97NiYZdri+iMbc1pz2GEJCMFzYHBD9/w6ywNT/UdnYhYtqP2R7GK MMgSNn6WSKu5vZOTGT46+T1MWZs5wUp2/HYY8Kcv9s/8lvpAO3Rui7qPdTnarWXKSlZzRIteqxaS IjfB3ZbcSZobJeEZIf+rrAPW3Jf6ZDQIbU+GA8Hys7qyNsAXS1qHiOrq+Z8nBosXE9djaIoo5xdJ xzgd6L1JKLS4fW8A5rks1k2SkqLovvEME2IcmIQpuHzAeCx8wE3Rk8pS2iwrO73uDBP/xVXC1/WU ZpzMXz6gPgZ4EWmrSScQSph8trAlZLMmzObrSbjEW0/SOa6ZozMiWaSbGJ2udhmaZ55nRsCoaVks ZXV6jOt4mhGiS8bxYF084v+1XTbbdndxoQ8Vsrvh5fNK3g+WfouwnHytVPtpWGpTmhgzEZjFzmRe E5i93nVPvz+pNm10OAH45EN0w0a9o7m2lyrpwx2FvKUalcbVMOVmOd2BqU5HlajjtEGwAqPsUpVr B8UeIwaJXjV2cYA/0Rx59Q4e5lLiuzDHTY62WLyY1mYUVW80DsfSPYNqUJ5r34EpWHZPJvcUWIHe 4zEA10JaXwwXvTWN4aLGOCww/2OmoR2E4UlZW26QKWUnkrE0LDL2sMT60UI0n8YdpN6SGRhwPuCU dBc5z5UMl+YHsoFXNpjd499BVu1Zkqm35cR4e3rZ41XDCmPp1AVsf48vpZHGlCQXHIargWHnNdTR 8haLEfN9B4Jf5ADxju55dCZEIBGrTyle2vZ0daAU/bfM9ryIITTGvVgetS577EYghQf5L2uRmOlh uJyOa54UR3Zb1znHk9X4kLg8DUfQbWd0JK5Dvx2db0Wk1Nr0NepGTvWLTT0IP0P1UhFkovxJjrle rcmhSdiaDgoe4WYAjWFz8g+ihCPMW+7Oexrptw2vgcyRQ2PhCsuEgMj4wdsZFOJWK92xYotzi3SY AqkmFH2taklQdL5I5wujkI4NP+Ol7bz1rcra2pKo4vdkiGdtUdP1OEFEmCqXBz5zjxxEfNEM1KPv HSGs3JwRMk0S9+RVA3sm+WcJIOqHewMWTs0djwSD4VU3pX6B3n8QU09jrBC5JHZaTPawpQln2VgH p9j6QBiZ+Tx/gPuJKZnmo8OZ0v3lQRTaPS+gidCjE2DqUrGa9OuQAMt0FPT0efk5g+b+h6z3KPWz dkDhoA6X1F1zEmQ7YLSNUZ01BTycICi8jPSI9vTK8D5QtdasXq9C+sS66yRQS8mDFoBN231Gp6P9 dny9cAq3lmnjRHxW2QJpEavhrkXiV1QekfkOl37YUXpt02PzSbsGaXWKJfuBlBgGKbH4Oes208Xh PDMrX90O/b569OmMjOpboadjl97OTgwKjUAvvAqHsBY02jt+T+cPW7XwpAaGmQ3EjREazrZAxmTv HsJ0d2NnJGlWfQBDjYM8LonO39Jly3gzaCBbSS30AbImPvlvP5dT26ouarGqLONc21B/xm9tT1Lh r0oWaI+szwmppHmaXgBNNDDBvMHLZy00tXxTSx92j9SQjMbcdvP5OtmjKLtoFRbBCRQT6vD3JRxe n8gTk9GCIfcKAhK7MJ6n1CCNPXv0V5uCUDmbrRmzXv9jZZ08hWnLqgCu9yTMszAoRO54DclXqodw c8cvDvnq+1CBlypNSOLskj6n+qG+DMgQ/2q/vTtAAtyufZRT83D7jnssQ0Zeew2UDlNJ5/UdvzsI fvDV/sfaiAwYhzZ5CLnCU4FySa13pOmXBYBDxanC0ttMhukdpRGy5jUjl32gMZMIg5l4kXmglSsR x7gUEE4vOAfWv4PjKgBYQ/us2ydr+2ET4/tbTKPFxxyfPl6pIfif+5MJa4iyGMVSbMdxlX7ojAI1 R/+PsrCeOhWwjaD7U+9KP672h8y9qgALEGRjz7SSwVG3t3YfIHJoEjh18EFzD6u3AGEnafa+381d 4SjBNFCARKw47+ZiVlK6ewtPjS+71G3qtz38GUkotHRN8QiJQveGOJDlOAh3FPO7z+ft8Wr4L1C8 zVL2Po5MMdOvmihdh2274TMu2B2EwdXOfdc5wOykb/ZYuGxTHljmUk5GWG/TzDM6RmeEWNSlztDK GmI4+BI/ywSR9MOlhsAV3lWqwBsZ067tsmcJ9sAHeztDYDjuMbaDcQWbjP2eyVu+YOl8XVPbDTVy pUb56dLf5WExTPoVEWhXYkGQkzkd7WAnXi8KLB+4b4hcZL1JN9RoRd9Hs3Wd5Q56Le6gm3+r+a2O 15KT9jvZVCX7UYivzRBQFeepmvh7qJF5tQZgSyLF3U6+fQYg5cUUM4wnIHrWm5aafZJs+e8+uCfh yQY5qfgGoFPjF15Ipnt3WwjfFNFExXqV3hiwZXLWkV2pRhWAgnzYQ7wfJKgJHs3cZwinPaqK/18f LtSRq/DaoONtxOhMB31Mj4WNjzvGFRikJA0LVr72bV04cDnm/xdI/xolej+JQltPr8SrXAsKR33d bi59BgNbZwc/3lrc1Qj2EIfCIdrqv/FBjeV4EOo1ICfkgOWW7tpnBCOwgUORS8iQc+MjC/XOlRrM frklPC6UqxlGgwpo/1YiEaudXUSrmDZzgu+u/eQcioeUe/G6uTb7GVHrGYMtfJeakSDbC+ijIRxA UgqP+NzbaiT3bRg3sud8HXp+/LKYDa7hdzyY5o97Of2LLLS6c+1nNnj/aGHJrmYtpKcE9U/vqQUT AJDUI4np0FJvvertzrOs8N3HikEEW+gdu1i6Tow8Dq7HRbk37qLtgXoGsQQNwdi7M6a2IBzphDVu RNAYRZNsFX/V+CN6604bSYihAd6RsWBHpB1Af2bnWwihW5REsTm5BbUK2JzY6BkSs8YyerFHDgFw rmdOgM0HpjchXLknPKWIhGxFilgbDMYDJAinTcK8MoRkst9EAUkOvTJ5GkYWmL2LffVtqUtW1eHl SMbLL/Cbq3e75muBZE+t8QFjdJpq3Xt+TGpZUYUXFTtLQ6YG7nNKuwZgDE2Cq9HQ6iyjgEd3jJ9w 5ZfQ4pwFjYzEVBfkoiuol2iWjIu5q8bCGt9UE9v3Cp3nIBcb8SHpl4rycbpGeTSemppCpUC4aBw1 HwOl519DKdOrJ0xfYagyGASwRe3hiyw24tGpijpLE+BT4lAcXqj+WB9fEDVwGDtkEuJMe5ISrYxr W63CugBNdmfUgWWLSeE+ELE15kNAMsUW6QNTj+1CjXiabr2lTaWs/jRX41RWOmtcpN8R4AyEjkML I6XqdAdDlfoBrphL6bdPfIWqupfgmW0DUkjZ690/iNWtal41xj9tBHwRdyz/eDePYiGGf4iGhUcl ro+9ZKV0lcL+8rFn8yt0lcvOJtopLsBKv4CmSNHX6tKbg3WX795eBKDgFgdJ1emN2M6NqXrDHPTc ePYFe3OSt4gVxWDY4YrfR9Glkzy1XcGUba54UBfLBEMG5j+fqkAqUJOWNERp82h4cOIe0G1WV8Gi El3rwitqRsfMu5GVWMuzyjKlE8G1dZGJGx0lGbMvulF/WZzwPyKnXdsvYwhAvBHg7NHjJG6HApen 9DNHS1BSeDkFHNfWuEMGY0ziMPausLvJbzllSNyySpgER2KK5J41HTxKMjdEuureqbf+rZ47xWRy WU/HN+fEcZCvdIgE4NCGW4COXBmufYP4QwiZ6DrylkSXhLxCjnW3TU/eb5vVOvjF4p+edLJhLa5A 5kVCbRq7s7fKVJG05uZBQuu6xrRmzrfwg6qhvTgumEWMs5h2quAgYOBFvY9zX04esz/cdBRwcsIG RiKEosSB57rwnmfGDlrP/h7rpE/2TrN7Mb9Fa5LnPQ33eehQ2VsQF7ntqyW3zsDVCSATGglodFio xwDL/C4/EBvQnIqDhUzzQLdMU5Ii23hyqvx5dXwiolI924M5SyfFcp3ZYH9viBpjHx9hpHTTRGOl 4VNR/NepDW9GndgvWT2h/TLQZZkIAUAYKx+1HjCfaLYYTZRNq29gRctuEI04pknbKtotgro9FVZk tJTH+eDTLnO3nELeqZzbf8lCmpt0l71uKvOCnQlraDTi66IihNgoDoOPMYA5orzObhVjBUrAQDk7 GpvJ7rPxFvqi8SFQcF+fPO3h7hFrpo8OCtwV0mN0L77WqTthuZaxXCfwA6Eq3twG8M/lvgiC/lCJ 6k9gJdTo1zSSCEHKOEL7MlDi2zKWImIx9PUY7CQre2Cd5NGTLXHyuh4fd3eH9ND1kBxEYfrQywe9 Yx3lu3k+GGRc9ZR0ivCqxYVucUOGvQRVucwMdvIcJzNO0s8Sih75k0ZsU89mTVaqpzITt2n19b8N 2DQ2RPYxH3H5FJLrnECZHhLrAX1oUDoHiUpni6NhP7uOaZQ1I7zNRW96wVJSSxL868LosheTcC+x 5pHX1uo4Y7m6/Dq2y7rIUyAW7BdMJcg3QOuoLRo9Smp4ToJkSO+dOzH//JAge1Z+oCyNFonI2Umk IEWZT6zqfMAKfDw35ds7fBggGbeev3lQxWkjNvY7k16vnlFMvPaMyz/BFgxQTKJ+qKBpH3S5svz2 7xiatr3lUZu8ymW61c3lDShJQzZbhfwmHdmhk/8BgYnDbBb61KVVUGMgzpKXMAmmwdhHnTjyfHT7 mABDzXPnd4z8UYO6Edm2guDEpL9GNwUAbYZ+6hPcmEak9av1V7ShoJdU/MPFTe9u8fVPORbtAFgU CLgs32Q0FiGEFmBfnV6+0iD7PgH2q7HhT9EDuy/rj2qevfj93U6vMXCAFZ6dqMleVyAuHu+/d/1q qsyj0YQuLYOrGBRIrxhfDe+r1NSsbGaTYJWMAls0tT8p+QyKcWn15vZcgNaAoXSHQz+EijJ4hMg9 XpuVT13YsqPKLBuiGRGpJK14oVlC6YhJT2rjBg9HT+TJtMQCUEzLTiPLZk9rsOrJvUQLLVq41C0x In8+DunWbVUG0dMxLkXm6eZY0BUW33DdN4GzP1sEONRt/K4g2lHITyjZbGOR3QjVu31O5y9U7xJj R4J7U57Fta/fpmJAkD8Od17vlcO5iylATTmptbZP5+guvLej0ivp3QByyd3z3LPzLKIVwt+5q8jM ww8oO3w1bllIXTcL9mSUPq26acd+yfh11NqaKuEzLlZlfTpuDiAvjy2cwYTADI960hcLOazKdtuf u/tsWL/Ch754hbcuiYfYfqwJOSJDqM1w4Ztft0T0YazG/0QYPx0Hxi0Qoh+c7zrJpBfFQTMlnNLR BcvXHesL4Wr6v97exHesxFoJ07IOts9/YPGEKK32IpBre7aLsS4j1aiKcsgN1V4W+PqRaDghZtGJ 631J/4SHILVm1KeXAqbQW8yYJNyXyw6AyCfbDVO3kg1/ZswjxXglZ967QRBF4mrzAfVY8VzZ1bFD Lfotf/gzRDjqVFgk6fF0FcAmqYFFrKJvuim5Y7XyT72+7Y8+Pc1fCI/jrnJnFd9QbeidN/aCRSUJ mmF31PNCuCQ7U6ddAWoGkUBDakmcjkMOYAqt64zRqiGqQvx86qJE2eOiFlc5yEuhXZCvFTfAjr9D ag7IpVp9U7nhkfReiniivy5AUX3HNT0Z8zu/KvknI7/JNsal9Y/SPyjaT8wfHSiMc3KGKULjA1O1 Jwrw5kqNIw02AHLveNqZUU0ocy4lvdErbv3l7ngVI21f+nAbOc+b4nurdaX+sRJw0ntEM4zfK6qR C7SNebFLHB7Vbels9MiLqK/mXBlCVY6v8WySlZGoh0CcLYf55h7QeP4OuQVe3mo/WQd3q1ACihki 51TVaYoYVCxSRb8caNiyYhOFOxBB1XeMj7sZJ40Bd997mfmsIfl1STHsSuP6fAQXvPCFg3qUcPgu UVwCuRCmKso3zTj/WRcPS+EVgDc2BlP/YyNhl5hob1FE2MovsQC8YX/Wk1ihpZyx/jdIGlIG/oMf EYix+F0vkKiJSlC57rMbGaFisyu/k5tPpJQSIFzEr82rJPJFsjnsOXxWKPGyEhAjEXzjmT3bC0CO Avj1zYG/CNJWQdraBAS4eztTdEvvc1sd7UBdDXxOTYmfIH1FsE7lUtlO6O84iafNBe5XrpN6SC3W EJIPFqipfFJTh0ia/znfZIG5XYDGqy2FqgDOVCqzEdF2nDf8BtsGstqHhDeFk6Lcr6EXePtRCiPS AAywmcXXohstukJsdi7Hf3O2EvvWcgH8eK6wyNSBoBCPbJIU1+ZTXFZZ8IcGPVAeI0OQaZ7d3oUD FtxCDasAdpeJcDnuDy+YQiWf/tlSXdET9cvYR1geZCR0ZKQxSc3ZVqSODCppIkrQTOC2UY0l/6xm 17Qw6DQVY2DjKZ0tgrkoBl1W7NarUiMjdFOtqKTrN7V8CAjF0vH21sc339aD9noakrTi7ELizxlL cpInmnMDK8oAPpD0sFh4jHqwDdW+/5rVJPzFYTY8OincaS8plA2DZ9/RQYAYM54s+Q+czrEITnP/ baOmLR8g8nvjPPTwvrqeiNu169/nf+EX2y2TPpHokySO5cURVDjIw6NbmXeg/K17Sb4qQ4WBFdhn jdVmUWsTfbCieTFDfGSi0JM3tjlQxLTBIldcyz412fRjn8eOhA5zwmCxh0Yg4j6O3XrYmxBN6mDs 8EBuG/IwmDCNI/+mk5VdiwTF/b1jzZzhRP/wZ1LJWLN9avuZyxU5w0Pjgs0x4IkDE+/F60EKBOen BTcOdRt6q/Zyk8XPQfPufHcEr2LlZ4spTiIGND0G6tUkC0R+QglZmRRlfLYBoAlBeUxYFWBJpPEm GtLRYWc1hHo3NKR+UokGVJknfRDO3ykiBzsdgyaLYRkzWqcpHEJAql8mZMTOw77Z3ej0wuWV6ADG Zt4lLkrRrbkn4J4fx2+ZR29/Swr4DQraR31sKJpZ/EBpluEV/8Lakl35Ret/KhkSV1NHcl2aqpxV 9vkXLth5nHSgff4gGBkaNDcMvY74r+7IX9E5QcO/PicoNy2EHWAtkPfxCuoA+U4jdoe5T+YHOelM 2V0E6a4fLsXh9Si9i8aooOEu9Stdt4wuGHR9ilLZPISZJJ94dCObxTV8jronlW7xOJ6V0CW/6dZ8 GxSwpS/HxFlRAqer1sLUaF/mcgV6TSjPyYqf1D9MTBnmvDJYi/qZ15MjlP19od7iaddGh+NYyINX q/AmR95C+YIRyN3SyE1RwW9aQOmPTJkiRkJQ5JxWndVLVBeoPBMQ5hXkdINMhZHF9U/AK4IXZVqq Pr4E/YXVbCBKJN06brvBqIiOkoNcmhZLNwSLw//NAZ+l+vJHmuqBzS7+Gn1q4KwM4wiKi8Sugkyr Xh3pEpjK3AYKcjGKbJpI/DcTrQIYA/Oqba7r7hr1BzpLJQ4sCxwWwV4wFBylW/43/bUp+r8vDrUU PgLVF+2wxKja59Esz5x8kYetTNv8Wxd9F42l4Fg6D6lCnarYGS5UvPLmWpR2GsDXNCUSLghyvjsf XMG4Km7LllI6fkLHQpfMWvbaiZ34bDe3obK+EFUDi/iE7zoZwZah2nWtCbI/gb9aBwAw7Yz8pIUa 4QqFnDKxm0dBkxOdinmhDKb1juw5e75nSbXCoCUS/loVyM8FnAY7ZEfjHZ/XzSXGn7vPezSkLQ/T hJegcX1Vlb/h9GsAJoSeZusbaVurpdONxgSoBtPziP4HcadNcXdtudNplB3vr4nfI71jnL5pMtFD 1UU/HfqTjvBkM7Ia27yAnw+9yc09Ei4PrMpsxyonrKDv93eMgkdbMJ+Dl80grRBELE4KDdiZZJmG uBO5tyP/2hV4oITIwOhSKSwdeUJcsx4X3Q8cpkBeQOVw/ORxv1aVu4aFetIT7/zyw0aOU9f2QVAm aMLz+z6TUQz1AXecFR8AXDrw36Y2WuwhcA3ucW5h87hZTuWFnVW5YltHWpthgieOhUj2HblyJaeA wmifD1vIZKShga7f8zUUrjkisOEvramtZ1t94Gj6VvV/b6W80pFk+jetmV6B0TluI0FIzouLqF/w AxGpOpl8F9XKkWp3AT1UmOa3vvGivpGT6LE/MSvjH0bowICOyrBkdKhI6IVpZUUEbiD8TZ4Dr4Fr eLNXIPQb/u9y9wxqV3+nAe3CWxWozNpULkDEzqWmTHETVBEtKGOVCFZ6IKaVy7q7Bv3Y29ao0w+5 0BPjKmn8gK3IhLoFiTnRx2njGG+vBzUPu8KO6TnD5nt5DNgWSEUgCLVAQCQkAuXq/gZeACXTu1V0 bbO2VC/mP1t8taxIU7qQY3quUqAMK9SeMMJhZtjKb+k/VrHkc9NmuHJ1zV4PenwPTFv1khDhmWih ZdC65HQtVbrtR6Ud5NxM+gRaWc7ja8dQh7B3lrM8NyZpELqL6wPiNfjT33kIljw6fgESUEVC89D/ MwBHwysYYI9CJPVatynDiXK1TZOqVeobH5izOr0600ZptqhY4jdwA7ED8377rOHAOZQQcNDkAvJN Wd+FG0SBsZE0iPeeSDigKKvCrt+/cJr5OFzCZUAPZePp6j5Wp+dG97Yv0+EMHwmQodYafX4q2Xjh dtTdO8GnjJokp/3HYiilYD8fS7kDG7hBCk5BBxdftG0yZu3669JoPaIUJGjR1Tj+88U2AxWcKMgZ CrRiJhdsJcoiK9FhtkutpBXnqB1gUm6U6pL0supyK1ZtzMQz+CNvFMmDfKwm6Fi4sQvCOCuGnfXy JLPHYtTtTfsxJnfuVHf24TYnaKLZqKKLjdk9bdNlspLhsrsJ6mCrIKIPmMsuNpDgS+oUA/jWNhuC uszuqnYF1gtq3yisPujmAGaQLrJBTmgsle5HB9wQ1bw3ky6PROSNgK+FhtA3m1Y6dtTyFdQwiwfT UxKfdNKWEoUM23/UreZzbeSbktZXvkIcMU4qFSHcOJCegwdQmZv3gY1bEDjgA6sduDJa48Desusk lD67w0QzqxDrbvxhuZipFMHmjW6mJEok/I/0B0juWIuXld0T0KHS6Bfl2WUHPe88HSnEF6TL5qmw c3EBtOkhKhj6GLRMly+q1V44FbjCzq/PY4+SUtN0qNpt3Ld7R95GWAmDGgZ1nM3+YKQvcQsX3JyD QQcdr85Eu4OMyOc4xXz0Wb8eagp2/nWdoCM90nbsW8loZR00NNgKvAKBjVjJYz1CBtDJh8AZY0yi RBSqJ2S2nqTzzAKt6Wq2iq6hZ2Xro1NZDAz+DStkvI17ca3UqcZ4xoKSN1z/qnfv/tfR3cWo63lq 4R5h6hvwi5Y1H91Y/ZyDykmfTRFVPwN9fwSQWjdTqQrzgSO6pokFIngPhuImksc1YeDGsEaKdoEx bCkEFzeFsak2eBVABQWhoV61n4V6wCMySyUnBIx9//qIkAPz23cB3rZohJd2utby56NBWmENvIOy jyAIxzFf/ucNEEfkLgf1evSLA6RiW3l5JbruGIJqV/Giblbcl9NvgPOgT9CQxKZ4grpq6fcRw2ZN +X7FRdaZ3yCx7MEAvrbQ6Y5xXRwutFov7dX9XJpkSBnWrMXRWRzv1lJ1FAcnMpiH47t0lYCxtE93 PTUR7jMRMvpbgWtHVpzTwn5hzNbiZaJ/2jKHOESnOPCVeaqkbalzL4E28Xj2BAsuxOZgP2QUIaFS mjdsiEVtFM263196+Lbxid+gMKLc9IJWo3pYKFVp0t99IH7uKp2g3qeY5EZl9IqCN++8GX3POKPJ bqxmLqUZ6/Bs+kJbtfIit6zosr7Zf7cIOsYf90+/mrtvIrVNUSKN/b9iQY8DRAdB1kxOsxsBQedg tEs/CnpIpIUbeJz47/0uezt7lwwdxVUqK663ZkBUQ4BSNRibRo3KvGJ3epUZL1Sua9C2JhZo/Q/o aTnJDtORv/c6c+/60v2nrkLh9s+vRNmutjilvTZJJbykG47kXOvpKhY/SrfdFFFCduziiwDBgPfF ecVW1cf6V5e2amEWx+k1YrlT/32vQK3hSGMO2WPg9yeUsTz5mrFpQP/ymuzZ8Vc/QjAg/XsbsKvs q1tbPo2Hx4Ap23CHH78QTixbd2mxBddattM1NrYutH33R7l3Ls19j5Us/ICFV56xZc1R+5xLr8se BGwpCfGOWwTiuxhdzEu2wMgOTIwENSJDM78ZjpLDIo2P3HN+WqjuBugdXc58nI2JBNds1YJwrq5O vhJsvBRfkxU9ebVV1tyE1thuCHUAaToXznt125tw0oizqqHawngqv75JfHSsZGK67sfGRM2f6fC6 M1zUfgLKJSLwSFAwdImNn/MQj3OFihZn2Vav94BGLaaT/n3Iee9fHaICd6FQdeRCOdEykmmRp/du nOVlNiWHrpqy9VaM1IouN+POYMWi2dZLuVSvS1Ish1H1ANbZi/9mJvpXngb9blntMW7RO6O7d2Ad S9uGqUKi+k9GbRmm09zVBcZW+33b5sKSzeI9dLyoqu0B/5FZ0rjIiFXVI12YfnMvXDRm5bMWDfW1 lTiuSuo+xfgNa5DbN+KvN/FS8lcl8vGruMqf5Ra94e4T9V2gW5RLqr94vbJZ57jDDkTvqsMhWYOZ TIhMVHa5yfZyog7Wl4XYE4oAyqCHkyKq6o5P3ziZQs3dDTRBeabgmSgdSKHFwxolf6SeoaWMrcBG V6xKlT8Clv23cehGcrBaDuZP4Q+nhqBePxg0cI5cLph1xya860l96f7Ub47aqbkMJPUsjFmuiW+P zreu4srsag83mArw4VyU+1U4TdNv2KrPREs2gPP6RTQzxemqIiy963D3vADEWhtQK3nnDWmWnpb0 G8OUBZIE5OKKTjfzvj1/LLpfYpv195TaHigbBNye2l7jCOogKC6/5UPwsOsD5BqyiUt9ieHGHFtI ydB5u/0nj8h4d4dC42oR7Y/vKeSOaqM+UvqhKw6whIvwNCMk03O/ZnQL9RWr9U+Ph5S8W8sXRbb+ mj0ROTArMjDwpDx23/++IfJCn3gzvo5VeZZXAbBufuU01v5MKVIMcbRw/y3YFwn8li6RXcFSGqav VG8pKqtYjpMGCyATCroqnsaImuaT23W0pmhcI93yh/XrVwdR7ZvfjAwGCdovewgMutgQHZcDIo+Q vQhMnZkoqLNPD9H3uf6oEu93vfoPYsXSjDyaKpkWlBUORRW/ro1pyy54VR4dW8fryTlJxxiAV2q6 kELTzivA4qYdUA58n2Qa3wRCSAZahvRq+u5V35y4MbdAPwobZ2KeONqCVhoXDUmxEe8c6X7349V7 RaYEwMIzFEV8NUojAxGDjnzhCQ5445D3buDXebCin7LpQ+J5WiCWdDZ4ShCrk3p8cjWW9+ohJPII JnJcYp99BDrQo2JKW/tksDWuHYQ663YR0VvrEOjRzYREUq41WkNORu2WsENHVJCmZ6W5KcW6jWEQ ujDsTExUtYtidoM5T5+GJEqSnvewMhyEPxtVe2AETvkGZovhNx+ByRH0xoHeqnGRkdRIjsH0nYmz RlDVGPGjHPl8TqeREn+G94PwHOvI+fPoKDGjIQTZ4ff6ILAqt0CAn/fJrUd0BTtXiK+fc6y+3K7N +qhoQCtZyQdA6KAgShIWDOAnVclhjKFDfGCLS7ToJs+8s89+OhuUBii2Ofxj41NpKwbyDqxpqD16 jrLYMPDLBpuRcQX6SnPdz+ZM0eH9xuGKi57ApzNQTw8WfXmtYOw8kSJw95JPdBxqj/BbdO5rcSLO eKGYw3EcitMOeLMTN4IqNrGZ0IziPgbm6KNSmjDm24uBiZzh44PU9ZHDarQ8FaUbqnZwoA1VwOvb pnsQhYSvcHzwfKJLQfMa0yxybFW5cVdNlVJOaybYwjo1/Jc6XBATuithl98q1LZCs82tQZee/xQ3 YLXnoQanU0/Mz6bwfXkXENcUZFgEKJan4se0LCj4hnvjxKn3XMZrIT3/ZKE+aov8jptBG9qGHWJm W7XDBP7w163U64b10jgVOX++WM2lOp7PxWGteIJXh7yP2RtjP6Don6FHfPfpEhx6apQU6SSqRR0A /lF2IKAWPre7aCcoYQGdb9HEtrzIevpfMxfBAAH8SsZtbIDXQDGdtPA7GrNVwcVTD3+RpzfCbJGY EX6ZRncTnhmnUAw8QbYkntvOYC1c4Z/gWUwuCGH1Zg214MuR+4RoKfZs0bRa81TcoAiJGlx56P61 ydSk0o7DjqsZ6HCkhsEc2bHlXHtZ7IVKQg0xAsFCIv87mSgPgXvn0voAjTuq8a2XdTEtYLXx6Fa3 wYigREXBo+hzdrKyFM4TELyf+qlsZmO9lO7Zcn7HoX0wBvUpOmQbIgJc2sLaww3IFxIRk1YCj6O1 OO0K5lvj/QFvpwFZFStiqoGmlXKuAGt70wugbJJ/OVulEGzVHiph8ZTS+d02XRLSgPbz5qTXdDaE uwpy+ho1hP/xVZDhDd9SiINZUrqG3XGOWtuHcBP9kkb+D5NNnrHJVb+HuapwF5vykhlWcqd/nHP2 i2MNqPu+ZlbIkKojvpV4KzE2fXqrfQu7ZPadbnRMEk4tEMIcWA0i43qCA44Y97CC+xPjQAM0lL3o ltz7x8KEGnZxh2IbozIMtPQs/G4ePzLSxXjqk5+MeLIT4NB7wOENH4vyPc7+pbrthR+GMtM98nVI QUkha2iMbJJEwgySff9J2wSOFXGU8gsjwHeHLXaueBy2T1V8gbLfhmZQs9XoeQ1ixFJL1eNZCFJd EDutsaumeB9TLGplro4AGVdIBBuQrhqEITowjWylaRf0C04gT/GtmD+g+aGbXRvOkd4PCHX9d9/s 4xmUT7JrmErOh9cEmRclY8rHkhPOpsomckp9v6W2Psz1y7IvTrrSo2B+kHxNJERYhWTelU42f9Oa RfxcoyvzDEemZYRwCHPTy2CA2fucg0o8b86PeatO5F1lmgUq1aNwg36PuDWOqr0nygB5s9cOnpxq jEo2DAX76J0GaUyfxzZuYvYxBut6LWeKa2UmCggNYa/LLbrXAyFRhjUa4l9PJ8UrOCT04uecV/px usN7fRQ23FNq7GTydLXNggyiUr8owqP21AFjYH3P8yjd1ojuPEggEGAZJrG4TW6NMP8UcOt2U4fa xcOQfou2fhpODfwAJpSCvNomyjB1d1W2qE5wMFWFfLBH/u80dNmcb3plQN33utrAnT9/KRPltOIM GDL69ouMBOyISHiijsdabco4peYO/EUxcypSmzdlAMsxiYrTk8uAyRBS1iGLLQik0oLYf1S/9dXA tiPV2IRMFODfNboNNXSBUaPZmcLpoKZdUSVoUQULyJuLF6YFPTPN+nw7ljkGvax+0lgwUWFQRn8V 894WMkY/5uHxyr42lEJ26hNs4RyeHO0EddyAPhcRXL2oR/7zIXfue0rpTdYfTd4jO+y/KYeelLgf FFDYPYMPTXAJjOuQDXaULzfGVvhom8iOi+rpMgDc07EBzrRMoT93PTC62o2PSLDBkV+BHujh23q0 ZQ+CmxJkNWPhDdjtJkH4W9XpuNd8MHkDX6C/KZ+rmAAn1vlb69hIo6zMX0AW+cyeGnOU8sTP5czn S2G2XUw5xWdQz2t69/9k24OC0sYxdw0opN0ZYFoYyxajkN4zdaAl/9NHTgZCUBNhaM8b5WmfT85j btKZPTBpGzuqjgw86JzRyv8CsiiY2cLyed70wzpWUGw6NFyZ10hAWMKRhdNW2vZT4y67clmAwafj a8s9/ticJ4gTVZ1w8+94+PofzZODREhDfq5zJjbi/Q/89fWp0JyhmaQgJec4esZNxRalB8ufbvPv 6gAHa7oY9cziUr+4FZaen4ajCtni6GllYW8D9lwXYzWPnq4kBYNkp8PFlfF2AxPQ1Y7A9/OtCu4g VvHygePzCKMDBUDtIRaLO3yyZMQZQQP+bgEet1WmjeTOa+q05//EyeTbtqPXXYjVNhDAgYjatvnW Nu5rt0bBFdkriQyp60B5B5dp4jFV/dcfggZhg1XoBVdph7TYSQULUIbW1SbBVyjNMia1mAk1fkPS Y7+COyAR7qmOE9O6j8bnQAoCIYXLfXg0s6+gG3W4tmfkGvo9dHULn42DOnORuz1kIl3fHD5OsIpv uscrF9ja4xXImrPemwkThk3WQ2P2ybucuGoQ9uf2SwI4o0OfVp0oBTq6nTpbe1hLGiwNJEIlQmYs 4un16jazmXvveSJW9Pz4rjadzxxEktXXqSReWmVsV1aD9GbFe4tYYPq96CIs0OracLSdzMmH73JJ 9bP/duC/RCF8eXMEJ43vvz8mVczjoP1zy7ymcd1RM2D1rmMVD/Mygt5KYcY4JZKot2n9hphmerO8 XffpEKsVV0q1MldNXAM8VeEMHJxKgvSDXB6oFKwHOt2oJhqnXI9FDB2XhRLRpmRbJkoEX0aiylKg yvHngtgkMReCrhDZucNUBgm3Tsh2i5MsdmF8vMSApFQAGkIo8C+RKxvdubCrDWaNwExAZ/USI4yC SaarIfd2y0PtZNKUqEx19yvFLT2hhYTu5a94mOcLInFm/v17VjvI2VPs+3Fpuu10d+XQQJgiLTD/ VWzGL6dlEtAx7HDKcSha1WNxdqJTBNeGzbmkAlYEiYdTXj5Fv3WrxheG8PuBdqhu0Pbel2AEOI8g P9QA0bKuAyzXO15fieK/yVZY5pFxP1KnI3a6b+MtFhc8ljfhFAX5DPUO1coWuVhdQhqwJQs3YgpT poYVafhVQj27/ZN80pOZjvhjOEeebtkr32ZRCINmZVXIb1KLg85wJR3/GXF8NB5fHaUlDnFlXfpu bjMwyDQ1a4BwLzSZzXyLaLtkmnzOgcBrrvOMAEUtENOrAI7T48z9BzRAZs9ex30VdNy29XOMMlqr ui+FoosVrjUMIPy77yjthnGHrkr3aQ/wRpPIJaQeuXsPgIUFEkB/2KwNPnprZl7M6kcXK7AiUKE6 MQ5X7uhYrKij8gt4ud0O2LzmAK2yLku7H2cc9yf55LRN4ZieFWiIc2bRrTPQUetJuYAdUau+4Esu 0Vh+CuvYpQn8ulB9LVSYJyvu6QqcrqIKygWZ9YMxcpXeAejbhwotW6gqjg6x+nsQzSaO3A8k31L1 ym4ZtoIK+Neo7SaBVaFNSRMgUGBz8K0xW+8rT6VgiA49xAFRzEpPsE6NDKryLFZDP8+MSs3YyV1q euBUIdnn4qQP2bdM1bmk0Ay4ex9rtqRS2IPepFe2/p1OFCWgR9OAT58hhtOWbFl4uFsurtP8yr4R ck1PFpvYzvNeJgKcYBoIx6QOY+H4X2kjx6KkQc+xmq9UrbZi8iN4JHOweliSb3qzlZ3FGZlRvqvW v1bjhfsExf3w0M1qWene5mxw8zmteDjzzwKbADFrAcmvF+WHWkBW2iRvcoa2at0j2wOonRyWkkzq qYbLvtb8BRuPa8fMkoJRhW3KlOtslHcEDsjqVnDiERTUrDYhN9gjYtEn4NxsKSPu+GrIHtxlrE0w vFK9bQX9PhxeJddzMnNJHWdaKD9Va2AFZFlOsTDaDLbaduXgzuqNlWg2+XwBcx6C5Cudsmr1Jx3M TSVCgazJJMygFRySH1LodfKMRjoTqNFgp2/uNvaKRZg3WUPWsB1JZpb/CiO3qAlRruPfZ0aKGavT mX7SYvg2s3U148Cqv6URGJ38fHLAEtyadMs3MgHcDp4FgayuJqNkJ7tdhsCiw3dFz7dWg9QWfPIj NCP2wrOuDTN0yFg/JyUdLh718zF9A616UwmVzUnEpSlkIiooqUOYVYx0J40ECR+RaH0STBTTwT35 /5IYxujzB7otdpANieEo3N09vUg0vBU67Wn3APv7DatkpZQ4dHjpEXDwWdSRgbNXMUjGe5YxqcxF 88l9jLVlGsIS0Mhaha1UUZh2AYFLtMlOEHtZWTwa7d1XtH3unJK8am7bsZZw0apBsAX9quAOAWiZ r32GeenrQVpAI+jS3zzzNbJwRLxVjzFx2kQHQGH9EDhmQ2mqS+5r6c9OYgnMEA/Ic8ErOo5j1p48 wzYahyUzyJwNENUbmaHGi1Pt66davD8XEuuqQVs0eYshKFEkU1VqJcMDvOMCH1FbCgMlYIdbIUWb 5mvfd7vq+0+XRKK3/wx8BYXj2lYq4On8N2Vw5FO5ug789cGwlatL4eNGtDHUhWS1Lpg5H7PlCr9S 0PHFJcdk9naKTngo+iQkidTGHl6r7Qllu+tIxJHvMX+OvTbqN9e/UTUGkkjrB5UQRAHQ12tkpCWk RFJoMWQ54X+8Jp3xQLtW/fV6DyFyd0P51Zo84IMVwTvvuCz0MIQgG2BRMQTX/GISr4KAQSskUh9M FEgVqJHAX+HzN7teCAVjqgV6/MMB/VO4EQmDc4jNv50byLOfI+IfoPOHHEAg9jsbVb063XwXtjiV 7Dzm2x8h5sKa8ZMoNVxDUO5+qmHUKcDyCKhnKYXn8Py2/41ShEeHJvcVKqpKblLB9l8oANeMDoH2 oV0JGm2tAOxdN/XpqHH+pN3JT1MdQstqNucr61lgAjTppFgaA5YHHJphJnP0RuJ4QrrApYB9MgsS kBQKpymLsnFCodxiJHaw9PQSQnCwZYAImTSeGMkL/s+ti7hxnXYCNe9hbunsnEMNXqiCXoBX9o8m kgbV6BZFPzgStTGUgQ3EDRvWnlw7EeKHFsXJ1ZiW1pRBIcHwRD1blemmity4ZwWXpj+ICqhHPFkz anff8b5yXXJsbhI2uIL8kXlB3E7AOxx2Hrp6rMuIvy2K4hxK7SHqPy5bdqdCj+yhLzWDwaLp47/d 5VFLo6bqPhH9a6LfrQGDujneoRPptQiQsKWQtxRgggEakLFw2IYWZbXb75ZSlZ5uDaR8SsRQkZ2k 91xWCnjhBllClS7WBhiJNrX9M6eZFzD9iUPlzmYhDTXw0QTRJD4s79vWvHaTxlW0aomYTD3Qgdji pUep/jwIoIJU6VSr7OAVTm6lN7lKN6H2DSsNQqHkmxMqFvo4+DoDSsXIHDuSmOdGzYJlsPxBxY1M tDbUz/rTy2jRMWTY3Yw9vxolygAmo1jfpwkfTf67WO27eRcqn0PgY6X1yKzIYNdEOfIJ+hx+VCjs IqZ9X1IATq8pBhbSVTC3BWcTvaWKlVzhEfT3oNyCbITvzJncrXAuMmpjrDnKB3X+/pjPUMpuUF96 99HOnceyIDzZ1ylZDMGMyRfYOetP1CwsTnZ156YFCCkAJnPwXA1Zt93EfIoyQr8I5CzyWJsQvpVd sI8+aW+IklEFtY20VWkbghZp45Mo3NX2TW59dq/Af4LrMizI8lzk5m/Y9GNjxnLRLEYmlJGpaBva PBAj6fhJQ/WIJtAvIYyxQvzFYuLfj+dxiOsvV7dP3e5zGoBbZnDeED1Hrth7K+DExEFfAGI1+LLf or2D8Qf2FQnoMNEKgajGwe4w73kW8OGlcaScepD3rXoERjf6Vs+yM40DSNVYAepkBzUiEEfmec2+ HpPBqhJPhUT0eMaCLk5p7TLhdQkFwPUT8UEKuqpRvni01FxMQgGqWPiiHuKfogATWCMlzV/0RXKg qsx/1ZdnU3F2awCi2V+YNbqLhH3uQSqkgPUZFdGbyC2zXp24Wgiqx/Oalv90tb20OrcLH8o9stJw aK+F5iELrROxMByQ4J32LkaMFxcpZdIAgqfsWUhk5+tU8h4Y427/ofFFGdKol5p3rln/17Zbtifv AX3xRpy+thbuJrAHK4e1+VDmGsO7DmCTdfY3Wnlheia4LZxAYivE8F/V7XkN7++yhFPKLEBQUkp/ QqM5ZIb/lCzXQJgrusZWEBukRaoa1awnWokUtUk5MGPd0ekMuy5NuwGR6lPE/DXu+R3yQqD22E9g L4CrDLd7FNvwI/9tFSGarhhnveo8rRkhT63GKohPTxuceleXpJR1zjxZ2llNGNRbXMlU7AjdgHa0 DClOOcNcNeglIgNUWg/foYDMw3H8p2Br0GXVCpVBjagc2rj6Ab8a/MVVVeafRtU/ULMvzdjhn209 tehwozkUSixs54DT3AkG5BND0Ek4f9AGe8tZWieJOWov5gxM3XZSSAKfIhrY0/53Qu0oDnxWZeEx Sb1JYKlFrpcQYPjBxPVGf0SXaHL6zdnU5kfuIJl7nDO3KdmXIQDC9j97lDyGcg+Z85soRtSJWl3A AFJiSxwkcQC8iI6aqWhfPOcqROOW7MpyO7AunUfuWAV6tUyPLc4VSCCtGG87h/DaVosIpmYBsQHT eEalZPOAFE4qYro+GzL72lO6DNc4nssWLvoOlQs2SkCQgaFJn4qIIW4joo/WmNJQ6jQJ8ZnCsNV9 wgKKAdWb0IB6EX10T+CypAnkhCidvxpIu84all/8+1bC5H2AwSkK1DjdeXuPMrDkLsba7epb+J3G 8uaBIosIRwqlaxeQQpolX12qPdWGTJymv1qOoyLDu0XxgA1U7SyB3t8Ipy5NDJ6M1vEIZsThRcdK GvBhd/ldYYQQjwaF70w+6Yi1hZ5m7tHG0ysnFKln1fjaDP1JLlhpMimdq0UmTtBVTo0UYNL53LMw 6UN+dC8IMxvBMepDr/3YtSRrrDbhL8xUZ5+VkZY761S5b0dh3O228dYd38I0gBGGPX86UpoX154I XacMiG3xH1DSIwtNz1U5IWhmRCzRB0HoLW2Tee6H8WtIe+zXpzBbbYRqQeY8Tko+uj0r66D8USwo V1Q1hpt04bMC2pUw4reL4fdW9vO04QiDe1GB8XUNApqSLz2Fxy2lDxGYeV9KaUC288FUbAHst9ab hv0c2RFg0zqxI5FMuWDDtey0XO2OQVCbOf8VyJe84jkSawj989HeUdXdi2DiW5cYZbGTEf9CLKlI NjFvlNeRaUinMfhPSGYf9GUIxKUevaUvtDgp6mesP73FeCB5lK9oyKVwmNwAd9Jwxh42p0pkSy/f yEIMsGRi8M4kY0xWKi8g2/J9qcd/GN1nrrYRFr7ZNurG8Bcb+4ssXOaAjs3TljWwUUky0RxQebNf RvBkg/UaAsp03qdESVSIzelZEzZ3YjTjCWTjx4Y93EkSzOJ0dsln2avvTbCXda9nH+XnEZ4hpb/P ChHZlcHGCuKt9lBtMnAop75yMAl4BjHZkIDLhcICkoIHQeLgFeuuukoIJQMPCLwDa6huyibBP5Bj HuZZHJPxbDjBS5NJXeTYQLI2RwCtATzafNdKwR4jbT8IRNIm7KezGX1nR6YBYZ2374fGqrDQcPdV 2XeRNeEUzg1UBmDKmmnVNiMlditfOMnmqJwLRUkthB5lh0pWHPkN8xhVPSygWi2s3f88o/nRvQP9 q9XNz8zyCxU8yDMU9Pbnh/CHqegdkhtPb0bxXetruyxbpEZ4qSgZMEImlE7aPFP1l4tKR3UeUg0l GkXqfNa8BtveFw7jni1Hc+z2X3pf64d/XGPW5KHvBS7oJDCwLBnteIquPc++fGx0L3nbvmZc8KJp buW5Ia1i7ZurcOk0XePyyTnkc7/WSSwX6uhptsWYXJ+VPAEaigyRObIvIN60ENDG28oGTzHA7zou hZppTKajEqwGhEHeK0PPFzS3EL/9XZ1jJ3kqh3fSy8UZ2+cqntBkAOuKYhFEIrKwEIScHzbPnBxw uIQhaXjJke/Ywiq79YXDP416F7F19uRD4Y4OAOqsI9YN2z9ZB3NbKkxEQywhDiwWg55sQMpb/Tu/ uskNZeqmLM8jt6c/agzZwnVcsheajaLY2bEBn+lYsdRrU5oroJLew4pXMDhrfJ7oY1iI005LBkeh 6clhyfypqxoz4Sk2CclJpgV+TfWsMlNxgWZ/Av6EkGlG+D2zWbrfHkVeDH/rp1NdY+8YfBtF+hip Vza6uaB1NKtRFfjPVa4UnVg+h+VHW9Jq9hqs29hQeBC46K7ssP0KgVJK3Bm7CGfb0J/w4EJyAxI6 6jJRa4CW9Msr+W/9hYSmd7UlnPc+y5Fm+kl9EYj+csU9sB52LQWB1ZvT9ebM+Jzf3c6RuJEsjiDr js9fBU+QhnEVqUFoLb/oinshf0yMFzw14Ph4ZzfxiC8JsSSuVQ7jC9G3cNzvAzs4eWPvByfxUQWN sV/kMEQmTWdeLux+SAEfn+RbNo42dSiTnSm+vPWVSVi/tSjUBOqBaBD4c1DnLh+75xSutmxZiZCZ ZVhIqpc7YsB6kXgQglPWD96uxPoDCD1HACpZamewzltIFErr9Tp7XfX2xH8gPl6ibiKZ8D2yW8PB JmetTCVvKb3jslLh27K+tglhvYxqZsvNvMLobzLYMpgSN48XB0YHDSJsxFUHdG6b04di+/yY4hPd Z7ZOE7IKbdp3ensL2FLOHqqO+r01MWTME9yk5PFCZzG9CIGsHbRP+K3TeAd3VHQqPe57scQRLmUP St2g2b6ZmtyLvMMpen+kWneEj+cO9UdJl3xCVOla0iWtZ/na5Yx+AxYPyEWFArWck7+lyb2Di21b NUPcJPV67rBQrmrfY4esarZV52Azr6Z0jEPUVryK+jKlj6rRfVqNJcNavNPV4fd5eW+nJapTlhdb 5EmtehsAIvUfQnk+I9Qe7vuvVBYv00JWQvm6kXU/w9cqH6303skp0KXVhYj0mgwvdoUrvjJoKzoz fvTCvpjFDS2rZluvZX4lFyUTRnogYWPGPN5HzzP0cMjB8zoDH8zIuC/UEHKK7ElvszWcIe8+idxn rXAoVkxx/oAkZ3d12E65w5zUyYocsppqj8WQ4IZomCZ97xFlE3QNFivgcUnyfZhvamTsxdFZPZmq 6oLriQWIZ/6F1c9hq7H5C9Id/58hRVnR0BKZ1mEnKkxwvvqWtV8Qv7NMzUNuU/TpqSoIyOGBaY2o R+vnlkb4XmRUYTskB9d3YK2K8KFx7IZJTzi0C4eTiGhPw5MS5aShKi03lQe2Tw4Hu7QZ7wihxq4l kCmcG/DmM0Vb0TmN9ixRZvVOgwDcFtZ5e3583nL/w/hvWJFk+TI8kDFIOWmHY+cNguyZ6FJ6w1Bw YeANAJC7u1UF4Xq5uVHiKd2gU/wNd/TXeTMxyr7mHNCV2g3UgfTY60Rr3gDL/4X63nR7gCmIUTfj 7GAI/Hribfi9/FScm+hLkWaca/CA96cfk5hNenCBB7CJzwd7bwOisTSlSJCRLaL0Y5xtvJr85Xx5 uB8CDAnE59jxDJ0Vgh6gUdfLv4Pjssqw0IBe/D0F5lQEuNAtHXDZGhPlc5u9h94fdtwSrGnbtP1z nJ9aNVklZhWsg6a2U5wsBRFogq9VpEXk8MbkClJkgUTQQn1cFkzKgZBZy3GVgwIeL/n6RILPOGny 0eWxiwLjmT8Nneidp72Kj+Kxt7QfAcGfrkTbN05hH11l6q5S5W5F8/N6hCA3R0eX3QoCHCfzSepw 6c1O2d/f8kP+T7xTktYtqHXQfjBJbjBFWSZpXu3R5KG5Q+2FKfcOv/NNd3dV0AJ9lqhXRZVsZNrQ Kylfw9Cps+fQnPTbB+eSxkiHkZR8s147q2pxk4LpsRpFA949zFRVdl0GrYyl/LguF91h5p2sCuv1 ePQualm7ShJQR8CskMCaw8PM0D5xcT9cMuGrV0zGk0gxttPqBUD5ltv7NZakRy1QuuA6u0jGE+1T Zi57iPzgzweEp8J9q1RaVczC8k+3bu924elEy+lVRGv7Fryp7oRs9bQmmUxxbOiKx1mqwhzpL8Vj bmVO1WYXdWmXfc3v1DMJxlwb7CBlLLEiSrMC/ny/jdvcTbbXkASa/QXhsoZ8tGOhodM9BYVru7vb dgAFXzrsXfaNY/Qdhm0Q5nk8qF6y0BOaxql7JxUeGYEr9yCLYRgCq1yp//NQBNTYX8unPQyVr8tz KQ4kWhuENzlLKuiCWMwWyOR70ZSNxKEbTI8toI6KmiM7s3OO/1rVivOtqd11geIe99dUjzKPBII5 4VxZDQ/Xa5O342rsbtgT4w6CfOjb9VyRNBGhKxNmzKJY0ACfftuCrddjCGwvx/U8B4Rn8oVVeYQu WDh7f8d3//jY9YvaFKLR8Pomj4MunNIarOtTTXZI2kn82jAOJwVEqfDY/eHhtaBHdkzoa02Z3lMq iItvfoKUtwxMyqhclMd9l2aLsjnLrYON7UExH6eTP172RkKopGYDfu1ZSjFXTo9vokhrzlc5pVE+ 5CqU5IoidEEOt+tj07obkL9+Fvu3xpiW90F0Q+saVINTv7DiDR1oUf4Nb8KuuwCuh7BLrDHgFxsI 1wtRaZ713nYoZvsy26kFaqktbt1AJte0q1zBf8nIrhaUZE3fw4SyTp5Wc6le6byOkrdMPjebhoor JbsO2E8sfdWwPFKxG4Jw3uH6IS3SbUC9ljieuds4l3W6PFJoZnkCRLB4cQt/DAM+mTQbIw0rH9x0 97+n+VSZRed1vAg3NYrs6JR2QiqBX+sfUovdOGmTuyP2BCWc+LxiTGg5rHIvwcUNx1t/pp8fxIwu xm7HayypTMNDnnxW/TQxZqryKw18zzmBwNUaIB0bGV4PodP7teAoKokmXEg02VZmTJ7P8hTAA7C7 agmAR1zuTL+YGo9PFZ/NhOz4bV9LbRUR/MdBOIWcBobeJe7PUpZW4Ku6mCiRuvfcd8XtefFn/VYk 4efdAwH1OrOhZnHV+PWY2vqtUuBG5e+OBsT+zB5JebVXjMHiatqlfOgtcXJ53HmM8FpthU7nFrAY fUGrb5VyrKTJ2KGHGjSIisQfuDcJLEkNts02Ko7F0cMjYmfuowJOZCEHx3LUsGmDP7G7LsErsoSv S457pMULWRX2o1vYBG75qCyFWHA1hoRWSRsVS68TI74tXlMtpp1pM/lPxbc8C8StbUUpfXyck080 qxcYLWYNgIWQdS7eUdf0+up1eFJXO6pE88LA2f/9SgyUfjqf3Jxg5PcwiUBACidD1TPp+R3mSVkW bdb0dU8lZQj297MI/qbMEsg/2Im41SVperCQ2EdeElspb2ct9i76Tss6KCMSdYhQtHDnvVhD8gpf d2csYkCxvJtTco6PV+FDYx5l2ZCX6RKVKniVt/GmpMBwGDUAPMdUv0+O3Yusl3WbVQUbEKAUKKaN xHnGk7Ogs1aTU99fSYD/fTjuYdn0eX6R/K8hsw+KY1T59rBS3s0kGhzWJ36mA5Fgzjpe4PMGvenh 1AhVKK5mHnMPite+w/zv7z+wIc2S5A458iqCH/TvxoX/pV5H9/ndD3YtfyjHRqKspw9IA6gJ96on hI8dgRfK4ADlOV9Z9IjWXoX0OP/twmWhxNsUWQAw93zEVgAtGgP+6PscC6h/JJ42js1niNWf18nc w4GRwFe2PxzK76gvIwrciS4lByFGv5wg7QvBpLufw4QqEHWUKHBstin7Bo+QhFMKB0Blheehk70Y pxRNjRCp1OG3+4RAS2HXxV6PNPrNh89upi7zb01eALzsPUbECXuSgvbSAm8BHlC11RA42qVy6kw3 +UOio/UPX1zg4hXhRkfqkrZZ3C+UN7VCMUvHrxCPKcC0mYSWtDpam712e33MMsq+ho8lZ7NAAcnC C6nmRwFlS3/N+MdUwFeKEIlvf10Ev+TrS999Xmo4/Y2Ze2OexqOPgftx1L4pObXJdiyG6Q0U3/UE FgUc4C1dKoQQiWSKRpimsydmoD1nokbwsK9lb2Oqqf5gLHjoZjmH8t6pp3fS3tbrykEiZRPdP0Lu tHHNg11F//kV5hYqWuCItz54oB4H5rYeRqBffOFB8/5XDibrXxFhELZdp4ZE49ogUtKNxyrxd9L0 TpkA3prkXzJqiZVUjURxr01s+Cmi6I7/1oonIU4ukAgp+oVMHC/q3I/XbftY0dzAQf5xK7lkZCXC Vzo4JuHJi7sFxjBj5NYR24d5eFNMpFX4DWVfp6a7agTji4dDR6e5GhOXA+sR+vSQFoHnUzgiXnpp Toypic0p0XZefIyEZ4QkW+WXj1ndIIlV87qvooA0T7WmMC0dBvNuJeJeSfO28tb36BRmjL5kKQi2 pYCK0VT3d1g2nAS+d+dCU33LJY/LX7N64t/WdX/+JbjnJErhhj771G5LY3qViQtiSankxwd2ZPrx Fbs1OIimpnLPCU169Ky472/StIZSQOy3ChwCl/ENfJX7IwqF0v3tUwj7YSfqECdo4+hSQ6OvRp8o upDcQTes1pRimYIg3NK1iIs6yvS/eXcLbyZc8bpTn12eC4e/nZgGo0vQIqbFkVZessrwTTQ0On/i bd7salIRJOu5vRvvRCahuBweiS23fQN0WkUa7YrWD52jGpekApyNiXbOMttIK91IV8fSHwezfTLj rsnJXRXZXGBglJiAH+Y5ZIdG/s44rsBC0Y5gbCNRfGkl54REjHhNSP4AItY3T6U94ZxhneTfj2Lx mVmnrwmgFp0PcJtpU/Dtue5X8fDdGRotwGF/7VmhB5Ks9SXAhYiI6TTKImwGOIfEi+PTQbKXPUts 9Mb2qDLxiqTvIj1gP7CFe1Asfj+5rgNgP4KplBneakQkXFntTy29YSRMUfYo9h7zhIdHNpUMO9I= `protect end_protected

bsd-2-clause

41cacbc2d7285e31c37d69cbb876e16f

0.947056

1.844521

false

Yarr/Yarr-fw

sim/sim_aurora_channel.vhd

1

6,777

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/11/2017 04:01:21 PM -- Design Name: -- Module Name: sim_aurora_channel - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. library UNISIM; use UNISIM.VComponents.all; entity sim_aurora_channel is -- Port ( ); end sim_aurora_channel; architecture Behavioral of sim_aurora_channel is component aurora_rx_channel generic ( g_NUM_LANES : integer range 1 to 4 := 1 ); port ( -- Sys connect rst_n_i : in std_logic; clk_rx_i : in std_logic; -- Fabric clock (serdes/8) clk_serdes_i : in std_logic; -- IO clock -- Input enable_i : in std_logic; rx_data_i_p : in std_logic_vector(g_NUM_LANES-1 downto 0); rx_data_i_n : in std_logic_vector(g_NUM_LANES-1 downto 0); trig_tag_i : in std_logic_vector(63 downto 0); -- Output rx_data_o : out std_logic_vector(63 downto 0); rx_valid_o : out std_logic; rx_stat_o : out std_logic_vector(7 downto 0) ); end component aurora_rx_channel; component scrambler port ( data_in : in std_logic_vector(0 to 63); data_out : out std_logic_vector(65 downto 0); enable : in std_logic; sync_info : in std_logic_vector(1 downto 0); clk : in std_logic; rst : in std_logic ); end component scrambler; signal rst_n_i : std_logic := '0'; signal rst2_n_i : std_logic := '0'; signal clk_rx_i : std_logic := '0'; signal clk_serdes_i : std_logic := '0'; signal clk_ddr_i : std_logic := '0'; signal enable_i : std_logic := '0'; signal rx_data_i_p : std_logic := '0'; signal rx_data_i_n : std_logic := '0'; signal trig_tag_i : std_logic_vector(63 downto 0) := (others => '0'); signal rx_data_o : std_logic_vector(63 downto 0); signal rx_valid_o : std_logic; signal rx_stat_o : std_logic_vector(7 downto 0); constant RX_CLK_PERIOD : time := 6.4ns; constant SERDES_CLK_PERIOD : time := 1.6ns; constant DDR_CLK_PERIOD : time := 0.8ns; constant IDELAY_CLK_PERIOD : time := 3.2ns; signal tx_data : std_logic_vector(65 downto 0); signal tx_data_s : std_logic_vector(65 downto 0); signal tx_data_t : std_logic_vector(65 downto 0); signal tx_counter : unsigned(31 downto 0); signal cnt : unsigned(31 downto 0); signal clk_idelay : std_logic; signal idelay_rdy : std_logic; signal tx_data_valid : std_logic; attribute IODELAY_GROUP : STRING; attribute IODELAY_GROUP of IDELAYCTRL_inst : label is "aurora"; begin rx_clk_proc: process begin clk_rx_i <= '1'; wait for RX_CLK_PERIOD/2; clk_rx_i <= '0'; wait for RX_CLK_PERIOD/2; end process rx_clk_proc; serdes_clk_proc: process begin clk_serdes_i <= '1'; wait for SERDES_CLK_PERIOD/2; clk_serdes_i <= '0'; wait for SERDES_CLK_PERIOD/2; end process serdes_clk_proc; ddr_clk_proc: process begin clk_ddr_i <= '1'; wait for DDR_CLK_PERIOD/2; clk_ddr_i <= '0'; wait for DDR_CLK_PERIOD/2; end process ddr_clk_proc; idelay_clk_proc: process begin clk_idelay <= '1'; wait for IDELAY_CLK_PERIOD/2; clk_idelay <= '0'; wait for IDELAY_CLK_PERIOD/2; end process idelay_clk_proc; IDELAYCTRL_inst : IDELAYCTRL port map ( RDY => idelay_rdy, -- 1-bit output: Ready output REFCLK => clk_idelay, -- 1-bit input: Reference clock input RST => not rst_n_i -- 1-bit input: Active high reset input ); rst_proc: process begin rst_n_i <= '0'; rst2_n_i <= '0'; wait for 200ns; rst2_n_i <= '1'; wait for 350ns; rst_n_i <= '1'; wait; end process rst_proc; aurora_cmp: aurora_rx_channel port map ( rst_n_i => rst_n_i, clk_rx_i => clk_rx_i, clk_serdes_i => clk_serdes_i, enable_i => enable_i, rx_data_i_p(0) => rx_data_i_p, rx_data_i_n(0) => rx_data_i_n, trig_tag_i => trig_tag_i, rx_data_o => rx_data_o, rx_valid_o => rx_valid_o, rx_stat_o => rx_stat_o ); piso_proc: process(clk_rx_i, clk_ddr_i, rst2_n_i) begin if (rst2_n_i = '0') then tx_data <= (others => '1'); tx_counter <= to_unsigned(1, 32); cnt <= (others => '0'); tx_data_t <= (others => '0'); tx_data_valid <= '0'; elsif rising_edge(clk_ddr_i) then --tx_data_valid <= '0'; rx_data_i_p <= tx_data_t(65);-- after 3.3ns; rx_data_i_n <= not tx_data_t(65);-- after 3.3ns; tx_data_t <= tx_data_t(64 downto 0) & '0'; -- rx_data_i_p <= tx_data_t(0); -- rx_data_i_n <= not tx_data_t(0); -- tx_data_t <= '0' & tx_data_t(65 downto 1); tx_counter <= tx_counter + 1; if (tx_counter = 64) then if (to_integer(cnt) mod 64 = 0) then tx_data <= "01" & std_logic_vector(cnt) & std_logic_vector(cnt); else tx_data <= "10" & std_logic_vector(cnt) & std_logic_vector(cnt); end if; tx_data_valid <= '1'; tx_counter <= tx_counter + 1; --tx_data <= "01" & x"0123456789abcdef"; cnt <= cnt + 1; elsif (tx_counter = 65) then tx_data_valid <= '0'; tx_data_t <= tx_data_s; tx_counter <= (others => '0'); end if; end if; end process piso_proc; scrambler_cmp: scrambler port map ( data_in => tx_data(63 downto 0), data_out => tx_data_s(65 downto 0), enable => tx_data_valid, sync_info => tx_data(65 downto 64), clk => clk_ddr_i, rst => not rst2_n_i ); end Behavioral;

gpl-3.0

a28a48b5839e2fec9a3bbd6e72a19fcd

0.510993

3.415827

false

zcold/fft.vhdl

src/array_slicer.vhdl

1

2,077

-- The MIT License (MIT) -- Copyright (c) 2014 Shuo Li -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- The above copyright notice and this permission notice shall be included in all -- copies or substantial portions of the Software. -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -- SOFTWARE. --------------- -- array slicer --------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity array_slicer is generic ( data_width : integer := 16; array_length : integer := 8; address_width : integer := 3 ); port ( array_in : in std_logic_vector(array_length * data_width - 1 downto 0); address_in : in std_logic_vector(address_width - 1 downto 0); data_out : out std_logic_vector(data_width - 1 downto 0) ); end array_slicer; -- Function Implementation 0 architecture FIMP_0 of array_slicer is signal address_integer : integer range 0 to array_length - 1; signal address_unsigned : unsigned(address_width - 1 downto 0); begin address_integer <= to_integer(address_unsigned); address_unsigned <= unsigned(address_in); data_out <= array_in((address_integer + 1) * data_width - 1 downto address_integer * data_width); end FIMP_0;

mit

5620d7aab528e085540f6897ff0a0c36

0.705826

4.112871

false

Jorge9314/ElectronicaDigital

Impresora2D/antirebote_tb.vhd

1

1,132

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY antirebote_tb IS END antirebote_tb; ARCHITECTURE behavior OF antirebote_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT antirebote PORT( CLK : IN std_logic; a : IN std_logic; b : OUT std_logic ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal a : std_logic := '0'; --Outputs signal b : std_logic; -- Clock period definitions constant CLK_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: antirebote PORT MAP ( CLK => CLK, a => a, b => b ); -- Clock process definitions CLK_process : process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin a <= '0'; wait for 100ms; a <= '1'; wait for 100ms; a <= '0'; wait for 10ms; a <= '1'; wait for 50ms; a <= '0'; wait for 60ms; a <= '1'; wait for 50ms; a <= '0'; wait; end process; END;

gpl-3.0

90a53cb6f4f769698b3d9bacbdcf5785

0.54947

3.162011

false

rjarzmik/mips_processor

MEM/Memory_access_tb.vhd

1

9,225

------------------------------------------------------------------------------- -- Title : Testbench for design "Memory_access" -- Project : ------------------------------------------------------------------------------- -- File : Memory_access_tb.vhd -- Author : Simon Desfarges -- Company : -- Created : 2016-11-28 -- Last update: 2016-12-14 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Very simple testbench for the memory stage module. ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-28 1.0 simon Created library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cpu_defs.all; ------------------------------------------------------------------------------- entity Memory_access_tb is end entity Memory_access_tb; ------------------------------------------------------------------------------- architecture tb of Memory_access_tb is -- component generics constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; -- component ports signal clk : std_logic := '0'; signal rst : std_logic := '1'; signal stall_req : std_logic; signal kill_req : std_logic := '0'; signal o_exception : std_logic; signal i_reg1 : register_port_type; signal i_reg2 : register_port_type; signal i_mem_op : memory_op_type; signal i_mem_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_is_jump : std_logic; signal i_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal o_reg1 : register_port_type; signal o_reg2 : register_port_type; signal o_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal o_is_jump : std_logic; signal o_stage1_reg1 : register_port_type; signal o_stage1_reg2 : register_port_type; signal o_stage2_reg1 : register_port_type; signal o_stage2_reg2 : register_port_type; signal i_mem_rd_valid : std_logic; signal i_mem_rd_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_mem_wr_en : std_logic; signal o_mem_word_width : std_logic; signal i_mem_wr_ack : std_logic; signal o_mem_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal o_mem_wr_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_need_stall : std_logic; signal i_dbg_mem_pc : std_logic_vector(ADDR_WIDTH -1 downto 0); signal o_dbg_mem_pc : std_logic_vector(ADDR_WIDTH -1 downto 0); begin -- architecture tb -- component instantiation DUT : entity work.Memory_access generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH) port map ( clk => clk, rst => rst, stall_req => stall_req, kill_req => kill_req, o_exception => o_exception, i_reg1 => i_reg1, i_reg2 => i_reg2, i_mem_op => i_mem_op, i_mem_data => i_mem_data, i_is_jump => i_is_jump, i_jump_target => i_jump_target, o_reg1 => o_reg1, o_reg2 => o_reg2, o_jump_target => o_jump_target, o_is_jump => o_is_jump, o_stage1_reg1 => o_stage1_reg1, o_stage1_reg2 => o_stage1_reg2, o_stage2_reg1 => o_stage2_reg1, o_stage2_reg2 => o_stage2_reg2, i_mem_rd_valid => i_mem_rd_valid, i_mem_rd_data => i_mem_rd_data, o_mem_wr_en => o_mem_wr_en, o_mem_word_width => o_mem_word_width, i_mem_wr_ack => i_mem_wr_ack, o_mem_addr => o_mem_addr, o_mem_wr_data => o_mem_wr_data, o_need_stall => o_need_stall, i_dbg_mem_pc => i_dbg_mem_pc, o_dbg_mem_pc => o_dbg_mem_pc ); -- clock generation clk <= not clk after 10 ns; -- waveform generation WaveGen_Proc : process begin -- constant signals stall_req <= '0'; kill_req <= '0'; i_is_jump <= '0'; i_jump_target <= X"01234567"; rst <= '1'; i_reg2.idx <= 8; i_reg2.we <= '0'; i_reg2.data <= X"FEDCBA98"; i_reg1.idx <= 5; i_reg1.we <= '1'; i_reg1.data <= (others => '0'); -- none, loadw, storew, load8, load8_signextend32, store8 i_mem_op <= none; i_mem_data <= (others => '0'); wait until clk = '1'; wait until clk = '1'; rst <= '0'; -- Testing mem_op == none... i_mem_op <= none; i_reg2.idx <= 1; i_reg2.we <= '0'; i_reg2.data <= X"00000001"; i_reg1.idx <= 5; i_reg1.we <= '1'; i_reg1.data <= (others => '0'); wait until clk = '1'; i_reg2.idx <= 2; i_reg2.we <= '1'; i_reg2.data <= X"00000002"; i_reg1.idx <= 3; i_reg1.we <= '0'; i_reg1.data <= X"AAAAAAAA"; wait until clk = '1'; -- Testing mem_op == loadw... i_mem_op <= loadw; i_reg2.idx <= 2; i_reg2.we <= not i_reg2.we; i_reg2.data <= X"00000002"; i_reg1.idx <= 4; i_reg1.we <= '1'; i_reg1.data <= X"01234567"; wait until clk = '1'; -- Testing mem_op == none... i_mem_op <= none; i_reg2.idx <= 1; i_reg2.we <= '0'; i_reg2.data <= X"00000001"; i_reg1.idx <= 5; i_reg1.we <= '1'; i_reg1.data <= (others => '0'); wait until clk = '1'; -- Testing mem_op == load8... i_mem_op <= load8; i_reg2.idx <= 1; i_reg2.we <= '1'; i_reg2.data <= X"00011111"; i_reg1.idx <= 4; i_reg1.we <= '1'; i_reg1.data <= X"89ABCDEF"; wait until clk = '1'; -- Testing mem_op == load8_signextend32... i_mem_op <= load8_signextend32; i_reg2.idx <= 2; i_reg2.we <= '0'; i_reg2.data <= X"00011111"; i_reg1.idx <= 6; i_reg1.we <= '1'; i_reg1.data <= X"01234567"; wait until clk = '1'; -- Testing mem_op == storew... i_mem_op <= storew; i_reg2.idx <= 2; i_reg2.we <= '0'; i_reg2.data <= X"00011111"; i_reg1.idx <= 3; i_reg1.we <= '0'; i_reg1.data <= X"0000FFFF"; i_mem_data <= X"ABABABAB"; wait until clk = '1'; -- 1 cycle stall wait until clk = '1'; i_mem_op <= none; wait until clk = '1'; wait until clk = '1'; wait until clk = '1'; -- Testing mem_op == store8... i_mem_op <= store8; i_reg2.idx <= 2; i_reg2.we <= '0'; i_reg2.data <= X"00011111"; i_reg1.idx <= 1; i_reg1.we <= '0'; i_reg1.data <= X"FFFF0000"; i_mem_data <= X"DFDFDFDF"; wait until clk = '1'; wait until clk = '1'; -- 1 cycle stall -- Testing mem_op == load8... i_mem_op <= load8; i_reg2.idx <= 1; i_reg2.we <= '1'; i_reg2.data <= X"00011111"; i_reg1.idx <= 4; i_reg1.we <= '1'; i_reg1.data <= X"89ABCDEF"; stall_req <= '1'; wait until clk = '1'; wait until clk = '1'; wait until clk = '1'; wait until clk = '1'; stall_req <= '0'; wait until clk = '1'; i_mem_op <= none; i_reg1.we <= '0'; report "end of simulation"; wait; end process WaveGen_Proc; -- purpose: memory -- type : sequential -- inputs : clk, rst -- outputs: mem : process (clk, rst) is begin -- process mem if rst = '1' then -- asynchronous reset (active low) i_mem_rd_valid <= '0'; i_mem_rd_data <= (others => '0'); i_mem_wr_ack <= '0'; elsif rising_edge(clk) then -- rising clock edge i_mem_wr_ack <= '0'; if o_mem_wr_en = '1' then i_mem_rd_valid <= '0'; i_mem_rd_data <= i_mem_rd_data; assert i_mem_wr_ack = '0' report "Invalid transaction" severity error; i_mem_wr_ack <= '1'; else -- copy rd @ to data and change data order (ABCD -> DCBA) i_mem_rd_data <= o_mem_addr(3 downto 0) & o_mem_addr(7 downto 4) & o_mem_addr(11 downto 8) & o_mem_addr(15 downto 12) & o_mem_addr(19 downto 16) & o_mem_addr(23 downto 20) & o_mem_addr(27 downto 24) & o_mem_addr(31 downto 28); i_mem_rd_valid <= '1'; end if; end if; end process mem; -- purpose: handles the PC -- type : sequential -- inputs : clk, rst -- outputs: dbg_pc : process (clk, rst) is begin -- process dbg_pc if rst = '1' then -- asynchronous reset (active low) i_dbg_mem_pc <= (others => '0'); elsif rising_edge(clk) then -- rising clock edge if stall_req = '0' and o_need_stall = '0' then i_dbg_mem_pc <= std_logic_vector(unsigned(i_dbg_mem_pc) + 4); end if; end if; end process dbg_pc; end architecture tb; -------------------------------------------------------------------------------

gpl-3.0

cba065bfd14c349abd377b377584a8da

0.477507

3.101883

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/constant/rule_013_test_input.fixed.vhd

1

607

architecture RTL of ENTITY1 is constant c_size : integer := 5; constant c_ones : std_logic_vector(c_size - 1 downto 0) := (others => '1'); constant c_zeros : std_logic_vector(c_size - 1 downto 0) := (others => '0'); signal data : std_logic_vector(c_size - 1 downto 0); begin data <= c_ones; PROC_NAME : process () is begin data <= c_ones & c_zeros; if (sig2 = '0') then data <= c_zeros; end if; if (sig2 = '1') then data <= c_ones; end if; if (sig3 = '1') then data <= c_zeros; end if; end process PROC_NAME; end architecture RTL;

gpl-3.0

6247d8659a310af9defb2a91caed303a

0.565074

3.050251

false

kjellhar/axi_mmc

sim/dat_if_standalone_1bit/dat_if_standalone_1bit.vhd

1

4,071

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11/29/2014 09:07:43 PM -- Design Name: -- Module Name: dat_if_standalone_1bit - testbench -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dat_if_standalone_1bit is -- Port ( ); end dat_if_standalone_1bit; architecture testbench of dat_if_standalone_1bit is constant clk100M_per : time := 10 ns; component mmc_dat_if is Port ( clk : in std_logic; clk_en : in std_logic; reset : in std_logic; receive_dat_trigger_i : in std_logic; transmit_dat_trigger_i : in std_logic; dat_block_finished_o : out std_logic; bus_width_i : in std_logic_vector (1 downto 0); data_fifo_out_i : in std_logic_vector (31 downto 0); data_fifo_out_wr_i : in std_logic; data_fifo_out_full_o : out std_logic; data_fifo_in_o : out std_logic_vector (31 downto 0); data_fifo_in_rd_i : in std_logic; data_fifo_in_empty_o : out std_logic; dat_out_o : out std_logic_vector (7 downto 0); dat_in_i : in std_logic_vector (7 downto 0) ); end component; signal test_en : std_logic := '1'; signal clk100M : std_logic := '0'; signal reset : std_logic := '1'; signal clk_en : std_logic := '0'; signal receive_dat_trigger : std_logic := '0'; signal transmit_dat_trigger : std_logic := '0'; signal dat_block_finished : std_logic; signal bus_width : std_logic_vector (1 downto 0) := "00"; signal data_fifo_out : std_logic_vector (31 downto 0); signal data_fifo_out_wr : std_logic := '0'; signal data_fifo_out_full : std_logic; signal data_fifo_in : std_logic_vector (31 downto 0) := X"00000000"; signal data_fifo_in_rd : std_logic := '0'; signal data_fifo_in_empty : std_logic; signal dat_out : std_logic_vector (7 downto 0); signal dat_in : std_logic_vector (7 downto 0) := X"00"; begin u_dut : mmc_dat_if Port map ( clk => clk, clk_en => clk_en, reset => reset, receive_dat_trigger_i => receive_dat_trigger, transmit_dat_trigger_i => transmit_dat_trigger, dat_block_finished_o => dat_block_finished, bus_width_i => bus_width, data_fifo_out_i => data_fifo_out, data_fifo_out_wr_i => data_fifo_out_wr, data_fifo_out_full_o => data_fifo_out_full, data_fifo_in_o => data_fifo_in, data_fifo_in_rd_i => data_fifo_in_rd, data_fifo_in_empty_o => data_fifo_in_empty, dat_out_o => dat_out, dat_in_i => dat_in ); -- Clock generator process begin if test_en='1' then clk100M <= '1', '0' after clk100M_per/2; wait for clk100M_per; else wait; end if; end process; -- Testbench stimuli process begin test_en <= '1'; reset <= '1'; wait for 100 ns; reset <= '0'; wait for 10*clk100M_per; wait until rising_edge(clk100M); wait for 200 ns; test_en <= '0'; wait; end process; end testbench;

mit

870a7995e3f75571afc49ad05cb2a932

0.517809

3.690843

false

true

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_reset.vhd

1

23,163

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_reset.vhd -- -- Description: -- This file implements the DataMover Reset module. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg_reset.vhd -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_sg_reset is generic ( C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0 -- 0 = Use Synchronous Command/Statys User Interface -- 1 = Use Asynchronous Command/Statys User Interface ); port ( -- Primary Clock and Reset Inputs ----------------- -- primary_aclk : in std_logic; -- primary_aresetn : in std_logic; -- --------------------------------------------------- -- Async operation clock and reset from User ------ -- Used for Command/Status User interface -- -- synchronization when C_STSCMD_IS_ASYNC = 1 -- -- secondary_awclk : in std_logic; -- secondary_aresetn : in std_logic; -- --------------------------------------------------- -- Halt request input control ------------------------------- halt_req : in std_logic; -- -- Active high soft shutdown request (can be a pulse) -- -- -- Halt Complete status flag -- halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Soft Shutdown internal interface ------------------------------------------------ -- flush_stop_request : Out std_logic; -- -- Active high soft stop request to modules -- -- data_cntlr_stopped : in std_logic; -- -- Active high flag indicating the data controller is flushed and stopped -- -- addr_cntlr_stopped : in std_logic; -- -- Active high flag indicating the address controller is flushed and stopped -- -- aux1_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 1 module -- -- Tie high if unused -- -- aux2_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 2 module -- -- Tie high if unused -- ------------------------------------------------------------------------------------ -- HW Reset outputs to reset groups ------------------------------------- -- cmd_stat_rst_user : Out std_logic; -- -- The reset to the Command/Status Module User interface side -- -- cmd_stat_rst_int : Out std_logic; -- -- The reset to the Command/Status Module internal interface side -- -- mmap_rst : Out std_logic; -- -- The reset to the Memory Map interface side -- -- stream_rst : Out std_logic -- -- The reset to the Stream interface side -- -------------------------------------------------------------------------- ); end entity axi_sg_reset; architecture implementation of axi_sg_reset is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Signals signal sig_cmd_stat_rst_user_n : std_logic := '0'; signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0'; signal sig_cmd_stat_rst_int_reg_n : std_logic := '0'; signal sig_mmap_rst_reg_n : std_logic := '0'; signal sig_stream_rst_reg_n : std_logic := '0'; signal sig_syncd_sec_rst : std_logic := '0'; -- soft shutdown support signal sig_internal_reset : std_logic := '0'; signal sig_s_h_halt_reg : std_logic := '0'; signal sig_halt_cmplt : std_logic := '0'; -- additional CDC synchronization signals signal sig_sec_neg_edge_plus_delay : std_logic := '0'; signal sig_secondary_aresetn_reg : std_logic := '0'; signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0'; signal sig_prim2sec_rst_reg2_n : std_logic := '0'; begin --(architecture implementation) -- Assign outputs cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n); cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; mmap_rst <= not(sig_mmap_rst_reg_n) or sig_syncd_sec_rst; stream_rst <= not(sig_stream_rst_reg_n) or sig_syncd_sec_rst; -- Internal logic Implmentation ------------------------------------------------------------ -- If Generate -- -- Label: GEN_SYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Synchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate begin sig_syncd_sec_rst <= '0'; sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from); end generate GEN_SYNC_CMDSTAT_RESET; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ASYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Asynchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate signal sig_sec_reset_in_reg_n : std_logic := '0'; -- Secondary reset pulse stretcher signal sig_secondary_dly1 : std_logic := '0'; signal sig_secondary_dly2 : std_logic := '0'; signal sig_neg_edge_detect : std_logic := '0'; signal sig_sec2prim_reset : std_logic := '0'; signal sig_sec2prim_reset_reg : std_logic := '0'; signal sig_sec2prim_reset_reg2 : std_logic := '0'; signal sig_sec2prim_rst_syncro1 : std_logic := '0'; signal sig_sec2prim_rst_syncro2 : std_logic := '0'; begin -- Generate the reset in the primary clock domain. Use the longer -- of the pulse stretched reset or the actual reset. sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or sig_sec2prim_rst_syncro2; -- Check for falling edge of secondary_aresetn input sig_neg_edge_detect <= '1' when (sig_sec_reset_in_reg_n = '1' and secondary_aresetn = '0') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSE_STRETCH_FLOPS -- -- Process Description: -- This process implements a 3 clock wide pulse whenever the -- secondary reset is asserted -- ------------------------------------------------------------- IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then If (sig_secondary_dly2 = '1') Then sig_secondary_dly1 <= '0' ; sig_secondary_dly2 <= '0' ; Elsif (sig_neg_edge_detect = '1') Then sig_secondary_dly1 <= '1'; else sig_secondary_dly2 <= sig_secondary_dly1 ; End if; end if; end process IMP_PUSE_STRETCH_FLOPS; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_NEG_EDGE -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- negative edge detection, -- ------------------------------------------------------------- SYNC_NEG_EDGE : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or sig_secondary_dly1 or sig_secondary_dly2; end if; end process SYNC_NEG_EDGE; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO -- -- Process Description: -- This process registers the secondary reset input to -- the primary clock domain. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_sec2prim_reset_reg <= sig_sec_neg_edge_plus_delay ; sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg; end if; end process SEC2PRIM_RST_SYNCRO; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SEC_RST -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- secondary reset input, -- ------------------------------------------------------------- REG_SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_secondary_aresetn_reg <= secondary_aresetn; end if; end process REG_SEC_RST; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO_2 -- -- Process Description: -- Second stage (destination) synchronizers for the secondary -- reset CDC to the primary clock. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then -- CDC sig_sec2prim_rst_syncro1 <= not(secondary_aresetn); sig_sec2prim_rst_syncro1 <= not(sig_secondary_aresetn_reg); sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1; end if; end process SEC2PRIM_RST_SYNCRO_2; -- Generate the Command and Status side reset sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and sig_prim2sec_rst_reg2_n; -- CDC sig_cmd_stat_rst_user_reg_n_cdc_from; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_RESET_ASYNC -- -- Process Description: -- This process registers the secondary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_RESET_ASYNC : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_reset_in_reg_n <= secondary_aresetn; end if; end process REG_RESET_ASYNC; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_PRIM2SEC_RST -- -- Process Description: -- Second (destination clock) stage synchronizers for CDC of -- primary reset input, -- ------------------------------------------------------------- SYNC_PRIM2SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from; sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to; end if; end process SYNC_PRIM2SEC_RST; -- end generate GEN_ASYNC_CMDSTAT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_PRIM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_PRIM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn; end if; end process REG_CMDSTAT_PRIM_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_INT_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status internal interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_INT_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_int_reg_n <= primary_aresetn; end if; end process REG_CMDSTAT_INT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_MMAP_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Memory Map interface reset. -- ------------------------------------------------------------- REG_MMAP_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_rst_reg_n <= primary_aresetn; end if; end process REG_MMAP_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_STREAM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Stream interface reset. -- ------------------------------------------------------------- REG_STREAM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_stream_rst_reg_n <= primary_aresetn; end if; end process REG_STREAM_RESET; -- Soft Shutdown logic ------------------------------------------------------ sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; flush_stop_request <= sig_s_h_halt_reg; halt_cmplt <= sig_halt_cmplt; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_HALT_REQ -- -- Process Description: -- Implements a sample and hold flop for the halt request -- input. Can only be cleared on a HW reset. -- ------------------------------------------------------------- REG_HALT_REQ : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_s_h_halt_reg <= '0'; elsif (halt_req = '1') then sig_s_h_halt_reg <= '1'; else null; -- hold current state end if; end if; end process REG_HALT_REQ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT -- -- Process Description: -- Implements a the flop for the halt complete status -- output. Can only be cleared on a HW reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_halt_cmplt <= '0'; elsif (data_cntlr_stopped = '1' and addr_cntlr_stopped = '1' and aux1_stopped = '1' and aux2_stopped = '1') then sig_halt_cmplt <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT; end implementation;

bsd-2-clause

ea60dcc25f9b538eb0c591bbb73ceced

0.412425

5.469421

false

NicoLedwith/Dr.AluOpysel

RAT_MCU/PC.vhd

1

1,385

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.all; entity PC is port ( RST,CLK,PC_LD,PC_OE,PC_INC : in std_logic; FROM_IMMED : in std_logic_vector (9 downto 0); FROM_STACK : in std_logic_vector (9 downto 0); FROM_INTRR : in std_logic_vector (9 downto 0); PC_MUX_SEL : in std_logic_vector (1 downto 0); PC_COUNT : out std_logic_vector (9 downto 0); PC_TRI : out std_logic_vector(9 downto 0)); end PC; architecture my_count of PC is signal s_cnt : std_logic_vector(9 downto 0); begin process (CLK, RST, PC_LD, PC_INC) begin if (RST = '1') then s_cnt <= "0000000000"; -- asynchronous clear elsif (rising_edge(CLK)) then if (PC_LD = '1') then case PC_MUX_SEL is when "00" => s_cnt <= FROM_IMMED; when "01" => s_cnt <= FROM_STACK; when "10" => s_cnt <= FROM_INTRR; when others => s_cnt <= "0000000000"; end case; else if (PC_INC = '1') then s_cnt <= s_cnt + 1; -- increment else s_cnt <= s_cnt; -- hold end if; end if; end if; end process; process (PC_OE, s_cnt) begin if(PC_OE = '1') then PC_TRI <= s_cnt; else PC_TRI <= "ZZZZZZZZZZ"; end if; end process; PC_COUNT <= s_cnt; end my_count;

mit

e8a1640982361209b02344e3b1512c1d

0.530686

2.928118

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/instantiation/rule_008_test_input.vhd

1

407

architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below u_inst1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;

gpl-3.0

b12e9763e637e8f31e60c2ab3c7fae10

0.481572

2.787671

false

Yarr/Yarr-fw

rtl/spartan6/rx-core/decode_8b10b/decode_8b10b_bram.vhd

2

12,996

--------------------------------------------------------------------------- -- -- Module : decode_8b10b_bram.vhd -- -- Version : 1.1 -- -- Last Update : 2008-10-31 -- -- Project : 8b/10b Decoder Reference Design -- -- Description : Block memory-based Decoder for decoding 8b/10b encoded symbols -- -- Company : Xilinx, Inc. -- -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ------------------------------------------------------------------------------- -- -- History -- -- Date Version Description -- -- 10/31/2008 1.1 Initial release -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.std_logic_unsigned.ALL; USE STD.textio.ALL; -- required to initialize bram from .mif library work; USE work.decode_8b10b_pkg.ALL; ----------------------------------------------------------------------------- -- Entity Declaration ----------------------------------------------------------------------------- ENTITY decode_8b10b_bram IS GENERIC ( C_ELABORATION_DIR : STRING := "./../../src/"; C_HAS_BPORTS : INTEGER := 0; C_HAS_DISP_IN : INTEGER := 0; C_HAS_DISP_IN_B : INTEGER := 0; C_HAS_DISP_ERR : INTEGER := 0; C_HAS_DISP_ERR_B : INTEGER := 0; C_HAS_RUN_DISP : INTEGER := 0; C_HAS_RUN_DISP_B : INTEGER := 0; C_HAS_SYM_DISP : INTEGER := 0; C_HAS_SYM_DISP_B : INTEGER := 0; C_HAS_ND : INTEGER := 0; C_HAS_ND_B : INTEGER := 0; C_SINIT_DOUT : STRING := "00000000"; C_SINIT_DOUT_B : STRING := "00000000"; C_SINIT_KOUT : INTEGER := 0; C_SINIT_KOUT_B : INTEGER := 0; C_SINIT_RUN_DISP : INTEGER := 0; C_SINIT_RUN_DISP_B : INTEGER := 0 ); PORT ( CLK : IN STD_LOGIC := '0'; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; KOUT : OUT STD_LOGIC ; CE : IN STD_LOGIC := '0'; CE_B : IN STD_LOGIC := '0'; CLK_B : IN STD_LOGIC := '0'; DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := "0000000000"; DISP_IN : IN STD_LOGIC := '0'; DISP_IN_B : IN STD_LOGIC := '0'; SINIT : IN STD_LOGIC := '0'; SINIT_B : IN STD_LOGIC := '0'; CODE_ERR : OUT STD_LOGIC := '0'; CODE_ERR_B : OUT STD_LOGIC := '0'; DISP_ERR : OUT STD_LOGIC := '0'; DISP_ERR_B : OUT STD_LOGIC := '0'; DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; KOUT_B : OUT STD_LOGIC ; ND : OUT STD_LOGIC := '0'; ND_B : OUT STD_LOGIC := '0'; RUN_DISP : OUT STD_LOGIC ; RUN_DISP_B : OUT STD_LOGIC ; SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END decode_8b10b_bram; ----------------------------------------------------------------------------- -- Architecture ----------------------------------------------------------------------------- ARCHITECTURE xilinx OF decode_8b10b_bram IS ----------------------------------------------------------------------------- -- .MIF file support ----------------------------------------------------------------------------- -- Specify relative path for .mif file CONSTANT mif_file_name : STRING := "dec.mif"; -- Initialize inferred ROM from mif file TYPE RomType IS ARRAY(0 TO 1023) OF BIT_VECTOR(13 DOWNTO 0); IMPURE FUNCTION InitRomFromFile (RomFileName : IN STRING) RETURN RomType IS FILE RomFile : TEXT OPEN READ_MODE IS RomFileName; VARIABLE RomFileLine : LINE; VARIABLE ROM : RomType; BEGIN FOR I IN RomType'range LOOP READLINE (RomFile, RomFileLine); READ (RomFileLine, ROM(I)); END LOOP; RETURN ROM; END FUNCTION; SIGNAL ROM : RomType := InitRomFromFile(mif_file_name); ----------------------------------------------------------------------------- -- Constant initialization values for internal signals ROM_data(_b) ----------------------------------------------------------------------------- CONSTANT INIT_DATA : STRING := concat_sinit(C_SINIT_RUN_DISP,C_SINIT_KOUT, C_SINIT_DOUT); CONSTANT INIT_DATA_B : STRING := concat_sinit(C_SINIT_RUN_DISP_B,C_SINIT_KOUT_B, C_SINIT_DOUT_B); ----------------------------------------------------------------------------- -- Signal Declarations ----------------------------------------------------------------------------- SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) := str_to_slv(C_SINIT_DOUT,8); SIGNAL kout_i : STD_LOGIC := bint_2_sl(C_SINIT_KOUT); SIGNAL dout_b_i : STD_LOGIC_VECTOR(7 DOWNTO 0) := str_to_slv(C_SINIT_DOUT_B,8); SIGNAL kout_b_i : STD_LOGIC := bint_2_sl(C_SINIT_KOUT_B); SIGNAL run_disp_i : STD_LOGIC := bint_2_sl(C_SINIT_RUN_DISP); SIGNAL run_disp_b_i : STD_LOGIC := bint_2_sl(C_SINIT_RUN_DISP_B); SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := conv_std_logic_vector(C_SINIT_RUN_DISP,2); SIGNAL sym_disp_b_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := conv_std_logic_vector(C_SINIT_RUN_DISP_B,2); --Internal signals tied to the 14x1k block memory---------------------------- SIGNAL ROM_address : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); SIGNAL ROM_data : STD_LOGIC_VECTOR(13 DOWNTO 0) := str_to_slv(INIT_DATA, 14); ----------------------------------------------------------------------------- -- BEGIN ARCHITECTURE ----------------------------------------------------------------------------- BEGIN -- Map internal signals to outputs DOUT <= dout_i; KOUT <= kout_i; DOUT_B <= dout_b_i; KOUT_B <= kout_b_i; RUN_DISP <= run_disp_i; RUN_DISP_B <= run_disp_b_i; SYM_DISP <= sym_disp_i; SYM_DISP_B <= sym_disp_b_i; ----------------------------------------------------------------------------- -- Decoder A ----------------------------------------------------------------------------- ROM_address <= DIN; PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN IF (CE = '1') THEN IF (SINIT = '1') THEN ROM_data <= str_to_slv(INIT_DATA, 14) AFTER TFF; ELSE ROM_data <= to_stdlogicvector(ROM(conv_integer(ROM_address))) AFTER TFF; END IF; END IF; END IF; END PROCESS; -- Map ROM data into dout, kout, and code_err outputs dout_i <= ROM_data(7 DOWNTO 0); kout_i <= ROM_data(8); CODE_ERR <= ROM_data(9); ----------------------------------------------------------------------------- -- Instantiate disparity logic block for Decoder A ----------------------------------------------------------------------------- dla : entity work.decode_8b10b_disp GENERIC MAP( C_SINIT_DOUT => C_SINIT_DOUT, C_SINIT_RUN_DISP => C_SINIT_RUN_DISP, C_HAS_DISP_IN => C_HAS_DISP_IN, C_HAS_DISP_ERR => C_HAS_DISP_ERR, C_HAS_RUN_DISP => C_HAS_RUN_DISP, C_HAS_SYM_DISP => C_HAS_SYM_DISP ) PORT MAP( SINIT => SINIT, CE => CE, CLK => CLK, SYM_DISP => ROM_data(13 DOWNTO 10), DISP_IN => DISP_IN, RUN_DISP => run_disp_i, DISP_ERR => DISP_ERR, USER_SYM_DISP => sym_disp_i ); -- create ND output gndr : IF (C_HAS_ND = 1) GENERATE PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN IF ((SINIT = '1') AND (CE = '1')) THEN ND <= '0' AFTER TFF; ELSE ND <= CE AFTER TFF; END IF; END IF; END PROCESS; END GENERATE gndr; ------------------------------------------------------------------------------- -- Generate Decoder B ------------------------------------------------------------------------------- gdp : IF (C_HAS_BPORTS=1) GENERATE --Internal signals tied to the 14x1k block memory (B)---------------------- SIGNAL ROM_address_b : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); SIGNAL ROM_data_b : STD_LOGIC_VECTOR(13 DOWNTO 0) := str_to_slv(INIT_DATA_B, 14); BEGIN ROM_address_b <= DIN_B; PROCESS (CLK_B) BEGIN IF (CLK_B'event AND CLK_B = '1') THEN IF (CE_B = '1') THEN IF (SINIT_B = '1') THEN ROM_data_b <= str_to_slv(INIT_DATA_B, 14) AFTER TFF; ELSE ROM_data_b <= to_stdlogicvector(ROM(conv_integer(ROM_address_b))) AFTER TFF; END IF; END IF; END IF; END PROCESS; -- Map ROM_data_b into dout_b, kout_b, and code_err_b outputs dout_b_i <= ROM_data_b(7 DOWNTO 0); kout_b_i <= ROM_data_b(8); CODE_ERR_B <= ROM_data_b(9); ----------------------------------------------------------------------------- -- Instantiate disparity logic block for Decoder B ----------------------------------------------------------------------------- dlb : entity work.decode_8b10b_disp GENERIC MAP( C_SINIT_DOUT => C_SINIT_DOUT_B, C_SINIT_RUN_DISP => C_SINIT_RUN_DISP_B, C_HAS_DISP_IN => C_HAS_DISP_IN_B, C_HAS_DISP_ERR => C_HAS_DISP_ERR_B, C_HAS_RUN_DISP => C_HAS_RUN_DISP_B, C_HAS_SYM_DISP => C_HAS_SYM_DISP_B ) PORT MAP( SINIT => SINIT_B, CE => CE_B, CLK => CLK_B, SYM_DISP => ROM_data_b(13 DOWNTO 10), DISP_IN => DISP_IN_B, RUN_DISP => run_disp_b_i, DISP_ERR => DISP_ERR_B, USER_SYM_DISP => sym_disp_b_i ); -- create ND_B output gndbr : IF (C_HAS_ND_B = 1) GENERATE PROCESS (CLK_B) BEGIN IF (CLK_B'event AND CLK_B = '1') THEN IF ((SINIT_B = '1') AND (CE_B = '1')) THEN ND_B <= '0' AFTER TFF; ELSE ND_B <= CE_B AFTER TFF; END IF; END IF; END PROCESS; END GENERATE gndbr; END GENERATE gdp; END xilinx;

gpl-3.0

f705c8114bd7875e31d34524e798f294

0.453909

4.044818

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/conditional_waveforms/rule_500_test_input.fixed_upper.vhd

1

400

architecture rtl of fifo is begin process begin var1 := '0' WHEN rd_en = '1' else '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' WHEN rd_en = '1' else '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1'; concurrent_wr_en_b <= '0' WHEN rd_en = '1' else '1'; end architecture rtl;

gpl-3.0

7deef51b2f7f8b6b2037627ef9dd5775

0.54

2.564103

false

Nibble-Knowledge/peripheral-ethernet

vhdl-serial/DCM32MhzTo9600Hz.vhd

1

3,069

-------------------------------------------------------------------------------- -- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 14.7 -- \ \ Application : xaw2vhdl -- / / Filename : DCM32MhzTo9600Hz.vhd -- /___/ /\ Timestamp : 03/03/2016 20:22:17 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-intstyle C:/Users/Yakov/OneDrive/School/University Stuff/ENEL500/test232/ipcore_dir/DCM32MhzTo9600Hz.xaw -st DCM32MhzTo9600Hz.vhd --Design Name: DCM32MhzTo9600Hz --Device: xc3s250e-4vq100 -- -- Module DCM32MhzTo9600Hz -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST -- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 5.17 ns library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity DCM32MhzTo9600Hz is port ( CLKIN_IN : in std_logic; CLKFX_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic); end DCM32MhzTo9600Hz; architecture BEHAVIORAL of DCM32MhzTo9600Hz is signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLKIN_IBUFG_INST : IBUFG port map (I=>CLKIN_IN, O=>CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_SP_INST : DCM_SP generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 32, CLKFX_MULTIPLY => 9, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 31.250, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, PSINCDEC=>GND_BIT, RST=>GND_BIT, CLKDV=>open, CLKFX=>CLKFX_BUF, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>open, PSDONE=>open, STATUS=>open); end BEHAVIORAL;

unlicense

eeaa4d06b336b75da4ea1eabf6e4af10

0.491691

3.693141

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/process/rule_029_test_input.fixed_event.vhd

1

434

architecture RTL of FIFO is begin process begin if (rst = c_asserted) then elsif (clk'event and clk = '1') then end if; if (rst = c_asserted) then elsif (clk'event and clk = '0') then end if; if (rst = c_asserted) then elsif (clk'event and clk = '1') then end if; if (rst = c_asserted) then elsif (clk'event and clk = '0') then end if; end process; end architecture RTL;

gpl-3.0

2bb78cc1890c957da9960692aad3115f

0.589862

3.287879

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/wr_chnl.vhd

1

186,977

------------------------------------------------------------------------------- -- wr_chnl.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: wr_chnl.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller write channel interfaces. Controls all -- handshaking and data flow on the AXI write address (AW), -- write data (W) and write response (B) channels. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- ------------------------------------------------------------------------------- -- -- History: -- -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/3/2011 v1.03a -- ~~~~~~ -- Edits for scalability and support of 512 and 1024-bit data widths. -- ^^^^^^ -- JLJ 2/10/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter. -- ^^^^^^ -- JLJ 2/14/2011 v1.03a -- ~~~~~~ -- Shift Hsiao ECC generate logic so not dependent on C_S_AXI_DATA_WIDTH. -- ^^^^^^ -- JLJ 2/18/2011 v1.03a -- ~~~~~~ -- Update WE size based on 128-bit ECC configuration. -- Update for usage of ecc_gen.vhd module directly from MIG. -- Clean-up XST warnings. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Found issue with ECC decoding on read path. Remove MSB '0' usage -- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Code clean-up. -- Move all MIG functions to package body. -- ^^^^^^ -- JLJ 2/28/2011 v1.03a -- ~~~~~~ -- Fix mapping on BRAM_WE with bram_we_int for 128-bit w/ ECC. -- ^^^^^^ -- JLJ 3/1/2011 v1.03a -- ~~~~~~ -- Fix XST handling for DIV functions. Create seperate process when -- divisor is not constant and a power of two. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. And general code clean-up. -- Fix double clock assertion of CE/UE error flags when asserted -- during the RMW sequence. -- ^^^^^^ -- JLJ 3/23/2011 v1.03a -- ~~~~~~ -- Code clean-up. -- ^^^^^^ -- JLJ 3/30/2011 v1.03a -- ~~~~~~ -- Add code coverage on/off statements. -- ^^^^^^ -- JLJ 4/8/2011 v1.03a -- ~~~~~~ -- Modify back-to-back capability to remove combinatorial loop -- on WREADY to AXI interface. Add internal constant, C_REG_WREADY. -- Update axi_wready_int reset value (ensure it is '0'). -- -- Create new SM for C_REG_WREADY with dual port. Seperate assertion of BVALID -- from WREADY. Create a FIFO to store AWID/BID values. -- Use counter (with max of 8 ID values) to allow WREADY assertions -- to be ahead of BVALID assertions. -- Add sub module, SRL_FIFO. -- ^^^^^^ -- JLJ 4/11/2011 v1.03a -- ~~~~~~ -- Implement similar updates on WREADY for single port & ECC configurations. -- Remove use of signal, axi_wready_sng with constant, C_REG_WREADY. -- -- For single port operation with registered WREADY, provide BVALID counter -- value to arbitration SM, add output signal, AW2Arb_BVALID_Cnt. -- -- Create an additional SM for single port when C_REG_WREADY. -- ^^^^^^ -- JLJ 4/14/2011 v1.03a -- ~~~~~~ -- Remove attempt to create AXI write data pipeline full flag outside of SM -- logic. Add corner case checks for BID FIFO/BVALID counter. -- ^^^^^^ -- JLJ 4/15/2011 v1.03a -- ~~~~~~ -- Clean up all code not related to C_REG_WREADY. -- Goal to remove internal constant, C_REG_WREADY. -- Work on size optimization. Implement signals to represent BVALID -- counter values. -- ^^^^^^ -- JLJ 4/20/2011 v1.03a -- ~~~~~~ -- Code clean up. Remove unused signals. -- Remove additional generate blocks with C_REG_WREADY. -- ^^^^^^ -- JLJ 4/21/2011 v1.03a -- ~~~~~~ -- Code clean up. Remove use of IF_IS_AXI4 constant. -- Create new SM TYPE for each configuration. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Add check in data SM on back-to-back for BVALID counter max. -- Clean up AXI_WREADY generate blocks. -- ^^^^^^ -- JLJ 4/22/2011 v1.03a -- ~~~~~~ -- Code clean up. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove usage of C_FAMILY. -- Hard code C_USE_LUT6 constant. -- ^^^^^^ -- JLJ 5/26/2011 v1.03a -- ~~~~~~ -- Fix CR # 609695. -- Modify usage of WLAST. Ensure that WLAST is qualified with -- WVALID/WREADY assertions. -- -- With CR # 609695, update else clause for narrow_burst_cnt_ld to -- remove simulation warnings when axi_byte_div_curr_awsize = zero. -- -- Catch code clean up with WLAST in data SM for axi_wr_burst_cmb -- signal assertion. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.srl_fifo; use work.wrap_brst; use work.ua_narrow; use work.checkbit_handler; use work.checkbit_handler_64; use work.correct_one_bit; use work.correct_one_bit_64; use work.ecc_gen; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity wr_chnl is generic ( -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type C_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) C_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_SUPPORTS_NARROW : INTEGER := 1; -- Support for narrow burst operations C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to "AXI4LITE" to optimize out burst transaction support C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_ECC_TYPE : integer := 0 -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ); port ( -- AXI Global Signals S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI Write Address Channel Signals (AW) AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_AWADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0); AXI_AWLEN : in std_logic_vector(7 downto 0); -- Specifies the number of data transfers in the burst -- "0000 0000" 1 data transfer -- "0000 0001" 2 data transfers -- ... -- "1111 1111" 256 data transfers AXI_AWSIZE : in std_logic_vector(2 downto 0); -- Specifies the max number of data bytes to transfer in each data beat -- "000" 1 byte to transfer -- "001" 2 bytes to transfer -- "010" 3 bytes to transfer -- ... AXI_AWBURST : in std_logic_vector(1 downto 0); -- Specifies burst type -- "00" FIXED = Fixed burst address (handled as INCR) -- "01" INCR = Increment burst address -- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary -- "11" Reserved (not checked) AXI_AWLOCK : in std_logic; -- Currently unused AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused AXI_AWVALID : in std_logic; AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) AXI_WDATA : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0); AXI_WSTRB : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0); AXI_WLAST : in std_logic; AXI_WVALID : in std_logic; AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0); AXI_BRESP : out std_logic_vector(1 downto 0); AXI_BVALID : out std_logic; AXI_BREADY : in std_logic; -- ECC Register Interface Signals Enable_ECC : in std_logic; BRAM_Addr_En : out std_logic := '0'; FaultInjectClr : out std_logic := '0'; CE_Failing_We : out std_logic := '0'; Sl_CE : out std_logic := '0'; Sl_UE : out std_logic := '0'; Active_Wr : out std_logic := '0'; FaultInjectData : in std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0); FaultInjectECC : in std_logic_vector (C_ECC_WIDTH-1 downto 0); -- Single Port Arbitration Signals Arb2AW_Active : in std_logic; AW2Arb_Busy : out std_logic := '0'; AW2Arb_Active_Clr : out std_logic := '0'; AW2Arb_BVALID_Cnt : out std_logic_vector (2 downto 0) := (others => '0'); Sng_BRAM_Addr_Rst : out std_logic := '0'; Sng_BRAM_Addr_Ld_En : out std_logic := '0'; Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); Sng_BRAM_Addr_Inc : out std_logic := '0'; Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- BRAM Write Port Interface Signals BRAM_En : out std_logic := '0'; BRAM_WE : out std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); BRAM_WrData : out std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); end entity wr_chnl; ------------------------------------------------------------------------------- architecture implementation of wr_chnl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error -- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response -- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error -- Set constants for AWLEN equal to a count of one or two beats. constant AXI_AWLEN_ONE : std_logic_vector (7 downto 0) := (others => '0'); constant AXI_AWLEN_TWO : std_logic_vector (7 downto 0) := "00000001"; constant AXI_AWSIZE_ONE : std_logic_vector (2 downto 0) := "001"; -- Determine maximum size for narrow burst length counter -- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits -- resulting in a count 3 downto 0 => so minimum counter width = 2 bits. -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits -- resulting in a count 31 downto 0 => so minimum counter width = 5 bits. constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8); constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); -- AXI Size Constants -- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte -- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes -- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM -- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM -- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM -- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM -- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM -- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM -- Determine max value of ARSIZE based on the AXI data width. -- Use function in axi_bram_ctrl_funcs package. constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH); -- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width -- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00" -- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000" -- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000" -- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000" -- Move to full_axi module -- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8); -- Not used -- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR; constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8; -- AXI Burst Types -- AXI Spec 4.4 constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10"; constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01"; constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00"; -- Internal ECC data width size. constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Write Address Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type WR_ADDR_SM_TYPE is ( IDLE, LD_AWADDR ); signal wr_addr_sm_cs, wr_addr_sm_ns : WR_ADDR_SM_TYPE; signal aw_active_set : std_logic := '0'; signal aw_active_set_i : std_logic := '0'; signal aw_active_clr : std_logic := '0'; signal delay_aw_active_clr_cmb : std_logic := '0'; signal delay_aw_active_clr : std_logic := '0'; signal aw_active : std_logic := '0'; signal aw_active_d1 : std_logic := '0'; signal aw_active_re : std_logic := '0'; signal axi_awaddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal curr_awaddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0'); signal awaddr_pipe_ld : std_logic := '0'; signal awaddr_pipe_ld_i : std_logic := '0'; signal awaddr_pipe_sel : std_logic := '0'; -- '0' indicates mux select from AXI -- '1' indicates mux select from AW Addr Register signal axi_awaddr_full : std_logic := '0'; signal axi_awid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_awsize_pipe : std_logic_vector(2 downto 0) := (others => '0'); signal curr_awsize : std_logic_vector(2 downto 0) := (others => '0'); signal curr_awsize_reg : std_logic_vector (2 downto 0) := (others => '0'); -- Narrow Burst Signals signal curr_narrow_burst_cmb : std_logic := '0'; signal curr_narrow_burst : std_logic := '0'; signal curr_narrow_burst_en : std_logic := '0'; signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal narrow_addr_rst : std_logic := '0'; signal narrow_addr_ld_en : std_logic := '0'; signal narrow_addr_dec : std_logic := '0'; signal axi_awlen_pipe : std_logic_vector(7 downto 0) := (others => '0'); signal axi_awlen_pipe_1_or_2 : std_logic := '0'; signal curr_awlen : std_logic_vector(7 downto 0) := (others => '0'); signal curr_awlen_reg : std_logic_vector(7 downto 0) := (others => '0'); signal curr_awlen_reg_1_or_2 : std_logic := '0'; signal axi_awburst_pipe : std_logic_vector(1 downto 0) := (others => '0'); signal axi_awburst_pipe_fixed : std_logic := '0'; signal curr_awburst : std_logic_vector(1 downto 0) := (others => '0'); signal curr_wrap_burst : std_logic := '0'; signal curr_wrap_burst_reg : std_logic := '0'; signal curr_incr_burst : std_logic := '0'; signal curr_fixed_burst : std_logic := '0'; signal curr_fixed_burst_reg : std_logic := '0'; signal max_wrap_burst_mod : std_logic := '0'; signal axi_awready_int : std_logic := '0'; signal axi_aresetn_d1 : std_logic := '0'; signal axi_aresetn_d2 : std_logic := '0'; signal axi_aresetn_re : std_logic := '0'; signal axi_aresetn_re_reg : std_logic := '0'; -- BRAM Address Counter signal bram_addr_ld_en : std_logic := '0'; signal bram_addr_ld_en_i : std_logic := '0'; signal bram_addr_ld_en_mod : std_logic := '0'; signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_addr_inc : std_logic := '0'; signal bram_addr_inc_mod : std_logic := '0'; signal bram_addr_inc_wrap_mod : std_logic := '0'; signal bram_addr_rst : std_logic := '0'; signal bram_addr_rst_cmb : std_logic := '0'; signal narrow_bram_addr_inc : std_logic := '0'; signal narrow_bram_addr_inc_d1 : std_logic := '0'; signal narrow_bram_addr_inc_re : std_logic := '0'; signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); signal curr_ua_narrow_wrap : std_logic := '0'; signal curr_ua_narrow_incr : std_logic := '0'; signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Write Data Channel Signals ------------------------------------------------------------------------------- -- State machine type declarations type WR_DATA_SM_TYPE is ( IDLE, W8_AWADDR, -- W8_BREADY, SNG_WR_DATA, BRST_WR_DATA, -- NEW_BRST_WR_DATA, B2B_W8_WR_DATA --, -- B2B_W8_BRESP, -- W8_BRESP ); signal wr_data_sm_cs, wr_data_sm_ns : WR_DATA_SM_TYPE; type WR_DATA_SNG_SM_TYPE is ( IDLE, SNG_WR_DATA, BRST_WR_DATA ); signal wr_data_sng_sm_cs, wr_data_sng_sm_ns : WR_DATA_SNG_SM_TYPE; type WR_DATA_ECC_SM_TYPE is ( IDLE, RMW_RD_DATA, RMW_CHK_DATA, RMW_MOD_DATA, RMW_WR_DATA ); signal wr_data_ecc_sm_cs, wr_data_ecc_sm_ns : WR_DATA_ECC_SM_TYPE; -- Wr Data Buffer/Register signal wrdata_reg_ld : std_logic := '0'; signal axi_wready_int : std_logic := '0'; signal axi_wready_int_mod : std_logic := '0'; signal axi_wdata_full_cmb : std_logic := '0'; signal axi_wdata_full : std_logic := '0'; signal axi_wdata_empty : std_logic := '0'; signal axi_wdata_full_reg : std_logic := '0'; -- WE Generator Signals signal clr_bram_we_cmb : std_logic := '0'; signal clr_bram_we : std_logic := '0'; signal bram_we_ld : std_logic := '0'; signal axi_wr_burst_cmb : std_logic := '0'; signal axi_wr_burst : std_logic := '0'; signal wr_b2b_elgible : std_logic := '0'; -- CR # 609695 signal last_data_ack : std_logic := '0'; -- CR # 609695 signal last_data_ack_throttle : std_logic := '0'; signal last_data_ack_mod : std_logic := '0'; -- CR # 609695 signal w8_b2b_bresp : std_logic := '0'; signal axi_wlast_d1 : std_logic := '0'; signal axi_wlast_re : std_logic := '0'; -- Single Port Signals -- Write busy flags only used in ECC configuration -- when waiting for BVALID/BREADY handshake signal wr_busy_cmb : std_logic := '0'; signal wr_busy_reg : std_logic := '0'; -- Only used by ECC register module. signal active_wr_cmb : std_logic := '0'; signal active_wr_reg : std_logic := '0'; ------------------------------------------------------------------------------- -- AXI Write Response Channel Signals ------------------------------------------------------------------------------- signal axi_bid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_bid_temp_full : std_logic := '0'; signal axi_bid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0'); signal axi_bvalid_int : std_logic := '0'; signal axi_bvalid_set_cmb : std_logic := '0'; ------------------------------------------------------------------------------- -- Internal BRAM Signals ------------------------------------------------------------------------------- signal reset_bram_we : std_logic := '0'; signal set_bram_we_cmb : std_logic := '0'; signal set_bram_we : std_logic := '0'; signal bram_we_int : std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0'); signal bram_en_cmb : std_logic := '0'; signal bram_en_int : std_logic := '0'; signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); signal bram_wrdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- ECC Signals ------------------------------------------------------------------------------- signal CorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1); signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence signal WrData : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal WrData_cmb : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0'); signal UE_Q : std_logic := '0'; ------------------------------------------------------------------------------- -- BVALID Signals ------------------------------------------------------------------------------- signal bvalid_cnt_inc : std_logic := '0'; signal bvalid_cnt_inc_d1 : std_logic := '0'; signal bvalid_cnt_dec : std_logic := '0'; signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0'); signal bvalid_cnt_amax : std_logic := '0'; signal bvalid_cnt_max : std_logic := '0'; signal bvalid_cnt_non_zero : std_logic := '0'; ------------------------------------------------------------------------------- -- BID FIFO Signals ------------------------------------------------------------------------------- signal bid_fifo_rst : std_logic := '0'; signal bid_fifo_ld_en : std_logic := '0'; signal bid_fifo_ld : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal bid_fifo_rd_en : std_logic := '0'; signal bid_fifo_rd : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal bid_fifo_not_empty : std_logic := '0'; signal bid_gets_fifo_load : std_logic := '0'; signal bid_gets_fifo_load_d1 : std_logic := '0'; signal first_fifo_bid : std_logic := '0'; signal b2b_fifo_bid : std_logic := '0'; ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin --------------------------------------------------------------------------- -- AXI Write Address Channel Output Signals --------------------------------------------------------------------------- AXI_AWREADY <= axi_awready_int; --------------------------------------------------------------------------- -- AXI Write Data Channel Output Signals --------------------------------------------------------------------------- -- WREADY same signal assertion regardless of ECC or single port configuration. AXI_WREADY <= axi_wready_int_mod; --------------------------------------------------------------------------- -- AXI Write Response Channel Output Signals --------------------------------------------------------------------------- AXI_BRESP <= axi_bresp_int; AXI_BVALID <= axi_bvalid_int; AXI_BID <= axi_bid_int; --------------------------------------------------------------------------- -- *** AXI Write Address Channel Interface *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_AW_PIPE_SNG -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AW_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate begin -- Unused AW pipeline (set default values) awaddr_pipe_ld <= '0'; axi_awaddr_pipe <= AXI_AWADDR; axi_awid_pipe <= AXI_AWID; axi_awsize_pipe <= AXI_AWSIZE; axi_awlen_pipe <= AXI_AWLEN; axi_awburst_pipe <= AXI_AWBURST; axi_awlen_pipe_1_or_2 <= '0'; axi_awburst_pipe_fixed <= '0'; axi_awaddr_full <= '0'; end generate GEN_AW_PIPE_SNG; --------------------------------------------------------------------------- -- Generate: GEN_AW_PIPE_DUAL -- Purpose: Only generate pipeline registers when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AW_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate begin ----------------------------------------------------------------------- -- -- AXI Write Address Buffer/Register -- (mimic behavior of address pipeline for AXI_AWID) -- ----------------------------------------------------------------------- GEN_AWADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate begin REG_AWADDR: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awaddr_pipe (i) <= AXI_AWADDR (i); else axi_awaddr_pipe (i) <= axi_awaddr_pipe (i); end if; end if; end process REG_AWADDR; end generate GEN_AWADDR; ----------------------------------------------------------------------- -- Register AWID REG_AWID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awid_pipe <= AXI_AWID; else axi_awid_pipe <= axi_awid_pipe; end if; end if; end process REG_AWID; --------------------------------------------------------------------------- -- In parallel to AWADDR pipeline and AWID -- Use same control signals to capture AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST. -- Register AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST REG_AWCTRL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then axi_awsize_pipe <= AXI_AWSIZE; axi_awlen_pipe <= AXI_AWLEN; axi_awburst_pipe <= AXI_AWBURST; else axi_awsize_pipe <= axi_awsize_pipe; axi_awlen_pipe <= axi_awlen_pipe; axi_awburst_pipe <= axi_awburst_pipe; end if; end if; end process REG_AWCTRL; --------------------------------------------------------------------------- -- Create signals that indicate value of AXI_AWLEN in pipeline stage -- Used to decode length of burst when BRAM address can be loaded early -- when pipeline is full. -- -- Add early decode of AWBURST in pipeline. REG_AWLEN_PIPE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (awaddr_pipe_ld = '1') then -- Create merge to decode AWLEN of ONE or TWO if (AXI_AWLEN = AXI_AWLEN_ONE) or (AXI_AWLEN = AXI_AWLEN_TWO) then axi_awlen_pipe_1_or_2 <= '1'; else axi_awlen_pipe_1_or_2 <= '0'; end if; -- Early decode on value in pipeline of AWBURST if (AXI_AWBURST = C_AXI_BURST_FIXED) then axi_awburst_pipe_fixed <= '1'; else axi_awburst_pipe_fixed <= '0'; end if; else axi_awlen_pipe_1_or_2 <= axi_awlen_pipe_1_or_2; axi_awburst_pipe_fixed <= axi_awburst_pipe_fixed; end if; end if; end process REG_AWLEN_PIPE; --------------------------------------------------------------------------- -- Create full flag for AWADDR pipeline -- Set when write address register is loaded. -- Cleared when write address stored in register is loaded into BRAM -- address counter. REG_WRADDR_FULL: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then axi_awaddr_full <= '0'; elsif (awaddr_pipe_ld = '1') then axi_awaddr_full <= '1'; else axi_awaddr_full <= axi_awaddr_full; end if; end if; end process REG_WRADDR_FULL; --------------------------------------------------------------------------- end generate GEN_AW_PIPE_DUAL; --------------------------------------------------------------------------- -- Generate: GEN_DUAL_ADDR_CNT -- Purpose: Instantiate BRAM address counter unique for wr_chnl logic -- only when controller configured in dual port mode. --------------------------------------------------------------------------- GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate begin ---------------------------------------------------------------------------- -- Replace I_ADDR_CNT module usage of pf_counter in proc_common library. -- Only need to use lower 12-bits of address due to max AXI burst size -- Since AXI guarantees bursts do not cross 4KB boundary, the counting part -- of I_ADDR_CNT can be reduced to max 4KB. -- -- Counter size is adjusted based on data width of BRAM. -- For example, 32-bit data width BRAM, BRAM_Addr (1:0) -- are fixed at "00". So, counter increments from -- (C_AXI_ADDR_WIDTH - 1 : C_BRAM_ADDR_ADJUST). ---------------------------------------------------------------------------- I_ADDR_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Reset usage differs from RD CHNL if (bram_addr_rst = '1') then bram_addr_int <= (others => '0'); elsif (bram_addr_ld_en_mod = '1') then bram_addr_int <= bram_addr_ld; elsif (bram_addr_inc_mod = '1') then bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <= bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12); bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <= std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1); end if; end if; end process I_ADDR_CNT; -- Set defaults to shared address counter -- Only used in single port configurations Sng_BRAM_Addr_Rst <= '0'; Sng_BRAM_Addr_Ld_En <= '0'; Sng_BRAM_Addr_Ld <= (others => '0'); Sng_BRAM_Addr_Inc <= '0'; end generate GEN_DUAL_ADDR_CNT; --------------------------------------------------------------------------- -- Generate: GEN_SNG_ADDR_CNT -- Purpose: When configured in single port BRAM mode, address counter -- is shared with rd_chnl module. Assign output signals here -- to counter instantiation at full_axi module level. --------------------------------------------------------------------------- GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate begin Sng_BRAM_Addr_Rst <= bram_addr_rst; Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod; Sng_BRAM_Addr_Ld <= bram_addr_ld; Sng_BRAM_Addr_Inc <= bram_addr_inc_mod; bram_addr_int <= Sng_BRAM_Addr; end generate GEN_SNG_ADDR_CNT; --------------------------------------------------------------------------- -- -- Add BRAM counter reset for @ end of transfer -- -- Create a unique BRAM address reset signal -- If the write transaction is throttling on the AXI bus, then -- the BRAM EN may get negated during the write transfer -- -- Use combinatorial output from SM, bram_addr_rst_cmb, but ensure the -- BRAM address is not reset while loading a new address. bram_addr_rst <= (not (S_AXI_AResetn)) or (bram_addr_rst_cmb and not (bram_addr_ld_en_mod) and not (bram_addr_inc_mod)); --------------------------------------------------------------------------- -- BRAM address counter load mux -- -- Either load BRAM counter directly from AXI bus or from stored registered value -- -- Added bram_addr_ld_wrap for loading on wrap burst types -- Use registered signal to indicate current operation is a WRAP burst -- -- Do not load bram_addr_ld_wrap when bram_addr_ld_en signal is asserted at beginning of write burst -- BRAM address counter load. Due to condition when max_wrap_burst_mod remains asserted, due to BRAM address -- counter not incrementing (at the end of the previous write burst). -- bram_addr_ld <= bram_addr_ld_wrap when -- (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else -- axi_awaddr_pipe (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR) -- when (awaddr_pipe_sel = '1') else -- AXI_AWADDR (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- Replace C_BRAM_ADDR_SIZE w/ C_AXI_ADDR_WIDTH parameter usage bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else axi_awaddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) when (awaddr_pipe_sel = '1') else AXI_AWADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); --------------------------------------------------------------------------- -- On wrap burst max loads (simultaneous BRAM address increment is asserted). -- Ensure that load has higher priority over increment. -- Use registered signal to indicate current operation is a WRAP burst -- bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or -- (max_wrap_burst_mod = '1' and -- curr_wrap_burst_reg = '1' and -- bram_addr_inc_mod = '1')) -- else '0'; -- Use duplicate version of bram_addr_ld_en in effort -- to reduce fanout of signal routed to BRAM address counter bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_inc_wrap_mod = '1')) else '0'; -- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal -- logic. No need for the check if the current operation is NOT a fixed AND a wrap -- burst. The transfer will be one or the other. -- Found issue when narrow FIXED length burst is incorrectly -- incrementing BRAM address counter bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0') else narrow_bram_addr_inc_re; ---------------------------------------------------------------------------- -- Handling for WRAP burst types -- -- For WRAP burst types, the counter value will roll over when the burst -- boundary is reached. -- Boundary is reached based on ARSIZE and ARLEN. -- -- Goal is to minimize muxing on initial load of counter value. -- On WRAP burst types, detect when the max address is reached. -- When the max address is reached, re-load counter with lower -- address value set to '0'. ---------------------------------------------------------------------------- -- Detect valid WRAP burst types curr_wrap_burst <= '1' when (curr_awburst = C_AXI_BURST_WRAP) else '0'; -- Detect INCR & FIXED burst type operations curr_incr_burst <= '1' when (curr_awburst = C_AXI_BURST_INCR) else '0'; curr_fixed_burst <= '1' when (curr_awburst = C_AXI_BURST_FIXED) else '0'; ---------------------------------------------------------------------------- -- Register curr_wrap_burst signal when BRAM address counter is initially -- loaded REG_CURR_WRAP_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset same as BRAM address counter if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then curr_wrap_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_wrap_burst_reg <= curr_wrap_burst; else curr_wrap_burst_reg <= curr_wrap_burst_reg; end if; end if; end process REG_CURR_WRAP_BRST; ---------------------------------------------------------------------------- -- Register curr_fixed_burst signal when BRAM address counter is initially -- loaded REG_CURR_FIXED_BRST: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Add reset same as BRAM address counter if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then curr_fixed_burst_reg <= '0'; elsif (bram_addr_ld_en = '1') then curr_fixed_burst_reg <= curr_fixed_burst; else curr_fixed_burst_reg <= curr_fixed_burst_reg; end if; end if; end process REG_CURR_FIXED_BRST; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Instance: I_WRAP_BRST -- -- Description: -- -- Instantiate WRAP_BRST module -- Logic to generate the wrap around value to load into the BRAM address -- counter on WRAP burst transactions. -- WRAP value is based on current AWLEN, AWSIZE (for narrows) and -- data width of BRAM module. -- --------------------------------------------------------------------------- I_WRAP_BRST : entity work.wrap_brst generic map ( C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ) port map ( S_AXI_AClk => S_AXI_AClk , S_AXI_AResetn => S_AXI_AResetn , curr_axlen => curr_awlen , curr_axsize => curr_awsize , curr_narrow_burst => curr_narrow_burst , narrow_bram_addr_inc_re => narrow_bram_addr_inc_re , bram_addr_ld_en => bram_addr_ld_en , bram_addr_ld => bram_addr_ld , bram_addr_int => bram_addr_int , bram_addr_ld_wrap => bram_addr_ld_wrap , max_wrap_burst_mod => max_wrap_burst_mod ); --------------------------------------------------------------------------- -- Generate: GEN_WO_NARROW -- Purpose: Create BRAM address increment signal when narrow bursts -- are disabled. --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate begin -- For non narrow burst operations, use bram_addr_inc from data SM. -- Add in check that burst type is not FIXED, curr_fixed_burst_reg bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg); -- The signal, curr_narrow_burst should always be set to '0' when narrow bursts -- are disabled. curr_narrow_burst <= '0'; narrow_bram_addr_inc_re <= '0'; end generate GEN_WO_NARROW; --------------------------------------------------------------------------- -- Only instantiate NARROW_CNT and supporting logic when narrow transfers -- are supported and utilized by masters in the AXI system. -- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this. --------------------------------------------------------------------------- -- Generate: GEN_NARROW_CNT -- Purpose: Instantiate narrow counter and logic when narrow -- operation support is enabled. -- And, only instantiate logic for narrow operations when -- AXI bus protocol is not set for AXI-LITE. --------------------------------------------------------------------------- GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin -- Based on current operation being a narrow burst, hold off BRAM -- address increment until narrow burst fits BRAM data width. -- For non narrow burst operations, use bram_addr_inc from data SM. -- Add in check that burst type is not FIXED, curr_fixed_burst_reg bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') -- else narrow_bram_addr_inc_re; -- Seeing incorrect BRAM address increment on narrow -- fixed length burst operations. -- Add this check for curr_fixed_burst_reg else (narrow_bram_addr_inc_re and not (curr_fixed_burst_reg)); --------------------------------------------------------------------------- -- -- Generate seperate smaller counter for narrow burst operations -- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library. -- -- Counter size is adjusted based on size of data burst. -- -- For example, 32-bit data width BRAM, minimum narrow width -- burst is 8 bits resulting in a count 3 downto 0. So the -- minimum counter width = 2 bits. -- -- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst -- is 8 bits resulting in a count 31 downto 0. So the -- minimum counter width = 5 bits. -- -- Size of counter = C_NARROW_BURST_CNT_LEN -- --------------------------------------------------------------------------- I_NARROW_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (narrow_addr_rst = '1') then narrow_addr_int <= (others => '0'); -- Load narrow address counter elsif (narrow_addr_ld_en = '1') then narrow_addr_int <= narrow_burst_cnt_ld_mod; -- Decrement ONLY (no increment functionality) elsif (narrow_addr_dec = '1') then narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <= std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1); end if; end if; end process I_NARROW_CNT; --------------------------------------------------------------------------- narrow_addr_rst <= not (S_AXI_AResetn); -- Narrow burst counter load mux -- Modify narrow burst count load value based on -- unalignment of AXI address value -- Account for INCR burst types at unaligned addresses narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else narrow_burst_cnt_ld_reg; narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0'; narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re; narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and (curr_narrow_burst = '1') -- Ensure that narrow address counter doesn't -- flag max or get loaded to -- reset narrow counter until AXI read data -- bus has acknowledged current -- data on the AXI bus. Use rd_adv_buf signal -- to indicate the non throttle -- condition on the AXI bus. and (bram_addr_inc = '1') else '0'; -- Detect rising edge of narrow_bram_addr_inc REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_bram_addr_inc_d1 <= '0'; else narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc; end if; end if; end process REG_NARROW_BRAM_ADDR_INC; narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and (narrow_bram_addr_inc_d1 = '0') else '0'; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT; --------------------------------------------------------------------------- -- Generate: GEN_AWREADY -- Purpose: AWREADY is only created here when in dual port BRAM mode. --------------------------------------------------------------------------- GEN_AWREADY: if (C_SINGLE_PORT_BRAM = 0) generate begin -- v1.03a ---------------------------------------------------------------------------- -- AXI_AWREADY Output Register -- Description: Keep AXI_AWREADY output asserted until AWADDR pipeline -- is full. When a full condition is reached, negate -- AWREADY as another AW address can not be accepted. -- Add condition to keep AWReady asserted if loading current --- AWADDR pipeline value into the BRAM address counter. -- Indicated by assertion of bram_addr_ld_en & awaddr_pipe_sel. -- ---------------------------------------------------------------------------- REG_AWREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_awready_int <= '0'; -- Detect end of S_AXI_AResetn to assert AWREADY and accept -- new AWADDR values elsif (axi_aresetn_re_reg = '1') or (bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then axi_awready_int <= '1'; elsif (awaddr_pipe_ld = '1') then axi_awready_int <= '0'; else axi_awready_int <= axi_awready_int; end if; end if; end process REG_AWREADY; ---------------------------------------------------------------------------- -- Need to detect end of reset cycle to assert AWREADY on AXI bus REG_ARESETN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then axi_aresetn_d1 <= S_AXI_AResetn; axi_aresetn_d2 <= axi_aresetn_d1; axi_aresetn_re_reg <= axi_aresetn_re; end if; end process REG_ARESETN; -- Create combinatorial RE detect of S_AXI_AResetn axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0'; end generate GEN_AWREADY; ---------------------------------------------------------------------------- -- Specify current AWSIZE signal -- Address pipeline MUX curr_awsize <= axi_awsize_pipe when (awaddr_pipe_sel = '1') else AXI_AWSIZE; -- Register curr_awsize when bram_addr_ld_en = '1' REG_AWSIZE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_awsize_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then curr_awsize_reg <= curr_awsize; else curr_awsize_reg <= curr_awsize_reg; end if; end if; end process REG_AWSIZE; --------------------------------------------------------------------------- -- -- Generate: GEN_NARROW_EN -- Purpose: Only instantiate logic to determine if current burst -- is a narrow burst when narrow bursting logic is supported. -- --------------------------------------------------------------------------- GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin ----------------------------------------------------------------------- -- Determine "narrow" burst transfers -- Compare the AWSIZE to the BRAM data width ----------------------------------------------------------------------- -- v1.03a -- Detect if current burst operation is of size /= to the full -- AXI data bus width. If not, then the current operation is a -- "narrow" burst. curr_narrow_burst_cmb <= '1' when (curr_awsize /= C_AXI_SIZE_MAX) else '0'; --------------------------------------------------------------------------- curr_narrow_burst_en <= '1' when (bram_addr_ld_en = '1') and (curr_awlen /= AXI_AWLEN_ONE) and (curr_fixed_burst = '0') else '0'; -- Register flag indicating the current operation -- is a narrow write burst NARROW_BURST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then -- Need to reset this flag at end of narrow burst operation -- Use handshaking signals on AXI if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Check for back to back narrow burst. If that is the case, then -- do not clear curr_narrow_burst flag. (axi_wlast_re = '1' and curr_narrow_burst_en = '0' -- If ECC is enabled, no clear to curr_narrow_burst when WLAST is asserted -- this causes the BRAM address to incorrectly get asserted on the last -- beat in the burst (due to delay in RMW logic) and C_ECC = 0) then curr_narrow_burst <= '0'; elsif (curr_narrow_burst_en = '1') then curr_narrow_burst <= curr_narrow_burst_cmb; end if; end if; end process NARROW_BURST_REG; --------------------------------------------------------------------------- -- Detect RE of AXI_WLAST -- Only used when narrow bursts are enabled. WLAST_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wlast_d1 <= '0'; else -- axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod; -- CR # 609695 axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod and AXI_WVALID; end if; end if; end process WLAST_REG; -- axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod) and not (axi_wlast_d1); -- CR # 609695 axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod and AXI_WVALID) and not (axi_wlast_d1); end generate GEN_NARROW_EN; --------------------------------------------------------------------------- -- Generate registered flag that active burst is a "narrow" burst -- and load narrow burst counter --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_NARROW_CNT_LD -- Purpose: Only instantiate logic to determine narrow burst counter -- load value when narrow bursts are enabled. -- --------------------------------------------------------------------------- GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate signal curr_awsize_unsigned : unsigned (2 downto 0) := (others => '0'); signal axi_byte_div_curr_awsize : integer := 1; begin -- v1.03a -- Create narrow burst counter load value based on current operation -- "narrow" data width (indicated by value of AWSIZE). curr_awsize_unsigned <= unsigned (curr_awsize); -- XST does not support divisors that are not constants and powers of 2. -- Create process to create a fixed value for divisor. -- Replace this statement: -- narrow_burst_cnt_ld <= std_logic_vector ( -- to_unsigned ( -- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_awsize_unsigned))) ) - 1, -- C_NARROW_BURST_CNT_LEN)); -- -- With this new process and subsequent signal assignment: -- DIV_AWSIZE: process (curr_awsize_unsigned) -- begin -- -- case (to_integer (curr_awsize_unsigned)) is -- when 0 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1; -- when 1 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2; -- when 2 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4; -- when 3 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8; -- when 4 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16; -- when 5 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32; -- when 6 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64; -- when 7 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128; -- --coverage off -- when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES; -- --coverage on -- end case; -- -- end process DIV_AWSIZE; -- w/ CR # 609695 -- With this new process and subsequent signal assignment: DIV_AWSIZE: process (curr_awsize_unsigned) begin case (curr_awsize_unsigned) is when "000" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1; when "001" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2; when "010" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4; when "011" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8; when "100" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16; when "101" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32; when "110" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64; when "111" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128; --coverage off when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES; --coverage on end case; end process DIV_AWSIZE; --------------------------------------------------------------------------- -- Create narrow burst count load value. -- -- Size is based on [C_NARROW_BURST_CNT_LEN-1 : 0] -- For 32-bit BRAM, C_NARROW_BURST_CNT_LEN = 2. -- For 64-bit BRAM, C_NARROW_BURST_CNT_LEN = 3. -- For 128-bit BRAM, C_NARROW_BURST_CNT_LEN = 4. (etc.) -- -- Signal, narrow_burst_cnt_ld signal is sized according to C_AXI_DATA_WIDTH. -- Updated else clause for simulation warnings w/ CR # 609695 narrow_burst_cnt_ld <= std_logic_vector ( to_unsigned ( (axi_byte_div_curr_awsize) - 1, C_NARROW_BURST_CNT_LEN)) when (axi_byte_div_curr_awsize > 0) else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN)); --------------------------------------------------------------------------- -- Register narrow_burst_cnt_ld REG_NAR_BRST_CNT_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then narrow_burst_cnt_ld_reg <= (others => '0'); elsif (bram_addr_ld_en = '1') then narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld; else narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg; end if; end if; end process REG_NAR_BRST_CNT_LD; --------------------------------------------------------------------------- end generate GEN_NARROW_CNT_LD; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_awburst <= axi_awburst_pipe when (awaddr_pipe_sel = '1') else AXI_AWBURST; ---------------------------------------------------------------------------- -- Specify current AWBURST signal -- Input address pipeline MUX curr_awlen <= axi_awlen_pipe when (awaddr_pipe_sel = '1') else AXI_AWLEN; -- Duplicate early decode of AWLEN value to use in wr_b2b_elgible logic REG_CURR_AWLEN: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then curr_awlen_reg_1_or_2 <= '0'; elsif (bram_addr_ld_en = '1') then -- Create merge to decode AWLEN of ONE or TWO if (curr_awlen = AXI_AWLEN_ONE) or (curr_awlen = AXI_AWLEN_TWO) then curr_awlen_reg_1_or_2 <= '1'; else curr_awlen_reg_1_or_2 <= '0'; end if; else curr_awlen_reg_1_or_2 <= curr_awlen_reg_1_or_2; end if; end if; end process REG_CURR_AWLEN; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_UA_NARROW -- Purpose: Only instantiate logic for burst narrow WRAP operations when -- AXI bus protocol is not set for AXI-LITE and narrow -- burst operations are supported. -- --------------------------------------------------------------------------- GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate begin --------------------------------------------------------------------------- -- New logic to detect unaligned address on a narrow WRAP burst transaction. -- If this condition is met, then the narrow burst counter will be -- initially loaded with an offset value corresponding to the unalignment -- in the ARADDR value. -- Create a sub module for all logic to determine the narrow burst counter -- offset value on unaligned WRAP burst operations. -- Module generates the following signals: -- -- => curr_ua_narrow_wrap, to indicate the current -- operation is an unaligned narrow WRAP burst. -- -- => curr_ua_narrow_incr, to load narrow burst counter -- for unaligned INCR burst operations. -- -- => ua_narrow_load, narrow counter load value. -- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0) -- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Instance: I_UA_NARROW -- -- Description: -- -- Creates a narrow burst count load value when an operation -- is an unaligned narrow WRAP or INCR burst type. Used by -- I_NARROW_CNT module. -- -- Logic is customized for each C_AXI_DATA_WIDTH. --------------------------------------------------------------------------- I_UA_NARROW : entity work.ua_narrow generic map ( C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH , C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR , C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN ) port map ( curr_wrap_burst => curr_wrap_burst , -- in curr_incr_burst => curr_incr_burst , -- in bram_addr_ld_en => bram_addr_ld_en , -- in curr_axlen => curr_awlen , -- in curr_axsize => curr_awsize , -- in curr_axaddr_lsb => curr_awaddr_lsb , -- in curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out curr_ua_narrow_incr => curr_ua_narrow_incr , -- out ua_narrow_load => ua_narrow_load -- out ); -- Use in all C_AXI_DATA_WIDTH generate statements -- Only probe least significant BRAM address bits -- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0. curr_awaddr_lsb <= axi_awaddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) when (awaddr_pipe_sel = '1') else AXI_AWADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0); end generate GEN_UA_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_SNG -- Purpose: If single port BRAM configuration, set all AW flags from -- logic generated in sng_port_arb module. -- --------------------------------------------------------------------------- GEN_AW_SNG: if (C_SINGLE_PORT_BRAM = 1) generate begin aw_active <= Arb2AW_Active; bram_addr_ld_en <= aw_active_re; AW2Arb_Active_Clr <= aw_active_clr; AW2Arb_Busy <= wr_busy_reg; AW2Arb_BVALID_Cnt <= bvalid_cnt; end generate GEN_AW_SNG; -- Rising edge detect of aw_active -- For single port configurations, aw_active = Arb2AW_Active. -- For dual port configurations, aw_active generated in ADDR SM. RE_AW_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then aw_active_d1 <= '0'; else aw_active_d1 <= aw_active; end if; end if; end process RE_AW_ACT; aw_active_re <= '1' when (aw_active = '1' and aw_active_d1 = '0') else '0'; --------------------------------------------------------------------------- -- -- Generate: GEN_AW_DUAL -- Purpose: Generate AW control state machine logic only when AXI4 -- controller is configured for dual port mode. In dual port -- mode, wr_chnl has full access over AW & port A of BRAM. -- --------------------------------------------------------------------------- GEN_AW_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate begin AW2Arb_Active_Clr <= '0'; -- Only used in single port case AW2Arb_Busy <= '0'; -- Only used in single port case AW2Arb_BVALID_Cnt <= (others => '0'); ---------------------------------------------------------------------------- REG_LAST_DATA_ACK: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then last_data_ack_mod <= '0'; else -- last_data_ack_mod <= AXI_WLAST; -- CR # 609695 last_data_ack_mod <= AXI_WLAST and AXI_WVALID and axi_wready_int_mod; end if; end if; end process REG_LAST_DATA_ACK; ---------------------------------------------------------------------------- --------------------------------------------------------------------------- -- WR ADDR State Machine -- -- Description: Central processing unit for AXI write address -- channel interface handling and handshaking. -- -- Outputs: awaddr_pipe_ld Combinatorial -- awaddr_pipe_sel -- bram_addr_ld_en -- -- -- -- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine. --------------------------------------------------------------------------- WR_ADDR_SM_CMB_PROCESS: process ( AXI_AWVALID, bvalid_cnt_max, axi_awaddr_full, aw_active, wr_b2b_elgible, last_data_ack_mod, wr_addr_sm_cs ) begin -- assign default values for state machine outputs wr_addr_sm_ns <= wr_addr_sm_cs; awaddr_pipe_ld_i <= '0'; bram_addr_ld_en_i <= '0'; aw_active_set_i <= '0'; case wr_addr_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Check for pending operation in address pipeline that may -- be elgible for back-to-back performance to BRAM. -- Prevent loading BRAM address counter if BID FIFO can not -- store the AWID value. Check the BVALID counter. if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; -- Ensure AWVALID is recognized. -- Address pipeline may be loaded, but BRAM counter -- can not be loaded if at max of BID FIFO. elsif (AXI_AWVALID = '1') then -- If address pipeline is full -- AWReady output is negated -- If write address logic is ready for new operation -- Load BRAM address counter and set aw_active = '1' -- If address pipeline is already full to start next operation -- load address counter from pipeline. -- Prevent loading BRAM address counter if BID FIFO can not -- store the AWID value. Check the BVALID counter. -- Remain in this state if (aw_active = '0') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Stay in this state to capture AWVALID if asserted -- in next clock cycle. bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; -- Address counter is currently busy. -- No check on BVALID counter for address pipeline load. -- Only the BRAM address counter is checked for BID FIFO capacity. else -- Check if AWADDR pipeline is not full and can be loaded if (axi_awaddr_full = '0') then wr_addr_sm_ns <= LD_AWADDR; awaddr_pipe_ld_i <= '1'; end if; end if; -- aw_active -- Pending operation in pipeline that is waiting -- until current operation is complete (aw_active = '0') elsif (axi_awaddr_full = '1') and (aw_active = '0') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then wr_addr_sm_ns <= IDLE; -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; end if; -- AWVALID ---------------------------- LD_AWADDR State --------------------------- when LD_AWADDR => wr_addr_sm_ns <= IDLE; if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Load BRAM address counter from pipelined value bram_addr_ld_en_i <= '1'; aw_active_set_i <= '1'; end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_addr_sm_ns <= IDLE; --coverage on end case; end process WR_ADDR_SM_CMB_PROCESS; --------------------------------------------------------------------------- -- CR # 582705 -- Ensure combinatorial SM output signals do not get set before -- the end of the reset (and ARREAADY can be set). bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2; aw_active_set <= aw_active_set_i and axi_aresetn_d2; awaddr_pipe_ld <= awaddr_pipe_ld_i and axi_aresetn_d2; WR_ADDR_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- if (S_AXI_AResetn = C_RESET_ACTIVE) then -- CR # 582705 -- Ensure that ar_active does not get asserted (from SM) before -- the end of reset and the ARREADY flag is set. if (axi_aresetn_d2 = C_RESET_ACTIVE) then wr_addr_sm_cs <= IDLE; else wr_addr_sm_cs <= wr_addr_sm_ns; end if; end if; end process WR_ADDR_SM_REG_PROCESS; --------------------------------------------------------------------------- -- Asserting awaddr_pipe_sel outside of SM logic -- The BRAM address counter will get loaded with value in AWADDR pipeline -- when data is stored in the AWADDR pipeline. awaddr_pipe_sel <= '1' when (axi_awaddr_full = '1') else '0'; --------------------------------------------------------------------------- -- Register for aw_active REG_AW_ACT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- CR # 582705 -- if (S_AXI_AResetn = C_RESET_ACTIVE) then if (axi_aresetn_d2 = C_RESET_ACTIVE) then aw_active <= '0'; elsif (aw_active_set = '1') then aw_active <= '1'; elsif (aw_active_clr = '1') then aw_active <= '0'; else aw_active <= aw_active; end if; end if; end process REG_AW_ACT; --------------------------------------------------------------------------- end generate GEN_AW_DUAL; --------------------------------------------------------------------------- -- *** AXI Write Data Channel Interface *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- AXI WrData Buffer/Register --------------------------------------------------------------------------- GEN_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin REG_WRDATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (wrdata_reg_ld = '1') then bram_wrdata_int (i) <= AXI_WDATA (i); else bram_wrdata_int (i) <= bram_wrdata_int (i); end if; end if; end process REG_WRDATA; end generate GEN_WRDATA; --------------------------------------------------------------------------- -- Generate: GEN_WR_NO_ECC -- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA -- and AXI_WSTRBs when C_ECC is disabled. --------------------------------------------------------------------------- GEN_WR_NO_ECC: if C_ECC = 0 generate begin --------------------------------------------------------------------------- -- AXI WSTRB Buffer/Register -- Use AXI write data channel data strobe signals to generate BRAM WE. --------------------------------------------------------------------------- REG_BRAM_WE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Ensure we don't clear WE when loading subsequent WSTRB value if (S_AXI_AResetn = C_RESET_ACTIVE) or (clr_bram_we = '1' and bram_we_ld = '0') then bram_we_int <= (others => '0'); elsif (bram_we_ld = '1') then bram_we_int <= AXI_WSTRB; else bram_we_int <= bram_we_int; end if; end if; end process REG_BRAM_WE; ---------------------------------------------------------------------------- -- New logic to detect if pending operation in AWADDR pipeline is -- elgible for back-to-back no "bubble" performance. And BRAM address -- counter can be loaded upon last BRAM address presented for the current -- operation. -- This condition exists when the AWADDR pipeline is full and the pending -- operation is a burst >= length of two data beats. -- And not a FIXED burst type (must be INCR or WRAP type). -- -- Narrow bursts are be neglible -- -- Add check to complete current single and burst of two data bursts -- prior to loading BRAM counter wr_b2b_elgible <= '1' when (axi_awaddr_full = '1') and -- Replace comparator logic here with register signal (pre pipeline stage -- on axi_awlen_pipe value -- Use merge in decode of ONE or TWO (axi_awlen_pipe_1_or_2 /= '1') and (axi_awburst_pipe_fixed /= '1') and -- Use merge in decode of ONE or TWO (curr_awlen_reg_1_or_2 /= '1') else '0'; ---------------------------------------------------------------------------- end generate GEN_WR_NO_ECC; --------------------------------------------------------------------------- -- Generate: GEN_WR_ECC -- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA -- and AXI_WSTRBs when C_ECC is enabled. --------------------------------------------------------------------------- GEN_WR_ECC: if C_ECC = 1 generate begin wr_b2b_elgible <= '0'; --------------------------------------------------------------------------- -- AXI WSTRB Buffer/Register -- Use AXI write data channel data strobe signals to generate BRAM WE. --------------------------------------------------------------------------- REG_BRAM_WE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Ensure we don't clear WE when loading subsequent WSTRB value if (S_AXI_AResetn = C_RESET_ACTIVE) or (reset_bram_we = '1') then bram_we_int <= (others => '0'); elsif (set_bram_we = '1') then bram_we_int <= (others => '1'); else bram_we_int <= bram_we_int; end if; end if; end process REG_BRAM_WE; end generate GEN_WR_ECC; ----------------------------------------------------------------------- -- v1.03a ----------------------------------------------------------------------- -- -- Implement WREADY to be a registered output. Used by all configurations. -- This will disable the back-to-back streamlined WDATA -- for write operations to BRAM. -- ----------------------------------------------------------------------- REG_WREADY: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wready_int_mod <= '0'; -- Keep AXI WREADY asserted unless write data register is full -- Use combinatorial signal from SM. elsif (axi_wdata_full_cmb = '1') then axi_wready_int_mod <= '0'; else axi_wready_int_mod <= '1'; end if; end if; end process REG_WREADY; --------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- Generate: GEN_WDATA_SM_ECC -- Purpose: Create seperate SM for ECC read-modify-write logic. -- Only used in single port BRAM mode. So, no address -- pipelining. Must use aw_active from arbitration logic -- to determine start of write to BRAM. -- ---------------------------------------------------------------------------- -- Test using same write data SM for single or dual port configuration. -- The difference is the source of aw_active. In a single port configuration, -- the aw_active is coming from the arbiter SM. In a dual port configuration, -- the aw_active is coming from the write address SM in this module. GEN_WDATA_SM_ECC: if C_ECC = 1 generate begin -- Unused in this SM configuration bram_we_ld <= '0'; bram_addr_rst_cmb <= '0'; -- Output only used by ECC register module. Active_Wr <= active_wr_reg; --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking when ECC is enabled. SM will handle -- each transaction as a read-modify-write to ensure -- the correct ECC bits are stored in BRAM. -- -- Dedicated to single port BRAM interface. Transaction -- is not initiated until valid AWADDR is arbitration, -- ie. aw_active will be asserted. SM can do early reads -- while waiting for WVALID to be asserted. -- -- Valid AWADDR recieve indicator comes from arbitration -- logic (aw_active will be asserted). -- -- Outputs: Name Type -- -- aw_active_clr Not Registered -- axi_wdata_full_reg Registered -- wrdata_reg_ld Not Registered -- bvalid_cnt_inc Not Registered -- bram_addr_inc Not Registered -- bram_en_int Registered -- reset_bram_we Not Registered -- set_bram_we Not Registered -- -- -- WR_DATA_ECC_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_ECC_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_ECC_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, aw_active, wr_busy_reg, axi_wdata_full_reg, axi_wr_burst, AXI_BREADY, active_wr_reg, wr_data_ecc_sm_cs ) begin -- Assign default values for state machine outputs wr_data_ecc_sm_ns <= wr_data_ecc_sm_cs; aw_active_clr <= '0'; wr_busy_cmb <= wr_busy_reg; bvalid_cnt_inc <= '0'; wrdata_reg_ld <= '0'; reset_bram_we <= '0'; set_bram_we_cmb <= '0'; bram_en_cmb <= '0'; bram_addr_inc <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; axi_wr_burst_cmb <= axi_wr_burst; active_wr_cmb <= active_wr_reg; case wr_data_ecc_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Prior to AWVALID assertion, WVALID may be asserted -- and data accepted into WDATA register. -- Catch this condition and ensure the register full flag is set. -- Check that data pipeline is not already full. if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- Check if AWVALID is asserted & wins arbitration if (aw_active = '1') then active_wr_cmb <= '1'; -- Set flag that RMW SM is active -- Controls mux select for BRAM and ECC register module -- (Set to '1' wr_chnl or '0' for rd_chnl control) bram_en_cmb <= '1'; -- Initiate BRAM read transfer reset_bram_we <= '1'; -- Disable Port A write enables -- Will proceed to read-modify-write if we get a -- valid write address early (before WVALID) wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; -- WVALID ------------------------- RMW_RD_DATA State ------------------------- when RMW_RD_DATA => -- Check if data to write is available in data pipeline if (axi_wdata_full_reg = '1') then wr_data_ecc_sm_ns <= RMW_CHK_DATA; -- Else may have address, but not yet data from W channel elsif (AXI_WVALID = '1') then -- Ensure that WDATA pipeline is marked as full, so WREADY negates axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data wrdata_reg_ld <= '1'; -- Load write data register -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not wr_data_ecc_sm_ns <= RMW_CHK_DATA; else -- Hold here and wait for write data wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; ------------------------- RMW_CHK_DATA State ------------------------- when RMW_CHK_DATA => -- New state here to add register stage on calculating -- checkbits for read data and then muxing/creating new -- checkbits for write cycle. -- Go immediately to MODIFY stage in RMW sequence wr_data_ecc_sm_ns <= RMW_MOD_DATA; set_bram_we_cmb <= '1'; -- Enable all WEs to BRAM ------------------------- RMW_MOD_DATA State ------------------------- when RMW_MOD_DATA => -- Modify clock cycle in RMW sequence -- Only reach this state after a read AND we have data -- in the write data pipeline to modify and subsequently write to BRAM. bram_en_cmb <= '1'; -- Initiate BRAM write transfer -- Can clear WDATA pipeline full condition flag if (axi_wr_burst = '1') then axi_wdata_full_cmb <= '0'; end if; wr_data_ecc_sm_ns <= RMW_WR_DATA; -- Go to write data to BRAM ------------------------- RMW_WR_DATA State ------------------------- when RMW_WR_DATA => -- Check if last data beat in a burst (or the write is a single) if (axi_wr_burst = '0') then -- Can clear WDATA pipeline full condition flag now that -- write data has gone out to BRAM (for single data transfers) axi_wdata_full_cmb <= '0'; bvalid_cnt_inc <= '1'; -- Set flag to assert BVALID and increment counter wr_data_ecc_sm_ns <= IDLE; -- Go back to IDLE, BVALID assertion is seperate wr_busy_cmb <= '0'; -- Clear flag to arbiter active_wr_cmb <= '0'; -- Clear flag (wr_chnl is done accessing BRAM) -- Used for single port arbitration SM axi_wr_burst_cmb <= '0'; aw_active_clr <= '1'; -- Clear aw_active flag reset_bram_we <= '1'; -- Disable Port A write enables else -- Continue with read-modify-write sequence for write burst -- If next data beat is available on AXI, capture the data if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data -- w/ CR # 609695 -- -- -- Set flag to check if single or not -- if (AXI_WLAST = '1') then -- axi_wr_burst_cmb <= '0'; -- else -- axi_wr_burst_cmb <= '1'; -- end if; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- After write cycle (in RMW) => Increment BRAM address counter bram_addr_inc <= '1'; bram_en_cmb <= '1'; -- Initiate BRAM read transfer reset_bram_we <= '1'; -- Disable Port A write enables -- Will proceed to read-modify-write if we get a -- valid write address early (before WVALID) wr_data_ecc_sm_ns <= RMW_RD_DATA; end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_data_ecc_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_ECC_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_ECC_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_ecc_sm_cs <= IDLE; bram_en_int <= '0'; axi_wdata_full_reg <= '0'; wr_busy_reg <= '0'; active_wr_reg <= '0'; set_bram_we <= '0'; else wr_data_ecc_sm_cs <= wr_data_ecc_sm_ns; bram_en_int <= bram_en_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; wr_busy_reg <= wr_busy_cmb; active_wr_reg <= active_wr_cmb; set_bram_we <= set_bram_we_cmb; end if; end if; end process WR_DATA_ECC_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_ECC; -- v1.03a ---------------------------------------------------------------------------- -- -- Generate: GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY -- Purpose: Create seperate SM use case of no ECC (no read-modify-write) -- and single port BRAM configuration (no back to back operations -- are supported). Must wait for aw_active from arbiter to indicate -- control on BRAM interface. -- ---------------------------------------------------------------------------- GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY: if C_ECC = 0 and C_SINGLE_PORT_BRAM = 1 generate begin -- Unused in this SM configuration wr_busy_cmb <= '0'; -- Unused wr_busy_reg <= '0'; -- Unused active_wr_cmb <= '0'; -- Unused active_wr_reg <= '0'; -- Unused Active_Wr <= '0'; -- Unused --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- aw_active_clr Not Registered -- bvalid_cnt_inc Not Registered -- wrdata_reg_ld Not Registered -- bram_we_ld Not Registered -- bram_en_int Registered -- clr_bram_we Registered -- bram_addr_inc Not Registered -- wrdata_reg_ld Not Registered -- -- Note: -- -- On "narrow burst transfers" BRAM address only -- gets incremented at BRAM data width. -- On WRAP bursts, the BRAM address must wrap when -- the max is reached -- -- -- -- WR_DATA_SNG_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_SNG_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_SNG_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, aw_active, axi_wr_burst, axi_wdata_full_reg, wr_data_sng_sm_cs ) begin -- assign default values for state machine outputs wr_data_sng_sm_ns <= wr_data_sng_sm_cs; aw_active_clr <= '0'; bvalid_cnt_inc <= '0'; axi_wr_burst_cmb <= axi_wr_burst; wrdata_reg_ld <= '0'; bram_we_ld <= '0'; bram_en_cmb <= '0'; clr_bram_we_cmb <= '0'; bram_addr_inc <= '0'; bram_addr_rst_cmb <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; case wr_data_sng_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Prior to AWVALID assertion, WVALID may be asserted -- and data accepted into WDATA register. -- Catch this condition and ensure the register full flag is set. -- Check that data pipeline is not already full. -- -- Modify WE pipeline and mux to BRAM -- as well. Since WE may be asserted early (when pipeline is loaded), -- but not yet ready to go out to BRAM. -- -- Only first data beat will be accepted early into data pipeline. -- All remaining beats in a burst will only be accepted upon WVALID. if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not end if; -- Wait for WVALID and aw_active to initiate write transfer if (aw_active = '1' and (AXI_WVALID = '1' or axi_wdata_full_reg = '1')) then -- If operation is a single, then it goes directly out to BRAM -- WDATA register is never marked as FULL in this case. -- If data pipeline is not previously loaded, do so now. if (axi_wdata_full_reg = '0') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register end if; -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- If data goes out to BRAM, mark data register as EMPTY axi_wdata_full_cmb <= '0'; axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not -- Check for singles, by checking WLAST assertion w/ WVALID -- Only if write data pipeline is not yet filled, check WLAST -- Otherwise, if pipeline is already full, use registered value of WLAST -- to check for single vs. burst write operation. if (AXI_WLAST = '1' and axi_wdata_full_reg = '0') or (axi_wdata_full_reg = '1' and axi_wr_burst = '0') then -- Single data write wr_data_sng_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; else -- Burst data write wr_data_sng_sm_ns <= BRST_WR_DATA; end if; -- WLAST end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- If WREADY is registered, then BVALID generation is seperate -- from write data flow. -- Go back to IDLE automatically -- BVALID will get asserted seperately from W channel wr_data_sng_sm_ns <= IDLE; bram_addr_rst_cmb <= '1'; aw_active_clr <= '1'; -- Check for capture of next data beat (WREADY will be asserted) if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not else axi_wdata_full_cmb <= '0'; -- If no next data, ensure data register is flagged EMPTY. end if; ------------------------- BRST_WR_DATA State ------------------------- when BRST_WR_DATA => -- Reach this state at the 2nd data beat of a burst -- AWADDR is already accepted -- Continue to accept data from AXI write channel -- and wait for assertion of WLAST -- Check that WVALID remains asserted for burst -- If negated, indicates throttling from AXI master if (AXI_WVALID = '1') then -- If WVALID is asserted for the 2nd and remaining -- data beats of the transfer -- Continue w/ BRAM write enable assertion & advance -- write data register -- Write data goes directly out to BRAM. -- WDATA register is never marked as FULL in this case. wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Increment BRAM address counter bram_addr_inc <= '1'; -- Check for last data beat in burst transfer if (AXI_WLAST = '1') then -- Last/single data write wr_data_sng_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; end if; -- WLAST -- Throttling -- Suspend BRAM write & halt write data & WE register load else -- Negate write data register load wrdata_reg_ld <= '0'; -- Negate WE register load bram_we_ld <= '0'; -- Negate write to BRAM bram_en_cmb <= '0'; -- Do not increment BRAM address counter bram_addr_inc <= '0'; end if; -- WVALID --coverage off ------------------------------ Default ---------------------------- when others => wr_data_sng_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_SNG_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_SNG_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_sng_sm_cs <= IDLE; bram_en_int <= '0'; clr_bram_we <= '0'; axi_wdata_full_reg <= '0'; else wr_data_sng_sm_cs <= wr_data_sng_sm_ns; bram_en_int <= bram_en_cmb; clr_bram_we <= clr_bram_we_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; end if; end if; end process WR_DATA_SNG_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY; ---------------------------------------------------------------------------- -- -- Generate: GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY -- -- Purpose: Create seperate SM for new logic to register out WREADY -- signal. Behavior for back-to-back operations is different -- than with combinatorial genearted WREADY output to AXI. -- -- New SM design supports seperate WREADY and BVALID responses. -- -- New logic here for axi_bvalid_int output register based -- on counter design of BVALID. -- ---------------------------------------------------------------------------- GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY: if C_ECC = 0 and C_SINGLE_PORT_BRAM = 0 generate begin -- Unused in this SM configuration active_wr_cmb <= '0'; -- Unused active_wr_reg <= '0'; -- Unused Active_Wr <= '0'; -- Unused wr_busy_cmb <= '0'; -- Unused wr_busy_reg <= '0'; -- Unused --------------------------------------------------------------------------- -- -- WR DATA State Machine -- -- Description: Central processing unit for AXI write data -- channel interface handling and AXI write data response -- handshaking. -- -- Outputs: Name Type -- bvalid_cnt_inc Not Registered -- aw_active_clr Not Registered -- delay_aw_active_clr Registered -- axi_wdata_full_reg Registered -- bram_en_int Registered -- wrdata_reg_ld Not Registered -- bram_we_ld Not Registered -- clr_bram_we Registered -- bram_addr_inc -- -- Note: -- -- On "narrow burst transfers" BRAM address only -- gets incremented at BRAM data width. -- On WRAP bursts, the BRAM address must wrap when -- the max is reached -- -- Add check on BVALID counter max. Check with -- AWVALID assertions (since AWID is connected to AWVALID). -- -- -- WR_DATA_SM_CMB_PROCESS: Combinational process to determine next state. -- WR_DATA_SM_REG_PROCESS: Registered process of the state machine. -- --------------------------------------------------------------------------- WR_DATA_SM_CMB_PROCESS: process ( AXI_WVALID, AXI_WLAST, bvalid_cnt_max, bvalid_cnt_amax, aw_active, delay_aw_active_clr, AXI_AWVALID, axi_awready_int, bram_addr_ld_en, axi_awaddr_full, awaddr_pipe_sel, axi_wr_burst, axi_wdata_full_reg, wr_b2b_elgible, wr_data_sm_cs ) begin -- assign default values for state machine outputs wr_data_sm_ns <= wr_data_sm_cs; aw_active_clr <= '0'; delay_aw_active_clr_cmb <= delay_aw_active_clr; bvalid_cnt_inc <= '0'; axi_wr_burst_cmb <= axi_wr_burst; wrdata_reg_ld <= '0'; bram_we_ld <= '0'; bram_en_cmb <= '0'; clr_bram_we_cmb <= '0'; bram_addr_inc <= '0'; bram_addr_rst_cmb <= '0'; axi_wdata_full_cmb <= axi_wdata_full_reg; case wr_data_sm_cs is ---------------------------- IDLE State --------------------------- when IDLE => -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register -- Add condition to check for simultaneous assertion -- of AWVALID and AWREADY if ((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Check for singles, by checking WLAST assertion w/ WVALID if (AXI_WLAST = '1') then -- Single data write wr_data_sm_ns <= SNG_WR_DATA; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- Set flag to delay clear of AW active flag delay_aw_active_clr_cmb <= '1'; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; axi_wr_burst_cmb <= '0'; else -- Burst data write wr_data_sm_ns <= BRST_WR_DATA; axi_wr_burst_cmb <= '1'; end if; -- WLAST else -- AWADDR not yet received -- Go to wait for write address wr_data_sm_ns <= W8_AWADDR; -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. axi_wdata_full_cmb <= '1'; -- Set flag for single/burst write operation -- when AWADDR is not yet received if (AXI_WLAST = '1') then axi_wr_burst_cmb <= '0'; else axi_wr_burst_cmb <= '1'; end if; -- WLAST end if; -- aw_active end if; -- WVALID ------------------------- W8_AWADDR State ------------------------- when W8_AWADDR => -- As we transition into this state, the write data pipeline -- is already filled. axi_wdata_full_reg should be = '1'. -- Disable any additional loads into write data register -- Default value in SM is applied. -- Wait for write address to be acknowledged if (((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) or -- Detect load of BRAM address counter from value stored in pipeline. -- No need to wait until aw_active is asserted or address is captured from AXI bus. -- As BRAM address is loaded from pipe and ready to be presented to BRAM. -- Assert BRAM WE. (bram_addr_ld_en = '1' and axi_awaddr_full = '1' and awaddr_pipe_sel = '1')) and -- Ensure the BVALID counter does not roll over (max = 8 ID values) (bvalid_cnt_max = '0') then -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Negate write data full condition axi_wdata_full_cmb <= '0'; -- Check if single or burst operation if (axi_wr_burst = '1') then wr_data_sm_ns <= BRST_WR_DATA; else wr_data_sm_ns <= SNG_WR_DATA; -- BRAM WE only asserted for single clock cycle clr_bram_we_cmb <= '1'; -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; delay_aw_active_clr_cmb <= '1'; end if; else -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. axi_wdata_full_cmb <= '1'; end if; ------------------------- SNG_WR_DATA State ------------------------- when SNG_WR_DATA => -- No need to check for BVALID assertion here. -- Move here under if clause on write response channel -- acknowledging completion of write data. -- If aw_active was not cleared prior to this state, then -- clear the flag now. if (delay_aw_active_clr = '1') then delay_aw_active_clr_cmb <= '0'; aw_active_clr <= '1'; end if; -- Add check here if while writing single data beat to BRAM, -- a new AXI data beat is received (prior to the AWVALID assertion). -- Ensure here that full flag is asserted for data pipeline state. -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then -- Load write data register wrdata_reg_ld <= '1'; -- Must also load WE register bram_we_ld <= '1'; -- Set flag that AXI write data pipe is full -- and can not accept any more data beats -- WREADY on AXI will negate in this condition. -- Ensure that axi_wdata_full_reg is asserted -- to prevent early captures on next data burst (or single data -- transfer) -- This ensures that the data beats do not get skipped. axi_wdata_full_cmb <= '1'; -- AWADDR not yet received -- Go to wait for write address wr_data_sm_ns <= W8_AWADDR; -- Accept no more new write data after this first data beat -- Pipeline is already full in this state. No need to assert -- no_wdata_accept flag to '1'. -- Set flag for single/burst write operation -- when AWADDR is not yet received if (AXI_WLAST = '1') then axi_wr_burst_cmb <= '0'; else axi_wr_burst_cmb <= '1'; end if; -- WLAST else -- No subsequent pending operation -- Return to IDLE wr_data_sm_ns <= IDLE; bram_addr_rst_cmb <= '1'; end if; ------------------------- BRST_WR_DATA State ------------------------- when BRST_WR_DATA => -- Reach this state at the 2nd data beat of a burst -- AWADDR is already accepted -- Continue to accept data from AXI write channel -- and wait for assertion of WLAST -- Check that WVALID remains asserted for burst -- If negated, indicates throttling from AXI master if (AXI_WVALID = '1') then -- If WVALID is asserted for the 2nd and remaining -- data beats of the transfer -- Continue w/ BRAM write enable assertion & advance -- write data register wrdata_reg_ld <= '1'; -- Load write data register bram_we_ld <= '1'; -- Load WE register bram_en_cmb <= '1'; -- Initiate BRAM write transfer bram_addr_inc <= '1'; -- Increment BRAM address counter -- Check for last data beat in burst transfer if (AXI_WLAST = '1') then -- Set flag to assert BVALID and increment counter bvalid_cnt_inc <= '1'; -- The elgible signal will not be asserted for a subsequent -- single data beat operation. Next operation is a burst. -- And the AWADDR is loaded in the address pipeline. -- Only if BVALID counter can handle next transfer, -- proceed with back-to-back. Otherwise, go to IDLE -- (after last data write). if (wr_b2b_elgible = '1' and bvalid_cnt_amax = '0') then -- Go to next operation and handle as a -- back-to-back burst. No empty clock cycles. -- Go to handle new burst for back to back condition wr_data_sm_ns <= B2B_W8_WR_DATA; axi_wr_burst_cmb <= '1'; -- No pending subsequent transfer (burst > 2 data beats) -- to process else -- Last/single data write wr_data_sm_ns <= SNG_WR_DATA; -- Be sure to clear aw_active flag at end of write burst -- But delay when the flag is cleared delay_aw_active_clr_cmb <= '1'; end if; end if; -- WLAST -- Throttling -- Suspend BRAM write & halt write data & WE register load else wrdata_reg_ld <= '0'; -- Negate write data register load bram_we_ld <= '0'; -- Negate WE register load bram_en_cmb <= '0'; -- Negate write to BRAM bram_addr_inc <= '0'; -- Do not increment BRAM address counter end if; -- WVALID ------------------------- B2B_W8_WR_DATA -------------------------- when B2B_W8_WR_DATA => -- Reach this state upon a back-to-back condition -- when BVALID/BREADY handshake is received, -- but WVALID is not yet asserted for subsequent transfer. -- Check valid write data on AXI write data channel if (AXI_WVALID = '1') then -- Load write data register wrdata_reg_ld <= '1'; -- Load WE register bram_we_ld <= '1'; -- Initiate BRAM write transfer bram_en_cmb <= '1'; -- Burst data write wr_data_sm_ns <= BRST_WR_DATA; axi_wr_burst_cmb <= '1'; -- Make modification to last_data_ack_mod signal -- so that it is asserted when this state is reached -- and the BRAM address counter gets loaded. -- WVALID not yet asserted else wrdata_reg_ld <= '0'; -- Negate write data register load bram_we_ld <= '0'; -- Negate WE register load bram_en_cmb <= '0'; -- Negate write to BRAM bram_addr_inc <= '0'; -- Do not increment BRAM address counter end if; --coverage off ------------------------------ Default ---------------------------- when others => wr_data_sm_ns <= IDLE; --coverage on end case; end process WR_DATA_SM_CMB_PROCESS; --------------------------------------------------------------------------- WR_DATA_SM_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then wr_data_sm_cs <= IDLE; bram_en_int <= '0'; clr_bram_we <= '0'; delay_aw_active_clr <= '0'; axi_wdata_full_reg <= '0'; else wr_data_sm_cs <= wr_data_sm_ns; bram_en_int <= bram_en_cmb; clr_bram_we <= clr_bram_we_cmb; delay_aw_active_clr <= delay_aw_active_clr_cmb; axi_wdata_full_reg <= axi_wdata_full_cmb; end if; end if; end process WR_DATA_SM_REG_PROCESS; --------------------------------------------------------------------------- end generate GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY; --------------------------------------------------------------------------- WR_BURST_REG_PROCESS: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_wr_burst <= '0'; else axi_wr_burst <= axi_wr_burst_cmb; end if; end if; end process WR_BURST_REG_PROCESS; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- *** AXI Write Response Channel Interface *** --------------------------------------------------------------------------- -- v1.03a --------------------------------------------------------------------------- -- -- -- New FIFO storage for BID, so AWID can be stored in -- a FIFO and B response is seperated from W response. -- -- Use registered WREADY & BID FIFO in single port configuration. -- --------------------------------------------------------------------------- -- Instantiate FIFO to store BID values to be asserted back on B channel. -- Only 8 entries deep, BVALID counter only allows W channel to be 8 ahead of -- B channel. -- -- If AWID is a single bit wide, sythesis optimizes the module, srl_fifo, -- to a single SRL16E library module. BID_FIFO: entity work.srl_fifo generic map ( C_DATA_BITS => C_AXI_ID_WIDTH, C_DEPTH => 8 ) port map ( Clk => S_AXI_AClk, Reset => bid_fifo_rst, FIFO_Write => bid_fifo_ld_en, Data_In => bid_fifo_ld, FIFO_Read => bid_fifo_rd_en, Data_Out => bid_fifo_rd, FIFO_Full => open, Data_Exists => bid_fifo_not_empty, Addr => open ); bid_fifo_rst <= not (S_AXI_AResetn); bid_fifo_ld_en <= bram_addr_ld_en; bid_fifo_ld <= AXI_AWID when (awaddr_pipe_sel = '0') else axi_awid_pipe; -- Read from FIFO when BVALID is to be asserted on bus, or in a back-to-back assertion -- when a BID value is available in the FIFO. bid_fifo_rd_en <= bid_fifo_not_empty and -- Only read if data is available. ((bid_gets_fifo_load_d1) or -- a) Do the FIFO read in the clock cycle -- following the BID value directly -- aserted on the B channel (from AWID or pipeline). (first_fifo_bid) or -- b) Read from FIFO when BID is previously stored -- but BVALID is not yet asserted on AXI. (bvalid_cnt_dec)); -- c) Or read when next BID value is to be updated -- on B channel (and exists waiting in FIFO). -- 1) Special case (1st load in FIFO) (and single clock cycle turnaround needed on BID, from AWID). -- If loading the FIFO and BVALID is to be asserted in the next clock cycle -- Then capture this condition to read from FIFO in the subsequent clock cycle -- (and clear the BID value stored in the FIFO). bid_gets_fifo_load <= '1' when (bid_fifo_ld_en = '1') and (first_fifo_bid = '1' or b2b_fifo_bid = '1') else '0'; first_fifo_bid <= '1' when ((bvalid_cnt_inc = '1') and (bvalid_cnt_non_zero = '0')) else '0'; -- 2) An additional special case. -- When write data register is loaded for single (bvalid_cnt = "001", due to WLAST/WVALID) -- But, AWID not yet received (FIFO is still empty). -- If BID FIFO is still empty with the BVALID counter decrement, but simultaneously -- is increment (same condition as first_fifo_bid). b2b_fifo_bid <= '1' when (bvalid_cnt_inc = '1' and bvalid_cnt_dec = '1' and bvalid_cnt = "001" and bid_fifo_not_empty = '0') else '0'; -- Output BID register to B AXI channel REG_BID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bid_int <= (others => '0'); -- If loading the FIFO and BVALID is to be asserted in the next clock cycle -- Then output the AWID or pipelined value (the same BID that gets loaded into FIFO). elsif (bid_gets_fifo_load = '1') then axi_bid_int <= bid_fifo_ld; -- If new value read from FIFO then ensure that value is updated on AXI. elsif (bid_fifo_rd_en = '1') then axi_bid_int <= bid_fifo_rd; else axi_bid_int <= axi_bid_int; end if; end if; end process REG_BID; -- Capture condition of BID output updated while the FIFO is also -- getting updated. Read FIFO in the subsequent clock cycle to -- clear the value stored in the FIFO. REG_BID_LD: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bid_gets_fifo_load_d1 <= '0'; else bid_gets_fifo_load_d1 <= bid_gets_fifo_load; end if; end if; end process REG_BID_LD; --------------------------------------------------------------------------- -- AXI_BRESP Output Register --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_BRESP -- Purpose: Generate BRESP output signal when ECC is disabled. -- Only allowable output is RESP_OKAY. --------------------------------------------------------------------------- GEN_BRESP: if C_ECC = 0 generate begin REG_BRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bresp_int <= (others => '0'); -- elsif (AXI_WLAST = '1') then -- CR # 609695 elsif ((AXI_WLAST and AXI_WVALID and axi_wready_int_mod) = '1') then -- AXI BRAM only supports OK response for normal operations -- Exclusive operations not yet supported axi_bresp_int <= RESP_OKAY; else axi_bresp_int <= axi_bresp_int; end if; end if; end process REG_BRESP; end generate GEN_BRESP; --------------------------------------------------------------------------- -- Generate: GEN_BRESP_ECC -- Purpose: Generate BRESP output signal when ECC is enabled -- If no ECC error condition is detected during the RMW -- sequence, then output will be RESP_OKAY. When an -- uncorrectable error is detected, the output will RESP_SLVERR. --------------------------------------------------------------------------- GEN_BRESP_ECC: if C_ECC = 1 generate signal UE_Q_reg : std_logic := '0'; begin REG_BRESP: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then axi_bresp_int <= (others => '0'); elsif (bvalid_cnt_inc_d1 = '1') then --coverage off -- Exclusive operations not yet supported -- If no ECC errors occur, respond with OK if (UE_Q = '1') or (UE_Q_reg = '1') then axi_bresp_int <= RESP_SLVERR; --coverage on else axi_bresp_int <= RESP_OKAY; end if; else axi_bresp_int <= axi_bresp_int; end if; end if; end process REG_BRESP; -- Check if any error conditions occured during the write operation. -- Capture condition for each write transfer. REG_UE: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- Clear at end of current write (and ensure the flag is cleared -- at the beginning of a write transfer) if (S_AXI_AResetn = C_RESET_ACTIVE) or (aw_active_re = '1') or (AXI_BREADY = '1' and axi_bvalid_int = '1') then UE_Q_reg <= '0'; --coverage off elsif (UE_Q = '1') then UE_Q_reg <= '1'; --coverage on else UE_Q_reg <= UE_Q_reg; end if; end if; end process REG_UE; end generate GEN_BRESP_ECC; -- v1.03a --------------------------------------------------------------------------- -- Instantiate BVALID counter outside of specific SM generate block. --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- BVALID counter to track the # of required BVALID/BREADY handshakes -- needed to occur on the AXI interface. Based on early and seperate -- AWVALID/AWREADY and WVALID/WREADY handshake exchanges. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt <= (others => '0'); -- Ensure we only increment counter wyhen BREADY is not asserted elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1); -- Ensure that we only decrement when SM is not incrementing elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1); else bvalid_cnt <= bvalid_cnt; end if; end if; end process REG_BVALID_CNT; bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and axi_bvalid_int = '1' and bvalid_cnt_non_zero = '1') else '0'; bvalid_cnt_non_zero <= '1' when (bvalid_cnt /= "000") else '0'; bvalid_cnt_amax <= '1' when (bvalid_cnt = "110") else '0'; bvalid_cnt_max <= '1' when (bvalid_cnt = "111") else '0'; -- Replace BVALID output register -- Assert BVALID as long as BVALID counter /= zero REG_BVALID: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (S_AXI_AResetn = C_RESET_ACTIVE) or -- Ensure that if we are also incrementing BVALID counter, the BVALID stays asserted. (bvalid_cnt = "001" and bvalid_cnt_dec = '1' and bvalid_cnt_inc = '0') then axi_bvalid_int <= '0'; elsif (bvalid_cnt_non_zero = '1') or (bvalid_cnt_inc = '1') then axi_bvalid_int <= '1'; else axi_bvalid_int <= '0'; end if; end if; end process REG_BVALID; --------------------------------------------------------------------------- -- *** ECC Logic *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- -- Generate: GEN_ECC -- Purpose: Generate BRAM ECC write data and check ECC on read operations. -- Create signals to update ECC registers (lite_ecc_reg module interface). -- --------------------------------------------------------------------------- GEN_ECC: if C_ECC = 1 generate constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite) constant null8 : std_logic_vector(0 to 7) := "00000000"; -- Specific to 64-bit data width -- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6; -- Remove usage of C_FAMILY. -- All architectures supporting AXI will support a LUT6. -- Hard code this internal constant used in ECC algorithm. constant C_USE_LUT6 : boolean := TRUE; signal RdECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Temp signal WrECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width signal WrECC_i : std_logic_vector(C_ECC_WIDTH-1 downto 0) := (others => '0'); signal AXI_WSTRB_Q : std_logic_vector((C_AXI_DATA_WIDTH/8 - 1) downto 0) := (others => '0'); signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to 64-bit ECC signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence signal RdModifyWr_Read_i : std_logic := '0'; signal RdModifyWr_Check : std_logic := '0'; signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width signal UnCorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1) := (others => '0'); signal CE_Q : std_logic := '0'; signal Sl_CE_i : std_logic := '0'; signal Sl_UE_i : std_logic := '0'; subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1); -- 0:6 for 32-bit ECC -- 0:7 for 64-bit ECC type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits; type bool_array is array (natural range 0 to 6) of boolean; constant inverted_bit : bool_array := (false,false,true,false,true,false,false); -- v1.03a constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH; constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0); begin -- Generate signal to advance BRAM read address pipeline to -- capture address for ECC error conditions (in lite_ecc_reg module). BRAM_Addr_En <= RdModifyWr_Read; -- v1.03a RdModifyWr_Read <= '1' when (wr_data_ecc_sm_cs = RMW_RD_DATA) else '0'; RdModifyWr_Modify <= '1' when (wr_data_ecc_sm_cs = RMW_MOD_DATA) else '0'; RdModifyWr_Write <= '1' when (wr_data_ecc_sm_cs = RMW_WR_DATA) else '0'; ----------------------------------------------------------------------- -- Remember write data one cycle to be available after read has been completed in a -- read/modify write operation. -- Save WSTRBs here in this register REG_WSTRB : process (S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then AXI_WSTRB_Q <= (others => '0'); elsif (wrdata_reg_ld = '1') then AXI_WSTRB_Q <= AXI_WSTRB; end if; end if; end process REG_WSTRB; -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_WRDATA_CMB -- Purpose: Replace manual signal assignment for WrData_cmb with -- generate funtion. -- -- Ensure correct byte swapping occurs with -- CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) assignment -- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0). -- -- AXI_WSTRB_Q (C_AXI_DATA_WIDTH_BYTES-1 downto 0) matches -- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0). -- ------------------------------------------------------------------------ GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate begin WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= bram_wrdata_int ((((i+1)*8)-1) downto i*8) when (RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1') else CorrectedRdData ( (C_AXI_DATA_WIDTH - ((i+1)*8)) to (C_AXI_DATA_WIDTH - (i*8) - 1) ); end generate GEN_WRDATA_CMB; REG_WRDATA : process (S_AXI_AClk) is begin -- Remove reset value to minimize resources & improve timing if (S_AXI_AClk'event and S_AXI_AClk = '1') then WrData <= WrData_cmb; end if; end process REG_WRDATA; ------------------------------------------------------------------------ -- New assignment of ECC bits to BRAM write data outside generate -- blocks. Same signal assignment regardless of ECC type. BRAM_WrData ((C_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto C_AXI_DATA_WIDTH) <= WrECC_i xor FaultInjectECC; ------------------------------------------------------------------------ -- v1.03a ------------------------------------------------------------------------ -- Generate: GEN_HSIAO_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. -- Derived from MIG v3.7 Hsiao HDL. ------------------------------------------------------------------------ GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate constant ECC_WIDTH : integer := C_INT_ECC_WIDTH; type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0); signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0); signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0); signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); signal h_matrix : type_int0; signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0); begin ---------------------- Hsiao ECC Write Logic ---------------------- -- Instantiate ecc_gen_hsiao module, generated from MIG ECC_GEN_HSIAO: entity work.ecc_gen generic map ( code_width => CODE_WIDTH, ecc_width => ECC_WIDTH, data_width => C_AXI_DATA_WIDTH ) port map ( -- Output h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0) ); -- Merge muxed rd/write data to gen HSIAO_ECC: process (h_rows, WrData) constant DQ_WIDTH : integer := CODE_WIDTH; variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_AXI_DATA_WIDTH); begin -- Loop to generate all ECC bits for k in 0 to ECC_WIDTH - 1 loop ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_AXI_DATA_WIDTH - 1 downto 0) and h_rows (k * CODE_WIDTH + C_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH))); end loop; WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_AXI_DATA_WIDTH); end process HSIAO_ECC; ----------------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: For 32-bit ECC implementations, assign unused -- MSB of ECC output to BRAM with '0'. ----------------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate begin -- Account for 32-bit and MSB '0' of ECC bits WrECC_i <= '0' & WrECC; end generate GEN_ECC_32; ----------------------------------------------------------------------- -- Generate: GEN_ECC_N -- Purpose: For all non 32-bit ECC implementations, assign ECC -- bits for BRAM output. ----------------------------------------------------------------------- GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate begin WrECC_i <= WrECC; end generate GEN_ECC_N; ---------------------- Hsiao ECC Read Logic ----------------------- GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate begin syndrome_ns (m) <= REDUCTION_XOR ( BRAM_RdData (CODE_WIDTH-1 downto 0) and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH))); end generate GEN_RD_ECC; -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_r <= syndrome_ns; end if; end process REG_SYNDROME; ecc_rddata_r <= UnCorrectedRdData; -- Reconstruct H-matrix H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate begin H_BIT: for p in 0 to ECC_WIDTH - 1 generate begin h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n); end generate H_BIT; end generate H_COL; GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate begin flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r); end generate GEN_FLIP_BIT; CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor flip_bits (C_AXI_DATA_WIDTH-1 downto 0); Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0))); end generate GEN_HSIAO_ECC; ------------------------------------------------------------------------ -- Generate: GEN_HAMMING_ECC -- Purpose: Determine type of ECC encoding. Hsiao or Hamming. -- Add parameter/generate level. ------------------------------------------------------------------------ GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate begin ----------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: Assign ECC out data vector (N:0) unique for 32-bit BRAM. -- Add extra '0' at MSB of ECC vector for data2mem alignment -- w/ 32-bit BRAM data widths. -- ECC bits are in upper order bits. ----------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate constant correct_data_table_32 : correct_data_table_type := ( 0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001", 4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001", 8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101", 12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101", 16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101", 20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101", 24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011", 28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011" ); signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC begin --------------------- Hamming 32-bit ECC Write Logic ------------------ ------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_32 -- Description: Generate ECC bits for writing into BRAM. -- WrData (N:0) ------------------------------------------------------------------------- CHK_HANDLER_WR_32: entity work.checkbit_handler generic map ( C_ENCODE => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( DataIn => WrData, -- [in std_logic_vector(0 to 31)] CheckIn => null7, -- [in std_logic_vector(0 to 6)] CheckOut => WrECC, -- [out std_logic_vector(0 to 6)] Syndrome => open, -- [out std_logic_vector(0 to 6)] Syndrome_4 => open, -- [out std_logic_vector(0 to 1)] Syndrome_6 => open, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)] Enable_ECC => '1', -- [in std_logic] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] -- v1.03a -- Account for 32-bit and MSB '0' of ECC bits WrECC_i <= '0' & WrECC; --------------------- Hamming 32-bit ECC Read Logic ------------------- -------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_32 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) -------------------------------------------------------------------------- CHK_HANDLER_RD_32: entity work.checkbit_handler generic map ( C_ENCODE => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( -- DataIn (8:39) -- CheckIn (1:7) DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)] CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)] CheckOut => open, -- [out std_logic_vector(0 to 6)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)] Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)] Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] --------------------------------------------------------------------------- -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_4_reg <= Syndrome_4; syndrome_6_reg <= Syndrome_6; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl -- w/ balanced pipeline stage) before correct_one_bit module. syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3); PARITY_CHK4: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2) port map ( InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (4) ); -- [out std_logic] syndrome_reg_i (5) <= syndrome_reg (5); PARITY_CHK6: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome_reg_i (6) ); -- [out std_logic] --------------------------------------------------------------------------- -- Generate: GEN_CORR_32 -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_32 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_32: entity work.correct_one_bit generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_32 (i)) port map ( DIn => UnCorrectedRdData (i), Syndrome => syndrome_reg_i, DCorr => CorrectedRdData (i)); end generate GEN_CORR_32; end generate GEN_ECC_32; ----------------------------------------------------------------- -- Generate: GEN_ECC_64 -- Purpose: Assign ECC out data vector (N:0) unique for 64-bit BRAM. -- No extra '0' at MSB of ECC vector for data2mem alignment -- w/ 64-bit BRAM data widths. -- ECC bits are in upper order bits. ----------------------------------------------------------------- GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate constant correct_data_table_64 : correct_data_table_type := ( 0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001", 4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001", 8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001", 12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001", 16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001", 20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001", 24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101", 28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101", 32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101", 36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101", 40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101", 44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101", 48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101", 52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101", 56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011", 60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011" ); signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); signal syndrome7_a : std_logic := '0'; signal syndrome7_b : std_logic := '0'; begin --------------------- Hamming 64-bit ECC Write Logic ------------------ --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_WR_64 -- Description: Generate ECC bits for writing into BRAM when configured -- as 64-bit wide BRAM. -- WrData (N:0) -- Enable C_REG on encode path. --------------------------------------------------------------------------- CHK_HANDLER_WR_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => true, -- [boolean] C_REG => true, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] DataIn => WrData_cmb, -- [in std_logic_vector(0 to 63)] CheckIn => null8, -- [in std_logic_vector(0 to 7)] CheckOut => WrECC, -- [out std_logic_vector(0 to 7)] Syndrome => open, -- [out std_logic_vector(0 to 7)] Syndrome_7 => open, -- [out std_logic_vector(0 to 11)] Syndrome_Chk => null8, -- [in std_logic_vector(0 to 7)] Enable_ECC => '1', -- [in std_logic] UE_Q => '0', -- [in std_logic] CE_Q => '0', -- [in std_logic] UE => open, -- [out std_logic] CE => open ); -- [out std_logic] -- Note: (7:0) Old bit lane assignment -- BRAM_WrData ((C_ECC_WIDTH - 1) downto 0) -- v1.02a -- WrECC is assigned to BRAM_WrData (71:64) -- v1.03a -- BRAM_WrData (71:64) assignment done outside of this -- ECC type generate block. WrECC_i <= WrECC; --------------------- Hamming 64-bit ECC Read Logic ------------------- --------------------------------------------------------------------------- -- Instance: CHK_HANDLER_RD_64 -- Description: Generate ECC bits for checking data read from BRAM. -- All vectors oriented (0:N) --------------------------------------------------------------------------- CHK_HANDLER_RD_64: entity work.checkbit_handler_64 generic map ( C_ENCODE => false, -- [boolean] C_REG => false, -- [boolean] C_USE_LUT6 => C_USE_LUT6) -- [boolean] port map ( Clk => S_AXI_AClk, -- [in std_logic] -- DataIn (8:71) -- CheckIn (0:7) DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)] CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)] CheckOut => open, -- [out std_logic_vector(0 to 7)] Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)] Syndrome_7 => Syndrome_7, -- [out std_logic_vector(0 to 11)] Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)] Enable_ECC => Enable_ECC, -- [in std_logic] UE_Q => UE_Q, -- [in std_logic] CE_Q => CE_Q, -- [in std_logic] UE => Sl_UE_i, -- [out std_logic] CE => Sl_CE_i ); -- [out std_logic] --------------------------------------------------------------------------- -- Insert register stage for syndrome REG_SYNDROME: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then syndrome_reg <= Syndrome; syndrome_7_reg <= Syndrome_7; end if; end process REG_SYNDROME; --------------------------------------------------------------------------- -- Move final XOR to registered side of syndrome bits. -- Do last XOR on select syndrome bits after pipeline stage -- before correct_one_bit_64 module. syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6); PARITY_CHK7_A: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome7_a ); -- [out std_logic] PARITY_CHK7_B: entity work.parity generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6) port map ( InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)] Res => syndrome7_b ); -- [out std_logic] syndrome_reg_i (7) <= syndrome7_a xor syndrome7_b; --------------------------------------------------------------------------- -- Generate: GEN_CORRECT_DATA -- Purpose: Generate corrected read data based on syndrome value. -- All vectors oriented (0:N) --------------------------------------------------------------------------- GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate begin --------------------------------------------------------------------------- -- Instance: CORR_ONE_BIT_64 -- Description: Generate ECC bits for checking data read from BRAM. --------------------------------------------------------------------------- CORR_ONE_BIT_64: entity work.correct_one_bit_64 generic map ( C_USE_LUT6 => C_USE_LUT6, Correct_Value => correct_data_table_64 (i)) port map ( DIn => UnCorrectedRdData (i), Syndrome => syndrome_reg_i, DCorr => CorrectedRdData (i)); end generate GEN_CORR_64; end generate GEN_ECC_64; end generate GEN_HAMMING_ECC; -- Remember correctable/uncorrectable error from BRAM read CORR_REG: process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if RdModifyWr_Modify = '1' then -- Capture error signals CE_Q <= Sl_CE_i; UE_Q <= Sl_UE_i; else CE_Q <= '0'; UE_Q <= '0'; end if; end if; end process CORR_REG; -- ECC register block gets registered UE or CE conditions to update -- ECC registers/interrupt/flag outputs. Sl_CE <= CE_Q; Sl_UE <= UE_Q; CE_Failing_We <= CE_Q; FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0'; ----------------------------------------------------------------------- -- Add register delay on BVALID counter increment -- Used to clear fault inject register. REG_BVALID_CNT: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then bvalid_cnt_inc_d1 <= '0'; else bvalid_cnt_inc_d1 <= bvalid_cnt_inc; end if; end if; end process REG_BVALID_CNT; ----------------------------------------------------------------------- -- Map BRAM_RdData (N:0) to bram_din_a_i (0:N) -- Including read back ECC bits. bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0); ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- Generate: GEN_ECC_32 -- Purpose: For 32-bit ECC implementations, account for -- extra bit in read data mapping on registered value. ----------------------------------------------------------------------- GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate begin -- Insert register stage for read data to correct REG_CHK_DATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH); end if; end process REG_CHK_DATA; end generate GEN_ECC_32; ----------------------------------------------------------------------- -- Generate: GEN_ECC_N -- Purpose: For all non 32-bit ECC implementations, assign ECC -- bits for BRAM output. ----------------------------------------------------------------------- GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate begin -- Insert register stage for read data to correct REG_CHK_DATA: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1); end if; end process REG_CHK_DATA; end generate GEN_ECC_N; end generate GEN_ECC; --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Drive default output signals when ECC is diabled. --------------------------------------------------------------------------- GEN_NO_ECC: if C_ECC = 0 generate begin BRAM_Addr_En <= '0'; FaultInjectClr <= '0'; CE_Failing_We <= '0'; Sl_CE <= '0'; Sl_UE <= '0'; end generate GEN_NO_ECC; --------------------------------------------------------------------------- -- *** BRAM Interface Signals *** --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WE -- Purpose: BRAM WE generate process -- One WE per 8-bits of BRAM data. --------------------------------------------------------------------------- GEN_BRAM_WE: for i in C_AXI_DATA_WIDTH/8 + (C_ECC*(1+(C_AXI_DATA_WIDTH/128))) - 1 downto 0 generate begin BRAM_WE (i) <= bram_we_int (i); end generate GEN_BRAM_WE; --------------------------------------------------------------------------- BRAM_En <= bram_en_int; --------------------------------------------------------------------------- -- BRAM Address Generate --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Generate: GEN_L_BRAM_ADDR -- Purpose: Generate zeros on lower order address bits adjustable -- based on BRAM data width. --------------------------------------------------------------------------- GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin BRAM_Addr (i) <= '0'; end generate GEN_L_BRAM_ADDR; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_ADDR -- Purpose: Assign BRAM address output from address counter. -- --------------------------------------------------------------------------- GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin BRAM_Addr (i) <= bram_addr_int (i); end generate GEN_BRAM_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_BRAM_WRDATA -- Purpose: Generate BRAM Write Data. --------------------------------------------------------------------------- GEN_BRAM_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate begin -- Check if ECC is enabled -- If so, XOR the fault injection vector with the data -- (post-pipeline) to avoid any timing issues on the data vector -- from AXI. ----------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is disabled. ----------------------------------------------------------------------- GEN_NO_ECC : if C_ECC = 0 generate begin BRAM_WrData (i) <= bram_wrdata_int (i); end generate GEN_NO_ECC; ----------------------------------------------------------------------- -- Generate: GEN_NO_ECC -- Purpose: Generate output write data when ECC is enable -- (use fault vector) -- (N:0) -- for 32-bit (31:0) WrData while (ECC = [39:32]) ----------------------------------------------------------------------- GEN_W_ECC : if C_ECC = 1 generate begin BRAM_WrData (i) <= WrData (i) xor FaultInjectData (i); end generate GEN_W_ECC; end generate GEN_BRAM_WRDATA; --------------------------------------------------------------------------- end architecture implementation;

bsd-2-clause

5f18d2348e650d8c0a1f2c0ecac0c6ce

0.416174

4.795635

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/conditional_waveforms/rule_501_test_input.fixed_lower.vhd

1

400

architecture rtl of fifo is begin process begin var1 := '0' when rd_en = '1' ELSE '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' when rd_en = '1' ELSE '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' when rd_en = '1' else '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;

gpl-3.0

8acf6c44e6068b5d74722bd09b449a70

0.54

2.564103

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/if_statement/rule_002_test_input.fixed_parenthesis_remove.vhd

1

1,508

architecture RTL of FIFO is begin process begin if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; elsif a(3 downto 0) = 0 then b <= '0'; elsif a(3 downto 0) + f(34, 56, 72) - g(f(35, 25, 60) downto h(45, 32)) then b <= '1'; elsif (a or b) and (c or d) then b <= '0'; end if; -- Violations below if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; elsif a(3 downto 0) = 0 then b <= '0'; elsif a(3 downto 0) + f(34, 56, 72) - g(f(35, 25, 60) downto h(45, 32)) then b <= '1'; elsif (a or b) and (c or d) then b <= '0'; end if; end process; process begin if (x(k) = '1') and (v_y = '0') then b <= '0'; end if; if ((ctrl_done_d1 = '0') and (CTRL_DONE = '1')) or (dev_addr = dev_addr_prv) then b <= '0'; end if; end process; process begin if (sync_reset) = '1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; if a='1' then b <= '0'; end if; end process; process begin if something then b <= 0; elsif something_else then b <= 1; end if; if something then b <= 0; elsif something_else then b <= 1; end if; end process; end architecture RTL;

gpl-3.0

1492e91421ff1ffc1ca3d5ebd1535f81

0.440981

2.9

false

jeremiah-c-leary/vhdl-style-guide

vsg/tests/conditional_waveforms/rule_500_test_input.vhd

2

400

architecture rtl of fifo is begin process begin var1 := '0' WHEN rd_en = '1' else '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' WHEN rd_en = '1' else '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;

gpl-3.0

14bddea23108b1bda8a233e34e25356a

0.54

2.564103

false

Yarr/Yarr-fw

rtl/trigger-logic/delayer.vhd

1

1,125

-- #################################### -- # Project: Yarr -- # Author: Vyassa Baratham -- # E-Mail: vbaratham at berkeley.edu -- # Comments: Allows configurable delay of up to N clk cycles -- # Data: 09/2017 -- # Outputs are synchronous to clk_i -- #################################### library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity delayer is generic (N : integer); -- shift register width port ( clk_i : in std_logic; rst_n_i : in std_logic; dat_i : in std_logic; dat_o : out std_logic; delay : in std_logic_vector(N-1 downto 0) ); end delayer; architecture rtl of delayer is signal shift_reg : std_logic_vector(2**N-1 downto 0); begin proc : process(clk_i, rst_n_i) begin if (rst_n_i = '0') then dat_o <= '0'; shift_reg <= (others => '0'); elsif rising_edge(clk_i) then shift_reg(2**N-1 downto 1) <= shift_reg(2**N-2 downto 0); shift_reg(0) <= dat_i; dat_o <= shift_reg(to_integer(unsigned(delay))); end if; end process proc; end rtl;

gpl-3.0

524e9a1198e282374174318899b5a09b

0.535111

3.270349

false

Yarr/Yarr-fw

rtl/kintex7/rx-core/wb_rx_bridge.vhd

1

13,975

-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: Bridge between Rx core and Mem -- #################################### -- # Address Map: -- # 0x0000: Start Adr (RO) -- # 0x0001: Data Cnt (RO) -- # 0x0002[0]: Loopback (RW) -- # 0x0003: Data Rate (RO) -- # 0x0004: Loop Fifo (WO) library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity wb_rx_bridge is port ( -- Sys Connect sys_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- Wishbone DMA Master Interface dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(63 downto 0); dma_dat_i : in std_logic_vector(63 downto 0); dma_cyc_o : out std_logic; dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_ack_i : in std_logic; dma_stall_i : in std_logic; -- Rx Interface rx_data_i : in std_logic_vector(63 downto 0); rx_valid_i : in std_logic; -- Status In trig_pulse_i : in std_logic; -- Status out irq_o : out std_logic; busy_o : out std_logic ); end wb_rx_bridge; architecture Behavioral of wb_rx_bridge is -- Cmoponents COMPONENT rx_bridge_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC ); END COMPONENT; COMPONENT rx_bridge_ctrl_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; -- Constants constant c_ALMOST_FULL_THRESHOLD : unsigned(7 downto 0) := TO_UNSIGNED(240, 8); constant c_PACKAGE_SIZE : unsigned(31 downto 0) := TO_UNSIGNED((1680*30), 32); -- ~200kByte, magic number (!!) divisible my any channel number of to 8 constant c_TIMEOUT : unsigned(31 downto 0) := TO_UNSIGNED(2**14, 32); -- Counts in 5ns = 0.1ms constant c_TIME_FRAME : unsigned(31 downto 0) := TO_UNSIGNED(200000000-1, 32); -- 200MHz clock cycles in 1 sec constant c_EMPTY_THRESHOLD : unsigned(7 downto 0) := TO_UNSIGNED(16, 8); constant c_EMPTY_TIMEOUT : unsigned(9 downto 0) := TO_UNSIGNED(2000, 10); -- Signals signal data_fifo_din : std_logic_vector(63 downto 0); signal data_fifo_dout : std_logic_vector(63 downto 0); signal data_fifo_wren : std_logic; signal data_fifo_rden : std_logic; signal data_fifo_full : std_logic; signal data_fifo_empty : std_logic; signal data_fifo_almost_full : std_logic; signal data_fifo_prog_empty : std_logic; signal data_fifo_empty_cnt : unsigned(10 downto 0); signal data_fifo_empty_true : std_logic; signal data_fifo_empty_pressure : std_logic; signal ctrl_fifo_din : std_logic_vector(63 downto 0); signal ctrl_fifo_dout : std_logic_vector(63 downto 0); signal ctrl_fifo_wren : std_logic; signal ctrl_fifo_rden : std_logic; signal ctrl_fifo_full : std_logic; signal ctrl_fifo_empty : std_logic; signal dma_stb_t : std_logic; signal dma_stb_valid : std_logic; signal dma_adr_cnt : unsigned(31 downto 0); signal dma_start_adr : unsigned(31 downto 0); signal dma_data_cnt : unsigned(31 downto 0); signal dma_data_cnt_d : unsigned(31 downto 0); signal dma_timeout_cnt : unsigned(31 downto 0); signal dma_ack_cnt : unsigned(7 downto 0); signal rx_data_local : std_logic_vector(31 downto 0); signal rx_valid_local : std_logic; signal rx_data_local_d : std_logic_vector(31 downto 0); signal rx_valid_local_d : std_logic; signal ctrl_fifo_dout_tmp : std_logic_vector(31 downto 0); signal time_cnt : unsigned(31 downto 0); signal time_pulse : std_logic; signal data_rate_cnt : unsigned(31 downto 0); signal trig_cnt : unsigned(31 downto 0); signal trig_pulse_d0 : std_logic; signal trig_pulse_d1 : std_logic; signal trig_pulse_pos : std_logic; -- Registers signal loopback : std_logic; signal data_rate : std_logic_vector(31 downto 0); begin --Tie offs irq_o <= '0'; busy_o <= data_fifo_full; -- Wishbone Slave wb_slave_proc: process(sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; wb_stall_o <= '0'; ctrl_fifo_rden <= '0'; rx_valid_local <= '0'; ctrl_fifo_dout_tmp <= (others => '0'); -- Regs loopback <= '0'; elsif rising_edge(sys_clk_i) then -- Default wb_ack_o <= '0'; ctrl_fifo_rden <= '0'; wb_stall_o <= '0'; rx_valid_local <= '0'; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '0') then -- READ if (wb_adr_i(3 downto 0) = x"0") then -- Start Addr if (ctrl_fifo_empty = '0') then wb_dat_o <= ctrl_fifo_dout(31 downto 0); ctrl_fifo_dout_tmp <= ctrl_fifo_dout(63 downto 32); wb_ack_o <= '1'; ctrl_fifo_rden <= '1'; else wb_dat_o <= x"FFFFFFFF"; ctrl_fifo_dout_tmp <= (others => '0'); wb_ack_o <= '1'; ctrl_fifo_rden <= '0'; end if; elsif (wb_adr_i(3 downto 0) = x"1") then -- Count wb_dat_o <= ctrl_fifo_dout_tmp; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"2") then -- Loopback wb_dat_o(31 downto 1) <= (others => '0'); wb_dat_o(0) <= loopback; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"3") then -- Data Rate wb_dat_o <= data_rate; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"5") then -- Bridge Empty wb_dat_o(31 downto 1) <= (others => '0'); wb_dat_o(0) <= data_fifo_empty_true; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"6") then -- Cur Count wb_dat_o <= std_logic_vector(dma_data_cnt_d); wb_ack_o <= '1'; else wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end if; else -- WRITE wb_ack_o <= '1'; if (wb_adr_i(3 downto 0) = x"2") then loopback <= wb_dat_i(0); elsif (wb_adr_i(3 downto 0) = x"4") then rx_valid_local <= '1'; end if; end if; end if; end if; end process wb_slave_proc; -- Data from Rx data_rec : process (sys_clk_i, rst_n_i) begin if (rst_n_i <= '0') then data_fifo_wren <= '0'; data_fifo_din <= (others => '0'); elsif rising_edge(sys_clk_i) then if (loopback = '1') then data_fifo_wren <= rx_valid_local_d; data_fifo_din <= X"03000000" & rx_data_local_d; else data_fifo_wren <= rx_valid_i; data_fifo_din <= rx_data_i; end if; end if; end process data_rec; -- Empty logic to produce some backpressure data_fifo_empty <= '1' when (data_fifo_empty_true = '1') else data_fifo_empty_pressure; empty_proc : process(dma_clk_i, rst_n_i) begin if (rst_n_i = '0') then data_fifo_empty_pressure <= '0'; data_fifo_empty_cnt <= (others => '0'); elsif rising_edge(dma_clk_i) then -- Timeout Counter if (data_fifo_empty_true = '0' and data_fifo_empty_pressure = '1') then data_fifo_empty_cnt <= data_fifo_empty_cnt + 1; elsif (data_fifo_empty_true = '1') then data_fifo_empty_cnt <= (others => '0'); end if; if (data_fifo_empty_cnt > c_EMPTY_TIMEOUT) then data_fifo_empty_pressure <= '0'; elsif (data_fifo_prog_empty = '0') then data_fifo_empty_pressure <= '0'; elsif (data_fifo_empty_true = '1') then data_fifo_empty_pressure <= '1'; end if; end if; end process empty_proc; -- DMA Master and data control dma_stb_valid <= dma_stb_t and not data_fifo_empty; to_ddr_proc: process(dma_clk_i, rst_n_i) begin if(rst_n_i = '0') then dma_stb_t <= '0'; data_fifo_rden <= '0'; dma_adr_o <= (others => '0'); dma_dat_o <= (others => '0'); dma_cyc_o <= '0'; dma_stb_o <= '0'; dma_we_o <= '1'; -- Write only elsif rising_edge(dma_clk_i) then if (data_fifo_empty = '0' and dma_stall_i = '0' and ctrl_fifo_full = '0') then dma_stb_t <= '1'; data_fifo_rden <= '1'; else dma_stb_t <= '0'; data_fifo_rden <= '0'; end if; if (data_fifo_empty = '0' or dma_ack_cnt > 0) then dma_cyc_o <= '1'; else dma_cyc_o <= '0'; end if; dma_adr_o <= std_logic_vector(dma_adr_cnt); dma_dat_o <= data_fifo_dout; dma_stb_o <= dma_stb_t and not data_fifo_empty; dma_we_o <= '1'; -- Write only end if; end process to_ddr_proc; adr_proc : process (dma_clk_i, rst_n_i) begin if (rst_n_i = '0') then ctrl_fifo_wren <= '0'; dma_adr_cnt <= (others => '0'); dma_start_adr <= (others => '0'); dma_data_cnt <= (others => '0'); dma_data_cnt_d <= (others => '0'); dma_timeout_cnt <= (others => '0'); ctrl_fifo_din(63 downto 0) <= (others => '0'); dma_ack_cnt <= (others => '0'); elsif rising_edge(dma_clk_i) then -- Address Counter if (dma_stb_valid = '1') then dma_adr_cnt <= dma_adr_cnt + 1; end if; if (dma_stb_valid = '1' and dma_ack_i = '0') then dma_ack_cnt <= dma_ack_cnt + 1; elsif (dma_stb_valid = '0' and dma_ack_i = '1' and dma_ack_cnt > 0) then dma_ack_cnt <= dma_ack_cnt - 1; end if; -- Package size counter -- Check if Fifo is full if (dma_stb_valid = '1' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE; dma_data_cnt <= TO_UNSIGNED(2, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '0' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE; dma_data_cnt <= TO_UNSIGNED(0, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '0' and dma_timeout_cnt >= c_TIMEOUT and dma_data_cnt > 0 and ctrl_fifo_full ='0') then ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt); ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr); dma_start_adr <= dma_start_adr + dma_data_cnt; dma_data_cnt <= TO_UNSIGNED(0, 32); ctrl_fifo_wren <= '1'; elsif (dma_stb_valid = '1') then dma_data_cnt <= dma_data_cnt + 2; ctrl_fifo_wren <= '0'; else ctrl_fifo_wren <= '0'; end if; dma_data_cnt_d <= dma_data_cnt; -- if (dma_data_cnt = 0 and ctrl_fifo_wren = '1') then -- New package -- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt); -- elsif (dma_data_cnt = 1 and ctrl_fifo_wren = '1') then -- Flying take over -- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt-1); -- end if; -- Timeout counter if (dma_data_cnt > 0 and data_fifo_empty = '1') then dma_timeout_cnt <= dma_timeout_cnt + 1; elsif (data_fifo_empty = '0') then dma_timeout_cnt <= TO_UNSIGNED(0, 32); end if; end if; end process adr_proc; -- Data Rate maeasurement data_rate_proc: process(sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then data_rate_cnt <= (others => '0'); data_rate <= (others => '0'); time_cnt <= (others => '0'); time_pulse <= '0'; elsif rising_edge(sys_clk_i) then -- 1Hz pulser if (time_cnt = c_TIME_FRAME) then time_cnt <= (others => '0'); time_pulse <= '1'; else time_cnt <= time_cnt + 1; time_pulse <= '0'; end if; if (time_pulse = '1') then data_rate <= std_logic_vector(data_rate_cnt); data_rate_cnt <= (others => '0'); elsif (data_fifo_wren = '1') then data_rate_cnt <= data_rate_cnt + 1; end if; end if; end process data_rate_proc; -- Loopback delay delayproc : process (sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then rx_data_local <= (others => '0'); rx_data_local_d <= (others => '0'); rx_valid_local_d <= '0'; elsif rising_edge(sys_clk_i) then rx_data_local_d <= wb_dat_i; rx_valid_local_d <= rx_valid_local; end if; end process; -- Trigger sync and count trig_sync : process (sys_clk_i, rst_n_i) begin if (rst_n_i = '0') then trig_pulse_d0 <= '0'; trig_pulse_d1 <= '0'; trig_pulse_pos <= '0'; trig_cnt <= (others => '0'); elsif rising_edge(sys_clk_i) then trig_pulse_d0 <= trig_pulse_i; trig_pulse_d1 <= trig_pulse_d0; if (trig_pulse_d0 = '1' and trig_pulse_d1 = '0') then trig_pulse_pos <= '1'; else trig_pulse_pos <= '0'; end if; if (trig_pulse_pos = '1') then trig_cnt <= trig_cnt + 1; end if; end if; end process trig_sync; cmp_rx_bridge_fifo : rx_bridge_fifo PORT MAP ( rst => not rst_n_i, wr_clk => sys_clk_i, rd_clk => dma_clk_i, din => data_fifo_din, wr_en => data_fifo_wren, rd_en => data_fifo_rden, prog_full_thresh => std_logic_vector(c_ALMOST_FULL_THRESHOLD), prog_empty_thresh => std_logic_vector(c_EMPTY_THRESHOLD), dout => data_fifo_dout, full => data_fifo_full, empty => data_fifo_empty_true, prog_full => data_fifo_almost_full, prog_empty => data_fifo_prog_empty ); cmp_rx_bridge_ctrl_fifo : rx_bridge_ctrl_fifo PORT MAP ( rst => not rst_n_i, wr_clk => dma_clk_i, rd_clk => sys_clk_i, din => ctrl_fifo_din, wr_en => ctrl_fifo_wren, rd_en => ctrl_fifo_rden, dout => ctrl_fifo_dout, full => ctrl_fifo_full, empty => ctrl_fifo_empty ); end Behavioral;

gpl-3.0

b9717917d9cb14290b12ff081e8ca29b

0.593345

2.595654

false

tdaede/daala_zynq

daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_cntrl_strm.vhd

1

24,997

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_cntrl_strm.vhd -- Description: This entity is MM2S control stream logic -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.clog2; use proc_common_v4_0.proc_common_pkg.max2; ------------------------------------------------------------------------------- entity axi_sg_cntrl_strm is generic( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Control Stream Data Width C_FAMILY : string := "virtex7" -- Target FPGA Device Family ); port ( -- Secondary clock / reset m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Primary clock / reset -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- -- MM2S Error -- mm2s_stop : in std_logic ; -- -- -- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) -- cntrlstrm_fifo_wren : in std_logic ; -- cntrlstrm_fifo_din : in std_logic_vector -- (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); -- cntrlstrm_fifo_full : out std_logic ; -- -- -- -- Memory Map to Stream Control Stream Interface -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- ((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);-- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic ; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_cntrl_strm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_cntrl_strm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Number of words deep fifo needs to be -- Only 5 app fields, but set to 8 so depth is a power of 2 constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH); -- Width of fifo rd and wr counts - only used for proper fifo operation constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- FIFO signals signal cntrl_fifo_rden : std_logic := '0'; signal cntrl_fifo_empty : std_logic := '0'; signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0'); signal cntrl_fifo_dvalid: std_logic := '0'; signal cntrl_tdata : std_logic_vector (C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0'); signal cntrl_tkeep : std_logic_vector ((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0'; signal cntrl_tvalid : std_logic := '0'; signal cntrl_tready : std_logic := '0'; signal cntrl_tlast : std_logic := '0'; signal sinit : std_logic := '0'; signal m_valid : std_logic := '0'; signal m_ready : std_logic := '0'; signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_last : std_logic := '0'; signal skid_rst : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- All bytes always valid cntrl_tkeep <= (others => '1'); -- Primary Clock is synchronous to Secondary Clock therfore -- instantiate a sync fifo. GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate signal mm2s_stop_d1 : std_logic := '0'; signal mm2s_stop_re : std_logic := '0'; signal xfer_in_progress : std_logic := '0'; begin -- reset on hard reset or mm2s stop sinit <= not m_axi_sg_aresetn or mm2s_stop; -- Generate Synchronous FIFO I_CNTRL_FIFO : entity proc_common_v4_0.sync_fifo_fg generic map ( C_FAMILY => C_FAMILY , C_MEMORY_TYPE => USE_LOGIC_FIFOS, C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1, C_WRITE_DEPTH => CNTRL_FIFO_DEPTH , C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1, C_READ_DEPTH => CNTRL_FIFO_DEPTH , C_PORTS_DIFFER => 0, C_HAS_DCOUNT => 0, --req for proper fifo operation C_HAS_ALMOST_FULL => 0, C_HAS_RD_ACK => 0, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 0, C_HAS_WR_ERR => 0, C_RD_ACK_LOW => 0, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_PRELOAD_REGS => 1,-- 1 = first word fall through C_PRELOAD_LATENCY => 0 -- 0 = first word fall through -- C_USE_EMBEDDED_REG => 1 -- 0 ; ) port map ( Clk => m_axi_sg_aclk , Sinit => sinit , Din => cntrlstrm_fifo_din , Wr_en => cntrlstrm_fifo_wren , Rd_en => cntrl_fifo_rden , Dout => cntrl_fifo_dout , Full => cntrlstrm_fifo_full , Empty => cntrl_fifo_empty , Almost_full => open , Data_count => open , Rd_ack => open , Rd_err => open , Wr_ack => open , Wr_err => open ); -- I_UPDT_DATA_FIFO : entity proc_common_v4_0.srl_fifo_f -- generic map ( -- C_DWIDTH => 33 , -- C_DEPTH => 24 , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- Clk => m_axi_sg_aclk , -- Reset => sinit , -- FIFO_Write => cntrlstrm_fifo_wren , -- Data_In => cntrlstrm_fifo_din , -- FIFO_Read => cntrl_fifo_rden , -- Data_Out => cntrl_fifo_dout , -- FIFO_Empty => cntrl_fifo_empty , -- FIFO_Full => cntrlstrm_fifo_full, -- Addr => open -- ); cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty); VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then -- follower_reg_mm2s <= (others => '0'); follower_full_mm2s <= '0'; follower_empty_mm2s <= '1'; else if (cntrl_fifo_rden = '1') then -- follower_reg_mm2s <= sts_queue_dout; follower_full_mm2s <= '1'; follower_empty_mm2s <= '0'; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE; VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then follower_reg_mm2s <= (others => '0'); else if (cntrl_fifo_rden = '1') then follower_reg_mm2s <= cntrl_fifo_dout; end if; end if; end if; end process VALID_REG_MM2S_ACTIVE1; ----------------------------------------------------------------------- -- Control Stream OUT Side ----------------------------------------------------------------------- -- Read if fifo is not empty and target is ready -- cntrl_fifo_rden <= not cntrl_fifo_empty -- and cntrl_tready; -- Drive valid if fifo is not empty or in the middle -- of transfer and stop issued. cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty or (xfer_in_progress and mm2s_stop_re); -- Pass data out to control channel with MSB driving tlast cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH)) or (xfer_in_progress and mm2s_stop_re); cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); -- Register stop to create re pulse for cleaning shutting down -- stream out during soft reset. REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_stop_d1 <= '0'; else mm2s_stop_d1 <= mm2s_stop; end if; end if; end process REG_STOP; mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1; ------------------------------------------------------------- -- Flag transfer in progress. If xfer in progress then -- a fake tlast and tvalid need to be asserted during soft -- reset else no need of tlast. ------------------------------------------------------------- TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then xfer_in_progress <= '0'; elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then xfer_in_progress <= '1'; end if; end if; end process TRANSFER_IN_PROGRESS; skid_rst <= not m_axi_sg_aresetn; --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- -- CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf -- generic map( -- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH -- ) -- port map( -- -- System Ports -- ACLK => m_axi_sg_aclk , -- ARST => skid_rst , -- skid_stop => mm2s_stop_re , -- -- Slave Side (Stream Data Input) -- S_VALID => cntrl_tvalid , -- S_READY => cntrl_tready , -- S_Data => cntrl_tdata , -- S_STRB => cntrl_tkeep , -- S_Last => cntrl_tlast , -- -- Master Side (Stream Data Output -- M_VALID => m_axis_mm2s_cntrl_tvalid , -- M_READY => m_axis_mm2s_cntrl_tready , -- M_Data => m_axis_mm2s_cntrl_tdata , -- M_STRB => m_axis_mm2s_cntrl_tkeep , -- M_Last => m_axis_mm2s_cntrl_tlast -- ); m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid; cntrl_tready <= m_axis_mm2s_cntrl_tready; m_axis_mm2s_cntrl_tdata <= cntrl_tdata; m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep; m_axis_mm2s_cntrl_tlast <= cntrl_tlast; end generate GEN_SYNC_FIFO; -- Primary Clock is asynchronous to Secondary Clock therfore -- instantiate an async fifo. GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate ATTRIBUTE async_reg : STRING; signal mm2s_stop_reg : std_logic := '0'; -- CR605883 signal p_mm2s_stop_d1_cdc_tig : std_logic := '0'; signal p_mm2s_stop_d2 : std_logic := '0'; signal p_mm2s_stop_d3 : std_logic := '0'; signal p_mm2s_stop_re : std_logic := '0'; signal xfer_in_progress : std_logic := '0'; -- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true"; begin -- reset on hard reset, soft reset, or mm2s error sinit <= not p_reset_n or p_mm2s_stop_d2; -- Generate Asynchronous FIFO I_CNTRL_STRM_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord generic map( C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 , -- Temp work around for issue in async fifo model C_DEPTH => CNTRL_FIFO_DEPTH-1 , C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH , -- C_DEPTH => 31 , -- C_CNT_WIDTH => 5 , C_USE_BLKMEM => USE_LOGIC_FIFOS , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => sinit , AFIFO_Wr_clk => m_axi_sg_aclk , AFIFO_Wr_en => cntrlstrm_fifo_wren , AFIFO_Din => cntrlstrm_fifo_din , AFIFO_Rd_clk => axi_prmry_aclk , AFIFO_Rd_en => cntrl_fifo_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => cntrl_fifo_dvalid , AFIFO_Dout => cntrl_fifo_dout , AFIFO_Full => cntrlstrm_fifo_full , AFIFO_Empty => cntrl_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); ----------------------------------------------------------------------- -- Control Stream OUT Side ----------------------------------------------------------------------- -- Read if fifo is not empty and target is ready cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data and cntrl_tready; -- target ready -- Drive valid if fifo is not empty or in the middle -- of transfer and stop issued. cntrl_tvalid <= cntrl_fifo_dvalid or (xfer_in_progress and p_mm2s_stop_re); -- Pass data out to control channel with MSB driving tlast cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH); -- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH)) -- or (xfer_in_progress and p_mm2s_stop_re); cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); -- CR605883 -- Register stop to provide pure FF output for synchronizer REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_stop_reg <= '0'; else mm2s_stop_reg <= mm2s_stop; end if; end if; end process REG_STOP; -- Double/triple register mm2s error into primary clock domain -- Triple register to give two versions with min double reg for use -- in rising edge detection. IMP_SYNC_FLOP : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => 2 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => mm2s_stop_reg, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => p_mm2s_stop_d2, scndry_vect_out => open ); REG_ERR2PRMRY : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then -- p_mm2s_stop_d1_cdc_tig <= '0'; -- p_mm2s_stop_d2 <= '0'; p_mm2s_stop_d3 <= '0'; else --p_mm2s_stop_d1_cdc_tig <= mm2s_stop; -- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg; -- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig; p_mm2s_stop_d3 <= p_mm2s_stop_d2; end if; end if; end process REG_ERR2PRMRY; -- Rising edge pulse for use in shutting down stream output p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3; ------------------------------------------------------------- -- Flag transfer in progress. If xfer in progress then -- a fake tlast needs to be asserted during soft reset. -- else no need of tlast. ------------------------------------------------------------- TRANSFER_IN_PROGRESS : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then xfer_in_progress <= '0'; elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then xfer_in_progress <= '1'; end if; end if; end process TRANSFER_IN_PROGRESS; skid_rst <= not p_reset_n; CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf generic map( C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ) port map( -- System Ports ACLK => axi_prmry_aclk , ARST => skid_rst , skid_stop => p_mm2s_stop_re , -- Slave Side (Stream Data Input) S_VALID => cntrl_tvalid , S_READY => cntrl_tready , S_Data => cntrl_tdata , S_STRB => cntrl_tkeep , S_Last => cntrl_tlast , -- Master Side (Stream Data Output M_VALID => m_axis_mm2s_cntrl_tvalid , M_READY => m_axis_mm2s_cntrl_tready , M_Data => m_axis_mm2s_cntrl_tdata , M_STRB => m_axis_mm2s_cntrl_tkeep , M_Last => m_axis_mm2s_cntrl_tlast ); end generate GEN_ASYNC_FIFO; end implementation;

bsd-2-clause

0606f2c65d4cf3ed33f98c63e14ca093

0.441853

4.139261

false

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0/synth/system_ov7670_controller_1_0.vhd

2

4,423

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:ov7670_controller:1.0 -- IP Revision: 9 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_ov7670_controller_1_0 IS PORT ( clk : IN STD_LOGIC; resend : IN STD_LOGIC; config_finished : OUT STD_LOGIC; sioc : OUT STD_LOGIC; siod : INOUT STD_LOGIC; reset : OUT STD_LOGIC; pwdn : OUT STD_LOGIC; xclk : OUT STD_LOGIC ); END system_ov7670_controller_1_0; ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT ov7670_controller IS PORT ( clk : IN STD_LOGIC; resend : IN STD_LOGIC; config_finished : OUT STD_LOGIC; sioc : OUT STD_LOGIC; siod : INOUT STD_LOGIC; reset : OUT STD_LOGIC; pwdn : OUT STD_LOGIC; xclk : OUT STD_LOGIC ); END COMPONENT ov7670_controller; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_1_0_arch : ARCHITECTURE IS "system_ov7670_controller_1_0,ov7670_controller,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "system_ov7670_controller_1_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; BEGIN U0 : ov7670_controller PORT MAP ( clk => clk, resend => resend, config_finished => config_finished, sioc => sioc, siod => siod, reset => reset, pwdn => pwdn, xclk => xclk ); END system_ov7670_controller_1_0_arch;

mit

606ce4eccf38fe8202c08fb43f4ba93a

0.732534

3.914159

false

loa-org/loa-hdl

modules/ir_rx/tb/ir_rx_adcs_tb.vhd

2

2,463

------------------------------------------------------------------------------- -- Title : Testbench for design "ir_rx_adcs" -- Project : ------------------------------------------------------------------------------- -- File : ir_rx_adcs_tb.vhd -- Author : strongly-typed -- Created : 2012-04-27 -- Platform : -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.adc_ltc2351_pkg.all; use work.ir_rx_module_pkg.all; ------------------------------------------------------------------------------- entity ir_rx_adcs_tb is end ir_rx_adcs_tb; ------------------------------------------------------------------------------- architecture tb of ir_rx_adcs_tb is -- component generics constant CHANNELS : positive := 12; -- component ports signal clk_sample_en : std_logic := '0'; signal adc_out_s : ir_rx_module_spi_out_type; signal adc_in_s : ir_rx_module_spi_in_type; signal adc_values_s : adc_ltc2351_values_type(CHANNELS-1 downto 0); signal adc_done_s : std_logic; -- clock signal Clk : std_logic := '1'; begin -- tb -- component instantiation DUT : ir_rx_adcs generic map ( CHANNELS => CHANNELS) port map ( clk_sample_en_i_p => clk_sample_en, adc_o_p => adc_out_s, adc_i_p => adc_in_s, adc_values_o_p => adc_values_s, adc_done_o_p => adc_done_s, clk => clk); -- clock generation clk <= not clk after 10 ns; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here wait until clk = '0'; wait until clk = '0'; wait until clk = '0'; clk_sample_en <= '1'; wait until clk = '0'; clk_sample_en <= '0'; wait for 10 ms; end process WaveGen_Proc; end tb; ------------------------------------------------------------------------------- configuration ir_rx_adcs_tb_tb_cfg of ir_rx_adcs_tb is for tb end for; end ir_rx_adcs_tb_tb_cfg; -------------------------------------------------------------------------------

bsd-3-clause

454544ccdf71a5bc3a09d6c4e384bf4c

0.405197

4.253886

false

loa-org/loa-hdl

modules/motor_control/tb/commutation_tb.vhd

2

2,121

library ieee; use ieee.std_logic_1164.all; entity commutation_tb is end commutation_tb; library work; use work.motor_control_pkg.all; use work.symmetric_pwm_deadtime_pkg.all; use work.commutation_pkg.all; architecture behavior of commutation_tb is signal clk : std_logic := '0'; signal clk_en : std_logic := '1'; signal center : std_logic; signal value : std_logic_vector(7 downto 0) := x"F0"; signal driver_stage : bldc_driver_stage_type; signal pwm : half_bridge_type; signal sd : std_logic := '0'; signal dir : std_logic := '0'; signal hall : hall_sensor_type := ('0', '0', '0'); begin clk <= not clk after 10 NS; -- 50 Mhz clock waveform : process begin wait for 50 US; hall <= ('1', '0', '1'); wait for 100 US; hall <= ('1', '0', '0'); wait for 100 US; hall <= ('1', '1', '0'); wait for 100 US; hall <= ('0', '1', '0'); wait for 100 US; hall <= ('0', '1', '1'); wait for 100 US; hall <= ('0', '0', '1'); wait for 100 US; hall <= ('1', '0', '1'); wait for 100 US; hall <= ('1', '0', '0'); wait for 100 US; hall <= ('1', '1', '0'); wait for 100 US; hall <= ('0', '1', '0'); wait for 100 US; hall <= ('0', '1', '1'); wait for 100 US; hall <= ('0', '0', '1'); end process; waveform2 : process begin wait for 600 US; sd <= '1'; wait for 20 US; sd <= '0'; dir <= '1'; end process; pwm_generator : symmetric_pwm_deadtime generic map ( WIDTH => 8, T_DEAD => 20) port map ( pwm_p => pwm, clk_en_p => clk_en, value_p => value, center_p => center, reset => '0', clk => clk); commutation_1 : commutation port map ( driver_stage_p => driver_stage, hall_p => hall, pwm_p => pwm, dir_p => dir, sd_p => sd, clk => clk); end;

bsd-3-clause

f61b2ac16d400e3f0f75adbcd9716765

0.459689

3.319249

false

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl

1

804,717

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Thu May 25 15:28:04 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_zed_hdmi_0_0/system_zed_hdmi_0_0_sim_netlist.vhdl -- Design : system_zed_hdmi_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_zed_hdmi_0_0_i2c_sender is port ( hdmi_sda : out STD_LOGIC; hdmi_scl : out STD_LOGIC; clk_100 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_zed_hdmi_0_0_i2c_sender : entity is "i2c_sender"; end system_zed_hdmi_0_0_i2c_sender; architecture STRUCTURE of system_zed_hdmi_0_0_i2c_sender is signal address : STD_LOGIC_VECTOR ( 5 downto 0 ); signal \address[0]_i_1_n_0\ : STD_LOGIC; signal \address[1]_i_1_n_0\ : STD_LOGIC; signal \address[2]_i_1_n_0\ : STD_LOGIC; signal \address[3]_i_1_n_0\ : STD_LOGIC; signal \address[3]_i_2_n_0\ : STD_LOGIC; signal \address[4]_i_1_n_0\ : STD_LOGIC; signal \address[5]_i_1_n_0\ : STD_LOGIC; signal \address[5]_i_2_n_0\ : STD_LOGIC; signal \address[5]_i_3_n_0\ : STD_LOGIC; signal \address[5]_i_4_n_0\ : STD_LOGIC; signal \address[5]_i_5_n_0\ : STD_LOGIC; signal \address[5]_i_6_n_0\ : STD_LOGIC; signal \address[5]_i_7_n_0\ : STD_LOGIC; signal busy_sr : STD_LOGIC; signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[28]_i_2_n_0\ : STD_LOGIC; signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC; signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[19]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[20]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC; signal clk_first_quarter : STD_LOGIC_VECTOR ( 28 to 28 ); signal \clk_first_quarter[28]_i_1_n_0\ : STD_LOGIC; signal clk_last_quarter : STD_LOGIC_VECTOR ( 28 downto 1 ); signal \clk_last_quarter[2]_i_1_n_0\ : STD_LOGIC; signal \data_sr[0]_i_1_n_0\ : STD_LOGIC; signal \data_sr[0]_i_2_n_0\ : STD_LOGIC; signal \data_sr_reg_n_0_[0]\ : STD_LOGIC; signal \data_sr_reg_n_0_[10]\ : STD_LOGIC; signal \data_sr_reg_n_0_[11]\ : STD_LOGIC; signal \data_sr_reg_n_0_[12]\ : STD_LOGIC; signal \data_sr_reg_n_0_[13]\ : STD_LOGIC; signal \data_sr_reg_n_0_[14]\ : STD_LOGIC; signal \data_sr_reg_n_0_[15]\ : STD_LOGIC; signal \data_sr_reg_n_0_[16]\ : STD_LOGIC; signal \data_sr_reg_n_0_[17]\ : STD_LOGIC; signal \data_sr_reg_n_0_[18]\ : STD_LOGIC; signal \data_sr_reg_n_0_[19]\ : STD_LOGIC; signal \data_sr_reg_n_0_[1]\ : STD_LOGIC; signal \data_sr_reg_n_0_[20]\ : STD_LOGIC; signal \data_sr_reg_n_0_[21]\ : STD_LOGIC; signal \data_sr_reg_n_0_[22]\ : STD_LOGIC; signal \data_sr_reg_n_0_[23]\ : STD_LOGIC; signal \data_sr_reg_n_0_[24]\ : STD_LOGIC; signal \data_sr_reg_n_0_[25]\ : STD_LOGIC; signal \data_sr_reg_n_0_[26]\ : STD_LOGIC; signal \data_sr_reg_n_0_[27]\ : STD_LOGIC; signal \data_sr_reg_n_0_[28]\ : STD_LOGIC; signal \data_sr_reg_n_0_[2]\ : STD_LOGIC; signal \data_sr_reg_n_0_[3]\ : STD_LOGIC; signal \data_sr_reg_n_0_[4]\ : STD_LOGIC; signal \data_sr_reg_n_0_[5]\ : STD_LOGIC; signal \data_sr_reg_n_0_[6]\ : STD_LOGIC; signal \data_sr_reg_n_0_[7]\ : STD_LOGIC; signal \data_sr_reg_n_0_[8]\ : STD_LOGIC; signal \data_sr_reg_n_0_[9]\ : STD_LOGIC; signal divider : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \divider[0]_i_1_n_0\ : STD_LOGIC; signal \divider[1]_i_1_n_0\ : STD_LOGIC; signal \divider[2]_i_1_n_0\ : STD_LOGIC; signal \divider[3]_i_1_n_0\ : STD_LOGIC; signal \divider[4]_i_1_n_0\ : STD_LOGIC; signal \divider[5]_i_1_n_0\ : STD_LOGIC; signal \divider[5]_i_2_n_0\ : STD_LOGIC; signal \divider[6]_i_1_n_0\ : STD_LOGIC; signal \divider[7]_i_1_n_0\ : STD_LOGIC; signal \divider[7]_i_2_n_0\ : STD_LOGIC; signal \divider[7]_i_3_n_0\ : STD_LOGIC; signal finished_i_1_n_0 : STD_LOGIC; signal finished_reg_n_0 : STD_LOGIC; signal \initial_pause[5]_i_2_n_0\ : STD_LOGIC; signal \initial_pause[7]_i_1_n_0\ : STD_LOGIC; signal \initial_pause[7]_i_3_n_0\ : STD_LOGIC; signal \initial_pause_reg_n_0_[0]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[1]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[2]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[3]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[4]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[5]\ : STD_LOGIC; signal \initial_pause_reg_n_0_[6]\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal p_1_in : STD_LOGIC; signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal p_2_in : STD_LOGIC_VECTOR ( 18 downto 2 ); signal reg_value_reg_n_10 : STD_LOGIC; signal reg_value_reg_n_11 : STD_LOGIC; signal reg_value_reg_n_12 : STD_LOGIC; signal reg_value_reg_n_13 : STD_LOGIC; signal reg_value_reg_n_14 : STD_LOGIC; signal reg_value_reg_n_15 : STD_LOGIC; signal reg_value_reg_n_8 : STD_LOGIC; signal reg_value_reg_n_9 : STD_LOGIC; signal \tristate_sr[19]_i_1_n_0\ : STD_LOGIC; signal \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC; signal \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC; signal \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC; signal \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\ : STD_LOGIC; signal \tristate_sr_reg[28]_inv_n_0\ : STD_LOGIC; signal \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ : STD_LOGIC; signal \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ : STD_LOGIC; signal \tristate_sr_reg_gate__0_n_0\ : STD_LOGIC; signal \tristate_sr_reg_gate__1_n_0\ : STD_LOGIC; signal tristate_sr_reg_gate_n_0 : STD_LOGIC; signal \tristate_sr_reg_n_0_[10]\ : STD_LOGIC; signal \tristate_sr_reg_n_0_[18]\ : STD_LOGIC; signal \tristate_sr_reg_n_0_[19]\ : STD_LOGIC; signal \tristate_sr_reg_n_0_[1]\ : STD_LOGIC; signal \tristate_sr_reg_n_0_[9]\ : STD_LOGIC; signal tristate_sr_reg_r_0_n_0 : STD_LOGIC; signal tristate_sr_reg_r_1_n_0 : STD_LOGIC; signal tristate_sr_reg_r_2_n_0 : STD_LOGIC; signal tristate_sr_reg_r_3_n_0 : STD_LOGIC; signal tristate_sr_reg_r_4_n_0 : STD_LOGIC; signal tristate_sr_reg_r_5_n_0 : STD_LOGIC; signal tristate_sr_reg_r_6_n_0 : STD_LOGIC; signal tristate_sr_reg_r_n_0 : STD_LOGIC; signal NLW_reg_value_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_reg_value_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_reg_value_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \address[0]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \address[1]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \address[3]_i_2\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \address[5]_i_4\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \address[5]_i_6\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \data_sr[0]_i_2\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \data_sr[11]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \data_sr[2]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \initial_pause[0]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \initial_pause[1]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \initial_pause[2]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \initial_pause[5]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \initial_pause[6]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \initial_pause[7]_i_2\ : label is "soft_lutpair5"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of reg_value_reg : label is "INDEPENDENT"; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of reg_value_reg : label is "p0_d16"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of reg_value_reg : label is "{SYNTH-6 {cell *THIS*}}"; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of reg_value_reg : label is 1024; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of reg_value_reg : label is "reg_value"; attribute bram_addr_begin : integer; attribute bram_addr_begin of reg_value_reg : label is 0; attribute bram_addr_end : integer; attribute bram_addr_end of reg_value_reg : label is 1023; attribute bram_slice_begin : integer; attribute bram_slice_begin of reg_value_reg : label is 0; attribute bram_slice_end : integer; attribute bram_slice_end of reg_value_reg : label is 15; attribute srl_bus_name : string; attribute srl_bus_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg "; attribute srl_name : string; attribute srl_name of \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 "; attribute srl_bus_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg "; attribute srl_name of \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5 "; attribute srl_bus_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg "; attribute srl_name of \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\ : label is "\U0/Inst_i2c_sender/tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4 "; attribute SOFT_HLUTNM of \tristate_sr_reg_gate__0\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \tristate_sr_reg_gate__1\ : label is "soft_lutpair16"; begin \address[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => p_0_in, I1 => \address[5]_i_5_n_0\, I2 => \address[5]_i_3_n_0\, I3 => address(0), O => \address[0]_i_1_n_0\ ); \address[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00080800" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => address(0), I4 => address(1), O => \address[1]_i_1_n_0\ ); \address[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0008080808000000" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => address(1), I4 => address(0), I5 => address(2), O => \address[2]_i_1_n_0\ ); \address[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"08000008" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => \address[3]_i_2_n_0\, I4 => address(3), O => \address[3]_i_1_n_0\ ); \address[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => address(1), I1 => address(0), I2 => address(2), O => \address[3]_i_2_n_0\ ); \address[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"08000008" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => \address[5]_i_6_n_0\, I4 => address(4), O => \address[4]_i_1_n_0\ ); \address[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => finished_reg_n_0, I2 => p_1_in, I3 => \address[5]_i_4_n_0\, I4 => divider(7), I5 => p_0_in, O => \address[5]_i_1_n_0\ ); \address[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0808000800000800" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => \address[5]_i_5_n_0\, I2 => p_0_in, I3 => address(4), I4 => \address[5]_i_6_n_0\, I5 => address(5), O => \address[5]_i_2_n_0\ ); \address[5]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF7FFF" ) port map ( I0 => \p_0_in__0\(2), I1 => \p_0_in__0\(3), I2 => \p_0_in__0\(0), I3 => \p_0_in__0\(1), I4 => \address[5]_i_7_n_0\, O => \address[5]_i_3_n_0\ ); \address[5]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \divider[7]_i_3_n_0\, I1 => divider(6), O => \address[5]_i_4_n_0\ ); \address[5]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"00400000" ) port map ( I0 => finished_reg_n_0, I1 => p_1_in, I2 => divider(6), I3 => \divider[7]_i_3_n_0\, I4 => divider(7), O => \address[5]_i_5_n_0\ ); \address[5]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => address(2), I1 => address(0), I2 => address(1), I3 => address(3), O => \address[5]_i_6_n_0\ ); \address[5]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \p_0_in__0\(5), I1 => \p_0_in__0\(4), I2 => \p_0_in__0\(7), I3 => \p_0_in__0\(6), O => \address[5]_i_7_n_0\ ); \address_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[0]_i_1_n_0\, Q => address(0), R => '0' ); \address_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[1]_i_1_n_0\, Q => address(1), R => '0' ); \address_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[2]_i_1_n_0\, Q => address(2), R => '0' ); \address_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[3]_i_1_n_0\, Q => address(3), R => '0' ); \address_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[4]_i_1_n_0\, Q => address(4), R => '0' ); \address_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \address[5]_i_1_n_0\, D => \address[5]_i_2_n_0\, Q => address(5), R => '0' ); \busy_sr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FF200000" ) port map ( I0 => \address[5]_i_3_n_0\, I1 => finished_reg_n_0, I2 => p_1_in, I3 => p_0_in, I4 => divider(7), I5 => \address[5]_i_4_n_0\, O => busy_sr ); \busy_sr[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[9]\, O => \busy_sr[10]_i_1_n_0\ ); \busy_sr[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[10]\, O => \busy_sr[11]_i_1_n_0\ ); \busy_sr[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[11]\, O => \busy_sr[12]_i_1_n_0\ ); \busy_sr[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[12]\, O => \busy_sr[13]_i_1_n_0\ ); \busy_sr[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[13]\, O => \busy_sr[14]_i_1_n_0\ ); \busy_sr[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[14]\, O => \busy_sr[15]_i_1_n_0\ ); \busy_sr[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[15]\, O => \busy_sr[16]_i_1_n_0\ ); \busy_sr[17]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[16]\, O => \busy_sr[17]_i_1_n_0\ ); \busy_sr[18]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[17]\, O => \busy_sr[18]_i_1_n_0\ ); \busy_sr[19]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[18]\, O => \busy_sr[19]_i_1_n_0\ ); \busy_sr[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[0]\, O => \busy_sr[1]_i_1_n_0\ ); \busy_sr[20]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[19]\, O => \busy_sr[20]_i_1_n_0\ ); \busy_sr[21]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[20]\, O => \busy_sr[21]_i_1_n_0\ ); \busy_sr[22]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[21]\, O => \busy_sr[22]_i_1_n_0\ ); \busy_sr[23]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[22]\, O => \busy_sr[23]_i_1_n_0\ ); \busy_sr[24]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[23]\, O => \busy_sr[24]_i_1_n_0\ ); \busy_sr[25]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[24]\, O => \busy_sr[25]_i_1_n_0\ ); \busy_sr[26]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[25]\, O => \busy_sr[26]_i_1_n_0\ ); \busy_sr[27]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[26]\, O => \busy_sr[27]_i_1_n_0\ ); \busy_sr[28]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000040000000000" ) port map ( I0 => \address[5]_i_4_n_0\, I1 => divider(7), I2 => p_0_in, I3 => p_1_in, I4 => finished_reg_n_0, I5 => \address[5]_i_3_n_0\, O => \busy_sr[28]_i_1_n_0\ ); \busy_sr[28]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[27]\, O => \busy_sr[28]_i_2_n_0\ ); \busy_sr[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[1]\, O => \busy_sr[2]_i_1_n_0\ ); \busy_sr[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[2]\, O => \busy_sr[3]_i_1_n_0\ ); \busy_sr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[3]\, O => \busy_sr[4]_i_1_n_0\ ); \busy_sr[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[4]\, O => \busy_sr[5]_i_1_n_0\ ); \busy_sr[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[5]\, O => \busy_sr[6]_i_1_n_0\ ); \busy_sr[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[6]\, O => \busy_sr[7]_i_1_n_0\ ); \busy_sr[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[7]\, O => \busy_sr[8]_i_1_n_0\ ); \busy_sr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => \busy_sr_reg_n_0_[8]\, O => \busy_sr[9]_i_1_n_0\ ); \busy_sr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \address[5]_i_1_n_0\, Q => \busy_sr_reg_n_0_[0]\, R => '0' ); \busy_sr_reg[10]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[10]_i_1_n_0\, Q => \busy_sr_reg_n_0_[10]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[11]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[11]_i_1_n_0\, Q => \busy_sr_reg_n_0_[11]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[12]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[12]_i_1_n_0\, Q => \busy_sr_reg_n_0_[12]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[13]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[13]_i_1_n_0\, Q => \busy_sr_reg_n_0_[13]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[14]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[14]_i_1_n_0\, Q => \busy_sr_reg_n_0_[14]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[15]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[15]_i_1_n_0\, Q => \busy_sr_reg_n_0_[15]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[16]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[16]_i_1_n_0\, Q => \busy_sr_reg_n_0_[16]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[17]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[17]_i_1_n_0\, Q => \busy_sr_reg_n_0_[17]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[18]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[18]_i_1_n_0\, Q => \busy_sr_reg_n_0_[18]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[19]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[19]_i_1_n_0\, Q => \busy_sr_reg_n_0_[19]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[1]_i_1_n_0\, Q => \busy_sr_reg_n_0_[1]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[20]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[20]_i_1_n_0\, Q => \busy_sr_reg_n_0_[20]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[21]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[21]_i_1_n_0\, Q => \busy_sr_reg_n_0_[21]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[22]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[22]_i_1_n_0\, Q => \busy_sr_reg_n_0_[22]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[23]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[23]_i_1_n_0\, Q => \busy_sr_reg_n_0_[23]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[24]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[24]_i_1_n_0\, Q => \busy_sr_reg_n_0_[24]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[25]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[25]_i_1_n_0\, Q => \busy_sr_reg_n_0_[25]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[26]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[26]_i_1_n_0\, Q => \busy_sr_reg_n_0_[26]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[27]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[27]_i_1_n_0\, Q => \busy_sr_reg_n_0_[27]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[28]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[28]_i_2_n_0\, Q => p_0_in, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[2]_i_1_n_0\, Q => \busy_sr_reg_n_0_[2]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[3]_i_1_n_0\, Q => \busy_sr_reg_n_0_[3]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[4]_i_1_n_0\, Q => \busy_sr_reg_n_0_[4]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[5]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[5]_i_1_n_0\, Q => \busy_sr_reg_n_0_[5]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[6]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[6]_i_1_n_0\, Q => \busy_sr_reg_n_0_[6]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[7]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[7]_i_1_n_0\, Q => \busy_sr_reg_n_0_[7]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[8]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[8]_i_1_n_0\, Q => \busy_sr_reg_n_0_[8]\, S => \busy_sr[28]_i_1_n_0\ ); \busy_sr_reg[9]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \busy_sr[9]_i_1_n_0\, Q => \busy_sr_reg_n_0_[9]\, S => \busy_sr[28]_i_1_n_0\ ); \clk_first_quarter[28]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, I4 => clk_last_quarter(28), O => \clk_first_quarter[28]_i_1_n_0\ ); \clk_first_quarter_reg[28]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \clk_first_quarter[28]_i_1_n_0\, Q => clk_first_quarter(28), S => \busy_sr[28]_i_1_n_0\ ); \clk_last_quarter[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => p_1_in, I1 => finished_reg_n_0, I2 => \address[5]_i_3_n_0\, I3 => p_0_in, I4 => divider(7), I5 => \address[5]_i_4_n_0\, O => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(9), Q => clk_last_quarter(10), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(10), Q => clk_last_quarter(11), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(11), Q => clk_last_quarter(12), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(12), Q => clk_last_quarter(13), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(13), Q => clk_last_quarter(14), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(14), Q => clk_last_quarter(15), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(15), Q => clk_last_quarter(16), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(16), Q => clk_last_quarter(17), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(17), Q => clk_last_quarter(18), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(18), Q => clk_last_quarter(19), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \tristate_sr[19]_i_1_n_0\, Q => clk_last_quarter(1), R => '0' ); \clk_last_quarter_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(19), Q => clk_last_quarter(20), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(20), Q => clk_last_quarter(21), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(21), Q => clk_last_quarter(22), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(22), Q => clk_last_quarter(23), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(23), Q => clk_last_quarter(24), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(24), Q => clk_last_quarter(25), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(25), Q => clk_last_quarter(26), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(26), Q => clk_last_quarter(27), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(27), Q => clk_last_quarter(28), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(1), Q => clk_last_quarter(2), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(2), Q => clk_last_quarter(3), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(3), Q => clk_last_quarter(4), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(4), Q => clk_last_quarter(5), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(5), Q => clk_last_quarter(6), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(6), Q => clk_last_quarter(7), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(7), Q => clk_last_quarter(8), R => \clk_last_quarter[2]_i_1_n_0\ ); \clk_last_quarter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => clk_last_quarter(8), Q => clk_last_quarter(9), R => \clk_last_quarter[2]_i_1_n_0\ ); \data_sr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EAEACAEAEAEAEAEA" ) port map ( I0 => \data_sr_reg_n_0_[0]\, I1 => p_0_in, I2 => \data_sr[0]_i_2_n_0\, I3 => p_1_in, I4 => finished_reg_n_0, I5 => \address[5]_i_3_n_0\, O => \data_sr[0]_i_1_n_0\ ); \data_sr[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"20" ) port map ( I0 => divider(7), I1 => \divider[7]_i_3_n_0\, I2 => divider(6), O => \data_sr[0]_i_2_n_0\ ); \data_sr[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[10]\, I1 => p_0_in, I2 => \p_0_in__0\(0), O => p_2_in(11) ); \data_sr[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[11]\, I1 => p_0_in, I2 => \p_0_in__0\(1), O => p_2_in(12) ); \data_sr[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[12]\, I1 => p_0_in, I2 => \p_0_in__0\(2), O => p_2_in(13) ); \data_sr[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[13]\, I1 => p_0_in, I2 => \p_0_in__0\(3), O => p_2_in(14) ); \data_sr[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[14]\, I1 => p_0_in, I2 => \p_0_in__0\(4), O => p_2_in(15) ); \data_sr[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[15]\, I1 => p_0_in, I2 => \p_0_in__0\(5), O => p_2_in(16) ); \data_sr[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[16]\, I1 => p_0_in, I2 => \p_0_in__0\(6), O => p_2_in(17) ); \data_sr[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[17]\, I1 => p_0_in, I2 => \p_0_in__0\(7), O => p_2_in(18) ); \data_sr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[1]\, I1 => p_0_in, I2 => reg_value_reg_n_15, O => p_2_in(2) ); \data_sr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[2]\, I1 => p_0_in, I2 => reg_value_reg_n_14, O => p_2_in(3) ); \data_sr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[3]\, I1 => p_0_in, I2 => reg_value_reg_n_13, O => p_2_in(4) ); \data_sr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[4]\, I1 => p_0_in, I2 => reg_value_reg_n_12, O => p_2_in(5) ); \data_sr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[5]\, I1 => p_0_in, I2 => reg_value_reg_n_11, O => p_2_in(6) ); \data_sr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[6]\, I1 => p_0_in, I2 => reg_value_reg_n_10, O => p_2_in(7) ); \data_sr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[7]\, I1 => p_0_in, I2 => reg_value_reg_n_9, O => p_2_in(8) ); \data_sr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[8]\, I1 => p_0_in, I2 => reg_value_reg_n_8, O => p_2_in(9) ); \data_sr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => '1', D => \data_sr[0]_i_1_n_0\, Q => \data_sr_reg_n_0_[0]\, R => '0' ); \data_sr_reg[10]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[9]\, Q => \data_sr_reg_n_0_[10]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(11), Q => \data_sr_reg_n_0_[11]\, R => '0' ); \data_sr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(12), Q => \data_sr_reg_n_0_[12]\, R => '0' ); \data_sr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(13), Q => \data_sr_reg_n_0_[13]\, R => '0' ); \data_sr_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(14), Q => \data_sr_reg_n_0_[14]\, R => '0' ); \data_sr_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(15), Q => \data_sr_reg_n_0_[15]\, R => '0' ); \data_sr_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(16), Q => \data_sr_reg_n_0_[16]\, R => '0' ); \data_sr_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(17), Q => \data_sr_reg_n_0_[17]\, R => '0' ); \data_sr_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(18), Q => \data_sr_reg_n_0_[18]\, R => '0' ); \data_sr_reg[19]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[18]\, Q => \data_sr_reg_n_0_[19]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[0]\, Q => \data_sr_reg_n_0_[1]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[19]\, Q => \data_sr_reg_n_0_[20]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[21]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[20]\, Q => \data_sr_reg_n_0_[21]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[21]\, Q => \data_sr_reg_n_0_[22]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[22]\, Q => \data_sr_reg_n_0_[23]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[24]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[23]\, Q => \data_sr_reg_n_0_[24]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[25]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[24]\, Q => \data_sr_reg_n_0_[25]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[26]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[25]\, Q => \data_sr_reg_n_0_[26]\, S => \address[5]_i_1_n_0\ ); \data_sr_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[26]\, Q => \data_sr_reg_n_0_[27]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => \data_sr_reg_n_0_[27]\, Q => \data_sr_reg_n_0_[28]\, R => \address[5]_i_1_n_0\ ); \data_sr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(2), Q => \data_sr_reg_n_0_[2]\, R => '0' ); \data_sr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(3), Q => \data_sr_reg_n_0_[3]\, R => '0' ); \data_sr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(4), Q => \data_sr_reg_n_0_[4]\, R => '0' ); \data_sr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(5), Q => \data_sr_reg_n_0_[5]\, R => '0' ); \data_sr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(6), Q => \data_sr_reg_n_0_[6]\, R => '0' ); \data_sr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(7), Q => \data_sr_reg_n_0_[7]\, R => '0' ); \data_sr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(8), Q => \data_sr_reg_n_0_[8]\, R => '0' ); \data_sr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_100, CE => busy_sr, D => p_2_in(9), Q => \data_sr_reg_n_0_[9]\, R => '0' ); \divider[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00AE" ) port map ( I0 => p_0_in, I1 => p_1_in, I2 => finished_reg_n_0, I3 => divider(0), O => \divider[0]_i_1_n_0\ ); \divider[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00F4F400" ) port map ( I0 => finished_reg_n_0, I1 => p_1_in, I2 => p_0_in, I3 => divider(0), I4 => divider(1), O => \divider[1]_i_1_n_0\ ); \divider[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00F4F4F4F4000000" ) port map ( I0 => finished_reg_n_0, I1 => p_1_in, I2 => p_0_in, I3 => divider(1), I4 => divider(0), I5 => divider(2), O => \divider[2]_i_1_n_0\ ); \divider[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2AAA8000" ) port map ( I0 => \divider[7]_i_1_n_0\, I1 => divider(2), I2 => divider(0), I3 => divider(1), I4 => divider(3), O => \divider[3]_i_1_n_0\ ); \divider[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFF000080000000" ) port map ( I0 => divider(2), I1 => divider(0), I2 => divider(1), I3 => divider(3), I4 => \divider[7]_i_1_n_0\, I5 => divider(4), O => \divider[4]_i_1_n_0\ ); \divider[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"88A84454" ) port map ( I0 => \divider[5]_i_2_n_0\, I1 => p_0_in, I2 => p_1_in, I3 => finished_reg_n_0, I4 => divider(5), O => \divider[5]_i_1_n_0\ ); \divider[5]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => divider(3), I1 => divider(1), I2 => divider(0), I3 => divider(2), I4 => divider(4), O => \divider[5]_i_2_n_0\ ); \divider[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"88A84454" ) port map ( I0 => \divider[7]_i_3_n_0\, I1 => p_0_in, I2 => p_1_in, I3 => finished_reg_n_0, I4 => divider(6), O => \divider[6]_i_1_n_0\ ); \divider[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"F4" ) port map ( I0 => finished_reg_n_0, I1 => p_1_in, I2 => p_0_in, O => \divider[7]_i_1_n_0\ ); \divider[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"B0B0BBB040404440" ) port map ( I0 => \divider[7]_i_3_n_0\, I1 => divider(6), I2 => p_0_in, I3 => p_1_in, I4 => finished_reg_n_0, I5 => divider(7), O => \divider[7]_i_2_n_0\ ); \divider[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => divider(4), I1 => divider(2), I2 => divider(0), I3 => divider(1), I4 => divider(3), I5 => divider(5), O => \divider[7]_i_3_n_0\ ); \divider_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[0]_i_1_n_0\, Q => divider(0), R => '0' ); \divider_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[1]_i_1_n_0\, Q => divider(1), R => '0' ); \divider_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[2]_i_1_n_0\, Q => divider(2), R => '0' ); \divider_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[3]_i_1_n_0\, Q => divider(3), R => '0' ); \divider_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[4]_i_1_n_0\, Q => divider(4), R => '0' ); \divider_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[5]_i_1_n_0\, Q => divider(5), R => '0' ); \divider_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[6]_i_1_n_0\, Q => divider(6), R => '0' ); \divider_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \divider[7]_i_1_n_0\, D => \divider[7]_i_2_n_0\, Q => divider(7), R => '0' ); finished_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00000020" ) port map ( I0 => p_1_in, I1 => \address[5]_i_4_n_0\, I2 => divider(7), I3 => \address[5]_i_3_n_0\, I4 => p_0_in, I5 => finished_reg_n_0, O => finished_i_1_n_0 ); finished_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => '1', D => finished_i_1_n_0, Q => finished_reg_n_0, R => '0' ); hdmi_scl_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => clk_first_quarter(28), I1 => divider(7), O => hdmi_scl ); hdmi_sda_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \data_sr_reg_n_0_[28]\, I1 => \tristate_sr_reg[28]_inv_n_0\, O => hdmi_sda ); \initial_pause[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => p_1_in, I1 => p_0_in, I2 => \initial_pause_reg_n_0_[0]\, O => \p_1_in__0\(0) ); \initial_pause[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0110" ) port map ( I0 => p_0_in, I1 => p_1_in, I2 => \initial_pause_reg_n_0_[0]\, I3 => \initial_pause_reg_n_0_[1]\, O => \p_1_in__0\(1) ); \initial_pause[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00070008" ) port map ( I0 => \initial_pause_reg_n_0_[0]\, I1 => \initial_pause_reg_n_0_[1]\, I2 => p_1_in, I3 => p_0_in, I4 => \initial_pause_reg_n_0_[2]\, O => \p_1_in__0\(2) ); \initial_pause[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000007F00000080" ) port map ( I0 => \initial_pause_reg_n_0_[1]\, I1 => \initial_pause_reg_n_0_[0]\, I2 => \initial_pause_reg_n_0_[2]\, I3 => p_1_in, I4 => p_0_in, I5 => \initial_pause_reg_n_0_[3]\, O => \p_1_in__0\(3) ); \initial_pause[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFF000080000000" ) port map ( I0 => \initial_pause_reg_n_0_[2]\, I1 => \initial_pause_reg_n_0_[0]\, I2 => \initial_pause_reg_n_0_[1]\, I3 => \initial_pause_reg_n_0_[3]\, I4 => \initial_pause[7]_i_1_n_0\, I5 => \initial_pause_reg_n_0_[4]\, O => \p_1_in__0\(4) ); \initial_pause[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0201" ) port map ( I0 => \initial_pause[5]_i_2_n_0\, I1 => p_1_in, I2 => p_0_in, I3 => \initial_pause_reg_n_0_[5]\, O => \p_1_in__0\(5) ); \initial_pause[5]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => \initial_pause_reg_n_0_[3]\, I1 => \initial_pause_reg_n_0_[1]\, I2 => \initial_pause_reg_n_0_[0]\, I3 => \initial_pause_reg_n_0_[2]\, I4 => \initial_pause_reg_n_0_[4]\, O => \initial_pause[5]_i_2_n_0\ ); \initial_pause[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0201" ) port map ( I0 => \initial_pause[7]_i_3_n_0\, I1 => p_1_in, I2 => p_0_in, I3 => \initial_pause_reg_n_0_[6]\, O => \p_1_in__0\(6) ); \initial_pause[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => p_0_in, I1 => p_1_in, O => \initial_pause[7]_i_1_n_0\ ); \initial_pause[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \initial_pause_reg_n_0_[6]\, I1 => p_0_in, I2 => p_1_in, I3 => \initial_pause[7]_i_3_n_0\, O => \p_1_in__0\(7) ); \initial_pause[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \initial_pause_reg_n_0_[4]\, I1 => \initial_pause_reg_n_0_[2]\, I2 => \initial_pause_reg_n_0_[0]\, I3 => \initial_pause_reg_n_0_[1]\, I4 => \initial_pause_reg_n_0_[3]\, I5 => \initial_pause_reg_n_0_[5]\, O => \initial_pause[7]_i_3_n_0\ ); \initial_pause_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(0), Q => \initial_pause_reg_n_0_[0]\, R => '0' ); \initial_pause_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(1), Q => \initial_pause_reg_n_0_[1]\, R => '0' ); \initial_pause_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(2), Q => \initial_pause_reg_n_0_[2]\, R => '0' ); \initial_pause_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(3), Q => \initial_pause_reg_n_0_[3]\, R => '0' ); \initial_pause_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(4), Q => \initial_pause_reg_n_0_[4]\, R => '0' ); \initial_pause_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(5), Q => \initial_pause_reg_n_0_[5]\, R => '0' ); \initial_pause_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(6), Q => \initial_pause_reg_n_0_[6]\, R => '0' ); \initial_pause_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => \initial_pause[7]_i_1_n_0\, D => \p_1_in__0\(7), Q => p_1_in, R => '0' ); reg_value_reg: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"AF04D03C1700163748101506F9005512E0D0A3A4A2A49D619C309AE098034110", INIT_01 => X"2524241F23AD220421DC201D1F1B1E1C1D001C001BAD1A04193418E740004C04", INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFF2F772E1B2D7C2C082BAD2A042900280027352601", INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 18, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(13 downto 10) => B"0000", ADDRARDADDR(9 downto 4) => address(5 downto 0), ADDRARDADDR(3 downto 0) => B"0000", ADDRBWRADDR(13 downto 0) => B"11111111111111", CLKARDCLK => clk_100, CLKBWRCLK => '0', DIADI(15 downto 0) => B"1111111111111111", DIBDI(15 downto 0) => B"1111111111111111", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"11", DOADO(15 downto 8) => \p_0_in__0\(7 downto 0), DOADO(7) => reg_value_reg_n_8, DOADO(6) => reg_value_reg_n_9, DOADO(5) => reg_value_reg_n_10, DOADO(4) => reg_value_reg_n_11, DOADO(3) => reg_value_reg_n_12, DOADO(2) => reg_value_reg_n_13, DOADO(1) => reg_value_reg_n_14, DOADO(0) => reg_value_reg_n_15, DOBDO(15 downto 0) => NLW_reg_value_reg_DOBDO_UNCONNECTED(15 downto 0), DOPADOP(1 downto 0) => NLW_reg_value_reg_DOPADOP_UNCONNECTED(1 downto 0), DOPBDOP(1 downto 0) => NLW_reg_value_reg_DOPBDOP_UNCONNECTED(1 downto 0), ENARDEN => '1', ENBWREN => '0', REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1 downto 0) => B"00", WEBWE(3 downto 0) => B"0000" ); \tristate_sr[19]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => divider(6), I1 => \divider[7]_i_3_n_0\, I2 => divider(7), I3 => p_0_in, O => \tristate_sr[19]_i_1_n_0\ ); \tristate_sr_reg[10]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg_n_0_[9]\, Q => \tristate_sr_reg_n_0_[10]\, S => \address[5]_i_1_n_0\ ); \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '1', A1 => '0', A2 => '1', A3 => '0', CE => \tristate_sr[19]_i_1_n_0\, CLK => clk_100, D => \tristate_sr_reg_n_0_[10]\, Q => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ ); \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg[16]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\, Q => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, R => '0' ); \tristate_sr_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg_gate__0_n_0\, Q => \tristate_sr_reg_n_0_[18]\, R => \address[5]_i_1_n_0\ ); \tristate_sr_reg[19]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg_n_0_[18]\, Q => \tristate_sr_reg_n_0_[19]\, S => \address[5]_i_1_n_0\ ); \tristate_sr_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => '0', Q => \tristate_sr_reg_n_0_[1]\, S => \address[5]_i_1_n_0\ ); \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '1', A3 => '0', CE => \tristate_sr[19]_i_1_n_0\, CLK => clk_100, D => \tristate_sr_reg_n_0_[19]\, Q => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\ ); \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg[26]_srl7___U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, Q => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\, R => '0' ); \tristate_sr_reg[28]_inv\: unisim.vcomponents.FDSE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_gate_n_0, Q => \tristate_sr_reg[28]_inv_n_0\, S => \address[5]_i_1_n_0\ ); \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '1', A1 => '0', A2 => '1', A3 => '0', CE => \tristate_sr[19]_i_1_n_0\, CLK => clk_100, D => \tristate_sr_reg_n_0_[1]\, Q => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\ ); \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg[7]_srl6___U0_Inst_i2c_sender_tristate_sr_reg_r_4_n_0\, Q => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, R => '0' ); \tristate_sr_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => \tristate_sr_reg_gate__1_n_0\, Q => \tristate_sr_reg_n_0_[9]\, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_gate: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \tristate_sr_reg[27]_U0_Inst_i2c_sender_tristate_sr_reg_r_6_n_0\, I1 => tristate_sr_reg_r_6_n_0, O => tristate_sr_reg_gate_n_0 ); \tristate_sr_reg_gate__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \tristate_sr_reg[17]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, I1 => tristate_sr_reg_r_5_n_0, O => \tristate_sr_reg_gate__0_n_0\ ); \tristate_sr_reg_gate__1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \tristate_sr_reg[8]_U0_Inst_i2c_sender_tristate_sr_reg_r_5_n_0\, I1 => tristate_sr_reg_r_5_n_0, O => \tristate_sr_reg_gate__1_n_0\ ); tristate_sr_reg_r: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => '1', Q => tristate_sr_reg_r_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_0: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_n_0, Q => tristate_sr_reg_r_0_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_1: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_0_n_0, Q => tristate_sr_reg_r_1_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_2: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_1_n_0, Q => tristate_sr_reg_r_2_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_3: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_2_n_0, Q => tristate_sr_reg_r_3_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_4: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_3_n_0, Q => tristate_sr_reg_r_4_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_5: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_4_n_0, Q => tristate_sr_reg_r_5_n_0, R => \address[5]_i_1_n_0\ ); tristate_sr_reg_r_6: unisim.vcomponents.FDRE port map ( C => clk_100, CE => \tristate_sr[19]_i_1_n_0\, D => tristate_sr_reg_r_5_n_0, Q => tristate_sr_reg_r_6_n_0, R => \address[5]_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_zed_hdmi_0_0_zed_hdmi is port ( hdmi_clk : out STD_LOGIC; hdmi_hsync : out STD_LOGIC; hdmi_vsync : out STD_LOGIC; hdmi_de : out STD_LOGIC; DI : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[31]_0\ : out STD_LOGIC; \cr_int_reg[31]_1\ : out STD_LOGIC; O : out STD_LOGIC_VECTOR ( 1 downto 0 ); \cb_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[27]_0\ : out STD_LOGIC; \cr_int_reg[27]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); CO : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[31]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \cr_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \cr_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \cr_int_reg[27]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cr_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \y_int_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[23]_1\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \y_int_reg[23]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \y_int_reg[19]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \y_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \cb_int_reg[3]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cb_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cb_int_reg[3]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cb_int_reg[27]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cb_int_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \cr_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[3]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[19]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[23]_3\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \y_int_reg[15]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); hdmi_sda : out STD_LOGIC; hdmi_d : out STD_LOGIC_VECTOR ( 7 downto 0 ); hdmi_scl : out STD_LOGIC; clk_x2 : in STD_LOGIC; active : in STD_LOGIC; clk_100 : in STD_LOGIC; rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 ); \rgb888[8]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[13]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[12]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[12]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_6\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_8\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_9\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_10\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[0]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[0]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_11\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_12\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_13\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_5\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[0]_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_14\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_15\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_16\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_17\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_18\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_19\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \rgb888[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_20\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_21\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \rgb888[0]_7\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[1]\ : in STD_LOGIC_VECTOR ( 13 downto 0 ); \rgb888[14]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_22\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_23\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_24\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_25\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_26\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_27\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_28\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_29\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rgb888[8]_30\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \rgb888[8]_31\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \rgb888[0]_8\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[8]_32\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rgb888[0]_9\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); hsync : in STD_LOGIC; vsync : in STD_LOGIC; clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_zed_hdmi_0_0_zed_hdmi : entity is "zed_hdmi"; end system_zed_hdmi_0_0_zed_hdmi; architecture STRUCTURE of system_zed_hdmi_0_0_zed_hdmi is signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal D1 : STD_LOGIC; signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^o\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal cb : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \cb[0]_i_1_n_0\ : STD_LOGIC; signal \cb[1]_i_1_n_0\ : STD_LOGIC; signal \cb[2]_i_1_n_0\ : STD_LOGIC; signal \cb[3]_i_1_n_0\ : STD_LOGIC; signal \cb[4]_i_1_n_0\ : STD_LOGIC; signal \cb[5]_i_1_n_0\ : STD_LOGIC; signal \cb[6]_i_1_n_0\ : STD_LOGIC; signal \cb[7]_i_10_n_0\ : STD_LOGIC; signal \cb[7]_i_11_n_0\ : STD_LOGIC; signal \cb[7]_i_13_n_0\ : STD_LOGIC; signal \cb[7]_i_14_n_0\ : STD_LOGIC; signal \cb[7]_i_15_n_0\ : STD_LOGIC; signal \cb[7]_i_16_n_0\ : STD_LOGIC; signal \cb[7]_i_17_n_0\ : STD_LOGIC; signal \cb[7]_i_18_n_0\ : STD_LOGIC; signal \cb[7]_i_19_n_0\ : STD_LOGIC; signal \cb[7]_i_20_n_0\ : STD_LOGIC; signal \cb[7]_i_21_n_0\ : STD_LOGIC; signal \cb[7]_i_22_n_0\ : STD_LOGIC; signal \cb[7]_i_23_n_0\ : STD_LOGIC; signal \cb[7]_i_24_n_0\ : STD_LOGIC; signal \cb[7]_i_25_n_0\ : STD_LOGIC; signal \cb[7]_i_26_n_0\ : STD_LOGIC; signal \cb[7]_i_27_n_0\ : STD_LOGIC; signal \cb[7]_i_28_n_0\ : STD_LOGIC; signal \cb[7]_i_2_n_0\ : STD_LOGIC; signal \cb[7]_i_4_n_0\ : STD_LOGIC; signal \cb[7]_i_5_n_0\ : STD_LOGIC; signal \cb[7]_i_6_n_0\ : STD_LOGIC; signal \cb[7]_i_7_n_0\ : STD_LOGIC; signal \cb[7]_i_8_n_0\ : STD_LOGIC; signal \cb[7]_i_9_n_0\ : STD_LOGIC; signal cb_hold : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \cb_hold[7]_i_1_n_0\ : STD_LOGIC; signal \cb_int[11]_i_100_n_0\ : STD_LOGIC; signal \cb_int[11]_i_101_n_0\ : STD_LOGIC; signal \cb_int[11]_i_102_n_0\ : STD_LOGIC; signal \cb_int[11]_i_103_n_0\ : STD_LOGIC; signal \cb_int[11]_i_104_n_0\ : STD_LOGIC; signal \cb_int[11]_i_105_n_0\ : STD_LOGIC; signal \cb_int[11]_i_106_n_0\ : STD_LOGIC; signal \cb_int[11]_i_107_n_0\ : STD_LOGIC; signal \cb_int[11]_i_108_n_0\ : STD_LOGIC; signal \cb_int[11]_i_109_n_0\ : STD_LOGIC; signal \cb_int[11]_i_10_n_0\ : STD_LOGIC; signal \cb_int[11]_i_110_n_0\ : STD_LOGIC; signal \cb_int[11]_i_111_n_0\ : STD_LOGIC; signal \cb_int[11]_i_112_n_0\ : STD_LOGIC; signal \cb_int[11]_i_113_n_0\ : STD_LOGIC; signal \cb_int[11]_i_114_n_0\ : STD_LOGIC; signal \cb_int[11]_i_11_n_0\ : STD_LOGIC; signal \cb_int[11]_i_12_n_0\ : STD_LOGIC; signal \cb_int[11]_i_13_n_0\ : STD_LOGIC; signal \cb_int[11]_i_14_n_0\ : STD_LOGIC; signal \cb_int[11]_i_15_n_0\ : STD_LOGIC; signal \cb_int[11]_i_19_n_0\ : STD_LOGIC; signal \cb_int[11]_i_20_n_0\ : STD_LOGIC; signal \cb_int[11]_i_22_n_0\ : STD_LOGIC; signal \cb_int[11]_i_27_n_0\ : STD_LOGIC; signal \cb_int[11]_i_29_n_0\ : STD_LOGIC; signal \cb_int[11]_i_2_n_0\ : STD_LOGIC; signal \cb_int[11]_i_30_n_0\ : STD_LOGIC; signal \cb_int[11]_i_31_n_0\ : STD_LOGIC; signal \cb_int[11]_i_32_n_0\ : STD_LOGIC; signal \cb_int[11]_i_34_n_0\ : STD_LOGIC; signal \cb_int[11]_i_35_n_0\ : STD_LOGIC; signal \cb_int[11]_i_36_n_0\ : STD_LOGIC; signal \cb_int[11]_i_37_n_0\ : STD_LOGIC; signal \cb_int[11]_i_39_n_0\ : STD_LOGIC; signal \cb_int[11]_i_3_n_0\ : STD_LOGIC; signal \cb_int[11]_i_40_n_0\ : STD_LOGIC; signal \cb_int[11]_i_41_n_0\ : STD_LOGIC; signal \cb_int[11]_i_42_n_0\ : STD_LOGIC; signal \cb_int[11]_i_43_n_0\ : STD_LOGIC; signal \cb_int[11]_i_44_n_0\ : STD_LOGIC; signal \cb_int[11]_i_45_n_0\ : STD_LOGIC; signal \cb_int[11]_i_46_n_0\ : STD_LOGIC; signal \cb_int[11]_i_47_n_0\ : STD_LOGIC; signal \cb_int[11]_i_49_n_0\ : STD_LOGIC; signal \cb_int[11]_i_4_n_0\ : STD_LOGIC; signal \cb_int[11]_i_50_n_0\ : STD_LOGIC; signal \cb_int[11]_i_51_n_0\ : STD_LOGIC; signal \cb_int[11]_i_52_n_0\ : STD_LOGIC; signal \cb_int[11]_i_53_n_0\ : STD_LOGIC; signal \cb_int[11]_i_54_n_0\ : STD_LOGIC; signal \cb_int[11]_i_55_n_0\ : STD_LOGIC; signal \cb_int[11]_i_56_n_0\ : STD_LOGIC; signal \cb_int[11]_i_57_n_0\ : STD_LOGIC; signal \cb_int[11]_i_58_n_0\ : STD_LOGIC; signal \cb_int[11]_i_59_n_0\ : STD_LOGIC; signal \cb_int[11]_i_5_n_0\ : STD_LOGIC; signal \cb_int[11]_i_60_n_0\ : STD_LOGIC; signal \cb_int[11]_i_61_n_0\ : STD_LOGIC; signal \cb_int[11]_i_62_n_0\ : STD_LOGIC; signal \cb_int[11]_i_63_n_0\ : STD_LOGIC; signal \cb_int[11]_i_64_n_0\ : STD_LOGIC; signal \cb_int[11]_i_65_n_0\ : STD_LOGIC; signal \cb_int[11]_i_67_n_0\ : STD_LOGIC; signal \cb_int[11]_i_68_n_0\ : STD_LOGIC; signal \cb_int[11]_i_69_n_0\ : STD_LOGIC; signal \cb_int[11]_i_6_n_0\ : STD_LOGIC; signal \cb_int[11]_i_70_n_0\ : STD_LOGIC; signal \cb_int[11]_i_71_n_0\ : STD_LOGIC; signal \cb_int[11]_i_72_n_0\ : STD_LOGIC; signal \cb_int[11]_i_73_n_0\ : STD_LOGIC; signal \cb_int[11]_i_74_n_0\ : STD_LOGIC; signal \cb_int[11]_i_76_n_0\ : STD_LOGIC; signal \cb_int[11]_i_77_n_0\ : STD_LOGIC; signal \cb_int[11]_i_78_n_0\ : STD_LOGIC; signal \cb_int[11]_i_79_n_0\ : STD_LOGIC; signal \cb_int[11]_i_7_n_0\ : STD_LOGIC; signal \cb_int[11]_i_80_n_0\ : STD_LOGIC; signal \cb_int[11]_i_82_n_0\ : STD_LOGIC; signal \cb_int[11]_i_83_n_0\ : STD_LOGIC; signal \cb_int[11]_i_84_n_0\ : STD_LOGIC; signal \cb_int[11]_i_85_n_0\ : STD_LOGIC; signal \cb_int[11]_i_86_n_0\ : STD_LOGIC; signal \cb_int[11]_i_87_n_0\ : STD_LOGIC; signal \cb_int[11]_i_88_n_0\ : STD_LOGIC; signal \cb_int[11]_i_89_n_0\ : STD_LOGIC; signal \cb_int[11]_i_8_n_0\ : STD_LOGIC; signal \cb_int[11]_i_91_n_0\ : STD_LOGIC; signal \cb_int[11]_i_92_n_0\ : STD_LOGIC; signal \cb_int[11]_i_93_n_0\ : STD_LOGIC; signal \cb_int[11]_i_94_n_0\ : STD_LOGIC; signal \cb_int[11]_i_95_n_0\ : STD_LOGIC; signal \cb_int[11]_i_96_n_0\ : STD_LOGIC; signal \cb_int[11]_i_97_n_0\ : STD_LOGIC; signal \cb_int[11]_i_98_n_0\ : STD_LOGIC; signal \cb_int[11]_i_99_n_0\ : STD_LOGIC; signal \cb_int[11]_i_9_n_0\ : STD_LOGIC; signal \cb_int[15]_i_10_n_0\ : STD_LOGIC; signal \cb_int[15]_i_11_n_0\ : STD_LOGIC; signal \cb_int[15]_i_12_n_0\ : STD_LOGIC; signal \cb_int[15]_i_13_n_0\ : STD_LOGIC; signal \cb_int[15]_i_14_n_0\ : STD_LOGIC; signal \cb_int[15]_i_15_n_0\ : STD_LOGIC; signal \cb_int[15]_i_16_n_0\ : STD_LOGIC; signal \cb_int[15]_i_17_n_0\ : STD_LOGIC; signal \cb_int[15]_i_18_n_0\ : STD_LOGIC; signal \cb_int[15]_i_21_n_0\ : STD_LOGIC; signal \cb_int[15]_i_23_n_0\ : STD_LOGIC; signal \cb_int[15]_i_25_n_0\ : STD_LOGIC; signal \cb_int[15]_i_27_n_0\ : STD_LOGIC; signal \cb_int[15]_i_28_n_0\ : STD_LOGIC; signal \cb_int[15]_i_29_n_0\ : STD_LOGIC; signal \cb_int[15]_i_2_n_0\ : STD_LOGIC; signal \cb_int[15]_i_30_n_0\ : STD_LOGIC; signal \cb_int[15]_i_3_n_0\ : STD_LOGIC; signal \cb_int[15]_i_43_n_0\ : STD_LOGIC; signal \cb_int[15]_i_44_n_0\ : STD_LOGIC; signal \cb_int[15]_i_45_n_0\ : STD_LOGIC; signal \cb_int[15]_i_46_n_0\ : STD_LOGIC; signal \cb_int[15]_i_4_n_0\ : STD_LOGIC; signal \cb_int[15]_i_5_n_0\ : STD_LOGIC; signal \cb_int[15]_i_6_n_0\ : STD_LOGIC; signal \cb_int[15]_i_7_n_0\ : STD_LOGIC; signal \cb_int[15]_i_8_n_0\ : STD_LOGIC; signal \cb_int[15]_i_9_n_0\ : STD_LOGIC; signal \cb_int[19]_i_10_n_0\ : STD_LOGIC; signal \cb_int[19]_i_11_n_0\ : STD_LOGIC; signal \cb_int[19]_i_12_n_0\ : STD_LOGIC; signal \cb_int[19]_i_13_n_0\ : STD_LOGIC; signal \cb_int[19]_i_14_n_0\ : STD_LOGIC; signal \cb_int[19]_i_15_n_0\ : STD_LOGIC; signal \cb_int[19]_i_16_n_0\ : STD_LOGIC; signal \cb_int[19]_i_17_n_0\ : STD_LOGIC; signal \cb_int[19]_i_18_n_0\ : STD_LOGIC; signal \cb_int[19]_i_21_n_0\ : STD_LOGIC; signal \cb_int[19]_i_23_n_0\ : STD_LOGIC; signal \cb_int[19]_i_26_n_0\ : STD_LOGIC; signal \cb_int[19]_i_28_n_0\ : STD_LOGIC; signal \cb_int[19]_i_29_n_0\ : STD_LOGIC; signal \cb_int[19]_i_2_n_0\ : STD_LOGIC; signal \cb_int[19]_i_30_n_0\ : STD_LOGIC; signal \cb_int[19]_i_31_n_0\ : STD_LOGIC; signal \cb_int[19]_i_34_n_0\ : STD_LOGIC; signal \cb_int[19]_i_35_n_0\ : STD_LOGIC; signal \cb_int[19]_i_36_n_0\ : STD_LOGIC; signal \cb_int[19]_i_37_n_0\ : STD_LOGIC; signal \cb_int[19]_i_3_n_0\ : STD_LOGIC; signal \cb_int[19]_i_4_n_0\ : STD_LOGIC; signal \cb_int[19]_i_5_n_0\ : STD_LOGIC; signal \cb_int[19]_i_6_n_0\ : STD_LOGIC; signal \cb_int[19]_i_7_n_0\ : STD_LOGIC; signal \cb_int[19]_i_8_n_0\ : STD_LOGIC; signal \cb_int[19]_i_9_n_0\ : STD_LOGIC; signal \cb_int[23]_i_10_n_0\ : STD_LOGIC; signal \cb_int[23]_i_11_n_0\ : STD_LOGIC; signal \cb_int[23]_i_12_n_0\ : STD_LOGIC; signal \cb_int[23]_i_13_n_0\ : STD_LOGIC; signal \cb_int[23]_i_14_n_0\ : STD_LOGIC; signal \cb_int[23]_i_15_n_0\ : STD_LOGIC; signal \cb_int[23]_i_16_n_0\ : STD_LOGIC; signal \cb_int[23]_i_17_n_0\ : STD_LOGIC; signal \cb_int[23]_i_18_n_0\ : STD_LOGIC; signal \cb_int[23]_i_20_n_0\ : STD_LOGIC; signal \cb_int[23]_i_22_n_0\ : STD_LOGIC; signal \cb_int[23]_i_25_n_0\ : STD_LOGIC; signal \cb_int[23]_i_29_n_0\ : STD_LOGIC; signal \cb_int[23]_i_2_n_0\ : STD_LOGIC; signal \cb_int[23]_i_30_n_0\ : STD_LOGIC; signal \cb_int[23]_i_31_n_0\ : STD_LOGIC; signal \cb_int[23]_i_32_n_0\ : STD_LOGIC; signal \cb_int[23]_i_3_n_0\ : STD_LOGIC; signal \cb_int[23]_i_4_n_0\ : STD_LOGIC; signal \cb_int[23]_i_5_n_0\ : STD_LOGIC; signal \cb_int[23]_i_6_n_0\ : STD_LOGIC; signal \cb_int[23]_i_7_n_0\ : STD_LOGIC; signal \cb_int[23]_i_8_n_0\ : STD_LOGIC; signal \cb_int[23]_i_9_n_0\ : STD_LOGIC; signal \cb_int[27]_i_10_n_0\ : STD_LOGIC; signal \cb_int[27]_i_12_n_0\ : STD_LOGIC; signal \cb_int[27]_i_13_n_0\ : STD_LOGIC; signal \cb_int[27]_i_14_n_0\ : STD_LOGIC; signal \cb_int[27]_i_15_n_0\ : STD_LOGIC; signal \cb_int[27]_i_2_n_0\ : STD_LOGIC; signal \cb_int[27]_i_3_n_0\ : STD_LOGIC; signal \cb_int[27]_i_4_n_0\ : STD_LOGIC; signal \cb_int[27]_i_5_n_0\ : STD_LOGIC; signal \cb_int[27]_i_6_n_0\ : STD_LOGIC; signal \cb_int[27]_i_7_n_0\ : STD_LOGIC; signal \cb_int[27]_i_8_n_0\ : STD_LOGIC; signal \cb_int[31]_i_13_n_0\ : STD_LOGIC; signal \cb_int[31]_i_15_n_0\ : STD_LOGIC; signal \cb_int[31]_i_16_n_0\ : STD_LOGIC; signal \cb_int[31]_i_2_n_0\ : STD_LOGIC; signal \cb_int[31]_i_31_n_0\ : STD_LOGIC; signal \cb_int[31]_i_32_n_0\ : STD_LOGIC; signal \cb_int[31]_i_35_n_0\ : STD_LOGIC; signal \cb_int[31]_i_36_n_0\ : STD_LOGIC; signal \cb_int[31]_i_38_n_0\ : STD_LOGIC; signal \cb_int[31]_i_39_n_0\ : STD_LOGIC; signal \cb_int[31]_i_3_n_0\ : STD_LOGIC; signal \cb_int[31]_i_40_n_0\ : STD_LOGIC; signal \cb_int[31]_i_41_n_0\ : STD_LOGIC; signal \cb_int[31]_i_4_n_0\ : STD_LOGIC; signal \cb_int[31]_i_5_n_0\ : STD_LOGIC; signal \cb_int[31]_i_67_n_0\ : STD_LOGIC; signal \cb_int[31]_i_68_n_0\ : STD_LOGIC; signal \cb_int[31]_i_69_n_0\ : STD_LOGIC; signal \cb_int[31]_i_6_n_0\ : STD_LOGIC; signal \cb_int[31]_i_70_n_0\ : STD_LOGIC; signal \cb_int[31]_i_71_n_0\ : STD_LOGIC; signal \cb_int[31]_i_72_n_0\ : STD_LOGIC; signal \cb_int[31]_i_74_n_0\ : STD_LOGIC; signal \cb_int[31]_i_75_n_0\ : STD_LOGIC; signal \cb_int[31]_i_76_n_0\ : STD_LOGIC; signal \cb_int[31]_i_77_n_0\ : STD_LOGIC; signal \cb_int[31]_i_78_n_0\ : STD_LOGIC; signal \cb_int[31]_i_79_n_0\ : STD_LOGIC; signal \cb_int[31]_i_80_n_0\ : STD_LOGIC; signal \cb_int[31]_i_81_n_0\ : STD_LOGIC; signal \cb_int[31]_i_82_n_0\ : STD_LOGIC; signal \cb_int[31]_i_95_n_0\ : STD_LOGIC; signal \cb_int[31]_i_96_n_0\ : STD_LOGIC; signal \cb_int[31]_i_97_n_0\ : STD_LOGIC; signal \cb_int[31]_i_98_n_0\ : STD_LOGIC; signal \cb_int[3]_i_100_n_0\ : STD_LOGIC; signal \cb_int[3]_i_101_n_0\ : STD_LOGIC; signal \cb_int[3]_i_102_n_0\ : STD_LOGIC; signal \cb_int[3]_i_103_n_0\ : STD_LOGIC; signal \cb_int[3]_i_104_n_0\ : STD_LOGIC; signal \cb_int[3]_i_105_n_0\ : STD_LOGIC; signal \cb_int[3]_i_106_n_0\ : STD_LOGIC; signal \cb_int[3]_i_10_n_0\ : STD_LOGIC; signal \cb_int[3]_i_12_n_0\ : STD_LOGIC; signal \cb_int[3]_i_13_n_0\ : STD_LOGIC; signal \cb_int[3]_i_17_n_0\ : STD_LOGIC; signal \cb_int[3]_i_18_n_0\ : STD_LOGIC; signal \cb_int[3]_i_22_n_0\ : STD_LOGIC; signal \cb_int[3]_i_23_n_0\ : STD_LOGIC; signal \cb_int[3]_i_24_n_0\ : STD_LOGIC; signal \cb_int[3]_i_25_n_0\ : STD_LOGIC; signal \cb_int[3]_i_27_n_0\ : STD_LOGIC; signal \cb_int[3]_i_28_n_0\ : STD_LOGIC; signal \cb_int[3]_i_29_n_0\ : STD_LOGIC; signal \cb_int[3]_i_2_n_0\ : STD_LOGIC; signal \cb_int[3]_i_30_n_0\ : STD_LOGIC; signal \cb_int[3]_i_31_n_0\ : STD_LOGIC; signal \cb_int[3]_i_3_n_0\ : STD_LOGIC; signal \cb_int[3]_i_45_n_0\ : STD_LOGIC; signal \cb_int[3]_i_46_n_0\ : STD_LOGIC; signal \cb_int[3]_i_47_n_0\ : STD_LOGIC; signal \cb_int[3]_i_48_n_0\ : STD_LOGIC; signal \cb_int[3]_i_49_n_0\ : STD_LOGIC; signal \cb_int[3]_i_4_n_0\ : STD_LOGIC; signal \cb_int[3]_i_50_n_0\ : STD_LOGIC; signal \cb_int[3]_i_51_n_0\ : STD_LOGIC; signal \cb_int[3]_i_52_n_0\ : STD_LOGIC; signal \cb_int[3]_i_53_n_0\ : STD_LOGIC; signal \cb_int[3]_i_54_n_0\ : STD_LOGIC; signal \cb_int[3]_i_55_n_0\ : STD_LOGIC; signal \cb_int[3]_i_56_n_0\ : STD_LOGIC; signal \cb_int[3]_i_5_n_0\ : STD_LOGIC; signal \cb_int[3]_i_64_n_0\ : STD_LOGIC; signal \cb_int[3]_i_65_n_0\ : STD_LOGIC; signal \cb_int[3]_i_66_n_0\ : STD_LOGIC; signal \cb_int[3]_i_67_n_0\ : STD_LOGIC; signal \cb_int[3]_i_69_n_0\ : STD_LOGIC; signal \cb_int[3]_i_6_n_0\ : STD_LOGIC; signal \cb_int[3]_i_70_n_0\ : STD_LOGIC; signal \cb_int[3]_i_71_n_0\ : STD_LOGIC; signal \cb_int[3]_i_72_n_0\ : STD_LOGIC; signal \cb_int[3]_i_76_n_0\ : STD_LOGIC; signal \cb_int[3]_i_77_n_0\ : STD_LOGIC; signal \cb_int[3]_i_78_n_0\ : STD_LOGIC; signal \cb_int[3]_i_79_n_0\ : STD_LOGIC; signal \cb_int[3]_i_7_n_0\ : STD_LOGIC; signal \cb_int[3]_i_80_n_0\ : STD_LOGIC; signal \cb_int[3]_i_81_n_0\ : STD_LOGIC; signal \cb_int[3]_i_82_n_0\ : STD_LOGIC; signal \cb_int[3]_i_83_n_0\ : STD_LOGIC; signal \cb_int[3]_i_89_n_0\ : STD_LOGIC; signal \cb_int[3]_i_8_n_0\ : STD_LOGIC; signal \cb_int[3]_i_90_n_0\ : STD_LOGIC; signal \cb_int[3]_i_91_n_0\ : STD_LOGIC; signal \cb_int[3]_i_92_n_0\ : STD_LOGIC; signal \cb_int[3]_i_93_n_0\ : STD_LOGIC; signal \cb_int[3]_i_99_n_0\ : STD_LOGIC; signal \cb_int[3]_i_9_n_0\ : STD_LOGIC; signal \cb_int[7]_i_10_n_0\ : STD_LOGIC; signal \cb_int[7]_i_11_n_0\ : STD_LOGIC; signal \cb_int[7]_i_13_n_0\ : STD_LOGIC; signal \cb_int[7]_i_14_n_0\ : STD_LOGIC; signal \cb_int[7]_i_16_n_0\ : STD_LOGIC; signal \cb_int[7]_i_17_n_0\ : STD_LOGIC; signal \cb_int[7]_i_19_n_0\ : STD_LOGIC; signal \cb_int[7]_i_21_n_0\ : STD_LOGIC; signal \cb_int[7]_i_22_n_0\ : STD_LOGIC; signal \cb_int[7]_i_2_n_0\ : STD_LOGIC; signal \cb_int[7]_i_39_n_0\ : STD_LOGIC; signal \cb_int[7]_i_3_n_0\ : STD_LOGIC; signal \cb_int[7]_i_40_n_0\ : STD_LOGIC; signal \cb_int[7]_i_41_n_0\ : STD_LOGIC; signal \cb_int[7]_i_42_n_0\ : STD_LOGIC; signal \cb_int[7]_i_4_n_0\ : STD_LOGIC; signal \cb_int[7]_i_52_n_0\ : STD_LOGIC; signal \cb_int[7]_i_53_n_0\ : STD_LOGIC; signal \cb_int[7]_i_54_n_0\ : STD_LOGIC; signal \cb_int[7]_i_55_n_0\ : STD_LOGIC; signal \cb_int[7]_i_56_n_0\ : STD_LOGIC; signal \cb_int[7]_i_57_n_0\ : STD_LOGIC; signal \cb_int[7]_i_58_n_0\ : STD_LOGIC; signal \cb_int[7]_i_59_n_0\ : STD_LOGIC; signal \cb_int[7]_i_5_n_0\ : STD_LOGIC; signal \cb_int[7]_i_60_n_0\ : STD_LOGIC; signal \cb_int[7]_i_62_n_0\ : STD_LOGIC; signal \cb_int[7]_i_63_n_0\ : STD_LOGIC; signal \cb_int[7]_i_64_n_0\ : STD_LOGIC; signal \cb_int[7]_i_65_n_0\ : STD_LOGIC; signal \cb_int[7]_i_67_n_0\ : STD_LOGIC; signal \cb_int[7]_i_68_n_0\ : STD_LOGIC; signal \cb_int[7]_i_69_n_0\ : STD_LOGIC; signal \cb_int[7]_i_6_n_0\ : STD_LOGIC; signal \cb_int[7]_i_70_n_0\ : STD_LOGIC; signal \cb_int[7]_i_71_n_0\ : STD_LOGIC; signal \cb_int[7]_i_72_n_0\ : STD_LOGIC; signal \cb_int[7]_i_73_n_0\ : STD_LOGIC; signal \cb_int[7]_i_74_n_0\ : STD_LOGIC; signal \cb_int[7]_i_75_n_0\ : STD_LOGIC; signal \cb_int[7]_i_76_n_0\ : STD_LOGIC; signal \cb_int[7]_i_77_n_0\ : STD_LOGIC; signal \cb_int[7]_i_78_n_0\ : STD_LOGIC; signal \cb_int[7]_i_79_n_0\ : STD_LOGIC; signal \cb_int[7]_i_7_n_0\ : STD_LOGIC; signal \cb_int[7]_i_80_n_0\ : STD_LOGIC; signal \cb_int[7]_i_81_n_0\ : STD_LOGIC; signal \cb_int[7]_i_82_n_0\ : STD_LOGIC; signal \cb_int[7]_i_8_n_0\ : STD_LOGIC; signal \cb_int[7]_i_9_n_0\ : STD_LOGIC; signal cb_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal cb_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal cb_int_reg5 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal cb_int_reg7 : STD_LOGIC_VECTOR ( 30 downto 8 ); signal cb_int_reg8 : STD_LOGIC; signal \cb_int_reg[11]_i_16_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_16_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_16_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_16_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_17_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_17_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_17_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_17_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_18_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_18_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[11]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_4\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_5\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_6\ : STD_LOGIC; signal \cb_int_reg[11]_i_24_n_7\ : STD_LOGIC; signal \cb_int_reg[11]_i_25_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_25_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_25_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_25_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_26_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_26_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_26_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_26_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_28_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_28_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_28_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_28_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_38_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_38_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_38_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_38_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_48_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_48_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_48_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_48_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_66_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_66_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_66_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_66_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_75_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_75_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_75_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_75_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_81_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_81_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_81_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_81_n_3\ : STD_LOGIC; signal \cb_int_reg[11]_i_90_n_0\ : STD_LOGIC; signal \cb_int_reg[11]_i_90_n_1\ : STD_LOGIC; signal \cb_int_reg[11]_i_90_n_2\ : STD_LOGIC; signal \cb_int_reg[11]_i_90_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[15]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[15]_i_20_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_20_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_20_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_20_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[19]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[19]_i_20_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_20_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_20_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_20_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_25_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_25_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_25_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_25_n_3\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[23]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[23]_i_24_n_0\ : STD_LOGIC; signal \cb_int_reg[23]_i_24_n_1\ : STD_LOGIC; signal \cb_int_reg[23]_i_24_n_2\ : STD_LOGIC; signal \cb_int_reg[23]_i_24_n_3\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[27]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[27]_i_9_n_1\ : STD_LOGIC; signal \cb_int_reg[27]_i_9_n_2\ : STD_LOGIC; signal \cb_int_reg[27]_i_9_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_11_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_11_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_12_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_12_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_12_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_12_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_14_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_14_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_14_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_14_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_30_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_30_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_30_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_30_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_33_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_34_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_34_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_37_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_37_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_37_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_37_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_73_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_7_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_7_n_3\ : STD_LOGIC; signal \^cb_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cb_int_reg[3]_i_15_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_15_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_15_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_15_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_16_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_20_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_21_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_21_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_21_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_21_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_26_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_33_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_34_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_34_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_34_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_44_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_57_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_63_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_63_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_63_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_63_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_75_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_94_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_1_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_25_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_25_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_25_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_28_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_28_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_28_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_28_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_29_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_38_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_38_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_38_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_38_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_61_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_61_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_61_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_61_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_66_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_66_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_66_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_66_n_3\ : STD_LOGIC; signal \cb_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \cb_int_reg_n_0_[0]\ : STD_LOGIC; signal \cb_int_reg_n_0_[1]\ : STD_LOGIC; signal \cb_int_reg_n_0_[2]\ : STD_LOGIC; signal \cb_int_reg_n_0_[3]\ : STD_LOGIC; signal \cb_int_reg_n_0_[4]\ : STD_LOGIC; signal \cb_int_reg_n_0_[5]\ : STD_LOGIC; signal \cb_int_reg_n_0_[6]\ : STD_LOGIC; signal \cb_int_reg_n_0_[7]\ : STD_LOGIC; signal \cb_reg[7]_i_12_n_0\ : STD_LOGIC; signal \cb_reg[7]_i_12_n_1\ : STD_LOGIC; signal \cb_reg[7]_i_12_n_2\ : STD_LOGIC; signal \cb_reg[7]_i_12_n_3\ : STD_LOGIC; signal \cb_reg[7]_i_1_n_0\ : STD_LOGIC; signal \cb_reg[7]_i_1_n_1\ : STD_LOGIC; signal \cb_reg[7]_i_1_n_2\ : STD_LOGIC; signal \cb_reg[7]_i_1_n_3\ : STD_LOGIC; signal \cb_reg[7]_i_3_n_0\ : STD_LOGIC; signal \cb_reg[7]_i_3_n_1\ : STD_LOGIC; signal \cb_reg[7]_i_3_n_2\ : STD_LOGIC; signal \cb_reg[7]_i_3_n_3\ : STD_LOGIC; signal cb_regn_0_0 : STD_LOGIC; signal cr : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \cr[0]_i_1_n_0\ : STD_LOGIC; signal \cr[1]_i_1_n_0\ : STD_LOGIC; signal \cr[2]_i_1_n_0\ : STD_LOGIC; signal \cr[3]_i_1_n_0\ : STD_LOGIC; signal \cr[4]_i_1_n_0\ : STD_LOGIC; signal \cr[5]_i_1_n_0\ : STD_LOGIC; signal \cr[6]_i_1_n_0\ : STD_LOGIC; signal \cr[7]_i_10_n_0\ : STD_LOGIC; signal \cr[7]_i_11_n_0\ : STD_LOGIC; signal \cr[7]_i_13_n_0\ : STD_LOGIC; signal \cr[7]_i_14_n_0\ : STD_LOGIC; signal \cr[7]_i_15_n_0\ : STD_LOGIC; signal \cr[7]_i_16_n_0\ : STD_LOGIC; signal \cr[7]_i_17_n_0\ : STD_LOGIC; signal \cr[7]_i_18_n_0\ : STD_LOGIC; signal \cr[7]_i_19_n_0\ : STD_LOGIC; signal \cr[7]_i_20_n_0\ : STD_LOGIC; signal \cr[7]_i_21_n_0\ : STD_LOGIC; signal \cr[7]_i_22_n_0\ : STD_LOGIC; signal \cr[7]_i_23_n_0\ : STD_LOGIC; signal \cr[7]_i_24_n_0\ : STD_LOGIC; signal \cr[7]_i_25_n_0\ : STD_LOGIC; signal \cr[7]_i_26_n_0\ : STD_LOGIC; signal \cr[7]_i_27_n_0\ : STD_LOGIC; signal \cr[7]_i_28_n_0\ : STD_LOGIC; signal \cr[7]_i_2_n_0\ : STD_LOGIC; signal \cr[7]_i_4_n_0\ : STD_LOGIC; signal \cr[7]_i_5_n_0\ : STD_LOGIC; signal \cr[7]_i_6_n_0\ : STD_LOGIC; signal \cr[7]_i_7_n_0\ : STD_LOGIC; signal \cr[7]_i_8_n_0\ : STD_LOGIC; signal \cr[7]_i_9_n_0\ : STD_LOGIC; signal \cr_hold_reg_n_0_[0]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[1]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[2]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[3]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[4]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[5]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[6]\ : STD_LOGIC; signal \cr_hold_reg_n_0_[7]\ : STD_LOGIC; signal \cr_int[11]_i_100_n_0\ : STD_LOGIC; signal \cr_int[11]_i_101_n_0\ : STD_LOGIC; signal \cr_int[11]_i_102_n_0\ : STD_LOGIC; signal \cr_int[11]_i_104_n_0\ : STD_LOGIC; signal \cr_int[11]_i_105_n_0\ : STD_LOGIC; signal \cr_int[11]_i_106_n_0\ : STD_LOGIC; signal \cr_int[11]_i_107_n_0\ : STD_LOGIC; signal \cr_int[11]_i_109_n_0\ : STD_LOGIC; signal \cr_int[11]_i_10_n_0\ : STD_LOGIC; signal \cr_int[11]_i_110_n_0\ : STD_LOGIC; signal \cr_int[11]_i_111_n_0\ : STD_LOGIC; signal \cr_int[11]_i_112_n_0\ : STD_LOGIC; signal \cr_int[11]_i_113_n_0\ : STD_LOGIC; signal \cr_int[11]_i_114_n_0\ : STD_LOGIC; signal \cr_int[11]_i_115_n_0\ : STD_LOGIC; signal \cr_int[11]_i_117_n_0\ : STD_LOGIC; signal \cr_int[11]_i_118_n_0\ : STD_LOGIC; signal \cr_int[11]_i_119_n_0\ : STD_LOGIC; signal \cr_int[11]_i_11_n_0\ : STD_LOGIC; signal \cr_int[11]_i_120_n_0\ : STD_LOGIC; signal \cr_int[11]_i_121_n_0\ : STD_LOGIC; signal \cr_int[11]_i_122_n_0\ : STD_LOGIC; signal \cr_int[11]_i_123_n_0\ : STD_LOGIC; signal \cr_int[11]_i_124_n_0\ : STD_LOGIC; signal \cr_int[11]_i_126_n_0\ : STD_LOGIC; signal \cr_int[11]_i_127_n_0\ : STD_LOGIC; signal \cr_int[11]_i_128_n_0\ : STD_LOGIC; signal \cr_int[11]_i_129_n_0\ : STD_LOGIC; signal \cr_int[11]_i_12_n_0\ : STD_LOGIC; signal \cr_int[11]_i_130_n_0\ : STD_LOGIC; signal \cr_int[11]_i_131_n_0\ : STD_LOGIC; signal \cr_int[11]_i_132_n_0\ : STD_LOGIC; signal \cr_int[11]_i_133_n_0\ : STD_LOGIC; signal \cr_int[11]_i_134_n_0\ : STD_LOGIC; signal \cr_int[11]_i_135_n_0\ : STD_LOGIC; signal \cr_int[11]_i_136_n_0\ : STD_LOGIC; signal \cr_int[11]_i_137_n_0\ : STD_LOGIC; signal \cr_int[11]_i_138_n_0\ : STD_LOGIC; signal \cr_int[11]_i_139_n_0\ : STD_LOGIC; signal \cr_int[11]_i_13_n_0\ : STD_LOGIC; signal \cr_int[11]_i_140_n_0\ : STD_LOGIC; signal \cr_int[11]_i_141_n_0\ : STD_LOGIC; signal \cr_int[11]_i_142_n_0\ : STD_LOGIC; signal \cr_int[11]_i_143_n_0\ : STD_LOGIC; signal \cr_int[11]_i_144_n_0\ : STD_LOGIC; signal \cr_int[11]_i_145_n_0\ : STD_LOGIC; signal \cr_int[11]_i_146_n_0\ : STD_LOGIC; signal \cr_int[11]_i_147_n_0\ : STD_LOGIC; signal \cr_int[11]_i_148_n_0\ : STD_LOGIC; signal \cr_int[11]_i_149_n_0\ : STD_LOGIC; signal \cr_int[11]_i_14_n_0\ : STD_LOGIC; signal \cr_int[11]_i_150_n_0\ : STD_LOGIC; signal \cr_int[11]_i_151_n_0\ : STD_LOGIC; signal \cr_int[11]_i_152_n_0\ : STD_LOGIC; signal \cr_int[11]_i_153_n_0\ : STD_LOGIC; signal \cr_int[11]_i_154_n_0\ : STD_LOGIC; signal \cr_int[11]_i_155_n_0\ : STD_LOGIC; signal \cr_int[11]_i_156_n_0\ : STD_LOGIC; signal \cr_int[11]_i_15_n_0\ : STD_LOGIC; signal \cr_int[11]_i_22_n_0\ : STD_LOGIC; signal \cr_int[11]_i_23_n_0\ : STD_LOGIC; signal \cr_int[11]_i_24_n_0\ : STD_LOGIC; signal \cr_int[11]_i_25_n_0\ : STD_LOGIC; signal \cr_int[11]_i_27_n_0\ : STD_LOGIC; signal \cr_int[11]_i_2_n_0\ : STD_LOGIC; signal \cr_int[11]_i_32_n_0\ : STD_LOGIC; signal \cr_int[11]_i_33_n_0\ : STD_LOGIC; signal \cr_int[11]_i_34_n_0\ : STD_LOGIC; signal \cr_int[11]_i_35_n_0\ : STD_LOGIC; signal \cr_int[11]_i_37_n_0\ : STD_LOGIC; signal \cr_int[11]_i_38_n_0\ : STD_LOGIC; signal \cr_int[11]_i_39_n_0\ : STD_LOGIC; signal \cr_int[11]_i_3_n_0\ : STD_LOGIC; signal \cr_int[11]_i_40_n_0\ : STD_LOGIC; signal \cr_int[11]_i_42_n_0\ : STD_LOGIC; signal \cr_int[11]_i_43_n_0\ : STD_LOGIC; signal \cr_int[11]_i_44_n_0\ : STD_LOGIC; signal \cr_int[11]_i_45_n_0\ : STD_LOGIC; signal \cr_int[11]_i_47_n_0\ : STD_LOGIC; signal \cr_int[11]_i_48_n_0\ : STD_LOGIC; signal \cr_int[11]_i_49_n_0\ : STD_LOGIC; signal \cr_int[11]_i_4_n_0\ : STD_LOGIC; signal \cr_int[11]_i_50_n_0\ : STD_LOGIC; signal \cr_int[11]_i_52_n_0\ : STD_LOGIC; signal \cr_int[11]_i_53_n_0\ : STD_LOGIC; signal \cr_int[11]_i_54_n_0\ : STD_LOGIC; signal \cr_int[11]_i_55_n_0\ : STD_LOGIC; signal \cr_int[11]_i_57_n_0\ : STD_LOGIC; signal \cr_int[11]_i_58_n_0\ : STD_LOGIC; signal \cr_int[11]_i_59_n_0\ : STD_LOGIC; signal \cr_int[11]_i_5_n_0\ : STD_LOGIC; signal \cr_int[11]_i_60_n_0\ : STD_LOGIC; signal \cr_int[11]_i_65_n_0\ : STD_LOGIC; signal \cr_int[11]_i_66_n_0\ : STD_LOGIC; signal \cr_int[11]_i_67_n_0\ : STD_LOGIC; signal \cr_int[11]_i_68_n_0\ : STD_LOGIC; signal \cr_int[11]_i_6_n_0\ : STD_LOGIC; signal \cr_int[11]_i_70_n_0\ : STD_LOGIC; signal \cr_int[11]_i_71_n_0\ : STD_LOGIC; signal \cr_int[11]_i_72_n_0\ : STD_LOGIC; signal \cr_int[11]_i_73_n_0\ : STD_LOGIC; signal \cr_int[11]_i_74_n_0\ : STD_LOGIC; signal \cr_int[11]_i_75_n_0\ : STD_LOGIC; signal \cr_int[11]_i_76_n_0\ : STD_LOGIC; signal \cr_int[11]_i_77_n_0\ : STD_LOGIC; signal \cr_int[11]_i_78_n_0\ : STD_LOGIC; signal \cr_int[11]_i_7_n_0\ : STD_LOGIC; signal \cr_int[11]_i_80_n_0\ : STD_LOGIC; signal \cr_int[11]_i_81_n_0\ : STD_LOGIC; signal \cr_int[11]_i_82_n_0\ : STD_LOGIC; signal \cr_int[11]_i_83_n_0\ : STD_LOGIC; signal \cr_int[11]_i_84_n_0\ : STD_LOGIC; signal \cr_int[11]_i_85_n_0\ : STD_LOGIC; signal \cr_int[11]_i_86_n_0\ : STD_LOGIC; signal \cr_int[11]_i_87_n_0\ : STD_LOGIC; signal \cr_int[11]_i_88_n_0\ : STD_LOGIC; signal \cr_int[11]_i_89_n_0\ : STD_LOGIC; signal \cr_int[11]_i_8_n_0\ : STD_LOGIC; signal \cr_int[11]_i_90_n_0\ : STD_LOGIC; signal \cr_int[11]_i_91_n_0\ : STD_LOGIC; signal \cr_int[11]_i_93_n_0\ : STD_LOGIC; signal \cr_int[11]_i_94_n_0\ : STD_LOGIC; signal \cr_int[11]_i_95_n_0\ : STD_LOGIC; signal \cr_int[11]_i_96_n_0\ : STD_LOGIC; signal \cr_int[11]_i_97_n_0\ : STD_LOGIC; signal \cr_int[11]_i_98_n_0\ : STD_LOGIC; signal \cr_int[11]_i_99_n_0\ : STD_LOGIC; signal \cr_int[11]_i_9_n_0\ : STD_LOGIC; signal \cr_int[15]_i_10_n_0\ : STD_LOGIC; signal \cr_int[15]_i_11_n_0\ : STD_LOGIC; signal \cr_int[15]_i_12_n_0\ : STD_LOGIC; signal \cr_int[15]_i_13_n_0\ : STD_LOGIC; signal \cr_int[15]_i_14_n_0\ : STD_LOGIC; signal \cr_int[15]_i_15_n_0\ : STD_LOGIC; signal \cr_int[15]_i_16_n_0\ : STD_LOGIC; signal \cr_int[15]_i_17_n_0\ : STD_LOGIC; signal \cr_int[15]_i_18_n_0\ : STD_LOGIC; signal \cr_int[15]_i_19_n_0\ : STD_LOGIC; signal \cr_int[15]_i_22_n_0\ : STD_LOGIC; signal \cr_int[15]_i_23_n_0\ : STD_LOGIC; signal \cr_int[15]_i_24_n_0\ : STD_LOGIC; signal \cr_int[15]_i_25_n_0\ : STD_LOGIC; signal \cr_int[15]_i_26_n_0\ : STD_LOGIC; signal \cr_int[15]_i_27_n_0\ : STD_LOGIC; signal \cr_int[15]_i_29_n_0\ : STD_LOGIC; signal \cr_int[15]_i_2_n_0\ : STD_LOGIC; signal \cr_int[15]_i_30_n_0\ : STD_LOGIC; signal \cr_int[15]_i_31_n_0\ : STD_LOGIC; signal \cr_int[15]_i_32_n_0\ : STD_LOGIC; signal \cr_int[15]_i_33_n_0\ : STD_LOGIC; signal \cr_int[15]_i_34_n_0\ : STD_LOGIC; signal \cr_int[15]_i_35_n_0\ : STD_LOGIC; signal \cr_int[15]_i_36_n_0\ : STD_LOGIC; signal \cr_int[15]_i_3_n_0\ : STD_LOGIC; signal \cr_int[15]_i_40_n_0\ : STD_LOGIC; signal \cr_int[15]_i_41_n_0\ : STD_LOGIC; signal \cr_int[15]_i_42_n_0\ : STD_LOGIC; signal \cr_int[15]_i_43_n_0\ : STD_LOGIC; signal \cr_int[15]_i_48_n_0\ : STD_LOGIC; signal \cr_int[15]_i_49_n_0\ : STD_LOGIC; signal \cr_int[15]_i_4_n_0\ : STD_LOGIC; signal \cr_int[15]_i_50_n_0\ : STD_LOGIC; signal \cr_int[15]_i_51_n_0\ : STD_LOGIC; signal \cr_int[15]_i_5_n_0\ : STD_LOGIC; signal \cr_int[15]_i_6_n_0\ : STD_LOGIC; signal \cr_int[15]_i_7_n_0\ : STD_LOGIC; signal \cr_int[15]_i_8_n_0\ : STD_LOGIC; signal \cr_int[15]_i_9_n_0\ : STD_LOGIC; signal \cr_int[19]_i_10_n_0\ : STD_LOGIC; signal \cr_int[19]_i_11_n_0\ : STD_LOGIC; signal \cr_int[19]_i_12_n_0\ : STD_LOGIC; signal \cr_int[19]_i_13_n_0\ : STD_LOGIC; signal \cr_int[19]_i_14_n_0\ : STD_LOGIC; signal \cr_int[19]_i_15_n_0\ : STD_LOGIC; signal \cr_int[19]_i_16_n_0\ : STD_LOGIC; signal \cr_int[19]_i_17_n_0\ : STD_LOGIC; signal \cr_int[19]_i_18_n_0\ : STD_LOGIC; signal \cr_int[19]_i_19_n_0\ : STD_LOGIC; signal \cr_int[19]_i_22_n_0\ : STD_LOGIC; signal \cr_int[19]_i_23_n_0\ : STD_LOGIC; signal \cr_int[19]_i_24_n_0\ : STD_LOGIC; signal \cr_int[19]_i_25_n_0\ : STD_LOGIC; signal \cr_int[19]_i_26_n_0\ : STD_LOGIC; signal \cr_int[19]_i_27_n_0\ : STD_LOGIC; signal \cr_int[19]_i_29_n_0\ : STD_LOGIC; signal \cr_int[19]_i_2_n_0\ : STD_LOGIC; signal \cr_int[19]_i_30_n_0\ : STD_LOGIC; signal \cr_int[19]_i_31_n_0\ : STD_LOGIC; signal \cr_int[19]_i_32_n_0\ : STD_LOGIC; signal \cr_int[19]_i_33_n_0\ : STD_LOGIC; signal \cr_int[19]_i_34_n_0\ : STD_LOGIC; signal \cr_int[19]_i_35_n_0\ : STD_LOGIC; signal \cr_int[19]_i_36_n_0\ : STD_LOGIC; signal \cr_int[19]_i_38_n_0\ : STD_LOGIC; signal \cr_int[19]_i_39_n_0\ : STD_LOGIC; signal \cr_int[19]_i_3_n_0\ : STD_LOGIC; signal \cr_int[19]_i_40_n_0\ : STD_LOGIC; signal \cr_int[19]_i_41_n_0\ : STD_LOGIC; signal \cr_int[19]_i_4_n_0\ : STD_LOGIC; signal \cr_int[19]_i_5_n_0\ : STD_LOGIC; signal \cr_int[19]_i_6_n_0\ : STD_LOGIC; signal \cr_int[19]_i_7_n_0\ : STD_LOGIC; signal \cr_int[19]_i_8_n_0\ : STD_LOGIC; signal \cr_int[19]_i_9_n_0\ : STD_LOGIC; signal \cr_int[23]_i_10_n_0\ : STD_LOGIC; signal \cr_int[23]_i_11_n_0\ : STD_LOGIC; signal \cr_int[23]_i_12_n_0\ : STD_LOGIC; signal \cr_int[23]_i_13_n_0\ : STD_LOGIC; signal \cr_int[23]_i_14_n_0\ : STD_LOGIC; signal \cr_int[23]_i_15_n_0\ : STD_LOGIC; signal \cr_int[23]_i_16_n_0\ : STD_LOGIC; signal \cr_int[23]_i_17_n_0\ : STD_LOGIC; signal \cr_int[23]_i_18_n_0\ : STD_LOGIC; signal \cr_int[23]_i_19_n_0\ : STD_LOGIC; signal \cr_int[23]_i_21_n_0\ : STD_LOGIC; signal \cr_int[23]_i_22_n_0\ : STD_LOGIC; signal \cr_int[23]_i_23_n_0\ : STD_LOGIC; signal \cr_int[23]_i_24_n_0\ : STD_LOGIC; signal \cr_int[23]_i_25_n_0\ : STD_LOGIC; signal \cr_int[23]_i_26_n_0\ : STD_LOGIC; signal \cr_int[23]_i_27_n_0\ : STD_LOGIC; signal \cr_int[23]_i_28_n_0\ : STD_LOGIC; signal \cr_int[23]_i_29_n_0\ : STD_LOGIC; signal \cr_int[23]_i_2_n_0\ : STD_LOGIC; signal \cr_int[23]_i_30_n_0\ : STD_LOGIC; signal \cr_int[23]_i_3_n_0\ : STD_LOGIC; signal \cr_int[23]_i_4_n_0\ : STD_LOGIC; signal \cr_int[23]_i_5_n_0\ : STD_LOGIC; signal \cr_int[23]_i_6_n_0\ : STD_LOGIC; signal \cr_int[23]_i_7_n_0\ : STD_LOGIC; signal \cr_int[23]_i_8_n_0\ : STD_LOGIC; signal \cr_int[23]_i_9_n_0\ : STD_LOGIC; signal \cr_int[27]_i_10_n_0\ : STD_LOGIC; signal \cr_int[27]_i_11_n_0\ : STD_LOGIC; signal \cr_int[27]_i_12_n_0\ : STD_LOGIC; signal \cr_int[27]_i_13_n_0\ : STD_LOGIC; signal \cr_int[27]_i_2_n_0\ : STD_LOGIC; signal \cr_int[27]_i_3_n_0\ : STD_LOGIC; signal \cr_int[27]_i_4_n_0\ : STD_LOGIC; signal \cr_int[27]_i_5_n_0\ : STD_LOGIC; signal \cr_int[27]_i_6_n_0\ : STD_LOGIC; signal \cr_int[27]_i_7_n_0\ : STD_LOGIC; signal \cr_int[27]_i_8_n_0\ : STD_LOGIC; signal \cr_int[31]_i_100_n_0\ : STD_LOGIC; signal \cr_int[31]_i_103_n_0\ : STD_LOGIC; signal \cr_int[31]_i_108_n_0\ : STD_LOGIC; signal \cr_int[31]_i_109_n_0\ : STD_LOGIC; signal \cr_int[31]_i_110_n_0\ : STD_LOGIC; signal \cr_int[31]_i_111_n_0\ : STD_LOGIC; signal \cr_int[31]_i_112_n_0\ : STD_LOGIC; signal \cr_int[31]_i_113_n_0\ : STD_LOGIC; signal \cr_int[31]_i_114_n_0\ : STD_LOGIC; signal \cr_int[31]_i_115_n_0\ : STD_LOGIC; signal \cr_int[31]_i_116_n_0\ : STD_LOGIC; signal \cr_int[31]_i_117_n_0\ : STD_LOGIC; signal \cr_int[31]_i_118_n_0\ : STD_LOGIC; signal \cr_int[31]_i_119_n_0\ : STD_LOGIC; signal \cr_int[31]_i_120_n_0\ : STD_LOGIC; signal \cr_int[31]_i_121_n_0\ : STD_LOGIC; signal \cr_int[31]_i_122_n_0\ : STD_LOGIC; signal \cr_int[31]_i_123_n_0\ : STD_LOGIC; signal \cr_int[31]_i_124_n_0\ : STD_LOGIC; signal \cr_int[31]_i_125_n_0\ : STD_LOGIC; signal \cr_int[31]_i_126_n_0\ : STD_LOGIC; signal \cr_int[31]_i_13_n_0\ : STD_LOGIC; signal \cr_int[31]_i_15_n_0\ : STD_LOGIC; signal \cr_int[31]_i_16_n_0\ : STD_LOGIC; signal \cr_int[31]_i_17_n_0\ : STD_LOGIC; signal \cr_int[31]_i_18_n_0\ : STD_LOGIC; signal \cr_int[31]_i_19_n_0\ : STD_LOGIC; signal \cr_int[31]_i_20_n_0\ : STD_LOGIC; signal \cr_int[31]_i_22_n_0\ : STD_LOGIC; signal \cr_int[31]_i_23_n_0\ : STD_LOGIC; signal \cr_int[31]_i_25_n_0\ : STD_LOGIC; signal \cr_int[31]_i_26_n_0\ : STD_LOGIC; signal \cr_int[31]_i_2_n_0\ : STD_LOGIC; signal \cr_int[31]_i_31_n_0\ : STD_LOGIC; signal \cr_int[31]_i_32_n_0\ : STD_LOGIC; signal \cr_int[31]_i_33_n_0\ : STD_LOGIC; signal \cr_int[31]_i_34_n_0\ : STD_LOGIC; signal \cr_int[31]_i_35_n_0\ : STD_LOGIC; signal \cr_int[31]_i_37_n_0\ : STD_LOGIC; signal \cr_int[31]_i_38_n_0\ : STD_LOGIC; signal \cr_int[31]_i_3_n_0\ : STD_LOGIC; signal \cr_int[31]_i_40_n_0\ : STD_LOGIC; signal \cr_int[31]_i_41_n_0\ : STD_LOGIC; signal \cr_int[31]_i_42_n_0\ : STD_LOGIC; signal \cr_int[31]_i_43_n_0\ : STD_LOGIC; signal \cr_int[31]_i_44_n_0\ : STD_LOGIC; signal \cr_int[31]_i_45_n_0\ : STD_LOGIC; signal \cr_int[31]_i_46_n_0\ : STD_LOGIC; signal \cr_int[31]_i_47_n_0\ : STD_LOGIC; signal \cr_int[31]_i_4_n_0\ : STD_LOGIC; signal \cr_int[31]_i_50_n_0\ : STD_LOGIC; signal \cr_int[31]_i_51_n_0\ : STD_LOGIC; signal \cr_int[31]_i_52_n_0\ : STD_LOGIC; signal \cr_int[31]_i_53_n_0\ : STD_LOGIC; signal \cr_int[31]_i_55_n_0\ : STD_LOGIC; signal \cr_int[31]_i_56_n_0\ : STD_LOGIC; signal \cr_int[31]_i_57_n_0\ : STD_LOGIC; signal \cr_int[31]_i_58_n_0\ : STD_LOGIC; signal \cr_int[31]_i_59_n_0\ : STD_LOGIC; signal \cr_int[31]_i_5_n_0\ : STD_LOGIC; signal \cr_int[31]_i_60_n_0\ : STD_LOGIC; signal \cr_int[31]_i_61_n_0\ : STD_LOGIC; signal \cr_int[31]_i_62_n_0\ : STD_LOGIC; signal \cr_int[31]_i_6_n_0\ : STD_LOGIC; signal \cr_int[31]_i_71_n_0\ : STD_LOGIC; signal \cr_int[31]_i_72_n_0\ : STD_LOGIC; signal \cr_int[31]_i_73_n_0\ : STD_LOGIC; signal \cr_int[31]_i_74_n_0\ : STD_LOGIC; signal \cr_int[31]_i_75_n_0\ : STD_LOGIC; signal \cr_int[31]_i_76_n_0\ : STD_LOGIC; signal \cr_int[31]_i_77_n_0\ : STD_LOGIC; signal \cr_int[31]_i_78_n_0\ : STD_LOGIC; signal \cr_int[31]_i_79_n_0\ : STD_LOGIC; signal \cr_int[31]_i_80_n_0\ : STD_LOGIC; signal \cr_int[31]_i_81_n_0\ : STD_LOGIC; signal \cr_int[31]_i_82_n_0\ : STD_LOGIC; signal \cr_int[31]_i_83_n_0\ : STD_LOGIC; signal \cr_int[31]_i_84_n_0\ : STD_LOGIC; signal \cr_int[31]_i_85_n_0\ : STD_LOGIC; signal \cr_int[31]_i_87_n_0\ : STD_LOGIC; signal \cr_int[31]_i_88_n_0\ : STD_LOGIC; signal \cr_int[31]_i_89_n_0\ : STD_LOGIC; signal \cr_int[31]_i_90_n_0\ : STD_LOGIC; signal \cr_int[31]_i_92_n_0\ : STD_LOGIC; signal \cr_int[31]_i_93_n_0\ : STD_LOGIC; signal \cr_int[31]_i_94_n_0\ : STD_LOGIC; signal \cr_int[31]_i_95_n_0\ : STD_LOGIC; signal \cr_int[31]_i_96_n_0\ : STD_LOGIC; signal \cr_int[31]_i_97_n_0\ : STD_LOGIC; signal \cr_int[3]_i_10_n_0\ : STD_LOGIC; signal \cr_int[3]_i_11_n_0\ : STD_LOGIC; signal \cr_int[3]_i_13_n_0\ : STD_LOGIC; signal \cr_int[3]_i_14_n_0\ : STD_LOGIC; signal \cr_int[3]_i_17_n_0\ : STD_LOGIC; signal \cr_int[3]_i_18_n_0\ : STD_LOGIC; signal \cr_int[3]_i_22_n_0\ : STD_LOGIC; signal \cr_int[3]_i_23_n_0\ : STD_LOGIC; signal \cr_int[3]_i_24_n_0\ : STD_LOGIC; signal \cr_int[3]_i_25_n_0\ : STD_LOGIC; signal \cr_int[3]_i_28_n_0\ : STD_LOGIC; signal \cr_int[3]_i_29_n_0\ : STD_LOGIC; signal \cr_int[3]_i_2_n_0\ : STD_LOGIC; signal \cr_int[3]_i_30_n_0\ : STD_LOGIC; signal \cr_int[3]_i_31_n_0\ : STD_LOGIC; signal \cr_int[3]_i_34_n_0\ : STD_LOGIC; signal \cr_int[3]_i_35_n_0\ : STD_LOGIC; signal \cr_int[3]_i_36_n_0\ : STD_LOGIC; signal \cr_int[3]_i_37_n_0\ : STD_LOGIC; signal \cr_int[3]_i_38_n_0\ : STD_LOGIC; signal \cr_int[3]_i_39_n_0\ : STD_LOGIC; signal \cr_int[3]_i_3_n_0\ : STD_LOGIC; signal \cr_int[3]_i_40_n_0\ : STD_LOGIC; signal \cr_int[3]_i_41_n_0\ : STD_LOGIC; signal \cr_int[3]_i_43_n_0\ : STD_LOGIC; signal \cr_int[3]_i_44_n_0\ : STD_LOGIC; signal \cr_int[3]_i_45_n_0\ : STD_LOGIC; signal \cr_int[3]_i_46_n_0\ : STD_LOGIC; signal \cr_int[3]_i_47_n_0\ : STD_LOGIC; signal \cr_int[3]_i_48_n_0\ : STD_LOGIC; signal \cr_int[3]_i_49_n_0\ : STD_LOGIC; signal \cr_int[3]_i_4_n_0\ : STD_LOGIC; signal \cr_int[3]_i_50_n_0\ : STD_LOGIC; signal \cr_int[3]_i_51_n_0\ : STD_LOGIC; signal \cr_int[3]_i_52_n_0\ : STD_LOGIC; signal \cr_int[3]_i_53_n_0\ : STD_LOGIC; signal \cr_int[3]_i_55_n_0\ : STD_LOGIC; signal \cr_int[3]_i_56_n_0\ : STD_LOGIC; signal \cr_int[3]_i_57_n_0\ : STD_LOGIC; signal \cr_int[3]_i_58_n_0\ : STD_LOGIC; signal \cr_int[3]_i_5_n_0\ : STD_LOGIC; signal \cr_int[3]_i_60_n_0\ : STD_LOGIC; signal \cr_int[3]_i_61_n_0\ : STD_LOGIC; signal \cr_int[3]_i_62_n_0\ : STD_LOGIC; signal \cr_int[3]_i_63_n_0\ : STD_LOGIC; signal \cr_int[3]_i_66_n_0\ : STD_LOGIC; signal \cr_int[3]_i_67_n_0\ : STD_LOGIC; signal \cr_int[3]_i_68_n_0\ : STD_LOGIC; signal \cr_int[3]_i_69_n_0\ : STD_LOGIC; signal \cr_int[3]_i_6_n_0\ : STD_LOGIC; signal \cr_int[3]_i_71_n_0\ : STD_LOGIC; signal \cr_int[3]_i_72_n_0\ : STD_LOGIC; signal \cr_int[3]_i_73_n_0\ : STD_LOGIC; signal \cr_int[3]_i_74_n_0\ : STD_LOGIC; signal \cr_int[3]_i_75_n_0\ : STD_LOGIC; signal \cr_int[3]_i_76_n_0\ : STD_LOGIC; signal \cr_int[3]_i_77_n_0\ : STD_LOGIC; signal \cr_int[3]_i_78_n_0\ : STD_LOGIC; signal \cr_int[3]_i_79_n_0\ : STD_LOGIC; signal \cr_int[3]_i_7_n_0\ : STD_LOGIC; signal \cr_int[3]_i_80_n_0\ : STD_LOGIC; signal \cr_int[3]_i_81_n_0\ : STD_LOGIC; signal \cr_int[3]_i_82_n_0\ : STD_LOGIC; signal \cr_int[3]_i_83_n_0\ : STD_LOGIC; signal \cr_int[3]_i_84_n_0\ : STD_LOGIC; signal \cr_int[3]_i_85_n_0\ : STD_LOGIC; signal \cr_int[3]_i_86_n_0\ : STD_LOGIC; signal \cr_int[3]_i_87_n_0\ : STD_LOGIC; signal \cr_int[3]_i_88_n_0\ : STD_LOGIC; signal \cr_int[3]_i_89_n_0\ : STD_LOGIC; signal \cr_int[3]_i_8_n_0\ : STD_LOGIC; signal \cr_int[3]_i_90_n_0\ : STD_LOGIC; signal \cr_int[3]_i_91_n_0\ : STD_LOGIC; signal \cr_int[3]_i_92_n_0\ : STD_LOGIC; signal \cr_int[3]_i_93_n_0\ : STD_LOGIC; signal \cr_int[3]_i_94_n_0\ : STD_LOGIC; signal \cr_int[3]_i_95_n_0\ : STD_LOGIC; signal \cr_int[3]_i_96_n_0\ : STD_LOGIC; signal \cr_int[7]_i_11_n_0\ : STD_LOGIC; signal \cr_int[7]_i_12_n_0\ : STD_LOGIC; signal \cr_int[7]_i_14_n_0\ : STD_LOGIC; signal \cr_int[7]_i_15_n_0\ : STD_LOGIC; signal \cr_int[7]_i_17_n_0\ : STD_LOGIC; signal \cr_int[7]_i_18_n_0\ : STD_LOGIC; signal \cr_int[7]_i_20_n_0\ : STD_LOGIC; signal \cr_int[7]_i_21_n_0\ : STD_LOGIC; signal \cr_int[7]_i_25_n_0\ : STD_LOGIC; signal \cr_int[7]_i_26_n_0\ : STD_LOGIC; signal \cr_int[7]_i_27_n_0\ : STD_LOGIC; signal \cr_int[7]_i_28_n_0\ : STD_LOGIC; signal \cr_int[7]_i_2_n_0\ : STD_LOGIC; signal \cr_int[7]_i_3_n_0\ : STD_LOGIC; signal \cr_int[7]_i_4_n_0\ : STD_LOGIC; signal \cr_int[7]_i_5_n_0\ : STD_LOGIC; signal \cr_int[7]_i_6_n_0\ : STD_LOGIC; signal \cr_int[7]_i_7_n_0\ : STD_LOGIC; signal \cr_int[7]_i_8_n_0\ : STD_LOGIC; signal \cr_int[7]_i_9_n_0\ : STD_LOGIC; signal cr_int_reg3 : STD_LOGIC_VECTOR ( 7 to 7 ); signal \cr_int_reg3__0\ : STD_LOGIC_VECTOR ( 8 downto 1 ); signal cr_int_reg4 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal cr_int_reg6 : STD_LOGIC_VECTOR ( 30 downto 8 ); signal cr_int_reg7 : STD_LOGIC; signal \^cr_int_reg[11]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cr_int_reg[11]_i_103_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_103_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_103_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_103_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_108_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_108_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_108_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_108_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_116_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_116_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_116_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_116_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_125_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_125_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_125_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_125_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_16_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_17_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_17_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_17_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_17_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_18_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_19_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_19_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_19_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_19_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_20_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_29_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_29_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_29_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_29_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_30_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_30_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_30_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_31_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_36_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_36_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_36_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_36_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_41_n_7\ : STD_LOGIC; signal \cr_int_reg[11]_i_46_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_46_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_46_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_46_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_51_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_51_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_51_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_51_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_56_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_56_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_56_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_56_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_69_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_69_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_69_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_69_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_79_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_79_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_79_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_79_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_92_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_92_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_92_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_92_n_3\ : STD_LOGIC; signal \^cr_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cr_int_reg[15]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[15]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[15]_i_20_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_20_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_28_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_28_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_28_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_28_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_4\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_5\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_6\ : STD_LOGIC; signal \cr_int_reg[15]_i_38_n_7\ : STD_LOGIC; signal \^cr_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cr_int_reg[19]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[19]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[19]_i_20_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_20_n_3\ : STD_LOGIC; signal \cr_int_reg[19]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[19]_i_28_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_28_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_28_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_28_n_3\ : STD_LOGIC; signal \^cr_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^cr_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \cr_int_reg[23]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[23]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[23]_i_20_n_0\ : STD_LOGIC; signal \cr_int_reg[23]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[23]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[23]_i_20_n_3\ : STD_LOGIC; signal \^cr_int_reg[27]_0\ : STD_LOGIC; signal \^cr_int_reg[27]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^cr_int_reg[27]_2\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \cr_int_reg[27]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[27]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[27]_i_9_n_3\ : STD_LOGIC; signal \^cr_int_reg[31]_0\ : STD_LOGIC; signal \^cr_int_reg[31]_1\ : STD_LOGIC; signal \^cr_int_reg[31]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cr_int_reg[31]_i_101_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_101_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_101_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_101_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_102_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_11_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_12_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_12_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_14_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_21_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_24_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_24_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_24_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_24_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_30_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_36_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_36_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_36_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_36_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_39_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_48_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_48_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_49_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_63_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_63_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_70_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_70_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_70_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_70_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_7_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_86_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_8_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_8_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_8_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_8_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_91_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_9_n_3\ : STD_LOGIC; signal \^cr_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \^cr_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^cr_int_reg[3]_2\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cr_int_reg[3]_i_15_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_15_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_15_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_15_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_16_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_19_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_20_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_20_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_20_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_20_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_21_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_21_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_21_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_21_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_26_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_26_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_26_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_26_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_27_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_32_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_33_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_42_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_42_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_42_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_42_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_54_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_59_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_59_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_59_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_59_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_64_n_7\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_65_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_0\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_1\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_2\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_3\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_4\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_5\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_6\ : STD_LOGIC; signal \cr_int_reg[3]_i_70_n_7\ : STD_LOGIC; signal \^cr_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^cr_int_reg[7]_1\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cr_int_reg[7]_i_1_n_0\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_1\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_2\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_3\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_4\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_5\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_6\ : STD_LOGIC; signal \cr_int_reg[7]_i_1_n_7\ : STD_LOGIC; signal \cr_int_reg[7]_i_23_n_0\ : STD_LOGIC; signal \cr_int_reg[7]_i_23_n_1\ : STD_LOGIC; signal \cr_int_reg[7]_i_23_n_2\ : STD_LOGIC; signal \cr_int_reg[7]_i_23_n_3\ : STD_LOGIC; signal \cr_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \cr_int_reg_n_0_[0]\ : STD_LOGIC; signal \cr_int_reg_n_0_[1]\ : STD_LOGIC; signal \cr_int_reg_n_0_[2]\ : STD_LOGIC; signal \cr_int_reg_n_0_[3]\ : STD_LOGIC; signal \cr_int_reg_n_0_[4]\ : STD_LOGIC; signal \cr_int_reg_n_0_[5]\ : STD_LOGIC; signal \cr_int_reg_n_0_[6]\ : STD_LOGIC; signal \cr_int_reg_n_0_[7]\ : STD_LOGIC; signal \cr_reg[7]_i_12_n_0\ : STD_LOGIC; signal \cr_reg[7]_i_12_n_1\ : STD_LOGIC; signal \cr_reg[7]_i_12_n_2\ : STD_LOGIC; signal \cr_reg[7]_i_12_n_3\ : STD_LOGIC; signal \cr_reg[7]_i_1_n_0\ : STD_LOGIC; signal \cr_reg[7]_i_1_n_1\ : STD_LOGIC; signal \cr_reg[7]_i_1_n_2\ : STD_LOGIC; signal \cr_reg[7]_i_1_n_3\ : STD_LOGIC; signal \cr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \cr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \cr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \cr_reg[7]_i_3_n_3\ : STD_LOGIC; signal edge : STD_LOGIC; signal edge_i_1_n_0 : STD_LOGIC; signal edge_rb : STD_LOGIC; signal edge_rb_i_1_n_0 : STD_LOGIC; signal \hdmi_d[10]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[11]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[12]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[13]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[14]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[15]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[15]_i_2_n_0\ : STD_LOGIC; signal \hdmi_d[8]_i_1_n_0\ : STD_LOGIC; signal \hdmi_d[9]_i_1_n_0\ : STD_LOGIC; signal hdmi_vsync_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal y : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \y[0]_i_1_n_0\ : STD_LOGIC; signal \y[1]_i_1_n_0\ : STD_LOGIC; signal \y[2]_i_1_n_0\ : STD_LOGIC; signal \y[3]_i_1_n_0\ : STD_LOGIC; signal \y[4]_i_1_n_0\ : STD_LOGIC; signal \y[5]_i_1_n_0\ : STD_LOGIC; signal \y[6]_i_1_n_0\ : STD_LOGIC; signal \y[7]_i_10_n_0\ : STD_LOGIC; signal \y[7]_i_11_n_0\ : STD_LOGIC; signal \y[7]_i_13_n_0\ : STD_LOGIC; signal \y[7]_i_14_n_0\ : STD_LOGIC; signal \y[7]_i_15_n_0\ : STD_LOGIC; signal \y[7]_i_16_n_0\ : STD_LOGIC; signal \y[7]_i_17_n_0\ : STD_LOGIC; signal \y[7]_i_18_n_0\ : STD_LOGIC; signal \y[7]_i_19_n_0\ : STD_LOGIC; signal \y[7]_i_20_n_0\ : STD_LOGIC; signal \y[7]_i_21_n_0\ : STD_LOGIC; signal \y[7]_i_22_n_0\ : STD_LOGIC; signal \y[7]_i_23_n_0\ : STD_LOGIC; signal \y[7]_i_24_n_0\ : STD_LOGIC; signal \y[7]_i_25_n_0\ : STD_LOGIC; signal \y[7]_i_26_n_0\ : STD_LOGIC; signal \y[7]_i_27_n_0\ : STD_LOGIC; signal \y[7]_i_28_n_0\ : STD_LOGIC; signal \y[7]_i_2_n_0\ : STD_LOGIC; signal \y[7]_i_4_n_0\ : STD_LOGIC; signal \y[7]_i_5_n_0\ : STD_LOGIC; signal \y[7]_i_6_n_0\ : STD_LOGIC; signal \y[7]_i_7_n_0\ : STD_LOGIC; signal \y[7]_i_8_n_0\ : STD_LOGIC; signal \y[7]_i_9_n_0\ : STD_LOGIC; signal y_hold : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \y_int[11]_i_100_n_0\ : STD_LOGIC; signal \y_int[11]_i_10_n_0\ : STD_LOGIC; signal \y_int[11]_i_12_n_0\ : STD_LOGIC; signal \y_int[11]_i_16_n_0\ : STD_LOGIC; signal \y_int[11]_i_19_n_0\ : STD_LOGIC; signal \y_int[11]_i_29_n_0\ : STD_LOGIC; signal \y_int[11]_i_2_n_0\ : STD_LOGIC; signal \y_int[11]_i_30_n_0\ : STD_LOGIC; signal \y_int[11]_i_31_n_0\ : STD_LOGIC; signal \y_int[11]_i_32_n_0\ : STD_LOGIC; signal \y_int[11]_i_34_n_0\ : STD_LOGIC; signal \y_int[11]_i_35_n_0\ : STD_LOGIC; signal \y_int[11]_i_36_n_0\ : STD_LOGIC; signal \y_int[11]_i_37_n_0\ : STD_LOGIC; signal \y_int[11]_i_3_n_0\ : STD_LOGIC; signal \y_int[11]_i_40_n_0\ : STD_LOGIC; signal \y_int[11]_i_41_n_0\ : STD_LOGIC; signal \y_int[11]_i_42_n_0\ : STD_LOGIC; signal \y_int[11]_i_43_n_0\ : STD_LOGIC; signal \y_int[11]_i_45_n_0\ : STD_LOGIC; signal \y_int[11]_i_46_n_0\ : STD_LOGIC; signal \y_int[11]_i_47_n_0\ : STD_LOGIC; signal \y_int[11]_i_48_n_0\ : STD_LOGIC; signal \y_int[11]_i_4_n_0\ : STD_LOGIC; signal \y_int[11]_i_50_n_0\ : STD_LOGIC; signal \y_int[11]_i_51_n_0\ : STD_LOGIC; signal \y_int[11]_i_52_n_0\ : STD_LOGIC; signal \y_int[11]_i_53_n_0\ : STD_LOGIC; signal \y_int[11]_i_58_n_0\ : STD_LOGIC; signal \y_int[11]_i_59_n_0\ : STD_LOGIC; signal \y_int[11]_i_5_n_0\ : STD_LOGIC; signal \y_int[11]_i_60_n_0\ : STD_LOGIC; signal \y_int[11]_i_61_n_0\ : STD_LOGIC; signal \y_int[11]_i_62_n_0\ : STD_LOGIC; signal \y_int[11]_i_63_n_0\ : STD_LOGIC; signal \y_int[11]_i_64_n_0\ : STD_LOGIC; signal \y_int[11]_i_65_n_0\ : STD_LOGIC; signal \y_int[11]_i_66_n_0\ : STD_LOGIC; signal \y_int[11]_i_67_n_0\ : STD_LOGIC; signal \y_int[11]_i_68_n_0\ : STD_LOGIC; signal \y_int[11]_i_69_n_0\ : STD_LOGIC; signal \y_int[11]_i_6_n_0\ : STD_LOGIC; signal \y_int[11]_i_70_n_0\ : STD_LOGIC; signal \y_int[11]_i_71_n_0\ : STD_LOGIC; signal \y_int[11]_i_72_n_0\ : STD_LOGIC; signal \y_int[11]_i_73_n_0\ : STD_LOGIC; signal \y_int[11]_i_74_n_0\ : STD_LOGIC; signal \y_int[11]_i_75_n_0\ : STD_LOGIC; signal \y_int[11]_i_76_n_0\ : STD_LOGIC; signal \y_int[11]_i_77_n_0\ : STD_LOGIC; signal \y_int[11]_i_78_n_0\ : STD_LOGIC; signal \y_int[11]_i_79_n_0\ : STD_LOGIC; signal \y_int[11]_i_7_n_0\ : STD_LOGIC; signal \y_int[11]_i_81_n_0\ : STD_LOGIC; signal \y_int[11]_i_82_n_0\ : STD_LOGIC; signal \y_int[11]_i_83_n_0\ : STD_LOGIC; signal \y_int[11]_i_84_n_0\ : STD_LOGIC; signal \y_int[11]_i_86_n_0\ : STD_LOGIC; signal \y_int[11]_i_87_n_0\ : STD_LOGIC; signal \y_int[11]_i_88_n_0\ : STD_LOGIC; signal \y_int[11]_i_89_n_0\ : STD_LOGIC; signal \y_int[11]_i_8_n_0\ : STD_LOGIC; signal \y_int[11]_i_90_n_0\ : STD_LOGIC; signal \y_int[11]_i_91_n_0\ : STD_LOGIC; signal \y_int[11]_i_92_n_0\ : STD_LOGIC; signal \y_int[11]_i_93_n_0\ : STD_LOGIC; signal \y_int[11]_i_94_n_0\ : STD_LOGIC; signal \y_int[11]_i_95_n_0\ : STD_LOGIC; signal \y_int[11]_i_96_n_0\ : STD_LOGIC; signal \y_int[11]_i_97_n_0\ : STD_LOGIC; signal \y_int[11]_i_98_n_0\ : STD_LOGIC; signal \y_int[11]_i_99_n_0\ : STD_LOGIC; signal \y_int[11]_i_9_n_0\ : STD_LOGIC; signal \y_int[15]_i_10_n_0\ : STD_LOGIC; signal \y_int[15]_i_12_n_0\ : STD_LOGIC; signal \y_int[15]_i_16_n_0\ : STD_LOGIC; signal \y_int[15]_i_18_n_0\ : STD_LOGIC; signal \y_int[15]_i_25_n_0\ : STD_LOGIC; signal \y_int[15]_i_26_n_0\ : STD_LOGIC; signal \y_int[15]_i_27_n_0\ : STD_LOGIC; signal \y_int[15]_i_28_n_0\ : STD_LOGIC; signal \y_int[15]_i_29_n_0\ : STD_LOGIC; signal \y_int[15]_i_2_n_0\ : STD_LOGIC; signal \y_int[15]_i_30_n_0\ : STD_LOGIC; signal \y_int[15]_i_31_n_0\ : STD_LOGIC; signal \y_int[15]_i_32_n_0\ : STD_LOGIC; signal \y_int[15]_i_3_n_0\ : STD_LOGIC; signal \y_int[15]_i_40_n_0\ : STD_LOGIC; signal \y_int[15]_i_41_n_0\ : STD_LOGIC; signal \y_int[15]_i_42_n_0\ : STD_LOGIC; signal \y_int[15]_i_43_n_0\ : STD_LOGIC; signal \y_int[15]_i_48_n_0\ : STD_LOGIC; signal \y_int[15]_i_49_n_0\ : STD_LOGIC; signal \y_int[15]_i_4_n_0\ : STD_LOGIC; signal \y_int[15]_i_50_n_0\ : STD_LOGIC; signal \y_int[15]_i_51_n_0\ : STD_LOGIC; signal \y_int[15]_i_5_n_0\ : STD_LOGIC; signal \y_int[15]_i_6_n_0\ : STD_LOGIC; signal \y_int[15]_i_7_n_0\ : STD_LOGIC; signal \y_int[15]_i_8_n_0\ : STD_LOGIC; signal \y_int[15]_i_9_n_0\ : STD_LOGIC; signal \y_int[19]_i_10_n_0\ : STD_LOGIC; signal \y_int[19]_i_12_n_0\ : STD_LOGIC; signal \y_int[19]_i_16_n_0\ : STD_LOGIC; signal \y_int[19]_i_18_n_0\ : STD_LOGIC; signal \y_int[19]_i_25_n_0\ : STD_LOGIC; signal \y_int[19]_i_26_n_0\ : STD_LOGIC; signal \y_int[19]_i_27_n_0\ : STD_LOGIC; signal \y_int[19]_i_28_n_0\ : STD_LOGIC; signal \y_int[19]_i_29_n_0\ : STD_LOGIC; signal \y_int[19]_i_2_n_0\ : STD_LOGIC; signal \y_int[19]_i_30_n_0\ : STD_LOGIC; signal \y_int[19]_i_31_n_0\ : STD_LOGIC; signal \y_int[19]_i_32_n_0\ : STD_LOGIC; signal \y_int[19]_i_3_n_0\ : STD_LOGIC; signal \y_int[19]_i_48_n_0\ : STD_LOGIC; signal \y_int[19]_i_49_n_0\ : STD_LOGIC; signal \y_int[19]_i_4_n_0\ : STD_LOGIC; signal \y_int[19]_i_50_n_0\ : STD_LOGIC; signal \y_int[19]_i_51_n_0\ : STD_LOGIC; signal \y_int[19]_i_5_n_0\ : STD_LOGIC; signal \y_int[19]_i_6_n_0\ : STD_LOGIC; signal \y_int[19]_i_7_n_0\ : STD_LOGIC; signal \y_int[19]_i_8_n_0\ : STD_LOGIC; signal \y_int[19]_i_9_n_0\ : STD_LOGIC; signal \y_int[23]_i_100_n_0\ : STD_LOGIC; signal \y_int[23]_i_101_n_0\ : STD_LOGIC; signal \y_int[23]_i_102_n_0\ : STD_LOGIC; signal \y_int[23]_i_103_n_0\ : STD_LOGIC; signal \y_int[23]_i_104_n_0\ : STD_LOGIC; signal \y_int[23]_i_12_n_0\ : STD_LOGIC; signal \y_int[23]_i_14_n_0\ : STD_LOGIC; signal \y_int[23]_i_18_n_0\ : STD_LOGIC; signal \y_int[23]_i_20_n_0\ : STD_LOGIC; signal \y_int[23]_i_26_n_0\ : STD_LOGIC; signal \y_int[23]_i_27_n_0\ : STD_LOGIC; signal \y_int[23]_i_28_n_0\ : STD_LOGIC; signal \y_int[23]_i_29_n_0\ : STD_LOGIC; signal \y_int[23]_i_2_n_0\ : STD_LOGIC; signal \y_int[23]_i_30_n_0\ : STD_LOGIC; signal \y_int[23]_i_31_n_0\ : STD_LOGIC; signal \y_int[23]_i_36_n_0\ : STD_LOGIC; signal \y_int[23]_i_37_n_0\ : STD_LOGIC; signal \y_int[23]_i_38_n_0\ : STD_LOGIC; signal \y_int[23]_i_39_n_0\ : STD_LOGIC; signal \y_int[23]_i_3_n_0\ : STD_LOGIC; signal \y_int[23]_i_40_n_0\ : STD_LOGIC; signal \y_int[23]_i_41_n_0\ : STD_LOGIC; signal \y_int[23]_i_42_n_0\ : STD_LOGIC; signal \y_int[23]_i_43_n_0\ : STD_LOGIC; signal \y_int[23]_i_46_n_0\ : STD_LOGIC; signal \y_int[23]_i_47_n_0\ : STD_LOGIC; signal \y_int[23]_i_48_n_0\ : STD_LOGIC; signal \y_int[23]_i_49_n_0\ : STD_LOGIC; signal \y_int[23]_i_4_n_0\ : STD_LOGIC; signal \y_int[23]_i_52_n_0\ : STD_LOGIC; signal \y_int[23]_i_53_n_0\ : STD_LOGIC; signal \y_int[23]_i_54_n_0\ : STD_LOGIC; signal \y_int[23]_i_55_n_0\ : STD_LOGIC; signal \y_int[23]_i_56_n_0\ : STD_LOGIC; signal \y_int[23]_i_57_n_0\ : STD_LOGIC; signal \y_int[23]_i_5_n_0\ : STD_LOGIC; signal \y_int[23]_i_62_n_0\ : STD_LOGIC; signal \y_int[23]_i_63_n_0\ : STD_LOGIC; signal \y_int[23]_i_64_n_0\ : STD_LOGIC; signal \y_int[23]_i_65_n_0\ : STD_LOGIC; signal \y_int[23]_i_67_n_0\ : STD_LOGIC; signal \y_int[23]_i_68_n_0\ : STD_LOGIC; signal \y_int[23]_i_69_n_0\ : STD_LOGIC; signal \y_int[23]_i_6_n_0\ : STD_LOGIC; signal \y_int[23]_i_70_n_0\ : STD_LOGIC; signal \y_int[23]_i_71_n_0\ : STD_LOGIC; signal \y_int[23]_i_72_n_0\ : STD_LOGIC; signal \y_int[23]_i_73_n_0\ : STD_LOGIC; signal \y_int[23]_i_74_n_0\ : STD_LOGIC; signal \y_int[23]_i_76_n_0\ : STD_LOGIC; signal \y_int[23]_i_77_n_0\ : STD_LOGIC; signal \y_int[23]_i_78_n_0\ : STD_LOGIC; signal \y_int[23]_i_79_n_0\ : STD_LOGIC; signal \y_int[23]_i_7_n_0\ : STD_LOGIC; signal \y_int[23]_i_80_n_0\ : STD_LOGIC; signal \y_int[23]_i_81_n_0\ : STD_LOGIC; signal \y_int[23]_i_82_n_0\ : STD_LOGIC; signal \y_int[23]_i_83_n_0\ : STD_LOGIC; signal \y_int[23]_i_84_n_0\ : STD_LOGIC; signal \y_int[23]_i_85_n_0\ : STD_LOGIC; signal \y_int[23]_i_86_n_0\ : STD_LOGIC; signal \y_int[23]_i_87_n_0\ : STD_LOGIC; signal \y_int[23]_i_88_n_0\ : STD_LOGIC; signal \y_int[23]_i_8_n_0\ : STD_LOGIC; signal \y_int[23]_i_90_n_0\ : STD_LOGIC; signal \y_int[23]_i_91_n_0\ : STD_LOGIC; signal \y_int[23]_i_92_n_0\ : STD_LOGIC; signal \y_int[23]_i_93_n_0\ : STD_LOGIC; signal \y_int[23]_i_94_n_0\ : STD_LOGIC; signal \y_int[23]_i_95_n_0\ : STD_LOGIC; signal \y_int[23]_i_96_n_0\ : STD_LOGIC; signal \y_int[23]_i_97_n_0\ : STD_LOGIC; signal \y_int[23]_i_98_n_0\ : STD_LOGIC; signal \y_int[23]_i_99_n_0\ : STD_LOGIC; signal \y_int[23]_i_9_n_0\ : STD_LOGIC; signal \y_int[27]_i_2_n_0\ : STD_LOGIC; signal \y_int[27]_i_3_n_0\ : STD_LOGIC; signal \y_int[27]_i_4_n_0\ : STD_LOGIC; signal \y_int[27]_i_5_n_0\ : STD_LOGIC; signal \y_int[31]_i_101_n_0\ : STD_LOGIC; signal \y_int[31]_i_104_n_0\ : STD_LOGIC; signal \y_int[31]_i_105_n_0\ : STD_LOGIC; signal \y_int[31]_i_106_n_0\ : STD_LOGIC; signal \y_int[31]_i_107_n_0\ : STD_LOGIC; signal \y_int[31]_i_108_n_0\ : STD_LOGIC; signal \y_int[31]_i_109_n_0\ : STD_LOGIC; signal \y_int[31]_i_110_n_0\ : STD_LOGIC; signal \y_int[31]_i_111_n_0\ : STD_LOGIC; signal \y_int[31]_i_112_n_0\ : STD_LOGIC; signal \y_int[31]_i_113_n_0\ : STD_LOGIC; signal \y_int[31]_i_114_n_0\ : STD_LOGIC; signal \y_int[31]_i_115_n_0\ : STD_LOGIC; signal \y_int[31]_i_116_n_0\ : STD_LOGIC; signal \y_int[31]_i_13_n_0\ : STD_LOGIC; signal \y_int[31]_i_14_n_0\ : STD_LOGIC; signal \y_int[31]_i_15_n_0\ : STD_LOGIC; signal \y_int[31]_i_17_n_0\ : STD_LOGIC; signal \y_int[31]_i_18_n_0\ : STD_LOGIC; signal \y_int[31]_i_19_n_0\ : STD_LOGIC; signal \y_int[31]_i_20_n_0\ : STD_LOGIC; signal \y_int[31]_i_2_n_0\ : STD_LOGIC; signal \y_int[31]_i_32_n_0\ : STD_LOGIC; signal \y_int[31]_i_33_n_0\ : STD_LOGIC; signal \y_int[31]_i_34_n_0\ : STD_LOGIC; signal \y_int[31]_i_35_n_0\ : STD_LOGIC; signal \y_int[31]_i_36_n_0\ : STD_LOGIC; signal \y_int[31]_i_3_n_0\ : STD_LOGIC; signal \y_int[31]_i_40_n_0\ : STD_LOGIC; signal \y_int[31]_i_41_n_0\ : STD_LOGIC; signal \y_int[31]_i_42_n_0\ : STD_LOGIC; signal \y_int[31]_i_43_n_0\ : STD_LOGIC; signal \y_int[31]_i_44_n_0\ : STD_LOGIC; signal \y_int[31]_i_45_n_0\ : STD_LOGIC; signal \y_int[31]_i_46_n_0\ : STD_LOGIC; signal \y_int[31]_i_47_n_0\ : STD_LOGIC; signal \y_int[31]_i_4_n_0\ : STD_LOGIC; signal \y_int[31]_i_5_n_0\ : STD_LOGIC; signal \y_int[31]_i_63_n_0\ : STD_LOGIC; signal \y_int[31]_i_64_n_0\ : STD_LOGIC; signal \y_int[31]_i_65_n_0\ : STD_LOGIC; signal \y_int[31]_i_66_n_0\ : STD_LOGIC; signal \y_int[31]_i_67_n_0\ : STD_LOGIC; signal \y_int[31]_i_68_n_0\ : STD_LOGIC; signal \y_int[31]_i_69_n_0\ : STD_LOGIC; signal \y_int[31]_i_6_n_0\ : STD_LOGIC; signal \y_int[31]_i_70_n_0\ : STD_LOGIC; signal \y_int[31]_i_89_n_0\ : STD_LOGIC; signal \y_int[31]_i_90_n_0\ : STD_LOGIC; signal \y_int[31]_i_91_n_0\ : STD_LOGIC; signal \y_int[31]_i_92_n_0\ : STD_LOGIC; signal \y_int[3]_i_10_n_0\ : STD_LOGIC; signal \y_int[3]_i_13_n_0\ : STD_LOGIC; signal \y_int[3]_i_17_n_0\ : STD_LOGIC; signal \y_int[3]_i_18_n_0\ : STD_LOGIC; signal \y_int[3]_i_22_n_0\ : STD_LOGIC; signal \y_int[3]_i_23_n_0\ : STD_LOGIC; signal \y_int[3]_i_24_n_0\ : STD_LOGIC; signal \y_int[3]_i_25_n_0\ : STD_LOGIC; signal \y_int[3]_i_27_n_0\ : STD_LOGIC; signal \y_int[3]_i_28_n_0\ : STD_LOGIC; signal \y_int[3]_i_29_n_0\ : STD_LOGIC; signal \y_int[3]_i_2_n_0\ : STD_LOGIC; signal \y_int[3]_i_31_n_0\ : STD_LOGIC; signal \y_int[3]_i_32_n_0\ : STD_LOGIC; signal \y_int[3]_i_33_n_0\ : STD_LOGIC; signal \y_int[3]_i_34_n_0\ : STD_LOGIC; signal \y_int[3]_i_3_n_0\ : STD_LOGIC; signal \y_int[3]_i_4_n_0\ : STD_LOGIC; signal \y_int[3]_i_50_n_0\ : STD_LOGIC; signal \y_int[3]_i_51_n_0\ : STD_LOGIC; signal \y_int[3]_i_52_n_0\ : STD_LOGIC; signal \y_int[3]_i_53_n_0\ : STD_LOGIC; signal \y_int[3]_i_54_n_0\ : STD_LOGIC; signal \y_int[3]_i_56_n_0\ : STD_LOGIC; signal \y_int[3]_i_57_n_0\ : STD_LOGIC; signal \y_int[3]_i_58_n_0\ : STD_LOGIC; signal \y_int[3]_i_59_n_0\ : STD_LOGIC; signal \y_int[3]_i_5_n_0\ : STD_LOGIC; signal \y_int[3]_i_60_n_0\ : STD_LOGIC; signal \y_int[3]_i_61_n_0\ : STD_LOGIC; signal \y_int[3]_i_62_n_0\ : STD_LOGIC; signal \y_int[3]_i_63_n_0\ : STD_LOGIC; signal \y_int[3]_i_66_n_0\ : STD_LOGIC; signal \y_int[3]_i_67_n_0\ : STD_LOGIC; signal \y_int[3]_i_68_n_0\ : STD_LOGIC; signal \y_int[3]_i_69_n_0\ : STD_LOGIC; signal \y_int[3]_i_6_n_0\ : STD_LOGIC; signal \y_int[3]_i_71_n_0\ : STD_LOGIC; signal \y_int[3]_i_72_n_0\ : STD_LOGIC; signal \y_int[3]_i_73_n_0\ : STD_LOGIC; signal \y_int[3]_i_74_n_0\ : STD_LOGIC; signal \y_int[3]_i_7_n_0\ : STD_LOGIC; signal \y_int[3]_i_84_n_0\ : STD_LOGIC; signal \y_int[3]_i_85_n_0\ : STD_LOGIC; signal \y_int[3]_i_86_n_0\ : STD_LOGIC; signal \y_int[3]_i_87_n_0\ : STD_LOGIC; signal \y_int[3]_i_88_n_0\ : STD_LOGIC; signal \y_int[3]_i_89_n_0\ : STD_LOGIC; signal \y_int[3]_i_8_n_0\ : STD_LOGIC; signal \y_int[3]_i_90_n_0\ : STD_LOGIC; signal \y_int[3]_i_91_n_0\ : STD_LOGIC; signal \y_int[3]_i_92_n_0\ : STD_LOGIC; signal \y_int[7]_i_11_n_0\ : STD_LOGIC; signal \y_int[7]_i_13_n_0\ : STD_LOGIC; signal \y_int[7]_i_16_n_0\ : STD_LOGIC; signal \y_int[7]_i_19_n_0\ : STD_LOGIC; signal \y_int[7]_i_29_n_0\ : STD_LOGIC; signal \y_int[7]_i_2_n_0\ : STD_LOGIC; signal \y_int[7]_i_30_n_0\ : STD_LOGIC; signal \y_int[7]_i_31_n_0\ : STD_LOGIC; signal \y_int[7]_i_32_n_0\ : STD_LOGIC; signal \y_int[7]_i_33_n_0\ : STD_LOGIC; signal \y_int[7]_i_3_n_0\ : STD_LOGIC; signal \y_int[7]_i_4_n_0\ : STD_LOGIC; signal \y_int[7]_i_5_n_0\ : STD_LOGIC; signal \y_int[7]_i_6_n_0\ : STD_LOGIC; signal \y_int[7]_i_7_n_0\ : STD_LOGIC; signal \y_int[7]_i_8_n_0\ : STD_LOGIC; signal \y_int[7]_i_9_n_0\ : STD_LOGIC; signal y_int_reg1 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal y_int_reg2 : STD_LOGIC_VECTOR ( 8 downto 1 ); signal y_int_reg20_in : STD_LOGIC_VECTOR ( 22 downto 1 ); signal y_int_reg3 : STD_LOGIC_VECTOR ( 22 downto 1 ); signal y_int_reg5 : STD_LOGIC_VECTOR ( 30 downto 8 ); signal y_int_reg6 : STD_LOGIC; signal \y_int_reg[11]_i_14_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_14_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_14_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_14_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_15_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_15_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_15_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_15_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[11]_i_20_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_20_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_20_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_21_n_7\ : STD_LOGIC; signal \y_int_reg[11]_i_22_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_22_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_22_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_28_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_28_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_28_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_28_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_33_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_33_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_33_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_33_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_38_n_7\ : STD_LOGIC; signal \y_int_reg[11]_i_39_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_39_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_39_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_39_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_44_n_7\ : STD_LOGIC; signal \y_int_reg[11]_i_49_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_49_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_49_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_49_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_80_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_80_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_80_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_80_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_85_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_85_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_85_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_85_n_3\ : STD_LOGIC; signal \^y_int_reg[15]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \y_int_reg[15]_i_14_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_14_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_14_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_14_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_15_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_15_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_15_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_15_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[15]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_4\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_5\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_6\ : STD_LOGIC; signal \y_int_reg[15]_i_33_n_7\ : STD_LOGIC; signal \y_int_reg[15]_i_35_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_35_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_35_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_35_n_3\ : STD_LOGIC; signal \^y_int_reg[19]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \y_int_reg[19]_i_14_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_14_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_14_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_14_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_15_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_15_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_15_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_15_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[19]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[19]_i_35_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_35_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_35_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_35_n_3\ : STD_LOGIC; signal \^y_int_reg[23]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^y_int_reg[23]_1\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^y_int_reg[23]_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \y_int_reg[23]_i_10_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_10_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_10_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_11_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_16_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_16_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_16_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_16_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_17_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_17_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_17_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_17_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[23]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[23]_i_25_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_25_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_25_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_25_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_33_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_33_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_33_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_34_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_44_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_44_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_44_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_44_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_45_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_45_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_45_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_45_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_51_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_51_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_51_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_51_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_66_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_66_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_66_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_66_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_75_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_75_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_75_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_75_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_89_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_89_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_89_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_89_n_3\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[27]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_11_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_16_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_30_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_62_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_75_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_75_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_7_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_7_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_86_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_87_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_88_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_8_n_7\ : STD_LOGIC; signal \^y_int_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^y_int_reg[3]_1\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \y_int_reg[3]_i_15_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_15_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_15_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_15_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_16_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_21_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_21_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_21_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_21_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_26_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_30_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_35_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_36_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_36_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_36_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_55_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_64_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_64_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_65_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_65_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_65_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_65_n_3\ : STD_LOGIC; signal \^y_int_reg[7]_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \y_int_reg[7]_i_1_n_0\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_1\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_2\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_3\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_4\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_5\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_6\ : STD_LOGIC; signal \y_int_reg[7]_i_1_n_7\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_0\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_1\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_2\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_3\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_4\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_5\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_6\ : STD_LOGIC; signal \y_int_reg[7]_i_24_n_7\ : STD_LOGIC; signal \y_int_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \y_int_reg_n_0_[0]\ : STD_LOGIC; signal \y_int_reg_n_0_[1]\ : STD_LOGIC; signal \y_int_reg_n_0_[2]\ : STD_LOGIC; signal \y_int_reg_n_0_[3]\ : STD_LOGIC; signal \y_int_reg_n_0_[4]\ : STD_LOGIC; signal \y_int_reg_n_0_[5]\ : STD_LOGIC; signal \y_int_reg_n_0_[6]\ : STD_LOGIC; signal \y_int_reg_n_0_[7]\ : STD_LOGIC; signal \y_reg[7]_i_12_n_0\ : STD_LOGIC; signal \y_reg[7]_i_12_n_1\ : STD_LOGIC; signal \y_reg[7]_i_12_n_2\ : STD_LOGIC; signal \y_reg[7]_i_12_n_3\ : STD_LOGIC; signal \y_reg[7]_i_1_n_0\ : STD_LOGIC; signal \y_reg[7]_i_1_n_1\ : STD_LOGIC; signal \y_reg[7]_i_1_n_2\ : STD_LOGIC; signal \y_reg[7]_i_1_n_3\ : STD_LOGIC; signal \y_reg[7]_i_3_n_0\ : STD_LOGIC; signal \y_reg[7]_i_3_n_1\ : STD_LOGIC; signal \y_reg[7]_i_3_n_2\ : STD_LOGIC; signal \y_reg[7]_i_3_n_3\ : STD_LOGIC; signal NLW_ODDR_inst_R_UNCONNECTED : STD_LOGIC; signal NLW_ODDR_inst_S_UNCONNECTED : STD_LOGIC; signal \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cb_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_cr_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_reg[7]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_reg[7]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_reg[7]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute \__SRVAL\ : string; attribute \__SRVAL\ of ODDR_inst : label is "TRUE"; attribute box_type : string; attribute box_type of ODDR_inst : label is "PRIMITIVE"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cb[0]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \cb[1]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \cb[2]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \cb[3]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \cb[4]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \cb[5]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \cb[6]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \cb[7]_i_2\ : label is "soft_lutpair34"; attribute HLUTNM : string; attribute HLUTNM of \cb_int[11]_i_2\ : label is "lutpair8"; attribute HLUTNM of \cb_int[11]_i_3\ : label is "lutpair7"; attribute HLUTNM of \cb_int[11]_i_4\ : label is "lutpair6"; attribute HLUTNM of \cb_int[11]_i_6\ : label is "lutpair9"; attribute HLUTNM of \cb_int[11]_i_7\ : label is "lutpair8"; attribute HLUTNM of \cb_int[11]_i_8\ : label is "lutpair7"; attribute HLUTNM of \cb_int[11]_i_9\ : label is "lutpair6"; attribute HLUTNM of \cb_int[15]_i_2\ : label is "lutpair12"; attribute HLUTNM of \cb_int[15]_i_3\ : label is "lutpair11"; attribute HLUTNM of \cb_int[15]_i_4\ : label is "lutpair10"; attribute HLUTNM of \cb_int[15]_i_5\ : label is "lutpair9"; attribute HLUTNM of \cb_int[15]_i_6\ : label is "lutpair13"; attribute HLUTNM of \cb_int[15]_i_7\ : label is "lutpair12"; attribute HLUTNM of \cb_int[15]_i_8\ : label is "lutpair11"; attribute HLUTNM of \cb_int[15]_i_9\ : label is "lutpair10"; attribute HLUTNM of \cb_int[19]_i_2\ : label is "lutpair16"; attribute HLUTNM of \cb_int[19]_i_3\ : label is "lutpair15"; attribute HLUTNM of \cb_int[19]_i_4\ : label is "lutpair14"; attribute HLUTNM of \cb_int[19]_i_5\ : label is "lutpair13"; attribute HLUTNM of \cb_int[19]_i_6\ : label is "lutpair17"; attribute HLUTNM of \cb_int[19]_i_7\ : label is "lutpair16"; attribute HLUTNM of \cb_int[19]_i_8\ : label is "lutpair15"; attribute HLUTNM of \cb_int[19]_i_9\ : label is "lutpair14"; attribute HLUTNM of \cb_int[23]_i_2\ : label is "lutpair20"; attribute SOFT_HLUTNM of \cb_int[23]_i_20\ : label is "soft_lutpair19"; attribute HLUTNM of \cb_int[23]_i_3\ : label is "lutpair19"; attribute HLUTNM of \cb_int[23]_i_4\ : label is "lutpair18"; attribute HLUTNM of \cb_int[23]_i_5\ : label is "lutpair17"; attribute HLUTNM of \cb_int[23]_i_6\ : label is "lutpair21"; attribute HLUTNM of \cb_int[23]_i_7\ : label is "lutpair20"; attribute HLUTNM of \cb_int[23]_i_8\ : label is "lutpair19"; attribute HLUTNM of \cb_int[23]_i_9\ : label is "lutpair18"; attribute HLUTNM of \cb_int[27]_i_2\ : label is "lutpair21"; attribute SOFT_HLUTNM of \cb_int[31]_i_13\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \cb_int[31]_i_86\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cb_int[31]_i_87\ : label is "soft_lutpair18"; attribute HLUTNM of \cb_int[3]_i_2\ : label is "lutpair2"; attribute HLUTNM of \cb_int[3]_i_3\ : label is "lutpair1"; attribute HLUTNM of \cb_int[3]_i_4\ : label is "lutpair39"; attribute HLUTNM of \cb_int[3]_i_5\ : label is "lutpair3"; attribute HLUTNM of \cb_int[3]_i_6\ : label is "lutpair2"; attribute HLUTNM of \cb_int[3]_i_7\ : label is "lutpair1"; attribute HLUTNM of \cb_int[3]_i_8\ : label is "lutpair39"; attribute HLUTNM of \cb_int[7]_i_3\ : label is "lutpair5"; attribute HLUTNM of \cb_int[7]_i_4\ : label is "lutpair4"; attribute HLUTNM of \cb_int[7]_i_5\ : label is "lutpair3"; attribute HLUTNM of \cb_int[7]_i_8\ : label is "lutpair5"; attribute HLUTNM of \cb_int[7]_i_9\ : label is "lutpair4"; attribute SOFT_HLUTNM of \cr[0]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \cr[1]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \cr[2]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \cr[3]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \cr[4]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \cr[5]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \cr[6]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \cr[7]_i_2\ : label is "soft_lutpair26"; attribute HLUTNM of \cr_int[11]_i_2\ : label is "lutpair29"; attribute SOFT_HLUTNM of \cr_int[11]_i_22\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \cr_int[11]_i_23\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \cr_int[11]_i_27\ : label is "soft_lutpair20"; attribute HLUTNM of \cr_int[11]_i_7\ : label is "lutpair29"; attribute HLUTNM of \cr_int[15]_i_2\ : label is "lutpair30"; attribute HLUTNM of \cr_int[15]_i_7\ : label is "lutpair30"; attribute HLUTNM of \cr_int[19]_i_2\ : label is "lutpair31"; attribute HLUTNM of \cr_int[19]_i_7\ : label is "lutpair31"; attribute HLUTNM of \cr_int[23]_i_2\ : label is "lutpair32"; attribute HLUTNM of \cr_int[23]_i_7\ : label is "lutpair32"; attribute SOFT_HLUTNM of \cr_int[31]_i_13\ : label is "soft_lutpair20"; attribute HLUTNM of \cr_int[31]_i_16\ : label is "lutpair23"; attribute HLUTNM of \cr_int[31]_i_44\ : label is "lutpair23"; attribute HLUTNM of \cr_int[3]_i_2\ : label is "lutpair25"; attribute HLUTNM of \cr_int[3]_i_3\ : label is "lutpair24"; attribute HLUTNM of \cr_int[3]_i_34\ : label is "lutpair22"; attribute HLUTNM of \cr_int[3]_i_39\ : label is "lutpair22"; attribute HLUTNM of \cr_int[3]_i_4\ : label is "lutpair40"; attribute HLUTNM of \cr_int[3]_i_5\ : label is "lutpair26"; attribute HLUTNM of \cr_int[3]_i_6\ : label is "lutpair25"; attribute HLUTNM of \cr_int[3]_i_7\ : label is "lutpair24"; attribute HLUTNM of \cr_int[3]_i_8\ : label is "lutpair40"; attribute HLUTNM of \cr_int[7]_i_3\ : label is "lutpair28"; attribute HLUTNM of \cr_int[7]_i_4\ : label is "lutpair27"; attribute HLUTNM of \cr_int[7]_i_5\ : label is "lutpair26"; attribute HLUTNM of \cr_int[7]_i_8\ : label is "lutpair28"; attribute HLUTNM of \cr_int[7]_i_9\ : label is "lutpair27"; attribute SOFT_HLUTNM of \y[0]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \y[1]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \y[2]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \y[3]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \y[4]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \y[5]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \y[6]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \y[7]_i_2\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \y_hold[0]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \y_hold[1]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \y_hold[2]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \y_hold[3]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \y_hold[4]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \y_hold[5]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \y_hold[6]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \y_hold[7]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \y_int[23]_i_12\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \y_int[31]_i_13\ : label is "soft_lutpair21"; attribute HLUTNM of \y_int[3]_i_2\ : label is "lutpair35"; attribute HLUTNM of \y_int[3]_i_3\ : label is "lutpair34"; attribute HLUTNM of \y_int[3]_i_4\ : label is "lutpair33"; attribute HLUTNM of \y_int[3]_i_5\ : label is "lutpair36"; attribute HLUTNM of \y_int[3]_i_6\ : label is "lutpair35"; attribute HLUTNM of \y_int[3]_i_7\ : label is "lutpair34"; attribute HLUTNM of \y_int[3]_i_8\ : label is "lutpair33"; attribute HLUTNM of \y_int[7]_i_3\ : label is "lutpair38"; attribute HLUTNM of \y_int[7]_i_4\ : label is "lutpair37"; attribute HLUTNM of \y_int[7]_i_5\ : label is "lutpair36"; attribute HLUTNM of \y_int[7]_i_8\ : label is "lutpair38"; attribute HLUTNM of \y_int[7]_i_9\ : label is "lutpair37"; begin CO(0) <= \^co\(0); DI(0) <= \^di\(0); O(1 downto 0) <= \^o\(1 downto 0); \cb_int_reg[3]_0\(3 downto 0) <= \^cb_int_reg[3]_0\(3 downto 0); \cr_int_reg[11]_0\(3 downto 0) <= \^cr_int_reg[11]_0\(3 downto 0); \cr_int_reg[15]_0\(3 downto 0) <= \^cr_int_reg[15]_0\(3 downto 0); \cr_int_reg[19]_0\(3 downto 0) <= \^cr_int_reg[19]_0\(3 downto 0); \cr_int_reg[23]_0\(3 downto 0) <= \^cr_int_reg[23]_0\(3 downto 0); \cr_int_reg[23]_1\(0) <= \^cr_int_reg[23]_1\(0); \cr_int_reg[27]_0\ <= \^cr_int_reg[27]_0\; \cr_int_reg[27]_1\(1 downto 0) <= \^cr_int_reg[27]_1\(1 downto 0); \cr_int_reg[27]_2\(0) <= \^cr_int_reg[27]_2\(0); \cr_int_reg[31]_0\ <= \^cr_int_reg[31]_0\; \cr_int_reg[31]_1\ <= \^cr_int_reg[31]_1\; \cr_int_reg[31]_2\(1 downto 0) <= \^cr_int_reg[31]_2\(1 downto 0); \cr_int_reg[3]_0\(2 downto 0) <= \^cr_int_reg[3]_0\(2 downto 0); \cr_int_reg[3]_1\(0) <= \^cr_int_reg[3]_1\(0); \cr_int_reg[3]_2\(1 downto 0) <= \^cr_int_reg[3]_2\(1 downto 0); \cr_int_reg[7]_0\(3 downto 0) <= \^cr_int_reg[7]_0\(3 downto 0); \cr_int_reg[7]_1\(3 downto 0) <= \^cr_int_reg[7]_1\(3 downto 0); \y_int_reg[15]_0\(3 downto 0) <= \^y_int_reg[15]_0\(3 downto 0); \y_int_reg[19]_0\(3 downto 0) <= \^y_int_reg[19]_0\(3 downto 0); \y_int_reg[23]_0\(0) <= \^y_int_reg[23]_0\(0); \y_int_reg[23]_1\(1 downto 0) <= \^y_int_reg[23]_1\(1 downto 0); \y_int_reg[23]_2\(3 downto 0) <= \^y_int_reg[23]_2\(3 downto 0); \y_int_reg[3]_0\(3 downto 0) <= \^y_int_reg[3]_0\(3 downto 0); \y_int_reg[3]_1\(0) <= \^y_int_reg[3]_1\(0); \y_int_reg[7]_0\(0) <= \^y_int_reg[7]_0\(0); Inst_i2c_sender: entity work.system_zed_hdmi_0_0_i2c_sender port map ( clk_100 => clk_100, hdmi_scl => hdmi_scl, hdmi_sda => hdmi_sda ); ODDR_inst: unisim.vcomponents.ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0', IS_C_INVERTED => '0', IS_D1_INVERTED => '0', IS_D2_INVERTED => '0', SRTYPE => "SYNC" ) port map ( C => clk_x2, CE => '1', D1 => D1, D2 => D1, Q => hdmi_clk, R => NLW_ODDR_inst_R_UNCONNECTED, S => NLW_ODDR_inst_S_UNCONNECTED ); \cb[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[0]\, I1 => \cb_int_reg__0\(31), O => \cb[0]_i_1_n_0\ ); \cb[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[1]\, I1 => \cb_int_reg__0\(31), O => \cb[1]_i_1_n_0\ ); \cb[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[2]\, I1 => \cb_int_reg__0\(31), O => \cb[2]_i_1_n_0\ ); \cb[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[3]\, I1 => \cb_int_reg__0\(31), O => \cb[3]_i_1_n_0\ ); \cb[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[4]\, I1 => \cb_int_reg__0\(31), O => \cb[4]_i_1_n_0\ ); \cb[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[5]\, I1 => \cb_int_reg__0\(31), O => \cb[5]_i_1_n_0\ ); \cb[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[6]\, I1 => \cb_int_reg__0\(31), O => \cb[6]_i_1_n_0\ ); \cb[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(26), I1 => \cb_int_reg__0\(27), O => \cb[7]_i_10_n_0\ ); \cb[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(24), I1 => \cb_int_reg__0\(25), O => \cb[7]_i_11_n_0\ ); \cb[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(22), I1 => \cb_int_reg__0\(23), O => \cb[7]_i_13_n_0\ ); \cb[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(20), I1 => \cb_int_reg__0\(21), O => \cb[7]_i_14_n_0\ ); \cb[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(18), I1 => \cb_int_reg__0\(19), O => \cb[7]_i_15_n_0\ ); \cb[7]_i_16\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(16), I1 => \cb_int_reg__0\(17), O => \cb[7]_i_16_n_0\ ); \cb[7]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(22), I1 => \cb_int_reg__0\(23), O => \cb[7]_i_17_n_0\ ); \cb[7]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(20), I1 => \cb_int_reg__0\(21), O => \cb[7]_i_18_n_0\ ); \cb[7]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(18), I1 => \cb_int_reg__0\(19), O => \cb[7]_i_19_n_0\ ); \cb[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg_n_0_[7]\, I1 => \cb_int_reg__0\(31), O => \cb[7]_i_2_n_0\ ); \cb[7]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(16), I1 => \cb_int_reg__0\(17), O => \cb[7]_i_20_n_0\ ); \cb[7]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(14), I1 => \cb_int_reg__0\(15), O => \cb[7]_i_21_n_0\ ); \cb[7]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(12), I1 => \cb_int_reg__0\(13), O => \cb[7]_i_22_n_0\ ); \cb[7]_i_23\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(10), I1 => \cb_int_reg__0\(11), O => \cb[7]_i_23_n_0\ ); \cb[7]_i_24\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(8), I1 => \cb_int_reg__0\(9), O => \cb[7]_i_24_n_0\ ); \cb[7]_i_25\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(14), I1 => \cb_int_reg__0\(15), O => \cb[7]_i_25_n_0\ ); \cb[7]_i_26\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(12), I1 => \cb_int_reg__0\(13), O => \cb[7]_i_26_n_0\ ); \cb[7]_i_27\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(10), I1 => \cb_int_reg__0\(11), O => \cb[7]_i_27_n_0\ ); \cb[7]_i_28\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(8), I1 => \cb_int_reg__0\(9), O => \cb[7]_i_28_n_0\ ); \cb[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg__0\(30), I1 => \cb_int_reg__0\(31), O => \cb[7]_i_4_n_0\ ); \cb[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(28), I1 => \cb_int_reg__0\(29), O => \cb[7]_i_5_n_0\ ); \cb[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(26), I1 => \cb_int_reg__0\(27), O => \cb[7]_i_6_n_0\ ); \cb[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg__0\(24), I1 => \cb_int_reg__0\(25), O => \cb[7]_i_7_n_0\ ); \cb[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(30), I1 => \cb_int_reg__0\(31), O => \cb[7]_i_8_n_0\ ); \cb[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg__0\(28), I1 => \cb_int_reg__0\(29), O => \cb[7]_i_9_n_0\ ); \cb_hold[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => edge, I1 => edge_rb, O => \cb_hold[7]_i_1_n_0\ ); \cb_hold_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(0), Q => cb_hold(0), R => '0' ); \cb_hold_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(1), Q => cb_hold(1), R => '0' ); \cb_hold_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(2), Q => cb_hold(2), R => '0' ); \cb_hold_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(3), Q => cb_hold(3), R => '0' ); \cb_hold_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(4), Q => cb_hold(4), R => '0' ); \cb_hold_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(5), Q => cb_hold(5), R => '0' ); \cb_hold_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(6), Q => cb_hold(6), R => '0' ); \cb_hold_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cb(7), Q => cb_hold(7), R => '0' ); \cb_int[11]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(10), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(18), I3 => cb_int_reg8, I4 => \cb_int[15]_i_25_n_0\, I5 => cb_int_reg2(10), O => \cb_int[11]_i_10_n_0\ ); \cb_int[11]_i_100\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_16_n_6\, I1 => \cb_int_reg[3]_i_16_n_5\, O => \cb_int[11]_i_100_n_0\ ); \cb_int[11]_i_101\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_26_n_4\, I1 => \cb_int_reg[3]_i_16_n_7\, O => \cb_int[11]_i_101_n_0\ ); \cb_int[11]_i_102\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_26_n_6\, I1 => \cb_int_reg[3]_i_26_n_5\, O => \cb_int[11]_i_102_n_0\ ); \cb_int[11]_i_103\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_7\, I1 => \cb_int_reg[3]_i_16_n_4\, O => \cb_int[11]_i_103_n_0\ ); \cb_int[11]_i_104\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_5\, I1 => \cb_int_reg[3]_i_16_n_6\, O => \cb_int[11]_i_104_n_0\ ); \cb_int[11]_i_105\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_7\, I1 => \cb_int_reg[3]_i_26_n_4\, O => \cb_int[11]_i_105_n_0\ ); \cb_int[11]_i_106\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_26_n_5\, I1 => \cb_int_reg[3]_i_26_n_6\, O => \cb_int[11]_i_106_n_0\ ); \cb_int[11]_i_107\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_20_n_7\, I1 => \cb_int_reg[3]_i_20_n_6\, O => \cb_int[11]_i_107_n_0\ ); \cb_int[11]_i_108\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_44_n_7\, I1 => \cb_int_reg[3]_i_44_n_6\, O => \cb_int[11]_i_108_n_0\ ); \cb_int[11]_i_109\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_75_n_5\, I1 => \cb_int_reg[3]_i_75_n_4\, O => \cb_int[11]_i_109_n_0\ ); \cb_int[11]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(9), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(17), I3 => cb_int_reg8, I4 => \cb_int[11]_i_20_n_0\, I5 => cb_int_reg2(9), O => \cb_int[11]_i_11_n_0\ ); \cb_int[11]_i_110\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_75_n_7\, I1 => \cb_int_reg[3]_i_75_n_6\, O => \cb_int[11]_i_110_n_0\ ); \cb_int[11]_i_111\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_6\, I1 => \cb_int_reg[3]_i_20_n_7\, O => \cb_int[11]_i_111_n_0\ ); \cb_int[11]_i_112\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_44_n_6\, I1 => \cb_int_reg[3]_i_44_n_7\, O => \cb_int[11]_i_112_n_0\ ); \cb_int[11]_i_113\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_4\, I1 => \cb_int_reg[3]_i_75_n_5\, O => \cb_int[11]_i_113_n_0\ ); \cb_int[11]_i_114\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_6\, I1 => \cb_int_reg[3]_i_75_n_7\, O => \cb_int[11]_i_114_n_0\ ); \cb_int[11]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(9), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(17), I3 => cb_int_reg8, I4 => \cb_int[11]_i_20_n_0\, I5 => cb_int_reg2(9), O => \cb_int[11]_i_12_n_0\ ); \cb_int[11]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(8), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(16), I3 => cb_int_reg8, I4 => \cb_int[11]_i_22_n_0\, I5 => cb_int_reg2(8), O => \cb_int[11]_i_13_n_0\ ); \cb_int[11]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(8), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(16), I3 => cb_int_reg8, I4 => \cb_int[11]_i_22_n_0\, I5 => cb_int_reg2(8), O => \cb_int[11]_i_14_n_0\ ); \cb_int[11]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFE200E2" ) port map ( I0 => \cb_int_reg[11]_i_24_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(1), I3 => \rgb888[0]\(3), I4 => cb_int_reg3(7), I5 => \cb_int[11]_i_27_n_0\, O => \cb_int[11]_i_15_n_0\ ); \cb_int[11]_i_19\: unisim.vcomponents.LUT6 generic map( INIT => X"FFE200E2001DFF1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(1), I3 => \rgb888[0]\(3), I4 => cb_int_reg3(7), I5 => \cb_int[11]_i_27_n_0\, O => \cb_int[11]_i_19_n_0\ ); \cb_int[11]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[11]_i_10_n_0\, I1 => \cb_int[11]_i_11_n_0\, O => \cb_int[11]_i_2_n_0\ ); \cb_int[11]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_4\(0), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]_0\(0), O => \cb_int[11]_i_20_n_0\ ); \cb_int[11]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(9), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_4\(0), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(9) ); \cb_int[11]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_3\(3), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]\(3), O => \cb_int[11]_i_22_n_0\ ); \cb_int[11]_i_23\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(8), I1 => \rgb888[0]\(3), I2 => \rgb888[0]\(2), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[11]_i_24_n_4\, O => cb_int_reg2(8) ); \cb_int[11]_i_27\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_3\(2), I1 => \rgb888[8]_1\(1), I2 => \rgb888[12]\(2), I3 => \^co\(0), I4 => \rgb888[8]_1\(0), O => \cb_int[11]_i_27_n_0\ ); \cb_int[11]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(16), O => \cb_int[11]_i_29_n_0\ ); \cb_int[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[11]_i_12_n_0\, I1 => \cb_int[11]_i_13_n_0\, O => \cb_int[11]_i_3_n_0\ ); \cb_int[11]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(15), O => \cb_int[11]_i_30_n_0\ ); \cb_int[11]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(14), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_12_n_6\, O => \cb_int[11]_i_31_n_0\ ); \cb_int[11]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(13), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_12_n_7\, O => \cb_int[11]_i_32_n_0\ ); \cb_int[11]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_34_n_0\ ); \cb_int[11]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_35_n_0\ ); \cb_int[11]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_36_n_0\ ); \cb_int[11]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_37_n_0\ ); \cb_int[11]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_39_n_0\ ); \cb_int[11]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[11]_i_14_n_0\, I1 => \cb_int[11]_i_15_n_0\, O => \cb_int[11]_i_4_n_0\ ); \cb_int[11]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_40_n_0\ ); \cb_int[11]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_41_n_0\ ); \cb_int[11]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_42_n_0\ ); \cb_int[11]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_43_n_0\ ); \cb_int[11]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(2), O => \cb_int[11]_i_44_n_0\ ); \cb_int[11]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(1), O => \cb_int[11]_i_45_n_0\ ); \cb_int[11]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(0), O => \cb_int[11]_i_46_n_0\ ); \cb_int[11]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(3), O => \cb_int[11]_i_47_n_0\ ); \cb_int[11]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_49_n_0\ ); \cb_int[11]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"DD1D0000" ) port map ( I0 => cb_int_reg5(7), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(15), I3 => cb_int_reg8, I4 => \cb_int[11]_i_19_n_0\, O => \cb_int[11]_i_5_n_0\ ); \cb_int[11]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_50_n_0\ ); \cb_int[11]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_51_n_0\ ); \cb_int[11]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_52_n_0\ ); \cb_int[11]_i_53\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_4\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(2), O => \cb_int[11]_i_53_n_0\ ); \cb_int[11]_i_54\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(1), O => \cb_int[11]_i_54_n_0\ ); \cb_int[11]_i_55\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_6\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]\(0), O => \cb_int[11]_i_55_n_0\ ); \cb_int[11]_i_56\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[11]_i_24_n_7\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_0\(3), O => \cb_int[11]_i_56_n_0\ ); \cb_int[11]_i_57\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(8), I1 => cb_int_reg8, I2 => \cb_int_reg[3]_i_16_n_4\, O => \cb_int[11]_i_57_n_0\ ); \cb_int[11]_i_58\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(12), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_4\, O => \cb_int[11]_i_58_n_0\ ); \cb_int[11]_i_59\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(11), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_5\, O => \cb_int[11]_i_59_n_0\ ); \cb_int[11]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[15]_i_16_n_0\, I1 => \cb_int[15]_i_17_n_0\, I2 => \cb_int[11]_i_2_n_0\, O => \cb_int[11]_i_6_n_0\ ); \cb_int[11]_i_60\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(10), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_6\, O => \cb_int[11]_i_60_n_0\ ); \cb_int[11]_i_61\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cb_int_reg7(9), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_7\, O => \cb_int[11]_i_61_n_0\ ); \cb_int[11]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_6\, O => \cb_int[11]_i_62_n_0\ ); \cb_int[11]_i_63\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_7\, O => \cb_int[11]_i_63_n_0\ ); \cb_int[11]_i_64\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_4\, O => \cb_int[11]_i_64_n_0\ ); \cb_int[11]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_5\, O => \cb_int[11]_i_65_n_0\ ); \cb_int[11]_i_67\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_67_n_0\ ); \cb_int[11]_i_68\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_68_n_0\ ); \cb_int[11]_i_69\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_69_n_0\ ); \cb_int[11]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[11]_i_10_n_0\, I1 => \cb_int[11]_i_11_n_0\, I2 => \cb_int[11]_i_3_n_0\, O => \cb_int[11]_i_7_n_0\ ); \cb_int[11]_i_70\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_70_n_0\ ); \cb_int[11]_i_71\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_71_n_0\ ); \cb_int[11]_i_72\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_72_n_0\ ); \cb_int[11]_i_73\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_73_n_0\ ); \cb_int[11]_i_74\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_74_n_0\ ); \cb_int[11]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[0]\(2), I1 => \rgb888[0]\(3), O => \cb_int[11]_i_76_n_0\ ); \cb_int[11]_i_77\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_77_n_0\ ); \cb_int[11]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_78_n_0\ ); \cb_int[11]_i_79\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), O => \cb_int[11]_i_79_n_0\ ); \cb_int[11]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[11]_i_12_n_0\, I1 => \cb_int[11]_i_13_n_0\, I2 => \cb_int[11]_i_4_n_0\, O => \cb_int[11]_i_8_n_0\ ); \cb_int[11]_i_80\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(3), I1 => \rgb888[0]\(2), O => \cb_int[11]_i_80_n_0\ ); \cb_int[11]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_82_n_0\ ); \cb_int[11]_i_83\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_6\, I1 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_83_n_0\ ); \cb_int[11]_i_84\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[31]_i_33_n_4\, I1 => \cb_int_reg[31]_i_12_n_7\, O => \cb_int[11]_i_84_n_0\ ); \cb_int[11]_i_85\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[31]_i_33_n_6\, I1 => \cb_int_reg[31]_i_33_n_5\, O => \cb_int[11]_i_85_n_0\ ); \cb_int[11]_i_86\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[11]_i_86_n_0\ ); \cb_int[11]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => \cb_int_reg[31]_i_12_n_6\, O => \cb_int[11]_i_87_n_0\ ); \cb_int[11]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_12_n_7\, I1 => \cb_int_reg[31]_i_33_n_4\, O => \cb_int[11]_i_88_n_0\ ); \cb_int[11]_i_89\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_5\, I1 => \cb_int_reg[31]_i_33_n_6\, O => \cb_int[11]_i_89_n_0\ ); \cb_int[11]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[11]_i_14_n_0\, I1 => \cb_int[11]_i_15_n_0\, I2 => \cb_int[11]_i_5_n_0\, O => \cb_int[11]_i_9_n_0\ ); \cb_int[11]_i_91\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[0]\(0), I1 => \rgb888[0]\(1), O => \cb_int[11]_i_91_n_0\ ); \cb_int[11]_i_92\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[0]_0\(2), I1 => \rgb888[0]_0\(3), O => \cb_int[11]_i_92_n_0\ ); \cb_int[11]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[0]_0\(0), I1 => \rgb888[0]_0\(1), O => \cb_int[11]_i_93_n_0\ ); \cb_int[11]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_20_n_5\, I1 => \cb_int_reg[3]_i_20_n_4\, O => \cb_int[11]_i_94_n_0\ ); \cb_int[11]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]\(1), I1 => \rgb888[0]\(0), O => \cb_int[11]_i_95_n_0\ ); \cb_int[11]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(3), I1 => \rgb888[0]_0\(2), O => \cb_int[11]_i_96_n_0\ ); \cb_int[11]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(1), I1 => \rgb888[0]_0\(0), O => \cb_int[11]_i_97_n_0\ ); \cb_int[11]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_4\, I1 => \cb_int_reg[3]_i_20_n_5\, O => \cb_int[11]_i_98_n_0\ ); \cb_int[11]_i_99\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cb_int_reg[3]_i_16_n_4\, I1 => \cb_int_reg[31]_i_33_n_7\, O => \cb_int[11]_i_99_n_0\ ); \cb_int[15]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(14), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(22), I3 => cb_int_reg8, I4 => \cb_int[19]_i_26_n_0\, I5 => cb_int_reg2(14), O => \cb_int[15]_i_10_n_0\ ); \cb_int[15]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(13), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(21), I3 => cb_int_reg8, I4 => \cb_int[15]_i_18_n_0\, I5 => cb_int_reg2(13), O => \cb_int[15]_i_11_n_0\ ); \cb_int[15]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(13), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(21), I3 => cb_int_reg8, I4 => \cb_int[15]_i_18_n_0\, I5 => cb_int_reg2(13), O => \cb_int[15]_i_12_n_0\ ); \cb_int[15]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(12), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(20), I3 => cb_int_reg8, I4 => \cb_int[15]_i_21_n_0\, I5 => cb_int_reg2(12), O => \cb_int[15]_i_13_n_0\ ); \cb_int[15]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(12), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(20), I3 => cb_int_reg8, I4 => \cb_int[15]_i_21_n_0\, I5 => cb_int_reg2(12), O => \cb_int[15]_i_14_n_0\ ); \cb_int[15]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(11), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(19), I3 => cb_int_reg8, I4 => \cb_int[15]_i_23_n_0\, I5 => cb_int_reg2(11), O => \cb_int[15]_i_15_n_0\ ); \cb_int[15]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(11), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(19), I3 => cb_int_reg8, I4 => \cb_int[15]_i_23_n_0\, I5 => cb_int_reg2(11), O => \cb_int[15]_i_16_n_0\ ); \cb_int[15]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(10), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(18), I3 => cb_int_reg8, I4 => \cb_int[15]_i_25_n_0\, I5 => cb_int_reg2(10), O => \cb_int[15]_i_17_n_0\ ); \cb_int[15]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_5\(0), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_6\(0), O => \cb_int[15]_i_18_n_0\ ); \cb_int[15]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(13), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_3\(0), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(13) ); \cb_int[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[15]_i_10_n_0\, I1 => \cb_int[15]_i_11_n_0\, O => \cb_int[15]_i_2_n_0\ ); \cb_int[15]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_4\(3), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]_0\(3), O => \cb_int[15]_i_21_n_0\ ); \cb_int[15]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(12), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_4\(3), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(12) ); \cb_int[15]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_4\(2), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]_0\(2), O => \cb_int[15]_i_23_n_0\ ); \cb_int[15]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(11), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_4\(2), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(11) ); \cb_int[15]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_4\(1), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[12]_0\(1), O => \cb_int[15]_i_25_n_0\ ); \cb_int[15]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(10), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_4\(1), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(10) ); \cb_int[15]_i_27\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(20), O => \cb_int[15]_i_27_n_0\ ); \cb_int[15]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(19), O => \cb_int[15]_i_28_n_0\ ); \cb_int[15]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(18), O => \cb_int[15]_i_29_n_0\ ); \cb_int[15]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[15]_i_12_n_0\, I1 => \cb_int[15]_i_13_n_0\, O => \cb_int[15]_i_3_n_0\ ); \cb_int[15]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(17), O => \cb_int[15]_i_30_n_0\ ); \cb_int[15]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[15]_i_14_n_0\, I1 => \cb_int[15]_i_15_n_0\, O => \cb_int[15]_i_4_n_0\ ); \cb_int[15]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_4\(3), O => \cb_int[15]_i_43_n_0\ ); \cb_int[15]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_4\(2), O => \cb_int[15]_i_44_n_0\ ); \cb_int[15]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_4\(1), O => \cb_int[15]_i_45_n_0\ ); \cb_int[15]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_4\(0), O => \cb_int[15]_i_46_n_0\ ); \cb_int[15]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[15]_i_16_n_0\, I1 => \cb_int[15]_i_17_n_0\, O => \cb_int[15]_i_5_n_0\ ); \cb_int[15]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[19]_i_16_n_0\, I1 => \cb_int[19]_i_17_n_0\, I2 => \cb_int[15]_i_2_n_0\, O => \cb_int[15]_i_6_n_0\ ); \cb_int[15]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[15]_i_10_n_0\, I1 => \cb_int[15]_i_11_n_0\, I2 => \cb_int[15]_i_3_n_0\, O => \cb_int[15]_i_7_n_0\ ); \cb_int[15]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[15]_i_12_n_0\, I1 => \cb_int[15]_i_13_n_0\, I2 => \cb_int[15]_i_4_n_0\, O => \cb_int[15]_i_8_n_0\ ); \cb_int[15]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[15]_i_14_n_0\, I1 => \cb_int[15]_i_15_n_0\, I2 => \cb_int[15]_i_5_n_0\, O => \cb_int[15]_i_9_n_0\ ); \cb_int[19]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(18), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(26), I3 => cb_int_reg8, I4 => \cb_int[23]_i_25_n_0\, I5 => cb_int_reg2(18), O => \cb_int[19]_i_10_n_0\ ); \cb_int[19]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(17), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(25), I3 => cb_int_reg8, I4 => \cb_int[19]_i_18_n_0\, I5 => cb_int_reg2(17), O => \cb_int[19]_i_11_n_0\ ); \cb_int[19]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(17), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(25), I3 => cb_int_reg8, I4 => \cb_int[19]_i_18_n_0\, I5 => cb_int_reg2(17), O => \cb_int[19]_i_12_n_0\ ); \cb_int[19]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(16), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(24), I3 => cb_int_reg8, I4 => \cb_int[19]_i_21_n_0\, I5 => cb_int_reg2(16), O => \cb_int[19]_i_13_n_0\ ); \cb_int[19]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(16), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(24), I3 => cb_int_reg8, I4 => \cb_int[19]_i_21_n_0\, I5 => cb_int_reg2(16), O => \cb_int[19]_i_14_n_0\ ); \cb_int[19]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(15), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(23), I3 => cb_int_reg8, I4 => \cb_int[19]_i_23_n_0\, I5 => cb_int_reg2(15), O => \cb_int[19]_i_15_n_0\ ); \cb_int[19]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(15), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(23), I3 => cb_int_reg8, I4 => \cb_int[19]_i_23_n_0\, I5 => cb_int_reg2(15), O => \cb_int[19]_i_16_n_0\ ); \cb_int[19]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(14), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(22), I3 => cb_int_reg8, I4 => \cb_int[19]_i_26_n_0\, I5 => cb_int_reg2(14), O => \cb_int[19]_i_17_n_0\ ); \cb_int[19]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_7\(0), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_8\(0), O => \cb_int[19]_i_18_n_0\ ); \cb_int[19]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(17), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_2\(0), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(17) ); \cb_int[19]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[19]_i_10_n_0\, I1 => \cb_int[19]_i_11_n_0\, O => \cb_int[19]_i_2_n_0\ ); \cb_int[19]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_5\(3), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_6\(3), O => \cb_int[19]_i_21_n_0\ ); \cb_int[19]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(16), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_3\(3), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(16) ); \cb_int[19]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_5\(2), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_6\(2), O => \cb_int[19]_i_23_n_0\ ); \cb_int[19]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(15), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_3\(2), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(15) ); \cb_int[19]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_5\(1), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_6\(1), O => \cb_int[19]_i_26_n_0\ ); \cb_int[19]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(14), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_3\(1), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(14) ); \cb_int[19]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(24), O => \cb_int[19]_i_28_n_0\ ); \cb_int[19]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(23), O => \cb_int[19]_i_29_n_0\ ); \cb_int[19]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[19]_i_12_n_0\, I1 => \cb_int[19]_i_13_n_0\, O => \cb_int[19]_i_3_n_0\ ); \cb_int[19]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(22), O => \cb_int[19]_i_30_n_0\ ); \cb_int[19]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(21), O => \cb_int[19]_i_31_n_0\ ); \cb_int[19]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[19]_i_34_n_0\ ); \cb_int[19]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[19]_i_35_n_0\ ); \cb_int[19]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[19]_i_36_n_0\ ); \cb_int[19]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[19]_i_37_n_0\ ); \cb_int[19]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[19]_i_14_n_0\, I1 => \cb_int[19]_i_15_n_0\, O => \cb_int[19]_i_4_n_0\ ); \cb_int[19]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[19]_i_16_n_0\, I1 => \cb_int[19]_i_17_n_0\, O => \cb_int[19]_i_5_n_0\ ); \cb_int[19]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[23]_i_16_n_0\, I1 => \cb_int[23]_i_17_n_0\, I2 => \cb_int[19]_i_2_n_0\, O => \cb_int[19]_i_6_n_0\ ); \cb_int[19]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[19]_i_10_n_0\, I1 => \cb_int[19]_i_11_n_0\, I2 => \cb_int[19]_i_3_n_0\, O => \cb_int[19]_i_7_n_0\ ); \cb_int[19]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[19]_i_12_n_0\, I1 => \cb_int[19]_i_13_n_0\, I2 => \cb_int[19]_i_4_n_0\, O => \cb_int[19]_i_8_n_0\ ); \cb_int[19]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[19]_i_14_n_0\, I1 => \cb_int[19]_i_15_n_0\, I2 => \cb_int[19]_i_5_n_0\, O => \cb_int[19]_i_9_n_0\ ); \cb_int[23]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(22), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(30), I3 => cb_int_reg8, I4 => \cb_int[27]_i_10_n_0\, I5 => cb_int_reg2(22), O => \cb_int[23]_i_10_n_0\ ); \cb_int[23]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(21), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(29), I3 => cb_int_reg8, I4 => \cb_int[23]_i_18_n_0\, I5 => cb_int_reg2(21), O => \cb_int[23]_i_11_n_0\ ); \cb_int[23]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(21), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(29), I3 => cb_int_reg8, I4 => \cb_int[23]_i_18_n_0\, I5 => cb_int_reg2(21), O => \cb_int[23]_i_12_n_0\ ); \cb_int[23]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(20), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(28), I3 => cb_int_reg8, I4 => \cb_int[23]_i_20_n_0\, I5 => cb_int_reg2(20), O => \cb_int[23]_i_13_n_0\ ); \cb_int[23]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(20), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(28), I3 => cb_int_reg8, I4 => \cb_int[23]_i_20_n_0\, I5 => cb_int_reg2(20), O => \cb_int[23]_i_14_n_0\ ); \cb_int[23]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(19), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(27), I3 => cb_int_reg8, I4 => \cb_int[23]_i_22_n_0\, I5 => cb_int_reg2(19), O => \cb_int[23]_i_15_n_0\ ); \cb_int[23]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"DD1D22E222E2DD1D" ) port map ( I0 => cb_int_reg5(19), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(27), I3 => cb_int_reg8, I4 => \cb_int[23]_i_22_n_0\, I5 => cb_int_reg2(19), O => \cb_int[23]_i_16_n_0\ ); \cb_int[23]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(18), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(26), I3 => cb_int_reg8, I4 => \cb_int[23]_i_25_n_0\, I5 => cb_int_reg2(18), O => \cb_int[23]_i_17_n_0\ ); \cb_int[23]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_9\(0), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_10\(0), O => \cb_int[23]_i_18_n_0\ ); \cb_int[23]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(21), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_1\(0), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(21) ); \cb_int[23]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[23]_i_10_n_0\, I1 => \cb_int[23]_i_11_n_0\, O => \cb_int[23]_i_2_n_0\ ); \cb_int[23]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_7\(3), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_8\(3), O => \cb_int[23]_i_20_n_0\ ); \cb_int[23]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(20), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_2\(3), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(20) ); \cb_int[23]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_7\(2), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_8\(2), O => \cb_int[23]_i_22_n_0\ ); \cb_int[23]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(19), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_2\(2), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(19) ); \cb_int[23]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_7\(1), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_8\(1), O => \cb_int[23]_i_25_n_0\ ); \cb_int[23]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(18), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_2\(1), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(18) ); \cb_int[23]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[23]_i_29_n_0\ ); \cb_int[23]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[23]_i_12_n_0\, I1 => \cb_int[23]_i_13_n_0\, O => \cb_int[23]_i_3_n_0\ ); \cb_int[23]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[23]_i_30_n_0\ ); \cb_int[23]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[23]_i_31_n_0\ ); \cb_int[23]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[23]_i_32_n_0\ ); \cb_int[23]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[23]_i_14_n_0\, I1 => \cb_int[23]_i_15_n_0\, O => \cb_int[23]_i_4_n_0\ ); \cb_int[23]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[23]_i_16_n_0\, I1 => \cb_int[23]_i_17_n_0\, O => \cb_int[23]_i_5_n_0\ ); \cb_int[23]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[27]_i_7_n_0\, I1 => \cb_int[27]_i_8_n_0\, I2 => \cb_int[23]_i_2_n_0\, O => \cb_int[23]_i_6_n_0\ ); \cb_int[23]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[23]_i_10_n_0\, I1 => \cb_int[23]_i_11_n_0\, I2 => \cb_int[23]_i_3_n_0\, O => \cb_int[23]_i_7_n_0\ ); \cb_int[23]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[23]_i_12_n_0\, I1 => \cb_int[23]_i_13_n_0\, I2 => \cb_int[23]_i_4_n_0\, O => \cb_int[23]_i_8_n_0\ ); \cb_int[23]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int[23]_i_14_n_0\, I1 => \cb_int[23]_i_15_n_0\, I2 => \cb_int[23]_i_5_n_0\, O => \cb_int[23]_i_9_n_0\ ); \cb_int[27]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_9\(1), I1 => \rgb888[8]_1\(1), I2 => \^co\(0), I3 => \rgb888[8]_10\(1), O => \cb_int[27]_i_10_n_0\ ); \cb_int[27]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => cb_int_reg3(22), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_1\(1), I3 => \cb_int_reg[11]_i_25_n_0\, O => cb_int_reg2(22) ); \cb_int[27]_i_12\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[27]_i_12_n_0\ ); \cb_int[27]_i_13\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[27]_i_13_n_0\ ); \cb_int[27]_i_14\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[27]_i_14_n_0\ ); \cb_int[27]_i_15\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[27]_i_15_n_0\ ); \cb_int[27]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cb_int[27]_i_7_n_0\, I1 => \cb_int[27]_i_8_n_0\, O => \cb_int[27]_i_2_n_0\ ); \cb_int[27]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_3_n_0\ ); \cb_int[27]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_4_n_0\ ); \cb_int[27]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_5_n_0\ ); \cb_int[27]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[27]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_6_n_0\ ); \cb_int[27]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"1E111E11E1EE1E11" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => \cb_int_reg[31]_i_11_n_1\, I2 => \rgb888[8]_11\(0), I3 => \rgb888[8]_1\(1), I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[27]_i_7_n_0\ ); \cb_int[27]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFDD1DDD1D0000" ) port map ( I0 => cb_int_reg5(22), I1 => \cb_int_reg[31]_i_12_n_1\, I2 => cb_int_reg7(30), I3 => cb_int_reg8, I4 => \cb_int[27]_i_10_n_0\, I5 => cb_int_reg2(22), O => \cb_int[27]_i_8_n_0\ ); \cb_int[31]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \rgb888[8]_11\(0), I1 => \rgb888[8]_1\(1), O => \cb_int[31]_i_13_n_0\ ); \cb_int[31]_i_15\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_1\(1), O => \cb_int[31]_i_15_n_0\ ); \cb_int[31]_i_16\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_1\(0), O => \cb_int[31]_i_16_n_0\ ); \cb_int[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"4404440444040000" ) port map ( I0 => \cb_int_reg[31]_i_7_n_1\, I1 => \rgb888[0]\(3), I2 => \rgb888[8]_1\(1), I3 => \rgb888[8]_11\(0), I4 => \cb_int_reg[31]_i_11_n_1\, I5 => \cb_int_reg[31]_i_12_n_1\, O => \cb_int[31]_i_2_n_0\ ); \cb_int[31]_i_24\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \^di\(0) ); \cb_int[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[31]_i_3_n_0\ ); \cb_int[31]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(30), O => \cb_int[31]_i_31_n_0\ ); \cb_int[31]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(29), O => \cb_int[31]_i_32_n_0\ ); \cb_int[31]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_34_n_2\, O => \cb_int[31]_i_35_n_0\ ); \cb_int[31]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_34_n_2\, O => \cb_int[31]_i_36_n_0\ ); \cb_int[31]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_2\(3), O => \cb_int[31]_i_38_n_0\ ); \cb_int[31]_i_39\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_2\(2), O => \cb_int[31]_i_39_n_0\ ); \cb_int[31]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[31]_i_4_n_0\ ); \cb_int[31]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_2\(1), O => \cb_int[31]_i_40_n_0\ ); \cb_int[31]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_2\(0), O => \cb_int[31]_i_41_n_0\ ); \cb_int[31]_i_43\: unisim.vcomponents.LUT6 generic map( INIT => X"00000001FFFFFFFE" ) port map ( I0 => rgb888(5), I1 => rgb888(3), I2 => rgb888(1), I3 => rgb888(2), I4 => rgb888(4), I5 => rgb888(6), O => \^cr_int_reg[27]_1\(1) ); \cb_int[31]_i_44\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFE" ) port map ( I0 => rgb888(4), I1 => rgb888(2), I2 => rgb888(1), I3 => rgb888(3), I4 => rgb888(5), O => \^cr_int_reg[27]_1\(0) ); \cb_int[31]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[31]_i_5_n_0\ ); \cb_int[31]_i_51\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => rgb888(5), I1 => rgb888(3), I2 => rgb888(1), I3 => rgb888(2), I4 => rgb888(4), I5 => rgb888(6), O => \^cr_int_reg[27]_0\ ); \cb_int[31]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"55565556A9555556" ) port map ( I0 => \cb_int[31]_i_2_n_0\, I1 => \cb_int_reg[31]_i_12_n_1\, I2 => \cb_int_reg[31]_i_11_n_1\, I3 => \cb_int[31]_i_13_n_0\, I4 => \rgb888[0]\(3), I5 => \cb_int_reg[31]_i_7_n_1\, O => \cb_int[31]_i_6_n_0\ ); \cb_int[31]_i_67\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(28), O => \cb_int[31]_i_67_n_0\ ); \cb_int[31]_i_68\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(27), O => \cb_int[31]_i_68_n_0\ ); \cb_int[31]_i_69\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(26), O => \cb_int[31]_i_69_n_0\ ); \cb_int[31]_i_70\: unisim.vcomponents.LUT3 generic map( INIT => X"8B" ) port map ( I0 => \cb_int_reg[31]_i_12_n_1\, I1 => cb_int_reg8, I2 => cb_int_reg7(25), O => \cb_int[31]_i_70_n_0\ ); \cb_int[31]_i_71\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \cb_int_reg[31]_i_73_n_5\, I1 => rgb888(23), I2 => rgb888(22), O => \cb_int[31]_i_71_n_0\ ); \cb_int[31]_i_72\: unisim.vcomponents.LUT3 generic map( INIT => X"82" ) port map ( I0 => \cb_int_reg[31]_i_73_n_6\, I1 => rgb888(23), I2 => rgb888(22), O => \cb_int[31]_i_72_n_0\ ); \cb_int[31]_i_74\: unisim.vcomponents.LUT4 generic map( INIT => X"1FE0" ) port map ( I0 => rgb888(22), I1 => rgb888(23), I2 => \cb_int_reg[31]_i_73_n_4\, I3 => \cb_int_reg[31]_i_34_n_7\, O => \cb_int[31]_i_74_n_0\ ); \cb_int[31]_i_75\: unisim.vcomponents.LUT4 generic map( INIT => X"3336" ) port map ( I0 => \cb_int_reg[31]_i_73_n_5\, I1 => \cb_int_reg[31]_i_73_n_4\, I2 => rgb888(22), I3 => rgb888(23), O => \cb_int[31]_i_75_n_0\ ); \cb_int[31]_i_76\: unisim.vcomponents.LUT4 generic map( INIT => X"7E81" ) port map ( I0 => \cb_int_reg[31]_i_73_n_6\, I1 => rgb888(22), I2 => rgb888(23), I3 => \cb_int_reg[31]_i_73_n_5\, O => \cb_int[31]_i_76_n_0\ ); \cb_int[31]_i_77\: unisim.vcomponents.LUT4 generic map( INIT => X"9669" ) port map ( I0 => \cb_int_reg[31]_i_73_n_7\, I1 => \cb_int_reg[31]_i_73_n_6\, I2 => rgb888(22), I3 => rgb888(23), O => \cb_int[31]_i_77_n_0\ ); \cb_int[31]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(23), O => \cb_int[31]_i_78_n_0\ ); \cb_int[31]_i_79\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_3\(3), O => \cb_int[31]_i_79_n_0\ ); \cb_int[31]_i_80\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_3\(2), O => \cb_int[31]_i_80_n_0\ ); \cb_int[31]_i_81\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_3\(1), O => \cb_int[31]_i_81_n_0\ ); \cb_int[31]_i_82\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[0]\(3), I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_3\(0), O => \cb_int[31]_i_82_n_0\ ); \cb_int[31]_i_86\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => rgb888(11), I1 => rgb888(10), I2 => rgb888(12), I3 => rgb888(13), O => \^cr_int_reg[31]_1\ ); \cb_int[31]_i_87\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => rgb888(12), I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(13), I4 => rgb888(14), O => \^cr_int_reg[31]_0\ ); \cb_int[31]_i_95\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(22), O => \cb_int[31]_i_95_n_0\ ); \cb_int[31]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(23), I1 => rgb888(21), O => \cb_int[31]_i_96_n_0\ ); \cb_int[31]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(22), I1 => rgb888(20), O => \cb_int[31]_i_97_n_0\ ); \cb_int[31]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(21), I1 => rgb888(19), O => \cb_int[31]_i_98_n_0\ ); \cb_int[3]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_2\(1), I1 => \rgb888[8]_1\(1), I2 => \rgb888[13]_0\(1), I3 => \^co\(0), I4 => \rgb888[8]\(3), O => \cb_int[3]_i_10_n_0\ ); \cb_int[3]_i_100\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(0), I1 => rgb888(2), O => \cb_int[3]_i_100_n_0\ ); \cb_int[3]_i_101\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), O => \cb_int[3]_i_101_n_0\ ); \cb_int[3]_i_102\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(0), O => \cb_int[3]_i_102_n_0\ ); \cb_int[3]_i_103\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(8), I1 => rgb888(11), O => \cb_int[3]_i_103_n_0\ ); \cb_int[3]_i_104\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(10), O => \cb_int[3]_i_104_n_0\ ); \cb_int[3]_i_105\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(9), O => \cb_int[3]_i_105_n_0\ ); \cb_int[3]_i_106\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(8), O => \cb_int[3]_i_106_n_0\ ); \cb_int[3]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(2), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_0\(0), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[7]_i_29_n_6\, O => cb_int_reg2(2) ); \cb_int[3]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(9), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_7\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(1), O => \cb_int[3]_i_12_n_0\ ); \cb_int[3]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_2\(0), I1 => \rgb888[8]_1\(1), I2 => \rgb888[13]_0\(0), I3 => \^co\(0), I4 => \rgb888[8]\(2), O => \cb_int[3]_i_13_n_0\ ); \cb_int[3]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(1), I1 => \rgb888[0]\(3), I2 => \cb_int_reg[3]_i_20_n_4\, I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[7]_i_29_n_7\, O => cb_int_reg2(1) ); \cb_int[3]_i_17\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \rgb888[8]\(1), I1 => \^co\(0), I2 => \rgb888[13]\(0), O => \cb_int[3]_i_17_n_0\ ); \cb_int[3]_i_18\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cb_int_reg[3]_i_20_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \cb_int_reg[3]_i_33_n_4\, O => \cb_int[3]_i_18_n_0\ ); \cb_int[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[3]_i_9_n_0\, I1 => \cb_int[3]_i_10_n_0\, I2 => cb_int_reg2(2), O => \cb_int[3]_i_2_n_0\ ); \cb_int[3]_i_22\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_6\, O => \cb_int[3]_i_22_n_0\ ); \cb_int[3]_i_23\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_33_n_7\, O => \cb_int[3]_i_23_n_0\ ); \cb_int[3]_i_24\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_4\, O => \cb_int[3]_i_24_n_0\ ); \cb_int[3]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_5\, O => \cb_int[3]_i_25_n_0\ ); \cb_int[3]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_73_n_7\, O => \cb_int[3]_i_27_n_0\ ); \cb_int[3]_i_28\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cb_int_reg[31]_i_73_n_7\, I1 => rgb888(22), O => \cb_int[3]_i_28_n_0\ ); \cb_int[3]_i_29\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(21), I1 => \cb_int_reg[3]_i_57_n_4\, O => \cb_int[3]_i_29_n_0\ ); \cb_int[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[3]_i_12_n_0\, I1 => \cb_int[3]_i_13_n_0\, I2 => cb_int_reg2(1), O => \cb_int[3]_i_3_n_0\ ); \cb_int[3]_i_30\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(20), I1 => \cb_int_reg[3]_i_57_n_5\, O => \cb_int[3]_i_30_n_0\ ); \cb_int[3]_i_31\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(19), I1 => \cb_int_reg[3]_i_57_n_6\, O => \cb_int[3]_i_31_n_0\ ); \cb_int[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"1DFF001D" ) port map ( I0 => cb_int_reg7(8), I1 => cb_int_reg8, I2 => \cb_int_reg[3]_i_16_n_4\, I3 => \cb_int[3]_i_17_n_0\, I4 => \cb_int[3]_i_18_n_0\, O => \cb_int[3]_i_4_n_0\ ); \cb_int[3]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(2), I1 => rgb888(1), I2 => \rgb888[0]_8\(1), O => \cb_int[3]_i_45_n_0\ ); \cb_int[3]_i_46\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \rgb888[0]_8\(0), I1 => rgb888(1), O => \cb_int[3]_i_46_n_0\ ); \cb_int[3]_i_47\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cb_int_reg[3]_i_44_n_4\, I1 => rgb888(0), O => \cb_int[3]_i_47_n_0\ ); \cb_int[3]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[3]_i_44_n_5\, O => \cb_int[3]_i_48_n_0\ ); \cb_int[3]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_26_n_6\, O => \cb_int[3]_i_49_n_0\ ); \cb_int[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[7]_i_16_n_0\, I1 => \cb_int[7]_i_17_n_0\, I2 => cb_int_reg2(3), I3 => \cb_int[3]_i_2_n_0\, O => \cb_int[3]_i_5_n_0\ ); \cb_int[3]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_6\, O => \cb_int[3]_i_50_n_0\ ); \cb_int[3]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_16_n_7\, O => \cb_int[3]_i_51_n_0\ ); \cb_int[3]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_26_n_4\, O => \cb_int[3]_i_52_n_0\ ); \cb_int[3]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_26_n_5\, O => \cb_int[3]_i_53_n_0\ ); \cb_int[3]_i_54\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(18), I1 => \cb_int_reg[3]_i_57_n_7\, O => \cb_int[3]_i_54_n_0\ ); \cb_int[3]_i_55\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(17), I1 => rgb888(16), O => \cb_int[3]_i_55_n_0\ ); \cb_int[3]_i_56\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(16), O => \cb_int[3]_i_56_n_0\ ); \cb_int[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[3]_i_9_n_0\, I1 => \cb_int[3]_i_10_n_0\, I2 => cb_int_reg2(2), I3 => \cb_int[3]_i_3_n_0\, O => \cb_int[3]_i_6_n_0\ ); \cb_int[3]_i_64\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_5\, O => \cb_int[3]_i_64_n_0\ ); \cb_int[3]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_6\, O => \cb_int[3]_i_65_n_0\ ); \cb_int[3]_i_66\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_7\, O => \cb_int[3]_i_66_n_0\ ); \cb_int[3]_i_67\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_44_n_6\, O => \cb_int[3]_i_67_n_0\ ); \cb_int[3]_i_69\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(8), I1 => rgb888(10), I2 => \rgb888[8]_31\(2), O => \cb_int[3]_i_69_n_0\ ); \cb_int[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[3]_i_12_n_0\, I1 => \cb_int[3]_i_13_n_0\, I2 => cb_int_reg2(1), I3 => \cb_int[3]_i_4_n_0\, O => \cb_int[3]_i_7_n_0\ ); \cb_int[3]_i_70\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_31\(1), I1 => rgb888(9), O => \cb_int[3]_i_70_n_0\ ); \cb_int[3]_i_71\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_31\(0), I1 => rgb888(8), O => \cb_int[3]_i_71_n_0\ ); \cb_int[3]_i_72\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cb_int_reg[3]_i_94_n_4\, O => \cb_int[3]_i_72_n_0\ ); \cb_int[3]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(7), I1 => rgb888(5), O => \cb_int[3]_i_76_n_0\ ); \cb_int[3]_i_77\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(6), I1 => rgb888(4), O => \cb_int[3]_i_77_n_0\ ); \cb_int[3]_i_78\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(5), I1 => rgb888(3), O => \cb_int[3]_i_78_n_0\ ); \cb_int[3]_i_79\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(4), I1 => rgb888(2), O => \cb_int[3]_i_79_n_0\ ); \cb_int[3]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"1DE2E21D" ) port map ( I0 => cb_int_reg7(8), I1 => cb_int_reg8, I2 => \cb_int_reg[3]_i_16_n_4\, I3 => \cb_int[3]_i_17_n_0\, I4 => \cb_int[3]_i_18_n_0\, O => \cb_int[3]_i_8_n_0\ ); \cb_int[3]_i_80\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(20), I1 => rgb888(18), O => \cb_int[3]_i_80_n_0\ ); \cb_int[3]_i_81\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(19), I1 => rgb888(17), O => \cb_int[3]_i_81_n_0\ ); \cb_int[3]_i_82\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(18), I1 => rgb888(16), O => \cb_int[3]_i_82_n_0\ ); \cb_int[3]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(17), O => \cb_int[3]_i_83_n_0\ ); \cb_int[3]_i_89\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_7\, O => \cb_int[3]_i_89_n_0\ ); \cb_int[3]_i_9\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(10), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_6\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(2), O => \cb_int[3]_i_9_n_0\ ); \cb_int[3]_i_90\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_44_n_7\, O => \cb_int[3]_i_90_n_0\ ); \cb_int[3]_i_91\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_4\, O => \cb_int[3]_i_91_n_0\ ); \cb_int[3]_i_92\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_5\, O => \cb_int[3]_i_92_n_0\ ); \cb_int[3]_i_93\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_75_n_6\, O => \cb_int[3]_i_93_n_0\ ); \cb_int[3]_i_99\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(3), I1 => rgb888(1), O => \cb_int[3]_i_99_n_0\ ); \cb_int[7]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(13), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_12_n_7\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(5), O => \cb_int[7]_i_10_n_0\ ); \cb_int[7]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_3\(0), I1 => \rgb888[8]_1\(1), I2 => \rgb888[12]\(0), I3 => \^co\(0), I4 => \rgb888[8]_0\(2), O => \cb_int[7]_i_11_n_0\ ); \cb_int[7]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(5), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_0\(3), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[11]_i_24_n_7\, O => cb_int_reg2(5) ); \cb_int[7]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(12), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_4\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(4), O => \cb_int[7]_i_13_n_0\ ); \cb_int[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_2\(3), I1 => \rgb888[8]_1\(1), I2 => \rgb888[13]_0\(3), I3 => \^co\(0), I4 => \rgb888[8]_0\(1), O => \cb_int[7]_i_14_n_0\ ); \cb_int[7]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(4), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_0\(2), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[7]_i_29_n_4\, O => cb_int_reg2(4) ); \cb_int[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(11), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_33_n_5\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(3), O => \cb_int[7]_i_16_n_0\ ); \cb_int[7]_i_17\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_2\(2), I1 => \rgb888[8]_1\(1), I2 => \rgb888[13]_0\(2), I3 => \^co\(0), I4 => \rgb888[8]_0\(0), O => \cb_int[7]_i_17_n_0\ ); \cb_int[7]_i_18\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(3), I1 => \rgb888[0]\(3), I2 => \rgb888[0]_0\(1), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[7]_i_29_n_5\, O => cb_int_reg2(3) ); \cb_int[7]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"B0BF" ) port map ( I0 => cb_int_reg8, I1 => cb_int_reg7(15), I2 => \cb_int_reg[31]_i_12_n_1\, I3 => cb_int_reg5(7), O => \cb_int[7]_i_19_n_0\ ); \cb_int[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"5959A959" ) port map ( I0 => \cb_int[11]_i_19_n_0\, I1 => cb_int_reg5(7), I2 => \cb_int_reg[31]_i_12_n_1\, I3 => cb_int_reg7(15), I4 => cb_int_reg8, O => \cb_int[7]_i_2_n_0\ ); \cb_int[7]_i_20\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cb_int_reg3(6), I1 => \rgb888[0]\(3), I2 => \rgb888[0]\(0), I3 => \cb_int_reg[11]_i_25_n_0\, I4 => \cb_int_reg[11]_i_24_n_6\, O => cb_int_reg2(6) ); \cb_int[7]_i_21\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_3\(1), I1 => \rgb888[8]_1\(1), I2 => \rgb888[12]\(1), I3 => \^co\(0), I4 => \rgb888[8]_0\(3), O => \cb_int[7]_i_21_n_0\ ); \cb_int[7]_i_22\: unisim.vcomponents.LUT5 generic map( INIT => X"1D001DFF" ) port map ( I0 => cb_int_reg7(14), I1 => cb_int_reg8, I2 => \cb_int_reg[31]_i_12_n_6\, I3 => \cb_int_reg[31]_i_12_n_1\, I4 => cb_int_reg5(6), O => \cb_int[7]_i_22_n_0\ ); \cb_int[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[7]_i_10_n_0\, I1 => \cb_int[7]_i_11_n_0\, I2 => cb_int_reg2(5), O => \cb_int[7]_i_3_n_0\ ); \cb_int[7]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_39_n_0\ ); \cb_int[7]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[7]_i_13_n_0\, I1 => \cb_int[7]_i_14_n_0\, I2 => cb_int_reg2(4), O => \cb_int[7]_i_4_n_0\ ); \cb_int[7]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_40_n_0\ ); \cb_int[7]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_41_n_0\ ); \cb_int[7]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_42_n_0\ ); \cb_int[7]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int[7]_i_16_n_0\, I1 => \cb_int[7]_i_17_n_0\, I2 => cb_int_reg2(3), O => \cb_int[7]_i_5_n_0\ ); \cb_int[7]_i_52\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[3]_i_33_n_4\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \cb_int_reg[3]_i_20_n_5\, O => \cb_int[7]_i_52_n_0\ ); \cb_int[7]_i_53\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_29_n_4\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_0\(2), O => \cb_int[7]_i_53_n_0\ ); \cb_int[7]_i_54\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_29_n_5\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_0\(1), O => \cb_int[7]_i_54_n_0\ ); \cb_int[7]_i_55\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_29_n_6\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \rgb888[0]_0\(0), O => \cb_int[7]_i_55_n_0\ ); \cb_int[7]_i_56\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_29_n_7\, I1 => \cb_int_reg[11]_i_25_n_0\, I2 => \cb_int_reg[3]_i_20_n_4\, O => \cb_int[7]_i_56_n_0\ ); \cb_int[7]_i_57\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(2), O => \cb_int[7]_i_57_n_0\ ); \cb_int[7]_i_58\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(1), O => \cb_int[7]_i_58_n_0\ ); \cb_int[7]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[0]_0\(0), O => \cb_int[7]_i_59_n_0\ ); \cb_int[7]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"99969666" ) port map ( I0 => \cb_int[7]_i_19_n_0\, I1 => \cb_int[11]_i_19_n_0\, I2 => cb_int_reg2(6), I3 => \cb_int[7]_i_21_n_0\, I4 => \cb_int[7]_i_22_n_0\, O => \cb_int[7]_i_6_n_0\ ); \cb_int[7]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_20_n_4\, O => \cb_int[7]_i_60_n_0\ ); \cb_int[7]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_62_n_0\ ); \cb_int[7]_i_63\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_63_n_0\ ); \cb_int[7]_i_64\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_64_n_0\ ); \cb_int[7]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(1), O => \cb_int[7]_i_65_n_0\ ); \cb_int[7]_i_67\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_0\(3), I1 => \rgb888[8]_1\(0), O => \cb_int[7]_i_67_n_0\ ); \cb_int[7]_i_68\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_0\(1), I1 => \rgb888[8]_0\(2), O => \cb_int[7]_i_68_n_0\ ); \cb_int[7]_i_69\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]\(3), I1 => \rgb888[8]_0\(0), O => \cb_int[7]_i_69_n_0\ ); \cb_int[7]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[7]_i_3_n_0\, I1 => cb_int_reg2(6), I2 => \cb_int[7]_i_21_n_0\, I3 => \cb_int[7]_i_22_n_0\, O => \cb_int[7]_i_7_n_0\ ); \cb_int[7]_i_70\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]\(1), I1 => \rgb888[8]\(2), O => \cb_int[7]_i_70_n_0\ ); \cb_int[7]_i_71\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_1\(0), I1 => \rgb888[8]_0\(3), O => \cb_int[7]_i_71_n_0\ ); \cb_int[7]_i_72\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_0\(2), I1 => \rgb888[8]_0\(1), O => \cb_int[7]_i_72_n_0\ ); \cb_int[7]_i_73\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_0\(0), I1 => \rgb888[8]\(3), O => \cb_int[7]_i_73_n_0\ ); \cb_int[7]_i_74\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]\(2), I1 => \rgb888[8]\(1), O => \cb_int[7]_i_74_n_0\ ); \cb_int[7]_i_75\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cb_int_reg[3]_0\(3), I1 => \rgb888[8]\(0), O => \cb_int[7]_i_75_n_0\ ); \cb_int[7]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cb_int_reg[3]_0\(1), I1 => \^cb_int_reg[3]_0\(2), O => \cb_int[7]_i_76_n_0\ ); \cb_int[7]_i_77\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^o\(1), I1 => \^cb_int_reg[3]_0\(0), O => \cb_int[7]_i_77_n_0\ ); \cb_int[7]_i_78\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rgb888(8), I1 => \^o\(0), O => \cb_int[7]_i_78_n_0\ ); \cb_int[7]_i_79\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]\(0), I1 => \^cb_int_reg[3]_0\(3), O => \cb_int[7]_i_79_n_0\ ); \cb_int[7]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[7]_i_10_n_0\, I1 => \cb_int[7]_i_11_n_0\, I2 => cb_int_reg2(5), I3 => \cb_int[7]_i_4_n_0\, O => \cb_int[7]_i_8_n_0\ ); \cb_int[7]_i_80\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cb_int_reg[3]_0\(2), I1 => \^cb_int_reg[3]_0\(1), O => \cb_int[7]_i_80_n_0\ ); \cb_int[7]_i_81\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cb_int_reg[3]_0\(0), I1 => \^o\(1), O => \cb_int[7]_i_81_n_0\ ); \cb_int[7]_i_82\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^o\(0), I1 => rgb888(8), O => \cb_int[7]_i_82_n_0\ ); \cb_int[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cb_int[7]_i_13_n_0\, I1 => \cb_int[7]_i_14_n_0\, I2 => cb_int_reg2(4), I3 => \cb_int[7]_i_5_n_0\, O => \cb_int[7]_i_9_n_0\ ); \cb_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[3]_i_1_n_7\, Q => \cb_int_reg_n_0_[0]\, R => '0' ); \cb_int_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[11]_i_1_n_5\, Q => \cb_int_reg__0\(10), R => '0' ); \cb_int_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[11]_i_1_n_4\, Q => \cb_int_reg__0\(11), R => '0' ); \cb_int_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_1_n_0\, CO(3) => \cb_int_reg[11]_i_1_n_0\, CO(2) => \cb_int_reg[11]_i_1_n_1\, CO(1) => \cb_int_reg[11]_i_1_n_2\, CO(0) => \cb_int_reg[11]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[11]_i_2_n_0\, DI(2) => \cb_int[11]_i_3_n_0\, DI(1) => \cb_int[11]_i_4_n_0\, DI(0) => \cb_int[11]_i_5_n_0\, O(3) => \cb_int_reg[11]_i_1_n_4\, O(2) => \cb_int_reg[11]_i_1_n_5\, O(1) => \cb_int_reg[11]_i_1_n_6\, O(0) => \cb_int_reg[11]_i_1_n_7\, S(3) => \cb_int[11]_i_6_n_0\, S(2) => \cb_int[11]_i_7_n_0\, S(1) => \cb_int[11]_i_8_n_0\, S(0) => \cb_int[11]_i_9_n_0\ ); \cb_int_reg[11]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_28_n_0\, CO(3) => \cb_int_reg[11]_i_16_n_0\, CO(2) => \cb_int_reg[11]_i_16_n_1\, CO(1) => \cb_int_reg[11]_i_16_n_2\, CO(0) => \cb_int_reg[11]_i_16_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(8 downto 5), S(3) => \cb_int[11]_i_29_n_0\, S(2) => \cb_int[11]_i_30_n_0\, S(1) => \cb_int[11]_i_31_n_0\, S(0) => \cb_int[11]_i_32_n_0\ ); \cb_int_reg[11]_i_17\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_33_n_0\, CO(3) => \cb_int_reg[11]_i_17_n_0\, CO(2) => \cb_int_reg[11]_i_17_n_1\, CO(1) => \cb_int_reg[11]_i_17_n_2\, CO(0) => \cb_int_reg[11]_i_17_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(18 downto 15), S(3) => \cb_int[11]_i_34_n_0\, S(2) => \cb_int[11]_i_35_n_0\, S(1) => \cb_int[11]_i_36_n_0\, S(0) => \cb_int[11]_i_37_n_0\ ); \cb_int_reg[11]_i_18\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_38_n_0\, CO(3) => \NLW_cb_int_reg[11]_i_18_CO_UNCONNECTED\(3), CO(2) => cb_int_reg8, CO(1) => \cb_int_reg[11]_i_18_n_2\, CO(0) => \cb_int_reg[11]_i_18_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \cb_int[11]_i_39_n_0\, DI(0) => \cb_int[11]_i_40_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_18_O_UNCONNECTED\(3 downto 0), S(3) => '0', S(2) => \cb_int[11]_i_41_n_0\, S(1) => \cb_int[11]_i_42_n_0\, S(0) => \cb_int[11]_i_43_n_0\ ); \cb_int_reg[11]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_29_n_0\, CO(3) => \cb_int_reg[15]_0\(0), CO(2) => \cb_int_reg[11]_i_24_n_1\, CO(1) => \cb_int_reg[11]_i_24_n_2\, CO(0) => \cb_int_reg[11]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[11]_i_24_n_4\, O(2) => \cb_int_reg[11]_i_24_n_5\, O(1) => \cb_int_reg[11]_i_24_n_6\, O(0) => \cb_int_reg[11]_i_24_n_7\, S(3) => \cb_int[11]_i_44_n_0\, S(2) => \cb_int[11]_i_45_n_0\, S(1) => \cb_int[11]_i_46_n_0\, S(0) => \cb_int[11]_i_47_n_0\ ); \cb_int_reg[11]_i_25\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_48_n_0\, CO(3) => \cb_int_reg[11]_i_25_n_0\, CO(2) => \cb_int_reg[11]_i_25_n_1\, CO(1) => \cb_int_reg[11]_i_25_n_2\, CO(0) => \cb_int_reg[11]_i_25_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \rgb888[0]\(3), DI(1) => \rgb888[0]\(3), DI(0) => \rgb888[0]\(3), O(3 downto 0) => \NLW_cb_int_reg[11]_i_25_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_49_n_0\, S(2) => \cb_int[11]_i_50_n_0\, S(1) => \cb_int[11]_i_51_n_0\, S(0) => \cb_int[11]_i_52_n_0\ ); \cb_int_reg[11]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_28_n_0\, CO(3) => \cb_int_reg[11]_i_26_n_0\, CO(2) => \cb_int_reg[11]_i_26_n_1\, CO(1) => \cb_int_reg[11]_i_26_n_2\, CO(0) => \cb_int_reg[11]_i_26_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(8 downto 5), S(3) => \cb_int[11]_i_53_n_0\, S(2) => \cb_int[11]_i_54_n_0\, S(1) => \cb_int[11]_i_55_n_0\, S(0) => \cb_int[11]_i_56_n_0\ ); \cb_int_reg[11]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[11]_i_28_n_0\, CO(2) => \cb_int_reg[11]_i_28_n_1\, CO(1) => \cb_int_reg[11]_i_28_n_2\, CO(0) => \cb_int_reg[11]_i_28_n_3\, CYINIT => \cb_int[11]_i_57_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(4 downto 1), S(3) => \cb_int[11]_i_58_n_0\, S(2) => \cb_int[11]_i_59_n_0\, S(1) => \cb_int[11]_i_60_n_0\, S(0) => \cb_int[11]_i_61_n_0\ ); \cb_int_reg[11]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_15_n_0\, CO(3) => \cb_int_reg[11]_i_33_n_0\, CO(2) => \cb_int_reg[11]_i_33_n_1\, CO(1) => \cb_int_reg[11]_i_33_n_2\, CO(0) => \cb_int_reg[11]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(14 downto 11), S(3) => \cb_int[11]_i_62_n_0\, S(2) => \cb_int[11]_i_63_n_0\, S(1) => \cb_int[11]_i_64_n_0\, S(0) => \cb_int[11]_i_65_n_0\ ); \cb_int_reg[11]_i_38\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_66_n_0\, CO(3) => \cb_int_reg[11]_i_38_n_0\, CO(2) => \cb_int_reg[11]_i_38_n_1\, CO(1) => \cb_int_reg[11]_i_38_n_2\, CO(0) => \cb_int_reg[11]_i_38_n_3\, CYINIT => '0', DI(3) => \cb_int[11]_i_67_n_0\, DI(2) => \cb_int[11]_i_68_n_0\, DI(1) => \cb_int[11]_i_69_n_0\, DI(0) => \cb_int[11]_i_70_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_38_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_71_n_0\, S(2) => \cb_int[11]_i_72_n_0\, S(1) => \cb_int[11]_i_73_n_0\, S(0) => \cb_int[11]_i_74_n_0\ ); \cb_int_reg[11]_i_48\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_75_n_0\, CO(3) => \cb_int_reg[11]_i_48_n_0\, CO(2) => \cb_int_reg[11]_i_48_n_1\, CO(1) => \cb_int_reg[11]_i_48_n_2\, CO(0) => \cb_int_reg[11]_i_48_n_3\, CYINIT => '0', DI(3) => \rgb888[0]\(3), DI(2) => \rgb888[0]\(3), DI(1) => \rgb888[0]\(3), DI(0) => \cb_int[11]_i_76_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_48_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_77_n_0\, S(2) => \cb_int[11]_i_78_n_0\, S(1) => \cb_int[11]_i_79_n_0\, S(0) => \cb_int[11]_i_80_n_0\ ); \cb_int_reg[11]_i_66\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_81_n_0\, CO(3) => \cb_int_reg[11]_i_66_n_0\, CO(2) => \cb_int_reg[11]_i_66_n_1\, CO(1) => \cb_int_reg[11]_i_66_n_2\, CO(0) => \cb_int_reg[11]_i_66_n_3\, CYINIT => '0', DI(3) => \cb_int[11]_i_82_n_0\, DI(2) => \cb_int[11]_i_83_n_0\, DI(1) => \cb_int[11]_i_84_n_0\, DI(0) => \cb_int[11]_i_85_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_66_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_86_n_0\, S(2) => \cb_int[11]_i_87_n_0\, S(1) => \cb_int[11]_i_88_n_0\, S(0) => \cb_int[11]_i_89_n_0\ ); \cb_int_reg[11]_i_75\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_90_n_0\, CO(3) => \cb_int_reg[11]_i_75_n_0\, CO(2) => \cb_int_reg[11]_i_75_n_1\, CO(1) => \cb_int_reg[11]_i_75_n_2\, CO(0) => \cb_int_reg[11]_i_75_n_3\, CYINIT => '0', DI(3) => \cb_int[11]_i_91_n_0\, DI(2) => \cb_int[11]_i_92_n_0\, DI(1) => \cb_int[11]_i_93_n_0\, DI(0) => \cb_int[11]_i_94_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_75_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_95_n_0\, S(2) => \cb_int[11]_i_96_n_0\, S(1) => \cb_int[11]_i_97_n_0\, S(0) => \cb_int[11]_i_98_n_0\ ); \cb_int_reg[11]_i_81\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[11]_i_81_n_0\, CO(2) => \cb_int_reg[11]_i_81_n_1\, CO(1) => \cb_int_reg[11]_i_81_n_2\, CO(0) => \cb_int_reg[11]_i_81_n_3\, CYINIT => '1', DI(3) => \cb_int[11]_i_99_n_0\, DI(2) => \cb_int[11]_i_100_n_0\, DI(1) => \cb_int[11]_i_101_n_0\, DI(0) => \cb_int[11]_i_102_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_81_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_103_n_0\, S(2) => \cb_int[11]_i_104_n_0\, S(1) => \cb_int[11]_i_105_n_0\, S(0) => \cb_int[11]_i_106_n_0\ ); \cb_int_reg[11]_i_90\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[11]_i_90_n_0\, CO(2) => \cb_int_reg[11]_i_90_n_1\, CO(1) => \cb_int_reg[11]_i_90_n_2\, CO(0) => \cb_int_reg[11]_i_90_n_3\, CYINIT => '1', DI(3) => \cb_int[11]_i_107_n_0\, DI(2) => \cb_int[11]_i_108_n_0\, DI(1) => \cb_int[11]_i_109_n_0\, DI(0) => \cb_int[11]_i_110_n_0\, O(3 downto 0) => \NLW_cb_int_reg[11]_i_90_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[11]_i_111_n_0\, S(2) => \cb_int[11]_i_112_n_0\, S(1) => \cb_int[11]_i_113_n_0\, S(0) => \cb_int[11]_i_114_n_0\ ); \cb_int_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[15]_i_1_n_7\, Q => \cb_int_reg__0\(12), R => '0' ); \cb_int_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[15]_i_1_n_6\, Q => \cb_int_reg__0\(13), R => '0' ); \cb_int_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[15]_i_1_n_5\, Q => \cb_int_reg__0\(14), R => '0' ); \cb_int_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[15]_i_1_n_4\, Q => \cb_int_reg__0\(15), R => '0' ); \cb_int_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_1_n_0\, CO(3) => \cb_int_reg[15]_i_1_n_0\, CO(2) => \cb_int_reg[15]_i_1_n_1\, CO(1) => \cb_int_reg[15]_i_1_n_2\, CO(0) => \cb_int_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[15]_i_2_n_0\, DI(2) => \cb_int[15]_i_3_n_0\, DI(1) => \cb_int[15]_i_4_n_0\, DI(0) => \cb_int[15]_i_5_n_0\, O(3) => \cb_int_reg[15]_i_1_n_4\, O(2) => \cb_int_reg[15]_i_1_n_5\, O(1) => \cb_int_reg[15]_i_1_n_6\, O(0) => \cb_int_reg[15]_i_1_n_7\, S(3) => \cb_int[15]_i_6_n_0\, S(2) => \cb_int[15]_i_7_n_0\, S(1) => \cb_int[15]_i_8_n_0\, S(0) => \cb_int[15]_i_9_n_0\ ); \cb_int_reg[15]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_16_n_0\, CO(3) => \cb_int_reg[15]_i_20_n_0\, CO(2) => \cb_int_reg[15]_i_20_n_1\, CO(1) => \cb_int_reg[15]_i_20_n_2\, CO(0) => \cb_int_reg[15]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(12 downto 9), S(3) => \cb_int[15]_i_27_n_0\, S(2) => \cb_int[15]_i_28_n_0\, S(1) => \cb_int[15]_i_29_n_0\, S(0) => \cb_int[15]_i_30_n_0\ ); \cb_int_reg[15]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_26_n_0\, CO(3) => \cb_int_reg[15]_i_33_n_0\, CO(2) => \cb_int_reg[15]_i_33_n_1\, CO(1) => \cb_int_reg[15]_i_33_n_2\, CO(0) => \cb_int_reg[15]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(12 downto 9), S(3) => \cb_int[15]_i_43_n_0\, S(2) => \cb_int[15]_i_44_n_0\, S(1) => \cb_int[15]_i_45_n_0\, S(0) => \cb_int[15]_i_46_n_0\ ); \cb_int_reg[16]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[19]_i_1_n_7\, Q => \cb_int_reg__0\(16), R => '0' ); \cb_int_reg[17]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[19]_i_1_n_6\, Q => \cb_int_reg__0\(17), R => '0' ); \cb_int_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[19]_i_1_n_5\, Q => \cb_int_reg__0\(18), R => '0' ); \cb_int_reg[19]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[19]_i_1_n_4\, Q => \cb_int_reg__0\(19), R => '0' ); \cb_int_reg[19]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_1_n_0\, CO(3) => \cb_int_reg[19]_i_1_n_0\, CO(2) => \cb_int_reg[19]_i_1_n_1\, CO(1) => \cb_int_reg[19]_i_1_n_2\, CO(0) => \cb_int_reg[19]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[19]_i_2_n_0\, DI(2) => \cb_int[19]_i_3_n_0\, DI(1) => \cb_int[19]_i_4_n_0\, DI(0) => \cb_int[19]_i_5_n_0\, O(3) => \cb_int_reg[19]_i_1_n_4\, O(2) => \cb_int_reg[19]_i_1_n_5\, O(1) => \cb_int_reg[19]_i_1_n_6\, O(0) => \cb_int_reg[19]_i_1_n_7\, S(3) => \cb_int[19]_i_6_n_0\, S(2) => \cb_int[19]_i_7_n_0\, S(1) => \cb_int[19]_i_8_n_0\, S(0) => \cb_int[19]_i_9_n_0\ ); \cb_int_reg[19]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_20_n_0\, CO(3) => \cb_int_reg[19]_i_20_n_0\, CO(2) => \cb_int_reg[19]_i_20_n_1\, CO(1) => \cb_int_reg[19]_i_20_n_2\, CO(0) => \cb_int_reg[19]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(16 downto 13), S(3) => \cb_int[19]_i_28_n_0\, S(2) => \cb_int[19]_i_29_n_0\, S(1) => \cb_int[19]_i_30_n_0\, S(0) => \cb_int[19]_i_31_n_0\ ); \cb_int_reg[19]_i_25\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[11]_i_17_n_0\, CO(3) => \cb_int_reg[19]_i_25_n_0\, CO(2) => \cb_int_reg[19]_i_25_n_1\, CO(1) => \cb_int_reg[19]_i_25_n_2\, CO(0) => \cb_int_reg[19]_i_25_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(22 downto 19), S(3) => \cb_int[19]_i_34_n_0\, S(2) => \cb_int[19]_i_35_n_0\, S(1) => \cb_int[19]_i_36_n_0\, S(0) => \cb_int[19]_i_37_n_0\ ); \cb_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[3]_i_1_n_6\, Q => \cb_int_reg_n_0_[1]\, R => '0' ); \cb_int_reg[20]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[23]_i_1_n_7\, Q => \cb_int_reg__0\(20), R => '0' ); \cb_int_reg[21]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[23]_i_1_n_6\, Q => \cb_int_reg__0\(21), R => '0' ); \cb_int_reg[22]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[23]_i_1_n_5\, Q => \cb_int_reg__0\(22), R => '0' ); \cb_int_reg[23]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[23]_i_1_n_4\, Q => \cb_int_reg__0\(23), R => '0' ); \cb_int_reg[23]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_1_n_0\, CO(3) => \cb_int_reg[23]_i_1_n_0\, CO(2) => \cb_int_reg[23]_i_1_n_1\, CO(1) => \cb_int_reg[23]_i_1_n_2\, CO(0) => \cb_int_reg[23]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[23]_i_2_n_0\, DI(2) => \cb_int[23]_i_3_n_0\, DI(1) => \cb_int[23]_i_4_n_0\, DI(0) => \cb_int[23]_i_5_n_0\, O(3) => \cb_int_reg[23]_i_1_n_4\, O(2) => \cb_int_reg[23]_i_1_n_5\, O(1) => \cb_int_reg[23]_i_1_n_6\, O(0) => \cb_int_reg[23]_i_1_n_7\, S(3) => \cb_int[23]_i_6_n_0\, S(2) => \cb_int[23]_i_7_n_0\, S(1) => \cb_int[23]_i_8_n_0\, S(0) => \cb_int[23]_i_9_n_0\ ); \cb_int_reg[23]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_25_n_0\, CO(3) => \cb_int_reg[23]_i_24_n_0\, CO(2) => \cb_int_reg[23]_i_24_n_1\, CO(1) => \cb_int_reg[23]_i_24_n_2\, CO(0) => \cb_int_reg[23]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(26 downto 23), S(3) => \cb_int[23]_i_29_n_0\, S(2) => \cb_int[23]_i_30_n_0\, S(1) => \cb_int[23]_i_31_n_0\, S(0) => \cb_int[23]_i_32_n_0\ ); \cb_int_reg[24]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[27]_i_1_n_7\, Q => \cb_int_reg__0\(24), R => '0' ); \cb_int_reg[25]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[27]_i_1_n_6\, Q => \cb_int_reg__0\(25), R => '0' ); \cb_int_reg[26]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[27]_i_1_n_5\, Q => \cb_int_reg__0\(26), R => '0' ); \cb_int_reg[27]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[27]_i_1_n_4\, Q => \cb_int_reg__0\(27), R => '0' ); \cb_int_reg[27]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[23]_i_1_n_0\, CO(3) => \cb_int_reg[27]_i_1_n_0\, CO(2) => \cb_int_reg[27]_i_1_n_1\, CO(1) => \cb_int_reg[27]_i_1_n_2\, CO(0) => \cb_int_reg[27]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[31]_i_2_n_0\, DI(2) => \cb_int[31]_i_2_n_0\, DI(1) => \cb_int[31]_i_2_n_0\, DI(0) => \cb_int[27]_i_2_n_0\, O(3) => \cb_int_reg[27]_i_1_n_4\, O(2) => \cb_int_reg[27]_i_1_n_5\, O(1) => \cb_int_reg[27]_i_1_n_6\, O(0) => \cb_int_reg[27]_i_1_n_7\, S(3) => \cb_int[27]_i_3_n_0\, S(2) => \cb_int[27]_i_4_n_0\, S(1) => \cb_int[27]_i_5_n_0\, S(0) => \cb_int[27]_i_6_n_0\ ); \cb_int_reg[27]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[23]_i_24_n_0\, CO(3) => \NLW_cb_int_reg[27]_i_9_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[27]_i_9_n_1\, CO(1) => \cb_int_reg[27]_i_9_n_2\, CO(0) => \cb_int_reg[27]_i_9_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg7(30 downto 27), S(3) => \cb_int[27]_i_12_n_0\, S(2) => \cb_int[27]_i_13_n_0\, S(1) => \cb_int[27]_i_14_n_0\, S(0) => \cb_int[27]_i_15_n_0\ ); \cb_int_reg[28]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[31]_i_1_n_7\, Q => \cb_int_reg__0\(28), R => '0' ); \cb_int_reg[29]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[31]_i_1_n_6\, Q => \cb_int_reg__0\(29), R => '0' ); \cb_int_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[3]_i_1_n_5\, Q => \cb_int_reg_n_0_[2]\, R => '0' ); \cb_int_reg[30]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[31]_i_1_n_5\, Q => \cb_int_reg__0\(30), R => '0' ); \cb_int_reg[31]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[31]_i_1_n_4\, Q => \cb_int_reg__0\(31), R => '0' ); \cb_int_reg[31]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[27]_i_1_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_1_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_1_n_1\, CO(1) => \cb_int_reg[31]_i_1_n_2\, CO(0) => \cb_int_reg[31]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \cb_int[31]_i_2_n_0\, DI(1) => \cb_int[31]_i_2_n_0\, DI(0) => \cb_int[31]_i_2_n_0\, O(3) => \cb_int_reg[31]_i_1_n_4\, O(2) => \cb_int_reg[31]_i_1_n_5\, O(1) => \cb_int_reg[31]_i_1_n_6\, O(0) => \cb_int_reg[31]_i_1_n_7\, S(3) => \cb_int[31]_i_3_n_0\, S(2) => \cb_int[31]_i_4_n_0\, S(1) => \cb_int[31]_i_5_n_0\, S(0) => \cb_int[31]_i_6_n_0\ ); \cb_int_reg[31]_i_11\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_30_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_11_n_1\, CO(1) => \NLW_cb_int_reg[31]_i_11_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[31]_i_11_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_11_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => cb_int_reg5(22 downto 21), S(3 downto 2) => B"01", S(1) => \cb_int[31]_i_31_n_0\, S(0) => \cb_int[31]_i_32_n_0\ ); \cb_int_reg[31]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_33_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_12_n_1\, CO(1) => \NLW_cb_int_reg[31]_i_12_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[31]_i_12_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \cb_int_reg[31]_i_34_n_2\, DI(0) => '0', O(3 downto 2) => \NLW_cb_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_12_n_6\, O(0) => \cb_int_reg[31]_i_12_n_7\, S(3 downto 2) => B"01", S(1) => \cb_int[31]_i_35_n_0\, S(0) => \cb_int[31]_i_36_n_0\ ); \cb_int_reg[31]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_37_n_0\, CO(3) => \cb_int_reg[31]_i_14_n_0\, CO(2) => \cb_int_reg[31]_i_14_n_1\, CO(1) => \cb_int_reg[31]_i_14_n_2\, CO(0) => \cb_int_reg[31]_i_14_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(20 downto 17), S(3) => \cb_int[31]_i_38_n_0\, S(2) => \cb_int[31]_i_39_n_0\, S(1) => \cb_int[31]_i_40_n_0\, S(0) => \cb_int[31]_i_41_n_0\ ); \cb_int_reg[31]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_20_n_0\, CO(3) => \cb_int_reg[31]_i_30_n_0\, CO(2) => \cb_int_reg[31]_i_30_n_1\, CO(1) => \cb_int_reg[31]_i_30_n_2\, CO(0) => \cb_int_reg[31]_i_30_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg5(20 downto 17), S(3) => \cb_int[31]_i_67_n_0\, S(2) => \cb_int[31]_i_68_n_0\, S(1) => \cb_int[31]_i_69_n_0\, S(0) => \cb_int[31]_i_70_n_0\ ); \cb_int_reg[31]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_16_n_0\, CO(3) => \cb_int_reg[31]_i_33_n_0\, CO(2) => \cb_int_reg[31]_i_33_n_1\, CO(1) => \cb_int_reg[31]_i_33_n_2\, CO(0) => \cb_int_reg[31]_i_33_n_3\, CYINIT => '0', DI(3) => \cb_int_reg[31]_i_34_n_7\, DI(2) => \cb_int[31]_i_71_n_0\, DI(1) => \cb_int[31]_i_72_n_0\, DI(0) => \cb_int_reg[31]_i_73_n_7\, O(3) => \cb_int_reg[31]_i_33_n_4\, O(2) => \cb_int_reg[31]_i_33_n_5\, O(1) => \cb_int_reg[31]_i_33_n_6\, O(0) => \cb_int_reg[31]_i_33_n_7\, S(3) => \cb_int[31]_i_74_n_0\, S(2) => \cb_int[31]_i_75_n_0\, S(1) => \cb_int[31]_i_76_n_0\, S(0) => \cb_int[31]_i_77_n_0\ ); \cb_int_reg[31]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_73_n_0\, CO(3 downto 2) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(3 downto 2), CO(1) => \cb_int_reg[31]_i_34_n_2\, CO(0) => \NLW_cb_int_reg[31]_i_34_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(23), O(3 downto 1) => \NLW_cb_int_reg[31]_i_34_O_UNCONNECTED\(3 downto 1), O(0) => \cb_int_reg[31]_i_34_n_7\, S(3 downto 1) => B"001", S(0) => \cb_int[31]_i_78_n_0\ ); \cb_int_reg[31]_i_37\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_33_n_0\, CO(3) => \cb_int_reg[31]_i_37_n_0\, CO(2) => \cb_int_reg[31]_i_37_n_1\, CO(1) => \cb_int_reg[31]_i_37_n_2\, CO(0) => \cb_int_reg[31]_i_37_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(16 downto 13), S(3) => \cb_int[31]_i_79_n_0\, S(2) => \cb_int[31]_i_80_n_0\, S(1) => \cb_int[31]_i_81_n_0\, S(0) => \cb_int[31]_i_82_n_0\ ); \cb_int_reg[31]_i_7\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_14_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_7_n_1\, CO(1) => \NLW_cb_int_reg[31]_i_7_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[31]_i_7_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => cb_int_reg3(22 downto 21), S(3 downto 2) => B"01", S(1) => \cb_int[31]_i_15_n_0\, S(0) => \cb_int[31]_i_16_n_0\ ); \cb_int_reg[31]_i_73\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_57_n_0\, CO(3) => \cb_int_reg[31]_i_73_n_0\, CO(2) => \cb_int_reg[31]_i_73_n_1\, CO(1) => \cb_int_reg[31]_i_73_n_2\, CO(0) => \cb_int_reg[31]_i_73_n_3\, CYINIT => '0', DI(3) => rgb888(22), DI(2 downto 0) => rgb888(23 downto 21), O(3) => \cb_int_reg[31]_i_73_n_4\, O(2) => \cb_int_reg[31]_i_73_n_5\, O(1) => \cb_int_reg[31]_i_73_n_6\, O(0) => \cb_int_reg[31]_i_73_n_7\, S(3) => \cb_int[31]_i_95_n_0\, S(2) => \cb_int[31]_i_96_n_0\, S(1) => \cb_int[31]_i_97_n_0\, S(0) => \cb_int[31]_i_98_n_0\ ); \cb_int_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[3]_i_1_n_4\, Q => \cb_int_reg_n_0_[3]\, R => '0' ); \cb_int_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_1_n_0\, CO(2) => \cb_int_reg[3]_i_1_n_1\, CO(1) => \cb_int_reg[3]_i_1_n_2\, CO(0) => \cb_int_reg[3]_i_1_n_3\, CYINIT => '1', DI(3) => \cb_int[3]_i_2_n_0\, DI(2) => \cb_int[3]_i_3_n_0\, DI(1) => \cb_int[3]_i_4_n_0\, DI(0) => '1', O(3) => \cb_int_reg[3]_i_1_n_4\, O(2) => \cb_int_reg[3]_i_1_n_5\, O(1) => \cb_int_reg[3]_i_1_n_6\, O(0) => \cb_int_reg[3]_i_1_n_7\, S(3) => \cb_int[3]_i_5_n_0\, S(2) => \cb_int[3]_i_6_n_0\, S(1) => \cb_int[3]_i_7_n_0\, S(0) => \cb_int[3]_i_8_n_0\ ); \cb_int_reg[3]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_21_n_0\, CO(3) => \cb_int_reg[3]_i_15_n_0\, CO(2) => \cb_int_reg[3]_i_15_n_1\, CO(1) => \cb_int_reg[3]_i_15_n_2\, CO(0) => \cb_int_reg[3]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => cb_int_reg7(10 downto 8), O(0) => \NLW_cb_int_reg[3]_i_15_O_UNCONNECTED\(0), S(3) => \cb_int[3]_i_22_n_0\, S(2) => \cb_int[3]_i_23_n_0\, S(1) => \cb_int[3]_i_24_n_0\, S(0) => \cb_int[3]_i_25_n_0\ ); \cb_int_reg[3]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_26_n_0\, CO(3) => \cb_int_reg[3]_i_16_n_0\, CO(2) => \cb_int_reg[3]_i_16_n_1\, CO(1) => \cb_int_reg[3]_i_16_n_2\, CO(0) => \cb_int_reg[3]_i_16_n_3\, CYINIT => '0', DI(3) => \cb_int[3]_i_27_n_0\, DI(2 downto 0) => rgb888(21 downto 19), O(3) => \cb_int_reg[3]_i_16_n_4\, O(2) => \cb_int_reg[3]_i_16_n_5\, O(1) => \cb_int_reg[3]_i_16_n_6\, O(0) => \cb_int_reg[3]_i_16_n_7\, S(3) => \cb_int[3]_i_28_n_0\, S(2) => \cb_int[3]_i_29_n_0\, S(1) => \cb_int[3]_i_30_n_0\, S(0) => \cb_int[3]_i_31_n_0\ ); \cb_int_reg[3]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[27]_0\(0), CO(2) => \cb_int_reg[3]_i_20_n_1\, CO(1) => \cb_int_reg[3]_i_20_n_2\, CO(0) => \cb_int_reg[3]_i_20_n_3\, CYINIT => '0', DI(3 downto 2) => \rgb888[0]_8\(1 downto 0), DI(1) => \cb_int_reg[3]_i_44_n_4\, DI(0) => '0', O(3) => \cb_int_reg[3]_i_20_n_4\, O(2) => \cb_int_reg[3]_i_20_n_5\, O(1) => \cb_int_reg[3]_i_20_n_6\, O(0) => \cb_int_reg[3]_i_20_n_7\, S(3) => \cb_int[3]_i_45_n_0\, S(2) => \cb_int[3]_i_46_n_0\, S(1) => \cb_int[3]_i_47_n_0\, S(0) => \cb_int[3]_i_48_n_0\ ); \cb_int_reg[3]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_21_n_0\, CO(2) => \cb_int_reg[3]_i_21_n_1\, CO(1) => \cb_int_reg[3]_i_21_n_2\, CO(0) => \cb_int_reg[3]_i_21_n_3\, CYINIT => \cb_int[3]_i_49_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cb_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[3]_i_50_n_0\, S(2) => \cb_int[3]_i_51_n_0\, S(1) => \cb_int[3]_i_52_n_0\, S(0) => \cb_int[3]_i_53_n_0\ ); \cb_int_reg[3]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_26_n_0\, CO(2) => \cb_int_reg[3]_i_26_n_1\, CO(1) => \cb_int_reg[3]_i_26_n_2\, CO(0) => \cb_int_reg[3]_i_26_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(18 downto 16), DI(0) => '0', O(3) => \cb_int_reg[3]_i_26_n_4\, O(2) => \cb_int_reg[3]_i_26_n_5\, O(1) => \cb_int_reg[3]_i_26_n_6\, O(0) => \NLW_cb_int_reg[3]_i_26_O_UNCONNECTED\(0), S(3) => \cb_int[3]_i_54_n_0\, S(2) => \cb_int[3]_i_55_n_0\, S(1) => \cb_int[3]_i_56_n_0\, S(0) => '0' ); \cb_int_reg[3]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_63_n_0\, CO(3) => \cb_int_reg[3]_i_33_n_0\, CO(2) => \cb_int_reg[3]_i_33_n_1\, CO(1) => \cb_int_reg[3]_i_33_n_2\, CO(0) => \cb_int_reg[3]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[3]_i_33_n_4\, O(2 downto 0) => \NLW_cb_int_reg[3]_i_33_O_UNCONNECTED\(2 downto 0), S(3) => \cb_int[3]_i_64_n_0\, S(2) => \cb_int[3]_i_65_n_0\, S(1) => \cb_int[3]_i_66_n_0\, S(0) => \cb_int[3]_i_67_n_0\ ); \cb_int_reg[3]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_2\(0), CO(2) => \cb_int_reg[3]_i_34_n_1\, CO(1) => \cb_int_reg[3]_i_34_n_2\, CO(0) => \cb_int_reg[3]_i_34_n_3\, CYINIT => '0', DI(3 downto 1) => \rgb888[8]_31\(2 downto 0), DI(0) => '0', O(3 downto 0) => \^cb_int_reg[3]_0\(3 downto 0), S(3) => \cb_int[3]_i_69_n_0\, S(2) => \cb_int[3]_i_70_n_0\, S(1) => \cb_int[3]_i_71_n_0\, S(0) => \cb_int[3]_i_72_n_0\ ); \cb_int_reg[3]_i_44\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_75_n_0\, CO(3) => \cb_int_reg[3]_3\(0), CO(2) => \cb_int_reg[3]_i_44_n_1\, CO(1) => \cb_int_reg[3]_i_44_n_2\, CO(0) => \cb_int_reg[3]_i_44_n_3\, CYINIT => '0', DI(3 downto 0) => rgb888(5 downto 2), O(3) => \cb_int_reg[3]_i_44_n_4\, O(2) => \cb_int_reg[3]_i_44_n_5\, O(1) => \cb_int_reg[3]_i_44_n_6\, O(0) => \cb_int_reg[3]_i_44_n_7\, S(3) => \cb_int[3]_i_76_n_0\, S(2) => \cb_int[3]_i_77_n_0\, S(1) => \cb_int[3]_i_78_n_0\, S(0) => \cb_int[3]_i_79_n_0\ ); \cb_int_reg[3]_i_57\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_57_n_0\, CO(2) => \cb_int_reg[3]_i_57_n_1\, CO(1) => \cb_int_reg[3]_i_57_n_2\, CO(0) => \cb_int_reg[3]_i_57_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(20 downto 18), DI(0) => '0', O(3) => \cb_int_reg[3]_i_57_n_4\, O(2) => \cb_int_reg[3]_i_57_n_5\, O(1) => \cb_int_reg[3]_i_57_n_6\, O(0) => \cb_int_reg[3]_i_57_n_7\, S(3) => \cb_int[3]_i_80_n_0\, S(2) => \cb_int[3]_i_81_n_0\, S(1) => \cb_int[3]_i_82_n_0\, S(0) => \cb_int[3]_i_83_n_0\ ); \cb_int_reg[3]_i_63\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_63_n_0\, CO(2) => \cb_int_reg[3]_i_63_n_1\, CO(1) => \cb_int_reg[3]_i_63_n_2\, CO(0) => \cb_int_reg[3]_i_63_n_3\, CYINIT => \cb_int[3]_i_89_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cb_int_reg[3]_i_63_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[3]_i_90_n_0\, S(2) => \cb_int[3]_i_91_n_0\, S(1) => \cb_int[3]_i_92_n_0\, S(0) => \cb_int[3]_i_93_n_0\ ); \cb_int_reg[3]_i_75\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_75_n_0\, CO(2) => \cb_int_reg[3]_i_75_n_1\, CO(1) => \cb_int_reg[3]_i_75_n_2\, CO(0) => \cb_int_reg[3]_i_75_n_3\, CYINIT => '0', DI(3 downto 2) => rgb888(1 downto 0), DI(1 downto 0) => B"01", O(3) => \cb_int_reg[3]_i_75_n_4\, O(2) => \cb_int_reg[3]_i_75_n_5\, O(1) => \cb_int_reg[3]_i_75_n_6\, O(0) => \cb_int_reg[3]_i_75_n_7\, S(3) => \cb_int[3]_i_99_n_0\, S(2) => \cb_int[3]_i_100_n_0\, S(1) => \cb_int[3]_i_101_n_0\, S(0) => \cb_int[3]_i_102_n_0\ ); \cb_int_reg[3]_i_94\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_1\(0), CO(2) => \cb_int_reg[3]_i_94_n_1\, CO(1) => \cb_int_reg[3]_i_94_n_2\, CO(0) => \cb_int_reg[3]_i_94_n_3\, CYINIT => '0', DI(3) => rgb888(8), DI(2 downto 0) => B"001", O(3) => \cb_int_reg[3]_i_94_n_4\, O(2 downto 1) => \^o\(1 downto 0), O(0) => \cb_int_reg[3]_i_94_n_7\, S(3) => \cb_int[3]_i_103_n_0\, S(2) => \cb_int[3]_i_104_n_0\, S(1) => \cb_int[3]_i_105_n_0\, S(0) => \cb_int[3]_i_106_n_0\ ); \cb_int_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[7]_i_1_n_7\, Q => \cb_int_reg_n_0_[4]\, R => '0' ); \cb_int_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[7]_i_1_n_6\, Q => \cb_int_reg_n_0_[5]\, R => '0' ); \cb_int_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[7]_i_1_n_5\, Q => \cb_int_reg_n_0_[6]\, R => '0' ); \cb_int_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[7]_i_1_n_4\, Q => \cb_int_reg_n_0_[7]\, R => '0' ); \cb_int_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_1_n_0\, CO(3) => \cb_int_reg[7]_i_1_n_0\, CO(2) => \cb_int_reg[7]_i_1_n_1\, CO(1) => \cb_int_reg[7]_i_1_n_2\, CO(0) => \cb_int_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \cb_int[7]_i_2_n_0\, DI(2) => \cb_int[7]_i_3_n_0\, DI(1) => \cb_int[7]_i_4_n_0\, DI(0) => \cb_int[7]_i_5_n_0\, O(3) => \cb_int_reg[7]_i_1_n_4\, O(2) => \cb_int_reg[7]_i_1_n_5\, O(1) => \cb_int_reg[7]_i_1_n_6\, O(0) => \cb_int_reg[7]_i_1_n_7\, S(3) => \cb_int[7]_i_6_n_0\, S(2) => \cb_int[7]_i_7_n_0\, S(1) => \cb_int[7]_i_8_n_0\, S(0) => \cb_int[7]_i_9_n_0\ ); \cb_int_reg[7]_i_25\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_38_n_0\, CO(3) => \^co\(0), CO(2) => \cb_int_reg[7]_i_25_n_1\, CO(1) => \cb_int_reg[7]_i_25_n_2\, CO(0) => \cb_int_reg[7]_i_25_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \rgb888[8]_1\(1), DI(1) => \rgb888[8]_1\(1), DI(0) => \rgb888[8]_1\(1), O(3 downto 0) => \NLW_cb_int_reg[7]_i_25_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[7]_i_39_n_0\, S(2) => \cb_int[7]_i_40_n_0\, S(1) => \cb_int[7]_i_41_n_0\, S(0) => \cb_int[7]_i_42_n_0\ ); \cb_int_reg[7]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[7]_i_28_n_0\, CO(2) => \cb_int_reg[7]_i_28_n_1\, CO(1) => \cb_int_reg[7]_i_28_n_2\, CO(0) => \cb_int_reg[7]_i_28_n_3\, CYINIT => \cb_int[7]_i_52_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => cb_int_reg3(4 downto 1), S(3) => \cb_int[7]_i_53_n_0\, S(2) => \cb_int[7]_i_54_n_0\, S(1) => \cb_int[7]_i_55_n_0\, S(0) => \cb_int[7]_i_56_n_0\ ); \cb_int_reg[7]_i_29\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_33_n_0\, CO(3) => \cb_int_reg[7]_i_29_n_0\, CO(2) => \cb_int_reg[7]_i_29_n_1\, CO(1) => \cb_int_reg[7]_i_29_n_2\, CO(0) => \cb_int_reg[7]_i_29_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_29_n_4\, O(2) => \cb_int_reg[7]_i_29_n_5\, O(1) => \cb_int_reg[7]_i_29_n_6\, O(0) => \cb_int_reg[7]_i_29_n_7\, S(3) => \cb_int[7]_i_57_n_0\, S(2) => \cb_int[7]_i_58_n_0\, S(1) => \cb_int[7]_i_59_n_0\, S(0) => \cb_int[7]_i_60_n_0\ ); \cb_int_reg[7]_i_38\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_61_n_0\, CO(3) => \cb_int_reg[7]_i_38_n_0\, CO(2) => \cb_int_reg[7]_i_38_n_1\, CO(1) => \cb_int_reg[7]_i_38_n_2\, CO(0) => \cb_int_reg[7]_i_38_n_3\, CYINIT => '0', DI(3) => \rgb888[8]_1\(1), DI(2) => \rgb888[8]_1\(1), DI(1) => \rgb888[8]_1\(1), DI(0) => \rgb888[8]_1\(1), O(3 downto 0) => \NLW_cb_int_reg[7]_i_38_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[7]_i_62_n_0\, S(2) => \cb_int[7]_i_63_n_0\, S(1) => \cb_int[7]_i_64_n_0\, S(0) => \cb_int[7]_i_65_n_0\ ); \cb_int_reg[7]_i_61\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_66_n_0\, CO(3) => \cb_int_reg[7]_i_61_n_0\, CO(2) => \cb_int_reg[7]_i_61_n_1\, CO(1) => \cb_int_reg[7]_i_61_n_2\, CO(0) => \cb_int_reg[7]_i_61_n_3\, CYINIT => '0', DI(3) => \cb_int[7]_i_67_n_0\, DI(2) => \cb_int[7]_i_68_n_0\, DI(1) => \cb_int[7]_i_69_n_0\, DI(0) => \cb_int[7]_i_70_n_0\, O(3 downto 0) => \NLW_cb_int_reg[7]_i_61_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[7]_i_71_n_0\, S(2) => \cb_int[7]_i_72_n_0\, S(1) => \cb_int[7]_i_73_n_0\, S(0) => \cb_int[7]_i_74_n_0\ ); \cb_int_reg[7]_i_66\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[7]_i_66_n_0\, CO(2) => \cb_int_reg[7]_i_66_n_1\, CO(1) => \cb_int_reg[7]_i_66_n_2\, CO(0) => \cb_int_reg[7]_i_66_n_3\, CYINIT => '1', DI(3) => \cb_int[7]_i_75_n_0\, DI(2) => \cb_int[7]_i_76_n_0\, DI(1) => \cb_int[7]_i_77_n_0\, DI(0) => \cb_int[7]_i_78_n_0\, O(3 downto 0) => \NLW_cb_int_reg[7]_i_66_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[7]_i_79_n_0\, S(2) => \cb_int[7]_i_80_n_0\, S(1) => \cb_int[7]_i_81_n_0\, S(0) => \cb_int[7]_i_82_n_0\ ); \cb_int_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[11]_i_1_n_7\, Q => \cb_int_reg__0\(8), R => '0' ); \cb_int_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cb_int_reg[11]_i_1_n_6\, Q => \cb_int_reg__0\(9), R => '0' ); \cb_reg[0]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[0]_i_1_n_0\, Q => cb(0), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[1]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[1]_i_1_n_0\, Q => cb(1), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[2]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[2]_i_1_n_0\, Q => cb(2), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[3]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[3]_i_1_n_0\, Q => cb(3), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[4]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[4]_i_1_n_0\, Q => cb(4), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[5]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[5]_i_1_n_0\, Q => cb(5), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[6]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[6]_i_1_n_0\, Q => cb(6), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[7]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cb[7]_i_2_n_0\, Q => cb(7), S => \cb_reg[7]_i_1_n_0\ ); \cb_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cb_reg[7]_i_3_n_0\, CO(3) => \cb_reg[7]_i_1_n_0\, CO(2) => \cb_reg[7]_i_1_n_1\, CO(1) => \cb_reg[7]_i_1_n_2\, CO(0) => \cb_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \cb[7]_i_4_n_0\, DI(2) => \cb[7]_i_5_n_0\, DI(1) => \cb[7]_i_6_n_0\, DI(0) => \cb[7]_i_7_n_0\, O(3 downto 0) => \NLW_cb_reg[7]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \cb[7]_i_8_n_0\, S(2) => \cb[7]_i_9_n_0\, S(1) => \cb[7]_i_10_n_0\, S(0) => \cb[7]_i_11_n_0\ ); \cb_reg[7]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_reg[7]_i_12_n_0\, CO(2) => \cb_reg[7]_i_12_n_1\, CO(1) => \cb_reg[7]_i_12_n_2\, CO(0) => \cb_reg[7]_i_12_n_3\, CYINIT => '0', DI(3) => \cb[7]_i_21_n_0\, DI(2) => \cb[7]_i_22_n_0\, DI(1) => \cb[7]_i_23_n_0\, DI(0) => \cb[7]_i_24_n_0\, O(3 downto 0) => \NLW_cb_reg[7]_i_12_O_UNCONNECTED\(3 downto 0), S(3) => \cb[7]_i_25_n_0\, S(2) => \cb[7]_i_26_n_0\, S(1) => \cb[7]_i_27_n_0\, S(0) => \cb[7]_i_28_n_0\ ); \cb_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \cb_reg[7]_i_12_n_0\, CO(3) => \cb_reg[7]_i_3_n_0\, CO(2) => \cb_reg[7]_i_3_n_1\, CO(1) => \cb_reg[7]_i_3_n_2\, CO(0) => \cb_reg[7]_i_3_n_3\, CYINIT => '0', DI(3) => \cb[7]_i_13_n_0\, DI(2) => \cb[7]_i_14_n_0\, DI(1) => \cb[7]_i_15_n_0\, DI(0) => \cb[7]_i_16_n_0\, O(3 downto 0) => \NLW_cb_reg[7]_i_3_O_UNCONNECTED\(3 downto 0), S(3) => \cb[7]_i_17_n_0\, S(2) => \cb[7]_i_18_n_0\, S(1) => \cb[7]_i_19_n_0\, S(0) => \cb[7]_i_20_n_0\ ); cb_regi_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => clk, O => cb_regn_0_0 ); \cr[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[0]\, I1 => \cr_int_reg__0\(31), O => \cr[0]_i_1_n_0\ ); \cr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[1]\, I1 => \cr_int_reg__0\(31), O => \cr[1]_i_1_n_0\ ); \cr[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[2]\, I1 => \cr_int_reg__0\(31), O => \cr[2]_i_1_n_0\ ); \cr[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[3]\, I1 => \cr_int_reg__0\(31), O => \cr[3]_i_1_n_0\ ); \cr[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[4]\, I1 => \cr_int_reg__0\(31), O => \cr[4]_i_1_n_0\ ); \cr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[5]\, I1 => \cr_int_reg__0\(31), O => \cr[5]_i_1_n_0\ ); \cr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[6]\, I1 => \cr_int_reg__0\(31), O => \cr[6]_i_1_n_0\ ); \cr[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(26), I1 => \cr_int_reg__0\(27), O => \cr[7]_i_10_n_0\ ); \cr[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(24), I1 => \cr_int_reg__0\(25), O => \cr[7]_i_11_n_0\ ); \cr[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(22), I1 => \cr_int_reg__0\(23), O => \cr[7]_i_13_n_0\ ); \cr[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(20), I1 => \cr_int_reg__0\(21), O => \cr[7]_i_14_n_0\ ); \cr[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(18), I1 => \cr_int_reg__0\(19), O => \cr[7]_i_15_n_0\ ); \cr[7]_i_16\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(16), I1 => \cr_int_reg__0\(17), O => \cr[7]_i_16_n_0\ ); \cr[7]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(22), I1 => \cr_int_reg__0\(23), O => \cr[7]_i_17_n_0\ ); \cr[7]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(20), I1 => \cr_int_reg__0\(21), O => \cr[7]_i_18_n_0\ ); \cr[7]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(18), I1 => \cr_int_reg__0\(19), O => \cr[7]_i_19_n_0\ ); \cr[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg_n_0_[7]\, I1 => \cr_int_reg__0\(31), O => \cr[7]_i_2_n_0\ ); \cr[7]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(16), I1 => \cr_int_reg__0\(17), O => \cr[7]_i_20_n_0\ ); \cr[7]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(14), I1 => \cr_int_reg__0\(15), O => \cr[7]_i_21_n_0\ ); \cr[7]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(12), I1 => \cr_int_reg__0\(13), O => \cr[7]_i_22_n_0\ ); \cr[7]_i_23\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(10), I1 => \cr_int_reg__0\(11), O => \cr[7]_i_23_n_0\ ); \cr[7]_i_24\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(8), I1 => \cr_int_reg__0\(9), O => \cr[7]_i_24_n_0\ ); \cr[7]_i_25\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(14), I1 => \cr_int_reg__0\(15), O => \cr[7]_i_25_n_0\ ); \cr[7]_i_26\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(12), I1 => \cr_int_reg__0\(13), O => \cr[7]_i_26_n_0\ ); \cr[7]_i_27\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(10), I1 => \cr_int_reg__0\(11), O => \cr[7]_i_27_n_0\ ); \cr[7]_i_28\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(8), I1 => \cr_int_reg__0\(9), O => \cr[7]_i_28_n_0\ ); \cr[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg__0\(30), I1 => \cr_int_reg__0\(31), O => \cr[7]_i_4_n_0\ ); \cr[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(28), I1 => \cr_int_reg__0\(29), O => \cr[7]_i_5_n_0\ ); \cr[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(26), I1 => \cr_int_reg__0\(27), O => \cr[7]_i_6_n_0\ ); \cr[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg__0\(24), I1 => \cr_int_reg__0\(25), O => \cr[7]_i_7_n_0\ ); \cr[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(30), I1 => \cr_int_reg__0\(31), O => \cr[7]_i_8_n_0\ ); \cr[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg__0\(28), I1 => \cr_int_reg__0\(29), O => \cr[7]_i_9_n_0\ ); \cr_hold_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(0), Q => \cr_hold_reg_n_0_[0]\, R => '0' ); \cr_hold_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(1), Q => \cr_hold_reg_n_0_[1]\, R => '0' ); \cr_hold_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(2), Q => \cr_hold_reg_n_0_[2]\, R => '0' ); \cr_hold_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(3), Q => \cr_hold_reg_n_0_[3]\, R => '0' ); \cr_hold_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(4), Q => \cr_hold_reg_n_0_[4]\, R => '0' ); \cr_hold_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(5), Q => \cr_hold_reg_n_0_[5]\, R => '0' ); \cr_hold_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(6), Q => \cr_hold_reg_n_0_[6]\, R => '0' ); \cr_hold_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \cb_hold[7]_i_1_n_0\, D => cr(7), Q => \cr_hold_reg_n_0_[7]\, R => '0' ); \cr_int[11]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(18), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(10), I4 => \cr_int[15]_i_26_n_0\, I5 => \cr_int[15]_i_27_n_0\, O => \cr_int[11]_i_10_n_0\ ); \cr_int[11]_i_100\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(11), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_30_n_6\, O => \cr_int[11]_i_100_n_0\ ); \cr_int[11]_i_101\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(10), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_30_n_7\, O => \cr_int[11]_i_101_n_0\ ); \cr_int[11]_i_102\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(9), I1 => cr_int_reg7, I2 => \cr_int_reg[3]_i_16_n_4\, O => \cr_int[11]_i_102_n_0\ ); \cr_int[11]_i_104\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_104_n_0\ ); \cr_int[11]_i_105\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_105_n_0\ ); \cr_int[11]_i_106\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_106_n_0\ ); \cr_int[11]_i_107\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_107_n_0\ ); \cr_int[11]_i_109\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_7_n_6\, I1 => \cr_int_reg[31]_i_7_n_5\, O => \cr_int[11]_i_109_n_0\ ); \cr_int[11]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(17), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(9), I4 => \cr_int[11]_i_24_n_0\, I5 => \cr_int[11]_i_25_n_0\, O => \cr_int[11]_i_11_n_0\ ); \cr_int[11]_i_110\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_14_n_4\, I1 => \cr_int_reg[31]_i_7_n_7\, O => \cr_int[11]_i_110_n_0\ ); \cr_int[11]_i_111\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_14_n_6\, I1 => \cr_int_reg[31]_i_14_n_5\, O => \cr_int[11]_i_111_n_0\ ); \cr_int[11]_i_112\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_112_n_0\ ); \cr_int[11]_i_113\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_5\, I1 => \cr_int_reg[31]_i_7_n_6\, O => \cr_int[11]_i_113_n_0\ ); \cr_int[11]_i_114\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_7\, I1 => \cr_int_reg[31]_i_14_n_4\, O => \cr_int[11]_i_114_n_0\ ); \cr_int[11]_i_115\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_5\, I1 => \cr_int_reg[31]_i_14_n_6\, O => \cr_int[11]_i_115_n_0\ ); \cr_int[11]_i_117\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_11_n_7\, I1 => \cr_int_reg[31]_i_11_n_6\, O => \cr_int[11]_i_117_n_0\ ); \cr_int[11]_i_118\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_30_n_5\, I1 => \cr_int_reg[31]_i_30_n_4\, O => \cr_int[11]_i_118_n_0\ ); \cr_int[11]_i_119\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_30_n_7\, I1 => \cr_int_reg[31]_i_30_n_6\, O => \cr_int[11]_i_119_n_0\ ); \cr_int[11]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(17), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(9), I4 => \cr_int[11]_i_24_n_0\, I5 => \cr_int[11]_i_25_n_0\, O => \cr_int[11]_i_12_n_0\ ); \cr_int[11]_i_120\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_16_n_5\, I1 => \cr_int_reg[3]_i_16_n_4\, O => \cr_int[11]_i_120_n_0\ ); \cr_int[11]_i_121\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_6\, I1 => \cr_int_reg[31]_i_11_n_7\, O => \cr_int[11]_i_121_n_0\ ); \cr_int[11]_i_122\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_4\, I1 => \cr_int_reg[31]_i_30_n_5\, O => \cr_int[11]_i_122_n_0\ ); \cr_int[11]_i_123\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_6\, I1 => \cr_int_reg[31]_i_30_n_7\, O => \cr_int[11]_i_123_n_0\ ); \cr_int[11]_i_124\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_4\, I1 => \cr_int_reg[3]_i_16_n_5\, O => \cr_int[11]_i_124_n_0\ ); \cr_int[11]_i_126\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cr_int_reg[7]_0\(3), I1 => \^cr_int_reg[31]_2\(0), O => \cr_int[11]_i_126_n_0\ ); \cr_int[11]_i_127\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cr_int_reg[7]_0\(1), I1 => \^cr_int_reg[7]_0\(2), O => \cr_int[11]_i_127_n_0\ ); \cr_int[11]_i_128\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cr_int_reg[3]_0\(2), I1 => \^cr_int_reg[7]_0\(0), O => \cr_int[11]_i_128_n_0\ ); \cr_int[11]_i_129\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^cr_int_reg[3]_0\(0), I1 => \^cr_int_reg[3]_0\(1), O => \cr_int[11]_i_129_n_0\ ); \cr_int[11]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"8EEE8E888EEE8EEE" ) port map ( I0 => \cr_int_reg3__0\(8), I1 => \cr_int[11]_i_27_n_0\, I2 => \cr_int_reg[11]_i_16_n_4\, I3 => \^cr_int_reg[27]_2\(0), I4 => \cr_int_reg[11]_i_17_n_0\, I5 => \cr_int_reg[11]_i_18_n_4\, O => \cr_int[11]_i_13_n_0\ ); \cr_int[11]_i_130\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(0), I1 => \^cr_int_reg[7]_0\(3), O => \cr_int[11]_i_130_n_0\ ); \cr_int[11]_i_131\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(2), I1 => \^cr_int_reg[7]_0\(1), O => \cr_int[11]_i_131_n_0\ ); \cr_int[11]_i_132\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(0), I1 => \^cr_int_reg[3]_0\(2), O => \cr_int[11]_i_132_n_0\ ); \cr_int[11]_i_133\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[3]_0\(1), I1 => \^cr_int_reg[3]_0\(0), O => \cr_int[11]_i_133_n_0\ ); \cr_int[11]_i_134\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_39_n_4\, I1 => \cr_int_reg[31]_i_14_n_7\, O => \cr_int[11]_i_134_n_0\ ); \cr_int[11]_i_135\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_39_n_6\, I1 => \cr_int_reg[31]_i_39_n_5\, O => \cr_int[11]_i_135_n_0\ ); \cr_int[11]_i_136\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_86_n_6\, I1 => \cr_int_reg[31]_i_39_n_7\, O => \cr_int[11]_i_136_n_0\ ); \cr_int[11]_i_137\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rgb888(0), I1 => \cr_int_reg[31]_i_86_n_7\, O => \cr_int[11]_i_137_n_0\ ); \cr_int[11]_i_138\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_7\, I1 => \cr_int_reg[31]_i_39_n_4\, O => \cr_int[11]_i_138_n_0\ ); \cr_int[11]_i_139\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_5\, I1 => \cr_int_reg[31]_i_39_n_6\, O => \cr_int[11]_i_139_n_0\ ); \cr_int[11]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"6999696669996999" ) port map ( I0 => \cr_int_reg3__0\(8), I1 => \cr_int[11]_i_27_n_0\, I2 => \cr_int_reg[11]_i_16_n_4\, I3 => \^cr_int_reg[27]_2\(0), I4 => \cr_int_reg[11]_i_17_n_0\, I5 => \cr_int_reg[11]_i_18_n_4\, O => \cr_int[11]_i_14_n_0\ ); \cr_int[11]_i_140\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_7\, I1 => \cr_int_reg[31]_i_86_n_6\, O => \cr_int[11]_i_140_n_0\ ); \cr_int[11]_i_141\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_86_n_7\, I1 => rgb888(0), O => \cr_int[11]_i_141_n_0\ ); \cr_int[11]_i_142\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_16_n_7\, I1 => \cr_int_reg[3]_i_16_n_6\, O => \cr_int[11]_i_142_n_0\ ); \cr_int[11]_i_143\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_27_n_7\, I1 => \cr_int_reg[3]_i_27_n_6\, O => \cr_int[11]_i_143_n_0\ ); \cr_int[11]_i_144\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_54_n_5\, I1 => \cr_int_reg[3]_i_54_n_4\, O => \cr_int[11]_i_144_n_0\ ); \cr_int[11]_i_145\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_54_n_7\, I1 => \cr_int_reg[3]_i_54_n_6\, O => \cr_int[11]_i_145_n_0\ ); \cr_int[11]_i_146\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_6\, I1 => \cr_int_reg[3]_i_16_n_7\, O => \cr_int[11]_i_146_n_0\ ); \cr_int[11]_i_147\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_27_n_6\, I1 => \cr_int_reg[3]_i_27_n_7\, O => \cr_int[11]_i_147_n_0\ ); \cr_int[11]_i_148\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_4\, I1 => \cr_int_reg[3]_i_54_n_5\, O => \cr_int[11]_i_148_n_0\ ); \cr_int[11]_i_149\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_6\, I1 => \cr_int_reg[3]_i_54_n_7\, O => \cr_int[11]_i_149_n_0\ ); \cr_int[11]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_13\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[11]_0\(1), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[31]_2\(0), O => \cr_int[11]_i_15_n_0\ ); \cr_int[11]_i_150\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_33_n_4\, I1 => \cr_int_reg[3]_i_19_n_7\, O => \cr_int[11]_i_150_n_0\ ); \cr_int[11]_i_151\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[3]_i_33_n_6\, I1 => \cr_int_reg[3]_i_33_n_5\, O => \cr_int[11]_i_151_n_0\ ); \cr_int[11]_i_152\: unisim.vcomponents.LUT3 generic map( INIT => X"BE" ) port map ( I0 => \cr_int_reg[3]_i_65_n_6\, I1 => \cr_int_reg[3]_i_65_n_5\, I2 => rgb888(8), O => \cr_int[11]_i_152_n_0\ ); \cr_int[11]_i_153\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_19_n_7\, I1 => \cr_int_reg[3]_i_33_n_4\, O => \cr_int[11]_i_153_n_0\ ); \cr_int[11]_i_154\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_33_n_5\, I1 => \cr_int_reg[3]_i_33_n_6\, O => \cr_int[11]_i_154_n_0\ ); \cr_int[11]_i_155\: unisim.vcomponents.LUT3 generic map( INIT => X"09" ) port map ( I0 => rgb888(8), I1 => \cr_int_reg[3]_i_65_n_5\, I2 => \cr_int_reg[3]_i_65_n_6\, O => \cr_int[11]_i_155_n_0\ ); \cr_int[11]_i_156\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_94_n_7\, O => \cr_int[11]_i_156_n_0\ ); \cr_int[11]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[11]_i_10_n_0\, I1 => \cr_int[11]_i_11_n_0\, O => \cr_int[11]_i_2_n_0\ ); \cr_int[11]_i_22\: unisim.vcomponents.LUT5 generic map( INIT => X"0DFDF202" ) port map ( I0 => \cr_int_reg[11]_i_18_n_5\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \^cr_int_reg[27]_2\(0), I3 => \cr_int_reg[11]_i_16_n_5\, I4 => \cr_int[11]_i_15_n_0\, O => \cr_int[11]_i_22_n_0\ ); \cr_int[11]_i_23\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF0DFD" ) port map ( I0 => \cr_int_reg[11]_i_18_n_5\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \^cr_int_reg[27]_2\(0), I3 => \cr_int_reg[11]_i_16_n_5\, I4 => \cr_int[11]_i_15_n_0\, O => \cr_int[11]_i_23_n_0\ ); \cr_int[11]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_14\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[11]_0\(3), O => \cr_int[11]_i_24_n_0\ ); \cr_int[11]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[15]_i_38_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]\(0), O => \cr_int[11]_i_25_n_0\ ); \cr_int[11]_i_26\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(8), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_11_n_5\, I3 => cr_int_reg7, I4 => cr_int_reg6(16), O => \cr_int_reg3__0\(8) ); \cr_int[11]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_13\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[11]_0\(2), O => \cr_int[11]_i_27_n_0\ ); \cr_int[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[11]_i_12_n_0\, I1 => \cr_int[11]_i_13_n_0\, O => \cr_int[11]_i_3_n_0\ ); \cr_int[11]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[11]_i_18_n_4\, O => \cr_int[11]_i_32_n_0\ ); \cr_int[11]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[11]_i_18_n_5\, O => \cr_int[11]_i_33_n_0\ ); \cr_int[11]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[11]_i_18_n_6\, O => \cr_int[11]_i_34_n_0\ ); \cr_int[11]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_18_n_7\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_7_n_5\, O => \cr_int[11]_i_35_n_0\ ); \cr_int[11]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_37_n_0\ ); \cr_int[11]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_38_n_0\ ); \cr_int[11]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_39_n_0\ ); \cr_int[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA8A888AAA8AAA" ) port map ( I0 => \cr_int[11]_i_14_n_0\, I1 => \cr_int[11]_i_15_n_0\, I2 => \cr_int_reg[11]_i_16_n_5\, I3 => \^cr_int_reg[27]_2\(0), I4 => \cr_int_reg[11]_i_17_n_0\, I5 => \cr_int_reg[11]_i_18_n_5\, O => \cr_int[11]_i_4_n_0\ ); \cr_int[11]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_40_n_0\ ); \cr_int[11]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_42_n_0\ ); \cr_int[11]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_43_n_0\ ); \cr_int[11]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_44_n_0\ ); \cr_int[11]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_5\, O => \cr_int[11]_i_45_n_0\ ); \cr_int[11]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_5\, O => \cr_int[11]_i_47_n_0\ ); \cr_int[11]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_6\, O => \cr_int[11]_i_48_n_0\ ); \cr_int[11]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_7\, O => \cr_int[11]_i_49_n_0\ ); \cr_int[11]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFE200E200000000" ) port map ( I0 => cr_int_reg6(15), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_11_n_6\, I3 => \cr_int_reg[31]_i_11_n_4\, I4 => cr_int_reg4(7), I5 => \cr_int[11]_i_22_n_0\, O => \cr_int[11]_i_5_n_0\ ); \cr_int[11]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_4\, O => \cr_int[11]_i_50_n_0\ ); \cr_int[11]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_52_n_0\ ); \cr_int[11]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_53_n_0\ ); \cr_int[11]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_54_n_0\ ); \cr_int[11]_i_55\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_55_n_0\ ); \cr_int[11]_i_57\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(16), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_11_n_5\, O => \cr_int[11]_i_57_n_0\ ); \cr_int[11]_i_58\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(15), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_11_n_6\, O => \cr_int[11]_i_58_n_0\ ); \cr_int[11]_i_59\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(14), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_11_n_7\, O => \cr_int[11]_i_59_n_0\ ); \cr_int[11]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[15]_i_16_n_0\, I1 => \cr_int[15]_i_17_n_0\, I2 => \cr_int[11]_i_2_n_0\, O => \cr_int[11]_i_6_n_0\ ); \cr_int[11]_i_60\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(13), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_30_n_4\, O => \cr_int[11]_i_60_n_0\ ); \cr_int[11]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_65_n_0\ ); \cr_int[11]_i_66\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_66_n_0\ ); \cr_int[11]_i_67\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(0), O => \cr_int[11]_i_67_n_0\ ); \cr_int[11]_i_68\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(3), O => \cr_int[11]_i_68_n_0\ ); \cr_int[11]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[11]_i_10_n_0\, I1 => \cr_int[11]_i_11_n_0\, I2 => \cr_int[11]_i_3_n_0\, O => \cr_int[11]_i_7_n_0\ ); \cr_int[11]_i_70\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_70_n_0\ ); \cr_int[11]_i_71\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_71_n_0\ ); \cr_int[11]_i_72\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_72_n_0\ ); \cr_int[11]_i_73\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[11]_i_73_n_0\ ); \cr_int[11]_i_74\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[3]_i_32_n_4\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_14_n_6\, O => \cr_int[11]_i_74_n_0\ ); \cr_int[11]_i_75\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_41_n_4\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_7_n_6\, O => \cr_int[11]_i_75_n_0\ ); \cr_int[11]_i_76\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_41_n_5\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_7_n_7\, O => \cr_int[11]_i_76_n_0\ ); \cr_int[11]_i_77\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_41_n_6\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_14_n_4\, O => \cr_int[11]_i_77_n_0\ ); \cr_int[11]_i_78\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cr_int_reg[11]_i_41_n_7\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[31]_i_14_n_5\, O => \cr_int[11]_i_78_n_0\ ); \cr_int[11]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[11]_i_12_n_0\, I1 => \cr_int[11]_i_13_n_0\, I2 => \cr_int[11]_i_4_n_0\, O => \cr_int[11]_i_8_n_0\ ); \cr_int[11]_i_80\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_80_n_0\ ); \cr_int[11]_i_81\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_81_n_0\ ); \cr_int[11]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_82_n_0\ ); \cr_int[11]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_2\(0), O => \cr_int[11]_i_83_n_0\ ); \cr_int[11]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_6\, O => \cr_int[11]_i_84_n_0\ ); \cr_int[11]_i_85\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_7_n_7\, O => \cr_int[11]_i_85_n_0\ ); \cr_int[11]_i_86\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_4\, O => \cr_int[11]_i_86_n_0\ ); \cr_int[11]_i_87\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_5\, O => \cr_int[11]_i_87_n_0\ ); \cr_int[11]_i_88\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_5\, O => \cr_int[11]_i_88_n_0\ ); \cr_int[11]_i_89\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_6\, O => \cr_int[11]_i_89_n_0\ ); \cr_int[11]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[11]_i_5_n_0\, I1 => \cr_int[11]_i_14_n_0\, I2 => \cr_int[11]_i_23_n_0\, O => \cr_int[11]_i_9_n_0\ ); \cr_int[11]_i_90\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_30_n_7\, O => \cr_int[11]_i_90_n_0\ ); \cr_int[11]_i_91\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_4\, O => \cr_int[11]_i_91_n_0\ ); \cr_int[11]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \cr_int_reg[31]_i_11_n_5\, I1 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_93_n_0\ ); \cr_int[11]_i_94\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_94_n_0\ ); \cr_int[11]_i_95\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_95_n_0\ ); \cr_int[11]_i_96\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[11]_i_96_n_0\ ); \cr_int[11]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => \cr_int_reg[31]_i_11_n_5\, O => \cr_int[11]_i_97_n_0\ ); \cr_int[11]_i_98\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(8), I1 => cr_int_reg7, I2 => \cr_int_reg[3]_i_16_n_5\, O => \cr_int[11]_i_98_n_0\ ); \cr_int[11]_i_99\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => cr_int_reg6(12), I1 => cr_int_reg7, I2 => \cr_int_reg[31]_i_30_n_5\, O => \cr_int[11]_i_99_n_0\ ); \cr_int[15]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(22), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(14), I4 => \cr_int[19]_i_26_n_0\, I5 => \cr_int[19]_i_27_n_0\, O => \cr_int[15]_i_10_n_0\ ); \cr_int[15]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(21), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(13), I4 => \cr_int[15]_i_18_n_0\, I5 => \cr_int[15]_i_19_n_0\, O => \cr_int[15]_i_11_n_0\ ); \cr_int[15]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(21), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(13), I4 => \cr_int[15]_i_18_n_0\, I5 => \cr_int[15]_i_19_n_0\, O => \cr_int[15]_i_12_n_0\ ); \cr_int[15]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(20), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(12), I4 => \cr_int[15]_i_22_n_0\, I5 => \cr_int[15]_i_23_n_0\, O => \cr_int[15]_i_13_n_0\ ); \cr_int[15]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(20), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(12), I4 => \cr_int[15]_i_22_n_0\, I5 => \cr_int[15]_i_23_n_0\, O => \cr_int[15]_i_14_n_0\ ); \cr_int[15]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(19), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(11), I4 => \cr_int[15]_i_24_n_0\, I5 => \cr_int[15]_i_25_n_0\, O => \cr_int[15]_i_15_n_0\ ); \cr_int[15]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(19), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(11), I4 => \cr_int[15]_i_24_n_0\, I5 => \cr_int[15]_i_25_n_0\, O => \cr_int[15]_i_16_n_0\ ); \cr_int[15]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(18), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(10), I4 => \cr_int[15]_i_26_n_0\, I5 => \cr_int[15]_i_27_n_0\, O => \cr_int[15]_i_17_n_0\ ); \cr_int[15]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_15\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[15]_0\(3), O => \cr_int[15]_i_18_n_0\ ); \cr_int[15]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_49_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]_0\(0), O => \cr_int[15]_i_19_n_0\ ); \cr_int[15]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[15]_i_10_n_0\, I1 => \cr_int[15]_i_11_n_0\, O => \cr_int[15]_i_2_n_0\ ); \cr_int[15]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_14\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[15]_0\(2), O => \cr_int[15]_i_22_n_0\ ); \cr_int[15]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[15]_i_38_n_4\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]\(3), O => \cr_int[15]_i_23_n_0\ ); \cr_int[15]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_14\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[15]_0\(1), O => \cr_int[15]_i_24_n_0\ ); \cr_int[15]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[15]_i_38_n_5\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]\(2), O => \cr_int[15]_i_25_n_0\ ); \cr_int[15]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_14\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[15]_0\(0), O => \cr_int[15]_i_26_n_0\ ); \cr_int[15]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[15]_i_38_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]\(1), O => \cr_int[15]_i_27_n_0\ ); \cr_int[15]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[15]_i_29_n_0\ ); \cr_int[15]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[15]_i_12_n_0\, I1 => \cr_int[15]_i_13_n_0\, O => \cr_int[15]_i_3_n_0\ ); \cr_int[15]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[15]_i_30_n_0\ ); \cr_int[15]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[15]_i_31_n_0\ ); \cr_int[15]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[15]_i_32_n_0\ ); \cr_int[15]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(20), O => \cr_int[15]_i_33_n_0\ ); \cr_int[15]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(19), O => \cr_int[15]_i_34_n_0\ ); \cr_int[15]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(18), O => \cr_int[15]_i_35_n_0\ ); \cr_int[15]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(17), O => \cr_int[15]_i_36_n_0\ ); \cr_int[15]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[15]_i_14_n_0\, I1 => \cr_int[15]_i_15_n_0\, O => \cr_int[15]_i_4_n_0\ ); \cr_int[15]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[15]_i_40_n_0\ ); \cr_int[15]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[15]_i_41_n_0\ ); \cr_int[15]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[15]_i_42_n_0\ ); \cr_int[15]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[15]_i_43_n_0\ ); \cr_int[15]_i_48\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]\(3), O => \cr_int[15]_i_48_n_0\ ); \cr_int[15]_i_49\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]\(2), O => \cr_int[15]_i_49_n_0\ ); \cr_int[15]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[15]_i_16_n_0\, I1 => \cr_int[15]_i_17_n_0\, O => \cr_int[15]_i_5_n_0\ ); \cr_int[15]_i_50\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]\(1), O => \cr_int[15]_i_50_n_0\ ); \cr_int[15]_i_51\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]\(0), O => \cr_int[15]_i_51_n_0\ ); \cr_int[15]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[19]_i_16_n_0\, I1 => \cr_int[19]_i_17_n_0\, I2 => \cr_int[15]_i_2_n_0\, O => \cr_int[15]_i_6_n_0\ ); \cr_int[15]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[15]_i_10_n_0\, I1 => \cr_int[15]_i_11_n_0\, I2 => \cr_int[15]_i_3_n_0\, O => \cr_int[15]_i_7_n_0\ ); \cr_int[15]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[15]_i_12_n_0\, I1 => \cr_int[15]_i_13_n_0\, I2 => \cr_int[15]_i_4_n_0\, O => \cr_int[15]_i_8_n_0\ ); \cr_int[15]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[15]_i_14_n_0\, I1 => \cr_int[15]_i_15_n_0\, I2 => \cr_int[15]_i_5_n_0\, O => \cr_int[15]_i_9_n_0\ ); \cr_int[19]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(26), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(18), I4 => \cr_int[23]_i_25_n_0\, I5 => \cr_int[23]_i_26_n_0\, O => \cr_int[19]_i_10_n_0\ ); \cr_int[19]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(25), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(17), I4 => \cr_int[19]_i_18_n_0\, I5 => \cr_int[19]_i_19_n_0\, O => \cr_int[19]_i_11_n_0\ ); \cr_int[19]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(25), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(17), I4 => \cr_int[19]_i_18_n_0\, I5 => \cr_int[19]_i_19_n_0\, O => \cr_int[19]_i_12_n_0\ ); \cr_int[19]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(24), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(16), I4 => \cr_int[19]_i_22_n_0\, I5 => \cr_int[19]_i_23_n_0\, O => \cr_int[19]_i_13_n_0\ ); \cr_int[19]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(24), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(16), I4 => \cr_int[19]_i_22_n_0\, I5 => \cr_int[19]_i_23_n_0\, O => \cr_int[19]_i_14_n_0\ ); \cr_int[19]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(23), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(15), I4 => \cr_int[19]_i_24_n_0\, I5 => \cr_int[19]_i_25_n_0\, O => \cr_int[19]_i_15_n_0\ ); \cr_int[19]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(23), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(15), I4 => \cr_int[19]_i_24_n_0\, I5 => \cr_int[19]_i_25_n_0\, O => \cr_int[19]_i_16_n_0\ ); \cr_int[19]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(22), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(14), I4 => \cr_int[19]_i_26_n_0\, I5 => \cr_int[19]_i_27_n_0\, O => \cr_int[19]_i_17_n_0\ ); \cr_int[19]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_16\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[19]_0\(3), O => \cr_int[19]_i_18_n_0\ ); \cr_int[19]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_21_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_5\(0), O => \cr_int[19]_i_19_n_0\ ); \cr_int[19]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[19]_i_10_n_0\, I1 => \cr_int[19]_i_11_n_0\, O => \cr_int[19]_i_2_n_0\ ); \cr_int[19]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_15\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[19]_0\(2), O => \cr_int[19]_i_22_n_0\ ); \cr_int[19]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_49_n_4\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]_0\(3), O => \cr_int[19]_i_23_n_0\ ); \cr_int[19]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_15\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[19]_0\(1), O => \cr_int[19]_i_24_n_0\ ); \cr_int[19]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_49_n_5\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]_0\(2), O => \cr_int[19]_i_25_n_0\ ); \cr_int[19]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_15\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[19]_0\(0), O => \cr_int[19]_i_26_n_0\ ); \cr_int[19]_i_27\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_49_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[3]_0\(1), O => \cr_int[19]_i_27_n_0\ ); \cr_int[19]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[19]_i_29_n_0\ ); \cr_int[19]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[19]_i_12_n_0\, I1 => \cr_int[19]_i_13_n_0\, O => \cr_int[19]_i_3_n_0\ ); \cr_int[19]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[19]_i_30_n_0\ ); \cr_int[19]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[19]_i_31_n_0\ ); \cr_int[19]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[19]_i_32_n_0\ ); \cr_int[19]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(24), O => \cr_int[19]_i_33_n_0\ ); \cr_int[19]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(23), O => \cr_int[19]_i_34_n_0\ ); \cr_int[19]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(22), O => \cr_int[19]_i_35_n_0\ ); \cr_int[19]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(21), O => \cr_int[19]_i_36_n_0\ ); \cr_int[19]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[19]_i_38_n_0\ ); \cr_int[19]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[19]_i_39_n_0\ ); \cr_int[19]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[19]_i_14_n_0\, I1 => \cr_int[19]_i_15_n_0\, O => \cr_int[19]_i_4_n_0\ ); \cr_int[19]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[19]_i_40_n_0\ ); \cr_int[19]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[19]_i_41_n_0\ ); \cr_int[19]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[19]_i_16_n_0\, I1 => \cr_int[19]_i_17_n_0\, O => \cr_int[19]_i_5_n_0\ ); \cr_int[19]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[23]_i_16_n_0\, I1 => \cr_int[23]_i_17_n_0\, I2 => \cr_int[19]_i_2_n_0\, O => \cr_int[19]_i_6_n_0\ ); \cr_int[19]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[19]_i_10_n_0\, I1 => \cr_int[19]_i_11_n_0\, I2 => \cr_int[19]_i_3_n_0\, O => \cr_int[19]_i_7_n_0\ ); \cr_int[19]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[19]_i_12_n_0\, I1 => \cr_int[19]_i_13_n_0\, I2 => \cr_int[19]_i_4_n_0\, O => \cr_int[19]_i_8_n_0\ ); \cr_int[19]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[19]_i_14_n_0\, I1 => \cr_int[19]_i_15_n_0\, I2 => \cr_int[19]_i_5_n_0\, O => \cr_int[19]_i_9_n_0\ ); \cr_int[23]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(30), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(22), I4 => \cr_int[27]_i_10_n_0\, I5 => \cr_int[27]_i_11_n_0\, O => \cr_int[23]_i_10_n_0\ ); \cr_int[23]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(29), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(21), I4 => \cr_int[23]_i_18_n_0\, I5 => \cr_int[23]_i_19_n_0\, O => \cr_int[23]_i_11_n_0\ ); \cr_int[23]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(29), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(21), I4 => \cr_int[23]_i_18_n_0\, I5 => \cr_int[23]_i_19_n_0\, O => \cr_int[23]_i_12_n_0\ ); \cr_int[23]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(28), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(20), I4 => \cr_int[23]_i_21_n_0\, I5 => \cr_int[23]_i_22_n_0\, O => \cr_int[23]_i_13_n_0\ ); \cr_int[23]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(28), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(20), I4 => \cr_int[23]_i_21_n_0\, I5 => \cr_int[23]_i_22_n_0\, O => \cr_int[23]_i_14_n_0\ ); \cr_int[23]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(27), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(19), I4 => \cr_int[23]_i_23_n_0\, I5 => \cr_int[23]_i_24_n_0\, O => \cr_int[23]_i_15_n_0\ ); \cr_int[23]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"F4040BFB0BFBF404" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(27), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(19), I4 => \cr_int[23]_i_23_n_0\, I5 => \cr_int[23]_i_24_n_0\, O => \cr_int[23]_i_16_n_0\ ); \cr_int[23]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(26), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(18), I4 => \cr_int[23]_i_25_n_0\, I5 => \cr_int[23]_i_26_n_0\, O => \cr_int[23]_i_17_n_0\ ); \cr_int[23]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_17\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_0\(3), O => \cr_int[23]_i_18_n_0\ ); \cr_int[23]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_8_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_6\(0), O => \cr_int[23]_i_19_n_0\ ); \cr_int[23]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[23]_i_10_n_0\, I1 => \cr_int[23]_i_11_n_0\, O => \cr_int[23]_i_2_n_0\ ); \cr_int[23]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_16\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_0\(2), O => \cr_int[23]_i_21_n_0\ ); \cr_int[23]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_21_n_4\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_5\(3), O => \cr_int[23]_i_22_n_0\ ); \cr_int[23]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_16\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_0\(1), O => \cr_int[23]_i_23_n_0\ ); \cr_int[23]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_21_n_5\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_5\(2), O => \cr_int[23]_i_24_n_0\ ); \cr_int[23]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_16\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_0\(0), O => \cr_int[23]_i_25_n_0\ ); \cr_int[23]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_21_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_5\(1), O => \cr_int[23]_i_26_n_0\ ); \cr_int[23]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[23]_i_27_n_0\ ); \cr_int[23]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[23]_i_28_n_0\ ); \cr_int[23]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[23]_i_29_n_0\ ); \cr_int[23]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[23]_i_12_n_0\, I1 => \cr_int[23]_i_13_n_0\, O => \cr_int[23]_i_3_n_0\ ); \cr_int[23]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[23]_i_30_n_0\ ); \cr_int[23]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[23]_i_14_n_0\, I1 => \cr_int[23]_i_15_n_0\, O => \cr_int[23]_i_4_n_0\ ); \cr_int[23]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[23]_i_16_n_0\, I1 => \cr_int[23]_i_17_n_0\, O => \cr_int[23]_i_5_n_0\ ); \cr_int[23]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[27]_i_7_n_0\, I1 => \cr_int[27]_i_8_n_0\, I2 => \cr_int[23]_i_2_n_0\, O => \cr_int[23]_i_6_n_0\ ); \cr_int[23]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[23]_i_10_n_0\, I1 => \cr_int[23]_i_11_n_0\, I2 => \cr_int[23]_i_3_n_0\, O => \cr_int[23]_i_7_n_0\ ); \cr_int[23]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[23]_i_12_n_0\, I1 => \cr_int[23]_i_13_n_0\, I2 => \cr_int[23]_i_4_n_0\, O => \cr_int[23]_i_8_n_0\ ); \cr_int[23]_i_9\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[23]_i_14_n_0\, I1 => \cr_int[23]_i_15_n_0\, I2 => \cr_int[23]_i_5_n_0\, O => \cr_int[23]_i_9_n_0\ ); \cr_int[27]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \rgb888[8]_17\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_1\(0), I3 => \^cr_int_reg[23]_1\(0), O => \cr_int[27]_i_10_n_0\ ); \cr_int[27]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[31]_i_8_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \rgb888[0]_6\(1), O => \cr_int[27]_i_11_n_0\ ); \cr_int[27]_i_12\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[27]_i_12_n_0\ ); \cr_int[27]_i_13\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, O => \cr_int[27]_i_13_n_0\ ); \cr_int[27]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \cr_int[27]_i_7_n_0\, I1 => \cr_int[27]_i_8_n_0\, O => \cr_int[27]_i_2_n_0\ ); \cr_int[27]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_3_n_0\ ); \cr_int[27]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_4_n_0\ ); \cr_int[27]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_5_n_0\ ); \cr_int[27]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[27]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_6_n_0\ ); \cr_int[27]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"4B44B4BB4B444B44" ) port map ( I0 => \cr_int_reg[31]_i_12_n_1\, I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \rgb888[8]_18\(0), I3 => \^cr_int_reg[31]_2\(1), I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[27]_i_7_n_0\ ); \cr_int[27]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => cr_int_reg7, I1 => cr_int_reg6(30), I2 => \cr_int_reg[31]_i_11_n_4\, I3 => cr_int_reg4(22), I4 => \cr_int[27]_i_10_n_0\, I5 => \cr_int[27]_i_11_n_0\, O => \cr_int[27]_i_8_n_0\ ); \cr_int[31]_i_100\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => rgb888(13), I1 => rgb888(11), I2 => rgb888(10), I3 => rgb888(12), I4 => rgb888(14), I5 => rgb888(15), O => \cr_int[31]_i_100_n_0\ ); \cr_int[31]_i_103\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \cr_int[31]_i_103_n_0\ ); \cr_int[31]_i_108\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_108_n_0\ ); \cr_int[31]_i_109\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_109_n_0\ ); \cr_int[31]_i_110\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_110_n_0\ ); \cr_int[31]_i_111\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_111_n_0\ ); \cr_int[31]_i_112\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_112_n_0\ ); \cr_int[31]_i_113\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(4), I1 => rgb888(2), O => \cr_int[31]_i_113_n_0\ ); \cr_int[31]_i_114\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(3), I1 => rgb888(1), O => \cr_int[31]_i_114_n_0\ ); \cr_int[31]_i_115\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(2), I1 => rgb888(0), O => \cr_int[31]_i_115_n_0\ ); \cr_int[31]_i_116\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(1), O => \cr_int[31]_i_116_n_0\ ); \cr_int[31]_i_117\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(6), O => \cr_int[31]_i_117_n_0\ ); \cr_int[31]_i_118\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(7), I1 => rgb888(5), O => \cr_int[31]_i_118_n_0\ ); \cr_int[31]_i_119\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(6), I1 => rgb888(4), O => \cr_int[31]_i_119_n_0\ ); \cr_int[31]_i_120\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(5), I1 => rgb888(3), O => \cr_int[31]_i_120_n_0\ ); \cr_int[31]_i_121\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \cr_int[31]_i_121_n_0\ ); \cr_int[31]_i_122\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(15), I1 => rgb888(14), O => \cr_int[31]_i_122_n_0\ ); \cr_int[31]_i_123\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(14), O => \cr_int[31]_i_123_n_0\ ); \cr_int[31]_i_124\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(15), I1 => rgb888(13), O => \cr_int[31]_i_124_n_0\ ); \cr_int[31]_i_125\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(14), I1 => rgb888(12), O => \cr_int[31]_i_125_n_0\ ); \cr_int[31]_i_126\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(13), I1 => rgb888(11), O => \cr_int[31]_i_126_n_0\ ); \cr_int[31]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \rgb888[8]_18\(0), I1 => \^cr_int_reg[31]_2\(1), O => \cr_int[31]_i_13_n_0\ ); \cr_int[31]_i_15\: unisim.vcomponents.LUT3 generic map( INIT => X"60" ) port map ( I0 => \^cr_int_reg[27]_0\, I1 => rgb888(7), I2 => \cr_int_reg[31]_i_48_n_2\, O => \cr_int[31]_i_15_n_0\ ); \cr_int[31]_i_16\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[27]_1\(1), I1 => \cr_int_reg[31]_i_48_n_2\, O => \cr_int[31]_i_16_n_0\ ); \cr_int[31]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => \^cr_int_reg[27]_0\, O => \cr_int[31]_i_17_n_0\ ); \cr_int[31]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => \^cr_int_reg[27]_0\, O => \cr_int[31]_i_18_n_0\ ); \cr_int[31]_i_19\: unisim.vcomponents.LUT3 generic map( INIT => X"17" ) port map ( I0 => \cr_int_reg[31]_i_48_n_2\, I1 => \^cr_int_reg[27]_0\, I2 => rgb888(7), O => \cr_int[31]_i_19_n_0\ ); \cr_int[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000DD0D0000" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[31]_i_8_n_1\, I2 => \^cr_int_reg[31]_2\(1), I3 => \rgb888[8]_18\(0), I4 => \cr_int_reg[31]_i_11_n_4\, I5 => \cr_int_reg[31]_i_12_n_1\, O => \cr_int[31]_i_2_n_0\ ); \cr_int[31]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \^cr_int_reg[27]_0\, I1 => rgb888(7), I2 => \cr_int[31]_i_16_n_0\, I3 => \cr_int_reg[31]_i_48_n_2\, O => \cr_int[31]_i_20_n_0\ ); \cr_int[31]_i_22\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_6\(1), O => \cr_int[31]_i_22_n_0\ ); \cr_int[31]_i_23\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_6\(0), O => \cr_int[31]_i_23_n_0\ ); \cr_int[31]_i_25\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \cr_int[31]_i_25_n_0\ ); \cr_int[31]_i_26\: unisim.vcomponents.LUT2 generic map( INIT => X"4" ) port map ( I0 => \cr_int_reg[31]_i_63_n_2\, I1 => \^di\(0), O => \cr_int[31]_i_26_n_0\ ); \cr_int[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[31]_i_3_n_0\ ); \cr_int[31]_i_31\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => rgb888(22), I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(17), I4 => rgb888(19), I5 => rgb888(21), O => \cr_int[31]_i_31_n_0\ ); \cr_int[31]_i_32\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(23), I1 => \cr_int[31]_i_79_n_0\, O => \cr_int[31]_i_32_n_0\ ); \cr_int[31]_i_33\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(23), I1 => \cr_int[31]_i_79_n_0\, O => \cr_int[31]_i_33_n_0\ ); \cr_int[31]_i_34\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(23), I1 => \cr_int[31]_i_79_n_0\, O => \cr_int[31]_i_34_n_0\ ); \cr_int[31]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"95" ) port map ( I0 => rgb888(23), I1 => \cr_int[31]_i_80_n_0\, I2 => rgb888(22), O => \cr_int[31]_i_35_n_0\ ); \cr_int[31]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(30), O => \cr_int[31]_i_37_n_0\ ); \cr_int[31]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(29), O => \cr_int[31]_i_38_n_0\ ); \cr_int[31]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[31]_i_4_n_0\ ); \cr_int[31]_i_40\: unisim.vcomponents.LUT6 generic map( INIT => X"8888888888888882" ) port map ( I0 => \cr_int_reg[31]_i_48_n_7\, I1 => rgb888(5), I2 => rgb888(3), I3 => rgb888(1), I4 => rgb888(2), I5 => rgb888(4), O => \cr_int[31]_i_40_n_0\ ); \cr_int[31]_i_41\: unisim.vcomponents.LUT5 generic map( INIT => X"EEEEEEEB" ) port map ( I0 => \cr_int_reg[31]_i_91_n_4\, I1 => rgb888(4), I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), O => \cr_int[31]_i_41_n_0\ ); \cr_int[31]_i_42\: unisim.vcomponents.LUT5 generic map( INIT => X"99999996" ) port map ( I0 => \cr_int_reg[31]_i_91_n_4\, I1 => rgb888(4), I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), O => \cr_int[31]_i_42_n_0\ ); \cr_int[31]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"82" ) port map ( I0 => \cr_int_reg[31]_i_91_n_6\, I1 => rgb888(2), I2 => rgb888(1), O => \cr_int[31]_i_43_n_0\ ); \cr_int[31]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cr_int_reg[27]_1\(1), I1 => \cr_int_reg[31]_i_48_n_2\, I2 => \cr_int[31]_i_40_n_0\, O => \cr_int[31]_i_44_n_0\ ); \cr_int[31]_i_45\: unisim.vcomponents.LUT4 generic map( INIT => X"1EE1" ) port map ( I0 => \cr_int[31]_i_92_n_0\, I1 => \cr_int_reg[31]_i_91_n_4\, I2 => \^cr_int_reg[27]_1\(0), I3 => \cr_int_reg[31]_i_48_n_7\, O => \cr_int[31]_i_45_n_0\ ); \cr_int[31]_i_46\: unisim.vcomponents.LUT6 generic map( INIT => X"6969699999999996" ) port map ( I0 => rgb888(4), I1 => \cr_int_reg[31]_i_91_n_4\, I2 => \cr_int_reg[31]_i_91_n_5\, I3 => rgb888(2), I4 => rgb888(1), I5 => rgb888(3), O => \cr_int[31]_i_46_n_0\ ); \cr_int[31]_i_47\: unisim.vcomponents.LUT5 generic map( INIT => X"817E7E81" ) port map ( I0 => \cr_int_reg[31]_i_91_n_6\, I1 => rgb888(2), I2 => rgb888(1), I3 => rgb888(3), I4 => \cr_int_reg[31]_i_91_n_5\, O => \cr_int[31]_i_47_n_0\ ); \cr_int[31]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[31]_i_5_n_0\ ); \cr_int[31]_i_50\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_5\(3), O => \cr_int[31]_i_50_n_0\ ); \cr_int[31]_i_51\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_5\(2), O => \cr_int[31]_i_51_n_0\ ); \cr_int[31]_i_52\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_5\(1), O => \cr_int[31]_i_52_n_0\ ); \cr_int[31]_i_53\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[0]_5\(0), O => \cr_int[31]_i_53_n_0\ ); \cr_int[31]_i_55\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \cr_int[31]_i_100_n_0\, I1 => \cr_int_reg[31]_i_63_n_2\, O => \cr_int[31]_i_55_n_0\ ); \cr_int[31]_i_56\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAA00000000" ) port map ( I0 => rgb888(14), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => \cr_int_reg[31]_i_63_n_7\, O => \cr_int[31]_i_56_n_0\ ); \cr_int[31]_i_57\: unisim.vcomponents.LUT6 generic map( INIT => X"BFFFEAAA2AAA8000" ) port map ( I0 => \cr_int_reg[31]_i_101_n_1\, I1 => rgb888(11), I2 => rgb888(10), I3 => rgb888(12), I4 => rgb888(13), I5 => \cr_int_reg[31]_i_102_n_4\, O => \cr_int[31]_i_57_n_0\ ); \cr_int[31]_i_58\: unisim.vcomponents.LUT5 generic map( INIT => X"BFEA2A80" ) port map ( I0 => \cr_int_reg[31]_i_101_n_6\, I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(12), I4 => \cr_int_reg[31]_i_102_n_5\, O => \cr_int[31]_i_58_n_0\ ); \cr_int[31]_i_59\: unisim.vcomponents.LUT3 generic map( INIT => X"36" ) port map ( I0 => \cr_int[31]_i_100_n_0\, I1 => \^di\(0), I2 => \cr_int_reg[31]_i_63_n_2\, O => \cr_int[31]_i_59_n_0\ ); \cr_int[31]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"6555559A65556555" ) port map ( I0 => \cr_int[31]_i_2_n_0\, I1 => \cr_int_reg[31]_i_12_n_1\, I2 => \cr_int_reg[31]_i_11_n_4\, I3 => \cr_int[31]_i_13_n_0\, I4 => \cr_int_reg[31]_i_8_n_1\, I5 => \^cr_int_reg[27]_2\(0), O => \cr_int[31]_i_6_n_0\ ); \cr_int[31]_i_60\: unisim.vcomponents.LUT4 generic map( INIT => X"7887" ) port map ( I0 => \cr_int_reg[31]_i_63_n_7\, I1 => \^cr_int_reg[31]_0\, I2 => \cr_int_reg[31]_i_63_n_2\, I3 => \cr_int[31]_i_100_n_0\, O => \cr_int[31]_i_60_n_0\ ); \cr_int[31]_i_61\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int[31]_i_57_n_0\, I1 => \^cr_int_reg[31]_0\, I2 => \cr_int_reg[31]_i_63_n_7\, O => \cr_int[31]_i_61_n_0\ ); \cr_int[31]_i_62\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int[31]_i_58_n_0\, I1 => \cr_int_reg[31]_i_102_n_4\, I2 => \^cr_int_reg[31]_1\, I3 => \cr_int_reg[31]_i_101_n_1\, O => \cr_int[31]_i_62_n_0\ ); \cr_int[31]_i_71\: unisim.vcomponents.LUT6 generic map( INIT => X"00000001FFFFFFFE" ) port map ( I0 => rgb888(21), I1 => rgb888(19), I2 => rgb888(17), I3 => rgb888(18), I4 => rgb888(20), I5 => rgb888(22), O => \cr_int[31]_i_71_n_0\ ); \cr_int[31]_i_72\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFE" ) port map ( I0 => rgb888(20), I1 => rgb888(18), I2 => rgb888(17), I3 => rgb888(19), I4 => rgb888(21), O => \cr_int[31]_i_72_n_0\ ); \cr_int[31]_i_73\: unisim.vcomponents.LUT5 generic map( INIT => X"99999996" ) port map ( I0 => \cr_int_reg[3]_i_26_n_1\, I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(17), I4 => rgb888(19), O => \cr_int[31]_i_73_n_0\ ); \cr_int[31]_i_74\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(18), I1 => rgb888(17), O => \cr_int[31]_i_74_n_0\ ); \cr_int[31]_i_75\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAA955555555" ) port map ( I0 => rgb888(22), I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(17), I4 => rgb888(19), I5 => rgb888(21), O => \cr_int[31]_i_75_n_0\ ); \cr_int[31]_i_76\: unisim.vcomponents.LUT6 generic map( INIT => X"CCCCCCC999999993" ) port map ( I0 => \cr_int_reg[3]_i_26_n_1\, I1 => rgb888(21), I2 => rgb888(19), I3 => rgb888(17), I4 => rgb888(18), I5 => rgb888(20), O => \cr_int[31]_i_76_n_0\ ); \cr_int[31]_i_77\: unisim.vcomponents.LUT5 generic map( INIT => X"AAA99995" ) port map ( I0 => rgb888(20), I1 => \cr_int_reg[3]_i_26_n_1\, I2 => rgb888(18), I3 => rgb888(17), I4 => rgb888(19), O => \cr_int[31]_i_77_n_0\ ); \cr_int[31]_i_78\: unisim.vcomponents.LUT4 generic map( INIT => X"6A95" ) port map ( I0 => \cr_int_reg[3]_i_26_n_1\, I1 => rgb888(18), I2 => rgb888(17), I3 => rgb888(19), O => \cr_int[31]_i_78_n_0\ ); \cr_int[31]_i_79\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => rgb888(21), I1 => rgb888(19), I2 => rgb888(17), I3 => rgb888(18), I4 => rgb888(20), I5 => rgb888(22), O => \cr_int[31]_i_79_n_0\ ); \cr_int[31]_i_80\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => rgb888(20), I1 => rgb888(18), I2 => rgb888(17), I3 => rgb888(19), I4 => rgb888(21), O => \cr_int[31]_i_80_n_0\ ); \cr_int[31]_i_81\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(28), O => \cr_int[31]_i_81_n_0\ ); \cr_int[31]_i_82\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(27), O => \cr_int[31]_i_82_n_0\ ); \cr_int[31]_i_83\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(26), O => \cr_int[31]_i_83_n_0\ ); \cr_int[31]_i_84\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cr_int_reg[31]_i_11_n_4\, I1 => cr_int_reg7, I2 => cr_int_reg6(25), O => \cr_int[31]_i_84_n_0\ ); \cr_int[31]_i_85\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), O => \cr_int[31]_i_85_n_0\ ); \cr_int[31]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(2), I1 => \cr_int_reg[31]_i_91_n_6\, O => \cr_int[31]_i_87_n_0\ ); \cr_int[31]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(1), I1 => \cr_int_reg[31]_i_91_n_7\, O => \cr_int[31]_i_88_n_0\ ); \cr_int[31]_i_89\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[31]_i_86_n_4\, I1 => rgb888(0), O => \cr_int[31]_i_89_n_0\ ); \cr_int[31]_i_90\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg[31]_i_86_n_5\, O => \cr_int[31]_i_90_n_0\ ); \cr_int[31]_i_92\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => rgb888(3), I1 => rgb888(1), I2 => rgb888(2), I3 => rgb888(4), O => \cr_int[31]_i_92_n_0\ ); \cr_int[31]_i_93\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(7), O => \cr_int[31]_i_93_n_0\ ); \cr_int[31]_i_94\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]_0\(3), O => \cr_int[31]_i_94_n_0\ ); \cr_int[31]_i_95\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]_0\(2), O => \cr_int[31]_i_95_n_0\ ); \cr_int[31]_i_96\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]_0\(1), O => \cr_int[31]_i_96_n_0\ ); \cr_int[31]_i_97\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^cr_int_reg[27]_2\(0), I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \rgb888[3]_0\(0), O => \cr_int[31]_i_97_n_0\ ); \cr_int[3]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_12\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[7]_1\(0), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[3]_0\(2), O => \cr_int[3]_i_10_n_0\ ); \cr_int[3]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_31_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_41_n_6\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_14_n_4\, O => \cr_int[3]_i_11_n_0\ ); \cr_int[3]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(1), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[3]_i_16_n_4\, I3 => cr_int_reg7, I4 => cr_int_reg6(9), O => \cr_int_reg3__0\(1) ); \cr_int[3]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_12\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[3]_2\(1), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[3]_0\(1), O => \cr_int[3]_i_13_n_0\ ); \cr_int[3]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_31_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_41_n_7\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_14_n_5\, O => \cr_int[3]_i_14_n_0\ ); \cr_int[3]_i_17\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^cr_int_reg[3]_0\(0), I1 => \^cr_int_reg[3]_1\(0), I2 => \^cr_int_reg[3]_2\(0), O => \cr_int[3]_i_17_n_0\ ); \cr_int[3]_i_18\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cr_int_reg[31]_i_14_n_6\, I1 => \cr_int_reg[11]_i_17_n_0\, I2 => \cr_int_reg[3]_i_32_n_4\, O => \cr_int[3]_i_18_n_0\ ); \cr_int[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(2), I1 => \cr_int[3]_i_10_n_0\, I2 => \cr_int[3]_i_11_n_0\, O => \cr_int[3]_i_2_n_0\ ); \cr_int[3]_i_22\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_5\, O => \cr_int[3]_i_22_n_0\ ); \cr_int[3]_i_23\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_6\, O => \cr_int[3]_i_23_n_0\ ); \cr_int[3]_i_24\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_16_n_7\, O => \cr_int[3]_i_24_n_0\ ); \cr_int[3]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_27_n_6\, O => \cr_int[3]_i_25_n_0\ ); \cr_int[3]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(18), I1 => rgb888(17), I2 => \cr_int_reg[3]_i_26_n_6\, O => \cr_int[3]_i_28_n_0\ ); \cr_int[3]_i_29\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \cr_int_reg[3]_i_26_n_7\, I1 => rgb888(17), O => \cr_int[3]_i_29_n_0\ ); \cr_int[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(1), I1 => \cr_int[3]_i_13_n_0\, I2 => \cr_int[3]_i_14_n_0\, O => \cr_int[3]_i_3_n_0\ ); \cr_int[3]_i_30\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[3]_i_27_n_4\, I1 => rgb888(16), O => \cr_int[3]_i_30_n_0\ ); \cr_int[3]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \cr_int_reg[3]_i_27_n_5\, O => \cr_int[3]_i_31_n_0\ ); \cr_int[3]_i_34\: unisim.vcomponents.LUT4 generic map( INIT => X"BE28" ) port map ( I0 => \cr_int_reg[31]_i_101_n_7\, I1 => rgb888(10), I2 => rgb888(11), I3 => \cr_int_reg[31]_i_102_n_6\, O => \cr_int[3]_i_34_n_0\ ); \cr_int[3]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => rgb888(10), I1 => \cr_int_reg[3]_i_64_n_4\, I2 => \cr_int_reg[31]_i_102_n_7\, O => \cr_int[3]_i_35_n_0\ ); \cr_int[3]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg[3]_i_64_n_5\, I1 => rgb888(9), I2 => \cr_int_reg[3]_i_70_n_4\, O => \cr_int[3]_i_36_n_0\ ); \cr_int[3]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cr_int_reg[3]_i_64_n_5\, I1 => rgb888(9), I2 => \cr_int_reg[3]_i_70_n_4\, O => \cr_int[3]_i_37_n_0\ ); \cr_int[3]_i_38\: unisim.vcomponents.LUT6 generic map( INIT => X"9669696969969696" ) port map ( I0 => \cr_int[3]_i_34_n_0\, I1 => \cr_int_reg[31]_i_102_n_5\, I2 => rgb888(12), I3 => rgb888(11), I4 => rgb888(10), I5 => \cr_int_reg[31]_i_101_n_6\, O => \cr_int[3]_i_38_n_0\ ); \cr_int[3]_i_39\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \cr_int_reg[31]_i_101_n_7\, I1 => rgb888(10), I2 => rgb888(11), I3 => \cr_int_reg[31]_i_102_n_6\, I4 => \cr_int[3]_i_35_n_0\, O => \cr_int[3]_i_39_n_0\ ); \cr_int[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"00E2E2FF" ) port map ( I0 => cr_int_reg6(8), I1 => cr_int_reg7, I2 => \cr_int_reg[3]_i_16_n_5\, I3 => \cr_int[3]_i_17_n_0\, I4 => \cr_int[3]_i_18_n_0\, O => \cr_int[3]_i_4_n_0\ ); \cr_int[3]_i_40\: unisim.vcomponents.LUT6 generic map( INIT => X"E81717E817E8E817" ) port map ( I0 => \cr_int_reg[3]_i_70_n_4\, I1 => rgb888(9), I2 => \cr_int_reg[3]_i_64_n_5\, I3 => \cr_int_reg[31]_i_102_n_7\, I4 => rgb888(10), I5 => \cr_int_reg[3]_i_64_n_4\, O => \cr_int[3]_i_40_n_0\ ); \cr_int[3]_i_41\: unisim.vcomponents.LUT5 generic map( INIT => X"69969696" ) port map ( I0 => \cr_int_reg[3]_i_70_n_4\, I1 => rgb888(9), I2 => \cr_int_reg[3]_i_64_n_5\, I3 => \cr_int_reg[3]_i_70_n_5\, I4 => rgb888(8), O => \cr_int[3]_i_41_n_0\ ); \cr_int[3]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[3]_0\(1), O => \cr_int[3]_i_43_n_0\ ); \cr_int[3]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[3]_0\(0), O => \cr_int[3]_i_44_n_0\ ); \cr_int[3]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_19_n_7\, O => \cr_int[3]_i_45_n_0\ ); \cr_int[3]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_33_n_4\, O => \cr_int[3]_i_46_n_0\ ); \cr_int[3]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_7\, O => \cr_int[3]_i_47_n_0\ ); \cr_int[3]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_27_n_7\, O => \cr_int[3]_i_48_n_0\ ); \cr_int[3]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_4\, O => \cr_int[3]_i_49_n_0\ ); \cr_int[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(3), I1 => \cr_int[7]_i_17_n_0\, I2 => \cr_int[7]_i_18_n_0\, I3 => \cr_int[3]_i_2_n_0\, O => \cr_int[3]_i_5_n_0\ ); \cr_int[3]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_5\, O => \cr_int[3]_i_50_n_0\ ); \cr_int[3]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_54_n_6\, O => \cr_int[3]_i_51_n_0\ ); \cr_int[3]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(23), O => \cr_int[3]_i_52_n_0\ ); \cr_int[3]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(22), O => \cr_int[3]_i_53_n_0\ ); \cr_int[3]_i_55\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(21), I1 => rgb888(23), O => \cr_int[3]_i_55_n_0\ ); \cr_int[3]_i_56\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(20), I1 => rgb888(22), O => \cr_int[3]_i_56_n_0\ ); \cr_int[3]_i_57\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(19), I1 => rgb888(21), O => \cr_int[3]_i_57_n_0\ ); \cr_int[3]_i_58\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(18), I1 => rgb888(20), O => \cr_int[3]_i_58_n_0\ ); \cr_int[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(2), I1 => \cr_int[3]_i_10_n_0\, I2 => \cr_int[3]_i_11_n_0\, I3 => \cr_int[3]_i_3_n_0\, O => \cr_int[3]_i_6_n_0\ ); \cr_int[3]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_6\, O => \cr_int[3]_i_60_n_0\ ); \cr_int[3]_i_61\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_14_n_7\, O => \cr_int[3]_i_61_n_0\ ); \cr_int[3]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_4\, O => \cr_int[3]_i_62_n_0\ ); \cr_int[3]_i_63\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_5\, O => \cr_int[3]_i_63_n_0\ ); \cr_int[3]_i_66\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(8), I1 => \cr_int_reg[3]_i_70_n_5\, I2 => \cr_int_reg[3]_i_64_n_6\, O => \cr_int[3]_i_66_n_0\ ); \cr_int[3]_i_67\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[3]_i_64_n_7\, I1 => \cr_int_reg[3]_i_70_n_6\, O => \cr_int[3]_i_67_n_0\ ); \cr_int[3]_i_68\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[3]_i_65_n_4\, I1 => \cr_int_reg[3]_i_70_n_7\, O => \cr_int[3]_i_68_n_0\ ); \cr_int[3]_i_69\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \cr_int_reg[3]_i_65_n_5\, I1 => rgb888(8), O => \cr_int[3]_i_69_n_0\ ); \cr_int[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(1), I1 => \cr_int[3]_i_13_n_0\, I2 => \cr_int[3]_i_14_n_0\, I3 => \cr_int[3]_i_4_n_0\, O => \cr_int[3]_i_7_n_0\ ); \cr_int[3]_i_71\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_94_n_7\, O => \cr_int[3]_i_71_n_0\ ); \cr_int[3]_i_72\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_33_n_5\, O => \cr_int[3]_i_72_n_0\ ); \cr_int[3]_i_73\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_33_n_6\, O => \cr_int[3]_i_73_n_0\ ); \cr_int[3]_i_74\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(8), I1 => \cr_int_reg[3]_i_65_n_5\, O => \cr_int[3]_i_74_n_0\ ); \cr_int[3]_i_75\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[3]_i_65_n_6\, O => \cr_int[3]_i_75_n_0\ ); \cr_int[3]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(17), I1 => rgb888(19), O => \cr_int[3]_i_76_n_0\ ); \cr_int[3]_i_77\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(16), I1 => rgb888(18), O => \cr_int[3]_i_77_n_0\ ); \cr_int[3]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(17), O => \cr_int[3]_i_78_n_0\ ); \cr_int[3]_i_79\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(16), O => \cr_int[3]_i_79_n_0\ ); \cr_int[3]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"1DE2E21D" ) port map ( I0 => cr_int_reg6(8), I1 => cr_int_reg7, I2 => \cr_int_reg[3]_i_16_n_5\, I3 => \cr_int[3]_i_17_n_0\, I4 => \cr_int[3]_i_18_n_0\, O => \cr_int[3]_i_8_n_0\ ); \cr_int[3]_i_80\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(0), O => \cr_int[3]_i_80_n_0\ ); \cr_int[3]_i_81\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_6\, O => \cr_int[3]_i_81_n_0\ ); \cr_int[3]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_39_n_7\, O => \cr_int[3]_i_82_n_0\ ); \cr_int[3]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_86_n_6\, O => \cr_int[3]_i_83_n_0\ ); \cr_int[3]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cr_int_reg[31]_i_86_n_7\, O => \cr_int[3]_i_84_n_0\ ); \cr_int[3]_i_85\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(15), I1 => rgb888(13), O => \cr_int[3]_i_85_n_0\ ); \cr_int[3]_i_86\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(12), I1 => rgb888(14), O => \cr_int[3]_i_86_n_0\ ); \cr_int[3]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(11), I1 => rgb888(13), O => \cr_int[3]_i_87_n_0\ ); \cr_int[3]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(10), I1 => rgb888(12), O => \cr_int[3]_i_88_n_0\ ); \cr_int[3]_i_89\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(9), I1 => rgb888(11), O => \cr_int[3]_i_89_n_0\ ); \cr_int[3]_i_9\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(2), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_30_n_7\, I3 => cr_int_reg7, I4 => cr_int_reg6(10), O => \cr_int_reg3__0\(2) ); \cr_int[3]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(8), I1 => rgb888(10), O => \cr_int[3]_i_90_n_0\ ); \cr_int[3]_i_91\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(9), O => \cr_int[3]_i_91_n_0\ ); \cr_int[3]_i_92\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(8), O => \cr_int[3]_i_92_n_0\ ); \cr_int[3]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(12), I1 => rgb888(10), O => \cr_int[3]_i_93_n_0\ ); \cr_int[3]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(11), I1 => rgb888(9), O => \cr_int[3]_i_94_n_0\ ); \cr_int[3]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(10), I1 => rgb888(8), O => \cr_int[3]_i_95_n_0\ ); \cr_int[3]_i_96\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(9), O => \cr_int[3]_i_96_n_0\ ); \cr_int[7]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(5), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_30_n_4\, I3 => cr_int_reg7, I4 => cr_int_reg6(13), O => \cr_int_reg3__0\(5) ); \cr_int[7]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_13\(0), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[7]_1\(3), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[7]_0\(2), O => \cr_int[7]_i_11_n_0\ ); \cr_int[7]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_16_n_7\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_18_n_7\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_7_n_5\, O => \cr_int[7]_i_12_n_0\ ); \cr_int[7]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(4), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_30_n_5\, I3 => cr_int_reg7, I4 => cr_int_reg6(12), O => \cr_int_reg3__0\(4) ); \cr_int[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_12\(3), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[7]_1\(2), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[7]_0\(1), O => \cr_int[7]_i_14_n_0\ ); \cr_int[7]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_31_n_4\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_41_n_4\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_7_n_6\, O => \cr_int[7]_i_15_n_0\ ); \cr_int[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(3), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_30_n_6\, I3 => cr_int_reg7, I4 => cr_int_reg6(11), O => \cr_int_reg3__0\(3) ); \cr_int[7]_i_17\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_12\(2), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[7]_1\(1), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[7]_0\(0), O => \cr_int[7]_i_17_n_0\ ); \cr_int[7]_i_18\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \cr_int_reg[11]_i_31_n_5\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_41_n_5\, I3 => \cr_int_reg[11]_i_17_n_0\, I4 => \cr_int_reg[31]_i_7_n_7\, O => \cr_int[7]_i_18_n_0\ ); \cr_int[7]_i_19\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(7), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_11_n_6\, I3 => cr_int_reg7, I4 => cr_int_reg6(15), O => cr_int_reg3(7) ); \cr_int[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"555556A6AAAA56A6" ) port map ( I0 => \cr_int[11]_i_22_n_0\, I1 => cr_int_reg6(15), I2 => cr_int_reg7, I3 => \cr_int_reg[31]_i_11_n_6\, I4 => \cr_int_reg[31]_i_11_n_4\, I5 => cr_int_reg4(7), O => \cr_int[7]_i_2_n_0\ ); \cr_int[7]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"7477" ) port map ( I0 => \cr_int_reg[11]_i_16_n_6\, I1 => \^cr_int_reg[27]_2\(0), I2 => \cr_int_reg[11]_i_17_n_0\, I3 => \cr_int_reg[11]_i_18_n_6\, O => \cr_int[7]_i_20_n_0\ ); \cr_int[7]_i_21\: unisim.vcomponents.LUT5 generic map( INIT => X"44477747" ) port map ( I0 => \rgb888[8]_13\(1), I1 => \^cr_int_reg[31]_2\(1), I2 => \^cr_int_reg[11]_0\(0), I3 => \^cr_int_reg[3]_1\(0), I4 => \^cr_int_reg[7]_0\(3), O => \cr_int[7]_i_21_n_0\ ); \cr_int[7]_i_22\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => cr_int_reg4(6), I1 => \cr_int_reg[31]_i_11_n_4\, I2 => \cr_int_reg[31]_i_11_n_7\, I3 => cr_int_reg7, I4 => cr_int_reg6(14), O => \cr_int_reg3__0\(6) ); \cr_int[7]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(2), O => \cr_int[7]_i_25_n_0\ ); \cr_int[7]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(1), O => \cr_int[7]_i_26_n_0\ ); \cr_int[7]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[7]_0\(0), O => \cr_int[7]_i_27_n_0\ ); \cr_int[7]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^cr_int_reg[3]_0\(2), O => \cr_int[7]_i_28_n_0\ ); \cr_int[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(5), I1 => \cr_int[7]_i_11_n_0\, I2 => \cr_int[7]_i_12_n_0\, O => \cr_int[7]_i_3_n_0\ ); \cr_int[7]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(4), I1 => \cr_int[7]_i_14_n_0\, I2 => \cr_int[7]_i_15_n_0\, O => \cr_int[7]_i_4_n_0\ ); \cr_int[7]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cr_int_reg3__0\(3), I1 => \cr_int[7]_i_17_n_0\, I2 => \cr_int[7]_i_18_n_0\, O => \cr_int[7]_i_5_n_0\ ); \cr_int[7]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"99969666" ) port map ( I0 => cr_int_reg3(7), I1 => \cr_int[11]_i_22_n_0\, I2 => \cr_int[7]_i_20_n_0\, I3 => \cr_int[7]_i_21_n_0\, I4 => \cr_int_reg3__0\(6), O => \cr_int[7]_i_6_n_0\ ); \cr_int[7]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int[7]_i_3_n_0\, I1 => \cr_int[7]_i_20_n_0\, I2 => \cr_int[7]_i_21_n_0\, I3 => \cr_int_reg3__0\(6), O => \cr_int[7]_i_7_n_0\ ); \cr_int[7]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(5), I1 => \cr_int[7]_i_11_n_0\, I2 => \cr_int[7]_i_12_n_0\, I3 => \cr_int[7]_i_4_n_0\, O => \cr_int[7]_i_8_n_0\ ); \cr_int[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \cr_int_reg3__0\(4), I1 => \cr_int[7]_i_14_n_0\, I2 => \cr_int[7]_i_15_n_0\, I3 => \cr_int[7]_i_5_n_0\, O => \cr_int[7]_i_9_n_0\ ); \cr_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[3]_i_1_n_7\, Q => \cr_int_reg_n_0_[0]\, R => '0' ); \cr_int_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[11]_i_1_n_5\, Q => \cr_int_reg__0\(10), R => '0' ); \cr_int_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[11]_i_1_n_4\, Q => \cr_int_reg__0\(11), R => '0' ); \cr_int_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[7]_i_1_n_0\, CO(3) => \cr_int_reg[11]_i_1_n_0\, CO(2) => \cr_int_reg[11]_i_1_n_1\, CO(1) => \cr_int_reg[11]_i_1_n_2\, CO(0) => \cr_int_reg[11]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[11]_i_2_n_0\, DI(2) => \cr_int[11]_i_3_n_0\, DI(1) => \cr_int[11]_i_4_n_0\, DI(0) => \cr_int[11]_i_5_n_0\, O(3) => \cr_int_reg[11]_i_1_n_4\, O(2) => \cr_int_reg[11]_i_1_n_5\, O(1) => \cr_int_reg[11]_i_1_n_6\, O(0) => \cr_int_reg[11]_i_1_n_7\, S(3) => \cr_int[11]_i_6_n_0\, S(2) => \cr_int[11]_i_7_n_0\, S(1) => \cr_int[11]_i_8_n_0\, S(0) => \cr_int[11]_i_9_n_0\ ); \cr_int_reg[11]_i_103\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_125_n_0\, CO(3) => \cr_int_reg[11]_i_103_n_0\, CO(2) => \cr_int_reg[11]_i_103_n_1\, CO(1) => \cr_int_reg[11]_i_103_n_2\, CO(0) => \cr_int_reg[11]_i_103_n_3\, CYINIT => '0', DI(3) => \cr_int[11]_i_126_n_0\, DI(2) => \cr_int[11]_i_127_n_0\, DI(1) => \cr_int[11]_i_128_n_0\, DI(0) => \cr_int[11]_i_129_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_103_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_130_n_0\, S(2) => \cr_int[11]_i_131_n_0\, S(1) => \cr_int[11]_i_132_n_0\, S(0) => \cr_int[11]_i_133_n_0\ ); \cr_int_reg[11]_i_108\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_108_n_0\, CO(2) => \cr_int_reg[11]_i_108_n_1\, CO(1) => \cr_int_reg[11]_i_108_n_2\, CO(0) => \cr_int_reg[11]_i_108_n_3\, CYINIT => '1', DI(3) => \cr_int[11]_i_134_n_0\, DI(2) => \cr_int[11]_i_135_n_0\, DI(1) => \cr_int[11]_i_136_n_0\, DI(0) => \cr_int[11]_i_137_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_108_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_138_n_0\, S(2) => \cr_int[11]_i_139_n_0\, S(1) => \cr_int[11]_i_140_n_0\, S(0) => \cr_int[11]_i_141_n_0\ ); \cr_int_reg[11]_i_116\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_116_n_0\, CO(2) => \cr_int_reg[11]_i_116_n_1\, CO(1) => \cr_int_reg[11]_i_116_n_2\, CO(0) => \cr_int_reg[11]_i_116_n_3\, CYINIT => '1', DI(3) => \cr_int[11]_i_142_n_0\, DI(2) => \cr_int[11]_i_143_n_0\, DI(1) => \cr_int[11]_i_144_n_0\, DI(0) => \cr_int[11]_i_145_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_116_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_146_n_0\, S(2) => \cr_int[11]_i_147_n_0\, S(1) => \cr_int[11]_i_148_n_0\, S(0) => \cr_int[11]_i_149_n_0\ ); \cr_int_reg[11]_i_125\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_125_n_0\, CO(2) => \cr_int_reg[11]_i_125_n_1\, CO(1) => \cr_int_reg[11]_i_125_n_2\, CO(0) => \cr_int_reg[11]_i_125_n_3\, CYINIT => '1', DI(3) => \cr_int[11]_i_150_n_0\, DI(2) => \cr_int[11]_i_151_n_0\, DI(1) => \cr_int[11]_i_152_n_0\, DI(0) => \cb_int_reg[3]_i_94_n_7\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_125_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_153_n_0\, S(2) => \cr_int[11]_i_154_n_0\, S(1) => \cr_int[11]_i_155_n_0\, S(0) => \cr_int[11]_i_156_n_0\ ); \cr_int_reg[11]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_31_n_0\, CO(3) => \cr_int_reg[11]_i_16_n_0\, CO(2) => \cr_int_reg[11]_i_16_n_1\, CO(1) => \cr_int_reg[11]_i_16_n_2\, CO(0) => \cr_int_reg[11]_i_16_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_16_n_4\, O(2) => \cr_int_reg[11]_i_16_n_5\, O(1) => \cr_int_reg[11]_i_16_n_6\, O(0) => \cr_int_reg[11]_i_16_n_7\, S(3) => \cr_int[11]_i_32_n_0\, S(2) => \cr_int[11]_i_33_n_0\, S(1) => \cr_int[11]_i_34_n_0\, S(0) => \cr_int[11]_i_35_n_0\ ); \cr_int_reg[11]_i_17\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_36_n_0\, CO(3) => \cr_int_reg[11]_i_17_n_0\, CO(2) => \cr_int_reg[11]_i_17_n_1\, CO(1) => \cr_int_reg[11]_i_17_n_2\, CO(0) => \cr_int_reg[11]_i_17_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \^cr_int_reg[27]_2\(0), DI(1) => \^cr_int_reg[27]_2\(0), DI(0) => \^cr_int_reg[27]_2\(0), O(3 downto 0) => \NLW_cr_int_reg[11]_i_17_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_37_n_0\, S(2) => \cr_int[11]_i_38_n_0\, S(1) => \cr_int[11]_i_39_n_0\, S(0) => \cr_int[11]_i_40_n_0\ ); \cr_int_reg[11]_i_18\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_41_n_0\, CO(3) => \cr_int_reg[15]_1\(0), CO(2) => \cr_int_reg[11]_i_18_n_1\, CO(1) => \cr_int_reg[11]_i_18_n_2\, CO(0) => \cr_int_reg[11]_i_18_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_18_n_4\, O(2) => \cr_int_reg[11]_i_18_n_5\, O(1) => \cr_int_reg[11]_i_18_n_6\, O(0) => \cr_int_reg[11]_i_18_n_7\, S(3) => \cr_int[11]_i_42_n_0\, S(2) => \cr_int[11]_i_43_n_0\, S(1) => \cr_int[11]_i_44_n_0\, S(0) => \cr_int[11]_i_45_n_0\ ); \cr_int_reg[11]_i_19\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_46_n_0\, CO(3) => \cr_int_reg[11]_i_19_n_0\, CO(2) => \cr_int_reg[11]_i_19_n_1\, CO(1) => \cr_int_reg[11]_i_19_n_2\, CO(0) => \cr_int_reg[11]_i_19_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(16 downto 13), S(3) => \cr_int[11]_i_47_n_0\, S(2) => \cr_int[11]_i_48_n_0\, S(1) => \cr_int[11]_i_49_n_0\, S(0) => \cr_int[11]_i_50_n_0\ ); \cr_int_reg[11]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_51_n_0\, CO(3) => cr_int_reg7, CO(2) => \cr_int_reg[11]_i_20_n_1\, CO(1) => \cr_int_reg[11]_i_20_n_2\, CO(0) => \cr_int_reg[11]_i_20_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \cr_int_reg[31]_i_11_n_4\, DI(1) => \cr_int_reg[31]_i_11_n_4\, DI(0) => \cr_int_reg[31]_i_11_n_4\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_20_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_52_n_0\, S(2) => \cr_int[11]_i_53_n_0\, S(1) => \cr_int[11]_i_54_n_0\, S(0) => \cr_int[11]_i_55_n_0\ ); \cr_int_reg[11]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_56_n_0\, CO(3) => \cr_int_reg[11]_i_21_n_0\, CO(2) => \cr_int_reg[11]_i_21_n_1\, CO(1) => \cr_int_reg[11]_i_21_n_2\, CO(0) => \cr_int_reg[11]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(8 downto 5), S(3) => \cr_int[11]_i_57_n_0\, S(2) => \cr_int[11]_i_58_n_0\, S(1) => \cr_int[11]_i_59_n_0\, S(0) => \cr_int[11]_i_60_n_0\ ); \cr_int_reg[11]_i_29\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[7]_i_23_n_0\, CO(3) => \cr_int_reg[11]_i_29_n_0\, CO(2) => \cr_int_reg[11]_i_29_n_1\, CO(1) => \cr_int_reg[11]_i_29_n_2\, CO(0) => \cr_int_reg[11]_i_29_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[11]_0\(3 downto 0), S(3) => \cr_int[11]_i_65_n_0\, S(2) => \cr_int[11]_i_66_n_0\, S(1) => \cr_int[11]_i_67_n_0\, S(0) => \cr_int[11]_i_68_n_0\ ); \cr_int_reg[11]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_69_n_0\, CO(3) => \^cr_int_reg[3]_1\(0), CO(2) => \cr_int_reg[11]_i_30_n_1\, CO(1) => \cr_int_reg[11]_i_30_n_2\, CO(0) => \cr_int_reg[11]_i_30_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \^cr_int_reg[31]_2\(1), DI(1) => \^cr_int_reg[31]_2\(1), DI(0) => \^cr_int_reg[31]_2\(1), O(3 downto 0) => \NLW_cr_int_reg[11]_i_30_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_70_n_0\, S(2) => \cr_int[11]_i_71_n_0\, S(1) => \cr_int[11]_i_72_n_0\, S(0) => \cr_int[11]_i_73_n_0\ ); \cr_int_reg[11]_i_31\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_31_n_0\, CO(2) => \cr_int_reg[11]_i_31_n_1\, CO(1) => \cr_int_reg[11]_i_31_n_2\, CO(0) => \cr_int_reg[11]_i_31_n_3\, CYINIT => \cr_int[11]_i_74_n_0\, DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_31_n_4\, O(2) => \cr_int_reg[11]_i_31_n_5\, O(1) => \cr_int_reg[11]_i_31_n_6\, O(0) => \cr_int_reg[11]_i_31_n_7\, S(3) => \cr_int[11]_i_75_n_0\, S(2) => \cr_int[11]_i_76_n_0\, S(1) => \cr_int[11]_i_77_n_0\, S(0) => \cr_int[11]_i_78_n_0\ ); \cr_int_reg[11]_i_36\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_79_n_0\, CO(3) => \cr_int_reg[11]_i_36_n_0\, CO(2) => \cr_int_reg[11]_i_36_n_1\, CO(1) => \cr_int_reg[11]_i_36_n_2\, CO(0) => \cr_int_reg[11]_i_36_n_3\, CYINIT => '0', DI(3) => \^cr_int_reg[27]_2\(0), DI(2) => \^cr_int_reg[27]_2\(0), DI(1) => \^cr_int_reg[27]_2\(0), DI(0) => \^cr_int_reg[27]_2\(0), O(3 downto 0) => \NLW_cr_int_reg[11]_i_36_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_80_n_0\, S(2) => \cr_int[11]_i_81_n_0\, S(1) => \cr_int[11]_i_82_n_0\, S(0) => \cr_int[11]_i_83_n_0\ ); \cr_int_reg[11]_i_41\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_32_n_0\, CO(3) => \cr_int_reg[11]_i_41_n_0\, CO(2) => \cr_int_reg[11]_i_41_n_1\, CO(1) => \cr_int_reg[11]_i_41_n_2\, CO(0) => \cr_int_reg[11]_i_41_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_41_n_4\, O(2) => \cr_int_reg[11]_i_41_n_5\, O(1) => \cr_int_reg[11]_i_41_n_6\, O(0) => \cr_int_reg[11]_i_41_n_7\, S(3) => \cr_int[11]_i_84_n_0\, S(2) => \cr_int[11]_i_85_n_0\, S(1) => \cr_int[11]_i_86_n_0\, S(0) => \cr_int[11]_i_87_n_0\ ); \cr_int_reg[11]_i_46\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_15_n_0\, CO(3) => \cr_int_reg[11]_i_46_n_0\, CO(2) => \cr_int_reg[11]_i_46_n_1\, CO(1) => \cr_int_reg[11]_i_46_n_2\, CO(0) => \cr_int_reg[11]_i_46_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(12 downto 9), S(3) => \cr_int[11]_i_88_n_0\, S(2) => \cr_int[11]_i_89_n_0\, S(1) => \cr_int[11]_i_90_n_0\, S(0) => \cr_int[11]_i_91_n_0\ ); \cr_int_reg[11]_i_51\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_92_n_0\, CO(3) => \cr_int_reg[11]_i_51_n_0\, CO(2) => \cr_int_reg[11]_i_51_n_1\, CO(1) => \cr_int_reg[11]_i_51_n_2\, CO(0) => \cr_int_reg[11]_i_51_n_3\, CYINIT => '0', DI(3) => \cr_int_reg[31]_i_11_n_4\, DI(2) => \cr_int_reg[31]_i_11_n_4\, DI(1) => \cr_int_reg[31]_i_11_n_4\, DI(0) => \cr_int[11]_i_93_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_51_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_94_n_0\, S(2) => \cr_int[11]_i_95_n_0\, S(1) => \cr_int[11]_i_96_n_0\, S(0) => \cr_int[11]_i_97_n_0\ ); \cr_int_reg[11]_i_56\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[11]_i_56_n_0\, CO(2) => \cr_int_reg[11]_i_56_n_1\, CO(1) => \cr_int_reg[11]_i_56_n_2\, CO(0) => \cr_int_reg[11]_i_56_n_3\, CYINIT => \cr_int[11]_i_98_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(4 downto 1), S(3) => \cr_int[11]_i_99_n_0\, S(2) => \cr_int[11]_i_100_n_0\, S(1) => \cr_int[11]_i_101_n_0\, S(0) => \cr_int[11]_i_102_n_0\ ); \cr_int_reg[11]_i_69\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_103_n_0\, CO(3) => \cr_int_reg[11]_i_69_n_0\, CO(2) => \cr_int_reg[11]_i_69_n_1\, CO(1) => \cr_int_reg[11]_i_69_n_2\, CO(0) => \cr_int_reg[11]_i_69_n_3\, CYINIT => '0', DI(3) => \^cr_int_reg[31]_2\(1), DI(2) => \^cr_int_reg[31]_2\(1), DI(1) => \^cr_int_reg[31]_2\(1), DI(0) => \^cr_int_reg[31]_2\(1), O(3 downto 0) => \NLW_cr_int_reg[11]_i_69_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_104_n_0\, S(2) => \cr_int[11]_i_105_n_0\, S(1) => \cr_int[11]_i_106_n_0\, S(0) => \cr_int[11]_i_107_n_0\ ); \cr_int_reg[11]_i_79\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_108_n_0\, CO(3) => \cr_int_reg[11]_i_79_n_0\, CO(2) => \cr_int_reg[11]_i_79_n_1\, CO(1) => \cr_int_reg[11]_i_79_n_2\, CO(0) => \cr_int_reg[11]_i_79_n_3\, CYINIT => '0', DI(3) => \^cr_int_reg[27]_2\(0), DI(2) => \cr_int[11]_i_109_n_0\, DI(1) => \cr_int[11]_i_110_n_0\, DI(0) => \cr_int[11]_i_111_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_79_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_112_n_0\, S(2) => \cr_int[11]_i_113_n_0\, S(1) => \cr_int[11]_i_114_n_0\, S(0) => \cr_int[11]_i_115_n_0\ ); \cr_int_reg[11]_i_92\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_116_n_0\, CO(3) => \cr_int_reg[11]_i_92_n_0\, CO(2) => \cr_int_reg[11]_i_92_n_1\, CO(1) => \cr_int_reg[11]_i_92_n_2\, CO(0) => \cr_int_reg[11]_i_92_n_3\, CYINIT => '0', DI(3) => \cr_int[11]_i_117_n_0\, DI(2) => \cr_int[11]_i_118_n_0\, DI(1) => \cr_int[11]_i_119_n_0\, DI(0) => \cr_int[11]_i_120_n_0\, O(3 downto 0) => \NLW_cr_int_reg[11]_i_92_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[11]_i_121_n_0\, S(2) => \cr_int[11]_i_122_n_0\, S(1) => \cr_int[11]_i_123_n_0\, S(0) => \cr_int[11]_i_124_n_0\ ); \cr_int_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[15]_i_1_n_7\, Q => \cr_int_reg__0\(12), R => '0' ); \cr_int_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[15]_i_1_n_6\, Q => \cr_int_reg__0\(13), R => '0' ); \cr_int_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[15]_i_1_n_5\, Q => \cr_int_reg__0\(14), R => '0' ); \cr_int_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[15]_i_1_n_4\, Q => \cr_int_reg__0\(15), R => '0' ); \cr_int_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_1_n_0\, CO(3) => \cr_int_reg[15]_i_1_n_0\, CO(2) => \cr_int_reg[15]_i_1_n_1\, CO(1) => \cr_int_reg[15]_i_1_n_2\, CO(0) => \cr_int_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[15]_i_2_n_0\, DI(2) => \cr_int[15]_i_3_n_0\, DI(1) => \cr_int[15]_i_4_n_0\, DI(0) => \cr_int[15]_i_5_n_0\, O(3) => \cr_int_reg[15]_i_1_n_4\, O(2) => \cr_int_reg[15]_i_1_n_5\, O(1) => \cr_int_reg[15]_i_1_n_6\, O(0) => \cr_int_reg[15]_i_1_n_7\, S(3) => \cr_int[15]_i_6_n_0\, S(2) => \cr_int[15]_i_7_n_0\, S(1) => \cr_int[15]_i_8_n_0\, S(0) => \cr_int[15]_i_9_n_0\ ); \cr_int_reg[15]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_19_n_0\, CO(3) => \cr_int_reg[15]_i_20_n_0\, CO(2) => \cr_int_reg[15]_i_20_n_1\, CO(1) => \cr_int_reg[15]_i_20_n_2\, CO(0) => \cr_int_reg[15]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(20 downto 17), S(3) => \cr_int[15]_i_29_n_0\, S(2) => \cr_int[15]_i_30_n_0\, S(1) => \cr_int[15]_i_31_n_0\, S(0) => \cr_int[15]_i_32_n_0\ ); \cr_int_reg[15]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_21_n_0\, CO(3) => \cr_int_reg[15]_i_21_n_0\, CO(2) => \cr_int_reg[15]_i_21_n_1\, CO(1) => \cr_int_reg[15]_i_21_n_2\, CO(0) => \cr_int_reg[15]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(12 downto 9), S(3) => \cr_int[15]_i_33_n_0\, S(2) => \cr_int[15]_i_34_n_0\, S(1) => \cr_int[15]_i_35_n_0\, S(0) => \cr_int[15]_i_36_n_0\ ); \cr_int_reg[15]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_29_n_0\, CO(3) => \cr_int_reg[15]_i_28_n_0\, CO(2) => \cr_int_reg[15]_i_28_n_1\, CO(1) => \cr_int_reg[15]_i_28_n_2\, CO(0) => \cr_int_reg[15]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[15]_0\(3 downto 0), S(3) => \cr_int[15]_i_40_n_0\, S(2) => \cr_int[15]_i_41_n_0\, S(1) => \cr_int[15]_i_42_n_0\, S(0) => \cr_int[15]_i_43_n_0\ ); \cr_int_reg[15]_i_38\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_16_n_0\, CO(3) => \cr_int_reg[15]_i_38_n_0\, CO(2) => \cr_int_reg[15]_i_38_n_1\, CO(1) => \cr_int_reg[15]_i_38_n_2\, CO(0) => \cr_int_reg[15]_i_38_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[15]_i_38_n_4\, O(2) => \cr_int_reg[15]_i_38_n_5\, O(1) => \cr_int_reg[15]_i_38_n_6\, O(0) => \cr_int_reg[15]_i_38_n_7\, S(3) => \cr_int[15]_i_48_n_0\, S(2) => \cr_int[15]_i_49_n_0\, S(1) => \cr_int[15]_i_50_n_0\, S(0) => \cr_int[15]_i_51_n_0\ ); \cr_int_reg[16]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[19]_i_1_n_7\, Q => \cr_int_reg__0\(16), R => '0' ); \cr_int_reg[17]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[19]_i_1_n_6\, Q => \cr_int_reg__0\(17), R => '0' ); \cr_int_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[19]_i_1_n_5\, Q => \cr_int_reg__0\(18), R => '0' ); \cr_int_reg[19]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[19]_i_1_n_4\, Q => \cr_int_reg__0\(19), R => '0' ); \cr_int_reg[19]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_1_n_0\, CO(3) => \cr_int_reg[19]_i_1_n_0\, CO(2) => \cr_int_reg[19]_i_1_n_1\, CO(1) => \cr_int_reg[19]_i_1_n_2\, CO(0) => \cr_int_reg[19]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[19]_i_2_n_0\, DI(2) => \cr_int[19]_i_3_n_0\, DI(1) => \cr_int[19]_i_4_n_0\, DI(0) => \cr_int[19]_i_5_n_0\, O(3) => \cr_int_reg[19]_i_1_n_4\, O(2) => \cr_int_reg[19]_i_1_n_5\, O(1) => \cr_int_reg[19]_i_1_n_6\, O(0) => \cr_int_reg[19]_i_1_n_7\, S(3) => \cr_int[19]_i_6_n_0\, S(2) => \cr_int[19]_i_7_n_0\, S(1) => \cr_int[19]_i_8_n_0\, S(0) => \cr_int[19]_i_9_n_0\ ); \cr_int_reg[19]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_20_n_0\, CO(3) => \cr_int_reg[19]_i_20_n_0\, CO(2) => \cr_int_reg[19]_i_20_n_1\, CO(1) => \cr_int_reg[19]_i_20_n_2\, CO(0) => \cr_int_reg[19]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(24 downto 21), S(3) => \cr_int[19]_i_29_n_0\, S(2) => \cr_int[19]_i_30_n_0\, S(1) => \cr_int[19]_i_31_n_0\, S(0) => \cr_int[19]_i_32_n_0\ ); \cr_int_reg[19]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_21_n_0\, CO(3) => \cr_int_reg[19]_i_21_n_0\, CO(2) => \cr_int_reg[19]_i_21_n_1\, CO(1) => \cr_int_reg[19]_i_21_n_2\, CO(0) => \cr_int_reg[19]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(16 downto 13), S(3) => \cr_int[19]_i_33_n_0\, S(2) => \cr_int[19]_i_34_n_0\, S(1) => \cr_int[19]_i_35_n_0\, S(0) => \cr_int[19]_i_36_n_0\ ); \cr_int_reg[19]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_28_n_0\, CO(3) => \cr_int_reg[19]_i_28_n_0\, CO(2) => \cr_int_reg[19]_i_28_n_1\, CO(1) => \cr_int_reg[19]_i_28_n_2\, CO(0) => \cr_int_reg[19]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[19]_0\(3 downto 0), S(3) => \cr_int[19]_i_38_n_0\, S(2) => \cr_int[19]_i_39_n_0\, S(1) => \cr_int[19]_i_40_n_0\, S(0) => \cr_int[19]_i_41_n_0\ ); \cr_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[3]_i_1_n_6\, Q => \cr_int_reg_n_0_[1]\, R => '0' ); \cr_int_reg[20]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[23]_i_1_n_7\, Q => \cr_int_reg__0\(20), R => '0' ); \cr_int_reg[21]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[23]_i_1_n_6\, Q => \cr_int_reg__0\(21), R => '0' ); \cr_int_reg[22]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[23]_i_1_n_5\, Q => \cr_int_reg__0\(22), R => '0' ); \cr_int_reg[23]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[23]_i_1_n_4\, Q => \cr_int_reg__0\(23), R => '0' ); \cr_int_reg[23]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_1_n_0\, CO(3) => \cr_int_reg[23]_i_1_n_0\, CO(2) => \cr_int_reg[23]_i_1_n_1\, CO(1) => \cr_int_reg[23]_i_1_n_2\, CO(0) => \cr_int_reg[23]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[23]_i_2_n_0\, DI(2) => \cr_int[23]_i_3_n_0\, DI(1) => \cr_int[23]_i_4_n_0\, DI(0) => \cr_int[23]_i_5_n_0\, O(3) => \cr_int_reg[23]_i_1_n_4\, O(2) => \cr_int_reg[23]_i_1_n_5\, O(1) => \cr_int_reg[23]_i_1_n_6\, O(0) => \cr_int_reg[23]_i_1_n_7\, S(3) => \cr_int[23]_i_6_n_0\, S(2) => \cr_int[23]_i_7_n_0\, S(1) => \cr_int[23]_i_8_n_0\, S(0) => \cr_int[23]_i_9_n_0\ ); \cr_int_reg[23]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_20_n_0\, CO(3) => \cr_int_reg[23]_i_20_n_0\, CO(2) => \cr_int_reg[23]_i_20_n_1\, CO(1) => \cr_int_reg[23]_i_20_n_2\, CO(0) => \cr_int_reg[23]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg6(28 downto 25), S(3) => \cr_int[23]_i_27_n_0\, S(2) => \cr_int[23]_i_28_n_0\, S(1) => \cr_int[23]_i_29_n_0\, S(0) => \cr_int[23]_i_30_n_0\ ); \cr_int_reg[24]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[27]_i_1_n_7\, Q => \cr_int_reg__0\(24), R => '0' ); \cr_int_reg[25]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[27]_i_1_n_6\, Q => \cr_int_reg__0\(25), R => '0' ); \cr_int_reg[26]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[27]_i_1_n_5\, Q => \cr_int_reg__0\(26), R => '0' ); \cr_int_reg[27]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[27]_i_1_n_4\, Q => \cr_int_reg__0\(27), R => '0' ); \cr_int_reg[27]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[23]_i_1_n_0\, CO(3) => \cr_int_reg[27]_i_1_n_0\, CO(2) => \cr_int_reg[27]_i_1_n_1\, CO(1) => \cr_int_reg[27]_i_1_n_2\, CO(0) => \cr_int_reg[27]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_2_n_0\, DI(2) => \cr_int[31]_i_2_n_0\, DI(1) => \cr_int[31]_i_2_n_0\, DI(0) => \cr_int[27]_i_2_n_0\, O(3) => \cr_int_reg[27]_i_1_n_4\, O(2) => \cr_int_reg[27]_i_1_n_5\, O(1) => \cr_int_reg[27]_i_1_n_6\, O(0) => \cr_int_reg[27]_i_1_n_7\, S(3) => \cr_int[27]_i_3_n_0\, S(2) => \cr_int[27]_i_4_n_0\, S(1) => \cr_int[27]_i_5_n_0\, S(0) => \cr_int[27]_i_6_n_0\ ); \cr_int_reg[27]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[23]_i_20_n_0\, CO(3 downto 1) => \NLW_cr_int_reg[27]_i_9_CO_UNCONNECTED\(3 downto 1), CO(0) => \cr_int_reg[27]_i_9_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[27]_i_9_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => cr_int_reg6(30 downto 29), S(3 downto 2) => B"00", S(1) => \cr_int[27]_i_12_n_0\, S(0) => \cr_int[27]_i_13_n_0\ ); \cr_int_reg[28]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[31]_i_1_n_7\, Q => \cr_int_reg__0\(28), R => '0' ); \cr_int_reg[29]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[31]_i_1_n_6\, Q => \cr_int_reg__0\(29), R => '0' ); \cr_int_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[3]_i_1_n_5\, Q => \cr_int_reg_n_0_[2]\, R => '0' ); \cr_int_reg[30]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[31]_i_1_n_5\, Q => \cr_int_reg__0\(30), R => '0' ); \cr_int_reg[31]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[31]_i_1_n_4\, Q => \cr_int_reg__0\(31), R => '0' ); \cr_int_reg[31]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[27]_i_1_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_1_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_1_n_1\, CO(1) => \cr_int_reg[31]_i_1_n_2\, CO(0) => \cr_int_reg[31]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \cr_int[31]_i_2_n_0\, DI(1) => \cr_int[31]_i_2_n_0\, DI(0) => \cr_int[31]_i_2_n_0\, O(3) => \cr_int_reg[31]_i_1_n_4\, O(2) => \cr_int_reg[31]_i_1_n_5\, O(1) => \cr_int_reg[31]_i_1_n_6\, O(0) => \cr_int_reg[31]_i_1_n_7\, S(3) => \cr_int[31]_i_3_n_0\, S(2) => \cr_int[31]_i_4_n_0\, S(1) => \cr_int[31]_i_5_n_0\, S(0) => \cr_int[31]_i_6_n_0\ ); \cr_int_reg[31]_i_101\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_64_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_101_n_1\, CO(1) => \NLW_cr_int_reg[31]_i_101_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[31]_i_101_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1 downto 0) => rgb888(15 downto 14), O(3 downto 2) => \NLW_cr_int_reg[31]_i_101_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[31]_i_101_n_6\, O(0) => \cr_int_reg[31]_i_101_n_7\, S(3 downto 2) => B"01", S(1) => \cr_int[31]_i_121_n_0\, S(0) => \cr_int[31]_i_122_n_0\ ); \cr_int_reg[31]_i_102\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_70_n_0\, CO(3) => \cr_int_reg[31]_i_102_n_0\, CO(2) => \cr_int_reg[31]_i_102_n_1\, CO(1) => \cr_int_reg[31]_i_102_n_2\, CO(0) => \cr_int_reg[31]_i_102_n_3\, CYINIT => '0', DI(3) => rgb888(14), DI(2 downto 0) => rgb888(15 downto 13), O(3) => \cr_int_reg[31]_i_102_n_4\, O(2) => \cr_int_reg[31]_i_102_n_5\, O(1) => \cr_int_reg[31]_i_102_n_6\, O(0) => \cr_int_reg[31]_i_102_n_7\, S(3) => \cr_int[31]_i_123_n_0\, S(2) => \cr_int[31]_i_124_n_0\, S(1) => \cr_int[31]_i_125_n_0\, S(0) => \cr_int[31]_i_126_n_0\ ); \cr_int_reg[31]_i_11\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_30_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_11_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_11_n_1\, CO(1) => \cr_int_reg[31]_i_11_n_2\, CO(0) => \cr_int_reg[31]_i_11_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \cr_int[31]_i_31_n_0\, O(3) => \cr_int_reg[31]_i_11_n_4\, O(2) => \cr_int_reg[31]_i_11_n_5\, O(1) => \cr_int_reg[31]_i_11_n_6\, O(0) => \cr_int_reg[31]_i_11_n_7\, S(3) => \cr_int[31]_i_32_n_0\, S(2) => \cr_int[31]_i_33_n_0\, S(1) => \cr_int[31]_i_34_n_0\, S(0) => \cr_int[31]_i_35_n_0\ ); \cr_int_reg[31]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_36_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_12_n_1\, CO(1) => \NLW_cr_int_reg[31]_i_12_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[31]_i_12_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => cr_int_reg4(22 downto 21), S(3 downto 2) => B"01", S(1) => \cr_int[31]_i_37_n_0\, S(0) => \cr_int[31]_i_38_n_0\ ); \cr_int_reg[31]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_39_n_0\, CO(3) => \cr_int_reg[31]_i_14_n_0\, CO(2) => \cr_int_reg[31]_i_14_n_1\, CO(1) => \cr_int_reg[31]_i_14_n_2\, CO(0) => \cr_int_reg[31]_i_14_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_40_n_0\, DI(2) => \cr_int[31]_i_41_n_0\, DI(1) => \cr_int[31]_i_42_n_0\, DI(0) => \cr_int[31]_i_43_n_0\, O(3) => \cr_int_reg[31]_i_14_n_4\, O(2) => \cr_int_reg[31]_i_14_n_5\, O(1) => \cr_int_reg[31]_i_14_n_6\, O(0) => \cr_int_reg[31]_i_14_n_7\, S(3) => \cr_int[31]_i_44_n_0\, S(2) => \cr_int[31]_i_45_n_0\, S(1) => \cr_int[31]_i_46_n_0\, S(0) => \cr_int[31]_i_47_n_0\ ); \cr_int_reg[31]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_49_n_0\, CO(3) => \cr_int_reg[31]_i_21_n_0\, CO(2) => \cr_int_reg[31]_i_21_n_1\, CO(1) => \cr_int_reg[31]_i_21_n_2\, CO(0) => \cr_int_reg[31]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[31]_i_21_n_4\, O(2) => \cr_int_reg[31]_i_21_n_5\, O(1) => \cr_int_reg[31]_i_21_n_6\, O(0) => \cr_int_reg[31]_i_21_n_7\, S(3) => \cr_int[31]_i_50_n_0\, S(2) => \cr_int[31]_i_51_n_0\, S(1) => \cr_int[31]_i_52_n_0\, S(0) => \cr_int[31]_i_53_n_0\ ); \cr_int_reg[31]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_19_n_0\, CO(3) => \cr_int_reg[31]_i_24_n_0\, CO(2) => \cr_int_reg[31]_i_24_n_1\, CO(1) => \cr_int_reg[31]_i_24_n_2\, CO(0) => \cr_int_reg[31]_i_24_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_55_n_0\, DI(2) => \cr_int[31]_i_56_n_0\, DI(1) => \cr_int[31]_i_57_n_0\, DI(0) => \cr_int[31]_i_58_n_0\, O(3 downto 0) => \^cr_int_reg[7]_0\(3 downto 0), S(3) => \cr_int[31]_i_59_n_0\, S(2) => \cr_int[31]_i_60_n_0\, S(1) => \cr_int[31]_i_61_n_0\, S(0) => \cr_int[31]_i_62_n_0\ ); \cr_int_reg[31]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_16_n_0\, CO(3) => \cr_int_reg[31]_i_30_n_0\, CO(2) => \cr_int_reg[31]_i_30_n_1\, CO(1) => \cr_int_reg[31]_i_30_n_2\, CO(0) => \cr_int_reg[31]_i_30_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_71_n_0\, DI(2) => \cr_int[31]_i_72_n_0\, DI(1) => \cr_int[31]_i_73_n_0\, DI(0) => \cr_int[31]_i_74_n_0\, O(3) => \cr_int_reg[31]_i_30_n_4\, O(2) => \cr_int_reg[31]_i_30_n_5\, O(1) => \cr_int_reg[31]_i_30_n_6\, O(0) => \cr_int_reg[31]_i_30_n_7\, S(3) => \cr_int[31]_i_75_n_0\, S(2) => \cr_int[31]_i_76_n_0\, S(1) => \cr_int[31]_i_77_n_0\, S(0) => \cr_int[31]_i_78_n_0\ ); \cr_int_reg[31]_i_36\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_21_n_0\, CO(3) => \cr_int_reg[31]_i_36_n_0\, CO(2) => \cr_int_reg[31]_i_36_n_1\, CO(1) => \cr_int_reg[31]_i_36_n_2\, CO(0) => \cr_int_reg[31]_i_36_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => cr_int_reg4(20 downto 17), S(3) => \cr_int[31]_i_81_n_0\, S(2) => \cr_int[31]_i_82_n_0\, S(1) => \cr_int[31]_i_83_n_0\, S(0) => \cr_int[31]_i_84_n_0\ ); \cr_int_reg[31]_i_39\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[31]_i_39_n_0\, CO(2) => \cr_int_reg[31]_i_39_n_1\, CO(1) => \cr_int_reg[31]_i_39_n_2\, CO(0) => \cr_int_reg[31]_i_39_n_3\, CYINIT => '0', DI(3) => \cr_int[31]_i_85_n_0\, DI(2) => rgb888(1), DI(1) => \cr_int_reg[31]_i_86_n_4\, DI(0) => '0', O(3) => \cr_int_reg[31]_i_39_n_4\, O(2) => \cr_int_reg[31]_i_39_n_5\, O(1) => \cr_int_reg[31]_i_39_n_6\, O(0) => \cr_int_reg[31]_i_39_n_7\, S(3) => \cr_int[31]_i_87_n_0\, S(2) => \cr_int[31]_i_88_n_0\, S(1) => \cr_int[31]_i_89_n_0\, S(0) => \cr_int[31]_i_90_n_0\ ); \cr_int_reg[31]_i_48\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_91_n_0\, CO(3 downto 2) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(3 downto 2), CO(1) => \cr_int_reg[31]_i_48_n_2\, CO(0) => \NLW_cr_int_reg[31]_i_48_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(7), O(3 downto 1) => \NLW_cr_int_reg[31]_i_48_O_UNCONNECTED\(3 downto 1), O(0) => \cr_int_reg[31]_i_48_n_7\, S(3 downto 1) => B"001", S(0) => \cr_int[31]_i_93_n_0\ ); \cr_int_reg[31]_i_49\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_38_n_0\, CO(3) => \cr_int_reg[31]_i_49_n_0\, CO(2) => \cr_int_reg[31]_i_49_n_1\, CO(1) => \cr_int_reg[31]_i_49_n_2\, CO(0) => \cr_int_reg[31]_i_49_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[31]_i_49_n_4\, O(2) => \cr_int_reg[31]_i_49_n_5\, O(1) => \cr_int_reg[31]_i_49_n_6\, O(0) => \cr_int_reg[31]_i_49_n_7\, S(3) => \cr_int[31]_i_94_n_0\, S(2) => \cr_int[31]_i_95_n_0\, S(1) => \cr_int[31]_i_96_n_0\, S(0) => \cr_int[31]_i_97_n_0\ ); \cr_int_reg[31]_i_63\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_102_n_0\, CO(3 downto 2) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(3 downto 2), CO(1) => \cr_int_reg[31]_i_63_n_2\, CO(0) => \NLW_cr_int_reg[31]_i_63_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(15), O(3 downto 1) => \NLW_cr_int_reg[31]_i_63_O_UNCONNECTED\(3 downto 1), O(0) => \cr_int_reg[31]_i_63_n_7\, S(3 downto 1) => B"001", S(0) => \cr_int[31]_i_103_n_0\ ); \cr_int_reg[31]_i_69\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_70_n_0\, CO(3 downto 0) => \NLW_cr_int_reg[31]_i_69_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_cr_int_reg[31]_i_69_O_UNCONNECTED\(3 downto 1), O(0) => \^cr_int_reg[23]_1\(0), S(3 downto 1) => B"000", S(0) => \cr_int[31]_i_108_n_0\ ); \cr_int_reg[31]_i_7\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_14_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_7_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_7_n_1\, CO(1) => \cr_int_reg[31]_i_7_n_2\, CO(0) => \cr_int_reg[31]_i_7_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \cr_int[31]_i_15_n_0\, DI(0) => \cr_int[31]_i_16_n_0\, O(3) => \^cr_int_reg[27]_2\(0), O(2) => \cr_int_reg[31]_i_7_n_5\, O(1) => \cr_int_reg[31]_i_7_n_6\, O(0) => \cr_int_reg[31]_i_7_n_7\, S(3) => \cr_int[31]_i_17_n_0\, S(2) => \cr_int[31]_i_18_n_0\, S(1) => \cr_int[31]_i_19_n_0\, S(0) => \cr_int[31]_i_20_n_0\ ); \cr_int_reg[31]_i_70\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_28_n_0\, CO(3) => \cr_int_reg[31]_i_70_n_0\, CO(2) => \cr_int_reg[31]_i_70_n_1\, CO(1) => \cr_int_reg[31]_i_70_n_2\, CO(0) => \cr_int_reg[31]_i_70_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[23]_0\(3 downto 0), S(3) => \cr_int[31]_i_109_n_0\, S(2) => \cr_int[31]_i_110_n_0\, S(1) => \cr_int[31]_i_111_n_0\, S(0) => \cr_int[31]_i_112_n_0\ ); \cr_int_reg[31]_i_8\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_21_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_8_n_1\, CO(1) => \NLW_cr_int_reg[31]_i_8_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[31]_i_8_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[31]_i_8_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[31]_i_8_n_6\, O(0) => \cr_int_reg[31]_i_8_n_7\, S(3 downto 2) => B"01", S(1) => \cr_int[31]_i_22_n_0\, S(0) => \cr_int[31]_i_23_n_0\ ); \cr_int_reg[31]_i_86\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[31]_i_86_n_0\, CO(2) => \cr_int_reg[31]_i_86_n_1\, CO(1) => \cr_int_reg[31]_i_86_n_2\, CO(0) => \cr_int_reg[31]_i_86_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(4 downto 2), DI(0) => '0', O(3) => \cr_int_reg[31]_i_86_n_4\, O(2) => \cr_int_reg[31]_i_86_n_5\, O(1) => \cr_int_reg[31]_i_86_n_6\, O(0) => \cr_int_reg[31]_i_86_n_7\, S(3) => \cr_int[31]_i_113_n_0\, S(2) => \cr_int[31]_i_114_n_0\, S(1) => \cr_int[31]_i_115_n_0\, S(0) => \cr_int[31]_i_116_n_0\ ); \cr_int_reg[31]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_24_n_0\, CO(3 downto 1) => \NLW_cr_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1), CO(0) => \cr_int_reg[31]_i_9_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \^di\(0), O(3 downto 2) => \NLW_cr_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => \^cr_int_reg[31]_2\(1 downto 0), S(3 downto 2) => B"00", S(1) => \cr_int[31]_i_25_n_0\, S(0) => \cr_int[31]_i_26_n_0\ ); \cr_int_reg[31]_i_91\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_86_n_0\, CO(3) => \cr_int_reg[31]_i_91_n_0\, CO(2) => \cr_int_reg[31]_i_91_n_1\, CO(1) => \cr_int_reg[31]_i_91_n_2\, CO(0) => \cr_int_reg[31]_i_91_n_3\, CYINIT => '0', DI(3) => rgb888(6), DI(2 downto 0) => rgb888(7 downto 5), O(3) => \cr_int_reg[31]_i_91_n_4\, O(2) => \cr_int_reg[31]_i_91_n_5\, O(1) => \cr_int_reg[31]_i_91_n_6\, O(0) => \cr_int_reg[31]_i_91_n_7\, S(3) => \cr_int[31]_i_117_n_0\, S(2) => \cr_int[31]_i_118_n_0\, S(1) => \cr_int[31]_i_119_n_0\, S(0) => \cr_int[31]_i_120_n_0\ ); \cr_int_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[3]_i_1_n_4\, Q => \cr_int_reg_n_0_[3]\, R => '0' ); \cr_int_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_1_n_0\, CO(2) => \cr_int_reg[3]_i_1_n_1\, CO(1) => \cr_int_reg[3]_i_1_n_2\, CO(0) => \cr_int_reg[3]_i_1_n_3\, CYINIT => '1', DI(3) => \cr_int[3]_i_2_n_0\, DI(2) => \cr_int[3]_i_3_n_0\, DI(1) => \cr_int[3]_i_4_n_0\, DI(0) => '1', O(3) => \cr_int_reg[3]_i_1_n_4\, O(2) => \cr_int_reg[3]_i_1_n_5\, O(1) => \cr_int_reg[3]_i_1_n_6\, O(0) => \cr_int_reg[3]_i_1_n_7\, S(3) => \cr_int[3]_i_5_n_0\, S(2) => \cr_int[3]_i_6_n_0\, S(1) => \cr_int[3]_i_7_n_0\, S(0) => \cr_int[3]_i_8_n_0\ ); \cr_int_reg[3]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_21_n_0\, CO(3) => \cr_int_reg[3]_i_15_n_0\, CO(2) => \cr_int_reg[3]_i_15_n_1\, CO(1) => \cr_int_reg[3]_i_15_n_2\, CO(0) => \cr_int_reg[3]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => cr_int_reg6(8), O(2 downto 0) => \NLW_cr_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0), S(3) => \cr_int[3]_i_22_n_0\, S(2) => \cr_int[3]_i_23_n_0\, S(1) => \cr_int[3]_i_24_n_0\, S(0) => \cr_int[3]_i_25_n_0\ ); \cr_int_reg[3]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_16_n_0\, CO(2) => \cr_int_reg[3]_i_16_n_1\, CO(1) => \cr_int_reg[3]_i_16_n_2\, CO(0) => \cr_int_reg[3]_i_16_n_3\, CYINIT => '0', DI(3) => \cr_int_reg[3]_i_26_n_6\, DI(2) => \cr_int_reg[3]_i_26_n_7\, DI(1) => \cr_int_reg[3]_i_27_n_4\, DI(0) => '0', O(3) => \cr_int_reg[3]_i_16_n_4\, O(2) => \cr_int_reg[3]_i_16_n_5\, O(1) => \cr_int_reg[3]_i_16_n_6\, O(0) => \cr_int_reg[3]_i_16_n_7\, S(3) => \cr_int[3]_i_28_n_0\, S(2) => \cr_int[3]_i_29_n_0\, S(1) => \cr_int[3]_i_30_n_0\, S(0) => \cr_int[3]_i_31_n_0\ ); \cr_int_reg[3]_i_19\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_33_n_0\, CO(3) => \cr_int_reg[3]_i_19_n_0\, CO(2) => \cr_int_reg[3]_i_19_n_1\, CO(1) => \cr_int_reg[3]_i_19_n_2\, CO(0) => \cr_int_reg[3]_i_19_n_3\, CYINIT => '0', DI(3) => \cr_int[3]_i_34_n_0\, DI(2) => \cr_int[3]_i_35_n_0\, DI(1) => \cr_int[3]_i_36_n_0\, DI(0) => \cr_int[3]_i_37_n_0\, O(3 downto 1) => \^cr_int_reg[3]_0\(2 downto 0), O(0) => \cr_int_reg[3]_i_19_n_7\, S(3) => \cr_int[3]_i_38_n_0\, S(2) => \cr_int[3]_i_39_n_0\, S(1) => \cr_int[3]_i_40_n_0\, S(0) => \cr_int[3]_i_41_n_0\ ); \cr_int_reg[3]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_42_n_0\, CO(3) => \cr_int_reg[3]_i_20_n_0\, CO(2) => \cr_int_reg[3]_i_20_n_1\, CO(1) => \cr_int_reg[3]_i_20_n_2\, CO(0) => \cr_int_reg[3]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \^cr_int_reg[3]_2\(1 downto 0), O(1 downto 0) => \NLW_cr_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0), S(3) => \cr_int[3]_i_43_n_0\, S(2) => \cr_int[3]_i_44_n_0\, S(1) => \cr_int[3]_i_45_n_0\, S(0) => \cr_int[3]_i_46_n_0\ ); \cr_int_reg[3]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_21_n_0\, CO(2) => \cr_int_reg[3]_i_21_n_1\, CO(1) => \cr_int_reg[3]_i_21_n_2\, CO(0) => \cr_int_reg[3]_i_21_n_3\, CYINIT => \cr_int[3]_i_47_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cr_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[3]_i_48_n_0\, S(2) => \cr_int[3]_i_49_n_0\, S(1) => \cr_int[3]_i_50_n_0\, S(0) => \cr_int[3]_i_51_n_0\ ); \cr_int_reg[3]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_27_n_0\, CO(3) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[3]_i_26_n_1\, CO(1) => \NLW_cr_int_reg[3]_i_26_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[3]_i_26_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => rgb888(23), DI(0) => '0', O(3 downto 2) => \NLW_cr_int_reg[3]_i_26_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[3]_i_26_n_6\, O(0) => \cr_int_reg[3]_i_26_n_7\, S(3 downto 2) => B"01", S(1) => \cr_int[3]_i_52_n_0\, S(0) => \cr_int[3]_i_53_n_0\ ); \cr_int_reg[3]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_54_n_0\, CO(3) => \cr_int_reg[3]_i_27_n_0\, CO(2) => \cr_int_reg[3]_i_27_n_1\, CO(1) => \cr_int_reg[3]_i_27_n_2\, CO(0) => \cr_int_reg[3]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => rgb888(21 downto 18), O(3) => \cr_int_reg[3]_i_27_n_4\, O(2) => \cr_int_reg[3]_i_27_n_5\, O(1) => \cr_int_reg[3]_i_27_n_6\, O(0) => \cr_int_reg[3]_i_27_n_7\, S(3) => \cr_int[3]_i_55_n_0\, S(2) => \cr_int[3]_i_56_n_0\, S(1) => \cr_int[3]_i_57_n_0\, S(0) => \cr_int[3]_i_58_n_0\ ); \cr_int_reg[3]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_59_n_0\, CO(3) => \cr_int_reg[3]_i_32_n_0\, CO(2) => \cr_int_reg[3]_i_32_n_1\, CO(1) => \cr_int_reg[3]_i_32_n_2\, CO(0) => \cr_int_reg[3]_i_32_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[3]_i_32_n_4\, O(2 downto 0) => \NLW_cr_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0), S(3) => \cr_int[3]_i_60_n_0\, S(2) => \cr_int[3]_i_61_n_0\, S(1) => \cr_int[3]_i_62_n_0\, S(0) => \cr_int[3]_i_63_n_0\ ); \cr_int_reg[3]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_33_n_0\, CO(2) => \cr_int_reg[3]_i_33_n_1\, CO(1) => \cr_int_reg[3]_i_33_n_2\, CO(0) => \cr_int_reg[3]_i_33_n_3\, CYINIT => '0', DI(3) => \cr_int_reg[3]_i_64_n_6\, DI(2) => \cr_int_reg[3]_i_64_n_7\, DI(1) => \cr_int_reg[3]_i_65_n_4\, DI(0) => \cr_int_reg[3]_i_65_n_5\, O(3) => \cr_int_reg[3]_i_33_n_4\, O(2) => \cr_int_reg[3]_i_33_n_5\, O(1) => \cr_int_reg[3]_i_33_n_6\, O(0) => \NLW_cr_int_reg[3]_i_33_O_UNCONNECTED\(0), S(3) => \cr_int[3]_i_66_n_0\, S(2) => \cr_int[3]_i_67_n_0\, S(1) => \cr_int[3]_i_68_n_0\, S(0) => \cr_int[3]_i_69_n_0\ ); \cr_int_reg[3]_i_42\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_42_n_0\, CO(2) => \cr_int_reg[3]_i_42_n_1\, CO(1) => \cr_int_reg[3]_i_42_n_2\, CO(0) => \cr_int_reg[3]_i_42_n_3\, CYINIT => \cr_int[3]_i_71_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cr_int_reg[3]_i_42_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[3]_i_72_n_0\, S(2) => \cr_int[3]_i_73_n_0\, S(1) => \cr_int[3]_i_74_n_0\, S(0) => \cr_int[3]_i_75_n_0\ ); \cr_int_reg[3]_i_54\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_54_n_0\, CO(2) => \cr_int_reg[3]_i_54_n_1\, CO(1) => \cr_int_reg[3]_i_54_n_2\, CO(0) => \cr_int_reg[3]_i_54_n_3\, CYINIT => '0', DI(3 downto 2) => rgb888(17 downto 16), DI(1 downto 0) => B"01", O(3) => \cr_int_reg[3]_i_54_n_4\, O(2) => \cr_int_reg[3]_i_54_n_5\, O(1) => \cr_int_reg[3]_i_54_n_6\, O(0) => \cr_int_reg[3]_i_54_n_7\, S(3) => \cr_int[3]_i_76_n_0\, S(2) => \cr_int[3]_i_77_n_0\, S(1) => \cr_int[3]_i_78_n_0\, S(0) => \cr_int[3]_i_79_n_0\ ); \cr_int_reg[3]_i_59\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_59_n_0\, CO(2) => \cr_int_reg[3]_i_59_n_1\, CO(1) => \cr_int_reg[3]_i_59_n_2\, CO(0) => \cr_int_reg[3]_i_59_n_3\, CYINIT => \cr_int[3]_i_80_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cr_int_reg[3]_i_59_O_UNCONNECTED\(3 downto 0), S(3) => \cr_int[3]_i_81_n_0\, S(2) => \cr_int[3]_i_82_n_0\, S(1) => \cr_int[3]_i_83_n_0\, S(0) => \cr_int[3]_i_84_n_0\ ); \cr_int_reg[3]_i_64\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_65_n_0\, CO(3) => \cr_int_reg[3]_i_64_n_0\, CO(2) => \cr_int_reg[3]_i_64_n_1\, CO(1) => \cr_int_reg[3]_i_64_n_2\, CO(0) => \cr_int_reg[3]_i_64_n_3\, CYINIT => '0', DI(3) => rgb888(15), DI(2 downto 0) => rgb888(12 downto 10), O(3) => \cr_int_reg[3]_i_64_n_4\, O(2) => \cr_int_reg[3]_i_64_n_5\, O(1) => \cr_int_reg[3]_i_64_n_6\, O(0) => \cr_int_reg[3]_i_64_n_7\, S(3) => \cr_int[3]_i_85_n_0\, S(2) => \cr_int[3]_i_86_n_0\, S(1) => \cr_int[3]_i_87_n_0\, S(0) => \cr_int[3]_i_88_n_0\ ); \cr_int_reg[3]_i_65\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_65_n_0\, CO(2) => \cr_int_reg[3]_i_65_n_1\, CO(1) => \cr_int_reg[3]_i_65_n_2\, CO(0) => \cr_int_reg[3]_i_65_n_3\, CYINIT => '0', DI(3 downto 2) => rgb888(9 downto 8), DI(1 downto 0) => B"01", O(3) => \cr_int_reg[3]_i_65_n_4\, O(2) => \cr_int_reg[3]_i_65_n_5\, O(1) => \cr_int_reg[3]_i_65_n_6\, O(0) => \NLW_cr_int_reg[3]_i_65_O_UNCONNECTED\(0), S(3) => \cr_int[3]_i_89_n_0\, S(2) => \cr_int[3]_i_90_n_0\, S(1) => \cr_int[3]_i_91_n_0\, S(0) => \cr_int[3]_i_92_n_0\ ); \cr_int_reg[3]_i_70\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[3]_i_70_n_0\, CO(2) => \cr_int_reg[3]_i_70_n_1\, CO(1) => \cr_int_reg[3]_i_70_n_2\, CO(0) => \cr_int_reg[3]_i_70_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(12 downto 10), DI(0) => '0', O(3) => \cr_int_reg[3]_i_70_n_4\, O(2) => \cr_int_reg[3]_i_70_n_5\, O(1) => \cr_int_reg[3]_i_70_n_6\, O(0) => \cr_int_reg[3]_i_70_n_7\, S(3) => \cr_int[3]_i_93_n_0\, S(2) => \cr_int[3]_i_94_n_0\, S(1) => \cr_int[3]_i_95_n_0\, S(0) => \cr_int[3]_i_96_n_0\ ); \cr_int_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[7]_i_1_n_7\, Q => \cr_int_reg_n_0_[4]\, R => '0' ); \cr_int_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[7]_i_1_n_6\, Q => \cr_int_reg_n_0_[5]\, R => '0' ); \cr_int_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[7]_i_1_n_5\, Q => \cr_int_reg_n_0_[6]\, R => '0' ); \cr_int_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[7]_i_1_n_4\, Q => \cr_int_reg_n_0_[7]\, R => '0' ); \cr_int_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_1_n_0\, CO(3) => \cr_int_reg[7]_i_1_n_0\, CO(2) => \cr_int_reg[7]_i_1_n_1\, CO(1) => \cr_int_reg[7]_i_1_n_2\, CO(0) => \cr_int_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \cr_int[7]_i_2_n_0\, DI(2) => \cr_int[7]_i_3_n_0\, DI(1) => \cr_int[7]_i_4_n_0\, DI(0) => \cr_int[7]_i_5_n_0\, O(3) => \cr_int_reg[7]_i_1_n_4\, O(2) => \cr_int_reg[7]_i_1_n_5\, O(1) => \cr_int_reg[7]_i_1_n_6\, O(0) => \cr_int_reg[7]_i_1_n_7\, S(3) => \cr_int[7]_i_6_n_0\, S(2) => \cr_int[7]_i_7_n_0\, S(1) => \cr_int[7]_i_8_n_0\, S(0) => \cr_int[7]_i_9_n_0\ ); \cr_int_reg[7]_i_23\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[3]_i_20_n_0\, CO(3) => \cr_int_reg[7]_i_23_n_0\, CO(2) => \cr_int_reg[7]_i_23_n_1\, CO(1) => \cr_int_reg[7]_i_23_n_2\, CO(0) => \cr_int_reg[7]_i_23_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^cr_int_reg[7]_1\(3 downto 0), S(3) => \cr_int[7]_i_25_n_0\, S(2) => \cr_int[7]_i_26_n_0\, S(1) => \cr_int[7]_i_27_n_0\, S(0) => \cr_int[7]_i_28_n_0\ ); \cr_int_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[11]_i_1_n_7\, Q => \cr_int_reg__0\(8), R => '0' ); \cr_int_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \cr_int_reg[11]_i_1_n_6\, Q => \cr_int_reg__0\(9), R => '0' ); \cr_reg[0]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[0]_i_1_n_0\, Q => cr(0), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[1]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[1]_i_1_n_0\, Q => cr(1), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[2]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[2]_i_1_n_0\, Q => cr(2), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[3]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[3]_i_1_n_0\, Q => cr(3), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[4]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[4]_i_1_n_0\, Q => cr(4), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[5]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[5]_i_1_n_0\, Q => cr(5), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[6]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[6]_i_1_n_0\, Q => cr(6), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[7]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \cr[7]_i_2_n_0\, Q => cr(7), S => \cr_reg[7]_i_1_n_0\ ); \cr_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \cr_reg[7]_i_3_n_0\, CO(3) => \cr_reg[7]_i_1_n_0\, CO(2) => \cr_reg[7]_i_1_n_1\, CO(1) => \cr_reg[7]_i_1_n_2\, CO(0) => \cr_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \cr[7]_i_4_n_0\, DI(2) => \cr[7]_i_5_n_0\, DI(1) => \cr[7]_i_6_n_0\, DI(0) => \cr[7]_i_7_n_0\, O(3 downto 0) => \NLW_cr_reg[7]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \cr[7]_i_8_n_0\, S(2) => \cr[7]_i_9_n_0\, S(1) => \cr[7]_i_10_n_0\, S(0) => \cr[7]_i_11_n_0\ ); \cr_reg[7]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_reg[7]_i_12_n_0\, CO(2) => \cr_reg[7]_i_12_n_1\, CO(1) => \cr_reg[7]_i_12_n_2\, CO(0) => \cr_reg[7]_i_12_n_3\, CYINIT => '0', DI(3) => \cr[7]_i_21_n_0\, DI(2) => \cr[7]_i_22_n_0\, DI(1) => \cr[7]_i_23_n_0\, DI(0) => \cr[7]_i_24_n_0\, O(3 downto 0) => \NLW_cr_reg[7]_i_12_O_UNCONNECTED\(3 downto 0), S(3) => \cr[7]_i_25_n_0\, S(2) => \cr[7]_i_26_n_0\, S(1) => \cr[7]_i_27_n_0\, S(0) => \cr[7]_i_28_n_0\ ); \cr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \cr_reg[7]_i_12_n_0\, CO(3) => \cr_reg[7]_i_3_n_0\, CO(2) => \cr_reg[7]_i_3_n_1\, CO(1) => \cr_reg[7]_i_3_n_2\, CO(0) => \cr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3) => \cr[7]_i_13_n_0\, DI(2) => \cr[7]_i_14_n_0\, DI(1) => \cr[7]_i_15_n_0\, DI(0) => \cr[7]_i_16_n_0\, O(3 downto 0) => \NLW_cr_reg[7]_i_3_O_UNCONNECTED\(3 downto 0), S(3) => \cr[7]_i_17_n_0\, S(2) => \cr[7]_i_18_n_0\, S(1) => \cr[7]_i_19_n_0\, S(0) => \cr[7]_i_20_n_0\ ); edge_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => edge, O => edge_i_1_n_0 ); edge_rb_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => edge, I1 => edge_rb, O => edge_rb_i_1_n_0 ); edge_rb_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_x2, CE => '1', D => edge_rb_i_1_n_0, Q => edge_rb, R => \hdmi_d[15]_i_1_n_0\ ); edge_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_x2, CE => '1', D => edge_i_1_n_0, Q => edge, R => '0' ); \hdmi_clk_bits_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => edge_i_1_n_0, Q => D1, R => '0' ); \hdmi_d[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(2), I1 => \cr_hold_reg_n_0_[2]\, I2 => y_hold(2), I3 => edge_rb, I4 => y(2), I5 => edge, O => \hdmi_d[10]_i_1_n_0\ ); \hdmi_d[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(3), I1 => \cr_hold_reg_n_0_[3]\, I2 => y_hold(3), I3 => edge_rb, I4 => y(3), I5 => edge, O => \hdmi_d[11]_i_1_n_0\ ); \hdmi_d[12]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(4), I1 => \cr_hold_reg_n_0_[4]\, I2 => y_hold(4), I3 => edge_rb, I4 => y(4), I5 => edge, O => \hdmi_d[12]_i_1_n_0\ ); \hdmi_d[13]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(5), I1 => \cr_hold_reg_n_0_[5]\, I2 => y_hold(5), I3 => edge_rb, I4 => y(5), I5 => edge, O => \hdmi_d[13]_i_1_n_0\ ); \hdmi_d[14]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(6), I1 => \cr_hold_reg_n_0_[6]\, I2 => y_hold(6), I3 => edge_rb, I4 => y(6), I5 => edge, O => \hdmi_d[14]_i_1_n_0\ ); \hdmi_d[15]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => active, O => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(7), I1 => \cr_hold_reg_n_0_[7]\, I2 => y_hold(7), I3 => edge_rb, I4 => y(7), I5 => edge, O => \hdmi_d[15]_i_2_n_0\ ); \hdmi_d[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(0), I1 => \cr_hold_reg_n_0_[0]\, I2 => y_hold(0), I3 => edge_rb, I4 => y(0), I5 => edge, O => \hdmi_d[8]_i_1_n_0\ ); \hdmi_d[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AACCAACCF0FFF000" ) port map ( I0 => cb_hold(1), I1 => \cr_hold_reg_n_0_[1]\, I2 => y_hold(1), I3 => edge_rb, I4 => y(1), I5 => edge, O => \hdmi_d[9]_i_1_n_0\ ); \hdmi_d_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[10]_i_1_n_0\, Q => hdmi_d(2), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[11]_i_1_n_0\, Q => hdmi_d(3), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[12]_i_1_n_0\, Q => hdmi_d(4), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[13]_i_1_n_0\, Q => hdmi_d(5), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[14]_i_1_n_0\, Q => hdmi_d(6), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[15]_i_2_n_0\, Q => hdmi_d(7), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[8]_i_1_n_0\, Q => hdmi_d(0), R => \hdmi_d[15]_i_1_n_0\ ); \hdmi_d_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => \hdmi_d[9]_i_1_n_0\, Q => hdmi_d(1), R => \hdmi_d[15]_i_1_n_0\ ); hdmi_de_reg: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => active, Q => hdmi_de, R => '0' ); hdmi_hsync_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => hsync, O => p_0_in ); hdmi_hsync_reg: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => p_0_in, Q => hdmi_hsync, R => '0' ); hdmi_vsync_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => vsync, O => hdmi_vsync_i_1_n_0 ); hdmi_vsync_reg: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => '1', D => hdmi_vsync_i_1_n_0, Q => hdmi_vsync, R => '0' ); \y[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[0]\, I1 => \y_int_reg__0\(31), O => \y[0]_i_1_n_0\ ); \y[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[1]\, I1 => \y_int_reg__0\(31), O => \y[1]_i_1_n_0\ ); \y[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[2]\, I1 => \y_int_reg__0\(31), O => \y[2]_i_1_n_0\ ); \y[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[3]\, I1 => \y_int_reg__0\(31), O => \y[3]_i_1_n_0\ ); \y[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[4]\, I1 => \y_int_reg__0\(31), O => \y[4]_i_1_n_0\ ); \y[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[5]\, I1 => \y_int_reg__0\(31), O => \y[5]_i_1_n_0\ ); \y[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[6]\, I1 => \y_int_reg__0\(31), O => \y[6]_i_1_n_0\ ); \y[7]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(26), I1 => \y_int_reg__0\(27), O => \y[7]_i_10_n_0\ ); \y[7]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(24), I1 => \y_int_reg__0\(25), O => \y[7]_i_11_n_0\ ); \y[7]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(22), I1 => \y_int_reg__0\(23), O => \y[7]_i_13_n_0\ ); \y[7]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(20), I1 => \y_int_reg__0\(21), O => \y[7]_i_14_n_0\ ); \y[7]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(18), I1 => \y_int_reg__0\(19), O => \y[7]_i_15_n_0\ ); \y[7]_i_16\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(16), I1 => \y_int_reg__0\(17), O => \y[7]_i_16_n_0\ ); \y[7]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(22), I1 => \y_int_reg__0\(23), O => \y[7]_i_17_n_0\ ); \y[7]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(20), I1 => \y_int_reg__0\(21), O => \y[7]_i_18_n_0\ ); \y[7]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(18), I1 => \y_int_reg__0\(19), O => \y[7]_i_19_n_0\ ); \y[7]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg_n_0_[7]\, I1 => \y_int_reg__0\(31), O => \y[7]_i_2_n_0\ ); \y[7]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(16), I1 => \y_int_reg__0\(17), O => \y[7]_i_20_n_0\ ); \y[7]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(14), I1 => \y_int_reg__0\(15), O => \y[7]_i_21_n_0\ ); \y[7]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(12), I1 => \y_int_reg__0\(13), O => \y[7]_i_22_n_0\ ); \y[7]_i_23\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(10), I1 => \y_int_reg__0\(11), O => \y[7]_i_23_n_0\ ); \y[7]_i_24\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(8), I1 => \y_int_reg__0\(9), O => \y[7]_i_24_n_0\ ); \y[7]_i_25\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(14), I1 => \y_int_reg__0\(15), O => \y[7]_i_25_n_0\ ); \y[7]_i_26\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(12), I1 => \y_int_reg__0\(13), O => \y[7]_i_26_n_0\ ); \y[7]_i_27\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(10), I1 => \y_int_reg__0\(11), O => \y[7]_i_27_n_0\ ); \y[7]_i_28\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(8), I1 => \y_int_reg__0\(9), O => \y[7]_i_28_n_0\ ); \y[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg__0\(30), I1 => \y_int_reg__0\(31), O => \y[7]_i_4_n_0\ ); \y[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(28), I1 => \y_int_reg__0\(29), O => \y[7]_i_5_n_0\ ); \y[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(26), I1 => \y_int_reg__0\(27), O => \y[7]_i_6_n_0\ ); \y[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg__0\(24), I1 => \y_int_reg__0\(25), O => \y[7]_i_7_n_0\ ); \y[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(30), I1 => \y_int_reg__0\(31), O => \y[7]_i_8_n_0\ ); \y[7]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg__0\(28), I1 => \y_int_reg__0\(29), O => \y[7]_i_9_n_0\ ); \y_hold[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(0), I1 => y(0), I2 => edge_rb, O => p_1_in(0) ); \y_hold[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(1), I1 => y(1), I2 => edge_rb, O => p_1_in(1) ); \y_hold[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(2), I1 => y(2), I2 => edge_rb, O => p_1_in(2) ); \y_hold[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(3), I1 => y(3), I2 => edge_rb, O => p_1_in(3) ); \y_hold[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(4), I1 => y(4), I2 => edge_rb, O => p_1_in(4) ); \y_hold[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(5), I1 => y(5), I2 => edge_rb, O => p_1_in(5) ); \y_hold[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(6), I1 => y(6), I2 => edge_rb, O => p_1_in(6) ); \y_hold[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => y_hold(7), I1 => y(7), I2 => edge_rb, O => p_1_in(7) ); \y_hold_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(0), Q => y_hold(0), R => '0' ); \y_hold_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(1), Q => y_hold(1), R => '0' ); \y_hold_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(2), Q => y_hold(2), R => '0' ); \y_hold_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(3), Q => y_hold(3), R => '0' ); \y_hold_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(4), Q => y_hold(4), R => '0' ); \y_hold_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(5), Q => y_hold(5), R => '0' ); \y_hold_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(6), Q => y_hold(6), R => '0' ); \y_hold_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => edge_i_1_n_0, D => p_1_in(7), Q => y_hold(7), R => '0' ); \y_int[11]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \y_int_reg[15]_i_33_n_6\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_29\(0), I3 => \^y_int_reg[3]_1\(0), O => \y_int[11]_i_10_n_0\ ); \y_int[11]_i_100\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), I1 => rgb888(0), O => \y_int[11]_i_100_n_0\ ); \y_int[11]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(1), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[15]_0\(1), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(10) ); \y_int[11]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \y_int_reg[15]_i_33_n_7\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_22\(3), I3 => \^y_int_reg[3]_1\(0), O => \y_int[11]_i_12_n_0\ ); \y_int[11]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(0), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[15]_0\(0), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(9) ); \y_int[11]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[11]_i_38_n_4\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_21\(1), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[8]_22\(2), O => \y_int[11]_i_16_n_0\ ); \y_int[11]_i_17\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg2(8), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[11]_i_21_n_4\, I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(8) ); \y_int[11]_i_18\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(7), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_8_n_6\, I3 => y_int_reg6, I4 => y_int_reg5(15), O => y_int_reg20_in(7) ); \y_int[11]_i_19\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[11]_i_38_n_5\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_21\(0), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[8]_22\(1), O => \y_int[11]_i_19_n_0\ ); \y_int[11]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(18), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(10), I4 => \y_int[11]_i_10_n_0\, I5 => y_int_reg1(10), O => \y_int[11]_i_2_n_0\ ); \y_int[11]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(11), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(19), I3 => y_int_reg6, O => y_int_reg20_in(11) ); \y_int[11]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(10), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(18), I3 => y_int_reg6, O => y_int_reg20_in(10) ); \y_int[11]_i_25\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(9), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(17), I3 => y_int_reg6, O => y_int_reg20_in(9) ); \y_int[11]_i_26\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(8), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(16), I3 => y_int_reg6, O => y_int_reg20_in(8) ); \y_int[11]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[11]_i_29_n_0\ ); \y_int[11]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(17), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(9), I4 => \y_int[11]_i_12_n_0\, I5 => y_int_reg1(9), O => \y_int[11]_i_3_n_0\ ); \y_int[11]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_6\, O => \y_int[11]_i_30_n_0\ ); \y_int[11]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_7\, O => \y_int[11]_i_31_n_0\ ); \y_int[11]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_4\, O => \y_int[11]_i_32_n_0\ ); \y_int[11]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(16), O => \y_int[11]_i_34_n_0\ ); \y_int[11]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(15), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_8_n_6\, O => \y_int[11]_i_35_n_0\ ); \y_int[11]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(14), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_8_n_7\, O => \y_int[11]_i_36_n_0\ ); \y_int[11]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(13), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_16_n_4\, O => \y_int[11]_i_37_n_0\ ); \y_int[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(16), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(8), I4 => \y_int[11]_i_16_n_0\, I5 => y_int_reg1(8), O => \y_int[11]_i_4_n_0\ ); \y_int[11]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^y_int_reg[23]_0\(0), I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[11]_i_21_n_4\, O => \y_int[11]_i_40_n_0\ ); \y_int[11]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^y_int_reg[23]_0\(0), I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[11]_i_21_n_5\, O => \y_int[11]_i_41_n_0\ ); \y_int[11]_i_42\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \^y_int_reg[23]_0\(0), I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[11]_i_21_n_6\, O => \y_int[11]_i_42_n_0\ ); \y_int[11]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_21_n_7\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_11_n_5\, O => \y_int[11]_i_43_n_0\ ); \y_int[11]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_45_n_0\ ); \y_int[11]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_46_n_0\ ); \y_int[11]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_47_n_0\ ); \y_int[11]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_5\, O => \y_int[11]_i_48_n_0\ ); \y_int[11]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"E888E888E8EEE888" ) port map ( I0 => y_int_reg20_in(7), I1 => \y_int[11]_i_19_n_0\, I2 => y_int_reg2(7), I3 => \^y_int_reg[23]_0\(0), I4 => \y_int_reg[11]_i_21_n_5\, I5 => \^y_int_reg[7]_0\(0), O => \y_int[11]_i_5_n_0\ ); \y_int[11]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_50_n_0\ ); \y_int[11]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_51_n_0\ ); \y_int[11]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_52_n_0\ ); \y_int[11]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_53_n_0\ ); \y_int[11]_i_58\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_5\, O => \y_int[11]_i_58_n_0\ ); \y_int[11]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_6\, O => \y_int[11]_i_59_n_0\ ); \y_int[11]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[11]_i_2_n_0\, I1 => y_int_reg1(11), I2 => \y_int[15]_i_18_n_0\, I3 => y_int_reg20_in(11), O => \y_int[11]_i_6_n_0\ ); \y_int[11]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_7\, O => \y_int[11]_i_60_n_0\ ); \y_int[11]_i_61\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_4\, O => \y_int[11]_i_61_n_0\ ); \y_int[11]_i_62\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(8), I1 => y_int_reg6, I2 => \y_int_reg[3]_i_16_n_5\, O => \y_int[11]_i_62_n_0\ ); \y_int[11]_i_63\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(12), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_16_n_5\, O => \y_int[11]_i_63_n_0\ ); \y_int[11]_i_64\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(11), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_16_n_6\, O => \y_int[11]_i_64_n_0\ ); \y_int[11]_i_65\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(10), I1 => y_int_reg6, I2 => \y_int_reg[31]_i_16_n_7\, O => \y_int[11]_i_65_n_0\ ); \y_int[11]_i_66\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => y_int_reg5(9), I1 => y_int_reg6, I2 => \y_int_reg[3]_i_16_n_4\, O => \y_int[11]_i_66_n_0\ ); \y_int[11]_i_67\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[8]_22\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_21\(1), O => \y_int[11]_i_67_n_0\ ); \y_int[11]_i_68\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[8]_22\(1), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_21\(0), O => \y_int[11]_i_68_n_0\ ); \y_int[11]_i_69\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[8]_22\(0), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_20\(3), O => \y_int[11]_i_69_n_0\ ); \y_int[11]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[11]_i_3_n_0\, I1 => y_int_reg1(10), I2 => \y_int[11]_i_10_n_0\, I3 => y_int_reg20_in(10), O => \y_int[11]_i_7_n_0\ ); \y_int[11]_i_70\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_1\(3), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_20\(2), O => \y_int[11]_i_70_n_0\ ); \y_int[11]_i_71\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[3]_i_35_n_4\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_30_n_6\, O => \y_int[11]_i_71_n_0\ ); \y_int[11]_i_72\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_44_n_4\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_11_n_6\, O => \y_int[11]_i_72_n_0\ ); \y_int[11]_i_73\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_44_n_5\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_11_n_7\, O => \y_int[11]_i_73_n_0\ ); \y_int[11]_i_74\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_44_n_6\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_30_n_4\, O => \y_int[11]_i_74_n_0\ ); \y_int[11]_i_75\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \y_int_reg[11]_i_44_n_7\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[31]_i_30_n_5\, O => \y_int[11]_i_75_n_0\ ); \y_int[11]_i_76\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_6\, O => \y_int[11]_i_76_n_0\ ); \y_int[11]_i_77\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_7\, O => \y_int[11]_i_77_n_0\ ); \y_int[11]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_4\, O => \y_int[11]_i_78_n_0\ ); \y_int[11]_i_79\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_5\, O => \y_int[11]_i_79_n_0\ ); \y_int[11]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[11]_i_4_n_0\, I1 => y_int_reg1(9), I2 => \y_int[11]_i_12_n_0\, I3 => y_int_reg20_in(9), O => \y_int[11]_i_8_n_0\ ); \y_int[11]_i_81\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_81_n_0\ ); \y_int[11]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_82_n_0\ ); \y_int[11]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_83_n_0\ ); \y_int[11]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_84_n_0\ ); \y_int[11]_i_86\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_11_n_6\, I1 => \y_int_reg[31]_i_11_n_5\, O => \y_int[11]_i_86_n_0\ ); \y_int[11]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_30_n_4\, I1 => \y_int_reg[31]_i_11_n_7\, O => \y_int[11]_i_87_n_0\ ); \y_int[11]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_30_n_6\, I1 => \y_int_reg[31]_i_30_n_5\, O => \y_int[11]_i_88_n_0\ ); \y_int[11]_i_89\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[11]_i_89_n_0\ ); \y_int[11]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[11]_i_5_n_0\, I1 => y_int_reg1(8), I2 => \y_int[11]_i_16_n_0\, I3 => y_int_reg20_in(8), O => \y_int[11]_i_9_n_0\ ); \y_int[11]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_5\, I1 => \y_int_reg[31]_i_11_n_6\, O => \y_int[11]_i_90_n_0\ ); \y_int[11]_i_91\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_11_n_7\, I1 => \y_int_reg[31]_i_30_n_4\, O => \y_int[11]_i_91_n_0\ ); \y_int[11]_i_92\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_5\, I1 => \y_int_reg[31]_i_30_n_6\, O => \y_int[11]_i_92_n_0\ ); \y_int[11]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_62_n_4\, I1 => \y_int_reg[31]_i_30_n_7\, O => \y_int[11]_i_93_n_0\ ); \y_int[11]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_62_n_6\, I1 => \y_int_reg[31]_i_62_n_5\, O => \y_int[11]_i_94_n_0\ ); \y_int[11]_i_95\: unisim.vcomponents.LUT3 generic map( INIT => X"BE" ) port map ( I0 => \y_int_reg[31]_i_88_n_6\, I1 => \y_int_reg[31]_i_88_n_5\, I2 => rgb888(0), O => \y_int[11]_i_95_n_0\ ); \y_int[11]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rgb888(0), I1 => rgb888(1), O => \y_int[11]_i_96_n_0\ ); \y_int[11]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_7\, I1 => \y_int_reg[31]_i_62_n_4\, O => \y_int[11]_i_97_n_0\ ); \y_int[11]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_62_n_5\, I1 => \y_int_reg[31]_i_62_n_6\, O => \y_int[11]_i_98_n_0\ ); \y_int[11]_i_99\: unisim.vcomponents.LUT3 generic map( INIT => X"09" ) port map ( I0 => rgb888(0), I1 => \y_int_reg[31]_i_88_n_5\, I2 => \y_int_reg[31]_i_88_n_6\, O => \y_int[11]_i_99_n_0\ ); \y_int[15]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_28\(1), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_27\(0), I3 => \^y_int_reg[3]_1\(0), O => \y_int[15]_i_10_n_0\ ); \y_int[15]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(5), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[19]_0\(1), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(14) ); \y_int[15]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_28\(0), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_29\(3), I3 => \^y_int_reg[3]_1\(0), O => \y_int[15]_i_12_n_0\ ); \y_int[15]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(4), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[19]_0\(0), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(13) ); \y_int[15]_i_16\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \y_int_reg[15]_i_33_n_4\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_29\(2), I3 => \^y_int_reg[3]_1\(0), O => \y_int[15]_i_16_n_0\ ); \y_int[15]_i_17\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(3), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[15]_0\(3), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(12) ); \y_int[15]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \y_int_reg[15]_i_33_n_5\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_29\(1), I3 => \^y_int_reg[3]_1\(0), O => \y_int[15]_i_18_n_0\ ); \y_int[15]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(2), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[15]_0\(2), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(11) ); \y_int[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(22), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(14), I4 => \y_int[15]_i_10_n_0\, I5 => y_int_reg1(14), O => \y_int[15]_i_2_n_0\ ); \y_int[15]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(15), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(23), I3 => y_int_reg6, O => y_int_reg20_in(15) ); \y_int[15]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(14), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(22), I3 => y_int_reg6, O => y_int_reg20_in(14) ); \y_int[15]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(13), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(21), I3 => y_int_reg6, O => y_int_reg20_in(13) ); \y_int[15]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(12), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(20), I3 => y_int_reg6, O => y_int_reg20_in(12) ); \y_int[15]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[15]_i_25_n_0\ ); \y_int[15]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[15]_i_26_n_0\ ); \y_int[15]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[15]_i_27_n_0\ ); \y_int[15]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[15]_i_28_n_0\ ); \y_int[15]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(20), O => \y_int[15]_i_29_n_0\ ); \y_int[15]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(21), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(13), I4 => \y_int[15]_i_12_n_0\, I5 => y_int_reg1(13), O => \y_int[15]_i_3_n_0\ ); \y_int[15]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(19), O => \y_int[15]_i_30_n_0\ ); \y_int[15]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(18), O => \y_int[15]_i_31_n_0\ ); \y_int[15]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(17), O => \y_int[15]_i_32_n_0\ ); \y_int[15]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(20), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(12), I4 => \y_int[15]_i_16_n_0\, I5 => y_int_reg1(12), O => \y_int[15]_i_4_n_0\ ); \y_int[15]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_29\(2), O => \y_int[15]_i_40_n_0\ ); \y_int[15]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_29\(1), O => \y_int[15]_i_41_n_0\ ); \y_int[15]_i_42\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_29\(0), O => \y_int[15]_i_42_n_0\ ); \y_int[15]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_22\(3), O => \y_int[15]_i_43_n_0\ ); \y_int[15]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[15]_i_48_n_0\ ); \y_int[15]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[15]_i_49_n_0\ ); \y_int[15]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(19), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(11), I4 => \y_int[15]_i_18_n_0\, I5 => y_int_reg1(11), O => \y_int[15]_i_5_n_0\ ); \y_int[15]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[15]_i_50_n_0\ ); \y_int[15]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[15]_i_51_n_0\ ); \y_int[15]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[15]_i_2_n_0\, I1 => y_int_reg1(15), I2 => \y_int[19]_i_18_n_0\, I3 => y_int_reg20_in(15), O => \y_int[15]_i_6_n_0\ ); \y_int[15]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[15]_i_3_n_0\, I1 => y_int_reg1(14), I2 => \y_int[15]_i_10_n_0\, I3 => y_int_reg20_in(14), O => \y_int[15]_i_7_n_0\ ); \y_int[15]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[15]_i_4_n_0\, I1 => y_int_reg1(13), I2 => \y_int[15]_i_12_n_0\, I3 => y_int_reg20_in(13), O => \y_int[15]_i_8_n_0\ ); \y_int[15]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[15]_i_5_n_0\, I1 => y_int_reg1(12), I2 => \y_int[15]_i_16_n_0\, I3 => y_int_reg20_in(12), O => \y_int[15]_i_9_n_0\ ); \y_int[19]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_26\(1), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_25\(0), I3 => \^y_int_reg[3]_1\(0), O => \y_int[19]_i_10_n_0\ ); \y_int[19]_i_11\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(9), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_2\(1), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(18) ); \y_int[19]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_26\(0), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_27\(3), I3 => \^y_int_reg[3]_1\(0), O => \y_int[19]_i_12_n_0\ ); \y_int[19]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(8), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_2\(0), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(17) ); \y_int[19]_i_16\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_28\(3), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_27\(2), I3 => \^y_int_reg[3]_1\(0), O => \y_int[19]_i_16_n_0\ ); \y_int[19]_i_17\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(7), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[19]_0\(3), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(16) ); \y_int[19]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_28\(2), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_27\(1), I3 => \^y_int_reg[3]_1\(0), O => \y_int[19]_i_18_n_0\ ); \y_int[19]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(6), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[19]_0\(2), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(15) ); \y_int[19]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(26), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(18), I4 => \y_int[19]_i_10_n_0\, I5 => y_int_reg1(18), O => \y_int[19]_i_2_n_0\ ); \y_int[19]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(19), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(27), I3 => y_int_reg6, O => y_int_reg20_in(19) ); \y_int[19]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(18), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(26), I3 => y_int_reg6, O => y_int_reg20_in(18) ); \y_int[19]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(17), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(25), I3 => y_int_reg6, O => y_int_reg20_in(17) ); \y_int[19]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(16), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(24), I3 => y_int_reg6, O => y_int_reg20_in(16) ); \y_int[19]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[19]_i_25_n_0\ ); \y_int[19]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[19]_i_26_n_0\ ); \y_int[19]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[19]_i_27_n_0\ ); \y_int[19]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[19]_i_28_n_0\ ); \y_int[19]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(24), O => \y_int[19]_i_29_n_0\ ); \y_int[19]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(25), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(17), I4 => \y_int[19]_i_12_n_0\, I5 => y_int_reg1(17), O => \y_int[19]_i_3_n_0\ ); \y_int[19]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(23), O => \y_int[19]_i_30_n_0\ ); \y_int[19]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(22), O => \y_int[19]_i_31_n_0\ ); \y_int[19]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(21), O => \y_int[19]_i_32_n_0\ ); \y_int[19]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(24), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(16), I4 => \y_int[19]_i_16_n_0\, I5 => y_int_reg1(16), O => \y_int[19]_i_4_n_0\ ); \y_int[19]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[19]_i_48_n_0\ ); \y_int[19]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[19]_i_49_n_0\ ); \y_int[19]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(23), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(15), I4 => \y_int[19]_i_18_n_0\, I5 => y_int_reg1(15), O => \y_int[19]_i_5_n_0\ ); \y_int[19]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[19]_i_50_n_0\ ); \y_int[19]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[19]_i_51_n_0\ ); \y_int[19]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[19]_i_2_n_0\, I1 => y_int_reg1(19), I2 => \y_int[23]_i_20_n_0\, I3 => y_int_reg20_in(19), O => \y_int[19]_i_6_n_0\ ); \y_int[19]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[19]_i_3_n_0\, I1 => y_int_reg1(18), I2 => \y_int[19]_i_10_n_0\, I3 => y_int_reg20_in(18), O => \y_int[19]_i_7_n_0\ ); \y_int[19]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[19]_i_4_n_0\, I1 => y_int_reg1(17), I2 => \y_int[19]_i_12_n_0\, I3 => y_int_reg20_in(17), O => \y_int[19]_i_8_n_0\ ); \y_int[19]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[19]_i_5_n_0\, I1 => y_int_reg1(16), I2 => \y_int[19]_i_16_n_0\, I3 => y_int_reg20_in(16), O => \y_int[19]_i_9_n_0\ ); \y_int[23]_i_100\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_19\(0), I1 => \^y_int_reg[3]_0\(0), O => \y_int[23]_i_100_n_0\ ); \y_int[23]_i_101\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[14]\(0), I1 => \^y_int_reg[3]_0\(3), O => \y_int[23]_i_101_n_0\ ); \y_int[23]_i_102\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[3]_0\(2), I1 => \^y_int_reg[3]_0\(1), O => \y_int[23]_i_102_n_0\ ); \y_int[23]_i_103\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[3]_0\(0), I1 => \rgb888[8]_19\(0), O => \y_int[23]_i_103_n_0\ ); \y_int[23]_i_104\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(8), O => \y_int[23]_i_104_n_0\ ); \y_int[23]_i_12\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_23\(1), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_24\(0), I3 => \^y_int_reg[3]_1\(0), O => \y_int[23]_i_12_n_0\ ); \y_int[23]_i_13\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(13), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_1\(1), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(22) ); \y_int[23]_i_14\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_23\(0), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_25\(3), I3 => \^y_int_reg[3]_1\(0), O => \y_int[23]_i_14_n_0\ ); \y_int[23]_i_15\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(12), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_1\(0), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(21) ); \y_int[23]_i_18\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_26\(3), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_25\(2), I3 => \^y_int_reg[3]_1\(0), O => \y_int[23]_i_18_n_0\ ); \y_int[23]_i_19\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(11), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_2\(3), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(20) ); \y_int[23]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(30), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(22), I4 => \y_int[23]_i_12_n_0\, I5 => y_int_reg1(22), O => \y_int[23]_i_2_n_0\ ); \y_int[23]_i_20\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[8]_26\(2), I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_25\(1), I3 => \^y_int_reg[3]_1\(0), O => \y_int[23]_i_20_n_0\ ); \y_int[23]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => \rgb888[1]\(10), I1 => \^y_int_reg[23]_0\(0), I2 => \^y_int_reg[23]_2\(2), I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(19) ); \y_int[23]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(22), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(30), I3 => y_int_reg6, O => y_int_reg20_in(22) ); \y_int[23]_i_23\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(21), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(29), I3 => y_int_reg6, O => y_int_reg20_in(21) ); \y_int[23]_i_24\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg3(20), I1 => \y_int_reg[31]_i_8_n_5\, I2 => y_int_reg5(28), I3 => y_int_reg6, O => y_int_reg20_in(20) ); \y_int[23]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_26_n_0\ ); \y_int[23]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_27_n_0\ ); \y_int[23]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_28_n_0\ ); \y_int[23]_i_29\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_29_n_0\ ); \y_int[23]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(29), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(21), I4 => \y_int[23]_i_14_n_0\, I5 => y_int_reg1(21), O => \y_int[23]_i_3_n_0\ ); \y_int[23]_i_30\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_30_n_0\ ); \y_int[23]_i_31\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_31_n_0\ ); \y_int[23]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_36_n_0\ ); \y_int[23]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_37_n_0\ ); \y_int[23]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_38_n_0\ ); \y_int[23]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_39_n_0\ ); \y_int[23]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(28), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(20), I4 => \y_int[23]_i_18_n_0\, I5 => y_int_reg1(20), O => \y_int[23]_i_4_n_0\ ); \y_int[23]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(28), O => \y_int[23]_i_40_n_0\ ); \y_int[23]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(27), O => \y_int[23]_i_41_n_0\ ); \y_int[23]_i_42\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(26), O => \y_int[23]_i_42_n_0\ ); \y_int[23]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(25), O => \y_int[23]_i_43_n_0\ ); \y_int[23]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_46_n_0\ ); \y_int[23]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_47_n_0\ ); \y_int[23]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_48_n_0\ ); \y_int[23]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, O => \y_int[23]_i_49_n_0\ ); \y_int[23]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF404F4040000" ) port map ( I0 => y_int_reg6, I1 => y_int_reg5(27), I2 => \y_int_reg[31]_i_8_n_5\, I3 => y_int_reg3(19), I4 => \y_int[23]_i_20_n_0\, I5 => y_int_reg1(19), O => \y_int[23]_i_5_n_0\ ); \y_int[23]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_52_n_0\ ); \y_int[23]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_53_n_0\ ); \y_int[23]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_54_n_0\ ); \y_int[23]_i_55\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_55_n_0\ ); \y_int[23]_i_56\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_56_n_0\ ); \y_int[23]_i_57\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_57_n_0\ ); \y_int[23]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[23]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[23]_i_6_n_0\ ); \y_int[23]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_62_n_0\ ); \y_int[23]_i_63\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_63_n_0\ ); \y_int[23]_i_64\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_64_n_0\ ); \y_int[23]_i_65\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^y_int_reg[23]_0\(0), O => \y_int[23]_i_65_n_0\ ); \y_int[23]_i_67\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_8_n_7\, I1 => \y_int_reg[31]_i_8_n_6\, O => \y_int[23]_i_67_n_0\ ); \y_int[23]_i_68\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_16_n_5\, I1 => \y_int_reg[31]_i_16_n_4\, O => \y_int[23]_i_68_n_0\ ); \y_int[23]_i_69\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_16_n_7\, I1 => \y_int_reg[31]_i_16_n_6\, O => \y_int[23]_i_69_n_0\ ); \y_int[23]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[23]_i_3_n_0\, I1 => y_int_reg1(22), I2 => \y_int[23]_i_12_n_0\, I3 => y_int_reg20_in(22), O => \y_int[23]_i_7_n_0\ ); \y_int[23]_i_70\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[3]_i_16_n_5\, I1 => \y_int_reg[3]_i_16_n_4\, O => \y_int[23]_i_70_n_0\ ); \y_int[23]_i_71\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_8_n_6\, I1 => \y_int_reg[31]_i_8_n_7\, O => \y_int[23]_i_71_n_0\ ); \y_int[23]_i_72\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_4\, I1 => \y_int_reg[31]_i_16_n_5\, O => \y_int[23]_i_72_n_0\ ); \y_int[23]_i_73\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_16_n_6\, I1 => \y_int_reg[31]_i_16_n_7\, O => \y_int[23]_i_73_n_0\ ); \y_int[23]_i_74\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_4\, I1 => \y_int_reg[3]_i_16_n_5\, O => \y_int[23]_i_74_n_0\ ); \y_int[23]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_21\(1), I1 => \rgb888[8]_21\(2), O => \y_int[23]_i_76_n_0\ ); \y_int[23]_i_77\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_77_n_0\ ); \y_int[23]_i_78\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_78_n_0\ ); \y_int[23]_i_79\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), O => \y_int[23]_i_79_n_0\ ); \y_int[23]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[23]_i_4_n_0\, I1 => y_int_reg1(21), I2 => \y_int[23]_i_14_n_0\, I3 => y_int_reg20_in(21), O => \y_int[23]_i_8_n_0\ ); \y_int[23]_i_80\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \rgb888[8]_21\(1), O => \y_int[23]_i_80_n_0\ ); \y_int[23]_i_81\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[3]_i_16_n_7\, I1 => \y_int_reg[3]_i_16_n_6\, O => \y_int[23]_i_81_n_0\ ); \y_int[23]_i_82\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[3]_i_26_n_5\, I1 => \y_int_reg[3]_i_26_n_4\, O => \y_int[23]_i_82_n_0\ ); \y_int[23]_i_83\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[3]_i_26_n_7\, I1 => \y_int_reg[3]_i_26_n_6\, O => \y_int[23]_i_83_n_0\ ); \y_int[23]_i_84\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rgb888(16), I1 => rgb888(17), O => \y_int[23]_i_84_n_0\ ); \y_int[23]_i_85\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_6\, I1 => \y_int_reg[3]_i_16_n_7\, O => \y_int[23]_i_85_n_0\ ); \y_int[23]_i_86\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_4\, I1 => \y_int_reg[3]_i_26_n_5\, O => \y_int[23]_i_86_n_0\ ); \y_int[23]_i_87\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_6\, I1 => \y_int_reg[3]_i_26_n_7\, O => \y_int[23]_i_87_n_0\ ); \y_int[23]_i_88\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => rgb888(17), I1 => rgb888(16), O => \y_int[23]_i_88_n_0\ ); \y_int[23]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[23]_i_5_n_0\, I1 => y_int_reg1(20), I2 => \y_int[23]_i_18_n_0\, I3 => y_int_reg20_in(20), O => \y_int[23]_i_9_n_0\ ); \y_int[23]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_20\(3), I1 => \rgb888[8]_21\(0), O => \y_int[23]_i_90_n_0\ ); \y_int[23]_i_91\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[8]_20\(1), I1 => \rgb888[8]_20\(2), O => \y_int[23]_i_91_n_0\ ); \y_int[23]_i_92\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[14]\(3), I1 => \rgb888[8]_20\(0), O => \y_int[23]_i_92_n_0\ ); \y_int[23]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rgb888[14]\(1), I1 => \rgb888[14]\(2), O => \y_int[23]_i_93_n_0\ ); \y_int[23]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_21\(0), I1 => \rgb888[8]_20\(3), O => \y_int[23]_i_94_n_0\ ); \y_int[23]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_20\(2), I1 => \rgb888[8]_20\(1), O => \y_int[23]_i_95_n_0\ ); \y_int[23]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[8]_20\(0), I1 => \rgb888[14]\(3), O => \y_int[23]_i_96_n_0\ ); \y_int[23]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \rgb888[14]\(2), I1 => \rgb888[14]\(1), O => \y_int[23]_i_97_n_0\ ); \y_int[23]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^y_int_reg[3]_0\(3), I1 => \rgb888[14]\(0), O => \y_int[23]_i_98_n_0\ ); \y_int[23]_i_99\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^y_int_reg[3]_0\(1), I1 => \^y_int_reg[3]_0\(2), O => \y_int[23]_i_99_n_0\ ); \y_int[27]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[27]_i_2_n_0\ ); \y_int[27]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[27]_i_3_n_0\ ); \y_int[27]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[27]_i_4_n_0\ ); \y_int[27]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[27]_i_5_n_0\ ); \y_int[31]_i_101\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(7), O => \y_int[31]_i_101_n_0\ ); \y_int[31]_i_104\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(1), I1 => rgb888(3), O => \y_int[31]_i_104_n_0\ ); \y_int[31]_i_105\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => rgb888(3), I1 => rgb888(1), I2 => rgb888(2), O => \y_int[31]_i_105_n_0\ ); \y_int[31]_i_106\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(2), I1 => rgb888(0), O => \y_int[31]_i_106_n_0\ ); \y_int[31]_i_107\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), O => \y_int[31]_i_107_n_0\ ); \y_int[31]_i_108\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(0), O => \y_int[31]_i_108_n_0\ ); \y_int[31]_i_109\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(6), O => \y_int[31]_i_109_n_0\ ); \y_int[31]_i_110\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(7), I1 => rgb888(5), O => \y_int[31]_i_110_n_0\ ); \y_int[31]_i_111\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(6), I1 => rgb888(4), O => \y_int[31]_i_111_n_0\ ); \y_int[31]_i_112\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(5), I1 => rgb888(3), O => \y_int[31]_i_112_n_0\ ); \y_int[31]_i_113\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(4), I1 => rgb888(2), O => \y_int[31]_i_113_n_0\ ); \y_int[31]_i_114\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(3), I1 => rgb888(1), O => \y_int[31]_i_114_n_0\ ); \y_int[31]_i_115\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(2), I1 => rgb888(0), O => \y_int[31]_i_115_n_0\ ); \y_int[31]_i_116\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(1), O => \y_int[31]_i_116_n_0\ ); \y_int[31]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \rgb888[8]_21\(2), I1 => \rgb888[8]_30\(0), O => \y_int[31]_i_13_n_0\ ); \y_int[31]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(30), O => \y_int[31]_i_14_n_0\ ); \y_int[31]_i_15\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_8_n_5\, I1 => y_int_reg6, I2 => y_int_reg5(29), O => \y_int[31]_i_15_n_0\ ); \y_int[31]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => rgb888(20), I1 => rgb888(18), I2 => rgb888(19), I3 => rgb888(21), I4 => rgb888(22), I5 => rgb888(23), O => \y_int[31]_i_17_n_0\ ); \y_int[31]_i_18\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(23), I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(19), I4 => rgb888(21), I5 => rgb888(22), O => \y_int[31]_i_18_n_0\ ); \y_int[31]_i_19\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(23), I1 => rgb888(20), I2 => rgb888(18), I3 => rgb888(19), I4 => rgb888(21), I5 => rgb888(22), O => \y_int[31]_i_19_n_0\ ); \y_int[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0040004044F40040" ) port map ( I0 => \y_int_reg[31]_i_7_n_1\, I1 => \y_int_reg[31]_i_8_n_5\, I2 => \rgb888[8]_21\(2), I3 => \rgb888[8]_30\(0), I4 => \^y_int_reg[23]_0\(0), I5 => \rgb888[1]_0\(0), O => \y_int[31]_i_2_n_0\ ); \y_int[31]_i_20\: unisim.vcomponents.LUT6 generic map( INIT => X"000000007FFFFFFF" ) port map ( I0 => rgb888(22), I1 => rgb888(21), I2 => rgb888(19), I3 => rgb888(18), I4 => rgb888(20), I5 => rgb888(23), O => \y_int[31]_i_20_n_0\ ); \y_int[31]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[31]_i_3_n_0\ ); \y_int[31]_i_32\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \rgb888[0]_7\(3), I1 => \y_int_reg[31]_i_75_n_2\, O => \y_int[31]_i_32_n_0\ ); \y_int[31]_i_33\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \rgb888[0]_9\(2), O => \y_int[31]_i_33_n_0\ ); \y_int[31]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \rgb888[0]_9\(2), O => \y_int[31]_i_34_n_0\ ); \y_int[31]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \y_int_reg[31]_i_75_n_2\, I1 => \rgb888[0]_9\(0), I2 => \rgb888[0]_9\(1), O => \y_int[31]_i_35_n_0\ ); \y_int[31]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"36" ) port map ( I0 => \rgb888[0]_7\(3), I1 => \rgb888[0]_9\(0), I2 => \y_int_reg[31]_i_75_n_2\, O => \y_int[31]_i_36_n_0\ ); \y_int[31]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[31]_i_4_n_0\ ); \y_int[31]_i_40\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => rgb888(20), I1 => rgb888(18), I2 => rgb888(19), I3 => rgb888(21), I4 => rgb888(22), O => \y_int[31]_i_40_n_0\ ); \y_int[31]_i_41\: unisim.vcomponents.LUT5 generic map( INIT => X"BEEEEEEE" ) port map ( I0 => \y_int_reg[3]_i_64_n_2\, I1 => rgb888(21), I2 => rgb888(20), I3 => rgb888(18), I4 => rgb888(19), O => \y_int[31]_i_41_n_0\ ); \y_int[31]_i_42\: unisim.vcomponents.LUT5 generic map( INIT => X"7FD51540" ) port map ( I0 => \y_int_reg[3]_i_64_n_2\, I1 => rgb888(18), I2 => rgb888(19), I3 => rgb888(20), I4 => rgb888(23), O => \y_int[31]_i_42_n_0\ ); \y_int[31]_i_43\: unisim.vcomponents.LUT4 generic map( INIT => X"BE28" ) port map ( I0 => \y_int_reg[3]_i_64_n_7\, I1 => rgb888(18), I2 => rgb888(19), I3 => rgb888(22), O => \y_int[31]_i_43_n_0\ ); \y_int[31]_i_44\: unisim.vcomponents.LUT6 generic map( INIT => X"A999999999999999" ) port map ( I0 => rgb888(23), I1 => rgb888(22), I2 => rgb888(21), I3 => rgb888(19), I4 => rgb888(18), I5 => rgb888(20), O => \y_int[31]_i_44_n_0\ ); \y_int[31]_i_45\: unisim.vcomponents.LUT6 generic map( INIT => X"6CC9C9C9C9C9C9C9" ) port map ( I0 => \y_int_reg[3]_i_64_n_2\, I1 => rgb888(22), I2 => rgb888(21), I3 => rgb888(19), I4 => rgb888(18), I5 => rgb888(20), O => \y_int[31]_i_45_n_0\ ); \y_int[31]_i_46\: unisim.vcomponents.LUT6 generic map( INIT => X"157FEA807FEA8015" ) port map ( I0 => rgb888(23), I1 => rgb888(19), I2 => rgb888(18), I3 => rgb888(20), I4 => rgb888(21), I5 => \y_int_reg[3]_i_64_n_2\, O => \y_int[31]_i_46_n_0\ ); \y_int[31]_i_47\: unisim.vcomponents.LUT6 generic map( INIT => X"6996966996699669" ) port map ( I0 => \y_int[31]_i_43_n_0\, I1 => \y_int_reg[3]_i_64_n_2\, I2 => rgb888(23), I3 => rgb888(20), I4 => rgb888(19), I5 => rgb888(18), O => \y_int[31]_i_47_n_0\ ); \y_int[31]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[31]_i_5_n_0\ ); \y_int[31]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"659A659A9A65659A" ) port map ( I0 => \y_int[31]_i_2_n_0\, I1 => \rgb888[1]_0\(0), I2 => \^y_int_reg[23]_0\(0), I3 => \y_int[31]_i_13_n_0\, I4 => \y_int_reg[31]_i_8_n_5\, I5 => \y_int_reg[31]_i_7_n_1\, O => \y_int[31]_i_6_n_0\ ); \y_int[31]_i_63\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \rgb888[0]_7\(2), I1 => \y_int_reg[31]_i_75_n_7\, O => \y_int[31]_i_63_n_0\ ); \y_int[31]_i_64\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \y_int_reg[31]_i_87_n_4\, I1 => \rgb888[0]_7\(1), O => \y_int[31]_i_64_n_0\ ); \y_int[31]_i_65\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \y_int_reg[31]_i_87_n_4\, I1 => \rgb888[0]_7\(1), O => \y_int[31]_i_65_n_0\ ); \y_int[31]_i_66\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \y_int_reg[31]_i_86_n_4\, I1 => \y_int_reg[31]_i_87_n_6\, O => \y_int[31]_i_66_n_0\ ); \y_int[31]_i_67\: unisim.vcomponents.LUT4 generic map( INIT => X"7887" ) port map ( I0 => \y_int_reg[31]_i_75_n_7\, I1 => \rgb888[0]_7\(2), I2 => \y_int_reg[31]_i_75_n_2\, I3 => \rgb888[0]_7\(3), O => \y_int[31]_i_67_n_0\ ); \y_int[31]_i_68\: unisim.vcomponents.LUT4 generic map( INIT => X"E11E" ) port map ( I0 => \rgb888[0]_7\(1), I1 => \y_int_reg[31]_i_87_n_4\, I2 => \rgb888[0]_7\(2), I3 => \y_int_reg[31]_i_75_n_7\, O => \y_int[31]_i_68_n_0\ ); \y_int[31]_i_69\: unisim.vcomponents.LUT4 generic map( INIT => X"6999" ) port map ( I0 => \rgb888[0]_7\(1), I1 => \y_int_reg[31]_i_87_n_4\, I2 => \y_int_reg[31]_i_87_n_5\, I3 => \rgb888[0]_7\(0), O => \y_int[31]_i_69_n_0\ ); \y_int[31]_i_70\: unisim.vcomponents.LUT4 generic map( INIT => X"8778" ) port map ( I0 => \y_int_reg[31]_i_87_n_6\, I1 => \y_int_reg[31]_i_86_n_4\, I2 => \rgb888[0]_7\(0), I3 => \y_int_reg[31]_i_87_n_5\, O => \y_int[31]_i_70_n_0\ ); \y_int[31]_i_89\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \y_int_reg[31]_i_86_n_5\, I1 => \y_int_reg[31]_i_86_n_4\, I2 => \y_int_reg[31]_i_87_n_6\, O => \y_int[31]_i_89_n_0\ ); \y_int[31]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \y_int_reg[31]_i_86_n_5\, I1 => \y_int_reg[31]_i_87_n_7\, O => \y_int[31]_i_90_n_0\ ); \y_int[31]_i_91\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[31]_i_88_n_4\, I1 => \y_int_reg[31]_i_86_n_6\, O => \y_int[31]_i_91_n_0\ ); \y_int[31]_i_92\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[31]_i_88_n_5\, I1 => rgb888(0), O => \y_int[31]_i_92_n_0\ ); \y_int[3]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[7]_i_24_n_6\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[14]\(3), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_1\(0), O => \y_int[3]_i_10_n_0\ ); \y_int[3]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(2), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_30_n_4\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_44_n_6\, O => y_int_reg1(2) ); \y_int[3]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(1), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[3]_i_16_n_4\, I3 => y_int_reg6, I4 => y_int_reg5(9), O => y_int_reg20_in(1) ); \y_int[3]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[7]_i_24_n_7\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[14]\(2), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_0\(1), O => \y_int[3]_i_13_n_0\ ); \y_int[3]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(1), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_30_n_5\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_44_n_7\, O => y_int_reg1(1) ); \y_int[3]_i_17\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \rgb888[14]\(1), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[14]_0\(0), O => \y_int[3]_i_17_n_0\ ); \y_int[3]_i_18\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \y_int_reg[31]_i_30_n_6\, I1 => \^y_int_reg[7]_0\(0), I2 => \y_int_reg[3]_i_35_n_4\, O => \y_int[3]_i_18_n_0\ ); \y_int[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(2), I1 => \y_int[3]_i_10_n_0\, I2 => y_int_reg1(2), O => \y_int[3]_i_2_n_0\ ); \y_int[3]_i_22\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_5\, O => \y_int[3]_i_22_n_0\ ); \y_int[3]_i_23\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_6\, O => \y_int[3]_i_23_n_0\ ); \y_int[3]_i_24\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_16_n_7\, O => \y_int[3]_i_24_n_0\ ); \y_int[3]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_4\, O => \y_int[3]_i_25_n_0\ ); \y_int[3]_i_27\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => rgb888(18), I1 => \y_int_reg[3]_i_30_n_4\, I2 => rgb888(21), O => \y_int[3]_i_27_n_0\ ); \y_int[3]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \y_int_reg[3]_i_30_n_5\, I1 => rgb888(17), I2 => rgb888(20), O => \y_int[3]_i_28_n_0\ ); \y_int[3]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \y_int_reg[3]_i_30_n_5\, I1 => rgb888(17), I2 => rgb888(20), O => \y_int[3]_i_29_n_0\ ); \y_int[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(1), I1 => \y_int[3]_i_13_n_0\, I2 => y_int_reg1(1), O => \y_int[3]_i_3_n_0\ ); \y_int[3]_i_31\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \y_int[3]_i_27_n_0\, I1 => rgb888(22), I2 => rgb888(19), I3 => rgb888(18), I4 => \y_int_reg[3]_i_64_n_7\, O => \y_int[3]_i_31_n_0\ ); \y_int[3]_i_32\: unisim.vcomponents.LUT6 generic map( INIT => X"E81717E817E8E817" ) port map ( I0 => rgb888(20), I1 => rgb888(17), I2 => \y_int_reg[3]_i_30_n_5\, I3 => rgb888(21), I4 => rgb888(18), I5 => \y_int_reg[3]_i_30_n_4\, O => \y_int[3]_i_32_n_0\ ); \y_int[3]_i_33\: unisim.vcomponents.LUT5 generic map( INIT => X"69969696" ) port map ( I0 => rgb888(20), I1 => rgb888(17), I2 => \y_int_reg[3]_i_30_n_5\, I3 => rgb888(19), I4 => rgb888(16), O => \y_int[3]_i_33_n_0\ ); \y_int[3]_i_34\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(16), I1 => rgb888(19), I2 => \y_int_reg[3]_i_30_n_6\, O => \y_int[3]_i_34_n_0\ ); \y_int[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFE2E200" ) port map ( I0 => y_int_reg5(8), I1 => y_int_reg6, I2 => \y_int_reg[3]_i_16_n_5\, I3 => \y_int[3]_i_17_n_0\, I4 => \y_int[3]_i_18_n_0\, O => \y_int[3]_i_4_n_0\ ); \y_int[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(3), I1 => \y_int[7]_i_19_n_0\, I2 => y_int_reg1(3), I3 => \y_int[3]_i_2_n_0\, O => \y_int[3]_i_5_n_0\ ); \y_int[3]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(16), O => \y_int[3]_i_50_n_0\ ); \y_int[3]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_5\, O => \y_int[3]_i_51_n_0\ ); \y_int[3]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_6\, O => \y_int[3]_i_52_n_0\ ); \y_int[3]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_26_n_7\, O => \y_int[3]_i_53_n_0\ ); \y_int[3]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(17), O => \y_int[3]_i_54_n_0\ ); \y_int[3]_i_56\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[3]_i_30_n_7\, I1 => rgb888(18), O => \y_int[3]_i_56_n_0\ ); \y_int[3]_i_57\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[3]_i_55_n_4\, I1 => rgb888(17), O => \y_int[3]_i_57_n_0\ ); \y_int[3]_i_58\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \y_int_reg[3]_i_55_n_5\, I1 => rgb888(16), O => \y_int[3]_i_58_n_0\ ); \y_int[3]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \y_int_reg[3]_i_55_n_6\, O => \y_int[3]_i_59_n_0\ ); \y_int[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(2), I1 => \y_int[3]_i_10_n_0\, I2 => y_int_reg1(2), I3 => \y_int[3]_i_3_n_0\, O => \y_int[3]_i_6_n_0\ ); \y_int[3]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(22), O => \y_int[3]_i_60_n_0\ ); \y_int[3]_i_61\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(23), I1 => rgb888(21), O => \y_int[3]_i_61_n_0\ ); \y_int[3]_i_62\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(22), I1 => rgb888(20), O => \y_int[3]_i_62_n_0\ ); \y_int[3]_i_63\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(21), I1 => rgb888(19), O => \y_int[3]_i_63_n_0\ ); \y_int[3]_i_66\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_6\, O => \y_int[3]_i_66_n_0\ ); \y_int[3]_i_67\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_30_n_7\, O => \y_int[3]_i_67_n_0\ ); \y_int[3]_i_68\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_62_n_4\, O => \y_int[3]_i_68_n_0\ ); \y_int[3]_i_69\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_62_n_5\, O => \y_int[3]_i_69_n_0\ ); \y_int[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(1), I1 => \y_int[3]_i_13_n_0\, I2 => y_int_reg1(1), I3 => \y_int[3]_i_4_n_0\, O => \y_int[3]_i_7_n_0\ ); \y_int[3]_i_71\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_32\(1), I1 => rgb888(10), O => \y_int[3]_i_71_n_0\ ); \y_int[3]_i_72\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_32\(0), I1 => rgb888(9), O => \y_int[3]_i_72_n_0\ ); \y_int[3]_i_73\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rgb888[8]_19\(2), I1 => rgb888(8), O => \y_int[3]_i_73_n_0\ ); \y_int[3]_i_74\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => \rgb888[8]_19\(1), O => \y_int[3]_i_74_n_0\ ); \y_int[3]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"E21D1DE2" ) port map ( I0 => y_int_reg5(8), I1 => y_int_reg6, I2 => \y_int_reg[3]_i_16_n_5\, I3 => \y_int[3]_i_17_n_0\, I4 => \y_int[3]_i_18_n_0\, O => \y_int[3]_i_8_n_0\ ); \y_int[3]_i_84\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(20), I1 => rgb888(18), O => \y_int[3]_i_84_n_0\ ); \y_int[3]_i_85\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(19), I1 => rgb888(17), O => \y_int[3]_i_85_n_0\ ); \y_int[3]_i_86\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(18), I1 => rgb888(16), O => \y_int[3]_i_86_n_0\ ); \y_int[3]_i_87\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(17), O => \y_int[3]_i_87_n_0\ ); \y_int[3]_i_88\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(23), O => \y_int[3]_i_88_n_0\ ); \y_int[3]_i_89\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_62_n_6\, O => \y_int[3]_i_89_n_0\ ); \y_int[3]_i_9\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(2), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_16_n_7\, I3 => y_int_reg6, I4 => y_int_reg5(10), O => y_int_reg20_in(2) ); \y_int[3]_i_90\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(0), I1 => \y_int_reg[31]_i_88_n_5\, O => \y_int[3]_i_90_n_0\ ); \y_int[3]_i_91\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_88_n_6\, O => \y_int[3]_i_91_n_0\ ); \y_int[3]_i_92\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(1), O => \y_int[3]_i_92_n_0\ ); \y_int[7]_i_10\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(6), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_8_n_7\, I3 => y_int_reg6, I4 => y_int_reg5(14), O => y_int_reg20_in(6) ); \y_int[7]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[11]_i_38_n_6\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_20\(3), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[8]_22\(0), O => \y_int[7]_i_11_n_0\ ); \y_int[7]_i_12\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(5), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_16_n_4\, I3 => y_int_reg6, I4 => y_int_reg5(13), O => y_int_reg20_in(5) ); \y_int[7]_i_13\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[11]_i_38_n_7\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_20\(2), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_1\(3), O => \y_int[7]_i_13_n_0\ ); \y_int[7]_i_14\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(5), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_11_n_5\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_21_n_7\, O => y_int_reg1(5) ); \y_int[7]_i_15\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(4), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_16_n_5\, I3 => y_int_reg6, I4 => y_int_reg5(12), O => y_int_reg20_in(4) ); \y_int[7]_i_16\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[7]_i_24_n_4\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_20\(1), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_1\(2), O => \y_int[7]_i_16_n_0\ ); \y_int[7]_i_17\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(4), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_11_n_6\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_44_n_4\, O => y_int_reg1(4) ); \y_int[7]_i_18\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg3(3), I1 => \y_int_reg[31]_i_8_n_5\, I2 => \y_int_reg[31]_i_16_n_6\, I3 => y_int_reg6, I4 => y_int_reg5(11), O => y_int_reg20_in(3) ); \y_int[7]_i_19\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \y_int_reg[7]_i_24_n_5\, I1 => \rgb888[8]_21\(2), I2 => \rgb888[8]_20\(0), I3 => \^y_int_reg[3]_1\(0), I4 => \rgb888[14]_1\(1), O => \y_int[7]_i_19_n_0\ ); \y_int[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"E888E888E8EEE888" ) port map ( I0 => y_int_reg20_in(6), I1 => \y_int[7]_i_11_n_0\, I2 => y_int_reg2(6), I3 => \^y_int_reg[23]_0\(0), I4 => \y_int_reg[11]_i_21_n_6\, I5 => \^y_int_reg[7]_0\(0), O => \y_int[7]_i_2_n_0\ ); \y_int[7]_i_20\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => y_int_reg2(3), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[31]_i_11_n_7\, I3 => \^y_int_reg[7]_0\(0), I4 => \y_int_reg[11]_i_44_n_5\, O => y_int_reg1(3) ); \y_int[7]_i_21\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg2(7), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[11]_i_21_n_5\, I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(7) ); \y_int[7]_i_22\: unisim.vcomponents.LUT4 generic map( INIT => X"88B8" ) port map ( I0 => y_int_reg2(6), I1 => \^y_int_reg[23]_0\(0), I2 => \y_int_reg[11]_i_21_n_6\, I3 => \^y_int_reg[7]_0\(0), O => y_int_reg1(6) ); \y_int[7]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_0\(0), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[14]\(1), O => \y_int[7]_i_29_n_0\ ); \y_int[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(5), I1 => \y_int[7]_i_13_n_0\, I2 => y_int_reg1(5), O => \y_int[7]_i_3_n_0\ ); \y_int[7]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_1\(2), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_20\(1), O => \y_int[7]_i_30_n_0\ ); \y_int[7]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_1\(1), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[8]_20\(0), O => \y_int[7]_i_31_n_0\ ); \y_int[7]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_1\(0), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[14]\(3), O => \y_int[7]_i_32_n_0\ ); \y_int[7]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \rgb888[14]_0\(1), I1 => \^y_int_reg[3]_1\(0), I2 => \rgb888[14]\(2), O => \y_int[7]_i_33_n_0\ ); \y_int[7]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(4), I1 => \y_int[7]_i_16_n_0\, I2 => y_int_reg1(4), O => \y_int[7]_i_4_n_0\ ); \y_int[7]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => y_int_reg20_in(3), I1 => \y_int[7]_i_19_n_0\, I2 => y_int_reg1(3), O => \y_int[7]_i_5_n_0\ ); \y_int[7]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[7]_i_2_n_0\, I1 => y_int_reg1(7), I2 => \y_int[11]_i_19_n_0\, I3 => y_int_reg20_in(7), O => \y_int[7]_i_6_n_0\ ); \y_int[7]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => \y_int[7]_i_3_n_0\, I1 => y_int_reg1(6), I2 => \y_int[7]_i_11_n_0\, I3 => y_int_reg20_in(6), O => \y_int[7]_i_7_n_0\ ); \y_int[7]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(5), I1 => \y_int[7]_i_13_n_0\, I2 => y_int_reg1(5), I3 => \y_int[7]_i_4_n_0\, O => \y_int[7]_i_8_n_0\ ); \y_int[7]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => y_int_reg20_in(4), I1 => \y_int[7]_i_16_n_0\, I2 => y_int_reg1(4), I3 => \y_int[7]_i_5_n_0\, O => \y_int[7]_i_9_n_0\ ); \y_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[3]_i_1_n_7\, Q => \y_int_reg_n_0_[0]\, R => '0' ); \y_int_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[11]_i_1_n_5\, Q => \y_int_reg__0\(10), R => '0' ); \y_int_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[11]_i_1_n_4\, Q => \y_int_reg__0\(11), R => '0' ); \y_int_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[7]_i_1_n_0\, CO(3) => \y_int_reg[11]_i_1_n_0\, CO(2) => \y_int_reg[11]_i_1_n_1\, CO(1) => \y_int_reg[11]_i_1_n_2\, CO(0) => \y_int_reg[11]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[11]_i_2_n_0\, DI(2) => \y_int[11]_i_3_n_0\, DI(1) => \y_int[11]_i_4_n_0\, DI(0) => \y_int[11]_i_5_n_0\, O(3) => \y_int_reg[11]_i_1_n_4\, O(2) => \y_int_reg[11]_i_1_n_5\, O(1) => \y_int_reg[11]_i_1_n_6\, O(0) => \y_int_reg[11]_i_1_n_7\, S(3) => \y_int[11]_i_6_n_0\, S(2) => \y_int[11]_i_7_n_0\, S(1) => \y_int[11]_i_8_n_0\, S(0) => \y_int[11]_i_9_n_0\ ); \y_int_reg[11]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_28_n_0\, CO(3) => \y_int_reg[11]_i_14_n_0\, CO(2) => \y_int_reg[11]_i_14_n_1\, CO(1) => \y_int_reg[11]_i_14_n_2\, CO(0) => \y_int_reg[11]_i_14_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(16 downto 13), S(3) => \y_int[11]_i_29_n_0\, S(2) => \y_int[11]_i_30_n_0\, S(1) => \y_int[11]_i_31_n_0\, S(0) => \y_int[11]_i_32_n_0\ ); \y_int_reg[11]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_33_n_0\, CO(3) => \y_int_reg[11]_i_15_n_0\, CO(2) => \y_int_reg[11]_i_15_n_1\, CO(1) => \y_int_reg[11]_i_15_n_2\, CO(0) => \y_int_reg[11]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(8 downto 5), S(3) => \y_int[11]_i_34_n_0\, S(2) => \y_int[11]_i_35_n_0\, S(1) => \y_int[11]_i_36_n_0\, S(0) => \y_int[11]_i_37_n_0\ ); \y_int_reg[11]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_39_n_0\, CO(3) => \y_int_reg[15]_1\(0), CO(2) => \y_int_reg[11]_i_20_n_1\, CO(1) => \y_int_reg[11]_i_20_n_2\, CO(0) => \y_int_reg[11]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(8 downto 5), S(3) => \y_int[11]_i_40_n_0\, S(2) => \y_int[11]_i_41_n_0\, S(1) => \y_int[11]_i_42_n_0\, S(0) => \y_int[11]_i_43_n_0\ ); \y_int_reg[11]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_44_n_0\, CO(3) => \y_int_reg[11]_i_21_n_0\, CO(2) => \y_int_reg[11]_i_21_n_1\, CO(1) => \y_int_reg[11]_i_21_n_2\, CO(0) => \y_int_reg[11]_i_21_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[11]_i_21_n_4\, O(2) => \y_int_reg[11]_i_21_n_5\, O(1) => \y_int_reg[11]_i_21_n_6\, O(0) => \y_int_reg[11]_i_21_n_7\, S(3) => \y_int[11]_i_45_n_0\, S(2) => \y_int[11]_i_46_n_0\, S(1) => \y_int[11]_i_47_n_0\, S(0) => \y_int[11]_i_48_n_0\ ); \y_int_reg[11]_i_22\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_49_n_0\, CO(3) => \^y_int_reg[7]_0\(0), CO(2) => \y_int_reg[11]_i_22_n_1\, CO(1) => \y_int_reg[11]_i_22_n_2\, CO(0) => \y_int_reg[11]_i_22_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \^y_int_reg[23]_0\(0), DI(1) => \^y_int_reg[23]_0\(0), DI(0) => \^y_int_reg[23]_0\(0), O(3 downto 0) => \NLW_y_int_reg[11]_i_22_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[11]_i_50_n_0\, S(2) => \y_int[11]_i_51_n_0\, S(1) => \y_int[11]_i_52_n_0\, S(0) => \y_int[11]_i_53_n_0\ ); \y_int_reg[11]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_15_n_0\, CO(3) => \y_int_reg[11]_i_28_n_0\, CO(2) => \y_int_reg[11]_i_28_n_1\, CO(1) => \y_int_reg[11]_i_28_n_2\, CO(0) => \y_int_reg[11]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(12 downto 9), S(3) => \y_int[11]_i_58_n_0\, S(2) => \y_int[11]_i_59_n_0\, S(1) => \y_int[11]_i_60_n_0\, S(0) => \y_int[11]_i_61_n_0\ ); \y_int_reg[11]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[11]_i_33_n_0\, CO(2) => \y_int_reg[11]_i_33_n_1\, CO(1) => \y_int_reg[11]_i_33_n_2\, CO(0) => \y_int_reg[11]_i_33_n_3\, CYINIT => \y_int[11]_i_62_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(4 downto 1), S(3) => \y_int[11]_i_63_n_0\, S(2) => \y_int[11]_i_64_n_0\, S(1) => \y_int[11]_i_65_n_0\, S(0) => \y_int[11]_i_66_n_0\ ); \y_int_reg[11]_i_38\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[7]_i_24_n_0\, CO(3) => \y_int_reg[11]_i_38_n_0\, CO(2) => \y_int_reg[11]_i_38_n_1\, CO(1) => \y_int_reg[11]_i_38_n_2\, CO(0) => \y_int_reg[11]_i_38_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[11]_i_38_n_4\, O(2) => \y_int_reg[11]_i_38_n_5\, O(1) => \y_int_reg[11]_i_38_n_6\, O(0) => \y_int_reg[11]_i_38_n_7\, S(3) => \y_int[11]_i_67_n_0\, S(2) => \y_int[11]_i_68_n_0\, S(1) => \y_int[11]_i_69_n_0\, S(0) => \y_int[11]_i_70_n_0\ ); \y_int_reg[11]_i_39\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[11]_i_39_n_0\, CO(2) => \y_int_reg[11]_i_39_n_1\, CO(1) => \y_int_reg[11]_i_39_n_2\, CO(0) => \y_int_reg[11]_i_39_n_3\, CYINIT => \y_int[11]_i_71_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(4 downto 1), S(3) => \y_int[11]_i_72_n_0\, S(2) => \y_int[11]_i_73_n_0\, S(1) => \y_int[11]_i_74_n_0\, S(0) => \y_int[11]_i_75_n_0\ ); \y_int_reg[11]_i_44\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_35_n_0\, CO(3) => \y_int_reg[11]_i_44_n_0\, CO(2) => \y_int_reg[11]_i_44_n_1\, CO(1) => \y_int_reg[11]_i_44_n_2\, CO(0) => \y_int_reg[11]_i_44_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[11]_i_44_n_4\, O(2) => \y_int_reg[11]_i_44_n_5\, O(1) => \y_int_reg[11]_i_44_n_6\, O(0) => \y_int_reg[11]_i_44_n_7\, S(3) => \y_int[11]_i_76_n_0\, S(2) => \y_int[11]_i_77_n_0\, S(1) => \y_int[11]_i_78_n_0\, S(0) => \y_int[11]_i_79_n_0\ ); \y_int_reg[11]_i_49\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_80_n_0\, CO(3) => \y_int_reg[11]_i_49_n_0\, CO(2) => \y_int_reg[11]_i_49_n_1\, CO(1) => \y_int_reg[11]_i_49_n_2\, CO(0) => \y_int_reg[11]_i_49_n_3\, CYINIT => '0', DI(3) => \^y_int_reg[23]_0\(0), DI(2) => \^y_int_reg[23]_0\(0), DI(1) => \^y_int_reg[23]_0\(0), DI(0) => \^y_int_reg[23]_0\(0), O(3 downto 0) => \NLW_y_int_reg[11]_i_49_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[11]_i_81_n_0\, S(2) => \y_int[11]_i_82_n_0\, S(1) => \y_int[11]_i_83_n_0\, S(0) => \y_int[11]_i_84_n_0\ ); \y_int_reg[11]_i_80\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_85_n_0\, CO(3) => \y_int_reg[11]_i_80_n_0\, CO(2) => \y_int_reg[11]_i_80_n_1\, CO(1) => \y_int_reg[11]_i_80_n_2\, CO(0) => \y_int_reg[11]_i_80_n_3\, CYINIT => '0', DI(3) => \^y_int_reg[23]_0\(0), DI(2) => \y_int[11]_i_86_n_0\, DI(1) => \y_int[11]_i_87_n_0\, DI(0) => \y_int[11]_i_88_n_0\, O(3 downto 0) => \NLW_y_int_reg[11]_i_80_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[11]_i_89_n_0\, S(2) => \y_int[11]_i_90_n_0\, S(1) => \y_int[11]_i_91_n_0\, S(0) => \y_int[11]_i_92_n_0\ ); \y_int_reg[11]_i_85\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[11]_i_85_n_0\, CO(2) => \y_int_reg[11]_i_85_n_1\, CO(1) => \y_int_reg[11]_i_85_n_2\, CO(0) => \y_int_reg[11]_i_85_n_3\, CYINIT => '1', DI(3) => \y_int[11]_i_93_n_0\, DI(2) => \y_int[11]_i_94_n_0\, DI(1) => \y_int[11]_i_95_n_0\, DI(0) => \y_int[11]_i_96_n_0\, O(3 downto 0) => \NLW_y_int_reg[11]_i_85_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[11]_i_97_n_0\, S(2) => \y_int[11]_i_98_n_0\, S(1) => \y_int[11]_i_99_n_0\, S(0) => \y_int[11]_i_100_n_0\ ); \y_int_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[15]_i_1_n_7\, Q => \y_int_reg__0\(12), R => '0' ); \y_int_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[15]_i_1_n_6\, Q => \y_int_reg__0\(13), R => '0' ); \y_int_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[15]_i_1_n_5\, Q => \y_int_reg__0\(14), R => '0' ); \y_int_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[15]_i_1_n_4\, Q => \y_int_reg__0\(15), R => '0' ); \y_int_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_1_n_0\, CO(3) => \y_int_reg[15]_i_1_n_0\, CO(2) => \y_int_reg[15]_i_1_n_1\, CO(1) => \y_int_reg[15]_i_1_n_2\, CO(0) => \y_int_reg[15]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[15]_i_2_n_0\, DI(2) => \y_int[15]_i_3_n_0\, DI(1) => \y_int[15]_i_4_n_0\, DI(0) => \y_int[15]_i_5_n_0\, O(3) => \y_int_reg[15]_i_1_n_4\, O(2) => \y_int_reg[15]_i_1_n_5\, O(1) => \y_int_reg[15]_i_1_n_6\, O(0) => \y_int_reg[15]_i_1_n_7\, S(3) => \y_int[15]_i_6_n_0\, S(2) => \y_int[15]_i_7_n_0\, S(1) => \y_int[15]_i_8_n_0\, S(0) => \y_int[15]_i_9_n_0\ ); \y_int_reg[15]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_14_n_0\, CO(3) => \y_int_reg[15]_i_14_n_0\, CO(2) => \y_int_reg[15]_i_14_n_1\, CO(1) => \y_int_reg[15]_i_14_n_2\, CO(0) => \y_int_reg[15]_i_14_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(20 downto 17), S(3) => \y_int[15]_i_25_n_0\, S(2) => \y_int[15]_i_26_n_0\, S(1) => \y_int[15]_i_27_n_0\, S(0) => \y_int[15]_i_28_n_0\ ); \y_int_reg[15]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_15_n_0\, CO(3) => \y_int_reg[15]_i_15_n_0\, CO(2) => \y_int_reg[15]_i_15_n_1\, CO(1) => \y_int_reg[15]_i_15_n_2\, CO(0) => \y_int_reg[15]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(12 downto 9), S(3) => \y_int[15]_i_29_n_0\, S(2) => \y_int[15]_i_30_n_0\, S(1) => \y_int[15]_i_31_n_0\, S(0) => \y_int[15]_i_32_n_0\ ); \y_int_reg[15]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_38_n_0\, CO(3) => \y_int_reg[19]_1\(0), CO(2) => \y_int_reg[15]_i_33_n_1\, CO(1) => \y_int_reg[15]_i_33_n_2\, CO(0) => \y_int_reg[15]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[15]_i_33_n_4\, O(2) => \y_int_reg[15]_i_33_n_5\, O(1) => \y_int_reg[15]_i_33_n_6\, O(0) => \y_int_reg[15]_i_33_n_7\, S(3) => \y_int[15]_i_40_n_0\, S(2) => \y_int[15]_i_41_n_0\, S(1) => \y_int[15]_i_42_n_0\, S(0) => \y_int[15]_i_43_n_0\ ); \y_int_reg[15]_i_35\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_21_n_0\, CO(3) => \y_int_reg[15]_i_35_n_0\, CO(2) => \y_int_reg[15]_i_35_n_1\, CO(1) => \y_int_reg[15]_i_35_n_2\, CO(0) => \y_int_reg[15]_i_35_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^y_int_reg[15]_0\(3 downto 0), S(3) => \y_int[15]_i_48_n_0\, S(2) => \y_int[15]_i_49_n_0\, S(1) => \y_int[15]_i_50_n_0\, S(0) => \y_int[15]_i_51_n_0\ ); \y_int_reg[16]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[19]_i_1_n_7\, Q => \y_int_reg__0\(16), R => '0' ); \y_int_reg[17]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[19]_i_1_n_6\, Q => \y_int_reg__0\(17), R => '0' ); \y_int_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[19]_i_1_n_5\, Q => \y_int_reg__0\(18), R => '0' ); \y_int_reg[19]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[19]_i_1_n_4\, Q => \y_int_reg__0\(19), R => '0' ); \y_int_reg[19]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_1_n_0\, CO(3) => \y_int_reg[19]_i_1_n_0\, CO(2) => \y_int_reg[19]_i_1_n_1\, CO(1) => \y_int_reg[19]_i_1_n_2\, CO(0) => \y_int_reg[19]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[19]_i_2_n_0\, DI(2) => \y_int[19]_i_3_n_0\, DI(1) => \y_int[19]_i_4_n_0\, DI(0) => \y_int[19]_i_5_n_0\, O(3) => \y_int_reg[19]_i_1_n_4\, O(2) => \y_int_reg[19]_i_1_n_5\, O(1) => \y_int_reg[19]_i_1_n_6\, O(0) => \y_int_reg[19]_i_1_n_7\, S(3) => \y_int[19]_i_6_n_0\, S(2) => \y_int[19]_i_7_n_0\, S(1) => \y_int[19]_i_8_n_0\, S(0) => \y_int[19]_i_9_n_0\ ); \y_int_reg[19]_i_14\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_14_n_0\, CO(3) => \y_int_reg[19]_i_14_n_0\, CO(2) => \y_int_reg[19]_i_14_n_1\, CO(1) => \y_int_reg[19]_i_14_n_2\, CO(0) => \y_int_reg[19]_i_14_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(24 downto 21), S(3) => \y_int[19]_i_25_n_0\, S(2) => \y_int[19]_i_26_n_0\, S(1) => \y_int[19]_i_27_n_0\, S(0) => \y_int[19]_i_28_n_0\ ); \y_int_reg[19]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_15_n_0\, CO(3) => \y_int_reg[19]_i_15_n_0\, CO(2) => \y_int_reg[19]_i_15_n_1\, CO(1) => \y_int_reg[19]_i_15_n_2\, CO(0) => \y_int_reg[19]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(16 downto 13), S(3) => \y_int[19]_i_29_n_0\, S(2) => \y_int[19]_i_30_n_0\, S(1) => \y_int[19]_i_31_n_0\, S(0) => \y_int[19]_i_32_n_0\ ); \y_int_reg[19]_i_35\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_35_n_0\, CO(3) => \y_int_reg[19]_i_35_n_0\, CO(2) => \y_int_reg[19]_i_35_n_1\, CO(1) => \y_int_reg[19]_i_35_n_2\, CO(0) => \y_int_reg[19]_i_35_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^y_int_reg[19]_0\(3 downto 0), S(3) => \y_int[19]_i_48_n_0\, S(2) => \y_int[19]_i_49_n_0\, S(1) => \y_int[19]_i_50_n_0\, S(0) => \y_int[19]_i_51_n_0\ ); \y_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[3]_i_1_n_6\, Q => \y_int_reg_n_0_[1]\, R => '0' ); \y_int_reg[20]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[23]_i_1_n_7\, Q => \y_int_reg__0\(20), R => '0' ); \y_int_reg[21]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[23]_i_1_n_6\, Q => \y_int_reg__0\(21), R => '0' ); \y_int_reg[22]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[23]_i_1_n_5\, Q => \y_int_reg__0\(22), R => '0' ); \y_int_reg[23]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[23]_i_1_n_4\, Q => \y_int_reg__0\(23), R => '0' ); \y_int_reg[23]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_1_n_0\, CO(3) => \y_int_reg[23]_i_1_n_0\, CO(2) => \y_int_reg[23]_i_1_n_1\, CO(1) => \y_int_reg[23]_i_1_n_2\, CO(0) => \y_int_reg[23]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[23]_i_2_n_0\, DI(2) => \y_int[23]_i_3_n_0\, DI(1) => \y_int[23]_i_4_n_0\, DI(0) => \y_int[23]_i_5_n_0\, O(3) => \y_int_reg[23]_i_1_n_4\, O(2) => \y_int_reg[23]_i_1_n_5\, O(1) => \y_int_reg[23]_i_1_n_6\, O(0) => \y_int_reg[23]_i_1_n_7\, S(3) => \y_int[23]_i_6_n_0\, S(2) => \y_int[23]_i_7_n_0\, S(1) => \y_int[23]_i_8_n_0\, S(0) => \y_int[23]_i_9_n_0\ ); \y_int_reg[23]_i_10\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_25_n_0\, CO(3) => y_int_reg6, CO(2) => \y_int_reg[23]_i_10_n_1\, CO(1) => \y_int_reg[23]_i_10_n_2\, CO(0) => \y_int_reg[23]_i_10_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \y_int_reg[31]_i_8_n_5\, DI(1) => \y_int_reg[31]_i_8_n_5\, DI(0) => \y_int_reg[31]_i_8_n_5\, O(3 downto 0) => \NLW_y_int_reg[23]_i_10_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_26_n_0\, S(2) => \y_int[23]_i_27_n_0\, S(1) => \y_int[23]_i_28_n_0\, S(0) => \y_int[23]_i_29_n_0\ ); \y_int_reg[23]_i_11\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_16_n_0\, CO(3 downto 1) => \NLW_y_int_reg[23]_i_11_CO_UNCONNECTED\(3 downto 1), CO(0) => \y_int_reg[23]_i_11_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[23]_i_11_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => y_int_reg5(30 downto 29), S(3 downto 2) => B"00", S(1) => \y_int[23]_i_30_n_0\, S(0) => \y_int[23]_i_31_n_0\ ); \y_int_reg[23]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_14_n_0\, CO(3) => \y_int_reg[23]_i_16_n_0\, CO(2) => \y_int_reg[23]_i_16_n_1\, CO(1) => \y_int_reg[23]_i_16_n_2\, CO(0) => \y_int_reg[23]_i_16_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg5(28 downto 25), S(3) => \y_int[23]_i_36_n_0\, S(2) => \y_int[23]_i_37_n_0\, S(1) => \y_int[23]_i_38_n_0\, S(0) => \y_int[23]_i_39_n_0\ ); \y_int_reg[23]_i_17\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_15_n_0\, CO(3) => \y_int_reg[23]_i_17_n_0\, CO(2) => \y_int_reg[23]_i_17_n_1\, CO(1) => \y_int_reg[23]_i_17_n_2\, CO(0) => \y_int_reg[23]_i_17_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg3(20 downto 17), S(3) => \y_int[23]_i_40_n_0\, S(2) => \y_int[23]_i_41_n_0\, S(1) => \y_int[23]_i_42_n_0\, S(0) => \y_int[23]_i_43_n_0\ ); \y_int_reg[23]_i_25\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_45_n_0\, CO(3) => \y_int_reg[23]_i_25_n_0\, CO(2) => \y_int_reg[23]_i_25_n_1\, CO(1) => \y_int_reg[23]_i_25_n_2\, CO(0) => \y_int_reg[23]_i_25_n_3\, CYINIT => '0', DI(3) => \y_int_reg[31]_i_8_n_5\, DI(2) => \y_int_reg[31]_i_8_n_5\, DI(1) => \y_int_reg[31]_i_8_n_5\, DI(0) => \y_int_reg[31]_i_8_n_5\, O(3 downto 0) => \NLW_y_int_reg[23]_i_25_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_46_n_0\, S(2) => \y_int[23]_i_47_n_0\, S(1) => \y_int[23]_i_48_n_0\, S(0) => \y_int[23]_i_49_n_0\ ); \y_int_reg[23]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_51_n_0\, CO(3) => \^y_int_reg[3]_1\(0), CO(2) => \y_int_reg[23]_i_33_n_1\, CO(1) => \y_int_reg[23]_i_33_n_2\, CO(0) => \y_int_reg[23]_i_33_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \rgb888[8]_21\(2), DI(1) => \rgb888[8]_21\(2), DI(0) => \rgb888[8]_21\(2), O(3 downto 0) => \NLW_y_int_reg[23]_i_33_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_52_n_0\, S(2) => \y_int[23]_i_53_n_0\, S(1) => \y_int[23]_i_54_n_0\, S(0) => \y_int[23]_i_55_n_0\ ); \y_int_reg[23]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_44_n_0\, CO(3 downto 1) => \NLW_y_int_reg[23]_i_34_CO_UNCONNECTED\(3 downto 1), CO(0) => \y_int_reg[23]_i_34_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[23]_i_34_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => \^y_int_reg[23]_1\(1 downto 0), S(3 downto 2) => B"00", S(1) => \y_int[23]_i_56_n_0\, S(0) => \y_int[23]_i_57_n_0\ ); \y_int_reg[23]_i_44\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_35_n_0\, CO(3) => \y_int_reg[23]_i_44_n_0\, CO(2) => \y_int_reg[23]_i_44_n_1\, CO(1) => \y_int_reg[23]_i_44_n_2\, CO(0) => \y_int_reg[23]_i_44_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \^y_int_reg[23]_2\(3 downto 0), S(3) => \y_int[23]_i_62_n_0\, S(2) => \y_int[23]_i_63_n_0\, S(1) => \y_int[23]_i_64_n_0\, S(0) => \y_int[23]_i_65_n_0\ ); \y_int_reg[23]_i_45\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_66_n_0\, CO(3) => \y_int_reg[23]_i_45_n_0\, CO(2) => \y_int_reg[23]_i_45_n_1\, CO(1) => \y_int_reg[23]_i_45_n_2\, CO(0) => \y_int_reg[23]_i_45_n_3\, CYINIT => '0', DI(3) => \y_int[23]_i_67_n_0\, DI(2) => \y_int[23]_i_68_n_0\, DI(1) => \y_int[23]_i_69_n_0\, DI(0) => \y_int[23]_i_70_n_0\, O(3 downto 0) => \NLW_y_int_reg[23]_i_45_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_71_n_0\, S(2) => \y_int[23]_i_72_n_0\, S(1) => \y_int[23]_i_73_n_0\, S(0) => \y_int[23]_i_74_n_0\ ); \y_int_reg[23]_i_51\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_75_n_0\, CO(3) => \y_int_reg[23]_i_51_n_0\, CO(2) => \y_int_reg[23]_i_51_n_1\, CO(1) => \y_int_reg[23]_i_51_n_2\, CO(0) => \y_int_reg[23]_i_51_n_3\, CYINIT => '0', DI(3) => \rgb888[8]_21\(2), DI(2) => \rgb888[8]_21\(2), DI(1) => \rgb888[8]_21\(2), DI(0) => \y_int[23]_i_76_n_0\, O(3 downto 0) => \NLW_y_int_reg[23]_i_51_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_77_n_0\, S(2) => \y_int[23]_i_78_n_0\, S(1) => \y_int[23]_i_79_n_0\, S(0) => \y_int[23]_i_80_n_0\ ); \y_int_reg[23]_i_66\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[23]_i_66_n_0\, CO(2) => \y_int_reg[23]_i_66_n_1\, CO(1) => \y_int_reg[23]_i_66_n_2\, CO(0) => \y_int_reg[23]_i_66_n_3\, CYINIT => '1', DI(3) => \y_int[23]_i_81_n_0\, DI(2) => \y_int[23]_i_82_n_0\, DI(1) => \y_int[23]_i_83_n_0\, DI(0) => \y_int[23]_i_84_n_0\, O(3 downto 0) => \NLW_y_int_reg[23]_i_66_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_85_n_0\, S(2) => \y_int[23]_i_86_n_0\, S(1) => \y_int[23]_i_87_n_0\, S(0) => \y_int[23]_i_88_n_0\ ); \y_int_reg[23]_i_75\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_89_n_0\, CO(3) => \y_int_reg[23]_i_75_n_0\, CO(2) => \y_int_reg[23]_i_75_n_1\, CO(1) => \y_int_reg[23]_i_75_n_2\, CO(0) => \y_int_reg[23]_i_75_n_3\, CYINIT => '0', DI(3) => \y_int[23]_i_90_n_0\, DI(2) => \y_int[23]_i_91_n_0\, DI(1) => \y_int[23]_i_92_n_0\, DI(0) => \y_int[23]_i_93_n_0\, O(3 downto 0) => \NLW_y_int_reg[23]_i_75_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_94_n_0\, S(2) => \y_int[23]_i_95_n_0\, S(1) => \y_int[23]_i_96_n_0\, S(0) => \y_int[23]_i_97_n_0\ ); \y_int_reg[23]_i_89\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[23]_i_89_n_0\, CO(2) => \y_int_reg[23]_i_89_n_1\, CO(1) => \y_int_reg[23]_i_89_n_2\, CO(0) => \y_int_reg[23]_i_89_n_3\, CYINIT => '1', DI(3) => \y_int[23]_i_98_n_0\, DI(2) => \y_int[23]_i_99_n_0\, DI(1) => \y_int[23]_i_100_n_0\, DI(0) => rgb888(8), O(3 downto 0) => \NLW_y_int_reg[23]_i_89_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[23]_i_101_n_0\, S(2) => \y_int[23]_i_102_n_0\, S(1) => \y_int[23]_i_103_n_0\, S(0) => \y_int[23]_i_104_n_0\ ); \y_int_reg[24]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[27]_i_1_n_7\, Q => \y_int_reg__0\(24), R => '0' ); \y_int_reg[25]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[27]_i_1_n_6\, Q => \y_int_reg__0\(25), R => '0' ); \y_int_reg[26]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[27]_i_1_n_5\, Q => \y_int_reg__0\(26), R => '0' ); \y_int_reg[27]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[27]_i_1_n_4\, Q => \y_int_reg__0\(27), R => '0' ); \y_int_reg[27]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_1_n_0\, CO(3) => \y_int_reg[27]_i_1_n_0\, CO(2) => \y_int_reg[27]_i_1_n_1\, CO(1) => \y_int_reg[27]_i_1_n_2\, CO(0) => \y_int_reg[27]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_2_n_0\, DI(2) => \y_int[31]_i_2_n_0\, DI(1) => \y_int[31]_i_2_n_0\, DI(0) => \y_int[31]_i_2_n_0\, O(3) => \y_int_reg[27]_i_1_n_4\, O(2) => \y_int_reg[27]_i_1_n_5\, O(1) => \y_int_reg[27]_i_1_n_6\, O(0) => \y_int_reg[27]_i_1_n_7\, S(3) => \y_int[27]_i_2_n_0\, S(2) => \y_int[27]_i_3_n_0\, S(1) => \y_int[27]_i_4_n_0\, S(0) => \y_int[27]_i_5_n_0\ ); \y_int_reg[28]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[31]_i_1_n_7\, Q => \y_int_reg__0\(28), R => '0' ); \y_int_reg[29]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[31]_i_1_n_6\, Q => \y_int_reg__0\(29), R => '0' ); \y_int_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[3]_i_1_n_5\, Q => \y_int_reg_n_0_[2]\, R => '0' ); \y_int_reg[30]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[31]_i_1_n_5\, Q => \y_int_reg__0\(30), R => '0' ); \y_int_reg[31]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[31]_i_1_n_4\, Q => \y_int_reg__0\(31), R => '0' ); \y_int_reg[31]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[27]_i_1_n_0\, CO(3) => \NLW_y_int_reg[31]_i_1_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_1_n_1\, CO(1) => \y_int_reg[31]_i_1_n_2\, CO(0) => \y_int_reg[31]_i_1_n_3\, CYINIT => '0', DI(3) => '0', DI(2) => \y_int[31]_i_2_n_0\, DI(1) => \y_int[31]_i_2_n_0\, DI(0) => \y_int[31]_i_2_n_0\, O(3) => \y_int_reg[31]_i_1_n_4\, O(2) => \y_int_reg[31]_i_1_n_5\, O(1) => \y_int_reg[31]_i_1_n_6\, O(0) => \y_int_reg[31]_i_1_n_7\, S(3) => \y_int[31]_i_3_n_0\, S(2) => \y_int[31]_i_4_n_0\, S(1) => \y_int[31]_i_5_n_0\, S(0) => \y_int[31]_i_6_n_0\ ); \y_int_reg[31]_i_11\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_30_n_0\, CO(3) => \NLW_y_int_reg[31]_i_11_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_11_n_1\, CO(1) => \y_int_reg[31]_i_11_n_2\, CO(0) => \y_int_reg[31]_i_11_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \rgb888[0]_9\(1), DI(0) => \y_int[31]_i_32_n_0\, O(3) => \^y_int_reg[23]_0\(0), O(2) => \y_int_reg[31]_i_11_n_5\, O(1) => \y_int_reg[31]_i_11_n_6\, O(0) => \y_int_reg[31]_i_11_n_7\, S(3) => \y_int[31]_i_33_n_0\, S(2) => \y_int[31]_i_34_n_0\, S(1) => \y_int[31]_i_35_n_0\, S(0) => \y_int[31]_i_36_n_0\ ); \y_int_reg[31]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_16_n_0\, CO(3) => \y_int_reg[31]_i_16_n_0\, CO(2) => \y_int_reg[31]_i_16_n_1\, CO(1) => \y_int_reg[31]_i_16_n_2\, CO(0) => \y_int_reg[31]_i_16_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_40_n_0\, DI(2) => \y_int[31]_i_41_n_0\, DI(1) => \y_int[31]_i_42_n_0\, DI(0) => \y_int[31]_i_43_n_0\, O(3) => \y_int_reg[31]_i_16_n_4\, O(2) => \y_int_reg[31]_i_16_n_5\, O(1) => \y_int_reg[31]_i_16_n_6\, O(0) => \y_int_reg[31]_i_16_n_7\, S(3) => \y_int[31]_i_44_n_0\, S(2) => \y_int[31]_i_45_n_0\, S(1) => \y_int[31]_i_46_n_0\, S(0) => \y_int[31]_i_47_n_0\ ); \y_int_reg[31]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_62_n_0\, CO(3) => \y_int_reg[31]_i_30_n_0\, CO(2) => \y_int_reg[31]_i_30_n_1\, CO(1) => \y_int_reg[31]_i_30_n_2\, CO(0) => \y_int_reg[31]_i_30_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_63_n_0\, DI(2) => \y_int[31]_i_64_n_0\, DI(1) => \y_int[31]_i_65_n_0\, DI(0) => \y_int[31]_i_66_n_0\, O(3) => \y_int_reg[31]_i_30_n_4\, O(2) => \y_int_reg[31]_i_30_n_5\, O(1) => \y_int_reg[31]_i_30_n_6\, O(0) => \y_int_reg[31]_i_30_n_7\, S(3) => \y_int[31]_i_67_n_0\, S(2) => \y_int[31]_i_68_n_0\, S(1) => \y_int[31]_i_69_n_0\, S(0) => \y_int[31]_i_70_n_0\ ); \y_int_reg[31]_i_62\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[31]_i_62_n_0\, CO(2) => \y_int_reg[31]_i_62_n_1\, CO(1) => \y_int_reg[31]_i_62_n_2\, CO(0) => \y_int_reg[31]_i_62_n_3\, CYINIT => '0', DI(3) => \y_int_reg[31]_i_86_n_5\, DI(2) => \y_int_reg[31]_i_87_n_7\, DI(1) => \y_int_reg[31]_i_88_n_4\, DI(0) => \y_int_reg[31]_i_88_n_5\, O(3) => \y_int_reg[31]_i_62_n_4\, O(2) => \y_int_reg[31]_i_62_n_5\, O(1) => \y_int_reg[31]_i_62_n_6\, O(0) => \NLW_y_int_reg[31]_i_62_O_UNCONNECTED\(0), S(3) => \y_int[31]_i_89_n_0\, S(2) => \y_int[31]_i_90_n_0\, S(1) => \y_int[31]_i_91_n_0\, S(0) => \y_int[31]_i_92_n_0\ ); \y_int_reg[31]_i_7\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_17_n_0\, CO(3) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_7_n_1\, CO(1) => \NLW_y_int_reg[31]_i_7_CO_UNCONNECTED\(1), CO(0) => \y_int_reg[31]_i_7_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[31]_i_7_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => y_int_reg3(22 downto 21), S(3 downto 2) => B"01", S(1) => \y_int[31]_i_14_n_0\, S(0) => \y_int[31]_i_15_n_0\ ); \y_int_reg[31]_i_75\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_87_n_0\, CO(3 downto 2) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[31]_i_75_n_2\, CO(0) => \NLW_y_int_reg[31]_i_75_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(7), O(3 downto 1) => \NLW_y_int_reg[31]_i_75_O_UNCONNECTED\(3 downto 1), O(0) => \y_int_reg[31]_i_75_n_7\, S(3 downto 1) => B"001", S(0) => \y_int[31]_i_101_n_0\ ); \y_int_reg[31]_i_8\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_16_n_0\, CO(3 downto 2) => \NLW_y_int_reg[31]_i_8_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[31]_i_8_n_2\, CO(0) => \y_int_reg[31]_i_8_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \y_int[31]_i_17_n_0\, O(3) => \NLW_y_int_reg[31]_i_8_O_UNCONNECTED\(3), O(2) => \y_int_reg[31]_i_8_n_5\, O(1) => \y_int_reg[31]_i_8_n_6\, O(0) => \y_int_reg[31]_i_8_n_7\, S(3) => '0', S(2) => \y_int[31]_i_18_n_0\, S(1) => \y_int[31]_i_19_n_0\, S(0) => \y_int[31]_i_20_n_0\ ); \y_int_reg[31]_i_86\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[23]_3\(0), CO(2) => \y_int_reg[31]_i_86_n_1\, CO(1) => \y_int_reg[31]_i_86_n_2\, CO(0) => \y_int_reg[31]_i_86_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_104_n_0\, DI(2) => rgb888(2), DI(1 downto 0) => B"01", O(3) => \y_int_reg[31]_i_86_n_4\, O(2) => \y_int_reg[31]_i_86_n_5\, O(1) => \y_int_reg[31]_i_86_n_6\, O(0) => \NLW_y_int_reg[31]_i_86_O_UNCONNECTED\(0), S(3) => \y_int[31]_i_105_n_0\, S(2) => \y_int[31]_i_106_n_0\, S(1) => \y_int[31]_i_107_n_0\, S(0) => \y_int[31]_i_108_n_0\ ); \y_int_reg[31]_i_87\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_88_n_0\, CO(3) => \y_int_reg[31]_i_87_n_0\, CO(2) => \y_int_reg[31]_i_87_n_1\, CO(1) => \y_int_reg[31]_i_87_n_2\, CO(0) => \y_int_reg[31]_i_87_n_3\, CYINIT => '0', DI(3) => rgb888(6), DI(2 downto 0) => rgb888(7 downto 5), O(3) => \y_int_reg[31]_i_87_n_4\, O(2) => \y_int_reg[31]_i_87_n_5\, O(1) => \y_int_reg[31]_i_87_n_6\, O(0) => \y_int_reg[31]_i_87_n_7\, S(3) => \y_int[31]_i_109_n_0\, S(2) => \y_int[31]_i_110_n_0\, S(1) => \y_int[31]_i_111_n_0\, S(0) => \y_int[31]_i_112_n_0\ ); \y_int_reg[31]_i_88\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[31]_i_88_n_0\, CO(2) => \y_int_reg[31]_i_88_n_1\, CO(1) => \y_int_reg[31]_i_88_n_2\, CO(0) => \y_int_reg[31]_i_88_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(4 downto 2), DI(0) => '0', O(3) => \y_int_reg[31]_i_88_n_4\, O(2) => \y_int_reg[31]_i_88_n_5\, O(1) => \y_int_reg[31]_i_88_n_6\, O(0) => \NLW_y_int_reg[31]_i_88_O_UNCONNECTED\(0), S(3) => \y_int[31]_i_113_n_0\, S(2) => \y_int[31]_i_114_n_0\, S(1) => \y_int[31]_i_115_n_0\, S(0) => \y_int[31]_i_116_n_0\ ); \y_int_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[3]_i_1_n_4\, Q => \y_int_reg_n_0_[3]\, R => '0' ); \y_int_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_1_n_0\, CO(2) => \y_int_reg[3]_i_1_n_1\, CO(1) => \y_int_reg[3]_i_1_n_2\, CO(0) => \y_int_reg[3]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[3]_i_2_n_0\, DI(2) => \y_int[3]_i_3_n_0\, DI(1) => \y_int[3]_i_4_n_0\, DI(0) => '0', O(3) => \y_int_reg[3]_i_1_n_4\, O(2) => \y_int_reg[3]_i_1_n_5\, O(1) => \y_int_reg[3]_i_1_n_6\, O(0) => \y_int_reg[3]_i_1_n_7\, S(3) => \y_int[3]_i_5_n_0\, S(2) => \y_int[3]_i_6_n_0\, S(1) => \y_int[3]_i_7_n_0\, S(0) => \y_int[3]_i_8_n_0\ ); \y_int_reg[3]_i_15\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_21_n_0\, CO(3) => \y_int_reg[3]_i_15_n_0\, CO(2) => \y_int_reg[3]_i_15_n_1\, CO(1) => \y_int_reg[3]_i_15_n_2\, CO(0) => \y_int_reg[3]_i_15_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => y_int_reg5(8), O(2 downto 0) => \NLW_y_int_reg[3]_i_15_O_UNCONNECTED\(2 downto 0), S(3) => \y_int[3]_i_22_n_0\, S(2) => \y_int[3]_i_23_n_0\, S(1) => \y_int[3]_i_24_n_0\, S(0) => \y_int[3]_i_25_n_0\ ); \y_int_reg[3]_i_16\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_26_n_0\, CO(3) => \y_int_reg[3]_i_16_n_0\, CO(2) => \y_int_reg[3]_i_16_n_1\, CO(1) => \y_int_reg[3]_i_16_n_2\, CO(0) => \y_int_reg[3]_i_16_n_3\, CYINIT => '0', DI(3) => \y_int[3]_i_27_n_0\, DI(2) => \y_int[3]_i_28_n_0\, DI(1) => \y_int[3]_i_29_n_0\, DI(0) => \y_int_reg[3]_i_30_n_6\, O(3) => \y_int_reg[3]_i_16_n_4\, O(2) => \y_int_reg[3]_i_16_n_5\, O(1) => \y_int_reg[3]_i_16_n_6\, O(0) => \y_int_reg[3]_i_16_n_7\, S(3) => \y_int[3]_i_31_n_0\, S(2) => \y_int[3]_i_32_n_0\, S(1) => \y_int[3]_i_33_n_0\, S(0) => \y_int[3]_i_34_n_0\ ); \y_int_reg[3]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_21_n_0\, CO(2) => \y_int_reg[3]_i_21_n_1\, CO(1) => \y_int_reg[3]_i_21_n_2\, CO(0) => \y_int_reg[3]_i_21_n_3\, CYINIT => \y_int[3]_i_50_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_y_int_reg[3]_i_21_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[3]_i_51_n_0\, S(2) => \y_int[3]_i_52_n_0\, S(1) => \y_int[3]_i_53_n_0\, S(0) => \y_int[3]_i_54_n_0\ ); \y_int_reg[3]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_26_n_0\, CO(2) => \y_int_reg[3]_i_26_n_1\, CO(1) => \y_int_reg[3]_i_26_n_2\, CO(0) => \y_int_reg[3]_i_26_n_3\, CYINIT => '0', DI(3) => \y_int_reg[3]_i_30_n_7\, DI(2) => \y_int_reg[3]_i_55_n_4\, DI(1) => \y_int_reg[3]_i_55_n_5\, DI(0) => '0', O(3) => \y_int_reg[3]_i_26_n_4\, O(2) => \y_int_reg[3]_i_26_n_5\, O(1) => \y_int_reg[3]_i_26_n_6\, O(0) => \y_int_reg[3]_i_26_n_7\, S(3) => \y_int[3]_i_56_n_0\, S(2) => \y_int[3]_i_57_n_0\, S(1) => \y_int[3]_i_58_n_0\, S(0) => \y_int[3]_i_59_n_0\ ); \y_int_reg[3]_i_30\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_55_n_0\, CO(3) => \y_int_reg[3]_i_30_n_0\, CO(2) => \y_int_reg[3]_i_30_n_1\, CO(1) => \y_int_reg[3]_i_30_n_2\, CO(0) => \y_int_reg[3]_i_30_n_3\, CYINIT => '0', DI(3) => rgb888(22), DI(2 downto 0) => rgb888(23 downto 21), O(3) => \y_int_reg[3]_i_30_n_4\, O(2) => \y_int_reg[3]_i_30_n_5\, O(1) => \y_int_reg[3]_i_30_n_6\, O(0) => \y_int_reg[3]_i_30_n_7\, S(3) => \y_int[3]_i_60_n_0\, S(2) => \y_int[3]_i_61_n_0\, S(1) => \y_int[3]_i_62_n_0\, S(0) => \y_int[3]_i_63_n_0\ ); \y_int_reg[3]_i_35\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_65_n_0\, CO(3) => \y_int_reg[3]_i_35_n_0\, CO(2) => \y_int_reg[3]_i_35_n_1\, CO(1) => \y_int_reg[3]_i_35_n_2\, CO(0) => \y_int_reg[3]_i_35_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[3]_i_35_n_4\, O(2 downto 0) => \NLW_y_int_reg[3]_i_35_O_UNCONNECTED\(2 downto 0), S(3) => \y_int[3]_i_66_n_0\, S(2) => \y_int[3]_i_67_n_0\, S(1) => \y_int[3]_i_68_n_0\, S(0) => \y_int[3]_i_69_n_0\ ); \y_int_reg[3]_i_36\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_2\(0), CO(2) => \y_int_reg[3]_i_36_n_1\, CO(1) => \y_int_reg[3]_i_36_n_2\, CO(0) => \y_int_reg[3]_i_36_n_3\, CYINIT => '0', DI(3 downto 2) => \rgb888[8]_32\(1 downto 0), DI(1) => \rgb888[8]_19\(2), DI(0) => '0', O(3 downto 0) => \^y_int_reg[3]_0\(3 downto 0), S(3) => \y_int[3]_i_71_n_0\, S(2) => \y_int[3]_i_72_n_0\, S(1) => \y_int[3]_i_73_n_0\, S(0) => \y_int[3]_i_74_n_0\ ); \y_int_reg[3]_i_55\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_55_n_0\, CO(2) => \y_int_reg[3]_i_55_n_1\, CO(1) => \y_int_reg[3]_i_55_n_2\, CO(0) => \y_int_reg[3]_i_55_n_3\, CYINIT => '0', DI(3 downto 1) => rgb888(20 downto 18), DI(0) => '0', O(3) => \y_int_reg[3]_i_55_n_4\, O(2) => \y_int_reg[3]_i_55_n_5\, O(1) => \y_int_reg[3]_i_55_n_6\, O(0) => \NLW_y_int_reg[3]_i_55_O_UNCONNECTED\(0), S(3) => \y_int[3]_i_84_n_0\, S(2) => \y_int[3]_i_85_n_0\, S(1) => \y_int[3]_i_86_n_0\, S(0) => \y_int[3]_i_87_n_0\ ); \y_int_reg[3]_i_64\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_30_n_0\, CO(3 downto 2) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[3]_i_64_n_2\, CO(0) => \NLW_y_int_reg[3]_i_64_CO_UNCONNECTED\(0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => rgb888(23), O(3 downto 1) => \NLW_y_int_reg[3]_i_64_O_UNCONNECTED\(3 downto 1), O(0) => \y_int_reg[3]_i_64_n_7\, S(3 downto 1) => B"001", S(0) => \y_int[3]_i_88_n_0\ ); \y_int_reg[3]_i_65\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_65_n_0\, CO(2) => \y_int_reg[3]_i_65_n_1\, CO(1) => \y_int_reg[3]_i_65_n_2\, CO(0) => \y_int_reg[3]_i_65_n_3\, CYINIT => \cr_int[3]_i_80_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_y_int_reg[3]_i_65_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[3]_i_89_n_0\, S(2) => \y_int[3]_i_90_n_0\, S(1) => \y_int[3]_i_91_n_0\, S(0) => \y_int[3]_i_92_n_0\ ); \y_int_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[7]_i_1_n_7\, Q => \y_int_reg_n_0_[4]\, R => '0' ); \y_int_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[7]_i_1_n_6\, Q => \y_int_reg_n_0_[5]\, R => '0' ); \y_int_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[7]_i_1_n_5\, Q => \y_int_reg_n_0_[6]\, R => '0' ); \y_int_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[7]_i_1_n_4\, Q => \y_int_reg_n_0_[7]\, R => '0' ); \y_int_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_1_n_0\, CO(3) => \y_int_reg[7]_i_1_n_0\, CO(2) => \y_int_reg[7]_i_1_n_1\, CO(1) => \y_int_reg[7]_i_1_n_2\, CO(0) => \y_int_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \y_int[7]_i_2_n_0\, DI(2) => \y_int[7]_i_3_n_0\, DI(1) => \y_int[7]_i_4_n_0\, DI(0) => \y_int[7]_i_5_n_0\, O(3) => \y_int_reg[7]_i_1_n_4\, O(2) => \y_int_reg[7]_i_1_n_5\, O(1) => \y_int_reg[7]_i_1_n_6\, O(0) => \y_int_reg[7]_i_1_n_7\, S(3) => \y_int[7]_i_6_n_0\, S(2) => \y_int[7]_i_7_n_0\, S(1) => \y_int[7]_i_8_n_0\, S(0) => \y_int[7]_i_9_n_0\ ); \y_int_reg[7]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[7]_i_24_n_0\, CO(2) => \y_int_reg[7]_i_24_n_1\, CO(1) => \y_int_reg[7]_i_24_n_2\, CO(0) => \y_int_reg[7]_i_24_n_3\, CYINIT => \y_int[7]_i_29_n_0\, DI(3 downto 0) => B"0000", O(3) => \y_int_reg[7]_i_24_n_4\, O(2) => \y_int_reg[7]_i_24_n_5\, O(1) => \y_int_reg[7]_i_24_n_6\, O(0) => \y_int_reg[7]_i_24_n_7\, S(3) => \y_int[7]_i_30_n_0\, S(2) => \y_int[7]_i_31_n_0\, S(1) => \y_int[7]_i_32_n_0\, S(0) => \y_int[7]_i_33_n_0\ ); \y_int_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[11]_i_1_n_7\, Q => \y_int_reg__0\(8), R => '0' ); \y_int_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \y_int_reg[11]_i_1_n_6\, Q => \y_int_reg__0\(9), R => '0' ); \y_reg[0]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[0]_i_1_n_0\, Q => y(0), S => \y_reg[7]_i_1_n_0\ ); \y_reg[1]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[1]_i_1_n_0\, Q => y(1), S => \y_reg[7]_i_1_n_0\ ); \y_reg[2]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[2]_i_1_n_0\, Q => y(2), S => \y_reg[7]_i_1_n_0\ ); \y_reg[3]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[3]_i_1_n_0\, Q => y(3), S => \y_reg[7]_i_1_n_0\ ); \y_reg[4]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[4]_i_1_n_0\, Q => y(4), S => \y_reg[7]_i_1_n_0\ ); \y_reg[5]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[5]_i_1_n_0\, Q => y(5), S => \y_reg[7]_i_1_n_0\ ); \y_reg[6]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[6]_i_1_n_0\, Q => y(6), S => \y_reg[7]_i_1_n_0\ ); \y_reg[7]\: unisim.vcomponents.FDSE port map ( C => cb_regn_0_0, CE => '1', D => \y[7]_i_2_n_0\, Q => y(7), S => \y_reg[7]_i_1_n_0\ ); \y_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \y_reg[7]_i_3_n_0\, CO(3) => \y_reg[7]_i_1_n_0\, CO(2) => \y_reg[7]_i_1_n_1\, CO(1) => \y_reg[7]_i_1_n_2\, CO(0) => \y_reg[7]_i_1_n_3\, CYINIT => '0', DI(3) => \y[7]_i_4_n_0\, DI(2) => \y[7]_i_5_n_0\, DI(1) => \y[7]_i_6_n_0\, DI(0) => \y[7]_i_7_n_0\, O(3 downto 0) => \NLW_y_reg[7]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \y[7]_i_8_n_0\, S(2) => \y[7]_i_9_n_0\, S(1) => \y[7]_i_10_n_0\, S(0) => \y[7]_i_11_n_0\ ); \y_reg[7]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_reg[7]_i_12_n_0\, CO(2) => \y_reg[7]_i_12_n_1\, CO(1) => \y_reg[7]_i_12_n_2\, CO(0) => \y_reg[7]_i_12_n_3\, CYINIT => '0', DI(3) => \y[7]_i_21_n_0\, DI(2) => \y[7]_i_22_n_0\, DI(1) => \y[7]_i_23_n_0\, DI(0) => \y[7]_i_24_n_0\, O(3 downto 0) => \NLW_y_reg[7]_i_12_O_UNCONNECTED\(3 downto 0), S(3) => \y[7]_i_25_n_0\, S(2) => \y[7]_i_26_n_0\, S(1) => \y[7]_i_27_n_0\, S(0) => \y[7]_i_28_n_0\ ); \y_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \y_reg[7]_i_12_n_0\, CO(3) => \y_reg[7]_i_3_n_0\, CO(2) => \y_reg[7]_i_3_n_1\, CO(1) => \y_reg[7]_i_3_n_2\, CO(0) => \y_reg[7]_i_3_n_3\, CYINIT => '0', DI(3) => \y[7]_i_13_n_0\, DI(2) => \y[7]_i_14_n_0\, DI(1) => \y[7]_i_15_n_0\, DI(0) => \y[7]_i_16_n_0\, O(3 downto 0) => \NLW_y_reg[7]_i_3_O_UNCONNECTED\(3 downto 0), S(3) => \y[7]_i_17_n_0\, S(2) => \y[7]_i_18_n_0\, S(1) => \y[7]_i_19_n_0\, S(0) => \y[7]_i_20_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_zed_hdmi_0_0 is port ( clk : in STD_LOGIC; clk_x2 : in STD_LOGIC; clk_100 : in STD_LOGIC; active : in STD_LOGIC; hsync : in STD_LOGIC; vsync : in STD_LOGIC; rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 ); hdmi_clk : out STD_LOGIC; hdmi_hsync : out STD_LOGIC; hdmi_vsync : out STD_LOGIC; hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 ); hdmi_de : out STD_LOGIC; hdmi_scl : out STD_LOGIC; hdmi_sda : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_zed_hdmi_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_zed_hdmi_0_0 : entity is "system_zed_hdmi_0_0,zed_hdmi,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_zed_hdmi_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_zed_hdmi_0_0 : entity is "zed_hdmi,Vivado 2016.4"; end system_zed_hdmi_0_0; architecture STRUCTURE of system_zed_hdmi_0_0 is signal \<const0>\ : STD_LOGIC; signal U0_n_10 : STD_LOGIC; signal U0_n_11 : STD_LOGIC; signal U0_n_12 : STD_LOGIC; signal U0_n_13 : STD_LOGIC; signal U0_n_14 : STD_LOGIC; signal U0_n_15 : STD_LOGIC; signal U0_n_16 : STD_LOGIC; signal U0_n_17 : STD_LOGIC; signal U0_n_18 : STD_LOGIC; signal U0_n_19 : STD_LOGIC; signal U0_n_20 : STD_LOGIC; signal U0_n_21 : STD_LOGIC; signal U0_n_22 : STD_LOGIC; signal U0_n_23 : STD_LOGIC; signal U0_n_24 : STD_LOGIC; signal U0_n_25 : STD_LOGIC; signal U0_n_26 : STD_LOGIC; signal U0_n_27 : STD_LOGIC; signal U0_n_28 : STD_LOGIC; signal U0_n_29 : STD_LOGIC; signal U0_n_30 : STD_LOGIC; signal U0_n_31 : STD_LOGIC; signal U0_n_32 : STD_LOGIC; signal U0_n_33 : STD_LOGIC; signal U0_n_34 : STD_LOGIC; signal U0_n_35 : STD_LOGIC; signal U0_n_36 : STD_LOGIC; signal U0_n_37 : STD_LOGIC; signal U0_n_38 : STD_LOGIC; signal U0_n_39 : STD_LOGIC; signal U0_n_4 : STD_LOGIC; signal U0_n_40 : STD_LOGIC; signal U0_n_41 : STD_LOGIC; signal U0_n_42 : STD_LOGIC; signal U0_n_43 : STD_LOGIC; signal U0_n_44 : STD_LOGIC; signal U0_n_45 : STD_LOGIC; signal U0_n_46 : STD_LOGIC; signal U0_n_47 : STD_LOGIC; signal U0_n_48 : STD_LOGIC; signal U0_n_49 : STD_LOGIC; signal U0_n_5 : STD_LOGIC; signal U0_n_50 : STD_LOGIC; signal U0_n_51 : STD_LOGIC; signal U0_n_52 : STD_LOGIC; signal U0_n_53 : STD_LOGIC; signal U0_n_54 : STD_LOGIC; signal U0_n_55 : STD_LOGIC; signal U0_n_56 : STD_LOGIC; signal U0_n_57 : STD_LOGIC; signal U0_n_58 : STD_LOGIC; signal U0_n_59 : STD_LOGIC; signal U0_n_6 : STD_LOGIC; signal U0_n_60 : STD_LOGIC; signal U0_n_61 : STD_LOGIC; signal U0_n_62 : STD_LOGIC; signal U0_n_63 : STD_LOGIC; signal U0_n_64 : STD_LOGIC; signal U0_n_65 : STD_LOGIC; signal U0_n_66 : STD_LOGIC; signal U0_n_67 : STD_LOGIC; signal U0_n_68 : STD_LOGIC; signal U0_n_69 : STD_LOGIC; signal U0_n_7 : STD_LOGIC; signal U0_n_70 : STD_LOGIC; signal U0_n_71 : STD_LOGIC; signal U0_n_72 : STD_LOGIC; signal U0_n_73 : STD_LOGIC; signal U0_n_74 : STD_LOGIC; signal U0_n_75 : STD_LOGIC; signal U0_n_76 : STD_LOGIC; signal U0_n_77 : STD_LOGIC; signal U0_n_78 : STD_LOGIC; signal U0_n_79 : STD_LOGIC; signal U0_n_8 : STD_LOGIC; signal U0_n_80 : STD_LOGIC; signal U0_n_81 : STD_LOGIC; signal U0_n_9 : STD_LOGIC; signal \cb_int[15]_i_35_n_0\ : STD_LOGIC; signal \cb_int[15]_i_36_n_0\ : STD_LOGIC; signal \cb_int[15]_i_37_n_0\ : STD_LOGIC; signal \cb_int[15]_i_38_n_0\ : STD_LOGIC; signal \cb_int[15]_i_39_n_0\ : STD_LOGIC; signal \cb_int[15]_i_40_n_0\ : STD_LOGIC; signal \cb_int[15]_i_41_n_0\ : STD_LOGIC; signal \cb_int[15]_i_42_n_0\ : STD_LOGIC; signal \cb_int[15]_i_47_n_0\ : STD_LOGIC; signal \cb_int[15]_i_48_n_0\ : STD_LOGIC; signal \cb_int[15]_i_49_n_0\ : STD_LOGIC; signal \cb_int[15]_i_50_n_0\ : STD_LOGIC; signal \cb_int[19]_i_38_n_0\ : STD_LOGIC; signal \cb_int[19]_i_39_n_0\ : STD_LOGIC; signal \cb_int[19]_i_40_n_0\ : STD_LOGIC; signal \cb_int[19]_i_41_n_0\ : STD_LOGIC; signal \cb_int[19]_i_42_n_0\ : STD_LOGIC; signal \cb_int[19]_i_43_n_0\ : STD_LOGIC; signal \cb_int[19]_i_44_n_0\ : STD_LOGIC; signal \cb_int[19]_i_45_n_0\ : STD_LOGIC; signal \cb_int[23]_i_33_n_0\ : STD_LOGIC; signal \cb_int[23]_i_34_n_0\ : STD_LOGIC; signal \cb_int[23]_i_35_n_0\ : STD_LOGIC; signal \cb_int[23]_i_36_n_0\ : STD_LOGIC; signal \cb_int[23]_i_37_n_0\ : STD_LOGIC; signal \cb_int[23]_i_38_n_0\ : STD_LOGIC; signal \cb_int[23]_i_39_n_0\ : STD_LOGIC; signal \cb_int[23]_i_40_n_0\ : STD_LOGIC; signal \cb_int[31]_i_100_n_0\ : STD_LOGIC; signal \cb_int[31]_i_101_n_0\ : STD_LOGIC; signal \cb_int[31]_i_18_n_0\ : STD_LOGIC; signal \cb_int[31]_i_19_n_0\ : STD_LOGIC; signal \cb_int[31]_i_20_n_0\ : STD_LOGIC; signal \cb_int[31]_i_21_n_0\ : STD_LOGIC; signal \cb_int[31]_i_22_n_0\ : STD_LOGIC; signal \cb_int[31]_i_25_n_0\ : STD_LOGIC; signal \cb_int[31]_i_26_n_0\ : STD_LOGIC; signal \cb_int[31]_i_28_n_0\ : STD_LOGIC; signal \cb_int[31]_i_29_n_0\ : STD_LOGIC; signal \cb_int[31]_i_45_n_0\ : STD_LOGIC; signal \cb_int[31]_i_46_n_0\ : STD_LOGIC; signal \cb_int[31]_i_47_n_0\ : STD_LOGIC; signal \cb_int[31]_i_48_n_0\ : STD_LOGIC; signal \cb_int[31]_i_49_n_0\ : STD_LOGIC; signal \cb_int[31]_i_50_n_0\ : STD_LOGIC; signal \cb_int[31]_i_52_n_0\ : STD_LOGIC; signal \cb_int[31]_i_53_n_0\ : STD_LOGIC; signal \cb_int[31]_i_54_n_0\ : STD_LOGIC; signal \cb_int[31]_i_55_n_0\ : STD_LOGIC; signal \cb_int[31]_i_56_n_0\ : STD_LOGIC; signal \cb_int[31]_i_57_n_0\ : STD_LOGIC; signal \cb_int[31]_i_58_n_0\ : STD_LOGIC; signal \cb_int[31]_i_59_n_0\ : STD_LOGIC; signal \cb_int[31]_i_60_n_0\ : STD_LOGIC; signal \cb_int[31]_i_62_n_0\ : STD_LOGIC; signal \cb_int[31]_i_63_n_0\ : STD_LOGIC; signal \cb_int[31]_i_64_n_0\ : STD_LOGIC; signal \cb_int[31]_i_65_n_0\ : STD_LOGIC; signal \cb_int[31]_i_83_n_0\ : STD_LOGIC; signal \cb_int[31]_i_84_n_0\ : STD_LOGIC; signal \cb_int[31]_i_88_n_0\ : STD_LOGIC; signal \cb_int[31]_i_89_n_0\ : STD_LOGIC; signal \cb_int[31]_i_90_n_0\ : STD_LOGIC; signal \cb_int[31]_i_91_n_0\ : STD_LOGIC; signal \cb_int[31]_i_92_n_0\ : STD_LOGIC; signal \cb_int[31]_i_93_n_0\ : STD_LOGIC; signal \cb_int[31]_i_94_n_0\ : STD_LOGIC; signal \cb_int[31]_i_99_n_0\ : STD_LOGIC; signal \cb_int[3]_i_35_n_0\ : STD_LOGIC; signal \cb_int[3]_i_36_n_0\ : STD_LOGIC; signal \cb_int[3]_i_37_n_0\ : STD_LOGIC; signal \cb_int[3]_i_38_n_0\ : STD_LOGIC; signal \cb_int[3]_i_39_n_0\ : STD_LOGIC; signal \cb_int[3]_i_40_n_0\ : STD_LOGIC; signal \cb_int[3]_i_41_n_0\ : STD_LOGIC; signal \cb_int[3]_i_42_n_0\ : STD_LOGIC; signal \cb_int[3]_i_59_n_0\ : STD_LOGIC; signal \cb_int[3]_i_60_n_0\ : STD_LOGIC; signal \cb_int[3]_i_61_n_0\ : STD_LOGIC; signal \cb_int[3]_i_62_n_0\ : STD_LOGIC; signal \cb_int[3]_i_73_n_0\ : STD_LOGIC; signal \cb_int[3]_i_74_n_0\ : STD_LOGIC; signal \cb_int[3]_i_84_n_0\ : STD_LOGIC; signal \cb_int[3]_i_85_n_0\ : STD_LOGIC; signal \cb_int[3]_i_86_n_0\ : STD_LOGIC; signal \cb_int[3]_i_87_n_0\ : STD_LOGIC; signal \cb_int[3]_i_88_n_0\ : STD_LOGIC; signal \cb_int[3]_i_95_n_0\ : STD_LOGIC; signal \cb_int[3]_i_96_n_0\ : STD_LOGIC; signal \cb_int[3]_i_97_n_0\ : STD_LOGIC; signal \cb_int[3]_i_98_n_0\ : STD_LOGIC; signal \cb_int[7]_i_30_n_0\ : STD_LOGIC; signal \cb_int[7]_i_31_n_0\ : STD_LOGIC; signal \cb_int[7]_i_32_n_0\ : STD_LOGIC; signal \cb_int[7]_i_33_n_0\ : STD_LOGIC; signal \cb_int[7]_i_34_n_0\ : STD_LOGIC; signal \cb_int[7]_i_35_n_0\ : STD_LOGIC; signal \cb_int[7]_i_36_n_0\ : STD_LOGIC; signal \cb_int[7]_i_37_n_0\ : STD_LOGIC; signal \cb_int[7]_i_43_n_0\ : STD_LOGIC; signal \cb_int[7]_i_44_n_0\ : STD_LOGIC; signal \cb_int[7]_i_45_n_0\ : STD_LOGIC; signal \cb_int[7]_i_46_n_0\ : STD_LOGIC; signal \cb_int[7]_i_47_n_0\ : STD_LOGIC; signal \cb_int[7]_i_48_n_0\ : STD_LOGIC; signal \cb_int[7]_i_49_n_0\ : STD_LOGIC; signal \cb_int[7]_i_50_n_0\ : STD_LOGIC; signal \cb_int[7]_i_51_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_4\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_5\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_6\ : STD_LOGIC; signal \cb_int_reg[15]_i_31_n_7\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_4\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_5\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_6\ : STD_LOGIC; signal \cb_int_reg[15]_i_32_n_7\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_0\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_1\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_2\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_3\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_4\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_5\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_6\ : STD_LOGIC; signal \cb_int_reg[15]_i_34_n_7\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_4\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_5\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_6\ : STD_LOGIC; signal \cb_int_reg[19]_i_32_n_7\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_0\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_1\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_2\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_3\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_4\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_5\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_6\ : STD_LOGIC; signal \cb_int_reg[19]_i_33_n_7\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_0\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_1\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_2\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_3\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_4\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_5\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_6\ : STD_LOGIC; signal \cb_int_reg[23]_i_27_n_7\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_0\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_1\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_2\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_3\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_4\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_5\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_6\ : STD_LOGIC; signal \cb_int_reg[23]_i_28_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_10_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_10_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_10_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_10_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_17_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_23_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_27_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_42_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_42_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_42_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_61_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_66_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_66_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_66_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_0\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_85_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_1\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_2\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_4\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_5\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_8_n_7\ : STD_LOGIC; signal \cb_int_reg[31]_i_9_n_3\ : STD_LOGIC; signal \cb_int_reg[31]_i_9_n_6\ : STD_LOGIC; signal \cb_int_reg[31]_i_9_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_19_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_32_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_43_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_43_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_43_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_43_n_7\ : STD_LOGIC; signal \cb_int_reg[3]_i_58_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_58_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_58_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_58_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_0\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_1\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_2\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_3\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_4\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_5\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_6\ : STD_LOGIC; signal \cb_int_reg[3]_i_68_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_23_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_24_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_26_n_7\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_0\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_1\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_2\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_3\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_4\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_5\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_6\ : STD_LOGIC; signal \cb_int_reg[7]_i_27_n_7\ : STD_LOGIC; signal \cr_int[11]_i_61_n_0\ : STD_LOGIC; signal \cr_int[11]_i_62_n_0\ : STD_LOGIC; signal \cr_int[11]_i_63_n_0\ : STD_LOGIC; signal \cr_int[11]_i_64_n_0\ : STD_LOGIC; signal \cr_int[15]_i_44_n_0\ : STD_LOGIC; signal \cr_int[15]_i_45_n_0\ : STD_LOGIC; signal \cr_int[15]_i_46_n_0\ : STD_LOGIC; signal \cr_int[15]_i_47_n_0\ : STD_LOGIC; signal \cr_int[15]_i_52_n_0\ : STD_LOGIC; signal \cr_int[15]_i_53_n_0\ : STD_LOGIC; signal \cr_int[15]_i_54_n_0\ : STD_LOGIC; signal \cr_int[15]_i_55_n_0\ : STD_LOGIC; signal \cr_int[19]_i_42_n_0\ : STD_LOGIC; signal \cr_int[19]_i_43_n_0\ : STD_LOGIC; signal \cr_int[19]_i_44_n_0\ : STD_LOGIC; signal \cr_int[19]_i_45_n_0\ : STD_LOGIC; signal \cr_int[23]_i_32_n_0\ : STD_LOGIC; signal \cr_int[23]_i_33_n_0\ : STD_LOGIC; signal \cr_int[23]_i_34_n_0\ : STD_LOGIC; signal \cr_int[23]_i_35_n_0\ : STD_LOGIC; signal \cr_int[31]_i_104_n_0\ : STD_LOGIC; signal \cr_int[31]_i_105_n_0\ : STD_LOGIC; signal \cr_int[31]_i_106_n_0\ : STD_LOGIC; signal \cr_int[31]_i_107_n_0\ : STD_LOGIC; signal \cr_int[31]_i_28_n_0\ : STD_LOGIC; signal \cr_int[31]_i_29_n_0\ : STD_LOGIC; signal \cr_int[31]_i_65_n_0\ : STD_LOGIC; signal \cr_int[31]_i_66_n_0\ : STD_LOGIC; signal \cr_int[31]_i_67_n_0\ : STD_LOGIC; signal \cr_int[31]_i_68_n_0\ : STD_LOGIC; signal \cr_int[31]_i_98_n_0\ : STD_LOGIC; signal \cr_int[31]_i_99_n_0\ : STD_LOGIC; signal \cr_int[7]_i_29_n_0\ : STD_LOGIC; signal \cr_int[7]_i_30_n_0\ : STD_LOGIC; signal \cr_int[7]_i_31_n_0\ : STD_LOGIC; signal \cr_int[7]_i_32_n_0\ : STD_LOGIC; signal \cr_int[7]_i_33_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_0\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_1\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_2\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_3\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_4\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_5\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_6\ : STD_LOGIC; signal \cr_int_reg[11]_i_28_n_7\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_4\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_5\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_6\ : STD_LOGIC; signal \cr_int_reg[15]_i_37_n_7\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_0\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_1\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_2\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_3\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_4\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_5\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_6\ : STD_LOGIC; signal \cr_int_reg[15]_i_39_n_7\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_0\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_1\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_2\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_3\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_4\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_5\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_6\ : STD_LOGIC; signal \cr_int_reg[19]_i_37_n_7\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_0\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_1\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_2\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_3\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_4\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_5\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_6\ : STD_LOGIC; signal \cr_int_reg[23]_i_31_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_10_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_10_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_10_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_10_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_27_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_54_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_54_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_54_n_7\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_0\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_1\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_2\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_3\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_4\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_5\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_6\ : STD_LOGIC; signal \cr_int_reg[31]_i_64_n_7\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_0\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_1\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_2\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_3\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_4\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_5\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_6\ : STD_LOGIC; signal \cr_int_reg[7]_i_24_n_7\ : STD_LOGIC; signal \^hdmi_d\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \y_int[11]_i_54_n_0\ : STD_LOGIC; signal \y_int[11]_i_55_n_0\ : STD_LOGIC; signal \y_int[11]_i_56_n_0\ : STD_LOGIC; signal \y_int[11]_i_57_n_0\ : STD_LOGIC; signal \y_int[15]_i_36_n_0\ : STD_LOGIC; signal \y_int[15]_i_37_n_0\ : STD_LOGIC; signal \y_int[15]_i_38_n_0\ : STD_LOGIC; signal \y_int[15]_i_39_n_0\ : STD_LOGIC; signal \y_int[15]_i_44_n_0\ : STD_LOGIC; signal \y_int[15]_i_45_n_0\ : STD_LOGIC; signal \y_int[15]_i_46_n_0\ : STD_LOGIC; signal \y_int[15]_i_47_n_0\ : STD_LOGIC; signal \y_int[19]_i_36_n_0\ : STD_LOGIC; signal \y_int[19]_i_37_n_0\ : STD_LOGIC; signal \y_int[19]_i_38_n_0\ : STD_LOGIC; signal \y_int[19]_i_39_n_0\ : STD_LOGIC; signal \y_int[19]_i_40_n_0\ : STD_LOGIC; signal \y_int[19]_i_41_n_0\ : STD_LOGIC; signal \y_int[19]_i_42_n_0\ : STD_LOGIC; signal \y_int[19]_i_43_n_0\ : STD_LOGIC; signal \y_int[19]_i_44_n_0\ : STD_LOGIC; signal \y_int[19]_i_45_n_0\ : STD_LOGIC; signal \y_int[19]_i_46_n_0\ : STD_LOGIC; signal \y_int[19]_i_47_n_0\ : STD_LOGIC; signal \y_int[23]_i_50_n_0\ : STD_LOGIC; signal \y_int[23]_i_58_n_0\ : STD_LOGIC; signal \y_int[23]_i_59_n_0\ : STD_LOGIC; signal \y_int[23]_i_60_n_0\ : STD_LOGIC; signal \y_int[23]_i_61_n_0\ : STD_LOGIC; signal \y_int[31]_i_100_n_0\ : STD_LOGIC; signal \y_int[31]_i_102_n_0\ : STD_LOGIC; signal \y_int[31]_i_103_n_0\ : STD_LOGIC; signal \y_int[31]_i_22_n_0\ : STD_LOGIC; signal \y_int[31]_i_23_n_0\ : STD_LOGIC; signal \y_int[31]_i_24_n_0\ : STD_LOGIC; signal \y_int[31]_i_25_n_0\ : STD_LOGIC; signal \y_int[31]_i_26_n_0\ : STD_LOGIC; signal \y_int[31]_i_28_n_0\ : STD_LOGIC; signal \y_int[31]_i_29_n_0\ : STD_LOGIC; signal \y_int[31]_i_38_n_0\ : STD_LOGIC; signal \y_int[31]_i_39_n_0\ : STD_LOGIC; signal \y_int[31]_i_48_n_0\ : STD_LOGIC; signal \y_int[31]_i_49_n_0\ : STD_LOGIC; signal \y_int[31]_i_50_n_0\ : STD_LOGIC; signal \y_int[31]_i_51_n_0\ : STD_LOGIC; signal \y_int[31]_i_52_n_0\ : STD_LOGIC; signal \y_int[31]_i_53_n_0\ : STD_LOGIC; signal \y_int[31]_i_54_n_0\ : STD_LOGIC; signal \y_int[31]_i_55_n_0\ : STD_LOGIC; signal \y_int[31]_i_56_n_0\ : STD_LOGIC; signal \y_int[31]_i_57_n_0\ : STD_LOGIC; signal \y_int[31]_i_58_n_0\ : STD_LOGIC; signal \y_int[31]_i_59_n_0\ : STD_LOGIC; signal \y_int[31]_i_60_n_0\ : STD_LOGIC; signal \y_int[31]_i_61_n_0\ : STD_LOGIC; signal \y_int[31]_i_72_n_0\ : STD_LOGIC; signal \y_int[31]_i_73_n_0\ : STD_LOGIC; signal \y_int[31]_i_74_n_0\ : STD_LOGIC; signal \y_int[31]_i_76_n_0\ : STD_LOGIC; signal \y_int[31]_i_77_n_0\ : STD_LOGIC; signal \y_int[31]_i_78_n_0\ : STD_LOGIC; signal \y_int[31]_i_79_n_0\ : STD_LOGIC; signal \y_int[31]_i_80_n_0\ : STD_LOGIC; signal \y_int[31]_i_81_n_0\ : STD_LOGIC; signal \y_int[31]_i_83_n_0\ : STD_LOGIC; signal \y_int[31]_i_84_n_0\ : STD_LOGIC; signal \y_int[31]_i_85_n_0\ : STD_LOGIC; signal \y_int[31]_i_93_n_0\ : STD_LOGIC; signal \y_int[31]_i_94_n_0\ : STD_LOGIC; signal \y_int[31]_i_95_n_0\ : STD_LOGIC; signal \y_int[31]_i_96_n_0\ : STD_LOGIC; signal \y_int[31]_i_97_n_0\ : STD_LOGIC; signal \y_int[31]_i_98_n_0\ : STD_LOGIC; signal \y_int[31]_i_99_n_0\ : STD_LOGIC; signal \y_int[3]_i_37_n_0\ : STD_LOGIC; signal \y_int[3]_i_38_n_0\ : STD_LOGIC; signal \y_int[3]_i_39_n_0\ : STD_LOGIC; signal \y_int[3]_i_41_n_0\ : STD_LOGIC; signal \y_int[3]_i_42_n_0\ : STD_LOGIC; signal \y_int[3]_i_43_n_0\ : STD_LOGIC; signal \y_int[3]_i_44_n_0\ : STD_LOGIC; signal \y_int[3]_i_46_n_0\ : STD_LOGIC; signal \y_int[3]_i_47_n_0\ : STD_LOGIC; signal \y_int[3]_i_48_n_0\ : STD_LOGIC; signal \y_int[3]_i_49_n_0\ : STD_LOGIC; signal \y_int[3]_i_75_n_0\ : STD_LOGIC; signal \y_int[3]_i_76_n_0\ : STD_LOGIC; signal \y_int[3]_i_77_n_0\ : STD_LOGIC; signal \y_int[3]_i_78_n_0\ : STD_LOGIC; signal \y_int[3]_i_79_n_0\ : STD_LOGIC; signal \y_int[3]_i_80_n_0\ : STD_LOGIC; signal \y_int[3]_i_81_n_0\ : STD_LOGIC; signal \y_int[3]_i_82_n_0\ : STD_LOGIC; signal \y_int[3]_i_83_n_0\ : STD_LOGIC; signal \y_int[3]_i_93_n_0\ : STD_LOGIC; signal \y_int[3]_i_94_n_0\ : STD_LOGIC; signal \y_int[3]_i_95_n_0\ : STD_LOGIC; signal \y_int[3]_i_96_n_0\ : STD_LOGIC; signal \y_int[7]_i_25_n_0\ : STD_LOGIC; signal \y_int[7]_i_26_n_0\ : STD_LOGIC; signal \y_int[7]_i_27_n_0\ : STD_LOGIC; signal \y_int[7]_i_28_n_0\ : STD_LOGIC; signal y_int_reg2 : STD_LOGIC_VECTOR ( 22 downto 9 ); signal \y_int_reg[11]_i_27_n_0\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_1\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_2\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_3\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_4\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_5\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_6\ : STD_LOGIC; signal \y_int_reg[11]_i_27_n_7\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_3\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_4\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_5\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_6\ : STD_LOGIC; signal \y_int_reg[15]_i_24_n_7\ : STD_LOGIC; signal \y_int_reg[15]_i_34_n_0\ : STD_LOGIC; signal \y_int_reg[15]_i_34_n_1\ : STD_LOGIC; signal \y_int_reg[15]_i_34_n_2\ : STD_LOGIC; signal \y_int_reg[15]_i_34_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_4\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_5\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_6\ : STD_LOGIC; signal \y_int_reg[19]_i_24_n_7\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_3\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_4\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_5\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_6\ : STD_LOGIC; signal \y_int_reg[19]_i_33_n_7\ : STD_LOGIC; signal \y_int_reg[19]_i_34_n_0\ : STD_LOGIC; signal \y_int_reg[19]_i_34_n_1\ : STD_LOGIC; signal \y_int_reg[19]_i_34_n_2\ : STD_LOGIC; signal \y_int_reg[19]_i_34_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_32_n_7\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_0\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_1\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_2\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_3\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_4\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_5\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_6\ : STD_LOGIC; signal \y_int_reg[23]_i_35_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_10_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_10_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_10_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_10_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_12_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_12_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_21_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_27_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_31_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_37_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_37_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_37_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_37_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_0\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_4\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_71_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_82_n_1\ : STD_LOGIC; signal \y_int_reg[31]_i_82_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_82_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_82_n_7\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_2\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_3\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_5\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_6\ : STD_LOGIC; signal \y_int_reg[31]_i_9_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_19_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_20_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_6\ : STD_LOGIC; signal \y_int_reg[3]_i_40_n_7\ : STD_LOGIC; signal \y_int_reg[3]_i_45_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_45_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_45_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_45_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_0\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_1\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_2\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_3\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_4\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_5\ : STD_LOGIC; signal \y_int_reg[3]_i_70_n_6\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_0\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_1\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_2\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_3\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_4\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_5\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_6\ : STD_LOGIC; signal \y_int_reg[7]_i_23_n_7\ : STD_LOGIC; signal \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 ); attribute HLUTNM : string; attribute HLUTNM of \cb_int[3]_i_35\ : label is "lutpair0"; attribute HLUTNM of \cb_int[3]_i_40\ : label is "lutpair0"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \y_int[31]_i_57\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \y_int[31]_i_80\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \y_int[31]_i_81\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \y_int[31]_i_84\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \y_int[31]_i_85\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \y_int[3]_i_79\ : label is "soft_lutpair38"; begin hdmi_d(15 downto 8) <= \^hdmi_d\(15 downto 8); hdmi_d(7) <= \<const0>\; hdmi_d(6) <= \<const0>\; hdmi_d(5) <= \<const0>\; hdmi_d(4) <= \<const0>\; hdmi_d(3) <= \<const0>\; hdmi_d(2) <= \<const0>\; hdmi_d(1) <= \<const0>\; hdmi_d(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); U0: entity work.system_zed_hdmi_0_0_zed_hdmi port map ( CO(0) => U0_n_16, DI(0) => U0_n_4, O(1) => U0_n_7, O(0) => U0_n_8, active => active, \cb_int_reg[15]_0\(0) => U0_n_76, \cb_int_reg[27]_0\(0) => U0_n_75, \cb_int_reg[3]_0\(3) => U0_n_9, \cb_int_reg[3]_0\(2) => U0_n_10, \cb_int_reg[3]_0\(1) => U0_n_11, \cb_int_reg[3]_0\(0) => U0_n_12, \cb_int_reg[3]_1\(0) => U0_n_72, \cb_int_reg[3]_2\(0) => U0_n_73, \cb_int_reg[3]_3\(0) => U0_n_74, clk => clk, clk_100 => clk_100, clk_x2 => clk_x2, \cr_int_reg[11]_0\(3) => U0_n_34, \cr_int_reg[11]_0\(2) => U0_n_35, \cr_int_reg[11]_0\(1) => U0_n_36, \cr_int_reg[11]_0\(0) => U0_n_37, \cr_int_reg[15]_0\(3) => U0_n_38, \cr_int_reg[15]_0\(2) => U0_n_39, \cr_int_reg[15]_0\(1) => U0_n_40, \cr_int_reg[15]_0\(0) => U0_n_41, \cr_int_reg[15]_1\(0) => U0_n_77, \cr_int_reg[19]_0\(3) => U0_n_42, \cr_int_reg[19]_0\(2) => U0_n_43, \cr_int_reg[19]_0\(1) => U0_n_44, \cr_int_reg[19]_0\(0) => U0_n_45, \cr_int_reg[23]_0\(3) => U0_n_46, \cr_int_reg[23]_0\(2) => U0_n_47, \cr_int_reg[23]_0\(1) => U0_n_48, \cr_int_reg[23]_0\(0) => U0_n_49, \cr_int_reg[23]_1\(0) => U0_n_50, \cr_int_reg[27]_0\ => U0_n_13, \cr_int_reg[27]_1\(1) => U0_n_14, \cr_int_reg[27]_1\(0) => U0_n_15, \cr_int_reg[27]_2\(0) => U0_n_29, \cr_int_reg[31]_0\ => U0_n_5, \cr_int_reg[31]_1\ => U0_n_6, \cr_int_reg[31]_2\(1) => U0_n_17, \cr_int_reg[31]_2\(0) => U0_n_18, \cr_int_reg[3]_0\(2) => U0_n_23, \cr_int_reg[3]_0\(1) => U0_n_24, \cr_int_reg[3]_0\(0) => U0_n_25, \cr_int_reg[3]_1\(0) => U0_n_26, \cr_int_reg[3]_2\(1) => U0_n_27, \cr_int_reg[3]_2\(0) => U0_n_28, \cr_int_reg[7]_0\(3) => U0_n_19, \cr_int_reg[7]_0\(2) => U0_n_20, \cr_int_reg[7]_0\(1) => U0_n_21, \cr_int_reg[7]_0\(0) => U0_n_22, \cr_int_reg[7]_1\(3) => U0_n_30, \cr_int_reg[7]_1\(2) => U0_n_31, \cr_int_reg[7]_1\(1) => U0_n_32, \cr_int_reg[7]_1\(0) => U0_n_33, hdmi_clk => hdmi_clk, hdmi_d(7 downto 0) => \^hdmi_d\(15 downto 8), hdmi_de => hdmi_de, hdmi_hsync => hdmi_hsync, hdmi_scl => hdmi_scl, hdmi_sda => hdmi_sda, hdmi_vsync => hdmi_vsync, hsync => hsync, rgb888(23 downto 0) => rgb888(23 downto 0), \rgb888[0]\(3) => \cb_int_reg[31]_i_8_n_4\, \rgb888[0]\(2) => \cb_int_reg[31]_i_8_n_5\, \rgb888[0]\(1) => \cb_int_reg[31]_i_8_n_6\, \rgb888[0]\(0) => \cb_int_reg[31]_i_8_n_7\, \rgb888[0]_0\(3) => \cb_int_reg[31]_i_17_n_4\, \rgb888[0]_0\(2) => \cb_int_reg[31]_i_17_n_5\, \rgb888[0]_0\(1) => \cb_int_reg[31]_i_17_n_6\, \rgb888[0]_0\(0) => \cb_int_reg[31]_i_17_n_7\, \rgb888[0]_1\(1) => \cb_int_reg[31]_i_42_n_6\, \rgb888[0]_1\(0) => \cb_int_reg[31]_i_42_n_7\, \rgb888[0]_2\(3) => \cb_int_reg[23]_i_28_n_4\, \rgb888[0]_2\(2) => \cb_int_reg[23]_i_28_n_5\, \rgb888[0]_2\(1) => \cb_int_reg[23]_i_28_n_6\, \rgb888[0]_2\(0) => \cb_int_reg[23]_i_28_n_7\, \rgb888[0]_3\(3) => \cb_int_reg[19]_i_33_n_4\, \rgb888[0]_3\(2) => \cb_int_reg[19]_i_33_n_5\, \rgb888[0]_3\(1) => \cb_int_reg[19]_i_33_n_6\, \rgb888[0]_3\(0) => \cb_int_reg[19]_i_33_n_7\, \rgb888[0]_4\(3) => \cb_int_reg[15]_i_34_n_4\, \rgb888[0]_4\(2) => \cb_int_reg[15]_i_34_n_5\, \rgb888[0]_4\(1) => \cb_int_reg[15]_i_34_n_6\, \rgb888[0]_4\(0) => \cb_int_reg[15]_i_34_n_7\, \rgb888[0]_5\(3) => \cr_int_reg[23]_i_31_n_4\, \rgb888[0]_5\(2) => \cr_int_reg[23]_i_31_n_5\, \rgb888[0]_5\(1) => \cr_int_reg[23]_i_31_n_6\, \rgb888[0]_5\(0) => \cr_int_reg[23]_i_31_n_7\, \rgb888[0]_6\(1) => \cr_int_reg[31]_i_54_n_6\, \rgb888[0]_6\(0) => \cr_int_reg[31]_i_54_n_7\, \rgb888[0]_7\(3) => \y_int_reg[31]_i_71_n_4\, \rgb888[0]_7\(2) => \y_int_reg[31]_i_71_n_5\, \rgb888[0]_7\(1) => \y_int_reg[31]_i_71_n_6\, \rgb888[0]_7\(0) => \y_int_reg[31]_i_71_n_7\, \rgb888[0]_8\(1) => \cb_int_reg[3]_i_43_n_6\, \rgb888[0]_8\(0) => \cb_int_reg[3]_i_43_n_7\, \rgb888[0]_9\(2) => \y_int_reg[31]_i_31_n_5\, \rgb888[0]_9\(1) => \y_int_reg[31]_i_31_n_6\, \rgb888[0]_9\(0) => \y_int_reg[31]_i_31_n_7\, \rgb888[12]\(3) => \cb_int_reg[7]_i_24_n_4\, \rgb888[12]\(2) => \cb_int_reg[7]_i_24_n_5\, \rgb888[12]\(1) => \cb_int_reg[7]_i_24_n_6\, \rgb888[12]\(0) => \cb_int_reg[7]_i_24_n_7\, \rgb888[12]_0\(3) => \cb_int_reg[15]_i_32_n_4\, \rgb888[12]_0\(2) => \cb_int_reg[15]_i_32_n_5\, \rgb888[12]_0\(1) => \cb_int_reg[15]_i_32_n_6\, \rgb888[12]_0\(0) => \cb_int_reg[15]_i_32_n_7\, \rgb888[13]\(0) => \cb_int_reg[3]_i_32_n_4\, \rgb888[13]_0\(3) => \cb_int_reg[7]_i_27_n_4\, \rgb888[13]_0\(2) => \cb_int_reg[7]_i_27_n_5\, \rgb888[13]_0\(1) => \cb_int_reg[7]_i_27_n_6\, \rgb888[13]_0\(0) => \cb_int_reg[7]_i_27_n_7\, \rgb888[14]\(3) => \y_int_reg[3]_i_19_n_4\, \rgb888[14]\(2) => \y_int_reg[3]_i_19_n_5\, \rgb888[14]\(1) => \y_int_reg[3]_i_19_n_6\, \rgb888[14]\(0) => \y_int_reg[3]_i_19_n_7\, \rgb888[14]_0\(1) => \y_int_reg[3]_i_20_n_4\, \rgb888[14]_0\(0) => \y_int_reg[3]_i_20_n_5\, \rgb888[14]_1\(3) => \y_int_reg[7]_i_23_n_4\, \rgb888[14]_1\(2) => \y_int_reg[7]_i_23_n_5\, \rgb888[14]_1\(1) => \y_int_reg[7]_i_23_n_6\, \rgb888[14]_1\(0) => \y_int_reg[7]_i_23_n_7\, \rgb888[1]\(13 downto 0) => y_int_reg2(22 downto 9), \rgb888[1]_0\(0) => \y_int_reg[31]_i_12_n_1\, \rgb888[3]\(3) => \cr_int_reg[15]_i_39_n_4\, \rgb888[3]\(2) => \cr_int_reg[15]_i_39_n_5\, \rgb888[3]\(1) => \cr_int_reg[15]_i_39_n_6\, \rgb888[3]\(0) => \cr_int_reg[15]_i_39_n_7\, \rgb888[3]_0\(3) => \cr_int_reg[19]_i_37_n_4\, \rgb888[3]_0\(2) => \cr_int_reg[19]_i_37_n_5\, \rgb888[3]_0\(1) => \cr_int_reg[19]_i_37_n_6\, \rgb888[3]_0\(0) => \cr_int_reg[19]_i_37_n_7\, \rgb888[8]\(3) => \cb_int_reg[3]_i_19_n_4\, \rgb888[8]\(2) => \cb_int_reg[3]_i_19_n_5\, \rgb888[8]\(1) => \cb_int_reg[3]_i_19_n_6\, \rgb888[8]\(0) => \cb_int_reg[3]_i_19_n_7\, \rgb888[8]_0\(3) => \cb_int_reg[31]_i_23_n_4\, \rgb888[8]_0\(2) => \cb_int_reg[31]_i_23_n_5\, \rgb888[8]_0\(1) => \cb_int_reg[31]_i_23_n_6\, \rgb888[8]_0\(0) => \cb_int_reg[31]_i_23_n_7\, \rgb888[8]_1\(1) => \cb_int_reg[31]_i_9_n_6\, \rgb888[8]_1\(0) => \cb_int_reg[31]_i_9_n_7\, \rgb888[8]_10\(1) => \cb_int_reg[31]_i_66_n_6\, \rgb888[8]_10\(0) => \cb_int_reg[31]_i_66_n_7\, \rgb888[8]_11\(0) => \cb_int_reg[31]_i_10_n_1\, \rgb888[8]_12\(3) => \cr_int_reg[7]_i_24_n_4\, \rgb888[8]_12\(2) => \cr_int_reg[7]_i_24_n_5\, \rgb888[8]_12\(1) => \cr_int_reg[7]_i_24_n_6\, \rgb888[8]_12\(0) => \cr_int_reg[7]_i_24_n_7\, \rgb888[8]_13\(3) => \cr_int_reg[11]_i_28_n_4\, \rgb888[8]_13\(2) => \cr_int_reg[11]_i_28_n_5\, \rgb888[8]_13\(1) => \cr_int_reg[11]_i_28_n_6\, \rgb888[8]_13\(0) => \cr_int_reg[11]_i_28_n_7\, \rgb888[8]_14\(3) => \cr_int_reg[15]_i_37_n_4\, \rgb888[8]_14\(2) => \cr_int_reg[15]_i_37_n_5\, \rgb888[8]_14\(1) => \cr_int_reg[15]_i_37_n_6\, \rgb888[8]_14\(0) => \cr_int_reg[15]_i_37_n_7\, \rgb888[8]_15\(3) => \cr_int_reg[31]_i_64_n_4\, \rgb888[8]_15\(2) => \cr_int_reg[31]_i_64_n_5\, \rgb888[8]_15\(1) => \cr_int_reg[31]_i_64_n_6\, \rgb888[8]_15\(0) => \cr_int_reg[31]_i_64_n_7\, \rgb888[8]_16\(3) => \cr_int_reg[31]_i_27_n_4\, \rgb888[8]_16\(2) => \cr_int_reg[31]_i_27_n_5\, \rgb888[8]_16\(1) => \cr_int_reg[31]_i_27_n_6\, \rgb888[8]_16\(0) => \cr_int_reg[31]_i_27_n_7\, \rgb888[8]_17\(1) => \cr_int_reg[31]_i_10_n_6\, \rgb888[8]_17\(0) => \cr_int_reg[31]_i_10_n_7\, \rgb888[8]_18\(0) => \cr_int_reg[31]_i_10_n_1\, \rgb888[8]_19\(2) => \y_int_reg[3]_i_70_n_4\, \rgb888[8]_19\(1) => \y_int_reg[3]_i_70_n_5\, \rgb888[8]_19\(0) => \y_int_reg[3]_i_70_n_6\, \rgb888[8]_2\(3) => \cb_int_reg[7]_i_26_n_4\, \rgb888[8]_2\(2) => \cb_int_reg[7]_i_26_n_5\, \rgb888[8]_2\(1) => \cb_int_reg[7]_i_26_n_6\, \rgb888[8]_2\(0) => \cb_int_reg[7]_i_26_n_7\, \rgb888[8]_20\(3) => \y_int_reg[31]_i_21_n_4\, \rgb888[8]_20\(2) => \y_int_reg[31]_i_21_n_5\, \rgb888[8]_20\(1) => \y_int_reg[31]_i_21_n_6\, \rgb888[8]_20\(0) => \y_int_reg[31]_i_21_n_7\, \rgb888[8]_21\(2) => \y_int_reg[31]_i_9_n_5\, \rgb888[8]_21\(1) => \y_int_reg[31]_i_9_n_6\, \rgb888[8]_21\(0) => \y_int_reg[31]_i_9_n_7\, \rgb888[8]_22\(3) => \y_int_reg[11]_i_27_n_4\, \rgb888[8]_22\(2) => \y_int_reg[11]_i_27_n_5\, \rgb888[8]_22\(1) => \y_int_reg[11]_i_27_n_6\, \rgb888[8]_22\(0) => \y_int_reg[11]_i_27_n_7\, \rgb888[8]_23\(1) => \y_int_reg[31]_i_10_n_6\, \rgb888[8]_23\(0) => \y_int_reg[31]_i_10_n_7\, \rgb888[8]_24\(0) => \y_int_reg[23]_i_32_n_7\, \rgb888[8]_25\(3) => \y_int_reg[23]_i_35_n_4\, \rgb888[8]_25\(2) => \y_int_reg[23]_i_35_n_5\, \rgb888[8]_25\(1) => \y_int_reg[23]_i_35_n_6\, \rgb888[8]_25\(0) => \y_int_reg[23]_i_35_n_7\, \rgb888[8]_26\(3) => \y_int_reg[31]_i_27_n_4\, \rgb888[8]_26\(2) => \y_int_reg[31]_i_27_n_5\, \rgb888[8]_26\(1) => \y_int_reg[31]_i_27_n_6\, \rgb888[8]_26\(0) => \y_int_reg[31]_i_27_n_7\, \rgb888[8]_27\(3) => \y_int_reg[19]_i_24_n_4\, \rgb888[8]_27\(2) => \y_int_reg[19]_i_24_n_5\, \rgb888[8]_27\(1) => \y_int_reg[19]_i_24_n_6\, \rgb888[8]_27\(0) => \y_int_reg[19]_i_24_n_7\, \rgb888[8]_28\(3) => \y_int_reg[19]_i_33_n_4\, \rgb888[8]_28\(2) => \y_int_reg[19]_i_33_n_5\, \rgb888[8]_28\(1) => \y_int_reg[19]_i_33_n_6\, \rgb888[8]_28\(0) => \y_int_reg[19]_i_33_n_7\, \rgb888[8]_29\(3) => \y_int_reg[15]_i_24_n_4\, \rgb888[8]_29\(2) => \y_int_reg[15]_i_24_n_5\, \rgb888[8]_29\(1) => \y_int_reg[15]_i_24_n_6\, \rgb888[8]_29\(0) => \y_int_reg[15]_i_24_n_7\, \rgb888[8]_3\(3) => \cb_int_reg[7]_i_23_n_4\, \rgb888[8]_3\(2) => \cb_int_reg[7]_i_23_n_5\, \rgb888[8]_3\(1) => \cb_int_reg[7]_i_23_n_6\, \rgb888[8]_3\(0) => \cb_int_reg[7]_i_23_n_7\, \rgb888[8]_30\(0) => \y_int_reg[31]_i_10_n_1\, \rgb888[8]_31\(2) => \cb_int_reg[3]_i_68_n_5\, \rgb888[8]_31\(1) => \cb_int_reg[3]_i_68_n_6\, \rgb888[8]_31\(0) => \cb_int_reg[3]_i_68_n_7\, \rgb888[8]_32\(1) => \y_int_reg[3]_i_40_n_6\, \rgb888[8]_32\(0) => \y_int_reg[3]_i_40_n_7\, \rgb888[8]_4\(3) => \cb_int_reg[15]_i_31_n_4\, \rgb888[8]_4\(2) => \cb_int_reg[15]_i_31_n_5\, \rgb888[8]_4\(1) => \cb_int_reg[15]_i_31_n_6\, \rgb888[8]_4\(0) => \cb_int_reg[15]_i_31_n_7\, \rgb888[8]_5\(3) => \cb_int_reg[31]_i_61_n_4\, \rgb888[8]_5\(2) => \cb_int_reg[31]_i_61_n_5\, \rgb888[8]_5\(1) => \cb_int_reg[31]_i_61_n_6\, \rgb888[8]_5\(0) => \cb_int_reg[31]_i_61_n_7\, \rgb888[8]_6\(3) => \cb_int_reg[19]_i_32_n_4\, \rgb888[8]_6\(2) => \cb_int_reg[19]_i_32_n_5\, \rgb888[8]_6\(1) => \cb_int_reg[19]_i_32_n_6\, \rgb888[8]_6\(0) => \cb_int_reg[19]_i_32_n_7\, \rgb888[8]_7\(3) => \cb_int_reg[31]_i_27_n_4\, \rgb888[8]_7\(2) => \cb_int_reg[31]_i_27_n_5\, \rgb888[8]_7\(1) => \cb_int_reg[31]_i_27_n_6\, \rgb888[8]_7\(0) => \cb_int_reg[31]_i_27_n_7\, \rgb888[8]_8\(3) => \cb_int_reg[23]_i_27_n_4\, \rgb888[8]_8\(2) => \cb_int_reg[23]_i_27_n_5\, \rgb888[8]_8\(1) => \cb_int_reg[23]_i_27_n_6\, \rgb888[8]_8\(0) => \cb_int_reg[23]_i_27_n_7\, \rgb888[8]_9\(1) => \cb_int_reg[31]_i_10_n_6\, \rgb888[8]_9\(0) => \cb_int_reg[31]_i_10_n_7\, vsync => vsync, \y_int_reg[15]_0\(3) => U0_n_68, \y_int_reg[15]_0\(2) => U0_n_69, \y_int_reg[15]_0\(1) => U0_n_70, \y_int_reg[15]_0\(0) => U0_n_71, \y_int_reg[15]_1\(0) => U0_n_81, \y_int_reg[19]_0\(3) => U0_n_64, \y_int_reg[19]_0\(2) => U0_n_65, \y_int_reg[19]_0\(1) => U0_n_66, \y_int_reg[19]_0\(0) => U0_n_67, \y_int_reg[19]_1\(0) => U0_n_79, \y_int_reg[23]_0\(0) => U0_n_55, \y_int_reg[23]_1\(1) => U0_n_58, \y_int_reg[23]_1\(0) => U0_n_59, \y_int_reg[23]_2\(3) => U0_n_60, \y_int_reg[23]_2\(2) => U0_n_61, \y_int_reg[23]_2\(1) => U0_n_62, \y_int_reg[23]_2\(0) => U0_n_63, \y_int_reg[23]_3\(0) => U0_n_80, \y_int_reg[3]_0\(3) => U0_n_51, \y_int_reg[3]_0\(2) => U0_n_52, \y_int_reg[3]_0\(1) => U0_n_53, \y_int_reg[3]_0\(0) => U0_n_54, \y_int_reg[3]_1\(0) => U0_n_57, \y_int_reg[3]_2\(0) => U0_n_78, \y_int_reg[7]_0\(0) => U0_n_56 ); \cb_int[15]_i_35\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[15]_i_32_n_4\, O => \cb_int[15]_i_35_n_0\ ); \cb_int[15]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[15]_i_32_n_5\, O => \cb_int[15]_i_36_n_0\ ); \cb_int[15]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[15]_i_32_n_6\, O => \cb_int[15]_i_37_n_0\ ); \cb_int[15]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[15]_i_32_n_7\, O => \cb_int[15]_i_38_n_0\ ); \cb_int[15]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[15]_i_39_n_0\ ); \cb_int[15]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[15]_i_40_n_0\ ); \cb_int[15]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[15]_i_41_n_0\ ); \cb_int[15]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[15]_i_42_n_0\ ); \cb_int[15]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[15]_i_47_n_0\ ); \cb_int[15]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[15]_i_48_n_0\ ); \cb_int[15]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[15]_i_49_n_0\ ); \cb_int[15]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[15]_i_50_n_0\ ); \cb_int[19]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[19]_i_38_n_0\ ); \cb_int[19]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[19]_i_39_n_0\ ); \cb_int[19]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[19]_i_40_n_0\ ); \cb_int[19]_i_41\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[19]_i_41_n_0\ ); \cb_int[19]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[19]_i_42_n_0\ ); \cb_int[19]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[19]_i_43_n_0\ ); \cb_int[19]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[19]_i_44_n_0\ ); \cb_int[19]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[19]_i_45_n_0\ ); \cb_int[23]_i_33\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[23]_i_33_n_0\ ); \cb_int[23]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[23]_i_34_n_0\ ); \cb_int[23]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[23]_i_35_n_0\ ); \cb_int[23]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[23]_i_36_n_0\ ); \cb_int[23]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[23]_i_37_n_0\ ); \cb_int[23]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[23]_i_38_n_0\ ); \cb_int[23]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[23]_i_39_n_0\ ); \cb_int[23]_i_40\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[23]_i_40_n_0\ ); \cb_int[31]_i_100\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(14), O => \cb_int[31]_i_100_n_0\ ); \cb_int[31]_i_101\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(13), O => \cb_int[31]_i_101_n_0\ ); \cb_int[31]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => U0_n_13, I1 => rgb888(7), O => \cb_int[31]_i_18_n_0\ ); \cb_int[31]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => U0_n_13, O => \cb_int[31]_i_19_n_0\ ); \cb_int[31]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => U0_n_13, O => \cb_int[31]_i_20_n_0\ ); \cb_int[31]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(7), I1 => U0_n_13, O => \cb_int[31]_i_21_n_0\ ); \cb_int[31]_i_22\: unisim.vcomponents.LUT3 generic map( INIT => X"95" ) port map ( I0 => rgb888(7), I1 => \cb_int[31]_i_52_n_0\, I2 => rgb888(6), O => \cb_int[31]_i_22_n_0\ ); \cb_int[31]_i_25\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \cb_int[31]_i_25_n_0\ ); \cb_int[31]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \cb_int[31]_i_26_n_0\ ); \cb_int[31]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_66_n_6\, O => \cb_int[31]_i_28_n_0\ ); \cb_int[31]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_66_n_7\, O => \cb_int[31]_i_29_n_0\ ); \cb_int[31]_i_45\: unisim.vcomponents.LUT5 generic map( INIT => X"99999996" ) port map ( I0 => \cb_int_reg[3]_i_43_n_1\, I1 => rgb888(4), I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), O => \cb_int[31]_i_45_n_0\ ); \cb_int[31]_i_46\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(2), I1 => rgb888(1), O => \cb_int[31]_i_46_n_0\ ); \cb_int[31]_i_47\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAA955555555" ) port map ( I0 => rgb888(6), I1 => rgb888(4), I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), I5 => rgb888(5), O => \cb_int[31]_i_47_n_0\ ); \cb_int[31]_i_48\: unisim.vcomponents.LUT6 generic map( INIT => X"CCCCCCC999999993" ) port map ( I0 => \cb_int_reg[3]_i_43_n_1\, I1 => rgb888(5), I2 => rgb888(3), I3 => rgb888(1), I4 => rgb888(2), I5 => rgb888(4), O => \cb_int[31]_i_48_n_0\ ); \cb_int[31]_i_49\: unisim.vcomponents.LUT5 generic map( INIT => X"AAA99995" ) port map ( I0 => rgb888(4), I1 => \cb_int_reg[3]_i_43_n_1\, I2 => rgb888(2), I3 => rgb888(1), I4 => rgb888(3), O => \cb_int[31]_i_49_n_0\ ); \cb_int[31]_i_50\: unisim.vcomponents.LUT4 generic map( INIT => X"6A95" ) port map ( I0 => \cb_int_reg[3]_i_43_n_1\, I1 => rgb888(2), I2 => rgb888(1), I3 => rgb888(3), O => \cb_int[31]_i_50_n_0\ ); \cb_int[31]_i_52\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => rgb888(4), I1 => rgb888(2), I2 => rgb888(1), I3 => rgb888(3), I4 => rgb888(5), O => \cb_int[31]_i_52_n_0\ ); \cb_int[31]_i_53\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000080000000" ) port map ( I0 => rgb888(14), I1 => rgb888(12), I2 => rgb888(10), I3 => rgb888(11), I4 => rgb888(13), I5 => rgb888(15), O => \cb_int[31]_i_53_n_0\ ); \cb_int[31]_i_54\: unisim.vcomponents.LUT6 generic map( INIT => X"000000006AAAAAAA" ) port map ( I0 => rgb888(14), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(15), O => \cb_int[31]_i_54_n_0\ ); \cb_int[31]_i_55\: unisim.vcomponents.LUT6 generic map( INIT => X"2BBBBBBBB2222222" ) port map ( I0 => \cb_int_reg[31]_i_85_n_0\, I1 => rgb888(15), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(13), O => \cb_int[31]_i_55_n_0\ ); \cb_int[31]_i_56\: unisim.vcomponents.LUT5 generic map( INIT => X"BFEA2A80" ) port map ( I0 => \cb_int_reg[31]_i_85_n_5\, I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(12), I4 => rgb888(14), O => \cb_int[31]_i_56_n_0\ ); \cb_int[31]_i_57\: unisim.vcomponents.LUT6 generic map( INIT => X"9555555555555555" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \cb_int[31]_i_57_n_0\ ); \cb_int[31]_i_58\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAABFFFFFFF" ) port map ( I0 => rgb888(15), I1 => rgb888(13), I2 => rgb888(11), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \cb_int[31]_i_58_n_0\ ); \cb_int[31]_i_59\: unisim.vcomponents.LUT4 generic map( INIT => X"7E81" ) port map ( I0 => U0_n_6, I1 => \cb_int_reg[31]_i_85_n_0\, I2 => rgb888(15), I3 => U0_n_5, O => \cb_int[31]_i_59_n_0\ ); \cb_int[31]_i_60\: unisim.vcomponents.LUT6 generic map( INIT => X"E81717E817E8E817" ) port map ( I0 => rgb888(14), I1 => \cb_int[31]_i_88_n_0\, I2 => \cb_int_reg[31]_i_85_n_5\, I3 => U0_n_6, I4 => rgb888(15), I5 => \cb_int_reg[31]_i_85_n_0\, O => \cb_int[31]_i_60_n_0\ ); \cb_int[31]_i_62\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[23]_i_27_n_4\, O => \cb_int[31]_i_62_n_0\ ); \cb_int[31]_i_63\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[23]_i_27_n_5\, O => \cb_int[31]_i_63_n_0\ ); \cb_int[31]_i_64\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[23]_i_27_n_6\, O => \cb_int[31]_i_64_n_0\ ); \cb_int[31]_i_65\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[23]_i_27_n_7\, O => \cb_int[31]_i_65_n_0\ ); \cb_int[31]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[31]_i_83_n_0\ ); \cb_int[31]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_8_n_4\, O => \cb_int[31]_i_84_n_0\ ); \cb_int[31]_i_88\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => rgb888(10), I1 => rgb888(11), I2 => rgb888(12), O => \cb_int[31]_i_88_n_0\ ); \cb_int[31]_i_89\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[19]_i_32_n_4\, O => \cb_int[31]_i_89_n_0\ ); \cb_int[31]_i_90\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[19]_i_32_n_5\, O => \cb_int[31]_i_90_n_0\ ); \cb_int[31]_i_91\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[19]_i_32_n_6\, O => \cb_int[31]_i_91_n_0\ ); \cb_int[31]_i_92\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[19]_i_32_n_7\, O => \cb_int[31]_i_92_n_0\ ); \cb_int[31]_i_93\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[31]_i_93_n_0\ ); \cb_int[31]_i_94\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[31]_i_94_n_0\ ); \cb_int[31]_i_99\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \cb_int[31]_i_99_n_0\ ); \cb_int[3]_i_35\: unisim.vcomponents.LUT4 generic map( INIT => X"BE28" ) port map ( I0 => \cb_int_reg[31]_i_85_n_6\, I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(13), O => \cb_int[3]_i_35_n_0\ ); \cb_int[3]_i_36\: unisim.vcomponents.LUT3 generic map( INIT => X"D4" ) port map ( I0 => rgb888(10), I1 => \cb_int_reg[31]_i_85_n_7\, I2 => rgb888(12), O => \cb_int[3]_i_36_n_0\ ); \cb_int[3]_i_37\: unisim.vcomponents.LUT3 generic map( INIT => X"E8" ) port map ( I0 => \cb_int_reg[3]_i_68_n_4\, I1 => rgb888(9), I2 => rgb888(11), O => \cb_int[3]_i_37_n_0\ ); \cb_int[3]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cb_int_reg[3]_i_68_n_4\, I1 => rgb888(9), I2 => rgb888(11), O => \cb_int[3]_i_38_n_0\ ); \cb_int[3]_i_39\: unisim.vcomponents.LUT6 generic map( INIT => X"9669696969969696" ) port map ( I0 => \cb_int[3]_i_35_n_0\, I1 => rgb888(14), I2 => rgb888(12), I3 => rgb888(11), I4 => rgb888(10), I5 => \cb_int_reg[31]_i_85_n_5\, O => \cb_int[3]_i_39_n_0\ ); \cb_int[3]_i_40\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \cb_int_reg[31]_i_85_n_6\, I1 => rgb888(10), I2 => rgb888(11), I3 => rgb888(13), I4 => \cb_int[3]_i_36_n_0\, O => \cb_int[3]_i_40_n_0\ ); \cb_int[3]_i_41\: unisim.vcomponents.LUT6 generic map( INIT => X"E81717E817E8E817" ) port map ( I0 => rgb888(11), I1 => rgb888(9), I2 => \cb_int_reg[3]_i_68_n_4\, I3 => rgb888(12), I4 => rgb888(10), I5 => \cb_int_reg[31]_i_85_n_7\, O => \cb_int[3]_i_41_n_0\ ); \cb_int[3]_i_42\: unisim.vcomponents.LUT5 generic map( INIT => X"69969696" ) port map ( I0 => rgb888(11), I1 => rgb888(9), I2 => \cb_int_reg[3]_i_68_n_4\, I3 => rgb888(10), I4 => rgb888(8), O => \cb_int[3]_i_42_n_0\ ); \cb_int[3]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_19_n_6\, O => \cb_int[3]_i_59_n_0\ ); \cb_int[3]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_19_n_7\, O => \cb_int[3]_i_60_n_0\ ); \cb_int[3]_i_61\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_9, O => \cb_int[3]_i_61_n_0\ ); \cb_int[3]_i_62\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_10, O => \cb_int[3]_i_62_n_0\ ); \cb_int[3]_i_73\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(7), O => \cb_int[3]_i_73_n_0\ ); \cb_int[3]_i_74\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(6), O => \cb_int[3]_i_74_n_0\ ); \cb_int[3]_i_84\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(8), O => \cb_int[3]_i_84_n_0\ ); \cb_int[3]_i_85\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_11, O => \cb_int[3]_i_85_n_0\ ); \cb_int[3]_i_86\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_12, O => \cb_int[3]_i_86_n_0\ ); \cb_int[3]_i_87\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_7, O => \cb_int[3]_i_87_n_0\ ); \cb_int[3]_i_88\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_8, O => \cb_int[3]_i_88_n_0\ ); \cb_int[3]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(12), I1 => rgb888(15), O => \cb_int[3]_i_95_n_0\ ); \cb_int[3]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(11), I1 => rgb888(14), O => \cb_int[3]_i_96_n_0\ ); \cb_int[3]_i_97\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(10), I1 => rgb888(13), O => \cb_int[3]_i_97_n_0\ ); \cb_int[3]_i_98\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(9), I1 => rgb888(12), O => \cb_int[3]_i_98_n_0\ ); \cb_int[7]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[7]_i_24_n_4\, O => \cb_int[7]_i_30_n_0\ ); \cb_int[7]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_24_n_5\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_9_n_7\, O => \cb_int[7]_i_31_n_0\ ); \cb_int[7]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_24_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_23_n_4\, O => \cb_int[7]_i_32_n_0\ ); \cb_int[7]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_24_n_7\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_23_n_5\, O => \cb_int[7]_i_33_n_0\ ); \cb_int[7]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_6\, O => \cb_int[7]_i_34_n_0\ ); \cb_int[7]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_9_n_7\, O => \cb_int[7]_i_35_n_0\ ); \cb_int[7]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_23_n_4\, O => \cb_int[7]_i_36_n_0\ ); \cb_int[7]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_23_n_5\, O => \cb_int[7]_i_37_n_0\ ); \cb_int[7]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[3]_i_32_n_4\, I1 => U0_n_16, I2 => \cb_int_reg[3]_i_19_n_6\, O => \cb_int[7]_i_43_n_0\ ); \cb_int[7]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_27_n_4\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_23_n_6\, O => \cb_int[7]_i_44_n_0\ ); \cb_int[7]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_27_n_5\, I1 => U0_n_16, I2 => \cb_int_reg[31]_i_23_n_7\, O => \cb_int[7]_i_45_n_0\ ); \cb_int[7]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_27_n_6\, I1 => U0_n_16, I2 => \cb_int_reg[3]_i_19_n_4\, O => \cb_int[7]_i_46_n_0\ ); \cb_int[7]_i_47\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => \cb_int_reg[7]_i_27_n_7\, I1 => U0_n_16, I2 => \cb_int_reg[3]_i_19_n_5\, O => \cb_int[7]_i_47_n_0\ ); \cb_int[7]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_23_n_6\, O => \cb_int[7]_i_48_n_0\ ); \cb_int[7]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[31]_i_23_n_7\, O => \cb_int[7]_i_49_n_0\ ); \cb_int[7]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_19_n_4\, O => \cb_int[7]_i_50_n_0\ ); \cb_int[7]_i_51\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \cb_int_reg[3]_i_19_n_5\, O => \cb_int[7]_i_51_n_0\ ); \cb_int_reg[15]_i_31\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_23_n_0\, CO(3) => \cb_int_reg[15]_i_31_n_0\, CO(2) => \cb_int_reg[15]_i_31_n_1\, CO(1) => \cb_int_reg[15]_i_31_n_2\, CO(0) => \cb_int_reg[15]_i_31_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[15]_i_31_n_4\, O(2) => \cb_int_reg[15]_i_31_n_5\, O(1) => \cb_int_reg[15]_i_31_n_6\, O(0) => \cb_int_reg[15]_i_31_n_7\, S(3) => \cb_int[15]_i_35_n_0\, S(2) => \cb_int[15]_i_36_n_0\, S(1) => \cb_int[15]_i_37_n_0\, S(0) => \cb_int[15]_i_38_n_0\ ); \cb_int_reg[15]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_24_n_0\, CO(3) => \cb_int_reg[15]_i_32_n_0\, CO(2) => \cb_int_reg[15]_i_32_n_1\, CO(1) => \cb_int_reg[15]_i_32_n_2\, CO(0) => \cb_int_reg[15]_i_32_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[15]_i_32_n_4\, O(2) => \cb_int_reg[15]_i_32_n_5\, O(1) => \cb_int_reg[15]_i_32_n_6\, O(0) => \cb_int_reg[15]_i_32_n_7\, S(3) => \cb_int[15]_i_39_n_0\, S(2) => \cb_int[15]_i_40_n_0\, S(1) => \cb_int[15]_i_41_n_0\, S(0) => \cb_int[15]_i_42_n_0\ ); \cb_int_reg[15]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_76, CO(3) => \cb_int_reg[15]_i_34_n_0\, CO(2) => \cb_int_reg[15]_i_34_n_1\, CO(1) => \cb_int_reg[15]_i_34_n_2\, CO(0) => \cb_int_reg[15]_i_34_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[15]_i_34_n_4\, O(2) => \cb_int_reg[15]_i_34_n_5\, O(1) => \cb_int_reg[15]_i_34_n_6\, O(0) => \cb_int_reg[15]_i_34_n_7\, S(3) => \cb_int[15]_i_47_n_0\, S(2) => \cb_int[15]_i_48_n_0\, S(1) => \cb_int[15]_i_49_n_0\, S(0) => \cb_int[15]_i_50_n_0\ ); \cb_int_reg[19]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_32_n_0\, CO(3) => \cb_int_reg[19]_i_32_n_0\, CO(2) => \cb_int_reg[19]_i_32_n_1\, CO(1) => \cb_int_reg[19]_i_32_n_2\, CO(0) => \cb_int_reg[19]_i_32_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[19]_i_32_n_4\, O(2) => \cb_int_reg[19]_i_32_n_5\, O(1) => \cb_int_reg[19]_i_32_n_6\, O(0) => \cb_int_reg[19]_i_32_n_7\, S(3) => \cb_int[19]_i_38_n_0\, S(2) => \cb_int[19]_i_39_n_0\, S(1) => \cb_int[19]_i_40_n_0\, S(0) => \cb_int[19]_i_41_n_0\ ); \cb_int_reg[19]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_34_n_0\, CO(3) => \cb_int_reg[19]_i_33_n_0\, CO(2) => \cb_int_reg[19]_i_33_n_1\, CO(1) => \cb_int_reg[19]_i_33_n_2\, CO(0) => \cb_int_reg[19]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[19]_i_33_n_4\, O(2) => \cb_int_reg[19]_i_33_n_5\, O(1) => \cb_int_reg[19]_i_33_n_6\, O(0) => \cb_int_reg[19]_i_33_n_7\, S(3) => \cb_int[19]_i_42_n_0\, S(2) => \cb_int[19]_i_43_n_0\, S(1) => \cb_int[19]_i_44_n_0\, S(0) => \cb_int[19]_i_45_n_0\ ); \cb_int_reg[23]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_32_n_0\, CO(3) => \cb_int_reg[23]_i_27_n_0\, CO(2) => \cb_int_reg[23]_i_27_n_1\, CO(1) => \cb_int_reg[23]_i_27_n_2\, CO(0) => \cb_int_reg[23]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[23]_i_27_n_4\, O(2) => \cb_int_reg[23]_i_27_n_5\, O(1) => \cb_int_reg[23]_i_27_n_6\, O(0) => \cb_int_reg[23]_i_27_n_7\, S(3) => \cb_int[23]_i_33_n_0\, S(2) => \cb_int[23]_i_34_n_0\, S(1) => \cb_int[23]_i_35_n_0\, S(0) => \cb_int[23]_i_36_n_0\ ); \cb_int_reg[23]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[19]_i_33_n_0\, CO(3) => \cb_int_reg[23]_i_28_n_0\, CO(2) => \cb_int_reg[23]_i_28_n_1\, CO(1) => \cb_int_reg[23]_i_28_n_2\, CO(0) => \cb_int_reg[23]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[23]_i_28_n_4\, O(2) => \cb_int_reg[23]_i_28_n_5\, O(1) => \cb_int_reg[23]_i_28_n_6\, O(0) => \cb_int_reg[23]_i_28_n_7\, S(3) => \cb_int[23]_i_37_n_0\, S(2) => \cb_int[23]_i_38_n_0\, S(1) => \cb_int[23]_i_39_n_0\, S(0) => \cb_int[23]_i_40_n_0\ ); \cb_int_reg[31]_i_10\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_27_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_10_n_1\, CO(1) => \NLW_cb_int_reg[31]_i_10_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[31]_i_10_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_10_n_6\, O(0) => \cb_int_reg[31]_i_10_n_7\, S(3 downto 2) => B"01", S(1) => \cb_int[31]_i_28_n_0\, S(0) => \cb_int[31]_i_29_n_0\ ); \cb_int_reg[31]_i_17\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_75, CO(3) => \cb_int_reg[31]_i_17_n_0\, CO(2) => \cb_int_reg[31]_i_17_n_1\, CO(1) => \cb_int_reg[31]_i_17_n_2\, CO(0) => \cb_int_reg[31]_i_17_n_3\, CYINIT => '0', DI(3) => U0_n_14, DI(2) => U0_n_15, DI(1) => \cb_int[31]_i_45_n_0\, DI(0) => \cb_int[31]_i_46_n_0\, O(3) => \cb_int_reg[31]_i_17_n_4\, O(2) => \cb_int_reg[31]_i_17_n_5\, O(1) => \cb_int_reg[31]_i_17_n_6\, O(0) => \cb_int_reg[31]_i_17_n_7\, S(3) => \cb_int[31]_i_47_n_0\, S(2) => \cb_int[31]_i_48_n_0\, S(1) => \cb_int[31]_i_49_n_0\, S(0) => \cb_int[31]_i_50_n_0\ ); \cb_int_reg[31]_i_23\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_19_n_0\, CO(3) => \cb_int_reg[31]_i_23_n_0\, CO(2) => \cb_int_reg[31]_i_23_n_1\, CO(1) => \cb_int_reg[31]_i_23_n_2\, CO(0) => \cb_int_reg[31]_i_23_n_3\, CYINIT => '0', DI(3) => \cb_int[31]_i_53_n_0\, DI(2) => \cb_int[31]_i_54_n_0\, DI(1) => \cb_int[31]_i_55_n_0\, DI(0) => \cb_int[31]_i_56_n_0\, O(3) => \cb_int_reg[31]_i_23_n_4\, O(2) => \cb_int_reg[31]_i_23_n_5\, O(1) => \cb_int_reg[31]_i_23_n_6\, O(0) => \cb_int_reg[31]_i_23_n_7\, S(3) => \cb_int[31]_i_57_n_0\, S(2) => \cb_int[31]_i_58_n_0\, S(1) => \cb_int[31]_i_59_n_0\, S(0) => \cb_int[31]_i_60_n_0\ ); \cb_int_reg[31]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_61_n_0\, CO(3) => \cb_int_reg[31]_i_27_n_0\, CO(2) => \cb_int_reg[31]_i_27_n_1\, CO(1) => \cb_int_reg[31]_i_27_n_2\, CO(0) => \cb_int_reg[31]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[31]_i_27_n_4\, O(2) => \cb_int_reg[31]_i_27_n_5\, O(1) => \cb_int_reg[31]_i_27_n_6\, O(0) => \cb_int_reg[31]_i_27_n_7\, S(3) => \cb_int[31]_i_62_n_0\, S(2) => \cb_int[31]_i_63_n_0\, S(1) => \cb_int[31]_i_64_n_0\, S(0) => \cb_int[31]_i_65_n_0\ ); \cb_int_reg[31]_i_42\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[23]_i_28_n_0\, CO(3 downto 1) => \NLW_cb_int_reg[31]_i_42_CO_UNCONNECTED\(3 downto 1), CO(0) => \cb_int_reg[31]_i_42_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_42_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_42_n_6\, O(0) => \cb_int_reg[31]_i_42_n_7\, S(3 downto 2) => B"00", S(1) => \cb_int[31]_i_83_n_0\, S(0) => \cb_int[31]_i_84_n_0\ ); \cb_int_reg[31]_i_61\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[15]_i_31_n_0\, CO(3) => \cb_int_reg[31]_i_61_n_0\, CO(2) => \cb_int_reg[31]_i_61_n_1\, CO(1) => \cb_int_reg[31]_i_61_n_2\, CO(0) => \cb_int_reg[31]_i_61_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[31]_i_61_n_4\, O(2) => \cb_int_reg[31]_i_61_n_5\, O(1) => \cb_int_reg[31]_i_61_n_6\, O(0) => \cb_int_reg[31]_i_61_n_7\, S(3) => \cb_int[31]_i_89_n_0\, S(2) => \cb_int[31]_i_90_n_0\, S(1) => \cb_int[31]_i_91_n_0\, S(0) => \cb_int[31]_i_92_n_0\ ); \cb_int_reg[31]_i_66\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[23]_i_27_n_0\, CO(3 downto 1) => \NLW_cb_int_reg[31]_i_66_CO_UNCONNECTED\(3 downto 1), CO(0) => \cb_int_reg[31]_i_66_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cb_int_reg[31]_i_66_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_66_n_6\, O(0) => \cb_int_reg[31]_i_66_n_7\, S(3 downto 2) => B"00", S(1) => \cb_int[31]_i_93_n_0\, S(0) => \cb_int[31]_i_94_n_0\ ); \cb_int_reg[31]_i_8\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_17_n_0\, CO(3) => \NLW_cb_int_reg[31]_i_8_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[31]_i_8_n_1\, CO(1) => \cb_int_reg[31]_i_8_n_2\, CO(0) => \cb_int_reg[31]_i_8_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \cb_int[31]_i_18_n_0\, O(3) => \cb_int_reg[31]_i_8_n_4\, O(2) => \cb_int_reg[31]_i_8_n_5\, O(1) => \cb_int_reg[31]_i_8_n_6\, O(0) => \cb_int_reg[31]_i_8_n_7\, S(3) => \cb_int[31]_i_19_n_0\, S(2) => \cb_int[31]_i_20_n_0\, S(1) => \cb_int[31]_i_21_n_0\, S(0) => \cb_int[31]_i_22_n_0\ ); \cb_int_reg[31]_i_85\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_68_n_0\, CO(3) => \cb_int_reg[31]_i_85_n_0\, CO(2) => \NLW_cb_int_reg[31]_i_85_CO_UNCONNECTED\(2), CO(1) => \cb_int_reg[31]_i_85_n_2\, CO(0) => \cb_int_reg[31]_i_85_n_3\, CYINIT => '0', DI(3) => '0', DI(2 downto 1) => rgb888(15 downto 14), DI(0) => '0', O(3) => \NLW_cb_int_reg[31]_i_85_O_UNCONNECTED\(3), O(2) => \cb_int_reg[31]_i_85_n_5\, O(1) => \cb_int_reg[31]_i_85_n_6\, O(0) => \cb_int_reg[31]_i_85_n_7\, S(3) => '1', S(2) => \cb_int[31]_i_99_n_0\, S(1) => \cb_int[31]_i_100_n_0\, S(0) => \cb_int[31]_i_101_n_0\ ); \cb_int_reg[31]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[31]_i_23_n_0\, CO(3 downto 1) => \NLW_cb_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 1), CO(0) => \cb_int_reg[31]_i_9_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => U0_n_4, O(3 downto 2) => \NLW_cb_int_reg[31]_i_9_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[31]_i_9_n_6\, O(0) => \cb_int_reg[31]_i_9_n_7\, S(3 downto 2) => B"00", S(1) => \cb_int[31]_i_25_n_0\, S(0) => \cb_int[31]_i_26_n_0\ ); \cb_int_reg[3]_i_19\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_73, CO(3) => \cb_int_reg[3]_i_19_n_0\, CO(2) => \cb_int_reg[3]_i_19_n_1\, CO(1) => \cb_int_reg[3]_i_19_n_2\, CO(0) => \cb_int_reg[3]_i_19_n_3\, CYINIT => '0', DI(3) => \cb_int[3]_i_35_n_0\, DI(2) => \cb_int[3]_i_36_n_0\, DI(1) => \cb_int[3]_i_37_n_0\, DI(0) => \cb_int[3]_i_38_n_0\, O(3) => \cb_int_reg[3]_i_19_n_4\, O(2) => \cb_int_reg[3]_i_19_n_5\, O(1) => \cb_int_reg[3]_i_19_n_6\, O(0) => \cb_int_reg[3]_i_19_n_7\, S(3) => \cb_int[3]_i_39_n_0\, S(2) => \cb_int[3]_i_40_n_0\, S(1) => \cb_int[3]_i_41_n_0\, S(0) => \cb_int[3]_i_42_n_0\ ); \cb_int_reg[3]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_58_n_0\, CO(3) => \cb_int_reg[3]_i_32_n_0\, CO(2) => \cb_int_reg[3]_i_32_n_1\, CO(1) => \cb_int_reg[3]_i_32_n_2\, CO(0) => \cb_int_reg[3]_i_32_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[3]_i_32_n_4\, O(2 downto 0) => \NLW_cb_int_reg[3]_i_32_O_UNCONNECTED\(2 downto 0), S(3) => \cb_int[3]_i_59_n_0\, S(2) => \cb_int[3]_i_60_n_0\, S(1) => \cb_int[3]_i_61_n_0\, S(0) => \cb_int[3]_i_62_n_0\ ); \cb_int_reg[3]_i_43\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_74, CO(3) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(3), CO(2) => \cb_int_reg[3]_i_43_n_1\, CO(1) => \NLW_cb_int_reg[3]_i_43_CO_UNCONNECTED\(1), CO(0) => \cb_int_reg[3]_i_43_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => rgb888(7), DI(0) => '0', O(3 downto 2) => \NLW_cb_int_reg[3]_i_43_O_UNCONNECTED\(3 downto 2), O(1) => \cb_int_reg[3]_i_43_n_6\, O(0) => \cb_int_reg[3]_i_43_n_7\, S(3 downto 2) => B"01", S(1) => \cb_int[3]_i_73_n_0\, S(0) => \cb_int[3]_i_74_n_0\ ); \cb_int_reg[3]_i_58\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[3]_i_58_n_0\, CO(2) => \cb_int_reg[3]_i_58_n_1\, CO(1) => \cb_int_reg[3]_i_58_n_2\, CO(0) => \cb_int_reg[3]_i_58_n_3\, CYINIT => \cb_int[3]_i_84_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_cb_int_reg[3]_i_58_O_UNCONNECTED\(3 downto 0), S(3) => \cb_int[3]_i_85_n_0\, S(2) => \cb_int[3]_i_86_n_0\, S(1) => \cb_int[3]_i_87_n_0\, S(0) => \cb_int[3]_i_88_n_0\ ); \cb_int_reg[3]_i_68\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_72, CO(3) => \cb_int_reg[3]_i_68_n_0\, CO(2) => \cb_int_reg[3]_i_68_n_1\, CO(1) => \cb_int_reg[3]_i_68_n_2\, CO(0) => \cb_int_reg[3]_i_68_n_3\, CYINIT => '0', DI(3 downto 0) => rgb888(12 downto 9), O(3) => \cb_int_reg[3]_i_68_n_4\, O(2) => \cb_int_reg[3]_i_68_n_5\, O(1) => \cb_int_reg[3]_i_68_n_6\, O(0) => \cb_int_reg[3]_i_68_n_7\, S(3) => \cb_int[3]_i_95_n_0\, S(2) => \cb_int[3]_i_96_n_0\, S(1) => \cb_int[3]_i_97_n_0\, S(0) => \cb_int[3]_i_98_n_0\ ); \cb_int_reg[7]_i_23\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_26_n_0\, CO(3) => \cb_int_reg[7]_i_23_n_0\, CO(2) => \cb_int_reg[7]_i_23_n_1\, CO(1) => \cb_int_reg[7]_i_23_n_2\, CO(0) => \cb_int_reg[7]_i_23_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_23_n_4\, O(2) => \cb_int_reg[7]_i_23_n_5\, O(1) => \cb_int_reg[7]_i_23_n_6\, O(0) => \cb_int_reg[7]_i_23_n_7\, S(3) => \cb_int[7]_i_30_n_0\, S(2) => \cb_int[7]_i_31_n_0\, S(1) => \cb_int[7]_i_32_n_0\, S(0) => \cb_int[7]_i_33_n_0\ ); \cb_int_reg[7]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[7]_i_27_n_0\, CO(3) => \cb_int_reg[7]_i_24_n_0\, CO(2) => \cb_int_reg[7]_i_24_n_1\, CO(1) => \cb_int_reg[7]_i_24_n_2\, CO(0) => \cb_int_reg[7]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_24_n_4\, O(2) => \cb_int_reg[7]_i_24_n_5\, O(1) => \cb_int_reg[7]_i_24_n_6\, O(0) => \cb_int_reg[7]_i_24_n_7\, S(3) => \cb_int[7]_i_34_n_0\, S(2) => \cb_int[7]_i_35_n_0\, S(1) => \cb_int[7]_i_36_n_0\, S(0) => \cb_int[7]_i_37_n_0\ ); \cb_int_reg[7]_i_26\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cb_int_reg[7]_i_26_n_0\, CO(2) => \cb_int_reg[7]_i_26_n_1\, CO(1) => \cb_int_reg[7]_i_26_n_2\, CO(0) => \cb_int_reg[7]_i_26_n_3\, CYINIT => \cb_int[7]_i_43_n_0\, DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_26_n_4\, O(2) => \cb_int_reg[7]_i_26_n_5\, O(1) => \cb_int_reg[7]_i_26_n_6\, O(0) => \cb_int_reg[7]_i_26_n_7\, S(3) => \cb_int[7]_i_44_n_0\, S(2) => \cb_int[7]_i_45_n_0\, S(1) => \cb_int[7]_i_46_n_0\, S(0) => \cb_int[7]_i_47_n_0\ ); \cb_int_reg[7]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cb_int_reg[3]_i_32_n_0\, CO(3) => \cb_int_reg[7]_i_27_n_0\, CO(2) => \cb_int_reg[7]_i_27_n_1\, CO(1) => \cb_int_reg[7]_i_27_n_2\, CO(0) => \cb_int_reg[7]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cb_int_reg[7]_i_27_n_4\, O(2) => \cb_int_reg[7]_i_27_n_5\, O(1) => \cb_int_reg[7]_i_27_n_6\, O(0) => \cb_int_reg[7]_i_27_n_7\, S(3) => \cb_int[7]_i_48_n_0\, S(2) => \cb_int[7]_i_49_n_0\, S(1) => \cb_int[7]_i_50_n_0\, S(0) => \cb_int[7]_i_51_n_0\ ); \cr_int[11]_i_61\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_35, O => \cr_int[11]_i_61_n_0\ ); \cr_int[11]_i_62\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_36, I1 => U0_n_26, I2 => U0_n_18, O => \cr_int[11]_i_62_n_0\ ); \cr_int[11]_i_63\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_37, I1 => U0_n_26, I2 => U0_n_19, O => \cr_int[11]_i_63_n_0\ ); \cr_int[11]_i_64\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_30, I1 => U0_n_26, I2 => U0_n_20, O => \cr_int[11]_i_64_n_0\ ); \cr_int[15]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_39, O => \cr_int[15]_i_44_n_0\ ); \cr_int[15]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_40, O => \cr_int[15]_i_45_n_0\ ); \cr_int[15]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_41, O => \cr_int[15]_i_46_n_0\ ); \cr_int[15]_i_47\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_34, O => \cr_int[15]_i_47_n_0\ ); \cr_int[15]_i_52\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[15]_i_52_n_0\ ); \cr_int[15]_i_53\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[15]_i_53_n_0\ ); \cr_int[15]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[15]_i_54_n_0\ ); \cr_int[15]_i_55\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[15]_i_55_n_0\ ); \cr_int[19]_i_42\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[19]_i_42_n_0\ ); \cr_int[19]_i_43\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[19]_i_43_n_0\ ); \cr_int[19]_i_44\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[19]_i_44_n_0\ ); \cr_int[19]_i_45\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[19]_i_45_n_0\ ); \cr_int[23]_i_32\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[23]_i_32_n_0\ ); \cr_int[23]_i_33\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[23]_i_33_n_0\ ); \cr_int[23]_i_34\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[23]_i_34_n_0\ ); \cr_int[23]_i_35\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[23]_i_35_n_0\ ); \cr_int[31]_i_104\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_43, O => \cr_int[31]_i_104_n_0\ ); \cr_int[31]_i_105\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_44, O => \cr_int[31]_i_105_n_0\ ); \cr_int[31]_i_106\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_45, O => \cr_int[31]_i_106_n_0\ ); \cr_int[31]_i_107\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_38, O => \cr_int[31]_i_107_n_0\ ); \cr_int[31]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_50, O => \cr_int[31]_i_28_n_0\ ); \cr_int[31]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_46, O => \cr_int[31]_i_29_n_0\ ); \cr_int[31]_i_65\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_47, O => \cr_int[31]_i_65_n_0\ ); \cr_int[31]_i_66\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_48, O => \cr_int[31]_i_66_n_0\ ); \cr_int[31]_i_67\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_49, O => \cr_int[31]_i_67_n_0\ ); \cr_int[31]_i_68\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_17, I1 => U0_n_26, I2 => U0_n_42, O => \cr_int[31]_i_68_n_0\ ); \cr_int[31]_i_98\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[31]_i_98_n_0\ ); \cr_int[31]_i_99\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_29, O => \cr_int[31]_i_99_n_0\ ); \cr_int[7]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_28, I1 => U0_n_26, I2 => U0_n_25, O => \cr_int[7]_i_29_n_0\ ); \cr_int[7]_i_30\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_31, I1 => U0_n_26, I2 => U0_n_21, O => \cr_int[7]_i_30_n_0\ ); \cr_int[7]_i_31\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_32, I1 => U0_n_26, I2 => U0_n_22, O => \cr_int[7]_i_31_n_0\ ); \cr_int[7]_i_32\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_33, I1 => U0_n_26, I2 => U0_n_23, O => \cr_int[7]_i_32_n_0\ ); \cr_int[7]_i_33\: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => U0_n_27, I1 => U0_n_26, I2 => U0_n_24, O => \cr_int[7]_i_33_n_0\ ); \cr_int_reg[11]_i_28\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[7]_i_24_n_0\, CO(3) => \cr_int_reg[11]_i_28_n_0\, CO(2) => \cr_int_reg[11]_i_28_n_1\, CO(1) => \cr_int_reg[11]_i_28_n_2\, CO(0) => \cr_int_reg[11]_i_28_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[11]_i_28_n_4\, O(2) => \cr_int_reg[11]_i_28_n_5\, O(1) => \cr_int_reg[11]_i_28_n_6\, O(0) => \cr_int_reg[11]_i_28_n_7\, S(3) => \cr_int[11]_i_61_n_0\, S(2) => \cr_int[11]_i_62_n_0\, S(1) => \cr_int[11]_i_63_n_0\, S(0) => \cr_int[11]_i_64_n_0\ ); \cr_int_reg[15]_i_37\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[11]_i_28_n_0\, CO(3) => \cr_int_reg[15]_i_37_n_0\, CO(2) => \cr_int_reg[15]_i_37_n_1\, CO(1) => \cr_int_reg[15]_i_37_n_2\, CO(0) => \cr_int_reg[15]_i_37_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[15]_i_37_n_4\, O(2) => \cr_int_reg[15]_i_37_n_5\, O(1) => \cr_int_reg[15]_i_37_n_6\, O(0) => \cr_int_reg[15]_i_37_n_7\, S(3) => \cr_int[15]_i_44_n_0\, S(2) => \cr_int[15]_i_45_n_0\, S(1) => \cr_int[15]_i_46_n_0\, S(0) => \cr_int[15]_i_47_n_0\ ); \cr_int_reg[15]_i_39\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_77, CO(3) => \cr_int_reg[15]_i_39_n_0\, CO(2) => \cr_int_reg[15]_i_39_n_1\, CO(1) => \cr_int_reg[15]_i_39_n_2\, CO(0) => \cr_int_reg[15]_i_39_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[15]_i_39_n_4\, O(2) => \cr_int_reg[15]_i_39_n_5\, O(1) => \cr_int_reg[15]_i_39_n_6\, O(0) => \cr_int_reg[15]_i_39_n_7\, S(3) => \cr_int[15]_i_52_n_0\, S(2) => \cr_int[15]_i_53_n_0\, S(1) => \cr_int[15]_i_54_n_0\, S(0) => \cr_int[15]_i_55_n_0\ ); \cr_int_reg[19]_i_37\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_39_n_0\, CO(3) => \cr_int_reg[19]_i_37_n_0\, CO(2) => \cr_int_reg[19]_i_37_n_1\, CO(1) => \cr_int_reg[19]_i_37_n_2\, CO(0) => \cr_int_reg[19]_i_37_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[19]_i_37_n_4\, O(2) => \cr_int_reg[19]_i_37_n_5\, O(1) => \cr_int_reg[19]_i_37_n_6\, O(0) => \cr_int_reg[19]_i_37_n_7\, S(3) => \cr_int[19]_i_42_n_0\, S(2) => \cr_int[19]_i_43_n_0\, S(1) => \cr_int[19]_i_44_n_0\, S(0) => \cr_int[19]_i_45_n_0\ ); \cr_int_reg[23]_i_31\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[19]_i_37_n_0\, CO(3) => \cr_int_reg[23]_i_31_n_0\, CO(2) => \cr_int_reg[23]_i_31_n_1\, CO(1) => \cr_int_reg[23]_i_31_n_2\, CO(0) => \cr_int_reg[23]_i_31_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[23]_i_31_n_4\, O(2) => \cr_int_reg[23]_i_31_n_5\, O(1) => \cr_int_reg[23]_i_31_n_6\, O(0) => \cr_int_reg[23]_i_31_n_7\, S(3) => \cr_int[23]_i_32_n_0\, S(2) => \cr_int[23]_i_33_n_0\, S(1) => \cr_int[23]_i_34_n_0\, S(0) => \cr_int[23]_i_35_n_0\ ); \cr_int_reg[31]_i_10\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_27_n_0\, CO(3) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(3), CO(2) => \cr_int_reg[31]_i_10_n_1\, CO(1) => \NLW_cr_int_reg[31]_i_10_CO_UNCONNECTED\(1), CO(0) => \cr_int_reg[31]_i_10_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[31]_i_10_n_6\, O(0) => \cr_int_reg[31]_i_10_n_7\, S(3 downto 2) => B"01", S(1) => \cr_int[31]_i_28_n_0\, S(0) => \cr_int[31]_i_29_n_0\ ); \cr_int_reg[31]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[31]_i_64_n_0\, CO(3) => \cr_int_reg[31]_i_27_n_0\, CO(2) => \cr_int_reg[31]_i_27_n_1\, CO(1) => \cr_int_reg[31]_i_27_n_2\, CO(0) => \cr_int_reg[31]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[31]_i_27_n_4\, O(2) => \cr_int_reg[31]_i_27_n_5\, O(1) => \cr_int_reg[31]_i_27_n_6\, O(0) => \cr_int_reg[31]_i_27_n_7\, S(3) => \cr_int[31]_i_65_n_0\, S(2) => \cr_int[31]_i_66_n_0\, S(1) => \cr_int[31]_i_67_n_0\, S(0) => \cr_int[31]_i_68_n_0\ ); \cr_int_reg[31]_i_54\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[23]_i_31_n_0\, CO(3 downto 1) => \NLW_cr_int_reg[31]_i_54_CO_UNCONNECTED\(3 downto 1), CO(0) => \cr_int_reg[31]_i_54_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_cr_int_reg[31]_i_54_O_UNCONNECTED\(3 downto 2), O(1) => \cr_int_reg[31]_i_54_n_6\, O(0) => \cr_int_reg[31]_i_54_n_7\, S(3 downto 2) => B"00", S(1) => \cr_int[31]_i_98_n_0\, S(0) => \cr_int[31]_i_99_n_0\ ); \cr_int_reg[31]_i_64\: unisim.vcomponents.CARRY4 port map ( CI => \cr_int_reg[15]_i_37_n_0\, CO(3) => \cr_int_reg[31]_i_64_n_0\, CO(2) => \cr_int_reg[31]_i_64_n_1\, CO(1) => \cr_int_reg[31]_i_64_n_2\, CO(0) => \cr_int_reg[31]_i_64_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[31]_i_64_n_4\, O(2) => \cr_int_reg[31]_i_64_n_5\, O(1) => \cr_int_reg[31]_i_64_n_6\, O(0) => \cr_int_reg[31]_i_64_n_7\, S(3) => \cr_int[31]_i_104_n_0\, S(2) => \cr_int[31]_i_105_n_0\, S(1) => \cr_int[31]_i_106_n_0\, S(0) => \cr_int[31]_i_107_n_0\ ); \cr_int_reg[7]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \cr_int_reg[7]_i_24_n_0\, CO(2) => \cr_int_reg[7]_i_24_n_1\, CO(1) => \cr_int_reg[7]_i_24_n_2\, CO(0) => \cr_int_reg[7]_i_24_n_3\, CYINIT => \cr_int[7]_i_29_n_0\, DI(3 downto 0) => B"0000", O(3) => \cr_int_reg[7]_i_24_n_4\, O(2) => \cr_int_reg[7]_i_24_n_5\, O(1) => \cr_int_reg[7]_i_24_n_6\, O(0) => \cr_int_reg[7]_i_24_n_7\, S(3) => \cr_int[7]_i_30_n_0\, S(2) => \cr_int[7]_i_31_n_0\, S(1) => \cr_int[7]_i_32_n_0\, S(0) => \cr_int[7]_i_33_n_0\ ); \y_int[11]_i_54\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[11]_i_54_n_0\ ); \y_int[11]_i_55\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_6\, O => \y_int[11]_i_55_n_0\ ); \y_int[11]_i_56\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_7\, O => \y_int[11]_i_56_n_0\ ); \y_int[11]_i_57\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_21_n_4\, O => \y_int[11]_i_57_n_0\ ); \y_int[15]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[15]_i_36_n_0\ ); \y_int[15]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[15]_i_37_n_0\ ); \y_int[15]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[15]_i_38_n_0\ ); \y_int[15]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[15]_i_39_n_0\ ); \y_int[15]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_68, O => \y_int[15]_i_44_n_0\ ); \y_int[15]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_69, O => \y_int[15]_i_45_n_0\ ); \y_int[15]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_70, O => \y_int[15]_i_46_n_0\ ); \y_int[15]_i_47\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_71, O => \y_int[15]_i_47_n_0\ ); \y_int[19]_i_36\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[19]_i_36_n_0\ ); \y_int[19]_i_37\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[19]_i_37_n_0\ ); \y_int[19]_i_38\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[19]_i_38_n_0\ ); \y_int[19]_i_39\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[19]_i_39_n_0\ ); \y_int[19]_i_40\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[19]_i_24_n_5\, O => \y_int[19]_i_40_n_0\ ); \y_int[19]_i_41\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[19]_i_24_n_6\, O => \y_int[19]_i_41_n_0\ ); \y_int[19]_i_42\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[19]_i_24_n_7\, O => \y_int[19]_i_42_n_0\ ); \y_int[19]_i_43\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[15]_i_24_n_4\, O => \y_int[19]_i_43_n_0\ ); \y_int[19]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_64, O => \y_int[19]_i_44_n_0\ ); \y_int[19]_i_45\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_65, O => \y_int[19]_i_45_n_0\ ); \y_int[19]_i_46\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_66, O => \y_int[19]_i_46_n_0\ ); \y_int[19]_i_47\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_67, O => \y_int[19]_i_47_n_0\ ); \y_int[23]_i_50\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_50_n_0\ ); \y_int[23]_i_58\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_58_n_0\ ); \y_int[23]_i_59\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_59_n_0\ ); \y_int[23]_i_60\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_60_n_0\ ); \y_int[23]_i_61\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, O => \y_int[23]_i_61_n_0\ ); \y_int[31]_i_100\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => rgb888(3), I1 => rgb888(1), I2 => rgb888(4), I3 => rgb888(2), O => \y_int[31]_i_100_n_0\ ); \y_int[31]_i_102\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \y_int[31]_i_102_n_0\ ); \y_int[31]_i_103\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(15), I1 => rgb888(14), O => \y_int[31]_i_103_n_0\ ); \y_int[31]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(15), I1 => \y_int[31]_i_56_n_0\, O => \y_int[31]_i_22_n_0\ ); \y_int[31]_i_23\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => rgb888(15), I1 => \y_int[31]_i_57_n_0\, I2 => rgb888(14), O => \y_int[31]_i_23_n_0\ ); \y_int[31]_i_24\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => rgb888(15), I1 => \y_int[31]_i_56_n_0\, O => \y_int[31]_i_24_n_0\ ); \y_int[31]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(15), O => \y_int[31]_i_25_n_0\ ); \y_int[31]_i_26\: unisim.vcomponents.LUT3 generic map( INIT => X"15" ) port map ( I0 => rgb888(15), I1 => rgb888(14), I2 => \y_int[31]_i_57_n_0\, O => \y_int[31]_i_26_n_0\ ); \y_int[31]_i_28\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_32_n_7\, O => \y_int[31]_i_28_n_0\ ); \y_int[31]_i_29\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_35_n_4\, O => \y_int[31]_i_29_n_0\ ); \y_int[31]_i_38\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_58, O => \y_int[31]_i_38_n_0\ ); \y_int[31]_i_39\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_59, O => \y_int[31]_i_39_n_0\ ); \y_int[31]_i_48\: unisim.vcomponents.LUT4 generic map( INIT => X"1002" ) port map ( I0 => rgb888(14), I1 => rgb888(15), I2 => \y_int[31]_i_80_n_0\, I3 => rgb888(13), O => \y_int[31]_i_48_n_0\ ); \y_int[31]_i_49\: unisim.vcomponents.LUT5 generic map( INIT => X"81560042" ) port map ( I0 => rgb888(13), I1 => rgb888(12), I2 => \y_int[31]_i_81_n_0\, I3 => rgb888(15), I4 => \y_int_reg[31]_i_82_n_1\, O => \y_int[31]_i_49_n_0\ ); \y_int[31]_i_50\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A88A80808008" ) port map ( I0 => \y_int[31]_i_83_n_0\, I1 => rgb888(14), I2 => rgb888(11), I3 => rgb888(9), I4 => rgb888(10), I5 => \y_int_reg[31]_i_82_n_6\, O => \y_int[31]_i_50_n_0\ ); \y_int[31]_i_51\: unisim.vcomponents.LUT6 generic map( INIT => X"9696966996000069" ) port map ( I0 => rgb888(14), I1 => rgb888(11), I2 => \y_int_reg[31]_i_82_n_6\, I3 => rgb888(9), I4 => rgb888(10), I5 => rgb888(13), O => \y_int[31]_i_51_n_0\ ); \y_int[31]_i_52\: unisim.vcomponents.LUT4 generic map( INIT => X"6559" ) port map ( I0 => \y_int[31]_i_48_n_0\, I1 => rgb888(15), I2 => \y_int[31]_i_57_n_0\, I3 => rgb888(14), O => \y_int[31]_i_52_n_0\ ); \y_int[31]_i_53\: unisim.vcomponents.LUT6 generic map( INIT => X"6CCCCCC9CCCCC993" ) port map ( I0 => \y_int_reg[31]_i_82_n_1\, I1 => rgb888(14), I2 => rgb888(12), I3 => \y_int[31]_i_81_n_0\, I4 => rgb888(13), I5 => rgb888(15), O => \y_int[31]_i_53_n_0\ ); \y_int[31]_i_54\: unisim.vcomponents.LUT6 generic map( INIT => X"366C6CC96CC9C993" ) port map ( I0 => \y_int[31]_i_84_n_0\, I1 => rgb888(13), I2 => \y_int[31]_i_81_n_0\, I3 => rgb888(12), I4 => rgb888(15), I5 => \y_int_reg[31]_i_82_n_1\, O => \y_int[31]_i_54_n_0\ ); \y_int[31]_i_55\: unisim.vcomponents.LUT5 generic map( INIT => X"99969666" ) port map ( I0 => \y_int[31]_i_51_n_0\, I1 => \y_int[31]_i_83_n_0\, I2 => \y_int_reg[31]_i_82_n_6\, I3 => \y_int[31]_i_85_n_0\, I4 => rgb888(14), O => \y_int[31]_i_55_n_0\ ); \y_int[31]_i_56\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => rgb888(13), I1 => rgb888(11), I2 => rgb888(9), I3 => rgb888(10), I4 => rgb888(12), I5 => rgb888(14), O => \y_int[31]_i_56_n_0\ ); \y_int[31]_i_57\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => rgb888(12), I1 => rgb888(10), I2 => rgb888(9), I3 => rgb888(11), I4 => rgb888(13), O => \y_int[31]_i_57_n_0\ ); \y_int[31]_i_58\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_35_n_5\, O => \y_int[31]_i_58_n_0\ ); \y_int[31]_i_59\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_35_n_6\, O => \y_int[31]_i_59_n_0\ ); \y_int[31]_i_60\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[23]_i_35_n_7\, O => \y_int[31]_i_60_n_0\ ); \y_int[31]_i_61\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => \y_int_reg[31]_i_9_n_5\, I1 => U0_n_57, I2 => \y_int_reg[19]_i_24_n_4\, O => \y_int[31]_i_61_n_0\ ); \y_int[31]_i_72\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(5), I1 => rgb888(7), O => \y_int[31]_i_72_n_0\ ); \y_int[31]_i_73\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(6), I1 => rgb888(7), O => \y_int[31]_i_73_n_0\ ); \y_int[31]_i_74\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => rgb888(7), I1 => rgb888(5), I2 => rgb888(6), O => \y_int[31]_i_74_n_0\ ); \y_int[31]_i_76\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_60, O => \y_int[31]_i_76_n_0\ ); \y_int[31]_i_77\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_61, O => \y_int[31]_i_77_n_0\ ); \y_int[31]_i_78\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_62, O => \y_int[31]_i_78_n_0\ ); \y_int[31]_i_79\: unisim.vcomponents.LUT3 generic map( INIT => X"47" ) port map ( I0 => U0_n_55, I1 => U0_n_56, I2 => U0_n_63, O => \y_int[31]_i_79_n_0\ ); \y_int[31]_i_80\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => rgb888(11), I1 => rgb888(9), I2 => rgb888(10), I3 => rgb888(12), O => \y_int[31]_i_80_n_0\ ); \y_int[31]_i_81\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => rgb888(10), I1 => rgb888(9), I2 => rgb888(11), O => \y_int[31]_i_81_n_0\ ); \y_int[31]_i_83\: unisim.vcomponents.LUT6 generic map( INIT => X"6666666999999996" ) port map ( I0 => \y_int_reg[31]_i_82_n_1\, I1 => rgb888(15), I2 => rgb888(11), I3 => rgb888(9), I4 => rgb888(10), I5 => rgb888(12), O => \y_int[31]_i_83_n_0\ ); \y_int[31]_i_84\: unisim.vcomponents.LUT5 generic map( INIT => X"FEABA802" ) port map ( I0 => \y_int_reg[31]_i_82_n_6\, I1 => rgb888(10), I2 => rgb888(9), I3 => rgb888(11), I4 => rgb888(14), O => \y_int[31]_i_84_n_0\ ); \y_int[31]_i_85\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => rgb888(10), I1 => rgb888(9), I2 => rgb888(11), O => \y_int[31]_i_85_n_0\ ); \y_int[31]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(4), I1 => rgb888(6), O => \y_int[31]_i_93_n_0\ ); \y_int[31]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(3), I1 => rgb888(5), O => \y_int[31]_i_94_n_0\ ); \y_int[31]_i_95\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(2), I1 => rgb888(4), O => \y_int[31]_i_95_n_0\ ); \y_int[31]_i_96\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rgb888(1), I1 => rgb888(3), O => \y_int[31]_i_96_n_0\ ); \y_int[31]_i_97\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => rgb888(6), I1 => rgb888(4), I2 => rgb888(7), I3 => rgb888(5), O => \y_int[31]_i_97_n_0\ ); \y_int[31]_i_98\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => rgb888(5), I1 => rgb888(3), I2 => rgb888(6), I3 => rgb888(4), O => \y_int[31]_i_98_n_0\ ); \y_int[31]_i_99\: unisim.vcomponents.LUT4 generic map( INIT => X"D22D" ) port map ( I0 => rgb888(4), I1 => rgb888(2), I2 => rgb888(5), I3 => rgb888(3), O => \y_int[31]_i_99_n_0\ ); \y_int[3]_i_37\: unisim.vcomponents.LUT4 generic map( INIT => X"8228" ) port map ( I0 => \y_int_reg[31]_i_82_n_7\, I1 => rgb888(9), I2 => rgb888(10), I3 => rgb888(13), O => \y_int[3]_i_37_n_0\ ); \y_int[3]_i_38\: unisim.vcomponents.LUT4 generic map( INIT => X"6996" ) port map ( I0 => rgb888(9), I1 => rgb888(10), I2 => rgb888(13), I3 => \y_int_reg[31]_i_82_n_7\, O => \y_int[3]_i_38_n_0\ ); \y_int[3]_i_39\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \y_int_reg[3]_i_40_n_4\, I1 => rgb888(9), I2 => rgb888(12), O => \y_int[3]_i_39_n_0\ ); \y_int[3]_i_41\: unisim.vcomponents.LUT5 generic map( INIT => X"99969699" ) port map ( I0 => \y_int[3]_i_37_n_0\, I1 => \y_int[3]_i_79_n_0\, I2 => rgb888(13), I3 => rgb888(10), I4 => rgb888(9), O => \y_int[3]_i_41_n_0\ ); \y_int[3]_i_42\: unisim.vcomponents.LUT6 generic map( INIT => X"9669696969696996" ) port map ( I0 => \y_int_reg[31]_i_82_n_7\, I1 => rgb888(13), I2 => rgb888(10), I3 => rgb888(12), I4 => \y_int_reg[3]_i_40_n_4\, I5 => rgb888(9), O => \y_int[3]_i_42_n_0\ ); \y_int[3]_i_43\: unisim.vcomponents.LUT5 generic map( INIT => X"96696969" ) port map ( I0 => rgb888(12), I1 => rgb888(9), I2 => \y_int_reg[3]_i_40_n_4\, I3 => rgb888(11), I4 => rgb888(8), O => \y_int[3]_i_43_n_0\ ); \y_int[3]_i_44\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => rgb888(8), I1 => rgb888(11), I2 => \y_int_reg[3]_i_40_n_5\, O => \y_int[3]_i_44_n_0\ ); \y_int[3]_i_46\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_19_n_5\, O => \y_int[3]_i_46_n_0\ ); \y_int[3]_i_47\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_19_n_6\, O => \y_int[3]_i_47_n_0\ ); \y_int[3]_i_48\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_19_n_7\, O => \y_int[3]_i_48_n_0\ ); \y_int[3]_i_49\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_51, O => \y_int[3]_i_49_n_0\ ); \y_int[3]_i_75\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => rgb888(15), I1 => rgb888(13), O => \y_int[3]_i_75_n_0\ ); \y_int[3]_i_76\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(12), I1 => rgb888(14), O => \y_int[3]_i_76_n_0\ ); \y_int[3]_i_77\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(11), I1 => rgb888(13), O => \y_int[3]_i_77_n_0\ ); \y_int[3]_i_78\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(10), I1 => rgb888(12), O => \y_int[3]_i_78_n_0\ ); \y_int[3]_i_79\: unisim.vcomponents.LUT5 generic map( INIT => X"A95656A9" ) port map ( I0 => \y_int_reg[31]_i_82_n_6\, I1 => rgb888(10), I2 => rgb888(9), I3 => rgb888(11), I4 => rgb888(14), O => \y_int[3]_i_79_n_0\ ); \y_int[3]_i_80\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_52, O => \y_int[3]_i_80_n_0\ ); \y_int[3]_i_81\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_53, O => \y_int[3]_i_81_n_0\ ); \y_int[3]_i_82\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => U0_n_54, O => \y_int[3]_i_82_n_0\ ); \y_int[3]_i_83\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_70_n_6\, O => \y_int[3]_i_83_n_0\ ); \y_int[3]_i_93\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(9), I1 => rgb888(11), O => \y_int[3]_i_93_n_0\ ); \y_int[3]_i_94\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => rgb888(8), I1 => rgb888(10), O => \y_int[3]_i_94_n_0\ ); \y_int[3]_i_95\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => rgb888(9), O => \y_int[3]_i_95_n_0\ ); \y_int[3]_i_96\: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => rgb888(8), O => \y_int[3]_i_96_n_0\ ); \y_int[7]_i_25\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_21_n_5\, O => \y_int[7]_i_25_n_0\ ); \y_int[7]_i_26\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_21_n_6\, O => \y_int[7]_i_26_n_0\ ); \y_int[7]_i_27\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[31]_i_21_n_7\, O => \y_int[7]_i_27_n_0\ ); \y_int[7]_i_28\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \y_int_reg[3]_i_19_n_4\, O => \y_int[7]_i_28_n_0\ ); \y_int_reg[11]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[7]_i_23_n_0\, CO(3) => \y_int_reg[11]_i_27_n_0\, CO(2) => \y_int_reg[11]_i_27_n_1\, CO(1) => \y_int_reg[11]_i_27_n_2\, CO(0) => \y_int_reg[11]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[11]_i_27_n_4\, O(2) => \y_int_reg[11]_i_27_n_5\, O(1) => \y_int_reg[11]_i_27_n_6\, O(0) => \y_int_reg[11]_i_27_n_7\, S(3) => \y_int[11]_i_54_n_0\, S(2) => \y_int[11]_i_55_n_0\, S(1) => \y_int[11]_i_56_n_0\, S(0) => \y_int[11]_i_57_n_0\ ); \y_int_reg[15]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[11]_i_27_n_0\, CO(3) => \y_int_reg[15]_i_24_n_0\, CO(2) => \y_int_reg[15]_i_24_n_1\, CO(1) => \y_int_reg[15]_i_24_n_2\, CO(0) => \y_int_reg[15]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[15]_i_24_n_4\, O(2) => \y_int_reg[15]_i_24_n_5\, O(1) => \y_int_reg[15]_i_24_n_6\, O(0) => \y_int_reg[15]_i_24_n_7\, S(3) => \y_int[15]_i_36_n_0\, S(2) => \y_int[15]_i_37_n_0\, S(1) => \y_int[15]_i_38_n_0\, S(0) => \y_int[15]_i_39_n_0\ ); \y_int_reg[15]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_81, CO(3) => \y_int_reg[15]_i_34_n_0\, CO(2) => \y_int_reg[15]_i_34_n_1\, CO(1) => \y_int_reg[15]_i_34_n_2\, CO(0) => \y_int_reg[15]_i_34_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(12 downto 9), S(3) => \y_int[15]_i_44_n_0\, S(2) => \y_int[15]_i_45_n_0\, S(1) => \y_int[15]_i_46_n_0\, S(0) => \y_int[15]_i_47_n_0\ ); \y_int_reg[19]_i_24\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_24_n_0\, CO(3) => \y_int_reg[19]_i_24_n_0\, CO(2) => \y_int_reg[19]_i_24_n_1\, CO(1) => \y_int_reg[19]_i_24_n_2\, CO(0) => \y_int_reg[19]_i_24_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[19]_i_24_n_4\, O(2) => \y_int_reg[19]_i_24_n_5\, O(1) => \y_int_reg[19]_i_24_n_6\, O(0) => \y_int_reg[19]_i_24_n_7\, S(3) => \y_int[19]_i_36_n_0\, S(2) => \y_int[19]_i_37_n_0\, S(1) => \y_int[19]_i_38_n_0\, S(0) => \y_int[19]_i_39_n_0\ ); \y_int_reg[19]_i_33\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_79, CO(3) => \y_int_reg[19]_i_33_n_0\, CO(2) => \y_int_reg[19]_i_33_n_1\, CO(1) => \y_int_reg[19]_i_33_n_2\, CO(0) => \y_int_reg[19]_i_33_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[19]_i_33_n_4\, O(2) => \y_int_reg[19]_i_33_n_5\, O(1) => \y_int_reg[19]_i_33_n_6\, O(0) => \y_int_reg[19]_i_33_n_7\, S(3) => \y_int[19]_i_40_n_0\, S(2) => \y_int[19]_i_41_n_0\, S(1) => \y_int[19]_i_42_n_0\, S(0) => \y_int[19]_i_43_n_0\ ); \y_int_reg[19]_i_34\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[15]_i_34_n_0\, CO(3) => \y_int_reg[19]_i_34_n_0\, CO(2) => \y_int_reg[19]_i_34_n_1\, CO(1) => \y_int_reg[19]_i_34_n_2\, CO(0) => \y_int_reg[19]_i_34_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(16 downto 13), S(3) => \y_int[19]_i_44_n_0\, S(2) => \y_int[19]_i_45_n_0\, S(1) => \y_int[19]_i_46_n_0\, S(0) => \y_int[19]_i_47_n_0\ ); \y_int_reg[23]_i_32\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[23]_i_35_n_0\, CO(3 downto 0) => \NLW_y_int_reg[23]_i_32_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_y_int_reg[23]_i_32_O_UNCONNECTED\(3 downto 1), O(0) => \y_int_reg[23]_i_32_n_7\, S(3 downto 1) => B"000", S(0) => \y_int[23]_i_50_n_0\ ); \y_int_reg[23]_i_35\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_24_n_0\, CO(3) => \y_int_reg[23]_i_35_n_0\, CO(2) => \y_int_reg[23]_i_35_n_1\, CO(1) => \y_int_reg[23]_i_35_n_2\, CO(0) => \y_int_reg[23]_i_35_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[23]_i_35_n_4\, O(2) => \y_int_reg[23]_i_35_n_5\, O(1) => \y_int_reg[23]_i_35_n_6\, O(0) => \y_int_reg[23]_i_35_n_7\, S(3) => \y_int[23]_i_58_n_0\, S(2) => \y_int[23]_i_59_n_0\, S(1) => \y_int[23]_i_60_n_0\, S(0) => \y_int[23]_i_61_n_0\ ); \y_int_reg[31]_i_10\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_27_n_0\, CO(3) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_10_n_1\, CO(1) => \NLW_y_int_reg[31]_i_10_CO_UNCONNECTED\(1), CO(0) => \y_int_reg[31]_i_10_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[31]_i_10_O_UNCONNECTED\(3 downto 2), O(1) => \y_int_reg[31]_i_10_n_6\, O(0) => \y_int_reg[31]_i_10_n_7\, S(3 downto 2) => B"01", S(1) => \y_int[31]_i_28_n_0\, S(0) => \y_int[31]_i_29_n_0\ ); \y_int_reg[31]_i_12\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_37_n_0\, CO(3) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_12_n_1\, CO(1) => \NLW_y_int_reg[31]_i_12_CO_UNCONNECTED\(1), CO(0) => \y_int_reg[31]_i_12_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_y_int_reg[31]_i_12_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => y_int_reg2(22 downto 21), S(3 downto 2) => B"01", S(1) => \y_int[31]_i_38_n_0\, S(0) => \y_int[31]_i_39_n_0\ ); \y_int_reg[31]_i_21\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_19_n_0\, CO(3) => \y_int_reg[31]_i_21_n_0\, CO(2) => \y_int_reg[31]_i_21_n_1\, CO(1) => \y_int_reg[31]_i_21_n_2\, CO(0) => \y_int_reg[31]_i_21_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_48_n_0\, DI(2) => \y_int[31]_i_49_n_0\, DI(1) => \y_int[31]_i_50_n_0\, DI(0) => \y_int[31]_i_51_n_0\, O(3) => \y_int_reg[31]_i_21_n_4\, O(2) => \y_int_reg[31]_i_21_n_5\, O(1) => \y_int_reg[31]_i_21_n_6\, O(0) => \y_int_reg[31]_i_21_n_7\, S(3) => \y_int[31]_i_52_n_0\, S(2) => \y_int[31]_i_53_n_0\, S(1) => \y_int[31]_i_54_n_0\, S(0) => \y_int[31]_i_55_n_0\ ); \y_int_reg[31]_i_27\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_33_n_0\, CO(3) => \y_int_reg[31]_i_27_n_0\, CO(2) => \y_int_reg[31]_i_27_n_1\, CO(1) => \y_int_reg[31]_i_27_n_2\, CO(0) => \y_int_reg[31]_i_27_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[31]_i_27_n_4\, O(2) => \y_int_reg[31]_i_27_n_5\, O(1) => \y_int_reg[31]_i_27_n_6\, O(0) => \y_int_reg[31]_i_27_n_7\, S(3) => \y_int[31]_i_58_n_0\, S(2) => \y_int[31]_i_59_n_0\, S(1) => \y_int[31]_i_60_n_0\, S(0) => \y_int[31]_i_61_n_0\ ); \y_int_reg[31]_i_31\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_71_n_0\, CO(3 downto 2) => \NLW_y_int_reg[31]_i_31_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[31]_i_31_n_2\, CO(0) => \y_int_reg[31]_i_31_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => rgb888(6), DI(0) => \y_int[31]_i_72_n_0\, O(3) => \NLW_y_int_reg[31]_i_31_O_UNCONNECTED\(3), O(2) => \y_int_reg[31]_i_31_n_5\, O(1) => \y_int_reg[31]_i_31_n_6\, O(0) => \y_int_reg[31]_i_31_n_7\, S(3 downto 2) => B"01", S(1) => \y_int[31]_i_73_n_0\, S(0) => \y_int[31]_i_74_n_0\ ); \y_int_reg[31]_i_37\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[19]_i_34_n_0\, CO(3) => \y_int_reg[31]_i_37_n_0\, CO(2) => \y_int_reg[31]_i_37_n_1\, CO(1) => \y_int_reg[31]_i_37_n_2\, CO(0) => \y_int_reg[31]_i_37_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => y_int_reg2(20 downto 17), S(3) => \y_int[31]_i_76_n_0\, S(2) => \y_int[31]_i_77_n_0\, S(1) => \y_int[31]_i_78_n_0\, S(0) => \y_int[31]_i_79_n_0\ ); \y_int_reg[31]_i_71\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_80, CO(3) => \y_int_reg[31]_i_71_n_0\, CO(2) => \y_int_reg[31]_i_71_n_1\, CO(1) => \y_int_reg[31]_i_71_n_2\, CO(0) => \y_int_reg[31]_i_71_n_3\, CYINIT => '0', DI(3) => \y_int[31]_i_93_n_0\, DI(2) => \y_int[31]_i_94_n_0\, DI(1) => \y_int[31]_i_95_n_0\, DI(0) => \y_int[31]_i_96_n_0\, O(3) => \y_int_reg[31]_i_71_n_4\, O(2) => \y_int_reg[31]_i_71_n_5\, O(1) => \y_int_reg[31]_i_71_n_6\, O(0) => \y_int_reg[31]_i_71_n_7\, S(3) => \y_int[31]_i_97_n_0\, S(2) => \y_int[31]_i_98_n_0\, S(1) => \y_int[31]_i_99_n_0\, S(0) => \y_int[31]_i_100_n_0\ ); \y_int_reg[31]_i_82\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_40_n_0\, CO(3) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(3), CO(2) => \y_int_reg[31]_i_82_n_1\, CO(1) => \NLW_y_int_reg[31]_i_82_CO_UNCONNECTED\(1), CO(0) => \y_int_reg[31]_i_82_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1 downto 0) => rgb888(15 downto 14), O(3 downto 2) => \NLW_y_int_reg[31]_i_82_O_UNCONNECTED\(3 downto 2), O(1) => \y_int_reg[31]_i_82_n_6\, O(0) => \y_int_reg[31]_i_82_n_7\, S(3 downto 2) => B"01", S(1) => \y_int[31]_i_102_n_0\, S(0) => \y_int[31]_i_103_n_0\ ); \y_int_reg[31]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[31]_i_21_n_0\, CO(3 downto 2) => \NLW_y_int_reg[31]_i_9_CO_UNCONNECTED\(3 downto 2), CO(1) => \y_int_reg[31]_i_9_n_2\, CO(0) => \y_int_reg[31]_i_9_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \y_int[31]_i_22_n_0\, DI(0) => \y_int[31]_i_23_n_0\, O(3) => \NLW_y_int_reg[31]_i_9_O_UNCONNECTED\(3), O(2) => \y_int_reg[31]_i_9_n_5\, O(1) => \y_int_reg[31]_i_9_n_6\, O(0) => \y_int_reg[31]_i_9_n_7\, S(3) => '0', S(2) => \y_int[31]_i_24_n_0\, S(1) => \y_int[31]_i_25_n_0\, S(0) => \y_int[31]_i_26_n_0\ ); \y_int_reg[3]_i_19\: unisim.vcomponents.CARRY4 port map ( CI => U0_n_78, CO(3) => \y_int_reg[3]_i_19_n_0\, CO(2) => \y_int_reg[3]_i_19_n_1\, CO(1) => \y_int_reg[3]_i_19_n_2\, CO(0) => \y_int_reg[3]_i_19_n_3\, CYINIT => '0', DI(3) => \y_int[3]_i_37_n_0\, DI(2) => \y_int[3]_i_38_n_0\, DI(1) => \y_int[3]_i_39_n_0\, DI(0) => \y_int_reg[3]_i_40_n_5\, O(3) => \y_int_reg[3]_i_19_n_4\, O(2) => \y_int_reg[3]_i_19_n_5\, O(1) => \y_int_reg[3]_i_19_n_6\, O(0) => \y_int_reg[3]_i_19_n_7\, S(3) => \y_int[3]_i_41_n_0\, S(2) => \y_int[3]_i_42_n_0\, S(1) => \y_int[3]_i_43_n_0\, S(0) => \y_int[3]_i_44_n_0\ ); \y_int_reg[3]_i_20\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_45_n_0\, CO(3) => \y_int_reg[3]_i_20_n_0\, CO(2) => \y_int_reg[3]_i_20_n_1\, CO(1) => \y_int_reg[3]_i_20_n_2\, CO(0) => \y_int_reg[3]_i_20_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[3]_i_20_n_4\, O(2) => \y_int_reg[3]_i_20_n_5\, O(1 downto 0) => \NLW_y_int_reg[3]_i_20_O_UNCONNECTED\(1 downto 0), S(3) => \y_int[3]_i_46_n_0\, S(2) => \y_int[3]_i_47_n_0\, S(1) => \y_int[3]_i_48_n_0\, S(0) => \y_int[3]_i_49_n_0\ ); \y_int_reg[3]_i_40\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_70_n_0\, CO(3) => \y_int_reg[3]_i_40_n_0\, CO(2) => \y_int_reg[3]_i_40_n_1\, CO(1) => \y_int_reg[3]_i_40_n_2\, CO(0) => \y_int_reg[3]_i_40_n_3\, CYINIT => '0', DI(3) => rgb888(15), DI(2 downto 0) => rgb888(12 downto 10), O(3) => \y_int_reg[3]_i_40_n_4\, O(2) => \y_int_reg[3]_i_40_n_5\, O(1) => \y_int_reg[3]_i_40_n_6\, O(0) => \y_int_reg[3]_i_40_n_7\, S(3) => \y_int[3]_i_75_n_0\, S(2) => \y_int[3]_i_76_n_0\, S(1) => \y_int[3]_i_77_n_0\, S(0) => \y_int[3]_i_78_n_0\ ); \y_int_reg[3]_i_45\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_45_n_0\, CO(2) => \y_int_reg[3]_i_45_n_1\, CO(1) => \y_int_reg[3]_i_45_n_2\, CO(0) => \y_int_reg[3]_i_45_n_3\, CYINIT => \cb_int[3]_i_84_n_0\, DI(3 downto 0) => B"0000", O(3 downto 0) => \NLW_y_int_reg[3]_i_45_O_UNCONNECTED\(3 downto 0), S(3) => \y_int[3]_i_80_n_0\, S(2) => \y_int[3]_i_81_n_0\, S(1) => \y_int[3]_i_82_n_0\, S(0) => \y_int[3]_i_83_n_0\ ); \y_int_reg[3]_i_70\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \y_int_reg[3]_i_70_n_0\, CO(2) => \y_int_reg[3]_i_70_n_1\, CO(1) => \y_int_reg[3]_i_70_n_2\, CO(0) => \y_int_reg[3]_i_70_n_3\, CYINIT => '0', DI(3 downto 2) => rgb888(9 downto 8), DI(1 downto 0) => B"01", O(3) => \y_int_reg[3]_i_70_n_4\, O(2) => \y_int_reg[3]_i_70_n_5\, O(1) => \y_int_reg[3]_i_70_n_6\, O(0) => \NLW_y_int_reg[3]_i_70_O_UNCONNECTED\(0), S(3) => \y_int[3]_i_93_n_0\, S(2) => \y_int[3]_i_94_n_0\, S(1) => \y_int[3]_i_95_n_0\, S(0) => \y_int[3]_i_96_n_0\ ); \y_int_reg[7]_i_23\: unisim.vcomponents.CARRY4 port map ( CI => \y_int_reg[3]_i_20_n_0\, CO(3) => \y_int_reg[7]_i_23_n_0\, CO(2) => \y_int_reg[7]_i_23_n_1\, CO(1) => \y_int_reg[7]_i_23_n_2\, CO(0) => \y_int_reg[7]_i_23_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \y_int_reg[7]_i_23_n_4\, O(2) => \y_int_reg[7]_i_23_n_5\, O(1) => \y_int_reg[7]_i_23_n_6\, O(0) => \y_int_reg[7]_i_23_n_7\, S(3) => \y_int[7]_i_25_n_0\, S(2) => \y_int[7]_i_26_n_0\, S(1) => \y_int[7]_i_27_n_0\, S(0) => \y_int[7]_i_28_n_0\ ); end STRUCTURE;

mit

5bc8dc83af012c539e3a80902cbec615

0.480129

2.23181

false

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_util_ds_buf_1_0/sim/system_util_ds_buf_1_0.vhd

1

5,806

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:util_ds_buf:2.1 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY util_ds_buf_v2_01_a; USE util_ds_buf_v2_01_a.util_ds_buf; ENTITY system_util_ds_buf_1_0 IS PORT ( BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END system_util_ds_buf_1_0; ARCHITECTURE system_util_ds_buf_1_0_arch OF system_util_ds_buf_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_ds_buf_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT util_ds_buf IS GENERIC ( C_BUF_TYPE : STRING; C_SIZE : INTEGER ); PORT ( IBUF_DS_P : IN STD_LOGIC_VECTOR(0 DOWNTO 0); IBUF_DS_N : IN STD_LOGIC_VECTOR(0 DOWNTO 0); IBUF_OUT : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); IBUF_DS_ODIV2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); OBUF_IN : IN STD_LOGIC_VECTOR(0 DOWNTO 0); OBUF_DS_P : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); OBUF_DS_N : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_DS_P : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_DS_N : INOUT STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_IO_T : IN STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_IO_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); IOBUF_IO_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFGCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFGCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFGCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFH_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFH_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFHCE_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFHCE_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFHCE_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_CEMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_CLR : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_CLRMASK : IN STD_LOGIC_VECTOR(0 DOWNTO 0); BUFG_GT_DIV : IN STD_LOGIC_VECTOR(2 DOWNTO 0); BUFG_GT_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT util_ds_buf; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF BUFG_I: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_I CLK"; ATTRIBUTE X_INTERFACE_INFO OF BUFG_O: SIGNAL IS "xilinx.com:signal:clock:1.0 BUFG_O CLK"; BEGIN U0 : util_ds_buf GENERIC MAP ( C_BUF_TYPE => "BUFG", C_SIZE => 1 ) PORT MAP ( IBUF_DS_P => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), IBUF_DS_N => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), OBUF_IN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), IOBUF_IO_T => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), IOBUF_IO_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_I => BUFG_I, BUFG_O => BUFG_O, BUFGCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFGCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFH_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFHCE_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFHCE_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_I => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_CE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_CEMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_CLR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_CLRMASK => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), BUFG_GT_DIV => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)) ); END system_util_ds_buf_1_0_arch;

mit

5053240f1b435396b002343bfe430f46

0.680331

3.356069

false

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl

1

10,123

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Thu May 25 21:06:44 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl -- Design : system_ov7670_vga_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_ov7670_vga_0_0_ov7670_vga is port ( rgb : out STD_LOGIC_VECTOR ( 15 downto 0 ); active : in STD_LOGIC; clk_x2 : in STD_LOGIC; data : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_ov7670_vga_0_0_ov7670_vga : entity is "ov7670_vga"; end system_ov7670_vga_0_0_ov7670_vga; architecture STRUCTURE of system_ov7670_vga_0_0_ov7670_vga is signal cycle : STD_LOGIC; signal \data_pair[15]_i_1_n_0\ : STD_LOGIC; signal \data_pair[7]_i_1_n_0\ : STD_LOGIC; signal \data_pair_reg_n_0_[0]\ : STD_LOGIC; signal \data_pair_reg_n_0_[10]\ : STD_LOGIC; signal \data_pair_reg_n_0_[11]\ : STD_LOGIC; signal \data_pair_reg_n_0_[12]\ : STD_LOGIC; signal \data_pair_reg_n_0_[13]\ : STD_LOGIC; signal \data_pair_reg_n_0_[14]\ : STD_LOGIC; signal \data_pair_reg_n_0_[15]\ : STD_LOGIC; signal \data_pair_reg_n_0_[1]\ : STD_LOGIC; signal \data_pair_reg_n_0_[2]\ : STD_LOGIC; signal \data_pair_reg_n_0_[3]\ : STD_LOGIC; signal \data_pair_reg_n_0_[4]\ : STD_LOGIC; signal \data_pair_reg_n_0_[5]\ : STD_LOGIC; signal \data_pair_reg_n_0_[6]\ : STD_LOGIC; signal \data_pair_reg_n_0_[7]\ : STD_LOGIC; signal \data_pair_reg_n_0_[8]\ : STD_LOGIC; signal \data_pair_reg_n_0_[9]\ : STD_LOGIC; signal rgb_regn_0_0 : STD_LOGIC; begin cycle_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_x2, CE => '1', D => \data_pair[7]_i_1_n_0\, Q => cycle, R => '0' ); \data_pair[15]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => cycle, I1 => active, O => \data_pair[15]_i_1_n_0\ ); \data_pair[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => active, I1 => cycle, O => \data_pair[7]_i_1_n_0\ ); \data_pair_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(0), Q => \data_pair_reg_n_0_[0]\, R => '0' ); \data_pair_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(2), Q => \data_pair_reg_n_0_[10]\, R => '0' ); \data_pair_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(3), Q => \data_pair_reg_n_0_[11]\, R => '0' ); \data_pair_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(4), Q => \data_pair_reg_n_0_[12]\, R => '0' ); \data_pair_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(5), Q => \data_pair_reg_n_0_[13]\, R => '0' ); \data_pair_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(6), Q => \data_pair_reg_n_0_[14]\, R => '0' ); \data_pair_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(7), Q => \data_pair_reg_n_0_[15]\, R => '0' ); \data_pair_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(1), Q => \data_pair_reg_n_0_[1]\, R => '0' ); \data_pair_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(2), Q => \data_pair_reg_n_0_[2]\, R => '0' ); \data_pair_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(3), Q => \data_pair_reg_n_0_[3]\, R => '0' ); \data_pair_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(4), Q => \data_pair_reg_n_0_[4]\, R => '0' ); \data_pair_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(5), Q => \data_pair_reg_n_0_[5]\, R => '0' ); \data_pair_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(6), Q => \data_pair_reg_n_0_[6]\, R => '0' ); \data_pair_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[7]_i_1_n_0\, D => data(7), Q => \data_pair_reg_n_0_[7]\, R => '0' ); \data_pair_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(0), Q => \data_pair_reg_n_0_[8]\, R => '0' ); \data_pair_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk_x2, CE => \data_pair[15]_i_1_n_0\, D => data(1), Q => \data_pair_reg_n_0_[9]\, R => '0' ); \rgb_reg[0]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[0]\, Q => rgb(0), R => '0' ); \rgb_reg[10]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[10]\, Q => rgb(10), R => '0' ); \rgb_reg[11]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[11]\, Q => rgb(11), R => '0' ); \rgb_reg[12]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[12]\, Q => rgb(12), R => '0' ); \rgb_reg[13]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[13]\, Q => rgb(13), R => '0' ); \rgb_reg[14]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[14]\, Q => rgb(14), R => '0' ); \rgb_reg[15]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[15]\, Q => rgb(15), R => '0' ); \rgb_reg[1]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[1]\, Q => rgb(1), R => '0' ); \rgb_reg[2]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[2]\, Q => rgb(2), R => '0' ); \rgb_reg[3]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[3]\, Q => rgb(3), R => '0' ); \rgb_reg[4]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[4]\, Q => rgb(4), R => '0' ); \rgb_reg[5]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[5]\, Q => rgb(5), R => '0' ); \rgb_reg[6]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[6]\, Q => rgb(6), R => '0' ); \rgb_reg[7]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[7]\, Q => rgb(7), R => '0' ); \rgb_reg[8]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[8]\, Q => rgb(8), R => '0' ); \rgb_reg[9]\: unisim.vcomponents.FDRE port map ( C => rgb_regn_0_0, CE => cycle, D => \data_pair_reg_n_0_[9]\, Q => rgb(9), R => '0' ); rgb_regi_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => clk_x2, O => rgb_regn_0_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_ov7670_vga_0_0 is port ( clk_x2 : in STD_LOGIC; active : in STD_LOGIC; data : in STD_LOGIC_VECTOR ( 7 downto 0 ); rgb : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_ov7670_vga_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_ov7670_vga_0_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_ov7670_vga_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_ov7670_vga_0_0 : entity is "ov7670_vga,Vivado 2016.4"; end system_ov7670_vga_0_0; architecture STRUCTURE of system_ov7670_vga_0_0 is begin U0: entity work.system_ov7670_vga_0_0_ov7670_vga port map ( active => active, clk_x2 => clk_x2, data(7 downto 0) => data(7 downto 0), rgb(15 downto 0) => rgb(15 downto 0) ); end STRUCTURE;

mit

7fb98e94afb35836da219f74a8f65606

0.506569

2.785636

false

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_buffer_register_1_0/system_buffer_register_1_0_sim_netlist.vhdl

1

7,575

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Sun Jun 04 17:33:00 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top system_buffer_register_1_0 -prefix -- system_buffer_register_1_0_ system_buffer_register_0_0_sim_netlist.vhdl -- Design : system_buffer_register_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_buffer_register_1_0_buffer_register is port ( val_out : out STD_LOGIC_VECTOR ( 31 downto 0 ); val_in : in STD_LOGIC_VECTOR ( 31 downto 0 ); clk : in STD_LOGIC ); end system_buffer_register_1_0_buffer_register; architecture STRUCTURE of system_buffer_register_1_0_buffer_register is begin \val_out_reg[0]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(0), Q => val_out(0), R => '0' ); \val_out_reg[10]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(10), Q => val_out(10), R => '0' ); \val_out_reg[11]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(11), Q => val_out(11), R => '0' ); \val_out_reg[12]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(12), Q => val_out(12), R => '0' ); \val_out_reg[13]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(13), Q => val_out(13), R => '0' ); \val_out_reg[14]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(14), Q => val_out(14), R => '0' ); \val_out_reg[15]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(15), Q => val_out(15), R => '0' ); \val_out_reg[16]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(16), Q => val_out(16), R => '0' ); \val_out_reg[17]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(17), Q => val_out(17), R => '0' ); \val_out_reg[18]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(18), Q => val_out(18), R => '0' ); \val_out_reg[19]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(19), Q => val_out(19), R => '0' ); \val_out_reg[1]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(1), Q => val_out(1), R => '0' ); \val_out_reg[20]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(20), Q => val_out(20), R => '0' ); \val_out_reg[21]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(21), Q => val_out(21), R => '0' ); \val_out_reg[22]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(22), Q => val_out(22), R => '0' ); \val_out_reg[23]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(23), Q => val_out(23), R => '0' ); \val_out_reg[24]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(24), Q => val_out(24), R => '0' ); \val_out_reg[25]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(25), Q => val_out(25), R => '0' ); \val_out_reg[26]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(26), Q => val_out(26), R => '0' ); \val_out_reg[27]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(27), Q => val_out(27), R => '0' ); \val_out_reg[28]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(28), Q => val_out(28), R => '0' ); \val_out_reg[29]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(29), Q => val_out(29), R => '0' ); \val_out_reg[2]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(2), Q => val_out(2), R => '0' ); \val_out_reg[30]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(30), Q => val_out(30), R => '0' ); \val_out_reg[31]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(31), Q => val_out(31), R => '0' ); \val_out_reg[3]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(3), Q => val_out(3), R => '0' ); \val_out_reg[4]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(4), Q => val_out(4), R => '0' ); \val_out_reg[5]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(5), Q => val_out(5), R => '0' ); \val_out_reg[6]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(6), Q => val_out(6), R => '0' ); \val_out_reg[7]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(7), Q => val_out(7), R => '0' ); \val_out_reg[8]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(8), Q => val_out(8), R => '0' ); \val_out_reg[9]\: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => val_in(9), Q => val_out(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_buffer_register_1_0 is port ( clk : in STD_LOGIC; val_in : in STD_LOGIC_VECTOR ( 31 downto 0 ); val_out : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_buffer_register_1_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_buffer_register_1_0 : entity is "system_buffer_register_0_0,buffer_register,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_buffer_register_1_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_buffer_register_1_0 : entity is "buffer_register,Vivado 2016.4"; end system_buffer_register_1_0; architecture STRUCTURE of system_buffer_register_1_0 is begin U0: entity work.system_buffer_register_1_0_buffer_register port map ( clk => clk, val_in(31 downto 0) => val_in(31 downto 0), val_out(31 downto 0) => val_out(31 downto 0) ); end STRUCTURE;

mit

93a42abdb21ab09c4dcf4ee3d1cdc502

0.486865

3.101966

false

loa-org/loa-hdl

modules/signalprocessing/hdl/goertzel_pipelined_v2.vhd

2

5,089

------------------------------------------------------------------------------- -- Title : Goertzel Algorithm pipelined with BRAM -- Project : ------------------------------------------------------------------------------- -- File : goertzel_pipelined_v2.vhd -- Author : strongly-typed -- Created : 2012-04-24 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: -- -- ToDos : The throughput can be increased by: -- i) Reduce steps in pipeline -- ii) Do not wait to put a new value into the pipeline until the -- last result was processed. Alternate reading and writing to -- the BRAM. Need to store the address of the the data -- currently in progress. ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.signalprocessing_pkg.all; entity goertzel_pipelined_v2 is generic ( FREQUENCIES : positive; CHANNELS : positive := 12; SAMPLES : positive := 250; Q : positive := 13); port ( start_p : in std_logic; bram_addr_p : out std_logic_vector(7 downto 0); bram_data_i : in std_logic_vector(35 downto 0); bram_data_o : out std_logic_vector(35 downto 0); bram_we_p : out std_logic; ready_p : out std_logic; enable_p : in std_logic; coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0); inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0); clk : in std_logic); end entity goertzel_pipelined_v2; architecture structural of goertzel_pipelined_v2 is signal start_s : std_logic := '0'; -- select signals of muxes signal mux_delay1_s : std_logic := '0'; signal mux_delay2_s : std_logic := '0'; signal mux_coef_s : natural range FREQUENCIES-1 downto 0 := 0; signal mux_input_s : natural range CHANNELS-1 downto 0 := 0; -- outputs of the muxes signal muxed_delay1_s : goertzel_data_type := (others => '0'); signal muxed_delay2_s : goertzel_data_type := (others => '0'); signal muxed_coef_s : goertzel_coef_type := (others => '0'); signal muxed_input_s : goertzel_input_type := (others => '0'); -- inter-instance routing signal bram_data_i_s : goertzel_result_type := (others => (others => '0')); signal goertzel_result_to_bram_s : goertzel_result_type := (others => (others => '0')); signal pipeline_input_s : goertzel_result_type := (others => (others => '0')); begin -- architecture structural start_s <= start_p; pipeline_input_s(0) <= muxed_delay1_s; pipeline_input_s(1) <= muxed_delay2_s; -- map generic std_logic_vector(35 downto 0) form bram -- to strongly-tyed goertzel_result_type of pipeline -- |35 ---- 18||17 ------ 0| BRAM -- |--delay2--||--delay1--|| pipeline bram_data_i_s(0) <= signed(bram_data_i(17 downto 0)); bram_data_i_s(1) <= signed(bram_data_i(35 downto 18)); -- from pipeline to bram bram_data_o <= std_logic_vector(goertzel_result_to_bram_s(1)) & std_logic_vector(goertzel_result_to_bram_s(0)); -- muxes to multiplex one of the channels to the pipeline goertzel_muxes_1 : entity work.goertzel_muxes generic map ( CHANNELS => CHANNELS, FREQUENCIES => FREQUENCIES) port map ( mux_delay1_p => mux_delay1_s, mux_delay2_p => mux_delay2_s, mux_coef => mux_coef_s, mux_input => mux_input_s, bram_data => bram_data_i_s, coefs_p => coefs_p, inputs_p => inputs_p, delay1_p => muxed_delay1_s, delay2_p => muxed_delay2_s, coef_p => muxed_coef_s, input_p => muxed_input_s); -- control the pipeline goertzel_control_unit_1 : entity work.goertzel_control_unit generic map ( SAMPLES => SAMPLES, FREQUENCIES => FREQUENCIES, CHANNELS => CHANNELS) port map ( start_p => start_s, ready_p => ready_p, -- output to the bram bram_addr_p => bram_addr_p, bram_we_p => bram_we_p, -- outputs to the mux mux_delay1_p => mux_delay1_s, mux_delay2_p => mux_delay2_s, mux_coef_p => mux_coef_s, mux_input_p => mux_input_s, clk => clk); -- the actual pipiline working on one frequency and on one channel goertzel_pipeline_1 : entity work.goertzel_pipeline generic map ( Q => Q) port map ( coef_p => muxed_coef_s, input_p => muxed_input_s, delay_p => pipeline_input_s, result_p => goertzel_result_to_bram_s, clk => clk); end architecture structural;

bsd-3-clause

f6089eaf5317dedad86604886703ea07

0.525251

3.586328

false

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_c_addsub_0_0/sim/system_c_addsub_0_0.vhd

1

5,365

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:c_addsub:12.0 -- IP Revision: 10 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY c_addsub_v12_0_10; USE c_addsub_v12_0_10.c_addsub_v12_0_10; ENTITY system_c_addsub_0_0 IS PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END system_c_addsub_0_0; ARCHITECTURE system_c_addsub_0_0_arch OF system_c_addsub_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_c_addsub_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT c_addsub_v12_0_10 IS GENERIC ( C_VERBOSITY : INTEGER; C_XDEVICEFAMILY : STRING; C_IMPLEMENTATION : INTEGER; C_A_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_OUT_WIDTH : INTEGER; C_CE_OVERRIDES_SCLR : INTEGER; C_A_TYPE : INTEGER; C_B_TYPE : INTEGER; C_LATENCY : INTEGER; C_ADD_MODE : INTEGER; C_B_CONSTANT : INTEGER; C_B_VALUE : STRING; C_AINIT_VAL : STRING; C_SINIT_VAL : STRING; C_CE_OVERRIDES_BYPASS : INTEGER; C_BYPASS_LOW : INTEGER; C_SCLR_OVERRIDES_SSET : INTEGER; C_HAS_C_IN : INTEGER; C_HAS_C_OUT : INTEGER; C_BORROW_LOW : INTEGER; C_HAS_CE : INTEGER; C_HAS_BYPASS : INTEGER; C_HAS_SCLR : INTEGER; C_HAS_SSET : INTEGER; C_HAS_SINIT : INTEGER ); PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLK : IN STD_LOGIC; ADD : IN STD_LOGIC; C_IN : IN STD_LOGIC; CE : IN STD_LOGIC; BYPASS : IN STD_LOGIC; SCLR : IN STD_LOGIC; SSET : IN STD_LOGIC; SINIT : IN STD_LOGIC; C_OUT : OUT STD_LOGIC; S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT c_addsub_v12_0_10; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA"; ATTRIBUTE X_INTERFACE_INFO OF S: SIGNAL IS "xilinx.com:signal:data:1.0 s_intf DATA"; BEGIN U0 : c_addsub_v12_0_10 GENERIC MAP ( C_VERBOSITY => 0, C_XDEVICEFAMILY => "zynq", C_IMPLEMENTATION => 0, C_A_WIDTH => 10, C_B_WIDTH => 10, C_OUT_WIDTH => 10, C_CE_OVERRIDES_SCLR => 0, C_A_TYPE => 0, C_B_TYPE => 0, C_LATENCY => 0, C_ADD_MODE => 0, C_B_CONSTANT => 0, C_B_VALUE => "0000000000", C_AINIT_VAL => "0", C_SINIT_VAL => "0", C_CE_OVERRIDES_BYPASS => 1, C_BYPASS_LOW => 0, C_SCLR_OVERRIDES_SSET => 1, C_HAS_C_IN => 0, C_HAS_C_OUT => 0, C_BORROW_LOW => 1, C_HAS_CE => 0, C_HAS_BYPASS => 0, C_HAS_SCLR => 0, C_HAS_SSET => 0, C_HAS_SINIT => 0 ) PORT MAP ( A => A, B => B, CLK => '0', ADD => '1', C_IN => '0', CE => '1', BYPASS => '0', SCLR => '0', SSET => '0', SINIT => '0', S => S ); END system_c_addsub_0_0_arch;

mit

dd55901c45e5564c696234dd529fe45d

0.643616

3.479248

false

pgavin/carpe

hdl/tech/inferred/mul_pipe-rtl.vhdl

1

1,566

-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- architecture rtl of mul_pipe is begin mul : entity work.mul_pipe_inferred(rtl) generic map ( stages => stages, src1_bits => src1_bits, src2_bits => src2_bits ) port map ( clk => clk, rstn => rstn, unsgnd => unsgnd, src1 => src1, src2 => src2, result => result ); end;

apache-2.0

b9affe650de8447564bb3190844cdff6

0.476373

5.168317

false

loa-org/loa-hdl

modules/peripheral_register/tb/peripheral_register_tb.vhd

1

3,803

------------------------------------------------------------------------------- -- Title : Testbench for design "peripheral_register" ------------------------------------------------------------------------------- -- Author : Calle <calle@Alukiste> -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2011 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library std; use std.textio.all; library work; use work.bus_pkg.all; use work.reg_file_pkg.all; ------------------------------------------------------------------------------- entity peripheral_register_tb is end peripheral_register_tb; ------------------------------------------------------------------------------- architecture tb of peripheral_register_tb is -- component generics constant BASE_ADDRESS : positive := 16#0100#; -- component ports signal reg : std_logic_vector(15 downto 0) := (others => '0'); signal bus_o : busdevice_out_type; signal bus_i : busdevice_in_type := (addr => (others => '0'), data => (others => '0'), we => '0', re => '0'); signal clk : std_logic := '0'; signal reg_readback : std_logic_vector(15 downto 0); -- comments for the wave view of the testbench type comment_type is (idle, read_wrong_addr, read_correct_addr, write_wrong_addr, write_correct_addr, sequential_cycles); signal comment : comment_type := idle; begin reg_readback <= not reg; -- component instantiation DUT : peripheral_register generic map ( BASE_ADDRESS => BASE_ADDRESS) port map ( dout_p => reg, din_p => reg_readback, -- read back the written values bus_o => bus_o, bus_i => bus_i, reset => '0', clk => clk); -- clock generation clk <= not clk after 10 ns; waveform : process begin wait for 20 ns; -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); -- Read from correct address comment <= read_correct_addr; readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk); -- Write to wrong address comment <= write_wrong_addr; writeWord(addr => BASE_ADDRESS + 1, data => 16#affe#, bus_i => bus_i, clk => clk); -- Write to correct address comment <= write_correct_addr; writeWord(addr => BASE_ADDRESS, data => 16#54af#, bus_i => bus_i, clk => clk); -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); -- Read from correct address comment <= read_correct_addr; readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk); -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); wait until rising_edge(clk); -- generate two read cycles directly following each other comment <= sequential_cycles; bus_i.re <= '1'; wait until rising_edge(clk); wait until rising_edge(clk); bus_i.re <= '0'; wait until rising_edge(clk); bus_i.data <= x"4321"; bus_i.we <= '1'; wait until rising_edge(clk); bus_i.we <= '0'; wait until rising_edge(clk); bus_i.re <= '1'; wait until rising_edge(clk); bus_i.re <= '0'; end process waveform; end tb;

bsd-3-clause

426ec433e84c133af17fce663baab898

0.478833

4.24442

false

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/sim/system_ov7670_controller_1_0.vhd

2

3,747

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:ov7670_controller:1.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_ov7670_controller_1_0 IS PORT ( clk : IN STD_LOGIC; resend : IN STD_LOGIC; config_finished : OUT STD_LOGIC; sioc : OUT STD_LOGIC; siod : INOUT STD_LOGIC; reset : OUT STD_LOGIC; pwdn : OUT STD_LOGIC; xclk : OUT STD_LOGIC ); END system_ov7670_controller_1_0; ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT ov7670_controller IS PORT ( clk : IN STD_LOGIC; resend : IN STD_LOGIC; config_finished : OUT STD_LOGIC; sioc : OUT STD_LOGIC; siod : INOUT STD_LOGIC; reset : OUT STD_LOGIC; pwdn : OUT STD_LOGIC; xclk : OUT STD_LOGIC ); END COMPONENT ov7670_controller; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST"; BEGIN U0 : ov7670_controller PORT MAP ( clk => clk, resend => resend, config_finished => config_finished, sioc => sioc, siod => siod, reset => reset, pwdn => pwdn, xclk => xclk ); END system_ov7670_controller_1_0_arch;

mit

3a6e86a241014057e31609a2d83f2d0f

0.721911

4.037716

false

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl

1

4,177

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Sun Jun 04 14:48:58 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top system_vga_pll_0_0 -prefix -- system_vga_pll_0_0_ system_vga_pll_0_0_sim_netlist.vhdl -- Design : system_vga_pll_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_vga_pll_0_0_vga_pll is port ( clk_50 : out STD_LOGIC; clk_25 : out STD_LOGIC; clk_12_5 : out STD_LOGIC; clk_6_25 : out STD_LOGIC; clk_100 : in STD_LOGIC ); end system_vga_pll_0_0_vga_pll; architecture STRUCTURE of system_vga_pll_0_0_vga_pll is signal \^clk_12_5\ : STD_LOGIC; signal clk_12_5_s_i_1_n_0 : STD_LOGIC; signal \^clk_25\ : STD_LOGIC; signal clk_25_s_i_1_n_0 : STD_LOGIC; signal \^clk_50\ : STD_LOGIC; signal \^clk_6_25\ : STD_LOGIC; signal clk_6_25_s_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; begin clk_12_5 <= \^clk_12_5\; clk_25 <= \^clk_25\; clk_50 <= \^clk_50\; clk_6_25 <= \^clk_6_25\; clk_12_5_s_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^clk_12_5\, O => clk_12_5_s_i_1_n_0 ); clk_12_5_s_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \^clk_25\, CE => '1', D => clk_12_5_s_i_1_n_0, Q => \^clk_12_5\, R => '0' ); clk_25_s_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^clk_25\, O => clk_25_s_i_1_n_0 ); clk_25_s_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \^clk_50\, CE => '1', D => clk_25_s_i_1_n_0, Q => \^clk_25\, R => '0' ); clk_50_s_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^clk_50\, O => p_0_in ); clk_50_s_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_100, CE => '1', D => p_0_in, Q => \^clk_50\, R => '0' ); clk_6_25_s_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^clk_6_25\, O => clk_6_25_s_i_1_n_0 ); clk_6_25_s_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \^clk_6_25\, CE => '1', D => clk_6_25_s_i_1_n_0, Q => \^clk_6_25\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_vga_pll_0_0 is port ( clk_100 : in STD_LOGIC; clk_50 : out STD_LOGIC; clk_25 : out STD_LOGIC; clk_12_5 : out STD_LOGIC; clk_6_25 : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4"; end system_vga_pll_0_0; architecture STRUCTURE of system_vga_pll_0_0 is begin U0: entity work.system_vga_pll_0_0_vga_pll port map ( clk_100 => clk_100, clk_12_5 => clk_12_5, clk_25 => clk_25, clk_50 => clk_50, clk_6_25 => clk_6_25 ); end STRUCTURE;

mit

535e7d159a568a2394c3893ae83aafdd

0.546804

2.931228

false

loa-org/loa-hdl

modules/encoder/hdl/encoder_hall_sensor_module.vhd

2

3,209

------------------------------------------------------------------------------- -- Title : Hall Sensor Encoder Module -- Project : Loa ------------------------------------------------------------------------------- -- Platform : Spartan 3 ------------------------------------------------------------------------------- -- Description: Connectes a hall sensor encoder with a 16-bit counter to -- the internal bus system. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.bus_pkg.all; use work.encoder_module_pkg.all; use work.motor_control_pkg.all; use work.hall_sensor_decoder_pkg.all; use work.up_down_counter_pkg.all; ------------------------------------------------------------------------------- entity encoder_hall_sensor_module is generic ( BASE_ADDRESS : integer range 0 to 16#7FFF# ); port ( hall_sensor_p : in hall_sensor_type; -- counter, set to '0' if not used load_p : in std_logic; -- Save the current encoder value in a -- buffer register bus_o : out busdevice_out_type; bus_i : in busdevice_in_type; clk : in std_logic ); end encoder_hall_sensor_module; ------------------------------------------------------------------------------- architecture behavioral of encoder_hall_sensor_module is type encoder_hall_sensor_module_type is record counter : std_logic_vector(15 downto 0); data_out : std_logic_vector(15 downto 0); end record; signal r, rin : encoder_hall_sensor_module_type := (data_out => (others => '0'), counter => (others => '0')); signal step : std_logic := '0'; signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down) signal decode_error : std_logic; -- Decoding Error, currently not used signal counter : std_logic_vector(15 downto 0); begin seq_proc : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process seq_proc; comb_proc : process(bus_i, counter, load_p, r) variable v : encoder_hall_sensor_module_type; begin v := r; v.data_out := (others => '0'); -- Load counter into own buffer if load_p = '1' then v.counter := counter; end if; -- Check Bus Address if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then if bus_i.we = '1' then -- TODO elsif bus_i.re = '1' then v.data_out := r.counter; end if; end if; rin <= v; end process comb_proc; bus_o.data <= r.data_out; decoder : hall_sensor_decoder port map ( hall_sensor_p => hall_sensor_p, step_p => step, dir_p => up_down, error_p => decode_error, clk => clk); up_down_counter_1 : up_down_counter generic map ( WIDTH => 16) port map ( clk_en_p => step, up_down_p => up_down, value_p => counter, reset => '0', clk => clk); end behavioral;

bsd-3-clause

d2061eb9dbb28767338d628b3daa318d

0.48364

3.976456

false