Datasets:
AWfaw
/
ai-hdlcoder-dataset-clean

Dataset card Data Studio Files Community
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jeremiah-c-leary/vhdl-style-guide
vsg/tests/generic/rule_013_test_input.fixed.vhd
1
260
entity FIFO is generic ( G_WIDTH : integer := 256; G_DEPTH : integer := 32 ); end entity FIFO; -- Violation below entity FIFO is GENERIC( g_size : integer := 10; g_width : integer := 256; g_depth : integer := 32 ); end entity FIFO;
gpl-3.0
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cwilkens/ecen4024-microphone-array
microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/add_sub.vhd
2
15,965
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block WozsSiCuDSL9GZFA8ln/YjSjPxpX909dMjTfz6RmgNot0x7PzppV6ZBneX0XbgIfbQp+NTb1DBQd b7gNKkgv2w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bPkIF2PoFBURUMfnRqidLvbsYogAd15OU9IRwxsjlKRGKB7m4hCaNUvBNJ6iIp5tzUJJUCwYZglI fQJRojdmqiuu7JrOHOiLIW3568EcpWE5vhsk7flGfmoPmjdAKHV3x6gbConRUB/vynFBl9koZeNw 3Dy9MpLHjhnDs7WyNjE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit
7e32f99f2b86729030dfa81a7de35f30
0.938929
1.868344
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/concurrent/rule_006_test_input_smart_tabs.fixed_indent_4.vhd
1
214
architecture RTL of FIFO is begin a <= b; a <= when c = '0' else '1'; block_label: block is begin a <= b; a <= c; end block; a <= b; a <= when c = '0' else '1'; end architecture RTL;
gpl-3.0
339d49ba160b0caea0bc0b4374a23c1a
0.504673
2.431818
false
false
false
false
spzSource/MPFSM.RegFile.Sort
MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/Reg.vhd
1
755
library ieee; use ieee.std_logic_1164.all; entity REGn is generic(INITIAL : std_logic_vector := "00000000"); port( data_input : in std_logic_vector(INITIAL'range); enabled : in std_logic; init : in std_logic; clk : in std_logic; output_enabled : in std_logic; data_output : out std_logic_vector(INITIAL'range)); end REGn; architecture beh_regn of REGn is signal reg : std_logic_vector(INITIAL'range); begin MAIN : process(data_input, enabled, init, clk) begin if init = '1' then reg <= INITIAL; elsif enabled = '1' then if rising_edge(clk) then reg <= data_input; end if; end if; end process; data_output <= reg when output_enabled = '0' else (others => 'Z'); end beh_regn;
mit
a4fbdc76f1be346ce6f34d6adcd60991
0.638411
2.926357
false
false
false
false
Yarr/Yarr-fw
syn/kintex7/rd53_ohio_16x1_640Mbps/board_pkg.vhd
1
953
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library work; use work.hw_type_pkg.all; package board_pkg is constant c_FW_IDENT : std_logic_vector(31 downto 0) := c_HW_IDENT & x"030232"; constant c_TX_ENCODING : string := "OSERDES"; constant c_TX_CHANNELS : integer := 4; constant c_RX_CHANNELS : integer := 16; constant c_FE_TYPE : string := "RD53"; constant c_RX_NUM_LANES : integer := 1; constant c_RX_SPEED : string := "0640"; constant c_TX_IDLE_WORD : std_logic_vector(31 downto 0) := x"AAAAAAAA"; constant c_TX_SYNC_WORD : std_logic_vector(31 downto 0) := x"817e817e"; constant c_TX_SYNC_INTERVAL : unsigned(7 downto 0) := to_unsigned(16,8); constant c_TX_AZ_WORD : std_logic_vector(31 downto 0) := x"00000000"; constant c_TX_AZ_INTERVAL : unsigned(15 downto 0) := to_unsigned(500,16); constant c_TX_40_DIVIDER : unsigned(3 downto 0) := to_unsigned(4,4); end board_pkg;
gpl-3.0
ac655dedf3aeea0335c0ca6b7fda08c0
0.665268
3.006309
false
false
false
false
zcold/fft.vhdl
src/cmul.vhdl
1
3,091
-- The MIT License (MIT) -- Copyright (c) 2014 Shuo Li -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- The above copyright notice and this permission notice shall be included in all -- copies or substantial portions of the Software. -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -- SOFTWARE. ------------------------- -- complex multiplication ------------------------- -- Description -- This design unit `cmul` is for multiply two complex fixed point numbers with -- configurable data width. The value of the inputs are limited to (+1, -1]. The -- MSB is sign bit and the rest bits are all for decimal part. -- library declaration for Cadence, not for Modelsim library ieee_proposed; use ieee_proposed.fixed_float_types.all; use ieee_proposed.fixed_pkg.all; entity cmul is generic ( -- same data width is used for the real and imaginary component data_width : integer range 0 to 128 := 16 ); port ( -- input a input_a_re : in sfixed (0 downto 1 - data_width); input_a_im : in sfixed (0 downto 1 - data_width); -- input b input_b_re : in sfixed (0 downto 1 - data_width); input_b_im : in sfixed (0 downto 1 - data_width); -- output output_re : out sfixed(0 downto 1 - data_width); output_im : out sfixed(0 downto 1 - data_width) ); end cmul; -- Function Implementation 0 architecture FIMP_0 of cmul is -- internal signals with short names -- input a = a + b * j -- input b = x + y * j signal a, b, x, y : sfixed (0 downto 1 - data_width); -- output = re + im * j -- cropping is required signal re, im : sfixed(2 downto 2 - 2 * data_width); begin -- input a = a + b * j a <= input_a_re; b <= input_a_im; -- input b = x + y * j x <= input_b_re; y <= input_b_im; -- output real part -- a * x - b * y re <= (a * x) - (b * y); -- output imaginary part -- a * y + b * x im <= (a * y) + (b * x); -- crop the outputs to fit with data width output_re(0) <= re(2); output_re(-1 downto 1 - data_width) <= re(-1 downto 1 - data_width); output_im(0) <= im(2); output_im(-1 downto 1 - data_width) <= im(-1 downto 1 - data_width); end FIMP_0;
mit
b9f018ff860902ec8d881cd3a9d823ce
0.634423
3.78799
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/if_statement/rule_028_test_input.vhd
1
566
architecture RTL of FIFO is begin process begin if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; else if x = '1' then z <= '0'; elsif x = '0' then z <= '1'; else z <= 'Z'; end if; end if; -- Violations below if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; else if x = '1' then z <= '0'; elsif x = '0' then z <= '1'; else z <= 'Z'; END if; END if; end process; end architecture RTL;
gpl-3.0
f10285fe587ca4fd41881bb51db55cbd
0.379859
3.19774
false
false
false
false
Yarr/Yarr-fw
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd
2
35,790
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.9 -- \ \ Application : MIG -- / / Filename : ddr3_ctrl_spec_bank3_64b_32b.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- --Device : Spartan-6 --Design Name : DDR/DDR2/DDR3/LPDDR --Purpose : This is the design top level. which instantiates top wrapper, -- test bench top and infrastructure modules. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; entity ddr3_ctrl_spec_bank3_64b_32b is generic ( C3_P0_MASK_SIZE : integer := 8; C3_P0_DATA_PORT_SIZE : integer := 64; C3_P1_MASK_SIZE : integer := 4; C3_P1_DATA_PORT_SIZE : integer := 32; C3_MEMCLK_PERIOD : integer := 3000; -- Memory data transfer clock period. C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset. C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED. C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic. C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design. DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls. C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN. C3_NUM_DQ_PINS : integer := 16; -- External memory data width. C3_MEM_ADDR_WIDTH : integer := 14; -- External memory address width. C3_MEM_BANKADDR_WIDTH : integer := 3 -- External memory bank address width. ); port ( mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_reset_n : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_dram_udm : out std_logic; c3_sys_clk : in std_logic; c3_sys_rst_i : in std_logic; c3_calib_done : out std_logic; c3_clk0 : out std_logic; c3_rst0 : out std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; c3_p0_cmd_clk : in std_logic; c3_p0_cmd_en : in std_logic; c3_p0_cmd_instr : in std_logic_vector(2 downto 0); c3_p0_cmd_bl : in std_logic_vector(5 downto 0); c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0); c3_p0_cmd_empty : out std_logic; c3_p0_cmd_full : out std_logic; c3_p0_wr_clk : in std_logic; c3_p0_wr_en : in std_logic; c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0); c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0); c3_p0_wr_full : out std_logic; c3_p0_wr_empty : out std_logic; c3_p0_wr_count : out std_logic_vector(6 downto 0); c3_p0_wr_underrun : out std_logic; c3_p0_wr_error : out std_logic; c3_p0_rd_clk : in std_logic; c3_p0_rd_en : in std_logic; c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0); c3_p0_rd_full : out std_logic; c3_p0_rd_empty : out std_logic; c3_p0_rd_count : out std_logic_vector(6 downto 0); c3_p0_rd_overflow : out std_logic; c3_p0_rd_error : out std_logic; c3_p1_cmd_clk : in std_logic; c3_p1_cmd_en : in std_logic; c3_p1_cmd_instr : in std_logic_vector(2 downto 0); c3_p1_cmd_bl : in std_logic_vector(5 downto 0); c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0); c3_p1_cmd_empty : out std_logic; c3_p1_cmd_full : out std_logic; c3_p1_wr_clk : in std_logic; c3_p1_wr_en : in std_logic; c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0); c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0); c3_p1_wr_full : out std_logic; c3_p1_wr_empty : out std_logic; c3_p1_wr_count : out std_logic_vector(6 downto 0); c3_p1_wr_underrun : out std_logic; c3_p1_wr_error : out std_logic; c3_p1_rd_clk : in std_logic; c3_p1_rd_en : in std_logic; c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0); c3_p1_rd_full : out std_logic; c3_p1_rd_empty : out std_logic; c3_p1_rd_count : out std_logic_vector(6 downto 0); c3_p1_rd_overflow : out std_logic; c3_p1_rd_error : out std_logic ); end ddr3_ctrl_spec_bank3_64b_32b; architecture arc of ddr3_ctrl_spec_bank3_64b_32b is component memc3_infrastructure is generic ( C_RST_ACT_LOW : integer; C_INPUT_CLK_TYPE : string; C_CLKOUT0_DIVIDE : integer; C_CLKOUT1_DIVIDE : integer; C_CLKOUT2_DIVIDE : integer; C_CLKOUT3_DIVIDE : integer; C_CLKFBOUT_MULT : integer; C_DIVCLK_DIVIDE : integer; C_INCLK_PERIOD : integer ); port ( sys_clk_p : in std_logic; sys_clk_n : in std_logic; sys_clk : in std_logic; sys_rst_i : in std_logic; clk0 : out std_logic; rst0 : out std_logic; async_rst : out std_logic; sysclk_2x : out std_logic; sysclk_2x_180 : out std_logic; pll_ce_0 : out std_logic; pll_ce_90 : out std_logic; pll_lock : out std_logic; mcb_drp_clk : out std_logic ); end component; component memc3_wrapper is generic ( C_MEMCLK_PERIOD : integer; C_CALIB_SOFT_IP : string; C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_ARB_NUM_TIME_SLOTS : integer; C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0); C_MEM_TRAS : integer; C_MEM_TRCD : integer; C_MEM_TREFI : integer; C_MEM_TRFC : integer; C_MEM_TRP : integer; C_MEM_TWR : integer; C_MEM_TRTP : integer; C_MEM_TWTR : integer; C_MEM_ADDR_ORDER : string; C_NUM_DQ_PINS : integer; C_MEM_TYPE : string; C_MEM_DENSITY : string; C_MEM_BURST_LEN : integer; C_MEM_CAS_LATENCY : integer; C_MEM_ADDR_WIDTH : integer; C_MEM_BANKADDR_WIDTH : integer; C_MEM_NUM_COL_BITS : integer; C_MEM_DDR1_2_ODS : string; C_MEM_DDR2_RTT : string; C_MEM_DDR2_DIFF_DQS_EN : string; C_MEM_DDR2_3_PA_SR : string; C_MEM_DDR2_3_HIGH_TEMP_SR : string; C_MEM_DDR3_CAS_LATENCY : integer; C_MEM_DDR3_ODS : string; C_MEM_DDR3_RTT : string; C_MEM_DDR3_CAS_WR_LATENCY : integer; C_MEM_DDR3_AUTO_SR : string; C_MEM_MOBILE_PA_SR : string; C_MEM_MDDR_ODS : string; C_MC_CALIB_BYPASS : string; C_MC_CALIBRATION_MODE : string; C_MC_CALIBRATION_DELAY : string; C_SKIP_IN_TERM_CAL : integer; C_SKIP_DYNAMIC_CAL : integer; C_LDQSP_TAP_DELAY_VAL : integer; C_LDQSN_TAP_DELAY_VAL : integer; C_UDQSP_TAP_DELAY_VAL : integer; C_UDQSN_TAP_DELAY_VAL : integer; C_DQ0_TAP_DELAY_VAL : integer; C_DQ1_TAP_DELAY_VAL : integer; C_DQ2_TAP_DELAY_VAL : integer; C_DQ3_TAP_DELAY_VAL : integer; C_DQ4_TAP_DELAY_VAL : integer; C_DQ5_TAP_DELAY_VAL : integer; C_DQ6_TAP_DELAY_VAL : integer; C_DQ7_TAP_DELAY_VAL : integer; C_DQ8_TAP_DELAY_VAL : integer; C_DQ9_TAP_DELAY_VAL : integer; C_DQ10_TAP_DELAY_VAL : integer; C_DQ11_TAP_DELAY_VAL : integer; C_DQ12_TAP_DELAY_VAL : integer; C_DQ13_TAP_DELAY_VAL : integer; C_DQ14_TAP_DELAY_VAL : integer; C_DQ15_TAP_DELAY_VAL : integer ); port ( mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0); mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0); mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_reset_n : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_dram_udm : out std_logic; calib_done : out std_logic; async_rst : in std_logic; sysclk_2x : in std_logic; sysclk_2x_180 : in std_logic; pll_ce_0 : in std_logic; pll_ce_90 : in std_logic; pll_lock : in std_logic; mcb_drp_clk : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; p0_cmd_clk : in std_logic; p0_cmd_en : in std_logic; p0_cmd_instr : in std_logic_vector(2 downto 0); p0_cmd_bl : in std_logic_vector(5 downto 0); p0_cmd_byte_addr : in std_logic_vector(29 downto 0); p0_cmd_empty : out std_logic; p0_cmd_full : out std_logic; p0_wr_clk : in std_logic; p0_wr_en : in std_logic; p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0); p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); p0_wr_full : out std_logic; p0_wr_empty : out std_logic; p0_wr_count : out std_logic_vector(6 downto 0); p0_wr_underrun : out std_logic; p0_wr_error : out std_logic; p0_rd_clk : in std_logic; p0_rd_en : in std_logic; p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); p0_rd_full : out std_logic; p0_rd_empty : out std_logic; p0_rd_count : out std_logic_vector(6 downto 0); p0_rd_overflow : out std_logic; p0_rd_error : out std_logic; p1_cmd_clk : in std_logic; p1_cmd_en : in std_logic; p1_cmd_instr : in std_logic_vector(2 downto 0); p1_cmd_bl : in std_logic_vector(5 downto 0); p1_cmd_byte_addr : in std_logic_vector(29 downto 0); p1_cmd_empty : out std_logic; p1_cmd_full : out std_logic; p1_wr_clk : in std_logic; p1_wr_en : in std_logic; p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0); p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); p1_wr_full : out std_logic; p1_wr_empty : out std_logic; p1_wr_count : out std_logic_vector(6 downto 0); p1_wr_underrun : out std_logic; p1_wr_error : out std_logic; p1_rd_clk : in std_logic; p1_rd_en : in std_logic; p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); p1_rd_full : out std_logic; p1_rd_empty : out std_logic; p1_rd_count : out std_logic_vector(6 downto 0); p1_rd_overflow : out std_logic; p1_rd_error : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic ); end component; constant C3_CLKOUT0_DIVIDE : integer := 1; constant C3_CLKOUT1_DIVIDE : integer := 1; constant C3_CLKOUT2_DIVIDE : integer := 16; constant C3_CLKOUT3_DIVIDE : integer := 8; constant C3_CLKFBOUT_MULT : integer := 2; constant C3_DIVCLK_DIVIDE : integer := 1; constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); constant C3_ARB_NUM_TIME_SLOTS : integer := 12; constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"02"; constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"20"; constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"02"; constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"20"; constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"02"; constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"20"; constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"02"; constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"20"; constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"02"; constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"20"; constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"02"; constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"20"; constant C3_MEM_TRAS : integer := 36000; constant C3_MEM_TRCD : integer := 13500; constant C3_MEM_TREFI : integer := 7800000; constant C3_MEM_TRFC : integer := 160000; constant C3_MEM_TRP : integer := 13500; constant C3_MEM_TWR : integer := 15000; constant C3_MEM_TRTP : integer := 7500; constant C3_MEM_TWTR : integer := 7500; constant C3_MEM_TYPE : string := "DDR3"; constant C3_MEM_DENSITY : string := "2Gb"; constant C3_MEM_BURST_LEN : integer := 8; constant C3_MEM_CAS_LATENCY : integer := 6; constant C3_MEM_NUM_COL_BITS : integer := 10; constant C3_MEM_DDR1_2_ODS : string := "FULL"; constant C3_MEM_DDR2_RTT : string := "50OHMS"; constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES"; constant C3_MEM_DDR2_3_PA_SR : string := "FULL"; constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; constant C3_MEM_DDR3_CAS_LATENCY : integer := 6; constant C3_MEM_DDR3_ODS : string := "DIV6"; constant C3_MEM_DDR3_RTT : string := "DIV4"; constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5; constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED"; constant C3_MEM_MOBILE_PA_SR : string := "FULL"; constant C3_MEM_MDDR_ODS : string := "FULL"; constant C3_MC_CALIB_BYPASS : string := "NO"; constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION"; constant C3_MC_CALIBRATION_DELAY : string := "HALF"; constant C3_SKIP_IN_TERM_CAL : integer := 1; constant C3_SKIP_DYNAMIC_CAL : integer := 0; constant C3_LDQSP_TAP_DELAY_VAL : integer := 0; constant C3_LDQSN_TAP_DELAY_VAL : integer := 0; constant C3_UDQSP_TAP_DELAY_VAL : integer := 0; constant C3_UDQSN_TAP_DELAY_VAL : integer := 0; constant C3_DQ0_TAP_DELAY_VAL : integer := 0; constant C3_DQ1_TAP_DELAY_VAL : integer := 0; constant C3_DQ2_TAP_DELAY_VAL : integer := 0; constant C3_DQ3_TAP_DELAY_VAL : integer := 0; constant C3_DQ4_TAP_DELAY_VAL : integer := 0; constant C3_DQ5_TAP_DELAY_VAL : integer := 0; constant C3_DQ6_TAP_DELAY_VAL : integer := 0; constant C3_DQ7_TAP_DELAY_VAL : integer := 0; constant C3_DQ8_TAP_DELAY_VAL : integer := 0; constant C3_DQ9_TAP_DELAY_VAL : integer := 0; constant C3_DQ10_TAP_DELAY_VAL : integer := 0; constant C3_DQ11_TAP_DELAY_VAL : integer := 0; constant C3_DQ12_TAP_DELAY_VAL : integer := 0; constant C3_DQ13_TAP_DELAY_VAL : integer := 0; constant C3_DQ14_TAP_DELAY_VAL : integer := 0; constant C3_DQ15_TAP_DELAY_VAL : integer := 0; constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device -- as most of them cannot fit the complete example design when the -- Chip scope modules are enabled signal c3_sys_clk_p : std_logic; signal c3_sys_clk_n : std_logic; signal c3_async_rst : std_logic; signal c3_sysclk_2x : std_logic; signal c3_sysclk_2x_180 : std_logic; signal c3_pll_ce_0 : std_logic; signal c3_pll_ce_90 : std_logic; signal c3_pll_lock : std_logic; signal c3_mcb_drp_clk : std_logic; signal c3_cmp_error : std_logic; signal c3_cmp_data_valid : std_logic; signal c3_vio_modify_enable : std_logic; signal c3_error_status : std_logic_vector(191 downto 0); signal c3_vio_data_mode_value : std_logic_vector(2 downto 0); signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0); signal c3_cmp_data : std_logic_vector(31 downto 0); signal c3_selfrefresh_enter : std_logic; signal c3_selfrefresh_mode : std_logic; begin c3_sys_clk_p <= '0'; c3_sys_clk_n <= '0'; c3_selfrefresh_enter <= '0'; c3_selfrefresh_enter <= '0'; memc3_infrastructure_inst : memc3_infrastructure generic map ( C_RST_ACT_LOW => C3_RST_ACT_LOW, C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE, C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE, C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE, C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE, C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT, C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE, C_INCLK_PERIOD => C3_INCLK_PERIOD ) port map ( sys_clk_p => c3_sys_clk_p, sys_clk_n => c3_sys_clk_n, sys_clk => c3_sys_clk, sys_rst_i => c3_sys_rst_i, clk0 => c3_clk0, rst0 => c3_rst0, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk ); -- wrapper instantiation memc3_wrapper_inst : memc3_wrapper generic map ( C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP, C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS, C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0, C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1, C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2, C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3, C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4, C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5, C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6, C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7, C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8, C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9, C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10, C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11, C_MEM_TRAS => C3_MEM_TRAS, C_MEM_TRCD => C3_MEM_TRCD, C_MEM_TREFI => C3_MEM_TREFI, C_MEM_TRFC => C3_MEM_TRFC, C_MEM_TRP => C3_MEM_TRP, C_MEM_TWR => C3_MEM_TWR, C_MEM_TRTP => C3_MEM_TRTP, C_MEM_TWTR => C3_MEM_TWTR, C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_TYPE => C3_MEM_TYPE, C_MEM_DENSITY => C3_MEM_DENSITY, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY, C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS, C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT, C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN, C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR, C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR, C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS, C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT, C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY, C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR, C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR, C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS, C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS, C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE, C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY, C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL, C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL, C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL, C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL, C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL, C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL, C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL, C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL, C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL, C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL, C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL, C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL, C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL, C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL, C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL, C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL, C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL, C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL, C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL, C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL, C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL, C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL ) port map ( mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_reset_n => mcb3_dram_reset_n, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_dm => mcb3_dram_dm, mcb3_dram_udqs => mcb3_dram_udqs, mcb3_dram_udqs_n => mcb3_dram_udqs_n, mcb3_rzq => mcb3_rzq, mcb3_dram_udm => mcb3_dram_udm, calib_done => c3_calib_done, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk, mcb3_dram_dqs => mcb3_dram_dqs, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, p0_cmd_clk => c3_p0_cmd_clk, p0_cmd_en => c3_p0_cmd_en, p0_cmd_instr => c3_p0_cmd_instr, p0_cmd_bl => c3_p0_cmd_bl, p0_cmd_byte_addr => c3_p0_cmd_byte_addr, p0_cmd_empty => c3_p0_cmd_empty, p0_cmd_full => c3_p0_cmd_full, p0_wr_clk => c3_p0_wr_clk, p0_wr_en => c3_p0_wr_en, p0_wr_mask => c3_p0_wr_mask, p0_wr_data => c3_p0_wr_data, p0_wr_full => c3_p0_wr_full, p0_wr_empty => c3_p0_wr_empty, p0_wr_count => c3_p0_wr_count, p0_wr_underrun => c3_p0_wr_underrun, p0_wr_error => c3_p0_wr_error, p0_rd_clk => c3_p0_rd_clk, p0_rd_en => c3_p0_rd_en, p0_rd_data => c3_p0_rd_data, p0_rd_full => c3_p0_rd_full, p0_rd_empty => c3_p0_rd_empty, p0_rd_count => c3_p0_rd_count, p0_rd_overflow => c3_p0_rd_overflow, p0_rd_error => c3_p0_rd_error, p1_cmd_clk => c3_p1_cmd_clk, p1_cmd_en => c3_p1_cmd_en, p1_cmd_instr => c3_p1_cmd_instr, p1_cmd_bl => c3_p1_cmd_bl, p1_cmd_byte_addr => c3_p1_cmd_byte_addr, p1_cmd_empty => c3_p1_cmd_empty, p1_cmd_full => c3_p1_cmd_full, p1_wr_clk => c3_p1_wr_clk, p1_wr_en => c3_p1_wr_en, p1_wr_mask => c3_p1_wr_mask, p1_wr_data => c3_p1_wr_data, p1_wr_full => c3_p1_wr_full, p1_wr_empty => c3_p1_wr_empty, p1_wr_count => c3_p1_wr_count, p1_wr_underrun => c3_p1_wr_underrun, p1_wr_error => c3_p1_wr_error, p1_rd_clk => c3_p1_rd_clk, p1_rd_en => c3_p1_rd_en, p1_rd_data => c3_p1_rd_data, p1_rd_full => c3_p1_rd_full, p1_rd_empty => c3_p1_rd_empty, p1_rd_count => c3_p1_rd_count, p1_rd_overflow => c3_p1_rd_overflow, p1_rd_error => c3_p1_rd_error, selfrefresh_enter => c3_selfrefresh_enter, selfrefresh_mode => c3_selfrefresh_mode ); end arc;
gpl-3.0
253221feddc94c6802d8e4078cf54ea2
0.454037
3.434741
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_bram_0/daala_zynq_axi_bram_ctrl_0_bram_0/simulation/data_gen.vhd
1
5,024
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v8_0 Core - Data Generator -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: data_gen.vhd -- -- Description: -- Data Generator -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY DATA_GEN IS GENERIC ( DATA_GEN_WIDTH : INTEGER := 32; DOUT_WIDTH : INTEGER := 32; DATA_PART_CNT : INTEGER := 1; SEED : INTEGER := 2 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR ); END DATA_GEN; ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); SIGNAL LOCAL_CNT : INTEGER :=1; SIGNAL DATA_GEN_I : STD_LOGIC :='0'; BEGIN LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; PROCESS(CLK) BEGIN IF(RISING_EDGE (CLK)) THEN IF(EN ='1' AND (DATA_PART_CNT =1)) THEN LOCAL_CNT <=1; ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN IF(LOCAL_CNT = 1) THEN LOCAL_CNT <= LOCAL_CNT+1; ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN LOCAL_CNT <= LOCAL_CNT+1; ELSE LOCAL_CNT <= 1; END IF; ELSE LOCAL_CNT <= 1; END IF; END IF; END PROCESS; RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE RAND_GEN_INST:ENTITY work.RANDOM GENERIC MAP( WIDTH => 8, SEED => (SEED+N) ) PORT MAP( CLK => CLK, RST => RST, EN => DATA_GEN_I, RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) ); END GENERATE RAND_GEN; END ARCHITECTURE;
bsd-2-clause
4ca455cd9f08fb012d28f8f4646b2278
0.581608
4.279387
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_fifo.vhd
1
25,703
------------------------------------------------------------------------------- -- axi_datamover_fifo.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_fifo.vhd -- Version: initial -- Description: -- This file is a wrapper file for the Synchronous FIFO used by the DataMover. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_fifo.vhd -- | -- |-- proc_common_v4_0.srl_fifo_f -- | -- | -- |-- axi_datamover_sfifo_autord.vhd -- | | -- | |--- proc_common_v4_0.sync_fifo_fg -- | -- | -- |-- axi_datamover_afifo_autord.vhd -- | -- |--- proc_common_v4_0.async_fifo_fg -- -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- --------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; use proc_common_v4_0.proc_common_pkg.clog2; use proc_common_v4_0.srl_fifo_f; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_sfifo_autord; use axi_datamover_v5_1.axi_datamover_afifo_autord; ------------------------------------------------------------------------------- entity axi_datamover_fifo is generic ( C_DWIDTH : integer := 32 ; -- Bit width of the FIFO C_DEPTH : integer := 4 ; -- Depth of the fifo in fifo width words C_IS_ASYNC : Integer range 0 to 1 := 0 ; -- 0 = Syncronous FIFO -- 1 = Asynchronous (2 clock) FIFO C_PRIM_TYPE : Integer range 0 to 2 := 2 ; -- 0 = Register -- 1 = Block Memory -- 2 = SRL C_FAMILY : String := "virtex7" -- Specifies the Target FPGA device family ); port ( -- Write Clock and reset ----------------- fifo_wr_reset : In std_logic; -- fifo_wr_clk : In std_logic; -- ------------------------------------------ -- Write Side ------------------------------------------------------ fifo_wr_tvalid : In std_logic; -- fifo_wr_tready : Out std_logic; -- fifo_wr_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); -- fifo_wr_full : Out std_logic; -- -------------------------------------------------------------------- -- Read Clock and reset ----------------------------------------------- fifo_async_rd_reset : In std_logic; -- only used if C_IS_ASYNC = 1 -- fifo_async_rd_clk : In std_logic; -- only used if C_IS_ASYNC = 1 -- ----------------------------------------------------------------------- -- Read Side -------------------------------------------------------- fifo_rd_tvalid : Out std_logic; -- fifo_rd_tready : In std_logic; -- fifo_rd_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); -- fifo_rd_empty : Out std_logic -- --------------------------------------------------------------------- ); end entity axi_datamover_fifo; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of axi_datamover_fifo is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; -- function Declarations ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_prim_type -- -- Function Description: -- Sorts out the FIFO Primitive type selection based on fifo -- depth and original primitive choice. -- ------------------------------------------------------------------- function funct_get_prim_type (depth : integer; input_prim_type : integer) return integer is Variable temp_prim_type : Integer := 0; begin If (depth > 64) Then temp_prim_type := 1; -- use BRAM Elsif (depth <= 64 and input_prim_type = 0) Then temp_prim_type := 0; -- use regiaters else temp_prim_type := 1; -- use BRAM End if; Return (temp_prim_type); end function funct_get_prim_type; -- Signal declarations Signal sig_init_reg : std_logic := '0'; Signal sig_init_reg2 : std_logic := '0'; Signal sig_init_done : std_logic := '0'; signal sig_inhibit_rdy_n : std_logic := '0'; ----------------------------------------------------------------------------- -- Begin architecture ----------------------------------------------------------------------------- begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_INIT_REG -- -- Process Description: -- Registers the reset signal input. -- ------------------------------------------------------------- IMP_INIT_REG : process (fifo_wr_clk) begin if (fifo_wr_clk'event and fifo_wr_clk = '1') then if (fifo_wr_reset = '1') then sig_init_reg <= '1'; sig_init_reg2 <= '1'; else sig_init_reg <= '0'; sig_init_reg2 <= sig_init_reg; end if; end if; end process IMP_INIT_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_INIT_DONE_REG -- -- Process Description: -- Create a 1 clock wide init done pulse. -- ------------------------------------------------------------- IMP_INIT_DONE_REG : process (fifo_wr_clk) begin if (fifo_wr_clk'event and fifo_wr_clk = '1') then if (fifo_wr_reset = '1' or sig_init_done = '1') then sig_init_done <= '0'; Elsif (sig_init_reg = '1' and sig_init_reg2 = '1') Then sig_init_done <= '1'; else null; -- hold current state end if; end if; end process IMP_INIT_DONE_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RDY_INHIBIT_REG -- -- Process Description: -- Implements a ready inhibit flop. -- ------------------------------------------------------------- IMP_RDY_INHIBIT_REG : process (fifo_wr_clk) begin if (fifo_wr_clk'event and fifo_wr_clk = '1') then if (fifo_wr_reset = '1') then sig_inhibit_rdy_n <= '0'; Elsif (sig_init_done = '1') Then sig_inhibit_rdy_n <= '1'; else null; -- hold current state end if; end if; end process IMP_RDY_INHIBIT_REG; ------------------------------------------------------------ -- If Generate -- -- Label: USE_SINGLE_REG -- -- If Generate Description: -- Implements a 1 deep register FIFO (synchronous mode only) -- -- ------------------------------------------------------------ USE_SINGLE_REG : if (C_IS_ASYNC = 0 and C_DEPTH <= 1) generate -- Local Constants -- local signals signal sig_data_in : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal sig_regfifo_dout_reg : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal sig_regfifo_full_reg : std_logic := '0'; signal sig_regfifo_empty_reg : std_logic := '0'; signal sig_push_regfifo : std_logic := '0'; signal sig_pop_regfifo : std_logic := '0'; begin -- Internal signals -- Write signals fifo_wr_tready <= sig_regfifo_empty_reg; fifo_wr_full <= sig_regfifo_full_reg ; sig_push_regfifo <= fifo_wr_tvalid and sig_regfifo_empty_reg; sig_data_in <= fifo_wr_tdata ; -- Read signals fifo_rd_tdata <= sig_regfifo_dout_reg ; fifo_rd_tvalid <= sig_regfifo_full_reg ; fifo_rd_empty <= sig_regfifo_empty_reg; sig_pop_regfifo <= sig_regfifo_full_reg and fifo_rd_tready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_REG_FIFO -- -- Process Description: -- This process implements the data and full flag for the -- register fifo. -- ------------------------------------------------------------- IMP_REG_FIFO : process (fifo_wr_clk) begin if (fifo_wr_clk'event and fifo_wr_clk = '1') then if (fifo_wr_reset = '1' or sig_pop_regfifo = '1') then sig_regfifo_full_reg <= '0'; elsif (sig_push_regfifo = '1') then sig_regfifo_full_reg <= '1'; else null; -- don't change state end if; end if; end process IMP_REG_FIFO; IMP_REG_FIFO1 : process (fifo_wr_clk) begin if (fifo_wr_clk'event and fifo_wr_clk = '1') then if (fifo_wr_reset = '1') then sig_regfifo_dout_reg <= (others => '0'); elsif (sig_push_regfifo = '1') then sig_regfifo_dout_reg <= sig_data_in; else null; -- don't change state end if; end if; end process IMP_REG_FIFO1; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_REG_EMPTY_FLOP -- -- Process Description: -- This process implements the empty flag for the -- register fifo. -- ------------------------------------------------------------- IMP_REG_EMPTY_FLOP : process (fifo_wr_clk) begin if (fifo_wr_clk'event and fifo_wr_clk = '1') then if (fifo_wr_reset = '1') then sig_regfifo_empty_reg <= '0'; -- since this is used for the ready (invertd) -- it can't be asserted during reset elsif (sig_pop_regfifo = '1' or sig_init_done = '1') then sig_regfifo_empty_reg <= '1'; elsif (sig_push_regfifo = '1') then sig_regfifo_empty_reg <= '0'; else null; -- don't change state end if; end if; end process IMP_REG_EMPTY_FLOP; end generate USE_SINGLE_REG; ------------------------------------------------------------ -- If Generate -- -- Label: USE_SRL_FIFO -- -- If Generate Description: -- Generates a fifo implementation usinf SRL based FIFOa -- -- ------------------------------------------------------------ USE_SRL_FIFO : if (C_IS_ASYNC = 0 and C_DEPTH <= 64 and C_DEPTH > 1 and C_PRIM_TYPE = 2 ) generate -- Local Constants Constant LOGIC_LOW : std_logic := '0'; Constant NEED_ALMOST_EMPTY : Integer := 0; Constant NEED_ALMOST_FULL : Integer := 0; -- local signals signal sig_wr_full : std_logic := '0'; signal sig_wr_fifo : std_logic := '0'; signal sig_wr_ready : std_logic := '0'; signal sig_rd_fifo : std_logic := '0'; signal sig_rd_empty : std_logic := '0'; signal sig_rd_valid : std_logic := '0'; signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); begin -- Write side signals fifo_wr_tready <= sig_wr_ready; fifo_wr_full <= sig_wr_full; sig_wr_ready <= not(sig_wr_full) and sig_inhibit_rdy_n; sig_wr_fifo <= fifo_wr_tvalid and sig_wr_ready; sig_fifo_wr_data <= fifo_wr_tdata; -- Read Side Signals fifo_rd_tvalid <= sig_rd_valid; sig_rd_valid <= not(sig_rd_empty); fifo_rd_tdata <= sig_fifo_rd_data ; fifo_rd_empty <= not(sig_rd_valid); sig_rd_fifo <= sig_rd_valid and fifo_rd_tready; ------------------------------------------------------------ -- Instance: I_SYNC_FIFO -- -- Description: -- Implement the synchronous FIFO using SRL FIFO elements -- ------------------------------------------------------------ I_SYNC_FIFO : entity proc_common_v4_0.srl_fifo_f generic map ( C_DWIDTH => C_DWIDTH , C_DEPTH => C_DEPTH , C_FAMILY => C_FAMILY ) port map ( Clk => fifo_wr_clk , Reset => fifo_wr_reset , FIFO_Write => sig_wr_fifo , Data_In => sig_fifo_wr_data , FIFO_Read => sig_rd_fifo , Data_Out => sig_fifo_rd_data , FIFO_Empty => sig_rd_empty , FIFO_Full => sig_wr_full , Addr => open ); end generate USE_SRL_FIFO; ------------------------------------------------------------ -- If Generate -- -- Label: USE_SYNC_FIFO -- -- If Generate Description: -- Instantiates a synchronous FIFO design for use in the -- synchronous operating mode. -- ------------------------------------------------------------ USE_SYNC_FIFO : if (C_IS_ASYNC = 0 and (C_DEPTH > 64 or (C_DEPTH > 1 and C_PRIM_TYPE < 2 ))) or (C_IS_ASYNC = 0 and C_DEPTH <= 64 and C_DEPTH > 1 and C_PRIM_TYPE = 0 ) generate -- Local Constants Constant LOGIC_LOW : std_logic := '0'; Constant NEED_ALMOST_EMPTY : Integer := 0; Constant NEED_ALMOST_FULL : Integer := 0; Constant DATA_CNT_WIDTH : Integer := clog2(C_DEPTH)+1; Constant PRIM_TYPE : Integer := funct_get_prim_type(C_DEPTH, C_PRIM_TYPE); -- local signals signal sig_wr_full : std_logic := '0'; signal sig_wr_fifo : std_logic := '0'; signal sig_wr_ready : std_logic := '0'; signal sig_rd_fifo : std_logic := '0'; signal sig_rd_valid : std_logic := '0'; signal sig_fifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal sig_fifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); begin -- Write side signals fifo_wr_tready <= sig_wr_ready; fifo_wr_full <= sig_wr_full; sig_wr_ready <= not(sig_wr_full) and sig_inhibit_rdy_n; sig_wr_fifo <= fifo_wr_tvalid and sig_wr_ready; sig_fifo_wr_data <= fifo_wr_tdata; -- Read Side Signals fifo_rd_tvalid <= sig_rd_valid; fifo_rd_tdata <= sig_fifo_rd_data ; fifo_rd_empty <= not(sig_rd_valid); sig_rd_fifo <= sig_rd_valid and fifo_rd_tready; ------------------------------------------------------------ -- Instance: I_SYNC_FIFO -- -- Description: -- Implement the synchronous FIFO -- ------------------------------------------------------------ I_SYNC_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord generic map ( C_DWIDTH => C_DWIDTH , C_DEPTH => C_DEPTH , C_DATA_CNT_WIDTH => DATA_CNT_WIDTH , C_NEED_ALMOST_EMPTY => NEED_ALMOST_EMPTY , C_NEED_ALMOST_FULL => NEED_ALMOST_FULL , C_USE_BLKMEM => PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Inputs SFIFO_Sinit => fifo_wr_reset , SFIFO_Clk => fifo_wr_clk , SFIFO_Wr_en => sig_wr_fifo , SFIFO_Din => fifo_wr_tdata , SFIFO_Rd_en => sig_rd_fifo , SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs SFIFO_DValid => sig_rd_valid , SFIFO_Dout => sig_fifo_rd_data , SFIFO_Full => sig_wr_full , SFIFO_Empty => open , SFIFO_Almost_full => open , SFIFO_Almost_empty => open , SFIFO_Rd_count => open , SFIFO_Rd_count_minus1 => open , SFIFO_Wr_count => open , SFIFO_Rd_ack => open ); end generate USE_SYNC_FIFO; ------------------------------------------------------------ -- If Generate -- -- Label: USE_ASYNC_FIFO -- -- If Generate Description: -- Instantiates an asynchronous FIFO design for use in the -- asynchronous operating mode. -- ------------------------------------------------------------ USE_ASYNC_FIFO : if (C_IS_ASYNC = 1) generate -- Local Constants Constant LOGIC_LOW : std_logic := '0'; Constant CNT_WIDTH : Integer := clog2(C_DEPTH); -- local signals signal sig_async_wr_full : std_logic := '0'; signal sig_async_wr_fifo : std_logic := '0'; signal sig_async_wr_ready : std_logic := '0'; signal sig_async_rd_fifo : std_logic := '0'; signal sig_async_rd_valid : std_logic := '0'; signal sig_afifo_rd_data : std_logic_vector(C_DWIDTH-1 downto 0); signal sig_afifo_wr_data : std_logic_vector(C_DWIDTH-1 downto 0); signal sig_fifo_ainit : std_logic := '0'; Signal sig_init_reg : std_logic := '0'; begin sig_fifo_ainit <= fifo_async_rd_reset or fifo_wr_reset; -- Write side signals fifo_wr_tready <= sig_async_wr_ready; fifo_wr_full <= sig_async_wr_full; sig_async_wr_ready <= not(sig_async_wr_full) and sig_inhibit_rdy_n; sig_async_wr_fifo <= fifo_wr_tvalid and sig_async_wr_ready; sig_afifo_wr_data <= fifo_wr_tdata; -- Read Side Signals fifo_rd_tvalid <= sig_async_rd_valid; fifo_rd_tdata <= sig_afifo_rd_data ; fifo_rd_empty <= not(sig_async_rd_valid); sig_async_rd_fifo <= sig_async_rd_valid and fifo_rd_tready; ------------------------------------------------------------ -- Instance: I_ASYNC_FIFO -- -- Description: -- Implement the asynchronous FIFO -- ------------------------------------------------------------ I_ASYNC_FIFO : entity axi_datamover_v5_1.axi_datamover_afifo_autord generic map ( C_DWIDTH => C_DWIDTH , C_DEPTH => C_DEPTH , C_CNT_WIDTH => CNT_WIDTH , C_USE_BLKMEM => C_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Inputs AFIFO_Ainit => sig_fifo_ainit , AFIFO_Ainit_Rd_clk => fifo_async_rd_reset , AFIFO_Wr_clk => fifo_wr_clk , AFIFO_Wr_en => sig_async_wr_fifo , AFIFO_Din => sig_afifo_wr_data , AFIFO_Rd_clk => fifo_async_rd_clk , AFIFO_Rd_en => sig_async_rd_fifo , AFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs AFIFO_DValid => sig_async_rd_valid, AFIFO_Dout => sig_afifo_rd_data , AFIFO_Full => sig_async_wr_full , AFIFO_Empty => open , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); end generate USE_ASYNC_FIFO; end imp;
bsd-2-clause
739e7d39cf6c1d3be0ae20b5e067c445
0.413959
4.491961
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/vhdlFile/if_generate_statement/classification_test_input.vhd
1
1,622
architecture RTL of FIFO is begin LABEL0 : if a = 1 generate end generate LABEL0; -- Simple test case LABEL1 : if a = 1 generate elsif a = 0 generate elsif a = 1 generate else generate end generate LABEL1; -- Test nesting LABEL2A: if a = 1 generate LABEL3A : if x = 0 generate elsif y = 1 generate else generate end generate LABEL3A; elsif b = 0 generate elsif c = 1 generate else generate end generate LABEL2A; -- Test multiple layers of nesting LABEL2A: if a = 1 generate LABEL3A : if x = 0 generate LABEL4A : if x = 0 generate elsif y = 1 generate else generate end generate LABEL4A; elsif y = 1 generate else generate end generate LABEL3A; elsif b = 0 generate LABEL3A : if x = 0 generate LABEL4A : if x = 0 generate elsif y = 1 generate else generate end generate LABEL4A; elsif y = 1 generate else generate end generate LABEL3A; elsif c = 1 generate LABEL3A : if x = 0 generate LABEL4A : if x = 0 generate elsif y = 1 generate else generate end generate LABEL4A; elsif y = 1 generate else generate end generate LABEL3A; else generate LABEL3A : if x = 0 generate LABEL4A : if x = 0 generate elsif y = 1 generate else generate end generate LABEL4A; elsif y = 1 generate else generate end generate LABEL3A; end generate LABEL2A; end architecture RTL;
gpl-3.0
17fd2337aff96cf40d0bf41efc9a7894
0.581998
4.302387
false
false
false
false
Yarr/Yarr-fw
syn/spec/top_yarr_spec2.vhd
2
18,420
-------------------------------------------- -- Project: YARR -- Author: Timon Heim ([email protected]) -- Description: Top module for YARR on SPEC -- Dependencies: - -------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library UNISIM; use UNISIM.vcomponents.all; library work; use work.gn4124_core_pkg.all; entity yarr is port ( ---------------------------------- -- Clocks ---------------------------------- L_CLKP : IN STD_LOGIC; L_CLKN : IN STD_LOGIC; CLK20_VCXO_I : IN STD_LOGIC; CLK_125M_PLLREF_P_I : IN STD_LOGIC; CLK_125M_PLLREF_N_I : IN STD_LOGIC; ---------------------------------- -- Reset ---------------------------------- L_RST_N : IN STD_LOGIC; ---------------------------------- -- GPIOs used for IRQ ---------------------------------- GPIO : OUT STD_LOGIC_VECTOR(1 downto 0); ---------------------------------- -- PCIe to Local [Inbound Data] - RX ---------------------------------- P2L_RDY : OUT std_logic; -- Rx Buffer Full Flag P2L_CLKn : IN std_logic; -- Receiver Source Synchronous Clock- P2L_CLKp : IN std_logic; -- Receiver Source Synchronous Clock+ P2L_DATA : IN std_logic_vector(15 downto 0); -- Parallel receive data P2L_DFRAME : IN std_logic; -- Receive Frame P2L_VALID : IN std_logic; -- Receive Data Valid ---------------------------------- -- Inbound buffer status ---------------------------------- P_WR_REQ : IN std_logic_vector(1 downto 0); -- PCIe Write Request P_WR_RDY : OUT std_logic_vector(1 downto 0); -- PCIe Write Ready RC_ERROR : OUT std_logic; -- Receive Error ---------------------------------- -- Local to PCIe [Outbound Data] - Tx ---------------------------------- L2P_DATA : OUT std_logic_vector(15 downto 0); L2P_DFRAME : OUT std_logic; L2P_VALID : OUT std_logic; L2P_CLKn : OUT std_logic; L2P_CLKp : OUT std_logic; L2P_EDB : OUT std_logic; ---------------------------------- -- Outbound buffer status ---------------------------------- L2P_RDY : IN std_logic; L_WR_RDY : IN std_logic_vector(1 downto 0); P_RD_D_RDY : IN std_logic_vector(1 downto 0); TX_ERROR : IN std_logic; VC_RDY : IN std_logic; ---------------------------------- -- Front Panel LEDs ---------------------------------- LED_GREEN_O : OUT std_logic; LED_RED_O : OUT std_logic; ---------------------------------- -- Auxiliary ports ---------------------------------- AUX_LEDS_O : OUT std_logic_vector(3 downto 0); AUX_BUTTONS_I : IN std_logic_vector(1 downto 0); ---------------------------------- -- DDR3 ---------------------------------- DDR3_CAS_N : OUT std_logic; DDR3_CK_P : OUT std_logic; DDR3_CK_N : OUT std_logic; DDR3_CKE : OUT std_logic; DDR3_LDM : OUT std_logic; DDR3_LDQS_N : INOUT std_logic; DDR3_LDQS_P : INOUT std_logic; DDR3_ODT : OUT std_logic; DDR3_RAS_N : OUT std_logic; DDR3_RESET_N : OUT std_logic; DDR3_UDM : OUT std_logic; DDR3_UDQS_N : INOUT std_logic; DDR3_UDQS_P : INOUT std_logic; DDR3_WE_N : OUT std_logic; DDR3_RZQ : INOUT std_logic; DDR3_ZIO : INOUT std_logic; DDR3_A : OUT std_logic_vector(13 downto 0); DDR3_BA : OUT std_logic_vector(2 downto 0); DDR3_DQ : INOUT std_logic_vector(15 downto 0) ); end yarr; architecture rtl of yarr is ---------------------------------- -- Components ---------------------------------- component gn4124_core port ( --------------------------------------------------------- -- Control and status rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124 status_o : out std_logic_vector(31 downto 0); -- Core status output --------------------------------------------------------- -- P2L Direction -- -- Source Sync DDR related signals p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+ p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock- p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data p2l_dframe_i : in std_logic; -- Receive Frame p2l_valid_i : in std_logic; -- Receive Data Valid -- P2L Control p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready rx_error_o : out std_logic; -- Receive Error --------------------------------------------------------- -- L2P Direction -- -- Source Sync DDR related signals l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data l2p_dframe_o : out std_logic; -- Transmit Data Frame l2p_valid_o : out std_logic; -- Transmit Data Valid l2p_edb_o : out std_logic; -- Packet termination and discard -- L2P Control l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready tx_error_i : in std_logic; -- Transmit Error vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready --------------------------------------------------------- -- Interrupt interface dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO --------------------------------------------------------- -- DMA registers wishbone interface (slave classic) dma_reg_clk_i : in std_logic; dma_reg_adr_i : in std_logic_vector(31 downto 0); dma_reg_dat_i : in std_logic_vector(31 downto 0); dma_reg_sel_i : in std_logic_vector(3 downto 0); dma_reg_stb_i : in std_logic; dma_reg_we_i : in std_logic; dma_reg_cyc_i : in std_logic; dma_reg_dat_o : out std_logic_vector(31 downto 0); dma_reg_ack_o : out std_logic; dma_reg_stall_o : out std_logic; --------------------------------------------------------- -- CSR wishbone interface (master pipelined) csr_clk_i : in std_logic; csr_adr_o : out std_logic_vector(31 downto 0); csr_dat_o : out std_logic_vector(31 downto 0); csr_sel_o : out std_logic_vector(3 downto 0); csr_stb_o : out std_logic; csr_we_o : out std_logic; csr_cyc_o : out std_logic; csr_dat_i : in std_logic_vector(31 downto 0); csr_ack_i : in std_logic; csr_stall_i : in std_logic; csr_err_i : in std_logic; csr_rty_i : in std_logic; csr_int_i : in std_logic; --------------------------------------------------------- -- DMA interface (Pipelined wishbone master) dma_clk_i : in std_logic; dma_adr_o : out std_logic_vector(31 downto 0); dma_dat_o : out std_logic_vector(31 downto 0); dma_sel_o : out std_logic_vector(3 downto 0); dma_stb_o : out std_logic; dma_we_o : out std_logic; dma_cyc_o : out std_logic; dma_dat_i : in std_logic_vector(31 downto 0); dma_ack_i : in std_logic; dma_stall_i : in std_logic; dma_err_i : in std_logic; dma_rty_i : in std_logic; dma_int_i : in std_logic ); end component; -- gn4124_core component wb_addr_decoder generic ( g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address) g_WB_SLAVES_NB : integer := 2 ); port ( --------------------------------------------------------- -- GN4124 core clock and reset clk_i : in std_logic; rst_n_i : in std_logic; --------------------------------------------------------- -- wishbone master interface wbm_adr_i : in std_logic_vector(31 downto 0); -- Address wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select wbm_stb_i : in std_logic; -- Strobe wbm_we_i : in std_logic; -- Write wbm_cyc_i : in std_logic; -- Cycle wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in wbm_ack_o : out std_logic; -- Acknowledge wbm_stall_o : out std_logic; -- Stall --------------------------------------------------------- -- wishbone slaves interface wb_adr_o : out std_logic_vector(31 downto 0); -- Address wb_dat_o : out std_logic_vector(31 downto 0); -- Data out wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select wb_stb_o : out std_logic; -- Strobe wb_we_o : out std_logic; -- Write wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall ); end component wb_addr_decoder; -- wb_addr_decoder component ddr3_ctrl generic( --! Bank and port size selection g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B"; --! Core's clock period in ps g_MEMCLK_PERIOD : integer := 3000; --! If TRUE, uses Xilinx calibration core (Input term, DQS centering) g_CALIB_SOFT_IP : string := "TRUE"; --! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN) g_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN"; --! Simulation mode g_SIMULATION : string := "FALSE"; --! DDR3 data port width g_NUM_DQ_PINS : integer := 16; --! DDR3 address port width g_MEM_ADDR_WIDTH : integer := 14; --! DDR3 bank address width g_MEM_BANKADDR_WIDTH : integer := 3; --! Wishbone port 0 data mask size (8-bit granularity) g_P0_MASK_SIZE : integer := 4; --! Wishbone port 0 data width g_P0_DATA_PORT_SIZE : integer := 32; --! Port 0 byte address width g_P0_BYTE_ADDR_WIDTH : integer := 30; --! Wishbone port 1 data mask size (8-bit granularity) g_P1_MASK_SIZE : integer := 4; --! Wishbone port 1 data width g_P1_DATA_PORT_SIZE : integer := 32; --! Port 1 byte address width g_P1_BYTE_ADDR_WIDTH : integer := 30 ); port( ---------------------------------------------------------------------------- -- Clock, control and status ---------------------------------------------------------------------------- --! Clock input clk_i : in std_logic; --! Reset input (active low) rst_n_i : in std_logic; --! Status output status_o : out std_logic_vector(31 downto 0); ---------------------------------------------------------------------------- -- DDR3 interface ---------------------------------------------------------------------------- --! DDR3 data bus ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0); --! DDR3 address bus ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0); --! DDR3 bank address ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0); --! DDR3 row address strobe ddr3_ras_n_o : out std_logic; --! DDR3 column address strobe ddr3_cas_n_o : out std_logic; --! DDR3 write enable ddr3_we_n_o : out std_logic; --! DDR3 on-die termination ddr3_odt_o : out std_logic; --! DDR3 reset ddr3_rst_n_o : out std_logic; --! DDR3 clock enable ddr3_cke_o : out std_logic; --! DDR3 lower byte data mask ddr3_dm_o : out std_logic; --! DDR3 upper byte data mask ddr3_udm_o : out std_logic; --! DDR3 lower byte data strobe (pos) ddr3_dqs_p_b : inout std_logic; --! DDR3 lower byte data strobe (neg) ddr3_dqs_n_b : inout std_logic; --! DDR3 upper byte data strobe (pos) ddr3_udqs_p_b : inout std_logic; --! DDR3 upper byte data strobe (pos) ddr3_udqs_n_b : inout std_logic; --! DDR3 clock (pos) ddr3_clk_p_o : out std_logic; --! DDR3 clock (neg) ddr3_clk_n_o : out std_logic; --! MCB internal termination calibration resistor ddr3_rzq_b : inout std_logic; --! MCB internal termination calibration ddr3_zio_b : inout std_logic; ---------------------------------------------------------------------------- -- Wishbone bus - Port 0 ---------------------------------------------------------------------------- --! Wishbone bus clock wb0_clk_i : in std_logic; --! Wishbone bus byte select wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0); --! Wishbone bus cycle select wb0_cyc_i : in std_logic; --! Wishbone bus cycle strobe wb0_stb_i : in std_logic; --! Wishbone bus write enable wb0_we_i : in std_logic; --! Wishbone bus address wb0_addr_i : in std_logic_vector(31 downto 0); --! Wishbone bus data input wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus data output wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus acknowledge wb0_ack_o : out std_logic; --! Wishbone bus stall (for pipelined mode) wb0_stall_o : out std_logic; ---------------------------------------------------------------------------- -- Status - Port 0 ---------------------------------------------------------------------------- --! Command FIFO empty p0_cmd_empty_o : out std_logic; --! Command FIFO full p0_cmd_full_o : out std_logic; --! Read FIFO full p0_rd_full_o : out std_logic; --! Read FIFO empty p0_rd_empty_o : out std_logic; --! Read FIFO count p0_rd_count_o : out std_logic_vector(6 downto 0); --! Read FIFO overflow p0_rd_overflow_o : out std_logic; --! Read FIFO error (pointers unsynchronized, reset required) p0_rd_error_o : out std_logic; --! Write FIFO full p0_wr_full_o : out std_logic; --! Write FIFO empty p0_wr_empty_o : out std_logic; --! Write FIFO count p0_wr_count_o : out std_logic_vector(6 downto 0); --! Write FIFO underrun p0_wr_underrun_o : out std_logic; --! Write FIFO error (pointers unsynchronized, reset required) p0_wr_error_o : out std_logic; ---------------------------------------------------------------------------- -- Wishbone bus - Port 1 ---------------------------------------------------------------------------- --! Wishbone bus clock wb1_clk_i : in std_logic; --! Wishbone bus byte select wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0); --! Wishbone bus cycle select wb1_cyc_i : in std_logic; --! Wishbone bus cycle strobe wb1_stb_i : in std_logic; --! Wishbone bus write enable wb1_we_i : in std_logic; --! Wishbone bus address wb1_addr_i : in std_logic_vector(31 downto 0); --! Wishbone bus data input wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus data output wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0); --! Wishbone bus acknowledge wb1_ack_o : out std_logic; --! Wishbone bus stall (for pipelined mode) wb1_stall_o : out std_logic; ---------------------------------------------------------------------------- -- Status - Port 1 ---------------------------------------------------------------------------- --! Command FIFO empty p1_cmd_empty_o : out std_logic; --! Command FIFO full p1_cmd_full_o : out std_logic; --! Read FIFO full p1_rd_full_o : out std_logic; --! Read FIFO empty p1_rd_empty_o : out std_logic; --! Read FIFO count p1_rd_count_o : out std_logic_vector(6 downto 0); --! Read FIFO overflow p1_rd_overflow_o : out std_logic; --! Read FIFO error (pointers unsynchronized, reset required) p1_rd_error_o : out std_logic; --! Write FIFO full p1_wr_full_o : out std_logic; --! Write FIFO empty p1_wr_empty_o : out std_logic; --! Write FIFO count p1_wr_count_o : out std_logic_vector(6 downto 0); --! Write FIFO underrun p1_wr_underrun_o : out std_logic; --! Write FIFO error (pointers unsynchronized, reset required) p1_wr_error_o : out std_logic ); end component ddr3_ctrl; begin end rtl;
gpl-3.0
4ce6daaaf8bb57aa8f45d18e2adda48b
0.470413
3.756884
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register_s2mm.vhd
1
177,887
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_register_s2mm.vhd -- -- Description: This entity encompasses the channel register set. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_register_s2mm is generic( C_NUM_REGISTERS : integer := 11 ; C_INCLUDE_SG : integer := 1 ; C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ; C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ; C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ; C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ; C_MICRO_DMA : integer range 0 to 1 := 0 ; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 --C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034 ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- AXI Interface Control -- axi2ip_wrce : in std_logic_vector -- (C_NUM_REGISTERS-1 downto 0) ; -- axi2ip_wrdata : in std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- -- -- DMASR Control -- stop_dma : in std_logic ; -- halted_clr : in std_logic ; -- halted_set : in std_logic ; -- idle_set : in std_logic ; -- idle_clr : in std_logic ; -- ioc_irq_set : in std_logic ; -- dly_irq_set : in std_logic ; -- irqdelay_status : in std_logic_vector(7 downto 0) ; -- irqthresh_status : in std_logic_vector(7 downto 0) ; -- irqthresh_wren : out std_logic ; -- irqdelay_wren : out std_logic ; -- dlyirq_dsble : out std_logic ; -- CR605888 -- -- Error Control -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- ftch_interr_set : in std_logic ; -- ftch_slverr_set : in std_logic ; -- ftch_decerr_set : in std_logic ; -- ftch_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_interr_set : in std_logic ; -- updt_slverr_set : in std_logic ; -- updt_decerr_set : in std_logic ; -- updt_error_addr : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- error_in : in std_logic ; -- error_out : out std_logic ; -- introut : out std_logic ; -- soft_reset_in : in std_logic ; -- soft_reset_clr : in std_logic ; -- -- -- CURDESC Update -- update_curdesc : in std_logic ; -- tdest_in : in std_logic_vector (5 downto 0) ; new_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- -- TAILDESC Update -- tailpntr_updated : out std_logic ; -- -- -- Channel Register Out -- sg_ctl : out std_logic_vector (7 downto 0) ; dmacr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- dmasr : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc1_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc2_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc3_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc4_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc5_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc6_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc7_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc8_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc9_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc10_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc11_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc12_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc13_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc14_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- curdesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_lsb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- taildesc15_msb : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- buffer_address : out std_logic_vector -- (C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- buffer_length : out std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- buffer_length_wren : out std_logic ; -- bytes_received : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- bytes_received_wren : in std_logic -- ); -- end axi_dma_register_s2mm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_register_s2mm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant SGCTL_INDEX : integer := 0; constant DMACR_INDEX : integer := 1; -- DMACR Register index constant DMASR_INDEX : integer := 2; -- DMASR Register index constant CURDESC_LSB_INDEX : integer := 3; -- CURDESC LSB Reg index constant CURDESC_MSB_INDEX : integer := 4; -- CURDESC MSB Reg index constant TAILDESC_LSB_INDEX : integer := 5; -- TAILDESC LSB Reg index constant TAILDESC_MSB_INDEX : integer := 6; -- TAILDESC MSB Reg index constant CURDESC1_LSB_INDEX : integer := 17; -- CURDESC LSB Reg index constant CURDESC1_MSB_INDEX : integer := 18; -- CURDESC MSB Reg index constant TAILDESC1_LSB_INDEX : integer := 19; -- TAILDESC LSB Reg index constant TAILDESC1_MSB_INDEX : integer := 20; -- TAILDESC MSB Reg index constant CURDESC2_LSB_INDEX : integer := 25; -- CURDESC LSB Reg index constant CURDESC2_MSB_INDEX : integer := 26; -- CURDESC MSB Reg index constant TAILDESC2_LSB_INDEX : integer := 27; -- TAILDESC LSB Reg index constant TAILDESC2_MSB_INDEX : integer := 28; -- TAILDESC MSB Reg index constant CURDESC3_LSB_INDEX : integer := 33; -- CURDESC LSB Reg index constant CURDESC3_MSB_INDEX : integer := 34; -- CURDESC MSB Reg index constant TAILDESC3_LSB_INDEX : integer := 35; -- TAILDESC LSB Reg index constant TAILDESC3_MSB_INDEX : integer := 36; -- TAILDESC MSB Reg index constant CURDESC4_LSB_INDEX : integer := 41; -- CURDESC LSB Reg index constant CURDESC4_MSB_INDEX : integer := 42; -- CURDESC MSB Reg index constant TAILDESC4_LSB_INDEX : integer := 43; -- TAILDESC LSB Reg index constant TAILDESC4_MSB_INDEX : integer := 44; -- TAILDESC MSB Reg index constant CURDESC5_LSB_INDEX : integer := 49; -- CURDESC LSB Reg index constant CURDESC5_MSB_INDEX : integer := 50; -- CURDESC MSB Reg index constant TAILDESC5_LSB_INDEX : integer := 51; -- TAILDESC LSB Reg index constant TAILDESC5_MSB_INDEX : integer := 52; -- TAILDESC MSB Reg index constant CURDESC6_LSB_INDEX : integer := 57; -- CURDESC LSB Reg index constant CURDESC6_MSB_INDEX : integer := 58; -- CURDESC MSB Reg index constant TAILDESC6_LSB_INDEX : integer := 59; -- TAILDESC LSB Reg index constant TAILDESC6_MSB_INDEX : integer := 60; -- TAILDESC MSB Reg index constant CURDESC7_LSB_INDEX : integer := 65; -- CURDESC LSB Reg index constant CURDESC7_MSB_INDEX : integer := 66; -- CURDESC MSB Reg index constant TAILDESC7_LSB_INDEX : integer := 67; -- TAILDESC LSB Reg index constant TAILDESC7_MSB_INDEX : integer := 68; -- TAILDESC MSB Reg index constant CURDESC8_LSB_INDEX : integer := 73; -- CURDESC LSB Reg index constant CURDESC8_MSB_INDEX : integer := 74; -- CURDESC MSB Reg index constant TAILDESC8_LSB_INDEX : integer := 75; -- TAILDESC LSB Reg index constant TAILDESC8_MSB_INDEX : integer := 76; -- TAILDESC MSB Reg index constant CURDESC9_LSB_INDEX : integer := 81; -- CURDESC LSB Reg index constant CURDESC9_MSB_INDEX : integer := 82; -- CURDESC MSB Reg index constant TAILDESC9_LSB_INDEX : integer := 83; -- TAILDESC LSB Reg index constant TAILDESC9_MSB_INDEX : integer := 84; -- TAILDESC MSB Reg index constant CURDESC10_LSB_INDEX : integer := 89; -- CURDESC LSB Reg index constant CURDESC10_MSB_INDEX : integer := 90; -- CURDESC MSB Reg index constant TAILDESC10_LSB_INDEX : integer := 91; -- TAILDESC LSB Reg index constant TAILDESC10_MSB_INDEX : integer := 92; -- TAILDESC MSB Reg index constant CURDESC11_LSB_INDEX : integer := 97; -- CURDESC LSB Reg index constant CURDESC11_MSB_INDEX : integer := 98; -- CURDESC MSB Reg index constant TAILDESC11_LSB_INDEX : integer := 99; -- TAILDESC LSB Reg index constant TAILDESC11_MSB_INDEX : integer := 100; -- TAILDESC MSB Reg index constant CURDESC12_LSB_INDEX : integer := 105; -- CURDESC LSB Reg index constant CURDESC12_MSB_INDEX : integer := 106; -- CURDESC MSB Reg index constant TAILDESC12_LSB_INDEX : integer := 107; -- TAILDESC LSB Reg index constant TAILDESC12_MSB_INDEX : integer := 108; -- TAILDESC MSB Reg index constant CURDESC13_LSB_INDEX : integer := 113; -- CURDESC LSB Reg index constant CURDESC13_MSB_INDEX : integer := 114; -- CURDESC MSB Reg index constant TAILDESC13_LSB_INDEX : integer := 115; -- TAILDESC LSB Reg index constant TAILDESC13_MSB_INDEX : integer := 116; -- TAILDESC MSB Reg index constant CURDESC14_LSB_INDEX : integer := 121; -- CURDESC LSB Reg index constant CURDESC14_MSB_INDEX : integer := 122; -- CURDESC MSB Reg index constant TAILDESC14_LSB_INDEX : integer := 123; -- TAILDESC LSB Reg index constant TAILDESC14_MSB_INDEX : integer := 124; -- TAILDESC MSB Reg index constant CURDESC15_LSB_INDEX : integer := 129; -- CURDESC LSB Reg index constant CURDESC15_MSB_INDEX : integer := 130; -- CURDESC MSB Reg index constant TAILDESC15_LSB_INDEX : integer := 131; -- TAILDESC LSB Reg index constant TAILDESC15_MSB_INDEX : integer := 132; -- TAILDESC MSB Reg index -- CR603034 moved s2mm back to offset 6 --constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA) --constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA) -- -- --constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA) -- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx -- SA_ADDRESS_INDEX, -- Source Address Index -- DA_ADDRESS_INDEX); -- Destination Address Index constant BUFF_ADDRESS_INDEX : integer := 7; constant BUFF_LENGTH_INDEX : integer := 11; -- Buffer Length Reg constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0'); constant DMA_CONFIG : std_logic_vector(0 downto 0) := std_logic_vector(to_unsigned(C_INCLUDE_SG,1)); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal dmacr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal dmasr_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal curdesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0'); signal taildesc_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_address_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal buffer_length_i : std_logic_vector (C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc1_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc2_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc3_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc4_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc5_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc6_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc7_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc8_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc9_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc10_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc11_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc12_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc13_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc14_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_lsb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal taildesc15_msb_i : std_logic_vector (C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal update_curdesc1 : std_logic := '0'; signal update_curdesc2 : std_logic := '0'; signal update_curdesc3 : std_logic := '0'; signal update_curdesc4 : std_logic := '0'; signal update_curdesc5 : std_logic := '0'; signal update_curdesc6 : std_logic := '0'; signal update_curdesc7 : std_logic := '0'; signal update_curdesc8 : std_logic := '0'; signal update_curdesc9 : std_logic := '0'; signal update_curdesc10 : std_logic := '0'; signal update_curdesc11 : std_logic := '0'; signal update_curdesc12 : std_logic := '0'; signal update_curdesc13 : std_logic := '0'; signal update_curdesc14 : std_logic := '0'; signal update_curdesc15 : std_logic := '0'; signal dest0 : std_logic := '0'; signal dest1 : std_logic := '0'; signal dest2 : std_logic := '0'; signal dest3 : std_logic := '0'; signal dest4 : std_logic := '0'; signal dest5 : std_logic := '0'; signal dest6 : std_logic := '0'; signal dest7 : std_logic := '0'; signal dest8 : std_logic := '0'; signal dest9 : std_logic := '0'; signal dest10 : std_logic := '0'; signal dest11 : std_logic := '0'; signal dest12 : std_logic := '0'; signal dest13 : std_logic := '0'; signal dest14 : std_logic := '0'; signal dest15 : std_logic := '0'; -- DMASR Signals signal halted : std_logic := '0'; signal idle : std_logic := '0'; signal cmplt : std_logic := '0'; signal error : std_logic := '0'; signal dma_interr : std_logic := '0'; signal dma_slverr : std_logic := '0'; signal dma_decerr : std_logic := '0'; signal sg_interr : std_logic := '0'; signal sg_slverr : std_logic := '0'; signal sg_decerr : std_logic := '0'; signal ioc_irq : std_logic := '0'; signal dly_irq : std_logic := '0'; signal error_d1 : std_logic := '0'; signal error_re : std_logic := '0'; signal err_irq : std_logic := '0'; signal sg_ftch_error : std_logic := '0'; signal sg_updt_error : std_logic := '0'; signal error_pointer_set : std_logic := '0'; signal error_pointer_set1 : std_logic := '0'; signal error_pointer_set2 : std_logic := '0'; signal error_pointer_set3 : std_logic := '0'; signal error_pointer_set4 : std_logic := '0'; signal error_pointer_set5 : std_logic := '0'; signal error_pointer_set6 : std_logic := '0'; signal error_pointer_set7 : std_logic := '0'; signal error_pointer_set8 : std_logic := '0'; signal error_pointer_set9 : std_logic := '0'; signal error_pointer_set10 : std_logic := '0'; signal error_pointer_set11 : std_logic := '0'; signal error_pointer_set12 : std_logic := '0'; signal error_pointer_set13 : std_logic := '0'; signal error_pointer_set14 : std_logic := '0'; signal error_pointer_set15 : std_logic := '0'; -- interrupt coalescing support signals signal different_delay : std_logic := '0'; signal different_thresh : std_logic := '0'; signal threshold_is_zero : std_logic := '0'; -- soft reset support signals signal soft_reset_i : std_logic := '0'; signal run_stop_clr : std_logic := '0'; signal tail_update_lsb : std_logic := '0'; signal tail_update_msb : std_logic := '0'; signal sg_cache_info : std_logic_vector (7 downto 0); signal halt_free : std_logic := '0'; signal tmp11 : std_logic := '0'; signal sig_cur_updated : std_logic := '0'; signal tailpntr_updated_d1 : std_logic; signal tailpntr_updated_d2 : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin GEN_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate begin halt_free <= '1'; end generate GEN_MULTI_CH; GEN_NOMULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate begin halt_free <= dmasr_i(DMASR_HALTED_BIT); end generate GEN_NOMULTI_CH; GEN_DESC_UPDATE_FOR_SG : if C_NUM_S2MM_CHANNELS = 1 generate begin update_curdesc1 <= '0'; update_curdesc2 <= '0'; update_curdesc3 <= '0'; update_curdesc4 <= '0'; update_curdesc5 <= '0'; update_curdesc6 <= '0'; update_curdesc7 <= '0'; update_curdesc8 <= '0'; update_curdesc9 <= '0'; update_curdesc10 <= '0'; update_curdesc11 <= '0'; update_curdesc12 <= '0'; update_curdesc13 <= '0'; update_curdesc14 <= '0'; update_curdesc15 <= '0'; end generate GEN_DESC_UPDATE_FOR_SG; dest0 <= '1' when tdest_in (4 downto 0) = "00000" else '0'; dest1 <= '1' when tdest_in (4 downto 0) = "00001" else '0'; dest2 <= '1' when tdest_in (4 downto 0) = "00010" else '0'; dest3 <= '1' when tdest_in (4 downto 0) = "00011" else '0'; dest4 <= '1' when tdest_in (4 downto 0) = "00100" else '0'; dest5 <= '1' when tdest_in (4 downto 0) = "00101" else '0'; dest6 <= '1' when tdest_in (4 downto 0) = "00110" else '0'; dest7 <= '1' when tdest_in (4 downto 0) = "00111" else '0'; dest8 <= '1' when tdest_in (4 downto 0) = "01000" else '0'; dest9 <= '1' when tdest_in (4 downto 0) = "01001" else '0'; dest10 <= '1' when tdest_in (4 downto 0) = "01010" else '0'; dest11 <= '1' when tdest_in (4 downto 0) = "01011" else '0'; dest12 <= '1' when tdest_in (4 downto 0) = "01100" else '0'; dest13 <= '1' when tdest_in (4 downto 0) = "01101" else '0'; dest14 <= '1' when tdest_in (4 downto 0) = "01110" else '0'; dest15 <= '1' when tdest_in (4 downto 0) = "01111" else '0'; GEN_DESC_UPDATE_FOR_SG_CH : if C_NUM_S2MM_CHANNELS > 1 generate update_curdesc1 <= update_curdesc when tdest_in (4 downto 0) = "00001" else '0'; update_curdesc2 <= update_curdesc when tdest_in (4 downto 0) = "00010" else '0'; update_curdesc3 <= update_curdesc when tdest_in (4 downto 0) = "00011" else '0'; update_curdesc4 <= update_curdesc when tdest_in (4 downto 0) = "00100" else '0'; update_curdesc5 <= update_curdesc when tdest_in (4 downto 0) = "00101" else '0'; update_curdesc6 <= update_curdesc when tdest_in (4 downto 0) = "00110" else '0'; update_curdesc7 <= update_curdesc when tdest_in (4 downto 0) = "00111" else '0'; update_curdesc8 <= update_curdesc when tdest_in (4 downto 0) = "01000" else '0'; update_curdesc9 <= update_curdesc when tdest_in (4 downto 0) = "01001" else '0'; update_curdesc10 <= update_curdesc when tdest_in (4 downto 0) = "01010" else '0'; update_curdesc11 <= update_curdesc when tdest_in (4 downto 0) = "01011" else '0'; update_curdesc12 <= update_curdesc when tdest_in (4 downto 0) = "01100" else '0'; update_curdesc13 <= update_curdesc when tdest_in (4 downto 0) = "01101" else '0'; update_curdesc14 <= update_curdesc when tdest_in (4 downto 0) = "01110" else '0'; update_curdesc15 <= update_curdesc when tdest_in (4 downto 0) = "01111" else '0'; end generate GEN_DESC_UPDATE_FOR_SG_CH; dmacr <= dmacr_i ; dmasr <= dmasr_i ; curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ; curdesc_msb <= curdesc_msb_i ; taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ; taildesc_msb <= taildesc_msb_i ; buffer_address <= buffer_address_i ; buffer_length <= buffer_length_i ; curdesc1_lsb <= curdesc1_lsb_i ; curdesc1_msb <= curdesc1_msb_i ; taildesc1_lsb <= taildesc1_lsb_i ; taildesc1_msb <= taildesc1_msb_i ; curdesc2_lsb <= curdesc2_lsb_i ; curdesc2_msb <= curdesc2_msb_i ; taildesc2_lsb <= taildesc2_lsb_i ; taildesc2_msb <= taildesc2_msb_i ; curdesc3_lsb <= curdesc3_lsb_i ; curdesc3_msb <= curdesc3_msb_i ; taildesc3_lsb <= taildesc3_lsb_i ; taildesc3_msb <= taildesc3_msb_i ; curdesc4_lsb <= curdesc4_lsb_i ; curdesc4_msb <= curdesc4_msb_i ; taildesc4_lsb <= taildesc4_lsb_i ; taildesc4_msb <= taildesc4_msb_i ; curdesc5_lsb <= curdesc5_lsb_i ; curdesc5_msb <= curdesc5_msb_i ; taildesc5_lsb <= taildesc5_lsb_i ; taildesc5_msb <= taildesc5_msb_i ; curdesc6_lsb <= curdesc6_lsb_i ; curdesc6_msb <= curdesc6_msb_i ; taildesc6_lsb <= taildesc6_lsb_i ; taildesc6_msb <= taildesc6_msb_i ; curdesc7_lsb <= curdesc7_lsb_i ; curdesc7_msb <= curdesc7_msb_i ; taildesc7_lsb <= taildesc7_lsb_i ; taildesc7_msb <= taildesc7_msb_i ; curdesc8_lsb <= curdesc8_lsb_i ; curdesc8_msb <= curdesc8_msb_i ; taildesc8_lsb <= taildesc8_lsb_i ; taildesc8_msb <= taildesc8_msb_i ; curdesc9_lsb <= curdesc9_lsb_i ; curdesc9_msb <= curdesc9_msb_i ; taildesc9_lsb <= taildesc9_lsb_i ; taildesc9_msb <= taildesc9_msb_i ; curdesc10_lsb <= curdesc10_lsb_i ; curdesc10_msb <= curdesc10_msb_i ; taildesc10_lsb <= taildesc10_lsb_i ; taildesc10_msb <= taildesc10_msb_i ; curdesc11_lsb <= curdesc11_lsb_i ; curdesc11_msb <= curdesc11_msb_i ; taildesc11_lsb <= taildesc11_lsb_i ; taildesc11_msb <= taildesc11_msb_i ; curdesc12_lsb <= curdesc12_lsb_i ; curdesc12_msb <= curdesc12_msb_i ; taildesc12_lsb <= taildesc12_lsb_i ; taildesc12_msb <= taildesc12_msb_i ; curdesc13_lsb <= curdesc13_lsb_i ; curdesc13_msb <= curdesc13_msb_i ; taildesc13_lsb <= taildesc13_lsb_i ; taildesc13_msb <= taildesc13_msb_i ; curdesc14_lsb <= curdesc14_lsb_i ; curdesc14_msb <= curdesc14_msb_i ; taildesc14_lsb <= taildesc14_lsb_i ; taildesc14_msb <= taildesc14_msb_i ; curdesc15_lsb <= curdesc15_lsb_i ; curdesc15_msb <= curdesc15_msb_i ; taildesc15_lsb <= taildesc15_lsb_i ; taildesc15_msb <= taildesc15_msb_i ; --------------------------------------------------------------------------- -- DMA Control Register --------------------------------------------------------------------------- -- DMACR - Interrupt Delay Value ------------------------------------------------------------------------------- DMACR_DELAY : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0'); elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT); end if; end if; end process DMACR_DELAY; -- If written delay is different than previous value then assert write enable different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT) else '0'; -- delay value different, drive write of delay value to interrupt controller NEW_DELAY_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqdelay_wren <= '0'; -- If AXI Lite write to DMACR and delay different than current -- setting then update delay value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then irqdelay_wren <= '1'; else irqdelay_wren <= '0'; end if; end if; end process NEW_DELAY_WRITE; ------------------------------------------------------------------------------- -- DMACR - Interrupt Threshold Value ------------------------------------------------------------------------------- threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD else '0'; DMACR_THRESH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- On AXI Lite write elsif(axi2ip_wrce(DMACR_INDEX) = '1')then -- If value is 0 then set threshold to 1 if(threshold_is_zero='1')then dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD; -- else set threshold to axi lite wrdata value else dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT); end if; end if; end if; end process DMACR_THRESH; -- If written threshold is different than previous value then assert write enable different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) /= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) else '0'; -- new treshold written therefore drive write of threshold out NEW_THRESH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then irqthresh_wren <= '0'; -- If AXI Lite write to DMACR and threshold different than current -- setting then update threshold value elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then irqthresh_wren <= '1'; else irqthresh_wren <= '0'; end if; end if; end process NEW_THRESH_WRITE; ------------------------------------------------------------------------------- -- DMACR - Remainder of DMA Control Register, Key Hole write bit (3) ------------------------------------------------------------------------------- DMACR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 downto DMACR_RESERVED5_BIT) <= (others => '0'); dmacr_i(DMACR_KH_BIT) <= '0'; dmacr_i(CYCLIC_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15 downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT) -- bit 14 & axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 13 & axi2ip_wrdata(DMACR_DLY_IRQEN_BIT) -- bit 12 & axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bits 11 downto 3 & ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT); dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT); dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT); end if; end if; end process DMACR_REGISTER; ------------------------------------------------------------------------------- -- DMACR - Reset Bit ------------------------------------------------------------------------------- DMACR_RESET : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(soft_reset_clr = '1')then dmacr_i(DMACR_RESET_BIT) <= '0'; -- If soft reset set in other channel then set -- reset bit here too elsif(soft_reset_in = '1')then dmacr_i(DMACR_RESET_BIT) <= '1'; -- If DMACR Write then pass axi lite write bus to DMARC reset bit elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT); end if; end if; end process DMACR_RESET; soft_reset_i <= dmacr_i(DMACR_RESET_BIT); ------------------------------------------------------------------------------- -- Tail Pointer Enable fixed at 1 for this release of axi dma ------------------------------------------------------------------------------- dmacr_i(DMACR_TAILPEN_BIT) <= '1'; ------------------------------------------------------------------------------- -- DMACR - Run/Stop Bit ------------------------------------------------------------------------------- run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error or error_in = '1' -- S2MM Error or stop_dma = '1' -- Stop due to error or soft_reset_i = '1' -- MM2S Soft Reset or soft_reset_in = '1' -- S2MM Soft Reset else '0'; DMACR_RUNSTOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dmacr_i(DMACR_RS_BIT) <= '0'; -- Clear on sg error (i.e. error) or other channel -- error (i.e. error_in) or dma error or soft reset elsif(run_stop_clr = '1')then dmacr_i(DMACR_RS_BIT) <= '0'; elsif(axi2ip_wrce(DMACR_INDEX) = '1')then dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT); end if; end if; end process DMACR_RUNSTOP; --------------------------------------------------------------------------- -- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA -- channel is halted. --------------------------------------------------------------------------- DMASR_HALTED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or halted_set = '1')then halted <= '1'; elsif(halted_clr = '1')then halted <= '0'; end if; end if; end process DMASR_HALTED; --------------------------------------------------------------------------- -- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA -- channel is IDLE waiting at tail pointer. Update of Tail Pointer -- will cause engine to resume. Note: Halted channels return to a -- reset condition. --------------------------------------------------------------------------- DMASR_IDLE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or idle_clr = '1' or halted_set = '1')then idle <= '0'; elsif(idle_set = '1')then idle <= '1'; end if; end if; end process DMASR_IDLE; --------------------------------------------------------------------------- -- DMA Status Error bit (BIT 3) -- Note: any error will cause entire engine to halt --------------------------------------------------------------------------- error <= dma_interr or dma_slverr or dma_decerr or sg_interr or sg_slverr or sg_decerr; -- Scatter Gather Error --sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; -- SG Update Errors or DMA errors assert flag on descriptor update -- Used to latch current descriptor pointer --sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set -- or dma_interr or dma_slverr or dma_decerr; -- Map out to halt opposing channel error_out <= error; SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_ftch_error <= '0'; sg_updt_error <= '0'; else sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set; sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set or dma_interr or dma_slverr or dma_decerr; end if; end if; end process SG_FTCH_ERROR_PROC; --------------------------------------------------------------------------- -- DMA Status DMA Internal Error bit (BIT 4) --------------------------------------------------------------------------- DMASR_DMAINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_interr <= '0'; elsif(dma_interr_set = '1' )then dma_interr <= '1'; end if; end if; end process DMASR_DMAINTERR; --------------------------------------------------------------------------- -- DMA Status DMA Slave Error bit (BIT 5) --------------------------------------------------------------------------- DMASR_DMASLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_slverr <= '0'; elsif(dma_slverr_set = '1' )then dma_slverr <= '1'; end if; end if; end process DMASR_DMASLVERR; --------------------------------------------------------------------------- -- DMA Status DMA Decode Error bit (BIT 6) --------------------------------------------------------------------------- DMASR_DMADECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dma_decerr <= '0'; elsif(dma_decerr_set = '1' )then dma_decerr <= '1'; end if; end if; end process DMASR_DMADECERR; --------------------------------------------------------------------------- -- DMA Status SG Internal Error bit (BIT 8) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGINTERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_interr <= '0'; elsif(ftch_interr_set = '1' or updt_interr_set = '1')then sg_interr <= '1'; end if; end if; end process DMASR_SGINTERR; --------------------------------------------------------------------------- -- DMA Status SG Slave Error bit (BIT 9) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGSLVERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_slverr <= '0'; elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then sg_slverr <= '1'; end if; end if; end process DMASR_SGSLVERR; --------------------------------------------------------------------------- -- DMA Status SG Decode Error bit (BIT 10) -- (SG Mode only - trimmed at build time if simple mode) --------------------------------------------------------------------------- DMASR_SGDECERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_decerr <= '0'; elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then sg_decerr <= '1'; end if; end if; end process DMASR_SGDECERR; --------------------------------------------------------------------------- -- DMA Status IOC Interrupt status bit (BIT 11) --------------------------------------------------------------------------- DMASR_IOCIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ioc_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT))) or ioc_irq_set; elsif(ioc_irq_set = '1')then ioc_irq <= '1'; end if; end if; end process DMASR_IOCIRQ; --------------------------------------------------------------------------- -- DMA Status Delay Interrupt status bit (BIT 12) --------------------------------------------------------------------------- DMASR_DLYIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then dly_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT))) or dly_irq_set; elsif(dly_irq_set = '1')then dly_irq <= '1'; end if; end if; end process DMASR_DLYIRQ; -- CR605888 Disable delay timer if halted or on delay irq set --dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348 dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348 or dmasr_i(DMASR_DLYIRQ_BIT); --------------------------------------------------------------------------- -- DMA Status Error Interrupt status bit (BIT 12) --------------------------------------------------------------------------- -- Delay error setting for generation of error strobe GEN_ERROR_RE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then error_d1 <= '0'; else error_d1 <= error; end if; end if; end process GEN_ERROR_RE; -- Generate rising edge pulse on error error_re <= error and not error_d1; DMASR_ERRIRQ : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then err_irq <= '0'; -- CPU Writing a '1' to clear - OR'ed with setting to prevent -- missing a 'set' during the write. elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT))) or error_re; elsif(error_re = '1')then err_irq <= '1'; end if; end if; end process DMASR_ERRIRQ; --------------------------------------------------------------------------- -- DMA Interrupt OUT --------------------------------------------------------------------------- REG_INTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then introut <= '0'; else introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT)) or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT)) or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT)); end if; end if; end process; --------------------------------------------------------------------------- -- DMA Status Register --------------------------------------------------------------------------- dmasr_i <= irqdelay_status -- Bits 31 downto 24 & irqthresh_status -- Bits 23 downto 16 & '0' -- Bit 15 & err_irq -- Bit 14 & dly_irq -- Bit 13 & ioc_irq -- Bit 12 & '0' -- Bit 11 & sg_decerr -- Bit 10 & sg_slverr -- Bit 9 & sg_interr -- Bit 8 & '0' -- Bit 7 & dma_decerr -- Bit 6 & dma_slverr -- Bit 5 & dma_interr -- Bit 4 & DMA_CONFIG -- Bit 3 & '0' -- Bit 2 & idle -- Bit 1 & halted; -- Bit 0 -- Generate current descriptor and tail descriptor register for Scatter Gather Mode GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate begin GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate begin MM2S_SGCTL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sg_cache_info <= "00000011"; --(others => '0'); elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0); else sg_cache_info <= sg_cache_info; end if; end if; end process MM2S_SGCTL; sg_ctl <= sg_cache_info; end generate GEN_SG_CTL_REG; GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate begin sg_ctl <= "00000011"; --(others => '0'); end generate GEN_SG_NO_CTL_REG; -- Signals not used for Scatter Gather Mode, only simple mode buffer_address_i <= (others => '0'); buffer_length_i <= (others => '0'); buffer_length_wren <= '0'; --------------------------------------------------------------------------- -- Current Descriptor LSB Register --------------------------------------------------------------------------- CURDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_lsb_i <= (others => '0'); error_pointer_set <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest0 = '1')then curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest0 = '1')then -- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6); error_pointer_set <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and halt_free = '1')then curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(CURDESC_RESERVED_BIT5 -- downto CURDESC_RESERVED_BIT0); error_pointer_set <= '0'; end if; end if; end if; end process CURDESC_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT); -- & ZERO_VALUE(TAILDESC_RESERVED_BIT5 -- downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC_LSB_REGISTER; GEN_DESC1_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_lsb_i <= (others => '0'); error_pointer_set1 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set1 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set1 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_LSB_INDEX) = '1' and halt_free = '1')then curdesc1_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set1 <= '0'; end if; end if; end if; end process CURDESC1_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC1_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_LSB_INDEX) = '1')then taildesc1_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC1_LSB_REGISTER; end generate GEN_DESC1_REG_FOR_SG; GEN_DESC2_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_lsb_i <= (others => '0'); error_pointer_set2 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set2 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set2 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_LSB_INDEX) = '1' and halt_free = '1')then curdesc2_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set2 <= '0'; end if; end if; end if; end process CURDESC2_LSB_REGISTER; TAILDESC2_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_LSB_INDEX) = '1')then taildesc2_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC2_LSB_REGISTER; end generate GEN_DESC2_REG_FOR_SG; GEN_DESC3_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_lsb_i <= (others => '0'); error_pointer_set3 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set3 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set3 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_LSB_INDEX) = '1' and halt_free = '1')then curdesc3_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set3 <= '0'; end if; end if; end if; end process CURDESC3_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC3_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_LSB_INDEX) = '1')then taildesc3_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC3_LSB_REGISTER; end generate GEN_DESC3_REG_FOR_SG; GEN_DESC4_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_lsb_i <= (others => '0'); error_pointer_set4 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set4 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set4 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_LSB_INDEX) = '1' and halt_free = '1')then curdesc4_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set4 <= '0'; end if; end if; end if; end process CURDESC4_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC4_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_LSB_INDEX) = '1')then taildesc4_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC4_LSB_REGISTER; end generate GEN_DESC4_REG_FOR_SG; GEN_DESC5_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_lsb_i <= (others => '0'); error_pointer_set5 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set5 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set5 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_LSB_INDEX) = '1' and halt_free = '1')then curdesc5_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set5 <= '0'; end if; end if; end if; end process CURDESC5_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC5_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_LSB_INDEX) = '1')then taildesc5_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC5_LSB_REGISTER; end generate GEN_DESC5_REG_FOR_SG; GEN_DESC6_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_lsb_i <= (others => '0'); error_pointer_set6 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set6 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set6 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_LSB_INDEX) = '1' and halt_free = '1')then curdesc6_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set6 <= '0'; end if; end if; end if; end process CURDESC6_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC6_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_LSB_INDEX) = '1')then taildesc6_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC6_LSB_REGISTER; end generate GEN_DESC6_REG_FOR_SG; GEN_DESC7_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_lsb_i <= (others => '0'); error_pointer_set7 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set7 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set7 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_LSB_INDEX) = '1' and halt_free = '1')then curdesc7_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set7 <= '0'; end if; end if; end if; end process CURDESC7_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC7_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_LSB_INDEX) = '1')then taildesc7_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC7_LSB_REGISTER; end generate GEN_DESC7_REG_FOR_SG; GEN_DESC8_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_lsb_i <= (others => '0'); error_pointer_set8 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set8 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set8 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_LSB_INDEX) = '1' and halt_free = '1')then curdesc8_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set8 <= '0'; end if; end if; end if; end process CURDESC8_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC8_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_LSB_INDEX) = '1')then taildesc8_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC8_LSB_REGISTER; end generate GEN_DESC8_REG_FOR_SG; GEN_DESC9_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_lsb_i <= (others => '0'); error_pointer_set9 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set9 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set9 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_LSB_INDEX) = '1' and halt_free = '1')then curdesc9_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set9 <= '0'; end if; end if; end if; end process CURDESC9_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC9_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_LSB_INDEX) = '1')then taildesc9_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC9_LSB_REGISTER; end generate GEN_DESC9_REG_FOR_SG; GEN_DESC10_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_lsb_i <= (others => '0'); error_pointer_set10 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set10 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set10 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_LSB_INDEX) = '1' and halt_free = '1')then curdesc10_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set10 <= '0'; end if; end if; end if; end process CURDESC10_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC10_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_LSB_INDEX) = '1')then taildesc10_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC10_LSB_REGISTER; end generate GEN_DESC10_REG_FOR_SG; GEN_DESC11_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_lsb_i <= (others => '0'); error_pointer_set11 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set11 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set11 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_LSB_INDEX) = '1' and halt_free = '1')then curdesc11_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set11 <= '0'; end if; end if; end if; end process CURDESC11_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC11_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_LSB_INDEX) = '1')then taildesc11_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC11_LSB_REGISTER; end generate GEN_DESC11_REG_FOR_SG; GEN_DESC12_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_lsb_i <= (others => '0'); error_pointer_set12 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set12 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set12 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_LSB_INDEX) = '1' and halt_free = '1')then curdesc12_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set12 <= '0'; end if; end if; end if; end process CURDESC12_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC12_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_LSB_INDEX) = '1')then taildesc12_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC12_LSB_REGISTER; end generate GEN_DESC12_REG_FOR_SG; GEN_DESC13_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_lsb_i <= (others => '0'); error_pointer_set13 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set13 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set13 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_LSB_INDEX) = '1' and halt_free = '1')then curdesc13_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set13 <= '0'; end if; end if; end if; end process CURDESC13_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC13_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_LSB_INDEX) = '1')then taildesc13_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC13_LSB_REGISTER; end generate GEN_DESC13_REG_FOR_SG; GEN_DESC14_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_lsb_i <= (others => '0'); error_pointer_set14 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set14 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set14 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_LSB_INDEX) = '1' and halt_free = '1')then curdesc14_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set14 <= '0'; end if; end if; end if; end process CURDESC14_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC14_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_LSB_INDEX) = '1')then taildesc14_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC14_LSB_REGISTER; end generate GEN_DESC14_REG_FOR_SG; GEN_DESC15_REG_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_lsb_i <= (others => '0'); error_pointer_set15 <= '0'; -- Detected error has NOT register a desc pointer elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '1'; -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); -- error_pointer_set15 <= '1'; -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); error_pointer_set15 <= '0'; -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_LSB_INDEX) = '1' and halt_free = '1')then curdesc15_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT downto CURDESC_LOWER_LSB_BIT) & ZERO_VALUE(CURDESC_RESERVED_BIT5 downto CURDESC_RESERVED_BIT0); error_pointer_set15 <= '0'; end if; end if; end if; end process CURDESC15_LSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor LSB Register --------------------------------------------------------------------------- TAILDESC15_LSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_lsb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_LSB_INDEX) = '1')then taildesc15_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT downto TAILDESC_LOWER_LSB_BIT) & ZERO_VALUE(TAILDESC_RESERVED_BIT5 downto TAILDESC_RESERVED_BIT0); end if; end if; end process TAILDESC15_LSB_REGISTER; end generate GEN_DESC15_REG_FOR_SG; --------------------------------------------------------------------------- -- Current Descriptor MSB Register --------------------------------------------------------------------------- -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin CURDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc_msb_i <= (others => '0'); elsif(error_pointer_set = '0')then -- Scatter Gather Fetch Error if(sg_ftch_error = '1' and dest0 = '1')then curdesc_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error elsif(sg_updt_error = '1' and dest0 = '1')then curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest0 = '1')then curdesc_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and halt_free = '1')then curdesc_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then taildesc_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC_MSB_REGISTER; GEN_DESC1_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 1 generate CURDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc1_msb_i <= (others => '0'); elsif(error_pointer_set1 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest1 = '1')then curdesc1_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest1 = '1')then -- curdesc1_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc1 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest1 = '1')then curdesc1_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC1_MSB_INDEX) = '1' and halt_free = '1')then curdesc1_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC1_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC1_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc1_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC1_MSB_INDEX) = '1')then taildesc1_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC1_MSB_REGISTER; end generate GEN_DESC1_MSB_FOR_SG; GEN_DESC2_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 2 generate CURDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc2_msb_i <= (others => '0'); elsif(error_pointer_set2 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest2 = '1')then curdesc2_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest2 = '1')then -- curdesc2_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc2 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest2 = '1')then curdesc2_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC2_MSB_INDEX) = '1' and halt_free = '1')then curdesc2_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC2_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC2_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc2_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC2_MSB_INDEX) = '1')then taildesc2_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC2_MSB_REGISTER; end generate GEN_DESC2_MSB_FOR_SG; GEN_DESC3_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 3 generate CURDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc3_msb_i <= (others => '0'); elsif(error_pointer_set3 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest3 = '1')then curdesc3_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest3 = '1')then -- curdesc3_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc3 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest3 = '1')then curdesc3_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC3_MSB_INDEX) = '1' and halt_free = '1')then curdesc3_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC3_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC3_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc3_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC3_MSB_INDEX) = '1')then taildesc3_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC3_MSB_REGISTER; end generate GEN_DESC3_MSB_FOR_SG; GEN_DESC4_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 4 generate CURDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc4_msb_i <= (others => '0'); elsif(error_pointer_set4 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest4 = '1')then curdesc4_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest4 = '1')then -- curdesc4_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc4 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest4 = '1')then curdesc4_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC4_MSB_INDEX) = '1' and halt_free = '1')then curdesc4_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC4_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC4_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc4_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC4_MSB_INDEX) = '1')then taildesc4_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC4_MSB_REGISTER; end generate GEN_DESC4_MSB_FOR_SG; GEN_DESC5_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 5 generate CURDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc5_msb_i <= (others => '0'); elsif(error_pointer_set5 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest5 = '1')then curdesc5_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest5 = '1')then -- curdesc5_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc5 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest5 = '1')then curdesc5_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC5_MSB_INDEX) = '1' and halt_free = '1')then curdesc5_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC5_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC5_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc5_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC5_MSB_INDEX) = '1')then taildesc5_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC5_MSB_REGISTER; end generate GEN_DESC5_MSB_FOR_SG; GEN_DESC6_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 6 generate CURDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc6_msb_i <= (others => '0'); elsif(error_pointer_set6 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest6 = '1')then curdesc6_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest6 = '1')then -- curdesc6_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc6 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest6 = '1')then curdesc6_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC6_MSB_INDEX) = '1' and halt_free = '1')then curdesc6_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC6_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC6_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc6_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC6_MSB_INDEX) = '1')then taildesc6_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC6_MSB_REGISTER; end generate GEN_DESC6_MSB_FOR_SG; GEN_DESC7_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 7 generate CURDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc7_msb_i <= (others => '0'); elsif(error_pointer_set7 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest7 = '1')then curdesc7_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest7 = '1')then -- curdesc7_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc7 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest7 = '1')then curdesc7_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC7_MSB_INDEX) = '1' and halt_free = '1')then curdesc7_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC7_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC7_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc7_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC7_MSB_INDEX) = '1')then taildesc7_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC7_MSB_REGISTER; end generate GEN_DESC7_MSB_FOR_SG; GEN_DESC8_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 8 generate CURDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc8_msb_i <= (others => '0'); elsif(error_pointer_set8 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest8 = '1')then curdesc8_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest8 = '1')then -- curdesc8_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc8 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest8 = '1')then curdesc8_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC8_MSB_INDEX) = '1' and halt_free = '1')then curdesc8_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC8_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC8_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc8_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC8_MSB_INDEX) = '1')then taildesc8_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC8_MSB_REGISTER; end generate GEN_DESC8_MSB_FOR_SG; GEN_DESC9_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 9 generate CURDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc9_msb_i <= (others => '0'); elsif(error_pointer_set9 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest9 = '1')then curdesc9_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest9 = '1')then -- curdesc9_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc9 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest9 = '1')then curdesc9_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC9_MSB_INDEX) = '1' and halt_free = '1')then curdesc9_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC9_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC9_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc9_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC9_MSB_INDEX) = '1')then taildesc9_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC9_MSB_REGISTER; end generate GEN_DESC9_MSB_FOR_SG; GEN_DESC10_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 10 generate CURDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc10_msb_i <= (others => '0'); elsif(error_pointer_set10 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest10 = '1')then curdesc10_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest10 = '1')then -- curdesc10_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc10 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest10 = '1')then curdesc10_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC10_MSB_INDEX) = '1' and halt_free = '1')then curdesc10_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC10_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC10_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc10_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC10_MSB_INDEX) = '1')then taildesc10_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC10_MSB_REGISTER; end generate GEN_DESC10_MSB_FOR_SG; GEN_DESC11_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 11 generate CURDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc11_msb_i <= (others => '0'); elsif(error_pointer_set11 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest11 = '1')then curdesc11_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest11 = '1')then -- curdesc11_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc11 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest11 = '1')then curdesc11_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC11_MSB_INDEX) = '1' and halt_free = '1')then curdesc11_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC11_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC11_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc11_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC11_MSB_INDEX) = '1')then taildesc11_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC11_MSB_REGISTER; end generate GEN_DESC11_MSB_FOR_SG; GEN_DESC12_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 12 generate CURDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc12_msb_i <= (others => '0'); elsif(error_pointer_set12 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest12 = '1')then curdesc12_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest12 = '1')then -- curdesc12_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc12 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest12 = '1')then curdesc12_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC12_MSB_INDEX) = '1' and halt_free = '1')then curdesc12_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC12_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC12_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc12_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC12_MSB_INDEX) = '1')then taildesc12_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC12_MSB_REGISTER; end generate GEN_DESC12_MSB_FOR_SG; GEN_DESC13_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 13 generate CURDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc13_msb_i <= (others => '0'); elsif(error_pointer_set13 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest13 = '1')then curdesc13_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest13 = '1')then -- curdesc13_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc13 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest13 = '1')then curdesc13_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC13_MSB_INDEX) = '1' and halt_free = '1')then curdesc13_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC13_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC13_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc13_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC13_MSB_INDEX) = '1')then taildesc13_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC13_MSB_REGISTER; end generate GEN_DESC13_MSB_FOR_SG; GEN_DESC14_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 14 generate CURDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc14_msb_i <= (others => '0'); elsif(error_pointer_set14 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest14 = '1')then curdesc14_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest14 = '1')then -- curdesc14_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc14 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest14 = '1')then curdesc14_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC14_MSB_INDEX) = '1' and halt_free = '1')then curdesc14_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC14_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC14_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc14_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC14_MSB_INDEX) = '1')then taildesc14_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC14_MSB_REGISTER; end generate GEN_DESC14_MSB_FOR_SG; GEN_DESC15_MSB_FOR_SG : if C_NUM_S2MM_CHANNELS > 15 generate CURDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then curdesc15_msb_i <= (others => '0'); elsif(error_pointer_set15 = '0')then -- Scatter Gather Fetch Error if((sg_ftch_error = '1' or sg_updt_error = '1') and dest15 = '1')then curdesc15_msb_i <= ftch_error_addr((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- Scatter Gather Update Error -- elsif(sg_updt_error = '1' and dest15 = '1')then -- curdesc15_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH -- - C_S_AXI_LITE_DATA_WIDTH)-1 -- downto 0); -- Commanded to update descriptor value - used for indicating -- current descriptor begin processed by dma controller elsif(update_curdesc15 = '1' and dmacr_i(DMACR_RS_BIT) = '1' and dest15 = '1')then curdesc15_msb_i <= new_curdesc ((C_M_AXI_SG_ADDR_WIDTH - C_S_AXI_LITE_DATA_WIDTH)-1 downto 0); -- CPU update of current descriptor pointer. CPU -- only allowed to update when engine is halted. elsif(axi2ip_wrce(CURDESC15_MSB_INDEX) = '1' and halt_free = '1')then curdesc15_msb_i <= axi2ip_wrdata; end if; end if; end if; end process CURDESC15_MSB_REGISTER; --------------------------------------------------------------------------- -- Tail Descriptor MSB Register --------------------------------------------------------------------------- TAILDESC15_MSB_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then taildesc15_msb_i <= (others => '0'); elsif(axi2ip_wrce(TAILDESC15_MSB_INDEX) = '1')then taildesc15_msb_i <= axi2ip_wrdata; end if; end if; end process TAILDESC15_MSB_REGISTER; end generate GEN_DESC15_MSB_FOR_SG; end generate GEN_SG_ADDR_EQL64; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin curdesc_msb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to the extra registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); end generate GEN_SG_ADDR_EQL32; -- Scatter Gather Interface configured for 32-Bit SG Addresses GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin -- Added dest so that BD can be dynamically updated GENERATE_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 1 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_LSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_LSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_LSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_LSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_LSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_LSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_LSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_LSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_LSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_LSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_LSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_LSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_LSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_LSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_LSB_INDEX) and dest15); end generate GENERATE_MULTI_CH; GENERATE_NO_MULTI_CH : if C_ENABLE_MULTI_CHANNEL = 0 generate tail_update_lsb <= (axi2ip_wrce(TAILDESC_LSB_INDEX) and dest0); end generate GENERATE_NO_MULTI_CH; TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_lsb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL32; -- Scatter Gather Interface configured for 64-Bit SG Addresses GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin -- Added dest so that BD can be dynamically updated tail_update_msb <= (axi2ip_wrce(TAILDESC_MSB_INDEX) and dest0) or (axi2ip_wrce(TAILDESC1_MSB_INDEX) and dest1) or (axi2ip_wrce(TAILDESC2_MSB_INDEX) and dest2) or (axi2ip_wrce(TAILDESC3_MSB_INDEX) and dest3) or (axi2ip_wrce(TAILDESC4_MSB_INDEX) and dest4) or (axi2ip_wrce(TAILDESC5_MSB_INDEX) and dest5) or (axi2ip_wrce(TAILDESC6_MSB_INDEX) and dest6) or (axi2ip_wrce(TAILDESC7_MSB_INDEX) and dest7) or (axi2ip_wrce(TAILDESC8_MSB_INDEX) and dest8) or (axi2ip_wrce(TAILDESC9_MSB_INDEX) and dest9) or (axi2ip_wrce(TAILDESC10_MSB_INDEX) and dest10) or (axi2ip_wrce(TAILDESC11_MSB_INDEX) and dest11) or (axi2ip_wrce(TAILDESC12_MSB_INDEX) and dest12) or (axi2ip_wrce(TAILDESC13_MSB_INDEX) and dest13) or (axi2ip_wrce(TAILDESC14_MSB_INDEX) and dest14) or (axi2ip_wrce(TAILDESC15_MSB_INDEX) and dest15); -- tail_update_msb <= axi2ip_wrce(TAILDESC_MSB_INDEX) or -- axi2ip_wrce(TAILDESC1_MSB_INDEX) or -- axi2ip_wrce(TAILDESC2_MSB_INDEX) or -- axi2ip_wrce(TAILDESC3_MSB_INDEX) or -- axi2ip_wrce(TAILDESC4_MSB_INDEX) or -- axi2ip_wrce(TAILDESC5_MSB_INDEX) or -- axi2ip_wrce(TAILDESC6_MSB_INDEX) or -- axi2ip_wrce(TAILDESC7_MSB_INDEX) or -- axi2ip_wrce(TAILDESC8_MSB_INDEX) or -- axi2ip_wrce(TAILDESC9_MSB_INDEX) or -- axi2ip_wrce(TAILDESC10_MSB_INDEX) or -- axi2ip_wrce(TAILDESC11_MSB_INDEX) or -- axi2ip_wrce(TAILDESC12_MSB_INDEX) or -- axi2ip_wrce(TAILDESC13_MSB_INDEX) or -- axi2ip_wrce(TAILDESC14_MSB_INDEX) or -- axi2ip_wrce(TAILDESC15_MSB_INDEX); TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then tailpntr_updated_d1 <= '0'; elsif (tail_update_msb = '1' and tdest_in(5) = '0')then tailpntr_updated_d1 <= '1'; else tailpntr_updated_d1 <= '0'; end if; end if; end process TAILPNTR_UPDT_PROCESS; TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tailpntr_updated_d2 <= '0'; else tailpntr_updated_d2 <= tailpntr_updated_d1; end if; end if; end process TAILPNTR_UPDT_PROCESS_DEL; tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2); end generate GEN_TAILUPDATE_EQL64; end generate GEN_DESC_REG_FOR_SG; -- Generate Buffer Address and Length Register for Simple DMA Mode GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate begin -- Signals not used for simple dma mode, only for sg mode curdesc_lsb_i <= (others => '0'); curdesc_msb_i <= (others => '0'); taildesc_lsb_i <= (others => '0'); taildesc_msb_i <= (others => '0'); -- Extending this to new registers curdesc1_msb_i <= (others => '0'); taildesc1_msb_i <= (others => '0'); curdesc2_msb_i <= (others => '0'); taildesc2_msb_i <= (others => '0'); curdesc3_msb_i <= (others => '0'); taildesc3_msb_i <= (others => '0'); curdesc4_msb_i <= (others => '0'); taildesc4_msb_i <= (others => '0'); curdesc5_msb_i <= (others => '0'); taildesc5_msb_i <= (others => '0'); curdesc6_msb_i <= (others => '0'); taildesc6_msb_i <= (others => '0'); curdesc7_msb_i <= (others => '0'); taildesc7_msb_i <= (others => '0'); curdesc8_msb_i <= (others => '0'); taildesc8_msb_i <= (others => '0'); curdesc9_msb_i <= (others => '0'); taildesc9_msb_i <= (others => '0'); curdesc10_msb_i <= (others => '0'); taildesc10_msb_i <= (others => '0'); curdesc11_msb_i <= (others => '0'); taildesc11_msb_i <= (others => '0'); curdesc12_msb_i <= (others => '0'); taildesc12_msb_i <= (others => '0'); curdesc13_msb_i <= (others => '0'); taildesc13_msb_i <= (others => '0'); curdesc14_msb_i <= (others => '0'); taildesc14_msb_i <= (others => '0'); curdesc15_msb_i <= (others => '0'); taildesc15_msb_i <= (others => '0'); curdesc1_lsb_i <= (others => '0'); taildesc1_lsb_i <= (others => '0'); curdesc2_lsb_i <= (others => '0'); taildesc2_lsb_i <= (others => '0'); curdesc3_lsb_i <= (others => '0'); taildesc3_lsb_i <= (others => '0'); curdesc4_lsb_i <= (others => '0'); taildesc4_lsb_i <= (others => '0'); curdesc5_lsb_i <= (others => '0'); taildesc5_lsb_i <= (others => '0'); curdesc6_lsb_i <= (others => '0'); taildesc6_lsb_i <= (others => '0'); curdesc7_lsb_i <= (others => '0'); taildesc7_lsb_i <= (others => '0'); curdesc8_lsb_i <= (others => '0'); taildesc8_lsb_i <= (others => '0'); curdesc9_lsb_i <= (others => '0'); taildesc9_lsb_i <= (others => '0'); curdesc10_lsb_i <= (others => '0'); taildesc10_lsb_i <= (others => '0'); curdesc11_lsb_i <= (others => '0'); taildesc11_lsb_i <= (others => '0'); curdesc12_lsb_i <= (others => '0'); taildesc12_lsb_i <= (others => '0'); curdesc13_lsb_i <= (others => '0'); taildesc13_lsb_i <= (others => '0'); curdesc14_lsb_i <= (others => '0'); taildesc14_lsb_i <= (others => '0'); curdesc15_lsb_i <= (others => '0'); taildesc15_lsb_i <= (others => '0'); tailpntr_updated <= '0'; error_pointer_set <= '0'; -- Buffer Address register. Used for Source Address (SA) if MM2S -- and used for Destination Address (DA) if S2MM BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_address_i <= (others => '0'); elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then buffer_address_i <= axi2ip_wrdata; end if; end if; end process BUFFER_ADDR_REGISTER; -- Buffer Length register. Used for number of bytes to transfer if MM2S -- and used for size of receive buffer is S2MM BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_i <= (others => '0'); -- Update with actual bytes received (Only for S2MM channel) elsif(bytes_received_wren = '1' and C_MICRO_DMA = 0)then buffer_length_i <= bytes_received; elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0); end if; end if; end process BUFFER_LNGTH_REGISTER; -- Buffer Length Write Enable control. Assertion of wren will -- begin a transfer if channel is Idle. BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then buffer_length_wren <= '0'; -- Non-zero length value written elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1' and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then buffer_length_wren <= '1'; else buffer_length_wren <= '0'; end if; end if; end process BUFFER_LNGTH_WRITE; end generate GEN_REG_FOR_SMPL; end implementation;
bsd-2-clause
c2283bb78711ee0fb0fc57ca2f7caffa
0.433843
4.278804
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/vhdlFile/component_declaration/classification_inside_package_declarative_item_test_input.vhd
1
687
architecture RTL of FIFO is component COMP is end component COMP; component COMP end component COMP; component COMP end component; -- test with generics component COMP is generic ( G_GEN1 : integer := 1; G_GEN2 : integer := 0 ); end component COMP; -- test with ports component COMP is port ( I_PORT : in integer := 1; O_PORT : out integer := 0 ); end component COMP; -- test with both component COMP is generic ( G_GEN1 : integer := 1; G_GEN2 : integer := 0 ); port ( I_PORT : in integer := 1; O_PORT : out integer := 0 ); end component COMP; end architecture RTL;
gpl-3.0
d56d0294f8bc709b65e57d8a93479e28
0.576419
3.925714
false
true
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd
2
32,006
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bsd-2-clause
5a8b8342cc52691e9c8f140ca3e551d9
0.947385
1.816149
false
false
false
false
cwilkens/ecen4024-microphone-array
microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/axi_utils_v2_0/hdl/glb_srl_fifo.vhd
3
35,288
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block kVk7NjfT4rUeDjbNh3KaKqx8aJSpUjFkiZ7HcCWAacoIHVVPoRq5tMtjup/PsKSPAvFLAMmkPti7 Nn7PAutsQw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XxzKRua2xRuq4U7gx6gch//fIXrW2sjuVuACfxkVmSOl0JwUQHZQZ5kPp+Nq8KIjrw2WK0liGidW WnS2B0l4lCoTJOToGu8Fbpqsz8R/2KU8xnLn/30gaXuvq8is6W0U6r1MJ8PNW79xY3WxHJ47cJqc nCTAXjT4l3Ntn+V50Ls= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit
70a5ab7319921b14a35b2ffb22c24aec
0.946752
1.833333
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/conditional_waveforms/rule_500_test_input.fixed_lower.vhd
1
400
architecture rtl of fifo is begin process begin var1 := '0' WHEN rd_en = '1' else '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' WHEN rd_en = '1' else '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' when rd_en = '1' else '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;
gpl-3.0
bd6ea1bc7be3a4f2da26cd04b183dc08
0.54
2.564103
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/instantiation/rule_027_test_input.fixed_lower.vhd
1
565
architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : entity fifo_dsn.1clk_fifo port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : entity fifo_dsn.1clk_fifo port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;
gpl-3.0
cfc460715dc774ff19cb6624c7b0a0f1
0.493805
2.742718
false
false
false
false
cwilkens/ecen4024-microphone-array
microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/halfband_decimation.vhd
2
339,334
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RzhECzT+9ycWh1bgnkpz56bWSMlOS2C2qo/ehOaT3WPvy013PYz4OZ5v0LrNvNJ1mw2s1DnGQ1Em kLAQwYDipg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block o+fP5UbR/yhpfo9MfJOSyqjpaQCgRoUuDtMGqGidyoLwM65TS+j+Q3wrwWAuQeE95uVt5C1HY8ru vaSNXSRS7yOhaGUx4Rb2yvDyU/Q1u7TYuvqAE81C/+/TGqpfd02N3DfdBTEDvwn76RfSfFI6LYTN HqGmu5ZimdzZTN3Exkk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block n/5RfExNmY5h6rIItRFeDQpjpiOANqHHnIWvMDBj9uQNPDnsruxyk/5f+ySWD90BFy5ctcrImCSM QeisTaLJxRA7hAgtE7lEUUK4yrxrpaiWBmwphEDR92QpYigMNCYgjLZUPA7z/CljnqmkcTdtmwT/ JCB0DBXxiDvoUC9NkETilIo6+WYcM0hDx1QDKaR/FkB4l0vx0O0zq2vd6aA9aUxY45Lion+2amxj 3HGOWnBaVcvTdxm+H5baMUjMWgtnU9umbCXYHzEY5zyTQzdSlfoDssWwuyLMnexhJ/ZhBR6Vf8Ly eQbiUuBSeXJSyN5Gk2q1IwHuUw3uFdj+G8j2Ww== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block YnhiysvyTci4sHtzqW54U2ODyWQA/Zc7iHdB/SakTtFquqBb6k/q3ta/SWV8DknaGxdL+JRcq7E+ /M2v9R9Xy6D5ce2y3mQbQtgmJRluN6OSHXvxqaGiHciPw6/2NDN5qEsfO0mvVpLX1vDL4bcSKAuv DkxybBhkHnXJez1j+yM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block kcFlikViD9VP3HhWC6L4szfOwqupofLtcwekCEuA/YL5tZNpUh9Xy6V9yMXNxZmjA48b/mopE3xq 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mit
a788d0bf43137adc29c47f9a91389f8b
0.955475
1.809357
false
false
false
false
niketancm/tsea26
lab2-3/rtl/min_max_ctrl.vhd
1
883
library ieee; use ieee.std_logic_1164.all; entity min_max_ctrl is port ( function_i : in std_logic_vector(2 downto 0); opa_sign_i : in std_logic; opb_sign_i : in std_logic; carry_i : in std_logic; mx_minmax_o : out std_logic); end min_max_ctrl; architecture min_max_ctrl_rtl of min_max_ctrl is begin -- min_max_ctrl_rtl min_max_logic:process(function_i,opa_sign_i,opb_sign_i,carry_i) begin --Max instruction, assuming that the data is unsigned data. L1: if(function_i = "110") then if(carry_i = '0') then --check for carry in mx_minmax_o <= '0'; else mx_minmax_o <= '1'; end if; --MIN instruction elsif(function_i = "111") then if(carry_i = '0') then --check for carry in mx_minmax_o <= '1'; else mx_minmax_o <= '0'; end if; end if L1; end process; end min_max_ctrl_rtl;
gpl-2.0
ed2297c54c6fb01da9dec96d5d7b84f2
0.603624
2.794304
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/styles/jcl/turbocodes/iteration_synth.fixed.vhd
1
10,177
---------------------------------------------------------------------- ---- ---- ---- iteration_synth.vhd ---- ---- ---- ---- This file is part of the turbo decoder IP core project ---- ---- http://www.opencores.org/projects/turbocodes/ ---- ---- ---- ---- Author(s): ---- ---- - David Brochart([email protected]) ---- ---- ---- ---- All additional information is available in the README.txt ---- ---- file. ---- ---- ---- ---------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2005 Authors ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------- architecture SYNTH of ITERATION is signal zout1 : ARRAY4c; signal zout2 : ARRAY4c; signal zout1perm : ARRAY4c; signal zoutint1 : ARRAY4c; signal zout2int : ARRAY4c; signal tmp0 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0); signal tmp1 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0); signal tmp2 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0); signal tmp3 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0); signal tmp4 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0); signal tmp5 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0); signal tmp6 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0); signal tmp7 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0); signal tmp8 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0); signal tmp9 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0); signal tmp10 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0); signal tmp11 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0); signal abdel1perm : ARRAY2a; signal abdel1permint : ARRAY2a; signal adel1 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal bdel1 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal ydel1 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal wdel1 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal yintdel1 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal wintdel1 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal adel2 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal bdel2 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal ydel2 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal wdel2 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal adecint : std_logic; signal bdecint : std_logic; signal adel3 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal bdel3 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal ydel3 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal wdel3 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal yintdel3 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal wintdel3 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal yintdel4 : std_logic_vector(SIG_WIDTH - 1 downto 0); signal wintdel4 : std_logic_vector(SIG_WIDTH - 1 downto 0); begin SOVA_I0 : SOVA port map ( CLK => clk, RST => rst, ANOISY => a, BNOISY => b, YNOISY => y, WNOISY => w, ZIN => zin, ZOUT => zout1, ACLEAN => aDec, BCLEAN => bDec ); ZPERMUT_I0 : ZPERMUT generic map ( FLIP => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2 ) port map ( FLIPFLOP => flipflop, Z => zout1, ZPERM => zout1perm ); tmp0 <= zout1perm(0) & zout1perm(1) & zout1perm(2) & zout1perm(3) & abdel1perm(0) & abdel1perm(1); INTERLEAVER_I0 : INTERLEAVER generic map ( DELAY => TREL1_LEN + TREL2_LEN + 2 + delay, WAY => 0 ) port map ( CLK => clk, RST => rst, D => tmp0, Q => tmp1 ); zoutint1(0) <= tmp1(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 3 + SIG_WIDTH * 2); zoutint1(1) <= tmp1(Z_WIDTH * 3 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 2 + SIG_WIDTH * 2); zoutint1(2) <= tmp1(Z_WIDTH * 2 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 1 + SIG_WIDTH * 2); zoutint1(3) <= tmp1(Z_WIDTH * 1 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 0 + SIG_WIDTH * 2); abdel1permint(0) <= tmp1(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1); abdel1permint(1) <= tmp1(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0); tmp2 <= a & b & y & w & yInt & wInt; DELAYER_I0 : DELAYER generic map ( DELAY => TREL1_LEN + TREL2_LEN ) port map ( CLK => clk, RST => rst, D => tmp2, Q => tmp3 ); adel1 <= tmp3(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5); bdel1 <= tmp3(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4); ydel1 <= tmp3(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3); wdel1 <= tmp3(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2); yintdel1 <= tmp3(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1); wintdel1 <= tmp3(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0); ABPERMUT_I0 : ABPERMUT generic map ( FLIP => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2 ) port map ( FLIPFLOP => flipflop, A => adel1, B => bdel1, ABPERM => abdel1perm ); tmp4 <= adel1 & bdel1 & ydel1 & wdel1; DELAYER_I1 : DELAYER generic map ( DELAY => FRSIZE ) port map ( CLK => clk, RST => rst, D => tmp4, Q => tmp5 ); adel2 <= tmp5(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3); bdel2 <= tmp5(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2); ydel2 <= tmp5(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1); wdel2 <= tmp5(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0); SOVA_I1 : SOVA port map ( CLK => clk, RST => rst, ANOISY => abdel1permint(1), BNOISY => abdel1permint(0), YNOISY => yintdel1, WNOISY => wintdel1, ZIN => zoutint1, ZOUT => zout2, ACLEAN => adecint, BCLEAN => bdecint ); tmp6 <= zout2(0) & zout2(1) & zout2(2) & zout2(3); DEINTERLEAVER_I0 : INTERLEAVER generic map ( DELAY => 2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay, WAY => 1 ) port map ( CLK => clk, RST => rst, D => tmp6, Q => tmp7 ); zout2int(0) <= tmp7(Z_WIDTH * 4 - 1 downto Z_WIDTH * 3); zout2int(1) <= tmp7(Z_WIDTH * 3 - 1 downto Z_WIDTH * 2); zout2int(2) <= tmp7(Z_WIDTH * 2 - 1 downto Z_WIDTH * 1); zout2int(3) <= tmp7(Z_WIDTH * 1 - 1 downto Z_WIDTH * 0); ZPERMUT_I1 : ZPERMUT generic map ( FLIP => (2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay) mod 2 ) port map ( FLIPFLOP => flipflop, Z => zout2int, ZPERM => zout ); tmp8 <= adel2 & bdel2 & ydel2 & wdel2 & yintdel1 & wintdel1; DELAYER_I2 : DELAYER generic map ( DELAY => TREL1_LEN + TREL2_LEN ) port map ( CLK => clk, RST => rst, D => tmp8, Q => tmp9 ); adel3 <= tmp9(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5); bdel3 <= tmp9(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4); ydel3 <= tmp9(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3); wdel3 <= tmp9(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2); yintdel3 <= tmp9(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1); wintdel3 <= tmp9(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0); tmp10 <= adel3 & bdel3 & ydel3 & wdel3 & yintdel3 & wintdel3 & yintdel4 & wintdel4; DELAYER_I3 : DELAYER generic map ( DELAY => FRSIZE ) port map ( CLK => clk, RST => rst, D => tmp10, Q => tmp11 ); aDel <= tmp11(SIG_WIDTH * 8 - 1 downto SIG_WIDTH * 7); bDel <= tmp11(SIG_WIDTH * 7 - 1 downto SIG_WIDTH * 6); yDel <= tmp11(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5); wDel <= tmp11(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4); yintdel4 <= tmp11(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3); wintdel4 <= tmp11(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2); yIntDel <= tmp11(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1); wIntDel <= tmp11(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0); end architecture SYNTH;
gpl-3.0
bd47d54cd16c4782c9a4add1f436c695
0.488749
3.43122
false
false
false
false
NicoLedwith/Dr.AluOpysel
RAT_MCU/RAT_Wrapper_vga_only_F14.vhd
1
8,109
------------------------------------------------------------------------------- -- Company: RAT Technologies -- Engineer: Various RAT rats -- -- Create Date: 1/31/2012 -- Design Name: -- Module Name: RAT_wrapper - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: Wrapper for RAT MCU. This model provides a template to -- interface the RAT MCU to the Nexys2 development board. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity RAT_wrapper is Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0); SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0); DISP_EN : out STD_LOGIC_VECTOR (3 downto 0); SWITCHES : in STD_LOGIC_VECTOR (7 downto 0); BUTTONS : in STD_LOGIC_VECTOR (3 downto 0); RESET : in STD_LOGIC; CLK : in STD_LOGIC; -- VGA support signals ----------------------------- VGA_RGB : out std_logic_vector(7 downto 0); VGA_HS : out std_logic; VGA_VS : out std_logic); end RAT_wrapper; architecture Behavioral of RAT_wrapper is ------------------------------------------------------------------------------- -- INPUT PORT IDS ------------------------------------------------------------- CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := X"20"; CONSTANT BUTTONS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"24"; CONSTANT VGA_READ_ID : STD_LOGIC_VECTOR(7 downto 0) := x"93"; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- OUTPUT PORT IDS ------------------------------------------------------------ CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40"; CONSTANT SEGMENTS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"82"; CONSTANT DISP_EN_ID : STD_LOGIC_VECTOR (7 downto 0) := X"83"; CONSTANT VGA_HADDR_ID : STD_LOGIC_VECTOR(7 downto 0) := x"90"; CONSTANT VGA_LADDR_ID : STD_LOGIC_VECTOR(7 downto 0) := x"91"; CONSTANT VGA_WRITE_ID : STD_LOGIC_VECTOR(7 downto 0) := x"92"; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Declare RAT_MCU ------------------------------------------------------------ component RAT_MCU Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0); OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0); PORT_ID : out STD_LOGIC_VECTOR (7 downto 0); IO_STRB : out STD_LOGIC; RESET : in STD_LOGIC; INT : in STD_LOGIC; CLK : in STD_LOGIC); end component RAT_MCU; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Declare VGA Driver --------------------------------------------------------- component vgaDriverBuffer is Port (CLK, we : in std_logic; wa : in std_logic_vector (10 downto 0); wd : in std_logic_vector (7 downto 0); Rout : out std_logic_vector(2 downto 0); Gout : out std_logic_vector(2 downto 0); Bout : out std_logic_vector(1 downto 0); HS : out std_logic; VS : out std_logic; pixelData : out std_logic_vector(7 downto 0)); end component; -- Signals for connecting RAT_MCU to RAT_wrapper ------------------------------- signal s_input_port : std_logic_vector (7 downto 0); signal s_output_port : std_logic_vector (7 downto 0); signal s_port_id : std_logic_vector (7 downto 0); signal s_load : std_logic; --signal s_interrupt : std_logic; -- not yet used -- VGA signals signal s_vga_we : std_logic; -- Write enable signal r_vga_wa : std_logic_vector(10 downto 0); -- Address to read from/write to signal r_vga_wd : std_logic_vector(7 downto 0); -- Pixel data to write to framebuffer signal r_vgaData : std_logic_vector(7 downto 0); -- Pixel data read from framebuffer -- Register definitions for output devices ------------------------------------ signal r_LEDS : std_logic_vector (7 downto 0) := (others => '0'); signal r_SEGMENTS : std_logic_vector (7 downto 0) := (others => '0'); signal r_DISP_EN : std_logic_vector (3 downto 0) := (others => '0'); ------------------------------------------------------------------------------- begin -- Instantiate RAT_MCU -------------------------------------------------------- MCU: RAT_MCU port map( IN_PORT => s_input_port, OUT_PORT => s_output_port, PORT_ID => s_port_id, RESET => RESET, IO_STRB => s_load, INT => BUTTONS(3), CLK => CLK); ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Instantiate the VGA Driver VGA: vgaDriverBuffer port map(CLK => CLK, WE => s_vga_we, WA => r_vga_wa, WD => r_vga_wd, Rout => VGA_RGB(7 downto 5), Gout => VGA_RGB(4 downto 2), Bout => VGA_RGB(1 downto 0), HS => VGA_HS, VS => VGA_VS, pixelData => r_vgaData); ------------------------------------------------------------------------------- -- MUX for selecting what input to read ------------------------------------------------------------------------------- inputs: process(s_port_id, SWITCHES, BUTTONS) begin if (s_port_id = SWITCHES_ID) then s_input_port <= SWITCHES; elsif (s_port_id = VGA_READ_ID) then s_input_port <= r_vgaData; else s_input_port <= x"00"; end if; end process inputs; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Decoder for updating output registers -- Register updates depend on rising clock edge and asserted load signal ------------------------------------------------------------------------------- outputs: process(CLK, s_load, s_port_id) begin if (rising_edge(CLK)) then if (s_load = '1') then if (s_port_id = LEDS_ID) then r_LEDS <= s_output_port; elsif (s_port_id = SEGMENTS_ID) then r_SEGMENTS <= s_output_port; elsif (s_port_id = DISP_EN_ID) then r_DISP_EN <= s_output_port(3 downto 0); elsif (s_port_id = VGA_HADDR_ID) then r_vga_wa(10 downto 8) <= s_output_port(2 downto 0); elsif (s_port_id = VGA_LADDR_ID) then r_vga_wa(7 downto 0) <= s_output_port; elsif (s_port_id = VGA_WRITE_ID) then r_vga_wd <= s_output_port; if(s_port_id = VGA_WRITE_ID) then s_vga_we <= '1'; else s_vga_we <= '0'; end if; end if; end if; end if; end process outputs; ------------------------------------------------------------------------------- -- Register Interface Assignments --------------------------------------------- LEDS <= r_LEDS; SEGMENTS <= r_SEGMENTS; DISP_EN <= r_DISP_EN; ------------------------------------------------------------------------------- -- VGA_RGB <= "11111111"; -- s_vga_we <= '1'; -- r_vga_wa <= "00000000000"; -- r_vga_wd <= "00000011"; -- VGA_HS <= '1'; -- VGA_VS <= '1'; end Behavioral;
mit
4e6e43eb745dcff071fa668e045ebe62
0.410038
4.423895
false
false
false
false
rjarzmik/mips_processor
Caches/SinglePort_Cache_tb.vhd
1
5,561
------------------------------------------------------------------------------- -- Title : Testbench for design "SinglePort_Cache" -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : SinglePort_Cache_tb.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-19 -- Last update: 2016-11-26 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-19 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity SinglePort_Cache_tb is end entity SinglePort_Cache_tb; architecture passthrough of SinglePort_Cache_tb is -- component generics constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; constant MEMORY_LATENCY : integer := 1; -- component ports signal clk : std_logic := '1'; signal rst : std_logic := '1'; signal i_porta_req : std_logic; signal i_porta_we : std_logic; signal i_porta_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal i_porta_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_porta_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_porta_valid : std_logic; signal o_memory_req : std_logic; signal o_memory_we : std_logic; signal o_memory_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal o_memory_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_memory_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_memory_valid : std_logic; -- L2 connections signal o_L2c_req : std_logic; signal o_L2c_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal i_L2c_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_L2c_valid : std_logic; begin -- architecture passthrough_and_simulated_memory -- component instantiation DUT : entity work.SinglePort_Cache generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH) port map ( clk => clk, rst => rst, i_porta_req => i_porta_req, i_porta_we => i_porta_we, i_porta_addr => i_porta_addr, i_porta_write_data => i_porta_write_data, o_porta_read_data => o_porta_read_data, o_porta_valid => o_porta_valid, o_memory_req => o_memory_req, o_memory_we => o_memory_we, o_memory_addr => o_memory_addr, o_memory_write_data => o_memory_write_data, i_memory_read_data => i_memory_read_data, i_memory_valid => i_memory_valid); -- reset rst <= '0' after 12 ps; -- clock generation clk <= not clk after 5 ps; -- waveform generation WaveGen_Proc : process variable nb_clk : natural := 0; begin -- insert signal assignments here wait until clk = '1'; nb_clk := nb_clk + 1; if nb_clk <= 24 then if nb_clk mod (MEMORY_LATENCY + 2) = 0 then i_porta_we <= '0'; i_porta_addr <= std_logic_vector(to_unsigned(4 * nb_clk / (MEMORY_LATENCY + 2), ADDR_WIDTH)); i_porta_req <= '1'; else i_porta_we <= '0'; i_porta_addr <= (others => 'X'); i_porta_req <= '0'; end if; end if; if nb_clk > 24 and nb_clk <= 27 then i_porta_we <= '0'; i_porta_addr <= std_logic_vector(to_unsigned(24, ADDR_WIDTH)); i_porta_req <= '1'; end if; if nb_clk = 28 then i_porta_req <= '0'; i_porta_addr <= (others => 'X'); end if; if nb_clk > 32 and nb_clk <= 42 then i_porta_we <= '0'; if nb_clk = 33 or nb_clk = (33 + MEMORY_LATENCY + 3) then i_porta_req <= '1'; i_porta_addr <= std_logic_vector(to_unsigned(8, ADDR_WIDTH)); else i_porta_req <= '0'; i_porta_addr <= (others => 'X'); end if; end if; if nb_clk > 42 then i_porta_req <= '0'; i_porta_addr <= (others => 'X'); end if; end process WaveGen_Proc; -- memory simulator Simulated_Memory_1 : entity work.Simulated_Memory generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, MEMORY_LATENCY => MEMORY_LATENCY) port map ( clk => clk, rst => Rst, i_memory_req => o_memory_req, i_memory_we => '0', i_memory_addr => o_memory_addr, i_memory_write_data => (others => 'X'), o_memory_read_data => i_memory_read_data, o_memory_valid => i_memory_valid); end architecture passthrough; ------------------------------------------------------------------------------- configuration SinglePort_Cache_tb_passthrough_cfg of SinglePort_Cache_tb is for passthrough end for; end SinglePort_Cache_tb_passthrough_cfg; -------------------------------------------------------------------------------
gpl-3.0
ee97ae74177744feed9749c346dc4950
0.496314
3.682781
false
false
false
false
eurobotics/aversive4dspic
modules/devices/encoders/encoders_eirbot/xilinx_vhdl/test1.vhd
1
2,583
-- xilinx carte_prop LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; --USE IEEE.STD_LOGIC_ARITH.ALL; --USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY carte1 IS PORT ( CLK : IN std_logic; sortie : OUT unsigned(7 DOWNTO 0); SEL : IN unsigned(1 DOWNTO 0); TX_bus : OUT std_logic; RX_bus : IN std_logic; TX_avr : IN std_logic; RX_avr : OUT std_logic; AB0 : IN unsigned(1 DOWNTO 0); AB1 : IN unsigned(1 DOWNTO 0); -- MASSE : std_logic ); -- carte 1 ATTRIBUTE pin_assign : string; ATTRIBUTE pin_assign OF CLK : SIGNAL IS "7"; --clock ATTRIBUTE pin_assign OF sortie : SIGNAL IS "11 12 9 8 6 5 4 3 "; --data 0 -- a 7 ATTRIBUTE pin_assign OF AB0 : SIGNAL IS "27 26"; --cod_d0 ATTRIBUTE pin_assign OF AB1 : SIGNAL IS "25 29"; --cod_g0 ATTRIBUTE pin_assign OF RX_bus : SIGNAL IS "19"; --rx_bus ATTRIBUTE pin_assign OF TX_bus : SIGNAL IS "22"; --tx_bus ATTRIBUTE pin_assign OF RX_avr : SIGNAL IS "14"; --rx_avr ATTRIBUTE pin_assign OF TX_avr : SIGNAL IS "13"; --tx_avr ATTRIBUTE pin_assign OF SEL : SIGNAL IS "1 44"; -- il reste data2 qui est inutilise -- ATTRIBUTE pin_assign OF MASSE : SIGNAL IS " 43"; END carte1; ARCHITECTURE Behavioral OF carte1 IS -- 1 traitement de codeur COMPONENT compteur GENERIC (Nb_bascules : natural); PORT ( AB : IN unsigned(1 DOWNTO 0); cpt : OUT unsigned(7 DOWNTO 0); clk : IN std_ulogic; INV : IN std_ulogic ); END COMPONENT; SIGNAL sortie0 : unsigned(7 DOWNTO 0); SIGNAL sortie1 : unsigned(7 DOWNTO 0); for cod0 : compteur use entity work.compteur(Behavioral); for cod1 : compteur BEGIN -- compteur 0 cod0 : compteur GENERIC MAP (Nb_bascules => 1) PORT MAP ( AB => AB0, cpt => sortie0, clk => CLK , INV => '0' ); -- compteur 1 cod1 : compteur GENERIC MAP (Nb_bascules => 1) PORT MAP ( AB => AB1, cpt => sortie1, clk => CLK, INV => '1' ); MUX: PROCESS (SEL, sortie0, sortie1, sortie2, sortie3) BEGIN -- PROCESS MUX CASE SEL IS WHEN "00" => sortie <= sortie0; WHEN "01" => sortie <= sortie1; WHEN OTHERS => sortie <= (OTHERS => 'Z'); END CASE; END PROCESS MUX; UART : PROCESS (TX_avr,RX_bus) BEGIN -- PROCESS UART TX_bus <= TX_avr; RX_avr <= RX_bus; END PROCESS UART; END Behavioral;
gpl-3.0
10d1f3c0c8e0c63722410b49ef0cf1ff
0.562911
3.389764
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/logic_builtin.vhd
2
30,579
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PrcUm/lZr3CcimYfdPVY5boEakykwMBdn+a0r4l5thupmK3ENAHXOMnIWC2qdjii0xo+QafFPib8 /0hI4pAgeg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cceCNxx9A19VIKekLdBOhxfwIcLYMC3QxsbvTzUwHT5Y5RHcRUc5YB0zZbRVXo00oHar3+MiDV13 a5m8B95Jr8Eh6AldRK77BIeae3xkZKBe55s9pg60ENKDMqqHqXaM8xkHMubZcES9MVZQvhT2idV8 7su+sGp3KwSrUKoN/g8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XEvkzi6XEe9xbybGIq9FE+BWaH9gHMWC/lnTYDdCWZjLxdaqWvuK1Bmqg00BXi3az3GHNhQt9hne uq3P0SLBN1FSx0Bt4V1rgNYkIHgWO23FtpFusDYotcc6s7rR6ouVJC5qkyDfKTowFQbSIyKzjkcL /3ojSZt8sIxeArPN/wNm7l/AqkaeJYIuoegeVUUICwmL63/Ym9j3g41Qnmb7TpvazU0UpTe5kiK+ o6qxBZ6+3JzGZSWk5LZqZh0si5Xr+nlhTU/cbppuntip2yGCGlTLfbibH77YIQxw8XBVgbnqDCOl 4DqIQt/0rOq/ut+bXHjIgYTp4+fqEWk7dPriAg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block POPZY5l9JMHB9WK1pevP5/w+VO2I94gm60wfkJ7sMf+7LbzMugCPD+Bflcbw2YnrTzWsDla5a9Nj drzEj7EKVSkSU23oja7ypwhIMC+H1onGiWgWQKXPrV7eX6/WcXTcAyRUCexoW2ZDuB8IqahZdTkn rs9QF4Rw2y03ceka6qo= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LIvBuZ0kKMQaeXVTP8xA+UmuRwvyo+P8JdsOV3SUeNj4vZcTwkN7D+MKrGsZm407deEBvDtU+wn+ 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bsd-2-clause
d9b9398d6f1c94e0bcfca550b5ccd82f
0.946041
1.835474
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/parity.vhd
1
11,625
------------------------------------------------------------------------------- -- parity.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------ -- Filename: parity.vhd -- -- Description: Generate parity optimally for all target architectures. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity Parity is generic ( C_USE_LUT6 : boolean := true; C_SIZE : integer := 6 ); port ( InA : in std_logic_vector(0 to C_SIZE - 1); Res : out std_logic ); end entity Parity; library unisim; use unisim.vcomponents.all; architecture IMP of Parity is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; -- Non-recursive loop implementation function ParityGen (InA : std_logic_vector) return std_logic is variable result : std_logic; begin result := '0'; for I in InA'range loop result := result xor InA(I); end loop; return result; end function ParityGen; begin -- architecture IMP Using_LUT6 : if (C_USE_LUT6) generate -------------------------------------------------------------------------------------------------- -- Single LUT6 -------------------------------------------------------------------------------------------------- Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate signal inA6 : std_logic_vector(0 to 5); begin Assign_InA : process (InA) is begin inA6 <= (others => '0'); inA6(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => Res, I0 => inA6(5), I1 => inA6(4), I2 => inA6(3), I3 => inA6(2), I4 => inA6(1), I5 => inA6(0)); end generate Single_LUT6; -------------------------------------------------------------------------------------------------- -- Two LUT6 and one MUXF7 -------------------------------------------------------------------------------------------------- Use_MUXF7 : if C_SIZE = 7 generate signal inA7 : std_logic_vector(0 to 6); signal result6 : std_logic; signal result6n : std_logic; begin Assign_InA : process (InA) is begin inA7 <= (others => '0'); inA7(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT : LUT6 generic map( INIT => X"6996966996696996") port map( O => result6, I0 => inA7(5), I1 => inA7(4), I2 => inA7(3), I3 => inA7(2), I4 => inA7(1), I5 => inA7(0)); XOR6_LUT_N : LUT6 generic map( INIT => X"9669699669969669") port map( O => result6n, I0 => inA7(5), I1 => inA7(4), I2 => inA7(3), I3 => inA7(2), I4 => inA7(1), I5 => inA7(0)); MUXF7_LUT : MUXF7 port map ( O => Res, I0 => result6, I1 => result6n, S => inA7(6)); end generate Use_MUXF7; -------------------------------------------------------------------------------------------------- -- Four LUT6, two MUXF7 and one MUXF8 -------------------------------------------------------------------------------------------------- Use_MUXF8 : if C_SIZE = 8 generate signal inA8 : std_logic_vector(0 to 7); signal result6_1 : std_logic; signal result6_1n : std_logic; signal result6_2 : std_logic; signal result6_2n : std_logic; signal result7_1 : std_logic; signal result7_1n : std_logic; begin Assign_InA : process (InA) is begin inA8 <= (others => '0'); inA8(0 to InA'length - 1) <= InA; end process Assign_InA; XOR6_LUT1 : LUT6 generic map( INIT => X"6996966996696996") port map( O => result6_1, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); XOR6_LUT2_N : LUT6 generic map( INIT => X"9669699669969669") port map( O => result6_1n, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); MUXF7_LUT1 : MUXF7 port map ( O => result7_1, I0 => result6_1, I1 => result6_1n, S => inA8(6)); XOR6_LUT3 : LUT6 generic map( INIT => X"6996966996696996") port map( O => result6_2, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); XOR6_LUT4_N : LUT6 generic map( INIT => X"9669699669969669") port map( O => result6_2n, I0 => inA8(5), I1 => inA8(4), I2 => inA8(3), I3 => inA8(2), I4 => inA8(1), I5 => inA8(0)); MUXF7_LUT2 : MUXF7 port map ( O => result7_1n, I0 => result6_2n, I1 => result6_2, S => inA8(6)); MUXF8_LUT : MUXF8 port map ( O => res, I0 => result7_1, I1 => result7_1n, S => inA8(7)); end generate Use_MUXF8; end generate Using_LUT6; -- Fall-back implementation without LUT6 Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate begin Res <= ParityGen(InA); end generate Not_Using_LUT6; end architecture IMP;
bsd-2-clause
eb63ad92d57a919106a68048f7c202d9
0.43957
4.267621
false
false
false
false
rjarzmik/mips_processor
Caches/DualPort_Cache.vhd
1
5,353
------------------------------------------------------------------------------- -- Title : Dual port cache -- Project : ------------------------------------------------------------------------------- -- File : DualPort_Cache.vhd -- Author : Robert Jarzmik (Intel) <[email protected]> -- Company : -- Created : 2016-11-15 -- Last update: 2016-11-18 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Cache with 2 input ports and one port towards memory/next cache ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-15 1.0 rjarzmik Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; ------------------------------------------------------------------------------- entity DualPort_Cache is generic ( ADDR_WIDTH : integer := 32; DATA_WIDTH : integer := 32 ); port ( clk : in std_logic; rst : in std_logic; i_porta_req : in std_logic; i_porta_we : in std_logic; i_porta_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); i_porta_write_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); o_porta_read_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); o_porta_valid : out std_logic; i_portb_req : in std_logic; i_portb_we : in std_logic; i_portb_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); i_portb_write_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); o_portb_read_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); o_portb_valid : out std_logic; o_memory_req : out std_logic; o_memory_we : out std_logic; o_memory_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0); o_memory_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); i_memory_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); i_memory_valid : in std_logic ); end entity DualPort_Cache; ------------------------------------------------------------------------------- architecture passthrough of DualPort_Cache is ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- -- access handling signal cache_valid : boolean; signal cache_acquiring_porta : boolean; signal cache_acquiring_portb : boolean; signal cache_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal cache_data : std_logic_vector(DATA_WIDTH - 1 downto 0); begin -- architecture rtl ----------------------------------------------------------------------------- -- Component instantiations ----------------------------------------------------------------------------- process(rst, clk) is begin if rst = '1' then o_porta_valid <= '0'; o_portb_valid <= '0'; o_memory_we <= '0'; cache_valid <= false; cache_acquiring_porta <= false; cache_acquiring_portb <= false; elsif rising_edge(clk) then if cache_valid and cache_acquiring_porta then o_porta_read_data <= cache_data; o_porta_valid <= '1'; cache_addr <= (others => 'X'); cache_acquiring_porta <= false; else o_porta_valid <= '0'; o_porta_read_data <= (others => 'X'); end if; if cache_valid and cache_acquiring_portb then o_portb_read_data <= cache_data; o_portb_valid <= '1'; cache_addr <= (others => 'X'); cache_acquiring_portb <= false; else o_portb_valid <= '0'; o_portb_read_data <= (others => 'X'); end if; if not (cache_acquiring_porta or cache_acquiring_portb) and (not cache_valid or (cache_addr /= i_porta_addr and cache_addr /= i_portb_addr)) then if i_porta_req = '1' then cache_valid <= false; cache_data <= (others => 'X'); o_memory_addr <= i_porta_addr; o_memory_write_data <= i_porta_write_data; cache_addr <= i_porta_addr; o_memory_we <= i_porta_we; cache_acquiring_porta <= true; elsif i_portb_req = '1' then cache_valid <= false; cache_data <= (others => 'X'); o_memory_addr <= i_portb_addr; o_memory_write_data <= i_portb_write_data; cache_addr <= i_portb_addr; o_memory_we <= i_portb_we; cache_acquiring_portb <= true; end if; end if; if i_memory_valid = '1' then cache_data <= i_memory_read_data; cache_valid <= true; end if; end if; end process; o_memory_req <= '1' when cache_acquiring_porta or cache_acquiring_portb else '0'; end architecture passthrough;
gpl-3.0
82b95ea4b9f9736bd3adb92918ee01b8
0.456006
4.052233
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_sm.vhd
1
47,879
-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_sm.vhd -- Description: This entity manages fetching of descriptors. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.clog2; ------------------------------------------------------------------------------- entity axi_sg_ftch_sm is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1 -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- updt_error : in std_logic ; -- -- -- Channel 1 Control and Status -- ch1_run_stop : in std_logic ; -- ch1_desc_flush : in std_logic ; -- ch1_updt_done : in std_logic ; -- ch1_sg_idle : in std_logic ; -- ch1_tailpntr_enabled : in std_logic ; -- ch1_ftch_queue_full : in std_logic ; -- ch1_ftch_queue_empty : in std_logic ; -- ch1_ftch_pause : in std_logic ; -- ch1_fetch_address : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_ftch_active : out std_logic ; -- ch1_ftch_idle : out std_logic ; -- ch1_ftch_interr_set : out std_logic ; -- ch1_ftch_slverr_set : out std_logic ; -- ch1_ftch_decerr_set : out std_logic ; -- ch1_ftch_err_early : out std_logic ; -- ch1_ftch_stale_desc : out std_logic ; -- -- -- Channel 2 Control and Status -- ch2_run_stop : in std_logic ; -- ch2_desc_flush : in std_logic ; -- ch2_updt_done : in std_logic ; -- ch2_sg_idle : in std_logic ; -- ch2_tailpntr_enabled : in std_logic ; -- ch2_ftch_queue_full : in std_logic ; -- ch2_ftch_queue_empty : in std_logic ; -- ch2_ftch_pause : in std_logic ; -- ch2_fetch_address : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_ftch_active : out std_logic ; -- ch2_ftch_idle : out std_logic ; -- ch2_ftch_interr_set : out std_logic ; -- ch2_ftch_slverr_set : out std_logic ; -- ch2_ftch_decerr_set : out std_logic ; -- ch2_ftch_err_early : out std_logic ; -- ch2_ftch_stale_desc : out std_logic ; -- -- -- DataMover Command -- ftch_cmnd_wr : out std_logic ; -- ftch_cmnd_data : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- DataMover Status -- ftch_done : in std_logic ; -- ftch_error : in std_logic ; -- ftch_interr : in std_logic ; -- ftch_slverr : in std_logic ; -- ftch_decerr : in std_logic ; -- ftch_stale_desc : in std_logic ; -- ftch_error_early : in std_logic ; -- ftch_error_addr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) -- ); end axi_sg_ftch_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Command Type constant FETCH_CMD_TYPE : std_logic := '1'; -- DataMover Cmnd Reserved Bits constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0'); -- DataMover Cmnd Bytes to Xfer for Channel 1 constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0) := std_logic_vector(to_unsigned( (C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH)); -- DataMover Cmnd Bytes to Xfer for Channel 2 constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0) := std_logic_vector(to_unsigned( (C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH)); -- DataMover Cmnd Reserved Bits constant FETCH_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH) := (others => '0'); -- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate -- Required width in bits for C_SG_FTCH_DESC2QUEUE --constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- ---- Vector version of C_SG_FTCH_DESC2QUEUE --constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG signal fetch_tag : std_logic_vector(3 downto 0) := (others => '0'); type SG_FTCH_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, FETCH_STATUS, FETCH_ERROR ); signal ftch_cs : SG_FTCH_STATE_TYPE; signal ftch_ns : SG_FTCH_STATE_TYPE; -- State Machine Signals signal ch1_active_set : std_logic := '0'; signal ch2_active_set : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal ch1_ftch_sm_idle : std_logic := '0'; signal ch2_ftch_sm_idle : std_logic := '0'; signal ch1_pause_fetch : std_logic := '0'; signal ch2_pause_fetch : std_logic := '0'; signal ch2_pause_fetch1 : std_logic := '0'; signal ch2_pause_fetch2 : std_logic := '0'; signal ch2_pause_fetch3 : std_logic := '0'; signal ch2_updt_done1 : std_logic := '0'; signal ch2_updt_done2 : std_logic := '0'; -- Misc Signals signal fetch_cmd_addr : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ch1_active_i : std_logic := '0'; signal service_ch1 : std_logic := '0'; signal ch2_active_i : std_logic := '0'; signal service_ch2 : std_logic := '0'; attribute mark_debug of ch1_active_i : signal is "true"; attribute mark_debug of ch2_active_i : signal is "true"; signal fetch_cmd_btt : std_logic_vector (SG_BTT_WIDTH-1 downto 0) := (others => '0'); signal ch1_stale_descriptor : std_logic := '0'; signal ch2_stale_descriptor : std_logic := '0'; attribute mark_debug of ch1_stale_descriptor : signal is "true"; attribute mark_debug of ch2_stale_descriptor : signal is "true"; signal ch1_ftch_interr_set_i : std_logic := '0'; signal ch2_ftch_interr_set_i : std_logic := '0'; -- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate -- counts for keeping track of queue descriptors to prevent -- fifo fill --signal ch1_desc_ftched_count : std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); --signal ch2_desc_ftched_count : std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ch1_ftch_active <= ch1_active_i; ch2_ftch_active <= ch2_active_i; ------------------------------------------------------------------------------- -- Scatter Gather Fetch State Machine ------------------------------------------------------------------------------- SG_FTCH_MACHINE : process(ftch_cs, ch1_active_i, ch2_active_i, service_ch1, service_ch2, ftch_error, ftch_done) begin -- Default signal assignment ch1_active_set <= '0'; ch2_active_set <= '0'; write_cmnd_cmb <= '0'; ch1_ftch_sm_idle <= '0'; ch2_ftch_sm_idle <= '0'; ftch_ns <= ftch_cs; case ftch_cs is ------------------------------------------------------------------- when IDLE => ch1_ftch_sm_idle <= not service_ch1; ch2_ftch_sm_idle <= not service_ch2; -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; -- If channel 1 is running and not idle and queue is not full -- then fetch descriptor for channel 1 elsif(service_ch1 = '1')then ch1_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- If channel 2 is running and not idle and queue is not full -- then fetch descriptor for channel 2 elsif(service_ch2 = '1')then ch2_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; else ftch_ns <= IDLE; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; else ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1; ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2; write_cmnd_cmb <= '1'; ftch_ns <= FETCH_STATUS; end if; ------------------------------------------------------------------- when FETCH_STATUS => ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1; ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2; -- sg error during fetch - shut down if(ftch_error = '1')then ftch_ns <= FETCH_ERROR; elsif(ftch_done = '1')then -- If just finished fethcing for channel 2 then... if(ch2_active_i = '1')then -- If ready, fetch descriptor for channel 1 if(service_ch1 = '1')then ch1_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Else if channel 2 still ready then fetch -- another descriptor for channel 2 elsif(service_ch2 = '1')then ch1_ftch_sm_idle <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Otherwise return to IDLE else ftch_ns <= IDLE; end if; -- If just finished fethcing for channel 1 then... elsif(ch1_active_i = '1')then -- If ready, fetch descriptor for channel 2 if(service_ch2 = '1')then ch2_active_set <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Else if channel 1 still ready then fetch -- another descriptor for channel 1 elsif(service_ch1 = '1')then ch2_ftch_sm_idle <= '1'; ftch_ns <= FETCH_DESCRIPTOR; -- Otherwise return to IDLE else ftch_ns <= IDLE; end if; else ftch_ns <= IDLE; end if; else ftch_ns <= FETCH_STATUS; end if; ------------------------------------------------------------------- when FETCH_ERROR => ch1_ftch_sm_idle <= '1'; ch2_ftch_sm_idle <= '1'; ftch_ns <= FETCH_ERROR; ------------------------------------------------------------------- -- coverage off when others => ftch_ns <= IDLE; -- coverage on end case; end process SG_FTCH_MACHINE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ftch_cs <= IDLE; else ftch_cs <= ftch_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Channel included therefore generate fetch logic ------------------------------------------------------------------------------- GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate begin ------------------------------------------------------------------------------- -- Active channel flag. Indicates which channel is active. -- 0 = channel active -- 1 = channel active ------------------------------------------------------------------------------- CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then ch1_active_i <= '0'; elsif(ch1_active_set = '1')then ch1_active_i <= '1'; end if; end if; end process CH1_ACTIVE_PROCESS; ------------------------------------------------------------------------------- -- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE -- This is 1 part of determining IDLE for a channel ------------------------------------------------------------------------------- CH1_IDLE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_idle <= '1'; -- SG Error therefore force IDLE -- CR564855 - fetch idle asserted too soon when update error occured. -- fetch idle does not need to be concerned with updt_error. This is -- because on going fetch is guarentteed to complete regardless of dma -- controller or sg update engine. --elsif(updt_error = '1' or ftch_error = '1' elsif(ftch_error = '1' or ch1_ftch_interr_set_i = '1')then ch1_ftch_idle <= '1'; -- When SG Fetch no longer idle then clear fetch idle elsif(ch1_sg_idle = '0')then ch1_ftch_idle <= '0'; -- If tail = cur and fetch queue is empty then elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then ch1_ftch_idle <= '1'; end if; end if; end process CH1_IDLE_PROCESS; ------------------------------------------------------------------------------- -- For No Fetch Queue, generate pause logic to prevent partial descriptor from -- being fetched and then endless throttle on AXI read bus ------------------------------------------------------------------------------- GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin REG_PAUSE_FETCH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- On descriptor update done clear pause if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then ch1_pause_fetch <= '0'; -- If channel active and command written then pause elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then ch1_pause_fetch <= '1'; end if; end if; end process REG_PAUSE_FETCH; end generate GEN_CH1_FETCH_PAUSE; -- Fetch queues so do not need to pause GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate -- -- CR585958 -- -- Required width in bits for C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- -- Vector version of C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); -- signal desc_queued_incr : std_logic := '0'; -- signal desc_queued_decr : std_logic := '0'; -- -- -- CR585958 -- signal ch1_desc_ftched_count: std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); -- begin -- -- desc_queued_incr <= '1' when ch1_active_i = '1' -- and write_cmnd_cmb = '1' -- and ch1_ftch_descpulled = '0' -- else '0'; -- -- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1' -- and not (ch1_active_i = '1' and write_cmnd_cmb = '1') -- else '0'; -- -- -- Keep track of descriptors queued version descriptors updated -- DESC_FETCHED_CNTR : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch1_desc_ftched_count <= (others => '0'); -- elsif(desc_queued_incr = '1')then -- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1); -- elsif(desc_queued_decr = '1')then -- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1); -- end if; -- end if; -- end process DESC_FETCHED_CNTR; -- -- REG_PAUSE_FETCH : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch1_pause_fetch <= '0'; -- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then -- ch1_pause_fetch <= '1'; -- else -- ch1_pause_fetch <= '0'; -- end if; -- end if; -- end process REG_PAUSE_FETCH; -- -- -- ch1_pause_fetch <= ch1_ftch_pause; end generate GEN_CH1_NO_FETCH_PAUSE; ------------------------------------------------------------------------------- -- Channel 1 ready to be serviced? ------------------------------------------------------------------------------- service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running and ch1_sg_idle = '0' -- SG Engine running and ch1_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch1_stale_descriptor = '0' -- No Stale Descriptors and ch1_desc_flush = '0' -- Not flushing desc and ch1_pause_fetch = '0' -- Not pausing else '0'; ------------------------------------------------------------------------------- -- Log Fetch Errors ------------------------------------------------------------------------------- INT_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_interr_set_i <= '0'; -- Channel active and datamover int error or fetch done and descriptor stale elsif((ch1_active_i = '1' and ftch_interr = '1') or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then ch1_ftch_interr_set_i <= '1'; end if; end if; end process INT_ERROR_PROCESS; ch1_ftch_interr_set <= ch1_ftch_interr_set_i; SLV_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_slverr_set <= '0'; elsif(ch1_active_i = '1' and ftch_slverr = '1')then ch1_ftch_slverr_set <= '1'; end if; end if; end process SLV_ERROR_PROCESS; DEC_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch1_ftch_decerr_set <= '0'; elsif(ch1_active_i = '1' and ftch_decerr = '1')then ch1_ftch_decerr_set <= '1'; end if; end if; end process DEC_ERROR_PROCESS; -- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor -- from being used by dma controller ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1' else '0'; -- Enable stale descriptor check GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate begin ----------------------------------------------------------------------- -- Stale Descriptor Error ----------------------------------------------------------------------- CH1_STALE_DESC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset then clear flag if(m_axi_sg_aresetn = '0')then ch1_stale_descriptor <= '0'; elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then ch1_stale_descriptor <= '1'; end if; end if; end process CH1_STALE_DESC; end generate GEN_CH1_STALE_CHECK; -- Disable stale descriptor check GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate begin ch1_stale_descriptor <= '0'; end generate GEN_CH1_NO_STALE_CHECK; -- Early detection of Stale Descriptor (valid only in tailpntr mode) used -- to prevent error'ed descriptor from being used. ch1_ftch_stale_desc <= ch1_stale_descriptor; end generate GEN_CH1_FETCH; ------------------------------------------------------------------------------- -- Channel excluded therefore do not generate fetch logic ------------------------------------------------------------------------------- GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate begin service_ch1 <= '0'; ch1_active_i <= '0'; ch1_ftch_idle <= '0'; ch1_ftch_interr_set <= '0'; ch1_ftch_slverr_set <= '0'; ch1_ftch_decerr_set <= '0'; ch1_ftch_err_early <= '0'; ch1_ftch_stale_desc <= '0'; end generate GEN_NO_CH1_FETCH; ------------------------------------------------------------------------------- -- Channel included therefore generate fetch logic ------------------------------------------------------------------------------- GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate begin ------------------------------------------------------------------------------- -- Active channel flag. Indicates which channel is active. -- 0 = channel active -- 1 = channel active ------------------------------------------------------------------------------- CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then ch2_active_i <= '0'; elsif(ch2_active_set = '1')then ch2_active_i <= '1'; end if; end if; end process CH2_ACTIVE_PROCESS; ------------------------------------------------------------------------------- -- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE -- This is 1 part of determining IDLE for a channel ------------------------------------------------------------------------------- CH2_IDLE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_idle <= '1'; -- SG Error therefore force IDLE -- CR564855 - fetch idle asserted too soon when update error occured. -- fetch idle does not need to be concerned with updt_error. This is -- because on going fetch is guarentteed to complete regardless of dma -- controller or sg update engine. -- elsif(updt_error = '1' or ftch_error = '1' elsif(ftch_error = '1' or ch2_ftch_interr_set_i = '1')then ch2_ftch_idle <= '1'; -- When SG Fetch no longer idle then clear fetch idle elsif(ch2_sg_idle = '0')then ch2_ftch_idle <= '0'; -- If tail = cur and fetch queue is empty then elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then ch2_ftch_idle <= '1'; end if; end if; end process CH2_IDLE_PROCESS; ------------------------------------------------------------------------------- -- For No Fetch Queue, generate pause logic to prevent partial descriptor from -- being fetched and then endless throttle on AXI read bus ------------------------------------------------------------------------------- GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate begin REG_PAUSE_FETCH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- On descriptor update done clear pause if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then ch2_pause_fetch <= '0'; -- If channel active and command written then pause elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then ch2_pause_fetch <= '1'; end if; ch2_pause_fetch1 <= ch2_pause_fetch; ch2_pause_fetch2 <= ch2_pause_fetch1; ch2_pause_fetch3 <= ch2_pause_fetch2; end if; end process REG_PAUSE_FETCH; end generate GEN_CH2_FETCH_PAUSE; -- Fetch queues so do not need to pause GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate -- -- CR585958 -- -- Required width in bits for C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1); -- -- Vector version of C_SG_FTCH_DESC2QUEUE -- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) -- := std_logic_vector(to_unsigned -- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH)); -- signal desc_queued_incr : std_logic := '0'; -- signal desc_queued_decr : std_logic := '0'; -- -- -- CR585958 -- signal ch2_desc_ftched_count: std_logic_vector -- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0'); -- -- begin -- -- desc_queued_incr <= '1' when ch2_active_i = '1' -- and write_cmnd_cmb = '1' -- and ch2_ftch_descpulled = '0' -- else '0'; -- -- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1' -- and not (ch2_active_i = '1' and write_cmnd_cmb = '1') -- else '0'; -- -- -- Keep track of descriptors queued version descriptors updated -- DESC_FETCHED_CNTR : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch2_desc_ftched_count <= (others => '0'); -- elsif(desc_queued_incr = '1')then -- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1); -- elsif(desc_queued_decr = '1')then -- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1); -- end if; -- end if; -- end process DESC_FETCHED_CNTR; -- -- REG_PAUSE_FETCH : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ch2_pause_fetch <= '0'; -- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then -- ch2_pause_fetch <= '1'; -- else -- ch2_pause_fetch <= '0'; -- end if; -- end if; -- end process REG_PAUSE_FETCH; -- ch2_pause_fetch <= ch2_ftch_pause; end generate GEN_CH2_NO_FETCH_PAUSE; ------------------------------------------------------------------------------- -- Channel 2 ready to be serviced? ------------------------------------------------------------------------------- MCDMA : if (C_ENABLE_MULTI_CHANNEL = 1) generate NOQUEUE : if (C_SG_FTCH_DESC2QUEUE = 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch3 = '0' -- No fetch pause else '0'; end generate NOQUEUE; QUEUE : if (C_SG_FTCH_DESC2QUEUE /= 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch = '0' -- No fetch pause else '0'; end generate QUEUE; end generate MCDMA; NO_MCDMA : if (C_ENABLE_MULTI_CHANNEL = 0) generate service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running and ch2_sg_idle = '0' -- SG Engine running and ch2_ftch_queue_full = '0' -- Queue not full and updt_error = '0' -- No SG Update error and ch2_stale_descriptor = '0' -- No Stale Descriptors and ch2_desc_flush = '0' -- Not flushing desc and ch2_pause_fetch = '0' -- No fetch pause else '0'; end generate NO_MCDMA; ------------------------------------------------------------------------------- -- Log Fetch Errors ------------------------------------------------------------------------------- INT_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_interr_set_i <= '0'; -- Channel active and datamover int error or fetch done and descriptor stale elsif((ch2_active_i = '1' and ftch_interr = '1') or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then ch2_ftch_interr_set_i <= '1'; end if; end if; end process INT_ERROR_PROCESS; ch2_ftch_interr_set <= ch2_ftch_interr_set_i; SLV_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_slverr_set <= '0'; elsif(ch2_active_i = '1' and ftch_slverr = '1')then ch2_ftch_slverr_set <= '1'; end if; end if; end process SLV_ERROR_PROCESS; DEC_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset or stopped then clear idle bit if(m_axi_sg_aresetn = '0')then ch2_ftch_decerr_set <= '0'; elsif(ch2_active_i = '1' and ftch_decerr = '1')then ch2_ftch_decerr_set <= '1'; end if; end if; end process DEC_ERROR_PROCESS; -- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor -- from being used by dma controller ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1' else '0'; -- Enable stale descriptor check GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate begin ----------------------------------------------------------------------- -- Stale Descriptor Error ----------------------------------------------------------------------- CH2_STALE_DESC : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- If reset then clear flag if(m_axi_sg_aresetn = '0')then ch2_stale_descriptor <= '0'; elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then ch2_stale_descriptor <= '1'; end if; end if; end process CH2_STALE_DESC; end generate GEN_CH2_STALE_CHECK; -- Disable stale descriptor check GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate begin ch2_stale_descriptor <= '0'; end generate GEN_CH2_NO_STALE_CHECK; -- Early detection of Stale Descriptor (valid only in tailpntr mode) used -- to prevent error'ed descriptor from being used. ch2_ftch_stale_desc <= ch2_stale_descriptor; end generate GEN_CH2_FETCH; ------------------------------------------------------------------------------- -- Channel excluded therefore do not generate fetch logic ------------------------------------------------------------------------------- GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate begin service_ch2 <= '0'; ch2_active_i <= '0'; ch2_ftch_idle <= '0'; ch2_ftch_interr_set <= '0'; ch2_ftch_slverr_set <= '0'; ch2_ftch_decerr_set <= '0'; ch2_ftch_err_early <= '0'; ch2_ftch_stale_desc <= '0'; end generate GEN_NO_CH2_FETCH; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- Assign fetch address fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1' else ch2_fetch_address; -- Assign bytes to transfer (BTT) fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1' else FETCH_CH2_CMD_BTT; fetch_tag <= "0001" when ch1_active_i = '1' else "0000"; -- When command by sm, drive command to ftch_cmdsts_if --GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- ftch_cmnd_wr <= '0'; -- ftch_cmnd_data <= (others => '0'); -- -- Fetch SM issued a command write -- elsif(write_cmnd_cmb = '1')then -- ftch_cmnd_wr <= '1'; -- ftch_cmnd_data <= FETCH_CMD_RSVD -- & fetch_tag -- & fetch_cmd_addr -- & FETCH_MSB_IGNORED -- & FETCH_CMD_TYPE -- & FETCH_LSB_IGNORED -- & fetch_cmd_btt; -- else -- ftch_cmnd_wr <= '0'; -- end if; -- end if; -- end process GEN_DATAMOVER_CMND; ftch_cmnd_wr <= write_cmnd_cmb; ftch_cmnd_data <= FETCH_CMD_RSVD & fetch_tag & fetch_cmd_addr & FETCH_MSB_IGNORED & FETCH_CMD_TYPE & FETCH_LSB_IGNORED & fetch_cmd_btt; ------------------------------------------------------------------------------- -- Capture and hold fetch address in case an error occurs ------------------------------------------------------------------------------- LOG_ERROR_ADDR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0'); elsif(write_cmnd_cmb = '1')then ftch_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= fetch_cmd_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB); end if; end if; end process LOG_ERROR_ADDR; ftch_error_addr (5 downto 0) <= "000000"; end implementation;
bsd-2-clause
ea47b4b33cdb5f6835ec8b3a598ef9f8
0.425823
4.41892
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/port_map/rule_002_test_input.vhd
2
585
architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1(3 downto 0) => 3, G_GEN_2(2 downto 1) => 4, G_GEN_3 => 5 ) port map ( PORT_1(3 downto 0) => w_port_1, PORT_2 => w_port_2, PORT_3(2 downto 1) => w_port_3 ); -- Violations below U_INST1 : INST1 generic map ( g_gen_1(3 downto 0) => 3, g_gen_2(2 downto 1) => 4, g_gen_3 => 5 ) port map ( port_1(3 downto 0) => w_port_1, port_2 => w_port_2, port_3(2 downto 1) => w_port_3 ); end architecture ARCH;
gpl-3.0
466513dc8167b3d66a7c163ea19996f2
0.492308
2.683486
false
false
false
false
cwilkens/ecen4024-microphone-array
microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/half_band_FIR_funcsim.vhdl
1
484,479
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014 -- Date : Mon Nov 03 20:57:00 2014 -- Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/half_band_FIR_funcsim.vhdl -- Design : half_band_FIR -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. 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"Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block icGX5jW9M9UfH4Fbpo33aLOWM0ZIbNPJssQ+4Y15eoQmg/DtPKZf9hNUGGq2Bq1dHM2ZZ9VnftkE WuFAO2aRSlRLfArJ2jxgVG07mnhBj5ivLS833132BgFC23sXhQMbSCbJ12C4kDg1OVZeEiEilO3/ VZ34TJoMxDAY2BuTt7VoVulWOrpkaM6eEqAYdOl59109jD6OWOx+higBE2JvIZaVh908dKjcP1GB 1jG0tZv2t0WVog6PeJnVTOYcx6MhYIxha0YDsb7zEntLlA081bq9M16MEU3n002THLez0XxmLnnX FvaQp+ZYkpXasytNLTF8TE3Dla+hp5m6CbQQoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MKbGhV1/FZOg0g80WSjhdP9oYk88ZTbVb0unqQ4ZKDcwvADq9vLe/CIxA4LXZTR/NJARybLlLvuVD1h11EhjTBruG9iVpRNV7hvN5IesumKPzADF5XY64jnFCe1EeGhSsoCFQPRdsHgMUp+MGbHBWPTq+eGPCoLB+RMA5d6OaFG/cC+jcfXUEfYlaabF2mlBa9QWpxJEpzp047EC2UHYPmotHxPj0a/rBBuVBXIS2rMkrP4PnBz5KPKKmRMcrX2JjgS8pxCoswuf/gBJONBHmnx6ZrVFPFgx+Qzh87VxKmJdy/ELf62D2EtC+lbHGWzeD1znOzkKNvAJvQq7IVIQFQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block QgrAhAEVwNKXHUWThUX0qA3QZ+hWr2qpdEfNP/4wwvz697dnuCzGeUg947+XOE2L2LydzwoiHzMK9vO+OEUbZ5hzqI2OUWKR8KJ2IeftQxp1wiLn/vuKnmExBY81UZ34129N7krciCCeuxjE5AlMt62/nT29RSjxBy/kyxg7n/Nb6kkJJGUXz9mYRMvVFSQt/EbMDVfAQmSIHMnpvhV8QPByi+/gU675SP5+9vZbdazCOMWPM2Tmy+Pe6EB1h83lXCFsyJLqo0MBB4yHy+gWwcQj74d+Wlp1PAGpLd2xKAjUhuZ0+mV20D6MSHS2xzDsLbPiMVXEVgN6AMnwW+V6qw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 1840) `protect data_block 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"MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UamE5dAG5MQ57cnvzbjv/nbemByPylwTykMfsMgfxnhu8KYynoWoCuMrOdf8j0bj+WgnxGj5J6Xl fEGwcU8q1nidn/W4loeFcDGryqn4WxgzPM3Pp+wjagldljTHyAiZv501E1fbakm3HMgBBPbx4ZxO nh0VGFkqOTg0EJC/vp8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block c/Iu9mELOaUlpKZt99oi/7RufIXVe9iqOjU76vF2w74mcyOGsO/Xhtl7ruhjZy/+E4/LVWwA9CLq OsyjZieTHtF5xwGDW5kECgeNUIkJAcg1eIVJhP0zEM94OgxqbwIwvz3ZITfPC+bJv/YRVdfn4eGR NeJibXKQE/L7CH4lAkM1YEyotl85T+PQ1APGJLs8SzrRD8qiOljliNjAAEQfYfMBFU0XuiS6a4n0 z6MPYENAXStgJEse5tPi8tVLosdVEzcoty37s7Nst4lc6/jT6nVZu10mCN6C/JSSAIavPx5f+kac TGOysI3H4IbP7or5YnoH5S/znz2Fy/tYN/6LjA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QzooJCNMdqnSUTKAKsQg2ex9VIY5dLW/YgIEPVErzvG8t+uFIkOZqq19S1TV1IMPEvJSjDuXAiRg Ru03UHSBacnkyxVTdBMCYRDAJWYiwpCUcA4xrRwMCPY+gDrEnlhETP9r47JOFwlxbFJ8p1yispIc Qu35Ye7NmOqCHA9KngI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block icGX5jW9M9UfH4Fbpo33aLOWM0ZIbNPJssQ+4Y15eoQmg/DtPKZf9hNUGGq2Bq1dHM2ZZ9VnftkE WuFAO2aRSlRLfArJ2jxgVG07mnhBj5ivLS833132BgFC23sXhQMbSCbJ12C4kDg1OVZeEiEilO3/ VZ34TJoMxDAY2BuTt7VoVulWOrpkaM6eEqAYdOl59109jD6OWOx+higBE2JvIZaVh908dKjcP1GB 1jG0tZv2t0WVog6PeJnVTOYcx6MhYIxha0YDsb7zEntLlA081bq9M16MEU3n002THLez0XxmLnnX FvaQp+ZYkpXasytNLTF8TE3Dla+hp5m6CbQQoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MKbGhV1/FZOg0g80WSjhdP9oYk88ZTbVb0unqQ4ZKDcwvADq9vLe/CIxA4LXZTR/NJARybLlLvuVD1h11EhjTBruG9iVpRNV7hvN5IesumKPzADF5XY64jnFCe1EeGhSsoCFQPRdsHgMUp+MGbHBWPTq+eGPCoLB+RMA5d6OaFG/cC+jcfXUEfYlaabF2mlBa9QWpxJEpzp047EC2UHYPmotHxPj0a/rBBuVBXIS2rMkrP4PnBz5KPKKmRMcrX2JjgS8pxCoswuf/gBJONBHmnx6ZrVFPFgx+Qzh87VxKmJdy/ELf62D2EtC+lbHGWzeD1znOzkKNvAJvQq7IVIQFQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block QgrAhAEVwNKXHUWThUX0qA3QZ+hWr2qpdEfNP/4wwvz697dnuCzGeUg947+XOE2L2LydzwoiHzMK9vO+OEUbZ5hzqI2OUWKR8KJ2IeftQxp1wiLn/vuKnmExBY81UZ34129N7krciCCeuxjE5AlMt62/nT29RSjxBy/kyxg7n/Nb6kkJJGUXz9mYRMvVFSQt/EbMDVfAQmSIHMnpvhV8QPByi+/gU675SP5+9vZbdazCOMWPM2Tmy+Pe6EB1h83lXCFsyJLqo0MBB4yHy+gWwcQj74d+Wlp1PAGpLd2xKAjUhuZ0+mV20D6MSHS2xzDsLbPiMVXEVgN6AMnwW+V6qw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 63088) `protect data_block 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key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block c/Iu9mELOaUlpKZt99oi/7RufIXVe9iqOjU76vF2w74mcyOGsO/Xhtl7ruhjZy/+E4/LVWwA9CLq OsyjZieTHtF5xwGDW5kECgeNUIkJAcg1eIVJhP0zEM94OgxqbwIwvz3ZITfPC+bJv/YRVdfn4eGR NeJibXKQE/L7CH4lAkM1YEyotl85T+PQ1APGJLs8SzrRD8qiOljliNjAAEQfYfMBFU0XuiS6a4n0 z6MPYENAXStgJEse5tPi8tVLosdVEzcoty37s7Nst4lc6/jT6nVZu10mCN6C/JSSAIavPx5f+kac TGOysI3H4IbP7or5YnoH5S/znz2Fy/tYN/6LjA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QzooJCNMdqnSUTKAKsQg2ex9VIY5dLW/YgIEPVErzvG8t+uFIkOZqq19S1TV1IMPEvJSjDuXAiRg Ru03UHSBacnkyxVTdBMCYRDAJWYiwpCUcA4xrRwMCPY+gDrEnlhETP9r47JOFwlxbFJ8p1yispIc Qu35Ye7NmOqCHA9KngI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block icGX5jW9M9UfH4Fbpo33aLOWM0ZIbNPJssQ+4Y15eoQmg/DtPKZf9hNUGGq2Bq1dHM2ZZ9VnftkE WuFAO2aRSlRLfArJ2jxgVG07mnhBj5ivLS833132BgFC23sXhQMbSCbJ12C4kDg1OVZeEiEilO3/ VZ34TJoMxDAY2BuTt7VoVulWOrpkaM6eEqAYdOl59109jD6OWOx+higBE2JvIZaVh908dKjcP1GB 1jG0tZv2t0WVog6PeJnVTOYcx6MhYIxha0YDsb7zEntLlA081bq9M16MEU3n002THLez0XxmLnnX FvaQp+ZYkpXasytNLTF8TE3Dla+hp5m6CbQQoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MKbGhV1/FZOg0g80WSjhdP9oYk88ZTbVb0unqQ4ZKDcwvADq9vLe/CIxA4LXZTR/NJARybLlLvuVD1h11EhjTBruG9iVpRNV7hvN5IesumKPzADF5XY64jnFCe1EeGhSsoCFQPRdsHgMUp+MGbHBWPTq+eGPCoLB+RMA5d6OaFG/cC+jcfXUEfYlaabF2mlBa9QWpxJEpzp047EC2UHYPmotHxPj0a/rBBuVBXIS2rMkrP4PnBz5KPKKmRMcrX2JjgS8pxCoswuf/gBJONBHmnx6ZrVFPFgx+Qzh87VxKmJdy/ELf62D2EtC+lbHGWzeD1znOzkKNvAJvQq7IVIQFQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block QgrAhAEVwNKXHUWThUX0qA3QZ+hWr2qpdEfNP/4wwvz697dnuCzGeUg947+XOE2L2LydzwoiHzMK9vO+OEUbZ5hzqI2OUWKR8KJ2IeftQxp1wiLn/vuKnmExBY81UZ34129N7krciCCeuxjE5AlMt62/nT29RSjxBy/kyxg7n/Nb6kkJJGUXz9mYRMvVFSQt/EbMDVfAQmSIHMnpvhV8QPByi+/gU675SP5+9vZbdazCOMWPM2Tmy+Pe6EB1h83lXCFsyJLqo0MBB4yHy+gWwcQj74d+Wlp1PAGpLd2xKAjUhuZ0+mV20D6MSHS2xzDsLbPiMVXEVgN6AMnwW+V6qw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 19184) `protect data_block ESMgvkgh/5ONfNQOpQ0mAut5bUo7KVZeNJhKemIV5vgE8lbIiRZwY3JM+kA3ybHibEYJ7TsjItvK CDEQvFMo2cnx+1NFH7AlMlHsSx4p+hzaOAmRlPYvlXg1FbeQutFjeRgwWuBuX9xCQgImWtPOAE2y 9EJDsZX6qtobJaDLdRyTIfF8e6LXFfMdw2AwD8ncs/K0hSI5WLtObvM+6wDDS/AwBIX5U90KFVkW psPgaQjbx901gzYoud/QoL+Q97gIYx4CNGpCqPRO8V7LW2HRHsMnc9k4VElTAChLlyJpbFG/8MIi eJYtT9SZDPbYgOtgG5RXcWUbLp570LuY9+8q3b7MS6Lna9hki81Bk/rJqDXHEXwkNLYP9n6fU7mS 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76, bytes = 128) `protect key_block QzooJCNMdqnSUTKAKsQg2ex9VIY5dLW/YgIEPVErzvG8t+uFIkOZqq19S1TV1IMPEvJSjDuXAiRg Ru03UHSBacnkyxVTdBMCYRDAJWYiwpCUcA4xrRwMCPY+gDrEnlhETP9r47JOFwlxbFJ8p1yispIc Qu35Ye7NmOqCHA9KngI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block icGX5jW9M9UfH4Fbpo33aLOWM0ZIbNPJssQ+4Y15eoQmg/DtPKZf9hNUGGq2Bq1dHM2ZZ9VnftkE WuFAO2aRSlRLfArJ2jxgVG07mnhBj5ivLS833132BgFC23sXhQMbSCbJ12C4kDg1OVZeEiEilO3/ VZ34TJoMxDAY2BuTt7VoVulWOrpkaM6eEqAYdOl59109jD6OWOx+higBE2JvIZaVh908dKjcP1GB 1jG0tZv2t0WVog6PeJnVTOYcx6MhYIxha0YDsb7zEntLlA081bq9M16MEU3n002THLez0XxmLnnX FvaQp+ZYkpXasytNLTF8TE3Dla+hp5m6CbQQoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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UamE5dAG5MQ57cnvzbjv/nbemByPylwTykMfsMgfxnhu8KYynoWoCuMrOdf8j0bj+WgnxGj5J6Xl fEGwcU8q1nidn/W4loeFcDGryqn4WxgzPM3Pp+wjagldljTHyAiZv501E1fbakm3HMgBBPbx4ZxO nh0VGFkqOTg0EJC/vp8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block c/Iu9mELOaUlpKZt99oi/7RufIXVe9iqOjU76vF2w74mcyOGsO/Xhtl7ruhjZy/+E4/LVWwA9CLq OsyjZieTHtF5xwGDW5kECgeNUIkJAcg1eIVJhP0zEM94OgxqbwIwvz3ZITfPC+bJv/YRVdfn4eGR NeJibXKQE/L7CH4lAkM1YEyotl85T+PQ1APGJLs8SzrRD8qiOljliNjAAEQfYfMBFU0XuiS6a4n0 z6MPYENAXStgJEse5tPi8tVLosdVEzcoty37s7Nst4lc6/jT6nVZu10mCN6C/JSSAIavPx5f+kac TGOysI3H4IbP7or5YnoH5S/znz2Fy/tYN/6LjA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QzooJCNMdqnSUTKAKsQg2ex9VIY5dLW/YgIEPVErzvG8t+uFIkOZqq19S1TV1IMPEvJSjDuXAiRg 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key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QzooJCNMdqnSUTKAKsQg2ex9VIY5dLW/YgIEPVErzvG8t+uFIkOZqq19S1TV1IMPEvJSjDuXAiRg Ru03UHSBacnkyxVTdBMCYRDAJWYiwpCUcA4xrRwMCPY+gDrEnlhETP9r47JOFwlxbFJ8p1yispIc Qu35Ye7NmOqCHA9KngI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block icGX5jW9M9UfH4Fbpo33aLOWM0ZIbNPJssQ+4Y15eoQmg/DtPKZf9hNUGGq2Bq1dHM2ZZ9VnftkE WuFAO2aRSlRLfArJ2jxgVG07mnhBj5ivLS833132BgFC23sXhQMbSCbJ12C4kDg1OVZeEiEilO3/ VZ34TJoMxDAY2BuTt7VoVulWOrpkaM6eEqAYdOl59109jD6OWOx+higBE2JvIZaVh908dKjcP1GB 1jG0tZv2t0WVog6PeJnVTOYcx6MhYIxha0YDsb7zEntLlA081bq9M16MEU3n002THLez0XxmLnnX FvaQp+ZYkpXasytNLTF8TE3Dla+hp5m6CbQQoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MKbGhV1/FZOg0g80WSjhdP9oYk88ZTbVb0unqQ4ZKDcwvADq9vLe/CIxA4LXZTR/NJARybLlLvuVD1h11EhjTBruG9iVpRNV7hvN5IesumKPzADF5XY64jnFCe1EeGhSsoCFQPRdsHgMUp+MGbHBWPTq+eGPCoLB+RMA5d6OaFG/cC+jcfXUEfYlaabF2mlBa9QWpxJEpzp047EC2UHYPmotHxPj0a/rBBuVBXIS2rMkrP4PnBz5KPKKmRMcrX2JjgS8pxCoswuf/gBJONBHmnx6ZrVFPFgx+Qzh87VxKmJdy/ELf62D2EtC+lbHGWzeD1znOzkKNvAJvQq7IVIQFQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block QgrAhAEVwNKXHUWThUX0qA3QZ+hWr2qpdEfNP/4wwvz697dnuCzGeUg947+XOE2L2LydzwoiHzMK9vO+OEUbZ5hzqI2OUWKR8KJ2IeftQxp1wiLn/vuKnmExBY81UZ34129N7krciCCeuxjE5AlMt62/nT29RSjxBy/kyxg7n/Nb6kkJJGUXz9mYRMvVFSQt/EbMDVfAQmSIHMnpvhV8QPByi+/gU675SP5+9vZbdazCOMWPM2Tmy+Pe6EB1h83lXCFsyJLqo0MBB4yHy+gWwcQj74d+Wlp1PAGpLd2xKAjUhuZ0+mV20D6MSHS2xzDsLbPiMVXEVgN6AMnwW+V6qw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = 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"Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block icGX5jW9M9UfH4Fbpo33aLOWM0ZIbNPJssQ+4Y15eoQmg/DtPKZf9hNUGGq2Bq1dHM2ZZ9VnftkE WuFAO2aRSlRLfArJ2jxgVG07mnhBj5ivLS833132BgFC23sXhQMbSCbJ12C4kDg1OVZeEiEilO3/ VZ34TJoMxDAY2BuTt7VoVulWOrpkaM6eEqAYdOl59109jD6OWOx+higBE2JvIZaVh908dKjcP1GB 1jG0tZv2t0WVog6PeJnVTOYcx6MhYIxha0YDsb7zEntLlA081bq9M16MEU3n002THLez0XxmLnnX FvaQp+ZYkpXasytNLTF8TE3Dla+hp5m6CbQQoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MKbGhV1/FZOg0g80WSjhdP9oYk88ZTbVb0unqQ4ZKDcwvADq9vLe/CIxA4LXZTR/NJARybLlLvuVD1h11EhjTBruG9iVpRNV7hvN5IesumKPzADF5XY64jnFCe1EeGhSsoCFQPRdsHgMUp+MGbHBWPTq+eGPCoLB+RMA5d6OaFG/cC+jcfXUEfYlaabF2mlBa9QWpxJEpzp047EC2UHYPmotHxPj0a/rBBuVBXIS2rMkrP4PnBz5KPKKmRMcrX2JjgS8pxCoswuf/gBJONBHmnx6ZrVFPFgx+Qzh87VxKmJdy/ELf62D2EtC+lbHGWzeD1znOzkKNvAJvQq7IVIQFQ== `protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128) `protect key_block QgrAhAEVwNKXHUWThUX0qA3QZ+hWr2qpdEfNP/4wwvz697dnuCzGeUg947+XOE2L2LydzwoiHzMK9vO+OEUbZ5hzqI2OUWKR8KJ2IeftQxp1wiLn/vuKnmExBY81UZ34129N7krciCCeuxjE5AlMt62/nT29RSjxBy/kyxg7n/Nb6kkJJGUXz9mYRMvVFSQt/EbMDVfAQmSIHMnpvhV8QPByi+/gU675SP5+9vZbdazCOMWPM2Tmy+Pe6EB1h83lXCFsyJLqo0MBB4yHy+gWwcQj74d+Wlp1PAGpLd2xKAjUhuZ0+mV20D6MSHS2xzDsLbPiMVXEVgN6AMnwW+V6qw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 64, bytes = 768) `protect data_block Y/nF0tx4MOOQIXOFJWhvdG50cI98Vmz4xOHSqDuuU9FdV+AfBu5aelFCMjf8f6r9wHYyQBWiVaOk dCSvE5XJe6M7wthy1WW7CujaVYP0aKclB+aSevNHXwomM/whC36UzhmdPz850r1wiiZhtNwcvI8s o8keWuQ5zgKKj5/Z2z/lOpd5Qvfl28YFI6L3LyeFPpUuzD4K2ghPWEPXSjUNvXSHU/h7u5lWkUMV YlXF3gW7J2mRI9kPzG8NV4fsIY24Ene2TEnDiMtmuAqK1oVXtn+Vb9NSwhOw/pQBOYj35959eX2R GhmF1xHkLJktZEKWHBH2wLz+m8ALoPY7VmTroZedWvJ0V/xYteZDLv6EqSlweC2w7fbyTorR5zsb Lm0RRzOEA1kqGboUvehv8yiYdXJPF1nT3FkQY0qcBf0OMAnbnuAO2zSTrf0IxENZO2texUfxIh9W 4p04AsLsQz0hn5U+KefyJzbDTNqVB1aa76vH30yiY2ctS7Nm8l4ak705AJwcbC4m+WyuqrCQMGAO y54OVHptk9/6RZtEqFON/MMLaYQ3DRAqSqfa2YMWZAImoESHC6Xid+Su0jXekFHNKJtzRe7/lK1B Ae7KK9qWCpIq+HfTDMS0P9Akh18Rjvuc6Q0wpMLRKWvUqUR09SrI1HpvWGZ1SBxoPSzPTM2yelao f02cAVvpqcB078H982pZtBVonHeKUiLvWql7I26ij3CuxSBXcwoQ2OXRJ6+8kGlUuBDp/ckggYr3 fGe3HjYBW8ig1AOy6KwHFgdeN/yLFqa6O+BCaFshondMH4Fhj18uqGaP5uSzuKyWOGbY4yutkAN1 x0iaaLSSjwo0SclPZNqzq3D5wuCMf+mufdLDh1sCcPfyXHTTISWULOaSinKds7JAUvOxpCR4Yw1d 0VkpC7Pzq+aBCtzg2zCsoqODQs3ACde/0CNKNLUHg+QU+VEySlxFQejojVGteyNEfqzd3vjL65Hj fnE6xbYzgxi+s8MQ2H3INlHmlkjicH4Dg2tV `protect end_protected `protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block XqJQaTuJKdlub4yCUiIhzpjkPQ+7CXZJZgjIuNSO3cJcgWtP9xabzoj0VU51IYOEvHYhf/Z4mkBM c2MJ8uzspQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UamE5dAG5MQ57cnvzbjv/nbemByPylwTykMfsMgfxnhu8KYynoWoCuMrOdf8j0bj+WgnxGj5J6Xl fEGwcU8q1nidn/W4loeFcDGryqn4WxgzPM3Pp+wjagldljTHyAiZv501E1fbakm3HMgBBPbx4ZxO nh0VGFkqOTg0EJC/vp8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block c/Iu9mELOaUlpKZt99oi/7RufIXVe9iqOjU76vF2w74mcyOGsO/Xhtl7ruhjZy/+E4/LVWwA9CLq OsyjZieTHtF5xwGDW5kECgeNUIkJAcg1eIVJhP0zEM94OgxqbwIwvz3ZITfPC+bJv/YRVdfn4eGR NeJibXKQE/L7CH4lAkM1YEyotl85T+PQ1APGJLs8SzrRD8qiOljliNjAAEQfYfMBFU0XuiS6a4n0 z6MPYENAXStgJEse5tPi8tVLosdVEzcoty37s7Nst4lc6/jT6nVZu10mCN6C/JSSAIavPx5f+kac TGOysI3H4IbP7or5YnoH5S/znz2Fy/tYN/6LjA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QzooJCNMdqnSUTKAKsQg2ex9VIY5dLW/YgIEPVErzvG8t+uFIkOZqq19S1TV1IMPEvJSjDuXAiRg Ru03UHSBacnkyxVTdBMCYRDAJWYiwpCUcA4xrRwMCPY+gDrEnlhETP9r47JOFwlxbFJ8p1yispIc Qu35Ye7NmOqCHA9KngI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block icGX5jW9M9UfH4Fbpo33aLOWM0ZIbNPJssQ+4Y15eoQmg/DtPKZf9hNUGGq2Bq1dHM2ZZ9VnftkE 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begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block XqJQaTuJKdlub4yCUiIhzpjkPQ+7CXZJZgjIuNSO3cJcgWtP9xabzoj0VU51IYOEvHYhf/Z4mkBM c2MJ8uzspQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UamE5dAG5MQ57cnvzbjv/nbemByPylwTykMfsMgfxnhu8KYynoWoCuMrOdf8j0bj+WgnxGj5J6Xl fEGwcU8q1nidn/W4loeFcDGryqn4WxgzPM3Pp+wjagldljTHyAiZv501E1fbakm3HMgBBPbx4ZxO nh0VGFkqOTg0EJC/vp8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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(enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block icGX5jW9M9UfH4Fbpo33aLOWM0ZIbNPJssQ+4Y15eoQmg/DtPKZf9hNUGGq2Bq1dHM2ZZ9VnftkE WuFAO2aRSlRLfArJ2jxgVG07mnhBj5ivLS833132BgFC23sXhQMbSCbJ12C4kDg1OVZeEiEilO3/ VZ34TJoMxDAY2BuTt7VoVulWOrpkaM6eEqAYdOl59109jD6OWOx+higBE2JvIZaVh908dKjcP1GB 1jG0tZv2t0WVog6PeJnVTOYcx6MhYIxha0YDsb7zEntLlA081bq9M16MEU3n002THLez0XxmLnnX FvaQp+ZYkpXasytNLTF8TE3Dla+hp5m6CbQQoQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MKbGhV1/FZOg0g80WSjhdP9oYk88ZTbVb0unqQ4ZKDcwvADq9vLe/CIxA4LXZTR/NJARybLlLvuVD1h11EhjTBruG9iVpRNV7hvN5IesumKPzADF5XY64jnFCe1EeGhSsoCFQPRdsHgMUp+MGbHBWPTq+eGPCoLB+RMA5d6OaFG/cC+jcfXUEfYlaabF2mlBa9QWpxJEpzp047EC2UHYPmotHxPj0a/rBBuVBXIS2rMkrP4PnBz5KPKKmRMcrX2JjgS8pxCoswuf/gBJONBHmnx6ZrVFPFgx+Qzh87VxKmJdy/ELf62D2EtC+lbHGWzeD1znOzkKNvAJvQq7IVIQFQ== `protect key_keyowner = "Synplicity", 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(enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UamE5dAG5MQ57cnvzbjv/nbemByPylwTykMfsMgfxnhu8KYynoWoCuMrOdf8j0bj+WgnxGj5J6Xl fEGwcU8q1nidn/W4loeFcDGryqn4WxgzPM3Pp+wjagldljTHyAiZv501E1fbakm3HMgBBPbx4ZxO nh0VGFkqOTg0EJC/vp8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block c/Iu9mELOaUlpKZt99oi/7RufIXVe9iqOjU76vF2w74mcyOGsO/Xhtl7ruhjZy/+E4/LVWwA9CLq OsyjZieTHtF5xwGDW5kECgeNUIkJAcg1eIVJhP0zEM94OgxqbwIwvz3ZITfPC+bJv/YRVdfn4eGR NeJibXKQE/L7CH4lAkM1YEyotl85T+PQ1APGJLs8SzrRD8qiOljliNjAAEQfYfMBFU0XuiS6a4n0 z6MPYENAXStgJEse5tPi8tVLosdVEzcoty37s7Nst4lc6/jT6nVZu10mCN6C/JSSAIavPx5f+kac TGOysI3H4IbP7or5YnoH5S/znz2Fy/tYN/6LjA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 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); s_axis_data_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); s_axis_config_tvalid : in STD_LOGIC; s_axis_config_tready : out STD_LOGIC; s_axis_config_tlast : in STD_LOGIC; s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_reload_tvalid : in STD_LOGIC; s_axis_reload_tready : out STD_LOGIC; s_axis_reload_tlast : in STD_LOGIC; s_axis_reload_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_data_tvalid : out STD_LOGIC; m_axis_data_tready : in STD_LOGIC; m_axis_data_tlast : out STD_LOGIC; m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ); event_s_data_tlast_missing : out STD_LOGIC; event_s_data_tlast_unexpected : out STD_LOGIC; event_s_data_chanid_incorrect : out STD_LOGIC; event_s_config_tlast_missing : out STD_LOGIC; event_s_config_tlast_unexpected : out STD_LOGIC; event_s_reload_tlast_missing : out STD_LOGIC; event_s_reload_tlast_unexpected : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "fir_compiler_v7_1"; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "artix7"; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "./"; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "half_band_FIR"; attribute C_COEF_FILE : string; attribute C_COEF_FILE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "half_band_FIR.mif"; attribute C_COEF_FILE_LINES : integer; attribute C_COEF_FILE_LINES of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 5; attribute C_FILTER_TYPE : integer; attribute C_FILTER_TYPE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 7; attribute C_INTERP_RATE : integer; attribute C_INTERP_RATE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_DECIM_RATE : integer; attribute C_DECIM_RATE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 2; attribute C_ZERO_PACKING_FACTOR : integer; attribute C_ZERO_PACKING_FACTOR of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_SYMMETRY : integer; attribute C_SYMMETRY of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_NUM_FILTS : integer; attribute C_NUM_FILTS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_NUM_TAPS : integer; attribute C_NUM_TAPS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 15; attribute C_NUM_CHANNELS : integer; attribute C_NUM_CHANNELS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_CHANNEL_PATTERN : string; attribute C_CHANNEL_PATTERN of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "fixed"; attribute C_ROUND_MODE : integer; attribute C_ROUND_MODE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_COEF_RELOAD : integer; attribute C_COEF_RELOAD of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_NUM_RELOAD_SLOTS : integer; attribute C_NUM_RELOAD_SLOTS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_COL_MODE : integer; attribute C_COL_MODE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_COL_PIPE_LEN : integer; attribute C_COL_PIPE_LEN of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 4; attribute C_COL_CONFIG : string; attribute C_COL_CONFIG of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "1"; attribute C_OPTIMIZATION : integer; attribute C_OPTIMIZATION of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_DATA_PATH_WIDTHS : string; attribute C_DATA_PATH_WIDTHS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "22"; attribute C_DATA_IP_PATH_WIDTHS : string; attribute C_DATA_IP_PATH_WIDTHS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "22"; attribute C_DATA_PX_PATH_WIDTHS : string; attribute C_DATA_PX_PATH_WIDTHS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "22"; attribute C_DATA_WIDTH : integer; attribute C_DATA_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 22; attribute C_COEF_PATH_WIDTHS : string; attribute C_COEF_PATH_WIDTHS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "15"; attribute C_COEF_WIDTH : integer; attribute C_COEF_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 15; attribute C_DATA_PATH_SRC : string; attribute C_DATA_PATH_SRC of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "0"; attribute C_COEF_PATH_SRC : string; attribute C_COEF_PATH_SRC of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "0"; attribute C_DATA_PATH_SIGN : string; attribute C_DATA_PATH_SIGN of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "0"; attribute C_COEF_PATH_SIGN : string; attribute C_COEF_PATH_SIGN of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "0"; attribute C_ACCUM_PATH_WIDTHS : string; attribute C_ACCUM_PATH_WIDTHS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "38"; attribute C_OUTPUT_WIDTH : integer; attribute C_OUTPUT_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 22; attribute C_OUTPUT_PATH_WIDTHS : string; attribute C_OUTPUT_PATH_WIDTHS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "22"; attribute C_ACCUM_OP_PATH_WIDTHS : string; attribute C_ACCUM_OP_PATH_WIDTHS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "38"; attribute C_EXT_MULT_CNFG : string; attribute C_EXT_MULT_CNFG of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "none"; attribute C_DATA_PATH_PSAMP_SRC : string; attribute C_DATA_PATH_PSAMP_SRC of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "0"; attribute C_OP_PATH_PSAMP_SRC : string; attribute C_OP_PATH_PSAMP_SRC of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "0"; attribute C_NUM_MADDS : integer; attribute C_NUM_MADDS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_OPT_MADDS : string; attribute C_OPT_MADDS of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "none"; attribute C_OVERSAMPLING_RATE : integer; attribute C_OVERSAMPLING_RATE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 5; attribute C_INPUT_RATE : integer; attribute C_INPUT_RATE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 16; attribute C_OUTPUT_RATE : integer; attribute C_OUTPUT_RATE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 32; attribute C_DATA_MEMTYPE : integer; attribute C_DATA_MEMTYPE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_COEF_MEMTYPE : integer; attribute C_COEF_MEMTYPE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 2; attribute C_IPBUFF_MEMTYPE : integer; attribute C_IPBUFF_MEMTYPE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 2; attribute C_OPBUFF_MEMTYPE : integer; attribute C_OPBUFF_MEMTYPE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_DATAPATH_MEMTYPE : integer; attribute C_DATAPATH_MEMTYPE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 2; attribute C_MEM_ARRANGEMENT : integer; attribute C_MEM_ARRANGEMENT of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_DATA_MEM_PACKING : integer; attribute C_DATA_MEM_PACKING of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_COEF_MEM_PACKING : integer; attribute C_COEF_MEM_PACKING of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_FILTS_PACKED : integer; attribute C_FILTS_PACKED of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_LATENCY : integer; attribute C_LATENCY of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 42; attribute C_HAS_ARESETn : integer; attribute C_HAS_ARESETn of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_HAS_ACLKEN : integer; attribute C_HAS_ACLKEN of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_DATA_HAS_TLAST : integer; attribute C_DATA_HAS_TLAST of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_S_DATA_HAS_FIFO : integer; attribute C_S_DATA_HAS_FIFO of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_S_DATA_HAS_TUSER : integer; attribute C_S_DATA_HAS_TUSER of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_S_DATA_TDATA_WIDTH : integer; attribute C_S_DATA_TDATA_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 24; attribute C_S_DATA_TUSER_WIDTH : integer; attribute C_S_DATA_TUSER_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_M_DATA_HAS_TREADY : integer; attribute C_M_DATA_HAS_TREADY of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_M_DATA_HAS_TUSER : integer; attribute C_M_DATA_HAS_TUSER of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_M_DATA_TDATA_WIDTH : integer; attribute C_M_DATA_TDATA_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 24; attribute C_M_DATA_TUSER_WIDTH : integer; attribute C_M_DATA_TUSER_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_HAS_CONFIG_CHANNEL : integer; attribute C_HAS_CONFIG_CHANNEL of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_CONFIG_SYNC_MODE : integer; attribute C_CONFIG_SYNC_MODE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_CONFIG_PACKET_SIZE : integer; attribute C_CONFIG_PACKET_SIZE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 0; attribute C_CONFIG_TDATA_WIDTH : integer; attribute C_CONFIG_TDATA_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute C_RELOAD_TDATA_WIDTH : integer; attribute C_RELOAD_TDATA_WIDTH of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is 1; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of \half_band_FIR_fir_compiler_v7_1__parameterized0\ : entity is "yes"; end \half_band_FIR_fir_compiler_v7_1__parameterized0\; architecture STRUCTURE of \half_band_FIR_fir_compiler_v7_1__parameterized0\ is attribute C_ACCUM_OP_PATH_WIDTHS of i_synth : label is "38"; attribute C_ACCUM_PATH_WIDTHS of i_synth : label is "38"; attribute C_CHANNEL_PATTERN of i_synth : label is "fixed"; attribute C_COEF_FILE of i_synth : label is "half_band_FIR.mif"; attribute C_COEF_FILE_LINES of i_synth : label is 5; attribute C_COEF_MEMTYPE of i_synth : label is 2; attribute C_COEF_MEM_PACKING of i_synth : label is 0; attribute C_COEF_PATH_SIGN of i_synth : label is "0"; attribute C_COEF_PATH_SRC of i_synth : label is "0"; attribute C_COEF_PATH_WIDTHS of i_synth : label is "15"; attribute C_COEF_RELOAD of i_synth : label is 0; attribute C_COEF_WIDTH of i_synth : label is 15; attribute C_COL_CONFIG of i_synth : label is "1"; attribute C_COL_MODE of i_synth : label is 1; attribute C_COL_PIPE_LEN of i_synth : label is 4; attribute C_COMPONENT_NAME of i_synth : label is "half_band_FIR"; attribute C_CONFIG_PACKET_SIZE of i_synth : label is 0; attribute C_CONFIG_SYNC_MODE of i_synth : label is 0; attribute C_CONFIG_TDATA_WIDTH of i_synth : label is 1; attribute C_DATAPATH_MEMTYPE of i_synth : label is 2; attribute C_DATA_HAS_TLAST of i_synth : label is 0; attribute C_DATA_IP_PATH_WIDTHS of i_synth : label is "22"; attribute C_DATA_MEMTYPE of i_synth : label is 0; attribute C_DATA_MEM_PACKING of i_synth : label is 0; attribute C_DATA_PATH_PSAMP_SRC of i_synth : label is "0"; attribute C_DATA_PATH_SIGN of i_synth : label is "0"; attribute C_DATA_PATH_SRC of i_synth : label is "0"; attribute C_DATA_PATH_WIDTHS of i_synth : label is "22"; attribute C_DATA_PX_PATH_WIDTHS of i_synth : label is "22"; attribute C_DATA_WIDTH of i_synth : label is 22; attribute C_DECIM_RATE of i_synth : label is 2; attribute C_ELABORATION_DIR of i_synth : label is "./"; attribute C_EXT_MULT_CNFG of i_synth : label is "none"; attribute C_FILTER_TYPE of i_synth : label is 7; attribute C_FILTS_PACKED of i_synth : label is 0; attribute C_HAS_ACLKEN of i_synth : label is 0; attribute C_HAS_ARESETn of i_synth : label is 0; attribute C_HAS_CONFIG_CHANNEL of i_synth : label is 0; attribute C_INPUT_RATE of i_synth : label is 16; attribute C_INTERP_RATE of i_synth : label is 1; attribute C_IPBUFF_MEMTYPE of i_synth : label is 2; attribute C_LATENCY of i_synth : label is 42; attribute C_MEM_ARRANGEMENT of i_synth : label is 1; attribute C_M_DATA_HAS_TREADY of i_synth : label is 0; attribute C_M_DATA_HAS_TUSER of i_synth : label is 0; attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 24; attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1; attribute C_NUM_CHANNELS of i_synth : label is 1; attribute C_NUM_FILTS of i_synth : label is 1; attribute C_NUM_MADDS of i_synth : label is 1; attribute C_NUM_RELOAD_SLOTS of i_synth : label is 1; attribute C_NUM_TAPS of i_synth : label is 15; attribute C_OPBUFF_MEMTYPE of i_synth : label is 0; attribute C_OPTIMIZATION of i_synth : label is 0; attribute C_OPT_MADDS of i_synth : label is "none"; attribute C_OP_PATH_PSAMP_SRC of i_synth : label is "0"; attribute C_OUTPUT_PATH_WIDTHS of i_synth : label is "22"; attribute C_OUTPUT_RATE of i_synth : label is 32; attribute C_OUTPUT_WIDTH of i_synth : label is 22; attribute C_OVERSAMPLING_RATE of i_synth : label is 5; attribute C_RELOAD_TDATA_WIDTH of i_synth : label is 1; attribute C_ROUND_MODE of i_synth : label is 1; attribute C_SYMMETRY of i_synth : label is 1; attribute C_S_DATA_HAS_FIFO of i_synth : label is 1; attribute C_S_DATA_HAS_TUSER of i_synth : label is 0; attribute C_S_DATA_TDATA_WIDTH of i_synth : label is 24; attribute C_S_DATA_TUSER_WIDTH of i_synth : label is 1; attribute C_XDEVICEFAMILY of i_synth : label is "artix7"; attribute C_ZERO_PACKING_FACTOR of i_synth : label is 1; attribute downgradeipidentifiedwarnings of i_synth : label is "yes"; attribute secure_extras : string; attribute secure_extras of i_synth : label is "A"; begin i_synth: entity work.\half_band_FIR_fir_compiler_v7_1_viv__parameterized0\ port map ( aclk => aclk, aclken => aclken, aresetn => aresetn, event_s_config_tlast_missing => event_s_config_tlast_missing, event_s_config_tlast_unexpected => event_s_config_tlast_unexpected, event_s_data_chanid_incorrect => event_s_data_chanid_incorrect, event_s_data_tlast_missing => event_s_data_tlast_missing, event_s_data_tlast_unexpected => event_s_data_tlast_unexpected, event_s_reload_tlast_missing => event_s_reload_tlast_missing, event_s_reload_tlast_unexpected => event_s_reload_tlast_unexpected, m_axis_data_tdata(23 downto 0) => m_axis_data_tdata(23 downto 0), m_axis_data_tlast => m_axis_data_tlast, m_axis_data_tready => m_axis_data_tready, m_axis_data_tuser(0) => m_axis_data_tuser(0), m_axis_data_tvalid => m_axis_data_tvalid, s_axis_config_tdata(0) => s_axis_config_tdata(0), s_axis_config_tlast => s_axis_config_tlast, s_axis_config_tready => s_axis_config_tready, s_axis_config_tvalid => s_axis_config_tvalid, s_axis_data_tdata(23 downto 0) => s_axis_data_tdata(23 downto 0), s_axis_data_tlast => s_axis_data_tlast, s_axis_data_tready => s_axis_data_tready, s_axis_data_tuser(0) => s_axis_data_tuser(0), s_axis_data_tvalid => s_axis_data_tvalid, s_axis_reload_tdata(0) => s_axis_reload_tdata(0), s_axis_reload_tlast => s_axis_reload_tlast, s_axis_reload_tready => s_axis_reload_tready, s_axis_reload_tvalid => s_axis_reload_tvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity half_band_FIR is port ( aclk : in STD_LOGIC; s_axis_data_tvalid : in STD_LOGIC; s_axis_data_tready : out STD_LOGIC; s_axis_data_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 ); m_axis_data_tvalid : out STD_LOGIC; m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of half_band_FIR : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of half_band_FIR : entity is "yes"; attribute x_core_info : string; attribute x_core_info of half_band_FIR : entity is "fir_compiler_v7_1,Vivado 2014.2"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of half_band_FIR : entity is "half_band_FIR,fir_compiler_v7_1,{}"; attribute core_generation_info : string; attribute core_generation_info of half_band_FIR : entity is "half_band_FIR,fir_compiler_v7_1,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_COMPONENT_NAME=half_band_FIR,C_COEF_FILE=half_band_FIR.mif,C_COEF_FILE_LINES=5,C_FILTER_TYPE=7,C_INTERP_RATE=1,C_DECIM_RATE=2,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=15,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=fixed,C_ROUND_MODE=1,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=1,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=22,C_DATA_IP_PATH_WIDTHS=22,C_DATA_PX_PATH_WIDTHS=22,C_DATA_WIDTH=22,C_COEF_PATH_WIDTHS=15,C_COEF_WIDTH=15,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=38,C_OUTPUT_WIDTH=22,C_OUTPUT_PATH_WIDTHS=22,C_ACCUM_OP_PATH_WIDTHS=38,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_MADDS=1,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=5,C_INPUT_RATE=16,C_OUTPUT_RATE=32,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=2,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=42,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=24,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=24,C_M_DATA_TUSER_WIDTH=1,C_HAS_CONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}"; end half_band_FIR; architecture STRUCTURE of half_band_FIR is signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_s_data_tlast_missing_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_s_reload_tlast_missing_UNCONNECTED : STD_LOGIC; signal NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axis_reload_tready_UNCONNECTED : STD_LOGIC; signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_ACCUM_OP_PATH_WIDTHS : string; attribute C_ACCUM_OP_PATH_WIDTHS of U0 : label is "38"; attribute C_ACCUM_PATH_WIDTHS : string; attribute C_ACCUM_PATH_WIDTHS of U0 : label is "38"; attribute C_CHANNEL_PATTERN : string; attribute C_CHANNEL_PATTERN of U0 : label is "fixed"; attribute C_COEF_FILE : string; attribute C_COEF_FILE of U0 : label is "half_band_FIR.mif"; attribute C_COEF_FILE_LINES : integer; attribute C_COEF_FILE_LINES of U0 : label is 5; attribute C_COEF_MEMTYPE : integer; attribute C_COEF_MEMTYPE of U0 : label is 2; attribute C_COEF_MEM_PACKING : integer; attribute C_COEF_MEM_PACKING of U0 : label is 0; attribute C_COEF_PATH_SIGN : string; attribute C_COEF_PATH_SIGN of U0 : label is "0"; attribute C_COEF_PATH_SRC : string; attribute C_COEF_PATH_SRC of U0 : label is "0"; attribute C_COEF_PATH_WIDTHS : string; attribute C_COEF_PATH_WIDTHS of U0 : label is "15"; attribute C_COEF_RELOAD : integer; attribute C_COEF_RELOAD of U0 : label is 0; attribute C_COEF_WIDTH : integer; attribute C_COEF_WIDTH of U0 : label is 15; attribute C_COL_CONFIG : string; attribute C_COL_CONFIG of U0 : label is "1"; attribute C_COL_MODE : integer; attribute C_COL_MODE of U0 : label is 1; attribute C_COL_PIPE_LEN : integer; attribute C_COL_PIPE_LEN of U0 : label is 4; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of U0 : label is "half_band_FIR"; attribute C_CONFIG_PACKET_SIZE : integer; attribute C_CONFIG_PACKET_SIZE of U0 : label is 0; attribute C_CONFIG_SYNC_MODE : integer; attribute C_CONFIG_SYNC_MODE of U0 : label is 0; attribute C_CONFIG_TDATA_WIDTH : integer; attribute C_CONFIG_TDATA_WIDTH of U0 : label is 1; attribute C_DATAPATH_MEMTYPE : integer; attribute C_DATAPATH_MEMTYPE of U0 : label is 2; attribute C_DATA_HAS_TLAST : integer; attribute C_DATA_HAS_TLAST of U0 : label is 0; attribute C_DATA_IP_PATH_WIDTHS : string; attribute C_DATA_IP_PATH_WIDTHS of U0 : label is "22"; attribute C_DATA_MEMTYPE : integer; attribute C_DATA_MEMTYPE of U0 : label is 0; attribute C_DATA_MEM_PACKING : integer; attribute C_DATA_MEM_PACKING of U0 : label is 0; attribute C_DATA_PATH_PSAMP_SRC : string; attribute C_DATA_PATH_PSAMP_SRC of U0 : label is "0"; attribute C_DATA_PATH_SIGN : string; attribute C_DATA_PATH_SIGN of U0 : label is "0"; attribute C_DATA_PATH_SRC : string; attribute C_DATA_PATH_SRC of U0 : label is "0"; attribute C_DATA_PATH_WIDTHS : string; attribute C_DATA_PATH_WIDTHS of U0 : label is "22"; attribute C_DATA_PX_PATH_WIDTHS : string; attribute C_DATA_PX_PATH_WIDTHS of U0 : label is "22"; attribute C_DATA_WIDTH : integer; attribute C_DATA_WIDTH of U0 : label is 22; attribute C_DECIM_RATE : integer; attribute C_DECIM_RATE of U0 : label is 2; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_EXT_MULT_CNFG : string; attribute C_EXT_MULT_CNFG of U0 : label is "none"; attribute C_FILTER_TYPE : integer; attribute C_FILTER_TYPE of U0 : label is 7; attribute C_FILTS_PACKED : integer; attribute C_FILTS_PACKED of U0 : label is 0; attribute C_HAS_ACLKEN : integer; attribute C_HAS_ACLKEN of U0 : label is 0; attribute C_HAS_ARESETn : integer; attribute C_HAS_ARESETn of U0 : label is 0; attribute C_HAS_CONFIG_CHANNEL : integer; attribute C_HAS_CONFIG_CHANNEL of U0 : label is 0; attribute C_INPUT_RATE : integer; attribute C_INPUT_RATE of U0 : label is 16; attribute C_INTERP_RATE : integer; attribute C_INTERP_RATE of U0 : label is 1; attribute C_IPBUFF_MEMTYPE : integer; attribute C_IPBUFF_MEMTYPE of U0 : label is 2; attribute C_LATENCY : integer; attribute C_LATENCY of U0 : label is 42; attribute C_MEM_ARRANGEMENT : integer; attribute C_MEM_ARRANGEMENT of U0 : label is 1; attribute C_M_DATA_HAS_TREADY : integer; attribute C_M_DATA_HAS_TREADY of U0 : label is 0; attribute C_M_DATA_HAS_TUSER : integer; attribute C_M_DATA_HAS_TUSER of U0 : label is 0; attribute C_M_DATA_TDATA_WIDTH : integer; attribute C_M_DATA_TDATA_WIDTH of U0 : label is 24; attribute C_M_DATA_TUSER_WIDTH : integer; attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1; attribute C_NUM_CHANNELS : integer; attribute C_NUM_CHANNELS of U0 : label is 1; attribute C_NUM_FILTS : integer; attribute C_NUM_FILTS of U0 : label is 1; attribute C_NUM_MADDS : integer; attribute C_NUM_MADDS of U0 : label is 1; attribute C_NUM_RELOAD_SLOTS : integer; attribute C_NUM_RELOAD_SLOTS of U0 : label is 1; attribute C_NUM_TAPS : integer; attribute C_NUM_TAPS of U0 : label is 15; attribute C_OPBUFF_MEMTYPE : integer; attribute C_OPBUFF_MEMTYPE of U0 : label is 0; attribute C_OPTIMIZATION : integer; attribute C_OPTIMIZATION of U0 : label is 0; attribute C_OPT_MADDS : string; attribute C_OPT_MADDS of U0 : label is "none"; attribute C_OP_PATH_PSAMP_SRC : string; attribute C_OP_PATH_PSAMP_SRC of U0 : label is "0"; attribute C_OUTPUT_PATH_WIDTHS : string; attribute C_OUTPUT_PATH_WIDTHS of U0 : label is "22"; attribute C_OUTPUT_RATE : integer; attribute C_OUTPUT_RATE of U0 : label is 32; attribute C_OUTPUT_WIDTH : integer; attribute C_OUTPUT_WIDTH of U0 : label is 22; attribute C_OVERSAMPLING_RATE : integer; attribute C_OVERSAMPLING_RATE of U0 : label is 5; attribute C_RELOAD_TDATA_WIDTH : integer; attribute C_RELOAD_TDATA_WIDTH of U0 : label is 1; attribute C_ROUND_MODE : integer; attribute C_ROUND_MODE of U0 : label is 1; attribute C_SYMMETRY : integer; attribute C_SYMMETRY of U0 : label is 1; attribute C_S_DATA_HAS_FIFO : integer; attribute C_S_DATA_HAS_FIFO of U0 : label is 1; attribute C_S_DATA_HAS_TUSER : integer; attribute C_S_DATA_HAS_TUSER of U0 : label is 0; attribute C_S_DATA_TDATA_WIDTH : integer; attribute C_S_DATA_TDATA_WIDTH of U0 : label is 24; attribute C_S_DATA_TUSER_WIDTH : integer; attribute C_S_DATA_TUSER_WIDTH of U0 : label is 1; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "artix7"; attribute C_ZERO_PACKING_FACTOR : integer; attribute C_ZERO_PACKING_FACTOR of U0 : label is 1; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.\half_band_FIR_fir_compiler_v7_1__parameterized0\ port map ( aclk => aclk, aclken => '1', aresetn => '1', event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED, event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED, event_s_data_chanid_incorrect => NLW_U0_event_s_data_chanid_incorrect_UNCONNECTED, event_s_data_tlast_missing => NLW_U0_event_s_data_tlast_missing_UNCONNECTED, event_s_data_tlast_unexpected => NLW_U0_event_s_data_tlast_unexpected_UNCONNECTED, event_s_reload_tlast_missing => NLW_U0_event_s_reload_tlast_missing_UNCONNECTED, event_s_reload_tlast_unexpected => NLW_U0_event_s_reload_tlast_unexpected_UNCONNECTED, m_axis_data_tdata(23 downto 0) => m_axis_data_tdata(23 downto 0), m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED, m_axis_data_tready => '1', m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0), m_axis_data_tvalid => m_axis_data_tvalid, s_axis_config_tdata(0) => '0', s_axis_config_tlast => '0', s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED, s_axis_config_tvalid => '0', s_axis_data_tdata(23 downto 0) => s_axis_data_tdata(23 downto 0), s_axis_data_tlast => '0', s_axis_data_tready => s_axis_data_tready, s_axis_data_tuser(0) => '0', s_axis_data_tvalid => s_axis_data_tvalid, s_axis_reload_tdata(0) => '0', s_axis_reload_tlast => '0', s_axis_reload_tready => NLW_U0_s_axis_reload_tready_UNCONNECTED, s_axis_reload_tvalid => '0' ); end STRUCTURE;
mit
ff2a3b8608e38006c9a1e0351eed7fe4
0.930932
1.884729
false
false
false
false
cwilkens/ecen4024-microphone-array
microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/axi_utils_v2_0/hdl/axi_utils_comps.vhd
3
35,937
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mit
80f7554c6eeae266d61ef8fbad507427
0.949718
1.837364
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false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_bram_0/daala_zynq_axi_bram_ctrl_0_bram_0/simulation/checker.vhd
1
5,607
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v8_0 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
bsd-2-clause
472d8d5fb941ab3c0d79bc843d24af15
0.589085
4.254173
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_input_block.vhd
2
45,404
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tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_rst_module.vhd
1
24,298
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_rst_module.vhd -- Description: This entity is the top level reset module entity for the -- AXI VDMA core. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; library proc_common_v4_0; use proc_common_v4_0.family_support.all; ------------------------------------------------------------------------------- entity axi_dma_rst_module is generic( C_INCLUDE_MM2S : integer range 0 to 1 := 1; -- Include or exclude MM2S primary data path -- 0 = Exclude MM2S primary data path -- 1 = Include MM2S primary data path C_INCLUDE_S2MM : integer range 0 to 1 := 1; -- Include or exclude S2MM primary data path -- 0 = Exclude S2MM primary data path -- 1 = Include S2MM primary data path C_INCLUDE_SG : integer range 0 to 1 := 1; -- Include or Exclude the Scatter Gather Engine -- 0 = Exclude SG Engine - Enables Simple DMA Mode -- 1 = Include SG Engine - Enables Scatter Gather Mode C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000; -- Primary clock frequency in hertz C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000; -- Primary clock frequency in hertz C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000 -- Scatter Gather clock frequency in hertz ); port ( ----------------------------------------------------------------------- -- Clock Sources ----------------------------------------------------------------------- s_axi_lite_aclk : in std_logic ; m_axi_sg_aclk : in std_logic ; -- m_axi_mm2s_aclk : in std_logic ; -- m_axi_s2mm_aclk : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- Hard Reset -- ----------------------------------------------------------------------- -- axi_resetn : in std_logic ; -- ----------------------------------------------------------------------- -- -- Soft Reset -- ----------------------------------------------------------------------- -- soft_reset : in std_logic ; -- soft_reset_clr : out std_logic := '0' ; -- -- ----------------------------------------------------------------------- -- -- MM2S Soft Reset Support -- ----------------------------------------------------------------------- -- mm2s_all_idle : in std_logic ; -- mm2s_stop : in std_logic ; -- mm2s_halt : out std_logic := '0' ; -- mm2s_halt_cmplt : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- S2MM Soft Reset Support -- ----------------------------------------------------------------------- -- s2mm_all_idle : in std_logic ; -- s2mm_stop : in std_logic ; -- s2mm_halt : out std_logic := '0' ; -- s2mm_halt_cmplt : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- MM2S Distributed Reset Out -- ----------------------------------------------------------------------- -- -- AXI DataMover Primary Reset (Raw) -- dm_mm2s_prmry_resetn : out std_logic := '1' ; -- -- AXI DataMover Secondary Reset (Raw) -- dm_mm2s_scndry_resetn : out std_logic := '1' ; -- AXI Stream Primary Reset Outputs -- mm2s_prmry_reset_out_n : out std_logic := '1' ; -- -- AXI Stream Control Reset Outputs -- mm2s_cntrl_reset_out_n : out std_logic := '1' ; -- -- AXI Secondary reset mm2s_scndry_resetn : out std_logic := '1' ; -- -- AXI Upsizer and Line Buffer -- mm2s_prmry_resetn : out std_logic := '1' ; -- -- -- ----------------------------------------------------------------------- -- -- S2MM Distributed Reset Out -- ----------------------------------------------------------------------- -- -- AXI DataMover Primary Reset (Raw) -- dm_s2mm_prmry_resetn : out std_logic := '1' ; -- -- AXI DataMover Secondary Reset (Raw) -- dm_s2mm_scndry_resetn : out std_logic := '1' ; -- AXI Stream Primary Reset Outputs -- s2mm_prmry_reset_out_n : out std_logic := '1' ; -- -- AXI Stream Control Reset Outputs -- s2mm_sts_reset_out_n : out std_logic := '1' ; -- -- AXI Secondary reset s2mm_scndry_resetn : out std_logic := '1' ; -- -- AXI Upsizer and Line Buffer -- s2mm_prmry_resetn : out std_logic := '1' ; -- ----------------------------------------------------------------------- -- -- Scatter Gather Distributed Reset Out ----------------------------------------------------------------------- -- -- AXI Scatter Gather Reset Out m_axi_sg_aresetn : out std_logic := '1' ; -- -- AXI Scatter Gather Datamover Reset Out dm_m_axi_sg_aresetn : out std_logic := '1' ; -- ----------------------------------------------------------------------- -- -- Hard Reset Out -- ----------------------------------------------------------------------- -- m_axi_sg_hrdresetn : out std_logic := '1' ; -- s_axi_lite_resetn : out std_logic := '1' -- ); Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of s_axi_lite_resetn : signal is "TRUE"; Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE"; Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no"; end axi_dma_rst_module; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_rst_module is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- ATTRIBUTE async_reg : STRING; signal hrd_resetn_i_cdc_tig : std_logic := '1'; signal hrd_resetn_i_d1_cdc_tig : std_logic := '1'; --ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true"; -- Soft reset support signal mm2s_soft_reset_clr : std_logic := '0'; signal s2mm_soft_reset_clr : std_logic := '0'; signal soft_reset_clr_i : std_logic := '0'; signal mm2s_soft_reset_done : std_logic := '0'; signal s2mm_soft_reset_done : std_logic := '0'; signal mm2s_scndry_resetn_i : std_logic := '0'; signal s2mm_scndry_resetn_i : std_logic := '0'; signal dm_mm2s_scndry_resetn_i : std_logic := '0'; signal dm_s2mm_scndry_resetn_i : std_logic := '0'; signal sg_hard_reset : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Register hard reset in REG_HRD_RST : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => axi_resetn, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => sg_hard_reset, scndry_vect_out => open ); m_axi_sg_hrdresetn <= sg_hard_reset; --REG_HRD_RST : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- hrd_resetn_i_cdc_tig <= axi_resetn; -- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig; -- end if; -- end process REG_HRD_RST; -- Regsiter hard reset out for axi lite interface REG_HRD_RST_OUT : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => axi_resetn, prmry_vect_in => (others => '0'), scndry_aclk => s_axi_lite_aclk, scndry_resetn => '0', scndry_out => s_axi_lite_resetn, scndry_vect_out => open ); --REG_HRD_RST_OUT : process(s_axi_lite_aclk) -- begin -- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then -- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig; -- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig; -- end if; -- end process REG_HRD_RST_OUT; dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i; dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i; -- mm2s channel included therefore map secondary resets to -- from mm2s reset module to scatter gather interface (default) MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate begin -- both must be low before sg reset is asserted. m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i; end generate MAP_SG_FOR_BOTH; -- Only s2mm channel included therefore map secondary resets to -- from s2mm reset module to scatter gather interface MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate begin m_axi_sg_aresetn <= s2mm_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i; end generate MAP_SG_FOR_S2MM; -- Only mm2s channel included therefore map secondary resets to -- from mm2s reset module to scatter gather interface MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate begin m_axi_sg_aresetn <= mm2s_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i; end generate MAP_SG_FOR_MM2S; -- Invalid configuration for axi dma - simply here for completeness MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate begin m_axi_sg_aresetn <= '1'; dm_m_axi_sg_aresetn <= '1'; end generate MAP_NO_SG; s2mm_scndry_resetn <= s2mm_scndry_resetn_i; mm2s_scndry_resetn <= mm2s_scndry_resetn_i; -- Generate MM2S reset signals GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate begin RESET_I : entity axi_dma_v7_1.axi_dma_reset generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ , C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_INCLUDE_SG => C_INCLUDE_SG ) port map( -- Clock Sources m_axi_sg_aclk => m_axi_sg_aclk , axi_prmry_aclk => m_axi_mm2s_aclk , -- Hard Reset axi_resetn => sg_hard_reset , -- Soft Reset soft_reset => soft_reset , soft_reset_clr => mm2s_soft_reset_clr , soft_reset_done => soft_reset_clr_i , all_idle => mm2s_all_idle , stop => mm2s_stop , halt => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , -- Secondary Reset scndry_resetn => mm2s_scndry_resetn_i , -- AXI Upsizer and Line Buffer prmry_resetn => mm2s_prmry_resetn , -- AXI DataMover Primary Reset (Raw) dm_prmry_resetn => dm_mm2s_prmry_resetn , -- AXI DataMover Secondary Reset (Raw) dm_scndry_resetn => dm_mm2s_scndry_resetn_i , -- AXI Stream Primary Reset Outputs prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Alternate Reset Outputs altrnt_reset_out_n => mm2s_cntrl_reset_out_n ); -- Sample an hold mm2s soft reset done to use in -- combined reset done to DMACR MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then mm2s_soft_reset_done <= '0'; elsif(mm2s_soft_reset_clr = '1')then mm2s_soft_reset_done <= '1'; end if; end if; end process MM2S_SOFT_RST_DONE; end generate GEN_RESET_FOR_MM2S; -- No MM2S therefore tie off mm2s reset signals GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate begin mm2s_prmry_reset_out_n <= '1'; mm2s_cntrl_reset_out_n <= '1'; dm_mm2s_scndry_resetn_i <= '1'; dm_mm2s_prmry_resetn <= '1'; mm2s_prmry_resetn <= '1'; mm2s_scndry_resetn_i <= '1'; mm2s_halt <= '0'; mm2s_soft_reset_clr <= '0'; mm2s_soft_reset_done <= '1'; end generate GEN_NO_RESET_FOR_MM2S; -- Generate S2MM reset signals GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate begin RESET_I : entity axi_dma_v7_1.axi_dma_reset generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ , C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_INCLUDE_SG => C_INCLUDE_SG ) port map( -- Clock Sources m_axi_sg_aclk => m_axi_sg_aclk , axi_prmry_aclk => m_axi_s2mm_aclk , -- Hard Reset axi_resetn => sg_hard_reset , -- Soft Reset soft_reset => soft_reset , soft_reset_clr => s2mm_soft_reset_clr , soft_reset_done => soft_reset_clr_i , all_idle => s2mm_all_idle , stop => s2mm_stop , halt => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , -- Secondary Reset scndry_resetn => s2mm_scndry_resetn_i , -- AXI Upsizer and Line Buffer prmry_resetn => s2mm_prmry_resetn , -- AXI DataMover Primary Reset (Raw) dm_prmry_resetn => dm_s2mm_prmry_resetn , -- AXI DataMover Secondary Reset (Raw) dm_scndry_resetn => dm_s2mm_scndry_resetn_i , -- AXI Stream Primary Reset Outputs prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Alternate Reset Outputs altrnt_reset_out_n => s2mm_sts_reset_out_n ); -- Sample an hold s2mm soft reset done to use in -- combined reset done to DMACR S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then s2mm_soft_reset_done <= '0'; elsif(s2mm_soft_reset_clr = '1')then s2mm_soft_reset_done <= '1'; end if; end if; end process S2MM_SOFT_RST_DONE; end generate GEN_RESET_FOR_S2MM; -- No SsMM therefore tie off mm2s reset signals GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate begin s2mm_prmry_reset_out_n <= '1'; dm_s2mm_scndry_resetn_i <= '1'; dm_s2mm_prmry_resetn <= '1'; s2mm_prmry_resetn <= '1'; s2mm_scndry_resetn_i <= '1'; s2mm_halt <= '0'; s2mm_soft_reset_clr <= '0'; s2mm_soft_reset_done <= '1'; end generate GEN_NO_RESET_FOR_S2MM; -- When both mm2s and s2mm are done then drive soft reset clear and -- also clear s_h registers above soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done; soft_reset_clr <= soft_reset_clr_i; end implementation;
bsd-2-clause
b9ed676eb264430fd90049403427b094
0.422792
4.427478
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/if_statement/rule_036_test_input.fixed.vhd
1
439
architecture RTL of FIFO is begin process begin if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; end if; -- Violations below if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; end if; if a = '1' then -- comment 1 b <= '0'; elsif c = '1' then -- comment 2 -- comment 3 -- comment 4 b <= '1'; end if; end process; end architecture RTL;
gpl-3.0
49388e6d09c97e7230f6aaaba5d53d8d
0.453303
3.158273
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_reset.vhd
1
26,929
------------------------------------------------------------------------------- -- axi_datamover_reset.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_reset.vhd -- -- Description: -- This file implements the DataMover Reset module. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_reset.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 9/1/2011 Initial -- ~~~~~~ -- - Corrected some CDC reported synchronizer issues for the async clock -- mode of the command/status user interface. -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library proc_common_v4_0; ------------------------------------------------------------------------------- entity axi_datamover_reset is generic ( C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0 -- 0 = Use Synchronous Command/Statys User Interface -- 1 = Use Asynchronous Command/Statys User Interface ); port ( -- Primary Clock and Reset Inputs ----------------- -- primary_aclk : in std_logic; -- primary_aresetn : in std_logic; -- --------------------------------------------------- -- Async operation clock and reset from User ------ -- Used for Command/Status User interface -- -- synchronization when C_STSCMD_IS_ASYNC = 1 -- -- secondary_awclk : in std_logic; -- secondary_aresetn : in std_logic; -- --------------------------------------------------- -- Halt request input control ------------------------------- halt_req : in std_logic; -- -- Active high soft shutdown request (can be a pulse) -- -- -- Halt Complete status flag -- halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Soft Shutdown internal interface ------------------------------------------------ -- flush_stop_request : Out std_logic; -- -- Active high soft stop request to modules -- -- data_cntlr_stopped : in std_logic; -- -- Active high flag indicating the data controller is flushed and stopped -- -- addr_cntlr_stopped : in std_logic; -- -- Active high flag indicating the address controller is flushed and stopped -- -- aux1_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 1 module -- -- Tie high if unused -- -- aux2_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 2 module -- -- Tie high if unused -- ------------------------------------------------------------------------------------ -- HW Reset outputs to reset groups ------------------------------------- -- cmd_stat_rst_user : Out std_logic; -- -- The reset to the Command/Status Module User interface side -- -- cmd_stat_rst_int : Out std_logic; -- -- The reset to the Command/Status Module internal interface side -- -- mmap_rst : Out std_logic; -- -- The reset to the Memory Map interface side -- -- stream_rst : Out std_logic -- -- The reset to the Stream interface side -- -------------------------------------------------------------------------- ); end entity axi_datamover_reset; architecture implementation of axi_datamover_reset is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; constant MTBF_STAGES : integer := 4; -- ATTRIBUTE async_reg : STRING; -- Signals signal sig_cmd_stat_rst_user_n : std_logic := '0'; signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0'; signal sig_cmd_stat_rst_int_reg_n : std_logic := '0'; signal sig_mmap_rst_reg_n : std_logic := '0'; signal sig_stream_rst_reg_n : std_logic := '0'; signal sig_syncd_sec_rst : std_logic := '0'; -- soft shutdown support signal sig_internal_reset : std_logic := '0'; signal sig_s_h_halt_reg : std_logic := '0'; signal sig_halt_cmplt : std_logic := '0'; -- additional CDC synchronization signals signal sig_sec_neg_edge_plus_delay : std_logic := '0'; signal sig_secondary_aresetn_reg : std_logic := '0'; signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0'; signal sig_prim2sec_rst_reg2_n : std_logic := '0'; -- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true"; begin --(architecture implementation) -- Assign outputs cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n); cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; mmap_rst <= not(sig_mmap_rst_reg_n) or sig_syncd_sec_rst; stream_rst <= not(sig_stream_rst_reg_n) or sig_syncd_sec_rst; -- Internal logic Implmentation ------------------------------------------------------------ -- If Generate -- -- Label: GEN_SYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Synchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate begin sig_syncd_sec_rst <= '0'; sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from); end generate GEN_SYNC_CMDSTAT_RESET; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ASYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Asynchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate -- ATTRIBUTE async_reg : STRING; signal sig_sec_reset_in_reg_n : std_logic := '0'; signal sig_secondary_aresetn_reg_tmp : std_logic := '0'; -- Secondary reset pulse stretcher signal sig_secondary_dly1 : std_logic := '0'; signal sig_secondary_dly2 : std_logic := '0'; signal sig_neg_edge_detect : std_logic := '0'; signal sig_sec2prim_reset : std_logic := '0'; signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0'; signal sig_sec2prim_reset_reg2 : std_logic := '0'; signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0'; signal sig_sec2prim_rst_syncro2 : std_logic := '0'; -- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true"; -- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true"; begin -- Generate the reset in the primary clock domain. Use the longer -- of the pulse stretched reset or the actual reset. sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or sig_sec2prim_rst_syncro2; -- Check for falling edge of secondary_aresetn input sig_neg_edge_detect <= '1' when (sig_sec_reset_in_reg_n = '1' and secondary_aresetn = '0') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSE_STRETCH_FLOPS -- -- Process Description: -- This process implements a 3 clock wide pulse whenever the -- secondary reset is asserted -- ------------------------------------------------------------- IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then If (sig_secondary_dly2 = '1') Then sig_secondary_dly1 <= '0' ; sig_secondary_dly2 <= '0' ; Elsif (sig_neg_edge_detect = '1') Then sig_secondary_dly1 <= '1'; else sig_secondary_dly2 <= sig_secondary_dly1 ; End if; end if; end process IMP_PUSE_STRETCH_FLOPS; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_NEG_EDGE -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- negative edge detection, -- ------------------------------------------------------------- SYNC_NEG_EDGE : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or sig_secondary_dly1 or sig_secondary_dly2; end if; end process SYNC_NEG_EDGE; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO -- -- Process Description: -- This process registers the secondary reset input to -- the primary clock domain. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_sec_neg_edge_plus_delay, prmry_vect_in => (others => '0'), scndry_aclk => primary_aclk, scndry_resetn => '0', scndry_out => sig_sec2prim_reset_reg2, scndry_vect_out => open ); -- SEC2PRIM_RST_SYNCRO : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- -- -- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ; -- -- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig; -- -- end if; -- end process SEC2PRIM_RST_SYNCRO; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SEC_RST -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- secondary reset input, -- ------------------------------------------------------------- REG_SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_secondary_aresetn_reg <= secondary_aresetn; end if; end process REG_SEC_RST; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO_2 -- -- Process Description: -- Second stage (destination) synchronizers for the secondary -- reset CDC to the primary clock. -- ------------------------------------------------------------- sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg); SEC2PRIM_RST_SYNCRO_2 : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_secondary_aresetn_reg_tmp, prmry_vect_in => (others => '0'), scndry_aclk => primary_aclk, scndry_resetn => '0', scndry_out => sig_sec2prim_rst_syncro2, scndry_vect_out => open ); -- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- -- -- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn); -- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg); -- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig; -- -- -- end if; -- end process SEC2PRIM_RST_SYNCRO_2; -- Generate the Command and Status side reset sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and sig_prim2sec_rst_reg2_n; -- CDC sig_cmd_stat_rst_user_reg_n_cdc_from; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_RESET_ASYNC -- -- Process Description: -- This process registers the secondary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_RESET_ASYNC : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_reset_in_reg_n <= secondary_aresetn; end if; end process REG_RESET_ASYNC; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_PRIM2SEC_RST -- -- Process Description: -- Second (destination clock) stage synchronizers for CDC of -- primary reset input, -- ------------------------------------------------------------- SYNC_PRIM2SEC_RST : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => secondary_awclk, scndry_resetn => '0', scndry_out => sig_prim2sec_rst_reg2_n, scndry_vect_out => open ); -- SYNC_PRIM2SEC_RST : process (secondary_awclk) -- begin -- if (secondary_awclk'event and secondary_awclk = '1') then -- -- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from; -- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to; -- -- end if; -- end process SYNC_PRIM2SEC_RST; -- end generate GEN_ASYNC_CMDSTAT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_PRIM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_PRIM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn; end if; end process REG_CMDSTAT_PRIM_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_INT_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status internal interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_INT_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_int_reg_n <= primary_aresetn; end if; end process REG_CMDSTAT_INT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_MMAP_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Memory Map interface reset. -- ------------------------------------------------------------- REG_MMAP_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_rst_reg_n <= primary_aresetn; end if; end process REG_MMAP_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_STREAM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Stream interface reset. -- ------------------------------------------------------------- REG_STREAM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_stream_rst_reg_n <= primary_aresetn; end if; end process REG_STREAM_RESET; -- Soft Shutdown logic ------------------------------------------------------ sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; flush_stop_request <= sig_s_h_halt_reg; halt_cmplt <= sig_halt_cmplt; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_HALT_REQ -- -- Process Description: -- Implements a sample and hold flop for the halt request -- input. Can only be cleared on a HW reset. -- ------------------------------------------------------------- REG_HALT_REQ : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_s_h_halt_reg <= '0'; elsif (halt_req = '1') then sig_s_h_halt_reg <= '1'; else null; -- hold current state end if; end if; end process REG_HALT_REQ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT -- -- Process Description: -- Implements a the flop for the halt complete status -- output. Can only be cleared on a HW reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_halt_cmplt <= '0'; elsif (data_cntlr_stopped = '1' and addr_cntlr_stopped = '1' and aux1_stopped = '1' and aux2_stopped = '1') then sig_halt_cmplt <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT; end implementation;
bsd-2-clause
7250a9906fc4c0f4ec926e6d4e66005c
0.414683
5.134223
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd
1
39,626
-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_q_mngr.vhd -- Description: This entity is the descriptor update queue manager -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library proc_common_v4_0; use proc_common_v4_0.sync_fifo_fg; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_q_mngr is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- --***********************************-- -- --** Channel 1 Control **-- -- --***********************************-- -- ch1_updt_curdesc_wren : out std_logic ; -- ch1_updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_updt_active : in std_logic ; -- ch1_updt_queue_empty : out std_logic ; -- ch1_updt_ioc : out std_logic ; -- ch1_updt_ioc_irq_set : in std_logic ; -- -- ch1_dma_interr : out std_logic ; -- ch1_dma_slverr : out std_logic ; -- ch1_dma_decerr : out std_logic ; -- ch1_dma_interr_set : in std_logic ; -- ch1_dma_slverr_set : in std_logic ; -- ch1_dma_decerr_set : in std_logic ; -- -- --***********************************-- -- --** Channel 2 Control **-- -- --***********************************-- -- ch2_updt_active : in std_logic ; -- -- ch2_updt_curdesc_wren : out std_logic ; -- -- ch2_updt_curdesc : out std_logic_vector -- -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_updt_queue_empty : out std_logic ; -- ch2_updt_ioc : out std_logic ; -- ch2_updt_ioc_irq_set : in std_logic ; -- -- ch2_dma_interr : out std_logic ; -- ch2_dma_slverr : out std_logic ; -- ch2_dma_decerr : out std_logic ; -- ch2_dma_interr_set : in std_logic ; -- ch2_dma_slverr_set : in std_logic ; -- ch2_dma_decerr_set : in std_logic ; -- -- --***********************************-- -- --** Channel 1 Update Interface In **-- -- --***********************************-- -- s_axis_ch1_updt_aclk : in std_logic ; -- -- Update Pointer Stream -- s_axis_ch1_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_ch1_updtptr_tvalid : in std_logic ; -- s_axis_ch1_updtptr_tready : out std_logic ; -- s_axis_ch1_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_ch1_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_ch1_updtsts_tvalid : in std_logic ; -- s_axis_ch1_updtsts_tready : out std_logic ; -- s_axis_ch1_updtsts_tlast : in std_logic ; -- -- --***********************************-- -- --** Channel 2 Update Interface In **-- -- --***********************************-- -- s_axis_ch2_updt_aclk : in std_logic ; -- -- Update Pointer Stream -- s_axis_ch2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_ch2_updtptr_tvalid : in std_logic ; -- s_axis_ch2_updtptr_tready : out std_logic ; -- s_axis_ch2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_ch2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_ch2_updtsts_tvalid : in std_logic ; -- s_axis_ch2_updtsts_tready : out std_logic ; -- s_axis_ch2_updtsts_tlast : in std_logic ; -- -- --***************************************-- -- --** Update Interface to AXI DataMover **-- -- --***************************************-- -- -- S2MM Stream Out To DataMover -- s_axis_s2mm_tdata : out std_logic_vector -- (C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_tlast : out std_logic ; -- s_axis_s2mm_tvalid : out std_logic ; -- s_axis_s2mm_tready : in std_logic -- ); end axi_sg_updt_q_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_q_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch1_updt_tlast : std_logic := '0'; signal m_axis_ch1_updt_tvalid : std_logic := '0'; signal m_axis_ch1_updt_tready : std_logic := '0'; signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch2_updt_tlast : std_logic := '0'; signal m_axis_ch2_updt_tvalid : std_logic := '0'; signal m_axis_ch2_updt_tready : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin --***************************************************************************** --** CHANNEL 1 ** --***************************************************************************** ------------------------------------------------------------------------------- -- If Channel 1 is enabled then instantiate descriptor update logic. ------------------------------------------------------------------------------- -- If Descriptor Update queueing enabled then instantiate Queue Logic GEN_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate begin ------------------------------------------------------------------------------- I_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE , C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE , C_SG2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE , C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_INCLUDE_MM2S => C_INCLUDE_CH1 , C_INCLUDE_S2MM => C_INCLUDE_CH2 , C_FAMILY => C_FAMILY ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , s_axis_updt_aclk => s_axis_ch1_updt_aclk , --********************************-- --** Control and Status **-- --********************************-- updt_curdesc_wren => ch1_updt_curdesc_wren , updt_curdesc => ch1_updt_curdesc , updt_active => ch1_updt_active , updt_queue_empty => ch1_updt_queue_empty , updt_ioc => ch1_updt_ioc , updt_ioc_irq_set => ch1_updt_ioc_irq_set , dma_interr => ch1_dma_interr , dma_slverr => ch1_dma_slverr , dma_decerr => ch1_dma_decerr , dma_interr_set => ch1_dma_interr_set , dma_slverr_set => ch1_dma_slverr_set , dma_decerr_set => ch1_dma_decerr_set , -- updt2_curdesc_wren => ch2_updt_curdesc_wren , -- updt2_curdesc => ch2_updt_curdesc , updt2_active => ch2_updt_active , updt2_queue_empty => ch2_updt_queue_empty , updt2_ioc => ch2_updt_ioc , updt2_ioc_irq_set => ch2_updt_ioc_irq_set , dma2_interr => ch2_dma_interr , dma2_slverr => ch2_dma_slverr , dma2_decerr => ch2_dma_decerr , dma2_interr_set => ch2_dma_interr_set , dma2_slverr_set => ch2_dma_slverr_set , dma2_decerr_set => ch2_dma_decerr_set , --********************************-- --** Update Interfaces In **-- --********************************-- -- Update Pointer Stream s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata , s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid , s_axis_updtptr_tready => s_axis_ch1_updtptr_tready , s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast , -- Update Status Stream s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata , s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid , s_axis_updtsts_tready => s_axis_ch1_updtsts_tready , s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast , -- Update Pointer Stream s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata , s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready , s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- Update Status Stream s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata , s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready , s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast , --********************************-- --** Update Interfaces Out **-- --********************************-- -- S2MM Stream Out To DataMover m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata , m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast , m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid , m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready , -- m_axis2_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis2_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis2_updt_tready => m_axis_ch2_updt_tready ); end generate GEN_QUEUE; --***************************************************************************** --** CHANNEL 1 - NO DESCRIPTOR QUEUE ** --***************************************************************************** -- No update queue enabled, therefore map internal stream logic -- directly to channel port. GEN_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate begin I_NO_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , --********************************-- --** Control and Status **-- --********************************-- updt_curdesc_wren => ch1_updt_curdesc_wren , updt_curdesc => ch1_updt_curdesc , updt_active => ch1_updt_active , updt_queue_empty => ch1_updt_queue_empty , updt_ioc => ch1_updt_ioc , updt_ioc_irq_set => ch1_updt_ioc_irq_set , dma_interr => ch1_dma_interr , dma_slverr => ch1_dma_slverr , dma_decerr => ch1_dma_decerr , dma_interr_set => ch1_dma_interr_set , dma_slverr_set => ch1_dma_slverr_set , dma_decerr_set => ch1_dma_decerr_set , updt2_active => ch2_updt_active , updt2_queue_empty => ch2_updt_queue_empty , updt2_ioc => ch2_updt_ioc , updt2_ioc_irq_set => ch2_updt_ioc_irq_set , dma2_interr => ch2_dma_interr , dma2_slverr => ch2_dma_slverr , dma2_decerr => ch2_dma_decerr , dma2_interr_set => ch2_dma_interr_set , dma2_slverr_set => ch2_dma_slverr_set , dma2_decerr_set => ch2_dma_decerr_set , --********************************-- --** Update Interfaces In **-- --********************************-- -- Update Pointer Stream s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata , s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid , s_axis_updtptr_tready => s_axis_ch1_updtptr_tready , s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast , -- Update Status Stream s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata , s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid , s_axis_updtsts_tready => s_axis_ch1_updtsts_tready , s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast , -- Update Pointer Stream s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata , s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready , s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- Update Status Stream s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata , s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready , s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast , --********************************-- --** Update Interfaces Out **-- --********************************-- -- S2MM Stream Out To DataMover m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata , m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast , m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid , m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready , -- m_axis_updt_tdata => m_axis_ch1_updt_tdata , -- m_axis_updt_tlast => m_axis_ch1_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch1_updt_tvalid , -- m_axis_updt_tready => m_axis_ch1_updt_tready , -- S2MM Stream Out To DataMover -- m_axis2_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis2_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis2_updt_tready => m_axis_ch2_updt_tready ); end generate GEN_NO_QUEUE; -- Channel 1 NOT included therefore tie ch1 outputs off --GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate --begin -- ch1_updt_curdesc_wren <= '0'; -- ch1_updt_curdesc <= (others => '0'); -- ch1_updt_queue_empty <= '1'; -- ch1_updt_ioc <= '0'; -- ch1_dma_interr <= '0'; -- ch1_dma_slverr <= '0'; -- ch1_dma_decerr <= '0'; -- m_axis_ch1_updt_tdata <= (others => '0'); -- m_axis_ch1_updt_tlast <= '0'; -- m_axis_ch1_updt_tvalid <= '0'; -- s_axis_ch1_updtptr_tready <= '0'; -- s_axis_ch1_updtsts_tready <= '0'; --end generate GEN_NO_CH1_UPDATE_Q_IF; --***************************************************************************** --** CHANNEL 2 ** --***************************************************************************** ------------------------------------------------------------------------------- -- If Channel 2 is enabled then instantiate descriptor update logic. ------------------------------------------------------------------------------- --GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate -- --begin -- -- --************************************************************************* -- --** CHANNEL 2 - DESCRIPTOR QUEUE ** -- --************************************************************************* -- -- If Descriptor Update queueing enabled then instantiate Queue Logic -- GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate -- begin -- --------------------------------------------------------------------------- -- I_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue -- generic map( -- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , -- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , -- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , -- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , -- C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE , -- C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE , -- C_FAMILY => C_FAMILY -- ) -- port map( -- --------------------------------------------------------------- -- -- AXI Scatter Gather Interface -- --------------------------------------------------------------- -- m_axi_sg_aclk => m_axi_sg_aclk , -- m_axi_sg_aresetn => m_axi_sg_aresetn , -- s_axis_updt_aclk => s_axis_ch2_updt_aclk , -- -- --********************************-- -- --** Control and Status **-- -- --********************************-- -- updt_curdesc_wren => ch2_updt_curdesc_wren , -- updt_curdesc => ch2_updt_curdesc , -- updt_active => ch2_updt_active , -- updt_queue_empty => ch2_updt_queue_empty , -- updt_ioc => ch2_updt_ioc , -- updt_ioc_irq_set => ch2_updt_ioc_irq_set , -- -- dma_interr => ch2_dma_interr , -- dma_slverr => ch2_dma_slverr , -- dma_decerr => ch2_dma_decerr , -- dma_interr_set => ch2_dma_interr_set , -- dma_slverr_set => ch2_dma_slverr_set , -- dma_decerr_set => ch2_dma_decerr_set , -- -- --********************************-- -- --** Update Interfaces In **-- -- --********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata , -- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , -- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready , -- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- -- -- Update Status Stream -- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata , -- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , -- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready , -- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast , -- -- --********************************-- -- --** Update Interfaces Out **-- -- --********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis_updt_tready => m_axis_ch2_updt_tready -- ); -- -- end generate GEN_CH2_QUEUE; -- -- -- --***************************************************************************** -- --** CHANNEL 2 - NO DESCRIPTOR QUEUE ** -- --***************************************************************************** -- -- -- No update queue enabled, therefore map internal stream logic -- -- directly to channel port. -- GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate -- I_NO_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue -- generic map( -- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , -- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , -- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , -- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH -- ) -- port map( -- --------------------------------------------------------------- -- -- AXI Scatter Gather Interface -- --------------------------------------------------------------- -- m_axi_sg_aclk => m_axi_sg_aclk , -- m_axi_sg_aresetn => m_axi_sg_aresetn , -- -- --********************************-- -- --** Control and Status **-- -- --********************************-- -- updt_curdesc_wren => ch2_updt_curdesc_wren , -- updt_curdesc => ch2_updt_curdesc , -- updt_active => ch2_updt_active , -- updt_queue_empty => ch2_updt_queue_empty , -- updt_ioc => ch2_updt_ioc , -- updt_ioc_irq_set => ch2_updt_ioc_irq_set , -- -- dma_interr => ch2_dma_interr , -- dma_slverr => ch2_dma_slverr , -- dma_decerr => ch2_dma_decerr , -- dma_interr_set => ch2_dma_interr_set , -- dma_slverr_set => ch2_dma_slverr_set , -- dma_decerr_set => ch2_dma_decerr_set , -- -- --********************************-- -- --** Update Interfaces In **-- -- --********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata , -- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , -- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready , -- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- -- -- Update Status Stream -- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata , -- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , -- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready , -- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast , -- -- --********************************-- -- --** Update Interfaces Out **-- -- --********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis_updt_tready => m_axis_ch2_updt_tready -- ); -- -- end generate GEN_CH2_NO_QUEUE; -- --end generate GEN_CH2_UPDATE_Q_IF; -- ---- Channel 2 NOT included therefore tie ch2 outputs off --GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate --begin -- ch2_updt_curdesc_wren <= '0'; -- ch2_updt_curdesc <= (others => '0'); -- ch2_updt_queue_empty <= '1'; -- -- ch2_updt_ioc <= '0'; -- ch2_dma_interr <= '0'; -- ch2_dma_slverr <= '0'; -- ch2_dma_decerr <= '0'; -- -- m_axis_ch2_updt_tdata <= (others => '0'); -- m_axis_ch2_updt_tlast <= '0'; -- m_axis_ch2_updt_tvalid <= '0'; -- -- s_axis_ch2_updtptr_tready <= '0'; -- s_axis_ch2_updtsts_tready <= '0'; -- --end generate GEN_NO_CH2_UPDATE_Q_IF; ------------------------------------------------------------------------------- -- MUX For DataMover ------------------------------------------------------------------------------- --TO_DATAMVR_MUX : process(ch1_updt_active, -- ch2_updt_active, -- m_axis_ch1_updt_tdata, -- m_axis_ch1_updt_tlast, -- m_axis_ch1_updt_tvalid, -- m_axis_ch2_updt_tdata, -- m_axis_ch2_updt_tlast, -- m_axis_ch2_updt_tvalid) -- begin -- if(ch1_updt_active = '1')then -- s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata; -- s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast; -- s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid; -- elsif(ch2_updt_active = '1')then -- s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata; -- s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast; -- s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid; -- else -- s_axis_s2mm_tdata <= (others => '0'); -- s_axis_s2mm_tlast <= '0'; -- s_axis_s2mm_tvalid <= '0'; -- end if; -- end process TO_DATAMVR_MUX; -- --m_axis_ch1_updt_tready <= s_axis_s2mm_tready; --m_axis_ch2_updt_tready <= s_axis_s2mm_tready; -- end implementation;
bsd-2-clause
6de61cff3e4de3844cf2b22b0581d6e3
0.352773
4.665725
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/constant/rule_007_test_input.vhd
1
859
architecture RTL of FIFO is constant c_width : integer; constant c_width : integer := 16; constant c_depth : integer := 512; constant AVMM_MASTER_NULL : avmm_master_t := ( (others => '0'), (others => '0'), '0', '0' ); --! Test stimulus CONSTANT c_stimulus : t_stimulus_array := ( ( name => "Hold in reset ", clk_in => "0101010101010101", rst_in => "1111111111111111", cnt_en_in => "0000000000000000", cnt_out => "0000000000000000" ), ( name => "Not enabled ", clk_in => "0101010101010101", rst_in => "0000000000000000", cnt_en_in => "0000000000000000", cnt_out => "0000000000000000" ) ); begin end architecture RTL;
gpl-3.0
5300283d9399fd8edd7000498021c84d
0.476135
4.149758
false
false
false
false
cwilkens/ecen4024-microphone-array
microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/polyphase_interpolation.vhd
2
648,655
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block k6+1ZDBPxx3J0vctj2PgcZsLNz2XGdfowg51JgXnb+MH9GZFXI/D3a9c7Va0vHzfzeKU3mVpW7Ut jLCf2XzWFQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block iTC31J0RUr0ytsxM/NPrBRviRpQ0je4h2YYt0WzW//Aweb3fhHpw2qrXAdWfnHVBLaN0Kdw3mt0W laVQdwix8hhzQlXo26Je0dfpRBp6a8EZhV2PXP1iDolToUm4iQbR5uY0kSC7whx+P50KI6Td83CH 7Vm5ud0+tetNdkpN5zU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit
f92061c14c26f9525a0829d51119cfb7
0.955662
1.806023
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/ieee/rule_500_test_input.fixed_lower.vhd
1
2,637
entity FIFO is generic ( G_GEN1 : std_logic, G_GEN2 : std_logic_vector(3 downto 0), G_GEN3 : integer, G_GEN4 : signed(15 downto 0), G_GEN5 : unsigned(7 downto 0) ); port ( I_PORT1 : in integer; I_PORT2 : in std_logic; I_PORTA : in t_user2; I_PORT3 : in std_logic_vector(3 downto 0); I_PORT4 : in signed(15 downto 0); I_PORT5 : in unsigned(7 downto 0); I_PORT6 : in std_ulogic; I_PORT7 : in t_user1 ); end entity FIFO; architecture rtl of fifo is signal my_sig : std_logic; constant my_con : std_logic_vector(3 downto 0); procedure my_proc ( init : in std_logic ) is variable my_sig : std_logic; constant my_con : std_logic_vector(3 downto 0); begin end procedure; component MY_COMP is generic ( G_GEN1 : std_logic, G_GEN2 : std_logic_vector(3 downto 0), G_GEN3 : integer, G_GEN4 : signed(15 downto 0), G_GEN5 : unsigned(7 downto 0) ); port ( I_PORT1 : in integer; I_PORT2 : in std_logic; I_PORTA : in t_user2; I_PORT3 : in std_logic_vector(3 downto 0); I_PORT4 : in signed(15 downto 0); I_PORT5 : in unsigned(7 downto 0); I_PORT6 : in std_ulogic; I_PORT7 : in t_user1 ); end component; begin end architecture rtl; --====== UPPERCASE before entity FIFO is generic ( G_GEN1 : std_logic, G_GEN2 : std_logic_vector(3 downto 0), G_GEN3 : integer, G_GEN4 : signed(15 downto 0), G_GEN5 : unsigned(7 downto 0) ); port ( I_PORT1 : in integer; I_PORT2 : in std_logic; I_PORTA : in t_user2; I_PORT3 : in std_logic_vector(3 downto 0); I_PORT4 : in signed(15 downto 0); I_PORT5 : in unsigned(7 downto 0); I_PORT6 : in std_ulogic; I_PORT7 : in t_user1 ); end entity FIFO; architecture rtl of fifo is signal my_sig : std_logic; constant my_con : std_logic_vector(3 downto 0); procedure my_proc ( init : in std_logic ) is variable my_sig : std_logic; constant my_con : std_logic_vector(3 downto 0); begin end procedure; component MY_COMP is generic ( G_GEN1 : std_logic, G_GEN2 : std_logic_vector(3 downto 0), G_GEN3 : integer, G_GEN4 : signed(15 downto 0), G_GEN5 : unsigned(7 downto 0) ); port ( I_PORT1 : in integer; I_PORT2 : in std_logic; I_PORTA : in t_user2; I_PORT3 : in std_logic_vector(3 downto 0); I_PORT4 : in signed(15 downto 0); I_PORT5 : in unsigned(7 downto 0); I_PORT6 : in std_ulogic; I_PORT7 : in t_user1 ); end component; begin end architecture rtl;
gpl-3.0
bc660dd9448bce3e177288500f0c1cc5
0.591202
2.979661
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/wr_pf_as.vhd
2
27,402
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block myg3RLudVQQ8pRHwqQt3BcEuqSX3U7Za+3AnmBvgKmwL/BRRwduhIj95YFwtJrAwJ0/ftASUzXQ7 3iA5sYfR8g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cVzTdts+/oQXywMAF1sMZ+Q6IrQ4zZPqGdEeishTTmNygjVIFG04efvIN4CxmmxrD4BgX7gJAvoX gh8juMicyHff8+7FXqIRd8jrFxsSld9l1QP2wDdCiBRF74TM0vh43nx+OqMfdyKrY5LRE2fafr8l xrMVCCbudTTCo/AaXpU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block WJg4g6Kf6i0tysLRwU80l2BcskWf11X8bDR/n6SPon97bbrNGJbxPDfPYWfEAAd4keNXa2tN0OBf XFKVDxWSME5qSizjgG28X62J3FjyrbxN50bhZzoVRDK5W5IOX7Yt4rYvVuOwn3BzOzis7+G/uIRG gDYn0LWZYB/p0J/7ZKYPk11GNJGmhZ/e+/I9pYmMWD0HLMii8R0ac47Hhw8N1ZL12zkbC9wAAbBk mdCz7VRM/o/TQR1K4/HyGBk32LPQP82CXjx2zOrdnUPhKrA0EJcHua470MXWdwPh2kQ1gMp58gHV 0KIq782tMSJy10+An0oVvUgrO+AEDUOZoSAdeg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jtk9Ak4nMh21Cj8KpLU+a35/DIolw9RAtd07tEEBHh4zSssdYtBDc4VH6U3rMQTBRBG+XgvNGEtG DH+e6zhywPFMX/4ibftpuokiSuTZ3D4/MLQA91qPWpgCIdWzJYurkT2KieQ0AMAYWLFrmsQW/gjA bLLZiKi6czn3Visqj9E= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block h10Oh7l10t2fVp0Wk8ec0fx1Jy/FC1bBFNvCWmeoOvh8E5IZKuKvA0kRO3zaICJliPWTSVWcqby5 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bsd-2-clause
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siavooshpayandehazad/TTU_CPU_Project
pico_CPU_pipelined_MIPS32/Controller.vhd
1
34,210
--Copyright (C) 2017 Siavoosh Payandeh Azad library IEEE; use IEEE.std_logic_1164.all; USE IEEE.std_logic_unsigned.ALL; USE IEEE.NUMERIC_STD.ALL; use work.pico_cpu.all; -- There are 4 stages of pipeline: -- * Fetch: we read the instruction from memory, since the memory will respond in 1 -- clock cycle, we need to pass the input of the PC register to be on time! -- * Decode/REGFILE: here we extract the registers used by the instructions -- * Execute: we execute ALU operations here -- * WB: we write into the REGFILE, in cases that we read from Memory and want to write into REGFILE, -- since the ALU generates the address, We will write into the REGFILE during WB but the value -- be inside the register in the next clock cycle, however, the REGFILE has a bypass mechanism -- that can push this value to output as soon as it gets it! ----------------------------------- -- Regarding the jumps, we assume that the compiler always executes 1 instruction -- after the jump! entity ControlUnit is generic (BitWidth: integer; InstructionWidth: integer); port( rst : in std_logic; clk : in std_logic; ---------------------------------------- Instr_In : in std_logic_vector (InstructionWidth-1 downto 0); Instr_Add : out std_logic_vector (BitWidth-1 downto 0); ---------------------------------------- MemRdAddress : out std_logic_vector (BitWidth-1 downto 0); MemWrtAddress : out std_logic_vector (BitWidth-1 downto 0); Mem_RW : out std_logic_vector (3 downto 0); MEM_IN_SEL : out MEM_IN_MUX; ---------------------------------------- IO_DIR : out std_logic; IO_RD : in std_logic_vector (BitWidth-1 downto 0); IO_WR : out std_logic_vector (BitWidth-1 downto 0); ---------------------------------------- DPU_OV : in std_logic; DataToDPU_2 : out std_logic_vector (BitWidth-1 downto 0); DPU_ALUCommand : out ALU_COMMAND; DPU_Mux_Cont_2 : out DPU_IN_MUX; ---------------------------------------- RFILE_data_sel : out RFILE_IN_MUX; RFILE_in_address: out std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); RFILE_WB_enable : out std_logic_vector (3 downto 0); RFILE_out_sel_1 : out std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); RFILE_out_sel_2 : out std_logic_vector (RFILE_SEL_WIDTH-1 downto 0); Data_to_RFILE : out std_logic_vector (BitWidth-1 downto 0); ---------------------------------------- DPU_RESULT : in std_logic_vector (2*BitWidth-1 downto 0); Result_ACC : in std_logic_vector (2*BitWidth-1 downto 0) ); end ControlUnit; architecture RTL of ControlUnit is --------------------------------------------- -- Signals and Types --------------------------------------------- signal Instr_F, Instr_D, Instr_E, Instr_WB :Instruction := NOP; signal PC_in, PC_out : std_logic_vector (BitWidth-1 downto 0):= (others => '0'); signal PC_jmp_in, PC_jmp_out : std_logic_vector (BitWidth-1 downto 0):= (others => '0'); signal InstrReg_out_D, InstrReg_out_E, InstrReg_out_WB: std_logic_vector (InstructionWidth-1 downto 0) := (others => '0'); signal arithmetic_operation : std_logic; signal IO_WR_in, IO_WR_in_FF : std_logic_vector(BitWidth-1 downto 0); signal IO_DIR_in, IO_DIR_FF :std_logic; signal address_error : std_logic; signal Illigal_opcode : std_logic; signal flush_F,flush_F2, flush_D : std_logic; signal trap : std_logic; type RFILE_type is array (0 to 31) of std_logic_vector(BitWidth-1 downto 0) ; signal cp0_control, cp0_control_in : RFILE_type := ((others=> (others=>'0'))); signal LOW_FF : std_logic_vector (BitWidth-1 downto 0); --------------------------------------------- -- Aliases --------------------------------------------- alias LOW : std_logic_vector is DPU_RESULT(31 downto 0); alias HIGH : std_logic_vector is DPU_RESULT(63 downto 32); alias SPECIAL_F : std_logic_vector (5 downto 0) is Instr_In (31 downto 26); alias opcode_F : std_logic_vector (5 downto 0) is Instr_In (5 downto 0); alias MF : std_logic_vector (4 downto 0) is Instr_In (25 downto 21); alias BRANCH_FIELD: std_logic_vector (4 downto 0) is Instr_In (20 downto 16); alias rs_wb : std_logic_vector (4 downto 0) is InstrReg_out_WB (25 downto 21); alias rt_wb : std_logic_vector (4 downto 0) is InstrReg_out_WB (20 downto 16); alias rd_wb : std_logic_vector (4 downto 0) is InstrReg_out_WB (15 downto 11); alias rs_ex : std_logic_vector (4 downto 0) is InstrReg_out_E (25 downto 21); alias rt_ex : std_logic_vector (4 downto 0) is InstrReg_out_E (20 downto 16); alias rd_ex : std_logic_vector (4 downto 0) is InstrReg_out_E (15 downto 11); alias sa_ex : std_logic_vector (4 downto 0) is InstrReg_out_E (10 downto 6); alias rs_d : std_logic_vector (4 downto 0) is InstrReg_out_D (25 downto 21); alias rt_d : std_logic_vector (4 downto 0) is InstrReg_out_D (20 downto 16); alias rd_d : std_logic_vector (4 downto 0) is InstrReg_out_D (15 downto 11); alias INST_INDEX_EX : std_logic_vector (25 downto 0) is InstrReg_out_E (25 downto 0); alias IMMEDIATE_EX : std_logic_vector (15 downto 0) is InstrReg_out_E (15 downto 0); alias OFFSET_EX : std_logic_vector (15 downto 0) is InstrReg_out_E (15 downto 0); alias BASE_D : std_logic_vector (4 downto 0) is InstrReg_out_D (25 downto 21); alias SR : std_logic_vector (BitWidth-1 downto 0) is cp0_control(12); alias Cause : std_logic_vector (BitWidth-1 downto 0) is cp0_control(13); alias EPC : std_logic_vector (BitWidth-1 downto 0) is cp0_control(14); begin --------------------------------------------- -- Clock Process --------------------------------------------- CLOCK_PROC:process (clk,rst) begin if rst = '1' then PC_out <= ZERO32-4; InstrReg_out_D <= (others=> '0'); InstrReg_out_E <= (others=> '0'); InstrReg_out_WB <= (others=> '0'); Instr_D <= NOP; Instr_E <= NOP; Instr_WB <= NOP; IO_WR_in_FF <= (others=> '0'); IO_DIR_FF <= '0'; cp0_control <= ((others=> (others=>'0'))); PC_jmp_out <= (others=> '0'); LOW_FF <= (others=> '0'); elsif clk'event and clk='1' then IO_WR_in_FF <= IO_WR_in; IO_DIR_FF <= IO_DIR_in; PC_out <= PC_in; InstrReg_out_D <= Instr_In; InstrReg_out_E <= InstrReg_out_D; InstrReg_out_WB <= InstrReg_out_E; Instr_D <= Instr_F; Instr_E <= Instr_D; if flush_F = '1' or flush_F2 = '1' then Instr_D <= NOP; InstrReg_out_D <= (others => '0'); end if; if flush_D = '1' then Instr_E <= NOP; InstrReg_out_E <= (others => '0'); end if; Instr_WB <= Instr_E; cp0_control <= cp0_control_in; PC_jmp_out <= PC_jmp_in; LOW_FF <= LOW; end if; end process; -- PC_in is used since we are using the same RAM for Instruction as well! (it returns the data after 1 clk) Instr_Add <= PC_in; -------------------------------------------------------------------------------- --GPIO STUFF -------------------------------------------------------------------------------- -- TODO: we need to map the IO-regs somewhere! IO_DIR <= IO_DIR_FF; IO_WR <= IO_WR_in_FF; -------------------------------------------------------------------------------- --Exception handling -------------------------------------------------------------------------------- EXCEPTION_HANDLING: process(DPU_OV, PC_out, cp0_control, Instr_E, Illigal_opcode)begin flush_F <= '0'; flush_D <= '0'; cp0_control_in(12) <= cp0_control(12); --SR cp0_control_in(13) <= cp0_control(13); --Cause cp0_control_in(14) <= cp0_control(14); --EPC if Illigal_opcode = '1' then cp0_control_in(14) <= PC_out; --EPC <= PC cp0_control_in(13)(1 downto 0) <="01"; --cause register cp0_control_in(12) <= std_logic_vector(shift_left(unsigned(cp0_control(12)), 4)); flush_F <= '1'; -- we flush the Fetch end if; if DPU_OV = '1' and (Instr_E = ADD or Instr_E = ADDI or Instr_E = SUB)then cp0_control_in(14) <= PC_out; --EPC <= PC cp0_control_in(13)(1 downto 0) <="10"; --cause register cp0_control_in(12) <= std_logic_vector(shift_left(unsigned(cp0_control(12)), 4)); flush_F <= '1'; -- we flush the Fetch flush_D <= '1'; -- here we flush the decode stage (it will be replaced with ) end if; if Instr_E = SYSCALL then cp0_control_in(14) <= PC_out; --EPC <= PC cp0_control_in(13)(1 downto 0) <="11"; --cause register cp0_control_in(12) <= std_logic_vector(shift_left(unsigned(cp0_control(12)), 4)); --status_reg flush_F <= '1'; -- we flush the Fetch flush_D <= '1'; -- here we flush the decode stage (it will be replaced with ) end if; if Instr_E = ERET then cp0_control_in(12) <= std_logic_vector(shift_right(unsigned(cp0_control(12)), 4)); --status_reg end if; if Instr_E = MTC0 then cp0_control_in(to_integer(unsigned(rd_wb))) <= LOW; end if; end process; -------------------------------------------------------------------------------- --Instruction Decoding -------------------------------------------------------------------------------- DEC_SIGNALS_GEN: process(Instr_D, rs_ex, rt_ex) begin RFILE_out_sel_1 <= (others => '0'); RFILE_out_sel_2 <= (others => '0'); -----------------------Arithmetic------------------------------------------- if Instr_D = ADD or Instr_D = ADDU or Instr_D = SUB or Instr_D = SUBU then RFILE_out_sel_1 <= rs_d; RFILE_out_sel_2 <= rt_d; elsif Instr_D = ADDI or Instr_D = ADDIU or Instr_D = CLO or Instr_D = CLZ then RFILE_out_sel_1 <= rs_d; RFILE_out_sel_2 <= rs_d; -----------------------LOGICAL--------------------------------------------- elsif Instr_D = AND_inst or Instr_D = OR_inst or Instr_D = NOR_inst or Instr_D = XOR_inst then RFILE_out_sel_1 <= rt_d; RFILE_out_sel_2 <= rs_d; elsif Instr_D = ANDI or Instr_D = ORI or Instr_D = XORI then RFILE_out_sel_1 <= rs_d; RFILE_out_sel_2 <= rs_d; -----------------------SHIFT AND ROTATE------------------------------------- elsif Instr_D = SLL_inst or Instr_D = SRL_inst or Instr_D = SRA_inst then RFILE_out_sel_1 <= rt_d; RFILE_out_sel_2 <= rt_d; elsif Instr_D = SLLV or Instr_D = SRLV or Instr_D = SRAV then RFILE_out_sel_1 <= rt_d; RFILE_out_sel_2 <= rs_d; -----------------------JUMP and BRANCH-------------------------------------- elsif Instr_D = J or Instr_D = JAL or Instr_D = JALR or Instr_D = JR or Instr_D = BEQ or Instr_D = BNE or Instr_D = BGEZ or Instr_D = BGEZAL or Instr_D = BLEZ or Instr_D = BGTZ or Instr_D = BLTZ or Instr_D = BLTZAL then if Instr_D = JALR or Instr_D = JR or Instr_D = BGEZ or Instr_D = BGEZAL or Instr_D = BGTZ then RFILE_out_sel_1 <= rs_d; RFILE_out_sel_2 <= rs_d; elsif Instr_D = BEQ or Instr_D = BNE then RFILE_out_sel_1 <= rt_d; RFILE_out_sel_2 <= rs_d; elsif Instr_D = BLEZ or Instr_D = BLTZ or Instr_D = BLTZAL then RFILE_out_sel_1 <= "00000"; -- we use R0 here! RFILE_out_sel_2 <= rs_d; end if; -----------------------MULTIPLICATION AND DIVISION-------------------------- elsif Instr_D = MULTU or Instr_D = MULT or Instr_D = MUL or Instr_D = DIV or Instr_D = DIVU or Instr_D = MADD or Instr_D = MADDU or Instr_D = MSUB or Instr_D = MSUBU then RFILE_out_sel_1 <= rt_d; RFILE_out_sel_2 <= rs_d; ----------------------ACCUMULATOR ACCESS ----------------------------------- elsif Instr_D = MTHI or Instr_D = MTLO then RFILE_out_sel_1 <= rs_d; RFILE_out_sel_2 <= rs_d; ----------------------LOAD AND STORE --------------------------------------- elsif Instr_D = LB or Instr_D = LBU or Instr_D = LH or Instr_D = LHU or Instr_D = LW or Instr_D = LWL or Instr_D = LWR then RFILE_out_sel_1 <= BASE_D; RFILE_out_sel_2 <= BASE_D; elsif Instr_D = SB or Instr_D = SH or Instr_D = SW or Instr_D = SWL or Instr_D = SWR then RFILE_out_sel_1 <= BASE_D; RFILE_out_sel_2 <= rt_d; ----------------------conditional move ----------------------------------- elsif Instr_D = SLT or Instr_D = SLTU then RFILE_out_sel_1 <= rt_d; RFILE_out_sel_2 <= rs_d; elsif Instr_D = MOVN or Instr_D = MOVZ then RFILE_out_sel_1 <= rt_d; RFILE_out_sel_2 <= "00000"; -- we use R0 here! elsif Instr_D = SLTI or Instr_D = SLTIU then RFILE_out_sel_1 <= rs_d; RFILE_out_sel_2 <= rs_d; ------------------------CO-PROCESSOR 0-------------------------------------- elsif Instr_D = MTC0 then RFILE_out_sel_1 <= rt_d; RFILE_out_sel_2 <= rt_d; -----------------------SYSCALL AND TRAPS------------------------------------ elsif Instr_D = SYSCALL then RFILE_out_sel_1 <= "00010"; RFILE_out_sel_2 <= "00010"; elsif Instr_D = TEQ or Instr_D = TGE or Instr_D = TGEU then RFILE_out_sel_1 <= rs_d; RFILE_out_sel_2 <= rt_d; elsif Instr_D = TGEI or Instr_D = TGEIU or Instr_D = TEQI then RFILE_out_sel_1 <= rs_d; RFILE_out_sel_2 <= rs_d; end if; end process; -------------------------------------------------------------------------------- --Execution -------------------------------------------------------------------------------- EX_SIGNALS_GEN:process(Instr_E, IMMEDIATE_EX, DPU_RESULT) begin -- DO NOT CHANGE THE DEFAULT VALUES! trap <= '0'; address_error <= '0'; MemWrtAddress <= (others => '0'); MemRdAddress <= (others => '0'); Mem_RW <= "0000"; DataToDPU_2 <= (others => '0'); DPU_ALUCommand <= ALU_PASS_A; DPU_Mux_Cont_2 <= RFILE; -----------------------Arithmetic------------------------------------------- if Instr_E = ADD then DPU_ALUCommand <= ALU_ADD; elsif Instr_E = ADDU then DPU_ALUCommand <= ALU_ADDU; elsif Instr_E = SUBU then DPU_ALUCommand <= ALU_SUBU; elsif Instr_E = SUB then DPU_ALUCommand <= ALU_SUB; elsif Instr_E = ADDI then DPU_ALUCommand <= ALU_ADD; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ONE16 & IMMEDIATE_EX; if IMMEDIATE_EX(15) = '0' then DataToDPU_2 <= ZERO16 & IMMEDIATE_EX; end if; elsif Instr_E = ADDIU then DPU_ALUCommand <= ALU_ADDU; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ONE16 & IMMEDIATE_EX; if IMMEDIATE_EX(15) = '0' then DataToDPU_2 <= ZERO16 & IMMEDIATE_EX; end if; elsif Instr_E = LUI then -- RFILE by default is giving R0 out DPU_ALUCommand <= ALU_OR; -- we OR the data from control unit with 0 DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= IMMEDIATE_EX & ZERO16; elsif Instr_E = CLO then DPU_ALUCommand <= ALU_CLO; elsif Instr_E = CLZ then DPU_ALUCommand <= ALU_CLZ; -----------------------SHIFT AND ROTATE------------------------------------- elsif Instr_E = SLL_inst or Instr_E = SRL_inst or Instr_E = SRA_inst then DataToDPU_2 <= ZERO16 & "00000000000" & sa_ex; DPU_Mux_Cont_2 <= CONT; case( Instr_E ) is when SLL_inst => DPU_ALUCommand <= ALU_SLL; when SRL_inst => DPU_ALUCommand <= ALU_SLR; when others => DPU_ALUCommand <= ALU_SAR; -- Instr_E = SRA_inst end case; elsif Instr_E = SLLV or Instr_E = SRLV or Instr_E = SRAV then case( Instr_E ) is when SLLV => DPU_ALUCommand <= ALU_SLL; when SRLV => DPU_ALUCommand <= ALU_SLR; when others => DPU_ALUCommand <= ALU_SAR; -- Instr_E = SRAV end case; -----------------------LOGICAL---------------------------------------------- elsif Instr_E = ANDI or Instr_E = ORI or Instr_E = XORI then DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ZERO16 & IMMEDIATE_EX; case( Instr_E ) is when ORI => DPU_ALUCommand <= ALU_OR; when ANDI => DPU_ALUCommand <= ALU_AND; when others => DPU_ALUCommand <= ALU_XOR; --Instr_E = XORI end case; elsif Instr_E = AND_inst then DPU_ALUCommand <= ALU_AND; elsif Instr_E = OR_inst then DPU_ALUCommand <= ALU_OR; elsif Instr_E = NOR_inst then DPU_ALUCommand <= ALU_NOR; elsif Instr_E = XOR_inst then DPU_ALUCommand <= ALU_XOR; -----------------------JUMP and BRANCH-------------------------------------- elsif Instr_E = BEQ or Instr_E = BNE then DPU_ALUCommand <= ALU_EQ; elsif Instr_E = BGTZ or (Instr_E = BGEZ or Instr_E = BGEZAL)then case( Instr_E ) is when BGTZ => DPU_ALUCommand <= ALU_COMP; when others => DPU_ALUCommand <= ALU_COMP_EQ; --BGEZ or BGEZAL end case; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= (others => '0'); elsif Instr_E = BLEZ or Instr_E = BLTZ or Instr_E = BLTZAL then case( Instr_E ) is when BLEZ => DPU_ALUCommand <= ALU_COMP_EQ; when others => DPU_ALUCommand <= ALU_COMP; --BLTZ or BLTZAL end case; ---------------CONDITION TESTING AND CONDITIONAL MOVE----------------------- elsif Instr_E = MOVN or Instr_E = MOVZ then DPU_ALUCommand <= ALU_EQ; elsif Instr_E = SLT then DPU_ALUCommand <= ALU_COMP; elsif Instr_E = SLTI then DPU_ALUCommand <= ALU_COMP; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ONE16 & IMMEDIATE_EX; if IMMEDIATE_EX(15) = '0' then DataToDPU_2 <= ZERO16 & IMMEDIATE_EX; end if; elsif Instr_E = SLTU then DPU_ALUCommand <= ALU_COMPU; elsif Instr_E = SLTIU then DPU_ALUCommand <= ALU_COMPU; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ONE16 & IMMEDIATE_EX; if IMMEDIATE_EX(15) = '0' then DataToDPU_2 <= ZERO16 & IMMEDIATE_EX; end if; -----------------------MULTIPLICATION AND DIVISION-------------------------- elsif Instr_E = MULTU or Instr_E = MULT or Instr_E = MUL or Instr_E = DIV or Instr_E = DIVU or Instr_E = MADD or Instr_E = MADDU or Instr_E = MSUB or Instr_E = MSUBU then case( Instr_E ) is when MULTU => DPU_ALUCommand <= ALU_MULTU; when MUL => DPU_ALUCommand <= ALU_MULT; when MULT => DPU_ALUCommand <= ALU_MULT; when MADD => DPU_ALUCommand <= ALU_MADD; when MADDU => DPU_ALUCommand <= ALU_MADDU; when MSUB => DPU_ALUCommand <= ALU_MSUB; when MSUBU => DPU_ALUCommand <= ALU_MSUBU; when DIV => DPU_ALUCommand <= ALU_DIV; when others => DPU_ALUCommand <= ALU_DIVU; -- Instr_E = DIVU end case; ----------------------ACCUMULATOR ACCESS ----------------------------------- elsif Instr_E = MTLO then DPU_ALUCommand <= ALU_MTLO; elsif Instr_E = MTHI then DPU_ALUCommand <= ALU_MTHI; ----------------------LOAD ------------------------------------------------- elsif Instr_E = LBU or Instr_E = LHU or Instr_E = LW or Instr_E = LWL or Instr_E = LWR then DPU_ALUCommand <= ALU_ADDU; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ONE16 & OFFSET_EX; if OFFSET_EX(15) = '0' then DataToDPU_2 <= ZERO16 & OFFSET_EX; end if; MemRdAddress <= DPU_RESULT(CPU_Bitwidth-1 downto 0); elsif Instr_E = LB or Instr_E = LH then DPU_ALUCommand <= ALU_ADD; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ONE16 & OFFSET_EX; if OFFSET_EX(15) = '0' then DataToDPU_2 <= ZERO16 & OFFSET_EX; end if; MemRdAddress <= DPU_RESULT(CPU_Bitwidth-1 downto 0); ------------------------store----------------------------------------------- elsif Instr_E = SB or Instr_E = SH or Instr_E = SW or Instr_E = SWL or Instr_E = SWR then DPU_ALUCommand <= ALU_ADDU; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ONE16 & OFFSET_EX; if OFFSET_EX(15) = '0' then DataToDPU_2 <= ZERO16 & OFFSET_EX; end if; -- Address Error Generration! if (Instr_E = SH) and DPU_RESULT(0) /= '0' then address_error <= '1'; elsif (Instr_E = SW) and DPU_RESULT(1 downto 0) /= "00" then address_error <= '1'; end if; MemWrtAddress <= DPU_RESULT(CPU_Bitwidth-1 downto 0); MEM_IN_SEL <= RFILE_DATA_2; case( Instr_E ) is when SB => Mem_RW <= "0001"; when SH => Mem_RW <= "0011"; when SW => Mem_RW <= "1111"; when SWL => Mem_RW <= "1100"; when others => Mem_RW <= "0011"; -- Instr_E = SWR end case; -------------------Co-Processor 0 and SYSCALL------------------------------- elsif Instr_E = MTC0 or Instr_E = SYSCALL then DPU_ALUCommand <= ALU_PASS_A; -------------------------------TRAPS---------------------------------------- elsif Instr_E = TEQ or Instr_E = TGE or Instr_E = TGEU then case( Instr_E ) is when TEQ => DPU_ALUCommand <= ALU_EQ; when TGE => DPU_ALUCommand <= ALU_COMP_EQ; when others => DPU_ALUCommand <= ALU_COMP_EQU; --TGEU end case; if LOW = ONE32 then trap <= '1'; end if; elsif Instr_E = TGEI or Instr_E = TGEIU or Instr_E = TEQI then case( Instr_E ) is when TGEI => DPU_ALUCommand <= ALU_COMP; when TGEIU => DPU_ALUCommand <= ALU_COMPU; when others => DPU_ALUCommand <= ALU_EQ; -- TEQI end case; DPU_Mux_Cont_2 <= CONT; DataToDPU_2 <= ONE16 & IMMEDIATE_EX; if IMMEDIATE_EX(15) = '0' then DataToDPU_2 <= ZERO16 & IMMEDIATE_EX; end if; if LOW = ONE32 then trap <= '1'; end if; end if; end process; -------------------------------------------------------------------------------- --WRITE BACK -------------------------------------------------------------------------------- WB_SIGNALS_GEN: process(Instr_WB, rt_wb, PC_out, LOW,PC_jmp_out) begin -- DO NOT CHANGE THE DEFAULT VALUES! RFILE_in_address <= (others => '0'); RFILE_data_sel <= DPU_LOW; Data_to_RFILE <= (others => '0'); RFILE_WB_enable <= "0000"; -----------------------Arithmetic----------------------------------------- if Instr_WB = ADD or Instr_WB = ADDU or Instr_WB = SUB or Instr_WB = SUBU or Instr_WB = CLO or Instr_WB = CLZ then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rd_wb; elsif Instr_WB = ADDI or Instr_WB = ADDIU or Instr_WB = LUI then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rt_wb; -----------------------logical-------------------------------------------- elsif Instr_WB = AND_inst or Instr_WB = OR_inst or Instr_WB = NOR_inst or Instr_WB = XOR_inst then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rd_wb; elsif Instr_WB = ANDI or Instr_WB = ORI or Instr_WB = XORI then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rt_wb; -----------------------SHIFT AND ROTATE----------------------------------- elsif Instr_WB = SLL_inst or Instr_WB = SRL_inst or Instr_WB = SLLV or Instr_WB = SRLV or Instr_WB = SRA_inst or Instr_WB = SRAV then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rd_wb; -----------------------MULTIPLICATION AND DIVISION------------------------ -- MULT and MULTU, MADD, MADDU, DIV and DIVU only WRITES IN ACC elsif Instr_WB = MUL then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rd_wb; ----------------------ACCUMULATOR ACCESS --------------------------------- -- MTHI and MTLO doesnt have WB elsif Instr_WB = MFLO then RFILE_data_sel <= ACC_LOW; RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rs_wb; elsif Instr_WB = MFHI then RFILE_data_sel <= ACC_HI; RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rs_wb; ----------------------LOAD AND STORE ----------------------------------- elsif Instr_WB = JAL or ((Instr_WB = BGEZAL or Instr_WB = BLTZAL) and LOW = ONE32) or Instr_WB = JALR then RFILE_WB_enable <= "1111"; if Instr_WB = JAL or ((Instr_WB = BGEZAL or Instr_WB = BLTZAL) and LOW = ONE32) then RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= "11111"; --REG(31) elsif Instr_WB = JALR then RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rd_wb; end if; RFILE_data_sel <= CU; --we are already in PC+8 since we are in execution cycle so the PC out --is 2*4 places ahead! Data_to_RFILE <= PC_jmp_out; ----------------------LOAD AND STORE---------------------------------------- elsif Instr_WB = LBU or Instr_WB = LB or Instr_WB = LH or Instr_WB = LW then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rt_wb; case( Instr_WB ) is when LBU => RFILE_data_sel <= FROM_MEM8; when LB => RFILE_data_sel <= FROM_MEM8_SGINED; when LHU => RFILE_data_sel <= FROM_MEM16; when LH => RFILE_data_sel <= FROM_MEM16_SGINED; when others => RFILE_data_sel <= FROM_MEM32; --Instr_WB = LW end case; elsif Instr_WB = LWL then RFILE_WB_enable <= "1100"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rt_wb; RFILE_data_sel <= FROM_MEM32; elsif Instr_WB = LWR then RFILE_WB_enable <= "0011"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rt_wb; RFILE_data_sel <= FROM_MEM32; --------------------------CO_PROCESSOR 0------------------------------------ elsif Instr_WB = MFC0 then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rt_wb; RFILE_data_sel <= CU; Data_to_RFILE <= cp0_control(to_integer(unsigned(rd_wb))); -------------CONDITION TESTING AND CONDITIONAL MOVE------------------------- elsif Instr_WB = MOVZ and LOW_FF = ONE32 then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rd_wb; RFILE_data_sel <= R2; elsif Instr_WB = MOVN and LOW_FF = ZERO32 then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rd_wb; RFILE_data_sel <= R2; elsif Instr_WB = SLT or Instr_WB = SLTI or Instr_WB = SLTU or Instr_WB = SLTIU then RFILE_WB_enable <= "1111"; RFILE_in_address(RFILE_SEL_WIDTH-1 downto 0) <= rd_wb; RFILE_data_sel <= CU; if LOW_FF = ONE32 then Data_to_RFILE <= "00000000000000000000000000000001"; else Data_to_RFILE <= (others => '0'); end if; end if; end process; -------------------------------------------------------------------------------- --PC handling -------------------------------------------------------------------------------- PC_HANDLING: process(PC_out,Instr_E, LOW, IMMEDIATE_EX, EPC, PC_jmp_out)begin PC_in <= PC_out + 4; flush_F2 <= '0'; PC_jmp_in <= PC_jmp_out; if Instr_E = SYSCALL then PC_in <= LOW; -- supposed to be contents of R2 elsif Instr_E = ERET then PC_in <= EPC; elsif Instr_E = J then flush_F2 <= '1'; PC_in <= PC_out(31 downto 28) & InstrReg_out_E(25 downto 0) & "00"; elsif Instr_E = JR then -- we are stroing PC in PC_jmp because we need WB for LINK. -- and by that time we have overwritten PC! PC_jmp_in <= PC_out; flush_F2 <= '1'; PC_in <= LOW; elsif Instr_E = JAL then -- we are stroing PC in PC_jmp because we need WB for LINK. -- and by that time we have overwritten PC! PC_jmp_in <= PC_out; flush_F2 <= '1'; PC_in <= PC_out(31 downto 28) & INST_INDEX_EX & "00"; elsif Instr_E = BEQ or Instr_E = BGTZ or Instr_E = BGEZ or Instr_E = BGEZAL or Instr_E = BLEZ or Instr_E = BLTZ or Instr_E = BLTZAL then if LOW = ONE32 then flush_F2 <= '1'; -- we are stroing PC in PC_jmp because we need WB in case of -- BGEZAL and BLTZAL. and by that time we have overwritten PC! PC_jmp_in <= PC_out; if IMMEDIATE_EX(15) = '0' then PC_in <= PC_out +(ZERO14 & IMMEDIATE_EX & "00")-1; else PC_in <= PC_out +(ONE14 & IMMEDIATE_EX & "00")-1; end if; end if; elsif Instr_E = BNE then if LOW = ZERO32 then flush_F2 <= '1'; if IMMEDIATE_EX(15) = '0' then PC_in <= PC_out +(ZERO14 & IMMEDIATE_EX & "00")-1; else PC_in <= PC_out +(ONE14 & IMMEDIATE_EX & "00")-1; end if; end if; end if; end process; -------------------------------------------------------------------------------- -- Instr decoder -------------------------------------------------------------------------------- INST_DECODER: process (SPECIAL_F, opcode_F) begin Instr_F <= NOP; Illigal_opcode <= '0'; case SPECIAL_F is when "000000" => case(opcode_F) is when "000000" => Instr_F <= SLL_inst; when "000010" => Instr_F <= SRL_inst; when "000011" => Instr_F <= SRA_inst; when "000100" => Instr_F <= SLLV; when "000110" => Instr_F <= SRLV; when "000111" => Instr_F <= SRAV; when "001000" => Instr_F <= JR; when "001001" => Instr_F <= JALR; when "001010" => Instr_F <= MOVZ; when "001011" => Instr_F <= MOVN; when "001100" => Instr_F <= SYSCALL; when "010000" => Instr_F <= MFHI; when "010001" => Instr_F <= MTHI; when "010010" => Instr_F <= MFLO; when "010011" => Instr_F <= MTLO; when "011000" => Instr_F <= MULT; when "011001" => Instr_F <= MULTU; when "011010" => Instr_F <= DIV; when "011011" => Instr_F <= DIVU; when "100000" => Instr_F <= ADD; when "100001" => Instr_F <= ADDU; when "100010" => Instr_F <= SUB; when "100011" => Instr_F <= SUBU; when "100100" => Instr_F <= AND_inst; when "100101" => Instr_F <= OR_inst; when "100110" => Instr_F <= XOR_inst; when "100111" => Instr_F <= NOR_inst; when "101010" => Instr_F <= SLT; when "101011" => Instr_F <= SLTU; when "110000" => Instr_F <= TGE; when "110001" => Instr_F <= TGEU; when "110100" => Instr_F <= TEQ; when others => Illigal_opcode <= '1'; end case; when "000001" => case(BRANCH_FIELD) is when "00000" => Instr_F <= BLTZ; when "00001" => Instr_F <= BGEZ; when "01000" => Instr_F <= TGEI; when "01001" => Instr_F <= TGEIU; when "01100" => Instr_F <= TEQI; when "10000" => Instr_F <= BLTZAL; when "10001" => Instr_F <= BGEZAL; when others => Illigal_opcode <= '1'; end case; when "000010" => Instr_F <= J; when "000011" => Instr_F <= JAL; when "000100" => Instr_F <= BEQ; when "000101" => Instr_F <= BNE; when "000110" => Instr_F <= BLEZ; when "000111" => Instr_F <= BGTZ; when "001000" => Instr_F <= ADDI; when "001001" => Instr_F <= ADDIU; when "001010" => Instr_F <= SLTI; when "001011" => Instr_F <= SLTIU; when "001100" => Instr_F <= ANDI; when "001101" => Instr_F <= ORI; when "001110" => Instr_F <= XORI; when "001111" => Instr_F <= LUI; when "010000" => if opcode_F = "011000" then Instr_F <= ERET; elsif MF = "00000" then Instr_F <= MFC0; elsif MF = "00100" then Instr_F <= MTC0; end if; when "011100" => case(opcode_F) is when "000000" => Instr_F <= MADD; when "000001" => Instr_F <= MADDU; when "000010" => Instr_F <= MUL; when "000100" => Instr_F <= MSUB; when "000101" => Instr_F <= MSUBU; when "100000" => Instr_F <= CLZ; when "100001" => Instr_F <= CLO; when others => Illigal_opcode <= '1'; end case; when "100000" => Instr_F <= LB; when "100001" => Instr_F <= LH; when "100010" => Instr_F <= LWL; when "100011" => Instr_F <= LW; when "100100" => Instr_F <= LBU; when "100101" => Instr_F <= LHU; when "100110" => Instr_F <= LWR; when "101000" => Instr_F <= SB; when "101001" => Instr_F <= SH; when "101010" => Instr_F <= SWL; when "101011" => Instr_F <= SW; when "101110" => Instr_F <= SWR; when others => Illigal_opcode <= '1'; end case; end process; end RTL;
gpl-2.0
60d686cc47d236e5a16d7ae958ef129e
0.493628
3.557612
false
false
false
false
Yarr/Yarr-fw
rtl/spartan6/ddr3-core/ddr3_ctrl_wb.vhd
2
10,270
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library work; use work.ddr3_ctrl_pkg.all; entity ddr3_ctrl_wb is generic ( g_BYTE_ADDR_WIDTH : integer := 30; g_MASK_SIZE : integer := 4; g_DATA_PORT_SIZE : integer := 32 ); port ( ---------------------------------------------------------------------------- -- Reset input (active low) ---------------------------------------------------------------------------- rst_n_i : in std_logic; ---------------------------------------------------------------------------- -- Status ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- DDR controller port ---------------------------------------------------------------------------- ddr_cmd_clk_o : out std_logic; ddr_cmd_en_o : out std_logic; ddr_cmd_instr_o : out std_logic_vector(2 downto 0); ddr_cmd_bl_o : out std_logic_vector(5 downto 0); ddr_cmd_byte_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0); ddr_cmd_empty_i : in std_logic; ddr_cmd_full_i : in std_logic; ddr_wr_clk_o : out std_logic; ddr_wr_en_o : out std_logic; ddr_wr_mask_o : out std_logic_vector(g_MASK_SIZE - 1 downto 0); ddr_wr_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0); ddr_wr_full_i : in std_logic; ddr_wr_empty_i : in std_logic; ddr_wr_count_i : in std_logic_vector(6 downto 0); ddr_wr_underrun_i : in std_logic; ddr_wr_error_i : in std_logic; ddr_rd_clk_o : out std_logic; ddr_rd_en_o : out std_logic; ddr_rd_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0); ddr_rd_full_i : in std_logic; ddr_rd_empty_i : in std_logic; ddr_rd_count_i : in std_logic_vector(6 downto 0); ddr_rd_overflow_i : in std_logic; ddr_rd_error_i : in std_logic; ---------------------------------------------------------------------------- -- Wishbone bus port ---------------------------------------------------------------------------- wb_clk_i : in std_logic; wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_addr_i : in std_logic_vector(31 downto 0); wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0); wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0); wb_ack_o : out std_logic; wb_stall_o : out std_logic ); end entity ddr3_ctrl_wb; architecture behavioral of ddr3_ctrl_wb is -------------------------------------- -- Constants -------------------------------------- constant c_DDR_BURST_LENGTH : unsigned(5 downto 0) := TO_UNSIGNED(16, 6); constant c_READ_STALL_ASSERT : unsigned(6 downto 0) := TO_UNSIGNED(54, 7); constant c_READ_STALL_NEGATE : unsigned(6 downto 0) := TO_UNSIGNED(42, 7); constant c_WRITE_STALL_ASSERT : unsigned(6 downto 0) := TO_UNSIGNED(52, 7); constant c_WRITE_STALL_NEGATE : unsigned(6 downto 0) := TO_UNSIGNED(42, 7); constant c_ADDR_SHIFT : integer := log2_ceil(g_DATA_PORT_SIZE/8); constant c_STALL_TIME : unsigned(3 downto 0) := TO_UNSIGNED(15, 4); -------------------------------------- -- Signals -------------------------------------- signal ddr_wr_ack : std_logic; signal ddr_rd_ack : std_logic; signal ddr_rd_en : std_logic; signal ddr_cmd_en : std_logic; signal ddr_cmd_full : std_logic; signal wb_stall : std_logic; signal wb_stall_d : std_logic; signal wb_stall_dd : std_logic; signal wb_we_d : std_logic; signal wb_addr_d : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0); signal wb_stall_restart : std_logic; signal addr_shift : std_logic_vector(c_ADDR_SHIFT-1 downto 0); -------------------------------------- -- Counter -------------------------------------- signal wb_stall_cnt : unsigned(3 downto 0); signal ddr_burst_cnt : unsigned(5 downto 0); signal ddr_burst_cnt_d : unsigned(5 downto 0); signal read_cnt : unsigned(7 downto 0); signal write_cnt : unsigned(7 downto 0); begin -- Tie offs ddr_wr_clk_o <= wb_clk_i; ddr_rd_clk_o <= wb_clk_i; ddr_cmd_clk_o <= wb_clk_i; wb_ack_o <= ddr_wr_ack or ddr_rd_ack; -------------------------------------- -- Wishbone write -------------------------------------- p_wb_write : process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then ddr_wr_en_o <= '0'; ddr_wr_ack <= '0'; ddr_wr_data_o <= (others => '0'); ddr_wr_mask_o <= (others => '0'); elsif rising_edge(wb_clk_i) then if (wb_cyc_i = '1' and wb_stb_i = '1' and wb_we_i = '1') then ddr_wr_data_o <= wb_data_i; ddr_wr_mask_o <= not(wb_sel_i); ddr_wr_en_o <= '1'; ddr_wr_ack <= '1'; else ddr_wr_data_o <= (others => '0'); ddr_wr_mask_o <= (others => '0'); ddr_wr_en_o <= '0'; ddr_wr_ack <= '0'; end if; end if; end process p_wb_write; -------------------------------------- -- Wishbone read -------------------------------------- ddr_rd_en_o <= ddr_rd_en; p_wb_read : process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then ddr_rd_en <= '0'; ddr_rd_ack <= '0'; wb_data_o <= (others => '0'); elsif rising_edge(wb_clk_i) then if (wb_cyc_i = '1' and ddr_rd_empty_i = '0') then ddr_rd_en <= '1'; else ddr_rd_en <= '0'; end if; if (ddr_rd_en = '1' and ddr_rd_empty_i = '0') then ddr_rd_ack <= '1'; wb_data_o <= ddr_rd_data_i; else ddr_rd_ack <= '0'; wb_data_o <= (others => '1'); end if; end if; end process p_wb_read; -------------------------------------- -- DDR Control -------------------------------------- addr_shift <= (others => '0'); ddr_cmd_en_o <= ddr_cmd_en; p_ddr_ctrl : process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then ddr_burst_cnt <= (others => '0'); ddr_cmd_en <= '0'; ddr_cmd_byte_addr_o <= (others => '0'); ddr_cmd_instr_o <= (others => '0'); ddr_cmd_bl_o <= (others => '0'); wb_addr_d <= (others => '0'); wb_we_d <= '0'; wb_stall_restart <= '1'; read_cnt <= (others => '0'); write_cnt <= (others =>'0'); elsif rising_edge(wb_clk_i) then if (wb_cyc_i = '1' and wb_stb_i = '1') then if (ddr_burst_cnt = c_DDR_BURST_LENGTH) then ddr_burst_cnt <= TO_UNSIGNED(1, 6); ddr_cmd_en <= '1'; else ddr_burst_cnt <= ddr_burst_cnt + 1; ddr_cmd_en <= '0'; end if; elsif (wb_cyc_i = '1' and wb_stb_i = '0' and ddr_burst_cnt > 0 and wb_stall_dd = '0') then ddr_burst_cnt <= TO_UNSIGNED(0, 6); ddr_cmd_en <= '1'; else ddr_cmd_en <= '0'; end if; ddr_cmd_bl_o <= STD_LOGIC_VECTOR(ddr_burst_cnt - 1); ddr_burst_cnt_d <= ddr_burst_cnt; if (wb_stb_i = '1') then wb_addr_d <= wb_addr_i; wb_we_d <= wb_we_i; end if; if (ddr_burst_cnt = 0) then ddr_cmd_byte_addr_o <= wb_addr_i(g_BYTE_ADDR_WIDTH-c_ADDR_SHIFT-1 downto 0) & addr_shift; ddr_cmd_instr_o <= "00" & not(wb_we_i); elsif (ddr_cmd_en = '1') then ddr_cmd_byte_addr_o <= wb_addr_d(g_BYTE_ADDR_WIDTH-c_ADDR_SHIFT-1 downto 0) & addr_shift; ddr_cmd_instr_o <= "00" & not(wb_we_d); end if; if (wb_we_i = '0') then if (ddr_cmd_en = '1' and ddr_rd_ack = '0') then read_cnt <= read_cnt + ddr_burst_cnt_d; elsif (ddr_cmd_en = '1' and ddr_rd_ack = '1') then read_cnt <= read_cnt + ddr_burst_cnt_d - 1; elsif (ddr_cmd_en = '0' and ddr_rd_ack = '1' and read_cnt > 0) then read_cnt <= read_cnt - 1; end if; else if (ddr_cmd_en = '1' and ddr_wr_ack = '0' and write_cnt >= ddr_burst_cnt_d) then write_cnt <= write_cnt - ddr_burst_cnt_d; elsif (ddr_cmd_en = '1' and ddr_wr_ack = '1' and write_cnt >= ddr_burst_cnt_d ) then write_cnt <= (write_cnt - ddr_burst_cnt_d) + 1; elsif (ddr_cmd_en = '0' and ddr_wr_ack = '1') then write_cnt <= write_cnt + 1; end if; end if; if (wb_stall = '1') then wb_stall_restart <= '0'; elsif (wb_stb_i = '1' ) then wb_stall_restart <= '1'; end if; end if; end process p_ddr_ctrl; -------------------------------------- -- Stall proc -------------------------------------- wb_stall_o <= wb_stall; p_wb_stall : process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_stall <= '0'; wb_stall_d <= '0'; wb_stall_dd <= '0'; ddr_cmd_full <= '0'; wb_stall_cnt <= (others => '0'); elsif rising_edge(wb_clk_i) then ddr_cmd_full <= ddr_cmd_full_i; if (ddr_cmd_full = '1' or read_cnt > c_READ_STALL_ASSERT or unsigned(ddr_wr_count_i) > c_WRITE_STALL_ASSERT) then wb_stall <= '1'; elsif (ddr_cmd_full = '0' and read_cnt < c_READ_STALL_NEGATE and unsigned(ddr_wr_count_i) < c_WRITE_STALL_NEGATE) then wb_stall <= '0'; end if; wb_stall_d <= wb_stall; wb_stall_dd <= wb_stall_d; end if; end process p_wb_stall; end architecture behavioral;
gpl-3.0
890de148a5a0e736693963d369cd4180
0.437196
3.276962
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/reset_builtin.vhd
2
19,078
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bsd-2-clause
d781be738a5b2f64a51d627f6be9e59b
0.939774
1.860542
false
false
false
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Yarr/Yarr-fw
rtl/kintex7/ddr3k7-core/ddr3_write_core.vhd
1
15,010
---------------------------------------------------------------------------------- -- Company: LBNL -- Engineer: Arnaud Sautaux -- -- Create Date: 07/27/2017 10:50:41 AM -- Design Name: ddr3k7-core -- Module Name: ddr3_write_core - Behavioral -- Project Name: YARR -- Target Devices: xc7k160t -- Tool Versions: Vivado v2016.2 (64 bit) -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity ddr3_write_core is generic ( g_BYTE_ADDR_WIDTH : integer := 29; g_MASK_SIZE : integer := 8; g_DATA_PORT_SIZE : integer := 64; g_NOT_CONSECUTIVE_DETECTION : boolean := false ); Port ( ---------------------------------------------------------------------------- -- Reset input (active low) ---------------------------------------------------------------------------- rst_n_i : in std_logic; wb_clk_i : in STD_LOGIC; wb_sel_i : in STD_LOGIC_VECTOR (g_MASK_SIZE - 1 downto 0); wb_stb_i : in STD_LOGIC; wb_cyc_i : in STD_LOGIC; wb_we_i : in STD_LOGIC; wb_adr_i : in STD_LOGIC_VECTOR (32 - 1 downto 0); wb_dat_i : in STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0); wb_dat_o : out STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0); wb_ack_o : out STD_LOGIC; wb_stall_o : out STD_LOGIC; ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0); ddr_cmd_o : out std_logic_vector(2 downto 0); ddr_cmd_en_o : out std_logic; ddr_wdf_data_o : out std_logic_vector(511 downto 0); ddr_wdf_end_o : out std_logic; ddr_wdf_mask_o : out std_logic_vector(63 downto 0); ddr_wdf_wren_o : out std_logic; ddr_rdy_i : in std_logic; ddr_wdf_rdy_i : in std_logic; ddr_ui_clk_i : in std_logic; ddr_req_o : out std_logic; ddr_gnt_i : in std_logic ); end ddr3_write_core; architecture Behavioral of ddr3_write_core is -------------------------------------- -- Components -------------------------------------- COMPONENT fifo_605x32 PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(604 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(604 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; -------------------------------------- -- Constants -------------------------------------- constant c_write_wait_time : unsigned(7 downto 0) := TO_UNSIGNED(15, 8); constant c_register_shift_size : integer := 8; -------------------------------------- -- Types -------------------------------------- type data_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0); type mask_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_MASK_SIZE - 1 downto 0); type addr_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0); type row_array is array (0 to c_register_shift_size-1) of std_logic_vector(c_register_shift_size-1 downto 0); -------------------------------------- -- Signals -------------------------------------- signal rst_s : std_logic; signal wb_sel_s : std_logic_vector(g_MASK_SIZE - 1 downto 0); signal wb_cyc_s : std_logic; signal wb_stb_s : std_logic; signal wb_we_s : std_logic; signal wb_adr_s : std_logic_vector(32 - 1 downto 0); signal wb_dat_s : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0); signal wb_ack_s : std_logic; signal wb_stall_s : std_logic; signal wb_wr_data_shift_a : data_array; signal wb_wr_data_shift_next_a : data_array; signal wb_wr_data_shift_s : std_logic_vector(511 downto 0); signal wb_wr_mask_shift_a : mask_array; signal wb_wr_mask_shift_next_a : mask_array; signal wb_wr_valid_shift_s : std_logic_vector(c_register_shift_size-1 downto 0); signal wb_wr_valid_shift_next_s : std_logic_vector(c_register_shift_size-1 downto 0); signal wb_wr_addr_shift_a : addr_array; signal wb_wr_addr_shift_next_a : addr_array; signal wb_wr_shifting_s : std_logic; signal wb_wr_aligned : std_logic_vector(c_register_shift_size-1 downto 0); signal wb_wr_row_a : row_array; signal wb_wr_global_row_s : std_logic_vector(c_register_shift_size-1 downto 0); signal wb_wr_first_row_s : std_logic_vector(c_register_shift_size-1 downto 0); signal wb_wr_several_row_s : std_logic; signal wb_wr_flush_v_s : std_logic_vector(c_register_shift_size-1 downto 0); signal wb_wr_shift_flush_s : std_logic; signal wb_wr_shift_flush_1_s : std_logic; signal fifo_wb_wr_mask_s : std_logic_vector(63 downto 0); signal fifo_wb_wr_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0); signal fifo_wb_wr_din_s : std_logic_vector(604 downto 0); signal fifo_wb_wr_wr_s : std_logic; signal fifo_wb_wr_rd_s : std_logic; signal fifo_wb_wr_rd_d : std_logic; signal fifo_wb_wr_dout_s : std_logic_vector(604 downto 0); signal fifo_wb_wr_full_s : std_logic; signal fifo_wb_wr_empty_s : std_logic; -------------------------------------- -- Counter -------------------------------------- signal wb_write_wait_cnt : unsigned(7 downto 0); begin rst_s <= not rst_n_i; -------------------------------------- -- Wishbone input delay -------------------------------------- p_wb_in : process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_sel_s <= (others =>'0'); wb_cyc_s <= '0'; wb_stb_s <= '0'; wb_we_s <= '0'; wb_adr_s <= (others =>'0'); wb_dat_s <= (others =>'0'); elsif rising_edge(wb_clk_i) then wb_sel_s <= wb_sel_i; wb_cyc_s <= wb_cyc_i; wb_stb_s <= wb_stb_i; wb_we_s <= wb_we_i; wb_adr_s <= wb_adr_i; wb_dat_s <= wb_dat_i; end if; end process p_wb_in; -------------------------------------- -- Wishbone ouput -------------------------------------- wb_ack_o <= wb_ack_s; wb_dat_o <= (others => '0'); detection_gen : if (g_NOT_CONSECUTIVE_DETECTION = true) generate wb_stall_s <= fifo_wb_wr_full_s or wb_wr_several_row_s; end generate; no_dectection_gen : if (g_NOT_CONSECUTIVE_DETECTION = false) generate wb_stall_s <= fifo_wb_wr_full_s; end generate; wb_stall_o <= wb_stall_s; -------------------------------------- -- Wishbone write process -------------------------------------- p_wb_write : process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_write_wait_cnt <= c_write_wait_time; wb_wr_shift_flush_1_s <= '0'; wb_wr_valid_shift_s <= (others => '0'); for i in 0 to c_register_shift_size-1 loop wb_wr_addr_shift_a(i) <= (others => '1'); wb_wr_data_shift_a(i) <= (others => '0'); wb_wr_mask_shift_a(i) <= (others => '0'); end loop; wb_ack_s <= '0'; elsif rising_edge(wb_clk_i) then wb_wr_shift_flush_1_s <= wb_wr_shift_flush_s; if (wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '1') then wb_ack_s <= '1'; wb_write_wait_cnt <= c_write_wait_time; else wb_ack_s <= '0'; if(wb_wr_valid_shift_s /= (wb_wr_valid_shift_s'range => '0')) then if (wb_write_wait_cnt /= 0) then wb_write_wait_cnt <= wb_write_wait_cnt - 1; end if; end if; end if; if(wb_wr_shift_flush_s = '1') then wb_write_wait_cnt <= c_write_wait_time; end if; wb_wr_addr_shift_a <= wb_wr_addr_shift_next_a; wb_wr_data_shift_a <= wb_wr_data_shift_next_a; wb_wr_mask_shift_a <= wb_wr_mask_shift_next_a; wb_wr_valid_shift_s <= wb_wr_valid_shift_next_s; end if; end process p_wb_write; p_wb_write_rtl : process (wb_write_wait_cnt,wb_wr_addr_shift_a,wb_wr_valid_shift_s,wb_wr_shift_flush_s,wb_wr_first_row_s,wb_wr_row_a,wb_wr_aligned,wb_wr_global_row_s) begin fifo_wb_wr_addr_s <= (others => '0'); wb_wr_first_row_s <= (others => '0'); for i in (c_register_shift_size-1) downto 0 loop if wb_wr_global_row_s(i) = '1' then fifo_wb_wr_addr_s <= wb_wr_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) & "000" ; wb_wr_first_row_s <= wb_wr_row_a(i); end if; end loop; if((wb_wr_global_row_s /= wb_wr_first_row_s) and (wb_wr_global_row_s /= (wb_wr_global_row_s'range => '0'))) then wb_wr_several_row_s <= '1'; else wb_wr_several_row_s <= '0'; end if; end process p_wb_write_rtl; p_wb_write_shift: process (wb_wr_shifting_s,wb_wr_addr_shift_a,wb_wr_data_shift_a,wb_wr_mask_shift_a,wb_wr_valid_shift_s,wb_adr_s,wb_dat_s,wb_sel_s,wb_wr_flush_v_s) begin if(wb_wr_shifting_s = '1') then wb_wr_addr_shift_next_a(c_register_shift_size-1) <= wb_adr_s(g_BYTE_ADDR_WIDTH-1 downto 0); wb_wr_data_shift_next_a(c_register_shift_size-1) <= wb_dat_s; wb_wr_mask_shift_next_a(c_register_shift_size-1) <= wb_sel_s; wb_wr_valid_shift_next_s(c_register_shift_size-1) <= wb_cyc_s and wb_stb_s and wb_we_s; for i in 1 to c_register_shift_size-1 loop wb_wr_addr_shift_next_a(i-1) <= wb_wr_addr_shift_a(i); wb_wr_data_shift_next_a(i-1) <= wb_wr_data_shift_a(i); wb_wr_mask_shift_next_a(i-1) <= wb_wr_mask_shift_a(i); if wb_wr_flush_v_s(i) = '0' then wb_wr_valid_shift_next_s(i-1) <= wb_wr_valid_shift_s(i); else wb_wr_valid_shift_next_s(i-1) <= '0'; end if; end loop; else for i in 0 to c_register_shift_size-1 loop wb_wr_addr_shift_next_a(i) <= wb_wr_addr_shift_a(i); wb_wr_data_shift_next_a(i) <= wb_wr_data_shift_a(i); wb_wr_mask_shift_next_a(i) <= wb_wr_mask_shift_a(i); if wb_wr_flush_v_s(i) = '0' then wb_wr_valid_shift_next_s(i) <= wb_wr_valid_shift_s(i); else wb_wr_valid_shift_next_s(i) <= '0'; end if; end loop; end if; end process p_wb_write_shift; wb_wr_shifting_s <= --'0' when wb_wr_several_row_s = '1' else '1' when wb_cyc_s = '1' and wb_stb_s = '1' and wb_we_s = '1' else --and wb_stall_s = '0' else '1' when wb_write_wait_cnt = 0 else '0'; wb_wr_global_row_s <= wb_wr_aligned and wb_wr_valid_shift_s; wb_wr_flush_v_s <= wb_wr_first_row_s; wb_wr_shift_flush_s <= '1' when wb_wr_flush_v_s /= (wb_wr_flush_v_s'range => '0') else '0'; wr_mask_match_g:for i in 0 to c_register_shift_size-1 generate wb_wr_aligned(i) <= '1' when wb_wr_addr_shift_a(i)(2 downto 0) = std_logic_vector(to_unsigned(i,3)) else '0'; wr_row_g:for j in 0 to c_register_shift_size-1 generate wb_wr_row_a(i)(j) <= '1' when wb_wr_addr_shift_a(i)(g_BYTE_ADDR_WIDTH-1 downto 3) = wb_wr_addr_shift_a(j)(g_BYTE_ADDR_WIDTH-1 downto 3) and wb_wr_aligned(i) = '1' and wb_wr_aligned(j) = '1' and wb_wr_valid_shift_s(i) = '1' and wb_wr_valid_shift_s(j) = '1' else '0'; end generate; fifo_wb_wr_mask_s((i)*8+7 downto (i)*8) <= wb_wr_mask_shift_a(i) when wb_wr_flush_v_s(i) = '1' else (others=>'0'); end generate; wb_wr_data_shift_s <= wb_wr_data_shift_a(7) & wb_wr_data_shift_a(6) & wb_wr_data_shift_a(5) & wb_wr_data_shift_a(4) & wb_wr_data_shift_a(3) & wb_wr_data_shift_a(2) & wb_wr_data_shift_a(1) & wb_wr_data_shift_a(0); fifo_wr_data_in : process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then fifo_wb_wr_din_s <= (others => '0'); fifo_wb_wr_wr_s <= '0'; elsif rising_edge(wb_clk_i) then fifo_wb_wr_din_s <= fifo_wb_wr_addr_s & fifo_wb_wr_mask_s & wb_wr_data_shift_s; fifo_wb_wr_wr_s <= wb_wr_shift_flush_s; end if; end process; fifo_wb_write : fifo_605x32 PORT MAP ( rst => rst_s, wr_clk => wb_clk_i, rd_clk => ddr_ui_clk_i, din => fifo_wb_wr_din_s, wr_en => fifo_wb_wr_wr_s, rd_en => fifo_wb_wr_rd_s, dout => fifo_wb_wr_dout_s, full => fifo_wb_wr_full_s, empty => fifo_wb_wr_empty_s ); -------------------------------------- -- DDR CMD -------------------------------------- ddr_cmd_en_o <= fifo_wb_wr_rd_s; ddr_addr_o <= fifo_wb_wr_dout_s(604 downto 576); ddr_cmd_o <= "000"; -------------------------------------- -- DDR Data out -------------------------------------- ddr_wdf_wren_o <= fifo_wb_wr_rd_s; ddr_wdf_end_o <= fifo_wb_wr_rd_s; ddr_wdf_data_o <= fifo_wb_wr_dout_s(511 downto 0); ddr_wdf_mask_o <= not fifo_wb_wr_dout_s(575 downto 512); ddr_req_o <= not fifo_wb_wr_empty_s; -------------------------------------- -- DDR Data in -------------------------------------- fifo_wb_wr_rd_s <= ddr_wdf_rdy_i and ddr_rdy_i and ddr_gnt_i and (not fifo_wb_wr_empty_s); end Behavioral;
gpl-3.0
f92caa50eca210bd2cab1c65c784fa16
0.462891
3.208636
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/styles/code_examples/timestamp.vhdl
1
6,175
-- -- PowerPC 405 APU FCM "timestamp" -- record a time (counter value) of User Defined Instruction execution -- -- Marek Peca <[email protected]> 07/2008 -- KRT FEL CVUT http://dce.felk.cvut.cz/ -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.RAMB16; entity timestamp is port ( reset: in std_logic; -- APU i/f: CPMFCMCLK: in std_logic; APUFCMFLUSH: in std_logic; APUFCMDECODED: in std_logic; APUFCMINSTRVALID: in std_logic; APUFCMDECUDIVALID: in std_logic; APUFCMDECUDI: in std_logic_vector (2 downto 0); APUFCMWRITEBACKOK: in std_logic; APUFCMRADATA: in std_logic_vector (31 downto 0); APUFCMRBDATA: in std_logic_vector (31 downto 0); FCMAPUDONE: out std_logic; FCMAPUSLEEPNOTREADY: out std_logic; -- BRAM slave i/f: BRAM_Rst_B: in std_logic; BRAM_Clk_B: in std_logic; BRAM_EN_B: in std_logic; BRAM_WEN_B: in std_logic_vector (7 downto 0); BRAM_Addr_B: in std_logic_vector (31 downto 0); BRAM_Dout_B: in std_logic_vector (63 downto 0); BRAM_Din_B: out std_logic_vector (63 downto 0); -- etc. debug: out std_logic_vector (3 downto 0) ); end timestamp; architecture timestamp_fcm of timestamp is type state_type is (IDLE, WAIT_OPERAND); -- global signal clock: std_logic; -- FSM signal state, next_state: state_type; signal counter: std_logic_vector (31 downto 0); signal addr_counter: std_logic_vector (9 downto 0); signal save_udi_code: std_logic; signal udi_code: std_logic_vector (2 downto 0); -- BRAM signal wea: std_logic; signal dia0, dia1: std_logic_vector (31 downto 0); signal addra: std_logic_vector (9 downto 0); begin clock <= CPMFCMCLK; dia0 <= counter; dia1 <= APUFCMRADATA; addra <= addr_counter; -- debug(0) <= addr_counter(0); -- debug(1) <= APUFCMDECUDIVALID; -- debug(2) <= APUFCMWRITEBACKOK; -- debug(3) <= wea; debug(0) <= CPMFCMCLK; debug(1) <= APUFCMDECODED; debug(2) <= APUFCMDECUDIVALID; debug(3) <= APUFCMWRITEBACKOK; seq: process () begin wait until clock'event and clock = '1'; if reset = '1' then state <= IDLE; counter <= X"00000000"; addr_counter <= "0000000000"; else if save_udi_code = '1' then udi_code <= APUFCMDECUDI; end if; state <= next_state; counter <= counter + 1; if wea = '1' then addr_counter <= addr_counter + 1; end if; end if; end process; comb_apu: process (state, udi_code, APUFCMFLUSH, APUFCMINSTRVALID, APUFCMDECUDIVALID, APUFCMWRITEBACKOK, APUFCMDECUDI) begin save_udi_code <= '0'; wea <= '0'; FCMAPUSLEEPNOTREADY <= '0'; FCMAPUDONE <= '0'; case state is when IDLE => if APUFCMFLUSH = '1' then next_state <= IDLE; elsif (APUFCMINSTRVALID and APUFCMDECODED and APUFCMDECUDIVALID) = '1' then if APUFCMWRITEBACKOK = '1' then -- operands are ready if APUFCMDECUDI = "000" then wea <= '1'; FCMAPUDONE <= '1'; end if; else save_udi_code <= '1'; next_state <= WAIT_OPERAND; end if; end if; when WAIT_OPERAND => FCMAPUSLEEPNOTREADY <= '1'; if APUFCMFLUSH = '1' then next_state <= IDLE; elsif APUFCMWRITEBACKOK = '1' then if udi_code = "000" then wea <= '1'; FCMAPUDONE <= '1'; end if; end if; next_state <= IDLE; end case; end process; -- comb_action: process (action, action_udi_code) -- -- following block causes "gated clock" warning -- -- after FCMAPUDONE removal, everything seems to be OK -- -- what is strange: the same construct above at FCMAPUSLEEPNOTREADY -- -- causes no warning -- begin -- wea <= '0'; -- FCMAPUDONE <= '0'; -- if (action = '1') and (action_udi_code = "111") then -- wea <= '1'; -- FCMAPUDONE <= '1'; -- end if; -- end process; bram0: RAMB16 generic map ( INVERT_CLK_DOA_REG => false, INVERT_CLK_DOB_REG => false, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", READ_WIDTH_A => 36, READ_WIDTH_B => 36, WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 36, WRITE_WIDTH_B => 36 ) port map ( DOA => open, DOB => BRAM_Din_B(31 downto 0), ADDRA(14 downto 5) => addra, ADDRA(4 downto 0) => "00000", ADDRB(14 downto 2) => BRAM_Addr_B(12 downto 0), ADDRB(1 downto 0) => "00", CASCADEINA => '0', CASCADEINB => '0', CLKA => clock, CLKB => BRAM_Clk_B, DIA => dia0, DIB => BRAM_Dout_B(31 downto 0), DIPA => "0000", DIPB => "0000", ENA => '1', ENB => BRAM_EN_B, REGCEA => '1', REGCEB => '1', SSRA => '0', SSRB => BRAM_Rst_B, WEA(0) => wea, WEA(1) => wea, WEA(2) => wea, WEA(3) => wea, WEB => BRAM_WEN_B(3 downto 0) ); bram1: RAMB16 generic map ( INVERT_CLK_DOA_REG => false, INVERT_CLK_DOB_REG => false, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", READ_WIDTH_A => 36, READ_WIDTH_B => 36, WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 36, WRITE_WIDTH_B => 36 ) port map ( DOA => open, DOB => BRAM_Din_B(63 downto 32), ADDRA(14 downto 5) => addra, ADDRA(4 downto 0) => "00000", ADDRB(14 downto 2) => BRAM_Addr_B(12 downto 0), ADDRB(1 downto 0) => "00", CASCADEINA => '0', CASCADEINB => '0', CLKA => clock, CLKB => BRAM_Clk_B, DIA => dia1, DIB => BRAM_Dout_B(63 downto 32), DIPA => "0000", DIPB => "0000", ENA => '1', ENB => BRAM_EN_B, REGCEA => '1', REGCEB => '1', SSRA => '0', SSRB => BRAM_Rst_B, WEA(0) => wea, WEA(1) => wea, WEA(2) => wea, WEA(3) => wea, WEB => BRAM_WEN_B(7 downto 4) ); end timestamp_fcm; -- EOF
gpl-3.0
9930c78144d186e42d06a6106f1beadb
0.560324
3.309218
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/conditional_expressions/rule_500_test_input.fixed_lower.vhd
1
400
architecture rtl of fifo is begin process begin var1 := '0' when rd_en = '1' else '1'; var2 := '0' when rd_en = '1' else '1'; wr_en_a <= force '0' when rd_en = '1' else '1'; wr_en_b <= force '0' when rd_en = '1' else '1'; end process; concurrent_wr_en_a <= '0' WHEN rd_en = '1' else '1'; concurrent_wr_en_b <= '0' when rd_en = '1' else '1'; end architecture rtl;
gpl-3.0
2a09e2a08acf3e745f2466e66f94075e
0.54
2.564103
false
false
false
false
okaxaki/vm2413
Operator.vhd
2
3,716
-- -- Operator.vhd -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use WORK.VM2413.ALL; entity Operator is port ( clk : in std_logic; reset : in std_logic; clkena : in std_logic; slot : in SLOT_TYPE; stage : in STAGE_TYPE; rhythm : in std_logic; WF : in WF_TYPE; FB : in FB_TYPE; noise : in std_logic; pgout : in PGOUT_TYPE; egout : in DB_TYPE; faddr : out CH_TYPE; fdata : in SIGNED_LI_TYPE; opout : out SIGNED_DB_TYPE ); end Operator; architecture RTL of Operator is component AttackTable port ( clk : in std_logic; addr : in DB_TYPE; data : out DB_TYPE ); end component; component SineTable port ( clk : in std_logic; wf : in std_logic; addr : in integer range 0 to (2 ** (PGOUT_TYPE'high+1) - 1); data : out SIGNED_DB_TYPE ); end component; signal addr : integer range 0 to (2 ** (PGOUT_TYPE'high+1) - 1); signal data : SIGNED_DB_TYPE; begin SINTBL : SineTable port map ( clk, WF, addr, data ); process(clk, reset) variable modula : std_logic_vector(LI_TYPE'high + 2 downto 0); variable opout_buf : SIGNED_DB_TYPE; begin if reset='1' then opout <= ( sign=>'0', value=>(others=>'0') ); elsif clk'event and clk='1' then if clkena = '1' then if stage = 0 then -- periodic noise if rhythm = '1' and ( slot = 14 or slot = 17 ) then -- HH or CYM if noise = '1' then addr <= 127; -- phase of max value else addr <= 383; -- phase of min value end if; elsif rhythm = '1' and slot = 15 then -- SD if pgout(pgout'high) = '1' then addr <= 127; -- phase of max value else addr <= 383; -- phase of min value end if; elsif rhythm = '1' and slot = 16 then -- TOM addr <= CONV_INTEGER(pgout); else if slot mod 2 = 0 then if FB = "000" then modula := (others => '0') ; else modula := "0" & fdata.value & "0"; modula := SHR( modula, "111" - FB ); end if; else modula := fdata.value & "00"; end if; if fdata.sign = '0' then addr <= CONV_INTEGER(pgout + modula(pgout'range)); else addr <= CONV_INTEGER(pgout - modula(pgout'range)); end if; end if; elsif stage = 1 then -- Wait for sine and attack table. elsif stage = 2 then -- output if ( ( '0'&egout ) + ('0'&data.value) ) < "10000000" then opout_buf := ( sign=>data.sign, value=> egout + data.value ); else opout_buf := ( sign=>data.sign, value=> (others=>'1') ); end if; -- read feedback data for the next slot if slot mod 2 = 1 then if slot/2 = 8 then faddr <= 0; else faddr <= slot/2 + 1; end if; else faddr <= slot/2; end if; opout <= opout_buf; elsif stage = 3 then -- wait for feedback data. end if; end if; end if; end process; end RTL;
mit
f34637ef0cc7dc71025d5d05c75d1963
0.445102
3.965848
false
false
false
false
Jorge9314/ElectronicaDigital
Impresora2D/TB_Utilidad_RS232.vhd
1
3,908
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY TB_Utilidad_RS232 IS END TB_Utilidad_RS232; ARCHITECTURE behavior OF TB_Utilidad_RS232 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Utilidad_RS232 PORT( clk : IN std_logic; Recibo : IN std_logic; Devuelvo : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal Recibo : std_logic := '0'; --Outputs signal Devuelvo : std_logic; -- Clock period definitions constant clk_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Utilidad_RS232 PORT MAP ( clk => clk, Recibo => Recibo, Devuelvo => Devuelvo ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin ------------------------------------------------------------- -- Recibo un 11111111 con paridad 0 ------------------------------------------------------------- -- IDLE -- Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; -- BIT DE INICIO -- Recibo <= '0'; wait for 0.10416 ms; -- 8 BITS DE INFORMACION -- Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; -- BIT DE PARIDAD -- Recibo <= '0'; wait for 0.10416 ms; -- BIT DE PARADA -- Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; ------------------------------------------------------------- -- Recibo un 01111110 con paridad 1 MALO!!!!!! ------------------------------------------------------------- -- IDLE -- Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; -- BIT DE INICIO -- Recibo <= '0'; wait for 0.10416 ms; -- 8 BITS DE INFORMACION -- Recibo <= '0'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '0'; wait for 0.10416 ms; -- BIT DE PARIDAD -- Recibo <= '1'; wait for 0.10416 ms; -- BIT DE PARADA -- Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; ------------------------------------------------------------- -- Recibo un 10110110 con paridad 1 ------------------------------------------------------------- -- IDLE -- Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; -- BIT DE INICIO -- Recibo <= '0'; wait for 0.10416 ms; -- 8 BITS DE INFORMACION -- Recibo <= '1'; wait for 0.10416 ms; Recibo <= '0'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '0'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; Recibo <= '0'; wait for 0.10416 ms; -- BIT DE PARIDAD -- Recibo <= '1'; wait for 0.10416 ms; -- BIT DE PARADA -- Recibo <= '1'; wait for 0.10416 ms; Recibo <= '1'; wait for 0.10416 ms; wait; end process; END;
gpl-3.0
b1925a3010c5c7804f33172ee89e8931
0.455476
3.452297
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_pcc.vhd
1
105,202
------------------------------------------------------------------------------- -- axi_datamover_pcc.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_pcc.vhd -- -- Description: -- This file implements the DataMover Predictive Command Calculator (PCC). -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_pcc.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- -- DET 5/9/2011 Initial version for EDK 13.3 -- ~~~~~~ -- - Added Start Offset output port (mstr2dre_strt_offset) to support the -- new packing/unpacking functions in the Store and Forward modules. Also -- added the parameter C_STRT_SF_OFFSET_WIDTH to size the new port. -- - Added the C_IS_MM2S parameter to support MM2S DRE control via DRE -- Control port out. The Dest and SRC DRE alignemnts need to be swapped -- depending on a MM2S or S2MM instance. -- ^^^^^^ -- -- DET 6/20/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added 512 and 1024 data width support -- ^^^^^^ -- -- DET 6/23/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added expanded addressing support up to 64 bits -- ^^^^^^ -- -- DET 9/1/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Fixed Lint reported excesive line length for line 287. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_strb_gen2; ------------------------------------------------------------------------------- entity axi_datamover_pcc is generic ( C_IS_MM2S : Integer range 0 to 1 := 0; -- This parameter tells the PCC module if it is a MM2S -- instance or a S2MM instance. -- 0 = S2MM Instance -- 1 = MM2S Instance C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE Aligment output ports C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the LS address bus used for -- Muxing/Demuxing data to/from a wider AXI4 data bus C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the width of the AXi Address Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Stream Data width that -- is being supported by the PCC C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates the max allowed burst length to use for -- AXI4 transfer calculations C_CMD_WIDTH : Integer := 68; -- Sets the width of the input command port C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the input command C_BTT_USED : Integer range 8 to 23 := 16; -- Sets the width of the used portion of the BTT field -- of the input command C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates if the Indeterminate BTT mode is enabled C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32; -- Indicates the Native transfer width to use for all -- transfer calculations. This will either be the DataMover -- input Stream width or the AXI4 MMap data width depending -- on DataMover parameterization. C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 -- Indicates the width of the starting address offset -- bus passed to Store and Forward functions ); port ( -- Clock and Reset input ---------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------------- -- Master Command FIFO/Register Interface -------------------------------------------- -- cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- -- The next command value available from the Command FIFO/Register -- -- cache2mstr_command : in std_logic_vector(7 downto 0); -- -- The next command value available from the Command FIFO/Register -- cmd2mstr_cmd_valid : in std_logic; -- -- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry -- -- mst2cmd_cmd_ready : out std_logic; -- -- Handshake bit indicating the Command Calculator is ready to accept -- -- another command -- -------------------------------------------------------------------------------------- -- Address Channel Controller Interface ----------------------------------- -- mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : out std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- mstr2addr_size : out std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : out std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_user : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_cmd_cmplt : out std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calcualtion error -- -- mstr2addr_cmd_valid : out std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : In std_logic; -- -- Indication from the Address Channel Controller that the -- -- command is being accepted -- --------------------------------------------------------------------------- -- Data Channel Controller Interface ------------------------------------------------ -- mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap data -- -- width). -- -- mstr2data_len : out std_logic_vector(7 downto 0); -- -- The LEN value output to the Address Channel -- -- mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The starting strobe value to use for the data transfer -- -- mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The endiing (LAST) strobe value to use for the data transfer -- -- mstr2data_drr : out std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2data_eof : out std_logic; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2data_sequential : Out std_logic; -- -- The next sequential tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2data_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2data_cmd_cmplt : out std_logic; -- -- The indication to the Data Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2data_cmd_valid : out std_logic; -- -- The next command valid indication to the Data Channel -- -- Controller for the AXI MMap -- -- data2mstr_cmd_ready : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- command is being accepted on the AXI Address -- -- Channel -- -- mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the MM2S DRE -- -- mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the MM2S DRE -- ------------------------------------------------------------------------------------- -- Output flag indicating that a calculation error has occured ---------------------- -- calc_error : Out std_logic; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- ------------------------------------------------------------------------------------- -- Special DRE Controller Interface -------------------------------------------- -- dre2mstr_cmd_ready : In std_logic ; -- -- Indication from the S2MM DRE Controller that it can -- -- accept another command. -- -- mstr2dre_cmd_valid : out std_logic ; -- -- The next command valid indication to the S2MM DRE -- -- Controller. -- -- mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The source (S2MM Stream) alignment for the S2MM DRE -- -- mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The destinstion (S2MM MMap) alignment for the S2MM DRE -- -- mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; -- -- The BTT value output to the S2MM DRE. This is needed for -- -- Scatter operations. -- -- mstr2dre_drr : out std_logic ; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : out std_logic ; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2dre_cmd_cmplt : Out std_logic ; -- -- The last child tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : out std_logic ; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- ------------------------------------------------------------------------------------- -- Store and Forward Support Start Offset --------------------------------------------- -- mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) -- -- Relays the starting address offset for a transfer to the Store and Forward -- -- functions incorporating upsizer/downsizer logic -- --------------------------------------------------------------------------------------- ); end entity axi_datamover_pcc; architecture implementation of axi_datamover_pcc is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declarations ------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_dbeat_residue_width -- -- Function Description: -- Calculates the number of Least significant bits of the BTT field -- that are unused for the LEN calculation -- ------------------------------------------------------------------- function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream begin case bytes_per_beat is when 1 => temp_dbeat_residue_width := 0; when 2 => temp_dbeat_residue_width := 1; when 4 => temp_dbeat_residue_width := 2; when 8 => temp_dbeat_residue_width := 3; when 16 => temp_dbeat_residue_width := 4; when 32 => temp_dbeat_residue_width := 5; when 64 => temp_dbeat_residue_width := 6; when others => -- 128-byte transfers temp_dbeat_residue_width := 7; end case; Return (temp_dbeat_residue_width); end function funct_get_dbeat_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_burstcnt_offset -- -- Function Description: -- Calculates the bit offset from the residue bits needed to detirmine -- the load value for the burst counter. -- ------------------------------------------------------------------- function funct_get_burst_residue_width (max_burst_len : integer) return integer is Variable temp_burst_residue_width : Integer := 0; begin case max_burst_len is when 256 => temp_burst_residue_width := 8; when 128 => temp_burst_residue_width := 7; when 64 => temp_burst_residue_width := 6; when 32 => temp_burst_residue_width := 5; when 16 => temp_burst_residue_width := 4; when 8 => temp_burst_residue_width := 3; when 4 => temp_burst_residue_width := 2; when others => -- assume 2 dbeats temp_burst_residue_width := 1; end case; Return (temp_burst_residue_width); end function funct_get_burst_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_axi_size -- -- Function Description: -- Calculates the AXI SIZE Qualifier based on the data width. -- ------------------------------------------------------------------- function func_get_axi_size (native_dwidth : integer) return std_logic_vector is Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000"; Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001"; Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010"; Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011"; Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100"; Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101"; Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110"; Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111"; Variable temp_size : std_logic_vector(2 downto 0) := (others => '0'); begin case native_dwidth is when 8 => temp_size := AXI_SIZE_1BYTE; when 16 => temp_size := AXI_SIZE_2BYTE; when 32 => temp_size := AXI_SIZE_4BYTE; when 64 => temp_size := AXI_SIZE_8BYTE; when 128 => temp_size := AXI_SIZE_16BYTE; when 256 => temp_size := AXI_SIZE_32BYTE; when 512 => temp_size := AXI_SIZE_64BYTE; when others => -- 1024 bit dwidth temp_size := AXI_SIZE_128BYTE; end case; Return (temp_size); end function func_get_axi_size; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_ls_index -- -- Function Description: -- Calculates the Ls index of the Store and Forward -- starting offset bus based on the User Stream Width. -- ------------------------------------------------------------------- function funct_get_sf_offset_ls_index (stream_width : integer) return integer is Variable lvar_temp_ls_index : Integer := 0; begin case stream_width is when 8 => lvar_temp_ls_index := 0; when 16 => lvar_temp_ls_index := 1; when 32 => lvar_temp_ls_index := 2; when 64 => lvar_temp_ls_index := 3; when 128 => lvar_temp_ls_index := 4; when 256 => lvar_temp_ls_index := 5; when 512 => lvar_temp_ls_index := 6; when others => -- 1024 lvar_temp_ls_index := 7; end case; Return (lvar_temp_ls_index); end function funct_get_sf_offset_ls_index; -- Constant Declarations ---------------------------------------- Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address) Constant CMD_BTT_WIDTH : integer := C_BTT_USED; Constant CMD_BTT_LS_INDEX : integer := 0; Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1; Constant CMD_TYPE_INDEX : integer := 23; Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1; Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2; Constant CMD_DSA_WIDTH : integer := 6; Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1; Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1; Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH; Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1; Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH; Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH; Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1; ---------------------------------------------------------------------------------------- -- Command calculation constants Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH); Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8; Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN; Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT; Constant LEN_WIDTH : integer := 8; -- 8 bits fixed Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1; Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT); Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN); Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH; Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH); Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH); Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH); Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH); Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH); Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH; Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH); Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH); Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH); Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH); Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1; -- Type Declarations -------------------------------------------- type PCC_SM_STATE_TYPE is ( INIT, WAIT_FOR_CMD, CALC_1, CALC_2, CALC_3, WAIT_ON_XFER_PUSH, CHK_IF_DONE, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT; Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT; signal sig_sm_halt_ns : std_logic := '0'; signal sig_sm_halt_reg : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0'; signal sig_sm_pop_input_reg_ns : std_logic := '0'; signal sig_sm_pop_input_reg : std_logic := '0'; signal sig_sm_ld_calc1_reg_ns : std_logic := '0'; signal sig_sm_ld_calc1_reg : std_logic := '0'; signal sig_sm_ld_calc2_reg_ns : std_logic := '0'; signal sig_sm_ld_calc2_reg : std_logic := '0'; signal sig_sm_ld_calc3_reg_ns : std_logic := '0'; signal sig_sm_ld_calc3_reg : std_logic := '0'; signal sig_parent_done : std_logic := '0'; signal sig_ld_xfer_reg : std_logic := '0'; signal sig_ld_xfer_reg_tmp : std_logic := '0'; signal sig_btt_raw : std_logic := '0'; signal sig_btt_is_zero : std_logic := '0'; signal sig_btt_is_zero_reg : std_logic := '0'; -- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0'); -- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0'); -- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); -- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); ---------------------------------------------------------------------------------------- -- Burst Buster signals signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_last_xfer_valid_im1 : std_logic := '0'; signal sig_brst_cnt_eq_zero_im0 : std_logic := '0'; signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0'; signal sig_brst_cnt_eq_one_im0 : std_logic := '0'; signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0'; signal sig_brst_residue_eq_zero : std_logic := '0'; signal sig_brst_residue_eq_zero_reg : std_logic := '0'; signal sig_no_btt_residue_im0 : std_logic := '0'; signal sig_no_btt_residue_ireg1 : std_logic := '0'; signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); -- Input command register signal sig_push_input_reg : std_logic := '0'; signal sig_pop_input_reg : std_logic := '0'; signal sig_input_burst_type_reg : std_logic := '0'; signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_input_drr_reg : std_logic := '0'; signal sig_input_eof_reg : std_logic := '0'; signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_input_reg_empty : std_logic := '0'; signal sig_input_reg_full : std_logic := '0'; -- Output qualifier Register -- signal sig_ld_output : std_logic := '0'; signal sig_push_xfer_reg : std_logic := '0'; signal sig_pop_xfer_reg : std_logic := '0'; signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_type_reg : std_logic := '0'; signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_drr_reg : std_logic := '0'; signal sig_xfer_eof_reg : std_logic := '0'; signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_is_seq_reg : std_logic := '0'; signal sig_xfer_cmd_cmplt_reg : std_logic := '0'; signal sig_xfer_calc_err_reg : std_logic := '0'; signal sig_xfer_reg_empty : std_logic := '0'; signal sig_xfer_reg_full : std_logic := '0'; -- Address Counter signal sig_ld_addr_cntr : std_logic := '0'; signal sig_incr_addr_cntr : std_logic := '0'; signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); -- misc signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0); signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_type_slice : std_logic := '0'; signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_drr_slice : std_logic := '0'; signal sig_cmd_eof_slice : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_calc_error_pushed : std_logic := '0'; -- PCC2 stuff signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_im2 : std_logic := '0'; signal sig_first_xfer_im0 : std_logic := '0'; signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover : std_logic := '0'; signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_ld_btt_cntr : std_logic := '0'; signal sig_decr_btt_cntr : std_logic := '0'; signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2data_valid : std_logic := '0'; signal sig_clr_cmd2data_valid : std_logic := '0'; signal sig_cmd2addr_valid : std_logic := '0'; signal sig_clr_cmd2addr_valid : std_logic := '0'; signal sig_btt_lt_b2mbaa_im0 : std_logic := '0'; signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0'; signal sig_btt_eq_b2mbaa_im0 : std_logic := '0'; signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0'; signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0'; -- Unaligned start address support signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_aligned_im0 : std_logic := '0'; signal sig_addr_aligned_ireg1 : std_logic := '0'; -- S2MM DRE Support signal sig_cmd2dre_valid : std_logic := '0'; signal sig_clr_cmd2dre_valid : std_logic := '0'; signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dre_eof_reg : std_logic := '0'; -- Long Timing path breakup intermediate registers signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_ireg3 : std_logic := '0'; signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover_im3 : std_logic := '0'; signal sig_mmap_reset_reg : std_logic := '0'; ---------------------------------------------------------- begin --(architecture implementation) -- Assign calculation error output calc_error <= sig_calc_error_reg; -- Assign the ready output to the Command FIFO mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and sig_input_reg_empty and not(sig_calc_error_pushed); -- Assign the Address Channel Controller Qualifiers mstr2addr_tag <= sig_xfer_tag_reg ; mstr2addr_addr <= sig_xfer_addr_reg; mstr2addr_len <= sig_xfer_len_reg ; mstr2addr_size <= sig_xfer_size ; mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported mstr2addr_cmd_valid <= sig_cmd2addr_valid; mstr2addr_calc_error <= sig_xfer_calc_err_reg; mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Assign the Data Channel Controller Qualifiers mstr2data_tag <= sig_xfer_tag_reg ; mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0); mstr2data_len <= sig_xfer_len_reg ; mstr2data_strt_strb <= sig_xfer_strt_strb_reg; mstr2data_last_strb <= sig_xfer_end_strb_reg ; mstr2data_drr <= sig_xfer_drr_reg ; mstr2data_eof <= sig_xfer_eof_reg ; mstr2data_sequential <= sig_xfer_is_seq_reg ; mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; mstr2data_cmd_valid <= sig_cmd2data_valid ; mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_calc_error <= sig_xfer_calc_err_reg ; -- Assign the DRE Controller Qualifiers mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE ------------------------------------------------------------ -- If Generate -- -- Label: DO_MM2S_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the MM2S use case. -- ------------------------------------------------------------ DO_MM2S_CASE : if (C_IS_MM2S = 1) generate begin mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE end generate DO_MM2S_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: DO_S2MM_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the S2MM use case. -- ------------------------------------------------------------ DO_S2MM_CASE : if (C_IS_MM2S = 0) generate begin mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE end generate DO_S2MM_CASE; -- Store and Forward Support Start Offset (used by Packer/Unpacker logic) mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX); -- Start internal logic. -- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines) sig_cmd_user_slice <= cache2mstr_command(7 downto 4); sig_cmd_cache_slice <= cache2mstr_command(3 downto 0); sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX); sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX); sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX); sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX); sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX); sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX); -- Check for a zero length BTT (error condition) sig_btt_is_zero <= '1' when (sig_cmd_btt_slice = BTT_ZEROS) Else '0'; sig_xfer_size <= SIZE_TO_USE; ----------------------------------------------------------------- -- Reset fanout control ----------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RESET_REG -- -- Process Description: -- Registers the input reset to reduce fanout. This module -- has a high number of register bits to reset. -- ------------------------------------------------------------- IMP_RESET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_reset_reg <= mmap_reset; end if; end process IMP_RESET_REG; ----------------------------------------------------------------- -- Input xfer register design sig_push_input_reg <= not(sig_sm_halt_reg) and cmd2mstr_cmd_valid and sig_input_reg_empty and not(sig_calc_error_reg); sig_pop_input_reg <= sig_sm_pop_input_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_INPUT_QUAL -- -- Process Description: -- Implements the input command qualifier holding register -- ------------------------------------------------------------- REG_INPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_input_reg = '1' or sig_calc_error_pushed = '1') then sig_input_cache_type_reg <= (others => '0'); sig_input_user_type_reg <= (others => '0'); sig_input_burst_type_reg <= '0'; sig_input_tag_reg <= (others => '0'); sig_input_dsa_reg <= (others => '0'); sig_input_drr_reg <= '0'; sig_input_eof_reg <= '0'; sig_input_reg_empty <= '1'; sig_input_reg_full <= '0'; elsif (sig_push_input_reg = '1') then sig_input_cache_type_reg <= sig_cmd_cache_slice; sig_input_user_type_reg <= sig_cmd_user_slice; sig_input_burst_type_reg <= sig_cmd_type_slice; sig_input_tag_reg <= sig_cmd_tag_slice; sig_input_dsa_reg <= sig_cmd_dsa_slice; sig_input_drr_reg <= sig_cmd_drr_slice; sig_input_eof_reg <= sig_cmd_eof_slice; sig_input_reg_empty <= '0'; sig_input_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_INPUT_QUAL; ---------------------------------------------------------------------- -- Calculation Error Logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_FLOP -- -- Process Description: -- Implements the flop for the Calc Error flag, Once set, -- the flag cannot be cleared until a reset is issued. -- ------------------------------------------------------------- IMP_CALC_ERROR_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_reg <= '0'; elsif (sig_push_input_reg = '1' and sig_calc_error_reg = '0') then sig_calc_error_reg <= sig_btt_is_zero; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_PUSHED -- -- Process Description: -- Implements the flop for generating a flag indicating the -- calculation error flag has been pushed to the addr and data -- controllers. -- ------------------------------------------------------------- IMP_CALC_ERROR_PUSHED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_pushed <= '0'; elsif (sig_push_xfer_reg = '1' and sig_calc_error_pushed = '0') then sig_calc_error_pushed <= sig_calc_error_reg; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_PUSHED; --------------------------------------------------------------------- -- Strobe Generator Logic sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3 When (sig_first_xfer_im0 = '1') Else (others => '1'); sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3 When (sig_xfer_len_eq_0_ireg3 = '1' and sig_first_xfer_im0 = '1') else sig_xfer_end_strb_ireg3 When (sig_last_xfer_valid_im1 = '1') Else (others => '1'); ---------------------------------------------------------- -- Intermediate registers for STBGEN Fmax path ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_REGS -- -- Process Description: -- Intermediate registers for Strobegen inputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_strbgen_addr_ireg2 <= (others => '0'); sig_strbgen_bytes_ireg2 <= (others => '0'); sig_finish_addr_offset_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ; sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ; sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_REGS; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_OUT_REGS -- -- Process Description: -- Intermediate registers for Strobegen outputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_OUT_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_xfer_strt_strb_ireg3 <= (others => '0'); sig_xfer_end_strb_ireg3 <= (others => '0'); sig_xfer_len_eq_0_ireg3 <= '0'; elsif (sig_sm_ld_calc3_reg = '1') then sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2; sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ; sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_OUT_REGS; ------------------------------------------------------------ -- Instance: I_STRT_STRB_GEN -- -- Description: -- Strobe generator instance. Generates strobe bits for -- a designated starting byte lane and the number of bytes -- to be transfered (for that data beat). -- ------------------------------------------------------------ I_STRT_STRB_GEN : entity axi_datamover_v5_1.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 0 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1 ) port map ( start_addr_offset => sig_strbgen_addr_ireg2 , end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0 num_valid_bytes => sig_strbgen_bytes_ireg2 , strb_out => sig_xfer_strt_strb_im2 ); -- The ending address offset is 1 less than the calculated -- starting address for the next sequential transfer. sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) - STRBGEN_ADDR_SLICE_1); ------------------------------------------------------------ -- Instance: I_END_STRB_GEN -- -- Description: -- End Strobe generator instance. Generates asserted strobe -- bits from byte offset 0 to the ending byte offset. -- ------------------------------------------------------------ I_END_STRB_GEN : entity axi_datamover_v5_1.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 1 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ) port map ( start_addr_offset => STRBGEN_ADDR_0 , end_addr_offset => sig_last_addr_offset_im2 , num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1 strb_out => sig_xfer_end_strb_im2 ); ----------------------------------------------------------------- -- Output xfer register design sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty); -- Data taking xfer after Addr and DRE sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or -- Addr taking xfer after Data and DRE (sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or -- DRE taking xfer after Data and ADDR (sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or -- data and Addr taking xfer after DRE (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or -- Addr and DRE taking xfer after Data (sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or -- Data and DRE taking xfer after Addr (sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or -- Addr, Data, and DRE all taking xfer (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_OUTPUT_QUAL -- -- Process Description: -- Implements the output xfer qualifier holding register -- ------------------------------------------------------------- REG_OUTPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or (sig_pop_xfer_reg = '1' and sig_push_xfer_reg = '0')) then -- sig_xfer_cache_reg <= (others => '0'); -- sig_xfer_user_reg <= (others => '0'); -- sig_xfer_addr_reg <= (others => '0'); -- sig_xfer_type_reg <= '0'; -- sig_xfer_len_reg <= (others => '0'); -- sig_xfer_tag_reg <= (others => '0'); -- sig_xfer_dsa_reg <= (others => '0'); -- sig_xfer_drr_reg <= '0'; -- sig_xfer_eof_reg <= '0'; -- sig_xfer_strt_strb_reg <= (others => '0'); -- sig_xfer_end_strb_reg <= (others => '0'); -- sig_xfer_is_seq_reg <= '0'; -- sig_xfer_cmd_cmplt_reg <= '0'; -- sig_xfer_calc_err_reg <= '0'; -- sig_xfer_btt_reg <= (others => '0'); -- sig_xfer_dre_eof_reg <= '0'; sig_xfer_reg_empty <= '1'; sig_xfer_reg_full <= '0'; elsif (sig_push_xfer_reg = '1') then -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else -- sig_xfer_addr_reg <= sig_xfer_address_im0 ; -- end if; -- sig_xfer_type_reg <= sig_input_burst_type_reg ; -- sig_xfer_cache_reg <= sig_input_cache_type_reg ; -- sig_xfer_user_reg <= sig_input_user_type_reg ; -- sig_xfer_len_reg <= sig_xfer_len_im2 ; -- sig_xfer_tag_reg <= sig_input_tag_reg ; -- sig_xfer_dsa_reg <= sig_input_dsa_reg ; -- sig_xfer_drr_reg <= sig_input_drr_reg and -- sig_first_xfer_im0 ; -- sig_xfer_eof_reg <= sig_input_eof_reg and -- sig_last_xfer_valid_im1 ; -- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; -- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; -- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; -- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or -- sig_calc_error_reg ; -- sig_xfer_calc_err_reg <= sig_calc_error_reg ; -- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; -- sig_xfer_dre_eof_reg <= sig_input_eof_reg ; sig_xfer_reg_empty <= '0'; sig_xfer_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_OUTPUT_QUAL; -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else sig_addr_cntr_lsh_kh ; -- end if; sig_xfer_type_reg <= sig_input_burst_type_reg ; sig_xfer_cache_reg <= sig_input_cache_type_reg ; sig_xfer_user_reg <= sig_input_user_type_reg ; sig_xfer_len_reg <= sig_xfer_len_im2 ; sig_xfer_tag_reg <= sig_input_tag_reg ; sig_xfer_dsa_reg <= sig_input_dsa_reg ; sig_xfer_drr_reg <= sig_input_drr_reg and sig_first_xfer_im0 ; sig_xfer_eof_reg <= sig_input_eof_reg and sig_last_xfer_valid_im1 ; sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or sig_calc_error_reg ; sig_xfer_calc_err_reg <= sig_calc_error_reg ; sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; sig_xfer_dre_eof_reg <= sig_input_eof_reg ; -------------------------------------------------------------- -- BTT Counter Logic sig_ld_btt_cntr <= sig_ld_addr_cntr; -- sig_decr_btt_cntr <= sig_incr_addr_cntr; -- above signal is using the incr_addr_cntr signal and hence cannot be -- used if burst type is Fixed sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_CNTR -- -- Process Description: -- Bytes to transfer counter implementation. -- ------------------------------------------------------------- IMP_BTT_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_btt_cntr_im0 <= (others => '0'); elsif (sig_ld_btt_cntr = '1') then sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice); Elsif (sig_decr_btt_cntr = '1') Then sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH); else null; -- hold current state end if; end if; end process IMP_BTT_CNTR; -- Convert to logic vector for the S2MM DRE use -- The DRE will only use this value prior to the first -- decrement of the BTT Counter. Using this saves a separate -- BTT register. sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0); -- Rip the Burst Count slice from BTT counter value sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX); sig_brst_cnt_eq_zero_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_0) Else '0'; sig_brst_cnt_eq_one_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_1) Else '0'; -- Rip the BTT residue field from the BTT counter value sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0); -- Check for transfer length residue of zero prior to subtracting 1 sig_no_btt_residue_im0 <= '1' when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Unaligned address compensation -- Add the number of starting address offset byte positions to the -- final byte change value needed to calculate the AXI LEN field sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0); sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 + RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH); -- adjust the address increment down by 1 byte to compensate -- for the LEN requirement of being N-1 data beats sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE; -- Rip the new transfer length value sig_xfer_len_im2 <= STD_LOGIC_VECTOR( RESIZE( sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto DBEAT_RESIDUE_WIDTH), LEN_WIDTH) ); -- Check to see if the new xfer length is zero (1 data beat) sig_xfer_len_eq_0_im2 <= '1' when (sig_xfer_len_im2 = XFER_LEN_ZERO) Else '0'; -- Check for Last transfer condition --sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and --sig_no_btt_residue_im0 and sig_no_btt_residue_ireg1 and -- sig_addr_aligned_im0) or -- always the last databeat case sig_addr_aligned_ireg1) or -- always the last databeat case -- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining ((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining -- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0))); (sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1))); ---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------- -- -- General Address Counter Logic (applies to any address width of 32 or greater -- The address counter is divided into 2 16-bit segements for 32-bit address support. As the -- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit -- addressing. -- ---------------------------------------------------------------------------------------------------- -- Rip the LS bits of the LS Address Counter for the StrobeGen -- starting address offset sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); -- Check if the calcualted address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat sig_addr_incr_ge_bpdb_im1 <= '1' When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH)) Else '0'; -- If the calculated address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat, then clip the -- strobegen byte value to the number of bytes per data beat, else use the -- increment value. sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1)) when (sig_addr_incr_ge_bpdb_im1 = '1') else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0)); -------------------------------------------------------------------------- -- Address Counter logic sig_ld_addr_cntr <= sig_push_input_reg; -- don't increment address cntr if type is '0' (non-incrementing) sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and -- sig_input_burst_type_reg; sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0); sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) - RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH); sig_addr_aligned_im0 <= '1' when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less -- than or equal to the remaining bytes to transfer. If it is, then at least -- two tranfers have to be scheduled. sig_btt_lt_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; sig_btt_eq_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_REG1 -- -- Process Description: -- Intermediate register stage 1 for Address Counter -- derivative calculations. -- ------------------------------------------------------------- IMP_IM_REG1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_bytes_to_mbaa_ireg1 <= (others => '0'); sig_addr_aligned_ireg1 <= '0' ; sig_btt_lt_b2mbaa_ireg1 <= '0' ; sig_btt_eq_b2mbaa_ireg1 <= '0' ; sig_brst_cnt_eq_zero_ireg1 <= '0' ; sig_brst_cnt_eq_one_ireg1 <= '0' ; sig_no_btt_residue_ireg1 <= '0' ; elsif (sig_sm_ld_calc1_reg = '1') then sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ; sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ; sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ; sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ; sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0; sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ; sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ; else null; -- hold state end if; end if; end process IMP_IM_REG1; -- Select the address counter increment value to use sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) --When (sig_btt_lt_b2mbaa_im0 = '1') When (sig_btt_lt_b2mbaa_ireg1 = '1') --else sig_bytes_to_mbaa_im0 else sig_bytes_to_mbaa_ireg1 when (sig_first_xfer_im0 = '1') else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH); -- calculate the next starting address after the current -- xfer completes sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1; -- Predict next transfer's address offset for the Strobe Generator sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- Determine if an address count lsh rollover is going to occur when -- jumping to the next starting address by comparing the MS bit of the -- current address lsh to the MS bit of the predicted address lsh . -- A transition of a '1' to a '0' is a rollover. sig_addr_lsh_rollover_im3 <= '1' when ( (sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and (sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0') ) Else '0'; ---------------------------------------------------------- -- Intermediate registers for reducing the Address Counter -- Increment timing path ---------------------------------------------------------- -- calculate the next starting address after the current -- xfer completes using intermediate register values sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2; sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_ADDRINC_REG -- -- Process Description: -- Intermediate registers for address counter increment to -- break long timing paths. -- ------------------------------------------------------------- IMP_IM_ADDRINC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1; else null; -- hold state end if; end if; end process IMP_IM_ADDRINC_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_PREDICT_ADDR_REG -- -- Process Description: -- Intermediate register for predicted address to break up -- long timing paths. -- ------------------------------------------------------------- IMP_IM_PREDICT_ADDR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_predict_addr_lsh_ireg3 <= (others => '0'); elsif (sig_sm_ld_calc3_reg = '1') then sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2; else null; -- hold state end if; end if; end process IMP_IM_PREDICT_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_ADDR_STUFF -- -- Process Description: -- Implements a general register for address counter related -- things. -- ------------------------------------------------------------- REG_ADDR_STUFF : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_adjusted_addr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1; else null; -- hold state end if; end if; end process REG_ADDR_STUFF; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_LSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_LSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_lsh_im0 <= (others => '0'); sig_addr_cntr_lsh_kh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0)); sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice; Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3; else null; -- hold current state end if; end if; end process IMP_LSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_MSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_im0_msh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1') then sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE; else null; -- hold current state end if; end if; end process IMP_MSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIRST_XFER_FLOP -- -- Process Description: -- Implements the register flop for the first transfer flag. -- ------------------------------------------------------------- IMP_FIRST_XFER_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_incr_addr_cntr = '1') then sig_first_xfer_im0 <= '0'; elsif (sig_ld_addr_cntr = '1') then sig_first_xfer_im0 <= '1'; else null; -- hold current state end if; end if; end process IMP_FIRST_XFER_FLOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_32 -- -- If Generate Description: -- Implements the Address segment merge logic for the 32-bit -- address width case. The address counter segments are split -- into two 16-bit sections to improve Fmax convergence. -- -- ------------------------------------------------------------ GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate begin -- Populate the transfer address value by concatonating the -- address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); end generate GEN_ADDR_32; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_32_LE_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 32 bits and less than -- or equal to 48 bits. In this case, an additional counter segment -- is implemented (segment 3) that is variable width of 1 -- to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and C_ADDR_WIDTH <= 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; begin -- Populate the transfer address value by concatonating the -- 3 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Adress Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter MSH (Segment 2) is at max value and will rollover -- at the next increment interval for the counter. Registering -- this signal and using it for the Seg 3 increment logic only -- works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 counter to go to -- max and the next increment operation that can bump segment 3. -- ------------------------------------------------------------- IMP_SEG2_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; end if; end if; end process IMP_SEG2_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; end generate GEN_ADDR_GT_32_LE_48; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 48 bits and less than -- or equal to 64. In this case, an additional 2 counter segments -- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits -- and segment 4 is variable width of 1 to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48; Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH); Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; signal lsig_acntr_seg3_eq_max : std_logic := '0'; signal lsig_acntr_seg3_eq_max_reg : std_logic := '0'; signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0'); begin -- Populate the transfer address value by concatonating the -- 4 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) & STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Address Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; -- See if the Segment 3 of the Address Counter is at a max value lsig_acntr_seg3_eq_max <= '1' when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_3_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter segments 2 and 3 are at max value and will rollover -- at the next increment interval for the counter. Registering -- these signals and using themt for the Seg 3/4 increment logic -- only works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 or 3 counter to go -- to max and the next increment operation. -- ------------------------------------------------------------- IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; lsig_acntr_seg3_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max; end if; end if; end process IMP_SEG2_3_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG4_ADDR_CNTR -- -- Process Description: -- Segment 4 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG4_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg4_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto SEG4_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1' and lsig_acntr_seg3_eq_max_reg = '1') then lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE; else null; -- hold current state end if; end if; end process IMP_SEG4_ADDR_CNTR; end generate GEN_ADDR_GT_48; -- Addr and data Cntlr FIFO interface handshake logic ------------------------------ sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready; sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready; sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DATA_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Data Controller Module. -- ------------------------------------------------------------- CMD2DATA_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2data_valid = '1') then sig_cmd2data_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2data_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DATA_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2ADDR_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Address Controller Module. -- ------------------------------------------------------------- CMD2ADDR_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2addr_valid = '1') then sig_cmd2addr_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2addr_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2ADDR_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DRE_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the DRE Module (S2MM DRE Only). -- -- Note that the S2MM DRE only needs to be loaded with a command -- for each parent command, not every child command. -- ------------------------------------------------------------- CMD2DRE_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2dre_valid = '1') then sig_cmd2dre_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1' and sig_first_xfer_im0 = '1') then sig_cmd2dre_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DRE_VALID_FLOP; ------------------------------------------------------------------------- -- PCC State machine Logic ------------------------------------------------------------- -- Combinational Process -- -- Label: PCC_SM_COMBINATIONAL -- -- Process Description: -- PCC State Machine combinational implementation -- ------------------------------------------------------------- PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state , sig_parent_done , sig_push_input_reg , sig_pop_xfer_reg , sig_calc_error_pushed) begin -- SM Defaults sig_pcc_sm_state_ns <= INIT; sig_sm_halt_ns <= '0'; sig_sm_ld_xfer_reg_ns <= '0'; sig_sm_pop_input_reg_ns <= '0'; sig_sm_ld_calc1_reg_ns <= '0'; sig_sm_ld_calc2_reg_ns <= '0'; sig_sm_ld_calc3_reg_ns <= '0'; case sig_pcc_sm_state is -------------------------------------------- when INIT => sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_halt_ns <= '1'; -------------------------------------------- when WAIT_FOR_CMD => If (sig_push_input_reg = '1') Then sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; else sig_pcc_sm_state_ns <= WAIT_FOR_CMD; End if; -------------------------------------------- when CALC_1 => sig_pcc_sm_state_ns <= CALC_2; sig_sm_ld_calc2_reg_ns <= '1'; -------------------------------------------- when CALC_2 => sig_pcc_sm_state_ns <= CALC_3; sig_sm_ld_calc3_reg_ns <= '1'; -------------------------------------------- when CALC_3 => sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; sig_sm_ld_xfer_reg_ns <= '1'; -------------------------------------------- when WAIT_ON_XFER_PUSH => if (sig_pop_xfer_reg = '1') then sig_pcc_sm_state_ns <= CHK_IF_DONE; else -- wait until output register is loaded sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; end if; -------------------------------------------- when CHK_IF_DONE => If (sig_calc_error_pushed = '1') then -- Internal error, go to trap sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; elsif (sig_parent_done = '1') Then -- done with parent command sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_pop_input_reg_ns <= '1'; else -- Still breaking up parent command sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; end if; -------------------------------------------- when ERROR_TRAP => sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; -------------------------------------------- when others => sig_pcc_sm_state_ns <= INIT; end case; end process PCC_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PCC_SM_REGISTERED -- -- Process Description: -- PCC State Machine registered implementation -- ------------------------------------------------------------- PCC_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_pcc_sm_state <= INIT; sig_sm_halt_reg <= '1' ; sig_sm_pop_input_reg <= '0' ; sig_sm_ld_calc1_reg <= '0' ; sig_sm_ld_calc2_reg <= '0' ; sig_sm_ld_calc3_reg <= '0' ; else sig_pcc_sm_state <= sig_pcc_sm_state_ns ; sig_sm_halt_reg <= sig_sm_halt_ns ; sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns; sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ; sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ; sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ; end if; end if; end process PCC_SM_REGISTERED; ------------------------------------------------------------------ -- Transfer Register Load Enable logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: LD_XFER_REG_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- LD_XFER_REG_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_xfer_reg = '1') then sig_ld_xfer_reg <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP; LD_XFER_REG_FLOP1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_xfer_reg = '1') then sig_ld_xfer_reg_tmp <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg_tmp <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP1; ------------------------------------------------------------------ -- Parent Done flag logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PARENT_DONE_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- PARENT_DONE_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_input_reg = '1') then sig_parent_done <= '0'; Elsif (sig_ld_xfer_reg_tmp = '1') Then sig_parent_done <= sig_last_xfer_valid_im1; else null; -- hold current state end if; end if; end process PARENT_DONE_FLOP; end implementation;
bsd-2-clause
1c671df6f71d51384a80fe47d7587b23
0.457111
4.279461
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/block/block_test_input.vhd
1
501
entity BLOCK_EXAMPLE is end entity BLOCK_EXAMPLE; architecture RTL of BLOCK_EXAMPLE is begin -- correct block format BLK : block is signal private : integer; type int_array is array (natural range <>) of integer; constant vals : int_array(1 downto 0) := ( 3, 10 ); begin private <= vals(1); U_INST1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end block BLK; end architecture RTL;
gpl-3.0
28f2c170e215ad02e8424373be867d81
0.58483
3.455172
false
false
false
false
cwilkens/ecen4024-microphone-array
microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/dec_scaler.vhd
1
9,914
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mit
8ac06ed231f605c7ebc0db0cb0487350
0.925661
1.911317
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/sim/daala_zynq_axi_dma_0_0.vhd
1
24,572
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_dma:7.1 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_dma_v7_1; USE axi_dma_v7_1.axi_dma; ENTITY daala_zynq_axi_dma_0_0 IS PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axi_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; mm2s_prmry_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awvalid : OUT STD_LOGIC; m_axi_s2mm_awready : IN STD_LOGIC; m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_wlast : OUT STD_LOGIC; m_axi_s2mm_wvalid : OUT STD_LOGIC; m_axi_s2mm_wready : IN STD_LOGIC; m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; s_axis_s2mm_tlast : IN STD_LOGIC; mm2s_introut : OUT STD_LOGIC; s2mm_introut : OUT STD_LOGIC; axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END daala_zynq_axi_dma_0_0; ARCHITECTURE daala_zynq_axi_dma_0_0_arch OF daala_zynq_axi_dma_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF daala_zynq_axi_dma_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_dma IS GENERIC ( C_S_AXI_LITE_ADDR_WIDTH : INTEGER; C_S_AXI_LITE_DATA_WIDTH : INTEGER; C_DLYTMR_RESOLUTION : INTEGER; C_PRMRY_IS_ACLK_ASYNC : INTEGER; C_ENABLE_MULTI_CHANNEL : INTEGER; C_NUM_MM2S_CHANNELS : INTEGER; C_NUM_S2MM_CHANNELS : INTEGER; C_INCLUDE_SG : INTEGER; C_SG_INCLUDE_STSCNTRL_STRM : INTEGER; C_SG_USE_STSAPP_LENGTH : INTEGER; C_SG_LENGTH_WIDTH : INTEGER; C_M_AXI_SG_ADDR_WIDTH : INTEGER; C_M_AXI_SG_DATA_WIDTH : INTEGER; C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER; C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER; C_MICRO_DMA : INTEGER; C_INCLUDE_MM2S : INTEGER; C_INCLUDE_MM2S_DRE : INTEGER; C_INCLUDE_MM2S_SF : INTEGER; C_MM2S_BURST_SIZE : INTEGER; C_M_AXI_MM2S_ADDR_WIDTH : INTEGER; C_M_AXI_MM2S_DATA_WIDTH : INTEGER; C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER; C_INCLUDE_S2MM : INTEGER; C_INCLUDE_S2MM_DRE : INTEGER; C_INCLUDE_S2MM_SF : INTEGER; C_S2MM_BURST_SIZE : INTEGER; C_M_AXI_S2MM_ADDR_WIDTH : INTEGER; C_M_AXI_S2MM_DATA_WIDTH : INTEGER; C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER; C_FAMILY : STRING ); PORT ( s_axi_lite_aclk : IN STD_LOGIC; m_axi_sg_aclk : IN STD_LOGIC; m_axi_mm2s_aclk : IN STD_LOGIC; m_axi_s2mm_aclk : IN STD_LOGIC; axi_resetn : IN STD_LOGIC; s_axi_lite_awvalid : IN STD_LOGIC; s_axi_lite_awready : OUT STD_LOGIC; s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); s_axi_lite_wvalid : IN STD_LOGIC; s_axi_lite_wready : OUT STD_LOGIC; s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_lite_bvalid : OUT STD_LOGIC; s_axi_lite_bready : IN STD_LOGIC; s_axi_lite_arvalid : IN STD_LOGIC; s_axi_lite_arready : OUT STD_LOGIC; s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0); s_axi_lite_rvalid : OUT STD_LOGIC; s_axi_lite_rready : IN STD_LOGIC; s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_awvalid : OUT STD_LOGIC; m_axi_sg_awready : IN STD_LOGIC; m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_wlast : OUT STD_LOGIC; m_axi_sg_wvalid : OUT STD_LOGIC; m_axi_sg_wready : IN STD_LOGIC; m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_bvalid : IN STD_LOGIC; m_axi_sg_bready : OUT STD_LOGIC; m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_sg_arvalid : OUT STD_LOGIC; m_axi_sg_arready : IN STD_LOGIC; m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_sg_rlast : IN STD_LOGIC; m_axi_sg_rvalid : IN STD_LOGIC; m_axi_sg_rready : OUT STD_LOGIC; m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_mm2s_arvalid : OUT STD_LOGIC; m_axi_mm2s_arready : IN STD_LOGIC; m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_mm2s_rlast : IN STD_LOGIC; m_axi_mm2s_rvalid : IN STD_LOGIC; m_axi_mm2s_rready : OUT STD_LOGIC; mm2s_prmry_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_mm2s_tvalid : OUT STD_LOGIC; m_axis_mm2s_tready : IN STD_LOGIC; m_axis_mm2s_tlast : OUT STD_LOGIC; m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); mm2s_cntrl_reset_out_n : OUT STD_LOGIC; m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC; m_axis_mm2s_cntrl_tready : IN STD_LOGIC; m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC; m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_s2mm_awvalid : OUT STD_LOGIC; m_axi_s2mm_awready : IN STD_LOGIC; m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_s2mm_wlast : OUT STD_LOGIC; m_axi_s2mm_wvalid : OUT STD_LOGIC; m_axi_s2mm_wready : IN STD_LOGIC; m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_s2mm_bvalid : IN STD_LOGIC; m_axi_s2mm_bready : OUT STD_LOGIC; s2mm_prmry_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_s2mm_tvalid : IN STD_LOGIC; s_axis_s2mm_tready : OUT STD_LOGIC; s_axis_s2mm_tlast : IN STD_LOGIC; s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0); s2mm_sts_reset_out_n : OUT STD_LOGIC; s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axis_s2mm_sts_tvalid : IN STD_LOGIC; s_axis_s2mm_sts_tready : OUT STD_LOGIC; s_axis_s2mm_sts_tlast : IN STD_LOGIC; mm2s_introut : OUT STD_LOGIC; s2mm_introut : OUT STD_LOGIC; axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_dma; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST"; ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT"; BEGIN U0 : axi_dma GENERIC MAP ( C_S_AXI_LITE_ADDR_WIDTH => 10, C_S_AXI_LITE_DATA_WIDTH => 32, C_DLYTMR_RESOLUTION => 125, C_PRMRY_IS_ACLK_ASYNC => 0, C_ENABLE_MULTI_CHANNEL => 0, C_NUM_MM2S_CHANNELS => 1, C_NUM_S2MM_CHANNELS => 1, C_INCLUDE_SG => 0, C_SG_INCLUDE_STSCNTRL_STRM => 0, C_SG_USE_STSAPP_LENGTH => 0, C_SG_LENGTH_WIDTH => 14, C_M_AXI_SG_ADDR_WIDTH => 32, C_M_AXI_SG_DATA_WIDTH => 32, C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32, C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32, C_MICRO_DMA => 0, C_INCLUDE_MM2S => 1, C_INCLUDE_MM2S_DRE => 0, C_INCLUDE_MM2S_SF => 1, C_MM2S_BURST_SIZE => 256, C_M_AXI_MM2S_ADDR_WIDTH => 32, C_M_AXI_MM2S_DATA_WIDTH => 64, C_M_AXIS_MM2S_TDATA_WIDTH => 64, C_INCLUDE_S2MM => 1, C_INCLUDE_S2MM_DRE => 0, C_INCLUDE_S2MM_SF => 1, C_S2MM_BURST_SIZE => 256, C_M_AXI_S2MM_ADDR_WIDTH => 32, C_M_AXI_S2MM_DATA_WIDTH => 64, C_S_AXIS_S2MM_TDATA_WIDTH => 64, C_FAMILY => "zynq" ) PORT MAP ( s_axi_lite_aclk => s_axi_lite_aclk, m_axi_sg_aclk => '0', m_axi_mm2s_aclk => m_axi_mm2s_aclk, m_axi_s2mm_aclk => m_axi_s2mm_aclk, axi_resetn => axi_resetn, s_axi_lite_awvalid => s_axi_lite_awvalid, s_axi_lite_awready => s_axi_lite_awready, s_axi_lite_awaddr => s_axi_lite_awaddr, s_axi_lite_wvalid => s_axi_lite_wvalid, s_axi_lite_wready => s_axi_lite_wready, s_axi_lite_wdata => s_axi_lite_wdata, s_axi_lite_bresp => s_axi_lite_bresp, s_axi_lite_bvalid => s_axi_lite_bvalid, s_axi_lite_bready => s_axi_lite_bready, s_axi_lite_arvalid => s_axi_lite_arvalid, s_axi_lite_arready => s_axi_lite_arready, s_axi_lite_araddr => s_axi_lite_araddr, s_axi_lite_rvalid => s_axi_lite_rvalid, s_axi_lite_rready => s_axi_lite_rready, s_axi_lite_rdata => s_axi_lite_rdata, s_axi_lite_rresp => s_axi_lite_rresp, m_axi_sg_awready => '0', m_axi_sg_wready => '0', m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_sg_bvalid => '0', m_axi_sg_arready => '0', m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_sg_rlast => '0', m_axi_sg_rvalid => '0', m_axi_mm2s_araddr => m_axi_mm2s_araddr, m_axi_mm2s_arlen => m_axi_mm2s_arlen, m_axi_mm2s_arsize => m_axi_mm2s_arsize, m_axi_mm2s_arburst => m_axi_mm2s_arburst, m_axi_mm2s_arprot => m_axi_mm2s_arprot, m_axi_mm2s_arcache => m_axi_mm2s_arcache, m_axi_mm2s_arvalid => m_axi_mm2s_arvalid, m_axi_mm2s_arready => m_axi_mm2s_arready, m_axi_mm2s_rdata => m_axi_mm2s_rdata, m_axi_mm2s_rresp => m_axi_mm2s_rresp, m_axi_mm2s_rlast => m_axi_mm2s_rlast, m_axi_mm2s_rvalid => m_axi_mm2s_rvalid, m_axi_mm2s_rready => m_axi_mm2s_rready, mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n, m_axis_mm2s_tdata => m_axis_mm2s_tdata, m_axis_mm2s_tkeep => m_axis_mm2s_tkeep, m_axis_mm2s_tvalid => m_axis_mm2s_tvalid, m_axis_mm2s_tready => m_axis_mm2s_tready, m_axis_mm2s_tlast => m_axis_mm2s_tlast, m_axis_mm2s_cntrl_tready => '0', m_axi_s2mm_awaddr => m_axi_s2mm_awaddr, m_axi_s2mm_awlen => m_axi_s2mm_awlen, m_axi_s2mm_awsize => m_axi_s2mm_awsize, m_axi_s2mm_awburst => m_axi_s2mm_awburst, m_axi_s2mm_awprot => m_axi_s2mm_awprot, m_axi_s2mm_awcache => m_axi_s2mm_awcache, m_axi_s2mm_awvalid => m_axi_s2mm_awvalid, m_axi_s2mm_awready => m_axi_s2mm_awready, m_axi_s2mm_wdata => m_axi_s2mm_wdata, m_axi_s2mm_wstrb => m_axi_s2mm_wstrb, m_axi_s2mm_wlast => m_axi_s2mm_wlast, m_axi_s2mm_wvalid => m_axi_s2mm_wvalid, m_axi_s2mm_wready => m_axi_s2mm_wready, m_axi_s2mm_bresp => m_axi_s2mm_bresp, m_axi_s2mm_bvalid => m_axi_s2mm_bvalid, m_axi_s2mm_bready => m_axi_s2mm_bready, s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n, s_axis_s2mm_tdata => s_axis_s2mm_tdata, s_axis_s2mm_tkeep => s_axis_s2mm_tkeep, s_axis_s2mm_tvalid => s_axis_s2mm_tvalid, s_axis_s2mm_tready => s_axis_s2mm_tready, s_axis_s2mm_tlast => s_axis_s2mm_tlast, s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)), s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)), s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_s2mm_sts_tkeep => X"F", s_axis_s2mm_sts_tvalid => '0', s_axis_s2mm_sts_tlast => '0', mm2s_introut => mm2s_introut, s2mm_introut => s2mm_introut, axi_dma_tstvec => axi_dma_tstvec ); END daala_zynq_axi_dma_0_0_arch;
bsd-2-clause
be7982e0da5e4efc3a7c522b32cf0249
0.673165
2.782471
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg.vhd
1
84,516
-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg.vhd -- Description: This entity is the top level entity for the AXI Scatter Gather -- Engine. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg.vhd -- axi_sg_pkg.vhd -- |- axi_sg_ftch_mngr.vhd -- | |- axi_sg_ftch_sm.vhd -- | |- axi_sg_ftch_pntr.vhd -- | |- axi_sg_ftch_cmdsts_if.vhd -- |- axi_sg_updt_mngr.vhd -- | |- axi_sg_updt_sm.vhd -- | |- axi_sg_updt_cmdsts_if.vhd -- |- axi_sg_ftch_q_mngr.vhd -- | |- axi_sg_ftch_queue.vhd -- | | |- proc_common_v4_0.sync_fifo_fg.vhd -- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd -- | |- axi_sg_ftch_noqueue.vhd -- |- axi_sg_updt_q_mngr.vhd -- | |- axi_sg_updt_queue.vhd -- | | |- proc_common_v4_0.sync_fifo_fg.vhd -- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd -- | |- axi_sg_updt_noqueue.vhd -- |- axi_sg_intrpt.vhd -- |- axi_datamover_v4_01_a.axi_datamover.vhd -- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.max2; ------------------------------------------------------------------------------- entity axi_sg is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- AXI Master Stream out for descriptor fetch C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0; -- Starting update word offset C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8; -- Number of words to fetch C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0; -- Starting update word offset C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1; -- Enable or disable stale descriptor check -- 0 = Disable stale descriptor error check -- 1 = Enable stale descriptor error check C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1; -- Include or Exclude Scatter Gather Descriptor Update -- 0 = Exclude Descriptor Update -- 1 = Include Descriptor Update C_INCLUDE_INTRPT : integer range 0 to 1 := 1; -- Include/Exclude interrupt logic coalescing -- 0 = Exclude Delay timer -- 1 = Include Delay timer C_INCLUDE_DLYTMR : integer range 0 to 1 := 1; -- Include/Exclude interrupt delay timer -- 0 = Exclude Delay timer -- 1 = Include Delay timer C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125; -- Interrupt Delay Timer resolution in usec C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_ENABLE_CDMA : integer range 0 to 1 := 0; C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0; C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1; C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_mm2s_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- p_reset_n : in std_logic ; -- dm_resetn : in std_logic ; -- sg_ctl : in std_logic_vector (7 downto 0) ; -- -- Scatter Gather Write Address Channel -- m_axi_sg_awaddr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; -- m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; -- m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; -- m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; -- m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; -- m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; -- m_axi_sg_awvalid : out std_logic ; -- m_axi_sg_awready : in std_logic ; -- -- -- Scatter Gather Write Data Channel -- m_axi_sg_wdata : out std_logic_vector -- (C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; -- m_axi_sg_wstrb : out std_logic_vector -- ((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); -- m_axi_sg_wlast : out std_logic ; -- m_axi_sg_wvalid : out std_logic ; -- m_axi_sg_wready : in std_logic ; -- -- -- Scatter Gather Write Response Channel -- m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; -- m_axi_sg_bvalid : in std_logic ; -- m_axi_sg_bready : out std_logic ; -- -- -- Scatter Gather Read Address Channel -- m_axi_sg_araddr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; -- m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; -- m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; -- m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; -- m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; -- m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; -- m_axi_sg_arvalid : out std_logic ; -- m_axi_sg_arready : in std_logic ; -- -- -- Memory Map to Stream Scatter Gather Read Data Channel -- m_axi_sg_rdata : in std_logic_vector -- (C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; -- m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; -- m_axi_sg_rlast : in std_logic ; -- m_axi_sg_rvalid : in std_logic ; -- m_axi_sg_rready : out std_logic ; -- -- -- Channel 1 Control and Status -- ch1_run_stop : in std_logic ; -- ch1_cyclic : in std_logic ; -- ch1_desc_flush : in std_logic ; -- ch1_cntrl_strm_stop : in std_logic ; ch1_tailpntr_enabled : in std_logic ; -- ch1_taildesc_wren : in std_logic ; -- ch1_taildesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_ftch_idle : out std_logic ; -- ch1_ftch_interr_set : out std_logic ; -- ch1_ftch_slverr_set : out std_logic ; -- ch1_ftch_decerr_set : out std_logic ; -- ch1_ftch_err_early : out std_logic ; -- ch1_ftch_stale_desc : out std_logic ; -- ch1_updt_idle : out std_logic ; -- ch1_updt_ioc_irq_set : out std_logic ; -- ch1_updt_interr_set : out std_logic ; -- ch1_updt_slverr_set : out std_logic ; -- ch1_updt_decerr_set : out std_logic ; -- ch1_dma_interr_set : out std_logic ; -- ch1_dma_slverr_set : out std_logic ; -- ch1_dma_decerr_set : out std_logic ; -- -- -- -- Channel 1 Interrupt Coalescing Signals -- ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 -- ch1_dlyirq_dsble : in std_logic ; -- ch1_irqdelay_wren : in std_logic ; -- ch1_irqdelay : in std_logic_vector(7 downto 0) ; -- ch1_irqthresh_wren : in std_logic ; -- ch1_irqthresh : in std_logic_vector(7 downto 0) ; -- ch1_packet_sof : in std_logic ; -- ch1_packet_eof : in std_logic ; -- ch1_ioc_irq_set : out std_logic ; -- ch1_dly_irq_set : out std_logic ; -- ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; -- ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ch1_ftch_aclk : in std_logic ; -- m_axis_ch1_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ch1_ftch_tvalid : out std_logic ; -- m_axis_ch1_ftch_tready : in std_logic ; -- m_axis_ch1_ftch_tlast : out std_logic ; -- m_axis_ch1_ftch_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ch1_ftch_tvalid_new : out std_logic ; -- m_axis_ftch1_desc_available : out std_logic; -- -- -- Channel 1 AXI Update Stream In -- s_axis_ch1_updt_aclk : in std_logic ; -- s_axis_ch1_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_ch1_updtptr_tvalid : in std_logic ; -- s_axis_ch1_updtptr_tready : out std_logic ; -- s_axis_ch1_updtptr_tlast : in std_logic ; -- -- s_axis_ch1_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_ch1_updtsts_tvalid : in std_logic ; -- s_axis_ch1_updtsts_tready : out std_logic ; -- s_axis_ch1_updtsts_tlast : in std_logic ; -- -- -- Channel 2 Control and Status -- ch2_run_stop : in std_logic ; -- ch2_cyclic : in std_logic ; -- ch2_desc_flush : in std_logic ; -- ch2_tailpntr_enabled : in std_logic ; -- ch2_taildesc_wren : in std_logic ; -- ch2_taildesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_curdesc : in std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_ftch_idle : out std_logic ; -- ch2_ftch_interr_set : out std_logic ; -- ch2_ftch_slverr_set : out std_logic ; -- ch2_ftch_decerr_set : out std_logic ; -- ch2_ftch_err_early : out std_logic ; -- ch2_ftch_stale_desc : out std_logic ; -- ch2_updt_idle : out std_logic ; -- ch2_updt_ioc_irq_set : out std_logic ; -- ch2_updt_interr_set : out std_logic ; -- ch2_updt_slverr_set : out std_logic ; -- ch2_updt_decerr_set : out std_logic ; -- ch2_dma_interr_set : out std_logic ; -- ch2_dma_slverr_set : out std_logic ; -- ch2_dma_decerr_set : out std_logic ; -- -- -- Channel 2 Interrupt Coalescing Signals -- ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 -- ch2_dlyirq_dsble : in std_logic ; -- ch2_irqdelay_wren : in std_logic ; -- ch2_irqdelay : in std_logic_vector(7 downto 0) ; -- ch2_irqthresh_wren : in std_logic ; -- ch2_irqthresh : in std_logic_vector(7 downto 0) ; -- ch2_packet_sof : in std_logic ; -- ch2_packet_eof : in std_logic ; -- ch2_ioc_irq_set : out std_logic ; -- ch2_dly_irq_set : out std_logic ; -- ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; -- ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; -- ch2_update_active : out std_logic ; -- -- Channel 2 AXI Fetch Stream Out -- m_axis_ch2_ftch_aclk : in std_logic ; -- m_axis_ch2_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_ch2_ftch_tvalid : out std_logic ; -- m_axis_ch2_ftch_tready : in std_logic ; -- m_axis_ch2_ftch_tlast : out std_logic ; -- -- m_axis_ch2_ftch_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector -- (31 downto 0); -- m_axis_ch2_ftch_tvalid_new : out std_logic ; -- m_axis_ftch2_desc_available : out std_logic; -- Channel 2 AXI Update Stream In -- s_axis_ch2_updt_aclk : in std_logic ; -- s_axis_ch2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_ch2_updtptr_tvalid : in std_logic ; -- s_axis_ch2_updtptr_tready : out std_logic ; -- s_axis_ch2_updtptr_tlast : in std_logic ; -- -- -- s_axis_ch2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_ch2_updtsts_tvalid : in std_logic ; -- s_axis_ch2_updtsts_tready : out std_logic ; -- s_axis_ch2_updtsts_tlast : in std_logic ; -- -- -- -- Error addresses -- ftch_error : out std_logic ; -- ftch_error_addr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_error : out std_logic ; -- updt_error_addr : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (31 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- (3 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic := '0'; -- m_axis_mm2s_cntrl_tlast : out std_logic ); end axi_sg; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode constant EXCLUDE : integer := 0; -- Define Exclude as 0 constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover -- Always include descriptor fetch (use lite datamover) constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE; -- Selectable include descriptor update (use lite datamover) constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE; -- Always allow address requests constant ALWAYS_ALLOW : std_logic := '1'; -- If async mode and number of descriptors to fetch is zero then set number -- of descriptors to fetch as 1. constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC); constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- DataMover MM2S Fetch Command Stream Signals signal s_axis_ftch_cmd_tvalid : std_logic := '0'; signal s_axis_ftch_cmd_tready : std_logic := '0'; signal s_axis_ftch_cmd_tdata : std_logic_vector (((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); -- DataMover MM2S Fetch Status Stream Signals signal m_axis_ftch_sts_tvalid : std_logic := '0'; signal m_axis_ftch_sts_tready : std_logic := '0'; signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0'); signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0'); signal mm2s_err : std_logic := '0'; -- DataMover MM2S Fetch Stream Signals signal m_axis_mm2s_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_mm2s_tkeep : std_logic_vector ((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_axis_mm2s_tlast : std_logic := '0'; signal m_axis_mm2s_tvalid : std_logic := '0'; signal m_axis_mm2s_tready : std_logic := '0'; -- DataMover S2MM Update Command Stream Signals signal s_axis_updt_cmd_tvalid : std_logic := '0'; signal s_axis_updt_cmd_tready : std_logic := '0'; signal s_axis_updt_cmd_tdata : std_logic_vector (((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); -- DataMover S2MM Update Status Stream Signals signal m_axis_updt_sts_tvalid : std_logic := '0'; signal m_axis_updt_sts_tready : std_logic := '0'; signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0'); signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0'); signal s2mm_err : std_logic := '0'; -- DataMover S2MM Update Stream Signals signal s_axis_s2mm_tdata : std_logic_vector (C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); signal s_axis_s2mm_tkeep : std_logic_vector ((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1'); signal s_axis_s2mm_tlast : std_logic := '0'; signal s_axis_s2mm_tvalid : std_logic := '0'; signal s_axis_s2mm_tready : std_logic := '0'; -- Channel 1 internals signal ch1_ftch_active : std_logic := '0'; signal ch1_ftch_queue_empty : std_logic := '0'; signal ch1_ftch_queue_full : std_logic := '0'; signal ch1_nxtdesc_wren : std_logic := '0'; signal ch1_updt_active : std_logic := '0'; signal ch1_updt_queue_empty : std_logic := '0'; signal ch1_updt_curdesc_wren : std_logic := '0'; signal ch1_updt_curdesc : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ch1_updt_ioc : std_logic := '0'; signal ch1_updt_ioc_irq_set_i : std_logic := '0'; signal ch1_dma_interr : std_logic := '0'; signal ch1_dma_slverr : std_logic := '0'; signal ch1_dma_decerr : std_logic := '0'; signal ch1_dma_interr_set_i : std_logic := '0'; signal ch1_dma_slverr_set_i : std_logic := '0'; signal ch1_dma_decerr_set_i : std_logic := '0'; signal ch1_updt_done : std_logic := '0'; signal ch1_ftch_pause : std_logic := '0'; -- Channel 2 internals signal ch2_ftch_active : std_logic := '0'; signal ch2_ftch_queue_empty : std_logic := '0'; signal ch2_ftch_queue_full : std_logic := '0'; signal ch2_nxtdesc_wren : std_logic := '0'; signal ch2_updt_active : std_logic := '0'; signal ch2_updt_queue_empty : std_logic := '0'; signal ch2_updt_curdesc_wren : std_logic := '0'; signal ch2_updt_curdesc : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ch2_updt_ioc : std_logic := '0'; signal ch2_updt_ioc_irq_set_i : std_logic := '0'; signal ch2_dma_interr : std_logic := '0'; signal ch2_dma_slverr : std_logic := '0'; signal ch2_dma_decerr : std_logic := '0'; signal ch2_dma_interr_set_i : std_logic := '0'; signal ch2_dma_slverr_set_i : std_logic := '0'; signal ch2_dma_decerr_set_i : std_logic := '0'; signal ch2_updt_done : std_logic := '0'; signal ch2_ftch_pause : std_logic := '0'; signal nxtdesc : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0'); signal ftch_cmnd_wr : std_logic := '0'; signal ftch_cmnd_data : std_logic_vector ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0'); signal ftch_stale_desc : std_logic := '0'; signal ftch_error_i : std_logic := '0'; signal updt_error_i : std_logic := '0'; signal ch1_irqthresh_decr : std_logic := '0'; --CR567661 signal ch2_irqthresh_decr : std_logic := '0'; --CR567661 signal m_axi_sg_awaddr_int : std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- signal m_axi_sg_awlen_int : std_logic_vector(7 downto 0) ; -- signal m_axi_sg_awsize_int : std_logic_vector(2 downto 0) ; -- signal m_axi_sg_awburst_int : std_logic_vector(1 downto 0) ; -- signal m_axi_sg_awprot_int : std_logic_vector(2 downto 0) ; -- signal m_axi_sg_awcache_int : std_logic_vector(3 downto 0) ; -- signal m_axi_sg_awuser_int : std_logic_vector(3 downto 0) ; -- signal m_axi_sg_awvalid_int : std_logic ; -- signal m_axi_sg_awready_int : std_logic ; -- -- -- Scatter Gather Write Data Channel -- signal m_axi_sg_wdata_int : std_logic_vector -- (C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; -- signal m_axi_sg_wstrb_int : std_logic_vector -- ((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); -- signal m_axi_sg_wlast_int : std_logic ; -- signal m_axi_sg_wvalid_int : std_logic ; -- signal m_axi_sg_wready_int : std_logic ; -- signal m_axi_sg_bresp_int : std_logic_vector (1 downto 0); signal m_axi_sg_bvalid_int : std_logic; signal m_axi_sg_bready_int : std_logic; signal m_axi_sg_bvalid_int_del : std_logic; signal ch2_eof_detected : std_logic; signal s_axis_ch2_updtsts_tready_i : std_logic; signal ch2_sg_idle, tail_updt_latch : std_logic; signal tail_updt : std_logic; signal ch2_taildesc_wren_int : std_logic; signal ch2_sg_idle_int : std_logic; signal ftch_error_addr_1 : std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; signal updt_error_addr_1 : std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; signal ch1_ftch_interr_set_i : std_logic := '0'; signal ch1_ftch_slverr_set_i : std_logic := '0'; signal ch1_ftch_decerr_set_i : std_logic := '0'; signal ch2_ftch_interr_set_i : std_logic := '0'; signal ch2_ftch_slverr_set_i : std_logic := '0'; signal ch2_ftch_decerr_set_i : std_logic := '0'; signal ch1_updt_interr_set_i : std_logic := '0'; signal ch1_updt_slverr_set_i : std_logic := '0'; signal ch1_updt_decerr_set_i : std_logic := '0'; signal ch2_updt_interr_set_i : std_logic := '0'; signal ch2_updt_slverr_set_i : std_logic := '0'; signal ch2_updt_decerr_set_i : std_logic := '0'; signal ftch_error_capture : std_logic := '0'; signal updt_error_capture : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin updt_error <= updt_error_i; ftch_error <= ftch_error_i; ftch_error_capture <= ch1_ftch_interr_set_i or ch1_ftch_slverr_set_i or ch1_ftch_decerr_set_i or ch2_ftch_interr_set_i or ch2_ftch_slverr_set_i or ch2_ftch_decerr_set_i; ch1_ftch_interr_set <= ch1_ftch_interr_set_i; ch1_ftch_slverr_set <= ch1_ftch_slverr_set_i; ch1_ftch_decerr_set <= ch1_ftch_decerr_set_i; ch2_ftch_interr_set <= ch2_ftch_interr_set_i; ch2_ftch_slverr_set <= ch2_ftch_slverr_set_i; ch2_ftch_decerr_set <= ch2_ftch_decerr_set_i; updt_error_capture <= ch1_updt_interr_set_i or ch1_updt_slverr_set_i or ch1_updt_decerr_set_i or ch2_updt_interr_set_i or ch2_updt_slverr_set_i or ch2_updt_decerr_set_i or ch2_dma_interr_set_i or ch2_dma_slverr_set_i or ch2_dma_decerr_set_i or ch1_dma_interr_set_i or ch1_dma_slverr_set_i or ch1_dma_decerr_set_i; ch1_updt_interr_set <= ch1_updt_interr_set_i; ch1_updt_slverr_set <= ch1_updt_slverr_set_i; ch1_updt_decerr_set <= ch1_updt_decerr_set_i; ch2_updt_interr_set <= ch2_updt_interr_set_i; ch2_updt_slverr_set <= ch2_updt_slverr_set_i; ch2_updt_decerr_set <= ch2_updt_decerr_set_i; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (m_axi_sg_aresetn = '0') then ftch_error_addr (31 downto 6) <= (others => '0'); elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then ftch_error_addr (31 downto 6)<= ftch_error_addr_1(31 downto 6); elsif (updt_error_capture = '1') then ftch_error_addr (31 downto 6)<= updt_error_addr_1(31 downto 6); end if; end if; end process; updt_error_addr <= (others => '0'); ftch_error_addr (5 downto 0) <= (others => '0'); -- Always valid therefore fix to '1' s_axis_s2mm_tkeep <= (others => '1'); -- Drive interrupt on complete set out --ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661 --ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661 ch1_dma_interr_set <= ch1_dma_interr_set_i; ch1_dma_slverr_set <= ch1_dma_slverr_set_i; ch1_dma_decerr_set <= ch1_dma_decerr_set_i; ch2_dma_interr_set <= ch2_dma_interr_set_i; ch2_dma_slverr_set <= ch2_dma_slverr_set_i; ch2_dma_decerr_set <= ch2_dma_decerr_set_i; s_axis_ch2_updtsts_tready <= s_axis_ch2_updtsts_tready_i; EOF_DET : if (C_ENABLE_MULTI_CHANNEL = 1) generate ch2_eof_detected <= s_axis_ch2_updtsts_tdata (26) and s_axis_ch2_updtsts_tready_i and s_axis_ch2_updtsts_tvalid and s_axis_ch2_updtsts_tlast; ch2_sg_idle_int <= ch2_sg_idle; TAILUPDT_LATCH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or tail_updt = '1' ) then -- nned to have some reset condition here tail_updt <= '0'; elsif(ch2_sg_idle = '1' and tail_updt_latch = '1' and tail_updt = '0')then tail_updt <= '1'; end if; end if; end process TAILUPDT_LATCH; ch2_taildesc_wren_int <= ch2_taildesc_wren or tail_updt; end generate EOF_DET; NOEOF_DET : if (C_ENABLE_MULTI_CHANNEL = 0) generate tail_updt <= '0'; ch2_eof_detected <= '0'; ch2_taildesc_wren_int <= ch2_taildesc_wren; ch2_sg_idle_int <= '0'; --ch2_sg_idle; end generate NOEOF_DET; ------------------------------------------------------------------------------- -- Scatter Gather Fetch Manager ------------------------------------------------------------------------------- I_SG_FETCH_MNGR : entity axi_sg_v4_1.axi_sg_ftch_mngr generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 , C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH , C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR , C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR , C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Channel 1 Control and Status ch1_run_stop => ch1_run_stop , ch1_desc_flush => ch1_desc_flush , ch1_updt_done => ch1_updt_done , ch1_ftch_idle => ch1_ftch_idle , ch1_ftch_active => ch1_ftch_active , ch1_ftch_interr_set => ch1_ftch_interr_set_i , ch1_ftch_slverr_set => ch1_ftch_slverr_set_i , ch1_ftch_decerr_set => ch1_ftch_decerr_set_i , ch1_ftch_err_early => ch1_ftch_err_early , ch1_ftch_stale_desc => ch1_ftch_stale_desc , ch1_tailpntr_enabled => ch1_tailpntr_enabled , ch1_taildesc_wren => ch1_taildesc_wren , ch1_taildesc => ch1_taildesc , ch1_nxtdesc_wren => ch1_nxtdesc_wren , ch1_curdesc => ch1_curdesc , ch1_ftch_queue_empty => ch1_ftch_queue_empty , ch1_ftch_queue_full => ch1_ftch_queue_full , ch1_ftch_pause => ch1_ftch_pause , -- Channel 2 Control and Status ch2_run_stop => ch2_run_stop , ch2_desc_flush => ch2_desc_flush , ch2_updt_done => ch2_updt_done , ch2_ftch_idle => ch2_ftch_idle , ch2_ftch_active => ch2_ftch_active , ch2_ftch_interr_set => ch2_ftch_interr_set_i , ch2_ftch_slverr_set => ch2_ftch_slverr_set_i , ch2_ftch_decerr_set => ch2_ftch_decerr_set_i , ch2_ftch_err_early => ch2_ftch_err_early , ch2_ftch_stale_desc => ch2_ftch_stale_desc , ch2_tailpntr_enabled => ch2_tailpntr_enabled , ch2_taildesc_wren => ch2_taildesc_wren_int , ch2_taildesc => ch2_taildesc , ch2_nxtdesc_wren => ch2_nxtdesc_wren , ch2_curdesc => ch2_curdesc , ch2_ftch_queue_empty => ch2_ftch_queue_empty , ch2_ftch_queue_full => ch2_ftch_queue_full , ch2_ftch_pause => ch2_ftch_pause , ch2_eof_detected => ch2_eof_detected , tail_updt => tail_updt , tail_updt_latch => tail_updt_latch , ch2_sg_idle => ch2_sg_idle , nxtdesc => nxtdesc , -- Read response for detecting slverr, decerr early m_axi_sg_rresp => m_axi_sg_rresp , m_axi_sg_rvalid => m_axi_sg_rvalid , -- User Command Interface Ports (AXI Stream) s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid , s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready , s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) , -- User Status Interface Ports (AXI Stream) m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid , m_axis_ftch_sts_tready => m_axis_ftch_sts_tready , m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata , m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep , mm2s_err => mm2s_err , -- DataMover Command ftch_cmnd_wr => ftch_cmnd_wr , ftch_cmnd_data => ftch_cmnd_data , ftch_stale_desc => ftch_stale_desc , updt_error => updt_error_i , ftch_error => ftch_error_i , ftch_error_addr => ftch_error_addr_1 ); ------------------------------------------------------------------------------- -- Scatter Gather Fetch Queue ------------------------------------------------------------------------------- I_SG_FETCH_QUEUE : entity axi_sg_v4_1.axi_sg_ftch_q_mngr generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE , C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH , C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH , C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR , C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR , C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL , C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 , C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_ASYNC => C_ASYNC , C_ENABLE_CDMA => C_ENABLE_CDMA, C_FAMILY => C_FAMILY ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_mm2s_aclk => m_axi_mm2s_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , p_reset_n => p_reset_n , ch2_sg_idle => ch2_sg_idle_int , -- Channel 1 Control ch1_desc_flush => ch1_desc_flush , ch1_cyclic => ch1_cyclic , ch1_cntrl_strm_stop => ch1_cntrl_strm_stop , ch1_ftch_active => ch1_ftch_active , ch1_nxtdesc_wren => ch1_nxtdesc_wren , ch1_ftch_queue_empty => ch1_ftch_queue_empty , ch1_ftch_queue_full => ch1_ftch_queue_full , ch1_ftch_pause => ch1_ftch_pause , -- Channel 2 Control ch2_ftch_active => ch2_ftch_active , ch2_cyclic => ch2_cyclic , ch2_desc_flush => ch2_desc_flush , ch2_nxtdesc_wren => ch2_nxtdesc_wren , ch2_ftch_queue_empty => ch2_ftch_queue_empty , ch2_ftch_queue_full => ch2_ftch_queue_full , ch2_ftch_pause => ch2_ftch_pause , nxtdesc => nxtdesc , -- DataMover Command ftch_cmnd_wr => ftch_cmnd_wr , ftch_cmnd_data => ftch_cmnd_data , ftch_stale_desc => ftch_stale_desc , -- MM2S Stream In from DataMover m_axis_mm2s_tdata => m_axis_mm2s_tdata , m_axis_mm2s_tkeep => m_axis_mm2s_tkeep , m_axis_mm2s_tlast => m_axis_mm2s_tlast , m_axis_mm2s_tvalid => m_axis_mm2s_tvalid , m_axis_mm2s_tready => m_axis_mm2s_tready , -- Channel 1 AXI Fetch Stream Out m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk , m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata , m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid , m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready , m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast , m_axis_ch1_ftch_tdata_new => m_axis_ch1_ftch_tdata_new , m_axis_ch1_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new , m_axis_ch1_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new , m_axis_ftch1_desc_available => m_axis_ftch1_desc_available, m_axis_ch2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new , m_axis_ch2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new , m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt , m_axis_ch2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new , m_axis_ftch2_desc_available => m_axis_ftch2_desc_available, -- Channel 2 AXI Fetch Stream Out m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk , m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata , m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid , m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready , m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast , m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); -- Include Scatter Gather Descriptor Update logic GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate begin -- CR567661 -- Route update version of IOC set to threshold -- counter decrement control ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i; ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i; -- Drive interrupt on complete set out ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; ------------------------------------------------------------------------------- -- Scatter Gather Update Manager ------------------------------------------------------------------------------- I_SG_UPDATE_MNGR : entity axi_sg_v4_1.axi_sg_updt_mngr generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 , C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE , C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD , C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE , C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD ) port map( m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Channel 1 Control and Status ch1_updt_idle => ch1_updt_idle , ch1_updt_active => ch1_updt_active , ch1_updt_ioc => ch1_updt_ioc , ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i , -- Update Descriptor Status ch1_dma_interr => ch1_dma_interr , ch1_dma_slverr => ch1_dma_slverr , ch1_dma_decerr => ch1_dma_decerr , ch1_dma_interr_set => ch1_dma_interr_set_i , ch1_dma_slverr_set => ch1_dma_slverr_set_i , ch1_dma_decerr_set => ch1_dma_decerr_set_i , ch1_updt_interr_set => ch1_updt_interr_set_i , ch1_updt_slverr_set => ch1_updt_slverr_set_i , ch1_updt_decerr_set => ch1_updt_decerr_set_i , ch1_updt_queue_empty => ch1_updt_queue_empty , ch1_updt_curdesc_wren => ch1_updt_curdesc_wren , ch1_updt_curdesc => ch1_updt_curdesc , ch1_updt_done => ch1_updt_done , -- Channel 2 Control and Status ch2_dma_interr => ch2_dma_interr , ch2_dma_slverr => ch2_dma_slverr , ch2_dma_decerr => ch2_dma_decerr , ch2_updt_idle => ch2_updt_idle , ch2_updt_active => ch2_updt_active , ch2_updt_ioc => ch2_updt_ioc , ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i , ch2_dma_interr_set => ch2_dma_interr_set_i , ch2_dma_slverr_set => ch2_dma_slverr_set_i , ch2_dma_decerr_set => ch2_dma_decerr_set_i , ch2_updt_interr_set => ch2_updt_interr_set_i , ch2_updt_slverr_set => ch2_updt_slverr_set_i , ch2_updt_decerr_set => ch2_updt_decerr_set_i , ch2_updt_queue_empty => ch2_updt_queue_empty , -- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren , -- ch2_updt_curdesc => ch2_updt_curdesc , ch2_updt_done => ch2_updt_done , -- User Command Interface Ports (AXI Stream) s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid , s_axis_updt_cmd_tready => s_axis_updt_cmd_tready , s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) , -- User Status Interface Ports (AXI Stream) m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid , m_axis_updt_sts_tready => m_axis_updt_sts_tready , m_axis_updt_sts_tdata => m_axis_updt_sts_tdata , m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep , s2mm_err => s2mm_err , ftch_error => ftch_error_i , updt_error => updt_error_i , updt_error_addr => updt_error_addr_1 ); ------------------------------------------------------------------------------- -- Scatter Gather Update Queue ------------------------------------------------------------------------------- I_SG_UPDATE_QUEUE : entity axi_sg_v4_1.axi_sg_updt_q_mngr generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE , C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE , C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE , C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 , C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_FAMILY => C_FAMILY ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Channel 1 Control ch1_updt_curdesc_wren => ch1_updt_curdesc_wren , ch1_updt_curdesc => ch1_updt_curdesc , ch1_updt_active => ch1_updt_active , ch1_updt_queue_empty => ch1_updt_queue_empty , ch1_updt_ioc => ch1_updt_ioc , ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i , -- Channel 1 Update Descriptor Status ch1_dma_interr => ch1_dma_interr , ch1_dma_slverr => ch1_dma_slverr , ch1_dma_decerr => ch1_dma_decerr , ch1_dma_interr_set => ch1_dma_interr_set_i , ch1_dma_slverr_set => ch1_dma_slverr_set_i , ch1_dma_decerr_set => ch1_dma_decerr_set_i , -- Channel 2 Control ch2_updt_active => ch2_updt_active , -- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren , -- ch2_updt_curdesc => ch2_updt_curdesc , ch2_updt_queue_empty => ch2_updt_queue_empty , ch2_updt_ioc => ch2_updt_ioc , ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i , -- Channel 2 Update Descriptor Status ch2_dma_interr => ch2_dma_interr , ch2_dma_slverr => ch2_dma_slverr , ch2_dma_decerr => ch2_dma_decerr , ch2_dma_interr_set => ch2_dma_interr_set_i , ch2_dma_slverr_set => ch2_dma_slverr_set_i , ch2_dma_decerr_set => ch2_dma_decerr_set_i , -- S2MM Stream Out To DataMover s_axis_s2mm_tdata => s_axis_s2mm_tdata , s_axis_s2mm_tlast => s_axis_s2mm_tlast , s_axis_s2mm_tvalid => s_axis_s2mm_tvalid , s_axis_s2mm_tready => s_axis_s2mm_tready , -- Channel 1 AXI Update Stream In s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk , s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata , s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid , s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready , s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast , s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata , s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid , s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready , s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast , -- Channel 2 AXI Update Stream In s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk , s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata , s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready , s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast , s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata , s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready_i , s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast ); end generate GEN_DESC_UPDATE; -- Exclude Scatter Gather Descriptor Update logic GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate begin ch1_updt_idle <= '1'; ch1_updt_active <= '0'; -- ch1_updt_ioc_irq_set <= '0';--CR#569609 ch1_updt_interr_set <= '0'; ch1_updt_slverr_set <= '0'; ch1_updt_decerr_set <= '0'; ch1_dma_interr_set_i <= '0'; ch1_dma_slverr_set_i <= '0'; ch1_dma_decerr_set_i <= '0'; ch1_updt_done <= '1'; -- Always done ch2_updt_idle <= '1'; ch2_updt_active <= '0'; -- ch2_updt_ioc_irq_set <= '0'; --CR#569609 ch2_updt_interr_set <= '0'; ch2_updt_slverr_set <= '0'; ch2_updt_decerr_set <= '0'; ch2_dma_interr_set_i <= '0'; ch2_dma_slverr_set_i <= '0'; ch2_dma_decerr_set_i <= '0'; ch2_updt_done <= '1'; -- Always done s_axis_updt_cmd_tvalid <= '0'; s_axis_updt_cmd_tdata <= (others => '0'); m_axis_updt_sts_tready <= '0'; updt_error_i <= '0'; updt_error_addr <= (others => '0'); ch1_updt_curdesc_wren <= '0'; ch1_updt_curdesc <= (others => '0'); ch1_updt_queue_empty <= '0'; ch1_updt_ioc <= '0'; ch1_dma_interr <= '0'; ch1_dma_slverr <= '0'; ch1_dma_decerr <= '0'; ch2_updt_curdesc_wren <= '0'; ch2_updt_curdesc <= (others => '0'); ch2_updt_queue_empty <= '0'; ch2_updt_ioc <= '0'; ch2_dma_interr <= '0'; ch2_dma_slverr <= '0'; ch2_dma_decerr <= '0'; s_axis_s2mm_tdata <= (others => '0'); s_axis_s2mm_tlast <= '0'; s_axis_s2mm_tvalid <= '0'; s_axis_ch1_updtptr_tready <= '0'; s_axis_ch2_updtptr_tready <= '0'; s_axis_ch1_updtsts_tready <= '0'; s_axis_ch2_updtsts_tready <= '0'; -- CR567661 -- Route packet eof to threshold counter decrement control ch1_irqthresh_decr <= ch1_packet_eof; ch2_irqthresh_decr <= ch2_packet_eof; -- Drive interrupt on complete set out ch1_updt_ioc_irq_set <= ch1_packet_eof; ch2_updt_ioc_irq_set <= ch2_packet_eof; end generate GEN_NO_DESC_UPDATE; ------------------------------------------------------------------------------- -- Scatter Gather Interrupt Coalescing ------------------------------------------------------------------------------- GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate begin I_AXI_SG_INTRPT : entity axi_sg_v4_1.axi_sg_intrpt generic map( C_INCLUDE_CH1 => C_INCLUDE_CH1 , C_INCLUDE_CH2 => C_INCLUDE_CH2 , C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR , C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ) port map( -- Secondary Clock and Reset m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661 ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013 ch1_dlyirq_dsble => ch1_dlyirq_dsble , ch1_irqdelay_wren => ch1_irqdelay_wren , ch1_irqdelay => ch1_irqdelay , ch1_irqthresh_wren => ch1_irqthresh_wren , ch1_irqthresh => ch1_irqthresh , ch1_packet_sof => ch1_packet_sof , ch1_packet_eof => ch1_packet_eof , ch1_ioc_irq_set => ch1_ioc_irq_set , ch1_dly_irq_set => ch1_dly_irq_set , ch1_irqdelay_status => ch1_irqdelay_status , ch1_irqthresh_status => ch1_irqthresh_status , ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661 ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013 ch2_dlyirq_dsble => ch2_dlyirq_dsble , ch2_irqdelay_wren => ch2_irqdelay_wren , ch2_irqdelay => ch2_irqdelay , ch2_irqthresh_wren => ch2_irqthresh_wren , ch2_irqthresh => ch2_irqthresh , ch2_packet_sof => ch2_packet_sof , ch2_packet_eof => ch2_packet_eof , ch2_ioc_irq_set => ch2_ioc_irq_set , ch2_dly_irq_set => ch2_dly_irq_set , ch2_irqdelay_status => ch2_irqdelay_status , ch2_irqthresh_status => ch2_irqthresh_status ); end generate GEN_INTERRUPT_LOGIC; GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate begin ch1_ioc_irq_set <= '0'; ch1_dly_irq_set <= '0'; ch1_irqdelay_status <= (others => '0'); ch1_irqthresh_status <= (others => '0'); ch2_ioc_irq_set <= '0'; ch2_dly_irq_set <= '0'; ch2_irqdelay_status <= (others => '0'); ch2_irqthresh_status <= (others => '0'); end generate GEN_NO_INTRPT_LOGIC; ------------------------------------------------------------------------------- -- Scatter Gather DataMover Lite ------------------------------------------------------------------------------- I_SG_AXI_DATAMOVER : entity axi_sg_v4_1.axi_sg_datamover generic map( C_INCLUDE_MM2S => 2, --INCLUDE_DESC_FETCH, -- Lite C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64 C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32 C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32 C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous C_INCLUDE_MM2S_DRE => 0, -- No DRE C_MM2S_BURST_SIZE => 16, -- Set to Min C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, -- C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD, C_INCLUDE_S2MM => 2, --INCLUDE_DESC_UPDATE, -- Lite C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64 C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32 C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32 C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous C_INCLUDE_S2MM_DRE => 0, -- No DRE C_S2MM_BURST_SIZE => 16, -- Set to Min; C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward C_FAMILY => C_FAMILY ) port map( -- MM2S Primary Clock / Reset input m_axi_mm2s_aclk => m_axi_sg_aclk , m_axi_mm2s_aresetn => dm_resetn , mm2s_halt => NEVER_HALT , mm2s_halt_cmplt => open , mm2s_err => mm2s_err , mm2s_allow_addr_req => ALWAYS_ALLOW , mm2s_addr_req_posted => open , mm2s_rd_xfer_cmplt => open , sg_ctl => sg_ctl , -- Memory Map to Stream Command FIFO and Status FIFO I/O -------------- m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk , m_axis_mm2s_cmdsts_aresetn => dm_resetn , -- User Command Interface Ports (AXI Stream) s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid , s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready , s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid , m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready , m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata , m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep , -- MM2S AXI Address Channel I/O -------------------------------------- m_axi_mm2s_arid => open , m_axi_mm2s_araddr => m_axi_sg_araddr , m_axi_mm2s_arlen => m_axi_sg_arlen , m_axi_mm2s_arsize => m_axi_sg_arsize , m_axi_mm2s_arburst => m_axi_sg_arburst , m_axi_mm2s_arprot => m_axi_sg_arprot , m_axi_mm2s_arcache => m_axi_sg_arcache , m_axi_mm2s_aruser => m_axi_sg_aruser , m_axi_mm2s_arvalid => m_axi_sg_arvalid , m_axi_mm2s_arready => m_axi_sg_arready , -- MM2S AXI MMap Read Data Channel I/O ------------------------------- m_axi_mm2s_rdata => m_axi_sg_rdata , m_axi_mm2s_rresp => m_axi_sg_rresp , m_axi_mm2s_rlast => m_axi_sg_rlast , m_axi_mm2s_rvalid => m_axi_sg_rvalid , m_axi_mm2s_rready => m_axi_sg_rready , -- MM2S AXI Master Stream Channel I/O -------------------------------- m_axis_mm2s_tdata => m_axis_mm2s_tdata , m_axis_mm2s_tkeep => m_axis_mm2s_tkeep , m_axis_mm2s_tlast => m_axis_mm2s_tlast , m_axis_mm2s_tvalid => m_axis_mm2s_tvalid , m_axis_mm2s_tready => m_axis_mm2s_tready , -- Testing Support I/O mm2s_dbg_sel => (others => '0') , mm2s_dbg_data => open , -- S2MM Primary Clock/Reset input m_axi_s2mm_aclk => m_axi_sg_aclk , m_axi_s2mm_aresetn => dm_resetn , s2mm_halt => NEVER_HALT , s2mm_halt_cmplt => open , s2mm_err => s2mm_err , s2mm_allow_addr_req => ALWAYS_ALLOW , s2mm_addr_req_posted => open , s2mm_wr_xfer_cmplt => open , s2mm_ld_nxt_len => open , s2mm_wr_len => open , -- Stream to Memory Map Command FIFO and Status FIFO I/O -------------- m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk , m_axis_s2mm_cmdsts_aresetn => dm_resetn , -- User Command Interface Ports (AXI Stream) s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid , s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready , s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata , -- User Status Interface Ports (AXI Stream) m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid , m_axis_s2mm_sts_tready => m_axis_updt_sts_tready , m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata , m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep , -- S2MM AXI Address Channel I/O -------------------------------------- m_axi_s2mm_awid => open , m_axi_s2mm_awaddr => m_axi_sg_awaddr_int , m_axi_s2mm_awlen => m_axi_sg_awlen_int , m_axi_s2mm_awsize => m_axi_sg_awsize_int , m_axi_s2mm_awburst => m_axi_sg_awburst_int , m_axi_s2mm_awprot => m_axi_sg_awprot_int , m_axi_s2mm_awcache => m_axi_sg_awcache_int , m_axi_s2mm_awuser => m_axi_sg_awuser_int , m_axi_s2mm_awvalid => m_axi_sg_awvalid_int , m_axi_s2mm_awready => m_axi_sg_awready_int , -- S2MM AXI MMap Write Data Channel I/O ------------------------------ m_axi_s2mm_wdata => m_axi_sg_wdata , m_axi_s2mm_wstrb => m_axi_sg_wstrb , m_axi_s2mm_wlast => m_axi_sg_wlast , m_axi_s2mm_wvalid => m_axi_sg_wvalid_int , m_axi_s2mm_wready => m_axi_sg_wready_int , -- S2MM AXI MMap Write response Channel I/O -------------------------- m_axi_s2mm_bresp => m_axi_sg_bresp_int , m_axi_s2mm_bvalid => m_axi_sg_bvalid_int , m_axi_s2mm_bready => m_axi_sg_bready_int , -- S2MM AXI Slave Stream Channel I/O --------------------------------- s_axis_s2mm_tdata => s_axis_s2mm_tdata , s_axis_s2mm_tkeep => s_axis_s2mm_tkeep , s_axis_s2mm_tlast => s_axis_s2mm_tlast , s_axis_s2mm_tvalid => s_axis_s2mm_tvalid , s_axis_s2mm_tready => s_axis_s2mm_tready , -- Testing Support I/O s2mm_dbg_sel => (others => '0') , s2mm_dbg_data => open ); --ENABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS = 1) generate -- begin m_axi_sg_awaddr <= m_axi_sg_awaddr_int ; m_axi_sg_awlen <= m_axi_sg_awlen_int ; m_axi_sg_awsize <= m_axi_sg_awsize_int ; m_axi_sg_awburst <= m_axi_sg_awburst_int; m_axi_sg_awprot <= m_axi_sg_awprot_int ; m_axi_sg_awcache <= m_axi_sg_awcache_int; m_axi_sg_awuser <= m_axi_sg_awuser_int ; m_axi_sg_awvalid <= m_axi_sg_awvalid_int; m_axi_sg_awready_int <= m_axi_sg_awready; m_axi_sg_wvalid <= m_axi_sg_wvalid_int; m_axi_sg_wready_int <= m_axi_sg_wready; m_axi_sg_bresp_int <= m_axi_sg_bresp; m_axi_sg_bvalid_int <= m_axi_sg_bvalid; m_axi_sg_bready <= m_axi_sg_bready_int; -- end generate ENABLE_MM2S_STATUS; --DISABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS > 1) generate -- -- m_axi_sg_awaddr <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awaddr_int; -- m_axi_sg_awlen <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awlen_int; -- m_axi_sg_awsize <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awsize_int; -- m_axi_sg_awburst <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awburst_int; -- m_axi_sg_awprot <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awprot_int; -- m_axi_sg_awcache <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awcache_int; -- m_axi_sg_awuser <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awuser_int; -- m_axi_sg_awvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_awvalid_int; -- m_axi_sg_awready_int <= m_axi_sg_awvalid_int when ch1_updt_active = '1' else m_axi_sg_awready; -- to make sure that AXI logic is fine. -- -- m_axi_sg_wvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_wvalid_int; -- m_axi_sg_wready_int <= m_axi_sg_wvalid_int when ch1_updt_active = '1' else m_axi_sg_wready; -- to make sure that AXI logic is fine -- -- m_axi_sg_bresp_int <= m_axi_sg_bresp; -- m_axi_sg_bvalid_int <= m_axi_sg_bvalid_int_del when ch1_updt_active = '1' else m_axi_sg_bvalid; -- m_axi_sg_bready <= m_axi_sg_bready_int; -- ch2_update_active <= ch2_updt_active; -- ---- A dummy response is needed to keep things running on DMA side -- PROC_DUMMY_RESP : process (m_axi_sg_aclk) -- begin -- if (dm_resetn = '0') then -- m_axi_sg_bvalid_int_del <= '0'; -- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then -- m_axi_sg_bvalid_int_del <= m_axi_sg_wvalid_int; -- end if; -- end process PROC_DUMMY_RESP; -- -- end generate DISABLE_MM2S_STATUS; end implementation;
bsd-2-clause
e76065141d76e3cdb2366aaff7d2bbfe
0.400374
4.038224
false
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false
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Nibble-Knowledge/peripheral-ethernet
vhdl-serial/dcm.vhd
1
2,966
-------------------------------------------------------------------------------- -- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 14.7 -- \ \ Application : xaw2vhdl -- / / Filename : dcm.vhd -- /___/ /\ Timestamp : 03/07/2016 00:14:36 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-intstyle C:/Users/Yakov/OneDrive/School/University Stuff/ENEL500/test232/ipcore_dir/dcm.xaw -st dcm.vhd --Design Name: dcm --Device: xc3s250e-4vq100 -- -- Module dcm -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST -- Period Jitter (unit interval) for block DCM_SP_INST = 0.06 UI -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.91 ns library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity dcm is port ( CLKIN_IN : in std_logic; CLKFX_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic); end dcm; architecture BEHAVIORAL of dcm is signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLKIN_IBUFG_INST : IBUFG port map (I=>CLKIN_IN, O=>CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_SP_INST : DCM_SP generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 32, CLKFX_MULTIPLY => 19, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 31.250, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, PSINCDEC=>GND_BIT, RST=>GND_BIT, CLKDV=>open, CLKFX=>CLKFX_BUF, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>open, PSDONE=>open, STATUS=>open); end BEHAVIORAL;
unlicense
4ccdda5dfaf881a42861383fcd56b1e2
0.474039
3.749684
false
false
false
false
cwilkens/ecen4024-microphone-array
microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/dec_shifter.vhd
1
9,221
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mit
afafa25c97900f48234133faf5c85bda
0.92311
1.914659
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/if_statement/rule_035_test_input.vhd
1
550
architecture RTL of FIFO is begin process begin if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; end if; -- Violations below if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; end if; if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; end if; if a = '1' then b <= '0'; elsif c = '1' and d = '0' then b <= '1'; end if; end process; end architecture RTL;
gpl-3.0
ad5d009db4558ea579b87a90b3e3287e
0.363636
3.235294
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux8_1_x_n.vhd
1
6,425
------------------------------------------------------------------------------- -- axi_datamover_dre_mux8_1_x_n.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_dre_mux8_1_x_n.vhd -- -- Description: -- -- This VHDL file provides a 8 to 1 xn bit wide mux for the AXI Data Realignment -- Engine (DRE). -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_dre_mux8_1_x_n.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- --------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.STD_LOGIC_UNSIGNED.all; use ieee.std_logic_arith.all; ------------------------------------------------------------------------------- -- Start 8 to 1 xN Mux ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- Entity axi_datamover_dre_mux8_1_x_n is generic ( C_WIDTH : Integer := 8 -- Sets the bit width of the 8x Mux slice ); port ( Sel : In std_logic_vector(2 downto 0); -- Mux select control I0 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 0 input I1 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 1 input I2 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 2 input I3 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 3 input I4 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 4 input I5 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 5 input I6 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 6 input I7 : In std_logic_vector(C_WIDTH-1 downto 0); -- Select 7 input Y : Out std_logic_vector(C_WIDTH-1 downto 0) -- Mux output value ); end entity axi_datamover_dre_mux8_1_x_n; -- Architecture implementation of axi_datamover_dre_mux8_1_x_n is begin ------------------------------------------------------------- -- Combinational Process -- -- Label: SELECT8_1 -- -- Process Description: -- This process implements an 8 to 1 mux. -- ------------------------------------------------------------- SELECT8_1 : process (Sel, I0, I1, I2, I3, I4, I5, I6, I7) begin case Sel is when "000" => Y <= I0; when "001" => Y <= I1; when "010" => Y <= I2; when "011" => Y <= I3; when "100" => Y <= I4; when "101" => Y <= I5; when "110" => Y <= I6; when "111" => Y <= I7; when others => Y <= I0; end case; end process SELECT8_1; end implementation; -- axi_datamover_dre_mux8_1_x_n ------------------------------------------------------------------------------- -- End 8 to 1 xN Mux -------------------------------------------------------------------------------
bsd-2-clause
7a99abee7edc5c5ec4d17ebc2db178fa
0.463191
4.745199
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/port_map/rule_001_test_input.fixed_lower.vhd
1
643
architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;
gpl-3.0
18183b24f33c80d5311d9b2e8c5e86de
0.463453
2.701681
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/builtin_extdepth_v6.vhd
2
50,137
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block nuS/k7STq7sk4TLgDIJlx2UtMCk4Mi26c4NVXpSSGHMAmmhDq7GyXGgkuM9Py6R1rNGXeOE8g60c 2EhPgjL8ww== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block X/iuJ660rNw6jfReLlXvpfvE7HsEvQAh3UvADwZlPOA7+VB8/+ziLZc2Mn+ndn4hW91yypTtiz+D UhKoWv5bDuk41/fjKXZqtrdO9HAEA1LSicKzcWc6NRTRVgSuJMcx/Bf4za3iVf++h2dO18LpZ4vK +rrcH/qDGKyn65EcnI8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block L0noImdj6o+g6C7r9kfUKMYT4SrFIvkiriieaOwuR5/1h/eNpHDRFo05O4n7n1++Gw/hENa/n9R5 EbtNUP5yDavBJVqvGZdwv/hztXpLCcujM01S46/yq+TP2i85Ui8pFrSlbE7iKFGA4aKEXbty5g8s ob0bf2MG/tUazxjhtPSsC9HwsDuxt21W5gXW5p58yZXRGaqMc7JNoex2wbLWOTcijmGhHpAUPHo6 +M7z+2zmX+vwIBQo5Wnshle673wuRxn1V/rUGK0yg5njOvJGCL7QGw5WgYxvaODA9lG2XrJCxIAP +ODHTsEq2spCVhWdR8gMnPFHg/mO2MjL+Y0AVQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block v0V7VN80CyFDDeGcOpssY/lAMJ3T+b/nU8Kl779TEWH//7XnVtiKmO8GdzSaekYEJhdnIRJ3ujPg N9dW8VuVu9xvZXSDmdMIwK5YaRlizS/SgNE+B0khxK7rYjlTwufLptJdLWqzaMOKruxNgQ6eJVXw /0MBlAo5SrCBiSama/w= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block fMYr9a89Xcj3rXgCwcUmEJuk28yTl5B/RAX3aqbb5WXRvwkjyflBZGjBgOk67G3LdmturwsvgVeD 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bsd-2-clause
46a9948b74be9007b06cf2e8a52d6776
0.94894
1.814717
false
false
false
false
rjarzmik/mips_processor
IF/Instruction_Provider_tb.vhd
1
5,791
------------------------------------------------------------------------------- -- Title : Testbench for design "Instruction_Provider" -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : Instruction_Provider_tb.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-12-03 -- Last update: 2017-01-03 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-03 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cpu_defs.all; use work.cache_defs.all; use work.instruction_defs.all; ------------------------------------------------------------------------------- entity Instruction_Provider_tb is end entity Instruction_Provider_tb; ------------------------------------------------------------------------------- architecture test of Instruction_Provider_tb is -- component generics constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0); subtype data_t is std_logic_vector(DATA_WIDTH - 1 downto 0); -- component ports signal clk : std_logic := '1'; signal rst : std_logic := '1'; signal o_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal o_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_valid : std_logic; signal o_do_step_pc : std_logic; -- L2 connections signal cls_creq : cache_request_t; signal cls_cresp : cache_response_t; signal o_L2c_req : std_logic; signal o_L2c_we : std_logic; signal o_L2c_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal i_L2c_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_L2c_wdata : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_L2c_valid : std_logic; signal next_pc : addr_t; signal after_pc : addr_t; signal next_itag : instr_tag_t := INSTR_TAG_NONE; signal after_itag : instr_tag_t := INSTR_TAG_NONE; begin -- architecture test -- component instantiation DUT : entity work.Instruction_Provider generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH) port map ( clk => clk, rst => rst, kill_req => '0', stall_req => '0', i_next_pc => next_pc, i_next_pc_instr_tag => next_itag, i_next_next_pc => after_pc, i_next_next_pc_instr_tag => after_itag, o_pc => o_pc, o_data => o_data, o_valid => o_valid, o_do_step_pc => o_do_step_pc, o_creq => cls_creq, i_cresp => cls_cresp); -- reset rst <= '0' after 12 ps; -- clock generation clk <= not clk after 5 ps; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here wait until Clk = '1'; end process WaveGen_Proc; pc_emulator : process(clk, rst) begin if rst = '1' then next_pc <= std_logic_vector(to_signed(0, ADDR_WIDTH)); after_pc <= std_logic_vector(to_unsigned(4, ADDR_WIDTH)); elsif rst = '0' and rising_edge(clk) then if o_do_step_pc = '1' then --if unsigned(next_pc) = to_unsigned(20, ADDR_WIDTH) then --next_pc <= std_logic_vector(to_unsigned(8, ADDR_WIDTH)); --after_pc <= std_logic_vector(to_unsigned(12, ADDR_WIDTH)); if unsigned(next_pc) = to_unsigned(16, ADDR_WIDTH) then next_pc <= std_logic_vector(to_unsigned(20, ADDR_WIDTH)); after_pc <= std_logic_vector(to_unsigned(8, ADDR_WIDTH)); else next_pc <= after_pc; after_pc <= std_logic_vector(unsigned(after_pc) + 4); end if; end if; end if; end process pc_emulator; cls : entity work.cache_line_streamer generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, DATAS_PER_LINE_WIDTH => DATAS_PER_LINE_WIDTH) port map ( clk => clk, rst => rst, i_creq => cls_creq, o_cresp => cls_cresp, o_memory_req => o_L2c_req, o_memory_we => o_L2c_we, o_memory_addr => o_L2c_addr, o_memory_wdata => o_L2c_wdata, i_memory_rdata => i_L2c_read_data, i_memory_done => i_L2c_valid); Simulated_Memory_1 : entity work.Simulated_Memory generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, MEMORY_LATENCY => 3) port map ( clk => clk, rst => rst, i_memory_req => o_L2c_req, i_memory_we => o_L2c_we, i_memory_addr => o_L2c_addr, i_memory_write_data => o_L2c_wdata, o_memory_read_data => i_L2c_read_data, o_memory_valid => i_L2c_valid); end architecture test; ------------------------------------------------------------------------------- configuration Instruction_Provider_tb_test_cfg of Instruction_Provider_tb is for test end for; end Instruction_Provider_tb_test_cfg; -------------------------------------------------------------------------------
gpl-3.0
b00981b19fc1f96969adb5a5d8108826
0.490243
3.621639
false
false
false
false
rjarzmik/mips_processor
MIPS_CPU_tb.vhd
1
17,320
------------------------------------------------------------------------------- -- Title : Testbench for design "MIPS_CPU" -- Project : ------------------------------------------------------------------------------- -- File : MIPS_CPU_tb.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-12 -- Last update: 2017-01-04 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-12 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.cpu_defs.all; use work.cache_defs.all; use work.instruction_defs.instr_tag_t; use work.instruction_defs.INSTR_TAG_FIRST_VALID; use work.instruction_prediction.prediction_t; ------------------------------------------------------------------------------- entity MIPS_CPU_tb is end entity MIPS_CPU_tb; ------------------------------------------------------------------------------- architecture rtl of MIPS_CPU_tb is -- component generics constant ADDR_WIDTH : integer := 32; constant DATA_WIDTH : integer := 32; constant NB_REGISTERS_GP : integer := 32; constant NB_REGISTERS_SPECIAL : integer := 2; constant DEBUG : boolean := false; -- clock signal Clk : std_logic := '1'; signal Rst : std_logic := '1'; signal stop : std_logic := '0'; -- L2 connections signal cls_creq : cache_request_t; signal cls_cresp : cache_response_t; signal o_memory_req : std_logic := '0'; signal o_memory_we : std_logic := '0'; signal o_memory_addr : addr_t; signal o_memory_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_memory_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_memory_valid : std_logic; -- Temprorary Data Memory interface signal o_mem_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal i_mem_rd_valid : std_logic; signal i_mem_rd_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal o_mem_wr_en : std_logic; signal o_mem_word_width : std_logic; signal o_mem_wr_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal i_mem_wr_ack : std_logic; -- Debug signals signal dbg_if_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_di_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_ex_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_mem_m0_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_mem_m1_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_mem_m2_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_wb_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_commited_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_ife_killed : std_logic; signal dbg_di_killed : std_logic; signal dbg_ex_killed : std_logic; signal dbg_mem_killed : std_logic; signal dbg_wb_killed : std_logic; signal dbg_pc_stalled : std_logic; signal dbg_ife_stalled : std_logic; signal dbg_di_stalled : std_logic; signal dbg_ex_stalled : std_logic; signal dbg_mem_stalled : std_logic; signal dbg_wb_stalled : std_logic; signal dbg_jump_pc : std_logic; signal dbg_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0); signal dbg_wb2di_reg1 : register_port_type; signal dbg_wb2di_reg2 : register_port_type; signal dbg_if_itag : instr_tag_t; signal dbg_di_itag : instr_tag_t; signal dbg_ex_itag : instr_tag_t; signal dbg_mem_m0_itag : instr_tag_t; signal dbg_mem_m1_itag : instr_tag_t; signal dbg_mem_m2_itag : instr_tag_t; signal dbg_wb_itag : instr_tag_t; signal dbg_commited_itag : instr_tag_t; signal dbg_if_prediction : prediction_t; function dbg_get_stage_letter( rst : std_logic; kill : std_logic; stall : std_logic; itag : instr_tag_t) return string is variable o : string(1 to 2); begin if rst = '1' then o := " R"; elsif kill = '1' then o := " K"; elsif stall = '1' then o := " S"; elsif not itag.valid then o := " -"; else if itag.tag < 10 then o := ' ' & integer'image(itag.tag); else o := integer'image(itag.tag); end if; end if; return o; end function dbg_get_stage_letter; function dbg_get_stage_string( stage : string; rst : std_logic; kill : std_logic; stall : std_logic; pc : std_logic_vector(ADDR_WIDTH - 1 downto 0); itag : instr_tag_t) return string is constant length : integer := stage'length + 5; variable head : string(1 to length); begin head(1 to stage'length) := stage; head(stage'length + 1) := '('; head(stage'length + 2 to stage'length + 3) := dbg_get_stage_letter(rst, kill, stall, itag); if stage /= "di" then head(stage'length + 4 to stage'length + 4) := ")"; return head(1 to length - 1); else head(stage'length + 4 to stage'length + 5) := ")@"; return head & to_hstring(pc); end if; end function dbg_get_stage_string; function dbg_get_done_string( stage : string; rst : std_logic; itag : instr_tag_t; pc : std_logic_vector(ADDR_WIDTH - 1 downto 0)) return string is constant length : integer := stage'length + 6; variable head : string(1 to length); variable state : string(1 to 3); begin if itag.is_branch then if itag.is_branch_taken then state := "BR+"; else state := "BR-"; end if; elsif itag.is_ja then state := "JA+"; elsif itag.is_jr then state := "JR+"; else state := "---"; end if; head(1 to stage'length) := stage; head(stage'length + 1) := '('; head(stage'length + 2 to stage'length + 4) := state; head(stage'length + 5 to stage'length + 6) := ")@"; return head & to_hstring(pc); end function dbg_get_done_string; function dbg_get_prediction_string(p : prediction_t; last_prediction : prediction_t) return string is variable move : string(1 to 4); begin if last_prediction.pc = p.pc and last_prediction.next_pc = p.next_pc and last_prediction.take_branch = p.take_branch then -- Nothing changed return ""; else if p.is_ja_jr then move := "JUMP"; elsif p.is_branch then case p.take_branch is when 0 => move := "BR--"; when 1 => move := "BR- "; when 2 => move := "BR+ "; when 3 => move := "BR++"; end case; else move := "----"; end if; if p.valid then return to_hstring(p.pc) & "->" & to_hstring(p.next_pc) & "=" & move; else return ""; end if; end if; end function dbg_get_prediction_string; function dbg_get_regname(regnum : natural) return string is variable name : string(1 to 4); begin case regnum is when 0 => name := "zero"; when 1 => name := "at "; when 2 => name := "v0 "; when 3 => name := "v1 "; when 4 => name := "a0 "; when 5 => name := "a1 "; when 6 => name := "a2 "; when 7 => name := "a3 "; when 8 => name := "t0 "; when 9 => name := "t1 "; when 10 => name := "t2 "; when 11 => name := "t3 "; when 12 => name := "t4 "; when 13 => name := "t5 "; when 14 => name := "t6 "; when 15 => name := "t7 "; when 16 => name := "s0 "; when 17 => name := "s1 "; when 18 => name := "s2 "; when 19 => name := "s3 "; when 20 => name := "s4 "; when 21 => name := "s5 "; when 22 => name := "s6 "; when 23 => name := "s7 "; when 24 => name := "t8 "; when 25 => name := "t9 "; when 26 => name := "k0 "; when 27 => name := "k1 "; when 28 => name := "gp "; when 29 => name := "sp "; when 30 => name := "fp "; when 31 => name := "ra "; when 32 => name := "mflo"; when 33 => name := "mfhi"; when others => name := " "; end case; return name; end function dbg_get_regname; function dbg_get_regwrite_string(ireg : register_port_type) return string is variable rname : string(1 to 4); variable rlen : natural := 4; begin rname := dbg_get_regname(ireg.idx); for i in 4 downto 1 loop if rname(i) = ' ' then rlen := rlen - 1; end if; end loop; if ireg.we = '1' then return "$" & rname(1 to rlen) & "=0x" & to_hstring(ireg.data) & " "; else return ""; end if; end function dbg_get_regwrite_string; function dbg_get_jump_string(is_jump : std_logic; jump_target : std_logic_vector) return string is begin if is_jump = '1' then return "$pc<=0x" & to_hstring(jump_target) & " "; else return ""; end if; end function dbg_get_jump_string; begin -- architecture rtl -- component instantiation DUT : entity work.MIPS_CPU generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, NB_REGISTERS_GP => NB_REGISTERS_GP, NB_REGISTERS_SPECIAL => NB_REGISTERS_SPECIAL) port map ( clk => clk, rst => rst, o_creq => cls_creq, i_cresp => cls_cresp, o_mem_addr => o_mem_addr, i_mem_rd_valid => i_mem_rd_valid, i_mem_rd_data => i_mem_rd_data, o_mem_wr_en => o_mem_wr_en, o_mem_word_width => o_mem_word_width, o_mem_wr_data => o_mem_wr_data, i_mem_wr_ack => i_mem_wr_ack, o_dbg_if_pc => dbg_if_pc, o_dbg_di_pc => dbg_di_pc, o_dbg_ex_pc => dbg_ex_pc, o_dbg_mem_m0_pc => dbg_mem_m0_pc, o_dbg_mem_m1_pc => dbg_mem_m1_pc, o_dbg_mem_m2_pc => dbg_mem_m2_pc, o_dbg_wb_pc => dbg_wb_pc, o_dbg_commited_pc => dbg_commited_pc, o_dbg_ife_killed => dbg_ife_killed, o_dbg_di_killed => dbg_di_killed, o_dbg_ex_killed => dbg_ex_killed, o_dbg_mem_killed => dbg_mem_killed, o_dbg_wb_killed => dbg_wb_killed, o_dbg_pc_stalled => dbg_pc_stalled, o_dbg_ife_stalled => dbg_ife_stalled, o_dbg_di_stalled => dbg_di_stalled, o_dbg_ex_stalled => dbg_ex_stalled, o_dbg_mem_stalled => dbg_mem_stalled, o_dbg_wb_stalled => dbg_wb_stalled, o_dbg_jump_pc => dbg_jump_pc, o_dbg_jump_target => dbg_jump_target, o_dbg_commited_instr_tag => dbg_commited_itag, o_dbg_wb2di_reg1 => dbg_wb2di_reg1, o_dbg_wb2di_reg2 => dbg_wb2di_reg2, o_dbg_if_instr_tag => dbg_if_itag, o_dbg_di_instr_tag => dbg_di_itag, o_dbg_ex_instr_tag => dbg_ex_itag, o_dbg_mem_m0_instr_tag => dbg_mem_m0_itag, o_dbg_mem_m1_instr_tag => dbg_mem_m1_itag, o_dbg_mem_m2_instr_tag => dbg_mem_m2_itag, o_dbg_wb_instr_tag => dbg_wb_itag, o_dbg_if_prediction => dbg_if_prediction ); cls : entity work.cache_line_streamer generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, DATAS_PER_LINE_WIDTH => DATAS_PER_LINE_WIDTH) port map ( clk => clk, rst => rst, i_creq => cls_creq, o_cresp => cls_cresp, o_memory_req => o_memory_req, o_memory_we => o_memory_we, o_memory_addr => o_memory_addr, o_memory_wdata => o_memory_write_data, i_memory_rdata => i_memory_read_data, i_memory_done => i_memory_valid); -- memory simulator Simulated_Memory_1 : entity work.Simulated_Memory generic map ( ADDR_WIDTH => ADDR_WIDTH, DATA_WIDTH => DATA_WIDTH, MEMORY_ADDR_WIDTH => 16, MEMORY_LATENCY => 3, DEBUG => DEBUG) port map ( clk => clk, rst => rst, i_memory_req => o_memory_req, i_memory_we => o_memory_we, i_memory_addr => o_memory_addr, i_memory_write_data => o_memory_write_data, o_memory_read_data => i_memory_read_data, o_memory_valid => i_memory_valid); -- reset Rst <= '0' or stop after 30 ps; -- clock generation Clk <= not stop and not Clk after 5 ps; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here wait until Clk = '1'; end process WaveGen_Proc; debug_proc : process(clk, rst) variable cycle : integer := 1; variable unusable_op : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => 'X'); variable passed_by_addr0 : natural := 0; variable fkill : std_logic; variable last_prediction : prediction_t; --alias dbg_mem1_pc is -- <<signal DUT.mem_stage.r1_dbg_mem_pc : std_logic_vector(ADDR_WIDTH -1 downto 0) >>; --alias dbg_mem2_pc is -- <<signal DUT.mem_stage.r2_dbg_mem_pc : std_logic_vector(ADDR_WIDTH -1 downto 0) >>; begin if not stop then if dbg_ife_killed = '1' or dbg_jump_pc = '1' then fkill := '1'; else fkill := '0'; end if; if rising_edge(clk) then cycle := cycle + 1; report "[" & integer'image(cycle) & "] " & dbg_get_stage_string("if", rst, fkill, dbg_ife_stalled, dbg_if_pc, dbg_if_itag) & " " & dbg_get_stage_string("di", rst, dbg_di_killed, dbg_di_stalled, dbg_di_pc, dbg_di_itag) & " " & dbg_get_stage_string("ex", rst, dbg_ex_killed, dbg_ex_stalled, dbg_ex_pc, dbg_ex_itag) & " " & dbg_get_stage_string("m0", rst, dbg_mem_killed, dbg_mem_stalled, dbg_mem_m0_pc, dbg_mem_m0_itag) & " " & dbg_get_stage_string("m1", rst, dbg_mem_killed, dbg_mem_stalled, dbg_mem_m1_pc, dbg_mem_m1_itag) & " " & dbg_get_stage_string("m2", rst, dbg_mem_killed, dbg_mem_stalled, dbg_mem_m2_pc, dbg_mem_m2_itag) & " " & dbg_get_stage_string("wb", rst, dbg_wb_killed, dbg_wb_stalled, dbg_wb_pc, dbg_wb_itag) & " " & dbg_get_done_string("done", rst, dbg_commited_itag, dbg_commited_pc) & " " & dbg_get_regwrite_string(dbg_wb2di_reg1) & dbg_get_regwrite_string(dbg_wb2di_reg2) & dbg_get_jump_string(dbg_jump_pc, dbg_jump_target) & " " & dbg_get_prediction_string(dbg_if_prediction, last_prediction); if dbg_commited_pc /= unusable_op then if to_integer(unsigned(dbg_commited_pc)) = 0 then passed_by_addr0 := passed_by_addr0 + 1; end if; end if; if passed_by_addr0 > 4 then report "PC rolled over to 0, ending simulation." severity error; stop <= '1'; end if; last_prediction := dbg_if_prediction; end if; end if; end process debug_proc; -- purpose: memory -- type : sequential -- inputs : clk, rst -- outputs: mem : process (clk, rst) is begin -- process mem if rst = '1' then -- asynchronous reset (active low) i_mem_rd_valid <= '0'; i_mem_rd_data <= (others => '0'); i_mem_wr_ack <= '0'; elsif stop = '0' and rising_edge(clk) then -- rising clock edge i_mem_wr_ack <= '0'; if o_mem_wr_en = '1' then i_mem_rd_valid <= '0'; i_mem_rd_data <= i_mem_rd_data; assert i_mem_wr_ack = '0' report "Invalid transaction" severity error; i_mem_wr_ack <= '1'; else -- copy rd @ to data and change data order (ABCD -> DCBA) i_mem_rd_data <= o_mem_addr(3 downto 0) & o_mem_addr(7 downto 4) & o_mem_addr(11 downto 8) & o_mem_addr(15 downto 12) & o_mem_addr(19 downto 16) & o_mem_addr(23 downto 20) & o_mem_addr(27 downto 24) & o_mem_addr(31 downto 28); i_mem_rd_valid <= '1'; end if; end if; end process mem; end architecture rtl; ------------------------------------------------------------------------------- configuration MIPS_CPU_tb_rtl_cfg of MIPS_CPU_tb is for rtl end for; end MIPS_CPU_tb_rtl_cfg; -------------------------------------------------------------------------------
gpl-3.0
df35e632bbc8da50cf7849aeeb3927f5
0.508545
3.294028
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/output_blk.vhd
2
27,142
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bsd-2-clause
993983dc9c010a10915db5167520219f
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tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/srl_fifo.vhd
1
11,966
------------------------------------------------------------------------------- -- $Id: srl_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- SRL_FIFO entity and architecture ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the user’s sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: srl_fifo.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- srl_fifo.vhd -- ------------------------------------------------------------------------------- -- Author: goran -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- goran 2001-05-11 First Version -- KC 2001-06-20 Added Addr as an output port, for use as an occupancy -- value -- -- DCW 2002-03-12 Structural implementation of synchronous reset for -- Data_Exists DFF (using FDR) -- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims -- -- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR -- component declarations -- -- DET 1/17/2008 v3_00_a -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.all; entity SRL_FIFO is generic ( C_DATA_BITS : natural := 8; C_DEPTH : natural := 16; C_XON : boolean := false ); port ( Clk : in std_logic; Reset : in std_logic; FIFO_Write : in std_logic; Data_In : in std_logic_vector(0 to C_DATA_BITS-1); FIFO_Read : in std_logic; Data_Out : out std_logic_vector(0 to C_DATA_BITS-1); FIFO_Full : out std_logic; Data_Exists : out std_logic; Addr : out std_logic_vector(0 to 3) -- Added Addr as a port ); end entity SRL_FIFO; architecture IMP of SRL_FIFO is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; component SRL16E is -- pragma translate_off generic ( INIT : bit_vector := X"0000" ); -- pragma translate_on port ( CE : in std_logic; D : in std_logic; Clk : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic); end component SRL16E; component LUT4 generic( INIT : bit_vector := X"0000" ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic); end component; component MULT_AND port ( I0 : in std_logic; I1 : in std_logic; LO : out std_logic); end component; component MUXCY_L port ( DI : in std_logic; CI : in std_logic; S : in std_logic; LO : out std_logic); end component; component XORCY port ( LI : in std_logic; CI : in std_logic; O : out std_logic); end component; component FDRE is port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic); end component FDRE; component FDR is port ( Q : out std_logic; C : in std_logic; D : in std_logic; R : in std_logic); end component FDR; signal addr_i : std_logic_vector(0 to 3); signal buffer_Full : std_logic; signal buffer_Empty : std_logic; signal next_Data_Exists : std_logic; signal data_Exists_I : std_logic; signal valid_Write : std_logic; signal hsum_A : std_logic_vector(0 to 3); signal sum_A : std_logic_vector(0 to 3); signal addr_cy : std_logic_vector(0 to 4); begin -- architecture IMP buffer_Full <= '1' when (addr_i = "1111") else '0'; FIFO_Full <= buffer_Full; buffer_Empty <= '1' when (addr_i = "0000") else '0'; next_Data_Exists <= (data_Exists_I and not buffer_Empty) or (buffer_Empty and FIFO_Write) or (data_Exists_I and not FIFO_Read); Data_Exists_DFF : FDR port map ( Q => data_Exists_I, -- [out std_logic] C => Clk, -- [in std_logic] D => next_Data_Exists, -- [in std_logic] R => Reset); -- [in std_logic] Data_Exists <= data_Exists_I; valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full); addr_cy(0) <= valid_Write; Addr_Counters : for I in 0 to 3 generate hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty); MUXCY_L_I : MUXCY_L port map ( DI => addr_i(I), -- [in std_logic] CI => addr_cy(I), -- [in std_logic] S => hsum_A(I), -- [in std_logic] LO => addr_cy(I+1)); -- [out std_logic] XORCY_I : XORCY port map ( LI => hsum_A(I), -- [in std_logic] CI => addr_cy(I), -- [in std_logic] O => sum_A(I)); -- [out std_logic] FDRE_I : FDRE port map ( Q => addr_i(I), -- [out std_logic] C => Clk, -- [in std_logic] CE => data_Exists_I, -- [in std_logic] D => sum_A(I), -- [in std_logic] R => Reset); -- [in std_logic] end generate Addr_Counters; FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate SRL16E_I : SRL16E -- pragma translate_off generic map ( INIT => x"0000") -- pragma translate_on port map ( CE => valid_Write, -- [in std_logic] D => Data_In(I), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => addr_i(0), -- [in std_logic] A1 => addr_i(1), -- [in std_logic] A2 => addr_i(2), -- [in std_logic] A3 => addr_i(3), -- [in std_logic] Q => Data_Out(I)); -- [out std_logic] end generate FIFO_RAM; ------------------------------------------------------------------------------- -- INT_ADDR_PROCESS ------------------------------------------------------------------------------- -- This process assigns the internal address to the output port ------------------------------------------------------------------------------- INT_ADDR_PROCESS:process (addr_i) begin -- process Addr <= addr_i; end process; end architecture IMP;
bsd-2-clause
dfebab07317953cabe84912d8537ce01
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Yarr/Yarr-fw
rtl/kintex7/rx-core/wb_rx_core.vhd
1
13,023
-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: RX core -- # Outputs are synchronous to wb_clk_i -- #################################### -- # Adress Map: -- # Adr[3:0]: -- # 0x0 : RX Enable Mask library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.VComponents.all; entity wb_rx_core is generic ( g_NUM_RX : integer range 1 to 32 := 1; g_TYPE : string := "FEI4"; g_NUM_LANES : integer range 1 to 4 := 1 ); port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Wishbone slave interface wb_adr_i : in std_logic_vector(31 downto 0); wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic; wb_stb_i : in std_logic; wb_we_i : in std_logic; wb_ack_o : out std_logic; wb_stall_o : out std_logic; -- RX IN rx_clk_i : in std_logic; rx_serdes_clk_i : in std_logic; rx_data_i_p : in std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0); rx_data_i_n : in std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0); trig_tag_i : in std_logic_vector(31 downto 0); -- RX OUT (sync to sys_clk) rx_valid_o : out std_logic; rx_data_o : out std_logic_vector(63 downto 0); busy_o : out std_logic; debug_o : out std_logic_vector(31 downto 0) ); end wb_rx_core; architecture behavioral of wb_rx_core is function log2_ceil(val : integer) return natural is variable result : natural; begin for i in 0 to g_NUM_RX-1 loop if (val <= (2 ** i)) then result := i; exit; end if; end loop; return result; end function; constant c_ALL_ZEROS : std_logic_vector(g_NUM_RX-1 downto 0) := (others => '0'); component frr_arbiter generic ( g_CHANNELS : integer := g_NUM_RX ); port ( -- sys connect clk_i : in std_logic; rst_i : in std_logic; -- requests req_i : in std_logic_vector(g_CHANNELS-1 downto 0); en_i : in std_logic_vector(g_CHANNELS-1 downto 0); -- grants gnt_o : out std_logic_vector(g_CHANNELS-1 downto 0) ); end component frr_arbiter; component fei4_rx_channel port ( -- Sys connect rst_n_i : in std_logic; clk_160_i : in std_logic; clk_640_i : in std_logic; enable_i : in std_logic; -- Input rx_data_i : in std_logic; trig_tag_i : in std_logic_vector(31 downto 0); -- Output rx_data_o : out std_logic_vector(25 downto 0); rx_valid_o : out std_logic; rx_stat_o : out std_logic_vector(7 downto 0); rx_data_raw_o : out std_logic_vector(7 downto 0) ); end component; component aurora_rx_channel generic ( g_NUM_LANES : integer range 1 to 4 := g_NUM_LANES ); port ( rst_n_i : in std_logic; clk_rx_i : in std_logic; -- Fabric clock (serdes/8) clk_serdes_i : in std_logic; -- IO clock -- Input enable_i : in std_logic; rx_data_i_p : in std_logic_vector(g_NUM_LANES-1 downto 0); rx_data_i_n : in std_logic_vector(g_NUM_LANES-1 downto 0); rx_polarity_i : in std_logic_vector(g_NUM_LANES-1 downto 0); trig_tag_i : in std_logic_vector(63 downto 0); -- Output rx_data_o : out std_logic_vector(63 downto 0); rx_valid_o : out std_logic; rx_stat_o : out std_logic_vector(7 downto 0) ); end component aurora_rx_channel; COMPONENT rx_channel_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC ); END COMPONENT; COMPONENT ila_rx_dma_wb PORT ( clk : IN STD_LOGIC; probe0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); probe1 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); probe2 : IN STD_LOGIC_VECTOR(63 DOWNTO 0); probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT ; type rx_data_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(63 downto 0); type rx_data_fifo_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(63 downto 0); type rx_stat_array is array (g_NUM_RX-1 downto 0) of std_logic_vector(7 downto 0); signal rx_data_i : std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0); signal rx_polarity : std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0); signal rx_polarity_t : std_logic_vector((g_NUM_RX*g_NUM_LANES)-1 downto 0); signal rx_data : rx_data_array; signal rx_valid : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_stat : rx_stat_array; signal rx_data_raw : rx_stat_array; signal rx_fifo_dout :rx_data_fifo_array; signal rx_fifo_dout_t :rx_data_fifo_array; signal rx_fifo_din : rx_data_fifo_array; signal rx_fifo_full : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_empty : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_empty_t : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_rden : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_rden_t : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_fifo_wren : std_logic_vector(g_NUM_RX-1 downto 0); signal rx_enable : std_logic_vector(31 downto 0); signal rx_enable_d : std_logic_vector(31 downto 0); signal rx_enable_dd : std_logic_vector(31 downto 0); signal rx_status : std_logic_vector(31 downto 0); signal rx_status_s : std_logic_vector(31 downto 0); signal channel : integer range 0 to g_NUM_RX-1; signal debug : std_logic_vector(31 downto 0); begin debug_o <= debug; debug(7 downto 0) <= rx_stat(0); debug(15 downto 8) <= rx_data_raw(0); debug(16) <= rx_valid(0); -- wb_core_debug : ila_rx_dma_wb -- PORT MAP ( -- clk => wb_clk_i, -- probe0 => (others => '0'), -- probe1 => (others => '0'), -- probe2 => (others => '0'), -- probe3(0) => rx_fifo_empty(0), -- probe4(0) => rx_fifo_empty(1), -- probe5(0) => rx_enable_d(0), -- probe6(0) => rx_enable_d(1), -- probe7(0) => '0', -- probe8 => (others => '0'), -- probe9(0) => '0', -- probe10(0) => rx_fifo_rden_t(0), -- probe11(0) => rx_fifo_rden_t(1) -- ); wb_proc: process (wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then wb_dat_o <= (others => '0'); wb_ack_o <= '0'; rx_enable <= (others => '0'); wb_stall_o <= '0'; rx_enable_d <= (others => '0'); rx_polarity <= (others => '0'); elsif rising_edge(wb_clk_i) then wb_ack_o <= '0'; rx_enable_d <= rx_enable; if (wb_cyc_i = '1' and wb_stb_i = '1') then if (wb_we_i = '1') then if (wb_adr_i(3 downto 0) = x"0") then -- Set enable mask wb_ack_o <= '1'; rx_enable <= wb_dat_i; elsif (wb_adr_i(3 downto 0) = x"2") then -- Set RX polarity wb_ack_o <= '1'; rx_polarity <= wb_dat_i((g_NUM_RX*g_NUM_LANES)-1 downto 0); else wb_ack_o <= '1'; end if; else if (wb_adr_i(3 downto 0) = x"0") then -- Read enable mask wb_dat_o <= rx_enable; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"1") then -- Link status wb_dat_o <= rx_status; wb_ack_o <= '1'; elsif (wb_adr_i(3 downto 0) = x"2") then -- RX polarity wb_dat_o <= (others => '0'); wb_dat_o((g_NUM_RX*g_NUM_LANES)-1 downto 0) <= rx_polarity; wb_ack_o <= '1'; else wb_dat_o <= x"DEADBEEF"; wb_ack_o <= '1'; end if; end if; end if; end if; end process wb_proc; -- Arbiter cmp_frr_arbiter : frr_arbiter port map ( clk_i => wb_clk_i, rst_i => not rst_n_i, req_i => not rx_fifo_empty_t, en_i => rx_enable_dd(g_NUM_RX-1 downto 0), gnt_o => rx_fifo_rden_t ); --rx_valid_o <= '0' when (unsigned(rx_fifo_rden) = 0 or ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden)) else '1'; --rx_data_o <= x"DEADBEEF" when (unsigned(rx_fifo_rden) = 0) else rx_fifo_dout(log2_ceil(to_integer(unsigned(rx_fifo_rden)))); reg_proc : process(wb_clk_i, rst_n_i) begin if (rst_n_i = '0') then --rx_fifo_rden <= (others => '0'); rx_valid_o <= '0'; channel <= 0; rx_fifo_dout <= (others => (others => '0')); rx_fifo_rden <= (others => '0'); rx_fifo_empty <= (others => '0'); elsif rising_edge(wb_clk_i) then rx_fifo_dout <= rx_fifo_dout_t; rx_fifo_rden <= rx_fifo_rden_t; rx_fifo_empty <= rx_fifo_empty_t; channel <= log2_ceil(to_integer(unsigned(rx_fifo_rden_t))); if (unsigned(rx_fifo_rden) = 0) then -- no channel being filled right now rx_valid_o <= '0'; rx_data_o <= x"DEADBEEFDEADBEEF"; elsif ((rx_fifo_rden and rx_fifo_empty) = rx_fifo_rden) then -- channel being read is empty, add empty word rx_valid_o <= '1'; rx_data_o <= x"FFFFDEADFFFFDEAD"; else -- channel being read is not empty rx_valid_o <= '1'; rx_data_o <= rx_fifo_dout(channel); end if; end if; end process reg_proc; fei4_iobuf: if g_TYPE = "FEI4" generate rx_loop: for I in 0 to (g_NUM_RX*g_NUM_LANES)-1 generate begin rx_buf : IBUFDS generic map ( DIFF_TERM => TRUE, -- Differential Termination IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards IOSTANDARD => "LVDS_25") port map ( O => rx_data_i(I), -- Buffer output I => rx_data_i_p(I), -- Diff_p buffer input (connect directly to top-level port) IB => rx_data_i_n(I) -- Diff_n buffer input (connect directly to top-level port) ); end generate; end generate fei4_iobuf; enable_sync: process (rx_clk_i, rst_n_i) begin if (rst_n_i = '0') then rx_enable_dd <= (others => '0'); rx_status <= (others => '0'); rx_polarity_t <= (others => '0'); elsif rising_edge(rx_clk_i) then rx_enable_dd <= rx_enable_d; rx_status <= rx_status_s; rx_polarity_t <= rx_polarity; end if; end process enable_sync; -- Generate Rx Channels busy_o <= '0' when (rx_fifo_full = c_ALL_ZEROS) else '1'; rx_channels: for I in 0 to g_NUM_RX-1 generate begin fei4_type: if g_TYPE = "FEI4" generate cmp_fei4_rx_channel: fei4_rx_channel PORT MAP( rst_n_i => rst_n_i, clk_160_i => rx_clk_i, clk_640_i => rx_serdes_clk_i, enable_i => rx_enable_dd(I), rx_data_i => rx_data_i(I), trig_tag_i => trig_tag_i, rx_data_o => rx_data(I)(25 downto 0), rx_valid_o => rx_valid(I), rx_stat_o => rx_stat(I), rx_data_raw_o => rx_data_raw(I) ); rx_fifo_din(I) <= x"03000000" & STD_LOGIC_VECTOR(TO_UNSIGNED(I,6)) & rx_data(I)(25 downto 0); end generate fei4_type; rd53_type: if g_TYPE = "RD53" generate cmp_aurora_rx_channel : aurora_rx_channel PORT MAP ( rst_n_i => rst_n_i, clk_rx_i => rx_clk_i, clk_serdes_i => rx_serdes_clk_i, enable_i => rx_enable_dd(I), rx_data_i_p => rx_data_i_p((I+1)*g_NUM_LANES-1 downto (I*g_NUM_LANES)), rx_data_i_n => rx_data_i_n((I+1)*g_NUM_LANES-1 downto (I*g_NUM_LANES)), rx_polarity_i => rx_polarity_t((I+1)*g_NUM_LANES-1 downto (I*g_NUM_LANES)), trig_tag_i => x"00000000" & trig_tag_i, rx_data_o => rx_data(I), rx_valid_o => rx_valid(I), rx_stat_o => rx_stat(I) ); rx_status_s(I) <= '1' when rx_stat(I)(1) = '1' else '1' when rx_enable_dd(I) = '0' else '0'; rx_fifo_din(I) <= rx_data(I); end generate rd53_type; rx_fifo_wren(I) <= rx_valid(I) and rx_enable_dd(I); cmp_rx_channel_fifo : rx_channel_fifo PORT MAP ( rst => not rst_n_i, wr_clk => rx_clk_i, rd_clk => wb_clk_i, din => rx_fifo_din(I), wr_en => rx_fifo_wren(I), rd_en => rx_fifo_rden_t(I), dout => rx_fifo_dout_t(I), full => rx_fifo_full(I), empty => rx_fifo_empty_t(I) ); end generate; end behavioral;
gpl-3.0
9b55971ecd114d8434b458a0f453f775
0.546571
2.815784
false
false
false
false
wklimann/PCM3168
CLK_GEN/CLK_GEN_tb.vhd
1
1,434
-------------------------------------------------------------------------------- -- Engineer: Klimann Wendlin -- -- Create Date: 07:25:11 11/Okt/2013 -- Design Name: clk_gen_tb -- Description: -- -- VHDL Test Bench for module: clk_gen -- -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY clk_gen_tb_vhd IS END clk_gen_tb_vhd; ARCHITECTURE behavior OF clk_gen_tb_vhd IS constant width : integer := 24; -- Component Declaration for the Unit Under Test (UUT) COMPONENT clk_gen generic(width : integer := width); PORT( CLK : IN std_logic; RESET : IN std_logic; LR_CLK : OUT std_logic; BIT_CLK : OUT std_logic ); END COMPONENT; --Inputs SIGNAL CLK : std_logic := '0'; SIGNAL RESET : std_logic := '0'; --Outputs SIGNAL LR_CLK : std_logic := '0'; SIGNAL BIT_CLK : std_logic := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: clk_gen PORT MAP( CLK => CLK, RESET => RESET, LR_CLK => LR_CLK, BIT_CLK => BIT_CLK ); p_reset : process begin RESET <= '0'; --LR_CK <= '1'; wait for 100 ns; RESET <= '1'; -- Reset finished wait; end process p_reset; p_clk : process begin CLK <= '0'; wait for 10 ns; CLK <= '1'; wait for 10 ns; end process p_clk; END;
gpl-2.0
cf29d76996dbf3fb615447fdf1df0e5e
0.526499
3.051064
false
false
false
false
rjarzmik/mips_processor
Caches/cache_defs.vhd
1
8,140
------------------------------------------------------------------------------- -- Title : Cache definitions -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : cache_defs.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-12-15 -- Last update: 2017-01-01 -- Platform : -- Standard : VHDL'08 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-15 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; ------------------------------------------------------------------------------- package cache_defs is -- Constants for Singleport_Associative_Cache_tb constant ADDR_WIDTH : natural := 32; constant DATA_WIDTH : natural := 32; constant DATAS_PER_LINE_WIDTH : natural := 1; constant INDEX_WIDTH : natural := 1; constant WAYS_WIDTH : natural := 1; --constant ADDR_WIDTH : natural := 32; --constant DATA_WIDTH : natural := 32; --constant DATAS_PER_LINE_WIDTH : natural := 4; --constant INDEX_WIDTH : natural := 7; --constant WAYS_WIDTH : natural := 2; -- Infered constants constant NB_LINES : natural := 2**INDEX_WIDTH; constant DATAS_PER_LINE : natural := 2**DATAS_PER_LINE_WIDTH; constant NB_WAYS : natural := 2**WAYS_WIDTH; constant ADDR_DATA_NBITS : natural := integer(log2(real(DATA_WIDTH / 8))); constant ADDR_DATALINE_NBITS : natural := ADDR_DATA_NBITS + DATAS_PER_LINE_WIDTH + INDEX_WIDTH; constant TAG_WIDTH : natural := ADDR_WIDTH - ADDR_DATALINE_NBITS; subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0); subtype data_t is std_logic_vector(DATA_WIDTH - 1 downto 0); type data_vector is array(natural range <>) of data_t; subtype cache_line_selector_t is std_logic_vector(0 to DATAS_PER_LINE - 1); subtype way_selector_t is std_logic_vector(0 to NB_WAYS - 1); subtype cache_line_t is data_vector(0 to DATAS_PER_LINE - 1); subtype flat_cache_line_t is std_logic_vector(DATAS_PER_LINE * DATA_WIDTH - 1 downto 0); type cache_line_vector is array (natural range <>) of cache_line_t; type flat_cache_line_vector is array (natural range <>) of flat_cache_line_t; type cls_op is (cls_none, cls_refill, cls_flush); type cache_request_t is record req : cls_op; addr : addr_t; sel : cache_line_selector_t; cline : cache_line_t; end record; type cache_response_t is record cline : cache_line_t; sel : cache_line_selector_t; rdy : std_logic; done : std_logic; end record; -- Tag entry --- entry = [ [valid_bits_of_line] [dirty_bits_of_line] [tag_context] [tag] --- +-------------------------------------------------------+ --- | Tag context | Dirty line bits | Valid line bits | Tag | --- +-------------------------------------------------------+ subtype tag_t is std_logic_vector(TAG_WIDTH - 1 downto 0); subtype tag_context_t is std_logic_vector(1 downto 0); type tag_entry_t is record ctxt : tag_context_t; valids : cache_line_selector_t; dirtys : cache_line_selector_t; tag : tag_t; end record; type tag_entry_vector is array(natural range <>) of tag_entry_t; constant TAG_ENTRY_EMPTY : tag_entry_t := ( (others => '0'), (others => '0'), (others => '0'), (others => '0')); -- Eviction types --- eviction_entry = [ [alloc_counter] ] constant alloc_entry_len : natural := ((WAYS_WIDTH * NB_WAYS + 7) / 8) * 8; subtype alloc_entry_t is std_logic_vector(0 to alloc_entry_len - 1); type mem_tag_status_t is record valid : std_logic; dirty : std_logic; end record; type cache_state is (s_idle, s_searching, s_prepare_flushing, s_flush_outer, s_flushing, s_refill_memory, s_refill_cache, s_writethrough, s_write_allocate); -- Cache statistics type cache_stats_t is record read_hits : natural; write_hits : natural; read_misses : natural; write_misses : natural; write_throughs : natural; write_backs : natural; flushes : natural; refills : natural; end record cache_stats_t; function get_address_index(i_address : std_logic_vector) return natural; function get_address_tag(i_address : std_logic_vector) return std_logic_vector; function get_data_set_index(i_address : std_logic_vector) return natural; function get_address(tag : tag_t; index : natural range 0 to NB_LINES - 1; data_in_line : natural range 0 to DATAS_PER_LINE - 1) return addr_t; function data_is_valid(addr : addr_t; te : tag_entry_t) return std_logic; function dataline_is_dirty(te : tag_entry_t) return boolean; function to_way_selector(way : natural range 0 to NB_WAYS - 1) return way_selector_t; function to_cacheline_selector(addr : addr_t) return cache_line_selector_t; end package cache_defs; package body cache_defs is function get_address_index(i_address : std_logic_vector) return natural is variable idx : natural; begin idx := to_integer(unsigned(i_address( ADDR_DATALINE_NBITS - 1 downto DATAS_PER_LINE_WIDTH + ADDR_DATA_NBITS))); return idx; end function get_address_index; function get_address_tag(i_address : std_logic_vector) return std_logic_vector is variable tag : tag_t; begin tag := i_address(i_address'length - 1 downto i_address'length - TAG_WIDTH); return tag; end function get_address_tag; function get_data_set_index(i_address : std_logic_vector) return natural is variable set_index : natural range 0 to DATAS_PER_LINE - 1; begin if DATAS_PER_LINE = 1 then set_index := 0; else set_index := to_integer(unsigned(i_address( DATAS_PER_LINE_WIDTH + ADDR_DATA_NBITS - 1 downto ADDR_DATA_NBITS))); end if; return set_index; end function get_data_set_index; function get_address(tag : tag_t; index : natural range 0 to NB_LINES - 1; data_in_line : natural range 0 to DATAS_PER_LINE - 1) return addr_t is begin return tag & std_logic_vector(to_unsigned(index, INDEX_WIDTH) & to_unsigned(data_in_line, DATAS_PER_LINE_WIDTH) & to_unsigned(0, ADDR_DATA_NBITS)); end function get_address; function data_is_valid(addr : addr_t; te : tag_entry_t) return std_logic is variable data_in_line : natural range 0 to DATAS_PER_LINE - 1; begin data_in_line := get_data_set_index(addr); return te.valids(data_in_line); end function data_is_valid; function dataline_is_dirty(te : tag_entry_t) return boolean is constant z : cache_line_selector_t := (others => '0'); variable o : boolean; begin o := te.dirtys /= z; return o; end function dataline_is_dirty; function to_way_selector(way : natural range 0 to NB_WAYS - 1) return way_selector_t is variable ws : way_selector_t := (others => '0'); begin for i in ws'range loop if i = way then ws(i) := '1'; end if; end loop; return ws; end function to_way_selector; function to_cacheline_selector(addr : addr_t) return cache_line_selector_t is variable clsel : cache_line_selector_t := (others => '0'); variable data_in_line : natural range 0 to DATAS_PER_LINE - 1; begin data_in_line := get_data_set_index(addr); clsel(data_in_line) := '1'; return clsel; end function to_cacheline_selector; end package body cache_defs;
gpl-3.0
37efd609964ff5d1e1cb032119468df0
0.579853
3.60177
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/rd_pe_as.vhd
2
25,238
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Pg6aok5Vq/p86aDF2gpXOXP48v1CRRpaRij2s+uQ0+X4vx8S7tXBjQPu+8NIW/vGpNBtyzN1sVkC UoHzSd21/A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block gUJrwsqWshgEBipBkgjgEC6nR7K4TS9HaoK5H3qvHXFXpvZGPekrMCPWlaj4aFNjQVavLRFPf6o3 A0l0Ip1QOw+niXzC5gsBL3rJEZy1qhnRryRS54VanuBZ2fW2/TEy0cinRI55ZyJYFjuod0VVx8Qw heaXTgRUK5PitKieR1M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_omit_wrap.vhd
1
16,832
------------------------------------------------------------------------------- -- axi_datamover_mm2s_omit_wrap.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_omit_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Omit Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_mm2s_omit_wrap.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 6/20/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Added 512 and 1024 data width support -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_omit_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 0; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 0; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input -------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------- -- MM2S Halt request input control------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ----------------------------------------------------------- -- Error discrete output ---------------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- ----------------------------------------------------------- -- Optional MM2S Command and Status clock and Reset ----------- -- Only used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- --------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- ---------------------------------------------------------------- -- Address Posting contols ------------------------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- ---------------------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------ mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ----------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ----------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ---------------------------------------------------------------------- ); end entity axi_datamover_mm2s_omit_wrap; architecture implementation of axi_datamover_mm2s_omit_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; begin --(architecture implementation) mm2s_dbg_data <= X"BEEF0000" ; -- 32 bit Constant indicating OMIT type -- Just tie off output ports mm2s_halt_cmplt <= mm2s_halt ; mm2s_err <= '0' ; mm2s_cmd_wready <= '0' ; mm2s_sts_wvalid <= '0' ; mm2s_sts_wdata <= (others => '0'); mm2s_sts_wstrb <= (others => '0'); mm2s_sts_wlast <= '0' ; mm2s_arid <= (others => '0'); mm2s_araddr <= (others => '0'); mm2s_arlen <= (others => '0'); mm2s_arsize <= (others => '0'); mm2s_arburst <= (others => '0'); mm2s_arprot <= (others => '0'); mm2s_arcache <= (others => '0'); mm2s_aruser <= (others => '0'); mm2s_arvalid <= '0' ; mm2s_rready <= '0' ; mm2s_strm_wdata <= (others => '0'); mm2s_strm_wstrb <= (others => '0'); mm2s_strm_wlast <= '0' ; mm2s_strm_wvalid <= '0' ; mm2s_addr_req_posted <= '0' ; mm2s_rd_xfer_cmplt <= '0' ; -- Input ports are ignored end implementation;
bsd-2-clause
e9e3306365c0b9d3025eb08bbf09c4d8
0.41433
5.097517
false
false
false
false
Yarr/Yarr-fw
syn/kintex7/rd53_ohio_4x4_640Mbps/board_pkg.vhd
1
952
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library work; use work.hw_type_pkg.all; package board_pkg is constant c_FW_IDENT : std_logic_vector(31 downto 0) := c_HW_IDENT & x"030231"; constant c_TX_ENCODING : string := "OSERDES"; constant c_TX_CHANNELS : integer := 4; constant c_RX_CHANNELS : integer := 4; constant c_FE_TYPE : string := "RD53"; constant c_RX_NUM_LANES : integer := 4; constant c_RX_SPEED : string := "0640"; constant c_TX_IDLE_WORD : std_logic_vector(31 downto 0) := x"AAAAAAAA"; constant c_TX_SYNC_WORD : std_logic_vector(31 downto 0) := x"817e817e"; constant c_TX_SYNC_INTERVAL : unsigned(7 downto 0) := to_unsigned(16,8); constant c_TX_AZ_WORD : std_logic_vector(31 downto 0) := x"00000000"; constant c_TX_AZ_INTERVAL : unsigned(15 downto 0) := to_unsigned(500,16); constant c_TX_40_DIVIDER : unsigned(3 downto 0) := to_unsigned(4,4); end board_pkg;
gpl-3.0
625ab0bc1ca4c32a381e230a223319f0
0.664916
3.003155
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rd_sf.vhd
1
76,429
------------------------------------------------------------------------------- -- axi_datamover_rd_sf.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_rd_sf.vhd -- -- Description: -- This file implements the AXI DataMover Read (MM2S) Store and Forward module. -- The design utilizes the AXI DataMover's new address pipelining -- control function. The design is such that predictive address -- pipelining can be supported on the AXI Read Bus without over-commiting -- the internal Data FIFO and potentially throttling the Read Data Channel -- if the Data FIFO goes full. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/21/2011 Initial Version for 13.3 -- -- DET 6/10/2011 Initial Version for 13.3 -- ~~~~~~ -- -- Per CR613147 -- - Added the DRE Flush control input from the RDC. This passes through -- the Data FIFO (just like sin2sf_tlast) and out the downsizer to -- the sf2dre_flush output. -- ^^^^^^ -- -- DET 9/1/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- - Fixed Lint reported excesive line length for lines 1388 and 1564. -- - Removed commented-out code as part of general cleanup. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; use proc_common_v4_0.proc_common_pkg.clog2; use proc_common_v4_0.srl_fifo_f; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_sfifo_autord; use axi_datamover_v5_1.axi_datamover_fifo; ------------------------------------------------------------------------------- entity axi_datamover_rd_sf is generic ( C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512; -- Sets the desired depth of the internal Data FIFO. C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates the max burst length being used by the external -- AXI4 Master for each AXI4 transfer request. C_DRE_IS_USED : Integer range 0 to 1 := 0; -- Indicates if the external Master is utilizing a DRE on -- the stream input to this module. C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1; -- Specifies the depth of the internal dre control queue fifo C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE alignment control ports C_MMAP_DWIDTH : Integer range 32 to 1024 := 64; -- Sets the AXI4 Memory Mapped Bus Data Width C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the Stream Data Width for the Input and Output -- Data streams. C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2; -- Sets the bit width of the starting address offset port -- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH) C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Indicates the width of the Tag field of the input DRE command C_FAMILY : String := "virtex7" -- Indicates the target FPGA Family. ); port ( -- Clock and Reset inputs -------------------------------------------- -- aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- reset : in std_logic; -- -- Reset used for the internal syncronization logic -- ---------------------------------------------------------------------- -- DataMover Read Side Address Pipelining Control Interface ---------- -- ok_to_post_rd_addr : Out Std_logic; -- -- Indicates that the transfer token pool has at least -- -- one token available to borrow -- -- rd_addr_posted : In std_logic; -- -- Indication that a read address has been posted to AXI4 -- -- rd_xfer_cmplt : In std_logic; -- -- Indicates that the Datamover has completed a Read Data -- -- transfer on the AXI4 -- ---------------------------------------------------------------------- -- Read Side Stream In from DataMover MM2S Read Data Controller ---------------------- -- sf2sin_tready : Out Std_logic; -- -- DRE Stream READY input -- -- sin2sf_tvalid : In std_logic; -- -- DRE Stream VALID Output -- -- sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); -- -- DRE Stream DATA input -- -- sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); -- -- DRE Stream STRB input -- -- sin2sf_tlast : In std_logic; -- -- DRE Xfer LAST input -- -------------------------------------------------------------------------------------- -- RDC Store and Forward Supplimental Controls --------------------- -- These are time aligned and qualified with the RDC Stream Input -- -- data2sf_cmd_cmplt : In std_logic; -- data2sf_dre_flush : In std_logic; -- -------------------------------------------------------------------- -- DRE Control Interface from the Command Calculator ----------------------------- -- dre2mstr_cmd_ready : Out std_logic ; -- -- Indication from the DRE that the command is being -- -- accepted from the Command Calculator -- -- mstr2dre_cmd_valid : In std_logic; -- -- The next command valid indication to the DRE -- -- from the Command Calculator -- -- mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the DRE -- -- mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the DRE -- -- -- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); -- -- -- The bytes to transfer value for the input command -- -- mstr2dre_drr : In std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : In std_logic; -- -- The endiing tranfer of a sequence of transfers -- -- -- mstr2dre_cmd_cmplt : In std_logic; -- -- -- The last tranfer command of a sequence of transfers -- -- -- spawned from a single parent command -- -- mstr2dre_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);-- -- Outputs the starting offset of a transfer. This is used with Store -- -- and Forward Packer/Unpacker logic -- ----------------------------------------------------------------------------------- -- MM2S DRE Control ------------------------------------------------------------- -- sf2dre_new_align : Out std_logic; -- -- Active high signal indicating new DRE aligment required -- -- sf2dre_use_autodest : Out std_logic; -- -- Active high signal indicating to the DRE to use an auto- -- -- calculated desination alignment based on the last transfer -- -- sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- Bit field indicating the byte lane of the first valid data byte -- -- being sent to the DRE -- -- sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- Bit field indicating the desired byte lane of the first valid data byte -- -- to be output by the DRE -- -- sf2dre_flush : Out std_logic; -- -- Active high signal indicating to the DRE to flush the current -- -- contents to the output register in preparation of a new alignment -- -- that will be comming on the next transfer input -- --------------------------------------------------------------------------------- -- Stream Out ----------------------------------------------------------------------- -- sout2sf_tready : In std_logic; -- -- Write READY input from the Stream Master -- -- sf2sout_tvalid : Out std_logic; -- -- Write VALID output to the Stream Master -- -- sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- Write DATA output to the Stream Master -- -- sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- Write DATA output to the Stream Master -- -- sf2sout_tlast : Out std_logic -- -- Write LAST output to the Stream Master -- -------------------------------------------------------------------------------------- ); end entity axi_datamover_rd_sf; architecture implementation of axi_datamover_rd_sf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Functions --------------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_fifo_cnt_width -- -- Function Description: -- simple function to set the width of the data fifo read -- and write count outputs. ------------------------------------------------------------------- function funct_get_fifo_cnt_width (fifo_depth : integer) return integer is Variable temp_width : integer := 8; begin if (fifo_depth = 1) then temp_width := 1; elsif (fifo_depth = 2) then temp_width := 2; elsif (fifo_depth <= 4) then temp_width := 3; elsif (fifo_depth <= 8) then temp_width := 4; elsif (fifo_depth <= 16) then temp_width := 5; elsif (fifo_depth <= 32) then temp_width := 6; elsif (fifo_depth <= 64) then temp_width := 7; elsif (fifo_depth <= 128) then temp_width := 8; elsif (fifo_depth <= 256) then temp_width := 9; elsif (fifo_depth <= 512) then temp_width := 10; elsif (fifo_depth <= 1024) then temp_width := 11; elsif (fifo_depth <= 2048) then temp_width := 12; elsif (fifo_depth <= 4096) then temp_width := 13; else -- assume 8192 depth temp_width := 14; end if; Return (temp_width); end function funct_get_fifo_cnt_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_wrcnt_lsrip -- -- Function Description: -- Calculates the ls index of the upper slice of the data fifo -- write count needed to repesent one max burst worth of data -- present in the fifo. -- ------------------------------------------------------------------- function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is Variable temp_ls_index : Integer := 0; begin if (max_burst_dbeats <= 2) then temp_ls_index := 1; elsif (max_burst_dbeats <= 4) then temp_ls_index := 2; elsif (max_burst_dbeats <= 8) then temp_ls_index := 3; elsif (max_burst_dbeats <= 16) then temp_ls_index := 4; elsif (max_burst_dbeats <= 32) then temp_ls_index := 5; elsif (max_burst_dbeats <= 64) then temp_ls_index := 6; elsif (max_burst_dbeats <= 128) then temp_ls_index := 7; else temp_ls_index := 8; end if; Return (temp_ls_index); end function funct_get_wrcnt_lsrip; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stall_thresh -- -- Function Description: -- Calculates the Stall threshold for the input side of the Data -- FIFO. If DRE is being used by the DataMover, then the threshold -- must be reduced to account for the potential of an extra write -- databeat per request (DRE alignment dependent). -- ------------------------------------------------------------------- function funct_get_stall_thresh (dre_is_used : integer; max_xfer_length : integer; data_fifo_depth : integer; pipeline_delay_clks : integer; fifo_settling_clks : integer) return integer is Constant DRE_PIPE_DELAY : integer := 2; -- clks Variable var_num_max_xfers_allowed : Integer := 0; Variable var_dre_dbeat_overhead : Integer := 0; Variable var_delay_fudge_factor : Integer := 0; Variable var_thresh_headroom : Integer := 0; Variable var_stall_thresh : Integer := 0; begin var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length; var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used; var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) + pipeline_delay_clks + fifo_settling_clks; var_thresh_headroom := max_xfer_length + var_dre_dbeat_overhead + var_delay_fudge_factor; -- Scale the result to be in max transfer length increments var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length; Return (var_stall_thresh); end function funct_get_stall_thresh; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_size_drecntl_fifo -- -- Function Description: -- Assures that the DRE control fifo depth is at least 4 deep else it -- is equal to the number of max burst transfers that can fit in the -- Store and Forward Data FIFO. -- ------------------------------------------------------------------- function funct_size_drecntl_fifo (sf_fifo_depth : integer; max_burst_length : integer) return integer is Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length; Variable temp_fifo_depth : Integer := 4; begin If (NEEDED_FIFO_DEPTH < 4) Then temp_fifo_depth := 4; Else temp_fifo_depth := NEEDED_FIFO_DEPTH; End if; Return (temp_fifo_depth); end function funct_size_drecntl_fifo; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_cntr_width -- -- Function Description: -- Detirmine the width needed for the address offset counter used -- for the data fifo mux selects. -- ------------------------------------------------------------------- function funct_get_cntr_width (num_count_states : integer) return integer is Variable lvar_temp_width : Integer := 1; begin if (num_count_states <= 2) then lvar_temp_width := 1; elsif (num_count_states <= 4) then lvar_temp_width := 2; elsif (num_count_states <= 8) then lvar_temp_width := 3; elsif (num_count_states <= 16) then lvar_temp_width := 4; elsif (num_count_states <= 32) then lvar_temp_width := 5; elsif (num_count_states <= 64) then lvar_temp_width := 6; Else -- 128 cnt states lvar_temp_width := 7; end if; Return (lvar_temp_width); end function funct_get_cntr_width; -- Constants --------------------------------------------------------------------------- Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant BLK_MEM_FIFO : integer := 1; Constant SRL_FIFO : integer := 0; Constant NOT_NEEDED : integer := 0; Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits Constant TLAST_WIDTH : integer := 1; -- bits Constant CMPLT_WIDTH : integer := 1; -- bits Constant DRE_FLUSH_WIDTH : integer := 1; -- bits Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH; Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH); Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN); Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH + MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP + TLAST_WIDTH + CMPLT_WIDTH + DRE_FLUSH_WIDTH; Constant DATA_OUT_LSB_INDEX : integer := 0; Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1; Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1; Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP; Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP; Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1; Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1; Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN; Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1; Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, TOKEN_CNTR_WIDTH); Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, TOKEN_CNTR_WIDTH); Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH); Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2; Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on -- the output side of the Store and Forward Constant RD_ADDR_POST_STALL_THRESH : integer := funct_get_stall_thresh(DRE_COMPENSATION , C_MAX_BURST_LEN , C_SF_FIFO_DEPTH , RD_PATH_PIPE_DEPTH , WRCNT_SETTLING_TIME); Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH , THRESH_COMPARE_WIDTH); Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH); Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH); Constant USE_SYNC_FIFO : integer := 0; Constant SRL_FIFO_PRIM : integer := 2; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH; Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH; Constant DRR_WIDTH : integer := 1; Constant EOF_WIDTH : integer := 1; Constant CALC_ERR_WIDTH : integer := 1; Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH; -- Signals --------------------------------------------------------------------------- signal sig_good_sin_strm_dbeat : std_logic := '0'; signal sig_strm_sin_ready : std_logic := '0'; signal sig_good_sout_strm_dbeat : std_logic := '0'; signal sig_sout2sf_tready : std_logic := '0'; signal sig_sf2sout_tvalid : std_logic := '0'; signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_sf2sout_tlast : std_logic := '0'; signal sig_sf2dre_flush : std_logic := '0'; signal sig_push_data_fifo : std_logic := '0'; signal sig_pop_data_fifo : std_logic := '0'; signal sig_data_fifo_full : std_logic := '0'; signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_dvalid : std_logic := '0'; signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto DF_WRCNT_RIP_LS_INDEX) := (others => '0'); signal sig_ok_to_post_rd_addr : std_logic := '0'; signal sig_rd_addr_posted : std_logic := '0'; signal sig_rd_xfer_cmplt : std_logic := '0'; signal sig_taking_last_token : std_logic := '0'; signal sig_stall_rd_addr_posts : std_logic := '0'; signal sig_incr_token_cntr : std_logic := '0'; signal sig_decr_token_cntr : std_logic := '0'; signal sig_token_eq_max : std_logic := '0'; signal sig_token_eq_zero : std_logic := '0'; signal sig_token_eq_one : std_logic := '0'; signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0'); signal sig_cntl_fifo_has_data : std_logic := '0'; signal sig_get_cntl_fifo_data : std_logic := '0'; signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_drr_reg : std_logic := '0'; signal sig_curr_eof_reg : std_logic := '0'; signal sig_curr_calc_error_reg : std_logic := '0'; signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_ld_dre_cntl_reg : std_logic := '0'; signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0'); signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0'); signal sig_dfifo_tlast_out : std_logic := '0'; signal sig_dfifo_cmd_cmplt_out : std_logic := '0'; signal sig_dfifo_dre_flush_out : std_logic := '0'; begin --(architecture implementation) -- Read Side (MM2S) Control Flags port connections ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ; sig_rd_addr_posted <= rd_addr_posted ; sig_rd_xfer_cmplt <= rd_xfer_cmplt ; -- Output Stream Port connections sig_sout2sf_tready <= sout2sf_tready ; sf2sout_tvalid <= sig_sf2sout_tvalid ; sf2sout_tdata <= sig_sf2sout_tdata ; --sf2sout_tkeep <= sig_sf2sout_tkeep ; sf2sout_tlast <= sig_sf2sout_tlast and sig_sf2sout_tvalid ; GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate begin sf2sout_tkeep <= sig_sf2sout_tkeep ; end generate GEN_MM2S_TKEEP_ENABLE4; GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate begin sf2sout_tkeep <= (others => '1'); end generate GEN_MM2S_TKEEP_DISABLE4; -- Input Stream port connections sf2sin_tready <= sig_strm_sin_ready; sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full. -- This should never happen if read address -- posting control is working properly. -- Stream transfer qualifiers sig_good_sin_strm_dbeat <= sin2sf_tvalid and sig_strm_sin_ready; sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and sig_sout2sf_tready; ---------------------------------------------------------------- -- Unpacking Logic ------------------------------------------ ---------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_UNPACKING -- -- If Generate Description: -- Omits any unpacking logic in the Store and Forward module. -- The Stream and MMap data widths are the same. The Data FIFO -- output can be connected directly to the stream outputs. -- ------------------------------------------------------------ OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate signal lsig_cmd_loaded : std_logic := '0'; signal lsig_ld_cmd : std_logic := '0'; signal lsig_cmd_cmplt_dbeat : std_logic := '0'; signal lsig_cmd_cmplt : std_logic := '0'; begin -- Data FIFO Output to the stream attachments sig_sf2sout_tvalid <= sig_data_fifo_dvalid and lsig_cmd_loaded ; sig_sf2sout_tdata <= sig_dfifo_data_out ; sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ; sig_sf2sout_tlast <= sig_dfifo_tlast_out ; sig_sf2dre_flush <= sig_dfifo_dre_flush_out ; -- Control for reading the Data FIFO sig_pop_data_fifo <= lsig_cmd_loaded and sig_sout2sf_tready and sig_data_fifo_dvalid; -- Control for reading the Command/Offset FIFO sig_get_cntl_fifo_data <= lsig_ld_cmd ; -- Control for loading the DRE Control Reg sig_ld_dre_cntl_reg <= lsig_ld_cmd ; lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and lsig_cmd_loaded and sig_data_fifo_dvalid and sig_sout2sf_tready ; -- Generate the control that loads the DRE lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case not(lsig_cmd_loaded)) or (sig_cntl_fifo_has_data and -- back to back commands lsig_cmd_cmplt_dbeat); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_LOADED -- -- Process Description: -- Implements the flop indicating a command from the cmd fifo -- has been loaded into the DRE Output Register. -- ------------------------------------------------------------- IMP_CMD_LOADED : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_cmd_loaded <= '0'; Elsif (lsig_ld_cmd = '1' ) Then lsig_cmd_loaded <= '1'; elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and lsig_cmd_cmplt_dbeat = '1') then lsig_cmd_loaded <= '0'; else null; -- Hold Current State end if; end if; end process IMP_CMD_LOADED; end generate OMIT_UNPACKING; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_UNPACKING -- -- If Generate Description: -- Includes unpacking logic in the Store and Forward module. -- The MMap Data bus is wider than the Stream width. -- ------------------------------------------------------------ INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH; Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH; Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8; Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH; Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO); Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, OFFSET_CNTR_WIDTH); Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH); -- Types ----------------------------------------------------------------------------- type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(DATA_SLICE_WIDTH-1 downto 0); type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0); type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0); -- local signals signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0'); signal lsig_ld_offset : std_logic := '0'; signal lsig_incr_offset : std_logic := '0'; signal lsig_offset_cntr_eq_max : std_logic := '0'; signal lsig_fifo_data_out_wide : lsig_data_slice_type; signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type; signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1; signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ; signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0); signal lsig_tlast_out : std_logic := '0'; signal lsig_dre_flush_out : std_logic := '0'; signal lsig_this_fifo_wrd_done : std_logic := '0'; signal lsig_cmd_loaded : std_logic := '0'; signal lsig_cmd_cmplt_dbeat : std_logic := '0'; signal lsig_cmd_cmplt : std_logic := '0'; signal lsig_next_slice_tkeep_0 : std_logic := '0'; begin sig_sf2sout_tvalid <= sig_data_fifo_dvalid and lsig_cmd_loaded ; sig_sf2sout_tdata <= lsig_data_mux_out ; sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0); sig_sf2sout_tlast <= lsig_tlast_out ; sig_sf2dre_flush <= lsig_dre_flush_out ; -- Control for reading the Data FIFO sig_pop_data_fifo <= lsig_this_fifo_wrd_done and lsig_cmd_loaded and sig_sout2sf_tready and sig_data_fifo_dvalid; -- Control for reading the Command/Offset FIFO sig_get_cntl_fifo_data <= lsig_ld_offset; -- Control for loading the DRE Control Reg sig_ld_dre_cntl_reg <= lsig_ld_offset ; lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0); -- Detirmine if a Command Complete condition exists lsig_cmd_cmplt <= '1' when (sig_dfifo_cmd_cmplt_out = '1' and lsig_next_slice_tkeep_0 = '0') Else '0'; -- Detirmine if a TLAST condition exists -- From the RDC via the Data FIFO lsig_tlast_out <= '1' when (sig_dfifo_tlast_out = '1' and lsig_next_slice_tkeep_0 = '0') Else '0'; -- Detimine if a DRE Flush condition exists -- From the RDC via the Data FIFO lsig_dre_flush_out <= '1' when (sig_dfifo_dre_flush_out = '1' and lsig_next_slice_tkeep_0 = '0') Else '0'; lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and lsig_cmd_loaded and sig_data_fifo_dvalid and sig_sout2sf_tready ; -- Check to see if the FIFO output word is finished. This occurs -- when the offset counter is at max value or the tlast from the -- fifo is set and the LS TKEED of the next MS Slice is zero. lsig_this_fifo_wrd_done <= '1' When (lsig_offset_cntr_eq_max = '1' or (lsig_cmd_cmplt_dbeat = '1' and lsig_next_slice_tkeep_0 = '0')) Else '0'; -- Generate the control that loads the starting address -- offset for the next input packet lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case not(lsig_cmd_loaded)) or (sig_cntl_fifo_has_data and -- back to back commands lsig_cmd_cmplt_dbeat); -- Generate the control for incrementing the offset counter lsig_incr_offset <= sig_good_sout_strm_dbeat; -- Check to see if the offset counter has reached its max -- value lsig_offset_cntr_eq_max <= '1' when (lsig_0ffset_cntr = OFFSET_CNT_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_LOADED -- -- Process Description: -- Implements the flop indicating a command from the cmd fifo -- has been loaded into the unpacker control logic. -- ------------------------------------------------------------- IMP_CMD_LOADED : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_cmd_loaded <= '0'; Elsif (lsig_ld_offset = '1' ) Then lsig_cmd_loaded <= '1'; elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued lsig_cmd_cmplt_dbeat = '1') then lsig_cmd_loaded <= '0'; else null; -- Hold Current State end if; end if; end process IMP_CMD_LOADED; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_OFFSET_CNTR -- -- Process Description: -- Implements the address offset counter that is used to -- generate the data and tkeep mux selects. -- Note that the counter has to be loaded with the starting -- offset plus one to sync up with the data input. ------------------------------------------------------------- IMP_OFFSET_CNTR : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then lsig_0ffset_cntr <= (others => '0'); Elsif (lsig_ld_offset = '1') Then lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg); elsif (lsig_incr_offset = '1') then lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE; else null; -- Hold Current State end if; end if; end process IMP_OFFSET_CNTR; ------------------------------------------------------------ -- For Generate -- -- Label: DO_DATA_CONVERTER -- -- For Generate Description: -- This ForGen converts the FIFO output data and tkeep from a single -- std logic vector type to a vector of slices. -- ------------------------------------------------------------ DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate begin lsig_fifo_data_out_wide(slice_index-1) <= sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto (slice_index-1)*DATA_SLICE_WIDTH); lsig_fifo_tkeep_out_wide(slice_index-1) <= sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto (slice_index-1)*TKEEP_SLICE_WIDTH); end generate DO_DATA_CONVERTER; -- Assign the extra tkeep slice to all zeros to allow for detection -- of the data word done when the ls tkeep bit of the next tkeep -- slice is zero and the offset count is pointing to the last slice -- position. lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0'); -- Mux the appropriate data and tkeep slice to the stream output lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr); lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ; lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel); end generate INCLUDE_UNPACKING; ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_DRE_CNTL -- -- If Generate Description: -- This IfGen is used to omit the DRE control logic and -- minimize the Control FIFO when MM2S DRE is not included -- in the MM2S. -- ------------------------------------------------------------ OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate -- Constant Declarations ------------------------------------------------------------------ Constant USE_SYNC_FIFO : integer := 0; Constant SRL_FIFO_PRIM : integer := 2; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant DRR_WIDTH : integer := 1; Constant EOF_WIDTH : integer := 1; Constant CALC_ERR_WIDTH : integer := 1; Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH; Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH, C_MAX_BURST_LEN); Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field DRR_WIDTH + -- DRE Re-alignment Request Flag Field EOF_WIDTH + -- EOF flag field CALC_ERR_WIDTH + -- Calc error flag SF_OFFSET_WIDTH; -- Store and Forward Offset Constant TAG_STRT_INDEX : integer := 0; Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH; Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH; Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH; Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH; -- Signal Declarations -------------------------------------------------------------------- signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_offset_fifo_wr_valid : std_logic := '0'; signal sig_offset_fifo_wr_ready : std_logic := '0'; signal sig_offset_fifo_rd_valid : std_logic := '0'; signal sig_offset_fifo_rd_ready : std_logic := '0'; begin -- PCC DRE Command interface handshake dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ; sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ; -- No DRE so no controls sf2dre_new_align <= '0'; sf2dre_use_autodest <= '0'; sf2dre_src_align <= (others => '0'); sf2dre_dest_align <= (others => '0'); sf2dre_flush <= '0'; -- No DRE so no alignment values sig_curr_src_align_reg <= (others => '0'); sig_curr_dest_align_reg <= (others => '0'); -- Format the input data word for the Offset FIFO Queue sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field mstr2dre_calc_error & mstr2dre_eof & mstr2dre_drr & mstr2dre_tag; -- LS Field sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ; sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ; -- Rip the output fifo data word sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX); sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX); sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX); sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX); sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX); ------------------------------------------------------------ -- Instance: I_DRE_CNTL_FIFO -- -- Description: -- Instance for the Offset Control FIFO. This is still needed -- by the unpacker logic to get the starting offset at the -- begining of an input packet coming out of the Store and -- Forward data FIFO. -- ------------------------------------------------------------ I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => SF_OFFSET_FIFO_WIDTH , C_DEPTH => SF_OFFSET_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => SRL_FIFO_PRIM , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => reset , fifo_wr_clk => aclk , -- Write Side fifo_wr_tvalid => sig_offset_fifo_wr_valid , fifo_wr_tready => sig_offset_fifo_wr_ready , fifo_wr_tdata => sig_offset_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => aclk , fifo_async_rd_clk => reset , -- Read Side fifo_rd_tvalid => sig_offset_fifo_rd_valid , fifo_rd_tready => sig_offset_fifo_rd_ready , fifo_rd_tdata => sig_offset_fifo_data_out , fifo_rd_empty => open ); end generate OMIT_DRE_CNTL; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_DRE_CNTL -- -- If Generate Description: -- This IfGen is used to include the DRE control logic and -- Control FIFO when MM2S DRE is included in the MM2S. -- -- ------------------------------------------------------------ INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate -- Constant Declarations Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH, C_MAX_BURST_LEN); Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field SRC_ALIGN_WIDTH + -- Source align field width DEST_ALIGN_WIDTH + -- Dest align field width DRR_WIDTH + -- DRE Re-alignment Request Flag Field EOF_WIDTH + -- EOF flag field CALC_ERR_WIDTH + -- Calc error flag SF_OFFSET_WIDTH; -- Store and Forward Offset Constant TAG_STRT_INDEX : integer := 0; Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH; Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH; Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH; Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH; Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH; Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH; signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_fifo_rd_cmd_ready : std_logic := '0'; signal sig_dre_align_ready : std_logic := '0'; signal sig_dre_align_valid_reg : std_logic := '0'; signal sig_dre_use_autodest_reg : std_logic := '0'; signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush_reg : std_logic := '0'; begin -- Assign the DRE Control Outputs sf2dre_new_align <= sig_dre_align_valid_reg; sf2dre_use_autodest <= sig_dre_use_autodest_reg; sf2dre_src_align <= sig_dre_src_align_reg; sf2dre_dest_align <= sig_dre_dest_align_reg; sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO -- PCC DRE Command interface handshake dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ; -- Format the input data word for the DRE Control FIFO Queue sig_cmd_fifo_data_in <= mstr2dre_strt_offset & mstr2dre_calc_error & mstr2dre_eof & mstr2dre_drr & mstr2dre_dre_dest_align & mstr2dre_dre_src_align & mstr2dre_tag; -- Formulate the DRE Control FIFO Read signaling sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ; sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ; -- Rip the output fifo data word sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX); sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX); sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX); sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX); sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX); sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX); sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX); ------------------------------------------------------------ -- Instance: I_DRE_CNTL_FIFO -- -- Description: -- Instance for the DRE Control FIFO -- ------------------------------------------------------------ I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => DRECNTL_FIFO_WIDTH , C_DEPTH => DRECNTL_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => SRL_FIFO_PRIM , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => reset , fifo_wr_clk => aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_cmd_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => aclk , fifo_async_rd_clk => reset , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_fifo_rd_cmd_ready , fifo_rd_tdata => sig_cmd_fifo_data_out , fifo_rd_empty => open ); ------------------------------------------------------------------------- -- DRE Control Register ------------------------------------------------------------------------- -- The DRE will auto-flush on a received TLAST so a commanded Flush -- is not needed. sig_dre_flush_reg <= '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CNTL_REG -- -- Process Description: -- Implements the DRE alignment Output Register. -- ------------------------------------------------------------- IMP_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then sig_dre_use_autodest_reg <= '0' ; sig_dre_src_align_reg <= (others => '0') ; sig_dre_dest_align_reg <= (others => '0') ; Elsif (sig_ld_dre_cntl_reg = '1' ) Then sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ; sig_dre_src_align_reg <= sig_curr_src_align_reg ; sig_dre_dest_align_reg <= sig_curr_dest_align_reg ; Elsif (sig_good_sout_strm_dbeat = '1') Then sig_dre_use_autodest_reg <= '0' ; sig_dre_src_align_reg <= (others => '0') ; sig_dre_dest_align_reg <= (others => '0') ; else null; -- Hold Current State end if; end if; end process IMP_CNTL_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DRE_CNTL_VALID_REG -- -- Process Description: -- Implements the DRE Alignment valid Register. -- ------------------------------------------------------------- IMP_DRE_CNTL_VALID_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1') then sig_dre_align_valid_reg <= '0' ; Elsif (sig_ld_dre_cntl_reg = '1' ) Then sig_dre_align_valid_reg <= '1' ; Elsif (sig_good_sout_strm_dbeat = '1') Then sig_dre_align_valid_reg <= '0' ; else null; -- Hold Current State end if; end if; end process IMP_DRE_CNTL_VALID_REG; end generate INCLUDE_DRE_CNTL; ---------------------------------------------------------------- -- Token Counter Logic -- Predicting fifo space availability at some point in the -- future is based on managing a virtual pool of transfer tokens. -- A token represents 1 max length burst worth of space in the -- Data FIFO. ---------------------------------------------------------------- -- calculate how many tokens are commited to pending transfers sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr; -- Decrement the token counter when a token is -- borrowed sig_decr_token_cntr <= '1' when (sig_rd_addr_posted = '1' and sig_token_eq_zero = '0') else '0'; -- Increment the token counter when a -- token is returned. sig_incr_token_cntr <= '1' when (sig_rd_xfer_cmplt = '1' and sig_token_eq_max = '0') else '0'; -- Detect when the xfer token count is at max value sig_token_eq_max <= '1' when (sig_token_cntr = TOKEN_CNT_MAX) Else '0'; -- Detect when the xfer token count is at one sig_token_eq_one <= '1' when (sig_token_cntr = TOKEN_CNT_ONE) Else '0'; -- Detect when the xfer token count is at zero sig_token_eq_zero <= '1' when (sig_token_cntr = TOKEN_CNT_ZERO) Else '0'; -- Look ahead to see if the xfer token pool is going empty sig_taking_last_token <= '1' When (sig_token_eq_one = '1' and sig_rd_addr_posted = '1') Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TOKEN_CNTR -- -- Process Description: -- Implements the Token counter -- ------------------------------------------------------------- IMP_TOKEN_CNTR : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1' ) then sig_token_cntr <= TOKEN_CNT_MAX; elsif (sig_incr_token_cntr = '1' and sig_decr_token_cntr = '0') then sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE; elsif (sig_incr_token_cntr = '0' and sig_decr_token_cntr = '1') then sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE; else null; -- hold current value end if; end if; end process IMP_TOKEN_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TOKEN_AVAIL_FLAG -- -- Process Description: -- Implements the flag indicating that the AXI Read Master -- can post a read address request on the AXI4 bus. -- -- Read address posting can occur if: -- -- - The write side LEN fifo is not empty. -- - The commited plus actual Data FIFO space is less than -- the stall threshold (a max length read burst can fit -- in the data FIFO without overflow). -- - The max allowed commited read count has not been reached. -- -- The flag is cleared after each address has been posted to -- ensure a second unauthorized post does not occur. ------------------------------------------------------------- IMP_TOKEN_AVAIL_FLAG : process (aclk) begin if (aclk'event and aclk = '1') then if (reset = '1' or sig_rd_addr_posted = '1') then sig_ok_to_post_rd_addr <= '0'; else sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full not(sig_token_eq_zero) and -- max allowed pending reads has not been reached not(sig_taking_last_token); -- the max allowed pending reads is about to be reached end if; end if; end process IMP_TOKEN_AVAIL_FLAG; ---------------------------------------------------------------- -- Data FIFO Logic ------------------------------------------ ---------------------------------------------------------------- GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate begin -- FIFO Output ripping to components sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto DATA_OUT_LSB_INDEX); sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto TKEEP_OUT_LSB_INDEX); sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ; sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ; sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ; end generate GEN_MM2S_TKEEP_ENABLE3; GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate begin -- FIFO Output ripping to components sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto DATA_OUT_LSB_INDEX); sig_dfifo_tkeep_out <= (others => '1'); sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ; sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ; sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ; end generate GEN_MM2S_TKEEP_DISABLE3; -- Stall Threshold calculations sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt); sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto DF_WRCNT_RIP_LS_INDEX); sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) + RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH); -- Compare the commited read space plus the actual used space against the -- stall threshold. Assert the read address posting stall flag if the -- threshold is met or exceeded. sig_stall_rd_addr_posts <= '1' when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US) Else '0'; -- FIFO Rd/WR Controls sig_push_data_fifo <= sig_good_sin_strm_dbeat; -- sig_pop_data_fifo <= sig_sout2sf_tready and -- sig_data_fifo_dvalid; GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate begin -- Concatonate the Stream inputs into the single FIFO data in value sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field data2sf_cmd_cmplt & sin2sf_tlast & sin2sf_tkeep & sin2sf_tdata; -- ls field end generate GEN_MM2S_TKEEP_ENABLE2; GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate begin -- Concatonate the Stream inputs into the single FIFO data in value sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field data2sf_cmd_cmplt & sin2sf_tlast & --sin2sf_tkeep & sin2sf_tdata; -- ls field end generate GEN_MM2S_TKEEP_DISABLE2; ------------------------------------------------------------ -- Instance: I_DATA_FIFO -- -- Description: -- Implements the Store and Forward data FIFO (synchronous) -- ------------------------------------------------------------ I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord generic map ( C_DWIDTH => DATA_FIFO_WIDTH , C_DEPTH => DATA_FIFO_DEPTH , C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH , C_NEED_ALMOST_EMPTY => NOT_NEEDED , C_NEED_ALMOST_FULL => NOT_NEEDED , C_USE_BLKMEM => BLK_MEM_FIFO , C_FAMILY => C_FAMILY ) port map ( -- Inputs SFIFO_Sinit => reset , SFIFO_Clk => aclk , SFIFO_Wr_en => sig_push_data_fifo , SFIFO_Din => sig_data_fifo_data_in , SFIFO_Rd_en => sig_pop_data_fifo , SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW , -- Outputs SFIFO_DValid => sig_data_fifo_dvalid , SFIFO_Dout => sig_data_fifo_data_out , SFIFO_Full => sig_data_fifo_full , SFIFO_Empty => open , SFIFO_Almost_full => open , SFIFO_Almost_empty => open , SFIFO_Rd_count => open , SFIFO_Rd_count_minus1 => open , SFIFO_Wr_count => sig_data_fifo_wr_cnt , SFIFO_Rd_ack => open ); end implementation;
bsd-2-clause
52483986cad01903ded132fb522aa753
0.426291
4.835136
false
false
false
false
rjarzmik/mips_processor
Caches/SinglePort_Cache.vhd
1
5,146
------------------------------------------------------------------------------- -- Title : Single port cache -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : SinglePort_Cache.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-11-19 -- Last update: 2016-11-27 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Cache with one access port and one port to the memory/L+1 cache ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-19 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- entity SinglePort_Cache is generic ( ADDR_WIDTH : integer := 32; DATA_WIDTH : integer := 32 ); port ( clk : in std_logic; rst : in std_logic; i_porta_req : in std_logic; i_porta_we : in std_logic; i_porta_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0); i_porta_write_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); o_porta_read_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); o_porta_valid : out std_logic; o_memory_req : out std_logic; o_memory_we : out std_logic; o_memory_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0); o_memory_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0); i_memory_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); i_memory_valid : in std_logic ); end entity SinglePort_Cache; ------------------------------------------------------------------------------- architecture passthrough of SinglePort_Cache is ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- -- access handling signal cache_initialized : boolean := false; signal cache_loaded : boolean; signal cache_hit : boolean; signal cache_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) := (others => '1'); signal cache_data : std_logic_vector(DATA_WIDTH - 1 downto 0); -- cache_valid means: for previously latched address, cache_data is valid. -- cache_valid also means: for last time i_porta_req was raised, for the -- i_porta_addr that was input, the data on cache_data is valid. signal cache_valid : boolean; -- dearm_memory_req : ensure o_memory_req is held only 1 cycle for each request signal dearm_memory_req : boolean := false; signal memory_ongoing : boolean := false; begin -- architecture str ----------------------------------------------------------------------------- -- Component instantiations ----------------------------------------------------------------------------- process(rst, clk) is begin if rst = '0' then if rising_edge(clk) then if i_porta_req = '1' then if not cache_initialized or cache_addr /= i_porta_addr then cache_addr <= i_porta_addr; cache_valid <= false; cache_data <= (others => 'X'); o_memory_addr <= i_porta_addr; o_memory_req <= '1'; dearm_memory_req <= true; memory_ongoing <= true; o_memory_we <= i_porta_we; o_memory_write_data <= i_porta_write_data; end if; -- If cache_valid and cache_valid = i_porta_addr, output is still -- valid and nothing is to be done. elsif dearm_memory_req then o_memory_req <= '0'; dearm_memory_req <= false; if i_memory_valid = '0' then cache_valid <= false; -- dearm cache_valid one cycle after -- cache_addr changed end if; end if; if i_memory_valid = '1' then memory_ongoing <= false; cache_data <= i_memory_read_data; cache_initialized <= true; if not (i_porta_req = '1' and (cache_addr /= i_porta_addr)) then cache_valid <= true; end if; -- In parallel, o_porta_valid will become '1' end if; end if; else o_memory_req <= '0'; cache_valid <= false; end if; end process; o_porta_valid <= '1' when cache_valid else '0'; o_porta_read_data <= cache_data when cache_valid else (others => 'X'); end architecture passthrough; ---------------------------------------------------------------------------------
gpl-3.0
732d1b3ca3c55b9a48d207442ff3465e
0.451807
4.413379
false
false
false
false
Yarr/Yarr-fw
ip-cores/spartan6/tx_fifo.vhd
2
10,252
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2014 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file tx_fifo.vhd when simulating -- the core, tx_fifo. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY tx_fifo IS PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; prog_full : OUT STD_LOGIC ); END tx_fifo; ARCHITECTURE tx_fifo_a OF tx_fifo IS -- synthesis translate_off COMPONENT wrapped_tx_fifo PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; prog_full : OUT STD_LOGIC ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_tx_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral) GENERIC MAP ( c_add_ngc_constraint => 0, c_application_type_axis => 0, c_application_type_rach => 0, c_application_type_rdch => 0, c_application_type_wach => 0, c_application_type_wdch => 0, c_application_type_wrch => 0, c_axi_addr_width => 32, c_axi_aruser_width => 1, c_axi_awuser_width => 1, c_axi_buser_width => 1, c_axi_data_width => 64, c_axi_id_width => 4, c_axi_ruser_width => 1, c_axi_type => 0, c_axi_wuser_width => 1, c_axis_tdata_width => 64, c_axis_tdest_width => 4, c_axis_tid_width => 8, c_axis_tkeep_width => 4, c_axis_tstrb_width => 4, c_axis_tuser_width => 4, c_axis_type => 0, c_common_clock => 0, c_count_type => 0, c_data_count_width => 10, c_default_value => "BlankString", c_din_width => 32, c_din_width_axis => 1, c_din_width_rach => 32, c_din_width_rdch => 64, c_din_width_wach => 32, c_din_width_wdch => 64, c_din_width_wrch => 2, c_dout_rst_val => "0", c_dout_width => 32, c_enable_rlocs => 0, c_enable_rst_sync => 1, c_error_injection_type => 0, c_error_injection_type_axis => 0, c_error_injection_type_rach => 0, c_error_injection_type_rdch => 0, c_error_injection_type_wach => 0, c_error_injection_type_wdch => 0, c_error_injection_type_wrch => 0, c_family => "spartan6", c_full_flags_rst_val => 1, c_has_almost_empty => 0, c_has_almost_full => 0, c_has_axi_aruser => 0, c_has_axi_awuser => 0, c_has_axi_buser => 0, c_has_axi_rd_channel => 0, c_has_axi_ruser => 0, c_has_axi_wr_channel => 0, c_has_axi_wuser => 0, c_has_axis_tdata => 0, c_has_axis_tdest => 0, c_has_axis_tid => 0, c_has_axis_tkeep => 0, c_has_axis_tlast => 0, c_has_axis_tready => 1, c_has_axis_tstrb => 0, c_has_axis_tuser => 0, c_has_backup => 0, c_has_data_count => 0, c_has_data_counts_axis => 0, c_has_data_counts_rach => 0, c_has_data_counts_rdch => 0, c_has_data_counts_wach => 0, c_has_data_counts_wdch => 0, c_has_data_counts_wrch => 0, c_has_int_clk => 0, c_has_master_ce => 0, c_has_meminit_file => 0, c_has_overflow => 0, c_has_prog_flags_axis => 0, c_has_prog_flags_rach => 0, c_has_prog_flags_rdch => 0, c_has_prog_flags_wach => 0, c_has_prog_flags_wdch => 0, c_has_prog_flags_wrch => 0, c_has_rd_data_count => 0, c_has_rd_rst => 0, c_has_rst => 1, c_has_slave_ce => 0, c_has_srst => 0, c_has_underflow => 0, c_has_valid => 0, c_has_wr_ack => 0, c_has_wr_data_count => 0, c_has_wr_rst => 0, c_implementation_type => 2, c_implementation_type_axis => 1, c_implementation_type_rach => 1, c_implementation_type_rdch => 1, c_implementation_type_wach => 1, c_implementation_type_wdch => 1, c_implementation_type_wrch => 1, c_init_wr_pntr_val => 0, c_interface_type => 0, c_memory_type => 1, c_mif_file_name => "BlankString", c_msgon_val => 1, c_optimization_mode => 0, c_overflow_low => 0, c_preload_latency => 0, c_preload_regs => 1, c_prim_fifo_type => "1kx36", c_prog_empty_thresh_assert_val => 4, c_prog_empty_thresh_assert_val_axis => 1022, c_prog_empty_thresh_assert_val_rach => 1022, c_prog_empty_thresh_assert_val_rdch => 1022, c_prog_empty_thresh_assert_val_wach => 1022, c_prog_empty_thresh_assert_val_wdch => 1022, c_prog_empty_thresh_assert_val_wrch => 1022, c_prog_empty_thresh_negate_val => 5, c_prog_empty_type => 0, c_prog_empty_type_axis => 0, c_prog_empty_type_rach => 0, c_prog_empty_type_rdch => 0, c_prog_empty_type_wach => 0, c_prog_empty_type_wdch => 0, c_prog_empty_type_wrch => 0, c_prog_full_thresh_assert_val => 1023, c_prog_full_thresh_assert_val_axis => 1023, c_prog_full_thresh_assert_val_rach => 1023, c_prog_full_thresh_assert_val_rdch => 1023, c_prog_full_thresh_assert_val_wach => 1023, c_prog_full_thresh_assert_val_wdch => 1023, c_prog_full_thresh_assert_val_wrch => 1023, c_prog_full_thresh_negate_val => 1022, c_prog_full_type => 1, c_prog_full_type_axis => 0, c_prog_full_type_rach => 0, c_prog_full_type_rdch => 0, c_prog_full_type_wach => 0, c_prog_full_type_wdch => 0, c_prog_full_type_wrch => 0, c_rach_type => 0, c_rd_data_count_width => 10, c_rd_depth => 1024, c_rd_freq => 1, c_rd_pntr_width => 10, c_rdch_type => 0, c_reg_slice_mode_axis => 0, c_reg_slice_mode_rach => 0, c_reg_slice_mode_rdch => 0, c_reg_slice_mode_wach => 0, c_reg_slice_mode_wdch => 0, c_reg_slice_mode_wrch => 0, c_synchronizer_stage => 2, c_underflow_low => 0, c_use_common_overflow => 0, c_use_common_underflow => 0, c_use_default_settings => 0, c_use_dout_rst => 1, c_use_ecc => 0, c_use_ecc_axis => 0, c_use_ecc_rach => 0, c_use_ecc_rdch => 0, c_use_ecc_wach => 0, c_use_ecc_wdch => 0, c_use_ecc_wrch => 0, c_use_embedded_reg => 0, c_use_fifo16_flags => 0, c_use_fwft_data_count => 0, c_valid_low => 0, c_wach_type => 0, c_wdch_type => 0, c_wr_ack_low => 0, c_wr_data_count_width => 10, c_wr_depth => 1024, c_wr_depth_axis => 1024, c_wr_depth_rach => 16, c_wr_depth_rdch => 1024, c_wr_depth_wach => 16, c_wr_depth_wdch => 1024, c_wr_depth_wrch => 16, c_wr_freq => 1, c_wr_pntr_width => 10, c_wr_pntr_width_axis => 10, c_wr_pntr_width_rach => 4, c_wr_pntr_width_rdch => 10, c_wr_pntr_width_wach => 4, c_wr_pntr_width_wdch => 10, c_wr_pntr_width_wrch => 4, c_wr_response_latency => 1, c_wrch_type => 0 ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_tx_fifo PORT MAP ( rst => rst, wr_clk => wr_clk, rd_clk => rd_clk, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty, prog_full => prog_full ); -- synthesis translate_on END tx_fifo_a;
gpl-3.0
d10e5143c8ba49baf012daf5b11b66f8
0.5357
3.327491
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/concurrent/rule_006_test_input.fixed.vhd
1
1,180
architecture RTL of FIFO is begin -- These are passing a <= b; a <= when c = '0' else '1'; with z select a <= b when z = "000", c when z = "001"; a <= b; a <= when c = '0' else '1'; -- Failing variations a <= b; a <= when c = '0' else '1'; with z select a <= b when z = "000", c when z = "001"; a <= b; a <= when c = '0' else '1'; -- Testing generate breaks a <= b; gen : if '1' = '1' generate anExtraLoooooooooooooooooooongName <= c; end generate gen; aSlighltyLongerName <= d; b <= c; a <= b; gen : for i in 0 to 7 generate anExtraLoooooooooooooooooooongName <= c; end generate gen; aSlighltyLongerName <= d; b <= c; a <= b; aSlightlyLooongerName <= c; LABEL0 : case a & b & c generate when "000" => anExtraLoooooooooooooooooooongName <= c; anExtraLoooooooooooongName <= c; when "001" => anExtraLoooooooooooooooongName <= c; anExtraLooooooooooooooooooooooooongName <= c; end generate LABEL0; aSlighltyLongerName <= d; b <= c; end architecture RTL;
gpl-3.0
394b419bc5e005fdceb32e919368d31b
0.532203
3.286908
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/styles/indent_only/c16/BaudGen.vhd
1
1,485
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use STD.TEXTIO.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity BaudGen is Generic(bg_clock_freq : integer; bg_baud_rate : integer); Port( CLK_I : in std_logic; RST_I : in std_logic; CE_16 : out std_logic ); end BaudGen; architecture Behavioral of BaudGen is -- divide bg_clock_freq and bg_baud_rate -- by their common divisor... -- function gcd(M, N: integer) return integer is begin if ((M mod N) = 0) then return N; else return gcd(N, M mod N); end if; end; constant common_div : integer := gcd(bg_clock_freq, 16 * bg_baud_rate); constant clock_freq : integer := bg_clock_freq / common_div; constant baud_freq : integer := 16 * bg_baud_rate / common_div; constant limit : integer := clock_freq - baud_freq; signal COUNTER : integer range 0 to clock_freq - 1; begin process(CLK_I) begin if (rising_edge(CLK_I)) then CE_16 <= '0'; -- make CE_16 stay on for (at most) one cycle if (RST_I = '1') then COUNTER <= 0; elsif (COUNTER >= limit) then CE_16 <= '1'; COUNTER <= COUNTER - limit; else COUNTER <= COUNTER + baud_freq; end if; end if; end process; end Behavioral;
gpl-3.0
0bffa1a8f5e8f205dd2f92b4cecf9ba9
0.626936
3.375
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_v8_0_pkg.vhd
2
123,409
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PZQjRORpZCQwmYmzAPS4sYrbQQK63zY66SlyXjjvBolfgY6jh9tsEJN2zZLV5OCgMkJOIjzZYNj6 YMJPnLlKUA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block G/+OY2uCU775hkNuVSIgFYAPd458wYed3SXK7wIXKsovODndXlY2GtBFyYpvqWd788hfw/uULGTV ZY3/WGvwXBPouDq257b7fN4sXUCSe9pX+P3Nd8Tbd3MRUsAQANIKL2+Z8SMYJ8VDL+oSVZISr/yG PAb1VCgvdrFC34kD+CE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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bsd-2-clause
e6679c94e38c47f3aee9eab555550e7c
0.953877
1.814491
false
false
false
false
NicoLedwith/Dr.AluOpysel
RAT_MCU/Scratch_ram.vhd
1
1,202
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; entity SCR is Port ( DATA : inout STD_LOGIC_VECTOR (9 downto 0); ADDR : in STD_LOGIC_VECTOR (7 downto 0); OE : in STD_LOGIC; WE : in STD_LOGIC; CLK : in STD_LOGIC); end SCR; architecture SCR of SCR is TYPE memory is array (0 to 255) of std_logic_vector(9 downto 0); -----------------------------------------------------------(1) SIGNAL BD_RAM : memory := (others => (others =>'0') ); begin my_bi_dir: process(CLK,OE,WE,DATA,ADDR,BD_RAM) begin --------------------------------------------------------(2) if (OE = '1') then DATA <= BD_RAM(conv_integer(ADDR)); --------------------------------------------------------(3) else -----------------------------------------------------(4) DATA <= (others => 'Z'); -----------------------------------------------------(5) if (WE = '1') then if (rising_edge(CLK)) then BD_RAM(conv_integer(ADDR)) <= DATA; end if; end if; end if; end process my_bi_dir; end SCR;
mit
b427432322fe20038cb91bbf4f0360d0
0.476705
3.545723
false
false
false
false
rjarzmik/mips_processor
ProgramCounter/instruction_record.vhd
1
3,510
------------------------------------------------------------------------------- -- Title : Instruction recording -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : instruction_record.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-12-07 -- Last update: 2016-12-10 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-07 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.instruction_defs.instr_tag_t; use work.instruction_defs.NB_PIPELINE_STAGES; ------------------------------------------------------------------------------- package instruction_record is constant ADDR_WIDTH : integer := 32; subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0); type instr_record is record pc : addr_t; predict_next_pc : addr_t; predict_is_branch : boolean; predict_is_ja : boolean; predict_is_jr : boolean; predict_take_branch : boolean; commited : boolean; commit_is_branch : boolean; commit_take_branch : boolean; end record; type instr_records is array(0 to NB_PIPELINE_STAGES - 1) of instr_record; function get_record(itag : in instr_tag_t; irecords : in instr_records) return instr_record; procedure record_one_instr(signal pc : in addr_t; signal predict_next_pc : in addr_t; signal itag : in instr_tag_t; signal itags : out instr_records); procedure retire_one_instr(signal itag : in instr_tag_t; signal itags : out instr_records); end package instruction_record; package body instruction_record is function get_record(itag : in instr_tag_t; irecords : in instr_records) return instr_record is variable o : instr_record; begin o := irecords(itag.tag); return o; end function get_record; procedure record_one_instr(signal pc : in addr_t; signal predict_next_pc : in addr_t; signal itag : in instr_tag_t; signal itags : out instr_records) is begin itags(itag.tag) <= (pc => pc, predict_next_pc => predict_next_pc, predict_is_branch => itag.is_branch, predict_is_ja => itag.is_ja, predict_is_jr => itag.is_jr, predict_take_branch => itag.is_branch_taken, commited => false, commit_is_branch => false, commit_take_branch => false ); end procedure record_one_instr; procedure retire_one_instr(signal itag : in instr_tag_t; signal itags : out instr_records) is begin itags(itag.tag).commited <= true; end procedure retire_one_instr; end package body instruction_record;
gpl-3.0
70836603189ba04fb5a4192629516a9d
0.480912
4.376559
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/variable_assignment/rule_008_test_input.vhd
1
456
architecture RTL of FIFO is begin process begin -- These are passing ret := ( data => (others => '-'), valid => '0', sop => '0', eop => '0', empty => (others => '0'), error => (others => '0') ); -- These are failing ret := (data => (others => '-'), valid => '0', sop => '0', eop => '0', empty => (others => '0'), error => (others => '0')); end process; end architecture RTL;
gpl-3.0
5e638b19c10882a4ada144721cf41be3
0.438596
3.507692
false
false
false
false
Yarr/Yarr-fw
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd
4
47,982
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.9 -- \ \ Application : MIG -- / / Filename : memc3_wrapper.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $ -- \ \ / \ Date Created : -- \___\/\___\ -- --Device : Spartan-6 --Design Name : DDR/DDR2/DDR3/LPDDR --Purpose : This module instantiates mcb_raw_wrapper module. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity memc3_wrapper is generic ( C_MEMCLK_PERIOD : integer := 2500; C_P0_MASK_SIZE : integer := 4; C_P0_DATA_PORT_SIZE : integer := 32; C_P1_MASK_SIZE : integer := 4; C_P1_DATA_PORT_SIZE : integer := 32; C_ARB_NUM_TIME_SLOTS : integer := 12; C_ARB_TIME_SLOT_0 : bit_vector := "000"; C_ARB_TIME_SLOT_1 : bit_vector := "000"; C_ARB_TIME_SLOT_2 : bit_vector := "000"; C_ARB_TIME_SLOT_3 : bit_vector := "000"; C_ARB_TIME_SLOT_4 : bit_vector := "000"; C_ARB_TIME_SLOT_5 : bit_vector := "000"; C_ARB_TIME_SLOT_6 : bit_vector := "000"; C_ARB_TIME_SLOT_7 : bit_vector := "000"; C_ARB_TIME_SLOT_8 : bit_vector := "000"; C_ARB_TIME_SLOT_9 : bit_vector := "000"; C_ARB_TIME_SLOT_10 : bit_vector := "000"; C_ARB_TIME_SLOT_11 : bit_vector := "000"; C_MEM_TRAS : integer := 45000; C_MEM_TRCD : integer := 12500; C_MEM_TREFI : integer := 7800000; C_MEM_TRFC : integer := 127500; C_MEM_TRP : integer := 12500; C_MEM_TWR : integer := 15000; C_MEM_TRTP : integer := 7500; C_MEM_TWTR : integer := 7500; C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN"; C_MEM_TYPE : string :="DDR2"; C_MEM_DENSITY : string :="1Gb"; C_NUM_DQ_PINS : integer := 4; C_MEM_BURST_LEN : integer := 8; C_MEM_CAS_LATENCY : integer := 5; C_MEM_ADDR_WIDTH : integer := 14; C_MEM_BANKADDR_WIDTH : integer := 3; C_MEM_NUM_COL_BITS : integer := 11; C_MEM_DDR1_2_ODS : string := "FULL"; C_MEM_DDR2_RTT : string := "50OHMS"; C_MEM_DDR2_DIFF_DQS_EN : string := "YES"; C_MEM_DDR2_3_PA_SR : string := "FULL"; C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; C_MEM_DDR3_CAS_LATENCY : integer:= 7; C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5; C_MEM_DDR3_ODS : string := "DIV6"; C_MEM_DDR3_RTT : string := "DIV2"; C_MEM_DDR3_AUTO_SR : string := "ENABLED"; C_MEM_MOBILE_PA_SR : string := "FULL"; C_MEM_MDDR_ODS : string := "FULL"; C_MC_CALIB_BYPASS : string := "NO"; C_LDQSP_TAP_DELAY_VAL : integer := 0; C_UDQSP_TAP_DELAY_VAL : integer := 0; C_LDQSN_TAP_DELAY_VAL : integer := 0; C_UDQSN_TAP_DELAY_VAL : integer := 0; C_DQ0_TAP_DELAY_VAL : integer := 0; C_DQ1_TAP_DELAY_VAL : integer := 0; C_DQ2_TAP_DELAY_VAL : integer := 0; C_DQ3_TAP_DELAY_VAL : integer := 0; C_DQ4_TAP_DELAY_VAL : integer := 0; C_DQ5_TAP_DELAY_VAL : integer := 0; C_DQ6_TAP_DELAY_VAL : integer := 0; C_DQ7_TAP_DELAY_VAL : integer := 0; C_DQ8_TAP_DELAY_VAL : integer := 0; C_DQ9_TAP_DELAY_VAL : integer := 0; C_DQ10_TAP_DELAY_VAL : integer := 0; C_DQ11_TAP_DELAY_VAL : integer := 0; C_DQ12_TAP_DELAY_VAL : integer := 0; C_DQ13_TAP_DELAY_VAL : integer := 0; C_DQ14_TAP_DELAY_VAL : integer := 0; C_DQ15_TAP_DELAY_VAL : integer := 0; C_SKIP_IN_TERM_CAL : integer := 0; C_SKIP_DYNAMIC_CAL : integer := 0; C_SIMULATION : string := "FALSE"; C_MC_CALIBRATION_MODE : string := "CALIBRATION"; C_MC_CALIBRATION_DELAY : string := "QUARTER"; C_CALIB_SOFT_IP : string := "TRUE" ); port ( -- high-speed PLL clock interface sysclk_2x : in std_logic; sysclk_2x_180 : in std_logic; pll_ce_0 : in std_logic; pll_ce_90 : in std_logic; pll_lock : in std_logic; async_rst : in std_logic; --User Port0 Interface Signals p0_cmd_clk : in std_logic; p0_cmd_en : in std_logic; p0_cmd_instr : in std_logic_vector(2 downto 0) ; p0_cmd_bl : in std_logic_vector(5 downto 0) ; p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ; p0_cmd_empty : out std_logic; p0_cmd_full : out std_logic; -- Data Wr Port signals p0_wr_clk : in std_logic; p0_wr_en : in std_logic; p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ; p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ; p0_wr_full : out std_logic; p0_wr_empty : out std_logic; p0_wr_count : out std_logic_vector(6 downto 0) ; p0_wr_underrun : out std_logic; p0_wr_error : out std_logic; --Data Rd Port signals p0_rd_clk : in std_logic; p0_rd_en : in std_logic; p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ; p0_rd_full : out std_logic; p0_rd_empty : out std_logic; p0_rd_count : out std_logic_vector(6 downto 0) ; p0_rd_overflow : out std_logic; p0_rd_error : out std_logic; --User Port1 Interface Signals p1_cmd_clk : in std_logic; p1_cmd_en : in std_logic; p1_cmd_instr : in std_logic_vector(2 downto 0) ; p1_cmd_bl : in std_logic_vector(5 downto 0) ; p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ; p1_cmd_empty : out std_logic; p1_cmd_full : out std_logic; -- Data Wr Port signals p1_wr_clk : in std_logic; p1_wr_en : in std_logic; p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ; p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ; p1_wr_full : out std_logic; p1_wr_empty : out std_logic; p1_wr_count : out std_logic_vector(6 downto 0) ; p1_wr_underrun : out std_logic; p1_wr_error : out std_logic; --Data Rd Port signals p1_rd_clk : in std_logic; p1_rd_en : in std_logic; p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ; p1_rd_full : out std_logic; p1_rd_empty : out std_logic; p1_rd_count : out std_logic_vector(6 downto 0) ; p1_rd_overflow : out std_logic; p1_rd_error : out std_logic; -- memory interface signals mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; -- mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0); mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_reset_n : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_dram_udm : out std_logic; mcb3_dram_dm : out std_logic; mcb3_rzq : inout std_logic; -- Calibration signals mcb_drp_clk : in std_logic; calib_done : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic ); end entity; architecture acch of memc3_wrapper is component mcb_raw_wrapper IS GENERIC ( C_MEMCLK_PERIOD : integer; C_PORT_ENABLE : std_logic_vector(5 downto 0); C_MEM_ADDR_ORDER : string; C_ARB_NUM_TIME_SLOTS : integer; C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0); C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0); C_PORT_CONFIG : string; C_MEM_TRAS : integer; C_MEM_TRCD : integer; C_MEM_TREFI : integer; C_MEM_TRFC : integer; C_MEM_TRP : integer; C_MEM_TWR : integer; C_MEM_TRTP : integer; C_MEM_TWTR : integer; C_NUM_DQ_PINS : integer; C_MEM_TYPE : string; C_MEM_DENSITY : string; C_MEM_BURST_LEN : integer; C_MEM_CAS_LATENCY : integer; C_MEM_ADDR_WIDTH : integer; C_MEM_BANKADDR_WIDTH : integer; C_MEM_NUM_COL_BITS : integer; C_MEM_DDR3_CAS_LATENCY : integer; C_MEM_MOBILE_PA_SR : string; C_MEM_DDR1_2_ODS : string; C_MEM_DDR3_ODS : string; C_MEM_DDR2_RTT : string; C_MEM_DDR3_RTT : string; C_MEM_MDDR_ODS : string; C_MEM_DDR2_DIFF_DQS_EN : string; C_MEM_DDR2_3_PA_SR : string; C_MEM_DDR3_CAS_WR_LATENCY : integer; C_MEM_DDR3_AUTO_SR : string; C_MEM_DDR2_3_HIGH_TEMP_SR : string; C_MEM_DDR3_DYN_WRT_ODT : string; C_MC_CALIB_BYPASS : string; C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0); C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0); C_CALIB_SOFT_IP : string; C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0); C_MC_CALIBRATION_CLK_DIV : integer; C_MC_CALIBRATION_MODE : string; C_MC_CALIBRATION_DELAY : string; LDQSP_TAP_DELAY_VAL : integer; UDQSP_TAP_DELAY_VAL : integer; LDQSN_TAP_DELAY_VAL : integer; UDQSN_TAP_DELAY_VAL : integer; DQ0_TAP_DELAY_VAL : integer; DQ1_TAP_DELAY_VAL : integer; DQ2_TAP_DELAY_VAL : integer; DQ3_TAP_DELAY_VAL : integer; DQ4_TAP_DELAY_VAL : integer; DQ5_TAP_DELAY_VAL : integer; DQ6_TAP_DELAY_VAL : integer; DQ7_TAP_DELAY_VAL : integer; DQ8_TAP_DELAY_VAL : integer; DQ9_TAP_DELAY_VAL : integer; DQ10_TAP_DELAY_VAL : integer; DQ11_TAP_DELAY_VAL : integer; DQ12_TAP_DELAY_VAL : integer; DQ13_TAP_DELAY_VAL : integer; DQ14_TAP_DELAY_VAL : integer; DQ15_TAP_DELAY_VAL : integer; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_SIMULATION : string ; C_SKIP_IN_TERM_CAL : integer; C_SKIP_DYNAMIC_CAL : integer; C_SKIP_DYN_IN_TERM : integer; C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) ); PORT ( -- HIGH-SPEED PLL clock interface sysclk_2x : in std_logic; sysclk_2x_180 : in std_logic; pll_ce_0 : in std_logic; pll_ce_90 : in std_logic; pll_lock : in std_logic; sys_rst : in std_logic; p0_arb_en : in std_logic; p0_cmd_clk : in std_logic; p0_cmd_en : in std_logic; p0_cmd_instr : in std_logic_vector(2 DOWNTO 0); p0_cmd_bl : in std_logic_vector(5 DOWNTO 0); p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); p0_cmd_empty : out std_logic; p0_cmd_full : out std_logic; p0_wr_clk : in std_logic; p0_wr_en : in std_logic; p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0); p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0); p0_wr_full : out std_logic; p0_wr_empty : out std_logic; p0_wr_count : out std_logic_vector(6 DOWNTO 0); p0_wr_underrun : out std_logic; p0_wr_error : out std_logic; p0_rd_clk : in std_logic; p0_rd_en : in std_logic; p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0); p0_rd_full : out std_logic; p0_rd_empty : out std_logic; p0_rd_count : out std_logic_vector(6 DOWNTO 0); p0_rd_overflow : out std_logic; p0_rd_error : out std_logic; p1_arb_en : in std_logic; p1_cmd_clk : in std_logic; p1_cmd_en : in std_logic; p1_cmd_instr : in std_logic_vector(2 DOWNTO 0); p1_cmd_bl : in std_logic_vector(5 DOWNTO 0); p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); p1_cmd_empty : out std_logic; p1_cmd_full : out std_logic; p1_wr_clk : in std_logic; p1_wr_en : in std_logic; p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0); p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0); p1_wr_full : out std_logic; p1_wr_empty : out std_logic; p1_wr_count : out std_logic_vector(6 DOWNTO 0); p1_wr_underrun : out std_logic; p1_wr_error : out std_logic; p1_rd_clk : in std_logic; p1_rd_en : in std_logic; p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0); p1_rd_full : out std_logic; p1_rd_empty : out std_logic; p1_rd_count : out std_logic_vector(6 DOWNTO 0); p1_rd_overflow : out std_logic; p1_rd_error : out std_logic; p2_arb_en : in std_logic; p2_cmd_clk : in std_logic; p2_cmd_en : in std_logic; p2_cmd_instr : in std_logic_vector(2 DOWNTO 0); p2_cmd_bl : in std_logic_vector(5 DOWNTO 0); p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); p2_cmd_empty : out std_logic; p2_cmd_full : out std_logic; p2_wr_clk : in std_logic; p2_wr_en : in std_logic; p2_wr_mask : in std_logic_vector(3 DOWNTO 0); p2_wr_data : in std_logic_vector(31 DOWNTO 0); p2_wr_full : out std_logic; p2_wr_empty : out std_logic; p2_wr_count : out std_logic_vector(6 DOWNTO 0); p2_wr_underrun : out std_logic; p2_wr_error : out std_logic; p2_rd_clk : in std_logic; p2_rd_en : in std_logic; p2_rd_data : out std_logic_vector(31 DOWNTO 0); p2_rd_full : out std_logic; p2_rd_empty : out std_logic; p2_rd_count : out std_logic_vector(6 DOWNTO 0); p2_rd_overflow : out std_logic; p2_rd_error : out std_logic; p3_arb_en : in std_logic; p3_cmd_clk : in std_logic; p3_cmd_en : in std_logic; p3_cmd_instr : in std_logic_vector(2 DOWNTO 0); p3_cmd_bl : in std_logic_vector(5 DOWNTO 0); p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); p3_cmd_empty : out std_logic; p3_cmd_full : out std_logic; p3_wr_clk : in std_logic; p3_wr_en : in std_logic; p3_wr_mask : in std_logic_vector(3 DOWNTO 0); p3_wr_data : in std_logic_vector(31 DOWNTO 0); p3_wr_full : out std_logic; p3_wr_empty : out std_logic; p3_wr_count : out std_logic_vector(6 DOWNTO 0); p3_wr_underrun : out std_logic; p3_wr_error : out std_logic; p3_rd_clk : in std_logic; p3_rd_en : in std_logic; p3_rd_data : out std_logic_vector(31 DOWNTO 0); p3_rd_full : out std_logic; p3_rd_empty : out std_logic; p3_rd_count : out std_logic_vector(6 DOWNTO 0); p3_rd_overflow : out std_logic; p3_rd_error : out std_logic; p4_arb_en : in std_logic; p4_cmd_clk : in std_logic; p4_cmd_en : in std_logic; p4_cmd_instr : in std_logic_vector(2 DOWNTO 0); p4_cmd_bl : in std_logic_vector(5 DOWNTO 0); p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); p4_cmd_empty : out std_logic; p4_cmd_full : out std_logic; p4_wr_clk : in std_logic; p4_wr_en : in std_logic; p4_wr_mask : in std_logic_vector(3 DOWNTO 0); p4_wr_data : in std_logic_vector(31 DOWNTO 0); p4_wr_full : out std_logic; p4_wr_empty : out std_logic; p4_wr_count : out std_logic_vector(6 DOWNTO 0); p4_wr_underrun : out std_logic; p4_wr_error : out std_logic; p4_rd_clk : in std_logic; p4_rd_en : in std_logic; p4_rd_data : out std_logic_vector(31 DOWNTO 0); p4_rd_full : out std_logic; p4_rd_empty : out std_logic; p4_rd_count : out std_logic_vector(6 DOWNTO 0); p4_rd_overflow : out std_logic; p4_rd_error : out std_logic; p5_arb_en : in std_logic; p5_cmd_clk : in std_logic; p5_cmd_en : in std_logic; p5_cmd_instr : in std_logic_vector(2 DOWNTO 0); p5_cmd_bl : in std_logic_vector(5 DOWNTO 0); p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0); p5_cmd_empty : out std_logic; p5_cmd_full : out std_logic; p5_wr_clk : in std_logic; p5_wr_en : in std_logic; p5_wr_mask : in std_logic_vector(3 DOWNTO 0); p5_wr_data : in std_logic_vector(31 DOWNTO 0); p5_wr_full : out std_logic; p5_wr_empty : out std_logic; p5_wr_count : out std_logic_vector(6 DOWNTO 0); p5_wr_underrun : out std_logic; p5_wr_error : out std_logic; p5_rd_clk : in std_logic; p5_rd_en : in std_logic; p5_rd_data : out std_logic_vector(31 DOWNTO 0); p5_rd_full : out std_logic; p5_rd_empty : out std_logic; p5_rd_count : out std_logic_vector(6 DOWNTO 0); p5_rd_overflow : out std_logic; p5_rd_error : out std_logic; mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0); mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0); mcbx_dram_ras_n : out std_logic; mcbx_dram_cas_n : out std_logic; mcbx_dram_we_n : out std_logic; mcbx_dram_cke : out std_logic; mcbx_dram_clk : out std_logic; mcbx_dram_clk_n : out std_logic; mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0); mcbx_dram_dqs : inout std_logic; mcbx_dram_dqs_n : inout std_logic; mcbx_dram_udqs : inout std_logic; mcbx_dram_udqs_n : inout std_logic; mcbx_dram_udm : out std_logic; mcbx_dram_ldm : out std_logic; mcbx_dram_odt : out std_logic; mcbx_dram_ddr3_rst : out std_logic; calib_recal : in std_logic; rzq : inout std_logic; zio : inout std_logic; ui_read : in std_logic; ui_add : in std_logic; ui_cs : in std_logic; ui_clk : in std_logic; ui_sdi : in std_logic; ui_addr : in std_logic_vector(4 DOWNTO 0); ui_broadcast : in std_logic; ui_drp_update : in std_logic; ui_done_cal : in std_logic; ui_cmd : in std_logic; ui_cmd_in : in std_logic; ui_cmd_en : in std_logic; ui_dqcount : in std_logic_vector(3 DOWNTO 0); ui_dq_lower_dec : in std_logic; ui_dq_lower_inc : in std_logic; ui_dq_upper_dec : in std_logic; ui_dq_upper_inc : in std_logic; ui_udqs_inc : in std_logic; ui_udqs_dec : in std_logic; ui_ldqs_inc : in std_logic; ui_ldqs_dec : in std_logic; uo_data : out std_logic_vector(7 DOWNTO 0); uo_data_valid : out std_logic; uo_done_cal : out std_logic; uo_cmd_ready_in : out std_logic; uo_refrsh_flag : out std_logic; uo_cal_start : out std_logic; uo_sdo : out std_logic; status : out std_logic_vector(31 DOWNTO 0); selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic ); end component; signal uo_data : std_logic_vector(7 downto 0); constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "000011"; constant C_PORT_CONFIG : string := "B64_B32_B32"; constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0)); constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0)); constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0)); constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0)); constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0)); constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0)); constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0)); constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0)); constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0)); constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0)); constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0)); constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & "000" & "000" & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0)); constant C_MC_CALIBRATION_CLK_DIV : integer := 1; constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000" + "0000010000"; -- 16 cycles are added to avoid trfc violations constant C_SKIP_DYN_IN_TERM : integer := 1; constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000"; constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0"; constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000"; constant C_MEM_DDR3_DYN_WRT_ODT : string := "OFF"; signal status : std_logic_vector(31 downto 0); signal uo_data_valid : std_logic; signal uo_cmd_ready_in : std_logic; signal uo_refrsh_flag : std_logic; signal uo_cal_start : std_logic; signal uo_sdo : std_logic; signal mcb3_zio : std_logic; attribute X_CORE_INFO : string; attribute X_CORE_INFO of acch : architecture IS "mig_v3_9_ddr3_s6, Coregen 13.3"; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr3_s6,mig_v3_9,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR3_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt41j128m16xx-15e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=DIV6, RTT_NOM=DIV4, AUTO_SR=ENABLED, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=One 64-bit bi-directional and two 32-bit bi-directional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1, INPUT_PIN_TERMINATION=EXTERN_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}"; begin memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper generic map ( C_MEMCLK_PERIOD => C_MEMCLK_PERIOD, C_P0_MASK_SIZE => C_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE, C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS, C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0, C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1, C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2, C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3, C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4, C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5, C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6, C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7, C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8, C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9, C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10, C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11, C_PORT_CONFIG => C_PORT_CONFIG, C_PORT_ENABLE => C_PORT_ENABLE, C_MEM_TRAS => C_MEM_TRAS, C_MEM_TRCD => C_MEM_TRCD, C_MEM_TREFI => C_MEM_TREFI, C_MEM_TRFC => C_MEM_TRFC, C_MEM_TRP => C_MEM_TRP, C_MEM_TWR => C_MEM_TWR, C_MEM_TRTP => C_MEM_TRTP, C_MEM_TWTR => C_MEM_TWTR, C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER, C_NUM_DQ_PINS => C_NUM_DQ_PINS, C_MEM_TYPE => C_MEM_TYPE, C_MEM_DENSITY => C_MEM_DENSITY, C_MEM_BURST_LEN => C_MEM_BURST_LEN, C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY, C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH, C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH, C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS, C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS, C_MEM_DDR2_RTT => C_MEM_DDR2_RTT, C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN, C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR, C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR, C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_ODS => C_MEM_DDR3_ODS, C_MEM_DDR3_RTT => C_MEM_DDR3_RTT, C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY, C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR, C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT, C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR, C_MEM_MDDR_ODS => C_MEM_MDDR_ODS, C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV, C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY, C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS, C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA, C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA, C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA, C_CALIB_SOFT_IP => C_CALIB_SOFT_IP, C_SIMULATION => C_SIMULATION, C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL, C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL, C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM, C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT, LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL, UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL, LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL, UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL, DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL, DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL, DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL, DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL, DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL, DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL, DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL, DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL, DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL, DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL, DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL, DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL, DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL, DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL, DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL, DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL ) port map ( sys_rst => async_rst, sysclk_2x => sysclk_2x, sysclk_2x_180 => sysclk_2x_180, pll_ce_0 => pll_ce_0, pll_ce_90 => pll_ce_90, pll_lock => pll_lock, mcbx_dram_addr => mcb3_dram_a, mcbx_dram_ba => mcb3_dram_ba, mcbx_dram_ras_n => mcb3_dram_ras_n, mcbx_dram_cas_n => mcb3_dram_cas_n, mcbx_dram_we_n => mcb3_dram_we_n, mcbx_dram_cke => mcb3_dram_cke, mcbx_dram_clk => mcb3_dram_ck, mcbx_dram_clk_n => mcb3_dram_ck_n, mcbx_dram_dq => mcb3_dram_dq, mcbx_dram_odt => mcb3_dram_odt, mcbx_dram_ldm => mcb3_dram_dm, mcbx_dram_udm => mcb3_dram_udm, mcbx_dram_dqs => mcb3_dram_dqs, mcbx_dram_dqs_n => mcb3_dram_dqs_n, mcbx_dram_udqs => mcb3_dram_udqs, mcbx_dram_udqs_n => mcb3_dram_udqs_n, mcbx_dram_ddr3_rst => mcb3_dram_reset_n, calib_recal => '0', rzq => mcb3_rzq, zio => mcb3_zio, ui_read => '0', ui_add => '0', ui_cs => '0', ui_clk => mcb_drp_clk, ui_sdi => '0', ui_addr => (others => '0'), ui_broadcast => '0', ui_drp_update => '0', ui_done_cal => '1', ui_cmd => '0', ui_cmd_in => '0', ui_cmd_en => '0', ui_dqcount => (others => '0'), ui_dq_lower_dec => '0', ui_dq_lower_inc => '0', ui_dq_upper_dec => '0', ui_dq_upper_inc => '0', ui_udqs_inc => '0', ui_udqs_dec => '0', ui_ldqs_inc => '0', ui_ldqs_dec => '0', uo_data => uo_data, uo_data_valid => uo_data_valid, uo_done_cal => calib_done, uo_cmd_ready_in => uo_cmd_ready_in, uo_refrsh_flag => uo_refrsh_flag, uo_cal_start => uo_cal_start, uo_sdo => uo_sdo, status => status, selfrefresh_enter => '0', selfrefresh_mode => selfrefresh_mode, p0_arb_en => '1', p0_cmd_clk => p0_cmd_clk, p0_cmd_en => p0_cmd_en, p0_cmd_instr => p0_cmd_instr, p0_cmd_bl => p0_cmd_bl, p0_cmd_byte_addr => p0_cmd_byte_addr, p0_cmd_empty => p0_cmd_empty, p0_cmd_full => p0_cmd_full, p0_wr_clk => p0_wr_clk, p0_wr_en => p0_wr_en, p0_wr_mask => p0_wr_mask, p0_wr_data => p0_wr_data, p0_wr_full => p0_wr_full, p0_wr_empty => p0_wr_empty, p0_wr_count => p0_wr_count, p0_wr_underrun => p0_wr_underrun, p0_wr_error => p0_wr_error, p0_rd_clk => p0_rd_clk, p0_rd_en => p0_rd_en, p0_rd_data => p0_rd_data, p0_rd_full => p0_rd_full, p0_rd_empty => p0_rd_empty, p0_rd_count => p0_rd_count, p0_rd_overflow => p0_rd_overflow, p0_rd_error => p0_rd_error, p1_arb_en => '1', p1_cmd_clk => p1_cmd_clk, p1_cmd_en => p1_cmd_en, p1_cmd_instr => p1_cmd_instr, p1_cmd_bl => p1_cmd_bl, p1_cmd_byte_addr => p1_cmd_byte_addr, p1_cmd_empty => p1_cmd_empty, p1_cmd_full => p1_cmd_full, p1_wr_clk => p1_wr_clk, p1_wr_en => p1_wr_en, p1_wr_mask => p1_wr_mask, p1_wr_data => p1_wr_data, p1_wr_full => p1_wr_full, p1_wr_empty => p1_wr_empty, p1_wr_count => p1_wr_count, p1_wr_underrun => p1_wr_underrun, p1_wr_error => p1_wr_error, p1_rd_clk => p1_rd_clk, p1_rd_en => p1_rd_en, p1_rd_data => p1_rd_data, p1_rd_full => p1_rd_full, p1_rd_empty => p1_rd_empty, p1_rd_count => p1_rd_count, p1_rd_overflow => p1_rd_overflow, p1_rd_error => p1_rd_error, p2_arb_en => '0', p2_cmd_clk => '0', p2_cmd_en => '0', p2_cmd_instr => (others => '0'), p2_cmd_bl => (others => '0'), p2_cmd_byte_addr => (others => '0'), p2_cmd_empty => open, p2_cmd_full => open, p2_rd_clk => '0', p2_rd_en => '0', p2_rd_data => open, p2_rd_full => open, p2_rd_empty => open, p2_rd_count => open, p2_rd_overflow => open, p2_rd_error => open, p2_wr_clk => '0', p2_wr_en => '0', p2_wr_mask => (others => '0'), p2_wr_data => (others => '0'), p2_wr_full => open, p2_wr_empty => open, p2_wr_count => open, p2_wr_underrun => open, p2_wr_error => open, p3_arb_en => '0', p3_cmd_clk => '0', p3_cmd_en => '0', p3_cmd_instr => (others => '0'), p3_cmd_bl => (others => '0'), p3_cmd_byte_addr => (others => '0'), p3_cmd_empty => open, p3_cmd_full => open, p3_rd_clk => '0', p3_rd_en => '0', p3_rd_data => open, p3_rd_full => open, p3_rd_empty => open, p3_rd_count => open, p3_rd_overflow => open, p3_rd_error => open, p3_wr_clk => '0', p3_wr_en => '0', p3_wr_mask => (others => '0'), p3_wr_data => (others => '0'), p3_wr_full => open, p3_wr_empty => open, p3_wr_count => open, p3_wr_underrun => open, p3_wr_error => open, p4_arb_en => '0', p4_cmd_clk => '0', p4_cmd_en => '0', p4_cmd_instr => (others => '0'), p4_cmd_bl => (others => '0'), p4_cmd_byte_addr => (others => '0'), p4_cmd_empty => open, p4_cmd_full => open, p4_rd_clk => '0', p4_rd_en => '0', p4_rd_data => open, p4_rd_full => open, p4_rd_empty => open, p4_rd_count => open, p4_rd_overflow => open, p4_rd_error => open, p4_wr_clk => '0', p4_wr_en => '0', p4_wr_mask => (others => '0'), p4_wr_data => (others => '0'), p4_wr_full => open, p4_wr_empty => open, p4_wr_count => open, p4_wr_underrun => open, p4_wr_error => open, p5_arb_en => '0', p5_cmd_clk => '0', p5_cmd_en => '0', p5_cmd_instr => (others => '0'), p5_cmd_bl => (others => '0'), p5_cmd_byte_addr => (others => '0'), p5_cmd_empty => open, p5_cmd_full => open, p5_rd_clk => '0', p5_rd_en => '0', p5_rd_data => open, p5_rd_full => open, p5_rd_empty => open, p5_rd_count => open, p5_rd_overflow => open, p5_rd_error => open, p5_wr_clk => '0', p5_wr_en => '0', p5_wr_mask => (others => '0'), p5_wr_data => (others => '0'), p5_wr_full => open, p5_wr_empty => open, p5_wr_count => open, p5_wr_underrun => open, p5_wr_error => open ); end architecture;
gpl-3.0
2303f3215033aa72f023c64e28ba2173
0.425806
3.495956
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/instantiation/rule_028_test_input.fixed_upper.vhd
1
823
architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); -- Violations below U_INST1 : entity fifo_dsn.1CLK_FIFO port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : entity fifo_dsn.1CLK_FIFO port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : entity 1CLK_FIFO port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); U_INST1 : entity 1CLK_FIFO port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3 ); end architecture ARCH;
gpl-3.0
64be2eef7ca817143b8c527895cf7577
0.484812
2.707237
false
false
false
false
rjarzmik/mips_processor
Caches/mask_feeder.vhd
1
3,379
------------------------------------------------------------------------------- -- Title : Feeds all first set bits of a mask -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : mask_feeder.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-12-21 -- Last update: 2016-12-21 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: -- Mask outputing the first set bit to clear on fbitset. -- Each cycle, bclr bit is cleared if bclrena is set. -- Priority of operation : -- 1) sclr : latch sdata -- 2) bclrean : clear one bit ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-21 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- entity mask_feeder is generic ( WIDTH : natural := 8 ); port ( clk : in std_logic; sclr : in std_logic; sdata : in std_logic_vector(WIDTH - 1 downto 0); bclrena : in std_logic; bclr : in natural range 0 to WIDTH - 1; fbitset : out natural range 0 to WIDTH - 1; allclear : out std_logic; dbg_data : out std_logic_vector(WIDTH - 1 downto 0) ); end entity mask_feeder; ------------------------------------------------------------------------------- architecture str of mask_feeder is constant ZERO_DATA : std_logic_vector(WIDTH - 1 downto 0) := (others => '0'); signal data : std_logic_vector(WIDTH - 1 downto 0); function get_fbs(vect : std_logic_vector) return natural is variable hlen : natural; variable hzero : std_logic_vector(vect'length / 2 - 1 downto 0); variable vlow : std_logic_vector(vect'length / 2 - 1 downto 0); variable vhigh : std_logic_vector(vect'length / 2 - 1 downto 0); begin hzero := (others => '0'); if vect'length = 2 then if vect(1) = '1' then return 1; else return 0; end if; else hlen := vect'length / 2; vlow := vect(hlen - 1 downto 0); vhigh := vect(vect'length - 1 downto hlen); if vhigh /= hzero then return hlen + get_fbs(vhigh); else return get_fbs(vlow); end if; end if; end function get_fbs; begin -- architecture str process(clk, sclr, bclrena, data) variable next_data : std_logic_vector(WIDTH - 1 downto 0); begin if rising_edge(clk) then if sclr = '1' then data <= sdata; fbitset <= get_fbs(sdata); elsif bclrena = '1' then data(bclr) <= '0'; next_data := data; next_data(bclr) := '0'; fbitset <= get_fbs(next_data); end if; end if; if data = ZERO_DATA then allclear <= '1'; else allclear <= '0'; end if; dbg_data <= data; end process; end architecture str; -------------------------------------------------------------------------------
gpl-3.0
7c12431a5bae566d57d955a910d5c967
0.463747
4.135863
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/vhdlFile/selected_waveform_assignment/classification_test_input.vhd
1
1,878
architecture RTL of ENTITY_NAME is begin process begin SEL_LABEL : with some expression select ? some target <= transport some expression when some choice | some other choice | some other other choice, some expression when some choice, some expression when some choice | some other choice; SEL_LABEL : with some expression select ? some target <= some expression when some choice | some other choice | some other other choice, some expression when some choice, some expression when some choice | some other choice; SEL_LABEL : with some expression select some target <= transport some expression when some choice | some other choice | some other other choice, some expression when some choice, some expression when some choice | some other choice; SEL_LABEL : with some expression select ? some target <= transport some expression when some choice; with some expression select ? some target <= some expression when some choice | some other choice | some other other choice, some expression when some choice, some expression when some choice | some other choice; with some expression select ? some target <= some expression after 10 ns when some choice | some other choice | some other other choice, null when some choice, null after 20 ns when some choice | some other choice, some expression after 10 ns, some other expression after 20 ns, some last expression when some choice | some other choice, unaffected when some last choice; end process; end architecture RTL;
gpl-3.0
f70dc72140d9eece8117be581bd1779a
0.617146
6.038585
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/constant/rule_016_test_input_assignment.fixed_assign_on_single_line_true.vhd
1
478
architecture rtl of fifo is constant cons1 : t_type := ( 1 => func1(std_logic_vector(G_GEN), G_GEN2), 2 => func1(std_logic_vector(G_GEN3), G_GEN4) ); constant cons1 : t_type := ( 1 => func1(std_logic_vector(G_GEN), G_GEN2), 2 => func1( std_logic_vector(G_GEN3), G_GEN4) ); constant cons1 : t_type := ( 1 => func1(std_logic_vector(G_GEN), G_GEN2), (others => '0'), 2 => func2(std_logic( G_GEN), G_GEN2) ); begin end architecture rtl;
gpl-3.0
096570f03de7aa3400962ceabc582cf8
0.579498
2.529101
false
false
false
false
siavooshpayandehazad/TTU_CPU_Project
pico_CPU/InstMem.vhd
1
3,075
library ieee; use ieee.std_logic_1164.all; use IEEE.Numeric_Std.all; use work.pico_cpu.all; entity InstMem is generic (BitWidth: integer; InstructionWidth: integer); port ( address : in std_logic_vector(BitWidth-1 downto 0); data : out std_logic_vector(InstructionWidth-1 downto 0) ); end entity InstMem; architecture behavioral of InstMem is type mem is array ( 0 to InstMem_depth-1) of std_logic_vector(InstructionWidth-1 downto 0); constant my_InstMem : mem := ( 0 => "10000100000000000000000000000000011000",--Load_B_Dir 1 => "00111100000000000000000000000000000000",--OR_A_B 2 => "00011000000000000000000000000000000000",--IncA 3 => "00001100000000000000000000000000000000",--Sub_A_B 4 => "01011000000000000000000000000000000111",--JmpC 7 5 => "11111000000000000000000000000011110000",--NOP 6 => "11111000000000000000000000000000000000",--NOP 7 => "00110000000000000000000000000000000000",--RRC 8 => "00110100000000000000000000000000000000",--RLC 9 => "11111000000000000000000000000000000000",--NOP 10 => "01101100000000000000000000000000000000",--ClearC 11 => "10000000000000000000000000000000010000",--Store_A_Mem 12 => "11110000000000000000000000000000000000",--PUSH 13 => "01111000000000000000000000000000000000",--SavePC 14 => "11110000000000000000000000000000000000",--PUSH 15 => "01001100000000000000000000000000010100",--Jmp 20 16 => "11110100000000000000000000000000000000", --pop 17 => "00100100000000000000000000000000000000", --ShiftArithL 18 => "00011100000000000000000000000000000000",--DecA 19 => "11111100000000000000000000000000000000", --HALT 20 => "01111100000000000000000000000000010000",--Load_A_Mem 21 => "00111000000000000000000000000000000000",--AND 22 => "01010000000000000000000000000000011000",--JMPZ 24 23 => "11111000000000000000000000000000000000",--NOP 24 => "01101100000000000000000000000000000000",--ClearZ 25 => "00000100000000000000000000000000010000",--Add_A_Mem 26 => "00010000000000000000000000000000010000",--Sub_A_Mem 27 => "00000000000000000000000000000000000000",--ADD_A_B 28 => "00010100000000000000000000000000001100",--SUB_A_DIR C 29 => "01000100000000000000000000000000000000",--FlipA 30 => "01000000000000000000000000000000000000",--XOR_A_B 31 => "01001000000000000000000000000000000000",--NegA 32 => "00100000000000000000000000000000000000",--ShiftArithR 33 => "00101100000000000000000000000000000000",--ShiftA_L 34 => "00101000000000000000000000000000000000",--ShiftA_R 35 => "01110000000000000000000000000000000000",--ClearACC 36 => "11110100000000000000000000000000000000",--POP 37 => "00001000000000000000000000000000000011",--Add_A_Dir 38 => "01110100000000000000000000000000000000",--LoadPC others => "00000000000000000000000000000000000000" ); begin process(address)begin if to_integer(unsigned(address)) <= InstMem_depth-1 then data <= my_InstMem(to_integer(unsigned(address))); else data <= (others => '0'); end if; end process; end architecture behavioral;
gpl-2.0
4593735da65ca205c4345d2143c96548
0.755447
4.767442
false
false
false
false
Yarr/Yarr-fw
rtl/tx-core/tx_channel.vhd
1
8,857
-- #################################### -- # Project: Yarr -- # Author: Timon Heim -- # E-Mail: timon.heim at cern.ch -- # Comments: Single tx_channel -- #################################### library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.board_pkg.all; entity tx_channel is port ( -- Sys connect wb_clk_i : in std_logic; rst_n_i : in std_logic; -- Data In wb_dat_i : in std_logic_vector(31 downto 0); wb_wr_en_i : in std_logic; -- TX tx_clk_i : in std_logic; tx_data_o : out std_logic; tx_enable_i : in std_logic; -- Word Looper loop_pulse_i : in std_logic; loop_mode_i : in std_logic; -- (WB clk domain) loop_word_i : in std_logic_vector(1023 downto 0); -- (WB clk domain) loop_word_bytes_i : in std_logic_vector(7 downto 0); -- (WB clk domain) -- Pulse pulse_word_i : in std_logic_vector(31 downto 0); pulse_interval_i : in std_logic_vector(15 downto 0); -- Sync sync_word_i : in std_logic_vector(31 downto 0); sync_interval_i : in std_logic_vector(7 downto 0); -- Idle idle_word_i : in std_logic_vector(31 downto 0); -- Status tx_underrun_o : out std_logic; tx_overrun_o : out std_logic; tx_almost_full_o : out std_logic; tx_empty_o : out std_logic ); end tx_channel; architecture rtl of tx_channel is -- Components component serial_port generic ( g_PORT_WIDTH : integer := 32 ); port ( -- Sys connect clk_i : in std_logic; rst_n_i : in std_logic; -- Input enable_i : in std_logic; data_i : in std_logic_vector(31 downto 0); idle_i : in std_logic_vector(31 downto 0); sync_i : in std_logic_vector(31 downto 0); sync_interval_i : in std_logic_vector(7 downto 0); pulse_i : in std_logic_vector(31 downto 0); pulse_interval_i : in std_logic_vector(15 downto 0); data_valid_i : in std_logic; -- Output data_o : out std_logic; data_read_o : out std_logic ); end component; component tx_fifo port ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; prog_full : OUT STD_LOGIC ); end component; --constant c_MAX_LOOP_CNT : unsigned(7 downto 0) := to_unsigned(4,8); signal tx_fifo_rd : std_logic; signal tx_fifo_wr : std_logic; signal tx_fifo_din : std_logic_vector(31 downto 0); signal tx_fifo_dout : std_logic_vector(31 downto 0); signal tx_fifo_full : std_logic; signal tx_fifo_empty : std_logic; signal tx_fifo_almost_full : std_logic; signal sport_data_valid : std_logic; signal sport_data : std_logic_vector(31 downto 0); signal sport_data_read : std_logic; signal loop_cnt : unsigned(7 downto 0); signal loop_empty : std_logic; signal loop_mode_s : std_logic; signal loop_word_s : std_logic_vector(1023 downto 0); signal loop_word_bytes_s : std_logic_vector(7 downto 0); signal pulse_word_s : std_logic_vector(31 downto 0); signal pulse_interval_s : std_logic_vector(15 downto 0); signal sync_word_s : std_logic_vector(31 downto 0); signal sync_interval_s : std_logic_vector(7 downto 0); signal idle_word_s : std_logic_vector(31 downto 0); begin -- Write to FiFo tx_fifo_wr <= wb_wr_en_i; tx_fifo_din <= wb_dat_i; -- Status outputs tx_underrun_o <= tx_fifo_rd and tx_fifo_empty; tx_overrun_o <= tx_fifo_wr and tx_fifo_full; tx_almost_full_o <= tx_fifo_almost_full; tx_empty_o <= tx_fifo_empty; loop_proc: process(tx_clk_i, rst_n_i) begin if (rst_n_i = '0') then loop_cnt <= (others => '0'); loop_empty <= '1'; loop_mode_s <= '0'; loop_word_s <= (others => '0'); loop_word_bytes_s <= (others => '0'); pulse_word_s <= c_TX_AZ_WORD; pulse_interval_s <= std_logic_vector(c_TX_AZ_INTERVAL); sync_word_s <= c_TX_SYNC_WORD; sync_interval_s <= std_logic_vector(c_TX_SYNC_INTERVAL); idle_word_s <= c_TX_IDLE_WORD; elsif rising_edge(tx_clk_i) then loop_empty <= '1'; loop_mode_s <= loop_mode_i; loop_word_s <= loop_word_i; loop_word_bytes_s <= loop_word_bytes_i; if (loop_mode_s = '1') then loop_empty <= '1'; if (loop_pulse_i = '1') then -- new pulse will restart the counter loop_cnt <= unsigned(loop_word_bytes_s); -- reload counter loop_empty <= '0'; elsif (sport_data_read = '1' and loop_cnt /= to_unsigned(0, 8)) then loop_cnt <= loop_cnt - 1; -- sport read one word loop_empty <= '0'; elsif (loop_cnt > to_unsigned(0,8)) then loop_empty <= '0'; end if; end if; pulse_word_s <= pulse_word_i; pulse_interval_s <= pulse_interval_i; sync_word_s <= sync_word_i; sync_interval_s <= sync_interval_i; idle_word_s <= idle_word_i; end if; end process loop_proc; sport_data_valid <= not tx_fifo_empty when (loop_mode_s = '0') else not loop_empty; tx_fifo_rd <= sport_data_read when (loop_mode_s = '0') else '0'; sport_data <= tx_fifo_dout when (loop_mode_s = '0') else loop_word_s(1023 downto 992) when (loop_cnt = to_unsigned(32, 8)) else -- MSB first loop_word_s(991 downto 960) when (loop_cnt = to_unsigned(31, 8)) else loop_word_s(959 downto 928) when (loop_cnt = to_unsigned(30, 8)) else loop_word_s(927 downto 896) when (loop_cnt = to_unsigned(29, 8)) else loop_word_s(895 downto 864) when (loop_cnt = to_unsigned(28, 8)) else loop_word_s(863 downto 832) when (loop_cnt = to_unsigned(27, 8)) else loop_word_s(831 downto 800) when (loop_cnt = to_unsigned(26, 8)) else loop_word_s(799 downto 768) when (loop_cnt = to_unsigned(25, 8)) else loop_word_s(767 downto 736) when (loop_cnt = to_unsigned(24, 8)) else loop_word_s(735 downto 704) when (loop_cnt = to_unsigned(23, 8)) else loop_word_s(703 downto 672) when (loop_cnt = to_unsigned(22, 8)) else loop_word_s(671 downto 640) when (loop_cnt = to_unsigned(21, 8)) else loop_word_s(639 downto 608) when (loop_cnt = to_unsigned(20, 8)) else loop_word_s(607 downto 576) when (loop_cnt = to_unsigned(19, 8)) else loop_word_s(575 downto 544) when (loop_cnt = to_unsigned(18, 8)) else loop_word_s(543 downto 512) when (loop_cnt = to_unsigned(17, 8)) else loop_word_s(511 downto 480) when (loop_cnt = to_unsigned(16, 8)) else loop_word_s(479 downto 448) when (loop_cnt = to_unsigned(15, 8)) else loop_word_s(447 downto 416) when (loop_cnt = to_unsigned(14, 8)) else loop_word_s(415 downto 384) when (loop_cnt = to_unsigned(13, 8)) else loop_word_s(383 downto 352) when (loop_cnt = to_unsigned(12, 8)) else loop_word_s(351 downto 320) when (loop_cnt = to_unsigned(11, 8)) else loop_word_s(319 downto 288) when (loop_cnt = to_unsigned(10, 8)) else loop_word_s(287 downto 256) when (loop_cnt = to_unsigned(9, 8)) else loop_word_s(255 downto 224) when (loop_cnt = to_unsigned(8, 8)) else loop_word_s(223 downto 192) when (loop_cnt = to_unsigned(7, 8)) else loop_word_s(191 downto 160) when (loop_cnt = to_unsigned(6, 8)) else loop_word_s(159 downto 128) when (loop_cnt = to_unsigned(5, 8)) else loop_word_s(127 downto 96) when (loop_cnt = to_unsigned(4, 8)) else loop_word_s(95 downto 64) when (loop_cnt = to_unsigned(3, 8)) else loop_word_s(63 downto 32) when (loop_cnt = to_unsigned(2, 8)) else loop_word_s(31 downto 0) when (loop_cnt = to_unsigned(1, 8)) else x"69696969"; cmp_sport: serial_port PORT MAP( clk_i => tx_clk_i, rst_n_i => rst_n_i, enable_i => tx_enable_i, data_i => sport_data, idle_i => idle_word_s, sync_i => sync_word_s, sync_interval_i => sync_interval_s, pulse_i => pulse_word_s, pulse_interval_i => pulse_interval_s, data_valid_i => sport_data_valid, data_o => tx_data_o, data_read_o => sport_data_read ); cmp_tx_fifo : tx_fifo PORT MAP ( rst => not rst_n_i, wr_clk => wb_clk_i, rd_clk => tx_clk_i, din => tx_fifo_din, wr_en => tx_fifo_wr, rd_en => tx_fifo_rd, dout => tx_fifo_dout, full => tx_fifo_full, empty => tx_fifo_empty, prog_full => tx_fifo_almost_full ); end rtl;
gpl-3.0
658b2dbd9d143233f061ef907e6c42f5
0.577848
2.944481
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sg_if.vhd
1
79,676
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sg_if.vhd -- Description: This entity is the S2MM Scatter Gather Interface for Descriptor -- Fetches and Updates. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; library proc_common_v4_0; use proc_common_v4_0.srl_fifo_f; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sg_if is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Any one of the 4 clock inputs is not -- synchronous to the other ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ; -- AXI Master Stream in for descriptor fetch C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ; -- 1 IOC bit + 32 Update Status Bits C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ; -- Master AXI Memory Map Address Width for S2MM Write Port C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ; -- Slave AXI Status Stream Data Width C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ; C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- s2mm_desc_info_in : in std_logic_vector (13 downto 0) ; -- -- SG S2MM Descriptor Fetch AXI Stream In -- m_axis_s2mm_ftch_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); -- m_axis_s2mm_ftch_tvalid : in std_logic ; -- m_axis_s2mm_ftch_tready : out std_logic ; -- m_axis_s2mm_ftch_tlast : in std_logic ; -- m_axis_s2mm_ftch_tdata_new : in std_logic_vector -- (96 downto 0); -- m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector -- (63 downto 0); -- m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector -- (31 downto 0); -- m_axis_s2mm_ftch_tvalid_new : in std_logic ; -- m_axis_ftch2_desc_available : in std_logic; -- -- -- SG S2MM Descriptor Update AXI Stream Out -- s_axis_s2mm_updtptr_tdata : out std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_updtptr_tvalid : out std_logic ; -- s_axis_s2mm_updtptr_tready : in std_logic ; -- s_axis_s2mm_updtptr_tlast : out std_logic ; -- -- s_axis_s2mm_updtsts_tdata : out std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_updtsts_tvalid : out std_logic ; -- s_axis_s2mm_updtsts_tready : in std_logic ; -- s_axis_s2mm_updtsts_tlast : out std_logic ; -- -- -- S2MM Descriptor Fetch Request (from s2mm_sm) -- desc_available : out std_logic ; -- desc_fetch_req : in std_logic ; -- updt_pending : out std_logic ; desc_fetch_done : out std_logic ; -- -- -- S2MM Descriptor Update Request (from s2mm_sm) -- desc_update_done : out std_logic ; -- s2mm_sts_received_clr : out std_logic ; -- s2mm_sts_received : in std_logic ; -- -- -- Scatter Gather Update Status -- s2mm_done : in std_logic ; -- s2mm_interr : in std_logic ; -- s2mm_slverr : in std_logic ; -- s2mm_decerr : in std_logic ; -- s2mm_tag : in std_logic_vector(3 downto 0) ; -- s2mm_brcvd : in std_logic_vector -- (C_SG_LENGTH_WIDTH-1 downto 0) ; -- s2mm_eof_set : in std_logic ; -- s2mm_packet_eof : in std_logic ; -- s2mm_halt : in std_logic ; -- -- -- S2MM Status Stream Interface -- stsstrm_fifo_rden : out std_logic ; -- stsstrm_fifo_empty : in std_logic ; -- stsstrm_fifo_dout : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); -- -- -- DataMover Command -- s2mm_cmnd_wr : in std_logic ; -- s2mm_cmnd_data : in std_logic_vector -- (((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- S2MM Descriptor Field Output -- s2mm_new_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- s2mm_new_curdesc_wren : out std_logic ; -- -- s2mm_desc_info : out std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_desc_baddress : out std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_desc_blength : out std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- s2mm_desc_blength_v : out std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- s2mm_desc_blength_s : out std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- s2mm_desc_cmplt : out std_logic ; -- s2mm_eof_micro : out std_logic ; s2mm_sof_micro : out std_logic ; s2mm_desc_app0 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- s2mm_desc_app1 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- s2mm_desc_app2 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- s2mm_desc_app3 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- s2mm_desc_app4 : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) -- ); end axi_dma_s2mm_sg_if; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sg_if is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ATTRIBUTE async_reg : STRING; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Status reserved bits constant RESERVED_STS : std_logic_vector(2 downto 0) := (others => '0'); -- Zero value constant constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0'); -- Zero length constant constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal ftch_shftenbl : std_logic := '0'; -- fetch descriptor holding registers signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_pending_update : std_logic := '0'; signal s2mm_new_curdesc_wren_i : std_logic := '0'; signal s2mm_ioc : std_logic := '0'; signal s2mm_pending_pntr_updt : std_logic := '0'; -- Descriptor Update Signals signal s2mm_complete : std_logic := '0'; signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0'); signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0'); -- Signals for pointer support -- Make 1 bit wider to allow tagging of LAST for use in generating tlast signal updt_desc_reg0 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0'); signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0'); signal updt_shftenbl : std_logic := '0'; signal updtptr_tvalid : std_logic := '0'; signal updtptr_tlast : std_logic := '0'; signal updtptr_tdata : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); -- Signals for Status Stream Support signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0'); signal writing_app_fields : std_logic := '0'; signal stsstrm_fifo_rden_i : std_logic := '0'; signal sts_shftenbl : std_logic := '0'; signal sts_received : std_logic := '0'; signal sts_received_d1 : std_logic := '0'; signal sts_received_re : std_logic := '0'; -- Queued Update signals signal updt_data_clr : std_logic := '0'; signal updt_sts_clr : std_logic := '0'; signal updt_data : std_logic := '0'; signal updt_sts : std_logic := '0'; signal ioc_tag : std_logic := '0'; signal s2mm_sof_set : std_logic := '0'; signal s2mm_in_progress : std_logic := '0'; signal eof_received : std_logic := '0'; signal sof_received : std_logic := '0'; signal updtsts_tvalid : std_logic := '0'; signal updtsts_tlast : std_logic := '0'; signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s2mm_halt_d1_cdc_tig : std_logic := '0'; signal s2mm_halt_cdc_d2 : std_logic := '0'; signal s2mm_halt_d2 : std_logic := '0'; --ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true"; signal desc_fetch_done_i : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Drive buffer length out s2mm_desc_blength <= s2mm_desc_blength_i; s2mm_desc_blength_v <= s2mm_desc_blength_v_i; s2mm_desc_blength_s <= s2mm_desc_blength_s_i; updt_pending <= s2mm_pending_update; -- Drive ready if descriptor fetch request is being made m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch and not s2mm_pending_update; -- No pending pointer updates desc_fetch_done <= desc_fetch_done_i; -- Shift in data from SG engine if tvalid and fetch request ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new and desc_fetch_req and not s2mm_pending_update; -- Passed curdes write out to register module s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i; -- tvalid asserted means descriptor availble desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new; --***************************************************************************-- --** Register DataMover Halt to secondary if needed --***************************************************************************-- GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate begin -- Double register to secondary clock domain. This is sufficient -- because halt will remain asserted until halt_cmplt detected in -- reset module in secondary clock domain. REG_TO_SECONDARY : entity proc_common_v4_0.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_halt, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => s2mm_halt_cdc_d2, scndry_vect_out => open ); -- REG_TO_SECONDARY : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- -- if(m_axi_sg_aresetn = '0')then -- -- s2mm_halt_d1_cdc_tig <= '0'; -- -- s2mm_halt_d2 <= '0'; -- -- else -- s2mm_halt_d1_cdc_tig <= s2mm_halt; -- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig; -- -- end if; -- end if; -- end process REG_TO_SECONDARY; s2mm_halt_d2 <= s2mm_halt_cdc_d2; end generate GEN_FOR_ASYNC; GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate begin -- No clock crossing required therefore simple pass through s2mm_halt_d2 <= s2mm_halt; end generate GEN_FOR_SYNC; --***************************************************************************-- --** Descriptor Fetch Logic **-- --***************************************************************************-- s2mm_desc_curdesc_lsb <= desc_reg0; s2mm_desc_curdesc_msb <= (others => '0'); --desc_reg1; --s2mm_desc_curdesc_lsb_nxt <= desc_reg2; --s2mm_desc_curdesc_msb_nxt <= desc_reg3; s2mm_desc_baddr_lsb <= desc_reg4; s2mm_desc_baddr_msb <= (others => '0'); --desc_reg5; GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0); desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32); desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); desc_reg9(30 downto 0) <= (others => '0'); s2mm_desc_curdesc_lsb_nxt <= desc_reg0; s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1; s2mm_desc_info <= (others => '0'); -- desc 4 and desc 5 are reserved and thus don't care s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT); s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT); s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT); s2mm_desc_blength_v_i <= (others => '0'); s2mm_desc_blength_s_i <= (others => '0') ; end generate GEN_NO_MCDMA; GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl; desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96); desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0); desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32); desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64); desc_reg9(30 downto 0) <= (others => '0'); desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0); desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0); desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32); s2mm_desc_curdesc_lsb_nxt <= desc_reg2; s2mm_desc_curdesc_msb_nxt <= desc_reg3; s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0); -- desc 4 and desc 5 are reserved and thus don't care s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0); s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19); s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0); end generate GEN_MCDMA; s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT); s2mm_desc_app0 <= (others => '0'); s2mm_desc_app1 <= (others => '0'); s2mm_desc_app2 <= (others => '0'); s2mm_desc_app3 <= (others => '0'); s2mm_desc_app4 <= (others => '0'); ------------------------------------------------------------------------------- -- BUFFER ADDRESS ------------------------------------------------------------------------------- -- If 64 bit addressing then concatinate msb to lsb GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb; end generate GEN_NEW_64BIT_BUFADDR; -- If 32 bit addressing then simply pass lsb out GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate s2mm_desc_baddress <= s2mm_desc_baddr_lsb; end generate GEN_NEW_32BIT_BUFADDR; ------------------------------------------------------------------------------- -- NEW CURRENT DESCRIPTOR ------------------------------------------------------------------------------- -- If 64 bit addressing then concatinate msb to lsb GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt; end generate GEN_NEW_64BIT_CURDESC; -- If 32 bit addressing then simply pass lsb out GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt; end generate GEN_NEW_32BIT_CURDESC; s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl; --***************************************************************************-- --** Descriptor Update Logic **-- --***************************************************************************-- -- SOF Flagging logic for when descriptor queues are enabled in SG Engine GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate -- SOF Queued one count value constant ONE_COUNT : std_logic_vector(2 downto 0) := "001"; signal incr_sof_count : std_logic := '0'; signal decr_sof_count : std_logic := '0'; signal sof_count : std_logic_vector(2 downto 0) := (others => '0'); signal sof_received_set : std_logic := '0'; signal sof_received_clr : std_logic := '0'; signal cmd_wr_mask : std_logic := '0'; begin -- Keep track of number of commands queued up in data mover to -- allow proper setting of SOF's and EOF's when associated -- descriptor is updated. REG_SOF_COUNT : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sof_count <= (others => '0'); elsif(incr_sof_count = '1')then sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1); elsif(decr_sof_count = '1')then sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1); end if; end if; end process REG_SOF_COUNT; -- Increment count on each command write that does NOT occur -- coincident with a status received incr_sof_count <= s2mm_cmnd_wr and not sts_received_re; -- Decrement count on each status received that does NOT -- occur coincident with a command write decr_sof_count <= sts_received_re and not s2mm_cmnd_wr; -- Drive sof and eof setting to interrupt module for delay interrupt --s2mm_packet_sof <= s2mm_sof_set; REG_SOF_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sof_received <= '0'; elsif(sof_received_set = '1')then sof_received <= '1'; elsif(sof_received_clr = '1')then sof_received <= '0'; end if; end if; end process REG_SOF_STATUS; -- SOF Received -- Case 1 (i.e. already running): EOF received therefore next has to be SOF -- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover and eof_received = '1') -- End of packet received -- OR... or (s2mm_cmnd_wr = '1' -- Command written to datamover and cmd_wr_mask = '0' -- Not inner-packet command and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds else '0'; -- Done with SOF's -- Status received and EOF received flag not set -- Or status received and EOF received flag set and last SOF sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0') or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT) else '0'; -- Mask command writes if inner-packet command written. An inner packet -- command is one where status if received and eof_received is not asserted. -- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning -- no commands happen to be queued in datamover. WR_MASK : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then cmd_wr_mask <= '0'; -- received data mover status, mask if EOF not set -- clear mask if EOF set. elsif(sts_received_re = '1')then cmd_wr_mask <= not eof_received; end if; end if; end process WR_MASK; end generate GEN_SOF_QUEUE_MODE; -- SOF Flagging logic for when descriptor queues are disabled in SG Engine GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin ----------------------------------------------------------------------- -- Assert window around receive packet in order to properly set -- SOF and EOF bits in descriptor -- -- SOF for S2MM determined by new command write to datamover, i.e. -- command write receive packet not already in progress. ----------------------------------------------------------------------- RX_IN_PROG_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then s2mm_in_progress <= '0'; s2mm_sof_set <= '0'; elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then s2mm_in_progress <= '1'; s2mm_sof_set <= '1'; else s2mm_in_progress <= s2mm_in_progress; s2mm_sof_set <= '0'; end if; end if; end process RX_IN_PROG_PROCESS; -- Drive sof and eof setting to interrupt module for delay interrupt --s2mm_packet_sof <= s2mm_sof_set; REG_SOF_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then sof_received <= '0'; elsif(s2mm_sof_set = '1')then sof_received <= '1'; end if; end if; end process REG_SOF_STATUS; end generate GEN_SOF_NO_QUEUE_MODE; -- IOC and EOF bits in desc update both set via packet eof flag from -- command/status interface. eof_received <= s2mm_packet_eof; s2mm_ioc <= s2mm_packet_eof; --***************************************************************************-- --** Descriptor Update Logic **-- --***************************************************************************-- --***************************************************************************** --** Pointer Update Logic --***************************************************************************** ----------------------------------------------------------------------- -- Capture LSB cur descriptor on write for use on descriptor update. -- This will be the address the descriptor is updated to ----------------------------------------------------------------------- UPDT_DESC_WRD0: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_reg0 <= (others => '0'); elsif(s2mm_new_curdesc_wren_i = '1')then updt_desc_reg0 <= DESC_LAST & s2mm_desc_curdesc_lsb; end if; end if; end process UPDT_DESC_WRD0; --------------------------------------------------------------------------- -- Capture MSB cur descriptor on write for use on descriptor update. -- This will be the address the descriptor is updated to --------------------------------------------------------------------------- UPDT_DESC_WRD1: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_reg1 <= (others => '0'); elsif(s2mm_new_curdesc_wren_i = '1')then updt_desc_reg1 <= DESC_LAST & s2mm_desc_curdesc_msb; end if; end if; end process UPDT_DESC_WRD1; -- Shift in pointer to SG engine if tvalid, tready, and not on last word updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready; -- Update data done when updating data and tlast received and target -- (i.e. SG Engine) is ready updt_data_clr <= '1' when updtptr_tvalid = '1' and updtptr_tlast = '1' and s_axis_s2mm_updtptr_tready = '1' else '0'; --------------------------------------------------------------------------- -- When desc data ready for update set and hold flag until -- data can be updated to queue. Note it may -- be held off due to update of status --------------------------------------------------------------------------- UPDT_DATA_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then updt_data <= '0'; -- clear flag when data update complete -- elsif(updt_data_clr = '1')then -- updt_data <= '0'; -- -- set flag when desc fetched as indicated -- -- by curdesc wren elsif(s2mm_new_curdesc_wren_i = '1')then updt_data <= '1'; end if; end if; end process UPDT_DATA_PROCESS; updtptr_tvalid <= updt_data; updtptr_tlast <= updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH); updtptr_tdata <= updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- Pass out to sg engine s_axis_s2mm_updtptr_tdata <= updtptr_tdata; s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid; s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid; --***************************************************************************** --** Status Update Logic - DESCRIPTOR QUEUES INCLUDED ** --***************************************************************************** GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate signal xb_fifo_reset : std_logic := '0'; signal xb_fifo_full : std_logic := '0'; begin s2mm_complete <= '1'; -- Fixed at '1' ----------------------------------------------------------------------- -- Need to flag a pending point update to prevent subsequent fetch of -- descriptor from stepping on the stored pointer, and buffer length ----------------------------------------------------------------------- REG_PENDING_UPDT : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then s2mm_pending_pntr_updt <= '0'; elsif(s2mm_new_curdesc_wren_i = '1')then s2mm_pending_pntr_updt <= '1'; end if; end if; end process REG_PENDING_UPDT; -- Pending update on pointer not updated yet or xfer'ed bytes fifo full s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full; -- Clear status received flag in cmdsts_if to -- allow more status to be received from datamover s2mm_sts_received_clr <= updt_sts_clr; -- Generate a rising edge off status received in order to -- flag status update REG_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sts_received_d1 <= '0'; else sts_received_d1 <= s2mm_sts_received; end if; end if; end process REG_STATUS; -- CR 566306 Status invalid during halt -- sts_received_re <= s2mm_sts_received and not sts_received_d1; sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2; --------------------------------------------------------------------------- -- When status received set and hold flag until -- status can be updated to queue. Note it may -- be held off due to update of data --------------------------------------------------------------------------- UPDT_STS_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then updt_sts <= '0'; -- clear flag when status update done or -- datamover halted -- elsif(updt_sts_clr = '1')then -- updt_sts <= '0'; -- set flag when status received elsif(sts_received_re = '1')then updt_sts <= '1'; end if; end if; end process UPDT_STS_PROCESS; updt_sts_clr <= '1' when updt_sts = '1' and updtsts_tvalid = '1' and updtsts_tlast = '1' and s_axis_s2mm_updtsts_tready = '1' else '0'; -- for queue case used to keep track of number of datamover queued cmnds UPDT_DONE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_update_done <= '0'; else desc_update_done <= updt_sts_clr; end if; end if; end process UPDT_DONE_PROCESS; --***********************************************************************-- --** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **-- --***********************************************************************-- --------------------------------------------------------------------------- -- Generate Descriptor Update Signaling for NO Status App Stream --------------------------------------------------------------------------- GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate begin stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode -- Transferred byte length from status is equal to bytes transferred field -- in descriptor status GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate begin s2mm_xferd_bytes <= s2mm_brcvd; end generate GEN_EQ_23BIT_BYTE_XFERED; -- Transferred byte length from status is less than bytes transferred field -- in descriptor status therefore need to pad value. GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd; end generate GEN_LESSTHN_23BIT_BYTE_XFERED; ----------------------------------------------------------------------- -- Catpure Status. Status is built from status word from DataMover -- and from transferred bytes value. ----------------------------------------------------------------------- UPDT_DESC_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_sts <= (others => '0'); elsif(sts_received_re = '1')then updt_desc_sts <= DESC_LAST & s2mm_ioc & s2mm_complete & s2mm_decerr & s2mm_slverr & s2mm_interr & sof_received -- If asserted also set SOF & eof_received -- If asserted also set EOF & RESERVED_STS & s2mm_xferd_bytes; end if; end if; end process UPDT_DESC_STATUS; -- Drive TVALID updtsts_tvalid <= updt_sts; -- Drive TLast updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH); -- Drive TData GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) & s2mm_desc_info_in (13 downto 10) & "000" & s2mm_desc_info_in (9 downto 5) & "000" & s2mm_desc_info_in (4 downto 0); end generate GEN_DESC_UPDT_MCDMA; GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); end generate GEN_DESC_UPDT_DMA; end generate GEN_DESC_UPDT_NO_STSAPP; --***********************************************************************-- --** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **-- --***********************************************************************-- --------------------------------------------------------------------------- -- Generate Descriptor Update Signaling for Status App Stream --------------------------------------------------------------------------- GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate begin -- Get rx length is identical to command written, therefor store -- the BTT value from the command written to be used as the xferd bytes. GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin ----------------------------------------------------------------------- -- On S2MM transferred bytes equals buffer length. Capture length -- on curdesc write. ----------------------------------------------------------------------- XFERRED_BYTE_FIFO : entity proc_common_v4_0.srl_fifo_f generic map( C_DWIDTH => BUFFER_LENGTH_WIDTH , C_DEPTH => 16 , C_FAMILY => C_FAMILY ) port map( Clk => m_axi_sg_aclk , Reset => xb_fifo_reset , FIFO_Write => s2mm_cmnd_wr , Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) , FIFO_Read => sts_received_re , Data_Out => s2mm_xferd_bytes , FIFO_Empty => open , FIFO_Full => xb_fifo_full , Addr => open ); xb_fifo_reset <= not m_axi_sg_aresetn; end generate GEN_USING_STSAPP_LENGTH; -- Not using status app length field therefore primary S2MM DataMover is -- configured as a store and forward channel (i.e. indeterminate BTT mode) -- Receive length will be reported in datamover status. GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode -- Transferred byte length from status is equal to bytes transferred field -- in descriptor status GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate begin s2mm_xferd_bytes <= s2mm_brcvd; end generate GEN_EQ_23BIT_BYTE_XFERED; -- Transferred byte length from status is less than bytes transferred field -- in descriptor status therefore need to pad value. GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd; end generate GEN_LESSTHN_23BIT_BYTE_XFERED; end generate GEN_NOT_USING_STSAPP_LENGTH; ----------------------------------------------------------------------- -- For EOF Descriptor then need to update APP fields from Status -- Stream FIFO ----------------------------------------------------------------------- WRITE_APP_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then writing_app_fields <= '0'; -- If writing app fields and reach LAST then stop writing -- app fields elsif(writing_app_fields = '1' -- Writing app fields and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1) and stsstrm_fifo_rden_i = '1')then -- Fifo read writing_app_fields <= '0'; -- ON EOF Descriptor, then need to write application fields on desc -- update elsif(s2mm_packet_eof = '1' and s2mm_xferd_bytes /= ZERO_LENGTH) then writing_app_fields <= '1'; end if; end if; end process WRITE_APP_PROCESS; -- Shift in apps to SG engine if tvalid, tready, and not on last word sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready; ----------------------------------------------------------------------- -- Catpure Status. Status is built from status word from DataMover -- and from transferred bytes value. ----------------------------------------------------------------------- UPDT_DESC_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_sts <= (others => '0'); elsif(sts_received_re = '1')then updt_desc_sts <= DESC_NOT_LAST & s2mm_ioc & s2mm_complete & s2mm_decerr & s2mm_slverr & s2mm_interr & sof_received -- If asserted also set SOF & eof_received -- If asserted also set EOF & RESERVED_STS & s2mm_xferd_bytes; elsif(sts_shftenbl='1')then updt_desc_sts <= updt_desc_reg3; end if; end if; end process UPDT_DESC_STATUS; ----------------------------------------------------------------------- -- If EOF Descriptor (writing_app_fields=1) then pass data from -- status stream FIFO into descriptor update shift registers -- Else pass zeros ----------------------------------------------------------------------- UPDT_REG3_MUX : process(writing_app_fields, stsstrm_fifo_dout, updt_zero_reg3, sts_shftenbl) begin if(writing_app_fields = '1')then updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting & '0' & stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word stsstrm_fifo_rden_i <= sts_shftenbl; else updt_desc_reg3 <= updt_zero_reg3; stsstrm_fifo_rden_i <= '0'; end if; end process UPDT_REG3_MUX; stsstrm_fifo_rden <= stsstrm_fifo_rden_i; ----------------------------------------------------------------------- -- APP 0 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD3 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream & '0' -- Don't set IOC & ZERO_VALUE; -- Remainder is zero -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg3 <= updt_zero_reg4; end if; end if; end process UPDT_ZERO_WRD3; ----------------------------------------------------------------------- -- APP 1 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD4 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream & '0' -- Don't set IOC & ZERO_VALUE; -- Remainder is zero -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg4 <= updt_zero_reg5; end if; end if; end process UPDT_ZERO_WRD4; ----------------------------------------------------------------------- -- APP 2 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD5 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream & '0' -- Don't set IOC & ZERO_VALUE; -- Remainder is zero -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg5 <= updt_zero_reg6; end if; end if; end process UPDT_ZERO_WRD5; ----------------------------------------------------------------------- -- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD6 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream & '0' -- Don't set IOC & ZERO_VALUE; -- Remainder is zero -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg6 <= DESC_LAST -- Last word of stream & s2mm_ioc & ZERO_VALUE; -- Remainder is zero end if; end if; end process UPDT_ZERO_WRD6; ----------------------------------------------------------------------- -- Drive TVALID -- If writing app then base on stsstrm fifo empty flag -- If writing datamover status then base simply assert on updt_sts ----------------------------------------------------------------------- TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty) begin if(updt_sts = '1' and writing_app_fields = '1')then updtsts_tvalid <= not stsstrm_fifo_empty; else updtsts_tvalid <= updt_sts; end if; end process TVALID_MUX; -- Drive TLAST updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH); -- Drive TDATA updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); end generate GEN_DESC_UPDT_STSAPP; -- Pass out to sg engine s_axis_s2mm_updtsts_tdata <= updtsts_tdata; s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid; s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid; end generate GEN_DESC_UPDT_QUEUE; --***************************************************************************-- --** Status Update Logic - NO DESCRIPTOR QUEUES **-- --***************************************************************************-- GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration -- Status received based on a DONE or an ERROR from DataMover sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr; -- Generate a rising edge off done for use in triggering an -- update to the SG engine REG_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sts_received_d1 <= '0'; else sts_received_d1 <= sts_received; end if; end if; end process REG_STATUS; -- CR 566306 Status invalid during halt -- sts_received_re <= sts_received and not sts_received_d1; sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2; --------------------------------------------------------------------------- -- When status received set and hold flag until -- status can be updated to queue. Note it may -- be held off due to update of data --------------------------------------------------------------------------- UPDT_STS_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_sts <= '0'; -- clear flag when status update done elsif(updt_sts_clr = '1')then updt_sts <= '0'; -- set flag when status received elsif(sts_received_re = '1')then updt_sts <= '1'; end if; end if; end process UPDT_STS_PROCESS; -- Clear status update on acceptance of tlast by sg engine updt_sts_clr <= '1' when updt_sts = '1' and updtsts_tvalid = '1' and updtsts_tlast = '1' and s_axis_s2mm_updtsts_tready = '1' else '0'; -- for queue case used to keep track of number of datamover queued cmnds UPDT_DONE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_update_done <= '0'; else desc_update_done <= updt_sts_clr; end if; end if; end process UPDT_DONE_PROCESS; --***********************************************************************-- --** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **-- --***********************************************************************-- --------------------------------------------------------------------------- -- Generate Descriptor Update Signaling for NO Status App Stream --------------------------------------------------------------------------- GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate begin stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate begin -- Transferred byte length from status is equal to bytes transferred field -- in descriptor status GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate begin s2mm_xferd_bytes <= s2mm_brcvd; end generate GEN_EQ_23BIT_BYTE_XFERED; -- Transferred byte length from status is less than bytes transferred field -- in descriptor status therefore need to pad value. GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd; end generate GEN_LESSTHN_23BIT_BYTE_XFERED; end generate GEN_NO_MICRO_DMA; GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate begin s2mm_xferd_bytes <= (others => '0'); end generate GEN_MICRO_DMA; ----------------------------------------------------------------------- -- Catpure Status. Status is built from status word from DataMover -- and from transferred bytes value. ----------------------------------------------------------------------- UPDT_DESC_WRD2 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_sts <= (others => '0'); -- Register Status on status received rising edge elsif(sts_received_re = '1')then updt_desc_sts <= DESC_LAST & s2mm_ioc & s2mm_complete & s2mm_decerr & s2mm_slverr & s2mm_interr & sof_received -- If asserted also set SOF & eof_received -- If asserted also set EOF & RESERVED_STS & s2mm_xferd_bytes; end if; end if; end process UPDT_DESC_WRD2; GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) & s2mm_desc_info_in (13 downto 10) & "000" & s2mm_desc_info_in (9 downto 5) & "000" & s2mm_desc_info_in (4 downto 0); end generate GEN_DESC_UPDT_MCDMA_NOQUEUE; GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); end generate GEN_DESC_UPDT_DMA_NOQUEUE; -- Drive TVALID updtsts_tvalid <= updt_sts; -- Drive TLAST updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH); -- Drive TData -- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0); end generate GEN_DESC_UPDT_NO_STSAPP; --***********************************************************************-- --** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **-- --***********************************************************************-- --------------------------------------------------------------------------- -- Generate Descriptor Update Signaling for NO Status App Stream --------------------------------------------------------------------------- GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate begin -- Rx length is identical to command written, therefore store -- the BTT value from the command written to be used as the xferd bytes. GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin ----------------------------------------------------------------------- -- On S2MM transferred bytes equals buffer length. Capture length -- on curdesc write. ----------------------------------------------------------------------- REG_XFERRED_BYTES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_xferd_bytes <= (others => '0'); elsif(s2mm_cmnd_wr = '1')then s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0); end if; end if; end process REG_XFERRED_BYTES; end generate GEN_USING_STSAPP_LENGTH; -- Configured as a store and forward channel (i.e. indeterminate BTT mode) -- Receive length will be reported in datamover status. GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin -- Transferred byte length from status is equal to bytes transferred field -- in descriptor status GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate begin s2mm_xferd_bytes <= s2mm_brcvd; end generate GEN_EQ_23BIT_BYTE_XFERED; -- Transferred byte length from status is less than bytes transferred field -- in descriptor status therefore need to pad value. GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd; end generate GEN_LESSTHN_23BIT_BYTE_XFERED; end generate GEN_NOT_USING_STSAPP_LENGTH; ----------------------------------------------------------------------- -- For EOF Descriptor then need to update APP fields from Status -- Stream FIFO ----------------------------------------------------------------------- WRITE_APP_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_app_fields <= '0'; -- If writing app fields and reach LAST then stop writing -- app fields elsif(writing_app_fields = '1' -- Writing app fields and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1) and stsstrm_fifo_rden_i = '1')then -- Fifo read writing_app_fields <= '0'; -- ON EOF Descriptor, then need to write application fields on desc -- update elsif(eof_received = '1' and s2mm_xferd_bytes /= ZERO_LENGTH) then writing_app_fields <= '1'; end if; end if; end process WRITE_APP_PROCESS; -- Shift in apps to SG engine if tvalid, tready, and not on last word sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready; ----------------------------------------------------------------------- -- Catpure Status. Status is built from status word from DataMover -- and from transferred bytes value. ----------------------------------------------------------------------- UPDT_DESC_WRD2 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_desc_sts <= (others => '0'); -- Status from Prmry Datamover received elsif(sts_received_re = '1')then updt_desc_sts <= DESC_NOT_LAST & s2mm_ioc & s2mm_complete & s2mm_decerr & s2mm_slverr & s2mm_interr & sof_received -- If asserted also set SOF & eof_received -- If asserted also set EOF & RESERVED_STS & s2mm_xferd_bytes; -- Shift on descriptor update elsif(sts_shftenbl = '1')then updt_desc_sts <= updt_desc_reg3; end if; end if; end process UPDT_DESC_WRD2; ----------------------------------------------------------------------- -- If EOF Descriptor (writing_app_fields=1) then pass data from -- status stream FIFO into descriptor update shift registers -- Else pass zeros ----------------------------------------------------------------------- UPDT_REG3_MUX : process(writing_app_fields, stsstrm_fifo_dout, updt_zero_reg3, sts_shftenbl) begin if(writing_app_fields = '1')then updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting & '0' & stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word stsstrm_fifo_rden_i <= sts_shftenbl; else updt_desc_reg3 <= updt_zero_reg3; stsstrm_fifo_rden_i <= '0'; end if; end process UPDT_REG3_MUX; stsstrm_fifo_rden <= stsstrm_fifo_rden_i; ----------------------------------------------------------------------- -- APP 0 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD3 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg3 <= (others => '0'); -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg3 <= updt_zero_reg4; end if; end if; end process UPDT_ZERO_WRD3; ----------------------------------------------------------------------- -- APP 1 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD4 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg4 <= (others => '0'); -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg4 <= updt_zero_reg5; end if; end if; end process UPDT_ZERO_WRD4; ----------------------------------------------------------------------- -- APP 2 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD5 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg5 <= (others => '0'); -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg5 <= updt_zero_reg6; end if; end if; end process UPDT_ZERO_WRD5; ----------------------------------------------------------------------- -- APP 3 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD6 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then updt_zero_reg6 <= (others => '0'); -- Shift data out on shift enable elsif(sts_shftenbl = '1')then updt_zero_reg6 <= updt_zero_reg7; end if; end if; end process UPDT_ZERO_WRD6; ----------------------------------------------------------------------- -- APP 4 Register (Set to Zero for Non-EOF Descriptor) ----------------------------------------------------------------------- UPDT_ZERO_WRD7 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_zero_reg7 <= (others => '0'); elsif(sts_received_re = '1')then updt_zero_reg7 <= DESC_LAST & '0' & ZERO_VALUE; end if; end if; end process UPDT_ZERO_WRD7; ----------------------------------------------------------------------- -- Drive TVALID -- If writing app then base on stsstrm fifo empty flag -- If writing datamover status then base simply assert on updt_sts ----------------------------------------------------------------------- TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty) begin if(updt_sts = '1' and writing_app_fields = '1')then updtsts_tvalid <= not stsstrm_fifo_empty; else updtsts_tvalid <= updt_sts; end if; end process TVALID_MUX; -- Drive TDATA updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- DRIVE TLAST updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH); end generate GEN_DESC_UPDT_STSAPP; -- Pass out to sg engine s_axis_s2mm_updtsts_tdata <= updtsts_tdata; s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid; s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid; end generate GEN_DESC_UPDT_NO_QUEUE; end implementation;
bsd-2-clause
2e23cc21e2e87f2f4023c02aca7564b7
0.432916
4.529362
false
false
false
false
rjarzmik/mips_processor
ProgramCounter/Instruction_Tracker.vhd
1
3,930
------------------------------------------------------------------------------- -- Title : Instruction Tracker -- Project : Source files in two directories, custom library name, VHDL'87 ------------------------------------------------------------------------------- -- File : Instruction_Tracker.vhd -- Author : Robert Jarzmik <[email protected]> -- Company : -- Created : 2016-12-07 -- Last update: 2016-12-10 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Each in-flight instruction in the pipeline tracker ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-12-07 1.0 rj Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.cpu_defs.all; use work.instruction_defs.all; use work.instruction_record.all; ------------------------------------------------------------------------------- entity Instruction_Tracker is generic ( ADDR_WIDTH : integer ); port ( clk : in std_logic; rst : in std_logic; -- Input instruction recorder --- Acquire enable, (i_pc1 and i_pc1_instr_tag will be linked together). i_record_pc1_req : in std_logic; --- Acquire enable, (i_pc2 and i_pc2_instr_tag will be linked together). i_record_pc2_req : in std_logic; i_pc1 : in std_logic_vector(ADDR_WIDTH - 1 downto 0); i_pc2 : in std_logic_vector(ADDR_WIDTH - 1 downto 0); i_pc1_instr_tag : in instr_tag_t; i_pc2_instr_tag : in instr_tag_t; i_pc1_predict_next_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0); i_pc2_predict_next_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- Retire instruction recorder i_commited_instr_tag : in instr_tag_t; i_jump_target : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- Misprediction computation o_commited_instr_record : out instr_record; o_commited_instr_tag : out instr_tag_t; -- Branch prediction module i_btb_instr_tag : in instr_tag_t; o_btb_instr_record : out instr_record -- available on next cycle ); end entity Instruction_Tracker; ------------------------------------------------------------------------------- architecture rtl of Instruction_Tracker is subtype addr_t is std_logic_vector(ADDR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- signal irecords : instr_records; signal commited_instr_record : instr_record; begin -- architecture rtl itrack_recorder : process(clk, rst) is begin if rst = '1' then elsif rising_edge(clk) then if i_record_pc1_req = '1' then record_one_instr(i_pc1, i_pc1_predict_next_pc, i_pc1_instr_tag, irecords); end if; if i_record_pc2_req = '1' then record_one_instr(i_pc2, i_pc2_predict_next_pc, i_pc2_instr_tag, irecords); end if; if i_commited_instr_tag.valid then retire_one_instr(i_commited_instr_tag, irecords); end if; end if; end process itrack_recorder; -- Misprediction forwarding commited_instr_record <= get_record(i_commited_instr_tag, irecords); o_commited_instr_record <= commited_instr_record; -- Commited instruction forwarding o_commited_instr_tag <= i_commited_instr_tag; end architecture rtl; -------------------------------------------------------------------------------
gpl-3.0
cc8915a5f44c99851b0ef498591e20a2
0.489567
4.16755
false
false
false
false
Yarr/Yarr-fw
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd
19
21,926
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version: %version -- \ \ Application: MIG -- / / Filename: mcb_soft_calibration_top.vhd -- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $ -- \ \ / \ Date Created: Mon Feb 9 2009 -- \___\/\___\ -- --Device: Spartan6 --Design Name: DDR/DDR2/DDR3/LPDDR --Purpose: Xilinx reference design top-level simulation -- wrapper file for input termination calibration --Reference: -- -- Revision: Date: Comment -- 1.0: 2/06/09: Initial version for MIG wrapper. -- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset -- 1.2: 6/06/09: Removed MCB_UIDQCOUNT. -- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port -- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets -- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration -- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration -- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin. -- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait . -- End Revision --********************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity mcb_soft_calibration_top is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values, -- and does dynamic recal, -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* -- no dynamic recal will be done SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design ); port ( UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for -- IODRP (sub)controller IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high -- (MCB hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; MCB_UODONECAL : in std_logic; MCB_UOREFRSHFLAG : in std_logic; MCB_UICS : out std_logic; MCB_UIDRPUPDATE : out std_logic; MCB_UIBROADCAST : out std_logic; MCB_UIADDR : out std_logic_vector(4 downto 0); MCB_UICMDEN : out std_logic; MCB_UIDONECAL : out std_logic; MCB_UIDQLOWERDEC : out std_logic; MCB_UIDQLOWERINC : out std_logic; MCB_UIDQUPPERDEC : out std_logic; MCB_UIDQUPPERINC : out std_logic; MCB_UILDQSDEC : out std_logic; MCB_UILDQSINC : out std_logic; MCB_UIREAD : out std_logic; MCB_UIUDQSDEC : out std_logic; MCB_UIUDQSINC : out std_logic; MCB_RECAL : out std_logic; MCB_SYSRST : out std_logic; MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; RZQ_PIN : inout std_logic; ZIO_PIN : inout std_logic; CKE_Train : out std_logic ); end entity mcb_soft_calibration_top; architecture trans of mcb_soft_calibration_top is component mcb_soft_calibration is generic ( C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY -- (Quarter, etc) C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented C_MEM_TYPE : string := "DDR" ); port ( UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB -- CLK pins RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB -- hard calib complete) PLL_LOCK : in std_logic; -- Lock signal from PLL SELFREFRESH_REQ : in std_logic; SELFREFRESH_MCB_MODE : in std_logic; SELFREFRESH_MCB_REQ : out std_logic; SELFREFRESH_MODE : out std_logic; IODRP_ADD : out std_logic; -- IODRP ADD port IODRP_SDI : out std_logic; -- IODRP SDI port RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port MCB_UIADD : out std_logic; -- to MCB's UIADD port MCB_UISDI : out std_logic; -- to MCB's UISDI port MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO) MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS) MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used -- during IODRP2_MCB writes). Currently just trasnparent MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port) MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state MCB_UIDQLOWERDEC : out std_logic := '0'; MCB_UIDQLOWERINC : out std_logic := '0'; MCB_UIDQUPPERDEC : out std_logic := '0'; MCB_UIDQUPPERINC : out std_logic := '0'; MCB_UILDQSDEC : out std_logic := '0'; MCB_UILDQSINC : out std_logic := '0'; MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in -- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care. MCB_UIUDQSDEC : out std_logic := '0'; MCB_UIUDQSINC : out std_logic := '0'; MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high MCB_UICMD : out std_logic; MCB_UICMDIN : out std_logic; MCB_UIDQCOUNT : out std_logic_vector(3 downto 0); MCB_UODATA : in std_logic_vector(7 downto 0); MCB_UODATAVALID : in std_logic; MCB_UOCMDREADY : in std_logic; MCB_UO_CAL_START : in std_logic; MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB Max_Value : out std_logic_vector(7 downto 0); CKE_Train : out std_logic ); end component; signal IODRP_ADD : std_logic; signal IODRP_SDI : std_logic; signal RZQ_IODRP_SDO : std_logic; signal RZQ_IODRP_CS : std_logic; signal ZIO_IODRP_SDO : std_logic; signal ZIO_IODRP_CS : std_logic; signal IODRP_SDO : std_logic; signal IODRP_CS : std_logic; signal IODRP_BKST : std_logic; signal RZQ_ZIO_ODATAIN : std_logic; signal RZQ_ZIO_TRISTATE : std_logic; signal RZQ_TOUT : std_logic; signal ZIO_TOUT : std_logic; signal Max_Value : std_logic_vector(7 downto 0); signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally signal RZQ_OUT : std_logic; signal ZIO_OUT : std_logic; -- Declare intermediate signals for referenced outputs signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic; signal MCB_UIADD_xilinx3 : std_logic; signal MCB_UISDI_xilinx17 : std_logic; signal MCB_UICS_xilinx7 : std_logic; signal MCB_UIDRPUPDATE_xilinx13 : std_logic; signal MCB_UIBROADCAST_xilinx5 : std_logic; signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0); signal MCB_UICMDEN_xilinx6 : std_logic; signal MCB_UIDONECAL_xilinx8 : std_logic; signal MCB_UIDQLOWERDEC_xilinx9 : std_logic; signal MCB_UIDQLOWERINC_xilinx10 : std_logic; signal MCB_UIDQUPPERDEC_xilinx11 : std_logic; signal MCB_UIDQUPPERINC_xilinx12 : std_logic; signal MCB_UILDQSDEC_xilinx14 : std_logic; signal MCB_UILDQSINC_xilinx15 : std_logic; signal MCB_UIREAD_xilinx16 : std_logic; signal MCB_UIUDQSDEC_xilinx18 : std_logic; signal MCB_UIUDQSINC_xilinx19 : std_logic; signal MCB_RECAL_xilinx1 : std_logic; signal MCB_SYSRST_xilinx2 : std_logic; begin -- Drive referenced outputs DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0; MCB_UIADD <= MCB_UIADD_xilinx3; MCB_UISDI <= MCB_UISDI_xilinx17; MCB_UICS <= MCB_UICS_xilinx7; MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13; MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5; MCB_UIADDR <= MCB_UIADDR_xilinx4; MCB_UICMDEN <= MCB_UICMDEN_xilinx6; MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8; MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9; MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10; MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11; MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12; MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14; MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15; MCB_UIREAD <= MCB_UIREAD_xilinx16; MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18; MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19; MCB_RECAL <= MCB_RECAL_xilinx1; MCB_SYSRST <= MCB_SYSRST_xilinx2; RZQ_ZIO_ODATAIN <= not(RST); RZQ_ZIO_TRISTATE <= not(RST); IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ mcb_soft_calibration_inst : mcb_soft_calibration generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT, C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL, SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL, SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM, C_SIMULATION => C_SIMULATION, C_MEM_TYPE => C_MEM_TYPE ) port map ( UI_CLK => UI_CLK, RST => RST, PLL_LOCK => PLL_LOCK, SELFREFRESH_REQ => SELFREFRESH_REQ, SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE, SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ, SELFREFRESH_MODE => SELFREFRESH_MODE, DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0, IODRP_ADD => IODRP_ADD, IODRP_SDI => IODRP_SDI, RZQ_IN => RZQ_IN_R2, RZQ_IODRP_SDO => RZQ_IODRP_SDO, RZQ_IODRP_CS => RZQ_IODRP_CS, ZIO_IN => ZIO_IN_R2, ZIO_IODRP_SDO => ZIO_IODRP_SDO, ZIO_IODRP_CS => ZIO_IODRP_CS, MCB_UIADD => MCB_UIADD_xilinx3, MCB_UISDI => MCB_UISDI_xilinx17, MCB_UOSDO => MCB_UOSDO, MCB_UODONECAL => MCB_UODONECAL, MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG, MCB_UICS => MCB_UICS_xilinx7, MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13, MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5, MCB_UIADDR => MCB_UIADDR_xilinx4, MCB_UICMDEN => MCB_UICMDEN_xilinx6, MCB_UIDONECAL => MCB_UIDONECAL_xilinx8, MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9, MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10, MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11, MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12, MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14, MCB_UILDQSINC => MCB_UILDQSINC_xilinx15, MCB_UIREAD => MCB_UIREAD_xilinx16, MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18, MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19, MCB_RECAL => MCB_RECAL_xilinx1, MCB_UICMD => MCB_UICMD, MCB_UICMDIN => MCB_UICMDIN, MCB_UIDQCOUNT => MCB_UIDQCOUNT, MCB_UODATA => MCB_UODATA, MCB_UODATAVALID => MCB_UODATAVALID, MCB_UOCMDREADY => MCB_UOCMDREADY, MCB_UO_CAL_START => MCB_UO_CAL_START, mcb_sysrst => MCB_SYSRST_xilinx2, Max_Value => Max_Value, CKE_Train => CKE_Train ); process(UI_CLK,RST) begin if (RST = '1') then ZIO_IN_R1 <= '0'; ZIO_IN_R2 <= '0'; RZQ_IN_R1 <= '0'; RZQ_IN_R2 <= '0'; elsif (UI_CLK'event and UI_CLK = '1') then ZIO_IN_R1 <= ZIO_IN; ZIO_IN_R2 <= ZIO_IN_R1; RZQ_IN_R1 <= RZQ_IN; RZQ_IN_R2 <= RZQ_IN_R1; end if; end process; IOBUF_RZQ : IOBUF port map ( o => RZQ_IN, io => RZQ_PIN, i => RZQ_OUT, t => RZQ_TOUT ); IODRP2_RZQ : IODRP2 port map ( dataout => open, dataout2 => open, dout => RZQ_OUT, sdo => RZQ_IODRP_SDO, tout => RZQ_TOUT, add => IODRP_ADD, bkst => IODRP_BKST, clk => UI_CLK, cs => RZQ_IODRP_CS, idatain => RZQ_IN, ioclk0 => IOCLK, ioclk1 => '1', odatain => RZQ_ZIO_ODATAIN, sdi => IODRP_SDI, t => RZQ_ZIO_TRISTATE ); gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and (SKIP_IN_TERM_CAL = 0)) generate IOBUF_ZIO : IOBUF port map ( o => ZIO_IN, io => ZIO_PIN, i => ZIO_OUT, t => ZIO_TOUT ); IODRP2_ZIO : IODRP2 port map ( dataout => open, dataout2 => open, dout => ZIO_OUT, sdo => ZIO_IODRP_SDO, tout => ZIO_TOUT, add => IODRP_ADD, bkst => IODRP_BKST, clk => UI_CLK, cs => ZIO_IODRP_CS, idatain => ZIO_IN, ioclk0 => IOCLK, ioclk1 => '1', odatain => RZQ_ZIO_ODATAIN, sdi => IODRP_SDI, t => RZQ_ZIO_TRISTATE ); end generate; end architecture trans;
gpl-3.0
392aad444be888ece8a137d81af1353d
0.543692
4.053614
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_axi_write_fsm.vhd
2
61,464
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block q/T1Iy/+MUBBlCcGvQX+JOyPTRTh6qcwsjx1LpKKWPOARQH0sAb+u6zC8Ncgi7zkjfu0yJJXVMqp Wf8VCd8vpA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block M1opFEihVmWFAXOD7Q1IGCTzwbpujUxRNCRmHNjJsd7UgyLrke3GKIzEVtt8eaET1PMOPoIm8fQD HZ/rjM3Mv7wmgvEtdC5XK9OI+dSBT3royWsH1IhbnRz++qahjWaXhqUO+4ofwzb3vG8UN5N7nRl/ 5XPAUPalGaYGAmnuI40= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Ud9YT2VeZwLBE8WkFwGik3aMFUpP+j5zsGS6qy3s+Ubw0O7OaB+MO0Q390XVW/u34cTYFBROKr9z PvuwUv1J9e5X11udCwfno9JZRym3I7oBp8uZL4T49g2XKaO6uf/IccE4x58v6mucFup5Cv9j9kY+ qN05VbKY0t04tWSDDP1ELf9+Twn0RpLNehcpdlIwVNUH77gv/LmoKsXicSOZ1CgEJ25GCvzwO4cw E1828nrMpOjUFdwDMxSeod8/ZkGIdVMJ9YUBro3GR/+mW+V6oV2bnCZ3dpPKlI4qIdSybuGTB90+ Af2649x6Ts9W6Dq3RyDc5183kwukGy1bf/oB1A== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cLcLLOLJTqARkcevlIPrmHxDlZTIawUClQ9tBmSXPARNTFiBw4hCE46as62gNM3JocZhJ2zzZxrG V1sfHt/1QQ2ErXgD7hfR6WScMk3jIDuVcI6FtnEVvWBH4Wp7KmXw1ilBNSVP4oZZlq1M6/13wJ73 jbtO3poVcS1IGPGp3So= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block CgZEXG6KWSO8i1V2TS7Ukwn/CzYGfShnbDog5GY2MAsh465RuYecO+AEILUIkQyS/NF427ttFnv8 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bsd-2-clause
79a3a553c9110b6cbfd44ce4ffb0746c
0.951646
1.826133
false
false
false
false
tdaede/daala_zynq
daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_status_flags_as.vhd
2
15,251
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block OsXabe8iQ0uCYAflbus8jqDzhNPlSFlh0WfiZSIXmJ5r1lUYhqZAYZGx2U3WoeEr3fztnrUzUNzI ypsYLeAbUA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ctC7yKWKUsfuMmq29AjIvbE5ykSf7vcCrupTGPQUOGVPoKDUJVYQA1Ie+EF9czCQbqTPR9s+6XBO seTBx1Uj9YcyZOqjn8xvKaR01fuDdVstRRHtc84YfnizVarAg/oN53vSRDa5/D+uKQZ86H9Jm47k 8DqxArx1CfRLaIZLgsg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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bsd-2-clause
2460fae04316af891a48c6e7a6fdd215
0.937053
1.874048
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/component/rule_019_test_input.vhd
1
903
architecture RTl of FIFO is component fifo is generic ( gen_dec1 : integer := 0; -- Comment -- Keep Comment gen_dec2 : integer := 1; -- Comment gen_dec3 : integer := 2 -- Comment ); port ( sig1 : std_logic; -- Comment -- Keep Comment sig2 : std_logic; -- Comment sig3 : std_logic -- Comment -- Keep Comment ); end component fifo; -- Failures below component fifo is generic ( gen_dec1 : integer := 0;-- Comment -- Keep Comment gen_dec2 : integer := 1; gen_dec3 : integer := 2-- Comment -- Keep Comment ); port ( -- Keep Comment sig1 : std_logic; -- Comment -- Keep Comment sig2 : std_logic; -- Comment -- Keep Comment sig3 : std_logic -- Comment -- Keep Comment ); end component fifo; begin end architecture RTL;
gpl-3.0
b7f359f5f18de7af3aec5750b34fa673
0.532669
3.926087
false
false
false
false
Yarr/Yarr-fw
rtl/spartan6/gn4124-core/spartan6/p2l_des.vhd
2
9,650
-------------------------------------------------------------------------------- -- -- -- CERN BE-CO-HT GN4124 core for PCIe FMC carrier -- -- http://www.ohwr.org/projects/gn4124-core -- -------------------------------------------------------------------------------- -- -- unit name: P2L deserializer (p2l_des_s6.vhd) -- -- authors: Simon Deprez ([email protected]) -- Matthieu Cattin ([email protected]) -- -- date: 31-08-2010 -- -- version: 1.0 -- -- description: Takes the DDR P2L bus and converts to SDR that is synchronous -- to the core clock. Spartan6 FPGAs version. -- -- dependencies: -- -------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE -------------------------------------------------------------------------------- -- This source file is free software; you can redistribute it and/or modify it -- under the terms of the GNU Lesser General Public License as published by the -- Free Software Foundation; either version 2.1 of the License, or (at your -- option) any later version. This source is distributed in the hope that it -- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty -- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -- See the GNU Lesser General Public License for more details. You should have -- received a copy of the GNU Lesser General Public License along with this -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html -------------------------------------------------------------------------------- -- last changes: 23-09-2010 (mcattin) Always active high reset for FFs. -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.gn4124_core_pkg.all; library UNISIM; use UNISIM.vcomponents.all; entity p2l_des is port ( --------------------------------------------------------- -- Reset and clock rst_n_i : in std_logic; sys_clk_i : in std_logic; io_clk_i : in std_logic; serdes_strobe_i : in std_logic; --------------------------------------------------------- -- P2L clock domain (DDR) -- -- P2L inputs p2l_valid_i : in std_logic; p2l_dframe_i : in std_logic; p2l_data_i : in std_logic_vector(15 downto 0); --------------------------------------------------------- -- Core clock domain (SDR) -- -- Deserialized output p2l_valid_o : out std_logic; p2l_dframe_o : out std_logic; p2l_data_o : out std_logic_vector(31 downto 0) ); end p2l_des; architecture rtl of p2l_des is ----------------------------------------------------------------------------- -- Components declaration ----------------------------------------------------------------------------- component serdes_1_to_n_data_s2_se generic ( USE_PD : boolean := false; -- Parameter to set generation of phase detector logic S : integer := 2; -- Parameter to set the serdes factor 1..8 D : integer := 16) ; -- Set the number of inputs and outputs port ( use_phase_detector : in std_logic; -- Set generation of phase detector logic datain : in std_logic_vector(D-1 downto 0); -- Input from se receiver pin rxioclk : in std_logic; -- IO Clock network rxserdesstrobe : in std_logic; -- Parallel data capture strobe reset : in std_logic; -- Reset line gclk : in std_logic; -- Global clock bitslip : in std_logic; -- Bitslip control line debug_in : in std_logic_vector(1 downto 0); -- input debug data data_out : out std_logic_vector((D*S)-1 downto 0); -- Output data -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required debug : out std_logic_vector((2*D)+6 downto 0)) ; end component serdes_1_to_n_data_s2_se; ----------------------------------------------------------------------------- -- Comnstants declaration ----------------------------------------------------------------------------- constant S : integer := 2; -- Set the serdes factor to 2 constant D : integer := 16; -- Set the number of inputs and outputs ----------------------------------------------------------------------------- -- Signals declaration ----------------------------------------------------------------------------- -- Serdes reset signal rst : std_logic; -- SDR signals signal p2l_valid_v : std_logic_vector(0 downto 0); signal p2l_dframe_v : std_logic_vector(0 downto 0); signal p2l_valid_t : std_logic_vector(1 downto 0); signal p2l_dframe_t : std_logic_vector(1 downto 0); signal p2l_data_t : std_logic_vector(p2l_data_o'range); signal p2l_valid_t2 : std_logic; signal p2l_dframe_t2 : std_logic; signal p2l_data_t2 : std_logic_vector(p2l_data_o'range); signal p2l_data_bitslip : std_logic_vector(1 downto 0); signal p2l_data_bitslip_p : std_logic; --signal p2l_ctrl_v : std_logic_vector(1 downto 0); --signal p2l_ctrl_t : std_logic_vector(3 downto 0); begin ------------------------------------------------------------------------------ -- Active high reset ------------------------------------------------------------------------------ gen_rst_n : if c_RST_ACTIVE = '0' generate rst <= not(rst_n_i); end generate; gen_rst : if c_RST_ACTIVE = '1' generate rst <= rst_n_i; end generate; ------------------------------------------------------------------------------ -- data input bit slip ------------------------------------------------------------------------------ p_din_bitslip : process (sys_clk_i, rst_n_i) begin if rst_n_i = c_RST_ACTIVE then p2l_data_bitslip <= (others => '0'); elsif rising_edge(sys_clk_i) then p2l_data_bitslip <= p2l_data_bitslip(0) & '1'; end if; end process p_din_bitslip; p2l_data_bitslip_p <= p2l_data_bitslip(0) and not(p2l_data_bitslip(1)); ------------------------------------------------------------------------------ -- data inputs ------------------------------------------------------------------------------ cmp_data_in : serdes_1_to_n_data_s2_se generic map( USE_PD => false, S => S, D => D) port map ( use_phase_detector => '0', -- '1' enables the phase detector logic datain => p2l_data_i, rxioclk => io_clk_i, rxserdesstrobe => serdes_strobe_i, gclk => sys_clk_i, bitslip => '0', --p2l_data_bitslip_p, reset => rst, data_out => p2l_data_t, debug_in => "00", debug => open); ------------------------------------------------------------------------------ -- dframe input ------------------------------------------------------------------------------ cmp_dframe_in : serdes_1_to_n_data_s2_se generic map( USE_PD => false, S => S, D => 1) port map ( use_phase_detector => '0', -- '1' enables the phase detector logic datain => p2l_dframe_v, rxioclk => io_clk_i, rxserdesstrobe => serdes_strobe_i, gclk => sys_clk_i, bitslip => '0', reset => rst, data_out => p2l_dframe_t, debug_in => "00", debug => open); -- Type conversion, std_logic to std_logic_vector p2l_dframe_v(0) <= p2l_dframe_i; ------------------------------------------------------------------------------ -- valid input ------------------------------------------------------------------------------ cmp_valid_in : serdes_1_to_n_data_s2_se generic map( USE_PD => false, S => S, D => 1) port map ( use_phase_detector => '0', -- '1' enables the phase detector logic datain => p2l_valid_v, rxioclk => io_clk_i, rxserdesstrobe => serdes_strobe_i, gclk => sys_clk_i, bitslip => '0', reset => rst, data_out => p2l_valid_t, debug_in => "00", debug => open); -- Type conversion, std_logic to std_logic_vector p2l_valid_v(0) <= p2l_valid_i; p_in_sys_sync : process (sys_clk_i, rst_n_i) begin if rst_n_i = c_RST_ACTIVE then p2l_data_o <= (others => '0'); p2l_dframe_o <= '0'; p2l_valid_o <= '0'; p2l_data_t2 <= (others => '0'); p2l_dframe_t2 <= '0'; p2l_valid_t2 <= '0'; elsif rising_edge(sys_clk_i) then p2l_data_t2 <= p2l_data_t; p2l_dframe_t2 <= p2l_dframe_t(0); p2l_valid_t2 <= p2l_valid_t(0); p2l_data_o <= p2l_data_t2; p2l_dframe_o <= p2l_dframe_t2; p2l_valid_o <= p2l_valid_t2; end if; end process p_in_sys_sync; end rtl;
gpl-3.0
9a762d4149c0e754e3db255c1c89baa3
0.426321
4.139854
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/if_statement/rule_009_test_input.vhd
1
838
architecture RTL of FIFO is begin process begin if (a = '1' or b = '0' and c = '1' xor d = '1' and g = x) then b <= '0'; elsif (a = '1' or b = '0' and c = '1' xor d = '1' and g = x) then b <= '1'; else b <= '1'; end if; -- Violations below if (a = '1' or b = '0' and c = '1' xor d = '1' and g = x) then b <= '0'; elsif (a = '1' or b = '0' and c = '1' xor d = '1' and g = x) then b <= '1'; else b <= '1'; end if; if a = 1 then b <= 1; elsif b = 1 then c <= 2; end if; end process; -- Check comments in if statements process begin if (a = 1 and -- Comment b = 0) then b <= '1'; end if; end process; end architecture RTL;
gpl-3.0
84639404a09d0071fd76d18db423b210
0.394988
2.992857
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/if_statement/rule_034_test_input.fixed_upper.vhd
1
566
architecture RTL of FIFO is begin process begin if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; else if x = '1' then z <= '0'; elsif x = '0' then z <= '1'; else z <= 'Z'; end IF; end IF; -- Violations below if a = '1' then b <= '0'; elsif c = '1' then b <= '1'; else if x = '1' then z <= '0'; elsif x = '0' then z <= '1'; else z <= 'Z'; end IF; end IF; end process; end architecture RTL;
gpl-3.0
2f1e253cb0db376f71839777a7b13fbc
0.379859
3.19774
false
false
false
false
Yarr/Yarr-fw
rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/memc3_tb_top.vhd
4
29,610
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.9 -- \ \ Application : MIG -- / / Filename : memc3_tb_top.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- --Device : Spartan-6 --Design Name : DDR/DDR2/DDR3/LPDDR --Purpose : This is top level module for test bench. which instantiates -- init_mem_pattern_ctr and mcb_traffic_gen modules for each user -- port. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity memc3_tb_top is generic ( C_P0_MASK_SIZE : integer := 4; C_P0_DATA_PORT_SIZE : integer := 32; C_P1_MASK_SIZE : integer := 4; C_P1_DATA_PORT_SIZE : integer := 32; C_MEM_BURST_LEN : integer := 8; C_SIMULATION : string := "FALSE"; C_MEM_NUM_COL_BITS : integer := 11; C_NUM_DQ_PINS : integer := 8; C_SMALL_DEVICE : string := "FALSE"; C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000200"; C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010"; C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000003ff"; C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800"; C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000200"; C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000400"; C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010"; C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000005ff"; C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000"; C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000400" ); port ( clk0 : in std_logic; rst0 : in std_logic; calib_done : in std_logic; p0_mcb_cmd_en_o : out std_logic; p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0); p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0); p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0); p0_mcb_cmd_full_i : in std_logic; p0_mcb_wr_en_o : out std_logic; p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0); p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); p0_mcb_wr_full_i : in std_logic; p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0); p0_mcb_rd_en_o : out std_logic; p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); p0_mcb_rd_empty_i : in std_logic; p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0); p1_mcb_cmd_en_o : out std_logic; p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0); p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0); p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0); p1_mcb_cmd_full_i : in std_logic; p1_mcb_wr_en_o : out std_logic; p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0); p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); p1_mcb_wr_full_i : in std_logic; p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0); p1_mcb_rd_en_o : out std_logic; p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); p1_mcb_rd_empty_i : in std_logic; p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0); vio_modify_enable : in std_logic; vio_data_mode_value : in std_logic_vector(2 downto 0); vio_addr_mode_value : in std_logic_vector(2 downto 0); cmp_error : out std_logic; cmp_data : out std_logic_vector(31 downto 0); cmp_data_valid : out std_logic; error : out std_logic; error_status : out std_logic_vector(191 downto 0) ); end memc3_tb_top; architecture arc of memc3_tb_top is function ERROR_DQWIDTH (val_i : integer) return integer is begin if (val_i = 4) then return 1; else return val_i/8; end if; end function ERROR_DQWIDTH; constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS); component init_mem_pattern_ctr IS generic ( FAMILY : string; BEGIN_ADDRESS : std_logic_vector(31 downto 0); END_ADDRESS : std_logic_vector(31 downto 0); DWIDTH : integer; CMD_SEED_VALUE : std_logic_vector(31 downto 0); DATA_SEED_VALUE : std_logic_vector(31 downto 0); DATA_MODE : std_logic_vector(3 downto 0); PORT_MODE : string ); PORT ( clk_i : in std_logic; rst_i : in std_logic; mcb_cmd_bl_i : in std_logic_vector(5 downto 0); mcb_cmd_en_i : in std_logic; mcb_cmd_instr_i : in std_logic_vector(2 downto 0); mcb_init_done_i : in std_logic; mcb_wr_en_i : in std_logic; vio_modify_enable : in std_logic; vio_data_mode_value : in std_logic_vector(2 downto 0); vio_addr_mode_value : in std_logic_vector(2 downto 0); vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0); vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0); cmp_error : in std_logic; run_traffic_o : out std_logic; start_addr_o : out std_logic_vector(31 downto 0); end_addr_o : out std_logic_vector(31 downto 0); cmd_seed_o : out std_logic_vector(31 downto 0); data_seed_o : out std_logic_vector(31 downto 0); load_seed_o : out std_logic; addr_mode_o : out std_logic_vector(2 downto 0); instr_mode_o : out std_logic_vector(3 downto 0); bl_mode_o : out std_logic_vector(1 downto 0); data_mode_o : out std_logic_vector(3 downto 0); mode_load_o : out std_logic; fixed_bl_o : out std_logic_vector(5 downto 0); fixed_instr_o : out std_logic_vector(2 downto 0); fixed_addr_o : out std_logic_vector(31 downto 0) ); end component; component mcb_traffic_gen is generic ( FAMILY : string; SIMULATION : string; MEM_BURST_LEN : integer; PORT_MODE : string; DATA_PATTERN : string; CMD_PATTERN : string; ADDR_WIDTH : integer; CMP_DATA_PIPE_STAGES : integer; MEM_COL_WIDTH : integer; NUM_DQ_PINS : integer; DQ_ERROR_WIDTH : integer; DWIDTH : integer; PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0); PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0); PRBS_EADDR : std_logic_vector(31 downto 0); PRBS_SADDR : std_logic_vector(31 downto 0) ); port ( clk_i : in std_logic; rst_i : in std_logic; run_traffic_i : in std_logic; manual_clear_error : in std_logic; -- *** runtime parameter *** start_addr_i : in std_logic_vector(31 downto 0); end_addr_i : in std_logic_vector(31 downto 0); cmd_seed_i : in std_logic_vector(31 downto 0); data_seed_i : in std_logic_vector(31 downto 0); load_seed_i : in std_logic; addr_mode_i : in std_logic_vector(2 downto 0); instr_mode_i : in std_logic_vector(3 downto 0); bl_mode_i : in std_logic_vector(1 downto 0); data_mode_i : in std_logic_vector(3 downto 0); mode_load_i : in std_logic; -- fixed pattern inputs interface fixed_bl_i : in std_logic_vector(5 downto 0); fixed_instr_i : in std_logic_vector(2 downto 0); fixed_addr_i : in std_logic_vector(31 downto 0); fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0); bram_cmd_i : in std_logic_vector(38 downto 0); bram_valid_i : in std_logic; bram_rdy_o : out std_logic; --/////////////////////////////////////////////////////////////////////////// -- MCB INTERFACE -- interface to mcb command port mcb_cmd_en_o : out std_logic; mcb_cmd_instr_o : out std_logic_vector(2 downto 0); mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0); mcb_cmd_bl_o : out std_logic_vector(5 downto 0); mcb_cmd_full_i : in std_logic; -- interface to mcb wr data port mcb_wr_en_o : out std_logic; mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0); mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0); mcb_wr_data_end_o : OUT std_logic; mcb_wr_full_i : in std_logic; mcb_wr_fifo_counts : in std_logic_vector(6 downto 0); -- interface to mcb rd data port mcb_rd_en_o : out std_logic; mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0); mcb_rd_empty_i : in std_logic; mcb_rd_fifo_counts : in std_logic_vector(6 downto 0); --/////////////////////////////////////////////////////////////////////////// -- status feedback counts_rst : in std_logic; wr_data_counts : out std_logic_vector(47 downto 0); rd_data_counts : out std_logic_vector(47 downto 0); cmp_data : out std_logic_vector(DWIDTH - 1 downto 0); cmp_data_valid : out std_logic; cmp_error : out std_logic; error : out std_logic; error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0); mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0); dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0); cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0) ); end component; -- Function to determine the number of data patterns to be generated function DATA_PATTERN_CALC return string is begin if (C_SMALL_DEVICE = "FALSE") then return "DGEN_ALL"; else return "DGEN_ADDR"; end if; end function; constant FAMILY : string := "SPARTAN6"; constant DATA_PATTERN : string := DATA_PATTERN_CALC; constant CMD_PATTERN : string := "CGEN_ALL"; constant ADDR_WIDTH : integer := 30; constant CMP_DATA_PIPE_STAGES : integer := 0; constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000"; constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000"; constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000"; constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff"; constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000"; constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff"; constant DATA_MODE : std_logic_vector(3 downto 0) := "0010"; constant p0_DWIDTH : integer := 64; constant p1_DWIDTH : integer := 32; constant p0_PORT_MODE : string := "BI_MODE"; constant p1_PORT_MODE : string := "BI_MODE"; --p0 Signal declarations signal p0_tg_run_traffic : std_logic; signal p0_tg_start_addr : std_logic_vector(31 downto 0); signal p0_tg_end_addr : std_logic_vector(31 downto 0); signal p0_tg_cmd_seed : std_logic_vector(31 downto 0); signal p0_tg_data_seed : std_logic_vector(31 downto 0); signal p0_tg_load_seed : std_logic; signal p0_tg_addr_mode : std_logic_vector(2 downto 0); signal p0_tg_instr_mode : std_logic_vector(3 downto 0); signal p0_tg_bl_mode : std_logic_vector(1 downto 0); signal p0_tg_data_mode : std_logic_vector(3 downto 0); signal p0_tg_mode_load : std_logic; signal p0_tg_fixed_bl : std_logic_vector(5 downto 0); signal p0_tg_fixed_instr : std_logic_vector(2 downto 0); signal p0_tg_fixed_addr : std_logic_vector(31 downto 0); signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0); signal p0_error : std_logic; signal p0_cmp_error : std_logic; signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0); signal p0_cmp_data_valid : std_logic; signal p0_mcb_cmd_en_o_int : std_logic; signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0); signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0); signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0); signal p0_mcb_wr_en_o_int : std_logic; --p1 Signal declarations signal p1_tg_run_traffic : std_logic; signal p1_tg_start_addr : std_logic_vector(31 downto 0); signal p1_tg_end_addr : std_logic_vector(31 downto 0); signal p1_tg_cmd_seed : std_logic_vector(31 downto 0); signal p1_tg_data_seed : std_logic_vector(31 downto 0); signal p1_tg_load_seed : std_logic; signal p1_tg_addr_mode : std_logic_vector(2 downto 0); signal p1_tg_instr_mode : std_logic_vector(3 downto 0); signal p1_tg_bl_mode : std_logic_vector(1 downto 0); signal p1_tg_data_mode : std_logic_vector(3 downto 0); signal p1_tg_mode_load : std_logic; signal p1_tg_fixed_bl : std_logic_vector(5 downto 0); signal p1_tg_fixed_instr : std_logic_vector(2 downto 0); signal p1_tg_fixed_addr : std_logic_vector(31 downto 0); signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0); signal p1_error : std_logic; signal p1_cmp_error : std_logic; signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0); signal p1_cmp_data_valid : std_logic; signal p1_mcb_cmd_en_o_int : std_logic; signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0); signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0); signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0); signal p1_mcb_wr_en_o_int : std_logic; --signal cmp_data : std_logic_vector(31 downto 0); begin cmp_error <= p0_cmp_error or p1_cmp_error; error <= p0_error or p1_error; error_status <= p0_error_status; cmp_data <= p0_cmp_data(31 downto 0); cmp_data_valid <= p0_cmp_data_valid; p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int; p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int; p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int; p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int; p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int; init_mem_pattern_ctr_p0 :init_mem_pattern_ctr generic map ( DWIDTH => p0_DWIDTH, FAMILY => FAMILY, BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS, END_ADDRESS => C_p0_END_ADDRESS, CMD_SEED_VALUE => X"56456783", DATA_SEED_VALUE => X"12345678", DATA_MODE => C_p0_DATA_MODE, PORT_MODE => p0_PORT_MODE ) port map ( clk_i => clk0, rst_i => rst0, mcb_cmd_en_i => p0_mcb_cmd_en_o_int, mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int, mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int, mcb_wr_en_i => p0_mcb_wr_en_o_int, vio_modify_enable => vio_modify_enable, vio_data_mode_value => vio_data_mode_value, vio_addr_mode_value => vio_addr_mode_value, vio_bl_mode_value => "10",--vio_bl_mode_value, vio_fixed_bl_value => "000000",--vio_fixed_bl_value, mcb_init_done_i => calib_done, cmp_error => p0_error, run_traffic_o => p0_tg_run_traffic, start_addr_o => p0_tg_start_addr, end_addr_o => p0_tg_end_addr , cmd_seed_o => p0_tg_cmd_seed , data_seed_o => p0_tg_data_seed , load_seed_o => p0_tg_load_seed , addr_mode_o => p0_tg_addr_mode , instr_mode_o => p0_tg_instr_mode , bl_mode_o => p0_tg_bl_mode , data_mode_o => p0_tg_data_mode , mode_load_o => p0_tg_mode_load , fixed_bl_o => p0_tg_fixed_bl , fixed_instr_o => p0_tg_fixed_instr, fixed_addr_o => p0_tg_fixed_addr ); m_traffic_gen_p0 : mcb_traffic_gen generic map( MEM_BURST_LEN => C_MEM_BURST_LEN, MEM_COL_WIDTH => C_MEM_NUM_COL_BITS, NUM_DQ_PINS => C_NUM_DQ_PINS, DQ_ERROR_WIDTH => DQ_ERROR_WIDTH, PORT_MODE => p0_PORT_MODE, DWIDTH => p0_DWIDTH, CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES, FAMILY => FAMILY, SIMULATION => "FALSE", DATA_PATTERN => DATA_PATTERN, CMD_PATTERN => "CGEN_ALL", ADDR_WIDTH => 30, PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS, PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS, PRBS_SADDR => C_p0_BEGIN_ADDRESS, PRBS_EADDR => C_p0_END_ADDRESS ) port map ( clk_i => clk0, rst_i => rst0, run_traffic_i => p0_tg_run_traffic, manual_clear_error => rst0, -- runtime parameter start_addr_i => p0_tg_start_addr , end_addr_i => p0_tg_end_addr , cmd_seed_i => p0_tg_cmd_seed , data_seed_i => p0_tg_data_seed , load_seed_i => p0_tg_load_seed, addr_mode_i => p0_tg_addr_mode, instr_mode_i => p0_tg_instr_mode , bl_mode_i => p0_tg_bl_mode , data_mode_i => p0_tg_data_mode , mode_load_i => p0_tg_mode_load , -- fixed pattern inputs interface fixed_bl_i => p0_tg_fixed_bl, fixed_instr_i => p0_tg_fixed_instr, fixed_addr_i => p0_tg_fixed_addr, fixed_data_i => (others => '0'), -- BRAM interface. bram_cmd_i => (others => '0'), bram_valid_i => '0', bram_rdy_o => open, -- MCB INTERFACE mcb_cmd_en_o => p0_mcb_cmd_en_o_int, mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int, mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int, mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int, mcb_cmd_full_i => p0_mcb_cmd_full_i, mcb_wr_en_o => p0_mcb_wr_en_o_int, mcb_wr_mask_o => p0_mcb_wr_mask_o, mcb_wr_data_o => p0_mcb_wr_data_o, mcb_wr_data_end_o => open, mcb_wr_full_i => p0_mcb_wr_full_i, mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts, mcb_rd_en_o => p0_mcb_rd_en_o, mcb_rd_data_i => p0_mcb_rd_data_i, mcb_rd_empty_i => p0_mcb_rd_empty_i, mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts, -- status feedback counts_rst => rst0, wr_data_counts => open, rd_data_counts => open, cmp_data => p0_cmp_data, cmp_data_valid => p0_cmp_data_valid, cmp_error => p0_cmp_error, error => p0_error, error_status => p0_error_status, mem_rd_data => open, dq_error_bytelane_cmp => open, cumlative_dq_lane_error => open ); p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int; p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int; p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int; p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int; p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int; init_mem_pattern_ctr_p1 :init_mem_pattern_ctr generic map ( DWIDTH => p1_DWIDTH, FAMILY => FAMILY, BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS, END_ADDRESS => C_p1_END_ADDRESS, CMD_SEED_VALUE => X"56456783", DATA_SEED_VALUE => X"12345678", DATA_MODE => C_p1_DATA_MODE, PORT_MODE => p1_PORT_MODE ) port map ( clk_i => clk0, rst_i => rst0, mcb_cmd_en_i => p1_mcb_cmd_en_o_int, mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int, mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int, mcb_wr_en_i => p1_mcb_wr_en_o_int, vio_modify_enable => vio_modify_enable, vio_data_mode_value => vio_data_mode_value, vio_addr_mode_value => vio_addr_mode_value, vio_bl_mode_value => "10",--vio_bl_mode_value, vio_fixed_bl_value => "000000",--vio_fixed_bl_value, mcb_init_done_i => calib_done, cmp_error => p1_error, run_traffic_o => p1_tg_run_traffic, start_addr_o => p1_tg_start_addr, end_addr_o => p1_tg_end_addr , cmd_seed_o => p1_tg_cmd_seed , data_seed_o => p1_tg_data_seed , load_seed_o => p1_tg_load_seed , addr_mode_o => p1_tg_addr_mode , instr_mode_o => p1_tg_instr_mode , bl_mode_o => p1_tg_bl_mode , data_mode_o => p1_tg_data_mode , mode_load_o => p1_tg_mode_load , fixed_bl_o => p1_tg_fixed_bl , fixed_instr_o => p1_tg_fixed_instr, fixed_addr_o => p1_tg_fixed_addr ); m_traffic_gen_p1 : mcb_traffic_gen generic map( MEM_BURST_LEN => C_MEM_BURST_LEN, MEM_COL_WIDTH => C_MEM_NUM_COL_BITS, NUM_DQ_PINS => C_NUM_DQ_PINS, DQ_ERROR_WIDTH => DQ_ERROR_WIDTH, PORT_MODE => p1_PORT_MODE, DWIDTH => p1_DWIDTH, CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES, FAMILY => FAMILY, SIMULATION => "FALSE", DATA_PATTERN => DATA_PATTERN, CMD_PATTERN => "CGEN_ALL", ADDR_WIDTH => 30, PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS, PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS, PRBS_SADDR => C_p1_BEGIN_ADDRESS, PRBS_EADDR => C_p1_END_ADDRESS ) port map ( clk_i => clk0, rst_i => rst0, run_traffic_i => p1_tg_run_traffic, manual_clear_error => rst0, -- runtime parameter start_addr_i => p1_tg_start_addr , end_addr_i => p1_tg_end_addr , cmd_seed_i => p1_tg_cmd_seed , data_seed_i => p1_tg_data_seed , load_seed_i => p1_tg_load_seed, addr_mode_i => p1_tg_addr_mode, instr_mode_i => p1_tg_instr_mode , bl_mode_i => p1_tg_bl_mode , data_mode_i => p1_tg_data_mode , mode_load_i => p1_tg_mode_load , -- fixed pattern inputs interface fixed_bl_i => p1_tg_fixed_bl, fixed_instr_i => p1_tg_fixed_instr, fixed_addr_i => p1_tg_fixed_addr, fixed_data_i => (others => '0'), -- BRAM interface. bram_cmd_i => (others => '0'), bram_valid_i => '0', bram_rdy_o => open, -- MCB INTERFACE mcb_cmd_en_o => p1_mcb_cmd_en_o_int, mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int, mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int, mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int, mcb_cmd_full_i => p1_mcb_cmd_full_i, mcb_wr_en_o => p1_mcb_wr_en_o_int, mcb_wr_mask_o => p1_mcb_wr_mask_o, mcb_wr_data_o => p1_mcb_wr_data_o, mcb_wr_data_end_o => open, mcb_wr_full_i => p1_mcb_wr_full_i, mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts, mcb_rd_en_o => p1_mcb_rd_en_o, mcb_rd_data_i => p1_mcb_rd_data_i, mcb_rd_empty_i => p1_mcb_rd_empty_i, mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts, -- status feedback counts_rst => rst0, wr_data_counts => open, rd_data_counts => open, cmp_data => p1_cmp_data, cmp_data_valid => p1_cmp_data_valid, cmp_error => p1_cmp_error, error => p1_error, error_status => p1_error_status, mem_rd_data => open, dq_error_bytelane_cmp => open, cumlative_dq_lane_error => open ); end architecture;
gpl-3.0
0cbc916c108d30a7ccc4e2647e858af8
0.497129
3.30801
false
false
false
false
okaxaki/vm2413
OutputMemory.vhd
2
1,250
-- -- OutputMemory.vhd -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use WORK.VM2413.ALL; entity OutputMemory is port ( clk : in std_logic; reset : in std_logic; wr : in std_logic; addr : in SLOT_TYPE; wdata : in SIGNED_LI_TYPE; rdata : out SIGNED_LI_TYPE; addr2 : in SLOT_TYPE; rdata2 : out SIGNED_LI_TYPE ); end OutputMemory; architecture RTL of OutputMemory is type SIGNED_LI_ARRAY_TYPE is array (0 to MAXSLOT) of SIGNED_LI_VECTOR_TYPE; signal data_array : SIGNED_LI_ARRAY_TYPE; begin process(clk, reset) variable init_ch : integer range 0 to MAXSLOT; begin if (reset = '1') then init_ch := 0; elsif clk'event and clk='1' then if init_ch /= MAXSLOT then data_array(init_ch) <= (others=>'0'); init_ch := init_ch + 1; elsif wr='1' then data_array(addr) <= CONV_SIGNED_LI_VECTOR(wdata); end if; rdata <= CONV_SIGNED_LI(data_array(addr)); rdata2 <= CONV_SIGNED_LI(data_array(addr2)); end if; end process; end RTL;
mit
0c09986bd211e2dd5d79c24749eca2cc
0.5384
3.472222
false
false
false
false
siavooshpayandehazad/TTU_CPU_Project
pico_CPU_pipelined_MIPS32/Memory.vhd
1
4,192
--Copyright (C) 2017 Siavoosh Payandeh Azad -- this is a dual port memory with 1 clock cycle delay -- ___ ___ ___ ___ ___ --CLK ____| |____| |____| |____| |____| |___ -- ____ _________ ________________________________ --ADDR ____X_ADDRESS_X________________________________ -- _____________ _________________________________ --DOUT _____________X___DATA OUT______________________ -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.all; use work.pico_cpu.all; use ieee.std_logic_textio.all; use std.textio.all; entity RAM is generic (BitWidth: integer; preload_file: string :="code.txt"); port ( RdAddress_1: in std_logic_vector (BitWidth-1 downto 0); RdAddress_2: in std_logic_vector (BitWidth-1 downto 0); Data_in: in std_logic_vector (BitWidth-1 downto 0); WrtAddress: in std_logic_vector (BitWidth-1 downto 0); clk: in std_logic; RW: in std_logic_vector(3 downto 0); rst: in std_logic; Data_Out_1: out std_logic_vector (BitWidth-1 downto 0); Data_Out_2: out std_logic_vector (BitWidth-1 downto 0) ); end RAM; architecture beh of RAM is type Mem_type is array (0 to DataMem_depth-1) of std_logic_vector(BitWidth-1 downto 0) ; signal Mem : Mem_type := ((others=> (others=>'0'))); signal write_enable : std_logic; begin write_enable <= RW(0) or RW(1) or RW(2) or RW(3); ------------------------------------------------------------------------------------------------- MemProcess: process(clk,rst) is file preloadfile : text open read_mode is preload_file; variable address : integer := 0; variable line_read : line; variable line_data : std_logic_vector(31 downto 0); begin if rst = '1' then -- reading from file and load the momory -- remove the following lines for syntehsis address := 0; while not endfile(preloadfile) loop readline(preloadfile, line_read); hread(line_read, line_data); Mem(address) <= line_data; address := address + 1; end loop; -- For synthesis replace the above block with the following: --Mem<= ((others=> (others=>'0'))); elsif rising_edge(clk) then if write_enable = '1' then if to_integer(unsigned(WrtAddress(BitWidth-1 downto 0))) <= DataMem_depth-1 then if RW(0) = '1' then Mem(to_integer(unsigned(WrtAddress(BitWidth-1 downto 0))))(7 downto 0) <= Data_in(7 downto 0); end if; if RW(1) = '1' then Mem(to_integer(unsigned(WrtAddress(BitWidth-1 downto 0))))(15 downto 8) <= Data_in(15 downto 8); end if; if RW(2) = '1' then Mem(to_integer(unsigned(WrtAddress(BitWidth-1 downto 0))))(23 downto 16) <= Data_in(23 downto 16); end if; if RW(3) = '1' then Mem(to_integer(unsigned(WrtAddress(BitWidth-1 downto 0))))(31 downto 24) <= Data_in(31 downto 24); end if; end if; end if; end if; end process; ------------------------------------------------------------------------------------------------- DATA_OUT_1_SEL:process(RdAddress_1,clk)begin if rising_edge(clk) then -- here we check if the address is in the momory could be removed if the memory depth is -- fixed if to_integer(unsigned(RdAddress_1(BitWidth-1 downto 0))) <= DataMem_depth-1 then Data_Out_1 <= Mem(to_integer(unsigned(RdAddress_1(BitWidth-1 downto 0)))); else Data_Out_1 <= (others=> '0'); end if; end if; end process; ------------------------------------------------------------------------------------------------- DATA_OUT_2_SEL:process(RdAddress_2,clk)begin if rising_edge(clk) then -- here we check if the address is in the momory could be removed if the memory depth is -- fixed if to_integer(unsigned(RdAddress_2(BitWidth-1 downto 0))) <= DataMem_depth-1 then Data_Out_2 <= Mem(to_integer(unsigned(RdAddress_2(BitWidth-1 downto 0)))); else Data_Out_2 <= (others=> '0'); end if; end if; end process; end beh;
gpl-2.0
b6355b4ceb7a283dc136cd172eb8352b
0.528626
3.817851
false
false
false
false
Yarr/Yarr-fw
rtl/common/k_dual_bram.vhd
1
23,984
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 07/11/2017 11:39:54 AM -- Design Name: -- Module Name: k_dual_bram - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; Library UNISIM; use UNISIM.vcomponents.all; Library UNIMACRO; use UNIMACRO.vcomponents.all; entity k_dual_bram is Port ( -- SYS CON clk_i : in std_logic; rst_i : in std_logic; -- Wishbone Slave in wba_adr_i : in std_logic_vector(32-1 downto 0); wba_dat_i : in std_logic_vector(64-1 downto 0); wba_we_i : in std_logic; wba_stb_i : in std_logic; wba_cyc_i : in std_logic; -- Wishbone Slave out wba_dat_o : out std_logic_vector(64-1 downto 0); wba_ack_o : out std_logic; -- Wishbone Slave in wbb_adr_i : in std_logic_vector(32-1 downto 0); wbb_dat_i : in std_logic_vector(64-1 downto 0); wbb_we_i : in std_logic; wbb_stb_i : in std_logic; wbb_cyc_i : in std_logic; -- Wishbone Slave out wbb_dat_o : out std_logic_vector(64-1 downto 0); wbb_ack_o : out std_logic ); end k_dual_bram; architecture Behavioral of k_dual_bram is constant BLOCK_ADDR_WIDTH_C : integer := 13; constant DATA_WIDTH_C : integer := 64; constant BLOCK_ROW_C : integer := 32; constant BLOCK_COL_EXP_C : integer := 4; constant BLOCK_COL_C : integer := 2**BLOCK_COL_EXP_C; constant BLOCK_DATA_WIDTH_C : integer := DATA_WIDTH_C/BLOCK_ROW_C; signal WEA_S : std_logic_vector(0 downto 0); signal WEB_S : std_logic_vector(0 downto 0); signal selecta_s : std_logic_vector (BLOCK_COL_EXP_C-1 downto 0); signal selectb_s : std_logic_vector (BLOCK_COL_EXP_C-1 downto 0); type ram_data_bus is array (BLOCK_COL_C-1 downto 0) of std_logic_vector(DATA_WIDTH_C-1 downto 0); signal wba_dat_a : ram_data_bus; signal wbb_dat_a : ram_data_bus; signal wba_cyc_v_s : std_logic_vector(BLOCK_COL_C-1 downto 0); signal wbb_cyc_v_s : std_logic_vector(BLOCK_COL_C-1 downto 0); -- Wishbone Slave in signal wba_adr_s : std_logic_vector(32-1 downto 0); signal wba_dat_i_s : std_logic_vector(64-1 downto 0); signal wba_we_s : std_logic; signal wba_stb_s : std_logic; signal wba_cyc_s : std_logic; signal wba_dat_o_s : std_logic_vector(64-1 downto 0); signal wba_ack_s : std_logic; signal wbb_adr_s : std_logic_vector(32-1 downto 0); signal wbb_dat_i_s : std_logic_vector(64-1 downto 0); signal wbb_we_s : std_logic; signal wbb_stb_s : std_logic; signal wbb_cyc_s : std_logic; signal wbb_dat_o_s : std_logic_vector(64-1 downto 0); signal wbb_ack_s : std_logic; begin --to improve the fanout input_delay: process (clk_i, rst_i) begin if (rst_i ='1') then wba_adr_s <= (others => '0'); wba_dat_i_s <= (others => '0'); wba_we_s <= '0'; wba_stb_s <= '0'; wba_cyc_s <= '0'; wbb_adr_s <= (others => '0'); wbb_dat_i_s <= (others => '0'); wbb_we_s <= '0'; wbb_stb_s <= '0'; wbb_cyc_s <= '0'; elsif (clk_i'event and clk_i = '1') then wba_adr_s <= wba_adr_i; wba_dat_i_s <= wba_dat_i; wba_we_s <= wba_we_i and wba_stb_i; wba_stb_s <= wba_stb_i; wba_cyc_s <= wba_cyc_i; wbb_adr_s <= wbb_adr_i; wbb_dat_i_s <= wbb_dat_i; wbb_we_s <= wbb_we_i and wbb_stb_i; wbb_stb_s <= wbb_stb_i; wbb_cyc_s <= wbb_cyc_i; end if; end process input_delay; bram: process (clk_i, rst_i) begin if (rst_i ='1') then wba_ack_s <= '0'; wbb_ack_s <= '0'; elsif (clk_i'event and clk_i = '1') then if (wba_stb_s = '1' and wba_cyc_s = '1') then wba_ack_s <= '1'; else wba_ack_s <= '0'; end if; if (wbb_stb_s = '1' and wbb_cyc_s = '1') then wbb_ack_s <= '1'; else wbb_ack_s <= '0'; end if; end if; end process bram; process(clk_i) begin if (clk_i'event and clk_i = '1') then selecta_s <= wba_adr_s(BLOCK_ADDR_WIDTH_C+BLOCK_COL_EXP_C-1 downto BLOCK_ADDR_WIDTH_C); selectb_s <= wbb_adr_s(BLOCK_ADDR_WIDTH_C+BLOCK_COL_EXP_C-1 downto BLOCK_ADDR_WIDTH_C); end if; end process; WEA_S <= (others => '1') when wba_we_s = '1' else (others => '0'); WEB_S <= (others => '1') when wbb_we_s = '1' else (others => '0'); output_delay_p:process(clk_i) begin if (rst_i ='1') then wba_dat_o_s <= (others => '0'); wbb_dat_o_s <= (others => '0'); wba_ack_o <= '0'; wbb_ack_o <= '0'; elsif (clk_i'event and clk_i = '1') then wba_dat_o_s <= wba_dat_a(conv_integer(selecta_s)); wbb_dat_o_s <= wbb_dat_a(conv_integer(selectb_s)); wba_ack_o <= wba_ack_s; wbb_ack_o <= wbb_ack_s; end if; end process; wba_dat_o <= wba_dat_o_s; wbb_dat_o <= wbb_dat_o_s; -- BRAM_TDP_MACRO: True Dual Port RAM -- Kintex-7 -- Xilinx HDL Language Template, version 2016.2 -- Note - This Unimacro model assumes the port directions to be "downto". -- Simulation of this model with "to" in the port directions could lead to erroneous results. -------------------------------------------------------------------------- -- DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width -- -- ===============|===========|===========|===============|=============-- -- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit -- -- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit -- -- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit -- -- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit -- -- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit -- -- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit -- -- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit -- -- 2 | "36Kb" | 16384 | 14-bit | 1-bit -- -- 2 | "18Kb" | 8192 | 13-bit | 1-bit -- -- 1 | "36Kb" | 32768 | 15-bit | 1-bit -- -- 1 | "18Kb" | 16384 | 14-bit | 1-bit -- -------------------------------------------------------------------------- gen_bram_col:for j in 0 to BLOCK_COL_C-1 generate wba_cyc_v_s(j) <= '1' when wba_adr_s(BLOCK_ADDR_WIDTH_C+BLOCK_COL_EXP_C-1 downto BLOCK_ADDR_WIDTH_C) = std_logic_vector(to_unsigned(j,BLOCK_COL_EXP_C)) else '0'; wbb_cyc_v_s(j) <= '1' when wbb_adr_s(BLOCK_ADDR_WIDTH_C+BLOCK_COL_EXP_C-1 downto BLOCK_ADDR_WIDTH_C) = std_logic_vector(to_unsigned(j,BLOCK_COL_EXP_C)) else '0'; gen_bram_row:for i in 0 to BLOCK_ROW_C-1 generate BRAM_TDP_MACRO_inst : BRAM_TDP_MACRO generic map ( BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb" DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6" DOA_REG => 0, -- Optional port A output register (0 or 1) DOB_REG => 0, -- Optional port B output register (0 or 1) INIT_A => X"000000000", -- Initial values on A output port INIT_B => X"000000000", -- Initial values on B output port INIT_FILE => "NONE", READ_WIDTH_A => BLOCK_DATA_WIDTH_C, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") READ_WIDTH_B => BLOCK_DATA_WIDTH_C, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY", -- "GENERATE_X_ONLY" or "NONE" SRVAL_A => X"000000000", -- Set/Reset value for A port output SRVAL_B => X"000000000", -- Set/Reset value for B port output WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE" WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE" WRITE_WIDTH_A => BLOCK_DATA_WIDTH_C, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") WRITE_WIDTH_B => BLOCK_DATA_WIDTH_C, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb") -- The following INIT_xx declarations specify the initial contents of the RAM INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INIT_xx are valid when configured as 36Kb INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INITP_xx are for the parity bits INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", -- The next set of INIT_xx are valid when configured as 36Kb INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000") port map ( DOA => wba_dat_a(j)(BLOCK_DATA_WIDTH_C-1+BLOCK_DATA_WIDTH_C*i downto 0+BLOCK_DATA_WIDTH_C*i), -- Output port-A data, width defined by READ_WIDTH_A parameter DOB => wbb_dat_a(j)(BLOCK_DATA_WIDTH_C-1+BLOCK_DATA_WIDTH_C*i downto 0+BLOCK_DATA_WIDTH_C*i), -- Output port-B data, width defined by READ_WIDTH_B parameter ADDRA => wba_adr_s(BLOCK_ADDR_WIDTH_C-1 downto 0), -- Input port-A address, width defined by Port A depth ADDRB => wbb_adr_s(BLOCK_ADDR_WIDTH_C-1 downto 0), -- Input port-B address, width defined by Port B depth CLKA => clk_i, -- 1-bit input port-A clock CLKB => clk_i, -- 1-bit input port-B clock DIA => wba_dat_i_s(BLOCK_DATA_WIDTH_C-1+BLOCK_DATA_WIDTH_C*i downto 0+BLOCK_DATA_WIDTH_C*i), -- Input port-A data, width defined by WRITE_WIDTH_A parameter DIB => wbb_dat_i_s(BLOCK_DATA_WIDTH_C-1+BLOCK_DATA_WIDTH_C*i downto 0+BLOCK_DATA_WIDTH_C*i), -- Input port-B data, width defined by WRITE_WIDTH_B parameter ENA => wba_cyc_v_s(j), -- 1-bit input port-A enable ENB => wbb_cyc_v_s(j), -- 1-bit input port-B enable REGCEA => wba_stb_s, -- 1-bit input port-A output register enable REGCEB => wbb_stb_s, -- 1-bit input port-B output register enable RSTA => rst_i, -- 1-bit input port-A reset RSTB => rst_i, -- 1-bit input port-B reset WEA => WEA_S, -- Input port-A write enable, width defined by Port A depth WEB => WEB_S -- Input port-B write enable, width defined by Port B depth ); end generate; end generate; -- End of BRAM_TDP_MACRO_inst instantiation end Behavioral;
gpl-3.0
9dd47e44bb34b06ed5d179de7dd119ce
0.675575
4.766296
false
false
false
false
jeremiah-c-leary/vhdl-style-guide
vsg/tests/port_map/rule_004_test_input.fixed_same_line.vhd
1
1,034
architecture ARCH of ENTITY1 is begin U_INST1 : INST1 generic map ( G_GEN_1 => 3, G_GEN_2 => 4, G_GEN_3 => 5 ) port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3) ; -- Violations below U_INST1 : INST1 port map ( PORT_1 => w_port_1, PORT_2 => w_port_2, PORT_3 => w_port_3); U_INST1 : INST1 port map ( PORT_1 => w_port_1)-- Comment ; U_INST1 : INST1 port map ( PORT_1 => w_port_1)-- Comment ; U_INST1 : INST1 port map ( PORT_1 => w_port_1) -- Comment ; U_INST1 : INST1 port map ( PORT_1 => w_port_1) -- Comment ; U_INST1 : INST1 port map ( PORT_1 => w_port_1) -- Comment ;-- Comment2 U_INST1 : INST1 port map ( PORT_1 => w_port_1) -- Comment ;-- Comment2 U_INST1 : INST1 port map ( PORT_1 => w_port_1) -- Comment ; -- Comment2 U_INST1 : INST1 port map ( PORT_1 => w_port_1) -- Comment ; -- Comment2 end architecture ARCH;
gpl-3.0
f4a5da15a821ce68f01d27d9632f2ccb
0.499033
2.794595
false
false
false
false